{"commit":"cec833cb99cc80dd9a9213574ee4d65e8f3acaac","subject":"fix identation [skip ci]","message":"fix identation [skip ci]\n","repos":"jeefo\/yapb,jeefo\/yapb","old_file":"version_script.lds","new_file":"version_script.lds","new_contents":"YAPB_ABI_1.0 {\n   global: \n      Meta_*;\n      GiveFnptrsToDll;\n      GetBotAPI;\n      GetEntityAPI;\n   local: \n      *;\n};","old_contents":"YAPB_ABI_1.0 {\n\tglobal: \n\t\tMeta_*;\n      GiveFnptrsToDll;\n      GetBotAPI;\n      GetEntityAPI;\n\tlocal: \n\t\t*;\n};","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"41e335c2b5471a3ab96e8e769d22f45a1cbd3390","subject":"fix boot stack size","message":"fix boot stack size\n","repos":"bradylee\/nautilus_fs,yhx189\/nautilus,yhx189\/nautilus,haiyang1992\/NautilusVirtio,bradylee\/nautilus_fs,bradylee\/nautilus_fs,haiyang1992\/NautilusVirtio,yhx189\/nautilus,haiyang1992\/NautilusVirtio","old_file":"nautilus.ld","new_file":"nautilus.ld","new_contents":"ENTRY(nautilus_entry)\n\nVIRT_BASE = 0Xffffffff80000000;\n\nSECTIONS\n{\n    . = 0x100000;\n\n    .boot :\n    {\n        *(.mbhdr)\n        _loadStart = .;\n        *(.boot)\n        . = ALIGN(4096);\n        pml4 = .;\n        . += 0x1000;\n        pdpt = .;\n        . += 0x1000;\n        pd = .;\n        . += 0x1000;\n        pt = .;\n        . += 0x1000;\n        boot_stack = .;\n        . += 0x8000;\n    }\n\n    . += VIRT_BASE;\n\n    .text ALIGN(0x1000) : AT(ADDR(.text) - VIRT_BASE)\n    {\n        *(.text)\n        *(.gnu.linkonce.t*)\n    }\n    \n    .data ALIGN(0x1000) : AT(ADDR(.data) - VIRT_BASE)\n    {\n        *(.data)\n        *(.gnu.linkonce.d*)\n    }\n    \n    .rodata ALIGN(0x1000) : AT(ADDR(.rodata) - VIRT_BASE)\n    {\n        *(.rodata*)\n        *(.gnu.linkonce.r*)\n    }\n    \n    _loadEnd = . - VIRT_BASE;\n    \n    .bss ALIGN(0x1000) : AT(ADDR(.bss) - VIRT_BASE)\n    {\n        *(COMMON)\n        *(.bss)\n        *(.gnu.linkonce.b*)\n    }\n    \n    _bssEnd = . - VIRT_BASE;\n    \n    \/DISCARD\/ :\n    {\n        *(.comment)\n        *(.eh_frame)\n    }\n}\n\n","old_contents":"ENTRY(nautilus_entry)\n\nVIRT_BASE = 0Xffffffff80000000;\n\nSECTIONS\n{\n    . = 0x100000;\n\n    .boot :\n    {\n        *(.mbhdr)\n        _loadStart = .;\n        *(.boot)\n        . = ALIGN(4096);\n        pml4 = .;\n        . += 0x1000;\n        pdpt = .;\n        . += 0x1000;\n        pd = .;\n        . += 0x1000;\n        pt = .;\n        . += 0x1000;\n        . += 0x8000;\n        boot_stack = .;\n    }\n\n    . += VIRT_BASE;\n\n    .text ALIGN(0x1000) : AT(ADDR(.text) - VIRT_BASE)\n    {\n        *(.text)\n        *(.gnu.linkonce.t*)\n    }\n    \n    .data ALIGN(0x1000) : AT(ADDR(.data) - VIRT_BASE)\n    {\n        *(.data)\n        *(.gnu.linkonce.d*)\n    }\n    \n    .rodata ALIGN(0x1000) : AT(ADDR(.rodata) - VIRT_BASE)\n    {\n        *(.rodata*)\n        *(.gnu.linkonce.r*)\n    }\n    \n    _loadEnd = . - VIRT_BASE;\n    \n    .bss ALIGN(0x1000) : AT(ADDR(.bss) - VIRT_BASE)\n    {\n        *(COMMON)\n        *(.bss)\n        *(.gnu.linkonce.b*)\n    }\n    \n    _bssEnd = . - VIRT_BASE;\n    \n    \/DISCARD\/ :\n    {\n        *(.comment)\n        *(.eh_frame)\n    }\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5c189beb42fedfb5c63c979fa6c51c87d090b1bb","subject":"Correct the .bss end setting.","message":"Correct the .bss end setting.\n","repos":"FreeRTOS\/FreeRTOS-Kernel,FreeRTOS\/FreeRTOS-Kernel","old_file":"Demo\/ARM7_LPC2368_Eclipse\/RTOSDemo\/lpc2368.ld","new_file":"Demo\/ARM7_LPC2368_Eclipse\/RTOSDemo\/lpc2368.ld","new_contents":"MEMORY \r\n{\r\n\tflash\t: ORIGIN = 0x00000000, LENGTH = 500K\r\n\tram\t: ORIGIN = 0x40000000, LENGTH = 32K\r\n\tusbram   : ORIGIN = 0x7FD00000, LENGTH = 8K\r\n\tethram   : ORIGIN = 0x7FE00000, LENGTH = 16K\r\n}\r\n\r\n__stack_end__ = 0x40000000 + 32K - 4;\r\n\r\nSECTIONS \r\n{\r\n\t. = 0;\r\n\tstartup : { *(.startup)} >flash\r\n\r\n\tprog : \r\n\t{\r\n\t\t*(.text)\r\n\t\t*(.rodata)\r\n\t\t*(.rodata*)\r\n\t\t*(.glue_7)\r\n\t\t*(.glue_7t)\r\n\t} >flash\r\n\r\n\t__end_of_text__ = .;\r\n\r\n\t.data : \r\n\t{\r\n\t\t__data_beg__ = .;\r\n\t\t__data_beg_src__ = __end_of_text__;\r\n\t\t*(.data)\r\n\t\t__data_end__ = .;\r\n\t} >ram AT>flash\r\n\r\n\t.bss : \r\n\t{\r\n\t\t__bss_beg__ = .;\r\n\t\t*(.bss)\r\n\t} >ram\r\n\r\n\t\/* Align here to ensure that the .bss section occupies space up to\r\n\t_end.  Align after .bss to ensure correct alignment even if the\r\n\t.bss section disappears because there are no input sections.  *\/\r\n\t. = ALIGN(32 \/ 8);\r\n\t_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r\n\r\n\t.usbram (NOLOAD):\r\n\t{\r\n\t__usbram_beg__ = .;\r\n\t*(.dmaram)\r\n\t\t__usbram_end__ = .;\r\n\t} >usbram\r\n\r\n\t.ethram (NOLOAD):\r\n\t{\r\n\t__ethram_beg__ = .;\r\n\t*(.ethram)\r\n\t\t__ethram_end__ = .;\r\n\t} >ethram\r\n\r\n\r\n}\r\n\t. = ALIGN(32 \/ 8);\r\n\t_end = .;\r\n\t\r\n\tPROVIDE (end = .);\r\n\r\n\r\n","old_contents":"MEMORY \r\n{\r\n\tflash\t: ORIGIN = 0x00000000, LENGTH = 500K\r\n\tram\t: ORIGIN = 0x40000000, LENGTH = 32K\r\n\tusbram   : ORIGIN = 0x7FD00000, LENGTH = 8K\r\n\tethram   : ORIGIN = 0x7FE00000, LENGTH = 16K\r\n}\r\n\r\n__stack_end__ = 0x40000000 + 32K - 4;\r\n\r\nSECTIONS \r\n{\r\n\t. = 0;\r\n\tstartup : { *(.startup)} >flash\r\n\r\n\tprog : \r\n\t{\r\n\t\t*(.text)\r\n\t\t*(.rodata)\r\n\t\t*(.rodata*)\r\n\t\t*(.glue_7)\r\n\t\t*(.glue_7t)\r\n\t} >flash\r\n\r\n\t__end_of_text__ = .;\r\n\r\n\t.data : \r\n\t{\r\n\t\t__data_beg__ = .;\r\n\t\t__data_beg_src__ = __end_of_text__;\r\n\t\t*(.data)\r\n\t\t__data_end__ = .;\r\n\t} >ram AT>flash\r\n\r\n\t.bss : \r\n\t{\r\n\t\t__bss_beg__ = .;\r\n\t\t*(.bss)\r\n\t} >ram\r\n\r\n\t\/* Align here to ensure that the .bss section occupies space up to\r\n\t_end.  Align after .bss to ensure correct alignment even if the\r\n\t.bss section disappears because there are no input sections.  *\/\r\n\t. = ALIGN(32 \/ 8);\r\n\r\n\t.usbram (NOLOAD):\r\n\t{\r\n\t__usbram_beg__ = .;\r\n\t*(.dmaram)\r\n\t\t__usbram_end__ = .;\r\n\t} >usbram\r\n\r\n\t.ethram (NOLOAD):\r\n\t{\r\n\t__ethram_beg__ = .;\r\n\t*(.ethram)\r\n\t\t__ethram_end__ = .;\r\n\t} >ethram\r\n\r\n\r\n}\r\n\t. = ALIGN(32 \/ 8);\r\n\t_end = .;\r\n\t_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r\n\tPROVIDE (end = .);\r\n\r\n\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f1ec9ea78082d3a136fe36ca3996df7b870751a5","subject":"add comments to z80\/sound driver linker script","message":"add comments to z80\/sound driver linker script\n","repos":"freem\/freemlib-neogeo,freem\/freemlib-neogeo","old_file":"src_z80\/sounddrv.ld","new_file":"src_z80\/sounddrv.ld","new_contents":"\/* vlink linker script for freemlib sound driver *\/\r\n\r\nMEMORY\r\n{\r\n\tstart:   ORIGIN = 0x0000, LENGTH = 0x0004 \/* 0x0000: entry point *\/\r\n\tdelay1:  ORIGIN = 0x0008, LENGTH = 0x0003 \/* 0x0008: port write delay (addr) *\/\r\n\tdelay2:  ORIGIN = 0x0010, LENGTH = 0x0003 \/* 0x0010: port write delay (data) *\/\r\n\twrite45: ORIGIN = 0x0018, LENGTH = 0x0003 \/* 0x0018: shortcut to write_45 *\/\r\n\twrite67: ORIGIN = 0x0020, LENGTH = 0x0003 \/* 0x0020: shortcut to write_67 *\/\r\n\tymwait:  ORIGIN = 0x0028, LENGTH = 0x0006 \/* 0x0028: YM2610 busy wait *\/\r\n\tIRQ:     ORIGIN = 0x0038, LENGTH = 0x0004 \/* 0x0038: IRQ trampoline *\/\r\n\tidstr:   ORIGIN = 0x0040, LENGTH = 0x0020 \/* 0x0040: driver identification *\/\r\n\tNMI:     ORIGIN = 0x0066, LENGTH = 0x002B \/* 0x0066: NMI routine *\/\r\n\trom:     ORIGIN = 0x00A0, LENGTH = 0xF760 \/* 0x00A0: start of the rest of ROM *\/\r\n\tram:     ORIGIN = 0xF800, LENGTH = 0x0800 \/* RAM at 0xF800-0xFFFF *\/\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.start : { *(start) } > start\r\n\t.delay1 : { *(delay1) } > delay1\r\n\t.delay2 : { *(delay2) } > delay2\r\n\t.write45 : { *(write45) } > write45\r\n\t.write67 : { *(write67) } > write67\r\n\t.ymwait : { *(ymwait) } > ymwait\r\n\t.IRQ : { *(IRQ) } > IRQ\r\n\t.idstr : { *(idstr) } > idstr\r\n\t.NMI : { *(NMI) } > NMI\r\n\t.code : { *(code) } > rom\r\n\t.bss (NOLOAD) : { *(bss) } > ram\r\n}\r\n","old_contents":"\/* vlink linker script for freemlib sound driver *\/\r\n\r\nMEMORY\r\n{\r\n\tstart:   ORIGIN = 0x0000, LENGTH = 0x0038\r\n\tdelay1:  ORIGIN = 0x0008, LENGTH = 0x0003\r\n\tdelay2:  ORIGIN = 0x0010, LENGTH = 0x0003\r\n\twrite45: ORIGIN = 0x0018, LENGTH = 0x0003\r\n\twrite67: ORIGIN = 0x0020, LENGTH = 0x0003\r\n\tymwait:  ORIGIN = 0x0028, LENGTH = 0x0006\r\n\tIRQ:     ORIGIN = 0x0038, LENGTH = 0x0024\r\n\tidstr:   ORIGIN = 0x0040, LENGTH = 0x0020\r\n\tNMI:     ORIGIN = 0x0066, LENGTH = 0x002B\r\n\trom:     ORIGIN = 0x00A0, LENGTH = 0xF760\r\n\tram:     ORIGIN = 0xF800, LENGTH = 0x0800\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.start : { *(start) } > start\r\n\t.delay1 : { *(delay1) } > delay1\r\n\t.delay2 : { *(delay2) } > delay2\r\n\t.write45 : { *(write45) } > write45\r\n\t.write67 : { *(write67) } > write67\r\n\t.ymwait : { *(ymwait) } > ymwait\r\n\t.IRQ : { *(IRQ) } > IRQ\r\n\t.idstr : { *(idstr) } > idstr\r\n\t.NMI : { *(NMI) } > NMI\r\n\t.code : { *(code) } > rom\r\n\t.bss (NOLOAD) : { *(bss) } > ram\r\n}\r\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"5e002e8d7d1d98e662e03c38473df94765fb5c36","subject":"riscv: linker: align end of ROM area to a \"page\" boundary for QEMU","message":"riscv: linker: align end of ROM area to a \"page\" boundary for QEMU\n\nQEMU does its dynamic instruction translation in 4096-byte-sized chunks.\nTherefore it doesn't vet PMP access for each instruction prefetch but\nfor the whole \"page\" at once. If the end of the ROM area lands in the\nmiddle of such a page with a corresponding PMP entry then any instruction\naccess within that page will fault even if it is located in the PMP\nmapped portion.\n\nTo work around this QEMU peculiarity, we simply align the end of the ROM\narea to a page boundary.\n\nSigned-off-by: Nicolas Pitre <76342682d5afc62854e1102d9578521fe1ed6813@baylibre.com>\n","repos":"galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"include\/zephyr\/arch\/riscv\/common\/linker.ld","new_file":"include\/zephyr\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <zephyr\/devicetree.h>\n\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE);\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    LINKER_DT_REGIONS()\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakenly contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n#ifdef CONFIG_QEMU_TARGET\n\t\t\/*\n\t\t * QEMU doesn't vet each instruction fetch individually.\n\t\t * Instead, it grabs a whole page and perform dynamic\n\t\t * transation on it in a batch. It therefore validates\n\t\t * PMP permissions using page-sized and -aligned chunks.\n\t\t *\/\n\t\t. = ALIGN(0x1000);\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_BASE;\n\t_image_ram_start = .;\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakenly contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <zephyr\/devicetree.h>\n\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE);\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    LINKER_DT_REGIONS()\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakenly contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_BASE;\n\t_image_ram_start = .;\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakenly contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"513194953aad4b40c31d1fe1c84b1318d9da5780","subject":"Increased maximum ROM size (up to almost 4GB)","message":"Increased maximum ROM size (up to almost 4GB)\n","repos":"andwn\/SGDK,Stephane-D\/SGDK,andwn\/SGDK,andwn\/SGDK,Stephane-D\/SGDK,Stephane-D\/SGDK","old_file":"md.ld","new_file":"md.ld","new_contents":"OUTPUT_ARCH(m68k)\r\nSEARCH_DIR(.)\r\n\/*GROUP(-lbcc -lc -lgcc)*\/\r\n__DYNAMIC  =  0;\r\n\r\n\/*\r\n * Setup the memory map of the SEGA Genesis.\r\n * stack grows down from high memory.\r\n *\r\n * The memory map look like this:\r\n * +--------------------+ <- low memory\r\n * | .text              |\r\n * |        _etext      |\r\n * |        ctor list   | the ctor and dtor lists are for\r\n * |        dtor list   | C++ support\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * +--------------------+ <- 0xFFFF0000\r\n * | .data              | initialized data goes here\r\n * |        _data       |\r\n * |        _edata      |\r\n * +--------------------+\r\n * | .bss               |\r\n * |        _bstart     | start of bss, cleared by crt0\r\n * |        _bend       | start of heap, used by sbrk()\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * |        __stack     | top of stack\r\n * +--------------------+ <- 0x00000000\r\n *\/\r\nMEMORY\r\n{\r\n\trom (rx) : ORIGIN = 0x00000000, LENGTH = 0x10000000\r\n\tram : ORIGIN = 0xFFFF0000, LENGTH = 0x00010000\r\n}\r\n\r\n\/*\r\n * allocate the stack to be at the top of memory, since the stack\r\n * grows down\r\n *\/\r\n\r\nPROVIDE (__stack = 0x00000000);\r\n\r\n\r\nSECTIONS\r\n{\r\n  .text 0x00000000:\r\n  {\r\n    KEEP(*(.text.keepboot)) *(.text.*) *(.text)\r\n    . = ALIGN(0x4);\r\n     __CTOR_LIST__ = .;\r\n    LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\r\n    *(.ctors)\r\n    LONG(0)\r\n    __CTOR_END__ = .;\r\n    __DTOR_LIST__ = .;\r\n    LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\r\n    *(.dtors)\r\n     LONG(0)\r\n    __DTOR_END__ = .;\r\n\r\n    *(.rodata .rodata.*)\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n\r\n    . = ALIGN(0x4);\r\n    __INIT_SECTION__ = . ;\r\n    *(.init)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    __FINI_SECTION__ = . ;\r\n    *(.fini)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    _etext = .;\r\n    *(.lit)\r\n\r\n    *(.rodata_bin)\r\n    *(.rodata_binf)\r\n  } > rom\r\n  _stext = SIZEOF (.text);\r\n\r\n  .data 0xFFFF0000 :\r\n  AT ( ADDR (.text) + SIZEOF (.text) )\r\n  {\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.*)\r\n    _edata = .;\r\n  } > ram\r\n  _sdata = SIZEOF (.data);\r\n\r\n  .bss 0xFFFF0000 + SIZEOF (.data) :\r\n  {\r\n    _start = . ;\r\n    *(.shbss)\r\n    *(.bss .bss.*)\r\n    *(COMMON)\r\n    _bend = . ;\r\n  } > ram\r\n\r\n  .stab 0 (NOLOAD) :\r\n  {\r\n    *(.stab)\r\n  }\r\n\r\n  .stabstr 0 (NOLOAD) :\r\n  {\r\n    *(.stabstr)\r\n  }\r\n\r\n  .eh_frame 0 (NOLOAD) :\r\n  {\r\n    *(.eh_frame)\r\n  }\r\n}\r\n","old_contents":"OUTPUT_ARCH(m68k)\r\nSEARCH_DIR(.)\r\n\/*GROUP(-lbcc -lc -lgcc)*\/\r\n__DYNAMIC  =  0;\r\n\r\n\/*\r\n * Setup the memory map of the SEGA Genesis.\r\n * stack grows down from high memory.\r\n *\r\n * The memory map look like this:\r\n * +--------------------+ <- low memory\r\n * | .text              |\r\n * |        _etext      |\r\n * |        ctor list   | the ctor and dtor lists are for\r\n * |        dtor list   | C++ support\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * +--------------------+ <- 0x00FF0000\r\n * | .data              | initialized data goes here\r\n * |        _data       |\r\n * |        _edata      |\r\n * +--------------------+\r\n * | .bss               |\r\n * |        _bstart     | start of bss, cleared by crt0\r\n * |        _bend       | start of heap, used by sbrk()\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * |        __stack     | top of stack\r\n * +--------------------+ <- 0x01000000\r\n *\/\r\nMEMORY\r\n{\r\n\trom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00C00000\r\n\tram : ORIGIN = 0x00FF0000, LENGTH = 0x00010000\r\n}\r\n\r\n\/*\r\n * allocate the stack to be at the top of memory, since the stack\r\n * grows down\r\n *\/\r\n\r\nPROVIDE (__stack = 0x01000000);\r\n\r\n\r\nSECTIONS\r\n{\r\n  .text 0x00000000:\r\n  {\r\n    KEEP(*(.text.keepboot)) *(.text.*) *(.text)\r\n    . = ALIGN(0x4);\r\n     __CTOR_LIST__ = .;\r\n    LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\r\n    *(.ctors)\r\n    LONG(0)\r\n    __CTOR_END__ = .;\r\n    __DTOR_LIST__ = .;\r\n    LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\r\n    *(.dtors)\r\n     LONG(0)\r\n    __DTOR_END__ = .;\r\n\r\n    *(.rodata .rodata.*)\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n\r\n    . = ALIGN(0x4);\r\n    __INIT_SECTION__ = . ;\r\n    *(.init)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    __FINI_SECTION__ = . ;\r\n    *(.fini)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    _etext = .;\r\n    *(.lit)\r\n\r\n    *(.rodata_bin)\r\n    *(.rodata_binf)\r\n  } > rom\r\n  _stext = SIZEOF (.text);\r\n\r\n  .data 0xFF0000 :\r\n  AT ( ADDR (.text) + SIZEOF (.text) )\r\n  {\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.*)\r\n    _edata = .;\r\n  } > ram\r\n  _sdata = SIZEOF (.data);\r\n\r\n  .bss 0xFF0000 + SIZEOF (.data) :\r\n  {\r\n    _start = . ;\r\n    *(.shbss)\r\n    *(.bss .bss.*)\r\n    *(COMMON)\r\n    _bend = . ;\r\n  } > ram\r\n\r\n  .stab 0 (NOLOAD) :\r\n  {\r\n    *(.stab)\r\n  }\r\n\r\n  .stabstr 0 (NOLOAD) :\r\n  {\r\n    *(.stabstr)\r\n  }\r\n\r\n  .eh_frame 0 (NOLOAD) :\r\n  {\r\n    *(.eh_frame)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"95c6d1859c1e88ecd8b3187aa0dc7c176c3aff88","subject":"cpu\/esp32: fix for crashes of tests\/pkg_spiffs","message":"cpu\/esp32: fix for crashes of tests\/pkg_spiffs\n\nESP32 nodes can crash during SPI Flash write operations if required parts of the code are not in the IRAM but in the cached SPI Flash memory, which is disabled during the SPI Flash write operations. Therefore, the code of the SPIFFS package and the VFS module are now stored in the IRAM.","repos":"mtausig\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,toonst\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,OlegHahm\/RIOT,authmillenon\/RIOT,miri64\/RIOT,yogo1212\/RIOT,aeneby\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,yogo1212\/RIOT,ant9000\/RIOT,basilfx\/RIOT,toonst\/RIOT,mtausig\/RIOT,mtausig\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,kYc0o\/RIOT,x3ro\/RIOT,mtausig\/RIOT,smlng\/RIOT,kYc0o\/RIOT,authmillenon\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,yogo1212\/RIOT,aeneby\/RIOT,OTAkeys\/RIOT,OTAkeys\/RIOT,smlng\/RIOT,kYc0o\/RIOT,basilfx\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,toonst\/RIOT,x3ro\/RIOT,smlng\/RIOT,josephnoir\/RIOT,ant9000\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,basilfx\/RIOT,josephnoir\/RIOT,yogo1212\/RIOT,x3ro\/RIOT,x3ro\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,toonst\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,aeneby\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,aeneby\/RIOT,miri64\/RIOT,ant9000\/RIOT,josephnoir\/RIOT,authmillenon\/RIOT,miri64\/RIOT,jasonatran\/RIOT,josephnoir\/RIOT,jasonatran\/RIOT,OTAkeys\/RIOT,smlng\/RIOT,mtausig\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,authmillenon\/RIOT,smlng\/RIOT,ant9000\/RIOT,basilfx\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,josephnoir\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,x3ro\/RIOT,toonst\/RIOT","old_file":"cpu\/esp32\/ld\/esp32.common.ld","new_file":"cpu\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of RIOT ports that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    \/* *spiffs_fs.a:*(.literal .text .literal.* .text.*) *\/\n    \/* *spiffs.a:*(.literal .text .literal.* .text.*) *\/\n\n    \/* part of RIOT ports that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"2e783ccd89d0da81e84d0ea65855fb2a84f654dd","subject":"Amend memory layout to match tock 1.5 release","message":"Amend memory layout to match tock 1.5 release\n","repos":"tock\/libtock-rs","old_file":"boards\/layout_nrf52.ld","new_file":"boards\/layout_nrf52.ld","new_contents":"\/* Layout for the nRF52-DK, used by the examples in this repository. *\/\n\nMEMORY {\n  \/* The application region is 64 bytes (0x40) *\/\n  FLASH (rx) : ORIGIN = 0x00030040, LENGTH = 0x0005FFC0\n  SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 62K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 8K;\n\nINCLUDE layout_generic.ld\n","old_contents":"\/* Layout for the nRF52-DK, used by the examples in this repository. *\/\n\nMEMORY {\n  \/* The application region is 64 bytes (0x40) *\/\n  FLASH (rx) : ORIGIN = 0x00030040, LENGTH = 0x0005FFC0\n  SRAM (rwx) : ORIGIN = 0x20002000, LENGTH = 62K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 8K;\n\nINCLUDE layout_generic.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"163104d3224a2520b9e939dc61860adf7338f546","subject":"core\/host: Format linker script","message":"core\/host: Format linker script\n\nThis is a cleanup\/reformat of the linker script.\nThis brings no functional change.\n\nBRANCH=none\nBUG=b:146083406\nTEST=make buildall\n\nChange-Id: I55bef2d9f1a4e3e544b2ef1b4d28825b3a628a44\nSigned-off-by: Craig Hesling <383db090fd8ef907a606ac8a9eccd2962bc489cf@chromium.org>\nReviewed-on: https:\/\/chromium-review.googlesource.com\/c\/chromiumos\/platform\/ec\/+\/1966288\nReviewed-by: Daisuke Nojiri <fd5f93af191bf7e8f73ea71cc3c0f66b41b1dd49@chromium.org>\n","repos":"coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec","old_file":"core\/host\/host_exe.lds","new_file":"core\/host\/host_exe.lds","new_contents":"\/* Copyright 2013 The Chromium OS Authors. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n *\/\nSECTIONS {\n\t.rodata.ec_sections : {\n\t\t\/* Symbols defined here are declared in link_defs.h *\/\n\t\t__irqprio = .;\n\t\t*(.rodata.irqprio)\n\t\t__irqprio_end = .;\n\n\t\t. = ALIGN(8);\n\t\t__cmds = .;\n\t\t*(SORT(.rodata.cmds*))\n\t\t__cmds_end = .;\n\n\t\t. = ALIGN(8);\n\t\t__hcmds = .;\n\t\t*(SORT(.rodata.hcmds*))\n\t\t__hcmds_end = .;\n\n\t\t. = ALIGN(4);\n\t\t__mkbp_evt_srcs = .;\n\t\tKEEP(*(.rodata.evtsrcs))\n\t\t__mkbp_evt_srcs_end = .;\n\n\t\t. = ALIGN(8);\n\t\t__hooks_init = .;\n\t\t*(.rodata.HOOK_INIT)\n\t\t__hooks_init_end = .;\n\n\t\t__hooks_pre_freq_change = .;\n\t\t*(.rodata.HOOK_PRE_FREQ_CHANGE)\n\t\t__hooks_pre_freq_change_end = .;\n\n\t\t__hooks_freq_change = .;\n\t\t*(.rodata.HOOK_FREQ_CHANGE)\n\t\t__hooks_freq_change_end = .;\n\n\t\t__hooks_sysjump = .;\n\t\t*(.rodata.HOOK_SYSJUMP)\n\t\t__hooks_sysjump_end = .;\n\n\t\t__hooks_chipset_pre_init = .;\n\t\t*(.rodata.HOOK_CHIPSET_PRE_INIT)\n\t\t__hooks_chipset_pre_init_end = .;\n\n\t\t__hooks_chipset_startup = .;\n\t\t*(.rodata.HOOK_CHIPSET_STARTUP)\n\t\t__hooks_chipset_startup_end = .;\n\n\t\t__hooks_chipset_resume = .;\n\t\t*(.rodata.HOOK_CHIPSET_RESUME)\n\t\t__hooks_chipset_resume_end = .;\n\n\t\t__hooks_chipset_suspend = .;\n\t\t*(.rodata.HOOK_CHIPSET_SUSPEND)\n\t\t__hooks_chipset_suspend_end = .;\n\n\t\t__hooks_chipset_shutdown = .;\n\t\t*(.rodata.HOOK_CHIPSET_SHUTDOWN)\n\t\t__hooks_chipset_shutdown_end = .;\n\n\t\t__hooks_chipset_reset = .;\n\t\t*(.rodata.HOOK_CHIPSET_RESET)\n\t\t__hooks_chipset_reset_end = .;\n\n\t\t__hooks_ac_change = .;\n\t\t*(.rodata.HOOK_AC_CHANGE)\n\t\t__hooks_ac_change_end = .;\n\n\t\t__hooks_lid_change = .;\n\t\t*(.rodata.HOOK_LID_CHANGE)\n\t\t__hooks_lid_change_end = .;\n\n\t\t__hooks_tablet_mode_change = .;\n\t\tKEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))\n\t\t__hooks_tablet_mode_change_end = .;\n\n\t\t__hooks_base_attached_change = .;\n\t\tKEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))\n\t\t__hooks_base_attached_change_end = .;\n\n\t\t__hooks_pwrbtn_change = .;\n\t\t*(.rodata.HOOK_POWER_BUTTON_CHANGE)\n\t\t__hooks_pwrbtn_change_end = .;\n\n\t\t__hooks_battery_soc_change = .;\n\t\t*(.rodata.HOOK_BATTERY_SOC_CHANGE)\n\t\t__hooks_battery_soc_change_end = .;\n\n\t\t__hooks_tick = .;\n\t\t*(.rodata.HOOK_TICK)\n\t\t__hooks_tick_end = .;\n\n\t\t__hooks_second = .;\n\t\t*(.rodata.HOOK_SECOND)\n\t\t__hooks_second_end = .;\n\n\t\t__hooks_usb_pd_disconnect = .;\n\t\t*(.rodata.HOOK_USB_PD_DISCONNECT)\n\t\t__hooks_usb_pd_disconnect_end = .;\n\n\t\t__hooks_usb_pd_connect = .;\n\t\tKEEP(*(.rodata.HOOK_USB_PD_CONNECT))\n\t\t__hooks_usb_pd_connect_end = .;\n\n\t\t__deferred_funcs = .;\n\t\t*(.rodata.deferred)\n\t\t__deferred_funcs_end = .;\n\n\t\t__test_i2c_xfer = .;\n\t\t*(.rodata.test_i2c.xfer)\n\t\t__test_i2c_xfer_end = .;\n\t}\n}\nINSERT BEFORE .rodata;\n\nSECTIONS {\n\t.bss.ec_sections : {\n\t\t\/* Symbols defined here are declared in link_defs.h *\/\n\t\t. = ALIGN(8);\n\t\t__deferred_until = .;\n\t\t. += (__deferred_funcs_end - __deferred_funcs) * (8 \/ 4);\n\t\t__deferred_until_end = .;\n\t}\n}\nINSERT BEFORE .bss;\n","old_contents":"\/* Copyright 2013 The Chromium OS Authors. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n *\/\nSECTIONS {\n  .rodata.ec_sections : {\n    \/* Symbols defined here are declared in link_defs.h *\/\n    __irqprio = .;\n    *(.rodata.irqprio)\n    __irqprio_end = .;\n\n    . = ALIGN(8);\n    __cmds = .;\n    *(SORT(.rodata.cmds*))\n    __cmds_end = .;\n\n    . = ALIGN(8);\n    __hcmds = .;\n    *(SORT(.rodata.hcmds*))\n    __hcmds_end = .;\n\n    . = ALIGN(4);\n    __mkbp_evt_srcs = .;\n    KEEP(*(.rodata.evtsrcs))\n    __mkbp_evt_srcs_end = .;\n\n    . = ALIGN(8);\n    __hooks_init = .;\n    *(.rodata.HOOK_INIT)\n    __hooks_init_end = .;\n\n    __hooks_pre_freq_change = .;\n    *(.rodata.HOOK_PRE_FREQ_CHANGE)\n    __hooks_pre_freq_change_end = .;\n\n    __hooks_freq_change = .;\n    *(.rodata.HOOK_FREQ_CHANGE)\n    __hooks_freq_change_end = .;\n\n    __hooks_sysjump = .;\n    *(.rodata.HOOK_SYSJUMP)\n    __hooks_sysjump_end = .;\n\n    __hooks_chipset_pre_init = .;\n    *(.rodata.HOOK_CHIPSET_PRE_INIT)\n    __hooks_chipset_pre_init_end = .;\n\n    __hooks_chipset_startup = .;\n    *(.rodata.HOOK_CHIPSET_STARTUP)\n    __hooks_chipset_startup_end = .;\n\n    __hooks_chipset_resume = .;\n    *(.rodata.HOOK_CHIPSET_RESUME)\n    __hooks_chipset_resume_end = .;\n\n    __hooks_chipset_suspend = .;\n    *(.rodata.HOOK_CHIPSET_SUSPEND)\n    __hooks_chipset_suspend_end = .;\n\n    __hooks_chipset_shutdown = .;\n    *(.rodata.HOOK_CHIPSET_SHUTDOWN)\n    __hooks_chipset_shutdown_end = .;\n\n    __hooks_chipset_reset = .;\n    *(.rodata.HOOK_CHIPSET_RESET)\n    __hooks_chipset_reset_end = .;\n\n    __hooks_ac_change = .;\n    *(.rodata.HOOK_AC_CHANGE)\n    __hooks_ac_change_end = .;\n\n    __hooks_lid_change = .;\n    *(.rodata.HOOK_LID_CHANGE)\n    __hooks_lid_change_end = .;\n\n    __hooks_tablet_mode_change = .;\n    KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))\n    __hooks_tablet_mode_change_end = .;\n\n    __hooks_base_attached_change = .;\n    KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))\n    __hooks_base_attached_change_end = .;\n\n    __hooks_pwrbtn_change = .;\n    *(.rodata.HOOK_POWER_BUTTON_CHANGE)\n    __hooks_pwrbtn_change_end = .;\n\n    __hooks_battery_soc_change = .;\n    *(.rodata.HOOK_BATTERY_SOC_CHANGE)\n    __hooks_battery_soc_change_end = .;\n\n    __hooks_tick = .;\n    *(.rodata.HOOK_TICK)\n    __hooks_tick_end = .;\n\n    __hooks_second = .;\n    *(.rodata.HOOK_SECOND)\n    __hooks_second_end = .;\n\n    __hooks_usb_pd_disconnect = .;\n    *(.rodata.HOOK_USB_PD_DISCONNECT)\n    __hooks_usb_pd_disconnect_end = .;\n\n    __hooks_usb_pd_connect = .;\n    KEEP(*(.rodata.HOOK_USB_PD_CONNECT))\n    __hooks_usb_pd_connect_end = .;\n\n    __deferred_funcs = .;\n    *(.rodata.deferred)\n    __deferred_funcs_end = .;\n\n    __test_i2c_xfer = .;\n    *(.rodata.test_i2c.xfer)\n    __test_i2c_xfer_end = .;\n  }\n}\nINSERT BEFORE .rodata;\n\nSECTIONS {\n  .bss.ec_sections : {\n    \/* Symbols defined here are declared in link_defs.h *\/\n    . = ALIGN(8);\n    __deferred_until = .;\n    . += (__deferred_funcs_end - __deferred_funcs) * (8 \/ 4);\n    __deferred_until_end = .;\n  }\n}\nINSERT BEFORE .bss;\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"e31c140ca8e6cc7025ef308375ea52d3d093b02b","subject":"New linkscript including stuff from supplied AArch64 scripts","message":"New linkscript including stuff from supplied AArch64 scripts\n","repos":"switchbrew\/libnx","old_file":"buildscripts\/lib\/switch.ld","new_file":"buildscripts\/lib\/switch.ld","new_contents":"OUTPUT_ARCH(aarch64)\nENTRY(_start)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(5) \/* Read | Execute *\/;\n\trodata PT_LOAD FLAGS(4) \/* Read *\/;\n\tdata   PT_LOAD FLAGS(6) \/* Read | Write *\/;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\tPROVIDE(__start__ = 0x0);\n\t. = __start__;\n\n\t.crt0 :\n\t{\n\t\tKEEP (*(.crt0))\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.init :\n\t{\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.plt :\n\t{\n\t\t*(.plt)\n\t\t*(.iplt)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.text :\n\t{\n\t\t*(.text.unlikely .text.*_unlikely .text.unlikely.*)\n\t\t*(.text.exit .text.exit.*)\n\t\t*(.text.startup .text.startup.*)\n\t\t*(.text.hot .text.hot.*)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.fini :\n\t{\n\t\tKEEP( *(.fini) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t\/* =========== RODATA section =========== *\/\n\t. = ALIGN(0x1000);\n\n\t.rodata :\n\t{\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(8);\n\t} :rodata\n\n\t.eh_frame_hdr     : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } :rodata\n\t.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata\n\t.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata\n\t.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata\n\n\t.interp            : { *(.interp) } :rodata\n\t.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata\n\t.hash              : { *(.hash) } :rodata\n\t.gnu.hash          : { *(.gnu.hash) } :rodata\n\t.gnu.version       : { *(.gnu.version) } :rodata\n\t.gnu.version_d     : { *(.gnu.version_d) } :rodata\n\t.gnu.version_r     : { *(.gnu.version_r) } :rodata\n\t.dynsym            : { *(.dynsym) } :rodata\n\t.dynstr            : { *(.dynstr) } :rodata\n\t.rela.dyn          : { *(.rela.*) } :rodata\n\n\t\/* =========== DATA section =========== *\/\n\t. = ALIGN(0x1000);\n\n\t.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data\n\t.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data\n\t.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data\n\t.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data\n\n\t.tdata ALIGN(8) :\n\t{\n\t\t__tdata_lma = .;\n\t\t*(.tdata .tdata.* .gnu.linkonce.td.*)\n\t\t. = ALIGN(8);\n\t\t__tdata_lma_end = .;\n\t} :data\n\n\t.tbss ALIGN(8) :\n\t{\n\t\t*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)\n\t\t. = ALIGN(8);\n\t} :data\n\n\t.preinit_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\t} 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{"commit":"3d9ee8eeeda0af84eeebc742660ff803da3ee99e","subject":"Fix up GPIO addresses","message":"Fix up GPIO addresses\n","repos":"richo\/zinc,richo\/zinc,richo\/zinc,richo\/zinc,richo\/zinc","old_file":"src\/hal\/lpc17xx\/iomem.ld","new_file":"src\/hal\/lpc17xx\/iomem.ld","new_contents":"PROVIDE(isr_dac          = isr_hardfault);\nPROVIDE(isr_m0app        = isr_hardfault);\nPROVIDE(isr_dma          = isr_hardfault);\nPROVIDE(isr_reserved     = isr_hardfault);\nPROVIDE(isr_flasheeprom  = isr_hardfault);\nPROVIDE(isr_enet         = isr_hardfault);\nPROVIDE(isr_sdio         = isr_hardfault);\nPROVIDE(isr_lcd          = isr_hardfault);\nPROVIDE(isr_usb0         = isr_hardfault);\nPROVIDE(isr_usb1         = isr_hardfault);\nPROVIDE(isr_sctimer_pwm  = isr_hardfault);\nPROVIDE(isr_ritimer      = isr_hardfault);\nPROVIDE(isr_timer_0      = isr_hardfault);\nPROVIDE(isr_timer_1      = isr_hardfault);\nPROVIDE(isr_timer_2      = isr_hardfault);\nPROVIDE(isr_timer_3      = isr_hardfault);\nPROVIDE(isr_mcpwm        = isr_hardfault);\nPROVIDE(isr_adc0         = isr_hardfault);\nPROVIDE(isr_i2c_0        = isr_hardfault);\nPROVIDE(isr_i2c_1        = isr_hardfault);\nPROVIDE(isr_spi          = isr_hardfault);\nPROVIDE(isr_adc1         = isr_hardfault);\nPROVIDE(isr_ssp_0        = isr_hardfault);\nPROVIDE(isr_ssp_1        = isr_hardfault);\nPROVIDE(isr_uart_0       = isr_hardfault);\nPROVIDE(isr_uart_1       = isr_hardfault);\nPROVIDE(isr_uart_2       = isr_hardfault);\nPROVIDE(isr_uart_3       = isr_hardfault);\nPROVIDE(isr_i2s0         = isr_hardfault);\nPROVIDE(isr_i2s1         = isr_hardfault);\nPROVIDE(isr_spifi        = isr_hardfault);\nPROVIDE(isr_sgpio        = isr_hardfault);\nPROVIDE(isr_pin_int0     = isr_hardfault);\nPROVIDE(isr_pin_int1     = isr_hardfault);\nPROVIDE(isr_pin_int2     = isr_hardfault);\nPROVIDE(isr_pin_int3     = isr_hardfault);\nPROVIDE(isr_pin_int4     = isr_hardfault);\nPROVIDE(isr_pin_int5     = isr_hardfault);\nPROVIDE(isr_pin_int6     = isr_hardfault);\nPROVIDE(isr_pin_int7     = isr_hardfault);\nPROVIDE(isr_gint0        = isr_hardfault);\nPROVIDE(isr_gint1        = isr_hardfault);\nPROVIDE(isr_eventrouter  = isr_hardfault);\nPROVIDE(isr_c_can1       = isr_hardfault);\nPROVIDE(isr_reserved     = isr_hardfault);\nPROVIDE(isr_adchs        = isr_hardfault);\nPROVIDE(isr_atimer       = isr_hardfault);\nPROVIDE(isr_rtc          = isr_hardfault);\nPROVIDE(isr_reserved     = isr_hardfault);\nPROVIDE(isr_wwdt         = isr_hardfault);\nPROVIDE(isr_m0sub        = isr_hardfault);\nPROVIDE(isr_c_can0       = isr_hardfault);\nPROVIDE(isr_qei          = isr_hardfault);\n\n\/* --- LPC43XX specific peripheral definitions ----------------------------- *\/\n\/* local SRAM \/ external static memory banks (0x1000 0000 - 0x2000 0000) *\/\n\nlpc17xx_iomem_SPIFI_DATA = 0x14000000;\n\n\/* Memory map for all busses *\/\nlpc17xx_iomem_PERIPH_AHB  = 0x40000000;\nlpc17xx_iomem_PERIPH_APB0 = 0x40080000;\nlpc17xx_iomem_PERIPH_APB1 = 0x400A0000;\nlpc17xx_iomem_PERIPH_APB2 = 0x400C0000;\nlpc17xx_iomem_PERIPH_APB3 = 0x400E0000;\n\n\/* Register boundary addresses *\/\n\/* AHB (0x4000 0000 - 0x4001 2000) *\/\nlpc17xx_iomem_SCT = (lpc17xx_iomem_PERIPH_AHB + 0x00000);\n\n\/* PERIPH_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved *\/\nlpc17xx_iomem_GPDMA = (lpc17xx_iomem_PERIPH_AHB + 0x02000);\nlpc17xx_iomem_SPIFI = (lpc17xx_iomem_PERIPH_AHB + 0x03000);\nlpc17xx_iomem_SDIO  = (lpc17xx_iomem_PERIPH_AHB + 0x04000);\nlpc17xx_iomem_EMC   = (lpc17xx_iomem_PERIPH_AHB + 0x05000);\nlpc17xx_iomem_USB0  = (lpc17xx_iomem_PERIPH_AHB + 0x06000);\nlpc17xx_iomem_USB1  = (lpc17xx_iomem_PERIPH_AHB + 0x07000);\nlpc17xx_iomem_LCD   = (lpc17xx_iomem_PERIPH_AHB + 0x08000);\n\n\/* PERIPH_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved *\/\nlpc17xx_iomem_ETHERNET = (lpc17xx_iomem_PERIPH_AHB + 0x10000);\n\n\/* 0x4001 2000 - 0x4003 FFFF Reserved *\/\n\n\/* RTC domain peripherals *\/\nlpc17xx_iomem_ATIMER      = 0x40040000;\nlpc17xx_iomem_BACKUP_REG  = 0x40041000;\nlpc17xx_iomem_PMC         = 0x40042000;\nlpc17xx_iomem_CREG        = 0x40043000;\nlpc17xx_iomem_EVENTROUTER = 0x40044000;\nlpc17xx_iomem_OTP         = 0x40045000;\nlpc17xx_iomem_RTC         = 0x40046000;\n\n\/* 0x4004 7000 - 0x4004 FFFF Reserved *\/\n\n\/* clocking\/reset control peripherals *\/\nlpc17xx_iomem_CGU  = 0x40050000;\nlpc17xx_iomem_CCU1 = 0x40051000;\nlpc17xx_iomem_CCU2 = 0x40052000;\nlpc17xx_iomem_RGU  = 0x40053000;\n\n\/* 0x4005 4000 - 0x4005 FFFF Reserved *\/\n\/* 0x4006 0000 - 0x4007 FFFF Reserved *\/\n\n\/* APB0 ( 0x4008 0000 - 0x4008 FFFF) *\/\nlpc17xx_iomem_WWDT                  = (lpc17xx_iomem_PERIPH_APB0 + 0x00000);\nlpc17xx_iomem_USART0                = (lpc17xx_iomem_PERIPH_APB0 + 0x01000);\nlpc17xx_iomem_UART1                 = (lpc17xx_iomem_PERIPH_APB0 + 0x02000);\nlpc17xx_iomem_SSP0                  = (lpc17xx_iomem_PERIPH_APB0 + 0x03000);\nlpc17xx_iomem_TIMER0                = (lpc17xx_iomem_PERIPH_APB0 + 0x04000);\nlpc17xx_iomem_TIMER1                = (lpc17xx_iomem_PERIPH_APB0 + 0x05000);\nlpc17xx_iomem_SCU                   = (lpc17xx_iomem_PERIPH_APB0 + 0x06000);\nlpc17xx_iomem_GPIO_PIN_INTERRUPT    = (lpc17xx_iomem_PERIPH_APB0 + 0x07000);\nlpc17xx_iomem_GPIO_GROUP0_INTERRUPT = (lpc17xx_iomem_PERIPH_APB0 + 0x08000);\nlpc17xx_iomem_GPIO_GROUP1_INTERRUPT = (lpc17xx_iomem_PERIPH_APB0 + 0x09000);\n\n\/* 0x4008 A000 - 0x4008 FFFF Reserved *\/\n\/* 0x4009 0000 - 0x4009 FFFF Reserved *\/\n\n\/* APB1 (0x400A 0000 - 0x400A FFFF) *\/\nlpc17xx_iomem_MCPWM   = (lpc17xx_iomem_PERIPH_APB1 + 0x00000);\nlpc17xx_iomem_I2C0    = (lpc17xx_iomem_PERIPH_APB1 + 0x01000);\nlpc17xx_iomem_I2S0    = (lpc17xx_iomem_PERIPH_APB1 + 0x02000);\nlpc17xx_iomem_I2S1    = (lpc17xx_iomem_PERIPH_APB1 + 0x03000);\nlpc17xx_iomem_C_CCAN1 = (lpc17xx_iomem_PERIPH_APB1 + 0x04000);\n\n\/* 0x400A 5000 - 0x400A FFFF Reserved *\/\n\/* 0x400B 0000 - 0x400B FFFF Reserved *\/\n\n\/* APB2 (0x400C 0000 - 0x400C FFFF) *\/\nlpc17xx_iomem_RITIMER = (lpc17xx_iomem_PERIPH_APB2 + 0x00000);\nlpc17xx_iomem_USART2  = (lpc17xx_iomem_PERIPH_APB2 + 0x01000);\nlpc17xx_iomem_USART3  = (lpc17xx_iomem_PERIPH_APB2 + 0x02000);\nlpc17xx_iomem_TIMER2  = (lpc17xx_iomem_PERIPH_APB2 + 0x03000);\nlpc17xx_iomem_TIMER3  = (lpc17xx_iomem_PERIPH_APB2 + 0x04000);\nlpc17xx_iomem_SSP1    = (lpc17xx_iomem_PERIPH_APB2 + 0x05000);\nlpc17xx_iomem_QEI     = (lpc17xx_iomem_PERIPH_APB2 + 0x06000);\nlpc17xx_iomem_GIMA    = (lpc17xx_iomem_PERIPH_APB2 + 0x07000);\n\n\/* 0x400C 8000 - 0x400C FFFF Reserved *\/\n\/* 0x400D 0000 - 0x400D FFFF Reserved *\/\n\n\/* APB3 (0x400E 0000 - 0x400E FFFF) *\/\nlpc17xx_iomem_I2C1   = (lpc17xx_iomem_PERIPH_APB3 + 0x00000);\nlpc17xx_iomem_DAC    = (lpc17xx_iomem_PERIPH_APB3 + 0x01000);\nlpc17xx_iomem_C_CAN0 = (lpc17xx_iomem_PERIPH_APB3 + 0x02000);\nlpc17xx_iomem_ADC0   = (lpc17xx_iomem_PERIPH_APB3 + 0x03000);\nlpc17xx_iomem_ADC1   = (lpc17xx_iomem_PERIPH_APB3 + 0x04000);\n\n\/* 0x400E 5000 - 0x400E FFFF Reserved *\/\n\/* 0x400F 0000 - 0x400F 0FFF Reserved *\/\n\nlpc17xx_iomem_AES = 0x400F1000;\n\n\/* 0x400F 2000 - 0x400F 3FFF Reserved *\/\n\nlpc17xx_iomem_GPIO_PORT = 0x400F4000;\n\n\/* 0x400F 8000 - 0x400F FFFF Reserved *\/\n\nlpc17xx_iomem_SPI_PORT   = 0x40100000;\nlpc17xx_iomem_SGPIO_PORT = 0x40101000;\n\n\/* 0x4010 2000 - 0x41FF FFFF Reserved *\/\n\/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region *\/\n\/* 0x4400 0000 - 0x5FFF FFFF Reserved *\/\n\n\/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus *\/\nlpc17xx_iomem_SPIFI_DATA_UNCACHED = 0x80000000;\n\n\/* Lifted from a real lpc17xx, maybe (probably) incorrect) *\/\nlpc17xx_iomem_PINSEL0   = 0x4002C000;\nlpc17xx_iomem_PINSEL1   = 0x4002C004;\nlpc17xx_iomem_PINSEL2   = 0x4002C008;\nlpc17xx_iomem_PINSEL3   = 0x4002C00C;\nlpc17xx_iomem_PINSEL4   = 0x4002C010;\nlpc17xx_iomem_PINSEL7   = 0x4002C01C;\nlpc17xx_iomem_PINSEL9   = 0x4002C024;\nlpc17xx_iomem_PINSEL10  = 0x4002C028;\n\nlpc17xx_iomem_PINMODE0  = 0x4002C040;\nlpc17xx_iomem_PINMODE1  = 0x4002C044;\nlpc17xx_iomem_PINMODE2  = 0x4002C048;\nlpc17xx_iomem_PINMODE3  = 0x4002C04C;\nlpc17xx_iomem_PINMODE4  = 0x4002C050;\nlpc17xx_iomem_PINMODE7  = 0x4002C05C;\nlpc17xx_iomem_PINMODE9  = 0x4002C064;\n\nlpc17xx_iomem_PCONP     = 0x400FC0C4;\n\nlpc17xx_iomem_PCLKSEL0  = 0x400FC1A8;\nlpc17xx_iomem_PCLKSEL1  = 0x400FC1AC;\n\nlpc17xx_iomem_ADC       = 0x40034000;\n\nGPIO_LPC_PORT_OFFSET = lpc17xx_iomem_GPIO_PORT + 0x2000;\nlpc17xx_iomem_GPIO0  = GPIO_LPC_PORT_OFFSET + (0*4);\nlpc17xx_iomem_GPIO1  = GPIO_LPC_PORT_OFFSET + (1*4);\nlpc17xx_iomem_GPIO2  = GPIO_LPC_PORT_OFFSET + (2*4);\nlpc17xx_iomem_GPIO3  = GPIO_LPC_PORT_OFFSET + (3*4);\nlpc17xx_iomem_GPIO4  = GPIO_LPC_PORT_OFFSET + (4*4);\nlpc17xx_iomem_GPIO5  = GPIO_LPC_PORT_OFFSET + (5*4);\nlpc17xx_iomem_GPIO6  = GPIO_LPC_PORT_OFFSET + (6*4);\nlpc17xx_iomem_GPIO7  = GPIO_LPC_PORT_OFFSET + (7*4);\n","old_contents":"PROVIDE(isr_dac          = isr_hardfault);\nPROVIDE(isr_m0app        = isr_hardfault);\nPROVIDE(isr_dma          = isr_hardfault);\nPROVIDE(isr_reserved     = isr_hardfault);\nPROVIDE(isr_flasheeprom  = isr_hardfault);\nPROVIDE(isr_enet         = isr_hardfault);\nPROVIDE(isr_sdio         = isr_hardfault);\nPROVIDE(isr_lcd          = isr_hardfault);\nPROVIDE(isr_usb0         = isr_hardfault);\nPROVIDE(isr_usb1         = isr_hardfault);\nPROVIDE(isr_sctimer_pwm  = isr_hardfault);\nPROVIDE(isr_ritimer      = isr_hardfault);\nPROVIDE(isr_timer_0      = isr_hardfault);\nPROVIDE(isr_timer_1      = isr_hardfault);\nPROVIDE(isr_timer_2      = isr_hardfault);\nPROVIDE(isr_timer_3      = isr_hardfault);\nPROVIDE(isr_mcpwm        = isr_hardfault);\nPROVIDE(isr_adc0         = isr_hardfault);\nPROVIDE(isr_i2c_0        = isr_hardfault);\nPROVIDE(isr_i2c_1        = isr_hardfault);\nPROVIDE(isr_spi          = isr_hardfault);\nPROVIDE(isr_adc1         = isr_hardfault);\nPROVIDE(isr_ssp_0        = isr_hardfault);\nPROVIDE(isr_ssp_1        = isr_hardfault);\nPROVIDE(isr_uart_0       = isr_hardfault);\nPROVIDE(isr_uart_1       = isr_hardfault);\nPROVIDE(isr_uart_2       = isr_hardfault);\nPROVIDE(isr_uart_3       = isr_hardfault);\nPROVIDE(isr_i2s0         = isr_hardfault);\nPROVIDE(isr_i2s1         = isr_hardfault);\nPROVIDE(isr_spifi        = isr_hardfault);\nPROVIDE(isr_sgpio        = isr_hardfault);\nPROVIDE(isr_pin_int0     = isr_hardfault);\nPROVIDE(isr_pin_int1     = isr_hardfault);\nPROVIDE(isr_pin_int2     = isr_hardfault);\nPROVIDE(isr_pin_int3     = isr_hardfault);\nPROVIDE(isr_pin_int4     = isr_hardfault);\nPROVIDE(isr_pin_int5     = isr_hardfault);\nPROVIDE(isr_pin_int6     = isr_hardfault);\nPROVIDE(isr_pin_int7     = isr_hardfault);\nPROVIDE(isr_gint0        = isr_hardfault);\nPROVIDE(isr_gint1        = isr_hardfault);\nPROVIDE(isr_eventrouter  = isr_hardfault);\nPROVIDE(isr_c_can1       = isr_hardfault);\nPROVIDE(isr_reserved     = isr_hardfault);\nPROVIDE(isr_adchs        = isr_hardfault);\nPROVIDE(isr_atimer       = isr_hardfault);\nPROVIDE(isr_rtc          = isr_hardfault);\nPROVIDE(isr_reserved     = isr_hardfault);\nPROVIDE(isr_wwdt         = isr_hardfault);\nPROVIDE(isr_m0sub        = isr_hardfault);\nPROVIDE(isr_c_can0       = isr_hardfault);\nPROVIDE(isr_qei          = isr_hardfault);\n\n\/* --- LPC43XX specific peripheral definitions ----------------------------- *\/\n\/* local SRAM \/ external static memory banks (0x1000 0000 - 0x2000 0000) *\/\n\nlpc17xx_iomem_SPIFI_DATA = 0x14000000;\n\n\/* Memory map for all busses *\/\nlpc17xx_iomem_PERIPH_AHB  = 0x40000000;\nlpc17xx_iomem_PERIPH_APB0 = 0x40080000;\nlpc17xx_iomem_PERIPH_APB1 = 0x400A0000;\nlpc17xx_iomem_PERIPH_APB2 = 0x400C0000;\nlpc17xx_iomem_PERIPH_APB3 = 0x400E0000;\n\n\/* Register boundary addresses *\/\n\/* AHB (0x4000 0000 - 0x4001 2000) *\/\nlpc17xx_iomem_SCT = (lpc17xx_iomem_PERIPH_AHB + 0x00000);\n\n\/* PERIPH_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved *\/\nlpc17xx_iomem_GPDMA = (lpc17xx_iomem_PERIPH_AHB + 0x02000);\nlpc17xx_iomem_SPIFI = (lpc17xx_iomem_PERIPH_AHB + 0x03000);\nlpc17xx_iomem_SDIO  = (lpc17xx_iomem_PERIPH_AHB + 0x04000);\nlpc17xx_iomem_EMC   = (lpc17xx_iomem_PERIPH_AHB + 0x05000);\nlpc17xx_iomem_USB0  = (lpc17xx_iomem_PERIPH_AHB + 0x06000);\nlpc17xx_iomem_USB1  = (lpc17xx_iomem_PERIPH_AHB + 0x07000);\nlpc17xx_iomem_LCD   = (lpc17xx_iomem_PERIPH_AHB + 0x08000);\n\n\/* PERIPH_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved *\/\nlpc17xx_iomem_ETHERNET = (lpc17xx_iomem_PERIPH_AHB + 0x10000);\n\n\/* 0x4001 2000 - 0x4003 FFFF Reserved *\/\n\n\/* RTC domain peripherals *\/\nlpc17xx_iomem_ATIMER      = 0x40040000;\nlpc17xx_iomem_BACKUP_REG  = 0x40041000;\nlpc17xx_iomem_PMC         = 0x40042000;\nlpc17xx_iomem_CREG        = 0x40043000;\nlpc17xx_iomem_EVENTROUTER = 0x40044000;\nlpc17xx_iomem_OTP         = 0x40045000;\nlpc17xx_iomem_RTC         = 0x40046000;\n\n\/* 0x4004 7000 - 0x4004 FFFF Reserved *\/\n\n\/* clocking\/reset control peripherals *\/\nlpc17xx_iomem_CGU  = 0x40050000;\nlpc17xx_iomem_CCU1 = 0x40051000;\nlpc17xx_iomem_CCU2 = 0x40052000;\nlpc17xx_iomem_RGU  = 0x40053000;\n\n\/* 0x4005 4000 - 0x4005 FFFF Reserved *\/\n\/* 0x4006 0000 - 0x4007 FFFF Reserved *\/\n\n\/* APB0 ( 0x4008 0000 - 0x4008 FFFF) *\/\nlpc17xx_iomem_WWDT                  = (lpc17xx_iomem_PERIPH_APB0 + 0x00000);\nlpc17xx_iomem_USART0                = (lpc17xx_iomem_PERIPH_APB0 + 0x01000);\nlpc17xx_iomem_UART1                 = (lpc17xx_iomem_PERIPH_APB0 + 0x02000);\nlpc17xx_iomem_SSP0                  = (lpc17xx_iomem_PERIPH_APB0 + 0x03000);\nlpc17xx_iomem_TIMER0                = (lpc17xx_iomem_PERIPH_APB0 + 0x04000);\nlpc17xx_iomem_TIMER1                = (lpc17xx_iomem_PERIPH_APB0 + 0x05000);\nlpc17xx_iomem_SCU                   = (lpc17xx_iomem_PERIPH_APB0 + 0x06000);\nlpc17xx_iomem_GPIO_PIN_INTERRUPT    = (lpc17xx_iomem_PERIPH_APB0 + 0x07000);\nlpc17xx_iomem_GPIO_GROUP0_INTERRUPT = (lpc17xx_iomem_PERIPH_APB0 + 0x08000);\nlpc17xx_iomem_GPIO_GROUP1_INTERRUPT = (lpc17xx_iomem_PERIPH_APB0 + 0x09000);\n\n\/* 0x4008 A000 - 0x4008 FFFF Reserved *\/\n\/* 0x4009 0000 - 0x4009 FFFF Reserved *\/\n\n\/* APB1 (0x400A 0000 - 0x400A FFFF) *\/\nlpc17xx_iomem_MCPWM   = (lpc17xx_iomem_PERIPH_APB1 + 0x00000);\nlpc17xx_iomem_I2C0    = (lpc17xx_iomem_PERIPH_APB1 + 0x01000);\nlpc17xx_iomem_I2S0    = (lpc17xx_iomem_PERIPH_APB1 + 0x02000);\nlpc17xx_iomem_I2S1    = (lpc17xx_iomem_PERIPH_APB1 + 0x03000);\nlpc17xx_iomem_C_CCAN1 = (lpc17xx_iomem_PERIPH_APB1 + 0x04000);\n\n\/* 0x400A 5000 - 0x400A FFFF Reserved *\/\n\/* 0x400B 0000 - 0x400B FFFF Reserved *\/\n\n\/* APB2 (0x400C 0000 - 0x400C FFFF) *\/\nlpc17xx_iomem_RITIMER = (lpc17xx_iomem_PERIPH_APB2 + 0x00000);\nlpc17xx_iomem_USART2  = (lpc17xx_iomem_PERIPH_APB2 + 0x01000);\nlpc17xx_iomem_USART3  = (lpc17xx_iomem_PERIPH_APB2 + 0x02000);\nlpc17xx_iomem_TIMER2  = (lpc17xx_iomem_PERIPH_APB2 + 0x03000);\nlpc17xx_iomem_TIMER3  = (lpc17xx_iomem_PERIPH_APB2 + 0x04000);\nlpc17xx_iomem_SSP1    = (lpc17xx_iomem_PERIPH_APB2 + 0x05000);\nlpc17xx_iomem_QEI     = (lpc17xx_iomem_PERIPH_APB2 + 0x06000);\nlpc17xx_iomem_GIMA    = (lpc17xx_iomem_PERIPH_APB2 + 0x07000);\n\n\/* 0x400C 8000 - 0x400C FFFF Reserved *\/\n\/* 0x400D 0000 - 0x400D FFFF Reserved *\/\n\n\/* APB3 (0x400E 0000 - 0x400E FFFF) *\/\nlpc17xx_iomem_I2C1   = (lpc17xx_iomem_PERIPH_APB3 + 0x00000);\nlpc17xx_iomem_DAC    = (lpc17xx_iomem_PERIPH_APB3 + 0x01000);\nlpc17xx_iomem_C_CAN0 = (lpc17xx_iomem_PERIPH_APB3 + 0x02000);\nlpc17xx_iomem_ADC0   = (lpc17xx_iomem_PERIPH_APB3 + 0x03000);\nlpc17xx_iomem_ADC1   = (lpc17xx_iomem_PERIPH_APB3 + 0x04000);\n\n\/* 0x400E 5000 - 0x400E FFFF Reserved *\/\n\/* 0x400F 0000 - 0x400F 0FFF Reserved *\/\n\nlpc17xx_iomem_AES = 0x400F1000;\n\n\/* 0x400F 2000 - 0x400F 3FFF Reserved *\/\n\nlpc17xx_iomem_GPIO_PORT = 0x400F4000;\n\n\/* 0x400F 8000 - 0x400F FFFF Reserved *\/\n\nlpc17xx_iomem_SPI_PORT   = 0x40100000;\nlpc17xx_iomem_SGPIO_PORT = 0x40101000;\n\n\/* 0x4010 2000 - 0x41FF FFFF Reserved *\/\n\/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region *\/\n\/* 0x4400 0000 - 0x5FFF FFFF Reserved *\/\n\n\/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus *\/\nlpc17xx_iomem_SPIFI_DATA_UNCACHED = 0x80000000;\n\n\/* Lifted from a real lpc17xx, maybe (probably) incorrect) *\/\nlpc17xx_iomem_PINSEL0   = 0x4002C000;\nlpc17xx_iomem_PINSEL1   = 0x4002C004;\nlpc17xx_iomem_PINSEL2   = 0x4002C008;\nlpc17xx_iomem_PINSEL3   = 0x4002C00C;\nlpc17xx_iomem_PINSEL4   = 0x4002C010;\nlpc17xx_iomem_PINSEL7   = 0x4002C01C;\nlpc17xx_iomem_PINSEL9   = 0x4002C024;\nlpc17xx_iomem_PINSEL10  = 0x4002C028;\n\nlpc17xx_iomem_PINMODE0  = 0x4002C040;\nlpc17xx_iomem_PINMODE1  = 0x4002C044;\nlpc17xx_iomem_PINMODE2  = 0x4002C048;\nlpc17xx_iomem_PINMODE3  = 0x4002C04C;\nlpc17xx_iomem_PINMODE4  = 0x4002C050;\nlpc17xx_iomem_PINMODE7  = 0x4002C05C;\nlpc17xx_iomem_PINMODE9  = 0x4002C064;\n\nlpc17xx_iomem_PCONP     = 0x400FC0C4;\n\nlpc17xx_iomem_PCLKSEL0  = 0x400FC1A8;\nlpc17xx_iomem_PCLKSEL1  = 0x400FC1AC;\n\nlpc17xx_iomem_ADC       = 0x40034000;\n\nlpc17xx_iomem_GPIO0     = 0x2009C000;\nlpc17xx_iomem_GPIO1     = 0x2009C020;\nlpc17xx_iomem_GPIO2     = 0x2009C040;\nlpc17xx_iomem_GPIO3     = 0x2009C060;\nlpc17xx_iomem_GPIO4     = 0x2009C080;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"be35924820ef58c93969fef208a06edf7c0364e5","subject":"adds comments.","message":"adds comments.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/microchip-pic32mx-duinomitemega\/target.ld","new_file":"boards\/microchip-pic32mx-duinomitemega\/target.ld","new_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 64K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_userboot (rx) : ORIGIN = 0xBD000000, LENGTH = 0x1000\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0xBD001000, LENGTH = 512K - 4K \/*we skipped the first page to allow for the interrupt vector table. There is a lot of free space there, but linking needs to flow around existing absolute sections there. *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0xBFC00000, LENGTH = 0x0 \/* Don't allow stuff in the boot flash, there is a bootloader there *\/\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** TEMPORARY: located at end of bootflash for now (this is \"debug page\")...\r\n** 0xBFC03000-(0x10 config registers + 0x200+ (64 vectors * x20))= 0xBFC025F0\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0xBD000000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\n\/* NOT NEEDED -- we have our own entry routine, not using cs3's\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) *\/\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 9k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** First thing in  flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n  } >PIC32MX_flash_userboot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; DRN updated this; seems correct...  bracz: not really. *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","old_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 64K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_userboot (rx) : ORIGIN = 0xBD000000, LENGTH = 0x1000\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0xBD001000, LENGTH = 512K - 4K \/*we skipped the first page to allow for the interrupt vector table. There is a lot of free space there, but linking needs to flow around existing absolute sections there. *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0xBFC00000, LENGTH = 0x0 \/* Don't allow stuff in the boot flash, there is a bootloader there *\/\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** TEMPORARY: located at end of bootflash for now (this is \"debug page\")...\r\n** 0xBFC03000-(0x10 config registers + 0x200+ (64 vectors * x20))= 0xBFC025F0\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0xBD000000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\n\/* EXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) *\/\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 9k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** First thing in  flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n  } >PIC32MX_flash_userboot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; \/* DRN updated this; seems correct... *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"1dd6adb0a6872f17bf7c0c802afcc52a5d1844ec","subject":"Fix linker script","message":"Fix linker script\n","repos":"sonicyang\/uRock,BeyondCloud\/uRock,BeyondCloud\/uRock,BeyondCloud\/uRock,sonicyang\/uRock,sonicyang\/uRock,sonicyang\/uRock,BeyondCloud\/uRock","old_file":"STM32F429I_DISCO\/STM32F429ZI_FLASH.ld","new_file":"STM32F429I_DISCO\/STM32F429ZI_FLASH.ld","new_contents":"\/*\r\n*****************************************************************************\r\n**\r\n**  File        : stm32_flash.ld\r\n**\r\n**  Abstract    : Linker script for STM32F429ZI Device with\r\n**                2048KByte FLASH, 192KByte RAM\r\n**\r\n**                Set heap size, stack size and stack location according\r\n**                to application requirements.\r\n**\r\n**                Set memory bank area and size if external memory is used.\r\n**\r\n**  Target      : STMicroelectronics STM32\r\n**\r\n**  Environment : Atollic TrueSTUDIO(R)\r\n**\r\n**  Distribution: The file is distributed as is, without any warranty\r\n**                of any kind.\r\n**\r\n**  (c)Copyright Atollic AB.\r\n**  You may use this file as-is or modify it according to the needs of your\r\n**  project. This file may only be built (assembled or compiled and linked)\r\n**  using the Atollic TrueSTUDIO(R) product. The use of this file together\r\n**  with other tools than Atollic TrueSTUDIO(R) is not permitted.\r\n**\r\n*****************************************************************************\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\n\/* Highest address of the user mode stack *\/\r\n_estack = 0x2002FFFF;    \/* end of RAM *\/\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x800;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x800; \/* required amount of stack *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 2048K\r\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 192K\r\nCCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector)) \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  \/* The program code and other data goes into FLASH *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)           \/* .text sections (code) *\/\r\n    *(.text*)          \/* .text* sections (code) *\/\r\n    *(.glue_7)         \/* glue arm to thumb code *\/\r\n    *(.glue_7t)        \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;        \/* define a global symbols at end of code *\/\r\n  } >FLASH\r\n\r\n  \/* Constant data goes into FLASH *\/\r\n  .rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n  .ARM : {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } >FLASH\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } >FLASH\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } >FLASH\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } >FLASH\r\n\r\n  \/* used by the startup to initialize data *\/\r\n  _sidata = LOADADDR(.data);\r\n\r\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\r\n  .data : \r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .;        \/* create a global symbol at data start *\/\r\n    *(.data)           \/* .data sections *\/\r\n    *(.data*)          \/* .data* sections *\/\r\n\r\n    . = ALIGN(4);\r\n    _edata = .;        \/* define a global symbol at data end *\/\r\n  } >RAM AT> FLASH\r\n\r\n  _siccmram = LOADADDR(.ccmram);\r\n\r\n  \/* CCM-RAM section \r\n  * \r\n  * IMPORTANT NOTE! \r\n  * If initialized variables will be placed in this section, \r\n  * the startup code needs to be modified to copy the init-values.  \r\n  *\/\r\n  .ccmram :\r\n  {\r\n    . = ALIGN(4);\r\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\r\n    *(.ccmram)\r\n    *(.ccmram*)\r\n    \r\n    . = ALIGN(4);\r\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\r\n  } >CCMRAM AT> FLASH\r\n\r\n  \r\n  \/* Uninitialized data section *\/\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n    _sbss = .;         \/* define a global symbol at bss start *\/\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .;         \/* define a global symbol at bss end *\/\r\n    __bss_end__ = _ebss;\r\n  } >RAM\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(4);\r\n  } >RAM\r\n\r\n  \r\n\r\n  \/* Remove information from the standard libraries *\/\r\n  \/DISCARD\/ :\r\n  {\r\n    libc.a ( * )\r\n    libm.a ( * )\r\n    libgcc.a ( * )\r\n  }\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n","old_contents":"","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"31e675b3591e8f515da3484cc329c67d4a41e803","subject":"cpu: cortex_common: Add entry point to tell gdb where to start","message":"cpu: cortex_common: Add entry point to tell gdb where to start\n","repos":"Josar\/RIOT,kaleb-himes\/RIOT,d00616\/RIOT,mfrey\/RIOT,biboc\/RIOT,altairpearl\/RIOT,BytesGalore\/RIOT,toonst\/RIOT,neumodisch\/RIOT,josephnoir\/RIOT,yogo1212\/RIOT,adrianghc\/RIOT,avmelnikoff\/RIOT,hamilton-mote\/RIOT-OS,kbumsik\/RIOT,syin2\/RIOT,A-Paul\/RIOT,yogo1212\/RIOT,jfischer-phytec-iot\/RIOT,hamilton-mote\/RIOT-OS,immesys\/RiSyn,smlng\/RIOT,d00616\/RIOT,altairpearl\/RIOT,Josar\/RIOT,jbeyerstedt\/RIOT-OTA-update,katezilla\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,plushvoxel\/RIOT,gebart\/RIOT,dkm\/RIOT,OlegHahm\/RIOT,A-Paul\/RIOT,BytesGalore\/RIOT,OTAkeys\/RIOT,tfar\/RIOT,basilfx\/RIOT,lazytech-org\/RIOT,backenklee\/RIOT,cladmi\/RIOT,LudwigKnuepfer\/RIOT,ant9000\/RIOT,syin2\/RIOT,backenklee\/RIOT,TobiasFredersdorf\/RIOT,Ell-i\/RIOT,ks156\/RIOT,RIOT-OS\/RIOT,gebart\/RIOT,alignan\/RIOT,backenklee\/RIOT,Ell-i\/RIOT,avmelnikoff\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,dkm\/RIOT,rfuentess\/RIOT,roberthartung\/RIOT,gautric\/RIOT,altairpearl\/RIOT,adjih\/RIOT,Hyungsin\/RIOT-OS,mfrey\/RIOT,tfar\/RIOT,yogo1212\/RIOT,smlng\/RIOT,kaleb-himes\/RIOT,lazytech-org\/RIOT,ks156\/RIOT,altairpearl\/RIOT,RIOT-OS\/RIOT,tfar\/RIOT,OlegHahm\/RIOT,mtausig\/RIOT,neumodisch\/RIOT,mtausig\/RIOT,jfischer-phytec-iot\/RIOT,neumodisch\/RIOT,josephnoir\/RIOT,LudwigOrtmann\/RIOT,smlng\/RIOT,gebart\/RIOT,alignan\/RIOT,avmelnikoff\/RIOT,d00616\/RIOT,dkm\/RIOT,kerneltask\/RIOT,kb2ma\/RIOT,Hyungsin\/RIOT-OS,mtausig\/RIOT,roberthartung\/RIOT,dailab\/RIOT,jasonatran\/RIOT,syin2\/RIOT,smlng\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,thomaseichinger\/RIOT,jbeyerstedt\/RIOT-OTA-update,josephnoir\/RIOT,TobiasFredersdorf\/RIOT,TobiasFredersdorf\/RIOT,A-Paul\/RIOT,neumodisch\/RIOT,neiljay\/RIOT,avmelnikoff\/RIOT,Josar\/RIOT,d00616\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,altairpearl\/RIOT,josephnoir\/RIOT,kYc0o\/RIOT,katezilla\/RIOT,katezilla\/RIOT,OTAkeys\/RIOT,tfar\/RIOT,jfischer-phytec-iot\/RIOT,syin2\/RIOT,katezilla\/RIOT,tfar\/RIOT,thomaseichinger\/RIOT,authmillenon\/RIOT,ks156\/RIOT,LudwigOrtmann\/RIOT,toonst\/RIOT,gautric\/RIOT,BytesGalore\/RIOT,lazytech-org\/RIOT,kYc0o\/RIOT,LudwigKnuepfer\/RIOT,hamilton-mote\/RIOT-OS,OlegHahm\/RIOT,BytesGalore\/RIOT,beurdouche\/RIOT,jbeyerstedt\/RIOT-OTA-update,kerneltask\/RIOT,kbumsik\/RIOT,biboc\/RIOT,kaspar030\/RIOT,mfrey\/RIOT,backenklee\/RIOT,adjih\/RIOT,kb2ma\/RIOT,jbeyerstedt\/RIOT-OTA-update,jfischer-phytec-iot\/RIOT,d00616\/RIOT,cladmi\/RIOT,alignan\/RIOT,authmillenon\/RIOT,cladmi\/RIOT,LudwigKnuepfer\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,kYc0o\/RIOT,aeneby\/RIOT,biboc\/RIOT,ant9000\/RIOT,Hyungsin\/RIOT-OS,lazytech-org\/RIOT,kb2ma\/RIOT,rfuentess\/RIOT,adrianghc\/RIOT,OlegHahm\/RIOT,neiljay\/RIOT,beurdouche\/RIOT,LudwigOrtmann\/RIOT,RIOT-OS\/RIOT,gebart\/RIOT,RIOT-OS\/RIOT,gautric\/RIOT,aeneby\/RIOT,hamilton-mote\/RIOT-OS,josephnoir\/RIOT,immesys\/RiSyn,jasonatran\/RIOT,dkm\/RIOT,aeneby\/RIOT,basilfx\/RIOT,dkm\/RIOT,rfuentess\/RIOT,kaleb-himes\/RIOT,dailab\/RIOT,aeneby\/RIOT,TobiasFredersdorf\/RIOT,yogo1212\/RIOT,thomaseichinger\/RIOT,immesys\/RiSyn,kaspar030\/RIOT,biboc\/RIOT,miri64\/RIOT,jbeyerstedt\/RIOT-OTA-update,mtausig\/RIOT,immesys\/RiSyn,katezilla\/RIOT,OlegHahm\/RIOT,LudwigKnuepfer\/RIOT,x3ro\/RIOT,adrianghc\/RIOT,thomaseichinger\/RIOT,Josar\/RIOT,beurdouche\/RIOT,rfuentess\/RIOT,kaleb-himes\/RIOT,hamilton-mote\/RIOT-OS,neiljay\/RIOT,BytesGalore\/RIOT,mtausig\/RIOT,lazytech-org\/RIOT,A-Paul\/RIOT,ant9000\/RIOT,adjih\/RIOT,miri64\/RIOT,toonst\/RIOT,kbumsik\/RIOT,kbumsik\/RIOT,kerneltask\/RIOT,basilfx\/RIOT,cladmi\/RIOT,roberthartung\/RIOT,altairpearl\/RIOT,LudwigOrtmann\/RIOT,gautric\/RIOT,basilfx\/RIOT,ks156\/RIOT,dailab\/RIOT,alignan\/RIOT,toonst\/RIOT,syin2\/RIOT,mfrey\/RIOT,dailab\/RIOT,jasonatran\/RIOT,avmelnikoff\/RIOT,neumodisch\/RIOT,LudwigOrtmann\/RIOT,neumodisch\/RIOT,jfischer-phytec-iot\/RIOT,x3ro\/RIOT,kb2ma\/RIOT,beurdouche\/RIOT,kerneltask\/RIOT,roberthartung\/RIOT,Ell-i\/RIOT,plushvoxel\/RIOT,ant9000\/RIOT,plushvoxel\/RIOT,kaspar030\/RIOT,Ell-i\/RIOT,ks156\/RIOT,kb2ma\/RIOT,kaleb-himes\/RIOT,adjih\/RIOT,jasonatran\/RIOT,Josar\/RIOT,miri64\/RIOT,adjih\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,x3ro\/RIOT,RIOT-OS\/RIOT,plushvoxel\/RIOT,TobiasFredersdorf\/RIOT,dailab\/RIOT,yogo1212\/RIOT,immesys\/RiSyn,cladmi\/RIOT,LudwigOrtmann\/RIOT,roberthartung\/RIOT,beurdouche\/RIOT,A-Paul\/RIOT,adrianghc\/RIOT,kbumsik\/RIOT,immesys\/RiSyn,kaspar030\/RIOT,toonst\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,mfrey\/RIOT,kaspar030\/RIOT,Ell-i\/RIOT,kerneltask\/RIOT,kYc0o\/RIOT,gebart\/RIOT,yogo1212\/RIOT,basilfx\/RIOT,Hyungsin\/RIOT-OS,miri64\/RIOT,Hyungsin\/RIOT-OS,d00616\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,OTAkeys\/RIOT,adrianghc\/RIOT,OTAkeys\/RIOT,gautric\/RIOT,miri64\/RIOT,LudwigKnuepfer\/RIOT,x3ro\/RIOT,ant9000\/RIOT,smlng\/RIOT,authmillenon\/RIOT,alignan\/RIOT,biboc\/RIOT,rfuentess\/RIOT,neiljay\/RIOT,authmillenon\/RIOT,thomaseichinger\/RIOT,backenklee\/RIOT,neiljay\/RIOT,plushvoxel\/RIOT,aeneby\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* This is only used by gdb to understand where to start *\/\nENTRY(reset_handler_default)\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information abour ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information abour ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"27f553d431d0a54c1b78e4d2d7ee826acac1b7c7","subject":"changes to ld script for C++","message":"changes to ld script for C++\n","repos":"yhx189\/nautilus,yhx189\/nautilus,yhx189\/nautilus,haiyang1992\/NautilusVirtio,bradylee\/nautilus_fs,haiyang1992\/NautilusVirtio,bradylee\/nautilus_fs,haiyang1992\/NautilusVirtio,bradylee\/nautilus_fs","old_file":"nautilus.ld","new_file":"nautilus.ld","new_contents":"ENTRY(nautilus_entry)\n\nSECTIONS\n{\n    . = 0x100000;\n\n    .boot :\n    {\n        *(.mbhdr)\n        _loadStart = .;\n        *(.boot)\n        . = ALIGN(4096);\n        pml4 = .;\n        . += 0x1000;\n        pdpt = .;\n        . += 0x1000;\n        pd = .;\n        . += 0x1000; \n\n        \/* stack *\/\n        . += 0x4000;\n        boot_stack = .;\n        . += 0x1000; \/* TODO: remove this, for now to be safe... *\/\n    }\n\n\n    .text ALIGN(0x1000) : \n    {\n        *(.text*)\n        *(.gnu.linkonce.t*)\n    }\n\n    .init_array ALIGN(0x1000) : AT(ADDR(.text) + SIZEOF(.text))\n    {\n        *(.init_array*)\n        *(.gnu.linkonce.init_array*)\n    }\n\n\n    .gcc_except_table ALIGN(0x1000) : AT(ADDR(.init_array) + SIZEOF(.init_array))\n    {\n        *(.gcc_except_table*)\n        *(.gnu.linkonce.gcc_except*)\n    }\n    \n    .data ALIGN(0x1000) : AT(ADDR(.gcc_except_table) + SIZEOF(.gcc_except_table))\n    {\n        *(.data*)\n        *(.gnu.linkonce.d*)\n    }\n    \n    .rodata ALIGN(0x1000) : AT(ADDR(.data) + SIZEOF(.data))\n    {\n        *(.rodata*)\n        *(.gnu.linkonce.r*)\n    }\n    \n\n    .got ALIGN(0x1000) : AT(ADDR(.rodata)+SIZEOF(.rodata))\n    {\n        *(.got*)\n        *(.gnu.linkconce.got*)\n    }\n\n\n    _loadEnd = .; \n    \n    .bss ALIGN(0x1000) : AT(ADDR(.rodata)+SIZEOF(.rodata))\n    {\n        *(COMMON)\n        *(.bss*)\n        *(.gnu.linkonce.b*)\n    }\n    \n    _bssEnd = .; \n    \n    \/DISCARD\/ :\n    {\n        *(.comment)\n        *(.eh_frame)\n    }\n}\n\n","old_contents":"ENTRY(nautilus_entry)\n\nSECTIONS\n{\n    . = 0x100000;\n\n    .boot :\n    {\n        *(.mbhdr)\n        _loadStart = .;\n        *(.boot)\n        . = ALIGN(4096);\n        pml4 = .;\n        . += 0x1000;\n        pdpt = .;\n        . += 0x1000;\n        pd = .;\n        . += 0x1000; \n\n        \/* stack *\/\n        . += 0x4000;\n        boot_stack = .;\n        . += 0x1000; \/* TODO: remove this, for now to be safe... *\/\n    }\n\n\n    .text ALIGN(0x1000) : \n    {\n        *(.text)\n        *(.gnu.linkonce.t*)\n    }\n    \n    .data ALIGN(0x1000) : AT(ADDR(.text) + SIZEOF(.text))\n    {\n        *(.data)\n        *(.gnu.linkonce.d*)\n    }\n    \n    .rodata ALIGN(0x1000) : AT(ADDR(.data) + SIZEOF(.data))\n    {\n        *(.rodata*)\n        *(.gnu.linkonce.r*)\n    }\n    \n    _loadEnd = .; \n    \n    .bss ALIGN(0x1000) : AT(ADDR(.rodata)+SIZEOF(.rodata))\n    {\n        *(COMMON)\n        *(.bss)\n        *(.gnu.linkonce.b*)\n    }\n    \n    _bssEnd = .; \n    \n    \/DISCARD\/ :\n    {\n        *(.comment)\n        *(.eh_frame)\n    }\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ed5c091bed02c489cf324023dcadfbaafb9d2cb1","subject":"linker: add missing symbols (only needed for debug build)","message":"linker: add missing symbols (only needed for debug build)\n","repos":"posborne\/zinc,farcaller\/zinc,ntwyman\/zinc,mcoffin\/zinc,troplin\/zinc,farcaller\/zinc,richo\/zinc,troplin\/zinc,phil-opp\/zinc,mcoffin\/zinc,posborne\/zinc,posborne\/zinc,richo\/zinc,farcaller\/zinc,mcoffin\/zinc,posborne\/zinc,ntwyman\/zinc,phil-opp\/zinc,hackndev\/zinc,troplin\/zinc,hackndev\/zinc,farcaller\/zinc,mcoffin\/zinc,hackndev\/zinc,phil-opp\/zinc,phil-opp\/zinc,phil-opp\/zinc,mcoffin\/zinc,richo\/zinc,richo\/zinc,ntwyman\/zinc,troplin\/zinc,posborne\/zinc,ntwyman\/zinc,hackndev\/zinc,farcaller\/zinc,ntwyman\/zinc,troplin\/zinc,hackndev\/zinc,richo\/zinc","old_file":"src\/hal\/layout_common.ld","new_file":"src\/hal\/layout_common.ld","new_contents":"\/* TODO(farcaller): layout_common isn't actually common. k20 keeps own copy *\/\n__aeabi_unwind_cpp_pr0 = abort;\n__aeabi_unwind_cpp_pr1 = abort;\n__aeabi_unwind_cpp_pr2 = abort;\n__exidx_start          = abort;\n__exidx_end            = abort;\n\n__aeabi_memclr4 = __aeabi_memclr;\n\nSECTIONS\n{\n    .vector : ALIGN(4)\n    {\n        FILL(0xff)\n\n        KEEP(*(.isr_vector))\n        KEEP(*(.isr_vector_nvic))\n    } > vectors\n\n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        *(.text*)\n        *(.rodata .rodata.*)\n    } > rom\n\n    .data : ALIGN(4)\n    {\n        _data = .;\n\n        *(SORT_BY_ALIGNMENT(.data*))\n        . = ALIGN(4);\n\n        _edata = .;\n    } > ram AT>rom = 0xff\n\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n\n        _ebss = .;\n\n        . += 4;\n\n        __STACK_LIMIT = .;\n\n        . += 4;\n\n        _eglobals = .;\n    } > ram\n\n    \/DISCARD\/ :\n    {\n        *(.glue_7*)  \/* arm-thumb interworking *\/\n        *(.v4_bx)  \/* ARMv4 interworking fixup for missing BX *\/\n        *(.vfp11_veneer)  \/* VFP11 bugfixes s.a. http:\/\/sourceware.org\/ml\/binutils\/2006-12\/msg00196.html *\/\n        *(.iplt .igot.plt)  \/* STT_GNU_IFUNC symbols *\/\n        *(.rel.*)  \/* dynamic relocations *\/\n        *(.ARM.exidx*) \/* index entries for section unwinding *\/\n        *(.ARM.extab*) \/* exception unwinding information *\/\n        *(.debug_gdb_scripts)\n    }\n}\n","old_contents":"\/* TODO(farcaller): layout_common isn't actually common. k20 keeps own copy *\/\n__aeabi_unwind_cpp_pr0 = abort;\n__aeabi_unwind_cpp_pr1 = abort;\n__aeabi_unwind_cpp_pr2 = abort;\n\n__aeabi_memclr4 = __aeabi_memclr;\n\nSECTIONS\n{\n    .vector : ALIGN(4)\n    {\n        FILL(0xff)\n\n        KEEP(*(.isr_vector))\n        KEEP(*(.isr_vector_nvic))\n    } > vectors\n\n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        *(.text*)\n        *(.rodata .rodata.*)\n    } > rom\n\n    .data : ALIGN(4)\n    {\n        _data = .;\n\n        *(SORT_BY_ALIGNMENT(.data*))\n        . = ALIGN(4);\n\n        _edata = .;\n    } > ram AT>rom = 0xff\n\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n\n        _ebss = .;\n\n        . += 4;\n\n        __STACK_LIMIT = .;\n\n        . += 4;\n\n        _eglobals = .;\n    } > ram\n\n    \/DISCARD\/ :\n    {\n        *(.glue_7*)  \/* arm-thumb interworking *\/\n        *(.v4_bx)  \/* ARMv4 interworking fixup for missing BX *\/\n        *(.vfp11_veneer)  \/* VFP11 bugfixes s.a. http:\/\/sourceware.org\/ml\/binutils\/2006-12\/msg00196.html *\/\n        *(.iplt .igot.plt)  \/* STT_GNU_IFUNC symbols *\/\n        *(.rel.*)  \/* dynamic relocations *\/\n        *(.ARM.exidx*) \/* index entries for section unwinding *\/\n        *(.ARM.extab*) \/* exception unwinding information *\/\n        *(.debug_gdb_scripts)\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4513aea65e78792baba85fd92c040b251f61a1ab","subject":"Strip debug symbols from user apps","message":"Strip debug symbols from user apps\n","repos":"escortkeel\/k-os,escortkeel\/k-os,escortkeel\/k-os","old_file":"libc\/linker.ld","new_file":"libc\/linker.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\")\nOUTPUT_ARCH(\"i386\")\nENTRY(_start)\nSECTIONS {\n    . = 0x500000;\n\n    .text ALIGN (0x1000) : AT(ADDR(.text)) {\n        *(.text.entry)\n        *(.text.startup)\n        *(.text)\n        *(.rodata*)\n    }\n    _data_start = .;\n    .data ALIGN (0x1000) : AT(ADDR(.data)) {\n        *(.data)\n    }\n    .bss ALIGN (0x1000) : AT(ADDR(.bss)) {\n        _sbss = .;\n        *(COMMON)\n        *(.bss)\n        _ebss = .;\n    }\n    _data_end = .;\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.eh_frame)\n    }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\")\nOUTPUT_ARCH(\"i386\")\nENTRY(_start)\nSECTIONS {\n    . = 0x500000;\n\n    .text ALIGN (0x1000) : AT(ADDR(.text)) {\n        *(.text.entry)\n        *(.text.startup)\n        *(.text)\n        *(.rodata*)\n    }\n    _data_start = .;\n    .data ALIGN (0x1000) : AT(ADDR(.data)) {\n        *(.data)\n    }\n    .bss ALIGN (0x1000) : AT(ADDR(.bss)) {\n        _sbss = .;\n        *(COMMON)\n        *(.bss)\n        _ebss = .;\n    }\n    _data_end = .;\n    \/DISCARD\/ : {\n        *(.comment)\n    }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"1b95c09a275a97b4749f4e1ffc292d4f5fc2f8c5","subject":"switch.ld: update init_array\/fini_array handling for latest devkitA64","message":"switch.ld: update init_array\/fini_array handling for latest devkitA64\n","repos":"switchbrew\/libnx","old_file":"nx\/switch.ld","new_file":"nx\/switch.ld","new_contents":"OUTPUT_ARCH(aarch64)\nENTRY(_start)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(5) \/* Read | Execute *\/;\n\trodata PT_LOAD FLAGS(4) \/* Read *\/;\n\tdata   PT_LOAD FLAGS(6) \/* Read | Write *\/;\n\tdyn    PT_DYNAMIC;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\tPROVIDE(__start__ = 0x0);\n\t. = __start__;\n\t__code_start = . ;\n\n\t.crt0 :\n\t{\n\t\tKEEP (*(.crt0))\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.init :\n\t{\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.plt :\n\t{\n\t\t*(.plt)\n\t\t*(.iplt)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.text :\n\t{\n\t\t*(.text.unlikely .text.*_unlikely .text.unlikely.*)\n\t\t*(.text.exit .text.exit.*)\n\t\t*(.text.startup .text.startup.*)\n\t\t*(.text.hot .text.hot.*)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.fini :\n\t{\n\t\tKEEP( *(.fini) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t\/* =========== RODATA section =========== *\/\n\t. = ALIGN(0x1000);\n\t__rodata_start = . ;\n\n\t.nx-module-name : { KEEP (*(.nx-module-name)) } :rodata\n\n\t.rodata :\n\t{\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(8);\n\t} :rodata\n\n\t.eh_frame_hdr     : { __eh_frame_hdr_start = .; *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) __eh_frame_hdr_end = .; } :rodata\n\t.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata\n\t.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata\n\t.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata\n\n\t.dynamic           : { *(.dynamic) } :rodata :dyn\n\t.dynsym            : { *(.dynsym) } :rodata\n\t.dynstr            : { *(.dynstr) } :rodata\n\t.rela.dyn          : { *(.rela.*) } :rodata\n\t.interp            : { *(.interp) } :rodata\n\t.hash              : { *(.hash) } :rodata\n\t.gnu.hash          : { *(.gnu.hash) } :rodata\n\t.gnu.version       : { *(.gnu.version) } :rodata\n\t.gnu.version_d     : { *(.gnu.version_d) } :rodata\n\t.gnu.version_r     : { *(.gnu.version_r) } :rodata\n\t.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata\n\n\t\/* =========== DATA section =========== *\/\n\t. = ALIGN(0x1000);\n\t__data_start = . ;\n\n\t.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data\n\t.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data\n\t.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data\n\t.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data\n\n\t.tdata ALIGN(8) :\n\t{\n\t\t__tdata_lma = .;\n\t\t*(.tdata .tdata.* .gnu.linkonce.td.*)\n\t\t. = ALIGN(8);\n\t\t__tdata_lma_end = .;\n\t} :data\n\n\t.tbss ALIGN(8) :\n\t{\n\t\t*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)\n\t\t. = ALIGN(8);\n\t} :data\n\n\t.preinit_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\t} :data\n\n\t.init_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__init_array_start = .);\n\t\tKEEP( *(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)) )\n\t\tKEEP( *(.init_array .ctors) )\n\t\tPROVIDE (__init_array_end = .);\n\t} :data\n\n\t.fini_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__fini_array_start = .);\n\t\tKEEP( *(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)) )\n\t\tKEEP( *(.fini_array .dtors) )\n\t\tPROVIDE (__fini_array_end = .);\n\t} :data\n\n\t__got_start__ = .;\n\n\t.got            : { *(.got) *(.igot) } :data\n\t.got.plt        : { *(.got.plt)  *(.igot.plt) } :data\n\n\t__got_end__ = .;\n\n\t.data ALIGN(8) :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tSORT(CONSTRUCTORS)\n\t} :data\n\n\t__bss_start__ = .;\n\t.bss ALIGN(8) :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\n\t\t\/* Reserve space for the TLS segment of the main thread *\/\n\t\t__tls_start = .;\n\t\t. += + SIZEOF(.tdata) + SIZEOF(.tbss);\n\t\t__tls_end = .;\n\t} : data\n\t__bss_end__ = .;\n\n\t__end__ = ABSOLUTE(.) ;\n\n\t. = ALIGN(0x1000);\n\t__argdata__ = ABSOLUTE(.) ;\n\n\t\/* ==================\n\t   ==== Metadata ====\n\t   ================== *\/\n\n\t\/* Discard sections that difficult post-processing *\/\n\t\/DISCARD\/ : { *(.group .comment .note) }\n\n\t\/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n}\n","old_contents":"OUTPUT_ARCH(aarch64)\nENTRY(_start)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(5) \/* Read | Execute *\/;\n\trodata PT_LOAD FLAGS(4) \/* Read *\/;\n\tdata   PT_LOAD FLAGS(6) \/* Read | Write *\/;\n\tdyn    PT_DYNAMIC;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\tPROVIDE(__start__ = 0x0);\n\t. = __start__;\n\t__code_start = . ;\n\n\t.crt0 :\n\t{\n\t\tKEEP (*(.crt0))\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.init :\n\t{\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.plt :\n\t{\n\t\t*(.plt)\n\t\t*(.iplt)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.text :\n\t{\n\t\t*(.text.unlikely .text.*_unlikely .text.unlikely.*)\n\t\t*(.text.exit .text.exit.*)\n\t\t*(.text.startup .text.startup.*)\n\t\t*(.text.hot .text.hot.*)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.fini :\n\t{\n\t\tKEEP( *(.fini) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t\/* =========== RODATA section =========== *\/\n\t. = ALIGN(0x1000);\n\t__rodata_start = . ;\n\n\t.nx-module-name : { KEEP (*(.nx-module-name)) } :rodata\n\n\t.rodata :\n\t{\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(8);\n\t} :rodata\n\n\t.eh_frame_hdr     : { __eh_frame_hdr_start = .; *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) __eh_frame_hdr_end = .; } :rodata\n\t.eh_frame         : ONLY_IF_RO { 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==================\n\t   ==== Metadata ====\n\t   ================== *\/\n\n\t\/* Discard sections that difficult post-processing *\/\n\t\/DISCARD\/ : { *(.group .comment .note) }\n\n\t\/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"9587977c8fa51fe917db7a17b9af94d27a6daae7","subject":"set fsmc sram region size in linker script","message":"set fsmc sram region size in linker script\n","repos":"chrisy\/freertos-test,chrisy\/freertos-test,chrisy\/freertos-test","old_file":"src\/platform\/STM32F103ZG.ld","new_file":"src\/platform\/STM32F103ZG.ld","new_contents":"\/** Linker script for STM32F103ZG\n * vim: set softtabstop=4 shiftwidth=4 tabstop=4 expandtab:\n * \\file src\/platform\/STM32F1032G.ld\n *\n * \\author Chris Luke <chrisy@flirble.org>\n * \\copyright Copyright (c) Chris Luke <chrisy@flirble.org>\n *\n * \\copyright This file is distributed under the terms of the MIT License.\n * See the LICENSE file at the top of this tree, or if it is missing a copy can\n * be found at http:\/\/opensource.org\/licenses\/MIT\n *\/\n\nMEMORY\n{\n    flash (rx)        : ORIGIN = 0x08000000, LENGTH = 1M\n    ram (rwx)         : ORIGIN = 0x20000000, LENGTH = 96K\n    stack (rw)        : ORIGIN = 0x20010000, LENGTH = 0K\n    fsmc_bank1 (rw)   : ORIGIN = 0x60000000, LENGTH = 256M \/* 256MB max *\/\n    fsmc_bank1_1 (rw) : ORIGIN = 0x60000000, LENGTH = 64M  \/* 64MB max *\/\n    fsmc_bank1_2 (rw) : ORIGIN = 0x64000000, LENGTH = 64M  \/* 64MB max *\/\n    fsmc_bank1_3 (rw) : ORIGIN = 0x68000000, LENGTH = 1M   \/* 64MB max *\/\n    fsmc_bank1_4 (rw) : ORIGIN = 0x6c000000, LENGTH = 64M  \/* 64MB max *\/\n    fsmc_bank2 (rw)   : ORIGIN = 0x70000000, LENGTH = 256M \/* 256MB max *\/\n    fsmc_bank3 (rw)   : ORIGIN = 0x80000000, LENGTH = 256M \/* 256MB max *\/\n    fsmc_bank4 (rw)   : ORIGIN = 0x90000000, LENGTH = 256M \/* 256MB max *\/\n}\n\nENTRY(_crt0_init)\n\nSECTIONS\n{\n    . = 0;\n\n    .nvic_vector :\n    {\n        *(vectors)  \/* Vector table *\/\n    } >flash\n\n    .info :\n    {\n        *(info)     \/* Text info *\/\n    } >flash\n\n    .text :\n    {\n        *(.text)    \/* Program code *\/\n        *(.text.*)\n        *(.rodata)  \/* Read only data *\/\n        *(.rodata.*)\n    } >flash\n\n    .data :\n    {\n        . = ALIGN(4);\n        _mm_data_start = .;\n        *(.data)    \/* Data memory *\/\n        *(.data.*)\n        . = ALIGN(4);\n        _mm_data_end = .;\n    } >ram AT >flash\n    _mm_datai_start = LOADADDR(.data);\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _mm_bss_start = .;\n        *(.bss)     \/* BSS is zero-filled at runtime *\/\n        *(.bss.*)\n        *(COMMON)\n        _mm_bss_end = .;\n    } >ram\n\n    .heap :\n    {\n        . = ALIGN(4);\n        _mm_heap_start = .;\n    } >ram\n\n    .stack :\n    {\n        _mm_heap_end = .;\n        _mm_stack_top = .;\n    } >stack\n\n    .fsmc_bank1 :\n    {\n        _fsmc_bank1_start = .;\n        *(.fsmc_bank1)\n        *(.fsmc_bank1.*)\n        _fsmc_bank1_end = .;\n    } >fsmc_bank1\n\n    .fsmc_bank1_1 :\n    {\n        _fsmc_bank1_1_start = .;\n        *(.fsmc_bank1_1)\n        *(.fsmc_bank1_1.*)\n        _fsmc_bank1_1_end = .;\n    } >fsmc_bank1_1\n\n    .fsmc_bank1_2 :\n    {\n        _fsmc_bank1_2_start = .;\n        *(.fsmc_bank1_2)\n        *(.fsmc_bank1_2.*)\n        _fsmc_bank1_2_end = .;\n    } >fsmc_bank1_2\n\n    .fsmc_bank1_3 :\n    {\n        _fsmc_bank1_3_start = .;\n        *(.fsmc_bank1_3)\n        *(.fsmc_bank1_3.*)\n        _fsmc_bank1_3_end = .;\n    } >fsmc_bank1_3\n\n    .fsmc_bank1_4 :\n    {\n        _fsmc_bank1_4_start = .;\n        *(.fsmc_bank1_4)\n        *(.fsmc_bank1_4.*)\n        _fsmc_bank1_4_end = .;\n    } >fsmc_bank1_4\n\n    .fsmc_bank2 :\n    {\n        _fsmc_bank2_start = .;\n        *(.fsmc_bank2)\n        *(.fsmc_bank2.*)\n        _fsmc_bank2_end = .;\n    } >fsmc_bank2\n\n    .fsmc_bank3 :\n    {\n        _fsmc_bank3_start = .;\n        *(.fsmc_bank3)\n        *(.fsmc_bank3.*)\n        _fsmc_bank3_end = .;\n    } >fsmc_bank3\n\n    .fsmc_bank4 :\n    {\n        _fsmc_bank4_start = .;\n        *(.fsmc_bank4)\n        *(.fsmc_bank4.*)\n        _fsmc_bank4_end = .;\n    } >fsmc_bank4\n\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n       Symbols in the DWARF debugging sections are relative to the beginning\n       of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end ) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n    \/* DWARF 3 *\/\n    .debug_pubtypes 0 : { *(.debug_pubtypes) }\n    .debug_ranges   0 : { *(.debug_ranges) }\n    \/* DWARF Extension.  *\/\n    .debug_macro    0 : { *(.debug_macro) }\n\n}\n\n","old_contents":"\/** Linker script for STM32F103ZG\n * vim: set softtabstop=4 shiftwidth=4 tabstop=4 expandtab:\n * \\file src\/platform\/STM32F1032G.ld\n *\n * \\author Chris Luke <chrisy@flirble.org>\n * \\copyright Copyright (c) Chris Luke <chrisy@flirble.org>\n *\n * \\copyright This file is distributed under the terms of the MIT License.\n * See the LICENSE file at the top of this tree, or if it is missing a copy can\n * be found at http:\/\/opensource.org\/licenses\/MIT\n *\/\n\nMEMORY\n{\n    flash (rx)        : ORIGIN = 0x08000000, LENGTH = 1M\n    ram (rwx)         : ORIGIN = 0x20000000, LENGTH = 96K\n    stack (rw)        : ORIGIN = 0x20010000, LENGTH = 0K\n    fsmc_bank1 (rw)   : ORIGIN = 0x60000000, LENGTH = 256M \/* 256MB max *\/\n    fsmc_bank1_1 (rw) : ORIGIN = 0x60000000, LENGTH = 64M  \/* 64MB max *\/\n    fsmc_bank1_2 (rw) : ORIGIN = 0x64000000, LENGTH = 64M  \/* 64MB max *\/\n    fsmc_bank1_3 (rw) : ORIGIN = 0x68000000, LENGTH = 64M  \/* 64MB max *\/\n    fsmc_bank1_4 (rw) : ORIGIN = 0x6c000000, LENGTH = 64M  \/* 64MB max *\/\n    fsmc_bank2 (rw)   : ORIGIN = 0x70000000, LENGTH = 256M \/* 256MB max *\/\n    fsmc_bank3 (rw)   : ORIGIN = 0x80000000, LENGTH = 256M \/* 256MB max *\/\n    fsmc_bank4 (rw)   : ORIGIN = 0x90000000, LENGTH = 256M \/* 256MB max *\/\n}\n\nENTRY(_crt0_init)\n\nSECTIONS\n{\n    . = 0;\n\n    .nvic_vector :\n    {\n        *(vectors)  \/* Vector table *\/\n    } >flash\n\n    .info :\n    {\n        *(info)     \/* Text info *\/\n    } >flash\n\n    .text :\n    {\n        *(.text)    \/* Program code *\/\n        *(.text.*)\n        *(.rodata)  \/* Read only data *\/\n        *(.rodata.*)\n    } >flash\n\n    .data :\n    {\n        . = ALIGN(4);\n        _mm_data_start = .;\n        *(.data)    \/* Data memory *\/\n        *(.data.*)\n        . = ALIGN(4);\n        _mm_data_end = .;\n    } >ram AT >flash\n    _mm_datai_start = LOADADDR(.data);\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _mm_bss_start = .;\n        *(.bss)     \/* BSS is zero-filled at runtime *\/\n        *(.bss.*)\n        *(COMMON)\n        _mm_bss_end = .;\n    } >ram\n\n    .heap :\n    {\n        . = ALIGN(4);\n        _mm_heap_start = .;\n    } >ram\n\n    .stack :\n    {\n        _mm_heap_end = .;\n        _mm_stack_top = .;\n    } >stack\n\n    .fsmc_bank1 :\n    {\n        _fsmc_bank1_start = .;\n        *(.fsmc_bank1)\n        *(.fsmc_bank1.*)\n        _fsmc_bank1_end = .;\n    } >fsmc_bank1\n\n    .fsmc_bank1_1 :\n    {\n        _fsmc_bank1_1_start = .;\n        *(.fsmc_bank1_1)\n        *(.fsmc_bank1_1.*)\n        _fsmc_bank1_1_end = .;\n    } >fsmc_bank1_1\n\n    .fsmc_bank1_2 :\n    {\n        _fsmc_bank1_2_start = .;\n        *(.fsmc_bank1_2)\n        *(.fsmc_bank1_2.*)\n        _fsmc_bank1_2_end = .;\n    } >fsmc_bank1_2\n\n    .fsmc_bank1_3 :\n    {\n        _fsmc_bank1_3_start = .;\n        *(.fsmc_bank1_3)\n        *(.fsmc_bank1_3.*)\n        _fsmc_bank1_3_end = .;\n    } >fsmc_bank1_3\n\n    .fsmc_bank1_4 :\n    {\n        _fsmc_bank1_4_start = .;\n        *(.fsmc_bank1_4)\n        *(.fsmc_bank1_4.*)\n        _fsmc_bank1_4_end = .;\n    } >fsmc_bank1_4\n\n    .fsmc_bank2 :\n    {\n        _fsmc_bank2_start = .;\n        *(.fsmc_bank2)\n        *(.fsmc_bank2.*)\n        _fsmc_bank2_end = .;\n    } >fsmc_bank2\n\n    .fsmc_bank3 :\n    {\n        _fsmc_bank3_start = .;\n        *(.fsmc_bank3)\n        *(.fsmc_bank3.*)\n        _fsmc_bank3_end = .;\n    } >fsmc_bank3\n\n    .fsmc_bank4 :\n    {\n        _fsmc_bank4_start = .;\n        *(.fsmc_bank4)\n        *(.fsmc_bank4.*)\n        _fsmc_bank4_end = .;\n    } >fsmc_bank4\n\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n       Symbols in the DWARF debugging sections are relative to the beginning\n       of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end ) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n    \/* DWARF 3 *\/\n    .debug_pubtypes 0 : { *(.debug_pubtypes) }\n    .debug_ranges   0 : { *(.debug_ranges) }\n    \/* DWARF Extension.  *\/\n    .debug_macro    0 : { *(.debug_macro) }\n\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"11070676d30bae3a36ee5e60ec2b787dfc6f58a3","subject":"fix in linker script","message":"fix in linker script\n","repos":"yhx189\/nautilus,yhx189\/nautilus,bradylee\/nautilus_fs,haiyang1992\/NautilusVirtio,haiyang1992\/NautilusVirtio,bradylee\/nautilus_fs,yhx189\/nautilus,bradylee\/nautilus_fs,haiyang1992\/NautilusVirtio","old_file":"nautilus.ld","new_file":"nautilus.ld","new_contents":"ENTRY(nautilus_entry)\n\nSECTIONS\n{\n    . = 0x100000;\n\n    .boot :\n    {\n        *(.mbhdr)\n        _loadStart = .;\n        *(.boot)\n        . = ALIGN(4096);\n        pml4 = .;\n        . += 0x1000;\n        pdpt = .;\n        . += 0x1000;\n        pd = .;\n        . += 0x1000; \n\n        \/* stack *\/\n        . += 0x4000;\n        boot_stack = .;\n        . += 0x1000; \/* TODO: remove this, for now to be safe... *\/\n    }\n\n\n    .text ALIGN(0x1000) : \n    {\n        *(.text*)\n        *(.gnu.linkonce.t*)\n    }\n\n    .init_array ALIGN(0x1000) : AT(ADDR(.text) + SIZEOF(.text))\n    {\n        *(.init_array*)\n        *(.gnu.linkonce.init_array*)\n    }\n\n\n    .gcc_except_table ALIGN(0x1000) : AT(ADDR(.init_array) + SIZEOF(.init_array))\n    {\n        *(.gcc_except_table*)\n        *(.gnu.linkonce.gcc_except*)\n    }\n    \n    .data ALIGN(0x1000) : AT(ADDR(.gcc_except_table) + SIZEOF(.gcc_except_table))\n    {\n        *(.data*)\n        *(.gnu.linkonce.d*)\n    }\n    \n    .rodata ALIGN(0x1000) : AT(ADDR(.data) + SIZEOF(.data))\n    {\n        *(.rodata*)\n        *(.gnu.linkonce.r*)\n    }\n    \n\n    .got ALIGN(0x1000) : AT(ADDR(.rodata)+SIZEOF(.rodata))\n    {\n        *(.got*)\n        *(.gnu.linkconce.got*)\n    }\n\n\n    _loadEnd = .; \n    \n    .bss ALIGN(0x1000) : AT(ADDR(.got)+SIZEOF(.got))\n    {\n        *(COMMON)\n        *(.bss*)\n        *(.gnu.linkonce.b*)\n    }\n    \n    _bssEnd = .; \n    \n    \/DISCARD\/ :\n    {\n        *(.comment)\n        *(.eh_frame)\n    }\n}\n\n","old_contents":"ENTRY(nautilus_entry)\n\nSECTIONS\n{\n    . = 0x100000;\n\n    .boot :\n    {\n        *(.mbhdr)\n        _loadStart = .;\n        *(.boot)\n        . = ALIGN(4096);\n        pml4 = .;\n        . += 0x1000;\n        pdpt = .;\n        . += 0x1000;\n        pd = .;\n        . += 0x1000; \n\n        \/* stack *\/\n        . += 0x4000;\n        boot_stack = .;\n        . += 0x1000; \/* TODO: remove this, for now to be safe... *\/\n    }\n\n\n    .text ALIGN(0x1000) : \n    {\n        *(.text*)\n        *(.gnu.linkonce.t*)\n    }\n\n    .init_array ALIGN(0x1000) : AT(ADDR(.text) + SIZEOF(.text))\n    {\n        *(.init_array*)\n        *(.gnu.linkonce.init_array*)\n    }\n\n\n    .gcc_except_table ALIGN(0x1000) : AT(ADDR(.init_array) + SIZEOF(.init_array))\n    {\n        *(.gcc_except_table*)\n        *(.gnu.linkonce.gcc_except*)\n    }\n    \n    .data ALIGN(0x1000) : AT(ADDR(.gcc_except_table) + SIZEOF(.gcc_except_table))\n    {\n        *(.data*)\n        *(.gnu.linkonce.d*)\n    }\n    \n    .rodata ALIGN(0x1000) : AT(ADDR(.data) + SIZEOF(.data))\n    {\n        *(.rodata*)\n        *(.gnu.linkonce.r*)\n    }\n    \n\n    .got ALIGN(0x1000) : AT(ADDR(.rodata)+SIZEOF(.rodata))\n    {\n        *(.got*)\n        *(.gnu.linkconce.got*)\n    }\n\n\n    _loadEnd = .; \n    \n    .bss ALIGN(0x1000) : AT(ADDR(.rodata)+SIZEOF(.rodata))\n    {\n        *(COMMON)\n        *(.bss*)\n        *(.gnu.linkonce.b*)\n    }\n    \n    _bssEnd = .; \n    \n    \/DISCARD\/ :\n    {\n        *(.comment)\n        *(.eh_frame)\n    }\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c30f48c3b1c83ce5d4d00c8e1af13f5c27880d25","subject":"Fix linker script handling of irom\/irom0 segments","message":"Fix linker script handling of irom\/irom0 segments\n","repos":"mr-nice\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,andree182\/esp-open-rtos,Angus71\/esp-open-rtos,UncleRus\/esp-open-rtos,foogod\/esp-open-rtos,kamejoko80\/esp-open-rtos,UncleRus\/esp-open-rtos,someburner\/esp-rtos-tests,mr-nice\/esp-open-rtos,UncleRus\/esp-open-rtos,someburner\/esp-rtos-tests,ourairquality\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,urx\/esp-open-rtos,andree182\/esp-open-rtos,SuperHouse\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,ourairquality\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,sheinz\/esp-open-rtos,andree182\/esp-open-rtos,jaeh\/esp-open-rtos,Zaltora\/esp-open-rtos,DCoJA\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,kamejoko80\/esp-open-rtos,andree182\/esp-open-rtos,Angus71\/esp-open-rtos,urx\/esp-open-rtos,kanflo\/esp-open-rtos,ourairquality\/esp-open-rtos,UncleRus\/esp-open-rtos,gpascualg\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,kanflo\/esp-open-rtos,yesco\/esp-open-rtos,Zaltora\/esp-open-rtos,SuperHouse\/esp-open-rtos,hawkhsieh\/esp-open-rtos,sheinz\/esp-open-rtos,urx\/esp-open-rtos,alainmaes\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,DCoJA\/esp-open-rtos,jaeh\/esp-open-rtos,kanflo\/esp-open-rtos,UncleRus\/esp-open-rtos,DCoJA\/esp-open-rtos,sheinz\/esp-open-rtos,mr-nice\/esp-open-rtos,urx\/esp-open-rtos,Zaltora\/esp-open-rtos,DCoJA\/esp-open-rtos,yesco\/esp-open-rtos,UncleRus\/esp-open-rtos,hawkhsieh\/esp-open-rtos,someburner\/esp-rtos-tests,Zaltora\/esp-open-rtos,someburner\/esp-rtos-tests,kanflo\/esp-open-rtos,SuperHouse\/esp-open-rtos,ourairquality\/esp-open-rtos,urx\/esp-open-rtos,Zaltora\/esp-open-rtos,sheinz\/esp-open-rtos,hawkhsieh\/esp-open-rtos,foogod\/esp-open-rtos,kanflo\/esp-open-rtos,SuperHouse\/esp-open-rtos,hawkhsieh\/esp-open-rtos,gpascualg\/esp-open-rtos,kanflo\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,SuperHouse\/esp-open-rtos,gpascualg\/esp-open-rtos,urx\/esp-open-rtos,alainmaes\/esp-open-rtos,ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos,foogod\/esp-open-rtos,mr-nice\/esp-open-rtos,alainmaes\/esp-open-rtos,SuperHouse\/esp-open-rtos,alainmaes\/esp-open-rtos,Zaltora\/esp-open-rtos","old_file":"ld\/eagle.app.v6.ld","new_file":"ld\/eagle.app.v6.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP .\n\n   Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one.\n*\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* FreeRTOS lock functions.\n\n   Rely on a patch to libc that produces weak linked versions of the\n   below symbols. Currently treating locking primitives like universal\n   global critical section rather than individual locks, but this seems\n   OK from the use cases in newlib.\n*\/\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\n\/* Evaluate FLASH_SIZE to calculate irom size, etc.\n*\/\n#ifndef OTA\n\n#define IROM0_START 0x40240000\n\n\/* Non-OTA sizes *\/\n#if FLASH_SIZE == 2 \/* 256kB *\/\n#define IROM0_LEN 0x3C000\n#elif FLASH_SIZE == 4 \/* 512kB *\/\n#define IROM0_LEN 0x7C000\n#elif FLASH_SIZE == 8 \/* 1MB *\/\n#define IROM0_LEN 0xFC000\n#elif FLASH_SIZE == 16 \/* 2MB *\/\n#define IROM0_LEN 0x1FC000\n#elif FLASH_SIZE == 32 \/* 4MB *\/\n#define IROM0_LEN 0x3FC000\n#else \/*FLASH_SIZE*\/\n#error \"Unknown flash size for linker script. Check the FLASH_SIZE variable in your Makefile.\"\n#endif\n\n#else \/* OTA *\/\n\n\/* IROM0 becomes an actual \"section\" of the bootloader image, so we need to leave\n   space for the bootloader (0x2000 bytes) and space for the bootloader & section\n   headers (0x10 bytes)\n*\/\n#define IROM0_START 0x40202010\n\n\/* OTA sizes *\/\n#if FLASH_SIZE < 16\n#error \"OTA support currently requires 16 or 32 megabit flash\"\n#elif FLASH_SIZE == 16 || FLASH_SIZE == 32\n\/* 1MB irom0 section regardless, minus the space for the bootloader *\/\n#define IROM0_LEN (0x100000 - 0x2010)\n#else \/*FLASH_SIZE*\/\n#error \"Unknown flash size for linker script. Check the FLASH_SIZE variable in your Makefile.\"\n#endif\n\n#endif\n\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x08000\n  irom0_0_seg :                       \torg = IROM0_START, len = IROM0_LEN\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    . = ALIGN (16);\n    *(.vecbase.text)\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* esp-open-rtos compiled source files use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *sdklib*:*(.literal .text .literal.* .text.*)\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    \/* xthal_set_intset() called from PendSV in NMI context *\/\n    *libhal.a:*set_intset.o(.literal .text .literal.* .text.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    \/* esp-open-rtos compiled code goes into IROM by default\n       (except for libgcc which is matched above.)\n    *\/\n    *(.literal .text .literal.* .text.*)\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom.* .irom.*.* .irom0.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP .\n\n   Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one.\n*\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* FreeRTOS lock functions.\n\n   Rely on a patch to libc that produces weak linked versions of the\n   below symbols. Currently treating locking primitives like universal\n   global critical section rather than individual locks, but this seems\n   OK from the use cases in newlib.\n*\/\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\n\/* Evaluate FLASH_SIZE to calculate irom size, etc.\n*\/\n#ifndef OTA\n\n#define IROM0_START 0x40240000\n\n\/* Non-OTA sizes *\/\n#if FLASH_SIZE == 2 \/* 256kB *\/\n#define IROM0_LEN 0x3C000\n#elif FLASH_SIZE == 4 \/* 512kB *\/\n#define IROM0_LEN 0x7C000\n#elif FLASH_SIZE == 8 \/* 1MB *\/\n#define IROM0_LEN 0xFC000\n#elif FLASH_SIZE == 16 \/* 2MB *\/\n#define IROM0_LEN 0x1FC000\n#elif FLASH_SIZE == 32 \/* 4MB *\/\n#define IROM0_LEN 0x3FC000\n#else \/*FLASH_SIZE*\/\n#error \"Unknown flash size for linker script. Check the FLASH_SIZE variable in your Makefile.\"\n#endif\n\n#else \/* OTA *\/\n\n\/* IROM0 becomes an actual \"section\" of the bootloader image, so we need to leave\n   space for the bootloader (0x2000 bytes) and space for the bootloader & section\n   headers (0x10 bytes)\n*\/\n#define IROM0_START 0x40202010\n\n\/* OTA sizes *\/\n#if FLASH_SIZE < 16\n#error \"OTA support currently requires 16 or 32 megabit flash\"\n#elif FLASH_SIZE == 16 || FLASH_SIZE == 32\n\/* 1MB irom0 section regardless, minus the space for the bootloader *\/\n#define IROM0_LEN (0x100000 - 0x2010)\n#else \/*FLASH_SIZE*\/\n#error \"Unknown flash size for linker script. Check the FLASH_SIZE variable in your Makefile.\"\n#endif\n\n#endif\n\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x08000\n  irom0_0_seg :                       \torg = IROM0_START, len = IROM0_LEN\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    . = ALIGN (16);\n    *(.vecbase.text)\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* esp-open-rtos compiled source files use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *sdklib*:*(.literal .text .literal.* .text.*)\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    \/* xthal_set_intset() called from PendSV in NMI context *\/\n    *libhal.a:*set_intset.o(.literal .text .literal.* .text.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    \/* esp-open-rtos compiled code goes into IROM by default\n       (except for libgcc which is matched above.)\n    *\/\n    *(.literal .text .literal.* .text.*)\n    \/* SDK libraries expect ICACHE_FLASH_ATTR\/etc functions to be loaded explicitly as IROM *\/\n    *sdklib*:*(.irom.* .irom.*.* .irom0.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"a62db23626ea2f98d3bc3ce6506ce8cbb14c09b1","subject":"Fix nodemcu.ld (#2762)","message":"Fix nodemcu.ld (#2762)\n\n","repos":"eku\/nodemcu-firmware,vsky279\/nodemcu-firmware,vsky279\/nodemcu-firmware,nodemcu\/nodemcu-firmware,TerryE\/nodemcu-firmware,FelixPe\/nodemcu-firmware,nodemcu\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,FelixPe\/nodemcu-firmware,TerryE\/nodemcu-firmware,TerryE\/nodemcu-firmware,eku\/nodemcu-firmware,nwf\/nodemcu-firmware,TerryE\/nodemcu-firmware,FelixPe\/nodemcu-firmware,nwf\/nodemcu-firmware,nwf\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,eku\/nodemcu-firmware,vsky279\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,FelixPe\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,eku\/nodemcu-firmware,nodemcu\/nodemcu-firmware,vsky279\/nodemcu-firmware,nodemcu\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,nodemcu\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,TerryE\/nodemcu-firmware,nwf\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,vsky279\/nodemcu-firmware,FelixPe\/nodemcu-firmware,nwf\/nodemcu-firmware","old_file":"ld\/nodemcu.ld","new_file":"ld\/nodemcu.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  iram0_0_seg :                         org = 0x4010E000, len = 0x2000\n  irom0_0_seg :                         org = 0x40210000, len = 0xE0000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n   \/*\n    * SDK libraries that used in bootup process, interruption handling\n    * and other ways where flash cache (iROM) is unavailable:\n    *\/\n    *libmain.a:*(    .literal .literal.* .text .text.*)\n    *libphy.a:*(     .literal .literal.* .text .text.*)\n    *libpp.a:*(      .literal .literal.* .text .text.*)\n    *libgcc.a:*(     .literal .literal.* .text .text.*)\n    *libnet80211.a:*(.literal            .text        )\n   \/*\n    * The following SDK libraries have .literal and .text sections, but are\n    * either not used in NodeMCU or are safe to execute out of in iROM: \n    *   libat.a libcrypto.a libdriver.a libnet80211.a libespnow.a\n    *   liblwip_536.a ibpwm.a libwpa.a ibwps.a\n    *\/\n    *(.iram.text .iram0.text .iram0.text.*)\n    *(.iram0.data.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    *(.rodata.dram .rodata.dram*)\n\n    *(.gnu.linkonce.r.*)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    *(.noinit)\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .pre_init_ram : ALIGN(0x1000)\n  {\n    _iram0_start = ABSOLUTE(.);\n    *(*.pre_init)\n    _iram0_end = ABSOLUTE(.);\n  } >iram0_0_seg :iram0_0_phdr\n\n  .irom0.text : ALIGN(0x1000)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    KEEP(*(.irom0.ptable))\n    . = ALIGN(0x1000);\n    *(.servercert.flash)\n    *(.clientcert.flash)\n    . = ALIGN(0x1000);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal .text .literal.* .text.*)\n    *(.rodata*)\n    *(.sdk.version)\n\n    \/* Link-time arrays containing the defs for the included modules *\/\n    . = ALIGN(4);\n    lua_libs_base = ABSOLUTE(.);\n    \/* Allow either empty define or defined-to-1 to include the module *\/\n    KEEP(*(.lua_libs))\n    LONG(0) LONG(0) \/* Null-terminate the array *\/\n    lua_rotable_base = ABSOLUTE(.);\n    KEEP(*(.lua_rotable))\n    LONG(0) LONG(0) \/* Null-terminate the array *\/\n\n    \/* SDK doesn't use libc functions, and are therefore safe to put in flash *\/\n    *\/libc.a:*.o(.text* .literal*)\n    \/* end libc functions *\/\n\n    \/* Reserved areas, flash page aligned and last *\/\n    . = ALIGN(4096);\n\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_used_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr =0xffffffff\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  iram0_0_seg :                         org = 0x4010E000, len = 0x2000\n  irom0_0_seg :                         org = 0x40210000, len = 0xE0000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n   \/*\n    * SDK libraries that used in bootup process, interruption handling\n    * and other ways where flash cache (iROM) is unavailable:\n    *\/\n    *libmain.a:*(    .literal .literal.* .text .text.*)\n    *libphy.a:*(     .literal .literal.* .text .text.*)\n    *libpp.a:*(      .literal .literal.* .text .text.*)\n    *libgcc.a:*(     .literal .literal.* .text .text.*)\n   \/*\n    * The following SDK libraries have .literal and .text sections, but are\n    * either not used in NodeMCU or are safe to execute out of in iROM: \n    *   libat.a libcrypto.a libdriver.a libnet80211.a libespnow.a\n    *   liblwip_536.a ibpwm.a libwpa.a ibwps.a\n    *\/\n    *(.iram.text .iram0.text .iram0.text.*)\n    *(.iram0.data.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    *(.rodata.dram .rodata.dram*)\n\n    *(.gnu.linkonce.r.*)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    *(.noinit)\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .pre_init_ram : ALIGN(0x1000)\n  {\n    _iram0_start = ABSOLUTE(.);\n    *(*.pre_init)\n    _iram0_end = ABSOLUTE(.);\n  } >iram0_0_seg :iram0_0_phdr\n\n  .irom0.text : ALIGN(0x1000)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    KEEP(*(.irom0.ptable))\n    . = ALIGN(0x1000);\n    *(.servercert.flash)\n    *(.clientcert.flash)\n    . = ALIGN(0x1000);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal .text .literal.* .text.*)\n    *(.rodata*)\n    *(.sdk.version)\n\n    \/* Link-time arrays containing the defs for the included modules *\/\n    . = ALIGN(4);\n    lua_libs_base = ABSOLUTE(.);\n    \/* Allow either empty define or defined-to-1 to include the module *\/\n    KEEP(*(.lua_libs))\n    LONG(0) LONG(0) \/* Null-terminate the array *\/\n    lua_rotable_base = ABSOLUTE(.);\n    KEEP(*(.lua_rotable))\n    LONG(0) LONG(0) \/* Null-terminate the array *\/\n\n    \/* SDK doesn't use libc functions, and are therefore safe to put in flash *\/\n    *\/libc.a:*.o(.text* .literal*)\n    \/* end libc functions *\/\n\n    \/* Reserved areas, flash page aligned and last *\/\n    . = ALIGN(4096);\n\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_used_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr =0xffffffff\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3a10f81eaca273e79a3c5c7e24182c42bfc1d00d","subject":"gcc_arm.ld: remove GROUP command","message":"gcc_arm.ld: remove GROUP command\n\nThis looked odd before since one might be using nano (libc_s.a) and not\nlinking newlib's conception of nosys.  Here's ek-tm4c123gxl nop with the\noriginal:\n\n   text    data     bss     dec     hex filename\n   1920    1080      28    3028     bd4 app.axf\n\nAnd here it is with the GROUP command removed:\n\n   text    data     bss     dec     hex filename\n   1324     112      28    1464     5b8 app.axf\n\ngithub: fixes #4\n","repos":"pabigot\/bspacm,pabigot\/bspacm,pabigot\/bspacm,pabigot\/bspacm","old_file":"toolchain\/GCC\/gcc_arm.ld","new_file":"toolchain\/GCC\/gcc_arm.ld","new_contents":"\/* From CMSIS 4.00 specification CMSIS-SP-00300-r4p0-00rel0.zip\n * !! MODIFIED to support BSPACM (http:\/\/github.com\/pabigot\/bspacm)\n * - Use external memory.ld instead of hard-coding constants\n * - Remove GROUP command with hard-coded library list\n *\/\n\n\/* Include the device-specific memory map.  Pass\n * -L$(DEVICE_LDSCRIPT_PATH) to ld so the right one is located. *\/\nINCLUDE memory.ld\n\n\/* Library configurations *\/\n\/* !!REMOVED: GROUP(libgcc.a libc.a libm.a libnosys.a)\n * These may not be the libraries we're using, and they force\n * inclusion of impure_data and other material sucking up\n * over 1 kB RAM *\/\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* From CMSIS 4.00 specification CMSIS-SP-00300-r4p0-00rel0.zip\n * !! MODIFIED to support BSPACM (http:\/\/github.com\/pabigot\/bspacm)\n *\/\n\n\/* Include the device-specific memory map.  Pass\n * -L$(DEVICE_LDSCRIPT_PATH) to ld so the right one is located. *\/\nINCLUDE memory.ld\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"bd521f09fb829363db53040218f374412b7cb340","subject":"Add .data and .bss to the linker","message":"Add .data and .bss to the linker\n","repos":"jvns\/puddle,jvns\/puddle","old_file":"src\/linker.ld","new_file":"src\/linker.ld","new_contents":"ENTRY(start)\nOUTPUT_FORMAT(binary)\n\nSECTIONS {\n  . = 0x7e00;\n  .text : {\n    *(.text)\n  }\n\n  .data : {\n    *(.data .rodata)\n  }\n\n  .bss : {\n    *(.bss*);\n  }\n }\n","old_contents":"ENTRY(start)\nOUTPUT_FORMAT(binary)\n\nSECTIONS {\n    . = 0x7e00;\n\n    .text : {\n        *(.text)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"194c8c761e853cb200d5aab885b6d62ec87cf4b2","subject":"cc3200: Increment interrupt stack size from 2K to 3K.","message":"cc3200: Increment interrupt stack size from 2K to 3K.\n","repos":"puuu\/micropython,feilongfl\/micropython,lowRISC\/micropython,heisewangluo\/micropython,SHA2017-badge\/micropython-esp32,firstval\/micropython,kerneltask\/micropython,tuc-osg\/micropython,AriZuu\/micropython,suda\/micropython,ryannathans\/micropython,selste\/micropython,matthewelse\/micropython,pfalcon\/micropython,pramasoul\/micropython,matthewelse\/micropython,MrSurly\/micropython-esp32,micropython\/micropython-esp32,blmorris\/micropython,ericsnowcurrently\/micropython,heisewangluo\/micropython,supergis\/micropython,cloudformdesign\/micropython,dhylands\/micropython,alex-robbins\/micropython,ChuckM\/micropython,trezor\/micropython,lowRISC\/micropython,Peetz0r\/micropython-esp32,ahotam\/micropython,Timmenem\/micropython,chrisdearman\/micropython,ceramos\/micropython,heisewangluo\/micropython,neilh10\/micropython,supergis\/micropython,PappaPeppar\/micropython,PappaPeppar\/micropython,ceramos\/micropython,suda\/micropython,mgyenik\/micropython,vriera\/micropython,trezor\/micropython,suda\/micropython,lbattraw\/micropython,turbinenreiter\/micropython,cwyark\/micropython,turbinenreiter\/micropython,selste\/micropython,utopiaprince\/micropython,emfcamp\/micropython,henriknelson\/micropython,tobbad\/micropython,oopy\/micropython,alex-march\/micropython,kerneltask\/micropython,dhylands\/micropython,rubencabrera\/micropython,adafruit\/micropython,ceramos\/micropython,AriZuu\/micropython,noahchense\/micropython,vriera\/micropython,dhylands\/micropython,firstval\/micropython,EcmaXp\/micropython,utopiaprince\/micropython,dmazzella\/micropython,praemdonck\/micropython,dxxb\/micropython,swegener\/micropython,dmazzella\/micropython,mpalomer\/micropython,bvernoux\/micropython,blmorris\/micropython,omtinez\/micropython,alex-march\/micropython,ganshun666\/micropython,pozetroninc\/micropython,deshipu\/micropython,galenhz\/micropython,noahwilliamsson\/micropython,martinribelotta\/micropython,noahchense\/micropython,ryannathans\/micropython,vitiral\/micropython,ericsnowcurrently\/micropython,ericsnowcurrently\/micropython,tdautc19841202\/micropython,jlillest\/micropython,xhat\/micropython,blazewicz\/micropython,rubencabrera\/micropython,tobbad\/micropython,henriknelson\/micropython,alex-march\/micropython,dmazzella\/micropython,mhoffma\/micropython,mpalomer\/micropython,Peetz0r\/micropython-esp32,hosaka\/micropython,utopiaprince\/micropython,orionrobots\/micropython,omtinez\/micropython,cnoviello\/micropython,hiway\/micropython,xyb\/micropython,kerneltask\/micropython,ganshun666\/micropython,redbear\/micropython,stonegithubs\/micropython,galenhz\/micropython,lowRISC\/micropython,torwag\/micropython,alex-robbins\/micropython,pramasoul\/micropython,cnoviello\/micropython,mpalomer\/micropython,ernesto-g\/micropython,trezor\/micropython,jmarcelino\/pycom-micropython,orionrobots\/micropython,redbear\/micropython,pramasoul\/micropython,adafruit\/micropython,xyb\/micropython,heisewangluo\/micropython,martinribelotta\/micropython,stonegithubs\/micropython,mgyenik\/micropython,pramasoul\/micropython,cwyark\/micropython,MrSurly\/micropython,alex-robbins\/micropython,mianos\/micropython,orionrobots\/micropython,mgyenik\/micropython,supergis\/micropython,Timmenem\/micropython,noahwilliamsson\/micropython,AriZuu\/micropython,skybird6672\/micropython,adamkh\/micropython,oopy\/micropython,torwag\/micropython,adafruit\/circuitpython,Timmenem\/micropython,alex-robbins\/micropython,adafruit\/circuitpython,drrk\/micropython,adafruit\/micropython,tuc-osg\/micropython,skybird6672\/micropython,hiway\/micropython,ryannathans\/micropython,tuc-osg\/micropython,ruffy91\/micropython,trezor\/micropython,orionrobots\/micropython,tralamazza\/micropython,swegener\/micropython,chrisdearman\/micropython,dxxb\/micropython,puuu\/micropython,dinau\/micropython,ganshun666\/micropython,SHA2017-badge\/micropython-esp32,toolmacher\/micropython,micropython\/micropython-esp32,ernesto-g\/micropython,torwag\/micropython,danicampora\/micropython,cloudformdesign\/micropython,cwyark\/micropython,EcmaXp\/micropython,jmarcelino\/pycom-micropython,dhylands\/micropython,tralamazza\/micropython,alex-robbins\/micropython,rubencabrera\/micropython,pfalcon\/micropython,adamkh\/micropython,mpalomer\/micropython,martinribelotta\/micropython,feilongfl\/micropython,EcmaXp\/micropython,TDAbboud\/micropython,bvernoux\/micropython,deshipu\/micropython,henriknelson\/micropython,pozetroninc\/micropython,HenrikSolver\/micropython,puuu\/micropython,MrSurly\/micropython,tralamazza\/micropython,pfalcon\/micropython,jmarcelino\/pycom-micropython,blmorris\/micropython,Timmenem\/micropython,galenhz\/micropython,cloudformdesign\/micropython,utopiaprince\/micropython,ruffy91\/micropython,puuu\/micropython,blazewicz\/micropython,misterdanb\/micropython,misterdanb\/micropython,toolmacher\/micropython,mianos\/micropython,infinnovation\/micropython,xhat\/micropython,infinnovation\/micropython,ChuckM\/micropython,ChuckM\/micropython,pozetroninc\/micropython,Timmenem\/micropython,redbear\/micropython,vriera\/micropython,kostyll\/micropython,skybird6672\/micropython,ChuckM\/micropython,dhylands\/micropython,cwyark\/micropython,MrSurly\/micropython-esp32,ganshun666\/micropython,xuxiaoxin\/micropython,ruffy91\/micropython,mianos\/micropython,feilongfl\/micropython,MrSurly\/micropython-esp32,hosaka\/micropython,noahwilliamsson\/micropython,drrk\/micropython,bvernoux\/micropython,MrSurly\/micropython,lbattraw\/micropython,henriknelson\/micropython,selste\/micropython,ceramos\/micropython,HenrikSolver\/micropython,cwyark\/micropython,TDAbboud\/micropython,noahwilliamsson\/micropython,kerneltask\/micropython,dxxb\/micropython,feilongfl\/micropython,tdautc19841202\/micropython,EcmaXp\/micropython,lbattraw\/micropython,vitiral\/micropython,dinau\/micropython,orionrobots\/micropython,matthewelse\/micropython,xyb\/micropython,deshipu\/micropython,xhat\/micropython,MrSurly\/micropython-esp32,stonegithubs\/micropython,firstval\/micropython,xuxiaoxin\/micropython,tralamazza\/micropython,xuxiaoxin\/micropython,vitiral\/micropython,ahotam\/micropython,tuc-osg\/micropython,toolmacher\/micropython,oopy\/micropython,hosaka\/micropython,hiway\/micropython,alex-march\/micropython,praemdonck\/micropython,swegener\/micropython,mgyenik\/micropython,emfcamp\/micropython,vriera\/micropython,xyb\/micropython,rubencabrera\/micropython,mianos\/micropython,kostyll\/micropython,ericsnowcurrently\/micropython,pramasoul\/micropython,swegener\/micropython,dxxb\/micropython,dinau\/micropython,ahotam\/micropython,redbear\/micropython,drrk\/micropython,supergis\/micropython,lbattraw\/micropython,chrisdearman\/micropython,dinau\/micropython,danicampora\/micropython,cloudformdesign\/micropython,stonegithubs\/micropython,torwag\/micropython,micropython\/micropython-esp32,omtinez\/micropython,infinnovation\/micropython,kerneltask\/micropython,suda\/micropython,vitiral\/micropython,adafruit\/circuitpython,adamkh\/micropython,neilh10\/micropython,galenhz\/micropython,torwag\/micropython,xuxiaoxin\/micropython,mhoffma\/micropython,xyb\/micropython,lowRISC\/micropython,infinnovation\/micropython,adafruit\/circuitpython,chrisdearman\/micropython,selste\/micropython,MrSurly\/micropython,chrisdearman\/micropython,blmorris\/micropython,blazewicz\/micropython,oopy\/micropython,Peetz0r\/micropython-esp32,matthewelse\/micropython,noahchense\/micropython,tdautc19841202\/micropython,deshipu\/micropython,jlillest\/micropython,EcmaXp\/micropython,ahotam\/micropython,adamkh\/micropython,turbinenreiter\/micropython,turbinenreiter\/micropython,henriknelson\/micropython,jlillest\/micropython,puuu\/micropython,toolmacher\/micropython,pfalcon\/micropython,HenrikSolver\/micropython,SHA2017-badge\/micropython-esp32,mhoffma\/micropython,tdautc19841202\/micropython,adafruit\/circuitpython,PappaPeppar\/micropython,firstval\/micropython,martinribelotta\/micropython,xhat\/micropython,tobbad\/micropython,ruffy91\/micropython,stonegithubs\/micropython,danicampora\/micropython,hosaka\/micropython,kostyll\/micropython,cnoviello\/micropython,blazewicz\/micropython,mhoffma\/micropython,hiway\/micropython,dmazzella\/micropython,supergis\/micropython,misterdanb\/micropython,pfalcon\/micropython,SHA2017-badge\/micropython-esp32,jmarcelino\/pycom-micropython,praemdonck\/micropython,utopiaprince\/micropython,neilh10\/micropython,redbear\/micropython,ernesto-g\/micropython,toolmacher\/micropython,emfcamp\/micropython,mgyenik\/micropython,selste\/micropython,oopy\/micropython,PappaPeppar\/micropython,mianos\/micropython,ChuckM\/micropython,suda\/micropython,HenrikSolver\/micropython,adafruit\/circuitpython,ahotam\/micropython,emfcamp\/micropython,tobbad\/micropython,lbattraw\/micropython,swegener\/micropython,neilh10\/micropython,mhoffma\/micropython,Peetz0r\/micropython-esp32,cnoviello\/micropython,noahchense\/micropython,galenhz\/micropython,adafruit\/micropython,dinau\/micropython,MrSurly\/micropython-esp32,pozetroninc\/micropython,firstval\/micropython,tdautc19841202\/micropython,MrSurly\/micropython,alex-march\/micropython,blazewicz\/micropython,vriera\/micropython,jlillest\/micropython,jlillest\/micropython,tuc-osg\/micropython,skybird6672\/micropython,praemdonck\/micropython,turbinenreiter\/micropython,xuxiaoxin\/micropython,ryannathans\/micropython,ganshun666\/micropython,skybird6672\/micropython,tobbad\/micropython,PappaPeppar\/micropython,ceramos\/micropython,micropython\/micropython-esp32,omtinez\/micropython,omtinez\/micropython,heisewangluo\/micropython,praemdonck\/micropython,dxxb\/micropython,SHA2017-badge\/micropython-esp32,martinribelotta\/micropython,hosaka\/micropython,feilongfl\/micropython,ernesto-g\/micropython,adamkh\/micropython,kostyll\/micropython,AriZuu\/micropython,neilh10\/micropython,danicampora\/micropython,blmorris\/micropython,pozetroninc\/micropython,TDAbboud\/micropython,matthewelse\/micropython,bvernoux\/micropython,kostyll\/micropython,TDAbboud\/micropython,emfcamp\/micropython,bvernoux\/micropython,ryannathans\/micropython,trezor\/micropython,noahchense\/micropython,xhat\/micropython,micropython\/micropython-esp32,drrk\/micropython,danicampora\/micropython,mpalomer\/micropython,cnoviello\/micropython,jmarcelino\/pycom-micropython,adafruit\/micropython,AriZuu\/micropython,matthewelse\/micropython,misterdanb\/micropython,noahwilliamsson\/micropython,vitiral\/micropython,deshipu\/micropython,ericsnowcurrently\/micropython,ernesto-g\/micropython,hiway\/micropython,misterdanb\/micropython,infinnovation\/micropython,drrk\/micropython,rubencabrera\/micropython,lowRISC\/micropython,ruffy91\/micropython,cloudformdesign\/micropython,TDAbboud\/micropython,HenrikSolver\/micropython,Peetz0r\/micropython-esp32","old_file":"cc3200\/application.lds","new_file":"cc3200\/application.lds","new_contents":"\/*\n * This file is part of the Micro Python project, http:\/\/micropython.org\/\n *\n * The MIT License (MIT)\n *\n * Copyright (c) 2015 Daniel Campora\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\/\n\n__stack_size__    = 3K;       \/* interrupts are handled within this stack *\/\n__min_heap_size__ = 8K;\n\nMEMORY\n{\n    SRAMB (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000\n    SRAM  (rwx) : ORIGIN = 0x20004000, LENGTH = 0x0003C000\n}\n\nENTRY(ResetISR)\n\nSECTIONS\n{  \n    \/* place the FreeRTOS heap (the micropython stack will live here) *\/\n    .rtos_heap (NOLOAD) :\n    {\n        . = ALIGN(8);\n        *(.rtos_heap*)\n        . = ALIGN(8);\n    } > SRAMB\n\n    .text :\n    {\n        _text = .;\n        KEEP(*(.intvecs))\n        *(.text*)\n        *(.rodata*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(8);\n    } > SRAM\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n        _etext = .;\n    } > SRAM\n\n    .data :\n    {\n        . = ALIGN(8);\n        _data = .;\n        *(.data*)\n        . = ALIGN(8);\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        . = ALIGN(8);\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        _ebss = .;\n    } > SRAM\n\n    \/* place here functions that are only called during boot up, *\/\n    \/* that way, we can re-use this area for the micropython heap *\/\n    .boot :\n    {\n        . = ALIGN(8);\n        _boot = .;\n        *(.boot*)\n        . = ALIGN(8);\n        _eboot = .;\n    } > SRAM\n     \n    \/* allocate the micropython heap *\/\n    .heap :\n    {\n        . = ALIGN(8);\n        _heap = .;\n        . = . + __min_heap_size__;\n        . = . + (ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ - ABSOLUTE(.));\n        . = ALIGN(8);\n        _eheap = .;\n    } > SRAM\n\n    \/* allocate the main stack *\/\n    .stack ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ :\n    {\n        . = ALIGN(8);\n        _stack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > SRAM\n}\n","old_contents":"\/*\n * This file is part of the Micro Python project, http:\/\/micropython.org\/\n *\n * The MIT License (MIT)\n *\n * Copyright (c) 2015 Daniel Campora\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\/\n\n__stack_size__    = 2K;       \/* interrupts are handled within this stack *\/\n__min_heap_size__ = 8K;\n\nMEMORY\n{\n    SRAMB (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000\n    SRAM  (rwx) : ORIGIN = 0x20004000, LENGTH = 0x0003C000\n}\n\nENTRY(ResetISR)\n\nSECTIONS\n{  \n    \/* place the FreeRTOS heap (the micropython stack will live here) *\/\n    .rtos_heap (NOLOAD) :\n    {\n        . = ALIGN(8);\n        *(.rtos_heap*)\n        . = ALIGN(8);\n    } > SRAMB\n\n    .text :\n    {\n        _text = .;\n        KEEP(*(.intvecs))\n        *(.text*)\n        *(.rodata*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(8);\n    } > SRAM\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n        _etext = .;\n    } > SRAM\n\n    .data :\n    {\n        . = ALIGN(8);\n        _data = .;\n        *(.data*)\n        . = ALIGN(8);\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        . = ALIGN(8);\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        _ebss = .;\n    } > SRAM\n\n    \/* place here functions that are only called during boot up, *\/\n    \/* that way, we can re-use this area for the micropython heap *\/\n    .boot :\n    {\n        . = ALIGN(8);\n        _boot = .;\n        *(.boot*)\n        . = ALIGN(8);\n        _eboot = .;\n    } > SRAM\n     \n    \/* allocate the micropython heap *\/\n    .heap :\n    {\n        . = ALIGN(8);\n        _heap = .;\n        . = . + __min_heap_size__;\n        . = . + (ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ - ABSOLUTE(.));\n        . = ALIGN(8);\n        _eheap = .;\n    } > SRAM\n\n    \/* allocate the main stack *\/\n    .stack ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ :\n    {\n        . = ALIGN(8);\n        _stack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > SRAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7b79eb9abece7102a51ff55cdc88d4bd15c06ebb","subject":"Add comment.","message":"Add comment.\n","repos":"eigenholser\/embedded_programming_intro,eigenholser\/embedded_programming_intro","old_file":"demo\/linker.lds","new_file":"demo\/linker.lds","new_contents":"\/*\n * Modified from default. Primary change moved stack to bottom of RAM.\n *\/\n\/******************************************************************************\n *\n * Default Linker script for the Texas Instruments TM4C123GH6PM\n *\n * This is derived from revision 15071 of the TivaWare Library.\n *\n *****************************************************************************\/\n\nMEMORY\n{\n    FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n    SRAM (WX)  : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\nSTACK_SIZE = 0x400;\nHEAP_SIZE = 0x1000;\n\nREGION_ALIAS(\"REGION_TEXT\", FLASH);\nREGION_ALIAS(\"REGION_BSS\", SRAM);\nREGION_ALIAS(\"REGION_DATA\", SRAM);\nREGION_ALIAS(\"REGION_STACK\", SRAM);\nREGION_ALIAS(\"REGION_HEAP\", SRAM);\nREGION_ALIAS(\"REGION_ARM_EXIDX\", FLASH);\nREGION_ALIAS(\"REGION_ARM_EXTAB\", FLASH);\n\nSECTIONS {\n\n    PROVIDE (_intvecs_base_address = 0x0);\n\n    .intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {\n        KEEP (*(.intvecs))\n        . = ALIGN(0x4);\n    } > REGION_TEXT\n\n    PROVIDE (_vtable_base_address = 0x20000000);\n\n    .vtable (_vtable_base_address) : AT (_vtable_base_address) {\n        KEEP (*(.vtable))\n    } > REGION_DATA\n\n    .text : {\n        CREATE_OBJECT_SYMBOLS\n        *(.text)\n        *(.text.*)\n        . = ALIGN(0x4);\n        KEEP (*(.ctors))\n        . = ALIGN(0x4);\n        KEEP (*(.dtors))\n        . = ALIGN(0x4);\n        __init_array_start = .;\n        KEEP (*(.init_array*))\n        __init_array_end = .;\n        *(.init)\n        *(.fini*)\n    } > REGION_TEXT\n\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata*)\n    } > REGION_TEXT\n\n    .stack : ALIGN(0x4) {\n        __stack_start__ = .;\n        . = . + STACK_SIZE;\n        KEEP(*(.stack))\n        __stack_end__ = .;\n    } > REGION_STACK\n\n    .data : ALIGN (0x4) {\n        __data_load__ = LOADADDR (.data);\n        __data_start__ = .;\n        *(.data)\n        *(.data*)\n        . = ALIGN (0x4);\n        __data_end__ = .;\n    } > REGION_DATA AT> REGION_TEXT\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > REGION_ARM_EXIDX\n\n    .ARM.extab : {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > REGION_ARM_EXTAB\n\n    .bss : {\n        __bss_start__ = .;\n        *(.shbss)\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN (0x4);\n        __bss_end__ = .;\n    } > REGION_BSS\n\n    .heap : {\n        __heap_start__ = .;\n        end = __heap_start__;\n        _end = end;\n        __end = end;\n        KEEP(*(.heap))\n        __heap_end__ = .;\n        __HeapLimit = __heap_end__;\n    } > REGION_HEAP\n\n    \/* Remove information from the standard libraries *\/\n    \/DISCARD\/ : {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n}\n","old_contents":"\/*\n\n *\/\n\/******************************************************************************\n *\n * Default Linker script for the Texas Instruments TM4C123GH6PM\n *\n * This is derived from revision 15071 of the TivaWare Library.\n *\n *****************************************************************************\/\n\nMEMORY\n{\n    FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n    SRAM (WX)  : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\nSTACK_SIZE = 0x400;\nHEAP_SIZE = 0x1000;\n\nREGION_ALIAS(\"REGION_TEXT\", FLASH);\nREGION_ALIAS(\"REGION_BSS\", SRAM);\nREGION_ALIAS(\"REGION_DATA\", SRAM);\nREGION_ALIAS(\"REGION_STACK\", SRAM);\nREGION_ALIAS(\"REGION_HEAP\", SRAM);\nREGION_ALIAS(\"REGION_ARM_EXIDX\", FLASH);\nREGION_ALIAS(\"REGION_ARM_EXTAB\", FLASH);\n\nSECTIONS {\n\n    PROVIDE (_intvecs_base_address = 0x0);\n\n    .intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {\n        KEEP (*(.intvecs))\n        . = ALIGN(0x4);\n    } > REGION_TEXT\n\n    PROVIDE (_vtable_base_address = 0x20000000);\n\n    .vtable (_vtable_base_address) : AT (_vtable_base_address) {\n        KEEP (*(.vtable))\n    } > REGION_DATA\n\n    .text : {\n        CREATE_OBJECT_SYMBOLS\n        *(.text)\n        *(.text.*)\n        . = ALIGN(0x4);\n        KEEP (*(.ctors))\n        . = ALIGN(0x4);\n        KEEP (*(.dtors))\n        . = ALIGN(0x4);\n        __init_array_start = .;\n        KEEP (*(.init_array*))\n        __init_array_end = .;\n        *(.init)\n        *(.fini*)\n    } > REGION_TEXT\n\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata*)\n    } > REGION_TEXT\n\n    .stack : ALIGN(0x4) {\n        __stack_start__ = .;\n        . = . + STACK_SIZE;\n        KEEP(*(.stack))\n        __stack_end__ = .;\n    } > REGION_STACK\n\n    .data : ALIGN (0x4) {\n        __data_load__ = LOADADDR (.data);\n        __data_start__ = .;\n        *(.data)\n        *(.data*)\n        . = ALIGN (0x4);\n        __data_end__ = .;\n    } > REGION_DATA AT> REGION_TEXT\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > REGION_ARM_EXIDX\n\n    .ARM.extab : {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > REGION_ARM_EXTAB\n\n    .bss : {\n        __bss_start__ = .;\n        *(.shbss)\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN (0x4);\n        __bss_end__ = .;\n    } > REGION_BSS\n\n    .heap : {\n        __heap_start__ = .;\n        end = __heap_start__;\n        _end = end;\n        __end = end;\n        KEEP(*(.heap))\n        __heap_end__ = .;\n        __HeapLimit = __heap_end__;\n    } > REGION_HEAP\n\n    \/* Remove information from the standard libraries *\/\n    \/DISCARD\/ : {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"68de334a9da636f4edda4b441506443751d9b7af","subject":"Linker script corrected","message":"Linker script corrected\n","repos":"codepainters\/FD1,codepainters\/FD1,codepainters\/FD1,codepainters\/FD1","old_file":"firmware\/LPC1343_flash.ld","new_file":"firmware\/LPC1343_flash.ld","new_contents":"\/**\n * Definitions for LPC1343 - 32kB Flash, 8kB RAM\n *\n * At the beginning of RAM there are 384 bytes reserved \n * for USB driver. \n *\/\n\nMEMORY\n{\n  flash(rx): ORIGIN = 0x00000000,       LENGTH = 32K - 8K\n  sram(rwx): ORIGIN = 0x10000000 + 384, LENGTH = 8K - 384\n}\n\n\/* Sectores reserved for configuration storage *\/\n\n__SETTINGS_SECTOR0_ADDR = 0x6000;\n__SETTINGS_SECTOR0_NUM = 6;\n\n__SETTINGS_SECTOR1 = 0x7000;\n__SETTINGS_SECTOR1_NUM = 7;\n\nINCLUDE lpc1xxx\/linkscript.ld\n","old_contents":"\/**\n * Definitions for LPC1343 - 32kB Flash, 8kB RAM\n *\n * At the beginning of RAM there are 384 bytes reserved \n * for USB driver. \n *\/\n\nMEMORY\n{\n  flash(rx): ORIGIN = 0x00000000,       LENGTH = 32K - 8K\n  sram(rwx): ORIGIN = 0x10000000 + 384, LENGTH = 8K - 384\n}\n\n__SETTINGS_SECTOR0_ADDR = 0x6000;\n__SETTINGS_SECTOR0_NUM = 6;\n\n__SETTINGS_SECTOR1 = 0x7000;\n__SETTINGS_SECTOR1_NUM = 7;\n\nINCLUDE LPC1343CodeBase\/lpc1xxx\/linkscript.ld\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"3d4595466a10a870e361e745d8f942429a13fc26","subject":"Fixes bug in memory map for PIC32 target no bootloader.ld","message":"Fixes bug in memory map for PIC32 target no bootloader.ld\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/microchip-pic32mx-generic\/misc\/target_no_bootloader.ld","new_file":"boards\/microchip-pic32mx-generic\/misc\/target_no_bootloader.ld","new_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n**\r\n** This file was adjusted for memory regions of the PIC32MX530F128 device which\r\n** has 128+3K flash and 16K ram.  \r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 16K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0x9D000000, LENGTH = 128K \/* to BD020000-1, bootloader gets first 128k *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0x9FC00000, LENGTH = 0x180 \/* The beginning of the interrupt vector table is empty. *\/\r\n  PIC32MX_flash_boot_remaining (rx): ORIGIN = 0x9FC00A00, LENGTH = 3K-0x10-0xA00 \/* Skipped flash_cfg rgister and 0xa00 at the beginning for the interupt vector table. NOTE(bracz): also one debug page might need to be reserved here, which would directly prevent us from placing the interrupt vector table here. -- need 2K + 1k debug. Maybe the vector table could be trimmed. Calculations give that 48 vectors would fit. *\/\r\n  \/* This is for PIC32MX795, where we have 12K boot ROM *\/\r\n  PIC32MX_flash_cfg  (r!x): ORIGIN = 0x9FC02FF0, LENGTH = 0x0010\r\n  \/* This is for the MX530 where we only have 3K boot ROM \r\n  PIC32MX_flash_cfg  (r!x): ORIGIN = 0x9FC00BF0, LENGTH = 0x0010 *\/\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** Located at the beginning of bootflash for now.\r\n** 0xBFC00000 + 0x200 + (64 vectors * x20)) = 0xBFC00A00\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0x9FC00000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\n\/* NOT NEEDED -- we have our own entry routine, not using cs3's\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) *\/\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 2k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** PIC32MX configuration registers\r\n  *\/\r\n  .PIC32MX_cfg_init :\r\n  {\r\n    KEEP(*(.PIC32MX_cfg_init))\r\n  } >PIC32MX_flash_cfg \/*AT>PIC32MX_physical_flash_cfg*\/\r\n  \/* Assert exactly 4 words are placed in configuration area *\/\r\n  \/* Note: terminating semicolon causes syntax error for ASSERT in following line ! *\/\r\n\r\n  ASSERT (SIZEOF(.PIC32MX_cfg_init) == 0x10, \"PIC32MX configuration register set must be 4 words long\")\r\n\r\n  \/*\r\n  ** First thing in boot flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n    \/*\r\n    ** While the PIC32MX is in Bootstrap mode, all interrupts are disabled\r\n    ** and all general exceptions are redirected to address 0xBFC00380\r\n    . = __cs3_reset_PIC32MX + 0x0380;\r\n    KEEP(*(.bev_handler)) \/* optional boot exception handler *\/\r\n    \r\n\r\n  } >PIC32MX_flash_boot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; DRN updated this; seems correct...  bracz: not really. *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","old_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n**\r\n** This file was adjusted for memory regions of the PIC32MX530F128 device which\r\n** has 128+3K flash and 16K ram.  \r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 16K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0x9D000000, LENGTH = 128K \/* to BD020000-1, bootloader gets first 128k *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0x9FC00000, LENGTH = 0x180 \/* The beginning of the interrupt vector table is empty. *\/\r\n  PIC32MX_flash_boot_remaining (rx): ORIGIN = 0x9FC00A00, LENGTH = 3K-0x10-0xA00 \/* Skipped flash_cfg rgister and 0xa00 at the beginning for the interupt vector table. NOTE(bracz): also one debug page might need to be reserved here, which would directly prevent us from placing the interrupt vector table here. -- need 2K + 1k debug. Maybe the vector table could be trimmed. Calculations give that 48 vectors would fit. *\/\r\n  PIC32MX_flash_cfg  (r!x): ORIGIN = 0x9FC00BF0, LENGTH = 0x0010\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** Located at the beginning of bootflash for now.\r\n** 0xBFC00000 + 0x200 + (64 vectors * x20)) = 0xBFC00A00\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0x9FC00000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\n\/* NOT NEEDED -- we have our own entry routine, not using cs3's\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) *\/\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 2k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** PIC32MX configuration registers\r\n  *\/\r\n  .PIC32MX_cfg_init :\r\n  {\r\n    KEEP(*(.PIC32MX_cfg_init))\r\n  } >PIC32MX_flash_cfg \/*AT>PIC32MX_physical_flash_cfg*\/\r\n  \/* Assert exactly 4 words are placed in configuration area *\/\r\n  \/* Note: terminating semicolon causes syntax error for ASSERT in following line ! *\/\r\n\r\n  ASSERT (SIZEOF(.PIC32MX_cfg_init) == 0x10, \"PIC32MX configuration register set must be 4 words long\")\r\n\r\n  \/*\r\n  ** First thing in boot flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n    \/*\r\n    ** While the PIC32MX is in Bootstrap mode, all interrupts are disabled\r\n    ** and all general exceptions are redirected to address 0xBFC00380\r\n    . = __cs3_reset_PIC32MX + 0x0380;\r\n    KEEP(*(.bev_handler)) \/* optional boot exception handler *\/\r\n    \r\n\r\n  } >PIC32MX_flash_boot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; DRN updated this; seems correct...  bracz: not really. *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"635f7d3f9dced752f84d429e1d51f5c2b29854e3","subject":"Align section size instead of section start due to #126","message":"Align section size instead of section start due to #126\n\nThis fixes the problem that GRUB sometimes puts the multiboot info struct between kernel sections if the hole is big enough. This leads to problems since we would try to map the same page twice in that case.\n","repos":"phil-opp\/blog_os,phil-opp\/blogOS,phil-opp\/blog_os,phil-opp\/blog_os,phil-opp\/blog_os,phil-opp\/blogOS","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/*\nCopyright 2015 Philipp Oppermann. See the README.md\nfile at the top-level directory of this distribution.\n\nLicensed under the Apache License, Version 2.0 <LICENSE-APACHE or\nhttp:\/\/www.apache.org\/licenses\/LICENSE-2.0> or the MIT license\n<LICENSE-MIT or http:\/\/opensource.org\/licenses\/MIT>, at your\noption. This file may not be copied, modified, or distributed\nexcept according to those terms.\n*\/\n\nENTRY(start)\n\nSECTIONS {\n  . = 1M;\n\n  .rodata :\n  {\n    \/* ensure that the multiboot header is at the beginning *\/\n    KEEP(*(.multiboot_header))\n    *(.rodata .rodata.*)\n    . = ALIGN(4K);\n  }\n\n  .text :\n  {\n    *(.text .text.*)\n    . = ALIGN(4K);\n  }\n\n  .data :\n  {\n    *(.data .data.*)\n    . = ALIGN(4K);\n  }\n\n  .bss :\n  {\n    *(.bss .bss.*)\n    . = ALIGN(4K);\n  }\n\n  .data.rel.ro : ALIGN(4K) {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n    . = ALIGN(4K);\n  }\n\n  .gcc_except_table : ALIGN(4K) {\n    *(.gcc_except_table)\n    . = ALIGN(4K);\n  }\n}\n","old_contents":"\/*\nCopyright 2015 Philipp Oppermann. See the README.md\nfile at the top-level directory of this distribution.\n\nLicensed under the Apache License, Version 2.0 <LICENSE-APACHE or\nhttp:\/\/www.apache.org\/licenses\/LICENSE-2.0> or the MIT license\n<LICENSE-MIT or http:\/\/opensource.org\/licenses\/MIT>, at your\noption. This file may not be copied, modified, or distributed\nexcept according to those terms.\n*\/\n\nENTRY(start)\n\nSECTIONS {\n  . = 1M;\n\n  .rodata : ALIGN(4K)\n  {\n    \/* ensure that the multiboot header is at the beginning *\/\n    KEEP(*(.multiboot_header))\n    *(.rodata .rodata.*)\n  }\n\n  .text : ALIGN(4K)\n  {\n    *(.text .text.*)\n  }\n\n  .data : ALIGN(4K)\n  {\n    *(.data .data.*)\n  }\n\n  .data.rel.ro : ALIGN(4K) {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n  }\n\n  .gcc_except_table : ALIGN(4K) {\n    *(.gcc_except_table)\n  }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5ce2baf605ac3a47e3bc95db3057993b792d7ccd","subject":"address review comments.","message":"address review comments.\n","repos":"tensorflow\/tensorflow-experimental_link_static_libraries_once,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,frreiss\/tensorflow-fred,annarev\/tensorflow,tensorflow\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,yongtang\/tensorflow,tensorflow\/tensorflow,davidzchen\/tensorflow,sarvex\/tensorflow,karllessard\/tensorflow,paolodedios\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,cxxgtxy\/tensorflow,yongtang\/tensorflow,annarev\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,sarvex\/tensorflow,freedomtan\/tensorflow,Intel-tensorflow\/tensorflow,davidzchen\/tensorflow,freedomtan\/tensorflow,karllessard\/tensorflow,davidzchen\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,petewarden\/tensorflow,cxxgtxy\/tensorflow,sarvex\/tensorflow,yongtang\/tensorflow,cxxgtxy\/tensorflow,annarev\/tensorflow,petewarden\/tensorflow,karllessard\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_tf_optimizer,annarev\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,petewarden\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow,cxxgtxy\/tensorflow,yongtang\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,sarvex\/tensorflow,frreiss\/tensorflow-fred,frreiss\/tensorflow-fred,davidzchen\/tensorflow,annarev\/tensorflow,frreiss\/tensorflow-fred,gautam1858\/tensorflow,petewarden\/tensorflow,karllessard\/tensorflow,yongtang\/tensorflow,frreiss\/tensorflow-fred,freedomtan\/tensorflow,davidzchen\/tensorflow,aam-at\/tensorflow,paolodedios\/tensorflow,annarev\/tensorflow,karllessard\/tensorflow,karllessard\/tensorflow,freedomtan\/tensorflow,davidzchen\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,gautam1858\/tensorflow,yongtang\/tensorflow,frreiss\/tensorflow-fred,petewarden\/tensorflow,davidzchen\/tensorflow,annarev\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,freedomtan\/tensorflow,gautam1858\/tensorflow,karllessard\/tensorflow,freedomtan\/tensorflow,freedomtan\/tensorflow,petewarden\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,aam-at\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,frreiss\/tensorflow-fred,annarev\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,davidzchen\/tensorflow,davidzchen\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,cxxgtxy\/tensorflow,paolodedios\/tensorflow,frreiss\/tensorflow-fred,freedomtan\/tensorflow,yongtang\/tensorflow,annarev\/tensorflow,Intel-Corporation\/tensorflow,aam-at\/tensorflow,aam-at\/tensorflow,Intel-tensorflow\/tensorflow,davidzchen\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,karllessard\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_saved_model,frreiss\/tensorflow-fred,cxxgtxy\/tensorflow,freedomtan\/tensorflow,aam-at\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,petewarden\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_saved_model,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-experimental_link_static_libraries_once,freedomtan\/tensorflow,petewarden\/tensorflow,Intel-Corporation\/tensorflow,Intel-tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,aam-at\/tensorflow,aam-at\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,gautam1858\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow,gautam1858\/tensorflow,gautam1858\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,cxxgtxy\/tensorflow,freedomtan\/tensorflow,davidzchen\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow,gautam1858\/tensorflow,paolodedios\/tensorflow,petewarden\/tensorflow,sarvex\/tensorflow,petewarden\/tensorflow,yongtang\/tensorflow,Intel-Corporation\/tensorflow,Intel-tensorflow\/tensorflow,annarev\/tensorflow,Intel-Corporation\/tensorflow,aam-at\/tensorflow,sarvex\/tensorflow,davidzchen\/tensorflow,Intel-tensorflow\/tensorflow,sarvex\/tensorflow,Intel-Corporation\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,aam-at\/tensorflow,gautam1858\/tensorflow","old_file":"tensorflow\/lite\/micro\/tools\/make\/targets\/bluepill\/bluepill.lds","new_file":"tensorflow\/lite\/micro\/tools\/make\/targets\/bluepill\/bluepill.lds","new_contents":"\/* Copyright 2018 Google Inc. All Rights Reserved.\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n==============================================================================*\/\n\n\/* Copied and modified from:\n   https:\/\/github.com\/google\/stm32_bare_lib\/blob\/master\/stm32_linker_layout.lds\n\n   Modifications:\n    * increased the flash size to 512K and RAM to 256K. This far exceeds the\n      actual hardware but enables running the tests in the emulator.\n*\/\n\n\/*\n * 0x00000000 - 0x07ffffff - aliased to flash or sys memory depending on BOOT jumpers.\n * 0x08000000 - 0x0807ffff - Flash.\n * 0x1ffff000 - 0x1ffff7ff - Boot firmware in system memory.\n * 0x1ffff800 - 0x1fffffff - Option bytes.\n * 0x20000000 - 0x2003ffff - SRAM.\n * 0x40000000 - 0x40023400 - Peripherals\n *\/\n\n\/* Define main entry point *\/\nENTRY(_main)\n\nMEMORY {\nRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K\nFLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K\n}\n\n\/* Compute where the stack ends rather than hard coding it *\/\n_ld_stack_end_addr = ORIGIN(RAM) + LENGTH(RAM);\n_ld_min_stack_size = 0x200;\n\nSECTIONS {\n\n\/* interrupt vector goes to top of flash *\/\n\n.interrupt_vector : {\n  . = ALIGN(4);\n  KEEP(*(.interrupt_vector))\n  . = ALIGN(4);\n} >FLASH\n\n\/* read only .text and .rodata go to flash *\/\n\n.text : {\n  . = ALIGN(4);\n  KEEP(*(.text.interrupt_handler))\n  *(.text*)\n} >FLASH\n\n.rodata : {\n  . = ALIGN(4);\n  *(.rodata*)\n  . = ALIGN(4);\n} >FLASH\n\n\/* read mwrite data needs to be stored in flash but copied to ram *\/\n.data : {\n  . = ALIGN(4);\n  _ld_data_load_dest_start = .; \/* export where to load from *\/\n  *(.data*)\n  . = ALIGN(4);\n  _ld_data_load_dest_stop = .; \/* export where to load from *\/\n} >RAM AT> FLASH\n_ld_data_load_source = LOADADDR(.data);\n\n\/* unitialized data section needs zero initialization *\/\n.bss :\n{\n  . = ALIGN(4);\n  _ld_bss_data_start = .;\n  *(.bss*)\n  . = ALIGN(4);\n  _ld_bss_data_stop = .;\n} >RAM\n\n._user_heap_stack :\n{\n  . = ALIGN(8);\n  . += _ld_min_stack_size;\n  PROVIDE(end = .);\n  . = ALIGN(8);\n} >RAM\n\n\/DISCARD\/ :\n{\n  libc.a (*)\n  libm.a (*)\n  libgcc.a (*)\n}\n\n}  \/* SECTIONS *\/\n","old_contents":"\/* Copyright 2018 Google Inc. All Rights Reserved.\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n==============================================================================*\/\n\n\/* Copied and modified from:\n   https:\/\/github.com\/google\/stm32_bare_lib\/blob\/master\/stm32_linker_layout.lds\n\n   Modifications:\n    * increased the flash size to 512K and RAM to 256K. This far exceeds the\n      actual hardware but enables running the tests in the emulator.\n*\/\n\n\/*\n * 0x00000000 - 0x07ffffff - aliased to flash or sys memory depending on BOOT jumpers.\n * 0x08000000 - 0x0807ffff - Flash.\n * 0x1ffff000 - 0x1ffff7ff - Boot firmware in system memory.\n * 0x1ffff800 - 0x1fffffff - Option bytes.\n * 0x20000000 - 0x2003ffff - SRAM.\n * 0x40000000 - 0x40023400 - Peripherals\n *\/\n\n\/* Define main entry point *\/\nENTRY(_main)\n\n\/* 20K of RAM and 128K of FLASH *\/\nMEMORY {\nRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K\nFLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K\n}\n\n\/* Compute where the stack ends rather than hard coding it *\/\n_ld_stack_end_addr = ORIGIN(RAM) + LENGTH(RAM);\n_ld_min_stack_size = 0x200;\n\nSECTIONS {\n\n\/* interrupt vector goes to top of flash *\/\n\n.interrupt_vector : {\n  . = ALIGN(4);\n  KEEP(*(.interrupt_vector))\n  . = ALIGN(4);\n} >FLASH\n\n\/* read only .text and .rodata go to flash *\/\n\n.text : {\n  . = ALIGN(4);\n  KEEP(*(.text.interrupt_handler))\n  *(.text*)\n} >FLASH\n\n.rodata : {\n  . = ALIGN(4);\n  *(.rodata*)\n  . = ALIGN(4);\n} >FLASH\n\n\/* read mwrite data needs to be stored in flash but copied to ram *\/\n.data : {\n  . = ALIGN(4);\n  _ld_data_load_dest_start = .; \/* export where to load from *\/\n  *(.data*)\n  . = ALIGN(4);\n  _ld_data_load_dest_stop = .; \/* export where to load from *\/\n} >RAM AT> FLASH\n_ld_data_load_source = LOADADDR(.data);\n\n\/* unitialized data section needs zero initialization *\/\n.bss :\n{\n  . = ALIGN(4);\n  _ld_bss_data_start = .;\n  *(.bss*)\n  . = ALIGN(4);\n  _ld_bss_data_stop = .;\n} >RAM\n\n._user_heap_stack :\n{\n  . = ALIGN(8);\n  . += _ld_min_stack_size;\n  PROVIDE(end = .);\n  . = ALIGN(8);\n} >RAM\n\n\/DISCARD\/ :\n{\n  libc.a (*)\n  libm.a (*)\n  libgcc.a (*)\n}\n\n}  \/* SECTIONS *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"0a5367d29b10bc9ae97a626a5ed2ecf50d3702f5","subject":"newlib: link ESP8684 ROM symbols _printf_float & _scanf_float","message":"newlib: link ESP8684 ROM symbols _printf_float & _scanf_float\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.newlib-nano.ld","new_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.newlib-nano.ld","new_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.newlib-nano.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group newlib_nano_format\n ***************************************\/\n\n\/* Functions *\/\n__sprint_r = 0x40000674;\n_fiprintf_r = 0x40000678;\n_fprintf_r = 0x4000067c;\n_printf_common = 0x40000680;\n_printf_i = 0x40000684;\n_vfiprintf_r = 0x40000688;\n_vfprintf_r = 0x4000068c;\nfiprintf = 0x40000690;\nfprintf = 0x40000694;\nprintf = 0x40000698;\nvfiprintf = 0x4000069c;\nvfprintf = 0x400006a0;\nasprintf = 0x400006a4;\nsprintf = 0x400006a8;\nsnprintf = 0x400006ac;\nsiprintf = 0x400006b0;\nsniprintf = 0x400006b4;\nvprintf = 0x400006b8;\nviprintf = 0x400006bc;\nvsnprintf = 0x400006c0;\nvsniprintf = 0x400006c4;\n_printf_float = 0x400006c8;\n_scanf_float = 0x400006cc;\n_scanf_i = 0x400006d0;\n_scanf_chars = 0x400006d4;\nsscanf = 0x400006d8;\nsiscanf = 0x400006dc;\n","old_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.newlib-nano.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group newlib_nano_format\n ***************************************\/\n\n\/* Functions *\/\n__sprint_r = 0x40000674;\n_fiprintf_r = 0x40000678;\n_fprintf_r = 0x4000067c;\n_printf_common = 0x40000680;\n_printf_i = 0x40000684;\n_vfiprintf_r = 0x40000688;\n_vfprintf_r = 0x4000068c;\nfiprintf = 0x40000690;\nfprintf = 0x40000694;\nprintf = 0x40000698;\nvfiprintf = 0x4000069c;\nvfprintf = 0x400006a0;\nasprintf = 0x400006a4;\nsprintf = 0x400006a8;\nsnprintf = 0x400006ac;\nsiprintf = 0x400006b0;\nsniprintf = 0x400006b4;\nvprintf = 0x400006b8;\nviprintf = 0x400006bc;\nvsnprintf = 0x400006c0;\nvsniprintf = 0x400006c4;\n__rom_printf_float = 0x400006c8;\n__rom_scanf_float = 0x400006cc;\n_scanf_i = 0x400006d0;\n_scanf_chars = 0x400006d4;\nsscanf = 0x400006d8;\nsiscanf = 0x400006dc;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d3e7e39fb2ada3bfe00f91b5152f2e97e303ff63","subject":"Group all .sdata sections together into GP relative section","message":"Group all .sdata sections together into GP relative section\n","repos":"tintin304\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,ricklon\/chipKIT32-MAX","old_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_contents":"\/************************************************************************\n *\tchipKIT-applicaiton-COMMON.ld\n *\n *\tThis is the common part of the linker script shared\n *\tacross all chipKIT PIC32 processors \/ boards.\n *\n ************************************************************************\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\n * \tThis library is free software; you can redistribute it and\/or\n *  modify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tThis library is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General\n *\tPublic License along with this library; if not, write to the\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\n *\tBoston, MA\t02111-1307\tUSA\n *\n *\n ************************************************************************\n *\tEdit History\n ************************************************************************\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\n ************************************************************************\n *\/\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\nINPUT(\"crtbegin.o\")\nINPUT(\"crtend.o\")\nINPUT(\"crtn.o\")\nOPTIONAL(\"libmchp_peripheral.a\")\n\n\/*************************************************************************\n * Start the layout of memory, the sections...\n *************************************************************************\/\n\nSECTIONS\n{\n  \/* Don't allow config-fuse sections in an application sketch *\/\n  \/DISCARD\/ : { *(.config_*) }\n}\n\nSECTIONS\n{\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\n  {\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n .image_ptr_table _IMAGE_PTR_TABLE :\n  {\n    LONG(_ebase_address)\n    LONG(_image_header_info)\n  } > exception_mem\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n\n  .vector_0 _ebase_address + 0x200 :\n  {\n    _new_vector_0 = . ;\n\tKEEP(*(.vector_new_0))\n    _original_vector_0 = . ;\n\tKEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_new_1))\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_new_2))\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_new_3))\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_new_4))\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_new_5))\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_new_6))\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_new_7))\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_new_8))\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_new_9))\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_new_10))\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_new_11))\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_new_12))\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_new_13))\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_new_14))\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_new_15))\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_new_16))\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_new_17))\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_new_18))\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_new_19))\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_new_20))\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_new_21))\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_new_22))\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_new_23))\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_new_24))\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_new_25))\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_new_26))\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_new_27))\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_new_28))\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_new_29))\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_new_30))\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_new_31))\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_new_32))\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_new_33))\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_new_34))\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_new_35))\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_new_36))\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_new_37))\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_new_38))\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_new_39))\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_new_40))\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_new_41))\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_new_42))\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_new_43))\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_new_44))\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_new_45))\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_new_46))\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_new_47))\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_new_48))\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_new_49))\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_new_50))\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_new_51))\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_new_52))\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_new_53))\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_new_54))\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_new_55))\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_new_56))\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_new_57))\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_new_58))\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_new_59))\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_new_60))\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_new_61))\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_new_62))\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_new_63))\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.stub .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n    *(.gnu.warning)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n    . = ALIGN(4) ;\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  \/* Read-only sections *\/\n  .header_info ALIGN(4) :\n  {\n    _image_header_info = . ;\n    LONG(SIZEOF(.header_info))                 \/* size of this structure       *\/\n    LONG(0xFFFFFFFF)                           \/* bootloader version           *\/\n    KEEP(*(.mpide_version *.mpide_version.*))  \/* MPIDE build version          *\/\n    LONG(0xFFFFFFFF)                           \/* booloader capabilities       *\/\n    LONG(0xFFFFFFFF)                           \/* VID and PID                  *\/\n    LONG(_IMAGE_TYPE)                          \/* image type and options       *\/\n    LONG(_JUMP_ADDR)                           \/* image execution address      *\/\n    LONG(_ebase_address)                       \/* image base address           *\/\n    LONG(_IMAGE_FLASH_SIZE)                    \/* size of image flash used     *\/\n    LONG(ORIGIN(kseg0_eeprom_mem))             \/* eeprom location              *\/\n    LONG(LENGTH(kseg0_eeprom_mem))             \/* eeprom size                  *\/\n    LONG(ORIGIN(configsfrs))                   \/* config bits location         *\/\n    LONG(LENGTH(configsfrs))                   \/* config bits size             *\/\n    LONG(_ram_header_addr)                     \/* ram header pointer           *\/\n    LONG(SIZEOF(.ram_exchange_data))           \/* ram Header size              *\/\n    LONG(0xFFFFFFFF)                           \/* what the bootloader skips    *\/\n    LONG(_original_vector_0)                   \/* the original vector 0        *\/\n    LONG(_new_vector_0)                        \/* new\/indirect vector 0        *\/\n    LONG(_vector_spacing << 5)                 \/* spacing of both org\/new vec  *\/\n    _image_header_info_end = . ;\n  } > kseg0_program_mem\n  ASSERT (SIZEOF(.header_info) == 76, \"MPIDE Version not specfied correctly\")\n\n  .rodata  ALIGN(4) :\n  {\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  .ram_exchange_data (NOLOAD) :\n  {\n    _ram_header_addr = . ;\n    . += 8 ;\n  } >kseg1_data_mem\n\n  \/* Persistent data - Use the new C 'persistent' attribute instead. *\/\n  .persist ALIGN(4) (NOLOAD) :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4) ;\n    _persist_end = .;\n  } >kseg1_data_mem\n\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\n\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\n\n  .protected_bootloader ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : 0x0);\n  }\n\n  \/*\n   *  Note that input sections named .data* are not mapped here.\n   *  The best-fit allocator locates them, so that they may flow\n   *  around absolute sections as needed.\n   *\/\n  .data :\n  {\n    _data_begin = . ;\n    *( .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  _data_image_begin = LOADADDR(.data) ;\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4) :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    . = ALIGN(4) ;\n    _sdata_end = . ;\n  } >kseg1_data_mem\n  .lit8           :\n  {\n    *(.lit8)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem\n\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n\n  .sbss ALIGN(4) :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    . = ALIGN(4) ;\n    _sbss_end = . ;\n  } >kseg1_data_mem\n\n  .bss   :\n  {\n    *(.dynbss)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n\n  \/*\n   *  The heap and stack are best-fit allocated by the linker after other\n   *  data and bss sections have been allocated.\n   *\/\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\n   * RAM functions are now allocated by the linker. The linker generates\n   * _ramfunc_begin and _bmxdkpba_address symbols depending on the\n   * location of RAM functions.\n   *\/\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n\n    \/* The .pdr section belongs in the absolute section *\/\n\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n\n  .gcc_compiled_long32 : { KEEP(*(.gcc_compiled_long32)) }\n  .gcc_compiled_long64 : { KEEP(*(.gcc_compiled_long64)) }\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0  : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) *(.discard) }\n}\n","old_contents":"\/************************************************************************\n *\tchipKIT-applicaiton-COMMON.ld\n *\t\n *\tThis is the common part of the linker script shared\n *\tacross all chipKIT PIC32 processors \/ boards.\n *\t\n ************************************************************************\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\n * \tThis library is free software; you can redistribute it and\/or\n *  modify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\t\n *\tThis library is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\n *\tLesser General Public License for more details.\n *\t\n *\tYou should have received a copy of the GNU Lesser General\n *\tPublic License along with this library; if not, write to the\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\n *\tBoston, MA\t02111-1307\tUSA\n *\t\n *\t\n ************************************************************************\n *\tEdit History\n ************************************************************************\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\n ************************************************************************\n *\/\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\nINPUT(\"crtbegin.o\")\nINPUT(\"crtend.o\")\nINPUT(\"crtn.o\")\nOPTIONAL(\"libmchp_peripheral.a\") \n\n\/*************************************************************************\n * Start the layout of memory, the sections...\n *************************************************************************\/\n\nSECTIONS\n{\n  \/* Don't allow config-fuse sections in an application sketch *\/\n  \/DISCARD\/ : { *(.config_*) }\n}\n\nSECTIONS\n{\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\n  {\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n .image_ptr_table _IMAGE_PTR_TABLE :\n  {\n    LONG(_ebase_address)\t\n    LONG(_image_header_info)\n  } > exception_mem\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n\n  .vector_0 _ebase_address + 0x200 :\n  {\n    _new_vector_0 = . ;\n\tKEEP(*(.vector_new_0))\n    _original_vector_0 = . ;\n\tKEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_new_1))\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_new_2))\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_new_3))\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_new_4))\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_new_5))\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_new_6))\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_new_7))\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_new_8))\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_new_9))\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_new_10))\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_new_11))\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_new_12))\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_new_13))\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_new_14))\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_new_15))\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_new_16))\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_new_17))\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_new_18))\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_new_19))\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_new_20))\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_new_21))\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_new_22))\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_new_23))\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_new_24))\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_new_25))\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_new_26))\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_new_27))\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_new_28))\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_new_29))\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_new_30))\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_new_31))\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_new_32))\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_new_33))\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_new_34))\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_new_35))\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_new_36))\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_new_37))\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_new_38))\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_new_39))\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_new_40))\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_new_41))\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_new_42))\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_new_43))\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_new_44))\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_new_45))\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_new_46))\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_new_47))\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_new_48))\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_new_49))\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_new_50))\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_new_51))\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_new_52))\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_new_53))\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_new_54))\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_new_55))\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_new_56))\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_new_57))\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_new_58))\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_new_59))\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_new_60))\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_new_61))\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_new_62))\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_new_63))\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.stub .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n    *(.gnu.warning)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n    . = ALIGN(4) ;\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  \/* Read-only sections *\/\n  .header_info ALIGN(4) :\n  {\n    _image_header_info = . ;\n    LONG(SIZEOF(.header_info))                 \/* size of this structure       *\/\n    LONG(0xFFFFFFFF)                           \/* bootloader version           *\/\n    KEEP(*(.mpide_version *.mpide_version.*))  \/* MPIDE build version          *\/\n    LONG(0xFFFFFFFF)                           \/* booloader capabilities       *\/\n    LONG(0xFFFFFFFF)                           \/* VID and PID                  *\/\n    LONG(_IMAGE_TYPE)                          \/* image type and options       *\/\n    LONG(_JUMP_ADDR)                           \/* image execution address      *\/\n    LONG(_ebase_address)                       \/* image base address           *\/\n    LONG(_IMAGE_FLASH_SIZE)                    \/* size of image flash used     *\/\n    LONG(ORIGIN(kseg0_eeprom_mem))             \/* eeprom location              *\/\n    LONG(LENGTH(kseg0_eeprom_mem))             \/* eeprom size                  *\/   \n    LONG(ORIGIN(configsfrs))                   \/* config bits location         *\/\n    LONG(LENGTH(configsfrs))                   \/* config bits size             *\/\n    LONG(_ram_header_addr)                     \/* ram header pointer           *\/\n    LONG(SIZEOF(.ram_exchange_data))           \/* ram Header size              *\/\n    LONG(0xFFFFFFFF)                           \/* what the bootloader skips    *\/\n    LONG(_original_vector_0)                   \/* the original vector 0        *\/\n    LONG(_new_vector_0)                        \/* new\/indirect vector 0        *\/\n    LONG(_vector_spacing << 5)                 \/* spacing of both org\/new vec  *\/\n    _image_header_info_end = . ;\n  } > kseg0_program_mem\n  ASSERT (SIZEOF(.header_info) == 76, \"MPIDE Version not specfied correctly\")\n\n  .rodata  ALIGN(4) :\n  {\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n  \n  .ram_exchange_data (NOLOAD) :\n  {\n    _ram_header_addr = . ;\n    . += 8 ;\n  } >kseg1_data_mem\n\n  \/* Persistent data - Use the new C 'persistent' attribute instead. *\/\n  .persist ALIGN(4) (NOLOAD) :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4) ;\n    _persist_end = .;\n  } >kseg1_data_mem\n\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\n\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\n\n  .protected_bootloader ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : 0x0);\n  }\n\n  \/*\n   *  Note that input sections named .data* are not mapped here.\n   *  The best-fit allocator locates them, so that they may flow\n   *  around absolute sections as needed.\n   *\/\n  .data :\n  {\n    _data_begin = . ;\n    *( .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  _data_image_begin = LOADADDR(.data) ;\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(4) ;\n    _sdata_end = . ;\n  } >kseg1_data_mem\n\n  .lit8           :\n  {\n    *(.lit8)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem \n\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    . = ALIGN(4) ;\n    _sbss_end = . ;\n  } >kseg1_data_mem\n\n  .bss   :\n  {\n    *(.dynbss)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n\n  \/*\n   *  The heap and stack are best-fit allocated by the linker after other\n   *  data and bss sections have been allocated.\n   *\/\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\n   * RAM functions are now allocated by the linker. The linker generates\n   * _ramfunc_begin and _bmxdkpba_address symbols depending on the\n   * location of RAM functions.\n   *\/\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n\n    \/* The .pdr section belongs in the absolute section *\/\n    \n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n\n  .gcc_compiled_long32 : { KEEP(*(.gcc_compiled_long32)) }\n  .gcc_compiled_long64 : { KEEP(*(.gcc_compiled_long64)) }\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0  : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) *(.discard) }\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"344be233cfa2fe82ac1275b76726a2cf88f85fda","subject":"mro ctrl-zero-h7:Properly configure BDMA","message":"mro ctrl-zero-h7:Properly configure BDMA\n","repos":"acfloria\/Firmware,acfloria\/Firmware,acfloria\/Firmware,acfloria\/Firmware,acfloria\/Firmware,acfloria\/Firmware,acfloria\/Firmware","old_file":"boards\/mro\/ctrl-zero-h7\/nuttx-config\/scripts\/script.ld","new_file":"boards\/mro\/ctrl-zero-h7\/nuttx-config\/scripts\/script.ld","new_contents":"\/****************************************************************************\n * scripts\/script.ld\n *\n *   Copyright (C) 2021 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The board uses an STM32H743XIH6 and has 2048Kb of main FLASH memory.\n * The flash memory is partitioned into a User Flash memory and a System\n * Flash memory. Each of these memories has two banks:\n *\n *   1) User Flash memory:\n *\n *      Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each\n *      Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each\n *\n *   2) System Flash memory:\n *\n *      Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector\n *      Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector\n *\n *   3) User option bytes for user configuration, only in Bank 1.\n *\n * In the STM32H743II, two different boot spaces can be selected through\n * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and\n * BOOT_ADD1 option bytes:\n *\n *   1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].\n *      ST programmed value: Flash memory at 0x0800:0000\n *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].\n *      ST programmed value: System bootloader at 0x1FF0:0000\n *\n * There's a switch on board, the BOOT0 pin is at ground so by default,\n * the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is\n * drepresed, then the boot will be from 0x1FF0:0000\n *\n * The STM32H743ZI also has 1024Kb of data SRAM.\n * SRAM is split up into several blocks and into three power domains:\n *\n *   1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with\n *      0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus\n *\n *      1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000\n *\n *           The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit\n *           DTCM ports. The DTCM-RAM could be used for critical real-time\n *           data, such as interrupt service routines or stack \/ heap memory.\n *           Both DTCM-RAMs can be used in parallel (for load\/store operations)\n *           thanks to the Cortex-M7 dual issue capability.\n *\n *      1.2)  64Kb of ITCM-RAM beginning at address 0x0000:0000\n *\n *           This RAM is connected to ITCM 64-bit interface designed for\n *           execution of critical real-times routines by the CPU.\n *\n *   2) AXI SRAM (D1 domain) accessible by all system masters except BDMA\n *      through D1 domain AXI bus matrix\n *\n *      2.1) 512Kb of SRAM beginning at address 0x2400:0000\n *\n *   3) AHB SRAM (D2 domain) accessible by all system masters except BDMA\n *      through D2 domain AHB bus matrix\n *\n *      3.1) 128Kb of SRAM1 beginning at address 0x3000:0000\n *      3.2) 128Kb of SRAM2 beginning at address 0x3002:0000\n *      3.3)  32Kb of SRAM3 beginning at address 0x3004:0000\n *\n *      SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000\n *\n *   4) AHB SRAM (D3 domain) accessible by most of system masters\n *      through D3 domain AHB bus matrix\n *\n *      4.1)  64Kb of SRAM4 beginning at address 0x3800:0000\n *      4.1)   4Kb of backup RAM beginning at address 0x3880:0000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0800:0000 address range.\n *\/\n\nMEMORY\n{\n\tITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K\n\tFLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K\n\n\tDTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K\n\tDTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K\n\tAXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K \/* D1 domain AXI bus *\/\n\tSRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K \/* D2 domain AHB bus *\/\n\tSRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K \/* D2 domain AHB bus *\/\n\tSRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K \/* D2 domain AHB bus *\/\n\tSRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K \/* D3 domain *\/\n\tBKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K\n}\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nENTRY(_stext)\n\n\/*\n * Ensure that abort() is present in the final object.  The exception handling\n * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).\n *\/\nEXTERN(abort)\nEXTERN(_bootdelay_signature)\n\nSECTIONS\n{\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t. = ALIGN(32);\n\t\t\/*\n\t\tThis signature provides the bootloader with a way to delay booting\n\t\t*\/\n\t\t_bootdelay_signature = ABSOLUTE(.);\n\t\tFILL(0xffecc2925d7d05c5)\n\t\t. += 8;\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\n\t} > FLASH\n\n\t\/*\n\t * Init functions (static constructors and the like)\n\t *\/\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\tKEEP(*(.init_array .init_array.*))\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH\n\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > AXI_SRAM AT > FLASH\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > AXI_SRAM\n\n\t\/* Emit the the D3 power domain section for locating BDMA data *\/\n\t.sram4 (NOLOAD) :\n\t{\n\t} > SRAM4\n\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.ramfunc : {\n\t\t_sramfuncs = .;\n\t\t*(.ramfunc  .ramfunc.*)\n\t\t. = ALIGN(4);\n\t\t_eramfuncs = .;\n\t} > ITCM_RAM AT > FLASH\n\n\t_framfuncs = LOADADDR(.ramfunc);\n}\n","old_contents":"\/****************************************************************************\n * scripts\/script.ld\n *\n *   Copyright (C) 2021 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The board uses an STM32H743XIH6 and has 2048Kb of main FLASH memory.\n * The flash memory is partitioned into a User Flash memory and a System\n * Flash memory. Each of these memories has two banks:\n *\n *   1) User Flash memory:\n *\n *      Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each\n *      Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each\n *\n *   2) System Flash memory:\n *\n *      Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector\n *      Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector\n *\n *   3) User option bytes for user configuration, only in Bank 1.\n *\n * In the STM32H743II, two different boot spaces can be selected through\n * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and\n * BOOT_ADD1 option bytes:\n *\n *   1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].\n *      ST programmed value: Flash memory at 0x0800:0000\n *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].\n *      ST programmed value: System bootloader at 0x1FF0:0000\n *\n * There's a switch on board, the BOOT0 pin is at ground so by default,\n * the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is\n * drepresed, then the boot will be from 0x1FF0:0000\n *\n * The STM32H743ZI also has 1024Kb of data SRAM.\n * SRAM is split up into several blocks and into three power domains:\n *\n *   1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with\n *      0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus\n *\n *      1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000\n *\n *           The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit\n *           DTCM ports. The DTCM-RAM could be used for critical real-time\n *           data, such as interrupt service routines or stack \/ heap memory.\n *           Both DTCM-RAMs can be used in parallel (for load\/store operations)\n *           thanks to the Cortex-M7 dual issue capability.\n *\n *      1.2)  64Kb of ITCM-RAM beginning at address 0x0000:0000\n *\n *           This RAM is connected to ITCM 64-bit interface designed for\n *           execution of critical real-times routines by the CPU.\n *\n *   2) AXI SRAM (D1 domain) accessible by all system masters except BDMA\n *      through D1 domain AXI bus matrix\n *\n *      2.1) 512Kb of SRAM beginning at address 0x2400:0000\n *\n *   3) AHB SRAM (D2 domain) accessible by all system masters except BDMA\n *      through D2 domain AHB bus matrix\n *\n *      3.1) 128Kb of SRAM1 beginning at address 0x3000:0000\n *      3.2) 128Kb of SRAM2 beginning at address 0x3002:0000\n *      3.3)  32Kb of SRAM3 beginning at address 0x3004:0000\n *\n *      SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000\n *\n *   4) AHB SRAM (D3 domain) accessible by most of system masters\n *      through D3 domain AHB bus matrix\n *\n *      4.1)  64Kb of SRAM4 beginning at address 0x3800:0000\n *      4.1)   4Kb of backup RAM beginning at address 0x3880:0000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0800:0000 address range.\n *\/\n\nMEMORY\n{\n\tITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K\n\tFLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K\n\n\tDTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K\n\tDTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K\n\tAXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K \/* D1 domain AXI bus *\/\n\tSRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K \/* D2 domain AHB bus *\/\n\tSRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K \/* D2 domain AHB bus *\/\n\tSRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K \/* D2 domain AHB bus *\/\n\tSRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K \/* D3 domain *\/\n\tBKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K\n}\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nENTRY(_stext)\n\n\/*\n * Ensure that abort() is present in the final object.  The exception handling\n * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).\n *\/\nEXTERN(abort)\nEXTERN(_bootdelay_signature)\n\nSECTIONS\n{\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t. = ALIGN(32);\n\t\t\/*\n\t\tThis signature provides the bootloader with a way to delay booting\n\t\t*\/\n\t\t_bootdelay_signature = ABSOLUTE(.);\n\t\tFILL(0xffecc2925d7d05c5)\n\t\t. += 8;\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\n\t} > FLASH\n\n\t\/*\n\t * Init functions (static constructors and the like)\n\t *\/\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\tKEEP(*(.init_array .init_array.*))\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH\n\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > AXI_SRAM AT > FLASH\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > AXI_SRAM\n\n\t\/* Emit the the D3 power domain section for locating BDMA data *\/\n\t.SRAM4 (NOLOAD) :\n\t{\n\t} > SRAM4\n\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.ramfunc : {\n\t\t_sramfuncs = .;\n\t\t*(.ramfunc  .ramfunc.*)\n\t\t. = ALIGN(4);\n\t\t_eramfuncs = .;\n\t} > ITCM_RAM AT > FLASH\n\n\t_framfuncs = LOADADDR(.ramfunc);\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"bc2748bba01c44c1f1a00755ca7dfef928e72ca6","subject":"fix(x86_64\/linker.ld): put boot\/GDT in a page-aligned ELF section","message":"fix(x86_64\/linker.ld): put boot\/GDT in a page-aligned ELF section\n\nThis may not be the Right Way to do this, but it works for now &\nprevents crashes.\n","repos":"hawkw\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .rodata :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n        *(.rodata .rodata.*)\n        . = ALIGN(4K);\n    }\n\n    .boot : ALIGN(4K)\n    {\n        KEEP(*(.boot._start))\n        libboot.a(*)\n        KEEP(*(.gdt))\n        . = ALIGN(4K);\n    }\n\n    .text :\n    {\n     \/* NOTE we use KEEP here to prevent the linker from dropping\n        these symbols\n      *\/\n        KEEP(*(.text.arch_init))\n        *(.text .text.*)\n        . = ALIGN(4K);\n    }\n\n     .data :\n     {\n       *(.data .data.*)\n       . = ALIGN(4K);\n     }\n\n     .bss :\n     {\n         *(.bss .bss.*)\n         . = ALIGN(4K);\n        \/* Page-Map Level-4 Table (PML4) *\/\n        pml4_table = .;\n        . += 4K;\n        \/* Page-Directory Pointer Table (PDP) *\/\n        pdp_table = .;\n        . += 4K;\n        \/* Page-Directory Table (PD) *\/\n        pd_table = .;\n        . += 4K;\n            . = ALIGN(4K);\n        stack_base = .;\n        . += 4K * 8;\n        stack_top = .;\n            . = ALIGN(4K);\n        heap_base_addr = .;\n        . += 4K * 2K;\n        heap_top_addr = .;\n        . = ALIGN(4K);\n     }\n\n    .got :\n    {\n      *(.got)\n      . = ALIGN(4K);\n    }\n\n    .got.plt :\n    {\n      *(.got.plt)\n      . = ALIGN(4K);\n    }\n\n    .data.rel.ro : ALIGN(4K) {\n      *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n      . = ALIGN(4K);\n    }\n\n    .gcc_except_table : ALIGN(4K) {\n      *(.gcc_except_table)\n      . = ALIGN(4K);\n}\n}\n","old_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .rodata :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n        *(.rodata .rodata.*)\n        . = ALIGN(4K);\n    }\n\n    .text ALIGN(4K) :\n    {\n     \/* NOTE we use KEEP here to prevent the linker from dropping\n        these symbols\n      *\/\n        KEEP(*(.text._start))\n        KEEP(*(.text.arch_init))\n        *(.text .text.*)\n    }\n\n     .data ALIGN(4K) :\n     {\n       *(.data .data.*)\n     }\n\n     .bss ALIGN(4K) :\n     {\n\n        *(.bss .bss.*)\n        . = ALIGN(4K);\n\n        \/* Page-Map Level-4 Table (PML4) *\/\n        pml4_table = .;\n        . += 4K;\n        \/* Page-Directory Pointer Table (PDP) *\/\n        pdp_table = .;\n        . += 4K;\n        \/* Page-Directory Table (PD) *\/\n        pd_table = .;\n        . += 4K;\n\n        stack_base = .;\n        . += 4K * 8;\n        stack_top = .;\n\n        heap_base_addr = .;\n        . += 4K * 2K;\n        heap_top_addr = .;\n     }\n\n    .got :\n    {\n      *(.got)\n      . = ALIGN(4K);\n    }\n\n    .got.plt :\n    {\n      *(.got.plt)\n      . = ALIGN(4K);\n    }\n\n    .data.rel.ro : ALIGN(4K) {\n      *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n      . = ALIGN(4K);\n    }\n\n    .gcc_except_table : ALIGN(4K) {\n      *(.gcc_except_table)\n      . = ALIGN(4K);\n}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f38e12f0abaf9a1a0ae84a0240958a27d99425ff","subject":"Update ports\/stm32f4\/boards\/STM32F405_boot.ld","message":"Update ports\/stm32f4\/boards\/STM32F405_boot.ld\n\nCo-Authored-By: Scott Shawcroft <625600233cb3bcab32268c17610882e0fdaed295@tannewt.org>","repos":"adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython","old_file":"ports\/stm32f4\/boards\/STM32F405_boot.ld","new_file":"ports\/stm32f4\/boards\/STM32F405_boot.ld","new_contents":"\/*\n    GNU linker script for STM32F405 with bootloader\n    Based on Micropython\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08010000, LENGTH = 1024K - 64K         \/* entire flash, sans bootloader region *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08010000, LENGTH = 64K                 \/* sector 0 *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 1024K - 64K - 64K   \/* sectors 5+ *\/\n    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 64K\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        \/* This first flash block is 16K annd the isr vectors only take up\n           about 400 bytes. Micropython pads this with files, but this didn't\n           work with the size of Circuitpython's ff object. *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n\n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT> FLASH_TEXT\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_heap_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n","old_contents":"\/*\n    GNU linker script for STM32F405 with bootloader\n    Based on Micropython\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08010000, LENGTH = 1024K - 64K         \/* entire flash, sans bootloader region *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08010000, LENGTH = 64K                 \/* sector 0 *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 1024K - 64K - 64K   \/* sectors 5+ *\/\n    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 64K\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        \/* This first flash block is 16K annd the isr vectors only take up\n           about 400 bytes. Micropython pads this with files, but this didn't\n           work with the size of Circuitpython's ff object. *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n\n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT> FLASH_TEXT\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_heap_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f5f8deb7ef24c6bd37082716114e7f21e0bc5ba3","subject":"heap and stack test","message":"heap and stack test\n","repos":"mikaleppanen\/mbed-os,YarivCol\/mbed-os,fahhem\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,mmorenobarm\/mbed-os,jeremybrodt\/mbed,bcostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,kjbracey-arm\/mbed,adamgreen\/mbed,YarivCol\/mbed-os,tung7970\/mbed-os-1,ryankurte\/mbed-os,mikaleppanen\/mbed-os,mmorenobarm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,andreaslarssonublox\/mbed,j-greffe\/mbed-os,adamgreen\/mbed,YarivCol\/mbed-os,fvincenzo\/mbed-os,nRFMesh\/mbed-os,adustm\/mbed,bcostm\/mbed-os,catiedev\/mbed-os,monkiineko\/mbed-os,NXPmicro\/mbed,catiedev\/mbed-os,nRFMesh\/mbed-os,karsev\/mbed-os,c1728p9\/mbed-os,kl-cruz\/mbed-os,Archcady\/mbed-os,monkiineko\/mbed-os,cvtsi2sd\/mbed-os,mazimkhan\/mbed-os,pradeep-gr\/mbed-os5-onsemi,jeremybrodt\/mbed,j-greffe\/mbed-os,andcor02\/mbed-os,catiedev\/mbed-os,bcostm\/mbed-os,mmorenobarm\/mbed-os,karsev\/mbed-os,CalSol\/mbed,fahhem\/mbed-os,cvtsi2sd\/mbed-os,NXPmicro\/mbed,cvtsi2sd\/mbed-os,fanghuaqi\/mbed,svogl\/mbed-os,catiedev\/mbed-os,HeadsUpDisplayInc\/mbed,jeremybrodt\/mbed,mbedmicro\/mbed,theotherjimmy\/mbed,Archcady\/mbed-os,pradeep-gr\/mbed-os5-onsemi,maximmbed\/mbed,nRFMesh\/mbed-os,netzimme\/mbed-os,theotherjimmy\/mbed,c1728p9\/mbed-os,bulislaw\/mbed-os,ryankurte\/mbed-os,tung7970\/mbed-os-1,monkiineko\/mbed-os,bcostm\/mbed-os,svogl\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,karsev\/mbed-os,fanghuaqi\/mbed,fahhem\/mbed-os,betzw\/mbed-os,svastm\/mbed,tung7970\/mbed-os-1,screamerbg\/mbed,bulislaw\/mbed-os,j-greffe\/mbed-os,catiedev\/mbed-os,mbedmicro\/mbed,CalSol\/mbed,adustm\/mbed,kl-cruz\/mbed-os,pradeep-gr\/mbed-os5-onsemi,andcor02\/mbed-os,maximmbed\/mbed,ryankurte\/mbed-os,mbedmicro\/mbed,nRFMesh\/mbed-os,mazimkhan\/mbed-os,mazimkhan\/mbed-os,netzimme\/mbed-os,mikaleppanen\/mbed-os,mazimkhan\/mbed-os,pradeep-gr\/mbed-os5-onsemi,radhika-raghavendran\/mbed-os5.1-onsemi,betzw\/mbed-os,fahhem\/mbed-os,mazimkhan\/mbed-os,c1728p9\/mbed-os,andcor02\/mbed-os,adustm\/mbed,andreaslarssonublox\/mbed,tung7970\/mbed-os,adamgreen\/mbed,HeadsUpDisplayInc\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,nvlsianpu\/mbed,RonEld\/mbed,kjbracey-arm\/mbed,betzw\/mbed-os,infinnovation\/mbed-os,kjbracey-arm\/mbed,betzw\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,nRFMesh\/mbed-os,andreaslarssonublox\/mbed,CalSol\/mbed,HeadsUpDisplayInc\/mbed,svastm\/mbed,theotherjimmy\/mbed,bulislaw\/mbed-os,Archcady\/mbed-os,tung7970\/mbed-os,karsev\/mbed-os,mikaleppanen\/mbed-os,j-greffe\/mbed-os,ryankurte\/mbed-os,adustm\/mbed,maximmbed\/mbed,adustm\/mbed,CalSol\/mbed,nvlsianpu\/mbed,monkiineko\/mbed-os,betzw\/mbed-os,mmorenobarm\/mbed-os,svastm\/mbed,YarivCol\/mbed-os,netzimme\/mbed-os,fvincenzo\/mbed-os,bcostm\/mbed-os,arostm\/mbed-os,screamerbg\/mbed,NXPmicro\/mbed,mikaleppanen\/mbed-os,Archcady\/mbed-os,nvlsianpu\/mbed,bulislaw\/mbed-os,bcostm\/mbed-os,infinnovation\/mbed-os,adamgreen\/mbed,arostm\/mbed-os,kl-cruz\/mbed-os,CalSol\/mbed,tung7970\/mbed-os-1,adamgreen\/mbed,theotherjimmy\/mbed,tung7970\/mbed-os-1,HeadsUpDisplayInc\/mbed,RonEld\/mbed,infinnovation\/mbed-os,CalSol\/mbed,fvincenzo\/mbed-os,nvlsianpu\/mbed,arostm\/mbed-os,RonEld\/mbed,j-greffe\/mbed-os,catiedev\/mbed-os,maximmbed\/mbed,fvincenzo\/mbed-os,netzimme\/mbed-os,mmorenobarm\/mbed-os,andcor02\/mbed-os,screamerbg\/mbed,kl-cruz\/mbed-os,RonEld\/mbed,andreaslarssonublox\/mbed,HeadsUpDisplayInc\/mbed,ryankurte\/mbed-os,j-greffe\/mbed-os,infinnovation\/mbed-os,tung7970\/mbed-os,cvtsi2sd\/mbed-os,maximmbed\/mbed,fanghuaqi\/mbed,nvlsianpu\/mbed,andreaslarssonublox\/mbed,theotherjimmy\/mbed,svastm\/mbed,andcor02\/mbed-os,infinnovation\/mbed-os,RonEld\/mbed,fanghuaqi\/mbed,bulislaw\/mbed-os,mbedmicro\/mbed,arostm\/mbed-os,netzimme\/mbed-os,mikaleppanen\/mbed-os,kl-cruz\/mbed-os,maximmbed\/mbed,adustm\/mbed,svogl\/mbed-os,mmorenobarm\/mbed-os,kjbracey-arm\/mbed,NXPmicro\/mbed,ryankurte\/mbed-os,arostm\/mbed-os,nvlsianpu\/mbed,theotherjimmy\/mbed,Archcady\/mbed-os,RonEld\/mbed,cvtsi2sd\/mbed-os,YarivCol\/mbed-os,andcor02\/mbed-os,svogl\/mbed-os,betzw\/mbed-os,fahhem\/mbed-os,fvincenzo\/mbed-os,YarivCol\/mbed-os,fahhem\/mbed-os,mazimkhan\/mbed-os,mbedmicro\/mbed,screamerbg\/mbed,nRFMesh\/mbed-os,kl-cruz\/mbed-os,tung7970\/mbed-os,infinnovation\/mbed-os,arostm\/mbed-os,monkiineko\/mbed-os,svastm\/mbed,monkiineko\/mbed-os,c1728p9\/mbed-os,screamerbg\/mbed,cvtsi2sd\/mbed-os,bulislaw\/mbed-os,tung7970\/mbed-os,jeremybrodt\/mbed,karsev\/mbed-os,NXPmicro\/mbed,Archcady\/mbed-os,karsev\/mbed-os,svogl\/mbed-os,adamgreen\/mbed,c1728p9\/mbed-os,NXPmicro\/mbed,svogl\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,screamerbg\/mbed,jeremybrodt\/mbed,netzimme\/mbed-os,fanghuaqi\/mbed","old_file":"hal\/targets\/cmsis\/TARGET_ONSEMI\/TARGET_NCS36510\/TOOLCHAIN_GCC_ARM\/NCS36510.ld","new_file":"hal\/targets\/cmsis\/TARGET_ONSEMI\/TARGET_NCS36510\/TOOLCHAIN_GCC_ARM\/NCS36510.ld","new_contents":"\/*\n * NCS36510 ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x00003000, LENGTH = 0x00000090\n  FLASH (rx)            : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90\n  RAM (rwx)             : ORIGIN = 0x3FFF4000, LENGTH = 48K \n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        . = ALIGN(32);\n        __uvisor_bss_end = .;\n    } > RAM\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assetions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += 0x4000;\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += 0x800 - (. - __StackLimit);\n    } > RAM\n\n    \/* Set stack top to end of RAM *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack);\n    PROVIDE(__stack = __StackTop);\n\n}\n","old_contents":"\/*\n * K64F ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x00003000, LENGTH = 0x00000090\n  FLASH (rx)            : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90\n  RAM (rwx)             : ORIGIN = 0x3FFF4000, LENGTH = 48K \n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        . = ALIGN(32);\n        __uvisor_bss_end = .;\n    } > RAM\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assetions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += 0x4000;\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += 0x800 - (. - __StackLimit);\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bb527edcb8106013b68b4943d453e54ecab80edb","subject":"Revert \"Workaround for ld bug\"","message":"Revert \"Workaround for ld bug\"\n\nThis reverts commit c6a8c99fd629e59d5b2b7db4de14dd7fd3a55b06.\n\nThe ld bug has been fixed in ps3toolchain, so the workaround no\nlonger serves any purpose.\n","repos":"ps3dev\/PSL1GHT,ps3dev\/PSL1GHT,ps3dev\/PSL1GHT,ps3dev\/PSL1GHT","old_file":"ppu\/crt\/lv2.ld","new_file":"ppu\/crt\/lv2.ld","new_contents":"OUTPUT_FORMAT(\"elf64-powerpc\", \"elf64-powerpc\", \"elf64-powerpc\")\nOUTPUT_ARCH(powerpc:common64)\n\nENTRY(_start)\n\nPHDRS\n{\n\thdr_text\tPT_LOAD FILEHDR PHDRS\tFLAGS(0x01 | 0x04);\n\thdr_data\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04);\n\thdr_srodata\tPT_LOAD\t\t\t\t\tFLAGS(0x04 | 0x00400000);\n\thdr_sdata\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04 | 0x00200000 | 0x00400000);\n\thdr_rsx\t\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04 | 0x00200000 | 0x00400000 | 0x02000000 | 0x04000000);\n\thdr_tls\t\tPT_TLS\t\t\t\t\tFLAGS(0x04);\n\thdr_param\t0x60000001\t\t\t\tFLAGS(0x00);\n\thdr_prx\t\t0x60000002\t\t\t\tFLAGS(0x00);\n}\n\nSECTIONS\n{\n\tPROVIDE (__executable_start = 0x10000); . = 0x10000 + SIZEOF_HEADERS;\n\t.interp         : { *(.interp) } : hdr_text\n\t.hash           : { *(.hash) }\n\t.dynsym         : { *(.dynsym) }\n\t.dynstr         : { *(.dynstr) }\n\t.gnu.version    : { *(.gnu.version) }\n\t.gnu.version_d  : { *(.gnu.version_d) }\n\t.gnu.version_r  : { *(.gnu.version_r) }\n\t.rel.dyn\t\t:\n\t  {\n\t    *(.rel.init)\n\t    *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n\t    *(.rel.fini)\n\t    *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n\t    *(.rel.data.rel.ro*)\n\t    *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n\t    *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n\t    *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n\t    *(.rel.ctors)\n\t    *(.rel.dtors)\n\t    *(.rel.got)\n\t    *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)\n\t    *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)\n\t    *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)\n\t    *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)\n\t    *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n\t  }\n\n\t.rela.dyn\t\t:\n\t  {\n\t    *(.rela.init)\n\t    *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n\t    *(.rela.fini)\n\t    *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n\t    *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n\t    *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n\t    *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n\t    *(.rela.ctors)\n\t    *(.rela.dtors)\n\t    *(.rela.got)\n\t    *(.rela.toc)\n\t    *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)\n\t    *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)\n\t    *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)\n\t    *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)\n\t    *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n\t  }\n\t.rel.plt        : { *(.rel.plt) }\n\t.rela.plt       : { *(.rela.plt) }\n\t.rela.tocbss    : { *(.rela.tocbss) }\n\t.init           : {\n\t\tKEEP (*(.init))\n\t} = 0x60000000\n\t.text           : {\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\tKEEP (*(.text.*personality*))\n\t\t\/* .gnu.warning sections are handled specially by elf32.em.  *\/\n\t\t*(.gnu.warning)\n\t\t*(.sfpr .glink)\n\t} = 0x60000000\n\t.fini           : {\n\t\tKEEP (*(.fini))\n\t} = 0x60000000\n\t.sceStub.text   : {\n\t\t*(.sceStub.text)\n\t\t*(SORT(.sceStub.text.*))\n\t}\n\tPROVIDE (__etext = .);\n\tPROVIDE (_etext = .);\n\tPROVIDE (etext = .);\n\n\t.eh_frame_hdr : { *(.eh_frame_hdr) }\n\t.eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n\t.gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n\n\t.rodata.sceResident : { KEEP (*(.rodata.sceResident)) }\n\t.rodata.sceFNID     : { KEEP (*(.rodata.sceFNID .rodata.sceFNID.*)) }\n\t.rodata.sceVNID     : { KEEP (*(.rodata.sceVNID .rodata.sceVNID.*)) }\n\t.rodata.sceTNID     : { KEEP (*(.rodata.sceTNID .rodata.sceTNID.*)) }\n\t.rodata.sceVStub    : { KEEP (*(.rodata.sceVStub)) KEEP (*(SORT(.rodata.sceVStub.*))) }\n\n\tPROVIDE (__libentstart = .);\n\t.lib.ent.top : { KEEP (*(.lib.ent.top)) }\n\t.lib.ent\t : { KEEP (*(.lib.ent)) }\n\t.lib.ent.btm : { KEEP (*(.lib.ent.btm)) }\n\tPROVIDE (__libentend = .);\n\n\tPROVIDE (__libstubstart = .);\n\t.lib.stub.top : { KEEP (*(.lib.stub.top)) }\n\t.lib.stub\t  : { KEEP (*(.lib.stub)) }\n\t.lib.stub.btm : { KEEP (*(.lib.stub.btm)) }\n\tPROVIDE (__libstubend = .);\n\n\t.ppu_rodata         : { *(.ppu_rodata .ppu_rodata.*) }\n\t.sys_proc_param     : { KEEP (*(.sys_proc_param)) } : hdr_text : hdr_param\n\t.sys_proc_prx_param : { KEEP (*(.sys_proc_prx_param)) } : hdr_text : hdr_prx\n\n\t. = ALIGN(64K);\n\t\n\t.ppu_data           : { *(.ppu_data .ppu_data.*) } : hdr_data\n\t.sdata2             : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }\n\t.sbss2              : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }\n\n\t\/* Exception handling  *\/\n\t.eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n\t.gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n\t\n\t. = ALIGN(64 \/ 8);\n\t\n\t.preinit_array     : {\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\t}\n\t.init_array     : {\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\t}\n\t.fini_array     : {\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\t}\n\t.ctors          : {\n\t\t\/* gcc uses crtbegin.o to find the start of\n\t\t   the constructors, so we make sure it is\n\t\t   first.  Because this is a wildcard, it\n\t\t   doesn't matter if the user does not\n\t\t   actually link against crtbegin.o; the\n\t\t   linker won't look for a file to match a\n\t\t   wildcard.  The wildcard also means that it\n\t\t   doesn't matter which directory crtbegin.o\n\t\t   is in.  *\/\n\t\tKEEP (*crtbegin.o(.ctors))\n\t\tKEEP (*crtbegin?.o(.ctors))\n\t\t\/* We don't want to include the .ctor section from\n\t\t   the crtend.o file until after the sorted ctors.\n\t\t   The .ctor section from the crtend file contains the\n\t\t   end of ctors marker and it must be last *\/\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t}\n\t.dtors          : {\n\t\tKEEP (*crtbegin.o(.dtors))\n\t\tKEEP (*crtbegin?.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t}\n\t.jcr            : { KEEP (*(.jcr)) }\n\t.data.rel.ro : { *(.data.rel.ro.local*) *(.data.rel.ro*) }\n\t.dynamic        : { *(.dynamic) }\n\n\t.data.sceFStub      : { KEEP (*(.data.sceFStub)) KEEP (*(SORT(.data.sceFStub.*))) }\n\t\n\t.toc1\t\t  : ALIGN(8) { *(.toc1) }\n\t.opd\t\t  : ALIGN(8) { KEEP (*(.opd)) }\n\t.branch_lt\t  : ALIGN(8) { *(.branch_lt) }\n\t.got\t\t  : ALIGN(8) { *(.got .toc) }\n\t.toc.sceStub  : { KEEP (*(.toc.sceStub)) KEEP (*(SORT(.toc.sceStub.*))) }\n\t\n\t\/* Thread Local Storage sections  *\/\n\t.tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } : hdr_data : hdr_tls\n\t.tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } : hdr_data : hdr_tls\n\t\n\t. = ALIGN(256M);\n\n\t.rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } : hdr_srodata\n\t.rodata1        : { *(.rodata1) } : hdr_srodata\n\n\t.spu_image\t\t: { *(.spu_image .spu_image.*) } : hdr_srodata\n\t\n\t. = ALIGN(64K);\n\n\t.data           :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tKEEP (*(.gnu.linkonce.d.*personality*))\n\t\tSORT(CONSTRUCTORS)\n\t} : hdr_sdata\n\t.data1          : { *(.data1) }\n\n  \/* We want the small data sections together, so single-instruction offsets\n     can access them all, and initialized data all before uninitialized, so\n     we can shorten the on-disk segment size.  *\/\n\t.sdata          : {\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t}\n\t_edata = .;\n\tPROVIDE (edata = .);\n\n\t__bss_start = .;\n\t.tocbss\t  : ALIGN(8) { *(.tocbss)}\n\t.sbss           :\n\t{\n\t\tPROVIDE (__sbss_start = .);\n\t\tPROVIDE (___sbss_start = .);\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\tPROVIDE (__sbss_end = .);\n\t\tPROVIDE (___sbss_end = .);\n\t}\n\t.plt            : { *(.plt) }\n\t.bss            :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t\/* Align here to ensure that the .bss section occupies space up to\n\t\t   _end.  Align after .bss to ensure correct alignment even if the\n\t\t   .bss section disappears because there are no input sections.\n\t\t   FIXME: Why do we need it? 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When there is no .bss section, we don't\n\t\t   pad the .data section.  *\/\n\t\t. = ALIGN(64 \/ 8);\n\t}\n\t\n\t. = ALIGN(256M);\n\n\t.rsx_image\t: { *(.rsx_*) } : hdr_rsx\n\t\t\n\t_end = .;\n\t__end = .;\n\tPROVIDE (end = .);\n\t\n\t. = ALIGN(8);\n\t\n\t\/* Stabs debugging sections.  *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment       0 : { *(.comment) }\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0.  *\/\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\n\t.debug_typenames 0 : { *(.debug_typenames) }\n\t.debug_varnames  0 : { *(.debug_varnames) }\n\t\/* DWARF 3 *\/\n\t.debug_pubtypes 0 : { *(.debug_pubtypes) }\n\t.debug_ranges   0 : { *(.debug_ranges) }\n\t.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n\t\/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"d67c1f389d7851e01ddde7c4016f3af0826e46a7","subject":"riscv: Fix C++ exception handling info linking","message":"riscv: Fix C++ exception handling info linking\n\nThe RISC-V architecture linker script was including `cplusplus-ram.ld`\nlinker script before `__data_region_start`, and this caused the content\nof `.gcc_except_table` section to be not copied to the RAM by the\n`z_data_copy` function; leading to the C++ exception handling\nmalfunction.\n\nThis commit relocates the `cplusplus-ram.ld` linker script inclusion\nsuch that the contents of the relevant sections are properly copied by\nthe `z_data_copy` function.\n\nSigned-off-by: Stephanos Ioannidis <dc76e9f0c0006e8f919e0c515c66dbba3982f785@stephanos.io>\n","repos":"galak\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c1ca7a15109c1f02f8f61d17f60aecbb38e41fdb","subject":"Fixed STM32F334 linker section addresses and attributes","message":"Fixed STM32F334 linker section addresses and attributes\n","repos":"cvra\/can-bootloader,cvra\/can-bootloader,cvra\/can-bootloader,cvra\/can-bootloader","old_file":"platform\/nucleo-board-stm32f334r8\/linkerscript.ld","new_file":"platform\/nucleo-board-stm32f334r8\/linkerscript.ld","new_contents":"\/*\n * Linker file for the STM32F334R8 microcontroller\n * http:\/\/www.st.com\/en\/microcontrollers\/stm32f334r8.html\n *\n * 64K flash memory, 12K RAM, 4K CCRAM\n * Flash page size: 2K (= 0x800)\n *\n * TODO: Complete section definitions below with definitions for CCRAM \n *\/\n\nMEMORY\n{\n    FLASH_TEXT    (RX) : ORIGIN = 0x08000000, LENGTH = 20K\n    FLASH_CONFIG1 (RX) : ORIGIN = 0x08005000, LENGTH = 2K\n    FLASH_CONFIG2 (RX) : ORIGIN = 0x08005800, LENGTH = 2K\n    FLASH_APP     (RX) : ORIGIN = 0x08006000, LENGTH = 40K\n    RAM          (RWX) : ORIGIN = 0x20000000, LENGTH = 12K\n    CCRAM        (RWX) : ORIGIN = 0x10000000, LENGTH = 4K\n}\n\nREGION_ALIAS(\"REGION_TEXT\",   FLASH_TEXT);\nREGION_ALIAS(\"REGION_RODATA\", FLASH_TEXT);\nREGION_ALIAS(\"REGION_DATA\",   RAM);\nREGION_ALIAS(\"REGION_BSS\",    RAM);\nREGION_ALIAS(\"REGION_NOINIT\", RAM);\n\nEXTERN(vector_table)\n\nENTRY(reset_handler)\n\nSECTIONS\n{\n    \/* config flash page *\/\n    config_page1 = ORIGIN(FLASH_CONFIG1);\n    config_page2 = ORIGIN(FLASH_CONFIG2);\n\n    \/* application in flash *\/\n    application_address = ORIGIN(FLASH_APP);\n    application_size = LENGTH(FLASH_APP);\n\n    .text :\n    {\n        *(.vectors) \/* vector_table *\/\n\n        _stext = .;\n\n        CREATE_OBJECT_SYMBOLS\n\n        *(.text .text.*)        \/* Program code *\/\n        *(.gnu.linkonce.t.*)\n\n\n        *(.plt)\n        *(.gnu.warning)\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\n\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _etext = .;\n    } > REGION_TEXT\n\n    .rodata :\n    {\n        . = ALIGN(4);\n        KEEP(*(.rodata.keep .rodata.keep.*))\n        *(.rodata .rodata.*)    \/* Read only data *\/\n        . = ALIGN(4);\n    } > REGION_RODATA\n\n    \/*\n     * .ARM.exidx exception unwinding; mandated by ARM's C++ ABI\n     *\/\n    __exidx_start = .;\n    .ARM.exidx :\n      {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n      } > REGION_RODATA\n    __exidx_end = .;\n\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        _data = _sdata;\n\n        *(.got.plt) *(.got)\n\n        *(.data .data.*)        \/* Data memory *\/\n        *(.gnu.linkonce.d.*)\n\n        . = ALIGN(4);\n        *(.fastrun .fastrun.*)  \/* Functions in RAM *\/\n\n        . = ALIGN(4);\n        _edata = .;\n    } > REGION_DATA AT > REGION_RODATA\n    _ldata = LOADADDR(.data);\n    _data_loadaddr = _ldata;\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n\n        *(.bss .bss.*)          \/* Zero-filled data memory *\/\n        *(.gnu.linkonce.b.*)\n\n        . = ALIGN(4);\n        _ebss = .;\n    } > REGION_BSS\n\n    .noinit :\n    {\n        _snoinit = .;\n        . = ALIGN(4);\n\n        *(.noinit .noinit.*)\n\n        . = ALIGN(4);\n        _enoinit = .;\n    } > REGION_NOINIT\n\n    . = ALIGN(8);\n    _sheap = .;\n    _sstack = .;\n\n    \/* default stack at the end of RAM *\/\n    _eram = ORIGIN(RAM) + LENGTH(RAM);\n    _eheap = _eram;\n    _estack = _eram;\n    _stack = _eram;\n\n    \/*\n     * Debugging sections\n     *\/\n    .stab 0 (NOLOAD) : { *(.stab) }\n    .stabstr 0 (NOLOAD) : { *(.stabstr) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n\n    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n    .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n * Linker file for the STM32F334R8 microcontroller\n * http:\/\/www.st.com\/en\/microcontrollers\/stm32f334r8.html\n *\n * 64K flash memory, 12K RAM, 4K CCRAM\n * Flash page size: 2K (= 0x800)\n *\n * TODO: Complete section definitions below with definitions for CCRAM \n *\/\n\nMEMORY\n{\n    FLASH_TEXT    (RX) : ORIGIN = 0x08000000, LENGTH = 20K\n    FLASH_CONFIG1 (RX) : ORIGIN = 0x08005000, LENGTH = 2K\n    FLASH_CONFIG2 (RX) : ORIGIN = 0x08005800, LENGTH = 2K\n    FLASH_APP     (RX) : ORIGIN = 0x08006000, LENGTH = 44K\n    RAM       (RWXAIL) : ORIGIN = 0x20000000, LENGTH = 12K\n    CCRAM         (RW) : ORIGIN = 0x20003000, LENGTH = 4K\n}\n\nREGION_ALIAS(\"REGION_TEXT\",   FLASH_TEXT);\nREGION_ALIAS(\"REGION_RODATA\", FLASH_TEXT);\nREGION_ALIAS(\"REGION_DATA\",   RAM);\nREGION_ALIAS(\"REGION_BSS\",    RAM);\nREGION_ALIAS(\"REGION_NOINIT\", RAM);\n\nEXTERN(vector_table)\n\nENTRY(reset_handler)\n\nSECTIONS\n{\n    \/* config flash page *\/\n    config_page1 = ORIGIN(FLASH_CONFIG1);\n    config_page2 = ORIGIN(FLASH_CONFIG2);\n\n    \/* application in flash *\/\n    application_address = ORIGIN(FLASH_APP);\n    application_size = LENGTH(FLASH_APP);\n\n    .text :\n    {\n        *(.vectors) \/* vector_table *\/\n\n        _stext = .;\n\n        CREATE_OBJECT_SYMBOLS\n\n        *(.text .text.*)        \/* Program code *\/\n        *(.gnu.linkonce.t.*)\n\n\n        *(.plt)\n        *(.gnu.warning)\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\n\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _etext = .;\n    } > REGION_TEXT\n\n    .rodata :\n    {\n        . = ALIGN(4);\n        KEEP(*(.rodata.keep .rodata.keep.*))\n        *(.rodata .rodata.*)    \/* Read only data *\/\n        . = ALIGN(4);\n    } > REGION_RODATA\n\n    \/*\n     * .ARM.exidx exception unwinding; mandated by ARM's C++ ABI\n     *\/\n    __exidx_start = .;\n    .ARM.exidx :\n      {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n      } > REGION_RODATA\n    __exidx_end = .;\n\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        _data = _sdata;\n\n        *(.got.plt) *(.got)\n\n        *(.data .data.*)        \/* Data memory *\/\n        *(.gnu.linkonce.d.*)\n\n        . = ALIGN(4);\n        *(.fastrun .fastrun.*)  \/* Functions in RAM *\/\n\n        . = ALIGN(4);\n        _edata = .;\n    } > REGION_DATA AT > REGION_RODATA\n    _ldata = LOADADDR(.data);\n    _data_loadaddr = _ldata;\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n\n        *(.bss .bss.*)          \/* Zero-filled data memory *\/\n        *(.gnu.linkonce.b.*)\n\n        . = ALIGN(4);\n        _ebss = .;\n    } > REGION_BSS\n\n    .noinit :\n    {\n        _snoinit = .;\n        . = ALIGN(4);\n\n        *(.noinit .noinit.*)\n\n        . = ALIGN(4);\n        _enoinit = .;\n    } > REGION_NOINIT\n\n    . = ALIGN(8);\n    _sheap = .;\n    _sstack = .;\n\n    \/* default stack at the end of RAM *\/\n    _eram = ORIGIN(RAM) + LENGTH(RAM);\n    _eheap = _eram;\n    _estack = _eram;\n    _stack = _eram;\n\n    \/*\n     * Debugging sections\n     *\/\n    .stab 0 (NOLOAD) : { *(.stab) }\n    .stabstr 0 (NOLOAD) : { *(.stabstr) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n\n    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n    .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"170ba1c802d5c36cf12eb3c842f5b95259c84c92","subject":"Move page heap after uVisor private data.","message":"Move page heap after uVisor private data.\n","repos":"jeremybrodt\/mbed,andreaslarssonublox\/mbed,YarivCol\/mbed-os,NXPmicro\/mbed,adamgreen\/mbed,HeadsUpDisplayInc\/mbed,maximmbed\/mbed,andreaslarssonublox\/mbed,j-greffe\/mbed-os,cvtsi2sd\/mbed-os,CalSol\/mbed,adustm\/mbed,NXPmicro\/mbed,tung7970\/mbed-os-1,mbedmicro\/mbed,andreaslarssonublox\/mbed,ryankurte\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,NXPmicro\/mbed,svogl\/mbed-os,fahhem\/mbed-os,HeadsUpDisplayInc\/mbed,andcor02\/mbed-os,bcostm\/mbed-os,netzimme\/mbed-os,HeadsUpDisplayInc\/mbed,karsev\/mbed-os,YarivCol\/mbed-os,ryankurte\/mbed-os,j-greffe\/mbed-os,arostm\/mbed-os,CalSol\/mbed,adustm\/mbed,karsev\/mbed-os,tung7970\/mbed-os,c1728p9\/mbed-os,CalSol\/mbed,j-greffe\/mbed-os,karsev\/mbed-os,fahhem\/mbed-os,kl-cruz\/mbed-os,theotherjimmy\/mbed,svastm\/mbed,mmorenobarm\/mbed-os,betzw\/mbed-os,YarivCol\/mbed-os,svastm\/mbed,betzw\/mbed-os,kl-cruz\/mbed-os,mazimkhan\/mbed-os,cvtsi2sd\/mbed-os,tung7970\/mbed-os,fvincenzo\/mbed-os,tung7970\/mbed-os,pradeep-gr\/mbed-os5-onsemi,HeadsUpDisplayInc\/mbed,tung7970\/mbed-os-1,screamerbg\/mbed,NXPmicro\/mbed,infinnovation\/mbed-os,bcostm\/mbed-os,c1728p9\/mbed-os,YarivCol\/mbed-os,fahhem\/mbed-os,fvincenzo\/mbed-os,bulislaw\/mbed-os,Archcady\/mbed-os,fanghuaqi\/mbed,catiedev\/mbed-os,c1728p9\/mbed-os,andcor02\/mbed-os,karsev\/mbed-os,Archcady\/mbed-os,karsev\/mbed-os,andreaslarssonublox\/mbed,fvincenzo\/mbed-os,kl-cruz\/mbed-os,adamgreen\/mbed,c1728p9\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,arostm\/mbed-os,Archcady\/mbed-os,mmorenobarm\/mbed-os,nvlsianpu\/mbed,j-greffe\/mbed-os,screamerbg\/mbed,Archcady\/mbed-os,andcor02\/mbed-os,ryankurte\/mbed-os,c1728p9\/mbed-os,RonEld\/mbed,monkiineko\/mbed-os,pradeep-gr\/mbed-os5-onsemi,adamgreen\/mbed,andcor02\/mbed-os,kl-cruz\/mbed-os,netzimme\/mbed-os,catiedev\/mbed-os,infinnovation\/mbed-os,mmorenobarm\/mbed-os,fanghuaqi\/mbed,fahhem\/mbed-os,theotherjimmy\/mbed,mikaleppanen\/mbed-os,netzimme\/mbed-os,adamgreen\/mbed,svogl\/mbed-os,arostm\/mbed-os,netzimme\/mbed-os,adamgreen\/mbed,nRFMesh\/mbed-os,adustm\/mbed,maximmbed\/mbed,fahhem\/mbed-os,monkiineko\/mbed-os,betzw\/mbed-os,fanghuaqi\/mbed,maximmbed\/mbed,ryankurte\/mbed-os,mmorenobarm\/mbed-os,catiedev\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,mazimkhan\/mbed-os,tung7970\/mbed-os,CalSol\/mbed,monkiineko\/mbed-os,svogl\/mbed-os,mmorenobarm\/mbed-os,adamgreen\/mbed,screamerbg\/mbed,cvtsi2sd\/mbed-os,netzimme\/mbed-os,tung7970\/mbed-os-1,mikaleppanen\/mbed-os,theotherjimmy\/mbed,HeadsUpDisplayInc\/mbed,cvtsi2sd\/mbed-os,fvincenzo\/mbed-os,nRFMesh\/mbed-os,betzw\/mbed-os,catiedev\/mbed-os,jeremybrodt\/mbed,fanghuaqi\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,karsev\/mbed-os,nRFMesh\/mbed-os,theotherjimmy\/mbed,betzw\/mbed-os,mbedmicro\/mbed,mikaleppanen\/mbed-os,cvtsi2sd\/mbed-os,RonEld\/mbed,RonEld\/mbed,jeremybrodt\/mbed,screamerbg\/mbed,cvtsi2sd\/mbed-os,netzimme\/mbed-os,andreaslarssonublox\/mbed,nvlsianpu\/mbed,maximmbed\/mbed,Archcady\/mbed-os,RonEld\/mbed,bcostm\/mbed-os,monkiineko\/mbed-os,svastm\/mbed,pradeep-gr\/mbed-os5-onsemi,fanghuaqi\/mbed,monkiineko\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,kjbracey-arm\/mbed,ryankurte\/mbed-os,catiedev\/mbed-os,bcostm\/mbed-os,adustm\/mbed,HeadsUpDisplayInc\/mbed,NXPmicro\/mbed,bulislaw\/mbed-os,infinnovation\/mbed-os,fahhem\/mbed-os,bulislaw\/mbed-os,theotherjimmy\/mbed,svastm\/mbed,maximmbed\/mbed,mazimkhan\/mbed-os,j-greffe\/mbed-os,kl-cruz\/mbed-os,bulislaw\/mbed-os,c1728p9\/mbed-os,Archcady\/mbed-os,nRFMesh\/mbed-os,mbedmicro\/mbed,fvincenzo\/mbed-os,mikaleppanen\/mbed-os,arostm\/mbed-os,svogl\/mbed-os,kjbracey-arm\/mbed,mikaleppanen\/mbed-os,bcostm\/mbed-os,nRFMesh\/mbed-os,tung7970\/mbed-os-1,svastm\/mbed,jeremybrodt\/mbed,adustm\/mbed,arostm\/mbed-os,bcostm\/mbed-os,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,nvlsianpu\/mbed,infinnovation\/mbed-os,andcor02\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,jeremybrodt\/mbed,arostm\/mbed-os,mazimkhan\/mbed-os,pradeep-gr\/mbed-os5-onsemi,mikaleppanen\/mbed-os,NXPmicro\/mbed,ryankurte\/mbed-os,nvlsianpu\/mbed,kjbracey-arm\/mbed,CalSol\/mbed,mmorenobarm\/mbed-os,nvlsianpu\/mbed,mazimkhan\/mbed-os,YarivCol\/mbed-os,svogl\/mbed-os,kl-cruz\/mbed-os,RonEld\/mbed,YarivCol\/mbed-os,nvlsianpu\/mbed,catiedev\/mbed-os,nRFMesh\/mbed-os,screamerbg\/mbed,pradeep-gr\/mbed-os5-onsemi,adustm\/mbed,monkiineko\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,theotherjimmy\/mbed,tung7970\/mbed-os,screamerbg\/mbed,tung7970\/mbed-os-1,bulislaw\/mbed-os,kjbracey-arm\/mbed,maximmbed\/mbed,mazimkhan\/mbed-os,j-greffe\/mbed-os,infinnovation\/mbed-os,CalSol\/mbed,bulislaw\/mbed-os,andcor02\/mbed-os,RonEld\/mbed,svogl\/mbed-os,infinnovation\/mbed-os","old_file":"hal\/targets\/cmsis\/TARGET_Freescale\/TARGET_MCU_K64F\/TOOLCHAIN_GCC_ARM\/MK64FN1M0xxx12.ld","new_file":"hal\/targets\/cmsis\/TARGET_Freescale\/TARGET_MCU_K64F\/TOOLCHAIN_GCC_ARM\/MK64FN1M0xxx12.ld","new_contents":"\/*\n** ###################################################################\n**     Processors:          MK64FN1M0VDC12\n**                          MK64FN1M0VLL12\n**                          MK64FN1M0VLQ12\n**                          MK64FN1M0VMD12\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014\n**     Version:             rev. 2.8, 2015-02-19\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n__ram_vector_table__ = 1;\n\n\/* Heap 1\/4 of ram and stack 1\/8 *\/\n__stack_size__ = 0x8000;\n__heap_size__ = 0x10000;\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: FLASH_OFFSET. *\/\n  __UVISOR_TEXT_OFFSET = 0x410;\n  __UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET;\n  .text __UVISOR_TEXT_START :\n  {\n    \/* uVisor code and data *\/\n    . = ALIGN(4);\n    __uvisor_main_start = .;\n    *(.uvisor.main)\n    __uvisor_main_end = .;\n\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  \/* Ensure that the uVisor BSS section is put first after the relocated\n   * interrupt table in SRAM. *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: SRAM_OFFSET. *\/\n  __UVISOR_SRAM_OFFSET = 0x400;\n  __UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;\n  ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,\n         \"The ISR relocation region overlaps with the uVisor BSS section.\")\n  .uvisor.bss __UVISOR_BSS_START (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uvisor_bss_start = .;\n\n    \/* protected uvisor main bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_main_start = .;\n    KEEP(*(.keep.uvisor.bss.main))\n    . = ALIGN(32);\n    __uvisor_bss_main_end = .;\n\n    \/* protected uvisor secure boxes bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_boxes_start = .;\n    KEEP(*(.keep.uvisor.bss.boxes))\n    . = ALIGN(32);\n    __uvisor_bss_boxes_end = .;\n\n    . = ALIGN(32);\n    __uvisor_bss_end = .;\n  } > m_data\n\n  \/* Heap space for the page allocator *\/\n  .page_heap (NOLOAD) :\n  {\n    . = ALIGN(32);\n    __uvisor_page_start = .;\n    KEEP(*(.keep.uvisor.page_heap))\n    . = ALIGN(32);\n    __uvisor_page_end = .;\n  } > m_data_2\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data :\n  {\n    PROVIDE(__etext = LOADADDR(.data));    \/* Define a global symbol at end of code, *\/\n    PROVIDE(__DATA_ROM = LOADADDR(.data)); \/* Symbol is used by startup for data initialization. *\/\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data_2 AT > m_text\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  \/* uVisor configuration section\n   * This section must be located after all other flash regions. *\/\n  .uvisor.secure :\n  {\n    . = ALIGN(32);\n    __uvisor_secure_start = .;\n\n    \/* uVisor secure boxes configuration tables *\/\n    . = ALIGN(32);\n    __uvisor_cfgtbl_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl))\n    . = ALIGN(32);\n    __uvisor_cfgtbl_end = .;\n\n    \/* Pointers to the uVisor secure boxes configuration tables *\/\n    \/* Note: Do not add any further alignment here, as uVisor will need to have\n     * access to the exact list of pointers. *\/\n    __uvisor_cfgtbl_ptr_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n    KEEP(*(.keep.uvisor.cfgtbl_ptr))\n    __uvisor_cfgtbl_ptr_end = .;\n\n    \/* Pointers to all boxes register gateways. These are grouped here to allow\n     * discoverability and firmware verification. *\/\n    __uvisor_register_gateway_ptr_start = .;\n    KEEP(*(.keep.uvisor.register_gateway_ptr))\n    __uvisor_register_gateway_ptr_end = .;\n\n    . = ALIGN(32);\n    __uvisor_secure_end = .;\n  } > m_text\n\n  \/* Uninitialized data section\n   * This region is not initialized by the C\/C++ library and can be used to\n   * store state across soft reboots. *\/\n  .uninitialized (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uninitialized_start = .;\n    *(.uninitialized)\n    KEEP(*(.keep.uninitialized))\n    . = ALIGN(32);\n    __uninitialized_end = .;\n  } > m_data_2\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data_2\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __uvisor_heap_start = .;\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n    __uvisor_heap_end = .;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n\n  \/* Provide the physical memory boundaries for uVisor. *\/\n  __uvisor_flash_start = ORIGIN(m_interrupts);\n  __uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);\n  __uvisor_sram_start = ORIGIN(m_data);\n  __uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);\n}\n","old_contents":"\/*\n** ###################################################################\n**     Processors:          MK64FN1M0VDC12\n**                          MK64FN1M0VLL12\n**                          MK64FN1M0VLQ12\n**                          MK64FN1M0VMD12\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014\n**     Version:             rev. 2.8, 2015-02-19\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n__ram_vector_table__ = 1;\n\n\/* Heap 1\/4 of ram and stack 1\/8 *\/\n__stack_size__ = 0x8000;\n__heap_size__ = 0x10000;\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: FLASH_OFFSET. *\/\n  __UVISOR_TEXT_OFFSET = 0x410;\n  __UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET;\n  .text __UVISOR_TEXT_START :\n  {\n    \/* uVisor code and data *\/\n    . = ALIGN(4);\n    __uvisor_main_start = .;\n    *(.uvisor.main)\n    __uvisor_main_end = .;\n\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  \/* Ensure that the uVisor BSS section is put first after the relocated\n   * interrupt table in SRAM. *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: SRAM_OFFSET. *\/\n  __UVISOR_SRAM_OFFSET = 0x400;\n  __UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;\n  ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,\n         \"The ISR relocation region overlaps with the uVisor BSS section.\")\n  .uvisor.bss __UVISOR_BSS_START (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uvisor_bss_start = .;\n\n    \/* protected uvisor main bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_main_start = .;\n    KEEP(*(.keep.uvisor.bss.main))\n    . = ALIGN(32);\n    __uvisor_bss_main_end = .;\n\n    \/* protected uvisor secure boxes bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_boxes_start = .;\n    KEEP(*(.keep.uvisor.bss.boxes))\n    . = ALIGN(32);\n    __uvisor_bss_boxes_end = .;\n\n    . = ALIGN(32);\n    __uvisor_bss_end = .;\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data :\n  {\n    PROVIDE(__etext = LOADADDR(.data));    \/* Define a global symbol at end of code, *\/\n    PROVIDE(__DATA_ROM = LOADADDR(.data)); \/* Symbol is used by startup for data initialization. *\/\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data_2 AT > m_text\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  \/* uVisor configuration section\n   * This section must be located after all other flash regions. *\/\n  .uvisor.secure :\n  {\n    . = ALIGN(32);\n    __uvisor_secure_start = .;\n\n    \/* uVisor secure boxes configuration tables *\/\n    . = ALIGN(32);\n    __uvisor_cfgtbl_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl))\n    . = ALIGN(32);\n    __uvisor_cfgtbl_end = .;\n\n    \/* Pointers to the uVisor secure boxes configuration tables *\/\n    \/* Note: Do not add any further alignment here, as uVisor will need to have\n     * access to the exact list of pointers. *\/\n    __uvisor_cfgtbl_ptr_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n    KEEP(*(.keep.uvisor.cfgtbl_ptr))\n    __uvisor_cfgtbl_ptr_end = .;\n\n    \/* Pointers to all boxes register gateways. These are grouped here to allow\n     * discoverability and firmware verification. *\/\n    __uvisor_register_gateway_ptr_start = .;\n    KEEP(*(.keep.uvisor.register_gateway_ptr))\n    __uvisor_register_gateway_ptr_end = .;\n\n    . = ALIGN(32);\n    __uvisor_secure_end = .;\n  } > m_text\n\n  \/* Uninitialized data section\n   * This region is not initialized by the C\/C++ library and can be used to\n   * store state across soft reboots. *\/\n  .uninitialized (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uninitialized_start = .;\n    *(.uninitialized)\n    KEEP(*(.keep.uninitialized))\n    . = ALIGN(32);\n    __uninitialized_end = .;\n  } > m_data_2\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data_2\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __uvisor_heap_start = .;\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n    __uvisor_heap_end = .;\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n    __StackTop = .;\n  } > m_data_2\n\n  \/* Heap space for the page allocator *\/\n  .page_heap (NOLOAD) :\n  {\n    __uvisor_page_start = .;\n    . = ORIGIN(m_data_2) + LENGTH(m_data_2) - 4;\n    __uvisor_page_end = .;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n\n  \/* Provide the physical memory boundaries for uVisor. *\/\n  __uvisor_flash_start = ORIGIN(m_interrupts);\n  __uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);\n  __uvisor_sram_start = ORIGIN(m_data);\n  __uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f0c27340c63d25fb31b9a98b49ae63bcd5284029","subject":"mc1322x: increase the HEAP to 2048 bytes: needed for COAP server.","message":"mc1322x: increase the HEAP to 2048 bytes: needed for COAP server.\n","repos":"bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,arurke\/contiki,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki","old_file":"cpu\/mc1322x\/mc1322x.lds","new_file":"cpu\/mc1322x\/mc1322x.lds","new_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\n\nMEMORY\n  {\n    ram (rwx) : org = 0x00400000, l = 96K\n  }\n\nSECTIONS\n{\n\nSYS_STACK_SIZE = 1024;\nIRQ_STACK_SIZE = 256;\nFIQ_STACK_SIZE = 256;\nSVC_STACK_SIZE = 256;\nABT_STACK_SIZE = 16;\nUND_STACK_SIZE = 16;\nHEAP_SIZE = 2048;\n\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x00400000); . = 0x00400000;\n  .text           :\n  {\n    *(.start)\n    *(.irq)\t\t\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  } =0\n\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n      *(.rela.ctors)\n      *(.rela.dtors)\n      *(.rela.got)\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n    }\n  .rel.plt        : { *(.rel.plt) }\n  .rela.plt       : { *(.rela.plt) }\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0\n  .plt            : { *(.plt) }\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Adjust the address for the data segment.  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The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .jcr            : { KEEP (*(.jcr)) } \n  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }\n  .dynamic        : { *(.dynamic) } \n  . = DATA_SEGMENT_RELRO_END (0, .);  \n  .got            : { *(.got.plt) *(.got) }\n  .data           :\n  {\n    __data_start = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .data1          : { *(.data1) }\n  _edata = .; PROVIDE (edata = .);\n\n\t.stack : {\n\t\t__stack_start__ = . ;\n\n\t\t. += IRQ_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__irq_stack_top__ = . ;\n\n\t\t. += FIQ_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__fiq_stack_top__ = . ;\n\n\t\t. += SVC_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__svc_stack_top__ = . ;\n\n\t\t. += ABT_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__abt_stack_top__ = . ;\n\n\t\t. += UND_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__und_stack_top__ = . ;\n\n\t\t. += SYS_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__sys_stack_top__ = . ;\n\n\t\t__stack_end__ = .;\n\t}\n\n\n  __bss_start = .;\n  __bss_start__ = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.\n      FIXME: Why do we need it? When there is no .bss section, we don't\n      pad the .data section.  *\/\n   . = ALIGN(. != 0 ? 32 \/ 8 : 1);\n  }\n  _bss_end__ = . ; __bss_end__ = . ;\n  . = ALIGN(32 \/ 8);\n\n   .heap : {\n                __heap_start__ = . ; PROVIDE(__HEAP_START = .);\n                *(.heap);\n                . += HEAP_SIZE;\n                . = ALIGN (4);\n                __heap_end__ = . ;  PROVIDE(__HEAP_END = .);\n   }\n\n\n  . = ALIGN(32 \/ 8);\n  __end__ = . ;\n  _end = .; PROVIDE (end = .);\n  . = DATA_SEGMENT_END (.);\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"d855951b623ef958fb62556d7cc2f9fa2c762f04","subject":"Reorganize the linker script and igore other sections","message":"Reorganize the linker script and igore other sections\n","repos":"Infinity-OS\/infinity,Infinity-OS\/infinity","old_file":"source\/kernel\/arch\/x86\/linker.ld","new_file":"source\/kernel\/arch\/x86\/linker.ld","new_contents":"ENTRY(start)\nOUTPUT_ARCH(\"i386:x86-64\")\nOUTPUT_FORMAT(\"elf64-x86-64\")\n\nSECTIONS {\n\n    \/* This define the Kernel's virtual base *\/\n    . = 0xffffffff80000000;\n    . += SIZEOF_HEADERS;\n    . = ALIGN(0x1000);\n\n    .text : {\n        __text_start = .;\n        *(.text)\n        *(.text.*)\n        . = ALIGN(0x1000);\n        __text_end = .;\n    }\n\n    .notes : {\n        *(.note.*)\n    }\n\n    .rodata ALIGN(0x1000) : {\n        __rodata_start = .;\n        *(.rodata)\n        *(.rodata.*)\n        . = ALIGN(0x1000);\n        __rodata_end = .;\n    }\n\n    .data ALIGN(0x1000) : {\n        __data_start = .;\n        *(.data)\n        *(.data.*)\n        . = ALIGN(0x1000);\n        __data_end = .;\n    }\n\n    .bss ALIGN(0x1000) : {\n        __bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN(0x1000);\n        __bss_end = .;\n    }\n\n    __end = .;\n\n    \/* Discard some unnecessary sections *\/\n    \/DISCARD\/ : {\n        *(.note.GNU-stack)\n        *(.note.gnu.*)\n        *(.comment*)\n        *(.debug*)\n        *(.eh_frame*)\n        *(.gcc_except_table*)\n        *(.rel.eh_frame*)\n    }\n}\n","old_contents":"ENTRY(start)\nOUTPUT_ARCH(\"i386:x86-64\")\nOUTPUT_FORMAT(\"elf64-x86-64\")\n\nSECTIONS {\n    . = 0xffffffff80000000 + SIZEOF_HEADERS;\n\n    .text : {\n        __text_start = .;\n        *(.text)\n        *(.text.*)\n        . = ALIGN(0x1000);\n        __text_end = .;\n    }\n\n    .notes : {\n        *(.note.*)\n    }\n\n    .rodata ALIGN(0x1000) : {\n        __rodata_start = .;\n        *(.rodata)\n        *(.rodata.*)\n        . = ALIGN(0x1000);\n        __rodata_end = .;\n    }\n\n    .data ALIGN(0x1000) : {\n        __data_start = .;\n        *(.data)\n        *(.data.*)\n        . = ALIGN(0x1000);\n        __data_end = .;\n    }\n\n    .bss ALIGN(0x1000) : {\n        __bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN(0x1000);\n        __bss_end = .;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ : {\n        *(.note.GNU-stack)\n        *(.comment*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"95b88542a111fe155ddaba36852335cb73256b56","subject":"[linker scripts] align all the special sections on 8 bytes","message":"[linker scripts] align all the special sections on 8 bytes\n\nThis satisfies 64bit architectures.\n","repos":"M1cha\/lk,littlekernel\/lk,srodrig1\/lk,sndnvaps\/lk,grub4android\/lk,nvll\/lk,minglun-tsai\/lk,ErikCorryGoogle\/lk,nvll\/lk,M1cha\/lk,travisg\/lk,srodrig1\/lk,minglun-tsai\/lk,GCrean\/lk,nvll\/lk,nvll\/lk,grub4android\/lk,littlekernel\/lk,sndnvaps\/lk,grub4android\/lk,grub4android\/lk,skabet\/lk,travisg\/lk,nvll\/lk,srodrig1\/lk,GCrean\/lk,ErikCorryGoogle\/lk,GCrean\/lk,littlekernel\/lk,GCrean\/lk,skabet\/lk,hollanderic\/lkstuff,M1cha\/lk,skabet\/lk,grub4android\/lk,hollanderic\/lkstuff,M1cha\/lk,travisg\/lk,srodrig1\/lk,M1cha\/lk,travisg\/lk,GCrean\/lk,minglun-tsai\/lk,ErikCorryGoogle\/lk,sndnvaps\/lk,littlekernel\/lk,skabet\/lk,ErikCorryGoogle\/lk,hollanderic\/lkstuff,sndnvaps\/lk,skabet\/lk,minglun-tsai\/lk,srodrig1\/lk,sndnvaps\/lk,hollanderic\/lkstuff","old_file":"arch\/shared_data_sections.ld","new_file":"arch\/shared_data_sections.ld","new_contents":"\/* should be included in all lk linker scripts in the .data segment *\/\n. = ALIGN(8);\n__commands_start = .;\nKEEP (*(.commands))\n__commands_end = .;\n. = ALIGN(8);\n__apps_start = .;\nKEEP (*(.apps))\n__apps_end = .;\n. = ALIGN(8);\n__devices = .;\nKEEP(*(.devices))\n__devices_end = .;\n\n","old_contents":"\/* should be included in all lk linker scripts in the .data segment *\/\n. = ALIGN(4);\n__commands_start = .;\nKEEP (*(.commands))\n__commands_end = .;\n. = ALIGN(4);\n__apps_start = .;\nKEEP (*(.apps))\n__apps_end = .;\n. = ALIGN(4);\n__devices = .;\nKEEP(*(.devices))\n__devices_end = .;\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"02c991fd963940eab2629f8f6fa7c1f0fdebfe6b","subject":"doc: defined symbols in comment did not match real ones","message":"doc: defined symbols in comment did not match real ones\n","repos":"ahessling\/STM32F4Template,ahessling\/STM32F4Template,ahessling\/STM32F4Template","old_file":"linker\/stm32f407vgt.ld","new_file":"linker\/stm32f407vgt.ld","new_contents":"\/* Default STM32F4xx linker script.\n *\n * Modify memory sections according to the targeted platform.\n *\/\nMEMORY\n{\n  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\n  CCMRAM (rw)    : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   _sdata\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   _edata\n *   _sbss\n *   __bss_start__\n *   __bss_end__\n *   _ebss\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __estack\n *   _sidata\n *   _siccmram\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t__etext = .;\n\t\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\t\n\t.data : AT (__etext)\n\t{\n\t\t_sdata = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t_edata = .;\n\n\t} > RAM\n\n  _siccmram = LOADADDR(.ccmram);\n\n  \/* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section,\n  * the startup code needs to be modified to copy the init-values.  \n  *\/\n  .ccmram :\n  {\n    . = ALIGN(4);\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\n  } >CCMRAM AT> FLASH\n  \n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t_sbss = .;\n    __bss_start__ = _sbss;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n    __bss_end__ = _ebss;\n\t} > RAM\n\t\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(_estack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Default STM32F4xx linker script.\n *\n * Modify memory sections according to the targeted platform.\n *\/\nMEMORY\n{\n  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\n  CCMRAM (rw)    : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t__etext = .;\n\t\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\t\n\t.data : AT (__etext)\n\t{\n\t\t_sdata = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t_edata = .;\n\n\t} > RAM\n\n  _siccmram = LOADADDR(.ccmram);\n\n  \/* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section,\n  * the startup code needs to be modified to copy the init-values.  \n  *\/\n  .ccmram :\n  {\n    . = ALIGN(4);\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\n  } >CCMRAM AT> FLASH\n  \n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t_sbss = .;\n    __bss_start__ = _sbss;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n    __bss_end__ = _ebss;\n\t} > RAM\n\t\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(_estack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a70f7f50f205cfede1fafd5d5f2e2e0384a9aa11","subject":"removed superfluous ALIGN in linker script","message":"removed superfluous ALIGN in linker script\n","repos":"CRust-OS\/CRust-OS,CRust-OS\/CRust-OS,CRust-OS\/CRust-OS,CRust-OS\/CRust-OS","old_file":"crust.lds","new_file":"crust.lds","new_contents":"ENTRY(_start)\n\n\/* all sections are padded with 0xCC (int 3, meaning breakpoint) in case we accidentally jump into uninitialized memory *\/\n\nSECTIONS {\n    .bss : ALIGN(0x1000) {\n        HYPERCALL_PAGE = .;\n        . += 0x1000;\n        STACK_TOP = .;\n        . += 0x2000;\n        STACK_BOTTOM = .;\n        *(.bss);\n        *(.bss.*);\n    } = 0xCC \n    .text : {\n        *(.text);\n        *(.text.*);\n    } = 0xCC\n    .data : {\n        *(.data);\n        *(.data.*);\n    } = 0xCC\n    .note : {\n        *(.note);\n        *(.note.*);\n    }\n}\n","old_contents":"ENTRY(_start)\n\n\/* all sections are padded with 0xCC (int 3, meaning breakpoint) in case we accidentally jump into uninitialized memory *\/\n\nSECTIONS {\n    .bss : ALIGN(0x1000) {\n        HYPERCALL_PAGE = .;\n        . += 0x1000;\n        STACK_TOP = .;\n        . += 0x2000;\n        STACK_BOTTOM = .;\n        *(.bss);\n        *(.bss.*);\n    } = 0xCC \n    .text : ALIGN(0x1000) {\n        *(.text);\n        *(.text.*);\n    } = 0xCC\n    .data : ALIGN(0x1000) {\n        *(.data);\n        *(.data.*);\n    } = 0xCC\n    .note : {\n        *(.note);\n        *(.note.*);\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"506a69917e4317251c3ebad75daa8a739d42a99d","subject":"x86: removed ctors and dtors from sneaking into binary","message":"x86: removed ctors and dtors from sneaking into binary\n","repos":"AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,mnordsletten\/IncludeOS,alfred-bratterud\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,hioa-cs\/IncludeOS,hioa-cs\/IncludeOS,hioa-cs\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,alfred-bratterud\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0x200000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  . = _ELF_START_ + SIZEOF_HEADERS;\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n  .text ALIGN(0x1000):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  _EXEC_END_ = .;\n  _READONLY_START_ = .;\n  .config ALIGN(0x1000) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n  _READONLY_END_ = .;\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","old_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0x200000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  . = _ELF_START_ + SIZEOF_HEADERS;\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n  .text ALIGN(0x1000):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x1000) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  _EXEC_END_ = .;\n  _READONLY_START_ = .;\n  .config ALIGN(0x1000) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n  _READONLY_END_ = .;\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ab1669f8c41697df04f4c776ceeae863ab6265bf","subject":"Fix linker file for ST_NUCLEO64_F091RC (#1269)","message":"Fix linker file for ST_NUCLEO64_F091RC (#1269)\n\n","repos":"nanoframework\/nf-interpreter,Eclo\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter,nanoframework\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter,Eclo\/nf-interpreter","old_file":"targets\/CMSIS-OS\/ChibiOS\/ST_NUCLEO64_F091RC\/nanoCLR\/STM32F091xC_CLR-DEBUG.ld","new_file":"targets\/CMSIS-OS\/ChibiOS\/ST_NUCLEO64_F091RC\/nanoCLR\/STM32F091xC_CLR-DEBUG.ld","new_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio.  All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n\n\/*\n * STM32F091xC memory setup.\n *\/\nMEMORY\n{\n    flash       : org = 0x08002800, len = 256k - 10k - 66k   \/* flash size less the space reserved for nanoBooter and application deployment*\/\n    config      : org = 0x00000000, len = 0                  \/* space reserved for configuration block *\/\n    deployment  : org = 0x0802F800, len = 66k                \/* space reserved for application deployment *\/\n    ramvt       : org = 0x20000000, len = 0xC0               \/* initial RAM address is reserved for a copy of the vector table *\/\n    ram0        : org = 0x200000C0, len = 32k - 0xC0         \/* remaining RAM is free for use *\/\n    ram1        : org = 0x00000000, len = 0\n    ram2        : org = 0x00000000, len = 0\n    ram3        : org = 0x00000000, len = 0\n    ram4        : org = 0x00000000, len = 0\n    ram5        : org = 0x00000000, len = 0\n    ram6        : org = 0x00000000, len = 0\n    ram7        : org = 0x00000000, len = 0\n}\n\n\/* For each data\/text section two region are defined, a virtual region\n   and a load region (_LMA suffix).*\/\n\n\/* Flash region to be used for exception vectors.*\/\nREGION_ALIAS(\"VECTORS_FLASH\", flash);\nREGION_ALIAS(\"VECTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for constructors and destructors.*\/\nREGION_ALIAS(\"XTORS_FLASH\", flash);\nREGION_ALIAS(\"XTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for code text.*\/\nREGION_ALIAS(\"TEXT_FLASH\", flash);\nREGION_ALIAS(\"TEXT_FLASH_LMA\", flash);\n\n\/* Flash region to be used for read only data.*\/\nREGION_ALIAS(\"RODATA_FLASH\", flash);\nREGION_ALIAS(\"RODATA_FLASH_LMA\", flash);\n\n\/* Flash region to be used for various.*\/\nREGION_ALIAS(\"VARIOUS_FLASH\", flash);\nREGION_ALIAS(\"VARIOUS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for RAM(n) initialization data.*\/\nREGION_ALIAS(\"RAM_INIT_FLASH_LMA\", flash);\n\n\/* RAM region to be used for Main stack. This stack accommodates the processing\n   of all exceptions and interrupts.*\/\nREGION_ALIAS(\"MAIN_STACK_RAM\", ram0);\n\n\/* RAM region to be used for the process stack. This is the stack used by\n   the main() function.*\/\nREGION_ALIAS(\"PROCESS_STACK_RAM\", ram0);\n\n\/* RAM region to be used for data segment.*\/\nREGION_ALIAS(\"DATA_RAM\", ram0);\nREGION_ALIAS(\"DATA_RAM_LMA\", flash);\n\n\/* RAM region to be used for BSS segment.*\/\nREGION_ALIAS(\"BSS_RAM\", ram0);\n\n\/* RAM region to be used for the default heap.*\/\nREGION_ALIAS(\"HEAP_RAM\", ram0);\n\n\/* RAM region to be used for the nanoFramework CLR managed heap.*\/\nREGION_ALIAS(\"CLR_MANAGED_HEAP_RAM\", ram0);\n\nINCLUDE rules.ld\n","old_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio.  All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n\n\/*\n * STM32F091xC memory setup.\n *\/\nMEMORY\n{\n    flash       : org = 0x08002000, len = 256k - 8k - 68k    \/* flash size less the space reserved for nanoBooter and application deployment*\/\n    config      : org = 0x00000000, len = 0                  \/* space reserved for configuration block *\/\n    deployment  : org = 0x0802F000, len = 68k                \/* space reserved for application deployment *\/\n    ramvt       : org = 0x20000000, len = 0xC0               \/* initial RAM address is reserved for a copy of the vector table *\/\n    ram0        : org = 0x200000C0, len = 32k - 0xC0         \/* remaining RAM is free for use *\/\n    ram1        : org = 0x00000000, len = 0\n    ram2        : org = 0x00000000, len = 0\n    ram3        : org = 0x00000000, len = 0\n    ram4        : org = 0x00000000, len = 0\n    ram5        : org = 0x00000000, len = 0\n    ram6        : org = 0x00000000, len = 0\n    ram7        : org = 0x00000000, len = 0\n}\n\n\/* For each data\/text section two region are defined, a virtual region\n   and a load region (_LMA suffix).*\/\n\n\/* Flash region to be used for exception vectors.*\/\nREGION_ALIAS(\"VECTORS_FLASH\", flash);\nREGION_ALIAS(\"VECTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for constructors and destructors.*\/\nREGION_ALIAS(\"XTORS_FLASH\", flash);\nREGION_ALIAS(\"XTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for code text.*\/\nREGION_ALIAS(\"TEXT_FLASH\", flash);\nREGION_ALIAS(\"TEXT_FLASH_LMA\", flash);\n\n\/* Flash region to be used for read only data.*\/\nREGION_ALIAS(\"RODATA_FLASH\", flash);\nREGION_ALIAS(\"RODATA_FLASH_LMA\", flash);\n\n\/* Flash region to be used for various.*\/\nREGION_ALIAS(\"VARIOUS_FLASH\", flash);\nREGION_ALIAS(\"VARIOUS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for RAM(n) initialization data.*\/\nREGION_ALIAS(\"RAM_INIT_FLASH_LMA\", flash);\n\n\/* RAM region to be used for Main stack. This stack accommodates the processing\n   of all exceptions and interrupts.*\/\nREGION_ALIAS(\"MAIN_STACK_RAM\", ram0);\n\n\/* RAM region to be used for the process stack. This is the stack used by\n   the main() function.*\/\nREGION_ALIAS(\"PROCESS_STACK_RAM\", ram0);\n\n\/* RAM region to be used for data segment.*\/\nREGION_ALIAS(\"DATA_RAM\", ram0);\nREGION_ALIAS(\"DATA_RAM_LMA\", flash);\n\n\/* RAM region to be used for BSS segment.*\/\nREGION_ALIAS(\"BSS_RAM\", ram0);\n\n\/* RAM region to be used for the default heap.*\/\nREGION_ALIAS(\"HEAP_RAM\", ram0);\n\n\/* RAM region to be used for the nanoFramework CLR managed heap.*\/\nREGION_ALIAS(\"CLR_MANAGED_HEAP_RAM\", ram0);\n\nINCLUDE rules.ld\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e59192b09d3779c740b9c902bd851b63273ff197","subject":"samples\/eagle.app.v6.ld: cut flash sectors into half","message":"samples\/eagle.app.v6.ld: cut flash sectors into half\n\nWe get an error when accessing high sectors, so just play safe.\n","repos":"ciminaghi\/libdfu,ciminaghi\/libdfu,ciminaghi\/libdfu","old_file":"samples\/eagle.app.v6.ld","new_file":"samples\/eagle.app.v6.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40240000, len = 0x3C000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    sectors_start = ABSOLUTE(.);\n    . += 512;\n    sectors_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n   .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *final.o(.literal*, .text*)\n    *libbathos.a:(.literal .text .literal.* .text.*)\n    *libdfu.a:(.literal .text .literal.* .text.*)\n    *libarch.a:(.literal .text .literal.* .text.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  \/* .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *bathos.o(.literal*, .text*)\n    *libbathos.a:(.literal .text .literal.* .text.*)\n    *libarch.a:(.literal .text .literal.* .text.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr *\/\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40240000, len = 0x3C000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    sectors_start = ABSOLUTE(.);\n    . += 1024;\n    sectors_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n   .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *final.o(.literal*, .text*)\n    *libbathos.a:(.literal .text .literal.* .text.*)\n    *libdfu.a:(.literal .text .literal.* .text.*)\n    *libarch.a:(.literal .text .literal.* .text.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  \/* .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *bathos.o(.literal*, .text*)\n    *libbathos.a:(.literal .text .literal.* .text.*)\n    *libarch.a:(.literal .text .literal.* .text.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr *\/\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"4f15a8ea232f737d3bb5303b234a5f7d4a1dc9af","subject":"[v831]change memory layout","message":"[v831]change memory layout\n","repos":"xboot\/xboot,xboot\/xboot","old_file":"src\/arch\/arm32\/mach-v831\/xboot.ld","new_file":"src\/arch\/arm32\/mach-v831\/xboot.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(_start)\r\n\r\nSTACK_UND_SIZE = 0x40000 * 1;\r\nSTACK_ABT_SIZE = 0x40000 * 1;\r\nSTACK_IRQ_SIZE = 0x40000 * 1;\r\nSTACK_FIQ_SIZE = 0x40000 * 1;\r\nSTACK_SRV_SIZE = 0x100000 * 1;\r\n\r\nMEMORY\r\n{\r\n\tram  : org = 0x40000000, len = 8M\r\n\tdma  : org = 0x40800000, len = 8M\r\n\theap : org = 0x41000000, len = 48M\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tPROVIDE(__image_start = .);\r\n\t\tPROVIDE(__text_start = .);\r\n\t\tPROVIDE(__spl_start = .);\r\n\t\t.obj\/arch\/arm32\/mach-v831\/start.o (.text*)\r\n\t\t.obj\/arch\/arm32\/lib\/memcpy.o (.text*)\r\n\t\t.obj\/arch\/arm32\/lib\/memset.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-jtag.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-uart.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-clock.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-dram.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-decompress.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-spinor.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-copyself.o (.text*)\r\n\t\tPROVIDE(__dram_param_start = .);\r\n\t\tKEEP(*(.dram.param))\r\n\t\tPROVIDE(__dram_param_end = .);\r\n\t\tPROVIDE(__dram_bin_start = .);\r\n\t\tKEEP(*(.dram.bin))\r\n\t\tPROVIDE(__dram_bin_end = .);\r\n\t\tPROVIDE(__spl_end = .);\r\n\t\t*(.text*)\r\n\t\t*(.init.text)\r\n\t\t*(.exit.text)\r\n\t\t*(.glue*)\r\n\t\t*(.note.gnu.build-id)\r\n\t\tPROVIDE(__text_end = .);\r\n\t} > ram\r\n\tPROVIDE(__spl_size = __spl_end - __spl_start);\r\n\r\n\t.ARM.exidx ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__exidx_start = .);\r\n\t\t*(.ARM.exidx*)\r\n\t\tPROVIDE (__exidx_end = .);\r\n\t} > ram\r\n\r\n\t.ARM.extab ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__extab_start = .);\r\n\t\t*(.ARM.extab*)\r\n\t\tPROVIDE (__extab_end = .);\r\n\t} > ram\r\n\r\n\t.initcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE(__initcall_end = .);\r\n\t} > ram\r\n\r\n\t.exitcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE(__exitcall_end = .);\r\n\t} > ram\r\n\r\n\t.ksymtab ALIGN(16) :\r\n\t{\r\n\t\tPROVIDE(__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE(__ksymtab_end = .);\r\n\t} > ram\r\n\r\n\t.romdisk ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE(__romdisk_end = .);\r\n\t} > ram\r\n\r\n\t.rodata ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__rodata_start = .);\r\n\t\t*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\r\n\t\tPROVIDE(__rodata_end = .);\r\n\t} > ram\r\n\r\n\t.data ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__data_start = .);\t\r\n\t\t*(.data*)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE(__data_end = .);\r\n\t\tPROVIDE(__image_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__bss_start = .);\r\n\t\t*(.bss*)\r\n\t\t*(.sbss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__bss_end = .);\r\n\t} > ram\r\n\r\n\t.stack ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__stack_start = .);\r\n\t\tPROVIDE(__stack_und_start = .);\r\n\t\t. += STACK_UND_SIZE;\r\n\t\tPROVIDE(__stack_und_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_abt_start = .);\r\n\t\t. += STACK_ABT_SIZE;\r\n\t\tPROVIDE(__stack_abt_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_irq_start = .);\r\n\t\t. += STACK_IRQ_SIZE;\r\n\t\tPROVIDE(__stack_irq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_fiq_start = .);\r\n\t\t. += STACK_FIQ_SIZE;\r\n\t\tPROVIDE(__stack_fiq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_srv_start = .);\r\n\t\t. += STACK_SRV_SIZE;\r\n\t\tPROVIDE(__stack_srv_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_end = .);\r\n\t} > ram\r\n\r\n\t.dma ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__dma_start = ORIGIN(dma));\r\n\t\tPROVIDE(__dma_end = ORIGIN(dma) + LENGTH(dma));\r\n\t} > dma\r\n\r\n\t.heap ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__heap_start = ORIGIN(heap));\r\n\t\tPROVIDE(__heap_end = ORIGIN(heap) + LENGTH(heap));\r\n\t} > heap\r\n\r\n\t.stab 0 : { *(.stab) }\r\n\t.stabstr 0 : { *(.stabstr) }\r\n\t.stab.excl 0 : { *(.stab.excl) }\r\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\r\n\t.stab.index 0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment 0 : { *(.comment) }\r\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\r\n\t.debug_info 0 : { *(.debug_info) }\r\n\t.debug_line 0 : { *(.debug_line) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t.debug_aranges 0 : { *(.debug_aranges) }\r\n}\r\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(_start)\r\n\r\nSTACK_UND_SIZE = 0x40000 * 1;\r\nSTACK_ABT_SIZE = 0x40000 * 1;\r\nSTACK_IRQ_SIZE = 0x40000 * 1;\r\nSTACK_FIQ_SIZE = 0x40000 * 1;\r\nSTACK_SRV_SIZE = 0x100000 * 1;\r\n\r\nMEMORY\r\n{\r\n\tram  : org = 0x40000000, len = 16M\r\n\tdma  : org = 0x41000000, len = 16M\r\n\theap : org = 0x42000000, len = 32M\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tPROVIDE(__image_start = .);\r\n\t\tPROVIDE(__text_start = .);\r\n\t\tPROVIDE(__spl_start = .);\r\n\t\t.obj\/arch\/arm32\/mach-v831\/start.o (.text*)\r\n\t\t.obj\/arch\/arm32\/lib\/memcpy.o (.text*)\r\n\t\t.obj\/arch\/arm32\/lib\/memset.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-jtag.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-uart.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-clock.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-dram.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-decompress.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-spinor.o (.text*)\r\n\t\t.obj\/arch\/arm32\/mach-v831\/sys-copyself.o (.text*)\r\n\t\tPROVIDE(__dram_param_start = .);\r\n\t\tKEEP(*(.dram.param))\r\n\t\tPROVIDE(__dram_param_end = .);\r\n\t\tPROVIDE(__dram_bin_start = .);\r\n\t\tKEEP(*(.dram.bin))\r\n\t\tPROVIDE(__dram_bin_end = .);\r\n\t\tPROVIDE(__spl_end = .);\r\n\t\t*(.text*)\r\n\t\t*(.init.text)\r\n\t\t*(.exit.text)\r\n\t\t*(.glue*)\r\n\t\t*(.note.gnu.build-id)\r\n\t\tPROVIDE(__text_end = .);\r\n\t} > ram\r\n\tPROVIDE(__spl_size = __spl_end - __spl_start);\r\n\r\n\t.ARM.exidx ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__exidx_start = .);\r\n\t\t*(.ARM.exidx*)\r\n\t\tPROVIDE (__exidx_end = .);\r\n\t} > ram\r\n\r\n\t.ARM.extab ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__extab_start = .);\r\n\t\t*(.ARM.extab*)\r\n\t\tPROVIDE (__extab_end = .);\r\n\t} > ram\r\n\r\n\t.initcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE(__initcall_end = .);\r\n\t} > ram\r\n\r\n\t.exitcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE(__exitcall_end = .);\r\n\t} > ram\r\n\r\n\t.ksymtab ALIGN(16) :\r\n\t{\r\n\t\tPROVIDE(__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE(__ksymtab_end = .);\r\n\t} > ram\r\n\r\n\t.romdisk ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE(__romdisk_end = .);\r\n\t} > ram\r\n\r\n\t.rodata ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__rodata_start = .);\r\n\t\t*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\r\n\t\tPROVIDE(__rodata_end = .);\r\n\t} > ram\r\n\r\n\t.data ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__data_start = .);\t\r\n\t\t*(.data*)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE(__data_end = .);\r\n\t\tPROVIDE(__image_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__bss_start = .);\r\n\t\t*(.bss*)\r\n\t\t*(.sbss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__bss_end = .);\r\n\t} > ram\r\n\r\n\t.stack ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__stack_start = .);\r\n\t\tPROVIDE(__stack_und_start = .);\r\n\t\t. += STACK_UND_SIZE;\r\n\t\tPROVIDE(__stack_und_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_abt_start = .);\r\n\t\t. += STACK_ABT_SIZE;\r\n\t\tPROVIDE(__stack_abt_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_irq_start = .);\r\n\t\t. += STACK_IRQ_SIZE;\r\n\t\tPROVIDE(__stack_irq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_fiq_start = .);\r\n\t\t. += STACK_FIQ_SIZE;\r\n\t\tPROVIDE(__stack_fiq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_srv_start = .);\r\n\t\t. += STACK_SRV_SIZE;\r\n\t\tPROVIDE(__stack_srv_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_end = .);\r\n\t} > ram\r\n\r\n\t.dma ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__dma_start = ORIGIN(dma));\r\n\t\tPROVIDE(__dma_end = ORIGIN(dma) + LENGTH(dma));\r\n\t} > dma\r\n\r\n\t.heap ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__heap_start = ORIGIN(heap));\r\n\t\tPROVIDE(__heap_end = ORIGIN(heap) + LENGTH(heap));\r\n\t} > heap\r\n\r\n\t.stab 0 : { *(.stab) }\r\n\t.stabstr 0 : { *(.stabstr) }\r\n\t.stab.excl 0 : { *(.stab.excl) }\r\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\r\n\t.stab.index 0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment 0 : { *(.comment) }\r\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\r\n\t.debug_info 0 : { *(.debug_info) }\r\n\t.debug_line 0 : { *(.debug_line) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t.debug_aranges 0 : { *(.debug_aranges) }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"124fe43c9f5c77548ee6222e342c2eb36a5336e7","subject":"update comment","message":"update comment\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX64M\/R5F564MJ.ld","new_file":"RX64M\/R5F564MJ.ld","new_contents":"\/*\n\nCopyright (c) 2005,2008,2009 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)   : ORIGIN = 0x00000000, LENGTH = 0x00080000 \/* 512k *\/\n\tSTACK (w) : ORIGIN = 0x00080000, LENGTH = 16 \/* top of RAM *\/\n\tROM (w)   : ORIGIN = 0xFFD00000, LENGTH = 0x002FFFD0 \/* 3M *\/\n\/* This is the largest RX6000: *\/\n\/*\tROM (w)   : ORIGIN = 0xffe00000, LENGTH = 0x001fffd0 *\/ \/* 2Mb *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)   : ORIGIN = 0x00000000, LENGTH = 0x00080000 \/* 512k *\/\n\tSTACK (w) : ORIGIN = 0x00080000, LENGTH = 16 \/* top of RAM *\/\n\n\tROM (w)   : ORIGIN = 0xFFD00000, LENGTH = 0x002FFFD0 \/* 3M *\/\n\/* This is the largest RX6000: *\/\n\/*\tROM (w)   : ORIGIN = 0xffe00000, LENGTH = 0x001fffd0 *\/ \/* 2Mb *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  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{"commit":"7a6a1727d084e2ad2a3d835945389e4780c10362","subject":"updated ld script","message":"updated ld script\n","repos":"yusiwen\/libmpdclient,jwise\/libmpdclient,yusiwen\/libmpdclient,yusiwen\/libmpdclient,psych0tik\/libmpdclient2,jwise\/libmpdclient,sl0th\/libmpdclient,psych0tik\/libmpdclient2,jwise\/libmpdclient,sl0th\/libmpdclient,cmende\/libmpdclient,OpenInkpot-archive\/iplinux-libmpdclient,jagleeso\/libmpdclient,cmende\/libmpdclient,OpenInkpot-archive\/iplinux-libmpdclient,jagleeso\/libmpdclient,jagleeso\/libmpdclient,sl0th\/libmpdclient,cmende\/libmpdclient","old_file":"libmpdclient.ld","new_file":"libmpdclient.ld","new_contents":"libmpdclient2 {\nglobal:\n\t\/* mpd\/async.h *\/\n\tmpd_async_new;\n\tmpd_async_free;\n\tmpd_async_get_error;\n\tmpd_async_get_error_message;\n\tmpd_async_fd;\n\tmpd_async_events;\n\tmpd_async_io;\n\tmpd_async_send_command_v;\n\tmpd_async_send_command;\n\tmpd_async_recv_line;\n\n\t\/* mpd\/capabilities.h *\/\n\tmpd_send_allowed_commands;\n\tmpd_send_disallowed_commands;\n\tmpd_send_list_url_schemes;\n\tmpd_send_list_tag_types;\n\n\t\/* mpd\/connection.h *\/\n\tmpd_connection_new;\n\tmpd_connection_new_async;\n\tmpd_connection_free;\n\tmpd_connection_set_timeout;\n\tmpd_get_error;\n\tmpd_get_error_message;\n\tmpd_get_server_error;\n\tmpd_clear_error;\n\tmpd_get_server_version;\n\tmpd_cmp_server_version;\n\n\t\/* mpd\/database.h *\/\n\tmpd_send_list_all;\n\tmpd_send_list_all_meta;\n\tmpd_send_list_meta;\n\tmpd_send_update;\n\tmpd_recv_update_id;\n\tmpd_run_update;\n\n\t\/* mpd\/directory.h *\/\n\tmpd_directory_dup;\n\tmpd_directory_free;\n\tmpd_directory_get_path;\n\tmpd_directory_begin;\n\tmpd_directory_feed;\n\tmpd_recv_directory;\n\n\t\/* mpd\/entity.h *\/\n\tmpd_entity_free;\n\tmpd_entity_get_type;\n\tmpd_entity_get_directory;\n\tmpd_entity_get_song;\n\tmpd_entity_get_playlist;\n\tmpd_entity_begin;\n\tmpd_entity_feed;\n\tmpd_recv_entity;\n\n\t\/* mpd\/idle.h *\/\n\tmpd_idle_name;\n\tmpd_idle_name_parse;\n\tmpd_send_idle;\n\tmpd_send_idle_mask;\n\tmpd_send_noidle;\n\tmpd_idle_parse_pair;\n\tmpd_recv_idle;\n\tmpd_run_idle;\n\tmpd_run_idle_mask;\n\n\t\/* mpd\/list.h *\/\n\tmpd_command_list_begin;\n\tmpd_command_list_end;\n\n\t\/* mpd\/mixer.h *\/\n\tmpd_send_set_volume;\n\tmpd_run_set_volume;\n\n\t\/* mpd\/output.h *\/\n\tmpd_output_begin;\n\tmpd_output_feed;\n\tmpd_output_free;\n\tmpd_output_get_id;\n\tmpd_output_get_name;\n\tmpd_output_get_enabled;\n\tmpd_send_outputs;\n\tmpd_recv_output;\n\tmpd_send_enable_output;\n\tmpd_run_enable_output;\n\tmpd_send_disable_output;\n\tmpd_run_disable_output;\n\n\t\/* mpd\/parser.h *\/\n\tmpd_parser_new;\n\tmpd_parser_free;\n\tmpd_parser_feed;\n\tmpd_parser_is_discrete;\n\tmpd_parser_get_ack;\n\tmpd_parser_get_at;\n\tmpd_parser_get_message;\n\tmpd_parser_get_name;\n\tmpd_parser_get_value;\n\n\t\/* mpd\/password.h *\/\n\tmpd_send_password;\n\tmpd_run_password;\n\n\t\/* mpd\/player.h *\/\n\tmpd_send_current_song;\n\tmpd_run_current_song;\n\tmpd_send_play;\n\tmpd_run_play;\n\tmpd_send_play_pos;\n\tmpd_run_play_pos;\n\tmpd_send_play_id;\n\tmpd_run_play_id;\n\tmpd_send_stop;\n\tmpd_run_stop;\n\tmpd_send_toggle_pause;\n\tmpd_run_toggle_pause;\n\tmpd_send_pause;\n\tmpd_run_pause;\n\tmpd_send_next;\n\tmpd_run_next;\n\tmpd_send_previous;\n\tmpd_run_previous;\n\tmpd_send_seek_pos;\n\tmpd_run_seek_pos;\n\tmpd_send_seek_id;\n\tmpd_run_seek_id;\n\tmpd_send_repeat;\n\tmpd_run_repeat;\n\tmpd_send_random;\n\tmpd_run_random;\n\tmpd_send_single;\n\tmpd_run_single;\n\tmpd_send_consume;\n\tmpd_run_consume;\n\tmpd_send_crossfade;\n\tmpd_run_crossfade;\n\n\t\/* mpd\/playlist.h *\/\n\tmpd_playlist_free;\n\tmpd_playlist_dup;\n\tmpd_playlist_get_path;\n\tmpd_playlist_get_last_modified;\n\tmpd_playlist_begin;\n\tmpd_playlist_feed;\n\tmpd_recv_playlist;\n\tmpd_send_list_playlist;\n\tmpd_send_list_playlist_meta;\n\tmpd_send_playlist_clear;\n\tmpd_run_playlist_clear;\n\tmpd_send_playlist_add;\n\tmpd_run_playlist_add;\n\tmpd_send_playlist_move;\n\tmpd_send_playlist_delete;\n\tmpd_run_playlist_delete;\n\tmpd_send_save;\n\tmpd_run_save;\n\tmpd_send_load;\n\tmpd_run_load;\n\tmpd_send_rename;\n\tmpd_run_rename;\n\tmpd_send_rm;\n\tmpd_run_rm;\n\n\t\/* mpd\/queue.h *\/\n\tmpd_send_list_queue_meta;\n\tmpd_send_get_queue_song_pos;\n\tmpd_send_get_queue_song_id;\n\tmpd_send_queue_changes_meta;\n\tmpd_send_queue_changes_brief;\n\tmpd_recv_queue_change_brief;\n\tmpd_send_add;\n\tmpd_send_add_id;\n\tmpd_recv_song_id;\n\tmpd_run_add_id;\n\tmpd_send_delete;\n\tmpd_send_delete_id;\n\tmpd_send_shuffle;\n\tmpd_run_shuffle;\n\tmpd_send_shuffle_range;\n\tmpd_run_shuffle_range;\n\tmpd_send_clear;\n\tmpd_run_clear;\n\tmpd_send_move;\n\tmpd_run_move;\n\tmpd_send_move_id;\n\tmpd_run_move_id;\n\tmpd_send_swap;\n\tmpd_run_swap;\n\tmpd_send_swap_id;\n\tmpd_run_swap_id;\n\n\t\/* mpd\/recv.h *\/\n\tmpd_recv_pair;\n\tmpd_recv_pair_named;\n\tmpd_return_pair;\n\tmpd_enqueue_pair;\n\n\t\/* mpd\/response.h *\/\n\tmpd_response_finish;\n\tmpd_response_next;\n\n\t\/* mpd\/search.h *\/\n\tmpd_search_db_songs;\n\tmpd_search_playlist_songs;\n\tmpd_search_db_tags;\n\tmpd_count_db_songs;\n\tmpd_search_add_constraint;\n\tmpd_search_commit;\n\tmpd_recv_pair_tag;\n\n\t\/* mpd\/send.h *\/\n\tmpd_send_command;\n\n\t\/* mpd\/song.h *\/\n\tmpd_song_free;\n\tmpd_song_dup;\n\tmpd_song_get_uri;\n\tmpd_song_add_tag;\n\tmpd_song_clear_tag;\n\tmpd_song_get_tag;\n\tmpd_song_set_duration;\n\tmpd_song_get_duration;\n\tmpd_song_set_last_modified;\n\tmpd_song_get_last_modified;\n\tmpd_song_set_pos;\n\tmpd_song_get_pos;\n\tmpd_song_set_id;\n\tmpd_song_get_id;\n\tmpd_song_begin;\n\tmpd_song_feed;\n\tmpd_recv_song;\n\n\t\/* mpd\/stats.h *\/\n\tmpd_send_stats;\n\tmpd_stats_begin;\n\tmpd_stats_feed;\n\tmpd_recv_stats;\n\tmpd_run_stats;\n\tmpd_stats_free;\n\tmpd_stats_get_number_of_artists;\n\tmpd_stats_get_number_of_albums;\n\tmpd_stats_get_number_of_songs;\n\tmpd_stats_get_uptime;\n\tmpd_stats_get_db_update_time;\n\tmpd_stats_get_play_time;\n\tmpd_stats_get_db_play_time;\n\n\t\/* mpd\/status.h *\/\n\tmpd_status_begin;\n\tmpd_status_feed;\n\tmpd_status_free;\n\tmpd_send_status;\n\tmpd_recv_status;\n\tmpd_run_status;\n\tmpd_status_get_volume;\n\tmpd_status_get_repeat;\n\tmpd_status_get_random;\n\tmpd_status_get_single;\n\tmpd_status_get_consume;\n\tmpd_status_get_queue_length;\n\tmpd_status_get_queue_version;\n\tmpd_status_get_state;\n\tmpd_status_get_crossfade;\n\tmpd_status_get_song_pos;\n\tmpd_status_get_song_id;\n\tmpd_status_get_elapsed_time;\n\tmpd_status_get_total_time;\n\tmpd_status_get_kbit_rate;\n\tmpd_status_get_audio_format;\n\tmpd_status_get_update_id;\n\tmpd_status_get_error;\n\n\t\/* mpd\/tag.h *\/\n\tmpd_tag_name;\n\tmpd_tag_name_parse;\n\nlocal:\n\t*;\n};\n","old_contents":"libmpdclient2 {\nglobal:\n\t\/* mpd\/async.h *\/\n\tmpd_async_new;\n\tmpd_async_free;\n\tmpd_async_is_alive;\n\tmpd_async_get_error;\n\tmpd_async_get_error_message;\n\tmpd_async_fd;\n\tmpd_async_events;\n\tmpd_async_io;\n\tmpd_async_send_command_v;\n\tmpd_async_send_command;\n\tmpd_async_recv_line;\n\n\t\/* mpd\/parser.h *\/\n\tmpd_parser_new;\n\tmpd_parser_free;\n\tmpd_parser_feed;\n\tmpd_parser_is_partial;\n\tmpd_parser_get_ack;\n\tmpd_parser_get_at;\n\tmpd_parser_get_message;\n\tmpd_parser_get_name;\n\tmpd_parser_get_value;\n\n\t\/* mpd\/send.h *\/\n\tmpd_send_command;\n\n\t\/* mpd\/command.h *\/\n\tmpd_send_currentsong;\n\tmpd_send_play;\n\tmpd_send_playid;\n\tmpd_send_stop;\n\tmpd_send_pause;\n\tmpd_send_next;\n\tmpd_send_previous;\n\tmpd_send_seek;\n\tmpd_send_seekid;\n\tmpd_send_repeat;\n\tmpd_send_random;\n\tmpd_send_single;\n\tmpd_send_consume;\n\tmpd_send_crossfade;\n\tmpd_send_playlistinfo;\n\tmpd_send_playlistid;\n\tmpd_send_plchanges;\n\tmpd_send_plchangesposid;\n\tmpd_send_add;\n\tmpd_send_addid;\n\tmpd_send_delete;\n\tmpd_send_deleteid;\n\tmpd_send_shuffle;\n\tmpd_send_shuffle_range;\n\tmpd_send_clear;\n\tmpd_send_move;\n\tmpd_send_moveid;\n\tmpd_send_swap;\n\tmpd_send_swapid;\n\tmpd_send_listplaylist;\n\tmpd_send_listplaylistinfo;\n\tmpd_send_playlistclear;\n\tmpd_send_playlistadd;\n\tmpd_send_playlistmove;\n\tmpd_send_playlistdelete;\n\tmpd_send_save;\n\tmpd_send_load;\n\tmpd_send_rename;\n\tmpd_send_rm;\n\tmpd_send_listall;\n\tmpd_send_listallinfo;\n\tmpd_send_lsinfo;\n\tmpd_send_list_artist;\n\tmpd_send_list_album;\n\tmpd_send_update;\n\tmpd_send_setvol;\n\tmpd_send_volume;\n\tmpd_send_password;\n\tmpd_send_commands;\n\tmpd_send_notcommands;\n\tmpd_send_urlhandlers;\n\tmpd_send_tagtypes;\n\n        *;\n};\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"5061760293541e67a4a18ec5ed35ef809a8563e2","subject":"linker: esp32: update linker with recent iterable","message":"linker: esp32: update linker with recent iterable\n\nbt_conn_cb section was added into common-rom.ld and\nas current ESP has limited segment section number, it\nneeds to be moved out from there.\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"18ca9b5e6cb956bb872db7af92397bcb7c49c66d","subject":"[M2351] Fix GCC linker file 'cannot move location counter backwards' issue","message":"[M2351] Fix GCC linker file 'cannot move location counter backwards' issue\n","repos":"betzw\/mbed-os,kjbracey-arm\/mbed,betzw\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed,c1728p9\/mbed-os,c1728p9\/mbed-os,betzw\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os,andcor02\/mbed-os,betzw\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,mbedmicro\/mbed,betzw\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,betzw\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os","old_file":"targets\/TARGET_NUVOTON\/TARGET_M2351\/device\/TOOLCHAIN_GCC_ARM\/M2351.ld","new_file":"targets\/TARGET_NUVOTON\/TARGET_M2351\/device\/TOOLCHAIN_GCC_ARM\/M2351.ld","new_contents":"\/*\n * Nuvoton M2351 GCC linker script file\n *\/\n \nStackSize = 0x800;\n\n#if (__DOMAIN_NS == 1U)\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x10040000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x10040400, LENGTH = 0x00040000 - 0x00000400\n  RAM_INTERN (rwx)      : ORIGIN = 0x30010000, LENGTH = 0x00010000 - 0x00000000\n}\n\n#else\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x0003F000 - 0x00000400\n  NSC_FLASH (rx)        : ORIGIN = 0x0003F000, LENGTH = 0x00040000 - 0x0003F000\n  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000\n}\n\n#endif\n\n\/**\n * Must match cmsis_nvic.h\n *\/\n__vector_size = 4 * (16 + 102);\n\n \n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    \n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        \/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. *\/\n        . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));\n        __uvisor_bss_end = .;\n    } > RAM_INTERN\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n#if (__DOMAIN_NS != 1U)    \n    \/* Veneer$$CMSE : *\/\n    .gnu.sgstubs :\n    {\n       __sgstubs_start = .;\n        *(.gnu.sgstubs.*)\n       __sgstubs_end = .;    \n    } > NSC_FLASH \n#endif\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += StackSize - (. - __StackLimit);\n    } > RAM_INTERN\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Relocate vector table in SRAM *\/\n    .isr_vector.reloc (NOLOAD) :\n    {\n        . = ALIGN(1 << LOG2CEIL(__vector_size));\n        PROVIDE(__start_vector_table__ = .);\n        . += __vector_size;\n        PROVIDE(__end_vector_table__ = .);\n    } > RAM_INTERN\n    \n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM_INTERN AT>FLASH\n\n    \/* uvisor configuration data *\/   \n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assertions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM_INTERN\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM_INTERN\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        __HeapLimit = .;\n    } > RAM_INTERN\n\n    __HeapLimit = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);    \n    \n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* Provide physical memory boundaries for uVisor. *\/    \n    __uvisor_flash_start = ORIGIN(VECTORS);\n    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n    __uvisor_sram_start = ORIGIN(RAM_INTERN);\n    __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);\n    \n}\n","old_contents":"\/*\n * Nuvoton M2351 GCC linker script file\n *\/\n \nStackSize = 0x800;\n\n#if (__DOMAIN_NS == 1U)\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x10040000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x10040400, LENGTH = 0x00040000 - 0x00000400\n  RAM_INTERN (rwx)      : ORIGIN = 0x30010000, LENGTH = 0x00010000 - 0x00000000\n}\n\n#else\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x0003F000 - 0x00000400\n  NSC_FLASH (rx)        : ORIGIN = 0x0003F000, LENGTH = 0x00040000 - 0x0003F000\n  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000\n}\n\n#endif\n\n\/**\n * Must match cmsis_nvic.h\n *\/\n__vector_size = 4 * (16 + 102);\n\n \n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    \n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        \/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. *\/\n        . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));\n        __uvisor_bss_end = .;\n    } > RAM_INTERN\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n#if (__DOMAIN_NS != 1U)    \n    \/* Veneer$$CMSE : *\/\n    .gnu.sgstubs :\n    {\n       __sgstubs_start = .;\n        *(.gnu.sgstubs.*)\n       __sgstubs_end = .;    \n    } > NSC_FLASH \n#endif\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += StackSize - (. - __StackLimit);\n    } > RAM_INTERN\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Relocate vector table in SRAM *\/\n    .isr_vector.reloc (NOLOAD) :\n    {\n        . = ALIGN(1 << LOG2CEIL(__vector_size));\n        PROVIDE(__start_vector_table__ = .);\n        . += __vector_size;\n        PROVIDE(__end_vector_table__ = .);\n    } > RAM_INTERN\n    \n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM_INTERN AT>FLASH\n\n    \/* uvisor configuration data *\/   \n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assertions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM_INTERN\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM_INTERN\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);\n        __HeapLimit = .;\n    } > RAM_INTERN\n\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* Provide physical memory boundaries for uVisor. *\/    \n    __uvisor_flash_start = ORIGIN(VECTORS);\n    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n    __uvisor_sram_start = ORIGIN(RAM_INTERN);\n    __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);\n    \n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"685dd95eddbebb23af31aaf5bef59742603b09da","subject":"fix MX to build with plib","message":"fix MX to build with plib\n","repos":"adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX","old_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_contents":"\/************************************************************************\n *\tchipKIT-applicaiton-COMMON.ld\n *\t\n *\tThis is the common part of the linker script shared\n *\tacross all chipKIT PIC32 processors \/ boards.\n *\t\n ************************************************************************\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\n * \tThis library is free software; you can redistribute it and\/or\n *  modify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\t\n *\tThis library is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\n *\tLesser General Public License for more details.\n *\t\n *\tYou should have received a copy of the GNU Lesser General\n *\tPublic License along with this library; if not, write to the\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\n *\tBoston, MA\t02111-1307\tUSA\n *\t\n *\t\n ************************************************************************\n *\tEdit History\n ************************************************************************\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\n ************************************************************************\n *\/\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\nINPUT(\"crtbegin.o\")\nINPUT(\"crtend.o\")\nINPUT(\"crtn.o\")\nOPTIONAL(\"libmchp_peripheral.a\") \n\n\/*************************************************************************\n * Start the layout of memory, the sections...\n *************************************************************************\/\nSECTIONS\n{\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\n  {\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n .image_ptr_table _IMAGE_PTR_TABLE :\n  {\n    LONG(_ebase_address)\t\n    LONG(_image_header_info)\n  } > exception_mem\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n\n  .vector_0 _ebase_address + 0x200 :\n  {\n    _new_vector_0 = . ;\n\tKEEP(*(.vector_new_0))\n    _original_vector_0 = . ;\n\tKEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_new_1))\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_new_2))\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_new_3))\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_new_4))\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_new_5))\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_new_6))\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_new_7))\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_new_8))\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_new_9))\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_new_10))\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_new_11))\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_new_12))\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_new_13))\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_new_14))\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_new_15))\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_new_16))\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_new_17))\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_new_18))\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_new_19))\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_new_20))\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_new_21))\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_new_22))\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_new_23))\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_new_24))\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_new_25))\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_new_26))\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_new_27))\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_new_28))\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_new_29))\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_new_30))\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_new_31))\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_new_32))\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_new_33))\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_new_34))\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_new_35))\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_new_36))\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_new_37))\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_new_38))\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_new_39))\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_new_40))\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_new_41))\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_new_42))\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_new_43))\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_new_44))\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_new_45))\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_new_46))\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_new_47))\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_new_48))\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_new_49))\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_new_50))\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_new_51))\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_new_52))\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_new_53))\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_new_54))\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_new_55))\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_new_56))\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_new_57))\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_new_58))\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_new_59))\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_new_60))\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_new_61))\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_new_62))\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_new_63))\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.stub .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n    *(.gnu.warning)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n    . = ALIGN(4) ;\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  \/* Read-only sections *\/\n  .header_info ALIGN(4) :\n  {\n    _image_header_info = . ;\n    LONG(SIZEOF(.header_info))                 \/* size of this structure       *\/\n    LONG(0xFFFFFFFF)                           \/* bootloader version           *\/\n    KEEP(*(.mpide_version *.mpide_version.*))  \/* MPIDE build version          *\/\n    LONG(0xFFFFFFFF)                           \/* booloader capabilities       *\/\n    LONG(0xFFFFFFFF)                           \/* VID and PID                  *\/\n    LONG(_IMAGE_TYPE)                          \/* image type and options       *\/\n    LONG(_JUMP_ADDR)                           \/* image execution address      *\/\n    LONG(_ebase_address)                       \/* image base address           *\/\n    LONG(_IMAGE_FLASH_SIZE)                    \/* size of image flash used     *\/\n    LONG(ORIGIN(kseg0_eeprom_mem))             \/* eeprom location              *\/\n    LONG(LENGTH(kseg0_eeprom_mem))             \/* eeprom size                  *\/   \n    LONG(ORIGIN(configsfrs))                   \/* config bits location         *\/\n    LONG(LENGTH(configsfrs))                   \/* config bits size             *\/\n    LONG(_ram_header_addr)                     \/* ram header pointer           *\/\n    LONG(SIZEOF(.ram_exchange_data))           \/* ram Header size              *\/\n    LONG(0xFFFFFFFF)                           \/* what the bootloader skips    *\/\n    LONG(_original_vector_0)                   \/* the original vector 0        *\/\n    LONG(_new_vector_0)                        \/* new\/indirect vector 0        *\/\n    LONG(_vector_spacing << 5)                 \/* spacing of both org\/new vec  *\/\n    _image_header_info_end = . ;\n  } > kseg0_program_mem\n  ASSERT (SIZEOF(.header_info) == 76, \"MPIDE Version not specfied correctly\")\n\n  .rodata  ALIGN(4) :\n  {\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n  \n  .ram_exchange_data (NOLOAD) :\n  {\n    _ram_header_addr = . ;\n    . += 8 ;\n  } >kseg1_data_mem\n\n  \/* Persistent data - Use the new C 'persistent' attribute instead. *\/\n  .persist ALIGN(4) (NOLOAD) :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4) ;\n    _persist_end = .;\n  } >kseg1_data_mem\n\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\n\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\n\n  .protected_bootloader ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : 0x0);\n  }\n\n  \/*\n   *  Note that input sections named .data* are not mapped here.\n   *  The best-fit allocator locates them, so that they may flow\n   *  around absolute sections as needed.\n   *\/\n  .data :\n  {\n    _data_begin = . ;\n    *( .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  _data_image_begin = LOADADDR(.data) ;\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(4) ;\n    _sdata_end = . ;\n  } >kseg1_data_mem\n\n  .lit8           :\n  {\n    *(.lit8)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem \n\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    . = ALIGN(4) ;\n    _sbss_end = . ;\n  } >kseg1_data_mem\n\n  .bss   :\n  {\n    *(.dynbss)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n\n  \/*\n   *  The heap and stack are best-fit allocated by the linker after other\n   *  data and bss sections have been allocated.\n   *\/\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\n   * RAM functions are now allocated by the linker. The linker generates\n   * _ramfunc_begin and _bmxdkpba_address symbols depending on the\n   * location of RAM functions.\n   *\/\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n\n    \/* The .pdr section belongs in the absolute section *\/\n    \n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n\n  .gcc_compiled_long32 : { KEEP(*(.gcc_compiled_long32)) }\n  .gcc_compiled_long64 : { KEEP(*(.gcc_compiled_long64)) }\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0  : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) *(.discard) }\n}\n","old_contents":"\/************************************************************************\n *\tchipKIT-applicaiton-COMMON.ld\n *\t\n *\tThis is the common part of the linker script shared\n *\tacross all chipKIT PIC32 processors \/ boards.\n *\t\n ************************************************************************\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\n * \tThis library is free software; you can redistribute it and\/or\n *  modify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\t\n *\tThis library is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\n *\tLesser General Public License for more details.\n *\t\n *\tYou should have received a copy of the GNU Lesser General\n *\tPublic License along with this library; if not, write to the\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\n *\tBoston, MA\t02111-1307\tUSA\n *\t\n *\t\n ************************************************************************\n *\tEdit History\n ************************************************************************\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\n ************************************************************************\n *\/\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\nINPUT(\"crtbegin.o\")\nINPUT(\"crtend.o\")\nINPUT(\"crtn.o\")\nOPTIONAL(\"libmchp_peripheral.a\") \n\n\/*************************************************************************\n * Start the layout of memory, the sections...\n *************************************************************************\/\nSECTIONS\n{\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\n  {\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n .image_ptr_table _IMAGE_PTR_TABLE :\n  {\n    LONG(_ebase_address)\t\n    LONG(_image_header_info)\n  } > exception_mem\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n\n  .vector_0 _ebase_address + 0x200 :\n  {\n    _new_vector_0 = . ;\n\tKEEP(*(.vector_new_0))\n    _original_vector_0 = . ;\n\tKEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_new_1))\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_new_2))\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_new_3))\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_new_4))\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_new_5))\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_new_6))\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_new_7))\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_new_8))\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_new_9))\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_new_10))\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_new_11))\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_new_12))\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_new_13))\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_new_14))\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_new_15))\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_new_16))\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_new_17))\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_new_18))\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_new_19))\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_new_20))\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_new_21))\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_new_22))\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_new_23))\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_new_24))\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_new_25))\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_new_26))\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_new_27))\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_new_28))\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_new_29))\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_new_30))\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_new_31))\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_new_32))\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_new_33))\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_new_34))\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_new_35))\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_new_36))\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_new_37))\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_new_38))\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_new_39))\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_new_40))\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_new_41))\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_new_42))\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_new_43))\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_new_44))\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_new_45))\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_new_46))\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_new_47))\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_new_48))\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_new_49))\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_new_50))\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_new_51))\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_new_52))\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_new_53))\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_new_54))\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_new_55))\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_new_56))\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_new_57))\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_new_58))\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_new_59))\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_new_60))\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_new_61))\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_new_62))\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_new_63))\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n    . = ALIGN(4) ;\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  \/* Read-only sections *\/\n  .header_info ALIGN(4) :\n  {\n    _image_header_info = . ;\n    LONG(SIZEOF(.header_info))                 \/* size of this structure       *\/\n    LONG(0xFFFFFFFF)                           \/* bootloader version           *\/\n    KEEP(*(.mpide_version *.mpide_version.*))  \/* MPIDE build version          *\/\n    LONG(0xFFFFFFFF)                           \/* booloader capabilities       *\/\n    LONG(0xFFFFFFFF)                           \/* VID and PID                  *\/\n    LONG(_IMAGE_TYPE)                          \/* image type and options       *\/\n    LONG(_JUMP_ADDR)                           \/* image execution address      *\/\n    LONG(_ebase_address)                       \/* image base address           *\/\n    LONG(_IMAGE_FLASH_SIZE)                    \/* size of image flash used     *\/\n    LONG(ORIGIN(kseg0_eeprom_mem))             \/* eeprom location              *\/\n    LONG(LENGTH(kseg0_eeprom_mem))             \/* eeprom size                  *\/   \n    LONG(ORIGIN(configsfrs))                   \/* config bits location         *\/\n    LONG(LENGTH(configsfrs))                   \/* config bits size             *\/\n    LONG(_ram_header_addr)                     \/* ram header pointer           *\/\n    LONG(SIZEOF(.ram_exchange_data))           \/* ram Header size              *\/\n    LONG(0xFFFFFFFF)                           \/* what the bootloader skips    *\/\n    LONG(_original_vector_0)                   \/* the original vector 0        *\/\n    LONG(_new_vector_0)                        \/* new\/indirect vector 0        *\/\n    LONG(_vector_spacing << 5)                 \/* spacing of both org\/new vec  *\/\n    _image_header_info_end = . ;\n  } > kseg0_program_mem\n  ASSERT (SIZEOF(.header_info) == 76, \"MPIDE Version not specfied correctly\")\n\n  .rodata  ALIGN(4) :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n  \n  .ram_exchange_data (NOLOAD) :\n  {\n    _ram_header_addr = . ;\n    . += 8 ;\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist ALIGN(4) (NOLOAD) :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4) ;\n    _persist_end = .;\n  } >kseg1_data_mem\n\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\n\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\n\n  .data  _protected_end :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n\n  _data_image_begin = LOADADDR(.data) ;\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(4) ;\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n\n  .lit8           :\n  {\n    *(.lit8)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    . = ALIGN(4) ;\n    _sbss_end = . ;\n  } >kseg1_data_mem\n\n  .bss   :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0  : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"e43f79fee7f2e285960153ba0bd4627fa2b5a6c9","subject":"nrf\/boards\/common.ld: Avoid overflowing the .text region.","message":"nrf\/boards\/common.ld: Avoid overflowing the .text region.\n\nSimilar commit to this one:\nhttps:\/\/github.com\/tralamazza\/micropython\/commit\/6e56e6269f467e59316b5e4cb04ea37ab6a0dfe3\n\nWhen .text + .data oveflow available flash, the linker may not show an\nerror. This change makes sure .data is included in the size calculation.\n","repos":"tralamazza\/micropython,tralamazza\/micropython,tralamazza\/micropython,tralamazza\/micropython","old_file":"ports\/nrf\/boards\/common.ld","new_file":"ports\/nrf\/boards\/common.ld","new_contents":"\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n        *(.text)             \/* .text sections (code) *\/\n        *(.text*)            \/* .text* sections (code) *\/\n        *(.rodata)           \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)          \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/      \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/      \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;          \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n     \n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n        \n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n        \n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT>FLASH_TEXT\n            \n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\tPROVIDE ( end = . );\n\tPROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n_flash_user_start = ORIGIN(FLASH_USER);\n_flash_user_end   = ORIGIN(FLASH_USER) + LENGTH(FLASH_USER);\n","old_contents":"\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n        *(.text)             \/* .text sections (code) *\/\n        *(.text*)            \/* .text* sections (code) *\/\n        *(.rodata)           \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)          \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/      \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/      \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;          \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n     \n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n        \n    \/* used by the startup to initialize data *\/\n    _sidata = .;\n        \n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM \n            \n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\tPROVIDE ( end = . );\n\tPROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n_flash_user_start = ORIGIN(FLASH_USER);\n_flash_user_end   = ORIGIN(FLASH_USER) + LENGTH(FLASH_USER);\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3bca8c5dee1e522bb90f220cd05c839aded42ff8","subject":"muen: Add separate rodata segment linker script","message":"muen: Add separate rodata segment linker script\n\nPut read-only sections like .rodata and manifests into rodata segment in\norder to separate them from .text which is executable.\n","repos":"mato\/solo5,Solo5\/solo5,Solo5\/solo5,mato\/solo5,mato\/solo5","old_file":"bindings\/muen\/solo5_muen.lds","new_file":"bindings\/muen\/solo5_muen.lds","new_contents":"\/*\n * Copyright (c) 2015-2019 Contributors as noted in the AUTHORS file\n *\n * This file is part of Solo5, a sandboxed execution environment.\n *\n * Permission to use, copy, modify, and\/or distribute this software\n * for any purpose with or without fee is hereby granted, provided\n * that the above copyright notice and this permission notice appear\n * in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL\n * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE\n * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR\n * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS\n * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,\n * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN\n * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\/\n\n\/*\n * This is the custom linker script for the Solo5 'muen' target.\n *\n * The script is tested to work with a minimal set of input sections. If there\n * are unexpected input sections not named here, the result will probably not be\n * correct.\n *\/\nTEXT_START = 0x100000;\n\nENTRY(_start)\n\n\/*\n * Program headers: In order to force the linker to place each of our NOTEs\n * into a separate PT_NOTE header, we need to lay these out explicitly.\n *\/\nPHDRS {\n    text PT_LOAD FLAGS(5); \/* No FILEHDR or PHDRS, force R\/E only.\n                              FLAGS values come from PF_x in elf.h *\/\n    rodata PT_LOAD;\n    data PT_LOAD;\n    note.abi PT_NOTE;\n    note.manifest PT_NOTE;\n}\n\n\/*\n * Output sections.\n *\/\nSECTIONS {\n    . = TEXT_START; \/* No + SIZEOF_HEADERS *\/\n\n    \/*\n     * :text: The following input sections are placed in the R\/E :text segment.\n     *\/\n    _stext = .;\n\n    .text :\n    {\n        *(.text)\n        *(.text.*)\n    } :text\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _etext = .;\n\n    \/* Read-only data *\/\n\n    \/* For Muen, the ABI and MFT NOTEs are read-only and can be in :rodata. *\/\n    .note.solo5.manifest :\n    {\n        *(.note.solo5.manifest*)\n    } :rodata :note.manifest\n    .note.solo5.abi :\n    {\n        *(.note.solo5.abi*)\n    } :rodata :note.abi\n\n    .rodata :\n    {\n        *(.rodata)\n        *(.rodata.*)\n    } :rodata\n    .eh_frame :\n    {\n        *(.eh_frame)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _erodata = .;\n\n    \/*\n     * :data: The following input sections are placed in the R\/W :data segment.\n     *\/\n\n    \/* Read-write data (initialized) *\/\n    .got :\n    {\n        *(.got.plt)\n        *(.got)\n    } :data\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n    }\n    .tdata :\n    {\n        *(.tdata)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _edata = .;\n\n    \/* Read-write data (uninitialized) *\/\n    .tbss :\n    {\n        *(.tbss)\n    }\n    .bss :\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _ebss = .;\n    _end = .;\n\n    \/* We are not building a GNU executable, so discard any default NOTEs the\n       toolchain might generate to prevent any surprises in the final layout. *\/\n    \/DISCARD\/ : {\n        *(.note.gnu.*)\n    }\n}\n","old_contents":"\/*\n * Copyright (c) 2015-2019 Contributors as noted in the AUTHORS file\n *\n * This file is part of Solo5, a sandboxed execution environment.\n *\n * Permission to use, copy, modify, and\/or distribute this software\n * for any purpose with or without fee is hereby granted, provided\n * that the above copyright notice and this permission notice appear\n * in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL\n * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE\n * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR\n * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS\n * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,\n * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN\n * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\/\n\n\/*\n * This is the custom linker script for the Solo5 'muen' target.\n *\n * The script is tested to work with a minimal set of input sections. If there\n * are unexpected input sections not named here, the result will probably not be\n * correct.\n *\/\nTEXT_START = 0x100000;\n\nENTRY(_start)\n\n\/*\n * Program headers: In order to force the linker to place each of our NOTEs\n * into a separate PT_NOTE header, we need to lay these out explicitly.\n *\/\nPHDRS {\n    text PT_LOAD FLAGS(5); \/* No FILEHDR or PHDRS, force R\/E only.\n                              FLAGS values come from PF_x in elf.h *\/\n    data PT_LOAD;\n    note.abi PT_NOTE;\n    note.manifest PT_NOTE;\n}\n\n\/*\n * Output sections.\n *\/\nSECTIONS {\n    . = TEXT_START; \/* No + SIZEOF_HEADERS *\/\n\n    \/*\n     * :text: The following input sections are placed in the R\/E :text segment.\n     *\/\n    _stext = .;\n\n    .text :\n    {\n        *(.text)\n        *(.text.*)\n    } :text\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _etext = .;\n\n    \/* Read-only data *\/\n\n    \/* For Muen, the ABI and MFT NOTEs are read-only and can be in :text. *\/\n    .note.solo5.manifest :\n    {\n        *(.note.solo5.manifest*)\n    } :text :note.manifest\n    .note.solo5.abi :\n    {\n        *(.note.solo5.abi*)\n    } :text :note.abi\n\n    .rodata :\n    {\n        *(.rodata)\n        *(.rodata.*)\n    } :text\n    .eh_frame :\n    {\n        *(.eh_frame)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _erodata = .;\n\n    \/*\n     * :data: The following input sections are placed in the R\/W :data segment.\n     *\/\n\n    \/* Read-write data (initialized) *\/\n    .got :\n    {\n        *(.got.plt)\n        *(.got)\n    } :data\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n    }\n    .tdata :\n    {\n        *(.tdata)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _edata = .;\n\n    \/* Read-write data (uninitialized) *\/\n    .tbss :\n    {\n        *(.tbss)\n    }\n    .bss :\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _ebss = .;\n    _end = .;\n\n    \/* We are not building a GNU executable, so discard any default NOTEs the\n       toolchain might generate to prevent any surprises in the final layout. *\/\n    \/DISCARD\/ : {\n        *(.note.gnu.*)\n    }\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"92147999b997e7e167ab0365cc98d1f2e99824c7","subject":"Update linker script for SDK 1.1.0","message":"Update linker script for SDK 1.1.0\n\nException vectors have moved into .text.\n","repos":"paulmand3l\/Arduino,gonium\/Arduino,koltegirish\/Arduino,drpjk\/Arduino,Protoneer\/Arduino,nkolban\/Arduino,Alfredynho\/AgroSis,mangelajo\/Arduino,noahchense\/Arduino-1,mattvenn\/Arduino,sanyaade-iot\/Arduino-1,wdoganowski\/Arduino,leftbrainstrain\/Arduino-ESP8266,weera00\/Arduino,smily77\/Arduino,aichi\/Arduino-2,Alfredynho\/AgroSis,Alfredynho\/AgroSis,paulo-raca\/ESP8266-Arduino,ogahara\/Arduino,zenmanenergy\/Arduino,danielchalef\/Arduino,raimohanska\/Arduino,raimohanska\/Arduino,mangelajo\/Arduino,noahchense\/Arduino-1,zenmanenergy\/Arduino,ogahara\/Arduino,fungxu\/Arduino,ogahara\/Arduino,gonium\/Arduino,drpjk\/Arduino,radut\/Arduino,radut\/Arduino,myrtleTree33\/Arduino,gonium\/Arduino,weera00\/Arduino,Cloudino\/Arduino,Protoneer\/Arduino,eeijcea\/Arduino-1,Cloudino\/Arduino,jomolinare\/Arduino,mangelajo\/Arduino,leftbrainstrain\/Arduino-ESP8266,koltegirish\/Arduino,NeuralSpaz\/Arduino,gonium\/Arduino,koltegirish\/Arduino,zenmanenergy\/Arduino,ssvs111\/Arduino,radut\/Arduino,wdoganowski\/Arduino,mateuszdw\/Arduino,mattvenn\/Arduino,spapadim\/Arduino,nkolban\/Arduino,EmuxEvans\/Arduino,aichi\/Arduino-2,Protoneer\/Arduino,paulo-raca\/ESP8266-Arduino,drpjk\/Arduino,radut\/Arduino,leftbrainstrain\/Arduino-ESP8266,Cloudino\/Arduino,sanyaade-iot\/Arduino-1,wdoganowski\/Arduino,fungxu\/Arduino,mateuszdw\/Arduino,mangelajo\/Arduino,paulo-raca\/ESP8266-Arduino,paulo-raca\/ESP8266-Arduino,noahchense\/Arduino-1,koltegirish\/Arduino,adafruit\/ESP8266-Arduino,fungxu\/Arduino,jomolinare\/Arduino,mangelajo\/Arduino,mattvenn\/Arduino,Alfredynho\/AgroSis,Protoneer\/Arduino,NeuralSpaz\/Arduino,raimohanska\/Arduino,spapadim\/Arduino,weera00\/Arduino,shiitakeo\/Arduino,drpjk\/Arduino,jomolinare\/Arduino,sanyaade-iot\/Arduino-1,wdoganowski\/Arduino,zenmanenergy\/Arduino,leftbrainstrain\/Arduino-ESP8266,gonium\/Arduino,tannewt\/Arduino,radut\/Arduino,NeuralSpaz\/Arduino,paulmand3l\/Arduino,gonium\/Arduino,eeijcea\/Arduino-1,paulo-raca\/ESP8266-Arduino,ogahara\/Arduino,danielchalef\/Arduino,weera00\/Arduino,jomolinare\/Arduino,radut\/Arduino,koltegirish\/Arduino,eeijcea\/Arduino-1,spapadim\/Arduino,smily77\/Arduino,tannewt\/Arduino,nkolban\/Arduino,mattvenn\/Arduino,adafruit\/ESP8266-Arduino,NeuralSpaz\/Arduino,aichi\/Arduino-2,spapadim\/Arduino,wdoganowski\/Arduino,shiitakeo\/Arduino,smily77\/Arduino,mateuszdw\/Arduino,EmuxEvans\/Arduino,koltegirish\/Arduino,ssvs111\/Arduino,ssvs111\/Arduino,raimohanska\/Arduino,zenmanenergy\/Arduino,Cloudino\/Cloudino-Arduino-IDE,myrtleTree33\/Arduino,tannewt\/Arduino,ogahara\/Arduino,jomolinare\/Arduino,paulmand3l\/Arduino,aichi\/Arduino-2,Cloudino\/Arduino,danielchalef\/Arduino,shiitakeo\/Arduino,EmuxEvans\/Arduino,smily77\/Arduino,ogahara\/Arduino,EmuxEvans\/Arduino,fungxu\/Arduino,danielchalef\/Arduino,spapadim\/Arduino,NeuralSpaz\/Arduino,leftbrainstrain\/Arduino-ESP8266,sanyaade-iot\/Arduino-1,noahchense\/Arduino-1,mattvenn\/Arduino,mateuszdw\/Arduino,raimohanska\/Arduino,fungxu\/Arduino,Alfredynho\/AgroSis,aichi\/Arduino-2,eeijcea\/Arduino-1,eeijcea\/Arduino-1,raimohanska\/Arduino,sanyaade-iot\/Arduino-1,ssvs111\/Arduino,Cloudino\/Cloudino-Arduino-IDE,myrtleTree33\/Arduino,zenmanenergy\/Arduino,wdoganowski\/Arduino,noahchense\/Arduino-1,mangelajo\/Arduino,Cloudino\/Cloudino-Arduino-IDE,paulmand3l\/Arduino,eeijcea\/Arduino-1,shiitakeo\/Arduino,mateuszdw\/Arduino,ssvs111\/Arduino,Cloudino\/Arduino,koltegirish\/Arduino,leftbrainstrain\/Arduino-ESP8266,nkolban\/Arduino,drpjk\/Arduino,EmuxEvans\/Arduino,adafruit\/ESP8266-Arduino,mattvenn\/Arduino,Cloudino\/Arduino,sanyaade-iot\/Arduino-1,shiitakeo\/Arduino,paulmand3l\/Arduino,myrtleTree33\/Arduino,EmuxEvans\/Arduino,weera00\/Arduino,NeuralSpaz\/Arduino,nkolban\/Arduino,paulo-raca\/ESP8266-Arduino,Cloudino\/Cloudino-Arduino-IDE,noahchense\/Arduino-1,danielchalef\/Arduino,fungxu\/Arduino,Protoneer\/Arduino,EmuxEvans\/Arduino,nkolban\/Arduino,Alfredynho\/AgroSis,Cloudino\/Cloudino-Arduino-IDE,jomolinare\/Arduino,raimohanska\/Arduino,zenmanenergy\/Arduino,ssvs111\/Arduino,Protoneer\/Arduino,shiitakeo\/Arduino,adafruit\/ESP8266-Arduino,mangelajo\/Arduino,ogahara\/Arduino,Cloudino\/Arduino,adafruit\/ESP8266-Arduino,Protoneer\/Arduino,wdoganowski\/Arduino,tannewt\/Arduino,gonium\/Arduino,sanyaade-iot\/Arduino-1,ssvs111\/Arduino,Cloudino\/Cloudino-Arduino-IDE,mattvenn\/Arduino,danielchalef\/Arduino,smily77\/Arduino,weera00\/Arduino,adafruit\/ESP8266-Arduino,adafruit\/ESP8266-Arduino,spapadim\/Arduino,myrtleTree33\/Arduino,paulmand3l\/Arduino,drpjk\/Arduino,fungxu\/Arduino,smily77\/Arduino,myrtleTree33\/Arduino,myrtleTree33\/Arduino,eeijcea\/Arduino-1,mateuszdw\/Arduino,aichi\/Arduino-2,noahchense\/Arduino-1,danielchalef\/Arduino,jomolinare\/Arduino,shiitakeo\/Arduino,leftbrainstrain\/Arduino-ESP8266,paulo-raca\/ESP8266-Arduino,paulmand3l\/Arduino,tannewt\/Arduino,tannewt\/Arduino,nkolban\/Arduino,Cloudino\/Cloudino-Arduino-IDE,Alfredynho\/AgroSis,smily77\/Arduino,spapadim\/Arduino,mateuszdw\/Arduino,NeuralSpaz\/Arduino,weera00\/Arduino,drpjk\/Arduino,aichi\/Arduino-2,radut\/Arduino,tannewt\/Arduino","old_file":"hardware\/esp8266com\/esp8266\/tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"hardware\/esp8266com\/esp8266\/tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *spiffs*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *spiffs*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"2cb2ada9b66234363ebea309d054c90cdd7ad87b","subject":"SiLabs Pearl: Mbed support for linker script","message":"SiLabs Pearl: Mbed support for linker script\n\nMbed needs to have interrupt vectors in RAM so reserve space at\nthe beginning of memory, and export the relevant symbols.\n","repos":"pradeep-gr\/mbed-os5-onsemi,svastm\/mbed,fahhem\/mbed-os,tung7970\/mbed-os-1,monkiineko\/mbed-os,betzw\/mbed-os,theotherjimmy\/mbed,svogl\/mbed-os,fanghuaqi\/mbed,fvincenzo\/mbed-os,c1728p9\/mbed-os,nRFMesh\/mbed-os,kl-cruz\/mbed-os,kjbracey-arm\/mbed,nRFMesh\/mbed-os,tung7970\/mbed-os,netzimme\/mbed-os,adamgreen\/mbed,jeremybrodt\/mbed,DanKupiniak\/mbed,adustm\/mbed,rgrover\/mbed,bcostm\/mbed-os,karsev\/mbed-os,betzw\/mbed-os,mbedmicro\/mbed,infinnovation\/mbed-os,mazimkhan\/mbed-os,cvtsi2sd\/mbed-os,ARM-software\/mbed-beetle,tung7970\/mbed-os,arostm\/mbed-os,geky\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,Archcady\/mbed-os,svastm\/mbed,mikaleppanen\/mbed-os,screamerbg\/mbed,adamgreen\/mbed,jrjang\/mbed,rgrover\/mbed,bcostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,theotherjimmy\/mbed,maximmbed\/mbed,ryankurte\/mbed-os,HeadsUpDisplayInc\/mbed,tung7970\/mbed-os,kl-cruz\/mbed-os,fvincenzo\/mbed-os,andreaslarssonublox\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,CalSol\/mbed,karsev\/mbed-os,nRFMesh\/mbed-os,mmorenobarm\/mbed-os,CalSol\/mbed,RonEld\/mbed,mazimkhan\/mbed-os,NXPmicro\/mbed,fvincenzo\/mbed-os,andreaslarssonublox\/mbed,j-greffe\/mbed-os,fahhem\/mbed-os,screamerbg\/mbed,HeadsUpDisplayInc\/mbed,Shengliang\/mbed,nvlsianpu\/mbed,NXPmicro\/mbed,bcostm\/mbed-os,karsev\/mbed-os,mazimkhan\/mbed-os,cvtsi2sd\/mbed-os,CalSol\/mbed,CalSol\/mbed,maximmbed\/mbed,geky\/mbed,HeadsUpDisplayInc\/mbed,cvtsi2sd\/mbed-os,j-greffe\/mbed-os,svogl\/mbed-os,tung7970\/mbed-os-1,fanghuaqi\/mbed,nRFMesh\/mbed-os,theotherjimmy\/mbed,arostm\/mbed-os,mbedmicro\/mbed,CalSol\/mbed,netzimme\/mbed-os,fahhem\/mbed-os,YarivCol\/mbed-os,jrjang\/mbed,NXPmicro\/mbed,RonEld\/mbed,bulislaw\/mbed-os,ARM-software\/mbed-beetle,c1728p9\/mbed-os,DanKupiniak\/mbed,catiedev\/mbed-os,ryankurte\/mbed-os,Archcady\/mbed-os,monkiineko\/mbed-os,maximmbed\/mbed,bulislaw\/mbed-os,kjbracey-arm\/mbed,screamerbg\/mbed,mazimkhan\/mbed-os,Shengliang\/mbed,bikeNomad\/mbed,fanghuaqi\/mbed,DanKupiniak\/mbed,RonEld\/mbed,screamerbg\/mbed,tung7970\/mbed-os-1,geky\/mbed,bcostm\/mbed-os,Shengliang\/mbed,Shengliang\/mbed,monkiineko\/mbed-os,svogl\/mbed-os,nvlsianpu\/mbed,catiedev\/mbed-os,ryankurte\/mbed-os,kl-cruz\/mbed-os,andreaslarssonublox\/mbed,YarivCol\/mbed-os,maximmbed\/mbed,infinnovation\/mbed-os,bulislaw\/mbed-os,geky\/mbed,andcor02\/mbed-os,mikaleppanen\/mbed-os,andreaslarssonublox\/mbed,kl-cruz\/mbed-os,jeremybrodt\/mbed,fahhem\/mbed-os,mmorenobarm\/mbed-os,kjbracey-arm\/mbed,jrjang\/mbed,kl-cruz\/mbed-os,mazimkhan\/mbed-os,RonEld\/mbed,adustm\/mbed,fanghuaqi\/mbed,adamgreen\/mbed,bcostm\/mbed-os,rgrover\/mbed,tung7970\/mbed-os-1,fanghuaqi\/mbed,fvincenzo\/mbed-os,mmorenobarm\/mbed-os,betzw\/mbed-os,jrjang\/mbed,mazimkhan\/mbed-os,arostm\/mbed-os,bulislaw\/mbed-os,tung7970\/mbed-os-1,svogl\/mbed-os,kl-cruz\/mbed-os,andcor02\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,DanKupiniak\/mbed,HeadsUpDisplayInc\/mbed,theotherjimmy\/mbed,mbedmicro\/mbed,Archcady\/mbed-os,infinnovation\/mbed-os,dbestm\/mbed,fahhem\/mbed-os,infinnovation\/mbed-os,adustm\/mbed,netzimme\/mbed-os,NXPmicro\/mbed,karsev\/mbed-os,jeremybrodt\/mbed,theotherjimmy\/mbed,svogl\/mbed-os,catiedev\/mbed-os,RonEld\/mbed,c1728p9\/mbed-os,mbedmicro\/mbed,dbestm\/mbed,nvlsianpu\/mbed,CalSol\/mbed,arostm\/mbed-os,dbestm\/mbed,betzw\/mbed-os,cvtsi2sd\/mbed-os,jrjang\/mbed,j-greffe\/mbed-os,adamgreen\/mbed,bulislaw\/mbed-os,NXPmicro\/mbed,bcostm\/mbed-os,nvlsianpu\/mbed,adustm\/mbed,screamerbg\/mbed,jeremybrodt\/mbed,svogl\/mbed-os,adustm\/mbed,andcor02\/mbed-os,mmorenobarm\/mbed-os,andcor02\/mbed-os,ARM-software\/mbed-beetle,maximmbed\/mbed,fahhem\/mbed-os,ryankurte\/mbed-os,j-greffe\/mbed-os,cvtsi2sd\/mbed-os,adamgreen\/mbed,netzimme\/mbed-os,arostm\/mbed-os,bikeNomad\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,svastm\/mbed,ryankurte\/mbed-os,theotherjimmy\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,Shengliang\/mbed,betzw\/mbed-os,nvlsianpu\/mbed,ryankurte\/mbed-os,j-greffe\/mbed-os,bikeNomad\/mbed,dbestm\/mbed,andcor02\/mbed-os,catiedev\/mbed-os,netzimme\/mbed-os,svastm\/mbed,YarivCol\/mbed-os,dbestm\/mbed,infinnovation\/mbed-os,bulislaw\/mbed-os,andcor02\/mbed-os,ARM-software\/mbed-beetle,mikaleppanen\/mbed-os,mikaleppanen\/mbed-os,cvtsi2sd\/mbed-os,tung7970\/mbed-os,tung7970\/mbed-os,RonEld\/mbed,YarivCol\/mbed-os,Archcady\/mbed-os,fvincenzo\/mbed-os,andreaslarssonublox\/mbed,rgrover\/mbed,jrjang\/mbed,Archcady\/mbed-os,YarivCol\/mbed-os,svastm\/mbed,catiedev\/mbed-os,karsev\/mbed-os,betzw\/mbed-os,nRFMesh\/mbed-os,c1728p9\/mbed-os,geky\/mbed,Shengliang\/mbed,YarivCol\/mbed-os,jeremybrodt\/mbed,mmorenobarm\/mbed-os,infinnovation\/mbed-os,maximmbed\/mbed,dbestm\/mbed,pradeep-gr\/mbed-os5-onsemi,arostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,pradeep-gr\/mbed-os5-onsemi,mikaleppanen\/mbed-os,karsev\/mbed-os,nRFMesh\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,HeadsUpDisplayInc\/mbed,rgrover\/mbed,adamgreen\/mbed,monkiineko\/mbed-os,catiedev\/mbed-os,j-greffe\/mbed-os,screamerbg\/mbed,HeadsUpDisplayInc\/mbed,Archcady\/mbed-os,bikeNomad\/mbed,netzimme\/mbed-os,bikeNomad\/mbed,nvlsianpu\/mbed,pradeep-gr\/mbed-os5-onsemi,adustm\/mbed,monkiineko\/mbed-os,monkiineko\/mbed-os,c1728p9\/mbed-os,mikaleppanen\/mbed-os,c1728p9\/mbed-os,NXPmicro\/mbed,mmorenobarm\/mbed-os","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_Silicon_Labs\/TARGET_EFM32\/TARGET_EFM32PG_STKXXXX\/TOOLCHAIN_GCC_ARM\/efm32pg1b.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_Silicon_Labs\/TARGET_EFM32\/TARGET_EFM32PG_STKXXXX\/TOOLCHAIN_GCC_ARM\/efm32pg1b.ld","new_contents":"\/* Linker script for Silicon Labs EFM32PG1B devices *\/\n\/*                                                                  *\/\n\/* This file is subject to the license terms as defined in ARM's    *\/\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\n\/* Example Code.                                                    *\/\n\/*                                                                  *\/\n\/* Silicon Laboratories, Inc. 2015                                  *\/\n\/*                                                                  *\/\n\/* Version 4.1.0 *\/\n\/*                                                                  *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768\n}\n\n\/* MBED: mbed needs to be able to dynamically set the interrupt vector table.\n * We make room for the table at the very beginning of RAM, i.e. at\n * 0x20000000. We need (16+34) * sizeof(uint32_t) = 200 bytes for EFM32LG *\/\n__vector_size = 0xC8;\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __Vectors_End\n *   __Vectors_Size\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    __Vectors_End = .;\n    __Vectors_Size = __Vectors_End - __Vectors;\n    __end__ = .;\n\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    \/* .ctors *\/\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    \/* .dtors *\/\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  \/* To copy multiple ROM to RAM sections,\n   * uncomment .copy.table section and,\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n  \/*\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG (__data_end__ - __data_start__)\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG (__data2_end__ - __data2_start__)\n    __copy_table_end__ = .;\n  } > FLASH\n  *\/\n\n  \/* To clear multiple BSS sections,\n   * uncomment .zero.table section and,\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n  \/*\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    LONG (__bss_start__)\n    LONG (__bss_end__ - __bss_start__)\n    LONG (__bss2_start__)\n    LONG (__bss2_end__ - __bss2_start__)\n    __zero_table_end__ = .;\n  } > FLASH\n  *\/\n\n  __etext = .;\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    PROVIDE( __start_vector_table__ = .);\n    . += __vector_size;\n    PROVIDE( __end_vector_table__ = .);\n    *(vtable)\n    *(.data*)\n    . = ALIGN (4);\n    *(.ram)\n\n    . = ALIGN(4);\n    \/* preinit data *\/\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    \/* init data *\/\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    \/* finit data *\/\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    \/* All data end *\/\n    __data_end__ = .;\n\n  } > RAM\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM\n\n  .heap (COPY):\n  {\n    __HeapBase = .;\n    __end__ = .;\n    end = __end__;\n    _end = __end__;\n    KEEP(*(.heap*))\n    __HeapLimit = .;\n  } > RAM\n\n  \/* .stack_dummy section doesn't contains any symbols. It is only\n   * used for linker to calculate size of stack sections, and assign\n   * values to stack symbols later *\/\n  .stack_dummy (COPY):\n  {\n    KEEP(*(.stack*))\n  } > RAM\n\n  \/* Set stack top to end of RAM, and stack limit move down by\n   * size of stack_dummy section *\/\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n  PROVIDE(__stack = __StackTop);\n\n  \/* Check if data + heap + stack exceeds RAM limit *\/\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n  \/* Check if FLASH usage exceeds FLASH size *\/\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\n}\n","old_contents":"\/* Linker script for Silicon Labs EFM32PG1B devices *\/\n\/*                                                                  *\/\n\/* This file is subject to the license terms as defined in ARM's    *\/\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\n\/* Example Code.                                                    *\/\n\/*                                                                  *\/\n\/* Silicon Laboratories, Inc. 2015                                  *\/\n\/*                                                                  *\/\n\/* Version 4.1.0 *\/\n\/*                                                                  *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __Vectors_End\n *   __Vectors_Size\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    __Vectors_End = .;\n    __Vectors_Size = __Vectors_End - __Vectors;\n    __end__ = .;\n\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    \/* .ctors *\/\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    \/* .dtors *\/\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  \/* To copy multiple ROM to RAM sections,\n   * uncomment .copy.table section and,\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n  \/*\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG (__data_end__ - __data_start__)\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG (__data2_end__ - __data2_start__)\n    __copy_table_end__ = .;\n  } > FLASH\n  *\/\n\n  \/* To clear multiple BSS sections,\n   * uncomment .zero.table section and,\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n  \/*\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    LONG (__bss_start__)\n    LONG (__bss_end__ - __bss_start__)\n    LONG (__bss2_start__)\n    LONG (__bss2_end__ - __bss2_start__)\n    __zero_table_end__ = .;\n  } > FLASH\n  *\/\n\n  __etext = .;\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data*)\n    . = ALIGN (4);\n    *(.ram)\n\n    . = ALIGN(4);\n    \/* preinit data *\/\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    \/* init data *\/\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    \/* finit data *\/\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    \/* All data end *\/\n    __data_end__ = .;\n\n  } > RAM\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM\n\n  .heap (COPY):\n  {\n    __HeapBase = .;\n    __end__ = .;\n    end = __end__;\n    _end = __end__;\n    KEEP(*(.heap*))\n    __HeapLimit = .;\n  } > RAM\n\n  \/* .stack_dummy section doesn't contains any symbols. It is only\n   * used for linker to calculate size of stack sections, and assign\n   * values to stack symbols later *\/\n  .stack_dummy (COPY):\n  {\n    KEEP(*(.stack*))\n  } > RAM\n\n  \/* Set stack top to end of RAM, and stack limit move down by\n   * size of stack_dummy section *\/\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n  PROVIDE(__stack = __StackTop);\n\n  \/* Check if data + heap + stack exceeds RAM limit *\/\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n  \/* Check if FLASH usage exceeds FLASH size *\/\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5144f9e40504be5a9c4f16d3fc0748d7e975d733","subject":"increased stack size to 16 KB","message":"increased stack size to 16 KB\n","repos":"jhseu\/tensorflow,paolodedios\/tensorflow,annarev\/tensorflow,theflofly\/tensorflow,aam-at\/tensorflow,gunan\/tensorflow,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,ppwwyyxx\/tensorflow,frreiss\/tensorflow-fred,cxxgtxy\/tensorflow,Intel-tensorflow\/tensorflow,alsrgv\/tensorflow,jbedorf\/tensorflow,karllessard\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_tf_optimizer,adit-chandra\/tensorflow,frreiss\/tensorflow-fred,sarvex\/tensorflow,yongtang\/tensorflow,ageron\/tensorflow,alsrgv\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-tensorflow\/tensorflow,adit-chandra\/tensorflow,paolodedios\/tensorflow,petewarden\/tensorflow,renyi533\/tensorflow,renyi533\/tensorflow,freedomtan\/tensorflow,DavidNorman\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,theflofly\/tensorflow,annarev\/tensorflow,arborh\/tensorflow,theflofly\/tensorflow,Intel-Corporation\/tensorflow,davidzchen\/tensorflow,petewarden\/tensorflow,gautam1858\/tensorflow,freedomtan\/tensorflow,yongtang\/tensorflow,alsrgv\/tensorflow,yongtang\/tensorflow,kevin-coder\/tensorflow-fork,jbedorf\/tensorflow,arborh\/tensorflow,Intel-Corporation\/tensorflow,alsrgv\/tensorflow,ppwwyyxx\/tensorflow,jhseu\/tensorflow,frreiss\/tensorflow-fred,xzturn\/tensorflow,ppwwyyxx\/tensorflow,jhseu\/tensorflow,ageron\/tensorflow,frreiss\/tensorflow-fred,kevin-coder\/tensorflow-fork,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,ageron\/tensorflow,yongtang\/tensorflow,paolodedios\/tensorflow,jbedorf\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,sarvex\/tensorflow,ageron\/tensorflow,DavidNorman\/tensorflow,chemelnucfin\/tensorflow,jbedorf\/tensorflow,renyi533\/tensorflow,davidzchen\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,cxxgtxy\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,ageron\/tensorflow,jhseu\/tensorflow,karllessard\/tensorflow,chemelnucfin\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-experimental_link_static_libraries_once,freedomtan\/tensorflow,gautam1858\/tensorflow,jbedorf\/tensorflow,Intel-tensorflow\/tensorflow,aam-at\/tensorflow,davidzchen\/tensorflow,petewarden\/tensorflow,freedomtan\/tensorflow,yongtang\/tensorflow,freedomtan\/tensorflow,chemelnucfin\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,gunan\/tensorflow,aam-at\/tensorflow,ppwwyyxx\/tensorflow,renyi533\/tensorflow,alsrgv\/tensorflow,ppwwyyxx\/tensorflow,ageron\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,freedomtan\/tensorflow,arborh\/tensorflow,adit-chandra\/tensorflow,jbedorf\/tensorflow,davidzchen\/tensorflow,gautam1858\/tensorflow,gautam1858\/tensorflow,petewarden\/tensorflow,annarev\/tensorflow,kevin-coder\/tensorflow-fork,adit-chandra\/tensorflow,aam-at\/tensorflow,freedomtan\/tensorflow,ghchinoy\/tensorflow,ghchinoy\/tensorflow,freedomtan\/tensorflow,DavidNorman\/tensorflow,jbedorf\/tensorflow,DavidNorman\/tensorflow,karllessard\/tensorflow,adit-chandra\/tensorflow,frreiss\/tensorflow-fred,xzturn\/tensorflow,arborh\/tensorflow,annarev\/tensorflow,ppwwyyxx\/tensorflow,karllessard\/tensorflow,theflofly\/tensorflow,ageron\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,jhseu\/tensorflow,arborh\/tensorflow,kevin-coder\/tensorflow-fork,gunan\/tensorflow,renyi533\/tensorflow,jbedorf\/tensorflow,arborh\/tensorflow,sarvex\/tensorflow,gautam1858\/tensorflow,renyi533\/tensorflow,annarev\/tensorflow,Intel-Corporation\/tensorflow,ageron\/tensorflow,gunan\/tensorflow,alsrgv\/tensorflow,gunan\/tensorflow,Intel-tensorflow\/tensorflow,cxxgtxy\/tensorflow,aam-at\/tensorflow,chemelnucfin\/tensorflow,xzturn\/tensorflow,arborh\/tensorflow,alsrgv\/tensorflow,jbedorf\/tensorflow,gunan\/tensorflow,yongtang\/tensorflow,Intel-Corporation\/tensorflow,frreiss\/tensorflow-fred,chemelnucfin\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,aam-at\/tensorflow,xzturn\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,jhseu\/tensorflow,petewarden\/tensorflow,davidzchen\/tensorflow,petewarden\/tensorflow,alsrgv\/tensorflow,gunan\/tensorflow,ageron\/tensorflow,ppwwyyxx\/tensorflow,annarev\/tensorflow,DavidNorman\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,aam-at\/tensorflow,xzturn\/tensorflow,davidzchen\/tensorflow,chemelnucfin\/tensorflow,chemelnucfin\/tensorflow,kevin-coder\/tensorflow-fork,Intel-tensorflow\/tensorflow,jhseu\/tensorflow,aam-at\/tensorflow,jbedorf\/tensorflow,frreiss\/tensorflow-fred,adit-chandra\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,theflofly\/tensorflow,ghchinoy\/tensorflow,theflofly\/tensorflow,annarev\/tensorflow,theflofly\/tensorflow,ghchinoy\/tensorflow,petewarden\/tensorflow,aldian\/tensorflow,jhseu\/tensorflow,kevin-coder\/tensorflow-fork,arborh\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow,Intel-Corporation\/tensorflow,jhseu\/tensorflow,arborh\/tensorflow,paolodedios\/tensorflow,adit-chandra\/tensorflow,xzturn\/tensorflow,DavidNorman\/tensorflow,karllessard\/tensorflow,ghchinoy\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,kevin-coder\/tensorflow-fork,alsrgv\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,ageron\/tensorflow,paolodedios\/tensorflow,davidzchen\/tensorflow,renyi533\/tensorflow,gunan\/tensorflow,gautam1858\/tensorflow,petewarden\/tensorflow,Intel-tensorflow\/tensorflow,kevin-coder\/tensorflow-fork,xzturn\/tensorflow,xzturn\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow,sarvex\/tensorflow,gunan\/tensorflow,gunan\/tensorflow,aldian\/tensorflow,cxxgtxy\/tensorflow,Intel-tensorflow\/tensorflow,xzturn\/tensorflow,freedomtan\/tensorflow,aam-at\/tensorflow,karllessard\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-Corporation\/tensorflow,alsrgv\/tensorflow,tensorflow\/tensorflow,chemelnucfin\/tensorflow,adit-chandra\/tensorflow,theflofly\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,aldian\/tensorflow,davidzchen\/tensorflow,aam-at\/tensorflow,theflofly\/tensorflow,ghchinoy\/tensorflow,adit-chandra\/tensorflow,sarvex\/tensorflow,DavidNorman\/tensorflow,ghchinoy\/tensorflow,aam-at\/tensorflow,ageron\/tensorflow,DavidNorman\/tensorflow,davidzchen\/tensorflow,renyi533\/tensorflow,yongtang\/tensorflow,alsrgv\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,ppwwyyxx\/tensorflow,Intel-tensorflow\/tensorflow,xzturn\/tensorflow,ghchinoy\/tensorflow,chemelnucfin\/tensorflow,DavidNorman\/tensorflow,kevin-coder\/tensorflow-fork,jhseu\/tensorflow,aldian\/tensorflow,renyi533\/tensorflow,jhseu\/tensorflow,theflofly\/tensorflow,sarvex\/tensorflow,frreiss\/tensorflow-fred,kevin-coder\/tensorflow-fork,alsrgv\/tensorflow,aldian\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,renyi533\/tensorflow,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,gautam1858\/tensorflow,DavidNorman\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,aam-at\/tensorflow,chemelnucfin\/tensorflow,gautam1858\/tensorflow,ppwwyyxx\/tensorflow,arborh\/tensorflow,cxxgtxy\/tensorflow,davidzchen\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,davidzchen\/tensorflow,gunan\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,paolodedios\/tensorflow,adit-chandra\/tensorflow,xzturn\/tensorflow,gautam1858\/tensorflow,annarev\/tensorflow,jhseu\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,frreiss\/tensorflow-fred,annarev\/tensorflow,annarev\/tensorflow,cxxgtxy\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow,arborh\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,aldian\/tensorflow,xzturn\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,ghchinoy\/tensorflow,DavidNorman\/tensorflow,paolodedios\/tensorflow,arborh\/tensorflow,paolodedios\/tensorflow,adit-chandra\/tensorflow,theflofly\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow,Intel-Corporation\/tensorflow,chemelnucfin\/tensorflow,ghchinoy\/tensorflow,theflofly\/tensorflow,freedomtan\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow,ghchinoy\/tensorflow,sarvex\/tensorflow,annarev\/tensorflow,jbedorf\/tensorflow,kevin-coder\/tensorflow-fork,DavidNorman\/tensorflow,Intel-Corporation\/tensorflow,ghchinoy\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,ppwwyyxx\/tensorflow,adit-chandra\/tensorflow,tensorflow\/tensorflow,chemelnucfin\/tensorflow,tensorflow\/tensorflow,ageron\/tensorflow,yongtang\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_tf_optimizer,aldian\/tensorflow,aldian\/tensorflow,renyi533\/tensorflow,renyi533\/tensorflow,yongtang\/tensorflow,freedomtan\/tensorflow,gunan\/tensorflow,tensorflow\/tensorflow,davidzchen\/tensorflow,jbedorf\/tensorflow","old_file":"tensorflow\/lite\/experimental\/micro\/tools\/make\/targets\/ecm3531\/ecm3531.lds","new_file":"tensorflow\/lite\/experimental\/micro\/tools\/make\/targets\/ecm3531\/ecm3531.lds","new_contents":"\/* Copyright 2015 The TensorFlow Authors. All Rights Reserved.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n==============================================================================*\/\n\n\n\/*\n * linker script for use with ECM3531\n * All sections must map to 128KBytes of SRAM beginning at 0x10000000\n *\n *\/\n\n \/*\n  * Indicate to the linker the entry point.\n  *\/\nENTRY(ResetISR)\n\n\/*\n *   SRAM is at 0x10000000 of length 0x00020000\n *\/\nMEMORY\n{\n    SRAM (RWX) : ORIGIN = 0x10000000, LENGTH = 0x00020000\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        . = ALIGN(0x4);\n        *(.text*)\n        . = ALIGN(0x4);\n        *(.rodata*)\n        . = ALIGN(0x4);\n        _etext = .;\n    } > SRAM= 0\n    .dummy :\n    {\n        . = ALIGN(0x4);\n        _eftext = .;\n    } > SRAM\n    .datax :\n    {\n        _datax = .;\n        KEEP(*(.mainStack))\n        . += 16384;\n        _edatax = .;\n        _stack_top = .;\n        . += 4;\n    } > SRAM\n    .data :\n       AT (ADDR(.text) + SIZEOF(.text) ) \n    {\n        _data = .;\n        *(.data*)\n        KEEP(*(.mainHeap))\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n    .ARM.exidx :\n    {\n       *(.ARM.exidx*)\n    }\n\n}\n\n","old_contents":"\/* Copyright 2015 The TensorFlow Authors. All Rights Reserved.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n==============================================================================*\/\n\n\n\/*\n * linker script for use with ECM3531\n * All sections must map to 128KBytes of SRAM beginning at 0x10000000\n *\n *\/\n\n \/*\n  * Indicate to the linker the entry point.\n  *\/\nENTRY(ResetISR)\n\n\/*\n *   SRAM is at 0x10000000 of length 0x00020000\n *\/\nMEMORY\n{\n    SRAM (RWX) : ORIGIN = 0x10000000, LENGTH = 0x00020000\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        . = ALIGN(0x4);\n        *(.text*)\n        . = ALIGN(0x4);\n        *(.rodata*)\n        . = ALIGN(0x4);\n        _etext = .;\n    } > SRAM= 0\n    .dummy :\n    {\n        . = ALIGN(0x4);\n        _eftext = .;\n    } > SRAM\n    .datax :\n    {\n        _datax = .;\n        KEEP(*(.mainStack))\n        . += 12288;\n        _edatax = .;\n        _stack_top = .;\n        . += 4;\n    } > SRAM\n    .data :\n       AT (ADDR(.text) + SIZEOF(.text) ) \n    {\n        _data = .;\n        *(.data*)\n        KEEP(*(.mainHeap))\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n    .ARM.exidx :\n    {\n       *(.ARM.exidx*)\n    }\n\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"dc9c69410c36d775e818cceed65bab444ad92ffb","subject":"Place all .rodata.* in the same section","message":"Place all .rodata.* in the same section\n\n","repos":"SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl","old_file":"build\/linker.lds","new_file":"build\/linker.lds","new_contents":"OUTPUT_ARCH(mips)\nENTRY(__start)\n\nSECTIONS\n{\n       \t. = 0x1000000;\n       \t.text ALIGN(4)  : { *(.init) *(.text) *(.text.*) }\n       \t. = 0x0;\n       \t.data ALIGN(16) : { *(.data0) *(.data) *(.rodata.str1.4)  *(.rodata.cst4) *(.rodata.cst8) *(.reginfo) }\n       \t.rodata ALIGN(16) : { *(.rodata) *(.rodata.*) }\n\tPROVIDE(__ctors_begin = .);\n\t.ctors ALIGN(4): { *(.ctors) }\n\tPROVIDE(__ctors_end = .);\n\tPROVIDE(__dtors_begin = .);\n\t.dtors ALIGN(4): { *(.dtors) }\n\tPROVIDE(__dtors_end = .);\n       \t.bss  ALIGN(16) : { *(.bss) *(.scommon) *(.sbss) }\n       \tPROVIDE(__edata = .);\n\n\t\/* The string table with the system call names *\/\n\t. = 0xff000000;\n       \t.cibylstrtab : { *(.cibylstrtab) }\n}\n","old_contents":"OUTPUT_ARCH(mips)\nENTRY(__start)\n\nSECTIONS\n{\n       \t. = 0x1000000;\n       \t.text ALIGN(4)  : { *(.init) *(.text) *(.text.*) }\n       \t. = 0x0;\n       \t.data ALIGN(16) : { *(.data0) *(.data) *(.rodata.str1.4)  *(.rodata.cst4) *(.rodata.cst8) *(.reginfo) }\n       \t.rodata ALIGN(16) : { *(.rodata) }\n\tPROVIDE(__ctors_begin = .);\n\t.ctors ALIGN(4): { *(.ctors) }\n\tPROVIDE(__ctors_end = .);\n\tPROVIDE(__dtors_begin = .);\n\t.dtors ALIGN(4): { *(.dtors) }\n\tPROVIDE(__dtors_end = .);\n       \t.bss  ALIGN(16) : { *(.bss) *(.scommon) *(.sbss) }\n       \tPROVIDE(__edata = .);\n\n\t\/* The string table with the system call names *\/\n\t. = 0xff000000;\n       \t.cibylstrtab : { *(.cibylstrtab) }\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"f87d4ec6627e35375656b5e673ffd1691becd278","subject":"Combine .entry and .text sections","message":"Combine .entry and .text sections\n","repos":"Dentosal\/rust_os,Dentosal\/rust_os,Dentosal\/rust_os","old_file":"build_config\/linker.ld","new_file":"build_config\/linker.ld","new_contents":"OUTPUT_FORMAT(elf64-x86-64)\nENTRY(start)\n\nSECTIONS {\n    . = 0x1000000;\n\n    \/* All sections are 0x200000 = 0x200_000 = 2MiB aligned,\n    ** as that is the correct huge-page boundary alignment.\n    *\/\n\n    .text : ALIGN(0x200000) {\n        \/* ensure that the kernel entry code is at the beginning *\/\n        KEEP(*(.entry))\n        *(.text .text.*)\n    }\n\n    .rodata : ALIGN(0x200000) {\n        KEEP(*(.rodata .rodata.*))\n    }\n\n    \/* BSS contains stack, so in case of overflow (growing downwards) it\n    ** tries to write to .rodata section, which is conveniently read-only.\n    *\/\n    .bss : ALIGN(0x200000) {\n        *(.bss .bss.*)\n    }\n\n    .data : ALIGN(0x200000) {\n        *(.data .data.*)\n    }\n}\n","old_contents":"OUTPUT_FORMAT(elf64-x86-64)\nENTRY(start)\n\nSECTIONS {\n    . = 0x1000000;\n\n    \/*\n    All sections are 0x200000 = 0x200_000 = 2MiB aligned,\n    as that is the correct huge-page boundary alignment.\n    *\/\n\n    \/* ensure that the kernel entry code is at the beginning *\/\n    .entry : ALIGN(0x200000) {\n        KEEP(*(.entry))\n    }\n\n    .text : ALIGN(0x200000) {\n        *(.text .text.*)\n    }\n\n    .rodata : ALIGN(0x200000) {\n        KEEP(*(.rodata .rodata.*))\n    }\n\n    .data : ALIGN(0x200000) {\n        *(.data .data.*)\n    }\n\n    .bss : ALIGN(0x200000) {\n        *(.bss .bss.*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"623ce09a6039bf53111c3cedc81cf5faca848717","subject":"toolchain\/GCC\/gcc_arm.ld: Use external definition for memory regions.","message":"toolchain\/GCC\/gcc_arm.ld: Use external definition for memory regions.\n\nThese are MCU-specific so are stored under platform\/device.\n","repos":"pabigot\/bspacm,pabigot\/bspacm,pabigot\/bspacm,pabigot\/bspacm","old_file":"toolchain\/GCC\/gcc_arm.ld","new_file":"toolchain\/GCC\/gcc_arm.ld","new_contents":"\/* From CMSIS 4.00 specification CMSIS-SP-00300-r4p0-00rel0.zip\n * !! MODIFIED to support BSPACM (http:\/\/github.com\/pabigot\/bspacm)\n *\/\n\n\/* Include the device-specific memory map.  Pass \n * -L$(DEVICE_LDSCRIPT_PATH) to ld so the right one is located. *\/\nINCLUDE memory.ld\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000   \/* 256k *\/\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x08000   \/*  32k *\/\n}\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"bfa0eec9780a682c8197603e1f60d5c24a3adef3","subject":"Changed ld script for configuratio demo","message":"Changed ld script for configuratio demo\n","repos":"sashadidukh\/kaa,kallelzied\/kaa,zofuthan\/kaa,abohomol\/kaa,aglne\/kaa,abohomol\/kaa,sashadidukh\/kaa,abohomol\/kaa,Oleh-Kravchenko\/kaa,sashadidukh\/kaa,aglne\/kaa,sashadidukh\/kaa,kallelzied\/kaa,Deepnekroz\/kaa,rasendubi\/kaa,forGGe\/kaa,rasendubi\/kaa,Deepnekroz\/kaa,Oleh-Kravchenko\/kaa,vtkhir\/kaa,liuhu\/Kaa,rasendubi\/kaa,vtkhir\/kaa,forGGe\/kaa,Dubland\/kaa,forGGe\/kaa,forGGe\/kaa,Oleh-Kravchenko\/kaa,liuhu\/Kaa,vtkhir\/kaa,aglne\/kaa,liuhu\/Kaa,kallelzied\/kaa,aglne\/kaa,abohomol\/kaa,liuhu\/Kaa,sashadidukh\/kaa,Dubland\/kaa,Oleh-Kravchenko\/kaa,aglne\/kaa,liuhu\/Kaa,zofuthan\/kaa,zofuthan\/kaa,rasendubi\/kaa,aglne\/kaa,kallelzied\/kaa,Oleh-Kravchenko\/kaa,rasendubi\/kaa,Oleh-Kravchenko\/kaa,aglne\/kaa,rasendubi\/kaa,Deepnekroz\/kaa,Dubland\/kaa,Dubland\/kaa,liuhu\/Kaa,rasendubi\/kaa,Dubland\/kaa,abohomol\/kaa,Deepnekroz\/kaa,abohomol\/kaa,abohomol\/kaa,sashadidukh\/kaa,vtkhir\/kaa,Dubland\/kaa,zofuthan\/kaa,sashadidukh\/kaa,zofuthan\/kaa,forGGe\/kaa,sashadidukh\/kaa,vtkhir\/kaa,Deepnekroz\/kaa,Oleh-Kravchenko\/kaa,vtkhir\/kaa,Dubland\/kaa,kallelzied\/kaa,vtkhir\/kaa,forGGe\/kaa,forGGe\/kaa,zofuthan\/kaa,liuhu\/Kaa,vtkhir\/kaa,Deepnekroz\/kaa,kallelzied\/kaa,Deepnekroz\/kaa","old_file":"examples\/configurationdemo\/source\/esp8266\/ld\/eagle.app.v6.ld","new_file":"examples\/configurationdemo\/source\/esp8266\/ld\/eagle.app.v6.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\r\n\/* Linker Script for ld -N *\/\r\nMEMORY\r\n{\r\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\r\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\r\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x8000\r\n  irom0_0_seg :                       \torg = 0x40240000, len = 0x3C000\r\n}\r\n\r\nPHDRS\r\n{\r\n  dport0_0_phdr PT_LOAD;\r\n  dram0_0_phdr PT_LOAD;\r\n  dram0_0_bss_phdr PT_LOAD;\r\n  iram1_0_phdr PT_LOAD;\r\n  irom0_0_phdr PT_LOAD;\r\n}\r\n\r\n\/*  Default entry point:  *\/\r\nENTRY(call_user_start)\r\nEXTERN(_DebugExceptionVector)\r\nEXTERN(_DoubleExceptionVector)\r\nEXTERN(_KernelExceptionVector)\r\nEXTERN(_NMIExceptionVector)\r\nEXTERN(_UserExceptionVector)\r\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\r\n\/* Various memory-map dependent cache attribute settings: *\/\r\n_memmap_cacheattr_wb_base = 0x00000110;\r\n_memmap_cacheattr_wt_base = 0x00000110;\r\n_memmap_cacheattr_bp_base = 0x00000220;\r\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\r\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\r\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\r\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\r\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\r\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\r\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\r\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\r\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\r\n_memmap_cacheattr_wb_allvalid = 0x22222112;\r\n_memmap_cacheattr_wt_allvalid = 0x22222112;\r\n_memmap_cacheattr_bp_allvalid = 0x22222222;\r\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\r\n\r\nSECTIONS\r\n{\r\n\r\n  .dport0.rodata : ALIGN(4)\r\n  {\r\n    _dport0_rodata_start = ABSOLUTE(.);\r\n    *(.dport0.rodata)\r\n    *(.dport.rodata)\r\n    _dport0_rodata_end = ABSOLUTE(.);\r\n  } >dport0_0_seg :dport0_0_phdr\r\n\r\n  .dport0.literal : ALIGN(4)\r\n  {\r\n    _dport0_literal_start = ABSOLUTE(.);\r\n    *(.dport0.literal)\r\n    *(.dport.literal)\r\n    _dport0_literal_end = ABSOLUTE(.);\r\n  } >dport0_0_seg :dport0_0_phdr\r\n\r\n  .dport0.data : ALIGN(4)\r\n  {\r\n    _dport0_data_start = ABSOLUTE(.);\r\n    *(.dport0.data)\r\n    *(.dport.data)\r\n    _dport0_data_end = ABSOLUTE(.);\r\n  } >dport0_0_seg :dport0_0_phdr\r\n\r\n  .data : ALIGN(4)\r\n  {\r\n    _data_start = ABSOLUTE(.);\r\n    *(.data)\r\n    *(.data.*)\r\n    *(.gnu.linkonce.d.*)\r\n    *(.data1)\r\n    *(.sdata)\r\n    *(.sdata.*)\r\n    *(.gnu.linkonce.s.*)\r\n    *(.sdata2)\r\n    *(.sdata2.*)\r\n    *(.gnu.linkonce.s2.*)\r\n    *(.jcr)\r\n    _data_end = ABSOLUTE(.);\r\n  } >dram0_0_seg :dram0_0_phdr\r\n\r\n  .rodata : ALIGN(4)\r\n  {\r\n    _rodata_start = ABSOLUTE(.);\r\n    *(.rodata)\r\n    *(.rodata.*)\r\n    *(.gnu.linkonce.r.*)\r\n    *(.rodata1)\r\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\r\n    *(.xt_except_table)\r\n    *(.gcc_except_table)\r\n    *(.gnu.linkonce.e.*)\r\n    *(.gnu.version_r)\r\n    *(.eh_frame)\r\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    \/*  C++ exception handlers table:  *\/\r\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\r\n    *(.xt_except_desc)\r\n    *(.gnu.linkonce.h.*)\r\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\r\n    *(.xt_except_desc_end)\r\n    *(.dynamic)\r\n    *(.gnu.version_d)\r\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\r\n    _bss_table_start = ABSOLUTE(.);\r\n    LONG(_bss_start)\r\n    LONG(_bss_end)\r\n    _bss_table_end = ABSOLUTE(.);\r\n    _rodata_end = ABSOLUTE(.);\r\n  } >dram0_0_seg :dram0_0_phdr\r\n\r\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\r\n  {\r\n  \t_UserExceptionVector_literal_start = ABSOLUTE(.);\r\n  \t*(.UserExceptionVector.literal)\r\n  \t_UserExceptionVector_literal_end = ABSOLUTE(.);\r\n  } >dram0_0_seg :dram0_0_phdr\r\n\r\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\r\n  {\r\n    . = ALIGN (8);\r\n    _bss_start = ABSOLUTE(.);\r\n    *(.dynsbss)\r\n    *(.sbss)\r\n    *(.sbss.*)\r\n    *(.gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.sbss2)\r\n    *(.sbss2.*)\r\n    *(.gnu.linkonce.sb2.*)\r\n    *(.dynbss)\r\n    *(.bss)\r\n    *(.bss.*)\r\n    *(.gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    _bss_end = ABSOLUTE(.);\r\n    _heap_start = ABSOLUTE(.);\r\n\/*    _stack_sentry = ALIGN(0x8); *\/\r\n  } >dram0_0_seg :dram0_0_bss_phdr\r\n\/* __stack = 0x3ffc8000; *\/\r\n\r\n  .irom0.text : ALIGN(4)\r\n  {\r\n    _irom0_text_start = ABSOLUTE(.);\r\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\r\n    *libkaac_s.a:(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    *libesp-platform.a:(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    *liblwip.a:(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    *libnet80211.a:(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    *libgcc.a:( .text .text.*  .literal .literal.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    _irom0_text_end = ABSOLUTE(.);\r\n  } >irom0_0_seg :irom0_0_phdr\r\n\r\n\r\n  .text : ALIGN(4)\r\n  {\r\n    _stext = .;\r\n    _text_start = ABSOLUTE(.);\r\n    *(.UserEnter.text)\r\n    . = ALIGN(16);\r\n    *(.DebugExceptionVector.text)\r\n    . = ALIGN(16);\r\n    *(.NMIExceptionVector.text)\r\n    . = ALIGN(16);\r\n    *(.KernelExceptionVector.text)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    . = ALIGN(16);\r\n    *(.UserExceptionVector.text)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    . = ALIGN(16);\r\n    *(.DoubleExceptionVector.text)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    . = ALIGN (16);\r\n    *(.entry.text)\r\n    *(.init.literal)\r\n    *(.init)\r\n    *( .literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    *(.fini.literal)\r\n    *(.fini)\r\n    *(.gnu.version)\r\n    _text_end = ABSOLUTE(.);\r\n    _etext = .;\r\n  } >iram1_0_seg :iram1_0_phdr\r\n\r\n  .lit4 : ALIGN(4)\r\n  {\r\n    _lit4_start = ABSOLUTE(.);\r\n    *(*.lit4)\r\n    *(.lit4.*)\r\n    *(.gnu.linkonce.lit4.*)\r\n    _lit4_end = ABSOLUTE(.);\r\n  } >iram1_0_seg :iram1_0_phdr\r\n\r\n}\r\n\r\n\/* get ROM code address *\/\r\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\r\n\r\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\r\n\/* Linker Script for ld -N *\/\r\nMEMORY\r\n{\r\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\r\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\r\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x8000\r\n  irom0_0_seg :                       \torg = 0x40240000, len = 0x3C000\r\n}\r\n\r\nPHDRS\r\n{\r\n  dport0_0_phdr PT_LOAD;\r\n  dram0_0_phdr PT_LOAD;\r\n  dram0_0_bss_phdr PT_LOAD;\r\n  iram1_0_phdr PT_LOAD;\r\n  irom0_0_phdr PT_LOAD;\r\n}\r\n\r\n\/*  Default entry point:  *\/\r\nENTRY(call_user_start)\r\nEXTERN(_DebugExceptionVector)\r\nEXTERN(_DoubleExceptionVector)\r\nEXTERN(_KernelExceptionVector)\r\nEXTERN(_NMIExceptionVector)\r\nEXTERN(_UserExceptionVector)\r\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\r\n\/* Various memory-map dependent cache attribute settings: *\/\r\n_memmap_cacheattr_wb_base = 0x00000110;\r\n_memmap_cacheattr_wt_base = 0x00000110;\r\n_memmap_cacheattr_bp_base = 0x00000220;\r\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\r\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\r\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\r\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\r\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\r\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\r\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\r\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\r\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\r\n_memmap_cacheattr_wb_allvalid = 0x22222112;\r\n_memmap_cacheattr_wt_allvalid = 0x22222112;\r\n_memmap_cacheattr_bp_allvalid = 0x22222222;\r\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\r\n\r\nSECTIONS\r\n{\r\n\r\n  .dport0.rodata : ALIGN(4)\r\n  {\r\n    _dport0_rodata_start = ABSOLUTE(.);\r\n    *(.dport0.rodata)\r\n    *(.dport.rodata)\r\n    _dport0_rodata_end = ABSOLUTE(.);\r\n  } >dport0_0_seg :dport0_0_phdr\r\n\r\n  .dport0.literal : ALIGN(4)\r\n  {\r\n    _dport0_literal_start = ABSOLUTE(.);\r\n    *(.dport0.literal)\r\n    *(.dport.literal)\r\n    _dport0_literal_end = ABSOLUTE(.);\r\n  } >dport0_0_seg :dport0_0_phdr\r\n\r\n  .dport0.data : ALIGN(4)\r\n  {\r\n    _dport0_data_start = ABSOLUTE(.);\r\n    *(.dport0.data)\r\n    *(.dport.data)\r\n    _dport0_data_end = ABSOLUTE(.);\r\n  } >dport0_0_seg :dport0_0_phdr\r\n\r\n  .data : ALIGN(4)\r\n  {\r\n    _data_start = ABSOLUTE(.);\r\n    *(.data)\r\n    *(.data.*)\r\n    *(.gnu.linkonce.d.*)\r\n    *(.data1)\r\n    *(.sdata)\r\n    *(.sdata.*)\r\n    *(.gnu.linkonce.s.*)\r\n    *(.sdata2)\r\n    *(.sdata2.*)\r\n    *(.gnu.linkonce.s2.*)\r\n    *(.jcr)\r\n    _data_end = ABSOLUTE(.);\r\n  } >dram0_0_seg :dram0_0_phdr\r\n\r\n  .rodata : ALIGN(4)\r\n  {\r\n    _rodata_start = ABSOLUTE(.);\r\n    *(.rodata)\r\n    *(.rodata.*)\r\n    *(.gnu.linkonce.r.*)\r\n    *(.rodata1)\r\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\r\n    *(.xt_except_table)\r\n    *(.gcc_except_table)\r\n    *(.gnu.linkonce.e.*)\r\n    *(.gnu.version_r)\r\n    *(.eh_frame)\r\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    \/*  C++ exception handlers table:  *\/\r\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\r\n    *(.xt_except_desc)\r\n    *(.gnu.linkonce.h.*)\r\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\r\n    *(.xt_except_desc_end)\r\n    *(.dynamic)\r\n    *(.gnu.version_d)\r\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\r\n    _bss_table_start = ABSOLUTE(.);\r\n    LONG(_bss_start)\r\n    LONG(_bss_end)\r\n    _bss_table_end = ABSOLUTE(.);\r\n    _rodata_end = ABSOLUTE(.);\r\n  } >dram0_0_seg :dram0_0_phdr\r\n\r\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\r\n  {\r\n  \t_UserExceptionVector_literal_start = ABSOLUTE(.);\r\n  \t*(.UserExceptionVector.literal)\r\n  \t_UserExceptionVector_literal_end = ABSOLUTE(.);\r\n  } >dram0_0_seg :dram0_0_phdr\r\n\r\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\r\n  {\r\n    . = ALIGN (8);\r\n    _bss_start = ABSOLUTE(.);\r\n    *(.dynsbss)\r\n    *(.sbss)\r\n    *(.sbss.*)\r\n    *(.gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.sbss2)\r\n    *(.sbss2.*)\r\n    *(.gnu.linkonce.sb2.*)\r\n    *(.dynbss)\r\n    *(.bss)\r\n    *(.bss.*)\r\n    *(.gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    _bss_end = ABSOLUTE(.);\r\n    _heap_start = ABSOLUTE(.);\r\n\/*    _stack_sentry = ALIGN(0x8); *\/\r\n  } >dram0_0_seg :dram0_0_bss_phdr\r\n\/* __stack = 0x3ffc8000; *\/\r\n\r\n  .irom0.text : ALIGN(4)\r\n  {\r\n    _irom0_text_start = ABSOLUTE(.);\r\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\r\n    *libkaac_s.a:(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    libesp-platform.a:(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    \/opt\/Espressif\/esp-rtos-sdk\/lib\/liblwip.a:(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    \/opt\/Espressif\/esp-rtos-sdk\/lib\/libnet80211.a:(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    \/opt\/Espressif\/crosstool-NG\/builds\/xtensa-lx106-elf\/lib\/gcc\/xtensa-lx106-elf\/4.8.2\/libgcc.a:( .text .text.*  .literal .literal.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    \/*\/opt\/Espressif\/esp-rtos-sdk\/lib\/libfreertos.a:(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *\/\r\n    _irom0_text_end = ABSOLUTE(.);\r\n  } >irom0_0_seg :irom0_0_phdr\r\n\r\n\r\n  .text : ALIGN(4)\r\n  {\r\n    _stext = .;\r\n    _text_start = ABSOLUTE(.);\r\n    *(.UserEnter.text)\r\n    . = ALIGN(16);\r\n    *(.DebugExceptionVector.text)\r\n    . = ALIGN(16);\r\n    *(.NMIExceptionVector.text)\r\n    . = ALIGN(16);\r\n    *(.KernelExceptionVector.text)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    . = ALIGN(16);\r\n    *(.UserExceptionVector.text)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    . = ALIGN(16);\r\n    *(.DoubleExceptionVector.text)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    LONG(0)\r\n    . = ALIGN (16);\r\n    *(.entry.text)\r\n    *(.init.literal)\r\n    *(.init)\r\n    *( .literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    *(.fini.literal)\r\n    *(.fini)\r\n    *(.gnu.version)\r\n    _text_end = ABSOLUTE(.);\r\n    _etext = .;\r\n  } >iram1_0_seg :iram1_0_phdr\r\n\r\n  .lit4 : ALIGN(4)\r\n  {\r\n    _lit4_start = ABSOLUTE(.);\r\n    *(*.lit4)\r\n    *(.lit4.*)\r\n    *(.gnu.linkonce.lit4.*)\r\n    _lit4_end = ABSOLUTE(.);\r\n  } >iram1_0_seg :iram1_0_phdr\r\n\r\n}\r\n\r\n\/* get ROM code address *\/\r\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\r\n\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9a9f765c1e465732e79411a2adf644f086edded9","subject":"Update architecture to i586.","message":"Update architecture to i586.\n","repos":"Lucretia\/bare_bones","old_file":"src\/pc\/linker.ld","new_file":"src\/pc\/linker.ld","new_contents":"OUTPUT_FORMAT(elf32-i586)\nSTARTUP(startup.o)\nENTRY (startup)\n\nSECTIONS\n{\n    . = 0x00100000;\n\n    .text : {\n        *(.text)\n    }\n\n    .rodata ALIGN (0x1000) : {\n        *(.rodata)\n    }\n\n    .data ALIGN (0x1000) : {\n        *(.data)\n    }\n\n    .bss : {\n        *(COMMON)\n        *(.bss)\n    }\n\n    .note : {\n    \t  *(.note)\n    }\n\n    .debug : {\n    \t  *(.debug)\n    }\n}\n","old_contents":"OUTPUT_FORMAT(elf32-i386)\nSTARTUP(startup.o)\nENTRY (startup)\n\nSECTIONS\n{\n    . = 0x00100000;\n\n    .text : {\n        *(.text)\n    }\n\n    .rodata ALIGN (0x1000) : {\n        *(.rodata)\n    }\n\n    .data ALIGN (0x1000) : {\n        *(.data)\n    }\n\n    .bss : {\n        *(COMMON)\n        *(.bss)\n    }\n\n    .note : {\n    \t  *(.note)\n    }\n\n    .debug : {\n    \t  *(.debug)\n    }\n}\n","returncode":0,"stderr":"","license":"cc0-1.0","lang":"Linker Script"}
{"commit":"51e7d9af3119a6a8d2c986d7dc966e1963ea3d0f","subject":"stm32.ld: add unwind section","message":"stm32.ld: add unwind section\n","repos":"raphui\/rnk,raphui\/rnk,raphui\/rnk,raphui\/rnk","old_file":"stm32.ld","new_file":"stm32.ld","new_contents":"MEMORY\n{\n    sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 128K\n    CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K\n    flash (RX) : ORIGIN = 0x08000000, LENGTH = 1024K\n}\n\nSECTIONS\n{  \n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        PROVIDE(stext = .);\n        KEEP(*(.isr_vector))\n        *(.text .text.*)        \n        *(.rodata .rodata.*)        \n        *(.gnu.linkonce.t.*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.r.*)\n        . = ALIGN(4);\n        _etext = .;\n\t\t_sidata = _etext;\n        PROVIDE(etext = .);   \n     \t\t_fini = . ;\n\t\t\t\t*(.fini)\n\n    } >flash\n\n    .data : AT (_etext)\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.ramfunc .ramfunc.* .fastrun .fastrun.*)\n        *(.data .data.*)\n        *(.gnu.linkonce.d.*)\n        . = ALIGN(4);\n        _edata = .;\n    } >flash\n\t\t\n    .ARM.extab : AT (_edata)\n    {\n        *(.ARM.extab*)\n    } >flash\n\t\n    .ARM.exidx :\n    {\n        __exidx_start = .;\n\t*(.ARM.exidx*)\n\t__exidx_end = .;\n    } >flash\n\n    PROVIDE( flash_used_size = SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.ARM.extab) + SIZEOF(.ARM.exidx) );\n\t\t\n    .bss (NOLOAD) : {\n\t\t. = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n        *(.bss .bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN(4);        \n        _ebss = .;\n    } >sram\n    \n    end = .;\n    PROVIDE( _estack = 0x20020000 );\n}\n\n","old_contents":"MEMORY\n{\n    sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 128K\n    CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K\n    flash (RX) : ORIGIN = 0x08000000, LENGTH = 1024K\n}\n\nSECTIONS\n{  \n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        PROVIDE(stext = .);\n        KEEP(*(.isr_vector))\n        *(.text .text.*)        \n        *(.rodata .rodata.*)        \n        *(.gnu.linkonce.t.*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.r.*)\n        . = ALIGN(4);\n        _etext = .;\n\t\t_sidata = _etext;\n        PROVIDE(etext = .);   \n     \t\t_fini = . ;\n\t\t\t\t*(.fini)\n\n    } >flash\n\n    .data : AT (_etext)\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.ramfunc .ramfunc.* .fastrun .fastrun.*)\n        *(.data .data.*)\n        *(.gnu.linkonce.d.*)\n        . = ALIGN(4);\n        _edata = .;\n    } >sram\n\t\t\n\t\t.ARM.extab :\n\t\t{\n\t\t    *(.ARM.extab*)\n\t\t} >sram\n\t\t\n\t\t__exidx_start = .;\n\t\t.ARM.exidx :\n\t\t{\n\t\t    *(.ARM.exidx*)\n\t\t} >sram\n\t\t__exidx_end = .;\n\n    PROVIDE( flash_used_size = SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.ARM.extab) + SIZEOF(.ARM.exidx) );\n\t\t\n    .bss (NOLOAD) : {\n\t\t. = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n        *(.bss .bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN(4);        \n        _ebss = .;\n    } >sram\n    \n    end = .;\n    PROVIDE( _estack = 0x20020000 );\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"140f27ddc618734044d38c9fa94a173ea0012d5a","subject":"app_test: test with fixed link addr","message":"app_test: test with fixed link addr\n","repos":"raphui\/rnk,raphui\/rnk,raphui\/rnk,raphui\/rnk","old_file":"apps\/app_test\/apps.ld","new_file":"apps\/app_test\/apps.ld","new_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\/* Internal Memory Map*\/\nMEMORY\n{\n    rom (rx)  : ORIGIN = 0x08010000, LENGTH = 0x00100000\n    ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000\n    ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 0x00010000\n}\n \n_eram = 0x20000000 + 0x00020000;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    \/* collect all uninitialized .ccm sections *\/\n\t\/* A directed static allocation would look like this :\n\t\tvolatile uint8_t buff0[16384] __attribute__((section(\".ccm\")));   *\/\n\t.ccm (NOLOAD) :\n    {\n        . = ALIGN(4);\n        *(.ccm)\n        *(.ccm.*)\n        . = ALIGN(4);\n    } > ccm\n \n    .text :\n    {\n        _text = .;\n        KEEP(*(.isr_vector .isr_vector.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n    } > rom\n \n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > rom\n \n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    __exidx_end = .;\n \n    . = ALIGN(4);\n    _etext = .;\n    _sidata = .;\n \n    .data : AT (_etext)\n    {\n        _sdata = .;\n        *(.data .data.*)\n        . = ALIGN(4);\n        _edata = . ;\n    } > ram\n \n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        _sbss = . ;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n    } > ram\n \n    \/* stack section *\/\n    .co_stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        *(.co_stack .co_stack.*)\n    } > ram\n \n    . = ALIGN(4);\n    _end = . ;\n    PROVIDE( _estack = 0x20020000 );\n}\n","old_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\/* Internal Memory Map*\/\nMEMORY\n{\n    rom (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00100000\n    ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000\n    ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 0x00010000\n}\n \n_eram = 0x20000000 + 0x00020000;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    \/* collect all uninitialized .ccm sections *\/\n\t\/* A directed static allocation would look like this :\n\t\tvolatile uint8_t buff0[16384] __attribute__((section(\".ccm\")));   *\/\n\t.ccm (NOLOAD) :\n    {\n        . = ALIGN(4);\n        *(.ccm)\n        *(.ccm.*)\n        . = ALIGN(4);\n    } > ccm\n \n    .text :\n    {\n        _text = .;\n        KEEP(*(.isr_vector .isr_vector.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n    } > rom\n \n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > rom\n \n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    __exidx_end = .;\n \n    . = ALIGN(4);\n    _etext = .;\n    _sidata = .;\n \n    .data : AT (_etext)\n    {\n        _sdata = .;\n        *(.data .data.*)\n        . = ALIGN(4);\n        _edata = . ;\n    } > ram\n \n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        _sbss = . ;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n    } > ram\n \n    \/* stack section *\/\n    .co_stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        *(.co_stack .co_stack.*)\n    } > ram\n \n    . = ALIGN(4);\n    _end = . ;\n    PROVIDE( _estack = 0x20020000 );\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c5033b00da9533b26a733248c596dd3021e415b6","subject":"removed MinWG specific stuff so now two kernel.ld files are identical","message":"removed MinWG specific stuff so now two kernel.ld files are identical\n","repos":"jtauber\/cleese,jtauber\/cleese,jtauber\/cleese","old_file":"oneplusone\/kernel.ld","new_file":"oneplusone\/kernel.ld","new_contents":"\nENTRY(entry)\n\nLS_Phys = 0x100000; \/* 1 meg = load (physical) address *\/\nLS_Virt = 0x100000; \/* 1 meg = virtual address *\/\n\nSECTIONS\n{\n    .text LS_Virt : AT(LS_Phys)\n    {\n        LS_Code = .;\n        \n        \/* symbols to mark start of code segment *\/\n        code = .;\n        _code = .;\n        \n        \/* kernel code *\/\n        *(.text)\n        \n        \/* .rodata is the ELF constant data section *\/\n        *(.rodata*)\n        \n        . = ALIGN(4096);\n    }\n    \n    .data : AT(LS_Phys + (LS_Data - LS_Code))\n    {\n        LS_Data = .;\n        \n        \/* symbols to mark start of data segment *\/\n        data = .;\n        _data = .;\n        \n        \/* kernel data *\/\n        *(.data)\n        \n        . = ALIGN(4096);\n    }\n    \n    .bss : AT(LS_Phys + (LS_Bss - LS_Code))\n    {\n        LS_Bss = .;\n        \n        \/* symbols to mark start of BSS segment *\/\n        bss = .;\n        _bss = .;\n        \n        \/* kernel BSS *\/\n        *(.bss)\n        \n        \/* \"common\" variables *\/\n        *(COMMON)\n        \n        . = ALIGN(4096);\n    }\n    \n    \/* symbols to mark end of kernel *\/\n    end = .;\n    _end = .;\n}\n","old_contents":"\/* let the linker use its 'native' format (ELF\/COFF\/PE)\nOUTPUT_FORMAT(\"coff-go32\") *\/\n\/* no leading underscore for symbols handled in asm: *\/\n\nENTRY(entry)\n\nLS_Phys = 0x100000; \/* 1 meg = load (physical) address *\/\nLS_Virt = 0x100000; \/* 1 meg = virtual address *\/\n\nSECTIONS\n{\n    .text LS_Virt : AT(LS_Phys)\n    {\n        LS_Code = .;\n        \n        \/* symbols to mark start of code segment *\/\n        code = .;\n        _code = .;\n        \n        \/* kernel code *\/\n        *(.text)\n        \n        \/* .rodata is the ELF constant data section *\/\n        *(.rodata*)\n        \n        . = ALIGN(4096);\n    }\n    \n    .data : AT(LS_Phys + (LS_Data - LS_Code))\n    {\n        LS_Data = .;\n        \n        \/* symbols to mark start of data segment *\/\n        data = .;\n        _data = .;\n        \n        \/* kernel data *\/\n        *(.data)\n        \n        . = ALIGN(4096);\n    }\n    \n    .bss : AT(LS_Phys + (LS_Bss - LS_Code))\n    {\n        LS_Bss = .;\n        \n        \/* symbols to mark start of BSS segment *\/\n        bss = .;\n        _bss = .;\n        \n        \/* kernel BSS *\/\n        *(.bss)\n        \n        \/* \"common\" variables *\/\n        *(COMMON)\n        \n        . = ALIGN(4096);\n    }\n    \n    \/* bug in MinGW? I get a bad executable file unless these\n    sections are here... *\/\n    .stab :\n    {\n        *(.stab)\n    }\n    \n    .stabstr :\n    {\n        *(.stabstr)\n    }\n    \n    \/* symbols to mark end of kernel *\/\n    end = .;\n    _end = .;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"41bc13871d2005f77a87b10c628a661ee41d35a3","subject":"Issue #217 the fix was applied. Needs to be verified.","message":"Issue #217 the fix was applied. Needs to be verified.\n\n\nFormer-commit-id: 7e6b744037d108acbe3da9fea862240821bdbae7","repos":"tintin304\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX","old_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-32MX440F512H.ld","new_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-32MX440F512H.ld","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\n_ebase_address  = 0x9D000000;\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_RESET_ADDR              = 0x9D001000;\n_EEPROM_ADDR             = 0x9D07F000;\n_BEV_EXCPT_ADDR          = 0xBFC00380;\n_DBG_EXCPT_ADDR          = 0xBFC00480;\n_DBG_CODE_ADDR           = 0xBFC02000;\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n\n  kseg0_program_mem (rx)     : ORIGIN = 0x9D001000, LENGTH = 0x7B000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 \n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x8000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\nSECTIONS\n{\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg0_program_mem\n  \n  .eeprom_pic32 _EEPROM_ADDR :\n  { \n    . += 0x1000;\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n  .vector_0 _ebase_address + 0x200 :\n  {\n    KEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n\n    _text_end = . ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }>kseg0_program_mem\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n  }>kseg0_program_mem\n\n\n  \/* Read-only sections *\/\n  .rodata   :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } >kseg1_data_mem\n  .data  ALIGN(4)  :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _data_image_begin = LOADADDR(.data) ;\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit8           :\n  {\n    *(.lit8)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    _sbss_end = . ;\n  } >kseg1_data_mem\n  .bss ALIGN(4)  :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  \/DISCARD\/         : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  \/DISCARD\/         : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\n_ebase_address  = 0x9D000000;\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_RESET_ADDR              = 0x9D001000;\n_EEPROM_ADDR             = 0x9D07F000;\n_BEV_EXCPT_ADDR          = 0xBFC00380;\n_DBG_EXCPT_ADDR          = 0xBFC00480;\n_DBG_CODE_ADDR           = 0xBFC02000;\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7E000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 \n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x8000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\nSECTIONS\n{\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg0_program_mem\n  \n  .eeprom_pic32 _EEPROM_ADDR :\n  { \n    . += 0x1000;\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n  .vector_0 _ebase_address + 0x200 :\n  {\n    KEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n\n    _text_end = . ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }>kseg0_program_mem\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n  }>kseg0_program_mem\n\n\n  \/* Read-only sections *\/\n  .rodata   :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } >kseg1_data_mem\n  .data  ALIGN(4)  :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _data_image_begin = LOADADDR(.data) ;\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit8           :\n  {\n    *(.lit8)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    _sbss_end = . ;\n  } >kseg1_data_mem\n  .bss ALIGN(4)  :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  \/DISCARD\/         : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  \/DISCARD\/         : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"7338b11deaf6afe22a9714ccfb4e085e354f81c6","subject":"* small cleanup around checksum computation for LPC, still having troubles here","message":"* small cleanup around checksum computation for LPC, still having troubles here\n","repos":"Squantor\/lpc_81x_frame","old_file":"ld\/nxp_lpc812.ld","new_file":"ld\/nxp_lpc812.ld","new_contents":"\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-2013\n * (c) NXP Semiconductors 2013-2017\n * Generated linker script file for LPC812\n * Created from linkscript.ldt by FMCreateLinkLibraries\n * Using Freemarker v2.3.23\n * LPCXpresso v8.2.0 [Build 647] [2016-07-18]  on Apr 17, 2017 11:39:50 AM\n *\/\n\nGROUP (\n  libgcc.a\n  libc.a\n  libm.a\n)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash16 (rx) : ORIGIN = 0x0, LENGTH = 0x4000 \/* 16K bytes (alias Flash) *\/\n  RamLoc4 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x1000 \/* 4K bytes (alias RAM) *\/\n}\n\n  \/* Define a symbol for the top of each memory region *\/\n  __base_MFlash16 = 0x0  ; \/* MFlash16 *\/\n  __base_Flash = 0x0 ; \/* Flash *\/\n  __top_MFlash16 = 0x0 + 0x4000 ; \/* 16K bytes *\/\n  __top_Flash = 0x0 + 0x4000 ; \/* 16K bytes *\/\n  __base_RamLoc4 = 0x10000000  ; \/* RamLoc4 *\/\n  __base_RAM = 0x10000000 ; \/* RAM *\/\n  __top_RamLoc4 = 0x10000000 + 0x1000 ; \/* 4K bytes *\/\n  __top_RAM = 0x10000000 + 0x1000 ; \/* 4K bytes *\/\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n    \/* MAIN TEXT SECTION *\/\n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        __vectors_start__ = ABSOLUTE(.) ;\n        KEEP(*(.isr_vector))\n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n\t    \/* End of Global Section Table *\/\n\n        *(.after_vectors*)\n\n        \/* Code Read Protection data *\/\n        \/* Disable CRP for now *\/\n        \/*\n        . = 0x000002FC ;\n        PROVIDE(__CRP_WORD_START__ = .) ;\n        KEEP(*(.crp))\n        PROVIDE(__CRP_WORD_END__ = .) ;\n        ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), \"Linker CRP Enabled, but no CRP_WORD provided within application\");\n        *\/\n        \/* End of Code Read Protection *\/\n    } >MFlash16\n\n    .text : ALIGN(4)\n    {\n        *(.text*)\n        *(.rodata .rodata.* .constdata .constdata.*)\n        . = ALIGN(4);\n    } > MFlash16\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this.\n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash16\n    __exidx_start = .;\n\n    .ARM.exidx : ALIGN(4)\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash16\n    __exidx_end = .;\n\n    _etext = .;\n\n    \/* MAIN DATA SECTION *\/\n        \/* Default MTB section *\/\n        .mtb_buffer_default (NOLOAD) :\n        {\n           KEEP(*(.mtb*))\n        } > RamLoc4\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > RamLoc4\n    \/* Main DATA section (RamLoc4) *\/\n    .data : ALIGN(4)\n    {\n       FILL(0xff)\n       _data = . ;\n       *(vtable)\n       *(.ramfunc*)\n       *(.data*)\n       . = ALIGN(4) ;\n       _edata = . ;\n    } > RamLoc4 AT>MFlash16\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n    } > RamLoc4\n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*)\n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > RamLoc4\n\n    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);\n    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc4 - 0);\n\n    \/* Calculate NXP Cortex-M3 valid user code checksum. This is 0-(sum of first 7 entries in vector table),\n     * Note that we must add 1 to each code space vector (LSB = marker for thumb code).\n     *\/\n    PROVIDE(__valid_user_code_checksum = ~(_vStackTop + ResetISR + 1 + NMI_Handler + 1 + HardFault_Handler + 1 ) + 1);\n\n}\n","old_contents":"\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-2013\n * (c) NXP Semiconductors 2013-2017\n * Generated linker script file for LPC812\n * Created from linkscript.ldt by FMCreateLinkLibraries\n * Using Freemarker v2.3.23\n * LPCXpresso v8.2.0 [Build 647] [2016-07-18]  on Apr 17, 2017 11:39:50 AM\n *\/\n\nGROUP (\n  libgcc.a\n  libc.a\n  libm.a\n)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash16 (rx) : ORIGIN = 0x0, LENGTH = 0x4000 \/* 16K bytes (alias Flash) *\/  \n  RamLoc4 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x1000 \/* 4K bytes (alias RAM) *\/  \n}\n\n  \/* Define a symbol for the top of each memory region *\/\n  __base_MFlash16 = 0x0  ; \/* MFlash16 *\/  \n  __base_Flash = 0x0 ; \/* Flash *\/  \n  __top_MFlash16 = 0x0 + 0x4000 ; \/* 16K bytes *\/  \n  __top_Flash = 0x0 + 0x4000 ; \/* 16K bytes *\/  \n  __base_RamLoc4 = 0x10000000  ; \/* RamLoc4 *\/  \n  __base_RAM = 0x10000000 ; \/* RAM *\/  \n  __top_RamLoc4 = 0x10000000 + 0x1000 ; \/* 4K bytes *\/  \n  __top_RAM = 0x10000000 + 0x1000 ; \/* 4K bytes *\/  \n\nENTRY(ResetISR)\n\nSECTIONS\n{\n    \/* MAIN TEXT SECTION *\/\n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        __vectors_start__ = ABSOLUTE(.) ;\n        KEEP(*(.isr_vector))\n        \/* Global Section Table *\/\n        . = ALIGN(4) ; \n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n\t    \/* End of Global Section Table *\/\n\n        *(.after_vectors*)\n\n        \/* Code Read Protection data *\/\n        \/* Disable CRP for now *\/\n        \/*\n        . = 0x000002FC ;\n        PROVIDE(__CRP_WORD_START__ = .) ;\n        KEEP(*(.crp))\n        PROVIDE(__CRP_WORD_END__ = .) ;\n        ASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), \"Linker CRP Enabled, but no CRP_WORD provided within application\");\n        *\/\n        \/* End of Code Read Protection *\/\n    } >MFlash16\n\n    .text : ALIGN(4)    \n    {\n        *(.text*)\n        *(.rodata .rodata.* .constdata .constdata.*)\n        . = ALIGN(4);\n    } > MFlash16\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4) \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash16\n    __exidx_start = .;\n\n    .ARM.exidx : ALIGN(4)\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash16\n    __exidx_end = .;\n\n    _etext = .;\n        \n    \/* MAIN DATA SECTION *\/\n        \/* Default MTB section *\/\n        .mtb_buffer_default (NOLOAD) :\n        {\n           KEEP(*(.mtb*))\n        } > RamLoc4\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > RamLoc4\n    \/* Main DATA section (RamLoc4) *\/\n    .data : ALIGN(4)\n    {\n       FILL(0xff)\n       _data = . ;\n       *(vtable)\n       *(.ramfunc*)\n       *(.data*)\n       . = ALIGN(4) ;\n       _edata = . ;\n    } > RamLoc4 AT>MFlash16\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n    } > RamLoc4\n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > RamLoc4\n\n    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);\n    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc4 - 0);\n\n    \/* ## Create checksum value (used in startup) ## *\/\n    PROVIDE(__valid_user_code_checksum = 0 - \n                                         (_vStackTop \n                                         + (ResetISR + 1) \n                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) \n                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) \n                                         )\n           );\n}","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"acc65b21d77494f639504867b95c15a8dbd6c5be","subject":"Don't move Reset_Handler to top of memory after all.","message":"Don't move Reset_Handler to top of memory after all.\n\nSee https:\/\/github.com\/openxc\/openlpc-USB_Bootloader\/issues\/2\n","repos":"openxc\/vi-firmware,ene-ilies\/vi-firmware,mgiannikouris\/vi-firmware,mgiannikouris\/vi-firmware,openxc\/vi-firmware,openxc\/vi-firmware,openxc\/vi-firmware,mgiannikouris\/vi-firmware,ene-ilies\/vi-firmware,ene-ilies\/vi-firmware,ene-ilies\/vi-firmware,mgiannikouris\/vi-firmware","old_file":"src\/lpc17xx\/LPC17xx-base.ld","new_file":"src\/lpc17xx\/LPC17xx-base.ld","new_contents":"\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        *startup.o\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"9232398ed3954186ae9fd7a6d4c6f132d831f928","subject":"update load script","message":"update load script\n","repos":"openss7\/openss7,openss7\/openss7,openss7\/openss7,openss7\/openss7,openss7\/openss7,openss7\/openss7,openss7\/openss7,openss7\/openss7","old_file":"scripts\/hot.lds","new_file":"scripts\/hot.lds","new_contents":"SECTIONS\n{\n\t\/DISCARD\/\t\t  : { *(.discard)\n\t\t\t\t      *(.discard.*) }\n\n\t.noaltinstructions\t0 : { *(.altinstructions) }\n\n\t.text\t\t\t0 : { *(.text.streams.hot.put)\n\t\t\t\t    *(.text.streams.hot.write)\n\t\t\t\t    *(.text.streams.hot.out)\n\t\t\t\t    *(.text.streams.hot)\n\t\t\t\t    *(.text.streams.hot.in)\n\t\t\t\t    *(.text.streams.hot.read)\n\t\t\t\t    *(.text.streams.hot.get)\n\t\t\t\t    *(.text)\n\t\t\t\t    *(.text.streams.unlikely) }\n\/*\n\t.text.unlikely\t\t0 : { *(.text.streams.unlikely)\t\t*(.text.unlikely)\t}\n *\/\n\t__ksymtab\t\t0 : { *(SORT(___ksymtab+*))\t\t*(__ksymtab)\t\t}\n\t__ksymtab_gpl\t\t0 : { *(SORT(___ksymtab_gpl+*))\t\t*(__ksymtab_gpl)\t}\n\t__ksymtab_unused\t0 : { *(SORT(___ksymtab_unused+*))\t*(__ksymtab_unused)\t}\n\t__ksymtab_unused_gpl\t0 : { *(SORT(___ksymtab_unused_gpl+*))\t*(__ksymtab_unused_gpl)\t}\n\t__ksymtab_gpl_future\t0 : { *(SORT(___ksymtab_gpl_future+*))\t*(__ksymtab_gpl_future)\t}\n\t__kcrctab\t\t0 : { *(SORT(___kcrctab+*))\t\t*(__kcrctab)\t\t}\n\t__kcrctab_gpl\t\t0 : { *(SORT(___kcrctab_gpl+*))\t\t*(__kcrctab_gpl)\t}\n\t__kcrctab_unused\t0 : { *(SORT(___kcrctab_unused+*))\t*(__kcrctab_unused)\t}\n\t__kcrctab_unused_gpl\t0 : { *(SORT(___kcrctab_unused_gpl+*))\t*(__kcrctab_unused_gpl)\t}\n\t__kcrctab_gpl_future\t0 : { *(SORT(___kcrctab_gpl_future+*))\t*(__kcrctab_gpl_future)\t}\n\n\t.init_array\t\t0 : ALIGN(8) { *(SORT(.init_array.*)) *(.init_array) }\n\n\t__jump_table\t\t0 : ALIGN(8) { KEEP(*(__jump_table)) }\n}\n","old_contents":"SECTIONS\n{\n\t\/DISCARD\/\t\t: { *(.discard) }\n\n\t.noaltinstructions\t: { *(.altinstructions) }\n\n\t.text\t\t\t: { *(.text.streams.hot.put)\n\t\t\t\t    *(.text.streams.hot.write)\n\t\t\t\t    *(.text.streams.hot.out)\n\t\t\t\t    *(.text.streams.hot)\n\t\t\t\t    *(.text.streams.hot.in)\n\t\t\t\t    *(.text.streams.hot.read)\n\t\t\t\t    *(.text.streams.hot.get)\n\t\t\t\t    *(.text)\n\t\t\t\t    *(.text.streams.unlikely) }\n\/*\n\t.text.unlikely\t\t: { *(.text.streams.unlikely)\t\t*(.text.unlikely)\t}\n *\/\n\t__ksymtab\t\t: { *(SORT(___ksymtab+*))\t\t*(__ksymtab)\t\t}\n\t__ksymtab_gpl\t\t: { *(SORT(___ksymtab_gpl+*))\t\t*(__ksymtab_gpl)\t}\n\t__ksymtab_unused\t: { *(SORT(___ksymtab_unused+*))\t*(__ksymtab_unused)\t}\n\t__ksymtab_unused_gpl\t: { *(SORT(___ksymtab_unused_gpl+*))\t*(__ksymtab_unused_gpl)\t}\n\t__ksymtab_gpl_future\t: { *(SORT(___ksymtab_gpl_future+*))\t*(__ksymtab_gpl_future)\t}\n\t__kcrctab\t\t: { *(SORT(___kcrctab+*))\t\t*(__kcrctab)\t\t}\n\t__kcrctab_gpl\t\t: { *(SORT(___kcrctab_gpl+*))\t\t*(__kcrctab_gpl)\t}\n\t__kcrctab_unused\t: { *(SORT(___kcrctab_unused+*))\t*(__kcrctab_unused)\t}\n\t__kcrctab_unused_gpl\t: { *(SORT(___kcrctab_unused_gpl+*))\t*(__kcrctab_unused_gpl)\t}\n\t__kcrctab_gpl_future\t: { *(SORT(___kcrctab_gpl_future+*))\t*(__kcrctab_gpl_future)\t}\n}\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"77a7615eb28e13ba43859ba54abba7e4be2a5ae2","subject":"linker: update posix linker template, linker.ld","message":"linker: update posix linker template, linker.ld\n\nThe function `zephyr_linker_sources()` states:\n> When placing into NOINIT, RWDATA, RODATA, ROM_START, the contents of\n> the files will be placed inside an output section, so assume the\n> section definition is already present.\n\nHowever, in the posix linker.ld template the NOINIT, RWDATA, RODATA, and\nROM_START was not placed inside a pre-defined output section, which\nmeans that linker scripts created for native_posix when\n`zephyr_linker_sources()` is used are invalid\n\nThis result in the following failure:\n> \/usr\/bin\/ld:zephyr\/linker_zephyr_prebuilt.cmd:81: syntax error\n> collect2: error: ld returned 1 exit status\n\nThis PR fixes this issue be predefining output sections according to\nthe documented behavior.\n\nSigned-off-by: Torsten Rasmussen <a7c5b1d5a1f41fce6edfa3f7c2392ae0c59deafe@nordicsemi.no>\n","repos":"zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr","old_file":"include\/arch\/posix\/linker.ld","new_file":"include\/arch\/posix\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n * Copyright (c) 2017 Oticon A\/S\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the POSIX (native) platform\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\nSECTIONS\n {\n\nSECTION_PROLOGUE(rom_start,,)\n{\n\t\/* Located in generated directory. This file is populated by the\n\t * zephyr_linker_sources() Cmake function.\n\t *\/\n\t#include <snippets-rom-start.ld>\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\nSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n{\n\t\/* Located in generated directory. This file is populated by the\n\t * zephyr_linker_sources() Cmake function.\n\t *\/\n\t#include <snippets-rodata.ld>\n} GROUP_LINK_IN(ROMABLE_REGION)\n\nSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n{\n\t\/* Located in generated directory. This file is populated by the\n\t * zephyr_linker_sources() Cmake function.\n\t *\/\n\t#include <snippets-rwdata.ld>\n} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#include <arch\/posix\/native_tasks.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n__data_region_end = .;\n\nSECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME,,)\n{\n\t\/* Located in generated directory. This file is populated by the\n\t * zephyr_linker_sources() Cmake function.\n\t *\/\n\t#include <snippets-noinit.ld>\n} GROUP_LINK_IN(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n } INSERT AFTER .data;\n\n\/*\n * Note that the INSERT command actually changes the meaning of the -T command\n * line switch: The script will now augment the default SECTIONS instead of\n * replacing it.\n *\/\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n * Copyright (c) 2017 Oticon A\/S\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the POSIX (native) platform\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\nSECTIONS\n {\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rom-start.ld>\n\n#include <linker\/common-rom.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#include <linker\/common-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#include <arch\/posix\/native_tasks.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n__data_region_end = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n } INSERT AFTER .data;\n\n\/*\n * Note that the INSERT command actually changes the meaning of the -T command\n * line switch: The script will now augment the default SECTIONS instead of\n * replacing it.\n *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"085eb3f40cc5b4dd690d325ad948860f427ee3ec","subject":"cpu\/esp32: place common CPU functions to IRAM","message":"cpu\/esp32: place common CPU functions to IRAM\n\n","repos":"kaspar030\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,miri64\/RIOT,ant9000\/RIOT,basilfx\/RIOT,basilfx\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,yogo1212\/RIOT,RIOT-OS\/RIOT,smlng\/RIOT,kYc0o\/RIOT,authmillenon\/RIOT,miri64\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,smlng\/RIOT,smlng\/RIOT,authmillenon\/RIOT,authmillenon\/RIOT,basilfx\/RIOT,OTAkeys\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,miri64\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,RIOT-OS\/RIOT,basilfx\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,jasonatran\/RIOT,smlng\/RIOT,OTAkeys\/RIOT,yogo1212\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,smlng\/RIOT,authmillenon\/RIOT,OlegHahm\/RIOT","old_file":"cpu\/esp32\/ld\/esp32.common.ld","new_file":"cpu\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *littlefs.a:*(.literal .text .literal.* .text.*)\n    *littlefs2.a:*(.literal .text .literal.* .text.*)\n    *newlib_syscalls_default.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *syscalls.o(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *esp_common.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *littlefs.a:*(.literal .text .literal.* .text.*)\n    *littlefs2.a:*(.literal .text .literal.* .text.*)\n    *newlib_syscalls_default.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *syscalls.o(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"09cc2424f9fe1a1710f62646aa62cac4e68af788","subject":"Fix bug in link.ld","message":"Fix bug in link.ld\n","repos":"alanbrady\/rawros","old_file":"link.ld","new_file":"link.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\")\nENTRY(loader)\n\nSECTIONS {\n    . = 0x00100000;\n\n    .multiboot : AT(ADDR(.multiboot))\n    {\n        *(.multiboot)\n    }\n\n    .text ALIGN(0x1000) : AT(ADDR(.text))\n    {\n        *(.text)\n        *(.rodata*)\n    }\n\n    .data ALIGN (0x1000) : AT(ADDR(.data))\n    {\n        *(.data)\n    }\n\n    .bss ALIGN (0x1000) : AT(ADDR(.bss))\n    {\n        *(COMMON)\n        *(.bss)\n    }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\")\nENTRY(loader)\n\nSECTIONS {\n    . = 0x00100000;\n\n    .multiboot : AT(ADDR(.multiboot))\n    {\n        *(.multiboot)\n    }\n\n    .text ALIGN(0x1000) : AT(ADDR(.text))\n    {\n        *(.text)\n        *(.rodata)\n    }\n\n    .data ALIGN (0x1000) : AT(ADDR(.data))\n    {\n        *(.data)\n    }\n\n    .bss ALIGN (0x1000) : AT(ADDR(.bss))\n    {\n        *(COMMON)\n        *(.bss)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b51eeb03f4a3c2b6ece78d2c79d336c90587f4cf","subject":"posix: linker: Wrap rodata and rwdata in sections.","message":"posix: linker: Wrap rodata and rwdata in sections.\n\n* zephyr_linker_sources states that RODATA and RWDATA\n  included will be wrapped in an outer section, so\n  add these sections for the posix arch too.\n\nSigned-off-by: Pete Johanson <4b8373d016f277527198385ba72fda0feb5da015@peterjohanson.com>\n","repos":"nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr","old_file":"include\/arch\/posix\/linker.ld","new_file":"include\/arch\/posix\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n * Copyright (c) 2017 Oticon A\/S\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the POSIX (native) platform\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\nSECTIONS\n {\n\n\tSECTION_PROLOGUE(romstart_snippet,,)\n\t{\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rom-start.ld>\n\t}\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(rodata_snippet,,)\n\t{\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\t}\n} INSERT AFTER .rodata;\n\nSECTIONS\n  {\n\n\tSECTION_DATA_PROLOGUE(data_snippet,,)\n\t{\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t}\n\n#include <linker\/common-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#include <arch\/posix\/native_tasks.ld>\n\n\tSECTION_DATA_PROLOGUE(noinit_snippet,,)\n\t{\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\t}\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n } INSERT AFTER .data;\n\n\/*\n * Note that the INSERT command actually changes the meaning of the -T command\n * line switch: The script will now augment the default SECTIONS instead of\n * replacing it.\n *\/\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n * Copyright (c) 2017 Oticon A\/S\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the POSIX (native) platform\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\nSECTIONS\n {\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rom-start.ld>\n\n#include <linker\/common-rom.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#include <linker\/common-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#include <arch\/posix\/native_tasks.ld>\n\n __data_ram_end = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n } INSERT AFTER .data;\n\n\/*\n * Note that the INSERT command actually changes the meaning of the -T command\n * line switch: The script will now augment the default SECTIONS instead of\n * replacing it.\n *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"811d97c32022cb7a73e01550076646928b824617","subject":"unified\/arm: Fix data start address for XIP images","message":"unified\/arm: Fix data start address for XIP images\n\nFor XIP images, in order to avoid the situation when\n__data_rom_start is 32-bit aligned, but the actual data is placed\nafter rodata section, which may not end exactly at 32-bit border,\npad rodata section, so __data_rom_start points at data and it is\n32-bit aligned.\n\nOn non-XIP images this may enlarge image size up to 3 bytes.\nThis is generally not an issue, since modern ROM and FLASH\nmemory is usually 4k aligned.\n\nChange-Id: I3d37fccbc610615585d776144ab9e281368258d6\nSigned-off-by: Dmitriy Korovkin <236c6d6726c42916ff3b3577f1e4a2ded1fbf8fe@windriver.com>\n","repos":"rsalveti\/zephyr,pklazy\/zephyr,punitvara\/zephyr,pklazy\/zephyr,kraj\/zephyr,kraj\/zephyr,nashif\/zephyr,punitvara\/zephyr,rsalveti\/zephyr,explora26\/zephyr,galak\/zephyr,pklazy\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,runchip\/zephyr-cc3220,ldts\/zephyr,tidyjiang8\/zephyr-doc,fractalclone\/zephyr-riscv,mbolivar\/zephyr,fbsder\/zephyr,bboozzoo\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,rsalveti\/zephyr,pklazy\/zephyr,kraj\/zephyr,holtmann\/zephyr,sharronliu\/zephyr,bigdinotech\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,bigdinotech\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,fractalclone\/zephyr-riscv,tidyjiang8\/zephyr-doc,explora26\/zephyr,bigdinotech\/zephyr,fbsder\/zephyr,nashif\/zephyr,explora26\/zephyr,Vudentz\/zephyr,sharronliu\/zephyr,erwango\/zephyr,runchip\/zephyr-cc3220,holtmann\/zephyr,runchip\/zephyr-cc3200,punitvara\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyriot\/zephyr,mbolivar\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3220,aceofall\/zephyr-iotos,aceofall\/zephyr-iotos,runchip\/zephyr-cc3200,sharronliu\/zephyr,runchip\/zephyr-cc3220,fbsder\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,erwango\/zephyr,zephyriot\/zephyr,tidyjiang8\/zephyr-doc,runchip\/zephyr-cc3220,holtmann\/zephyr,Vudentz\/zephyr,ldts\/zephyr,zephyriot\/zephyr,aceofall\/zephyr-iotos,erwango\/zephyr,bigdinotech\/zephyr,bboozzoo\/zephyr,bboozzoo\/zephyr,rsalveti\/zephyr,explora26\/zephyr,finikorg\/zephyr,finikorg\/zephyr,kraj\/zephyr,mbolivar\/zephyr,ldts\/zephyr,pklazy\/zephyr,aceofall\/zephyr-iotos,fbsder\/zephyr,zephyrproject-rtos\/zephyr,fbsder\/zephyr,nashif\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,tidyjiang8\/zephyr-doc,bboozzoo\/zephyr,GiulianoFranchetto\/zephyr,holtmann\/zephyr,runchip\/zephyr-cc3200,GiulianoFranchetto\/zephyr,galak\/zephyr,aceofall\/zephyr-iotos,Vudentz\/zephyr,bboozzoo\/zephyr,bigdinotech\/zephyr,kraj\/zephyr,ldts\/zephyr,holtmann\/zephyr,fractalclone\/zephyr-riscv,tidyjiang8\/zephyr-doc,finikorg\/zephyr,fractalclone\/zephyr-riscv,mbolivar\/zephyr,erwango\/zephyr,sharronliu\/zephyr,explora26\/zephyr,runchip\/zephyr-cc3200,galak\/zephyr,zephyriot\/zephyr,ldts\/zephyr,punitvara\/zephyr,galak\/zephyr,erwango\/zephyr,runchip\/zephyr-cc3200,fractalclone\/zephyr-riscv,rsalveti\/zephyr,mbolivar\/zephyr,sharronliu\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_SECURITY_FRDM_K64F)\n  #define SKIP_TO_SECURITY_FRDM_K64F\n#endif\n\n#define ROM_ADDR CONFIG_FLASH_BASE_ADDRESS\n#define ROM_SIZE CONFIG_FLASH_SIZE*1K\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE CONFIG_SRAM_SIZE * 1K\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    SYSTEM_CONTROL_SPACE  (wx) : ORIGIN = 0xE000E000,  LENGTH = 4K\n    SYSTEM_CONTROL_PERIPH (wx) : ORIGIN = 0x400FE000,  LENGTH = 4K\n    }\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = CONFIG_FLASH_BASE_ADDRESS;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n#if defined(CONFIG_GDB_INFO) && !defined(CONFIG_SW_ISR_TABLE)\n\tKEEP(*(.gdb_stub_irq_vector_table))\n\tKEEP(*(\".gdb_stub_irq_vector_table.*\"))\n#endif\n\n\tKEEP(*(.irq_vector_table))\n\tKEEP(*(\".irq_vector_table.*\"))\n\n\t\/* FRDM_K64F has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_SECURITY_FRDM_K64F\n\tKEEP(*(.security_frdm_k64f))\n\tKEEP(*(\".security_frdm_k64f.*\"))\n\n\tKEEP(*(.isr_irq*))\n\n\t\/* sections for IRQ0-9 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9])))\n\n\t\/* sections for IRQ10-99 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9])))\n\n\t\/* sections for IRQ100-999 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))\n\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE (devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\/*\n\t * The compiler fills the constructor pointers table below, hence symbol\n\t * __CTOR_LIST__ must be aligned on 4 byte boundary.\n\t * To align with the C++ standard, the first elment of the array\n\t * contains the number of actual constructors. The last element is\n\t * NULL.\n\t *\/\n\t. = ALIGN(4);\n\t__CTOR_LIST__ = .;\n\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\tLONG(0)\n\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t. = ALIGN(4);\n\t__init_array_start = .;\n\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n    __data_rom_start = .;    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE (initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE (_k_task_list, (OPTIONAL),)\n\t{\n\t\t_k_task_list_start = .;\n\t\t\t*(._k_task_list.public.*)\n\t\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE (_k_task_ptr, (OPTIONAL),)\n\t{\n\t\t_k_task_ptr_start = .;\n\t\t\t*(._k_task_ptr.public.*)\n\t\t\t*(._k_task_ptr.private.*)\n\t\t\t*(._k_task_ptr.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n\t\t_k_task_ptr_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE (_k_pipe_ptr, (OPTIONAL),)\n\t{\n\t\t_k_pipe_ptr_start = .;\n\t\t\t*(._k_pipe_ptr.public.*)\n\t\t\t*(._k_pipe_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n\t\t_k_pipe_ptr_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE (_k_mem_map_ptr, (OPTIONAL),)\n\t{\n\t\t_k_mem_map_ptr_start = .;\n\t\t\t*(._k_mem_map_ptr.public.*)\n\t\t\t*(._k_mem_map_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n\t\t_k_mem_map_ptr_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_event_list, (OPTIONAL),)\n\t{\n\t\t_k_event_list_start = .;\n\t\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_memory_pool, (OPTIONAL),)\n\t{\n\t\t*(._k_memory_pool.struct*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\n\t\t_k_mem_pool_start = .;\n\t\t*(._k_memory_pool.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool*\")))\n\t\t_k_mem_pool_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\tCOMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n\n\t_image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n    GROUP_START(SYSTEM_CONTROL_PERIPH)\n    SECTION_PROLOGUE(.scp,(NOLOAD),)\n\t{\n\t\/*\n\t * The leading '.' in the \".scp\" section name indicates that section is\n\t * mapped to neither a normal ROM nor a normal RAM area.\n\t *\/\n\n\t*(.scp)\n\t*(\".scp.*\")\n\t } GROUP_LINK_IN(SYSTEM_CONTROL_PERIPH)\n    GROUP_END(SYSTEM_CONTROL_PERIPH)\n\n    GROUP_START(SYSTEM_CONTROL_SPACE)\n    SECTION_PROLOGUE(.scs,(NOLOAD),)\n\t{\n\t\/*\n\t * The leading '.' in the \".scs\" section name indicates that section is\n\t * mapped to neither normal ROM nor normal RAM space.\n\t *\/\n\n\t*(.scs)\n\t*(\".scs.*\")\n\t } GROUP_LINK_IN(SYSTEM_CONTROL_SPACE)\n    GROUP_END(SYSTEM_CONTROL_SPACE)\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_SECURITY_FRDM_K64F)\n  #define SKIP_TO_SECURITY_FRDM_K64F\n#endif\n\n#define ROM_ADDR CONFIG_FLASH_BASE_ADDRESS\n#define ROM_SIZE CONFIG_FLASH_SIZE*1K\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE CONFIG_SRAM_SIZE * 1K\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    SYSTEM_CONTROL_SPACE  (wx) : ORIGIN = 0xE000E000,  LENGTH = 4K\n    SYSTEM_CONTROL_PERIPH (wx) : ORIGIN = 0x400FE000,  LENGTH = 4K\n    }\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = CONFIG_FLASH_BASE_ADDRESS;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n#if defined(CONFIG_GDB_INFO) && !defined(CONFIG_SW_ISR_TABLE)\n\tKEEP(*(.gdb_stub_irq_vector_table))\n\tKEEP(*(\".gdb_stub_irq_vector_table.*\"))\n#endif\n\n\tKEEP(*(.irq_vector_table))\n\tKEEP(*(\".irq_vector_table.*\"))\n\n\t\/* FRDM_K64F has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_SECURITY_FRDM_K64F\n\tKEEP(*(.security_frdm_k64f))\n\tKEEP(*(\".security_frdm_k64f.*\"))\n\n\tKEEP(*(.isr_irq*))\n\n\t\/* sections for IRQ0-9 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9])))\n\n\t\/* sections for IRQ10-99 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9])))\n\n\t\/* sections for IRQ100-999 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))\n\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE (devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\/*\n\t * The compiler fills the constructor pointers table below, hence symbol\n\t * __CTOR_LIST__ must be aligned on 4 byte boundary.\n\t * To align with the C++ standard, the first elment of the array\n\t * contains the number of actual constructors. The last element is\n\t * NULL.\n\t *\/\n\t. = ALIGN(4);\n\t__CTOR_LIST__ = .;\n\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\tLONG(0)\n\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t. = ALIGN(4);\n\t__init_array_start = .;\n\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE (initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE (_k_task_list, (OPTIONAL),)\n\t{\n\t\t_k_task_list_start = .;\n\t\t\t*(._k_task_list.public.*)\n\t\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE (_k_task_ptr, (OPTIONAL),)\n\t{\n\t\t_k_task_ptr_start = .;\n\t\t\t*(._k_task_ptr.public.*)\n\t\t\t*(._k_task_ptr.private.*)\n\t\t\t*(._k_task_ptr.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n\t\t_k_task_ptr_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE (_k_pipe_ptr, (OPTIONAL),)\n\t{\n\t\t_k_pipe_ptr_start = .;\n\t\t\t*(._k_pipe_ptr.public.*)\n\t\t\t*(._k_pipe_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n\t\t_k_pipe_ptr_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE (_k_mem_map_ptr, (OPTIONAL),)\n\t{\n\t\t_k_mem_map_ptr_start = .;\n\t\t\t*(._k_mem_map_ptr.public.*)\n\t\t\t*(._k_mem_map_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n\t\t_k_mem_map_ptr_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_event_list, (OPTIONAL),)\n\t{\n\t\t_k_event_list_start = .;\n\t\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_memory_pool, (OPTIONAL),)\n\t{\n\t\t*(._k_memory_pool.struct*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\n\t\t_k_mem_pool_start = .;\n\t\t*(._k_memory_pool.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool*\")))\n\t\t_k_mem_pool_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\tCOMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n\n\t_image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n    GROUP_START(SYSTEM_CONTROL_PERIPH)\n    SECTION_PROLOGUE(.scp,(NOLOAD),)\n\t{\n\t\/*\n\t * The leading '.' in the \".scp\" section name indicates that section is\n\t * mapped to neither a normal ROM nor a normal RAM area.\n\t *\/\n\n\t*(.scp)\n\t*(\".scp.*\")\n\t } GROUP_LINK_IN(SYSTEM_CONTROL_PERIPH)\n    GROUP_END(SYSTEM_CONTROL_PERIPH)\n\n    GROUP_START(SYSTEM_CONTROL_SPACE)\n    SECTION_PROLOGUE(.scs,(NOLOAD),)\n\t{\n\t\/*\n\t * The leading '.' in the \".scs\" section name indicates that section is\n\t * mapped to neither normal ROM nor normal RAM space.\n\t *\/\n\n\t*(.scs)\n\t*(\".scs.*\")\n\t } GROUP_LINK_IN(SYSTEM_CONTROL_SPACE)\n    GROUP_END(SYSTEM_CONTROL_SPACE)\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9a2cf203b1ee3e8a905d019be66eea34bc712d5e","subject":"Fix docs, evernote \u2192 exporter (#8158)","message":"Fix docs, evernote \u2192 exporter (#8158)\n\nCf. https:\/\/github.com\/koreader\/koreader\/pull\/7983#issuecomment-908981240","repos":"poire-z\/koreader,koreader\/koreader,Frenzie\/koreader,poire-z\/koreader,Frenzie\/koreader,koreader\/koreader,NiLuJe\/koreader,NiLuJe\/koreader","old_file":"doc\/config.ld","new_file":"doc\/config.ld","new_contents":"project = 'KOReader'\ndescription = 'Multi-platform ebook reader'\nfull_description = 'An ebook reader application supports PDF, DJVU, EPUB, FB2 and many more formats, running on Kindle, Kobo, PocketBook, Ubuntu Touch and Android devices.'\ntitle = 'KOReader Documentation'\ndir = 'html'\nstyle = '!fixed'\nuse_markdown_titles = true\ntopics = {\n    '..\/README.md',\n    '.\/Collaborating_with_Git.md',\n    '.\/DataStore.md',\n    '.\/Development_guide.md',\n    '.\/Events.md',\n    '.\/Hacking.md',\n    '.\/Porting.md',\n    '.\/Unit_tests.md',\n}\npackage = ''\nformat = 'markdown'\nsort_modules = true\nfile = {\n    '..\/frontend',\n    '..\/plugins',\n    '..\/base\/ffi',\n    '..\/platform\/android\/luajit-launcher\/assets',\n    exclude = {'..\/base\/ffi\/sha2.lua',\n        '..\/base\/ffi\/qrencode.lua',\n        '..\/plugins\/exporter.koplugin\/slt2.lua',\n        '..\/plugins\/newsdownloader.koplugin\/lib\/handler.lua',\n        '..\/plugins\/newsdownloader.koplugin\/lib\/xml.lua',\n    },\n}\n","old_contents":"project = 'KOReader'\ndescription = 'Multi-platform ebook reader'\nfull_description = 'An ebook reader application supports PDF, DJVU, EPUB, FB2 and many more formats, running on Kindle, Kobo, PocketBook, Ubuntu Touch and Android devices.'\ntitle = 'KOReader Documentation'\ndir = 'html'\nstyle = '!fixed'\nuse_markdown_titles = true\ntopics = {\n    '..\/README.md',\n    '.\/Collaborating_with_Git.md',\n    '.\/DataStore.md',\n    '.\/Development_guide.md',\n    '.\/Events.md',\n    '.\/Hacking.md',\n    '.\/Porting.md',\n    '.\/Unit_tests.md',\n}\npackage = ''\nformat = 'markdown'\nsort_modules = true\nfile = {\n    '..\/frontend',\n    '..\/plugins',\n    '..\/base\/ffi',\n    '..\/platform\/android\/luajit-launcher\/assets',\n    exclude = {'..\/base\/ffi\/sha2.lua',\n        '..\/base\/ffi\/qrencode.lua',\n        '..\/plugins\/evernote.koplugin\/slt2.lua',\n        '..\/plugins\/newsdownloader.koplugin\/lib\/handler.lua',\n        '..\/plugins\/newsdownloader.koplugin\/lib\/xml.lua',\n    },\n}\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"1a1f9b0c9db567e0699ca121c24066a21e270315","subject":"nrf5: updating flash size comment in nrf52832 linker script.","message":"nrf5: updating flash size comment in nrf52832 linker script.\n","repos":"tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,tralamazza\/micropython,adafruit\/micropython,tralamazza\/micropython,adafruit\/micropython,adafruit\/circuitpython","old_file":"nrf5\/boards\/nrf52832_aa.ld","new_file":"nrf5\/boards\/nrf52832_aa.ld","new_contents":"\/*\n    GNU linker script for NRF52 blank w\/ no SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x07F000 \/* 508 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x010000 \/* 64 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20005000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52 blank w\/ no SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x07F000 \/* 508 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x010000 \/* 64 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20005000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"df20ab8b90a2def2b7d16724058776760973b5b9","subject":"net: Renaming net_l2_init sections to net_l2","message":"net: Renaming net_l2_init sections to net_l2\n\nnet_l2 is the proper name, looked by sanitycheck.\n\nChange-Id: I08548865df21a57c8198fe0a801aa8c2a81b7fb0\nSigned-off-by: Tomasz Bursztyka <ba81a3a719836727e6857ae83462b9f52ec41006@linux.intel.com>\n","repos":"finikorg\/zephyr,nashif\/zephyr,ldts\/zephyr,holtmann\/zephyr,bigdinotech\/zephyr,punitvara\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3200,zephyriot\/zephyr,nashif\/zephyr,explora26\/zephyr,pklazy\/zephyr,punitvara\/zephyr,galak\/zephyr,mbolivar\/zephyr,holtmann\/zephyr,fractalclone\/zephyr-riscv,finikorg\/zephyr,fractalclone\/zephyr-riscv,aceofall\/zephyr-iotos,tidyjiang8\/zephyr-doc,zephyrproject-rtos\/zephyr,pklazy\/zephyr,zephyrproject-rtos\/zephyr,rsalveti\/zephyr,sharronliu\/zephyr,GiulianoFranchetto\/zephyr,fractalclone\/zephyr-riscv,bigdinotech\/zephyr,Vudentz\/zephyr,erwango\/zephyr,explora26\/zephyr,runchip\/zephyr-cc3220,zephyriot\/zephyr,bboozzoo\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,rsalveti\/zephyr,fbsder\/zephyr,Vudentz\/zephyr,kraj\/zephyr,tidyjiang8\/zephyr-doc,pklazy\/zephyr,sharronliu\/zephyr,erwango\/zephyr,mbolivar\/zephyr,tidyjiang8\/zephyr-doc,runchip\/zephyr-cc3220,zephyrproject-rtos\/zephyr,galak\/zephyr,kraj\/zephyr,punitvara\/zephyr,nashif\/zephyr,mbolivar\/zephyr,tidyjiang8\/zephyr-doc,erwango\/zephyr,Vudentz\/zephyr,runchip\/zephyr-cc3200,fractalclone\/zephyr-riscv,nashif\/zephyr,explora26\/zephyr,rsalveti\/zephyr,finikorg\/zephyr,aceofall\/zephyr-iotos,nashif\/zephyr,holtmann\/zephyr,fractalclone\/zephyr-riscv,rsalveti\/zephyr,tidyjiang8\/zephyr-doc,zephyrproject-rtos\/zephyr,bigdinotech\/zephyr,mbolivar\/zephyr,runchip\/zephyr-cc3220,erwango\/zephyr,pklazy\/zephyr,fbsder\/zephyr,explora26\/zephyr,runchip\/zephyr-cc3220,holtmann\/zephyr,ldts\/zephyr,sharronliu\/zephyr,bigdinotech\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,bboozzoo\/zephyr,fbsder\/zephyr,GiulianoFranchetto\/zephyr,sharronliu\/zephyr,GiulianoFranchetto\/zephyr,mbolivar\/zephyr,ldts\/zephyr,finikorg\/zephyr,galak\/zephyr,punitvara\/zephyr,aceofall\/zephyr-iotos,rsalveti\/zephyr,runchip\/zephyr-cc3200,erwango\/zephyr,galak\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3200,pklazy\/zephyr,bboozzoo\/zephyr,runchip\/zephyr-cc3200,fbsder\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,zephyriot\/zephyr,zephyriot\/zephyr,kraj\/zephyr,runchip\/zephyr-cc3220,Vudentz\/zephyr,Vudentz\/zephyr,bboozzoo\/zephyr,bboozzoo\/zephyr,aceofall\/zephyr-iotos,kraj\/zephyr,bigdinotech\/zephyr,kraj\/zephyr,sharronliu\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,aceofall\/zephyr-iotos,holtmann\/zephyr","old_file":"include\/linker\/common-rom.ld","new_file":"include\/linker\/common-rom.ld","new_contents":"#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on 4 byte\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE (devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(net_l2, (OPTIONAL),)\n\t{\n\t\t__net_l2_start = .;\n\t\t*(\".net_l2.init\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.init*\")))\n\t\t__net_l2_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n","old_contents":"#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on 4 byte\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE (devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(net_l2, (OPTIONAL),)\n\t{\n\t\t__net_l2_start = .;\n\t\t*(\".net_l2.init\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.init*\")))\n\t\t__net_l2_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(net_l2_init, (OPTIONAL),)\n\t{\n\t\t__net_l2_start = .;\n\t\t*(\".net_l2.init\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.init*\")))\n\t\t__net_l2_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bbbc9b132b4a913e1d9fa058d3951b6027d30f31","subject":"nios2: Fix C++ exception handling info linking","message":"nios2: Fix C++ exception handling info linking\n\nThe NIOS2 architecture linker script was including `cplusplus-ram.ld`\nlinker script after `__data_ram_end`, and this caused the content of\n`.gcc_except_table` section to be not copied to the RAM by the\n`z_data_copy` function; leading to the C++ exception handling\nmalfunction.\n\nThis commit relocates the `cplusplus-ram.ld` linker script inclusion\nsuch that the contents of the relevant sections are properly copied by\nthe `z_data_copy` function.\n\nSigned-off-by: Stephanos Ioannidis <dc76e9f0c0006e8f919e0c515c66dbba3982f785@stephanos.io>\n","repos":"finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/nios2\/linker.ld","new_file":"include\/arch\/nios2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specific linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to\n     * 'nios2-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n        {\n        *(.plt)\n        }\n\n    SECTION_PROLOGUE(.iplt,,)\n        {\n        *(.iplt)\n        }\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n#ifndef CONFIG_XIP\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined(CONFIG_GP_ALL_DATA)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        . = ALIGN(4);\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n        . = ALIGN(4);\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_DATA_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n\n#include <linker\/common-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n        *(.data)\n        *(\".data.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        \/* the Nios2 architecture only has 16-bit signed immediate offsets in\n         * the instructions, so accessing a general address requires typically\n         * three instructions - basically, two for the two halves of the 32-bit\n         * address, and one to merge them - but if we can put the most commonly\n         * accessed globals in a special 64K span of memory addressed by the GP\n         * register, then we can access those values in a single instruction,\n         * saving both codespace and runtime.\n         *\n         * Since these immediate offsets are signed, place gp 0x8000 past the\n         * beginning of .sdata so that we can use both positive and negative\n         * offsets.\n         *\/\n#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n        *(.sdata .sdata.* .gnu.linkonce.s.*)\n        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.sbss)\n        *(\".sbss.*\")\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specific linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to\n     * 'nios2-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n        {\n        *(.plt)\n        }\n\n    SECTION_PROLOGUE(.iplt,,)\n        {\n        *(.iplt)\n        }\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n#ifndef CONFIG_XIP\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined(CONFIG_GP_ALL_DATA)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        . = ALIGN(4);\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n        . = ALIGN(4);\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_DATA_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n\n#include <linker\/common-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n        *(.data)\n        *(\".data.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        \/* the Nios2 architecture only has 16-bit signed immediate offsets in\n         * the instructions, so accessing a general address requires typically\n         * three instructions - basically, two for the two halves of the 32-bit\n         * address, and one to merge them - but if we can put the most commonly\n         * accessed globals in a special 64K span of memory addressed by the GP\n         * register, then we can access those values in a single instruction,\n         * saving both codespace and runtime.\n         *\n         * Since these immediate offsets are signed, place gp 0x8000 past the\n         * beginning of .sdata so that we can use both positive and negative\n         * offsets.\n         *\/\n#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n        *(.sdata .sdata.* .gnu.linkonce.s.*)\n        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_ram_end = .;\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.sbss)\n        *(\".sbss.*\")\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"97cbeec749f46733042632d226efd8dd1931f3f3","subject":"Place the GDT and IDT in a good place. (Really not neccessary, but I thought it would be nice to have them on a page-aligned address)","message":"Place the GDT and IDT in a good place. (Really not neccessary, but I thought\nit would be nice to have them on a page-aligned address)\n\n\ngit-svn-id: 0e1153e6534495dc57987e8ae99aae841c146be6@211 1f819a86-672b-0410-b5ed-9de735de380c\n","repos":"chaos4ever\/stormG3,chaos4ever\/stormG3,chaos4ever\/stormG3,chaos4ever\/stormG3","old_file":"stormG3\/source\/ia32\/kernel.ld","new_file":"stormG3\/source\/ia32\/kernel.ld","new_contents":"\/* $chaos: kernel.ld,v 1.2 2002\/06\/05 18:17:26 per Exp $ *\/\n\/* Abstract: storm linker script. Heavily based on the elf_i386.xbn\n   from GNU binutils. *\/\n\/* Author: Per Lundberg <per@chaosdev.org> *\/\n\n\/* Copyright 2002 chaos development. *\/\n\/* Use freely under the terms listed in the file COPYING.\n   reference documentation. *\/\n\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\",\n\t      \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\/lib); SEARCH_DIR(\/usr\/lib); SEARCH_DIR(\/usr\/local\/lib); SEARCH_DIR(\/usr\/i386-linux\/lib);\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  . = 0x100000 + SIZEOF_HEADERS;\n  .interp     : { *(.interp) \t}\n  .hash          : { *(.hash)\t\t}\n  .dynsym        : { *(.dynsym)\t\t}\n  .dynstr        : { *(.dynstr)\t\t}\n  .gnu.version   : { *(.gnu.version)\t}\n  .gnu.version_d   : { *(.gnu.version_d)\t}\n  .gnu.version_r   : { *(.gnu.version_r)\t}\n  .rel.init      : { *(.rel.init)\t}\n  .rela.init     : { *(.rela.init)\t}\n  .rel.text      :\n    {\n      *(.rel.text)\n      *(.rel.text.*)\n      *(.rel.gnu.linkonce.t.*)\n    }\n  .rela.text     :\n    {\n      *(.rela.text)\n      *(.rela.text.*)\n      *(.rela.gnu.linkonce.t.*)\n    }\n  .rel.fini      : { *(.rel.fini)\t}\n  .rela.fini     : { *(.rela.fini)\t}\n  .rel.rodata    :\n    {\n      *(.rel.rodata)\n      *(.rel.rodata.*)\n      *(.rel.gnu.linkonce.r.*)\n    }\n  .rela.rodata   :\n    {\n      *(.rela.rodata)\n      *(.rela.rodata.*)\n      *(.rela.gnu.linkonce.r.*)\n    }\n  .rel.data      :\n    {\n      *(.rel.data)\n      *(.rel.data.*)\n      *(.rel.gnu.linkonce.d.*)\n    }\n  .rela.data     :\n    {\n      *(.rela.data)\n      *(.rela.data.*)\n      *(.rela.gnu.linkonce.d.*)\n    }\n  .rel.ctors     : { *(.rel.ctors)\t}\n  .rela.ctors    : { *(.rela.ctors)\t}\n  .rel.dtors     : { *(.rel.dtors)\t}\n  .rela.dtors    : { *(.rela.dtors)\t}\n  .rel.got       : { *(.rel.got)\t\t}\n  .rela.got      : { *(.rela.got)\t\t}\n  .rel.sdata     :\n    {\n      *(.rel.sdata)\n      *(.rel.sdata.*)\n      *(.rel.gnu.linkonce.s.*)\n    }\n  .rela.sdata     :\n    {\n      *(.rela.sdata)\n      *(.rela.sdata.*)\n      *(.rela.gnu.linkonce.s.*)\n    }\n  .rel.sbss      :\n    { \n      *(.rel.sbss)\n      *(.rel.sbss.*)\n      *(.rel.gnu.linkonce.sb.*)\n    }\n  .rela.sbss     :\n    {\n      *(.rela.sbss)\n      *(.rela.sbss.*)\n      *(.rel.gnu.linkonce.sb.*)\n    }\n  .rel.sdata2    : \n    { \n      *(.rel.sdata2)\n      *(.rel.sdata2.*)\n      *(.rel.gnu.linkonce.s2.*)\n    }\n  .rela.sdata2   : \n    {\n      *(.rela.sdata2)\n      *(.rela.sdata2.*)\n      *(.rela.gnu.linkonce.s2.*)\n    }\n  .rel.sbss2     : \n    { \n      *(.rel.sbss2)\t\n      *(.rel.sbss2.*)\n      *(.rel.gnu.linkonce.sb2.*)\n    }\n  .rela.sbss2    : \n    { \n      *(.rela.sbss2)\t\n      *(.rela.sbss2.*)\n      *(.rela.gnu.linkonce.sb2.*)\n    }\n  .rel.bss       : \n    { \n      *(.rel.bss)\n      *(.rel.bss.*)\n      *(.rel.gnu.linkonce.b.*)\n    }\n  .rela.bss      : \n    { \n      *(.rela.bss)\n      *(.rela.bss.*)\n      *(.rela.gnu.linkonce.b.*)\n    }\n  .rel.plt       : { *(.rel.plt)\t\t}\n  .rela.plt      : { *(.rela.plt)\t\t}\n\n  .init.pre  :\n  {\n    *(.init.pre)\n  }\n\n  .init          : \n  { \n    *(.text.init)\n    *(.data.init)\n  }\n\n  \/* We want the GDT and IDT to be page aligned. *\/\n  . = ALIGN (0x1000);\n  .special       :\n  {\n    *(.gdt)\n    *(.idt)\n  }\n  \n  . = ALIGN (0x1000);\n  _init_end = .;\n\n  .text      :\n  {\n    *(.text)\n    *(.text.*)\n    *(.stub)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.gnu.linkonce.t.*)\n  } =0x9090\n  .fini      :\n  {\n    KEEP (*(.fini))\n  } =0x9090\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata   : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) }\n  .rodata1   : { *(.rodata1) }\n  .sdata2   : { *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) }\n  .sbss2   : { *(.sbss2) *(.sbss2.*) *(.gnu.linkonce.sb2.*) }\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n  . = ALIGN(0x1000) + (. & (0x1000 - 1));\n  .data    :\n  {\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .data1   : { *(.data1) }\n  .eh_frame : { KEEP (*(.eh_frame)) }\n  .gcc_except_table : { *(.gcc_except_table) }\n  .ctors   : \n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n   .dtors         :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .got\t\t  : { *(.got.plt) *(.got) }\n  .dynamic       : { *(.dynamic) }\n  \/* We want the small data sections together, so single-instruction offsets\n     can access them all, and initialized data all before uninitialized, so\n     we can shorten the on-disk segment size.  *\/\n  .sdata     : \n  {\n    *(.sdata) \n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n  }\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .sbss      :\n  {\n    PROVIDE (__sbss_start = .);\n    PROVIDE (___sbss_start = .);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    PROVIDE (__sbss_end = .);\n    PROVIDE (___sbss_end = .);\n  }\n  .bss       :\n  {\n   *(.dynbss)\n   *(.bss)\n   *(.bss.*)\n   *(.gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  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{"commit":"0b899205793f9a4b07464b3f069f664bb7f5f600","subject":"arch\/x86: update linker definition for x86 real mode","message":"arch\/x86: update linker definition for x86 real mode\n\nWhen building the real mode, the linker definition has to place\nthe real mode entry code at the start of flash area.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"nashif\/zephyr,kraj\/zephyr,ldts\/zephyr,nashif\/zephyr,punitvara\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,finikorg\/zephyr,ldts\/zephyr,punitvara\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,explora26\/zephyr,kraj\/zephyr,galak\/zephyr,ldts\/zephyr,explora26\/zephyr,Vudentz\/zephyr,kraj\/zephyr,ldts\/zephyr,kraj\/zephyr,explora26\/zephyr,nashif\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,ldts\/zephyr,galak\/zephyr,kraj\/zephyr,Vudentz\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,galak\/zephyr","old_file":"include\/arch\/x86\/linker.ld","new_file":"include\/arch\/x86\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n#ifdef CONFIG_REALMODE\n\t\/* 16-bit sections *\/\n\t. = PHYS_RAM_ADDR;\n\n\tSECTION_PROLOGUE(boot, (OPTIONAL),)\n\t{\n\t*(.boot)\n\t. = ALIGN(16);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\t. = ALIGN(8);\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#ifndef CONFIG_REALMODE\n\t_image_text_start = PHYS_LOAD_ADDR;\n#else\n\t_image_text_start = .;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMMU_PAGE_ALIGN\n#ifdef CONFIG_XIP\n\t\/* Kernel ROM extends to the end of flash. Need to do this to program\n\t * the MMU\n\t *\/\n\t_image_rom_end = _image_rom_start + KB(CONFIG_ROM_SIZE);\n#else\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t_image_rom_end = .;\n#endif\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\t\/* APP SHARED MEMORY REGION *\/\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\tMMU_PAGE_ALIGN\n\t\t_app_smem_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n#ifndef CONFIG_XIP\n\t\tMMU_PAGE_ALIGN\n#endif\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t\tMMU_PAGE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * Without Jailhouse, we get the page alignment here for free by\n\t * definition of the beginning of the \"RAMable\" region on the board\n\t * configurations. With Jailhouse, everything falls in RAM and we\n\t * try to glue sections in sequence, thus we have to realign here so\n\t * that gen_mmu.py does not complain.\n\t *\/\n#ifdef CONFIG_JAILHOUSE\n\tMMU_PAGE_ALIGN\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n\n#ifdef CONFIG_X86_MMU\n\t\/* Can't really predict the size of this section. Anything after this\n\t * should not be affected if addresses change between builds (currently\n\t * just the gperf tables which is fine).\n\t *\n\t * However, __mmu_tables_start *must* remain stable between builds,\n\t * we can't have anything shifting the memory map beforehand.\n\t *\/\n\tSECTION_DATA_PROLOGUE(mmu_tables, (OPTIONAL),)\n\t{\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu_x86.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n#ifdef CONFIG_JAILHOUSE\n\t\/* 16-bit sections *\/\n\t. = PHYS_RAM_ADDR;\n\n\tSECTION_PROLOGUE(boot, (OPTIONAL),)\n\t{\n\t*(.boot)\n\t. = ALIGN(16);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\t. = ALIGN(8);\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#ifndef CONFIG_JAILHOUSE\n\t_image_text_start = PHYS_LOAD_ADDR;\n#else\n\t_image_text_start = .;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMMU_PAGE_ALIGN\n#ifdef CONFIG_XIP\n\t\/* Kernel ROM extends to the end of flash. Need to do this to program\n\t * the MMU\n\t *\/\n\t_image_rom_end = _image_rom_start + KB(CONFIG_ROM_SIZE);\n#else\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t_image_rom_end = .;\n#endif\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\t\/* APP SHARED MEMORY REGION *\/\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\tMMU_PAGE_ALIGN\n\t\t_app_smem_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n#ifndef CONFIG_XIP\n\t\tMMU_PAGE_ALIGN\n#endif\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t\tMMU_PAGE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * Without Jailhouse, we get the page alignment here for free by\n\t * definition of the beginning of the \"RAMable\" region on the board\n\t * configurations. With Jailhouse, everything falls in RAM and we\n\t * try to glue sections in sequence, thus we have to realign here so\n\t * that gen_mmu.py does not complain.\n\t *\/\n#ifdef CONFIG_JAILHOUSE\n\tMMU_PAGE_ALIGN\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n\n#ifdef CONFIG_X86_MMU\n\t\/* Can't really predict the size of this section. Anything after this\n\t * should not be affected if addresses change between builds (currently\n\t * just the gperf tables which is fine).\n\t *\n\t * However, __mmu_tables_start *must* remain stable between builds,\n\t * we can't have anything shifting the memory map beforehand.\n\t *\/\n\tSECTION_DATA_PROLOGUE(mmu_tables, (OPTIONAL),)\n\t{\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu_x86.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7d9e1d4b7515f9c56365bcb156169b9902e6a440","subject":"reserved topmost 32 bytes of RAM used by IAP functions","message":"reserved topmost 32 bytes of RAM used by IAP functions\n\nNXP LPC176x\/5x User Manual UM10360 Rev 4.1:\r\n32.3.2.8 RAM used by IAP command handler\r\nFlash programming commands use the top 32 bytes of on-chip RAM. The maximum stack \r\nusage in the user allocated stack space is 128 bytes and it grows downwards.","repos":"betzw\/mbed-os,adamgreen\/mbed,svogl\/mbed-os,YarivCol\/mbed-os,kl-cruz\/mbed-os,YarivCol\/mbed-os,kjbracey-arm\/mbed,Archcady\/mbed-os,svogl\/mbed-os,nRFMesh\/mbed-os,mmorenobarm\/mbed-os,c1728p9\/mbed-os,kjbracey-arm\/mbed,karsev\/mbed-os,mbedmicro\/mbed,kl-cruz\/mbed-os,kl-cruz\/mbed-os,karsev\/mbed-os,mazimkhan\/mbed-os,HeadsUpDisplayInc\/mbed,pradeep-gr\/mbed-os5-onsemi,netzimme\/mbed-os,andcor02\/mbed-os,ryankurte\/mbed-os,CalSol\/mbed,andcor02\/mbed-os,HeadsUpDisplayInc\/mbed,screamerbg\/mbed,monkiineko\/mbed-os,betzw\/mbed-os,infinnovation\/mbed-os,YarivCol\/mbed-os,HeadsUpDisplayInc\/mbed,mmorenobarm\/mbed-os,mikaleppanen\/mbed-os,mikaleppanen\/mbed-os,karsev\/mbed-os,catiedev\/mbed-os,mmorenobarm\/mbed-os,bcostm\/mbed-os,screamerbg\/mbed,YarivCol\/mbed-os,betzw\/mbed-os,arostm\/mbed-os,monkiineko\/mbed-os,mmorenobarm\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,adamgreen\/mbed,pradeep-gr\/mbed-os5-onsemi,c1728p9\/mbed-os,netzimme\/mbed-os,arostm\/mbed-os,catiedev\/mbed-os,c1728p9\/mbed-os,mikaleppanen\/mbed-os,andcor02\/mbed-os,monkiineko\/mbed-os,infinnovation\/mbed-os,betzw\/mbed-os,ryankurte\/mbed-os,fahhem\/mbed-os,ryankurte\/mbed-os,NXPmicro\/mbed,mazimkhan\/mbed-os,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,NXPmicro\/mbed,NXPmicro\/mbed,karsev\/mbed-os,ryankurte\/mbed-os,fahhem\/mbed-os,betzw\/mbed-os,CalSol\/mbed,mazimkhan\/mbed-os,bcostm\/mbed-os,catiedev\/mbed-os,CalSol\/mbed,HeadsUpDisplayInc\/mbed,kjbracey-arm\/mbed,pradeep-gr\/mbed-os5-onsemi,nRFMesh\/mbed-os,arostm\/mbed-os,mazimkhan\/mbed-os,mbedmicro\/mbed,mikaleppanen\/mbed-os,mazimkhan\/mbed-os,arostm\/mbed-os,YarivCol\/mbed-os,kl-cruz\/mbed-os,kl-cruz\/mbed-os,pradeep-gr\/mbed-os5-onsemi,c1728p9\/mbed-os,nRFMesh\/mbed-os,bcostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,adamgreen\/mbed,NXPmicro\/mbed,svogl\/mbed-os,fahhem\/mbed-os,pradeep-gr\/mbed-os5-onsemi,andcor02\/mbed-os,infinnovation\/mbed-os,svogl\/mbed-os,adamgreen\/mbed,ryankurte\/mbed-os,mazimkhan\/mbed-os,infinnovation\/mbed-os,mikaleppanen\/mbed-os,adamgreen\/mbed,adamgreen\/mbed,catiedev\/mbed-os,mmorenobarm\/mbed-os,nRFMesh\/mbed-os,karsev\/mbed-os,mbedmicro\/mbed,HeadsUpDisplayInc\/mbed,Archcady\/mbed-os,bcostm\/mbed-os,monkiineko\/mbed-os,YarivCol\/mbed-os,fahhem\/mbed-os,bcostm\/mbed-os,fahhem\/mbed-os,infinnovation\/mbed-os,kl-cruz\/mbed-os,Archcady\/mbed-os,bcostm\/mbed-os,fahhem\/mbed-os,andcor02\/mbed-os,NXPmicro\/mbed,Archcady\/mbed-os,screamerbg\/mbed,Archcady\/mbed-os,infinnovation\/mbed-os,screamerbg\/mbed,arostm\/mbed-os,betzw\/mbed-os,nRFMesh\/mbed-os,kjbracey-arm\/mbed,CalSol\/mbed,mikaleppanen\/mbed-os,svogl\/mbed-os,mmorenobarm\/mbed-os,catiedev\/mbed-os,monkiineko\/mbed-os,catiedev\/mbed-os,screamerbg\/mbed,CalSol\/mbed,svogl\/mbed-os,netzimme\/mbed-os,ryankurte\/mbed-os,CalSol\/mbed,c1728p9\/mbed-os,Archcady\/mbed-os,NXPmicro\/mbed,arostm\/mbed-os,karsev\/mbed-os,netzimme\/mbed-os,monkiineko\/mbed-os,nRFMesh\/mbed-os,screamerbg\/mbed,mbedmicro\/mbed,netzimme\/mbed-os,netzimme\/mbed-os","old_file":"targets\/TARGET_NXP\/TARGET_LPC176X\/device\/TOOLCHAIN_GCC_CS\/LPC1768.ld","new_file":"targets\/TARGET_NXP\/TARGET_LPC176X\/device\/TOOLCHAIN_GCC_CS\/LPC1768.ld","new_contents":"\/* Linker script for mbed LPC1768\n *\n * Version:CodeSourcery Sourcery G++ Lite 2007q3-53\n * BugURL:https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n *  Copyright 2007 CodeSourcery.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions. No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply. *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(__cs3_reset_cortex_m)\nSEARCH_DIR(.)\n\n\/*\nram ORIGIN: 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8\nram LENGTH: 32KB (RAM size) - 0xC8 (NIVT) - 32 (topmost 32 bytes used by IAP functions) = 0x7F18\n*\/\nMEMORY\n{\n  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 512K\n  \n  ram (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F18\n  \n  ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n *\/\nEXTERN(__cs3_reset_cortex_m)\nEXTERN(__cs3_interrupt_vector_cortex_m)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)\n\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n  .text :\n  {\n    CREATE_OBJECT_SYMBOLS\n    __cs3_region_start_rom = .;\n    *(.cs3.region-head.rom)\n    __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;\n    *(.cs3.interrupt_vector)\n    \/* Make sure we pulled in an interrupt vector.  *\/\n    ASSERT (. != __cs3_interrupt_vector_cortex_m, \"No interrupt vector\");\n    *(.rom)\n    *(.rom.b)\n\n    __cs3_reset = __cs3_reset_cortex_m;\n    *(.cs3.reset)\n    \/* Make sure we pulled in some reset code.  *\/\n    ASSERT (. != __cs3_reset, \"No reset code\");\n\n    *(.text .text.* .gnu.linkonce.t.*)\n    *(.plt)\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\n\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n    *(.gcc_except_table)\n    *(.eh_frame_hdr)\n    *(.eh_frame)\n\n    . = ALIGN(4);\n    KEEP(*(.init))\n\n    . = ALIGN(4);\n    __preinit_array_start = .;\n    KEEP (*(.preinit_array))\n    __preinit_array_end = .;\n\n    . = ALIGN(4);\n    __init_array_start = .;\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    __init_array_end = .;\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*crtend.o(.ctors))\n\n    . = ALIGN(4);\n    KEEP(*(.fini))\n\n    . = ALIGN(4);\n    __fini_array_start = .;\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    __fini_array_end = .;\n\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*crtend.o(.dtors))\n\n    . = ALIGN(4);\n    __cs3_regions = .;\n    LONG (0)\n    LONG (__cs3_region_init_ram)\n    LONG (__cs3_region_start_ram)\n    LONG (__cs3_region_init_size_ram)\n    LONG (__cs3_region_zero_size_ram)\n  }\n\n  \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } >rom\n  __exidx_end = .;\n  .text.align :\n  {\n    . = ALIGN(8);\n    _etext = .;\n  } >rom\n  __cs3_region_size_rom = LENGTH(rom);\n  __cs3_region_num = 1;\n  \n  .data :\n  {\n    __cs3_region_start_ram = .;\n    *(.cs3.region-head.ram)\n    KEEP(*(.jcr))\n    *(.got.plt) *(.got)\n    *(.shdata)\n    *(.data .data.* .gnu.linkonce.d.*)\n    *(.ram)\n    . = ALIGN (8);\n    _edata = .;\n  } >ram AT>rom\n  .bss :\n  {\n    *(.shbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    *(.ram.b)\n    . = ALIGN (8);\n    _end = .;\n    __end = .;\n  } >ram AT>rom\n  \/* This used for USB RAM section *\/\n\t.usb_ram (NOLOAD):\n\t{\n\t\t*.o (USB_RAM)\n\t} > ram2\n  .heap (NOLOAD) :\n  {\n    *(.heap)\n  } >ram\n  .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):\n  {\n    *(.stack)\n    _estack = .;\n    PROVIDE(estack = .);\n  } >ram\n\n  __cs3_region_init_ram = LOADADDR (.data);\n  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;\n  __cs3_region_zero_size_ram = _end - _edata;\n  __cs3_region_size_ram = LENGTH(ram);\n  __cs3_region_num = 1;\n\n  .stab 0 (NOLOAD) : { *(.stab) }\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\n  \/* DWARF debug sections.\n   * Symbols in the DWARF debugging sections are relative to the beginning\n   * of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/* Linker script for mbed LPC1768\n *\n * Version:CodeSourcery Sourcery G++ Lite 2007q3-53\n * BugURL:https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n *  Copyright 2007 CodeSourcery.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions. No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply. *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(__cs3_reset_cortex_m)\nSEARCH_DIR(.)\n\n\/*\nram ORIGIN: 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8\nram LENGTH: 32KB - 0xC8 = 0x7F38\n*\/\nMEMORY\n{\n  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 512K\n  \n  ram (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n  \n  ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n *\/\nEXTERN(__cs3_reset_cortex_m)\nEXTERN(__cs3_interrupt_vector_cortex_m)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)\n\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n  .text :\n  {\n    CREATE_OBJECT_SYMBOLS\n    __cs3_region_start_rom = .;\n    *(.cs3.region-head.rom)\n    __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;\n    *(.cs3.interrupt_vector)\n    \/* Make sure we pulled in an interrupt vector.  *\/\n    ASSERT (. != __cs3_interrupt_vector_cortex_m, \"No interrupt vector\");\n    *(.rom)\n    *(.rom.b)\n\n    __cs3_reset = __cs3_reset_cortex_m;\n    *(.cs3.reset)\n    \/* Make sure we pulled in some reset code.  *\/\n    ASSERT (. != __cs3_reset, \"No reset code\");\n\n    *(.text .text.* .gnu.linkonce.t.*)\n    *(.plt)\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\n\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n    *(.gcc_except_table)\n    *(.eh_frame_hdr)\n    *(.eh_frame)\n\n    . = ALIGN(4);\n    KEEP(*(.init))\n\n    . = ALIGN(4);\n    __preinit_array_start = .;\n    KEEP (*(.preinit_array))\n    __preinit_array_end = .;\n\n    . = ALIGN(4);\n    __init_array_start = .;\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    __init_array_end = .;\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*crtend.o(.ctors))\n\n    . = ALIGN(4);\n    KEEP(*(.fini))\n\n    . = ALIGN(4);\n    __fini_array_start = .;\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    __fini_array_end = .;\n\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*crtend.o(.dtors))\n\n    . = ALIGN(4);\n    __cs3_regions = .;\n    LONG (0)\n    LONG (__cs3_region_init_ram)\n    LONG (__cs3_region_start_ram)\n    LONG (__cs3_region_init_size_ram)\n    LONG (__cs3_region_zero_size_ram)\n  }\n\n  \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } >rom\n  __exidx_end = .;\n  .text.align :\n  {\n    . = ALIGN(8);\n    _etext = .;\n  } >rom\n  __cs3_region_size_rom = LENGTH(rom);\n  __cs3_region_num = 1;\n  \n  .data :\n  {\n    __cs3_region_start_ram = .;\n    *(.cs3.region-head.ram)\n    KEEP(*(.jcr))\n    *(.got.plt) *(.got)\n    *(.shdata)\n    *(.data .data.* .gnu.linkonce.d.*)\n    *(.ram)\n    . = ALIGN (8);\n    _edata = .;\n  } >ram AT>rom\n  .bss :\n  {\n    *(.shbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    *(.ram.b)\n    . = ALIGN (8);\n    _end = .;\n    __end = .;\n  } >ram AT>rom\n  \/* This used for USB RAM section *\/\n\t.usb_ram (NOLOAD):\n\t{\n\t\t*.o (USB_RAM)\n\t} > ram2\n  .heap (NOLOAD) :\n  {\n    *(.heap)\n  } >ram\n  .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):\n  {\n    *(.stack)\n    _estack = .;\n    PROVIDE(estack = .);\n  } >ram\n\n  __cs3_region_init_ram = LOADADDR (.data);\n  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;\n  __cs3_region_zero_size_ram = _end - _edata;\n  __cs3_region_size_ram = LENGTH(ram);\n  __cs3_region_num = 1;\n\n  .stab 0 (NOLOAD) : { *(.stab) }\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\n  \/* DWARF debug sections.\n   * Symbols in the DWARF debugging sections are relative to the beginning\n   * of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bf4878f91b17cb73aaa54ac833970903049d2b10","subject":"Pack some functions into the bootloader's first page","message":"Pack some functions into the bootloader's first page\n","repos":"mtharp\/laureline-firmware,mtharp\/laureline-firmware,mtharp\/laureline-firmware,mtharp\/laureline-firmware","old_file":"bootloader\/ports\/STM32F107xB.ld","new_file":"bootloader\/ports\/STM32F107xB.ld","new_contents":"MEMORY\n{\n    flash1 (rx) : org = 0x08000000, len = 2k\n    flash (rx)  : org = 0x08000000 + 256k - 64k, len = 64k\n    ram (!rx)   : org = 0x20000000, len = 64k\n}\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    . = 0;\n\n    \/* The bootloader occupies the first page of flash (2K), then the remainder\n     * goes at the end of flash.\n     *\/\n    .startup : ALIGN(512)\n    {\n        KEEP(*(isr_vector))\n        . = 512;\n        boot_table = .;\n        KEEP(*(*.boot_table))\n        \/* pack some big functions into this page, to potentially save a page\n         * from the other region.\n         *\/\n        *(*chk_mounted*);\n        *(*follow_path);\n        *(*try_flash);\n        *(*_free_r);\n    } > flash1\n    _user_start = 2k;\n\n    .data :\n    {\n        . = ALIGN(4);\n        PROVIDE(_sdata = .);\n        *(.data)\n        *(.data.*)\n        . = ALIGN(4);\n        PROVIDE(_edata = .);\n    } > ram AT > flash\n    _sidata = LOADADDR(.data);\n    _user_end = _sidata;\n\n    .text :\n    {\n        *(.text)\n        *(.text.*)\n        *(.rodata)\n        *(.rodata.*)\n    } > flash\n\n    .bss :\n    {\n        . = ALIGN(4);\n        PROVIDE(_sbss = .);\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        PROVIDE(_ebss = .);\n    } > ram\n\n    .uninit (NOLOAD) :\n    {\n        *(.uninit)\n    } > ram\n\n    .heap :\n    {\n        PROVIDE(_sheap = .);\n    } > ram\n    PROVIDE(_eheap = ORIGIN(ram) + LENGTH(ram));\n}\n","old_contents":"MEMORY\n{\n    flash1 (rx) : org = 0x08000000, len = 2k\n    flash (rx)  : org = 0x08000000 + 256k - 64k, len = 64k\n    ram (!rx)   : org = 0x20000000, len = 64k\n}\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    . = 0;\n\n    \/* The bootloader occupies the first page of flash (2K), then the remainder\n     * goes at the end of flash.\n     *\/\n    .startup : ALIGN(512)\n    {\n        KEEP(*(isr_vector))\n        . = 512;\n        boot_table = .;\n        KEEP(*(*.boot_table))\n        . = 2k;\n        _user_start = .;\n    } > flash1\n\n    .data :\n    {\n        . = ALIGN(4);\n        PROVIDE(_sdata = .);\n        *(.data)\n        *(.data.*)\n        . = ALIGN(4);\n        PROVIDE(_edata = .);\n    } > ram AT > flash\n    _sidata = LOADADDR(.data);\n    _user_end = _sidata;\n\n    .text :\n    {\n        *(.text)\n        *(.text.*)\n        *(.rodata)\n        *(.rodata.*)\n    } > flash\n\n    .bss :\n    {\n        . = ALIGN(4);\n        PROVIDE(_sbss = .);\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        PROVIDE(_ebss = .);\n    } > ram\n\n    .uninit (NOLOAD) :\n    {\n        *(.uninit)\n    } > ram\n\n    .heap :\n    {\n        PROVIDE(_sheap = .);\n    } > ram\n    PROVIDE(_eheap = ORIGIN(ram) + LENGTH(ram));\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"474ee67bf4937499d18f28e3b9e092356acaa36c","subject":"soc: esp32: Fix symbol placement in linker script","message":"soc: esp32: Fix symbol placement in linker script\n\nCreating static libraries for drivers moves some symbols out of IRAM.\nThis change fixes it.\n\nSigned-off-by: Shubham Kulkarni <1478dde7897089bf180c3c690a61b19b869e8abd@espressif.com>\n","repos":"galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef ITERABLE_SECTION_RAM_GC_ALLOWED\n#define ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef ITERABLE_SECTION_RAM\n#define ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef ITERABLE_SECTION_ROM\n#define ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef ITERABLE_SECTION_RAM_GC_ALLOWED\n#define ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef ITERABLE_SECTION_RAM\n#define ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef ITERABLE_SECTION_ROM\n#define ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b765ebe9f860ed005c4998cedfe0492256c41be7","subject":"update usp\/isp size","message":"update usp\/isp size\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX63T\/R5F563T6.ld","new_file":"RX63T\/R5F563T6.ld","new_contents":"\/*\n\nCopyright (c) 2005,2008,2009 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x00001F00 \/* 8k - 256(USP + SP) *\/\n\tUSTACK (w) : ORIGIN = 0x00001FC0, LENGTH = 4 \/* ustack 192 bytes *\/\n\tISTACK (w) : ORIGIN = 0x00002000, LENGTH = 4 \/* istack 64 bytes  *\/\n\tROM (w)    : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FFD0 \/* 64k - 0x30(.fvectors) *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .istack (ORIGIN (ISTACK)) :\n  {\n    PROVIDE (__istack = .);\n    *(.istack)\n  }\n\n  .ustack (ORIGIN (USTACK)) :\n  {\n    PROVIDE (__ustack = .);\n    *(.ustack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x00001F00 \/* 8k - 256(USP + SP) *\/\n\tSTACK (w)  : ORIGIN = 0x00002000, LENGTH = 16 \/* top of RAM *\/\n\tROM (w)    : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FFD0 \/* 64k - 0x30(.fvectors) *\/\n\/* This is the largest RX6000: *\/\n\/*\tROM (w)   : ORIGIN = 0xffe00000, LENGTH = 0x001fffd0 *\/ \/* 2Mb *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"fbea34b07a9e9d18899d94504827327dc279d40f","subject":"Linker script: Fix IROM0_LEN calculation","message":"Linker script: Fix IROM0_LEN calculation\n\nUse linker script arithmetic (yay?) to calculate flash size in bytes\nfrom FLASH_SIZE in megabits.\n\nCloses #64\n","repos":"Zaltora\/esp-open-rtos,foogod\/esp-open-rtos,urx\/esp-open-rtos,UncleRus\/esp-open-rtos,mr-nice\/esp-open-rtos,kanflo\/esp-open-rtos,someburner\/esp-rtos-tests,bhuvanchandra\/esp-open-rtos,DCoJA\/esp-open-rtos,mr-nice\/esp-open-rtos,sheinz\/esp-open-rtos,urx\/esp-open-rtos,ourairquality\/esp-open-rtos,UncleRus\/esp-open-rtos,ourairquality\/esp-open-rtos,alainmaes\/esp-open-rtos,someburner\/esp-rtos-tests,hawkhsieh\/esp-open-rtos,andree182\/esp-open-rtos,andree182\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,alainmaes\/esp-open-rtos,kanflo\/esp-open-rtos,ourairquality\/esp-open-rtos,UncleRus\/esp-open-rtos,alainmaes\/esp-open-rtos,kanflo\/esp-open-rtos,UncleRus\/esp-open-rtos,SuperHouse\/esp-open-rtos,SuperHouse\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,kanflo\/esp-open-rtos,foogod\/esp-open-rtos,SuperHouse\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,Zaltora\/esp-open-rtos,mr-nice\/esp-open-rtos,UncleRus\/esp-open-rtos,Zaltora\/esp-open-rtos,SuperHouse\/esp-open-rtos,ourairquality\/esp-open-rtos,hawkhsieh\/esp-open-rtos,hawkhsieh\/esp-open-rtos,gpascualg\/esp-open-rtos,mr-nice\/esp-open-rtos,andree182\/esp-open-rtos,hawkhsieh\/esp-open-rtos,kanflo\/esp-open-rtos,Zaltora\/esp-open-rtos,DCoJA\/esp-open-rtos,ourairquality\/esp-open-rtos,SuperHouse\/esp-open-rtos,urx\/esp-open-rtos,DCoJA\/esp-open-rtos,someburner\/esp-rtos-tests,Zaltora\/esp-open-rtos,someburner\/esp-rtos-tests,ourairquality\/esp-open-rtos,sheinz\/esp-open-rtos,gpascualg\/esp-open-rtos,foogod\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,urx\/esp-open-rtos,kanflo\/esp-open-rtos,SuperHouse\/esp-open-rtos,UncleRus\/esp-open-rtos,DCoJA\/esp-open-rtos,sheinz\/esp-open-rtos,Zaltora\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,urx\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,urx\/esp-open-rtos,sheinz\/esp-open-rtos,andree182\/esp-open-rtos,alainmaes\/esp-open-rtos,gpascualg\/esp-open-rtos","old_file":"ld\/eagle.app.v6.ld","new_file":"ld\/eagle.app.v6.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP .\n\n   Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one.\n*\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* FreeRTOS lock functions.\n\n   Rely on a patch to libc that produces weak linked versions of the\n   below symbols. Currently treating locking primitives like universal\n   global critical section rather than individual locks, but this seems\n   OK from the use cases in newlib.\n*\/\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\n\/* Evaluate FLASH_SIZE to calculate irom size, etc.\n*\/\n#ifndef OTA\n\n\/* IROM0 section sits after other sections in the \"v1\" non-OTA bootloader image,\n   so need an 128kB offset to leave room\n*\/\n#define IROM0_OFFSET 0x20000\n\n#else \/* OTA *\/\n\n\/* For OTA, IROM0 becomes an actual \"section\" of the bootloader image,\n   so we only need to leave space for the second stage bootloader\n   (0x2000 bytes) and space for the bootloader & section headers (0x10\n   bytes) *\/\n#define IROM0_OFFSET 0x2010\n\n#if FLASH_SIZE < 16\n#error \"OTA support currently requires minimum 16 megabit flash\"\n#endif\n\n#endif\n\n\/* Full maximum length of IROM section is length of mappable flash (ie up to 1 megabyte),\n   minus anything mapped at start, minus single config SDK WiFi config sector at end\n*\/\n#define IROM0_LEN   ((0x20000*MIN(FLASH_SIZE,8)) - IROM0_OFFSET - 0x1000)\n\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x08000\n  irom0_0_seg :                       \torg = 0x40200000+IROM0_OFFSET, len = IROM0_LEN\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    . = ALIGN (16);\n    *(.vecbase.text)\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* esp-open-rtos compiled source files use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *sdklib*:*(.literal .text .literal.* .text.*)\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    \/* xthal_set_intset() called from PendSV in NMI context *\/\n    *libhal.a:*set_intset.o(.literal .text .literal.* .text.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    \/* esp-open-rtos compiled code goes into IROM by default\n       (except for libgcc which is matched above.)\n    *\/\n    *(.literal .text .literal.* .text.*)\n    \/* mbedtls rodata *\/\n    *mbedtls.a:*.o(.rodata.* .rodata)\n    \/* actual certificate in example (TEMPORARY HACK) *\/\n    *:cert.o(.rodata.* .rodata)\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom.* .irom.*.* .irom0.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP .\n\n   Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one.\n*\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* FreeRTOS lock functions.\n\n   Rely on a patch to libc that produces weak linked versions of the\n   below symbols. Currently treating locking primitives like universal\n   global critical section rather than individual locks, but this seems\n   OK from the use cases in newlib.\n*\/\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\n\/* Evaluate FLASH_SIZE to calculate irom size, etc.\n*\/\n#ifndef OTA\n\n#define IROM0_START 0x40220000\n\n\/* Non-OTA sizes *\/\n#if FLASH_SIZE == 2 \/* 256kB *\/\n#define IROM0_LEN 0x3C000\n#elif FLASH_SIZE == 4 \/* 512kB *\/\n#define IROM0_LEN 0x7C000\n#elif FLASH_SIZE == 8 \/* 1MB *\/\n#define IROM0_LEN 0xFC000\n#elif FLASH_SIZE == 16 \/* 2MB *\/\n#define IROM0_LEN 0x1FC000\n#elif FLASH_SIZE == 32 \/* 4MB *\/\n#define IROM0_LEN 0x3FC000\n#else \/*FLASH_SIZE*\/\n#error \"Unknown flash size for linker script. Check the FLASH_SIZE variable in your Makefile.\"\n#endif\n\n#else \/* OTA *\/\n\n\/* IROM0 becomes an actual \"section\" of the bootloader image, so we need to leave\n   space for the bootloader (0x2000 bytes) and space for the bootloader & section\n   headers (0x10 bytes)\n*\/\n#define IROM0_START 0x40202010\n\n\/* OTA sizes *\/\n#if FLASH_SIZE < 16\n#error \"OTA support currently requires 16 or 32 megabit flash\"\n#elif FLASH_SIZE == 16 || FLASH_SIZE == 32\n\/* 1MB irom0 section regardless, minus the space for the bootloader *\/\n#define IROM0_LEN (0x100000 - 0x2010)\n#else \/*FLASH_SIZE*\/\n#error \"Unknown flash size for linker script. Check the FLASH_SIZE variable in your Makefile.\"\n#endif\n\n#endif\n\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x08000\n  irom0_0_seg :                       \torg = IROM0_START, len = IROM0_LEN\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    . = ALIGN (16);\n    *(.vecbase.text)\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* esp-open-rtos compiled source files use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *sdklib*:*(.literal .text .literal.* .text.*)\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    \/* xthal_set_intset() called from PendSV in NMI context *\/\n    *libhal.a:*set_intset.o(.literal .text .literal.* .text.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    \/* esp-open-rtos compiled code goes into IROM by default\n       (except for libgcc which is matched above.)\n    *\/\n    *(.literal .text .literal.* .text.*)\n    \/* mbedtls rodata *\/\n    *mbedtls.a:*.o(.rodata.* .rodata)\n    \/* actual certificate in example (TEMPORARY HACK) *\/\n    *:cert.o(.rodata.* .rodata)\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom.* .irom.*.* .irom0.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"abd24ae4f1b07180e3394f3ae7b915ddad39fc32","subject":"K64F: Explicitly set the start of .text","message":"K64F: Explicitly set the start of .text\n\nIf you don't specify the start address of a section explicitly, that\nsection can end up at different addresses depending on its alignment. If\nthe alignment of a section is not explicitly set, it inherits it from\nthe element with the highest alignment inside that section.\n\nSince the uVisor code is in the .text section, and it *must* end up at a\nknown location, we set the start address of .text to 0x410, which is the\nvalue that the uVisor binary expects.\n","repos":"andcor02\/mbed-os,Archcady\/mbed-os,mazimkhan\/mbed-os,jeremybrodt\/mbed,screamerbg\/mbed,j-greffe\/mbed-os,mikaleppanen\/mbed-os,catiedev\/mbed-os,mmorenobarm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,NXPmicro\/mbed,andreaslarssonublox\/mbed,karsev\/mbed-os,HeadsUpDisplayInc\/mbed,svastm\/mbed,mmorenobarm\/mbed-os,adustm\/mbed,rgrover\/mbed,infinnovation\/mbed-os,theotherjimmy\/mbed,svogl\/mbed-os,mazimkhan\/mbed-os,nRFMesh\/mbed-os,Archcady\/mbed-os,HeadsUpDisplayInc\/mbed,bcostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,svogl\/mbed-os,bulislaw\/mbed-os,nRFMesh\/mbed-os,ryankurte\/mbed-os,nvlsianpu\/mbed,mmorenobarm\/mbed-os,RonEld\/mbed,NXPmicro\/mbed,mazimkhan\/mbed-os,fahhem\/mbed-os,adustm\/mbed,catiedev\/mbed-os,netzimme\/mbed-os,fanghuaqi\/mbed,j-greffe\/mbed-os,betzw\/mbed-os,rgrover\/mbed,tung7970\/mbed-os-1,adustm\/mbed,fahhem\/mbed-os,svogl\/mbed-os,adustm\/mbed,bulislaw\/mbed-os,karsev\/mbed-os,ryankurte\/mbed-os,bcostm\/mbed-os,jeremybrodt\/mbed,bcostm\/mbed-os,arostm\/mbed-os,catiedev\/mbed-os,andreaslarssonublox\/mbed,Archcady\/mbed-os,tung7970\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,c1728p9\/mbed-os,bulislaw\/mbed-os,mbedmicro\/mbed,Archcady\/mbed-os,bcostm\/mbed-os,netzimme\/mbed-os,pradeep-gr\/mbed-os5-onsemi,theotherjimmy\/mbed,kl-cruz\/mbed-os,nRFMesh\/mbed-os,nRFMesh\/mbed-os,mazimkhan\/mbed-os,CalSol\/mbed,karsev\/mbed-os,YarivCol\/mbed-os,monkiineko\/mbed-os,infinnovation\/mbed-os,tung7970\/mbed-os,Archcady\/mbed-os,monkiineko\/mbed-os,NXPmicro\/mbed,fanghuaqi\/mbed,svastm\/mbed,fvincenzo\/mbed-os,nvlsianpu\/mbed,mbedmicro\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,c1728p9\/mbed-os,bulislaw\/mbed-os,adamgreen\/mbed,cvtsi2sd\/mbed-os,adamgreen\/mbed,fanghuaqi\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,nvlsianpu\/mbed,fvincenzo\/mbed-os,rgrover\/mbed,DanKupiniak\/mbed,infinnovation\/mbed-os,fahhem\/mbed-os,NXPmicro\/mbed,YarivCol\/mbed-os,nvlsianpu\/mbed,CalSol\/mbed,svastm\/mbed,nRFMesh\/mbed-os,nRFMesh\/mbed-os,rgrover\/mbed,cvtsi2sd\/mbed-os,tung7970\/mbed-os-1,kjbracey-arm\/mbed,bcostm\/mbed-os,screamerbg\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,svastm\/mbed,andcor02\/mbed-os,catiedev\/mbed-os,karsev\/mbed-os,arostm\/mbed-os,screamerbg\/mbed,fvincenzo\/mbed-os,monkiineko\/mbed-os,j-greffe\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,kl-cruz\/mbed-os,geky\/mbed,theotherjimmy\/mbed,adustm\/mbed,maximmbed\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,maximmbed\/mbed,c1728p9\/mbed-os,adamgreen\/mbed,c1728p9\/mbed-os,infinnovation\/mbed-os,CalSol\/mbed,tung7970\/mbed-os-1,arostm\/mbed-os,tung7970\/mbed-os-1,YarivCol\/mbed-os,cvtsi2sd\/mbed-os,maximmbed\/mbed,monkiineko\/mbed-os,RonEld\/mbed,mazimkhan\/mbed-os,betzw\/mbed-os,netzimme\/mbed-os,ryankurte\/mbed-os,CalSol\/mbed,mikaleppanen\/mbed-os,adamgreen\/mbed,geky\/mbed,fvincenzo\/mbed-os,fanghuaqi\/mbed,svastm\/mbed,mbedmicro\/mbed,kl-cruz\/mbed-os,fahhem\/mbed-os,j-greffe\/mbed-os,maximmbed\/mbed,tung7970\/mbed-os-1,catiedev\/mbed-os,fanghuaqi\/mbed,andreaslarssonublox\/mbed,betzw\/mbed-os,andcor02\/mbed-os,YarivCol\/mbed-os,ryankurte\/mbed-os,arostm\/mbed-os,YarivCol\/mbed-os,j-greffe\/mbed-os,YarivCol\/mbed-os,nvlsianpu\/mbed,c1728p9\/mbed-os,infinnovation\/mbed-os,kjbracey-arm\/mbed,betzw\/mbed-os,arostm\/mbed-os,kjbracey-arm\/mbed,tung7970\/mbed-os,pradeep-gr\/mbed-os5-onsemi,mikaleppanen\/mbed-os,andcor02\/mbed-os,kl-cruz\/mbed-os,svogl\/mbed-os,geky\/mbed,maximmbed\/mbed,RonEld\/mbed,nvlsianpu\/mbed,Archcady\/mbed-os,catiedev\/mbed-os,HeadsUpDisplayInc\/mbed,svogl\/mbed-os,betzw\/mbed-os,andreaslarssonublox\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,CalSol\/mbed,ryankurte\/mbed-os,j-greffe\/mbed-os,mikaleppanen\/mbed-os,jeremybrodt\/mbed,screamerbg\/mbed,svogl\/mbed-os,mmorenobarm\/mbed-os,bulislaw\/mbed-os,HeadsUpDisplayInc\/mbed,cvtsi2sd\/mbed-os,bcostm\/mbed-os,adamgreen\/mbed,tung7970\/mbed-os,geky\/mbed,netzimme\/mbed-os,maximmbed\/mbed,DanKupiniak\/mbed,screamerbg\/mbed,HeadsUpDisplayInc\/mbed,cvtsi2sd\/mbed-os,CalSol\/mbed,mazimkhan\/mbed-os,tung7970\/mbed-os,RonEld\/mbed,kjbracey-arm\/mbed,rgrover\/mbed,karsev\/mbed-os,kl-cruz\/mbed-os,RonEld\/mbed,monkiineko\/mbed-os,theotherjimmy\/mbed,theotherjimmy\/mbed,monkiineko\/mbed-os,adustm\/mbed,DanKupiniak\/mbed,jeremybrodt\/mbed,adamgreen\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,karsev\/mbed-os,cvtsi2sd\/mbed-os,infinnovation\/mbed-os,RonEld\/mbed,netzimme\/mbed-os,NXPmicro\/mbed,kl-cruz\/mbed-os,fahhem\/mbed-os,DanKupiniak\/mbed,bulislaw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,mikaleppanen\/mbed-os,HeadsUpDisplayInc\/mbed,arostm\/mbed-os,ryankurte\/mbed-os,fvincenzo\/mbed-os,mikaleppanen\/mbed-os,netzimme\/mbed-os,andreaslarssonublox\/mbed,fahhem\/mbed-os,c1728p9\/mbed-os,screamerbg\/mbed,mbedmicro\/mbed,geky\/mbed,NXPmicro\/mbed,andcor02\/mbed-os,theotherjimmy\/mbed,jeremybrodt\/mbed,mmorenobarm\/mbed-os,mmorenobarm\/mbed-os","old_file":"hal\/targets\/cmsis\/TARGET_Freescale\/TARGET_K64F\/TOOLCHAIN_GCC_ARM\/MK64FN1M0xxx12.ld","new_file":"hal\/targets\/cmsis\/TARGET_Freescale\/TARGET_K64F\/TOOLCHAIN_GCC_ARM\/MK64FN1M0xxx12.ld","new_contents":"\/*\n** ###################################################################\n**     Processors:          MK64FN1M0VDC12\n**                          MK64FN1M0VLL12\n**                          MK64FN1M0VLQ12\n**                          MK64FN1M0VMD12\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014\n**     Version:             rev. 2.8, 2015-02-19\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n__ram_vector_table__ = 1;\n\n\/* Heap 1\/4 of ram and stack 1\/8 *\/\n__stack_size__ = 0x8000;\n__heap_size__ = 0x10000;\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: FLASH_OFFSET. *\/\n  __UVISOR_TEXT_OFFSET = 0x410;\n  __UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET;\n  .text __UVISOR_TEXT_START :\n  {\n    \/* uVisor code and data *\/\n    . = ALIGN(4);\n    __uvisor_main_start = .;\n    *(.uvisor.main)\n    __uvisor_main_end = .;\n\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  \/* Ensure that the uVisor BSS section is put first after the relocated\n   * interrupt table in SRAM. *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: SRAM_OFFSET. *\/\n  __UVISOR_SRAM_OFFSET = 0x400;\n  __UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;\n  ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,\n         \"The ISR relocation region overlaps with the uVisor BSS section.\")\n  .uvisor.bss (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uvisor_bss_start = .;\n\n    \/* protected uvisor main bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_main_start = .;\n    KEEP(*(.keep.uvisor.bss.main))\n    . = ALIGN(32);\n    __uvisor_bss_main_end = .;\n\n    \/* protected uvisor secure boxes bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_boxes_start = .;\n    KEEP(*(.keep.uvisor.bss.boxes))\n    . = ALIGN(32);\n    __uvisor_bss_boxes_end = .;\n\n    . = ALIGN(32);\n    __uvisor_bss_end = .;\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data :\n  {\n    PROVIDE(__etext = LOADADDR(.data));    \/* Define a global symbol at end of code, *\/\n    PROVIDE(__DATA_ROM = LOADADDR(.data)); \/* Symbol is used by startup for data initialization. *\/\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data_2 AT > m_text\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  \/* uVisor configuration section\n   * This section must be located after all other flash regions. *\/\n  .uvisor.secure :\n  {\n    . = ALIGN(32);\n    __uvisor_secure_start = .;\n\n    \/* uVisor secure boxes configuration tables *\/\n    . = ALIGN(32);\n    __uvisor_cfgtbl_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl))\n    . = ALIGN(32);\n    __uvisor_cfgtbl_end = .;\n\n    \/* Pointers to the uVisor secure boxes configuration tables *\/\n    \/* Note: Do not add any further alignment here, as uVisor will need to have\n     * access to the exact list of pointers. *\/\n    __uvisor_cfgtbl_ptr_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n    KEEP(*(.keep.uvisor.cfgtbl_ptr))\n    __uvisor_cfgtbl_ptr_end = .;\n\n    \/* Pointers to all boxes register gateways. These are grouped here to allow\n     * discoverability and firmware verification. *\/\n    __uvisor_register_gateway_ptr_start = .;\n    KEEP(*(.keep.uvisor.register_gateway_ptr))\n    __uvisor_register_gateway_ptr_end = .;\n\n    . = ALIGN(32);\n    __uvisor_secure_end = .;\n  } > m_text\n\n  \/* Uninitialized data section\n   * This region is not initialized by the C\/C++ library and can be used to\n   * store state across soft reboots. *\/\n  .uninitialized (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uninitialized_start = .;\n    *(.uninitialized)\n    KEEP(*(.keep.uninitialized))\n    . = ALIGN(32);\n    __uninitialized_end = .;\n  } > m_data_2\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data_2\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __uvisor_heap_start = .;\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n    __uvisor_heap_end = .;\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n    __StackTop = .;\n  } > m_data_2\n\n  \/* Heap space for the page allocator *\/\n  .page_heap (NOLOAD) :\n  {\n    __uvisor_page_start = .;\n    . = ORIGIN(m_data_2) + LENGTH(m_data_2) - 4;\n    __uvisor_page_end = .;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n\n  \/* Provide the physical memory boundaries for uVisor. *\/\n  __uvisor_flash_start = ORIGIN(m_interrupts);\n  __uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);\n  __uvisor_sram_start = ORIGIN(m_data);\n  __uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);\n}\n\n","old_contents":"\/*\n** ###################################################################\n**     Processors:          MK64FN1M0VDC12\n**                          MK64FN1M0VLL12\n**                          MK64FN1M0VLQ12\n**                          MK64FN1M0VMD12\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014\n**     Version:             rev. 2.8, 2015-02-19\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n__ram_vector_table__ = 1;\n\n\/* Heap 1\/4 of ram and stack 1\/8 *\/\n__stack_size__ = 0x8000;\n__heap_size__ = 0x10000;\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    \/* uVisor code and data *\/\n    . = ALIGN(4);\n    __uvisor_main_start = .;\n    *(.uvisor.main)\n    __uvisor_main_end = .;\n\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  \/* Ensure that the uVisor BSS section is put first after the relocated\n   * interrupt table in SRAM. *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: SRAM_OFFSET. *\/\n  __UVISOR_SRAM_OFFSET = 0x400;\n  __UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;\n  ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,\n         \"The ISR relocation region overlaps with the uVisor BSS section.\")\n  .uvisor.bss (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uvisor_bss_start = .;\n\n    \/* protected uvisor main bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_main_start = .;\n    KEEP(*(.keep.uvisor.bss.main))\n    . = ALIGN(32);\n    __uvisor_bss_main_end = .;\n\n    \/* protected uvisor secure boxes bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_boxes_start = .;\n    KEEP(*(.keep.uvisor.bss.boxes))\n    . = ALIGN(32);\n    __uvisor_bss_boxes_end = .;\n\n    . = ALIGN(32);\n    __uvisor_bss_end = .;\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data :\n  {\n    PROVIDE(__etext = LOADADDR(.data));    \/* Define a global symbol at end of code, *\/\n    PROVIDE(__DATA_ROM = LOADADDR(.data)); \/* Symbol is used by startup for data initialization. *\/\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data_2 AT > m_text\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  \/* uVisor configuration section\n   * This section must be located after all other flash regions. *\/\n  .uvisor.secure :\n  {\n    . = ALIGN(32);\n    __uvisor_secure_start = .;\n\n    \/* uVisor secure boxes configuration tables *\/\n    . = ALIGN(32);\n    __uvisor_cfgtbl_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl))\n    . = ALIGN(32);\n    __uvisor_cfgtbl_end = .;\n\n    \/* Pointers to the uVisor secure boxes configuration tables *\/\n    \/* Note: Do not add any further alignment here, as uVisor will need to have\n     * access to the exact list of pointers. *\/\n    __uvisor_cfgtbl_ptr_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n    KEEP(*(.keep.uvisor.cfgtbl_ptr))\n    __uvisor_cfgtbl_ptr_end = .;\n\n    \/* Pointers to all boxes register gateways. These are grouped here to allow\n     * discoverability and firmware verification. *\/\n    __uvisor_register_gateway_ptr_start = .;\n    KEEP(*(.keep.uvisor.register_gateway_ptr))\n    __uvisor_register_gateway_ptr_end = .;\n\n    . = ALIGN(32);\n    __uvisor_secure_end = .;\n  } > m_text\n\n  \/* Uninitialized data section\n   * This region is not initialized by the C\/C++ library and can be used to\n   * store state across soft reboots. *\/\n  .uninitialized (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uninitialized_start = .;\n    *(.uninitialized)\n    KEEP(*(.keep.uninitialized))\n    . = ALIGN(32);\n    __uninitialized_end = .;\n  } > m_data_2\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data_2\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __uvisor_heap_start = .;\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n    __uvisor_heap_end = .;\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n    __StackTop = .;\n  } > m_data_2\n\n  \/* Heap space for the page allocator *\/\n  .page_heap (NOLOAD) :\n  {\n    __uvisor_page_start = .;\n    . = ORIGIN(m_data_2) + LENGTH(m_data_2) - 4;\n    __uvisor_page_end = .;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n\n  \/* Provide the physical memory boundaries for uVisor. *\/\n  __uvisor_flash_start = ORIGIN(m_interrupts);\n  __uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);\n  __uvisor_sram_start = ORIGIN(m_data);\n  __uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a40fd2e7bd6eac07d5a3210b4c7358094ea011de","subject":"esp32.ld: Add an entry for ets_write_char_uart","message":"esp32.ld: Add an entry for ets_write_char_uart\n\nIt is mentioned in ets_sys.h, but not actually PROVIDEd.\n\nMerges https:\/\/github.com\/espressif\/esp-idf\/pull\/545\n","repos":"armada-ai\/esp-idf,hwmaier\/esp-idf,Hermiedapwdrman\/esp-idf,MIhanguangyi\/esp-idf,nineisk\/esp-idf,Hermiedapwdrman\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,armada-ai\/esp-idf,Hermiedapwdrman\/esp-idf,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,espressif\/esp-idf,shukyisme\/esp-idf-kwik,armada-ai\/esp-idf,www220\/esp-idf,ajs124\/esp-idf,nineisk\/esp-idf,mashaoze\/esp-idf,nineisk\/esp-idf,jaracil\/esp-idf,Hermiedapwdrman\/esp-idf,www220\/esp-idf,espressif\/esp-idf,empoweredhomes\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf,empoweredhomes\/esp-idf,hwmaier\/esp-idf,shukyisme\/esp-idf-kwik,www220\/esp-idf,MIhanguangyi\/esp-idf,nineisk\/esp-idf,empoweredhomes\/esp-idf,jaracil\/esp-idf,www220\/esp-idf,hwmaier\/esp-idf,hwmaier\/esp-idf,MIhanguangyi\/esp-idf,ajs124\/esp-idf,dschaefer\/esp-idf,dschaefer\/esp-idf,www220\/esp-idf,jaracil\/esp-idf,ajs124\/esp-idf,empoweredhomes\/esp-idf,Hermiedapwdrman\/esp-idf,dschaefer\/esp-idf,mashaoze\/esp-idf,dschaefer\/esp-idf,MIhanguangyi\/esp-idf,shukyisme\/esp-idf-kwik,shukyisme\/esp-idf-kwik,jaracil\/esp-idf,armada-ai\/esp-idf,ajs124\/esp-idf,MIhanguangyi\/esp-idf,empoweredhomes\/esp-idf,dschaefer\/esp-idf","old_file":"components\/esp32\/ld\/esp32.rom.ld","new_file":"components\/esp32\/ld\/esp32.rom.ld","new_contents":"\/*\nESP32 ROM address table\nGenerated for ROM with MD5sum:\nab8282ae908fe9e7a63fb2a4ac2df013  ..\/..\/rom_image\/prorom.elf\n*\/\nPROVIDE ( abort = 0x4000bba4 );\nPROVIDE ( abs = 0x40056340 );\nPROVIDE ( __absvdi2 = 0x4006387c );\nPROVIDE ( __absvsi2 = 0x40063868 );\nPROVIDE ( Add2SelfBigHex256 = 0x40015b7c );\nPROVIDE ( AddBigHex256 = 0x40015b28 );\nPROVIDE ( AddBigHexModP256 = 0x40015c98 );\nPROVIDE ( __adddf3 = 0x40002590 );\nPROVIDE ( AddP256 = 0x40015c74 );\nPROVIDE ( AddPdiv2_256 = 0x40015ce0 );\nPROVIDE ( __addsf3 = 0x400020e8 );\nPROVIDE ( __addvdi3 = 0x40002cbc );\nPROVIDE ( __addvsi3 = 0x40002c98 );\nPROVIDE ( aes_128_cbc_decrypt = 0x4005cc7c );\nPROVIDE ( aes_128_cbc_encrypt = 0x4005cc18 );\nPROVIDE ( aes_unwrap = 0x4005ccf0 );\nPROVIDE ( app_gpio_arg = 0x3ffe003c );\nPROVIDE ( app_gpio_handler = 0x3ffe0040 );\nPROVIDE ( __ascii_wctomb = 0x40058ef0 );\nPROVIDE ( asctime = 0x40059588 );\nPROVIDE ( asctime_r = 0x40000ec8 );\nPROVIDE ( __ashldi3 = 0x4000c818 );\nPROVIDE ( __ashrdi3 = 0x4000c830 );\nPROVIDE ( atoi = 0x400566c4 );\nPROVIDE ( _atoi_r = 0x400566d4 );\nPROVIDE ( atol = 0x400566ec );\nPROVIDE ( _atol_r = 0x400566fc );\nPROVIDE ( base64_decode = 0x4005ced8 );\nPROVIDE ( base64_encode = 0x4005cdbc );\nPROVIDE ( BasePoint_x_256 = 0x3ff97488 );\nPROVIDE ( BasePoint_y_256 = 0x3ff97468 );\nPROVIDE ( bigHexInversion256 = 0x400168f0 );\nPROVIDE ( bigHexP256 = 0x3ff973bc );\nPROVIDE ( __bswapdi2 = 0x400649c4 );\nPROVIDE ( __bswapsi2 = 0x4006499c );\nPROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c );\nPROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 );\nPROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 );\nPROVIDE ( btdm_r_data_init = 0x4001002c );\nPROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 );\nPROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 );\nPROVIDE ( btdm_r_ip_func_p_set = 0x40019afc );\nPROVIDE ( btdm_r_modules_func_p_get = 0x4005427c );\nPROVIDE ( btdm_r_modules_func_p_set = 0x40054270 );\nPROVIDE ( btdm_r_plf_func_p_set = 0x40054288 );\nPROVIDE ( bt_util_buf_env = 0x3ffb8bd4 );\nPROVIDE ( bzero = 0x4000c1f4 );\nPROVIDE ( cache_flash_mmu_set_rom = 0x400095e0 );\nPROVIDE ( Cache_Flush_rom = 0x40009a14 );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\nPROVIDE ( cache_sram_mmu_set_rom = 0x400097f4 );\n\/* This is static function, but can be used, not generated by script*\/\nPROVIDE ( calc_rtc_memory_crc = 0x40008170 );\nPROVIDE ( calloc = 0x4000bee4 );\nPROVIDE ( _calloc_r = 0x4000bbf8 );\nPROVIDE ( _cleanup = 0x40001df8 );\nPROVIDE ( _cleanup_r = 0x40001d48 );\nPROVIDE ( __clear_cache = 0x40063860 );\nPROVIDE ( close = 0x40001778 );\nPROVIDE ( _close_r = 0x4000bd3c );\nPROVIDE ( __clrsbdi2 = 0x40064a38 );\nPROVIDE ( __clrsbsi2 = 0x40064a20 );\nPROVIDE ( __clzdi2 = 0x4000ca50 );\nPROVIDE ( __clzsi2 = 0x4000c7e8 );\nPROVIDE ( __cmpdi2 = 0x40063820 );\nPROVIDE ( co_default_bdaddr = 0x3ffae704 );\nPROVIDE ( co_null_bdaddr = 0x3ffb80e0 );\nPROVIDE ( co_sca2ppm = 0x3ff971e8 );\nPROVIDE ( crc16_be = 0x4005d09c );\nPROVIDE ( crc16_le = 0x4005d05c );\nPROVIDE ( crc32_be = 0x4005d024 );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( crc8_be = 0x4005d114 );\nPROVIDE ( crc8_le = 0x4005d0e0 );\nPROVIDE ( creat = 0x40000e8c );\nPROVIDE ( ctime = 0x400595b0 );\nPROVIDE ( ctime_r = 0x400595c4 );\nPROVIDE ( _ctype_ = 0x3ff96354 );\nPROVIDE ( __ctype_ptr__ = 0x3ff96350 );\nPROVIDE ( __ctzdi2 = 0x4000ca64 );\nPROVIDE ( __ctzsi2 = 0x4000c7f0 );\nPROVIDE ( _data_end_rom = 0x4000d5c8 );\nPROVIDE ( _data_end_btdm_rom = 0x4000d4f8 );\nPROVIDE ( _data_start_rom = 0x4000d4f8 );\nPROVIDE ( _data_start_btdm_rom = 0x4000d4f4 );\nPROVIDE ( _data_start_btdm = 0x3ffae6e0);\nPROVIDE ( _data_end_btdm = 0x3ffaff10);\nPROVIDE ( _bss_start_btdm = 0x3ffb8000);\nPROVIDE ( _bss_end_btdm = 0x3ffbff70);\nPROVIDE ( _daylight = 0x3ffae0a4 );\nPROVIDE ( dbg_default_handler = 0x3ff97218 );\nPROVIDE ( dbg_state = 0x3ffb8d5d );\nPROVIDE ( DebugE256PublicKey_x = 0x3ff97428 );\nPROVIDE ( DebugE256PublicKey_y = 0x3ff97408 );\nPROVIDE ( DebugE256SecretKey = 0x3ff973e8 );\nPROVIDE ( debug_timer = 0x3ffe042c );\nPROVIDE ( debug_timerfn = 0x3ffe0430 );\nPROVIDE ( dh_group14_generator = 0x3ff9ac60 );\nPROVIDE ( dh_group14_prime = 0x3ff9ab60 );\nPROVIDE ( dh_group15_generator = 0x3ff9ab5f );\nPROVIDE ( dh_group15_prime = 0x3ff9a9df );\nPROVIDE ( dh_group16_generator = 0x3ff9a9de );\nPROVIDE ( dh_group16_prime = 0x3ff9a7de );\nPROVIDE ( dh_group17_generator = 0x3ff9a7dd );\nPROVIDE ( dh_group17_prime = 0x3ff9a4dd );\nPROVIDE ( dh_group18_generator = 0x3ff9a4dc );\nPROVIDE ( dh_group18_prime = 0x3ff9a0dc );\nPROVIDE ( dh_group1_generator = 0x3ff9ae03 );\nPROVIDE ( dh_group1_prime = 0x3ff9ada3 );\nPROVIDE ( dh_group2_generator = 0x3ff9ada2 );\nPROVIDE ( dh_group2_prime = 0x3ff9ad22 );\nPROVIDE ( dh_group5_generator = 0x3ff9ad21 );\nPROVIDE ( dh_group5_prime = 0x3ff9ac61 );\nPROVIDE ( div = 0x40056348 );\nPROVIDE ( __divdc3 = 0x40064460 );\nPROVIDE ( __divdf3 = 0x40002954 );\nPROVIDE ( __divdi3 = 0x4000ca84 );\nPROVIDE ( __divsc3 = 0x40064200 );\nPROVIDE ( __divsf3 = 0x4000234c );\nPROVIDE ( __divsi3 = 0x4000c7b8 );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );\nPROVIDE ( __dummy_lock = 0x4000c728 );\nPROVIDE ( __dummy_lock_try = 0x4000c730 );\nPROVIDE ( ecc_env = 0x3ffb8d60 );\nPROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 );\nPROVIDE ( em_buf_env = 0x3ffb8d74 );\nPROVIDE ( environ = 0x3ffae0b4 );\nPROVIDE ( __env_lock = 0x40001fd4 );\nPROVIDE ( __env_unlock = 0x40001fe0 );\nPROVIDE ( __eqdf2 = 0x400636a8 );\nPROVIDE ( __eqsf2 = 0x40063374 );\nPROVIDE ( esp_crc8 = 0x4005d144 );\nPROVIDE ( _etext = 0x4000d66c );\nPROVIDE ( ets_readySet_ = 0x3ffe01f0 );\nPROVIDE ( ets_startup_callback = 0x3ffe0404 );\nPROVIDE ( exc_cause_table = 0x3ff991d0 );\nPROVIDE ( _exit_r = 0x4000bd28 );\nPROVIDE ( __extendsfdf2 = 0x40002c34 );\nPROVIDE ( fclose = 0x400020ac );\nPROVIDE ( _fclose_r = 0x40001fec );\nPROVIDE ( fflush = 0x40059394 );\nPROVIDE ( _fflush_r = 0x40059320 );\nPROVIDE ( __ffsdi2 = 0x4000ca2c );\nPROVIDE ( __ffssi2 = 0x4000c804 );\nPROVIDE ( _findenv_r = 0x40001f44 );\nPROVIDE ( __fixdfdi = 0x40002ac4 );\nPROVIDE ( __fixdfsi = 0x40002a78 );\nPROVIDE ( __fixsfdi = 0x4000244c );\nPROVIDE ( __fixsfsi = 0x4000240c );\nPROVIDE ( __fixunsdfsi = 0x40002b30 );\nPROVIDE ( __fixunssfdi = 0x40002504 );\nPROVIDE ( __fixunssfsi = 0x400024ac );\nPROVIDE ( __floatdidf = 0x4000c988 );\nPROVIDE ( __floatdisf = 0x4000c8c0 );\nPROVIDE ( __floatsidf = 0x4000c944 );\nPROVIDE ( __floatsisf = 0x4000c870 );\nPROVIDE ( __floatundidf = 0x4000c978 );\nPROVIDE ( __floatundisf = 0x4000c8b0 );\nPROVIDE ( __floatunsidf = 0x4000c938 );\nPROVIDE ( __floatunsisf = 0x4000c864 );\nPROVIDE ( __fp_lock_all = 0x40001f1c );\nPROVIDE ( __fp_unlock_all = 0x40001f30 );\nPROVIDE ( fputwc = 0x40058ea8 );\nPROVIDE ( __fputwc = 0x40058da0 );\nPROVIDE ( _fputwc_r = 0x40058e4c );\nPROVIDE ( free = 0x4000beb8 );\nPROVIDE ( _free_r = 0x4000bbcc );\nPROVIDE ( _fstat_r = 0x4000bccc );\nPROVIDE ( _fwalk = 0x4000c738 );\nPROVIDE ( _fwalk_reent = 0x4000c770 );\nPROVIDE ( __gcc_bcmp = 0x40064a70 );\nPROVIDE ( __gedf2 = 0x40063768 );\nPROVIDE ( __gesf2 = 0x4006340c );\nPROVIDE ( __get_current_time_locale = 0x40001834 );\nPROVIDE ( _getenv_r = 0x40001fbc );\nPROVIDE ( _getpid_r = 0x4000bcfc );\nPROVIDE ( __getreent = 0x4000be8c );\nPROVIDE ( _gettimeofday_r = 0x4000bc58 );\nPROVIDE ( __gettzinfo = 0x40001fcc );\nPROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 );\nPROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 );\nPROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c );\nPROVIDE ( _global_impure_ptr = 0x3ffae0b0 );\nPROVIDE ( gmtime = 0x40059848 );\nPROVIDE ( gmtime_r = 0x40059868 );\nPROVIDE ( g_phyFuns_instance = 0x3ffae0c4 );\nPROVIDE ( g_rom_flashchip = 0x3ffae270 );\nPROVIDE ( __gtdf2 = 0x400636dc );\nPROVIDE ( __gtsf2 = 0x400633a0 );\nPROVIDE ( gTxMsg = 0x3ffe0050 );\nPROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 );\nPROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 );\nPROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c );\nPROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 );\nPROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 );\nPROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c );\nPROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 );\nPROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 );\nPROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 );\nPROVIDE ( hci_command_handler = 0x4004c928 );\nPROVIDE ( hci_env = 0x3ffb9350 );\nPROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c );\nPROVIDE ( hci_evt_desc_tab = 0x3ff9751c );\nPROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 );\nPROVIDE ( hci_fc_env = 0x3ffb9340 );\nPROVIDE ( hmac_md5 = 0x4005d264 );\nPROVIDE ( hmac_md5_vector = 0x4005d17c );\nPROVIDE ( hmac_sha1 = 0x40060acc );\nPROVIDE ( hmac_sha1_vector = 0x400609e4 );\nPROVIDE ( hmac_sha256 = 0x40060d58 );\nPROVIDE ( hmac_sha256_vector = 0x40060c84 );\nPROVIDE ( isalnum = 0x40000f04 );\nPROVIDE ( isalpha = 0x40000f18 );\nPROVIDE ( isascii = 0x4000c20c );\nPROVIDE ( _isatty_r = 0x40000ea0 );\nPROVIDE ( isblank = 0x40000f2c );\nPROVIDE ( iscntrl = 0x40000f50 );\nPROVIDE ( isdigit = 0x40000f64 );\nPROVIDE ( isgraph = 0x40000f94 );\nPROVIDE ( islower = 0x40000f78 );\nPROVIDE ( isprint = 0x40000fa8 );\nPROVIDE ( ispunct = 0x40000fc0 );\nPROVIDE ( isspace = 0x40000fd4 );\nPROVIDE ( isupper = 0x40000fe8 );\nPROVIDE ( itoa = 0x400566b4 );\nPROVIDE ( __itoa = 0x40056678 );\nPROVIDE ( jd_decomp = 0x400613e8 );\nPROVIDE ( jd_prepare = 0x40060fa8 );\nPROVIDE ( ke_env = 0x3ffb93cc );\nPROVIDE ( _kill_r = 0x4000bd10 );\nPROVIDE ( labs = 0x40056370 );\nPROVIDE ( lb_default_handler = 0x3ff982b8 );\nPROVIDE ( lb_default_state_tab_p_get = 0x4001c198 );\nPROVIDE ( lb_env = 0x3ffb9424 );\nPROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c );\nPROVIDE ( lb_state = 0x3ffb94e8 );\nPROVIDE ( lc_default_handler = 0x3ff98648 );\nPROVIDE ( lc_default_state_tab_p_get = 0x4002f494 );\nPROVIDE ( lc_env = 0x3ffb94ec );\nPROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 );\nPROVIDE ( lc_state = 0x3ffb9508 );\nPROVIDE ( ld_acl_br_sizes = 0x3ff98a2a );\nPROVIDE ( ld_acl_br_types = 0x3ff98a36 );\nPROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 );\nPROVIDE ( ld_acl_edr_types = 0x3ff98a22 );\nPROVIDE ( ld_env = 0x3ffb9510 );\nPROVIDE ( ldiv = 0x40056378 );\nPROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c );\nPROVIDE ( ld_sched_params = 0x3ffb96c0 );\nPROVIDE ( ld_sync_train_channels = 0x3ff98a3c );\nPROVIDE ( __ledf2 = 0x40063704 );\nPROVIDE ( __lesf2 = 0x400633c0 );\nPROVIDE ( _link_r = 0x4000bc9c );\nPROVIDE ( llc_default_handler = 0x3ff98b3c );\nPROVIDE ( llc_default_state_tab_p_get = 0x40046058 );\nPROVIDE ( llc_env = 0x3ffb96d0 );\nPROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 );\nPROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 );\nPROVIDE ( llc_hci_command_handler = 0x40042360 );\nPROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 );\nPROVIDE ( llc_state = 0x3ffb96f8 );\nPROVIDE ( lldesc_build_chain = 0x4000a850 );\nPROVIDE ( lldesc_num2link = 0x4000a948 );\nPROVIDE ( lldesc_set_owner = 0x4000a974 );\nPROVIDE ( lld_evt_env = 0x3ffb9704 );\nPROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 );\nPROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 );\nPROVIDE ( LLM_AA_CT1 = 0x3ff98d8a );\nPROVIDE ( LLM_AA_CT2 = 0x3ff98d88 );\nPROVIDE ( llm_default_handler = 0x3ff98d80 );\nPROVIDE ( llm_default_state_tab_p_get = 0x4004e718 );\nPROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 );\nPROVIDE ( llm_le_env = 0x3ffb976c );\nPROVIDE ( llm_local_cmds = 0x3ff98d38 );\nPROVIDE ( llm_local_data_len_values = 0x3ff98d1c );\nPROVIDE ( llm_local_le_feats = 0x3ff98d30 );\nPROVIDE ( llm_local_le_states = 0x3ff98d28 );\nPROVIDE ( llm_state = 0x3ffb985c );\nPROVIDE ( lm_default_handler = 0x3ff990e0 );\nPROVIDE ( lm_default_state_tab_p_get = 0x40054268 );\nPROVIDE ( lm_env = 0x3ffb9860 );\nPROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c );\nPROVIDE ( lm_local_supp_feats = 0x3ff990ee );\nPROVIDE ( lm_n_page_tab = 0x3ff990e8 );\nPROVIDE ( lmp_desc_tab = 0x3ff96e6c );\nPROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c );\nPROVIDE ( lm_state = 0x3ffb9a1c );\nPROVIDE ( __locale_charset = 0x40059540 );\nPROVIDE ( __locale_cjk_lang = 0x40059558 );\nPROVIDE ( localeconv = 0x4005957c );\nPROVIDE ( _localeconv_r = 0x40059560 );\nPROVIDE ( __locale_mb_cur_max = 0x40059548 );\nPROVIDE ( __locale_msgcharset = 0x40059550 );\nPROVIDE ( localtime = 0x400595dc );\nPROVIDE ( localtime_r = 0x400595fc );\nPROVIDE ( _lock_acquire = 0x4000be14 );\nPROVIDE ( _lock_acquire_recursive = 0x4000be28 );\nPROVIDE ( _lock_close = 0x4000bdec );\nPROVIDE ( _lock_close_recursive = 0x4000be00 );\nPROVIDE ( _lock_init = 0x4000bdc4 );\nPROVIDE ( _lock_init_recursive = 0x4000bdd8 );\nPROVIDE ( _lock_release = 0x4000be64 );\nPROVIDE ( _lock_release_recursive = 0x4000be78 );\nPROVIDE ( _lock_try_acquire = 0x4000be3c );\nPROVIDE ( _lock_try_acquire_recursive = 0x4000be50 );\nPROVIDE ( longjmp = 0x400562cc );\nPROVIDE ( _lseek_r = 0x4000bd8c );\nPROVIDE ( __lshrdi3 = 0x4000c84c );\nPROVIDE ( __ltdf2 = 0x40063790 );\nPROVIDE ( __ltsf2 = 0x4006342c );\nPROVIDE ( malloc = 0x4000bea0 );\nPROVIDE ( _malloc_r = 0x4000bbb4 );\nPROVIDE ( maxSecretKey_256 = 0x3ff97448 );\nPROVIDE ( __mb_cur_max = 0x3ff96530 );\nPROVIDE ( MD5Final = 0x4005db1c );\nPROVIDE ( MD5Init = 0x4005da7c );\nPROVIDE ( MD5Update = 0x4005da9c );\nPROVIDE ( md5_vector = 0x4005db80 );\nPROVIDE ( memccpy = 0x4000c220 );\nPROVIDE ( memchr = 0x4000c244 );\nPROVIDE ( memcmp = 0x4000c260 );\nPROVIDE ( memcpy = 0x4000c2c8 );\nPROVIDE ( memmove = 0x4000c3c0 );\nPROVIDE ( memrchr = 0x4000c400 );\nPROVIDE ( memset = 0x4000c44c );\nPROVIDE ( mktime = 0x4005a5e8 );\nPROVIDE ( mmu_init = 0x400095a4 );\nPROVIDE ( __moddi3 = 0x4000cd4c );\nPROVIDE ( __modsi3 = 0x4000c7c0 );\nPROVIDE ( __month_lengths = 0x3ff9609c );\nPROVIDE ( __muldc3 = 0x40063bf4 );\nPROVIDE ( __muldf3 = 0x4006358c );\nPROVIDE ( __muldi3 = 0x4000c9fc );\nPROVIDE ( __mulsc3 = 0x40063934 );\nPROVIDE ( __mulsf3 = 0x400632c8 );\nPROVIDE ( __mulsi3 = 0x4000c7b0 );\nPROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 );\nPROVIDE ( MultiplyBigHexModP256 = 0x400160b8 );\nPROVIDE ( MultiplyByU32ModP256 = 0x40015fdc );\nPROVIDE ( multofup = 0x4000ab8c );\nPROVIDE ( __mulvdi3 = 0x40002d78 );\nPROVIDE ( __mulvsi3 = 0x40002d60 );\nPROVIDE ( mz_adler32 = 0x4005edbc );\nPROVIDE ( mz_crc32 = 0x4005ee88 );\nPROVIDE ( mz_free = 0x4005eed4 );\nPROVIDE ( __nedf2 = 0x400636a8 );\nPROVIDE ( __negdf2 = 0x400634a0 );\nPROVIDE ( __negdi2 = 0x4000ca14 );\nPROVIDE ( __negsf2 = 0x400020c0 );\nPROVIDE ( __negvdi2 = 0x40002e98 );\nPROVIDE ( __negvsi2 = 0x40002e78 );\nPROVIDE ( __nesf2 = 0x40063374 );\nPROVIDE ( notEqual256 = 0x40015b04 );\nPROVIDE ( __nsau_data = 0x3ff96544 );\nPROVIDE ( one_bits = 0x3ff971f8 );\nPROVIDE ( open = 0x4000178c );\nPROVIDE ( _open_r = 0x4000bd54 );\nPROVIDE ( __paritysi2 = 0x40002f3c );\nPROVIDE ( pbkdf2_sha1 = 0x40060ba4 );\nPROVIDE ( phy_get_romfuncs = 0x40004100 );\nPROVIDE ( __popcountdi2 = 0x40002ef8 );\nPROVIDE ( __popcountsi2 = 0x40002ed0 );\nPROVIDE ( __popcount_tab = 0x3ff96544 );\nPROVIDE ( __powidf2 = 0x400638d4 );\nPROVIDE ( __powisf2 = 0x4006389c );\nPROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 );\nPROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c );\nPROVIDE ( qsort = 0x40056424 );\nPROVIDE ( _raise_r = 0x4000bc70 );\nPROVIDE ( rand = 0x40001058 );\nPROVIDE ( rand_r = 0x400010d4 );\nPROVIDE ( r_btdm_option_data = 0x3ffae6e0 );\nPROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 );\nPROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 );\nPROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 );\nPROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 );\nPROVIDE ( r_bt_util_buf_init = 0x400100e4 );\nPROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 );\nPROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec );\nPROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 );\nPROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 );\nPROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 );\nPROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c );\nPROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec );\nPROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 );\nPROVIDE ( rc4_skip = 0x40060928 );\nPROVIDE ( r_co_bdaddr_compare = 0x40014324 );\nPROVIDE ( r_co_bytes_to_string = 0x400142e4 );\nPROVIDE ( r_co_list_check_size_available = 0x400142c4 );\nPROVIDE ( r_co_list_extract = 0x4001404c );\nPROVIDE ( r_co_list_extract_after = 0x40014118 );\nPROVIDE ( r_co_list_find = 0x4001419c );\nPROVIDE ( r_co_list_init = 0x40013f14 );\nPROVIDE ( r_co_list_insert_after = 0x40014254 );\nPROVIDE ( r_co_list_insert_before = 0x40014200 );\nPROVIDE ( r_co_list_merge = 0x400141bc );\nPROVIDE ( r_co_list_pool_init = 0x40013f30 );\nPROVIDE ( r_co_list_pop_front = 0x40014028 );\nPROVIDE ( r_co_list_push_back = 0x40013fb8 );\nPROVIDE ( r_co_list_push_front = 0x40013ff4 );\nPROVIDE ( r_co_list_size = 0x400142ac );\nPROVIDE ( r_co_nb_good_channels = 0x40014360 );\nPROVIDE ( r_co_slot_to_duration = 0x40014348 );\nPROVIDE ( r_dbg_init = 0x40014394 );\nPROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 );\nPROVIDE ( r_dbg_swdiag_init = 0x40014470 );\nPROVIDE ( r_dbg_swdiag_read = 0x400144a4 );\nPROVIDE ( r_dbg_swdiag_write = 0x400144d0 );\nPROVIDE ( r_E1 = 0x400108e8 );\nPROVIDE ( r_E21 = 0x40010968 );\nPROVIDE ( r_E22 = 0x400109b4 );\nPROVIDE ( r_E3 = 0x40010a58 );\nPROVIDE ( r_ea_alarm_clear = 0x40015ab4 );\nPROVIDE ( r_ea_alarm_set = 0x40015a10 );\nPROVIDE ( read = 0x400017dc );\nPROVIDE ( _read_r = 0x4000bda8 );\nPROVIDE ( r_ea_elt_cancel = 0x400150d0 );\nPROVIDE ( r_ea_elt_create = 0x40015264 );\nPROVIDE ( r_ea_elt_insert = 0x400152a8 );\nPROVIDE ( r_ea_elt_remove = 0x400154f0 );\nPROVIDE ( r_ea_finetimer_isr = 0x400155d4 );\nPROVIDE ( r_ea_init = 0x40015228 );\nPROVIDE ( r_ea_interval_create = 0x4001555c );\nPROVIDE ( r_ea_interval_delete = 0x400155a8 );\nPROVIDE ( r_ea_interval_duration_req = 0x4001597c );\nPROVIDE ( r_ea_interval_insert = 0x4001557c );\nPROVIDE ( r_ea_interval_remove = 0x40015590 );\nPROVIDE ( realloc = 0x4000becc );\nPROVIDE ( _realloc_r = 0x4000bbe0 );\nPROVIDE ( r_ea_offset_req = 0x40015748 );\nPROVIDE ( r_ea_sleep_check = 0x40015928 );\nPROVIDE ( r_ea_sw_isr = 0x40015724 );\nPROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 );\nPROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 );\nPROVIDE ( r_ecc_abort_key256_generation = 0x40017070 );\nPROVIDE ( r_ecc_generate_key256 = 0x40016e00 );\nPROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 );\nPROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 );\nPROVIDE ( r_ecc_get_debug_Keys = 0x40017224 );\nPROVIDE ( r_ecc_init = 0x40016dbc );\nPROVIDE ( RecvBuff = 0x3ffe009c );\nPROVIDE ( r_em_buf_init = 0x4001729c );\nPROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 );\nPROVIDE ( r_em_buf_rx_free = 0x400173c4 );\nPROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 );\nPROVIDE ( r_em_buf_tx_free = 0x4001741c );\nPROVIDE ( _rename_r = 0x4000bc28 );\nPROVIDE ( r_F1_256 = 0x400133e4 );\nPROVIDE ( r_F2_256 = 0x40013568 );\nPROVIDE ( r_F3_256 = 0x40013664 );\nPROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c );\nPROVIDE ( r_G_256 = 0x40013470 );\nPROVIDE ( r_H3 = 0x40013760 );\nPROVIDE ( r_H4 = 0x40013830 );\nPROVIDE ( r_h4tl_init = 0x40017878 );\nPROVIDE ( r_h4tl_start = 0x40017924 );\nPROVIDE ( r_h4tl_stop = 0x40017934 );\nPROVIDE ( r_h4tl_write = 0x400178d0 );\nPROVIDE ( r_H5 = 0x400138dc );\nPROVIDE ( r_hashConcat = 0x40013a38 );\nPROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c );\nPROVIDE ( r_hci_acl_tx_data_received = 0x40019654 );\nPROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 );\nPROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac );\nPROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c );\nPROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 );\nPROVIDE ( r_hci_cmd_received = 0x400192f8 );\nPROVIDE ( r_hci_evt_filter_add = 0x40018a64 );\nPROVIDE ( r_hci_evt_mask_set = 0x400189e4 );\nPROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 );\nPROVIDE ( r_hci_fc_acl_en = 0x400179d8 );\nPROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c );\nPROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 );\nPROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 );\nPROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c );\nPROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 );\nPROVIDE ( r_hci_fc_init = 0x40017974 );\nPROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 );\nPROVIDE ( r_hci_fc_sync_en = 0x40017a30 );\nPROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 );\nPROVIDE ( r_hci_init = 0x40018538 );\nPROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 );\nPROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 );\nPROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 );\nPROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 );\nPROVIDE ( r_hci_reset = 0x4001856c );\nPROVIDE ( r_hci_send_2_host = 0x400185bc );\nPROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 );\nPROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 );\nPROVIDE ( r_hci_tl_init = 0x40019290 );\nPROVIDE ( r_hci_tl_send = 0x40019228 );\nPROVIDE ( r_hci_util_pack = 0x40019874 );\nPROVIDE ( r_hci_util_unpack = 0x40019998 );\nPROVIDE ( r_hci_voice_settings_get = 0x40018bdc );\nPROVIDE ( r_hci_voice_settings_set = 0x40018be8 );\nPROVIDE ( r_HMAC = 0x40013968 );\nPROVIDE ( r_import_rf_phy_func = 0x3ffb8354 );\nPROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 );\nPROVIDE ( r_ip_funcs = 0x3ffae710 );\nPROVIDE ( r_ip_funcs_p = 0x3ffae70c );\nPROVIDE ( r_ke_check_malloc = 0x40019de0 );\nPROVIDE ( r_ke_event_callback_set = 0x40019ba8 );\nPROVIDE ( r_ke_event_clear = 0x40019c2c );\nPROVIDE ( r_ke_event_flush = 0x40019ccc );\nPROVIDE ( r_ke_event_get = 0x40019c78 );\nPROVIDE ( r_ke_event_get_all = 0x40019cc0 );\nPROVIDE ( r_ke_event_init = 0x40019b90 );\nPROVIDE ( r_ke_event_schedule = 0x40019cdc );\nPROVIDE ( r_ke_event_set = 0x40019be0 );\nPROVIDE ( r_ke_flush = 0x4001a374 );\nPROVIDE ( r_ke_free = 0x4001a014 );\nPROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 );\nPROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 );\nPROVIDE ( r_ke_init = 0x4001a318 );\nPROVIDE ( r_ke_is_free = 0x4001a184 );\nPROVIDE ( r_ke_malloc = 0x40019eb4 );\nPROVIDE ( r_ke_mem_init = 0x40019d3c );\nPROVIDE ( r_ke_mem_is_empty = 0x40019d8c );\nPROVIDE ( r_ke_msg_alloc = 0x4001a1e0 );\nPROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 );\nPROVIDE ( r_ke_msg_discard = 0x4001a850 );\nPROVIDE ( r_ke_msg_forward = 0x4001a290 );\nPROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac );\nPROVIDE ( r_ke_msg_free = 0x4001a2cc );\nPROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 );\nPROVIDE ( r_ke_msg_save = 0x4001a858 );\nPROVIDE ( r_ke_msg_send = 0x4001a234 );\nPROVIDE ( r_ke_msg_send_basic = 0x4001a26c );\nPROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec );\nPROVIDE ( r_ke_queue_extract = 0x40055fd0 );\nPROVIDE ( r_ke_queue_insert = 0x40056020 );\nPROVIDE ( r_ke_sleep_check = 0x4001a3d8 );\nPROVIDE ( r_ke_state_get = 0x4001a7d8 );\nPROVIDE ( r_ke_state_set = 0x4001a6fc );\nPROVIDE ( r_ke_stats_get = 0x4001a3f0 );\nPROVIDE ( r_ke_task_check = 0x4001a8a4 );\nPROVIDE ( r_ke_task_create = 0x4001a674 );\nPROVIDE ( r_ke_task_delete = 0x4001a6c0 );\nPROVIDE ( r_ke_task_init = 0x4001a650 );\nPROVIDE ( r_ke_task_msg_flush = 0x4001a860 );\nPROVIDE ( r_ke_timer_active = 0x4001ac08 );\nPROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 );\nPROVIDE ( r_ke_timer_clear = 0x4001ab90 );\nPROVIDE ( r_ke_timer_init = 0x4001aa9c );\nPROVIDE ( r_ke_timer_set = 0x4001aac0 );\nPROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 );\nPROVIDE ( r_KPrimC = 0x40010ad4 );\nPROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 );\nPROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 );\nPROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 );\nPROVIDE ( r_lb_init = 0x4001acd4 );\nPROVIDE ( r_lb_mst_key = 0x4001afc0 );\nPROVIDE ( r_lb_mst_key_cmp = 0x4001af74 );\nPROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 );\nPROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 );\nPROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c );\nPROVIDE ( r_lb_reset = 0x4001ad38 );\nPROVIDE ( r_lb_send_lmp = 0x4001adbc );\nPROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c );\nPROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 );\nPROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 );\nPROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 );\nPROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c );\nPROVIDE ( r_lc_afh_set = 0x4001cc74 );\nPROVIDE ( r_lc_afh_start = 0x4001d240 );\nPROVIDE ( r_lc_auth_cmp = 0x4001cd54 );\nPROVIDE ( r_lc_calc_link_key = 0x4001ce7c );\nPROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 );\nPROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc );\nPROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac );\nPROVIDE ( r_lc_chk_to = 0x4001d2a8 );\nPROVIDE ( r_lc_cmd_stat_send = 0x4001c914 );\nPROVIDE ( r_lc_comb_key_svr = 0x4001d30c );\nPROVIDE ( r_lc_con_cmp = 0x4001d44c );\nPROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc );\nPROVIDE ( r_lc_conn_seq_done = 0x40021334 );\nPROVIDE ( r_lc_detach = 0x4002037c );\nPROVIDE ( r_lc_dhkey = 0x4001d564 );\nPROVIDE ( r_lc_enc_cmp = 0x4001d8bc );\nPROVIDE ( r_lc_enc_key_refresh = 0x4001d720 );\nPROVIDE ( r_lc_end_chk_colli = 0x4001d858 );\nPROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 );\nPROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 );\nPROVIDE ( r_lc_epr_change_lk = 0x4001db38 );\nPROVIDE ( r_lc_epr_cmp = 0x4001da88 );\nPROVIDE ( r_lc_epr_resp = 0x4001e0b4 );\nPROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 );\nPROVIDE ( r_lc_ext_feat = 0x40020d6c );\nPROVIDE ( r_lc_feat = 0x40020984 );\nPROVIDE ( r_lc_hl_connect = 0x400209e8 );\nPROVIDE ( r_lc_init = 0x4001c948 );\nPROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 );\nPROVIDE ( r_lc_initiator_epr = 0x4001e064 );\nPROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 );\nPROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 );\nPROVIDE ( r_lc_key_exch_end = 0x4001e140 );\nPROVIDE ( r_lc_legacy_pair = 0x4001e1c0 );\nPROVIDE ( r_lc_local_switch = 0x4001e22c );\nPROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 );\nPROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 );\nPROVIDE ( r_lc_loc_auth = 0x40020ecc );\nPROVIDE ( r_lc_locepr_lkref = 0x4001d648 );\nPROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 );\nPROVIDE ( r_lc_loc_sniff = 0x40020a6c );\nPROVIDE ( r_lc_max_slot_mgt = 0x4001e410 );\nPROVIDE ( r_lc_mst_key = 0x4001e7c0 );\nPROVIDE ( r_lc_mst_qos_done = 0x4001ea80 );\nPROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 );\nPROVIDE ( r_lc_mutual_auth_end = 0x4001e670 );\nPROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 );\nPROVIDE ( r_lc_packet_type = 0x40021038 );\nPROVIDE ( r_lc_pair = 0x40020ddc );\nPROVIDE ( r_lc_pairing_cont = 0x4001eafc );\nPROVIDE ( r_lc_passkey_comm = 0x4001ed20 );\nPROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 );\nPROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec );\nPROVIDE ( r_lc_ptt = 0x4001ee2c );\nPROVIDE ( r_lc_ptt_cmp = 0x4001eeec );\nPROVIDE ( r_lc_qos_setup = 0x4001ef50 );\nPROVIDE ( r_lc_rd_rem_name = 0x4001efd0 );\nPROVIDE ( r_lc_release = 0x4001f8a8 );\nPROVIDE ( r_lc_rem_enc = 0x4001f124 );\nPROVIDE ( r_lc_rem_name_cont = 0x4001f290 );\nPROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 );\nPROVIDE ( r_lc_rem_sniff = 0x40020ca4 );\nPROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 );\nPROVIDE ( r_lc_rem_switch = 0x4001f070 );\nPROVIDE ( r_lc_rem_trans_mode = 0x4001f314 );\nPROVIDE ( r_lc_rem_unsniff = 0x400207a0 );\nPROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c );\nPROVIDE ( r_lc_reset = 0x4001c99c );\nPROVIDE ( r_lc_resp_auth = 0x4001f518 );\nPROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 );\nPROVIDE ( r_lc_resp_num_comp = 0x40020074 );\nPROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 );\nPROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c );\nPROVIDE ( r_lc_resp_pair = 0x400208a4 );\nPROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 );\nPROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c );\nPROVIDE ( r_lc_restart_enc = 0x4001f8ec );\nPROVIDE ( r_lc_restart_enc_cont = 0x4001f940 );\nPROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 );\nPROVIDE ( r_lc_restore_to = 0x4001f9e0 );\nPROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 );\nPROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 );\nPROVIDE ( r_lc_rsw_done = 0x4001db94 );\nPROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 );\nPROVIDE ( r_lc_sco_detach = 0x40021e40 );\nPROVIDE ( r_lc_sco_host_accept = 0x40022118 );\nPROVIDE ( r_lc_sco_host_reject = 0x400222b8 );\nPROVIDE ( r_lc_sco_host_request = 0x40021f4c );\nPROVIDE ( r_lc_sco_host_request_disc = 0x4002235c );\nPROVIDE ( r_lc_sco_init = 0x40021dc8 );\nPROVIDE ( r_lc_sco_peer_accept = 0x40022780 );\nPROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 );\nPROVIDE ( r_lc_sco_peer_reject = 0x40022824 );\nPROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c );\nPROVIDE ( r_lc_sco_peer_request = 0x4002240c );\nPROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec );\nPROVIDE ( r_lc_sco_release = 0x40021eec );\nPROVIDE ( r_lc_sco_reset = 0x40021dfc );\nPROVIDE ( r_lc_sco_timeout = 0x40022bd4 );\nPROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec );\nPROVIDE ( r_lc_semi_key_cmp = 0x40020294 );\nPROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c );\nPROVIDE ( r_lc_send_enc_mode = 0x40020220 );\nPROVIDE ( r_lc_send_lmp = 0x4001c1a8 );\nPROVIDE ( r_lc_send_pdu_acc = 0x4001c21c );\nPROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 );\nPROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 );\nPROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 );\nPROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c );\nPROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 );\nPROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 );\nPROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 );\nPROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 );\nPROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 );\nPROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 );\nPROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 );\nPROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec );\nPROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 );\nPROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 );\nPROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c );\nPROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c );\nPROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 );\nPROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec );\nPROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c );\nPROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 );\nPROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 );\nPROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 );\nPROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 );\nPROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 );\nPROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c );\nPROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 );\nPROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 );\nPROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 );\nPROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 );\nPROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 );\nPROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 );\nPROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 );\nPROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 );\nPROVIDE ( r_lc_send_pdu_sres = 0x4001c548 );\nPROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc );\nPROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 );\nPROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 );\nPROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 );\nPROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc );\nPROVIDE ( r_lc_sniff_init = 0x40022cac );\nPROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 );\nPROVIDE ( r_lc_sniff_reset = 0x40022cc8 );\nPROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 );\nPROVIDE ( r_lc_sniff_sub_mode = 0x400204fc );\nPROVIDE ( r_lc_sp_end = 0x400213a8 );\nPROVIDE ( r_lc_sp_fail = 0x40020470 );\nPROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc );\nPROVIDE ( r_lc_ssr_nego = 0x4002125c );\nPROVIDE ( r_lc_start = 0x4001ca28 );\nPROVIDE ( r_lc_start_enc = 0x4001fb28 );\nPROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c );\nPROVIDE ( r_lc_start_key_exch = 0x4001fe10 );\nPROVIDE ( r_lc_start_lmp_to = 0x4001fae8 );\nPROVIDE ( r_lc_start_oob = 0x4001fffc );\nPROVIDE ( r_lc_start_passkey = 0x4001feac );\nPROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 );\nPROVIDE ( r_lc_stop_afh_report = 0x40020184 );\nPROVIDE ( r_lc_stop_enc = 0x40020110 );\nPROVIDE ( r_lc_switch_cmp = 0x40020448 );\nPROVIDE ( r_lc_unit_key_svr = 0x400206d8 );\nPROVIDE ( r_lc_unsniff = 0x40020c50 );\nPROVIDE ( r_lc_unsniff_cmp = 0x40020810 );\nPROVIDE ( r_lc_unsniff_cont = 0x40020750 );\nPROVIDE ( r_lc_upd_to = 0x4002065c );\nPROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 );\nPROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac );\nPROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 );\nPROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c );\nPROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 );\nPROVIDE ( r_lc_version = 0x40020a30 );\nPROVIDE ( lmp_accepted_ext_handler = 0x40027290 );\nPROVIDE ( lmp_not_accepted_ext_handler = 0x40029c54 );\nPROVIDE ( lmp_clk_adj_handler = 0x40027468 );\nPROVIDE ( lmp_clk_adj_ack_handler = 0x400274f4 );\nPROVIDE ( lmp_clk_adj_req_handler = 0x4002751c );\nPROVIDE ( lmp_feats_res_ext_handler = 0x4002cac4 );\nPROVIDE ( lmp_feats_req_ext_handler = 0x4002ccb0 );\nPROVIDE ( lmp_pkt_type_tbl_req_handler = 0x40027574 );\nPROVIDE ( lmp_esco_link_req_handler = 0x40027610 );\nPROVIDE ( lmp_rmv_esco_link_req_handler = 0x400276e8 );\nPROVIDE ( lmp_ch_class_req_handler = 0x40027730 );\nPROVIDE ( lmp_ch_class_handler = 0x4002ca18 );\nPROVIDE ( lmp_ssr_req_handler = 0x4002780c );\nPROVIDE ( lmp_ssr_res_handler = 0x40027900 );\nPROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );\nPROVIDE ( lmp_pause_enc_req_handler = 0x4002df90 );\nPROVIDE ( lmp_resume_enc_req_handler = 0x4002e084 );\nPROVIDE ( lmp_num_comparison_fail_handler = 0x40027a74 );\nPROVIDE ( lmp_passkey_fail_handler = 0x40027aec );\nPROVIDE ( lmp_keypress_notif_handler = 0x4002c5c8 );\nPROVIDE ( lmp_pwr_ctrl_req_handler = 0x400263bc );\nPROVIDE ( lmp_pwr_ctrl_res_handler = 0x40026480 );\nPROVIDE ( lmp_auto_rate_handler = 0x40026548 );\nPROVIDE ( lmp_pref_rate_handler = 0x4002657c );\nPROVIDE ( lmp_name_req_handler = 0x40025050 );\nPROVIDE ( lmp_name_res_handler = 0x400250bc );\nPROVIDE ( lmp_not_accepted_handler = 0x400251d0 );\nPROVIDE ( lmp_accepted_handler = 0x4002e894 );\nPROVIDE ( lmp_clk_off_req_handler = 0x40025a44 );\nPROVIDE ( lmp_clk_off_res_handler = 0x40025ab8 );\nPROVIDE ( lmp_detach_handler = 0x40025b74 );\nPROVIDE ( lmp_tempkey_handler = 0x4002b6b0 );\nPROVIDE ( lmp_temprand_handler = 0x4002b74c );\nPROVIDE ( lmp_sres_handler = 0x4002b840 );\nPROVIDE ( lmp_aurand_handler = 0x4002bda0 );\nPROVIDE ( lmp_unitkey_handler = 0x4002c13c );\nPROVIDE ( lmp_combkey_handler = 0x4002c234 );\nPROVIDE ( lmp_inrand_handler = 0x4002c414 );\nPROVIDE ( lmp_oob_fail_handler = 0x40027b84 );\nPROVIDE ( lmp_ping_req_handler = 0x40027c08 );\nPROVIDE ( lmp_ping_res_handler = 0x40027c5c );\nPROVIDE ( lmp_enc_mode_req_handler = 0x40025c60 );\nPROVIDE ( lmp_enc_key_size_req_handler = 0x40025e54 );\nPROVIDE ( lmp_switch_req_handler = 0x40025f84 );\nPROVIDE ( lmp_start_enc_req_handler = 0x4002e124 );\nPROVIDE ( lmp_stop_enc_req_handler = 0x4002de30 );\nPROVIDE ( lmp_sniff_req_handler = 0x400260c8 );\nPROVIDE ( lmp_unsniff_req_handler = 0x400261e0 );\nPROVIDE ( lmp_incr_pwr_req_handler = 0x4002629c );\nPROVIDE ( lmp_decr_pwr_req_handler = 0x400262f8 );\nPROVIDE ( lmp_max_pwr_handler = 0x40026354 );\nPROVIDE ( lmp_min_pwr_handler = 0x40026388 );\nPROVIDE ( lmp_ver_req_handler = 0x400265f0 );\nPROVIDE ( lmp_ver_res_handler = 0x40026670 );\nPROVIDE ( lmp_qos_handler = 0x40026790 );\nPROVIDE ( lmp_qos_req_handler = 0x40026844 );\nPROVIDE ( lmp_sco_link_req_handler = 0x40026930 );\nPROVIDE ( lmp_rmv_sco_link_req_handler = 0x40026a10 );\nPROVIDE ( lmp_max_slot_handler = 0x40026a54 );\nPROVIDE ( lmp_max_slot_req_handler = 0x40026aac );\nPROVIDE ( lmp_timing_accu_req_handler = 0x40026b54 );\nPROVIDE ( lmp_timing_accu_res_handler = 0x40026bcc );\nPROVIDE ( lmp_setup_cmp_handler = 0x40026c84 );\nPROVIDE ( lmp_feats_res_handler = 0x4002b548 );\nPROVIDE ( lmp_feats_req_handler = 0x4002b620 );\nPROVIDE ( lmp_host_con_req_handler = 0x4002b3d8 );\nPROVIDE ( lmp_use_semi_perm_key_handler = 0x4002b4c4 );\nPROVIDE ( lmp_slot_off_handler = 0x40026cc8 );\nPROVIDE ( lmp_page_mode_req_handler = 0x40026d0c );\nPROVIDE ( lmp_page_scan_mode_req_handler = 0x40026d4c );\nPROVIDE ( lmp_supv_to_handler = 0x40026d94 );\nPROVIDE ( lmp_test_activate_handler = 0x40026e7c );\nPROVIDE ( lmp_test_ctrl_handler = 0x40026ee4 );\nPROVIDE ( lmp_enc_key_size_mask_req_handler = 0x40027038 );\nPROVIDE ( lmp_enc_key_size_mask_res_handler = 0x400270a4 );\nPROVIDE ( lmp_set_afh_handler = 0x4002b2e4 );\nPROVIDE ( lmp_encaps_hdr_handler = 0x40027120 );\nPROVIDE ( lmp_encaps_payl_handler = 0x4002e590 );\nPROVIDE ( lmp_sp_nb_handler = 0x4002acf0 );\nPROVIDE ( lmp_sp_cfm_handler = 0x4002b170 );\nPROVIDE ( lmp_dhkey_chk_handler = 0x4002ab48 );\nPROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );\nPROVIDE ( lmp_io_cap_res_handler = 0x4002c670 );\nPROVIDE ( lmp_io_cap_req_handler = 0x4002c7a4 );\nPROVIDE ( ld_acl_tx_packet_type_select = 0x4002fb40 );\nPROVIDE ( ld_acl_sched = 0x40033268 );\nPROVIDE ( ld_acl_sniff_sched = 0x4003340c );\nPROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 );\nPROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 );\nPROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 );\nPROVIDE ( r_ld_acl_afh_set = 0x40036b60 );\nPROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 );\nPROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 );\nPROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 );\nPROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 );\nPROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 );\nPROVIDE ( r_ld_acl_clk_set = 0x40036950 );\nPROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 );\nPROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 );\nPROVIDE ( r_ld_acl_data_flush = 0x400357bc );\nPROVIDE ( r_ld_acl_data_tx = 0x4003544c );\nPROVIDE ( r_ld_acl_edr_set = 0x4003678c );\nPROVIDE ( r_ld_acl_enc_key_load = 0x40036404 );\nPROVIDE ( r_ld_acl_flow_off = 0x40035400 );\nPROVIDE ( r_ld_acl_flow_on = 0x4003541c );\nPROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c );\nPROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 );\nPROVIDE ( r_ld_acl_init = 0x40034d08 );\nPROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 );\nPROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 );\nPROVIDE ( r_ld_acl_lsto_get = 0x400366b4 );\nPROVIDE ( r_ld_acl_lsto_set = 0x400366f8 );\nPROVIDE ( r_ld_acl_reset = 0x40034d24 );\nPROVIDE ( r_ld_acl_role_get = 0x40036b30 );\nPROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 );\nPROVIDE ( r_ld_acl_rsw_req = 0x40035e74 );\nPROVIDE ( r_ld_acl_rx_enc = 0x40036344 );\nPROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 );\nPROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 );\nPROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c );\nPROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 );\nPROVIDE ( r_ld_acl_sniff = 0x4003617c );\nPROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 );\nPROVIDE ( r_ld_acl_ssr_set = 0x40036274 );\nPROVIDE ( r_ld_acl_start = 0x40034ddc );\nPROVIDE ( r_ld_acl_stop = 0x4003532c );\nPROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 );\nPROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c );\nPROVIDE ( r_ld_acl_t_poll_get = 0x40036024 );\nPROVIDE ( r_ld_acl_t_poll_set = 0x40036068 );\nPROVIDE ( r_ld_acl_tx_enc = 0x400362f8 );\nPROVIDE ( r_ld_acl_unsniff = 0x400361e0 );\nPROVIDE ( r_ld_active_check = 0x4003cac4 );\nPROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec );\nPROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c );\nPROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 );\nPROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc );\nPROVIDE ( r_ld_bcst_acl_start = 0x4003882c );\nPROVIDE ( r_ld_bcst_afh_update = 0x40038f3c );\nPROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c );\nPROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 );\nPROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 );\nPROVIDE ( r_ld_bd_addr_get = 0x4003ca20 );\nPROVIDE ( r_ld_channel_assess = 0x4003c184 );\nPROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 );\nPROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 );\nPROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 );\nPROVIDE ( r_ld_csb_rx_init = 0x40039690 );\nPROVIDE ( r_ld_csb_rx_reset = 0x4003969c );\nPROVIDE ( r_ld_csb_rx_start = 0x4003972c );\nPROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 );\nPROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc );\nPROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c );\nPROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 );\nPROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 );\nPROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 );\nPROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 );\nPROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 );\nPROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 );\nPROVIDE ( r_ld_fm_frame_isr = 0x4003a82c );\nPROVIDE ( r_ld_fm_init = 0x4003a760 );\nPROVIDE ( r_ld_fm_prog_check = 0x4003ab28 );\nPROVIDE ( r_ld_fm_prog_disable = 0x4003a984 );\nPROVIDE ( r_ld_fm_prog_enable = 0x4003a944 );\nPROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 );\nPROVIDE ( r_ld_fm_reset = 0x4003a794 );\nPROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 );\nPROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 );\nPROVIDE ( r_ld_init = 0x4003c294 );\nPROVIDE ( r_ld_inq_init = 0x4003b15c );\nPROVIDE ( r_ld_inq_reset = 0x4003b168 );\nPROVIDE ( r_ld_inq_start = 0x4003b1f0 );\nPROVIDE ( r_ld_inq_stop = 0x4003b4f0 );\nPROVIDE ( r_ld_iscan_eir_get = 0x4003c118 );\nPROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 );\nPROVIDE ( r_ld_iscan_init = 0x4003b9f0 );\nPROVIDE ( r_ld_iscan_reset = 0x4003ba14 );\nPROVIDE ( r_ld_iscan_restart = 0x4003ba44 );\nPROVIDE ( r_ld_iscan_start = 0x4003bb28 );\nPROVIDE ( r_ld_iscan_stop = 0x4003bf1c );\nPROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 );\nPROVIDE ( r_ld_page_init = 0x4003d808 );\nPROVIDE ( r_ld_page_reset = 0x4003d814 );\nPROVIDE ( r_ld_page_start = 0x4003d848 );\nPROVIDE ( r_ld_page_stop = 0x4003da54 );\nPROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 );\nPROVIDE ( r_ld_pca_init = 0x4003deb4 );\nPROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac );\nPROVIDE ( r_ld_pca_local_config = 0x4003df6c );\nPROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 );\nPROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 );\nPROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 );\nPROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 );\nPROVIDE ( r_ld_pca_reset = 0x4003df0c );\nPROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 );\nPROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 );\nPROVIDE ( r_ld_pscan_init = 0x4003f474 );\nPROVIDE ( r_ld_pscan_reset = 0x4003f498 );\nPROVIDE ( r_ld_pscan_restart = 0x4003f4b8 );\nPROVIDE ( r_ld_pscan_start = 0x4003f514 );\nPROVIDE ( r_ld_pscan_stop = 0x4003f618 );\nPROVIDE ( r_ld_read_clock = 0x4003c9e4 );\nPROVIDE ( r_ld_reset = 0x4003c714 );\nPROVIDE ( r_ld_sched_acl_add = 0x4003f978 );\nPROVIDE ( r_ld_sched_acl_remove = 0x4003f99c );\nPROVIDE ( r_ld_sched_compute = 0x4003f6f8 );\nPROVIDE ( r_ld_sched_init = 0x4003f7ac );\nPROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 );\nPROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 );\nPROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 );\nPROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 );\nPROVIDE ( r_ld_sched_page_add = 0x4003f910 );\nPROVIDE ( r_ld_sched_page_remove = 0x4003f938 );\nPROVIDE ( r_ld_sched_pscan_add = 0x4003f828 );\nPROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 );\nPROVIDE ( r_ld_sched_reset = 0x4003f7d4 );\nPROVIDE ( r_ld_sched_sco_add = 0x4003fa4c );\nPROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c );\nPROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 );\nPROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c );\nPROVIDE ( r_ld_sched_sscan_add = 0x4003f868 );\nPROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 );\nPROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 );\nPROVIDE ( r_ld_sco_data_tx = 0x40037ee8 );\nPROVIDE ( r_ld_sco_start = 0x40037110 );\nPROVIDE ( r_ld_sco_stop = 0x40037c40 );\nPROVIDE ( r_ld_sco_update = 0x40037a74 );\nPROVIDE ( r_ld_sscan_activated = 0x4004031c );\nPROVIDE ( r_ld_sscan_init = 0x400402f0 );\nPROVIDE ( r_ld_sscan_reset = 0x400402fc );\nPROVIDE ( r_ld_sscan_start = 0x40040384 );\nPROVIDE ( r_ld_strain_init = 0x400409f4 );\nPROVIDE ( r_ld_strain_reset = 0x40040a00 );\nPROVIDE ( r_ld_strain_start = 0x40040a8c );\nPROVIDE ( r_ld_strain_stop = 0x40040df0 );\nPROVIDE ( r_ld_timing_accuracy_get = 0x4003caac );\nPROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c );\nPROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 );\nPROVIDE ( r_ld_util_bch_create = 0x40040fcc );\nPROVIDE ( r_ld_util_fhs_pk = 0x400411c8 );\nPROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 );\nPROVIDE ( r_ld_util_stp_pk = 0x400413f4 );\nPROVIDE ( r_ld_util_stp_unpk = 0x40041324 );\nPROVIDE ( r_ld_version_get = 0x4003ca6c );\nPROVIDE ( r_ld_wlcoex_set = 0x4003caf8 );\nPROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 );\nPROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c );\nPROVIDE ( r_llc_ch_assess_local = 0x40041494 );\nPROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 );\nPROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 );\nPROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac );\nPROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 );\nPROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c );\nPROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 );\nPROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c );\nPROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 );\nPROVIDE ( r_llc_con_update_complete_send = 0x40044d68 );\nPROVIDE ( r_llc_con_update_finished = 0x4004518c );\nPROVIDE ( r_llc_con_update_ind = 0x40045038 );\nPROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 );\nPROVIDE ( r_llc_end_evt_defer = 0x40046330 );\nPROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c );\nPROVIDE ( r_llc_init = 0x40044778 );\nPROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 );\nPROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 );\nPROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc );\nPROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 );\nPROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 );\nPROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 );\nPROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 );\nPROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 );\nPROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 );\nPROVIDE ( r_llc_llcp_get_autorize = 0x4004475c );\nPROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 );\nPROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac );\nPROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 );\nPROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 );\nPROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c );\nPROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 );\nPROVIDE ( r_llc_llcp_recv_handler = 0x40044678 );\nPROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c );\nPROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c );\nPROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 );\nPROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 );\nPROVIDE ( r_llc_llcp_tester_send = 0x400445e4 );\nPROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 );\nPROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c );\nPROVIDE ( r_llc_lsto_con_update = 0x40045098 );\nPROVIDE ( r_llc_ltk_req_send = 0x40044dc0 );\nPROVIDE ( r_llc_map_update_finished = 0x40045260 );\nPROVIDE ( r_llc_map_update_ind = 0x400450f0 );\nPROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc );\nPROVIDE ( r_llc_pdu_defer = 0x40046528 );\nPROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac );\nPROVIDE ( r_llc_reset = 0x400447b8 );\nPROVIDE ( r_llc_start = 0x400447f4 );\nPROVIDE ( r_llc_stop = 0x400449ac );\nPROVIDE ( r_llc_util_bw_mgt = 0x4004629c );\nPROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 );\nPROVIDE ( r_llc_util_dicon_procedure = 0x40046130 );\nPROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 );\nPROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 );\nPROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 );\nPROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 );\nPROVIDE ( r_llc_util_update_channel_map = 0x400461ac );\nPROVIDE ( r_llc_version_rd_event_send = 0x40044e60 );\nPROVIDE ( r_lld_adv_start = 0x40048b38 );\nPROVIDE ( r_lld_adv_stop = 0x40048ea0 );\nPROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 );\nPROVIDE ( r_lld_con_param_req = 0x40049f0c );\nPROVIDE ( r_lld_con_param_rsp = 0x40049e00 );\nPROVIDE ( r_lld_con_start = 0x400491f8 );\nPROVIDE ( r_lld_con_stop = 0x40049fdc );\nPROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc );\nPROVIDE ( r_lld_con_update_ind = 0x4004a30c );\nPROVIDE ( r_lld_con_update_req = 0x40049b60 );\nPROVIDE ( r_lld_core_reset = 0x40048a9c );\nPROVIDE ( r_lld_crypt_isr = 0x4004a324 );\nPROVIDE ( r_lld_evt_adv_create = 0x400481f4 );\nPROVIDE ( r_lld_evt_canceled = 0x400485c8 );\nPROVIDE ( r_lld_evt_channel_next = 0x40046aac );\nPROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc );\nPROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 );\nPROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c );\nPROVIDE ( r_lld_evt_drift_compute = 0x40047670 );\nPROVIDE ( r_lld_evt_elt_delete = 0x40047538 );\nPROVIDE ( r_lld_evt_elt_insert = 0x400474c8 );\nPROVIDE ( r_lld_evt_end = 0x400483e8 );\nPROVIDE ( r_lld_evt_end_isr = 0x4004862c );\nPROVIDE ( r_lld_evt_init = 0x40046b3c );\nPROVIDE ( r_lld_evt_init_evt = 0x40046cd0 );\nPROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 );\nPROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 );\nPROVIDE ( r_lld_evt_prevent_stop = 0x40047adc );\nPROVIDE ( r_lld_evt_restart = 0x40046d50 );\nPROVIDE ( r_lld_evt_rx = 0x40048578 );\nPROVIDE ( r_lld_evt_rx_isr = 0x40048678 );\nPROVIDE ( r_lld_evt_scan_create = 0x40047ae8 );\nPROVIDE ( r_lld_evt_schedule = 0x40047908 );\nPROVIDE ( r_lld_evt_schedule_next = 0x400477dc );\nPROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 );\nPROVIDE ( r_lld_evt_slave_update = 0x40048138 );\nPROVIDE ( r_lld_evt_update_create = 0x40047cd8 );\nPROVIDE ( r_lld_get_mode = 0x40049ff8 );\nPROVIDE ( r_lld_init = 0x4004873c );\nPROVIDE ( r_lld_move_to_master = 0x400499e0 );\nPROVIDE ( r_lld_move_to_slave = 0x4004a024 );\nPROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 );\nPROVIDE ( r_lld_pdu_check = 0x4004ac34 );\nPROVIDE ( r_lld_pdu_data_send = 0x4004b018 );\nPROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc );\nPROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 );\nPROVIDE ( r_lld_pdu_send_packet = 0x4004b774 );\nPROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 );\nPROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 );\nPROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 );\nPROVIDE ( r_lld_pdu_tx_push = 0x4004b080 );\nPROVIDE ( r_lld_ral_renew_req = 0x4004a73c );\nPROVIDE ( r_lld_scan_start = 0x40048ee0 );\nPROVIDE ( r_lld_scan_stop = 0x40049190 );\nPROVIDE ( r_lld_test_mode_rx = 0x4004a540 );\nPROVIDE ( r_lld_test_mode_tx = 0x4004a350 );\nPROVIDE ( r_lld_test_stop = 0x4004a710 );\nPROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc );\nPROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c );\nPROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 );\nPROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 );\nPROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 );\nPROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 );\nPROVIDE ( r_lld_util_flush_list = 0x4004bbd8 );\nPROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 );\nPROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac );\nPROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 );\nPROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 );\nPROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 );\nPROVIDE ( r_lld_util_instant_get = 0x4004b890 );\nPROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc );\nPROVIDE ( r_lld_util_priority_set = 0x4004bd10 );\nPROVIDE ( r_lld_util_priority_update = 0x4004bd78 );\nPROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 );\nPROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 );\nPROVIDE ( r_lld_wlcoex_set = 0x4004bd98 );\nPROVIDE ( r_llm_ble_ready = 0x4004cc34 );\nPROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 );\nPROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 );\nPROVIDE ( r_llm_con_req_ind = 0x4004cc54 );\nPROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 );\nPROVIDE ( r_llm_create_con = 0x4004de78 );\nPROVIDE ( r_llm_encryption_done = 0x4004dff8 );\nPROVIDE ( r_llm_encryption_start = 0x4004e128 );\nPROVIDE ( r_llm_end_evt_defer = 0x4004eb6c );\nPROVIDE ( r_llm_init = 0x4004c9f8 );\nPROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 );\nPROVIDE ( r_llm_pdu_defer = 0x4004ec48 );\nPROVIDE ( r_llm_ral_clear = 0x4004e1fc );\nPROVIDE ( r_llm_ral_dev_add = 0x4004e23c );\nPROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc );\nPROVIDE ( r_llm_ral_get_rpa = 0x4004e400 );\nPROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 );\nPROVIDE ( r_llm_ral_update = 0x4004e4f8 );\nPROVIDE ( r_llm_set_adv_data = 0x4004d960 );\nPROVIDE ( r_llm_set_adv_en = 0x4004d7ec );\nPROVIDE ( r_llm_set_adv_param = 0x4004d5f4 );\nPROVIDE ( r_llm_set_scan_en = 0x4004db64 );\nPROVIDE ( r_llm_set_scan_param = 0x4004dac8 );\nPROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 );\nPROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 );\nPROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc );\nPROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc );\nPROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 );\nPROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 );\nPROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 );\nPROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 );\nPROVIDE ( r_llm_util_bl_add = 0x4004e9ac );\nPROVIDE ( r_llm_util_bl_check = 0x4004e930 );\nPROVIDE ( r_llm_util_bl_rem = 0x4004ea70 );\nPROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 );\nPROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 );\nPROVIDE ( r_llm_util_check_map_validity = 0x4004e800 );\nPROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 );\nPROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 );\nPROVIDE ( r_llm_util_set_public_addr = 0x4004e89c );\nPROVIDE ( r_llm_wl_clr = 0x4004dc54 );\nPROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 );\nPROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 );\nPROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc );\nPROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 );\nPROVIDE ( r_lm_acl_disc = 0x4004f148 );\nPROVIDE ( r_LM_AddSniff = 0x40022d20 );\nPROVIDE ( r_lm_add_sync = 0x40051358 );\nPROVIDE ( r_lm_afh_activate_timer = 0x4004f444 );\nPROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 );\nPROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 );\nPROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c );\nPROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 );\nPROVIDE ( r_lm_check_active_sync = 0x40051334 );\nPROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c );\nPROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 );\nPROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c );\nPROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 );\nPROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 );\nPROVIDE ( r_LM_ComputePacketType = 0x4002f554 );\nPROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac );\nPROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 );\nPROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 );\nPROVIDE ( r_lm_dhkey_calc_init = 0x40013234 );\nPROVIDE ( r_lm_dhkey_compare = 0x400132d8 );\nPROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec );\nPROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 );\nPROVIDE ( r_lm_f1 = 0x40012bb8 );\nPROVIDE ( r_lm_f2 = 0x40012cfc );\nPROVIDE ( r_lm_f3 = 0x40013050 );\nPROVIDE ( r_lm_g = 0x40012f90 );\nPROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c );\nPROVIDE ( r_lm_get_auth_en = 0x4004f1ac );\nPROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c );\nPROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 );\nPROVIDE ( r_LM_GetFeature = 0x4002f924 );\nPROVIDE ( r_LM_GetLinkTimeout = 0x400233ec );\nPROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 );\nPROVIDE ( r_lm_get_loopback_mode = 0x4004f248 );\nPROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c );\nPROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 );\nPROVIDE ( r_LM_GetMasterKey = 0x4001b260 );\nPROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 );\nPROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 );\nPROVIDE ( r_lm_get_nb_acl = 0x4004ef9c );\nPROVIDE ( r_lm_get_nb_sync_link = 0x4005179c );\nPROVIDE ( r_lm_get_nonce = 0x400131c4 );\nPROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 );\nPROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 );\nPROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 );\nPROVIDE ( r_LM_GetPINType = 0x4004f1e8 );\nPROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 );\nPROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 );\nPROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 );\nPROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 );\nPROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 );\nPROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 );\nPROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c );\nPROVIDE ( r_lm_get_sp_en = 0x4004f1c0 );\nPROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 );\nPROVIDE ( r_lm_get_synchdl = 0x4005175c );\nPROVIDE ( r_lm_get_sync_param = 0x400503b4 );\nPROVIDE ( r_lm_init = 0x4004ed34 );\nPROVIDE ( r_lm_init_sync = 0x400512d8 );\nPROVIDE ( r_lm_is_acl_con = 0x4004f47c );\nPROVIDE ( r_lm_is_acl_con_role = 0x4004f49c );\nPROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 );\nPROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 );\nPROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 );\nPROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 );\nPROVIDE ( r_lm_look_for_sync = 0x40051774 );\nPROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c );\nPROVIDE ( r_lm_lt_addr_free = 0x4004ef74 );\nPROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 );\nPROVIDE ( r_LM_MakeCof = 0x4002f84c );\nPROVIDE ( r_LM_MakeRandVec = 0x400112d8 );\nPROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 );\nPROVIDE ( r_LM_MaxSlot = 0x4002f694 );\nPROVIDE ( r_lm_modif_sync = 0x40051578 );\nPROVIDE ( r_lm_n_is_zero = 0x40012170 );\nPROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 );\nPROVIDE ( r_lm_oob_f1 = 0x40012e54 );\nPROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 );\nPROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 );\nPROVIDE ( r_lmp_pack = 0x4001135c );\nPROVIDE ( r_lmp_unpack = 0x4001149c );\nPROVIDE ( r_lm_read_features = 0x4004f0d8 );\nPROVIDE ( r_LM_RemoveSniff = 0x40023124 );\nPROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 );\nPROVIDE ( r_lm_remove_sync = 0x400517c8 );\nPROVIDE ( r_lm_reset_sync = 0x40051304 );\nPROVIDE ( r_lm_role_switch_finished = 0x4004f028 );\nPROVIDE ( r_lm_role_switch_start = 0x4004efe0 );\nPROVIDE ( r_lm_sco_nego_end = 0x40051828 );\nPROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 );\nPROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 );\nPROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc );\nPROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 );\nPROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 );\nPROVIDE ( r_lm_sp_n_one = 0x400123a4 );\nPROVIDE ( r_lm_sp_p192_add = 0x40012828 );\nPROVIDE ( r_lm_sp_p192_dbl = 0x4001268c );\nPROVIDE ( r_lm_sp_p192_invert = 0x40012b6c );\nPROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 );\nPROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 );\nPROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 );\nPROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 );\nPROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 );\nPROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 );\nPROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 );\nPROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 );\nPROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 );\nPROVIDE ( r_modules_funcs = 0x3ffafd6c );\nPROVIDE ( r_modules_funcs_p = 0x3ffafd68 );\nPROVIDE ( r_nvds_del = 0x400544c4 );\nPROVIDE ( r_nvds_get = 0x40054488 );\nPROVIDE ( r_nvds_init = 0x40054410 );\nPROVIDE ( r_nvds_lock = 0x400544fc );\nPROVIDE ( r_nvds_put = 0x40054534 );\nPROVIDE ( rom_abs_temp = 0x400054f0 );\nPROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c );\nPROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac );\nPROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 );\nPROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 );\nPROVIDE ( rom_bb_wdg_test_en = 0x40003b70 );\nPROVIDE ( rom_cbw2040_cfg = 0x400040b0 );\nPROVIDE ( rom_check_noise_floor = 0x40003c78 );\nPROVIDE ( rom_chip_i2c_readReg = 0x40004110 );\nPROVIDE ( rom_chip_i2c_writeReg = 0x40004168 );\nPROVIDE ( rom_chip_v7_bt_init = 0x40004d8c );\nPROVIDE ( rom_chip_v7_rx_init = 0x40004cec );\nPROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 );\nPROVIDE ( rom_chip_v7_tx_init = 0x40004d18 );\nPROVIDE ( rom_clk_force_on_vit = 0x40003710 );\nPROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 );\nPROVIDE ( rom_dc_iq_est = 0x400055c8 );\nPROVIDE ( rom_disable_agc = 0x40002fa4 );\nPROVIDE ( rom_enable_agc = 0x40002fcc );\nPROVIDE ( rom_en_pwdet = 0x4000506c );\nPROVIDE ( rom_gen_rx_gain_table = 0x40003e3c );\nPROVIDE ( rom_get_data_sat = 0x4000312c );\nPROVIDE ( rom_get_fm_sar_dout = 0x40005204 );\nPROVIDE ( rom_get_power_db = 0x40005fc8 );\nPROVIDE ( rom_get_pwctrl_correct = 0x400065d4 );\nPROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc );\nPROVIDE ( rom_get_rf_gain_qdb = 0x40006290 );\nPROVIDE ( rom_get_sar_dout = 0x40006564 );\nPROVIDE ( rom_i2c_readReg = 0x40004148 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x400041c0 );\nPROVIDE ( rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x400041fc );\nPROVIDE ( rom_index_to_txbbgain = 0x40004df8 );\nPROVIDE ( rom_iq_est_disable = 0x40005590 );\nPROVIDE ( rom_iq_est_enable = 0x40005514 );\nPROVIDE ( rom_linear_to_db = 0x40005f64 );\nPROVIDE ( rom_loopback_mode_en = 0x400030f8 );\nPROVIDE ( rom_meas_tone_pwr_db = 0x40006004 );\nPROVIDE ( rom_mhz2ieee = 0x4000404c );\nPROVIDE ( rom_noise_floor_auto_set = 0x40003bdc );\nPROVIDE ( rom_pbus_debugmode = 0x40004458 );\nPROVIDE ( rom_pbus_force_mode = 0x40004270 );\nPROVIDE ( rom_pbus_force_test = 0x400043c0 );\nPROVIDE ( rom_pbus_rd = 0x40004414 );\nPROVIDE ( rom_pbus_rd_addr = 0x40004334 );\nPROVIDE ( rom_pbus_rd_shift = 0x40004374 );\nPROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 );\nPROVIDE ( rom_pbus_set_dco = 0x40004638 );\nPROVIDE ( rom_pbus_set_rxgain = 0x40004480 );\nPROVIDE ( rom_pbus_workmode = 0x4000446c );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 );\nPROVIDE ( rom_phy_disable_agc = 0x40002f6c );\nPROVIDE ( rom_phy_disable_cca = 0x40003000 );\nPROVIDE ( rom_phy_enable_agc = 0x40002f88 );\nPROVIDE ( rom_phy_enable_cca = 0x4000302c );\nPROVIDE ( rom_phy_freq_correct = 0x40004b44 );\nPROVIDE ( rom_phyFuns = 0x3ffae0c0 );\nPROVIDE ( rom_phy_get_noisefloor = 0x40003c2c );\nPROVIDE ( rom_phy_get_vdd33 = 0x4000642c );\nPROVIDE ( rom_pow_usr = 0x40003044 );\nPROVIDE ( rom_read_sar_dout = 0x400051c0 );\nPROVIDE ( rom_restart_cal = 0x400046e0 );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40006058 );\nPROVIDE ( rom_rfcal_rxiq = 0x40005b4c );\nPROVIDE ( rom_rfcal_txcap = 0x40005dec );\nPROVIDE ( rom_rfpll_reset = 0x40004680 );\nPROVIDE ( rom_rfpll_set_freq = 0x400047f8 );\nPROVIDE ( rom_rtc_mem_backup = 0x40003db4 );\nPROVIDE ( rom_rtc_mem_recovery = 0x40003df4 );\nPROVIDE ( rom_rx_gain_force = 0x4000351c );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 );\nPROVIDE ( rom_rxiq_get_mis = 0x400058e4 );\nPROVIDE ( rom_rxiq_set_reg = 0x40005a00 );\nPROVIDE ( rom_set_cal_rxdc = 0x400030b8 );\nPROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 );\nPROVIDE ( rom_set_channel_freq = 0x40004880 );\nPROVIDE ( rom_set_loopback_gain = 0x40003060 );\nPROVIDE ( rom_set_noise_floor = 0x40003d48 );\nPROVIDE ( rom_set_pbus_mem = 0x400031a4 );\nPROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 );\nPROVIDE ( rom_set_rxclk_en = 0x40003594 );\nPROVIDE ( rom_set_txcap_reg = 0x40005d50 );\nPROVIDE ( rom_set_txclk_en = 0x40003564 );\nPROVIDE ( rom_spur_coef_cfg = 0x40003ac8 );\nPROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 );\nPROVIDE ( rom_start_tx_tone = 0x400036b4 );\nPROVIDE ( rom_start_tx_tone_step = 0x400035d0 );\nPROVIDE ( rom_stop_tx_tone = 0x40003f98 );\nPROVIDE ( _rom_store = 0x4000d66c );\nPROVIDE ( _rom_store_table = 0x4000d4f8 );\nPROVIDE ( rom_target_power_add_backoff = 0x40006268 );\nPROVIDE ( rom_tx_atten_set_interp = 0x400061cc );\nPROVIDE ( rom_txbbgain_to_index = 0x40004dc0 );\nPROVIDE ( rom_txcal_work_mode = 0x4000510c );\nPROVIDE ( rom_txdc_cal_init = 0x40004e10 );\nPROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 );\nPROVIDE ( rom_txiq_cover = 0x4000538c );\nPROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc );\nPROVIDE ( rom_txiq_set_reg = 0x40005154 );\nPROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c );\nPROVIDE ( rom_txtone_linear_pwr = 0x40005290 );\nPROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 );\nPROVIDE ( rom_write_gain_mem = 0x4000348c );\nPROVIDE ( rom_write_rfpll_sdm = 0x40004740 );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( r_plf_funcs_p = 0x3ffb8360 );\nPROVIDE ( r_rf_rw_bt_init = 0x40054868 );\nPROVIDE ( r_rf_rw_init = 0x40054b0c );\nPROVIDE ( r_rf_rw_le_init = 0x400549d0 );\nPROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c );\nPROVIDE ( r_rwble_init = 0x40054bf4 );\nPROVIDE ( r_rwble_isr = 0x40054e08 );\nPROVIDE ( r_rwble_reset = 0x40054ce8 );\nPROVIDE ( r_rwble_sleep_check = 0x40054d78 );\nPROVIDE ( r_rwble_version = 0x40054dac );\nPROVIDE ( r_rwbt_init = 0x40055160 );\nPROVIDE ( r_rwbt_isr = 0x40055248 );\nPROVIDE ( r_rwbt_reset = 0x400551bc );\nPROVIDE ( r_rwbt_sleep_check = 0x4005577c );\nPROVIDE ( r_rwbt_sleep_enter = 0x400557a4 );\nPROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc );\nPROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc );\nPROVIDE ( r_rwbt_version = 0x4005520c );\nPROVIDE ( r_rwip_assert_err = 0x40055f88 );\nPROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc );\nPROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c );\nPROVIDE ( r_rwip_init = 0x4005595c );\nPROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 );\nPROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 );\nPROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 );\nPROVIDE ( r_rwip_reset = 0x40055ab8 );\nPROVIDE ( r_rwip_schedule = 0x40055b38 );\nPROVIDE ( r_rwip_sleep = 0x40055b5c );\nPROVIDE ( r_rwip_sleep_enable = 0x40055f30 );\nPROVIDE ( r_rwip_version = 0x40055b20 );\nPROVIDE ( r_rwip_wakeup = 0x40055dc4 );\nPROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c );\nPROVIDE ( r_rwip_wakeup_end = 0x40055e18 );\nPROVIDE ( r_rwip_wlcoex_set = 0x40055f60 );\nPROVIDE ( r_SHA_256 = 0x40013a90 );\nPROVIDE ( rwip_coex_cfg = 0x3ff9914c );\nPROVIDE ( rwip_priority = 0x3ff99159 );\nPROVIDE ( rwip_rf = 0x3ffbdb28 );\nPROVIDE ( rwip_rf_p_get = 0x400558f4 );\nPROVIDE ( r_XorKey = 0x400112c0 );\nPROVIDE ( sbrk = 0x400017f4 );\nPROVIDE ( _sbrk_r = 0x4000bce4 );\nPROVIDE ( __sccl = 0x4000c498 );\nPROVIDE ( __sclose = 0x400011b8 );\nPROVIDE ( __seofread = 0x40001148 );\nPROVIDE ( setjmp = 0x40056268 );\nPROVIDE ( setlocale = 0x40059568 );\nPROVIDE ( _setlocale_r = 0x4005950c );\nPROVIDE ( __sf_fake_stderr = 0x3ff96458 );\nPROVIDE ( __sf_fake_stdin = 0x3ff96498 );\nPROVIDE ( __sf_fake_stdout = 0x3ff96478 );\nPROVIDE ( __sflush_r = 0x400591e0 );\nPROVIDE ( __sfmoreglue = 0x40001dc8 );\nPROVIDE ( __sfp = 0x40001e90 );\nPROVIDE ( __sfp_lock_acquire = 0x40001e08 );\nPROVIDE ( __sfp_lock_release = 0x40001e14 );\nPROVIDE ( __sfputs_r = 0x40057790 );\nPROVIDE ( __sfvwrite_r = 0x4005893c );\nPROVIDE ( sha1_prf = 0x40060ae8 );\nPROVIDE ( sha1_vector = 0x40060b64 );\nPROVIDE ( sha256_prf = 0x40060d70 );\nPROVIDE ( sha256_vector = 0x40060e08 );\nPROVIDE ( sha_blk_bits = 0x3ff99290 );\nPROVIDE ( sha_blk_bits_bytes = 0x3ff99288 );\nPROVIDE ( sha_blk_hash_bytes = 0x3ff9928c );\nPROVIDE ( sig_matrix = 0x3ffae293 );\nPROVIDE ( __sinit = 0x40001e38 );\nPROVIDE ( __sinit_lock_acquire = 0x40001e20 );\nPROVIDE ( __sinit_lock_release = 0x40001e2c );\nPROVIDE ( sip_after_tx_complete = 0x4000b358 );\nPROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c );\nPROVIDE ( sip_get_ptr = 0x4000b34c );\nPROVIDE ( sip_get_state = 0x4000ae2c );\nPROVIDE ( sip_init_attach = 0x4000ae58 );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 );\nPROVIDE ( sip_install_rx_data_cb = 0x4000ae20 );\nPROVIDE ( sip_is_active = 0x4000b3c0 );\nPROVIDE ( sip_post_init = 0x4000aed8 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c );\nPROVIDE ( sip_send = 0x4000af54 );\nPROVIDE ( sip_to_host_chain_append = 0x4000aef8 );\nPROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 );\nPROVIDE ( slc_add_credits = 0x4000baf4 );\nPROVIDE ( slc_enable = 0x4000b64c );\nPROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 );\nPROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 );\nPROVIDE ( slc_has_pkt_to_host = 0x4000b5fc );\nPROVIDE ( slc_init_attach = 0x4000b918 );\nPROVIDE ( slc_init_credit = 0x4000badc );\nPROVIDE ( slc_reattach = 0x4000b62c );\nPROVIDE ( slc_send_to_host_chain = 0x4000b6a0 );\nPROVIDE ( slc_set_host_io_max_window = 0x4000b89c );\nPROVIDE ( slc_to_host_chain_recycle = 0x4000b758 );\nPROVIDE ( __smakebuf_r = 0x40059108 );\nPROVIDE ( specialModP256 = 0x4001600c );\nPROVIDE ( srand = 0x40001004 );\nPROVIDE ( __sread = 0x40001118 );\nPROVIDE ( __srefill_r = 0x400593d4 );\nPROVIDE ( __sseek = 0x40001184 );\nPROVIDE ( __ssprint_r = 0x40056ff8 );\nPROVIDE ( __ssputs_r = 0x40056f2c );\nPROVIDE ( __ssrefill_r = 0x40057fec );\nPROVIDE ( __stack = 0x3ffe3f20 );\nPROVIDE ( __stack_app = 0x3ffe7e30 );\nPROVIDE ( _stack_sentry = 0x3ffe1320 );\nPROVIDE ( _stack_sentry_app = 0x3ffe5230 );\nPROVIDE ( _start = 0x40000704 );\nPROVIDE ( start_tb_console = 0x4005a980 );\nPROVIDE ( _stat_r = 0x4000bcb4 );\nPROVIDE ( _stext = 0x40000560 );\nPROVIDE ( strcasecmp = 0x400011cc );\nPROVIDE ( strcasestr = 0x40001210 );\nPROVIDE ( strcat = 0x4000c518 );\nPROVIDE ( strchr = 0x4000c53c );\nPROVIDE ( strcmp = 0x40001274 );\nPROVIDE ( strcoll = 0x40001398 );\nPROVIDE ( strcpy = 0x400013ac );\nPROVIDE ( strcspn = 0x4000c558 );\nPROVIDE ( strdup = 0x4000143c );\nPROVIDE ( _strdup_r = 0x40001450 );\nPROVIDE ( strftime = 0x40059ab4 );\nPROVIDE ( strlcat = 0x40001470 );\nPROVIDE ( strlcpy = 0x4000c584 );\nPROVIDE ( strlen = 0x400014c0 );\nPROVIDE ( strlwr = 0x40001524 );\nPROVIDE ( strncasecmp = 0x40001550 );\nPROVIDE ( strncat = 0x4000c5c4 );\nPROVIDE ( strncmp = 0x4000c5f4 );\nPROVIDE ( strncpy = 0x400015d4 );\nPROVIDE ( strndup = 0x400016b0 );\nPROVIDE ( _strndup_r = 0x400016c4 );\nPROVIDE ( strnlen = 0x4000c628 );\nPROVIDE ( strrchr = 0x40001708 );\nPROVIDE ( strsep = 0x40001734 );\nPROVIDE ( strspn = 0x4000c648 );\nPROVIDE ( strstr = 0x4000c674 );\nPROVIDE ( __strtok_r = 0x4000c6a8 );\nPROVIDE ( strtok_r = 0x4000c70c );\nPROVIDE ( strtol = 0x4005681c );\nPROVIDE ( _strtol_r = 0x40056714 );\nPROVIDE ( strtoul = 0x4005692c );\nPROVIDE ( _strtoul_r = 0x40056834 );\nPROVIDE ( strupr = 0x4000174c );\nPROVIDE ( __subdf3 = 0x400026e4 );\nPROVIDE ( __submore = 0x40058f3c );\nPROVIDE ( __subsf3 = 0x400021d0 );\nPROVIDE ( SubtractBigHex256 = 0x40015bcc );\nPROVIDE ( SubtractBigHexMod256 = 0x40015e8c );\nPROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c );\nPROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 );\nPROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 );\nPROVIDE ( __subvdi3 = 0x40002d20 );\nPROVIDE ( __subvsi3 = 0x40002cf8 );\nPROVIDE ( _sungetc_r = 0x40057f6c );\nPROVIDE ( __swbuf = 0x40058cb4 );\nPROVIDE ( __swbuf_r = 0x40058bec );\nPROVIDE ( __swrite = 0x40001150 );\nPROVIDE ( __swsetup_r = 0x40058cc8 );\nPROVIDE ( sw_to_hw = 0x3ffb8d40 );\nPROVIDE ( syscall_table_ptr_app = 0x3ffae020 );\nPROVIDE ( syscall_table_ptr_pro = 0x3ffae024 );\nPROVIDE ( _system_r = 0x4000bc10 );\nPROVIDE ( tdefl_compress = 0x400600bc );\nPROVIDE ( tdefl_compress_buffer = 0x400607f4 );\nPROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 );\nPROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 );\nPROVIDE ( tdefl_get_adler32 = 0x400608d8 );\nPROVIDE ( tdefl_get_prev_return_status = 0x400608d0 );\nPROVIDE ( tdefl_init = 0x40060810 );\nPROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c );\nPROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 );\nPROVIDE ( time = 0x40001844 );\nPROVIDE ( __time_load_locale = 0x4000183c );\nPROVIDE ( times = 0x40001808 );\nPROVIDE ( _times_r = 0x4000bc40 );\nPROVIDE ( _timezone = 0x3ffae0a0 );\nPROVIDE ( tinfl_decompress = 0x4005ef30 );\nPROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 );\nPROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 );\nPROVIDE ( toascii = 0x4000c720 );\nPROVIDE ( tolower = 0x40001868 );\nPROVIDE ( toupper = 0x40001884 );\nPROVIDE ( __truncdfsf2 = 0x40002b90 );\nPROVIDE ( __tzcalc_limits = 0x400018a0 );\nPROVIDE ( __tz_lock = 0x40001a04 );\nPROVIDE ( _tzname = 0x3ffae030 );\nPROVIDE ( tzset = 0x40001a1c );\nPROVIDE ( _tzset_r = 0x40001a28 );\nPROVIDE ( __tz_unlock = 0x40001a10 );\nPROVIDE ( UartDev = 0x3ffe019c );\nPROVIDE ( __ucmpdi2 = 0x40063840 );\nPROVIDE ( __udivdi3 = 0x4000cff8 );\nPROVIDE ( __udivmoddi4 = 0x40064ab0 );\nPROVIDE ( __udivsi3 = 0x4000c7c8 );\nPROVIDE ( __udiv_w_sdiv = 0x40064aa8 );\nPROVIDE ( __umoddi3 = 0x4000d280 );\nPROVIDE ( __umodsi3 = 0x4000c7d0 );\nPROVIDE ( __umulsidi3 = 0x4000c7d8 );\nPROVIDE ( ungetc = 0x400590f4 );\nPROVIDE ( _ungetc_r = 0x40058fa0 );\nPROVIDE ( _unlink_r = 0x4000bc84 );\nPROVIDE ( __unorddf2 = 0x400637f4 );\nPROVIDE ( __unordsf2 = 0x40063478 );\nPROVIDE ( user_code_start = 0x3ffe0400 );\nPROVIDE ( utoa = 0x40056258 );\nPROVIDE ( __utoa = 0x400561f0 );\nPROVIDE ( veryBigHexP256 = 0x3ff9736c );\nPROVIDE ( wcrtomb = 0x40058920 );\nPROVIDE ( _wcrtomb_r = 0x400588d8 );\nPROVIDE ( __wctomb = 0x3ff96540 );\nPROVIDE ( _wctomb_r = 0x40058f14 );\nPROVIDE ( write = 0x4000181c );\nPROVIDE ( _write_r = 0x4000bd70 );\nPROVIDE ( xthal_bcopy = 0x4000c098 );\nPROVIDE ( xthal_copy123 = 0x4000c124 );\nPROVIDE ( xthal_get_ccompare = 0x4000c078 );\nPROVIDE ( xthal_get_ccount = 0x4000c050 );\nPROVIDE ( xthal_get_interrupt = 0x4000c1e4 );\nPROVIDE ( xthal_get_intread = 0x4000c1e4 );\nPROVIDE ( Xthal_intlevel = 0x3ff9c2b4 );\nPROVIDE ( xthal_memcpy = 0x4000c0bc );\nPROVIDE ( xthal_set_ccompare = 0x4000c058 );\nPROVIDE ( xthal_set_intclear = 0x4000c1ec );\nPROVIDE ( _xtos_set_intlevel = 0x4000bfdc );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( esp_rom_spiflash_config_param = 0x40063238 );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );\nPROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 );\nPROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 );\nPROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c );\nPROVIDE ( esp_rom_spiflash_select_qio_pins = 0x40061ddc );\nPROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );\n\n\/* \nThese functions are xtos-related (or call xtos-related functions) and do not play well \nwith multicore FreeRTOS. Where needed, we provide alternatives that are multicore\ncompatible. These functions also use a chunk of static RAM, by not using them we can\nallocate that RAM for general use.\n*\/\n\/*\nPROVIDE ( _DebugExceptionVector = 0x40000280 );\nPROVIDE ( _DoubleExceptionVector = 0x400003c0 );\nPROVIDE ( _KernelExceptionVector = 0x40000300 );\nPROVIDE ( _GeneralException = 0x40000e14 );\nPROVIDE ( _ResetHandler = 0x40000450 );\nPROVIDE ( _ResetVector = 0x40000400 );\nPROVIDE ( _UserExceptionVector = 0x40000340 );\nPROVIDE ( _NMIExceptionVector = 0x400002c0 );\nPROVIDE ( _WindowOverflow12 = 0x40000100 );\nPROVIDE ( _WindowOverflow4 = 0x40000000 );\nPROVIDE ( _WindowOverflow8 = 0x40000080 );\nPROVIDE ( _WindowUnderflow12 = 0x40000140 );\nPROVIDE ( _WindowUnderflow4 = 0x40000040 );\nPROVIDE ( _WindowUnderflow8 = 0x400000c0 );\nPROVIDE ( _Level2FromVector = 0x40000954 );\nPROVIDE ( _Level3FromVector = 0x40000a28 );\nPROVIDE ( _Level4FromVector = 0x40000af8 );\nPROVIDE ( _Level5FromVector = 0x40000c68 );\nPROVIDE ( _Level2Vector = 0x40000180 );\nPROVIDE ( _Level3Vector = 0x400001c0 );\nPROVIDE ( _Level4Vector = 0x40000200 );\nPROVIDE ( _Level5Vector = 0x40000240 );\nPROVIDE ( _LevelOneInterrupt = 0x40000835 );\nPROVIDE ( _SyscallException = 0x400007cf );\nPROVIDE ( _xtos_alloca_handler = 0x40000010 );\nPROVIDE ( _xtos_cause3_handler = 0x40000dd8 );\nPROVIDE ( _xtos_c_handler_table = 0x3ffe0548 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 );\nPROVIDE ( _xtos_enabled = 0x3ffe0650 );\nPROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 );\nPROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 );\nPROVIDE ( _xtos_interrupt_table = 0x3ffe0658 );\nPROVIDE ( _xtos_ints_off = 0x4000bfac );\nPROVIDE ( _xtos_ints_on = 0x4000bf88 );\nPROVIDE ( _xtos_intstruct = 0x3ffe0650 );\nPROVIDE ( _xtos_l1int_handler = 0x40000814 );\nPROVIDE ( _xtos_p_none = 0x4000bfd4 );\nPROVIDE ( _xtos_restore_intlevel = 0x40000928 );\nPROVIDE ( _xtos_return_from_exc = 0x4000c034 );\nPROVIDE ( _xtos_set_exception_handler = 0x4000074c );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 );\nPROVIDE ( _xtos_set_vpri = 0x40000934 );\nPROVIDE ( _xtos_syscall_handler = 0x40000790 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000c024 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c );\nPROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 );\nPROVIDE ( ets_intr_count = 0x3ffe03fc );\n*\/\n\n\/* These functions are part of the UART downloader but also contain general UART functions. *\/\nPROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x40008860 );\nPROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 );\nPROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec );\nPROVIDE ( MemDwnLdStartMsgProc = 0x40008948 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc );\nPROVIDE ( MemPacketSendReqMsgProc = 0x40008978 );\nPROVIDE ( uart_baudrate_detect = 0x40009034 );\nPROVIDE ( uart_buff_switch = 0x400093c0 );\nPROVIDE ( UartConnCheck = 0x40008738 );\nPROVIDE ( UartConnectProc = 0x40008a04 );\nPROVIDE ( UartDwnLdProc = 0x40008ce8 );\nPROVIDE ( UartRegReadProc = 0x40008a58 );\nPROVIDE ( UartRegWriteProc = 0x40008a14 );\nPROVIDE ( UartSetBaudProc = 0x40008aac );\nPROVIDE ( UartSpiAttachProc = 0x40008a6c );\nPROVIDE ( UartSpiReadProc = 0x40008a80 );\nPROVIDE ( VerifyFlashMd5Proc = 0x40008c44 );\nPROVIDE ( GetUartDevice = 0x40009598 );\nPROVIDE ( RcvMsg = 0x4000954c );\nPROVIDE ( SendMsg = 0x40009384 );\nPROVIDE ( UartGetCmdLn = 0x40009564 );\nPROVIDE ( UartRxString = 0x400092fc );\nPROVIDE ( Uart_Init = 0x40009120 );\nPROVIDE ( recv_packet = 0x40009424 );\nPROVIDE ( send_packet = 0x40009340 );\nPROVIDE ( uartAttach = 0x40008fd0 );\nPROVIDE ( uart_div_modify = 0x400090cc );\nPROVIDE ( uart_rx_intr_handler = 0x40008f4c );\nPROVIDE ( uart_rx_one_char = 0x400092d0 );\nPROVIDE ( uart_rx_one_char_block = 0x400092a4 );\nPROVIDE ( uart_rx_readbuff = 0x40009394 );\nPROVIDE ( uart_tx_flush = 0x40009258 );\nPROVIDE ( uart_tx_one_char = 0x40009200 );\nPROVIDE ( uart_tx_one_char2 = 0x4000922c );\nPROVIDE ( uart_tx_switch = 0x40009028 );\nPROVIDE ( uart_tx_wait_idle = 0x40009278 );\n\n\n\/*\nThese functions are part of the ROM GPIO driver. We do not use them; the provided esp-idf functions\nreplace them and this way we can re-use the fixed RAM addresses these routines need.\n*\/\n\/* <-- So you don't read over it: This comment disables the next lines.\nPROVIDE ( gpio_init = 0x40009c20 );\nPROVIDE ( gpio_intr_ack = 0x40009dd4 );\nPROVIDE ( gpio_intr_ack_high = 0x40009e1c );\nPROVIDE ( gpio_intr_handler_register = 0x40009e6c );\nPROVIDE ( gpio_intr_pending = 0x40009cec );\nPROVIDE ( gpio_intr_pending_high = 0x40009cf8 );\nPROVIDE ( gpio_pending_mask = 0x3ffe0038 );\nPROVIDE ( gpio_pending_mask_high = 0x3ffe0044 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40009d04 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c );\nPROVIDE ( gpio_register_get = 0x40009cbc );\nPROVIDE ( gpio_register_set = 0x40009bbc );\n*\/\n\/* These are still part of that driver, but have been verified not to use static RAM, so they can be used. *\/\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( gpio_input_get = 0x40009b88 );\nPROVIDE ( gpio_input_get_high = 0x40009b9c );\nPROVIDE ( gpio_matrix_in = 0x40009edc );\nPROVIDE ( gpio_matrix_out = 0x40009f0c );\nPROVIDE ( gpio_pad_select_gpio = 0x40009fdc );\nPROVIDE ( gpio_pad_set_drv = 0x4000a11c );\nPROVIDE ( gpio_pad_pulldown = 0x4000a348 );\nPROVIDE ( gpio_pad_pullup = 0x4000a22c );\nPROVIDE ( gpio_pad_hold = 0x4000a734 );\nPROVIDE ( gpio_pad_unhold = 0x4000a484 );\n\n\/*\nThese functions are part of the non-os kernel (etsc).\n*\/\nPROVIDE ( ets_aes_crypt = 0x4005c9b8 );\nPROVIDE ( ets_aes_disable = 0x4005c8f8 );\nPROVIDE ( ets_aes_enable = 0x4005c8cc );\nPROVIDE ( ets_aes_set_endian = 0x4005c928 );\nPROVIDE ( ets_aes_setkey_dec = 0x4005c994 );\nPROVIDE ( ets_aes_setkey_enc = 0x4005c97c );\nPROVIDE ( ets_bigint_disable = 0x4005c4e0 );\nPROVIDE ( ets_bigint_enable = 0x4005c498 );\nPROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 );\nPROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 );\nPROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 );\nPROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c );\nPROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 );\nPROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc );\nPROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 );\nPROVIDE ( ets_bigint_mult_prepare = 0x4005c630 );\nPROVIDE ( ets_bigint_wait_finish = 0x4005c520 );\nPROVIDE ( ets_post = 0x4000673c );\nPROVIDE ( ets_run = 0x400066bc );\nPROVIDE ( ets_set_idle_cb = 0x40006674 );\nPROVIDE ( ets_task = 0x40006688 );\nPROVIDE ( ets_efuse_get_8M_clock = 0x40008710 );\nPROVIDE ( ets_efuse_get_spiconfig = 0x40008658 );\nPROVIDE ( ets_efuse_program_op = 0x40008628 );\nPROVIDE ( ets_efuse_read_op = 0x40008600 );\nPROVIDE ( ets_intr_lock = 0x400067b0 );\nPROVIDE ( ets_intr_unlock = 0x400067c4 );\nPROVIDE ( ets_isr_attach = 0x400067ec );\nPROVIDE ( ets_isr_mask = 0x400067fc );\nPROVIDE ( ets_isr_unmask = 0x40006808 );\nPROVIDE ( ets_waiti0 = 0x400067d8 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( check_pos = 0x400068b8 );\nPROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( ets_set_startup_callback = 0x4000688c );\nPROVIDE ( ets_set_user_start = 0x4000687c );\nPROVIDE ( ets_unpack_flash_code = 0x40007018 );\nPROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c );\nPROVIDE ( rom_main = 0x400076c4 );\nPROVIDE ( ets_write_char_uart = 0x40007cf8 );\nPROVIDE ( ets_install_putc1 = 0x40007d18 );\nPROVIDE ( ets_install_putc2 = 0x40007d38 );\nPROVIDE ( ets_install_uart_printf = 0x40007d28 );\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( rtc_boot_control = 0x4000821c );\nPROVIDE ( rtc_get_reset_reason = 0x400081d4 );\nPROVIDE ( rtc_get_wakeup_cause = 0x400081f4 );\nPROVIDE ( rtc_select_apb_bridge = 0x40008288 );\nPROVIDE ( set_rtc_memory_crc = 0x40008208 );\nPROVIDE ( software_reset = 0x4000824c );\nPROVIDE ( software_reset_cpu = 0x40008264 );\nPROVIDE ( ets_secure_boot_check = 0x4005cb40 );\nPROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 );\nPROVIDE ( ets_secure_boot_check_start = 0x4005cbcc );\nPROVIDE ( ets_secure_boot_finish = 0x4005ca84 );\nPROVIDE ( ets_secure_boot_hash = 0x4005cad4 );\nPROVIDE ( ets_secure_boot_obtain = 0x4005cb14 );\nPROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 );\nPROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 );\nPROVIDE ( ets_secure_boot_start = 0x4005ca34 );\nPROVIDE ( ets_sha_disable = 0x4005c0a8 );\nPROVIDE ( ets_sha_enable = 0x4005c07c );\nPROVIDE ( ets_sha_finish = 0x4005c104 );\nPROVIDE ( ets_sha_init = 0x4005c0d4 );\nPROVIDE ( ets_sha_update = 0x4005c2a0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( ets_get_cpu_frequency = 0x4000855c );\nPROVIDE ( ets_get_detected_xtal_freq = 0x40008588 );\nPROVIDE ( ets_get_xtal_scale = 0x4000856c );\nPROVIDE ( ets_timer_arm = 0x40008368 );\nPROVIDE ( ets_timer_arm_us = 0x400083ac );\nPROVIDE ( ets_timer_disarm = 0x400083ec );\nPROVIDE ( ets_timer_done = 0x40008428 );\nPROVIDE ( ets_timer_handler_isr = 0x40008454 );\nPROVIDE ( ets_timer_init = 0x400084e8 );\nPROVIDE ( ets_timer_setfn = 0x40008350 );\nPROVIDE ( ets_update_cpu_frequency_rom = 0x40008550 );  \/* Updates g_ticks_per_us on the current CPU only; not on the other core *\/\n\n\/* Following are static data, but can be used, not generated by script <<<<< btdm data *\/\nPROVIDE ( ld_acl_env = 0x3ffb8258 );\nPROVIDE ( ld_active_ch_map = 0x3ffb8334 );\nPROVIDE ( ld_bcst_acl_env = 0x3ffb8274 );\nPROVIDE ( ld_csb_rx_env = 0x3ffb8278 );\nPROVIDE ( ld_csb_tx_env = 0x3ffb827c );\nPROVIDE ( ld_env = 0x3ffb9510 );\nPROVIDE ( ld_fm_env = 0x3ffb8284 );\nPROVIDE ( ld_inq_env = 0x3ffb82e4 );\nPROVIDE ( ld_iscan_env = 0x3ffb82e8 );\nPROVIDE ( ld_page_env = 0x3ffb82f0 );\nPROVIDE ( ld_pca_env = 0x3ffb82f4 );\nPROVIDE ( ld_pscan_env = 0x3ffb8308 );\nPROVIDE ( ld_sched_env = 0x3ffb830c );\nPROVIDE ( ld_sched_params = 0x3ffb96c0 );\nPROVIDE ( ld_sco_env = 0x3ffb824c );\nPROVIDE ( ld_sscan_env = 0x3ffb832c );\nPROVIDE ( ld_strain_env = 0x3ffb8330 );\nPROVIDE ( LM_Sniff = 0x3ffb8230 );\nPROVIDE ( LM_SniffSubRate = 0x3ffb8214 );\nPROVIDE ( prbs_64bytes = 0x3ff98992 );\n\/* Above are static data, but can be used, not generated by script >>>>> btdm data *\/\n\n","old_contents":"\/*\nESP32 ROM address table\nGenerated for ROM with MD5sum:\nab8282ae908fe9e7a63fb2a4ac2df013  ..\/..\/rom_image\/prorom.elf\n*\/\nPROVIDE ( abort = 0x4000bba4 );\nPROVIDE ( abs = 0x40056340 );\nPROVIDE ( __absvdi2 = 0x4006387c );\nPROVIDE ( __absvsi2 = 0x40063868 );\nPROVIDE ( Add2SelfBigHex256 = 0x40015b7c );\nPROVIDE ( AddBigHex256 = 0x40015b28 );\nPROVIDE ( AddBigHexModP256 = 0x40015c98 );\nPROVIDE ( __adddf3 = 0x40002590 );\nPROVIDE ( AddP256 = 0x40015c74 );\nPROVIDE ( AddPdiv2_256 = 0x40015ce0 );\nPROVIDE ( __addsf3 = 0x400020e8 );\nPROVIDE ( __addvdi3 = 0x40002cbc );\nPROVIDE ( __addvsi3 = 0x40002c98 );\nPROVIDE ( aes_128_cbc_decrypt = 0x4005cc7c );\nPROVIDE ( aes_128_cbc_encrypt = 0x4005cc18 );\nPROVIDE ( aes_unwrap = 0x4005ccf0 );\nPROVIDE ( app_gpio_arg = 0x3ffe003c );\nPROVIDE ( app_gpio_handler = 0x3ffe0040 );\nPROVIDE ( __ascii_wctomb = 0x40058ef0 );\nPROVIDE ( asctime = 0x40059588 );\nPROVIDE ( asctime_r = 0x40000ec8 );\nPROVIDE ( __ashldi3 = 0x4000c818 );\nPROVIDE ( __ashrdi3 = 0x4000c830 );\nPROVIDE ( atoi = 0x400566c4 );\nPROVIDE ( _atoi_r = 0x400566d4 );\nPROVIDE ( atol = 0x400566ec );\nPROVIDE ( _atol_r = 0x400566fc );\nPROVIDE ( base64_decode = 0x4005ced8 );\nPROVIDE ( base64_encode = 0x4005cdbc );\nPROVIDE ( BasePoint_x_256 = 0x3ff97488 );\nPROVIDE ( BasePoint_y_256 = 0x3ff97468 );\nPROVIDE ( bigHexInversion256 = 0x400168f0 );\nPROVIDE ( bigHexP256 = 0x3ff973bc );\nPROVIDE ( __bswapdi2 = 0x400649c4 );\nPROVIDE ( __bswapsi2 = 0x4006499c );\nPROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c );\nPROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 );\nPROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 );\nPROVIDE ( btdm_r_data_init = 0x4001002c );\nPROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 );\nPROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 );\nPROVIDE ( btdm_r_ip_func_p_set = 0x40019afc );\nPROVIDE ( btdm_r_modules_func_p_get = 0x4005427c );\nPROVIDE ( btdm_r_modules_func_p_set = 0x40054270 );\nPROVIDE ( btdm_r_plf_func_p_set = 0x40054288 );\nPROVIDE ( bt_util_buf_env = 0x3ffb8bd4 );\nPROVIDE ( bzero = 0x4000c1f4 );\nPROVIDE ( cache_flash_mmu_set_rom = 0x400095e0 );\nPROVIDE ( Cache_Flush_rom = 0x40009a14 );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\nPROVIDE ( cache_sram_mmu_set_rom = 0x400097f4 );\n\/* This is static function, but can be used, not generated by script*\/\nPROVIDE ( calc_rtc_memory_crc = 0x40008170 );\nPROVIDE ( calloc = 0x4000bee4 );\nPROVIDE ( _calloc_r = 0x4000bbf8 );\nPROVIDE ( _cleanup = 0x40001df8 );\nPROVIDE ( _cleanup_r = 0x40001d48 );\nPROVIDE ( __clear_cache = 0x40063860 );\nPROVIDE ( close = 0x40001778 );\nPROVIDE ( _close_r = 0x4000bd3c );\nPROVIDE ( __clrsbdi2 = 0x40064a38 );\nPROVIDE ( __clrsbsi2 = 0x40064a20 );\nPROVIDE ( __clzdi2 = 0x4000ca50 );\nPROVIDE ( __clzsi2 = 0x4000c7e8 );\nPROVIDE ( __cmpdi2 = 0x40063820 );\nPROVIDE ( co_default_bdaddr = 0x3ffae704 );\nPROVIDE ( co_null_bdaddr = 0x3ffb80e0 );\nPROVIDE ( co_sca2ppm = 0x3ff971e8 );\nPROVIDE ( crc16_be = 0x4005d09c );\nPROVIDE ( crc16_le = 0x4005d05c );\nPROVIDE ( crc32_be = 0x4005d024 );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( crc8_be = 0x4005d114 );\nPROVIDE ( crc8_le = 0x4005d0e0 );\nPROVIDE ( creat = 0x40000e8c );\nPROVIDE ( ctime = 0x400595b0 );\nPROVIDE ( ctime_r = 0x400595c4 );\nPROVIDE ( _ctype_ = 0x3ff96354 );\nPROVIDE ( __ctype_ptr__ = 0x3ff96350 );\nPROVIDE ( __ctzdi2 = 0x4000ca64 );\nPROVIDE ( __ctzsi2 = 0x4000c7f0 );\nPROVIDE ( _data_end_rom = 0x4000d5c8 );\nPROVIDE ( _data_end_btdm_rom = 0x4000d4f8 );\nPROVIDE ( _data_start_rom = 0x4000d4f8 );\nPROVIDE ( _data_start_btdm_rom = 0x4000d4f4 );\nPROVIDE ( _data_start_btdm = 0x3ffae6e0);\nPROVIDE ( _data_end_btdm = 0x3ffaff10);\nPROVIDE ( _bss_start_btdm = 0x3ffb8000);\nPROVIDE ( _bss_end_btdm = 0x3ffbff70);\nPROVIDE ( _daylight = 0x3ffae0a4 );\nPROVIDE ( dbg_default_handler = 0x3ff97218 );\nPROVIDE ( dbg_state = 0x3ffb8d5d );\nPROVIDE ( DebugE256PublicKey_x = 0x3ff97428 );\nPROVIDE ( DebugE256PublicKey_y = 0x3ff97408 );\nPROVIDE ( DebugE256SecretKey = 0x3ff973e8 );\nPROVIDE ( debug_timer = 0x3ffe042c );\nPROVIDE ( debug_timerfn = 0x3ffe0430 );\nPROVIDE ( dh_group14_generator = 0x3ff9ac60 );\nPROVIDE ( dh_group14_prime = 0x3ff9ab60 );\nPROVIDE ( dh_group15_generator = 0x3ff9ab5f );\nPROVIDE ( dh_group15_prime = 0x3ff9a9df );\nPROVIDE ( dh_group16_generator = 0x3ff9a9de );\nPROVIDE ( dh_group16_prime = 0x3ff9a7de );\nPROVIDE ( dh_group17_generator = 0x3ff9a7dd );\nPROVIDE ( dh_group17_prime = 0x3ff9a4dd );\nPROVIDE ( dh_group18_generator = 0x3ff9a4dc );\nPROVIDE ( dh_group18_prime = 0x3ff9a0dc );\nPROVIDE ( dh_group1_generator = 0x3ff9ae03 );\nPROVIDE ( dh_group1_prime = 0x3ff9ada3 );\nPROVIDE ( dh_group2_generator = 0x3ff9ada2 );\nPROVIDE ( dh_group2_prime = 0x3ff9ad22 );\nPROVIDE ( dh_group5_generator = 0x3ff9ad21 );\nPROVIDE ( dh_group5_prime = 0x3ff9ac61 );\nPROVIDE ( div = 0x40056348 );\nPROVIDE ( __divdc3 = 0x40064460 );\nPROVIDE ( __divdf3 = 0x40002954 );\nPROVIDE ( __divdi3 = 0x4000ca84 );\nPROVIDE ( __divsc3 = 0x40064200 );\nPROVIDE ( __divsf3 = 0x4000234c );\nPROVIDE ( __divsi3 = 0x4000c7b8 );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );\nPROVIDE ( __dummy_lock = 0x4000c728 );\nPROVIDE ( __dummy_lock_try = 0x4000c730 );\nPROVIDE ( ecc_env = 0x3ffb8d60 );\nPROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 );\nPROVIDE ( em_buf_env = 0x3ffb8d74 );\nPROVIDE ( environ = 0x3ffae0b4 );\nPROVIDE ( __env_lock = 0x40001fd4 );\nPROVIDE ( __env_unlock = 0x40001fe0 );\nPROVIDE ( __eqdf2 = 0x400636a8 );\nPROVIDE ( __eqsf2 = 0x40063374 );\nPROVIDE ( esp_crc8 = 0x4005d144 );\nPROVIDE ( _etext = 0x4000d66c );\nPROVIDE ( ets_readySet_ = 0x3ffe01f0 );\nPROVIDE ( ets_startup_callback = 0x3ffe0404 );\nPROVIDE ( exc_cause_table = 0x3ff991d0 );\nPROVIDE ( _exit_r = 0x4000bd28 );\nPROVIDE ( __extendsfdf2 = 0x40002c34 );\nPROVIDE ( fclose = 0x400020ac );\nPROVIDE ( _fclose_r = 0x40001fec );\nPROVIDE ( fflush = 0x40059394 );\nPROVIDE ( _fflush_r = 0x40059320 );\nPROVIDE ( __ffsdi2 = 0x4000ca2c );\nPROVIDE ( __ffssi2 = 0x4000c804 );\nPROVIDE ( _findenv_r = 0x40001f44 );\nPROVIDE ( __fixdfdi = 0x40002ac4 );\nPROVIDE ( __fixdfsi = 0x40002a78 );\nPROVIDE ( __fixsfdi = 0x4000244c );\nPROVIDE ( __fixsfsi = 0x4000240c );\nPROVIDE ( __fixunsdfsi = 0x40002b30 );\nPROVIDE ( __fixunssfdi = 0x40002504 );\nPROVIDE ( __fixunssfsi = 0x400024ac );\nPROVIDE ( __floatdidf = 0x4000c988 );\nPROVIDE ( __floatdisf = 0x4000c8c0 );\nPROVIDE ( __floatsidf = 0x4000c944 );\nPROVIDE ( __floatsisf = 0x4000c870 );\nPROVIDE ( __floatundidf = 0x4000c978 );\nPROVIDE ( __floatundisf = 0x4000c8b0 );\nPROVIDE ( __floatunsidf = 0x4000c938 );\nPROVIDE ( __floatunsisf = 0x4000c864 );\nPROVIDE ( __fp_lock_all = 0x40001f1c );\nPROVIDE ( __fp_unlock_all = 0x40001f30 );\nPROVIDE ( fputwc = 0x40058ea8 );\nPROVIDE ( __fputwc = 0x40058da0 );\nPROVIDE ( _fputwc_r = 0x40058e4c );\nPROVIDE ( free = 0x4000beb8 );\nPROVIDE ( _free_r = 0x4000bbcc );\nPROVIDE ( _fstat_r = 0x4000bccc );\nPROVIDE ( _fwalk = 0x4000c738 );\nPROVIDE ( _fwalk_reent = 0x4000c770 );\nPROVIDE ( __gcc_bcmp = 0x40064a70 );\nPROVIDE ( __gedf2 = 0x40063768 );\nPROVIDE ( __gesf2 = 0x4006340c );\nPROVIDE ( __get_current_time_locale = 0x40001834 );\nPROVIDE ( _getenv_r = 0x40001fbc );\nPROVIDE ( _getpid_r = 0x4000bcfc );\nPROVIDE ( __getreent = 0x4000be8c );\nPROVIDE ( _gettimeofday_r = 0x4000bc58 );\nPROVIDE ( __gettzinfo = 0x40001fcc );\nPROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 );\nPROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 );\nPROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c );\nPROVIDE ( _global_impure_ptr = 0x3ffae0b0 );\nPROVIDE ( gmtime = 0x40059848 );\nPROVIDE ( gmtime_r = 0x40059868 );\nPROVIDE ( g_phyFuns_instance = 0x3ffae0c4 );\nPROVIDE ( g_rom_flashchip = 0x3ffae270 );\nPROVIDE ( __gtdf2 = 0x400636dc );\nPROVIDE ( __gtsf2 = 0x400633a0 );\nPROVIDE ( gTxMsg = 0x3ffe0050 );\nPROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 );\nPROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 );\nPROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c );\nPROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 );\nPROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 );\nPROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c );\nPROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 );\nPROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 );\nPROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 );\nPROVIDE ( hci_command_handler = 0x4004c928 );\nPROVIDE ( hci_env = 0x3ffb9350 );\nPROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c );\nPROVIDE ( hci_evt_desc_tab = 0x3ff9751c );\nPROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 );\nPROVIDE ( hci_fc_env = 0x3ffb9340 );\nPROVIDE ( hmac_md5 = 0x4005d264 );\nPROVIDE ( hmac_md5_vector = 0x4005d17c );\nPROVIDE ( hmac_sha1 = 0x40060acc );\nPROVIDE ( hmac_sha1_vector = 0x400609e4 );\nPROVIDE ( hmac_sha256 = 0x40060d58 );\nPROVIDE ( hmac_sha256_vector = 0x40060c84 );\nPROVIDE ( isalnum = 0x40000f04 );\nPROVIDE ( isalpha = 0x40000f18 );\nPROVIDE ( isascii = 0x4000c20c );\nPROVIDE ( _isatty_r = 0x40000ea0 );\nPROVIDE ( isblank = 0x40000f2c );\nPROVIDE ( iscntrl = 0x40000f50 );\nPROVIDE ( isdigit = 0x40000f64 );\nPROVIDE ( isgraph = 0x40000f94 );\nPROVIDE ( islower = 0x40000f78 );\nPROVIDE ( isprint = 0x40000fa8 );\nPROVIDE ( ispunct = 0x40000fc0 );\nPROVIDE ( isspace = 0x40000fd4 );\nPROVIDE ( isupper = 0x40000fe8 );\nPROVIDE ( itoa = 0x400566b4 );\nPROVIDE ( __itoa = 0x40056678 );\nPROVIDE ( jd_decomp = 0x400613e8 );\nPROVIDE ( jd_prepare = 0x40060fa8 );\nPROVIDE ( ke_env = 0x3ffb93cc );\nPROVIDE ( _kill_r = 0x4000bd10 );\nPROVIDE ( labs = 0x40056370 );\nPROVIDE ( lb_default_handler = 0x3ff982b8 );\nPROVIDE ( lb_default_state_tab_p_get = 0x4001c198 );\nPROVIDE ( lb_env = 0x3ffb9424 );\nPROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c );\nPROVIDE ( lb_state = 0x3ffb94e8 );\nPROVIDE ( lc_default_handler = 0x3ff98648 );\nPROVIDE ( lc_default_state_tab_p_get = 0x4002f494 );\nPROVIDE ( lc_env = 0x3ffb94ec );\nPROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 );\nPROVIDE ( lc_state = 0x3ffb9508 );\nPROVIDE ( ld_acl_br_sizes = 0x3ff98a2a );\nPROVIDE ( ld_acl_br_types = 0x3ff98a36 );\nPROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 );\nPROVIDE ( ld_acl_edr_types = 0x3ff98a22 );\nPROVIDE ( ld_env = 0x3ffb9510 );\nPROVIDE ( ldiv = 0x40056378 );\nPROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c );\nPROVIDE ( ld_sched_params = 0x3ffb96c0 );\nPROVIDE ( ld_sync_train_channels = 0x3ff98a3c );\nPROVIDE ( __ledf2 = 0x40063704 );\nPROVIDE ( __lesf2 = 0x400633c0 );\nPROVIDE ( _link_r = 0x4000bc9c );\nPROVIDE ( llc_default_handler = 0x3ff98b3c );\nPROVIDE ( llc_default_state_tab_p_get = 0x40046058 );\nPROVIDE ( llc_env = 0x3ffb96d0 );\nPROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 );\nPROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 );\nPROVIDE ( llc_hci_command_handler = 0x40042360 );\nPROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 );\nPROVIDE ( llc_state = 0x3ffb96f8 );\nPROVIDE ( lldesc_build_chain = 0x4000a850 );\nPROVIDE ( lldesc_num2link = 0x4000a948 );\nPROVIDE ( lldesc_set_owner = 0x4000a974 );\nPROVIDE ( lld_evt_env = 0x3ffb9704 );\nPROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 );\nPROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 );\nPROVIDE ( LLM_AA_CT1 = 0x3ff98d8a );\nPROVIDE ( LLM_AA_CT2 = 0x3ff98d88 );\nPROVIDE ( llm_default_handler = 0x3ff98d80 );\nPROVIDE ( llm_default_state_tab_p_get = 0x4004e718 );\nPROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 );\nPROVIDE ( llm_le_env = 0x3ffb976c );\nPROVIDE ( llm_local_cmds = 0x3ff98d38 );\nPROVIDE ( llm_local_data_len_values = 0x3ff98d1c );\nPROVIDE ( llm_local_le_feats = 0x3ff98d30 );\nPROVIDE ( llm_local_le_states = 0x3ff98d28 );\nPROVIDE ( llm_state = 0x3ffb985c );\nPROVIDE ( lm_default_handler = 0x3ff990e0 );\nPROVIDE ( lm_default_state_tab_p_get = 0x40054268 );\nPROVIDE ( lm_env = 0x3ffb9860 );\nPROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c );\nPROVIDE ( lm_local_supp_feats = 0x3ff990ee );\nPROVIDE ( lm_n_page_tab = 0x3ff990e8 );\nPROVIDE ( lmp_desc_tab = 0x3ff96e6c );\nPROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c );\nPROVIDE ( lm_state = 0x3ffb9a1c );\nPROVIDE ( __locale_charset = 0x40059540 );\nPROVIDE ( __locale_cjk_lang = 0x40059558 );\nPROVIDE ( localeconv = 0x4005957c );\nPROVIDE ( _localeconv_r = 0x40059560 );\nPROVIDE ( __locale_mb_cur_max = 0x40059548 );\nPROVIDE ( __locale_msgcharset = 0x40059550 );\nPROVIDE ( localtime = 0x400595dc );\nPROVIDE ( localtime_r = 0x400595fc );\nPROVIDE ( _lock_acquire = 0x4000be14 );\nPROVIDE ( _lock_acquire_recursive = 0x4000be28 );\nPROVIDE ( _lock_close = 0x4000bdec );\nPROVIDE ( _lock_close_recursive = 0x4000be00 );\nPROVIDE ( _lock_init = 0x4000bdc4 );\nPROVIDE ( _lock_init_recursive = 0x4000bdd8 );\nPROVIDE ( _lock_release = 0x4000be64 );\nPROVIDE ( _lock_release_recursive = 0x4000be78 );\nPROVIDE ( _lock_try_acquire = 0x4000be3c );\nPROVIDE ( _lock_try_acquire_recursive = 0x4000be50 );\nPROVIDE ( longjmp = 0x400562cc );\nPROVIDE ( _lseek_r = 0x4000bd8c );\nPROVIDE ( __lshrdi3 = 0x4000c84c );\nPROVIDE ( __ltdf2 = 0x40063790 );\nPROVIDE ( __ltsf2 = 0x4006342c );\nPROVIDE ( malloc = 0x4000bea0 );\nPROVIDE ( _malloc_r = 0x4000bbb4 );\nPROVIDE ( maxSecretKey_256 = 0x3ff97448 );\nPROVIDE ( __mb_cur_max = 0x3ff96530 );\nPROVIDE ( MD5Final = 0x4005db1c );\nPROVIDE ( MD5Init = 0x4005da7c );\nPROVIDE ( MD5Update = 0x4005da9c );\nPROVIDE ( md5_vector = 0x4005db80 );\nPROVIDE ( memccpy = 0x4000c220 );\nPROVIDE ( memchr = 0x4000c244 );\nPROVIDE ( memcmp = 0x4000c260 );\nPROVIDE ( memcpy = 0x4000c2c8 );\nPROVIDE ( memmove = 0x4000c3c0 );\nPROVIDE ( memrchr = 0x4000c400 );\nPROVIDE ( memset = 0x4000c44c );\nPROVIDE ( mktime = 0x4005a5e8 );\nPROVIDE ( mmu_init = 0x400095a4 );\nPROVIDE ( __moddi3 = 0x4000cd4c );\nPROVIDE ( __modsi3 = 0x4000c7c0 );\nPROVIDE ( __month_lengths = 0x3ff9609c );\nPROVIDE ( __muldc3 = 0x40063bf4 );\nPROVIDE ( __muldf3 = 0x4006358c );\nPROVIDE ( __muldi3 = 0x4000c9fc );\nPROVIDE ( __mulsc3 = 0x40063934 );\nPROVIDE ( __mulsf3 = 0x400632c8 );\nPROVIDE ( __mulsi3 = 0x4000c7b0 );\nPROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 );\nPROVIDE ( MultiplyBigHexModP256 = 0x400160b8 );\nPROVIDE ( MultiplyByU32ModP256 = 0x40015fdc );\nPROVIDE ( multofup = 0x4000ab8c );\nPROVIDE ( __mulvdi3 = 0x40002d78 );\nPROVIDE ( __mulvsi3 = 0x40002d60 );\nPROVIDE ( mz_adler32 = 0x4005edbc );\nPROVIDE ( mz_crc32 = 0x4005ee88 );\nPROVIDE ( mz_free = 0x4005eed4 );\nPROVIDE ( __nedf2 = 0x400636a8 );\nPROVIDE ( __negdf2 = 0x400634a0 );\nPROVIDE ( __negdi2 = 0x4000ca14 );\nPROVIDE ( __negsf2 = 0x400020c0 );\nPROVIDE ( __negvdi2 = 0x40002e98 );\nPROVIDE ( __negvsi2 = 0x40002e78 );\nPROVIDE ( __nesf2 = 0x40063374 );\nPROVIDE ( notEqual256 = 0x40015b04 );\nPROVIDE ( __nsau_data = 0x3ff96544 );\nPROVIDE ( one_bits = 0x3ff971f8 );\nPROVIDE ( open = 0x4000178c );\nPROVIDE ( _open_r = 0x4000bd54 );\nPROVIDE ( __paritysi2 = 0x40002f3c );\nPROVIDE ( pbkdf2_sha1 = 0x40060ba4 );\nPROVIDE ( phy_get_romfuncs = 0x40004100 );\nPROVIDE ( __popcountdi2 = 0x40002ef8 );\nPROVIDE ( __popcountsi2 = 0x40002ed0 );\nPROVIDE ( __popcount_tab = 0x3ff96544 );\nPROVIDE ( __powidf2 = 0x400638d4 );\nPROVIDE ( __powisf2 = 0x4006389c );\nPROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 );\nPROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c );\nPROVIDE ( qsort = 0x40056424 );\nPROVIDE ( _raise_r = 0x4000bc70 );\nPROVIDE ( rand = 0x40001058 );\nPROVIDE ( rand_r = 0x400010d4 );\nPROVIDE ( r_btdm_option_data = 0x3ffae6e0 );\nPROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 );\nPROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 );\nPROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 );\nPROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 );\nPROVIDE ( r_bt_util_buf_init = 0x400100e4 );\nPROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 );\nPROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec );\nPROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 );\nPROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 );\nPROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 );\nPROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c );\nPROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec );\nPROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 );\nPROVIDE ( rc4_skip = 0x40060928 );\nPROVIDE ( r_co_bdaddr_compare = 0x40014324 );\nPROVIDE ( r_co_bytes_to_string = 0x400142e4 );\nPROVIDE ( r_co_list_check_size_available = 0x400142c4 );\nPROVIDE ( r_co_list_extract = 0x4001404c );\nPROVIDE ( r_co_list_extract_after = 0x40014118 );\nPROVIDE ( r_co_list_find = 0x4001419c );\nPROVIDE ( r_co_list_init = 0x40013f14 );\nPROVIDE ( r_co_list_insert_after = 0x40014254 );\nPROVIDE ( r_co_list_insert_before = 0x40014200 );\nPROVIDE ( r_co_list_merge = 0x400141bc );\nPROVIDE ( r_co_list_pool_init = 0x40013f30 );\nPROVIDE ( r_co_list_pop_front = 0x40014028 );\nPROVIDE ( r_co_list_push_back = 0x40013fb8 );\nPROVIDE ( r_co_list_push_front = 0x40013ff4 );\nPROVIDE ( r_co_list_size = 0x400142ac );\nPROVIDE ( r_co_nb_good_channels = 0x40014360 );\nPROVIDE ( r_co_slot_to_duration = 0x40014348 );\nPROVIDE ( r_dbg_init = 0x40014394 );\nPROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 );\nPROVIDE ( r_dbg_swdiag_init = 0x40014470 );\nPROVIDE ( r_dbg_swdiag_read = 0x400144a4 );\nPROVIDE ( r_dbg_swdiag_write = 0x400144d0 );\nPROVIDE ( r_E1 = 0x400108e8 );\nPROVIDE ( r_E21 = 0x40010968 );\nPROVIDE ( r_E22 = 0x400109b4 );\nPROVIDE ( r_E3 = 0x40010a58 );\nPROVIDE ( r_ea_alarm_clear = 0x40015ab4 );\nPROVIDE ( r_ea_alarm_set = 0x40015a10 );\nPROVIDE ( read = 0x400017dc );\nPROVIDE ( _read_r = 0x4000bda8 );\nPROVIDE ( r_ea_elt_cancel = 0x400150d0 );\nPROVIDE ( r_ea_elt_create = 0x40015264 );\nPROVIDE ( r_ea_elt_insert = 0x400152a8 );\nPROVIDE ( r_ea_elt_remove = 0x400154f0 );\nPROVIDE ( r_ea_finetimer_isr = 0x400155d4 );\nPROVIDE ( r_ea_init = 0x40015228 );\nPROVIDE ( r_ea_interval_create = 0x4001555c );\nPROVIDE ( r_ea_interval_delete = 0x400155a8 );\nPROVIDE ( r_ea_interval_duration_req = 0x4001597c );\nPROVIDE ( r_ea_interval_insert = 0x4001557c );\nPROVIDE ( r_ea_interval_remove = 0x40015590 );\nPROVIDE ( realloc = 0x4000becc );\nPROVIDE ( _realloc_r = 0x4000bbe0 );\nPROVIDE ( r_ea_offset_req = 0x40015748 );\nPROVIDE ( r_ea_sleep_check = 0x40015928 );\nPROVIDE ( r_ea_sw_isr = 0x40015724 );\nPROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 );\nPROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 );\nPROVIDE ( r_ecc_abort_key256_generation = 0x40017070 );\nPROVIDE ( r_ecc_generate_key256 = 0x40016e00 );\nPROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 );\nPROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 );\nPROVIDE ( r_ecc_get_debug_Keys = 0x40017224 );\nPROVIDE ( r_ecc_init = 0x40016dbc );\nPROVIDE ( RecvBuff = 0x3ffe009c );\nPROVIDE ( r_em_buf_init = 0x4001729c );\nPROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 );\nPROVIDE ( r_em_buf_rx_free = 0x400173c4 );\nPROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 );\nPROVIDE ( r_em_buf_tx_free = 0x4001741c );\nPROVIDE ( _rename_r = 0x4000bc28 );\nPROVIDE ( r_F1_256 = 0x400133e4 );\nPROVIDE ( r_F2_256 = 0x40013568 );\nPROVIDE ( r_F3_256 = 0x40013664 );\nPROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c );\nPROVIDE ( r_G_256 = 0x40013470 );\nPROVIDE ( r_H3 = 0x40013760 );\nPROVIDE ( r_H4 = 0x40013830 );\nPROVIDE ( r_h4tl_init = 0x40017878 );\nPROVIDE ( r_h4tl_start = 0x40017924 );\nPROVIDE ( r_h4tl_stop = 0x40017934 );\nPROVIDE ( r_h4tl_write = 0x400178d0 );\nPROVIDE ( r_H5 = 0x400138dc );\nPROVIDE ( r_hashConcat = 0x40013a38 );\nPROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c );\nPROVIDE ( r_hci_acl_tx_data_received = 0x40019654 );\nPROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 );\nPROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac );\nPROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c );\nPROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 );\nPROVIDE ( r_hci_cmd_received = 0x400192f8 );\nPROVIDE ( r_hci_evt_filter_add = 0x40018a64 );\nPROVIDE ( r_hci_evt_mask_set = 0x400189e4 );\nPROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 );\nPROVIDE ( r_hci_fc_acl_en = 0x400179d8 );\nPROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c );\nPROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 );\nPROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 );\nPROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c );\nPROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 );\nPROVIDE ( r_hci_fc_init = 0x40017974 );\nPROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 );\nPROVIDE ( r_hci_fc_sync_en = 0x40017a30 );\nPROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 );\nPROVIDE ( r_hci_init = 0x40018538 );\nPROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 );\nPROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 );\nPROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 );\nPROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 );\nPROVIDE ( r_hci_reset = 0x4001856c );\nPROVIDE ( r_hci_send_2_host = 0x400185bc );\nPROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 );\nPROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 );\nPROVIDE ( r_hci_tl_init = 0x40019290 );\nPROVIDE ( r_hci_tl_send = 0x40019228 );\nPROVIDE ( r_hci_util_pack = 0x40019874 );\nPROVIDE ( r_hci_util_unpack = 0x40019998 );\nPROVIDE ( r_hci_voice_settings_get = 0x40018bdc );\nPROVIDE ( r_hci_voice_settings_set = 0x40018be8 );\nPROVIDE ( r_HMAC = 0x40013968 );\nPROVIDE ( r_import_rf_phy_func = 0x3ffb8354 );\nPROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 );\nPROVIDE ( r_ip_funcs = 0x3ffae710 );\nPROVIDE ( r_ip_funcs_p = 0x3ffae70c );\nPROVIDE ( r_ke_check_malloc = 0x40019de0 );\nPROVIDE ( r_ke_event_callback_set = 0x40019ba8 );\nPROVIDE ( r_ke_event_clear = 0x40019c2c );\nPROVIDE ( r_ke_event_flush = 0x40019ccc );\nPROVIDE ( r_ke_event_get = 0x40019c78 );\nPROVIDE ( r_ke_event_get_all = 0x40019cc0 );\nPROVIDE ( r_ke_event_init = 0x40019b90 );\nPROVIDE ( r_ke_event_schedule = 0x40019cdc );\nPROVIDE ( r_ke_event_set = 0x40019be0 );\nPROVIDE ( r_ke_flush = 0x4001a374 );\nPROVIDE ( r_ke_free = 0x4001a014 );\nPROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 );\nPROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 );\nPROVIDE ( r_ke_init = 0x4001a318 );\nPROVIDE ( r_ke_is_free = 0x4001a184 );\nPROVIDE ( r_ke_malloc = 0x40019eb4 );\nPROVIDE ( r_ke_mem_init = 0x40019d3c );\nPROVIDE ( r_ke_mem_is_empty = 0x40019d8c );\nPROVIDE ( r_ke_msg_alloc = 0x4001a1e0 );\nPROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 );\nPROVIDE ( r_ke_msg_discard = 0x4001a850 );\nPROVIDE ( r_ke_msg_forward = 0x4001a290 );\nPROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac );\nPROVIDE ( r_ke_msg_free = 0x4001a2cc );\nPROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 );\nPROVIDE ( r_ke_msg_save = 0x4001a858 );\nPROVIDE ( r_ke_msg_send = 0x4001a234 );\nPROVIDE ( r_ke_msg_send_basic = 0x4001a26c );\nPROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec );\nPROVIDE ( r_ke_queue_extract = 0x40055fd0 );\nPROVIDE ( r_ke_queue_insert = 0x40056020 );\nPROVIDE ( r_ke_sleep_check = 0x4001a3d8 );\nPROVIDE ( r_ke_state_get = 0x4001a7d8 );\nPROVIDE ( r_ke_state_set = 0x4001a6fc );\nPROVIDE ( r_ke_stats_get = 0x4001a3f0 );\nPROVIDE ( r_ke_task_check = 0x4001a8a4 );\nPROVIDE ( r_ke_task_create = 0x4001a674 );\nPROVIDE ( r_ke_task_delete = 0x4001a6c0 );\nPROVIDE ( r_ke_task_init = 0x4001a650 );\nPROVIDE ( r_ke_task_msg_flush = 0x4001a860 );\nPROVIDE ( r_ke_timer_active = 0x4001ac08 );\nPROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 );\nPROVIDE ( r_ke_timer_clear = 0x4001ab90 );\nPROVIDE ( r_ke_timer_init = 0x4001aa9c );\nPROVIDE ( r_ke_timer_set = 0x4001aac0 );\nPROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 );\nPROVIDE ( r_KPrimC = 0x40010ad4 );\nPROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 );\nPROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 );\nPROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 );\nPROVIDE ( r_lb_init = 0x4001acd4 );\nPROVIDE ( r_lb_mst_key = 0x4001afc0 );\nPROVIDE ( r_lb_mst_key_cmp = 0x4001af74 );\nPROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 );\nPROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 );\nPROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c );\nPROVIDE ( r_lb_reset = 0x4001ad38 );\nPROVIDE ( r_lb_send_lmp = 0x4001adbc );\nPROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c );\nPROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 );\nPROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 );\nPROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 );\nPROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c );\nPROVIDE ( r_lc_afh_set = 0x4001cc74 );\nPROVIDE ( r_lc_afh_start = 0x4001d240 );\nPROVIDE ( r_lc_auth_cmp = 0x4001cd54 );\nPROVIDE ( r_lc_calc_link_key = 0x4001ce7c );\nPROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 );\nPROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc );\nPROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac );\nPROVIDE ( r_lc_chk_to = 0x4001d2a8 );\nPROVIDE ( r_lc_cmd_stat_send = 0x4001c914 );\nPROVIDE ( r_lc_comb_key_svr = 0x4001d30c );\nPROVIDE ( r_lc_con_cmp = 0x4001d44c );\nPROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc );\nPROVIDE ( r_lc_conn_seq_done = 0x40021334 );\nPROVIDE ( r_lc_detach = 0x4002037c );\nPROVIDE ( r_lc_dhkey = 0x4001d564 );\nPROVIDE ( r_lc_enc_cmp = 0x4001d8bc );\nPROVIDE ( r_lc_enc_key_refresh = 0x4001d720 );\nPROVIDE ( r_lc_end_chk_colli = 0x4001d858 );\nPROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 );\nPROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 );\nPROVIDE ( r_lc_epr_change_lk = 0x4001db38 );\nPROVIDE ( r_lc_epr_cmp = 0x4001da88 );\nPROVIDE ( r_lc_epr_resp = 0x4001e0b4 );\nPROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 );\nPROVIDE ( r_lc_ext_feat = 0x40020d6c );\nPROVIDE ( r_lc_feat = 0x40020984 );\nPROVIDE ( r_lc_hl_connect = 0x400209e8 );\nPROVIDE ( r_lc_init = 0x4001c948 );\nPROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 );\nPROVIDE ( r_lc_initiator_epr = 0x4001e064 );\nPROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 );\nPROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 );\nPROVIDE ( r_lc_key_exch_end = 0x4001e140 );\nPROVIDE ( r_lc_legacy_pair = 0x4001e1c0 );\nPROVIDE ( r_lc_local_switch = 0x4001e22c );\nPROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 );\nPROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 );\nPROVIDE ( r_lc_loc_auth = 0x40020ecc );\nPROVIDE ( r_lc_locepr_lkref = 0x4001d648 );\nPROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 );\nPROVIDE ( r_lc_loc_sniff = 0x40020a6c );\nPROVIDE ( r_lc_max_slot_mgt = 0x4001e410 );\nPROVIDE ( r_lc_mst_key = 0x4001e7c0 );\nPROVIDE ( r_lc_mst_qos_done = 0x4001ea80 );\nPROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 );\nPROVIDE ( r_lc_mutual_auth_end = 0x4001e670 );\nPROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 );\nPROVIDE ( r_lc_packet_type = 0x40021038 );\nPROVIDE ( r_lc_pair = 0x40020ddc );\nPROVIDE ( r_lc_pairing_cont = 0x4001eafc );\nPROVIDE ( r_lc_passkey_comm = 0x4001ed20 );\nPROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 );\nPROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec );\nPROVIDE ( r_lc_ptt = 0x4001ee2c );\nPROVIDE ( r_lc_ptt_cmp = 0x4001eeec );\nPROVIDE ( r_lc_qos_setup = 0x4001ef50 );\nPROVIDE ( r_lc_rd_rem_name = 0x4001efd0 );\nPROVIDE ( r_lc_release = 0x4001f8a8 );\nPROVIDE ( r_lc_rem_enc = 0x4001f124 );\nPROVIDE ( r_lc_rem_name_cont = 0x4001f290 );\nPROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 );\nPROVIDE ( r_lc_rem_sniff = 0x40020ca4 );\nPROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 );\nPROVIDE ( r_lc_rem_switch = 0x4001f070 );\nPROVIDE ( r_lc_rem_trans_mode = 0x4001f314 );\nPROVIDE ( r_lc_rem_unsniff = 0x400207a0 );\nPROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c );\nPROVIDE ( r_lc_reset = 0x4001c99c );\nPROVIDE ( r_lc_resp_auth = 0x4001f518 );\nPROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 );\nPROVIDE ( r_lc_resp_num_comp = 0x40020074 );\nPROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 );\nPROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c );\nPROVIDE ( r_lc_resp_pair = 0x400208a4 );\nPROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 );\nPROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c );\nPROVIDE ( r_lc_restart_enc = 0x4001f8ec );\nPROVIDE ( r_lc_restart_enc_cont = 0x4001f940 );\nPROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 );\nPROVIDE ( r_lc_restore_to = 0x4001f9e0 );\nPROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 );\nPROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 );\nPROVIDE ( r_lc_rsw_done = 0x4001db94 );\nPROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 );\nPROVIDE ( r_lc_sco_detach = 0x40021e40 );\nPROVIDE ( r_lc_sco_host_accept = 0x40022118 );\nPROVIDE ( r_lc_sco_host_reject = 0x400222b8 );\nPROVIDE ( r_lc_sco_host_request = 0x40021f4c );\nPROVIDE ( r_lc_sco_host_request_disc = 0x4002235c );\nPROVIDE ( r_lc_sco_init = 0x40021dc8 );\nPROVIDE ( r_lc_sco_peer_accept = 0x40022780 );\nPROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 );\nPROVIDE ( r_lc_sco_peer_reject = 0x40022824 );\nPROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c );\nPROVIDE ( r_lc_sco_peer_request = 0x4002240c );\nPROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec );\nPROVIDE ( r_lc_sco_release = 0x40021eec );\nPROVIDE ( r_lc_sco_reset = 0x40021dfc );\nPROVIDE ( r_lc_sco_timeout = 0x40022bd4 );\nPROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec );\nPROVIDE ( r_lc_semi_key_cmp = 0x40020294 );\nPROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c );\nPROVIDE ( r_lc_send_enc_mode = 0x40020220 );\nPROVIDE ( r_lc_send_lmp = 0x4001c1a8 );\nPROVIDE ( r_lc_send_pdu_acc = 0x4001c21c );\nPROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 );\nPROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 );\nPROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 );\nPROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c );\nPROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 );\nPROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 );\nPROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 );\nPROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 );\nPROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 );\nPROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 );\nPROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 );\nPROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec );\nPROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 );\nPROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 );\nPROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c );\nPROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c );\nPROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 );\nPROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec );\nPROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c );\nPROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 );\nPROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 );\nPROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 );\nPROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 );\nPROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 );\nPROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c );\nPROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 );\nPROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 );\nPROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 );\nPROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 );\nPROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 );\nPROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 );\nPROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 );\nPROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 );\nPROVIDE ( r_lc_send_pdu_sres = 0x4001c548 );\nPROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc );\nPROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 );\nPROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 );\nPROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 );\nPROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc );\nPROVIDE ( r_lc_sniff_init = 0x40022cac );\nPROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 );\nPROVIDE ( r_lc_sniff_reset = 0x40022cc8 );\nPROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 );\nPROVIDE ( r_lc_sniff_sub_mode = 0x400204fc );\nPROVIDE ( r_lc_sp_end = 0x400213a8 );\nPROVIDE ( r_lc_sp_fail = 0x40020470 );\nPROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc );\nPROVIDE ( r_lc_ssr_nego = 0x4002125c );\nPROVIDE ( r_lc_start = 0x4001ca28 );\nPROVIDE ( r_lc_start_enc = 0x4001fb28 );\nPROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c );\nPROVIDE ( r_lc_start_key_exch = 0x4001fe10 );\nPROVIDE ( r_lc_start_lmp_to = 0x4001fae8 );\nPROVIDE ( r_lc_start_oob = 0x4001fffc );\nPROVIDE ( r_lc_start_passkey = 0x4001feac );\nPROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 );\nPROVIDE ( r_lc_stop_afh_report = 0x40020184 );\nPROVIDE ( r_lc_stop_enc = 0x40020110 );\nPROVIDE ( r_lc_switch_cmp = 0x40020448 );\nPROVIDE ( r_lc_unit_key_svr = 0x400206d8 );\nPROVIDE ( r_lc_unsniff = 0x40020c50 );\nPROVIDE ( r_lc_unsniff_cmp = 0x40020810 );\nPROVIDE ( r_lc_unsniff_cont = 0x40020750 );\nPROVIDE ( r_lc_upd_to = 0x4002065c );\nPROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 );\nPROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac );\nPROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 );\nPROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c );\nPROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 );\nPROVIDE ( r_lc_version = 0x40020a30 );\nPROVIDE ( lmp_accepted_ext_handler = 0x40027290 );\nPROVIDE ( lmp_not_accepted_ext_handler = 0x40029c54 );\nPROVIDE ( lmp_clk_adj_handler = 0x40027468 );\nPROVIDE ( lmp_clk_adj_ack_handler = 0x400274f4 );\nPROVIDE ( lmp_clk_adj_req_handler = 0x4002751c );\nPROVIDE ( lmp_feats_res_ext_handler = 0x4002cac4 );\nPROVIDE ( lmp_feats_req_ext_handler = 0x4002ccb0 );\nPROVIDE ( lmp_pkt_type_tbl_req_handler = 0x40027574 );\nPROVIDE ( lmp_esco_link_req_handler = 0x40027610 );\nPROVIDE ( lmp_rmv_esco_link_req_handler = 0x400276e8 );\nPROVIDE ( lmp_ch_class_req_handler = 0x40027730 );\nPROVIDE ( lmp_ch_class_handler = 0x4002ca18 );\nPROVIDE ( lmp_ssr_req_handler = 0x4002780c );\nPROVIDE ( lmp_ssr_res_handler = 0x40027900 );\nPROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );\nPROVIDE ( lmp_pause_enc_req_handler = 0x4002df90 );\nPROVIDE ( lmp_resume_enc_req_handler = 0x4002e084 );\nPROVIDE ( lmp_num_comparison_fail_handler = 0x40027a74 );\nPROVIDE ( lmp_passkey_fail_handler = 0x40027aec );\nPROVIDE ( lmp_keypress_notif_handler = 0x4002c5c8 );\nPROVIDE ( lmp_pwr_ctrl_req_handler = 0x400263bc );\nPROVIDE ( lmp_pwr_ctrl_res_handler = 0x40026480 );\nPROVIDE ( lmp_auto_rate_handler = 0x40026548 );\nPROVIDE ( lmp_pref_rate_handler = 0x4002657c );\nPROVIDE ( lmp_name_req_handler = 0x40025050 );\nPROVIDE ( lmp_name_res_handler = 0x400250bc );\nPROVIDE ( lmp_not_accepted_handler = 0x400251d0 );\nPROVIDE ( lmp_accepted_handler = 0x4002e894 );\nPROVIDE ( lmp_clk_off_req_handler = 0x40025a44 );\nPROVIDE ( lmp_clk_off_res_handler = 0x40025ab8 );\nPROVIDE ( lmp_detach_handler = 0x40025b74 );\nPROVIDE ( lmp_tempkey_handler = 0x4002b6b0 );\nPROVIDE ( lmp_temprand_handler = 0x4002b74c );\nPROVIDE ( lmp_sres_handler = 0x4002b840 );\nPROVIDE ( lmp_aurand_handler = 0x4002bda0 );\nPROVIDE ( lmp_unitkey_handler = 0x4002c13c );\nPROVIDE ( lmp_combkey_handler = 0x4002c234 );\nPROVIDE ( lmp_inrand_handler = 0x4002c414 );\nPROVIDE ( lmp_oob_fail_handler = 0x40027b84 );\nPROVIDE ( lmp_ping_req_handler = 0x40027c08 );\nPROVIDE ( lmp_ping_res_handler = 0x40027c5c );\nPROVIDE ( lmp_enc_mode_req_handler = 0x40025c60 );\nPROVIDE ( lmp_enc_key_size_req_handler = 0x40025e54 );\nPROVIDE ( lmp_switch_req_handler = 0x40025f84 );\nPROVIDE ( lmp_start_enc_req_handler = 0x4002e124 );\nPROVIDE ( lmp_stop_enc_req_handler = 0x4002de30 );\nPROVIDE ( lmp_sniff_req_handler = 0x400260c8 );\nPROVIDE ( lmp_unsniff_req_handler = 0x400261e0 );\nPROVIDE ( lmp_incr_pwr_req_handler = 0x4002629c );\nPROVIDE ( lmp_decr_pwr_req_handler = 0x400262f8 );\nPROVIDE ( lmp_max_pwr_handler = 0x40026354 );\nPROVIDE ( lmp_min_pwr_handler = 0x40026388 );\nPROVIDE ( lmp_ver_req_handler = 0x400265f0 );\nPROVIDE ( lmp_ver_res_handler = 0x40026670 );\nPROVIDE ( lmp_qos_handler = 0x40026790 );\nPROVIDE ( lmp_qos_req_handler = 0x40026844 );\nPROVIDE ( lmp_sco_link_req_handler = 0x40026930 );\nPROVIDE ( lmp_rmv_sco_link_req_handler = 0x40026a10 );\nPROVIDE ( lmp_max_slot_handler = 0x40026a54 );\nPROVIDE ( lmp_max_slot_req_handler = 0x40026aac );\nPROVIDE ( lmp_timing_accu_req_handler = 0x40026b54 );\nPROVIDE ( lmp_timing_accu_res_handler = 0x40026bcc );\nPROVIDE ( lmp_setup_cmp_handler = 0x40026c84 );\nPROVIDE ( lmp_feats_res_handler = 0x4002b548 );\nPROVIDE ( lmp_feats_req_handler = 0x4002b620 );\nPROVIDE ( lmp_host_con_req_handler = 0x4002b3d8 );\nPROVIDE ( lmp_use_semi_perm_key_handler = 0x4002b4c4 );\nPROVIDE ( lmp_slot_off_handler = 0x40026cc8 );\nPROVIDE ( lmp_page_mode_req_handler = 0x40026d0c );\nPROVIDE ( lmp_page_scan_mode_req_handler = 0x40026d4c );\nPROVIDE ( lmp_supv_to_handler = 0x40026d94 );\nPROVIDE ( lmp_test_activate_handler = 0x40026e7c );\nPROVIDE ( lmp_test_ctrl_handler = 0x40026ee4 );\nPROVIDE ( lmp_enc_key_size_mask_req_handler = 0x40027038 );\nPROVIDE ( lmp_enc_key_size_mask_res_handler = 0x400270a4 );\nPROVIDE ( lmp_set_afh_handler = 0x4002b2e4 );\nPROVIDE ( lmp_encaps_hdr_handler = 0x40027120 );\nPROVIDE ( lmp_encaps_payl_handler = 0x4002e590 );\nPROVIDE ( lmp_sp_nb_handler = 0x4002acf0 );\nPROVIDE ( lmp_sp_cfm_handler = 0x4002b170 );\nPROVIDE ( lmp_dhkey_chk_handler = 0x4002ab48 );\nPROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );\nPROVIDE ( lmp_io_cap_res_handler = 0x4002c670 );\nPROVIDE ( lmp_io_cap_req_handler = 0x4002c7a4 );\nPROVIDE ( ld_acl_tx_packet_type_select = 0x4002fb40 );\nPROVIDE ( ld_acl_sched = 0x40033268 );\nPROVIDE ( ld_acl_sniff_sched = 0x4003340c );\nPROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 );\nPROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 );\nPROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 );\nPROVIDE ( r_ld_acl_afh_set = 0x40036b60 );\nPROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 );\nPROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 );\nPROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 );\nPROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 );\nPROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 );\nPROVIDE ( r_ld_acl_clk_set = 0x40036950 );\nPROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 );\nPROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 );\nPROVIDE ( r_ld_acl_data_flush = 0x400357bc );\nPROVIDE ( r_ld_acl_data_tx = 0x4003544c );\nPROVIDE ( r_ld_acl_edr_set = 0x4003678c );\nPROVIDE ( r_ld_acl_enc_key_load = 0x40036404 );\nPROVIDE ( r_ld_acl_flow_off = 0x40035400 );\nPROVIDE ( r_ld_acl_flow_on = 0x4003541c );\nPROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c );\nPROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 );\nPROVIDE ( r_ld_acl_init = 0x40034d08 );\nPROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 );\nPROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 );\nPROVIDE ( r_ld_acl_lsto_get = 0x400366b4 );\nPROVIDE ( r_ld_acl_lsto_set = 0x400366f8 );\nPROVIDE ( r_ld_acl_reset = 0x40034d24 );\nPROVIDE ( r_ld_acl_role_get = 0x40036b30 );\nPROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 );\nPROVIDE ( r_ld_acl_rsw_req = 0x40035e74 );\nPROVIDE ( r_ld_acl_rx_enc = 0x40036344 );\nPROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 );\nPROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 );\nPROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c );\nPROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 );\nPROVIDE ( r_ld_acl_sniff = 0x4003617c );\nPROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 );\nPROVIDE ( r_ld_acl_ssr_set = 0x40036274 );\nPROVIDE ( r_ld_acl_start = 0x40034ddc );\nPROVIDE ( r_ld_acl_stop = 0x4003532c );\nPROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 );\nPROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c );\nPROVIDE ( r_ld_acl_t_poll_get = 0x40036024 );\nPROVIDE ( r_ld_acl_t_poll_set = 0x40036068 );\nPROVIDE ( r_ld_acl_tx_enc = 0x400362f8 );\nPROVIDE ( r_ld_acl_unsniff = 0x400361e0 );\nPROVIDE ( r_ld_active_check = 0x4003cac4 );\nPROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec );\nPROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c );\nPROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 );\nPROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc );\nPROVIDE ( r_ld_bcst_acl_start = 0x4003882c );\nPROVIDE ( r_ld_bcst_afh_update = 0x40038f3c );\nPROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c );\nPROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 );\nPROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 );\nPROVIDE ( r_ld_bd_addr_get = 0x4003ca20 );\nPROVIDE ( r_ld_channel_assess = 0x4003c184 );\nPROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 );\nPROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 );\nPROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 );\nPROVIDE ( r_ld_csb_rx_init = 0x40039690 );\nPROVIDE ( r_ld_csb_rx_reset = 0x4003969c );\nPROVIDE ( r_ld_csb_rx_start = 0x4003972c );\nPROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 );\nPROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc );\nPROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c );\nPROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 );\nPROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 );\nPROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 );\nPROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 );\nPROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 );\nPROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 );\nPROVIDE ( r_ld_fm_frame_isr = 0x4003a82c );\nPROVIDE ( r_ld_fm_init = 0x4003a760 );\nPROVIDE ( r_ld_fm_prog_check = 0x4003ab28 );\nPROVIDE ( r_ld_fm_prog_disable = 0x4003a984 );\nPROVIDE ( r_ld_fm_prog_enable = 0x4003a944 );\nPROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 );\nPROVIDE ( r_ld_fm_reset = 0x4003a794 );\nPROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 );\nPROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 );\nPROVIDE ( r_ld_init = 0x4003c294 );\nPROVIDE ( r_ld_inq_init = 0x4003b15c );\nPROVIDE ( r_ld_inq_reset = 0x4003b168 );\nPROVIDE ( r_ld_inq_start = 0x4003b1f0 );\nPROVIDE ( r_ld_inq_stop = 0x4003b4f0 );\nPROVIDE ( r_ld_iscan_eir_get = 0x4003c118 );\nPROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 );\nPROVIDE ( r_ld_iscan_init = 0x4003b9f0 );\nPROVIDE ( r_ld_iscan_reset = 0x4003ba14 );\nPROVIDE ( r_ld_iscan_restart = 0x4003ba44 );\nPROVIDE ( r_ld_iscan_start = 0x4003bb28 );\nPROVIDE ( r_ld_iscan_stop = 0x4003bf1c );\nPROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 );\nPROVIDE ( r_ld_page_init = 0x4003d808 );\nPROVIDE ( r_ld_page_reset = 0x4003d814 );\nPROVIDE ( r_ld_page_start = 0x4003d848 );\nPROVIDE ( r_ld_page_stop = 0x4003da54 );\nPROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 );\nPROVIDE ( r_ld_pca_init = 0x4003deb4 );\nPROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac );\nPROVIDE ( r_ld_pca_local_config = 0x4003df6c );\nPROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 );\nPROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 );\nPROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 );\nPROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 );\nPROVIDE ( r_ld_pca_reset = 0x4003df0c );\nPROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 );\nPROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 );\nPROVIDE ( r_ld_pscan_init = 0x4003f474 );\nPROVIDE ( r_ld_pscan_reset = 0x4003f498 );\nPROVIDE ( r_ld_pscan_restart = 0x4003f4b8 );\nPROVIDE ( r_ld_pscan_start = 0x4003f514 );\nPROVIDE ( r_ld_pscan_stop = 0x4003f618 );\nPROVIDE ( r_ld_read_clock = 0x4003c9e4 );\nPROVIDE ( r_ld_reset = 0x4003c714 );\nPROVIDE ( r_ld_sched_acl_add = 0x4003f978 );\nPROVIDE ( r_ld_sched_acl_remove = 0x4003f99c );\nPROVIDE ( r_ld_sched_compute = 0x4003f6f8 );\nPROVIDE ( r_ld_sched_init = 0x4003f7ac );\nPROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 );\nPROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 );\nPROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 );\nPROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 );\nPROVIDE ( r_ld_sched_page_add = 0x4003f910 );\nPROVIDE ( r_ld_sched_page_remove = 0x4003f938 );\nPROVIDE ( r_ld_sched_pscan_add = 0x4003f828 );\nPROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 );\nPROVIDE ( r_ld_sched_reset = 0x4003f7d4 );\nPROVIDE ( r_ld_sched_sco_add = 0x4003fa4c );\nPROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c );\nPROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 );\nPROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c );\nPROVIDE ( r_ld_sched_sscan_add = 0x4003f868 );\nPROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 );\nPROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 );\nPROVIDE ( r_ld_sco_data_tx = 0x40037ee8 );\nPROVIDE ( r_ld_sco_start = 0x40037110 );\nPROVIDE ( r_ld_sco_stop = 0x40037c40 );\nPROVIDE ( r_ld_sco_update = 0x40037a74 );\nPROVIDE ( r_ld_sscan_activated = 0x4004031c );\nPROVIDE ( r_ld_sscan_init = 0x400402f0 );\nPROVIDE ( r_ld_sscan_reset = 0x400402fc );\nPROVIDE ( r_ld_sscan_start = 0x40040384 );\nPROVIDE ( r_ld_strain_init = 0x400409f4 );\nPROVIDE ( r_ld_strain_reset = 0x40040a00 );\nPROVIDE ( r_ld_strain_start = 0x40040a8c );\nPROVIDE ( r_ld_strain_stop = 0x40040df0 );\nPROVIDE ( r_ld_timing_accuracy_get = 0x4003caac );\nPROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c );\nPROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 );\nPROVIDE ( r_ld_util_bch_create = 0x40040fcc );\nPROVIDE ( r_ld_util_fhs_pk = 0x400411c8 );\nPROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 );\nPROVIDE ( r_ld_util_stp_pk = 0x400413f4 );\nPROVIDE ( r_ld_util_stp_unpk = 0x40041324 );\nPROVIDE ( r_ld_version_get = 0x4003ca6c );\nPROVIDE ( r_ld_wlcoex_set = 0x4003caf8 );\nPROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 );\nPROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c );\nPROVIDE ( r_llc_ch_assess_local = 0x40041494 );\nPROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 );\nPROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 );\nPROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac );\nPROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 );\nPROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c );\nPROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 );\nPROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c );\nPROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 );\nPROVIDE ( r_llc_con_update_complete_send = 0x40044d68 );\nPROVIDE ( r_llc_con_update_finished = 0x4004518c );\nPROVIDE ( r_llc_con_update_ind = 0x40045038 );\nPROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 );\nPROVIDE ( r_llc_end_evt_defer = 0x40046330 );\nPROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c );\nPROVIDE ( r_llc_init = 0x40044778 );\nPROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 );\nPROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 );\nPROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc );\nPROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 );\nPROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 );\nPROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 );\nPROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 );\nPROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 );\nPROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 );\nPROVIDE ( r_llc_llcp_get_autorize = 0x4004475c );\nPROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 );\nPROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac );\nPROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 );\nPROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 );\nPROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c );\nPROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 );\nPROVIDE ( r_llc_llcp_recv_handler = 0x40044678 );\nPROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c );\nPROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c );\nPROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 );\nPROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 );\nPROVIDE ( r_llc_llcp_tester_send = 0x400445e4 );\nPROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 );\nPROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c );\nPROVIDE ( r_llc_lsto_con_update = 0x40045098 );\nPROVIDE ( r_llc_ltk_req_send = 0x40044dc0 );\nPROVIDE ( r_llc_map_update_finished = 0x40045260 );\nPROVIDE ( r_llc_map_update_ind = 0x400450f0 );\nPROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc );\nPROVIDE ( r_llc_pdu_defer = 0x40046528 );\nPROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac );\nPROVIDE ( r_llc_reset = 0x400447b8 );\nPROVIDE ( r_llc_start = 0x400447f4 );\nPROVIDE ( r_llc_stop = 0x400449ac );\nPROVIDE ( r_llc_util_bw_mgt = 0x4004629c );\nPROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 );\nPROVIDE ( r_llc_util_dicon_procedure = 0x40046130 );\nPROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 );\nPROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 );\nPROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 );\nPROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 );\nPROVIDE ( r_llc_util_update_channel_map = 0x400461ac );\nPROVIDE ( r_llc_version_rd_event_send = 0x40044e60 );\nPROVIDE ( r_lld_adv_start = 0x40048b38 );\nPROVIDE ( r_lld_adv_stop = 0x40048ea0 );\nPROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 );\nPROVIDE ( r_lld_con_param_req = 0x40049f0c );\nPROVIDE ( r_lld_con_param_rsp = 0x40049e00 );\nPROVIDE ( r_lld_con_start = 0x400491f8 );\nPROVIDE ( r_lld_con_stop = 0x40049fdc );\nPROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc );\nPROVIDE ( r_lld_con_update_ind = 0x4004a30c );\nPROVIDE ( r_lld_con_update_req = 0x40049b60 );\nPROVIDE ( r_lld_core_reset = 0x40048a9c );\nPROVIDE ( r_lld_crypt_isr = 0x4004a324 );\nPROVIDE ( r_lld_evt_adv_create = 0x400481f4 );\nPROVIDE ( r_lld_evt_canceled = 0x400485c8 );\nPROVIDE ( r_lld_evt_channel_next = 0x40046aac );\nPROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc );\nPROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 );\nPROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c );\nPROVIDE ( r_lld_evt_drift_compute = 0x40047670 );\nPROVIDE ( r_lld_evt_elt_delete = 0x40047538 );\nPROVIDE ( r_lld_evt_elt_insert = 0x400474c8 );\nPROVIDE ( r_lld_evt_end = 0x400483e8 );\nPROVIDE ( r_lld_evt_end_isr = 0x4004862c );\nPROVIDE ( r_lld_evt_init = 0x40046b3c );\nPROVIDE ( r_lld_evt_init_evt = 0x40046cd0 );\nPROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 );\nPROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 );\nPROVIDE ( r_lld_evt_prevent_stop = 0x40047adc );\nPROVIDE ( r_lld_evt_restart = 0x40046d50 );\nPROVIDE ( r_lld_evt_rx = 0x40048578 );\nPROVIDE ( r_lld_evt_rx_isr = 0x40048678 );\nPROVIDE ( r_lld_evt_scan_create = 0x40047ae8 );\nPROVIDE ( r_lld_evt_schedule = 0x40047908 );\nPROVIDE ( r_lld_evt_schedule_next = 0x400477dc );\nPROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 );\nPROVIDE ( r_lld_evt_slave_update = 0x40048138 );\nPROVIDE ( r_lld_evt_update_create = 0x40047cd8 );\nPROVIDE ( r_lld_get_mode = 0x40049ff8 );\nPROVIDE ( r_lld_init = 0x4004873c );\nPROVIDE ( r_lld_move_to_master = 0x400499e0 );\nPROVIDE ( r_lld_move_to_slave = 0x4004a024 );\nPROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 );\nPROVIDE ( r_lld_pdu_check = 0x4004ac34 );\nPROVIDE ( r_lld_pdu_data_send = 0x4004b018 );\nPROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc );\nPROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 );\nPROVIDE ( r_lld_pdu_send_packet = 0x4004b774 );\nPROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 );\nPROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 );\nPROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 );\nPROVIDE ( r_lld_pdu_tx_push = 0x4004b080 );\nPROVIDE ( r_lld_ral_renew_req = 0x4004a73c );\nPROVIDE ( r_lld_scan_start = 0x40048ee0 );\nPROVIDE ( r_lld_scan_stop = 0x40049190 );\nPROVIDE ( r_lld_test_mode_rx = 0x4004a540 );\nPROVIDE ( r_lld_test_mode_tx = 0x4004a350 );\nPROVIDE ( r_lld_test_stop = 0x4004a710 );\nPROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc );\nPROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c );\nPROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 );\nPROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 );\nPROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 );\nPROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 );\nPROVIDE ( r_lld_util_flush_list = 0x4004bbd8 );\nPROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 );\nPROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac );\nPROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 );\nPROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 );\nPROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 );\nPROVIDE ( r_lld_util_instant_get = 0x4004b890 );\nPROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc );\nPROVIDE ( r_lld_util_priority_set = 0x4004bd10 );\nPROVIDE ( r_lld_util_priority_update = 0x4004bd78 );\nPROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 );\nPROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 );\nPROVIDE ( r_lld_wlcoex_set = 0x4004bd98 );\nPROVIDE ( r_llm_ble_ready = 0x4004cc34 );\nPROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 );\nPROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 );\nPROVIDE ( r_llm_con_req_ind = 0x4004cc54 );\nPROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 );\nPROVIDE ( r_llm_create_con = 0x4004de78 );\nPROVIDE ( r_llm_encryption_done = 0x4004dff8 );\nPROVIDE ( r_llm_encryption_start = 0x4004e128 );\nPROVIDE ( r_llm_end_evt_defer = 0x4004eb6c );\nPROVIDE ( r_llm_init = 0x4004c9f8 );\nPROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 );\nPROVIDE ( r_llm_pdu_defer = 0x4004ec48 );\nPROVIDE ( r_llm_ral_clear = 0x4004e1fc );\nPROVIDE ( r_llm_ral_dev_add = 0x4004e23c );\nPROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc );\nPROVIDE ( r_llm_ral_get_rpa = 0x4004e400 );\nPROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 );\nPROVIDE ( r_llm_ral_update = 0x4004e4f8 );\nPROVIDE ( r_llm_set_adv_data = 0x4004d960 );\nPROVIDE ( r_llm_set_adv_en = 0x4004d7ec );\nPROVIDE ( r_llm_set_adv_param = 0x4004d5f4 );\nPROVIDE ( r_llm_set_scan_en = 0x4004db64 );\nPROVIDE ( r_llm_set_scan_param = 0x4004dac8 );\nPROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 );\nPROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 );\nPROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc );\nPROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc );\nPROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 );\nPROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 );\nPROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 );\nPROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 );\nPROVIDE ( r_llm_util_bl_add = 0x4004e9ac );\nPROVIDE ( r_llm_util_bl_check = 0x4004e930 );\nPROVIDE ( r_llm_util_bl_rem = 0x4004ea70 );\nPROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 );\nPROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 );\nPROVIDE ( r_llm_util_check_map_validity = 0x4004e800 );\nPROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 );\nPROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 );\nPROVIDE ( r_llm_util_set_public_addr = 0x4004e89c );\nPROVIDE ( r_llm_wl_clr = 0x4004dc54 );\nPROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 );\nPROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 );\nPROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc );\nPROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 );\nPROVIDE ( r_lm_acl_disc = 0x4004f148 );\nPROVIDE ( r_LM_AddSniff = 0x40022d20 );\nPROVIDE ( r_lm_add_sync = 0x40051358 );\nPROVIDE ( r_lm_afh_activate_timer = 0x4004f444 );\nPROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 );\nPROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 );\nPROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c );\nPROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 );\nPROVIDE ( r_lm_check_active_sync = 0x40051334 );\nPROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c );\nPROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 );\nPROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c );\nPROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 );\nPROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 );\nPROVIDE ( r_LM_ComputePacketType = 0x4002f554 );\nPROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac );\nPROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 );\nPROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 );\nPROVIDE ( r_lm_dhkey_calc_init = 0x40013234 );\nPROVIDE ( r_lm_dhkey_compare = 0x400132d8 );\nPROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec );\nPROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 );\nPROVIDE ( r_lm_f1 = 0x40012bb8 );\nPROVIDE ( r_lm_f2 = 0x40012cfc );\nPROVIDE ( r_lm_f3 = 0x40013050 );\nPROVIDE ( r_lm_g = 0x40012f90 );\nPROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c );\nPROVIDE ( r_lm_get_auth_en = 0x4004f1ac );\nPROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c );\nPROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 );\nPROVIDE ( r_LM_GetFeature = 0x4002f924 );\nPROVIDE ( r_LM_GetLinkTimeout = 0x400233ec );\nPROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 );\nPROVIDE ( r_lm_get_loopback_mode = 0x4004f248 );\nPROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c );\nPROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 );\nPROVIDE ( r_LM_GetMasterKey = 0x4001b260 );\nPROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 );\nPROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 );\nPROVIDE ( r_lm_get_nb_acl = 0x4004ef9c );\nPROVIDE ( r_lm_get_nb_sync_link = 0x4005179c );\nPROVIDE ( r_lm_get_nonce = 0x400131c4 );\nPROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 );\nPROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 );\nPROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 );\nPROVIDE ( r_LM_GetPINType = 0x4004f1e8 );\nPROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 );\nPROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 );\nPROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 );\nPROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 );\nPROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 );\nPROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 );\nPROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c );\nPROVIDE ( r_lm_get_sp_en = 0x4004f1c0 );\nPROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 );\nPROVIDE ( r_lm_get_synchdl = 0x4005175c );\nPROVIDE ( r_lm_get_sync_param = 0x400503b4 );\nPROVIDE ( r_lm_init = 0x4004ed34 );\nPROVIDE ( r_lm_init_sync = 0x400512d8 );\nPROVIDE ( r_lm_is_acl_con = 0x4004f47c );\nPROVIDE ( r_lm_is_acl_con_role = 0x4004f49c );\nPROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 );\nPROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 );\nPROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 );\nPROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 );\nPROVIDE ( r_lm_look_for_sync = 0x40051774 );\nPROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c );\nPROVIDE ( r_lm_lt_addr_free = 0x4004ef74 );\nPROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 );\nPROVIDE ( r_LM_MakeCof = 0x4002f84c );\nPROVIDE ( r_LM_MakeRandVec = 0x400112d8 );\nPROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 );\nPROVIDE ( r_LM_MaxSlot = 0x4002f694 );\nPROVIDE ( r_lm_modif_sync = 0x40051578 );\nPROVIDE ( r_lm_n_is_zero = 0x40012170 );\nPROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 );\nPROVIDE ( r_lm_oob_f1 = 0x40012e54 );\nPROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 );\nPROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 );\nPROVIDE ( r_lmp_pack = 0x4001135c );\nPROVIDE ( r_lmp_unpack = 0x4001149c );\nPROVIDE ( r_lm_read_features = 0x4004f0d8 );\nPROVIDE ( r_LM_RemoveSniff = 0x40023124 );\nPROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 );\nPROVIDE ( r_lm_remove_sync = 0x400517c8 );\nPROVIDE ( r_lm_reset_sync = 0x40051304 );\nPROVIDE ( r_lm_role_switch_finished = 0x4004f028 );\nPROVIDE ( r_lm_role_switch_start = 0x4004efe0 );\nPROVIDE ( r_lm_sco_nego_end = 0x40051828 );\nPROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 );\nPROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 );\nPROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc );\nPROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 );\nPROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 );\nPROVIDE ( r_lm_sp_n_one = 0x400123a4 );\nPROVIDE ( r_lm_sp_p192_add = 0x40012828 );\nPROVIDE ( r_lm_sp_p192_dbl = 0x4001268c );\nPROVIDE ( r_lm_sp_p192_invert = 0x40012b6c );\nPROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 );\nPROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 );\nPROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 );\nPROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 );\nPROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 );\nPROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 );\nPROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 );\nPROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 );\nPROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 );\nPROVIDE ( r_modules_funcs = 0x3ffafd6c );\nPROVIDE ( r_modules_funcs_p = 0x3ffafd68 );\nPROVIDE ( r_nvds_del = 0x400544c4 );\nPROVIDE ( r_nvds_get = 0x40054488 );\nPROVIDE ( r_nvds_init = 0x40054410 );\nPROVIDE ( r_nvds_lock = 0x400544fc );\nPROVIDE ( r_nvds_put = 0x40054534 );\nPROVIDE ( rom_abs_temp = 0x400054f0 );\nPROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c );\nPROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac );\nPROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 );\nPROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 );\nPROVIDE ( rom_bb_wdg_test_en = 0x40003b70 );\nPROVIDE ( rom_cbw2040_cfg = 0x400040b0 );\nPROVIDE ( rom_check_noise_floor = 0x40003c78 );\nPROVIDE ( rom_chip_i2c_readReg = 0x40004110 );\nPROVIDE ( rom_chip_i2c_writeReg = 0x40004168 );\nPROVIDE ( rom_chip_v7_bt_init = 0x40004d8c );\nPROVIDE ( rom_chip_v7_rx_init = 0x40004cec );\nPROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 );\nPROVIDE ( rom_chip_v7_tx_init = 0x40004d18 );\nPROVIDE ( rom_clk_force_on_vit = 0x40003710 );\nPROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 );\nPROVIDE ( rom_dc_iq_est = 0x400055c8 );\nPROVIDE ( rom_disable_agc = 0x40002fa4 );\nPROVIDE ( rom_enable_agc = 0x40002fcc );\nPROVIDE ( rom_en_pwdet = 0x4000506c );\nPROVIDE ( rom_gen_rx_gain_table = 0x40003e3c );\nPROVIDE ( rom_get_data_sat = 0x4000312c );\nPROVIDE ( rom_get_fm_sar_dout = 0x40005204 );\nPROVIDE ( rom_get_power_db = 0x40005fc8 );\nPROVIDE ( rom_get_pwctrl_correct = 0x400065d4 );\nPROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc );\nPROVIDE ( rom_get_rf_gain_qdb = 0x40006290 );\nPROVIDE ( rom_get_sar_dout = 0x40006564 );\nPROVIDE ( rom_i2c_readReg = 0x40004148 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x400041c0 );\nPROVIDE ( rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x400041fc );\nPROVIDE ( rom_index_to_txbbgain = 0x40004df8 );\nPROVIDE ( rom_iq_est_disable = 0x40005590 );\nPROVIDE ( rom_iq_est_enable = 0x40005514 );\nPROVIDE ( rom_linear_to_db = 0x40005f64 );\nPROVIDE ( rom_loopback_mode_en = 0x400030f8 );\nPROVIDE ( rom_meas_tone_pwr_db = 0x40006004 );\nPROVIDE ( rom_mhz2ieee = 0x4000404c );\nPROVIDE ( rom_noise_floor_auto_set = 0x40003bdc );\nPROVIDE ( rom_pbus_debugmode = 0x40004458 );\nPROVIDE ( rom_pbus_force_mode = 0x40004270 );\nPROVIDE ( rom_pbus_force_test = 0x400043c0 );\nPROVIDE ( rom_pbus_rd = 0x40004414 );\nPROVIDE ( rom_pbus_rd_addr = 0x40004334 );\nPROVIDE ( rom_pbus_rd_shift = 0x40004374 );\nPROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 );\nPROVIDE ( rom_pbus_set_dco = 0x40004638 );\nPROVIDE ( rom_pbus_set_rxgain = 0x40004480 );\nPROVIDE ( rom_pbus_workmode = 0x4000446c );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 );\nPROVIDE ( rom_phy_disable_agc = 0x40002f6c );\nPROVIDE ( rom_phy_disable_cca = 0x40003000 );\nPROVIDE ( rom_phy_enable_agc = 0x40002f88 );\nPROVIDE ( rom_phy_enable_cca = 0x4000302c );\nPROVIDE ( rom_phy_freq_correct = 0x40004b44 );\nPROVIDE ( rom_phyFuns = 0x3ffae0c0 );\nPROVIDE ( rom_phy_get_noisefloor = 0x40003c2c );\nPROVIDE ( rom_phy_get_vdd33 = 0x4000642c );\nPROVIDE ( rom_pow_usr = 0x40003044 );\nPROVIDE ( rom_read_sar_dout = 0x400051c0 );\nPROVIDE ( rom_restart_cal = 0x400046e0 );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40006058 );\nPROVIDE ( rom_rfcal_rxiq = 0x40005b4c );\nPROVIDE ( rom_rfcal_txcap = 0x40005dec );\nPROVIDE ( rom_rfpll_reset = 0x40004680 );\nPROVIDE ( rom_rfpll_set_freq = 0x400047f8 );\nPROVIDE ( rom_rtc_mem_backup = 0x40003db4 );\nPROVIDE ( rom_rtc_mem_recovery = 0x40003df4 );\nPROVIDE ( rom_rx_gain_force = 0x4000351c );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 );\nPROVIDE ( rom_rxiq_get_mis = 0x400058e4 );\nPROVIDE ( rom_rxiq_set_reg = 0x40005a00 );\nPROVIDE ( rom_set_cal_rxdc = 0x400030b8 );\nPROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 );\nPROVIDE ( rom_set_channel_freq = 0x40004880 );\nPROVIDE ( rom_set_loopback_gain = 0x40003060 );\nPROVIDE ( rom_set_noise_floor = 0x40003d48 );\nPROVIDE ( rom_set_pbus_mem = 0x400031a4 );\nPROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 );\nPROVIDE ( rom_set_rxclk_en = 0x40003594 );\nPROVIDE ( rom_set_txcap_reg = 0x40005d50 );\nPROVIDE ( rom_set_txclk_en = 0x40003564 );\nPROVIDE ( rom_spur_coef_cfg = 0x40003ac8 );\nPROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 );\nPROVIDE ( rom_start_tx_tone = 0x400036b4 );\nPROVIDE ( rom_start_tx_tone_step = 0x400035d0 );\nPROVIDE ( rom_stop_tx_tone = 0x40003f98 );\nPROVIDE ( _rom_store = 0x4000d66c );\nPROVIDE ( _rom_store_table = 0x4000d4f8 );\nPROVIDE ( rom_target_power_add_backoff = 0x40006268 );\nPROVIDE ( rom_tx_atten_set_interp = 0x400061cc );\nPROVIDE ( rom_txbbgain_to_index = 0x40004dc0 );\nPROVIDE ( rom_txcal_work_mode = 0x4000510c );\nPROVIDE ( rom_txdc_cal_init = 0x40004e10 );\nPROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 );\nPROVIDE ( rom_txiq_cover = 0x4000538c );\nPROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc );\nPROVIDE ( rom_txiq_set_reg = 0x40005154 );\nPROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c );\nPROVIDE ( rom_txtone_linear_pwr = 0x40005290 );\nPROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 );\nPROVIDE ( rom_write_gain_mem = 0x4000348c );\nPROVIDE ( rom_write_rfpll_sdm = 0x40004740 );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( r_plf_funcs_p = 0x3ffb8360 );\nPROVIDE ( r_rf_rw_bt_init = 0x40054868 );\nPROVIDE ( r_rf_rw_init = 0x40054b0c );\nPROVIDE ( r_rf_rw_le_init = 0x400549d0 );\nPROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c );\nPROVIDE ( r_rwble_init = 0x40054bf4 );\nPROVIDE ( r_rwble_isr = 0x40054e08 );\nPROVIDE ( r_rwble_reset = 0x40054ce8 );\nPROVIDE ( r_rwble_sleep_check = 0x40054d78 );\nPROVIDE ( r_rwble_version = 0x40054dac );\nPROVIDE ( r_rwbt_init = 0x40055160 );\nPROVIDE ( r_rwbt_isr = 0x40055248 );\nPROVIDE ( r_rwbt_reset = 0x400551bc );\nPROVIDE ( r_rwbt_sleep_check = 0x4005577c );\nPROVIDE ( r_rwbt_sleep_enter = 0x400557a4 );\nPROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc );\nPROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc );\nPROVIDE ( r_rwbt_version = 0x4005520c );\nPROVIDE ( r_rwip_assert_err = 0x40055f88 );\nPROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc );\nPROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c );\nPROVIDE ( r_rwip_init = 0x4005595c );\nPROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 );\nPROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 );\nPROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 );\nPROVIDE ( r_rwip_reset = 0x40055ab8 );\nPROVIDE ( r_rwip_schedule = 0x40055b38 );\nPROVIDE ( r_rwip_sleep = 0x40055b5c );\nPROVIDE ( r_rwip_sleep_enable = 0x40055f30 );\nPROVIDE ( r_rwip_version = 0x40055b20 );\nPROVIDE ( r_rwip_wakeup = 0x40055dc4 );\nPROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c );\nPROVIDE ( r_rwip_wakeup_end = 0x40055e18 );\nPROVIDE ( r_rwip_wlcoex_set = 0x40055f60 );\nPROVIDE ( r_SHA_256 = 0x40013a90 );\nPROVIDE ( rwip_coex_cfg = 0x3ff9914c );\nPROVIDE ( rwip_priority = 0x3ff99159 );\nPROVIDE ( rwip_rf = 0x3ffbdb28 );\nPROVIDE ( rwip_rf_p_get = 0x400558f4 );\nPROVIDE ( r_XorKey = 0x400112c0 );\nPROVIDE ( sbrk = 0x400017f4 );\nPROVIDE ( _sbrk_r = 0x4000bce4 );\nPROVIDE ( __sccl = 0x4000c498 );\nPROVIDE ( __sclose = 0x400011b8 );\nPROVIDE ( __seofread = 0x40001148 );\nPROVIDE ( setjmp = 0x40056268 );\nPROVIDE ( setlocale = 0x40059568 );\nPROVIDE ( _setlocale_r = 0x4005950c );\nPROVIDE ( __sf_fake_stderr = 0x3ff96458 );\nPROVIDE ( __sf_fake_stdin = 0x3ff96498 );\nPROVIDE ( __sf_fake_stdout = 0x3ff96478 );\nPROVIDE ( __sflush_r = 0x400591e0 );\nPROVIDE ( __sfmoreglue = 0x40001dc8 );\nPROVIDE ( __sfp = 0x40001e90 );\nPROVIDE ( __sfp_lock_acquire = 0x40001e08 );\nPROVIDE ( __sfp_lock_release = 0x40001e14 );\nPROVIDE ( __sfputs_r = 0x40057790 );\nPROVIDE ( __sfvwrite_r = 0x4005893c );\nPROVIDE ( sha1_prf = 0x40060ae8 );\nPROVIDE ( sha1_vector = 0x40060b64 );\nPROVIDE ( sha256_prf = 0x40060d70 );\nPROVIDE ( sha256_vector = 0x40060e08 );\nPROVIDE ( sha_blk_bits = 0x3ff99290 );\nPROVIDE ( sha_blk_bits_bytes = 0x3ff99288 );\nPROVIDE ( sha_blk_hash_bytes = 0x3ff9928c );\nPROVIDE ( sig_matrix = 0x3ffae293 );\nPROVIDE ( __sinit = 0x40001e38 );\nPROVIDE ( __sinit_lock_acquire = 0x40001e20 );\nPROVIDE ( __sinit_lock_release = 0x40001e2c );\nPROVIDE ( sip_after_tx_complete = 0x4000b358 );\nPROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c );\nPROVIDE ( sip_get_ptr = 0x4000b34c );\nPROVIDE ( sip_get_state = 0x4000ae2c );\nPROVIDE ( sip_init_attach = 0x4000ae58 );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 );\nPROVIDE ( sip_install_rx_data_cb = 0x4000ae20 );\nPROVIDE ( sip_is_active = 0x4000b3c0 );\nPROVIDE ( sip_post_init = 0x4000aed8 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c );\nPROVIDE ( sip_send = 0x4000af54 );\nPROVIDE ( sip_to_host_chain_append = 0x4000aef8 );\nPROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 );\nPROVIDE ( slc_add_credits = 0x4000baf4 );\nPROVIDE ( slc_enable = 0x4000b64c );\nPROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 );\nPROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 );\nPROVIDE ( slc_has_pkt_to_host = 0x4000b5fc );\nPROVIDE ( slc_init_attach = 0x4000b918 );\nPROVIDE ( slc_init_credit = 0x4000badc );\nPROVIDE ( slc_reattach = 0x4000b62c );\nPROVIDE ( slc_send_to_host_chain = 0x4000b6a0 );\nPROVIDE ( slc_set_host_io_max_window = 0x4000b89c );\nPROVIDE ( slc_to_host_chain_recycle = 0x4000b758 );\nPROVIDE ( __smakebuf_r = 0x40059108 );\nPROVIDE ( specialModP256 = 0x4001600c );\nPROVIDE ( srand = 0x40001004 );\nPROVIDE ( __sread = 0x40001118 );\nPROVIDE ( __srefill_r = 0x400593d4 );\nPROVIDE ( __sseek = 0x40001184 );\nPROVIDE ( __ssprint_r = 0x40056ff8 );\nPROVIDE ( __ssputs_r = 0x40056f2c );\nPROVIDE ( __ssrefill_r = 0x40057fec );\nPROVIDE ( __stack = 0x3ffe3f20 );\nPROVIDE ( __stack_app = 0x3ffe7e30 );\nPROVIDE ( _stack_sentry = 0x3ffe1320 );\nPROVIDE ( _stack_sentry_app = 0x3ffe5230 );\nPROVIDE ( _start = 0x40000704 );\nPROVIDE ( start_tb_console = 0x4005a980 );\nPROVIDE ( _stat_r = 0x4000bcb4 );\nPROVIDE ( _stext = 0x40000560 );\nPROVIDE ( strcasecmp = 0x400011cc );\nPROVIDE ( strcasestr = 0x40001210 );\nPROVIDE ( strcat = 0x4000c518 );\nPROVIDE ( strchr = 0x4000c53c );\nPROVIDE ( strcmp = 0x40001274 );\nPROVIDE ( strcoll = 0x40001398 );\nPROVIDE ( strcpy = 0x400013ac );\nPROVIDE ( strcspn = 0x4000c558 );\nPROVIDE ( strdup = 0x4000143c );\nPROVIDE ( _strdup_r = 0x40001450 );\nPROVIDE ( strftime = 0x40059ab4 );\nPROVIDE ( strlcat = 0x40001470 );\nPROVIDE ( strlcpy = 0x4000c584 );\nPROVIDE ( strlen = 0x400014c0 );\nPROVIDE ( strlwr = 0x40001524 );\nPROVIDE ( strncasecmp = 0x40001550 );\nPROVIDE ( strncat = 0x4000c5c4 );\nPROVIDE ( strncmp = 0x4000c5f4 );\nPROVIDE ( strncpy = 0x400015d4 );\nPROVIDE ( strndup = 0x400016b0 );\nPROVIDE ( _strndup_r = 0x400016c4 );\nPROVIDE ( strnlen = 0x4000c628 );\nPROVIDE ( strrchr = 0x40001708 );\nPROVIDE ( strsep = 0x40001734 );\nPROVIDE ( strspn = 0x4000c648 );\nPROVIDE ( strstr = 0x4000c674 );\nPROVIDE ( __strtok_r = 0x4000c6a8 );\nPROVIDE ( strtok_r = 0x4000c70c );\nPROVIDE ( strtol = 0x4005681c );\nPROVIDE ( _strtol_r = 0x40056714 );\nPROVIDE ( strtoul = 0x4005692c );\nPROVIDE ( _strtoul_r = 0x40056834 );\nPROVIDE ( strupr = 0x4000174c );\nPROVIDE ( __subdf3 = 0x400026e4 );\nPROVIDE ( __submore = 0x40058f3c );\nPROVIDE ( __subsf3 = 0x400021d0 );\nPROVIDE ( SubtractBigHex256 = 0x40015bcc );\nPROVIDE ( SubtractBigHexMod256 = 0x40015e8c );\nPROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c );\nPROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 );\nPROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 );\nPROVIDE ( __subvdi3 = 0x40002d20 );\nPROVIDE ( __subvsi3 = 0x40002cf8 );\nPROVIDE ( _sungetc_r = 0x40057f6c );\nPROVIDE ( __swbuf = 0x40058cb4 );\nPROVIDE ( __swbuf_r = 0x40058bec );\nPROVIDE ( __swrite = 0x40001150 );\nPROVIDE ( __swsetup_r = 0x40058cc8 );\nPROVIDE ( sw_to_hw = 0x3ffb8d40 );\nPROVIDE ( syscall_table_ptr_app = 0x3ffae020 );\nPROVIDE ( syscall_table_ptr_pro = 0x3ffae024 );\nPROVIDE ( _system_r = 0x4000bc10 );\nPROVIDE ( tdefl_compress = 0x400600bc );\nPROVIDE ( tdefl_compress_buffer = 0x400607f4 );\nPROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 );\nPROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 );\nPROVIDE ( tdefl_get_adler32 = 0x400608d8 );\nPROVIDE ( tdefl_get_prev_return_status = 0x400608d0 );\nPROVIDE ( tdefl_init = 0x40060810 );\nPROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c );\nPROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 );\nPROVIDE ( time = 0x40001844 );\nPROVIDE ( __time_load_locale = 0x4000183c );\nPROVIDE ( times = 0x40001808 );\nPROVIDE ( _times_r = 0x4000bc40 );\nPROVIDE ( _timezone = 0x3ffae0a0 );\nPROVIDE ( tinfl_decompress = 0x4005ef30 );\nPROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 );\nPROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 );\nPROVIDE ( toascii = 0x4000c720 );\nPROVIDE ( tolower = 0x40001868 );\nPROVIDE ( toupper = 0x40001884 );\nPROVIDE ( __truncdfsf2 = 0x40002b90 );\nPROVIDE ( __tzcalc_limits = 0x400018a0 );\nPROVIDE ( __tz_lock = 0x40001a04 );\nPROVIDE ( _tzname = 0x3ffae030 );\nPROVIDE ( tzset = 0x40001a1c );\nPROVIDE ( _tzset_r = 0x40001a28 );\nPROVIDE ( __tz_unlock = 0x40001a10 );\nPROVIDE ( UartDev = 0x3ffe019c );\nPROVIDE ( __ucmpdi2 = 0x40063840 );\nPROVIDE ( __udivdi3 = 0x4000cff8 );\nPROVIDE ( __udivmoddi4 = 0x40064ab0 );\nPROVIDE ( __udivsi3 = 0x4000c7c8 );\nPROVIDE ( __udiv_w_sdiv = 0x40064aa8 );\nPROVIDE ( __umoddi3 = 0x4000d280 );\nPROVIDE ( __umodsi3 = 0x4000c7d0 );\nPROVIDE ( __umulsidi3 = 0x4000c7d8 );\nPROVIDE ( ungetc = 0x400590f4 );\nPROVIDE ( _ungetc_r = 0x40058fa0 );\nPROVIDE ( _unlink_r = 0x4000bc84 );\nPROVIDE ( __unorddf2 = 0x400637f4 );\nPROVIDE ( __unordsf2 = 0x40063478 );\nPROVIDE ( user_code_start = 0x3ffe0400 );\nPROVIDE ( utoa = 0x40056258 );\nPROVIDE ( __utoa = 0x400561f0 );\nPROVIDE ( veryBigHexP256 = 0x3ff9736c );\nPROVIDE ( wcrtomb = 0x40058920 );\nPROVIDE ( _wcrtomb_r = 0x400588d8 );\nPROVIDE ( __wctomb = 0x3ff96540 );\nPROVIDE ( _wctomb_r = 0x40058f14 );\nPROVIDE ( write = 0x4000181c );\nPROVIDE ( _write_r = 0x4000bd70 );\nPROVIDE ( xthal_bcopy = 0x4000c098 );\nPROVIDE ( xthal_copy123 = 0x4000c124 );\nPROVIDE ( xthal_get_ccompare = 0x4000c078 );\nPROVIDE ( xthal_get_ccount = 0x4000c050 );\nPROVIDE ( xthal_get_interrupt = 0x4000c1e4 );\nPROVIDE ( xthal_get_intread = 0x4000c1e4 );\nPROVIDE ( Xthal_intlevel = 0x3ff9c2b4 );\nPROVIDE ( xthal_memcpy = 0x4000c0bc );\nPROVIDE ( xthal_set_ccompare = 0x4000c058 );\nPROVIDE ( xthal_set_intclear = 0x4000c1ec );\nPROVIDE ( _xtos_set_intlevel = 0x4000bfdc );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( esp_rom_spiflash_config_param = 0x40063238 );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );\nPROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 );\nPROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 );\nPROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c );\nPROVIDE ( esp_rom_spiflash_select_qio_pins = 0x40061ddc );\nPROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );\n\n\/* \nThese functions are xtos-related (or call xtos-related functions) and do not play well \nwith multicore FreeRTOS. Where needed, we provide alternatives that are multicore\ncompatible. These functions also use a chunk of static RAM, by not using them we can\nallocate that RAM for general use.\n*\/\n\/*\nPROVIDE ( _DebugExceptionVector = 0x40000280 );\nPROVIDE ( _DoubleExceptionVector = 0x400003c0 );\nPROVIDE ( _KernelExceptionVector = 0x40000300 );\nPROVIDE ( _GeneralException = 0x40000e14 );\nPROVIDE ( _ResetHandler = 0x40000450 );\nPROVIDE ( _ResetVector = 0x40000400 );\nPROVIDE ( _UserExceptionVector = 0x40000340 );\nPROVIDE ( _NMIExceptionVector = 0x400002c0 );\nPROVIDE ( _WindowOverflow12 = 0x40000100 );\nPROVIDE ( _WindowOverflow4 = 0x40000000 );\nPROVIDE ( _WindowOverflow8 = 0x40000080 );\nPROVIDE ( _WindowUnderflow12 = 0x40000140 );\nPROVIDE ( _WindowUnderflow4 = 0x40000040 );\nPROVIDE ( _WindowUnderflow8 = 0x400000c0 );\nPROVIDE ( _Level2FromVector = 0x40000954 );\nPROVIDE ( _Level3FromVector = 0x40000a28 );\nPROVIDE ( _Level4FromVector = 0x40000af8 );\nPROVIDE ( _Level5FromVector = 0x40000c68 );\nPROVIDE ( _Level2Vector = 0x40000180 );\nPROVIDE ( _Level3Vector = 0x400001c0 );\nPROVIDE ( _Level4Vector = 0x40000200 );\nPROVIDE ( _Level5Vector = 0x40000240 );\nPROVIDE ( _LevelOneInterrupt = 0x40000835 );\nPROVIDE ( _SyscallException = 0x400007cf );\nPROVIDE ( _xtos_alloca_handler = 0x40000010 );\nPROVIDE ( _xtos_cause3_handler = 0x40000dd8 );\nPROVIDE ( _xtos_c_handler_table = 0x3ffe0548 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 );\nPROVIDE ( _xtos_enabled = 0x3ffe0650 );\nPROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 );\nPROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 );\nPROVIDE ( _xtos_interrupt_table = 0x3ffe0658 );\nPROVIDE ( _xtos_ints_off = 0x4000bfac );\nPROVIDE ( _xtos_ints_on = 0x4000bf88 );\nPROVIDE ( _xtos_intstruct = 0x3ffe0650 );\nPROVIDE ( _xtos_l1int_handler = 0x40000814 );\nPROVIDE ( _xtos_p_none = 0x4000bfd4 );\nPROVIDE ( _xtos_restore_intlevel = 0x40000928 );\nPROVIDE ( _xtos_return_from_exc = 0x4000c034 );\nPROVIDE ( _xtos_set_exception_handler = 0x4000074c );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 );\nPROVIDE ( _xtos_set_vpri = 0x40000934 );\nPROVIDE ( _xtos_syscall_handler = 0x40000790 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000c024 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c );\nPROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 );\nPROVIDE ( ets_intr_count = 0x3ffe03fc );\n*\/\n\n\/* These functions are part of the UART downloader but also contain general UART functions. *\/\nPROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x40008860 );\nPROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 );\nPROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec );\nPROVIDE ( MemDwnLdStartMsgProc = 0x40008948 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc );\nPROVIDE ( MemPacketSendReqMsgProc = 0x40008978 );\nPROVIDE ( uart_baudrate_detect = 0x40009034 );\nPROVIDE ( uart_buff_switch = 0x400093c0 );\nPROVIDE ( UartConnCheck = 0x40008738 );\nPROVIDE ( UartConnectProc = 0x40008a04 );\nPROVIDE ( UartDwnLdProc = 0x40008ce8 );\nPROVIDE ( UartRegReadProc = 0x40008a58 );\nPROVIDE ( UartRegWriteProc = 0x40008a14 );\nPROVIDE ( UartSetBaudProc = 0x40008aac );\nPROVIDE ( UartSpiAttachProc = 0x40008a6c );\nPROVIDE ( UartSpiReadProc = 0x40008a80 );\nPROVIDE ( VerifyFlashMd5Proc = 0x40008c44 );\nPROVIDE ( GetUartDevice = 0x40009598 );\nPROVIDE ( RcvMsg = 0x4000954c );\nPROVIDE ( SendMsg = 0x40009384 );\nPROVIDE ( UartGetCmdLn = 0x40009564 );\nPROVIDE ( UartRxString = 0x400092fc );\nPROVIDE ( Uart_Init = 0x40009120 );\nPROVIDE ( recv_packet = 0x40009424 );\nPROVIDE ( send_packet = 0x40009340 );\nPROVIDE ( uartAttach = 0x40008fd0 );\nPROVIDE ( uart_div_modify = 0x400090cc );\nPROVIDE ( uart_rx_intr_handler = 0x40008f4c );\nPROVIDE ( uart_rx_one_char = 0x400092d0 );\nPROVIDE ( uart_rx_one_char_block = 0x400092a4 );\nPROVIDE ( uart_rx_readbuff = 0x40009394 );\nPROVIDE ( uart_tx_flush = 0x40009258 );\nPROVIDE ( uart_tx_one_char = 0x40009200 );\nPROVIDE ( uart_tx_one_char2 = 0x4000922c );\nPROVIDE ( uart_tx_switch = 0x40009028 );\nPROVIDE ( uart_tx_wait_idle = 0x40009278 );\n\n\n\/*\nThese functions are part of the ROM GPIO driver. We do not use them; the provided esp-idf functions\nreplace them and this way we can re-use the fixed RAM addresses these routines need.\n*\/\n\/* <-- So you don't read over it: This comment disables the next lines.\nPROVIDE ( gpio_init = 0x40009c20 );\nPROVIDE ( gpio_intr_ack = 0x40009dd4 );\nPROVIDE ( gpio_intr_ack_high = 0x40009e1c );\nPROVIDE ( gpio_intr_handler_register = 0x40009e6c );\nPROVIDE ( gpio_intr_pending = 0x40009cec );\nPROVIDE ( gpio_intr_pending_high = 0x40009cf8 );\nPROVIDE ( gpio_pending_mask = 0x3ffe0038 );\nPROVIDE ( gpio_pending_mask_high = 0x3ffe0044 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40009d04 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c );\nPROVIDE ( gpio_register_get = 0x40009cbc );\nPROVIDE ( gpio_register_set = 0x40009bbc );\n*\/\n\/* These are still part of that driver, but have been verified not to use static RAM, so they can be used. *\/\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( gpio_input_get = 0x40009b88 );\nPROVIDE ( gpio_input_get_high = 0x40009b9c );\nPROVIDE ( gpio_matrix_in = 0x40009edc );\nPROVIDE ( gpio_matrix_out = 0x40009f0c );\nPROVIDE ( gpio_pad_select_gpio = 0x40009fdc );\nPROVIDE ( gpio_pad_set_drv = 0x4000a11c );\nPROVIDE ( gpio_pad_pulldown = 0x4000a348 );\nPROVIDE ( gpio_pad_pullup = 0x4000a22c );\nPROVIDE ( gpio_pad_hold = 0x4000a734 );\nPROVIDE ( gpio_pad_unhold = 0x4000a484 );\n\n\/*\nThese functions are part of the non-os kernel (etsc).\n*\/\nPROVIDE ( ets_aes_crypt = 0x4005c9b8 );\nPROVIDE ( ets_aes_disable = 0x4005c8f8 );\nPROVIDE ( ets_aes_enable = 0x4005c8cc );\nPROVIDE ( ets_aes_set_endian = 0x4005c928 );\nPROVIDE ( ets_aes_setkey_dec = 0x4005c994 );\nPROVIDE ( ets_aes_setkey_enc = 0x4005c97c );\nPROVIDE ( ets_bigint_disable = 0x4005c4e0 );\nPROVIDE ( ets_bigint_enable = 0x4005c498 );\nPROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 );\nPROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 );\nPROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 );\nPROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c );\nPROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 );\nPROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc );\nPROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 );\nPROVIDE ( ets_bigint_mult_prepare = 0x4005c630 );\nPROVIDE ( ets_bigint_wait_finish = 0x4005c520 );\nPROVIDE ( ets_post = 0x4000673c );\nPROVIDE ( ets_run = 0x400066bc );\nPROVIDE ( ets_set_idle_cb = 0x40006674 );\nPROVIDE ( ets_task = 0x40006688 );\nPROVIDE ( ets_efuse_get_8M_clock = 0x40008710 );\nPROVIDE ( ets_efuse_get_spiconfig = 0x40008658 );\nPROVIDE ( ets_efuse_program_op = 0x40008628 );\nPROVIDE ( ets_efuse_read_op = 0x40008600 );\nPROVIDE ( ets_intr_lock = 0x400067b0 );\nPROVIDE ( ets_intr_unlock = 0x400067c4 );\nPROVIDE ( ets_isr_attach = 0x400067ec );\nPROVIDE ( ets_isr_mask = 0x400067fc );\nPROVIDE ( ets_isr_unmask = 0x40006808 );\nPROVIDE ( ets_waiti0 = 0x400067d8 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( check_pos = 0x400068b8 );\nPROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( ets_set_startup_callback = 0x4000688c );\nPROVIDE ( ets_set_user_start = 0x4000687c );\nPROVIDE ( ets_unpack_flash_code = 0x40007018 );\nPROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c );\nPROVIDE ( rom_main = 0x400076c4 );\nPROVIDE ( ets_install_putc1 = 0x40007d18 );\nPROVIDE ( ets_install_putc2 = 0x40007d38 );\nPROVIDE ( ets_install_uart_printf = 0x40007d28 );\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( rtc_boot_control = 0x4000821c );\nPROVIDE ( rtc_get_reset_reason = 0x400081d4 );\nPROVIDE ( rtc_get_wakeup_cause = 0x400081f4 );\nPROVIDE ( rtc_select_apb_bridge = 0x40008288 );\nPROVIDE ( set_rtc_memory_crc = 0x40008208 );\nPROVIDE ( software_reset = 0x4000824c );\nPROVIDE ( software_reset_cpu = 0x40008264 );\nPROVIDE ( ets_secure_boot_check = 0x4005cb40 );\nPROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 );\nPROVIDE ( ets_secure_boot_check_start = 0x4005cbcc );\nPROVIDE ( ets_secure_boot_finish = 0x4005ca84 );\nPROVIDE ( ets_secure_boot_hash = 0x4005cad4 );\nPROVIDE ( ets_secure_boot_obtain = 0x4005cb14 );\nPROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 );\nPROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 );\nPROVIDE ( ets_secure_boot_start = 0x4005ca34 );\nPROVIDE ( ets_sha_disable = 0x4005c0a8 );\nPROVIDE ( ets_sha_enable = 0x4005c07c );\nPROVIDE ( ets_sha_finish = 0x4005c104 );\nPROVIDE ( ets_sha_init = 0x4005c0d4 );\nPROVIDE ( ets_sha_update = 0x4005c2a0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( ets_get_cpu_frequency = 0x4000855c );\nPROVIDE ( ets_get_detected_xtal_freq = 0x40008588 );\nPROVIDE ( ets_get_xtal_scale = 0x4000856c );\nPROVIDE ( ets_timer_arm = 0x40008368 );\nPROVIDE ( ets_timer_arm_us = 0x400083ac );\nPROVIDE ( ets_timer_disarm = 0x400083ec );\nPROVIDE ( ets_timer_done = 0x40008428 );\nPROVIDE ( ets_timer_handler_isr = 0x40008454 );\nPROVIDE ( ets_timer_init = 0x400084e8 );\nPROVIDE ( ets_timer_setfn = 0x40008350 );\nPROVIDE ( ets_update_cpu_frequency_rom = 0x40008550 );  \/* Updates g_ticks_per_us on the current CPU only; not on the other core *\/\n\n\/* Following are static data, but can be used, not generated by script <<<<< btdm data *\/\nPROVIDE ( ld_acl_env = 0x3ffb8258 );\nPROVIDE ( ld_active_ch_map = 0x3ffb8334 );\nPROVIDE ( ld_bcst_acl_env = 0x3ffb8274 );\nPROVIDE ( ld_csb_rx_env = 0x3ffb8278 );\nPROVIDE ( ld_csb_tx_env = 0x3ffb827c );\nPROVIDE ( ld_env = 0x3ffb9510 );\nPROVIDE ( ld_fm_env = 0x3ffb8284 );\nPROVIDE ( ld_inq_env = 0x3ffb82e4 );\nPROVIDE ( ld_iscan_env = 0x3ffb82e8 );\nPROVIDE ( ld_page_env = 0x3ffb82f0 );\nPROVIDE ( ld_pca_env = 0x3ffb82f4 );\nPROVIDE ( ld_pscan_env = 0x3ffb8308 );\nPROVIDE ( ld_sched_env = 0x3ffb830c );\nPROVIDE ( ld_sched_params = 0x3ffb96c0 );\nPROVIDE ( ld_sco_env = 0x3ffb824c );\nPROVIDE ( ld_sscan_env = 0x3ffb832c );\nPROVIDE ( ld_strain_env = 0x3ffb8330 );\nPROVIDE ( LM_Sniff = 0x3ffb8230 );\nPROVIDE ( LM_SniffSubRate = 0x3ffb8214 );\nPROVIDE ( prbs_64bytes = 0x3ff98992 );\n\/* Above are static data, but can be used, not generated by script >>>>> btdm data *\/\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3fbbbecec9537c56646e9dcd160e393a3f0e0828","subject":"esp8266: Put more code in iROM section.","message":"esp8266: Put more code in iROM section.\n\nAlso explicitly name the py\/*.o files in the linker file, to enable easy\ntesting of putting certain ones in iRAM.\n","repos":"PappaPeppar\/micropython,oopy\/micropython,blazewicz\/micropython,adafruit\/micropython,Peetz0r\/micropython-esp32,swegener\/micropython,mhoffma\/micropython,pozetroninc\/micropython,bvernoux\/micropython,HenrikSolver\/micropython,jmarcelino\/pycom-micropython,TDAbboud\/micropython,dxxb\/micropython,Timmenem\/micropython,jmarcelino\/pycom-micropython,dmazzella\/micropython,misterdanb\/micropython,drrk\/micropython,adafruit\/circuitpython,tobbad\/micropython,matthewelse\/micropython,PappaPeppar\/micropython,infinnovation\/micropython,bvernoux\/micropython,lowRISC\/micropython,Peetz0r\/micropython-esp32,drrk\/micropython,matthewelse\/micropython,selste\/micropython,dxxb\/micropython,PappaPeppar\/micropython,redbear\/micropython,redbear\/micropython,turbinenreiter\/micropython,adafruit\/micropython,henriknelson\/micropython,oopy\/micropython,torwag\/micropython,puuu\/micropython,Peetz0r\/micropython-esp32,dinau\/micropython,ganshun666\/micropython,toolmacher\/micropython,chrisdearman\/micropython,micropython\/micropython-esp32,Peetz0r\/micropython-esp32,adafruit\/micropython,kerneltask\/micropython,swegener\/micropython,dinau\/micropython,jmarcelino\/pycom-micropython,praemdonck\/micropython,kerneltask\/micropython,tuc-osg\/micropython,emfcamp\/micropython,dmazzella\/micropython,kerneltask\/micropython,MrSurly\/micropython,ryannathans\/micropython,deshipu\/micropython,drrk\/micropython,SHA2017-badge\/micropython-esp32,chrisdearman\/micropython,puuu\/micropython,HenrikSolver\/micropython,hosaka\/micropython,adafruit\/circuitpython,HenrikSolver\/micropython,TDAbboud\/micropython,blazewicz\/micropython,adafruit\/circuitpython,tobbad\/micropython,AriZuu\/micropython,hosaka\/micropython,PappaPeppar\/micropython,henriknelson\/micropython,torwag\/micropython,toolmacher\/micropython,tralamazza\/micropython,adafruit\/circuitpython,puuu\/micropython,pozetroninc\/micropython,kerneltask\/micropython,MrSurly\/micropython-esp32,misterdanb\/micropython,hosaka\/micropython,torwag\/micropython,praemdonck\/micropython,Peetz0r\/micropython-esp32,mpalomer\/micropython,MrSurly\/micropython,mpalomer\/micropython,HenrikSolver\/micropython,chrisdearman\/micropython,emfcamp\/micropython,puuu\/micropython,TDAbboud\/micropython,turbinenreiter\/micropython,dmazzella\/micropython,MrSurly\/micropython-esp32,dxxb\/micropython,drrk\/micropython,tobbad\/micropython,hiway\/micropython,SHA2017-badge\/micropython-esp32,trezor\/micropython,infinnovation\/micropython,alex-robbins\/micropython,ganshun666\/micropython,cwyark\/micropython,mhoffma\/micropython,misterdanb\/micropython,cwyark\/micropython,toolmacher\/micropython,TDAbboud\/micropython,deshipu\/micropython,pozetroninc\/micropython,TDAbboud\/micropython,turbinenreiter\/micropython,chrisdearman\/micropython,HenrikSolver\/micropython,Timmenem\/micropython,mpalomer\/micropython,ryannathans\/micropython,MrSurly\/micropython,dmazzella\/micropython,tuc-osg\/micropython,oopy\/micropython,henriknelson\/micropython,bvernoux\/micropython,turbinenreiter\/micropython,adafruit\/circuitpython,ganshun666\/micropython,MrSurly\/micropython-esp32,alex-march\/micropython,pramasoul\/micropython,alex-robbins\/micropython,blazewicz\/micropython,tralamazza\/micropython,selste\/micropython,AriZuu\/micropython,SHA2017-badge\/micropython-esp32,torwag\/micropython,pramasoul\/micropython,mpalomer\/micropython,mpalomer\/micropython,redbear\/micropython,pfalcon\/micropython,dinau\/micropython,blazewicz\/micropython,emfcamp\/micropython,matthewelse\/micropython,SHA2017-badge\/micropython-esp32,jmarcelino\/pycom-micropython,infinnovation\/micropython,Timmenem\/micropython,pfalcon\/micropython,deshipu\/micropython,lowRISC\/micropython,micropython\/micropython-esp32,alex-robbins\/micropython,selste\/micropython,micropython\/micropython-esp32,tuc-osg\/micropython,AriZuu\/micropython,ganshun666\/micropython,emfcamp\/micropython,deshipu\/micropython,ryannathans\/micropython,turbinenreiter\/micropython,hiway\/micropython,swegener\/micropython,infinnovation\/micropython,pramasoul\/micropython,tuc-osg\/micropython,tralamazza\/micropython,misterdanb\/micropython,drrk\/micropython,matthewelse\/micropython,alex-march\/micropython,adafruit\/micropython,alex-march\/micropython,redbear\/micropython,trezor\/micropython,pfalcon\/micropython,cwyark\/micropython,AriZuu\/micropython,lowRISC\/micropython,swegener\/micropython,Timmenem\/micropython,lowRISC\/micropython,ryannathans\/micropython,MrSurly\/micropython,chrisdearman\/micropython,selste\/micropython,emfcamp\/micropython,deshipu\/micropython,pfalcon\/micropython,hosaka\/micropython,mhoffma\/micropython,trezor\/micropython,dxxb\/micropython,praemdonck\/micropython,trezor\/micropython,MrSurly\/micropython-esp32,praemdonck\/micropython,lowRISC\/micropython,alex-robbins\/micropython,hosaka\/micropython,bvernoux\/micropython,matthewelse\/micropython,cwyark\/micropython,ganshun666\/micropython,hiway\/micropython,henriknelson\/micropython,hiway\/micropython,AriZuu\/micropython,trezor\/micropython,misterdanb\/micropython,ryannathans\/micropython,dinau\/micropython,alex-march\/micropython,cwyark\/micropython,Timmenem\/micropython,dinau\/micropython,torwag\/micropython,pfalcon\/micropython,oopy\/micropython,pramasoul\/micropython,praemdonck\/micropython,adafruit\/circuitpython,bvernoux\/micropython,henriknelson\/micropython,hiway\/micropython,oopy\/micropython,tuc-osg\/micropython,pozetroninc\/micropython,kerneltask\/micropython,alex-robbins\/micropython,blazewicz\/micropython,pozetroninc\/micropython,jmarcelino\/pycom-micropython,tobbad\/micropython,puuu\/micropython,pramasoul\/micropython,SHA2017-badge\/micropython-esp32,selste\/micropython,MrSurly\/micropython-esp32,PappaPeppar\/micropython,tobbad\/micropython,alex-march\/micropython,dxxb\/micropython,tralamazza\/micropython,mhoffma\/micropython,infinnovation\/micropython,matthewelse\/micropython,mhoffma\/micropython,redbear\/micropython,micropython\/micropython-esp32,micropython\/micropython-esp32,toolmacher\/micropython,toolmacher\/micropython,swegener\/micropython,MrSurly\/micropython,adafruit\/micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n        *py\/*.o*(.literal* .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *pyexec.o(.literal*, .text*)\n        *readline.o(.literal*, .text*)\n        *pybstdio.o(.literal*, .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *py\/*.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *py\/*.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *py\/*.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3b5e3e9495bd05dc942bda3530d82c3730f9ce24","subject":"Updated linker script to remove UICR sections (now merged separately during build)","message":"Updated linker script to remove UICR sections (now merged separately during build)\n","repos":"HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed","old_file":"targets\/TARGET_NORDIC\/TARGET_NRF5\/TARGET_MCU_NRF52832\/device\/TOOLCHAIN_GCC_ARM\/NRF52832.ld","new_file":"targets\/TARGET_NORDIC\/TARGET_NRF5\/TARGET_MCU_NRF52832\/device\/TOOLCHAIN_GCC_ARM\/NRF52832.ld","new_contents":"\/*\n * Copyright (c) 2015 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\n\n\/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\nHeads Up Modifications to allow configurable application locations\nAlso modified to allow UICR to be written to using the section attribute\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*\/\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x1C000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x64000\n#endif\n\n#if !defined(IMAGE_INFO_OFFSET)\n  #define IMAGE_INFO_OFFSET 0x300\n#endif\n\n\/*\n * UICR -> User Information Configuration Registers\n * UICR_AP -> UICR Access Port Protect (has a couple other functions)\n * Note: This is now taken care of by merging with a separate UICR hex file\n * This was done to avoid build errors with the mbed cli system\n * and to make the build more flexible (for OTA updates, etc)\n *\/\n\nMEMORY\n{\n  IMAGEINFO(r): ORIGIN = MBED_APP_START, LENGTH = IMAGE_INFO_OFFSET\n  FLASH(rx) : ORIGIN = MBED_APP_START+IMAGE_INFO_OFFSET, LENGTH = MBED_APP_SIZE-IMAGE_INFO_OFFSET\n  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0xd108\n  \/*UICR (rw) :  ORIGIN = 0x10001014, LENGTH = 0x8\n  UICR_AP (rw) : ORIGIN = 0x10001200, LENGTH = 0x10*\/\n}\n\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with the other linker script that defines memory regions FLASH and RAM.\n * It references the following symbols that must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines the following symbols that the code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\n\nSECTIONS\n{\n    \/*.vectors :\n    {\n\tKEEP(*(.Vectors))\n    } > VECTORS*\/\n\n    .imageinfo :\n    {\n\tKEEP(*(.ImageInfo))\n    } > IMAGEINFO\n    \n    .text :\n    {\n        KEEP(*(.Vectors))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        PROVIDE(__start_fs_data = .);\n        KEEP(*(.fs_data))\n        PROVIDE(__stop_fs_data = .);\n        \n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    __edata = .;\n\n    .noinit :\n    {\n      PROVIDE(__start_noinit = .);\n      KEEP(*(.noinit))\n      PROVIDE(__stop_noinit = .);\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n\n        \/* Expand the heap to reach the stack boundary. *\/\n        ASSERT(. <= (ORIGIN(RAM) + LENGTH(RAM) - 0x800), \"heap region overflowed into stack\");\n        . += (ORIGIN(RAM) + LENGTH(RAM) - 0x800) - .;\n    } > RAM\n    PROVIDE(__heap_start = ADDR(.heap));\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n\n    \/* .stack_dummy section does not contain any symbols. It is only\n     * used for the linker script to calculate the size of stack sections\n     * and assign values to stack symbols later. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*)\n        . += (ORIGIN(RAM) + LENGTH(RAM) - .);\n    } > RAM\n\n    \/* Set the stack top to the end of RAM and move down the stack limit by\n     * the size of the stack_dummy section. *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Heads Up Modification\n       Creates a memory section for the UICR registers\n       This allows them to be programmed with a\n       .hex file at the factory\n    *\/\n    \/*.uicr :\n    {\n\tKEEP(*(.uicr))\n    } > UICR\n\n    .uicr_ap :\n    {\n\tKEEP(*(.uicr_ap))\n    } > UICR_AP*\/\n\n\n}\n","old_contents":"\/*\n * Copyright (c) 2015 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\n\n\/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\nHeads Up Modifications to allow configurable application locations\nAlso modified to allow UICR to be written to using the section attribute\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*\/\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x1C000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x64000\n#endif\n\n#if !defined(IMAGE_INFO_OFFSET)\n  #define IMAGE_INFO_OFFSET 0x300\n#endif\n\n\/*\n * UICR -> User Information Configuration Registers\n * UICR_AP -> UICR Access Port Protect (has a couple other functions)\n *\/\n\nMEMORY\n{\n  \/*VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x100*\/\n  IMAGEINFO(r): ORIGIN = MBED_APP_START, LENGTH = IMAGE_INFO_OFFSET\n  FLASH(rx) : ORIGIN = MBED_APP_START+IMAGE_INFO_OFFSET, LENGTH = MBED_APP_SIZE-IMAGE_INFO_OFFSET\n  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0xd108\n  UICR (rw) :  ORIGIN = 0x10001014, LENGTH = 0x8\n  UICR_AP (rw) : ORIGIN = 0x10001200, LENGTH = 0x10\n}\n\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with the other linker script that defines memory regions FLASH and RAM.\n * It references the following symbols that must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines the following symbols that the code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\n\nSECTIONS\n{\n    \/*.vectors :\n    {\n\tKEEP(*(.Vectors))\n    } > VECTORS*\/\n\n    .imageinfo :\n    {\n\tKEEP(*(.ImageInfo))\n    } > IMAGEINFO\n    \n    .text :\n    {\n        KEEP(*(.Vectors))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        PROVIDE(__start_fs_data = .);\n        KEEP(*(.fs_data))\n        PROVIDE(__stop_fs_data = .);\n        \n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    __edata = .;\n\n    .noinit :\n    {\n      PROVIDE(__start_noinit = .);\n      KEEP(*(.noinit))\n      PROVIDE(__stop_noinit = .);\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n\n        \/* Expand the heap to reach the stack boundary. *\/\n        ASSERT(. <= (ORIGIN(RAM) + LENGTH(RAM) - 0x800), \"heap region overflowed into stack\");\n        . += (ORIGIN(RAM) + LENGTH(RAM) - 0x800) - .;\n    } > RAM\n    PROVIDE(__heap_start = ADDR(.heap));\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n\n    \/* .stack_dummy section does not contain any symbols. It is only\n     * used for the linker script to calculate the size of stack sections\n     * and assign values to stack symbols later. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*)\n        . += (ORIGIN(RAM) + LENGTH(RAM) - .);\n    } > RAM\n\n    \/* Set the stack top to the end of RAM and move down the stack limit by\n     * the size of the stack_dummy section. *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Heads Up Modification\n       Creates a memory section for the UICR registers\n       This allows them to be programmed with a\n       .hex file at the factory\n    *\/\n    .uicr :\n    {\n\tKEEP(*(.uicr))\n    } > UICR\n\n    .uicr_ap :\n    {\n\tKEEP(*(.uicr_ap))\n    } > UICR_AP\n\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8c83e6401cdfb0fa4eddcc2ea4f29baec6068f99","subject":"fix mach-smdk6410\/xboot.ld","message":"fix mach-smdk6410\/xboot.ld\n","repos":"xboot\/xboot,xboot\/xboot","old_file":"src\/arch\/arm32\/mach-smdk6410\/xboot.ld","new_file":"src\/arch\/arm32\/mach-smdk6410\/xboot.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(_start)\r\n\r\nSTACK_FIQ_SIZE \t= 0x0400;\r\nSTACK_IRQ_SIZE \t= 0x0400;\r\nSTACK_ABT_SIZE \t= 0x0400;\r\nSTACK_UND_SIZE \t= 0x0400;\r\nSTACK_SRV_SIZE \t= 0x8000;\r\n\r\nMEMORY\r\n{\r\n\trom (rx)\t: org = 0x57800000, len = 0x02000000\t\/* 32 MB *\/\r\n\tram (rwx)\t: org = 0x59800000, len = 0x02000000\t\/* 32 MB *\/\r\n}\r\n\r\nSECTIONS\r\n{   \r\n\t.text :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_start = .);\r\n\t\t.obj\/arch\/arm32\/mach-smdk6410\/start.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-smdk6410\/s3c6410-irom.o (.text)\r\n\t\t*(.text)\r\n\t\t*(.text.*)\r\n\t\t*(.init.text)\r\n    \t*(.exit.text)\r\n\r\n    \t. = ALIGN(8);\r\n    \tPROVIDE (__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE (__ksymtab_end = .);\r\n\r\n    \t. = ALIGN(8);\t\r\n\t\tPROVIDE (__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE (__initcall_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE (__exitcall_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE (__romdisk_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\t*(.rodata);\r\n\t\t*(.rodata.*);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\t*(.glue_7);\r\n\t\t*(.glue_7t);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_end = .);\r\n\t} > rom\r\n\r\n\t.data_shadow ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__data_shadow_start = .);\r\n\t\tPROVIDE (__data_shadow_end = (. + SIZEOF (.data)) );\r\n\t} > rom\r\n\r\n\t.data : AT ( ADDR (.data_shadow) )\r\n\t{\r\n\t\tPROVIDE (__data_start = .);\t\r\n\t\t*(.data)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE (__data_end = .);\t\t\r\n\t} > ram\r\n\r\n\t.ARM.exidx :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__exidx_start = .);\r\n\t\t*(.ARM.exidx*)\r\n\t\tPROVIDE (__exidx_end = .);\r\n\t} > ram\r\n\r\n\t.ARM.extab :\r\n\t{\r\n\t\tPROVIDE (__extab_start = .);\r\n\t\t*(.ARM.extab*)\r\n\t\tPROVIDE (__extab_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE (__bss_start = .);\r\n\t\t*(.bss)\r\n\t\t*(.bss.*)\r\n\t\t*(.sbss)\r\n\t\t*(COMMON)\r\n\t\tPROVIDE (__bss_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_start = .);\r\n\t\t*(.heap)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_start = .);\r\n\t\tPROVIDE (__stack_fiq_start = .);\r\n\t\t. += STACK_FIQ_SIZE;\r\n\t\tPROVIDE (__stack_fiq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_irq_start = .);\r\n\t\t. += STACK_IRQ_SIZE;\r\n\t\tPROVIDE (__stack_irq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_abt_start = .);\r\n\t\t. += STACK_ABT_SIZE;\r\n\t\tPROVIDE (__stack_abt_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_und_start = .);\r\n\t\t. += STACK_UND_SIZE;\r\n\t\tPROVIDE (__stack_und_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_srv_start = .);\r\n\t\t. += STACK_SRV_SIZE;\r\n\t\tPROVIDE (__stack_srv_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_end = .);\r\n\t} > ram\r\n\r\n\t\/*\r\n\t * Stabs debugging sections.\r\n\t *\/\r\n\t.stab 0 : { *(.stab) }\r\n\t.stabstr 0 : { *(.stabstr) }\r\n\t.stab.excl 0 : { *(.stab.excl) }\r\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\r\n\t.stab.index 0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment 0 : { *(.comment) }\r\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\r\n\t.debug_info 0 : { *(.debug_info) }\r\n\t.debug_line 0 : { *(.debug_line) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t.debug_aranges 0 : { *(.debug_aranges) }\r\n}\r\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(_start)\r\n\r\n\r\nSTACK_IRQ_SIZE \t= 0x0400;\r\nSTACK_ABT_SIZE \t= 0x0400;\r\nSTACK_UND_SIZE \t= 0x0400;\r\nSTACK_SRV_SIZE \t= 0x8000;\r\n\r\nMEMORY\r\n{\r\n\trom (rx)\t: org = 0x57800000, len = 0x02000000\t\/* 32 MB *\/\r\n\tram (rwx)\t: org = 0x59800000, len = 0x02000000\t\/* 32 MB *\/\r\n}\r\n\r\nSECTIONS\r\n{   \r\n\t.text :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_start = .);\r\n\t\t.obj\/arch\/arm32\/mach-smdk6410\/start.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-smdk6410\/s3c6410-irom.o (.text)\r\n\t\t*(.text)\r\n\t\t*(.text.*)\r\n\t\t*(.init.text)\r\n    \t*(.exit.text)\r\n\r\n    \t. = ALIGN(8);\r\n    \tPROVIDE (__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE (__ksymtab_end = .);\r\n\r\n    \t. = ALIGN(8);\t\r\n\t\tPROVIDE (__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE (__initcall_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE (__exitcall_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE (__romdisk_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\t*(.rodata);\r\n\t\t*(.rodata.*);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\t*(.glue_7);\r\n\t\t*(.glue_7t);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_end = .);\r\n\t} > rom\r\n\r\n\t.data_shadow ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__data_shadow_start = .);\r\n\t\tPROVIDE (__data_shadow_end = (. + SIZEOF (.data)) );\r\n\t} > rom\r\n\r\n\t.data : AT ( ADDR (.data_shadow) )\r\n\t{\r\n\t\tPROVIDE (__data_start = .);\t\r\n\t\t*(.data)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE (__data_end = .);\t\t\r\n\t} > ram\r\n\r\n\t.ARM.exidx :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__exidx_start = .);\r\n\t\t*(.ARM.exidx*)\r\n\t\tPROVIDE (__exidx_end = .);\r\n\t} > ram\r\n\r\n\t.ARM.extab :\r\n\t{\r\n\t\tPROVIDE (__extab_start = .);\r\n\t\t*(.ARM.extab*)\r\n\t\tPROVIDE (__extab_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE (__bss_start = .);\r\n\t\t*(.bss)\r\n\t\t*(.bss.*)\r\n\t\t*(.sbss)\r\n\t\t*(COMMON)\r\n\t\tPROVIDE (__bss_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_start = .);\r\n\t\t*(.heap)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_start = .);\r\n\t\tPROVIDE (__stack_fiq_start = .);\r\n\t\t. += STACK_FIQ_SIZE;\r\n\t\tPROVIDE (__stack_fiq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_irq_start = .);\r\n\t\t. += STACK_IRQ_SIZE;\r\n\t\tPROVIDE (__stack_irq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_abt_start = .);\r\n\t\t. += STACK_ABT_SIZE;\r\n\t\tPROVIDE (__stack_abt_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_und_start = .);\r\n\t\t. += STACK_UND_SIZE;\r\n\t\tPROVIDE (__stack_und_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_srv_start = .);\r\n\t\t. += STACK_SRV_SIZE;\r\n\t\tPROVIDE (__stack_srv_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_end = .);\r\n\t} > ram\r\n\r\n\t\/*\r\n\t * Stabs debugging sections.\r\n\t *\/\r\n\t.stab 0 : { *(.stab) }\r\n\t.stabstr 0 : { *(.stabstr) }\r\n\t.stab.excl 0 : { *(.stab.excl) }\r\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\r\n\t.stab.index 0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment 0 : { *(.comment) }\r\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\r\n\t.debug_info 0 : { *(.debug_info) }\r\n\t.debug_line 0 : { *(.debug_line) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t.debug_aranges 0 : { *(.debug_aranges) }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8c9ce8d00ad362855182d7e3ee99e9b236db58b2","subject":"Revert \"linker: more .rel for orphan sections\"","message":"Revert \"linker: more .rel for orphan sections\"\n\nThis reverts commit 6ba4488c7c635698f5d398982c4fa3da8fc24758.\n\nSigned-off-by: Anas Nashif <0d9952ec84ac43c159f6b7e7ed99a9080c00dd6e@intel.com>\n","repos":"nashif\/zephyr,galak\/zephyr,galak\/zephyr,punitvara\/zephyr,finikorg\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,galak\/zephyr,explora26\/zephyr,ldts\/zephyr,punitvara\/zephyr,explora26\/zephyr,explora26\/zephyr,nashif\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,ldts\/zephyr,ldts\/zephyr,galak\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,explora26\/zephyr,finikorg\/zephyr,punitvara\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr","old_file":"include\/linker\/rel-sections.ld","new_file":"include\/linker\/rel-sections.ld","new_contents":"\t\/*\n\t * .rel.* are for relocation.\n\t * These are being produced by compiler\/linker.\n\t * Specify these here so they are not considered orphan sections.\n\t *\n\t * Obtained via\n\t * '$(ARCH)-zephyr-elf-ld --verbose'\n\t *\/\n\n#if !defined(CONFIG_RISCV32) && !defined(CONFIG_XTENSA)\n\tSECTION_PROLOGUE(.rel.dyn,,)\n\t{\n\t*(.rel.init)\n\t*(.rel.text .rel.text.* .rel.text_start.* .rel.gnu.linkonce.t.*)\n\t*(.rel.fini)\n\t*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n\t*(.rel.data.rel.ro .rel.data.rel.ro.* .rel.gnu.linkonce.d.rel.ro.*)\n\t*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n\t*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n\t*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n\n#if defined(CONFIG_ARCH_POSIX)\n\t*(.rel.preinit_array)\n\t*(.rel.init_array)\n\t*(.rel.fini_array)\n#endif\n\n\t*(.rel.ctors)\n\t*(.rel.dtors)\n\t*(.rel.got)\n\t*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2)\n\tPROVIDE_HIDDEN (__rel_iplt_start = .);\n\t*(.rel.iplt)\n\tPROVIDE_HIDDEN (__rel_iplt_end = .);\n#endif\n\n\t\/* These are related to sections defined by Zephyr *\/\n\t*(.rel.kernel .rel.kernel.*)\n\t*(.rel.init_PRE_KERNEL*)\n\t*(.rel.init_POST_KERNEL*)\n\t*(.rel.init_APPLICATION*)\n\n#if defined(CONFIG_ARCH_POSIX)\n\t*(.rel.native_PRE_BOOT*)\n\t*(.rel.native_FIRST_SLEEP*)\n\t*(.rel.native_ON_EXIT*)\n#endif\n\n\t*(.rel.devconfig.*)\n\t*(.rel._k_alert.*)\n\t*(.rel._k_mem_pool.*)\n\t*(.rel._k_timer.*)\n\t*(.rel._static_thread_data.*)\n\n#if defined(CONFIG_X86)\n\t*(.rel.ifunc)\n\t*(.rel.mmulist)\n\t*(.rel.tss)\n#endif\n\t}\n#endif \/* !defined(CONFIG_RISCV32) *\/\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32)\n\tSECTION_PROLOGUE(.rela.dyn,,)\n\t{\n\t*(.rela.init)\n\t*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n\t*(.rela.fini)\n\t*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n\t*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n\t*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n\t*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n\t*(.rela.ctors)\n\t*(.rela.dtors)\n\t*(.rela.got)\n\t*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2)\n\tPROVIDE_HIDDEN (__rela_iplt_start = .);\n\t*(.rela.iplt)\n\tPROVIDE_HIDDEN (__rela_iplt_end = .);\n#endif\n\n\t\/* These are related to sections defined by Zephyr *\/\n\t*(.rela.kernel .rel.kernel.*)\n\t*(.rela.init_PRE_KERNEL*)\n\t*(.rela.init_POST_KERNEL*)\n\t*(.rela.init_APPLICATION*)\n\t*(.rela._k_alert.*)\n\t*(.rela._k_mem_pool.*)\n\t*(.rela._k_timer.*)\n\t*(.rela._static_thread_data.*)\n\n#if defined(CONFIG_RISCV32)\n\t*(.rela.devconfig.*)\n\t*(.rela.exception.*)\n\t*(.rela.gnu.linkonce.sw_isr_table)\n\t*(.rela.sdata.*)\n#endif\n\n\t}\n#endif\n\n#if !defined(CONFIG_RISCV32) && !defined(CONFIG_XTENSA)\n\tSECTION_PROLOGUE(.rel.plt,,)\n\t{\n\t*(.rel.plt)\n\n#if defined(CONFIG_X86)\n\tPROVIDE_HIDDEN (__rel_iplt_start = .);\n\t*(.rel.iplt)\n\tPROVIDE_HIDDEN (__rel_iplt_end = .);\n#endif\n\t}\n#endif \/* !defined(CONFIG_RISCV32) *\/\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32)\n\tSECTION_PROLOGUE(.rela.plt,,)\n\t{\n\t*(.rela.plt)\n\t}\n#endif\n","old_contents":"\t\/*\n\t * .rel.* are for relocation.\n\t * These are being produced by compiler\/linker.\n\t * Specify these here so they are not considered orphan sections.\n\t *\n\t * Obtained via\n\t * '$(ARCH)-zephyr-elf-ld --verbose'\n\t *\/\n\n#if !defined(CONFIG_RISCV32) && !defined(CONFIG_XTENSA)\n\tSECTION_PROLOGUE(.rel.dyn,,)\n\t{\n\t*(.rel.init)\n\t*(.rel.text .rel.text.* .rel.text_start.* .rel.gnu.linkonce.t.*)\n\t*(.rel.fini)\n\t*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n\t*(.rel.data.rel.ro .rel.data.rel.ro.* .rel.gnu.linkonce.d.rel.ro.*)\n\t*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n\t*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n\t*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n\n#if defined(CONFIG_ARCH_POSIX)\n\t*(.rel.preinit_array)\n\t*(.rel.init_array)\n\t*(.rel.fini_array)\n#endif\n\n\t*(.rel.ctors)\n\t*(.rel.dtors)\n\t*(.rel.got)\n\t*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2)\n\tPROVIDE_HIDDEN (__rel_iplt_start = .);\n\t*(.rel.iplt)\n\tPROVIDE_HIDDEN (__rel_iplt_end = .);\n#endif\n\n\t\/* These are related to sections defined by Zephyr *\/\n\t*(.rel.kernel .rel.kernel.*)\n\t*(.rel.init_PRE_KERNEL*)\n\t*(.rel.init_POST_KERNEL*)\n\t*(.rel.init_APPLICATION*)\n\n#if defined(CONFIG_ARCH_POSIX)\n\t*(.rel.native_PRE_BOOT*)\n\t*(.rel.native_FIRST_SLEEP*)\n\t*(.rel.native_ON_EXIT*)\n#endif\n\n\t*(.rel.devconfig.*)\n\n\t*(.rel._k_*)\n\n\t*(.rel._bt_settings.*)\n\n\t*(.rel.log_*)\n\n\t*(.rel._net_buf_pool.*)\n\t*(.rel.net_*)\n\n\t*(.rel._static_thread_data.*)\n\n\t*(.rel.usb.*)\n\n#if defined(CONFIG_X86)\n\t*(.rel.ifunc)\n\t*(.rel.mmulist)\n\t*(.rel.tss)\n#endif\n\t}\n#endif \/* !defined(CONFIG_RISCV32) *\/\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32)\n\tSECTION_PROLOGUE(.rela.dyn,,)\n\t{\n\t*(.rela.init)\n\t*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n\t*(.rela.fini)\n\t*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n\t*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n\t*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n\t*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n\t*(.rela.ctors)\n\t*(.rela.dtors)\n\t*(.rela.got)\n\t*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2)\n\tPROVIDE_HIDDEN (__rela_iplt_start = .);\n\t*(.rela.iplt)\n\tPROVIDE_HIDDEN (__rela_iplt_end = .);\n#endif\n\n\t\/* These are related to sections defined by Zephyr *\/\n\t*(.rela.kernel .rel.kernel.*)\n\t*(.rela.init_PRE_KERNEL*)\n\t*(.rela.init_POST_KERNEL*)\n\t*(.rela.init_APPLICATION*)\n\n\t*(.rela.devconfig.*)\n\n\t*(.rela._k_*)\n\n\t*(.rela._bt_settings.*)\n\n\t*(.rela.log_*)\n\n\t*(.rela._net_buf_pool.*)\n\t*(.rela.net_*)\n\n\t*(.rela._static_thread_data.*)\n\n\t*(.rela.usb.*)\n\n#if defined(CONFIG_RISCV32)\n\t*(.rela.exception.*)\n\t*(.rela.gnu.linkonce.sw_isr_table)\n\t*(.rela.sdata.*)\n#endif\n\n\t}\n#endif\n\n#if !defined(CONFIG_RISCV32) && !defined(CONFIG_XTENSA)\n\tSECTION_PROLOGUE(.rel.plt,,)\n\t{\n\t*(.rel.plt)\n\n#if defined(CONFIG_X86)\n\tPROVIDE_HIDDEN (__rel_iplt_start = .);\n\t*(.rel.iplt)\n\tPROVIDE_HIDDEN (__rel_iplt_end = .);\n#endif\n\t}\n#endif \/* !defined(CONFIG_RISCV32) *\/\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32)\n\tSECTION_PROLOGUE(.rela.plt,,)\n\t{\n\t*(.rela.plt)\n\t}\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bbc628d5a0e300c3029750c45da9b665ce121465","subject":"[STM32F4xx-HAL] Fix link error when enable cmbacktrace package.","message":"[STM32F4xx-HAL] Fix link error when enable cmbacktrace package.\n\nChange-Id: I879acd7c67ea782389b8f69acb2846c2879f8fcf\n","repos":"AubrCool\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,AubrCool\/rt-thread,igou\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,geniusgogo\/rt-thread,wolfgangz2013\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,weiyuliang\/rt-thread,FlyLu\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,AubrCool\/rt-thread,FlyLu\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,zhaojuntao\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,wolfgangz2013\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,nongxiaoming\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,armink\/rt-thread,armink\/rt-thread,weety\/rt-thread,igou\/rt-thread","old_file":"bsp\/stm32f4xx-HAL\/stm32_rom.ld","new_file":"bsp\/stm32f4xx-HAL\/stm32_rom.ld","new_contents":"\/*\n * linker script for STM32F10x with GNU ld\n * bernard.xiong 2009-10-14\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k \/* 1024KB flash *\/\n    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  128k \/* 128K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        _etext = .;\n    } > CODE = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > CODE\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >DATA\n\n    .stack : \n    {\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >DATA\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > DATA\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * linker script for STM32F10x with GNU ld\n * bernard.xiong 2009-10-14\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k \/* 1024KB flash *\/\n    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  128k \/* 128K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        _etext = .;\n    } > CODE = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > CODE\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >DATA\n\n    .stack : \n    {\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >DATA\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > DATA\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"79ca190666fdc49101ff92ff6be8d821424a33a1","subject":"lpc2387: Add missing exception tables to linker script","message":"lpc2387: Add missing exception tables to linker script\n\nCopied from kinetis_common\n","repos":"altairpearl\/RIOT,daniel-k\/RIOT,A-Paul\/RIOT,latsku\/RIOT,daniel-k\/RIOT,jremmert-phytec-iot\/RIOT,backenklee\/RIOT,rajma996\/RIOT,MonsterCode8000\/RIOT,TobiasFredersdorf\/RIOT,abkam07\/RIOT,luciotorre\/RIOT,changbiao\/RIOT,wentaoshang\/RIOT,lazytech-org\/RIOT,gautric\/RIOT,rajma996\/RIOT,lebrush\/RIOT,msolters\/RIOT,miri64\/RIOT,gbarnett\/RIOT,phiros\/RIOT,JensErdmann\/RIOT,neumodisch\/RIOT,luciotorre\/RIOT,katezilla\/RIOT,RBartz\/RIOT,MarkXYang\/RIOT,thomaseichinger\/RIOT,ant9000\/RIOT,asanka-code\/RIOT,MarkXYang\/RIOT,marcosalm\/RIOT,arvindpdmn\/RIOT,cladmi\/RIOT,wentaoshang\/RIOT,bartfaizoltan\/RIOT,neumodisch\/RIOT,latsku\/RIOT,marcosalm\/RIOT,Lexandro92\/RIOT-CoAP,altairpearl\/RIOT,mtausig\/RIOT,basilfx\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,latsku\/RIOT,brettswann\/RIOT,latsku\/RIOT,changbiao\/RIOT,tdautc19841202\/RIOT,Ell-i\/RIOT,MonsterCode8000\/RIOT,Darredevil\/RIOT,rousselk\/RIOT,Osblouf\/RIOT,gbarnett\/RIOT,Josar\/RIOT,neumodisch\/RIOT,kaleb-himes\/RIOT,rfuentess\/RIOT,DipSwitch\/RIOT,marcosalm\/RIOT,ntrtrung\/RIOT,zhuoshuguo\/RIOT,sumanpanchal\/RIOT,jremmert-phytec-iot\/RIOT,attdona\/RIOT,patkan\/RIOT,openkosmosorg\/RIOT,koenning\/RIOT,chris-wood\/RIOT,Yonezawa-T2\/RIOT,RBartz\/RIOT,aeneby\/RIOT,LudwigOrtmann\/RIOT,sumanpanchal\/RIOT,backenklee\/RIOT,msolters\/RIOT,neiljay\/RIOT,MohmadAyman\/RIOT,ximus\/RIOT,jferreir\/RIOT,d00616\/RIOT,jferreir\/RIOT,syin2\/RIOT,attdona\/RIOT,alignan\/RIOT,d00616\/RIOT,ant9000\/RIOT,Josar\/RIOT,mziegert\/RIOT,jbeyerstedt\/RIOT-OTA-update,OTAkeys\/RIOT,ThanhVic\/RIOT,smlng\/RIOT,MohmadAyman\/RIOT,RBartz\/RIOT,ntrtrung\/RIOT,ximus\/RIOT,altairpearl\/RIOT,jbeyerstedt\/RIOT-OTA-update,luciotorre\/RIOT,syin2\/RIOT,Lexandro92\/RIOT-CoAP,LudwigOrtmann\/RIOT,khhhh\/RIOT,yogo1212\/RIOT,RubikonAlpha\/RIOT,abp719\/RIOT,wentaoshang\/RIOT,cladmi\/RIOT,phiros\/RIOT,malosek\/RIOT,chris-wood\/RIOT,smlng\/RIOT,plushvoxel\/RIOT,syin2\/RIOT,avmelnikoff\/RIOT,tdautc19841202\/RIOT,rakendrathapa\/RIOT,DipSwitch\/RIOT,msolters\/RIOT,beurdouche\/RIOT,automote\/RIOT,rfswarm\/RIOT,plushvoxel\/RIOT,BytesGalore\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,MohmadAyman\/RIOT,changbiao\/RIOT,herrfz\/RIOT,haoyangyu\/RIOT,rousselk\/RIOT,DipSwitch\/RIOT,alignan\/RIOT,OTAkeys\/RIOT,jremmert-phytec-iot\/RIOT,kushalsingh007\/RIOT,asanka-code\/RIOT,x3ro\/RIOT,Osblouf\/RIOT,kb2ma\/RIOT,x3ro\/RIOT,daniel-k\/RIOT,phiros\/RIOT,EmuxEvans\/RIOT,plushvoxel\/RIOT,PSHIVANI\/Riot-Code,avmelnikoff\/RIOT,abp719\/RIOT,alex1818\/RIOT,robixnai\/RIOT,ThanhVic\/RIOT,dkm\/RIOT,jasonatran\/RIOT,hamilton-mote\/RIOT-OS,attdona\/RIOT,mfrey\/RIOT,koenning\/RIOT,Ell-i\/RIOT,JensErdmann\/RIOT,kaspar030\/RIOT,patkan\/RIOT,khhhh\/RIOT,OTAkeys\/RIOT,brettswann\/RIOT,sumanpanchal\/RIOT,mtausig\/RIOT,herrfz\/RIOT,gbarnett\/RIOT,syin2\/RIOT,sumanpanchal\/RIOT,avmelnikoff\/RIOT,PSHIVANI\/Riot-Code,shady33\/RIOT,Hyungsin\/RIOT-OS,EmuxEvans\/RIOT,openkosmosorg\/RIOT,luciotorre\/RIOT,A-Paul\/RIOT,basilfx\/RIOT,katezilla\/RIOT,adrianghc\/RIOT,brettswann\/RIOT,basilfx\/RIOT,altairpearl\/RIOT,backenklee\/RIOT,Hyungsin\/RIOT-OS,binarylemon\/RIOT,dkm\/RIOT,RubikonAlpha\/RIOT,alex1818\/RIOT,kYc0o\/RIOT,LudwigKnuepfer\/RIOT,immesys\/RiSyn,roberthartung\/RIOT,TobiasFredersdorf\/RIOT,MohmadAyman\/RIOT,herrfz\/RIOT,centurysys\/RIOT,avmelnikoff\/RIOT,jasonatran\/RIOT,kb2ma\/RIOT,gautric\/RIOT,kb2ma\/RIOT,PSHIVANI\/Riot-Code,dhruvvyas90\/RIOT,LudwigOrtmann\/RIOT,l3nko\/RIOT,tdautc19841202\/RIOT,mtausig\/RIOT,jremmert-phytec-iot\/RIOT,automote\/RIOT,RIOT-OS\/RIOT,neiljay\/RIOT,thomaseichinger\/RIOT,ntrtrung\/RIOT,toonst\/RIOT,FrancescoErmini\/RIOT,toonst\/RIOT,haoyangyu\/RIOT,jfischer-phytec-iot\/RIOT,BytesGalore\/RIOT,aeneby\/RIOT,gebart\/RIOT,dailab\/RIOT,plushvoxel\/RIOT,arvindpdmn\/RIOT,koenning\/RIOT,kbumsik\/RIOT,l3nko\/RIOT,binarylemon\/RIOT,LudwigKnuepfer\/RIOT,abkam07\/RIOT,Hyungsin\/RIOT-OS,mziegert\/RIOT,msolters\/RIOT,l3nko\/RIOT,ThanhVic\/RIOT,OTAkeys\/RIOT,ximus\/RIOT,OTAkeys\/RIOT,patkan\/RIOT,abkam07\/RIOT,dailab\/RIOT,katezilla\/RIOT,RBartz\/RIOT,smlng\/RIOT,robixnai\/RIOT,attdona\/RIOT,katezilla\/RIOT,jferreir\/RIOT,haoyangyu\/RIOT,watr-li\/RIOT,EmuxEvans\/RIOT,PSHIVANI\/Riot-Code,ant9000\/RIOT,patkan\/RIOT,abkam07\/RIOT,malosek\/RIOT,jferreir\/RIOT,kerneltask\/RIOT,lebrush\/RIOT,neumodisch\/RIOT,gebart\/RIOT,kaspar030\/RIOT,openkosmosorg\/RIOT,Lexandro92\/RIOT-CoAP,immesys\/RiSyn,dkm\/RIOT,rajma996\/RIOT,brettswann\/RIOT,avmelnikoff\/RIOT,Darredevil\/RIOT,roberthartung\/RIOT,Osblouf\/RIOT,Josar\/RIOT,tdautc19841202\/RIOT,alex1818\/RIOT,haoyangyu\/RIOT,chris-wood\/RIOT,marcosalm\/RIOT,stevenj\/RIOT,miri64\/RIOT,JensErdmann\/RIOT,latsku\/RIOT,RBartz\/RIOT,bartfaizoltan\/RIOT,ant9000\/RIOT,dhruvvyas90\/RIOT,jfischer-phytec-iot\/RIOT,josephnoir\/RIOT,OlegHahm\/RIOT,thiagohd\/RIOT,openkosmosorg\/RIOT,basilfx\/RIOT,l3nko\/RIOT,thiagohd\/RIOT,jferreir\/RIOT,neiljay\/RIOT,MarkXYang\/RIOT,changbiao\/RIOT,thomaseichinger\/RIOT,herrfz\/RIOT,marcosalm\/RIOT,kYc0o\/RIOT,lazytech-org\/RIOT,mziegert\/RIOT,FrancescoErmini\/RIOT,rousselk\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,ks156\/RIOT,biboc\/RIOT,A-Paul\/RIOT,tdautc19841202\/RIOT,jfischer-phytec-iot\/RIOT,l3nko\/RIOT,mfrey\/RIOT,centurysys\/RIOT,lazytech-org\/RIOT,kaspar030\/RIOT,rakendrathapa\/RIOT,changbiao\/RIOT,ks156\/RIOT,rousselk\/RIOT,gautric\/RIOT,mziegert\/RIOT,msolters\/RIOT,dhruvvyas90\/RIOT,beurdouche\/RIOT,sumanpanchal\/RIOT,kbumsik\/RIOT,kaleb-himes\/RIOT,thiagohd\/RIOT,shady33\/RIOT,toonst\/RIOT,Hyungsin\/RIOT-OS,daniel-k\/RIOT,koenning\/RIOT,kbumsik\/RIOT,jfischer-phytec-iot\/RIOT,arvindpdmn\/RIOT,EmuxEvans\/RIOT,haoyangyu\/RIOT,tfar\/RIOT,automote\/RIOT,asanka-code\/RIOT,dhruvvyas90\/RIOT,Lexandro92\/RIOT-CoAP,malosek\/RIOT,malosek\/RIOT,jferreir\/RIOT,changbiao\/RIOT,MonsterCode8000\/RIOT,FrancescoErmini\/RIOT,zhuoshuguo\/RIOT,chris-wood\/RIOT,neiljay\/RIOT,kushalsingh007\/RIOT,RubikonAlpha\/RIOT,automote\/RIOT,Osblouf\/RIOT,miri64\/RIOT,kerneltask\/RIOT,stevenj\/RIOT,Yonezawa-T2\/RIOT,toonst\/RIOT,stevenj\/RIOT,rfuentess\/RIOT,d00616\/RIOT,yogo1212\/RIOT,OlegHahm\/RIOT,binarylemon\/RIOT,kb2ma\/RIOT,yogo1212\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,ThanhVic\/RIOT,kaspar030\/RIOT,stevenj\/RIOT,dailab\/RIOT,dhruvvyas90\/RIOT,dkm\/RIOT,ntrtrung\/RIOT,yogo1212\/RIOT,abp719\/RIOT,attdona\/RIOT,lebrush\/RIOT,adrianghc\/RIOT,smlng\/RIOT,beurdouche\/RIOT,rfswarm\/RIOT,alignan\/RIOT,BytesGalore\/RIOT,gautric\/RIOT,Ell-i\/RIOT,robixnai\/RIOT,PSHIVANI\/Riot-Code,robixnai\/RIOT,rajma996\/RIOT,kaleb-himes\/RIOT,DipSwitch\/RIOT,alignan\/RIOT,rajma996\/RIOT,centurysys\/RIOT,aeneby\/RIOT,herrfz\/RIOT,roberthartung\/RIOT,Lexandro92\/RIOT-CoAP,shady33\/RIOT,beurdouche\/RIOT,rfswarm\/RIOT,thiagohd\/RIOT,mfrey\/RIOT,FrancescoErmini\/RIOT,mtausig\/RIOT,altairpearl\/RIOT,brettswann\/RIOT,josephnoir\/RIOT,immesys\/RiSyn,MonsterCode8000\/RIOT,malosek\/RIOT,JensErdmann\/RIOT,tfar\/RIOT,thiagohd\/RIOT,RubikonAlpha\/RIOT,LudwigOrtmann\/RIOT,zhuoshuguo\/RIOT,adrianghc\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,bartfaizoltan\/RIOT,hamilton-mote\/RIOT-OS,marcosalm\/RIOT,shady33\/RIOT,tfar\/RIOT,authmillenon\/RIOT,toonst\/RIOT,dailab\/RIOT,authmillenon\/RIOT,asanka-code\/RIOT,lebrush\/RIOT,hamilton-mote\/RIOT-OS,gebart\/RIOT,neumodisch\/RIOT,immesys\/RiSyn,Hyungsin\/RIOT-OS,Darredevil\/RIOT,alex1818\/RIOT,TobiasFredersdorf\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,EmuxEvans\/RIOT,FrancescoErmini\/RIOT,kerneltask\/RIOT,wentaoshang\/RIOT,Yonezawa-T2\/RIOT,phiros\/RIOT,mfrey\/RIOT,jbeyerstedt\/RIOT-OTA-update,gbarnett\/RIOT,binarylemon\/RIOT,hamilton-mote\/RIOT-OS,biboc\/RIOT,LudwigOrtmann\/RIOT,ks156\/RIOT,DipSwitch\/RIOT,shady33\/RIOT,lazytech-org\/RIOT,DipSwitch\/RIOT,haoyangyu\/RIOT,kaspar030\/RIOT,jbeyerstedt\/RIOT-OTA-update,lebrush\/RIOT,miri64\/RIOT,katezilla\/RIOT,robixnai\/RIOT,ntrtrung\/RIOT,zhuoshuguo\/RIOT,thomaseichinger\/RIOT,latsku\/RIOT,kbumsik\/RIOT,jremmert-phytec-iot\/RIOT,josephnoir\/RIOT,yogo1212\/RIOT,mfrey\/RIOT,PSHIVANI\/Riot-Code,attdona\/RIOT,JensErdmann\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,ximus\/RIOT,roberthartung\/RIOT,phiros\/RIOT,binarylemon\/RIOT,neiljay\/RIOT,MarkXYang\/RIOT,abkam07\/RIOT,khhhh\/RIOT,kushalsingh007\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,RIOT-OS\/RIOT,khhhh\/RIOT,backenklee\/RIOT,adjih\/RIOT,wentaoshang\/RIOT,stevenj\/RIOT,miri64\/RIOT,rfswarm\/RIOT,MarkXYang\/RIOT,Josar\/RIOT,patkan\/RIOT,kYc0o\/RIOT,immesys\/RiSyn,adjih\/RIOT,daniel-k\/RIOT,Darredevil\/RIOT,josephnoir\/RIOT,arvindpdmn\/RIOT,arvindpdmn\/RIOT,alex1818\/RIOT,shady33\/RIOT,asanka-code\/RIOT,zhuoshuguo\/RIOT,watr-li\/RIOT,Darredevil\/RIOT,hamilton-mote\/RIOT-OS,phiros\/RIOT,watr-li\/RIOT,ntrtrung\/RIOT,EmuxEvans\/RIOT,rakendrathapa\/RIOT,kaleb-himes\/RIOT,RBartz\/RIOT,chris-wood\/RIOT,adrianghc\/RIOT,jfischer-phytec-iot\/RIOT,Yonezawa-T2\/RIOT,adrianghc\/RIOT,d00616\/RIOT,alex1818\/RIOT,wentaoshang\/RIOT,automote\/RIOT,centurysys\/RIOT,gebart\/RIOT,rfswarm\/RIOT,herrfz\/RIOT,jremmert-phytec-iot\/RIOT,plushvoxel\/RIOT,kYc0o\/RIOT,centurysys\/RIOT,gbarnett\/RIOT,Lexandro92\/RIOT-CoAP,ks156\/RIOT,aeneby\/RIOT,OlegHahm\/RIOT,roberthartung\/RIOT,aeneby\/RIOT,bartfaizoltan\/RIOT,x3ro\/RIOT,Yonezawa-T2\/RIOT,rakendrathapa\/RIOT,mtausig\/RIOT,kushalsingh007\/RIOT,kushalsingh007\/RIOT,syin2\/RIOT,rousselk\/RIOT,watr-li\/RIOT,rousselk\/RIOT,ThanhVic\/RIOT,A-Paul\/RIOT,thiagohd\/RIOT,lazytech-org\/RIOT,abp719\/RIOT,A-Paul\/RIOT,BytesGalore\/RIOT,daniel-k\/RIOT,LudwigKnuepfer\/RIOT,kerneltask\/RIOT,basilfx\/RIOT,JensErdmann\/RIOT,kb2ma\/RIOT,lebrush\/RIOT,gautric\/RIOT,RubikonAlpha\/RIOT,RIOT-OS\/RIOT,dailab\/RIOT,asanka-code\/RIOT,watr-li\/RIOT,Osblouf\/RIOT,openkosmosorg\/RIOT,rfswarm\/RIOT,d00616\/RIOT,LudwigKnuepfer\/RIOT,kbumsik\/RIOT,biboc\/RIOT,RIOT-OS\/RIOT,alignan\/RIOT,sumanpanchal\/RIOT,bartfaizoltan\/RIOT,immesys\/RiSyn,TobiasFredersdorf\/RIOT,arvindpdmn\/RIOT,adjih\/RIOT,MarkXYang\/RIOT,dhruvvyas90\/RIOT,biboc\/RIOT,altairpearl\/RIOT,kaleb-himes\/RIOT,rfuentess\/RIOT,cladmi\/RIOT,jasonatran\/RIOT,rfuentess\/RIOT,brettswann\/RIOT,ximus\/RIOT,Osblouf\/RIOT,gbarnett\/RIOT,dkm\/RIOT,adjih\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,watr-li\/RIOT,abp719\/RIOT,TobiasFredersdorf\/RIOT,LudwigKnuepfer\/RIOT,MonsterCode8000\/RIOT,msolters\/RIOT,MohmadAyman\/RIOT,adjih\/RIOT,centurysys\/RIOT,mziegert\/RIOT,abkam07\/RIOT,automote\/RIOT,authmillenon\/RIOT,patkan\/RIOT,ximus\/RIOT,backenklee\/RIOT,abp719\/RIOT,binarylemon\/RIOT,BytesGalore\/RIOT,l3nko\/RIOT,ThanhVic\/RIOT,Ell-i\/RIOT,MohmadAyman\/RIOT,josephnoir\/RIOT,luciotorre\/RIOT,thomaseichinger\/RIOT,koenning\/RIOT,jasonatran\/RIOT,LudwigOrtmann\/RIOT,Darredevil\/RIOT,mziegert\/RIOT,tdautc19841202\/RIOT,kushalsingh007\/RIOT,d00616\/RIOT,RubikonAlpha\/RIOT,khhhh\/RIOT,Yonezawa-T2\/RIOT,MonsterCode8000\/RIOT,RIOT-OS\/RIOT,luciotorre\/RIOT,rajma996\/RIOT,rakendrathapa\/RIOT,koenning\/RIOT,Josar\/RIOT,cladmi\/RIOT,cladmi\/RIOT,rakendrathapa\/RIOT,smlng\/RIOT,jbeyerstedt\/RIOT-OTA-update,FrancescoErmini\/RIOT,biboc\/RIOT,ant9000\/RIOT,kerneltask\/RIOT,Ell-i\/RIOT,robixnai\/RIOT,malosek\/RIOT,x3ro\/RIOT,tfar\/RIOT,stevenj\/RIOT,ks156\/RIOT,bartfaizoltan\/RIOT,gebart\/RIOT,beurdouche\/RIOT,zhuoshuguo\/RIOT,openkosmosorg\/RIOT,authmillenon\/RIOT,chris-wood\/RIOT,tfar\/RIOT,x3ro\/RIOT,neumodisch\/RIOT,khhhh\/RIOT","old_file":"cpu\/lpc2387\/ldscripts\/lpc2387.ld","new_file":"cpu\/lpc2387\/ldscripts\/lpc2387.ld","new_contents":"\/*\n * Copyright 2013, Freie Universitaet Berlin (FUB). All rights reserved.\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/* specify the LPC2387 memory areas (see LPC2387 datasheet page 15)  *\/\nMEMORY\n{\n    flash               : ORIGIN = 0,          LENGTH = 504K    \/* FLASH ROM 512kByte without ISP bootloader*\/\n    infomem             : ORIGIN = 0x0007D000, LENGTH = 4K      \/* Last sector in FLASH ROM for config data *\/\n    ram_battery         : ORIGIN = 0xE0084000, LENGTH = 2K      \/* Battery RAM                              *\/\n    ram                 : ORIGIN = 0x40000000, LENGTH = 64K     \/* LOCAL ON-CHIP STATIC RAM                 *\/\n    ram_usb             : ORIGIN = 0x7FD00000, LENGTH = 16K     \/* USB RAM  !!! first 1024 bytes are occupied from GPDMA for MCI *\/\n    ram_ethernet        : ORIGIN = 0x7FE00000, LENGTH = 16K     \/* ethernet RAM                             *\/\n}\n\n__stack_und_size = 4;           \/* stack for \"undefined instruction\" interrupts             *\/\n__stack_abt_size = 4;           \/* stack for \"abort\" interrupts                             *\/\n__stack_fiq_size = 64;          \/* stack for \"FIQ\" interrupts                               *\/\n__stack_irq_size = 400;         \/* stack for \"IRQ\" normal interrupts                        *\/\n__stack_svc_size = 400;         \/* stack for \"SVC\" supervisor mode                          *\/\n__stack_usr_size = 4096;        \/* stack for user operation (kernel init)                   *\/\n__stack_size = __stack_und_size + __stack_abt_size + __stack_fiq_size + __stack_irq_size + __stack_svc_size + __stack_usr_size;\n\n\/* now define the output sections  *\/\nSECTIONS\n{\n    .text :                             \/* collect all sections that should go into FLASH after startup  *\/\n    {\n        KEEP(*(.vectors))               \/* Exception Vectors and branch table >= 64 bytes *\/\n        . = ALIGN(64);\n        KEEP(*(.init))\n        KEEP(*(.init0))                 \/* Start here after reset.  *\/\n        KEEP(*(.init1))\n        KEEP(*(.init2))                 \/* Copy data loop  *\/\n        KEEP(*(.init3))\n        KEEP(*(.init4))                 \/* Clear bss  *\/\n        KEEP(*(.init5))\n        KEEP(*(.init6))                 \/* C++ constructors.  *\/\n        KEEP(*(.init7))\n        KEEP(*(.init8))\n        KEEP(*(.init9))                 \/* Call main().  *\/\n        *(.text)                        \/* all .text sections (code)  *\/\n        *(.text.*)\n        *(.gnu.linkonce.t.*)\n\n        . = ALIGN(4);\n        __commands_start = .;\n        KEEP(*(.commands))              \/* command table *\/\n        __commands_end = .;\n        . = ALIGN(4);\n        __cfgspec_start = .;\n        KEEP(*(.cfgspec))               \/* configuration spec table *\/\n        __cfgspec_end = .;\n        . = ALIGN(4);\n\n        __ctors_start = .;\n            PROVIDE(_os_ctor_start = .);\n            KEEP(*(.ctors));\n            KEEP(*(.init_array))\n            PROVIDE(_os_ctor_end = .);\n        __ctors_end = .;\n            KEEP(*(.dtors));\n            LONG (0);\n\n\n        *(.rodata .rodata.*)            \/* all .rodata sections (constants, strings, etc.)  *\/\n        *(.gnu.linkonce.r.*)\n        *(.glue_7)                      \/* all .glue_7 sections, see https:\/\/gcc.gnu.org\/ml\/gcc-help\/2009-03\/msg00306.html *\/\n        *(.glue_7t)                     \/* all .glue_7t sections *\/\n\n        KEEP(*(.fini9))\n        KEEP(*(.fini8))\n        KEEP(*(.fini7))\n        KEEP(*(.fini6))                     \/* C++ destructors.  *\/\n        KEEP(*(.fini5))\n        KEEP(*(.fini4))\n        KEEP(*(.fini3))\n        KEEP(*(.fini2))\n        KEEP(*(.fini1))\n        KEEP(*(.fini0))                     \/* Infinite loop after program termination.  *\/\n        KEEP(*(.fini))\n\n        *(.gcc_except_table)\n\n    } >flash                            \/* put all the above into FLASH *\/\n    . = ALIGN(4);\n\n    \/* The .extab, .exidx sections are used for C++ exception handling *\/\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > flash\n\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > flash\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    .eh_frame_hdr :\n    {\n        *(.eh_frame_hdr)\n    } > flash\n\n    .eh_frame : ONLY_IF_RO\n    {\n        KEEP (*(.eh_frame))\n    } > flash\n\n    .gcc_except_table : ONLY_IF_RO\n    {\n        *(.gcc_except_table .gcc_except_table.*)\n    } > flash\n\n\/*\n    .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } > sram_u AT > flash\n    .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } > sram_u AT > flash\n*\/\n\n    _etext = . ;                        \/* define a global symbol _etext just after the last code byte *\/\n\n    .config :\n    {\n        *(.configmem)\n        . = ALIGN(256);\n    } >infomem\n    . = ALIGN(4);\n\n    \/**************************************************************************\n     * RAM\n     **************************************************************************\/\n\n\n    .ctors (NOLOAD) :\n    {\n        . = ALIGN(4096);\n        start_ctors = .;\n        *(.init_array);\n        *(.ctors);\n        end_ctors = .;\n    } >ram\n\n    .dtors (NOLOAD) :\n    {\n        . = ALIGN(4096);\n        start_dtors = .;\n        *(.fini_array);\n        *(.dtors);\n        end_dtors = .;\n    } >ram\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        PROVIDE(__fiq_handler = .);\n        *(.fiq)\n        *(.noinit)\n    }  > ram\n    . = ALIGN(4);\n    __noinit_end = .;\n\n    \/*\n     * collect all zero initialized sections that go into RAM\n     *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);                   \/* ensure data is aligned so relocation can use 4-byte operations *\/\n        __bss_start = .;                \/* define a global symbol marking the start of the .bss section *\/\n        *(.bss*)                        \/* all .bss sections  *\/\n        *(COMMON)\n    } > ram                             \/* put all the above in RAM (it will be cleared in the startup code *\/\n    . = ALIGN(4);                       \/* ensure data is aligned so relocation can use 4-byte operations *\/\n    __bss_end = . ;                     \/* define a global symbol marking the end of the .bss section *\/\n\n    \/*\n     * collect all initialized .data sections that go into RAM\n     * initial values get placed at the end of .text in flash\n     *\/\n    .data : AT (_etext)\n    {\n        . = ALIGN(4);                   \/* ensure data is aligned so relocation can use 4-byte operations *\/\n        _data = .;                      \/* create a global symbol marking the start of the .data section  *\/\n        *(.data .data.*)                \/* all .data sections  *\/\n        *(.gnu.linkonce.d*)\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n            PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n            KEEP(*(.init_array))\n            PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n            KEEP(*(.fini_array))\n            PROVIDE_HIDDEN (__fini_array_end = .);\n    } >ram                              \/* put all the above into RAM (but load the LMA copy into FLASH) *\/\n    . = ALIGN(4);                       \/* ensure data is aligned so relocation can use 4-byte operations *\/\n    _edata = .;                         \/* define a global symbol marking the end of the .data section  *\/\n\n\n    \/*\n     * Exception frames (newer linker versions generate these but they use of\n     * most of the RAM.\n     *\/\n    \/DISCARD\/ :                         \/* discard exception frames *\/\n    {\n        *(.eh_*)\n    }\n\n    \/* to enable exception frames *\/\n    \/*\n    .eh_frame :\n    {\n         KEEP (*(.eh_frame))\n    } > ram\n    . = ALIGN(4);\n    *\/\n\n    _end = .;                           \/* define a global symbol marking the end of application RAM *\/\n\n    __heap1_size = ORIGIN(ram) + LENGTH(ram) - . - __stack_size;\n    .heap1 (NOLOAD) :\n    {\n        PROVIDE(__heap1_start = .);\n        . = . + __heap1_size;\n        PROVIDE(__heap1_max = .);\n    } > ram\n\n    \/*\n     * Stacks\n     *\/\n    .stack (NOLOAD) :\n    {\n        PROVIDE(__stack_start = .);\n\n        . = . + __stack_usr_size;\n        __stack_usr_start = .;\n        . = . + __stack_und_size;\n        __stack_und_start = .;\n        . = . + __stack_fiq_size;\n        __stack_fiq_start = .;\n        . = . + __stack_irq_size;\n        __stack_irq_start = .;\n        . = . + __stack_abt_size;\n        __stack_abt_start = .;\n        . = . + __stack_svc_size;\n        __stack_svc_start = .;\n\n        PROVIDE(__stack_end = .);\n    } > ram\n\n    __heap2_size = LENGTH(ram_ethernet);\n    .heap2 (NOLOAD) :\n    {\n        PROVIDE(__heap2_start = . );\n        . = . + __heap2_size;\n        PROVIDE(__heap2_max = .);       \/* _heap shall always be < _heap_max *\/\n    } > ram_ethernet\n\n    . = ORIGIN(ram_usb);\n    .usbdata (NOLOAD) :                 \/* USB RAM section, may be used otherwise if USB is disabled *\/\n    {\n        *(.usbdata)\n    } > ram_usb\n\n    .heap3 ALIGN(0x1000) (NOLOAD) :\n    {\n        __heap3_size = ORIGIN(ram_usb) + LENGTH(ram_usb) - ABSOLUTE(.);\n        PROVIDE(__heap3_start = . );\n        . += __heap3_size;\n        PROVIDE(__heap3_max = .);\n    } > ram_usb\n    __heap_size = SIZEOF(.heap3);\n\n\n    .batteryram (NOLOAD) :              \/* battery ram stays on during powerdown but needs to be handled specially *\/\n    {\n        *(.batteryram)\n    } > ram_battery\n}\n","old_contents":"\/*\n * Copyright 2013, Freie Universitaet Berlin (FUB). All rights reserved.\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/* specify the LPC2387 memory areas (see LPC2387 datasheet page 15)  *\/\nMEMORY\n{\n    flash               : ORIGIN = 0,          LENGTH = 504K    \/* FLASH ROM 512kByte without ISP bootloader*\/\n    infomem             : ORIGIN = 0x0007D000, LENGTH = 4K      \/* Last sector in FLASH ROM for config data *\/\n    ram_battery         : ORIGIN = 0xE0084000, LENGTH = 2K      \/* Battery RAM                              *\/\n    ram                 : ORIGIN = 0x40000000, LENGTH = 64K     \/* LOCAL ON-CHIP STATIC RAM                 *\/\n    ram_usb             : ORIGIN = 0x7FD00000, LENGTH = 16K     \/* USB RAM  !!! first 1024 bytes are occupied from GPDMA for MCI *\/\n    ram_ethernet        : ORIGIN = 0x7FE00000, LENGTH = 16K     \/* ethernet RAM                             *\/\n}\n\n__stack_und_size = 4;           \/* stack for \"undefined instruction\" interrupts             *\/\n__stack_abt_size = 4;           \/* stack for \"abort\" interrupts                             *\/\n__stack_fiq_size = 64;          \/* stack for \"FIQ\" interrupts                               *\/\n__stack_irq_size = 400;         \/* stack for \"IRQ\" normal interrupts                        *\/\n__stack_svc_size = 400;         \/* stack for \"SVC\" supervisor mode                          *\/\n__stack_usr_size = 4096;        \/* stack for user operation (kernel init)                   *\/\n__stack_size = __stack_und_size + __stack_abt_size + __stack_fiq_size + __stack_irq_size + __stack_svc_size + __stack_usr_size;\n\n\/* now define the output sections  *\/\nSECTIONS\n{\n    .text :                             \/* collect all sections that should go into FLASH after startup  *\/\n    {\n        KEEP(*(.vectors))               \/* Exception Vectors and branch table >= 64 bytes *\/\n        . = ALIGN(64);\n        KEEP(*(.init))\n        KEEP(*(.init0))                 \/* Start here after reset.  *\/\n        KEEP(*(.init1))\n        KEEP(*(.init2))                 \/* Copy data loop  *\/\n        KEEP(*(.init3))\n        KEEP(*(.init4))                 \/* Clear bss  *\/\n        KEEP(*(.init5))\n        KEEP(*(.init6))                 \/* C++ constructors.  *\/\n        KEEP(*(.init7))\n        KEEP(*(.init8))\n        KEEP(*(.init9))                 \/* Call main().  *\/\n        *(.text)                        \/* all .text sections (code)  *\/\n        *(.text.*)\n        *(.gnu.linkonce.t.*)\n\n        . = ALIGN(4);\n        __commands_start = .;\n        KEEP(*(.commands))              \/* command table *\/\n        __commands_end = .;\n        . = ALIGN(4);\n        __cfgspec_start = .;\n        KEEP(*(.cfgspec))               \/* configuration spec table *\/\n        __cfgspec_end = .;\n        . = ALIGN(4);\n\n        __ctors_start = .;\n            PROVIDE(_os_ctor_start = .);\n            KEEP(*(.ctors));\n            KEEP(*(.init_array))\n            PROVIDE(_os_ctor_end = .);\n        __ctors_end = .;\n            KEEP(*(.dtors));\n            LONG (0);\n\n\n        *(.rodata .rodata.*)            \/* all .rodata sections (constants, strings, etc.)  *\/\n        *(.gnu.linkonce.r.*)\n        *(.glue_7)                      \/* all .glue_7 sections, see https:\/\/gcc.gnu.org\/ml\/gcc-help\/2009-03\/msg00306.html *\/\n        *(.glue_7t)                     \/* all .glue_7t sections *\/\n\n        KEEP(*(.fini9))\n        KEEP(*(.fini8))\n        KEEP(*(.fini7))\n        KEEP(*(.fini6))                     \/* C++ destructors.  *\/\n        KEEP(*(.fini5))\n        KEEP(*(.fini4))\n        KEEP(*(.fini3))\n        KEEP(*(.fini2))\n        KEEP(*(.fini1))\n        KEEP(*(.fini0))                     \/* Infinite loop after program termination.  *\/\n        KEEP(*(.fini))\n\n        *(.gcc_except_table)\n\n    } >flash                            \/* put all the above into FLASH *\/\n    . = ALIGN(4);\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } >flash\n    __exidx_end = .;\n\n    _etext = . ;                        \/* define a global symbol _etext just after the last code byte *\/\n\n    .config :\n    {\n        *(.configmem)\n        . = ALIGN(256);\n    } >infomem\n    . = ALIGN(4);\n\n    \/**************************************************************************\n     * RAM\n     **************************************************************************\/\n\n\n    .ctors (NOLOAD) :\n    {\n        . = ALIGN(4096);\n        start_ctors = .;\n        *(.init_array);\n        *(.ctors);\n        end_ctors = .;\n    } >ram\n\n    .dtors (NOLOAD) :\n    {\n        . = ALIGN(4096);\n        start_dtors = .;\n        *(.fini_array);\n        *(.dtors);\n        end_dtors = .;\n    } >ram\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        PROVIDE(__fiq_handler = .);\n        *(.fiq)\n        *(.noinit)\n    }  > ram\n    . = ALIGN(4);\n    __noinit_end = .;\n\n    \/*\n     * collect all zero initialized sections that go into RAM\n     *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);                   \/* ensure data is aligned so relocation can use 4-byte operations *\/\n        __bss_start = .;                \/* define a global symbol marking the start of the .bss section *\/\n        *(.bss*)                        \/* all .bss sections  *\/\n        *(COMMON)\n    } > ram                             \/* put all the above in RAM (it will be cleared in the startup code *\/\n    . = ALIGN(4);                       \/* ensure data is aligned so relocation can use 4-byte operations *\/\n    __bss_end = . ;                     \/* define a global symbol marking the end of the .bss section *\/\n\n    \/*\n     * collect all initialized .data sections that go into RAM\n     * initial values get placed at the end of .text in flash\n     *\/\n    .data : AT (_etext)\n    {\n        . = ALIGN(4);                   \/* ensure data is aligned so relocation can use 4-byte operations *\/\n        _data = .;                      \/* create a global symbol marking the start of the .data section  *\/\n        *(.data .data.*)                \/* all .data sections  *\/\n        *(.gnu.linkonce.d*)\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n            PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n            KEEP(*(.init_array))\n            PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n            KEEP(*(.fini_array))\n            PROVIDE_HIDDEN (__fini_array_end = .);\n    } >ram                              \/* put all the above into RAM (but load the LMA copy into FLASH) *\/\n    . = ALIGN(4);                       \/* ensure data is aligned so relocation can use 4-byte operations *\/\n    _edata = .;                         \/* define a global symbol marking the end of the .data section  *\/\n\n\n    \/*\n     * Exception frames (newer linker versions generate these but they use of\n     * most of the RAM.\n     *\/\n    \/DISCARD\/ :                         \/* discard exception frames *\/\n    {\n        *(.eh_*)\n    }\n\n    \/* to enable exception frames *\/\n    \/*\n    .eh_frame :\n    {\n         KEEP (*(.eh_frame))\n    } > ram\n    . = ALIGN(4);\n    *\/\n\n    _end = .;                           \/* define a global symbol marking the end of application RAM *\/\n\n    __heap1_size = ORIGIN(ram) + LENGTH(ram) - . - __stack_size;\n    .heap1 (NOLOAD) :\n    {\n        PROVIDE(__heap1_start = .);\n        . = . + __heap1_size;\n        PROVIDE(__heap1_max = .);\n    } > ram\n\n    \/*\n     * Stacks\n     *\/\n    .stack (NOLOAD) :\n    {\n        PROVIDE(__stack_start = .);\n\n        . = . + __stack_usr_size;\n        __stack_usr_start = .;\n        . = . + __stack_und_size;\n        __stack_und_start = .;\n        . = . + __stack_fiq_size;\n        __stack_fiq_start = .;\n        . = . + __stack_irq_size;\n        __stack_irq_start = .;\n        . = . + __stack_abt_size;\n        __stack_abt_start = .;\n        . = . + __stack_svc_size;\n        __stack_svc_start = .;\n\n        PROVIDE(__stack_end = .);\n    } > ram\n\n    __heap2_size = LENGTH(ram_ethernet);\n    .heap2 (NOLOAD) :\n    {\n        PROVIDE(__heap2_start = . );\n        . = . + __heap2_size;\n        PROVIDE(__heap2_max = .);       \/* _heap shall always be < _heap_max *\/\n    } > ram_ethernet\n\n    . = ORIGIN(ram_usb);\n    .usbdata (NOLOAD) :                 \/* USB RAM section, may be used otherwise if USB is disabled *\/\n    {\n        *(.usbdata)\n    } > ram_usb\n\n    .heap3 ALIGN(0x1000) (NOLOAD) :\n    {\n        __heap3_size = ORIGIN(ram_usb) + LENGTH(ram_usb) - ABSOLUTE(.);\n        PROVIDE(__heap3_start = . );\n        . += __heap3_size;\n        PROVIDE(__heap3_max = .);\n    } > ram_usb\n    __heap_size = SIZEOF(.heap3);\n\n\n    .batteryram (NOLOAD) :              \/* battery ram stays on during powerdown but needs to be handled specially *\/\n    {\n        *(.batteryram)\n    } > ram_battery\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"74e0df5d2af0a2ea5dd92094bd9f84ddfa63c813","subject":"boot\/mbr\/syslinux-mbr: drop new gcc 8.2.1 section","message":"boot\/mbr\/syslinux-mbr: drop new gcc 8.2.1 section\n\ngcc 8.2.1 introduced a new section in ELF files, .note.gnu.property:\n\n    0400 0000 1000 0000 0500 0000 474e 5500\n    0100 00c0 0400 0000 0100 0000 0000 0000\n\nDrop this section in the linker script.\n","repos":"fishilico\/shared,fishilico\/shared,fishilico\/shared,fishilico\/shared,fishilico\/shared,fishilico\/shared,fishilico\/shared","old_file":"boot\/mbr\/syslinux-mbr\/mbr.ld","new_file":"boot\/mbr\/syslinux-mbr\/mbr.ld","new_contents":"\/*\n * Linker script for MBR\n *\/\n\n\/* Script for -z combreloc: combine and sort reloc sections *\/\nEXTERN(_start)\nENTRY(_start)\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  . = 0x600;\n  .text           :\n  {\n    *(.text*)\n    *(.rodata*)\n  } =0x90909090\n\n  . = ALIGN(4);\n  .data\t\t  :\n  {\n    *(.data*)\n  }\n\n  . = ALIGN(128);\n  .bss\t\t  :\n  {\n    *(.bss*)\n  }\n\n  . = 0x7c00;\n  .bootsec\t  :\n  {\n    *(.bootsec)\n  }\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : {\n    *(.note.GNU-stack)\n    *(.note.gnu.*)\n  }\n}\n","old_contents":"\/*\n * Linker script for MBR\n *\/\n\n\/* Script for -z combreloc: combine and sort reloc sections *\/\nEXTERN(_start)\nENTRY(_start)\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  . = 0x600;\n  .text           :\n  {\n    *(.text*)\n    *(.rodata*)\n  } =0x90909090\n\n  . = ALIGN(4);\n  .data\t\t  :\n  {\n    *(.data*)\n  }\n\n  . = ALIGN(128);\n  .bss\t\t  :\n  {\n    *(.bss*)\n  }\n\n  . = 0x7c00;\n  .bootsec\t  :\n  {\n    *(.bootsec)\n  }\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"9485fa006625f056b8a175c90e2a1f7f2386fb82","subject":"linker file: make length match comment","message":"linker file: make length match comment\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00070000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*) \/* for RISC-V *\/\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to\n\t\t * mark the first address in the SRAM memory. Since ELF files do\n\t\t * not really need to specify this address as they only care about\n\t\t * loading into flash, we need to manually mark this address for\n\t\t * elf2tab. elf2tab will use it to add a fixed address header in the\n\t\t * TBF header if needed.\n\t\t *\/\n\t    _sram_origin = .;\n\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        KEEP(*(.sbss*)) \/* for RISC-V *\/\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*) \/* for RISC-V *\/\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to\n\t\t * mark the first address in the SRAM memory. Since ELF files do\n\t\t * not really need to specify this address as they only care about\n\t\t * loading into flash, we need to manually mark this address for\n\t\t * elf2tab. elf2tab will use it to add a fixed address header in the\n\t\t * TBF header if needed.\n\t\t *\/\n\t    _sram_origin = .;\n\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        KEEP(*(.sbss*)) \/* for RISC-V *\/\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"323d6dd0ac406c3389c2521ab8d866cc43aa9952","subject":"mess with link.ld to make sure (?) that <main> starts at 0x0","message":"mess with link.ld to make sure (?) that <main> starts at 0x0\n","repos":"maikmerten\/riscv-tomthumb,maikmerten\/riscv-tomthumb","old_file":"src\/c\/link.ld","new_file":"src\/c\/link.ld","new_contents":"\/*======================================================================*\/\n\/* Default maven linker script                                          *\/\n\/*======================================================================*\/\n\/* This is the default linker script for maven. It is based off of the\n   mips idt32.ld linker script. I have added many more comments and\n   tried to clean things up a bit. For more information about standard\n   MIPS sections see Section 9.5 of \"See MIPS Run Linux\" by Dominic\n   Sweetman. For more generic information about the init, fini, ctors,\n   and dtors sections see the paper titled \"ELF From the Programmers\n   Perspective\" by Hongiu Lu. *\/\n\n\/*----------------------------------------------------------------------*\/\n\/* Setup                                                                *\/\n\/*----------------------------------------------------------------------*\/\n\n\/* The OUTPUT_ARCH command specifies the machine architecture where the\n   argument is one of the names used in the BFD library. More\n   specifically one of the entires in bfd\/cpu-mips.c *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\n\/* The ENTRY command specifies the entry point (ie. first instruction to\n   execute). The symbol _start is defined in crt0.S *\/\n\nENTRY( _start )\n\n\/* The GROUP command is special since the listed archives will be\n   searched repeatedly until there are no new undefined references. We\n   need this since -lc depends on -lgloss and -lgloss depends on -lc. I\n   thought gcc would automatically include -lgcc when needed, but\n   idt32.ld includes it explicitly here and I was seeing link errors\n   without it. *\/\n\nGROUP( -lc -lgloss -lgcc )\n\n\/*----------------------------------------------------------------------*\/\n\/* Sections                                                             *\/\n\/*----------------------------------------------------------------------*\/\n\/* This is where we specify how the input sections map to output\n   sections. The .= commands set the location counter, and the\n   sections are inserted in increasing address order according to the\n   location counter. The following statement will take all of the .bar\n   input sections and reloate them into the .foo output section which\n   starts at address 0x1000.\n\n    . = 0.x1000;\n    .foo : { *(.bar) }\n\n   If we wrap an input specification with a KEEP command then it\n   prevents it from being eliminted during \"link-time garbage\n   collection\". I'm not sure what this is, so I just followed what was\n   done in idt32.ld.\n\n   We can also set a global external symbol to a specific address in the\n   output binary with this syntax:\n\n    _etext = .;\n    PROVIDE( etext = . );\n\n   This will set the global symbol _ftext to the current location. If we\n   wrap this in a PROVIDE commad, the symbol will only be set if it is\n   not defined. We do this with symbols which don't begin with an\n   underscore since technically in ansi C someone might have a function\n   with the same name (eg. etext).\n\n   If we need to label the beginning of a section we need to make sure\n   that the linker doesn't insert an orphan section inbetween where we\n   set the symbol and the actual begining of the section. We can do that\n   by assigning the location dot to itself.\n\n    . = .\n    _ftext = .;\n    .text :\n    { }\n\n   *\/\n\nSECTIONS\n{\n\n  \/*--------------------------------------------------------------------*\/\n  \/* Code and read-only segment                                         *\/\n  \/*--------------------------------------------------------------------*\/\n\n  \/* Begining of code and text segment *\/\n  \/\/. = 0x00010000;\n  . = 0x0;\n  _ftext = .;\n  PROVIDE( eprol = . );\n\n  \/* text: Program code section *\/\n  .text : \n  {\n    *(.text.*)\n    *(.text)\n    *(.gnu.linkonce.t.*)\n  }\n\n  \/* init: Code to execute before main (called by crt0.S) *\/\n  .init : \n  {\n    KEEP( *(.init) )\n  }\n\n  \/* fini: Code to execute after main (called by crt0.S) *\/\n  .fini : \n  {\n    KEEP( *(.fini) )\n  }\n\n  \/* rodata: Read-only data *\/\n  .rodata : \n  {\n    *(.rdata)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n  }\n\n  \/* End of code and read-only segment *\/\n  PROVIDE( etext = . );\n  _etext = .;\n\n  \/*--------------------------------------------------------------------*\/\n  \/* Global constructor\/destructor segement                             *\/\n  \/*--------------------------------------------------------------------*\/\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array ))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array ))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  \/*--------------------------------------------------------------------*\/\n  \/* Other misc gcc segments (this was in idt32.ld)                     *\/\n  \/*--------------------------------------------------------------------*\/\n  \/* I am not quite sure about these sections but it seems they are for\n     C++ exception handling. I think .jcr is for \"Java Class\n     Registration\" but it seems to end up in C++ binaries as well. *\/\n\n  .eh_frame_hdr     : { *(.eh_frame_hdr)     }\n  .eh_frame         : { KEEP( *(.eh_frame) ) }\n  .gcc_except_table : { *(.gcc_except_table) }\n  .jcr              : { KEEP (*(.jcr))       } \n\n  \/*--------------------------------------------------------------------*\/\n  \/* Initialized data segment                                           *\/\n  \/*--------------------------------------------------------------------*\/\n\n  \/* Start of initialized data segment *\/\n  . = ALIGN(16);\n   _fdata = .;\n\n  \/* data: Writable data *\/\n  .data : \n  {\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n  }\n\n  \/* End of initialized data segment *\/\n  PROVIDE( edata = . );\n  _edata = .;\n\n  \/* Have _gp point to middle of sdata\/sbss to maximize displacement range *\/\n  . = ALIGN(16);\n  _gp = . + 0x800;\n\n  \/* Writable small data segment *\/\n  .sdata : \n  {\n    *(.sdata)\n    *(.sdata.*)\n    *(.srodata.*)\n    *(.gnu.linkonce.s.*)\n  }\n\n  \/*--------------------------------------------------------------------*\/\n  \/* Uninitialized data segment                                         *\/\n  \/*--------------------------------------------------------------------*\/\n\n  \/* Start of uninitialized data segment *\/\n  . = ALIGN(8);\n  _fbss = .;\n\n  \/* Writable uninitialized small data segment *\/\n  .sbss : \n  {\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n  }\n\n  \/* bss: Uninitialized writeable data section *\/\n  . = .;\n  _bss_start = .;\n  .bss : \n  {\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n  }\n\n  \/* End of uninitialized data segment (used by syscalls.c for heap) *\/\n  PROVIDE( end = . );\n  _end = ALIGN(8);\n}\n","old_contents":"\/*======================================================================*\/\n\/* Default maven linker script                                          *\/\n\/*======================================================================*\/\n\/* This is the default linker script for maven. It is based off of the\n   mips idt32.ld linker script. I have added many more comments and\n   tried to clean things up a bit. For more information about standard\n   MIPS sections see Section 9.5 of \"See MIPS Run Linux\" by Dominic\n   Sweetman. For more generic information about the init, fini, ctors,\n   and dtors sections see the paper titled \"ELF From the Programmers\n   Perspective\" by Hongiu Lu. *\/\n\n\/*----------------------------------------------------------------------*\/\n\/* Setup                                                                *\/\n\/*----------------------------------------------------------------------*\/\n\n\/* The OUTPUT_ARCH command specifies the machine architecture where the\n   argument is one of the names used in the BFD library. More\n   specifically one of the entires in bfd\/cpu-mips.c *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\n\/* The ENTRY command specifies the entry point (ie. first instruction to\n   execute). The symbol _start is defined in crt0.S *\/\n\nENTRY( _start )\n\n\/* The GROUP command is special since the listed archives will be\n   searched repeatedly until there are no new undefined references. We\n   need this since -lc depends on -lgloss and -lgloss depends on -lc. I\n   thought gcc would automatically include -lgcc when needed, but\n   idt32.ld includes it explicitly here and I was seeing link errors\n   without it. *\/\n\nGROUP( -lc -lgloss -lgcc )\n\n\/*----------------------------------------------------------------------*\/\n\/* Sections                                                             *\/\n\/*----------------------------------------------------------------------*\/\n\/* This is where we specify how the input sections map to output\n   sections. The .= commands set the location counter, and the\n   sections are inserted in increasing address order according to the\n   location counter. The following statement will take all of the .bar\n   input sections and reloate them into the .foo output section which\n   starts at address 0x1000.\n\n    . = 0.x1000;\n    .foo : { *(.bar) }\n\n   If we wrap an input specification with a KEEP command then it\n   prevents it from being eliminted during \"link-time garbage\n   collection\". I'm not sure what this is, so I just followed what was\n   done in idt32.ld.\n\n   We can also set a global external symbol to a specific address in the\n   output binary with this syntax:\n\n    _etext = .;\n    PROVIDE( etext = . );\n\n   This will set the global symbol _ftext to the current location. If we\n   wrap this in a PROVIDE commad, the symbol will only be set if it is\n   not defined. We do this with symbols which don't begin with an\n   underscore since technically in ansi C someone might have a function\n   with the same name (eg. etext).\n\n   If we need to label the beginning of a section we need to make sure\n   that the linker doesn't insert an orphan section inbetween where we\n   set the symbol and the actual begining of the section. We can do that\n   by assigning the location dot to itself.\n\n    . = .\n    _ftext = .;\n    .text :\n    { }\n\n   *\/\n\nSECTIONS\n{\n\n  \/*--------------------------------------------------------------------*\/\n  \/* Code and read-only segment                                         *\/\n  \/*--------------------------------------------------------------------*\/\n\n  \/* Begining of code and text segment *\/\n  \/\/. = 0x00010000;\n  . = 0x0;\n  _ftext = .;\n  PROVIDE( eprol = . );\n\n  \/* text: Program code section *\/\n  .text : \n  {\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t.*)\n  }\n\n  \/* init: Code to execute before main (called by crt0.S) *\/\n  .init : \n  {\n    KEEP( *(.init) )\n  }\n\n  \/* fini: Code to execute after main (called by crt0.S) *\/\n  .fini : \n  {\n    KEEP( *(.fini) )\n  }\n\n  \/* rodata: Read-only data *\/\n  .rodata : \n  {\n    *(.rdata)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n  }\n\n  \/* End of code and read-only segment *\/\n  PROVIDE( etext = . );\n  _etext = .;\n\n  \/*--------------------------------------------------------------------*\/\n  \/* Global constructor\/destructor segement                             *\/\n  \/*--------------------------------------------------------------------*\/\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array ))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array ))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  \/*--------------------------------------------------------------------*\/\n  \/* Other misc gcc segments (this was in idt32.ld)                     *\/\n  \/*--------------------------------------------------------------------*\/\n  \/* I am not quite sure about these sections but it seems they are for\n     C++ exception handling. I think .jcr is for \"Java Class\n     Registration\" but it seems to end up in C++ binaries as well. *\/\n\n  .eh_frame_hdr     : { *(.eh_frame_hdr)     }\n  .eh_frame         : { KEEP( *(.eh_frame) ) }\n  .gcc_except_table : { *(.gcc_except_table) }\n  .jcr              : { KEEP (*(.jcr))       } \n\n  \/*--------------------------------------------------------------------*\/\n  \/* Initialized data segment                                           *\/\n  \/*--------------------------------------------------------------------*\/\n\n  \/* Start of initialized data segment *\/\n  . = ALIGN(16);\n   _fdata = .;\n\n  \/* data: Writable data *\/\n  .data : \n  {\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n  }\n\n  \/* End of initialized data segment *\/\n  PROVIDE( edata = . );\n  _edata = .;\n\n  \/* Have _gp point to middle of sdata\/sbss to maximize displacement range *\/\n  . = ALIGN(16);\n  _gp = . + 0x800;\n\n  \/* Writable small data segment *\/\n  .sdata : \n  {\n    *(.sdata)\n    *(.sdata.*)\n    *(.srodata.*)\n    *(.gnu.linkonce.s.*)\n  }\n\n  \/*--------------------------------------------------------------------*\/\n  \/* Uninitialized data segment                                         *\/\n  \/*--------------------------------------------------------------------*\/\n\n  \/* Start of uninitialized data segment *\/\n  . = ALIGN(8);\n  _fbss = .;\n\n  \/* Writable uninitialized small data segment *\/\n  .sbss : \n  {\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n  }\n\n  \/* bss: Uninitialized writeable data section *\/\n  . = .;\n  _bss_start = .;\n  .bss : \n  {\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n  }\n\n  \/* End of uninitialized data segment (used by syscalls.c for heap) *\/\n  PROVIDE( end = . );\n  _end = ALIGN(8);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8dd52dc9fd059c8f2db1b74594eaebe6758f1cce","subject":"\tlib\/ldscripts\/stm32f100xx.ld : Some script moved to kernel.ld","message":"\tlib\/ldscripts\/stm32f100xx.ld : Some script moved to kernel.ld\n","repos":"masilvabustos\/CabbageOS,masilvabustos\/CabbageOS","old_file":"lib\/ldscripts\/stm32f100xx.ld","new_file":"lib\/ldscripts\/stm32f100xx.ld","new_contents":"\nSECTIONS {\n\t\n\t__end_of_ram = ALIGN(ORIGIN(SRAM) + LENGTH(SRAM), 4) ;\n\n\t.cm3.isr_vector ORIGIN(FLASH) : {\n\t\tLONG(__end_of_ram)\n\t\tLONG(Reset)\n\t\tLONG(NMI_Handler)\n\t\tLONG(HardFault_Handler)\n\t\tLONG(MemManage_Handler)\n\t\tLONG(BusFault_Handler)\n\t\t. = 0x2c ;\n\t\tLONG(SVC_Handler)\n\t\tLONG(DebugMon_Handler)\n\t\t. = 0x38 ;\n\t\tLONG(PSV_Handler)\n\t\tLONG(SysTick_Handler)\n\n\t\t* (.isr_vector)\n\n\t} > FLASH\n\n\t.text : { \n\t\t* (.text) \n\t} > FLASH\n\n\t.data : AT(ADDR(.text) + SIZEOF(.text)) { \n\t\t* (.data) \n\t} > SRAM\n\n\t.bss : {\n\t\t* (.bss)\n\t} > SRAM\n\n\t__brk = . ;\n\n\t.stm32f100xx.preripherals_registers : {\n\t\t. = 0x10800 ;\n\t\tGPIOA_CRL \t= . + 0x00 ;\n\t\tGPIOA_CRH \t= . + 0x04 ;\n\t\tGPIOA_IDR \t= . + 0x08 ;\n\t\tGPIOA_ODR \t= . + 0x0C ;\n\t\tGPIOA_BSRR \t= . + 0x10 ;\n\t\tGPIOA_BRR\t= . + 0x14 ;\n\t\tGPIOA_LCKR\t= . + 0x18 ;\n\t\t\n\t\t. = 0x11000 ;\n\t\tGPIOC_CRL \t= . + 0x00 ;\n\t\tGPIOC_CRH \t= . + 0x04 ;\n\t\tGPIOC_IDR \t= . + 0x08 ;\n\t\tGPIOC_ODR \t= . + 0x0C ;\n\t\tGPIOC_BSRR \t= . + 0x10 ;\n\t\tGPIOC_BRR\t= . + 0x14 ;\n\t\tGPIOC_LCKR\t= . + 0x18 ;\n\t\n\n\n\n\n\t\t\n\t} > PERIPH\n\n\t\n}\n\n","old_contents":"\nSECTIONS {\n\t\n\t__end_of_ram = ALIGN(ORIGIN(SRAM) + LENGTH(SRAM), 4) ;\n\n\t.cm3.isr_vector ORIGIN(FLASH) : {\n\t\tLONG(__end_of_ram)\n\t\tLONG(Reset)\n\t\tLONG(NMI_Handler)\n\t\tLONG(HardFault_Handler)\n\t\tLONG(MemManage_Handler)\n\t\tLONG(BusFault_Handler)\n\t\t. = 0x2c ;\n\t\tLONG(SVC_Handler)\n\t\tLONG(DebugMon_Handler)\n\t\t. = 0x38 ;\n\t\tLONG(PSV_Handler)\n\t\tLONG(SysTick_Handler)\n\n\t\t* (.isr_vector)\n\n\t} > FLASH\n\n\t.text : { \n\t\t* (.text) \n\t} > FLASH\n\n\t.data : { \n\t\t* (.data) \n\t} > SRAM\n\n\t.bss : {\n\t\t _bss_start = . ;\n\t\t* (.bss) * (COMMON)\n\t\t_bss_end = . ;\n\t} > SRAM\n\n\t__edata = . ;\n\n\t.stm32f100xx.preripherals_registers : {\n\t\t. = 0x800 ;\n\t\tGPIOA_CRL \t= . + 0x00 ;\n\t\tGPIOA_CRH \t= . + 0x04 ;\n\t\tGPIOA_IDR \t= . + 0x08 ;\n\t\tGPIOA_ODR \t= . + 0x0C ;\n\t\tGPIOA_BSRR \t= . + 0x10 ;\n\t\tGPIOA_BRR\t= . + 0x14 ;\n\t\tGPIOA_LCKR\t= . + 0x18 ;\n\t} > PERIPH\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"d777ae56e91428282a021272234aa4165b505fbf","subject":"\u628abss\u548c\u6808\u5206\u5f00\u4e86\uff0c\u4ee5\u514d\u6df7\u4e71","message":"\u628abss\u548c\u6808\u5206\u5f00\u4e86\uff0c\u4ee5\u514d\u6df7\u4e71\n","repos":"IcebergOS\/frogimine,IcebergOS\/frogimine,IcebergOS\/Cryst","old_file":"scripts\/linker.ld","new_file":"scripts\/linker.ld","new_contents":"ENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t\t. = ALIGN(4096);\n\t}\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(4096);\n\t}\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t. = ALIGN(4096);\n\t}\n\t.stab :\n\t{\n\t\t*(.stab)\n\t\t. = ALIGN(4096);\n\t}\n\t.stabstr :\n\t{\n\t\t*(.stabstr)\n\t\t. = ALIGN(4096);\n\t}\n\n\tSTACK_TOP = .;\n\t. = ALIGN(32768);\n\tKERNEL_CODE_END = .;\n\n\t\/DISCARD\/ : { *(.comment) *(.eh_frame) }\n}\n","old_contents":"ENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t\t. = ALIGN(4096);\n\t}\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(4096);\n\t}\n\t.stab :\n\t{\n\t\t*(.stab)\n\t\t. = ALIGN(4096);\n\t}\n\t.stabstr :\n\t{\n\t\t*(.stabstr)\n\t\t. = ALIGN(4096);\n\t}\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t. = ALIGN(4096);\n\t}\n\n\tSTACK_TOP = .;\n\t. = ALIGN(32768);\n\tKERNEL_CODE_END = .;\n\n\t\/DISCARD\/ : { *(.comment) *(.eh_frame) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"0e31eb458e649b66277e3705f603216740e845dd","subject":"esp32: Move heap_alloc_caps to IRAM","message":"esp32: Move heap_alloc_caps to IRAM\n\nRest of malloc() path was already in IRAM\n","repos":"mashaoze\/esp-idf,ajs124\/esp-idf,mashaoze\/esp-idf,Hermiedapwdrman\/esp-idf,tidyjiang8\/esp-idf-zh,nineisk\/esp-idf,ajs124\/esp-idf,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,dschaefer\/esp-idf,dantonets\/Pingzee-ESP32,dschaefer\/esp-idf,tidyjiang8\/esp-idf-zh,empoweredhomes\/esp-idf,dantonets\/Pingzee-ESP32,nineisk\/esp-idf,tidyjiang8\/esp-idf-zh,www220\/esp-idf,armada-ai\/esp-idf,empoweredhomes\/esp-idf,jaracil\/esp-idf,hwmaier\/esp-idf,empoweredhomes\/esp-idf,shukyisme\/esp-idf-kwik,dantonets\/Pingzee-ESP32,shukyisme\/esp-idf-kwik,MIhanguangyi\/esp-idf,armada-ai\/esp-idf,tidyjiang8\/esp-idf-zh,MIhanguangyi\/esp-idf,espressif\/esp-idf,www220\/esp-idf,jaracil\/esp-idf,Hermiedapwdrman\/esp-idf,ajs124\/esp-idf,jaracil\/esp-idf,dschaefer\/esp-idf,nineisk\/esp-idf,armada-ai\/esp-idf,tidyjiang8\/esp-idf-zh,espressif\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,espressif\/esp-idf,shukyisme\/esp-idf-kwik,dschaefer\/esp-idf,Hermiedapwdrman\/esp-idf,shukyisme\/esp-idf-kwik,dschaefer\/esp-idf,www220\/esp-idf,www220\/esp-idf,empoweredhomes\/esp-idf,hwmaier\/esp-idf,hwmaier\/esp-idf,empoweredhomes\/esp-idf,MIhanguangyi\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,Hermiedapwdrman\/esp-idf,dantonets\/Pingzee-ESP32,ajs124\/esp-idf,espressif\/esp-idf,nineisk\/esp-idf,jaracil\/esp-idf,MIhanguangyi\/esp-idf,Hermiedapwdrman\/esp-idf,MIhanguangyi\/esp-idf,hwmaier\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libesp32.a:heap_alloc_caps.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *librtc_clk.a:(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libcore.a:ets_timer.o(.literal .text .literal.* .text.*)\n    *libnet80211.a:ieee80211_misc.o(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libcoexist.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *librtc_clk.a:(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libcore.a:ets_timer.o(.literal .text .literal.* .text.*)\n    *libnet80211.a:ieee80211_misc.o(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libcoexist.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cbf865020685adab5be853157662007c243993ef","subject":"FIX: fixed ld script correct startup (.bss zero and .data copy)","message":"FIX: fixed ld script correct startup (.bss zero and .data copy)\n\nSigned-off-by: Giuseppe Monteleone <59bd0a3ff43b32849b319e645d4798d8a5d1e889@ing-monteleone.com>\n","repos":"kobrabyte\/YasminOS,geppo12\/YasminOS,geppo12\/YasminOS,kobrabyte\/YasminOS","old_file":"src\/application.ld","new_file":"src\/application.ld","new_contents":"\/* Memory Definitions *\/\nMEMORY\n{\n  CODE  (r)  : ORIGIN = 0x00000000, LENGTH = 0x1000\n  DRAM  (rw) : ORIGIN = 0x10000000, LENGTH = 0x0400\n} \n\nTOP_RAM\t\t= 0x10000400;\nSTACK_SIZE  = 0x100;\n\nSECTIONS\n{\n  .text : \n  {\n  \t_text = .;\n\tKEEP(*(.vectors))\n\tKEEP(*(.text.startup))\n\t. = 0x2FC; \n\tKEEP(*(.text.crp))   \n    *(.text.*)\n    *(.rodata.*)\n    *(.glue_7)\n    *(.glue_7t)\n    . = ALIGN(4);\n  } > CODE\n  _etext = .;\n  \n  .trace (NOLOAD) :\n  {\n  \tKEEP(*(.trace));\n  }  \n \n  \/* .data section which is used for initialized data *\/\n  .data : AT (ADDR(.text) + SIZEOF(.text))  \n  {\n  \t_data = .;\n    *(.data.*)\n\t. = ALIGN(4);  \n  } > DRAM\n  PROVIDE(_edata = .);\n  \n  .bss (NOLOAD) :\n  {\n  \t_bss = .;\n    *(.bss.*)\n    . = ALIGN(4);\n  } > DRAM\n  PROVIDE(_ebss = .);\n  \n  \n  PROVIDE(_stack = TOP_RAM - STACK_SIZE);\n  PROVIDE(_estack = TOP_RAM);  \n }","old_contents":"\/* Memory Definitions *\/\nMEMORY\n{\n  CODE  (r)  : ORIGIN = 0x00000000, LENGTH = 0x1000\n  DRAM  (rw) : ORIGIN = 0x10000000, LENGTH = 0x0400\n} \n\nTOP_RAM\t\t= 0x10000400;\nSTACK_SIZE  = 0x100;\n\nSECTIONS\n{\n  .text : \n  {\n  \t_text = .;\n\tKEEP(*(.vectors))\n\tKEEP(*(.text.startup))\n\t. = 0x2FC; \n\tKEEP(*(.text.crp))   \n    *(.text)        \t \/* Startup code *\/\n    *(.rodata)\n    *(.glue_7)\n    *(.glue_7t)\n    . = ALIGN(4);\n  } > CODE\n  _etext = .;\n  \n  .trace (NOLOAD) :\n  {\n  \tKEEP(*(.trace));\n  }  \n \n  \/* .data section which is used for initialized data *\/\n  .data : AT (ADDR(.text) + SIZEOF(.text))  \n  {\n  \t_data = .;\n    *(.data)\n\t. = ALIGN(4);  \n  } > DRAM\n  _edata = .;\n  \n  .bss (NOLOAD) :\n  {\n  \t_bss = .;\n    *(.bss)\n    _ebss = .;\n    . = ALIGN(4);\n  } > DRAM\n  \n  PROVIDE(_stack = TOP_RAM - STACK_SIZE);\n  PROVIDE(_estack = TOP_RAM);  \n }","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"cd61fc8e44202feb20a4c52b56f75740aa72d075","subject":"stm32\/boards\/stm32h743.ld: Enable D2 RAM and add eth-buffer section.","message":"stm32\/boards\/stm32h743.ld: Enable D2 RAM and add eth-buffer section.\n","repos":"bvernoux\/micropython,henriknelson\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,henriknelson\/micropython,bvernoux\/micropython,adafruit\/circuitpython,henriknelson\/micropython,adafruit\/circuitpython,bvernoux\/micropython,adafruit\/circuitpython,bvernoux\/micropython,henriknelson\/micropython,adafruit\/circuitpython,henriknelson\/micropython,bvernoux\/micropython","old_file":"ports\/stm32\/boards\/stm32h743.ld","new_file":"ports\/stm32\/boards\/stm32h743.ld","new_contents":"\/*\n    GNU linker script for STM32H743\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 128K    \/* sector 0, 128K *\/\n    FLASH_FS (r)    : ORIGIN = 0x08020000, LENGTH = 128K    \/* sector 1, 128K *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K   \/* sectors 6*128 + 8*128 *\/\n    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    \/* Used for storage cache *\/\n    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 512K    \/* AXI SRAM *\/    \n    RAM_D2 (xrw)    : ORIGIN = 0x30000000, LENGTH = 288K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K; \/* tunable *\/\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n\n\/* Define output sections *\/\nSECTIONS\n{\n    .eth_buffers (NOLOAD) : {\n        . = ABSOLUTE(0x30040000);\n        *eth.o*(.bss.eth_dma)\n    } >RAM_D2\n}\n","old_contents":"\/*\n    GNU linker script for STM32H743\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 128K    \/* sector 0, 128K *\/\n    FLASH_FS (r)    : ORIGIN = 0x08020000, LENGTH = 128K    \/* sector 1, 128K *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K   \/* sectors 6*128 + 8*128 *\/\n    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    \/* Used for storage cache *\/\n    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 512K    \/* AXI SRAM *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K; \/* tunable *\/\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7a9e59030edd80af709a5619464e26e4d8d7421d","subject":"ldscript: use wildcard for text\/date section placement","message":"ldscript: use wildcard for text\/date section placement\n\nSigned-off-by: Mahavir Jain <934132006b6c9b08831ff9ee396b986615350165@gmail.com>\n","repos":"mahavirj\/tinyos,mahavirj\/tinyos","old_file":"ldscript\/linker.ld","new_file":"ldscript\/linker.ld","new_contents":"ENTRY(_start)                \/* the name of the entry label *\/\n\nSECTIONS {\n    . = 0x00100000;          \/* the code should be loaded at 1 MB *\/\n\n    .text ALIGN (0x1000) :   \/* align at 4 KB *\/\n    {\n        code = .;\n\t*(.text*)             \/* all text sections from all files *\/\n        *(.rodata*)          \/* all read-only data sections from all files *\/\n    }\n\n    .data ALIGN (0x1000) :   \/* align at 4 KB *\/\n    {\n\tdata = .;\n        *(.data*)             \/* all data sections from all files *\/\n    }\n\n    .bss ALIGN (0x1000) :    \/* align at 4 KB *\/\n    {\n\tbss = .;\n        *(COMMON)            \/* all COMMON sections from all files *\/\n        *(.bss*)              \/* all bss sections from all files *\/\n    }\n\n    end = .;\n}\n","old_contents":"ENTRY(_start)                \/* the name of the entry label *\/\n\nSECTIONS {\n    . = 0x00100000;          \/* the code should be loaded at 1 MB *\/\n\n    .text ALIGN (0x1000) :   \/* align at 4 KB *\/\n    {\n        code = .;\n\t*(.text)             \/* all text sections from all files *\/\n        *(.rodata*)          \/* all read-only data sections from all files *\/\n    }\n\n    .data ALIGN (0x1000) :   \/* align at 4 KB *\/\n    {\n\tdata = .;\n        *(.data)             \/* all data sections from all files *\/\n    }\n\n    .bss ALIGN (0x1000) :    \/* align at 4 KB *\/\n    {\n\tbss = .;\n        *(COMMON)            \/* all COMMON sections from all files *\/\n        *(.bss)              \/* all bss sections from all files *\/\n    }\n\n    end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a066143de47ca2af44508f6ae5562d0e0776b8f2","subject":"Move C++ exceptions table to end of ELF","message":"Move C++ exceptions table to end of ELF\n\nWe currently don't actually serialize it to the TBF (we probably should\nbe if we care about exceptions), so it was screwing up the computation\nfor where the rel.data section would be placed. Placing it at the end,\nafter the dummy `endsec` section, avoids that, and otherwise doesn't\nmake a difference.\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    int got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    int data_size;\n         *    uint32_t bss_start;\n         *    int bss_size;\n         *    uint32_t reldata_start;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_sbss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n    } > FLASH =0xFF\n\n\n\/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    _sbss = .;\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += STACK_SIZE;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += APP_HEAP_SIZE;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += KERNEL_HEAP_SIZE;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    int got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    int data_size;\n         *    uint32_t bss_start;\n         *    int bss_size;\n         *    uint32_t reldata_start;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_sbss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n    } > FLASH =0xFF\n\n\n\/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    _sbss = .;\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += STACK_SIZE;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += APP_HEAP_SIZE;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += KERNEL_HEAP_SIZE;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2d279c00c3ccbae1a54aa130b8053627d08e0c5e","subject":"ldscript: add markers for .text\/.rodata end","message":"ldscript: add markers for .text\/.rodata end\n\n* Somehow markers within section like __bss_start\/end are\npointing to same value, removed them for now.\n* Also with PROVIDE attribute value seems to be start of memory\nitself, hence not using for now\n\nSigned-off-by: Mahavir Jain <934132006b6c9b08831ff9ee396b986615350165@gmail.com>\n","repos":"mahavirj\/tinyos,mahavirj\/tinyos","old_file":"ldscript\/linker.ld","new_file":"ldscript\/linker.ld","new_contents":"\/* the name of the entry label *\/\nENTRY(_start)\n\nSECTIONS {\n\t. = 0xC0100000;          \/* Kernel will execute from 3G + 1M *\/\n\n\t.text ALIGN (0x1000) : AT(0x100000)   \/* align at 4 KB *\/\n\t{\n\t\t*(.text*)             \/* all text sections from all files *\/\n\t\t*(.rodata*)          \/* all read-only data sections from all files *\/\n\t}\n\t\/* Align on page boundary, read only page mapping *\/\n\t. = ALIGN(0x1000);\n\tetext = .;\n\n\t.data ALIGN (0x1000) :   \/* align at 4 KB *\/\n\t{\n\t\t*(.data*)             \/* all data sections from all files *\/\n\t}\n\n\t.bss ALIGN (0x1000) :    \/* align at 4 KB *\/\n\t{\n\t\t*(COMMON)           \/* all COMMON sections from all files *\/\n\t\t*(.bss*)             \/* all bss sections from all files *\/\n\t}\n\n\t. = ALIGN(4);\n\tend = .;\n}\n","old_contents":"\/* the name of the entry label *\/\nENTRY(_start)\n\nSECTIONS {\n\t. = 0xC0100000;          \/* Kernel will execute from 3G + 1M *\/\n\n\t.text ALIGN (0x1000) : AT(0x100000)   \/* align at 4 KB *\/\n\t{\n\t\t*(.text*)             \/* all text sections from all files *\/\n\t\t*(.rodata*)          \/* all read-only data sections from all files *\/\n\t}\n\tPROVIDE(__etext = .);\n\n\t.data ALIGN (0x1000) :   \/* align at 4 KB *\/\n\t{\n\t\t__data_start = .;\n\t\t*(.data*)             \/* all data sections from all files *\/\n\t\t__data_end = .;\n\t}\n\tPROVIDE(__edata = .);\n\n\t.bss ALIGN (0x1000) :    \/* align at 4 KB *\/\n\t{\n\t\t__bss_start = .;\n\t\t*(COMMON)           \/* all COMMON sections from all files *\/\n\t\t*(.bss*)             \/* all bss sections from all files *\/\n\t\t__bss_end = .;\n\t}\n\n\tend = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"51db68f03a11df4b469de0332a09463c7ba0863d","subject":"updated linker script","message":"updated linker script\n","repos":"stateos\/IntrOS-LM4F120XL,stateos\/IntrOS-LM4F120XL","old_file":"startup\/LM4F\/GNUCC\/script.ld","new_file":"startup\/LM4F\/GNUCC\/script.ld","new_contents":"\/*******************************************************************************\n@file     lm4f120h5qr.ld\n@author   Rajmund Szymanski\n@date     28.02.2017\n@brief    Linker script for LM4F120H5QR device with 256KB FLASH and 32KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x00000000, LENGTH = 256K\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  32K\n}\n\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__heap_start = LOADADDR(.proc_stack);\n\t__heap_end   = __ram_end - __proc_stack_size;\n\n\t__proc_stack_start = __heap_end;\n\t__proc_stack_end   = __ram_end;\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n\tPROVIDE(__process_stack_end   = __proc_stack_end);\n}\n","old_contents":"\/*******************************************************************************\n@file     lm4f120h5qr.ld\n@author   Rajmund Szymanski\n@date     02.01.2017\n@brief    Linker script for LM4F120H5QR device with 256KB FLASH and 32KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x00000000, LENGTH = 256K\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  32K\n}\n\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t. = ABSOLUTE(__ram_end - __proc_stack_size);\n\t\t__heap_end = .;\n\t} > RAM\n\n\t__heap_size = SIZEOF(.heap);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"12db9b87d85849e1fceede7ee2bac55e1d083da1","subject":"Place frameworks to lib section","message":"Place frameworks to lib section\n","repos":"yanbe\/platform-espressif8266","old_file":"ldscripts\/esp8266.flash.common.ld","new_file":"ldscripts\/esp8266.flash.common.ld","new_contents":"\/* Base temaplte for ESP8266 *\/\n\n\/* PlatformIO modifications: please search for \"*.pioenvs\"  *\/\n\n\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.pioenvs\\\\*\\\\lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\\\\*\\\\lib\\*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/lib\/*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\\\\*\\\\src\\\\*.o(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/src\/*.o(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.pioenvs\\\\*\\\\lib*.a:(.iram.text)\n    *.pioenvs\/*\/lib*.a:(.iram.text)\n    *.pioenvs\\\\*\\\\lib\\\\*.a:(.iram.text)\n    *.pioenvs\/*\/lib\/*.a:(.iram.text)\n    *.pioenvs\\\\*\\\\src\\\\*.o(.iram.text)\n    *.pioenvs\/*\/src\/*.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( ets_run = 0x40000e04 );\nPROVIDE ( ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n","old_contents":"\/* Base temaplte for ESP8266 *\/\n\n\/* PlatformIO modifications: please search for \"*.pioenvs\"  *\/\n\n\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.pioenvs\\\\*\\\\lib\\\\*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/lib\/*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\\\\*\\\\src\\\\*.o(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/src\/*.o(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.pioenvs\\\\*\\\\lib\\\\*.a:(.iram.text)\n    *.pioenvs\/*\/lib\/*.a:(.iram.text)\n    *.pioenvs\\\\*\\\\src\\\\*.o(.iram.text)\n    *.pioenvs\/*\/src\/*.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( ets_run = 0x40000e04 );\nPROVIDE ( ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"57694f28bc26c7d9bb164a2f0287bf8464ec6f85","subject":"word-align binary section boundaries","message":"word-align binary section boundaries\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n\n    \/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM\n\n    \/*\n     * __NOTE__: The following symbols are used only to hint to elf2tbf how much\n     * total memory to request from the OS.\n     *\/\n    .stack :\n    {\n        . += STACK_SIZE;\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM\n\n    .app_heap :\n    {\n        . += APP_HEAP_SIZE;\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM\n\n    .kernel_heap :\n    {\n        . += KERNEL_HEAP_SIZE;\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n\n    \/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n    } > SRAM\n\n    \/*\n     * __NOTE__: The following symbols are used only to hint to elf2tbf how much\n     * total memory to request from the OS.\n     *\/\n    .stack :\n    {\n        . += STACK_SIZE;\n    } > SRAM\n\n    .app_heap :\n    {\n        . += APP_HEAP_SIZE;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        . += KERNEL_HEAP_SIZE;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7a28e6c383b54c528fa33caad9aa010281e7be00","subject":"Fix formatting of linker script.","message":"Fix formatting of linker script.\n","repos":"charleskorn\/stm32f4-project-template,charleskorn\/stm32f4-project-template,charleskorn\/stm32f4-project-template","old_file":"lib\/stm32f4xx\/src\/stm32f407vg.ld","new_file":"lib\/stm32f4xx\/src\/stm32f407vg.ld","new_contents":"\/* Linker script for STM32F407VG Cortex-M4 ARM MCU                              *\/\n\/* From http:\/\/tech.munts.com\/MCU\/Frameworks\/ARM\/stm32f4\/stm32f407vg.ld         *\/\n\n\/* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp.              *\/\n\/*                                                                              *\/\n\/* Redistribution and use in source and binary forms, with or without           *\/\n\/* modification, are permitted provided that the following conditions are met:  *\/\n\/*                                                                              *\/\n\/* * Redistributions of source code must retain the above copyright notice,     *\/\n\/*   this list of conditions and the following disclaimer.                      *\/\n\/*                                                                              *\/\n\/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"  *\/\n\/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE    *\/\n\/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE   *\/\n\/* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE    *\/\n\/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR          *\/\n\/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF         *\/\n\/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS     *\/\n\/* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN      *\/\n\/* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)      *\/\n\/* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE   *\/\n\/* POSSIBILITY OF SUCH DAMAGE.                                                  *\/\n\nMEMORY\n{\n  flash (rx): ORIGIN = 0x08000000, LENGTH = 1024K\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K\n  ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n__rom_start__   = ORIGIN(flash);\n__rom_size__    = LENGTH(flash);\n__ram_start__   = ORIGIN(ram);\n__ram_size__    = LENGTH(ram);\n__ram_end__     = __ram_start__ + __ram_size__;\n__stack_end__   = __ram_end__;      \/* Top of RAM *\/\n__stack_size__  = 16K;\n__stack_start__ = __stack_end__ - __stack_size__;\n__heap_start__  = __bss_end__;      \/* Between bss and stack *\/\n__heap_end__    = __stack_start__;\n__ccm_start__   = ORIGIN(ccm);\n__ccm_size__    = LENGTH(ccm);\nend             = __heap_start__;\n\nSECTIONS\n{\n  . = 0;\n\n  .text : {\n    KEEP(*(.startup))         \/* Startup code *\/\n    *(.text*)                 \/* Program code *\/\n    KEEP(*(.rodata*))         \/* Read only data *\/\n    *(.glue_7)\n    *(.glue_7t)\n    *(.eh_frame)\n    . = ALIGN(4);\n    __ctors_start__ = .;\n    KEEP(*(.init_array))      \/* C++ constructors *\/\n    KEEP(*(.ctors))           \/* C++ constructors *\/\n    __ctors_end__ = .;\n    . = ALIGN(16);\n    __text_end__ = .;\n  } >flash\n\n  .data : ALIGN(16) {\n    __data_beg__ = .;         \/* Used in crt0.S *\/\n    *(.data*)                 \/* Initialized data *\/\n    __data_end__ = .;         \/* Used in crt0.S *\/\n  } >ram AT > flash\n\n  .bss (NOLOAD) : ALIGN(16) {\n    __bss_beg__ = .;          \/* Used in crt0.S *\/\n    *(.bss*)                  \/* Uninitialized data *\/\n    *(COMMON)                 \/* Common data *\/\n    __bss_end__ = .;          \/* Used in crt0.S *\/\n  } >ram\n\n  \/* C++ exception unwinding stuff--needed by some toolchains *\/\n  .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash\n\n  __exidx_start = .;\n  .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash\n  __exidx_end = .;\n}\n\n\/* Firmware entry point *\/\n\nENTRY(_vectors)\n","old_contents":"\/* Linker script for STM32F407VG Cortex-M4 ARM MCU *\/\n\/* From http:\/\/tech.munts.com\/MCU\/Frameworks\/ARM\/stm32f4\/stm32f407vg.ld *\/\n\n\/* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp.\t\t*\/\n\/*\t\t\t\t\t\t\t\t\t\t*\/\n\/* Redistribution and use in source and binary forms, with or without\t\t*\/\n\/* modification, are permitted provided that the following conditions are met:\t*\/\n\/*\t\t\t\t\t\t\t\t\t\t*\/\n\/* * Redistributions of source code must retain the above copyright notice,\t*\/\n\/*   this list of conditions and the following disclaimer.\t\t\t*\/\n\/*\t\t\t\t\t\t\t\t\t\t*\/\n\/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\t*\/\n\/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\t*\/\n\/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\t*\/\n\/* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\t*\/\n\/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\t\t*\/\n\/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\t\t*\/\n\/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\t*\/\n\/* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\t*\/\n\/* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\t*\/\n\/* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\t*\/\n\/* POSSIBILITY OF SUCH DAMAGE.\t\t\t\t\t\t\t*\/\n\nMEMORY\n{\n  flash (rx)  : ORIGIN = 0x08000000, LENGTH = 1024K\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K\n  ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n__rom_start__\t= ORIGIN(flash);\n__rom_size__\t= LENGTH(flash);\n__ram_start__\t= ORIGIN(ram);\n__ram_size__\t= LENGTH(ram);\n__ram_end__\t= __ram_start__ + __ram_size__;\n__stack_end__\t= __ram_end__;\t\t\/* Top of RAM *\/\n__stack_size__\t= 16K;\n__stack_start__\t= __stack_end__ - __stack_size__;\n__heap_start__\t= __bss_end__;\t\t\/* Between bss and stack *\/\n__heap_end__\t= __stack_start__;\n__ccm_start__\t= ORIGIN(ccm);\n__ccm_size__\t= LENGTH(ccm);\nend             = __heap_start__;\n\nSECTIONS\n{\n  . = 0;\n\n  .text : {\n  KEEP(*(.startup))\t\t\t\/* Startup code *\/\n  *(.text*)\t\t\t\t\/* Program code *\/\n  KEEP(*(.rodata*))\t\t\t\/* Read only data *\/\n  *(.glue_7)\n  *(.glue_7t)\n  *(.eh_frame)\n  . = ALIGN(4);\n  __ctors_start__ = .;\n  KEEP(*(.init_array))\t\t\t\/* C++ constructors *\/\n  KEEP(*(.ctors))\t\t\t\/* C++ constructors *\/\n  __ctors_end__ = .;\n  . = ALIGN(16);\n  __text_end__ = .;\n  } >flash\n\n  .data : ALIGN(16) {\n  __data_beg__ = .;\t\t\t\/* Used in crt0.S *\/\n  *(.data*)\t\t\t\t\/* Initialized data *\/\n  __data_end__ = .;\t\t\t\/* Used in crt0.S *\/\n  } >ram AT > flash\n\n  .bss (NOLOAD) : ALIGN(16) {\n  __bss_beg__ = .;\t\t\t\/* Used in crt0.S *\/\n  *(.bss*)\t\t\t\t\/* Uninitialized data *\/\n  *(COMMON)\t\t\t\t\/* Common data *\/\n  __bss_end__ = .;\t\t\t\/* Used in crt0.S *\/\n  } >ram\n\n\/* C++ exception unwinding stuff--needed by some toolchains *\/\n\n  .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash\n\n  __exidx_start = .;\n  .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash\n  __exidx_end = .;\n}\n\n\/* Firmware entry point *\/\n\nENTRY(_vectors)\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"cd15ffedfe9e513abb6167beab81cf418463fa51","subject":"[bsp][bluetrum] update link.lds","message":"[bsp][bluetrum] update link.lds\n","repos":"RT-Thread\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,armink\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread","old_file":"bsp\/bluetrum\/ab32vg1-ab-prougen\/link.lds","new_file":"bsp\/bluetrum\/ab32vg1-ab-prougen\/link.lds","new_contents":"\/* Define the flash max size *\/\n__max_flash_size = 1024k;\n\n__data_ram_size = 8k;\n__stack_ram_size = 4k;\n__comm_ram_size = 83k;\n__heap_ram_size = 29k;\n\n__base = 0x10000000;\n\n__data_vma = 0x11000;\n__stack_vma = __data_vma + __data_ram_size;\n__comm_vma = __stack_vma + __stack_ram_size;\n__heap_vma = __comm_vma + __comm_ram_size;\n\n__ram1_vma = 0x50000;\n\nMEMORY\n{\n    init            : org = __base,             len = 512\n    flash(rx)       : org = __base + 512,       len = __max_flash_size\n    comm(rx)        : org = __comm_vma,         len = __comm_ram_size\n\n    data            : org = __data_vma,         len = __data_ram_size\n    stack           : org = __stack_vma,        len = __stack_ram_size\n    heap            : org = __heap_vma,         len = __heap_ram_size\n    ram1(rx)        : org = __ram1_vma,         len = 0x7a00\n}\n\nSECTIONS\n{\n    .init : {\n        *(.reset)\n    } > init\n\n    .ram1 __ram1_vma : {\n        . = ALIGN(4);\n        \/* section information for initial *\/\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(4);\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n        *components*drivers**.o (.text*)\n        *components.o (.text*)\n        *idle.o (.text*)\n        *object.o (.text*)\n        *scheduler.o (.text*)\n    } > ram1 AT > flash\n\n    .comm __comm_vma : {\n        . = ALIGN(4);\n        KEEP(*(.vector))\n        EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *dfs*filesystems**.o  \n        *romfs.o *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o\n        *letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o\n        *trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o) *(.text)\n        *finsh*shell.o (.text*)\n        *(.text.unlikely)\n        *(.text.startup)\n        EXCLUDE_FILE (*components*libc**.o *dfs*filesystems**.o *romfs.o *lib_a**.o \n        *cp-demangle.o *divdf3.o *muldf3.o *multf3.o *unwind*.o *_clz.o) *(.rodata)\n        *(.rodata.name)\n        EXCLUDE_FILE(*lib_a**.o *cp-demangle.o *cp-demangle.o) *(.rodata.str1.4)\n        EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata)\n        *(.rela*)\n        *(.data*)\n        *(.sdata*)\n    } > comm AT > flash\n\n    .bss (NOLOAD):\n    {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.sbss)\n        *(.buf*)\n        __bss_end = .;\n    } > data\n    __bss_size = __bss_end - __bss_start;\n\n    .stack (NOLOAD) : {\n        __irq_stack_start = .;\n        . = __stack_ram_size;\n        __irq_stack = .;\n    } > stack\n    __irq_stack_size = __irq_stack - __irq_stack_start;\n\n    .heap (NOLOAD) : {\n        __heap_start = .;\n        . = __heap_ram_size;\n        __heap_end = .;\n    } > heap\n\n    .flash : {\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*)\n        . = ALIGN(512);\n    } > flash\n}\n\n\/* Calc the lma *\/\n__bank_size = SIZEOF(.flash);\n__comm_lma = LOADADDR(.comm);\n__comm_size = SIZEOF(.comm);\n__ram1_lma = LOADADDR(.ram1);\n__ram1_size = SIZEOF(.ram1);\n","old_contents":"\/* Define the flash max size *\/\n__max_flash_size = 1024k;\n\n__data_ram_size = 8k;\n__stack_ram_size = 4k;\n__comm_ram_size = 83k;\n__heap_ram_size = 29k;\n\n__base = 0x10000000;\n\n__data_vma = 0x11000;\n__stack_vma = __data_vma + __data_ram_size;\n__comm_vma = __stack_vma + __stack_ram_size;\n__heap_vma = __comm_vma + __comm_ram_size;\n\n__ram1_vma = 0x50000;\n\nMEMORY\n{\n    init            : org = __base,             len = 512\n    flash(rx)       : org = __base + 512,       len = __max_flash_size\n    comm(rx)        : org = __comm_vma,         len = __comm_ram_size\n\n    data            : org = __data_vma,         len = __data_ram_size\n    stack           : org = __stack_vma,        len = __stack_ram_size\n    heap            : org = __heap_vma,         len = __heap_ram_size\n    ram1(rx)        : org = __ram1_vma,         len = 0x7a00\n}\n\nSECTIONS\n{\n    .init : {\n        *(.reset)\n    } > init\n\n    .ram1 __ram1_vma : {\n        . = ALIGN(4);\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n        *components*drivers**.o (.text*)\n        *device.o (.text*)\n        *components.o (.text*)\n        *idle.o (.text*)\n    } > ram1 AT > flash\n\n    .rti : {\n        . = ALIGN(4);\n        \/* section information for initial *\/\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(32);\n    } > ram1 AT > flash\n\n    .comm : {\n        . = ALIGN(4);\n        KEEP(*(.vector))\n        EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *dfs*filesystems**.o  \n        *romfs.o *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o\n        *letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o\n        *trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o) *(.text)\n        *finsh*shell.o (.text*)\n        *(.text.unlikely)\n        *(.text.startup)\n        EXCLUDE_FILE (*components*libc**.o *dfs*filesystems**.o *romfs.o *lib_a**.o \n        *cp-demangle.o *divdf3.o *muldf3.o *multf3.o *unwind*.o *_clz.o) *(.rodata)\n        *(.rodata.name)\n        EXCLUDE_FILE(*lib_a**.o *cp-demangle.o *cp-demangle.o) *(.rodata.str1.4)\n        EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata)\n        *(.rela*)\n        *(.data*)\n        *(.sdata*)\n    } > comm AT > flash\n\n    .bss (NOLOAD):\n    {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.sbss)\n        *(.buf*)\n        __bss_end = .;\n    } > data\n    __bss_size = __bss_end - __bss_start;\n\n    .stack (NOLOAD) : {\n        __irq_stack_start = .;\n        . = __stack_ram_size;\n        __irq_stack = .;\n    } > stack\n    __irq_stack_size = __irq_stack - __irq_stack_start;\n\n    .heap (NOLOAD) : {\n        __heap_start = .;\n        . = __heap_ram_size;\n        __heap_end = .;\n    } > heap\n\n    .flash : {\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*)\n        . = ALIGN(512);\n    } > flash\n}\n\n\/* Calc the lma *\/\n__bank_size = SIZEOF(.flash);\n__comm_lma = LOADADDR(.comm);\n__comm_size = SIZEOF(.comm);\n__ram1_lma = LOADADDR(.ram1);\n__ram1_size = SIZEOF(.ram1) + SIZEOF(.rti);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ea08aa0250ef25756c8155ab54cb26b5afc1c913","subject":"indented startup.ld","message":"indented startup.ld\n","repos":"matildah\/octocabbit","old_file":"scheduler\/startup.ld","new_file":"scheduler\/startup.ld","new_contents":"ENTRY(_Reset)\nSECTIONS\n{\n    . = 0x10000;\n    .startup : { startup.o(.text) }\n    .text : { *(.text) }\n    .data : { *(.data) }\n    .bss : { *(.bss COMMON) }\n    . = ALIGN(8);\n    . = . + 0x1000; \/* 4kB of stack memory *\/\n    stack_top = .;\n}\n","old_contents":"ENTRY(_Reset)\nSECTIONS\n{\n . = 0x10000;\n .startup : { startup.o(.text) }\n .text : { *(.text) }\n .data : { *(.data) }\n .bss : { *(.bss COMMON) }\n . = ALIGN(8);\n . = . + 0x1000; \/* 4kB of stack memory *\/\n stack_top = .;\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"30c3700a6dd9480188cd6a43236a8ebfa0bbcae5","subject":"userland: simplify linker script","message":"userland: simplify linker script\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _text);\n         \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n         \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n\n    \/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM\n\n    \/*\n     * __NOTE__: The following symbols are used only to hint to elf2tbf how much\n     * total memory to request from the OS.\n     *\/\n    .stack :\n    {\n        . += STACK_SIZE;\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM\n\n    .app_heap :\n    {\n        . += APP_HEAP_SIZE;\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM\n\n    .kernel_heap :\n    {\n        . += KERNEL_HEAP_SIZE;\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7207b646e25310a405084dfde3729382c9609d41","subject":"boards: opentitan: Update the SRAM layout","message":"boards: opentitan: Update the SRAM layout\n\nAs Tock for OT has gotten larger the SRAM allocated for apps has moved\nup in memory. Let's update the linker script to better match what Tock\nis allocating.\n\nSigned-off-by: Alistair Francis <52ecf00b70a50079ae8d5fa09b9af6904950b63c@wdc.com>\n","repos":"tock\/libtock-rs","old_file":"boards\/layout_opentitan.ld","new_file":"boards\/layout_opentitan.ld","new_contents":"\/* Layout for the RISC-V 32 boards, used by the examples in this repository. *\/\n\nMEMORY {\n  \/*\n   * The TBF header can change in size so use 0x40 combined with\n   * --protected-region-size with elf2tab to cover a header upto that\n   * size.\n   *\n   * Note that the SRAM address may need to be changed depending on\n   * the kernel binary, check for the actual address of APP_MEMORY!\n   *\/\n  FLASH (rx) : ORIGIN = 0x20030040, LENGTH = 32M\n  SRAM (rwx) : ORIGIN = 0x10002D00, LENGTH = 512K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 1K;\n\nINCLUDE layout_generic.ld\n","old_contents":"\/* Layout for the RISC-V 32 boards, used by the examples in this repository. *\/\n\nMEMORY {\n  \/*\n   * The TBF header can change in size so use 0x40 combined with\n   * --protected-region-size with elf2tab to cover a header upto that\n   * size.\n   *\n   * Note that the SRAM address may need to be changed depending on\n   * the kernel binary, check for the actual address of APP_MEMORY!\n   *\/\n  FLASH (rx) : ORIGIN = 0x20030040, LENGTH = 32M\n  SRAM (rwx) : ORIGIN = 0x10002800, LENGTH = 512K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 1K;\n\nINCLUDE layout_generic.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"635bdf4baae0795b143b63c9088e3a73dd6c9a1b","subject":"Sections updated","message":"Sections updated\n","repos":"ckdur\/mriscv_vivado_arty,ckdur\/mriscv_vivado_arty,ckdur\/mriscv_vivado_arty,onchipuis\/mriscv_vivado,onchipuis\/mriscv_vivado,onchipuis\/mriscv_vivado,onchipuis\/mriscv_vivado,ckdur\/mriscv_vivado_arty,onchipuis\/mriscv_vivado","old_file":"tests\/mriscv_fpga.ld","new_file":"tests\/mriscv_fpga.ld","new_contents":"\/*\n  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.\n\n  This library is free software; you can redistribute it and\/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*\/\n\n\/* Linker script to configure memory regions.\n * Need modifying for a specific board.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00002000 \/*Put here if necesary bootloader start addressing*\/\n  RAM (rwx) : ORIGIN = 0x00010000, LENGTH = 0x00001000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t\/** TODO: maybe this is necesary if there is a section called by this.*\/\n\t\/*.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;*\/\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/*\n  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.\n\n  This library is free software; you can redistribute it and\/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*\/\n\n\/* Linker script to configure memory regions.\n * Need modifying for a specific board.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x01000000 \/*Put here if necesary bootloader start addressing*\/\n  RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 0x80000000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t\/** TODO: maybe this is necesary if there is a section called by this.*\/\n\t\/*.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;*\/\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"29ef108002772ec2807fa8ac24b91b36fa04d37f","subject":"ld script fix","message":"ld script fix\n","repos":"okertanov\/VelaOS,okertanov\/VelaOS,okertanov\/VelaOS,okertanov\/VelaOS,okertanov\/VelaOS","old_file":"src\/pal\/Bare-x86\/boot\/kernel.ld","new_file":"src\/pal\/Bare-x86\/boot\/kernel.ld","new_contents":"\/**\n    @copyright  Copyright (C) 2011 Oleg Kertanov <okertanov@gmail.com>\n    @license    BSD\n*\/\n\n\/*OUTPUT_FORMAT(\"elf32-i386\")*\/\n\nENTRY (start)\n\nSECTIONS\n{\n    . = 0x00100000;\n\n    __image_start__ = . ;\n\n    .text ALIGN (0x1000) :\n    {\n        __text_start__ = . ;\n        *(.text)\n        __text_end__ = . ;\n    }\n\n    __xen_guest ALIGN (0x1000) :\n    {\n        __xen_guest_start__ = . ;\n        *(__xen_guest)\n        __xen_guest_end__ = . ;\n    }\n\n    . = 0x00104000;\n\n    .xen_shared_info ALIGN (0x4000) :\n    {\n        __xen_shared_info_start__ = . ;\n        *(.xen_shared_info)\n        __xen_shared_info_end__ = . ;\n    }\n\n    . = 0x00108000;\n\n    .xen_hypercall_page ALIGN (0x4000) :\n    {\n        __xen_hypercall_page_start__ = . ;\n        *(.xen_hypercall_page)\n        __xen_hypercall_page_end__ = . ;\n    }\n\n    .rodata ALIGN (0x1000) :\n    {\n        __rodata_start__ = . ;\n        *(.rodata)\n        *(.rdata)\n         __rodata_end__ = . ;\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        __data_start__ = . ;\n        *(.data)\n        __data_end__ = . ;\n    }\n\n    .note ALIGN (0x1000) :\n    {\n        __note_start__ = . ;\n        *(.note.*)\n        __note_end__ = . ;\n    }\n\n    .bss ALIGN (0x1000) :\n    {\n        __bss_start__ = . ;\n        *(COMMON)\n        *(.bss)\n        __bss_end__ = . ;\n    }\n\n    .end ALIGN (0x1000) :\n    {\n        __image_end__ = . ;\n    }\n}\n\n","old_contents":"\/**\n    @copyright  Copyright (C) 2011 Oleg Kertanov <okertanov@gmail.com>\n    @license    BSD\n*\/\n\n\/*OUTPUT_FORMAT(\"elf32-i386\")*\/\n\nENTRY (start)\n\nSECTIONS\n{\n    . = 0x00100000;\n\n    __image_start__ = . ;\n\n    .text 0x00100000 ALIGN (0x1000) :\n    {\n        __text_start__ = . ;\n        *(.text)\n        __text_end__ = . ;\n    }\n\n    __xen_guest ALIGN (0x1000) :\n    {\n        __xen_guest_start__ = . ;\n        *(__xen_guest)\n        __xen_guest_end__ = . ;\n    }\n\n    .xen_shared_info 0x00104000 ALIGN (0x4000) :\n    {\n        __xen_shared_info_start__ = . ;\n        *(.xen_shared_info)\n        __xen_shared_info_end__ = . ;\n    }\n\n    .xen_hypercall_page 0x00108000 ALIGN (0x4000) :\n    {\n        __xen_hypercall_page_start__ = . ;\n        *(.xen_hypercall_page)\n        __xen_hypercall_page_end__ = . ;\n    }\n\n    .rodata ALIGN (0x1000) :\n    {\n        __rodata_start__ = . ;\n        *(.rodata)\n        *(.rdata)\n         __rodata_end__ = . ;\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        __data_start__ = . ;\n        *(.data)\n        __data_end__ = . ;\n    }\n\n    .note ALIGN (0x1000) :\n    {\n        __note_start__ = . ;\n        *(.note.*)\n        __note_end__ = . ;\n    }\n\n    .bss ALIGN (0x1000) :\n    {\n        __bss_start__ = . ;\n        *(COMMON)\n        *(.bss)\n        __bss_end__ = . ;\n    }\n\n    .end ALIGN (0x1000) :\n    {\n        __image_end__ = . ;\n    }\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"988269a1b08dbe7b2660a227b1899927296dba95","subject":"x86: implement new linker variables","message":"x86: implement new linker variables\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"zephyrproject-rtos\/zephyr,rsalveti\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,kraj\/zephyr,galak\/zephyr,fbsder\/zephyr,kraj\/zephyr,fbsder\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3220,zephyriot\/zephyr,ldts\/zephyr,galak\/zephyr,explora26\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,punitvara\/zephyr,explora26\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,ldts\/zephyr,nashif\/zephyr,runchip\/zephyr-cc3220,aceofall\/zephyr-iotos,aceofall\/zephyr-iotos,mbolivar\/zephyr,galak\/zephyr,explora26\/zephyr,galak\/zephyr,runchip\/zephyr-cc3220,rsalveti\/zephyr,kraj\/zephyr,mbolivar\/zephyr,kraj\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,explora26\/zephyr,ldts\/zephyr,fbsder\/zephyr,rsalveti\/zephyr,GiulianoFranchetto\/zephyr,rsalveti\/zephyr,nashif\/zephyr,punitvara\/zephyr,aceofall\/zephyr-iotos,Vudentz\/zephyr,rsalveti\/zephyr,aceofall\/zephyr-iotos,fbsder\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,fbsder\/zephyr,mbolivar\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,runchip\/zephyr-cc3220,nashif\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,nashif\/zephyr,kraj\/zephyr,mbolivar\/zephyr,zephyriot\/zephyr,ldts\/zephyr,aceofall\/zephyr-iotos,explora26\/zephyr,ldts\/zephyr,runchip\/zephyr-cc3220,zephyriot\/zephyr,zephyriot\/zephyr,finikorg\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/x86\/linker.ld","new_file":"include\/arch\/x86\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\n\t\/* This align directive needs to be after __data_rom_start or XIP\n\t * won't be copying the data from the right LMA\n\t *\/\n\tMMU_PAGE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t_image_ram_start = .;\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t\tMMU_PAGE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_X86_STACK_PROTECTION\n#define GDT_NUM_ENTRIES\t5\n#else \/* CONFIG_X86_STACK_PROTECTION *\/\n#define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_STACK_PROTECTION *\/\n\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_MMU\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n#endif\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\t\/* All stacks go in kernel's noinit, regardless of where they\n\t * were defined.\n\t *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\n\t\/* This align directive needs to be after __data_rom_start or XIP\n\t * won't be copying the data from the right LMA\n\t *\/\n\tMMU_PAGE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t_image_ram_start = .;\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t\tMMU_PAGE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_X86_STACK_PROTECTION\n#define GDT_NUM_ENTRIES\t5\n#else \/* CONFIG_X86_STACK_PROTECTION *\/\n#define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_STACK_PROTECTION *\/\n\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_MMU\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n#endif\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\t\/* All stacks go in kernel's noinit, regardless of where they\n\t * were defined.\n\t *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t\/* Define linker symbols *\/\n\t__kernel_ram_end = .;\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e73d9b979b84c09f6f227a5c7cae28036394da57","subject":"userland_generic.ld: Include .sdata in the data section","message":"userland_generic.ld: Include .sdata in the data section\n\nIf an ELF has a .sdata section it won't be copied to the TBF file. To\nensure that it makes it in let's include it in the data section.\n\nSigned-off-by: Alistair Francis <52ecf00b70a50079ae8d5fa09b9af6904950b63c@wdc.com>\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n\t\/* Include the \"small data\" in the data section. Otherwise it will be\n\t * dropped when the TBF is created.\n\t *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"0b0505ea1a53afff40029b13541a7519207c7668","subject":"everyone gets a stack","message":"everyone gets a stack\n","repos":"matildah\/octocabbit","old_file":"src\/kernel.lds","new_file":"src\/kernel.lds","new_contents":"KERNEL_BASE   = 0xf0000000; \/* virtual address *\/\nPHYS_BASE     = 0x80000000; \/* physical address *\/\nKERNEL_OFFSET = KERNEL_BASE - PHYS_BASE;\n\nENTRY(asm_entry)\nSECTIONS\n{\n    . = PHYS_BASE;\n\n    .boot . :\n    {\n        *(.boot.text)\n        *(.boot.rodata)\n        *(.boot.data)\n        . = . + 4K;\n        . = ALIGN(8);\n        _boot_stack = .;\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        . = ALIGN(64K);\n        *(.vectors)\n        *(.vectors.text)\n        *(.text)\n    }\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n        . = ALIGN(8);\n        . = . + 0x1000;\n        svc_stack = .;\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n        *(.bss.aligned)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n        *(.ARM.attributes)\n    }\n\n}\n","old_contents":"KERNEL_BASE   = 0xf0000000; \/* virtual address *\/\nPHYS_BASE     = 0x80000000; \/* physical address *\/\nKERNEL_OFFSET = KERNEL_BASE - PHYS_BASE;\n\nENTRY(asm_entry)\nSECTIONS\n{\n    . = PHYS_BASE;\n\n    .boot . :\n    {\n        *(.boot.text)\n        *(.boot.rodata)\n        *(.boot.data)\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        . = ALIGN(64K);\n        *(.vectors)\n        *(.vectors.text)\n        *(.text)\n    }\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n        . = ALIGN(8);\n        . = . + 0x1000;\n        svc_stack = .;\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n        *(.bss.aligned)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n        *(.ARM.attributes)\n    }\n\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"68abceef1051b254964995c6acabaac95cec9c35","subject":"m68k: Put .bss at the end of the data section","message":"m68k: Put .bss at the end of the data section\n\nPut .bss at the end of the data section\n\nSigned-off-by: Roman Zippel <f9f6ad990b4a8c1974dc6544787c1cc3570b6f00@linux-m68k.org>\nSigned-off-by: Geert Uytterhoeven <0da414d9d963da4039c2a0525b1844228075aa58@linux-m68k.org>\nSigned-off-by: Linus Torvalds <69652caca27c8b940640ad396ab71f93cacec34f@linux-foundation.org>\n","repos":"TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs","old_file":"arch\/m68k\/kernel\/vmlinux-std.lds","new_file":"arch\/m68k\/kernel\/vmlinux-std.lds","new_contents":"\/* ld script to make m68k Linux kernel *\/\n\n#include <asm-generic\/vmlinux.lds.h>\n#include <asm\/page.h>\n\nOUTPUT_FORMAT(\"elf32-m68k\", \"elf32-m68k\", \"elf32-m68k\")\nOUTPUT_ARCH(m68k)\nENTRY(_start)\njiffies = jiffies_64 + 4;\nSECTIONS\n{\n  . = 0x1000;\n  _text = .;\t\t\t\/* Text and read-only data *\/\n  .text : {\n\t*(.text.head)\n\tTEXT_TEXT\n\tSCHED_TEXT\n\tLOCK_TEXT\n\t*(.fixup)\n\t*(.gnu.warning)\n\t} :text = 0x4e75\n\n  _etext = .;\t\t\t\/* End of text section *\/\n\n  . = ALIGN(16);\t\t\/* Exception table *\/\n  __start___ex_table = .;\n  __ex_table : { *(__ex_table) }\n  __stop___ex_table = .;\n\n  RODATA\n\n  .data : {\t\t\t\/* Data *\/\n\tDATA_DATA\n\tCONSTRUCTORS\n\t}\n\n  . = ALIGN(16);\n  .data.cacheline_aligned : { *(.data.cacheline_aligned) }\n\n  .bss : { *(.bss) }\t\t\/* BSS *\/\n\n  _edata = .;\t\t\t\/* End of data section *\/\n\n  \/* will be freed after init *\/\n  . = ALIGN(PAGE_SIZE);\t\t\/* Init code and data *\/\n  __init_begin = .;\n  .init.text : {\n\t_sinittext = .;\n\tINIT_TEXT\n\t_einittext = .;\n  } :data\n  .init.data : { INIT_DATA }\n  . = ALIGN(16);\n  __setup_start = .;\n  .init.setup : { *(.init.setup) }\n  __setup_end = .;\n  __initcall_start = .;\n  .initcall.init : {\n\tINITCALLS\n  }\n  __initcall_end = .;\n  __con_initcall_start = .;\n  .con_initcall.init : { *(.con_initcall.init) }\n  __con_initcall_end = .;\n  .m68k_fixup : {\n\t__start_fixup = .;\n\t*(.m68k_fixup)\n\t__stop_fixup = .;\n  }\n  SECURITY_INIT\n#ifdef CONFIG_BLK_DEV_INITRD\n  . = ALIGN(8192);\n  __initramfs_start = .;\n  .init.ramfs : { *(.init.ramfs) }\n  __initramfs_end = .;\n#endif\n  . = ALIGN(8192);\n  __init_end = .;\n\n  .data.init_task : { *(.data.init_task) }\t\/* The initial task and kernel stack *\/\n\n  _end = . ;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ : {\n\tEXIT_TEXT\n\tEXIT_DATA\n\t*(.exitcall.exit)\n\t}\n\n  \/* Stabs debugging sections.  *\/\n  .stab 0 : { *(.stab) }\n  .stabstr 0 : { *(.stabstr) }\n  .stab.excl 0 : { *(.stab.excl) }\n  .stab.exclstr 0 : { *(.stab.exclstr) }\n  .stab.index 0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment 0 : { *(.comment) }\n}\n","old_contents":"\/* ld script to make m68k Linux kernel *\/\n\n#include <asm-generic\/vmlinux.lds.h>\n#include <asm\/page.h>\n\nOUTPUT_FORMAT(\"elf32-m68k\", \"elf32-m68k\", \"elf32-m68k\")\nOUTPUT_ARCH(m68k)\nENTRY(_start)\njiffies = jiffies_64 + 4;\nSECTIONS\n{\n  . = 0x1000;\n  _text = .;\t\t\t\/* Text and read-only data *\/\n  .text : {\n\t*(.text.head)\n\tTEXT_TEXT\n\tSCHED_TEXT\n\tLOCK_TEXT\n\t*(.fixup)\n\t*(.gnu.warning)\n\t} :text = 0x4e75\n\n  _etext = .;\t\t\t\/* End of text section *\/\n\n  . = ALIGN(16);\t\t\/* Exception table *\/\n  __start___ex_table = .;\n  __ex_table : { *(__ex_table) }\n  __stop___ex_table = .;\n\n  RODATA\n\n  .data : {\t\t\t\/* Data *\/\n\tDATA_DATA\n\tCONSTRUCTORS\n\t}\n\n  .bss : { *(.bss) }\t\t\/* BSS *\/\n\n  . = ALIGN(16);\n  .data.cacheline_aligned : { *(.data.cacheline_aligned) } :data\n\n  _edata = .;\t\t\t\/* End of data section *\/\n\n  \/* will be freed after init *\/\n  . = ALIGN(PAGE_SIZE);\t\t\/* Init code and data *\/\n  __init_begin = .;\n  .init.text : {\n\t_sinittext = .;\n\tINIT_TEXT\n\t_einittext = .;\n  }\n  .init.data : { INIT_DATA }\n  . = ALIGN(16);\n  __setup_start = .;\n  .init.setup : { *(.init.setup) }\n  __setup_end = .;\n  __initcall_start = .;\n  .initcall.init : {\n\tINITCALLS\n  }\n  __initcall_end = .;\n  __con_initcall_start = .;\n  .con_initcall.init : { *(.con_initcall.init) }\n  __con_initcall_end = .;\n  .m68k_fixup : {\n\t__start_fixup = .;\n\t*(.m68k_fixup)\n\t__stop_fixup = .;\n  }\n  SECURITY_INIT\n#ifdef CONFIG_BLK_DEV_INITRD\n  . = ALIGN(8192);\n  __initramfs_start = .;\n  .init.ramfs : { *(.init.ramfs) }\n  __initramfs_end = .;\n#endif\n  . = ALIGN(8192);\n  __init_end = .;\n\n  .data.init_task : { *(.data.init_task) }\t\/* The initial task and kernel stack *\/\n\n  _end = . ;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ : {\n\tEXIT_TEXT\n\tEXIT_DATA\n\t*(.exitcall.exit)\n\t}\n\n  \/* Stabs debugging sections.  *\/\n  .stab 0 : { *(.stab) }\n  .stabstr 0 : { *(.stabstr) }\n  .stab.excl 0 : { *(.stab.excl) }\n  .stab.exclstr 0 : { *(.stab.exclstr) }\n  .stab.index 0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment 0 : { *(.comment) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"eaa475f085ac9d05d4a3243980931a527da60932","subject":"Align heap base on an 8-byte offset.","message":"Align heap base on an 8-byte offset.\n\nThe MCU linker scripts were only imposing 4-byte alignment on the heap\nbase, rather than 8-byte alignment.  This caused `malloc()` to return\npointers that were not 8-byte aligned.  This is problematic if the\npointer were subsequently used to access data that requires 8-byte\nalignment (e.g., a `double`).\n\nFrom n1570 (c11 draft), 7.22.3 (Memory management functions):\n\n    The pointer returned if the allocation succeeds is suitably aligned\n    so that it may be assigned to a pointer to any type of object with a\n    fundamental alignment requirement\n\nBy locating the heap base at an offset of 8, we ensure `_sbrk()` only\nreturns 8-byte aligned memory blocks.\n\n`malloc()` itself already imposes a greater restriction on itself: it\nonly allocates blocks whose size is a multiple of 16.  So, as long as\n`_sbrk()` gives malloc properly aligned blocks, `malloc()` will return\nproperly aligned pointers to the application.\n","repos":"runtimeinc\/mynewt_arduino_zero,runtimeinc\/mynewt_arduino_zero,runtimeinc\/mynewt_arduino_zero","old_file":"hw\/mcu\/atmel\/samd21xx\/samd21xx.ld","new_file":"hw\/mcu\/atmel\/samd21xx\/samd21xx.ld","new_contents":"\/**\r\n * \\file\r\n *\r\n * \\brief Linker script for running in internal FLASH on the SAMD21G18A\r\n *\r\n * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.\r\n *\r\n * \\asf_license_start\r\n *\r\n * \\page License\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * 1. Redistributions of source code must retain the above copyright notice,\r\n *    this list of conditions and the following disclaimer.\r\n *\r\n * 2. Redistributions in binary form must reproduce the above copyright notice,\r\n *    this list of conditions and the following disclaimer in the documentation\r\n *    and\/or other materials provided with the distribution.\r\n *\r\n * 3. The name of Atmel may not be used to endorse or promote products derived\r\n *    from this software without specific prior written permission.\r\n *\r\n * 4. This software may only be redistributed and used in connection with an\r\n *    Atmel microcontroller product.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\r\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n * POSSIBILITY OF SUCH DAMAGE.\r\n *\r\n * \\asf_license_stop\r\n *\r\n *\/\r\n\r\n\r\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nSEARCH_DIR(.)\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x200; \/* required amount of stack *\/\r\n\r\n\/* The stack size used by the application. NOTE: you need to adjust according to your application. *\/\r\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;\r\n\r\nENTRY(Reset_Handler)\r\n\r\n\/* Section Definitions *\/\r\nSECTIONS\r\n{\r\n\r\n    .imghdr (NOLOAD):\r\n    {\r\n        . = . + _imghdr_size;\r\n    } > FLASH\r\n\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        _sfixed = .;\r\n        __isr_vector_start = .;\r\n        KEEP(*(.vectors .vectors.*))\r\n        __isr_vector_end = .;\r\n\r\n        *(.text .text.* .gnu.linkonce.t.*)\r\n        *(.glue_7t) *(.glue_7)\r\n        *(.rodata .rodata* .gnu.linkonce.r.*)\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\r\n        \/* Support C constructors, and C destructors in both user code\r\n           and the C library. This also provides support for C++ code. *\/\r\n        . = ALIGN(4);\r\n        KEEP(*(.init))\r\n        . = ALIGN(4);\r\n        __preinit_array_start = .;\r\n        KEEP (*(.preinit_array))\r\n        __preinit_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        __init_array_start = .;\r\n        KEEP (*(SORT(.init_array.*)))\r\n        KEEP (*(.init_array))\r\n        __init_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        KEEP (*crtbegin.o(.ctors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n        KEEP (*(SORT(.ctors.*)))\r\n        KEEP (*crtend.o(.ctors))\r\n\r\n        . = ALIGN(4);\r\n        KEEP(*(.fini))\r\n\r\n        . = ALIGN(4);\r\n        __fini_array_start = .;\r\n        KEEP (*(.fini_array))\r\n        KEEP (*(SORT(.fini_array.*)))\r\n        __fini_array_end = .;\r\n\r\n        KEEP (*crtbegin.o(.dtors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n        KEEP (*(SORT(.dtors.*)))\r\n        KEEP (*crtend.o(.dtors))\r\n\r\n        . = ALIGN(4);\r\n        _efixed = .;            \/* End of text section *\/\r\n    } > FLASH\r\n\r\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n    PROVIDE_HIDDEN (__exidx_start = .);\r\n    .ARM.exidx :\r\n    {\r\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n    PROVIDE_HIDDEN (__exidx_end = .);\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n\r\n    .vector_relocation :\r\n    {\r\n        . = ALIGN(4);\r\n        __vector_tbl_reloc__ = .;\r\n        . = . + (__isr_vector_end - __isr_vector_start);\r\n        . = ALIGN(4);\r\n    } > RAM\r\n\r\n    .relocate :\r\n    {\r\n        . = ALIGN(4);\r\n        _srelocate = .;\r\n        *(.data .data.*);\r\n        . = ALIGN(4);\r\n        _erelocate = .;\r\n    } > RAM AT > FLASH\r\n\r\n    \/* .bss section which is used for uninitialized data *\/\r\n    .bss (NOLOAD) :\r\n    {\r\n        . = ALIGN(4);\r\n\t__bss_start__ = . ;\r\n        _sbss = . ;\r\n        _szero = .;\r\n        *(.bss .bss.*)\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n\t__bss_end__ = . ;\r\n        _ebss = . ;\r\n        _ezero = .;\r\n    } > RAM\r\n\r\n    \/* Heap starts after BSS *\/\r\n    . = ALIGN(8);    \r\n    __HeapBase = .;\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  .heap :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( _user_heap_start = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = ALIGN(4);\r\n  } > RAM\r\n\r\n\r\n    \/* .stack_dummy section doesn't contains any symbols. It is only\r\n     * used for linker to calculate size of stack sections, and assign\r\n     * values to stack symbols later *\/\r\n    .stack_dummy (COPY):\r\n    {\r\n        . = . + STACK_SIZE;\r\n        *(.stack*)\r\n    } > RAM\r\n\r\n    _ram_start = ORIGIN(RAM);\r\n\r\n    \/* Set stack top to end of RAM, and stack limit move down by\r\n     * size of stack_dummy section *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n    PROVIDE(__stack = __StackTop);\r\n\r\n    \/* Top of head is the bottom of the stack *\/\r\n  _user_heap_end = __StackLimit;\r\n  __HeapLimit = __StackLimit;\r\n\r\n\r\n    \/* Check if data + heap + stack exceeds RAM limit *\/\r\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","old_contents":"\/**\r\n * \\file\r\n *\r\n * \\brief Linker script for running in internal FLASH on the SAMD21G18A\r\n *\r\n * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.\r\n *\r\n * \\asf_license_start\r\n *\r\n * \\page License\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * 1. Redistributions of source code must retain the above copyright notice,\r\n *    this list of conditions and the following disclaimer.\r\n *\r\n * 2. Redistributions in binary form must reproduce the above copyright notice,\r\n *    this list of conditions and the following disclaimer in the documentation\r\n *    and\/or other materials provided with the distribution.\r\n *\r\n * 3. The name of Atmel may not be used to endorse or promote products derived\r\n *    from this software without specific prior written permission.\r\n *\r\n * 4. This software may only be redistributed and used in connection with an\r\n *    Atmel microcontroller product.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\r\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n * POSSIBILITY OF SUCH DAMAGE.\r\n *\r\n * \\asf_license_stop\r\n *\r\n *\/\r\n\r\n\r\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nSEARCH_DIR(.)\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x200; \/* required amount of stack *\/\r\n\r\n\/* The stack size used by the application. NOTE: you need to adjust according to your application. *\/\r\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;\r\n\r\nENTRY(Reset_Handler)\r\n\r\n\/* Section Definitions *\/\r\nSECTIONS\r\n{\r\n\r\n    .imghdr (NOLOAD):\r\n    {\r\n        . = . + _imghdr_size;\r\n    } > FLASH\r\n\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        _sfixed = .;\r\n        __isr_vector_start = .;\r\n        KEEP(*(.vectors .vectors.*))\r\n        __isr_vector_end = .;\r\n\r\n        *(.text .text.* .gnu.linkonce.t.*)\r\n        *(.glue_7t) *(.glue_7)\r\n        *(.rodata .rodata* .gnu.linkonce.r.*)\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\r\n        \/* Support C constructors, and C destructors in both user code\r\n           and the C library. This also provides support for C++ code. *\/\r\n        . = ALIGN(4);\r\n        KEEP(*(.init))\r\n        . = ALIGN(4);\r\n        __preinit_array_start = .;\r\n        KEEP (*(.preinit_array))\r\n        __preinit_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        __init_array_start = .;\r\n        KEEP (*(SORT(.init_array.*)))\r\n        KEEP (*(.init_array))\r\n        __init_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        KEEP (*crtbegin.o(.ctors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n        KEEP (*(SORT(.ctors.*)))\r\n        KEEP (*crtend.o(.ctors))\r\n\r\n        . = ALIGN(4);\r\n        KEEP(*(.fini))\r\n\r\n        . = ALIGN(4);\r\n        __fini_array_start = .;\r\n        KEEP (*(.fini_array))\r\n        KEEP (*(SORT(.fini_array.*)))\r\n        __fini_array_end = .;\r\n\r\n        KEEP (*crtbegin.o(.dtors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n        KEEP (*(SORT(.dtors.*)))\r\n        KEEP (*crtend.o(.dtors))\r\n\r\n        . = ALIGN(4);\r\n        _efixed = .;            \/* End of text section *\/\r\n    } > FLASH\r\n\r\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n    PROVIDE_HIDDEN (__exidx_start = .);\r\n    .ARM.exidx :\r\n    {\r\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n    PROVIDE_HIDDEN (__exidx_end = .);\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n\r\n    .vector_relocation :\r\n    {\r\n        . = ALIGN(4);\r\n        __vector_tbl_reloc__ = .;\r\n        . = . + (__isr_vector_end - __isr_vector_start);\r\n        . = ALIGN(4);\r\n    } > RAM\r\n\r\n    .relocate :\r\n    {\r\n        . = ALIGN(4);\r\n        _srelocate = .;\r\n        *(.data .data.*);\r\n        . = ALIGN(4);\r\n        _erelocate = .;\r\n    } > RAM AT > FLASH\r\n\r\n    \/* .bss section which is used for uninitialized data *\/\r\n    .bss (NOLOAD) :\r\n    {\r\n        . = ALIGN(4);\r\n\t__bss_start__ = . ;\r\n        _sbss = . ;\r\n        _szero = .;\r\n        *(.bss .bss.*)\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n\t__bss_end__ = . ;\r\n        _ebss = . ;\r\n        _ezero = .;\r\n    } > RAM\r\n\r\n    \/* Heap starts after BSS *\/\r\n    __HeapBase = .;\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  .heap :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( _user_heap_start = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = ALIGN(4);\r\n  } > RAM\r\n\r\n\r\n    \/* .stack_dummy section doesn't contains any symbols. It is only\r\n     * used for linker to calculate size of stack sections, and assign\r\n     * values to stack symbols later *\/\r\n    .stack_dummy (COPY):\r\n    {\r\n        . = . + STACK_SIZE;\r\n        *(.stack*)\r\n    } > RAM\r\n\r\n    _ram_start = ORIGIN(RAM);\r\n\r\n    \/* Set stack top to end of RAM, and stack limit move down by\r\n     * size of stack_dummy section *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n    PROVIDE(__stack = __StackTop);\r\n\r\n    \/* Top of head is the bottom of the stack *\/\r\n  _user_heap_end = __StackLimit;\r\n  __HeapLimit = __StackLimit;\r\n\r\n\r\n    \/* Check if data + heap + stack exceeds RAM limit *\/\r\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"131a5dfd626dbe181daace46400820f57b97d810","subject":"arch: arm: aarch32: fix section alignment behind rodata region start marker","message":"arch: arm: aarch32: fix section alignment behind rodata region start marker\n\nFix for issue 39978. This commit assigns the __rodata_region_start marker\nto the ROMABLE region prior to the inclusion of linker\/common-rom.ld,\nlinker\/thread-local-storage.ld and linker\/cplusplus-rom.ld. Prior to this\nfix, the __rodata_region_start marker was properly aligned and indicated\nthe expected memory location for the start of the rodata section and\nsimilar sections, but it was disconnected from the ROMABLE region into\nwhich the subsequent sections are being integrated, resulting in placement\nof those sections right behind the previous section in the ROMABLE region\nand therefore at addresses below the __rodata_region_start marker.\n\nFor the sake of consistent behaviour, the end marker of the text region\nhas been modified accordingly.\n\nSigned-off-by: Immo Birnbaum <9d53277017f7b972042afc81794f782b84cac388@weidmueller.com>\n","repos":"zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_a_r\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_a_r\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A and Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/devicetree_regions.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#elif defined(CONFIG_ARM_AARCH32_MMU)\n_region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n\/* If building without MPU\/MMU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\n#define BSS_ALIGN ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_ocm), rw)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n    __rom_region_start = ROM_ADDR;\n#else\n    __rom_region_start = RAM_ADDR;\n#endif\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        . = ALIGN(_region_min_align);\n        __text_region_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#include <linker\/kobject-text.ld>\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n        __text_region_end = .;\n        . = ALIGN(_region_min_align);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rodata_start,,)\n    {\n        . = ALIGN(_region_min_align);\n        __rodata_region_start = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n#include <linker\/cplusplus-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n\n        \/*\n         * RODATA must be the last section so that the size of the entire read\n         * only area will be filled to a power of 2.\n         *\/\n        MPU_ALIGN(ABSOLUTE(.) - __rom_region_start);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    __rodata_region_end = .;\n    __rom_region_end = .;\n    MPU_ALIGN(__rodata_region_end - __rom_region_start);\n    _image_rom_end_order = (LOG2CEIL(__rom_region_end) - 1) << 1;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_region_start = .;\n        __data_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n        __data_end = .;\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    . = ALIGN(_region_min_align);\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ocm), okay)\nGROUP_START(OCM)\n\n\tSECTION_PROLOGUE(_OCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__ocm_start = .;\n\t\t__ocm_bss_start = .;\n\t\t*(.ocm_bss)\n\t\t*(\".ocm_bss.*\")\n\t\t__ocm_bss_end = .;\n\t} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ocm)))\n\n\tSECTION_PROLOGUE(_OCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__ocm_data_start = .;\n\t\t*(.ocm_data)\n\t\t*(\".ocm_data.*\")\n\t\t__ocm_data_end = .;\n\t} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ocm)))\n\n  __ocm_end = .;\n  __ocm_size = __ocm_end - __ocm_start;\n\nGROUP_END(OCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A and Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/devicetree_regions.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#elif defined(CONFIG_ARM_AARCH32_MMU)\n_region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\n#define BSS_ALIGN ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_ocm), rw)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n    __rom_region_start = ROM_ADDR;\n#else\n    __rom_region_start = RAM_ADDR;\n#endif\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        . = ALIGN(_region_min_align);\n        __text_region_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#include <linker\/kobject-text.ld>\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n    . = ALIGN(_region_min_align);\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    . = ALIGN(_region_min_align);\n    __rodata_region_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n#include <linker\/cplusplus-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n\n        \/*\n         * RODATA must be the last section so that the size of the entire read\n         * only area will be filled to a power of 2.\n         *\/\n        MPU_ALIGN(ABSOLUTE(.) - __rom_region_start);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    __rodata_region_end = .;\n    __rom_region_end = .;\n    MPU_ALIGN(__rodata_region_end - __rom_region_start);\n    _image_rom_end_order = (LOG2CEIL(__rom_region_end) - 1) << 1;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_region_start = .;\n        __data_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n        __data_end = .;\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    . = ALIGN(_region_min_align);\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ocm), okay)\nGROUP_START(OCM)\n\n\tSECTION_PROLOGUE(_OCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__ocm_start = .;\n\t\t__ocm_bss_start = .;\n\t\t*(.ocm_bss)\n\t\t*(\".ocm_bss.*\")\n\t\t__ocm_bss_end = .;\n\t} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ocm)))\n\n\tSECTION_PROLOGUE(_OCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__ocm_data_start = .;\n\t\t*(.ocm_data)\n\t\t*(\".ocm_data.*\")\n\t\t__ocm_data_end = .;\n\t} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ocm)))\n\n  __ocm_end = .;\n  __ocm_size = __ocm_end - __ocm_start;\n\nGROUP_END(OCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6ba4488c7c635698f5d398982c4fa3da8fc24758","subject":"linker: more .rel for orphan sections","message":"linker: more .rel for orphan sections\n\nThere are sections defined in common-rom\/ram.ld where they are\nshowing up as orphan sections. So add these as known sections.\n\nFixes #10493\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"nashif\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,explora26\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,explora26\/zephyr,explora26\/zephyr,punitvara\/zephyr,ldts\/zephyr,ldts\/zephyr,explora26\/zephyr,galak\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,ldts\/zephyr,ldts\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr","old_file":"include\/linker\/rel-sections.ld","new_file":"include\/linker\/rel-sections.ld","new_contents":"\t\/*\n\t * .rel.* are for relocation.\n\t * These are being produced by compiler\/linker.\n\t * Specify these here so they are not considered orphan sections.\n\t *\n\t * Obtained via\n\t * '$(ARCH)-zephyr-elf-ld --verbose'\n\t *\/\n\n#if !defined(CONFIG_RISCV32) && !defined(CONFIG_XTENSA)\n\tSECTION_PROLOGUE(.rel.dyn,,)\n\t{\n\t*(.rel.init)\n\t*(.rel.text .rel.text.* .rel.text_start.* .rel.gnu.linkonce.t.*)\n\t*(.rel.fini)\n\t*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n\t*(.rel.data.rel.ro .rel.data.rel.ro.* .rel.gnu.linkonce.d.rel.ro.*)\n\t*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n\t*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n\t*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n\n#if defined(CONFIG_ARCH_POSIX)\n\t*(.rel.preinit_array)\n\t*(.rel.init_array)\n\t*(.rel.fini_array)\n#endif\n\n\t*(.rel.ctors)\n\t*(.rel.dtors)\n\t*(.rel.got)\n\t*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2)\n\tPROVIDE_HIDDEN (__rel_iplt_start = .);\n\t*(.rel.iplt)\n\tPROVIDE_HIDDEN (__rel_iplt_end = .);\n#endif\n\n\t\/* These are related to sections defined by Zephyr *\/\n\t*(.rel.kernel .rel.kernel.*)\n\t*(.rel.init_PRE_KERNEL*)\n\t*(.rel.init_POST_KERNEL*)\n\t*(.rel.init_APPLICATION*)\n\n#if defined(CONFIG_ARCH_POSIX)\n\t*(.rel.native_PRE_BOOT*)\n\t*(.rel.native_FIRST_SLEEP*)\n\t*(.rel.native_ON_EXIT*)\n#endif\n\n\t*(.rel.devconfig.*)\n\n\t*(.rel._k_*)\n\n\t*(.rel._bt_settings.*)\n\n\t*(.rel.log_*)\n\n\t*(.rel._net_buf_pool.*)\n\t*(.rel.net_*)\n\n\t*(.rel._static_thread_data.*)\n\n\t*(.rel.usb.*)\n\n#if defined(CONFIG_X86)\n\t*(.rel.ifunc)\n\t*(.rel.mmulist)\n\t*(.rel.tss)\n#endif\n\t}\n#endif \/* !defined(CONFIG_RISCV32) *\/\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32)\n\tSECTION_PROLOGUE(.rela.dyn,,)\n\t{\n\t*(.rela.init)\n\t*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n\t*(.rela.fini)\n\t*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n\t*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n\t*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n\t*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n\t*(.rela.ctors)\n\t*(.rela.dtors)\n\t*(.rela.got)\n\t*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2)\n\tPROVIDE_HIDDEN (__rela_iplt_start = .);\n\t*(.rela.iplt)\n\tPROVIDE_HIDDEN (__rela_iplt_end = .);\n#endif\n\n\t\/* These are related to sections defined by Zephyr *\/\n\t*(.rela.kernel .rel.kernel.*)\n\t*(.rela.init_PRE_KERNEL*)\n\t*(.rela.init_POST_KERNEL*)\n\t*(.rela.init_APPLICATION*)\n\n\t*(.rela.devconfig.*)\n\n\t*(.rela._k_*)\n\n\t*(.rela._bt_settings.*)\n\n\t*(.rela.log_*)\n\n\t*(.rela._net_buf_pool.*)\n\t*(.rela.net_*)\n\n\t*(.rela._static_thread_data.*)\n\n\t*(.rela.usb.*)\n\n#if defined(CONFIG_RISCV32)\n\t*(.rela.exception.*)\n\t*(.rela.gnu.linkonce.sw_isr_table)\n\t*(.rela.sdata.*)\n#endif\n\n\t}\n#endif\n\n#if !defined(CONFIG_RISCV32) && !defined(CONFIG_XTENSA)\n\tSECTION_PROLOGUE(.rel.plt,,)\n\t{\n\t*(.rel.plt)\n\n#if defined(CONFIG_X86)\n\tPROVIDE_HIDDEN (__rel_iplt_start = .);\n\t*(.rel.iplt)\n\tPROVIDE_HIDDEN (__rel_iplt_end = .);\n#endif\n\t}\n#endif \/* !defined(CONFIG_RISCV32) *\/\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32)\n\tSECTION_PROLOGUE(.rela.plt,,)\n\t{\n\t*(.rela.plt)\n\t}\n#endif\n","old_contents":"\t\/*\n\t * .rel.* are for relocation.\n\t * These are being produced by compiler\/linker.\n\t * Specify these here so they are not considered orphan sections.\n\t *\n\t * Obtained via\n\t * '$(ARCH)-zephyr-elf-ld --verbose'\n\t *\/\n\n#if !defined(CONFIG_RISCV32) && !defined(CONFIG_XTENSA)\n\tSECTION_PROLOGUE(.rel.dyn,,)\n\t{\n\t*(.rel.init)\n\t*(.rel.text .rel.text.* .rel.text_start.* .rel.gnu.linkonce.t.*)\n\t*(.rel.fini)\n\t*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n\t*(.rel.data.rel.ro .rel.data.rel.ro.* .rel.gnu.linkonce.d.rel.ro.*)\n\t*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n\t*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n\t*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n\n#if defined(CONFIG_ARCH_POSIX)\n\t*(.rel.preinit_array)\n\t*(.rel.init_array)\n\t*(.rel.fini_array)\n#endif\n\n\t*(.rel.ctors)\n\t*(.rel.dtors)\n\t*(.rel.got)\n\t*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2)\n\tPROVIDE_HIDDEN (__rel_iplt_start = .);\n\t*(.rel.iplt)\n\tPROVIDE_HIDDEN (__rel_iplt_end = .);\n#endif\n\n\t\/* These are related to sections defined by Zephyr *\/\n\t*(.rel.kernel .rel.kernel.*)\n\t*(.rel.init_PRE_KERNEL*)\n\t*(.rel.init_POST_KERNEL*)\n\t*(.rel.init_APPLICATION*)\n\n#if defined(CONFIG_ARCH_POSIX)\n\t*(.rel.native_PRE_BOOT*)\n\t*(.rel.native_FIRST_SLEEP*)\n\t*(.rel.native_ON_EXIT*)\n#endif\n\n\t*(.rel.devconfig.*)\n\t*(.rel._k_alert.*)\n\t*(.rel._k_mem_pool.*)\n\t*(.rel._k_timer.*)\n\t*(.rel._static_thread_data.*)\n\n#if defined(CONFIG_X86)\n\t*(.rel.ifunc)\n\t*(.rel.mmulist)\n\t*(.rel.tss)\n#endif\n\t}\n#endif \/* !defined(CONFIG_RISCV32) *\/\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32)\n\tSECTION_PROLOGUE(.rela.dyn,,)\n\t{\n\t*(.rela.init)\n\t*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n\t*(.rela.fini)\n\t*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n\t*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n\t*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n\t*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n\t*(.rela.ctors)\n\t*(.rela.dtors)\n\t*(.rela.got)\n\t*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2)\n\tPROVIDE_HIDDEN (__rela_iplt_start = .);\n\t*(.rela.iplt)\n\tPROVIDE_HIDDEN (__rela_iplt_end = .);\n#endif\n\n\t\/* These are related to sections defined by Zephyr *\/\n\t*(.rela.kernel .rel.kernel.*)\n\t*(.rela.init_PRE_KERNEL*)\n\t*(.rela.init_POST_KERNEL*)\n\t*(.rela.init_APPLICATION*)\n\t*(.rela._k_alert.*)\n\t*(.rela._k_mem_pool.*)\n\t*(.rela._k_timer.*)\n\t*(.rela._static_thread_data.*)\n\n#if defined(CONFIG_RISCV32)\n\t*(.rela.devconfig.*)\n\t*(.rela.exception.*)\n\t*(.rela.gnu.linkonce.sw_isr_table)\n\t*(.rela.sdata.*)\n#endif\n\n\t}\n#endif\n\n#if !defined(CONFIG_RISCV32) && !defined(CONFIG_XTENSA)\n\tSECTION_PROLOGUE(.rel.plt,,)\n\t{\n\t*(.rel.plt)\n\n#if defined(CONFIG_X86)\n\tPROVIDE_HIDDEN (__rel_iplt_start = .);\n\t*(.rel.iplt)\n\tPROVIDE_HIDDEN (__rel_iplt_end = .);\n#endif\n\t}\n#endif \/* !defined(CONFIG_RISCV32) *\/\n\n#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32)\n\tSECTION_PROLOGUE(.rela.plt,,)\n\t{\n\t*(.rela.plt)\n\t}\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"54a5a6eb5842d68fe0aaa60d50fdea532c19770b","subject":"[PATCH] m68k: fix reference to init_task in vmlinux-sun3.lds","message":"[PATCH] m68k: fix reference to init_task in vmlinux-sun3.lds\n\nit's *(.data.init_task), not init_task...\n\nSigned-off-by: Al Viro <de609eb4d5d70b1d38ec6642adbfc33a2781f63c@zeniv.linux.org.uk>\nCc: Roman Zippel <f9f6ad990b4a8c1974dc6544787c1cc3570b6f00@linux-m68k.org>\nSigned-off-by: Andrew Morton <5c1e68b099950c134891f0b6e179498a8ebe9cf9@osdl.org>\nSigned-off-by: Linus Torvalds <69652caca27c8b940640ad396ab71f93cacec34f@osdl.org>\n","repos":"TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas","old_file":"arch\/m68k\/kernel\/vmlinux-sun3.lds","new_file":"arch\/m68k\/kernel\/vmlinux-sun3.lds","new_contents":"\/* ld script to make m68k Linux kernel *\/\n\n#include <asm-generic\/vmlinux.lds.h>\n\nOUTPUT_FORMAT(\"elf32-m68k\", \"elf32-m68k\", \"elf32-m68k\")\nOUTPUT_ARCH(m68k)\nENTRY(_start)\njiffies = jiffies_64 + 4;\nSECTIONS\n{\n  . = 0xE004000;\n  _text = .;\t\t\t\/* Text and read-only data *\/\n  .text : {\n\t*(.head)\n\t*(.text)\n\tSCHED_TEXT\n\tLOCK_TEXT\n\t*(.fixup)\n\t*(.gnu.warning)\n\t} :text = 0x4e75\n\tRODATA\n\n  _etext = .;\t\t\t\/* End of text section *\/\n\n  .data : {\t\t\t\/* Data *\/\n\t*(.data)\n\tCONSTRUCTORS\n\t. = ALIGN(16);\t\t\/* Exception table *\/\n\t__start___ex_table = .;\n\t*(__ex_table)\n\t__stop___ex_table = .;\n\t} :data\n  \/* End of data goes *here* so that freeing init code works properly. *\/\n  _edata = .;\n\n  \/* will be freed after init *\/\n  . = ALIGN(8192);\t\/* Init code and data *\/\n__init_begin = .;\n\t.init.text : {\n\t\t_sinittext = .;\n\t\t*(.init.text)\n\t\t_einittext = .;\n\t}\n\t.init.data : { *(.init.data) }\n\t. = ALIGN(16);\n\t__setup_start = .;\n\t.init.setup : { *(.init.setup) }\n\t__setup_end = .;\n\t__initcall_start = .;\n\t.initcall.init : {\n\t\t*(.initcall1.init)\n\t\t*(.initcall2.init)\n\t\t*(.initcall3.init)\n\t\t*(.initcall4.init)\n\t\t*(.initcall5.init)\n\t\t*(.initcall6.init)\n\t\t*(.initcall7.init)\n\t}\n\t__initcall_end = .;\n\t__con_initcall_start = .;\n\t.con_initcall.init : { *(.con_initcall.init) }\n\t__con_initcall_end = .;\n\tSECURITY_INIT\n\t. = ALIGN(8192);\n\t__initramfs_start = .;\n\t.init.ramfs : { *(.init.ramfs) }\n\t__initramfs_end = .;\n\t. = ALIGN(8192);\n\t__init_end = .;\n\t.data.init.task : { *(.data.init_task) }\n\n\n  .bss : { *(.bss) }\t\t\/* BSS *\/\n\n  _end = . ;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ : {\n\t*(.exit.text)\n\t*(.exit.data)\n\t*(.exitcall.exit)\n\t}\n\n  .crap : {\n\t\/* Stabs debugging sections.  *\/\n\t*(.stab)\n\t*(.stabstr)\n\t*(.stab.excl)\n\t*(.stab.exclstr)\n\t*(.stab.index)\n\t*(.stab.indexstr)\n\t*(.comment)\n\t*(.note)\n  }\n\n}\n","old_contents":"\/* ld script to make m68k Linux kernel *\/\n\n#include <asm-generic\/vmlinux.lds.h>\n\nOUTPUT_FORMAT(\"elf32-m68k\", \"elf32-m68k\", \"elf32-m68k\")\nOUTPUT_ARCH(m68k)\nENTRY(_start)\njiffies = jiffies_64 + 4;\nSECTIONS\n{\n  . = 0xE004000;\n  _text = .;\t\t\t\/* Text and read-only data *\/\n  .text : {\n\t*(.head)\n\t*(.text)\n\tSCHED_TEXT\n\tLOCK_TEXT\n\t*(.fixup)\n\t*(.gnu.warning)\n\t} :text = 0x4e75\n\tRODATA\n\n  _etext = .;\t\t\t\/* End of text section *\/\n\n  .data : {\t\t\t\/* Data *\/\n\t*(.data)\n\tCONSTRUCTORS\n\t. = ALIGN(16);\t\t\/* Exception table *\/\n\t__start___ex_table = .;\n\t*(__ex_table)\n\t__stop___ex_table = .;\n\t} :data\n  \/* End of data goes *here* so that freeing init code works properly. *\/\n  _edata = .;\n\n  \/* will be freed after init *\/\n  . = ALIGN(8192);\t\/* Init code and data *\/\n__init_begin = .;\n\t.init.text : {\n\t\t_sinittext = .;\n\t\t*(.init.text)\n\t\t_einittext = .;\n\t}\n\t.init.data : { *(.init.data) }\n\t. = ALIGN(16);\n\t__setup_start = .;\n\t.init.setup : { *(.init.setup) }\n\t__setup_end = .;\n\t__initcall_start = .;\n\t.initcall.init : {\n\t\t*(.initcall1.init)\n\t\t*(.initcall2.init)\n\t\t*(.initcall3.init)\n\t\t*(.initcall4.init)\n\t\t*(.initcall5.init)\n\t\t*(.initcall6.init)\n\t\t*(.initcall7.init)\n\t}\n\t__initcall_end = .;\n\t__con_initcall_start = .;\n\t.con_initcall.init : { *(.con_initcall.init) }\n\t__con_initcall_end = .;\n\tSECURITY_INIT\n\t. = ALIGN(8192);\n\t__initramfs_start = .;\n\t.init.ramfs : { *(.init.ramfs) }\n\t__initramfs_end = .;\n\t. = ALIGN(8192);\n\t__init_end = .;\n\t.init.task : { *(init_task) }\n\n\n  .bss : { *(.bss) }\t\t\/* BSS *\/\n\n  _end = . ;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ : {\n\t*(.exit.text)\n\t*(.exit.data)\n\t*(.exitcall.exit)\n\t}\n\n  .crap : {\n\t\/* Stabs debugging sections.  *\/\n\t*(.stab)\n\t*(.stabstr)\n\t*(.stab.excl)\n\t*(.stab.exclstr)\n\t*(.stab.index)\n\t*(.stab.indexstr)\n\t*(.comment)\n\t*(.note)\n  }\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"93e31f91e1e65244e47b8304c3286db882f88962","subject":"[build] Make .rodata a separate section from .text (elf kernel)","message":"[build] Make .rodata a separate section from .text (elf kernel)\n","repos":"vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs","old_file":"kernel\/arch\/i386\/linker_script.ld","new_file":"kernel\/arch\/i386\/linker_script.ld","new_contents":"\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib32\");\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib\");\n\nkernel_base_va = 0xC0000000;\nkernel_paddr   = 0x00100000;\n\nSECTIONS\n{\n  . = SEGMENT_START(\"text-segment\", kernel_base_va + kernel_paddr);\n\n  .text : AT(kernel_paddr)\n  {\n    text = .;\n    *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    *(.text.exit .text.exit.*)\n    *(.text.startup .text.startup.*)\n    *(.text.hot .text.hot.*)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    . = ALIGN(4);\n  }\n\n   .rodata : AT(kernel_paddr + (rodata - text))\n   {\n      rodata = .;\n      *(.rodata .rodata.* .gnu.linkonce.r.*)\n      . = ALIGN(4096);\n   }\n\n  .data : AT(kernel_paddr + (data - text))\n  {\n    data = .;\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN(4096);\n  }\n\n  .bss : AT(kernel_paddr + (bss - text))\n  {\n    bss = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n  }\n\n  . = ALIGN(4);\n  _end = .;\n\n  \/DISCARD\/ : { *(.eh_frame*) }\n\n}\n\n\n","old_contents":"\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib32\");\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib\");\n\nkernel_base_va = 0xC0000000;\nkernel_paddr   = 0x00100000;\n\nSECTIONS\n{\n  . = SEGMENT_START(\"text-segment\", kernel_base_va + kernel_paddr);\n\n  .text : AT(kernel_paddr)\n  {\n    code = .;\n    *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    *(.text.exit .text.exit.*)\n    *(.text.startup .text.startup.*)\n    *(.text.hot .text.hot.*)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    . = ALIGN(4096);\n  }\n\n  .data : AT(kernel_paddr + (data - code))\n  {\n    data = .;\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN(4096);\n  }\n\n  .bss : AT(kernel_paddr + (bss - code))\n  {\n    bss = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n  }\n\n  . = ALIGN(4);\n  _end = .;\n\n  \/DISCARD\/ : { *(.eh_frame*) }\n\n}\n\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"d3967ac3ecb460b7e5df3869a38ef1695a8d893c","subject":"Tidying up","message":"Tidying up\n","repos":"stelfer\/nubbin,stelfer\/nubbin","old_file":"kernel\/asm\/os-image.elf_x86_64.ld","new_file":"kernel\/asm\/os-image.elf_x86_64.ld","new_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nboot_paddr   \t   = 0x007c00;\t\t\/* boot offset *\/\nkernel_paddr       = 0x100000;\nkernel_vaddr_off   = 0xffffffff00000000;\nkernel_vaddr \t   = kernel_vaddr_off + kernel_paddr;\nkernel_pos   \t   = 0x001000;\t\t\/* physical position in output *\/\npage_table_paddr   = 0x00200000;\nkernel_stack_paddr = 0x005fffff;\nkernel_size \t   = SIZEOF(.kernel);\nuser_vaddr \t   = 0x100000;\n\nSECTIONS\n{\n\t.boot-setup boot_paddr :\n\t{\n\t\t*(.boot)\n\t\t_setup_paddr = .;\n\t\t*(.setup)\n\t}\n\n\t.kernel kernel_vaddr : AT(boot_paddr + kernel_pos)\n\t{\n\t\t*.ko(.text)\n\t\t*.ko(.data*)\n\t\t*.ko(.rodata*)\n\t\t*.ko(COMMON*)\n\t\t*.ko(.bss*)\n\t}\n\n\t.user user_vaddr + SIZEOF(.kernel): AT(LOADADDR(.kernel) + SIZEOF(.kernel))\n\t{\n\t\t*.o(.text)\n\t\t*.o(.data*)\n\t\t*.o(.rodata*)\n\t\t*.o(COMMON*)\n\t\t*.o(.bss*)\n\t}\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.eh_frame)\n\t\t*(.comment)\n\t}\n}\n","old_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nboot_paddr   = 0x007c00;\t\t\/* boot offset *\/\nkernel_paddr = 0x100000;\nkernel_vaddr = 0xffffffff00100000;\n\nkernel_pos   = 0x001000;\t\t\/* physical position in output *\/\n\/* kernel_off   = - kernel_vaddr + kernel_pos + boot_paddr; *\/\n\npage_table_paddr   = 0x00200000;\nkernel_stack_paddr = 0x005fffff;\nkernel_size = SIZEOF(.kernel);\n\nuser_vaddr = 0x100000;\n\nSECTIONS\n{\n\t.boot-setup boot_paddr :\n\t{\n\t\t*(.boot)\n\t\t_setup_paddr = .;\n\t\t*(.setup)\n\t}\n\n\t.kernel kernel_vaddr : AT(boot_paddr + kernel_pos)\n\t{\n\t\t*.ko(.text)\n\t\t*.ko(.data*)\n\t\t*.ko(.rodata*)\n\t\t*.ko(COMMON*)\n\t\t*.ko(.bss*)\n\t}\n\n\t.user user_vaddr + SIZEOF(.kernel): AT(LOADADDR(.kernel) + SIZEOF(.kernel))\n\t{\n\t\t*.o(.text)\n\t\t*.o(.data*)\n\t\t*.o(.rodata*)\n\t\t*.o(COMMON*)\n\t\t*.o(.bss*)\n\t}\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.eh_frame)\n\t\t*(.comment)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"04de8e9b166ad77dcfce5eef34423a9a3d5135bd","subject":"Changed linker script alignment to 512.","message":"Changed linker script alignment to 512.\n","repos":"shockkolate\/shockk-os,shockkolate\/shockk-os,shockkolate\/shockk-os","old_file":"link.ld","new_file":"link.ld","new_contents":"ENTRY(start)\nSECTIONS\n{\n\t.text :\n\t{\n\t\tcode = .; _code = .; __code = .;\n\t\t*(.text)\n\t\t. = ALIGN(512);\n\t}\n\n\t.data :\n\t{\n\t\tdata = .; _data = .; __data = .;\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(512);\n\t}\n\n\t.bss :\n\t{\n\t\tbss = .; _bss = .; _bss = .;\n\t\t*(.bss)\n\t\t. = ALIGN(512);\n\t}\n\n\tend = .; _end = .; __end = .;\n}\n","old_contents":"ENTRY(start)\nSECTIONS\n{\n\t.text :\n\t{\n\t\tcode = .; _code = .; __code = .;\n\t\t*(.text)\n\t\t. = ALIGN(4096);\n\t}\n\n\t.data :\n\t{\n\t\tdata = .; _data = .; __data = .;\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(4096);\n\t}\n\n\t.bss :\n\t{\n\t\tbss = .; _bss = .; _bss = .;\n\t\t*(.bss)\n\t\t. = ALIGN(4096);\n\t}\n\n\tend = .; _end = .; __end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f770bbf33fc3b4ef9a52a44d64111627c604e9f4","subject":"update the link address","message":"update the link address\n","repos":"SI-RISCV\/e200_opensource,SI-RISCV\/e200_opensource,SI-RISCV\/e200_opensource,SI-RISCV\/e200_opensource,SI-RISCV\/e200_opensource","old_file":"sirv-e-sdk\/bsp\/env\/sirv-e201-arty\/link.lds","new_file":"sirv-e-sdk\/bsp\/env\/sirv-e201-arty\/link.lds","new_contents":"OUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nMEMORY\n{\n  flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 8M\n  itcm (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K\n  ram (wxa!ri) : ORIGIN = 0x90000000, LENGTH = 64K\n}\n\n\nSECTIONS\n{\n  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash AT>flash \n\n  .ilalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _itcm_lma = . );\n  } >flash AT>flash \n\n  .ialign         :\n  {\n    PROVIDE( _itcm = . );\n  } >itcm AT>flash \n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >itcm AT>flash \n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >itcm AT>flash \n\n  . = ALIGN(4);\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  PROVIDE( _eitcm = . );\n\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash AT>flash \n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash AT>flash \n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash AT>flash \n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash AT>flash \n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash AT>flash \n\n    . = ALIGN(4);\n    PROVIDE( _eitcm = . );\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash AT>flash \n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash \n\n  .data          :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n  } >ram AT>flash \n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram AT>ram \n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _heap_end = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram AT>ram \n}\n","old_contents":"OUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nMEMORY\n{\n  flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M\n  itcm (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K\n  ram (wxa!ri) : ORIGIN = 0x90000000, LENGTH = 16K\n}\n\n\nSECTIONS\n{\n  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash AT>flash \n\n  .ilalign         :\n  {\n    PROVIDE( _itcm_lma = . );\n  } >flash AT>flash \n\n  .ialign         :\n  {\n    PROVIDE( _itcm = . );\n  } >itcm AT>flash \n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >itcm AT>flash \n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >itcm AT>flash \n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n  } >itcm AT>flash \n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >itcm AT>flash \n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >itcm AT>flash \n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >itcm AT>flash \n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >itcm AT>flash \n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >itcm AT>flash \n\n    . = ALIGN(4);\n    PROVIDE( _eitcm = . );\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash AT>flash \n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash \n\n  .data          :\n  {\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n  } >ram AT>flash \n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram AT>ram \n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _heap_end = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram AT>ram \n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a01a3734f81c2cbc1bebe517c8a17929248c07f6","subject":"nrf5\/boards: Adjust heap end after increased .data usage in nrf52832 s132 linker script.","message":"nrf5\/boards: Adjust heap end after increased .data usage in nrf52832 s132 linker script.\n","repos":"adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,tralamazza\/micropython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,tralamazza\/micropython","old_file":"nrf5\/boards\/nrf52832_512k_64k_s132.ld","new_file":"nrf5\/boards\/nrf52832_512k_64k_s132.ld","new_contents":"\/*\n    GNU linker script for NRF52 w\/ s132 3.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x0001f000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x060000 \/* 396 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x200039c0, LENGTH = 0x0c640  \/* 49.5 KiB, give 8KiB headroom for softdevice *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20006000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52 w\/ s132 3.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x0001f000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x060000 \/* 396 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x200039c0, LENGTH = 0x0c640  \/* 49.5 KiB, give 8KiB headroom for softdevice *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20005000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c79c520233dabed2d8c3fd2e80ab895812be3f9c","subject":"pw_boot_cortex_m: Update to support pw_bloat.bloaty_config","message":"pw_boot_cortex_m: Update to support pw_bloat.bloaty_config\n\nUpdates the linker script in pw_boot_cortex_m to:\n1) Define the symbols necessary for pw_bloat.bloaty_config to\n   generate the memoryregions data source.\n2) Create sections containing the string unused_space which span\n   the end all of the memory regions after the used space (i.e.\n   the existing sections).\n\nChange-Id: Id1daefc71e1384f85ff85d366f03715d52bda013\nReviewed-on: https:\/\/pigweed-review.googlesource.com\/c\/pigweed\/pigweed\/+\/83641\nReviewed-by: Keir Mierle <69344103cc60b36d6e1fbdc31ce6504b2286c646@google.com>\nCommit-Queue: Ewout van Bekkum <638f134dbc68778d6b859fb04a64baea2b00b021@google.com>\n","repos":"google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed","old_file":"pw_boot_cortex_m\/basic_cortex_m.ld","new_file":"pw_boot_cortex_m\/basic_cortex_m.ld","new_contents":"\/*\n * Copyright 2020 The Pigweed Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\"); you may not\n * use this file except in compliance with the License. You may obtain a copy of\n * the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n * License for the specific language governing permissions and limitations under\n * the License.\n *\/\n\n\/* This relatively simplified linker script will work with many ARMv7-M and\n * ARMv8-M cores that have on-board memory-mapped RAM and FLASH. For more\n * complex projects and devices, it's possible this linker script will not be\n * sufficient as-is.\n *\n * This linker script is likely not suitable for a project with a bootloader.\n *\/\n\n\/* Provide useful error messages when required configurations are not set. *\/\n#ifndef PW_BOOT_VECTOR_TABLE_BEGIN\n#error \"PW_BOOT_VECTOR_TABLE_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_BEGIN\n\n#ifndef PW_BOOT_VECTOR_TABLE_SIZE\n#error \"PW_BOOT_VECTOR_TABLE_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_SIZE\n\n#ifndef PW_BOOT_FLASH_BEGIN\n#error \"PW_BOOT_FLASH_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_BEGIN\n\n#ifndef PW_BOOT_FLASH_SIZE\n#error \"PW_BOOT_FLASH_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_SIZE\n\n#ifndef PW_BOOT_RAM_BEGIN\n#error \"PW_BOOT_RAM_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_BEGIN\n\n#ifndef PW_BOOT_RAM_SIZE\n#error \"PW_BOOT_RAM_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_SIZE\n\n#ifndef PW_BOOT_HEAP_SIZE\n#error \"PW_BOOT_HEAP_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_HEAP_SIZE\n\n#ifndef PW_BOOT_MIN_STACK_SIZE\n#error \"PW_BOOT_MIN_STACK_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_MIN_STACK_SIZE\n\n\n\/* Note: This technically doesn't set the firmware's entry point. Setting the\n *       firmware entry point is done by setting vector_table[1]\n *       (Reset_Handler). However, this DOES tell the compiler how to optimize\n *       when --gc-sections is enabled.\n *\/\nENTRY(pw_boot_Entry)\n\nMEMORY\n{\n  \/* TODO(pwbug\/57): Make it possible for projects to freely customize\n   * memory regions.\n   *\/\n\n  \/* Vector Table (typically in flash) *\/\n  VECTOR_TABLE(rx) : \\\n    ORIGIN = PW_BOOT_VECTOR_TABLE_BEGIN, \\\n    LENGTH = PW_BOOT_VECTOR_TABLE_SIZE\n  \/* Internal Flash *\/\n  FLASH(rx) : \\\n    ORIGIN = PW_BOOT_FLASH_BEGIN, \\\n    LENGTH = PW_BOOT_FLASH_SIZE\n  \/* Internal SRAM *\/\n  RAM(rwx) : \\\n    ORIGIN = PW_BOOT_RAM_BEGIN, \\\n    LENGTH = PW_BOOT_RAM_SIZE\n}\n\nSECTIONS\n{\n  \/* This is the link-time vector table. If used, the VTOR (Vector Table Offset\n   * Register) MUST point to this memory location in order to be used. This can\n   * be done by ensuring this section exists at the default location of the VTOR\n   * so it's used on reset, or by explicitly setting the VTOR in a bootloader\n   * manually to point to &pw_boot_vector_table_addr before interrupts are enabled.\n   *\/\n  .vector_table : ALIGN(512)\n  {\n    pw_boot_vector_table_addr = .;\n    KEEP(*(.vector_table))\n  } >VECTOR_TABLE\n\n  \/* Main executable code. *\/\n  .code : ALIGN(8)\n  {\n    . = ALIGN(8);\n    \/* Application code. *\/\n    *(.text)\n    *(.text*)\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    . = ALIGN(8);\n    \/* Constants.*\/\n    *(.rodata)\n    *(.rodata*)\n\n    \/* .preinit_array, .init_array, .fini_array are used by libc.\n     * Each section is a list of function pointers that are called pre-main and\n     * post-exit for object initialization and tear-down.\n     * Since the region isn't explicitly referenced, specify KEEP to prevent\n     * link-time garbage collection. SORT is used for sections that have strict\n     * init\/de-init ordering requirements. *\/\n    . = ALIGN(8);\n    PROVIDE_HIDDEN(__preinit_array_start = .);\n    KEEP(*(.preinit_array*))\n    PROVIDE_HIDDEN(__preinit_array_end = .);\n\n    PROVIDE_HIDDEN(__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array*))\n    PROVIDE_HIDDEN(__init_array_end = .);\n\n    PROVIDE_HIDDEN(__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array*))\n    PROVIDE_HIDDEN(__fini_array_end = .);\n  } >FLASH\n\n  \/* Used by unwind-arm\/ *\/\n  .ARM : ALIGN(8) {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  \/* Explicitly initialized global and static data. (.data)*\/\n  .static_init_ram : ALIGN(8)\n  {\n    *(.data)\n    *(.data*)\n    . = ALIGN(8);\n  } >RAM AT> FLASH\n\n  \/* Zero initialized global\/static data. (.bss)\n   * This section is zero initialized in pw_boot_Entry(). *\/\n  .zero_init_ram : ALIGN(8)\n  {\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(8);\n  } >RAM\n\n  .heap : ALIGN(8)\n  {\n    pw_boot_heap_low_addr = .;\n    . = . + PW_BOOT_HEAP_SIZE;\n    . = ALIGN(8);\n    pw_boot_heap_high_addr = .;\n  } >RAM\n\n  \/* Link-time check for stack overlaps. *\/\n  .stack (NOLOAD) : ALIGN(8)\n  {\n    \/* Set the address that the main stack pointer should be initialized to. *\/\n    pw_boot_stack_low_addr = .;\n    HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);\n    \/* Align the stack to a lower address to ensure it isn't out of range. *\/\n    HIDDEN(_stack_high = (. + _stack_size) & ~0x7);\n    ASSERT(_stack_high - . >= PW_BOOT_MIN_STACK_SIZE,\n           \"Error: Not enough RAM for desired minimum stack size.\");\n    . = _stack_high;\n    pw_boot_stack_high_addr = .;\n  } >RAM\n\n  \/* Discard unwind info. *\/\n  .ARM.extab 0x0 (INFO) :\n  {\n    KEEP(*(.ARM.extab*))\n  }\n\n  \/*\n   * Do not declare any output sections after this comment. This area is\n   * reserved only for declaring unused sections of memory. These sections are\n   * used by pw_bloat.bloaty_config to create the utilization data source for\n   * bloaty.\n   *\/\n  .VECTOR_TABLE.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(VECTOR_TABLE) + LENGTH(VECTOR_TABLE));\n  } >VECTOR_TABLE\n\n  .FLASH.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(FLASH) + LENGTH(FLASH));\n  } >FLASH\n\n  .RAM.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(RAM) + LENGTH(RAM));\n  } >RAM\n}\n\n\/* Symbols used by core_init.c: *\/\n\/* Start of .static_init_ram in FLASH. *\/\n_pw_static_init_flash_start = LOADADDR(.static_init_ram);\n\n\/* Region of .static_init_ram in RAM. *\/\n_pw_static_init_ram_start = ADDR(.static_init_ram);\n_pw_static_init_ram_end = _pw_static_init_ram_start + SIZEOF(.static_init_ram);\n\n\/* Region of .zero_init_ram. *\/\n_pw_zero_init_ram_start = ADDR(.zero_init_ram);\n_pw_zero_init_ram_end = _pw_zero_init_ram_start + SIZEOF(.zero_init_ram);\n\n\/* arm-none-eabi expects `end` symbol to point to start of heap for sbrk. *\/\nPROVIDE(end = _pw_zero_init_ram_end);\n\n\/* These symbols are used by pw_bloat.bloaty_config to create the memoryregions\n * data source for bloaty in this format (where the optional _N defaults to 0):\n * pw_bloat_config_memory_region_NAME_{start,end}{_N,} *\/\npw_bloat_config_memory_region_VECTOR_TABLE_start = ORIGIN(VECTOR_TABLE);\npw_bloat_config_memory_region_VECTOR_TABLE_end =\n    ORIGIN(VECTOR_TABLE) + LENGTH(VECTOR_TABLE);\npw_bloat_config_memory_region_FLASH_start = ORIGIN(FLASH);\npw_bloat_config_memory_region_FLASH_end = ORIGIN(FLASH) + LENGTH(FLASH);\npw_bloat_config_memory_region_RAM_start = ORIGIN(RAM);\npw_bloat_config_memory_region_RAM_end = ORIGIN(RAM) + LENGTH(RAM);\n","old_contents":"\/*\n * Copyright 2020 The Pigweed Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\"); you may not\n * use this file except in compliance with the License. You may obtain a copy of\n * the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n * License for the specific language governing permissions and limitations under\n * the License.\n *\/\n\n\/* This relatively simplified linker script will work with many ARMv7-M and\n * ARMv8-M cores that have on-board memory-mapped RAM and FLASH. For more\n * complex projects and devices, it's possible this linker script will not be\n * sufficient as-is.\n *\n * This linker script is likely not suitable for a project with a bootloader.\n *\/\n\n\/* Provide useful error messages when required configurations are not set. *\/\n#ifndef PW_BOOT_VECTOR_TABLE_BEGIN\n#error \"PW_BOOT_VECTOR_TABLE_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_BEGIN\n\n#ifndef PW_BOOT_VECTOR_TABLE_SIZE\n#error \"PW_BOOT_VECTOR_TABLE_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_SIZE\n\n#ifndef PW_BOOT_FLASH_BEGIN\n#error \"PW_BOOT_FLASH_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_BEGIN\n\n#ifndef PW_BOOT_FLASH_SIZE\n#error \"PW_BOOT_FLASH_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_SIZE\n\n#ifndef PW_BOOT_RAM_BEGIN\n#error \"PW_BOOT_RAM_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_BEGIN\n\n#ifndef PW_BOOT_RAM_SIZE\n#error \"PW_BOOT_RAM_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_SIZE\n\n#ifndef PW_BOOT_HEAP_SIZE\n#error \"PW_BOOT_HEAP_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_HEAP_SIZE\n\n#ifndef PW_BOOT_MIN_STACK_SIZE\n#error \"PW_BOOT_MIN_STACK_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_MIN_STACK_SIZE\n\n\n\/* Note: This technically doesn't set the firmware's entry point. Setting the\n *       firmware entry point is done by setting vector_table[1]\n *       (Reset_Handler). However, this DOES tell the compiler how to optimize\n *       when --gc-sections is enabled.\n *\/\nENTRY(pw_boot_Entry)\n\nMEMORY\n{\n  \/* TODO(pwbug\/57): Make it possible for projects to freely customize\n   * memory regions.\n   *\/\n\n  \/* Vector Table (typically in flash) *\/\n  VECTOR_TABLE(rx) : \\\n    ORIGIN = PW_BOOT_VECTOR_TABLE_BEGIN, \\\n    LENGTH = PW_BOOT_VECTOR_TABLE_SIZE\n  \/* Internal Flash *\/\n  FLASH(rx) : \\\n    ORIGIN = PW_BOOT_FLASH_BEGIN, \\\n    LENGTH = PW_BOOT_FLASH_SIZE\n  \/* Internal SRAM *\/\n  RAM(rwx) : \\\n    ORIGIN = PW_BOOT_RAM_BEGIN, \\\n    LENGTH = PW_BOOT_RAM_SIZE\n}\n\nSECTIONS\n{\n  \/* This is the link-time vector table. If used, the VTOR (Vector Table Offset\n   * Register) MUST point to this memory location in order to be used. This can\n   * be done by ensuring this section exists at the default location of the VTOR\n   * so it's used on reset, or by explicitly setting the VTOR in a bootloader\n   * manually to point to &pw_boot_vector_table_addr before interrupts are enabled.\n   *\/\n  .vector_table : ALIGN(512)\n  {\n    pw_boot_vector_table_addr = .;\n    KEEP(*(.vector_table))\n  } >VECTOR_TABLE\n\n  \/* Main executable code. *\/\n  .code : ALIGN(8)\n  {\n    . = ALIGN(8);\n    \/* Application code. *\/\n    *(.text)\n    *(.text*)\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    . = ALIGN(8);\n    \/* Constants.*\/\n    *(.rodata)\n    *(.rodata*)\n\n    \/* .preinit_array, .init_array, .fini_array are used by libc.\n     * Each section is a list of function pointers that are called pre-main and\n     * post-exit for object initialization and tear-down.\n     * Since the region isn't explicitly referenced, specify KEEP to prevent\n     * link-time garbage collection. SORT is used for sections that have strict\n     * init\/de-init ordering requirements. *\/\n    . = ALIGN(8);\n    PROVIDE_HIDDEN(__preinit_array_start = .);\n    KEEP(*(.preinit_array*))\n    PROVIDE_HIDDEN(__preinit_array_end = .);\n\n    PROVIDE_HIDDEN(__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array*))\n    PROVIDE_HIDDEN(__init_array_end = .);\n\n    PROVIDE_HIDDEN(__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array*))\n    PROVIDE_HIDDEN(__fini_array_end = .);\n  } >FLASH\n\n  \/* Used by unwind-arm\/ *\/\n  .ARM : ALIGN(8) {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  \/* Explicitly initialized global and static data. (.data)*\/\n  .static_init_ram : ALIGN(8)\n  {\n    *(.data)\n    *(.data*)\n    . = ALIGN(8);\n  } >RAM AT> FLASH\n\n  \/* Zero initialized global\/static data. (.bss)\n   * This section is zero initialized in pw_boot_Entry(). *\/\n  .zero_init_ram : ALIGN(8)\n  {\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(8);\n  } >RAM\n\n  .heap : ALIGN(8)\n  {\n    pw_boot_heap_low_addr = .;\n    . = . + PW_BOOT_HEAP_SIZE;\n    . = ALIGN(8);\n    pw_boot_heap_high_addr = .;\n  } >RAM\n\n  \/* Link-time check for stack overlaps. *\/\n  .stack (NOLOAD) : ALIGN(8)\n  {\n    \/* Set the address that the main stack pointer should be initialized to. *\/\n    pw_boot_stack_low_addr = .;\n    HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);\n    \/* Align the stack to a lower address to ensure it isn't out of range. *\/\n    HIDDEN(_stack_high = (. + _stack_size) & ~0x7);\n    ASSERT(_stack_high - . >= PW_BOOT_MIN_STACK_SIZE,\n           \"Error: Not enough RAM for desired minimum stack size.\");\n    . = _stack_high;\n    pw_boot_stack_high_addr = .;\n  } >RAM\n\n  \/* Discard unwind info. *\/\n  .ARM.extab 0x0 (INFO) :\n  {\n    KEEP(*(.ARM.extab*))\n  }\n}\n\n\/* Symbols used by core_init.c: *\/\n\/* Start of .static_init_ram in FLASH. *\/\n_pw_static_init_flash_start = LOADADDR(.static_init_ram);\n\n\/* Region of .static_init_ram in RAM. *\/\n_pw_static_init_ram_start = ADDR(.static_init_ram);\n_pw_static_init_ram_end = _pw_static_init_ram_start + SIZEOF(.static_init_ram);\n\n\/* Region of .zero_init_ram. *\/\n_pw_zero_init_ram_start = ADDR(.zero_init_ram);\n_pw_zero_init_ram_end = _pw_zero_init_ram_start + SIZEOF(.zero_init_ram);\n\n\/* arm-none-eabi expects `end` symbol to point to start of heap for sbrk. *\/\nPROVIDE(end = _pw_zero_init_ram_end);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"00e029209de921177db74f7c210a2f4f99fa6fba","subject":"Reorganization of memory layout","message":"Reorganization of memory layout\n","repos":"Cloudino\/Cloudino-Arduino-IDE,smily77\/Arduino,ikbelkirasan\/Arduino,pdNor\/Arduino,bsmr-arduino\/Arduino,acosinwork\/Arduino,me-no-dev\/Arduino-1,weera00\/Arduino,ThoughtWorksIoTGurgaon\/Arduino,eggfly\/arduino,jabezGit\/Arduino,shannonshsu\/Arduino,fungxu\/Arduino,jamesrob4\/Arduino,ogahara\/Arduino,weera00\/Arduino,shannonshsu\/Arduino,smily77\/Arduino,ikbelkirasan\/Arduino,ThoughtWorksIoTGurgaon\/Arduino,Gourav2906\/Arduino,ektor5\/Arduino,wilhelmryan\/Arduino,adamkh\/Arduino,NaSymbol\/Arduino,ikbelkirasan\/Arduino,Cloudino\/Cloudino-Arduino-IDE,tommyli2014\/Arduino,drpjk\/Arduino,lulufei\/Arduino,jomolinare\/Arduino,ccoenen\/Arduino,superboonie\/Arduino,mc-hamster\/esp8266-Arduino,koltegirish\/Arduino,superboonie\/Arduino,HCastano\/Arduino,shannonshsu\/Arduino,myrtleTree33\/Arduino,gurbrinder\/Arduino,NeuralSpaz\/Arduino,zederson\/Arduino,wayoda\/Arduino,PaoloP74\/Arduino,cscenter\/Arduino,mattvenn\/Arduino,OpenDevice\/Arduino,tannewt\/Arduino,stevemarple\/Arduino-org,ssvs111\/Arduino,mattvenn\/Arduino,ogferreiro\/Arduino,arduino-org\/Arduino,vbextreme\/Arduino,paulmand3l\/Arduino,Cloudino\/Cloudino-Arduino-IDE,PaoloP74\/Arduino,niggor\/Arduino_cc,Chris--A\/Arduino,jmgonzalez00449\/Arduino,arunkuttiyara\/Arduino,Cloudino\/Arduino,plaintea\/esp8266-Arduino,lulufei\/Arduino,talhaburak\/Arduino,eggfly\/arduino,ThoughtWorksIoTGurgaon\/Arduino,cscenter\/Arduino,vbextreme\/Arduino,jaej-dev\/Arduino,majenkotech\/Arduino,SmartArduino\/Arduino-1,EmuxEvans\/Arduino,wdoganowski\/Arduino,jamesrob4\/Arduino,NaSymbol\/Arduino,Alfredynho\/AgroSis,piersoft\/esp8266-Arduino,paulo-raca\/ESP8266-Arduino,wayoda\/Arduino,NicoHood\/Arduino,arunkuttiyara\/Arduino,weera00\/Arduino,fungxu\/Arduino,superboonie\/Arduino,andyvand\/Arduino-1,ntruchsess\/Arduino-1,ashwin713\/Arduino,zaiexx\/Arduino,me-no-dev\/Arduino-1,scdls\/Arduino,ikbelkirasan\/Arduino,pdNor\/Arduino,ccoenen\/Arduino,jaehong\/Xmegaduino,jaimemaretoli\/Arduino,karlitxo\/Arduino,ForestNymph\/Arduino_sources,chaveiro\/Arduino,ogferreiro\/Arduino,myrtleTree33\/Arduino,stevemarple\/Arduino-org,sanyaade-iot\/Arduino-1,tbowmo\/Arduino,adafruit\/ESP8266-Arduino,piersoft\/esp8266-Arduino,mboufos\/esp8266-Arduino,NicoHood\/Arduino,bigjosh\/Arduino,ssvs111\/Arduino,myrtleTree33\/Arduino,ogahara\/Arduino,gonium\/Arduino,arduino-org\/Arduino,spapadim\/Arduino,scdls\/Arduino,tommyli2014\/Arduino,rcook\/DesignLab,NicoHood\/Arduino,koltegirish\/Arduino,mboufos\/esp8266-Arduino,leftbrainstrain\/Arduino-ESP8266,gestrem\/Arduino,paulo-raca\/ESP8266-Arduino,raimohanska\/Arduino,chaveiro\/Arduino,henningpohl\/Arduino,xxxajk\/Arduino-1,gonium\/Arduino,SmartArduino\/Arduino-1,jaej-dev\/Arduino,andyvand\/Arduino-1,lukeWal\/Arduino,ricklon\/Arduino,nkolban\/Arduino,gonium\/Arduino,Cloudino\/Cloudino-Arduino-IDE,jaehong\/Xmegaduino,laylthe\/Arduino,ntruchsess\/Arduino-1,zaiexx\/Arduino,mattvenn\/Arduino,probonopd\/Arduino,tbowmo\/Arduino,leftbrainstrain\/Arduino-ESP8266,ccoenen\/Arduino,mattvenn\/Arduino,ccoenen\/Arduino,tomkrus007\/Arduino,raimohanska\/Arduino,KlaasDeNys\/Arduino,Cloudino\/Arduino,henningpohl\/Arduino,rcook\/DesignLab,danielchalef\/Arduino,ogferreiro\/Arduino,mangelajo\/Arduino,plaintea\/esp8266-Arduino,KlaasDeNys\/Arduino,jmgonzalez00449\/Arduino,lukeWal\/Arduino,PaoloP74\/Arduino,Chris--A\/Arduino,henningpohl\/Arduino,jaimemaretoli\/Arduino,talhaburak\/Arduino,noahchense\/Arduino-1,garci66\/Arduino,henningpohl\/Arduino,eddyst\/Arduino-SourceCode,scdls\/Arduino,radut\/Arduino,UDOOboard\/Arduino,koltegirish\/Arduino,KlaasDeNys\/Arduino,spapadim\/Arduino,majenkotech\/Arduino,ashwin713\/Arduino,henningpohl\/Arduino,niggor\/Arduino_cc,shiitakeo\/Arduino,toddtreece\/esp8266-Arduino,ThoughtWorksIoTGurgaon\/Arduino,aichi\/Arduino-2,me-no-dev\/Arduino-1,kidswong999\/Arduino,HCastano\/Arduino,eeijcea\/Arduino-1,NaSymbol\/Arduino,danielchalef\/Arduino,raimohanska\/Arduino,mboufos\/esp8266-Arduino,aichi\/Arduino-2,mc-hamster\/esp8266-Arduino,paulmand3l\/Arduino,ari-analytics\/Arduino,mattvenn\/Arduino,plinioseniore\/Arduino,NicoHood\/Arduino,andrealmeidadomingues\/Arduino,mateuszdw\/Arduino,ssvs111\/Arduino,Alfredynho\/AgroSis,ssvs111\/Arduino,ntruchsess\/Arduino-1,damellis\/Arduino,ccoenen\/Arduino,raimohanska\/Arduino,gurbrinder\/Arduino,acosinwork\/Arduino,noahchense\/Arduino-1,xxxajk\/Arduino-1,adafruit\/ESP8266-Arduino,eeijcea\/Arduino-1,gestrem\/Arduino,gberl001\/Arduino,ricklon\/Arduino,tomkrus007\/Arduino,EmuxEvans\/Arduino,adafruit\/ESP8266-Arduino,leftbrainstrain\/Arduino-ESP8266,Gourav2906\/Arduino,aichi\/Arduino-2,bsmr-arduino\/Arduino,adafruit\/ESP8266-Arduino,ForestNymph\/Arduino_sources,xxxajk\/Arduino-1,byran\/Arduino,paulmand3l\/Arduino,OpenDevice\/Arduino,ricklon\/Arduino,HCastano\/Arduino,adamkh\/Arduino,cscenter\/Arduino,talhaburak\/Arduino,sanyaade-iot\/Arduino-1,byran\/Arduino,plaintea\/esp8266-Arduino,garci66\/Arduino,talhaburak\/Arduino,ricklon\/Arduino,SmartArduino\/Arduino-1,scdls\/Arduino,leftbrainstrain\/Arduino-ESP8266,radut\/Ardui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----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n\trom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 \/* Flash, 512K *\/\n\tsram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 \/* sram0, 64K *\/\n\tsram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 \/* sram1, 32K *\/\n\tram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 \/* sram, 96K *\/\n}\n\nRAM_END = 0x20088000 ; \/* There is a way to define this as ram.ORIGIN + ram.LENGTH ? *\/\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n\n    \/* put stack section at the bottom of ram space *\/\n    .stack RAM_END (NOLOAD):\n    {\n        _sstack = .;\n        _estack = .;\n    } > ram\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n\trom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 \/* Flash, 512K *\/\n\tsram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 \/* sram0, 64K *\/\n\tsram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 \/* sram1, 32K *\/\n\tram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 \/* sram, 96K *\/\n}\n\n\/* The stack size used by the application. NOTE: you need to adjust  *\/\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"481df00639a1c7d8b588b0ce32f7f8f7ef8e9043","subject":"lib: fix alignment in ldscript.","message":"lib: fix alignment in ldscript.\n","repos":"evilmartians\/foundry,whitequark\/foundry","old_file":"lib\/devices\/common32.ld","new_file":"lib\/devices\/common32.ld","new_contents":"OUTPUT_FORMAT(elf32-littlearm)\nENTRY(_startup)\n\nSECTIONS {\n\t.vectors : {\n\t\t*(.vectors)\n\t} > flash\n\n\t.text : {\n\t\t*(.text .text.*)\n\n\t\t. = ALIGN(4);\n\n\t\t*(.rodata .rodata.*)\n\n\t\t. = ALIGN(4);\n\n\t\t__text_end__ = .;\n\t} > flash\n\n\t.data : AT (__text_end__) {\n\t\t__ram_begin__  = .;\n\t\t__data_begin__ = .;\n\n\t\t*(.data .data.*)\n\n\t\t. = ALIGN(4);\n\n\t\t__data_end__ = .;\n\t} > ram\n\n\t. = ALIGN(4);\n\n\t.bss : {\n\t\t__bss_begin__ = .;\n\n\t\t*(.bss* COMMON)\n\n\t\t. = ALIGN(4);\n\n\t\t__bss_end__ = .;\n\t} > ram\n\n\t__stack_end__ = ADDR(.data) + RAMSIZE;\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t\t*(.ARM.attributes)\n\t}\n}\n","old_contents":"OUTPUT_FORMAT(elf32-littlearm)\nENTRY(_startup)\n\nSECTIONS {\n\t.vectors : {\n\t\t*(.vectors)\n\t} > flash\n\n\t.text : {\n\t\t*(.text)\n\n\t\t. = ALIGN(4);\n\n\t\t*(.rodata)\n\n\t\t. = ALIGN(4);\n\n\t\t__text_end__ = .;\n\t} > flash\n\n\t.data : {\n\t\t__ram_begin__  = .;\n\t\t__data_begin__ = .;\n\n\t\t*(.data)\n\n\t\t. = ALIGN(4);\n\n\t\t__data_end__ = .;\n\t} > ram AT>flash\n\n\t. = ALIGN(4);\n\n\t.bss : {\n\t\t__bss_begin__ = .;\n\n\t\t*(.bss)\n\t\t*(COMMON)\n\n\t\t. = ALIGN(4);\n\n\t\t__bss_end__ = .;\n\t} > ram\n\n\t__stack_end__ = ADDR(.data) + RAMSIZE;\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t\t*(.ARM.attributes)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ed85b76093d2311dc40f6084385dad63cd118d9e","subject":"LD: Assert when CONFIG_PRIVILEGED_STACK_TEXT_AREA is too small","message":"LD: Assert when CONFIG_PRIVILEGED_STACK_TEXT_AREA is too small\n\nThe error message is obscure when CONFIG_PRIVILEGED_STACK_TEXT_AREA is\nconfigured incorrectly. It looks like this:\n\nzephyr\/linker.cmd:73 cannot move location counter backwards (from\n0000000000069bfc to 0000000000069bd8)\n\nThis patch re-writes the linker script mechanism in a (believed and\ntested) semantically equivalent way such that it is possible to use an\nassertion.\n\nThe assertion's error message now looks like this:\n\nMemory region         Used Size  Region Size  %age Used\n           FLASH:      503012 B         1 MB     47.97%\n            SRAM:       53760 B       256 KB     20.51%\n        IDT_LIST:         120 B         2 KB      5.86\nreal-ld: The configuration system has incorrectly set\n'CONFIG_PRIVILEGED_STACK_TEXT_AREA' to\n128, which is not big enough. You must\nthrough Kconfig either disable 'CONFIG_USERSPACE', or set\n'CONFIG_PRIVILEGED_STACK_TEXT_AREA' to a value larger than\n128 .\ncollect2: error: ld returned 1 exit status\n\nSigned-off-by: Sebastian B\u00f8e <edee888afd63e94916688495334700803eba20a0@nordicsemi.no>\n","repos":"ldts\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,ldts\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,explora26\/zephyr,explora26\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,ldts\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr","old_file":"include\/linker\/priv_stacks-text.ld","new_file":"include\/linker\/priv_stacks-text.ld","new_contents":"\/*\n * Copyright (c) 2017 Linaro Limited.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n#ifdef CONFIG_USERSPACE\n\t\/* We need to reserve room for the gperf generated hash functions.\n\t * Fortunately, unlike the data tables, the size of the code is\n\t * reasonably predictable.\n\t *\/\n\t_priv_stacks_text_area_start = .;\n\t*(\".priv_stacks.text*\")\n\t_priv_stacks_text_area_end = .;\n\n\t_priv_stacks_text_area_used = _priv_stacks_text_area_end - _priv_stacks_text_area_start;\n\n#ifndef LINKER_PASS2\n\tPROVIDE(_k_priv_stack_find = .);\n#endif\n\n\t\/* In a valid build the MAX function will always evaluate to the\n\tsecond argument below, but to give the user a good error message\n\twhen the area overflows we need to temporarily corrupt the\n\tlocation counter, and then detect the overflow with an assertion\n\tlater on. *\/\n\n\t. = MAX(., _priv_stacks_text_area_start + CONFIG_PRIVILEGED_STACK_TEXT_AREA);\n\n\tASSERT(\n\t\tCONFIG_PRIVILEGED_STACK_TEXT_AREA >= _priv_stacks_text_area_used,\n\"The configuration system has incorrectly set\n'CONFIG_PRIVILEGED_STACK_TEXT_AREA' to\nCONFIG_PRIVILEGED_STACK_TEXT_AREA, which is not big enough. You must\nthrough Kconfig either disable 'CONFIG_USERSPACE', or set\n'CONFIG_PRIVILEGED_STACK_TEXT_AREA' to a value larger than\nCONFIG_PRIVILEGED_STACK_TEXT_AREA.\"\n\t\t);\n#endif \/* CONFIG_USERSPACE *\/\n","old_contents":"\/*\n * Copyright (c) 2017 Linaro Limited.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n#ifdef CONFIG_USERSPACE\n\t\/* We need to reserve room for the gperf generated hash functions.\n\t * Fortunately, unlike the data tables, the size of the code is\n\t * reasonably predictable.\n\t *\n\t * The linker will error out complaining that the location pointer\n\t * is moving backwards if the reserved room isn't large enough.\n\t *\/\n\t_priv_stacks_text_area_start = .;\n\t*(\".priv_stacks.text*\")\n\t_priv_stacks_text_area_end = .;\n#ifndef LINKER_PASS2\n\tPROVIDE(_k_priv_stack_find = .);\n#endif\n\t. += CONFIG_PRIVILEGED_STACK_TEXT_AREA - (_priv_stacks_text_area_end - _priv_stacks_text_area_start);\n#endif \/* CONFIG_USERSPACE *\/\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"59ef49564f214f5031cf7e6c67290dac6354fb69","subject":"Remove obsolete line from firmware\/sections.lds","message":"Remove obsolete line from firmware\/sections.lds\n\nSigned-off-by: Claire Wolf <da7dd17269675e6648b2de3690262d0e18b89cca@symbioticeda.com>\n","repos":"cliffordwolf\/picorv32,cliffordwolf\/picorv32,cliffordwolf\/picorv32,cliffordwolf\/picorv32","old_file":"firmware\/sections.lds","new_file":"firmware\/sections.lds","new_contents":"\/*\nThis is free and unencumbered software released into the public domain.\n\nAnyone is free to copy, modify, publish, use, compile, sell, or\ndistribute this software, either in source code form or as a compiled\nbinary, for any purpose, commercial or non-commercial, and by any\nmeans.\n*\/\n\nMEMORY {\n\t\/* the memory in the testbench is 128k in size;\n\t * set LENGTH=96k and leave at least 32k for stack *\/\n\tmem : ORIGIN = 0x00000000, LENGTH = 0x00018000\n}\n\nSECTIONS {\n\t.memory : {\n\t\t. = 0x000000;\n\t\tstart*(.text);\n\t\t*(.text);\n\t\t*(*);\n\t\tend = .;\n\t\t. = ALIGN(4);\n\t} > mem\n}\n","old_contents":"\/*\nThis is free and unencumbered software released into the public domain.\n\nAnyone is free to copy, modify, publish, use, compile, sell, or\ndistribute this software, either in source code form or as a compiled\nbinary, for any purpose, commercial or non-commercial, and by any\nmeans.\n*\/\n\nMEMORY {\n\t\/* the memory in the testbench is 128k in size;\n\t * set LENGTH=96k and leave at least 32k for stack *\/\n\tmem : ORIGIN = 0x00000000, LENGTH = 0x0000c000\n\tmem : ORIGIN = 0x00000000, LENGTH = 0x00018000\n}\n\nSECTIONS {\n\t.memory : {\n\t\t. = 0x000000;\n\t\tstart*(.text);\n\t\t*(.text);\n\t\t*(*);\n\t\tend = .;\n\t\t. = ALIGN(4);\n\t} > mem\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"ae8713fea8d81cb530d1bfed8b907b4c13469dec","subject":"cpu\/esp8266: places ztimer_core function in IRAM","message":"cpu\/esp8266: places ztimer_core function in IRAM\n\n`ztimer_core` functions have to reside in IRAM for timing reasons and to be available also when the IROM cache is disabled. Although the module is called `ztimer`, its object files are generated in directory `ztimer_core`.","repos":"miri64\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,ant9000\/RIOT,miri64\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,kYc0o\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT","old_file":"cpu\/esp8266\/ld\/esp8266.riot-os.ld","new_file":"cpu\/esp8266\/ld\/esp8266.riot-os.ld","new_contents":"\/**\n * This linker script is a combined and modified version of esp8266.ld and\n * esp8266.common.ld from ESP8266-RTOS-SDK.\n *\/\n\nMEMORY\n{\n  dport0_0_seg : org = 0x3FF00000, len = 0x10\n  dram0_0_seg  : org = 0x3FFE8000, len = 0x18000\n  iram1_0_seg  : org = 0x40100000, len = 0xC000\n  irom0_0_seg  : org = 0x40200010 + 0x10000, len = 0x80000 - 0x10 - 0x10000\n  rtc_seg      : org = 0x60001200, len = 0x200\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  \/* RTC memory holds user's data\/rodata *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .rtc.bss :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *(.rtc.bss)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    KEEP (*(SORT(.xfa.*)))\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    \/* TODO put only necessary .rodata to dram *\/\n    \/* *(.rodata .rodata.*) *\/\n    *libc.a:*.o(.rodata.* .rodata)\n    *core\/*(.rodata.* .rodata)\n    *cpu\/*(.rodata .rodata.*)\n    *libpp.a:(.rodata.* .rodata)\n    *liblog.a:(.rodata.* .rodata)\n\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    KEEP (*(SORT(.roxfa.*)))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  . = 0x3FFFFFF0;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    LONG(_text_start)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)   \/* 0x40100010 *\/\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)     \/* 0x40100020 *\/\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)  \/* 0x40100030 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)    \/* 0x40100050 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)  \/* 0x40100070 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.UserExceptionTrampoline.text)  \/* 0x40100090 *\/\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* normal code should be in irom0 *\/\n    \/*\n    *(.literal .text)\n    *core.a:*(.literal .text .literal.* .text.*)\n    *\/\n    *gdbstub\/*(.literal .text .literal.* .text.*)\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    \/* RIOT-OS compiled source files that use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1 .iram1.*)\n\n    \/* SDK libraries that expect their .text or .data sections to link to iram *\/\n    \/* TODO *libcore.a:(.bss .data .bss.* .data.* COMMON) *\/\n    *esp_idf_spi_flash\/spi_flash_raw.o(.literal .text .literal.* .text.*)\n    *esp_idf_esp8266\/ets_printf.o(.literal .text .literal.* .text.*)\n    \/*\n    *cpu.a:*.o(.literal .text .literal.* .text.*)\n    *\/\n    *core\/sched.o(.literal .text .literal.* .text.*)\n    *esp_wifi\/*(.literal .text .literal.* .text.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *freertos_common\/*(.literal .text .literal.* .text.*)\n    *periph\/*(.literal .text .literal.* .text.*)\n    *ztimer_core\/*(.literal .text .literal.* .text.*)\n\n    *libhal.a:clock.o(.literal .text .literal.* .text.*)\n    *libhal.a:int_asm--set_intclear.o(.literal .text .literal.* .text.*)\n    *libpp.a:esf_buf.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:rate_control.o(.literal .text .literal.* .text.*)\n    *libpp.a:trc.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_chip_v6_cal.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_sleep.o(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa\/*(.literal .text .literal.* .text.*)\n\n    \/* libgcc functions required for debugging have to be in IRAM *\/\n    *libgcc.a:unwind-dw2.o(.literal .text .literal.* .text.*)\n\n    \/* libgcc integer functions also need to be in .text *\/\n    \/* some are called before flash is mapped and also for performance) *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    *libgcc.a:*mulsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*divsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*fixsfsi.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    \/*\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memchr.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n    *\/\n\n    *enc28j60\/*(.literal .text .literal.* .text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    \/* RIOT-OS compiled code and RO data go into IROM by default *\/\n    *(.literal .text .literal.* .text.*)\n    *(.rodata .rodata.*)\n\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n    . = ALIGN(16);\n    __start_ksymatabesp_socket = .;\n    *(ksymatabesp_socket)\n    __stop_ksymatabesp_socket = .;\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","old_contents":"\/**\n * This linker script is a combined and modified version of esp8266.ld and\n * esp8266.common.ld from ESP8266-RTOS-SDK.\n *\/\n\nMEMORY\n{\n  dport0_0_seg : org = 0x3FF00000, len = 0x10\n  dram0_0_seg  : org = 0x3FFE8000, len = 0x18000\n  iram1_0_seg  : org = 0x40100000, len = 0xC000\n  irom0_0_seg  : org = 0x40200010 + 0x10000, len = 0x80000 - 0x10 - 0x10000\n  rtc_seg      : org = 0x60001200, len = 0x200\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  \/* RTC memory holds user's data\/rodata *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .rtc.bss :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *(.rtc.bss)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    KEEP (*(SORT(.xfa.*)))\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    \/* TODO put only necessary .rodata to dram *\/\n    \/* *(.rodata .rodata.*) *\/\n    *libc.a:*.o(.rodata.* .rodata)\n    *core\/*(.rodata.* .rodata)\n    *cpu\/*(.rodata .rodata.*)\n    *libpp.a:(.rodata.* .rodata)\n    *liblog.a:(.rodata.* .rodata)\n\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    KEEP (*(SORT(.roxfa.*)))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  . = 0x3FFFFFF0;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    LONG(_text_start)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)   \/* 0x40100010 *\/\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)     \/* 0x40100020 *\/\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)  \/* 0x40100030 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)    \/* 0x40100050 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)  \/* 0x40100070 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.UserExceptionTrampoline.text)  \/* 0x40100090 *\/\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* normal code should be in irom0 *\/\n    \/*\n    *(.literal .text)\n    *core.a:*(.literal .text .literal.* .text.*)\n    *\/\n    *gdbstub\/*(.literal .text .literal.* .text.*)\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    \/* RIOT-OS compiled source files that use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1 .iram1.*)\n\n    \/* SDK libraries that expect their .text or .data sections to link to iram *\/\n    \/* TODO *libcore.a:(.bss .data .bss.* .data.* COMMON) *\/\n    *esp_idf_spi_flash\/spi_flash_raw.o(.literal .text .literal.* .text.*)\n    *esp_idf_esp8266\/ets_printf.o(.literal .text .literal.* .text.*)\n    \/*\n    *cpu.a:*.o(.literal .text .literal.* .text.*)\n    *\/\n    *core\/sched.o(.literal .text .literal.* .text.*)\n    *esp_wifi\/*(.literal .text .literal.* .text.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *freertos_common\/*(.literal .text .literal.* .text.*)\n    *periph\/*(.literal .text .literal.* .text.*)\n    *ztimer\/*(.literal .text .literal.* .text.*)\n\n    *libhal.a:clock.o(.literal .text .literal.* .text.*)\n    *libhal.a:int_asm--set_intclear.o(.literal .text .literal.* .text.*)\n    *libpp.a:esf_buf.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:rate_control.o(.literal .text .literal.* .text.*)\n    *libpp.a:trc.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_chip_v6_cal.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_sleep.o(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa\/*(.literal .text .literal.* .text.*)\n\n    \/* libgcc functions required for debugging have to be in IRAM *\/\n    *libgcc.a:unwind-dw2.o(.literal .text .literal.* .text.*)\n\n    \/* libgcc integer functions also need to be in .text *\/\n    \/* some are called before flash is mapped and also for performance) *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    *libgcc.a:*mulsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*divsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*fixsfsi.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    \/*\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memchr.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n    *\/\n\n    *enc28j60\/*(.literal .text .literal.* .text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    \/* RIOT-OS compiled code and RO data go into IROM by default *\/\n    *(.literal .text .literal.* .text.*)\n    *(.rodata .rodata.*)\n\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n    . = ALIGN(16);\n    __start_ksymatabesp_socket = .;\n    *(ksymatabesp_socket)\n    __stop_ksymatabesp_socket = .;\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"ccd40d55027055f7f1ad256035dcdc7b79a219bc","subject":"linker: arm: discard .note.GNU-stack","message":"linker: arm: discard .note.GNU-stack\n\nSimilar to what was required for x86 in #12719 \/ PR#12752\n\nSigned-off-by: Peter Robinson <0cd2d1e82f6226d6d80917107cdcc165e1fecc43@gmail.com>\n","repos":"galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n#ifdef DT_DTCM_BASE_ADDRESS\n    DTCM                  (rw) : ORIGIN = DT_DTCM_BASE_ADDRESS, LENGTH = DT_DTCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#if defined(CONFIG_CC3220SF_DEBUG) || defined(CONFIG_CC3235SF_DEBUG)\n\t\/* Add CC32xx flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\n#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER\n\tKEEP(*(.boot_hdr.conf))\n\t. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;\n\tKEEP(*(.boot_hdr.ivt))\n\tKEEP(*(.boot_hdr.data))\n#ifdef CONFIG_DEVICE_CONFIGURATION_DATA\n\tKEEP(*(.boot_hdr.dcd_data))\n#endif\n#endif\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#ifdef CONFIG_KINETIS_FLASH_CONFIG\n\t. = CONFIG_KINETIS_FLASH_CONFIG_OFFSET;\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n#endif\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef DT_DTCM_BASE_ADDRESS\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_bss_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_data_end = .;\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif \/* DT_DTCM_BASE_ADDRESS *\/\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#elif defined(CONFIG_CPU_HAS_NRF_IDAU)\n\t\/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. *\/\n\t#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NSC_ALIGN_END . = ALIGN(0x8000)\n#else\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\tASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))\n\t\t\t == (0x8000 - (__sg_start % 0x8000))\n\t\t&& (0x8000 - (__sg_start % 0x8000)) >= 32\n\t\t&& (0x8000 - (__sg_start % 0x8000)) <= 4096,\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n#ifdef DT_DTCM_BASE_ADDRESS\n    DTCM                  (rw) : ORIGIN = DT_DTCM_BASE_ADDRESS, LENGTH = DT_DTCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#if defined(CONFIG_CC3220SF_DEBUG) || defined(CONFIG_CC3235SF_DEBUG)\n\t\/* Add CC32xx flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\n#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER\n\tKEEP(*(.boot_hdr.conf))\n\t. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;\n\tKEEP(*(.boot_hdr.ivt))\n\tKEEP(*(.boot_hdr.data))\n#ifdef CONFIG_DEVICE_CONFIGURATION_DATA\n\tKEEP(*(.boot_hdr.dcd_data))\n#endif\n#endif\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#ifdef CONFIG_KINETIS_FLASH_CONFIG\n\t. = CONFIG_KINETIS_FLASH_CONFIG_OFFSET;\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n#endif\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef DT_DTCM_BASE_ADDRESS\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_bss_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_data_end = .;\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif \/* DT_DTCM_BASE_ADDRESS *\/\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#elif defined(CONFIG_CPU_HAS_NRF_IDAU)\n\t\/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. *\/\n\t#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NSC_ALIGN_END . = ALIGN(0x8000)\n#else\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\tASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))\n\t\t\t == (0x8000 - (__sg_start % 0x8000))\n\t\t&& (0x8000 - (__sg_start % 0x8000)) >= 32\n\t\t&& (0x8000 - (__sg_start % 0x8000)) <= 4096,\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"516bf8e70288b682067670510993fe4ba83fb6a3","subject":".data1 section added","message":".data1 section added\n","repos":"okertanov\/VelaOS,okertanov\/VelaOS,okertanov\/VelaOS,okertanov\/VelaOS,okertanov\/VelaOS","old_file":"src\/pal\/Bare-x86\/boot\/kernel.ld","new_file":"src\/pal\/Bare-x86\/boot\/kernel.ld","new_contents":"\/**\n    @copyright  Copyright (C) 2011 Oleg Kertanov <okertanov@gmail.com>\n    @license    BSD\n*\/\n\nOUTPUT_FORMAT(\"elf32-i386\")\n\nENTRY (start)\n\nSECTIONS\n{\n    . = 0x00100000;\n\n    __image_start__ = . ;\n\n    .text ALIGN (0x1000) :\n    {\n        __text_start__ = . ;\n        start.o(.text)\n        *(.text)\n        __text_end__ = . ;\n    }\n\n    .rodata ALIGN (0x1000) :\n    {\n        __rodata_start__ = . ;\n        *(.rodata)\n        __rodata_end__ = . ;\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        __data_start__ = . ;\n        *(.data)\n        *(.data1)\n        *(.rdata)\n        __data_end__ = . ;\n    }\n\n    .bss ALIGN (0x1000) :\n    {\n        __bss_start__ = . ;\n        *(COMMON)\n        *(.bss)\n        __bss_end__ = . ;\n    }\n\n    .end ALIGN (0x1000) :\n    {\n        __image_end__ = . ;\n    }\n}\n\n","old_contents":"\/**\n    @copyright  Copyright (C) 2011 Oleg Kertanov <okertanov@gmail.com>\n    @license    BSD\n*\/\n\nOUTPUT_FORMAT(\"elf32-i386\")\n\nENTRY (start)\n\nSECTIONS\n{\n    . = 0x00100000;\n\n    __image_start__ = . ;\n\n    .text ALIGN (0x1000) :\n    {\n        __text_start__ = . ;\n        start.o(.text)\n        *(.text)\n        __text_end__ = . ;\n    }\n\n    .rodata ALIGN (0x1000) :\n    {\n        __rodata_start__ = . ;\n        *(.rodata)\n        __rodata_end__ = . ;\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        __data_start__ = . ;\n        *(.data)\n        *(.rdata)\n        __data_end__ = . ;\n    }\n\n    .bss ALIGN (0x1000) :\n    {\n        __bss_start__ = . ;\n        *(COMMON)\n        *(.bss)\n        __bss_end__ = . ;\n    }\n\n    .end ALIGN (0x1000) :\n    {\n        __image_end__ = . ;\n    }\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"7a31c5a6ae5a3a32945bc54e12fc9624e5533ad7","subject":"Align linker regions","message":"Align linker regions\n\nA bit of a hack.\n","repos":"iankronquist\/kernel-of-truth,iankronquist\/kernel-of-truth,iankronquist\/kernel-of-truth,iankronquist\/kernel-of-truth,iankronquist\/kernel-of-truth","old_file":"kernel\/arch\/x64\/link.ld","new_file":"kernel\/arch\/x64\/link.ld","new_contents":"ENTRY(_start)\n\nSECTIONS {\n\t. = 1M;\n\t__kernel_start = .;\n\t.multiboot BLOCK(4K) : ALIGN(4K) {\n\t\t*(.multiboot)\n\t}\n\n\t.text BLOCK(4K) : ALIGN(4K) {\n\t\t__text_start = .;\n\t\t*(.text)\n\t}\n\n\t.data BLOCK(4K) : ALIGN(4K) {\n\t\t__text_end = .;\n\t\t__data_start = .;\n\t\t*(.data)\n\t}\n\n\t.rodata BLOCK(4K) : ALIGN(4K) {\n\t\t__data_end = .;\n\t\t__rodata_start = .;\n\t\t*(.rodata)\n\t}\n\n\t.bss BLOCK(4K) : ALIGN(4K) {\n\t\t__bss_start = .;\n\t\t__rodata_end = .;\n\t\t*(.bss)\n\t}\n\n\t. = ALIGN(4K);\n\t__bss_end = .;\n\t__kernel_end = .;\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS {\n\t. = 1M;\n\t__kernel_start = .;\n\t.multiboot BLOCK(4K) : ALIGN(4K) {\n\t\t*(.multiboot)\n\t}\n\n\t__text_start = .;\n\t.text BLOCK(4K) : ALIGN(4K) {\n\t\t*(.text)\n\t}\n\t__text_end = .;\n\n\t__data_start = .;\n\t.data BLOCK(4K) : ALIGN(4K) {\n\t\t*(.data)\n\t}\n\t__data_end = .;\n\n\t__rodata_start = .;\n\t.rodata BLOCK(4K) : ALIGN(4K) {\n\t\t*(.rodata)\n\t}\n\t__rodata_end = .;\n\n\t__bss_start = .;\n\t.bss BLOCK(4K) : ALIGN(4K) {\n\t\t*(.bss)\n\t}\n\t__bss_end = .;\n\n\t. = ALIGN(4K);\n\t__kernel_end = .;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"14cb1284226fd96b1c7b348de7d2f56c2a0cb14c","subject":"x86: move .tbss \/ .tdata to read-only area","message":"x86: move .tbss \/ .tdata to read-only area\n","repos":"alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,alfred-bratterud\/IncludeOS,ingve\/IncludeOS,mnordsletten\/IncludeOS,AnnikaH\/IncludeOS,hioa-cs\/IncludeOS,AndreasAakesson\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,ingve\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,AndreasAakesson\/IncludeOS,ingve\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,AnnikaH\/IncludeOS,ingve\/IncludeOS,alfred-bratterud\/IncludeOS,hioa-cs\/IncludeOS,AndreasAakesson\/IncludeOS,ingve\/IncludeOS,hioa-cs\/IncludeOS","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0x200000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  . = _ELF_START_;\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n\n  .text ALIGN(0x1000):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x1000) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  _EXEC_END_ = .;\n  _READONLY_START_ = .;\n  .config ALIGN(0x1000) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n  _READONLY_END_ = .;\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","old_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0x200000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  . = _ELF_START_;\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n\n  .text ALIGN(0x1000):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x1000) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  _EXEC_END_ = .;\n  _READONLY_START_ = .;\n  .config ALIGN(0x1000) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n  _READONLY_END_ = .;\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"837ddf6d8c4302c3eb1082407af7d1651216791f","subject":"cpu\/esp32\/ld: use folder name instead of archive for module objects","message":"cpu\/esp32\/ld: use folder name instead of archive for module objects\n","repos":"miri64\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,miri64\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,authmillenon\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,OTAkeys\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,authmillenon\/RIOT,miri64\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT","old_file":"cpu\/esp32\/ld\/esp32.common.ld","new_file":"cpu\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* This section holds data that should not be initialized at power up\n     and will be retained during deep sleep. The section located in\n     RTC SLOW Memory area. User data marked with RTC_NOINIT_ATTR will be placed\n     into this section. See the file \"esp_attr.h\" for more information.\n  *\/\n  .rtc.noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _rtc_noinit_start = ABSOLUTE(.);\n    *(.rtc_noinit .rtc_noinit.*)\n    . = ALIGN(4) ;\n    _rtc_noinit_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  \/* If Bluetooth is not used, this DRAM section can be used as heap *\/\n  . = _data_start_btdm; \/* 0x3ffae6e0 *\/\n  . = ALIGN (4);\n  _sheap1 = ABSOLUTE(.);\n  . = 0x3ffb0000;\n  _eheap1 = ABSOLUTE(.);\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libc.a:*(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa\/*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap\/*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash\/*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core\/*(.literal .text .literal.* .text.*)\n    *littlefs\/*(.literal .text .literal.* .text.*)\n    *littlefs2\/*(.literal .text .literal.* .text.*)\n    *newlib_syscalls_default\/*(.literal .text .literal.* .text.*)\n    *spiffs_fs\/*(.literal .text .literal.* .text.*)\n    *spiffs\/*(.literal .text .literal.* .text.*)\n    *syscalls.o(.literal .text .literal.* .text.*)\n    *vfs\/*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu\/*(.literal .text .literal.* .text.*)\n    *esp_common\/*(.literal .text .literal.* .text.*)\n    *periph\/*(.literal .text .literal.* .text.*)\n    *mtd\/**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n\n    \/* IRAM can't be used as heap since it only allows 32-bit aligned access *\/\n    \/*\n    . = ALIGN (4);\n    _sheap4 = ABSOLUTE(.);\n    *\/\n  } > iram0_0_seg\n\n  \/* IRAM can't be used as heap since it only allows 32-bit aligned access *\/\n  \/*\n  . = 0x400a0000;\n  _eheap4 = ABSOLUTE(.);\n  *\/\n\n  \/* Starts at 0x3ffb000 if Bluetooth is not enabled, 0x3ffc0000 otherwise *\/\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* This section holds data that should not be initialized at power up.\n     The section located in Internal SRAM memory region. The macro _NOINIT\n     can be used as attribute to place data into this section.\n     See the esp_attr.h file for more information.\n  *\/\n  .noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _noinit_start = ABSOLUTE(.);\n    __noinit_start = ABSOLUTE(.);\n    *(.noinit .noinit.*)\n    . = ALIGN(4) ;\n    _noinit_end = ABSOLUTE(.);\n    __noinit_end = ABSOLUTE(.);\n  } > dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* Reserved ROM\/ETS data start at 0x3ffe000. *\/\n  . = 0x3ffe0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  \/* Reserved ROM\/ETS data region for PRO CPU: 0x3ffe0000 ... 0x3ffe440 *\/\n  . = 0x3ffe0440;\n  _sheap2 = ABSOLUTE(.);\n  . = 0x3ffe4000;\n  _eheap2 = ABSOLUTE(.);\n\n  \/* Reserved ROM\/ETS data region for APP CPU: 0x3ffe4000 ... 0x3ffe4350 *\/\n  . = 0x3ffe4350;\n  _sheap3 = ABSOLUTE(.);\n  . = 0x40000000;\n  _eheap3 = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* This section holds data that should not be initialized at power up\n     and will be retained during deep sleep. The section located in\n     RTC SLOW Memory area. User data marked with RTC_NOINIT_ATTR will be placed\n     into this section. See the file \"esp_attr.h\" for more information.\n  *\/\n  .rtc.noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _rtc_noinit_start = ABSOLUTE(.);\n    *(.rtc_noinit .rtc_noinit.*)\n    . = ALIGN(4) ;\n    _rtc_noinit_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  \/* If Bluetooth is not used, this DRAM section can be used as heap *\/\n  . = _data_start_btdm; \/* 0x3ffae6e0 *\/\n  . = ALIGN (4);\n  _sheap1 = ABSOLUTE(.);\n  . = 0x3ffb0000;\n  _eheap1 = ABSOLUTE(.);\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libc.a:*(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *littlefs.a:*(.literal .text .literal.* .text.*)\n    *littlefs2.a:*(.literal .text .literal.* .text.*)\n    *newlib_syscalls_default.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *syscalls.o(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *esp_common.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n\n    \/* IRAM can't be used as heap since it only allows 32-bit aligned access *\/\n    \/*\n    . = ALIGN (4);\n    _sheap4 = ABSOLUTE(.);\n    *\/\n  } > iram0_0_seg\n\n  \/* IRAM can't be used as heap since it only allows 32-bit aligned access *\/\n  \/*\n  . = 0x400a0000;\n  _eheap4 = ABSOLUTE(.);\n  *\/\n\n  \/* Starts at 0x3ffb000 if Bluetooth is not enabled, 0x3ffc0000 otherwise *\/\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* This section holds data that should not be initialized at power up.\n     The section located in Internal SRAM memory region. The macro _NOINIT\n     can be used as attribute to place data into this section.\n     See the esp_attr.h file for more information.\n  *\/\n  .noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _noinit_start = ABSOLUTE(.);\n    __noinit_start = ABSOLUTE(.);\n    *(.noinit .noinit.*)\n    . = ALIGN(4) ;\n    _noinit_end = ABSOLUTE(.);\n    __noinit_end = ABSOLUTE(.);\n  } > dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* Reserved ROM\/ETS data start at 0x3ffe000. *\/\n  . = 0x3ffe0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  \/* Reserved ROM\/ETS data region for PRO CPU: 0x3ffe0000 ... 0x3ffe440 *\/\n  . = 0x3ffe0440;\n  _sheap2 = ABSOLUTE(.);\n  . = 0x3ffe4000;\n  _eheap2 = ABSOLUTE(.);\n\n  \/* Reserved ROM\/ETS data region for APP CPU: 0x3ffe4000 ... 0x3ffe4350 *\/\n  . = 0x3ffe4350;\n  _sheap3 = ABSOLUTE(.);\n  . = 0x40000000;\n  _eheap3 = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"7e9b8bf535b1a8d160ffe3e865eb07f6cac5a07b","subject":"Set .sbss alignment to page size (#165)","message":"Set .sbss alignment to page size (#165)\n\n","repos":"rafalcieslak\/mimiker,cahirwpz\/mimiker,cahirwpz\/mimiker,cahirwpz\/wifire-os,czapiga\/mimiker,czapiga\/mimiker,czapiga\/mimiker,czapiga\/mimiker,rafalcieslak\/mimiker,dyniec\/mimiker,rafalcieslak\/mimiker,cahirwpz\/mimiker,rafalcieslak\/mimiker,cahirwpz\/mimiker,dyniec\/mimiker,dyniec\/mimiker,dyniec\/mimiker","old_file":"user\/mimiker.ld","new_file":"user\/mimiker.ld","new_contents":"OUTPUT_ARCH(mips)\nENTRY(_start)\n\nPHDRS\n{\n    text   PT_LOAD FLAGS(5); \/* read-only, executable *\/\n    data   PT_LOAD FLAGS(6); \/* read-write *\/\n    rodata PT_LOAD FLAGS(4); \/* read-only *\/\n    sdata  PT_LOAD FLAGS(6); \/* read-write *\/\n    bss    PT_LOAD FLAGS(6); \/* read-write *\/\n    sbss   PT_LOAD FLAGS(6); \/* read-write *\/\n}\nSECTIONS\n{\n    .text 0x00400000 :\n    {\n        *(.text .text.*)\n        . = ALIGN(4096);\n    } : text\n\n    . = ALIGN(4096);\n    .data :\n    {\n        *(.data .data.*)\n        . = ALIGN(4);\n    } : data\n\n    . = ALIGN(4096);\n    .rodata :\n    {\n        . = ALIGN(4096);\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n    } : rodata\n\n    . = ALIGN(4096);\n\n    _gp = ALIGN(16) + 0x7ff0;\n    .sdata :\n    {\n        *(.sdata .sdata.*)\n    } : sdata\n    . = ALIGN(4096);\n    .sbss :\n    {\n        *(.sbss .sbss.*)\n        *(.scommon)\n    } : sbss\n\n    . = ALIGN(4096);\n    .bss :\n    {\n        . = ALIGN(4096);\n        *(.bss .bss.*)\n        . = ALIGN(4);\n    } : bss\n\t\/DISCARD\/ :\n\t{\n\t\t*(.comment)\n\t\t*(.note)\n\t\t*(.options)\n\t\t*(.pdr)\n\t\t*(.reginfo)\n\t\t*(.gnu.attributes)\n\t\t*(.MIPS.abiflags)\n\t\t*(.MIPS.options)\n\t}\n\n}\n","old_contents":"OUTPUT_ARCH(mips)\nENTRY(_start)\n\nPHDRS\n{\n    text   PT_LOAD FLAGS(5); \/* read-only, executable *\/\n    data   PT_LOAD FLAGS(6); \/* read-write *\/\n    rodata PT_LOAD FLAGS(4); \/* read-only *\/\n    sdata  PT_LOAD FLAGS(6); \/* read-write *\/\n    bss    PT_LOAD FLAGS(6); \/* read-write *\/\n    sbss   PT_LOAD FLAGS(6); \/* read-write *\/\n}\nSECTIONS\n{\n    .text 0x00400000 :\n    {\n        *(.text .text.*)\n        . = ALIGN(4096);\n    } : text\n\n    . = ALIGN(4096);\n    .data :\n    {\n        *(.data .data.*)\n        . = ALIGN(4);\n    } : data\n\n    . = ALIGN(4096);\n    .rodata :\n    {\n        . = ALIGN(4096);\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n    } : rodata\n\n    . = ALIGN(4096);\n\n    _gp = ALIGN(16) + 0x7ff0;\n    .sdata :\n    {\n        *(.sdata .sdata.*)\n    } : sdata\n    .sbss :\n    {\n        *(.sbss .sbss.*)\n        *(.scommon)\n    } : sbss\n\n    . = ALIGN(4096);\n    .bss :\n    {\n        . = ALIGN(4096);\n        *(.bss .bss.*)\n        . = ALIGN(4);\n    } : bss\n\t\/DISCARD\/ :\n\t{\n\t\t*(.comment)\n\t\t*(.note)\n\t\t*(.options)\n\t\t*(.pdr)\n\t\t*(.reginfo)\n\t\t*(.gnu.attributes)\n\t\t*(.MIPS.abiflags)\n\t\t*(.MIPS.options)\n\t}\n\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"2e1f8090b0283a9cba4f4c9d961608ddd43ec640","subject":"linker: riscv: discard .note.GNU-stack","message":"linker: riscv: discard .note.GNU-stack\n\nSimilar to what was required for x86 in #12719 \/ PR#12752\n\nSigned-off-by: Peter Robinson <0cd2d1e82f6226d6d80917107cdcc165e1fecc43@gmail.com>\n","repos":"finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = DT_FLASH_BASE_ADDRESS, LENGTH = KB(DT_FLASH_SIZE)\n#endif\n    RAM (rwx) : ORIGIN = DT_SRAM_BASE_ADDRESS, LENGTH = KB(DT_SRAM_SIZE)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rom_end = .;\n    __data_rom_start = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(\".noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n#include <linker\/cplusplus-ram.ld>\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = DT_FLASH_BASE_ADDRESS, LENGTH = KB(DT_FLASH_SIZE)\n#endif\n    RAM (rwx) : ORIGIN = DT_SRAM_BASE_ADDRESS, LENGTH = KB(DT_SRAM_SIZE)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rom_end = .;\n    __data_rom_start = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(\".noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n#include <linker\/cplusplus-ram.ld>\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5eede3be49527d63255b894fb8effa8bc4f2dc40","subject":"Up userland max app size to 16384","message":"Up userland max app size to 16384\n\nSo, there's an issue here that demands more thought. Now that processes\ncan be any size, there's not a great way to check at compile time what the\nlimit on process size should be.\n\nIn theory, we could up this to be any size and only detect at load time that\nthings don't fit. In practice, that kinda sucks.\n\nThe process size commits up'd the heap from 1K to 2K by default, which caused\nsome of the bigger apps not to fit in 8K. Unclear what the best defaults for\nall that stuff is either. This whole area demands more exploration.\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(_start)\n\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 0x00080000\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 0x00004000\n}\n\nSECTIONS {\n\/* Load information, used by runtime to load app *\/\n    .load_info :\n    {\n        KEEP(*(.load_info))\n    } > FLASH =0xFF\n\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n    } > FLASH =0xFF\n\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n    .stack :\n    {\n        _stack = .;\n        KEEP(*(.stack*))\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        KEEP(*(.app_heap*))\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        KEEP(*(.kernel_heap*))\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n}\n","old_contents":"ENTRY(_start)\n\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 0x00080000\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 0x00002000\n}\n\nSECTIONS {\n\/* Load information, used by runtime to load app *\/\n    .load_info :\n    {\n        KEEP(*(.load_info))\n    } > FLASH =0xFF\n\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n    } > FLASH =0xFF\n\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n    .stack :\n    {\n        _stack = .;\n        KEEP(*(.stack*))\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        KEEP(*(.app_heap*))\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        KEEP(*(.kernel_heap*))\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5e8b584a5fcba8dbc10068d246f09f93a4e0e873","subject":"Discard dynamic sections","message":"Discard dynamic sections\n","repos":"Mrokkk\/objective-kernel,Mrokkk\/objective-kernel","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(_start)\n\n__kernel_phys = 0x00100000;\n__kernel_virt = 0xC0100000;\n\n__kernel_offset = __kernel_virt - __kernel_phys;\n\nSECTIONS {\n\n    . = __kernel_phys;\n\n    .unpagged BLOCK(4K) : ALIGN(4K) {\n        __unpagged_start = .;\n        KEEP(*(.multiboot))\n        KEEP(*(.boot))\n        *multiboot[1-2].cpp.o(.rodata)\n        __unpagged_end = .;\n    }\n\n    . += __kernel_offset;\n\n    . = ALIGN(4K);\n    .text BLOCK(4K) : AT(ADDR(.text) - __kernel_offset) {\n        __text_start = .;\n        *(.text*)\n        *(.gnu.linkonce.*)\n        __text_end = .;\n    }\n\n    . = ALIGN(4K);\n    .rodata BLOCK(4K) : AT(ADDR(.rodata) - __kernel_offset) {\n        KEEP (*(.rodata*))\n    }\n\n    . = ALIGN(4);\n    .preinit_array : AT(ADDR(.preinit_array) - __kernel_offset) {\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP (*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n    }\n\n    . = ALIGN(4);\n    .init_array : AT(ADDR(.init_array) - __kernel_offset) {\n        __init_array_start = .;\n        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n        KEEP (*(.init_array .ctors))\n        __init_array_end = .;\n    }\n\n    . = ALIGN(4K);\n    .data BLOCK(4K) : AT(ADDR(.data) - __kernel_offset) {\n        __data_start = .;\n        KEEP (*(.data))\n        KEEP (*(.data.*))\n        __data_end = .;\n    }\n\n    . = ALIGN(4K);\n    .bss BLOCK(4K) : AT(ADDR(.bss) - __kernel_offset) {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss*)\n        __bss_end = .;\n    }\n\n    . = ALIGN(4K);\n\n    __heap_start = .;\n\n    \/DISCARD\/ : {\n        *(.dynamic)\n        *(.gnu.hash)\n        *(.dynstr)\n        *(.dynsym)\n        *(.eh_frame)\n        *(.note)\n        *(.comment)\n    }\n}\n\n","old_contents":"ENTRY(_start)\n\n__kernel_phys = 0x00100000;\n__kernel_virt = 0xC0100000;\n\n__kernel_offset = __kernel_virt - __kernel_phys;\n\nSECTIONS {\n\n    . = __kernel_phys;\n\n    .unpagged BLOCK(4K) : ALIGN(4K) {\n        __unpagged_start = .;\n        KEEP(*(.multiboot))\n        KEEP(*(.boot))\n        *multiboot[1-2].cpp.o(.rodata)\n        __unpagged_end = .;\n    }\n\n    . += __kernel_offset;\n\n    . = ALIGN(4K);\n    .text BLOCK(4K) : AT(ADDR(.text) - __kernel_offset) {\n        __text_start = .;\n        *(.text*)\n        *(.gnu.linkonce.*)\n        __text_end = .;\n    }\n\n    . = ALIGN(4K);\n    .rodata BLOCK(4K) : AT(ADDR(.rodata) - __kernel_offset) {\n        KEEP (*(.rodata*))\n    }\n\n    . = ALIGN(4);\n    .preinit_array : AT(ADDR(.preinit_array) - __kernel_offset) {\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP (*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n    }\n\n    . = ALIGN(4);\n    .init_array : AT(ADDR(.init_array) - __kernel_offset) {\n        __init_array_start = .;\n        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n        KEEP (*(.init_array .ctors))\n        __init_array_end = .;\n    }\n\n    . = ALIGN(4K);\n    .data BLOCK(4K) : AT(ADDR(.data) - __kernel_offset) {\n        __data_start = .;\n        KEEP (*(.data))\n        KEEP (*(.data.*))\n        __data_end = .;\n    }\n\n    . = ALIGN(4K);\n    .bss BLOCK(4K) : AT(ADDR(.bss) - __kernel_offset) {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss*)\n        __bss_end = .;\n    }\n\n    . = ALIGN(4K);\n\n    __heap_start = .;\n\n    \/DISCARD\/ : {\n        \/**(.dynstr)*\/\n        \/**(.dynsym)*\/\n        *(.eh_frame)\n        *(.note)\n        *(.comment)\n    }\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"475ac5a3496b5e434ab95f806e1505bc82d36143","subject":"pw_boot_cortex_m: Fix nobits sections in lld","message":"pw_boot_cortex_m: Fix nobits sections in lld\n\nFixes an issue with lld failing to mark .zero_init_ram and .heap as\nnobits sections by marking them (NOLOAD).\n\nThis is necessary because lld intentionally interprets the linker file\ndifferently from ld:\nhttps:\/\/discourse.llvm.org\/t\/lld-vs-ld-section-type-progbits-vs-nobits\/5999\/3\n\nChange-Id: I7ba668b88b9815ac3b12fbd280bc913d325fb312\nReviewed-on: https:\/\/pigweed-review.googlesource.com\/c\/pigweed\/pigweed\/+\/106835\nReviewed-by: Armando Montanez <97ef6fdb231c129ac8827d9f0c4106bfbf57f74f@google.com>\nPigweed-Auto-Submit: Armando Montanez <97ef6fdb231c129ac8827d9f0c4106bfbf57f74f@google.com>\nCommit-Queue: Auto-Submit <14637eda5603879df170705285bf30f5996692f0@pigweed.google.com.iam.gserviceaccount.com>\n","repos":"google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed","old_file":"pw_boot_cortex_m\/basic_cortex_m.ld","new_file":"pw_boot_cortex_m\/basic_cortex_m.ld","new_contents":"\/*\n * Copyright 2020 The Pigweed Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\"); you may not\n * use this file except in compliance with the License. You may obtain a copy of\n * the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n * License for the specific language governing permissions and limitations under\n * the License.\n *\/\n\n\/* This relatively simplified linker script will work with many ARMv7-M and\n * ARMv8-M cores that have on-board memory-mapped RAM and FLASH. For more\n * complex projects and devices, it's possible this linker script will not be\n * sufficient as-is.\n *\n * This linker script is likely not suitable for a project with a bootloader.\n *\/\n\n\/* Provide useful error messages when required configurations are not set. *\/\n#ifndef PW_BOOT_VECTOR_TABLE_BEGIN\n#error \"PW_BOOT_VECTOR_TABLE_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_BEGIN\n\n#ifndef PW_BOOT_VECTOR_TABLE_SIZE\n#error \"PW_BOOT_VECTOR_TABLE_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_SIZE\n\n#ifndef PW_BOOT_FLASH_BEGIN\n#error \"PW_BOOT_FLASH_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_BEGIN\n\n#ifndef PW_BOOT_FLASH_SIZE\n#error \"PW_BOOT_FLASH_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_SIZE\n\n#ifndef PW_BOOT_RAM_BEGIN\n#error \"PW_BOOT_RAM_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_BEGIN\n\n#ifndef PW_BOOT_RAM_SIZE\n#error \"PW_BOOT_RAM_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_SIZE\n\n#ifndef PW_BOOT_HEAP_SIZE\n#error \"PW_BOOT_HEAP_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_HEAP_SIZE\n\n#ifndef PW_BOOT_MIN_STACK_SIZE\n#error \"PW_BOOT_MIN_STACK_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_MIN_STACK_SIZE\n\n\n\/* Note: This technically doesn't set the firmware's entry point. Setting the\n *       firmware entry point is done by setting vector_table[1]\n *       (Reset_Handler). However, this DOES tell the compiler how to optimize\n *       when --gc-sections is enabled.\n *\/\nENTRY(pw_boot_Entry)\n\nMEMORY\n{\n  \/* TODO(b\/234892223): Make it possible for projects to freely customize\n   * memory regions.\n   *\/\n\n  \/* Vector Table (typically in flash) *\/\n  VECTOR_TABLE(rx) : \\\n    ORIGIN = PW_BOOT_VECTOR_TABLE_BEGIN, \\\n    LENGTH = PW_BOOT_VECTOR_TABLE_SIZE\n  \/* Internal Flash *\/\n  FLASH(rx) : \\\n    ORIGIN = PW_BOOT_FLASH_BEGIN, \\\n    LENGTH = PW_BOOT_FLASH_SIZE\n  \/* Internal SRAM *\/\n  RAM(rwx) : \\\n    ORIGIN = PW_BOOT_RAM_BEGIN, \\\n    LENGTH = PW_BOOT_RAM_SIZE\n}\n\nSECTIONS\n{\n  \/* This is the link-time vector table. If used, the VTOR (Vector Table Offset\n   * Register) MUST point to this memory location in order to be used. This can\n   * be done by ensuring this section exists at the default location of the VTOR\n   * so it's used on reset, or by explicitly setting the VTOR in a bootloader\n   * manually to point to &pw_boot_vector_table_addr before interrupts are enabled.\n   *\/\n  .vector_table : ALIGN(512)\n  {\n    pw_boot_vector_table_addr = .;\n    KEEP(*(.vector_table))\n  } >VECTOR_TABLE\n\n  \/* Main executable code. *\/\n  .code : ALIGN(8)\n  {\n    . = ALIGN(8);\n    \/* Application code. *\/\n    *(.text)\n    *(.text*)\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    . = ALIGN(8);\n    \/* Constants.*\/\n    *(.rodata)\n    *(.rodata*)\n\n    \/* .preinit_array, .init_array, .fini_array are used by libc.\n     * Each section is a list of function pointers that are called pre-main and\n     * post-exit for object initialization and tear-down.\n     * Since the region isn't explicitly referenced, specify KEEP to prevent\n     * link-time garbage collection. SORT is used for sections that have strict\n     * init\/de-init ordering requirements. *\/\n    . = ALIGN(8);\n    PROVIDE_HIDDEN(__preinit_array_start = .);\n    KEEP(*(.preinit_array*))\n    PROVIDE_HIDDEN(__preinit_array_end = .);\n\n    PROVIDE_HIDDEN(__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array*))\n    PROVIDE_HIDDEN(__init_array_end = .);\n\n    PROVIDE_HIDDEN(__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array*))\n    PROVIDE_HIDDEN(__fini_array_end = .);\n  } >FLASH\n\n  \/* Used by unwind-arm\/ *\/\n  .ARM : ALIGN(8) {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  \/* Explicitly initialized global and static data. (.data)*\/\n  .static_init_ram : ALIGN(8)\n  {\n    *(.data)\n    *(.data*)\n    . = ALIGN(8);\n  } >RAM AT> FLASH\n\n  \/* Zero initialized global\/static data. (.bss)\n   * This section is zero initialized in pw_boot_Entry(). *\/\n  .zero_init_ram (NOLOAD) : ALIGN(8)\n  {\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(8);\n  } >RAM\n\n  .heap (NOLOAD) : ALIGN(8)\n  {\n    pw_boot_heap_low_addr = .;\n    . = . + PW_BOOT_HEAP_SIZE;\n    . = ALIGN(8);\n    pw_boot_heap_high_addr = .;\n  } >RAM\n\n  \/* Link-time check for stack overlaps. *\/\n  .stack (NOLOAD) : ALIGN(8)\n  {\n    \/* Set the address that the main stack pointer should be initialized to. *\/\n    pw_boot_stack_low_addr = .;\n    HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);\n    \/* Align the stack to a lower address to ensure it isn't out of range. *\/\n    HIDDEN(_stack_high = (. + _stack_size) & ~0x7);\n    ASSERT(_stack_high - . >= PW_BOOT_MIN_STACK_SIZE,\n           \"Error: Not enough RAM for desired minimum stack size.\");\n    . = _stack_high;\n    pw_boot_stack_high_addr = .;\n  } >RAM\n\n  \/* Discard unwind info. *\/\n  .ARM.extab 0x0 (INFO) :\n  {\n    KEEP(*(.ARM.extab*))\n  }\n\n  \/* The unused_space symbols do not currently work in clang\/lld and result in\n   * binary bloat by several orders of magnitude. Allow disabling them until a\n   * proper workaround is in place.\n   *\/\n  #if !PW_BOOT_WORKAROUND_DISABLE_UNUSED_SPACE\n  \/*\n   * Do not declare any output sections after this comment. This area is\n   * reserved only for declaring unused sections of memory. These sections are\n   * used by pw_bloat.bloaty_config to create the utilization data source for\n   * bloaty.\n   *\/\n  .VECTOR_TABLE.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(VECTOR_TABLE) + LENGTH(VECTOR_TABLE));\n  } >VECTOR_TABLE\n\n  .FLASH.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(FLASH) + LENGTH(FLASH));\n  } >FLASH\n\n  .RAM.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(RAM) + LENGTH(RAM));\n  } >RAM\n  #endif \/*PW_BOOT_WORKAROUND_DISABLE_UNUSED_SPACE*\/\n}\n\n\/* Symbols used by core_init.c: *\/\n\/* Start of .static_init_ram in FLASH. *\/\n_pw_static_init_flash_start = LOADADDR(.static_init_ram);\n\n\/* Region of .static_init_ram in RAM. *\/\n_pw_static_init_ram_start = ADDR(.static_init_ram);\n_pw_static_init_ram_end = _pw_static_init_ram_start + SIZEOF(.static_init_ram);\n\n\/* Region of .zero_init_ram. *\/\n_pw_zero_init_ram_start = ADDR(.zero_init_ram);\n_pw_zero_init_ram_end = _pw_zero_init_ram_start + SIZEOF(.zero_init_ram);\n\n\/* arm-none-eabi expects `end` symbol to point to start of heap for sbrk. *\/\nPROVIDE(end = _pw_zero_init_ram_end);\n\n\/* These symbols are used by pw_bloat.bloaty_config to create the memoryregions\n * data source for bloaty in this format (where the optional _N defaults to 0):\n * pw_bloat_config_memory_region_NAME_{start,end}{_N,} *\/\npw_bloat_config_memory_region_VECTOR_TABLE_start = ORIGIN(VECTOR_TABLE);\npw_bloat_config_memory_region_VECTOR_TABLE_end =\n    ORIGIN(VECTOR_TABLE) + LENGTH(VECTOR_TABLE);\npw_bloat_config_memory_region_FLASH_start = ORIGIN(FLASH);\npw_bloat_config_memory_region_FLASH_end = ORIGIN(FLASH) + LENGTH(FLASH);\npw_bloat_config_memory_region_RAM_start = ORIGIN(RAM);\npw_bloat_config_memory_region_RAM_end = ORIGIN(RAM) + LENGTH(RAM);\n","old_contents":"\/*\n * Copyright 2020 The Pigweed Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\"); you may not\n * use this file except in compliance with the License. You may obtain a copy of\n * the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n * License for the specific language governing permissions and limitations under\n * the License.\n *\/\n\n\/* This relatively simplified linker script will work with many ARMv7-M and\n * ARMv8-M cores that have on-board memory-mapped RAM and FLASH. For more\n * complex projects and devices, it's possible this linker script will not be\n * sufficient as-is.\n *\n * This linker script is likely not suitable for a project with a bootloader.\n *\/\n\n\/* Provide useful error messages when required configurations are not set. *\/\n#ifndef PW_BOOT_VECTOR_TABLE_BEGIN\n#error \"PW_BOOT_VECTOR_TABLE_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_BEGIN\n\n#ifndef PW_BOOT_VECTOR_TABLE_SIZE\n#error \"PW_BOOT_VECTOR_TABLE_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_SIZE\n\n#ifndef PW_BOOT_FLASH_BEGIN\n#error \"PW_BOOT_FLASH_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_BEGIN\n\n#ifndef PW_BOOT_FLASH_SIZE\n#error \"PW_BOOT_FLASH_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_SIZE\n\n#ifndef PW_BOOT_RAM_BEGIN\n#error \"PW_BOOT_RAM_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_BEGIN\n\n#ifndef PW_BOOT_RAM_SIZE\n#error \"PW_BOOT_RAM_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_SIZE\n\n#ifndef PW_BOOT_HEAP_SIZE\n#error \"PW_BOOT_HEAP_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_HEAP_SIZE\n\n#ifndef PW_BOOT_MIN_STACK_SIZE\n#error \"PW_BOOT_MIN_STACK_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_MIN_STACK_SIZE\n\n\n\/* Note: This technically doesn't set the firmware's entry point. Setting the\n *       firmware entry point is done by setting vector_table[1]\n *       (Reset_Handler). However, this DOES tell the compiler how to optimize\n *       when --gc-sections is enabled.\n *\/\nENTRY(pw_boot_Entry)\n\nMEMORY\n{\n  \/* TODO(b\/234892223): Make it possible for projects to freely customize\n   * memory regions.\n   *\/\n\n  \/* Vector Table (typically in flash) *\/\n  VECTOR_TABLE(rx) : \\\n    ORIGIN = PW_BOOT_VECTOR_TABLE_BEGIN, \\\n    LENGTH = PW_BOOT_VECTOR_TABLE_SIZE\n  \/* Internal Flash *\/\n  FLASH(rx) : \\\n    ORIGIN = PW_BOOT_FLASH_BEGIN, \\\n    LENGTH = PW_BOOT_FLASH_SIZE\n  \/* Internal SRAM *\/\n  RAM(rwx) : \\\n    ORIGIN = PW_BOOT_RAM_BEGIN, \\\n    LENGTH = PW_BOOT_RAM_SIZE\n}\n\nSECTIONS\n{\n  \/* This is the link-time vector table. If used, the VTOR (Vector Table Offset\n   * Register) MUST point to this memory location in order to be used. This can\n   * be done by ensuring this section exists at the default location of the VTOR\n   * so it's used on reset, or by explicitly setting the VTOR in a bootloader\n   * manually to point to &pw_boot_vector_table_addr before interrupts are enabled.\n   *\/\n  .vector_table : ALIGN(512)\n  {\n    pw_boot_vector_table_addr = .;\n    KEEP(*(.vector_table))\n  } >VECTOR_TABLE\n\n  \/* Main executable code. *\/\n  .code : ALIGN(8)\n  {\n    . = ALIGN(8);\n    \/* Application code. *\/\n    *(.text)\n    *(.text*)\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    . = ALIGN(8);\n    \/* Constants.*\/\n    *(.rodata)\n    *(.rodata*)\n\n    \/* .preinit_array, .init_array, .fini_array are used by libc.\n     * Each section is a list of function pointers that are called pre-main and\n     * post-exit for object initialization and tear-down.\n     * Since the region isn't explicitly referenced, specify KEEP to prevent\n     * link-time garbage collection. SORT is used for sections that have strict\n     * init\/de-init ordering requirements. *\/\n    . = ALIGN(8);\n    PROVIDE_HIDDEN(__preinit_array_start = .);\n    KEEP(*(.preinit_array*))\n    PROVIDE_HIDDEN(__preinit_array_end = .);\n\n    PROVIDE_HIDDEN(__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array*))\n    PROVIDE_HIDDEN(__init_array_end = .);\n\n    PROVIDE_HIDDEN(__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array*))\n    PROVIDE_HIDDEN(__fini_array_end = .);\n  } >FLASH\n\n  \/* Used by unwind-arm\/ *\/\n  .ARM : ALIGN(8) {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  \/* Explicitly initialized global and static data. (.data)*\/\n  .static_init_ram : ALIGN(8)\n  {\n    *(.data)\n    *(.data*)\n    . = ALIGN(8);\n  } >RAM AT> FLASH\n\n  \/* Zero initialized global\/static data. (.bss)\n   * This section is zero initialized in pw_boot_Entry(). *\/\n  .zero_init_ram : ALIGN(8)\n  {\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(8);\n  } >RAM\n\n  .heap : ALIGN(8)\n  {\n    pw_boot_heap_low_addr = .;\n    . = . + PW_BOOT_HEAP_SIZE;\n    . = ALIGN(8);\n    pw_boot_heap_high_addr = .;\n  } >RAM\n\n  \/* Link-time check for stack overlaps. *\/\n  .stack (NOLOAD) : ALIGN(8)\n  {\n    \/* Set the address that the main stack pointer should be initialized to. *\/\n    pw_boot_stack_low_addr = .;\n    HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);\n    \/* Align the stack to a lower address to ensure it isn't out of range. *\/\n    HIDDEN(_stack_high = (. + _stack_size) & ~0x7);\n    ASSERT(_stack_high - . >= PW_BOOT_MIN_STACK_SIZE,\n           \"Error: Not enough RAM for desired minimum stack size.\");\n    . = _stack_high;\n    pw_boot_stack_high_addr = .;\n  } >RAM\n\n  \/* Discard unwind info. *\/\n  .ARM.extab 0x0 (INFO) :\n  {\n    KEEP(*(.ARM.extab*))\n  }\n\n  \/* The unused_space symbols do not currently work in clang\/lld and result in\n   * binary bloat by several orders of magnitude. Allow disabling them until a\n   * proper workaround is in place.\n   *\/\n  #if !PW_BOOT_WORKAROUND_DISABLE_UNUSED_SPACE\n  \/*\n   * Do not declare any output sections after this comment. This area is\n   * reserved only for declaring unused sections of memory. These sections are\n   * used by pw_bloat.bloaty_config to create the utilization data source for\n   * bloaty.\n   *\/\n  .VECTOR_TABLE.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(VECTOR_TABLE) + LENGTH(VECTOR_TABLE));\n  } >VECTOR_TABLE\n\n  .FLASH.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(FLASH) + LENGTH(FLASH));\n  } >FLASH\n\n  .RAM.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(RAM) + LENGTH(RAM));\n  } >RAM\n  #endif \/*PW_BOOT_WORKAROUND_DISABLE_UNUSED_SPACE*\/\n}\n\n\/* Symbols used by core_init.c: *\/\n\/* Start of .static_init_ram in FLASH. *\/\n_pw_static_init_flash_start = LOADADDR(.static_init_ram);\n\n\/* Region of .static_init_ram in RAM. *\/\n_pw_static_init_ram_start = ADDR(.static_init_ram);\n_pw_static_init_ram_end = _pw_static_init_ram_start + SIZEOF(.static_init_ram);\n\n\/* Region of .zero_init_ram. *\/\n_pw_zero_init_ram_start = ADDR(.zero_init_ram);\n_pw_zero_init_ram_end = _pw_zero_init_ram_start + SIZEOF(.zero_init_ram);\n\n\/* arm-none-eabi expects `end` symbol to point to start of heap for sbrk. *\/\nPROVIDE(end = _pw_zero_init_ram_end);\n\n\/* These symbols are used by pw_bloat.bloaty_config to create the memoryregions\n * data source for bloaty in this format (where the optional _N defaults to 0):\n * pw_bloat_config_memory_region_NAME_{start,end}{_N,} *\/\npw_bloat_config_memory_region_VECTOR_TABLE_start = ORIGIN(VECTOR_TABLE);\npw_bloat_config_memory_region_VECTOR_TABLE_end =\n    ORIGIN(VECTOR_TABLE) + LENGTH(VECTOR_TABLE);\npw_bloat_config_memory_region_FLASH_start = ORIGIN(FLASH);\npw_bloat_config_memory_region_FLASH_end = ORIGIN(FLASH) + LENGTH(FLASH);\npw_bloat_config_memory_region_RAM_start = ORIGIN(RAM);\npw_bloat_config_memory_region_RAM_end = ORIGIN(RAM) + LENGTH(RAM);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6fc66f07a2716ce59babd03670e3f97d93c55862","subject":"Load ELF headers into memory","message":"Load ELF headers into memory\n","repos":"project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak","old_file":"experimental\/oak_baremetal_app_crosvm\/layout.ld","new_file":"experimental\/oak_baremetal_app_crosvm\/layout.ld","new_contents":"\/*\n * Copyright 2022 The Project Oak Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n*\/\n\nENTRY(_start)\n\nPHDRS\n{\n    \/* Note that the permissions flags are currently not respected. *\/\n    \/* Keep the sections here sorted from lowest memory address to largest; crosvm\n     * has a sanity check that expects the section with the lowest address to come\n     * first.\n     *\/\n    hdrs    PT_LOAD FILEHDR PHDRS FLAGS(4);\n    \/* Executable text. *\/\n    boot    PT_LOAD FLAGS(4 + 1); \/* PF_R + PF_X *\/\n    text    PT_LOAD FLAGS(4 + 1); \/* PF_R + PF_X *\/\n    \/* Read-only data. *\/\n    rodata  PT_LOAD FLAGS(4); \/* PF_R *\/\n    \/* Initialized read-write data. *\/\n    data    PT_LOAD FLAGS(4 + 2); \/* PF_R + PF_W *\/\n    \/* Uninitialized read-write data. *\/\n    bss     PT_LOAD FLAGS(4 + 2); \/* PF_R + PF_W *\/\n    \/* Special sections for SEV-SNP. *\/\n    cpuid   PT_LOAD FLAGS(1 << 23);\n    secrets PT_LOAD FLAGS(1 << 24);\n}\n\n\/* To set kernel VMA to low memory, set this to 0x0. *\/\nKERNEL_MEM_START = 0xFFFFFFFF80000000;\n\nSECTIONS {\n    \/* Don't touch the lower 2M of memory; there be dragons there. *\/\n    . = 2M;\n\n    hdrs = .;\n    . += SIZEOF_HEADERS;\n    .hdrs : {\n    } : hdrs\n\n     \/*\n     * Boot code is executed with identity mapping; the main duty of the boot\n     * code is to set up proper page tables before jumping to the kernel proper.\n     *\/\n    .boot : ALIGN(4K) {\n        ram_min = .;\n        *(.boot)\n    } : boot\n\n    \/*\n     * Load the rest of the kernel after KERNEL_MEM_START. The idea is that the initial\n     * boot code should set map KERNEL_MEM_START to physical address 0; therefore, all\n     * VMAs will be LMA + KERNEL_MEM_START.\n     *\/\n    . += KERNEL_MEM_START;\n\n    data_start = .;\n    text_start = .;\n\n    .text ALIGN(2M) : AT(ADDR(.text) - KERNEL_MEM_START) {\n        *(.text .text.*)\n    } : text\n\n    text_end = .;\n\n    .rodata ALIGN(2M) : {\n        *(.rodata .rodata.*)\n    } : rodata\n\n    .data ALIGN(2M) : {\n        *(.data .data.*)\n    } : data\n\n    data_end = .;\n\n    .bss : ALIGN(2M) {\n        bss_start = .;\n        *(.bss .bss.*)\n        bss_size = . - bss_start;\n    } : bss\n\n    \/* Stack grows down, so stack_start is the upper address in memory. *\/\n    .stack (NOLOAD) : ALIGN(2M) {\n        . += 512K;\n    } : bss\n    stack_start = .;\n\n    .cpuid (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : cpuid\n\n    .secrets (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : secrets\n\n    \/DISCARD\/ : {\n        *(.eh_frame*)\n    }\n}\n","old_contents":"\/*\n * Copyright 2022 The Project Oak Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n*\/\n\nENTRY(_start)\n\nPHDRS\n{\n    \/* Note that the permissions flags are currently not respected. *\/\n    \/* Keep the sections here sorted from lowest memory address to largest; crosvm\n     * has a sanity check that expects the section with the lowest address to come\n     * first.\n     *\/\n    \/* Executable text. *\/\n    boot    PT_LOAD FLAGS(4 + 1); \/* PF_R + PF_X *\/\n    text    PT_LOAD FLAGS(4 + 1); \/* PF_R + PF_X *\/\n    \/* Read-only data. *\/\n    rodata  PT_LOAD FLAGS(4); \/* PF_R *\/\n    \/* Initialized read-write data. *\/\n    data    PT_LOAD FLAGS(4 + 2); \/* PF_R + PF_W *\/\n    \/* Uninitialized read-write data. *\/\n    bss     PT_LOAD FLAGS(4 + 2); \/* PF_R + PF_W *\/\n    \/* Special sections for SEV-SNP. *\/\n    cpuid   PT_LOAD FLAGS(1 << 23);\n    secrets PT_LOAD FLAGS(1 << 24);\n}\n\n\/* To set kernel VMA to low memory, set this to 0x0. *\/\nKERNEL_MEM_START = 0xFFFFFFFF80000000;\n\nSECTIONS {\n    \/*\n     * Boot code is executed with identity mapping; the main duty of the boot\n     * code is to set up proper page tables before jumping to the kernel proper.\n     * We place that at 2M (both virtual and physical)\n     *\/\n    .boot 0x200000 : {\n        ram_min = .;\n        *(.boot)\n    } : boot\n\n    \/*\n     * Load the rest of the kernel after KERNEL_MEM_START. The idea is that the initial\n     * boot code should set map KERNEL_MEM_START to physical address 0; therefore, all\n     * VMAs will be LMA + KERNEL_MEM_START.\n     *\/\n    . += KERNEL_MEM_START;\n\n    data_start = .;\n    text_start = .;\n\n    .text ALIGN(2M) : AT(ADDR(.text) - KERNEL_MEM_START) {\n        *(.text .text.*)\n    } : text\n\n    text_end = .;\n\n    .rodata ALIGN(2M) : {\n        *(.rodata .rodata.*)\n    } : rodata\n\n    .data ALIGN(2M) : {\n        *(.data .data.*)\n    } : data\n\n    data_end = .;\n\n    .bss : ALIGN(2M) {\n        bss_start = .;\n        *(.bss .bss.*)\n        bss_size = . - bss_start;\n    } : bss\n\n    \/* Stack grows down, so stack_start is the upper address in memory. *\/\n    .stack (NOLOAD) : ALIGN(2M) {\n        . += 512K;\n    } : bss\n    stack_start = .;\n\n    .cpuid (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : cpuid\n\n    .secrets (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : secrets\n\n    \/DISCARD\/ : {\n        *(.eh_frame*)\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"67fce6593063579384d75d3f07e6c62e2456c9cf","subject":"stm32\/boards\/PYBD_SF2: Put BTstack library in external QSPI XIP flash.","message":"stm32\/boards\/PYBD_SF2: Put BTstack library in external QSPI XIP flash.\n\nIn the same way the nimble stack is put there.\n","repos":"pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython","old_file":"ports\/stm32\/boards\/PYBD_SF2\/f722_qspi.ld","new_file":"ports\/stm32\/boards\/PYBD_SF2\/f722_qspi.ld","new_contents":"\/*\n    Linker script for PYBD with STM32F722\/STM32F723\/STM32F732\/STM32F733\n\n    Memory layout for mboot configuration (this here describes the app part):\n\n    FLASH_APP   .isr_vector\n    FLASH_APP   .text\n    FLASH_APP   .data\n\n    FLASH_EXT   .big_const\n\n    RAM         .data\n    RAM         .bss\n    RAM         .heap\n    RAM         .stack\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 32K     \/* sectors 0,1 *\/\n    FLASH_APP (rx)  : ORIGIN = 0x08008000, LENGTH = 480K    \/* sectors 2-7 *\/\n    FLASH_EXT (rx)  : ORIGIN = 0x90000000, LENGTH = 2048K   \/* external QSPI *\/\n    RAM (rwx)       : ORIGIN = 0x20000000, LENGTH = 256K    \/* DTCM+SRAM1+SRAM2 *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K;\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n\nENTRY(Reset_Handler)\n\n\/* Define output sections *\/\nSECTIONS\n{\n    .text_ext :\n    {\n        . = ALIGN(4);\n        *lib\/btstack\/*(.text* .rodata*)\n        *lib\/mbedtls\/*(.text* .rodata*)\n        *lib\/mynewt-nimble\/*(.text* .rodata*)\n        . = ALIGN(512);\n        *(.big_const*)\n        . = ALIGN(4);\n    } >FLASH_EXT\n\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n    } >FLASH_APP\n\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        _etext = .;\n    } >FLASH_APP\n\n    _sidata = LOADADDR(.data);\n\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.data*)\n\n        . = ALIGN(4);\n        _edata = .;\n    } >RAM AT> FLASH_APP\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n    } >RAM\n\n    .heap :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_heap_size;\n        . = ALIGN(4);\n    } >RAM\n\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n}\n","old_contents":"\/*\n    Linker script for PYBD with STM32F722\/STM32F723\/STM32F732\/STM32F733\n\n    Memory layout for mboot configuration (this here describes the app part):\n\n    FLASH_APP   .isr_vector\n    FLASH_APP   .text\n    FLASH_APP   .data\n\n    FLASH_EXT   .big_const\n\n    RAM         .data\n    RAM         .bss\n    RAM         .heap\n    RAM         .stack\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 32K     \/* sectors 0,1 *\/\n    FLASH_APP (rx)  : ORIGIN = 0x08008000, LENGTH = 480K    \/* sectors 2-7 *\/\n    FLASH_EXT (rx)  : ORIGIN = 0x90000000, LENGTH = 2048K   \/* external QSPI *\/\n    RAM (rwx)       : ORIGIN = 0x20000000, LENGTH = 256K    \/* DTCM+SRAM1+SRAM2 *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K;\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n\nENTRY(Reset_Handler)\n\n\/* Define output sections *\/\nSECTIONS\n{\n    .text_ext :\n    {\n        . = ALIGN(4);\n        *lib\/mbedtls\/*(.text* .rodata*)\n        *lib\/mynewt-nimble\/*(.text* .rodata*)\n        . = ALIGN(512);\n        *(.big_const*)\n        . = ALIGN(4);\n    } >FLASH_EXT\n\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n    } >FLASH_APP\n\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        _etext = .;\n    } >FLASH_APP\n\n    _sidata = LOADADDR(.data);\n\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.data*)\n\n        . = ALIGN(4);\n        _edata = .;\n    } >RAM AT> FLASH_APP\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n    } >RAM\n\n    .heap :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_heap_size;\n        . = ALIGN(4);\n    } >RAM\n\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"55e5bdfc6cb28fa79f94953f292f66b38804fc67","subject":"Move 64-bit integer division and modulo functions into flash","message":"Move 64-bit integer division and modulo functions into flash\n\nSaves another 1819 bytes of IRAM (may help with #1582)\n","repos":"Juppit\/Arduino,Juppit\/Arduino,quertenmont\/Arduino,sticilface\/Arduino,Lan-Hekary\/Arduino,Adam5Wu\/Arduino,quertenmont\/Arduino,me-no-dev\/Arduino,KaloNK\/Arduino,Adam5Wu\/Arduino,wemos\/Arduino,jes\/Arduino,martinayotte\/ESP8266-Arduino,NullMedia\/Arduino,hallard\/Arduino,Adam5Wu\/Arduino,martinayotte\/ESP8266-Arduino,lrmoreno007\/Arduino,jes\/Arduino,toastedcode\/esp8266-Arduino,NextDevBoard\/Arduino,sticilface\/Arduino,gguuss\/Arduino,toastedcode\/esp8266-Arduino,jes\/Arduino,wemos\/Arduino,esp8266\/Arduino,sticilface\/Arduino,quertenmont\/Arduino,NextDevBoard\/Arduino,Links2004\/Arduino,toastedcode\/esp8266-Arduino,Lan-Hekary\/Arduino,NullMedia\/Arduino,lrmoreno007\/Arduino,KaloNK\/Arduino,lrmoreno007\/Arduino,esp8266\/Arduino,Links2004\/Arduino,gguuss\/Arduino,martinayotte\/ESP8266-Arduino,Juppit\/Arduino,martinayotte\/ESP8266-Arduino,Adam5Wu\/Arduino,sticilface\/Arduino,gguuss\/Arduino,NextDevBoard\/Arduino,toastedcode\/esp8266-Arduino,NullMedia\/Arduino,me-no-dev\/Arduino,esp8266\/Arduino,KaloNK\/Arduino,wemos\/Arduino,me-no-dev\/Arduino,NullMedia\/Arduino,Lan-Hekary\/Arduino,Adam5Wu\/Arduino,Links2004\/Arduino,NextDevBoard\/Arduino,lrmoreno007\/Arduino,hallard\/Arduino,hallard\/Arduino,hallard\/Arduino,esp8266\/Arduino,Juppit\/Arduino,NextDevBoard\/Arduino,KaloNK\/Arduino,me-no-dev\/Arduino,Juppit\/Arduino,KaloNK\/Arduino,me-no-dev\/Arduino,toastedcode\/esp8266-Arduino,wemos\/Arduino,jes\/Arduino,martinayotte\/ESP8266-Arduino,Lan-Hekary\/Arduino,quertenmont\/Arduino,hallard\/Arduino,gguuss\/Arduino,lrmoreno007\/Arduino,NullMedia\/Arduino,sticilface\/Arduino,Links2004\/Arduino,Links2004\/Arduino,quertenmont\/Arduino,jes\/Arduino,gguuss\/Arduino,Lan-Hekary\/Arduino,wemos\/Arduino,esp8266\/Arduino","old_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"8d333174d50963e6c10851de51d04291844cdf81","subject":"Ensure sections in ROM are 32-bit aligned","message":"Ensure sections in ROM are 32-bit aligned\n","repos":"zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder","old_file":"include\/xtensa\/esp8266\/ld\/eagle.app.v6.common.ld","new_file":"include\/xtensa\/esp8266\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n  \t_UserExceptionVector_literal_start = ABSOLUTE(.);\n  \t*(.UserExceptionVector.literal)\n  \t_UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/* These must be located in internal RAM to prevent far accesses to literal data.\n     *  All of the following libraries are distributed in binary form, so we cannot\n     *  change the compilation options to allow for far accesses to data. *\/\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libmain.a:(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libhal.a:int_asm--set_intclear.o(.literal .text .literal.* .text.*)\n    *libnet80211.a:wl_chm.o(.literal .text .literal.* .text.*)\n\n    \/* Arduino necessities *\/\n    *libarduino_core.a:*umm_malloc.o(.literal* .text*)\n    *libarduino_core.a:*cont.o(.literal* .text*)\n\n    *(.gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n\n    \/* Any compilation units that request to be located in interal RAM *\/\n    *.o(.iram.text)\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *.a(.literal*)\n    *.o(.literal*)\n    *.a(.text*)\n    *.o(.text*)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n\n    . = ALIGN (4);\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .irom0.other : ALIGN(4) SUBALIGN(4)\n  {\n    _irom0_other_start = ABSOLUTE(.);\n    *.bin.o(*)\n    . = ALIGN (4);\n    _irom0_other_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n  \t_UserExceptionVector_literal_start = ABSOLUTE(.);\n  \t*(.UserExceptionVector.literal)\n  \t_UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/* These must be located in internal RAM to prevent far accesses to literal data.\n     *  All of the following libraries are distributed in binary form, so we cannot\n     *  change the compilation options to allow for far accesses to data. *\/\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libmain.a:(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libhal.a:int_asm--set_intclear.o(.literal .text .literal.* .text.*)\n    *libnet80211.a:wl_chm.o(.literal .text .literal.* .text.*)\n\n    \/* Arduino necessities *\/\n    *libarduino_core.a:*umm_malloc.o(.literal* .text*)\n    *libarduino_core.a:*cont.o(.literal* .text*)\n\n    *(.gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n\n    \/* Any compilation units that request to be located in interal RAM *\/\n    *.o(.iram.text)\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *.a(.literal*)\n    *.o(.literal*)\n    *.a(.text*)\n    *.o(.text*)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .irom0.other : ALIGN(4) SUBALIGN(4)\n  {\n    _irom0_other_start = ABSOLUTE(.);\n    *.bin.o(*)\n    _irom0_other_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"17cda2782ed114118cea616098f77398c320a675","subject":"remove unused comment","message":"remove unused comment\n","repos":"freem\/hyperball,freem\/hyperball","old_file":"src_68k\/linkscript.ld","new_file":"src_68k\/linkscript.ld","new_contents":"\/* quick dumb m68k linker script *\/\n\nMEMORY\n{\n\theader68k : ORIGIN = 0x00000000, LENGTH = 0x00000100\n\trom : ORIGIN = 0x00000100, LENGTH = 0x0007FF00\n\tram : ORIGIN = 0x00100000, LENGTH = 0x0000F300 \/* $100000-$10F2FF (62208 bytes) *\/\n}\n\nSECTIONS\n{\n\t.header68k : { *(header68k) } > header68k\n\t.code : { *(code) } > rom\n\t.bss (NOLOAD) : { *(bss) } > ram\n\t.data : { *(data) } > ram AT> rom\n}\n","old_contents":"\/* quick dumb m68k linker script *\/\n\nMEMORY\n{\n\t\/*rom : ORIGIN = 0x00000000, LENGTH = 0x00080000*\/\n\theader68k: ORIGIN = 0x00000000, LENGTH = 0x00000100\n\trom : ORIGIN = 0x00000100, LENGTH = 0x0007FF00\n\tram : ORIGIN = 0x00100000, LENGTH = 0x0000F300 \/* $100000-$10F2FF (62208 bytes) *\/\n}\n\nSECTIONS\n{\n\t.header68k : { *(header68k) } > header68k\n\t.code : { *(code) } > rom\n\t.bss (NOLOAD) : { *(bss) } > ram\n\t.data : { *(data) } > ram AT> rom\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ec498ad86d0980fa2fc00179b239043095001a6a","subject":"libgcc: Place assembly functions (including __xtensa_libgcc_window_spill) in IRAM","message":"libgcc: Place assembly functions (including __xtensa_libgcc_window_spill) in IRAM\n","repos":"www220\/esp-idf,Hermiedapwdrman\/esp-idf,MIhanguangyi\/esp-idf,ajs124\/esp-idf,jaracil\/esp-idf,ajs124\/esp-idf,shukyisme\/esp-idf-kwik,MIhanguangyi\/esp-idf,jaracil\/esp-idf,Hermiedapwdrman\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf,Hermiedapwdrman\/esp-idf,shukyisme\/esp-idf-kwik,www220\/esp-idf,mashaoze\/esp-idf,empoweredhomes\/esp-idf,shukyisme\/esp-idf-kwik,Hermiedapwdrman\/esp-idf,empoweredhomes\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,MIhanguangyi\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf,nineisk\/esp-idf,www220\/esp-idf,www220\/esp-idf,empoweredhomes\/esp-idf,www220\/esp-idf,ajs124\/esp-idf,Hermiedapwdrman\/esp-idf,jaracil\/esp-idf,nineisk\/esp-idf,jaracil\/esp-idf,armada-ai\/esp-idf,nineisk\/esp-idf,espressif\/esp-idf,shukyisme\/esp-idf-kwik,shukyisme\/esp-idf-kwik,armada-ai\/esp-idf,nineisk\/esp-idf,MIhanguangyi\/esp-idf,ajs124\/esp-idf,empoweredhomes\/esp-idf,MIhanguangyi\/esp-idf,empoweredhomes\/esp-idf,espressif\/esp-idf,armada-ai\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap.o(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap_poisoning.o(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libapp_trace.a:(.literal .text .literal.* .text.*)\n    *libxtensa-debug-module.a:eri.o(.literal .text .literal.* .text.*)\n    *libesp32.a:app_trace.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap.o(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap_poisoning.o(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libapp_trace.a:(.literal .text .literal.* .text.*)\n    *libxtensa-debug-module.a:eri.o(.literal .text .literal.* .text.*)\n    *libesp32.a:app_trace.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ce84eb5e51b25770edb1e550d2ac2713cfc59438","subject":"Don't need this file, it's already in the ld_scripts","message":"Don't need this file, it's already in the ld_scripts\n","repos":"karlp\/kkstm32_base","old_file":"example\/32l_lcd\/generic_sections_flash.ld","new_file":"example\/32l_lcd\/generic_sections_flash.ld","new_contents":"","old_contents":"\/**\n * Karl Palsson, 2011\n * Considered to be released into the public domain\n *\n * Generic \"boot from flash\" linker script.\n *\n * This file simply defines how sections should get written.\n * You should INCLUDE this file from another file, that specifies the\n * memory map for the part you are using.\n *\/\n\nSECTIONS\n{\n    . = ORIGIN(FLASH);\n    .text :\n    {\n        *(.vectors)    \/* Vector table *\/\n        *(.text)      \/* Program code *\/\n        *(.rodata)    \/* Read only data *\/\n        *(.rodata*)\n        __text_end = .;\n    } >FLASH\n\n    \/*\n     * This is the initialized data section\n     * The program executes knowing that the data is in the RAM\n     * but the loader puts the initial values in the FLASH (inidata).\n     * One task of \"startup\" is to copy the initial values from FLASH to RAM.\n     *\/\n    .data :\n    {\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        PROVIDE (__data_start = .);\n        *(.data)\n        *(.data.*)\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        PROVIDE (__data_end = .);\n    } >RAM AT >FLASH\n\n\n    .bss :\n    {\n        PROVIDE(__bss_start = .);\n        *(.bss)\n        *(COMMON)\n        . = ALIGN(4);\n        PROVIDE(__bss_end = .);\n    } >RAM\n\n    . = ALIGN(4);\n\n    _stack_start = .;\n\n}\n\n_end = .;\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"06b87bc82c3720268907dec3db6a1d5af8efb7af","subject":"kernelremap\/src\/arch\/x86_64\/linker.ld: fix indentation","message":"kernelremap\/src\/arch\/x86_64\/linker.ld: fix indentation\n","repos":"makiftasova\/rustKernel","old_file":"kernelremap\/src\/arch\/x86_64\/linker.ld","new_file":"kernelremap\/src\/arch\/x86_64\/linker.ld","new_contents":"ENTRY(start)\n\nSECTIONS\n{\n\t. = 1M;\n\n\t.rodata :\n\t{\n\t\t\/* ensure that the multiboot header is at the beginning *\/\n\t\tKEEP(*(.multiboot_header))\n\t\t*(.rodata .rodata.*)\n\t\t. = ALIGN(4K);\n\t}\n\n\t.text :\n\t{\n\t\t*(.text .text.*)\n\t\t. = ALIGN(4K);\n\t}\n\n\t.data :\n\t{\n\t\t*(.data .data.*)\n\t\t. = ALIGN(4K);\n\t}\n\n\t.bss :\n\t{\n\t\t*(.bss .bss.*)\n\t\t. = ALIGN(4K);\n\t}\n\n\t.got :\n\t{\n\t\t*(.got)\n\t\t. = ALIGN(4K);\n\t}\n\n\t.got.plt :\n\t{\n\t\t*(.got.plt)\n\t\t. = ALIGN(4K);\n\t}\n\n\t.data.rel.ro : ALIGN(4K) \n\t{\n\t\t*(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n\t\t. = ALIGN(4K);\n\t}\n\n\t.gcc_except_table : ALIGN(4K) \n\t{\n\t\t*(.gcc_except_table)\n\t\t. = ALIGN(4K);\n\t}\n}\n","old_contents":"ENTRY(start)\n\nSECTIONS {\n  . = 1M;\n\n  .rodata :\n  {\n    \/* ensure that the multiboot header is at the beginning *\/\n    KEEP(*(.multiboot_header))\n    *(.rodata .rodata.*)\n    . = ALIGN(4K);\n  }\n\n  .text :\n  {\n    *(.text .text.*)\n    . = ALIGN(4K);\n  }\n\n  .data :\n  {\n    *(.data .data.*)\n    . = ALIGN(4K);\n  }\n\n  .bss :\n  {\n    *(.bss .bss.*)\n    . = ALIGN(4K);\n  }\n\n  .got :\n  {\n    *(.got)\n    . = ALIGN(4K);\n  }\n\n  .got.plt :\n  {\n    *(.got.plt)\n    . = ALIGN(4K);\n  }\n\n  .data.rel.ro : ALIGN(4K) {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n    . = ALIGN(4K);\n  }\n\n  .gcc_except_table : ALIGN(4K) {\n    *(.gcc_except_table)\n    . = ALIGN(4K);\n  }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f1260fb6186f2e7f20fe2f81ffb1c8eb58457b52","subject":"arc: linker.ld: fix BSS section declaration","message":"arc: linker.ld: fix BSS section declaration\n\nThe BSS section needs to use AT> in XIP systems otherwise the LMA\naddresses in the ELF binary are wrong, leading to issues if we\ntry to manipulate the binary with objcopy. The GROUP_DATA_LINK_IN\nmacro does the right thing here.\n\nThis was already done on other arches but ARC was missed.\n\nChange-Id: I93748e919e0b68c1ff2dfb4b85b7064a8d980f3a\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"bboozzoo\/zephyr,mbolivar\/zephyr,holtmann\/zephyr,zephyrproject-rtos\/zephyr,aceofall\/zephyr-iotos,explora26\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,sharronliu\/zephyr,finikorg\/zephyr,ldts\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,zephyriot\/zephyr,bigdinotech\/zephyr,bboozzoo\/zephyr,Vudentz\/zephyr,aceofall\/zephyr-iotos,holtmann\/zephyr,GiulianoFranchetto\/zephyr,tidyjiang8\/zephyr-doc,aceofall\/zephyr-iotos,pklazy\/zephyr,tidyjiang8\/zephyr-doc,rsalveti\/zephyr,finikorg\/zephyr,erwango\/zephyr,nashif\/zephyr,galak\/zephyr,ldts\/zephyr,erwango\/zephyr,runchip\/zephyr-cc3200,pklazy\/zephyr,aceofall\/zephyr-iotos,erwango\/zephyr,explora26\/zephyr,zephyriot\/zephyr,explora26\/zephyr,tidyjiang8\/zephyr-doc,nashif\/zephyr,zephyriot\/zephyr,GiulianoFranchetto\/zephyr,bigdinotech\/zephyr,pklazy\/zephyr,sharronliu\/zephyr,fbsder\/zephyr,punitvara\/zephyr,sharronliu\/zephyr,finikorg\/zephyr,runchip\/zephyr-cc3200,runchip\/zephyr-cc3220,nashif\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3200,rsalveti\/zephyr,tidyjiang8\/zephyr-doc,punitvara\/zephyr,rsalveti\/zephyr,punitvara\/zephyr,runchip\/zephyr-cc3200,nashif\/zephyr,erwango\/zephyr,bigdinotech\/zephyr,runchip\/zephyr-cc3220,rsalveti\/zephyr,fractalclone\/zephyr-riscv,aceofall\/zephyr-iotos,rsalveti\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,bigdinotech\/zephyr,kraj\/zephyr,fractalclone\/zephyr-riscv,explora26\/zephyr,kraj\/zephyr,nashif\/zephyr,mbolivar\/zephyr,pklazy\/zephyr,tidyjiang8\/zephyr-doc,fractalclone\/zephyr-riscv,galak\/zephyr,runchip\/zephyr-cc3220,zephyriot\/zephyr,ldts\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,fractalclone\/zephyr-riscv,Vudentz\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,pklazy\/zephyr,holtmann\/zephyr,sharronliu\/zephyr,Vudentz\/zephyr,mbolivar\/zephyr,fbsder\/zephyr,holtmann\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,bboozzoo\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,finikorg\/zephyr,bboozzoo\/zephyr,ldts\/zephyr,kraj\/zephyr,mbolivar\/zephyr,runchip\/zephyr-cc3200,fbsder\/zephyr,fractalclone\/zephyr-riscv,runchip\/zephyr-cc3220,explora26\/zephyr,kraj\/zephyr,GiulianoFranchetto\/zephyr,holtmann\/zephyr,bigdinotech\/zephyr,fbsder\/zephyr,erwango\/zephyr,runchip\/zephyr-cc3220,zephyrproject-rtos\/zephyr,sharronliu\/zephyr,zephyrproject-rtos\/zephyr,bboozzoo\/zephyr","old_file":"include\/arch\/arc\/v2\/linker.ld","new_file":"include\/arch\/arc\/v2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#if defined(CONFIG_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_HARVARD\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)\n\t\t#define ROMABLE_REGION FLASH\n\t\t#define RAMABLE_REGION SRAM\n\t#else\n\t\t#define ROMABLE_REGION SRAM\n\t\t#define RAMABLE_REGION SRAM\n\t#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(__start)\n\nMEMORY {\n#ifdef FLASH_START\n\tFLASH (rx)  : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n#endif\n#ifdef ICCM_START\n\tICCM  (rwx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n#endif\n#ifdef SRAM_START\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n#endif\n#ifdef DCCM_START\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n#endif\n}\n\nSECTIONS {\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\n\t\tKEEP(*(.openocd_dbg))\n\t\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*\n\t\t * The following sections maps the location of the different\n\t\t * rows for the _sw_isr_table. Each row maps to an IRQ entry\n\t\t * (handler, argument).\n\t\t *\n\t\t * In ARC architecture, IRQ 0-15 are reserved for the system\n\t\t * and are not * assignable by the user, for that reason the\n\t\t * linker sections start on IRQ 16\n\t\t *\/\n\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n\t\t_image_text_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\/* XIP imaged DATA ROM start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t\t_image_ram_start = .;\n\t\t__data_ram_start = .;\n\t\t*(.data)\n\t\t*(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(\".bss.*\")\n\t\tCOMMON_SYMBOLS\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t*(.noinit)\n\t\t*(\".noinit.*\")\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\tGROUP_START(DCCM)\n\tGROUP_END(DCCM)\n\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n","old_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#if defined(CONFIG_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_HARVARD\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)\n\t\t#define ROMABLE_REGION FLASH\n\t\t#define RAMABLE_REGION SRAM\n\t#else\n\t\t#define ROMABLE_REGION SRAM\n\t\t#define RAMABLE_REGION SRAM\n\t#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(__start)\n\nMEMORY {\n#ifdef FLASH_START\n\tFLASH (rx)  : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n#endif\n#ifdef ICCM_START\n\tICCM  (rwx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n#endif\n#ifdef SRAM_START\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n#endif\n#ifdef DCCM_START\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n#endif\n}\n\nSECTIONS {\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\n\t\tKEEP(*(.openocd_dbg))\n\t\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*\n\t\t * The following sections maps the location of the different\n\t\t * rows for the _sw_isr_table. Each row maps to an IRQ entry\n\t\t * (handler, argument).\n\t\t *\n\t\t * In ARC architecture, IRQ 0-15 are reserved for the system\n\t\t * and are not * assignable by the user, for that reason the\n\t\t * linker sections start on IRQ 16\n\t\t *\/\n\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n\t\t_image_text_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\/* XIP imaged DATA ROM start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t\t_image_ram_start = .;\n\t\t__data_ram_start = .;\n\t\t*(.data)\n\t\t*(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(\".bss.*\")\n\t\tCOMMON_SYMBOLS\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t*(.noinit)\n\t\t*(\".noinit.*\")\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\tGROUP_START(DCCM)\n\tGROUP_END(DCCM)\n\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5fcbe4e5d5771cc803323d174b804490e8486fe4","subject":"arch: arm: cortex-m: move openocd sections after _vector_end","message":"arch: arm: cortex-m: move openocd sections after _vector_end\n\nopenocd linker sections are not supposed to be part of the\nvector table sections. Place the sections after we define\nthe _vector_end linker symbol.\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\n","repos":"zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr","old_file":"arch\/arm\/core\/aarch32\/vector_table.ld","new_file":"arch\/arm\/core\/aarch32\/vector_table.ld","new_contents":"\/*\n * Copyright (c) 2019 Nordic Semiconductor ASA\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n_vector_start = .;\nKEEP(*(.exc_vector_table))\nKEEP(*(\".exc_vector_table.*\"))\n\nKEEP(*(IRQ_VECTOR_TABLE))\n\nKEEP(*(.vectors))\n\n_vector_end = .;\n\nKEEP(*(.openocd_dbg))\nKEEP(*(\".openocd_dbg.*\"))\n","old_contents":"\/*\n * Copyright (c) 2019 Nordic Semiconductor ASA\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n_vector_start = .;\nKEEP(*(.exc_vector_table))\nKEEP(*(\".exc_vector_table.*\"))\n\nKEEP(*(IRQ_VECTOR_TABLE))\n\nKEEP(*(.vectors))\n\nKEEP(*(.openocd_dbg))\nKEEP(*(\".openocd_dbg.*\"))\n\n_vector_end = .;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d19d6a76a764d233aef9fb66a89582b20c8f9382","subject":"arch: arm: aarch64: remove non-applicable linker section","message":"arch: arm: aarch64: remove non-applicable linker section\n\nThe non-secure callable functions' section is only applicable\nto Cortex-M with TrustZone-M extension. Remove it from AARCH64\nlinker script. (CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCTIONS\nis only enabled for Cortex-M so this is a no-op, but still, it\nis a useful cleanup.)\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n\/*\n * MMU currently supports 4 kB translation granule size,\n * so all regions are required to be 4 kB aligned\n *\/\n#define PAGE_SIZE\t0x1000\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_NAME))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n\/*\n * MMU currently supports 4 kB translation granule size,\n * so all regions are required to be 4 kB aligned\n *\/\n#define PAGE_SIZE\t0x1000\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_NAME))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n    #define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#else\n    #define NSC_ALIGN . = ALIGN(4)\n#endif\n\n    #define NSC_ALIGN_END . = ALIGN(4)\n\n    SECTION_PROLOGUE(.gnu.sgstubs,,)\n    {\n        NSC_ALIGN;\n        __sg_start = .;\n        \/* No input section necessary, since the Secure Entry Veneers are\n           automatically placed after the .gnu.sgstubs output section. *\/\n    } GROUP_LINK_IN(ROMABLE_REGION)\n    __sg_end = .;\n    __sg_size = __sg_end - __sg_start;\n    NSC_ALIGN_END;\n    __nsc_size = . - __sg_start;\n\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"28a11976daa0376db37766f807f5b234cc508dfb","subject":"Allow to set custom RAM base address for emulator","message":"Allow to set custom RAM base address for emulator\n\nThis is needed when loading the emulator to RAM\nwith an offset.\n","repos":"SpinalHDL\/VexRiscv,SpinalHDL\/VexRiscv,SpinalHDL\/VexRiscv,SpinalHDL\/VexRiscv,SpinalHDL\/VexRiscv","old_file":"src\/main\/c\/common\/ram.ld","new_file":"src\/main\/c\/common\/ram.ld","new_contents":"OUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nMEMORY\n{\n  ram : ORIGIN = DEFINED(__ram_origin) ? __ram_origin : 0x80000000, LENGTH = 64k\n}\n\n\nSECTIONS\n{\n  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  }> ram\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n    *(.note.gnu.build-id)\n  } > ram\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } > ram\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > ram\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > ram\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > ram\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } > ram\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > ram\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } > ram\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } > ram\n\n  .data          :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n  } >ram\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n\n  .stack :\n  {\n    PROVIDE( _heap_end = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } > ram\n}\n","old_contents":"OUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nMEMORY\n{\n  ram : ORIGIN = 0x80000000, LENGTH = 64k\n}\n\n\nSECTIONS\n{\n  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  }> ram\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n    *(.note.gnu.build-id)\n  } > ram\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } > ram\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > ram\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > ram\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > ram\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } > ram\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > ram\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } > ram\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } > ram\n\n  .data          :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n  } >ram\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n\n  .stack :\n  {\n    PROVIDE( _heap_end = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } > ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"429a5fb456d78e411bc90e8c8997cdbfdc0a2cca","subject":"soc\/intel_adsp: Remove spurious 4k padding of .text section","message":"soc\/intel_adsp: Remove spurious 4k padding of .text section\n\nThere was a \". = ALIGN(4096);\" sitting at the end of the .text section\nin the linker.  This had the effect of needlessly padding the size of\nthe segment as packed into and copied out of the firmware DMA image.\n\nThere's no value to storing unused bytes in the image.  It also makes\nanalysis easier for changes the modify code size.  The following\n.rodata section was already being 4k aligned anyway.\n\nSigned-off-by: Andy Ross <c70f9a6bf6ee0cd69c8af4ce5e6b131945769315@intel.com>\n","repos":"galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <cavs-vectors.h>\n#include <cavs-mem.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n\/* Offset of the entry point from the manifest start in IMR.  Magic\n * number must be synchronized with the module and rimage configuration!\n *\/\n#define ENTRY_POINT_OFF 0x6000\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n * (Note clumsy syntax because XCC doesn't understand the \"~\" operator)\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & 0xdfffffff) \/* == ~0x20000000 *\/\n#else\n#define SEGSTART_CACHED   \/**\/\n#define SEGSTART_UNCACHED \/**\/\n#define ucram ram\n#define ucram_phdr ram_phdr\n#endif\n\nMEMORY\n{\n  modules :\n        org = 0x10000,\n        len = 0x10000\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = CONFIG_IMR_MANIFEST_ADDR + ENTRY_POINT_OFF,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  imr_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram_phdr PT_LOAD;\n#endif\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n  module_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs25_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr :imr_phdr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr :imr_phdr\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >modules :module_phdr\n  .module.main : { KEEP(*(.module.main)) } >modules :module_phdr\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#ifdef CONFIG_KERNEL_COHERENCE\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n  . = SEGSTART_UNCACHED;\n#endif\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) : ALIGN(4096)\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram :ucram_phdr\n\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_CACHED;\n#endif\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <cavs-vectors.h>\n#include <cavs-mem.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n\/* Offset of the entry point from the manifest start in IMR.  Magic\n * number must be synchronized with the module and rimage configuration!\n *\/\n#define ENTRY_POINT_OFF 0x6000\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n * (Note clumsy syntax because XCC doesn't understand the \"~\" operator)\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & 0xdfffffff) \/* == ~0x20000000 *\/\n#else\n#define SEGSTART_CACHED   \/**\/\n#define SEGSTART_UNCACHED \/**\/\n#define ucram ram\n#define ucram_phdr ram_phdr\n#endif\n\nMEMORY\n{\n  modules :\n        org = 0x10000,\n        len = 0x10000\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = CONFIG_IMR_MANIFEST_ADDR + ENTRY_POINT_OFF,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  imr_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram_phdr PT_LOAD;\n#endif\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n  module_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs25_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr :imr_phdr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr :imr_phdr\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >modules :module_phdr\n  .module.main : { KEEP(*(.module.main)) } >modules :module_phdr\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#ifdef CONFIG_KERNEL_COHERENCE\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n  . = SEGSTART_UNCACHED;\n#endif\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) : ALIGN(4096)\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram :ucram_phdr\n\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_CACHED;\n#endif\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"106b1c2050a1cd31d1739ddd0633104bdc107ddd","subject":"arm: define _image_rodata_start\/end","message":"arm: define _image_rodata_start\/end\n\nDefine _image_rodata_start\/end to match x86 and so that we can\nrefer to them in the userspace test among others.\n\nSigned-off-by: Stephen Smalley <d6e1285e1c84d3d5885c2124fdacc780e9fc0a94@tycho.nsa.gov>\n","repos":"explora26\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,explora26\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,punitvara\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,kraj\/zephyr,punitvara\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,nashif\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,mbolivar\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,kraj\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,mbolivar\/zephyr,mbolivar\/zephyr,punitvara\/zephyr,finikorg\/zephyr,finikorg\/zephyr,aceofall\/zephyr-iotos,zephyrproject-rtos\/zephyr,explora26\/zephyr,galak\/zephyr,explora26\/zephyr,ldts\/zephyr,zephyriot\/zephyr,ldts\/zephyr,galak\/zephyr,aceofall\/zephyr-iotos,mbolivar\/zephyr,kraj\/zephyr,ldts\/zephyr,Vudentz\/zephyr,zephyriot\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,explora26\/zephyr,nashif\/zephyr,punitvara\/zephyr,zephyriot\/zephyr,mbolivar\/zephyr,aceofall\/zephyr-iotos,ldts\/zephyr,GiulianoFranchetto\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t_vector_start = .;\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t_vector_start = .;\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5f705adae06d4925351fe716f956d0fc922e53cf","subject":"nrf5\/boards: Adding more heap memory to the nrf51 256k\/32k s110 linker script. Leaving 2k for stack.","message":"nrf5\/boards: Adding more heap memory to the nrf51 256k\/32k s110 linker script. Leaving 2k for stack.\n","repos":"adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,tralamazza\/micropython,tralamazza\/micropython,tralamazza\/micropython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"nrf5\/boards\/nrf51x22_256k_32k_s110.ld","new_file":"nrf5\/boards\/nrf51x22_256k_32k_s110.ld","new_contents":"\/*\n    GNU linker script for NRF51822 AC w\/ S110 8.0.0 SoftDevice\n*\/\n\/* Specify the memory areas *\/\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00018000, LENGTH = 0x000400 \/* sector 0, 1 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 \/* 159 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20002000, LENGTH = 0x006000 \/* 24 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 1K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20005000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF51822 AC w\/ S110 8.0.0 SoftDevice\n*\/\n\/* Specify the memory areas *\/\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00018000, LENGTH = 0x000400 \/* sector 0, 1 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 \/* 159 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20002000, LENGTH = 0x006000 \/* 24 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 4K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20003000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e1a18c5553a256e6e760b1c5861eee0e93f534e5","subject":"solo5: Force page-aligment for first ELF segment","message":"solo5: Force page-aligment for first ELF segment\n","repos":"ingve\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,ingve\/IncludeOS,ingve\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,AndreasAakesson\/IncludeOS,hioa-cs\/IncludeOS,ingve\/IncludeOS,AnnikaH\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,alfred-bratterud\/IncludeOS,hioa-cs\/IncludeOS,AnnikaH\/IncludeOS,ingve\/IncludeOS,AndreasAakesson\/IncludeOS,alfred-bratterud\/IncludeOS,alfred-bratterud\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,alfred-bratterud\/IncludeOS,AnnikaH\/IncludeOS","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0xA00000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  . = _ELF_START_ + SIZEOF_HEADERS;\n  .multiboot ALIGN(0x1000): {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n  PROVIDE( _TEXT_START_ = . );\n  .text (_TEXT_START_ ) :\n  {\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x10) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  .config ALIGN(0x8) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","old_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0xA00000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  .multiboot (_ELF_START_ + SIZEOF_HEADERS): {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n  PROVIDE( _TEXT_START_ = . );\n  .text (_TEXT_START_ ) :\n  {\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x10) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  .config ALIGN(0x8) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"0c3879a55302eaad84a028e2a1e836b447bab17c","subject":"Add crash RAM to STM32F412xG","message":"Add crash RAM to STM32F412xG\n","repos":"mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed","old_file":"targets\/TARGET_STM\/TARGET_STM32F4\/TARGET_STM32F412xG\/TOOLCHAIN_GCC_ARM\/STM32F412xG.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32F4\/TARGET_STM32F412xG\/TOOLCHAIN_GCC_ARM\/STM32F412xG.ld","new_contents":"\/* Linker script to configure memory regions. *\/\n\/*\n * SPDX-License-Identifier: BSD-3-Clause\n ******************************************************************************\n * @attention\n *\n * Copyright (c) 2016-2020 STMicroelectronics.\n * All rights reserved.\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n *                        opensource.org\/licenses\/BSD-3-Clause\n *\n ******************************************************************************\n*\/\n\n#include \"..\/cmsis_nvic.h\"\n\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START  MBED_ROM_START\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE  MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    \/* This value is normally defined by the tools\n       to 0x1000 for bare metal and 0x400 for RTOS *\/\n    #define MBED_BOOT_STACK_SIZE  0x400\n#endif\n\n\/* Round up VECTORS_SIZE to 8 bytes *\/\n#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)\n\nM_CRASH_DATA_RAM_SIZE = 0x100;\n\nMEMORY\n{\n    FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n    RAM (rwx)    : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .crash_data_ram :\n    {\n        . = ALIGN(8);\n        __CRASH_DATA_RAM__ = .;\n        __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n        KEEP(*(.keep.crash_data_ram))\n        *(.m_crash_data_ram)     \/* This is a user defined section *\/\n        . += M_CRASH_DATA_RAM_SIZE;\n        . = ALIGN(8);\n        __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > RAM    \n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    \/* Uninitialized data section\n     * This region is not initialized by the C\/C++ library and can be used to\n     * store state across soft reboots. *\/\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        PROVIDE(end = .);\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\/*\n * SPDX-License-Identifier: BSD-3-Clause\n ******************************************************************************\n * @attention\n *\n * Copyright (c) 2016-2020 STMicroelectronics.\n * All rights reserved.\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n *                        opensource.org\/licenses\/BSD-3-Clause\n *\n ******************************************************************************\n*\/\n\n#include \"..\/cmsis_nvic.h\"\n\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START  MBED_ROM_START\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE  MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    \/* This value is normally defined by the tools\n       to 0x1000 for bare metal and 0x400 for RTOS *\/\n    #define MBED_BOOT_STACK_SIZE  0x400\n#endif\n\n\/* Round up VECTORS_SIZE to 8 bytes *\/\n#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)\n\nMEMORY\n{\n    FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n    RAM (rwx)    : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    \/* Uninitialized data section\n     * This region is not initialized by the C\/C++ library and can be used to\n     * store state across soft reboots. *\/\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        PROVIDE(end = .);\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"32ed937d0596e849e1976791e78c006cee8356ca","subject":"x86: fix comments in vmlinux_64.lds","message":"x86: fix comments in vmlinux_64.lds\n\nfor bzImage, the vmlinux_64.lds still have s32 bit code, and startup_32\nshould be 0. fix the comment.\n\nSigned-off-by: Yinghai Lu <85a101cfd167df9f17f083a8913750b6c2905e71@sun.com>\nSigned-off-by: Ingo Molnar <9dbbbf0688fedc85ad4da37637f1a64b8c718ee2@elte.hu>\n","repos":"KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas","old_file":"arch\/x86\/boot\/compressed\/vmlinux_64.lds","new_file":"arch\/x86\/boot\/compressed\/vmlinux_64.lds","new_contents":"OUTPUT_FORMAT(\"elf64-x86-64\", \"elf64-x86-64\", \"elf64-x86-64\")\nOUTPUT_ARCH(i386:x86-64)\nENTRY(startup_64)\nSECTIONS\n{\n\t\/* Be careful parts of head_64.S assume startup_32 is at\n\t * address 0.\n\t *\/\n\t. = 0;\n\t.text.head : {\n\t\t_head = . ;\n\t\t*(.text.head)\n\t\t_ehead = . ;\n\t}\n\t.rodata.compressed : {\n\t\t*(.rodata.compressed)\n\t}\n\t.text :\t{\n\t\t_text = .; \t\/* Text *\/\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t_etext = . ;\n\t}\n\t.rodata : {\n\t\t_rodata = . ;\n\t\t*(.rodata)\t \/* read-only data *\/\n\t\t*(.rodata.*)\n\t\t_erodata = . ;\n\t}\n\t.data :\t{\n\t\t_data = . ;\n\t\t*(.data)\n\t\t*(.data.*)\n\t\t_edata = . ;\n\t}\n\t.bss : {\n\t\t_bss = . ;\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\t\t_end = . ;\n\t\t. = ALIGN(4096);\n\t\tpgtable = . ;\n\t\t. = . + 4096 * 6;\n\t\t_heap = .;\n\t}\n}\n","old_contents":"OUTPUT_FORMAT(\"elf64-x86-64\", \"elf64-x86-64\", \"elf64-x86-64\")\nOUTPUT_ARCH(i386:x86-64)\nENTRY(startup_64)\nSECTIONS\n{\n\t\/* Be careful parts of head_64.S assume startup_64 is at\n\t * address 0.\n\t *\/\n\t. = 0;\n\t.text.head : {\n\t\t_head = . ;\n\t\t*(.text.head)\n\t\t_ehead = . ;\n\t}\n\t.rodata.compressed : {\n\t\t*(.rodata.compressed)\n\t}\n\t.text :\t{\n\t\t_text = .; \t\/* Text *\/\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t_etext = . ;\n\t}\n\t.rodata : {\n\t\t_rodata = . ;\n\t\t*(.rodata)\t \/* read-only data *\/\n\t\t*(.rodata.*)\n\t\t_erodata = . ;\n\t}\n\t.data :\t{\n\t\t_data = . ;\n\t\t*(.data)\n\t\t*(.data.*)\n\t\t_edata = . ;\n\t}\n\t.bss : {\n\t\t_bss = . ;\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\t\t_end = . ;\n\t\t. = ALIGN(4096);\n\t\tpgtable = . ;\n\t\t. = . + 4096 * 6;\n\t\t_heap = .;\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"00b00cc57bfe0fca54c904d4dd44a263e243c88b","subject":"BaseTools\/Scripts: discard .gnu.hash section in GCC builds","message":"BaseTools\/Scripts: discard .gnu.hash section in GCC builds\n\nSome builds of GCC\/binutils will default to using the GNU flavor of\nthe symbol hash table, and will emit it into a section called .gnu.hash\nrather than .hash. We have no use for its contents, and GenFw ignores\nit anyway, so it shouldn't really matter what we do with it.\n\nHowever, due to a workaround for AARCH64 we have in GenFw to deal with\nolder GCCs that corrupt section-based relocations when merging sections\nduring the final link, we need the ELF and PE\/COFF views of the binary\nto be identical. Since we don't place the .gnu.hash section explicitly,\nit may end up at the beginning of the ELF binary, causing other sections\nto be shifted in the ELF view but not in the PE\/COFF view.\n\nSo let's add .gnu.hash to the GCC linker script. We don't care about its\ncontents so add it to the \/DISCARD\/ section.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org>\nTested-by: Leif Lindholm <a613079f0455438b29e28a9c5b9eb3779a81a33a@linaro.org>\nReviewed-by: Liming Gao <6480311aeeb4b006862f6d13ebabddc03f51e507@intel.com>\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"BaseTools\/Scripts\/GccBase.lds","new_file":"BaseTools\/Scripts\/GccBase.lds","new_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are mostly constant from the POV of the\r\n     * program, but most of it ends up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     * Unfortunately, we cannot pull it into the .text section entirely, since\r\n     * patchable PCDs are also emitted here, but we can at least move all of the\r\n     * emitted GUIDs here.\r\n     *\/\r\n    *:AutoGen.obj(.data.g*Guid)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela (INFO) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/*\r\n   * Retain the GNU build id but in a non-allocatable section so GenFw\r\n   * does not copy it into the PE\/COFF image.\r\n   *\/\r\n  .build-id (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash .gnu.hash)\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","old_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are mostly constant from the POV of the\r\n     * program, but most of it ends up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     * Unfortunately, we cannot pull it into the .text section entirely, since\r\n     * patchable PCDs are also emitted here, but we can at least move all of the\r\n     * emitted GUIDs here.\r\n     *\/\r\n    *:AutoGen.obj(.data.g*Guid)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela (INFO) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/*\r\n   * Retain the GNU build id but in a non-allocatable section so GenFw\r\n   * does not copy it into the PE\/COFF image.\r\n   *\/\r\n  .build-id (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"a4995eb12fcd08d1c1bdd197526b2e7bf77aa202","subject":"Correct memory map to use all of RAM","message":"Correct memory map to use all of RAM\n","repos":"mbains\/bare-metal-arm,firebitsbr\/bare-metal-arm,payne92\/bare-metal-arm,firebitsbr\/bare-metal-arm,payne92\/bare-metal-arm,payne92\/bare-metal-arm,mbains\/bare-metal-arm","old_file":"mkl25z4.ld","new_file":"mkl25z4.ld","new_contents":"\/**************************************************************************\/\r\n\/* Configure memory regions *\/\r\nMEMORY\r\n{\r\n  VECTORS (rx)      : ORIGIN = 0x0,         LENGTH = 0x00c0\r\n  FLASHCFG (rx)     : ORIGIN = 0x00000400,  LENGTH = 0x00000010\r\n  FLASH (rx)        : ORIGIN = 0x00000410,  LENGTH = 128K - 0x410\r\n  RAM  (rwx)        : ORIGIN = 0x1FFFF000,  LENGTH = 16K\r\n}\r\n\r\n\/* Config Libraries *\/\r\nGROUP(libgcc.a libc.a libm.a libnosys.a)\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n * \r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(_reset_init)\r\n\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into INTERNAL_FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    __vector_table = .;\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))\r\n    . = ALIGN(4);\r\n  } > VECTORS\r\n\r\n  .cfmprotect :\r\n  {\r\n    . = ALIGN(4);\r\n        KEEP(*(.cfmconfig))     \/* Flash Configuration Field (FCF) *\/\r\n    . = ALIGN(4);\r\n  } > FLASHCFG\r\n\r\n    .text :\r\n    {\r\n        *(.text*)\r\n\r\n        KEEP(*(.init))\r\n        KEEP(*(.fini))\r\n\r\n        \/* .ctors *\/\r\n        *crtbegin.o(.ctors)\r\n        *crtbegin?.o(.ctors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n        *(SORT(.ctors.*))\r\n        *(.ctors)\r\n\r\n        \/* .dtors *\/\r\n        *crtbegin.o(.dtors)\r\n        *crtbegin?.o(.dtors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n        *(SORT(.dtors.*))\r\n        *(.dtors)\r\n\r\n        *(.rodata*)\r\n\r\n        KEEP(*(.eh_frame*))\r\n    } > FLASH\r\n\r\n    .ARM.extab : \r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > FLASH\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx :\r\n    {\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n    __exidx_end = .;\r\n\r\n    __etext = .;\r\n        \r\n    .data : AT (__etext)\r\n    {\r\n        __data_start__ = .;\r\n        *(vtable)\r\n        *(.data*)\r\n\r\n        . = ALIGN(4);\r\n        \/* preinit data *\/\r\n        PROVIDE_HIDDEN (__preinit_array_start = .);\r\n        KEEP(*(.preinit_array))\r\n        PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* init data *\/\r\n        PROVIDE_HIDDEN (__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n\r\n        . = ALIGN(4);\r\n        \/* finit data *\/\r\n        PROVIDE_HIDDEN (__fini_array_start = .);\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        KEEP(*(.fini_array))\r\n        PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* All data end *\/\r\n        __data_end__ = .;\r\n\r\n    } > RAM\r\n\r\n    .bss :\r\n    {\r\n        __bss_start__ = .;\r\n        *(.bss*)\r\n        *(COMMON)\r\n        __bss_end__ = .;\r\n    } > RAM\r\n    \r\n    .heap :\r\n    {\r\n        __end__ = .;\r\n        end = __end__;\r\n        __heap_start = .;\r\n        *(.heap*)\r\n        __heap_end = .;\r\n    } > RAM\r\n\r\n    \/* Set stack top to end of RAM *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - 1k;\r\n    PROVIDE(__stack = __StackTop);\r\n    \r\n    \/* Check if data + heap + stack exceeds RAM limit *\/\r\n    ASSERT(__StackLimit >= __heap_end, \"region RAM overflowed with stack\")\r\n}","old_contents":"\/**************************************************************************\/\r\n\/* Configure memory regions *\/\r\nMEMORY\r\n{\r\n  VECTORS (rx)      : ORIGIN = 0x0,         LENGTH = 0x00c0\r\n  FLASHCFG (rx)     : ORIGIN = 0x00000400,  LENGTH = 0x00000010\r\n  FLASH (rx)        : ORIGIN = 0x00000410,  LENGTH = 128K - 0x410\r\n  RAM  (rwx)        : ORIGIN = 0x20000000,  LENGTH = 12K\r\n}\r\n\r\n\/* Config Libraries *\/\r\nGROUP(libgcc.a libc.a libm.a libnosys.a)\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n * \r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(_reset_init)\r\n\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into INTERNAL_FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    __vector_table = .;\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))\r\n    . = ALIGN(4);\r\n  } > VECTORS\r\n\r\n  .cfmprotect :\r\n  {\r\n    . = ALIGN(4);\r\n        KEEP(*(.cfmconfig))     \/* Flash Configuration Field (FCF) *\/\r\n    . = ALIGN(4);\r\n  } > FLASHCFG\r\n\r\n    .text :\r\n    {\r\n        *(.text*)\r\n\r\n        KEEP(*(.init))\r\n        KEEP(*(.fini))\r\n\r\n        \/* .ctors *\/\r\n        *crtbegin.o(.ctors)\r\n        *crtbegin?.o(.ctors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n        *(SORT(.ctors.*))\r\n        *(.ctors)\r\n\r\n        \/* .dtors *\/\r\n        *crtbegin.o(.dtors)\r\n        *crtbegin?.o(.dtors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n        *(SORT(.dtors.*))\r\n        *(.dtors)\r\n\r\n        *(.rodata*)\r\n\r\n        KEEP(*(.eh_frame*))\r\n    } > FLASH\r\n\r\n    .ARM.extab : \r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > FLASH\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx :\r\n    {\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n    __exidx_end = .;\r\n\r\n    __etext = .;\r\n        \r\n    .data : AT (__etext)\r\n    {\r\n        __data_start__ = .;\r\n        *(vtable)\r\n        *(.data*)\r\n\r\n        . = ALIGN(4);\r\n        \/* preinit data *\/\r\n        PROVIDE_HIDDEN (__preinit_array_start = .);\r\n        KEEP(*(.preinit_array))\r\n        PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* init data *\/\r\n        PROVIDE_HIDDEN (__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n\r\n        . = ALIGN(4);\r\n        \/* finit data *\/\r\n        PROVIDE_HIDDEN (__fini_array_start = .);\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        KEEP(*(.fini_array))\r\n        PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* All data end *\/\r\n        __data_end__ = .;\r\n\r\n    } > RAM\r\n\r\n    .bss :\r\n    {\r\n        __bss_start__ = .;\r\n        *(.bss*)\r\n        *(COMMON)\r\n        __bss_end__ = .;\r\n    } > RAM\r\n    \r\n    .heap :\r\n    {\r\n        __end__ = .;\r\n        end = __end__;\r\n        __heap_start = .;\r\n        *(.heap*)\r\n        __heap_end = .;\r\n    } > RAM\r\n\r\n    \/* Set stack top to end of RAM *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - 1k;\r\n    PROVIDE(__stack = __StackTop);\r\n    \r\n    \/* Check if data + heap + stack exceeds RAM limit *\/\r\n    ASSERT(__StackLimit >= __heap_end, \"region RAM overflowed with stack\")\r\n}","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"29922943eba2ddf743e445b1271f37cf5c52627f","subject":"Modified memory sizes in linker script","message":"Modified memory sizes in linker script\n","repos":"bcostm\/mbed-os,fvincenzo\/mbed-os,bentwire\/mbed,Archcady\/mbed-os,nabilbendafi\/mbed,nvlsianpu\/mbed,andcor02\/mbed-os,nRFMesh\/mbed-os,pedromes\/mbed,jrjang\/mbed,c1728p9\/mbed-os,theotherjimmy\/mbed,rosterloh\/mbed,kpurusho\/mbed,adamgreen\/mbed,bcostm\/mbed-os,mmorenobarm\/mbed-os,screamerbg\/mbed,Shengliang\/mbed,kpurusho\/mbed,fvincenzo\/mbed-os,bentwire\/mbed,HeadsUpDisplayInc\/mbed,bikeNomad\/mbed,betzw\/mbed-os,mikaleppanen\/mbed-os,HeadsUpDisplayInc\/mbed,jeremybrodt\/mbed,andreaslarssonublox\/mbed,maximmbed\/mbed,adamgreen\/mbed,CalSol\/mbed,tung7970\/mbed-os,rosterloh\/mbed,fanghuaqi\/mbed,cvtsi2sd\/mbed-os,DanKupiniak\/mbed,svogl\/mbed-os,pradeep-gr\/mbed-os5-onsemi,YarivCol\/mbed-os,YarivCol\/mbed-os,getopenmono\/mbed,CalSol\/mbed,cvtsi2sd\/mbed-os,arostm\/mbed-os,adamgreen\/mbed,kl-cruz\/mbed-os,RonEld\/mbed,catiedev\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,bikeNomad\/mbed,bulislaw\/mbed-os,kl-cruz\/mbed-os,tung7970\/mbed-os,netzimme\/mbed-os,ryankurte\/mbed-os,theotherjimmy\/mbed,nRFMesh\/mbed-os,dbestm\/mbed,monkiineko\/mbed-os,karsev\/mbed-os,monkiineko\/mbed-os,dbestm\/mbed,kl-cruz\/mbed-os,netzimme\/mbed-os,cvtsi2sd\/mbed-os,nabilbendafi\/mbed,ryankurte\/mbed-os,adustm\/mbed,andreaslarssonublox\/mbed,mbedmicro\/mbed,monkiineko\/mbed-os,NXPmicro\/mbed,bikeNomad\/mbed,catiedev\/mbed-os,c1728p9\/mbed-os,nabilbendafi\/mbed,c1728p9\/mbed-os,nabilbendafi\/mbed,getopenmono\/mbed,mazimkhan\/mbed-os,betzw\/mbed-os,theotherjimmy\/mbed,fahhem\/mbed-os,DanKupiniak\/mbed,fvincenzo\/mbed-os,andcor02\/mbed-os,infinnovation\/mbed-os,screamerbg\/mbed,nvlsianpu\/mbed,mbedmicro\/mbed,mikaleppanen\/mbed-os,pedromes\/mbed,Tiryoh\/mbed,mmorenobarm\/mbed-os,nRFMesh\/mbed-os,mbedmicro\/mbed,maximmbed\/mbed,Shengliang\/mbed,kpurusho\/mbed,fahhem\/mbed-os,monkiineko\/mbed-os,monkiineko\/mbed-os,mazimkhan\/mbed-os,jrjang\/mbed,mikaleppanen\/mbed-os,c1728p9\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,theotherjimmy\/mbed,cvtsi2sd\/mbed-os,svogl\/mbed-os,mmorenobarm\/mbed-os,netzimme\/mbed-os,ryankurte\/mbed-os,jeremybrodt\/mbed,infinnovation\/mbed-os,Archcady\/mbed-os,karsev\/mbed-os,getopenmono\/mbed,maximmbed\/mbed,HeadsUpDisplayInc\/mbed,Tiryoh\/mbed,rgrover\/mbed,mikaleppanen\/mbed-os,kjbracey-arm\/mbed,j-greffe\/mbed-os,karsev\/mbed-os,getopenmono\/mbed,bentwire\/mbed,andcor02\/mbed-os,svastm\/mbed,screamerbg\/mbed,fanghuaqi\/mbed,bikeNomad\/mbed,betzw\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,pedromes\/mbed,karsev\/mbed-os,svastm\/mbed,bulislaw\/mbed-os,geky\/mbed,ARM-software\/mbed-beetle,dbestm\/mbed,mmorenobarm\/mbed-os,netzimme\/mbed-os,mikaleppanen\/mbed-os,Archcady\/mbed-os,netzimme\/mbed-os,tung7970\/mbed-os,fahhem\/mbed-os,svastm\/mbed,j-greffe\/mbed-os,screamerbg\/mbed,betzw\/mbed-os,maximmbed\/mbed,infinnovation\/mbed-os,Archcady\/mbed-os,jeremybrodt\/mbed,adustm\/mbed,netzimme\/mbed-os,NXPmicro\/mbed,DanKupiniak\/mbed,ryankurte\/mbed-os,svastm\/mbed,andreaslarssonublox\/mbed,cvtsi2sd\/mbed-os,CalSol\/mbed,jeremybrodt\/mbed,CalSol\/mbed,svogl\/mbed-os,adustm\/mbed,tung7970\/mbed-os-1,catiedev\/mbed-os,getopenmono\/mbed,kl-cruz\/mbed-os,dbestm\/mbed,CalSol\/mbed,catiedev\/mbed-os,rosterloh\/mbed,jeremybrodt\/mbed,infinnovation\/mbed-os,andreaslarssonublox\/mbed,c1728p9\/mbed-os,c1728p9\/mbed-os,bulislaw\/mbed-os,fanghuaqi\/mbed,YarivCol\/mbed-os,NXPmicro\/mbed,bulislaw\/mbed-os,NXPmicro\/mbed,bikeNomad\/mbed,maximmbed\/mbed,fanghuaqi\/mbed,mbedmicro\/mbed,cvtsi2sd\/mbed-os,pedromes\/mbed,tung7970\/mbed-os,maximmbed\/mbed,kjbracey-arm\/mbed,Archcady\/mbed-os,andreaslarssonublox\/mbed,YarivCol\/mbed-os,tung7970\/mbed-os-1,bentwire\/mbed,dbestm\/mbed,geky\/mbed,geky\/mbed,pedromes\/mbed,j-greffe\/mbed-os,mazimkhan\/mbed-os,mikaleppanen\/mbed-os,fahhem\/mbed-os,rosterloh\/mbed,adamgreen\/mbed,mmorenobarm\/mbed-os,geky\/mbed,fvincenzo\/mbed-os,mazimkhan\/mbed-os,pradeep-gr\/mbed-os5-onsemi,kjbracey-arm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,bcostm\/mbed-os,Tiryoh\/mbed,karsev\/mbed-os,geky\/mbed,mbedmicro\/mbed,tung7970\/mbed-os-1,mmorenobarm\/mbed-os,RonEld\/mbed,kl-cruz\/mbed-os,pradeep-gr\/mbed-os5-onsemi,Tiryoh\/mbed,arostm\/mbed-os,svogl\/mbed-os,Shengliang\/mbed,rgrover\/mbed,bcostm\/mbed-os,fahhem\/mbed-os,betzw\/mbed-os,svogl\/mbed-os,nRFMesh\/mbed-os,nRFMesh\/mbed-os,adamgreen\/mbed,Shengliang\/mbed,j-greffe\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,CalSol\/mbed,adustm\/mbed,bulislaw\/mbed-os,adustm\/mbed,theotherjimmy\/mbed,Shengliang\/mbed,YarivCol\/mbed-os,theotherjimmy\/mbed,nvlsianpu\/mbed,andcor02\/mbed-os,NXPmicro\/mbed,bulislaw\/mbed-os,bcostm\/mbed-os,jrjang\/mbed,kjbracey-arm\/mbed,getopenmono\/mbed,YarivCol\/mbed-os,mazimkhan\/mbed-os,screamerbg\/mbed,arostm\/mbed-os,adamgreen\/mbed,Archcady\/mbed-os,karsev\/mbed-os,NXPmicro\/mbed,nvlsianpu\/mbed,tung7970\/mbed-os,nabilbendafi\/mbed,arostm\/mbed-os,ARM-software\/mbed-beetle,kpurusho\/mbed,kl-cruz\/mbed-os,catiedev\/mbed-os,HeadsUpDisplayInc\/mbed,j-greffe\/mbed-os,ARM-software\/mbed-beetle,jrjang\/mbed,fanghuaqi\/mbed,pradeep-gr\/mbed-os5-onsemi,catiedev\/mbed-os,jrjang\/mbed,Tiryoh\/mbed,infinnovation\/mbed-os,monkiineko\/mbed-os,RonEld\/mbed,arostm\/mbed-os,ARM-software\/mbed-beetle,Shengliang\/mbed,infinnovation\/mbed-os,pedromes\/mbed,RonEld\/mbed,nabilbendafi\/mbed,andcor02\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,adustm\/mbed,kpurusho\/mbed,ryankurte\/mbed-os,fvincenzo\/mbed-os,bentwire\/mbed,Tiryoh\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,HeadsUpDisplayInc\/mbed,bentwire\/mbed,HeadsUpDisplayInc\/mbed,svastm\/mbed,andcor02\/mbed-os,screamerbg\/mbed,fahhem\/mbed-os,mazimkhan\/mbed-os,j-greffe\/mbed-os,ryankurte\/mbed-os,nvlsianpu\/mbed,nRFMesh\/mbed-os,bcostm\/mbed-os,rgrover\/mbed,RonEld\/mbed,jrjang\/mbed,tung7970\/mbed-os-1,tung7970\/mbed-os-1,dbestm\/mbed,nvlsianpu\/mbed,pradeep-gr\/mbed-os5-onsemi,DanKupiniak\/mbed,RonEld\/mbed,rosterloh\/mbed,rgrover\/mbed,rgrover\/mbed,rosterloh\/mbed,arostm\/mbed-os,kpurusho\/mbed,svogl\/mbed-os","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_STM32F4\/TARGET_NUCLEO_F410RB\/TOOLCHAIN_GCC_ARM\/STM32F411XE.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_STM32F4\/TARGET_NUCLEO_F410RB\/TOOLCHAIN_GCC_ARM\/STM32F411XE.ld","new_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K\n  RAM (rwx)  : ORIGIN = 0x20000198, LENGTH = 32k - 0x198\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K\n  RAM (rwx)  : ORIGIN = 0x20000198, LENGTH = 128k - 0x198\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8b5539d02c6d876615a1051ed5fd8b1756230c65","subject":"Update paths","message":"Update paths\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52840\/src\/nrf52840_xxaa.ld","new_file":"ARM\/Nordic\/nRF52840\/src\/nrf52840_xxaa.ld","new_contents":"\/* Linker script to configure memory regions. *\/\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000\r\n  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x40000\r\n}\r\n\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"\r\n","old_contents":"\/* Linker script to configure memory regions. *\/\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/nRF52840\/CMSIS\/Release\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000\r\n  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x40000\r\n}\r\n\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"4a6974bea598a9b76c4a49afcc0d6f82760a7006","subject":"stm32\/boards\/PYBD_SF2: Put nimble library in external QSPI XIP flash.","message":"stm32\/boards\/PYBD_SF2: Put nimble library in external QSPI XIP flash.\n\nThe BLE stack is not performance critical, so put it in external\nmemory-mapped flash to save internal flash for other things (like frozen\nbytecode).\n","repos":"henriknelson\/micropython,trezor\/micropython,adafruit\/circuitpython,bvernoux\/micropython,adafruit\/circuitpython,pramasoul\/micropython,tobbad\/micropython,pramasoul\/micropython,selste\/micropython,tobbad\/micropython,MrSurly\/micropython,pozetroninc\/micropython,pozetroninc\/micropython,kerneltask\/micropython,selste\/micropython,MrSurly\/micropython,adafruit\/circuitpython,pramasoul\/micropython,kerneltask\/micropython,pozetroninc\/micropython,kerneltask\/micropython,henriknelson\/micropython,tobbad\/micropython,tobbad\/micropython,trezor\/micropython,pramasoul\/micropython,henriknelson\/micropython,bvernoux\/micropython,tobbad\/micropython,bvernoux\/micropython,selste\/micropython,MrSurly\/micropython,adafruit\/circuitpython,pozetroninc\/micropython,bvernoux\/micropython,adafruit\/circuitpython,henriknelson\/micropython,selste\/micropython,MrSurly\/micropython,trezor\/micropython,pozetroninc\/micropython,adafruit\/circuitpython,selste\/micropython,pramasoul\/micropython,trezor\/micropython,bvernoux\/micropython,kerneltask\/micropython,kerneltask\/micropython,MrSurly\/micropython,henriknelson\/micropython,trezor\/micropython","old_file":"ports\/stm32\/boards\/PYBD_SF2\/f722_qspi.ld","new_file":"ports\/stm32\/boards\/PYBD_SF2\/f722_qspi.ld","new_contents":"\/*\n    Linker script for PYBD with STM32F722\/STM32F723\/STM32F732\/STM32F733\n\n    Memory layout for mboot configuration (this here describes the app part):\n\n    FLASH_APP   .isr_vector\n    FLASH_APP   .text\n    FLASH_APP   .data\n\n    FLASH_EXT   .big_const\n\n    RAM         .data\n    RAM         .bss\n    RAM         .heap\n    RAM         .stack\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 32K     \/* sectors 0,1 *\/\n    FLASH_APP (rx)  : ORIGIN = 0x08008000, LENGTH = 480K    \/* sectors 2-7 *\/\n    FLASH_EXT (rx)  : ORIGIN = 0x90000000, LENGTH = 2048K   \/* external QSPI *\/\n    RAM (rwx)       : ORIGIN = 0x20000000, LENGTH = 256K    \/* DTCM+SRAM1+SRAM2 *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K;\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n\nENTRY(Reset_Handler)\n\n\/* Define output sections *\/\nSECTIONS\n{\n    .text_ext :\n    {\n        . = ALIGN(4);\n        *lib\/mbedtls\/*(.text* .rodata*)\n        *lib\/mynewt-nimble\/*(.text* .rodata*)\n        . = ALIGN(512);\n        *(.big_const*)\n        . = ALIGN(4);\n    } >FLASH_EXT\n\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n    } >FLASH_APP\n\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        _etext = .;\n    } >FLASH_APP\n\n    _sidata = LOADADDR(.data);\n\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.data*)\n\n        . = ALIGN(4);\n        _edata = .;\n    } >RAM AT> FLASH_APP\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n    } >RAM\n\n    .heap :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_heap_size;\n        . = ALIGN(4);\n    } >RAM\n\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n}\n","old_contents":"\/*\n    Linker script for PYBD with STM32F722\/STM32F723\/STM32F732\/STM32F733\n\n    Memory layout for mboot configuration (this here describes the app part):\n\n    FLASH_APP   .isr_vector\n    FLASH_APP   .text\n    FLASH_APP   .data\n\n    FLASH_EXT   .big_const\n\n    RAM         .data\n    RAM         .bss\n    RAM         .heap\n    RAM         .stack\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 32K     \/* sectors 0,1 *\/\n    FLASH_APP (rx)  : ORIGIN = 0x08008000, LENGTH = 480K    \/* sectors 2-7 *\/\n    FLASH_EXT (rx)  : ORIGIN = 0x90000000, LENGTH = 2048K   \/* external QSPI *\/\n    RAM (rwx)       : ORIGIN = 0x20000000, LENGTH = 256K    \/* DTCM+SRAM1+SRAM2 *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K;\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n\nENTRY(Reset_Handler)\n\n\/* Define output sections *\/\nSECTIONS\n{\n    .text_ext :\n    {\n        . = ALIGN(4);\n        *lib\/mbedtls\/*(.text* .rodata*)\n        . = ALIGN(512);\n        *(.big_const*)\n        . = ALIGN(4);\n    } >FLASH_EXT\n\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n    } >FLASH_APP\n\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        _etext = .;\n    } >FLASH_APP\n\n    _sidata = LOADADDR(.data);\n\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.data*)\n\n        . = ALIGN(4);\n        _edata = .;\n    } >RAM AT> FLASH_APP\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n    } >RAM\n\n    .heap :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_heap_size;\n        . = ALIGN(4);\n    } >RAM\n\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"abb907b150e947b4dc864bcd4e080a75156ad383","subject":"name comes from the font itself","message":"name comes from the font itself","repos":"ggreif\/al4nin,ggreif\/al4nin","old_file":"purgatory\/db\/lm.ld","new_file":"purgatory\/db\/lm.ld","new_contents":"########\n# LMnine\n{\n@FontDef\n     @Tag { LMnine-Base }\n     @Family { LMnine }\n     @Face { Base }\n     @Name { LMRoman9-Regular }\n     @Metrics { lmr9.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMnine-Bold }\n     @Family { LMnine }\n     @Face { Bold }\n     @Name { LMRoman9-Bold }\n     @Metrics { lmbx9.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMnine-Slope }\n     @Family { LMnine }\n     @Face { Slope }\n     @Name { LMRoman9-Italic }\n     @Metrics { lmri9.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMnine-BoldSlope }\n     @Family { LMnine }\n     @Face { BoldSlope }\n     @Name { LMRoman9-BoldItalic }\n     @Metrics { lmbxi9.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n#######\n# LMten\n{\n@FontDef\n     @Tag { LMten-Base }\n     @Family { LMten }\n     @Face { Base }\n     @Name { LMRoman10-Regular }\n     @Metrics { lmr10.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMten-Bold }\n     @Family { LMten }\n     @Face { Bold }\n     @Name { LMRoman10-Bold }\n     @Metrics { lmbx10.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMten-Slope }\n     @Family { LMten }\n     @Face { Slope }\n     @Name { LMRoman10-Italic }\n     @Metrics { lmri10.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMten-BoldSlope }\n     @Family { LMten }\n     @Face { BoldSlope }\n     @Name { LMRoman10-BoldItalic }\n     @Metrics { lmbxi10.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n########\n# AMSYten\n{\n@FontDef\n     @Tag { AMSYten-Base }\n     @Family { AMSYten }\n     @Face { Base }\n     @Name { msam10 }\n     @Metrics { msam10.afm }\n     @Mapping { AmsSymb.LCM }\n}\n","old_contents":"########\n# LMnine\n{\n@FontDef\n     @Tag { LMnine-Base }\n     @Family { LMnine }\n     @Face { Base }\n     @Name { LMRoman9-Regular }\n     @Metrics { lmr9.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMnine-Bold }\n     @Family { LMnine }\n     @Face { Bold }\n     @Name { LMRoman9-Bold }\n     @Metrics { lmbx9.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMnine-Slope }\n     @Family { LMnine }\n     @Face { Slope }\n     @Name { LMRoman9-Italic }\n     @Metrics { lmri9.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMnine-BoldSlope }\n     @Family { LMnine }\n     @Face { BoldSlope }\n     @Name { LMRoman9-BoldItalic }\n     @Metrics { lmbxi9.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n#######\n# LMten\n{\n@FontDef\n     @Tag { LMten-Base }\n     @Family { LMten }\n     @Face { Base }\n     @Name { LMRoman10-Regular }\n     @Metrics { lmr10.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMten-Bold }\n     @Family { LMten }\n     @Face { Bold }\n     @Name { LMRoman10-Bold }\n     @Metrics { lmbx10.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMten-Slope }\n     @Family { LMten }\n     @Face { Slope }\n     @Name { LMRoman10-Italic }\n     @Metrics { lmri10.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n{\n@FontDef\n     @Tag { LMten-BoldSlope }\n     @Family { LMten }\n     @Face { BoldSlope }\n     @Name { LMRoman10-BoldItalic }\n     @Metrics { lmbxi10.afm }\n     @Mapping { LtLatin1.LCM }\n}\n\n########\n# AMSYten\n{\n@FontDef\n     @Tag { AMSYten-Base }\n     @Family { AMSYten }\n     @Face { Base }\n     @Name { AMSSymbolA10-Regular }\n     @Metrics { msam10.afm }\n     @Mapping { AmsSymb.LCM }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"671cfa548818b74cc345c53537ef58b0ed626112","subject":"linker: align the lma to 4 bytes","message":"linker: align the lma to 4 bytes\n\nThis is needed when the flash can be accessed via a different vma\naddress as in the case of the infineon xmc4xxx series where 0xc000000\nis the uncached start address and 0x8000000 is the cached start address.\n\nSigned-off-by: Andriy Gelman <9b800b50c068448b0612a5bdc33ac199b44926a7@gmail.com>\n","repos":"zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"include\/zephyr\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_file":"include\/zephyr\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/devicetree_regions.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGIONS()\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t__rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\t. = ALIGN(4);\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__text_region_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end -__rom_region_start);\n\t__rom_region_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    GROUP_START(DATA_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_region_start = .;\n\t__data_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\t__data_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    \/* Sections generated from 'zephyr,memory-region' nodes *\/\n    LINKER_DT_SECTIONS()\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/devicetree_regions.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGIONS()\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t__rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__text_region_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end -__rom_region_start);\n\t__rom_region_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    GROUP_START(DATA_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_region_start = .;\n\t__data_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\t__data_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    \/* Sections generated from 'zephyr,memory-region' nodes *\/\n    LINKER_DT_SECTIONS()\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c65cf1cd15213c4a14def1494fb6723fe247b722","subject":"soc\/intel_adsp: Newlib heap should be uncached","message":"soc\/intel_adsp: Newlib heap should be uncached\n\nThe sentry symbols that mark the ends of the newlib heap area were\nbeing placed in cached memory, which violates the coherence rules.\n\nSigned-off-by: Andy Ross <c70f9a6bf6ee0cd69c8af4ce5e6b131945769315@intel.com>\n","repos":"zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v15\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v15\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n  *\/\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n\n  \/* Initial\/boot stack lives in the CPU0 interrupt stack *\/\n  __stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE;\n\n  \/* These symbols bound the newlib heap, which must be uncached *\/\n  . = SEGSTART_UNCACHED;\n  _end = .;\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n  *\/\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n\n  \/* Initial\/boot stack lives in the CPU0 interrupt stack *\/\n  __stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE;\n\n  _end = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8820d898c30ea99ad36dd56f4bf676ba82ca4c08","subject":"\u4fee\u6b63\u94fe\u63a5\u811a\u672c\u6ce8\u91ca","message":"\u4fee\u6b63\u94fe\u63a5\u811a\u672c\u6ce8\u91ca\n","repos":"geniusgogo\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,FlyLu\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread","old_file":"bsp\/stm32\/stm32f401-st-nucleo\/board\/linker_scripts\/link.lds","new_file":"bsp\/stm32\/stm32f401-st-nucleo\/board\/linker_scripts\/link.lds","new_contents":"\/*\n * linker script for STM32F4xx with GNU ld\n * bernard.xiong 2009-10-14\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512k \/* 512KB flash *\/\n    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  96k \/* 96K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        _etext = .;\n    } > ROM = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > ROM\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >RAM\n\n    .stack : \n    {\n        . = ALIGN(4);\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >RAM\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > RAM\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * linker script for STM32F4xx with GNU ld\n * bernard.xiong 2009-10-14\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512k \/* 1024KB flash *\/\n    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  96k \/* 128K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        _etext = .;\n    } > ROM = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > ROM\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >RAM\n\n    .stack : \n    {\n        . = ALIGN(4);\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >RAM\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > RAM\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c0f536be32593c98e0b224670d01d7c4b222cf71","subject":"Hopefully work around FreeBSD linker bug","message":"Hopefully work around FreeBSD linker bug\n\nSee https:\/\/sourceware.org\/ml\/binutils\/2009-08\/msg00512.html.\n","repos":"Weichen81\/solo5,mato\/solo5,Solo5\/solo5,mato\/solo5,Weichen81\/solo5,mato\/solo5,djwillia\/solo5,djwillia\/solo5,Solo5\/solo5,djwillia\/solo5,Weichen81\/solo5","old_file":"kernel\/virtio\/solo5.lds","new_file":"kernel\/virtio\/solo5.lds","new_contents":"ENTRY(_start)\n\nSECTIONS {\n    . = 0x100000;\n    \n    .bootstrap :\n    {\n        *(.bootstrap)\n    }\n\n    .text BLOCK(4K) : ALIGN(4K)\n    {\n        *(.text)\n    }\n\n    \/* Read-only data. *\/\n    .rodata BLOCK(4K) : ALIGN(4K)\n    {\n        *(.rodata)\n    }\n\n    \/* Read-write data (initialized) *\/\n    .data BLOCK(4K) : ALIGN(4K)\n    {\n        *(.data)\n    }\n    _edata = .;\n\n    \/* Read-write data (uninitialized) *\/\n    .bss BLOCK(4K) : ALIGN(4K)\n    {\n        *(COMMON)\n        *(.bss)\n    }\n    _ebss = .;\n    _end = .;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf64-x86-64\", \"elf64-x86-64\", \"elf64-x86-64\")\nOUTPUT_ARCH(i386:x86-64)\nENTRY(_start)\n\nSECTIONS {\n    . = 0x100000;\n    \n    .bootstrap :\n    {\n        *(.bootstrap)\n    }\n\n    .text BLOCK(4K) : ALIGN(4K)\n    {\n        *(.text)\n    }\n\n    \/* Read-only data. *\/\n    .rodata BLOCK(4K) : ALIGN(4K)\n    {\n        *(.rodata)\n    }\n\n    \/* Read-write data (initialized) *\/\n    .data BLOCK(4K) : ALIGN(4K)\n    {\n        *(.data)\n    }\n    _edata = .;\n\n    \/* Read-write data (uninitialized) *\/\n    .bss BLOCK(4K) : ALIGN(4K)\n    {\n        *(COMMON)\n        *(.bss)\n    }\n    _ebss = .;\n    _end = .;\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"d6fe64b785178134019ebe944df1185c623862d3","subject":"Add kernel_start variable","message":"Add kernel_start variable\n","repos":"Herbstein\/kernel-of-truth,awensaunders\/kernel-of-truth,iankronquist\/kernel-of-truth,awensaunders\/kernel-of-truth,awensaunders\/kernel-of-truth,Herbstein\/kernel-of-truth,iankronquist\/kernel-of-truth,iankronquist\/kernel-of-truth,iankronquist\/kernel-of-truth,iankronquist\/kernel-of-truth,Herbstein\/kernel-of-truth","old_file":"kernel\/arch\/x86\/linker.ld","new_file":"kernel\/arch\/x86\/linker.ld","new_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 1M;\n\tkernel_start = .;\n\n\t\/* First put the multiboot header, as it is required to be put very early\n\t   early in the image or the bootloader won't recognize the file format.\n\t   Next we'll put the .text section. *\/\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t\tkernel_end = .;\n\t}\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","old_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 1M;\n\n\t\/* First put the multiboot header, as it is required to be put very early\n\t   early in the image or the bootloader won't recognize the file format.\n\t   Next we'll put the .text section. *\/\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t\tkernel_end = .;\n\t}\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"99456a45da7387889a0a99e289711f48f60c683b","subject":"Edit linker to align sections to page size.","message":"Edit linker to align sections to page size.\n","repos":"RichardHScott\/os_c","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"ENTRY(_start)\n\nSECTIONS {\n  . = 1M;\n\n  .rodata :\n  {\n    \/* ensure that the multiboot header is at the beginning *\/\n    KEEP(*(.multiboot_header))\n    *(.rodata .rodata.*)\n    . = ALIGN(4K);\n  }\n\n  .text :\n  {\n    *(.text .text.*)\n    . = ALIGN(4K);\n  }\n\n  .data :\n  {\n    *(.data .data.*)\n    . = ALIGN(4K);\n  }\n\n  .bss :\n  {\n    *(.bss .bss.*)\n    . = ALIGN(4K);\n  }\n\n  .got :\n  {\n    *(.got)\n    . = ALIGN(4K);\n  }\n\n  .got.plt :\n  {\n    *(.got.plt)\n    . = ALIGN(4K);\n  }\n\n  .data.rel.ro : ALIGN(4K) {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n    . = ALIGN(4K);\n  }\n\n  .gcc_except_table : ALIGN(4K) {\n    *(.gcc_except_table)\n    . = ALIGN(4K);\n  }\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS {\n    . = 1M;\n\n    .boot :\n    {\n        \/* ensure that the multiboot header is at the beginning *\/\n        KEEP(*(.multiboot_header))\n    }\n\n    .text :\n    {\n        *(.text .text.*)\n    }\n\n    .rodata : {\n        *(.rodata .rodata.*)\n    }\n\n    .data.rel.ro : {\n        *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cdcf04ae23549cecaa39bb0e123d4e20651d67fe","subject":"Updated linker script","message":"Updated linker script\n","repos":"neviim\/mirus,neviim\/mirus,neviim\/mirus,neviim\/mirus","old_file":"build\/linker.ld","new_file":"build\/linker.ld","new_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n    \/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n       loaded at by the bootloader. *\/\n    . = 1M;\n\n    \/* First put the multiboot header, as it is required to be put very early\n       early in the image or the bootloader won't recognize the file format.\n       Next we'll put the .text section. *\/\n    .text BLOCK(4K) : ALIGN(4K)\n    {\n        *(.multiboot)\n        *(.text)\n    }\n\n    \/* Read-only data. *\/\n    .rodata BLOCK(4K) : ALIGN(4K)\n    {\n        *(.rodata)\n    }\n\n    \/* Read-write data (initialized) *\/\n    .data BLOCK(4K) : ALIGN(4K)\n    {\n        *(.data)\n    }\n\n    \/* Read-write data (uninitialized) and stack *\/\n    .bss BLOCK(4K) : ALIGN(4K)\n    {\n        *(COMMON)\n        *(.bss)\n        *(.bootstrap_stack)\n    }\n\n    \/* The compiler may produce other sections, by default it will put them in\n       a segment with the same name. Simply add stuff here as needed. *\/\n    end = .;\n}","old_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n    \/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n       loaded at by the bootloader. *\/\n    . = 1M;\n\n    \/* First put the multiboot header, as it is required to be put very early\n       early in the image or the bootloader won't recognize the file format.\n       Next we'll put the .text section. *\/\n    .text BLOCK(4K) : ALIGN(4K)\n    {\n        *(.multiboot)\n        *(.text)\n    }\n\n    \/* Read-only data. *\/\n    .rodata BLOCK(4K) : ALIGN(4K)\n    {\n        *(.rodata)\n    }\n\n    \/* Read-write data (initialized) *\/\n    .data BLOCK(4K) : ALIGN(4K)\n    {\n        *(.data)\n    }\n\n    \/* Read-write data (uninitialized) and stack *\/\n    .bss BLOCK(4K) : ALIGN(4K)\n    {\n        *(COMMON)\n        *(.bss)\n        *(.bootstrap_stack)\n    }\n\n    \/* The compiler may produce other sections, by default it will put them in\n       a segment with the same name. Simply add stuff here as needed. *\/\n    end = .; _end = .; __end = .;\n}","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"fa518a130a624778bbe9594ca5241a1c1233b936","subject":"DFU settings","message":"DFU settings\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa.ld","new_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa.ld","new_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x20000, LENGTH = 0x60000\r\n\tRAM (rwx) :  ORIGIN = 0x20002200, LENGTH = 0xde00\r\n\t\/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n\t*  from application to bootloader when using buttonluss DFU OTA.\r\n\t*\/\r\n\tNOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n\t\/** Location of bootloader setting in flash. *\/\r\n\tBOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n}\r\n\r\n\r\nSECTIONS\r\n{\r\n\t\/* Place the bootloader settings page in flash. *\/\r\n\t.bootloaderSettings(NOLOAD) :\r\n\t{\r\n\r\n\t} > BOOTLOADER_SETTINGS\r\n\r\n\t\/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n\t.noinit(NOLOAD) :\r\n\t{\r\n\r\n\t} > NOINIT\r\n}\r\n\r\nSECTIONS\r\n{\r\n  .pwr_mgmt_data :\r\n  {\r\n    PROVIDE(__start_pwr_mgmt_data = .);\r\n    KEEP(*(.pwr_mgmt_data))\r\n    PROVIDE(__stop_pwr_mgmt_data = .);\r\n  } > FLASH\r\n} INSERT AFTER .text\r\n\r\nSECTIONS\r\n{\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","old_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x20000, LENGTH = 0x60000\r\n\tRAM (rwx) :  ORIGIN = 0x20002200, LENGTH = 0xde00\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"36d8852194e9dc7d17bcbf1e544cc8b2bf090e54","subject":"feat(ld): Put rodata into flash by default","message":"feat(ld): Put rodata into flash by default\n\nexcept rodata in libpp.a\n","repos":"espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK","old_file":"components\/esp8266\/ld\/eagle.app.v6.common.ld","new_file":"components\/esp8266\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *libcore.a:spi_flash.o(.literal .text .literal.* .text.*)\n    *(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *libpp.a:(.rodata.* .rodata)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.rodata.* .rodata .irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n\n    . = ALIGN(16);\n    __start_ksymatabesp_socket = .;\n    *(ksymatabesp_socket)\n    __stop_ksymatabesp_socket = .;\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n}\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *libcore.a:spi_flash.o(.literal .text .literal.* .text.*)\n    *(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *libuser.a:(.rodata.* .rodata)\n    *libcirom.a:(.rodata.* .rodata)\n    *libmbedtls.a:(.rodata.* .rodata)\n    *libssl.a:(.rodata.* .rodata)\n    *libopenssl.a:(.rodata.* .rodata)\n    *libplatforms.a:(.rodata.* .rodata)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n\n    . = ALIGN(16);\n    __start_ksymatabesp_socket = .;\n    *(ksymatabesp_socket)\n    __stop_ksymatabesp_socket = .;\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8e6add58b039b8a55bb994996fda6a2eb2e18128","subject":"Revert \"arm64: linker: define z_mapped_* symbols\"","message":"Revert \"arm64: linker: define z_mapped_* symbols\"\n\nThis reverts commit 9559223c7b4cc56506d04de72149cad58a4817a8.\n\nSigned-off-by: Anas Nashif <0d9952ec84ac43c159f6b7e7ed99a9080c00dd6e@intel.com>\n","repos":"finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_NAME))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_NAME))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n    z_mapped_size = z_mapped_end - z_mapped_start;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e41063d40e99807016f4ee560c0b5c71358d7c78","subject":"cpu\/riscv_common: fix undeclared memory region linker error","message":"cpu\/riscv_common: fix undeclared memory region linker error\n\nSince commit 3a11b1fbd280b2b46ef0a8011bead180800f83c2 (#16972)\nbuilding RIOT applications with `BOARD=hifive1` causes the following\nlinker error to be emitted on my system:\n\n\t\/opt\/rv32imc\/lib\/gcc\/riscv32-unknown-elf\/10.2.0\/..\/..\/..\/..\/riscv32-unknown-elf\/bin\/ld:riscv_base.ld:220: warning: memory region `rom' not declared\n\nThis is due to the fact that the RISC-V linker script doesn't have a rom\nmemory region. While many other ARM-based boards have a rom memory\nregion defined in the linker script, the corresponding region name in\nthe RISC-V linker script is flash and rom is not declared as a memory\nregion hence the warning.\n\nI think this was accidentally overlooked in\n3a11b1fbd280b2b46ef0a8011bead180800f83c2. It is fixed in this commit by\nreplacing the rom region with the flash region. The linker script\nidentifiers (e.g. _srom and _erom) are not renamed.\n","repos":"kaspar030\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,miri64\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,kaspar030\/RIOT","old_file":"cpu\/riscv_common\/ldscripts\/riscv_base.ld","new_file":"cpu\/riscv_common\/ldscripts\/riscv_base.ld","new_contents":"\/*\n * Copyright (C) 2017, 2019   Ken Rabold\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_riscv_common\n * @{\n *\n * @file\n * @brief           Common linker directives for the RISC-V CPU\n *\n * @author          Ken Rabold\n *\n * @}\n *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nPHDRS\n{\n  flash PT_LOAD;\n  ram_init PT_LOAD;\n  ram PT_NULL;\n  tls PT_TLS;\n}\n\nSECTIONS\n{\n  __stack_size     = DEFINED(__stack_size) ? __stack_size : 256;\n\n  \/* Populate information about rom size *\/\n  _srom = ORIGIN(flash);\n  _erom = ORIGIN(flash) + LENGTH(flash);\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash AT>flash :flash\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >flash AT>flash :flash\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >flash AT>flash :flash\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    KEEP (*(SORT(.roxfa.*)))\n  } >flash AT>flash :flash\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash AT>flash :flash\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash AT>flash :flash\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash AT>flash :flash\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash AT>flash :flash\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash AT>flash :flash\n\n  \/*\n   * TLS relocations are offsets relative to the address\n   * of the first TLS symbol. That means we just need to\n   * allocate them all together so that the TLS region\n   * is compact when allocated for each thread.\n   *\/\n\n  \/*\n   * TLS initialization data is loaded into ROM so that\n   * each thread can get its values initialized from there\n   * at startup\n   *\/\n  .tdata :\n  {\n       __tdata_start = .;\n      *(.tdata .tdata.* .gnu.linkonce.td.*)\n      __tdata_end = .;\n  } >flash AT>flash :tls\n  __tdata_source = LOADADDR(.tdata);\n  __tdata_size = SIZEOF(.tdata);\n\n  \/*\n   * TLS zeroed data is relocated as if it immediately followed\n   * the tdata values. However, the linker 'magically' erases the\n   * memory allocation so that no ROM is consumed by this\n   * section\n   *\/\n  .tbss :\n  {\n      *(.tbss .tbss.* .gnu.linkonce.tb.*)\n      *(.tcommon)\n      __tbss_end = .;\n  } >flash : tls\n  __tls_size = __tbss_end - __tdata_start;\n  __tbss_size = __tls_size - __tdata_size;\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash AT>flash :flash\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash :ram_init\n\n  .data          :\n  {\n    *(.ramfunc .ramfunc.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n    KEEP (*(SORT(.xfa.*)))\n  } >ram AT>flash :ram_init\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram AT>ram :ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n  PROVIDE( _sheap = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _eheap = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram AT>ram :ram\n\n  .end_fw (NOLOAD) : ALIGN(4) {\n    _end_fw = . ;\n  } > flash\n}\n","old_contents":"\/*\n * Copyright (C) 2017, 2019   Ken Rabold\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_riscv_common\n * @{\n *\n * @file\n * @brief           Common linker directives for the RISC-V CPU\n *\n * @author          Ken Rabold\n *\n * @}\n *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nPHDRS\n{\n  flash PT_LOAD;\n  ram_init PT_LOAD;\n  ram PT_NULL;\n  tls PT_TLS;\n}\n\nSECTIONS\n{\n  __stack_size     = DEFINED(__stack_size) ? __stack_size : 256;\n\n  \/* Populate information about rom size *\/\n  _srom = ORIGIN(rom);\n  _erom = ORIGIN(rom) + LENGTH(rom);\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash AT>flash :flash\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >flash AT>flash :flash\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >flash AT>flash :flash\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    KEEP (*(SORT(.roxfa.*)))\n  } >flash AT>flash :flash\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash AT>flash :flash\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash AT>flash :flash\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash AT>flash :flash\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash AT>flash :flash\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash AT>flash :flash\n\n  \/*\n   * TLS relocations are offsets relative to the address\n   * of the first TLS symbol. That means we just need to\n   * allocate them all together so that the TLS region\n   * is compact when allocated for each thread.\n   *\/\n\n  \/*\n   * TLS initialization data is loaded into ROM so that\n   * each thread can get its values initialized from there\n   * at startup\n   *\/\n  .tdata :\n  {\n       __tdata_start = .;\n      *(.tdata .tdata.* .gnu.linkonce.td.*)\n      __tdata_end = .;\n  } >flash AT>flash :tls\n  __tdata_source = LOADADDR(.tdata);\n  __tdata_size = SIZEOF(.tdata);\n\n  \/*\n   * TLS zeroed data is relocated as if it immediately followed\n   * the tdata values. However, the linker 'magically' erases the\n   * memory allocation so that no ROM is consumed by this\n   * section\n   *\/\n  .tbss :\n  {\n      *(.tbss .tbss.* .gnu.linkonce.tb.*)\n      *(.tcommon)\n      __tbss_end = .;\n  } >flash : tls\n  __tls_size = __tbss_end - __tdata_start;\n  __tbss_size = __tls_size - __tdata_size;\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash AT>flash :flash\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash :ram_init\n\n  .data          :\n  {\n    *(.ramfunc .ramfunc.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n    KEEP (*(SORT(.xfa.*)))\n  } >ram AT>flash :ram_init\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram AT>ram :ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n  PROVIDE( _sheap = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _eheap = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram AT>ram :ram\n\n  .end_fw (NOLOAD) : ALIGN(4) {\n    _end_fw = . ;\n  } > rom\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"0ca476069a27856e5554364366c709bf5f1606d6","subject":"Specify output arch","message":"Specify output arch\n","repos":"tailix\/kernelmq,tailix\/kernelmq","old_file":"arch\/linker.ld","new_file":"arch\/linker.ld","new_contents":"OUTPUT_ARCH(\"i386\")\nENTRY(_start)\n\nSECTIONS\n{\n    . = 1M;\n\n    .text BLOCK(4K) : ALIGN(4K)\n    {\n        *(.multiboot)\n        *(.text)\n    }\n\n    .rodata BLOCK(4K) : ALIGN(4K)\n    {\n        *(.rodata)\n    }\n\n    .data BLOCK(4K) : ALIGN(4K)\n    {\n        *(.data)\n    }\n\n    .bss BLOCK(4K) : ALIGN(4K)\n    {\n        *(COMMON)\n        *(.bss)\n    }\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS\n{\n    . = 1M;\n\n    .text BLOCK(4K) : ALIGN(4K)\n    {\n        *(.multiboot)\n        *(.text)\n    }\n\n    .rodata BLOCK(4K) : ALIGN(4K)\n    {\n        *(.rodata)\n    }\n\n    .data BLOCK(4K) : ALIGN(4K)\n    {\n        *(.data)\n    }\n\n    .bss BLOCK(4K) : ALIGN(4K)\n    {\n        *(COMMON)\n        *(.bss)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7df0212b925a937b374aaa7413abb2454548a64b","subject":"feat(ld): add \"ets_printf\" to rom link file","message":"feat(ld): add \"ets_printf\" to rom link file\n","repos":"espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK","old_file":"components\/esp8266\/ld\/eagle.rom.addr.v6.ld","new_file":"components\/esp8266\/ld\/eagle.rom.addr.v6.ld","new_contents":"PROVIDE ( SPI_sector_erase = 0x400040c0 );\nPROVIDE ( SPI_page_program = 0x40004174 );\nPROVIDE ( SPI_read_data = 0x400042ac );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( Disable_QMode = 0x40004508 );\n\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\n\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\n\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\n\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\n\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\n\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\n\nPROVIDE ( ets_printf = 0x400024cc );","old_contents":"PROVIDE ( SPI_sector_erase = 0x400040c0 );\nPROVIDE ( SPI_page_program = 0x40004174 );\nPROVIDE ( SPI_read_data = 0x400042ac );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( Disable_QMode = 0x40004508 );\n\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\n\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\n\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\n\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\n\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\n\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"07f7ae6327725b2f6d91e4c360d4e811334f51fd","subject":"fixed tabbing of lga.lds","message":"fixed tabbing of lga.lds\n","repos":"attie\/linker-generated-array,m-wichmann\/linker-generated-array","old_file":"lga.lds","new_file":"lga.lds","new_contents":"SECTIONS {\n\t__lga_start = .;\n\t.lga : {\n\t\tKEEP(*(SORT(.lga_*)));\n\t}\n\t__lga_end = .;\n}\nINSERT BEFORE .bss;\n","old_contents":"SECTIONS {\n  __lga_start = .;\n  .lga : {\n    KEEP(*(SORT(.lga_*)));\n  }\n\t__lga_end = .;\n}\nINSERT BEFORE .bss;\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4eace423f3d8fd84498e92e55250eaf3006a03b1","subject":"[kernel] Merge all .ctors.* sections into .ctors","message":"[kernel] Merge all .ctors.* sections into .ctors\n\nWith GCC >= 7.0, when -fprofile-arcs is passed as option, the per-TU ctors\nare placed in .ctors.NNN (where NNN is just a number) instead of in .ctors\nas with older compilers. That made Tilck's call_kernel_global_ctors() to stop\ncalling those ctors simply because the function just calls the function\npointers in the \".ctors\" section and doesn't know about the other one.\n\nTo avoid this problem, kernel's linker script has been updated to merge\nany .ctors.* sections in one single section called \".ctors\".\n","repos":"vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs","old_file":"kernel\/arch\/i386\/linker_script.ld","new_file":"kernel\/arch\/i386\/linker_script.ld","new_contents":"\/* SPDX-License-Identifier: BSD-2-Clause *\/\n\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib32\");\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib\");\n\nkernel_base_va      = @KERNEL_BASE_VA@;\nkernel_paddr        = @KERNEL_PADDR@;\nkernel_text_paddr   = kernel_paddr + 0x1000;\n\nPHDRS\n{\n   ro_segment PT_LOAD FILEHDR PHDRS;\n   rw_segment PT_LOAD;\n   special_ro PT_LOAD;\n}\n\nSECTIONS\n{\n   . = SEGMENT_START(\"text-segment\", kernel_base_va + kernel_text_paddr);\n\n   .text : AT(kernel_text_paddr)\n   {\n      text = .;\n      *(.text.start)\n      *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n      *(.text.exit .text.exit.*)\n      *(.text.startup .text.startup.*)\n      *(.text.hot .text.hot.*)\n      *(.text .stub .text.* .gnu.linkonce.t.*)\n   } : ro_segment\n\n   .rodata : AT(kernel_text_paddr + (rodata - text))\n   {\n      rodata = .;\n      *(.rodata .rodata.* .gnu.linkonce.r.*)\n   } : ro_segment\n\n   .ctors : AT(kernel_text_paddr + (ctors - text))\n   {\n      ctors = .;\n      *(.ctors .ctors.*)\n   } : ro_segment\n\n   .tilck_info : AT(kernel_text_paddr + (tilck_info - text))\n   {\n      tilck_info = .;\n      *(.tilck_info)\n   } : ro_segment\n\n   .data ALIGN(4K) : AT(kernel_text_paddr + (data - text))\n   {\n      data = .;\n      *(.data .data.* .gnu.linkonce.d.*)\n   } : rw_segment\n\n   .bss : AT(kernel_text_paddr + (bss - text))\n   {\n      bss = .;\n      *(.bss .bss.* .gnu.linkonce.b.*)\n   } : rw_segment\n\n   .Symtab ALIGN(4K) : AT(kernel_text_paddr + (Symtab - text))\n   {\n      Symtab = .;\n      *(.Symtab)\n   } : special_ro\n\n   .Strtab ALIGN(4): AT(kernel_text_paddr + (Strtab - text))\n   {\n      Strtab = .;\n      *(.Strtab)\n   } : special_ro\n\n   _end = .;\n\n   \/* Completely drop out from the file the following sections *\/\n   \/DISCARD\/ : { *(.eh_frame* .dtors .dtors.*) }\n}\n\n\n","old_contents":"\/* SPDX-License-Identifier: BSD-2-Clause *\/\n\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib32\");\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib\");\n\nkernel_base_va      = @KERNEL_BASE_VA@;\nkernel_paddr        = @KERNEL_PADDR@;\nkernel_text_paddr   = kernel_paddr + 0x1000;\n\nPHDRS\n{\n   ro_segment PT_LOAD FILEHDR PHDRS;\n   rw_segment PT_LOAD;\n   special_ro PT_LOAD;\n}\n\nSECTIONS\n{\n   . = SEGMENT_START(\"text-segment\", kernel_base_va + kernel_text_paddr);\n\n   .text : AT(kernel_text_paddr)\n   {\n      text = .;\n      *(.text.start)\n      *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n      *(.text.exit .text.exit.*)\n      *(.text.startup .text.startup.*)\n      *(.text.hot .text.hot.*)\n      *(.text .stub .text.* .gnu.linkonce.t.*)\n   } : ro_segment\n\n   .rodata : AT(kernel_text_paddr + (rodata - text))\n   {\n      rodata = .;\n      *(.rodata .rodata.* .gnu.linkonce.r.*)\n   } : ro_segment\n\n   .tilck_info : AT(kernel_text_paddr + (tilck_info - text))\n   {\n      tilck_info = .;\n      *(.tilck_info)\n   } : ro_segment\n\n   .data ALIGN(4K) : AT(kernel_text_paddr + (data - text))\n   {\n      data = .;\n      *(.data .data.* .gnu.linkonce.d.*)\n   } : rw_segment\n\n   .bss : AT(kernel_text_paddr + (bss - text))\n   {\n      bss = .;\n      *(.bss .bss.* .gnu.linkonce.b.*)\n   } : rw_segment\n\n   .Symtab ALIGN(4K) : AT(kernel_text_paddr + (Symtab - text))\n   {\n      Symtab = .;\n      *(.Symtab)\n   } : special_ro\n\n   .Strtab ALIGN(4): AT(kernel_text_paddr + (Strtab - text))\n   {\n      Strtab = .;\n      *(.Strtab)\n   } : special_ro\n\n   _end = .;\n\n   \/* Completely drop out from the file the following sections *\/\n   \/DISCARD\/ : { *(.eh_frame*) }\n}\n\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"41202b00b9e6d5465e617ab3996106e540ec714a","subject":"\tMiscelaneous changes.","message":"\tMiscelaneous changes.\n\n\t* ARM Thumb interwork damn bit.\n\t* RCC registers.\n\t* IOPCENR register (Just for test.)\n\t* Comments.\n\t* Some alignments (not sure if necessary).\n\t* Typos.\n\t* Others.\n","repos":"masilvabustos\/CabbageOS,masilvabustos\/CabbageOS","old_file":"lib\/ldscripts\/stm32f100xx.ld","new_file":"lib\/ldscripts\/stm32f100xx.ld","new_contents":"\nSECTIONS {\n\t\n\t__end_of_ram = ALIGN(ORIGIN(SRAM) + LENGTH(SRAM), 4) ;\n\n\t.cm3.isr_vector ORIGIN(FLASH) : {\n\t\tLONG(__end_of_ram)\n\t\t\/* ARM Thumb interwork requires the LSB to be set.\t*\n\t\t * (Can ld do this automatically?) \t\t\t*\/ \t\t\t\n\t\tLONG(Reset \t\t| 1)\n\t\tLONG(NMI_Handler \t| 1)\n\t\tLONG(HardFault_Handler \t| 1)\n\t\tLONG(MemManage_Handler \t| 1)\n\t\tLONG(BusFault_Handler \t| 1)\n\t\tLONG(UsageFault_Handler | 1)\n\t\t. = 0x2c ; \/* Reserved *\/\n\t\tLONG(SVC_Handler \t| 1)\n\t\tLONG(DebugMon_Handler\t| 1)\n\t\t. = 0x38 ; \/* Reserved *\/\n\t\tLONG(PendSV_Handler\t| 1)\n\t\tLONG(SysTick_Handler\t| 1)\n\n\t\t* (.isr_vector) \/* IRQs *\/\n\t\t\n\t\t. = 0x150 ; \/* Max. vector size? *\/\n\n\t} > FLASH\n\n\n\t.text : { \n\t\t. = ALIGN(4) ;\n\t\t* (.text) \n\t} > FLASH\n\t\n\t__init_data_start = . ;\n\t.data : AT(__init_data_start) { \n\t\t* (.data) \n\t} > SRAM\n\t__init_data_end = . ;\n\n\t.bss : {\n\t\t* (.bss)\n\t} > SRAM\n\n\t__brk = . ;\n\n\t.stm32f100xx.peripherals_registers : {\n\n\t\t\/* TODO: Add remaing registers *\/\n\t\t. = 0x10800 ;\n\t\tGPIOA_CRL \t= . + 0x00 ;\n\t\tGPIOA_CRH \t= . + 0x04 ;\n\t\tGPIOA_IDR \t= . + 0x08 ;\n\t\tGPIOA_ODR \t= . + 0x0C ;\n\t\tGPIOA_BSRR \t= . + 0x10 ;\n\t\tGPIOA_BRR\t= . + 0x14 ;\n\t\tGPIOA_LCKR\t= . + 0x18 ;\n\t\t\n\t\t. = 0x11000 ;\n\t\tGPIOC_CRL \t= . + 0x00 ;\n\t\tGPIOC_CRH \t= . + 0x04 ;\n\t\tGPIOC_IDR \t= . + 0x08 ;\n\t\tGPIOC_ODR \t= . + 0x0C ;\n\t\tGPIOC_BSRR \t= . + 0x10 ;\n\t\tGPIOC_BRR\t= . + 0x14 ;\n\t\tGPIOC_LCKR\t= . + 0x18 ;\n\n\t\t. = 0x21000 ;\n\t\tRCC_CR\t\t= . + 0x00 ;\n\t\tRCC_CFGR\t= . + 0x04 ;\n\t\tRCC_CIR\t\t= . + 0x08 ;\n\t\tRCC_APB2RSTR\t= . + 0x0C ;\n\t\tRCC_APB1RSTR \t= . + 0x10 ;\n\t\tRCC_AHBENR\t= . + 0x14 ;\n\t\tRCC_APB2ENR\t= . + 0x18 ;\n\t\tRCC_APB1ENR\t= . + 0x1C ;\n\t\tRCC_BDCR\t= . + 0x20 ;\n\t\tRCC_CSR\t\t= . + 0x24 ;\n\t\tRCC_CFGR2\t= . + 0x2C ;\n\n\n\t} > PERIPH\n\n\t.stm32f100xx.peripherals_bitband_alias 0x42000000 : {\n\n\t\t. \t\t= (RCC_APB2ENR \t- ORIGIN(PERIPH)) * 32 ;\n\t\tIOPCEN\t\t=  . +  4 * 4 ;\n\n\t} > PERIPH\t\n}\n\n","old_contents":"\nSECTIONS {\n\t\n\t__end_of_ram = ALIGN(ORIGIN(SRAM) + LENGTH(SRAM), 4) ;\n\n\t.cm3.isr_vector ORIGIN(FLASH) : {\n\t\tLONG(__end_of_ram)\n\t\tLONG(Reset)\n\t\tLONG(NMI_Handler)\n\t\tLONG(HardFault_Handler)\n\t\tLONG(MemManage_Handler)\n\t\tLONG(BusFault_Handler)\n\t\t. = 0x2c ;\n\t\tLONG(SVC_Handler)\n\t\tLONG(DebugMon_Handler)\n\t\t. = 0x38 ;\n\t\tLONG(PSV_Handler)\n\t\tLONG(SysTick_Handler)\n\n\t\t* (.isr_vector)\n\n\t} > FLASH\n\n\t.text : { \n\t\t* (.text) \n\t} > FLASH\n\n\t.data : AT(ADDR(.text) + SIZEOF(.text)) { \n\t\t* (.data) \n\t} > SRAM\n\n\t.bss : {\n\t\t* (.bss)\n\t} > SRAM\n\n\t__brk = . ;\n\n\t.stm32f100xx.preripherals_registers : {\n\t\t. = 0x10800 ;\n\t\tGPIOA_CRL \t= . + 0x00 ;\n\t\tGPIOA_CRH \t= . + 0x04 ;\n\t\tGPIOA_IDR \t= . + 0x08 ;\n\t\tGPIOA_ODR \t= . + 0x0C ;\n\t\tGPIOA_BSRR \t= . + 0x10 ;\n\t\tGPIOA_BRR\t= . + 0x14 ;\n\t\tGPIOA_LCKR\t= . + 0x18 ;\n\t\t\n\t\t. = 0x11000 ;\n\t\tGPIOC_CRL \t= . + 0x00 ;\n\t\tGPIOC_CRH \t= . + 0x04 ;\n\t\tGPIOC_IDR \t= . + 0x08 ;\n\t\tGPIOC_ODR \t= . + 0x0C ;\n\t\tGPIOC_BSRR \t= . + 0x10 ;\n\t\tGPIOC_BRR\t= . + 0x14 ;\n\t\tGPIOC_LCKR\t= . + 0x18 ;\n\t\n\n\n\n\n\t\t\n\t} > PERIPH\n\n\t\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"35763fb02f1787e8060b024f863fc2033c371051","subject":"add bss section to the linker script","message":"add bss section to the linker script\n","repos":"RWTH-OS\/eduOS-rs","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nOUTPUT_FORMAT(\"elf64-x86-64\")\nOUTPUT_ARCH(\"i386:x86-64\")\nENTRY(start)\n\nSECTIONS {\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n\tkernel_start = .;\n    .boot :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n    }\n\n    .text ALIGN(4096) : AT(ADDR(.text))\n    {\n        *(.text)\n\t\t*(.text.*)\n    }\n\n\t.rodata : AT(ADDR(.rodata))\n\t{\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t}\n\n\t.data ALIGN(4096) : AT(ADDR(.data))\n    {\n        *(.data)\n\t\t*(.data.*)\n    }\n\n\t.bss ALIGN(4096) : AT(ADDR(.bss))\n    {\n\t\t__bss_start = .;\n        *(.bss)\n\t\t*(.bss.*)\n    }\n\tkernel_end = .;\n}\n","old_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nOUTPUT_FORMAT(\"elf64-x86-64\")\nOUTPUT_ARCH(\"i386:x86-64\")\nENTRY(start)\n\nSECTIONS {\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .boot :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n    }\n\n    .text ALIGN(4096) : AT(ADDR(.text))\n    {\n        *(.text)\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c058fe0a052d2a1da1ee0c7a30af91ae2e1fefa6","subject":"custom linker script creates reserved portion in high flash mem","message":"custom linker script creates reserved portion in high flash mem\n\nreserved space intended for rules storage\n","repos":"PDXostc\/can_firewall_software,PDXostc\/can_firewall_software","old_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-avr32\", \"elf32-avr32\",\n\t      \"elf32-avr32\")\nOUTPUT_ARCH(avr32:uc)\nENTRY(_start)\nSEARCH_DIR(\"\/home\/toolsbuild\/jenkins-knuth\/workspace\/avr32-gnu-toolchain\/avr32-gnu-toolchain-win32_x86\/avr32\/lib\");\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY\n{\n    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K-10K-8K\n\t\tRSVDFLASH (rxai!w) : ORIGIN = 0x80000000+512K-10K-8K, LENGTH = 10K\n    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC\n    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512\n    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512\n    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8\n    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8\n}\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;\n\t\/* Next line should not be necessary for use of flash for storing rules *\/\n\t\/* .rsvd_flash : { *(.rsvd_flash) } >RSVDFLASH AT>RSVDFLASH *\/\n  .interp         : { *(.interp) } >FLASH AT>FLASH\n  .reset : {  *(.reset) } >FLASH AT>FLASH\n  .hash           : { *(.hash) } >FLASH AT>FLASH\n  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH\n  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH\n  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH\n  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH\n  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH\n  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH\n  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH\n  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH\n  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH\n  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH\n  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH\n  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH\n  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH\n  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH\n  .init           :\n  {\n    KEEP (*(.init))\n  } >FLASH AT>FLASH =0xd703d703\n  .plt            : { *(.plt) } >FLASH AT>FLASH\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } >FLASH AT>FLASH =0xd703d703\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } >FLASH AT>FLASH =0xd703d703\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH\n  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH\n  .dalign\t: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH\n  PROVIDE (_data = ORIGIN(CPUSRAM));\n  . = ORIGIN(CPUSRAM);\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  PROVIDE (__preinit_array_start = ALIGN(32 \/ 8));\n  .preinit_array     : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >CPUSRAM AT>FLASH\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >CPUSRAM AT>FLASH\n  .jcr            : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH\n  .dynamic        : { *(.dynamic) } >CPUSRAM AT>FLASH\n  .got            : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH\n  .data           :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  } >CPUSRAM AT>FLASH\n  .data1          : { *(.data1) } >CPUSRAM AT>FLASH\n  .balign\t: { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(8);\n  } >CPUSRAM\n  . = ALIGN(8);\n  _end = .;\n  PROVIDE (end = .);\n  __heap_start__ = ALIGN(8);\n  . = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;\n  __heap_end__ = .;\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :\n  {\n    _stack = .;\n    *(.stack)\n    . = _stack_size;\n    _estack = .;\n  } >CPUSRAM\n  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE\n  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE\n\t.flash : { *(.flash .flash.*) } >FLASH AT>FLASH\n\t.rsvd_flash : { *(.rsvd_flash .rsvd_flash.*) } >RSVDFLASH AT>RSVDFLASH\n  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE\n  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-avr32\", \"elf32-avr32\",\n\t      \"elf32-avr32\")\nOUTPUT_ARCH(avr32:uc)\nENTRY(_start)\nSEARCH_DIR(\"\/home\/toolsbuild\/jenkins-knuth\/workspace\/avr32-gnu-toolchain\/avr32-gnu-toolchain-win32_x86\/avr32\/lib\");\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY\n{\n    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K\n    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC\n    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512\n    FACTORYPAGE : ORIGIN = 0x80800100, LENGTH = 512\n    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8\n    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8\n}\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;\n  .interp         : { *(.interp) } >FLASH AT>FLASH\n  .reset : {  *(.reset) } >FLASH AT>FLASH\n  .hash           : { *(.hash) } >FLASH AT>FLASH\n  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH\n  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH\n  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH\n  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH\n  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH\n  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH\n  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH\n  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH\n  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH\n  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH\n  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH\n  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH\n  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH\n  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH\n  .init           :\n  {\n    KEEP (*(.init))\n  } >FLASH AT>FLASH =0xd703d703\n  .plt            : { *(.plt) } >FLASH AT>FLASH\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } >FLASH AT>FLASH =0xd703d703\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } >FLASH AT>FLASH =0xd703d703\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH\n  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH\n  .dalign\t: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH\n  PROVIDE (_data = ORIGIN(CPUSRAM));\n  . = ORIGIN(CPUSRAM);\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  PROVIDE (__preinit_array_start = ALIGN(32 \/ 8));\n  .preinit_array     : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >CPUSRAM AT>FLASH\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >CPUSRAM AT>FLASH\n  .jcr            : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH\n  .dynamic        : { *(.dynamic) } >CPUSRAM AT>FLASH\n  .got            : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH\n  .data           :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  } >CPUSRAM AT>FLASH\n  .data1          : { *(.data1) } >CPUSRAM AT>FLASH\n  .balign\t: { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(8);\n  } >CPUSRAM\n  . = ALIGN(8);\n  _end = .;\n  PROVIDE (end = .);\n  __heap_start__ = ALIGN(8);\n  . = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;\n  __heap_end__ = .;\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :\n  {\n    _stack = .;\n    *(.stack)\n    . = _stack_size;\n    _estack = .;\n  } >CPUSRAM\n  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE\n  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE\n  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE\n  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"f907139fab2bfeb9dcf42430dc61a363c2e27a97","subject":"nrf\/boards\/common.ld: Avoid overflowing the .text region.","message":"nrf\/boards\/common.ld: Avoid overflowing the .text region.\n\nSimilar commit to this one:\nhttps:\/\/github.com\/tralamazza\/micropython\/commit\/6e56e6269f467e59316b5e4cb04ea37ab6a0dfe3\n\nWhen .text + .data oveflow available flash, the linker may not show an\nerror. This change makes sure .data is included in the size calculation.\n","repos":"pfalcon\/micropython,tobbad\/micropython,henriknelson\/micropython,pramasoul\/micropython,kerneltask\/micropython,bvernoux\/micropython,MrSurly\/micropython,MrSurly\/micropython,pramasoul\/micropython,henriknelson\/micropython,pfalcon\/micropython,tobbad\/micropython,kerneltask\/micropython,pozetroninc\/micropython,bvernoux\/micropython,kerneltask\/micropython,henriknelson\/micropython,henriknelson\/micropython,selste\/micropython,pfalcon\/micropython,henriknelson\/micropython,tobbad\/micropython,MrSurly\/micropython,tobbad\/micropython,bvernoux\/micropython,pozetroninc\/micropython,selste\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,pozetroninc\/micropython,trezor\/micropython,pfalcon\/micropython,MrSurly\/micropython,pfalcon\/micropython,trezor\/micropython,kerneltask\/micropython,kerneltask\/micropython,adafruit\/circuitpython,pozetroninc\/micropython,trezor\/micropython,pozetroninc\/micropython,pramasoul\/micropython,adafruit\/circuitpython,MrSurly\/micropython,trezor\/micropython,bvernoux\/micropython,selste\/micropython,bvernoux\/micropython,selste\/micropython,selste\/micropython,pramasoul\/micropython,pramasoul\/micropython,trezor\/micropython,adafruit\/circuitpython,tobbad\/micropython","old_file":"ports\/nrf\/boards\/common.ld","new_file":"ports\/nrf\/boards\/common.ld","new_contents":"\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n        *(.text)             \/* .text sections (code) *\/\n        *(.text*)            \/* .text* sections (code) *\/\n        *(.rodata)           \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)          \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/      \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/      \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;          \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n     \n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n        \n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n        \n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT>FLASH_TEXT\n            \n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\tPROVIDE ( end = . );\n\tPROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n_flash_user_start = ORIGIN(FLASH_USER);\n_flash_user_end   = ORIGIN(FLASH_USER) + LENGTH(FLASH_USER);\n","old_contents":"\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n        *(.text)             \/* .text sections (code) *\/\n        *(.text*)            \/* .text* sections (code) *\/\n        *(.rodata)           \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)          \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/      \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/      \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;          \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n     \n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n        \n    \/* used by the startup to initialize data *\/\n    _sidata = .;\n        \n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM \n            \n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\tPROVIDE ( end = . );\n\tPROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n_flash_user_start = ORIGIN(FLASH_USER);\n_flash_user_end   = ORIGIN(FLASH_USER) + LENGTH(FLASH_USER);\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"403753142456c63905288644cf08f746957014ba","subject":"Fix h1b_tests' layout.ld: apps now start at 0x14000.","message":"Fix h1b_tests' layout.ld: apps now start at 0x14000.\n","repos":"google\/tock-on-titan,google\/tock-on-titan,google\/tock-on-titan","old_file":"userspace\/layout.ld","new_file":"userspace\/layout.ld","new_contents":"\/* Copyright 2018 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nMEMORY {\n  FLASH (rx) : ORIGIN = 0x00066040, LENGTH = 0x0001FFC0\n  SRAM (rwx) : ORIGIN = 0x00014000, LENGTH = 0x0000c000\n}\n\nMPU_MIN_ALIGN = 8K;\n\nINCLUDE ..\/third_party\/libtock-rs\/layout.ld\n","old_contents":"\/* Copyright 2018 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nMEMORY {\n  FLASH (rx) : ORIGIN = 0x00066040, LENGTH = 0x0001FFC0\n  SRAM (rwx) : ORIGIN = 0x00018000, LENGTH = 0x00008000\n}\n\nMPU_MIN_ALIGN = 8K;\n\nINCLUDE ..\/third_party\/libtock-rs\/layout.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6101a7cd5f07db91f26102af6e2f0bdcee7b26cc","subject":"[doc] don't require luadoc compatibility","message":"[doc] don't require luadoc compatibility\n","repos":"3scale\/docker-gateway,3scale\/apicast,3scale\/apicast,3scale\/apicast,3scale\/apicast,3scale\/docker-gateway","old_file":"doc\/config.ld","new_file":"doc\/config.ld","new_contents":"file = {\n  '..\/gateway\/src\/apicast',\n  '..\/gateway\/src\/resty',\n}\ndir = '..\/doc\/lua'\nproject = 'APIcast'\ntitle = 'NGINX based API gateway used to integrate your internal and external API services with 3scale\u2019s API Management Platform'\nmerge = true\nformat = 'markdown'\nnot_luadoc = true\n\nnew_type(\"http\",\"HTTP\")\nnew_type(\"http_ng.backend\",\"http_ng.backend\")\n","old_contents":"file = {\n  '..\/gateway\/src\/apicast',\n  '..\/gateway\/src\/resty',\n}\ndir = '..\/doc\/lua'\nproject = 'APIcast'\ntitle = 'NGINX based API gateway used to integrate your internal and external API services with 3scale\u2019s API Management Platform'\nmerge = true\nformat = 'markdown'\n\nnew_type(\"http\",\"HTTP\")\nnew_type(\"http_ng.backend\",\"http_ng.backend\")\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"bc6ad3cd824d163760e52644eefdb3daf4761362","subject":"x86: add MMU page alignment where necessary","message":"x86: add MMU page alignment where necessary\n\nDifferent areas of memory will need to have different access\npolicies programmed into the MMU. We introduce MMU page alignment\nto the following areas:\n\n- The boundaries of the image \"ROM\" area\n- The beginning of RAM representing kernel datas\/bss\/nonit\n- The beginning of RAM representing app datas\/bss\/noinit\n\nSome old alignment directives that are no longer necessary have\nbeen removed.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"kraj\/zephyr,aceofall\/zephyr-iotos,GiulianoFranchetto\/zephyr,nashif\/zephyr,mbolivar\/zephyr,Vudentz\/zephyr,rsalveti\/zephyr,zephyrproject-rtos\/zephyr,kraj\/zephyr,zephyriot\/zephyr,finikorg\/zephyr,zephyriot\/zephyr,nashif\/zephyr,explora26\/zephyr,fbsder\/zephyr,GiulianoFranchetto\/zephyr,rsalveti\/zephyr,zephyriot\/zephyr,mbolivar\/zephyr,punitvara\/zephyr,runchip\/zephyr-cc3220,nashif\/zephyr,punitvara\/zephyr,zephyriot\/zephyr,galak\/zephyr,punitvara\/zephyr,punitvara\/zephyr,explora26\/zephyr,rsalveti\/zephyr,finikorg\/zephyr,galak\/zephyr,explora26\/zephyr,ldts\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,kraj\/zephyr,explora26\/zephyr,aceofall\/zephyr-iotos,ldts\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,rsalveti\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,mbolivar\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3220,kraj\/zephyr,fbsder\/zephyr,Vudentz\/zephyr,fbsder\/zephyr,nashif\/zephyr,ldts\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,rsalveti\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,mbolivar\/zephyr,runchip\/zephyr-cc3220,runchip\/zephyr-cc3220,nashif\/zephyr,zephyrproject-rtos\/zephyr,aceofall\/zephyr-iotos,ldts\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,explora26\/zephyr,mbolivar\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,aceofall\/zephyr-iotos,zephyriot\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3220,galak\/zephyr","old_file":"include\/arch\/x86\/linker.ld","new_file":"include\/arch\/x86\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROMABLE_REGION start addr *\/\n\n\t\/* This align directive needs to be after __data_rom_start or XIP\n\t * won't be copying the data from the right LMA\n\t *\/\n\tMMU_PAGE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n#endif\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\n\t\/* All stacks go in kernel's noinit, regardless of where they\n\t * were defined.\n\t *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\t__kernel_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tMMU_PAGE_ALIGN\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n#define MMU_PAGE_SIZE KB(4)\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROMABLE_REGION start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_X86_MMU\n       \/* Page Tables are located here if MMU is enabled.*\/\n\t. = ALIGN(4096);\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n#endif\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\n\t\/* All stacks go in kernel's noinit, regardless of where they\n\t * were defined.\n\t *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\t__kernel_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\t. = ALIGN(MMU_PAGE_SIZE);\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ee95bb4fe9195619d281e2643f72190aa61067ba","subject":"update: add data flash size","message":"update: add data flash size\n","repos":"hirakuni45\/RL78,hirakuni45\/RL78,hirakuni45\/RL78","old_file":"L1C\/R5F110ME.ld","new_file":"L1C\/R5F110ME.ld","new_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/L1C, 64K Flash, 8K RAM, 8K Data-Flash *\/\n\/* R5F100LEAFB:  64K (0x00000 - 0x0FFFF) \/  8K (0xFDF00 - 0xFFEFF) \/ 8K (0xF1000 - 0xF2FFF) *\/\n\/* DataFlash Library(FDL T04) used self-ram: 0xFAF00 to 0xFAF87 (136 bytes) *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007C\n\tOPT (r)   : ORIGIN = 0x000C0, LENGTH = 0x00004\n\tSEC_ID (r): ORIGIN = 0x000C4, LENGTH = 0x0000A\n\tROM (r)   : ORIGIN = 0x000D8, LENGTH = 0x0FF28\n\tRAM (w)   : ORIGIN = 0xFDF00, LENGTH = 0x01F20\n\tDATAF (W) : ORIGIN = 0xF1000, LENGTH = 0x02000\n\tSTACK (w) : ORIGIN = 0xFFE20, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n\n  .opt :\n  {\n    KEEP(*(.opt))\n  } > OPT\n\n  .sec_id :\n  {\n    KEEP(*(.sec_id))\n  } > SEC_ID\n\n  \/* CubeSuite always starts at 0xd8.  *\/\n  .csstart : {\n    *(.csstart)\n  } > ROM\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  .rodata (MAX(__romdatastart + __romdatacopysize, 0x3000)) :\n  {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n\tPROVIDE (__dataflashsize = .);\n\tSHORT(LENGTH(DATAF));\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    PROVIDE (__ctor_start = .);\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    PROVIDE (__ctor_end = .);\n\n    PROVIDE (__dtor_start = .);\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    PROVIDE (__dtor_end = .);\n  } > ROM\n\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    *(PFDL_COD)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .hightext : {\n    *(.hightext)\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/L1C, 64K Flash, 8K RAM, 8K Data-Flash *\/\n\/* R5F100LEAFB:  64K (0x00000 - 0x0FFFF) \/  8K (0xFDF00 - 0xFFEFF) \/ 8K (0xF1000 - 0xF2FFF) *\/\n\/* DataFlash Library(FDL T04) used self-ram: 0xFAF00 to 0xFAF87 (136 bytes) *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007C\n\tOPT (r)   : ORIGIN = 0x000C0, LENGTH = 0x00004\n\tSEC_ID (r): ORIGIN = 0x000C4, LENGTH = 0x0000A\n\tROM (r)   : ORIGIN = 0x000D8, LENGTH = 0x0FF28\n\tRAM (w)   : ORIGIN = 0xFDF00, LENGTH = 0x01F20\n\tSTACK (w) : ORIGIN = 0xFFE20, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n\n  .opt :\n  {\n    KEEP(*(.opt))\n  } > OPT\n\n  .sec_id :\n  {\n    KEEP(*(.sec_id))\n  } > SEC_ID\n\n  \/* CubeSuite always starts at 0xd8.  *\/\n  .csstart : {\n    *(.csstart)\n  } > ROM\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n\t.rodata (MAX(__romdatastart + __romdatacopysize, 0x3000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    PROVIDE (__ctor_start = .);\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    PROVIDE (__ctor_end = .);\n\n    PROVIDE (__dtor_start = .);\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    PROVIDE (__dtor_end = .);\n  } > ROM\n\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    *(PFDL_COD)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .hightext : {\n    *(.hightext)\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"6aeb048e62ab5c62ef7e8f8857d097f2427b10dc","subject":"Fixing bug error 0x8001011F","message":"Fixing bug error 0x8001011F\n","repos":"kjbracey-arm\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed","old_file":"targets\/TARGET_TT\/TARGET_TT_M4G9\/device\/TOOLCHAIN_GCC_ARM\/tmpm4g9f15fg.ld","new_file":"targets\/TARGET_TT\/TARGET_TT_M4G9\/device\/TOOLCHAIN_GCC_ARM\/tmpm4g9f15fg.ld","new_contents":"\/* Linker script for Toshiba TMPM4G9 *\/\n\n\/* Linker script to configure memory regions. *\/\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x00000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x180000\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  RAM (rwx) : ORIGIN = 0x20000320, LENGTH = (192K - 0x320)\n}\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __Vectors_End\n *   __Vectors_Size\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.vectors))\n\t\t__Vectors_End = .;\n\t\t__Vectors_Size = __Vectors_End - __Vectors;\n\t\t__end__ = .;\n\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n        *(.ram_func*)\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__HeapBase = .;\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\tKEEP(*(.heap*))\n\t\t. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\tKEEP(*(.stack*))\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - STACK_SIZE;\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for Toshiba TMPM4G9 *\/\n\n\/* Linker script to configure memory regions. *\/\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x00000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x180000\n#endif\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  RAM (rwx) : ORIGIN = 0x20000320, LENGTH = (192K - 0x320)\n}\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __Vectors_End\n *   __Vectors_Size\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.vectors))\n\t\t__Vectors_End = .;\n\t\t__Vectors_Size = __Vectors_End - __Vectors;\n\t\t__end__ = .;\n\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n        *(.ram_func*)\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__HeapBase = .;\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\tKEEP(*(.heap*))\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\tKEEP(*(.stack*))\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"79f8291168750fd0ddcd1881da0f63f5f3ae132f","subject":"added hsb ram location to linker script","message":"added hsb ram location to linker script\n","repos":"PDXostc\/can_firewall_software,PDXostc\/can_firewall_software","old_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-avr32\", \"elf32-avr32\",\n\t      \"elf32-avr32\")\nOUTPUT_ARCH(avr32:uc)\nENTRY(_start)\nSEARCH_DIR(\"\/home\/toolsbuild\/jenkins-knuth\/workspace\/avr32-gnu-toolchain\/avr32-gnu-toolchain-win32_x86\/avr32\/lib\");\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY\n{\n    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K-10K-8K\n\t\tFLASHRSVD (rxai!w) : ORIGIN = 0x80000000+512K-10K-8K, LENGTH = 10K\n    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC\n    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512\n    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512\n    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8\n    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8\n    HSBRAM (wxa!ri) : ORIGIN = 0XA0000000, LENGTH = 4K\n}\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;\n\t\/* Next line should not be necessary for use of flash for storing rules *\/\n\t\/* .flash_rsvd : { *(.flash_rsvd) } >FLASHRSVD AT>FLASHRSVD *\/\n  .interp         : { *(.interp) } >FLASH AT>FLASH\n  .reset : {  *(.reset) } >FLASH AT>FLASH\n  .hash           : { *(.hash) } >FLASH AT>FLASH\n  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH\n  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH\n  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH\n  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH\n  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH\n  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH\n  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH\n  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH\n  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH\n  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH\n  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH\n  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH\n  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH\n  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH\n  .init           :\n  {\n    KEEP (*(.init))\n  } >FLASH AT>FLASH =0xd703d703\n  .plt            : { *(.plt) } >FLASH AT>FLASH\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } >FLASH AT>FLASH =0xd703d703\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } >FLASH AT>FLASH =0xd703d703\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH\n  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH\n  .dalign\t: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH\n  PROVIDE (_data = ORIGIN(CPUSRAM));\n  . = ORIGIN(CPUSRAM);\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  PROVIDE (__preinit_array_start = ALIGN(32 \/ 8));\n  .preinit_array     : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >CPUSRAM AT>FLASH\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >CPUSRAM AT>FLASH\n  .jcr            : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH\n  .dynamic        : { *(.dynamic) } >CPUSRAM AT>FLASH\n  .got            : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH\n  .data           :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  } >CPUSRAM AT>FLASH\n  .data1          : { *(.data1) } >CPUSRAM AT>FLASH\n  .balign\t: { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(8);\n  } >CPUSRAM\n  . = ALIGN(8);\n  _end = .;\n  PROVIDE (end = .);\n  __heap_start__ = ALIGN(8);\n  . = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;\n  __heap_end__ = .;\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :\n  {\n    _stack = .;\n    *(.stack)\n    . = _stack_size;\n    _estack = .;\n  } >CPUSRAM\n  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE\n  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE\n\t.flash : { *(.flash .flash.*) } >FLASH AT>FLASH\n\t.flash_rsvd : { *(.flash_rsvd .flash_rsvd.*) } >FLASHRSVD AT>FLASHRSVD\n  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE\n  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE\n  .hsb_ram_loc : { *(.hsb_ram_loc .hsb_ram_loc.*)  } >HSBRAM AT>HSBRAM\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-avr32\", \"elf32-avr32\",\n\t      \"elf32-avr32\")\nOUTPUT_ARCH(avr32:uc)\nENTRY(_start)\nSEARCH_DIR(\"\/home\/toolsbuild\/jenkins-knuth\/workspace\/avr32-gnu-toolchain\/avr32-gnu-toolchain-win32_x86\/avr32\/lib\");\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY\n{\n    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K-10K-8K\n\t\tFLASHRSVD (rxai!w) : ORIGIN = 0x80000000+512K-10K-8K, LENGTH = 10K\n    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC\n    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512\n    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512\n    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8\n    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8\n}\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;\n\t\/* Next line should not be necessary for use of flash for storing rules *\/\n\t\/* .flash_rsvd : { *(.flash_rsvd) } >FLASHRSVD AT>FLASHRSVD *\/\n  .interp         : { *(.interp) } >FLASH AT>FLASH\n  .reset : {  *(.reset) } >FLASH AT>FLASH\n  .hash           : { *(.hash) } >FLASH AT>FLASH\n  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH\n  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH\n  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH\n  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH\n  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH\n  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH\n  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH\n  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH\n  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH\n  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH\n  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH\n  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH\n  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH\n  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH\n  .init           :\n  {\n    KEEP (*(.init))\n  } >FLASH AT>FLASH =0xd703d703\n  .plt            : { *(.plt) } >FLASH AT>FLASH\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } >FLASH AT>FLASH =0xd703d703\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } >FLASH AT>FLASH =0xd703d703\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH\n  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH\n  .dalign\t: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH\n  PROVIDE (_data = ORIGIN(CPUSRAM));\n  . = ORIGIN(CPUSRAM);\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  PROVIDE (__preinit_array_start = ALIGN(32 \/ 8));\n  .preinit_array     : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >CPUSRAM AT>FLASH\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >CPUSRAM AT>FLASH\n  .jcr            : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH\n  .dynamic        : { *(.dynamic) } >CPUSRAM AT>FLASH\n  .got            : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH\n  .data           :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  } >CPUSRAM AT>FLASH\n  .data1          : { *(.data1) } >CPUSRAM AT>FLASH\n  .balign\t: { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(8);\n  } >CPUSRAM\n  . = ALIGN(8);\n  _end = .;\n  PROVIDE (end = .);\n  __heap_start__ = ALIGN(8);\n  . = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;\n  __heap_end__ = .;\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :\n  {\n    _stack = .;\n    *(.stack)\n    . = _stack_size;\n    _estack = .;\n  } >CPUSRAM\n  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE\n  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE\n\t.flash : { *(.flash .flash.*) } >FLASH AT>FLASH\n\t.flash_rsvd : { *(.flash_rsvd .flash_rsvd.*) } >FLASHRSVD AT>FLASHRSVD\n  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE\n  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"bb7fdb6edaf2d831fb53a67a0cbc3151f4ae8da0","subject":"lpc1768: Adjust ldscript memory segment attributes","message":"lpc1768: Adjust ldscript memory segment attributes\n","repos":"rfuentess\/RIOT,A-Paul\/RIOT,basilfx\/RIOT,biboc\/RIOT,josephnoir\/RIOT,kYc0o\/RIOT,mtausig\/RIOT,josephnoir\/RIOT,OTAkeys\/RIOT,cladmi\/RIOT,lazytech-org\/RIOT,OlegHahm\/RIOT,gebart\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,avmelnikoff\/RIOT,ant9000\/RIOT,biboc\/RIOT,josephnoir\/RIOT,avmelnikoff\/RIOT,rfuentess\/RIOT,BytesGalore\/RIOT,basilfx\/RIOT,kbumsik\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,basilfx\/RIOT,rfuentess\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,cladmi\/RIOT,toonst\/RIOT,yogo1212\/RIOT,mtausig\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,x3ro\/RIOT,jasonatran\/RIOT,kbumsik\/RIOT,neiljay\/RIOT,rfuentess\/RIOT,jasonatran\/RIOT,smlng\/RIOT,x3ro\/RIOT,OlegHahm\/RIOT,gebart\/RIOT,gebart\/RIOT,mfrey\/RIOT,yogo1212\/RIOT,kaspar030\/RIOT,kbumsik\/RIOT,neiljay\/RIOT,kaspar030\/RIOT,basilfx\/RIOT,neiljay\/RIOT,kYc0o\/RIOT,A-Paul\/RIOT,avmelnikoff\/RIOT,josephnoir\/RIOT,OlegHahm\/RIOT,cladmi\/RIOT,rfuentess\/RIOT,kaspar030\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,mfrey\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,BytesGalore\/RIOT,RIOT-OS\/RIOT,A-Paul\/RIOT,yogo1212\/RIOT,smlng\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,A-Paul\/RIOT,cladmi\/RIOT,neiljay\/RIOT,avmelnikoff\/RIOT,BytesGalore\/RIOT,toonst\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,mtausig\/RIOT,smlng\/RIOT,basilfx\/RIOT,biboc\/RIOT,mfrey\/RIOT,toonst\/RIOT,authmillenon\/RIOT,mtausig\/RIOT,mfrey\/RIOT,ant9000\/RIOT,toonst\/RIOT,x3ro\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,yogo1212\/RIOT,smlng\/RIOT,smlng\/RIOT,aeneby\/RIOT,kaspar030\/RIOT,gebart\/RIOT,mtausig\/RIOT,x3ro\/RIOT,A-Paul\/RIOT,lazytech-org\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,OTAkeys\/RIOT,BytesGalore\/RIOT,OTAkeys\/RIOT,neiljay\/RIOT,yogo1212\/RIOT,BytesGalore\/RIOT,biboc\/RIOT,lazytech-org\/RIOT,miri64\/RIOT,kbumsik\/RIOT,biboc\/RIOT,toonst\/RIOT,kYc0o\/RIOT,aeneby\/RIOT,lazytech-org\/RIOT,avmelnikoff\/RIOT,aeneby\/RIOT,authmillenon\/RIOT,josephnoir\/RIOT,aeneby\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,lazytech-org\/RIOT,mfrey\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,OTAkeys\/RIOT,kbumsik\/RIOT,miri64\/RIOT,gebart\/RIOT,cladmi\/RIOT","old_file":"cpu\/lpc1768\/ldscripts\/lpc1768.ld","new_file":"cpu\/lpc1768\/ldscripts\/lpc1768.ld","new_contents":"\/*\n * Copyright (C) 2015 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_lpc1768\n * @{\n *\n * @file\n * @brief           Memory definitions for the LPC1768\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)        : ORIGIN = 0x00000000, LENGTH = 512K\n    ram (w!rx)      : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)\n    usb_ram         : ORIGIN = 0x2007C000, LENGTH = 16K\n    eth_ram         : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2015 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_lpc1768\n * @{\n *\n * @file\n * @brief           Memory definitions for the LPC1768\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)        : ORIGIN = 0x00000000, LENGTH = 512K\n    ram (rwx)       : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)\n    usb_ram (rwx)   : ORIGIN = 0x2007C000, LENGTH = 16K\n    eth_ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"59d07b02473908c34c105c1c05eab5b76c732edb","subject":"linker: esp32: Add missing iterable sections","message":"linker: esp32: Add missing iterable sections\n\nThis fixes missing PPP iterable and adds all\ncommon-rom.ld iterables.\n\nESP32 and esptool does not support more then 16 segments, which\nblocks including common iterables section as is.\n\nThis partially reverts commit ad0bf94f772d28d12986bd17552575442147f9f7\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"07cd2ff0650a66eccebcab25a626fec5553d9133","subject":"restore 4kB gap pending resolution of #7011","message":"restore 4kB gap pending resolution of #7011\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/raspberrypi\/boards\/raspberry_pi_pico_w\/link.ld","new_file":"ports\/raspberrypi\/boards\/raspberry_pi_pico_w\/link.ld","new_contents":"\/* Based on GCC ARM embedded samples.\n   Defines the following symbols for use by code:\n    __exidx_start\n    __exidx_end\n    __etext\n    __data_start__\n    __preinit_array_start\n    __preinit_array_end\n    __init_array_start\n    __init_array_end\n    __fini_array_start\n    __fini_array_end\n    __data_end__\n    __bss_start__\n    __bss_end__\n    __end__\n    end\n    __HeapLimit\n    __StackLimit\n    __StackTop\n    __stack (== StackTop)\n*\/\n\nMEMORY\n{\n    FLASH_FIRMWARE (rx) : ORIGIN = 0x10000000, LENGTH = 1528k\n    RAM (rwx) : ORIGIN =  0x20000000, LENGTH = 256k\n    SCRATCH_X (rwx) : ORIGIN = 0x20040000, LENGTH = 4k\n    SCRATCH_Y (rwx) : ORIGIN = 0x20041000, LENGTH = 4k\n}\n\nENTRY(_entry_point)\n\nSECTIONS\n{\n    \/* Second stage bootloader is prepended to the image. It must be 256 bytes big\n       and checksummed. It is usually built by the boot_stage2 target\n       in the Pico SDK\n    *\/\n\n    .flash_begin : {\n        __flash_binary_start = .;\n    } > FLASH_FIRMWARE\n\n    .boot2 : {\n        __boot2_start__ = .;\n        KEEP (*(.boot2))\n        __boot2_end__ = .;\n    } > FLASH_FIRMWARE\n\n    ASSERT(__boot2_end__ - __boot2_start__ == 256,\n        \"ERROR: Pico second stage bootloader must be 256 bytes in size\")\n\n    \/* The second stage will always enter the image at the start of .text.\n       The debugger will use the ELF entry point, which is the _entry_point\n       symbol if present, otherwise defaults to start of .text.\n       This can be used to transfer control back to the bootrom on debugger\n       launches only, to perform proper flash setup.\n    *\/\n\n    .text : {\n        __logical_binary_start = .;\n        KEEP (*(.vectors))\n        KEEP (*(.binary_info_header))\n        __binary_info_header_end = .;\n        KEEP (*(.reset))\n        \/* TODO revisit this now memset\/memcpy\/float in ROM *\/\n        \/* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from\n         * FLASH ... we will include any thing excluded here in .data below by default *\/\n        *(.init)\n\n        __property_getter_start = .;\n        *(.property_getter)\n        __property_getter_end = .;\n        __property_getset_start = .;\n        *(.property_getset)\n        __property_getset_end = .;\n\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*)\n        *(.fini)\n        \/* Pull all c'tors into .text *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n        \/* Followed by destructors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH_FIRMWARE\n\n    .rodata : {\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*)\n        . = ALIGN(4);\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))\n        . = ALIGN(4);\n    } > FLASH_FIRMWARE\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH_FIRMWARE\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH_FIRMWARE\n    __exidx_end = .;\n\n    \/* Machine inspectable binary information *\/\n    . = ALIGN(4);\n    __binary_info_start = .;\n    .binary_info :\n    {\n        KEEP(*(.binary_info.keep.*))\n        *(.binary_info.*)\n    } > FLASH_FIRMWARE\n    __binary_info_end = .;\n    . = ALIGN(4);\n\n    \/* End of .text-like segments *\/\n    __etext = .;\n\n   .ram_vector_table (COPY): {\n        *(.ram_vector_table)\n    } > RAM\n\n    .data : {\n        __data_start__ = .;\n        *(vtable)\n\n        *(.time_critical*)\n\n        \/* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM *\/\n        *(.text*)\n        . = ALIGN(4);\n        *(.rodata*)\n        . = ALIGN(4);\n\n        *(.data*)\n\n        . = ALIGN(4);\n        *(.after_data.*)\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__mutex_array_start = .);\n        KEEP(*(SORT(.mutex_array.*)))\n        KEEP(*(.mutex_array))\n        PROVIDE_HIDDEN (__mutex_array_end = .);\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(SORT(.preinit_array.*)))\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM AT> FLASH_FIRMWARE\n\n    .itcm :\n    {\n        . = ALIGN(4);\n        *(.itcm.*)\n\n        . = ALIGN(4);\n    } > RAM AT> FLASH_FIRMWARE\n    _ld_itcm_destination = ADDR(.itcm);\n    _ld_itcm_flash_copy = LOADADDR(.itcm);\n    _ld_itcm_size = SIZEOF(.itcm);\n\n    .dtcm_data :\n    {\n        . = ALIGN(4);\n\n        *(.dtcm_data.*)\n\n        . = ALIGN(4);\n    } > RAM AT> FLASH_FIRMWARE\n    _ld_dtcm_data_destination = ADDR(.dtcm_data);\n    _ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data);\n    _ld_dtcm_data_size = SIZEOF(.dtcm_data);\n\n    .dtcm_bss :\n    {\n        . = ALIGN(4);\n\n        *(.dtcm_bss.*)\n\n        . = ALIGN(4);\n    } > RAM AT> RAM\n    _ld_dtcm_bss_start = ADDR(.dtcm_bss);\n    _ld_dtcm_bss_size = SIZEOF(.dtcm_bss);\n\n    .uninitialized_data (COPY): {\n        . = ALIGN(4);\n        *(.uninitialized_data*)\n    } > RAM\n\n    \/* Start and end symbols must be word-aligned *\/\n    .scratch_x : {\n        __scratch_x_start__ = .;\n        *(.scratch_x.*)\n        . = ALIGN(4);\n        __scratch_x_end__ = .;\n    } > SCRATCH_X AT > FLASH_FIRMWARE\n    __scratch_x_source__ = LOADADDR(.scratch_x);\n\n    .scratch_y : {\n        __scratch_y_start__ = .;\n        *(.scratch_y.*)\n        . = ALIGN(4);\n        __scratch_y_end__ = .;\n    } > SCRATCH_Y AT > FLASH_FIRMWARE\n    __scratch_y_source__ = LOADADDR(.scratch_y);\n\n    .bss  : {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack*_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later\n     *\n     * stack1 section may be empty\/missing if platform_launch_core1 is not used *\/\n\n    \/* by default we put core 0 stack at the end of scratch Y, so that if core 1\n     * stack is not used then all of SCRATCH_X is free.\n     *\/\n    .stack1_dummy (COPY):\n    {\n        *(.stack1*)\n    } > SCRATCH_X\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SCRATCH_Y\n\n    .flash_end : {\n        __flash_binary_end = .;\n    } > FLASH_FIRMWARE\n\n    \/* stack limit is poorly named, but historically is maximum heap ptr *\/\n    __StackLimit = ORIGIN(RAM) + LENGTH(RAM);\n    __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);\n    __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);\n    __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);\n    __StackBottom = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed\")\n\n    ASSERT( __binary_info_header_end - __logical_binary_start <= 256, \"Binary info must be in first 256 bytes of the binary\")\n    \/* todo assert on extra code *\/\n}\n","old_contents":"\/* Based on GCC ARM embedded samples.\n   Defines the following symbols for use by code:\n    __exidx_start\n    __exidx_end\n    __etext\n    __data_start__\n    __preinit_array_start\n    __preinit_array_end\n    __init_array_start\n    __init_array_end\n    __fini_array_start\n    __fini_array_end\n    __data_end__\n    __bss_start__\n    __bss_end__\n    __end__\n    end\n    __HeapLimit\n    __StackLimit\n    __StackTop\n    __stack (== StackTop)\n*\/\n\nMEMORY\n{\n    FLASH_FIRMWARE (rx) : ORIGIN = 0x10000000, LENGTH = 1532k\n    RAM (rwx) : ORIGIN =  0x20000000, LENGTH = 256k\n    SCRATCH_X (rwx) : ORIGIN = 0x20040000, LENGTH = 4k\n    SCRATCH_Y (rwx) : ORIGIN = 0x20041000, LENGTH = 4k\n}\n\nENTRY(_entry_point)\n\nSECTIONS\n{\n    \/* Second stage bootloader is prepended to the image. It must be 256 bytes big\n       and checksummed. It is usually built by the boot_stage2 target\n       in the Pico SDK\n    *\/\n\n    .flash_begin : {\n        __flash_binary_start = .;\n    } > FLASH_FIRMWARE\n\n    .boot2 : {\n        __boot2_start__ = .;\n        KEEP (*(.boot2))\n        __boot2_end__ = .;\n    } > FLASH_FIRMWARE\n\n    ASSERT(__boot2_end__ - __boot2_start__ == 256,\n        \"ERROR: Pico second stage bootloader must be 256 bytes in size\")\n\n    \/* The second stage will always enter the image at the start of .text.\n       The debugger will use the ELF entry point, which is the _entry_point\n       symbol if present, otherwise defaults to start of .text.\n       This can be used to transfer control back to the bootrom on debugger\n       launches only, to perform proper flash setup.\n    *\/\n\n    .text : {\n        __logical_binary_start = .;\n        KEEP (*(.vectors))\n        KEEP (*(.binary_info_header))\n        __binary_info_header_end = .;\n        KEEP (*(.reset))\n        \/* TODO revisit this now memset\/memcpy\/float in ROM *\/\n        \/* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from\n         * FLASH ... we will include any thing excluded here in .data below by default *\/\n        *(.init)\n\n        __property_getter_start = .;\n        *(.property_getter)\n        __property_getter_end = .;\n        __property_getset_start = .;\n        *(.property_getset)\n        __property_getset_end = .;\n\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*)\n        *(.fini)\n        \/* Pull all c'tors into .text *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n        \/* Followed by destructors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH_FIRMWARE\n\n    .rodata : {\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*)\n        . = ALIGN(4);\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))\n        . = ALIGN(4);\n    } > FLASH_FIRMWARE\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH_FIRMWARE\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH_FIRMWARE\n    __exidx_end = .;\n\n    \/* Machine inspectable binary information *\/\n    . = ALIGN(4);\n    __binary_info_start = .;\n    .binary_info :\n    {\n        KEEP(*(.binary_info.keep.*))\n        *(.binary_info.*)\n    } > FLASH_FIRMWARE\n    __binary_info_end = .;\n    . = ALIGN(4);\n\n    \/* End of .text-like segments *\/\n    __etext = .;\n\n   .ram_vector_table (COPY): {\n        *(.ram_vector_table)\n    } > RAM\n\n    .data : {\n        __data_start__ = .;\n        *(vtable)\n\n        *(.time_critical*)\n\n        \/* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM *\/\n        *(.text*)\n        . = ALIGN(4);\n        *(.rodata*)\n        . = ALIGN(4);\n\n        *(.data*)\n\n        . = ALIGN(4);\n        *(.after_data.*)\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__mutex_array_start = .);\n        KEEP(*(SORT(.mutex_array.*)))\n        KEEP(*(.mutex_array))\n        PROVIDE_HIDDEN (__mutex_array_end = .);\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(SORT(.preinit_array.*)))\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM AT> FLASH_FIRMWARE\n\n    .itcm :\n    {\n        . = ALIGN(4);\n        *(.itcm.*)\n\n        . = ALIGN(4);\n    } > RAM AT> FLASH_FIRMWARE\n    _ld_itcm_destination = ADDR(.itcm);\n    _ld_itcm_flash_copy = LOADADDR(.itcm);\n    _ld_itcm_size = SIZEOF(.itcm);\n\n    .dtcm_data :\n    {\n        . = ALIGN(4);\n\n        *(.dtcm_data.*)\n\n        . = ALIGN(4);\n    } > RAM AT> FLASH_FIRMWARE\n    _ld_dtcm_data_destination = ADDR(.dtcm_data);\n    _ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data);\n    _ld_dtcm_data_size = SIZEOF(.dtcm_data);\n\n    .dtcm_bss :\n    {\n        . = ALIGN(4);\n\n        *(.dtcm_bss.*)\n\n        . = ALIGN(4);\n    } > RAM AT> RAM\n    _ld_dtcm_bss_start = ADDR(.dtcm_bss);\n    _ld_dtcm_bss_size = SIZEOF(.dtcm_bss);\n\n    .uninitialized_data (COPY): {\n        . = ALIGN(4);\n        *(.uninitialized_data*)\n    } > RAM\n\n    \/* Start and end symbols must be word-aligned *\/\n    .scratch_x : {\n        __scratch_x_start__ = .;\n        *(.scratch_x.*)\n        . = ALIGN(4);\n        __scratch_x_end__ = .;\n    } > SCRATCH_X AT > FLASH_FIRMWARE\n    __scratch_x_source__ = LOADADDR(.scratch_x);\n\n    .scratch_y : {\n        __scratch_y_start__ = .;\n        *(.scratch_y.*)\n        . = ALIGN(4);\n        __scratch_y_end__ = .;\n    } > SCRATCH_Y AT > FLASH_FIRMWARE\n    __scratch_y_source__ = LOADADDR(.scratch_y);\n\n    .bss  : {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack*_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later\n     *\n     * stack1 section may be empty\/missing if platform_launch_core1 is not used *\/\n\n    \/* by default we put core 0 stack at the end of scratch Y, so that if core 1\n     * stack is not used then all of SCRATCH_X is free.\n     *\/\n    .stack1_dummy (COPY):\n    {\n        *(.stack1*)\n    } > SCRATCH_X\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SCRATCH_Y\n\n    .flash_end : {\n        __flash_binary_end = .;\n    } > FLASH_FIRMWARE\n\n    \/* stack limit is poorly named, but historically is maximum heap ptr *\/\n    __StackLimit = ORIGIN(RAM) + LENGTH(RAM);\n    __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);\n    __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);\n    __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);\n    __StackBottom = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed\")\n\n    ASSERT( __binary_info_header_end - __logical_binary_start <= 256, \"Binary info must be in first 256 bytes of the binary\")\n    \/* todo assert on extra code *\/\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"89a1aac42d5c91ceae79ba0c5ebe3324701869bd","subject":"Update project title","message":"Update project title\n","repos":"Quenty\/NevermoreEngine,Quenty\/NevermoreEngine,Quenty\/NevermoreEngine","old_file":"Doc\/config.ld","new_file":"Doc\/config.ld","new_contents":"-- Descriptors\nproject = 'Nevermore Reference'\ndescription = 'Nevemore Roblux Lua Libraries'\ntitle = 'Nevermore Reference'\nfull_description = [[\nNevermore is a ModuleScript loader for Roblox, and loads modules by name. Nevermore is designed to make code more portable. Nevermore comes with a variety of utility libraries. These libraries are used on both the client and server and are useful for a variety of things. \n]]\n\nfile = {'..\/Modules\/Events', '..\/App', '..\/Modules\/Character', '..\/Modules\/DataStore', '..\/Modules\/Camera', '..\/Modules\/Utility'}\ntopics = 'Manual'\nformat = 'markdown'\n\n-- Style options\nuse_markdown_titles = true\nno_summary = false\nno_space_before_args = true\n\n-- Output\ndir = 'api'\n\n-- Custom template\nstyle = 'Style'\ntemplate ='Style'\n\n\n\nnew_type(\"event\", \"Events\", false, \"Params\")\nnew_type(\"property\", \"Properties\", false, nil)\n","old_contents":"-- Descriptors\nproject = 'Nevermore'\ndescription = 'Nevemore Roblux Lua Libraries'\ntitle = 'Nevermore Reference'\nfull_description = [[\nNevermore is a ModuleScript loader for Roblox, and loads modules by name. Nevermore is designed to make code more portable. Nevermore comes with a variety of utility libraries. These libraries are used on both the client and server and are useful for a variety of things. \n]]\n\nfile = {'..\/Modules\/Events', '..\/App', '..\/Modules\/Character', '..\/Modules\/DataStore', '..\/Modules\/Camera', '..\/Modules\/Utility'}\ntopics = 'Manual'\nformat = 'markdown'\n\n-- Style options\nuse_markdown_titles = true\nno_summary = false\nno_space_before_args = true\n\n-- Output\ndir = 'api'\n\n-- Custom template\nstyle = 'Style'\ntemplate ='Style'\n\n\n\nnew_type(\"event\", \"Events\", false, \"Params\")\nnew_type(\"property\", \"Properties\", false, nil)\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3fb21ac39c97089d5143c8f16c48c571ab662c2c","subject":"test_mem_safe: bring x86 linker script up-to-date","message":"test_mem_safe: bring x86 linker script up-to-date\n\nSome modifications to the base linker scripts were not propagated.\n\nChange-Id: I73ab016d861779ad7e633ce8602d2e57845bde85\nSigned-off-by: Benjamin Walsh <578db18f23ec223e50c404886c947386478a464e@windriver.com>\n","repos":"mbolivar\/zephyr,Vudentz\/zephyr,pklazy\/zephyr,ldts\/zephyr,mbolivar\/zephyr,sharronliu\/zephyr,rsalveti\/zephyr,runchip\/zephyr-cc3200,bboozzoo\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,bigdinotech\/zephyr,runchip\/zephyr-cc3200,galak\/zephyr,pklazy\/zephyr,kraj\/zephyr,kraj\/zephyr,fractalclone\/zephyr-riscv,pklazy\/zephyr,aceofall\/zephyr-iotos,runchip\/zephyr-cc3220,ldts\/zephyr,runchip\/zephyr-cc3220,runchip\/zephyr-cc3200,aceofall\/zephyr-iotos,finikorg\/zephyr,bboozzoo\/zephyr,fbsder\/zephyr,zephyrproject-rtos\/zephyr,bigdinotech\/zephyr,punitvara\/zephyr,pklazy\/zephyr,galak\/zephyr,zephyriot\/zephyr,pklazy\/zephyr,rsalveti\/zephyr,explora26\/zephyr,runchip\/zephyr-cc3220,fbsder\/zephyr,explora26\/zephyr,erwango\/zephyr,nashif\/zephyr,finikorg\/zephyr,runchip\/zephyr-cc3220,Vudentz\/zephyr,punitvara\/zephyr,fractalclone\/zephyr-riscv,sharronliu\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,fbsder\/zephyr,bigdinotech\/zephyr,punitvara\/zephyr,aceofall\/zephyr-iotos,aceofall\/zephyr-iotos,fractalclone\/zephyr-riscv,rsalveti\/zephyr,tidyjiang8\/zephyr-doc,zephyrproject-rtos\/zephyr,fbsder\/zephyr,GiulianoFranchetto\/zephyr,erwango\/zephyr,fractalclone\/zephyr-riscv,rsalveti\/zephyr,Vudentz\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3200,tidyjiang8\/zephyr-doc,sharronliu\/zephyr,sharronliu\/zephyr,Vudentz\/zephyr,holtmann\/zephyr,holtmann\/zephyr,runchip\/zephyr-cc3220,holtmann\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,explora26\/zephyr,nashif\/zephyr,holtmann\/zephyr,tidyjiang8\/zephyr-doc,erwango\/zephyr,tidyjiang8\/zephyr-doc,bboozzoo\/zephyr,finikorg\/zephyr,finikorg\/zephyr,bigdinotech\/zephyr,galak\/zephyr,nashif\/zephyr,ldts\/zephyr,Vudentz\/zephyr,kraj\/zephyr,erwango\/zephyr,aceofall\/zephyr-iotos,runchip\/zephyr-cc3200,explora26\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,fractalclone\/zephyr-riscv,nashif\/zephyr,zephyriot\/zephyr,tidyjiang8\/zephyr-doc,kraj\/zephyr,bboozzoo\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,sharronliu\/zephyr,zephyrproject-rtos\/zephyr,fbsder\/zephyr,kraj\/zephyr,nashif\/zephyr,mbolivar\/zephyr,finikorg\/zephyr,rsalveti\/zephyr,bigdinotech\/zephyr,holtmann\/zephyr,zephyriot\/zephyr,erwango\/zephyr,GiulianoFranchetto\/zephyr,mbolivar\/zephyr,bboozzoo\/zephyr,ldts\/zephyr,galak\/zephyr,galak\/zephyr,mbolivar\/zephyr","old_file":"tests\/kernel\/test_mem_safe\/linker_qemu_x86.ld","new_file":"tests\/kernel\/test_mem_safe\/linker_qemu_x86.ld","new_contents":"\/*\n * Copyright (c) 2011-2014, Wind River Systems, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * This is the linker script for both standard images and XIP images.\n *\/\n\n#include <autoconf.h>\n\n\/* physical address where the kernel is loaded *\/\n#define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define PHYS_RAM_ADDR    CONFIG_PHYS_RAM_ADDR\n#else  \/* !CONFIG_XIP *\/\n  #define PHYS_RAM_ADDR    PHYS_LOAD_ADDR\n#endif \/* CONFIG_XIP *\/\n\nMEMORY\n    {\n#ifdef CONFIG_XIP\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K\n    RAM (wx)        : ORIGIN = PHYS_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE*1K\n#else  \/* !CONFIG_XIP *\/\n    RAM (wx)\t    : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_RAM_SIZE*1K\n#endif \/* CONFIG_XIP *\/\n\n    \/*\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 2K, LENGTH = 2K\n    }\n\n\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n#define MMU_PAGE_SIZE KB(4)\n\n#include <linker-tool.h>\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME, ,)\n\t{\n\t\/*\n\t * The compiler fills the constructor pointers table below, hence symbol\n\t * __CTOR_LIST__ must be aligned on 4 byte boundary.\n\t * To align with the C++ standard, the first elment of the array\n\t * contains the number of actual constructors. The last element is\n\t * NULL.\n\t *\/\n\t. = ALIGN(4);\n\t__CTOR_LIST__ = .;\n\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\tLONG(0)\n\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t. = ALIGN(4);\n\t__init_array_start = .;\n\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\tIDT_MEMORY\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\tIRQ_TO_INTERRUPT_VECTOR_MEMORY\n#endif\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROM start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAM *\/\n\tGROUP_START(RAM)\n\n#if defined(CONFIG_XIP)\n\tSECTION_AT_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL), , __data_rom_start)\n#else\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n#endif\n\t{\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\t*(.top_of_image_ram)\n\t*(.top_of_image_ram.*)\n\t*(.data)\n\t*(\".data.*\")\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(_k_task_list, ALIGN(4), ALIGN(4))\n\t{\n\t\t_k_task_list_start = .;\n\t\t\t*(._k_task_list.public.*)\n\t\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(_k_task_ptr, (OPTIONAL),)\n\t{\n\t\t_k_task_ptr_start = .;\n\t\t\t*(._k_task_ptr.public.*)\n\t\t\t*(._k_task_ptr.private.*)\n\t\t\t*(._k_task_ptr.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n\t\t_k_task_ptr_end = .;\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(_k_pipe_ptr, (OPTIONAL),)\n\t{\n\t\t_k_pipe_ptr_start = .;\n\t\t\t*(._k_pipe_ptr.public.*)\n\t\t\t*(._k_pipe_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n\t\t_k_pipe_ptr_end = .;\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(_k_mem_map_ptr, (OPTIONAL),)\n\t{\n\t\t_k_mem_map_ptr_start = .;\n\t\t\t*(._k_mem_map_ptr.public.*)\n\t\t\t*(._k_mem_map_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n\t\t_k_mem_map_ptr_end = .;\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(_k_event_list, (OPTIONAL),)\n\t{\n\t\t_k_event_list_start = .;\n\t\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_LINK_IN(RAM)\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\tCOMMON_SYMBOLS\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(RAM)\n#ifdef CONFIG_XIP\n\t\/*\n\t * Ensure linker keeps sections in correct order, despite the fact\n\t * the previous section specified a load address and this no-load\n\t * section doesn't.\n\t *\/\n\t  GROUP_FOLLOWS_AT(RAM)\n#endif\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t*(.noinit)\n\t*(\".noinit.*\")\n\n\tINT_STUB_NOINIT\n\t*(.bottom_of_image_ram)\n\t*(.bottom_of_image_ram.*)\n\t} GROUP_LINK_IN(RAM)\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t. = ALIGN(MMU_PAGE_SIZE);\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tGROUP_END(RAM)\n\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL), )\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n\n#endif\n\n\/* start adding platform specific linker sections here *\/\n\n\/* no sections should appear after linker-epilog.h *\/\n#include <arch\/x86\/linker-epilog.h>\n","old_contents":"\/*\n * Copyright (c) 2011-2014, Wind River Systems, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * This is the linker script for both standard images and XIP images.\n *\/\n\n#include <autoconf.h>\n\n\/* physical address where the kernel is loaded *\/\n#define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define PHYS_RAM_ADDR    CONFIG_PHYS_RAM_ADDR\n#else  \/* !CONFIG_XIP *\/\n  #define PHYS_RAM_ADDR    PHYS_LOAD_ADDR\n#endif \/* CONFIG_XIP *\/\n\nMEMORY\n    {\n#ifdef CONFIG_XIP\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K\n    RAM (wx)        : ORIGIN = PHYS_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE*1K\n#else  \/* !CONFIG_XIP *\/\n    RAM (wx)\t    : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_RAM_SIZE*1K\n#endif \/* CONFIG_XIP *\/\n\n    \/*\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 2K, LENGTH = 2K\n    }\n\n\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n#define MMU_PAGE_SIZE KB(4)\n\n#include <linker-tool.h>\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n#ifdef CONFIG_VERSION_HEADER\n\tSECTION_PROLOGUE (version_header_section, (OPTIONAL),)\n\t{\n\t\t*(.version_header)\n\t\tKEEP(*(\".version_header*\"))\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME, ,)\n\t{\n\t\/*\n\t * The compiler fills the constructor pointers table below, hence symbol\n\t * __CTOR_LIST__ must be aligned on 4 byte boundary.\n\t * To align with the C++ standard, the first elment of the array\n\t * contains the number of actual constructors. The last element is\n\t * NULL.\n\t *\/\n\t. = ALIGN(4);\n\t__CTOR_LIST__ = .;\n\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\tLONG(0)\n\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t. = ALIGN(4);\n\t__init_array_start = .;\n\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\tIDT_MEMORY\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\tIRQ_TO_INTERRUPT_VECTOR_MEMORY\n#endif \/* CONFIG_MVIC *\/\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROM start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAM *\/\n\tGROUP_START(RAM)\n\n#if defined(CONFIG_XIP)\n\tSECTION_AT_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL), , __data_rom_start)\n#else\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n#endif\n\t{\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\t*(.top_of_image_ram)\n\t*(.top_of_image_ram.*)\n\t*(.data)\n\t*(\".data.*\")\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(_k_task_list, ALIGN(4), ALIGN(4))\n\t{\n\t\t_k_task_list_start = .;\n\t\t\t*(._k_task_list.public.*)\n\t\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(_k_task_ptr, (OPTIONAL),)\n\t{\n\t\t_k_task_ptr_start = .;\n\t\t\t*(._k_task_ptr.public.*)\n\t\t\t*(._k_task_ptr.private.*)\n\t\t\t*(._k_task_ptr.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n\t\t_k_task_ptr_end = .;\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(_k_pipe_ptr, (OPTIONAL),)\n\t{\n\t\t_k_pipe_ptr_start = .;\n\t\t\t*(._k_pipe_ptr.public.*)\n\t\t\t*(._k_pipe_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n\t\t_k_pipe_ptr_end = .;\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(_k_mem_map_ptr, (OPTIONAL),)\n\t{\n\t\t_k_mem_map_ptr_start = .;\n\t\t\t*(._k_mem_map_ptr.public.*)\n\t\t\t*(._k_mem_map_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n\t\t_k_mem_map_ptr_end = .;\n\t} GROUP_LINK_IN(RAM)\n\n\tSECTION_PROLOGUE(_k_event_list, (OPTIONAL),)\n\t{\n\t\t_k_event_list_start = .;\n\t\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_LINK_IN(RAM)\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\tCOMMON_SYMBOLS\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(RAM)\n#ifdef CONFIG_XIP\n\t\/*\n\t * Ensure linker keeps sections in correct order, despite the fact\n\t * the previous section specified a load address and this no-load\n\t * section doesn't.\n\t *\/\n\t  GROUP_FOLLOWS_AT(RAM)\n#endif\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t*(.noinit)\n\t*(\".noinit.*\")\n\n\tINT_STUB_NOINIT\n\t*(.bottom_of_image_ram)\n\t*(.bottom_of_image_ram.*)\n\t} GROUP_LINK_IN(RAM)\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t. = ALIGN(MMU_PAGE_SIZE);\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tGROUP_END(RAM)\n\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL), )\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n\n#endif\n\n\/* start adding platform specific linker sections here *\/\n\n\/* no sections should appear after linker-epilog.h *\/\n#include <arch\/x86\/linker-epilog.h>\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"61e6476f35b3c893c88e322af0e021b77151746a","subject":"no vectors section","message":"no vectors section","repos":"dkudrow\/slice,dkudrow\/slice","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"\/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ *\r\n *\r\n * kernel.ld\r\n *\r\n * initialization and trampoline to OS entry\r\n *\r\n * Author:\tDaniel Kudrow (dkudrow@cs.ucsb.edu)\r\n * Date:\tMarch 7 2014\r\n *\r\n * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ *\r\n *\/\r\n\r\nENTRY(handle_reset)\r\n\r\nSECTIONS\r\n{\r\n\t.init\t0x8000\t: { *(.init) }\r\n\t.text\t\t: { *(.text) }\r\n\t.data\t\t: { *(.data) }\r\n\t.bss\t\t: { *(.bss) }\r\n}\r\n","old_contents":"\/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ *\r\n *\r\n * kernel.ld\r\n *\r\n * initialization and trampoline to OS entry\r\n *\r\n * Author:\tDaniel Kudrow (dkudrow@cs.ucsb.edu)\r\n * Date:\tMarch 7 2014\r\n *\r\n * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ *\r\n *\/\r\n\r\nENTRY(handle_reset)\r\n\r\nSECTIONS\r\n{\r\n\tvectors\t\t: { *(vectors) }\r\n\t.init\t0x8000\t: { *(.init) }\r\n\t.text\t\t: { *(.text) }\r\n\t.data\t\t: { *(.data) }\r\n\t.bss\t\t: { *(.bss) }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"d0ef4ba4fc84b7e545e90b9d8041dd7fc442b5ef","subject":"added updated maple jtag linker script","message":"added updated maple jtag linker script\n","repos":"leaflabs\/maple-ide,leaflabs\/maple-ide,leaflabs\/maple-ide,leaflabs\/maple-ide,leaflabs\/maple-ide","old_file":"hardware\/leaflabs\/cores\/maple\/maple\/jtag.ld","new_file":"hardware\/leaflabs\/cores\/maple\/maple\/jtag.ld","new_contents":"\/* Linker script for STM32 (by Lanchon),\r\n * ROM and RAM relocated to their positions \r\n * as placed by Maple bootloader\r\n *\r\n * Configure target memory and included script\r\n * according to your application requirements. *\/\r\n\r\n\/* Define memory spaces. *\/\r\nMEMORY\r\n{\r\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K\r\n  rom (rx)  : ORIGIN = 0x08000000, LENGTH = 128K\r\n}\r\n\r\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nENTRY(_start)\r\nSEARCH_DIR(.)\r\n\/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) *\/\r\nGROUP(libgcc.a libc.a libm.a libcs3-lanchon-stm32.a)\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_lanchon_stm32)\r\nINCLUDE names.inc\r\nEXTERN(__cs3_interrupt_vector_lanchon_stm32)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\r\nEXTERN(_start)\r\n\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\r\nPROVIDE(__cs3_heap_start = _end);\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;\r\n    *(.cs3.interrupt_vector)\r\n    \/* Make sure we pulled in an interrupt vector.  *\/\r\n    ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, \"No interrupt vector\");\r\n    *(.rom)\r\n    *(.rom.b)\r\n\r\n    PROVIDE(__cs3_reset_lanchon_stm32 = _start);\r\n    __cs3_reset = __cs3_reset_lanchon_stm32;\r\n    *(.cs3.reset)\r\n\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n    *(.plt)\r\n    *(.gnu.warning)\r\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\r\n\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    *(.gcc_except_table)\r\n    *(.eh_frame_hdr)\r\n    *(.eh_frame)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n  } >rom\r\n\r\n  \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } >rom\r\n  __exidx_end = .;\r\n  .text.align :\r\n  {\r\n    . = ALIGN(8);\r\n    _etext = .;\r\n  } >rom\r\n  \/* __cs3_region_end_rom is deprecated *\/\r\n  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);\r\n  __cs3_region_size_rom = LENGTH(rom);\r\n  __cs3_region_num = 1;\r\n\r\n  .data :\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.cs3.region-head.ram)\r\n    KEEP(*(.jcr))\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.ram)\r\n    . = ALIGN (8);\r\n    _edata = .;\r\n  } >ram AT>rom\r\n  .bss :\r\n  {\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    *(.ram.b)\r\n    . = ALIGN (8);\r\n    _end = .;\r\n    __end = .;\r\n  } >ram AT>rom\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  __cs3_region_init_ram = LOADADDR (.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n  __cs3_region_num = 1;\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n\r\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\r\n  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\r\n  \/DISCARD\/ : { *(.note.GNU-stack) }\r\n}\r\n","old_contents":"\/* Linker script for STM32 (by Lanchon),\r\n * ROM and RAM relocated to their positions \r\n * as placed by Maple bootloader\r\n *\r\n * Configure target memory and included script\r\n * according to your application requirements. *\/\r\n\r\n\/* Define memory spaces. *\/\r\nMEMORY\r\n{\r\n  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K\r\n  rom (rx)  : ORIGIN = 0x08005000, LENGTH = 108K\r\n}\r\n\r\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nENTRY(_start)\r\nSEARCH_DIR(.)\r\n\/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) *\/\r\nGROUP(libgcc.a libc.a libm.a libcs3-lanchon-stm32.a)\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_lanchon_stm32)\r\nINCLUDE names.inc\r\nEXTERN(__cs3_interrupt_vector_lanchon_stm32)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\r\nEXTERN(_start)\r\n\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\r\nPROVIDE(__cs3_heap_start = _end);\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;\r\n    *(.cs3.interrupt_vector)\r\n    \/* Make sure we pulled in an interrupt vector.  *\/\r\n    ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, \"No interrupt vector\");\r\n    *(.rom)\r\n    *(.rom.b)\r\n\r\n    PROVIDE(__cs3_reset_lanchon_stm32 = _start);\r\n    __cs3_reset = __cs3_reset_lanchon_stm32;\r\n    *(.cs3.reset)\r\n\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n    *(.plt)\r\n    *(.gnu.warning)\r\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\r\n\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    *(.gcc_except_table)\r\n    *(.eh_frame_hdr)\r\n    *(.eh_frame)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n  } >rom\r\n\r\n  \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } >rom\r\n  __exidx_end = .;\r\n  .text.align :\r\n  {\r\n    . = ALIGN(8);\r\n    _etext = .;\r\n  } >rom\r\n  \/* __cs3_region_end_rom is deprecated *\/\r\n  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);\r\n  __cs3_region_size_rom = LENGTH(rom);\r\n  __cs3_region_num = 1;\r\n\r\n  .data :\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.cs3.region-head.ram)\r\n    KEEP(*(.jcr))\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.ram)\r\n    . = ALIGN (8);\r\n    _edata = .;\r\n  } >ram AT>rom\r\n  .bss :\r\n  {\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    *(.ram.b)\r\n    . = ALIGN (8);\r\n    _end = .;\r\n    __end = .;\r\n  } >ram AT>rom\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  __cs3_region_init_ram = LOADADDR (.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n  __cs3_region_num = 1;\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n\r\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\r\n  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\r\n  \/DISCARD\/ : { *(.note.GNU-stack) }\r\n}\r\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"f786095b0c948fd5a474684dad7f09b8fb199fce","subject":"AT91SAM7A3. Fixed comment in linker script.","message":"AT91SAM7A3. Fixed comment in linker script.\n\ngit-svn-id: 30f789d7039adee4ab6dc5f7dbec2df9251e516b@4881 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"os\/ports\/GCC\/ARM\/AT91SAM7\/ld\/AT91SAM7A3.ld","new_file":"os\/ports\/GCC\/ARM\/AT91SAM7\/ld\/AT91SAM7A3.ld","new_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011,2012 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * AT91SAM7A3 memory setup.\r\n *\/\r\n__und_stack_size__\t= 0x0004;\r\n__abt_stack_size__\t= 0x0004;\r\n__fiq_stack_size__\t= 0x0010;\r\n__irq_stack_size__\t= 0x0080;\r\n__svc_stack_size__\t= 0x0004;\r\n__sys_stack_size__\t= 0x0400;\r\n__stacks_total_size__\t= __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x100000, len = 256k\r\n    ram : org = 0x200020, len = 32k - 0x20\r\n}\r\n\r\n__ram_start__\t\t= ORIGIN(ram);\r\n__ram_size__\t\t= LENGTH(ram);\r\n__ram_end__\t\t= __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n\t. = 0;\r\n\r\n\t.text : ALIGN(16) SUBALIGN(16)\r\n\t{\r\n        _text = .;\r\n        KEEP(*(vectors))\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n        *(.ctors)\r\n        *(.dtors)\r\n    } > flash\r\n\r\n    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash\r\n    __exidx_end = .;\r\n\r\n    .eh_frame_hdr : {*(.eh_frame_hdr)}\r\n\r\n    .eh_frame : ONLY_IF_RO {*(.eh_frame)}\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .data :\r\n    {\r\n        _data = .;\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        _edata = .;\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        _bss_start = .;\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _bss_end = .;\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end = .;\r\n\r\n__heap_base__              = _end;\r\n__heap_end__               = __ram_end__ - __stacks_total_size__;\r\n__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__;\r\n","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011,2012 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * AT91SAM7X256 memory setup.\r\n *\/\r\n__und_stack_size__\t= 0x0004;\r\n__abt_stack_size__\t= 0x0004;\r\n__fiq_stack_size__\t= 0x0010;\r\n__irq_stack_size__\t= 0x0080;\r\n__svc_stack_size__\t= 0x0004;\r\n__sys_stack_size__\t= 0x0400;\r\n__stacks_total_size__\t= __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x100000, len = 256k\r\n    ram : org = 0x200020, len = 32k - 0x20\r\n}\r\n\r\n__ram_start__\t\t= ORIGIN(ram);\r\n__ram_size__\t\t= LENGTH(ram);\r\n__ram_end__\t\t= __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n\t. = 0;\r\n\r\n\t.text : ALIGN(16) SUBALIGN(16)\r\n\t{\r\n        _text = .;\r\n        KEEP(*(vectors))\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n        *(.ctors)\r\n        *(.dtors)\r\n    } > flash\r\n\r\n    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash\r\n    __exidx_end = .;\r\n\r\n    .eh_frame_hdr : {*(.eh_frame_hdr)}\r\n\r\n    .eh_frame : ONLY_IF_RO {*(.eh_frame)}\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .data :\r\n    {\r\n        _data = .;\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        _edata = .;\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        _bss_start = .;\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _bss_end = .;\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end = .;\r\n\r\n__heap_base__              = _end;\r\n__heap_end__               = __ram_end__ - __stacks_total_size__;\r\n__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__;\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2cb1efb9533b6a3f3d6279ce67fc37122b5c8728","subject":"[simple-system] Add missing linker sections","message":"[simple-system] Add missing linker sections\n\nAdding the \"small\" sections to the example linker script. This ensures\nthat all sections of memory needing to be zeroed are captured.\n\nFixes #1092\n\nSigned-off-by: Tom Roberts <f3b1a53ee1cbeb35a47033dea932030093853292@lowrisc.org>\n","repos":"lowRISC\/ibex,lowRISC\/ibex,AmbiML\/ibex,lowRISC\/ibex,lowRISC\/ibex,AmbiML\/ibex,AmbiML\/ibex,AmbiML\/ibex","old_file":"examples\/sw\/simple_system\/common\/link.ld","new_file":"examples\/sw\/simple_system\/common\/link.ld","new_contents":"\/* Copyright lowRISC contributors.\n   Licensed under the Apache License, Version 2.0, see LICENSE for details.\n   SPDX-License-Identifier: Apache-2.0 *\/\n\nOUTPUT_ARCH(riscv)\n\nMEMORY\n{\n    \/* 992 kB should be enough for anybody... *\/\n    ram         : ORIGIN = 0x00100000, LENGTH = 0xF8000 \/* 992 kB *\/\n    stack       : ORIGIN = 0x001F8000, LENGTH = 0x8000  \/* 32 kB *\/\n}\n\n\/* Stack information variables *\/\n_min_stack      = 0x2000;   \/* 8K - minimum stack space to reserve *\/\n_stack_len     = LENGTH(stack);\n_stack_start   = ORIGIN(stack) + LENGTH(stack);\n\n_entry_point = _vectors_start + 0x80;\nENTRY(_entry_point)\n\n\/* The tohost address is used by Spike for a magic \"stop me now\" message. This\n   is set to equal SIM_CTRL_CTRL (see simple_system_regs.h), which has that\n   effect in simple_system simulations. Note that it must be 8-byte aligned.\n\n   We don't read data back from Spike, so fromhost is set to some dummy value:\n   we place it just above the top of the stack.\n *\/\ntohost   = 0x20008;\nfromhost = _stack_start + 0x10;\n\nSECTIONS\n{\n    .vectors :\n    {\n        . = ALIGN(4);\n\t\t_vectors_start = .;\n        KEEP(*(.vectors))\n\t\t_vectors_end = .;\n    } > ram\n\n    .text : {\n        . = ALIGN(4);\n        *(.text)\n        *(.text.*)\n    }  > ram\n\n    .rodata : {\n        . = ALIGN(4);\n        \/* Small RO data before large RO data *\/\n        *(.srodata)\n        *(.srodata.*)\n        *(.rodata);\n        *(.rodata.*)\n    } > ram\n\n    .data : {\n        . = ALIGN(4);\n        \/* Small data before large data *\/\n        *(.sdata)\n        *(.sdata.*)\n        *(.data);\n        *(.data.*)\n    } > ram\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _bss_start = .;\n        \/* Small BSS before large BSS *\/\n        *(.sbss)\n        *(.sbss.*)\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        _bss_end = .;\n    } > ram\n\n    \/* ensure there is enough room for stack *\/\n    .stack (NOLOAD): {\n        . = ALIGN(4);\n        . = . + _min_stack ;\n        . = ALIGN(4);\n        stack = . ;\n        _stack = . ;\n    } > stack\n}\n","old_contents":"\/* Copyright lowRISC contributors.\n   Licensed under the Apache License, Version 2.0, see LICENSE for details.\n   SPDX-License-Identifier: Apache-2.0 *\/\n\nOUTPUT_ARCH(riscv)\n\nMEMORY\n{\n    \/* 992 kB should be enough for anybody... *\/\n    ram         : ORIGIN = 0x00100000, LENGTH = 0xF8000 \/* 992 kB *\/\n    stack       : ORIGIN = 0x001F8000, LENGTH = 0x8000  \/* 32 kB *\/\n}\n\n\/* Stack information variables *\/\n_min_stack      = 0x2000;   \/* 8K - minimum stack space to reserve *\/\n_stack_len     = LENGTH(stack);\n_stack_start   = ORIGIN(stack) + LENGTH(stack);\n\n_entry_point = _vectors_start + 0x80;\nENTRY(_entry_point)\n\n\/* The tohost address is used by Spike for a magic \"stop me now\" message. This\n   is set to equal SIM_CTRL_CTRL (see simple_system_regs.h), which has that\n   effect in simple_system simulations. Note that it must be 8-byte aligned.\n\n   We don't read data back from Spike, so fromhost is set to some dummy value:\n   we place it just above the top of the stack.\n *\/\ntohost   = 0x20008;\nfromhost = _stack_start + 0x10;\n\nSECTIONS\n{\n    .vectors :\n    {\n        . = ALIGN(4);\n\t\t_vectors_start = .;\n        KEEP(*(.vectors))\n\t\t_vectors_end = .;\n    } > ram\n\n    .text : {\n        . = ALIGN(4);\n        *(.text)\n        *(.text.*)\n    }  > ram\n\n    .rodata : {\n        . = ALIGN(4);\n        *(.rodata);\n        *(.rodata.*)\n    } > ram\n\n    .data : {\n        . = ALIGN(4);\n        *(.data);\n        *(.data.*)\n    } > ram\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        _bss_end = .;\n    } > ram\n\n    \/* ensure there is enough room for stack *\/\n    .stack (NOLOAD): {\n        . = ALIGN(4);\n        . = . + _min_stack ;\n        . = ALIGN(4);\n        stack = . ;\n        _stack = . ;\n    } > stack\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c012a288c371c69420ea25c3bb7bb9af5a743f07","subject":"arch: arm: fix bug in linker symbol definitions for application memory","message":"arch: arm: fix bug in linker symbol definitions for application memory\n\nThe definition of __app_ram_end linker symbol has been\nerroneously placed outside the last linker section of\napplication memory. This commit fixes the problem.\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\n","repos":"GiulianoFranchetto\/zephyr,galak\/zephyr,explora26\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,punitvara\/zephyr,explora26\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,explora26\/zephyr,explora26\/zephyr,galak\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,punitvara\/zephyr,galak\/zephyr,ldts\/zephyr,explora26\/zephyr,ldts\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\tMPU_ALIGN(__app_ram_size);\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\n\t\t__app_last_address_used = .;\n\n\t\t\/* Align the end of the application memory\n\t\t * with MPU alignment requirement.\n\t\t *\/\n\t\tMPU_ALIGN(__app_ram_size);\n\t\t__app_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n#if defined(CONFIG_NOCACHE_MEMORY)\n\t\/* Non-cached region of RAM *\/\n\tSECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.nocache)\n\t\tKERNEL_INPUT_SECTION(\".nocache.*\")\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\t_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;\n#endif \/* CONFIG_NOCACHE_MEMORY *\/\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tAPP_SHARED_ALIGN;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t\/* Align the end of shared app mem section with the\n\t\t * minimum granularity required by MPU.\n\t\t *\/\n\t\tAPP_SHARED_ALIGN;\n\t\t_app_smem_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\tMPU_ALIGN(__app_ram_size);\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Align the end of the application memory\n\t * with MPU alignment requirement.\n\t *\/\n\tMPU_ALIGN(__app_ram_size);\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n#if defined(CONFIG_NOCACHE_MEMORY)\n\t\/* Non-cached region of RAM *\/\n\tSECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.nocache)\n\t\tKERNEL_INPUT_SECTION(\".nocache.*\")\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\t_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;\n#endif \/* CONFIG_NOCACHE_MEMORY *\/\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tAPP_SHARED_ALIGN;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t\/* Align the end of shared app mem section with the\n\t\t * minimum granularity required by MPU.\n\t\t *\/\n\t\tAPP_SHARED_ALIGN;\n\t\t_app_smem_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a353e5b089950c15131aaa6594d1c4e1447145d5","subject":"[sw] handle DWARF5 sections","message":"[sw] handle DWARF5 sections\n\nWhen (cross-)building with GCC 11, we are getting new DWARF5 debug\nsections. Ensure they are properly handled by the linker script rather\nthan failing the build with warnings such as:\n```\nbin\/ld: warning: orphan section `.debug_rnglists' from\n`sw\/device\/lib\/dif\/libsw_lib_dif_spi_device.a(dif_spi_device.c.o)' being\nplaced in section `.debug_rnglists'\n```\n\nFixes #9023\n\nSigned-off-by: Vincent Palatin <70a9964ec8fd10b0b08fcc8623c2add25ddf99ac@rivosinc.com>\n","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan","old_file":"sw\/device\/info_sections.ld","new_file":"sw\/device\/info_sections.ld","new_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * Partial Linker Script for OpenTitan Device Executables\n *\n * This Linker Script controls all the sections that we need in the ELF file for\n * a device executable, but which are not mapped into memory or otherwise\n * allocated on the device itself.\n *\n * These contain amongst other things:\n * - debugging information needed by DV logging,\n * - DWARF Sections\n * - RISC-V Attributes sections\n *\n * This is also where we specify the sections to discard, because it is a common\n * file between all our other linker scripts.\n *\n * This partial linker script requires the main linker script to define the\n * following symbols:\n * - _dv_log_offset\n *\/\n\n\/*\n * Start DV Sections.\n *\n * The following sections are used by DV to implement logging in an\n * alternate way, which enables simulation speed up by completely avoiding\n * any string format processing or even the actual transmission of log data\n * to a real peripheral.\n *\n * These sections are marked as dummy so that they can still be extracted\n * using readelf or similar utilities. As such, the content in these sections\n * is not relevant for the actual SW code and can be safely discarded.\n *\/\n\n\/**\n * The following section contains log fields constructed from the logs using\n * the log_fields_t struct defined in sw\/device\/lib\/runtime\/log.h. The size of\n * each log field is fixed - 20 bytes.\n *\/\n.logs.fields _dv_log_offset (INFO): {\n  *(.logs.fields)\n}\n\n\/*\n * End DV Sections\n *\/\n\n\/* ELF-internal Sections. *\/\n.symtab 0x0 : { *(.symtab) }\n.strtab 0x0 : { *(.strtab) }\n.shstrtab 0x0 : { *(.shstrtab) }\n\n\/* Preserve RISC-V Attributes *\/\n.riscv.attributes 0x0 : { *(.riscv.attributes) }\n\n\/* Preserve Debug Info in ELF Files *\/\n.debug_info 0x0 : { *(.debug_info) }\n.debug_abbrev 0x0 : { *(.debug_abbrev) }\n.debug_aranges 0x0 : { *(.debug_aranges) }\n.debug_line 0x0 : { *(.debug_line) }\n.debug_loc 0x0 : { *(.debug_loc) }\n.debug_ranges 0x0 : { *(.debug_ranges) }\n.debug_str 0x0 : { *(.debug_str) }\n.debug_frame 0x0 : { *(.debug_frame) }\n.debug_line_str 0x0 : { *(.debug_line_str) }\n.debug_loclists 0x0 : { *(.debug_loclists) }\n.debug_rnglists 0x0 : { *(.debug_rnglists) }\n\n\/* Discarded Sections (Not needed in device images). *\/\n\/DISCARD\/ : {\n  \/* We don't keep unwind information *\/\n  *(.eh_frame)\n  *(.eh_frame_hdr)\n\n  \/* Compiler Information *\/\n  *(.comment)\n  *(.comment.*)\n\n  \/* Other Notes *\/\n  *(.note)\n  *(.note.*)\n\n  \/* Relocations *\/\n  *(.rela.*)\n  *(.rela.dyn)\n\n  \/* STAB Debugging Info - We Use DWARF *\/\n  *(.stab)\n  *(.stab.*)\n  *(.stabstr)\n\n  \/* COMMON Sections *\/\n  *(COMMON)\n}\n","old_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * Partial Linker Script for OpenTitan Device Executables\n *\n * This Linker Script controls all the sections that we need in the ELF file for\n * a device executable, but which are not mapped into memory or otherwise\n * allocated on the device itself.\n *\n * These contain amongst other things:\n * - debugging information needed by DV logging,\n * - DWARF Sections\n * - RISC-V Attributes sections\n *\n * This is also where we specify the sections to discard, because it is a common\n * file between all our other linker scripts.\n *\n * This partial linker script requires the main linker script to define the\n * following symbols:\n * - _dv_log_offset\n *\/\n\n\/*\n * Start DV Sections.\n *\n * The following sections are used by DV to implement logging in an\n * alternate way, which enables simulation speed up by completely avoiding\n * any string format processing or even the actual transmission of log data\n * to a real peripheral.\n *\n * These sections are marked as dummy so that they can still be extracted\n * using readelf or similar utilities. As such, the content in these sections\n * is not relevant for the actual SW code and can be safely discarded.\n *\/\n\n\/**\n * The following section contains log fields constructed from the logs using\n * the log_fields_t struct defined in sw\/device\/lib\/runtime\/log.h. The size of\n * each log field is fixed - 20 bytes.\n *\/\n.logs.fields _dv_log_offset (INFO): {\n  *(.logs.fields)\n}\n\n\/*\n * End DV Sections\n *\/\n\n\/* ELF-internal Sections. *\/\n.symtab 0x0 : { *(.symtab) }\n.strtab 0x0 : { *(.strtab) }\n.shstrtab 0x0 : { *(.shstrtab) }\n\n\/* Preserve RISC-V Attributes *\/\n.riscv.attributes 0x0 : { *(.riscv.attributes) }\n\n\/* Preserve Debug Info in ELF Files *\/\n.debug_info 0x0 : { *(.debug_info) }\n.debug_abbrev 0x0 : { *(.debug_abbrev) }\n.debug_aranges 0x0 : { *(.debug_aranges) }\n.debug_line 0x0 : { *(.debug_line) }\n.debug_loc 0x0 : { *(.debug_loc) }\n.debug_ranges 0x0 : { *(.debug_ranges) }\n.debug_str 0x0 : { *(.debug_str) }\n.debug_frame 0x0 : { *(.debug_frame) }\n\n\/* Discarded Sections (Not needed in device images). *\/\n\/DISCARD\/ : {\n  \/* We don't keep unwind information *\/\n  *(.eh_frame)\n  *(.eh_frame_hdr)\n\n  \/* Compiler Information *\/\n  *(.comment)\n  *(.comment.*)\n\n  \/* Other Notes *\/\n  *(.note)\n  *(.note.*)\n\n  \/* Relocations *\/\n  *(.rela.*)\n  *(.rela.dyn)\n\n  \/* STAB Debugging Info - We Use DWARF *\/\n  *(.stab)\n  *(.stab.*)\n  *(.stabstr)\n\n  \/* COMMON Sections *\/\n  *(COMMON)\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"09e7a5e5bf8f83066e69e4e204fabc5d3ac87f62","subject":"remove obsolete alignment to a page boundary","message":"remove obsolete alignment to a page boundary\n","repos":"RWTH-OS\/eduOS-rs","old_file":"kernel\/src\/arch\/x86_64\/linker.ld","new_file":"kernel\/src\/arch\/x86_64\/linker.ld","new_contents":"OUTPUT_FORMAT(\"elf64-x86-64\")\nOUTPUT_ARCH(\"i386:x86-64\")\nENTRY(rust_start)\n\nSECTIONS {\n\t\/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n\t. = 2M;\n\n\tkernel_start = .;\n\n\t.boot :\n\t{\n\t\t\/* This goes first. *\/\n\t\tKEEP(*(.kheader))\n\t}\n\n\t.text : AT(ADDR(.text))\n\t{\n\t\t*(.text)\n\t\t*(.text.*)\n\t}\n\n\t.rodata : AT(ADDR(.rodata))\n\t{\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t}\n\n\t.data ALIGN(4096) : AT(ADDR(.data))\n\t{\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n\n\t.bss ALIGN(4096) : AT(ADDR(.bss))\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t}\n\tkernel_end = .;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf64-x86-64\")\nOUTPUT_ARCH(\"i386:x86-64\")\nENTRY(rust_start)\n\nSECTIONS {\n\t\/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n\t. = 2M;\n\n\tkernel_start = .;\n\n\t.boot :\n\t{\n\t\t\/* This goes first. *\/\n\t\tKEEP(*(.kheader))\n\t}\n\n\t.text ALIGN(4096) : AT(ADDR(.text))\n\t{\n\t\t*(.text)\n\t\t*(.text.*)\n\t}\n\n\t.rodata : AT(ADDR(.rodata))\n\t{\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t}\n\n\t.data ALIGN(4096) : AT(ADDR(.data))\n\t{\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n\n\t.bss ALIGN(4096) : AT(ADDR(.bss))\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t}\n\tkernel_end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8349fd0bb9977e17014064b4c3a5aae22eb989e4","subject":"nrf5\/boards: Tuning linker script for nrf51822_ac to get some more heap.","message":"nrf5\/boards: Tuning linker script for nrf51822_ac to get some more heap.\n","repos":"tralamazza\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,tralamazza\/micropython","old_file":"nrf5\/boards\/nrf51822_ac.ld","new_file":"nrf5\/boards\/nrf51822_ac.ld","new_contents":"\/*\n    GNU linker script for NRF52 blank w\/ no SoftDevice\n*\/\n\/* Specify the memory areas *\/\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x000400 \/* sector 0, 1 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00000400, LENGTH = 0x03F000 \/* 255 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x008000 \/* 32 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 20K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20005000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52 blank w\/ no SoftDevice\n*\/\n\/* Specify the memory areas *\/\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x000400 \/* sector 0, 1 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00000400, LENGTH = 0x03F000 \/* 255 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x008000 \/* 32 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 10K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20001000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e5fc236f8da0fc80a3aa4f0dcce2e367b37a4b12","subject":"put NOLOAD on persistent data section","message":"put NOLOAD on persistent data section\n\n\nFormer-commit-id: 0726be634dd7106eda57a21c34d6ce43ec5ed373\n","repos":"pontech\/chipKIT-core,adamwolf\/chipKIT-core,chipKIT32\/chipkit-core,chipKIT32\/chipkit-core,chipKIT32\/chipkit-core,adamwolf\/chipKIT-core,UECIDE\/chipKIT-core,majenkotech\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,ricklon\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,EmbeddedMan\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,UECIDE\/chipKIT-core,chipKIT32\/chipkit-core,majenkotech\/chipKIT-core,chipKIT32\/chipkit-core,pontech\/chipKIT-core,pontech\/chipKIT-core,ricklon\/chipKIT-core,adamwolf\/chipKIT-core,pontech\/chipKIT-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,UECIDE\/chipKIT-core,majenkotech\/chipKIT-core,ricklon\/chipKIT-core,EmbeddedMan\/chipKIT-core,adamwolf\/chipKIT-core,pontech\/chipKIT-core,UECIDE\/chipKIT-core,adamwolf\/chipKIT-core,UECIDE\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,ricklon\/chipKIT-core,EmbeddedMan\/chipKIT-core","old_file":"pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_file":"pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_contents":"\/************************************************************************\r\n *\tchipKIT-applicaiton-COMMON.ld\r\n *\t\r\n *\tThis is the common part of the linker script shared\r\n *\tacross all chipKIT PIC32 processors \/ boards.\r\n *\t\r\n ************************************************************************\r\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\r\n * \tThis library is free software; you can redistribute it and\/or\r\n *  modify it under the terms of the GNU Lesser General Public\r\n *\tLicense as published by the Free Software Foundation; either\r\n *\tversion 2.1 of the License, or (at your option) any later version.\r\n *\t\r\n *\tThis library is distributed in the hope that it will be useful,\r\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\r\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\r\n *\tLesser General Public License for more details.\r\n *\t\r\n *\tYou should have received a copy of the GNU Lesser General\r\n *\tPublic License along with this library; if not, write to the\r\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\r\n *\tBoston, MA\t02111-1307\tUSA\r\n *\t\r\n *\t\r\n ************************************************************************\r\n *\tEdit History\r\n ************************************************************************\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\r\n ************************************************************************\r\n *\/\r\n\r\n\/*************************************************************************\r\n * For interrupt vector handling\r\n *************************************************************************\/\r\nPROVIDE(_vector_spacing = 0x00000001);\r\n\r\n\/*************************************************************************\r\n * Start the layout of memory, the sections...\r\n *************************************************************************\/\r\nSECTIONS\r\n{\r\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\r\n  {\r\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\r\n  } > kseg0_eeprom_mem\r\n\r\n  \/DISCARD\/ : { *(.bev_handler) }\r\n\r\n .image_ptr_table _IMAGE_PTR_TABLE :\r\n  {\r\n    LONG(_ebase_address)\t\r\n    LONG(_image_header_info)\r\n  } > exception_mem\r\n\r\n  .app_excpt _GEN_EXCPT_ADDR :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  } > exception_mem\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  .startup :\r\n  {\r\n    KEEP(*(.startup))\r\n  } > kseg0_program_mem\r\n  \/* Code Sections *\/\r\n\r\n  .text  :\r\n  {\r\n    _text_begin = . ;\r\n\r\n    *(.text .stub .text.* .gnu.linkonce.t.*)\r\n    KEEP (*(.text.*personality*))\r\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\r\n    *(.gnu.warning)\r\n    *(.mips16.fn.*)\r\n    *(.mips16.call.*)\r\n    . = ALIGN(4) ;\r\n    _text_end = . ;\r\n  } >kseg0_program_mem =0\r\n\r\n   .init      :\r\n  {\r\n\tKEEP (*crti.o(.init))\r\n\tKEEP (*crtbegin.o(.init))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\r\n\tKEEP (*crtend.o(.init))\r\n    KEEP (*crtn.o(.init))\r\n    . = ALIGN(4) ;\r\n  }  >kseg0_program_mem\r\n\r\n  .fini       :\r\n  {\r\n    KEEP (*(.fini))\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .init_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .fini_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .ctors        :\r\n  {\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  .dtors          :\r\n  {\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  .preinit_array    :\r\n  {\r\n    KEEP (*(.preinit_array))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  \/* Read-only sections *\/\r\n  .header_info ALIGN(4) :\r\n  {\r\n    _image_header_info = . ;\r\n    LONG(SIZEOF(.header_info))          \/* size of this structure       *\/\r\n    LONG(0xFFFFFFFF)                    \/* bootloader version           *\/\r\n    KEEP(*(.mpide_version))             \/* MPIDE build version          *\/\r\n    LONG(0xFFFFFFFF)                    \/* booloader capabilities       *\/\r\n    LONG(0xFFFFFFFF)                    \/* VID and PID                  *\/\r\n    LONG(_IMAGE_TYPE)                   \/* image type and options       *\/\r\n    LONG(_JUMP_ADDR)                    \/* image execution address      *\/\r\n    LONG(_ebase_address)                \/* image base address           *\/\r\n    LONG(_IMAGE_FLASH_SIZE)             \/* size of image flash used     *\/\r\n    LONG(ORIGIN(kseg0_eeprom_mem))      \/* eeprom location              *\/\r\n    LONG(LENGTH(kseg0_eeprom_mem))      \/* eeprom size                  *\/   \r\n    LONG(ORIGIN(configsfrs))            \/* config bits location         *\/\r\n    LONG(LENGTH(configsfrs))            \/* config bits size             *\/\r\n    LONG(_ram_header_addr)              \/* ram header pointer           *\/\r\n    LONG(SIZEOF(.ram_exchange_data))    \/* ram Header size              *\/\r\n    LONG(0xFFFFFFFF)                    \/* what the bootloader skips    *\/\r\n    _image_header_info_end = . ;\r\n  } > kseg0_program_mem\r\n  ASSERT (SIZEOF(.header_info) == 64, \"MPIDE Version not specfied correctly\")\r\n\r\n  .rodata  ALIGN(4) :\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.rodata1)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  \/*\r\n   * Small initialized constant global and static data can be placed in the\r\n   * .sdata2 section.  This is different from .sdata, which contains small\r\n   * initialized non-constant global and static data.\r\n   *\/\r\n  .sdata2 ALIGN(4)   :\r\n  {\r\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  \/*\r\n   * Uninitialized constant global and static data (i.e., variables which will\r\n   * always be zero).  Again, this is different from .sbss, which contains\r\n   * small non-initialized, non-constant global and static data.\r\n   *\/\r\n  .sbss2 ALIGN(4)   :\r\n  {\r\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\r\n  {\r\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\r\n  } >kseg1_data_mem\r\n  \r\n  .ram_exchange_data (NOLOAD) :\r\n  {\r\n    _ram_header_addr = . ;\r\n    . += 8 ;\r\n  } >kseg1_data_mem\r\n\r\n  \/* Persistent data *\/\r\n  .persist ALIGN(4) (NOLOAD) :\r\n  {\r\n    _persist_begin = .;\r\n    *(.persist .persist.*)\r\n    . = ALIGN(4) ;\r\n    _persist_end = .;\r\n  } >kseg1_data_mem\r\n\r\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\r\n\r\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\r\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\r\n\r\n  .data  _protected_end :\r\n  { \r\n    _data_begin = . ;\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    KEEP (*(.gnu.linkonce.d.*personality*))\r\n\r\n    *(.data1)\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  _data_image_begin = LOADADDR(.data) ;\r\n  . = .;\r\n  _gp = ALIGN(16) + 0x7ff0;\r\n\r\n  .got ALIGN(4)   :\r\n  {\r\n     *(.got.plt) *(.got)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n  \/*\r\n   * We want the small data sections together, so single-instruction offsets\r\n   * can access them all, and initialized data all before uninitialized, so\r\n   * we can shorten the on-disk segment size.\r\n   *\/\r\n  .sdata ALIGN(4)   :\r\n  {\r\n    _sdata_begin = . ;\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n    . = ALIGN(4) ;\r\n    _sdata_end = . ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  .lit8           :\r\n  {\r\n    *(.lit8)\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  .lit4           :\r\n  {\r\n    *(.lit4)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  . = ALIGN (4) ;\r\n  _data_end = . ;\r\n  _bss_begin = . ;\r\n\r\n  .sbss ALIGN(4)   :\r\n  {\r\n    _sbss_begin = . ;\r\n    *(.dynsbss)\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    . = ALIGN(4) ;\r\n    _sbss_end = . ;\r\n  } >kseg1_data_mem\r\n\r\n  .bss   :\r\n  {\r\n    *(.dynbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    \/*\r\n     * Align here to ensure that the .bss section occupies space up to\r\n     * _end.  Align after .bss to ensure correct alignment even if the\r\n     * .bss section disappears because there are no input sections.\r\n     *\/\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem\r\n\r\n  . = ALIGN(4) ;\r\n  _end = . ;\r\n  _bss_end = . ;\r\n\r\n  \/* Heap allocating takes a chunk of memory following BSS *\/\r\n  .heap ALIGN(8) :\r\n  {\r\n    _heap = . ;\r\n    . += _min_heap_size ;\r\n    . = ALIGN(8);\r\n  } >kseg1_data_mem\r\n\r\n  \/* Stack allocation follows the heap *\/\r\n  .stack ALIGN(8) :\r\n  {\r\n    _splim = . ;\r\n    _SPLIM = . ;\r\n    . += _min_stack_size ;\r\n    . = ALIGN(8);\r\n  } >kseg1_data_mem\r\n\r\n  \/*\r\n   * RAM functions go at the end of our stack and heap allocation.\r\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\r\n   *\/\r\n  .ramfunc ALIGN(2K) :\r\n  {\r\n    _ramfunc_begin = . ;\r\n    *(.ramfunc  .ramfunc.*)\r\n    . = ALIGN(4) ;\r\n    _ramfunc_end = . ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\r\n  _ramfunc_length = SIZEOF(.ramfunc) ;\r\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\r\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\r\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\r\n  \/*\r\n   * The actual top of stack should include the gap between the stack\r\n   * section and the beginning of the .ramfunc section caused by the\r\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\r\n   * do not exist, then the top of the stack should point to the end of\r\n   * the data memory.\r\n   *\/\r\n  _stack = (_ramfunc_length > 0)\r\n         ? _ramfunc_begin - 4\r\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\r\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\r\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\r\n    \/* The .pdr section belongs in the absolute section *\/\r\n    \/DISCARD\/ : { *(.pdr) }\r\n    \/* We don't load .reginfo onto the target, so don't locate it\r\n     * in real memory\r\n     *\/\r\n    \/DISCARD\/ : { *(.reginfo) }\r\n  \/* Stabs debugging sections.  *\/\r\n  .stab          0 : { *(.stab) }\r\n  .stabstr       0 : { *(.stabstr) }\r\n  .stab.excl     0 : { *(.stab.excl) }\r\n  .stab.exclstr  0 : { *(.stab.exclstr) }\r\n  .stab.index    0 : { *(.stab.index) }\r\n  .stab.indexstr 0 : { *(.stab.indexstr) }\r\n  .comment       0 : { *(.comment) }\r\n  \/* DWARF debug sections.\r\n     Symbols in the DWARF debugging sections are relative to the beginning\r\n     of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0  : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n  \/* DWARF 3 *\/\r\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\r\n  .debug_ranges   0 : { *(.debug_ranges) }\r\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\r\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\r\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\r\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\r\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\r\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\r\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\r\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\r\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\r\n  \/DISCARD\/ : { *(.rel.dyn) }\r\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\r\n}\r\n","old_contents":"\/************************************************************************\r\n *\tchipKIT-applicaiton-COMMON.ld\r\n *\t\r\n *\tThis is the common part of the linker script shared\r\n *\tacross all chipKIT PIC32 processors \/ boards.\r\n *\t\r\n ************************************************************************\r\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\r\n * \tThis library is free software; you can redistribute it and\/or\r\n *  modify it under the terms of the GNU Lesser General Public\r\n *\tLicense as published by the Free Software Foundation; either\r\n *\tversion 2.1 of the License, or (at your option) any later version.\r\n *\t\r\n *\tThis library is distributed in the hope that it will be useful,\r\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\r\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\r\n *\tLesser General Public License for more details.\r\n *\t\r\n *\tYou should have received a copy of the GNU Lesser General\r\n *\tPublic License along with this library; if not, write to the\r\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\r\n *\tBoston, MA\t02111-1307\tUSA\r\n *\t\r\n *\t\r\n ************************************************************************\r\n *\tEdit History\r\n ************************************************************************\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\r\n ************************************************************************\r\n *\/\r\n\r\n\/*************************************************************************\r\n * For interrupt vector handling\r\n *************************************************************************\/\r\nPROVIDE(_vector_spacing = 0x00000001);\r\n\r\n\/*************************************************************************\r\n * Start the layout of memory, the sections...\r\n *************************************************************************\/\r\nSECTIONS\r\n{\r\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\r\n  {\r\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\r\n  } > kseg0_eeprom_mem\r\n\r\n  \/DISCARD\/ : { *(.bev_handler) }\r\n\r\n .image_ptr_table _IMAGE_PTR_TABLE :\r\n  {\r\n    LONG(_ebase_address)\t\r\n    LONG(_image_header_info)\r\n  } > exception_mem\r\n\r\n  .app_excpt _GEN_EXCPT_ADDR :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  } > exception_mem\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  .startup :\r\n  {\r\n    KEEP(*(.startup))\r\n  } > kseg0_program_mem\r\n  \/* Code Sections *\/\r\n\r\n  .text  :\r\n  {\r\n    _text_begin = . ;\r\n\r\n    *(.text .stub .text.* .gnu.linkonce.t.*)\r\n    KEEP (*(.text.*personality*))\r\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\r\n    *(.gnu.warning)\r\n    *(.mips16.fn.*)\r\n    *(.mips16.call.*)\r\n    . = ALIGN(4) ;\r\n    _text_end = . ;\r\n  } >kseg0_program_mem =0\r\n\r\n   .init      :\r\n  {\r\n\tKEEP (*crti.o(.init))\r\n\tKEEP (*crtbegin.o(.init))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\r\n\tKEEP (*crtend.o(.init))\r\n    KEEP (*crtn.o(.init))\r\n    . = ALIGN(4) ;\r\n  }  >kseg0_program_mem\r\n\r\n  .fini       :\r\n  {\r\n    KEEP (*(.fini))\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .init_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .fini_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .ctors        :\r\n  {\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  .dtors          :\r\n  {\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  .preinit_array    :\r\n  {\r\n    KEEP (*(.preinit_array))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  \/* Read-only sections *\/\r\n  .header_info ALIGN(4) :\r\n  {\r\n    _image_header_info = . ;\r\n    LONG(SIZEOF(.header_info))          \/* size of this structure       *\/\r\n    LONG(0xFFFFFFFF)                    \/* bootloader version           *\/\r\n    KEEP(*(.mpide_version))             \/* MPIDE build version          *\/\r\n    LONG(0xFFFFFFFF)                    \/* booloader capabilities       *\/\r\n    LONG(0xFFFFFFFF)                    \/* VID and PID                  *\/\r\n    LONG(_IMAGE_TYPE)                   \/* image type and options       *\/\r\n    LONG(_JUMP_ADDR)                    \/* image execution address      *\/\r\n    LONG(_ebase_address)                \/* image base address           *\/\r\n    LONG(_IMAGE_FLASH_SIZE)             \/* size of image flash used     *\/\r\n    LONG(ORIGIN(kseg0_eeprom_mem))      \/* eeprom location              *\/\r\n    LONG(LENGTH(kseg0_eeprom_mem))      \/* eeprom size                  *\/   \r\n    LONG(ORIGIN(configsfrs))            \/* config bits location         *\/\r\n    LONG(LENGTH(configsfrs))            \/* config bits size             *\/\r\n    LONG(_ram_header_addr)              \/* ram header pointer           *\/\r\n    LONG(SIZEOF(.ram_exchange_data))    \/* ram Header size              *\/\r\n    LONG(0xFFFFFFFF)                    \/* what the bootloader skips    *\/\r\n    _image_header_info_end = . ;\r\n  } > kseg0_program_mem\r\n  ASSERT (SIZEOF(.header_info) == 64, \"MPIDE Version not specfied correctly\")\r\n\r\n  .rodata  ALIGN(4) :\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.rodata1)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  \/*\r\n   * Small initialized constant global and static data can be placed in the\r\n   * .sdata2 section.  This is different from .sdata, which contains small\r\n   * initialized non-constant global and static data.\r\n   *\/\r\n  .sdata2 ALIGN(4)   :\r\n  {\r\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  \/*\r\n   * Uninitialized constant global and static data (i.e., variables which will\r\n   * always be zero).  Again, this is different from .sbss, which contains\r\n   * small non-initialized, non-constant global and static data.\r\n   *\/\r\n  .sbss2 ALIGN(4)   :\r\n  {\r\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\r\n  {\r\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\r\n  } >kseg1_data_mem\r\n  \r\n  .ram_exchange_data :\r\n  {\r\n    _ram_header_addr = . ;\r\n    . += 8 ;\r\n  } >kseg1_data_mem\r\n\r\n  \/* Persistent data *\/\r\n  .persist ALIGN(4) :\r\n  {\r\n    _persist_begin = .;\r\n    *(.persist .persist.*)\r\n    . = ALIGN(4) ;\r\n    _persist_end = .;\r\n  } >kseg1_data_mem\r\n\r\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\r\n\r\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\r\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\r\n\r\n  .data  _protected_end :\r\n  { \r\n    _data_begin = . ;\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    KEEP (*(.gnu.linkonce.d.*personality*))\r\n\r\n    *(.data1)\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  _data_image_begin = LOADADDR(.data) ;\r\n  . = .;\r\n  _gp = ALIGN(16) + 0x7ff0;\r\n\r\n  .got ALIGN(4)   :\r\n  {\r\n     *(.got.plt) *(.got)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n  \/*\r\n   * We want the small data sections together, so single-instruction offsets\r\n   * can access them all, and initialized data all before uninitialized, so\r\n   * we can shorten the on-disk segment size.\r\n   *\/\r\n  .sdata ALIGN(4)   :\r\n  {\r\n    _sdata_begin = . ;\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n    . = ALIGN(4) ;\r\n    _sdata_end = . ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  .lit8           :\r\n  {\r\n    *(.lit8)\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  .lit4           :\r\n  {\r\n    *(.lit4)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  . = ALIGN (4) ;\r\n  _data_end = . ;\r\n  _bss_begin = . ;\r\n\r\n  .sbss ALIGN(4)   :\r\n  {\r\n    _sbss_begin = . ;\r\n    *(.dynsbss)\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    . = ALIGN(4) ;\r\n    _sbss_end = . ;\r\n  } >kseg1_data_mem\r\n\r\n  .bss   :\r\n  {\r\n    *(.dynbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    \/*\r\n     * Align here to ensure that the .bss section occupies space up to\r\n     * _end.  Align after .bss to ensure correct alignment even if the\r\n     * .bss section disappears because there are no input sections.\r\n     *\/\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem\r\n\r\n  . = ALIGN(4) ;\r\n  _end = . ;\r\n  _bss_end = . ;\r\n\r\n  \/* Heap allocating takes a chunk of memory following BSS *\/\r\n  .heap ALIGN(8) :\r\n  {\r\n    _heap = . ;\r\n    . += _min_heap_size ;\r\n    . = ALIGN(8);\r\n  } >kseg1_data_mem\r\n\r\n  \/* Stack allocation follows the heap *\/\r\n  .stack ALIGN(8) :\r\n  {\r\n    _splim = . ;\r\n    _SPLIM = . ;\r\n    . += _min_stack_size ;\r\n    . = ALIGN(8);\r\n  } >kseg1_data_mem\r\n\r\n  \/*\r\n   * RAM functions go at the end of our stack and heap allocation.\r\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\r\n   *\/\r\n  .ramfunc ALIGN(2K) :\r\n  {\r\n    _ramfunc_begin = . ;\r\n    *(.ramfunc  .ramfunc.*)\r\n    . = ALIGN(4) ;\r\n    _ramfunc_end = . ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\r\n  _ramfunc_length = SIZEOF(.ramfunc) ;\r\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\r\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\r\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\r\n  \/*\r\n   * The actual top of stack should include the gap between the stack\r\n   * section and the beginning of the .ramfunc section caused by the\r\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\r\n   * do not exist, then the top of the stack should point to the end of\r\n   * the data memory.\r\n   *\/\r\n  _stack = (_ramfunc_length > 0)\r\n         ? _ramfunc_begin - 4\r\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\r\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\r\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\r\n    \/* The .pdr section belongs in the absolute section *\/\r\n    \/DISCARD\/ : { *(.pdr) }\r\n    \/* We don't load .reginfo onto the target, so don't locate it\r\n     * in real memory\r\n     *\/\r\n    \/DISCARD\/ : { *(.reginfo) }\r\n  \/* Stabs debugging sections.  *\/\r\n  .stab          0 : { *(.stab) }\r\n  .stabstr       0 : { *(.stabstr) }\r\n  .stab.excl     0 : { *(.stab.excl) }\r\n  .stab.exclstr  0 : { *(.stab.exclstr) }\r\n  .stab.index    0 : { *(.stab.index) }\r\n  .stab.indexstr 0 : { *(.stab.indexstr) }\r\n  .comment       0 : { *(.comment) }\r\n  \/* DWARF debug sections.\r\n     Symbols in the DWARF debugging sections are relative to the beginning\r\n     of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0  : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n  \/* DWARF 3 *\/\r\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\r\n  .debug_ranges   0 : { *(.debug_ranges) }\r\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\r\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\r\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\r\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\r\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\r\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\r\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\r\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\r\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\r\n  \/DISCARD\/ : { *(.rel.dyn) }\r\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"acbd147dae0fe9f0ac90b81160042b002094ad6b","subject":"Get additional 32K of RAM on nrf52. See errata #33 and #34","message":"Get additional 32K of RAM on nrf52. See errata #33 and #34\n","repos":"IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,mlaz\/mynewt-core,wes3\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,IMGJulian\/incubator-mynewt-core","old_file":"hw\/bsp\/nrf52pdk\/nrf52pdk.ld","new_file":"hw\/bsp\/nrf52pdk\/nrf52pdk.ld","new_contents":"\/**\n * Copyright (c) 2015 Runtime Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n *   http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script for Nordic Semiconductor nRF5 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* \n * NOTE: This linker script is for version 1.0 of the nrf52. See\n * errata #33 and #34 on nordic infocenter website for details. This errata\n * causes us to allocate a memory regision we call \"CODE_RAM\" so that we can\n * access the full 64K RAM provided by the chip.\n *\/ \nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000\n  CODE_RAM (rwx) : ORIGIN = 0x8000000, LENGTH = 0x8000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        __isr_vector_start = .;\n        KEEP(*(.isr_vector))\n        __isr_vector_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .vector_relocation :\n    {\n        . = ALIGN(4);\n        __vector_tbl_reloc__ = .;\n        . = . + (__isr_vector_end - __isr_vector_start);\n        . = ALIGN(4);\n    } > RAM\n            \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        *(.preinit_array)\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        *(SORT(.init_array.*))\n        *(.init_array)\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > CODE_RAM\n\n    \/* \n     * Place heap and stack in CODE_RAM. Heap is at start, stack is at the\n     * top and stack limit is the bottom of the stack.\n     *\/\n    __HeapBase = ORIGIN(CODE_RAM);\n    __StackTop = ORIGIN(CODE_RAM) + LENGTH(CODE_RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Top of head is the bottom of the stack *\/\n    __HeapLimit = __StackLimit;\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","old_contents":"\/**\n * Copyright (c) 2015 Runtime Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n *   http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script for Nordic Semiconductor nRF5 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000\n  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x8000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        __isr_vector_start = .;\n        KEEP(*(.isr_vector))\n        __isr_vector_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .vector_relocation :\n    {\n        . = ALIGN(4);\n        __vector_tbl_reloc__ = .;\n        . = . + (__isr_vector_end - __isr_vector_start);\n        . = ALIGN(4);\n    } > RAM\n            \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        *(.preinit_array)\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        *(SORT(.init_array.*))\n        *(.init_array)\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    \/* Heap starts after BSS *\/\n    __HeapBase = .;\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Top of head is the bottom of the stack *\/\n    __HeapLimit = __StackLimit;\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"78f3100b5a116a97c2e9e16eae4ed4e528bf6778","subject":"Fix around programs","message":"Fix around programs\n","repos":"onchipuis\/mriscv_vivado,ckdur\/mriscv_vivado_arty,onchipuis\/mriscv_vivado,onchipuis\/mriscv_vivado,ckdur\/mriscv_vivado_arty,ckdur\/mriscv_vivado_arty,onchipuis\/mriscv_vivado,onchipuis\/mriscv_vivado,ckdur\/mriscv_vivado_arty","old_file":"tests\/mriscv_fpga.ld","new_file":"tests\/mriscv_fpga.ld","new_contents":"\/*\n  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.\n\n  This library is free software; you can redistribute it and\/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*\/\n\n\/* Linker script to configure memory regions.\n * Need modifying for a specific board.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00800000 \/*Put here if necesary bootloader start addressing*\/\n  RAM (rwx) : ORIGIN = 0x00800000, LENGTH = 0x00001000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t\/** TODO: maybe this is necesary if there is a section called by this.*\/\n\t\/*.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;*\/\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/*\n  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.\n\n  This library is free software; you can redistribute it and\/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*\/\n\n\/* Linker script to configure memory regions.\n * Need modifying for a specific board.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00002000 \/*Put here if necesary bootloader start addressing*\/\n  RAM (rwx) : ORIGIN = 0x00010000, LENGTH = 0x00001000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t\/** TODO: maybe this is necesary if there is a section called by this.*\/\n\t\/*.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;*\/\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"48060c3b86556ea2b6d41b1796b020974e2363fc","subject":"[fix] Ignore sha2.lua in doc generation (#6229)","message":"[fix] Ignore sha2.lua in doc generation (#6229)\n\nOtherwise it'll choke on the comments in that file.\r\n\r\nSee <https:\/\/github.com\/koreader\/koreader\/pull\/6195#issuecomment-638801075>.\r\n\r\nAccidentally introduced in <https:\/\/github.com\/koreader\/koreader-base\/pull\/1105>.","repos":"poire-z\/koreader,koreader\/koreader,Markismus\/koreader,NiLuJe\/koreader,Frenzie\/koreader,pazos\/koreader,Frenzie\/koreader,koreader\/koreader,NiLuJe\/koreader,mwoz123\/koreader,poire-z\/koreader,Hzj-jie\/koreader","old_file":"doc\/config.ld","new_file":"doc\/config.ld","new_contents":"project = 'KOReader'\ndescription = 'Multi-platform ebook reader'\nfull_description = 'An ebook reader application supports PDF, DJVU, EPUB, FB2 and many more formats, running on Kindle, Kobo, PocketBook, Ubuntu Touch and Android devices.'\ntitle = 'KOReader Documentation'\ndir = 'html'\nstyle = '!fixed'\nuse_markdown_titles = true\ntopics = {\n    '..\/README.md',\n    '.\/Collaborating_with_Git.md',\n    '.\/DataStore.md',\n    '.\/Development_guide.md',\n    '.\/Events.md',\n    '.\/Hacking.md',\n    '.\/Porting.md',\n    '.\/Unit_tests.md',\n}\npackage = ''\nformat = 'markdown'\nsort_modules = true\nfile = {\n    '..\/frontend',\n    '..\/base\/ffi',\n    '..\/platform\/android\/luajit-launcher\/assets',\n    exclude = {'..\/base\/ffi\/sha2.lua'},\n}\n","old_contents":"project = 'KOReader'\ndescription = 'Multi-platform ebook reader'\nfull_description = 'An ebook reader application supports PDF, DJVU, EPUB, FB2 and many more formats, running on Kindle, Kobo, PocketBook, Ubuntu Touch and Android devices.'\ntitle = 'KOReader Documentation'\ndir = 'html'\nstyle = '!fixed'\nuse_markdown_titles = true\ntopics = {\n    '..\/README.md',\n    '.\/Collaborating_with_Git.md',\n    '.\/DataStore.md',\n    '.\/Development_guide.md',\n    '.\/Events.md',\n    '.\/Hacking.md',\n    '.\/Porting.md',\n    '.\/Unit_tests.md',\n}\npackage = ''\nformat = 'markdown'\nsort_modules = true\nfile = {\n    '..\/frontend',\n    '..\/base\/ffi',\n    '..\/platform\/android\/luajit-launcher\/assets',\n}\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"2be6594d3f96ca697d8a8555e356971da1f8af53","subject":"usb: bos: Add linker sections for USB BOS descriptor","message":"usb: bos: Add linker sections for USB BOS descriptor\n\nSince USB Binary Device Object Store (BOS) descriptor might be defined\nin several places create usb_bos_desc section.\n\nSigned-off-by: Andrei Emeltchenko <a6565233ddc88e4fb9c66c1d70743223493f2ed4@intel.com>\n","repos":"kraj\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,explora26\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,finikorg\/zephyr,nashif\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,ldts\/zephyr,ldts\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,Vudentz\/zephyr,explora26\/zephyr,finikorg\/zephyr,finikorg\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,kraj\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,ldts\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,explora26\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr","old_file":"include\/linker\/common-ram.ld","new_file":"include\/linker\/common-ram.ld","new_contents":"\tSECTION_DATA_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_DATA_PROLOGUE(initlevel_error, (OPTIONAL), )\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\tSECTION_DATA_PROLOGUE(initshell, (OPTIONAL),)\n\t{\n\t\tSHELL_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_static_thread_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_static_thread_data_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._static_thread_data.static.*\")))\n\t\t_static_thread_data_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_DATA_PROLOGUE(_k_timer_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_timer_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_timer.static.*\")))\n\t\t_k_timer_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_slab_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mem_slab_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_slab.static.*\")))\n\t\t_k_mem_slab_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\t\t_k_mem_pool_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_pool.static.*\")))\n\t\t_k_mem_pool_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_sem_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_sem_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_sem.static.*\")))\n\t\t_k_sem_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mutex_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mutex_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mutex.static.*\")))\n\t\t_k_mutex_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_alert_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_alert_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_alert.static.*\")))\n\t\t_k_alert_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_queue_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_queue_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_queue.static.*\")))\n\t\t_k_queue_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_stack_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_stack_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_stack.static.*\")))\n\t\t_k_stack_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_msgq_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_msgq_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_msgq.static.*\")))\n\t\t_k_msgq_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mbox_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mbox_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mbox.static.*\")))\n\t\t_k_mbox_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_pipe_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_pipe_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe.static.*\")))\n\t\t_k_pipe_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_work_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_work_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_work.static.*\")))\n\t\t_k_work_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_task_list, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_task_list_start = .;\n\t\t*(._k_task_list.public.*)\n\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_event_list, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_event_list_start = .;\n\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_memory_pool, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t*(._k_memory_pool.struct*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\n\t\t_k_mem_pool_start = .;\n\t\t*(._k_memory_pool.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool*\")))\n\t\t_k_mem_pool_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_start = .;\n\t\t*(\".net_if.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if.*\")))\n\t\t__net_if_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if_dev, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_dev_start = .;\n\t\t*(\".net_if_dev.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if_dev.*\")))\n\t\t__net_if_dev_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SHELL)\n\tSECTION_DATA_PROLOGUE(net_stack, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_stack_start = .;\n\t\t*(\".net_stack.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_stack*\")))\n\t\t__net_stack_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_NET_SHELL *\/\n\n\tSECTION_DATA_PROLOGUE(net_l2_data, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_l2_data_start = .;\n\t\t*(\".net_l2.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.data*\")))\n\t\t__net_l2_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(usb_data, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_data_start = .;\n\t\t*(\".usb.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.data*\")))\n\t\t__usb_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#if defined(CONFIG_USB_DEVICE_BOS)\n\tSECTION_DATA_PROLOGUE(usb_bos_desc, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_bos_desc_start = .;\n\t\t*(\".usb.bos_desc\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.bos_desc*\")))\n\t\t__usb_bos_desc_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_BOS *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n","old_contents":"\tSECTION_DATA_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_DATA_PROLOGUE(initlevel_error, (OPTIONAL), )\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\tSECTION_DATA_PROLOGUE(initshell, (OPTIONAL),)\n\t{\n\t\tSHELL_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_static_thread_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_static_thread_data_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._static_thread_data.static.*\")))\n\t\t_static_thread_data_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_DATA_PROLOGUE(_k_timer_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_timer_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_timer.static.*\")))\n\t\t_k_timer_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_slab_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mem_slab_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_slab.static.*\")))\n\t\t_k_mem_slab_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\t\t_k_mem_pool_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_pool.static.*\")))\n\t\t_k_mem_pool_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_sem_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_sem_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_sem.static.*\")))\n\t\t_k_sem_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mutex_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mutex_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mutex.static.*\")))\n\t\t_k_mutex_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_alert_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_alert_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_alert.static.*\")))\n\t\t_k_alert_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_queue_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_queue_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_queue.static.*\")))\n\t\t_k_queue_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_stack_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_stack_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_stack.static.*\")))\n\t\t_k_stack_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_msgq_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_msgq_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_msgq.static.*\")))\n\t\t_k_msgq_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mbox_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mbox_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mbox.static.*\")))\n\t\t_k_mbox_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_pipe_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_pipe_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe.static.*\")))\n\t\t_k_pipe_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_work_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_work_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_work.static.*\")))\n\t\t_k_work_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_task_list, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_task_list_start = .;\n\t\t*(._k_task_list.public.*)\n\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_event_list, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_event_list_start = .;\n\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_memory_pool, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t*(._k_memory_pool.struct*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\n\t\t_k_mem_pool_start = .;\n\t\t*(._k_memory_pool.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool*\")))\n\t\t_k_mem_pool_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_start = .;\n\t\t*(\".net_if.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if.*\")))\n\t\t__net_if_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if_dev, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_dev_start = .;\n\t\t*(\".net_if_dev.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if_dev.*\")))\n\t\t__net_if_dev_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SHELL)\n\tSECTION_DATA_PROLOGUE(net_stack, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_stack_start = .;\n\t\t*(\".net_stack.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_stack*\")))\n\t\t__net_stack_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_NET_SHELL *\/\n\n\tSECTION_DATA_PROLOGUE(net_l2_data, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_l2_data_start = .;\n\t\t*(\".net_l2.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.data*\")))\n\t\t__net_l2_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(usb_data, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_data_start = .;\n\t\t*(\".usb.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.data*\")))\n\t\t__usb_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8656d00af15c00602697aa8edc47cb8789be72d2","subject":"Updated linker script to move flash after config section","message":"Updated linker script to move flash after config section\n","repos":"bharrisau\/cmsis-freescale","old_file":"MKL25Z\/Source\/GCC\/MKL25Z64.ld","new_file":"MKL25Z\/Source\/GCC\/MKL25Z64.ld","new_contents":"\/* Linker script to configure memory regions. *\/\r\nMEMORY\r\n{\r\n  VECT (r)       : ORIGIN = 0x00000000, LENGTH = 0xC0  \t\t\t  \/*  Vector area *\/\r\n  FLASH (rx)     : ORIGIN = 0x00000410, LENGTH = 64K - 0x410  \/*  64k *\/\r\n  RAM (rwx)      : ORIGIN = 0x1FFFF800, LENGTH = 8K     \t\t\t\/*   8k *\/\r\n  FCFG (r)       : ORIGIN = 0x00000400, LENGTH = 16     \t\t\t\/*   16 flash configuration *\/\r\n  FIRC (r)       : ORIGIN = 0x000003FC, LENGTH = 4    \t\t\t\t\/*    4 IRC trim *\/\r\n}\r\n\r\n\/* Library configurations *\/\r\nGROUP(libgcc.a libc.a libm.a libnosys.a)\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n\t.vectors : {\r\n\t\tKEEP(*(.isr_vector))\r\n\t} > VECT\r\n\r\n\t.text :\r\n\t{\r\n\t\t*(.text*)\r\n\r\n\t\tKEEP(*(.init))\r\n\t\tKEEP(*(.fini))\r\n\r\n\t\t\/* .ctors *\/\r\n\t\t*crtbegin.o(.ctors)\r\n\t\t*crtbegin?.o(.ctors)\r\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n\t\t*(SORT(.ctors.*))\r\n\t\t*(.ctors)\r\n\r\n\t\t\/* .dtors *\/\r\n \t\t*crtbegin.o(.dtors)\r\n \t\t*crtbegin?.o(.dtors)\r\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n \t\t*(SORT(.dtors.*))\r\n \t\t*(.dtors)\r\n\r\n\t\t*(.rodata*)\r\n\r\n\t\tKEEP(*(.eh_frame*))\r\n\t} > FLASH\r\n\r\n\t.ARM.extab :\r\n\t{\r\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\t} > FLASH\r\n\r\n\t__exidx_start = .;\r\n\t.ARM.exidx :\r\n\t{\r\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\t} > FLASH\r\n\t__exidx_end = .;\r\n\r\n\t__etext = .;\r\n\r\n\t.data : AT (__etext)\r\n\t{\r\n\t\t__data_start__ = .;\r\n\t\t*(vtable)\r\n\t\t*(.data*)\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* preinit data *\/\r\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\r\n\t\tKEEP(*(.preinit_array))\r\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* init data *\/\r\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\r\n\t\tKEEP(*(SORT(.init_array.*)))\r\n\t\tKEEP(*(.init_array))\r\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* finit data *\/\r\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\r\n\t\tKEEP(*(SORT(.fini_array.*)))\r\n\t\tKEEP(*(.fini_array))\r\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n\t\tKEEP(*(.jcr*))\r\n\t\t. = ALIGN(4);\r\n\t\t\/* All data end *\/\r\n\t\t__data_end__ = .;\r\n\r\n\t} > RAM\r\n\r\n\t.bss :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t__bss_start__ = .;\r\n\t\t*(.bss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(4);\r\n\t\t__bss_end__ = .;\r\n\t} > RAM\r\n\r\n\t.heap (COPY):\r\n\t{\r\n\t\t__end__ = .;\r\n\t\tend = __end__;\r\n\t\t*(.heap*)\r\n\t\t__HeapLimit = .;\r\n\t} > RAM\r\n\r\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\r\n\t * used for linker to calculate size of stack sections, and assign\r\n\t * values to stack symbols later *\/\r\n\t.stack_dummy (COPY):\r\n\t{\r\n\t\t*(.stack*)\r\n\t} > RAM\r\n\r\n\t\/* Set stack top to end of RAM, and stack limit move down by\r\n\t * size of stack_dummy section *\/\r\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n\tPROVIDE(__stack = __StackTop);\r\n\r\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\r\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","old_contents":"\/* Linker script to configure memory regions. *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K      \/*  64k *\/\r\n  RAM (rwx)  : ORIGIN = 0x1FFFF800, LENGTH = 8K      \t\/*   8k *\/\r\n}\r\n\r\n\/* Library configurations *\/\r\nGROUP(libgcc.a libc.a libm.a libnosys.a)\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tKEEP(*(.isr_vector))\r\n\t\t*(.text*)\r\n\r\n\t\tKEEP(*(.init))\r\n\t\tKEEP(*(.fini))\r\n\r\n\t\t\/* .ctors *\/\r\n\t\t*crtbegin.o(.ctors)\r\n\t\t*crtbegin?.o(.ctors)\r\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n\t\t*(SORT(.ctors.*))\r\n\t\t*(.ctors)\r\n\r\n\t\t\/* .dtors *\/\r\n \t\t*crtbegin.o(.dtors)\r\n \t\t*crtbegin?.o(.dtors)\r\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n \t\t*(SORT(.dtors.*))\r\n \t\t*(.dtors)\r\n\r\n\t\t*(.rodata*)\r\n\r\n\t\tKEEP(*(.eh_frame*))\r\n\t} > FLASH\r\n\r\n\t.ARM.extab :\r\n\t{\r\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\t} > FLASH\r\n\r\n\t__exidx_start = .;\r\n\t.ARM.exidx :\r\n\t{\r\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\t} > FLASH\r\n\t__exidx_end = .;\r\n\r\n\t__etext = .;\r\n\r\n\t.data : AT (__etext)\r\n\t{\r\n\t\t__data_start__ = .;\r\n\t\t*(vtable)\r\n\t\t*(.data*)\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* preinit data *\/\r\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\r\n\t\tKEEP(*(.preinit_array))\r\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* init data *\/\r\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\r\n\t\tKEEP(*(SORT(.init_array.*)))\r\n\t\tKEEP(*(.init_array))\r\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* finit data *\/\r\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\r\n\t\tKEEP(*(SORT(.fini_array.*)))\r\n\t\tKEEP(*(.fini_array))\r\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n\t\tKEEP(*(.jcr*))\r\n\t\t. = ALIGN(4);\r\n\t\t\/* All data end *\/\r\n\t\t__data_end__ = .;\r\n\r\n\t} > RAM\r\n\r\n\t.bss :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t__bss_start__ = .;\r\n\t\t*(.bss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(4);\r\n\t\t__bss_end__ = .;\r\n\t} > RAM\r\n\r\n\t.heap (COPY):\r\n\t{\r\n\t\t__end__ = .;\r\n\t\tend = __end__;\r\n\t\t*(.heap*)\r\n\t\t__HeapLimit = .;\r\n\t} > RAM\r\n\r\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\r\n\t * used for linker to calculate size of stack sections, and assign\r\n\t * values to stack symbols later *\/\r\n\t.stack_dummy (COPY):\r\n\t{\r\n\t\t*(.stack*)\r\n\t} > RAM\r\n\r\n\t\/* Set stack top to end of RAM, and stack limit move down by\r\n\t * size of stack_dummy section *\/\r\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n\tPROVIDE(__stack = __StackTop);\r\n\r\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\r\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"e2761615e0c86f49819a836d1c06976c90792787","subject":"esp32: Update esp32.custom_common.ld to align with changes in ESP IDF.","message":"esp32: Update esp32.custom_common.ld to align with changes in ESP IDF.\n","repos":"micropython\/micropython-esp32,micropython\/micropython-esp32,Peetz0r\/micropython-esp32,Peetz0r\/micropython-esp32,SHA2017-badge\/micropython-esp32,micropython\/micropython-esp32,Peetz0r\/micropython-esp32,MrSurly\/micropython-esp32,SHA2017-badge\/micropython-esp32,MrSurly\/micropython-esp32,Peetz0r\/micropython-esp32,SHA2017-badge\/micropython-esp32,SHA2017-badge\/micropython-esp32,micropython\/micropython-esp32,micropython\/micropython-esp32,MrSurly\/micropython-esp32,MrSurly\/micropython-esp32,Peetz0r\/micropython-esp32,MrSurly\/micropython-esp32,SHA2017-badge\/micropython-esp32","old_file":"esp32\/esp32.custom_common.ld","new_file":"esp32\/esp32.custom_common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *esp32\/panic.o(.literal .text .literal.* .text.*)\n    *esp32\/core_dump.o(.literal .text .literal.* .text.*)\n    *esp32\/heap_alloc_caps.o(.literal .text .literal.* .text.*)\n    *esp32\/app_trace.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *spi_flash\/spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    *py\/scheduler.o*(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *esp32\/panic.o(.rodata .rodata.*)\n    *esp32\/app_trace.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *esp32\/panic.o(.literal .text .literal.* .text.*)\n    *esp32\/core_dump.o(.literal .text .literal.* .text.*)\n    *esp32\/heap_alloc_caps.o(.literal .text .literal.* .text.*)\n    *esp32\/app_trace.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libcore.a:ets_timer.o(.literal .text .literal.* .text.*)\n    *libnet80211.a:ieee80211_misc.o(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libcoexist.a:(.literal .text .literal.* .text.*)\n    *spi_flash\/spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    *py\/scheduler.o*(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *esp32\/panic.o(.rodata .rodata.*)\n    *esp32\/app_trace.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3f4831f32858fa45c6d212ce8b8282dcecf9631e","subject":"Reduce alignment of DMA pool and shared memory to 4K.","message":"Reduce alignment of DMA pool and shared memory to 4K.\n\nThis commit reduces the alignment constraints of both the DMA pool and shared\nmemory regions from 16MB to 4KB. It was overly conservative to align them to\n16MB, when we back both regions with 4K frames.\n\nCloses JIRA CAMKES-363\n","repos":"smaccm\/camkes-tool,smaccm\/camkes-tool,agacek\/camkes-tool,smaccm\/camkes-tool,agacek\/camkes-tool,smaccm\/camkes-tool,agacek\/camkes-tool","old_file":"camkes\/templates\/linker.lds","new_file":"camkes\/templates\/linker.lds","new_contents":"\/*#\n *# Copyright 2014, NICTA\n *#\n *# This software may be distributed and modified according to the terms of\n *# the BSD 2-Clause license. Note that NO WARRANTY is provided.\n *# See \"LICENSE_BSD2.txt\" for details.\n *#\n *# @TAG(NICTA_BSD)\n #*\/\n\n\/* Linker script for CAmkES components. *\/\nENTRY(_start)\n\nSECTIONS {\n    \/* __executable_start is required by libsel4platsupport. *\/\n    PROVIDE (__executable_start = 0x100000);\n    . = 0x100000;\n\n    \/* Code. *\/\n    .text : ALIGN(4096) {\n        *(.text*)\n    }\n\n    \/* Read Only Data. *\/\n    .rodata : ALIGN(4096) {\n        *(.rodata*)\n    }\n\n    \/*- if arch == 'arm' -*\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n    PROVIDE_HIDDEN (__exidx_end = .);\n    \/*- endif -*\/\n\n    \/* Data \/ BSS *\/\n    .data : ALIGN(4096) {\n        *(.data)\n    }\n\n    .bss : {\n        *(.bss)\n        *(COMMON)\n    }\n\n    guarded (NOLOAD) : ALIGN(4096) {\n\t *(guarded)\n    }\n\n    \/*- for c in me.composition.connections -*\/\n    \/*- if c.type.name == 'seL4SharedData' -*\/\n    shared_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000) {\n        *(shared_\/*? c.from_interface.name ?*\/)\n    }\n    shared_\/*? c.to_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000) {\n        *(shared_\/*? c.to_interface.name ?*\/)\n    }\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    persistent (NOLOAD) : ALIGN(0x1000) {\n\t *(persistent)\n    }\n\n    \/*- for c in me.composition.connections -*\/\n    \/*- if c.type.name == 'seL4HardwareMMIO' -*\/\n    \/*- if arch == 'arm' -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x100000) { \/*# ARM Section Size #*\/\n    \/*- else -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x400000) { \/*# IA32 4M Page Size #*\/\n    \/*- endif -*\/\n        *(ignore_\/*? c.from_interface.name ?*\/)\n    }\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    _end = .;\n}\n","old_contents":"\/*#\n *# Copyright 2014, NICTA\n *#\n *# This software may be distributed and modified according to the terms of\n *# the BSD 2-Clause license. Note that NO WARRANTY is provided.\n *# See \"LICENSE_BSD2.txt\" for details.\n *#\n *# @TAG(NICTA_BSD)\n #*\/\n\n\/* Linker script for CAmkES components. *\/\nENTRY(_start)\n\nSECTIONS {\n    \/* __executable_start is required by libsel4platsupport. *\/\n    PROVIDE (__executable_start = 0x100000);\n    . = 0x100000;\n\n    \/* Code. *\/\n    .text : ALIGN(4096) {\n        *(.text*)\n    }\n\n    \/* Read Only Data. *\/\n    .rodata : ALIGN(4096) {\n        *(.rodata*)\n    }\n\n    \/*- if arch == 'arm' -*\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n    PROVIDE_HIDDEN (__exidx_end = .);\n    \/*- endif -*\/\n\n    \/* Data \/ BSS *\/\n    .data : ALIGN(4096) {\n        *(.data)\n    }\n\n    .bss : {\n        *(.bss)\n        *(COMMON)\n    }\n\n    guarded (NOLOAD) : ALIGN(4096) {\n\t *(guarded)\n    }\n\n    \/*- for c in me.composition.connections -*\/\n    \/*- if c.type.name == 'seL4SharedData' -*\/\n    shared_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000000) {\n        *(shared_\/*? c.from_interface.name ?*\/)\n    }\n    shared_\/*? c.to_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000000) {\n        *(shared_\/*? c.to_interface.name ?*\/)\n    }\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    persistent (NOLOAD) : ALIGN(0x1000000) {\n\t *(persistent)\n    }\n\n    \/*- for c in me.composition.connections -*\/\n    \/*- if c.type.name == 'seL4HardwareMMIO' -*\/\n    \/*- if arch == 'arm' -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x100000) { \/*# ARM Section Size #*\/\n    \/*- else -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x400000) { \/*# IA32 4M Page Size #*\/\n    \/*- endif -*\/\n        *(ignore_\/*? c.from_interface.name ?*\/)\n    }\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    _end = .;\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"a2b725d758f98914e367079a77f45524c8c12d09","subject":"Provides symbols _end and _etext in user part linker script","message":"Provides symbols _end and _etext in user part linker script\n","repos":"redbear\/Espruino,redbear\/Espruino,redbear\/Espruino,redbear\/Espruino,redbear\/Espruino,redbear\/Espruino,redbear\/Espruino","old_file":"targetlibs\/duo\/linker_scripts\/gcc\/user.ld","new_file":"targetlibs\/duo\/linker_scripts\/gcc\/user.ld","new_contents":"\r\nSECTIONS\r\n{\r\n    sram_start = ORIGIN(SRAM);\r\n    sram_end = sram_start + LENGTH(SRAM);\r\n\r\n    INCLUDE module_start.ld\r\n    INCLUDE module_info.ld\r\n\r\n    .text :\r\n    {\r\n        expected_dynalib_start = ORIGIN (APP_FLASH) + 24 ;\r\n        link_dynalib_start = .;\r\n        KEEP(*(*.user_part_module))\r\n        link_dynalib_end = . ;\r\n        link_length_start = .;\r\n        KEEP(*(*.user_part_length))\r\n        link_length_end = .;\r\n\r\n        . = ALIGN(4);\r\n\r\n        link_code_location = .;\r\n        KEEP(*(.text.irq ))\r\n        *(.text .text.* .gnu.linkonce.t.*)\r\n        link_code_end = .;\r\n\r\n        . = ALIGN(0x4);\r\n\r\n        link_const_variable_data_location = .;\r\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n        link_const_variable_data_end = .;\r\n\r\n        . = ALIGN(0x4);\r\n\r\n        link_constructors_location = .;\r\n        KEEP(*(.preinit_array))\r\n        KEEP(*(.init_array))\r\n        KEEP (*crtbegin.o(.ctors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n        KEEP (*(SORT(.ctors.*)))\r\n        KEEP (*crtend.o(.ctors))\r\n        link_constructors_end = .;\r\n\r\n        . = ALIGN(0x4);\r\n\r\n        link_destructors_location = .;\r\n        KEEP (*crtbegin.o(.dtors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n        KEEP (*(SORT(.dtors.*)))\r\n        KEEP (*crtend.o(.dtors))\r\n        link_destructors_end = .;\r\n\r\n        . = ALIGN(16);\r\n\t\t_etext = .;\r\n\r\n    }>APP_FLASH  AT> APP_FLASH\r\n\r\n    \/*\r\n     * The .ARM.exidx and .ARM.extab sections are used for C++ exception handling.\r\n     * It is located here for completeness. Bare-metal ARM projects\r\n     * typically cannot afford the overhead associated with C++\r\n     * exceptions handling.\r\n     *\/\r\n    .ARM.exidx :\r\n    {\r\n        __exidx_start = ALIGN(4);\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n        __exidx_end = .;\r\n    } > APP_FLASH  AT> APP_FLASH\r\n\r\n    .ARM.extab :\r\n    {\r\n        __extab_start = ALIGN(4);\r\n        *(.ARM.extab*)\r\n        __extab_end = .;\r\n    } > APP_FLASH  AT> APP_FLASH\r\n\r\n    INCLUDE backup_ram_user.ld\r\n\r\n    .data : \/* Contains the non-zero initialised global variables *\/\r\n    {\r\n        link_global_data_initial_values = LOADADDR( .data ); \/* This is the location in flash of the initial values of global variables *\/\r\n        link_global_data_start = .;\r\n        *(.data*)\r\n        link_global_data_end = .;\r\n        . = ALIGN(., 4);\r\n    }> SRAM AT> APP_FLASH\r\n\r\n    .bss : \/* Zero initialised memory used for zero initialised variables *\/\r\n    {\r\n        link_bss_location = ALIGN(., 4);\r\n        *(.bss*)\r\n        *(COMMON)\r\n        link_bss_end = .;\r\n        link_heap_start = .;\r\n        . = ALIGN(., 4);\r\n\t\t_end = .;\r\n    }> SRAM AT> SRAM\r\n\r\n    INCLUDE module_end.ld\r\n\r\n    \/DISCARD\/ :\r\n    {\r\n        *(.ARM.attributes*)\r\n        *(.comment)\r\n        *(.init)\r\n        *(.preinit)\r\n        *(.fini)\r\n        *(.fini_array)\r\n        *(.ARM.exidx*)\r\n        *(.gnu.linkonce.armexidx.*)\r\n        *(.eh_frame_hdr)\r\n        *(.eh_frame)\r\n        *(.gnu.linkonce.armextab.*)\r\n        *(.v4_bx)\r\n        *(.vfp11_veneer)\r\n        *(.gcc_except_table)\r\n        *(.eh_frame_hdr)\r\n        *(.eh_frame)\r\n        *(.glue*)\r\n    }\r\n\r\n}\r\n\r\nPROVIDE ( end = system_heap_end );\r\n\r\nASSERT ( ORIGIN(SRAM) == system_part1_module_ram_end, \"Origin of SRAM should be at system_part1_module_ram_end\" );\r\n\r\nmin_heap_end = link_heap_start + min_heap_size;\r\nASSERT ( min_heap_end <= system_static_ram_start, \"Insufficient room for heap.\" );\r\n\r\nASSERT ( link_dynalib_start != link_dynalib_end , \"Dynalib table not found\" );\r\n\r\nASSERT ( link_dynalib_start == expected_dynalib_start, \"Dynalib location not correct\" );\r\n\r\n\/* Include this modules static exports for validation *\/\r\nINCLUDE module_user_export.ld\r\n\r\nASSERT ( link_dynalib_start == user_module_table, \"Dynalib location not same as exported location\" );\r\n\r\nASSERT ( USER_FIRMWARE_IMAGE_LOCATION == ORIGIN(APP_FLASH), \"User firmware location and APP_FLASH origin differ\" );\r\n\r\nASSERT ( USER_FIRMWARE_IMAGE_SIZE == LENGTH(APP_FLASH), \"User firmware size and APP_FLASH length differ\" );\r\n\r\nASSERT ( sram_start <= link_heap_start && link_heap_start < sram_end, \"link_heap_start is in the wrong memory space\" );\r\n\r\nASSERT ( link_module_info_start < link_module_info_end, \"module info not linked\" );\r\nASSERT ( link_module_info_suffix_start < link_module_info_suffix_end, \"module info suffix not linked\" );\r\nASSERT ( link_module_info_crc_start < link_module_info_crc_end, \"module info crc not linked\" );\r\n\r\nASSERT ( user_module_info == link_module_info_start, \"module info start not where expected\" );\r\nASSERT ( user_module_info_end == link_module_info_end, \"module info end not where expected\" );\r\n\r\nASSERT ( ORIGIN(SRAM) == system_part1_module_ram_end, \"ORIGIN of user SRAM should equal system_part1_module_ram_end\" );\r\n\r\nuser_sram_end =  ( ORIGIN(SRAM) + LENGTH(SRAM) );\r\nASSERT ( user_sram_end == system_static_ram_start, \"end of user SRAM should be at the start of system sram\" );\r\n\r\nASSERT ( ( link_module_info_suffix_start - link_module_info_static_start ) == 4 || ( link_module_info_suffix_start - link_module_info_static_start ) == 8, \"module info static details not linked\" );\r\n","old_contents":"\r\nSECTIONS\r\n{\r\n    sram_start = ORIGIN(SRAM);\r\n    sram_end = sram_start + LENGTH(SRAM);\r\n\r\n    INCLUDE module_start.ld\r\n    INCLUDE module_info.ld\r\n\r\n    .text :\r\n    {\r\n        expected_dynalib_start = ORIGIN (APP_FLASH) + 24 ;\r\n        link_dynalib_start = .;\r\n        KEEP(*(*.user_part_module))\r\n        link_dynalib_end = . ;\r\n        link_length_start = .;\r\n        KEEP(*(*.user_part_length))\r\n        link_length_end = .;\r\n\r\n        . = ALIGN(4);\r\n\r\n        link_code_location = .;\r\n        KEEP(*(.text.irq ))\r\n        *(.text .text.* .gnu.linkonce.t.*)\r\n        link_code_end = .;\r\n\r\n        . = ALIGN(0x4);\r\n\r\n        link_const_variable_data_location = .;\r\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n        link_const_variable_data_end = .;\r\n\r\n        . = ALIGN(0x4);\r\n\r\n        link_constructors_location = .;\r\n        KEEP(*(.preinit_array))\r\n        KEEP(*(.init_array))\r\n        KEEP (*crtbegin.o(.ctors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n        KEEP (*(SORT(.ctors.*)))\r\n        KEEP (*crtend.o(.ctors))\r\n        link_constructors_end = .;\r\n\r\n        . = ALIGN(0x4);\r\n\r\n        link_destructors_location = .;\r\n        KEEP (*crtbegin.o(.dtors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n        KEEP (*(SORT(.dtors.*)))\r\n        KEEP (*crtend.o(.dtors))\r\n        link_destructors_end = .;\r\n\r\n        . = ALIGN(16);\r\n\r\n    }>APP_FLASH  AT> APP_FLASH\r\n\r\n    \/*\r\n     * The .ARM.exidx and .ARM.extab sections are used for C++ exception handling.\r\n     * It is located here for completeness. Bare-metal ARM projects\r\n     * typically cannot afford the overhead associated with C++\r\n     * exceptions handling.\r\n     *\/\r\n    .ARM.exidx :\r\n    {\r\n        __exidx_start = ALIGN(4);\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n        __exidx_end = .;\r\n    } > APP_FLASH  AT> APP_FLASH\r\n\r\n    .ARM.extab :\r\n    {\r\n        __extab_start = ALIGN(4);\r\n        *(.ARM.extab*)\r\n        __extab_end = .;\r\n    } > APP_FLASH  AT> APP_FLASH\r\n\r\n    INCLUDE backup_ram_user.ld\r\n\r\n    .data : \/* Contains the non-zero initialised global variables *\/\r\n    {\r\n        link_global_data_initial_values = LOADADDR( .data ); \/* This is the location in flash of the initial values of global variables *\/\r\n        link_global_data_start = .;\r\n        *(.data*)\r\n        link_global_data_end = .;\r\n        . = ALIGN(., 4);\r\n    }> SRAM AT> APP_FLASH\r\n\r\n    .bss : \/* Zero initialised memory used for zero initialised variables *\/\r\n    {\r\n        link_bss_location = ALIGN(., 4);\r\n        *(.bss*)\r\n        *(COMMON)\r\n        link_bss_end = .;\r\n        link_heap_start = .;\r\n        . = ALIGN(., 4);\r\n    }> SRAM AT> SRAM\r\n\r\n    INCLUDE module_end.ld\r\n\r\n    \/DISCARD\/ :\r\n    {\r\n        *(.ARM.attributes*)\r\n        *(.comment)\r\n        *(.init)\r\n        *(.preinit)\r\n        *(.fini)\r\n        *(.fini_array)\r\n        *(.ARM.exidx*)\r\n        *(.gnu.linkonce.armexidx.*)\r\n        *(.eh_frame_hdr)\r\n        *(.eh_frame)\r\n        *(.gnu.linkonce.armextab.*)\r\n        *(.v4_bx)\r\n        *(.vfp11_veneer)\r\n        *(.gcc_except_table)\r\n        *(.eh_frame_hdr)\r\n        *(.eh_frame)\r\n        *(.glue*)\r\n    }\r\n\r\n}\r\n\r\nPROVIDE ( end = system_heap_end );\r\n\r\nASSERT ( ORIGIN(SRAM) == system_part1_module_ram_end, \"Origin of SRAM should be at system_part1_module_ram_end\" );\r\n\r\nmin_heap_end = link_heap_start + min_heap_size;\r\nASSERT ( min_heap_end <= system_static_ram_start, \"Insufficient room for heap.\" );\r\n\r\nASSERT ( link_dynalib_start != link_dynalib_end , \"Dynalib table not found\" );\r\n\r\nASSERT ( link_dynalib_start == expected_dynalib_start, \"Dynalib location not correct\" );\r\n\r\n\/* Include this modules static exports for validation *\/\r\nINCLUDE module_user_export.ld\r\n\r\nASSERT ( link_dynalib_start == user_module_table, \"Dynalib location not same as exported location\" );\r\n\r\nASSERT ( USER_FIRMWARE_IMAGE_LOCATION == ORIGIN(APP_FLASH), \"User firmware location and APP_FLASH origin differ\" );\r\n\r\nASSERT ( USER_FIRMWARE_IMAGE_SIZE == LENGTH(APP_FLASH), \"User firmware size and APP_FLASH length differ\" );\r\n\r\nASSERT ( sram_start <= link_heap_start && link_heap_start < sram_end, \"link_heap_start is in the wrong memory space\" );\r\n\r\nASSERT ( link_module_info_start < link_module_info_end, \"module info not linked\" );\r\nASSERT ( link_module_info_suffix_start < link_module_info_suffix_end, \"module info suffix not linked\" );\r\nASSERT ( link_module_info_crc_start < link_module_info_crc_end, \"module info crc not linked\" );\r\n\r\nASSERT ( user_module_info == link_module_info_start, \"module info start not where expected\" );\r\nASSERT ( user_module_info_end == link_module_info_end, \"module info end not where expected\" );\r\n\r\nASSERT ( ORIGIN(SRAM) == system_part1_module_ram_end, \"ORIGIN of user SRAM should equal system_part1_module_ram_end\" );\r\n\r\nuser_sram_end =  ( ORIGIN(SRAM) + LENGTH(SRAM) );\r\nASSERT ( user_sram_end == system_static_ram_start, \"end of user SRAM should be at the start of system sram\" );\r\n\r\nASSERT ( ( link_module_info_suffix_start - link_module_info_static_start ) == 4 || ( link_module_info_suffix_start - link_module_info_static_start ) == 8, \"module info static details not linked\" );\r\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"23cfef5753944b2019f91ebb0951ee1e4a1baec5","subject":"px4-same70xplained-v1:Ensure _ebss will be 4 byte aligned","message":"px4-same70xplained-v1:Ensure _ebss will be 4 byte aligned\n","repos":"mje-nz\/PX4-Firmware,dagar\/Firmware,krbeverx\/Firmware,mcgill-robotics\/Firmware,jlecoeur\/Firmware,Aerotenna\/Firmware,jlecoeur\/Firmware,dagar\/Firmware,mje-nz\/PX4-Firmware,Aerotenna\/Firmware,mcgill-robotics\/Firmware,Aerotenna\/Firmware,PX4\/Firmware,Aerotenna\/Firmware,Aerotenna\/Firmware,PX4\/Firmware,dagar\/Firmware,acfloria\/Firmware,mcgill-robotics\/Firmware,mje-nz\/PX4-Firmware,Aerotenna\/Firmware,PX4\/Firmware,dagar\/Firmware,mje-nz\/PX4-Firmware,jlecoeur\/Firmware,mcgill-robotics\/Firmware,jlecoeur\/Firmware,krbeverx\/Firmware,mcgill-robotics\/Firmware,mje-nz\/PX4-Firmware,dagar\/Firmware,acfloria\/Firmware,jlecoeur\/Firmware,dagar\/Firmware,krbeverx\/Firmware,acfloria\/Firmware,acfloria\/Firmware,mje-nz\/PX4-Firmware,mcgill-robotics\/Firmware,jlecoeur\/Firmware,PX4\/Firmware,PX4\/Firmware,mje-nz\/PX4-Firmware,mcgill-robotics\/Firmware,jlecoeur\/Firmware,acfloria\/Firmware,krbeverx\/Firmware,jlecoeur\/Firmware,acfloria\/Firmware,krbeverx\/Firmware,PX4\/Firmware,Aerotenna\/Firmware,krbeverx\/Firmware,dagar\/Firmware,PX4\/Firmware,krbeverx\/Firmware,acfloria\/Firmware","old_file":"nuttx-configs\/px4-same70xplained-v1\/scripts\/flash-dtcm.ld","new_file":"nuttx-configs\/px4-same70xplained-v1\/scripts\/flash-dtcm.ld","new_contents":"\/****************************************************************************\n * configs\/same70-xplained\/scripts\/flash-dtcm.ld\n *\n *   Copyright (C) 2015 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The SAME70Q21 has 2048Kb of FLASH beginning at address 0x0040:0000 and\n * 384Kb of SRAM beginining at 0x2040:0000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0400:0000 address range (Assuming that ITCM is not enable).\n *\n * NOTE: that the DTCM address of 0x2000:0000 is used for SRAM.  If DTCM is\n * disabled, then the accesses will actually occur on the AHB bus.\n *\/\n\nMEMORY\n{\n\tflash (rx) : ORIGIN = 0x00400000, LENGTH = 2048K\n\tsram (rwx) : ORIGIN = 0x20000000, LENGTH = 384K\n}\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nENTRY(_stext)\n\nSECTIONS\n{\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > flash\n\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\t*(.init_array .init_array.*)\n\t\t_einit = ABSOLUTE(.);\n\t} > flash\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > flash\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > flash\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > sram AT > flash\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > sram\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n}\n","old_contents":"\/****************************************************************************\n * configs\/same70-xplained\/scripts\/flash-dtcm.ld\n *\n *   Copyright (C) 2015 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The SAME70Q21 has 2048Kb of FLASH beginning at address 0x0040:0000 and\n * 384Kb of SRAM beginining at 0x2040:0000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0400:0000 address range (Assuming that ITCM is not enable).\n *\n * NOTE: that the DTCM address of 0x2000:0000 is used for SRAM.  If DTCM is\n * disabled, then the accesses will actually occur on the AHB bus.\n *\/\n\nMEMORY\n{\n\tflash (rx) : ORIGIN = 0x00400000, LENGTH = 2048K\n\tsram (rwx) : ORIGIN = 0x20000000, LENGTH = 384K\n}\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nENTRY(_stext)\n\nSECTIONS\n{\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > flash\n\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\t*(.init_array .init_array.*)\n\t\t_einit = ABSOLUTE(.);\n\t} > flash\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > flash\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > flash\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > sram AT > flash\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t_ebss = ABSOLUTE(.);\n\t} > sram\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"5f059c45528c80c1afebb4b3c15c55e1758fd525","subject":"Fix exported_symbols.lds","message":"Fix exported_symbols.lds\n\nThis was a regression introduced in https:\/\/github.com\/tensorflow\/tensorflow\/commit\/4cc4425aee000b6358fbf219fa3dd64710b7aed4#diff-bcab48f9617a557923ec1df5bd9b840e that was breaking OSX builds of `libtensorflowlite_c.so`.","repos":"frreiss\/tensorflow-fred,ppwwyyxx\/tensorflow,freedomtan\/tensorflow,aam-at\/tensorflow,arborh\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-Corporation\/tensorflow,gautam1858\/tensorflow,annarev\/tensorflow,Intel-tensorflow\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,petewarden\/tensorflow,xzturn\/tensorflow,ppwwyyxx\/tensorflow,freedomtan\/tensorflow,petewarden\/tensorflow,aam-at\/tensorflow,renyi533\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow,yongtang\/tensorflow,gunan\/tensorflow,jhseu\/tensorflow,arborh\/tensorflow,DavidNorman\/tensorflow,adit-chandra\/tensorflow,sarvex\/tensorflow,gautam1858\/tensorflow,sarvex\/tensorflow,yongtang\/tensorflow,gautam1858\/tensorflow,karllessard\/tensorflow,davidzchen\/tensorflow,DavidNorman\/tensorflow,davidzchen\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-experimental_link_static_libraries_once,cxxgtxy\/tensorflow,jhseu\/tensorflow,arborh\/tensorflow,aam-at\/tensorflow,renyi533\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-tensorflow\/tensorflow,gunan\/tensorflow,jhseu\/tensorflow,freedomtan\/tensorflow,frreiss\/tensorflow-fred,petewarden\/tensorflow,Intel-tensorflow\/tensorflow,DavidNorman\/tensorflow,Intel-tensorflow\/tensorflow,annarev\/tensorflow,aam-at\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-experimental_link_static_libraries_once,yongtang\/tensorflow,sarvex\/tensorflow,arborh\/tensorflow,paolodedios\/tensorflow,DavidNorman\/tensorflow,karllessard\/tensorflow,Intel-Corporation\/tensorflow,renyi533\/tensorflow,aam-at\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,jhseu\/tensorflow,DavidNorman\/tensorflow,petewarden\/tensorflow,xzturn\/tensorflow,paolodedios\/tensorflow,freedomtan\/tensorflow,adit-chandra\/tensorflow,cxxgtxy\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,aldian\/tensorflow,jhseu\/tensorflow,tensorflow\/tensorflow,yongtang\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,aldian\/tensorflow,davidzchen\/tensorflow,jhseu\/tensorflow,adit-chandra\/tensorflow,gautam1858\/tensorflow,paolodedios\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,petewarden\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,sarvex\/tensorflow,frreiss\/tensorflow-fred,xzturn\/tensorflow,xzturn\/tensorflow,jhseu\/tensorflow,adit-chandra\/tensorflow,DavidNorman\/tensorflow,Intel-tensorflow\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,aldian\/tensorflow,paolodedios\/tensorflow,annarev\/tensorflow,davidzchen\/tensorflow,petewarden\/tensorflow,Intel-tensorflow\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-Corporation\/tensorflow,arborh\/tensorflow,petewarden\/tensorflow,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,renyi533\/tensorflow,arborh\/tensorflow,frreiss\/tensorflow-fred,gunan\/tensorflow,aldian\/tensorflow,gautam1858\/tensorflow,gautam1858\/tensorflow,sarvex\/tensorflow,gunan\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_saved_model,cxxgtxy\/tensorflow,adit-chandra\/tensorflow,yongtang\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,ppwwyyxx\/tensorflow,annarev\/tensorflow,jhseu\/tensorflow,karllessard\/tensorflow,gunan\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,gautam1858\/tensorflow,davidzchen\/tensorflow,aam-at\/tensorflow,ppwwyyxx\/tensorflow,sarvex\/tensorflow,frreiss\/tensorflow-fred,paolodedios\/tensorflow,Intel-Corporation\/tensorflow,aam-at\/tensorflow,karllessard\/tensorflow,DavidNorman\/tensorflow,DavidNorman\/tensorflow,xzturn\/tensorflow,arborh\/tensorflow,paolodedios\/tensorflow,gunan\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow,jhseu\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,davidzchen\/tensorflow,yongtang\/tensorflow,xzturn\/tensorflow,gautam1858\/tensorflow,davidzchen\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,petewarden\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gunan\/tensorflow,aam-at\/tensorflow,annarev\/tensorflow,annarev\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow,xzturn\/tensorflow,renyi533\/tensorflow,yongtang\/tensorflow,paolodedios\/tensorflow,adit-chandra\/tensorflow,adit-chandra\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,xzturn\/tensorflow,freedomtan\/tensorflow,davidzchen\/tensorflow,yongtang\/tensorflow,arborh\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_tf_optimizer,frreiss\/tensorflow-fred,Intel-Corporation\/tensorflow,annarev\/tensorflow,annarev\/tensorflow,ppwwyyxx\/tensorflow,DavidNorman\/tensorflow,DavidNorman\/tensorflow,gunan\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,gautam1858\/tensorflow,gunan\/tensorflow,cxxgtxy\/tensorflow,arborh\/tensorflow,gunan\/tensorflow,aldian\/tensorflow,tensorflow\/tensorflow,ppwwyyxx\/tensorflow,arborh\/tensorflow,aldian\/tensorflow,ppwwyyxx\/tensorflow,karllessard\/tensorflow,gautam1858\/tensorflow,DavidNorman\/tensorflow,ppwwyyxx\/tensorflow,DavidNorman\/tensorflow,davidzchen\/tensorflow,Intel-Corporation\/tensorflow,frreiss\/tensorflow-fred,gunan\/tensorflow,ppwwyyxx\/tensorflow,davidzchen\/tensorflow,Intel-tensorflow\/tensorflow,petewarden\/tensorflow,freedomtan\/tensorflow,gunan\/tensorflow,ppwwyyxx\/tensorflow,Intel-tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,freedomtan\/tensorflow,aam-at\/tensorflow,adit-chandra\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,yongtang\/tensorflow,yongtang\/tensorflow,karllessard\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,annarev\/tensorflow,tensorflow\/tensorflow,jhseu\/tensorflow,xzturn\/tensorflow,arborh\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow,jhseu\/tensorflow,renyi533\/tensorflow,petewarden\/tensorflow,arborh\/tensorflow,jhseu\/tensorflow,yongtang\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,aam-at\/tensorflow,davidzchen\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow,renyi533\/tensorflow,frreiss\/tensorflow-fred,renyi533\/tensorflow,freedomtan\/tensorflow,paolodedios\/tensorflow,karllessard\/tensorflow,adit-chandra\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,xzturn\/tensorflow,karllessard\/tensorflow,davidzchen\/tensorflow,renyi533\/tensorflow,cxxgtxy\/tensorflow,aldian\/tensorflow,freedomtan\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,adit-chandra\/tensorflow,freedomtan\/tensorflow,xzturn\/tensorflow,adit-chandra\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,freedomtan\/tensorflow,renyi533\/tensorflow,aldian\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,renyi533\/tensorflow,adit-chandra\/tensorflow,renyi533\/tensorflow,petewarden\/tensorflow,xzturn\/tensorflow,sarvex\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer","old_file":"tensorflow\/lite\/experimental\/c\/exported_symbols.lds","new_file":"tensorflow\/lite\/experimental\/c\/exported_symbols.lds","new_contents":"_TfLite*\n","old_contents":"TfLite*\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"107fa71df8f8df35cf49c85765d046b8fc7ba2a9","subject":"riscv32_layout.ld: Correct the RV32 link address","message":"riscv32_layout.ld: Correct the RV32 link address\n\nSigned-off-by: Alistair Francis <52ecf00b70a50079ae8d5fa09b9af6904950b63c@wdc.com>\n","repos":"tock\/libtock-rs","old_file":"riscv32_layout.ld","new_file":"riscv32_layout.ld","new_contents":"\/* Layout for the RISC-V 32 boards, used by the examples in this repository. *\/\n\nMEMORY {\n  \/* The TBF header region is 32 bytes (0x20) *\/\n  FLASH (rx) : ORIGIN = 0x20430020, LENGTH = 32M\n  SRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 512K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 1K;\n\nINCLUDE layout.ld\n","old_contents":"\/* Layout for the RISC-V 32 boards, used by the examples in this repository. *\/\n\nMEMORY {\n  FLASH (rx) : ORIGIN = 0x20430000, LENGTH = 32M\n  SRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 512K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 1K;\n\nINCLUDE layout.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"666a6168eff4abc100f84c3430cb8834e98b5038","subject":"Specify right start address of the flash region","message":"Specify right start address of the flash region\n","repos":"RostakaGmfun\/theCore,forGGe\/theCore,forGGe\/theCore,RostakaGmfun\/theCore,RostakaGmfun\/theCore,forGGe\/theCore,forGGe\/theCore,RostakaGmfun\/theCore","old_file":"platform\/stm32l1xx\/linker\/gnu\/gcc_arm_stm32l1.ld","new_file":"platform\/stm32l1xx\/linker\/gnu\/gcc_arm_stm32l1.ld","new_contents":"\/* Linker script to configure memory regions. *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x80000   \/* 512k *\/\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x14000   \/*  80k *\/\r\n}\r\n\r\n\/* Library configurations *\/\r\nGROUP(libgcc.a libc.a libm.a libnosys.a)\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tKEEP(*(.vectors))\r\n\t\t__Vectors_End = .;\r\n\t\t__Vectors_Size = __Vectors_End - __Vectors;\r\n\t\t__end__ = .;\r\n\r\n\t\t*(.text*)\r\n\r\n\t\tKEEP(*(.init))\r\n\t\tKEEP(*(.fini))\r\n\r\n\t\t\/* .ctors *\/\r\n\t\t*crtbegin.o(.ctors)\r\n\t\t*crtbegin?.o(.ctors)\r\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n\t\t*(SORT(.ctors.*))\r\n\t\t*(.ctors)\r\n\r\n\t\t\/* .dtors *\/\r\n \t\t*crtbegin.o(.dtors)\r\n \t\t*crtbegin?.o(.dtors)\r\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n \t\t*(SORT(.dtors.*))\r\n \t\t*(.dtors)\r\n\r\n\t\t*(.rodata*)\r\n\r\n\t\tKEEP(*(.eh_frame*))\r\n\t} > FLASH\r\n\r\n\t.ARM.extab :\r\n\t{\r\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\t} > FLASH\r\n\r\n\t__exidx_start = .;\r\n\t.ARM.exidx :\r\n\t{\r\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\t} > FLASH\r\n\t__exidx_end = .;\r\n\r\n\t\/* To copy multiple ROM to RAM sections,\r\n\t * uncomment .copy.table section and,\r\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n\t\/*\r\n\t.copy.table :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t__copy_table_start__ = .;\r\n\t\tLONG (__etext)\r\n\t\tLONG (__data_start__)\r\n\t\tLONG (__data_end__ - __data_start__)\r\n\t\tLONG (__etext2)\r\n\t\tLONG (__data2_start__)\r\n\t\tLONG (__data2_end__ - __data2_start__)\r\n\t\t__copy_table_end__ = .;\r\n\t} > FLASH\r\n\t*\/\r\n\r\n\t\/* To clear multiple BSS sections,\r\n\t * uncomment .zero.table section and,\r\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n\t\/*\r\n\t.zero.table :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t__zero_table_start__ = .;\r\n\t\tLONG (__bss_start__)\r\n\t\tLONG (__bss_end__ - __bss_start__)\r\n\t\tLONG (__bss2_start__)\r\n\t\tLONG (__bss2_end__ - __bss2_start__)\r\n\t\t__zero_table_end__ = .;\r\n\t} > FLASH\r\n\t*\/\r\n\r\n\t__etext = .;\r\n\r\n\t.data : AT (__etext)\r\n\t{\r\n\t\t__data_start__ = .;\r\n\t\t*(vtable)\r\n\t\t*(.data*)\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* preinit data *\/\r\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\r\n\t\tKEEP(*(.preinit_array))\r\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* init data *\/\r\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\r\n\t\tKEEP(*(SORT(.init_array.*)))\r\n\t\tKEEP(*(.init_array))\r\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* finit data *\/\r\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\r\n\t\tKEEP(*(SORT(.fini_array.*)))\r\n\t\tKEEP(*(.fini_array))\r\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n\t\tKEEP(*(.jcr*))\r\n\t\t. = ALIGN(4);\r\n\t\t\/* All data end *\/\r\n\t\t__data_end__ = .;\r\n\r\n\t} > RAM\r\n\r\n\t.bss :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t__bss_start__ = .;\r\n\t\t*(.bss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(4);\r\n\t\t__bss_end__ = .;\r\n\t} > RAM\r\n\r\n\t.heap (COPY):\r\n\t{\r\n\t\t__HeapBase = .;\r\n\t\t__end__ = .;\r\n\t\tend = __end__;\r\n\t\tKEEP(*(.heap*))\r\n\t\t__HeapLimit = .;\r\n\t} > RAM\r\n\r\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\r\n\t * used for linker to calculate size of stack sections, and assign\r\n\t * values to stack symbols later *\/\r\n\t.stack_dummy (COPY):\r\n\t{\r\n\t\tKEEP(*(.stack*))\r\n\t} > RAM\r\n\r\n\t\/* Set stack top to end of RAM, and stack limit move down by\r\n\t * size of stack_dummy section *\/\r\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n\tPROVIDE(__stack = __StackTop);\r\n\r\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\r\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","old_contents":"\/* Linker script to configure memory regions. *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000   \/* 512k *\/\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x14000   \/*  80k *\/\r\n}\r\n\r\n\/* Library configurations *\/\r\nGROUP(libgcc.a libc.a libm.a libnosys.a)\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tKEEP(*(.vectors))\r\n\t\t__Vectors_End = .;\r\n\t\t__Vectors_Size = __Vectors_End - __Vectors;\r\n\t\t__end__ = .;\r\n\r\n\t\t*(.text*)\r\n\r\n\t\tKEEP(*(.init))\r\n\t\tKEEP(*(.fini))\r\n\r\n\t\t\/* .ctors *\/\r\n\t\t*crtbegin.o(.ctors)\r\n\t\t*crtbegin?.o(.ctors)\r\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n\t\t*(SORT(.ctors.*))\r\n\t\t*(.ctors)\r\n\r\n\t\t\/* .dtors *\/\r\n \t\t*crtbegin.o(.dtors)\r\n \t\t*crtbegin?.o(.dtors)\r\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n \t\t*(SORT(.dtors.*))\r\n \t\t*(.dtors)\r\n\r\n\t\t*(.rodata*)\r\n\r\n\t\tKEEP(*(.eh_frame*))\r\n\t} > FLASH\r\n\r\n\t.ARM.extab :\r\n\t{\r\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\t} > FLASH\r\n\r\n\t__exidx_start = .;\r\n\t.ARM.exidx :\r\n\t{\r\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\t} > FLASH\r\n\t__exidx_end = .;\r\n\r\n\t\/* To copy multiple ROM to RAM sections,\r\n\t * uncomment .copy.table section and,\r\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n\t\/*\r\n\t.copy.table :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t__copy_table_start__ = .;\r\n\t\tLONG (__etext)\r\n\t\tLONG (__data_start__)\r\n\t\tLONG (__data_end__ - __data_start__)\r\n\t\tLONG (__etext2)\r\n\t\tLONG (__data2_start__)\r\n\t\tLONG (__data2_end__ - __data2_start__)\r\n\t\t__copy_table_end__ = .;\r\n\t} > FLASH\r\n\t*\/\r\n\r\n\t\/* To clear multiple BSS sections,\r\n\t * uncomment .zero.table section and,\r\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n\t\/*\r\n\t.zero.table :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t__zero_table_start__ = .;\r\n\t\tLONG (__bss_start__)\r\n\t\tLONG (__bss_end__ - __bss_start__)\r\n\t\tLONG (__bss2_start__)\r\n\t\tLONG (__bss2_end__ - __bss2_start__)\r\n\t\t__zero_table_end__ = .;\r\n\t} > FLASH\r\n\t*\/\r\n\r\n\t__etext = .;\r\n\r\n\t.data : AT (__etext)\r\n\t{\r\n\t\t__data_start__ = .;\r\n\t\t*(vtable)\r\n\t\t*(.data*)\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* preinit data *\/\r\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\r\n\t\tKEEP(*(.preinit_array))\r\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* init data *\/\r\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\r\n\t\tKEEP(*(SORT(.init_array.*)))\r\n\t\tKEEP(*(.init_array))\r\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t\/* finit data *\/\r\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\r\n\t\tKEEP(*(SORT(.fini_array.*)))\r\n\t\tKEEP(*(.fini_array))\r\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n\t\tKEEP(*(.jcr*))\r\n\t\t. = ALIGN(4);\r\n\t\t\/* All data end *\/\r\n\t\t__data_end__ = .;\r\n\r\n\t} > RAM\r\n\r\n\t.bss :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t__bss_start__ = .;\r\n\t\t*(.bss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(4);\r\n\t\t__bss_end__ = .;\r\n\t} > RAM\r\n\r\n\t.heap (COPY):\r\n\t{\r\n\t\t__HeapBase = .;\r\n\t\t__end__ = .;\r\n\t\tend = __end__;\r\n\t\tKEEP(*(.heap*))\r\n\t\t__HeapLimit = .;\r\n\t} > RAM\r\n\r\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\r\n\t * used for linker to calculate size of stack sections, and assign\r\n\t * values to stack symbols later *\/\r\n\t.stack_dummy (COPY):\r\n\t{\r\n\t\tKEEP(*(.stack*))\r\n\t} > RAM\r\n\r\n\t\/* Set stack top to end of RAM, and stack limit move down by\r\n\t * size of stack_dummy section *\/\r\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n\tPROVIDE(__stack = __StackTop);\r\n\r\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\r\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"6e46c7ad98d8b1be815b69cdf6584ef95865dc1a","subject":"reserved topmost 32 bytes of RAM used by IAP functions","message":"reserved topmost 32 bytes of RAM used by IAP functions\n\nNXP LPC176x\/5x User Manual UM10360 Rev 4.1:\r\n32.3.2.8 RAM used by IAP command handler\r\nFlash programming commands use the top 32 bytes of on-chip RAM. The maximum stack \r\nusage in the user allocated stack space is 128 bytes and it grows downwards.","repos":"svogl\/mbed-os,YarivCol\/mbed-os,arostm\/mbed-os,arostm\/mbed-os,netzimme\/mbed-os,CalSol\/mbed,pradeep-gr\/mbed-os5-onsemi,Archcady\/mbed-os,monkiineko\/mbed-os,mazimkhan\/mbed-os,nRFMesh\/mbed-os,catiedev\/mbed-os,NXPmicro\/mbed,HeadsUpDisplayInc\/mbed,mikaleppanen\/mbed-os,CalSol\/mbed,screamerbg\/mbed,mikaleppanen\/mbed-os,ryankurte\/mbed-os,arostm\/mbed-os,netzimme\/mbed-os,YarivCol\/mbed-os,NXPmicro\/mbed,NXPmicro\/mbed,nRFMesh\/mbed-os,c1728p9\/mbed-os,Archcady\/mbed-os,mmorenobarm\/mbed-os,c1728p9\/mbed-os,CalSol\/mbed,nRFMesh\/mbed-os,YarivCol\/mbed-os,adamgreen\/mbed,Archcady\/mbed-os,kjbracey-arm\/mbed,netzimme\/mbed-os,betzw\/mbed-os,monkiineko\/mbed-os,mazimkhan\/mbed-os,svogl\/mbed-os,ryankurte\/mbed-os,karsev\/mbed-os,karsev\/mbed-os,andcor02\/mbed-os,Archcady\/mbed-os,andcor02\/mbed-os,netzimme\/mbed-os,kl-cruz\/mbed-os,mbedmicro\/mbed,CalSol\/mbed,kl-cruz\/mbed-os,andcor02\/mbed-os,nRFMesh\/mbed-os,adamgreen\/mbed,monkiineko\/mbed-os,ryankurte\/mbed-os,netzimme\/mbed-os,svogl\/mbed-os,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,bcostm\/mbed-os,catiedev\/mbed-os,YarivCol\/mbed-os,mmorenobarm\/mbed-os,mikaleppanen\/mbed-os,betzw\/mbed-os,bcostm\/mbed-os,mazimkhan\/mbed-os,kl-cruz\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,bcostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,kjbracey-arm\/mbed,monkiineko\/mbed-os,mbedmicro\/mbed,arostm\/mbed-os,fahhem\/mbed-os,adamgreen\/mbed,adamgreen\/mbed,c1728p9\/mbed-os,mikaleppanen\/mbed-os,Archcady\/mbed-os,mazimkhan\/mbed-os,mmorenobarm\/mbed-os,kjbracey-arm\/mbed,ryankurte\/mbed-os,monkiineko\/mbed-os,betzw\/mbed-os,infinnovation\/mbed-os,infinnovation\/mbed-os,bcostm\/mbed-os,andcor02\/mbed-os,fahhem\/mbed-os,mbedmicro\/mbed,arostm\/mbed-os,c1728p9\/mbed-os,screamerbg\/mbed,nRFMesh\/mbed-os,Archcady\/mbed-os,mmorenobarm\/mbed-os,svogl\/mbed-os,c1728p9\/mbed-os,CalSol\/mbed,pradeep-gr\/mbed-os5-onsemi,catiedev\/mbed-os,fahhem\/mbed-os,adamgreen\/mbed,HeadsUpDisplayInc\/mbed,infinnovation\/mbed-os,NXPmicro\/mbed,kl-cruz\/mbed-os,ryankurte\/mbed-os,ryankurte\/mbed-os,kl-cruz\/mbed-os,YarivCol\/mbed-os,mikaleppanen\/mbed-os,mbedmicro\/mbed,fahhem\/mbed-os,screamerbg\/mbed,pradeep-gr\/mbed-os5-onsemi,screamerbg\/mbed,bcostm\/mbed-os,karsev\/mbed-os,NXPmicro\/mbed,andcor02\/mbed-os,mikaleppanen\/mbed-os,screamerbg\/mbed,catiedev\/mbed-os,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,screamerbg\/mbed,arostm\/mbed-os,svogl\/mbed-os,HeadsUpDisplayInc\/mbed,pradeep-gr\/mbed-os5-onsemi,catiedev\/mbed-os,mmorenobarm\/mbed-os,catiedev\/mbed-os,YarivCol\/mbed-os,karsev\/mbed-os,betzw\/mbed-os,karsev\/mbed-os,NXPmicro\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,infinnovation\/mbed-os,svogl\/mbed-os,adamgreen\/mbed,infinnovation\/mbed-os,fahhem\/mbed-os,CalSol\/mbed,karsev\/mbed-os,monkiineko\/mbed-os,nRFMesh\/mbed-os,kjbracey-arm\/mbed,mazimkhan\/mbed-os,betzw\/mbed-os,mmorenobarm\/mbed-os,infinnovation\/mbed-os,fahhem\/mbed-os,mazimkhan\/mbed-os,netzimme\/mbed-os,bcostm\/mbed-os,kl-cruz\/mbed-os","old_file":"targets\/TARGET_NXP\/TARGET_LPC176X\/device\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_file":"targets\/TARGET_NXP\/TARGET_LPC176X\/device\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8 - 32)  \/* topmost 32 bytes used by IAP functions *\/\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Code can explicitly ask for data to be \n       placed in these higher RAM banks where\n       they will be left uninitialized. \n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Code can explicitly ask for data to be \n       placed in these higher RAM banks where\n       they will be left uninitialized. \n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"eb2655b622393a0df506a0fd365b5d2595e7aaf4","subject":"cpu\/esp8266\/ld: use folder name instead of archive for module objects","message":"cpu\/esp8266\/ld: use folder name instead of archive for module objects\n","repos":"authmillenon\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,authmillenon\/RIOT,miri64\/RIOT,jasonatran\/RIOT,OTAkeys\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,miri64\/RIOT,kYc0o\/RIOT,miri64\/RIOT,kYc0o\/RIOT,kYc0o\/RIOT,miri64\/RIOT,jasonatran\/RIOT,OTAkeys\/RIOT","old_file":"cpu\/esp8266\/ld\/esp8266.riot-os.ld","new_file":"cpu\/esp8266\/ld\/esp8266.riot-os.ld","new_contents":"\/**\n * This linker script is a combined and modified version of esp8266.ld and\n * esp8266.common.ld from ESP8266-RTOS-SDK.\n *\/\n\nMEMORY\n{\n  dport0_0_seg : org = 0x3FF00000, len = 0x10\n  dram0_0_seg  : org = 0x3FFE8000, len = 0x18000\n  iram1_0_seg  : org = 0x40100000, len = 0xC000\n  irom0_0_seg  : org = 0x40200010 + 0x10000, len = 0x80000 - 0x10 - 0x10000\n  rtc_seg      : org = 0x60001200, len = 0x200\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  \/* RTC memory holds user's data\/rodata *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .rtc.bss :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *(.rtc.bss)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    \/* TODO put only necessary .rodata to dram *\/\n    \/* *(.rodata .rodata.*) *\/\n    *libc.a:*.o(.rodata.* .rodata)\n    *core\/*(.rodata.* .rodata)\n    *cpu\/*(.rodata .rodata.*)\n    *libpp.a:(.rodata.* .rodata)\n    *liblog.a:(.rodata.* .rodata)\n\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  . = 0x3FFFFFF0;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    LONG(_text_start)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)   \/* 0x40100010 *\/\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)     \/* 0x40100020 *\/\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)  \/* 0x40100030 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)    \/* 0x40100050 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)  \/* 0x40100070 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.UserExceptionTrampoline.text)  \/* 0x40100090 *\/\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* normal code should be in irom0 *\/\n    \/*\n    *(.literal .text)\n    *core.a:*(.literal .text .literal.* .text.*)\n    *\/\n    *gdbstub\/*(.literal .text .literal.* .text.*)\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    \/* RIOT-OS compiled source files that use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1 .iram1.*)\n\n    \/* SDK libraries that expect their .text or .data sections to link to iram *\/\n    \/* TODO *libcore.a:(.bss .data .bss.* .data.* COMMON) *\/\n    *esp_idf_spi_flash\/spi_flash_raw.o(.literal .text .literal.* .text.*)\n    *esp_idf_esp8266\/ets_printf.o(.literal .text .literal.* .text.*)\n    \/*\n    *cpu.a:*.o(.literal .text .literal.* .text.*)\n    *\/\n    *core\/sched.o(.literal .text .literal.* .text.*)\n    *esp_wifi\/*(.literal .text .literal.* .text.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *periph\/*(.literal .text .literal.* .text.*)\n    *xtimer\/*(.literal .text .literal.* .text.*)\n\n    *libhal.a:clock.o(.literal .text .literal.* .text.*)\n    *libhal.a:int_asm--set_intclear.o(.literal .text .literal.* .text.*)\n    *libpp.a:esf_buf.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:rate_control.o(.literal .text .literal.* .text.*)\n    *libpp.a:trc.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_chip_v6_cal.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_sleep.o(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa\/*(.literal .text .literal.* .text.*)\n\n    \/* libgcc functions required for debugging have to be in IRAM *\/\n    *libgcc.a:unwind-dw2.o(.literal .text .literal.* .text.*)\n\n    \/* libgcc integer functions also need to be in .text *\/\n    \/* some are called before flash is mapped and also for performance) *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    *libgcc.a:*mulsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*divsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*fixsfsi.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    \/*\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memchr.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n    *\/\n\n    *enc28j60\/*(.literal .text .literal.* .text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    \/* RIOT-OS compiled code and RO data go into IROM by default *\/\n    *(.literal .text .literal.* .text.*)\n    *(.rodata .rodata.*)\n\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n    . = ALIGN(16);\n    __start_ksymatabesp_socket = .;\n    *(ksymatabesp_socket)\n    __stop_ksymatabesp_socket = .;\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","old_contents":"\/**\n * This linker script is a combined and modified version of esp8266.ld and\n * esp8266.common.ld from ESP8266-RTOS-SDK.\n *\/\n\nMEMORY\n{\n  dport0_0_seg : org = 0x3FF00000, len = 0x10\n  dram0_0_seg  : org = 0x3FFE8000, len = 0x18000\n  iram1_0_seg  : org = 0x40100000, len = 0xC000\n  irom0_0_seg  : org = 0x40200010 + 0x10000, len = 0x80000 - 0x10 - 0x10000\n  rtc_seg      : org = 0x60001200, len = 0x200\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  \/* RTC memory holds user's data\/rodata *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .rtc.bss :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *(.rtc.bss)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    \/* TODO put only necessary .rodata to dram *\/\n    \/* *(.rodata .rodata.*) *\/\n    *libc.a:*.o(.rodata.* .rodata)\n    *core.a:*(.rodata.* .rodata)\n    *cpu.a:*(.rodata .rodata.*)\n    *libpp.a:(.rodata.* .rodata)\n    *liblog.a:(.rodata.* .rodata)\n\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  . = 0x3FFFFFF0;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    LONG(_text_start)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)   \/* 0x40100010 *\/\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)     \/* 0x40100020 *\/\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)  \/* 0x40100030 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)    \/* 0x40100050 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)  \/* 0x40100070 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.UserExceptionTrampoline.text)  \/* 0x40100090 *\/\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* normal code should be in irom0 *\/\n    \/*\n    *(.literal .text)\n    *core.a:*(.literal .text .literal.* .text.*)\n    *\/\n    *gdbstub.a:*(.literal .text .literal.* .text.*)\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    \/* RIOT-OS compiled source files that use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1 .iram1.*)\n\n    \/* SDK libraries that expect their .text or .data sections to link to iram *\/\n    \/* TODO *libcore.a:(.bss .data .bss.* .data.* COMMON) *\/\n    *esp_idf_spi_flash.a:spi_flash_raw.o(.literal .text .literal.* .text.*)\n    *esp_idf_esp8266.a:ets_printf.o(.literal .text .literal.* .text.*)\n    \/*\n    *cpu.a:*.o(.literal .text .literal.* .text.*)\n    *\/\n    *core.a:sched.o(.literal .text .literal.* .text.*)\n    *esp_wifi.a:*(.literal .text .literal.* .text.*)\n    *freertos.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *xtimer.a:*(.literal .text .literal.* .text.*)\n\n    *libhal.a:clock.o(.literal .text .literal.* .text.*)\n    *libhal.a:int_asm--set_intclear.o(.literal .text .literal.* .text.*)\n    *libpp.a:esf_buf.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:rate_control.o(.literal .text .literal.* .text.*)\n    *libpp.a:trc.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_chip_v6_cal.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_sleep.o(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n\n    \/* libgcc functions required for debugging have to be in IRAM *\/\n    *libgcc.a:unwind-dw2.o(.literal .text .literal.* .text.*)\n\n    \/* libgcc integer functions also need to be in .text *\/\n    \/* some are called before flash is mapped and also for performance) *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    *libgcc.a:*mulsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*divsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*fixsfsi.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    \/*\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memchr.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n    *\/\n\n    enc28j60.a:*(.literal .text .literal.* .text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    \/* RIOT-OS compiled code and RO data go into IROM by default *\/\n    *(.literal .text .literal.* .text.*)\n    *(.rodata .rodata.*)\n\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n    . = ALIGN(16);\n    __start_ksymatabesp_socket = .;\n    *(ksymatabesp_socket)\n    __stop_ksymatabesp_socket = .;\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"a6e2b41cb9e2253bda231c6eb4dfd72aa273763c","subject":"Fixed: The issue of interrupt vector remapping for GCC_ARM LPC1114","message":"Fixed: The issue of interrupt vector remapping for GCC_ARM LPC1114\n","repos":"Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS","old_file":"TARGET_NXP\/TARGET_LPC11XX\/TOOLCHAIN_GCC_ARM\/LPC1114.ld","new_file":"TARGET_NXP\/TARGET_LPC11XX\/TOOLCHAIN_GCC_ARM\/LPC1114.ld","new_contents":"\/* Linker script for mbed LPC1114 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K\n  RAM (rwx) :  ORIGIN = 0x100000C0, LENGTH = 0x0F40\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n\t\t. = 0x200;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for mbed LPC1114 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K\n  RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 2K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c6a8c99fd629e59d5b2b7db4de14dd7fd3a55b06","subject":"Workaround for ld bug","message":"Workaround for ld bug\n\nApparently, there is a bug in ld that if there is a gap in the address\nspace between .tdata and .tbss, for example due to alignment\nrequirements of .tbss, it will error out with the message \"section\n`.tbss' can't be allocated in segment 1\".  Since .tbss will _probably_\nnot require more alignment than 16, pad out the .tdata section to 16\nbyte alignment to avoid the problem until it can be fixed properly.\n","repos":"ps3dev\/PSL1GHT,ps3dev\/PSL1GHT,ps3dev\/PSL1GHT,ps3dev\/PSL1GHT","old_file":"ppu\/crt\/lv2.ld","new_file":"ppu\/crt\/lv2.ld","new_contents":"OUTPUT_FORMAT(\"elf64-powerpc\", \"elf64-powerpc\", \"elf64-powerpc\")\nOUTPUT_ARCH(powerpc:common64)\n\nENTRY(_start)\n\nPHDRS\n{\n\thdr_text\tPT_LOAD FILEHDR PHDRS\tFLAGS(0x01 | 0x04);\n\thdr_data\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04);\n\thdr_srodata\tPT_LOAD\t\t\t\t\tFLAGS(0x04 | 0x00400000);\n\thdr_sdata\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04 | 0x00200000 | 0x00400000);\n\thdr_rsx\t\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04 | 0x00200000 | 0x00400000 | 0x02000000 | 0x04000000);\n\thdr_tls\t\tPT_TLS\t\t\t\t\tFLAGS(0x04);\n\thdr_param\t0x60000001\t\t\t\tFLAGS(0x00);\n\thdr_prx\t\t0x60000002\t\t\t\tFLAGS(0x00);\n}\n\nSECTIONS\n{\n\tPROVIDE (__executable_start = 0x10000); . = 0x10000 + SIZEOF_HEADERS;\n\t.interp         : { *(.interp) } : hdr_text\n\t.hash           : { *(.hash) }\n\t.dynsym         : { *(.dynsym) }\n\t.dynstr         : { *(.dynstr) }\n\t.gnu.version    : { *(.gnu.version) }\n\t.gnu.version_d  : { *(.gnu.version_d) }\n\t.gnu.version_r  : { *(.gnu.version_r) }\n\t.rel.dyn\t\t:\n\t  {\n\t    *(.rel.init)\n\t    *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n\t    *(.rel.fini)\n\t    *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n\t    *(.rel.data.rel.ro*)\n\t    *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n\t    *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n\t    *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n\t    *(.rel.ctors)\n\t    *(.rel.dtors)\n\t    *(.rel.got)\n\t    *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)\n\t    *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)\n\t    *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)\n\t    *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)\n\t    *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n\t  }\n\n\t.rela.dyn\t\t:\n\t  {\n\t    *(.rela.init)\n\t    *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n\t    *(.rela.fini)\n\t    *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n\t    *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n\t    *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n\t    *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n\t    *(.rela.ctors)\n\t    *(.rela.dtors)\n\t    *(.rela.got)\n\t    *(.rela.toc)\n\t    *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)\n\t    *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)\n\t    *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)\n\t    *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)\n\t    *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n\t  }\n\t.rel.plt        : { *(.rel.plt) }\n\t.rela.plt       : { *(.rela.plt) }\n\t.rela.tocbss    : { *(.rela.tocbss) }\n\t.init           : {\n\t\tKEEP (*(.init))\n\t} = 0x60000000\n\t.text           : {\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\tKEEP (*(.text.*personality*))\n\t\t\/* .gnu.warning sections are handled specially by elf32.em.  *\/\n\t\t*(.gnu.warning)\n\t\t*(.sfpr .glink)\n\t} = 0x60000000\n\t.fini           : {\n\t\tKEEP (*(.fini))\n\t} = 0x60000000\n\t.sceStub.text   : {\n\t\t*(.sceStub.text)\n\t\t*(SORT(.sceStub.text.*))\n\t}\n\tPROVIDE (__etext = .);\n\tPROVIDE (_etext = .);\n\tPROVIDE (etext = .);\n\n\t.eh_frame_hdr : { *(.eh_frame_hdr) }\n\t.eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n\t.gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n\n\t.rodata.sceResident : { KEEP (*(.rodata.sceResident)) }\n\t.rodata.sceFNID     : { KEEP (*(.rodata.sceFNID .rodata.sceFNID.*)) }\n\t.rodata.sceVNID     : { KEEP (*(.rodata.sceVNID .rodata.sceVNID.*)) }\n\t.rodata.sceTNID     : { KEEP (*(.rodata.sceTNID .rodata.sceTNID.*)) }\n\t.rodata.sceVStub    : { KEEP (*(.rodata.sceVStub)) KEEP (*(SORT(.rodata.sceVStub.*))) }\n\n\tPROVIDE (__libentstart = .);\n\t.lib.ent.top : { KEEP (*(.lib.ent.top)) }\n\t.lib.ent\t : { KEEP (*(.lib.ent)) }\n\t.lib.ent.btm : { KEEP (*(.lib.ent.btm)) }\n\tPROVIDE (__libentend = .);\n\n\tPROVIDE (__libstubstart = .);\n\t.lib.stub.top : { KEEP (*(.lib.stub.top)) }\n\t.lib.stub\t  : { KEEP (*(.lib.stub)) }\n\t.lib.stub.btm : { KEEP (*(.lib.stub.btm)) }\n\tPROVIDE (__libstubend = .);\n\n\t.ppu_rodata         : { *(.ppu_rodata .ppu_rodata.*) }\n\t.sys_proc_param     : { KEEP (*(.sys_proc_param)) } : hdr_text : hdr_param\n\t.sys_proc_prx_param : { KEEP (*(.sys_proc_prx_param)) } : hdr_text : hdr_prx\n\n\t. = ALIGN(64K);\n\t\n\t.ppu_data           : { *(.ppu_data .ppu_data.*) } : hdr_data\n\t.sdata2             : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }\n\t.sbss2              : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }\n\n\t\/* Exception handling  *\/\n\t.eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n\t.gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n\t\n\t. = ALIGN(64 \/ 8);\n\t\n\t.preinit_array     : {\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\t}\n\t.init_array     : {\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\t}\n\t.fini_array     : {\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\t}\n\t.ctors          : {\n\t\t\/* gcc uses crtbegin.o to find the start of\n\t\t   the constructors, so we make sure it is\n\t\t   first.  Because this is a wildcard, it\n\t\t   doesn't matter if the user does not\n\t\t   actually link against crtbegin.o; the\n\t\t   linker won't look for a file to match a\n\t\t   wildcard.  The wildcard also means that it\n\t\t   doesn't matter which directory crtbegin.o\n\t\t   is in.  *\/\n\t\tKEEP (*crtbegin.o(.ctors))\n\t\tKEEP (*crtbegin?.o(.ctors))\n\t\t\/* We don't want to include the .ctor section from\n\t\t   the crtend.o file until after the sorted ctors.\n\t\t   The .ctor section from the crtend file contains the\n\t\t   end of ctors marker and it must be last *\/\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t}\n\t.dtors          : {\n\t\tKEEP (*crtbegin.o(.dtors))\n\t\tKEEP (*crtbegin?.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t}\n\t.jcr            : { KEEP (*(.jcr)) }\n\t.data.rel.ro : { *(.data.rel.ro.local*) *(.data.rel.ro*) }\n\t.dynamic        : { *(.dynamic) }\n\n\t.data.sceFStub      : { KEEP (*(.data.sceFStub)) KEEP (*(SORT(.data.sceFStub.*))) }\n\t\n\t.toc1\t\t  : ALIGN(8) { *(.toc1) }\n\t.opd\t\t  : ALIGN(8) { KEEP (*(.opd)) }\n\t.branch_lt\t  : ALIGN(8) { *(.branch_lt) }\n\t.got\t\t  : ALIGN(8) { *(.got .toc) }\n\t.toc.sceStub  : { KEEP (*(.toc.sceStub)) KEEP (*(SORT(.toc.sceStub.*))) }\n\t\n\t\/* Thread Local Storage sections  *\/\n\t.tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*)\n\t\t      . = ALIGN(16);\n\t\t    } : hdr_data : hdr_tls\n\t.tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } : hdr_data : hdr_tls\n\t\n\t. = ALIGN(256M);\n\n\t.rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } : hdr_srodata\n\t.rodata1        : { *(.rodata1) } : hdr_srodata\n\n\t.spu_image\t\t: { *(.spu_image .spu_image.*) } : hdr_srodata\n\t\n\t. = ALIGN(64K);\n\n\t.data           :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tKEEP (*(.gnu.linkonce.d.*personality*))\n\t\tSORT(CONSTRUCTORS)\n\t} : hdr_sdata\n\t.data1          : { *(.data1) }\n\n  \/* We want the small data sections together, so single-instruction offsets\n     can access them all, and initialized data all before uninitialized, so\n     we can shorten the on-disk segment size.  *\/\n\t.sdata          : {\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t}\n\t_edata = .;\n\tPROVIDE (edata = .);\n\n\t__bss_start = .;\n\t.tocbss\t  : ALIGN(8) { *(.tocbss)}\n\t.sbss           :\n\t{\n\t\tPROVIDE (__sbss_start = .);\n\t\tPROVIDE (___sbss_start = .);\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\tPROVIDE (__sbss_end = .);\n\t\tPROVIDE (___sbss_end = .);\n\t}\n\t.plt            : { *(.plt) }\n\t.bss            :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t\/* Align here to ensure that the .bss section occupies space up to\n\t\t   _end.  Align after .bss to ensure correct alignment even if the\n\t\t   .bss section disappears because there are no input sections.\n\t\t   FIXME: Why do we need it? When there is no .bss section, we don't\n\t\t   pad the .data section.  *\/\n\t\t. = ALIGN(64 \/ 8);\n\t}\n\t\n\t. = ALIGN(256M);\n\n\t.rsx_image\t: { *(.rsx_*) } : hdr_rsx\n\t\t\n\t_end = .;\n\t__end = .;\n\tPROVIDE (end = .);\n\t\n\t. = ALIGN(8);\n\t\n\t\/* Stabs debugging sections.  *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment       0 : { *(.comment) }\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0.  *\/\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\n\t.debug_typenames 0 : { *(.debug_typenames) }\n\t.debug_varnames  0 : { *(.debug_varnames) }\n\t\/* DWARF 3 *\/\n\t.debug_pubtypes 0 : { *(.debug_pubtypes) }\n\t.debug_ranges   0 : { *(.debug_ranges) }\n\t.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n\t\/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf64-powerpc\", \"elf64-powerpc\", \"elf64-powerpc\")\nOUTPUT_ARCH(powerpc:common64)\n\nENTRY(_start)\n\nPHDRS\n{\n\thdr_text\tPT_LOAD FILEHDR PHDRS\tFLAGS(0x01 | 0x04);\n\thdr_data\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04);\n\thdr_srodata\tPT_LOAD\t\t\t\t\tFLAGS(0x04 | 0x00400000);\n\thdr_sdata\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04 | 0x00200000 | 0x00400000);\n\thdr_rsx\t\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04 | 0x00200000 | 0x00400000 | 0x02000000 | 0x04000000);\n\thdr_tls\t\tPT_TLS\t\t\t\t\tFLAGS(0x04);\n\thdr_param\t0x60000001\t\t\t\tFLAGS(0x00);\n\thdr_prx\t\t0x60000002\t\t\t\tFLAGS(0x00);\n}\n\nSECTIONS\n{\n\tPROVIDE (__executable_start = 0x10000); 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{"commit":"acc39878ff33307520a3005c7636fc5675b1d459","subject":"soc: riscv: ae350: Remove redundant .vectors sections","message":"soc: riscv: ae350: Remove redundant .vectors sections\n\nThis commit removes doubled .vectors sections in ae350 SoC.\n\nSigned-off-by: Mateusz Sierszulski <31fdbe6085304ea873c2e49eb8a8540c25fbf1c6@antmicro.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/riscv\/riscv-privilege\/andes_v5\/ae350\/linker.ld","new_file":"soc\/riscv\/riscv-privilege\/andes_v5\/ae350\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n * Copyright (c) 2021 Andes Technology Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the ae350 platform\n *\/\n\n#include <soc.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/linker\/devicetree_regions.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n\/* Make linker section alignment comply with PMA granularity. *\/\n#if defined(CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE;\n#else\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_SOC_ANDES_V5_PMA)\n\/*\n * Andes-V5 PMA needs power-of-2 alignment.\n *\/\n#define MPU_MIN_SIZE_ALIGN . = ALIGN(_region_min_align);\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_MIN_SIZE_ALIGN\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    LINKER_DT_REGIONS()\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\t\tKEEP(*(.init.*))\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <zephyr\/linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <zephyr\/linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n    __data_region_start = .;\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n * Copyright (c) 2021 Andes Technology Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the ae350 platform\n *\/\n\n#include <soc.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/linker\/devicetree_regions.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n\/* Make linker section alignment comply with PMA granularity. *\/\n#if defined(CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE;\n#else\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_SOC_ANDES_V5_PMA)\n\/*\n * Andes-V5 PMA needs power-of-2 alignment.\n *\/\n#define MPU_MIN_SIZE_ALIGN . = ALIGN(_region_min_align);\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_MIN_SIZE_ALIGN\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    LINKER_DT_REGIONS()\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t\/* In XIP mode, the .init section must be at the start of ROM *\/\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init.*))\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <zephyr\/linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <zephyr\/linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n    __data_region_start = .;\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1ad21156c4f53debeec69c7a0e1692976ed68844","subject":"linker.ld : provide end point to save memory in memory schedule","message":"linker.ld : provide end point to save memory in memory schedule\n","repos":"IcebergOS\/Cryst,IcebergOS\/frogimine,IcebergOS\/frogimine","old_file":"scripts\/linker.ld","new_file":"scripts\/linker.ld","new_contents":"ENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t\t. = ALIGN(4096);\n\t}\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(4096);\n\t}\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t. = ALIGN(4096);\n\t}\n\t.stab :\n\t{\n\t\t*(.stab)\n\t\t. = ALIGN(4096);\n\t}\n\t.stabstr :\n\t{\n\t\t*(.stabstr)\n\t\t. = ALIGN(4096);\n\t}\n\n\t. = ALIGN(4096);\n\tKERNEL_CODE_END = .;\n\n\t\/DISCARD\/ : { *(.comment) *(.eh_frame) }\n}\n","old_contents":"ENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t\t. = ALIGN(4096);\n\t}\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(4096);\n\t}\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t. = ALIGN(4096);\n\t}\n\t.stab :\n\t{\n\t\t*(.stab)\n\t\t. = ALIGN(4096);\n\t}\n\t.stabstr :\n\t{\n\t\t*(.stabstr)\n\t\t. = ALIGN(4096);\n\t}\n\t\n\t\/DISCARD\/ : { *(.comment) *(.eh_frame) }\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"669a7562cb3488f36550dc43b8db8d312da1f281","subject":"BaseTools\/GccBase.lds: don't copy RELA section to PE\/COFF","message":"BaseTools\/GccBase.lds: don't copy RELA section to PE\/COFF\n\nThe CLANG38 toolchain creates a PIE binary at link time. This is\nnecessary since the LTO code generation may otherwise result in\ncode that cannot execute correctly when loaded above 2 GB.\n\nPIE executables contain a RELA section consisting of dynamic\nrelocation entries that are intended for consumption by the loader\nat runtime. For this reason, it has the SHF_ALLOC attribute set by\ndefault, and will be identified by GenFw as a section that needs to\nbe copied into the PE\/COFF binary, resulting in waste of space since\nthe PE\/COFF loader does not use this data at all.\n\nSo mark the RELA section as informational: this will prevent the\nlinker from setting the SHF_ALLOC attribute, causing GenFw to\nignore it.\n\nDxeCore.efi before:\n\n    Detected 'X64' type PE\/COFF image consisting of 3 sections\n    Section alignment:      0x40\n    File alignment:         0x40\n    Section '.text' @ 0x00000240\n    File offset:            0x240\n    Virtual size:           0x21000\n    Raw size:               0x21000\n    Section '.data' @ 0x00021240\n    File offset:            0x21240\n    Virtual size:           0x3640\n    Raw size:               0x3640\n    Section '.reloc' @ 0x00024880\n    File offset:            0x24880\n    Virtual size:           0x280\n    Raw size:               0x280\n\nDxeCore.efi after:\n\n    Detected 'X64' type PE\/COFF image consisting of 3 sections\n    Section alignment:      0x40\n    File alignment:         0x40\n    Section '.text' @ 0x00000240\n    File offset:            0x240\n    Virtual size:           0x1f440\n    Raw size:               0x1f440\n    Section '.data' @ 0x0001f680\n    File offset:            0x1f680\n    Virtual size:           0x3640\n    Raw size:               0x3640\n    Section '.reloc' @ 0x00022cc0\n    File offset:            0x22cc0\n    Virtual size:           0x280\n    Raw size:               0x280\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org>\nReviewed-by: Liming Gao <6480311aeeb4b006862f6d13ebabddc03f51e507@intel.com>\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"BaseTools\/Scripts\/GccBase.lds","new_file":"BaseTools\/Scripts\/GccBase.lds","new_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are constant from the POV of the program,\r\n     * but most of its contents end up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     *\/\r\n    *:AutoGen.obj(.data .data.* .bss .bss.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela (INFO) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/*\r\n   * Retain the GNU build id but in a non-allocatable section so GenFw\r\n   * does not copy it into the PE\/COFF image.\r\n   *\/\r\n  .build-id (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","old_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are constant from the POV of the program,\r\n     * but most of its contents end up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     *\/\r\n    *:AutoGen.obj(.data .data.* .bss .bss.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/*\r\n   * Retain the GNU build id but in a non-allocatable section so GenFw\r\n   * does not copy it into the PE\/COFF image.\r\n   *\/\r\n  .build-id (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"cea2d6f9b541f51f1cc55c2d79cbbc5cf50aa6f2","subject":"fernvale.ld: Load at address 0x70000000","message":"fernvale.ld: Load at address 0x70000000\n\nWe're hacking on PSRAM now, so load to iram.\n","repos":"mandl\/fernly,urjaman\/fernly,xobs\/fernly,pfalcon\/fernly,mandl\/fernly,mandl\/fernly,urjaman\/fernly,urjaman\/fernly,pfalcon\/fernly,xobs\/fernly","old_file":"fernvale.ld","new_file":"fernvale.ld","new_contents":"\/************************************************************\n * configs\/c5471evm\/scripts\/ld.script\n *\n *   Copyright (C) 2007, 2011-2012, 2014 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name Gregory Nutt nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ************************************************************\/\n\nOUTPUT_ARCH(arm)\nENTRY(_stext)\nSECTIONS\n{\n\t\/* The OS entry point is here *\/\n\n\t. = 0x70000000; \/* bootloader will copy data to this address *\/\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\tKEEP(*(vectors))\n\t\t*(.text)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\t\t\t\/* Global offset table\t\t*\/\n\t\t_etext = ABSOLUTE(.);\n\t}\n\n\t_eronly = ABSOLUTE(.);\t\t\/* See below                    *\/\n\t. = ALIGN(4096);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t}\n\n\t.bss : {\t\t\t\/* BSS\t\t\t\t*\/\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss)\n\t\t*(COMMON)\n\t\t_ebss = ABSOLUTE(.);\n\t}\n\t\t\t\t\t\/* Stabs debugging sections.\t*\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n}\n","old_contents":"\/************************************************************\n * configs\/c5471evm\/scripts\/ld.script\n *\n *   Copyright (C) 2007, 2011-2012, 2014 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name Gregory Nutt nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ************************************************************\/\n\nOUTPUT_ARCH(arm)\nENTRY(_stext)\nSECTIONS\n{\n\t\/* The OS entry point is here *\/\n\n\t. = 0x00003460; \/* bootloader will copy data to this address *\/\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\tKEEP(*(vectors))\n\t\t*(.text)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\t\t\t\/* Global offset table\t\t*\/\n\t\t_etext = ABSOLUTE(.);\n\t}\n\n\t_eronly = ABSOLUTE(.);\t\t\/* See below                    *\/\n\t. = ALIGN(4096);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t}\n\n\t.bss : {\t\t\t\/* BSS\t\t\t\t*\/\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss)\n\t\t*(COMMON)\n\t\t_ebss = ABSOLUTE(.);\n\t}\n\t\t\t\t\t\/* Stabs debugging sections.\t*\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"4b00458c0af6bff903d4a88be5fd12a91ac92506","subject":"removed unneeded ALIGN directive","message":"removed unneeded ALIGN directive\n","repos":"matildah\/octocabbit","old_file":"src\/kernel.lds","new_file":"src\/kernel.lds","new_contents":"KERNEL_BASE   = 0xf0000000; \/* virtual address *\/\nPHYS_BASE     = 0x80000000; \/* physical address *\/\nKERNEL_OFFSET = KERNEL_BASE - PHYS_BASE;\n\nENTRY(asm_entry)\nSECTIONS\n{\n    . = PHYS_BASE;\n\n    .boot . :\n    {\n        *(.boot.text)\n        *(.boot.rodata)\n        *(.boot.data)\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        . = ALIGN(64K);\n        *(.vectors)\n        *(.vectors.text)\n        *(.text)\n    }\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n        . = ALIGN(8);\n        . = . + 0x1000;\n        svc_stack = .;\n        . = . + 0x1000;\n        usr_stack = .;\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n        *(.ARM.attributes)\n    }\n\n}\n","old_contents":"KERNEL_BASE   = 0xf0000000; \/* virtual address *\/\nPHYS_BASE     = 0x80000000; \/* physical address *\/\nKERNEL_OFFSET = KERNEL_BASE - PHYS_BASE;\n\nENTRY(asm_entry)\nSECTIONS\n{\n    . = PHYS_BASE;\n\n    .boot . :\n    {\n        *(.boot.text)\n        *(.boot.rodata)\n        *(.boot.data)\n        . = ALIGN(64K);\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        . = ALIGN(64K);\n        *(.vectors)\n        *(.vectors.text)\n        *(.text)\n    }\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n        . = ALIGN(8);\n        . = . + 0x1000;\n        svc_stack = .;\n        . = . + 0x1000;\n        usr_stack = .;\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n        *(.ARM.attributes)\n    }\n\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"4bcbadd9d745d122fa67244b01025345023e95ba","subject":"build: Correct symbols in linker script","message":"build: Correct symbols in linker script\n\nThe alignment might otherwise place them wrong\n","repos":"SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl","old_file":"build\/linker.lds","new_file":"build\/linker.lds","new_contents":"OUTPUT_ARCH(mips)\nENTRY(__start)\n\nSECTIONS\n{\n       \t. = 0x1000000;\n       \t.text : ALIGN(4) { *(.init) *(.text) *(.text.*) *(.gnu.linkonce.t.*) }\n       \t. = 0x0;\n       \t.data : ALIGN(16) { *(.data0) *(.data) *(.rodata.str1.4)  *(.rodata.cst4) *(.rodata.cst8) *(.reginfo) }\n       \t.rodata : ALIGN(16) { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) *(.cibylsetjmp) }\n\n\t.ctors : ALIGN(4) {\n\t       PROVIDE(__ctors_begin = .);\n\t       *(.ctors)\n\t       PROVIDE(__ctors_end = .);\n\t}\n\t.dtors : ALIGN(4) {\n\t       PROVIDE(__dtors_begin = .);\n\t       *(.dtors)\n\t       PROVIDE(__dtors_end = .);\n\t}\n       \t.bss : ALIGN(16) {\n\t     *(.bss) *(.scommon) *(.sbss)\n\t     PROVIDE(__edata = .);\n\t}\n\n        \/* Exported symbols (to Java) *\/\n       \t.cibylexpsyms : { *(.cibylexpsyms) }\n\n\t\/* The string table with the exception names *\/\n\t. = 0xfd000000;\n       \t.cibylexceptionstrs : { *(.cibylexceptionstrs) }\n\n\t\/* The string table with the system call names *\/\n\t. = 0xff000000;\n       \t.cibylstrtab : { *(.cibylstrtab) }\n}\n","old_contents":"OUTPUT_ARCH(mips)\nENTRY(__start)\n\nSECTIONS\n{\n       \t. = 0x1000000;\n       \t.text : ALIGN(4) { *(.init) *(.text) *(.text.*) *(.gnu.linkonce.t.*) }\n       \t. = 0x0;\n       \t.data : ALIGN(16) { *(.data0) *(.data) *(.rodata.str1.4)  *(.rodata.cst4) *(.rodata.cst8) *(.reginfo) }\n       \t.rodata : ALIGN(16) { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) *(.cibylsetjmp) }\n\tPROVIDE(__ctors_begin = .);\n\t.ctors : ALIGN(4) { *(.ctors) }\n\tPROVIDE(__ctors_end = .);\n\tPROVIDE(__dtors_begin = .);\n\t.dtors : ALIGN(4) { *(.dtors) }\n\tPROVIDE(__dtors_end = .);\n       \t.bss : ALIGN(16) { *(.bss) *(.scommon) *(.sbss) }\n       \tPROVIDE(__edata = .);\n\n        \/* Exported symbols (to Java) *\/\n       \t.cibylexpsyms : { *(.cibylexpsyms) }\n\n\t\/* The string table with the exception names *\/\n\t. = 0xfd000000;\n       \t.cibylexceptionstrs : { *(.cibylexceptionstrs) }\n\n\t\/* The string table with the system call names *\/\n\t. = 0xff000000;\n       \t.cibylstrtab : { *(.cibylstrtab) }\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"ac74e1746a28b364230072d4dac5a45077326dc2","subject":"Export google_find_phdr in JNI library","message":"Export google_find_phdr in JNI library\n\nThis is necessary in some circumstances when building internally, and is harmless otherwise.\n\nPiperOrigin-RevId: 358372796\nChange-Id: Ib53a5bc1e45acb7fb3fceee91ea25fe7e69283c4\n","repos":"paolodedios\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,petewarden\/tensorflow,Intel-tensorflow\/tensorflow,gautam1858\/tensorflow,yongtang\/tensorflow,sarvex\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,frreiss\/tensorflow-fred,gautam1858\/tensorflow,karllessard\/tensorflow,sarvex\/tensorflow,gautam1858\/tensorflow,frreiss\/tensorflow-fred,Intel-Corporation\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,paolodedios\/tensorflow,annarev\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,karllessard\/tensorflow,frreiss\/tensorflow-fred,gautam1858\/tensorflow,karllessard\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-experimental_link_static_libraries_once,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-Corporation\/tensorflow,karllessard\/tensorflow,karllessard\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow,paolodedios\/tensorflow,annarev\/tensorflow,annarev\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,sarvex\/tensorflow,Intel-Corporation\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,Intel-tensorflow\/tensorflow,gautam1858\/tensorflow,karllessard\/tensorflow,gautam1858\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,annarev\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow,yongtang\/tensorflow,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,paolodedios\/tensorflow,paolodedios\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,yongtang\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,petewarden\/tensorflow,frreiss\/tensorflow-fred,annarev\/tensorflow,Intel-Corporation\/tensorflow,petewarden\/tensorflow,gautam1858\/tensorflow,sarvex\/tensorflow,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-Corporation\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,tensorflow\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,Intel-Corporation\/tensorflow,yongtang\/tensorflow,paolodedios\/tensorflow,yongtang\/tensorflow,Intel-tensorflow\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,frreiss\/tensorflow-fred,frreiss\/tensorflow-fred,Intel-tensorflow\/tensorflow,Intel-Corporation\/tensorflow,annarev\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,frreiss\/tensorflow-fred,petewarden\/tensorflow,yongtang\/tensorflow,petewarden\/tensorflow,petewarden\/tensorflow,paolodedios\/tensorflow,sarvex\/tensorflow,petewarden\/tensorflow,sarvex\/tensorflow,Intel-tensorflow\/tensorflow,Intel-Corporation\/tensorflow,Intel-tensorflow\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,petewarden\/tensorflow,karllessard\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_saved_model,karllessard\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once","old_file":"tensorflow\/lite\/java\/tflite_version_script.lds","new_file":"tensorflow\/lite\/java\/tflite_version_script.lds","new_contents":"VERS_1.0 {\n  # Export JNI and native C symbols.\n  global:\n    Java_*;\n    JNI_OnLoad;\n    JNI_OnUnload;\n    TfLite*;\n\n  # Required for libunwind. This is needed if built and then run internally.\n    google_find_phdr;\n\n  # Hide everything else.\n  local:\n    *;\n};\n","old_contents":"VERS_1.0 {\n  # Export JNI and native C symbols.\n  global:\n    Java_*;\n    JNI_OnLoad;\n    JNI_OnUnload;\n    TfLite*;\n\n  # Hide everything else.\n  local:\n    *;\n};\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4f106c32d581779a6a40e5980d0134b732dedf85","subject":"linker: do not force keep common kernel objects","message":"linker: do not force keep common kernel objects\n\nThis uses the new macros so the common kernel objects can be\ngarbage collected if they are not referred directly anywhere\nin the code. This is useful for reducing library data size\nas not all library functions and their corresponding kobjects\nare being used.\n\nFixes #20663\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr","old_file":"include\/linker\/common-ram.ld","new_file":"include\/linker\/common-ram.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_DATA_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_NAME)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n\/*\n * Space for storing per device init status and busy bitmap in case PM is\n * enabled. Since we do not know beforehand the number of devices,\n * we go through the below mechanism to allocate the required space.\n * Both are made of 1 bit per-device instance, so we compute the size of\n * of an entire bitfield, aligned on 32bits.\n *\/\n#define DEVICE_COUNT \\\n\t((__device_end - __device_start) \/ _DEVICE_STRUCT_SIZEOF)\n#define DEVICE_BITFIELD_SIZE\t(((DEVICE_COUNT + 31) \/ 32) * 4)\n\n#define DEVICE_INIT_STATUS_BITFIELD() \t\t\\\n\t\tFILL(0x00);\t\t\t\\\n\t\t__device_init_status_start = .; \\\n\t\t. = . + DEVICE_BITFIELD_SIZE;\t\\\n\t\t__device_init_status_end = .;\n\n#ifdef CONFIG_DEVICE_POWER_MANAGEMENT\n#define DEVICE_BUSY_BITFIELD()\t\t\t\\\n\t\tFILL(0x00);\t\t\t\\\n\t\t__device_busy_start = .;\t\\\n\t\t. = . + DEVICE_BITFIELD_SIZE;\t\\\n\t\t__device_busy_end = .;\n#else\n#define DEVICE_BUSY_BITFIELD()\n#endif\n\n\tSECTION_DATA_PROLOGUE(devices,,)\n\t{\n\t\t\/* link in devices objects, which are tied to the init ones;\n\t\t * the objects are thus sorted the same way as their init\n\t\t * object parent see include\/device.h\n\t\t *\/\n\t\t__device_start = .;\n\t\tCREATE_OBJ_LEVEL(device, PRE_KERNEL_1)\n\t\tCREATE_OBJ_LEVEL(device, PRE_KERNEL_2)\n\t\tCREATE_OBJ_LEVEL(device, POST_KERNEL)\n\t\tCREATE_OBJ_LEVEL(device, APPLICATION)\n\t\tCREATE_OBJ_LEVEL(device, SMP)\n\t\t__device_end = .;\n\t\tDEVICE_INIT_STATUS_BITFIELD()\n\t\tDEVICE_BUSY_BITFIELD()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(initshell,,)\n\t{\n\t\t\/* link in shell initialization objects for all modules that\n\t\t * use shell and their shell commands are automatically\n\t\t * initialized by the kernel.\n\t\t *\/\n\t\t__shell_module_start = .;\n\t\tKEEP(*(\".shell_module_*\"));\n\t\t__shell_module_end = .;\n\t\t__shell_cmd_start = .;\n\t\tKEEP(*(\".shell_cmd_*\"));\n\t\t__shell_cmd_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_dynamic_sections,,)\n\t{\n\t\t__log_dynamic_start = .;\n\t\tKEEP(*(SORT(.log_dynamic_*)));\n\t\t__log_dynamic_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_timer, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mem_slab, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mem_pool, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_heap, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mutex, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_stack, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_msgq, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mbox, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_pipe, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_sem, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_queue, 4)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area,,SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NETWORKING)\n\tZ_ITERABLE_SECTION_RAM(net_if, 4)\n\tZ_ITERABLE_SECTION_RAM(net_if_dev, 4)\n\tZ_ITERABLE_SECTION_RAM(net_l2, 4)\n#endif \/* NETWORKING *\/\n\n#if defined(CONFIG_UART_MUX)\n\tSECTION_DATA_PROLOGUE(uart_mux,,SUBALIGN(4))\n\t{\n\t\t__uart_mux_start = .;\n\t\t*(\".uart_mux.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".uart_mux.*\")))\n\t\t__uart_mux_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor,,SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(usb_data,,SUBALIGN(1))\n\t{\n\t\t__usb_data_start = .;\n\t\t*(\".usb.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.data*\")))\n\t\t__usb_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#if defined(CONFIG_USB_DEVICE_BOS)\n\tSECTION_DATA_PROLOGUE(usb_bos_desc,,SUBALIGN(1))\n\t{\n\t\t__usb_bos_desc_start = .;\n\t\t*(\".usb.bos_desc\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.bos_desc*\")))\n\t\t__usb_bos_desc_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_BOS *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_DATA_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_NAME)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n\/*\n * Space for storing per device init status and busy bitmap in case PM is\n * enabled. Since we do not know beforehand the number of devices,\n * we go through the below mechanism to allocate the required space.\n * Both are made of 1 bit per-device instance, so we compute the size of\n * of an entire bitfield, aligned on 32bits.\n *\/\n#define DEVICE_COUNT \\\n\t((__device_end - __device_start) \/ _DEVICE_STRUCT_SIZEOF)\n#define DEVICE_BITFIELD_SIZE\t(((DEVICE_COUNT + 31) \/ 32) * 4)\n\n#define DEVICE_INIT_STATUS_BITFIELD() \t\t\\\n\t\tFILL(0x00);\t\t\t\\\n\t\t__device_init_status_start = .; \\\n\t\t. = . + DEVICE_BITFIELD_SIZE;\t\\\n\t\t__device_init_status_end = .;\n\n#ifdef CONFIG_DEVICE_POWER_MANAGEMENT\n#define DEVICE_BUSY_BITFIELD()\t\t\t\\\n\t\tFILL(0x00);\t\t\t\\\n\t\t__device_busy_start = .;\t\\\n\t\t. = . + DEVICE_BITFIELD_SIZE;\t\\\n\t\t__device_busy_end = .;\n#else\n#define DEVICE_BUSY_BITFIELD()\n#endif\n\n\tSECTION_DATA_PROLOGUE(devices,,)\n\t{\n\t\t\/* link in devices objects, which are tied to the init ones;\n\t\t * the objects are thus sorted the same way as their init\n\t\t * object parent see include\/device.h\n\t\t *\/\n\t\t__device_start = .;\n\t\tCREATE_OBJ_LEVEL(device, PRE_KERNEL_1)\n\t\tCREATE_OBJ_LEVEL(device, PRE_KERNEL_2)\n\t\tCREATE_OBJ_LEVEL(device, POST_KERNEL)\n\t\tCREATE_OBJ_LEVEL(device, APPLICATION)\n\t\tCREATE_OBJ_LEVEL(device, SMP)\n\t\t__device_end = .;\n\t\tDEVICE_INIT_STATUS_BITFIELD()\n\t\tDEVICE_BUSY_BITFIELD()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(initshell,,)\n\t{\n\t\t\/* link in shell initialization objects for all modules that\n\t\t * use shell and their shell commands are automatically\n\t\t * initialized by the kernel.\n\t\t *\/\n\t\t__shell_module_start = .;\n\t\tKEEP(*(\".shell_module_*\"));\n\t\t__shell_module_end = .;\n\t\t__shell_cmd_start = .;\n\t\tKEEP(*(\".shell_cmd_*\"));\n\t\t__shell_cmd_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_dynamic_sections,,)\n\t{\n\t\t__log_dynamic_start = .;\n\t\tKEEP(*(SORT(.log_dynamic_*)));\n\t\t__log_dynamic_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tZ_ITERABLE_SECTION_RAM(k_timer, 4)\n\tZ_ITERABLE_SECTION_RAM(k_mem_slab, 4)\n\tZ_ITERABLE_SECTION_RAM(k_mem_pool, 4)\n\tZ_ITERABLE_SECTION_RAM(k_heap, 4)\n\tZ_ITERABLE_SECTION_RAM(k_mutex, 4)\n\tZ_ITERABLE_SECTION_RAM(k_stack, 4)\n\tZ_ITERABLE_SECTION_RAM(k_msgq, 4)\n\tZ_ITERABLE_SECTION_RAM(k_mbox, 4)\n\tZ_ITERABLE_SECTION_RAM(k_pipe, 4)\n\tZ_ITERABLE_SECTION_RAM(k_sem, 4)\n\tZ_ITERABLE_SECTION_RAM(k_queue, 4)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area,,SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NETWORKING)\n\tZ_ITERABLE_SECTION_RAM(net_if, 4)\n\tZ_ITERABLE_SECTION_RAM(net_if_dev, 4)\n\tZ_ITERABLE_SECTION_RAM(net_l2, 4)\n#endif \/* NETWORKING *\/\n\n#if defined(CONFIG_UART_MUX)\n\tSECTION_DATA_PROLOGUE(uart_mux,,SUBALIGN(4))\n\t{\n\t\t__uart_mux_start = .;\n\t\t*(\".uart_mux.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".uart_mux.*\")))\n\t\t__uart_mux_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor,,SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(usb_data,,SUBALIGN(1))\n\t{\n\t\t__usb_data_start = .;\n\t\t*(\".usb.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.data*\")))\n\t\t__usb_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#if defined(CONFIG_USB_DEVICE_BOS)\n\tSECTION_DATA_PROLOGUE(usb_bos_desc,,SUBALIGN(1))\n\t{\n\t\t__usb_bos_desc_start = .;\n\t\t*(\".usb.bos_desc\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.bos_desc*\")))\n\t\t__usb_bos_desc_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_BOS *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"697001cb0ef805021196a491554a91270908dd90","subject":"update copyright","message":"update copyright\n","repos":"hirakuni45\/R8C,hirakuni45\/R8C,hirakuni45\/R8C","old_file":"M120AN\/m120an.ld","new_file":"M120AN\/m120an.ld","new_contents":"\/*======================================================================\/\n\/\t@file\n\/\t@brief    R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script @n\n\/\tFlash-ROM and RAM extends version @n\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes @n\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes\n\/   @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\/   @copyright\tCopyright (C) 2015, 2017 Kunihito Hiramatsu @n\n\/\t\t\t\tReleased under the MIT license @n\n\/\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n\/======================================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x00300, LENGTH = 0x00400\n\tROM (r)  : ORIGIN = 0x08000, LENGTH = 0x07ED8\n\tEXT (r)  : ORIGIN = 0x10000, LENGTH = 0x08000\n\tVVEC (r) : ORIGIN = 0x0FED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0x0FFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x07C0;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  .exttext   :\n  {\n    *(.exttext .stub .exttext.* .gnu.linkonce.t.*)\n    KEEP (*(.exttext.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n  } > EXT =0\n\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    KEEP( *(.vvec) )\n  } > VVEC\n\n  .fvec : {\n    KEEP( *(.fvec) )\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*======================================================================\/\n\/\t@file\n\/\t@brief    R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script @n\n\/\tFlash-ROM and RAM extends version @n\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes @n\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes\n\/   @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\/   @copyright\tCopyright (C) 2015, 2017 Kunihito Hiramatsu @n\n\/\t\t\t\tReleased under the MIT license @n\n\/\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n\/======================================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x00300, LENGTH = 0x00400\n\tROM (r)  : ORIGIN = 0x08000, LENGTH = 0x07FD8\n\tEXT (r)  : ORIGIN = 0x10000, LENGTH = 0x08000\n\tVVEC (r) : ORIGIN = 0x0FED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0x0FFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x07C0;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  .exttext   :\n  {\n    *(.exttext .stub .exttext.* .gnu.linkonce.t.*)\n    KEEP (*(.exttext.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n  } > EXT =0\n\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    KEEP( *(.vvec) )\n  } > VVEC\n\n  .fvec : {\n    KEEP( *(.fvec) )\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"db3f1864a0dd150c4380a464cf7b30237de73f2f","subject":"Increased minimum stack size, because rpl uses it much more.","message":"Increased minimum stack size, because rpl uses it much more.\n","repos":"arurke\/contiki,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr,arurke\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki","old_file":"cpu\/stm32w108\/hal\/micro\/cortexm3\/stm32w108\/gnu.ld","new_file":"cpu\/stm32w108\/hal\/micro\/cortexm3\/stm32w108\/gnu.ld","new_contents":"\/*SEARCH_DIR(\"C:\\Program Files\\Raisonance\\Ride\\Lib\\ARM\")\nEXTERN( __io_putchar )\nEXTERN( _write )\nGROUP(\n\"std_sbrk_thumb.lib\"\n\"smallprintf_thumb.a\"\n\"libc.a\"\n\"libm.a\"\n)\n*\/\n\/* default stack sizes. \n\nThese are used by the startup in order to allocate stacks for the different modes.\n*\/\n\n__Stack_Size = 0x400 ;\n\nPROVIDE ( _Stack_Size = __Stack_Size ) ;\n\n__Stack_Init = _estack  - __Stack_Size ;\n\n\/*\"PROVIDE\" allows to easily override these values from an object file or the commmand line.*\/\nPROVIDE ( _Stack_Init = __Stack_Init ) ;\n\n\/*\nThere will be a link error if there is not this amount of RAM free at the end.\n*\/\n_Minimum_Stack_Size = 0x500 ;\n\n\n\n\/*\nthis sends all unreferenced IRQHandlers to reset\n*\/\n\nPROVIDE(Default_Handler = 0 );\nPROVIDE(NMI_Handler = Default_Handler );\nPROVIDE(HardFault_Handler = Default_Handler );\nPROVIDE(MemManage_Handler = Default_Handler );\nPROVIDE(BusFault_Handler = Default_Handler );\nPROVIDE(UsageFault_Handler = Default_Handler );\nPROVIDE(SVC_Handler = Default_Handler );\nPROVIDE(DebugMonitor_Handler = Default_Handler );\nPROVIDE(PendSV_Handler = Default_Handler );\nPROVIDE(SysTick_Handler = Default_Handler );\nPROVIDE(halTimer1Isr = Default_Handler );\nPROVIDE(halTimer2Isr = Default_Handler );\nPROVIDE(halManagementIsr = Default_Handler );\nPROVIDE(halBaseBandIsr = Default_Handler );\nPROVIDE(halSleepTimerIsr = Default_Handler );\nPROVIDE(halSc1Isr = Default_Handler );\nPROVIDE(halSc2Isr = Default_Handler );\nPROVIDE(halSecurityIsr = Default_Handler );\nPROVIDE(halStackMacTimerIsr = Default_Handler );\nPROVIDE(stmRadioTransmitIsr = Default_Handler );\nPROVIDE(stmRadioReceiveIsr = Default_Handler );\nPROVIDE(halAdcIsr = Default_Handler );\nPROVIDE(halIrqAIsr = Default_Handler );\nPROVIDE(halIrqBIsr = Default_Handler );\nPROVIDE(halIrqCIsr = Default_Handler );\nPROVIDE(halIrqDIsr = Default_Handler );\nPROVIDE(halDebugIsr = Default_Handler );\n\/*PROVIDE(stSerialPrintf = printf );*\/\n\n\/******************************************************************************\/\n\/*                       Peripheral memory map                                *\/\n\/******************************************************************************\/\n\/*this allows to compile the ST lib in \"non-debug\" mode*\/\n\n\n\/* include the memory spaces definitions sub-script *\/\nMEMORY\n{\n  RAM_region (xrw) :            ORIGIN = 0x20000000,            LENGTH = 8K\n  ROM_region (rx) :           ORIGIN = 0x08000000,            LENGTH = 128K-3K\n  NVM_region (rx) :           ORIGIN = 0x0801F400,            LENGTH = 3K\n  FIB_region (ra) :            ORIGIN = 0x08040000,            LENGTH = 2K\n}\n\n\/* higher address of the user mode stack *\/\n_estack = 0x20002000;\n\n\/* Sections management for FLASH mode *\/\n\n\/* Sections Definitions *\/\n\nSECTIONS\n{\n\n    \/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH *\/\n    .isr_vector :\n    {\n\t. = ALIGN(4);\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\t. = ALIGN(4);\n    } >ROM_region\n \n    \/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH *\/\n    .flashtext :\n    {\n\t. = ALIGN(4);\n        *(.flashtext)            \/* Startup code *\/\n\t. = ALIGN(4);\n    } >ROM_region\n \n    \/* the program code is stored in the .text section, which goes to Flash *\/\n    .text :\n    {\n\t    . = ALIGN(4);\n\t    \n        *(.text)                   \/* remaining code *\/\n        *(.text.*)                   \/* remaining code *\/\n        *(.rodata)                 \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n\n\t    . = ALIGN(4);\n   \t _etext = .;\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\n   \t _sidata = _etext;\n    } >ROM_region\n    \n    NVM (NOLOAD):\n    {\n      . = ALIGN(1024);\n      KEEP(*(NVM))\n      . = ALIGN(4);\n    } > NVM_region\n   \n \n    FAT (NOLOAD) :\n    {\n      . = ALIGN(4);\n      KEEP(*(FAT))\n      . = ALIGN(4);\n    } > FIB_region\n\n\/*\n    .FAT (NOLOAD):\n    {\n      KEEP(*(.FAT))\n    } > FIB_region\n*\/\n    \/* after that it's only debugging information. *\/\n    \n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data  : AT ( _sidata )\n    {\n\t    . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n        \n        *(.data)\n        *(.data.*)\n\n\t    . = ALIGN(4);\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\n   \t _edata = . ;\n    } >RAM_region\n    \n    \n\n    \/* This is the uninitialized data section *\/\n    .bss :\n    {\n\t    . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n        \n        *(.bss)\n        *(COMMON)\n        \n\t    . = ALIGN(4);\n\t    \/* This is used by the startup in order to initialize the .bss secion *\/\n   \t _ebss = . ;\n    } >RAM_region\n    \n    PROVIDE ( end = _ebss );\n    PROVIDE ( _end = _ebss );\n    \n    \/* This is the user stack section \n    This is just to check that there is enough RAM left for the User mode stack\n    It should generate an error if it's full.\n     *\/\n    ._usrstack :\n    {\n\t    . = ALIGN(4);\n        _susrstack = . ;\n        \n        . = . + _Minimum_Stack_Size ;\n        \n\t    . = ALIGN(4);\n        _eusrstack = . ;\n    } >RAM_region\n       \n    __exidx_start = .;\n    __exidx_end = .;\n\n    \/* remove the debugging information from the standard libraries *\/\n    \/DISCARD\/ :\n    {\n     libc.a ( * )\n     libm.a ( * )\n     libgcc.a ( * )\n     }\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n       Symbols in the DWARF debugging sections are relative to the beginning\n       of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*SEARCH_DIR(\"C:\\Program Files\\Raisonance\\Ride\\Lib\\ARM\")\nEXTERN( __io_putchar )\nEXTERN( _write )\nGROUP(\n\"std_sbrk_thumb.lib\"\n\"smallprintf_thumb.a\"\n\"libc.a\"\n\"libm.a\"\n)\n*\/\n\/* default stack sizes. \n\nThese are used by the startup in order to allocate stacks for the different modes.\n*\/\n\n__Stack_Size = 0x400 ;\n\nPROVIDE ( _Stack_Size = __Stack_Size ) ;\n\n__Stack_Init = _estack  - __Stack_Size ;\n\n\/*\"PROVIDE\" allows to easily override these values from an object file or the commmand line.*\/\nPROVIDE ( _Stack_Init = __Stack_Init ) ;\n\n\/*\nThere will be a link error if there is not this amount of RAM free at the end.\n*\/\n_Minimum_Stack_Size = 0x400 ;\n\n\n\n\/*\nthis sends all unreferenced IRQHandlers to reset\n*\/\n\nPROVIDE(Default_Handler = 0 );\nPROVIDE(NMI_Handler = Default_Handler );\nPROVIDE(HardFault_Handler = Default_Handler );\nPROVIDE(MemManage_Handler = Default_Handler );\nPROVIDE(BusFault_Handler = Default_Handler );\nPROVIDE(UsageFault_Handler = Default_Handler );\nPROVIDE(SVC_Handler = Default_Handler );\nPROVIDE(DebugMonitor_Handler = Default_Handler );\nPROVIDE(PendSV_Handler = Default_Handler );\nPROVIDE(SysTick_Handler = Default_Handler );\nPROVIDE(halTimer1Isr = Default_Handler );\nPROVIDE(halTimer2Isr = Default_Handler );\nPROVIDE(halManagementIsr = Default_Handler );\nPROVIDE(halBaseBandIsr = Default_Handler );\nPROVIDE(halSleepTimerIsr = Default_Handler );\nPROVIDE(halSc1Isr = Default_Handler );\nPROVIDE(halSc2Isr = Default_Handler );\nPROVIDE(halSecurityIsr = Default_Handler );\nPROVIDE(halStackMacTimerIsr = Default_Handler );\nPROVIDE(stmRadioTransmitIsr = Default_Handler );\nPROVIDE(stmRadioReceiveIsr = Default_Handler );\nPROVIDE(halAdcIsr = Default_Handler );\nPROVIDE(halIrqAIsr = Default_Handler );\nPROVIDE(halIrqBIsr = Default_Handler );\nPROVIDE(halIrqCIsr = Default_Handler );\nPROVIDE(halIrqDIsr = Default_Handler );\nPROVIDE(halDebugIsr = Default_Handler );\n\/*PROVIDE(stSerialPrintf = printf );*\/\n\n\/******************************************************************************\/\n\/*                       Peripheral memory map                                *\/\n\/******************************************************************************\/\n\/*this allows to compile the ST lib in \"non-debug\" mode*\/\n\n\n\/* include the memory spaces definitions sub-script *\/\nMEMORY\n{\n  RAM_region (xrw) :            ORIGIN = 0x20000000,            LENGTH = 8K\n  ROM_region (rx) :           ORIGIN = 0x08000000,            LENGTH = 128K-3K\n  NVM_region (rx) :           ORIGIN = 0x0801F400,            LENGTH = 3K\n  FIB_region (ra) :            ORIGIN = 0x08040000,            LENGTH = 2K\n}\n\n\/* higher address of the user mode stack *\/\n_estack = 0x20002000;\n\n\/* Sections management for FLASH mode *\/\n\n\/* Sections Definitions *\/\n\nSECTIONS\n{\n\n    \/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH *\/\n    .isr_vector :\n    {\n\t. = ALIGN(4);\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\t. = ALIGN(4);\n    } >ROM_region\n \n    \/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH *\/\n    .flashtext :\n    {\n\t. = ALIGN(4);\n        *(.flashtext)            \/* Startup code *\/\n\t. = ALIGN(4);\n    } >ROM_region\n \n    \/* the program code is stored in the .text section, which goes to Flash *\/\n    .text :\n    {\n\t    . = ALIGN(4);\n\t    \n        *(.text)                   \/* remaining code *\/\n        *(.text.*)                   \/* remaining code *\/\n        *(.rodata)                 \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n\n\t    . = ALIGN(4);\n   \t _etext = .;\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\n   \t _sidata = _etext;\n    } >ROM_region\n    \n    NVM (NOLOAD):\n    {\n      . = ALIGN(1024);\n      KEEP(*(NVM))\n      . = ALIGN(4);\n    } > NVM_region\n   \n \n    FAT (NOLOAD) :\n    {\n      . = ALIGN(4);\n      KEEP(*(FAT))\n      . = ALIGN(4);\n    } > FIB_region\n\n\/*\n    .FAT (NOLOAD):\n    {\n      KEEP(*(.FAT))\n    } > FIB_region\n*\/\n    \/* after that it's only debugging information. *\/\n    \n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data  : AT ( _sidata )\n    {\n\t    . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n        \n        *(.data)\n        *(.data.*)\n\n\t    . = ALIGN(4);\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\n   \t _edata = . ;\n    } >RAM_region\n    \n    \n\n    \/* This is the uninitialized data section *\/\n    .bss :\n    {\n\t    . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n        \n        *(.bss)\n        *(COMMON)\n        \n\t    . = ALIGN(4);\n\t    \/* This is used by the startup in order to initialize the .bss secion *\/\n   \t _ebss = . ;\n    } >RAM_region\n    \n    PROVIDE ( end = _ebss );\n    PROVIDE ( _end = _ebss );\n    \n    \/* This is the user stack section \n    This is just to check that there is enough RAM left for the User mode stack\n    It should generate an error if it's full.\n     *\/\n    ._usrstack :\n    {\n\t    . = ALIGN(4);\n        _susrstack = . ;\n        \n        . = . + _Minimum_Stack_Size ;\n        \n\t    . = ALIGN(4);\n        _eusrstack = . ;\n    } >RAM_region\n       \n    __exidx_start = .;\n    __exidx_end = .;\n\n    \/* remove the debugging information from the standard libraries *\/\n    \/DISCARD\/ :\n    {\n     libc.a ( * )\n     libm.a ( * )\n     libgcc.a ( * )\n     }\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n       Symbols in the DWARF debugging sections are relative to the beginning\n       of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"211ffb199273f443eb0f35aeb06be992043cf4ec","subject":"unstaged linking script due to copyright issues","message":"unstaged linking script due to copyright issues\n","repos":"starsheriff\/ST-Nucleo-F303RE,starsheriff\/ST-Nucleo-F303RE","old_file":"first_run\/STM32F303XE_FLASH.ld","new_file":"first_run\/STM32F303XE_FLASH.ld","new_contents":"","old_contents":"\/*\r\n*****************************************************************************\r\n**\r\n**  File        : STM32F303XE_FLASH.ld\r\n**\r\n**  Abstract    : Linker script for STM32F303xE device with\r\n**                512-KByte FLASH, 64-KByte RAM, 16-KByte CCMRAM\r\n**\r\n**                Set heap size, stack size and stack location according\r\n**                to application requirements.\r\n**\r\n**                Set memory bank area and size if external memory is used.\r\n**\r\n**  Target      : STMicroelectronics STM32\r\n**\r\n**  Environment : Atollic TrueSTUDIO(R)\r\n**\r\n**  Distribution: The file is distributed as is, without any warranty\r\n**                of any kind.\r\n**\r\n**  (c)Copyright Atollic AB.\r\n**  You may use this file as-is or modify it according to the needs of your\r\n**  project. This file may only be built (assembled or compiled and linked)\r\n**  using the Atollic TrueSTUDIO(R) product. The use of this file together\r\n**  with other tools than Atollic TrueSTUDIO(R) is not permitted.\r\n**\r\n*****************************************************************************\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\n\/* Highest address of the user mode stack *\/\r\n_estack = 0x20013FFF;    \/* end of RAM *\/\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\nFLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K\r\nRAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 64K\r\nCCMRAM (rw)     : ORIGIN = 0x10000000, LENGTH = 16K\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector)) \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  \/* The program code and other data goes into FLASH *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)           \/* .text sections (code) *\/\r\n    *(.text*)          \/* .text* sections (code) *\/\r\n    *(.glue_7)         \/* glue arm to thumb code *\/\r\n    *(.glue_7t)        \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;        \/* define a global symbols at end of code *\/\r\n  } >FLASH\r\n\r\n  \/* Constant data goes into FLASH *\/\r\n  .rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n  .ARM : {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } >FLASH\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } >FLASH\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } >FLASH\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } >FLASH\r\n\r\n  \/* used by the startup to initialize data *\/\r\n  _sidata = LOADADDR(.data);\r\n\r\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\r\n  .data : \r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .;        \/* create a global symbol at data start *\/\r\n    *(.data)           \/* .data sections *\/\r\n    *(.data*)          \/* .data* sections *\/\r\n\r\n    . = ALIGN(4);\r\n    _edata = .;        \/* define a global symbol at data end *\/\r\n  } >RAM AT> FLASH\r\n\r\n  _siccmram = LOADADDR(.ccmram);\r\n\r\n  \/* CCM-RAM section \r\n  * \r\n  * IMPORTANT NOTE! \r\n  * If initialized variables will be placed in this section, \r\n  * the startup code needs to be modified to copy the init-values.  \r\n  *\/\r\n  .ccmram :\r\n  {\r\n    . = ALIGN(4);\r\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\r\n    *(.ccmram)\r\n    *(.ccmram*)\r\n    \r\n    . = ALIGN(4);\r\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\r\n  } >CCMRAM AT> FLASH\r\n\r\n  \r\n  \/* Uninitialized data section *\/\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n    _sbss = .;         \/* define a global symbol at bss start *\/\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .;         \/* define a global symbol at bss end *\/\r\n    __bss_end__ = _ebss;\r\n  } >RAM\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(4);\r\n  } >RAM\r\n\r\n  \r\n\r\n  \/* Remove information from the standard libraries *\/\r\n  \/DISCARD\/ :\r\n  {\r\n    libc.a ( * )\r\n    libm.a ( * )\r\n    libgcc.a ( * )\r\n  }\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2c517e8bd2acc890f3cb6dedf14f20fb7ce1f1b2","subject":"Update LPC11U68.ld","message":"Update LPC11U68.ld\n","repos":"Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos","old_file":"TARGET_NXP\/TARGET_LPC11U6X\/TOOLCHAIN_GCC_CR\/TARGET_LPC11U68\/LPC11U68.ld","new_file":"TARGET_NXP\/TARGET_LPC11U6X\/TOOLCHAIN_GCC_CR\/TARGET_LPC11U68\/LPC11U68.ld","new_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC11U68\n * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Sat Jun 14 15:26:54 JST 2014\n *\/\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 \/* 32K bytes *\/\n  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 \/* 2K bytes *\/\n  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_32 = 0x10000000+0x100 + 0x8000-0x100;\n  __top_Ram1_2 = 0x20000000 + 0x800;\n  __top_Ram2USB_2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n\t\t*(.text.ResetISR)\n        *(.text.SystemInit)\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \/* possible MTB section for Ram1_2 *\/\n    .mtb_buffer_RAM2 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM2*))\n        KEEP(*(.mtb.$RAM1_2*))\n    } > Ram1_2 \n    \n    \/* DATA section for Ram1_2 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_2)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 AT>MFlash256\n    \/* possible MTB section for Ram2USB_2 *\/\n    .mtb_buffer_RAM3 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM3*))\n        KEEP(*(.mtb.$RAM2USB_2*))\n    } > Ram2USB_2 \n    \n    \/* DATA section for Ram2USB_2 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2USB_2)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/\n    \n    \/* Default MTB section *\/\n    .mtb_buffer_default (NOLOAD) :\n    {\n       KEEP(*(.mtb*))\n    } > Ram0_32 \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_32\n\n\t\n\t\/* Main DATA section (Ram0_32) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_32 AT>MFlash256\n\n    \/* BSS section for Ram1_2 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2\n    \/* BSS section for Ram2USB_2 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_32\n        \n    \/* NOINIT section for Ram1_2 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 \n    \/* NOINIT section for Ram2USB_2 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_32 - 0);\n}\n","old_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC11U68\n * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Sat Jun 14 15:26:54 JST 2014\n *\/\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\/*GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)*\/\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 \/* 32K bytes *\/\n  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 \/* 2K bytes *\/\n  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_32 = 0x10000000+0x100 + 0x8000-0x100;\n  __top_Ram1_2 = 0x20000000 + 0x800;\n  __top_Ram2USB_2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n\t\t*(.text.ResetISR)\n        *(.text.SystemInit)\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \/* possible MTB section for Ram1_2 *\/\n    .mtb_buffer_RAM2 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM2*))\n        KEEP(*(.mtb.$RAM1_2*))\n    } > Ram1_2 \n    \n    \/* DATA section for Ram1_2 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_2)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 AT>MFlash256\n    \/* possible MTB section for Ram2USB_2 *\/\n    .mtb_buffer_RAM3 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM3*))\n        KEEP(*(.mtb.$RAM2USB_2*))\n    } > Ram2USB_2 \n    \n    \/* DATA section for Ram2USB_2 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2USB_2)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/\n    \n    \/* Default MTB section *\/\n    .mtb_buffer_default (NOLOAD) :\n    {\n       KEEP(*(.mtb*))\n    } > Ram0_32 \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_32\n\n\t\n\t\/* Main DATA section (Ram0_32) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_32 AT>MFlash256\n\n    \/* BSS section for Ram1_2 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2\n    \/* BSS section for Ram2USB_2 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_32\n        \n    \/* NOINIT section for Ram1_2 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 \n    \/* NOINIT section for Ram2USB_2 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_32 - 0);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"71d1bd60665240be44ea28499b6b2f40f4e8bf76","subject":"net: Remove unused net sections","message":"net: Remove unused net sections\n\nnet_l2_init sections used to exist in early stage of the native IP stack\nbut got removed since.\n\nChange-Id: I189d6e6f7aa05a6e5a62a28973c714d0367b0c5a\nSigned-off-by: Tomasz Bursztyka <ba81a3a719836727e6857ae83462b9f52ec41006@linux.intel.com>\n","repos":"erwango\/zephyr,finikorg\/zephyr,runchip\/zephyr-cc3200,punitvara\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3200,bboozzoo\/zephyr,rsalveti\/zephyr,galak\/zephyr,erwango\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3200,bboozzoo\/zephyr,fbsder\/zephyr,mbolivar\/zephyr,rsalveti\/zephyr,finikorg\/zephyr,runchip\/zephyr-cc3200,rsalveti\/zephyr,ldts\/zephyr,ldts\/zephyr,runchip\/zephyr-cc3220,bboozzoo\/zephyr,holtmann\/zephyr,fbsder\/zephyr,pklazy\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,ldts\/zephyr,bigdinotech\/zephyr,zephyriot\/zephyr,rsalveti\/zephyr,pklazy\/zephyr,sharronliu\/zephyr,tidyjiang8\/zephyr-doc,galak\/zephyr,explora26\/zephyr,pklazy\/zephyr,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,aceofall\/zephyr-iotos,bigdinotech\/zephyr,bigdinotech\/zephyr,fbsder\/zephyr,tidyjiang8\/zephyr-doc,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,mbolivar\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,runchip\/zephyr-cc3200,bboozzoo\/zephyr,sharronliu\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,explora26\/zephyr,kraj\/zephyr,nashif\/zephyr,fbsder\/zephyr,tidyjiang8\/zephyr-doc,erwango\/zephyr,tidyjiang8\/zephyr-doc,aceofall\/zephyr-iotos,holtmann\/zephyr,erwango\/zephyr,galak\/zephyr,fractalclone\/zephyr-riscv,mbolivar\/zephyr,runchip\/zephyr-cc3220,pklazy\/zephyr,fractalclone\/zephyr-riscv,tidyjiang8\/zephyr-doc,punitvara\/zephyr,sharronliu\/zephyr,explora26\/zephyr,sharronliu\/zephyr,runchip\/zephyr-cc3220,explora26\/zephyr,kraj\/zephyr,nashif\/zephyr,finikorg\/zephyr,mbolivar\/zephyr,Vudentz\/zephyr,aceofall\/zephyr-iotos,explora26\/zephyr,sharronliu\/zephyr,runchip\/zephyr-cc3220,zephyrproject-rtos\/zephyr,rsalveti\/zephyr,holtmann\/zephyr,bigdinotech\/zephyr,runchip\/zephyr-cc3220,erwango\/zephyr,fractalclone\/zephyr-riscv,aceofall\/zephyr-iotos,bboozzoo\/zephyr,holtmann\/zephyr,fbsder\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,galak\/zephyr,ldts\/zephyr,aceofall\/zephyr-iotos,ldts\/zephyr,kraj\/zephyr,pklazy\/zephyr,kraj\/zephyr,fractalclone\/zephyr-riscv,holtmann\/zephyr,bigdinotech\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,mbolivar\/zephyr,Vudentz\/zephyr,zephyriot\/zephyr,fractalclone\/zephyr-riscv,Vudentz\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,punitvara\/zephyr","old_file":"include\/linker\/common-rom.ld","new_file":"include\/linker\/common-rom.ld","new_contents":"#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on 4 byte\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE (devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(net_l2, (OPTIONAL),)\n\t{\n\t\t__net_l2_start = .;\n\t\t*(\".net_l2.init\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.init*\")))\n\t\t__net_l2_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(net_l2_init, (OPTIONAL),)\n\t{\n\t\t__net_l2_start = .;\n\t\t*(\".net_l2.init\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.init*\")))\n\t\t__net_l2_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n","old_contents":"#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on 4 byte\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE (devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(net_l2_init, (OPTIONAL),)\n\t{\n\t\t__net_l2_start = .;\n\t\t*(\".net_l2.init\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.init*\")))\n\t\t__net_l2_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(net_l2, (OPTIONAL),)\n\t{\n\t\t__net_l2_start = .;\n\t\t*(\".net_l2.init\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.init*\")))\n\t\t__net_l2_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c33baa72158cd01c30dde8333510cda0fd205d33","subject":"linker.ld: Fixup load address","message":"linker.ld: Fixup load address\n","repos":"akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix","old_file":"linker.ld","new_file":"linker.ld","new_contents":"\/************************************************************************\n *   Copyright (c) 2012 \u00c1kos Kov\u00e1cs - Akosix operating system\n *              http:\/\/akoskovacs.github.com\/Akosix\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION\n * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n ************************************************************************\/\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    . = 0x00100000;\n    .multiboot_header :\n    {\n    __start_multiboot_header = .;\n        boot\/multiboot.o\n    __end_multiboot_header = .;\n    }\n\n    \/* This stage the paging is still not enabled.\n     * (physical = virtual)\n     *\/\n    .setup :\n    {\n    __start_setup = .;\n        boot\/boot.o\n        boot\/pgsetup.o\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    \/* The following code and data has to be mapped after\n     * the first 3GB address space, giving the kernel 1GB usable\n     * address space.\n     *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf)\n    {\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n        *(.text)\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n\n    .note ALIGN(page_size) : AT(ADDR(.note) - hhalf)\n    {\n        *(.note.gnu.build-id)\n    }\n}\n","old_contents":"\/************************************************************************\n *   Copyright (c) 2012 \u00c1kos Kov\u00e1cs - Akosix operating system\n *              http:\/\/akoskovacs.github.com\/Akosix\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION\n * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n ************************************************************************\/\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    . = 0x00100000;\n    .multiboot_header :\n    {\n    __start_multiboot_header = .;\n        boot\/multiboot.o\n    __end_multiboot_header = .;\n    }\n\n    \/* This stage the paging is still\n     *  not enabled (physical = virtual).\n     *\/\n    . = 0x00100000;\n    .setup :\n    {\n    __start_setup = .;\n        boot\/boot.o\n        boot\/pgsetup.o\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    \/* The following code and data has to be mapped after\n     * the first 3GB address space, giving the kernel 1GB usable\n     * address space.\n     *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf)\n    {\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n        *(.text)\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n\n    .note ALIGN(page_size) : AT(ADDR(.note) - hhalf)\n    {\n        *(.note.gnu.build-id)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a298c890ee33dd6ce97b272bb9435d60a62db422","subject":"arm: linker.ld: move bss section to ram end","message":"arm: linker.ld: move bss section to ram end\n\nfix bss section be copy to binary.\n\nWhen compiling with non-xip.\nAll sections will be placed in the ram.\nIf NOBITS section isn't placed at the end of ram,\nobjcopy will placed these section to binary file.\n\nThe modify only for no-userspace.\nIn userspace the section will be adjust,\nkobject_data size increase,\nthe bss be shifted, the content of kobject_data\nwill no mactch to kernel obj of bss.\n\nSigned-off-by: Frank Li <49244b28ad48c35f973a9a3c4ee9a34d02acfa11@163.com>\n","repos":"nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n#define _DATA_IN_ROM __data_rom_start\n#else\n#define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_HAS_TI_CCFG\n#define CCFG_SIZE 88\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\tCCFG_SIZE)\n#define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_HAS_TI_CCFG\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#if DT_HAS_NODE(DT_CHOSEN(zephyr_ccm))\n    CCM                   (rw) : ORIGIN = DT_REG_ADDR(DT_CHOSEN(zephyr_ccm)), LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_ccm))\n#endif\n#if DT_HAS_NODE(DT_CHOSEN(zephyr_dtcm))\n    DTCM                  (rw) : ORIGIN = DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm)), LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm))\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_HAS_TI_CCFG\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(_TI_CCFG_SECTION_NAME))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_HAS_NODE(DT_CHOSEN(zephyr_dtcm))\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_bss_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_data_end = .;\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n#define _DATA_IN_ROM __data_rom_start\n#else\n#define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_HAS_TI_CCFG\n#define CCFG_SIZE 88\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\tCCFG_SIZE)\n#define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_HAS_TI_CCFG\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#if DT_HAS_NODE(DT_CHOSEN(zephyr_ccm))\n    CCM                   (rw) : ORIGIN = DT_REG_ADDR(DT_CHOSEN(zephyr_ccm)), LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_ccm))\n#endif\n#if DT_HAS_NODE(DT_CHOSEN(zephyr_dtcm))\n    DTCM                  (rw) : ORIGIN = DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm)), LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm))\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_HAS_TI_CCFG\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(_TI_CCFG_SECTION_NAME))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_HAS_NODE(DT_CHOSEN(zephyr_dtcm))\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_bss_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_data_end = .;\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3d19f891a3444d977f25f2f39b849726e2fed899","subject":"soc: intel_s1000: GNA model - linker script entry","message":"soc: intel_s1000: GNA model - linker script entry\n\nAdd a linker script entry for embedding a GNA model at a\n4KB page aligned address in .data section\n\nSigned-off-by: Sathish Kuttan <88b3ab91bbfd8c103d682ea5f9059cf275a3b834@intel.com>\n","repos":"finikorg\/zephyr,Vudentz\/zephyr,explora26\/zephyr,punitvara\/zephyr,nashif\/zephyr,ldts\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,ldts\/zephyr,explora26\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,explora26\/zephyr,nashif\/zephyr,finikorg\/zephyr,punitvara\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,explora26\/zephyr,punitvara\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr","old_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <generated_dts_board.h>\n#include \"memory.h\"\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION data :data_phdr\n#define ROMABLE_REGION text :text_phdr\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  text :\n       \torg = TEXT_BASE,\n        len = TEXT_SIZE,\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n        org = TEXT_BASE + TEXT_SIZE,\n        len = IDT_SIZE,\n#endif\n  data :\n       \torg = TEXT_BASE + TEXT_SIZE + IDT_SIZE,\n        len = DATA_SIZE\n  bss_data :\n        org = TEXT_BASE + TEXT_SIZE + IDT_SIZE + DATA_SIZE,\n        len = BSS_DATA_SIZE\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  text_phdr PT_LOAD;\n  data_phdr PT_LOAD;\n  bss_data_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n_memmap_cacheattr_intel_s1000 = 0xf2ff4242;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >text :text_phdr\n#include <linker\/common-rom.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >data :data_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >data :data_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    KEEP(*(SW_ISR_TABLE))\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >data :data_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >data :data_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >bss_data :bss_data_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <generated_dts_board.h>\n#include \"memory.h\"\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION data :data_phdr\n#define ROMABLE_REGION text :text_phdr\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  text :\n       \torg = TEXT_BASE,\n        len = TEXT_SIZE,\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n        org = TEXT_BASE + TEXT_SIZE,\n        len = IDT_SIZE,\n#endif\n  data :\n       \torg = TEXT_BASE + TEXT_SIZE + IDT_SIZE,\n        len = DATA_SIZE\n  bss_data :\n        org = TEXT_BASE + TEXT_SIZE + IDT_SIZE + DATA_SIZE,\n        len = BSS_DATA_SIZE\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  text_phdr PT_LOAD;\n  data_phdr PT_LOAD;\n  bss_data_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n_memmap_cacheattr_intel_s1000 = 0xf2ff4242;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >text :text_phdr\n#include <linker\/common-rom.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >data :data_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >data :data_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    KEEP(*(SW_ISR_TABLE))\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _data_end = ABSOLUTE(.);\n  } >data :data_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >data :data_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >bss_data :bss_data_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"56948ba190b8920f38564050e1c2742b967a4d13","subject":"BaseTools GCC: align start of .data to .text alignment","message":"BaseTools GCC: align start of .data to .text alignment\n\nNow that GenFw honors the ELF section alignment when placing the\nPE\/COFF sections in the output, the start of the PE\/COFF version of\n.data will be aligned to the alignment of .text if its alignment is\nhigher than the default. So duplicate this behavior in the ELF output,\nthis will make the memory layout of the PE\/COFF binary match the\nlayout of the ELF version more closely.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>\nTested-by: Liming Gao <liming.gao@intel.com>\nTested-by: Leif Lindholm <leif.lindholm@linaro.org>\n\ngit-svn-id: 3158a46dfd52e07d1fda3e32e1ab2e353a00b20f@18136 6f19259b-4bc3-4df7-8a09-765794883524\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"BaseTools\/Scripts\/GccBase.lds","new_file":"BaseTools\/Scripts\/GccBase.lds","new_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.* *COM*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n  }\r\n}\r\n","old_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.* *COM*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"cba34f894c05f535eaee6491b3c78cce2743cc0a","subject":"Move vtables into SRAM.","message":"Move vtables into SRAM.\n\nWith the reordering of the linker script in an earlier commit, we\ncan use basic wildcard matching to grab vtables before the rest of\n.rodata is placed into Flash.\n","repos":"cbiffle\/m4vgalib-demos,cbiffle\/m4vgalib-demos,cbiffle\/m4vgalib-demos","old_file":"m4vga-stm32f4xx.ld","new_file":"m4vga-stm32f4xx.ld","new_contents":"MEMORY {\n  \/* Alias of the SRAM112 region when it's remapped. *\/\n  sram112_at_zero (rwx) : ORIGIN = 0x00000000, LENGTH =  112K\n\n  rom (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  ccm (rwx)     : ORIGIN = 0x10000000, LENGTH =   64K\n  sram112 (rwx) : ORIGIN = 0x20000000, LENGTH =  112K\n  sram16  (rwx) : ORIGIN = 0x2001c000, LENGTH =   16K\n}\n\nEXTERN(_ZN6armv7mL19v7m_exception_tableE)\n\nENTRY(v7m_reset_handler)\n\nSECTIONS {\n  \/*\n   * The sram_image section is loaded at the base of ROM.  Early in boot, we\n   * copy it into SRAM to reduce access latency later.  This has an interesting\n   * implication: while the vector table is position independent and can be\n   * useful in both locations, the reset vector itself must not be in this\n   * section!\n   *\/\n  .sram_image : {\n    \/* The vector table will exist in both locations after copy. *\/\n    KEEP(*(.v7m_exception_table))\n    KEEP(*(.stm32f4xx_interrupt_table))\n    \/* Include any functions that have been explicitly placed here. *\/\n    KEEP(*(.ramcode*))\n    \/* Include vtables. *\/\n    KEEP(*(.rodata._ZTV*))\n    \/* Include initialized data here, so we initialize it during the copy. *\/\n    *(.data*)\n    \/* We use a word copy, so ensure alignment. *\/\n    . = ALIGN(4);\n  } >sram112_at_zero AT>rom\n\n  \/* Generate some symbols to direct the copying code. *\/\n  PROVIDE(_sram_image_start = LOADADDR(.sram_image));\n  PROVIDE(_sram_image_end = _sram_image_start + SIZEOF(.sram_image));\n  PROVIDE(_sram_image_dest = ORIGIN(sram112_at_zero));\n\n  \/*\n   * Plain old .text contains functions without strict latency requirements,\n   * and rodata.  This implies that const data goes in high-latency Flash,\n   * and must be copied into RAM by any programs with latency requirements.\n   *\/\n  .text : {\n    *(.text*)\n    . = ALIGN(4);\n    *(.rodata*)\n  } >rom\n\n  .init : ALIGN(2) {\n    KEEP(*(.init_prologue))\n    KEEP(*(.init))\n    KEEP(*(.init_epilogue))\n  } >rom\n\n  .preinit_array : ALIGN(4) {\n    _preinit_array_start = .;\n    KEEP(*(.preinit_array))\n    _preinit_array_end = .;\n  } >rom\n\n  .init_array : ALIGN(4) {\n    _init_array_start = .;\n    KEEP(*(.init_array))\n    _init_array_end = .;\n  } >rom\n\n  .bss (NOLOAD) : {\n    . = ALIGN(4);\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >sram112_at_zero\n\n  PROVIDE(_bss_start = ADDR(.bss));\n  PROVIDE(_bss_end   = ADDR(.bss) + SIZEOF(.bss));\n\n  .arena_sram112 (NOLOAD) : {\n    . = ALIGN(4);\n    PROVIDE(_sram112_arena_start = .);\n    \/* Exhaust the rest of this memory. *\/\n    . = ORIGIN(sram112_at_zero) + LENGTH(sram112_at_zero);\n  } >sram112_at_zero\n\n  .local (NOLOAD) : {\n    . += 1024;  \/* Leave room for a stack. *\/\n    PROVIDE(v7m_initial_stack_top = .);\n    \/* Allow stuff to be placed explicitly into CCM as needed. *\/\n    KEEP(*(.vga_local_ram))\n    . = ALIGN(4);\n\n    PROVIDE(_ccm_arena_start = .);\n    . += 60000;  \/* Encourage a minimum arena size. *\/\n    \/* Exhaust the rest of this memory. *\/\n    . = ORIGIN(ccm) + LENGTH(ccm);\n  } >ccm\n\n  \/* Allow stuff to be placed explicitly into scanout RAM as needed. *\/\n  .sram16 (NOLOAD) : {\n    KEEP(*(.vga_scan_ram))\n  } >sram16\n\n  \/*\n   * Generate a table defining the boundaries of free RAM for the arenas. *\/\n  .arena_regions : {\n    PROVIDE(_arena_regions_start = .);\n    LONG(_ccm_arena_start);\n    LONG(ORIGIN(ccm) + LENGTH(ccm));\n    LONG(_sram112_arena_start);\n    LONG(ORIGIN(sram112_at_zero) + LENGTH(sram112_at_zero));\n    PROVIDE(_arena_regions_end = .);\n  } >rom\n\n}\n\nPROVIDE(_flash_base = ORIGIN(rom));\n","old_contents":"MEMORY {\n  \/* Alias of the SRAM112 region when it's remapped. *\/\n  sram112_at_zero (rwx) : ORIGIN = 0x00000000, LENGTH =  112K\n\n  rom (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  ccm (rwx)     : ORIGIN = 0x10000000, LENGTH =   64K\n  sram112 (rwx) : ORIGIN = 0x20000000, LENGTH =  112K\n  sram16  (rwx) : ORIGIN = 0x2001c000, LENGTH =   16K\n}\n\nEXTERN(_ZN6armv7mL19v7m_exception_tableE)\n\nENTRY(v7m_reset_handler)\n\nSECTIONS {\n  \/*\n   * The sram_image section is loaded at the base of ROM.  Early in boot, we\n   * copy it into SRAM to reduce access latency later.  This has an interesting\n   * implication: while the vector table is position independent and can be\n   * useful in both locations, the reset vector itself must not be in this\n   * section!\n   *\/\n  .sram_image : {\n    \/* The vector table will exist in both locations after copy. *\/\n    KEEP(*(.v7m_exception_table))\n    KEEP(*(.stm32f4xx_interrupt_table))\n    \/* Include any functions that have been explicitly placed here. *\/\n    KEEP(*(.ramcode*))\n    \/* Include initialized data here, so we initialize it during the copy. *\/\n    *(.data*)\n    \/* We use a word copy, so ensure alignment. *\/\n    . = ALIGN(4);\n  } >sram112_at_zero AT>rom\n\n  \/* Generate some symbols to direct the copying code. *\/\n  PROVIDE(_sram_image_start = LOADADDR(.sram_image));\n  PROVIDE(_sram_image_end = _sram_image_start + SIZEOF(.sram_image));\n  PROVIDE(_sram_image_dest = ORIGIN(sram112_at_zero));\n\n  \/*\n   * Plain old .text contains functions without strict latency requirements,\n   * and rodata.  This implies that const data goes in high-latency Flash,\n   * and must be copied into RAM by any programs with latency requirements.\n   *\/\n  .text : {\n    *(.text*)\n    . = ALIGN(4);\n\n    \/* Unfortunately, gcc places vtables here, in Flash.  TODO. *\/\n    *(.rodata*)\n\n    . = ALIGN(4);\n  } >rom\n\n  .init : ALIGN(2) {\n    KEEP(*(.init_prologue))\n    KEEP(*(.init))\n    KEEP(*(.init_epilogue))\n  } >rom\n\n  .preinit_array : ALIGN(4) {\n    _preinit_array_start = .;\n    KEEP(*(.preinit_array))\n    _preinit_array_end = .;\n  } >rom\n\n  .init_array : ALIGN(4) {\n    _init_array_start = .;\n    KEEP(*(.init_array))\n    _init_array_end = .;\n  } >rom\n\n  .bss (NOLOAD) : {\n    . = ALIGN(4);\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >sram112_at_zero\n\n  PROVIDE(_bss_start = ADDR(.bss));\n  PROVIDE(_bss_end   = ADDR(.bss) + SIZEOF(.bss));\n\n  .arena_sram112 (NOLOAD) : {\n    . = ALIGN(4);\n    PROVIDE(_sram112_arena_start = .);\n    \/* Exhaust the rest of this memory. *\/\n    . = ORIGIN(sram112_at_zero) + LENGTH(sram112_at_zero);\n  } >sram112_at_zero\n\n  .local (NOLOAD) : {\n    . += 1024;  \/* Leave room for a stack. *\/\n    PROVIDE(v7m_initial_stack_top = .);\n    \/* Allow stuff to be placed explicitly into CCM as needed. *\/\n    KEEP(*(.vga_local_ram))\n    . = ALIGN(4);\n\n    PROVIDE(_ccm_arena_start = .);\n    . += 60000;  \/* Encourage a minimum arena size. *\/\n    \/* Exhaust the rest of this memory. *\/\n    . = ORIGIN(ccm) + LENGTH(ccm);\n  } >ccm\n\n  \/* Allow stuff to be placed explicitly into scanout RAM as needed. *\/\n  .sram16 (NOLOAD) : {\n    KEEP(*(.vga_scan_ram))\n  } >sram16\n\n  \/*\n   * Generate a table defining the boundaries of free RAM for the arenas. *\/\n  .arena_regions : {\n    PROVIDE(_arena_regions_start = .);\n    LONG(_ccm_arena_start);\n    LONG(ORIGIN(ccm) + LENGTH(ccm));\n    LONG(_sram112_arena_start);\n    LONG(ORIGIN(sram112_at_zero) + LENGTH(sram112_at_zero));\n    PROVIDE(_arena_regions_end = .);\n  } >rom\n\n}\n\nPROVIDE(_flash_base = ORIGIN(rom));\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"a709e252eb60dec7eb7f923797814e72ffda5dcc","subject":"ATLEDGE-334 Update version header location in linker script","message":"ATLEDGE-334 Update version header location in linker script\n\nNeed to update linker script to match recent firmware change:\n\nJIRA: FIRE-2160\n\n1024 bytes were used to store the version header, which is only\n48 bytes big. So we wasted 976 bytes. By moving it after the vector table,\nwe can free this 1024 bytes space.\n\nSigned-off-by: Brian Baltz <e33194ccd640f9fff080ead3cbd1c59a31a9ba3f@intel.com>\n","repos":"facchinm\/corelibs-arduino101,yashaswini-hanji\/corelibs-arduino101,linrjing\/corelibs-arduino101,facchinm\/corelibs-arduino101,01org\/corelibs-arduino101,yashaswini-hanji\/corelibs-arduino101,sandeepmistry\/corelibs-arduino101,sandeepmistry\/corelibs-arduino101,sgbihu\/corelibs-arduino101,sandeepmistry\/corelibs-arduino101,bigdinotech\/corelibs-arduino101,sgbihu\/corelibs-arduino101,SidLeung\/corelibs-arduino101,linrjing\/corelibs-arduino101,eriknyquist\/corelibs-arduino101,yashaswini-hanji\/corelibs-arduino101,bigdinotech\/corelibs-arduino101,01org\/corelibs-arduino101,eriknyquist\/corelibs-arduino101,sgbihu\/corelibs-arduino101,bigdinotech\/corelibs-arduino101,01org\/corelibs-arduino101,SidLeung\/corelibs-arduino101","old_file":"variants\/intel_edu_x\/linker_scripts\/flash.ld","new_file":"variants\/intel_edu_x\/linker_scripts\/flash.ld","new_contents":"\/* linker.cmd - Linker command\/script file *\/\n\n\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1) Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2) Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and\/or other materials provided with the distribution.\n *\n * 3) Neither the name of Wind River Systems nor the names of its contributors\n * may be used to endorse or promote products derived from this software without\n * specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\/\n\n\/*\nDESCRIPTION\nLinker script for the Atlas Peak ARC BSPs.\n*\/\n\nOUTPUT_FORMAT(\"elf32-littlearc\", \"elf32-bigarc\", \"elf32-littlearc\")\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = 0x40034000, LENGTH = 152K\n    SRAM                  (wx) : ORIGIN = 0xa800e000, LENGTH = 24K\n    DCCM                  (wx) : ORIGIN = 0x80000000, LENGTH = 8K\n    }\n\n\/* Define default stack size and FIRQ stack size.\n * See below stack section for __stack_start and __firq_stack_start\n *\/\n__stack_size = 2048;\n__firq_stack_size = 512;\n\n\/* Minimum heap size to allocate\n * Actual heap size might be bigger due to page size alignment *\/\n__HEAP_SIZE_MIN = 8192;\n\/* This should be set to the page size used by the malloc implementation *\/\n__PAGE_SIZE = 4096;\n\nSECTIONS\n    {\n\/* FLASH Start *\/\n\n    text : ALIGN(1024)\n\t{\n\t__text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\tKEEP(*(.int_vector_table))\n\tKEEP(*(\".int_vector_table.*\"))\n\n\t*(.version_header)\n\tKEEP(*(\".version_header*\"))\n\n\t*(.text)\n\t*(\".text.*\")\n\t__text_end = .;\n\t} > FLASH\n\n    ctors :\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __ctor_table_start must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first element of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } > FLASH\n\n    rodata :\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t} > FLASH\n\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n\/* FLASH End *\/\n\n\/* SRAM Start *\/\n\n    datas : AT(__data_rom_start)\n\t{\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t} > SRAM\n\n    __data_ram_end = .;\n\n    bss (NOLOAD) :\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n        \/*\n         * BSP clears this memory in words only and doesn't clear any\n         * potential left over bytes.\n\t *\/\n\t__bss_end = ALIGN(4);\n\t} > SRAM\n\n    noinit (NOLOAD) :\n        {\n        \/*\n         * This section is used for non-intialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t\/*\n\t * The seg_rxtx section is used by the Host IO module for\n\t * allocating RX\/TX buffers. If a specific memory location is\n\t * required for these buffers, then a MEMORY definition should be\n\t * made.\n\t *\/\n\t*(.seg_rxtx)\n\t*(\".seg_rxtx.*\")\n        } > SRAM\n\n    heap (NOLOAD) :\n    {\n        . = ALIGN(4);\n        __start_heap = .;\n        . = . + __HEAP_SIZE_MIN;\n        __end_heap = ALIGN(__PAGE_SIZE);\n    } > SRAM\n\n    stack :\n    {\n        . += __firq_stack_size;\n        . = ALIGN(4);\n        __firq_stack_start = .;\n\n        . += __stack_size;\n        . = ALIGN(4);\n        __stack_start = .;\n    } > SRAM\n\n    \/* Define linker symbols *\/\n\n    _end = .; \/* end of image *\/\n\n\/* SRAM End *\/\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\/* DCCM Start *\/\n\/* DCCM End *\/\n\n    }\n","old_contents":"\/* linker.cmd - Linker command\/script file *\/\n\n\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1) Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2) Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and\/or other materials provided with the distribution.\n *\n * 3) Neither the name of Wind River Systems nor the names of its contributors\n * may be used to endorse or promote products derived from this software without\n * specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\/\n\n\/*\nDESCRIPTION\nLinker script for the Atlas Peak ARC BSPs.\n*\/\n\nOUTPUT_FORMAT(\"elf32-littlearc\", \"elf32-bigarc\", \"elf32-littlearc\")\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = 0x40034000, LENGTH = 152K\n    SRAM                  (wx) : ORIGIN = 0xa800e000, LENGTH = 24K\n    DCCM                  (wx) : ORIGIN = 0x80000000, LENGTH = 8K\n    }\n\n\/* Define default stack size and FIRQ stack size.\n * See below stack section for __stack_start and __firq_stack_start\n *\/\n__stack_size = 2048;\n__firq_stack_size = 512;\n\n\/* Minimum heap size to allocate\n * Actual heap size might be bigger due to page size alignment *\/\n__HEAP_SIZE_MIN = 8192;\n\/* This should be set to the page size used by the malloc implementation *\/\n__PAGE_SIZE = 4096;\n\nSECTIONS\n    {\n\/* FLASH Start *\/\n\n    version_header_section :\n    {\n        *(.version_header)\n        KEEP(*(\".version_header*\"))\n    } > FLASH\n\n    text : ALIGN(1024)\n\t{\n\t__text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\tKEEP(*(.int_vector_table))\n\tKEEP(*(\".int_vector_table.*\"))\n\n\t*(.text)\n\t*(\".text.*\")\n\t__text_end = .;\n\t} > FLASH\n\n    ctors :\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __ctor_table_start must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first element of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } > FLASH\n\n    rodata :\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t} > FLASH\n\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n\/* FLASH End *\/\n\n\/* SRAM Start *\/\n\n    datas : AT(__data_rom_start)\n\t{\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t} > SRAM\n\n    __data_ram_end = .;\n\n    bss (NOLOAD) :\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n        \/*\n         * BSP clears this memory in words only and doesn't clear any\n         * potential left over bytes.\n\t *\/\n\t__bss_end = ALIGN(4);\n\t} > SRAM\n\n    noinit (NOLOAD) :\n        {\n        \/*\n         * This section is used for non-intialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t\/*\n\t * The seg_rxtx section is used by the Host IO module for\n\t * allocating RX\/TX buffers. If a specific memory location is\n\t * required for these buffers, then a MEMORY definition should be\n\t * made.\n\t *\/\n\t*(.seg_rxtx)\n\t*(\".seg_rxtx.*\")\n        } > SRAM\n\n    heap (NOLOAD) :\n    {\n        . = ALIGN(4);\n        __start_heap = .;\n        . = . + __HEAP_SIZE_MIN;\n        __end_heap = ALIGN(__PAGE_SIZE);\n    } > SRAM\n\n    stack :\n    {\n        . += __firq_stack_size;\n        . = ALIGN(4);\n        __firq_stack_start = .;\n\n        . += __stack_size;\n        . = ALIGN(4);\n        __stack_start = .;\n    } > SRAM\n\n    \/* Define linker symbols *\/\n\n    _end = .; \/* end of image *\/\n\n\/* SRAM End *\/\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\/* DCCM Start *\/\n\/* DCCM End *\/\n\n    }\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"0f1b7f7d12af6041238bec1a19459e04acbbb02d","subject":"add ext area","message":"add ext area\n","repos":"hirakuni45\/R8C,hirakuni45\/R8C,hirakuni45\/R8C","old_file":"M120AN\/m120an.ld","new_file":"M120AN\/m120an.ld","new_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x00300, LENGTH = 0x00400\n\tROM (r)  : ORIGIN = 0x08000, LENGTH = 0x07FD8\n\tEXT (r)  : ORIGIN = 0x10000, LENGTH = 0x17FFF\n\tVVEC (r) : ORIGIN = 0x0FED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0x0FFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0780;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  .exttext   :\n  {\n    *(.exttext .stub .exttext.* .gnu.linkonce.t.*)\n    KEEP (*(.exttext.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n  } > EXT =0\n\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x0300, LENGTH = 0x0400\n\tROM (r)  : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVVEC (r) : ORIGIN = 0xFED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0780;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"b8ebce0fef2ae09e03774f5e7ad019dde877aa75","subject":" add a memory section for RAM so that the linker will warn when you've     made your program too big.","message":" add a memory section for RAM so that the linker will warn when you've\n    made your program too big.\n","repos":"arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki","old_file":"cpu\/mc1322x\/mc1322x.lds","new_file":"cpu\/mc1322x\/mc1322x.lds","new_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\n\nMEMORY\n  {\n    ram (rwx) : org = 0x00400000, l = 96K\n  }\n\nSECTIONS\n{\n\nSYS_STACK_SIZE = 1024;\nIRQ_STACK_SIZE = 256;\nFIQ_STACK_SIZE = 256;\nSVC_STACK_SIZE = 256;\nABT_STACK_SIZE = 16;\nUND_STACK_SIZE = 16;\nHEAP_SIZE = 1024;\n\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x00400000); . = 0x00400000;\n  .text           :\n  {\n    *(.start)\n    *(.irq)\t\t\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  } =0\n\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n      *(.rela.ctors)\n      *(.rela.dtors)\n      *(.rela.got)\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n    }\n  .rel.plt        : { *(.rel.plt) }\n  .rela.plt       : { *(.rela.plt) }\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0\n  .plt            : { *(.plt) }\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n\n\/*  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); *\/\n\n\t. = ALIGN(4);\n\t. = DATA_SEGMENT_ALIGN(4,4); \n\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n  .init_array     :\n  {\n     PROVIDE_HIDDEN (__init_array_start = .);\n     KEEP (*(SORT(.init_array.*)))\n     KEEP (*(.init_array))\n     PROVIDE_HIDDEN (__init_array_end = .);\n  }\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  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{"commit":"d103eee64294a516b910ddcb16c0d0415b9dbbc8","subject":"intel_adsp: ace: Fix debug vector address","message":"intel_adsp: ace: Fix debug vector address\n\nIn ace15_mtpm the debug exception vector address is mapped to INTLEVEL4\nand not INTLEVEL 6. This can be checked in the core-isa header:\n\n\"\"\"\ndefine XCHAL_DEBUG_VECTOR_VADDR        XCHAL_INTLEVEL4_VECTOR_VADDR\n\"\"\"\n\nin\nmodules\/hal\/xtensa\/zephyr\/soc\/intel_ace15_mtpm\/xtensa\/config\/core-isa.h\n\nSigned-off-by: Flavio Ceolin <979b9165500b0741b9d0500e2efd74fc1547bff7@intel.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/ace\/ace-link.ld","new_file":"soc\/xtensa\/intel_adsp\/ace\/ace-link.ld","new_contents":"\/*\n * Copyright (c) 2022 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <zephyr\/devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <zephyr\/linker\/sections.h>\n#include <adsp-vectors.h>\n#include <adsp_memory.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n    _imr_end = .;\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int4_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int4_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_ram_start = .;\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.initcall)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <zephyr\/linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <zephyr\/linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n     _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n\n  \/* Heap start and end markers. Used to reserve system heap memory. *\/\n  .heap_mem SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _heap_start = .;\n    *(.heap_mem)\n    _heap_end = .;\n  } >ucram\n\n  .unused_ram_start_marker SEGSTART_CACHED (NOLOAD) :\n  {\n    . = ALIGN(4096);\n    _unused_ram_start_marker = .;\n    *(.unused_ram_start_marker)\n    *(.unused_ram_start_marker.*)\n  } >ram\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n    _image_ram_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2022 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <zephyr\/devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <zephyr\/linker\/sections.h>\n#include <adsp-vectors.h>\n#include <adsp_memory.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n    _imr_end = .;\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int6_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int6_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_ram_start = .;\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.initcall)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <zephyr\/linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <zephyr\/linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n     _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n\n  \/* Heap start and end markers. Used to reserve system heap memory. *\/\n  .heap_mem SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _heap_start = .;\n    *(.heap_mem)\n    _heap_end = .;\n  } >ucram\n\n  .unused_ram_start_marker SEGSTART_CACHED (NOLOAD) :\n  {\n    . = ALIGN(4096);\n    _unused_ram_start_marker = .;\n    *(.unused_ram_start_marker)\n    *(.unused_ram_start_marker.*)\n  } >ram\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n    _image_ram_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6ea12f0fbb48662062351105ec26de01ffc99df9","subject":"linker: esp32c3: add thread storage area","message":"linker: esp32c3: add thread storage area\n\nThis adds missing _end area and remove\nunused definitions present in the linker script\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/riscv\/esp32c3\/linker.ld","new_file":"soc\/riscv\/esp32c3\/linker.ld","new_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32c3 platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define IRAM_REGION  iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\n#define SRAM_IRAM_START     0x4037C000\n#define SRAM_DRAM_START     0x3FC7C000\n#define ICACHE_SIZE         0x4000 \/* ICache size is fixed to 16KB on ESP32-C3 *\/\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n\/* Global symbols required for espressif hal build *\/\nMEMORY\n{\n  iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n  irom0_0_seg(RX): org = 0x42000020, len = 0x8000000-0x20\n\n  drom0_0_seg (R) : org = 0x3C000020, len = 0x8000000-0x20\n  dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE\n\n  rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000\n\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(__start)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } > rtc_iram_seg\n\n  \/* This section is required to skip rtc.text area because the text and\n   * data segments reflect the same address space on different buses.\n   *\/\n  .rtc.dummy (NOLOAD):\n  {\n    . = SIZEOF(.rtc.text);\n  } > rtc_iram_seg\n\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n\n  .iram0.text : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _iram_start = ABSOLUTE(.);\n    _iram_text_start = ABSOLUTE(.);\n    _init_start = ABSOLUTE(.);\n    KEEP(*(.exception_vectors.text));\n    . = ALIGN(256);\n\n    KEEP(*(.exception.entry*)); \/* contains __irq_wrapper *\/\n    *(.exception.other*)\n    . = ALIGN(4);\n\n    . = ALIGN (4);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    . = ALIGN(4);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    . = ALIGN(4);\n    _init_end = ABSOLUTE(.);\n    _iram_text_end = ABSOLUTE(.);   *(.srodata)\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  \/**\n   * This section is required to skip .iram0.text area because iram0_0_seg and\n   * dram0_0_seg reflect the same address space on different buses.\n   *\/\n  .dram0.dummy (NOLOAD):\n  {\n    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } > dram0_0_seg\n\n#include <linker\/common-ram.ld>\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    __global_pointer$ = . + 0x800;\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    _end = .;\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  \/* Shared RAM *\/\n  dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  .flash.text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  .flash_rodata_dummy (NOLOAD):\n  {\n    . = SIZEOF(.flash.text);\n    . = ALIGN(0x10000) + 0x20;\n    _rodata_reserved_start = .;\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  .flash.rodata : ALIGN(0x10)\n  {\n    _rodata_start = ABSOLUTE(.);\n    _image_rodata_start = .;\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    *(.rodata_desc .rodata_desc.*)               \/* Should be the first.  App version info.        DO NOT PUT ANYTHING BEFORE IT! *\/\n    *(.rodata_custom_desc .rodata_custom_desc.*) \/* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! *\/\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*\n     * C++ constructor and destructor tables\n     * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.\n     *\n     * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.\n     * But the init_priority sections will be sorted for iteration in ascending order during startup.\n     * The rest of the init_array sections is sorted for iteration in descending order during startup, however.\n     * Hence a different section is generated for the init_priority functions which is iterated in\n     * ascending order during startup. The corresponding code can be found in startup.c.\n     *\/\n    __init_priority_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))\n    __init_priority_array_end = ABSOLUTE(.);\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/* C++ exception handlers table: *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_rodata_end = .;\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    *(.srodata)\n    *(\".srodata.*\")\n    *(.rodata)\n    *(.rodata.*)\n    _thread_local_end = ABSOLUTE(.);\n    _rodata_reserved_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n    KEEP(*(.riscv.attributes))\n    KEEP(*(.gnu.attributes))\n\t}\n}\n","old_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32c3 platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define IRAM_REGION  iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\n#define SRAM_IRAM_START     0x4037C000\n#define SRAM_DRAM_START     0x3FC7C000\n#define ICACHE_SIZE         0x4000 \/* ICache size is fixed to 16KB on ESP32-C3 *\/\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n\/* Global symbols required for espressif hal build *\/\nMEMORY\n{\n  iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n  irom0_0_seg(RX): org = 0x42000020, len = 0x8000000-0x20\n\n  drom0_0_seg (R) : org = 0x3C000020, len = 0x8000000-0x20\n  dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE\n\n  rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000\n\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(__start)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } > rtc_iram_seg\n\n  \/* This section is required to skip rtc.text area because the text and\n   * data segments reflect the same address space on different buses.\n   *\/\n  .rtc.dummy (NOLOAD):\n  {\n    . = SIZEOF(.rtc.text);\n  } > rtc_iram_seg\n\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n\n  .iram0.text : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _iram_start = ABSOLUTE(.);\n    _iram_text_start = ABSOLUTE(.);\n    _init_start = ABSOLUTE(.);\n    KEEP(*(.exception_vectors.text));\n    . = ALIGN(256);\n\n    KEEP(*(.exception.entry*)); \/* contains __irq_wrapper *\/\n    *(.exception.other*)\n    . = ALIGN(4);\n\n    . = ALIGN (4);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    . = ALIGN(4);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    . = ALIGN(4);\n    _init_end = ABSOLUTE(.);\n    _iram_text_end = ABSOLUTE(.);   *(.srodata)\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  \/**\n   * This section is required to skip .iram0.text area because iram0_0_seg and\n   * dram0_0_seg reflect the same address space on different buses.\n   *\/\n  .dram0.dummy (NOLOAD):\n  {\n    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } > dram0_0_seg\n\n#include <linker\/common-ram.ld>\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    __global_pointer$ = . + 0x800;\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  \/* Shared RAM *\/\n  dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  .flash.text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  .flash_rodata_dummy (NOLOAD):\n  {\n    . = SIZEOF(.flash.text);\n    . = ALIGN(0x10000) + 0x20;\n    _rodata_reserved_start = .;\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  .flash.rodata : ALIGN(0x10)\n  {\n    _rodata_start = ABSOLUTE(.);\n    _image_rodata_start = .;\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    *(.rodata_desc .rodata_desc.*)               \/* Should be the first.  App version info.        DO NOT PUT ANYTHING BEFORE IT! *\/\n    *(.rodata_custom_desc .rodata_custom_desc.*) \/* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! *\/\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*\n     * C++ constructor and destructor tables\n     * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.\n     *\n     * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.\n     * But the init_priority sections will be sorted for iteration in ascending order during startup.\n     * The rest of the init_array sections is sorted for iteration in descending order during startup, however.\n     * Hence a different section is generated for the init_priority functions which is iterated in\n     * ascending order during startup. The corresponding code can be found in startup.c.\n     *\/\n    __init_priority_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))\n    __init_priority_array_end = ABSOLUTE(.);\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/* C++ exception handlers table: *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    \/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() *\/\n    soc_reserved_memory_region_start = ABSOLUTE(.);\n    KEEP (*(.reserved_memory_address))\n    soc_reserved_memory_region_end = ABSOLUTE(.);\n    _image_rodata_end = .;\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    *(.srodata)\n    *(\".srodata.*\")\n    *(.rodata)\n    *(.rodata.*)\n    _thread_local_end = ABSOLUTE(.);\n    _rodata_reserved_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n    KEEP(*(.riscv.attributes))\n    KEEP(*(.gnu.attributes))\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c061b67afcffe63a65484cc818401d1a78a66cd7","subject":"[Reflection] Update Linux linker script for .swift3_fieldmd, .swift3_assocty","message":"[Reflection] Update Linux linker script for .swift3_fieldmd, .swift3_assocty\n","repos":"khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift","old_file":"stdlib\/public\/runtime\/swift.ld","new_file":"stdlib\/public\/runtime\/swift.ld","new_contents":"SECTIONS\n{\n  .swift3_typeref : { *(.swift3_typeref) },\n  .swift3_reflstr : { *(.swift3_reflstr) },\n  .swift3_fieldmd : { *(.swift3_fieldmd) },\n  .swift3_assocty : { *(.swift3_assocty) },\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","old_contents":"SECTIONS\n{\n  .swift3_typeref : { *(.swift3_typeref) },\n  .swift3_reflstr : { *(.swift3_reflstr) },\n  .swift3_reflect : { *(.swift3_reflect) },\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ab55b72f949bb4195356f4c87e75fdc9adb0c5d4","subject":"Make .rodata be included in .text","message":"Make .rodata be included in .text\n","repos":"semahawk\/leoman,semahawk\/figh,semahawk\/kernel","old_file":"kernel\/linker.ld","new_file":"kernel\/linker.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\")\nENTRY(_start)\nphys = 0x100000;\n\nSECTIONS\n{\n  .text phys : AT(phys)\n  {\n    text = .;\n    *(.multiboot)\n    *(.text)\n    *(.rodata*)\n    . = ALIGN(4K);\n  }\n\n  .data : AT(phys + (data - text))\n  {\n    data = .;\n    *(.data)\n    . = ALIGN(4K);\n  }\n\n  .bss : AT(phys + (bss - text))\n  {\n    bss = .;\n    *(COMMON)\n    *(.bss)\n    *(.stack)\n    . = ALIGN(4K);\n  }\n\n  kernels_end = .;\n}\n\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\")\nENTRY(_start)\nphys = 0x100000;\n\nSECTIONS\n{\n  .text phys : AT(phys)\n  {\n    text = .;\n    *(.multiboot)\n    *(.text)\n    . = ALIGN(4K);\n  }\n\n  .rodata : AT(phys + (rodata - text))\n  {\n    rodata = .;\n    *(.rodata*)\n    . = ALIGN(4K);\n  }\n\n  .data : AT(phys + (data - text))\n  {\n    data = .;\n    *(.data)\n    . = ALIGN(4K);\n  }\n\n  .bss : AT(phys + (bss - text))\n  {\n    bss = .;\n    *(COMMON)\n    *(.bss)\n    *(.stack)\n    . = ALIGN(4K);\n  }\n\n  kernels_end = .;\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c99a5f682218a40cbe0d41745e77c32c2f4a7b3d","subject":"Issue #217 the fix was applied. Needs to be verified.","message":"Issue #217 the fix was applied. Needs to be verified.\n\n\nFormer-commit-id: 7e6b744037d108acbe3da9fea862240821bdbae7\n","repos":"adamwolf\/chipKIT-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core,UECIDE\/chipKIT-core,pontech\/chipKIT-core,chipKIT32\/chipkit-core,chipKIT32\/chipkit-core,majenkotech\/chipKIT-core,EmbeddedMan\/chipKIT-core,UECIDE\/chipKIT-core,EmbeddedMan\/chipKIT-core,EmbeddedMan\/chipKIT-core,adamwolf\/chipKIT-core,majenkotech\/chipKIT-core,chipKIT32\/chipkit-core,UECIDE\/chipKIT-core,majenkotech\/chipKIT-core,UECIDE\/chipKIT-core,adamwolf\/chipKIT-core,chipKIT32\/chipkit-core,ricklon\/chipKIT-core,ricklon\/chipKIT-core,ricklon\/chipKIT-core,adamwolf\/chipKIT-core,UECIDE\/chipKIT-core,pontech\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,ricklon\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,chipKIT32\/chipkit-core,pontech\/chipKIT-core,adamwolf\/chipKIT-core,majenkotech\/chipKIT-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core","old_file":"pic32\/cores\/pic32\/chipKIT-application-32MX440F512H.ld","new_file":"pic32\/cores\/pic32\/chipKIT-application-32MX440F512H.ld","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\n_ebase_address  = 0x9D000000;\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_RESET_ADDR              = 0x9D001000;\n_EEPROM_ADDR             = 0x9D07F000;\n_BEV_EXCPT_ADDR          = 0xBFC00380;\n_DBG_EXCPT_ADDR          = 0xBFC00480;\n_DBG_CODE_ADDR           = 0xBFC02000;\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n\n  kseg0_program_mem (rx)     : ORIGIN = 0x9D001000, LENGTH = 0x7B000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 \n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x8000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\nSECTIONS\n{\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg0_program_mem\n  \n  .eeprom_pic32 _EEPROM_ADDR :\n  { \n    . += 0x1000;\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n  .vector_0 _ebase_address + 0x200 :\n  {\n    KEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n\n    _text_end = . ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }>kseg0_program_mem\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n  }>kseg0_program_mem\n\n\n  \/* Read-only sections *\/\n  .rodata   :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } >kseg1_data_mem\n  .data  ALIGN(4)  :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _data_image_begin = LOADADDR(.data) ;\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit8           :\n  {\n    *(.lit8)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    _sbss_end = . ;\n  } >kseg1_data_mem\n  .bss ALIGN(4)  :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  \/DISCARD\/         : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  \/DISCARD\/         : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\n_ebase_address  = 0x9D000000;\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_RESET_ADDR              = 0x9D001000;\n_EEPROM_ADDR             = 0x9D07F000;\n_BEV_EXCPT_ADDR          = 0xBFC00380;\n_DBG_EXCPT_ADDR          = 0xBFC00480;\n_DBG_CODE_ADDR           = 0xBFC02000;\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7E000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 \n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x8000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\nSECTIONS\n{\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg0_program_mem\n  \n  .eeprom_pic32 _EEPROM_ADDR :\n  { \n    . += 0x1000;\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n  .vector_0 _ebase_address + 0x200 :\n  {\n    KEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n\n    _text_end = . ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }>kseg0_program_mem\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n  }>kseg0_program_mem\n\n\n  \/* Read-only sections *\/\n  .rodata   :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } >kseg1_data_mem\n  .data  ALIGN(4)  :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _data_image_begin = LOADADDR(.data) ;\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit8           :\n  {\n    *(.lit8)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    _sbss_end = . ;\n  } >kseg1_data_mem\n  .bss ALIGN(4)  :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  \/DISCARD\/         : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  \/DISCARD\/         : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e0f7fbc5fa2988d87902d1362467427a51396abc","subject":"bootloader: expand the space for iram_loader_seg","message":"bootloader: expand the space for iram_loader_seg\n\nFixed ld issue: overflowed iram_loader_seg\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/ld\/esp32s2beta\/bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/ld\/esp32s2beta\/bootloader.ld","new_contents":"\/*\nLinker file used to link the bootloader.\n*\/\n\n\n\/* Simplified memory map for the bootloader\n\n   The main purpose is to make sure the bootloader can load into main memory\n   without overwriting itself.\n*\/\n\nMEMORY\n{\n  \/* I\/O *\/\n  dport0_seg (RW) :                 org = 0x3FF00000, len = 0x10\n  iram_loader_seg (RWX) :           org = 0x40062000, len = 0x4000  \/* 16KB, IRAM *\/\n  iram_seg (RWX) :                  org = 0x40066000, len = 0x4000  \/* 16KB, IRAM *\/\n  \/* 16k at the end of DRAM, before ROM data & stack *\/\n  dram_seg (RW) :                   org = 0x3FFF8000, len = 0x4000\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_wdt.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","old_contents":"\/*\nLinker file used to link the bootloader.\n*\/\n\n\n\/* Simplified memory map for the bootloader\n\n   The main purpose is to make sure the bootloader can load into main memory\n   without overwriting itself.\n*\/\n\nMEMORY\n{\n  \/* I\/O *\/\n  dport0_seg (RW) :                 org = 0x3FF00000, len = 0x10\n  iram_loader_seg (RWX) :           org = 0x40062000, len = 0x2000  \/* 8KB, IRAM *\/\n  iram_seg (RWX) :                  org = 0x40064000, len = 0x4000  \/* 16KB, IRAM *\/\n  \/* 16k at the end of DRAM, before ROM data & stack *\/\n  dram_seg (RW) :                   org = 0x3FFF8000, len = 0x4000\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_wdt.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9881ce0a11b5044d0bc5910efeb3b4e0ec354fdf","subject":"linker: cpp: Disable sorting of C++ exception handling info sections","message":"linker: cpp: Disable sorting of C++ exception handling info sections\n\nThe `CONFIG_LINKER_SORT_BY_ALIGNMENT` config, which is enabled by\ndefault, causes the sections containing C++ exception handling\ninformation to be re-ordered for certain targets (in particular, the\n64-bit arch targets). This effectively breaks the required \"crtbegin.o\n-> others -> crtend.o\" order and causes the address of the\n__EH_FRAME_BEGIN__ symbol to be invalid; thereby, causing C++\nexception unwinding to fail.\n\nThis commit adds SORT_NONE property to these sections in order to\nensure that the linking order specified in the linker command line is\nmaintained.\n\nSigned-off-by: Stephanos Ioannidis <dc76e9f0c0006e8f919e0c515c66dbba3982f785@stephanos.io>\n","repos":"finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr","old_file":"include\/linker\/cplusplus-ram.ld","new_file":"include\/linker\/cplusplus-ram.ld","new_contents":"\/*\n * Copyright (c) 2019 Jan Van Winkel <jan.van_winkel@dxplore.eu>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_DATA_PROLOGUE(.gcc_except_table,,ONLY_IF_RW)\n\t{\n\t*(.gcc_except_table .gcc_except_table.*)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined (CONFIG_EXCEPTIONS)\n    SECTION_PROLOGUE(.eh_frame_hdr,,)\n\t{\n\t*(.eh_frame_hdr)\n\t}\n\n    SECTION_PROLOGUE(.eh_frame,,)\n\t{\n\tKEEP (*(SORT_NONE(EXCLUDE_FILE (*crtend.o) .eh_frame)))\n\tKEEP (*(SORT_NONE(.eh_frame)))\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(.tm_clone_table,,)\n\t{\n\tKEEP (*(SORT_NONE(EXCLUDE_FILE (*crtend.o) .tm_clone_table)))\n\tKEEP (*(SORT_NONE(.tm_clone_table)))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_EXCEPTIONS *\/\n\n#endif \/* CONFIG_CPLUSPLUS *\/\n","old_contents":"\/*\n * Copyright (c) 2019 Jan Van Winkel <jan.van_winkel@dxplore.eu>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_DATA_PROLOGUE(.gcc_except_table,,ONLY_IF_RW)\n\t{\n\t*(.gcc_except_table .gcc_except_table.*)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined (CONFIG_EXCEPTIONS)\n    SECTION_PROLOGUE(.eh_frame_hdr,,)\n\t{\n\t*(.eh_frame_hdr)\n\t}\n\n    SECTION_PROLOGUE(.eh_frame,,)\n\t{\n\tKEEP (*(EXCLUDE_FILE (*crtend.o) .eh_frame))\n\tKEEP (*(.eh_frame))\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(.tm_clone_table,,)\n\t{\n\tKEEP (*(EXCLUDE_FILE (*crtend.o) .tm_clone_table))\n\tKEEP (*(.tm_clone_table))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_EXCEPTIONS *\/\n\n#endif \/* CONFIG_CPLUSPLUS *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e24e099bdb742fe5f2dcb51bfde9b99dd8d70541","subject":"Fixes linking","message":"Fixes linking\n\nThe previous commit did not seem to link properly.\n","repos":"ekohandel\/AM335x","old_file":"src\/echo\/echo.ld","new_file":"src\/echo\/echo.ld","new_contents":"","old_contents":"SECTIONS\n{\n  . = 0x402F0400;\n  .text : {*(reset)}\n  .text : {*(text)}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ccaeda6f0659954c1b88fe6f06be28168155a812","subject":"\u30d5\u30e9\u30c3\u30b7\u30e5\u306e\u30a8\u30ea\u30a2\u306e\u524a\u6e1b\\n\\n\u30e6\u30fc\u30b6\u30fc\u306e\u4f7f\u3046\u5206\uff08\u5b9a\u6570\u5b9a\u7fa9\u90e8\uff09\u3060\u3051\u6e1b\u3089\u3057\u307e\u3057\u305f\u3002","message":"\u30d5\u30e9\u30c3\u30b7\u30e5\u306e\u30a8\u30ea\u30a2\u306e\u524a\u6e1b\\n\\n\u30e6\u30fc\u30b6\u30fc\u306e\u4f7f\u3046\u5206\uff08\u5b9a\u6570\u5b9a\u7fa9\u90e8\uff09\u3060\u3051\u6e1b\u3089\u3057\u307e\u3057\u305f\u3002\n","repos":"nitkcrbkn\/2016BTeam,nitkcrbkn\/2016BTeam,nitkcrbkn\/2016ATeam,nitkcrbkn\/2016ATeam","old_file":"Drivers\/STM32F103RBTx_FLASH.ld","new_file":"Drivers\/STM32F103RBTx_FLASH.ld","new_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F103RBTx Device with\n**                128KByte FLASH, 20KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n*****************************************************************************\n** @attention\n**\n** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6<\/center><\/h2>\n**\n** Redistribution and use in source and binary forms, with or without modification,\n** are permitted provided that the following conditions are met:\n**   1. Redistributions of source code must retain the above copyright notice,\n**      this list of conditions and the following disclaimer.\n**   2. Redistributions in binary form must reproduce the above copyright notice,\n**      this list of conditions and the following disclaimer in the documentation\n**      and\/or other materials provided with the distribution.\n**   3. Neither the name of Ac6 nor the names of its contributors\n**      may be used to endorse or promote products derived from this software\n**      without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20005000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 128K-1k\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","old_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F103RBTx Device with\n**                128KByte FLASH, 20KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n*****************************************************************************\n** @attention\n**\n** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6<\/center><\/h2>\n**\n** Redistribution and use in source and binary forms, with or without modification,\n** are permitted provided that the following conditions are met:\n**   1. Redistributions of source code must retain the above copyright notice,\n**      this list of conditions and the following disclaimer.\n**   2. Redistributions in binary form must reproduce the above copyright notice,\n**      this list of conditions and the following disclaimer in the documentation\n**      and\/or other materials provided with the distribution.\n**   3. Neither the name of Ac6 nor the names of its contributors\n**      may be used to endorse or promote products derived from this software\n**      without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20005000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 128K\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"cfb05d43f99e602dc940a55d60c749bd949bb26c","subject":"update memory sections","message":"update memory sections\n","repos":"mbains\/STM32F4Discovery_GCC,mbains\/STM32F4Discovery_GCC","old_file":"stm32_flash.ld","new_file":"stm32_flash.ld","new_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F407VG Device with\n**                1024KByte FLASH, 192KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the Atollic TrueSTUDIO(R) toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20020000;    \/* end of 128K RAM on AHB bus*\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = _ebss );\n    PROVIDE ( _end = _ebss );\n    PROVIDE ( _exit = _ebss );\n    PROVIDE (_stackend = ORIGIN(RAM) + LENGTH(RAM) - _Minimum_Stack_Size);\n\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\n  .memory_b1_text :\n  {\n    *(.mb1text)        \/* .mb1text sections (code) *\/\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\n    *(.mb1rodata)      \/* read-only data (constants) *\/\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F407VG Device with\n**                1024KByte FLASH, 192KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the Atollic TrueSTUDIO(R) toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20020000;    \/* end of 128K RAM on AHB bus*\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    \/* Should this be _ebss?*\/\n    PROVIDE ( _exit = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\n  .memory_b1_text :\n  {\n    *(.mb1text)        \/* .mb1text sections (code) *\/\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\n    *(.mb1rodata)      \/* read-only data (constants) *\/\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"5f535100e65369e497b852fd1e6bc1947009cf81","subject":"Added missing exported symbol in commentary.","message":"Added missing exported symbol in commentary.\n","repos":"JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5","old_file":"Device\/_Template_Vendor\/Vendor\/Device\/Source\/GCC\/gcc_arm.ld","new_file":"Device\/_Template_Vendor\/Vendor\/Device\/Source\/GCC\/gcc_arm.ld","new_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000   \/* 256k *\/\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x08000   \/*  32k *\/\n}\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __Vectors_End\n *   __Vectors_Size\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.vectors))\n\t\t__Vectors_End = .;\n\t\t__Vectors_Size = __Vectors_End - __Vectors;\n\t\t__end__ = .;\n\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__HeapBase = .;\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\tKEEP(*(.heap*))\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\tKEEP(*(.stack*))\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000   \/* 256k *\/\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x08000   \/*  32k *\/\n}\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __Vectors_End\n *   __Vectors_Size\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.vectors))\n\t\t__Vectors_End = .;\n\t\t__Vectors_Size = __Vectors_End - __Vectors;\n\t\t__end__ = .;\n\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__HeapBase = .;\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\tKEEP(*(.heap*))\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\tKEEP(*(.stack*))\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"dc1472be928504f6474ea46d1a6ce9d590be64ca","subject":"soc: esp32s2: linker script update to support mcuboot","message":"soc: esp32s2: linker script update to support mcuboot\n\nThis change creates XiP image handling and proper\nLMA and VMA regions configurations.\n\nThis also adds common-ram.ld and common-rom.ld sections that\nrequire explicit handling due to image sections limitation\nin esptool.\n\nMove additional drivers into IRAM to protect against\nflash cache disable read\/write operation.\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"galak\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"soc\/xtensa\/esp32s2\/linker.ld","new_file":"soc\/xtensa\/esp32s2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32s2 platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAM_IRAM_START    0x40020000\n#define RAM_DRAM_START    0x3ffb0000\n\n#define DATA_RAM_END      0x3ffe0000  \/* 2nd stage bootloader iram_loader_seg\n                                       * starts at SRAM block 14 (reclaimed after\n                                       * app boots)\n                                       *\/\n\n#define IRAM_ORG    (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define DRAM_ORG    (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define I_D_RAM_SIZE   DATA_RAM_END - DRAM_ORG\n\n#define RAMABLE_REGION dram0_0_seg\n#define RODATA_REGION drom0_0_seg\n#define IRAM_REGION iram0_0_seg\n#define FLASH_CODE_REGION irom0_0_seg\n\n#define ROMABLE_REGION ROM\n\n#ifdef CONFIG_FLASH_SIZE\n#define FLASH_SIZE CONFIG_FLASH_SIZE\n#else\n#define FLASH_SIZE 0x400000\n#endif\n\n#ifdef CONFIG_BOOTLOADER_ESP_IDF\n#define IROM_SEG_ORG 0x40080020\n#define IROM_SEG_LEN (FLASH_SIZE-0x20)\n#define IROM_SEG_ALIGN 0x4\n#else\n#define IROM_SEG_ORG 0x40080000\n#define IROM_SEG_LEN FLASH_SIZE\n#define IROM_SEG_ALIGN 0x10000\n#endif\n\nMEMORY\n{\n  mcuboot_hdr (RX): org = 0x0, len = 0x20\n  metadata (RX): org = 0x20, len = 0x20\n  ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40\n  iram0_0_seg(RX): org = IRAM_ORG, len = I_D_RAM_SIZE\n  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN\n  dram0_0_seg(RW): org = DRAM_ORG, len = I_D_RAM_SIZE\n  drom0_0_seg(R): org = 0x3f000040, len = FLASH_SIZE - 0x40\n\n  rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x2000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3f500000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\n\/*  Default entry point:  *\/\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n  \/* Reserve space for MCUboot header in the binary *\/\n  .mcuboot_header :\n  {\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n  } > mcuboot_hdr\n  .metadata :\n  {\n    \/* Magic byte for load header *\/\n    LONG(0xace637d3)\n\n    \/* Application entry point address *\/\n    KEEP(*(.entry_addr))\n\n    \/* IRAM metadata:\n     * - Destination address (VMA) for IRAM region\n     * - Flash offset (LMA) for start of IRAM region\n     * - Size of IRAM region\n     *\/\n    LONG(ADDR(.iram0.vectors))\n    LONG(LOADADDR(.iram0.vectors))\n    LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors))\n\n    \/* DRAM metadata:\n     * - Destination address (VMA) for DRAM region\n     * - Flash offset (LMA) for start of DRAM region\n     * - Size of DRAM region\n     *\/\n    LONG(ADDR(.dram0.data))\n    LONG(LOADADDR(.dram0.data))\n    LONG(LOADADDR(.dummy.dram.data) + SIZEOF(.dummy.dram.data) - LOADADDR(.dram0.data))\n  } > metadata\n\n#include <linker\/rel-sections.ld>\n  _image_drom_start = LOADADDR(_RODATA_SECTION_NAME);\n  _image_drom_size = LOADADDR(_RODATA_SECTION_NAME) + SIZEOF(_RODATA_SECTION_NAME) - _image_drom_start;\n  _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);\n\n  \/* NOTE: .rodata section should be the first section in the linker script and no\n   * other section should appear before .rodata section. This is the requirement\n   * to align ROM section to 64K page offset.\n   * Adding .rodata as first section helps to reduce size of generated binary by\n   * few kBs.\n   *\/\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    *(.rodata_desc .rodata_desc.*)\n    *(.rodata_custom_desc .rodata_custom_desc.*)\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.*) .rodata)\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.*) .rodata.*)\n\n    . = ALIGN(4);\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/* C++ constructor and destructor tables *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*)))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    _rodata_reserved_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    _iram_start = ABSOLUTE(.);\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  .iram0.text : ALIGN(4)\n  {\n    \/* Code marked as running out of IRAM *\/\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:loader.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    \/* align + add 16B for CPU dummy speculative instr. fetch *\/\n    . = ALIGN(4) + 16;\n    _iram_text = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  .dram0.dummy (NOLOAD):\n  {\n    \/**\n    * This section is required to skip .iram0.text area because iram0_0_seg and\n    * dram0_0_seg reflect the same address space on different buses.\n    *\/\n    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN(8);\n    *(.noinit)\n    *(.noinit.*)\n    . = ALIGN(8);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libzephyr.a:loader.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    . = ALIGN(4);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  #pragma push_macro(\"GROUP_ROM_LINK_IN\")\n  #pragma push_macro(\"ITERABLE_SECTION_ROM\")\n  #undef GROUP_ROM_LINK_IN\n  #undef ITERABLE_SECTION_ROM\n  #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN\n  #define ITERABLE_SECTION_ROM(x,y)\n  #include <linker\/common-rom.ld>\n  #pragma pop_macro(\"GROUP_ROM_LINK_IN\")\n  #pragma pop_macro(\"ITERABLE_SECTION_ROM\")\n  #include <linker\/common-ram.ld>\n\n  __shell_root_cmds_start = __esp_shell_root_cmds_start;\n  __shell_root_cmds_end = __esp_shell_root_cmds_end;\n\n  .dummy.dram.data :\n  {\n    . = ALIGN(4);\n    _data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  .iram0.text_end (NOLOAD) :\n  {\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  _image_irom_start = LOADADDR(.flash.text);\n  _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;\n  _image_irom_vaddr = ADDR(.flash.text);\n\n  .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN)\n  {\n    . = SIZEOF(_RODATA_SECTION_NAME);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  .flash.text : ALIGN(IROM_SEG_ALIGN)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(rtc_slow_seg)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_bss_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    . = ALIGN(4);\n    _ext_ram_bss_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n}\n\nASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM0 segment data does not fit.\")\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","old_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32s2 platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAM_IRAM_START    0x40020000\n#define RAM_DRAM_START    0x3ffb0000\n\n#define DATA_RAM_END      0x3ffe0000  \/* 2nd stage bootloader iram_loader_seg starts at SRAM block 14 (reclaimed after app boots) *\/\n\n#define IRAM_ORG    (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define DRAM_ORG    (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define I_D_RAM_SIZE   DATA_RAM_END - DRAM_ORG\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = IRAM_ORG, len = I_D_RAM_SIZE\n  irom0_0_seg(RX): org = 0x40080020, len = 0x780000-0x20\n  dram0_0_seg(RW): org = DRAM_ORG, len = I_D_RAM_SIZE\n  drom0_0_seg(R): org = 0x3f000020, len = 0x3f0000-0x20\n  rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x2000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3f500000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    _iram_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n  } GROUP_LINK_IN(IRAM_REGION)\n\n   .dram0_reserved_for_iram (NOLOAD):\n  {\n   . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } > dram0_0_seg\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_condvar);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef ITERABLE_SECTION_RAM_GC_ALLOWED\n#define ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef ITERABLE_SECTION_RAM\n#define ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_bss_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    . = ALIGN(4);\n    _ext_ram_bss_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a092c8817f14f3fdca426d00c33eb0fa6c95a9ac","subject":"remove unused heap size linker variable","message":"remove unused heap size linker variable\n","repos":"dnseitz\/CortexM0Rust","old_file":"rust.ld","new_file":"rust.ld","new_contents":"MEMORY\n{\n  RAM (xrw)     : ORIGIN = 0x20000000, LENGTH = 6K\n  FLASH (rx)    : ORIGIN = 0x08000000, LENGTH = 32K\n}\n\nstack_size = 1024;\n\n_stack_start = ORIGIN(RAM) + LENGTH(RAM);\n_stack_end = _stack_start - stack_size;\n_heap_end = _stack_end;\n\nENTRY(start);\n\nSECTIONS\n{\n  .vector_table ORIGIN(FLASH) :\n  {\n    LONG(_stack_start)\n    KEEP(*(.reset))\n    KEEP(*(.exceptions))\n  } > FLASH\n\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)\n    *(.text*)\n    *(.rodata)\n    *(.rodata*)\n    *(.glue_6)      \/* Glue arm to thumb code *\/\n    *(.glue_6t)     \/* Glue thumb to arm code *\/\n    . = ALIGN(4);\n    _etext = .;\n  } > FLASH\n\n  .ARM.extab : \/* debug info *\/\n  {\n    *(.ARM.extab*)\n  } > FLASH\n\n  \/* Used by startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data section *\/\n  .data : AT (_sidata)\n  {\n    . = ALIGN(4);\n    _sdata = .;     \/* Create global symbol at start of data *\/\n    *(.data)\n    *(.data*)\n\n    . = ALIGN(4);\n    _edata = .;\n  } > RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  { \n    \/* Used by startup to initialize .bss section *\/\n    _sbss = .;\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .; \/* Define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } > RAM\n\n  . = ALIGN(4);\n  .heap :\n  {\n    _heap_start = .;\n  } > RAM\n\n  \/DISCARD\/ :\n  {\n    *(.ARM.exidx*)\n    *(.note.gnu.build-id*)\n  }\n}\n\n","old_contents":"MEMORY\n{\n  RAM (xrw)     : ORIGIN = 0x20000000, LENGTH = 6K\n  FLASH (rx)    : ORIGIN = 0x08000000, LENGTH = 32K\n}\n\nstack_size = 1024;\nheap_size = 256;\n\n_stack_start = ORIGIN(RAM) + LENGTH(RAM);\n_stack_end = _stack_start - stack_size;\n_heap_end = _stack_end;\n\nENTRY(start);\n\nSECTIONS\n{\n  .vector_table ORIGIN(FLASH) :\n  {\n    LONG(_stack_start)\n    KEEP(*(.reset))\n    KEEP(*(.exceptions))\n  } > FLASH\n\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)\n    *(.text*)\n    *(.rodata)\n    *(.rodata*)\n    *(.glue_6)      \/* Glue arm to thumb code *\/\n    *(.glue_6t)     \/* Glue thumb to arm code *\/\n    . = ALIGN(4);\n    _etext = .;\n  } > FLASH\n\n  .ARM.extab : \/* debug info *\/\n  {\n    *(.ARM.extab*)\n  } > FLASH\n\n  \/* Used by startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data section *\/\n  .data : AT (_sidata)\n  {\n    . = ALIGN(4);\n    _sdata = .;     \/* Create global symbol at start of data *\/\n    *(.data)\n    *(.data*)\n\n    . = ALIGN(4);\n    _edata = .;\n  } > RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  { \n    \/* Used by startup to initialize .bss section *\/\n    _sbss = .;\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .; \/* Define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } > RAM\n\n  . = ALIGN(4);\n  .heap :\n  {\n    _heap_start = .;\n  } > RAM\n\n  \/DISCARD\/ :\n  {\n    *(.ARM.exidx*)\n    *(.note.gnu.build-id*)\n  }\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e3f79eca779504b2aa58617245bfb3415552667f","subject":"LD - space reserved for vectors in RAM","message":"LD - space reserved for vectors in RAM\n","repos":"kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS","old_file":"TARGET_Freescale\/TARGET_KL25Z\/TOOLCHAIN_GCC_ARM\/MKL25Z4.ld","new_file":"TARGET_Freescale\/TARGET_KL25Z\/TOOLCHAIN_GCC_ARM\/MKL25Z4.ld","new_contents":"\/*\n * KL25Z ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS\t(rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH_PROTECTION\t(rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410\n  RAM (rwx) : ORIGIN = 0x1FFFF000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        *(.text.Reset_Handler)\n        *(.text.System_Init)\n         . = ALIGN(4);\n    } > VECTORS\n\n    .flash_protect :\n    {\n        KEEP(*(.kinetis_flash_config_field))\n         . = ALIGN(4);\n    } > FLASH_PROTECTION\n\n    .text :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        \/* vectors come here, shift 0xc0 *\/\n        . = . + 0xC0;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/*\n * KL25Z ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS\t(rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH_PROTECTION\t(rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410\n  RAM (rwx) : ORIGIN = 0x1FFFF000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        *(.text.Reset_Handler)\n        *(.text.System_Init)\n         . = ALIGN(4);\n    } > VECTORS\n\n    .flash_protect :\n    {\n        KEEP(*(.kinetis_flash_config_field))\n         . = ALIGN(4);\n    } > FLASH_PROTECTION\n\n    .text :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2b56b86190a03fbe613b0d1f51ae454e3c4dc99f","subject":"arm: tz: secure_entry_functions.ld: Fix NSC_ALIGN redefinition","message":"arm: tz: secure_entry_functions.ld: Fix NSC_ALIGN redefinition\n\nAllow CONFIG_ARM_NSC_REGION_BASE_ADDRESS to override the nRF-specific\nlogic for alignment.\n\nFixes issue https:\/\/github.com\/zephyrproject-rtos\/zephyr\/issues\/27544\n\nSigned-off-by: \u00d8yvind R\u00f8nningstad <5f9e1eedbdafebd99226f1498f634e1047455d88@nordicsemi.no>\n","repos":"galak\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr","old_file":"arch\/arm\/core\/aarch32\/cortex_m\/tz\/secure_entry_functions.ld","new_file":"arch\/arm\/core\/aarch32\/cortex_m\/tz\/secure_entry_functions.ld","new_contents":"\/*\n * Copyright (c) 2019 Nordic Semiconductor ASA\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* nRF-specific defines. *\/\n#if defined(CONFIG_CPU_HAS_NRF_IDAU) && CONFIG_ARM_NSC_REGION_BASE_ADDRESS == 0\n\t\/* This SOC needs the NSC region to be at the end of an SPU region. *\/\n\t#define NSC_ALIGN \\\n\t\t. = ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE) \\\n\t\t\t- (1 << LOG2CEIL(__sg_size))\n\t#define NSC_ALIGN_END . = ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE)\n#endif \/* CONFIG_CPU_HAS_NRF_IDAU && CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n\n#ifndef NSC_ALIGN\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS *\/\n#endif \/* !NSC_ALIGN *\/\n\n#ifndef NSC_ALIGN_END\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n\/* nRF-specific ASSERT. *\/\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NRF_SG_START (__sg_start % CONFIG_NRF_SPU_FLASH_REGION_SIZE)\n\t#define NRF_SG_SIZE (CONFIG_NRF_SPU_FLASH_REGION_SIZE - NRF_SG_START)\n\tASSERT((__sg_size == 0)\n\t\t|| (((1 << LOG2CEIL(NRF_SG_SIZE)) == NRF_SG_SIZE) \/* Pow of 2 *\/\n\t\t\t&& (NRF_SG_SIZE >= 32)\n\t\t\t&& (NRF_SG_SIZE <= 4096)),\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n","old_contents":"\/*\n * Copyright (c) 2019 Nordic Semiconductor ASA\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* nRF-specific defines. *\/\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t\/* This SOC needs the NSC region to be at the end of an SPU region. *\/\n\t#define NSC_ALIGN \\\n\t\t. = ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE) \\\n\t\t\t- (1 << LOG2CEIL(__sg_size))\n\t#define NSC_ALIGN_END . = ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE)\n#endif \/* CONFIG_CPU_HAS_NRF_IDAU *\/\n\n\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#elif !defined(NSC_ALIGN)\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS *\/\n\n#ifndef NSC_ALIGN_END\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n\/* nRF-specific ASSERT. *\/\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NRF_SG_START (__sg_start % CONFIG_NRF_SPU_FLASH_REGION_SIZE)\n\t#define NRF_SG_SIZE (CONFIG_NRF_SPU_FLASH_REGION_SIZE - NRF_SG_START)\n\tASSERT((__sg_size == 0)\n\t\t|| (((1 << LOG2CEIL(NRF_SG_SIZE)) == NRF_SG_SIZE) \/* Pow of 2 *\/\n\t\t\t&& (NRF_SG_SIZE >= 32)\n\t\t\t&& (NRF_SG_SIZE <= 4096)),\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c6f4a970f1266ca62aedbe8b6220b419c85b8a9d","subject":"soc: intel_s1000: add _heap_sentry to linker script","message":"soc: intel_s1000: add _heap_sentry to linker script\n\nNewlib requires a _heap_sentry so we add it to the linker script,\nsimilar to what other xtensa linker scripts.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr","old_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <generated_dts_board.h>\n#include \"memory.h\"\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#define LPRAM_REGION lpram\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LPRAM_BASE,\n\tlen = LPRAM_SIZE\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-through\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-through\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_s1000 = 0x1212fff2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    . = CONFIG_TEXT_SECTION_OFFSET;\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LPRAM_REGION\n  _heap_sentry = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <generated_dts_board.h>\n#include \"memory.h\"\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#define LPRAM_REGION lpram\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LPRAM_BASE,\n\tlen = LPRAM_SIZE\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-through\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-through\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_s1000 = 0x1212fff2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    . = CONFIG_TEXT_SECTION_OFFSET;\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LPRAM_REGION\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8527d6472d5e834911d114cc7e0a755c481b6edd","subject":"STM32F4xxxG.ld: small improvements","message":"STM32F4xxxG.ld: small improvements\n\nRename memories to match the names in current manual (with exception of\nflash - \"rom\", and SRAM1 - \"ram\").","repos":"jasmin-j\/distortos,DISTORTEC\/distortos,jasmin-j\/distortos,CezaryGapinski\/distortos,jasmin-j\/distortos,DISTORTEC\/distortos,jasmin-j\/distortos,CezaryGapinski\/distortos,CezaryGapinski\/distortos,DISTORTEC\/distortos,CezaryGapinski\/distortos,DISTORTEC\/distortos,CezaryGapinski\/distortos,jasmin-j\/distortos","old_file":"source\/chip\/STMicroelectronics\/STM32F4\/STM32F4xxxG.ld","new_file":"source\/chip\/STMicroelectronics\/STM32F4\/STM32F4xxxG.ld","new_contents":"\/**\n * \\file\n * \\brief Linker script for STM32F4xxxG chip:\n * - 1MB flash;\n * - 112kB SRAM1;\n * - 16kB SRAM2;\n * - 64kB CCM;\n * - 4kB BKPSRAM;\n *\n * \\author Copyright (C) 2014-2015 Kamil Szczygiel http:\/\/www.distortec.com http:\/\/www.freddiechopin.info\n *\n * \\par License\n * This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of the MPL was not\n * distributed with this file, You can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/.\n *\n * \\date 2015-08-27\n *\/\n\nSEARCH_DIR(.);\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| available memories definitions\n+---------------------------------------------------------------------------------------------------------------------*\/\n\nMEMORY\n{\n\trom (rx)\t\t: org = 0x08000000, len = 1M\n\tram (rwx)\t\t: org = 0x20000000, len = 112k\n\tsram2 (rwx)\t\t: org = 0x2001C000, len = 16k\n\tccm (rw)\t\t: org = 0x10000000, len = 64k\n\tbkpsram (rwx)\t: org = 0x40024000, len = 4k\n}\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| stacks sizes\n+---------------------------------------------------------------------------------------------------------------------*\/\n\n\/* Handler mode (core exceptions \/ interrupts) can use only main stack *\/\n\/* Thread mode can use main stack (default) or process stack - selected in CONTROL special register *\/\n\n__main_stack_size = 2k;\n__process_stack_size = 2k;\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| include generic linker script\n+---------------------------------------------------------------------------------------------------------------------*\/\n\nINCLUDE ARMv7-M.ld\n","old_contents":"\/**\n * \\file\n * \\brief Linker script for STM32F4xxxG chip (1MB Flash, 112kB SRAM, 16kB aux SRAM, 64kB CCM RAM and 4kB backup SRAM).\n * Only main block o SRAM (112kB) is used.\n *\n * \\author Copyright (C) 2014 Kamil Szczygiel http:\/\/www.distortec.com http:\/\/www.freddiechopin.info\n *\n * \\par License\n * This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of the MPL was not\n * distributed with this file, You can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/.\n *\n * \\date 2014-07-21\n *\/\n\nSEARCH_DIR(.);\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| available memories definitions\n+---------------------------------------------------------------------------------------------------------------------*\/\n\nMEMORY\n{\n\trom (rx)\t\t: org = 0x08000000, len = 1M\n\tram (rwx)\t\t: org = 0x20000000, len = 112k\n\taux_ram (rwx)\t: org = 0x2001C000, len = 16k\n\tccm_ram (rw)\t: org = 0x10000000, len = 64k\n\tbkp_ram (rwx)\t: org = 0x40024000, len = 4k\n}\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| stacks sizes\n+---------------------------------------------------------------------------------------------------------------------*\/\n\n\/* Handler mode (core exceptions \/ interrupts) can use only main stack *\/\n\/* Thread mode can use main stack (default) or process stack - selected in CONTROL special register *\/\n\n__main_stack_size = 2k;\n__process_stack_size = 2k;\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| include generic linker script\n+---------------------------------------------------------------------------------------------------------------------*\/\n\nINCLUDE ARMv7-M.ld\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"17c45e3e086ec9669954ff8e26ecc7812d2ac7eb","subject":"correct the linker configuration file about RAM size (excluding CCM); should be 128KB not 192KB.","message":"correct the linker configuration file about RAM size (excluding CCM); should be 128KB not 192KB.\n","repos":"kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos","old_file":"ld\/STM32F407VG.ld","new_file":"ld\/STM32F407VG.ld","new_contents":"\/*\n * PackageLicenseDeclared: Apache-2.0\n * Copyright (c) 2015 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x08000000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x08000400, LENGTH = 1024k - 0x400\n  CCM (rwx)             : ORIGIN = 0x10000000, LENGTH = 64K\n\n  \/*\n   * Refer RM0090: Table 61. Vector table for STM32F405xx\/07xx and STM32F415xx\/17xx.\n   *  4 * (16 + 82) = 392 = 0x188\n   *\/\n  RAM (rwx)             : ORIGIN = 0x20000188, LENGTH = 128k - 0x188\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.isr_vector))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        . = ALIGN(32);\n        __uvisor_bss_end = .;\n    } > CCM\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += 0x8000 - (. - __StackLimit);\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assertions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .bss (NOLOAD):\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM) + LENGTH(RAM) - .);\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n}\n","old_contents":"\/*\n * PackageLicenseDeclared: Apache-2.0\n * Copyright (c) 2015 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x08000000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x08000400, LENGTH = 1024k - 0x400\n  CCM (rwx)             : ORIGIN = 0x10000000, LENGTH = 64K\n\n  \/*\n   * Refer RM0090: Table 61. Vector table for STM32F405xx\/07xx and STM32F415xx\/17xx.\n   *  4 * (16 + 82) = 392 = 0x188\n   *\/\n  RAM (rwx)             : ORIGIN = 0x20000188, LENGTH = 192k - 0x188\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.isr_vector))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        . = ALIGN(32);\n        __uvisor_bss_end = .;\n    } > CCM\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += 0x8000 - (. - __StackLimit);\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assertions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .bss (NOLOAD):\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM) + LENGTH(RAM) - .);\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9458c7a8b42ed42ddb68ecbae2028109fdf234be","subject":"Removes obsolete linker script.","message":"Removes obsolete linker script.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/microchip-pic32mx-generic\/misc\/target_no_bootloader.ld","new_file":"boards\/microchip-pic32mx-generic\/misc\/target_no_bootloader.ld","new_contents":"","old_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n**\r\n** This file was adjusted for memory regions of the PIC32MX530F128 device which\r\n** has 128+3K flash and 16K ram.  \r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 16K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0x9D000000, LENGTH = 128K \/* to BD020000-1, bootloader gets first 128k *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0x9FC00000, LENGTH = 0x180 \/* The beginning of the interrupt vector table is empty. *\/\r\n  PIC32MX_flash_boot_remaining (rx): ORIGIN = 0x9FC00A00, LENGTH = 3K-0x10-0xA00 \/* Skipped flash_cfg rgister and 0xa00 at the beginning for the interupt vector table. NOTE(bracz): also one debug page might need to be reserved here, which would directly prevent us from placing the interrupt vector table here. -- need 2K + 1k debug. Maybe the vector table could be trimmed. Calculations give that 48 vectors would fit. *\/\r\n  \/* This is for PIC32MX795, where we have 12K boot ROM *\/\r\n  PIC32MX_flash_cfg  (r!x): ORIGIN = 0x9FC02FF0, LENGTH = 0x0010\r\n  \/* This is for the MX530 where we only have 3K boot ROM \r\n  PIC32MX_flash_cfg  (r!x): ORIGIN = 0x9FC00BF0, LENGTH = 0x0010 *\/\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** Located at the beginning of bootflash for now.\r\n** 0xBFC00000 + 0x200 + (64 vectors * x20)) = 0xBFC00A00\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0x9FC00000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\n\/* NOT NEEDED -- we have our own entry routine, not using cs3's\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) *\/\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 2k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** PIC32MX configuration registers\r\n  *\/\r\n  .PIC32MX_cfg_init :\r\n  {\r\n    KEEP(*(.PIC32MX_cfg_init))\r\n  } >PIC32MX_flash_cfg \/*AT>PIC32MX_physical_flash_cfg*\/\r\n  \/* Assert exactly 4 words are placed in configuration area *\/\r\n  \/* Note: terminating semicolon causes syntax error for ASSERT in following line ! *\/\r\n\r\n  ASSERT (SIZEOF(.PIC32MX_cfg_init) == 0x10, \"PIC32MX configuration register set must be 4 words long\")\r\n\r\n  \/*\r\n  ** First thing in boot flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n    \/*\r\n    ** While the PIC32MX is in Bootstrap mode, all interrupts are disabled\r\n    ** and all general exceptions are redirected to address 0xBFC00380\r\n    . = __cs3_reset_PIC32MX + 0x0380;\r\n    KEEP(*(.bev_handler)) \/* optional boot exception handler *\/\r\n    \r\n\r\n  } >PIC32MX_flash_boot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; DRN updated this; seems correct...  bracz: not really. *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"4a07f8303688838f3ce460a2f12dae3db1fe83fa","subject":"IO memory mapping","message":"IO memory mapping\n","repos":"hackndev\/zinc,ntwyman\/zinc,mcoffin\/zinc,hackndev\/zinc,richo\/zinc,hackndev\/zinc,hackndev\/zinc,ntwyman\/zinc,richo\/zinc,ntwyman\/zinc,mcoffin\/zinc,mcoffin\/zinc,mcoffin\/zinc,richo\/zinc,richo\/zinc,mcoffin\/zinc,richo\/zinc,ntwyman\/zinc,hackndev\/zinc,ntwyman\/zinc","old_file":"src\/hal\/stm32f1\/iomem.ld","new_file":"src\/hal\/stm32f1\/iomem.ld","new_contents":"stm32l1_iomem_PWR   = 0x40007000;\n\nstm32l1_iomem_FLASH = 0x40022000;\nstm32l1_iomem_RCC   = 0x40021000;\n\nstm32l1_iomem_GPIOA = 0x40010800;\nstm32l1_iomem_GPIOB = 0x40010C00;\nstm32l1_iomem_GPIOC = 0x40011000;\nstm32l1_iomem_GPIOD = 0x40011400;\nstm32l1_iomem_GPIOE = 0x40011800;\nstm32l1_iomem_GPIOF = 0x40011C00;\nstm32l1_iomem_GPIOG = 0x40012000;\n\nstm32f1_iomem_TIM1  = 0x40012C00;\nstm32l1_iomem_TIM2  = 0x40000000;\nstm32f1_iomem_TIM3  = 0x40000400;\nstm32f1_iomem_TIM4  = 0x40000800;\nstm32f1_iomem_TIM5  = 0x40000C00;\nstm32f1_iomem_TIM6  = 0x40001000;\nstm32f1_iomem_TIM7  = 0x40001400;\nstm32f1_iomem_TIM8  = 0x40013400;\nstm32f1_iomem_TIM9  = 0x40014C00;\nstm32f1_iomem_TIM10 = 0x40015000;\nstm32f1_iomem_TIM11 = 0x40015400;\nstm32f1_iomem_TIM12 = 0x40001800;\nstm32f1_iomem_TIM13 = 0x40001C00;\nstm32f1_iomem_TIM14 = 0x40002000;\n\nstm32l1_iomem_USART1   = 0x40013800;\nstm32l1_iomem_USART2   = 0x40004400;\nstm32l1_iomem_USART3   = 0x40004800;\nstm32l1_iomem_UART4    = 0x40004C00;\nstm32l1_iomem_UART5    = 0x40005000;\n\nstm32l1_iomem_SPI1     = 0x40013000;\nstm32l1_iomem_SPI2     = 0x40003800;\nstm32l1_iomem_SPI3     = 0x40003C00;\n","old_contents":"stm32l1_iomem_PWR   = 0x40007000;\n\nstm32l1_iomem_FLASH = 0x40023C00;\nstm32l1_iomem_RCC   = 0x40023800;\n\nstm32l1_iomem_GPIOA = 0x40020000;\nstm32l1_iomem_GPIOB = 0x40020400;\nstm32l1_iomem_GPIOC = 0x40020800;\nstm32l1_iomem_GPIOD = 0x40020c00;\nstm32l1_iomem_GPIOE = 0x40021000;\nstm32l1_iomem_GPIOF = 0x40021800;\nstm32l1_iomem_GPIOG = 0x40021C00;\nstm32l1_iomem_GPIOH = 0x40021400;\n\nstm32l1_iomem_TIM2  = 0x40000000;\n\nstm32l1_iomem_USART1   = 0x40013800;\nstm32l1_iomem_USART2   = 0x40004400;\nstm32l1_iomem_USART3   = 0x40004800;\nstm32l1_iomem_UART4    = 0x40004C00;\nstm32l1_iomem_UART5    = 0x40005000;\n\nstm32l1_iomem_SPI1     = 0x40013000;\nstm32l1_iomem_SPI2     = 0x40003800;\nstm32l1_iomem_SPI3     = 0x40003C00;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"59f25fb7a541c6099ea40f74299a2e240c4e90aa","subject":"Update to S140","message":"Update to S140","repos":"adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/nrf\/boards\/feather52840\/bluefruit_nrf52840_s140_6.0.0.ld","new_file":"ports\/nrf\/boards\/feather52840\/bluefruit_nrf52840_s140_6.0.0.ld","new_contents":"\/*\n    GNU linker script for NRF52 w\/S140 6.0.0 SoftDevice\n\n    MEMORY MAP\n    ------------------------------------------------------------------------\n    START ADDR  END ADDR   SIZE    DESCRIPTION\n    ----------  ---------- ------- -----------------------------------------\n    0x000FF000..0x000FFFFF (  4KB) Bootloader Settings\n    0x000FE000..0x000FEFFF (  4KB) Master Boot Record Params\n    0x000F4000..0x000FDFFF ( 40KB) Serial + OTA Bootloader\n    \n    0x000F3000..0x000F3FFF ( 4KB ) Private Config Data (Bonding, Keys, etc.)\n    0x000F2000..0x000F2FFF ( 4KB ) User NVM data\n    0x000D9000..0x000F1FFF ( 100KB) User Filesystem\n\n    0x00025000..0x000D8FFF (720KB) Application Code (including ISR vector)\n    0x00001000..0x00024FFF (144KB) SoftDevice\n    0x00000000..0x00000FFF   (4KB) Master Boot Record\n*\/\n\n\/* Specify the memory areas (S140 6.0.0) *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000\n\n    FLASH_ISR (rx)  : ORIGIN = 0x00025000, LENGTH = 0x001000\n    FLASH_TEXT (rx) : ORIGIN = 0x00026000, LENGTH = 0x0B3000\n    FLASH_FATFS (r) : ORIGIN = 0x000D9000, LENGTH = 0x019000\n    \n    \/* 0x2000000 - RAM:ORGIGIN is reserved for Softdevice *\/\n    RAM (xrw)       : ORIGIN = 0x20004000, LENGTH = 0x20040000 - 0x20004000\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20007000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52 w\/ s132 5.0.0 SoftDevice\n\n    MEMORY MAP\n    ------------------------------------------------------------------------\n    START ADDR  END ADDR   SIZE    DESCRIPTION\n    ----------  ---------- ------- -----------------------------------------\n    0x000FF000..0x000FFFFF (  4KB) Bootloader Settings\n    0x000FE000..0x000FEFFF (  4KB) Master Boot Record Params\n    0x000F4000..0x000FDFFF ( 40KB) Serial + OTA Bootloader\n    \n    0x000F3000..0x000F3FFF ( 4KB ) Private Config Data (Bonding, Keys, etc.)\n    0x000F2000..0x000F2FFF ( 4KB ) User NVM data\n    0x000D9000..0x000F1FFF ( 100KB) User Filesystem\n\n    0x00025000..0x000D8FFF (720KB) Application Code (including ISR vector)\n    0x00001000..0x00024FFF (144KB) SoftDevice\n    0x00000000..0x00000FFF   (4KB) Master Boot Record\n*\/\n\n\/* Specify the memory areas (S132 5.0.0) *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000\n\n    FLASH_ISR (rx)  : ORIGIN = 0x00025000, LENGTH = 0x001000\n    FLASH_TEXT (rx) : ORIGIN = 0x00026000, LENGTH = 0x0B3000\n    FLASH_FATFS (r) : ORIGIN = 0x000D9000, LENGTH = 0x019000\n    \n    \/* 0x2000000 - RAM:ORGIGIN is reserved for Softdevice *\/\n    RAM (xrw)       : ORIGIN = 0x20004000, LENGTH = 0x20040000 - 0x20004000\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 0 \/*16K Circuit Python use static variable for HEAP *\/;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20007000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3d24040ac68b1db8981888b24a12f3248bd6ef33","subject":"updated linker script","message":"updated linker script\n","repos":"stateos\/StateOS,stateos\/StateOS,stateos\/StateOS","old_file":"startup\/STM32F4\/GNUCC\/script.ld","new_file":"startup\/STM32F4\/GNUCC\/script.ld","new_contents":"\/*******************************************************************************\n@file     stm32f4xx.ld\n@author   Rajmund Szymanski\n@date     28.02.2017\n@brief    Linker script for STM32F407VG device with 1024KB FLASH and 192KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 1024k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   64k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  128k\n\/*\tAUX (rwx) : ORIGIN = 0x2001C000, LENGTH =   16k\n*\/\tBKP (rwx) : ORIGIN = 0x40024000, LENGTH =    4k\n}\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__heap_start = LOADADDR(.proc_stack);\n\t__heap_end   = __ram_end - __proc_stack_size;\n\n\t__proc_stack_start = __heap_end;\n\t__proc_stack_end   = __ram_end;\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n\tPROVIDE(__process_stack_end   = __proc_stack_end);\n}\n","old_contents":"\/*******************************************************************************\n@file     stm32f4xx.ld\n@author   Rajmund Szymanski\n@date     02.01.2017\n@brief    Linker script for STM32F407VG device with 1024KB FLASH and 192KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 1024k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   64k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  128k\n\/*\tAUX (rwx) : ORIGIN = 0x2001C000, LENGTH =   16k\n*\/\tBKP (rwx) : ORIGIN = 0x40024000, LENGTH =    4k\n}\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t. = ABSOLUTE(__ram_end - __proc_stack_size);\n\t\t__heap_end = .;\n\t} > RAM\n\n\t__heap_size = SIZEOF(.heap);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c1a4a902d4aa98bca513bbf7871f555ddb7c5e63","subject":"Switches async_blink to be built for use with bootloader.","message":"Switches async_blink to be built for use with bootloader.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"applications\/async_blink\/targets\/nonos.xtensa.esp8266-32mbit\/target.ld","new_file":"applications\/async_blink\/targets\/nonos.xtensa.esp8266-32mbit\/target.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"321aa567d6a1496625e9f8e1fd8270196a36ec13","subject":"kinetis: Memory segment attribute fixes","message":"kinetis: Memory segment attribute fixes\n\nvectors and flashsec memory segments will not be considered for orphan\nsections if rx is only given for the rom segment.\n","repos":"authmillenon\/RIOT,A-Paul\/RIOT,avmelnikoff\/RIOT,rfuentess\/RIOT,neiljay\/RIOT,yogo1212\/RIOT,kbumsik\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,x3ro\/RIOT,kaspar030\/RIOT,mtausig\/RIOT,basilfx\/RIOT,aeneby\/RIOT,cladmi\/RIOT,basilfx\/RIOT,x3ro\/RIOT,OlegHahm\/RIOT,mtausig\/RIOT,kaspar030\/RIOT,kbumsik\/RIOT,cladmi\/RIOT,x3ro\/RIOT,rfuentess\/RIOT,authmillenon\/RIOT,josephnoir\/RIOT,OTAkeys\/RIOT,rfuentess\/RIOT,yogo1212\/RIOT,biboc\/RIOT,yogo1212\/RIOT,yogo1212\/RIOT,mtausig\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,kbumsik\/RIOT,ant9000\/RIOT,josephnoir\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,authmillenon\/RIOT,toonst\/RIOT,RIOT-OS\/RIOT,rfuentess\/RIOT,biboc\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,lazytech-org\/RIOT,kaspar030\/RIOT,basilfx\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,gebart\/RIOT,mfrey\/RIOT,mtausig\/RIOT,yogo1212\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,A-Paul\/RIOT,biboc\/RIOT,kYc0o\/RIOT,A-Paul\/RIOT,toonst\/RIOT,rfuentess\/RIOT,kbumsik\/RIOT,toonst\/RIOT,avmelnikoff\/RIOT,mfrey\/RIOT,mfrey\/RIOT,gebart\/RIOT,kYc0o\/RIOT,BytesGalore\/RIOT,ant9000\/RIOT,avmelnikoff\/RIOT,lazytech-org\/RIOT,kYc0o\/RIOT,aeneby\/RIOT,kYc0o\/RIOT,smlng\/RIOT,mfrey\/RIOT,neiljay\/RIOT,aeneby\/RIOT,authmillenon\/RIOT,toonst\/RIOT,OTAkeys\/RIOT,biboc\/RIOT,BytesGalore\/RIOT,BytesGalore\/RIOT,neiljay\/RIOT,lazytech-org\/RIOT,cladmi\/RIOT,mtausig\/RIOT,x3ro\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,OTAkeys\/RIOT,smlng\/RIOT,miri64\/RIOT,toonst\/RIOT,A-Paul\/RIOT,smlng\/RIOT,BytesGalore\/RIOT,miri64\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,BytesGalore\/RIOT,aeneby\/RIOT,josephnoir\/RIOT,avmelnikoff\/RIOT,yogo1212\/RIOT,gebart\/RIOT,biboc\/RIOT,basilfx\/RIOT,neiljay\/RIOT,neiljay\/RIOT,lazytech-org\/RIOT,cladmi\/RIOT,ant9000\/RIOT,josephnoir\/RIOT,lazytech-org\/RIOT,jasonatran\/RIOT,kbumsik\/RIOT,authmillenon\/RIOT,miri64\/RIOT,smlng\/RIOT,avmelnikoff\/RIOT,josephnoir\/RIOT,x3ro\/RIOT,mfrey\/RIOT,gebart\/RIOT,A-Paul\/RIOT,jasonatran\/RIOT,smlng\/RIOT,aeneby\/RIOT,OTAkeys\/RIOT,gebart\/RIOT,cladmi\/RIOT","old_file":"cpu\/kinetis\/ldscripts\/kinetis.ld","new_file":"cpu\/kinetis\/ldscripts\/kinetis.ld","new_contents":"\/*\n * Copyright (C) 2015 PHYTEC Messtechnik GmbH\n * Copyright (C) 2015-2017 Eistec AB\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_kinetis\n * @{\n *\n * @file\n * @brief           Sections definitions for the Freescale Kinetis MCUs\n *\n * @author          Johann Fischer <j.fischer@phytec.de>\n * @author          Joakim Nohlg\u00e5rd <joakim.nohlgard@eistec.se>\n *\n * @}\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\n_vectors_length = 0x400;\n_flashsec_length = 0x10;\n\nMEMORY\n{\n    vectors    : ORIGIN = _rom_start_addr, LENGTH = _vectors_length\n    flashsec   : ORIGIN = _rom_start_addr + _vectors_length, LENGTH = _flashsec_length\n    rom (rx)   : ORIGIN = _rom_start_addr + _vectors_length + _flashsec_length, LENGTH = _rom_length - (_vectors_length + _flashsec_length)\n    ram (!rx)  : ORIGIN = _ram_start_addr, LENGTH = _ram_length\n}\n\nSECTIONS\n{\n    \/* Interrupt vectors 0x00-0x3ff. *\/\n    .vector :\n    {\n        _isr_vectors = .;\n        KEEP(*(SORT(.vector*)))\n    } > vectors\n    ASSERT (SIZEOF(.vector) == 0x400, \"Interrupt vector table of invalid size.\")\n    ASSERT (ADDR(.vector) == 0x00000000, \"Interrupt vector table at invalid location (linker-script error?)\")\n    ASSERT (LOADADDR(.vector) == 0x00000000, \"Interrupt vector table at invalid location (linker-script error?)\")\n\n    \/* Flash configuration field, very important in order to not accidentally lock the device *\/\n    \/* Flash configuration field 0x400-0x40f. *\/\n    .fcfield :\n    {\n        . = ALIGN(4);\n        KEEP(*(.fcfield))\n        . = ALIGN(4);\n    } > flashsec\n    ASSERT (SIZEOF(.fcfield) == 0x10, \"Flash configuration field of invalid size (linker-script error?)\")\n    ASSERT (ADDR(.fcfield) == 0x400, \"Flash configuration field at invalid position (linker-script error?)\")\n    ASSERT (LOADADDR(.fcfield) == 0x400, \"Flash configuration field at invalid position (linker-script error?)\")\n}\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2015 PHYTEC Messtechnik GmbH\n * Copyright (C) 2015-2017 Eistec AB\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_kinetis\n * @{\n *\n * @file\n * @brief           Sections definitions for the Freescale Kinetis MCUs\n *\n * @author          Johann Fischer <j.fischer@phytec.de>\n * @author          Joakim Nohlg\u00e5rd <joakim.nohlgard@eistec.se>\n *\n * @}\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\n_vectors_length = 0x400;\n_flashsec_length = 0x10;\n\nMEMORY\n{\n    vectors (rx)   : ORIGIN = _rom_start_addr, LENGTH = _vectors_length\n    flashsec (rx)  : ORIGIN = _rom_start_addr + _vectors_length, LENGTH = _flashsec_length\n    rom (rx)       : ORIGIN = _rom_start_addr + _vectors_length + _flashsec_length, LENGTH = _rom_length - (_vectors_length + _flashsec_length)\n    ram (rwx)      : ORIGIN = _ram_start_addr, LENGTH = _ram_length\n}\n\nSECTIONS\n{\n    \/* Interrupt vectors 0x00-0x3ff. *\/\n    .vector :\n    {\n        _isr_vectors = .;\n        KEEP(*(SORT(.vector*)))\n    } > vectors\n    ASSERT (SIZEOF(.vector) == 0x400, \"Interrupt vector table of invalid size.\")\n    ASSERT (ADDR(.vector) == 0x00000000, \"Interrupt vector table at invalid location (linker-script error?)\")\n    ASSERT (LOADADDR(.vector) == 0x00000000, \"Interrupt vector table at invalid location (linker-script error?)\")\n\n    \/* Flash configuration field, very important in order to not accidentally lock the device *\/\n    \/* Flash configuration field 0x400-0x40f. *\/\n    .fcfield :\n    {\n        . = ALIGN(4);\n        KEEP(*(.fcfield))\n        . = ALIGN(4);\n    } > flashsec\n    ASSERT (SIZEOF(.fcfield) == 0x10, \"Flash configuration field of invalid size (linker-script error?)\")\n    ASSERT (ADDR(.fcfield) == 0x400, \"Flash configuration field at invalid position (linker-script error?)\")\n    ASSERT (LOADADDR(.fcfield) == 0x400, \"Flash configuration field at invalid position (linker-script error?)\")\n}\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"d76904b002f399f8199ace5ad29a7bd2053538e3","subject":"Remove trailing spaces.","message":"Remove trailing spaces.\n","repos":"ak-fau\/fpga-cyclone_iv,ak-fau\/fpga-cyclone_iv","old_file":"sw\/common\/test.ld","new_file":"sw\/common\/test.ld","new_contents":"\/*======================================================================*\/\n\/* Proxy kernel linker script                                           *\/\n\/*======================================================================*\/\n\/* This is the linker script used when building the proxy kernel. *\/\n\n\/*----------------------------------------------------------------------*\/\n\/* Setup                                                                *\/\n\/*----------------------------------------------------------------------*\/\n\n\/* The OUTPUT_ARCH command specifies the machine architecture where the\n   argument is one of the names used in the BFD library. More\n   specifically one of the entires in bfd\/cpu-mips.c *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\n\/*----------------------------------------------------------------------*\/\n\/* Sections                                                             *\/\n\/*----------------------------------------------------------------------*\/\n\nSECTIONS\n{\n\n  \/* text: test code section *\/\n  . = 0x100;\n  .text :\n  {\n    crt.o(.text)\n    *(.text)\n  }\n\n  \/* data segment *\/\n  .data : { *(.data) }\n\n  .sdata : {\n    _gp = . + 0x800;\n    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n  }\n\n  \/* bss segment *\/\n  .sbss : {\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n  }\n  .bss : { *(.bss) }\n\n  \/* thread-local data segment *\/\n  .tdata :\n  {\n    _tls_data = .;\n    crt.o(.tdata.begin)\n    *(.tdata)\n    crt.o(.tdata.end)\n  }\n  .tbss :\n  {\n    *(.tbss)\n    crt.o(.tbss.end)\n  }\n\n  \/* End of uninitalized data segement *\/\n  _end = .;\n}\n","old_contents":"\/*======================================================================*\/\n\/* Proxy kernel linker script                                           *\/\n\/*======================================================================*\/\n\/* This is the linker script used when building the proxy kernel. *\/\n\n\/*----------------------------------------------------------------------*\/\n\/* Setup                                                                *\/\n\/*----------------------------------------------------------------------*\/\n\n\/* The OUTPUT_ARCH command specifies the machine architecture where the\n   argument is one of the names used in the BFD library. More\n   specifically one of the entires in bfd\/cpu-mips.c *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\n\/*----------------------------------------------------------------------*\/\n\/* Sections                                                             *\/\n\/*----------------------------------------------------------------------*\/\n\nSECTIONS\n{\n\n  \/* text: test code section *\/\n  . = 0x100;\n  .text : \n  {\n    crt.o(.text)\n    *(.text)\n  }\n\n  \/* data segment *\/\n  .data : { *(.data) }\n\n  .sdata : {\n    _gp = . + 0x800;\n    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n  }\n\n  \/* bss segment *\/\n  .sbss : {\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n  }\n  .bss : { *(.bss) }\n\n  \/* thread-local data segment *\/\n  .tdata :\n  {\n    _tls_data = .;\n    crt.o(.tdata.begin)\n    *(.tdata)\n    crt.o(.tdata.end)\n  }\n  .tbss :\n  {\n    *(.tbss)\n    crt.o(.tbss.end)\n  }\n\n  \/* End of uninitalized data segement *\/\n  _end = .;\n}\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"9329d73d87257b0e299063aec481dd0d3d1e9cc0","subject":"Leave enough space at the start of the RAM block for the dynamic vectors.","message":"Leave enough space at the start of the RAM block for the dynamic\nvectors.\n","repos":"pi19404\/mbed,YarivCol\/mbed-os,Tiryoh\/mbed,struempelix\/mbed,nvlsianpu\/mbed,logost\/mbed,nabilbendafi\/mbed,monkiineko\/mbed-os,nvlsianpu\/mbed,masaohamanaka\/mbed,j-greffe\/mbed-os,adamgreen\/mbed,tung7970\/mbed-os,svastm\/mbed,karsev\/mbed-os,betzw\/mbed-os,fvincenzo\/mbed-os,mazimkhan\/mbed-os,fvincenzo\/mbed-os,GustavWi\/mbed,jeremybrodt\/mbed,CalSol\/mbed,Archcady\/mbed-os,mbedmicro\/mbed,kl-cruz\/mbed-os,kl-cruz\/mbed-os,tung7970\/mbed-os,bulislaw\/mbed-os,svastm\/mbed,al177\/mbed,mmorenobarm\/mbed-os,xcrespo\/mbed,mikaleppanen\/mbed-os,EmuxEvans\/mbed,nRFMesh\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,getopenmono\/mbed,arostm\/mbed-os,alertby\/mbed,jpbrucker\/mbed,naves-thiago\/mbed-midi,pi19404\/mbed,RonEld\/mbed,pi19404\/mbed,JasonHow44\/mbed,dbestm\/mbed,fvincenzo\/mbed-os,brstew\/MBED-BUILD,kjbracey-arm\/mbed,larks\/mbed,rosterloh\/mbed,tung7970\/mbed-os-1,mbedmicro\/mbed,ryankurte\/mbed-os,pedromes\/mbed,xcrespo\/mbed,pi19404\/mbed,masaohamanaka\/mbed,arostm\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,ryankurte\/mbed-os,RonEld\/mbed,fahhem\/mbed-os,kl-cruz\/mbed-os,ARM-software\/mbed-beetle,screamerbg\/mbed,svogl\/mbed-os,infinnovation\/mbed-os,dbestm\/mbed,logost\/mbed,monkiineko\/mbed-os,betzw\/mbed-os,EmuxEvans\/mbed,catiedev\/mbed-os,karsev\/mbed-os,bremoran\/mbed-drivers,andreaslarssonublox\/mbed,struempelix\/mbed,cvtsi2sd\/mbed-os,bcostm\/mbed-os,Willem23\/mbed,jpbrucker\/mbed,monkiineko\/mbed-os,getopenmono\/mbed,rgrover\/mbed,Sweet-Peas\/mbed,svastm\/mbed,mazimkhan\/mbed-os,sg-\/mbed-drivers,dbestm\/mbed,naves-thiago\/mbed-midi,NitinBhaskar\/mbed,HeadsUpDisplayInc\/mbed,Marcomissyou\/mbed,HeadsUpDisplayInc\/mbed,hwfwgrp\/mbed,Marcomissyou\/mbed,nabilbendafi\/mbed,bentwire\/mbed,bulislaw\/mbed-os,tung7970\/mbed-os-1,RonEld\/mbed,theotherjimmy\/mbed,pradeep-gr\/mbed-os5-onsemi,CalSol\/mbed,mnlipp\/mbed,mikaleppanen\/mbed-os,hwfwgrp\/mbed,Sweet-Peas\/mbed,dbestm\/mbed,mnlipp\/mbed,mazimkhan\/mbed-os,NXPmicro\/mbed,sam-geek\/mbed,Timmmm\/mbed,adustm\/mbed,nabilbendafi\/mbed,adamgreen\/mbed,screamerbg\/mbed,andcor02\/mbed-os,j-greffe\/mbed-os,Shengliang\/mbed,c1728p9\/mbed-os,masaohamanaka\/mbed,j-greffe\/mbed-os,struempelix\/mbed,logost\/mbed,pbrook\/mbed,jamesadevine\/mbed,brstew\/MBED-BUILD,arostm\/mbed-os,ARM-software\/mbed-beetle,cvtsi2sd\/mbed-os,jrjang\/mbed,fanghuaqi\/mbed,struempelix\/mbed,fahhem\/mbed-os,andreaslarssonublox\/mbed,karsev\/mbed-os,jferreir\/mbed,EmuxEvans\/mbed,andcor02\/mbed-os,wodji\/mbed,tung7970\/mbed-os-1,jrjang\/mbed,Willem23\/mbed,ban4jp\/mbed,adamgreen\/mbed,DanKupiniak\/mbed,larks\/mbed,wodji\/mbed,jferreir\/mbed,pbrook\/mbed,infinnovation\/mbed-os,ARM-software\/mbed-beetle,Sweet-Peas\/mbed,JasonHow44\/mbed,xcrespo\/mbed,mazimkhan\/mbed-os,rgrover\/mbed,0xc0170\/mbed-drivers,maximmbed\/mbed,jeremybrodt\/mbed,pi19404\/mbed,pradeep-gr\/mbed-os5-onsemi,GustavWi\/mbed,FranklyDev\/mbed,maximmbed\/mbed,jferreir\/mbed,jpbrucker\/mbed,larks\/mbed,adamgreen\/mbed,mmorenobarm\/mbed-os,pbrook\/mbed,maximmbed\/mbed,logost\/mbed,bulislaw\/mbed-os,fanghuaqi\/mbed,bikeNomad\/mbed,Archcady\/mbed-os,CalSol\/mbed,c1728p9\/mbed-os,adustm\/mbed,arostm\/mbed-os,Marcomissyou\/mbed,K4zuki\/mbed,K4zuki\/mbed,Archcady\/mbed-os,JasonHow44\/mbed,svogl\/mbed-os,YarivCol\/mbed-os,FranklyDev\/mbed,andcor02\/mbed-os,ryankurte\/mbed-os,nvlsianpu\/mbed,bcostm\/mbed-os,nRFMesh\/mbed-os,adustm\/mbed,YarivCol\/mbed-os,larks\/mbed,brstew\/MBED-BUILD,mikaleppanen\/mbed-os,pedromes\/mbed,NordicSemiconductor\/mbed,andreaslarssonublox\/mbed,svogl\/mbed-os,nRFMesh\/mbed-os,bcostm\/mbed-os,alertby\/mbed,autopulated\/mbed,j-greffe\/mbed-os,autopulated\/mbed,jeremybrodt\/mbed,iriark01\/mbed-drivers,NXPmicro\/mbed,Timmmm\/mbed,rosterloh\/mbed,nRFMesh\/mbed-os,cvtsi2sd\/mbed-os,autopulated\/mbed,Sweet-Peas\/mbed,jpbrucker\/mbed,GustavWi\/mbed,monkiineko\/mbed-os,EmuxEvans\/mbed,catiedev\/mbed-os,jrjang\/mbed,catiedev\/mbed-os,screamerbg\/mbed,bentwire\/mbed,mikaleppanen\/mbed-os,catiedev\/mbed-os,NXPmicro\/mbed,jrjang\/mbed,fpiot\/mbed-ats,tung7970\/mbed-os,wodji\/mbed,NXPmicro\/mbed,bikeNomad\/mbed,YarivCol\/mbed-os,ban4jp\/mbed,HeadsUpDisplayInc\/mbed,YarivCol\/mbed-os,cvtsi2sd\/mbed-os,getopenmono\/mbed,al177\/mbed,fvincenzo\/mbed-os,kjbracey-arm\/mbed,K4zuki\/mbed,jrjang\/mbed,bentwire\/mbed,jferreir\/mbed,Shengliang\/mbed,nabilbendafi\/mbed,masaohamanaka\/mbed,fahhem\/mbed-os,kl-cruz\/mbed-os,kpurusho\/mbed,EmuxEvans\/mbed,ban4jp\/mbed,j-greffe\/mbed-os,xcrespo\/mbed,c1728p9\/mbed-os,sg-\/mbed-drivers,alertby\/mbed,bcostm\/mbed-os,devanlai\/mbed,Archcady\/mbed-os,theotherjimmy\/mbed,maximmbed\/mbed,arostm\/mbed-os,nRFMesh\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,netzimme\/mbed-os,adustm\/mbed,Timmmm\/mbed,tung7970\/mbed-os-1,fpiot\/mbed-ats,ryankurte\/mbed-os,karsev\/mbed-os,cvtsi2sd\/mbed-os,NitinBhaskar\/mbed,andcor02\/mbed-os,kpurusho\/mbed,fanghuaqi\/mbed,rgrover\/mbed,Marcomissyou\/mbed,Willem23\/mbed,jamesadevine\/mbed,tung7970\/mbed-os,al177\/mbed,nvlsianpu\/mbed,NordicSemiconductor\/mbed,autopulated\/mbed,c1728p9\/mbed-os,jeremybrodt\/mbed,pbrook\/mbed,NXPmicro\/mbed,CalSol\/mbed,fpiot\/mbed-ats,kjbracey-arm\/mbed,RonEld\/mbed,Timmmm\/mbed,hwfwgrp\/mbed,NordicSemiconductor\/mbed,FranklyDev\/mbed,wodji\/mbed,JasonHow44\/mbed,fpiot\/mbed-ats,svogl\/mbed-os,logost\/mbed,al177\/mbed,YarivCol\/mbed-os,devanlai\/mbed,kl-cruz\/mbed-os,CalSol\/mbed,netzimme\/mbed-os,betzw\/mbed-os,bremoran\/mbed-drivers,devanlai\/mbed,jferreir\/mbed,RonEld\/mbed,adustm\/mbed,jamesadevine\/mbed,Tiryoh\/mbed,K4zuki\/mbed,mikaleppanen\/mbed-os,devanlai\/mbed,jpbrucker\/mbed,bcostm\/mbed-os,sam-geek\/mbed,pradeep-gr\/mbed-os5-onsemi,pbrook\/mbed,geky\/mbed,autopulated\/mbed,sam-geek\/mbed,karsev\/mbed-os,getopenmono\/mbed,masaohamanaka\/mbed,pradeep-gr\/mbed-os5-onsemi,fahhem\/mbed-os,mikaleppanen\/mbed-os,fanghuaqi\/mbed,getopenmono\/mbed,DanKupiniak\/mbed,nabilbendafi\/mbed,JasonHow44\/mbed,rgrover\/mbed,bulislaw\/mbed-os,jamesadevine\/mbed,devanlai\/mbed,Marcomissyou\/mbed,Archcady\/mbed-os,screamerbg\/mbed,bikeNomad\/mbed,naves-thiago\/mbed-midi,bentwire\/mbed,mbedmicro\/mbed,mmorenobarm\/mbed-os,Sweet-Peas\/mbed,xcrespo\/mbed,theotherjimmy\/mbed,karsev\/mbed-os,kpurusho\/mbed,NitinBhaskar\/mbed,0xc0170\/mbed-drivers,kpurusho\/mbed,kpurusho\/mbed,nvlsianpu\/mbed,arostm\/mbed-os,mazimkhan\/mbed-os,bikeNomad\/mbed,al177\/mbed,logost\/mbed,ARM-software\/mbed-beetle,brstew\/MBED-BUILD,j-greffe\/mbed-os,theotherjimmy\/mbed,betzw\/mbed-os,dbestm\/mbed,mnlipp\/mbed,Sweet-Peas\/mbed,Shengliang\/mbed,pi19404\/mbed,Timmmm\/mbed,naves-thiago\/mbed-midi,rosterloh\/mbed,hwfwgrp\/mbed,svogl\/mbed-os,geky\/mbed,ryankurte\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,nRFMesh\/mbed-os,brstew\/MBED-BUILD,jamesadevine\/mbed,Shengliang\/mbed,naves-thiago\/mbed-midi,Willem23\/mbed,pedromes\/mbed,wodji\/mbed,svastm\/mbed,kjbracey-arm\/mbed,GustavWi\/mbed,JasonHow44\/mbed,autopulated\/mbed,netzimme\/mbed-os,mnlipp\/mbed,nabilbendafi\/mbed,mbedmicro\/mbed,sam-geek\/mbed,fahhem\/mbed-os,fanghuaqi\/mbed,netzimme\/mbed-os,K4zuki\/mbed,jferreir\/mbed,jeremybrodt\/mbed,fpiot\/mbed-ats,bikeNomad\/mbed,mnlipp\/mbed,larks\/mbed,andcor02\/mbed-os,pbrook\/mbed,andreaslarssonublox\/mbed,netzimme\/mbed-os,ban4jp\/mbed,masaohamanaka\/mbed,adamgreen\/mbed,jrjang\/mbed,bulislaw\/mbed-os,andcor02\/mbed-os,infinnovation\/mbed-os,struempelix\/mbed,betzw\/mbed-os,theotherjimmy\/mbed,mmorenobarm\/mbed-os,alertby\/mbed,hwfwgrp\/mbed,GustavWi\/mbed,kl-cruz\/mbed-os,ban4jp\/mbed,mazimkhan\/mbed-os,Shengliang\/mbed,HeadsUpDisplayInc\/mbed,maximmbed\/mbed,brstew\/MBED-BUILD,Marcomissyou\/mbed,NitinBhaskar\/mbed,adustm\/mbed,Timmmm\/mbed,bulislaw\/mbed-os,Archcady\/mbed-os,monkiineko\/mbed-os,infinnovation\/mbed-os,Tiryoh\/mbed,bentwire\/mbed,geky\/mbed,K4zuki\/mbed,jamesadevine\/mbed,bcostm\/mbed-os,catiedev\/mbed-os,rgrover\/mbed,sam-geek\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,catiedev\/mbed-os,infinnovation\/mbed-os,netzimme\/mbed-os,Tiryoh\/mbed,rosterloh\/mbed,xcrespo\/mbed,screamerbg\/mbed,EmuxEvans\/mbed,rosterloh\/mbed,iriark01\/mbed-drivers,rosterloh\/mbed,jpbrucker\/mbed,mmorenobarm\/mbed-os,NXPmicro\/mbed,fvincenzo\/mbed-os,pedromes\/mbed,betzw\/mbed-os,ryankurte\/mbed-os,pedromes\/mbed,screamerbg\/mbed,wodji\/mbed,c1728p9\/mbed-os,ban4jp\/mbed,infinnovation\/mbed-os,HeadsUpDisplayInc\/mbed,FranklyDev\/mbed,bentwire\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,kpurusho\/mbed,fpiot\/mbed-ats,Willem23\/mbed,mnlipp\/mbed,hwfwgrp\/mbed,adamgreen\/mbed,mmorenobarm\/mbed-os,theotherjimmy\/mbed,monkiineko\/mbed-os,svogl\/mbed-os,RonEld\/mbed,Tiryoh\/mbed,Shengliang\/mbed,al177\/mbed,fahhem\/mbed-os,nvlsianpu\/mbed,tung7970\/mbed-os,HeadsUpDisplayInc\/mbed,geky\/mbed,struempelix\/mbed,DanKupiniak\/mbed,DanKupiniak\/mbed,dbestm\/mbed,pradeep-gr\/mbed-os5-onsemi,getopenmono\/mbed,geky\/mbed,c1728p9\/mbed-os,NitinBhaskar\/mbed,cvtsi2sd\/mbed-os,larks\/mbed,Tiryoh\/mbed,alertby\/mbed,FranklyDev\/mbed,maximmbed\/mbed,andreaslarssonublox\/mbed,NordicSemiconductor\/mbed,svastm\/mbed,devanlai\/mbed,tung7970\/mbed-os-1,mbedmicro\/mbed,naves-thiago\/mbed-midi,pedromes\/mbed,pradeep-gr\/mbed-os5-onsemi,alertby\/mbed,CalSol\/mbed","old_file":"libraries\/mbed\/vendor\/STM\/cmsis\/STM32F407\/GCC_ARM\/STM32F407.ld","new_file":"libraries\/mbed\/vendor\/STM\/cmsis\/STM32F407\/GCC_ARM\/STM32F407.ld","new_contents":"\/* Linker script for STM32F407 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K\n  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n  RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 0x1FE78 \n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","old_contents":"\/* Linker script for STM32F407 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K\n  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5ba55a5201fd99c23688518d30f13356ce3a34c9","subject":"MYNEWT-512 Replace gen. sysinit with linker sect","message":"MYNEWT-512 Replace gen. sysinit with linker sect\n\nOLD MECHANISM:\n\n    * pkg.yml file specifies \"init_function\" and \"init_stage\"\n    * newt generates sysinit C files which call the packages' init functions in\n      the specified order.\n\nNEW MECHANISM:\n\n    * Each package defines an \"init entry\" struct containing:\n        * pointer to init function\n        * uint8_t stage\n    * Init entry structs are placed in a special section.\n    * At startup, the sysinit() function walks the list of entries in the\n      special section and calls their corresponding init functions in the\n      correct order.\n\nINTERFACE:\n\n    \/* Package initialization function. *\/\n    typedef void sysinit_init_fn(struct sysinit_init_ctxt *ctxt);\n\n    struct sysinit_entry {\n        \/* Initializes a package. *\/\n        sysinit_init_fn *init_fn;\n\n        \/* Specifies when the init function gets called.  0=first, 1=next, etc. *\/\n        uint8_t stage;\n    };\n\n    struct sysinit_init_ctxt {\n        \/* Corresponds to the init function currently executing. *\/\n        const struct sysinit_entry *entry;\n\n        \/* The stage that sysinit is currently processing. *\/\n        uint8_t cur_stage;\n    };\n\n    \/**\n     * Registers a package initialization function\n     *\n     * @param init_cb               Pointer to the init function to register.\n     * @param init_stage            Indicates when this init function gets called,\n     *                                  relative to other init functions.  0=first,\n     *                                  1=next, etc.\n     *\/\n    #define SYSINIT_REGISTER_INIT(init_cb, init_stage) \/* ... *\/\n\nEXAMPLE:\n\n    static void\n    my_pkg_init(struct sysinit_init_ctxt *ctxt)\n    {\n        \/* ... *\/\n    }\n\n    SYSINIT_REGISTER(my_pkg_init, 2);\n","repos":"runtimeinc\/mynewt_arduino_zero,runtimeinc\/mynewt_arduino_zero,runtimeinc\/mynewt_arduino_zero","old_file":"hw\/mcu\/atmel\/samd21xx\/samd21xx.ld","new_file":"hw\/mcu\/atmel\/samd21xx\/samd21xx.ld","new_contents":"\/**\r\n * \\file\r\n *\r\n * \\brief Linker script for running in internal FLASH on the SAMD21G18A\r\n *\r\n * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.\r\n *\r\n * \\asf_license_start\r\n *\r\n * \\page License\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * 1. Redistributions of source code must retain the above copyright notice,\r\n *    this list of conditions and the following disclaimer.\r\n *\r\n * 2. Redistributions in binary form must reproduce the above copyright notice,\r\n *    this list of conditions and the following disclaimer in the documentation\r\n *    and\/or other materials provided with the distribution.\r\n *\r\n * 3. The name of Atmel may not be used to endorse or promote products derived\r\n *    from this software without specific prior written permission.\r\n *\r\n * 4. This software may only be redistributed and used in connection with an\r\n *    Atmel microcontroller product.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\r\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n * POSSIBILITY OF SUCH DAMAGE.\r\n *\r\n * \\asf_license_stop\r\n *\r\n *\/\r\n\r\n\r\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nSEARCH_DIR(.)\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x200; \/* required amount of stack *\/\r\n\r\n\/* The stack size used by the application. NOTE: you need to adjust according to your application. *\/\r\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;\r\n\r\nENTRY(Reset_Handler)\r\n\r\n\/* Section Definitions *\/\r\nSECTIONS\r\n{\r\n\r\n    .imghdr (NOLOAD):\r\n    {\r\n        . = . + _imghdr_size;\r\n    } > FLASH\r\n\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        _sfixed = .;\r\n        __isr_vector_start = .;\r\n        KEEP(*(.vectors .vectors.*))\r\n        __isr_vector_end = .;\r\n\r\n        *(.text .text.* .gnu.linkonce.t.*)\r\n        *(.glue_7t) *(.glue_7)\r\n        *(.rodata .rodata* .gnu.linkonce.r.*)\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\r\n        \/* Support C constructors, and C destructors in both user code\r\n           and the C library. This also provides support for C++ code. *\/\r\n        . = ALIGN(4);\r\n        KEEP(*(.init))\r\n        . = ALIGN(4);\r\n        __preinit_array_start = .;\r\n        KEEP (*(.preinit_array))\r\n        __preinit_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        __init_array_start = .;\r\n        KEEP (*(SORT(.init_array.*)))\r\n        KEEP (*(.init_array))\r\n        __init_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        KEEP (*crtbegin.o(.ctors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n        KEEP (*(SORT(.ctors.*)))\r\n        KEEP (*crtend.o(.ctors))\r\n\r\n        . = ALIGN(4);\r\n        KEEP(*(.fini))\r\n\r\n        . = ALIGN(4);\r\n        __fini_array_start = .;\r\n        KEEP (*(.fini_array))\r\n        KEEP (*(SORT(.fini_array.*)))\r\n        __fini_array_end = .;\r\n\r\n        KEEP (*crtbegin.o(.dtors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n        KEEP (*(SORT(.dtors.*)))\r\n        KEEP (*crtend.o(.dtors))\r\n\r\n        . = ALIGN(4);\r\n        _efixed = .;            \/* End of text section *\/\r\n    } > FLASH\r\n\r\n    \/* The sysinit section contains package initialization information. *\/\r\n    .sysinit :\r\n    {\r\n        __sysinit_start__ = .;\r\n        KEEP(*(sysinit))\r\n        __sysinit_end__ = .;\r\n    } > FLASH\r\n\r\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n    PROVIDE_HIDDEN (__exidx_start = .);\r\n    .ARM.exidx :\r\n    {\r\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n    PROVIDE_HIDDEN (__exidx_end = .);\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n\r\n    .vector_relocation :\r\n    {\r\n        . = ALIGN(4);\r\n        __vector_tbl_reloc__ = .;\r\n        . = . + (__isr_vector_end - __isr_vector_start);\r\n        . = ALIGN(4);\r\n    } > RAM\r\n\r\n    .relocate :\r\n    {\r\n        . = ALIGN(4);\r\n        _srelocate = .;\r\n        *(.data .data.*);\r\n        . = ALIGN(4);\r\n        _erelocate = .;\r\n    } > RAM AT > FLASH\r\n\r\n    \/* .bss section which is used for uninitialized data *\/\r\n    .bss (NOLOAD) :\r\n    {\r\n        . = ALIGN(4);\r\n\t__bss_start__ = . ;\r\n        _sbss = . ;\r\n        _szero = .;\r\n        *(.bss .bss.*)\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n\t__bss_end__ = . ;\r\n        _ebss = . ;\r\n        _ezero = .;\r\n    } > RAM\r\n\r\n    \/* Heap starts after BSS *\/\r\n    __HeapBase = .;\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  .heap :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( _user_heap_start = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = ALIGN(4);\r\n  } > RAM\r\n\r\n\r\n    \/* .stack_dummy section doesn't contains any symbols. It is only\r\n     * used for linker to calculate size of stack sections, and assign\r\n     * values to stack symbols later *\/\r\n    .stack_dummy (COPY):\r\n    {\r\n        . = . + STACK_SIZE;\r\n        *(.stack*)\r\n    } > RAM\r\n\r\n    _ram_start = ORIGIN(RAM);\r\n\r\n    \/* Set stack top to end of RAM, and stack limit move down by\r\n     * size of stack_dummy section *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n    PROVIDE(__stack = __StackTop);\r\n\r\n    \/* Top of head is the bottom of the stack *\/\r\n  _user_heap_end = __StackLimit;\r\n  __HeapLimit = __StackLimit;\r\n\r\n\r\n    \/* Check if data + heap + stack exceeds RAM limit *\/\r\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","old_contents":"\/**\r\n * \\file\r\n *\r\n * \\brief Linker script for running in internal FLASH on the SAMD21G18A\r\n *\r\n * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.\r\n *\r\n * \\asf_license_start\r\n *\r\n * \\page License\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * 1. Redistributions of source code must retain the above copyright notice,\r\n *    this list of conditions and the following disclaimer.\r\n *\r\n * 2. Redistributions in binary form must reproduce the above copyright notice,\r\n *    this list of conditions and the following disclaimer in the documentation\r\n *    and\/or other materials provided with the distribution.\r\n *\r\n * 3. The name of Atmel may not be used to endorse or promote products derived\r\n *    from this software without specific prior written permission.\r\n *\r\n * 4. This software may only be redistributed and used in connection with an\r\n *    Atmel microcontroller product.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\r\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n * POSSIBILITY OF SUCH DAMAGE.\r\n *\r\n * \\asf_license_stop\r\n *\r\n *\/\r\n\r\n\r\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nSEARCH_DIR(.)\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x200; \/* required amount of stack *\/\r\n\r\n\/* The stack size used by the application. NOTE: you need to adjust according to your application. *\/\r\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;\r\n\r\nENTRY(Reset_Handler)\r\n\r\n\/* Section Definitions *\/\r\nSECTIONS\r\n{\r\n\r\n    .imghdr (NOLOAD):\r\n    {\r\n        . = . + _imghdr_size;\r\n    } > FLASH\r\n\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        _sfixed = .;\r\n        __isr_vector_start = .;\r\n        KEEP(*(.vectors .vectors.*))\r\n        __isr_vector_end = .;\r\n\r\n        *(.text .text.* .gnu.linkonce.t.*)\r\n        *(.glue_7t) *(.glue_7)\r\n        *(.rodata .rodata* .gnu.linkonce.r.*)\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\r\n        \/* Support C constructors, and C destructors in both user code\r\n           and the C library. This also provides support for C++ code. *\/\r\n        . = ALIGN(4);\r\n        KEEP(*(.init))\r\n        . = ALIGN(4);\r\n        __preinit_array_start = .;\r\n        KEEP (*(.preinit_array))\r\n        __preinit_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        __init_array_start = .;\r\n        KEEP (*(SORT(.init_array.*)))\r\n        KEEP (*(.init_array))\r\n        __init_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        KEEP (*crtbegin.o(.ctors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n        KEEP (*(SORT(.ctors.*)))\r\n        KEEP (*crtend.o(.ctors))\r\n\r\n        . = ALIGN(4);\r\n        KEEP(*(.fini))\r\n\r\n        . = ALIGN(4);\r\n        __fini_array_start = .;\r\n        KEEP (*(.fini_array))\r\n        KEEP (*(SORT(.fini_array.*)))\r\n        __fini_array_end = .;\r\n\r\n        KEEP (*crtbegin.o(.dtors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n        KEEP (*(SORT(.dtors.*)))\r\n        KEEP (*crtend.o(.dtors))\r\n\r\n        . = ALIGN(4);\r\n        _efixed = .;            \/* End of text section *\/\r\n    } > FLASH\r\n\r\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n    PROVIDE_HIDDEN (__exidx_start = .);\r\n    .ARM.exidx :\r\n    {\r\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n    PROVIDE_HIDDEN (__exidx_end = .);\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n\r\n    .vector_relocation :\r\n    {\r\n        . = ALIGN(4);\r\n        __vector_tbl_reloc__ = .;\r\n        . = . + (__isr_vector_end - __isr_vector_start);\r\n        . = ALIGN(4);\r\n    } > RAM\r\n\r\n    .relocate :\r\n    {\r\n        . = ALIGN(4);\r\n        _srelocate = .;\r\n        *(.data .data.*);\r\n        . = ALIGN(4);\r\n        _erelocate = .;\r\n    } > RAM AT > FLASH\r\n\r\n    \/* .bss section which is used for uninitialized data *\/\r\n    .bss (NOLOAD) :\r\n    {\r\n        . = ALIGN(4);\r\n\t__bss_start__ = . ;\r\n        _sbss = . ;\r\n        _szero = .;\r\n        *(.bss .bss.*)\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n\t__bss_end__ = . ;\r\n        _ebss = . ;\r\n        _ezero = .;\r\n    } > RAM\r\n\r\n    \/* Heap starts after BSS *\/\r\n    __HeapBase = .;\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  .heap :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( _user_heap_start = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = ALIGN(4);\r\n  } > RAM\r\n\r\n\r\n    \/* .stack_dummy section doesn't contains any symbols. It is only\r\n     * used for linker to calculate size of stack sections, and assign\r\n     * values to stack symbols later *\/\r\n    .stack_dummy (COPY):\r\n    {\r\n        . = . + STACK_SIZE;\r\n        *(.stack*)\r\n    } > RAM\r\n\r\n    _ram_start = ORIGIN(RAM);\r\n\r\n    \/* Set stack top to end of RAM, and stack limit move down by\r\n     * size of stack_dummy section *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n    PROVIDE(__stack = __StackTop);\r\n\r\n    \/* Top of head is the bottom of the stack *\/\r\n  _user_heap_end = __StackLimit;\r\n  __HeapLimit = __StackLimit;\r\n\r\n\r\n    \/* Check if data + heap + stack exceeds RAM limit *\/\r\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8d5acea57bc6acf93a7beb08820681ec9598a67a","subject":"linker: make sure the macro arguments both point to the vma","message":"linker: make sure the macro arguments both point to the vma\n\nIf the rom region can be accessed via a virtual memory address,\nthen __rodata_region_end will point to the vma, while __rom_region_start\nis the lma. This patch makes sure the two values are in the vma address\nspace.\n\nThis is in prepartion for a future patch which will allow the rom to be\naccessed via a virtual memory address.\n\nSigned-off-by: Andriy Gelman <9b800b50c068448b0612a5bdc33ac199b44926a7@gmail.com>\n","repos":"galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr","old_file":"include\/zephyr\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_file":"include\/zephyr\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/devicetree_regions.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGIONS()\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t__rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\t. = ALIGN(4);\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__text_region_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - ADDR(rom_start));\n\t__rom_region_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    GROUP_START(DATA_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_region_start = .;\n\t__data_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\t__data_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    \/* Sections generated from 'zephyr,memory-region' nodes *\/\n    LINKER_DT_SECTIONS()\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/devicetree_regions.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGIONS()\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t__rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\t. = ALIGN(4);\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__text_region_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end -__rom_region_start);\n\t__rom_region_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    GROUP_START(DATA_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_region_start = .;\n\t__data_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\t__data_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    \/* Sections generated from 'zephyr,memory-region' nodes *\/\n    LINKER_DT_SECTIONS()\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ddd323fe225254351e4135564659faf6d6999f98","subject":"[sw] Consistently format linker script","message":"[sw] Consistently format linker script\n\nUse a brace style that's consistent and aligns with our C style guide.\n\nSigned-off-by: Philipp Wagner <5a4b10454c30419e54a1570be358a516ff84bb63@lowrisc.org>\n","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan","old_file":"sw\/device\/exts\/common\/link.ld","new_file":"sw\/device\/exts\/common\/link.ld","new_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\nOUTPUT_ARCH(riscv)\n\nGROUP( -lgcc )\n\nSEARCH_DIR(.)\n__DYNAMIC  =  0;\n\nMEMORY {\n    flash (rx)  : ORIGIN = 0x20000000, LENGTH = 0x100000\n    ram   (!rx) : ORIGIN = 0x10000000, LENGTH = 0x10000\n}\n\n_stack_start = ORIGIN(ram) + LENGTH(ram);\n\n\/* We have to align each sector to word boundaries as our current s19->slm\n * conversion scripts are not able to handle non-word aligned sections. *\/\n\n\nSECTIONS {\n    .crt : {\n        *(.crt)\n    } > flash\n\n    \/* the 256 byte alignment is required by the machine trap vector table *\/\n    .vectors : {\n        . = ALIGN(0x100);\n        _svectors = .;\n        *(.vectors)\n        _evectors = .;\n    } > flash\n\n    .text : {\n        . = ALIGN(0x100);\n        _stext = .;\n        *(.text.startup)\n        *(.text)\n        *(.text.unlikely)\n        _etext  =  .;\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        *(.ctors)\n        LONG(0)\n        __CTOR_END__ = .;\n        __DTOR_LIST__ = .;\n        LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\n        *(.dtors)\n        LONG(0)\n        __DTOR_END__ = .;\n        *(.lit)\n        *(.shdata)\n        _endtext = .;\n    }  > flash\n\n    .rodata : {\n        . = ALIGN(4);\n        *(.rodata);\n        *(.rodata.*)\n    } > flash\n\n    .shbss : {\n        . = ALIGN(4);\n        *(.shbss)\n    } > flash\n\n    \/* idata stores the static variable data that will be loaded in ram below *\/\n    .idata : {\n        . = ALIGN(4);\n        _idata = .;\n    } > flash\n\n    \/* Static variable LMA at end of program\n       VMA at start of RAM.  Stack is at end of RAM *\/\n    .data 0x10000000 : AT ( _idata ) {\n        . = ALIGN(4);\n        _sdata  =  .; \/* start of data *\/\n        *(.data);\n        *(.data.*)\n        *(.sdata);\n        _edata  =  .; \/* end of data *\/\n    } > ram\n\n    .bss : {\n        . = ALIGN(4);\n        _bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(.sbss)\n        *(.sbss.*)\n        *(COMMON)\n        _bss_end = .;\n    } > ram\n\n    .stab  0 (NOLOAD) : {\n        [ .stab ]\n    }\n\n    .stabstr  0 (NOLOAD) : {\n        [ .stabstr ]\n    }\n\n    \/* Discard the remaining sections *\/\n    \/DISCARD\/ : { *(*) }\n}\n\nENTRY(main)\n","old_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\nOUTPUT_ARCH(riscv)\n\nGROUP( -lgcc )\n\nSEARCH_DIR(.)\n__DYNAMIC  =  0;\n\nMEMORY\n{\n    flash (rx)  : ORIGIN = 0x20000000, LENGTH = 0x100000\n    ram   (!rx) : ORIGIN = 0x10000000, LENGTH = 0x10000\n}\n\n_stack_start = ORIGIN(ram) + LENGTH(ram);\n\n\/* We have to align each sector to word boundaries as our current s19->slm\n * conversion scripts are not able to handle non-word aligned sections. *\/\n\n\nSECTIONS\n{\n    .crt : { *(.crt) } > flash\n\n    \/* the 256 byte alignment is required by the machine trap vector table *\/\n    .vectors : {\n        . = ALIGN(0x100);\n        _svectors = .;\n        *(.vectors)\n        _evectors = .;\n    } > flash\n\n    .text : {\n        . = ALIGN(0x100);\n        _stext = .;\n        *(.text.startup)\n        *(.text)\n        *(.text.unlikely)\n        _etext  =  .;\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        *(.ctors)\n        LONG(0)\n        __CTOR_END__ = .;\n        __DTOR_LIST__ = .;\n        LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\n        *(.dtors)\n        LONG(0)\n        __DTOR_END__ = .;\n        *(.lit)\n        *(.shdata)\n        _endtext = .;\n    }  > flash\n\n    .rodata : {\n        . = ALIGN(4);\n        *(.rodata);\n        *(.rodata.*)\n    } > flash\n\n    .shbss :\n    {\n        . = ALIGN(4);\n        *(.shbss)\n    } > flash\n\n    \/* idata stores the static variable data that will be loaded in ram below *\/\n    .idata :\n    {\n        . = ALIGN(4);\n        _idata = .;\n    } > flash\n\n    \/* Static variable LMA at end of program\n       VMA at start of RAM.  Stack is at end of RAM *\/\n    .data 0x10000000 : AT ( _idata ){\n        . = ALIGN(4);\n        _sdata  =  .; \/* start of data *\/\n        *(.data);\n        *(.data.*)\n        *(.sdata);\n        _edata  =  .; \/* end of data *\/\n    } > ram\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(.sbss)\n        *(.sbss.*)\n        *(COMMON)\n        _bss_end = .;\n    } > ram\n\n    .stab  0 (NOLOAD) :\n    {\n        [ .stab ]\n    }\n\n    .stabstr  0 (NOLOAD) :\n    {\n        [ .stabstr ]\n    }\n\n    \/* Discard the remaining sections *\/\n    \/DISCARD\/ : { *(*) }\n}\n\nENTRY(main)\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"71362ddf5da2c220f3300eb7721b5021a467d2ff","subject":"arch: arm: aarch64: linker.ld: Remove redundant text section offset","message":"arch: arm: aarch64: linker.ld: Remove redundant text section offset\n\nThis commit removes the redundant text section offset specification in\nthe AArch64 linker script.\n\nThe text section offset is already specified by the\n`text_section_offset.ld`, which is included by\n`arch\/common\/CMakeLists.txt`.\n\nSigned-off-by: Stephanos Ioannidis <dc76e9f0c0006e8f919e0c515c66dbba3982f785@stephanos.io>\n","repos":"zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#elif defined(CONFIG_CPU_HAS_NRF_IDAU)\n\t\/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. *\/\n\t#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NSC_ALIGN_END . = ALIGN(0x8000)\n#else\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\tASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))\n\t\t\t == (0x8000 - (__sg_start % 0x8000))\n\t\t&& (0x8000 - (__sg_start % 0x8000)) >= 32\n\t\t&& (0x8000 - (__sg_start % 0x8000)) <= 4096,\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#elif defined(CONFIG_CPU_HAS_NRF_IDAU)\n\t\/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. *\/\n\t#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NSC_ALIGN_END . = ALIGN(0x8000)\n#else\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\tASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))\n\t\t\t == (0x8000 - (__sg_start % 0x8000))\n\t\t&& (0x8000 - (__sg_start % 0x8000)) >= 32\n\t\t&& (0x8000 - (__sg_start % 0x8000)) <= 4096,\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"267ca19ae818bfccc0f604e416c24e1567d94fd0","subject":"bootloader: Fix dram_seg","message":"bootloader: Fix dram_seg\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/ld\/esp32s2beta\/bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/ld\/esp32s2beta\/bootloader.ld","new_contents":"\/*\nLinker file used to link the bootloader.\n*\/\n\n\n\/* Simplified memory map for the bootloader\n\n   The main purpose is to make sure the bootloader can load into main memory\n   without overwriting itself.\n*\/\n\nMEMORY\n{\n  \/* I\/O *\/\n  dport0_seg (RW) :                 org = 0x3FF00000, len = 0x10\n  iram_loader_seg (RWX) :           org = 0x40062000, len = 0x4000  \/* 16KB, IRAM *\/\n  iram_seg (RWX) :                  org = 0x40066000, len = 0x4000  \/* 16KB, IRAM *\/\n  \/* 8k at the end of DRAM, before ROM data & stack *\/\n  dram_seg (RW) :                   org = 0x3FFFA000, len = 0x2000\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_wdt.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","old_contents":"\/*\nLinker file used to link the bootloader.\n*\/\n\n\n\/* Simplified memory map for the bootloader\n\n   The main purpose is to make sure the bootloader can load into main memory\n   without overwriting itself.\n*\/\n\nMEMORY\n{\n  \/* I\/O *\/\n  dport0_seg (RW) :                 org = 0x3FF00000, len = 0x10\n  iram_loader_seg (RWX) :           org = 0x40062000, len = 0x4000  \/* 16KB, IRAM *\/\n  iram_seg (RWX) :                  org = 0x40066000, len = 0x4000  \/* 16KB, IRAM *\/\n  \/* 16k at the end of DRAM, before ROM data & stack *\/\n  dram_seg (RW) :                   org = 0x3FFF8000, len = 0x4000\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_wdt.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6dd18fa4cb53491fc52b1fb6e17b753636cdab47","subject":"link_dummy.ld: provide __data_start symbol","message":"link_dummy.ld: provide __data_start symbol\n\nSigned-off-by: Volodymyr Babchuk <07adff7e050dc3230ac0b7d9c296bbb62f4ecc95@gmail.com>\nReviewed-by: Jens Wiklander <7706914404370d7502c27a0eff493dcf491feb51@linaro.org>\n","repos":"pascal-brand-st-dev\/optee_os,pascal-brand-st-dev\/optee_os,pascal-brand-st-dev\/optee_os,pascal-brand-st-dev\/optee_os,pascal-brand-st-dev\/optee_os","old_file":"core\/arch\/arm\/kernel\/link_dummy.ld","new_file":"core\/arch\/arm\/kernel\/link_dummy.ld","new_contents":"\/* SPDX-License-Identifier: BSD-2-Clause *\/\n\/*\n * Copyright (c) 2017, Linaro Limited\n *\/\n\nSECTIONS\n{\n\t\/*\n\t * This seems to make the ARMv7 linker happy with regards to glue_7\n\t * sections etc.\n\t *\/\n\t..dummy : { }\n}\n\n__asan_map_end = .;\n__asan_map_start = .;\n__asan_map_size = .;\n__asan_shadow_end = .;\n__asan_shadow_start = .;\n__asan_shadow_size = .;\n__bss_end = .;\n__bss_start = .;\n__ctor_end = .;\n__ctor_list = .;\n__data_start = .;\n__data_end = .;\n__end = .;\n__end_phys_mem_map_section = .;\n__end_phys_nsec_ddr_section = .;\n__end_phys_sdp_mem_section = .;\n__end_phys_ddr_overall_section = .;\n__start_phys_ddr_overall_section = .;\n__exidx_end = .;\n__exidx_start = .;\n__extab_end = .;\n__extab_start = .;\n__heap1_end = .;\n__heap1_start = .;\n__heap2_end = .;\n__heap2_start = .;\n__initcall_end = .;\n__initcall_start = .;\n__init_end = .;\n__init_size = .;\n__init_start = .;\n__nozi_end = .;\n__nozi_stack_end = .;\n__nozi_stack_start = .;\n__nozi_start = .;\n__pageable_end = .;\n__pageable_part_end = .;\n__pageable_part_start = .;\n__pageable_start = .;\n__rodata_dtdrv_end = .;\n__rodata_dtdrv_start = .;\n__rodata_early_ta_start = .;\n__rodata_early_ta_end = .;\n__rodata_end = .;\n__rodata_start = .;\n__start_phys_nsec_ddr_section = .;\n__text_init_start = .;\n__text_start = .;\n__tmp_hashes_end = .;\n__tmp_hashes_size = .;\n__tmp_hashes_start = .;\n__vcore_init_ro_size = .;\n__vcore_init_ro_start = .;\n__vcore_init_rx_size = .;\n__vcore_init_rx_start = .;\n__vcore_unpg_ro_size = .;\n__vcore_unpg_ro_start = .;\n__vcore_unpg_rw_size = .;\n__vcore_unpg_rw_start = .;\n__vcore_unpg_rx_size = .;\n__vcore_unpg_rx_start = .;\nPROVIDE(core_v_str = 0);\nPROVIDE(tee_entry_std = 0);\nPROVIDE(tee_svc_handler = 0);\nPROVIDE(init_teecore = 0);\n","old_contents":"\/* SPDX-License-Identifier: BSD-2-Clause *\/\n\/*\n * Copyright (c) 2017, Linaro Limited\n *\/\n\nSECTIONS\n{\n\t\/*\n\t * This seems to make the ARMv7 linker happy with regards to glue_7\n\t * sections etc.\n\t *\/\n\t..dummy : { }\n}\n\n__asan_map_end = .;\n__asan_map_start = .;\n__asan_map_size = .;\n__asan_shadow_end = .;\n__asan_shadow_start = .;\n__asan_shadow_size = .;\n__bss_end = .;\n__bss_start = .;\n__ctor_end = .;\n__ctor_list = .;\n__data_end = .;\n__end = .;\n__end_phys_mem_map_section = .;\n__end_phys_nsec_ddr_section = .;\n__end_phys_sdp_mem_section = .;\n__end_phys_ddr_overall_section = .;\n__start_phys_ddr_overall_section = .;\n__exidx_end = .;\n__exidx_start = .;\n__extab_end = .;\n__extab_start = .;\n__heap1_end = .;\n__heap1_start = .;\n__heap2_end = .;\n__heap2_start = .;\n__initcall_end = .;\n__initcall_start = .;\n__init_end = .;\n__init_size = .;\n__init_start = .;\n__nozi_end = .;\n__nozi_stack_end = .;\n__nozi_stack_start = .;\n__nozi_start = .;\n__pageable_end = .;\n__pageable_part_end = .;\n__pageable_part_start = .;\n__pageable_start = .;\n__rodata_dtdrv_end = .;\n__rodata_dtdrv_start = .;\n__rodata_early_ta_start = .;\n__rodata_early_ta_end = .;\n__rodata_end = .;\n__rodata_start = .;\n__start_phys_nsec_ddr_section = .;\n__text_init_start = .;\n__text_start = .;\n__tmp_hashes_end = .;\n__tmp_hashes_size = .;\n__tmp_hashes_start = .;\n__vcore_init_ro_size = .;\n__vcore_init_ro_start = .;\n__vcore_init_rx_size = .;\n__vcore_init_rx_start = .;\n__vcore_unpg_ro_size = .;\n__vcore_unpg_ro_start = .;\n__vcore_unpg_rw_size = .;\n__vcore_unpg_rw_start = .;\n__vcore_unpg_rx_size = .;\n__vcore_unpg_rx_start = .;\nPROVIDE(core_v_str = 0);\nPROVIDE(tee_entry_std = 0);\nPROVIDE(tee_svc_handler = 0);\nPROVIDE(init_teecore = 0);\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"74690660f09a3d4fff6d9d5c08d1fe6ec3c18f64","subject":"discarding the .comment section (which is totally unnecessary in a kernel, since it basically just has a note saying that it was compiled on ubuntu)","message":"discarding the .comment section (which is totally unnecessary in a kernel, since it basically just has a note saying that it was compiled on ubuntu)\n","repos":"bytbox\/wyvern,bytbox\/wyvern","old_file":"kernel\/linker.ld","new_file":"kernel\/linker.ld","new_contents":"ENTRY (loader)\n\nSECTIONS {\n\t. = 0x00100000;\n\t\n\t.text : {\n\t\t*(.text)\n\t}\n\n\t.rodata ALIGN (0x1000) : {\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN (0x1000) : {\n\t\t*(.data)\n\t}\n\n\t.bss : {\n\t\tsbss = .;\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\tebss = .;\n\t}\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t}\n}\n","old_contents":"ENTRY (loader)\n\nSECTIONS {\n\t. = 0x00100000;\n\t\n\t.text : {\n\t\t*(.text)\n\t}\n\n\t.rodata ALIGN (0x1000) : {\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN (0x1000) : {\n\t\t*(.data)\n\t}\n\n\t.bss : {\n\t\tsbss = .;\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\tebss = .;\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"bbdcfb563419aef9d857b49001a5d25159e807f3","subject":"fix SRAM memory size in linker script","message":"fix SRAM memory size in linker script\n","repos":"SiarheiVolkau\/CC3200-Linux-SDK,SiarheiVolkau\/CC3200-Linux-SDK,SiarheiVolkau\/CC3200-Linux-SDK","old_file":"src\/example\/common\/gcc\/cc3200r1m2.ld","new_file":"src\/example\/common\/gcc\/cc3200r1m2.ld","new_contents":"\/*****************************************************************************\r\n* cc3200r1m2.ld\r\n*\r\n* GCC Linker script for cc3200 chips with 256k SRAM.\r\n*\r\n* Copyright (C) 2014 Texas Instruments Incorporated - http:\/\/www.ti.com\/ \r\n* \r\n* \r\n*  Redistribution and use in source and binary forms, with or without \r\n*  modification, are permitted provided that the following conditions \r\n*  are met:\r\n*\r\n*    Redistributions of source code must retain the above copyright \r\n*    notice, this list of conditions and the following disclaimer.\r\n*\r\n*    Redistributions in binary form must reproduce the above copyright\r\n*    notice, this list of conditions and the following disclaimer in the \r\n*    documentation and\/or other materials provided with the   \r\n*    distribution.\r\n*\r\n*    Neither the name of Texas Instruments Incorporated nor the names of\r\n*    its contributors may be used to endorse or promote products derived\r\n*    from this software without specific prior written permission.\r\n*\r\n*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r\n*  \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r\n*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r\n*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r\n*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r\n*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r\n*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r\n*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r\n*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r\n*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r\n*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*\r\n******************************************************************************\/\r\n\r\nHEAP_SIZE = 0x00010000;\r\n\r\nMEMORY\r\n{\r\n    SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 0x0003C000\r\n}\r\n\r\nSECTIONS\r\n{\r\n    .text :\r\n    {\r\n        _text = .;\r\n        KEEP(*(.intvecs))\r\n        *(.text*)\r\n        *(.rodata*)\r\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\t. = ALIGN(8);\r\n        _etext = .;\r\n    } > SRAM\r\n\r\n    .ARM : {\r\n    __exidx_start = .;\r\n      *(.ARM.exidx*)\r\n      __exidx_end = .;\r\n    } > SRAM\r\n\r\n    __init_data = .;\r\n\r\n    .data : AT(__init_data)\r\n    {\r\n        _data = .;\r\n        *(.data*)\r\n\t. = ALIGN (8);\r\n        _edata = .;\r\n    } > SRAM\r\n\r\n    .bss :\r\n    {\r\n        _bss = .;\r\n        *(.bss*)\r\n        *(COMMON)\r\n        _ebss = .;\r\n    } > SRAM\r\n\r\n    .heap :\r\n    {\r\n\t_heap = .;\r\n\t. = . + HEAP_SIZE;\r\n\t. = ALIGN(8);\r\n\t_eheap = .;\r\n\r\n    }\r\n}\r\n\r\n","old_contents":"\/*****************************************************************************\r\n* cc3200r1m2.ld\r\n*\r\n* GCC Linker script for cc3200 chips with 256k SRAM.\r\n*\r\n* Copyright (C) 2014 Texas Instruments Incorporated - http:\/\/www.ti.com\/ \r\n* \r\n* \r\n*  Redistribution and use in source and binary forms, with or without \r\n*  modification, are permitted provided that the following conditions \r\n*  are met:\r\n*\r\n*    Redistributions of source code must retain the above copyright \r\n*    notice, this list of conditions and the following disclaimer.\r\n*\r\n*    Redistributions in binary form must reproduce the above copyright\r\n*    notice, this list of conditions and the following disclaimer in the \r\n*    documentation and\/or other materials provided with the   \r\n*    distribution.\r\n*\r\n*    Neither the name of Texas Instruments Incorporated nor the names of\r\n*    its contributors may be used to endorse or promote products derived\r\n*    from this software without specific prior written permission.\r\n*\r\n*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r\n*  \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r\n*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r\n*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r\n*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r\n*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r\n*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r\n*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r\n*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r\n*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r\n*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*\r\n******************************************************************************\/\r\n\r\nHEAP_SIZE = 0x00010000;\r\n\r\nMEMORY\r\n{\r\n    SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 0x00030000\r\n}\r\n\r\nSECTIONS\r\n{\r\n    .text :\r\n    {\r\n        _text = .;\r\n        KEEP(*(.intvecs))\r\n        *(.text*)\r\n        *(.rodata*)\r\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\t. = ALIGN(8);\r\n        _etext = .;\r\n    } > SRAM\r\n\r\n    .ARM : {\r\n    __exidx_start = .;\r\n      *(.ARM.exidx*)\r\n      __exidx_end = .;\r\n    } > SRAM\r\n\r\n    __init_data = .;\r\n\r\n    .data : AT(__init_data)\r\n    {\r\n        _data = .;\r\n        *(.data*)\r\n\t. = ALIGN (8);\r\n        _edata = .;\r\n    } > SRAM\r\n\r\n    .bss :\r\n    {\r\n        _bss = .;\r\n        *(.bss*)\r\n        *(COMMON)\r\n        _ebss = .;\r\n    } > SRAM\r\n\r\n    .heap :\r\n    {\r\n\t_heap = .;\r\n\t. = . + HEAP_SIZE;\r\n\t. = ALIGN(8);\r\n\t_eheap = .;\r\n\r\n    }\r\n}\r\n\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"935e021250bb4de67d973f229dff27c55c7874f1","subject":"esp8266: Put modpybi2c.o to FlashROM.","message":"esp8266: Put modpybi2c.o to FlashROM.\n","repos":"PappaPeppar\/micropython,hosaka\/micropython,micropython\/micropython-esp32,oopy\/micropython,hosaka\/micropython,hosaka\/micropython,AriZuu\/micropython,bvernoux\/micropython,mhoffma\/micropython,selste\/micropython,drrk\/micropython,HenrikSolver\/micropython,alex-march\/micropython,pramasoul\/micropython,dxxb\/micropython,infinnovation\/micropython,jmarcelino\/pycom-micropython,TDAbboud\/micropython,HenrikSolver\/micropython,ryannathans\/micropython,Timmenem\/micropython,TDAbboud\/micropython,puuu\/micropython,Timmenem\/micropython,adafruit\/micropython,turbinenreiter\/micropython,Peetz0r\/micropython-esp32,tuc-osg\/micropython,misterdanb\/micropython,hiway\/micropython,jmarcelino\/pycom-micropython,dinau\/micropython,MrSurly\/micropython,infinnovation\/micropython,AriZuu\/micropython,lowRISC\/micropython,ganshun666\/micropython,alex-march\/micropython,emfcamp\/micropython,infinnovation\/micropython,deshipu\/micropython,chrisdearman\/micropython,MrSurly\/micropython,dmazzella\/micropython,toolmacher\/micropython,tuc-osg\/micropython,redbear\/micropython,adafruit\/micropython,chrisdearman\/micropython,infinnovation\/micropython,Peetz0r\/micropython-esp32,dinau\/micropython,redbear\/micropython,dinau\/micropython,PappaPeppar\/micropython,tuc-osg\/micropython,MrSurly\/micropython-esp32,swegener\/micropython,ganshun666\/micropython,dxxb\/micropython,AriZuu\/micropython,alex-march\/micropython,hosaka\/micropython,redbear\/micropython,chrisdearman\/micropython,lowRISC\/micropython,mhoffma\/micropython,blazewicz\/micropython,kerneltask\/micropython,turbinenreiter\/micropython,blazewicz\/micropython,matthewelse\/micropython,cwyark\/micropython,kerneltask\/micropython,infinnovation\/micropython,drrk\/micropython,hosaka\/micropython,mpalomer\/micropython,selste\/micropython,tobbad\/micropython,PappaPeppar\/micropython,PappaPeppar\/micropython,SHA2017-badge\/micropython-esp32,mhoffma\/micropython,alex-robbins\/micropython,torwag\/micropython,trezor\/micropython,ganshun666\/micropython,ganshun666\/micropython,MrSurly\/micropython-esp32,Timmenem\/micropython,selste\/micropython,dmazzella\/micropython,dinau\/micropython,cwyark\/micropython,praemdonck\/micropython,cwyark\/micropython,tobbad\/micropython,adafruit\/micropython,MrSurly\/micropython-esp32,ganshun666\/micropython,kerneltask\/micropython,SHA2017-badge\/micropython-esp32,adafruit\/circuitpython,henriknelson\/micropython,micropython\/micropython-esp32,mpalomer\/micropython,emfcamp\/micropython,MrSurly\/micropython,SHA2017-badge\/micropython-esp32,selste\/micropython,misterdanb\/micropython,pramasoul\/micropython,toolmacher\/micropython,swegener\/micropython,dinau\/micropython,cwyark\/micropython,TDAbboud\/micropython,oopy\/micropython,dxxb\/micropython,swegener\/micropython,adafruit\/micropython,pfalcon\/micropython,pramasoul\/micropython,TDAbboud\/micropython,toolmacher\/micropython,henriknelson\/micropython,ryannathans\/micropython,emfcamp\/micropython,oopy\/micropython,mhoffma\/micropython,trezor\/micropython,PappaPeppar\/micropython,Timmenem\/micropython,Peetz0r\/micropython-esp32,turbinenreiter\/micropython,blazewicz\/micropython,kerneltask\/micropython,tralamazza\/micropython,toolmacher\/micropython,pozetroninc\/micropython,AriZuu\/micropython,henriknelson\/micropython,chrisdearman\/micropython,dxxb\/micropython,alex-robbins\/micropython,puuu\/micropython,deshipu\/micropython,praemdonck\/micropython,praemdonck\/micropython,micropython\/micropython-esp32,micropython\/micropython-esp32,tobbad\/micropython,turbinenreiter\/micropython,MrSurly\/micropython,hiway\/micropython,TDAbboud\/micropython,pfalcon\/micropython,matthewelse\/micropython,tralamazza\/micropython,selste\/micropython,cwyark\/micropython,drrk\/micropython,dmazzella\/micropython,tralamazza\/micropython,trezor\/micropython,blazewicz\/micropython,alex-robbins\/micropython,deshipu\/micropython,mhoffma\/micropython,henriknelson\/micropython,pramasoul\/micropython,trezor\/micropython,lowRISC\/micropython,pfalcon\/micropython,drrk\/micropython,AriZuu\/micropython,drrk\/micropython,trezor\/micropython,mpalomer\/micropython,HenrikSolver\/micropython,jmarcelino\/pycom-micropython,redbear\/micropython,turbinenreiter\/micropython,adafruit\/micropython,misterdanb\/micropython,alex-robbins\/micropython,pozetroninc\/micropython,mpalomer\/micropython,tuc-osg\/micropython,swegener\/micropython,torwag\/micropython,Peetz0r\/micropython-esp32,matthewelse\/micropython,praemdonck\/micropython,oopy\/micropython,puuu\/micropython,dxxb\/micropython,kerneltask\/micropython,adafruit\/circuitpython,jmarcelino\/pycom-micropython,tralamazza\/micropython,alex-march\/micropython,bvernoux\/micropython,pramasoul\/micropython,dmazzella\/micropython,pozetroninc\/micropython,MrSurly\/micropython-esp32,alex-march\/micropython,pozetroninc\/micropython,puuu\/micropython,puuu\/micropython,ryannathans\/micropython,deshipu\/micropython,misterdanb\/micropython,oopy\/micropython,matthewelse\/micropython,tobbad\/micropython,jmarcelino\/pycom-micropython,ryannathans\/micropython,hiway\/micropython,HenrikSolver\/micropython,tobbad\/micropython,bvernoux\/micropython,blazewicz\/micropython,HenrikSolver\/micropython,adafruit\/circuitpython,emfcamp\/micropython,adafruit\/circuitpython,micropython\/micropython-esp32,swegener\/micropython,henriknelson\/micropython,mpalomer\/micropython,torwag\/micropython,bvernoux\/micropython,pfalcon\/micropython,toolmacher\/micropython,torwag\/micropython,torwag\/micropython,praemdonck\/micropython,matthewelse\/micropython,hiway\/micropython,adafruit\/circuitpython,Timmenem\/micropython,alex-robbins\/micropython,pozetroninc\/micropython,redbear\/micropython,Peetz0r\/micropython-esp32,lowRISC\/micropython,tuc-osg\/micropython,lowRISC\/micropython,bvernoux\/micropython,matthewelse\/micropython,chrisdearman\/micropython,pfalcon\/micropython,SHA2017-badge\/micropython-esp32,hiway\/micropython,deshipu\/micropython,adafruit\/circuitpython,MrSurly\/micropython,misterdanb\/micropython,emfcamp\/micropython,SHA2017-badge\/micropython-esp32,ryannathans\/micropython,MrSurly\/micropython-esp32","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"023748f80050330a4127503e44f18eaaff86da6c","subject":"Update LPC11U68.ld","message":"Update LPC11U68.ld\n","repos":"Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS","old_file":"TARGET_NXP\/TARGET_LPC11U6X\/TOOLCHAIN_GCC_ARM\/TARGET_LPC11U68\/LPC11U68.ld","new_file":"TARGET_NXP\/TARGET_LPC11U6X\/TOOLCHAIN_GCC_ARM\/TARGET_LPC11U68\/LPC11U68.ld","new_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC11U68\n * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Sat Jun 14 15:26:54 JST 2014\n *\/\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 \/* 32K bytes *\/\n  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 \/* 2K bytes *\/\n  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_32 = 0x10000000 + 0x8000;\n  __top_Ram1_2 = 0x20000000 + 0x800;\n  __top_Ram2USB_2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        __vectors_start__ = ABSOLUTE(.) ;\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \/* possible MTB section for Ram1_2 *\/\n    .mtb_buffer_RAM2 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM2*))\n        KEEP(*(.mtb.$RAM1_2*))\n    } > Ram1_2 \n    \n    \/* DATA section for Ram1_2 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_2)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 AT>MFlash256\n    \/* possible MTB section for Ram2USB_2 *\/\n    .mtb_buffer_RAM3 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM3*))\n        KEEP(*(.mtb.$RAM2USB_2*))\n    } > Ram2USB_2 \n    \n    \/* DATA section for Ram2USB_2 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2USB_2)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/\n    \n    \/* Default MTB section *\/\n    .mtb_buffer_default (NOLOAD) :\n    {\n       KEEP(*(.mtb*))\n    } > Ram0_32 \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_32\n\n\t\n\t\/* Main DATA section (Ram0_32) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_32 AT>MFlash256\n\n    \/* BSS section for Ram1_2 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2\n    \/* BSS section for Ram2USB_2 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_32\n        \n    \/* NOINIT section for Ram1_2 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 \n    \/* NOINIT section for Ram2USB_2 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_32 - 0);\n}\n","old_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC11U68\n * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Sat Jun 14 15:26:54 JST 2014\n *\/\n\n\/*GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a crti.o crtn.o crtbegin.o crtend.o)*\/\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 \/* 32K bytes *\/\n  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 \/* 2K bytes *\/\n  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_32 = 0x10000000 + 0x8000;\n  __top_Ram1_2 = 0x20000000 + 0x800;\n  __top_Ram2USB_2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        __vectors_start__ = ABSOLUTE(.) ;\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \/* possible MTB section for Ram1_2 *\/\n    .mtb_buffer_RAM2 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM2*))\n        KEEP(*(.mtb.$RAM1_2*))\n    } > Ram1_2 \n    \n    \/* DATA section for Ram1_2 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_2)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 AT>MFlash256\n    \/* possible MTB section for Ram2USB_2 *\/\n    .mtb_buffer_RAM3 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM3*))\n        KEEP(*(.mtb.$RAM2USB_2*))\n    } > Ram2USB_2 \n    \n    \/* DATA section for Ram2USB_2 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2USB_2)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/\n    \n    \/* Default MTB section *\/\n    .mtb_buffer_default (NOLOAD) :\n    {\n       KEEP(*(.mtb*))\n    } > Ram0_32 \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_32\n\n\t\n\t\/* Main DATA section (Ram0_32) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_32 AT>MFlash256\n\n    \/* BSS section for Ram1_2 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2\n    \/* BSS section for Ram2USB_2 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_32\n        \n    \/* NOINIT section for Ram1_2 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 \n    \/* NOINIT section for Ram2USB_2 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_32 - 0);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c2b87890d59b7d176c537d76c27c50d38d55ba71","subject":"\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u30fc\u30b9\u30bf\u30c3\u30af\u306e\u5897\u91cf","message":"\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u30fc\u30b9\u30bf\u30c3\u30af\u306e\u5897\u91cf\n","repos":"hirakuni45\/R8C,hirakuni45\/R8C,hirakuni45\/R8C","old_file":"M120AN\/m120an.ld","new_file":"M120AN\/m120an.ld","new_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x0300, LENGTH = 0x0480\n\tROM (r)  : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVVEC (r) : ORIGIN = 0xFED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0740;\n\t\t_isp_init = 0x0780;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x0300, LENGTH = 0x0480\n\tROM (r)  : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVVEC (r) : ORIGIN = 0xFED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0760;\n\t\t_isp_init = 0x0780;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"e7b957fb046ae82eef0130c95dcca58a71e77253","subject":"mips_pic32mz: Tabs to spaces in ldscript","message":"mips_pic32mz: Tabs to spaces in ldscript\n","repos":"josephnoir\/RIOT,kbumsik\/RIOT,aeneby\/RIOT,yogo1212\/RIOT,rfuentess\/RIOT,RIOT-OS\/RIOT,rfuentess\/RIOT,authmillenon\/RIOT,kbumsik\/RIOT,miri64\/RIOT,A-Paul\/RIOT,kaspar030\/RIOT,smlng\/RIOT,basilfx\/RIOT,gebart\/RIOT,BytesGalore\/RIOT,mfrey\/RIOT,OTAkeys\/RIOT,gebart\/RIOT,kbumsik\/RIOT,miri64\/RIOT,gebart\/RIOT,kYc0o\/RIOT,biboc\/RIOT,basilfx\/RIOT,lazytech-org\/RIOT,lazytech-org\/RIOT,biboc\/RIOT,x3ro\/RIOT,toonst\/RIOT,smlng\/RIOT,smlng\/RIOT,yogo1212\/RIOT,BytesGalore\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,neiljay\/RIOT,kaspar030\/RIOT,avmelnikoff\/RIOT,gebart\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,josephnoir\/RIOT,x3ro\/RIOT,OTAkeys\/RIOT,A-Paul\/RIOT,A-Paul\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,OlegHahm\/RIOT,josephnoir\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,kbumsik\/RIOT,kYc0o\/RIOT,authmillenon\/RIOT,mtausig\/RIOT,avmelnikoff\/RIOT,toonst\/RIOT,avmelnikoff\/RIOT,x3ro\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,x3ro\/RIOT,mtausig\/RIOT,rfuentess\/RIOT,OlegHahm\/RIOT,aeneby\/RIOT,smlng\/RIOT,mfrey\/RIOT,mfrey\/RIOT,jasonatran\/RIOT,rfuentess\/RIOT,cladmi\/RIOT,OTAkeys\/RIOT,mfrey\/RIOT,kbumsik\/RIOT,basilfx\/RIOT,mtausig\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,yogo1212\/RIOT,yogo1212\/RIOT,gebart\/RIOT,smlng\/RIOT,kYc0o\/RIOT,aeneby\/RIOT,cladmi\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,mtausig\/RIOT,BytesGalore\/RIOT,cladmi\/RIOT,jasonatran\/RIOT,biboc\/RIOT,jasonatran\/RIOT,yogo1212\/RIOT,lazytech-org\/RIOT,cladmi\/RIOT,cladmi\/RIOT,neiljay\/RIOT,x3ro\/RIOT,avmelnikoff\/RIOT,aeneby\/RIOT,A-Paul\/RIOT,ant9000\/RIOT,A-Paul\/RIOT,ant9000\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,basilfx\/RIOT,yogo1212\/RIOT,mtausig\/RIOT,biboc\/RIOT,neiljay\/RIOT,BytesGalore\/RIOT,toonst\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,ant9000\/RIOT,josephnoir\/RIOT,miri64\/RIOT,OTAkeys\/RIOT,biboc\/RIOT,mfrey\/RIOT,lazytech-org\/RIOT,basilfx\/RIOT,toonst\/RIOT,josephnoir\/RIOT,BytesGalore\/RIOT,lazytech-org\/RIOT,neiljay\/RIOT,RIOT-OS\/RIOT,neiljay\/RIOT,kaspar030\/RIOT,toonst\/RIOT,avmelnikoff\/RIOT","old_file":"cpu\/mips_pic32mz\/ldscripts\/pic32mz2048_uhi.ld","new_file":"cpu\/mips_pic32mz\/ldscripts\/pic32mz2048_uhi.ld","new_contents":"\/*\n * A platform and target independent link script to produce UHI\n * compliant binaries with varying levels of system initialization\n * support.\n *\/\n\n__entry = DEFINED(__reset_vector) ? 0xbfc00000 : _start;\nENTRY(__entry)\nOUTPUT_FORMAT(\"elf32-tradlittlemips\", \"elf32-tradbigmips\", \"elf32-tradlittlemips\")\nGROUP(-lc -luhi -lgcc -lhal)\nSEARCH_DIR(.)\n__DYNAMIC  =  0;\nSTARTUP(crt0.o)\n\/* Force the exception handler to be registered *\/\nEXTERN(__register_excpt_handler)\n\/* Force the exception handler to be included in the link *\/\nEXTERN(__exception_entry)\n\/*\n * Require verbose exceptions. This can be changed to pull in\n * __exception_handle_quiet to reduce code size but be less\n * informative\n *\/\nEXTERN(__exception_handle_verbose)\n\/* Force the interrupt handlers to tbe included in the link *\/\nEXTERN(__isr_vec)\n\/* Require the UHI getargs support *\/\nEXTERN(__getargs)\n\n\/*\n * Set the location of the top of the stack.  A value of 0 means\n * that it will be automatically placed at the highest address\n * available as described by the __memory_* setttings\n *\/\nPROVIDE (__stack = 0);\n\n\/* Size of the memory returned by _get_ram_range *\/\nPROVIDE (__memory_size = 512K);\n\n\/* Base of the memory returned by _get_ram_range *\/\nPROVIDE (__memory_base = 0x80000000);\n\n\/* Stride length for tlb software invalidate for tlbinvf\n * (mipsXXr3+). Some MIPS implementations may layout the sets\/ways\n * differently in the index register. Either sets LSB or ways LSB.\n *\n * By setting this to 1 we presume that sets come first. The default boot\n * code will decrement this value from the Number of TLB entries.\n *\/\nPROVIDE (__tlb_stride_length = 1);\n\n\/* By default, XPA is not used even if available. To enable XPA,\n * __enable_xpa should be 1.\n *\/\nPROVIDE (__enable_xpa = 0);\n\n\/*\n * 0 = Do not use exception handler present in boot for UHI\n * 1 = Use exception handler present in boot for UHI if BEV is 0 at\n *     startup\n * 2 = Always use exception handler present in boot for UHI\n *\/\nPROVIDE (__use_excpt_boot = 0);\n\/*\n * Include the code to be able to return to boot context.  This is\n * necessary if __use_excpt_boot != 0.\n *\/\nEXTERN (__register_excpt_boot);\n\nASSERT (DEFINED(__register_excpt_boot) || __use_excpt_boot == 0,\n        \"Registration for boot context is required for UHI chaining\")\n\n\/* Control if subnormal floating-point values are flushed to zero in\n   hardware.  This applies to both FPU and MSA operations.  *\/\nPROVIDE (__flush_to_zero = 1);\n\n\/* Set up the public symbols depending on whether the user has chosen\n   quiet or verbose exception handling above *\/\nEXTERN (__exception_handle);\nPROVIDE(__exception_handle = (DEFINED(__exception_handle_quiet)\n                                      ? __exception_handle_quiet\n                                      : __exception_handle_verbose));\nPROVIDE(_mips_handle_exception = __exception_handle);\n\n\/*\n * Initalize some symbols to be zero so we can reference them in the\n * crt0 without core dumping. These functions are all optional, but\n * we do this so we can have our crt0 always use them if they exist.\n * This is so BSPs work better when using the crt0 installed with gcc.\n * We have to initalize them twice, so we multiple object file\n * formats, as some prepend an underscore.\n *\/\nPROVIDE (hardware_exit_hook = 0);\nPROVIDE (hardware_hazard_hook = 0);\nPROVIDE (hardware_init_hook = 0);\nPROVIDE (software_init_hook = 0);\n\n\/* The default base address for application flash code is 0x9D001000 *\/\nPROVIDE (__app_start = 0x9D001000) ;\n\/* Set default vector spacing to 32 bytes. *\/\nPROVIDE (__isr_vec_space = 32);\n\/* Leave space for 9 vector entries by default. 8 entry points and one\n   fallback handler. *\/\nPROVIDE (__isr_vec_count = 9);\n\/*\n * The start of boot flash must be set if including boot code.  By default\n * the use of boot code will mean that application code is copied\n * from flash to RAM at runtime before being executed.\n *\/\nPROVIDE (__lower_boot_flash_start = DEFINED(__reset_vector) ? 0xbfc00000 : __app_start);\n\nPROVIDE (__boot_flash1_start = 0xbfc40000);\n\nPROVIDE (__boot_flash2_start = 0xbfc60000);\n\nPROVIDE (__bev_override = 0x9fc00000);\n\nPROVIDE (__flash_vector_start = 0x9D000000);\n\nPROVIDE (__flash_app_start = 0x9D001000);\n\nSECTIONS\n{\n  \/* Start of bootrom *\/\n  .lowerbootflashalias __bev_override : \/* Runs uncached (from 0xBfc00000) until I$ is\n                               initialized. *\/\n  AT (__lower_boot_flash_start)\n  {\n    __base = .;\n\n    *(.reset)           \/* Reset entry point. *\/\n    *(.boot)            \/* Boot code. *\/\n    . = ALIGN(8);\n\n    . = __base + 0xff40; \/*Alternate Config bits (lower Alias)*\/\n    KEEP(*(.adevcfg3_la))\n    KEEP(*(.adevcfg2_la))\n    KEEP(*(.adevcfg1_la))\n    KEEP(*(.adevcfg0_la))\n    . = __base + 0xff5c;\n    KEEP(*(.adevcp0_la))\n    . = __base + 0xff6c;\n    KEEP(*(.adevsign_la))\n\n    . = __base + 0xffc0; \/*Config bits (lower Alias)*\/\n    KEEP(*(.devcfg3_la))\n    KEEP(*(.devcfg2_la))\n    KEEP(*(.devcfg1_la))\n    KEEP(*(.devcfg0_la))\n    . = __base + 0xffdc;\n    KEEP(*(.devcp0_la))\n    . = __base + 0xffec;\n    KEEP(*(.devsign_la))\n\n    . = __base + 0xfff0;\n    KEEP(*(.seq_la))\n  } = 0xFFFFFFFF\n\n  \/*\n   * We only add this block to keep the MPLAB programmer happy\n   * It seems to want the config regs values in the non aliased locations\n   *\/\n  . = __base + 0x40000 + 0xff40;\n  .bootflash1 :\n  AT(__boot_flash1_start + 0xff40)\n  {\n    __altbase = .;\n\n    . = __altbase; \/* Alternate Config Bits (boot flash 1) *\/\n    KEEP(*(.adevcfg3_b1))\n    KEEP(*(.adevcfg2_b1))\n    KEEP(*(.adevcfg1_b1))\n    KEEP(*(.adevcfg0_b1))\n    . = __altbase + 0x1c;\n    KEEP(*(.adevcp0_b1))\n    . = __altbase + 0x2c;\n    KEEP(*(.adevsign_b1))\n\n    . = __altbase + 0x80;\n    KEEP(*(.devcfg3_b1))\n    KEEP(*(.devcfg2_b1))\n    KEEP(*(.devcfg1_b1))\n    KEEP(*(.devcfg0_b1))\n    . = __altbase + 0x9c;\n    KEEP(*(.devcp0_b1))\n    . = __altbase + 0xAc;\n    KEEP(*(.devsign_b1))\n    . = __altbase + 0xB0;\n    KEEP(*(.seq_b1))\n   }  = 0xFFFFFFFF\n\n  \/*\n   * We only add this block to keep the MPLAB programmer happy\n   * It seems to want the config regs values in the non aliased locations\n   *\/\n  . = __base + 0x60000 + 0xff40;\n  .bootflash2 :\n  AT(__boot_flash2_start + 0xff40)\n  {\n    __altbase = .;\n\n    . = __altbase; \/* Alternate Config Bits (boot flash 1) *\/\n    KEEP(*(.adevcfg3_b2))\n    KEEP(*(.adevcfg2_b2))\n    KEEP(*(.adevcfg1_b2))\n    KEEP(*(.adevcfg0_b2))\n    . = __altbase + 0x1c;\n    KEEP(*(.adevcp0_b2))\n     . = __altbase + 0x2c;\n    KEEP(*(.adevsign_b2))\n\n    . = __altbase + 0x80;\n    KEEP(*(.devcfg3_b2))\n    KEEP(*(.devcfg2_b2))\n    KEEP(*(.devcfg1_b2))\n    KEEP(*(.devcfg0_b2))\n    . = __altbase + 0x9c;\n    KEEP(*(.devcp0_b2))\n    . = __altbase + 0xAc;\n    KEEP(*(.devsign_b2))\n    . = __altbase + 0xB0;\n    KEEP(*(.seq_b2))\n  } = 0xFFFFFFFF\n\n  \/* Start of the application *\/\n  .exception_vector ALIGN(__flash_vector_start, 0x1000) :\n  AT (__flash_vector_start)\n  {\n    PROVIDE (__excpt_ebase = ABSOLUTE(.));\n    __base = .;\n    KEEP(* (.text.__exception_entry))\n\n    . = __base + 0x200;\n    KEEP(* (SORT(.text.__isr_vec*)))\n    \/* Leave space for all the vector entries *\/\n    . = __base + 0x200 + (__isr_vec_space * __isr_vec_count);\n    ASSERT(__isr_vec_space == (DEFINED(__isr_vec_sw0)\n                               ? __isr_vec_sw1 - __isr_vec_sw0\n                               : __isr_vec_space),\n           \"Actual ISR vector spacing does not match __isr_vec_space\");\n    ASSERT(__base + 0x200 == (DEFINED(__isr_vec_sw0)\n                              ? __isr_vec_sw0 & 0xfffffffe : __base + 0x200),\n           \"__isr_vec_sw0 is not placed at EBASE + 0x200\");\n    . = ALIGN(8);\n  } = 0\n\n  . = __flash_app_start;\n\n  .text : {\n     _ftext = . ;\n    PROVIDE (eprol  =  .);\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t.*)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n  }\n  .init : {\n    KEEP (*(.init))\n  }\n  .fini : {\n    KEEP (*(.fini))\n  }\n  .rel.sdata : {\n    PROVIDE (__runtime_reloc_start = .);\n    *(.rel.sdata)\n    PROVIDE (__runtime_reloc_stop = .);\n  }\n  PROVIDE (etext  =  .);\n  _etext  =  .;\n\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame : { KEEP (*(.eh_frame)) }\n  .gcc_except_table : { *(.gcc_except_table*) }\n  .jcr : { KEEP (*(.jcr)) }\n  .ctors    :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n\n    KEEP (*crtbegin.o(.ctors))\n\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n\n  .dtors    :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  . = .;\n  .MIPS.abiflags : {\n    __MIPS_abiflags_start = .;\n    *(.MIPS.abiflags)\n    __MIPS_abiflags_end = .;\n  }\n  .rodata : {\n    *(.rdata)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n  }\n  _rom_data_copy = .;\n\n  .data ALIGN(__memory_base + 0x1000, 16) :\n  AT (_rom_data_copy)\n  {\n     _fdata = .;\n\n      *(.data)\n      *(.data.*)\n      *(.gnu.linkonce.d.*)\n\n    . = ALIGN(8);\n    _gp = . + 0x8000;\n    __global = _gp;\n\n      *(.lit8)\n      *(.lit4)\n      *(.sdata)\n      *(.sdata.*)\n      *(.gnu.linkonce.s.*)\n  }\n  . = ALIGN(4);\n  PROVIDE (edata  =  .);\n  _edata  =  .;\n  _fbss = .;\n  .sbss : {\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n  }\n  .bss : {\n    _bss_start = . ;\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n  }\n\n  . = ALIGN(4);\n  PROVIDE (end = .);\n  _end = .;\n  \/* Now place the data that is only needed within start.S and can be\n     overwritten by the heap.  *\/\n  .startdata : {\n    *(.startdata)\n  }\n\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to\n     the beginning of the section so we begin them at 0.  *\/\n\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n\n  \/* Special sections generated by gcc *\/\n  \/* Newer GNU linkers strip by default *\/\n  .mdebug.abi32            0 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32           0 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64            0 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64           0 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32           0 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64           0 : { KEEP(*(.mdebug.eabi64)) }\n  .gcc_compiled_long32     0 : { KEEP(*(.gcc_compiled_long32)) }\n  .gcc_compiled_long64     0 : { KEEP(*(.gcc_compiled_long64)) }\n}\n","old_contents":"\/*\n * A platform and target independent link script to produce UHI\n * compliant binaries with varying levels of system initialization\n * support.\n *\/\n\n__entry = DEFINED(__reset_vector) ? 0xbfc00000 : _start;\nENTRY(__entry)\nOUTPUT_FORMAT(\"elf32-tradlittlemips\", \"elf32-tradbigmips\", \"elf32-tradlittlemips\")\nGROUP(-lc -luhi -lgcc -lhal)\nSEARCH_DIR(.)\n__DYNAMIC  =  0;\nSTARTUP(crt0.o)\n\/* Force the exception handler to be registered *\/\nEXTERN(__register_excpt_handler)\n\/* Force the exception handler to be included in the link *\/\nEXTERN(__exception_entry)\n\/*\n * Require verbose exceptions. This can be changed to pull in\n * __exception_handle_quiet to reduce code size but be less\n * informative\n *\/\nEXTERN(__exception_handle_verbose)\n\/* Force the interrupt handlers to tbe included in the link *\/\nEXTERN(__isr_vec)\n\/* Require the UHI getargs support *\/\nEXTERN(__getargs)\n\n\/*\n * Set the location of the top of the stack.  A value of 0 means\n * that it will be automatically placed at the highest address\n * available as described by the __memory_* setttings\n *\/\nPROVIDE (__stack = 0);\n\n\/* Size of the memory returned by _get_ram_range *\/\nPROVIDE (__memory_size = 512K);\n\n\/* Base of the memory returned by _get_ram_range *\/\nPROVIDE (__memory_base = 0x80000000);\n\n\/* Stride length for tlb software invalidate for tlbinvf\n * (mipsXXr3+). Some MIPS implementations may layout the sets\/ways\n * differently in the index register. Either sets LSB or ways LSB.\n *\n * By setting this to 1 we presume that sets come first. The default boot\n * code will decrement this value from the Number of TLB entries.\n *\/\nPROVIDE (__tlb_stride_length = 1);\n\n\/* By default, XPA is not used even if available. To enable XPA,\n * __enable_xpa should be 1.\n *\/\nPROVIDE (__enable_xpa = 0);\n\n\/*\n * 0 = Do not use exception handler present in boot for UHI\n * 1 = Use exception handler present in boot for UHI if BEV is 0 at\n *     startup\n * 2 = Always use exception handler present in boot for UHI\n *\/\nPROVIDE (__use_excpt_boot = 0);\n\/*\n * Include the code to be able to return to boot context.  This is\n * necessary if __use_excpt_boot != 0.\n *\/\nEXTERN (__register_excpt_boot);\n\nASSERT (DEFINED(__register_excpt_boot) || __use_excpt_boot == 0,\n\t\"Registration for boot context is required for UHI chaining\")\n\n\/* Control if subnormal floating-point values are flushed to zero in\n   hardware.  This applies to both FPU and MSA operations.  *\/\nPROVIDE (__flush_to_zero = 1);\n\n\/* Set up the public symbols depending on whether the user has chosen\n   quiet or verbose exception handling above *\/\nEXTERN (__exception_handle);\nPROVIDE(__exception_handle = (DEFINED(__exception_handle_quiet)\n\t\t\t\t      ? __exception_handle_quiet\n\t\t\t\t      : __exception_handle_verbose));\nPROVIDE(_mips_handle_exception = __exception_handle);\n\n\/*\n * Initalize some symbols to be zero so we can reference them in the\n * crt0 without core dumping. These functions are all optional, but\n * we do this so we can have our crt0 always use them if they exist.\n * This is so BSPs work better when using the crt0 installed with gcc.\n * We have to initalize them twice, so we multiple object file\n * formats, as some prepend an underscore.\n *\/\nPROVIDE (hardware_exit_hook = 0);\nPROVIDE (hardware_hazard_hook = 0);\nPROVIDE (hardware_init_hook = 0);\nPROVIDE (software_init_hook = 0);\n\n\/* The default base address for application flash code is 0x9D001000 *\/\nPROVIDE (__app_start = 0x9D001000) ;\n\/* Set default vector spacing to 32 bytes. *\/\nPROVIDE (__isr_vec_space = 32);\n\/* Leave space for 9 vector entries by default. 8 entry points and one\n   fallback handler. *\/\nPROVIDE (__isr_vec_count = 9);\n\/*\n * The start of boot flash must be set if including boot code.  By default\n * the use of boot code will mean that application code is copied\n * from flash to RAM at runtime before being executed.\n *\/\nPROVIDE (__lower_boot_flash_start = DEFINED(__reset_vector) ? 0xbfc00000 : __app_start);\n\nPROVIDE (__boot_flash1_start = 0xbfc40000);\n\nPROVIDE (__boot_flash2_start = 0xbfc60000);\n\nPROVIDE (__bev_override = 0x9fc00000);\n\nPROVIDE (__flash_vector_start = 0x9D000000);\n\nPROVIDE (__flash_app_start = 0x9D001000);\n\nSECTIONS\n{\n  \/* Start of bootrom *\/\n  .lowerbootflashalias __bev_override : \/* Runs uncached (from 0xBfc00000) until I$ is\n\t\t\t       initialized. *\/\n  AT (__lower_boot_flash_start)\n  {\n    __base = .;\n\n    *(.reset)\t\t\/* Reset entry point. *\/\n    *(.boot)\t\t\/* Boot code. *\/\n    . = ALIGN(8);\n\n    . = __base + 0xff40; \/*Alternate Config bits (lower Alias)*\/\n    KEEP(*(.adevcfg3_la))\n    KEEP(*(.adevcfg2_la))\n    KEEP(*(.adevcfg1_la))\n    KEEP(*(.adevcfg0_la))\n    . = __base + 0xff5c;\n    KEEP(*(.adevcp0_la))\n    . = __base + 0xff6c;\n    KEEP(*(.adevsign_la))\n\n    . = __base + 0xffc0; \/*Config bits (lower Alias)*\/\n    KEEP(*(.devcfg3_la))\n    KEEP(*(.devcfg2_la))\n    KEEP(*(.devcfg1_la))\n    KEEP(*(.devcfg0_la))\n    . = __base + 0xffdc;\n    KEEP(*(.devcp0_la))\n    . = __base + 0xffec;\n    KEEP(*(.devsign_la))\n\n    . = __base + 0xfff0;\n    KEEP(*(.seq_la))\n  } = 0xFFFFFFFF\n\n  \/*\n   * We only add this block to keep the MPLAB programmer happy\n   * It seems to want the config regs values in the non aliased locations\n   *\/\n  . = __base + 0x40000 + 0xff40;\n  .bootflash1 :\n  AT(__boot_flash1_start + 0xff40)\n  {\n    __altbase = .;\n\n    . = __altbase; \/* Alternate Config Bits (boot flash 1) *\/\n    KEEP(*(.adevcfg3_b1))\n    KEEP(*(.adevcfg2_b1))\n    KEEP(*(.adevcfg1_b1))\n    KEEP(*(.adevcfg0_b1))\n    . = __altbase + 0x1c;\n    KEEP(*(.adevcp0_b1))\n    . = __altbase + 0x2c;\n    KEEP(*(.adevsign_b1))\n\n    . = __altbase + 0x80;\n    KEEP(*(.devcfg3_b1))\n    KEEP(*(.devcfg2_b1))\n    KEEP(*(.devcfg1_b1))\n    KEEP(*(.devcfg0_b1))\n    . = __altbase + 0x9c;\n    KEEP(*(.devcp0_b1))\n    . = __altbase + 0xAc;\n    KEEP(*(.devsign_b1))\n    . = __altbase + 0xB0;\n    KEEP(*(.seq_b1))\n   }  = 0xFFFFFFFF\n\n  \/*\n   * We only add this block to keep the MPLAB programmer happy\n   * It seems to want the config regs values in the non aliased locations\n   *\/\n  . = __base + 0x60000 + 0xff40;\n  .bootflash2 :\n  AT(__boot_flash2_start + 0xff40)\n  {\n    __altbase = .;\n\n    . = __altbase; \/* Alternate Config Bits (boot flash 1) *\/\n    KEEP(*(.adevcfg3_b2))\n    KEEP(*(.adevcfg2_b2))\n    KEEP(*(.adevcfg1_b2))\n    KEEP(*(.adevcfg0_b2))\n    . = __altbase + 0x1c;\n    KEEP(*(.adevcp0_b2))\n     . = __altbase + 0x2c;\n    KEEP(*(.adevsign_b2))\n\n    . = __altbase + 0x80;\n    KEEP(*(.devcfg3_b2))\n    KEEP(*(.devcfg2_b2))\n    KEEP(*(.devcfg1_b2))\n    KEEP(*(.devcfg0_b2))\n    . = __altbase + 0x9c;\n    KEEP(*(.devcp0_b2))\n    . = __altbase + 0xAc;\n    KEEP(*(.devsign_b2))\n    . = __altbase + 0xB0;\n    KEEP(*(.seq_b2))\n  } = 0xFFFFFFFF\n\n  \/* Start of the application *\/\n  .exception_vector ALIGN(__flash_vector_start, 0x1000) :\n  AT (__flash_vector_start)\n  {\n    PROVIDE (__excpt_ebase = ABSOLUTE(.));\n    __base = .;\n    KEEP(* (.text.__exception_entry))\n\n    . = __base + 0x200;\n    KEEP(* (SORT(.text.__isr_vec*)))\n    \/* Leave space for all the vector entries *\/\n    . = __base + 0x200 + (__isr_vec_space * __isr_vec_count);\n    ASSERT(__isr_vec_space == (DEFINED(__isr_vec_sw0)\n\t\t\t       ? __isr_vec_sw1 - __isr_vec_sw0\n\t\t\t       : __isr_vec_space),\n\t   \"Actual ISR vector spacing does not match __isr_vec_space\");\n    ASSERT(__base + 0x200 == (DEFINED(__isr_vec_sw0)\n\t\t\t      ? __isr_vec_sw0 & 0xfffffffe : __base + 0x200),\n\t   \"__isr_vec_sw0 is not placed at EBASE + 0x200\");\n    . = ALIGN(8);\n  } = 0\n\n  . = __flash_app_start;\n\n  .text : {\n     _ftext = . ;\n    PROVIDE (eprol  =  .);\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t.*)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n  }\n  .init : {\n    KEEP (*(.init))\n  }\n  .fini : {\n    KEEP (*(.fini))\n  }\n  .rel.sdata : {\n    PROVIDE (__runtime_reloc_start = .);\n    *(.rel.sdata)\n    PROVIDE (__runtime_reloc_stop = .);\n  }\n  PROVIDE (etext  =  .);\n  _etext  =  .;\n\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame : { KEEP (*(.eh_frame)) }\n  .gcc_except_table : { *(.gcc_except_table*) }\n  .jcr : { KEEP (*(.jcr)) }\n  .ctors    :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n\n    KEEP (*crtbegin.o(.ctors))\n\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n\n  .dtors    :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  . = .;\n  .MIPS.abiflags : {\n    __MIPS_abiflags_start = .;\n    *(.MIPS.abiflags)\n    __MIPS_abiflags_end = .;\n  }\n  .rodata : {\n    *(.rdata)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n  }\n  _rom_data_copy = .;\n\n  .data ALIGN(__memory_base + 0x1000, 16) :\n  AT (_rom_data_copy)\n  {\n     _fdata = .;\n\n      *(.data)\n      *(.data.*)\n      *(.gnu.linkonce.d.*)\n\n    . = ALIGN(8);\n    _gp = . + 0x8000;\n    __global = _gp;\n\n      *(.lit8)\n      *(.lit4)\n      *(.sdata)\n      *(.sdata.*)\n      *(.gnu.linkonce.s.*)\n  }\n  . = ALIGN(4);\n  PROVIDE (edata  =  .);\n  _edata  =  .;\n  _fbss = .;\n  .sbss : {\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n  }\n  .bss : {\n    _bss_start = . ;\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n  }\n\n  . = ALIGN(4);\n  PROVIDE (end = .);\n  _end = .;\n  \/* Now place the data that is only needed within start.S and can be\n     overwritten by the heap.  *\/\n  .startdata : {\n    *(.startdata)\n  }\n\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to\n     the beginning of the section so we begin them at 0.  *\/\n\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n\n  \/* Special sections generated by gcc *\/\n  \/* Newer GNU linkers strip by default *\/\n  .mdebug.abi32            0 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32           0 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64            0 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64           0 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32           0 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64           0 : { KEEP(*(.mdebug.eabi64)) }\n  .gcc_compiled_long32     0 : { KEEP(*(.gcc_compiled_long32)) }\n  .gcc_compiled_long64     0 : { KEEP(*(.gcc_compiled_long64)) }\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"7b7a73092628fe4d6fda595d4384aa6144a8238a","subject":"Architecture: Core: Remove unused linker file.","message":"Architecture: Core: Remove unused linker file.","repos":"chrism333\/xpcc,chrism333\/xpcc,chrism333\/xpcc,chrism333\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc","old_file":"src\/xpcc\/architecture\/platform\/driver\/core\/cortex\/memory_sections.ld","new_file":"src\/xpcc\/architecture\/platform\/driver\/core\/cortex\/memory_sections.ld","new_contents":"","old_contents":"\/*\r\n *                           LINKER  SCRIPT\r\n *\r\n * The Linker Script defines how the code and data emitted by the GNU C compiler\r\n * and assembler are  to be loaded into memory (code goes into ROM, variables\r\n * go into RAM).\r\n * \r\n * Any symbols defined in the Linker Script are automatically global and\r\n * available to the rest of the program.\r\n * \r\n * Example for STM32F103xB:\r\n * \r\n *                          MEMORY MAP (RAM)\r\n *                |                                 | 0x200xxxxx <---- __ram_end, __head_end\r\n *                |---------------------------------| \r\n *                |                                 | \r\n *                |               ^                 | \r\n *                |               |                 | \r\n *                |            Heap Area            | \r\n *                |         (grows upwards)         | \r\n *                |                                 | <------- __head_start\r\n *                |---------------------------------| <------- __handler_stack_top, __stack_end\r\n *                |                                 | \r\n *                |    Handler\/Main Stack (msp)     |\r\n *                |       (grows downwards)         | \r\n *                |               |                 | \r\n *                |               v                 |  \r\n *                |                                 |  \r\n *                |---------------------------------| <------- __thread_stack_top\r\n *                |                                 | \r\n *                |    Thread\/Process Stack (psp)   |\r\n *                |       (grows downwards)         | \r\n *                |               |                 | \r\n *                |               v                 | \r\n *                |                                 | <------- __stack_start\r\n *      +-------> |---------------------------------| <------- __noinit_end\r\n *      |         |                                 |\r\n *   .noinit      |     Global data not cleared     |\r\n *      |         |           after reset           | <------- __noinit_start\r\n *      +-------> |---------------------------------| <------- __bss_end\r\n *      |         |                                 |\r\n *    .bss        |     uninitialized variables     |\r\n *      |         |                                 | <------- __bss_start\r\n *      +-------> |---------------------------------| <------- __data_end\r\n *      |         |                                 |\r\n *      |         |                                 |\r\n *    .data       |     initialized variables       |\r\n *      |         |                                 |\r\n *      |         |                                 | <------- __data_start\r\n *      +-------> |---------------------------------| <------- __fastcode_end\r\n *      |         |     C\/C++-Functions in RAM      | \r\n *      |         |    (e.g. Interrupt Handler)     | \r\n *  .fastcode     | ------------------------------- |\r\n *      |         |   Interrupt Vectors (.vectors)  |\r\n *      |         |        (if re-mapped)           |\r\n *      +-------> |---------------------------------| 0x20000000 <--- __ram_start, __fastcode_start\r\n * \r\n * \r\n *                         MEMORY MAP (Flash)\r\n *                |                                 |\r\n *                |---------------------------------| 0x08020000\r\n *                |                                 | 0x0801FFFF\r\n *                |                                 |\r\n *                |                                 |\r\n *                |          Unused flash           |\r\n *                |                                 |\r\n *                |                                 |\r\n *                |                                 |\r\n *     +--------> |---------------------------------|\r\n *     |          |                                 |\r\n *     |          |                                 |\r\n *     |          |                                 |\r\n *   .data        |      copy of .data area         |\r\n *     |          |                                 |\r\n *     |          |                                 |\r\n *     |          |                                 | <------- __data_load\r\n *     +--------> |---------------------------------| \r\n *     |          |    Static Constructors (C++)    |\r\n *     |          | ------------------------------- |\r\n *     |          |                                 |\r\n *   .text        |                                 |\r\n *     |          |          C\/C++ code             |\r\n *     |          |                                 |\r\n *     |          |                                 |\r\n *     +--------> |---------------------------------| \r\n *     |          |                                 | \r\n * .fastcode      |     C-Functions to be loaded    | \r\n *     |          |           into RAM              | <------- __fastcode_load\r\n *     +--------> |---------------------------------| \r\n *     |          |                                 | \r\n *  .reset        |        Interrupt Vectors        | \r\n *     |          |                                 | \r\n *     +--------> |---------------------------------| 0x08000000\r\n * \r\n * The first two words (32-bit) in the Flash defines the initial stack pointer\r\n * location and the reset handler location.\r\n * \r\n * Usage:\r\n *   Use __attribute__ ((long_call, section (\".fastcode\"))) to move functions\r\n *   into the RAM.\r\n *\/\r\n\r\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\n\r\n\/* First executable instruction in an output file *\/\r\nENTRY(Reset_Handler)\r\n\r\n\/* force linker to include the syscalls from libxpcc.a *\/\r\nEXTERN(_sbrk_r)\r\nEXTERN(_init)\r\n\r\nPROVIDE(__ram_start = ORIGIN(RAM));\r\nPROVIDE(__ram_end   = ORIGIN(RAM) + LENGTH(RAM));\r\nPROVIDE(__heap_end  = ORIGIN(RAM) + LENGTH(RAM));\r\n\r\n\/* Used for interrupt handlers *\/\r\nHANDLER_STACK_SIZE = 124 + 4;\r\n\r\n\/* Used during normal program execution *\/\r\nTHREAD_STACK_SIZE = 508 + 4;\r\n\r\nSECTIONS\r\n{\r\n\t.reset :\r\n\t{\r\n\t\t\/* Initial stack address, Reset and NMI handler *\/\r\n\t\tKEEP(*(.reset))\r\n\t\t. = ALIGN(4);\r\n\t} >ROM\r\n\t\r\n\t.fastcode :\r\n\t{\r\n\t\t__fastcode_load = LOADADDR (.fastcode);\t\t\/* address in ROM *\/\r\n\t\t__fastcode_start = .;\t\t\t\t\t\t\/* address in RAM *\/\r\n\t\t\r\n\t\t\/* used for vectors remapped to RAM *\/\r\n\t\tKEEP(*(.vectors))\r\n\t\tKEEP(*(.fastcode))\r\n\t\t\r\n\t\t*(.glue_7t)\t\t\/* TODO: are these useful here or better only in .text? *\/\r\n\t\t*(.glue_7)\r\n\t\t\r\n\t\t. = ALIGN (4);\r\n\t\t__fastcode_end = .;\r\n\t} >RAM AT>ROM\r\n\t\r\n\t.text :\r\n\t{\r\n\t\t\/* Create a symbol for each input file in the current section, set to\r\n\t\t * the address of the first byte of data written from that input file.\r\n\t\t * *\/\r\n\t\tCREATE_OBJECT_SYMBOLS\r\n\t\t\r\n\t\t\/* ABOUT .gnu.linkonce.* sections\r\n\t\t * \r\n\t\t * Unlike other input section types a section that is prefixed with\r\n\t\t * .gnu.linkonce. is treated differently by the linker. If for example\r\n\t\t * .gnu.linkonce.t.abc appears in two or more different object files then \r\n\t\t * the linker will only keep one and discard the others.\r\n\t\t * \r\n\t\t * This is done is to support C++ vague linkage.  It is related to\r\n\t\t * C++'s ODR (One Definition Rule), and can cause surprises if ODR is\r\n\t\t * violated.\r\n\t\t * \r\n\t\t * For example if you compile with RTTI turned on, you'll see linkonce\r\n\t\t * sections for all the RTTI of all the classes in the translation unit\r\n\t\t * of that object file.\r\n\t\t * Or if you keep generated functions for inline functions \r\n\t\t * (-fkeep-inline-functions), you'll see linkonce sections for all the\r\n\t\t * emitted kept inline functions.\r\n\t\t * \r\n\t\t * Might be replaced by ELF section groups in newer versions of ld.\r\n\t\t *\/\r\n\t\t*(.text .text.* .gnu.linkonce.t.*)\r\n\t\t. = ALIGN(4);\r\n\t\t\r\n\t\t\/* Position independent code will call non-static functions via the\r\n\t\t * Procedure Linkage Table or PLT. This PLT does not exist in .o files.\r\n\t\t * In a .o file, use of the PLT is indicated by a special relocation.\r\n\t\t * When the program linker processes such a relocation, it will create\r\n\t\t * an entry in the PLT\r\n\t\t *\/\r\n\t\t*(.plt)\r\n\t\t. = ALIGN(4);\r\n\t\t\r\n\t\t\/* These sections glue together ARM and Thumb code. \r\n\t\t * .glue_7 is used for ARM code calling Thumb code, and .glue_7t is\r\n\t\t * used for Thumb code calling ARM code.\r\n\t\t *\/\r\n\t\t*(.glue_7t)\r\n\t\t*(.glue_7)\r\n\t\t\r\n\t\t\/* .ARM.extab names a section that contains exception unwinding information *\/\r\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\t\t\r\n\t\t\/* .gcc_except_table is an input section name, which gcc uses\r\n\t\t * for information used to unwind the stack when an exception occurs. *\/\r\n\t\t*(.gcc_except_table)\r\n\t\t\r\n\t\t\/* When gcc generates code that handles exceptions, it produces tables\r\n\t\t * that describe how to unwind the stack. These tables are found in\r\n\t\t * the .eh_frame and .eh_frame_hdr section.\r\n\t\t * \r\n\t\t * See http:\/\/www.airs.com\/blog\/archives\/460 or\r\n\t\t * http:\/\/www.codesourcery.com\/public\/cxx-abi\/exceptions.pdf\r\n\t\t *\/\r\n\t\t*(.eh_frame_hdr)\r\n\t\t*(.eh_frame)\r\n\t\t\r\n\t\t*(.gnu.warning)\r\n\t} >ROM\r\n\t\r\n\t.rodata : ALIGN (4)\r\n\t{\r\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\tKEEP(*(.init))\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\r\n\t\tKEEP (*(.preinit_array))\r\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\r\n\t\tKEEP (*(SORT(.init_array.*)))\r\n\t\tKEEP (*(.init_array))\r\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\tKEEP(*(.fini))\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\r\n\t\tKEEP (*(.fini_array))\r\n\t\tKEEP (*(SORT(.fini_array.*)))\r\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\r\n\t\t\r\n\t\t\/* These are for static constructors and destructors under ELF *\/\r\n\t\tPROVIDE(__ctors_start__ = .);\r\n\t\tKEEP (*crtbegin.o(.ctors))\r\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n\t\tKEEP (*(SORT(.ctors.*)))\r\n\t\tKEEP (*crtend.o(.ctors))\r\n\t\tPROVIDE(__ctors_end__ = .);\r\n\r\n\t\t\/*PROVIDE(__dtors_start__ = .);\r\n\t\tKEEP (*crtbegin.o(.dtors))\r\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n\t\tKEEP (*(SORT(.dtors.*)))\r\n\t\tKEEP (*crtend.o(.dtors))\r\n\t\tPROVIDE(__dtors_end__ = .);*\/\r\n\t\t\r\n\t\t*(.init .init.*)\r\n\t\t*(.fini .fini.*)\r\n\t} >ROM\r\n\t\r\n\t\/* .ARM.exidx names a section that contains index entries for\r\n\t * section unwinding. It is sorted, so has to go in its own output section.\r\n\t *\/\r\n\t.ARM.exidx :\r\n\t{\r\n\t\t__exidx_start = .;\r\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\t\t__exidx_end = .;\r\n\t} >ROM\r\n\t_etext = .;\r\n\t\r\n\t\/* initialized variables *\/\r\n\t.data : ALIGN (8)\r\n\t{\r\n\t\t__data_load = LOADADDR (.data);\t\t\/* address in ROM *\/\r\n\t\t__data_start = .;\t\t\t\t\t\/* address in RAM *\/\r\n\t\t\r\n\t\tKEEP(*(.jcr))\r\n\t\t*(.got.plt) *(.got)\r\n\t\t*(.shdata)\r\n\t\t\r\n\t\t*(.data .data.* .gnu.linkonce.d.*)\r\n\t\t\r\n\t\t. = ALIGN (4);\r\n\t\t__data_end = .;\r\n\t} >RAM AT>ROM\r\n\t\r\n\t\/* uninitialized variables *\/\r\n\t.bss :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t__bss_start = . ;\r\n\t\t\r\n\t\t*(.shbss)\r\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\r\n\t\t*(COMMON)\r\n\t\t\r\n\t\t. = ALIGN (4);\r\n\t\t__bss_end = .;\r\n\t} >RAM\r\n\t\r\n\t\/* Global data not cleared after reset.  *\/\r\n\t.noinit :\r\n\t{\r\n\t\t. = ALIGN (4);\r\n\t\tPROVIDE (__noinit_start = .);\r\n\t\t\r\n\t\tKEEP(*(.noinit*))\r\n\t\t\r\n\t\t. = ALIGN (4);\r\n\t\tPROVIDE (__noinit_end = .);\r\n\t} >RAM\r\n\t\r\n\t.stack :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t__stack_start = . ;\r\n\t\t\r\n\t\t. += THREAD_STACK_SIZE;\r\n\t\t. = ALIGN (4);\r\n\t\t__thread_stack_top = . ;\r\n\t\t\r\n\t\t. += HANDLER_STACK_SIZE;\r\n\t\t. = ALIGN (4);\r\n\t\t__handler_stack_top = . ;\r\n\t\t\r\n\t\t__stack_end = .;\r\n\t\t\r\n\t\t. = ALIGN (4);\r\n\t\tPROVIDE (__heap_start = .);\r\n\t} >RAM\r\n\t\r\n\t. = ALIGN(4);\r\n\t_end = . ;\r\n\t__end = . ;\r\n\tPROVIDE(end = .);\r\n\t\r\n\t\/* Stabs debugging sections.  *\/\r\n\t.stab          0 : { *(.stab) }\r\n\t.stabstr       0 : { *(.stabstr) }\r\n\t.stab.excl     0 : { *(.stab.excl) }\r\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\r\n\t.stab.index    0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment       0 : { *(.comment) }\r\n\t\r\n\t\/* DWARF debug sections.\r\n\t Symbols in the DWARF debugging sections are relative to the beginning\r\n\t of the section so we begin them at 0.  *\/\r\n\t\r\n\t\/* DWARF 1 *\/\r\n\t.debug          0 : { *(.debug) }\r\n\t.line           0 : { *(.line) }\r\n\t\/* GNU DWARF 1 extensions *\/\r\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\r\n\t\/* DWARF 1.1 and DWARF 2 *\/\r\n\t.debug_aranges  0 : { *(.debug_aranges) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t\/* DWARF 2 *\/\r\n\t.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\r\n\t.debug_line     0 : { *(.debug_line) }\r\n\t.debug_frame    0 : { *(.debug_frame) }\r\n\t.debug_str      0 : { *(.debug_str) }\r\n\t.debug_loc      0 : { *(.debug_loc) }\r\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\r\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\r\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\r\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\r\n\t.debug_typenames 0 : { *(.debug_typenames) }\r\n\t.debug_varnames  0 : { *(.debug_varnames) }\r\n\t.debug_varnames  0 : { *(.debug_varnames) }\r\n\t\r\n\t.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\r\n\t.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\r\n\t\/DISCARD\/ : { *(.note.GNU-stack)  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"e71f99f94276bc9e2bafc97e2341eb1a70a174d0","subject":"[x6818]working on x6818...","message":"[x6818]working on x6818...\n","repos":"xboot\/xboot,xboot\/xboot","old_file":"src\/arch\/arm64\/mach-x6818\/xboot.ld","new_file":"src\/arch\/arm64\/mach-x6818\/xboot.ld","new_contents":"OUTPUT_FORMAT(\"elf64-littleaarch64\", \"elf64-littleaarch64\", \"elf64-littleaarch64\")\r\nOUTPUT_ARCH(\"aarch64\")\r\nENTRY(_start)\r\n\r\nSTACK_SIZE\t= 0x8000;\r\n\r\nMEMORY\r\n{\r\n\trom(rx) : org = 0x43c00000, len = 0x02000000\t\/* 32 MB *\/\r\n\tram(rwx): org = 0x45100000, len = 0x0a000000\t\/* 160 MB *\/\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.image_start :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__image_start = .);\r\n\t} > rom\r\n\r\n\t.text :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__text_start = .);\r\n\t\t.obj\/arch\/arm64\/mach-x6818\/start.o (.text*)\r\n\t\t.obj\/arch\/arm64\/mach-x6818\/debug.o (.text*)\r\n\t\t*(.text*)\r\n\t\t*(.init.text)\r\n    \t*(.exit.text)\r\n\t\t*(.note.gnu.build-id)\r\n\t\t*(.iplt)\r\n\t\tPROVIDE(__text_end = .);\r\n\t} > rom\r\n\r\n\t.ksymtab :\r\n\t{\r\n\t    . = ALIGN(8);\r\n    \tPROVIDE(__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE(__ksymtab_end = .);\r\n\t} > rom\r\n\r\n\t.initcall :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE(__initcall_end = .);\r\n\t} > rom\r\n\r\n\t.exitcall :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE(__exitcall_end = .);\r\n\t} > rom\r\n\r\n\t.romdisk :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE(__romdisk_end = .);\r\n\t} > rom\r\n\r\n\t.rodata :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__rodata_start = .);\r\n\t\t*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\r\n\t\tPROVIDE(__rodata_end = .);\r\n\t} > rom\r\n\r\n\t.data_shadow :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__data_shadow_start = .);\r\n\t\tPROVIDE(__data_shadow_end = (. + SIZEOF (.data)) );\r\n\t} > rom\r\n\r\n\t.image_end :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__image_end = .);\r\n\t} > rom\r\n\r\n\t.data : AT(ADDR(.data_shadow))\r\n\t{\r\n\t\tPROVIDE(__data_start = .);\t\r\n\t\t*(.data*)\r\n  \t\tPROVIDE(__data_end = .);\r\n\t} > ram\r\n\r\n\t.bss (NOLOAD) :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__bss_start = .);\r\n\t\t*(.bss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__bss_end = .);\r\n\t} > ram\r\n\r\n\t.heap (NOLOAD) :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__heap_start = .);\r\n\t\t*(.heap*)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__heap_end = .);\r\n\t} > ram\r\n\t\r\n\t.stack (NOLOAD) :\r\n\t{\r\n\t\t. = ALIGN(16);\r\n\t\tPROVIDE(__stack_start = .);\r\n\t\t. += STACK_SIZE;\r\n\t\t. = ALIGN(16);\r\n\t\tPROVIDE(__stack_end = .);\r\n\t} > ram\r\n\r\n\t\/DISCARD\/ : { *(.dynsym) }\r\n\t\/DISCARD\/ : { *(.dynstr*) }\r\n\t\/DISCARD\/ : { *(.dynamic*) }\r\n\t\/DISCARD\/ : { *(.plt*) }\r\n\t\/DISCARD\/ : { *(.interp*) }\r\n\t\/DISCARD\/ : { *(.gnu*) }\r\n}\r\n","old_contents":"OUTPUT_FORMAT(\"elf64-littleaarch64\", \"elf64-littleaarch64\", \"elf64-littleaarch64\")\r\nOUTPUT_ARCH(\"aarch64\")\r\nENTRY(_start)\r\n\r\nSTACK_SIZE\t= 0x8000;\r\n\r\nMEMORY\r\n{\r\n\trom (rx)\t: org = 0x43c00000, len = 0x02000000\t\/* 32 MB *\/\r\n\tram (rwx)\t: org = 0x45100000, len = 0x0a000000\t\/* 160 MB *\/\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.image_start :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__image_start = .);\r\n\t} > rom\r\n\r\n\t.text :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__text_start = .);\r\n\t\t.obj\/arch\/arm64\/mach-x6818\/start.o (.text*)\r\n\t\t.obj\/arch\/arm64\/mach-x6818\/debug.o (.text*)\r\n\t\t*(.text*)\r\n\t\t*(.init.text)\r\n    \t*(.exit.text)\r\n    \t*(.note.gnu.build-id)\r\n    \t*(.iplt)\r\n\t\tPROVIDE (__text_end = .);\r\n\t} > rom\r\n\r\n\t.ksymtab :\r\n\t{\r\n\t    . = ALIGN(8);\r\n    \tPROVIDE (__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE (__ksymtab_end = .);\r\n\t} > rom\r\n\r\n\t.initcall :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE (__initcall_end = .);\r\n\t} > rom\r\n\r\n\t.exitcall :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE (__exitcall_end = .);\r\n\t} > rom\r\n\r\n\t.romdisk :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE (__romdisk_end = .);\r\n\t} > rom\r\n\r\n\t.rodata :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__rodata_start = .);\r\n\t\t*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\r\n\t\tPROVIDE (__rodata_end = .);\r\n\t} > rom\r\n\r\n\t.data_shadow :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__data_shadow_start = .);\r\n\t\tPROVIDE (__data_shadow_end = (. + SIZEOF (.data)) );\r\n\t} > rom\r\n\r\n\t.image_end :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__image_end = .);\r\n\t} > rom\r\n\r\n\t.data : AT(ADDR(.data_shadow))\r\n\t{\r\n\t\tPROVIDE (__data_start = .);\t\r\n\t\t*(.data*)\r\n  \t\tPROVIDE (__data_end = .);\r\n\t} > ram\r\n\r\n\t.bss (NOLOAD) :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__bss_start = .);\r\n\t\t*(.bss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__bss_end = .);\r\n\t} > ram\r\n\r\n\t.heap (NOLOAD) :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_start = .);\r\n\t\t*(.heap*)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_end = .);\r\n\t} > ram\r\n\t\r\n\t.stack (NOLOAD) :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_start = .);\r\n\t\t. += STACK_SIZE;\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_end = .);\r\n\t} > ram\r\n\r\n\t\/DISCARD\/ : { *(.dynsym) }\r\n\t\/DISCARD\/ : { *(.dynstr*) }\r\n\t\/DISCARD\/ : { *(.dynamic*) }\r\n\t\/DISCARD\/ : { *(.plt*) }\r\n\t\/DISCARD\/ : { *(.interp*) }\r\n\t\/DISCARD\/ : { *(.gnu*) }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8f7b3435083cd09ee7d1f36299d4be7d41a8e2ae","subject":"kernel.ld: .init section is not necessary","message":"kernel.ld: .init section is not necessary\n","repos":"smaeul\/quarto","old_file":"scripts\/kernel.ld","new_file":"scripts\/kernel.ld","new_contents":"\/*\n * scripts\/kernel.ld - Main quarto linker script\n *\n * Copyright 2012-2013 Samuel Holland <samuel@sholland.net>\n *\/\n\nOUTPUT_FORMAT(elf32-x86-64)\nOUTPUT_ARCH(i386:x86-64)\n\nENTRY (__entry)\n\nHM_OFFSET = 0xFFFFFF8000000000;\n\nSECTIONS\n{\n    . = 0x00000000001000A0;\t\/* Reserve enough space for ELF header *\/\n\n    __start = .;\n\n    .loader : ALIGN(0x10)\n    {\n\t__loader_start = .;\n\t*(.loader)\t\t\/* BIOS and multiboot loader code *\/\n\t*(.loaderdata)\t\t\/* GDT, its pointer struct, and friends *\/\n\t__loader_end = .;\n    }\n\n    . += HM_OFFSET;\t\t\/* Move to the top of virtual memory *\/\n\n    .text : AT(ADDR(.text) - HM_OFFSET)\n    {\n\t__text_start = .;\n\t*(.text*)\t\t\/* Normal 64-Bit Code *\/\n\t__text_end = .;\n\t__multiboot_text_end = . - HM_OFFSET;\n    }\n\n    .data : AT(ADDR(.data) - HM_OFFSET)\n    {\n\t__data_start = .;\n\t*(.data*)\t\t\/* Global Variables *\/\n\t*(.rodata*)\t\t\/* String Constants *\/\n\t__data_end = .;\n\t__multiboot_data_end = . - HM_OFFSET;\n    }\n\n    .bss : AT(ADDR(.bss) - HM_OFFSET)\n    {\n\t__bss_start = .;\n\t__multiboot_bss_start = . - HM_OFFSET; \/* For 32-bit relocations *\/\n\t*(.loaderbss)\t\t\/* Temporary init data (multiboot struct) *\/\n\t*(.bss*)\t\t\/* Normal Reserved Memory *\/\n\t*(COMMON)\t\t\/* Other Uninitialized Data *\/\n\t__bss_end = .;\n\t__multiboot_bss_end = . - HM_OFFSET;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ :\n    {\n\t*(.comment)\n\t*(.eh_frame)\n\t*(.note*)\n    }\n}\n","old_contents":"\/*\n * scripts\/kernel.ld - Main quarto linker script\n *\n * Copyright 2012-2013 Samuel Holland <samuel@sholland.net>\n *\/\n\nOUTPUT_FORMAT(elf32-x86-64)\nOUTPUT_ARCH(i386:x86-64)\n\nENTRY (__entry)\n\nHM_OFFSET = 0xFFFFFF8000000000;\n\nSECTIONS\n{\n    . = 0x00000000001000A0;\t\/* Reserve enough space for ELF header *\/\n\n    __start = .;\n\n    .loader : ALIGN(0x10)\n    {\n\t__loader_start = .;\n\t*(.loader)\t\t\/* BIOS and multiboot loader code *\/\n\t*(.loaderdata)\t\t\/* GDT, its pointer struct, and friends *\/\n\t__loader_end = .;\n    }\n\n    . += HM_OFFSET;\t\t\/* Move to the top of virtual memory *\/\n\n    .text : AT(ADDR(.text) - HM_OFFSET)\n    {\n\t__text_start = .;\n\t*(.init)\t\t\/* The springboard we jump to in high RAM *\/\n\t*(.text*)\t\t\/* Normal 64-Bit Code *\/\n\t__text_end = .;\n\t__multiboot_text_end = . - HM_OFFSET;\n    }\n\n    .data : AT(ADDR(.data) - HM_OFFSET)\n    {\n\t__data_start = .;\n\t*(.data*)\t\t\/* Global Variables *\/\n\t*(.rodata*)\t\t\/* String Constants *\/\n\t__data_end = .;\n\t__multiboot_data_end = . - HM_OFFSET;\n    }\n\n    .bss : AT(ADDR(.bss) - HM_OFFSET)\n    {\n\t__bss_start = .;\n\t__multiboot_bss_start = . - HM_OFFSET; \/* For 32-bit relocations *\/\n\t*(.loaderbss)\t\t\/* Temporary init data (multiboot struct) *\/\n\t*(.bss*)\t\t\/* Normal Reserved Memory *\/\n\t*(COMMON)\t\t\/* Other Uninitialized Data *\/\n\t__bss_end = .;\n\t__multiboot_bss_end = . - HM_OFFSET;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ :\n    {\n\t*(.comment)\n\t*(.eh_frame)\n\t*(.note*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"db54c2125a9bb8c390493e5cac4f813301d21f5d","subject":"heap and stack test","message":"heap and stack test\n","repos":"maximmbed\/mbed,j-greffe\/mbed-os,theotherjimmy\/mbed,tung7970\/mbed-os,NXPmicro\/mbed,ryankurte\/mbed-os,kjbracey-arm\/mbed,kl-cruz\/mbed-os,nvlsianpu\/mbed,nRFMesh\/mbed-os,tung7970\/mbed-os,fahhem\/mbed-os,arostm\/mbed-os,betzw\/mbed-os,fahhem\/mbed-os,HeadsUpDisplayInc\/mbed,bcostm\/mbed-os,svogl\/mbed-os,c1728p9\/mbed-os,adamgreen\/mbed,andreaslarssonublox\/mbed,pradeep-gr\/mbed-os5-onsemi,tung7970\/mbed-os-1,karsev\/mbed-os,fanghuaqi\/mbed,karsev\/mbed-os,kjbracey-arm\/mbed,fvincenzo\/mbed-os,mbedmicro\/mbed,cvtsi2sd\/mbed-os,mmorenobarm\/mbed-os,svogl\/mbed-os,adustm\/mbed,karsev\/mbed-os,karsev\/mbed-os,adamgreen\/mbed,fahhem\/mbed-os,YarivCol\/mbed-os,CalSol\/mbed,CalSol\/mbed,cvtsi2sd\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,CalSol\/mbed,mikaleppanen\/mbed-os,ryankurte\/mbed-os,svastm\/mbed,RonEld\/mbed,screamerbg\/mbed,karsev\/mbed-os,adamgreen\/mbed,adustm\/mbed,HeadsUpDisplayInc\/mbed,andcor02\/mbed-os,pradeep-gr\/mbed-os5-onsemi,svastm\/mbed,bulislaw\/mbed-os,mmorenobarm\/mbed-os,fanghuaqi\/mbed,bcostm\/mbed-os,tung7970\/mbed-os,netzimme\/mbed-os,nvlsianpu\/mbed,arostm\/mbed-os,nRFMesh\/mbed-os,bulislaw\/mbed-os,screamerbg\/mbed,arostm\/mbed-os,RonEld\/mbed,monkiineko\/mbed-os,mazimkhan\/mbed-os,Archcady\/mbed-os,monkiineko\/mbed-os,HeadsUpDisplayInc\/mbed,netzimme\/mbed-os,RonEld\/mbed,pradeep-gr\/mbed-os5-onsemi,radhika-raghavendran\/mbed-os5.1-onsemi,svogl\/mbed-os,nvlsianpu\/mbed,NXPmicro\/mbed,netzimme\/mbed-os,monkiineko\/mbed-os,fahhem\/mbed-os,fahhem\/mbed-os,cvtsi2sd\/mbed-os,CalSol\/mbed,infinnovation\/mbed-os,infinnovation\/mbed-os,RonEld\/mbed,YarivCol\/mbed-os,catiedev\/mbed-os,maximmbed\/mbed,svogl\/mbed-os,Archcady\/mbed-os,andreaslarssonublox\/mbed,HeadsUpDisplayInc\/mbed,NXPmicro\/mbed,infinnovation\/mbed-os,HeadsUpDisplayInc\/mbed,tung7970\/mbed-os-1,screamerbg\/mbed,mbedmicro\/mbed,mazimkhan\/mbed-os,andreaslarssonublox\/mbed,tung7970\/mbed-os-1,andcor02\/mbed-os,kjbracey-arm\/mbed,maximmbed\/mbed,nvlsianpu\/mbed,fanghuaqi\/mbed,bulislaw\/mbed-os,RonEld\/mbed,netzimme\/mbed-os,netzimme\/mbed-os,YarivCol\/mbed-os,HeadsUpDisplayInc\/mbed,catiedev\/mbed-os,mbedmicro\/mbed,adustm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,maximmbed\/mbed,infinnovation\/mbed-os,NXPmicro\/mbed,jeremybrodt\/mbed,arostm\/mbed-os,screamerbg\/mbed,mikaleppanen\/mbed-os,NXPmicro\/mbed,jeremybrodt\/mbed,tung7970\/mbed-os,pradeep-gr\/mbed-os5-onsemi,mmorenobarm\/mbed-os,fvincenzo\/mbed-os,c1728p9\/mbed-os,catiedev\/mbed-os,maximmbed\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,NXPmicro\/mbed,screamerbg\/mbed,karsev\/mbed-os,mikaleppanen\/mbed-os,bcostm\/mbed-os,maximmbed\/mbed,kl-cruz\/mbed-os,cvtsi2sd\/mbed-os,arostm\/mbed-os,ryankurte\/mbed-os,infinnovation\/mbed-os,mazimkhan\/mbed-os,andcor02\/mbed-os,betzw\/mbed-os,adustm\/mbed,adamgreen\/mbed,bulislaw\/mbed-os,monkiineko\/mbed-os,nRFMesh\/mbed-os,svogl\/mbed-os,mmorenobarm\/mbed-os,svastm\/mbed,j-greffe\/mbed-os,Archcady\/mbed-os,fanghuaqi\/mbed,mazimkhan\/mbed-os,bcostm\/mbed-os,mmorenobarm\/mbed-os,c1728p9\/mbed-os,RonEld\/mbed,Archcady\/mbed-os,betzw\/mbed-os,mikaleppanen\/mbed-os,betzw\/mbed-os,kl-cruz\/mbed-os,jeremybrodt\/mbed,theotherjimmy\/mbed,infinnovation\/mbed-os,kjbracey-arm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,adustm\/mbed,cvtsi2sd\/mbed-os,adamgreen\/mbed,theotherjimmy\/mbed,tung7970\/mbed-os,c1728p9\/mbed-os,kl-cruz\/mbed-os,fahhem\/mbed-os,mbedmicro\/mbed,theotherjimmy\/mbed,pradeep-gr\/mbed-os5-onsemi,nvlsianpu\/mbed,bcostm\/mbed-os,catiedev\/mbed-os,bulislaw\/mbed-os,tung7970\/mbed-os-1,j-greffe\/mbed-os,andreaslarssonublox\/mbed,jeremybrodt\/mbed,andcor02\/mbed-os,CalSol\/mbed,YarivCol\/mbed-os,kl-cruz\/mbed-os,c1728p9\/mbed-os,betzw\/mbed-os,YarivCol\/mbed-os,nRFMesh\/mbed-os,catiedev\/mbed-os,mazimkhan\/mbed-os,c1728p9\/mbed-os,mazimkhan\/mbed-os,theotherjimmy\/mbed,svastm\/mbed,svogl\/mbed-os,bcostm\/mbed-os,nvlsianpu\/mbed,nRFMesh\/mbed-os,adamgreen\/mbed,bulislaw\/mbed-os,theotherjimmy\/mbed,andcor02\/mbed-os,fvincenzo\/mbed-os,catiedev\/mbed-os,ryankurte\/mbed-os,mikaleppanen\/mbed-os,fvincenzo\/mbed-os,nRFMesh\/mbed-os,j-greffe\/mbed-os,monkiineko\/mbed-os,fanghuaqi\/mbed,ryankurte\/mbed-os,pradeep-gr\/mbed-os5-onsemi,netzimme\/mbed-os,CalSol\/mbed,betzw\/mbed-os,andreaslarssonublox\/mbed,YarivCol\/mbed-os,Archcady\/mbed-os,andcor02\/mbed-os,fvincenzo\/mbed-os,mbedmicro\/mbed,arostm\/mbed-os,jeremybrodt\/mbed,mmorenobarm\/mbed-os,ryankurte\/mbed-os,Archcady\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,tung7970\/mbed-os-1,monkiineko\/mbed-os,j-greffe\/mbed-os,mikaleppanen\/mbed-os,adustm\/mbed,kl-cruz\/mbed-os,cvtsi2sd\/mbed-os,screamerbg\/mbed,j-greffe\/mbed-os,svastm\/mbed","old_file":"hal\/targets\/cmsis\/TARGET_ONSEMI\/TARGET_NCS36510\/TOOLCHAIN_GCC_ARM\/NCS36510.ld","new_file":"hal\/targets\/cmsis\/TARGET_ONSEMI\/TARGET_NCS36510\/TOOLCHAIN_GCC_ARM\/NCS36510.ld","new_contents":"\/*\n * NCS36510 ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x00003000, LENGTH = 0x00000090\n  FLASH (rx)            : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90\n  RAM (rwx)             : ORIGIN = 0x3FFF4000, LENGTH = 48K \n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        . = ALIGN(32);\n        __uvisor_bss_end = .;\n    } > RAM\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assetions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += 0x4000;\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += 0x800 - (. - __StackLimit);\n    } > RAM\n\n    \/* Set stack top to end of RAM *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack);\n    PROVIDE(__stack = __StackTop);\n\n}\n","old_contents":"\/*\n * NCS36510 ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x00003000, LENGTH = 0x00000090\n  FLASH (rx)            : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90\n  RAM (rwx)             : ORIGIN = 0x3FFF4000, LENGTH = 48K \n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        . = ALIGN(32);\n        __uvisor_bss_end = .;\n    } > RAM\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assetions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += 0x4000;\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += 0x800 - (. - __StackLimit);\n    } > RAM\n\n    \/* Set stack top to end of RAM *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack);\n    PROVIDE(__stack = __StackTop);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5f4cf7b908905126c4a38e261ee0e230fa448e25","subject":"nrf5\/boards: Bouncing up heap to 32k  on pca10040 to allow for application to allocate 9600bytes+ framebuffer when using LCD screen (240x320).","message":"nrf5\/boards: Bouncing up heap to 32k  on pca10040 to allow for application to allocate 9600bytes+ framebuffer when using LCD screen (240x320).\n","repos":"tralamazza\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython","old_file":"nrf5\/boards\/nrf52832_aa.ld","new_file":"nrf5\/boards\/nrf52832_aa.ld","new_contents":"\/*\n    GNU linker script for NRF52832 blank w\/ no SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x07F000 \/* 508 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x010000 \/* 64 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 32K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20008000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52832 blank w\/ no SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x07F000 \/* 508 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x010000 \/* 64 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20005000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"81ebbcc212737724601355a77bbc4ba711f50d82","subject":"nrf51\/s120: work around lack of support for 32 KiBy devices","message":"nrf51\/s120: work around lack of support for 32 KiBy devices\n","repos":"pabigot\/bspacm,pabigot\/bspacm,pabigot\/bspacm,pabigot\/bspacm","old_file":"device\/nrf51\/s120v1\/xxac\/memory.ld","new_file":"device\/nrf51\/s120v1\/xxac\/memory.ld","new_contents":"\/* Linker script for Nordic Semiconductor nRF51 variant XXAC\n * 256 kiB flash at 0x0000.0000\n *  32 kiB SRAM  at 0x2000.0000\n *\n * S120 v1 (SDS 1.1) reserves 96 KiBy FLASH, 10 KiBy RAM\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 160k \/* 256 - 96 *\/\n  \/* NB: S120v1 aborts if RAM goes beyond 16 KiBy.\n   * https:\/\/devzone.nordicsemi.com\/question\/24295\/s120-v-101-and-xxac-devices\/ *\/\n  RAM (rwx)  : ORIGIN = 0x20002800, LENGTH = 6k  \/* 32 - 10 *\/\n}\n","old_contents":"\/* Linker script for Nordic Semiconductor nRF51 variant XXAC\n * 256 kiB flash at 0x0000.0000\n *  32 kiB SRAM  at 0x2000.0000\n *\n * S120 v1 (SDS 1.1) reserves 96 KiBy FLASH, 10 KiBy RAM\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 160k \/* 256 - 96 *\/\n  RAM (rwx)  : ORIGIN = 0x20002800, LENGTH = 22k  \/* 32 - 10 *\/\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"841ce1d719766ef17814cf9b7ede8e146b5e11cf","subject":"Fixed: The issue of interrupt vector remapping for GCC_ARM LPC1114","message":"Fixed: The issue of interrupt vector remapping for GCC_ARM LPC1114\n","repos":"mnlipp\/mbed,larks\/mbed,svastm\/mbed,HeadsUpDisplayInc\/mbed,cvtsi2sd\/mbed-os,pradeep-gr\/mbed-os5-onsemi,adamgreen\/mbed,struempelix\/mbed,EmuxEvans\/mbed,tung7970\/mbed-os-1,kjbracey-arm\/mbed,maximmbed\/mbed,ryankurte\/mbed-os,pedromes\/mbed,CalSol\/mbed,monkiineko\/mbed-os,pbrook\/mbed,al177\/mbed,svastm\/mbed,wodji\/mbed,Archcady\/mbed-os,mikaleppanen\/mbed-os,kjbracey-arm\/mbed,kpurusho\/mbed,adustm\/mbed,NitinBhaskar\/mbed,NitinBhaskar\/mbed,Shengliang\/mbed,DanKupiniak\/mbed,svogl\/mbed-os,K4zuki\/mbed,RonEld\/mbed,autopulated\/mbed,NitinBhaskar\/mbed,screamerbg\/mbed,fpiot\/mbed-ats,mikaleppanen\/mbed-os,NitinBhaskar\/mbed,karsev\/mbed-os,rgrover\/mbed,pi19404\/mbed,Marcomissyou\/mbed,betzw\/mbed-os,jferreir\/mbed,naves-thiago\/mbed-midi,devanlai\/mbed,mazimkhan\/mbed-os,brstew\/MBED-BUILD,mnlipp\/mbed,jferreir\/mbed,bcostm\/mbed-os,catiedev\/mbed-os,dbestm\/mbed,mmorenobarm\/mbed-os,mmorenobarm\/mbed-os,bcostm\/mbed-os,jrjang\/mbed,andcor02\/mbed-os,mmorenobarm\/mbed-os,rosterloh\/mbed,bentwire\/mbed,RonEld\/mbed,arostm\/mbed-os,Sweet-Peas\/mbed,rosterloh\/mbed,brstew\/MBED-BUILD,CalSol\/mbed,GustavWi\/mbed,FranklyDev\/mbed,jferreir\/mbed,kjbracey-arm\/mbed,tung7970\/mbed-os,fanghuaqi\/mbed,svogl\/mbed-os,bentwire\/mbed,pedromes\/mbed,nabilbendafi\/mbed,Sweet-Peas\/mbed,pi19404\/mbed,c1728p9\/mbed-os,nabilbendafi\/mbed,Willem23\/mbed,pedromes\/mbed,andcor02\/mbed-os,fpiot\/mbed-ats,fahhem\/mbed-os,bikeNomad\/mbed,netzimme\/mbed-os,andcor02\/mbed-os,ryankurte\/mbed-os,kjbracey-arm\/mbed,cvtsi2sd\/mbed-os,pedromes\/mbed,CalSol\/mbed,rgrover\/mbed,karsev\/mbed-os,jeremybrodt\/mbed,tung7970\/mbed-os-1,ryankurte\/mbed-os,bremoran\/mbed-drivers,pbrook\/mbed,kl-cruz\/mbed-os,jeremybrodt\/mbed,jamesadevine\/mbed,xcrespo\/mbed,kpurusho\/mbed,andreaslarssonublox\/mbed,mmorenobarm\/mbed-os,pi19404\/mbed,j-greffe\/mbed-os,larks\/mbed,CalSol\/mbed,ban4jp\/mbed,nvlsianpu\/mbed,catiedev\/mbed-os,Sweet-Peas\/mbed,mazimkhan\/mbed-os,Marcomissyou\/mbed,ARM-software\/mbed-beetle,pi19404\/mbed,K4zuki\/mbed,K4zuki\/mbed,mbedmicro\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,jpbrucker\/mbed,betzw\/mbed-os,betzw\/mbed-os,alertby\/mbed,nRFMesh\/mbed-os,Marcomissyou\/mbed,betzw\/mbed-os,RonEld\/mbed,Marcomissyou\/mbed,mmorenobarm\/mbed-os,iriark01\/mbed-drivers,Shengliang\/mbed,mbedmicro\/mbed,larks\/mbed,larks\/mbed,getopenmono\/mbed,masaohamanaka\/mbed,catiedev\/mbed-os,catiedev\/mbed-os,masaohamanaka\/mbed,fahhem\/mbed-os,bikeNomad\/mbed,geky\/mbed,hwfwgrp\/mbed,tung7970\/mbed-os-1,kl-cruz\/mbed-os,cvtsi2sd\/mbed-os,pedromes\/mbed,wodji\/mbed,YarivCol\/mbed-os,NXPmicro\/mbed,andcor02\/mbed-os,screamerbg\/mbed,catiedev\/mbed-os,nvlsianpu\/mbed,nRFMesh\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,xcrespo\/mbed,xcrespo\/mbed,adustm\/mbed,getopenmono\/mbed,monkiineko\/mbed-os,al177\/mbed,struempelix\/mbed,EmuxEvans\/mbed,tung7970\/mbed-os,brstew\/MBED-BUILD,Shengliang\/mbed,pradeep-gr\/mbed-os5-onsemi,adamgreen\/mbed,fahhem\/mbed-os,fpiot\/mbed-ats,masaohamanaka\/mbed,adustm\/mbed,karsev\/mbed-os,geky\/mbed,infinnovation\/mbed-os,fanghuaqi\/mbed,Timmmm\/mbed,andreaslarssonublox\/mbed,Archcady\/mbed-os,andcor02\/mbed-os,Tiryoh\/mbed,cvtsi2sd\/mbed-os,infinnovation\/mbed-os,j-greffe\/mbed-os,mnlipp\/mbed,mnlipp\/mbed,rosterloh\/mbed,EmuxEvans\/mbed,Tiryoh\/mbed,netzimme\/mbed-os,infinnovation\/mbed-os,pi19404\/mbed,pbrook\/mbed,larks\/mbed,CalSol\/mbed,HeadsUpDisplayInc\/mbed,adamgreen\/mbed,dbestm\/mbed,arostm\/mbed-os,monkiineko\/mbed-os,mnlipp\/mbed,JasonHow44\/mbed,adustm\/mbed,Timmmm\/mbed,kl-cruz\/mbed-os,autopulated\/mbed,NordicSemiconductor\/mbed,masaohamanaka\/mbed,jpbrucker\/mbed,fvincenzo\/mbed-os,mikaleppanen\/mbed-os,naves-thiago\/mbed-midi,YarivCol\/mbed-os,nRFMesh\/mbed-os,nvlsianpu\/mbed,j-greffe\/mbed-os,JasonHow44\/mbed,NXPmicro\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,kpurusho\/mbed,DanKupiniak\/mbed,Willem23\/mbed,masaohamanaka\/mbed,logost\/mbed,Shengliang\/mbed,HeadsUpDisplayInc\/mbed,Tiryoh\/mbed,maximmbed\/mbed,fpiot\/mbed-ats,jrjang\/mbed,GustavWi\/mbed,rgrover\/mbed,hwfwgrp\/mbed,rgrover\/mbed,ban4jp\/mbed,logost\/mbed,NXPmicro\/mbed,maximmbed\/mbed,tung7970\/mbed-os-1,svastm\/mbed,NordicSemiconductor\/mbed,FranklyDev\/mbed,ryankurte\/mbed-os,autopulated\/mbed,svogl\/mbed-os,kl-cruz\/mbed-os,kl-cruz\/mbed-os,jamesadevine\/mbed,geky\/mbed,EmuxEvans\/mbed,mmorenobarm\/mbed-os,mazimkhan\/mbed-os,andreaslarssonublox\/mbed,alertby\/mbed,cvtsi2sd\/mbed-os,hwfwgrp\/mbed,NordicSemiconductor\/mbed,autopulated\/mbed,pedromes\/mbed,jamesadevine\/mbed,bikeNomad\/mbed,Willem23\/mbed,devanlai\/mbed,FranklyDev\/mbed,NitinBhaskar\/mbed,nabilbendafi\/mbed,ryankurte\/mbed-os,bikeNomad\/mbed,nvlsianpu\/mbed,bulislaw\/mbed-os,xcrespo\/mbed,logost\/mbed,brstew\/MBED-BUILD,ARM-software\/mbed-beetle,al177\/mbed,mnlipp\/mbed,JasonHow44\/mbed,Sweet-Peas\/mbed,svogl\/mbed-os,ryankurte\/mbed-os,wodji\/mbed,autopulated\/mbed,dbestm\/mbed,pi19404\/mbed,dbestm\/mbed,YarivCol\/mbed-os,screamerbg\/mbed,jamesadevine\/mbed,j-greffe\/mbed-os,tung7970\/mbed-os,bcostm\/mbed-os,EmuxEvans\/mbed,getopenmono\/mbed,YarivCol\/mbed-os,andreaslarssonublox\/mbed,nRFMesh\/mbed-os,bulislaw\/mbed-os,karsev\/mbed-os,dbestm\/mbed,mazimkhan\/mbed-os,geky\/mbed,HeadsUpDisplayInc\/mbed,pradeep-gr\/mbed-os5-onsemi,netzimme\/mbed-os,CalSol\/mbed,Timmmm\/mbed,ARM-software\/mbed-beetle,bulislaw\/mbed-os,nabilbendafi\/mbed,YarivCol\/mbed-os,fvincenzo\/mbed-os,alertby\/mbed,cvtsi2sd\/mbed-os,fahhem\/mbed-os,ban4jp\/mbed,dbestm\/mbed,svogl\/mbed-os,theotherjimmy\/mbed,jferreir\/mbed,kpurusho\/mbed,devanlai\/mbed,wodji\/mbed,theotherjimmy\/mbed,Shengliang\/mbed,struempelix\/mbed,nabilbendafi\/mbed,al177\/mbed,andreaslarssonublox\/mbed,c1728p9\/mbed-os,getopenmono\/mbed,tung7970\/mbed-os,arostm\/mbed-os,HeadsUpDisplayInc\/mbed,arostm\/mbed-os,jamesadevine\/mbed,NXPmicro\/mbed,karsev\/mbed-os,al177\/mbed,bcostm\/mbed-os,adamgreen\/mbed,bentwire\/mbed,monkiineko\/mbed-os,jferreir\/mbed,j-greffe\/mbed-os,naves-thiago\/mbed-midi,larks\/mbed,struempelix\/mbed,jpbrucker\/mbed,Timmmm\/mbed,jrjang\/mbed,c1728p9\/mbed-os,rosterloh\/mbed,fanghuaqi\/mbed,fvincenzo\/mbed-os,sam-geek\/mbed,tung7970\/mbed-os-1,HeadsUpDisplayInc\/mbed,mikaleppanen\/mbed-os,0xc0170\/mbed-drivers,kpurusho\/mbed,mbedmicro\/mbed,svastm\/mbed,Archcady\/mbed-os,screamerbg\/mbed,RonEld\/mbed,ban4jp\/mbed,hwfwgrp\/mbed,YarivCol\/mbed-os,pbrook\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,mbedmicro\/mbed,betzw\/mbed-os,fvincenzo\/mbed-os,ban4jp\/mbed,arostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,kpurusho\/mbed,mikaleppanen\/mbed-os,wodji\/mbed,hwfwgrp\/mbed,c1728p9\/mbed-os,GustavWi\/mbed,netzimme\/mbed-os,EmuxEvans\/mbed,JasonHow44\/mbed,bentwire\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,j-greffe\/mbed-os,bikeNomad\/mbed,monkiineko\/mbed-os,Timmmm\/mbed,jrjang\/mbed,jrjang\/mbed,bentwire\/mbed,andcor02\/mbed-os,jeremybrodt\/mbed,kl-cruz\/mbed-os,DanKupiniak\/mbed,pbrook\/mbed,svogl\/mbed-os,sg-\/mbed-drivers,bentwire\/mbed,Willem23\/mbed,bcostm\/mbed-os,sg-\/mbed-drivers,devanlai\/mbed,ARM-software\/mbed-beetle,Tiryoh\/mbed,jpbrucker\/mbed,Marcomissyou\/mbed,infinnovation\/mbed-os,fanghuaqi\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,adustm\/mbed,wodji\/mbed,struempelix\/mbed,FranklyDev\/mbed,sam-geek\/mbed,netzimme\/mbed-os,sam-geek\/mbed,devanlai\/mbed,0xc0170\/mbed-drivers,masaohamanaka\/mbed,fpiot\/mbed-ats,alertby\/mbed,iriark01\/mbed-drivers,logost\/mbed,monkiineko\/mbed-os,maximmbed\/mbed,fvincenzo\/mbed-os,screamerbg\/mbed,mazimkhan\/mbed-os,fpiot\/mbed-ats,betzw\/mbed-os,logost\/mbed,hwfwgrp\/mbed,arostm\/mbed-os,JasonHow44\/mbed,pbrook\/mbed,GustavWi\/mbed,theotherjimmy\/mbed,getopenmono\/mbed,JasonHow44\/mbed,Shengliang\/mbed,bcostm\/mbed-os,K4zuki\/mbed,bremoran\/mbed-drivers,Tiryoh\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,screamerbg\/mbed,tung7970\/mbed-os,fahhem\/mbed-os,DanKupiniak\/mbed,K4zuki\/mbed,alertby\/mbed,Marcomissyou\/mbed,naves-thiago\/mbed-midi,NXPmicro\/mbed,NordicSemiconductor\/mbed,pradeep-gr\/mbed-os5-onsemi,theotherjimmy\/mbed,svastm\/mbed,rosterloh\/mbed,NXPmicro\/mbed,ban4jp\/mbed,brstew\/MBED-BUILD,adamgreen\/mbed,bulislaw\/mbed-os,devanlai\/mbed,netzimme\/mbed-os,jpbrucker\/mbed,bulislaw\/mbed-os,c1728p9\/mbed-os,jpbrucker\/mbed,Timmmm\/mbed,xcrespo\/mbed,alertby\/mbed,nvlsianpu\/mbed,fanghuaqi\/mbed,jrjang\/mbed,sam-geek\/mbed,struempelix\/mbed,RonEld\/mbed,autopulated\/mbed,catiedev\/mbed-os,Willem23\/mbed,naves-thiago\/mbed-midi,getopenmono\/mbed,rosterloh\/mbed,FranklyDev\/mbed,jeremybrodt\/mbed,rgrover\/mbed,nRFMesh\/mbed-os,Sweet-Peas\/mbed,karsev\/mbed-os,geky\/mbed,Tiryoh\/mbed,mazimkhan\/mbed-os,Archcady\/mbed-os,infinnovation\/mbed-os,theotherjimmy\/mbed,RonEld\/mbed,nabilbendafi\/mbed,maximmbed\/mbed,mikaleppanen\/mbed-os,adustm\/mbed,adamgreen\/mbed,bulislaw\/mbed-os,al177\/mbed,GustavWi\/mbed,infinnovation\/mbed-os,sam-geek\/mbed,Archcady\/mbed-os,nRFMesh\/mbed-os,pradeep-gr\/mbed-os5-onsemi,jamesadevine\/mbed,K4zuki\/mbed,jeremybrodt\/mbed,logost\/mbed,jferreir\/mbed,Sweet-Peas\/mbed,nvlsianpu\/mbed,fahhem\/mbed-os,Archcady\/mbed-os,brstew\/MBED-BUILD,theotherjimmy\/mbed,maximmbed\/mbed,naves-thiago\/mbed-midi,xcrespo\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC11XX\/TOOLCHAIN_GCC_ARM\/LPC1114.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC11XX\/TOOLCHAIN_GCC_ARM\/LPC1114.ld","new_contents":"\/* Linker script for mbed LPC1114 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K\n  RAM (rwx) :  ORIGIN = 0x100000C0, LENGTH = 0x0F40\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n\t\t*(.text.Reset_Handler)\n        *(.text.SystemInit)\n\t\t. = 0x200;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for mbed LPC1114 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K\n  RAM (rwx) :  ORIGIN = 0x100000C0, LENGTH = 0x0F40\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n\t\t. = 0x200;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4e4853dcb26aa46db3269db45a8cbbbad61c44d8","subject":"common.template.ld: remove unneeded line","message":"common.template.ld: remove unneeded line\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/atmel-samd\/boards\/common.template.ld","new_file":"ports\/atmel-samd\/boards\/common.template.ld","new_contents":"\/* Template for SAMD21\/SAMD51 linking. dollar-sign-curly-bracket items are replaced with strings. *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_BOOTLOADER (rx): ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_FILESYSTEM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_CONFIG (r) : ORIGIN = ${CIRCUITPY_INTERNAL_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_CONFIG_SIZE}\n    FLASH_NVM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n\n    RAM (xrw)  : ORIGIN = 0x20000000, LENGTH = ${RAM_SIZE}\n}\n\n\/* top end of the stack *\/\n\/* stack must be double-word (8 byte) aligned *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - 8;\n_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n    } >FLASH_FIRMWARE\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = .;       \/* start of .data section *\/\n    } >FLASH_FIRMWARE\n\n    \/* Data accessed by the CAN peripheral must be in the first 64kB RAM *\/\n    \/* place it at the very start of RAM, before the .data section *\/\n    \/* it is zeroed by reset_port *\/\n    .canram (NOLOAD) :\n    {\n        . = ALIGN(4);\n        *(.canram)\n    } > RAM\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH_FIRMWARE to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _srelocate = .;        \/* create a global symbol at data start; used by startup code in order to initialize the .data section in RAM *\/\n        *(.ramfunc)\n        *(.ramfunc*)\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _erelocate = .;        \/* define a global symbol at data end; used by startup code in order to initialize the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        _szero = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ezero = .;         \/* define a global symbol at bss end; used by startup code *\/\n        _ebss = .;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the requested stack. *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/* Template for SAMD21\/SAMD51 linking. dollar-sign-curly-bracket items are replaced with strings. *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_BOOTLOADER (rx): ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_FILESYSTEM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_CONFIG (r) : ORIGIN = ${CIRCUITPY_INTERNAL_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_CONFIG_SIZE}\n    FLASH_NVM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n\n    RAM (xrw)  : ORIGIN = 0x20000000, LENGTH = ${RAM_SIZE}\n}\n\n\/* top end of the stack *\/\n\/* stack must be double-word (8 byte) aligned *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - 8;\n_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n    } >FLASH_FIRMWARE\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = .;       \/* start of .data section *\/\n    } >FLASH_FIRMWARE\n\n    \/* Data accessed by the CAN peripheral must be in the first 64kB RAM *\/\n    \/* place it at the very start of RAM, before the .data section *\/\n    \/* it is zeroed by reset_port *\/\n    .canram (NOLOAD) :\n    {\n        . = ALIGN(4);\n        *(.canram)\n    } > RAM\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH_FIRMWARE to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _srelocate = .;        \/* create a global symbol at data start; used by startup code in order to initialize the .data section in RAM *\/\n        . = ALIGN(4);\n        *(.ramfunc)\n        *(.ramfunc*)\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _erelocate = .;        \/* define a global symbol at data end; used by startup code in order to initialize the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        _szero = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ezero = .;         \/* define a global symbol at bss end; used by startup code *\/\n        _ebss = .;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the requested stack. *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"33930352f3c67dbcc6bac9586a80be000fb8ed7d","subject":"x86: intel64: enable MMU region list","message":"x86: intel64: enable MMU region list\n\nSame snippet as in our 32-bit linker file. Creates\nan iterable section with all the MMU_BOOT_REGION() info.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/x86\/intel64\/linker.ld","new_file":"include\/arch\/x86\/intel64\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corp.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION RAM\n#define RAMABLE_REGION RAM\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\t\/*\n\t * The \"locore\" must be in the 64K of RAM, so that 16-bit code (with\n\t * segment registers == 0x0000) and 32\/64-bit code agree on addresses.\n\t * ... there is no 16-bit code yet, but there will be when we add SMP.\n\t *\/\n\n\t.locore 0x8000 : ALIGN(16)\n\t{\n\t_locore_start = .;\n\t*(.locore)\n\t*(.locore.*)\n\tMMU_PAGE_ALIGN\n\t_lorodata_start = .;\n\t*(.lorodata)\n\tMMU_PAGE_ALIGN\n\t_lodata_start = .;\n\t*(.tss)\n\t*(.lodata)\n\tMMU_PAGE_ALIGN\n\t_lodata_end = .;\n\t}\n\n\t_locore_size = _lorodata_start - _locore_start;\n\t_lorodata_size = _lodata_start - _lorodata_start;\n\t_lodata_size = _lodata_end - _lodata_start;\n\n\t\/*\n\t * The rest of the system is loaded in \"normal\" memory (typically\n\t * placed above 1MB to avoid the by memory hole at 0x90000-0xFFFFF).\n\t *\/\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_rom_start = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(.text.*)\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n\t#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t*(.rodata)\n\t*(.rodata.*)\n\n\t#include <snippets-rodata.ld>\n\n\t#ifdef CONFIG_CUSTOM_RODATA_LD\n\t#include <custom-rodata.ld>\n\t#endif \/* CONFIG_CUSTOM_RODATA_LD *\/\n\n#ifdef CONFIG_X86_MMU\n\t. = ALIGN(8);\n\t_mmu_region_list_start = .;\n\tKEEP(*(\"._mmu_region.static.*\"))\n\t_mmu_region_list_end = .;\n#endif \/* CONFIG_X86_MMU *\/\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\t_image_rom_end = .;\n\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,ALIGN(16))\n\t{\n\tMMU_PAGE_ALIGN\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t*(.data)\n\t*(.data.*)\n\t#include <snippets-rwdata.ld>\n\t#ifdef CONFIG_CUSTOM_RWDATA_LD\n\t#include <custom-rwdata.ld>\n\t#endif \/* CONFIG_CUSTOM_RWDATA_LD *\/\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <snippets-ram-sections.ld>\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t__bss_start = .;\n\t*(.bss)\n\t*(.bss.*)\n\t*(COMMON)\n\t. = ALIGN(4);\t\/* so __bss_num_dwords is exact *\/\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_dwords = (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t*(.noinit)\n\t*(.noinit.*)\n\t#include <snippets-noinit.ld>\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <snippets-sections.ld>\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n#include <custom-sections.ld>\n#endif \/* CONFIG_CUSTOM_SECTIONS_LD *\/\n\n\t. = ALIGN(8);\n\t_image_ram_end = .;\n\t_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ :\n\t{\n\t*(.got)\n\t*(.got.plt)\n\t*(.igot)\n\t*(.igot.plt)\n\t*(.iplt)\n\t*(.plt)\n\t*(.note.GNU-stack)\n\t*(.rel.*)\n\t*(.rela.*)\n\t}\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corp.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION RAM\n#define RAMABLE_REGION RAM\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\t\/*\n\t * The \"locore\" must be in the 64K of RAM, so that 16-bit code (with\n\t * segment registers == 0x0000) and 32\/64-bit code agree on addresses.\n\t * ... there is no 16-bit code yet, but there will be when we add SMP.\n\t *\/\n\n\t.locore 0x8000 : ALIGN(16)\n\t{\n\t_locore_start = .;\n\t*(.locore)\n\t*(.locore.*)\n\tMMU_PAGE_ALIGN\n\t_lorodata_start = .;\n\t*(.lorodata)\n\tMMU_PAGE_ALIGN\n\t_lodata_start = .;\n\t*(.tss)\n\t*(.lodata)\n\tMMU_PAGE_ALIGN\n\t_lodata_end = .;\n\t}\n\n\t_locore_size = _lorodata_start - _locore_start;\n\t_lorodata_size = _lodata_start - _lorodata_start;\n\t_lodata_size = _lodata_end - _lodata_start;\n\n\t\/*\n\t * The rest of the system is loaded in \"normal\" memory (typically\n\t * placed above 1MB to avoid the by memory hole at 0x90000-0xFFFFF).\n\t *\/\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_rom_start = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(.text.*)\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n\t#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t*(.rodata)\n\t*(.rodata.*)\n\n\t#include <snippets-rodata.ld>\n\n\t#ifdef CONFIG_CUSTOM_RODATA_LD\n\t#include <custom-rodata.ld>\n\t#endif \/* CONFIG_CUSTOM_RODATA_LD *\/\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\t_image_rom_end = .;\n\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,ALIGN(16))\n\t{\n\tMMU_PAGE_ALIGN\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t*(.data)\n\t*(.data.*)\n\t#include <snippets-rwdata.ld>\n\t#ifdef CONFIG_CUSTOM_RWDATA_LD\n\t#include <custom-rwdata.ld>\n\t#endif \/* CONFIG_CUSTOM_RWDATA_LD *\/\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <snippets-ram-sections.ld>\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t__bss_start = .;\n\t*(.bss)\n\t*(.bss.*)\n\t*(COMMON)\n\t. = ALIGN(4);\t\/* so __bss_num_dwords is exact *\/\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_dwords = (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t*(.noinit)\n\t*(.noinit.*)\n\t#include <snippets-noinit.ld>\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <snippets-sections.ld>\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n#include <custom-sections.ld>\n#endif \/* CONFIG_CUSTOM_SECTIONS_LD *\/\n\n\t. = ALIGN(8);\n\t_image_ram_end = .;\n\t_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ :\n\t{\n\t*(.got)\n\t*(.got.plt)\n\t*(.igot)\n\t*(.igot.plt)\n\t*(.iplt)\n\t*(.plt)\n\t*(.note.GNU-stack)\n\t*(.rel.*)\n\t*(.rela.*)\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a106c5114b3774283b45fc69f53af02c7253da7b","subject":"bsp: fomu: fix rom address for example programs","message":"bsp: fomu: fix rom address for example programs\n\nDuring development, the ROM address was at offset 0x2001a000\n(due to the fact that the test program was located immediately\nfollowing the bitstream).\n\nIn normal Fomus, the ROM address is at offset 0x20040000, in order\nto take into account additional bitstreams and bootloaders.\n\nCorrect the address to the offset in order to get examples working\nwith existing Fomus.\n\nSigned-off-by: Sean Cross <d7e19930cc1f42c2d0781f4d9e6f1fe5891bf9cf@xobs.io>\n","repos":"hathach\/tinyusb,hathach\/tinyusb,hathach\/tinyusb","old_file":"hw\/bsp\/fomu\/fomu.ld","new_file":"hw\/bsp\/fomu\/fomu.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littleriscv\")\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nMEMORY {\n\tcsr : ORIGIN = 0x60000000, LENGTH = 0x01000000\n\tvexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100\n\tram : ORIGIN = 0x10000000, LENGTH = 0x00020000\n\trom : ORIGIN = 0x20040000, LENGTH = 0x00200000 - 0x40000\n}\n\n\/* The stack size used by the application. NOTE: you need to adjust according to your application. *\/\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _ftext = .;\n\t\t*(.text.start)\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;            \/* End of text section *\/\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(.sbss .sbss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n        end = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littleriscv\")\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nMEMORY {\n\tcsr : ORIGIN = 0x60000000, LENGTH = 0x01000000\n\tvexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100\n\tram : ORIGIN = 0x10000000, LENGTH = 0x00020000\n\trom : ORIGIN = 0x2001a000, LENGTH = 0x00200000 - 0x1a000\n}\n\n\/* The stack size used by the application. NOTE: you need to adjust according to your application. *\/\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _ftext = .;\n\t\t*(.text.start)\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;            \/* End of text section *\/\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(.sbss .sbss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n        end = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"6b2b66739d9fcfe579e1991bcb24e38f16b4b6c7","subject":"Moved ImageInfo section to 256-byte offset into image to allow vector table to occupy the bottom of the address space. This makes Nordics assumptions about your programs structure true...","message":"Moved ImageInfo section to 256-byte offset into image to allow vector table to occupy the bottom of the address space. This makes Nordics assumptions about your programs structure true...\n","repos":"HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed","old_file":"targets\/TARGET_NORDIC\/TARGET_NRF5\/TARGET_MCU_NRF52832\/device\/TOOLCHAIN_GCC_ARM\/NRF52832.ld","new_file":"targets\/TARGET_NORDIC\/TARGET_NRF5\/TARGET_MCU_NRF52832\/device\/TOOLCHAIN_GCC_ARM\/NRF52832.ld","new_contents":"\/*\n * Copyright (c) 2015 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\n\n\/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\nHeads Up Modifications to allow configurable application locations\nAlso modified to allow UICR to be written to using the section attribute\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*\/\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x1C000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x64000\n#endif\n\n#if !defined(IMAGE_INFO_OFFSET)\n  #define IMAGE_INFO_OFFSET 0x300\n#endif\n\n\/*\n * UICR -> User Information Configuration Registers\n * UICR_AP -> UICR Access Port Protect (has a couple other functions)\n * Note: This is now taken care of by merging with a separate UICR hex file\n * This was done to avoid build errors with the mbed cli system\n * and to make the build more flexible (for OTA updates, etc)\n *\/\n\nMEMORY\n{\n   FLASH(rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n   RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0xd108\n  \/*IMAGEINFO(r): ORIGIN = MBED_APP_START, LENGTH = IMAGE_INFO_OFFSET\n  FLASH(rx) : ORIGIN = MBED_APP_START+IMAGE_INFO_OFFSET, LENGTH = MBED_APP_SIZE-IMAGE_INFO_OFFSET\n  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0xd108*\/\n  \/*UICR (rw) :  ORIGIN = 0x10001014, LENGTH = 0x8\n  UICR_AP (rw) : ORIGIN = 0x10001200, LENGTH = 0x10*\/\n}\n\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with the other linker script that defines memory regions FLASH and RAM.\n * It references the following symbols that must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines the following symbols that the code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\n\nSECTIONS\n{\n    \/*.vectors :\n    {\n\tKEEP(*(.Vectors))\n    } > VECTORS*\/\n\n    \/*.imageinfo :\n    {\n\tKEEP(*(.ImageInfo))\n    } > IMAGEINFO*\/\n    \n    .text :\n    {\n        KEEP(*(.Vectors))\n\tFILL(0xff)\n\t. = 0x100;\n\tKEEP(*(.ImageInfo))\n\t. = 0x400;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        PROVIDE(__start_fs_data = .);\n        KEEP(*(.fs_data))\n        PROVIDE(__stop_fs_data = .);\n        \n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    __edata = .;\n\n    .noinit :\n    {\n      PROVIDE(__start_noinit = .);\n      KEEP(*(.noinit))\n      PROVIDE(__stop_noinit = .);\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n\n        \/* Expand the heap to reach the stack boundary. *\/\n        ASSERT(. <= (ORIGIN(RAM) + LENGTH(RAM) - 0x800), \"heap region overflowed into stack\");\n        . += (ORIGIN(RAM) + LENGTH(RAM) - 0x800) - .;\n    } > RAM\n    PROVIDE(__heap_start = ADDR(.heap));\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n\n    \/* .stack_dummy section does not contain any symbols. It is only\n     * used for the linker script to calculate the size of stack sections\n     * and assign values to stack symbols later. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*)\n        . += (ORIGIN(RAM) + LENGTH(RAM) - .);\n    } > RAM\n\n    \/* Set the stack top to the end of RAM and move down the stack limit by\n     * the size of the stack_dummy section. *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Heads Up Modification\n       Creates a memory section for the UICR registers\n       This allows them to be programmed with a\n       .hex file at the factory\n    *\/\n    \/*.uicr :\n    {\n\tKEEP(*(.uicr))\n    } > UICR\n\n    .uicr_ap :\n    {\n\tKEEP(*(.uicr_ap))\n    } > UICR_AP*\/\n\n\n}\n","old_contents":"\/*\n * Copyright (c) 2015 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\n\n\/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\nHeads Up Modifications to allow configurable application locations\nAlso modified to allow UICR to be written to using the section attribute\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*\/\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x1C000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x64000\n#endif\n\n#if !defined(IMAGE_INFO_OFFSET)\n  #define IMAGE_INFO_OFFSET 0x300\n#endif\n\n\/*\n * UICR -> User Information Configuration Registers\n * UICR_AP -> UICR Access Port Protect (has a couple other functions)\n * Note: This is now taken care of by merging with a separate UICR hex file\n * This was done to avoid build errors with the mbed cli system\n * and to make the build more flexible (for OTA updates, etc)\n *\/\n\nMEMORY\n{\n  IMAGEINFO(r): ORIGIN = MBED_APP_START, LENGTH = IMAGE_INFO_OFFSET\n  FLASH(rx) : ORIGIN = MBED_APP_START+IMAGE_INFO_OFFSET, LENGTH = MBED_APP_SIZE-IMAGE_INFO_OFFSET\n  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0xd108\n  \/*UICR (rw) :  ORIGIN = 0x10001014, LENGTH = 0x8\n  UICR_AP (rw) : ORIGIN = 0x10001200, LENGTH = 0x10*\/\n}\n\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with the other linker script that defines memory regions FLASH and RAM.\n * It references the following symbols that must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines the following symbols that the code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\n\nSECTIONS\n{\n    \/*.vectors :\n    {\n\tKEEP(*(.Vectors))\n    } > VECTORS*\/\n\n    .imageinfo :\n    {\n\tKEEP(*(.ImageInfo))\n    } > IMAGEINFO\n    \n    .text :\n    {\n        KEEP(*(.Vectors))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        PROVIDE(__start_fs_data = .);\n        KEEP(*(.fs_data))\n        PROVIDE(__stop_fs_data = .);\n        \n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    __edata = .;\n\n    .noinit :\n    {\n      PROVIDE(__start_noinit = .);\n      KEEP(*(.noinit))\n      PROVIDE(__stop_noinit = .);\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n\n        \/* Expand the heap to reach the stack boundary. *\/\n        ASSERT(. <= (ORIGIN(RAM) + LENGTH(RAM) - 0x800), \"heap region overflowed into stack\");\n        . += (ORIGIN(RAM) + LENGTH(RAM) - 0x800) - .;\n    } > RAM\n    PROVIDE(__heap_start = ADDR(.heap));\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n\n    \/* .stack_dummy section does not contain any symbols. It is only\n     * used for the linker script to calculate the size of stack sections\n     * and assign values to stack symbols later. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*)\n        . += (ORIGIN(RAM) + LENGTH(RAM) - .);\n    } > RAM\n\n    \/* Set the stack top to the end of RAM and move down the stack limit by\n     * the size of the stack_dummy section. *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Heads Up Modification\n       Creates a memory section for the UICR registers\n       This allows them to be programmed with a\n       .hex file at the factory\n    *\/\n    \/*.uicr :\n    {\n\tKEEP(*(.uicr))\n    } > UICR\n\n    .uicr_ap :\n    {\n\tKEEP(*(.uicr_ap))\n    } > UICR_AP*\/\n\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7320609c9a2baf795b818bde50e1e77a74124ceb","subject":"Update sdram.ld","message":"Update sdram.ld","repos":"weety\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,igou\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,zhaojuntao\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,AubrCool\/rt-thread,igou\/rt-thread,yongli3\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,weety\/rt-thread,yongli3\/rt-thread,ArdaFu\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,yongli3\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,armink\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,AubrCool\/rt-thread,wolfgangz2013\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,igou\/rt-thread,geniusgogo\/rt-thread,weiyuliang\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,igou\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,FlyLu\/rt-thread,yongli3\/rt-thread,wolfgangz2013\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread","old_file":"bsp\/asm9260t\/link_scripts\/sdram.ld","new_file":"bsp\/asm9260t\/link_scripts\/sdram.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(entry)\nSECTIONS\n{\n    . = 0x20000000;\n\n    . = ALIGN(4);\n    .text : \n    {\n        *(.init)\n        *(.text)\n        *(.gnu.linkonce.t*)\n        \n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);   \n\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n    }\n\n    . = ALIGN(4);\n    .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    }\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    }\n\n    . = ALIGN(4);\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n    }\n\n    . = ALIGN(4);\n    .nobss : { *(.nobss) }\n    \n    . = ALIGN(4);\n    __bss_start__ = .;\n    .bss : { *(.bss)}\n    __bss_end__ = .;\n\n    \/* stabs debugging sections. *\/\n    .stab 0 : { *(.stab) }\n    .stabstr 0 : { *(.stabstr) }\n    .stab.excl 0 : { *(.stab.excl) }\n    .stab.exclstr 0 : { *(.stab.exclstr) }\n    .stab.index 0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment 0 : { *(.comment) }\n    .debug_abbrev 0 : { *(.debug_abbrev) }\n    .debug_info 0 : { *(.debug_info) }\n    .debug_line 0 : { *(.debug_line) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    .debug_aranges 0 : { *(.debug_aranges) }\n\n    _end = .;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(start)\nSECTIONS\n{\n    . = 0x20000000;\n\n    . = ALIGN(4);\n    .text : \n    {\n        *(.init)\n        *(.text)\n        *(.gnu.linkonce.t*)\n        \n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);   \n\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n    }\n\n    . = ALIGN(4);\n    .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    }\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    }\n\n    . = ALIGN(4);\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n    }\n\n    . = ALIGN(4);\n    .nobss : { *(.nobss) }\n    \n    . = ALIGN(4);\n    __bss_start__ = .;\n    .bss : { *(.bss)}\n    __bss_end__ = .;\n\n    \/* stabs debugging sections. *\/\n    .stab 0 : { *(.stab) }\n    .stabstr 0 : { *(.stabstr) }\n    .stab.excl 0 : { *(.stab.excl) }\n    .stab.exclstr 0 : { *(.stab.exclstr) }\n    .stab.index 0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment 0 : { *(.comment) }\n    .debug_abbrev 0 : { *(.debug_abbrev) }\n    .debug_info 0 : { *(.debug_info) }\n    .debug_line 0 : { *(.debug_line) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    .debug_aranges 0 : { *(.debug_aranges) }\n\n    _end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7b42324e77925d6b91be5826168d9ce3ff68c5e8","subject":"arc: CONFIG_XIP can work with ICCM","message":"arc: CONFIG_XIP can work with ICCM\n\nI've tested that CONFIG_XIP does work with Harvard.\nUser's can build CONFIG_XIP=y, and then have their bootable image\nbe placed in SPI-FLASH. A bootloader will load up ICCM contents.\nZephyr will then copy remaining data from ICCM to DCCM.\nThis takes a bit of ICCM memory to do it, but it will work.\n\nChange-Id: Ic1cd201d19aab9083d63334527d9d68f4edc6075\nSigned-off-by: Chuck Jordan <c464ed312fa6f818297227c7e5018fc9f4bd95ad@synopsys.com>\n","repos":"punitvara\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,aceofall\/zephyr-iotos,mirzak\/zephyr-os,Vudentz\/zephyr,erwango\/zephyr,rsalveti\/zephyr,runchip\/zephyr-cc3200,fbsder\/zephyr,fractalclone\/zephyr-riscv,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,bigdinotech\/zephyr,sharronliu\/zephyr,explora26\/zephyr,aceofall\/zephyr-iotos,mirzak\/zephyr-os,nashif\/zephyr,nashif\/zephyr,runchip\/zephyr-cc3220,tidyjiang8\/zephyr-doc,finikorg\/zephyr,erwango\/zephyr,holtmann\/zephyr,erwango\/zephyr,zephyrproject-rtos\/zephyr,runchip\/zephyr-cc3220,finikorg\/zephyr,mirzak\/zephyr-os,mbolivar\/zephyr,bboozzoo\/zephyr,mbolivar\/zephyr,mbolivar\/zephyr,mirzak\/zephyr-os,rsalveti\/zephyr,bigdinotech\/zephyr,holtmann\/zephyr,Vudentz\/zephyr,sharronliu\/zephyr,runchip\/zephyr-cc3220,pklazy\/zephyr,aceofall\/zephyr-iotos,fractalclone\/zephyr-riscv,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,bboozzoo\/zephyr,nashif\/zephyr,kraj\/zephyr,punitvara\/zephyr,fbsder\/zephyr,aceofall\/zephyr-iotos,galak\/zephyr,runchip\/zephyr-cc3200,runchip\/zephyr-cc3220,GiulianoFranchetto\/zephyr,kraj\/zephyr,ldts\/zephyr,galak\/zephyr,kraj\/zephyr,pklazy\/zephyr,explora26\/zephyr,ldts\/zephyr,explora26\/zephyr,rsalveti\/zephyr,holtmann\/zephyr,holtmann\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,sharronliu\/zephyr,punitvara\/zephyr,bigdinotech\/zephyr,zephyriot\/zephyr,explora26\/zephyr,pklazy\/zephyr,erwango\/zephyr,runchip\/zephyr-cc3200,bigdinotech\/zephyr,zephyriot\/zephyr,fractalclone\/zephyr-riscv,galak\/zephyr,sharronliu\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,runchip\/zephyr-cc3200,pklazy\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,fractalclone\/zephyr-riscv,mirzak\/zephyr-os,fbsder\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,holtmann\/zephyr,tidyjiang8\/zephyr-doc,tidyjiang8\/zephyr-doc,aceofall\/zephyr-iotos,runchip\/zephyr-cc3220,bboozzoo\/zephyr,erwango\/zephyr,bboozzoo\/zephyr,kraj\/zephyr,explora26\/zephyr,rsalveti\/zephyr,runchip\/zephyr-cc3200,GiulianoFranchetto\/zephyr,sharronliu\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,zephyriot\/zephyr,mbolivar\/zephyr,pklazy\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,rsalveti\/zephyr,mbolivar\/zephyr,fbsder\/zephyr,bigdinotech\/zephyr,ldts\/zephyr,tidyjiang8\/zephyr-doc,tidyjiang8\/zephyr-doc,bboozzoo\/zephyr,Vudentz\/zephyr,fractalclone\/zephyr-riscv,fbsder\/zephyr,galak\/zephyr","old_file":"include\/arch\/arc\/v2\/linker_harvard.ld","new_file":"include\/arch\/arc\/v2\/linker_harvard.ld","new_contents":"\/*\n * Copyright (c) 2016 Synopsys, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARC EM Starter Kit targets.\n *\n * Linker script for the ARC EM Starter Kit board.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#if defined(CONFIG_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(__start)\n\nMEMORY {\n\tICCM  (rx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n}\n\nSECTIONS {\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\n\n\t\tKEEP(*(.irq_vector_table))\n\t\tKEEP(*(\".irq_vector_table.*\"))\n\n#ifdef CONFIG_VERSION_HEADER\n\t\t*(.version_header)\n\t\tKEEP(*(\".version_header*\"))\n#endif\n#ifndef CONFIG_SW_ISR_TABLE_DYNAMIC\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*The following sections maps the location of the different rows for\n\t\tthe _sw_isr_table. Each row maps to an IRQ entry (handler, argument).*\/\n\t\t\/*In ARC architecture, IRQ 0-15 are reserved for the system and are not\n\t\tassignable by the user, for that reason the linker sections start\n\t\ton IRQ 16*\/\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n#endif\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n\t\t_image_text_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE (devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(gpio_compat, (OPTIONAL),)\n\t{\n\t\t__gpio_compat_start = .;\n\t\t*(\".gpio_compat.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".gpio_compat*\")))\n\t\t__gpio_compat_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,) {\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below, hence\n\t\t * symbol __CTOR_LIST__ must be aligned on 4 byte boundary.\n\t\t * To align with the C++ standard, the first element of the array\n\t\t * contains the number of actual constructors. The last element is\n\t\t * NULL.\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\/* XIP imaged DATA ROM start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n\tSECTION_AT_PROLOGUE(_DATA_SECTION_NAME,,,_DATA_IN_ROM) {\n#else\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,) {\n#endif\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t\t_image_ram_start = .;\n\t\t__data_ram_start = .;\n\t\t*(.data)\n\t\t*(\".data.*\")\n\n#if CONFIG_SW_ISR_TABLE_DYNAMIC\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*The following sections maps the location of the different rows for\n\t\tthe _sw_isr_table. Each row maps to an IRQ entry (handler, argument).*\/\n\t\t\/*In ARC architecture, IRQ 0-15 are reserved for the system and are not\n\t\tassignable by the user, for that reason the linker sections start\n\t\ton IRQ 16*\/\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n#endif\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\nSECTION_PROLOGUE (_k_task_list, (OPTIONAL),)\n\t{\n\t\t_k_task_list_start = .;\n\t\t\t*(._k_task_list.public.*)\n\t\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE (_k_task_ptr, (OPTIONAL),)\n\t{\n\t\t_k_task_ptr_start = .;\n\t\t\t*(._k_task_ptr.public.*)\n\t\t\t*(._k_task_ptr.private.*)\n\t\t\t*(._k_task_ptr.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n\t\t_k_task_ptr_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE (_k_pipe_ptr, (OPTIONAL),)\n\t{\n\t\t_k_pipe_ptr_start = .;\n\t\t\t*(._k_pipe_ptr.public.*)\n\t\t\t*(._k_pipe_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n\t\t_k_pipe_ptr_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE (_k_mem_map_ptr, (OPTIONAL),)\n\t{\n\t\t_k_mem_map_ptr_start = .;\n\t\t\t*(._k_mem_map_ptr.public.*)\n\t\t\t*(._k_mem_map_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n\t\t_k_mem_map_ptr_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_k_event_list, (OPTIONAL),)\n\t{\n\t\t_k_event_list_start = .;\n\t\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(\".bss.*\")\n\t\tCOMMON_SYMBOLS\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t*(.noinit)\n\t\t*(\".noinit.*\")\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\t__bss_num_words = (__bss_end - __bss_start) >> 2;\n\n\tGROUP_END(RAMABLE_REGION)\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\tGROUP_START(DCCM)\n\tGROUP_END(DCCM)\n\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2016 Synopsys, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARC EM Starter Kit targets.\n *\n * Linker script for the ARC EM Starter Kit board.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#if defined(CONFIG_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n\t#error \"CONFIG_XIP is not supported at this time.\"\n#else\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#endif\n\n\/* TODO: For Harvard, probably want data in ICCM but have startup code\n * that copies it to DCCM.\n *\/\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(__start)\n\nMEMORY {\n\tICCM  (rx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n}\n\nSECTIONS {\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\n\n\t\tKEEP(*(.irq_vector_table))\n\t\tKEEP(*(\".irq_vector_table.*\"))\n\n#ifdef CONFIG_VERSION_HEADER\n\t\t*(.version_header)\n\t\tKEEP(*(\".version_header*\"))\n#endif\n#ifndef CONFIG_SW_ISR_TABLE_DYNAMIC\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*The following sections maps the location of the different rows for\n\t\tthe _sw_isr_table. Each row maps to an IRQ entry (handler, argument).*\/\n\t\t\/*In ARC architecture, IRQ 0-15 are reserved for the system and are not\n\t\tassignable by the user, for that reason the linker sections start\n\t\ton IRQ 16*\/\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n#endif\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n\t\t_image_text_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE (devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(gpio_compat, (OPTIONAL),)\n\t{\n\t\t__gpio_compat_start = .;\n\t\t*(\".gpio_compat.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".gpio_compat*\")))\n\t\t__gpio_compat_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,) {\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below, hence\n\t\t * symbol __CTOR_LIST__ must be aligned on 4 byte boundary.\n\t\t * To align with the C++ standard, the first element of the array\n\t\t * contains the number of actual constructors. The last element is\n\t\t * NULL.\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\/* XIP imaged DATA ROM start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n\tSECTION_AT_PROLOGUE(_DATA_SECTION_NAME,,,_DATA_IN_ROM) {\n#else\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,) {\n#endif\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t\t_image_ram_start = .;\n\t\t__data_ram_start = .;\n\t\t*(.data)\n\t\t*(\".data.*\")\n\n#if CONFIG_SW_ISR_TABLE_DYNAMIC\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*The following sections maps the location of the different rows for\n\t\tthe _sw_isr_table. Each row maps to an IRQ entry (handler, argument).*\/\n\t\t\/*In ARC architecture, IRQ 0-15 are reserved for the system and are not\n\t\tassignable by the user, for that reason the linker sections start\n\t\ton IRQ 16*\/\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n#endif\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\nSECTION_PROLOGUE (_k_task_list, (OPTIONAL),)\n\t{\n\t\t_k_task_list_start = .;\n\t\t\t*(._k_task_list.public.*)\n\t\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE (_k_task_ptr, (OPTIONAL),)\n\t{\n\t\t_k_task_ptr_start = .;\n\t\t\t*(._k_task_ptr.public.*)\n\t\t\t*(._k_task_ptr.private.*)\n\t\t\t*(._k_task_ptr.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n\t\t_k_task_ptr_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE (_k_pipe_ptr, (OPTIONAL),)\n\t{\n\t\t_k_pipe_ptr_start = .;\n\t\t\t*(._k_pipe_ptr.public.*)\n\t\t\t*(._k_pipe_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n\t\t_k_pipe_ptr_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE (_k_mem_map_ptr, (OPTIONAL),)\n\t{\n\t\t_k_mem_map_ptr_start = .;\n\t\t\t*(._k_mem_map_ptr.public.*)\n\t\t\t*(._k_mem_map_ptr.private.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n\t\t_k_mem_map_ptr_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_k_event_list, (OPTIONAL),)\n\t{\n\t\t_k_event_list_start = .;\n\t\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(\".bss.*\")\n\t\tCOMMON_SYMBOLS\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t*(.noinit)\n\t\t*(\".noinit.*\")\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\t__bss_num_words = (__bss_end - __bss_start) >> 2;\n\n\tGROUP_END(RAMABLE_REGION)\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\tGROUP_START(DCCM)\n\tGROUP_END(DCCM)\n\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cc43e0d57ec1c2acf0751c5d6dca7faa6211a3b9","subject":"changed section order \/ names","message":"changed section order \/ names\n","repos":"Stephane-D\/SGDK,Stephane-D\/SGDK,andwn\/SGDK,andwn\/SGDK,Stephane-D\/SGDK,andwn\/SGDK","old_file":"md.ld","new_file":"md.ld","new_contents":"OUTPUT_ARCH(m68k)\r\nSEARCH_DIR(.)\r\n\/*GROUP(-lbcc -lc -lgcc)*\/\r\n__DYNAMIC  =  0;\r\n\r\n\/*\r\n * Setup the memory map of the SEGA Genesis.\r\n * stack grows down from high memory.\r\n *\r\n * The memory map look like this:\r\n * +--------------------+ <- low memory\r\n * | .text              |\r\n * |        _etext      |\r\n * |        ctor list   | the ctor and dtor lists are for\r\n * |        dtor list   | C++ support\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * +--------------------+ <- 0x00FF0000\r\n * | .data              | initialized data goes here\r\n * |        _data       |\r\n * |        _edata      |\r\n * +--------------------+\r\n * | .bss               |\r\n * |        _bstart     | start of bss, cleared by crt0\r\n * |        _bend       | start of heap, used by sbrk()\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * |        __stack     | top of stack\r\n * +--------------------+ <- 0x01000000\r\n *\/\r\nMEMORY\r\n{\r\n\trom : ORIGIN = 0x00000000, LENGTH = 0x00A00000\r\n\tram : ORIGIN = 0x00FF0000, LENGTH = 0x00010000\r\n}\r\n\r\n\/*\r\n * allocate the stack to be at the top of memory, since the stack\r\n * grows down\r\n *\/\r\n\r\nPROVIDE (__stack = 0x01000000);\r\n\r\n\r\nSECTIONS\r\n{\r\n  .text 0x00000000:\r\n  {\r\n    KEEP(*(.text.keepboot)) *(.text.*) *(.text)\r\n    . = ALIGN(0x4);\r\n     __CTOR_LIST__ = .;\r\n    LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\r\n    *(.ctors)\r\n    LONG(0)\r\n    __CTOR_END__ = .;\r\n    __DTOR_LIST__ = .;\r\n    LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\r\n    *(.dtors)\r\n     LONG(0)\r\n    __DTOR_END__ = .;\r\n\r\n    *(.rodata .rodata.*)\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n\r\n    . = ALIGN(0x4);\r\n    __INIT_SECTION__ = . ;\r\n    *(.init)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    __FINI_SECTION__ = . ;\r\n    *(.fini)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    _etext = .;\r\n    *(.lit)\r\n\r\n    *(.rodata_bin)\r\n    *(.rodata_binf)\r\n  } > rom\r\n  _stext = SIZEOF (.text);\r\n\r\n  .data 0xFF0000 :\r\n  AT ( ADDR (.text) + SIZEOF (.text) )\r\n  {\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.*)\r\n    _edata = .;\r\n  } > ram\r\n  _sdata = SIZEOF (.data);\r\n\r\n  .bss 0xFF0000 + SIZEOF (.data) :\r\n  {\r\n    _start = . ;\r\n    *(.shbss)\r\n    *(.bss .bss.*)\r\n    *(COMMON)\r\n    _bend = . ;\r\n  } > ram\r\n\r\n  .stab 0 (NOLOAD) :\r\n  {\r\n    *(.stab)\r\n  }\r\n\r\n  .stabstr 0 (NOLOAD) :\r\n  {\r\n    *(.stabstr)\r\n  }\r\n\r\n  .eh_frame 0 (NOLOAD) :\r\n  {\r\n    *(.eh_frame)\r\n  }\r\n}\r\n","old_contents":"OUTPUT_ARCH(m68k)\r\nSEARCH_DIR(.)\r\n\/*GROUP(-lbcc -lc -lgcc)*\/\r\n__DYNAMIC  =  0;\r\n\r\n\/*\r\n * Setup the memory map of the SEGA Genesis.\r\n * stack grows down from high memory.\r\n *\r\n * The memory map look like this:\r\n * +--------------------+ <- low memory\r\n * | .text              |\r\n * |        _etext      |\r\n * |        ctor list   | the ctor and dtor lists are for\r\n * |        dtor list   | C++ support\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * +--------------------+ <- 0x00FF0000\r\n * | .data              | initialized data goes here\r\n * |        _data       |\r\n * |        _edata      |\r\n * +--------------------+\r\n * | .bss               |\r\n * |        _bstart     | start of bss, cleared by crt0\r\n * |        _bend       | start of heap, used by sbrk()\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * |        __stack     | top of stack\r\n * +--------------------+ <- 0x01000000\r\n *\/\r\nMEMORY\r\n{\r\n\trom : ORIGIN = 0x00000000, LENGTH = 0x00A00000\r\n\tram : ORIGIN = 0x00FF0000, LENGTH = 0x00010000\r\n}\r\n\r\n\/*\r\n * allocate the stack to be at the top of memory, since the stack\r\n * grows down\r\n *\/\r\n\r\nPROVIDE (__stack = 0x01000000);\r\n\r\n\r\nSECTIONS\r\n{\r\n  .text 0x00000000:\r\n  {\r\n    KEEP(*(.text.keepboot)) *(.text.*) *(.text)\r\n    . = ALIGN(0x4);\r\n     __CTOR_LIST__ = .;\r\n    LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\r\n    *(.ctors)\r\n    LONG(0)\r\n    __CTOR_END__ = .;\r\n    __DTOR_LIST__ = .;\r\n    LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\r\n    *(.dtors)\r\n     LONG(0)\r\n    __DTOR_END__ = .;\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n\r\n    . = ALIGN(0x4);\r\n    __INIT_SECTION__ = . ;\r\n    *(.init)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    __FINI_SECTION__ = . ;\r\n    *(.fini)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    _etext = .;\r\n    *(.lit)\r\n\r\n    *(.rodata .rodata.*)\r\n    *(.far_rodata .far_rodata.*)\r\n  } > rom\r\n  _stext = SIZEOF (.text);\r\n\r\n  .data 0xFF0000 :\r\n  AT ( ADDR (.text) + SIZEOF (.text) )\r\n  {\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.*)\r\n    _edata = .;\r\n  } > ram\r\n  _sdata = SIZEOF (.data);\r\n\r\n  .bss 0xFF0000 + SIZEOF (.data) :\r\n  {\r\n    _start = . ;\r\n    *(.shbss)\r\n    *(.bss .bss.*)\r\n    *(COMMON)\r\n    _bend = . ;\r\n  } > ram\r\n\r\n  .stab 0 (NOLOAD) :\r\n  {\r\n    *(.stab)\r\n  }\r\n\r\n  .stabstr 0 (NOLOAD) :\r\n  {\r\n    *(.stabstr)\r\n  }\r\n\r\n  .eh_frame 0 (NOLOAD) :\r\n  {\r\n    *(.eh_frame)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5e740c23106cc359d27a0879bcca86203ed25145","subject":"Revert initialization back to original state as in linker script from libgloss","message":"Revert initialization back to original state as in linker script from libgloss\n","repos":"msalau\/rl78-samples-R5F104FEAFP,msalau\/rl78-samples-R5F104FEAFP","old_file":"common\/R5F104xE.ld","new_file":"common\/R5F104xE.ld","new_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/G14 R5F104xE, 64k flash, 5.5k ram, 4k data flash *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007c\n\tOPT (r)   : ORIGIN = 0x000c0, LENGTH = 0x00004\n\tROM (r)   : ORIGIN = 0x000d8, LENGTH = 0x0ff28\n\tRAM (w)   : ORIGIN = 0xfe900, LENGTH = 0x015e0\n\tSTACK (w) : ORIGIN = 0xffee0, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n  .opt :\n  {\n    BYTE(0x6e)\n    BYTE(0xff)\n    BYTE(0xe9)\n    BYTE(0x04)\n  } > OPT\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  .rodata (MAX(__romdatastart + __romdatacopysize, 0x2000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > ROM\n\n  .text :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/G14 R5F104xE, 64k flash, 5.5k ram, 4k data flash *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007c\n\tOPT (r)   : ORIGIN = 0x000c0, LENGTH = 0x00004\n\tROM (r)   : ORIGIN = 0x000d8, LENGTH = 0x0ff28\n\tRAM (w)   : ORIGIN = 0xfe900, LENGTH = 0x015e0\n\tSTACK (w) : ORIGIN = 0xffee0, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n  .opt :\n  {\n    BYTE(0x6e)\n    BYTE(0xff)\n    BYTE(0xe9)\n    BYTE(0x04)\n  } > OPT\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  .rodata (MAX(__romdatastart + __romdatacopysize, 0x2000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > ROM\n\n  .text :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(EXCLUDE_FILE (*crtbegin*.o *crtend*.o) .init))\n    KEEP (*(.fini))\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"6af2778136d5b70555c75bab344a8960ba7fc989","subject":"Xtensa port: Fixed linker script for hifi_mini core.","message":"Xtensa port: Fixed linker script for hifi_mini core.\n\nChange-Id: I21f4ff0c136c1e72e6d36d179898bbde1b08b71f\nSigned-off-by: Mazen NEIFER <7004bbdb2ec6a96ce3829b3f6e754b7f9ff69de2@nestwave.com>\n","repos":"galak\/zephyr,GiulianoFranchetto\/zephyr,runchip\/zephyr-cc3200,aceofall\/zephyr-iotos,bigdinotech\/zephyr,runchip\/zephyr-cc3220,aceofall\/zephyr-iotos,aceofall\/zephyr-iotos,fbsder\/zephyr,holtmann\/zephyr,zephyriot\/zephyr,bigdinotech\/zephyr,fractalclone\/zephyr-riscv,erwango\/zephyr,pklazy\/zephyr,mbolivar\/zephyr,kraj\/zephyr,fractalclone\/zephyr-riscv,mbolivar\/zephyr,zephyriot\/zephyr,ldts\/zephyr,pklazy\/zephyr,Vudentz\/zephyr,bboozzoo\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,holtmann\/zephyr,ldts\/zephyr,runchip\/zephyr-cc3220,erwango\/zephyr,fbsder\/zephyr,bboozzoo\/zephyr,mbolivar\/zephyr,erwango\/zephyr,runchip\/zephyr-cc3200,sharronliu\/zephyr,tidyjiang8\/zephyr-doc,explora26\/zephyr,rsalveti\/zephyr,tidyjiang8\/zephyr-doc,punitvara\/zephyr,runchip\/zephyr-cc3220,fractalclone\/zephyr-riscv,nashif\/zephyr,Vudentz\/zephyr,ldts\/zephyr,finikorg\/zephyr,punitvara\/zephyr,fbsder\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,rsalveti\/zephyr,fractalclone\/zephyr-riscv,explora26\/zephyr,punitvara\/zephyr,kraj\/zephyr,sharronliu\/zephyr,finikorg\/zephyr,erwango\/zephyr,bigdinotech\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,bboozzoo\/zephyr,aceofall\/zephyr-iotos,zephyriot\/zephyr,mbolivar\/zephyr,fbsder\/zephyr,zephyrproject-rtos\/zephyr,sharronliu\/zephyr,bigdinotech\/zephyr,galak\/zephyr,bboozzoo\/zephyr,tidyjiang8\/zephyr-doc,explora26\/zephyr,ldts\/zephyr,bboozzoo\/zephyr,galak\/zephyr,runchip\/zephyr-cc3200,runchip\/zephyr-cc3200,nashif\/zephyr,zephyrproject-rtos\/zephyr,rsalveti\/zephyr,runchip\/zephyr-cc3200,rsalveti\/zephyr,sharronliu\/zephyr,ldts\/zephyr,sharronliu\/zephyr,Vudentz\/zephyr,explora26\/zephyr,holtmann\/zephyr,holtmann\/zephyr,punitvara\/zephyr,pklazy\/zephyr,nashif\/zephyr,mbolivar\/zephyr,fbsder\/zephyr,nashif\/zephyr,kraj\/zephyr,bigdinotech\/zephyr,nashif\/zephyr,holtmann\/zephyr,pklazy\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,pklazy\/zephyr,fractalclone\/zephyr-riscv,galak\/zephyr,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,kraj\/zephyr,tidyjiang8\/zephyr-doc,runchip\/zephyr-cc3220,tidyjiang8\/zephyr-doc,aceofall\/zephyr-iotos,Vudentz\/zephyr,explora26\/zephyr,galak\/zephyr,rsalveti\/zephyr,erwango\/zephyr,Vudentz\/zephyr,kraj\/zephyr,runchip\/zephyr-cc3220","old_file":"arch\/xtensa\/soc\/hifi_mini\/linker.ld","new_file":"arch\/xtensa\/soc\/hifi_mini\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\nMEMORY\n{\n  dram0_0_seg :                       \torg = 0x60000000, len = 0x20000\n  iram0_0_seg :                       \torg = 0x60020000, len = 0x2E0\n  iram0_1_seg :                       \torg = 0x600202E0, len = 0x4\n  iram0_2_seg :                       \torg = 0x600202E4, len = 0x1C\n  iram0_3_seg :                       \torg = 0x60020300, len = 0x4\n  iram0_4_seg :                       \torg = 0x60020304, len = 0x1C\n  iram0_5_seg :                       \torg = 0x60020320, len = 0x4\n  iram0_6_seg :                       \torg = 0x60020324, len = 0x1C\n  iram0_7_seg :                       \torg = 0x60020340, len = 0x1FCC0\n}\n\nPHDRS\n{\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  iram0_1_phdr PT_LOAD;\n  iram0_2_phdr PT_LOAD;\n  iram0_3_phdr PT_LOAD;\n  iram0_4_phdr PT_LOAD;\n  iram0_5_phdr PT_LOAD;\n  iram0_6_phdr PT_LOAD;\n  iram0_7_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(_ResetVector)\n\n\/*  Memory boundary addresses:  *\/\n_memmap_mem_dram0_start = 0x60000000;\n_memmap_mem_dram0_end   = 0x60020000;\n_memmap_mem_iram0_start = 0x60020000;\n_memmap_mem_iram0_end   = 0x60040000;\n\n\/*  Memory segment boundary addresses:  *\/\n_memmap_seg_dram0_0_start = 0x60000000;\n_memmap_seg_dram0_0_max   = 0x60020000;\n_memmap_seg_iram0_0_start = 0x60020000;\n_memmap_seg_iram0_0_max   = 0x600202e0;\n_memmap_seg_iram0_1_start = 0x600202e0;\n_memmap_seg_iram0_1_max   = 0x600202e4;\n_memmap_seg_iram0_2_start = 0x600202e4;\n_memmap_seg_iram0_2_max   = 0x60020300;\n_memmap_seg_iram0_3_start = 0x60020300;\n_memmap_seg_iram0_3_max   = 0x60020304;\n_memmap_seg_iram0_4_start = 0x60020304;\n_memmap_seg_iram0_4_max   = 0x60020320;\n_memmap_seg_iram0_5_start = 0x60020320;\n_memmap_seg_iram0_5_max   = 0x60020324;\n_memmap_seg_iram0_6_start = 0x60020324;\n_memmap_seg_iram0_6_max   = 0x60020340;\n_memmap_seg_iram0_7_start = 0x60020340;\n_memmap_seg_iram0_7_max   = 0x60040000;\n\n_rom_store_table = 0;\nPROVIDE(_memmap_reset_vector = 0x60020000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00001000;\n_memmap_cacheattr_wt_base = 0x00001000;\n_memmap_cacheattr_bp_base = 0x00002000;\n_memmap_cacheattr_unused_mask = 0xFFFF0FFF;\n_memmap_cacheattr_wb_trapnull = 0x2222122F;\n_memmap_cacheattr_wba_trapnull = 0x2222122F;\n_memmap_cacheattr_wbna_trapnull = 0x2222122F;\n_memmap_cacheattr_wt_trapnull = 0x2222122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFF1FFF;\n_memmap_cacheattr_wt_strict = 0xFFFF1FFF;\n_memmap_cacheattr_bp_strict = 0xFFFF2FFF;\n_memmap_cacheattr_wb_allvalid = 0x22221222;\n_memmap_cacheattr_wt_allvalid = 0x22221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dram0.rodata : ALIGN(4)\n  {\n    _dram0_rodata_start = ABSOLUTE(.);\n    _image_ram_start = ABSOLUTE(.);\n    *(.dram0.rodata)\n    *(.dram.rodata)\n    _dram0_rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .dram0.literal : ALIGN(4)\n  {\n    _dram0_literal_start = ABSOLUTE(.);\n    *(.dram0.literal)\n    *(.dram.literal)\n    _dram0_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .dram0.data : ALIGN(4)\n  {\n    _dram0_data_start = ABSOLUTE(.);\n    *(.dram0.data)\n    *(.dram.data)\n    _dram0_data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .sram.data : ALIGN(4)\n  {\n    _sram_data_start = ABSOLUTE(.);\n    *(.sram.data)\n    _sram_data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >dram0_0_seg :dram0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n\tKEEP(*(.isr_irq*))\n\t\/* sections for IRQ0-9 *\/\n\tKEEP(*(SORT(.gnu.linkonce.d.isr_irq[0-9])))\n\t\/* sections for IRQ10-99 *\/\n\tKEEP(*(SORT(.gnu.linkonce.d.isr_irq[0-9][0-9])))\n\t\/* sections for IRQ100-999 *\/\n\tKEEP(*(SORT(.gnu.linkonce.d.isr_irq[0-9][0-9][0-9])))\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    *(.dram0.bss)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _end = ALIGN(0x8);\n    _image_ram_end = ABSOLUTE(.);\n    PROVIDE(end = ALIGN(0x8));\n    _stack_sentry = ALIGN(0x8);\n    _memmap_seg_dram0_0_end = ALIGN(0x8);\n  } >dram0_0_seg :dram0_0_bss_phdr\n  __stack = 0x60020000;\n  _heap_sentry = 0x60020000;\n\n  .ResetVector.text : ALIGN(4)\n  {\n    _image_rom_start = ABSOLUTE(.);\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n    _memmap_seg_iram0_0_end = ALIGN(0x8);\n  } >iram0_0_seg :iram0_0_phdr\n\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n    _memmap_seg_iram0_1_end = ALIGN(0x8);\n  } >iram0_1_seg :iram0_1_phdr\n\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n    _memmap_seg_iram0_2_end = ALIGN(0x8);\n  } >iram0_2_seg :iram0_2_phdr\n\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n    _memmap_seg_iram0_3_end = ALIGN(0x8);\n  } >iram0_3_seg :iram0_3_phdr\n\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n    _memmap_seg_iram0_4_end = ALIGN(0x8);\n  } >iram0_4_seg :iram0_4_phdr\n\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n    _memmap_seg_iram0_5_end = ALIGN(0x8);\n  } >iram0_5_seg :iram0_5_phdr\n\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n    _memmap_seg_iram0_6_end = ALIGN(0x8);\n  } >iram0_6_seg :iram0_6_phdr\n\n  .iram0.text : ALIGN(4)\n  {\n    _iram0_text_start = ABSOLUTE(.);\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    _iram0_text_end = ABSOLUTE(.);\n    _image_rom_end = ABSOLUTE(.);\n  } >iram0_7_seg :iram0_7_phdr\n\n  _image_text_start =  ALIGN(4);\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_7_seg :iram0_7_phdr\n  _image_text_end = .;\n  .debug  0 :  { *(.debug) }\n  .line  0 :  { *(.line) }\n  .debug_srcinfo  0 :  { *(.debug_srcinfo) }\n  .debug_sfnames  0 :  { *(.debug_sfnames) }\n  .debug_aranges  0 :  { *(.debug_aranges) }\n  .debug_pubnames  0 :  { *(.debug_pubnames) }\n  .debug_info  0 :  { *(.debug_info) }\n  .debug_abbrev  0 :  { *(.debug_abbrev) }\n  .debug_line  0 :  { *(.debug_line) }\n  .debug_frame  0 :  { *(.debug_frame) }\n  .debug_str  0 :  { *(.debug_str) }\n  .debug_loc  0 :  { *(.debug_loc) }\n  .debug_macinfo  0 :  { *(.debug_macinfo) }\n  .debug_weaknames  0 :  { *(.debug_weaknames) }\n  .debug_funcnames  0 :  { *(.debug_funcnames) }\n  .debug_typenames  0 :  { *(.debug_typenames) }\n  .debug_varnames  0 :  { *(.debug_varnames) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .debug.xt.callgraph 0 :\n  {\n    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))\n  }\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define ROMABLE_REGION iram0_7_seg :iram0_7_phdr\n\n#include <linker\/common-rom.ld>\n#include <linker\/common-ram.ld>\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\nMEMORY\n{\n  dram0_0_seg :                       \torg = 0x60000000, len = 0x20000\n  iram0_0_seg :                       \torg = 0x60020000, len = 0x2E0\n  iram0_1_seg :                       \torg = 0x600202E0, len = 0x4\n  iram0_2_seg :                       \torg = 0x600202E4, len = 0x1C\n  iram0_3_seg :                       \torg = 0x60020300, len = 0x4\n  iram0_4_seg :                       \torg = 0x60020304, len = 0x1C\n  iram0_5_seg :                       \torg = 0x60020320, len = 0x4\n  iram0_6_seg :                       \torg = 0x60020324, len = 0x1C\n  iram0_7_seg :                       \torg = 0x60020340, len = 0x1FCC0\n}\n\nPHDRS\n{\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  iram0_1_phdr PT_LOAD;\n  iram0_2_phdr PT_LOAD;\n  iram0_3_phdr PT_LOAD;\n  iram0_4_phdr PT_LOAD;\n  iram0_5_phdr PT_LOAD;\n  iram0_6_phdr PT_LOAD;\n  iram0_7_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(_ResetVector)\n\n\/*  Memory boundary addresses:  *\/\n_memmap_mem_dram0_start = 0x60000000;\n_memmap_mem_dram0_end   = 0x60020000;\n_memmap_mem_iram0_start = 0x60020000;\n_memmap_mem_iram0_end   = 0x60040000;\n\n\/*  Memory segment boundary addresses:  *\/\n_memmap_seg_dram0_0_start = 0x60000000;\n_memmap_seg_dram0_0_max   = 0x60020000;\n_memmap_seg_iram0_0_start = 0x60020000;\n_memmap_seg_iram0_0_max   = 0x600202e0;\n_memmap_seg_iram0_1_start = 0x600202e0;\n_memmap_seg_iram0_1_max   = 0x600202e4;\n_memmap_seg_iram0_2_start = 0x600202e4;\n_memmap_seg_iram0_2_max   = 0x60020300;\n_memmap_seg_iram0_3_start = 0x60020300;\n_memmap_seg_iram0_3_max   = 0x60020304;\n_memmap_seg_iram0_4_start = 0x60020304;\n_memmap_seg_iram0_4_max   = 0x60020320;\n_memmap_seg_iram0_5_start = 0x60020320;\n_memmap_seg_iram0_5_max   = 0x60020324;\n_memmap_seg_iram0_6_start = 0x60020324;\n_memmap_seg_iram0_6_max   = 0x60020340;\n_memmap_seg_iram0_7_start = 0x60020340;\n_memmap_seg_iram0_7_max   = 0x60040000;\n\n_rom_store_table = 0;\nPROVIDE(_memmap_reset_vector = 0x60020000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00001000;\n_memmap_cacheattr_wt_base = 0x00001000;\n_memmap_cacheattr_bp_base = 0x00002000;\n_memmap_cacheattr_unused_mask = 0xFFFF0FFF;\n_memmap_cacheattr_wb_trapnull = 0x2222122F;\n_memmap_cacheattr_wba_trapnull = 0x2222122F;\n_memmap_cacheattr_wbna_trapnull = 0x2222122F;\n_memmap_cacheattr_wt_trapnull = 0x2222122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFF1FFF;\n_memmap_cacheattr_wt_strict = 0xFFFF1FFF;\n_memmap_cacheattr_bp_strict = 0xFFFF2FFF;\n_memmap_cacheattr_wb_allvalid = 0x22221222;\n_memmap_cacheattr_wt_allvalid = 0x22221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dram0.rodata : ALIGN(4)\n  {\n    _dram0_rodata_start = ABSOLUTE(.);\n    _image_ram_start = ABSOLUTE(.);\n    *(.dram0.rodata)\n    *(.dram.rodata)\n    _dram0_rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .dram0.literal : ALIGN(4)\n  {\n    _dram0_literal_start = ABSOLUTE(.);\n    *(.dram0.literal)\n    *(.dram.literal)\n    _dram0_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .dram0.data : ALIGN(4)\n  {\n    _dram0_data_start = ABSOLUTE(.);\n    *(.dram0.data)\n    *(.dram.data)\n    _dram0_data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .sram.data : ALIGN(4)\n  {\n    _sram_data_start = ABSOLUTE(.);\n    *(.sram.data)\n    _sram_data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >dram0_0_seg :dram0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n\tKEEP(*(.isr_irq*))\n\t\/* sections for IRQ0-9 *\/\n\tKEEP(*(SORT(.gnu.linkonce.d.isr_irq[0-9])))\n\t\/* sections for IRQ10-99 *\/\n\tKEEP(*(SORT(.gnu.linkonce.d.isr_irq[0-9][0-9])))\n\t\/* sections for IRQ100-999 *\/\n\tKEEP(*(SORT(.gnu.linkonce.d.isr_irq[0-9][0-9][0-9])))\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    *(.dram0.bss)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _end = ALIGN(0x8);\n    _image_ram_end = ABSOLUTE(.);\n    PROVIDE(end = ALIGN(0x8));\n    _stack_sentry = ALIGN(0x8);\n    _memmap_seg_dram0_0_end = ALIGN(0x8);\n  } >dram0_0_seg :dram0_0_bss_phdr\n  __stack = 0x60020000;\n  _heap_sentry = 0x60020000;\n\n  .ResetVector.text : ALIGN(4)\n  {\n    _image_rom_start = ABSOLUTE(.);\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n    _memmap_seg_iram0_0_end = ALIGN(0x8);\n  } >iram0_0_seg :iram0_0_phdr\n\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n    _memmap_seg_iram0_1_end = ALIGN(0x8);\n  } >iram0_1_seg :iram0_1_phdr\n\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n    _memmap_seg_iram0_2_end = ALIGN(0x8);\n  } >iram0_2_seg :iram0_2_phdr\n\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n    _memmap_seg_iram0_3_end = ALIGN(0x8);\n  } >iram0_3_seg :iram0_3_phdr\n\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n    _memmap_seg_iram0_4_end = ALIGN(0x8);\n  } >iram0_4_seg :iram0_4_phdr\n\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n    _memmap_seg_iram0_5_end = ALIGN(0x8);\n  } >iram0_5_seg :iram0_5_phdr\n\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n    _memmap_seg_iram0_6_end = ALIGN(0x8);\n  } >iram0_6_seg :iram0_6_phdr\n\n  .iram0.text : ALIGN(4)\n  {\n    _iram0_text_start = ABSOLUTE(.);\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    _iram0_text_end = ABSOLUTE(.);\n    _image_rom_end = ABSOLUTE(.);\n  } >iram0_7_seg :iram0_7_phdr\n\n  _image_text_start =  ALIGN(4);\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_7_seg :iram0_7_phdr\n  _image_text_end = .;\n  .debug  0 :  { *(.debug) }\n  .line  0 :  { *(.line) }\n  .debug_srcinfo  0 :  { *(.debug_srcinfo) }\n  .debug_sfnames  0 :  { *(.debug_sfnames) }\n  .debug_aranges  0 :  { *(.debug_aranges) }\n  .debug_pubnames  0 :  { *(.debug_pubnames) }\n  .debug_info  0 :  { *(.debug_info) }\n  .debug_abbrev  0 :  { *(.debug_abbrev) }\n  .debug_line  0 :  { *(.debug_line) }\n  .debug_frame  0 :  { *(.debug_frame) }\n  .debug_str  0 :  { *(.debug_str) }\n  .debug_loc  0 :  { *(.debug_loc) }\n  .debug_macinfo  0 :  { *(.debug_macinfo) }\n  .debug_weaknames  0 :  { *(.debug_weaknames) }\n  .debug_funcnames  0 :  { *(.debug_funcnames) }\n  .debug_typenames  0 :  { *(.debug_typenames) }\n  .debug_varnames  0 :  { *(.debug_varnames) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .debug.xt.callgraph 0 :\n  {\n    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))\n  }\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n#define RAMABLE_REGION sram0_0_seg :sram0_0_phdr\n#define ROMABLE_REGION srom1_seg :srom1_phdr\n\n#include <linker\/common-rom.ld>\n#include <linker\/common-ram.ld>\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"faea55f1dc3014d38d484522ba88c1f3fc1c3b7a","subject":"Update dead link in documentation","message":"Update dead link in documentation\n\nCloses #48.","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n\t\/* Include the \"small data\" in the data section. Otherwise it will be\n\t * dropped when the TBF is created.\n\t *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n\t\/* Include the \"small data\" in the data section. Otherwise it will be\n\t * dropped when the TBF is created.\n\t *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"34d449df7931b018a6c40ed769dd5ee7480a16c7","subject":"linker: add DWARF-5 debug sections","message":"linker: add DWARF-5 debug sections\n\nDWARF-5 standard replaced the location list (.debug_loc) and range\nlist (.debug_ranges) sections with new sections (.debug_loclists\nand .debug_rnglists).\nThey weren't handled which resulted in many orphan sections\nreported as warnings by linker.\n\nSigned-off-by: Micha\u0142 Barna\u015b <77666125932addc6fc525b281b518fd8fd2203d8@semihalf.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/linker\/debug-sections.ld","new_file":"include\/linker\/debug-sections.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\t\/* following sections are obtained via 'ld --verbose' *\/\n\n\t\/* Stabs debugging sections. *\/\n\tSECTION_PROLOGUE(.stab, 0,)            { *(.stab) }\n\tSECTION_PROLOGUE(.stabstr, 0,)         { *(.stabstr) }\n\tSECTION_PROLOGUE(.stab.excl, 0,)       { *(.stab.excl) }\n\tSECTION_PROLOGUE(.stab.exclstr, 0,)    { *(.stab.exclstr) }\n\tSECTION_PROLOGUE(.stab.index, 0,)      { *(.stab.index) }\n\tSECTION_PROLOGUE(.stab.indexstr, 0,)   { *(.stab.indexstr) }\n\tSECTION_PROLOGUE(.gnu.build.attributes, 0,) { *(.gnu.build.attributes .gnu.build.attributes.*) }\n\tSECTION_PROLOGUE(.comment, 0,)         { *(.comment) }\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\t\/* DWARF 1 *\/\n\tSECTION_PROLOGUE(.debug, 0,)           { *(.debug) }\n\tSECTION_PROLOGUE(.line, 0,)            { *(.line) }\n\t\/* GNU DWARF 1 extensions *\/\n\tSECTION_PROLOGUE(.debug_srcinfo, 0,)   { *(.debug_srcinfo) }\n\tSECTION_PROLOGUE(.debug_sfnames, 0,)   { *(.debug_sfnames) }\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\tSECTION_PROLOGUE(.debug_aranges, 0,)   { *(.debug_aranges) }\n\tSECTION_PROLOGUE(.debug_pubnames, 0,)  { *(.debug_pubnames) }\n\t\/* DWARF 2 *\/\n\tSECTION_PROLOGUE(.debug_info, 0,)      { *(.debug_info .gnu.linkonce.wi.*) }\n\tSECTION_PROLOGUE(.debug_abbrev, 0,)    { *(.debug_abbrev) }\n\tSECTION_PROLOGUE(.debug_line, 0,)      { *(.debug_line .debug_line.* .debug_line_end ) }\n\tSECTION_PROLOGUE(.debug_frame, 0,)     { *(.debug_frame) }\n\tSECTION_PROLOGUE(.debug_str, 0,)       { *(.debug_str) }\n\tSECTION_PROLOGUE(.debug_loc, 0,)       { *(.debug_loc) }\n\tSECTION_PROLOGUE(.debug_macinfo, 0,)   { *(.debug_macinfo) }\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\tSECTION_PROLOGUE(.debug_weaknames, 0,) { *(.debug_weaknames) }\n\tSECTION_PROLOGUE(.debug_funcnames, 0,) { *(.debug_funcnames) }\n\tSECTION_PROLOGUE(.debug_typenames, 0,) { *(.debug_typenames) }\n\tSECTION_PROLOGUE(.debug_varnames, 0,)  { *(.debug_varnames) }\n\t\/* DWARF 3 *\/\n\tSECTION_PROLOGUE(.debug_pubtypes, 0,)  { *(.debug_pubtypes) }\n\tSECTION_PROLOGUE(.debug_ranges, 0,)    { *(.debug_ranges) }\n\t\/* DWARF Extension. *\/\n\tSECTION_PROLOGUE(.debug_macro, 0,)     { *(.debug_macro) }\n\t\/* DWARF 5 *\/\n\tSECTION_PROLOGUE(.debug_line_str, 0,)  { *(.debug_line_str) }\n\tSECTION_PROLOGUE(.debug_loclists, 0,)  { *(.debug_loclists) }\n\tSECTION_PROLOGUE(.debug_rnglists, 0,)  { *(.debug_rnglists) }\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\t\/* following sections are obtained via 'ld --verbose' *\/\n\n\t\/* Stabs debugging sections. *\/\n\tSECTION_PROLOGUE(.stab, 0,)            { *(.stab) }\n\tSECTION_PROLOGUE(.stabstr, 0,)         { *(.stabstr) }\n\tSECTION_PROLOGUE(.stab.excl, 0,)       { *(.stab.excl) }\n\tSECTION_PROLOGUE(.stab.exclstr, 0,)    { *(.stab.exclstr) }\n\tSECTION_PROLOGUE(.stab.index, 0,)      { *(.stab.index) }\n\tSECTION_PROLOGUE(.stab.indexstr, 0,)   { *(.stab.indexstr) }\n\tSECTION_PROLOGUE(.gnu.build.attributes, 0,) { *(.gnu.build.attributes .gnu.build.attributes.*) }\n\tSECTION_PROLOGUE(.comment, 0,)         { *(.comment) }\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\t\/* DWARF 1 *\/\n\tSECTION_PROLOGUE(.debug, 0,)           { *(.debug) }\n\tSECTION_PROLOGUE(.line, 0,)            { *(.line) }\n\t\/* GNU DWARF 1 extensions *\/\n\tSECTION_PROLOGUE(.debug_srcinfo, 0,)   { *(.debug_srcinfo) }\n\tSECTION_PROLOGUE(.debug_sfnames, 0,)   { *(.debug_sfnames) }\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\tSECTION_PROLOGUE(.debug_aranges, 0,)   { *(.debug_aranges) }\n\tSECTION_PROLOGUE(.debug_pubnames, 0,)  { *(.debug_pubnames) }\n\t\/* DWARF 2 *\/\n\tSECTION_PROLOGUE(.debug_info, 0,)      { *(.debug_info .gnu.linkonce.wi.*) }\n\tSECTION_PROLOGUE(.debug_abbrev, 0,)    { *(.debug_abbrev) }\n\tSECTION_PROLOGUE(.debug_line, 0,)      { *(.debug_line .debug_line.* .debug_line_end ) }\n\tSECTION_PROLOGUE(.debug_frame, 0,)     { *(.debug_frame) }\n\tSECTION_PROLOGUE(.debug_str, 0,)       { *(.debug_str) }\n\tSECTION_PROLOGUE(.debug_loc, 0,)       { *(.debug_loc) }\n\tSECTION_PROLOGUE(.debug_macinfo, 0,)   { *(.debug_macinfo) }\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\tSECTION_PROLOGUE(.debug_weaknames, 0,) { *(.debug_weaknames) }\n\tSECTION_PROLOGUE(.debug_funcnames, 0,) { *(.debug_funcnames) }\n\tSECTION_PROLOGUE(.debug_typenames, 0,) { *(.debug_typenames) }\n\tSECTION_PROLOGUE(.debug_varnames, 0,)  { *(.debug_varnames) }\n\t\/* DWARF 3 *\/\n\tSECTION_PROLOGUE(.debug_pubtypes, 0,)  { *(.debug_pubtypes) }\n\tSECTION_PROLOGUE(.debug_ranges, 0,)    { *(.debug_ranges) }\n\t\/* DWARF Extension. *\/\n\tSECTION_PROLOGUE(.debug_macro, 0,)     { *(.debug_macro) }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"956b733d0f4999a5c5f6fbf42abaa96d79c91013","subject":"[STM32F676] correcting memory sizes for gcc_arm","message":"[STM32F676] correcting memory sizes for gcc_arm\n","repos":"adustm\/mbed,mazimkhan\/mbed-os,c1728p9\/mbed-os,svogl\/mbed-os,pradeep-gr\/mbed-os5-onsemi,bulislaw\/mbed-os,YarivCol\/mbed-os,HeadsUpDisplayInc\/mbed,geky\/mbed,ryankurte\/mbed-os,CalSol\/mbed,screamerbg\/mbed,svogl\/mbed-os,fahhem\/mbed-os,mazimkhan\/mbed-os,rgrover\/mbed,karsev\/mbed-os,bcostm\/mbed-os,tung7970\/mbed-os-1,fahhem\/mbed-os,svastm\/mbed,NXPmicro\/mbed,CalSol\/mbed,screamerbg\/mbed,geky\/mbed,infinnovation\/mbed-os,j-greffe\/mbed-os,nRFMesh\/mbed-os,bulislaw\/mbed-os,mikaleppanen\/mbed-os,bulislaw\/mbed-os,betzw\/mbed-os,c1728p9\/mbed-os,ryankurte\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,mazimkhan\/mbed-os,nvlsianpu\/mbed,kl-cruz\/mbed-os,rgrover\/mbed,nRFMesh\/mbed-os,mmorenobarm\/mbed-os,fvincenzo\/mbed-os,theotherjimmy\/mbed,svastm\/mbed,tung7970\/mbed-os,adamgreen\/mbed,pradeep-gr\/mbed-os5-onsemi,netzimme\/mbed-os,andcor02\/mbed-os,arostm\/mbed-os,kjbracey-arm\/mbed,cvtsi2sd\/mbed-os,theotherjimmy\/mbed,nRFMesh\/mbed-os,jeremybrodt\/mbed,rgrover\/mbed,andreaslarssonublox\/mbed,arostm\/mbed-os,j-greffe\/mbed-os,fanghuaqi\/mbed,bcostm\/mbed-os,maximmbed\/mbed,netzimme\/mbed-os,jeremybrodt\/mbed,netzimme\/mbed-os,nRFMesh\/mbed-os,c1728p9\/mbed-os,YarivCol\/mbed-os,andreaslarssonublox\/mbed,fahhem\/mbed-os,maximmbed\/mbed,arostm\/mbed-os,nvlsianpu\/mbed,karsev\/mbed-os,mikaleppanen\/mbed-os,catiedev\/mbed-os,fanghuaqi\/mbed,tung7970\/mbed-os-1,arostm\/mbed-os,karsev\/mbed-os,ryankurte\/mbed-os,kjbracey-arm\/mbed,catiedev\/mbed-os,bcostm\/mbed-os,fvincenzo\/mbed-os,cvtsi2sd\/mbed-os,j-greffe\/mbed-os,geky\/mbed,arostm\/mbed-os,theotherjimmy\/mbed,cvtsi2sd\/mbed-os,HeadsUpDisplayInc\/mbed,catiedev\/mbed-os,jeremybrodt\/mbed,adamgreen\/mbed,ryankurte\/mbed-os,andreaslarssonublox\/mbed,bcostm\/mbed-os,maximmbed\/mbed,mikaleppanen\/mbed-os,theotherjimmy\/mbed,mbedmicro\/mbed,j-greffe\/mbed-os,pradeep-gr\/mbed-os5-onsemi,kl-cruz\/mbed-os,betzw\/mbed-os,YarivCol\/mbed-os,monkiineko\/mbed-os,NXPmicro\/mbed,mikaleppanen\/mbed-os,cvtsi2sd\/mbed-os,Archcady\/mbed-os,adustm\/mbed,fahhem\/mbed-os,netzimme\/mbed-os,tung7970\/mbed-os-1,HeadsUpDisplayInc\/mbed,netzimme\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,NXPmicro\/mbed,mikaleppanen\/mbed-os,adamgreen\/mbed,andcor02\/mbed-os,theotherjimmy\/mbed,mmorenobarm\/mbed-os,kl-cruz\/mbed-os,mbedmicro\/mbed,rgrover\/mbed,geky\/mbed,bcostm\/mbed-os,bulislaw\/mbed-os,CalSol\/mbed,andreaslarssonublox\/mbed,HeadsUpDisplayInc\/mbed,betzw\/mbed-os,andcor02\/mbed-os,infinnovation\/mbed-os,svogl\/mbed-os,bulislaw\/mbed-os,screamerbg\/mbed,c1728p9\/mbed-os,adustm\/mbed,rgrover\/mbed,bulislaw\/mbed-os,infinnovation\/mbed-os,maximmbed\/mbed,tung7970\/mbed-os-1,betzw\/mbed-os,j-greffe\/mbed-os,fvincenzo\/mbed-os,andcor02\/mbed-os,nvlsianpu\/mbed,monkiineko\/mbed-os,YarivCol\/mbed-os,kl-cruz\/mbed-os,NXPmicro\/mbed,adamgreen\/mbed,catiedev\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,geky\/mbed,mbedmicro\/mbed,fahhem\/mbed-os,screamerbg\/mbed,fvincenzo\/mbed-os,infinnovation\/mbed-os,svogl\/mbed-os,tung7970\/mbed-os,mazimkhan\/mbed-os,mbedmicro\/mbed,nRFMesh\/mbed-os,RonEld\/mbed,infinnovation\/mbed-os,monkiineko\/mbed-os,screamerbg\/mbed,tung7970\/mbed-os-1,mmorenobarm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,kjbracey-arm\/mbed,Archcady\/mbed-os,fahhem\/mbed-os,infinnovation\/mbed-os,pradeep-gr\/mbed-os5-onsemi,andcor02\/mbed-os,RonEld\/mbed,andreaslarssonublox\/mbed,mazimkhan\/mbed-os,CalSol\/mbed,adustm\/mbed,karsev\/mbed-os,kl-cruz\/mbed-os,nvlsianpu\/mbed,monkiineko\/mbed-os,andcor02\/mbed-os,Archcady\/mbed-os,cvtsi2sd\/mbed-os,pradeep-gr\/mbed-os5-onsemi,tung7970\/mbed-os,mikaleppanen\/mbed-os,maximmbed\/mbed,nvlsianpu\/mbed,nRFMesh\/mbed-os,jeremybrodt\/mbed,ryankurte\/mbed-os,kjbracey-arm\/mbed,Archcady\/mbed-os,kl-cruz\/mbed-os,tung7970\/mbed-os,fvincenzo\/mbed-os,NXPmicro\/mbed,YarivCol\/mbed-os,ryankurte\/mbed-os,HeadsUpDisplayInc\/mbed,Archcady\/mbed-os,mmorenobarm\/mbed-os,svastm\/mbed,adustm\/mbed,mazimkhan\/mbed-os,adustm\/mbed,fanghuaqi\/mbed,monkiineko\/mbed-os,RonEld\/mbed,betzw\/mbed-os,NXPmicro\/mbed,svastm\/mbed,Archcady\/mbed-os,tung7970\/mbed-os,jeremybrodt\/mbed,RonEld\/mbed,catiedev\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,monkiineko\/mbed-os,karsev\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,RonEld\/mbed,svogl\/mbed-os,theotherjimmy\/mbed,CalSol\/mbed,YarivCol\/mbed-os,HeadsUpDisplayInc\/mbed,fanghuaqi\/mbed,cvtsi2sd\/mbed-os,maximmbed\/mbed,mmorenobarm\/mbed-os,svogl\/mbed-os,mbedmicro\/mbed,netzimme\/mbed-os,adamgreen\/mbed,betzw\/mbed-os,catiedev\/mbed-os,fanghuaqi\/mbed,nvlsianpu\/mbed,c1728p9\/mbed-os,svastm\/mbed,mmorenobarm\/mbed-os,arostm\/mbed-os,bcostm\/mbed-os,j-greffe\/mbed-os,adamgreen\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,RonEld\/mbed,screamerbg\/mbed,c1728p9\/mbed-os,karsev\/mbed-os,CalSol\/mbed","old_file":"hal\/targets\/cmsis\/TARGET_STM\/TARGET_STM32F7\/TARGET_NUCLEO_F767ZI\/TOOLCHAIN_GCC_ARM\/STM32F767ZI.ld","new_file":"hal\/targets\/cmsis\/TARGET_STM\/TARGET_STM32F7\/TARGET_NUCLEO_F767ZI\/TOOLCHAIN_GCC_ARM\/STM32F767ZI.ld","new_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K\n  RAM (rwx)  : ORIGIN = 0x200001F8, LENGTH = 512K - 0x1F8\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (rwx)  : ORIGIN = 0x200001F8, LENGTH = 320K - 0x1F8\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7137b7d5c40ec654d4dff5806b2f2777a6da4239","subject":"cpu\/nrf52\/ldscripts: extend script for multislot usage","message":"cpu\/nrf52\/ldscripts: extend script for multislot usage\n","repos":"OTAkeys\/RIOT,adrianghc\/RIOT,jasonatran\/RIOT,toonst\/RIOT,LudwigOrtmann\/RIOT,RIOT-OS\/RIOT,immesys\/RiSyn,kYc0o\/RIOT,gebart\/RIOT,kYc0o\/RIOT,Josar\/RIOT,hamilton-mote\/RIOT-OS,mfrey\/RIOT,OlegHahm\/RIOT,LudwigKnuepfer\/RIOT,kYc0o\/RIOT,A-Paul\/RIOT,cladmi\/RIOT,biboc\/RIOT,avmelnikoff\/RIOT,thomaseichinger\/RIOT,LudwigKnuepfer\/RIOT,cladmi\/RIOT,aeneby\/RIOT,rfuentess\/RIOT,neiljay\/RIOT,smlng\/RIOT,biboc\/RIOT,OTAkeys\/RIOT,plushvoxel\/RIOT,plushvoxel\/RIOT,biboc\/RIOT,OlegHahm\/RIOT,Josar\/RIOT,josephnoir\/RIOT,mtausig\/RIOT,mtausig\/RIOT,miri64\/RIOT,x3ro\/RIOT,kerneltask\/RIOT,plushvoxel\/RIOT,yogo1212\/RIOT,beurdouche\/RIOT,aeneby\/RIOT,smlng\/RIOT,adrianghc\/RIOT,plushvoxel\/RIOT,rfuentess\/RIOT,kerneltask\/RIOT,cladmi\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,avmelnikoff\/RIOT,gebart\/RIOT,lazytech-org\/RIOT,smlng\/RIOT,miri64\/RIOT,yogo1212\/RIOT,miri64\/RIOT,josephnoir\/RIOT,mfrey\/RIOT,aeneby\/RIOT,roberthartung\/RIOT,smlng\/RIOT,mtausig\/RIOT,thomaseichinger\/RIOT,adjih\/RIOT,Josar\/RIOT,rfuentess\/RIOT,miri64\/RIOT,lazytech-org\/RIOT,jasonatran\/RIOT,mfrey\/RIOT,A-Paul\/RIOT,neumodisch\/RIOT,LudwigKnuepfer\/RIOT,basilfx\/RIOT,LudwigOrtmann\/RIOT,kerneltask\/RIOT,immesys\/RiSyn,gebart\/RIOT,ks156\/RIOT,beurdouche\/RIOT,Josar\/RIOT,ant9000\/RIOT,basilfx\/RIOT,BytesGalore\/RIOT,beurdouche\/RIOT,neumodisch\/RIOT,OlegHahm\/RIOT,rfuentess\/RIOT,BytesGalore\/RIOT,adjih\/RIOT,biboc\/RIOT,toonst\/RIOT,lazytech-org\/RIOT,mtausig\/RIOT,beurdouche\/RIOT,x3ro\/RIOT,immesys\/RiSyn,jfischer-phytec-iot\/RIOT,immesys\/RiSyn,smlng\/RIOT,roberthartung\/RIOT,immesys\/RiSyn,ks156\/RIOT,LudwigOrtmann\/RIOT,hamilton-mote\/RIOT-OS,adjih\/RIOT,neumodisch\/RIOT,beurdouche\/RIOT,yogo1212\/RIOT,ant9000\/RIOT,roberthartung\/RIOT,jfischer-phytec-iot\/RIOT,authmillenon\/RIOT,lazytech-org\/RIOT,josephnoir\/RIOT,immesys\/RiSyn,adrianghc\/RIOT,A-Paul\/RIOT,avmelnikoff\/RIOT,neiljay\/RIOT,OlegHahm\/RIOT,neumodisch\/RIOT,LudwigOrtmann\/RIOT,LudwigKnuepfer\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,LudwigKnuepfer\/RIOT,x3ro\/RIOT,ks156\/RIOT,jfischer-phytec-iot\/RIOT,OTAkeys\/RIOT,biboc\/RIOT,neumodisch\/RIOT,neiljay\/RIOT,LudwigOrtmann\/RIOT,RIOT-OS\/RIOT,hamilton-mote\/RIOT-OS,jfischer-phytec-iot\/RIOT,OlegHahm\/RIOT,kbumsik\/RIOT,kYc0o\/RIOT,josephnoir\/RIOT,roberthartung\/RIOT,ks156\/RIOT,authmillenon\/RIOT,kerneltask\/RIOT,kYc0o\/RIOT,yogo1212\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,gebart\/RIOT,josephnoir\/RIOT,x3ro\/RIOT,aeneby\/RIOT,aeneby\/RIOT,OTAkeys\/RIOT,avmelnikoff\/RIOT,yogo1212\/RIOT,adjih\/RIOT,authmillenon\/RIOT,toonst\/RIOT,yogo1212\/RIOT,BytesGalore\/RIOT,kbumsik\/RIOT,kerneltask\/RIOT,thomaseichinger\/RIOT,neiljay\/RIOT,toonst\/RIOT,rfuentess\/RIOT,neiljay\/RIOT,jfischer-phytec-iot\/RIOT,RIOT-OS\/RIOT,mfrey\/RIOT,LudwigOrtmann\/RIOT,authmillenon\/RIOT,plushvoxel\/RIOT,kbumsik\/RIOT,hamilton-mote\/RIOT-OS,authmillenon\/RIOT,adrianghc\/RIOT,roberthartung\/RIOT,ant9000\/RIOT,kbumsik\/RIOT,avmelnikoff\/RIOT,miri64\/RIOT,A-Paul\/RIOT,ks156\/RIOT,OTAkeys\/RIOT,mtausig\/RIOT,adjih\/RIOT,adrianghc\/RIOT,thomaseichinger\/RIOT,gebart\/RIOT,BytesGalore\/RIOT,Josar\/RIOT,basilfx\/RIOT,basilfx\/RIOT,lazytech-org\/RIOT,basilfx\/RIOT,authmillenon\/RIOT,mfrey\/RIOT,cladmi\/RIOT,jasonatran\/RIOT,thomaseichinger\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,toonst\/RIOT,ant9000\/RIOT,cladmi\/RIOT,kbumsik\/RIOT,neumodisch\/RIOT,kaspar030\/RIOT,hamilton-mote\/RIOT-OS,x3ro\/RIOT,A-Paul\/RIOT,BytesGalore\/RIOT,jasonatran\/RIOT","old_file":"cpu\/nrf52\/ldscripts\/nrf52832xxaa.ld","new_file":"cpu\/nrf52\/ldscripts\/nrf52832xxaa.ld","new_contents":"\/*\n * Copyright (C) 2016 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_nrf52\n * @{\n *\n * @file\n * @brief           Memory definitions for the NRF52832XXAA\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n *\n * @}\n *\/\n\nrom_length = 512K;\n\nINCLUDE multislot.ld\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x00000000 + boot_offset, LENGTH = rom_length\n    ram (rwx)   : ORIGIN = 0x20000000,               LENGTH = 64K\n}\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2016 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_nrf52\n * @{\n *\n * @file\n * @brief           Memory definitions for the NRF52832XXAA\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x00000000, LENGTH = 512K\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 64K\n}\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"04bcfbfa723df8cc674f4efc3bf90aca516f995b","subject":"Remove the heap used with the new MicroBlaze demo.  As heap_2.c is being used, the heap area set up in the linker script is not required.","message":"Remove the heap used with the new MicroBlaze demo.  As heap_2.c is being used, the heap area set up in the linker script is not required.\n\ngit-svn-id: 43aea61533866f88f23079d48f4f5dc2d5288937@1455 1d2547de-c912-0410-9cb9-b8ca96c0e9e2\n","repos":"Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos","old_file":"Demo\/MicroBlaze_Spartan-6_EthernetLite\/SDKProjects\/RTOSDemoSource\/src\/lscript.ld","new_file":"Demo\/MicroBlaze_Spartan-6_EthernetLite\/SDKProjects\/RTOSDemoSource\/src\/lscript.ld","new_contents":"\/*******************************************************************\/\r\n\/*                                                                 *\/\r\n\/* This file is automatically generated by linker script generator.*\/\r\n\/*                                                                 *\/\r\n\/* Version: Xilinx EDK 13.1 EDK_O.40d                                *\/\r\n\/*                                                                 *\/\r\n\/* Copyright (c) 2010 Xilinx, Inc.  All rights reserved.           *\/\r\n\/*                                                                 *\/\r\n\/* Description : MicroBlaze Linker Script                          *\/\r\n\/*                                                                 *\/\r\n\/*******************************************************************\/\r\n\r\n_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;\r\n_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x8;\r\n\r\n\/* Define Memories in the system *\/\r\n\r\nMEMORY\r\n{\r\n   microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl : ORIGIN = 0x00000050, LENGTH = 0x00001FB0\r\n   MCB_DDR3_S0_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x08000000\r\n}\r\n\r\n\/* Specify the default entry point to the program *\/\r\n\r\nENTRY(_start)\r\n\r\n\/* Define the sections, and where they are mapped in memory *\/\r\n\r\nSECTIONS\r\n{\r\n.vectors.reset 0x00000000 : {\r\n   *(.vectors.reset)\r\n} \r\n\r\n.vectors.sw_exception 0x00000008 : {\r\n   *(.vectors.sw_exception)\r\n} \r\n\r\n.vectors.interrupt 0x00000010 : {\r\n   *(.vectors.interrupt)\r\n} \r\n\r\n.vectors.hw_exception 0x00000020 : {\r\n   *(.vectors.hw_exception)\r\n} \r\n\r\n.text : {\r\n   *(.text)\r\n   *(.text.*)\r\n   *(.gnu.linkonce.t.*)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.init : {\r\n   KEEP (*(.init))\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.fini : {\r\n   KEEP (*(.fini))\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.rodata : {\r\n   __rodata_start = .;\r\n   *(.rodata)\r\n   *(.rodata.*)\r\n   *(.gnu.linkonce.r.*)\r\n   __rodata_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.sdata2 : {\r\n   . = ALIGN(8);\r\n   __sdata2_start = .;\r\n   *(.sdata2)\r\n   *(.sdata2.*)\r\n   *(.gnu.linkonce.s2.*)\r\n   . = ALIGN(8);\r\n   __sdata2_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.sbss2 : {\r\n   __sbss2_start = .;\r\n   *(.sbss2)\r\n   *(.sbss2.*)\r\n   *(.gnu.linkonce.sb2.*)\r\n   __sbss2_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.data : {\r\n   . = ALIGN(4);\r\n   __data_start = .;\r\n   *(.data)\r\n   *(.data.*)\r\n   *(.gnu.linkonce.d.*)\r\n   __data_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.got : {\r\n   *(.got)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.got1 : {\r\n   *(.got1)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.got2 : {\r\n   *(.got2)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.ctors : {\r\n   __CTOR_LIST__ = .;\r\n   ___CTORS_LIST___ = .;\r\n   KEEP (*crtbegin.o(.ctors))\r\n   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))\r\n   KEEP (*(SORT(.ctors.*)))\r\n   KEEP (*(.ctors))\r\n   __CTOR_END__ = .;\r\n   ___CTORS_END___ = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.dtors : {\r\n   __DTOR_LIST__ = .;\r\n   ___DTORS_LIST___ = .;\r\n   KEEP (*crtbegin.o(.dtors))\r\n   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))\r\n   KEEP (*(SORT(.dtors.*)))\r\n   KEEP (*(.dtors))\r\n   __DTOR_END__ = .;\r\n   ___DTORS_END___ = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.eh_frame : {\r\n   *(.eh_frame)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.jcr : {\r\n   *(.jcr)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.gcc_except_table : {\r\n   *(.gcc_except_table)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.sdata : {\r\n   . = ALIGN(8);\r\n   __sdata_start = .;\r\n   *(.sdata)\r\n   *(.sdata.*)\r\n   *(.gnu.linkonce.s.*)\r\n   __sdata_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.sbss : {\r\n   . = ALIGN(4);\r\n   __sbss_start = .;\r\n   *(.sbss)\r\n   *(.sbss.*)\r\n   *(.gnu.linkonce.sb.*)\r\n   . = ALIGN(8);\r\n   __sbss_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.tdata : {\r\n   __tdata_start = .;\r\n   *(.tdata)\r\n   *(.tdata.*)\r\n   *(.gnu.linkonce.td.*)\r\n   __tdata_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.tbss : {\r\n   __tbss_start = .;\r\n   *(.tbss)\r\n   *(.tbss.*)\r\n   *(.gnu.linkonce.tb.*)\r\n   __tbss_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.bss : {\r\n   . = ALIGN(4);\r\n   __bss_start = .;\r\n   *(.bss)\r\n   *(.bss.*)\r\n   *(.gnu.linkonce.b.*)\r\n   *(COMMON)\r\n   . = ALIGN(4);\r\n   __bss_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) \/ 2 );\r\n\r\n_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) \/ 2 );\r\n\r\n\/* Generate Stack and Heap definitions *\/\r\n\r\n.heap : {\r\n   . = ALIGN(8);\r\n   _heap = .;\r\n   _heap_start = .;\r\n   . += _HEAP_SIZE;\r\n   _heap_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.stack : {\r\n   _stack_end = .;\r\n   . += _STACK_SIZE;\r\n   . = ALIGN(8);\r\n   _stack = .;\r\n   __stack = _stack;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n_end = .;\r\n}\r\n\r\n","old_contents":"\/*******************************************************************\/\r\n\/*                                                                 *\/\r\n\/* This file is automatically generated by linker script generator.*\/\r\n\/*                                                                 *\/\r\n\/* Version: Xilinx EDK 13.1 EDK_O.40d                                *\/\r\n\/*                                                                 *\/\r\n\/* Copyright (c) 2010 Xilinx, Inc.  All rights reserved.           *\/\r\n\/*                                                                 *\/\r\n\/* Description : MicroBlaze Linker Script                          *\/\r\n\/*                                                                 *\/\r\n\/*******************************************************************\/\r\n\r\n_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;\r\n_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;\r\n\r\n\/* Define Memories in the system *\/\r\n\r\nMEMORY\r\n{\r\n   microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl : ORIGIN = 0x00000050, LENGTH = 0x00001FB0\r\n   MCB_DDR3_S0_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x08000000\r\n}\r\n\r\n\/* Specify the default entry point to the program *\/\r\n\r\nENTRY(_start)\r\n\r\n\/* Define the sections, and where they are mapped in memory *\/\r\n\r\nSECTIONS\r\n{\r\n.vectors.reset 0x00000000 : {\r\n   *(.vectors.reset)\r\n} \r\n\r\n.vectors.sw_exception 0x00000008 : {\r\n   *(.vectors.sw_exception)\r\n} \r\n\r\n.vectors.interrupt 0x00000010 : {\r\n   *(.vectors.interrupt)\r\n} \r\n\r\n.vectors.hw_exception 0x00000020 : {\r\n   *(.vectors.hw_exception)\r\n} \r\n\r\n.text : {\r\n   *(.text)\r\n   *(.text.*)\r\n   *(.gnu.linkonce.t.*)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.init : {\r\n   KEEP (*(.init))\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.fini : {\r\n   KEEP (*(.fini))\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.rodata : {\r\n   __rodata_start = .;\r\n   *(.rodata)\r\n   *(.rodata.*)\r\n   *(.gnu.linkonce.r.*)\r\n   __rodata_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.sdata2 : {\r\n   . = ALIGN(8);\r\n   __sdata2_start = .;\r\n   *(.sdata2)\r\n   *(.sdata2.*)\r\n   *(.gnu.linkonce.s2.*)\r\n   . = ALIGN(8);\r\n   __sdata2_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.sbss2 : {\r\n   __sbss2_start = .;\r\n   *(.sbss2)\r\n   *(.sbss2.*)\r\n   *(.gnu.linkonce.sb2.*)\r\n   __sbss2_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.data : {\r\n   . = ALIGN(4);\r\n   __data_start = .;\r\n   *(.data)\r\n   *(.data.*)\r\n   *(.gnu.linkonce.d.*)\r\n   __data_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.got : {\r\n   *(.got)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.got1 : {\r\n   *(.got1)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.got2 : {\r\n   *(.got2)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.ctors : {\r\n   __CTOR_LIST__ = .;\r\n   ___CTORS_LIST___ = .;\r\n   KEEP (*crtbegin.o(.ctors))\r\n   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))\r\n   KEEP (*(SORT(.ctors.*)))\r\n   KEEP (*(.ctors))\r\n   __CTOR_END__ = .;\r\n   ___CTORS_END___ = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.dtors : {\r\n   __DTOR_LIST__ = .;\r\n   ___DTORS_LIST___ = .;\r\n   KEEP (*crtbegin.o(.dtors))\r\n   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))\r\n   KEEP (*(SORT(.dtors.*)))\r\n   KEEP (*(.dtors))\r\n   __DTOR_END__ = .;\r\n   ___DTORS_END___ = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.eh_frame : {\r\n   *(.eh_frame)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.jcr : {\r\n   *(.jcr)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.gcc_except_table : {\r\n   *(.gcc_except_table)\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.sdata : {\r\n   . = ALIGN(8);\r\n   __sdata_start = .;\r\n   *(.sdata)\r\n   *(.sdata.*)\r\n   *(.gnu.linkonce.s.*)\r\n   __sdata_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.sbss : {\r\n   . = ALIGN(4);\r\n   __sbss_start = .;\r\n   *(.sbss)\r\n   *(.sbss.*)\r\n   *(.gnu.linkonce.sb.*)\r\n   . = ALIGN(8);\r\n   __sbss_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.tdata : {\r\n   __tdata_start = .;\r\n   *(.tdata)\r\n   *(.tdata.*)\r\n   *(.gnu.linkonce.td.*)\r\n   __tdata_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.tbss : {\r\n   __tbss_start = .;\r\n   *(.tbss)\r\n   *(.tbss.*)\r\n   *(.gnu.linkonce.tb.*)\r\n   __tbss_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.bss : {\r\n   . = ALIGN(4);\r\n   __bss_start = .;\r\n   *(.bss)\r\n   *(.bss.*)\r\n   *(.gnu.linkonce.b.*)\r\n   *(COMMON)\r\n   . = ALIGN(4);\r\n   __bss_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) \/ 2 );\r\n\r\n_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) \/ 2 );\r\n\r\n\/* Generate Stack and Heap definitions *\/\r\n\r\n.heap : {\r\n   . = ALIGN(8);\r\n   _heap = .;\r\n   _heap_start = .;\r\n   . += _HEAP_SIZE;\r\n   _heap_end = .;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n.stack : {\r\n   _stack_end = .;\r\n   . += _STACK_SIZE;\r\n   . = ALIGN(8);\r\n   _stack = .;\r\n   __stack = _stack;\r\n} > MCB_DDR3_S0_AXI_BASEADDR\r\n\r\n_end = .;\r\n}\r\n\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ed73e07e491fd992c34d4c8192b7e9843452f6b5","subject":"fix syntax error in stubs ld file","message":"fix syntax error in stubs ld file\n","repos":"Solo5\/solo5,Solo5\/solo5","old_file":"bindings\/solo5_stub.lds","new_file":"bindings\/solo5_stub.lds","new_contents":"\/*\n * Copyright (c) 2015-2021 Contributors as noted in the AUTHORS file\n *\n * This file is part of Solo5, a sandboxed execution environment.\n *\n * Permission to use, copy, modify, and\/or distribute this software\n * for any purpose with or without fee is hereby granted, provided\n * that the above copyright notice and this permission notice appear\n * in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL\n * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE\n * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR\n * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS\n * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,\n * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN\n * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\/\n\n\/*\n * This is the custom linker script for the Solo5 'stub' target.\n *\n * The script is tested to work with a minimal set of input sections. If there\n * are unexpected input sections not named here, the result will probably not be\n * correct.\n *\/\nTEXT_START = 0x100000;\n\nENTRY(_start)\n\n\/*\n * Program headers: In order to force the linker to place each of our NOTEs\n * into a separate PT_NOTE header, we need to lay these out explicitly.\n *\/\nPHDRS {\n    interp PT_INTERP;\n    text PT_LOAD FLAGS(5); \/* No FILEHDR or PHDRS, force R\/E only.\n                              FLAGS values come from PF_x in elf.h *\/\n    data PT_LOAD;\n    note.not_openbsd PT_NOTE; \/* Must come first. *\/\n    note.abi PT_NOTE;\n    note.manifest PT_NOTE;\n}\n\n\/*\n * Output sections.\n *\/\nSECTIONS {\n    . = TEXT_START; \/* No + SIZEOF_HEADERS *\/\n\n    \/*\n     * :text: The following input sections are placed in the R\/E :text segment.\n     *\/\n    _stext = .;\n\n    .interp : {\n        *(.interp)\n    } :interp :text\n\n    .text :\n    {\n        *(.text)\n        *(.text.*)\n    } :text\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _etext = .;\n\n    \/* Read-only data *\/\n\n    \/* For Hvt, the ABI and MFT NOTEs are read-only and can be in :text. *\/\n    .note.solo5.manifest :\n    {\n        *(.note.solo5.manifest*)\n    } :text :note.manifest\n    .note.solo5.abi :\n    {\n        *(.note.solo5.abi*)\n    } :text :note.abi\n    .note.solo5.not_openbsd :\n    {\n        *(.note.solo5.not_openbsd*)\n    } :text :note.not_openbsd\n\n    .rodata :\n    {\n        *(.rodata)\n        *(.rodata.*)\n    } :text\n    .eh_frame :\n    {\n        *(.eh_frame)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _erodata = .;\n\n    \/*\n     * :data: The following input sections are placed in the R\/W :data segment.\n     *\/\n\n    \/* Read-write data (initialized) *\/\n    .got :\n    {\n        *(.got.plt)\n        *(.got)\n    } :data\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n    }\n    .tdata :\n    {\n        *(.tdata)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _edata = .;\n\n    \/* Read-write data (uninitialized) *\/\n    .tbss :\n    {\n        *(.tbss)\n    }\n    .bss :\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _ebss = .;\n    _end = .;\n\n    \/* We are not building a GNU executable, so discard any default NOTEs the\n       toolchain might generate to prevent any surprises in the final layout. *\/\n    \/DISCARD\/ : {\n        *(.note.gnu.*)\n    }\n}\n","old_contents":"\/*\n * Copyright (c) 2015-2021 Contributors as noted in the AUTHORS file\n *\n * This file is part of Solo5, a sandboxed execution environment.\n *\n * Permission to use, copy, modify, and\/or distribute this software\n * for any purpose with or without fee is hereby granted, provided\n * that the above copyright notice and this permission notice appear\n * in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL\n * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE\n * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR\n * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS\n * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,\n * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN\n * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\/\n\n\/*\n * This is the custom linker script for the Solo5 'stub' target.\n *\n * The script is tested to work with a minimal set of input sections. If there\n * are unexpected input sections not named here, the result will probably not be\n * correct.\n *\/\nTEXT_START = 0x100000;\n\nENTRY(_start)\n\n\/*\n * Program headers: In order to force the linker to place each of our NOTEs\n * into a separate PT_NOTE header, we need to lay these out explicitly.\n *\/\nPHDRS {\n    interp PT_INTERP;\n    text PT_LOAD FLAGS(5); \/* No FILEHDR or PHDRS, force R\/E only.\n                              FLAGS values come from PF_x in elf.h *\/\n    data PT_LOAD;\n    note.not-openbsd PT_NOTE; \/* Must come first. *\/\n    note.abi PT_NOTE;\n    note.manifest PT_NOTE;\n}\n\n\/*\n * Output sections.\n *\/\nSECTIONS {\n    . = TEXT_START; \/* No + SIZEOF_HEADERS *\/\n\n    \/*\n     * :text: The following input sections are placed in the R\/E :text segment.\n     *\/\n    _stext = .;\n\n    .interp : {\n        *(.interp)\n    } :interp :text\n\n    .text :\n    {\n        *(.text)\n        *(.text.*)\n    } :text\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _etext = .;\n\n    \/* Read-only data *\/\n\n    \/* For Hvt, the ABI and MFT NOTEs are read-only and can be in :text. *\/\n    .note.solo5.manifest :\n    {\n        *(.note.solo5.manifest*)\n    } :text :note.manifest\n    .note.solo5.abi :\n    {\n        *(.note.solo5.abi*)\n    } :text :note.abi\n    .note.solo5.not-openbsd :\n    {\n        *(.note.solo5.not-openbsd*)\n    } :text :note.not-openbsd\n\n    .rodata :\n    {\n        *(.rodata)\n        *(.rodata.*)\n    } :text\n    .eh_frame :\n    {\n        *(.eh_frame)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _erodata = .;\n\n    \/*\n     * :data: The following input sections are placed in the R\/W :data segment.\n     *\/\n\n    \/* Read-write data (initialized) *\/\n    .got :\n    {\n        *(.got.plt)\n        *(.got)\n    } :data\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n    }\n    .tdata :\n    {\n        *(.tdata)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _edata = .;\n\n    \/* Read-write data (uninitialized) *\/\n    .tbss :\n    {\n        *(.tbss)\n    }\n    .bss :\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _ebss = .;\n    _end = .;\n\n    \/* We are not building a GNU executable, so discard any default NOTEs the\n       toolchain might generate to prevent any surprises in the final layout. *\/\n    \/DISCARD\/ : {\n        *(.note.gnu.*)\n    }\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"a1a2fec25938c62b705cfefe30108798cf9397ea","subject":"[LPC4088]: Corrected RAM size in linker script (ARM_GCC)","message":"[LPC4088]: Corrected RAM size in linker script (ARM_GCC)\n","repos":"pradeep-gr\/mbed-os5-onsemi,mazimkhan\/mbed-os,jeremybrodt\/mbed,fvincenzo\/mbed-os,0xc0170\/mbed-drivers,EmuxEvans\/mbed,pbrook\/mbed,jpbrucker\/mbed,nvlsianpu\/mbed,ryankurte\/mbed-os,fahhem\/mbed-os,logost\/mbed,larks\/mbed,Timmmm\/mbed,pbrook\/mbed,hwfwgrp\/mbed,HeadsUpDisplayInc\/mbed,K4zuki\/mbed,K4zuki\/mbed,alertby\/mbed,RonEld\/mbed,nabilbendafi\/mbed,fahhem\/mbed-os,theotherjimmy\/mbed,svastm\/mbed,bulislaw\/mbed-os,struempelix\/mbed,rosterloh\/mbed,karsev\/mbed-os,bentwire\/mbed,geky\/mbed,RonEld\/mbed,mbedmicro\/mbed,EmuxEvans\/mbed,catiedev\/mbed-os,svogl\/mbed-os,pedromes\/mbed,getopenmono\/mbed,nvlsianpu\/mbed,pbrook\/mbed,mmorenobarm\/mbed-os,jrjang\/mbed,Shengliang\/mbed,mmorenobarm\/mbed-os,rgrover\/mbed,hwfwgrp\/mbed,mazimkhan\/mbed-os,devanlai\/mbed,andreaslarssonublox\/mbed,rosterloh\/mbed,Marcomissyou\/mbed,adamgreen\/mbed,arostm\/mbed-os,kl-cruz\/mbed-os,pi19404\/mbed,Timmmm\/mbed,andcor02\/mbed-os,devanlai\/mbed,sg-\/mbed-drivers,HeadsUpDisplayInc\/mbed,fpiot\/mbed-ats,bremoran\/mbed-drivers,kl-cruz\/mbed-os,al177\/mbed,ryankurte\/mbed-os,svogl\/mbed-os,jamesadevine\/mbed,alertby\/mbed,rosterloh\/mbed,wodji\/mbed,bcostm\/mbed-os,andreaslarssonublox\/mbed,maximmbed\/mbed,sam-geek\/mbed,Archcady\/mbed-os,fanghuaqi\/mbed,GustavWi\/mbed,logost\/mbed,Tiryoh\/mbed,fvincenzo\/mbed-os,NXPmicro\/mbed,bcostm\/mbed-os,larks\/mbed,logost\/mbed,svastm\/mbed,c1728p9\/mbed-os,catiedev\/mbed-os,cvtsi2sd\/mbed-os,maximmbed\/mbed,EmuxEvans\/mbed,kl-cruz\/mbed-os,maximmbed\/mbed,brstew\/MBED-BUILD,j-greffe\/mbed-os,naves-thiago\/mbed-midi,fpiot\/mbed-ats,Willem23\/mbed,jpbrucker\/mbed,pradeep-gr\/mbed-os5-onsemi,ban4jp\/mbed,JasonHow44\/mbed,bulislaw\/mbed-os,j-greffe\/mbed-os,DanKupiniak\/mbed,0xc0170\/mbed-drivers,Tiryoh\/mbed,betzw\/mbed-os,nvlsianpu\/mbed,tung7970\/mbed-os,jamesadevine\/mbed,betzw\/mbed-os,Sweet-Peas\/mbed,adustm\/mbed,kpurusho\/mbed,jamesadevine\/mbed,GustavWi\/mbed,naves-thiago\/mbed-midi,EmuxEvans\/mbed,c1728p9\/mbed-os,rgrover\/mbed,svogl\/mbed-os,bentwire\/mbed,bremoran\/mbed-drivers,Willem23\/mbed,alertby\/mbed,Willem23\/mbed,Willem23\/mbed,mmorenobarm\/mbed-os,screamerbg\/mbed,cvtsi2sd\/mbed-os,sam-geek\/mbed,pi19404\/mbed,Archcady\/mbed-os,jferreir\/mbed,brstew\/MBED-BUILD,jpbrucker\/mbed,adamgreen\/mbed,karsev\/mbed-os,nabilbendafi\/mbed,FranklyDev\/mbed,naves-thiago\/mbed-midi,svastm\/mbed,bentwire\/mbed,al177\/mbed,arostm\/mbed-os,dbestm\/mbed,iriark01\/mbed-drivers,jferreir\/mbed,betzw\/mbed-os,mnlipp\/mbed,logost\/mbed,catiedev\/mbed-os,arostm\/mbed-os,geky\/mbed,j-greffe\/mbed-os,kjbracey-arm\/mbed,pi19404\/mbed,JasonHow44\/mbed,YarivCol\/mbed-os,mikaleppanen\/mbed-os,NXPmicro\/mbed,Shengliang\/mbed,jpbrucker\/mbed,ban4jp\/mbed,c1728p9\/mbed-os,masaohamanaka\/mbed,infinnovation\/mbed-os,sam-geek\/mbed,theotherjimmy\/mbed,pradeep-gr\/mbed-os5-onsemi,autopulated\/mbed,bentwire\/mbed,FranklyDev\/mbed,infinnovation\/mbed-os,adustm\/mbed,nRFMesh\/mbed-os,bikeNomad\/mbed,monkiineko\/mbed-os,ban4jp\/mbed,bikeNomad\/mbed,Shengliang\/mbed,adustm\/mbed,masaohamanaka\/mbed,svogl\/mbed-os,nRFMesh\/mbed-os,adamgreen\/mbed,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,mbedmicro\/mbed,nRFMesh\/mbed-os,nvlsianpu\/mbed,struempelix\/mbed,bulislaw\/mbed-os,rosterloh\/mbed,catiedev\/mbed-os,bcostm\/mbed-os,jrjang\/mbed,tung7970\/mbed-os-1,mazimkhan\/mbed-os,netzimme\/mbed-os,j-greffe\/mbed-os,masaohamanaka\/mbed,geky\/mbed,dbestm\/mbed,al177\/mbed,Marcomissyou\/mbed,K4zuki\/mbed,brstew\/MBED-BUILD,kpurusho\/mbed,arostm\/mbed-os,maximmbed\/mbed,larks\/mbed,YarivCol\/mbed-os,RonEld\/mbed,NordicSemiconductor\/mbed,screamerbg\/mbed,Marcomissyou\/mbed,FranklyDev\/mbed,mnlipp\/mbed,fahhem\/mbed-os,alertby\/mbed,NordicSemiconductor\/mbed,K4zuki\/mbed,iriark01\/mbed-drivers,ryankurte\/mbed-os,autopulated\/mbed,nabilbendafi\/mbed,CalSol\/mbed,K4zuki\/mbed,fanghuaqi\/mbed,struempelix\/mbed,ryankurte\/mbed-os,betzw\/mbed-os,ARM-software\/mbed-beetle,cvtsi2sd\/mbed-os,YarivCol\/mbed-os,Marcomissyou\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,sg-\/mbed-drivers,struempelix\/mbed,xcrespo\/mbed,pedromes\/mbed,NXPmicro\/mbed,NXPmicro\/mbed,screamerbg\/mbed,pbrook\/mbed,autopulated\/mbed,Sweet-Peas\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,rosterloh\/mbed,jeremybrodt\/mbed,GustavWi\/mbed,pi19404\/mbed,kl-cruz\/mbed-os,pedromes\/mbed,adustm\/mbed,cvtsi2sd\/mbed-os,cvtsi2sd\/mbed-os,larks\/mbed,jrjang\/mbed,pradeep-gr\/mbed-os5-onsemi,nvlsianpu\/mbed,netzimme\/mbed-os,infinnovation\/mbed-os,sam-geek\/mbed,mnlipp\/mbed,mbedmicro\/mbed,bikeNomad\/mbed,kpurusho\/mbed,bikeNomad\/mbed,Tiryoh\/mbed,betzw\/mbed-os,screamerbg\/mbed,andcor02\/mbed-os,betzw\/mbed-os,rgrover\/mbed,rgrover\/mbed,geky\/mbed,monkiineko\/mbed-os,jrjang\/mbed,Willem23\/mbed,tung7970\/mbed-os-1,pi19404\/mbed,netzimme\/mbed-os,andcor02\/mbed-os,mikaleppanen\/mbed-os,autopulated\/mbed,andcor02\/mbed-os,Tiryoh\/mbed,RonEld\/mbed,NordicSemiconductor\/mbed,c1728p9\/mbed-os,arostm\/mbed-os,brstew\/MBED-BUILD,j-greffe\/mbed-os,mbedmicro\/mbed,catiedev\/mbed-os,NXPmicro\/mbed,nRFMesh\/mbed-os,dbestm\/mbed,fpiot\/mbed-ats,nabilbendafi\/mbed,xcrespo\/mbed,Timmmm\/mbed,svogl\/mbed-os,jeremybrodt\/mbed,ban4jp\/mbed,mikaleppanen\/mbed-os,Marcomissyou\/mbed,mazimkhan\/mbed-os,bcostm\/mbed-os,andreaslarssonublox\/mbed,andcor02\/mbed-os,larks\/mbed,pradeep-gr\/mbed-os5-onsemi,xcrespo\/mbed,JasonHow44\/mbed,svogl\/mbed-os,Timmmm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,naves-thiago\/mbed-midi,adamgreen\/mbed,pedromes\/mbed,brstew\/MBED-BUILD,infinnovation\/mbed-os,pradeep-gr\/mbed-os5-onsemi,sam-geek\/mbed,mikaleppanen\/mbed-os,monkiineko\/mbed-os,GustavWi\/mbed,JasonHow44\/mbed,CalSol\/mbed,brstew\/MBED-BUILD,nvlsianpu\/mbed,FranklyDev\/mbed,CalSol\/mbed,masaohamanaka\/mbed,jeremybrodt\/mbed,kjbracey-arm\/mbed,maximmbed\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,fpiot\/mbed-ats,screamerbg\/mbed,bcostm\/mbed-os,adamgreen\/mbed,jferreir\/mbed,svastm\/mbed,mnlipp\/mbed,jferreir\/mbed,ryankurte\/mbed-os,kl-cruz\/mbed-os,getopenmono\/mbed,jferreir\/mbed,jferreir\/mbed,DanKupiniak\/mbed,mazimkhan\/mbed-os,fanghuaqi\/mbed,NitinBhaskar\/mbed,mikaleppanen\/mbed-os,bulislaw\/mbed-os,JasonHow44\/mbed,karsev\/mbed-os,getopenmono\/mbed,tung7970\/mbed-os,kl-cruz\/mbed-os,EmuxEvans\/mbed,kjbracey-arm\/mbed,adamgreen\/mbed,mbedmicro\/mbed,Shengliang\/mbed,HeadsUpDisplayInc\/mbed,andcor02\/mbed-os,theotherjimmy\/mbed,kjbracey-arm\/mbed,NitinBhaskar\/mbed,Tiryoh\/mbed,theotherjimmy\/mbed,Archcady\/mbed-os,wodji\/mbed,fpiot\/mbed-ats,jpbrucker\/mbed,j-greffe\/mbed-os,adustm\/mbed,jpbrucker\/mbed,fanghuaqi\/mbed,bulislaw\/mbed-os,bentwire\/mbed,kpurusho\/mbed,xcrespo\/mbed,struempelix\/mbed,andreaslarssonublox\/mbed,nabilbendafi\/mbed,monkiineko\/mbed-os,Sweet-Peas\/mbed,Sweet-Peas\/mbed,netzimme\/mbed-os,mazimkhan\/mbed-os,Timmmm\/mbed,tung7970\/mbed-os-1,autopulated\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,mnlipp\/mbed,masaohamanaka\/mbed,logost\/mbed,ban4jp\/mbed,Shengliang\/mbed,pi19404\/mbed,fvincenzo\/mbed-os,K4zuki\/mbed,pedromes\/mbed,theotherjimmy\/mbed,mmorenobarm\/mbed-os,al177\/mbed,JasonHow44\/mbed,kpurusho\/mbed,Sweet-Peas\/mbed,larks\/mbed,al177\/mbed,ARM-software\/mbed-beetle,NordicSemiconductor\/mbed,arostm\/mbed-os,bulislaw\/mbed-os,karsev\/mbed-os,al177\/mbed,jamesadevine\/mbed,monkiineko\/mbed-os,wodji\/mbed,infinnovation\/mbed-os,DanKupiniak\/mbed,logost\/mbed,cvtsi2sd\/mbed-os,Archcady\/mbed-os,getopenmono\/mbed,HeadsUpDisplayInc\/mbed,jamesadevine\/mbed,YarivCol\/mbed-os,c1728p9\/mbed-os,theotherjimmy\/mbed,alertby\/mbed,mikaleppanen\/mbed-os,xcrespo\/mbed,NitinBhaskar\/mbed,geky\/mbed,tung7970\/mbed-os,kpurusho\/mbed,fahhem\/mbed-os,andreaslarssonublox\/mbed,ban4jp\/mbed,Shengliang\/mbed,pbrook\/mbed,fahhem\/mbed-os,rosterloh\/mbed,jrjang\/mbed,screamerbg\/mbed,hwfwgrp\/mbed,EmuxEvans\/mbed,Timmmm\/mbed,NitinBhaskar\/mbed,fahhem\/mbed-os,jamesadevine\/mbed,FranklyDev\/mbed,hwfwgrp\/mbed,wodji\/mbed,jeremybrodt\/mbed,Archcady\/mbed-os,Archcady\/mbed-os,YarivCol\/mbed-os,hwfwgrp\/mbed,wodji\/mbed,jrjang\/mbed,fvincenzo\/mbed-os,Sweet-Peas\/mbed,Tiryoh\/mbed,HeadsUpDisplayInc\/mbed,devanlai\/mbed,struempelix\/mbed,bcostm\/mbed-os,xcrespo\/mbed,adustm\/mbed,dbestm\/mbed,pbrook\/mbed,nabilbendafi\/mbed,getopenmono\/mbed,mnlipp\/mbed,NXPmicro\/mbed,Marcomissyou\/mbed,maximmbed\/mbed,ryankurte\/mbed-os,bentwire\/mbed,wodji\/mbed,devanlai\/mbed,masaohamanaka\/mbed,YarivCol\/mbed-os,karsev\/mbed-os,bikeNomad\/mbed,dbestm\/mbed,netzimme\/mbed-os,tung7970\/mbed-os,RonEld\/mbed,netzimme\/mbed-os,alertby\/mbed,mmorenobarm\/mbed-os,pedromes\/mbed,fvincenzo\/mbed-os,nRFMesh\/mbed-os,catiedev\/mbed-os,hwfwgrp\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,dbestm\/mbed,monkiineko\/mbed-os,fanghuaqi\/mbed,CalSol\/mbed,CalSol\/mbed,mmorenobarm\/mbed-os,naves-thiago\/mbed-midi,naves-thiago\/mbed-midi,infinnovation\/mbed-os,autopulated\/mbed,GustavWi\/mbed,nRFMesh\/mbed-os,fpiot\/mbed-ats,karsev\/mbed-os,ARM-software\/mbed-beetle,devanlai\/mbed,svastm\/mbed,tung7970\/mbed-os-1,ARM-software\/mbed-beetle,NitinBhaskar\/mbed,getopenmono\/mbed,tung7970\/mbed-os,devanlai\/mbed,rgrover\/mbed,RonEld\/mbed,tung7970\/mbed-os-1,CalSol\/mbed,DanKupiniak\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC408X\/TOOLCHAIN_GCC_ARM\/LPC4088.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC408X\/TOOLCHAIN_GCC_ARM\/LPC4088.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000E8, LENGTH = (64K - 0xE8)\n\n  USB_RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20004000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Code can explicitly ask for data to be \n       placed in these higher RAM banks where\n       they will be left uninitialized. \n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000E8, LENGTH = (32K - 0xE8)\n\n  USB_RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20004000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Code can explicitly ask for data to be \n       placed in these higher RAM banks where\n       they will be left uninitialized. \n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f002c784c0af2272b1fdd5430379bc7775d89743","subject":"nrf: linker: add a new .uninitialized section","message":"nrf: linker: add a new .uninitialized section\n\nThis section immediately follows the .bss section, and is designed to\ncontain uninitialized variables that should persist across reboots.\n\nThe section is placed directly after .bss, under the theory that the\nsize of Circuit Python's .bss + .data is bigger than the bootloader's\n.bss + .data, so there is less likely to be a conflict.\n\nSigned-off-by: Sean Cross <d7e19930cc1f42c2d0781f4d9e6f1fe5891bf9cf@xobs.io>\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython","old_file":"ports\/nrf\/boards\/common.template.ld","new_file":"ports\/nrf\/boards\/common.template.ld","new_contents":"\/*\n    GNU linker script for NRF52840 w\/ s140 6.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = ${FLASH_SIZE} \/* entire flash *\/\n    \/* nRF SoftDevice *\/\n    FLASH_MBR (rx)  : ORIGIN = ${MBR_START_ADDR}, LENGTH = ${MBR_SIZE}\n    FLASH_SD (rx)   : ORIGIN = ${SD_FLASH_START_ADDR}, LENGTH = ${SD_FLASH_SIZE}\n    FLASH_ISR (rx)  : ORIGIN = ${ISR_START_ADDR}, LENGTH = ${ISR_SIZE}\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_BLE_CONFIG (r) : ORIGIN = ${CIRCUITPY_BLE_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_BLE_CONFIG_SIZE}\n    FLASH_NVM (r)   : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n    FLASH_FATFS (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_BOOTLOADER (rx) : ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n    FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}\n\n\n    \/* 0x2000000 - RAM:ORIGIN is reserved for Softdevice *\/\n    \/* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.\n    \/* To measure the minimum required amount of memory for given configuration, set this number\n       high enough to work and then check the mutation of the value done by sd_ble_enable. *\/\n    SPIM3_RAM (rw)  : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE}\n    RAM (xrw)       : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = ${RAM_SIZE} - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE}\n\n}\n\n\/* produce a link error if there is not this amount of RAM available *\/\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\n\/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. *\/\n_spim3_ram = ORIGIN(SPIM3_RAM);\n_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_FIRMWARE\n\n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH_FIRMWARE\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH_FIRMWARE\n    *\/\n\n    \/* used by the startup to initialize data *\/\n    _sidata = .;\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* Zero-initialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Uninitialized data section\n    Data placed into this section will remain unchanged across reboots. *\/\n    .uninitialized (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _suninitialized = .; \/* define a global symbol at uninitialized start; currently unused *\/\n        *(.uninitialized)\n        *(.uninitialized*)\n\n        . = ALIGN(4);\n        _euninitialized = .; \/* define a global symbol at uninitialized end; currently unused *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\t      PROVIDE ( end = . );\n\t      PROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n    GNU linker script for NRF52840 w\/ s140 6.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = ${FLASH_SIZE} \/* entire flash *\/\n    \/* nRF SoftDevice *\/\n    FLASH_MBR (rx)  : ORIGIN = ${MBR_START_ADDR}, LENGTH = ${MBR_SIZE}\n    FLASH_SD (rx)   : ORIGIN = ${SD_FLASH_START_ADDR}, LENGTH = ${SD_FLASH_SIZE}\n    FLASH_ISR (rx)  : ORIGIN = ${ISR_START_ADDR}, LENGTH = ${ISR_SIZE}\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_BLE_CONFIG (r) : ORIGIN = ${CIRCUITPY_BLE_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_BLE_CONFIG_SIZE}\n    FLASH_NVM (r)   : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n    FLASH_FATFS (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_BOOTLOADER (rx) : ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n    FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}\n\n\n    \/* 0x2000000 - RAM:ORIGIN is reserved for Softdevice *\/\n    \/* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.\n    \/* To measure the minimum required amount of memory for given configuration, set this number\n       high enough to work and then check the mutation of the value done by sd_ble_enable. *\/\n    SPIM3_RAM (rw)  : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE}\n    RAM (xrw)       : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = ${RAM_SIZE} - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE}\n\n}\n\n\/* produce a link error if there is not this amount of RAM available *\/\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\n\/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. *\/\n_spim3_ram = ORIGIN(SPIM3_RAM);\n_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_FIRMWARE\n\n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH_FIRMWARE\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH_FIRMWARE\n    *\/\n\n    \/* used by the startup to initialize data *\/\n    _sidata = .;\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\t      PROVIDE ( end = . );\n\t      PROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"1079866b339cf9d35fab962aa3f5721b69af3f86","subject":"k64f: Use kinetis_common ldscript","message":"k64f: Use kinetis_common ldscript\n","repos":"dailab\/RIOT,syin2\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,rfuentess\/RIOT,kbumsik\/RIOT,immesys\/RiSyn,kaleb-himes\/RIOT,toonst\/RIOT,LudwigOrtmann\/RIOT,aeneby\/RIOT,kerneltask\/RIOT,aeneby\/RIOT,mtausig\/RIOT,RIOT-OS\/RIOT,immesys\/RiSyn,ant9000\/RIOT,kYc0o\/RIOT,avmelnikoff\/RIOT,gautric\/RIOT,A-Paul\/RIOT,adjih\/RIOT,toonst\/RIOT,syin2\/RIOT,neiljay\/RIOT,ant9000\/RIOT,neumodisch\/RIOT,ant9000\/RIOT,ks156\/RIOT,LudwigOrtmann\/RIOT,kaspar030\/RIOT,x3ro\/RIOT,jasonatran\/RIOT,Josar\/RIOT,roberthartung\/RIOT,x3ro\/RIOT,avmelnikoff\/RIOT,lazytech-org\/RIOT,ant9000\/RIOT,A-Paul\/RIOT,smlng\/RIOT,rfuentess\/RIOT,josephnoir\/RIOT,mfrey\/RIOT,Ell-i\/RIOT,toonst\/RIOT,jfischer-phytec-iot\/RIOT,yogo1212\/RIOT,beurdouche\/RIOT,neumodisch\/RIOT,x3ro\/RIOT,x3ro\/RIOT,cladmi\/RIOT,josephnoir\/RIOT,lazytech-org\/RIOT,avmelnikoff\/RIOT,OTAkeys\/RIOT,kaspar030\/RIOT,Josar\/RIOT,dkm\/RIOT,mtausig\/RIOT,biboc\/RIOT,adjih\/RIOT,rfuentess\/RIOT,BytesGalore\/RIOT,ks156\/RIOT,jfischer-phytec-iot\/RIOT,immesys\/RiSyn,basilfx\/RIOT,RIOT-OS\/RIOT,mtausig\/RIOT,plushvoxel\/RIOT,dkm\/RIOT,rfuentess\/RIOT,neiljay\/RIOT,kerneltask\/RIOT,cladmi\/RIOT,authmillenon\/RIOT,Hyungsin\/RIOT-OS,ks156\/RIOT,OlegHahm\/RIOT,Hyungsin\/RIOT-OS,OlegHahm\/RIOT,jasonatran\/RIOT,mtausig\/RIOT,authmillenon\/RIOT,biboc\/RIOT,adjih\/RIOT,mtausig\/RIOT,RIOT-OS\/RIOT,LudwigOrtmann\/RIOT,kYc0o\/RIOT,Ell-i\/RIOT,basilfx\/RIOT,adrianghc\/RIOT,authmillenon\/RIOT,Ell-i\/RIOT,LudwigOrtmann\/RIOT,yogo1212\/RIOT,neumodisch\/RIOT,dailab\/RIOT,authmillenon\/RIOT,avmelnikoff\/RIOT,smlng\/RIOT,kaleb-himes\/RIOT,miri64\/RIOT,jasonatran\/RIOT,kbumsik\/RIOT,kerneltask\/RIOT,BytesGalore\/RIOT,basilfx\/RIOT,BytesGalore\/RIOT,Hyungsin\/RIOT-OS,OTAkeys\/RIOT,kerneltask\/RIOT,cladmi\/RIOT,plushvoxel\/RIOT,A-Paul\/RIOT,adrianghc\/RIOT,x3ro\/RIOT,aeneby\/RIOT,aeneby\/RIOT,gautric\/RIOT,mfrey\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,immesys\/RiSyn,josephnoir\/RIOT,biboc\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,LudwigKnuepfer\/RIOT,smlng\/RIOT,lazytech-org\/RIOT,dkm\/RIOT,neumodisch\/RIOT,Hyungsin\/RIOT-OS,thomaseichinger\/RIOT,kbumsik\/RIOT,LudwigKnuepfer\/RIOT,basilfx\/RIOT,adjih\/RIOT,Josar\/RIOT,jasonatran\/RIOT,miri64\/RIOT,beurdouche\/RIOT,lazytech-org\/RIOT,kYc0o\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,neiljay\/RIOT,smlng\/RIOT,gebart\/RIOT,RIOT-OS\/RIOT,biboc\/RIOT,roberthartung\/RIOT,syin2\/RIOT,adrianghc\/RIOT,LudwigKnuepfer\/RIOT,A-Paul\/RIOT,kaleb-himes\/RIOT,kaleb-himes\/RIOT,toonst\/RIOT,OlegHahm\/RIOT,LudwigOrtmann\/RIOT,dailab\/RIOT,miri64\/RIOT,beurdouche\/RIOT,mfrey\/RIOT,immesys\/RiSyn,dkm\/RIOT,ant9000\/RIOT,neumodisch\/RIOT,gebart\/RIOT,adrianghc\/RIOT,roberthartung\/RIOT,Ell-i\/RIOT,adrianghc\/RIOT,LudwigKnuepfer\/RIOT,thomaseichinger\/RIOT,gautric\/RIOT,beurdouche\/RIOT,authmillenon\/RIOT,roberthartung\/RIOT,BytesGalore\/RIOT,plushvoxel\/RIOT,kbumsik\/RIOT,roberthartung\/RIOT,miri64\/RIOT,hamilton-mote\/RIOT-OS,cladmi\/RIOT,neumodisch\/RIOT,cladmi\/RIOT,BytesGalore\/RIOT,kaspar030\/RIOT,josephnoir\/RIOT,aeneby\/RIOT,neiljay\/RIOT,jfischer-phytec-iot\/RIOT,gautric\/RIOT,kerneltask\/RIOT,thomaseichinger\/RIOT,OlegHahm\/RIOT,gautric\/RIOT,gebart\/RIOT,LudwigOrtmann\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,syin2\/RIOT,immesys\/RiSyn,foss-for-synopsys-dwc-arc-processors\/RIOT,yogo1212\/RIOT,mfrey\/RIOT,OTAkeys\/RIOT,yogo1212\/RIOT,hamilton-mote\/RIOT-OS,ks156\/RIOT,gebart\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,jfischer-phytec-iot\/RIOT,Hyungsin\/RIOT-OS,dailab\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,syin2\/RIOT,josephnoir\/RIOT,Ell-i\/RIOT,kaspar030\/RIOT,Josar\/RIOT,adjih\/RIOT,hamilton-mote\/RIOT-OS,miri64\/RIOT,biboc\/RIOT,rfuentess\/RIOT,basilfx\/RIOT,kbumsik\/RIOT,smlng\/RIOT,beurdouche\/RIOT,dailab\/RIOT,lazytech-org\/RIOT,toonst\/RIOT,kYc0o\/RIOT,gebart\/RIOT,kaleb-himes\/RIOT,jfischer-phytec-iot\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,mfrey\/RIOT,avmelnikoff\/RIOT,hamilton-mote\/RIOT-OS,kaspar030\/RIOT,neiljay\/RIOT,hamilton-mote\/RIOT-OS,dkm\/RIOT,thomaseichinger\/RIOT,ks156\/RIOT,plushvoxel\/RIOT,A-Paul\/RIOT,LudwigKnuepfer\/RIOT,Josar\/RIOT,plushvoxel\/RIOT,thomaseichinger\/RIOT","old_file":"cpu\/k64f\/ldscripts\/mk64fn1m0vll12.ld","new_file":"cpu\/k64f\/ldscripts\/mk64fn1m0vll12.ld","new_contents":"","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\nMEMORY\n{\n    vectors (rx) : ORIGIN = 0x00000000, LENGTH = 0x400\n    flashsec (rx): ORIGIN = 0x00000400, LENGTH = 0x10\n    rom (rx)     : ORIGIN = 0x00000410, LENGTH = 1024K - 0x410\n    ram (rwx)    : ORIGIN = 0x1fff0198, LENGTH = 256K-0x198\n}\n\nINCLUDE kinetis.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"d54e2d6c1e68f2edfa06a6a331e808f109df779f","subject":"ArmVirtPkg\/ArmVirtPrePiUniCoreRelocatable: deal with relaxed XIP alignment","message":"ArmVirtPkg\/ArmVirtPrePiUniCoreRelocatable: deal with relaxed XIP alignment\n\nCommit b89919ee8f8c (\"BaseTools AARCH64: override XIP module linker\nalignment to 32 bytes\") updated the various AARCH64 toolchain definitions\nto allow SEC, PEI_CORE and PEIM modules to be built with minimal alignment\nrequirements even when using the AArch64 small code model which normally\nrequires 4 KB section alignment.\n\nThis involves conversion of ADRP instructions into ADR instructions, which\ncan only be done reliably if the ELF and the PE\/COFF sections appear at\nthe same offset modulo 4 KB.\n\nThe ArmVirtPrePiUniCoreRelocatable linker script did not yet take this\ninto account, so update it by starting the .text section at the next\nappropriately aligned offset PECOFF_HEADER_SIZE bytes into the image.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org>\nAcked-by: Laszlo Ersek <7437296077edea1cb64451c122c4dac071f0cfbc@redhat.com>\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"ArmVirtPkg\/PrePi\/Scripts\/PrePi-PIE.lds","new_file":"ArmVirtPkg\/PrePi\/Scripts\/PrePi-PIE.lds","new_contents":"\/** @file\r\n\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n\r\n  This program and the accompanying materials\r\n  are licensed and made available under the terms and conditions of the BSD License\r\n  which accompanies this distribution.  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS\r\n{\r\n  PROVIDE(__reloc_base = .);\r\n\r\n  . = PECOFF_HEADER_SIZE;\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text*)\r\n    *(.got .got*)\r\n    *(.rodata .rodata*)\r\n    *(.data .data*)\r\n    *(.bss .bss*)\r\n\r\n    . = ALIGN(0x20);\r\n    PROVIDE(__reloc_start = .);\r\n    *(.rel .rel.*)\r\n    *(.rela .rela.*)\r\n    PROVIDE(__reloc_end = .);\r\n  }\r\n\r\n  .note (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu.hash)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynamic)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.hash)\r\n    *(.comment)\r\n  }\r\n}\r\n","old_contents":"\/** @file\r\n\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n\r\n  This program and the accompanying materials\r\n  are licensed and made available under the terms and conditions of the BSD License\r\n  which accompanies this distribution.  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS\r\n{\r\n  .text 0x0 : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    PROVIDE(__reloc_base = .);\r\n\r\n    *(.text .text*)\r\n    *(.got .got*)\r\n    *(.rodata .rodata*)\r\n    *(.data .data*)\r\n    *(.bss .bss*)\r\n\r\n    . = ALIGN(0x20);\r\n    PROVIDE(__reloc_start = .);\r\n    *(.rel .rel.*)\r\n    *(.rela .rela.*)\r\n    PROVIDE(__reloc_end = .);\r\n  }\r\n\r\n  .note (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu.hash)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynamic)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.hash)\r\n    *(.comment)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"17ef2df2cacc234e98f729ab60c3af9ec02dd08d","subject":"nrf: ld: add ARM.exidx to output image","message":"nrf: ld: add ARM.exidx to output image\n\nWith the WDT changes, building Circuit Python results in the following error:\n\n\/opt\/gcc-arm-none-eabi-9-2019-q4-major\/bin\/..\/lib\/gcc\/arm-none-eabi\/9.2.1\/..\/..\/..\/..\/arm-none-eabi\/bin\/ld: section .ARM.exidx LMA [00000000000621c8,00000000000621cf] overlaps section .data LMA [00000000000621c8,0000000000062383]\n\nThis is because unwinding data is getting generated, but has nowhere to go.\nRe-enable this data in the linker script so it is saved.\n\nSigned-off-by: Sean Cross <d7e19930cc1f42c2d0781f4d9e6f1fe5891bf9cf@xobs.io>\n","repos":"adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython","old_file":"ports\/nrf\/boards\/common.template.ld","new_file":"ports\/nrf\/boards\/common.template.ld","new_contents":"\/*\n    GNU linker script for NRF52840 w\/ s140 6.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = ${FLASH_SIZE} \/* entire flash *\/\n    \/* nRF SoftDevice *\/\n    FLASH_MBR (rx)  : ORIGIN = ${MBR_START_ADDR}, LENGTH = ${MBR_SIZE}\n    FLASH_SD (rx)   : ORIGIN = ${SD_FLASH_START_ADDR}, LENGTH = ${SD_FLASH_SIZE}\n    FLASH_ISR (rx)  : ORIGIN = ${ISR_START_ADDR}, LENGTH = ${ISR_SIZE}\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_BLE_CONFIG (r) : ORIGIN = ${CIRCUITPY_BLE_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_BLE_CONFIG_SIZE}\n    FLASH_NVM (r)   : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n    FLASH_FATFS (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_BOOTLOADER (rx) : ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n    FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}\n\n\n    \/* 0x2000000 - RAM:ORIGIN is reserved for Softdevice *\/\n    \/* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.\n    \/* To measure the minimum required amount of memory for given configuration, set this number\n       high enough to work and then check the mutation of the value done by sd_ble_enable. *\/\n    SPIM3_RAM (rw)  : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE}\n    RAM (xrw)       : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = ${RAM_SIZE} - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE}\n\n}\n\n\/* produce a link error if there is not this amount of RAM available *\/\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\n\/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. *\/\n_spim3_ram = ORIGIN(SPIM3_RAM);\n_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_FIRMWARE\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH_FIRMWARE\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH_FIRMWARE\n\n    \/* used by the startup to initialize data *\/\n    _sidata = .;\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* Zero-initialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Uninitialized data section\n    Data placed into this section will remain unchanged across reboots. *\/\n    .uninitialized (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _suninitialized = .; \/* define a global symbol at uninitialized start; currently unused *\/\n        *(.uninitialized)\n        *(.uninitialized*)\n\n        . = ALIGN(4);\n        _euninitialized = .; \/* define a global symbol at uninitialized end; currently unused *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\t      PROVIDE ( end = . );\n\t      PROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n    GNU linker script for NRF52840 w\/ s140 6.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = ${FLASH_SIZE} \/* entire flash *\/\n    \/* nRF SoftDevice *\/\n    FLASH_MBR (rx)  : ORIGIN = ${MBR_START_ADDR}, LENGTH = ${MBR_SIZE}\n    FLASH_SD (rx)   : ORIGIN = ${SD_FLASH_START_ADDR}, LENGTH = ${SD_FLASH_SIZE}\n    FLASH_ISR (rx)  : ORIGIN = ${ISR_START_ADDR}, LENGTH = ${ISR_SIZE}\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_BLE_CONFIG (r) : ORIGIN = ${CIRCUITPY_BLE_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_BLE_CONFIG_SIZE}\n    FLASH_NVM (r)   : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n    FLASH_FATFS (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_BOOTLOADER (rx) : ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n    FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}\n\n\n    \/* 0x2000000 - RAM:ORIGIN is reserved for Softdevice *\/\n    \/* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.\n    \/* To measure the minimum required amount of memory for given configuration, set this number\n       high enough to work and then check the mutation of the value done by sd_ble_enable. *\/\n    SPIM3_RAM (rw)  : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE}\n    RAM (xrw)       : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = ${RAM_SIZE} - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE}\n\n}\n\n\/* produce a link error if there is not this amount of RAM available *\/\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\n\/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. *\/\n_spim3_ram = ORIGIN(SPIM3_RAM);\n_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_FIRMWARE\n\n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH_FIRMWARE\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH_FIRMWARE\n    *\/\n\n    \/* used by the startup to initialize data *\/\n    _sidata = .;\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* Zero-initialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Uninitialized data section\n    Data placed into this section will remain unchanged across reboots. *\/\n    .uninitialized (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _suninitialized = .; \/* define a global symbol at uninitialized start; currently unused *\/\n        *(.uninitialized)\n        *(.uninitialized*)\n\n        . = ALIGN(4);\n        _euninitialized = .; \/* define a global symbol at uninitialized end; currently unused *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\t      PROVIDE ( end = . );\n\t      PROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b18e69c87e30859c55b1230e79c4941d92f39cc0","subject":"Put .plt input section in its own output section","message":"Put .plt input section in its own output section\n\n\nChange-Id: I77aafc010fae8d5fb6755adc8c1139b9a5ddaa40\nReviewed-on: http:\/\/rchgit01.rchland.ibm.com\/gerrit1\/103727\nTested-by: Jenkins Server <8e3f934e4c44875bc48d33da3ea13d93ba9a233f@us.ibm.com>\nTested-by: Jenkins OP Build CI <e610bd72261d3c0a48f1e8ae36832ab00774d426@us.ibm.com>\nTested-by: FSP CI Jenkins <aa9e4d9ac7cd25905e9c0dd36d4150516e73dd86@us.ibm.com>\nTested-by: Jenkins Combined Simics CI <8312af3886dfc9bb930f549023677220805b137e@us.ibm.com>\nReviewed-by: Ilya Smirnov <2c7a6ec38cfb553b896499595cca9c656159f2a4@us.ibm.com>\nReviewed-by: Nicholas E Bofferding <fb8db48116bc8a69e29dd8cdb037246f232f4af5@us.ibm.com>\nReviewed-by: William G Hoffa <7dd6aa5e78423995d9d7c7ecada5b77ee07f88cc@us.ibm.com>\n","repos":"open-power\/hostboot,open-power\/hostboot,open-power\/hostboot,open-power\/hostboot,open-power\/hostboot","old_file":"src\/module.ld","new_file":"src\/module.ld","new_contents":"\/* IBM_PROLOG_BEGIN_TAG                                                   *\/\n\/* This is an automatically generated prolog.                             *\/\n\/*                                                                        *\/\n\/* $Source: src\/module.ld $                                               *\/\n\/*                                                                        *\/\n\/* OpenPOWER HostBoot Project                                             *\/\n\/*                                                                        *\/\n\/* Contributors Listed Below - COPYRIGHT 2010,2020                        *\/\n\/* [+] Google Inc.                                                        *\/\n\/* [+] International Business Machines Corp.                              *\/\n\/*                                                                        *\/\n\/*                                                                        *\/\n\/* Licensed under the Apache License, Version 2.0 (the \"License\");        *\/\n\/* you may not use this file except in compliance with the License.       *\/\n\/* You may obtain a copy of the License at                                *\/\n\/*                                                                        *\/\n\/*     http:\/\/www.apache.org\/licenses\/LICENSE-2.0                         *\/\n\/*                                                                        *\/\n\/* Unless required by applicable law or agreed to in writing, software    *\/\n\/* distributed under the License is distributed on an \"AS IS\" BASIS,      *\/\n\/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        *\/\n\/* implied. See the License for the specific language governing           *\/\n\/* permissions and limitations under the License.                         *\/\n\/*                                                                        *\/\n\/* IBM_PROLOG_END_TAG                                                     *\/\nSECTIONS\n{\n    \/* Discard the trace strings when linking the libraries (they have\n     * been hashed prior to this) *\/\n    \/DISCARD\/ : {\n        *(*parseInfo__DISCARD*)\n    }\n\n    .text : {\n        *(.text)\n        *(.text.*)\n        *(.text.unlikely.*)\n        *(.glink)\n    }\n\n    .plt ALIGN(0x8): {\n        *(.plt)\n    }\n\n    .rodata ALIGN(0x8): {\n        __minimum_data_start_addr = ALIGN(0x1000);\n        tls_start_address = .;\n        *(.tdata)\n        *(.tdata.*)\n        *(.tbss)\n        *(.tbss.*)\n        tls_end_address = .;\n        . = ALIGN(0x8);\n        ctor_start_address = .;\n        *(.ctors)\n        *(.ctors.*)\n        ctor_end_address = .;\n        *(.rodata)\n        *(.rodata.*)\n        . = ALIGN(8);\n        *(.toc)\n        *(.opd)\n        *(.got)\n        *(.data.rel.ro.*)\n        *(.data.*traceData_codeInfo*)\n        . = __minimum_data_start_addr > . ? __minimum_data_start_addr : .;\n    }\n\n    .data ALIGN(0x8): {\n        *(.data)\n        *(.data.*)\n        *(.bss)\n        *(.bss.*)\n    }\n\n    .rela : {\n        *(.rela.*)\n    }\n\n    .dynsym : { *(.dynsym) }\n    .dynstr : { *(.dynstr) }\n    .hash : { *(.hash) }\n    .gnu.hash : { *(.gnu.hash) }\n    .eh_frame : { *(.eh_frame) }\n\n    \/DISCARD\/ : {\n        *(.dtors)\n        *(.dtors.*)\n    }\n}\n","old_contents":"\/* IBM_PROLOG_BEGIN_TAG                                                   *\/\n\/* This is an automatically generated prolog.                             *\/\n\/*                                                                        *\/\n\/* $Source: src\/module.ld $                                               *\/\n\/*                                                                        *\/\n\/* OpenPOWER HostBoot Project                                             *\/\n\/*                                                                        *\/\n\/* Contributors Listed Below - COPYRIGHT 2010,2020                        *\/\n\/* [+] Google Inc.                                                        *\/\n\/* [+] International Business Machines Corp.                              *\/\n\/*                                                                        *\/\n\/*                                                                        *\/\n\/* Licensed under the Apache License, Version 2.0 (the \"License\");        *\/\n\/* you may not use this file except in compliance with the License.       *\/\n\/* You may obtain a copy of the License at                                *\/\n\/*                                                                        *\/\n\/*     http:\/\/www.apache.org\/licenses\/LICENSE-2.0                         *\/\n\/*                                                                        *\/\n\/* Unless required by applicable law or agreed to in writing, software    *\/\n\/* distributed under the License is distributed on an \"AS IS\" BASIS,      *\/\n\/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        *\/\n\/* implied. See the License for the specific language governing           *\/\n\/* permissions and limitations under the License.                         *\/\n\/*                                                                        *\/\n\/* IBM_PROLOG_END_TAG                                                     *\/\nSECTIONS\n{\n    \/* Discard the trace strings when linking the libraries (they have\n     * been hashed prior to this) *\/\n    \/DISCARD\/ : {\n        *(*parseInfo__DISCARD*)\n    }\n\n    .text : {\n        *(.text)\n        *(.text.*)\n        *(.text.unlikely.*)\n        *(.glink)\n    }\n\n    .rodata ALIGN(0x8): {\n        __minimum_data_start_addr = ALIGN(0x1000);\n        tls_start_address = .;\n        *(.tdata)\n        *(.tdata.*)\n        *(.tbss)\n        *(.tbss.*)\n        tls_end_address = .;\n        . = ALIGN(0x8);\n        ctor_start_address = .;\n        *(.ctors)\n        *(.ctors.*)\n        ctor_end_address = .;\n        *(.rodata)\n        *(.rodata.*)\n        . = ALIGN(8);\n        *(.toc)\n        *(.opd)\n        *(.got)\n        *(.plt)\n        *(.data.rel.ro.*)\n        *(.data.*traceData_codeInfo*)\n        . = __minimum_data_start_addr > . ? __minimum_data_start_addr : .;\n    }\n\n    .data ALIGN(0x8): {\n        *(.data)\n        *(.data.*)\n        *(.bss)\n        *(.bss.*)\n    }\n\n    .rela : {\n        *(.rela.*)\n    }\n\n    .dynsym : { *(.dynsym) }\n    .dynstr : { *(.dynstr) }\n    .hash : { *(.hash) }\n    .gnu.hash : { *(.gnu.hash) }\n    .eh_frame : { *(.eh_frame) }\n\n    \/DISCARD\/ : {\n        *(.dtors)\n        *(.dtors.*)\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"79c3c28a3299853e5be61964e528416a6d5466ad","subject":"Specify ram limit to prevent overflow","message":"Specify ram limit to prevent overflow\n","repos":"charliesome\/rustboot,tempbottle\/rustboot,charliesome\/rustboot,smkell\/rustboot,tempbottle\/rustboot,YangFan789\/fanmi-os,thesam\/rOSt,RustOS-Fork-Holding-Ground\/RustOS,ryanra\/RustOS,smkell\/rustboot,thesam\/rOSt","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(start)\nOUTPUT_FORMAT(binary)\n\nMEMORY {\n    ram : org = 0x7e00, l = 12K\n}\n\nSECTIONS {\n    . = 0x7e00;\n\n    .text : {\n        runtime.o(.text)\n        *(.text)\n    } >ram\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.eh_frame)\n        *(.rel.eh_frame)\n    }\n}\n","old_contents":"ENTRY(start)\nOUTPUT_FORMAT(binary)\n\nSECTIONS {\n    . = 0x7e00;\n\n    .text : {\n        *(.text)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ec2e27b4a9efe305639c509cd183eb4c429f2a1b","subject":"ld: match fixed header length","message":"ld: match fixed header length\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x4043003c, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x80004000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x4043002c, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x80004000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4fc5d45c7819c9310988b44dbaaa03151c88895a","subject":"remove device table from linker script","message":"remove device table from linker script\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"test\/targets\/freertos.armv7m.ek-lm4f120xl\/target.ld","new_file":"test\/targets\/freertos.armv7m.ek-lm4f120xl\/target.ld","new_contents":"\/* Linker script for ARM Simulator\n *\n * Version: Sourcery CodeBench Lite 2012.03-56\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(__cs3_reset)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lcs3 -lcs3micro)\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\n  ROM   (rx) : ORIGIN = 0x01000000, LENGTH = 256K\n  SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\n\/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n *\/\nEXTERN(__cs3_reset __cs3_reset_generic_m)\nEXTERN(__cs3_start_asm __cs3_start_asm_sim)\n\/* Bring in the interrupt routines & vector *\/\nINCLUDE arm-names.inc\nEXTERN(__cs3_interrupt_vector_micro)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\n\n\/* Provide fall-back values *\/\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n  .text :\n  {\n    CREATE_OBJECT_SYMBOLS\n    __cs3_region_start_flash = .;\n    _ftext = .;\n    *(.cs3.region-head.flash)\n    ASSERT (. == __cs3_region_start_flash, \".cs3.region-head.flash not permitted\");\n    __cs3_interrupt_vector = __cs3_interrupt_vector_micro ;\n    *(.cs3.interrupt_vector)\n    \/* Make sure we pulled in an interrupt vector.  *\/\n    ASSERT (. != __cs3_interrupt_vector_micro, \"No interrupt vector\");\n\n    PROVIDE(__cs3_reset = __cs3_reset_generic_m);\n    *(.cs3.reset)\n    __cs3_start_asm_sim = DEFINED(__cs3_start_asm) ? __cs3_start_asm : __cs3_start_asm_sim;\n\n    *(.text.cs3.init)\n    *(.text .text.* .gnu.linkonce.t.*)\n    *(.plt)\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\n\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n    *(.gcc_except_table)\n  } > FLASH\n  .eh_frame_hdr : ALIGN (4)\n  {\n    KEEP (*(.eh_frame_hdr))\n    *(.eh_frame_entry .eh_frame_entry.*)\n  } > FLASH\n  .eh_frame : ALIGN (4)\n  {\n    KEEP (*(.eh_frame)) *(.eh_frame.*)\n  } > FLASH\n  \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n  PROVIDE_HIDDEN (__exidx_start = .);\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  PROVIDE_HIDDEN (__exidx_end = .);\n  .rodata : ALIGN (4)\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n    . = ALIGN(4);\n    KEEP(*(.init))\n\n    . = ALIGN(4);\n    __preinit_array_start = .;\n    KEEP (*(.preinit_array))\n    __preinit_array_end = .;\n\n    . = ALIGN(4);\n    __init_array_start = .;\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    __init_array_end = .;\n\n    . = ALIGN(4);\n    KEEP(*(.fini))\n\n    . = ALIGN(4);\n    __fini_array_start = .;\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    __fini_array_end = .;\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*crtend.o(.ctors))\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*crtend.o(.dtors))\n\n    . = ALIGN(4);\n    __cs3_regions = .;\n    LONG (0)\n    LONG (__cs3_region_init_ram)\n    LONG (__cs3_region_start_ram)\n    LONG (__cs3_region_init_size_ram)\n    LONG (__cs3_region_zero_size_ram)\n    __cs3_regions_end = .;\n    . = ALIGN (8);\n    _etext = .;\n  } > FLASH\n\n  ASSERT (!(__cs3_region_init_ram & 7), \"__cs3_region_init_ram not aligned\")\n  ASSERT (!(__cs3_region_start_ram & 7), \"__cs3_region_start_ram not aligned\")\n  ASSERT (!(__cs3_region_init_size_ram & 7), \"__cs3_region_init_size_ram not aligned\")\n  ASSERT (!(__cs3_region_zero_size_ram & 7), \"__cs3_region_zero_size_ram not aligned\")\n  .data : ALIGN (8)\n  {\n    __cs3_region_start_ram = .;\n    KEEP(*(.jcr))\n    *(.got.plt) *(.got)\n    *(.shdata)\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN (8);\n    *(.ram)\n    . = ALIGN (8);\n    _edata = .;\n  } > SRAM AT > FLASH\n  .bss : ALIGN (8)\n  {\n    *(.shbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    *(.ram.b .bss.ram)\n    . = ALIGN (8);\n    _end = .;\n    __end = .;\n  } > SRAM\n  __cs3_region_init_ram = LOADADDR(.data);\n  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;\n  __cs3_region_zero_size_ram = _end - _edata;\n  __cs3_region_size_ram = LENGTH(SRAM);\n\n  .stab 0 (NOLOAD) : { *(.stab) }\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\n  \/* DWARF debug sections.\n   * Symbols in the DWARF debugging sections are relative to\n   * the beginning of the section so we begin them at 0.\n   *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* DWARF 2.1 *\/\n  .debug_ranges   0 : { *(.debug_ranges) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n\/* checksum: 04da8015fb5e3c64b435 *\/\n","old_contents":"\/* Linker script for ARM Simulator\n *\n * Version: Sourcery CodeBench Lite 2012.03-56\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(__cs3_reset)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lcs3 -lcs3micro)\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\n  ROM   (rx) : ORIGIN = 0x01000000, LENGTH = 256K\n  SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\n\/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n *\/\nEXTERN(__cs3_reset __cs3_reset_generic_m)\nEXTERN(__cs3_start_asm __cs3_start_asm_sim)\n\/* Bring in the interrupt routines & vector *\/\nINCLUDE arm-names.inc\nEXTERN(__cs3_interrupt_vector_micro)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\n\n\/* Provide fall-back values *\/\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n  .text :\n  {\n    CREATE_OBJECT_SYMBOLS\n    __cs3_region_start_flash = .;\n    _ftext = .;\n    *(.cs3.region-head.flash)\n    ASSERT (. == __cs3_region_start_flash, \".cs3.region-head.flash not permitted\");\n    __cs3_interrupt_vector = __cs3_interrupt_vector_micro ;\n    *(.cs3.interrupt_vector)\n    \/* Make sure we pulled in an interrupt vector.  *\/\n    ASSERT (. != __cs3_interrupt_vector_micro, \"No interrupt vector\");\n\n    PROVIDE(__cs3_reset = __cs3_reset_generic_m);\n    *(.cs3.reset)\n    __cs3_start_asm_sim = DEFINED(__cs3_start_asm) ? __cs3_start_asm : __cs3_start_asm_sim;\n\n    *(.text.cs3.init)\n    *(.text .text.* .gnu.linkonce.t.*)\n    *(.plt)\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\n\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n    *(.gcc_except_table)\n  } > FLASH\n  .eh_frame_hdr : ALIGN (4)\n  {\n    KEEP (*(.eh_frame_hdr))\n    *(.eh_frame_entry .eh_frame_entry.*)\n  } > FLASH\n  .eh_frame : ALIGN (4)\n  {\n    KEEP (*(.eh_frame)) *(.eh_frame.*)\n  } > FLASH\n  \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n  PROVIDE_HIDDEN (__exidx_start = .);\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  PROVIDE_HIDDEN (__exidx_end = .);\n  .rodata : ALIGN (4)\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n    . = ALIGN(4);\n    KEEP(*(.init))\n\n    . = ALIGN(4);\n    __preinit_array_start = .;\n    KEEP (*(.preinit_array))\n    __preinit_array_end = .;\n\n    . = ALIGN(4);\n    __init_array_start = .;\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    __init_array_end = .;\n\n    . = ALIGN(4);\n    KEEP(*(.fini))\n\n    . = ALIGN(4);\n    __fini_array_start = .;\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    __fini_array_end = .;\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*crtend.o(.ctors))\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*crtend.o(.dtors))\n\n    . = ALIGN(4);\n    __cs3_regions = .;\n    LONG (0)\n    LONG (__cs3_region_init_ram)\n    LONG (__cs3_region_start_ram)\n    LONG (__cs3_region_init_size_ram)\n    LONG (__cs3_region_zero_size_ram)\n    __cs3_regions_end = .;\n    . = ALIGN (8);\n    _etext = .;\n  } > FLASH\n\n  ASSERT (!(__cs3_region_init_ram & 7), \"__cs3_region_init_ram not aligned\")\n  ASSERT (!(__cs3_region_start_ram & 7), \"__cs3_region_start_ram not aligned\")\n  ASSERT (!(__cs3_region_init_size_ram & 7), \"__cs3_region_init_size_ram not aligned\")\n  ASSERT (!(__cs3_region_zero_size_ram & 7), \"__cs3_region_zero_size_ram not aligned\")\n  .data : ALIGN (8)\n  {\n    __cs3_region_start_ram = .;\n    KEEP(*(.jcr))\n    *(.got.plt) *(.got)\n    *(.shdata)\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN (8);\n    KEEP(*( SORT (.device.table.*))) ;\n    . = ALIGN (4);\n    *(.ram)\n    . = ALIGN (8);\n    _edata = .;\n  } > SRAM AT > FLASH\n  .bss : ALIGN (8)\n  {\n    *(.shbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    *(.ram.b .bss.ram)\n    . = ALIGN (8);\n    _end = .;\n    __end = .;\n  } > SRAM\n  __cs3_region_init_ram = LOADADDR(.data);\n  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;\n  __cs3_region_zero_size_ram = _end - _edata;\n  __cs3_region_size_ram = LENGTH(SRAM);\n\n  .stab 0 (NOLOAD) : { *(.stab) }\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\n  \/* DWARF debug sections.\n   * Symbols in the DWARF debugging sections are relative to\n   * the beginning of the section so we begin them at 0.\n   *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* DWARF 2.1 *\/\n  .debug_ranges   0 : { *(.debug_ranges) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n\/* checksum: 04da8015fb5e3c64b435 *\/\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"57f5f8029377fd548833a884003dc88f27dd8f1f","subject":"linker: no need to sort by name for kernel object","message":"linker: no need to sort by name for kernel object\n\nThere is no need to sort the kernel objects by name in the linker\nscript. This is just a simple clean-up.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,ldts\/zephyr,Vudentz\/zephyr,ldts\/zephyr,galak\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,ldts\/zephyr","old_file":"include\/linker\/common-ram.ld","new_file":"include\/linker\/common-ram.ld","new_contents":"\tSECTION_DATA_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_GEN_ISR_TABLES) && defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_DATA_PROLOGUE(sw_isr_table, (OPTIONAL),)\n\t{\n\t\t*(SW_ISR_TABLE)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_DATA_PROLOGUE(initlevel_error, (OPTIONAL), )\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\tSECTION_DATA_PROLOGUE(initshell, (OPTIONAL),)\n\t{\n\t\tSHELL_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_dynamic_sections, (OPTIONAL),)\n\t{\n\t\t__log_dynamic_start = .;\n\t\tKEEP(*(SORT(.log_dynamic_*)));\n\t\t__log_dynamic_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_static_thread_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_static_thread_data_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._static_thread_data.static.*\")))\n\t\t_static_thread_data_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_DATA_PROLOGUE(_k_timer_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_timer_list_start = .;\n\t\tKEEP(*(\"._k_timer.static.*\"))\n\t\t_k_timer_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_slab_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mem_slab_list_start = .;\n\t\tKEEP(*(\"._k_mem_slab.static.*\"))\n\t\t_k_mem_slab_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mem_pool_list_start = .;\n\t\tKEEP(*(\"._k_mem_pool.static.*\"))\n\t\t_k_mem_pool_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_sem_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_sem_list_start = .;\n\t\tKEEP(*(\"._k_sem.static.*\"))\n\t\t_k_sem_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mutex_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mutex_list_start = .;\n\t\tKEEP(*(\"._k_mutex.static.*\"))\n\t\t_k_mutex_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_queue_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_queue_list_start = .;\n\t\tKEEP(*(\"._k_queue.static.*\"))\n\t\t_k_queue_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_stack_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_stack_list_start = .;\n\t\tKEEP(*(\"._k_stack.static.*\"))\n\t\t_k_stack_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_msgq_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_msgq_list_start = .;\n\t\tKEEP(*(\"._k_msgq.static.*\"))\n\t\t_k_msgq_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mbox_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mbox_list_start = .;\n\t\tKEEP(*(\"._k_mbox.static.*\"))\n\t\t_k_mbox_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_pipe_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_pipe_list_start = .;\n\t\tKEEP(*(\"._k_pipe.static.*\"))\n\t\t_k_pipe_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_start = .;\n\t\t*(\".net_if.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if.*\")))\n\t\t__net_if_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if_dev, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_dev_start = .;\n\t\t*(\".net_if_dev.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if_dev.*\")))\n\t\t__net_if_dev_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SHELL)\n\tSECTION_DATA_PROLOGUE(net_stack, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_stack_start = .;\n\t\t*(\".net_stack.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_stack*\")))\n\t\t__net_stack_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_NET_SHELL *\/\n\n\tSECTION_DATA_PROLOGUE(net_l2_data, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_l2_data_start = .;\n\t\t*(\".net_l2.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.data*\")))\n\t\t__net_l2_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(usb_data, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_data_start = .;\n\t\t*(\".usb.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.data*\")))\n\t\t__usb_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#if defined(CONFIG_USB_DEVICE_BOS)\n\tSECTION_DATA_PROLOGUE(usb_bos_desc, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_bos_desc_start = .;\n\t\t*(\".usb.bos_desc\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.bos_desc*\")))\n\t\t__usb_bos_desc_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_BOS *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n","old_contents":"\tSECTION_DATA_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_GEN_ISR_TABLES) && defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_DATA_PROLOGUE(sw_isr_table, (OPTIONAL),)\n\t{\n\t\t*(SW_ISR_TABLE)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_DATA_PROLOGUE(initlevel_error, (OPTIONAL), )\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\tSECTION_DATA_PROLOGUE(initshell, (OPTIONAL),)\n\t{\n\t\tSHELL_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_dynamic_sections, (OPTIONAL),)\n\t{\n\t\t__log_dynamic_start = .;\n\t\tKEEP(*(SORT(.log_dynamic_*)));\n\t\t__log_dynamic_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_static_thread_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_static_thread_data_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._static_thread_data.static.*\")))\n\t\t_static_thread_data_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_DATA_PROLOGUE(_k_timer_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_timer_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_timer.static.*\")))\n\t\t_k_timer_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_slab_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mem_slab_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_slab.static.*\")))\n\t\t_k_mem_slab_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mem_pool_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_pool.static.*\")))\n\t\t_k_mem_pool_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_sem_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_sem_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_sem.static.*\")))\n\t\t_k_sem_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mutex_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mutex_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mutex.static.*\")))\n\t\t_k_mutex_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_queue_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_queue_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_queue.static.*\")))\n\t\t_k_queue_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_stack_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_stack_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_stack.static.*\")))\n\t\t_k_stack_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_msgq_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_msgq_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_msgq.static.*\")))\n\t\t_k_msgq_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mbox_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mbox_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mbox.static.*\")))\n\t\t_k_mbox_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_pipe_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_pipe_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe.static.*\")))\n\t\t_k_pipe_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_start = .;\n\t\t*(\".net_if.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if.*\")))\n\t\t__net_if_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if_dev, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_dev_start = .;\n\t\t*(\".net_if_dev.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if_dev.*\")))\n\t\t__net_if_dev_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SHELL)\n\tSECTION_DATA_PROLOGUE(net_stack, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_stack_start = .;\n\t\t*(\".net_stack.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_stack*\")))\n\t\t__net_stack_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_NET_SHELL *\/\n\n\tSECTION_DATA_PROLOGUE(net_l2_data, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_l2_data_start = .;\n\t\t*(\".net_l2.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.data*\")))\n\t\t__net_l2_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(usb_data, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_data_start = .;\n\t\t*(\".usb.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.data*\")))\n\t\t__usb_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#if defined(CONFIG_USB_DEVICE_BOS)\n\tSECTION_DATA_PROLOGUE(usb_bos_desc, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_bos_desc_start = .;\n\t\t*(\".usb.bos_desc\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.bos_desc*\")))\n\t\t__usb_bos_desc_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_BOS *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6ef40322ce357190a7c8f4773ae58ef11a047432","subject":"update comment","message":"update comment\n","repos":"hirakuni45\/RL78,hirakuni45\/RL78,hirakuni45\/RL78","old_file":"G13\/R5F100LC.ld","new_file":"G13\/R5F100LC.ld","new_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/G13, 32K Flash, 2K RAM, 4K Data-Flash *\/\n\/* R5F100LCAFB:  32K (0x00000 - 0x07FFF) \/  2K (0xFF700 - 0xFFEFF) \/ 4K (0xF1000 - 0xF1FFF) *\/\n\/* stack *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007C\n\tOPT (r)   : ORIGIN = 0x000C0, LENGTH = 0x00004\n\tSEC_ID (r): ORIGIN = 0x000C4, LENGTH = 0x0000A\n\tROM (r)   : ORIGIN = 0x000D8, LENGTH = 0x07F28\n\tRAM (w)   : ORIGIN = 0xFF700, LENGTH = 0x00720\n\tSTACK (w) : ORIGIN = 0xFFE20, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n\n  .opt :\n  {\n    KEEP(*(.opt))\n  } > OPT\n\n  .sec_id :\n  {\n    KEEP(*(.sec_id))\n  } > SEC_ID\n\n  \/* CubeSuite always starts at 0xd8.  *\/\n  .csstart : {\n    *(.csstart)\n  } > ROM\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  .rodata (MAX(__romdatastart + __romdatacopysize, 0x2000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    PROVIDE (__ctor_start = .);\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    PROVIDE (__ctor_end = .);\n\n    PROVIDE (__dtor_start = .);\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    PROVIDE (__dtor_end = .);\n  } > ROM\n\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    *(PFDL_COD)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .hightext : {\n    *(.hightext)\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/G13, 32K Flash, 2K RAM, 4K Data-Flash *\/\n\/* R5F100LCAFB:  32K (0x00000 - 0x03FFF) \/  2K (0xFF700 - 0xFFEFF) \/ 4K (0xF1000 - 0xF1FFF) *\/\n\/* stack *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007C\n\tOPT (r)   : ORIGIN = 0x000C0, LENGTH = 0x00004\n\tSEC_ID (r): ORIGIN = 0x000C4, LENGTH = 0x0000A\n\tROM (r)   : ORIGIN = 0x000D8, LENGTH = 0x07F28\n\tRAM (w)   : ORIGIN = 0xFF700, LENGTH = 0x00720\n\tSTACK (w) : ORIGIN = 0xFFE20, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n\n  .opt :\n  {\n    KEEP(*(.opt))\n  } > OPT\n\n  .sec_id :\n  {\n    KEEP(*(.sec_id))\n  } > SEC_ID\n\n  \/* CubeSuite always starts at 0xd8.  *\/\n  .csstart : {\n    *(.csstart)\n  } > ROM\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  .rodata (MAX(__romdatastart + __romdatacopysize, 0x2000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    PROVIDE (__ctor_start = .);\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    PROVIDE (__ctor_end = .);\n\n    PROVIDE (__dtor_start = .);\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    PROVIDE (__dtor_end = .);\n  } > ROM\n\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    *(PFDL_COD)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .hightext : {\n    *(.hightext)\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"25e124a612d928e428fe4f98cdc87db9eabfe5bc","subject":"ld: Link memmove into IRAM (used by sprintf, etc.)","message":"ld: Link memmove into IRAM (used by sprintf, etc.)\n","repos":"ourairquality\/esp-open-rtos,DCoJA\/esp-open-rtos,alainmaes\/esp-open-rtos,kanflo\/esp-open-rtos,Zaltora\/esp-open-rtos,kanflo\/esp-open-rtos,andree182\/esp-open-rtos,andree182\/esp-open-rtos,DCoJA\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,Zaltora\/esp-open-rtos,alainmaes\/esp-open-rtos,ourairquality\/esp-open-rtos,urx\/esp-open-rtos,yesco\/esp-open-rtos,SuperHouse\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,yesco\/esp-open-rtos,Zaltora\/esp-open-rtos,sheinz\/esp-open-rtos,kanflo\/esp-open-rtos,urx\/esp-open-rtos,mr-nice\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,mr-nice\/esp-open-rtos,hawkhsieh\/esp-open-rtos,gpascualg\/esp-open-rtos,ourairquality\/esp-open-rtos,DCoJA\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,SuperHouse\/esp-open-rtos,sheinz\/esp-open-rtos,foogod\/esp-open-rtos,sheinz\/esp-open-rtos,UncleRus\/esp-open-rtos,kanflo\/esp-open-rtos,andree182\/esp-open-rtos,foogod\/esp-open-rtos,SuperHouse\/esp-open-rtos,kanflo\/esp-open-rtos,hawkhsieh\/esp-open-rtos,ourairquality\/esp-open-rtos,SuperHouse\/esp-open-rtos,alainmaes\/esp-open-rtos,sheinz\/esp-open-rtos,someburner\/esp-rtos-tests,urx\/esp-open-rtos,gpascualg\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,hawkhsieh\/esp-open-rtos,someburner\/esp-rtos-tests,UncleRus\/esp-open-rtos,Zaltora\/esp-open-rtos,UncleRus\/esp-open-rtos,hawkhsieh\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,urx\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,mr-nice\/esp-open-rtos,DCoJA\/esp-open-rtos,Zaltora\/esp-open-rtos,UncleRus\/esp-open-rtos,alainmaes\/esp-open-rtos,foogod\/esp-open-rtos,urx\/esp-open-rtos,mr-nice\/esp-open-rtos,Zaltora\/esp-open-rtos,andree182\/esp-open-rtos,ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos,kanflo\/esp-open-rtos,SuperHouse\/esp-open-rtos,someburner\/esp-rtos-tests,urx\/esp-open-rtos,UncleRus\/esp-open-rtos,someburner\/esp-rtos-tests,gpascualg\/esp-open-rtos,SuperHouse\/esp-open-rtos,UncleRus\/esp-open-rtos,chaisme\/esp8266_FreeRTOS","old_file":"ld\/eagle.app.v6.ld","new_file":"ld\/eagle.app.v6.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP .\n\n   Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one.\n*\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* FreeRTOS lock functions.\n\n   Rely on a patch to libc that produces weak linked versions of the\n   below symbols. Currently treating locking primitives like universal\n   global critical section rather than individual locks, but this seems\n   OK from the use cases in newlib.\n*\/\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\n\/* Evaluate FLASH_SIZE to calculate irom size, etc.\n*\/\n#ifndef OTA\n\n#define IROM0_START 0x40240000\n\n\/* Non-OTA sizes *\/\n#if FLASH_SIZE == 2 \/* 256kB *\/\n#define IROM0_LEN 0x3C000\n#elif FLASH_SIZE == 4 \/* 512kB *\/\n#define IROM0_LEN 0x7C000\n#elif FLASH_SIZE == 8 \/* 1MB *\/\n#define IROM0_LEN 0xFC000\n#elif FLASH_SIZE == 16 \/* 2MB *\/\n#define IROM0_LEN 0x1FC000\n#elif FLASH_SIZE == 32 \/* 4MB *\/\n#define IROM0_LEN 0x3FC000\n#else \/*FLASH_SIZE*\/\n#error \"Unknown flash size for linker script. Check the FLASH_SIZE variable in your Makefile.\"\n#endif\n\n#else \/* OTA *\/\n\n\/* IROM0 becomes an actual \"section\" of the bootloader image, so we need to leave\n   space for the bootloader (0x2000 bytes) and space for the bootloader & section\n   headers (0x10 bytes)\n*\/\n#define IROM0_START 0x40202010\n\n\/* OTA sizes *\/\n#if FLASH_SIZE < 16\n#error \"OTA support currently requires 16 or 32 megabit flash\"\n#elif FLASH_SIZE == 16 || FLASH_SIZE == 32\n\/* 1MB irom0 section regardless, minus the space for the bootloader *\/\n#define IROM0_LEN (0x100000 - 0x2010)\n#else \/*FLASH_SIZE*\/\n#error \"Unknown flash size for linker script. Check the FLASH_SIZE variable in your Makefile.\"\n#endif\n\n#endif\n\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x08000\n  irom0_0_seg :                       \torg = IROM0_START, len = IROM0_LEN\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    . = ALIGN (16);\n    *(.vecbase.text)\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* esp-open-rtos compiled source files use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *sdklib*:*(.literal .text .literal.* .text.*)\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    \/* xthal_set_intset() called from PendSV in NMI context *\/\n    *libhal.a:*set_intset.o(.literal .text .literal.* .text.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    \/* esp-open-rtos compiled code goes into IROM by default\n       (except for libgcc which is matched above.)\n    *\/\n    *(.literal .text .literal.* .text.*)\n    \/* SDK libraries expect ICACHE_FLASH_ATTR\/etc functions to be loaded explicitly as IROM *\/\n    *sdklib*:*(.irom.* .irom.*.* .irom0.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP .\n\n   Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one.\n*\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* FreeRTOS lock functions.\n\n   Rely on a patch to libc that produces weak linked versions of the\n   below symbols. Currently treating locking primitives like universal\n   global critical section rather than individual locks, but this seems\n   OK from the use cases in newlib.\n*\/\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\n\/* Evaluate FLASH_SIZE to calculate irom size, etc.\n*\/\n#ifndef OTA\n\n#define IROM0_START 0x40240000\n\n\/* Non-OTA sizes *\/\n#if FLASH_SIZE == 2 \/* 256kB *\/\n#define IROM0_LEN 0x3C000\n#elif FLASH_SIZE == 4 \/* 512kB *\/\n#define IROM0_LEN 0x7C000\n#elif FLASH_SIZE == 8 \/* 1MB *\/\n#define IROM0_LEN 0xFC000\n#elif FLASH_SIZE == 16 \/* 2MB *\/\n#define IROM0_LEN 0x1FC000\n#elif FLASH_SIZE == 32 \/* 4MB *\/\n#define IROM0_LEN 0x3FC000\n#else \/*FLASH_SIZE*\/\n#error \"Unknown flash size for linker script. Check the FLASH_SIZE variable in your Makefile.\"\n#endif\n\n#else \/* OTA *\/\n\n\/* IROM0 becomes an actual \"section\" of the bootloader image, so we need to leave\n   space for the bootloader (0x2000 bytes) and space for the bootloader & section\n   headers (0x10 bytes)\n*\/\n#define IROM0_START 0x40202010\n\n\/* OTA sizes *\/\n#if FLASH_SIZE < 16\n#error \"OTA support currently requires 16 or 32 megabit flash\"\n#elif FLASH_SIZE == 16 || FLASH_SIZE == 32\n\/* 1MB irom0 section regardless, minus the space for the bootloader *\/\n#define IROM0_LEN (0x100000 - 0x2010)\n#else \/*FLASH_SIZE*\/\n#error \"Unknown flash size for linker script. Check the FLASH_SIZE variable in your Makefile.\"\n#endif\n\n#endif\n\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x08000\n  irom0_0_seg :                       \torg = IROM0_START, len = IROM0_LEN\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    . = ALIGN (16);\n    *(.vecbase.text)\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* esp-open-rtos compiled source files use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *sdklib*:*(.literal .text .literal.* .text.*)\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    \/* xthal_set_intset() called from PendSV in NMI context *\/\n    *libhal.a:*set_intset.o(.literal .text .literal.* .text.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    \/* esp-open-rtos compiled code goes into IROM by default\n       (except for libgcc which is matched above.)\n    *\/\n    *(.literal .text .literal.* .text.*)\n    \/* SDK libraries expect ICACHE_FLASH_ATTR\/etc functions to be loaded explicitly as IROM *\/\n    *sdklib*:*(.irom.* .irom.*.* .irom0.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"72f85def0b70337479d1820276aac31f4de1bd91","subject":"Clean linker script","message":"Clean linker script\n","repos":"batitous\/klipos,batitous\/klipos,batitous\/klipos","old_file":"klipos\/hw\/mcu\/lpc13xx\/lpc13xx.ld","new_file":"klipos\/hw\/mcu\/lpc13xx\/lpc13xx.ld","new_contents":"\/*\n * generic gcc linker script for LPC13XX\n * Taken from Kamal Mostafa <kamal@whence.com>.\n *\n * License: Public Domain\n *\/\n\nMEMORY\n{\n    FLASH (rx)    : ORIGIN = 0x00000000, LENGTH = 32K \n    RAM (rwx)     : ORIGIN = 0x10000000, LENGTH = 8192 - 32\n    USBRAM (rwx)  : ORIGIN = 0x20004000, LENGTH = 0x800   \/* 2k  *\/\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.isr_vector))\n        KEEP(*(.after_vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH\n\n    .data : AT (ADDR(.text) + SIZEOF(.text))\n    {\n        KEEP(*(.stack))\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > RAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > RAM\n\n}\n","old_contents":"\/*\n * generic gcc linker script for LPC13XX\n * Taken from Kamal Mostafa <kamal@whence.com>.\n *\n * License: Public Domain\n *\/\n\nMEMORY\n{\n    FLASH (rx)    : ORIGIN = 0x00000000, LENGTH = 32K \n    RAM (rwx)     : ORIGIN = 0x10000000, LENGTH = 8192 - 32\n    USBRAM (rwx)  : ORIGIN = 0x20004000, LENGTH = 0x800   \/* 2k  *\/\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.isr_vector))\n        KEEP(*(.after_vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH\n\n    .data : AT (ADDR(.text) + SIZEOF(.text))\n    {\n        KEEP(*(.stack))\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > RAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > RAM\n\n    .usb_ram (NOLOAD): ALIGN(4)\n    {\n        *(USB_RAM)\n    } > USBRAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"d9aac46ae503d460eabd615c39c605656365602a","subject":"FIX: correct ALIGN directive in *.ld files","message":"FIX: correct ALIGN directive in *.ld files\n\nSigned-off-by: Giuseppe Monteleone <59bd0a3ff43b32849b319e645d4798d8a5d1e889@ing-monteleone.com>\n","repos":"geppo12\/YasminOS,geppo12\/YasminOS,kobrabyte\/YasminOS,kobrabyte\/YasminOS","old_file":"src\/application.ld","new_file":"src\/application.ld","new_contents":"\/*\n\t Copyright (c) 2013 Giuseppe Monteleone, All rights reserved.\n\t contact info@ing-monteleone.com\n\n\t This file is part of 'YasminOS'\n\n\t GNU Lesser General Public License Usage\n\t this file may be used under the terms of the GNU Lesser\n\t General Public License version 2.1 as published by the Free Software\n\t Foundation and appearing in the file LICENSE.LGPL included in the\n\t packaging of this file.  Please review the following information to\n\t ensure the GNU Lesser General Public License version 2.1 requirements\n\t will be met: http:\/\/www.gnu.org\/licenses\/old-licenses\/lgpl-2.1.html.\n\n\t THIS SOFTWARE IS PROVIDED BY GIUSEPPE MONTELEONE ``AS IS'' AND ANY\n\t EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n\t IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n\t PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GIUSEPPE MONTELEONE BE\n\t LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,\n\t OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\n\t OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n\t OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n\t LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n\t NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n\t SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\t You should have received a copy of the GNU General Public License\n\t along with 'YasminOS'. If not, see <http:\/\/www.gnu.org\/licenses\/>.\n\n\t EXAMPLE EXCEPTION\n\t This is and example file. Modification of this file does not constitute\n\t a derivative work of YasminOS\n*\/\nMEMORY\n{\n  CODE  (r)  : ORIGIN = 0x00000000, LENGTH = 0x1000\n  DRAM  (rw) : ORIGIN = 0x10000000, LENGTH = 0x0400\n} \n\nTOP_RAM\t\t= 0x10000400;\nSTACK_SIZE  = 0x100;\n\nSECTIONS\n{\n  .text : \n  {\n  \t_text = .;\n\tKEEP(*(.vectors))\n\tKEEP(*(.startup))\n\t\/* we put text here beacuse is small *\/\n    *(.text.*)\n\t. = 0x2FC; \n\tKEEP(*(.crp))\n\t*(.yos.kernel)\n    *(.rodata.*)\n    *(.glue_7)\n    *(.glue_7t)\n  } > CODE\n  . = ALIGN(4);\n  _etext = .;\n  \n  .trace (NOLOAD) :\n  {\n  \tKEEP(*(.trace));\n  }  \n \n  \/* .data section which is used for initialized data *\/\n  .data : AT (ADDR(.text) + SIZEOF(.text))  \n  {\n  \t_data = .;\n    *(.data.*)\n  } > DRAM\n  . = ALIGN(4);  \n  PROVIDE(_edata = .);\n  \n  .bss (NOLOAD) :\n  {\n  \t_bss = .;\n    *(.bss.*)\n  } > DRAM\n  . = ALIGN(4);\n  PROVIDE(_ebss = .);\n  \n  \n  PROVIDE(_stack = TOP_RAM - STACK_SIZE);\n  PROVIDE(_estack = TOP_RAM);  \n }","old_contents":"\/*\n\t Copyright (c) 2013 Giuseppe Monteleone, All rights reserved.\n\t contact info@ing-monteleone.com\n\n\t This file is part of 'YasminOS'\n\n\t GNU Lesser General Public License Usage\n\t this file may be used under the terms of the GNU Lesser\n\t General Public License version 2.1 as published by the Free Software\n\t Foundation and appearing in the file LICENSE.LGPL included in the\n\t packaging of this file.  Please review the following information to\n\t ensure the GNU Lesser General Public License version 2.1 requirements\n\t will be met: http:\/\/www.gnu.org\/licenses\/old-licenses\/lgpl-2.1.html.\n\n\t THIS SOFTWARE IS PROVIDED BY GIUSEPPE MONTELEONE ``AS IS'' AND ANY\n\t EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n\t IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n\t PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GIUSEPPE MONTELEONE BE\n\t LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,\n\t OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\n\t OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n\t OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n\t LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n\t NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n\t SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\t You should have received a copy of the GNU General Public License\n\t along with 'YasminOS'. If not, see <http:\/\/www.gnu.org\/licenses\/>.\n\n\t EXAMPLE EXCEPTION\n\t This is and example file. Modification of this file does not constitute\n\t a derivative work of YasminOS\n*\/\nMEMORY\n{\n  CODE  (r)  : ORIGIN = 0x00000000, LENGTH = 0x1000\n  DRAM  (rw) : ORIGIN = 0x10000000, LENGTH = 0x0400\n} \n\nTOP_RAM\t\t= 0x10000400;\nSTACK_SIZE  = 0x100;\n\nSECTIONS\n{\n  .text : \n  {\n  \t_text = .;\n\tKEEP(*(.vectors))\n\tKEEP(*(.startup))\n\t\/* we put text here beacuse is small *\/\n    *(.text.*)\n\t. = 0x2FC; \n\tKEEP(*(.crp))\n\t*(.yos.kernel)\n    *(.rodata.*)\n    *(.glue_7)\n    *(.glue_7t)\n    . = ALIGN(4);\n  } > CODE\n  _etext = .;\n  \n  .trace (NOLOAD) :\n  {\n  \tKEEP(*(.trace));\n  }  \n \n  \/* .data section which is used for initialized data *\/\n  .data : AT (ADDR(.text) + SIZEOF(.text))  \n  {\n  \t_data = .;\n    *(.data.*)\n\t. = ALIGN(4);  \n  } > DRAM\n  PROVIDE(_edata = .);\n  \n  .bss (NOLOAD) :\n  {\n  \t_bss = .;\n    *(.bss.*)\n    . = ALIGN(4);\n  } > DRAM\n  PROVIDE(_ebss = .);\n  \n  \n  PROVIDE(_stack = TOP_RAM - STACK_SIZE);\n  PROVIDE(_estack = TOP_RAM);  \n }","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"0dcfbdf6441b7ae50ed557ae41078dc326682bc8","subject":"Fix command section name for STM32 targets","message":"Fix command section name for STM32 targets\n","repos":"w5292c\/mcode,w5292c\/mcode,w5292c\/mcode","old_file":"targets\/stm32\/console-test_custom.ld","new_file":"targets\/stm32\/console-test_custom.ld","new_contents":"\/* Update the linker script with rules for custom sections *\/\nSECTIONS\n{\n  .text :\n  {\n    . = ALIGN(4);\n    __start_command_section = .;\n    *(command_section)\n    __stop_command_section = .;\n  } >FLASH\n}\n","old_contents":"\/* Update the linker script with rules for custom sections *\/\nSECTIONS\n{\n  .text :\n  {\n    . = ALIGN(4);\n    __start_command_section = .;\n    *(.command_section)\n    __stop_command_section = .;\n  } >FLASH\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"29d8c35c2521ac8dcbd2854a1833b790d8fd0abe","subject":"Wrong map calculation","message":"Wrong map calculation\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/src\/gcc_arm_flash.ld","new_file":"ARM\/src\/gcc_arm_flash.ld","new_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t\n\t\t\/* At addr zero is the stack pointer *\/\n\t\tLONG(__StackTop);\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\tFILL(0xff)\n\t\t. = 0x10;\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : \n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n   \t__data_size__ = SIZEOF(.data);\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","old_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t\n\t\t\/* At addr zero is the stack pointer *\/\n\t\tLONG(__StackTop);\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector) - SIZEOF(.Version);\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\tFILL(0xff)\n\t\t. = 0x10;\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : \n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n   \t__data_size__ = SIZEOF(.data);\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"1c193e8501d3b274d813581bee5604b76d893309","subject":"linker.ld: More readable comments","message":"linker.ld: More readable comments\n","repos":"akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix","old_file":"linker.ld","new_file":"linker.ld","new_contents":"\/************************************************************************\n *   Copyright (c) 2012 \u00c1kos Kov\u00e1cs - Akosix operating system\n *              http:\/\/akoskovacs.github.com\/Akosix\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n * \n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, \n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION\n * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n ************************************************************************\/\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    \/* The multiboot header must be \n     * in the first 8192 bytes in the image,\n     * therefore 4096 (0x1000) will be fine.\n     *\/\n    . = 0x00001000;\n    .multiboot_header :\n    {\n    __start_multiboot_header = .;\n        boot\/multiboot.o\n    __end_multiboot_header = .;\n    }\n\n    \/* This stage the paging is still \n     *  not enabled (physical = virtual).\n     *\/\n    . = 0x00100000;\n    .setup :\n    {\n    __start_setup = .;\n        boot\/boot.o\n        boot\/pgsetup.o\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    \/* The following code and data has to be mapped after \n     * the first 3GB address space, giving the kernel 1GB usable\n     * address space. \n     *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf) \n    {\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n        *(.text)\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n}\n","old_contents":"\/************************************************************************\n *   Copyright (c) 2012 \u00c1kos Kov\u00e1cs - Akosix operating system\n *              http:\/\/akoskovacs.github.com\/Akosix\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n * \n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, \n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION\n * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n ************************************************************************\/\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    \/* The multiboot header must be \n       in the first 8192 bytes in the image,\n       therefore 4096 (0x1000) will be fine *\/\n    . = 0x00001000;\n    .multiboot_header :\n    {\n    __start_multiboot_header = .;\n        boot\/multiboot.o\n    __end_multiboot_header = .;\n    }\n\n    \/* This stage the paging is still \n       not enabled (physical = virtual) *\/\n    . = 0x00100000;\n    .setup :\n    {\n    __start_setup = .;\n        boot\/boot.o\n        boot\/pgsetup.o\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    \/* The following code and data has to be mapped after \n     * the first 3GB address space, giving the kernel 1GB usable\n     * address space. \n     *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf) \n    {\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n        *(.text)\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2626ae8a53a310fe8b3796d04c80075b66cf5c00","subject":"Match Tock's userland linker script","message":"Match Tock's userland linker script\n","repos":"tock\/libtock-rs","old_file":"layout.ld","new_file":"layout.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\nSTACK_SIZE = 2048;\nAPP_HEAP_SIZE = 1024;\nKERNEL_HEAP_SIZE = 1024;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 0x0040000\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0010000\n}\n\nSECTIONS {\n    \/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n\n    \/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n    } > SRAM\n\n    \/*\n     * __NOTE__: The following symbols are used only to hint to elf2tbf how much\n     * total memory to request from the OS.\n     *\/\n    .stack :\n    {\n        . += STACK_SIZE;\n    } > SRAM\n\n    .app_heap :\n    {\n        . += APP_HEAP_SIZE;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        . += KERNEL_HEAP_SIZE;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\nSTACK_SIZE = 2048;\nAPP_HEAP_SIZE = 1024;\nKERNEL_HEAP_SIZE = 1024;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 0x0040000\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0010000\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n\n\/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n    } > SRAM\n\n\/*\n     * __NOTE__: The following symbols are used only to hint to elf2tbf how much\n     * total memory to request from the OS.\n *\/\n    .stack :\n    {\n        . += STACK_SIZE;\n    } > SRAM\n\n    .app_heap :\n    {\n        . += APP_HEAP_SIZE;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        . += KERNEL_HEAP_SIZE;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9b699a52afeb43510270c6afcf81a1e6325dac39","subject":"Fixups to network code after recent merges.","message":"Fixups to network code after recent merges.\n\nPeter's and my changes to LPC1768.ld ended up adding the same AHBSRAM0\nand AHBSRAM1 section clauses to the script twice.  I removed one copy.\n\nI also pulled Peter's define of the ETHMEM_SECTION macro up into the\nprevious nested #if so that the preprocessor wouldn't spit out a\nredefined macro warning.\n\nI verified that building the code clean before and after these changes\nstill results in the same .bin file but now without warnings and\/or\nduplicate code.\n","repos":"Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos","old_file":"TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_file":"TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Code can explicitly ask for data to be \n       placed in these higher RAM banks where\n       they will be left uninitialized. \n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    \/* Code can explicitly ask for data to be\n       placed in these higher RAM banks where\n       they will be left uninitialized.\n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n    \n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Code can explicitly ask for data to be \n       placed in these higher RAM banks where\n       they will be left uninitialized. \n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2091e32c67fad024fdd9ecf3667df20d7252df53","subject":"Properly cite linker","message":"Properly cite linker\n","repos":"MalcolmLorber\/kernel,MalcolmLorber\/kernel,MalcolmLorber\/kernel","old_file":"src\/linker.ld","new_file":"src\/linker.ld","new_contents":"\/* Linker code ripped directly from osdev wiki *\/\n\n\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 1M;\n\n\t\/* First put the multiboot header, as it is required to be put very early\n\t   early in the image or the bootloader won't recognize the file format.\n\t   Next we'll put the .text section. *\/\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t}\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","old_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 1M;\n\n\t\/* First put the multiboot header, as it is required to be put very early\n\t   early in the image or the bootloader won't recognize the file format.\n\t   Next we'll put the .text section. *\/\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t}\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"1f7e83b0e6564c8c687de0237bd97cb68c56e078","subject":"use top-level dir","message":"use top-level dir\n","repos":"bakins\/stardust,bakins\/stardust,bakins\/stardust","old_file":"config.ld","new_file":"config.ld","new_contents":"file = 'lib'\nexamples = { 'examples' }\ndir = '.'\nreadme = \"README.md\"\nformat = 'discount'\n","old_contents":"file = 'lib'\nexamples = { 'examples' }\ndir = 'docs'\nreadme = \"README.md\"\nformat = 'discount'\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1ac3e94f7a89ff974326ff95b2d74527535cd5b9","subject":"soc: intel_adsp_cavs25: Fix linker section overlap, support !COHERENCE","message":"soc: intel_adsp_cavs25: Fix linker section overlap, support !COHERENCE\n\nThe alignment on .bss was coming out wrong.  The \". = ALIGN(4096);\"\nstatement was being ignored, somewhat inexplicably.  This resulted in\nthe bss symbols being assigned corret-seeming, non-overlapping\naddresses.  But it overlapped the page-sized padding at the end of\n.data.\n\nAs it turns out, the rimage format (not the linker or Zephyr) requires\npage-sized sections to copy, and the bootloader code does that copy by\nwriting to the CACHED mapping of the memory (.bss is, like .data,\nuncached\/coherent by default).  So at runtime the CPU was running in a\ncontext where the cache was populated with \"booby trap\" data at the\nstart of .bss.  True .bss access would hit the memory uncached and see\nthe \"correct\" value, but at arbitrary times during execution lines\nwould be flushed out of L1 cache on top of it.\n\nOops.  This was found by accident, actually, as routine changes to the\nlinker script to correctly support the case where KERNEL_COHERENCE=n\n(i.e. put everything in the cached mapping and nothing in uncached)\nsuddenly hit rimage failures because of the overlap.\n\nSigned-off-by: Andy Ross <c70f9a6bf6ee0cd69c8af4ce5e6b131945769315@intel.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v25\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v25\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n#else\n#define SEGSTART_CACHED   \/**\/\n#define SEGSTART_UNCACHED \/**\/\n#define ucram ram\n#define ucram_phdr ram_phdr\n#endif\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n\n  lpsram_alt_reset_vec_seg :\n        org = LP_SRAM_ALT_RESET_VEC_BASE,\n        len = LP_SRAM_ALT_RESET_VEC_SIZE\n  lpsram_alt_reset_int_vec_seg :\n        org = LP_SRAM_ALT_RESET_INT_VEC_BASE,\n        len = LP_SRAM_ALT_RESET_INT_VEC_SIZE\n  lpsram_code_seg :\n        org = LP_SRAM_CODE_BASE,\n        len = LP_SRAM_CODE_SIZE\n  lpsram_mem :\n        org = LP_SRAM_START,\n        len = LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram_phdr PT_LOAD;\n#endif\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n\n  lpsram_mem_phdr PT_LOAD;\n  sram_alt_fw_reset_vec_phdr PT_LOAD;\n  sram_alt_fw_reset_vec_int_phdr PT_LOAD;\n  lpsram_code_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\nEXTERN(_LpsramHeader)\nEXTERN(_AltResetVector)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs25_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .AlternateResetVector.text : ALIGN(64)\n  {\n    _alternate_reset_vector_start = ABSOLUTE(.);\n    KEEP (*(*.AlternateResetVector.text))\n    . = ALIGN(16);\n    _alternate_reset_vector_start_end = ABSOLUTE(.);\n  } >lpsram_alt_reset_vec_seg AT> ram : sram_alt_fw_reset_vec_phdr\n\n  .AlternateResetL2IntVector.text : ALIGN(16)\n  {\n    _alternate_reset_l2_int_vector_start = ABSOLUTE(.);\n    KEEP (*(*.AlternateResetL2IntVector.text))\n    . = ALIGN(16);\n    _alternate_reset_l2_int_vector_end = ABSOLUTE(.);\n  } >lpsram_alt_reset_int_vec_seg AT> ram : sram_alt_fw_reset_vec_int_phdr\n\n  .LpsramCode.text : ALIGN(16)\n  {\n    _lpsram_code_start = ABSOLUTE(.);\n    KEEP (*(*.LpsramCode.text))\n    . = ALIGN(16);\n    _lpsram_code_end = ABSOLUTE(.);\n  } >lpsram_code_seg AT> ram : lpsram_code_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#ifdef CONFIG_KERNEL_COHERENCE\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n  . = SEGSTART_UNCACHED;\n#endif\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n\n#include <linker\/common-ram.ld>\n\n  .AltBootManifest SEGSTART_CACHED : ALIGN(8)\n  {\n    \/* Single entry of strorage manifest\n     * consist of 3 items. Entries array\n     * is preceded by a single dword with\n     * entries count. *\/\n    _loader_storage_manifest_start = ABSOLUTE(.);\n    \/* Number of entries*\/\n    LONG(3);\n    \/* Entry 1 *\/\n    LONG(LOADADDR(.AlternateResetVector.text));\n    LONG(ADDR(.AlternateResetVector.text));\n    LONG(SIZEOF(.AlternateResetVector.text));\n    \/* Entry 2 *\/\n    LONG(LOADADDR(.AlternateResetL2IntVector.text));\n    LONG(ADDR(.AlternateResetL2IntVector.text));\n    LONG(SIZEOF(.AlternateResetL2IntVector.text));\n\t\/* Entry 3 *\/\n\tLONG(LOADADDR(.LpsramCode.text));\n    LONG(ADDR(.LpsramCode.text));\n    LONG(SIZEOF(.LpsramCode.text));\n\t_loader_storage_manifest_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) : ALIGN(4096)\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram :ucram_phdr\n\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_CACHED;\n#endif\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n\n  lpsram_alt_reset_vec_seg :\n        org = LP_SRAM_ALT_RESET_VEC_BASE,\n        len = LP_SRAM_ALT_RESET_VEC_SIZE\n  lpsram_alt_reset_int_vec_seg :\n        org = LP_SRAM_ALT_RESET_INT_VEC_BASE,\n        len = LP_SRAM_ALT_RESET_INT_VEC_SIZE\n  lpsram_code_seg :\n        org = LP_SRAM_CODE_BASE,\n        len = LP_SRAM_CODE_SIZE\n  lpsram_mem :\n        org = LP_SRAM_START,\n        len = LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n\n  lpsram_mem_phdr PT_LOAD;\n  sram_alt_fw_reset_vec_phdr PT_LOAD;\n  sram_alt_fw_reset_vec_int_phdr PT_LOAD;\n  lpsram_code_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\nEXTERN(_LpsramHeader)\nEXTERN(_AltResetVector)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs25_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .AlternateResetVector.text : ALIGN(64)\n  {\n    _alternate_reset_vector_start = ABSOLUTE(.);\n    KEEP (*(*.AlternateResetVector.text))\n    . = ALIGN(16);\n    _alternate_reset_vector_start_end = ABSOLUTE(.);\n  } >lpsram_alt_reset_vec_seg AT> ram : sram_alt_fw_reset_vec_phdr\n\n  .AlternateResetL2IntVector.text : ALIGN(16)\n  {\n    _alternate_reset_l2_int_vector_start = ABSOLUTE(.);\n    KEEP (*(*.AlternateResetL2IntVector.text))\n    . = ALIGN(16);\n    _alternate_reset_l2_int_vector_end = ABSOLUTE(.);\n  } >lpsram_alt_reset_int_vec_seg AT> ram : sram_alt_fw_reset_vec_int_phdr\n\n  .LpsramCode.text : ALIGN(16)\n  {\n    _lpsram_code_start = ABSOLUTE(.);\n    KEEP (*(*.LpsramCode.text))\n    . = ALIGN(16);\n    _lpsram_code_end = ABSOLUTE(.);\n  } >lpsram_code_seg AT> ram : lpsram_code_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n  . = SEGSTART_UNCACHED;\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n\n#include <linker\/common-ram.ld>\n\n  .AltBootManifest SEGSTART_CACHED : ALIGN(8)\n  {\n    \/* Single entry of strorage manifest\n     * consist of 3 items. Entries array\n     * is preceded by a single dword with\n     * entries count. *\/\n    _loader_storage_manifest_start = ABSOLUTE(.);\n    \/* Number of entries*\/\n    LONG(3);\n    \/* Entry 1 *\/\n    LONG(LOADADDR(.AlternateResetVector.text));\n    LONG(ADDR(.AlternateResetVector.text));\n    LONG(SIZEOF(.AlternateResetVector.text));\n    \/* Entry 2 *\/\n    LONG(LOADADDR(.AlternateResetL2IntVector.text));\n    LONG(ADDR(.AlternateResetL2IntVector.text));\n    LONG(SIZEOF(.AlternateResetL2IntVector.text));\n\t\/* Entry 3 *\/\n\tLONG(LOADADDR(.LpsramCode.text));\n    LONG(ADDR(.LpsramCode.text));\n    LONG(SIZEOF(.LpsramCode.text));\n\t_loader_storage_manifest_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n  . = SEGSTART_UNCACHED;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"79d9e2c224b0c2043ceffbaa6bf8d465ad1222d0","subject":"[sw] Remove outdated comment from linker script","message":"[sw] Remove outdated comment from linker script\n\nThat comment seems to be carried over from PULP and doesn't make much\nsense any more.\n\nSigned-off-by: Philipp Wagner <5a4b10454c30419e54a1570be358a516ff84bb63@lowrisc.org>\n","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan","old_file":"sw\/device\/exts\/common\/link.ld","new_file":"sw\/device\/exts\/common\/link.ld","new_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\nOUTPUT_ARCH(riscv)\n\nGROUP( -lgcc )\n\nSEARCH_DIR(.)\n__DYNAMIC  =  0;\n\nMEMORY {\n    flash (rx)  : ORIGIN = 0x20000000, LENGTH = 0x100000\n    ram   (!rx) : ORIGIN = 0x10000000, LENGTH = 0x10000\n}\n\n_stack_start = ORIGIN(ram) + LENGTH(ram);\n\nSECTIONS {\n    .crt : {\n        *(.crt)\n    } > flash\n\n    \/* the 256 byte alignment is required by the machine trap vector table *\/\n    .vectors : {\n        . = ALIGN(0x100);\n        _svectors = .;\n        *(.vectors)\n        _evectors = .;\n    } > flash\n\n    .text : {\n        . = ALIGN(0x100);\n        _stext = .;\n        *(.text.startup)\n        *(.text)\n        *(.text.unlikely)\n        _etext  =  .;\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        *(.ctors)\n        LONG(0)\n        __CTOR_END__ = .;\n        __DTOR_LIST__ = .;\n        LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\n        *(.dtors)\n        LONG(0)\n        __DTOR_END__ = .;\n        *(.lit)\n        *(.shdata)\n        _endtext = .;\n    }  > flash\n\n    .rodata : {\n        . = ALIGN(4);\n        *(.rodata);\n        *(.rodata.*)\n    } > flash\n\n    .shbss : {\n        . = ALIGN(4);\n        *(.shbss)\n    } > flash\n\n    \/* idata stores the static variable data that will be loaded in ram below *\/\n    .idata : {\n        . = ALIGN(4);\n        _idata = .;\n    } > flash\n\n    \/* Static variable LMA at end of program\n       VMA at start of RAM.  Stack is at end of RAM *\/\n    .data 0x10000000 : AT ( _idata ) {\n        . = ALIGN(4);\n        _sdata  =  .; \/* start of data *\/\n        *(.data);\n        *(.data.*)\n        *(.sdata);\n        _edata  =  .; \/* end of data *\/\n    } > ram\n\n    .bss : {\n        . = ALIGN(4);\n        _bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(.sbss)\n        *(.sbss.*)\n        *(COMMON)\n        _bss_end = .;\n    } > ram\n\n    .stab  0 (NOLOAD) : {\n        [ .stab ]\n    }\n\n    .stabstr  0 (NOLOAD) : {\n        [ .stabstr ]\n    }\n\n    \/* Discard the remaining sections *\/\n    \/DISCARD\/ : { *(*) }\n}\n\nENTRY(main)\n","old_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\nOUTPUT_ARCH(riscv)\n\nGROUP( -lgcc )\n\nSEARCH_DIR(.)\n__DYNAMIC  =  0;\n\nMEMORY {\n    flash (rx)  : ORIGIN = 0x20000000, LENGTH = 0x100000\n    ram   (!rx) : ORIGIN = 0x10000000, LENGTH = 0x10000\n}\n\n_stack_start = ORIGIN(ram) + LENGTH(ram);\n\n\/* We have to align each sector to word boundaries as our current s19->slm\n * conversion scripts are not able to handle non-word aligned sections. *\/\n\n\nSECTIONS {\n    .crt : {\n        *(.crt)\n    } > flash\n\n    \/* the 256 byte alignment is required by the machine trap vector table *\/\n    .vectors : {\n        . = ALIGN(0x100);\n        _svectors = .;\n        *(.vectors)\n        _evectors = .;\n    } > flash\n\n    .text : {\n        . = ALIGN(0x100);\n        _stext = .;\n        *(.text.startup)\n        *(.text)\n        *(.text.unlikely)\n        _etext  =  .;\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        *(.ctors)\n        LONG(0)\n        __CTOR_END__ = .;\n        __DTOR_LIST__ = .;\n        LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\n        *(.dtors)\n        LONG(0)\n        __DTOR_END__ = .;\n        *(.lit)\n        *(.shdata)\n        _endtext = .;\n    }  > flash\n\n    .rodata : {\n        . = ALIGN(4);\n        *(.rodata);\n        *(.rodata.*)\n    } > flash\n\n    .shbss : {\n        . = ALIGN(4);\n        *(.shbss)\n    } > flash\n\n    \/* idata stores the static variable data that will be loaded in ram below *\/\n    .idata : {\n        . = ALIGN(4);\n        _idata = .;\n    } > flash\n\n    \/* Static variable LMA at end of program\n       VMA at start of RAM.  Stack is at end of RAM *\/\n    .data 0x10000000 : AT ( _idata ) {\n        . = ALIGN(4);\n        _sdata  =  .; \/* start of data *\/\n        *(.data);\n        *(.data.*)\n        *(.sdata);\n        _edata  =  .; \/* end of data *\/\n    } > ram\n\n    .bss : {\n        . = ALIGN(4);\n        _bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(.sbss)\n        *(.sbss.*)\n        *(COMMON)\n        _bss_end = .;\n    } > ram\n\n    .stab  0 (NOLOAD) : {\n        [ .stab ]\n    }\n\n    .stabstr  0 (NOLOAD) : {\n        [ .stabstr ]\n    }\n\n    \/* Discard the remaining sections *\/\n    \/DISCARD\/ : { *(*) }\n}\n\nENTRY(main)\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7b56b08392e72deb8c3d555dcb6521acd1cff94e","subject":"Working box syntax! But the binary is now too big to be fully loaded by loader.asm","message":"Working box syntax! But the binary is now too big to be fully loaded by loader.asm\n","repos":"thesam\/rOSt,thesam\/rOSt","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(main)\nOUTPUT_FORMAT(binary)\n\nMEMORY {\n    ram : org = 0x7e00, l = 200K\n}\n\nSECTIONS {\n    . = 0x7e00;\n\n    .main : {\n        main.o(.text.main)\n    } >ram\n\n    .lib : {\n        lib.o(*)\n        libcore.rlib(.text)\n    } >ram\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.eh_frame)\n        *(.rel.eh_frame)\n    }\n}\n","old_contents":"ENTRY(main)\nOUTPUT_FORMAT(binary)\n\nMEMORY {\n    ram : org = 0x7e00, l = 12K\n}\n\nSECTIONS {\n    . = 0x7e00;\n\n    .main : {\n        main.o(.text.main)\n    } >ram\n\n    .lib : {\n        lib.o(*)\n        libcore.rlib(.text)\n    } >ram\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.eh_frame)\n        *(.rel.eh_frame)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4a33677c9720bd7f2ce5b0f816cc4c87220570ac","subject":"esp8266\/esp8266.ld: Move modmachinewdt to FlashROM.","message":"esp8266\/esp8266.ld: Move modmachinewdt to FlashROM.\n","repos":"pramasoul\/micropython,pozetroninc\/micropython,cwyark\/micropython,pfalcon\/micropython,dmazzella\/micropython,jmarcelino\/pycom-micropython,blazewicz\/micropython,lowRISC\/micropython,trezor\/micropython,adafruit\/micropython,selste\/micropython,adafruit\/circuitpython,TDAbboud\/micropython,tuc-osg\/micropython,adafruit\/circuitpython,MrSurly\/micropython,MrSurly\/micropython-esp32,Timmenem\/micropython,infinnovation\/micropython,alex-robbins\/micropython,Peetz0r\/micropython-esp32,swegener\/micropython,adafruit\/circuitpython,mhoffma\/micropython,blazewicz\/micropython,hosaka\/micropython,cwyark\/micropython,toolmacher\/micropython,ryannathans\/micropython,PappaPeppar\/micropython,pramasoul\/micropython,puuu\/micropython,Peetz0r\/micropython-esp32,hiway\/micropython,mhoffma\/micropython,bvernoux\/micropython,hosaka\/micropython,trezor\/micropython,oopy\/micropython,MrSurly\/micropython-esp32,bvernoux\/micropython,puuu\/micropython,trezor\/micropython,toolmacher\/micropython,MrSurly\/micropython,MrSurly\/micropython-esp32,dmazzella\/micropython,hosaka\/micropython,kerneltask\/micropython,MrSurly\/micropython,HenrikSolver\/micropython,PappaPeppar\/micropython,SHA2017-badge\/micropython-esp32,tobbad\/micropython,infinnovation\/micropython,Timmenem\/micropython,adafruit\/micropython,dxxb\/micropython,chrisdearman\/micropython,alex-march\/micropython,adafruit\/circuitpython,MrSurly\/micropython,pozetroninc\/micropython,ryannathans\/micropython,hosaka\/micropython,kerneltask\/micropython,MrSurly\/micropython-esp32,AriZuu\/micropython,AriZuu\/micropython,deshipu\/micropython,TDAbboud\/micropython,pramasoul\/micropython,alex-march\/micropython,selste\/micropython,toolmacher\/micropython,tuc-osg\/micropython,infinnovation\/micropython,lowRISC\/micropython,TDAbboud\/micropython,chrisdearman\/micropython,adafruit\/micropython,lowRISC\/micropython,chrisdearman\/micropython,tobbad\/micropython,tralamazza\/micropython,TDAbboud\/micropython,tobbad\/micropython,dxxb\/micropython,infinnovation\/micropython,pramasoul\/micropython,henriknelson\/micropython,ryannathans\/micropython,matthewelse\/micropython,kerneltask\/micropython,toolmacher\/micropython,MrSurly\/micropython,jmarcelino\/pycom-micropython,trezor\/micropython,kerneltask\/micropython,adafruit\/micropython,torwag\/micropython,tuc-osg\/micropython,deshipu\/micropython,SHA2017-badge\/micropython-esp32,lowRISC\/micropython,tobbad\/micropython,puuu\/micropython,tralamazza\/micropython,micropython\/micropython-esp32,puuu\/micropython,MrSurly\/micropython-esp32,alex-robbins\/micropython,trezor\/micropython,blazewicz\/micropython,torwag\/micropython,hiway\/micropython,pfalcon\/micropython,alex-robbins\/micropython,alex-march\/micropython,henriknelson\/micropython,adafruit\/circuitpython,pramasoul\/micropython,jmarcelino\/pycom-micropython,oopy\/micropython,hiway\/micropython,bvernoux\/micropython,AriZuu\/micropython,mhoffma\/micropython,micropython\/micropython-esp32,alex-march\/micropython,swegener\/micropython,blazewicz\/micropython,HenrikSolver\/micropython,turbinenreiter\/micropython,turbinenreiter\/micropython,dmazzella\/micropython,swegener\/micropython,PappaPeppar\/micropython,alex-robbins\/micropython,henriknelson\/micropython,AriZuu\/micropython,dxxb\/micropython,torwag\/micropython,torwag\/micropython,jmarcelino\/pycom-micropython,turbinenreiter\/micropython,bvernoux\/micropython,deshipu\/micropython,mhoffma\/micropython,ryannathans\/micropython,HenrikSolver\/micropython,hiway\/micropython,dmazzella\/micropython,turbinenreiter\/micropython,oopy\/micropython,Timmenem\/micropython,HenrikSolver\/micropython,HenrikSolver\/micropython,jmarcelino\/pycom-micropython,TDAbboud\/micropython,AriZuu\/micropython,bvernoux\/micropython,pozetroninc\/micropython,SHA2017-badge\/micropython-esp32,blazewicz\/micropython,mhoffma\/micropython,micropython\/micropython-esp32,selste\/micropython,adafruit\/circuitpython,tralamazza\/micropython,henriknelson\/micropython,matthewelse\/micropython,matthewelse\/micropython,cwyark\/micropython,matthewelse\/micropython,hosaka\/micropython,kerneltask\/micropython,pfalcon\/micropython,Peetz0r\/micropython-esp32,alex-march\/micropython,pozetroninc\/micropython,puuu\/micropython,tobbad\/micropython,tuc-osg\/micropython,alex-robbins\/micropython,pfalcon\/micropython,PappaPeppar\/micropython,tuc-osg\/micropython,selste\/micropython,hiway\/micropython,pfalcon\/micropython,Timmenem\/micropython,chrisdearman\/micropython,matthewelse\/micropython,chrisdearman\/micropython,PappaPeppar\/micropython,henriknelson\/micropython,Timmenem\/micropython,dxxb\/micropython,micropython\/micropython-esp32,SHA2017-badge\/micropython-esp32,cwyark\/micropython,Peetz0r\/micropython-esp32,selste\/micropython,oopy\/micropython,tralamazza\/micropython,Peetz0r\/micropython-esp32,torwag\/micropython,swegener\/micropython,deshipu\/micropython,deshipu\/micropython,adafruit\/micropython,SHA2017-badge\/micropython-esp32,lowRISC\/micropython,oopy\/micropython,dxxb\/micropython,turbinenreiter\/micropython,pozetroninc\/micropython,micropython\/micropython-esp32,matthewelse\/micropython,infinnovation\/micropython,cwyark\/micropython,swegener\/micropython,ryannathans\/micropython,toolmacher\/micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40209000, len = 0x87000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybuart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachinespi.o(.literal*, .text*)\n        *modmachinewdt.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modpybhspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40209000, len = 0x87000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybuart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachinespi.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modpybhspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"085c298e73c052b7a96e4b7ab92b3180217358ae","subject":"Update linker script for Freescale Flash security","message":"Update linker script for Freescale Flash security\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/src\/gcc_arm_flash.ld","new_file":"ARM\/src\/gcc_arm_flash.ld","new_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t\n\t\t\/* At addr zero is the stack pointer *\/\n\t\tLONG(__StackTop);\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xfffffffe);\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : \n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n   \t__data_size__ = SIZEOF(.data);\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","old_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t\n\t\t\/* At addr zero is the stack pointer *\/\n\t\tLONG(__StackTop);\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\tFILL(0xff)\n\t\t. = 0x10;\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : \n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n   \t__data_size__ = SIZEOF(.data);\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"2975f406790350c73d0877efaa173fc2cad94883","subject":"Changed section name from FLASH to ROM","message":"Changed section name from FLASH to ROM\n\nSigned-off-by: Maciej Kurc <572803cc6e8d7bb35033942e4b03254951a2e0d6@antmicro.com>\n","repos":"SymbiFlow\/symbiflow-arch-defs,SymbiFlow\/symbiflow-arch-defs","old_file":"soc_tests\/picosoc\/firmware\/sections.lds","new_file":"soc_tests\/picosoc\/firmware\/sections.lds","new_contents":"MEMORY\n{\n    ROM (rx)        : ORIGIN = 0x00100000, LENGTH = 0x100000 \/* Mockup flash 1MB *\/\n    RAM (xrw)       : ORIGIN = 0x00000000, LENGTH = 0x000400 \/* 1 KB *\/\n}\n\nSECTIONS {\n    \/* The program code and other data goes into ROM *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        *(.srodata)        \/* .rodata sections (constants, strings, etc.) *\/\n        *(.srodata*)       \/* .rodata* sections (constants, strings, etc.) *\/\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >ROM\n\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the ROM (inidata).\n    It is one task of the startup to copy the initial values from ROM to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        . = ALIGN(4);\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n        *(.sdata)           \/* .sdata sections *\/\n        *(.sdata*)          \/* .sdata* sections *\/\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n    } >RAM\n}\n","old_contents":"MEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00100000, LENGTH = 0x100000 \/* Mockup flash 1MB *\/\n    RAM (xrw)       : ORIGIN = 0x00000000, LENGTH = 0x000400 \/* 1 KB *\/\n}\n\nSECTIONS {\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        *(.srodata)        \/* .rodata sections (constants, strings, etc.) *\/\n        *(.srodata*)       \/* .rodata* sections (constants, strings, etc.) *\/\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH\n\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        . = ALIGN(4);\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n        *(.sdata)           \/* .sdata sections *\/\n        *(.sdata*)          \/* .sdata* sections *\/\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n    } >RAM\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"ce32e249a5e88deffef913c6bf888f57700753f7","subject":"recovered stm version of dro linker file","message":"recovered stm version of dro linker file\n","repos":"980f\/dro,980f\/dro,980f\/dro,980f\/dro","old_file":"dro.ld","new_file":"dro.ld","new_contents":"","old_contents":"\/* first include your processor's MEMORY layout stuff.*\/\nINCLUDE cortexm\/stm32\/f103rb.ld\n\n\/* then the generic \"flash only\" stuff, which presently is tightly tied into cstartup.cpp *\/\nINCLUDE cortexm\/cortexm.ld\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0becb666ef7c315f5ae39a73de9e273a21891e5c","subject":"linker: Add data sections to quemu_x86_tiny","message":"linker: Add data sections to quemu_x86_tiny\n\nThe data sections generated by zephyr_linker_sources(DATA_SECTIONS ...)\nwas missing for the qemu_x86_tiny.\n\nSigned-off-by: Yuval Peress <50dc11c009bd4d7e9d9d15a383c1743ce5ee82ef@google.com>\n","repos":"galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr","old_file":"boards\/x86\/qemu_x86\/qemu_x86_tiny.ld","new_file":"boards\/x86\/qemu_x86\/qemu_x86_tiny.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n * Copyright (c) 2021 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <zephyr\/devicetree.h>\n#include <offsets.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n#include <zephyr\/sys\/util.h>\n#include <zephyr\/sys\/mem_manage.h>\n\n\n\/* Bounds of physical RAM from DTS *\/\n#define PHYS_RAM_ADDR\t\t\tDT_REG_ADDR(DT_CHOSEN(zephyr_sram))\n#define PHYS_RAM_SIZE\t\t\tDT_REG_SIZE(DT_CHOSEN(zephyr_sram))\n\n\/* Bounds of flash from DTS *\/\n#define FLASH_ROM_ADDR\t\t\tDT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define FLASH_ROM_SIZE\t\t\tDT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n\n\/* Virtual base address for the kernel; with CONFIG_MMU this is not necessarily\n * the same as its physical location, although an identity mapping for RAM\n * is still supported by setting CONFIG_KERNEL_VM_BASE=CONFIG_SRAM_BASE_ADDRESS.\n *\/\n#ifdef Z_VM_KERNEL\n\n#define KERNEL_BASE_ADDR \\\n\t(CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET)\n\n#define KERNEL_RAM_SIZE \\\n\t(CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET)\n\n#define PHYS_RAM_AVAIL \\\n\t(PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n\n#else\n\n#define KERNEL_BASE_ADDR\t\t(PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n#define KERNEL_RAM_SIZE\t\t\t(PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n\n#endif\n\n\/* \"kernel RAM\" for linker VMA allocations starts at the offset *\/\n\n\/* Physical RAM location where the kernel image is loaded *\/\n#define PHYS_LOAD_ADDR\t\t\t(PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n\n#ifdef CONFIG_USERSPACE\n#define SMEM_PARTITION_ALIGN(size)\tMMU_PAGE_ALIGN_PERM\n#define APP_SHARED_ALIGN\t\tMMU_PAGE_ALIGN_PERM\n#endif\n\nMEMORY\n    {\n#if defined(Z_VM_KERNEL)\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_AVAIL\n#endif\n    RAM (wx)        : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n    FLASH (rw)      : ORIGIN = FLASH_ROM_ADDR, LENGTH = FLASH_ROM_SIZE\n#endif\n\n    \/*\n     * On 32-bit x86, fake memory area for build-time IDT generation data.\n     *\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 0xFFFF1000, LENGTH = 2K\n    }\n\n#if defined(Z_VM_KERNEL)\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_MMU\n\t#define MMU_PAGE_ALIGN\t\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n\n#undef SECTION_PROLOGUE\n#define SECTION_PROLOGUE(name, options, align) \\\n        name options : ALIGN_WITH_INPUT align\n\n#undef SECTION_DATA_PROLOGUE\n#define SECTION_DATA_PROLOGUE(name, options, align) \\\n        name options : ALIGN_WITH_INPUT align\n\n#undef GROUP_ROM_LINK_IN\n#define GROUP_ROM_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#undef GROUP_DATA_LINK_IN\n#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#undef GROUP_NOLOAD_LINK_IN\n#define GROUP_NOLOAD_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#endif\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN_PERM\tMMU_PAGE_ALIGN\n#else\n\t#define MMU_PAGE_ALIGN_PERM\n#endif\n\n\/* For all source files under arch\/x86\/. *\/\n#define LIB_ARCH_X86_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libarch__x86__core.a.a:(.##lsect)\t\t\t\t\\\n\t*libarch__x86__core.a:(.##lsect##.*)\n\n#ifdef CONFIG_MINIMAL_LIBC\n\/* For all source files under lib\/libc\/minimal\/.\n * These files includes, for example, math and string functions.\n *\/\n#define LIB_C_IN_SECT(lsect)\t\t\t\t\t\t\\\n\t*liblib__libc__minimal.a:(.##lsect)\t\t\t\t\\\n\t*liblib__libc__minimal.a:(.##lsect##.*)\n\n#endif \/* CONFIG_MINIMAL_LIBC *\/\n\n#ifdef CONFIG_NEWLIB_LIBC\n\/* For Newlib libc-hook.c. *\/\n#define LIB_C_IN_SECT(lsect)\t\t\t\t\t\t\\\n\t*liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect)\t\t\\\n\t*liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect##.*)\n\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n\/*\n * For drivers that are usually used (e.g. serial)\n *\/\n#define LIB_DRIVERS_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libdrivers__serial.a:(.##lsect)\t\t\t\t\\\n\t*libdrivers__serial.a:(.##lsect##.*)\t\t\t\t\\\n\t*hpet.c.obj(.##lsect)\t\t\t\t\t\t\\\n\t*hpet.c.obj(.##lsect##.*)\t\t\t\t\t\\\n\t*intc_ioapic.c.obj(.##lsect)\t\t\t\t\t\\\n\t*intc_ioapic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*intc_loapic.c.obj(.##lsect)\t\t\t\t\t\\\n\t*intc_loapic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*intc_system_apic.c.obj(.##lsect)\t\t\t\t\\\n\t*intc_system_apic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*rand32_timer.c.obj(.##lsect)\t\t\t\t\t\\\n\t*rand32_timer.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*uart_console.c.obj(.##lsect)\t\t\t\t\t\\\n\t*uart_console.c.obj(.##lsect##.*)\n\n\/* For all source files under kernel\/. and kernel related files *\/\n#define LIB_KERNEL_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libkernel.a:(.##lsect)\t\t\t\t\t\t\\\n\t*libkernel.a:(.##lsect##.*)\t\t\t\t\t\\\n\t*libsubsys__demand_paging__*.a:(.##lsect)\t\t\t\\\n\t*libsubsys__demand_paging__*.a:(.##lsect##.*)\n\n\/* For particular file packaged in libzephyr.a. *\/\n#define LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, objfile)\t\t\t\\\n\t*libzephyr.a:objfile.c.obj(.##lsect)\t\t\t\t\\\n\t*libzephyr.a:objfile.c.obj(.##lsect##.*)\n\n\/* For source files under lib\/os\/ with commonly used functions. *\/\n#define LIB_ZEPHYR_IN_SECT(lsect)\t\t\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, assert)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, bitarray)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_complete)\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_nano)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, configs)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap-validate)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, mutex)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, notify)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, printk)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sem)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, stdout_console)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sys_clock_init)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, rb)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, thread_entry)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, work_q)\n\n\/*\n * Catch all for all internal\/external kernel functions\n * as they are usually defined as \"static inline\" where\n * they are attached to the source which uses them.\n * Hence the need to specify them here so they can be pinned.\n *\/\n#define ZEPHYR_KERNEL_FUNCS_IN_SECT\t\t\t\t\t\\\n\t*(.text.atomic_*)\t\t\t\t\t\t\\\n\t*(.text.k_*)\t\t\t\t\t\t\t\\\n\t*(.text.sys_*_bit)\t\t\t\t\t\t\\\n\t*(.text.sys_bitfield_*)\t\t\t\t\t\t\\\n\t*(.text.sys_clock_hw_cycles_per_sec)\t\t\t\t\\\n\t*(.text.sys_cache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_dcache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_icache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_mutex_*)\t\t\t\t\t\t\\\n\t*(.text.sys_notify_*)\t\t\t\t\t\t\\\n\t*(.text.sys_dlist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_slist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_sflist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_sfnode_*)\t\t\t\t\t\t\\\n\t*(.text.sys_io_*)\t\t\t\t\t\t\\\n\t*(.text.sys_in*)\t\t\t\t\t\t\\\n\t*(.text.sys_out*)\t\t\t\t\t\t\\\n\t*(.text.sys_read*)\t\t\t\t\t\t\\\n\t*(.text.sys_write*)\t\t\t\t\t\t\\\n\t*(.text.sys_get_be*)\t\t\t\t\t\t\\\n\t*(.text.sys_get_le*)\t\t\t\t\t\t\\\n\t*(.text.sys_put_be*)\t\t\t\t\t\t\\\n\t*(.text.sys_put_le*)\t\t\t\t\t\t\\\n\t*(.text.sys_mem_swap)\t\t\t\t\t\t\\\n\t*(.text.sys_memcpy_swap)\t\t\t\t\t\\\n\t*(.text.z_*)\n\n\/* For logging subsys *\/\n#define LIB_SUBSYS_LOGGING_IN_SECT(lsect)\t\t\t\t\\\n\t*log_*.c.obj(.##lsect)\t\t\t\t\t\t\\\n\t*log_*.c.obj(.##lsect.*)\t\t\t\t\t\\\n\t*mpsc_pbuf.c.obj(.##lsect)\t\t\t\t\t\\\n\t*mpsc_pbuf.c.obj(.##lsect.*)\n\nepoint = Z_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY);\nENTRY(epoint)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n#ifdef CONFIG_LINKER_USE_BOOT_SECTION\n\n\tSECTION_PROLOGUE(boot.text,,)\n\t{\n#include <snippets-rom-start.ld>\n\n\t\tMMU_PAGE_ALIGN\n\t\tlnkr_boot_start = .;\n\t\tz_mapped_start = .;\n\n\t\tlnkr_boot_text_start = .;\n\n\t\tKEEP(*(.boot_text.__start))\n\t\t*(.boot_text)\n\t\t*(.boot_text.*)\n\n\t\t*(.text.k_mem_paging_backing_store_init)\n\t\t*(.text.k_mem_paging_eviction_init)\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_text_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.rodata,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_rodata_start = .;\n\n\t\t*(.boot_rodata)\n\t\t*(.boot_rodata.*)\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_rodata_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.data,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_data_start = .;\n\n\t\t*(.boot_data)\n\t\t*(.boot_data.*)\n\n\t\tlnkr_boot_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.bss, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_bss_start = .;\n\n\t\t*(.boot_bss)\n\t\t*(.boot_bss.*)\n\n\t\tlnkr_boot_bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.noinit, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_noinit_start = .;\n\n\t\t*(.boot_noinit)\n\t\t*(.boot_noinit.*)\n\n\t\tlnkr_boot_noinit_end = .;\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_boot_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tlnkr_boot_text_size = lnkr_boot_text_end - lnkr_boot_text_start;\n\tlnkr_boot_rodata_size = lnkr_boot_rodata_end - lnkr_boot_rodata_start;\n\tlnkr_boot_data_size = lnkr_boot_data_end - lnkr_boot_data_start;\n\tlnkr_boot_bss_size = lnkr_boot_bss_end - lnkr_boot_bss_start;\n\tlnkr_boot_noinit_size = lnkr_boot_noinit_end - lnkr_boot_noinit_start;\n\n#endif \/* CONFIG_LINKER_USE_BOOT_SECTION *\/\n\n#ifdef CONFIG_LINKER_USE_PINNED_SECTION\n\n\tSECTION_PROLOGUE(pinned.text,,)\n\t{\n#ifndef CONFIG_LINKER_USE_BOOT_SECTION\n#include <snippets-rom-start.ld>\n#endif\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_pinned_start = .;\n\n#ifndef CONFIG_LINKER_USE_BOOT_SECTION\n\t\tz_mapped_start = .;\n#endif\n\n\t\tlnkr_pinned_text_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(text)\n\t\tLIB_ARCH_X86_IN_SECT(text)\n\t\t*(.text._OffsetAbsSyms)\n\n\t\t*(.pinned_text)\n\t\t*(.pinned_text.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(text)\n\t\tLIB_C_IN_SECT(text)\n\t\tLIB_DRIVERS_IN_SECT(text)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(text)\n\n\t\t*_divdi3.o(.text)\n\t\t*_udivdi3.o(.text)\n\t\t*_udivmoddi4.o(.text)\n\t\t*_umoddi3.o(.text)\n\t\t*_popcountsi2.o(.text)\n\n\t\t*(.gnu.linkonce.t.exc_*)\n\n\t\t*(.text.*.constprop)\n\t\t*(.text.*.constprop.*)\n\n#ifdef CONFIG_NEWLIB_LIBC\n\t\t*libc.a:(.text)\n\t\t*libc.a:(.text.*)\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n\t\tZEPHYR_KERNEL_FUNCS_IN_SECT\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_text_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tMMU_PAGE_ALIGN_PERM\n\n\tlnkr_pinned_rodata_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n\tSECTION_PROLOGUE(pinned.rodata,,)\n\t{\n#include <zephyr\/arch\/x86\/ia32\/scripts\/static_intr.ld>\n\n\t\tLIB_KERNEL_IN_SECT(rodata)\n\t\tLIB_ARCH_X86_IN_SECT(rodata)\n\n\t\t*(.pinned_rodata)\n\t\t*(.pinned_rodata.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(rodata)\n\t\tLIB_C_IN_SECT(rodata)\n\t\tLIB_DRIVERS_IN_SECT(rodata)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(rodata)\n\n\t\t\/* Static strings *\/\n\t\t*(.rodata.str*.*)\n\t\t*(.rodata.*.str*.*)\n\n#ifdef CONFIG_NEWLIB_LIBC\n\t\t*libc.a:(.rodata)\n\t\t*libc.a:(.rodata.*)\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_rodata_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(pinned.data,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_data_start = .;\n\n\t\t. = ALIGN(4);\n\n#include <zephyr\/arch\/x86\/ia32\/scripts\/shared_kernel_pages.ld>\n#include <zephyr\/arch\/x86\/ia32\/scripts\/dynamic_intr.ld>\n\n\t\tLIB_KERNEL_IN_SECT(data)\n\t\tLIB_ARCH_X86_IN_SECT(data)\n\n\t\t*(.pinned_data)\n\t\t*(.pinned_data.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(data)\n\t\tLIB_C_IN_SECT(data)\n\t\tLIB_DRIVERS_IN_SECT(data)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(data)\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/arch\/x86\/pagetables.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n\tlnkr_pinned_data_end = .;\n\n\tSECTION_PROLOGUE(pinned.bss, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_pinned_bss_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(bss)\n\t\tLIB_ARCH_X86_IN_SECT(bss)\n\n\t\t*(.pinned_bss)\n\t\t*(.pinned_bss.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(bss)\n\t\tLIB_C_IN_SECT(bss)\n\t\tLIB_DRIVERS_IN_SECT(bss)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(bss)\n\n\t\tlnkr_pinned_bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t\/* PINNED APP SHARED MEMORY REGION *\/\n#include <app_smem_pinned.ld>\n\n\t_app_smem_pinned_size = _app_smem_pinned_end - _app_smem_pinned_start;\n\t_app_smem_pinned_num_words = _app_smem_pinned_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(pinned.noinit, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_pinned_noinit_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(noinit)\n\t\tLIB_ARCH_X86_IN_SECT(noinit)\n\n\t\t*(.pinned_noinit)\n\t\t*(.pinned_noinit.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(noinit)\n\t\tLIB_C_IN_SECT(noinit)\n\t\tLIB_DRIVERS_IN_SECT(noinit)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(noinit)\n\n#ifdef CONFIG_ZTEST\n\t\t\/* For tests\/kernel\/mem_slab\/ tests *\/\n\t\t*(.noinit.*.k_mem_slab_buf_*)\n\n\t\t\/* For tests\/kernel\/mem_heap tests *\/\n\t\t*(.noinit.*.kheap_buf_*)\n\n\t\t\/* Pin ztest_thread_stack.\n\t\t * This must be done or else double fault\n\t\t * may arise: testing exceptions while\n\t\t * page fault for the ztest stack.\n\t\t *\/\n\t\t*libsubsys__testsuite__ztest.a:(.noinit.*)\n#endif\n\n\t\tlnkr_pinned_noinit_end = .;\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_pinned_end = .;\n\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tlnkr_pinned_text_size = lnkr_pinned_text_end - lnkr_pinned_text_start;\n\tlnkr_pinned_rodata_size = lnkr_pinned_rodata_end - lnkr_pinned_rodata_start;\n\tlnkr_pinned_data_size = lnkr_pinned_data_end - lnkr_pinned_data_start;\n\tlnkr_pinned_bss_size = lnkr_pinned_bss_end - lnkr_pinned_bss_start;\n\tlnkr_pinned_noinit_size = lnkr_pinned_noinit_end - lnkr_pinned_noinit_start;\n\n#endif \/* CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n\/* From now on, put symbols into FLASH *\/\n#undef ROMABLE_REGION\n#define ROMABLE_REGION\tFLASH\n\n\t\/* This is to align the following sections in flash\n\t * to their corresponding virtual addresses.\n\t * In other words, the offset from start of flash\n\t * for these sections would be the same from start of\n\t * their virtual addresses. This provides a simple and\n\t * direct mapping from backing store.\n\t *\/\n\tflash_load_offset :\n\t{\n\t\t. = FLASH_ROM_ADDR + (lnkr_pinned_end - KERNEL_BASE_ADDR);\n\t} > FLASH AT > FLASH\n\n#endif\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \\\n    !defined(CONFIG_LINKER_USE_PINNED_SECTION)\n\tz_mapped_start = .;\n#endif\n\n#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \\\n    !defined(CONFIG_LINKER_USE_PINNED_SECTION)\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n#endif\n\n\t\/* Needs KEEP() as ENTRY() is given a physical address *\/\n\tKEEP(*(.text.__start))\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/linker\/kobject-text.ld>\n#endif\n\n\tMMU_PAGE_ALIGN_PERM\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__text_region_end = .;\n\t__text_region_size = __text_region_end - __text_region_start;\n\t__rodata_region_start = .;\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n#endif\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/arch\/x86\/ia32\/scripts\/static_intr.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n#endif\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t__rodata_region_end = .;\n\t__rodata_region_size = __rodata_region_end - __rodata_region_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN_PERM\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/arch\/x86\/ia32\/scripts\/dynamic_intr.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/arch\/x86\/ia32\/scripts\/shared_kernel_pages.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <zephyr\/linker\/kobject-data.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;\n\n\tz_mapped_end = .;\n\tz_mapped_size = z_mapped_end - z_mapped_start;\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_ZEPHYR_FINAL\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n * Copyright (c) 2021 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <zephyr\/devicetree.h>\n#include <offsets.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n#include <zephyr\/sys\/util.h>\n#include <zephyr\/sys\/mem_manage.h>\n\n\n\/* Bounds of physical RAM from DTS *\/\n#define PHYS_RAM_ADDR\t\t\tDT_REG_ADDR(DT_CHOSEN(zephyr_sram))\n#define PHYS_RAM_SIZE\t\t\tDT_REG_SIZE(DT_CHOSEN(zephyr_sram))\n\n\/* Bounds of flash from DTS *\/\n#define FLASH_ROM_ADDR\t\t\tDT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define FLASH_ROM_SIZE\t\t\tDT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n\n\/* Virtual base address for the kernel; with CONFIG_MMU this is not necessarily\n * the same as its physical location, although an identity mapping for RAM\n * is still supported by setting CONFIG_KERNEL_VM_BASE=CONFIG_SRAM_BASE_ADDRESS.\n *\/\n#ifdef Z_VM_KERNEL\n\n#define KERNEL_BASE_ADDR \\\n\t(CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET)\n\n#define KERNEL_RAM_SIZE \\\n\t(CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET)\n\n#define PHYS_RAM_AVAIL \\\n\t(PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n\n#else\n\n#define KERNEL_BASE_ADDR\t\t(PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n#define KERNEL_RAM_SIZE\t\t\t(PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n\n#endif\n\n\/* \"kernel RAM\" for linker VMA allocations starts at the offset *\/\n\n\/* Physical RAM location where the kernel image is loaded *\/\n#define PHYS_LOAD_ADDR\t\t\t(PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n\n#ifdef CONFIG_USERSPACE\n#define SMEM_PARTITION_ALIGN(size)\tMMU_PAGE_ALIGN_PERM\n#define APP_SHARED_ALIGN\t\tMMU_PAGE_ALIGN_PERM\n#endif\n\nMEMORY\n    {\n#if defined(Z_VM_KERNEL)\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_AVAIL\n#endif\n    RAM (wx)        : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n    FLASH (rw)      : ORIGIN = FLASH_ROM_ADDR, LENGTH = FLASH_ROM_SIZE\n#endif\n\n    \/*\n     * On 32-bit x86, fake memory area for build-time IDT generation data.\n     *\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 0xFFFF1000, LENGTH = 2K\n    }\n\n#if defined(Z_VM_KERNEL)\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_MMU\n\t#define MMU_PAGE_ALIGN\t\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n\n#undef SECTION_PROLOGUE\n#define SECTION_PROLOGUE(name, options, align) \\\n        name options : ALIGN_WITH_INPUT align\n\n#undef SECTION_DATA_PROLOGUE\n#define SECTION_DATA_PROLOGUE(name, options, align) \\\n        name options : ALIGN_WITH_INPUT align\n\n#undef GROUP_ROM_LINK_IN\n#define GROUP_ROM_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#undef GROUP_DATA_LINK_IN\n#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#undef GROUP_NOLOAD_LINK_IN\n#define GROUP_NOLOAD_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#endif\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN_PERM\tMMU_PAGE_ALIGN\n#else\n\t#define MMU_PAGE_ALIGN_PERM\n#endif\n\n\/* For all source files under arch\/x86\/. *\/\n#define LIB_ARCH_X86_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libarch__x86__core.a.a:(.##lsect)\t\t\t\t\\\n\t*libarch__x86__core.a:(.##lsect##.*)\n\n#ifdef CONFIG_MINIMAL_LIBC\n\/* For all source files under lib\/libc\/minimal\/.\n * These files includes, for example, math and string functions.\n *\/\n#define LIB_C_IN_SECT(lsect)\t\t\t\t\t\t\\\n\t*liblib__libc__minimal.a:(.##lsect)\t\t\t\t\\\n\t*liblib__libc__minimal.a:(.##lsect##.*)\n\n#endif \/* CONFIG_MINIMAL_LIBC *\/\n\n#ifdef CONFIG_NEWLIB_LIBC\n\/* For Newlib libc-hook.c. *\/\n#define LIB_C_IN_SECT(lsect)\t\t\t\t\t\t\\\n\t*liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect)\t\t\\\n\t*liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect##.*)\n\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n\/*\n * For drivers that are usually used (e.g. serial)\n *\/\n#define LIB_DRIVERS_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libdrivers__serial.a:(.##lsect)\t\t\t\t\\\n\t*libdrivers__serial.a:(.##lsect##.*)\t\t\t\t\\\n\t*hpet.c.obj(.##lsect)\t\t\t\t\t\t\\\n\t*hpet.c.obj(.##lsect##.*)\t\t\t\t\t\\\n\t*intc_ioapic.c.obj(.##lsect)\t\t\t\t\t\\\n\t*intc_ioapic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*intc_loapic.c.obj(.##lsect)\t\t\t\t\t\\\n\t*intc_loapic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*intc_system_apic.c.obj(.##lsect)\t\t\t\t\\\n\t*intc_system_apic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*rand32_timer.c.obj(.##lsect)\t\t\t\t\t\\\n\t*rand32_timer.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*uart_console.c.obj(.##lsect)\t\t\t\t\t\\\n\t*uart_console.c.obj(.##lsect##.*)\n\n\/* For all source files under kernel\/. and kernel related files *\/\n#define LIB_KERNEL_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libkernel.a:(.##lsect)\t\t\t\t\t\t\\\n\t*libkernel.a:(.##lsect##.*)\t\t\t\t\t\\\n\t*libsubsys__demand_paging__*.a:(.##lsect)\t\t\t\\\n\t*libsubsys__demand_paging__*.a:(.##lsect##.*)\n\n\/* For particular file packaged in libzephyr.a. *\/\n#define LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, objfile)\t\t\t\\\n\t*libzephyr.a:objfile.c.obj(.##lsect)\t\t\t\t\\\n\t*libzephyr.a:objfile.c.obj(.##lsect##.*)\n\n\/* For source files under lib\/os\/ with commonly used functions. *\/\n#define LIB_ZEPHYR_IN_SECT(lsect)\t\t\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, assert)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, bitarray)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_complete)\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_nano)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, configs)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap-validate)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, mutex)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, notify)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, printk)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sem)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, stdout_console)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sys_clock_init)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, rb)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, thread_entry)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, work_q)\n\n\/*\n * Catch all for all internal\/external kernel functions\n * as they are usually defined as \"static inline\" where\n * they are attached to the source which uses them.\n * Hence the need to specify them here so they can be pinned.\n *\/\n#define ZEPHYR_KERNEL_FUNCS_IN_SECT\t\t\t\t\t\\\n\t*(.text.atomic_*)\t\t\t\t\t\t\\\n\t*(.text.k_*)\t\t\t\t\t\t\t\\\n\t*(.text.sys_*_bit)\t\t\t\t\t\t\\\n\t*(.text.sys_bitfield_*)\t\t\t\t\t\t\\\n\t*(.text.sys_clock_hw_cycles_per_sec)\t\t\t\t\\\n\t*(.text.sys_cache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_dcache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_icache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_mutex_*)\t\t\t\t\t\t\\\n\t*(.text.sys_notify_*)\t\t\t\t\t\t\\\n\t*(.text.sys_dlist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_slist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_sflist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_sfnode_*)\t\t\t\t\t\t\\\n\t*(.text.sys_io_*)\t\t\t\t\t\t\\\n\t*(.text.sys_in*)\t\t\t\t\t\t\\\n\t*(.text.sys_out*)\t\t\t\t\t\t\\\n\t*(.text.sys_read*)\t\t\t\t\t\t\\\n\t*(.text.sys_write*)\t\t\t\t\t\t\\\n\t*(.text.sys_get_be*)\t\t\t\t\t\t\\\n\t*(.text.sys_get_le*)\t\t\t\t\t\t\\\n\t*(.text.sys_put_be*)\t\t\t\t\t\t\\\n\t*(.text.sys_put_le*)\t\t\t\t\t\t\\\n\t*(.text.sys_mem_swap)\t\t\t\t\t\t\\\n\t*(.text.sys_memcpy_swap)\t\t\t\t\t\\\n\t*(.text.z_*)\n\n\/* For logging subsys *\/\n#define LIB_SUBSYS_LOGGING_IN_SECT(lsect)\t\t\t\t\\\n\t*log_*.c.obj(.##lsect)\t\t\t\t\t\t\\\n\t*log_*.c.obj(.##lsect.*)\t\t\t\t\t\\\n\t*mpsc_pbuf.c.obj(.##lsect)\t\t\t\t\t\\\n\t*mpsc_pbuf.c.obj(.##lsect.*)\n\nepoint = Z_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY);\nENTRY(epoint)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n#ifdef CONFIG_LINKER_USE_BOOT_SECTION\n\n\tSECTION_PROLOGUE(boot.text,,)\n\t{\n#include <snippets-rom-start.ld>\n\n\t\tMMU_PAGE_ALIGN\n\t\tlnkr_boot_start = .;\n\t\tz_mapped_start = .;\n\n\t\tlnkr_boot_text_start = .;\n\n\t\tKEEP(*(.boot_text.__start))\n\t\t*(.boot_text)\n\t\t*(.boot_text.*)\n\n\t\t*(.text.k_mem_paging_backing_store_init)\n\t\t*(.text.k_mem_paging_eviction_init)\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_text_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.rodata,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_rodata_start = .;\n\n\t\t*(.boot_rodata)\n\t\t*(.boot_rodata.*)\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_rodata_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.data,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_data_start = .;\n\n\t\t*(.boot_data)\n\t\t*(.boot_data.*)\n\n\t\tlnkr_boot_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.bss, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_bss_start = .;\n\n\t\t*(.boot_bss)\n\t\t*(.boot_bss.*)\n\n\t\tlnkr_boot_bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.noinit, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_noinit_start = .;\n\n\t\t*(.boot_noinit)\n\t\t*(.boot_noinit.*)\n\n\t\tlnkr_boot_noinit_end = .;\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_boot_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tlnkr_boot_text_size = lnkr_boot_text_end - lnkr_boot_text_start;\n\tlnkr_boot_rodata_size = lnkr_boot_rodata_end - lnkr_boot_rodata_start;\n\tlnkr_boot_data_size = lnkr_boot_data_end - lnkr_boot_data_start;\n\tlnkr_boot_bss_size = lnkr_boot_bss_end - lnkr_boot_bss_start;\n\tlnkr_boot_noinit_size = lnkr_boot_noinit_end - lnkr_boot_noinit_start;\n\n#endif \/* CONFIG_LINKER_USE_BOOT_SECTION *\/\n\n#ifdef CONFIG_LINKER_USE_PINNED_SECTION\n\n\tSECTION_PROLOGUE(pinned.text,,)\n\t{\n#ifndef CONFIG_LINKER_USE_BOOT_SECTION\n#include <snippets-rom-start.ld>\n#endif\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_pinned_start = .;\n\n#ifndef CONFIG_LINKER_USE_BOOT_SECTION\n\t\tz_mapped_start = .;\n#endif\n\n\t\tlnkr_pinned_text_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(text)\n\t\tLIB_ARCH_X86_IN_SECT(text)\n\t\t*(.text._OffsetAbsSyms)\n\n\t\t*(.pinned_text)\n\t\t*(.pinned_text.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(text)\n\t\tLIB_C_IN_SECT(text)\n\t\tLIB_DRIVERS_IN_SECT(text)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(text)\n\n\t\t*_divdi3.o(.text)\n\t\t*_udivdi3.o(.text)\n\t\t*_udivmoddi4.o(.text)\n\t\t*_umoddi3.o(.text)\n\t\t*_popcountsi2.o(.text)\n\n\t\t*(.gnu.linkonce.t.exc_*)\n\n\t\t*(.text.*.constprop)\n\t\t*(.text.*.constprop.*)\n\n#ifdef CONFIG_NEWLIB_LIBC\n\t\t*libc.a:(.text)\n\t\t*libc.a:(.text.*)\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n\t\tZEPHYR_KERNEL_FUNCS_IN_SECT\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_text_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tMMU_PAGE_ALIGN_PERM\n\n\tlnkr_pinned_rodata_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n\tSECTION_PROLOGUE(pinned.rodata,,)\n\t{\n#include <zephyr\/arch\/x86\/ia32\/scripts\/static_intr.ld>\n\n\t\tLIB_KERNEL_IN_SECT(rodata)\n\t\tLIB_ARCH_X86_IN_SECT(rodata)\n\n\t\t*(.pinned_rodata)\n\t\t*(.pinned_rodata.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(rodata)\n\t\tLIB_C_IN_SECT(rodata)\n\t\tLIB_DRIVERS_IN_SECT(rodata)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(rodata)\n\n\t\t\/* Static strings *\/\n\t\t*(.rodata.str*.*)\n\t\t*(.rodata.*.str*.*)\n\n#ifdef CONFIG_NEWLIB_LIBC\n\t\t*libc.a:(.rodata)\n\t\t*libc.a:(.rodata.*)\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_rodata_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(pinned.data,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_data_start = .;\n\n\t\t. = ALIGN(4);\n\n#include <zephyr\/arch\/x86\/ia32\/scripts\/shared_kernel_pages.ld>\n#include <zephyr\/arch\/x86\/ia32\/scripts\/dynamic_intr.ld>\n\n\t\tLIB_KERNEL_IN_SECT(data)\n\t\tLIB_ARCH_X86_IN_SECT(data)\n\n\t\t*(.pinned_data)\n\t\t*(.pinned_data.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(data)\n\t\tLIB_C_IN_SECT(data)\n\t\tLIB_DRIVERS_IN_SECT(data)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(data)\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/arch\/x86\/pagetables.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n\tlnkr_pinned_data_end = .;\n\n\tSECTION_PROLOGUE(pinned.bss, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_pinned_bss_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(bss)\n\t\tLIB_ARCH_X86_IN_SECT(bss)\n\n\t\t*(.pinned_bss)\n\t\t*(.pinned_bss.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(bss)\n\t\tLIB_C_IN_SECT(bss)\n\t\tLIB_DRIVERS_IN_SECT(bss)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(bss)\n\n\t\tlnkr_pinned_bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t\/* PINNED APP SHARED MEMORY REGION *\/\n#include <app_smem_pinned.ld>\n\n\t_app_smem_pinned_size = _app_smem_pinned_end - _app_smem_pinned_start;\n\t_app_smem_pinned_num_words = _app_smem_pinned_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(pinned.noinit, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_pinned_noinit_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(noinit)\n\t\tLIB_ARCH_X86_IN_SECT(noinit)\n\n\t\t*(.pinned_noinit)\n\t\t*(.pinned_noinit.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(noinit)\n\t\tLIB_C_IN_SECT(noinit)\n\t\tLIB_DRIVERS_IN_SECT(noinit)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(noinit)\n\n#ifdef CONFIG_ZTEST\n\t\t\/* For tests\/kernel\/mem_slab\/ tests *\/\n\t\t*(.noinit.*.k_mem_slab_buf_*)\n\n\t\t\/* For tests\/kernel\/mem_heap tests *\/\n\t\t*(.noinit.*.kheap_buf_*)\n\n\t\t\/* Pin ztest_thread_stack.\n\t\t * This must be done or else double fault\n\t\t * may arise: testing exceptions while\n\t\t * page fault for the ztest stack.\n\t\t *\/\n\t\t*libsubsys__testsuite__ztest.a:(.noinit.*)\n#endif\n\n\t\tlnkr_pinned_noinit_end = .;\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_pinned_end = .;\n\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tlnkr_pinned_text_size = lnkr_pinned_text_end - lnkr_pinned_text_start;\n\tlnkr_pinned_rodata_size = lnkr_pinned_rodata_end - lnkr_pinned_rodata_start;\n\tlnkr_pinned_data_size = lnkr_pinned_data_end - lnkr_pinned_data_start;\n\tlnkr_pinned_bss_size = lnkr_pinned_bss_end - lnkr_pinned_bss_start;\n\tlnkr_pinned_noinit_size = lnkr_pinned_noinit_end - lnkr_pinned_noinit_start;\n\n#endif \/* CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n\/* From now on, put symbols into FLASH *\/\n#undef ROMABLE_REGION\n#define ROMABLE_REGION\tFLASH\n\n\t\/* This is to align the following sections in flash\n\t * to their corresponding virtual addresses.\n\t * In other words, the offset from start of flash\n\t * for these sections would be the same from start of\n\t * their virtual addresses. This provides a simple and\n\t * direct mapping from backing store.\n\t *\/\n\tflash_load_offset :\n\t{\n\t\t. = FLASH_ROM_ADDR + (lnkr_pinned_end - KERNEL_BASE_ADDR);\n\t} > FLASH AT > FLASH\n\n#endif\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \\\n    !defined(CONFIG_LINKER_USE_PINNED_SECTION)\n\tz_mapped_start = .;\n#endif\n\n#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \\\n    !defined(CONFIG_LINKER_USE_PINNED_SECTION)\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n#endif\n\n\t\/* Needs KEEP() as ENTRY() is given a physical address *\/\n\tKEEP(*(.text.__start))\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/linker\/kobject-text.ld>\n#endif\n\n\tMMU_PAGE_ALIGN_PERM\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__text_region_end = .;\n\t__text_region_size = __text_region_end - __text_region_start;\n\t__rodata_region_start = .;\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n#endif\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/arch\/x86\/ia32\/scripts\/static_intr.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n#endif\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t__rodata_region_end = .;\n\t__rodata_region_size = __rodata_region_end - __rodata_region_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN_PERM\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/arch\/x86\/ia32\/scripts\/dynamic_intr.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/arch\/x86\/ia32\/scripts\/shared_kernel_pages.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <zephyr\/linker\/kobject-data.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;\n\n\tz_mapped_end = .;\n\tz_mapped_size = z_mapped_end - z_mapped_start;\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_ZEPHYR_FINAL\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cb25a350eca4f0e6aef4546a13b0d42d21f81be7","subject":"x86: Improve linker script","message":"x86: Improve linker script\n","repos":"uni-rs\/uni.rs","old_file":"src\/arch\/x86\/linker.ld","new_file":"src\/arch\/x86\/linker.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSECTIONS\n{\n    . = 0x0;\n\n    .text : {\n        *(.text .text.*)\n    }\n\n    .rodata : {\n        *(.rodata .rodata.*)\n    }\n\n    .data : {\n        *(.data .data.*)\n    }\n\n    \/DISCARD\/ : {\n        *(.note .note.*)\n        *(.debug .debug.*)\n    }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSECTIONS\n{\n    . = 0x0;\n\n    .text : {\n        *(.text)\n        *(.text.*)\n    }\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data : {\n        *(.data)\n    }\n\n    \/DISCARD\/ : {\n        *(.note.*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"486d05ff17f8fee8626e27ca26ce00041952beef","subject":"nrf5\/boards: Releasing more RAM for heap use in the nrf51 s110 linker script.","message":"nrf5\/boards: Releasing more RAM for heap use in the nrf51 s110 linker script.\n","repos":"adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,tralamazza\/micropython,tralamazza\/micropython","old_file":"nrf5\/boards\/nrf51822_aa_s110.ld","new_file":"nrf5\/boards\/nrf51822_aa_s110.ld","new_contents":"\/*\n    GNU linker script for NRF51822 AA w\/ S110 8.0.0 SoftDevice\n*\/\n\/* Specify the memory areas *\/\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00018000, LENGTH = 0x000400 \/* sector 0, 1 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 \/* 159 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20001000, LENGTH = 0x003000 \/* 12 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 8K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20003000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF51822 AA w\/ S110 8.0.0 SoftDevice\n*\/\n\/* Specify the memory areas *\/\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00018000, LENGTH = 0x000400 \/* sector 0, 1 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 \/* 159 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20002000, LENGTH = 0x002000 \/* 8 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 4K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20003000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c1606587ef6340f77e50be44b0ba67bab0296c7b","subject":"Change linker script to STM32F405RG","message":"Change linker script to STM32F405RG\n\nRAM and Flash size are different.\n","repos":"UrsusPilot\/firmware,UrsusPilot\/firmware,UrsusPilot\/firmware,shengwen1997\/moonbear-firmware,shengwen1997\/moonbear-firmware,shengwen1997\/moonbear-firmware,ming6842\/firmware-new,ming6842\/firmware-new,fboris\/firmware,ming6842\/firmware,zxc2694\/moonbear-firmware,zxc2694\/moonbear-firmware,fboris\/firmware,ming6842\/firmware,ming6842\/firmware,ming6842\/firmware-new,fboris\/firmware,zxc2694\/moonbear-firmware","old_file":"Program\/stm32_flash.ld","new_file":"Program\/stm32_flash.ld","new_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F405RG Device with\n**                1024KByte FLASH, 192KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the Atollic TrueSTUDIO(R) toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20020000;    \/* end of 128K RAM on AHB bus*\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0xA00; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\n  .memory_b1_text :\n  {\n    *(.mb1text)        \/* .mb1text sections (code) *\/\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\n    *(.mb1rodata)      \/* read-only data (constants) *\/\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F207IG Device with\n**                1024KByte FLASH, 112KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the Atollic TrueSTUDIO(R) toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x2001c000;    \/* end of 112K RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0xA00; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 112K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\n  .memory_b1_text :\n  {\n    *(.mb1text)        \/* .mb1text sections (code) *\/\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\n    *(.mb1rodata)      \/* read-only data (constants) *\/\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"24855f71ebd387c5d7725ef2e6fd1ba9708c22e9","subject":"soc\/intel_adsp: Linkage cleanup","message":"soc\/intel_adsp: Linkage cleanup\n\nSyntax beautification and general simplification pass:\n\n+ Remove some spurious padding around the _data_end symbol.  That's a\n  Zephyr symbol and should reflect the actual end of the data section in\n  bytes.\n\n+ Squash a warning that crept in where the linker doesn't like\n  changing cache mapping and padding at one time, clarify in docs.\n\n+ Use the pre-existing-but-heretofore-unknown-to-me Zephyr\n  debug-sections.ld include file instead of putting all the DWARF\n  sections in by hand.\n\n+ Move the .xt* sections to explicit zero addresses, since that's what\n  debug-sections.ld does for its output and if I don't they'll end up\n  with funny values.\n\n+ Use Zephyr brace-on-same-line style consistently\n\n+ Remove cargo-cult noop patterns like ALIGN(4) and ABSOLUTE(.) (none\n  of these sections get furthur relocated!)\n\n+ Clean up the SEGSTART_* API so that it doesn't need to have\n  CONFIG_KERNEL_COHERENCE guards.\n\n+ Remove a few unused\/legacy symbol exports (\"end\", \"__stack\") so as\n  not to pollute the namespace.\n\nSigned-off-by: Andy Ross <c70f9a6bf6ee0cd69c8af4ce5e6b131945769315@intel.com>\n","repos":"zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <cavs-vectors.h>\n#include <cavs-mem.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n * (Note clumsy syntax because XCC doesn't understand the \"~\" operator)\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & 0xdfffffff) \/* == ~0x20000000 *\/\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#define ucram_phdr ram_phdr\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\nMEMORY {\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr\n\n .MemoryExceptionVector.literal : {\n    _MemoryExceptionVector_literal_start = .;\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = .;\n  } >vector_memory_lit\n  .MemoryExceptionVector.text : {\n    _MemoryExceptionVector_text_start = .;\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = .;\n  } >vector_memory_text\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int6_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int6_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.module_init)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n    *(.cached .cached.*)\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  \/* Heap start and end markers.  Mostly unused, though newlib likes them *\/\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) }\n  .module.main : { KEEP(*(.module.main)) }\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  }\n\n  .static_log_entries : {\n    *(*.static_log*)\n  }\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Assignment to \".\" forces this section to be\n   * created.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  }\n\n#include <linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <cavs-vectors.h>\n#include <cavs-mem.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n * (Note clumsy syntax because XCC doesn't understand the \"~\" operator)\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & 0xdfffffff) \/* == ~0x20000000 *\/\n#else\n#define SEGSTART_CACHED   \/**\/\n#define SEGSTART_UNCACHED \/**\/\n#define ucram ram\n#define ucram_phdr ram_phdr\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n}\n\n_EXT_MAN_ALIGN_ = 16;\n\nSECTIONS\n{\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram\n\n#ifdef CONFIG_KERNEL_COHERENCE\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n  . = SEGSTART_UNCACHED;\n#endif\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) : ALIGN(4096)\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_CACHED;\n#endif\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >lpram\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_UNCACHED;\n#endif\n  _heap_sentry = .;\n\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n  . = SEGSTART_CACHED;\n#endif\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) }\n  .module.main : { KEEP(*(.module.main)) }\n\n  .comment : { *(.comment) }\n  .debug : { *(.debug) }\n  .line : { *(.line) }\n  .debug_srcinfo : { *(.debug_srcinfo) }\n  .debug_sfnames : { *(.debug_sfnames) }\n  .debug_aranges : { *(.debug_aranges) }\n  .debug_pubnames : { *(.debug_pubnames) }\n  .debug_info : { *(.debug_info) }\n  .debug_abbrev : { *(.debug_abbrev) }\n  .debug_line : { *(.debug_line) }\n  .debug_frame : { *(.debug_frame) }\n  .debug_str : { *(.debug_str) }\n  .debug_loc : { *(.debug_loc) }\n  .debug_macinfo : { *(.debug_macinfo) }\n  .debug_weaknames : { *(.debug_weaknames) }\n  .debug_funcnames : { *(.debug_funcnames) }\n  .debug_typenames : { *(.debug_typenames) }\n  .debug_varnames : { *(.debug_varnames) }\n  .debug_ranges : { *(.debug_ranges) }\n  .xtensa.info : { *(.xtensa.info) }\n  .xt.insn :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  }\n\n  .static_log_entries : {\n    *(*.static_log*)\n  }\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Assignment to \".\" forces this section to be\n   * created.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    . = .;\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3fc1ccd8e57d8e36f45d3ef48d5ccb83620d83e0","subject":"arch: arm64: Include GOT in RODATA","message":"arch: arm64: Include GOT in RODATA\n\nGCC 12 and above may emit \"GOT indirections\" for the weak symbol\nreferences, and this requires the Global Offset Table (GOT) to be\nincluded in the output.\n\nThis commit places the `.got` section in the RODATA section so that\nthe addresses of the weak symbols can be resolved at run-time. Note\nthat the GOT is populated with the symbol addresses at the default\nlinking address by the linker.\n\nThe `.got.plt` section, although unused, is also placed in the RODATA\nsection because the linker refuses to allow discarding this section\neven when the `.plt` section is discarded.\n\nIn case of the GCC releases prior to 12, the weak symbol addresses are\nplaced in the literal pool and the `.got` section is not created at\nall; therefore, this patch will be no-op.\n\nFor more details, refer to the following GitHub issue:\nzephyrproject-rtos\/sdk-ng#547.\n\nSigned-off-by: Stephanos Ioannidis <dc76e9f0c0006e8f919e0c515c66dbba3982f785@stephanos.io>\n","repos":"galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"include\/zephyr\/arch\/arm64\/scripts\/linker.ld","new_file":"include\/zephyr\/arch\/arm64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#elif defined(CONFIG_ARM_MPU)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n  #define BSS_ALIGN ALIGN(_region_min_align)\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#ifndef BSS_ALIGN\n#define BSS_ALIGN\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    __rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        __text_region_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __text_region_end = .;\n    __text_region_size = __text_region_end - __text_region_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n        __rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n        \/*\n         * The following is a workaround to allow compiling with GCC 12 and\n         * above, which may emit \"GOT indirections\" for the weak symbol\n         * references (see the GitHub issue zephyrproject-rtos\/sdk-ng#547).\n         *\/\n        *(.got)\n        *(.got.plt)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    __rodata_region_end = .;\n    __rodata_region_size = __rodata_region_end - __rodata_region_start;\n    __rom_region_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.igot.plt)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#if defined(CONFIG_ARM_MPU)\n\/*\n * When _app_smem region is empty, alignment is also needed. If there\n * is no alignment, the _app_smem_start used by arm mpu can be lower\n * than __rodata_region_end, and this two regions can overlap.\n * The Armv8-R aarch64 MPU does not allow overlapped regions.\n *\/\n#define EMPTY_APP_SHARED_ALIGN APP_SHARED_ALIGN\n#endif\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n\t__data_region_start = .;\n\t__data_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        __data_end = .;\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#elif defined(CONFIG_ARM_MPU)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n  #define BSS_ALIGN ALIGN(_region_min_align)\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#ifndef BSS_ALIGN\n#define BSS_ALIGN\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    __rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        __text_region_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __text_region_end = .;\n    __text_region_size = __text_region_end - __text_region_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n        __rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    __rodata_region_end = .;\n    __rodata_region_size = __rodata_region_end - __rodata_region_start;\n    __rom_region_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#if defined(CONFIG_ARM_MPU)\n\/*\n * When _app_smem region is empty, alignment is also needed. If there\n * is no alignment, the _app_smem_start used by arm mpu can be lower\n * than __rodata_region_end, and this two regions can overlap.\n * The Armv8-R aarch64 MPU does not allow overlapped regions.\n *\/\n#define EMPTY_APP_SHARED_ALIGN APP_SHARED_ALIGN\n#endif\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n\t__data_region_start = .;\n\t__data_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        __data_end = .;\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"df379b84cb00a3ad694fb89877529c6862a455cb","subject":"remove unneeded symbols","message":"remove unneeded symbols\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/atmel-samd\/boards\/common.template.ld","new_file":"ports\/atmel-samd\/boards\/common.template.ld","new_contents":"\/* Template for SAMD21\/SAMD51 linking. dollar-sign-curly-bracket items are replaced with strings. *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_BOOTLOADER (rx): ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_FILESYSTEM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_CONFIG (r) : ORIGIN = ${CIRCUITPY_INTERNAL_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_CONFIG_SIZE}\n    FLASH_NVM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n\n    RAM (xrw)  : ORIGIN = 0x20000000, LENGTH = ${RAM_SIZE}\n}\n\n\/* top end of the stack *\/\n\/* stack must be double-word (8 byte) aligned *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - 8;\n_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n    } >FLASH_FIRMWARE\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = .;       \/* start of .data section *\/\n    } >FLASH_FIRMWARE\n\n    \/* Data accessed by the CAN peripheral must be in the first 64kB RAM *\/\n    \/* place it at the very start of RAM, before the .data section *\/\n    \/* it is zeroed by reset_port *\/\n    .canram (NOLOAD) :\n    {\n        . = ALIGN(4);\n        *(.canram)\n    } > RAM\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH_FIRMWARE to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _srelocate = .;        \/* create a global symbol at data start; used by startup code in order to initialize the .data section in RAM *\/\n        . = ALIGN(4);\n        *(.ramfunc)\n        *(.ramfunc*)\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _erelocate = .;        \/* define a global symbol at data end; used by startup code in order to initialize the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        _szero = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ezero = .;         \/* define a global symbol at bss end; used by startup code *\/\n        _ebss = .;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the requested stack. *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/* Template for SAMD21\/SAMD51 linking. dollar-sign-curly-bracket items are replaced with strings. *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_BOOTLOADER (rx): ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_FILESYSTEM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_CONFIG (r) : ORIGIN = ${CIRCUITPY_INTERNAL_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_CONFIG_SIZE}\n    FLASH_NVM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n\n    RAM (xrw)  : ORIGIN = 0x20000000, LENGTH = ${RAM_SIZE}\n}\n\n\/* top end of the stack *\/\n\/* stack must be double-word (8 byte) aligned *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - 8;\n_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n    } >FLASH_FIRMWARE\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = .;       \/* start of .data section *\/\n    } >FLASH_FIRMWARE\n\n    \/* Data accessed by the CAN peripheral must be in the first 64kB RAM *\/\n    \/* place it at the very start of RAM, before the .data section *\/\n    \/* it is zeroed by reset_port *\/\n    .canram (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _scanram = .;\n        *(.canram)\n        _ecanram = .;\n    } > RAM\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH_FIRMWARE to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _srelocate = .;        \/* create a global symbol at data start; used by startup code in order to initialize the .data section in RAM *\/\n        . = ALIGN(4);\n        *(.ramfunc)\n        *(.ramfunc*)\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _erelocate = .;        \/* define a global symbol at data end; used by startup code in order to initialize the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        _szero = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ezero = .;         \/* define a global symbol at bss end; used by startup code *\/\n        _ebss = .;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the requested stack. *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"658f57d9a61cb13665e746e1e66109958b77fefd","subject":"Correct calculation of image size in the simple app linker script","message":"Correct calculation of image size in the simple app linker script\n","repos":"skordal\/mordax","old_file":"applications\/simple.ld","new_file":"applications\/simple.ld","new_contents":"\/*          Mordax simple standalone application linker script         *\/\n\/*   (c) Kristian Klomsten Skordal 2013 <kristian.skordal@gmail.com>   *\/\n\/* Report bugs and issues on <http:\/\/github.com\/skordal\/mordax\/issues> *\/\n\n\/*\n * This linker script is for very simple test applications that are\n * loaded as the initial process for the kernel. Because of this, all\n * the memory allocated for the process is mapped as executable and\n * read-write. This linker script reflects this by putting every\n * section into the .text section.\n *\/\n\nSECTIONS\n{\n\tENTRY(_start)\n\n\t.text 0x1000 :\n\t{\n\t\timage_start = .;\n\t\t*(.init*)\n\t\t*(.text*)\n\t\t*(.rodata*)\n\t\t*(.data*)\n\t\t*(.bss*)\n\t\timage_end = .;\n\t\timage_size = image_end - image_start;\n\t}\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.comment)\n\t\t*(.ARM.attributes)\n\t}\n}\n\n\n","old_contents":"\/*          Mordax simple standalone application linker script         *\/\n\/*   (c) Kristian Klomsten Skordal 2013 <kristian.skordal@gmail.com>   *\/\n\/* Report bugs and issues on <http:\/\/github.com\/skordal\/mordax\/issues> *\/\n\n\/*\n * This linker script is for very simple test applications that are\n * loaded as the initial process for the kernel. Because of this, all\n * the memory allocated for the process is mapped as executable and\n * read-write. This linker script reflects this by putting every\n * section into the .text section.\n *\/\n\nSECTIONS\n{\n\tENTRY(_start)\n\n\t.text 0x1000 :\n\t{\n\t\timage_start = .;\n\t\t*(.init*)\n\t\t*(.text*)\n\t\t*(.rodata*)\n\t\t*(.data*)\n\t\t*(.bss*)\n\t\timage_end = .;\n\t\timage_size = image_start - image_end;\n\t}\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.comment)\n\t\t*(.ARM.attributes)\n\t}\n}\n\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"462748de0c2668d40b7f2ea8f2b264d134d5d39b","subject":"esp8266\/esp8266.ld: Move main.o to iROM.","message":"esp8266\/esp8266.ld: Move main.o to iROM.\n","repos":"pramasoul\/micropython,blazewicz\/micropython,matthewelse\/micropython,pozetroninc\/micropython,toolmacher\/micropython,TDAbboud\/micropython,PappaPeppar\/micropython,MrSurly\/micropython,puuu\/micropython,tobbad\/micropython,SHA2017-badge\/micropython-esp32,mhoffma\/micropython,cwyark\/micropython,mhoffma\/micropython,adafruit\/circuitpython,dxxb\/micropython,kerneltask\/micropython,alex-robbins\/micropython,selste\/micropython,oopy\/micropython,hiway\/micropython,hiway\/micropython,pfalcon\/micropython,henriknelson\/micropython,Peetz0r\/micropython-esp32,chrisdearman\/micropython,matthewelse\/micropython,hiway\/micropython,infinnovation\/micropython,mhoffma\/micropython,tuc-osg\/micropython,HenrikSolver\/micropython,tobbad\/micropython,tuc-osg\/micropython,dmazzella\/micropython,SHA2017-badge\/micropython-esp32,henriknelson\/micropython,matthewelse\/micropython,trezor\/micropython,torwag\/micropython,pfalcon\/micropython,hosaka\/micropython,Timmenem\/micropython,lowRISC\/micropython,MrSurly\/micropython-esp32,pozetroninc\/micropython,alex-robbins\/micropython,lowRISC\/micropython,tralamazza\/micropython,adafruit\/circuitpython,toolmacher\/micropython,cwyark\/micropython,pfalcon\/micropython,kerneltask\/micropython,hosaka\/micropython,bvernoux\/micropython,trezor\/micropython,lowRISC\/micropython,PappaPeppar\/micropython,PappaPeppar\/micropython,Peetz0r\/micropython-esp32,dxxb\/micropython,dmazzella\/micropython,adafruit\/micropython,torwag\/micropython,alex-march\/micropython,ryannathans\/micropython,torwag\/micropython,micropython\/micropython-esp32,infinnovation\/micropython,jmarcelino\/pycom-micropython,jmarcelino\/pycom-micropython,Timmenem\/micropython,deshipu\/micropython,dxxb\/micropython,MrSurly\/micropython,chrisdearman\/micropython,adafruit\/circuitpython,henriknelson\/micropython,AriZuu\/micropython,ryannathans\/micropython,torwag\/micropython,tralamazza\/micropython,MrSurly\/micropython,oopy\/micropython,chrisdearman\/micropython,AriZuu\/micropython,jmarcelino\/pycom-micropython,pozetroninc\/micropython,deshipu\/micropython,SHA2017-badge\/micropython-esp32,jmarcelino\/pycom-micropython,pramasoul\/micropython,adafruit\/circuitpython,tobbad\/micropython,selste\/micropython,adafruit\/circuitpython,Timmenem\/micropython,henriknelson\/micropython,pfalcon\/micropython,hiway\/micropython,trezor\/micropython,PappaPeppar\/micropython,tobbad\/micropython,Peetz0r\/micropython-esp32,matthewelse\/micropython,alex-march\/micropython,MrSurly\/micropython,TDAbboud\/micropython,micropython\/micropython-esp32,SHA2017-badge\/micropython-esp32,selste\/micropython,adafruit\/micropython,AriZuu\/micropython,pfalcon\/micropython,MrSurly\/micropython-esp32,ryannathans\/micropython,puuu\/micropython,toolmacher\/micropython,TDAbboud\/micropython,HenrikSolver\/micropython,blazewicz\/micropython,HenrikSolver\/micropython,blazewicz\/micropython,Peetz0r\/micropython-esp32,oopy\/micropython,henriknelson\/micropython,pozetroninc\/micropython,hosaka\/micropython,MrSurly\/micropython-esp32,AriZuu\/micropython,dxxb\/micropython,infinnovation\/micropython,AriZuu\/micropython,alex-robbins\/micropython,TDAbboud\/micropython,trezor\/micropython,MrSurly\/micropython-esp32,bvernoux\/micropython,adafruit\/micropython,swegener\/micropython,puuu\/micropython,alex-march\/micropython,pramasoul\/micropython,swegener\/micropython,kerneltask\/micropython,tralamazza\/micropython,dxxb\/micropython,cwyark\/micropython,swegener\/micropython,HenrikSolver\/micropython,micropython\/micropython-esp32,toolmacher\/micropython,oopy\/micropython,oopy\/micropython,HenrikSolver\/micropython,cwyark\/micropython,dmazzella\/micropython,adafruit\/micropython,infinnovation\/micropython,selste\/micropython,matthewelse\/micropython,hosaka\/micropython,ryannathans\/micropython,SHA2017-badge\/micropython-esp32,bvernoux\/micropython,alex-march\/micropython,Timmenem\/micropython,hosaka\/micropython,kerneltask\/micropython,alex-robbins\/micropython,infinnovation\/micropython,deshipu\/micropython,hiway\/micropython,kerneltask\/micropython,tobbad\/micropython,pramasoul\/micropython,MrSurly\/micropython-esp32,trezor\/micropython,Peetz0r\/micropython-esp32,tralamazza\/micropython,micropython\/micropython-esp32,ryannathans\/micropython,mhoffma\/micropython,MrSurly\/micropython,deshipu\/micropython,swegener\/micropython,adafruit\/circuitpython,blazewicz\/micropython,pramasoul\/micropython,micropython\/micropython-esp32,puuu\/micropython,alex-march\/micropython,mhoffma\/micropython,lowRISC\/micropython,tuc-osg\/micropython,Timmenem\/micropython,blazewicz\/micropython,bvernoux\/micropython,deshipu\/micropython,TDAbboud\/micropython,lowRISC\/micropython,swegener\/micropython,dmazzella\/micropython,selste\/micropython,bvernoux\/micropython,chrisdearman\/micropython,pozetroninc\/micropython,torwag\/micropython,PappaPeppar\/micropython,tuc-osg\/micropython,chrisdearman\/micropython,cwyark\/micropython,alex-robbins\/micropython,adafruit\/micropython,toolmacher\/micropython,jmarcelino\/pycom-micropython,puuu\/micropython,tuc-osg\/micropython,matthewelse\/micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40209000, len = 0x87000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        build\/main.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybuart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *modmachinewdt.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modpybhspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40209000, len = 0x87000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybuart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *modmachinewdt.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modpybhspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4bc4a5fb776a44e7289effcefd39dd9b727945d8","subject":"Added printf as irom for more space","message":"Added printf as irom for more space\n","repos":"mianos\/micropython,mianos\/micropython,mianos\/micropython,mianos\/micropython,mianos\/micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n        *py\/*.o*(.literal* .text*)\n        *pyexec.o(.literal*, .text*)\n        *readline.o(.literal*, .text*)\n        *pybstdio.o(.literal*, .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *modpybadc.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *strtoll.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *printf.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *py\/*.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *py\/*.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *py\/*.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n        *py\/*.o*(.literal* .text*)\n        *pyexec.o(.literal*, .text*)\n        *readline.o(.literal*, .text*)\n        *pybstdio.o(.literal*, .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *modpybadc.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *strtoll.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        \/* *extmod\/*.o(.literal* .text*)  *\/\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *py\/*.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *py\/*.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *py\/*.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c0adbd3c45d347304ad6df5b1e872614ab1e261d","subject":"fix KEEP","message":"fix KEEP\n","repos":"hirakuni45\/R8C,hirakuni45\/R8C,hirakuni45\/R8C","old_file":"M120AN\/m120an.ld","new_file":"M120AN\/m120an.ld","new_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x00300, LENGTH = 0x00400\n\tROM (r)  : ORIGIN = 0x08000, LENGTH = 0x07FD8\n\tEXT (r)  : ORIGIN = 0x10000, LENGTH = 0x08000\n\tVVEC (r) : ORIGIN = 0x0FED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0x0FFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0780;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  .exttext   :\n  {\n    *(.exttext .stub .exttext.* .gnu.linkonce.t.*)\n    KEEP (*(.exttext.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n  } > EXT =0\n\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    KEEP( *(.vvec) )\n  } > VVEC\n\n  .fvec : {\n    KEEP( *(.fvec) )\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x00300, LENGTH = 0x00400\n\tROM (r)  : ORIGIN = 0x08000, LENGTH = 0x07FD8\n\tEXT (r)  : ORIGIN = 0x10000, LENGTH = 0x08000\n\tVVEC (r) : ORIGIN = 0x0FED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0x0FFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0780;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  .exttext   :\n  {\n    *(.exttext .stub .exttext.* .gnu.linkonce.t.*)\n    KEEP (*(.exttext.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n  } > EXT =0\n\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"1afedd5382d4ca53de6d9f0948c9fe56de2ed242","subject":"x86: Add output formats to linker script","message":"x86: Add output formats to linker script\n","repos":"zhicheng\/seL4,cmr\/seL4,cmr\/seL4,cmr\/seL4,zhicheng\/seL4,zhicheng\/seL4","old_file":"src\/plat\/pc99\/linker.lds","new_file":"src\/plat\/pc99\/linker.lds","new_contents":"\/*\n * Copyright 2014, General Dynamics C4 Systems\n *\n * This software may be distributed and modified according to the terms of\n * the GNU General Public License version 2. Note that NO WARRANTY is provided.\n * See \"LICENSE_GPLv2.txt\" for details.\n *\n * @TAG(GD_GPL)\n *\/\n\n#include <config.h>\n\nENTRY(_start)\n\n\/* WARNING: constants also defined in plat\/machine\/hardware.h *\/\nPADDR_BASE = 0x00000000;\nPADDR_LOAD = 0x00100000;\nKERNEL_BASE  = 0xe0000000;\nOUTPUT_ARCH(i386)\nOUTPUT_FORMAT(elf32-i386)\n\nKERNEL_OFFSET = KERNEL_BASE - PADDR_BASE;\n\nSECTIONS\n{\n    \/* load kernel to 1M to avoid the famous IA-32 memory holes below *\/\n    . = PADDR_LOAD;\n\n    \/* code\/data only needed during bootstrapping, linked to physical addresses *\/\n\n    .phys . :\n    {\n        *(.mbh)\n        *(.phys.text)\n        _boot_stack_bottom = .;\n        . = . + 2K;\n        . = ALIGN(4K);\n        _boot_stack_top = .;\n        *(.phys)\n        *(.phys.*)\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .boot . : AT(ADDR(.boot) - KERNEL_OFFSET)\n    {\n        *(.boot.text)\n        *(.boot.data)\n        . = ALIGN(4K);\n    }\n\n    ki_boot_end = .;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        *(.text)\n    }\n\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    .ehframe : AT(ADDR(.ehframe) - KERNEL_OFFSET)\n    {\n        _ehframe = .;\n        *(.eh_frame)\n        . = ALIGN(4K);\n    }\n\n    . = ALIGN(4K);\n    ki_end = .;\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n    }\n}\n","old_contents":"\/*\n * Copyright 2014, General Dynamics C4 Systems\n *\n * This software may be distributed and modified according to the terms of\n * the GNU General Public License version 2. Note that NO WARRANTY is provided.\n * See \"LICENSE_GPLv2.txt\" for details.\n *\n * @TAG(GD_GPL)\n *\/\n\n#include <config.h>\n\nENTRY(_start)\n\n\/* WARNING: constants also defined in plat\/machine\/hardware.h *\/\nPADDR_BASE = 0x00000000;\nPADDR_LOAD = 0x00100000;\nKERNEL_BASE  = 0xe0000000;\nKERNEL_OFFSET = KERNEL_BASE - PADDR_BASE;\n\nSECTIONS\n{\n    \/* load kernel to 1M to avoid the famous IA-32 memory holes below *\/\n    . = PADDR_LOAD;\n\n    \/* code\/data only needed during bootstrapping, linked to physical addresses *\/\n\n    .phys . :\n    {\n        *(.mbh)\n        *(.phys.text)\n        _boot_stack_bottom = .;\n        . = . + 2K;\n        . = ALIGN(4K);\n        _boot_stack_top = .;\n        *(.phys)\n        *(.phys.*)\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .boot . : AT(ADDR(.boot) - KERNEL_OFFSET)\n    {\n        *(.boot.text)\n        *(.boot.data)\n        . = ALIGN(4K);\n    }\n\n    ki_boot_end = .;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        *(.text)\n    }\n\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    .ehframe : AT(ADDR(.ehframe) - KERNEL_OFFSET)\n    {\n        _ehframe = .;\n        *(.eh_frame)\n        . = ALIGN(4K);\n    }\n\n    . = ALIGN(4K);\n    ki_end = .;\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n    }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"504bea9e73eaa9c3a140736ba20b4b014ccfda7e","subject":"Carve things up - half of flash for the supervisor, 1\/4 of the ram.","message":"Carve things up - half of flash for the supervisor, 1\/4 of the ram.","repos":"rbsexton\/gecko,rbsexton\/gecko,rbsexton\/gecko","old_file":"leopard\/usb\/efm32lg.ld","new_file":"leopard\/usb\/efm32lg.ld","new_contents":"\/* Linker script for Silicon Labs EFM32LG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 4.1.0 *\/\r\n\/*                                                                  *\/\r\n\r\nMEMORY\r\n{\r\n  \/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144 *\/\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 131072\r\n  \/* RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768 *\/\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 8192\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.vectors))\r\n    __Vectors_End = .;\r\n    __Vectors_Size = __Vectors_End - __Vectors;\r\n    __end__ = .;\r\n\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  \/* To copy multiple ROM to RAM sections,\r\n   * uncomment .copy.table section and,\r\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .copy.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __copy_table_start__ = .;\r\n    LONG (__etext)\r\n    LONG (__data_start__)\r\n    LONG (__data_end__ - __data_start__)\r\n    LONG (__etext2)\r\n    LONG (__data2_start__)\r\n    LONG (__data2_end__ - __data2_start__)\r\n    __copy_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  \/* To clear multiple BSS sections,\r\n   * uncomment .zero.table section and,\r\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .zero.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __zero_table_start__ = .;\r\n    LONG (__bss_start__)\r\n    LONG (__bss_end__ - __bss_start__)\r\n    LONG (__bss2_start__)\r\n    LONG (__bss2_end__ - __bss2_start__)\r\n    __zero_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap (COPY):\r\n  {\r\n    __HeapBase = .;\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    KEEP(*(.heap*))\r\n    __HeapLimit = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy (COPY):\r\n  {\r\n    KEEP(*(.stack*))\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","old_contents":"\/* Linker script for Silicon Labs EFM32LG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 4.1.0 *\/\r\n\/*                                                                  *\/\r\n\r\nMEMORY\r\n{\r\n  \/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144 *\/\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128072\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.vectors))\r\n    __Vectors_End = .;\r\n    __Vectors_Size = __Vectors_End - __Vectors;\r\n    __end__ = .;\r\n\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  \/* To copy multiple ROM to RAM sections,\r\n   * uncomment .copy.table section and,\r\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .copy.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __copy_table_start__ = .;\r\n    LONG (__etext)\r\n    LONG (__data_start__)\r\n    LONG (__data_end__ - __data_start__)\r\n    LONG (__etext2)\r\n    LONG (__data2_start__)\r\n    LONG (__data2_end__ - __data2_start__)\r\n    __copy_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  \/* To clear multiple BSS sections,\r\n   * uncomment .zero.table section and,\r\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .zero.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __zero_table_start__ = .;\r\n    LONG (__bss_start__)\r\n    LONG (__bss_end__ - __bss_start__)\r\n    LONG (__bss2_start__)\r\n    LONG (__bss2_end__ - __bss2_start__)\r\n    __zero_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap (COPY):\r\n  {\r\n    __HeapBase = .;\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    KEEP(*(.heap*))\r\n    __HeapLimit = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy (COPY):\r\n  {\r\n    KEEP(*(.stack*))\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f72e62645dbb8caa06121b854a09801802a2b17f","subject":"Trivial: formatting changes made as requested.  See rb808.","message":"Trivial: formatting changes made as requested.  See rb808.\n\nSigned-off by: Eli Sennesh <esennesh@leaflabs.com>\n","repos":"projectara\/bootrom,gregkh\/bootrom","old_file":"chips\/tsb\/scripts\/common.ld","new_file":"chips\/tsb\/scripts\/common.ld","new_contents":"\n_workram_start = ORIGIN(sram);\n_workram_end = ORIGIN(sram) + LENGTH(sram);\n\n_resume_address_size = 8;\n_communication_area_size = 200; \/* except for resume address *\/\n\n_resume_address = _workram_end - _resume_address_size;\n_communication_area = _resume_address - _communication_area_size;\n_stack_top = _communication_area;\n\n\/* The high 12kB is used for boot ROM .data, .bss, stack and communication.\n   May need to revisit the number later. *\/\n_bootrom_data_area = ORIGIN(sram) + LENGTH(sram) - 12k;\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nSECTIONS\n{\n\n   \/* \n    * bootstrap sections are meant to contain input sections only when building \n    * with SPIROM+JTAG dual-image targets such as es1tsb.  In all other\n    * circumstances, such as when building for ES3's actual ROM, they must be\n    * empty.\n    *\/\n\t.bootstrap.loader : {\n\t\t*(.bootstrap.loader)\n\t\t_spi_stext = ABSOLUTE(.);\n\t} > rom\n\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > REGION_TEXT AT > rom\n\n\t_stext_lma = LOADADDR(.text);\n\t_text_size = SIZEOF(.text);\n\n\t.data (_bootrom_data_area): {\n\t\t_sdata = ALIGN(4);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\t_edata = ALIGN(4);\n\t} > sram AT > rom\n\n\t_data_in_rom = LOADADDR(.data);\n\n   \/* \n    * bootstrap sections are meant to contain input sections only when building\n    * with SPIROM+JTAG dual-image targets such as es1tsb.  In all other\n    * circumstances, such as when building for ES3's actual ROM, they must be\n    * empty.\n    *\/\n\t.bootstrap :  {\n\t\t*(.bootstrap)\n\t} > REGION_TEXT AT > rom\n\n\t_bootstrap_lma = LOADADDR(.bootstrap);\n\t_bootstrap_vma = ADDR(.bootstrap);\n\t_bootstrap_size = SIZEOF(.bootstrap);\n\n\t.bss ALIGN(4): {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t_ebss = ABSOLUTE(.);\n\t} > sram\n}\n","old_contents":"\n_workram_start = ORIGIN(sram);\n_workram_end = ORIGIN(sram) + LENGTH(sram);\n\n_resume_address_size = 8;\n_communication_area_size = 200; \/* except for resume address *\/\n\n_resume_address = _workram_end - _resume_address_size;\n_communication_area = _resume_address - _communication_area_size;\n_stack_top = _communication_area;\n\n\/* The high 12kB is used for boot ROM .data, .bss, stack and communication.\n   May need to revisit the number later. *\/\n_bootrom_data_area = ORIGIN(sram) + LENGTH(sram) - 12k;\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nSECTIONS\n{\n\n   \/* bootstrap sections are meant to contain input sections only when building \n    * with SPIROM+JTAG dual-image targets such as es1tsb.  In all other \n    * circumstances, such as when building for ES3's actual ROM, they must be \n    * empty. *\/\n\t.bootstrap.loader : {\n\t\t*(.bootstrap.loader)\n\t\t_spi_stext = ABSOLUTE(.);\n\t} > rom\n\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > REGION_TEXT AT > rom\n\n\t_stext_lma = LOADADDR(.text);\n\t_text_size = SIZEOF(.text);\n\n\t.data (_bootrom_data_area): {\n\t\t_sdata = ALIGN(4);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\t_edata = ALIGN(4);\n\t} > sram AT > rom\n\n\t_data_in_rom = LOADADDR(.data);\n\n   \/* bootstrap sections are meant to contain input sections only when building \n    * with SPIROM+JTAG dual-image targets such as es1tsb.  In all other \n    * circumstances, such as when building for ES3's actual ROM, they must be \n    * empty. *\/\n\t.bootstrap :  {\n\t\t*(.bootstrap)\n\t} > REGION_TEXT AT > rom\n\n\t_bootstrap_lma = LOADADDR(.bootstrap);\n\t_bootstrap_vma = ADDR(.bootstrap);\n\t_bootstrap_size = SIZEOF(.bootstrap);\n\n\t.bss ALIGN(4): {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t_ebss = ABSOLUTE(.);\n\t} > sram\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"81e7608c037ca80142db7484b27db7d7ac614d46","subject":"arm: tz: secure_entry_functions.ld: Fix NSC_ALIGN for nRF devices","message":"arm: tz: secure_entry_functions.ld: Fix NSC_ALIGN for nRF devices\n\nIf the location counter ('.') is within the area that the veneers\nshould go, the current solution will give a linker error (\"Cannot move\nlocation counter backwards\"). This patch places the veneers in the next\nSPU region in this case.\n\nSigned-off-by: \u00d8yvind R\u00f8nningstad <5f9e1eedbdafebd99226f1498f634e1047455d88@nordicsemi.no>\n","repos":"nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,Vudentz\/zephyr","old_file":"arch\/arm\/core\/aarch32\/cortex_m\/tz\/secure_entry_functions.ld","new_file":"arch\/arm\/core\/aarch32\/cortex_m\/tz\/secure_entry_functions.ld","new_contents":"\/*\n * Copyright (c) 2019 Nordic Semiconductor ASA\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* nRF-specific defines. *\/\n#if defined(CONFIG_CPU_HAS_NRF_IDAU) && CONFIG_ARM_NSC_REGION_BASE_ADDRESS == 0\n\t\/* This SOC needs the NSC region to be at the end of an SPU region. *\/\n\t#define __NSC_ALIGN (ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE) \\\n\t\t\t- MAX(32, (1 << LOG2CEIL(__sg_size))))\n\t#define NSC_ALIGN \\\n\t\t. =  (__NSC_ALIGN + ((ABSOLUTE(.) > __NSC_ALIGN) \\\n\t\t\t\t? CONFIG_NRF_SPU_FLASH_REGION_SIZE : 0))\n\t#define NSC_ALIGN_END . = ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE)\n#endif \/* CONFIG_CPU_HAS_NRF_IDAU && CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n\n#ifndef NSC_ALIGN\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS *\/\n#endif \/* !NSC_ALIGN *\/\n\n#ifndef NSC_ALIGN_END\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n\/* nRF-specific ASSERT. *\/\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NRF_SG_START (__sg_start % CONFIG_NRF_SPU_FLASH_REGION_SIZE)\n\t#define NRF_SG_SIZE (CONFIG_NRF_SPU_FLASH_REGION_SIZE - NRF_SG_START)\n\tASSERT((__sg_size == 0)\n\t\t|| (((1 << LOG2CEIL(NRF_SG_SIZE)) == NRF_SG_SIZE) \/* Pow of 2 *\/\n\t\t\t&& (NRF_SG_SIZE >= 32)\n\t\t\t&& (NRF_SG_SIZE <= 4096)),\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n","old_contents":"\/*\n * Copyright (c) 2019 Nordic Semiconductor ASA\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* nRF-specific defines. *\/\n#if defined(CONFIG_CPU_HAS_NRF_IDAU) && CONFIG_ARM_NSC_REGION_BASE_ADDRESS == 0\n\t\/* This SOC needs the NSC region to be at the end of an SPU region. *\/\n\t#define NSC_ALIGN \\\n\t\t. = ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE) \\\n\t\t\t- (1 << LOG2CEIL(__sg_size))\n\t#define NSC_ALIGN_END . = ALIGN(CONFIG_NRF_SPU_FLASH_REGION_SIZE)\n#endif \/* CONFIG_CPU_HAS_NRF_IDAU && CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n\n#ifndef NSC_ALIGN\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS *\/\n#endif \/* !NSC_ALIGN *\/\n\n#ifndef NSC_ALIGN_END\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n\/* nRF-specific ASSERT. *\/\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NRF_SG_START (__sg_start % CONFIG_NRF_SPU_FLASH_REGION_SIZE)\n\t#define NRF_SG_SIZE (CONFIG_NRF_SPU_FLASH_REGION_SIZE - NRF_SG_START)\n\tASSERT((__sg_size == 0)\n\t\t|| (((1 << LOG2CEIL(NRF_SG_SIZE)) == NRF_SG_SIZE) \/* Pow of 2 *\/\n\t\t\t&& (NRF_SG_SIZE >= 32)\n\t\t\t&& (NRF_SG_SIZE <= 4096)),\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"11957840e8ab7496ba87867fd73de38134a3fbbc","subject":"esp8266: Update 512k linker script, renaming modpyb to machine.","message":"esp8266: Update 512k linker script, renaming modpyb to machine.\n","repos":"deshipu\/micropython,ryannathans\/micropython,torwag\/micropython,puuu\/micropython,jmarcelino\/pycom-micropython,adafruit\/circuitpython,TDAbboud\/micropython,micropython\/micropython-esp32,tralamazza\/micropython,selste\/micropython,HenrikSolver\/micropython,Peetz0r\/micropython-esp32,trezor\/micropython,Peetz0r\/micropython-esp32,mhoffma\/micropython,ryannathans\/micropython,bvernoux\/micropython,MrSurly\/micropython,Peetz0r\/micropython-esp32,matthewelse\/micropython,blazewicz\/micropython,HenrikSolver\/micropython,mhoffma\/micropython,selste\/micropython,deshipu\/micropython,toolmacher\/micropython,henriknelson\/micropython,MrSurly\/micropython-esp32,dmazzella\/micropython,ryannathans\/micropython,matthewelse\/micropython,chrisdearman\/micropython,alex-robbins\/micropython,puuu\/micropython,pramasoul\/micropython,cwyark\/micropython,toolmacher\/micropython,matthewelse\/micropython,PappaPeppar\/micropython,toolmacher\/micropython,chrisdearman\/micropython,cwyark\/micropython,swegener\/micropython,selste\/micropython,TDAbboud\/micropython,blazewicz\/micropython,adafruit\/micropython,torwag\/micropython,bvernoux\/micropython,Peetz0r\/micropython-esp32,PappaPeppar\/micropython,pramasoul\/micropython,trezor\/micropython,infinnovation\/micropython,TDAbboud\/micropython,tobbad\/micropython,lowRISC\/micropython,mhoffma\/micropython,SHA2017-badge\/micropython-esp32,MrSurly\/micropython-esp32,chrisdearman\/micropython,MrSurly\/micropython-esp32,lowRISC\/micropython,chrisdearman\/micropython,HenrikSolver\/micropython,puuu\/micropython,cwyark\/micropython,SHA2017-badge\/micropython-esp32,TDAbboud\/micropython,tralamazza\/micropython,pfalcon\/micropython,oopy\/micropython,swegener\/micropython,pfalcon\/micropython,MrSurly\/micropython,micropython\/micropython-esp32,bvernoux\/micropython,pozetroninc\/micropython,hiway\/micropython,pozetroninc\/micropython,AriZuu\/micropython,Timmenem\/micropython,adafruit\/micropython,torwag\/micropython,oopy\/micropython,jmarcelino\/pycom-micropython,mhoffma\/micropython,Timmenem\/micropython,blazewicz\/micropython,lowRISC\/micropython,HenrikSolver\/micropython,adafruit\/circuitpython,adafruit\/micropython,jmarcelino\/pycom-micropython,PappaPeppar\/micropython,dmazzella\/micropython,AriZuu\/micropython,MrSurly\/micropython,matthewelse\/micropython,MrSurly\/micropython,trezor\/micropython,Peetz0r\/micropython-esp32,trezor\/micropython,oopy\/micropython,pfalcon\/micropython,micropython\/micropython-esp32,AriZuu\/micropython,micropython\/micropython-esp32,mhoffma\/micropython,tuc-osg\/micropython,MrSurly\/micropython,pramasoul\/micropython,deshipu\/micropython,dmazzella\/micropython,adafruit\/micropython,swegener\/micropython,kerneltask\/micropython,alex-robbins\/micropython,pozetroninc\/micropython,micropython\/micropython-esp32,alex-robbins\/micropython,tobbad\/micropython,swegener\/micropython,pfalcon\/micropython,tobbad\/micropython,matthewelse\/micropython,ryannathans\/micropython,Timmenem\/micropython,tobbad\/micropython,toolmacher\/micropython,alex-robbins\/micropython,deshipu\/micropython,hiway\/micropython,bvernoux\/micropython,hiway\/micropython,MrSurly\/micropython-esp32,tuc-osg\/micropython,oopy\/micropython,matthewelse\/micropython,blazewicz\/micropython,HenrikSolver\/micropython,MrSurly\/micropython-esp32,adafruit\/circuitpython,oopy\/micropython,hiway\/micropython,henriknelson\/micropython,pramasoul\/micropython,SHA2017-badge\/micropython-esp32,SHA2017-badge\/micropython-esp32,torwag\/micropython,tuc-osg\/micropython,tobbad\/micropython,selste\/micropython,jmarcelino\/pycom-micropython,puuu\/micropython,kerneltask\/micropython,Timmenem\/micropython,pozetroninc\/micropython,Timmenem\/micropython,lowRISC\/micropython,infinnovation\/micropython,puuu\/micropython,cwyark\/micropython,chrisdearman\/micropython,bvernoux\/micropython,henriknelson\/micropython,deshipu\/micropython,adafruit\/circuitpython,adafruit\/micropython,hiway\/micropython,kerneltask\/micropython,henriknelson\/micropython,tralamazza\/micropython,tuc-osg\/micropython,pfalcon\/micropython,SHA2017-badge\/micropython-esp32,pramasoul\/micropython,PappaPeppar\/micropython,selste\/micropython,kerneltask\/micropython,infinnovation\/micropython,AriZuu\/micropython,blazewicz\/micropython,jmarcelino\/pycom-micropython,tralamazza\/micropython,tuc-osg\/micropython,lowRISC\/micropython,torwag\/micropython,ryannathans\/micropython,PappaPeppar\/micropython,adafruit\/circuitpython,dmazzella\/micropython,toolmacher\/micropython,TDAbboud\/micropython,alex-robbins\/micropython,AriZuu\/micropython,trezor\/micropython,henriknelson\/micropython,cwyark\/micropython,pozetroninc\/micropython,adafruit\/circuitpython,swegener\/micropython,infinnovation\/micropython,kerneltask\/micropython,infinnovation\/micropython","old_file":"esp8266\/esp8266_512k.ld","new_file":"esp8266\/esp8266_512k.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40209000, len = 0x72000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        build\/main.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40209000, len = 0x72000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        build\/main.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybuart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *modmachinewdt.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modpybhspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"31ad52336b1d025216768dae73af8dd724d33c83","subject":"soc: riscv: telink_b91: fix required headers","message":"soc: riscv: telink_b91: fix required headers\n\nThe linker script is using the DT API, which was previously included via\n<soc.h>.\n\nSigned-off-by: Gerard Marull-Paretas <bedb45f43a286e49f4dcda039a436b216ae61ef3@nordicsemi.no>\n","repos":"finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr","old_file":"soc\/riscv\/riscv-privilege\/telink_b91\/linker.ld","new_file":"soc\/riscv\/riscv-privilege\/telink_b91\/linker.ld","new_contents":"\/*\n * Copyright (c) 2021 Telink Semiconductor\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @brief Linker script for the Telink B91 SoC\n *\/\n\n#include <autoconf.h>\n#include <devicetree.h>\n#include <linker\/linker-tool.h>\n\nMEMORY\n{\n\tROM_INIT (rx)  : ORIGIN = DT_REG_ADDR(DT_CHOSEN(zephyr_flash)), LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n\tRAM_ILM  (rwx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ram_ilm)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ram_ilm))\n}\n\nSECTIONS\n{\n\tSECTION_PROLOGUE(vector,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init.*))\n\t} GROUP_LINK_IN(ROM_INIT)\n}\n\n#include <arch\/riscv\/common\/linker.ld>\n\nSECTIONS\n{\n\tSECTION_DATA_PROLOGUE(retention_data,,)\n\t{\n\t\t. = ALIGN(8);\n\t\t*(.retention_data)\n\t\t*(\".retention_data.*\")\n\n\t\tPROVIDE (_RETENTION_DATA_VMA_END = .);\n\t\tPROVIDE (_RETENTION_DATA_VMA_START = ADDR(retention_data));\n\t\tPROVIDE (_RETENTION_DATA_LMA_START = LOADADDR(retention_data));\n\t} GROUP_DATA_LINK_IN(RAM_ILM, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(ram_code,,)\n\t{\n\t\t. = ALIGN(8);\n\t\t*(.ram_code)\n\t\t*(\".ram_code.*\")\n\n\t\tPROVIDE (_RAMCODE_VMA_END = .);\n\t\tPROVIDE (_RAMCODE_VMA_START = ADDR(ram_code));\n\t\tPROVIDE (_RAMCODE_LMA_START = LOADADDR(ram_code));\n\t} GROUP_DATA_LINK_IN(RAM_ILM, ROMABLE_REGION)\n}\n","old_contents":"\/*\n * Copyright (c) 2021 Telink Semiconductor\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @brief Linker script for the Telink B91 SoC\n *\/\n\n#include <soc.h>\n#include <autoconf.h>\n#include <linker\/linker-tool.h>\n\nMEMORY\n{\n\tROM_INIT (rx)  : ORIGIN = DT_REG_ADDR(DT_CHOSEN(zephyr_flash)), LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n\tRAM_ILM  (rwx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ram_ilm)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ram_ilm))\n}\n\nSECTIONS\n{\n\tSECTION_PROLOGUE(vector,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init.*))\n\t} GROUP_LINK_IN(ROM_INIT)\n}\n\n#include <arch\/riscv\/common\/linker.ld>\n\nSECTIONS\n{\n\tSECTION_DATA_PROLOGUE(retention_data,,)\n\t{\n\t\t. = ALIGN(8);\n\t\t*(.retention_data)\n\t\t*(\".retention_data.*\")\n\n\t\tPROVIDE (_RETENTION_DATA_VMA_END = .);\n\t\tPROVIDE (_RETENTION_DATA_VMA_START = ADDR(retention_data));\n\t\tPROVIDE (_RETENTION_DATA_LMA_START = LOADADDR(retention_data));\n\t} GROUP_DATA_LINK_IN(RAM_ILM, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(ram_code,,)\n\t{\n\t\t. = ALIGN(8);\n\t\t*(.ram_code)\n\t\t*(\".ram_code.*\")\n\n\t\tPROVIDE (_RAMCODE_VMA_END = .);\n\t\tPROVIDE (_RAMCODE_VMA_START = ADDR(ram_code));\n\t\tPROVIDE (_RAMCODE_LMA_START = LOADADDR(ram_code));\n\t} GROUP_DATA_LINK_IN(RAM_ILM, ROMABLE_REGION)\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c21b792f54525fd03e4098d05fd7a53140059509","subject":"Add .sbss section to .bss section","message":"Add .sbss section to .bss section\n\nThis is a special section that RISC-V uses (see the comment in\nthe Tock board linker)\n","repos":"tock\/libtock-rs","old_file":"layout_generic.ld","new_file":"layout_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * Currently, due to incomplete ROPI-RWPI support in rustc (see\n * https:\/\/github.com\/tock\/libtock-rs\/issues\/28), this layout implements static\n * linking. An application init script must define the FLASH and SRAM address\n * ranges as well as MPU_MIN_ALIGN before including this layout file.\n *\n * Here is a an example application linker script to get started:\n *     MEMORY {\n *         \/* FLASH memory region must start immediately *after* the Tock\n *          * Binary Format headers, which means you need to offset the\n *          * beginning of FLASH memory region relative to where the\n *          * application is loaded.\n *         FLASH (rx) : ORIGIN = 0x10030, LENGTH = 0x0FFD0\n *         SRAM (RWX) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     STACK_SIZE = 2048;\n *     MPU_MIN_ALIGN = 8K;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n        \/* Pad the header out to a multiple of 32 bytes so there is not a gap\n         * between the header and subsequent .data section. It's unclear why,\n         * but LLD is aligning sections to a multiple of 32 bytes. *\/\n        . = ALIGN(32);\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _etext = .;\n    } > FLASH =0xFF\n\n    \/* Application stack *\/\n    .stack :\n    {\n        . = . + STACK_SIZE;\n\n\t_stack_top_unaligned = .;\n        . = ALIGN(8);\n\t_stack_top_aligned = .;\n    } > SRAM\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data : AT (_etext)\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss* .sbss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT((_stack_top_aligned - _stack_top_unaligned) == 0, \"\nSTACK_SIZE must be 8 byte multiple\")\n","old_contents":"\/* Userland Generic Layout\n *\n * Currently, due to incomplete ROPI-RWPI support in rustc (see\n * https:\/\/github.com\/tock\/libtock-rs\/issues\/28), this layout implements static\n * linking. An application init script must define the FLASH and SRAM address\n * ranges as well as MPU_MIN_ALIGN before including this layout file.\n *\n * Here is a an example application linker script to get started:\n *     MEMORY {\n *         \/* FLASH memory region must start immediately *after* the Tock\n *          * Binary Format headers, which means you need to offset the\n *          * beginning of FLASH memory region relative to where the\n *          * application is loaded.\n *         FLASH (rx) : ORIGIN = 0x10030, LENGTH = 0x0FFD0\n *         SRAM (RWX) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     STACK_SIZE = 2048;\n *     MPU_MIN_ALIGN = 8K;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n        \/* Pad the header out to a multiple of 32 bytes so there is not a gap\n         * between the header and subsequent .data section. It's unclear why,\n         * but LLD is aligning sections to a multiple of 32 bytes. *\/\n        . = ALIGN(32);\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _etext = .;\n    } > FLASH =0xFF\n\n    \/* Application stack *\/\n    .stack :\n    {\n        . = . + STACK_SIZE;\n\n\t_stack_top_unaligned = .;\n        . = ALIGN(8);\n\t_stack_top_aligned = .;\n    } > SRAM\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data : AT (_etext)\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT((_stack_top_aligned - _stack_top_unaligned) == 0, \"\nSTACK_SIZE must be 8 byte multiple\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2b9a95d24a3ae0ae59483dc4c1836ca8c69b0fb4","subject":"more linker improvements","message":"more linker improvements\n","repos":"jezze\/fudge,jezze\/fudge,jezze\/fudge","old_file":"modules\/linker.ld","new_file":"modules\/linker.ld","new_contents":"SECTIONS\n{\n\n    .text ALIGN (0x1000) :\n    {\n        *(.text)\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        *(.rodata*)\n        *(.data)\n    }\n\n    .bss :\n    {\n        *(.bss)\n    }\n\n}\n","old_contents":"SECTIONS\n{\n\n    .text :\n    {\n        *(.text)\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        *(.data)\n        *(.rodata)\n        *(.bss)\n    }\n\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3aeb9a2e8017d99bc2ae4f410e099856a0e01a20","subject":"[sw] Fix spelling mistake in a comment","message":"[sw] Fix spelling mistake in a comment\n\nSigned-off-by: Miguel Young de la Sota <71b8e7f4945fd97b98544cf897992af89646547a@google.com>\n","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan","old_file":"sw\/device\/info_sections.ld","new_file":"sw\/device\/info_sections.ld","new_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * Partial Linker Script for OpenTitan Device Executables\n *\n * This Linker Script controls all the sections that we need in the ELF file for\n * a device executable, but which are not mapped into memory or otherwise\n * allocated on the device itself.\n *\n * These contain amongst other things:\n * - debugging information needed by DV logging,\n * - DWARF Sections\n * - RISC-V Attributes sections\n *\n * This is also where we specify the sections to discard, because it is a common\n * file between all our other linker scripts.\n *\n * This partial linker script requires the main linker script to define the\n * following symbols:\n * - _dv_log_offset\n *\/\n\n\/*\n * Start DV Sections.\n *\n * The following sections are used by DV to implement logging in an\n * alternate way, which enables simulation speed up by completely avoiding\n * any string format processing or even the actual transmission of log data\n * to a real peripheral.\n *\n * These sections are marked as dummy so that they can still be extracted\n * using readelf or similar utilities. As such, the content in these sections\n * is not relevant for the actual SW code and can be safely discarded.\n *\/\n\n\/**\n * The following section contains log fields constructed from the logs using\n * the log_fields_t struct defined in sw\/device\/lib\/runtime\/log.h. The size of\n * each log field is fixed - 20 bytes.\n *\/\n.logs.fields _dv_log_offset (INFO): {\n  \/* Force this section to always be emitted. The logs extraction script expects\n   * this section to be present in the ELF file, but the linker will not emit it\n   * if there are no outputs (i.e, the *(.logs.fields) statement) with contents.\n   *\n   * However, almost any assignment will implicitly create even an empty section,\n   * including the very silly . = . (set the program counter to itself).\n   * \n   * See https:\/\/sourceware.org\/binutils\/docs-2.29\/ld\/Output-Section-Discarding.html. *\/\n  . = .;\n  *(.logs.fields)\n}\n\n\/*\n * End DV Sections\n *\/\n\n\/* ELF-internal Sections. *\/\n.symtab 0x0 : { *(.symtab) }\n.strtab 0x0 : { *(.strtab) }\n.shstrtab 0x0 : { *(.shstrtab) }\n\n\/* Preserve RISC-V Attributes *\/\n.riscv.attributes 0x0 : { *(.riscv.attributes) }\n\n\/* Preserve Debug Info in ELF Files *\/\n.debug_info 0x0 : { *(.debug_info) }\n.debug_abbrev 0x0 : { *(.debug_abbrev) }\n.debug_aranges 0x0 : { *(.debug_aranges) }\n.debug_line 0x0 : { *(.debug_line) }\n.debug_loc 0x0 : { *(.debug_loc) }\n.debug_ranges 0x0 : { *(.debug_ranges) }\n.debug_str 0x0 : { *(.debug_str) }\n.debug_frame 0x0 : { *(.debug_frame) }\n.debug_line_str 0x0 : { *(.debug_line_str) }\n.debug_loclists 0x0 : { *(.debug_loclists) }\n.debug_rnglists 0x0 : { *(.debug_rnglists) }\n\n\/* Discarded Sections (Not needed in device images). *\/\n\/DISCARD\/ : {\n  \/* We don't keep unwind information *\/\n  *(.eh_frame)\n  *(.eh_frame_hdr)\n\n  \/* Compiler Information *\/\n  *(.comment)\n  *(.comment.*)\n\n  \/* Other Notes *\/\n  *(.note)\n  *(.note.*)\n\n  \/* Relocations *\/\n  *(.rela.*)\n  *(.rela.dyn)\n\n  \/* STAB Debugging Info - We Use DWARF *\/\n  *(.stab)\n  *(.stab.*)\n  *(.stabstr)\n\n  \/* COMMON Sections *\/\n  *(COMMON)\n}\n","old_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * Partial Linker Script for OpenTitan Device Executables\n *\n * This Linker Script controls all the sections that we need in the ELF file for\n * a device executable, but which are not mapped into memory or otherwise\n * allocated on the device itself.\n *\n * These contain amongst other things:\n * - debugging information needed by DV logging,\n * - DWARF Sections\n * - RISC-V Attributes sections\n *\n * This is also where we specify the sections to discard, because it is a common\n * file between all our other linker scripts.\n *\n * This partial linker script requires the main linker script to define the\n * following symbols:\n * - _dv_log_offset\n *\/\n\n\/*\n * Start DV Sections.\n *\n * The following sections are used by DV to implement logging in an\n * alternate way, which enables simulation speed up by completely avoiding\n * any string format processing or even the actual transmission of log data\n * to a real peripheral.\n *\n * These sections are marked as dummy so that they can still be extracted\n * using readelf or similar utilities. As such, the content in these sections\n * is not relevant for the actual SW code and can be safely discarded.\n *\/\n\n\/**\n * The following section contains log fields constructed from the logs using\n * the log_fields_t struct defined in sw\/device\/lib\/runtime\/log.h. The size of\n * each log field is fixed - 20 bytes.\n *\/\n.logs.fields _dv_log_offset (INFO): {\n  \/* Force this section to always be emitted. The logs extraction script expects\n   * this section to be present in the ELF file, but the linker will not emit it\n   * if there are no outputs (ie.e, the *(.logs.fields) statement) with contents.\n   *\n   * However, almost any assignment will implicitly create even an empty section,\n   * including the very silly . = . (set the program counter to itself).\n   * \n   * See https:\/\/sourceware.org\/binutils\/docs-2.29\/ld\/Output-Section-Discarding.html. *\/\n  . = .;\n  *(.logs.fields)\n}\n\n\/*\n * End DV Sections\n *\/\n\n\/* ELF-internal Sections. *\/\n.symtab 0x0 : { *(.symtab) }\n.strtab 0x0 : { *(.strtab) }\n.shstrtab 0x0 : { *(.shstrtab) }\n\n\/* Preserve RISC-V Attributes *\/\n.riscv.attributes 0x0 : { *(.riscv.attributes) }\n\n\/* Preserve Debug Info in ELF Files *\/\n.debug_info 0x0 : { *(.debug_info) }\n.debug_abbrev 0x0 : { *(.debug_abbrev) }\n.debug_aranges 0x0 : { *(.debug_aranges) }\n.debug_line 0x0 : { *(.debug_line) }\n.debug_loc 0x0 : { *(.debug_loc) }\n.debug_ranges 0x0 : { *(.debug_ranges) }\n.debug_str 0x0 : { *(.debug_str) }\n.debug_frame 0x0 : { *(.debug_frame) }\n.debug_line_str 0x0 : { *(.debug_line_str) }\n.debug_loclists 0x0 : { *(.debug_loclists) }\n.debug_rnglists 0x0 : { *(.debug_rnglists) }\n\n\/* Discarded Sections (Not needed in device images). *\/\n\/DISCARD\/ : {\n  \/* We don't keep unwind information *\/\n  *(.eh_frame)\n  *(.eh_frame_hdr)\n\n  \/* Compiler Information *\/\n  *(.comment)\n  *(.comment.*)\n\n  \/* Other Notes *\/\n  *(.note)\n  *(.note.*)\n\n  \/* Relocations *\/\n  *(.rela.*)\n  *(.rela.dyn)\n\n  \/* STAB Debugging Info - We Use DWARF *\/\n  *(.stab)\n  *(.stab.*)\n  *(.stabstr)\n\n  \/* COMMON Sections *\/\n  *(COMMON)\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ecb24e55bf39fbae2d12329c6215470eda031562","subject":"cpu\/stm32f103cb: generalized linkerscript","message":"cpu\/stm32f103cb: generalized linkerscript\n","repos":"gebart\/RIOT,jasonatran\/RIOT,BytesGalore\/RIOT,ks156\/RIOT,jbeyerstedt\/RIOT-OTA-update,OTAkeys\/RIOT,syin2\/RIOT,Hyungsin\/RIOT-OS,adrianghc\/RIOT,ks156\/RIOT,TobiasFredersdorf\/RIOT,Josar\/RIOT,kerneltask\/RIOT,neumodisch\/RIOT,hamilton-mote\/RIOT-OS,biboc\/RIOT,katezilla\/RIOT,dailab\/RIOT,TobiasFredersdorf\/RIOT,avmelnikoff\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,A-Paul\/RIOT,syin2\/RIOT,thomaseichinger\/RIOT,Ell-i\/RIOT,RIOT-OS\/RIOT,TobiasFredersdorf\/RIOT,dkm\/RIOT,A-Paul\/RIOT,neiljay\/RIOT,miri64\/RIOT,rfuentess\/RIOT,rfuentess\/RIOT,x3ro\/RIOT,jasonatran\/RIOT,jfischer-phytec-iot\/RIOT,biboc\/RIOT,neiljay\/RIOT,Ell-i\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,tfar\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,immesys\/RiSyn,foss-for-synopsys-dwc-arc-processors\/RIOT,backenklee\/RIOT,basilfx\/RIOT,dailab\/RIOT,lazytech-org\/RIOT,OlegHahm\/RIOT,kb2ma\/RIOT,kaleb-himes\/RIOT,miri64\/RIOT,adjih\/RIOT,plushvoxel\/RIOT,immesys\/RiSyn,roberthartung\/RIOT,kYc0o\/RIOT,mfrey\/RIOT,smlng\/RIOT,toonst\/RIOT,Josar\/RIOT,neumodisch\/RIOT,immesys\/RiSyn,OlegHahm\/RIOT,A-Paul\/RIOT,backenklee\/RIOT,dkm\/RIOT,kbumsik\/RIOT,rfuentess\/RIOT,kbumsik\/RIOT,adrianghc\/RIOT,kaleb-himes\/RIOT,yogo1212\/RIOT,dkm\/RIOT,kYc0o\/RIOT,kerneltask\/RIOT,rfuentess\/RIOT,adjih\/RIOT,kaleb-himes\/RIOT,BytesGalore\/RIOT,biboc\/RIOT,hamilton-mote\/RIOT-OS,kaspar030\/RIOT,Ell-i\/RIOT,lazytech-org\/RIOT,ant9000\/RIOT,kbumsik\/RIOT,basilfx\/RIOT,mfrey\/RIOT,dailab\/RIOT,neumodisch\/RIOT,beurdouche\/RIOT,alignan\/RIOT,Hyungsin\/RIOT-OS,gautric\/RIOT,Ell-i\/RIOT,adjih\/RIOT,smlng\/RIOT,BytesGalore\/RIOT,rfuentess\/RIOT,kaspar030\/RIOT,ks156\/RIOT,avmelnikoff\/RIOT,mtausig\/RIOT,adrianghc\/RIOT,adrianghc\/RIOT,katezilla\/RIOT,avmelnikoff\/RIOT,Josar\/RIOT,mfrey\/RIOT,yogo1212\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,alignan\/RIOT,biboc\/RIOT,beurdouche\/RIOT,tfar\/RIOT,smlng\/RIOT,jasonatran\/RIOT,LudwigKnuepfer\/RIOT,backenklee\/RIOT,kb2ma\/RIOT,authmillenon\/RIOT,gautric\/RIOT,biboc\/RIOT,x3ro\/RIOT,tfar\/RIOT,thomaseichinger\/RIOT,dkm\/RIOT,LudwigKnuepfer\/RIOT,cladmi\/RIOT,josephnoir\/RIOT,jbeyerstedt\/RIOT-OTA-update,x3ro\/RIOT,kerneltask\/RIOT,toonst\/RIOT,gautric\/RIOT,neumodisch\/RIOT,hamilton-mote\/RIOT-OS,alignan\/RIOT,miri64\/RIOT,josephnoir\/RIOT,Josar\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,syin2\/RIOT,LudwigOrtmann\/RIOT,aeneby\/RIOT,kbumsik\/RIOT,ant9000\/RIOT,Hyungsin\/RIOT-OS,authmillenon\/RIOT,mtausig\/RIOT,authmillenon\/RIOT,LudwigKnuepfer\/RIOT,josephnoir\/RIOT,roberthartung\/RIOT,aeneby\/RIOT,lazytech-org\/RIOT,neiljay\/RIOT,neiljay\/RIOT,roberthartung\/RIOT,mtausig\/RIOT,LudwigOrtmann\/RIOT,ks156\/RIOT,plushvoxel\/RIOT,smlng\/RIOT,jbeyerstedt\/RIOT-OTA-update,neumodisch\/RIOT,TobiasFredersdorf\/RIOT,adjih\/RIOT,neumodisch\/RIOT,kYc0o\/RIOT,ks156\/RIOT,yogo1212\/RIOT,mfrey\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,LudwigKnuepfer\/RIOT,katezilla\/RIOT,kaspar030\/RIOT,immesys\/RiSyn,thomaseichinger\/RIOT,dailab\/RIOT,x3ro\/RIOT,dkm\/RIOT,plushvoxel\/RIOT,jfischer-phytec-iot\/RIOT,OTAkeys\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,LudwigOrtmann\/RIOT,toonst\/RIOT,mtausig\/RIOT,OlegHahm\/RIOT,cladmi\/RIOT,miri64\/RIOT,avmelnikoff\/RIOT,katezilla\/RIOT,katezilla\/RIOT,cladmi\/RIOT,LudwigKnuepfer\/RIOT,OlegHahm\/RIOT,toonst\/RIOT,backenklee\/RIOT,kbumsik\/RIOT,gebart\/RIOT,avmelnikoff\/RIOT,kaleb-himes\/RIOT,gebart\/RIOT,adjih\/RIOT,A-Paul\/RIOT,alignan\/RIOT,tfar\/RIOT,cladmi\/RIOT,LudwigOrtmann\/RIOT,beurdouche\/RIOT,ant9000\/RIOT,backenklee\/RIOT,tfar\/RIOT,kaspar030\/RIOT,syin2\/RIOT,dailab\/RIOT,aeneby\/RIOT,LudwigOrtmann\/RIOT,immesys\/RiSyn,hamilton-mote\/RIOT-OS,josephnoir\/RIOT,jfischer-phytec-iot\/RIOT,plushvoxel\/RIOT,yogo1212\/RIOT,Ell-i\/RIOT,basilfx\/RIOT,jbeyerstedt\/RIOT-OTA-update,jasonatran\/RIOT,jasonatran\/RIOT,adrianghc\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,beurdouche\/RIOT,roberthartung\/RIOT,kb2ma\/RIOT,miri64\/RIOT,gebart\/RIOT,gebart\/RIOT,lazytech-org\/RIOT,kb2ma\/RIOT,RIOT-OS\/RIOT,syin2\/RIOT,A-Paul\/RIOT,yogo1212\/RIOT,alignan\/RIOT,kYc0o\/RIOT,plushvoxel\/RIOT,hamilton-mote\/RIOT-OS,lazytech-org\/RIOT,LudwigOrtmann\/RIOT,kerneltask\/RIOT,aeneby\/RIOT,basilfx\/RIOT,immesys\/RiSyn,neiljay\/RIOT,BytesGalore\/RIOT,jfischer-phytec-iot\/RIOT,thomaseichinger\/RIOT,authmillenon\/RIOT,Hyungsin\/RIOT-OS,basilfx\/RIOT,josephnoir\/RIOT,gautric\/RIOT,TobiasFredersdorf\/RIOT,gautric\/RIOT,BytesGalore\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,cladmi\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,kerneltask\/RIOT,Josar\/RIOT,thomaseichinger\/RIOT,ant9000\/RIOT,roberthartung\/RIOT,jfischer-phytec-iot\/RIOT,Hyungsin\/RIOT-OS,toonst\/RIOT,x3ro\/RIOT,jbeyerstedt\/RIOT-OTA-update,mtausig\/RIOT,beurdouche\/RIOT,kYc0o\/RIOT,authmillenon\/RIOT,kaleb-himes\/RIOT,kb2ma\/RIOT,smlng\/RIOT,mfrey\/RIOT","old_file":"cpu\/stm32f1\/ldscripts\/stm32f103cb.ld","new_file":"cpu\/stm32f1\/ldscripts\/stm32f103cb.ld","new_contents":"\/*\n * Copyright (C) 2015 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_stm32f1\n * @{\n *\n * @file\n * @brief           Memory definitions for the STM32F103CB\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x08000000, LENGTH = 128K\n    ram (xrw)   : ORIGIN = 0x20000000, LENGTH = 20K\n    cpuid (r)   : ORIGIN = 0x1ffff7e8, LENGTH = 12\n}\n\n_cpuid_address = ORIGIN(cpuid);\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2015 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_stm32f1\n * @{\n *\n * @file\n * @brief           Memory definitions for the STM32F103CB\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x08005000, LENGTH = 128K-0x5000\n    ram (xrw)   : ORIGIN = 0x20000000, LENGTH = 20K\n    cpuid (r)   : ORIGIN = 0x1ffff7e8, LENGTH = 12\n}\n\n_cpuid_address = ORIGIN(cpuid);\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"f5f33318517376156284705ca5a466001cf3cbe1","subject":"cmsis: add library group to efm32 linker script","message":"cmsis: add library group to efm32 linker script\n\nWithout this, libnosys isn't pulled in. This results in linker errors\nbecause _exit() isn't defined.\n","repos":"crawford\/arm-toolkit,crawford\/arm-toolkit","old_file":"src\/CMSIS\/Device\/ARM\/ARMCM3\/EFM32LG\/Source\/GCC\/efm32lg.ld","new_file":"src\/CMSIS\/Device\/ARM\/ARMCM3\/EFM32LG\/Source\/GCC\/efm32lg.ld","new_contents":"\/* Linker script for Energy Micro EFM32LG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Energy Micro AS, 2012                                            *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768\r\n}\r\n\r\n\/* Library configurations *\/\r\nGROUP(libc.a libm.a libnosys.a)\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n * \r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.isr_vector))\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab : \r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap :\r\n  {\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    *(.heap*)\r\n    __HeapLimit = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy :\r\n  {\r\n    *(.stack)\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","old_contents":"\/* Linker script for Energy Micro EFM32LG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Energy Micro AS, 2012                                            *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n * \r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.isr_vector))\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab : \r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap :\r\n  {\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    *(.heap*)\r\n    __HeapLimit = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy :\r\n  {\r\n    *(.stack)\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d58d803ca77bd5c2a1443cbc0d7af761df80699f","subject":"update alignments","message":"update alignments\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/src\/gcc_arm_flash.ld","new_file":"ARM\/src\/gcc_arm_flash.ld","new_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm_flash.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t__isr_vector = .;\n\t\t\/* At addr zero is the stack pointer *\/\n\t\t\/*LONG(__StackTop);*\/\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect*))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\t\/* in case security config is not defined, fill in default *\/\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xfffffffe);\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : ALIGN(4)\n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t. = ALIGN(4);\n\t__text_end__ = .;\n    __etext = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n\n   \t\/* calculate size to take full range from .data to .bss in case other data sections\n   \t   were inserted in between from outside of this file *\/\n   \t__data_size__ = __bss_start__ - __data_start__ ; \/* SIZEOF(.data);*\/\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __HeapLimit + 4;\/*__StackTop - SIZEOF(.stack_dummy);*\/\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","old_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t__isr_vector = .;\n\t\t\/* At addr zero is the stack pointer *\/\n\t\t\/*LONG(__StackTop);*\/\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect*))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\t\/* in case security config is not defined, fill in default *\/\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xfffffffe);\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : ALIGN(4)\n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\/*\t\t. = ALIGN(4);*\/\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\/*\t\t. = ALIGN(4);*\/\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n\n   \t\/* calculate size to take full range from .data to .bss in case other data sections\n   \t   were inserted in between from outside of this file *\/\n   \t__data_size__ = __bss_start__ - __data_start__ ; \/* SIZEOF(.data);*\/\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __HeapLimit + 4;\/*__StackTop - SIZEOF(.stack_dummy);*\/\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c74c38876473e0913d98e7ad165324a7fa610d9f","subject":"linker: use SECTION_DATA_PROLOGUE for app_smem","message":"linker: use SECTION_DATA_PROLOGUE for app_smem\n\nThis is data and needs the implicit ALIGN_WITH_INPUT that\nis provided with SECTION_DATA_PROLOGUE. Otherwise misalignment\nmay occur if XIP is turned on.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"galak\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr","old_file":"include\/linker\/common-rom.ld","new_file":"include\/linker\/common-rom.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\tSECTION_PROLOGUE(initlevel,,)\n\t{\n\t\t\/*\n\t\t * link in initialization objects for all objects that are\n\t\t * automatically initialized by the kernel; the objects are\n\t\t * sorted in the order they will be initialized (i.e. ordered\n\t\t * by level, sorted by priority within a level)\n\t\t *\/\n\t\t__init_start = .;\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_1)\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_2)\n\t\tCREATE_OBJ_LEVEL(init, POST_KERNEL)\n\t\tCREATE_OBJ_LEVEL(init, APPLICATION)\n\t\tCREATE_OBJ_LEVEL(init, SMP)\n\t\t__init_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && !defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_NAME)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_PROLOGUE(initlevel_error,,)\n\t{\n\t\tKEEP(*(SORT(.init_[_A-Z0-9]*)))\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on word\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n#ifdef CONFIG_64BIT\n\t\t. = ALIGN(8);\n\t\t__CTOR_LIST__ = .;\n\t\tQUAD((__CTOR_END__ - __CTOR_LIST__) \/ 8 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tQUAD(0)\n\t\t__CTOR_END__ = .;\n#else\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array,,)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n#ifdef CONFIG_USERSPACE\n\t\/* Build-time assignment of permissions to kernel objects to\n\t * threads declared with K_THREAD_DEFINE()\n\t *\/\n\tZ_ITERABLE_SECTION_ROM(z_object_assignment, 4)\n#endif\n\n\tSECTION_DATA_PROLOGUE(app_shmem_regions,,)\n\t{\n\t\t__app_shmem_regions_start = .;\n\t\tKEEP(*(SORT(.app_regions.*)));\n\t\t__app_shmem_regions_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SOCKETS)\n\tZ_ITERABLE_SECTION_ROM(net_socket_register, 4)\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n\tZ_ITERABLE_SECTION_ROM(ppp_protocol_handler, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_fixed_chan, 4)\n\n#if defined(CONFIG_BT_BREDR)\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_br_fixed_chan, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_gatt_service_static, 4)\n\n#if defined(CONFIG_EC_HOST_CMD)\n\tZ_ITERABLE_SECTION_ROM(ec_host_cmd_handler, 4)\n#endif\n\n#if defined(CONFIG_SETTINGS)\n\tZ_ITERABLE_SECTION_ROM(settings_handler_static, 4)\n#endif\n\n#if defined(CONFIG_EMUL)\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__emul_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".emulators\")));\n\t\t__emul_list_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_EMUL *\/\n\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__log_const_start = .;\n\t\tKEEP(*(SORT(.log_const_*)));\n\t\t__log_const_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_backends_sections,,)\n\t{\n\t\t__log_backends_start = .;\n\t\tKEEP(*(\"._log_backend.*\"));\n\t\t__log_backends_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(shell, 4)\n\n\tSECTION_DATA_PROLOGUE(shell_root_cmds_sections,,)\n\t{\n\t\t__shell_root_cmds_start = .;\n\t\tKEEP(*(SORT(.shell_root_cmd_*)));\n\t\t__shell_root_cmds_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(font_entry_sections,,)\n\t{\n\t\t__font_entry_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._cfb_font.*\")))\n\t\t__font_entry_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(tracing_backend, 4)\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\tSECTION_PROLOGUE(initlevel,,)\n\t{\n\t\t\/*\n\t\t * link in initialization objects for all objects that are\n\t\t * automatically initialized by the kernel; the objects are\n\t\t * sorted in the order they will be initialized (i.e. ordered\n\t\t * by level, sorted by priority within a level)\n\t\t *\/\n\t\t__init_start = .;\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_1)\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_2)\n\t\tCREATE_OBJ_LEVEL(init, POST_KERNEL)\n\t\tCREATE_OBJ_LEVEL(init, APPLICATION)\n\t\tCREATE_OBJ_LEVEL(init, SMP)\n\t\t__init_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && !defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_NAME)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_PROLOGUE(initlevel_error,,)\n\t{\n\t\tKEEP(*(SORT(.init_[_A-Z0-9]*)))\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on word\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n#ifdef CONFIG_64BIT\n\t\t. = ALIGN(8);\n\t\t__CTOR_LIST__ = .;\n\t\tQUAD((__CTOR_END__ - __CTOR_LIST__) \/ 8 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tQUAD(0)\n\t\t__CTOR_END__ = .;\n#else\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array,,)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n#ifdef CONFIG_USERSPACE\n\t\/* Build-time assignment of permissions to kernel objects to\n\t * threads declared with K_THREAD_DEFINE()\n\t *\/\n\tZ_ITERABLE_SECTION_ROM(z_object_assignment, 4)\n#endif\n\n\tSECTION_PROLOGUE(app_shmem_regions,,)\n\t{\n\t\t__app_shmem_regions_start = .;\n\t\tKEEP(*(SORT(.app_regions.*)));\n\t\t__app_shmem_regions_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SOCKETS)\n\tZ_ITERABLE_SECTION_ROM(net_socket_register, 4)\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n\tZ_ITERABLE_SECTION_ROM(ppp_protocol_handler, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_fixed_chan, 4)\n\n#if defined(CONFIG_BT_BREDR)\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_br_fixed_chan, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_gatt_service_static, 4)\n\n#if defined(CONFIG_EC_HOST_CMD)\n\tZ_ITERABLE_SECTION_ROM(ec_host_cmd_handler, 4)\n#endif\n\n#if defined(CONFIG_SETTINGS)\n\tZ_ITERABLE_SECTION_ROM(settings_handler_static, 4)\n#endif\n\n#if defined(CONFIG_EMUL)\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__emul_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".emulators\")));\n\t\t__emul_list_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_EMUL *\/\n\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__log_const_start = .;\n\t\tKEEP(*(SORT(.log_const_*)));\n\t\t__log_const_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_backends_sections,,)\n\t{\n\t\t__log_backends_start = .;\n\t\tKEEP(*(\"._log_backend.*\"));\n\t\t__log_backends_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(shell, 4)\n\n\tSECTION_DATA_PROLOGUE(shell_root_cmds_sections,,)\n\t{\n\t\t__shell_root_cmds_start = .;\n\t\tKEEP(*(SORT(.shell_root_cmd_*)));\n\t\t__shell_root_cmds_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(font_entry_sections,,)\n\t{\n\t\t__font_entry_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._cfb_font.*\")))\n\t\t__font_entry_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(tracing_backend, 4)\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b0852ef7a2b4c7d4ffc6b87b2bd89dde65029a6e","subject":"nrf\/boards: Update memory.ld to include bootloader offsets.","message":"nrf\/boards: Update memory.ld to include bootloader offsets.\n\nAdding variables that can be set from other linker scripts:\n\n- _bootloader_head_size:\n    Bootloader flash offset in front of the application.\n\n- _bootloader_tail_size:\n    Bootloader offset from the tail of the flash.\n    In case the bootloader is located at the end.\n\n- _bootloader_head_ram_size:\n    Bootloader RAM usage in front of the application.\n\nUpdated calculations of application flash and RAM.\n","repos":"pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython","old_file":"ports\/nrf\/boards\/memory.ld","new_file":"ports\/nrf\/boards\/memory.ld","new_contents":"\n\/* Flash layout: bootloader_head | softdevice     | application     | filesystem    | bootloader_tail *\/\n\/* RAM layout:   bootloader RAM  | softdevice RAM  | application RAM *\/\n_bootloader_head_size = DEFINED(_bootloader_head_size) ? _bootloader_head_size : 0;\n_bootloader_tail_size = DEFINED(_bootloader_tail_size) ? _bootloader_tail_size : 0;\n_bootloader_head_ram_size = DEFINED(_bootloader_head_ram_size) ? _bootloader_head_ram_size : 0;\n_head_size     = DEFINED(_sd_size) ? _sd_size : _bootloader_head_size;\n_head_ram      = DEFINED(_sd_ram)  ? _sd_ram : _bootloader_head_ram_size;\n_sd_size       = DEFINED(_sd_size) ? _sd_size : 0;\n_sd_ram        = DEFINED(_sd_ram)  ? _sd_ram : 0;\n_fs_size       = DEFINED(_fs_size) ? _fs_size : 64K; \/* TODO: set to 0 if not using the filesystem *\/\n_app_size      = _flash_size - _head_size - _fs_size  - _bootloader_tail_size;\n_app_start     = _head_size;\n_fs_start      = _head_size + _app_size;\n_fs_end        = _fs_start + _fs_size;\n_app_ram_start = 0x20000000 + _head_ram;\n_app_ram_size  = _ram_size - _head_ram;\n_heap_start    = _ebss;\n_heap_end      = _ram_end - _stack_size;\n_heap_size     = _heap_end - _heap_start;\n\nASSERT(_heap_size >= _minimum_heap_size, \"not enough RAM left for heap\")\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_TEXT (rx) : ORIGIN = _app_start,     LENGTH = _app_size     \/* app *\/\n    RAM (xrw)       : ORIGIN = _app_ram_start, LENGTH = _app_ram_size\n}\n","old_contents":"\n\/* Flash layout: softdevice     | application     | filesystem *\/\n\/* RAM layout:   softdevice RAM | application RAM *\/\n\n_ram_start     = DEFINED(_ram_start) ? _ram_start : 0x20000000;\n_flash_start   = DEFINED(_flash_start) ? _flash_start : 0;\n_sd_size       = DEFINED(_sd_size) ? _sd_size : _flash_start;\n_sd_ram        = DEFINED(_sd_ram)  ? _sd_ram : 0;\n_fs_size       = DEFINED(_fs_size) ? _fs_size : 64K; \/* TODO: set to 0 if not using the filesystem *\/\n_app_size      = _flash_size - _sd_size - _fs_size;\n_app_start     = _sd_size;\n_fs_start      = _sd_size + _app_size;\n_fs_end        = _fs_start + _fs_size;\n_app_ram_start = _ram_start + _sd_ram;\n_app_ram_size  = _ram_size - _sd_ram;\n_heap_start    = _ebss;\n_heap_end      = _ram_end - _stack_size;\n_heap_size     = _heap_end - _heap_start;\n\nASSERT(_heap_size >= _minimum_heap_size, \"not enough RAM left for heap\")\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_TEXT (rx) : ORIGIN = _app_start,     LENGTH = _app_size     \/* app *\/\n    RAM (xrw)       : ORIGIN = _app_ram_start, LENGTH = _app_ram_size\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"283e8384f08002f93de33e0c7ceee5b867c0f2e5","subject":"Add .data.rel.local to orex.ld","message":"Add .data.rel.local to orex.ld\n\nIt is apparently needed in some cases.","repos":"ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme","old_file":"orex.ld","new_file":"orex.ld","new_contents":"ENTRY (main)\n\nMEMORY\n{\n  ram : ORIGIN = 0x00001000, LENGTH = 31M\n  rom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n  .heap 0x1000 : \/* Space to futz with *\/\n  {\n    . = . + 25165824; \/* allocate 24 MB for dynamic memory use *\/\n  } >ram\n\n  .data : \/* Initialized data. *\/\n  {\n    _DataStart = . ;\n    *(.data)\n    *(.data.rel.local)\n    _DataEnd = . ;\n  } >ram\n\n  .bss : \/* Uninitialized data. *\/\n  {\n    _BssStart = . ;\n    *(.bss)\n    *(.sbss)\n    _BssEnd = . ;\n  } >ram\n\n  .text : \/* The actual instructions. *\/\n  {\n    *(.text)\n    *(.got)\n    *(.got.plt)\n    *(.rodata)\n    *(.rodata.str1.4)\n    *(.glue_7)\n    *(.glue_7t)\n  } >ram\n}\n","old_contents":"ENTRY (main)\n\nMEMORY\n{\n  ram : ORIGIN = 0x00001000, LENGTH = 31M\n  rom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n  .heap 0x1000 : \/* Space to futz with *\/\n  {\n    . = . + 25165824; \/* allocate 24 MB for dynamic memory use *\/\n  } >ram\n\n  .data : \/* Initialized data. *\/\n  {\n    _DataStart = . ;\n    *(.data)\n    _DataEnd = . ;\n  } >ram\n\n  .bss : \/* Uninitialized data. *\/\n  {\n    _BssStart = . ;\n    *(.bss)\n    *(.sbss)\n    _BssEnd = . ;\n  } >ram\n\n  .text : \/* The actual instructions. *\/\n  {\n    *(.text)\n    *(.got)\n    *(.got.plt)\n    *(.rodata)\n    *(.rodata.str1.4)\n    *(.glue_7)\n    *(.glue_7t)\n  } >ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"fc1b47de24a05f0b2edb6c269e1246bd318f1502","subject":"linker.ld: Move .note.gnu.build-id to a better place","message":"linker.ld: Move .note.gnu.build-id to a better place\n","repos":"akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix","old_file":"linker.ld","new_file":"linker.ld","new_contents":"\/************************************************************************\n *   Copyright (c) 2012 \u00c1kos Kov\u00e1cs - Akosix operating system\n *              http:\/\/akoskovacs.github.com\/Akosix\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n * \n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, \n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION\n * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n ************************************************************************\/\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    . = 0x00100000;\n    .setup :\n    {\n    __start_setup = .;\n        *(.setup)\n        *(.setup.data)\n        boot\/boot.o(.bss)\n        boot\/boot.o(COMMON)\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf) \n    {\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n        *(.text)\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n\n    .note ALIGN(page_size) : AT(ADDR(.note) - hhalf)\n    {\n        *(.note.gnu.build-id)\n    }\n}\n","old_contents":"\/************************************************************************\n *   Copyright (c) 2012 \u00c1kos Kov\u00e1cs - Akosix operating system\n *              http:\/\/akoskovacs.github.com\/Akosix\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n * \n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, \n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION\n * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n ************************************************************************\/\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    . = 0x00100000;\n    .setup :\n    {\n    __start_setup = .;\n        *(.setup)\n        *(.setup.data)\n        boot\/boot.o(.bss)\n        boot\/boot.o(COMMON)\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf) \n    {\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n        *(.text)\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f78f7076aa7461af450b4f50c3a81bea870a039d","subject":"soc: nxp: rt: Add custom memory areas to linker script","message":"soc: nxp: rt: Add custom memory areas to linker script\n\nRT SOCs have several memory areas (OCRAMs, DTCM, ITCM, SDRAM, FLASH...)\nbut only two are selected for FLASH (code) and RAM (data).\nIt would be good to let the linker be aware about other regions, which\ncould then be used by drivers or application to create dedicated\nsections and relocate memory. For example if we have code in ITCM and\ndata in DTCM, we still need a dma-able region\/section for e.g.\nvideo\/camera buffers.\n\nSigned-off-by: Loic Poulain <7dbc6498a90ff1ada42fc224430b4f763baa5c5c@linaro.org>\n","repos":"Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/arm\/nxp_imx\/rt\/linker.ld","new_file":"soc\/arm\/nxp_imx\/rt\/linker.ld","new_contents":"\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n #include <autoconf.h>\n #include <generated_dts_board.h>\n\nMEMORY\n     {\n#if (DT_MMIO_SRAM_20200000_SIZE > 0) && !defined(CONFIG_DATA_OCRAM)\n        OCRAM  (wx) : ORIGIN = DT_MMIO_SRAM_20200000_BASE_ADDRESS, LENGTH = DT_MMIO_SRAM_20200000_SIZE\n#endif\n#if (DT_MMIO_SRAM_80000000_SIZE > 0) && !defined(CONFIG_DATA_SEMC)\n        SDRAM  (wx) : ORIGIN = DT_MMIO_SRAM_80000000_BASE_ADDRESS, LENGTH = DT_MMIO_SRAM_80000000_SIZE\n#endif\n#if (DT_INST_0_NXP_IMX_DTCM_SIZE > 0) && !defined(CONFIG_DATA_DTCM)\n        DTCM    (wx) : ORIGIN = DT_INST_0_NXP_IMX_DTCM_BASE_ADDRESS, LENGTH = DT_INST_0_NXP_IMX_DTCM_SIZE\n#endif\n#if (DT_INST_0_NXP_IMX_ITCM_SIZE > 0) && !defined(CONFIG_CODE_ITCM)\n        ITCM    (wx) : ORIGIN = DT_INST_0_NXP_IMX_ITCM_BASE_ADDRESS, LENGTH = DT_INST_0_NXP_IMX_ITCM_SIZE\n#endif\n     }\n\n#include <arch\/arm\/cortex_m\/scripts\/linker.ld>\n","old_contents":"\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <arch\/arm\/cortex_m\/scripts\/linker.ld>\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1d9a7e94a49e9dfa2bdb0330e079c085de6cc5ae","subject":"remove unneeded symbols from linker script","message":"remove unneeded symbols from linker script\n","repos":"yeputons\/os-course-term4,yeputons\/os-course-term4","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"OUTPUT_FORMAT(elf64-x86-64)\nOUTPUT_ARCH(i386:x86-64)\nENTRY(start32)\n\nPAGE_SIZE = 0x1000;\nVIRTUAL_BASE = 0xffffffff80000000;\n\nSECTIONS\n{\n\t. = 1M + SIZEOF_HEADERS;\n\n\ttext_phys_begin = .;\n\t.bootstrap : { *(.bootstrap) }\n\n\t. += VIRTUAL_BASE;\n\t.text : AT(ADDR(.bootstrap) + SIZEOF(.bootstrap)) { *(.text) }\n\n\tdata_phys_begin = . - VIRTUAL_BASE;\n\t.rodata : { *(.rodata) }\n\t.data : { *(.data) }\n\tdata_phys_end = . - VIRTUAL_BASE;\n\t. = ALIGN(PAGE_SIZE);\n\n\tbss_phys_begin = . - VIRTUAL_BASE;\n\t.bss : {\n\t\t. += 6 * PAGE_SIZE;\n\t\t*(.bss)\n\t}\n\tbss_phys_end = . - VIRTUAL_BASE;\n}\n","old_contents":"OUTPUT_FORMAT(elf64-x86-64)\nOUTPUT_ARCH(i386:x86-64)\nENTRY(start32)\n\nPAGE_SIZE = 0x1000;\nVIRTUAL_BASE = 0xffffffff80000000;\n\nSECTIONS\n{\n\t. = 1M + SIZEOF_HEADERS;\n\n\ttext_phys_begin = .;\n\ttext_virt_begin = . + VIRTUAL_BASE;\n\t.bootstrap : { *(.bootstrap) }\n\n\t. += VIRTUAL_BASE;\n\t.text : AT(ADDR(.bootstrap) + SIZEOF(.bootstrap)) { *(.text) }\n\n\tdata_phys_begin = . - VIRTUAL_BASE;\n\tdata_virt_begin = .;\n\t.rodata : { *(.rodata) }\n\t.data : { *(.data) }\n\tdata_phys_end = . - VIRTUAL_BASE;\n\tdata_virt_end = .;\n\t. = ALIGN(PAGE_SIZE);\n\n\tbss_phys_begin = . - VIRTUAL_BASE;\n\tbss_virt_begin = .;\n\t.bss : {\n\t\t. += 6 * PAGE_SIZE;\n\t\t*(.bss)\n\t}\n\tbss_phys_end = . - VIRTUAL_BASE;\n\tbss_virt_end = .;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b33b7fcb5c80f95555356eea841ad4cdee7feafa","subject":"Add linker section to get an error for undefined sections This helps to identify problems in the linker phase. ---  scripts\/sections_FLASH.ld | 5 +++++  1 file changed, 5 insertions(+)","message":"Add linker section to get an error for undefined sections\nThis helps to identify problems in the linker phase.\n---\n scripts\/sections_FLASH.ld | 5 +++++\n 1 file changed, 5 insertions(+)\n","repos":"blandry\/crazyflie-tools,peteflorence\/crazyflie-tools,blandry\/crazyflie-tools,blandry\/crazyflie-tools,blandry\/crazyflie-tools,peteflorence\/crazyflie-tools,peteflorence\/crazyflie-tools,peteflorence\/crazyflie-tools","old_file":"scripts\/sections_FLASH.ld","new_file":"scripts\/sections_FLASH.ld","new_contents":"\/*\r\nCommon part of the linker scripts for STR71x devices in FLASH mode\r\n(that is, the FLASH is seen at 0)\r\nCopyright RAISONANCE 2005\r\nYou can use, modify and distribute thisfile freely, but without any waranty.\r\n*\/\r\n\r\n\r\nMEMORY {\r\n       UNEXPECTED_SECTIONS : ORIGIN = 0xffffffff, LENGTH = 0\r\n}\r\n\r\n\/* Sections Definitions *\/\r\n\r\nSECTIONS\r\n{\r\n    \/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH *\/\r\n    .isr_vector :\r\n    {\r\n\t. = ALIGN(4);\r\n        KEEP(*(.isr_vector))            \/* Startup code *\/\r\n\t. = ALIGN(4);\r\n    } >FLASH\r\n \r\n    \/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH *\/\r\n    .flashtext :\r\n    {\r\n\t. = ALIGN(4);\r\n        *(.flashtext)            \/* Startup code *\/\r\n\t. = ALIGN(4);\r\n    } >FLASH\r\n \r\n    \r\n    \/* the program code is stored in the .text section, which goes to Flash *\/\r\n    .text :\r\n    {\r\n\t    . = ALIGN(4);\r\n\t    \r\n        *(.text)                   \/* remaining code *\/\r\n        *(.text.*)                 \/* remaining code *\/\r\n        *(.rodata)                 \/* read-only data (constants) *\/\r\n        *(.rodata*)\r\n        *(.glue_7)\r\n        *(.glue_7t)\r\n        \r\n        \/* Some stuff of CodeSourcery? *\/\r\n        *(.init)\r\n        *(.fini)\r\n        *(.eh_frame)\r\n\r\n        \/* Parameters and log system datas *\/\r\n        . = ALIGN(4);\r\n        _param_start = .;\r\n        KEEP(*(.param))\r\n        KEEP(*(.param.*))\r\n        _param_stop = .;\r\n        . = ALIGN(4);\r\n        _log_start = .;\r\n        KEEP(*(.log))\r\n        KEEP(*(.log.*))\r\n        _log_stop = .;\r\n        \r\n        \r\n\t    . = ALIGN(4);\r\n   \t _etext = .;\r\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\r\n   \t \/* _sidata = _etext; *\/\r\n    } >FLASH\r\n\r\n    .libc :\r\n    {\r\n      . = ALIGN(4);\r\n      *(.ARM.exidx*)\r\n      . = ALIGN(4);\r\n      \r\n      _elibc = .;\r\n      _sidata = _elibc;\r\n    } >FLASH\r\n \r\n    \/* for some LPC devices, there is a FLASH patch to place at a specified address *\/\r\n    .flashpatch :\r\n    {\r\n\t. = ALIGN(4);\r\n        KEEP(*(.flashpatch))            \/* flashpatch data *\/\r\n\t. = ALIGN(4);\r\n    } >FLASHPATCH\r\n    \r\n    \/* for some LPC devices, there is a FLASH patch to place at a specified address\r\n    and then there is the rest of the flash *\/\r\n    .endflash :\r\n    {\r\n\t. = ALIGN(4);\r\n        *(.endflash)            \/* endflash code *\/\r\n\t. = ALIGN(4);\r\n    } >ENDFLASH\r\n\r\n    \/* This is the initialized data section\r\n    The program executes knowing that the data is in the RAM\r\n    but the loader puts the initial values in the FLASH (inidata).\r\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\r\n    .data  : AT ( _sidata )\r\n    {\r\n\t    . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sdata = . ;\r\n        \r\n        *(.data)\r\n        *(.data.*)\r\n        *(.RAMtext)\r\n\r\n\t    . = ALIGN(4);\r\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\r\n   \t _edata = . ;\r\n    } >RAM\r\n    \r\n    \r\n\r\n    \/* This is the uninitialized data section *\/\r\n    .bss :\r\n    {\r\n\t    . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _sbss = .;\r\n        \r\n        *(.bss)\r\n        *(.bss.*)\r\n        *(COMMON)\r\n        \r\n\t    . = ALIGN(4);\r\n\t    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n   \t _ebss = . ;\r\n    } >RAM\r\n    \r\n    PROVIDE ( end = _ebss );\r\n    PROVIDE ( _end = _ebss );\r\n    \r\n    \/* This is the user stack section \r\n    This is just to check that there is enough RAM left for the User mode stack\r\n    It should generate an error if it's full.\r\n     *\/\r\n    ._usrstack :\r\n    {\r\n\t    . = ALIGN(4);\r\n        _susrstack = . ;\r\n        \r\n        . = . + _Minimum_Stack_Size ;\r\n        \r\n\t    . = ALIGN(4);\r\n        _eusrstack = . ;\r\n    } >RAM\r\n    \r\n\r\n   \r\n    \/* this is the FLASH Bank1 *\/\r\n    \/* the C or assembly source must explicitly place the code or data there\r\n    using the \"section\" attribute *\/\r\n    .b1text :\r\n    {\r\n        *(.b1text)                   \/* remaining code *\/\r\n        *(.b1rodata)                 \/* read-only data (constants) *\/\r\n        *(.b1rodata*)\r\n    } >FLASHB1\r\n    \r\n    \/* this is the EXTMEM *\/\r\n    \/* the C or assembly source must explicitly place the code or data there\r\n    using the \"section\" attribute *\/\r\n    \r\n    \/* EXTMEM Bank0 *\/\r\n    .eb0text :\r\n    {\r\n        *(.eb0text)                   \/* remaining code *\/\r\n        *(.eb0rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb0rodata*)\r\n    } >EXTMEMB0\r\n    \r\n    \/* EXTMEM Bank1 *\/\r\n    .eb1text :\r\n    {\r\n        *(.eb1text)                   \/* remaining code *\/\r\n        *(.eb1rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb1rodata*)\r\n    } >EXTMEMB1\r\n    \r\n    \/* EXTMEM Bank2 *\/\r\n    .eb2text :\r\n    {\r\n        *(.eb2text)                   \/* remaining code *\/\r\n        *(.eb2rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb2rodata*)\r\n    } >EXTMEMB2\r\n    \r\n    \/* EXTMEM Bank0 *\/\r\n    .eb3text :\r\n    {\r\n        *(.eb3text)                   \/* remaining code *\/\r\n        *(.eb3rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb3rodata*)\r\n    } >EXTMEMB3\r\n    \r\n    __exidx_start = .;\r\n    __exidx_end = .;\r\n    \r\n    \/* after that it's only debugging information. *\/\r\n    \r\n    \/* remove the debugging information from the standard libraries *\/\r\n    \/DISCARD\/ :\r\n    {\r\n     libc.a ( * )\r\n     libm.a ( * )\r\n     libgcc.a ( * )\r\n     }\r\n\r\n    \/* Stabs debugging sections.  *\/\r\n    .stab          0 : { *(.stab) }\r\n    .stabstr       0 : { *(.stabstr) }\r\n    .stab.excl     0 : { *(.stab.excl) }\r\n    .stab.exclstr  0 : { *(.stab.exclstr) }\r\n    .stab.index    0 : { *(.stab.index) }\r\n    .stab.indexstr 0 : { *(.stab.indexstr) }\r\n    .comment       0 : { *(.comment) }\r\n    \/* DWARF debug sections.\r\n       Symbols in the DWARF debugging sections are relative to the beginning\r\n       of the section so we begin them at 0.  *\/\r\n    \/* DWARF 1 *\/\r\n    .debug          0 : { *(.debug) }\r\n    .line           0 : { *(.line) }\r\n    \/* GNU DWARF 1 extensions *\/\r\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n    .debug_sfnames  0 : { *(.debug_sfnames) }\r\n    \/* DWARF 1.1 and DWARF 2 *\/\r\n    .debug_aranges  0 : { *(.debug_aranges) }\r\n    .debug_pubnames 0 : { *(.debug_pubnames) }\r\n    \/* DWARF 2 *\/\r\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n    .debug_abbrev   0 : { *(.debug_abbrev) }\r\n    .debug_line     0 : { *(.debug_line) }\r\n    .debug_frame    0 : { *(.debug_frame) }\r\n    .debug_str      0 : { *(.debug_str) }\r\n    .debug_loc      0 : { *(.debug_loc) }\r\n    .debug_macinfo  0 : { *(.debug_macinfo) }\r\n    \/* SGI\/MIPS DWARF 2 extensions *\/\r\n    .debug_weaknames 0 : { *(.debug_weaknames) }\r\n    .debug_funcnames 0 : { *(.debug_funcnames) }\r\n    .debug_typenames 0 : { *(.debug_typenames) }\r\n    .debug_varnames  0 : { *(.debug_varnames) }\r\n\r\n    .unexpected_sections : { *(*) } > UNEXPECTED_SECTIONS\r\n}\r\n\r\n\r\n\r\n","old_contents":"\/*\r\nCommon part of the linker scripts for STR71x devices in FLASH mode\r\n(that is, the FLASH is seen at 0)\r\nCopyright RAISONANCE 2005\r\nYou can use, modify and distribute thisfile freely, but without any waranty.\r\n*\/\r\n\r\n\r\n\r\n\/* Sections Definitions *\/\r\n\r\nSECTIONS\r\n{\r\n    \/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH *\/\r\n    .isr_vector :\r\n    {\r\n\t. = ALIGN(4);\r\n        KEEP(*(.isr_vector))            \/* Startup code *\/\r\n\t. = ALIGN(4);\r\n    } >FLASH\r\n \r\n    \/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH *\/\r\n    .flashtext :\r\n    {\r\n\t. = ALIGN(4);\r\n        *(.flashtext)            \/* Startup code *\/\r\n\t. = ALIGN(4);\r\n    } >FLASH\r\n \r\n    \r\n    \/* the program code is stored in the .text section, which goes to Flash *\/\r\n    .text :\r\n    {\r\n\t    . = ALIGN(4);\r\n\t    \r\n        *(.text)                   \/* remaining code *\/\r\n        *(.text.*)                 \/* remaining code *\/\r\n        *(.rodata)                 \/* read-only data (constants) *\/\r\n        *(.rodata*)\r\n        *(.glue_7)\r\n        *(.glue_7t)\r\n        \r\n        \/* Some stuff of CodeSourcery? *\/\r\n        *(.init)\r\n        *(.fini)\r\n        *(.eh_frame)\r\n\r\n        \/* Parameters and log system datas *\/\r\n        . = ALIGN(4);\r\n        _param_start = .;\r\n        KEEP(*(.param))\r\n        KEEP(*(.param.*))\r\n        _param_stop = .;\r\n        . = ALIGN(4);\r\n        _log_start = .;\r\n        KEEP(*(.log))\r\n        KEEP(*(.log.*))\r\n        _log_stop = .;\r\n        \r\n        \r\n\t    . = ALIGN(4);\r\n   \t _etext = .;\r\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\r\n   \t \/* _sidata = _etext; *\/\r\n    } >FLASH\r\n\r\n    .libc :\r\n    {\r\n      . = ALIGN(4);\r\n      *(.ARM.exidx*)\r\n      . = ALIGN(4);\r\n      \r\n      _elibc = .;\r\n      _sidata = _elibc;\r\n    } >FLASH\r\n \r\n    \/* for some LPC devices, there is a FLASH patch to place at a specified address *\/\r\n    .flashpatch :\r\n    {\r\n\t. = ALIGN(4);\r\n        KEEP(*(.flashpatch))            \/* flashpatch data *\/\r\n\t. = ALIGN(4);\r\n    } >FLASHPATCH\r\n    \r\n    \/* for some LPC devices, there is a FLASH patch to place at a specified address\r\n    and then there is the rest of the flash *\/\r\n    .endflash :\r\n    {\r\n\t. = ALIGN(4);\r\n        *(.endflash)            \/* endflash code *\/\r\n\t. = ALIGN(4);\r\n    } >ENDFLASH\r\n\r\n    \/* This is the initialized data section\r\n    The program executes knowing that the data is in the RAM\r\n    but the loader puts the initial values in the FLASH (inidata).\r\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\r\n    .data  : AT ( _sidata )\r\n    {\r\n\t    . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sdata = . ;\r\n        \r\n        *(.data)\r\n        *(.data.*)\r\n        *(.RAMtext)\r\n\r\n\t    . = ALIGN(4);\r\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\r\n   \t _edata = . ;\r\n    } >RAM\r\n    \r\n    \r\n\r\n    \/* This is the uninitialized data section *\/\r\n    .bss :\r\n    {\r\n\t    . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _sbss = .;\r\n        \r\n        *(.bss)\r\n        *(.bss.*)\r\n        *(COMMON)\r\n        \r\n\t    . = ALIGN(4);\r\n\t    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n   \t _ebss = . ;\r\n    } >RAM\r\n    \r\n    PROVIDE ( end = _ebss );\r\n    PROVIDE ( _end = _ebss );\r\n    \r\n    \/* This is the user stack section \r\n    This is just to check that there is enough RAM left for the User mode stack\r\n    It should generate an error if it's full.\r\n     *\/\r\n    ._usrstack :\r\n    {\r\n\t    . = ALIGN(4);\r\n        _susrstack = . ;\r\n        \r\n        . = . + _Minimum_Stack_Size ;\r\n        \r\n\t    . = ALIGN(4);\r\n        _eusrstack = . ;\r\n    } >RAM\r\n    \r\n\r\n   \r\n    \/* this is the FLASH Bank1 *\/\r\n    \/* the C or assembly source must explicitly place the code or data there\r\n    using the \"section\" attribute *\/\r\n    .b1text :\r\n    {\r\n        *(.b1text)                   \/* remaining code *\/\r\n        *(.b1rodata)                 \/* read-only data (constants) *\/\r\n        *(.b1rodata*)\r\n    } >FLASHB1\r\n    \r\n    \/* this is the EXTMEM *\/\r\n    \/* the C or assembly source must explicitly place the code or data there\r\n    using the \"section\" attribute *\/\r\n    \r\n    \/* EXTMEM Bank0 *\/\r\n    .eb0text :\r\n    {\r\n        *(.eb0text)                   \/* remaining code *\/\r\n        *(.eb0rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb0rodata*)\r\n    } >EXTMEMB0\r\n    \r\n    \/* EXTMEM Bank1 *\/\r\n    .eb1text :\r\n    {\r\n        *(.eb1text)                   \/* remaining code *\/\r\n        *(.eb1rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb1rodata*)\r\n    } >EXTMEMB1\r\n    \r\n    \/* EXTMEM Bank2 *\/\r\n    .eb2text :\r\n    {\r\n        *(.eb2text)                   \/* remaining code *\/\r\n        *(.eb2rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb2rodata*)\r\n    } >EXTMEMB2\r\n    \r\n    \/* EXTMEM Bank0 *\/\r\n    .eb3text :\r\n    {\r\n        *(.eb3text)                   \/* remaining code *\/\r\n        *(.eb3rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb3rodata*)\r\n    } >EXTMEMB3\r\n    \r\n    __exidx_start = .;\r\n    __exidx_end = .;\r\n    \r\n    \/* after that it's only debugging information. *\/\r\n    \r\n    \/* remove the debugging information from the standard libraries *\/\r\n    \/DISCARD\/ :\r\n    {\r\n     libc.a ( * )\r\n     libm.a ( * )\r\n     libgcc.a ( * )\r\n     }\r\n\r\n    \/* Stabs debugging sections.  *\/\r\n    .stab          0 : { *(.stab) }\r\n    .stabstr       0 : { *(.stabstr) }\r\n    .stab.excl     0 : { *(.stab.excl) }\r\n    .stab.exclstr  0 : { *(.stab.exclstr) }\r\n    .stab.index    0 : { *(.stab.index) }\r\n    .stab.indexstr 0 : { *(.stab.indexstr) }\r\n    .comment       0 : { *(.comment) }\r\n    \/* DWARF debug sections.\r\n       Symbols in the DWARF debugging sections are relative to the beginning\r\n       of the section so we begin them at 0.  *\/\r\n    \/* DWARF 1 *\/\r\n    .debug          0 : { *(.debug) }\r\n    .line           0 : { *(.line) }\r\n    \/* GNU DWARF 1 extensions *\/\r\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n    .debug_sfnames  0 : { *(.debug_sfnames) }\r\n    \/* DWARF 1.1 and DWARF 2 *\/\r\n    .debug_aranges  0 : { *(.debug_aranges) }\r\n    .debug_pubnames 0 : { *(.debug_pubnames) }\r\n    \/* DWARF 2 *\/\r\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n    .debug_abbrev   0 : { *(.debug_abbrev) }\r\n    .debug_line     0 : { *(.debug_line) }\r\n    .debug_frame    0 : { *(.debug_frame) }\r\n    .debug_str      0 : { *(.debug_str) }\r\n    .debug_loc      0 : { *(.debug_loc) }\r\n    .debug_macinfo  0 : { *(.debug_macinfo) }\r\n    \/* SGI\/MIPS DWARF 2 extensions *\/\r\n    .debug_weaknames 0 : { *(.debug_weaknames) }\r\n    .debug_funcnames 0 : { *(.debug_funcnames) }\r\n    .debug_typenames 0 : { *(.debug_typenames) }\r\n    .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n\r\n\r\n\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2c06ece7e08aa2d7fa260ebf5728b0a628a7d781","subject":"Allocate 24MB for tasks to use as a heap","message":"Allocate 24MB for tasks to use as a heap","repos":"ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme","old_file":"orex.ld","new_file":"orex.ld","new_contents":"ENTRY (main)\n\nMEMORY\n{\n  ram : ORIGIN = 0x00001000, LENGTH = 31M\n  rom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n  .heap 0x1000 : \/* Space to futz with *\/\n  {\n    . = . + 25165824; \/* allocate 24 MB for dynamic memory use *\/\n  } >ram\n\n  .data : \/* Initialized data. *\/\n  {\n    _DataStart = . ;\n    *(.data)\n    _DataEnd = . ;\n  } >ram\n\n  .bss : \/* Uninitialized data. *\/\n  {\n    _BssStart = . ;\n    *(.bss)\n    *(.sbss)\n    _BssEnd = . ;\n  } >ram\n\n  .text : \/* The actual instructions. *\/\n  {\n    *(.text)\n    *(.got)\n    *(.got.plt)\n    *(.rodata)\n    *(.rodata.str1.4)\n    *(.glue_7)\n    *(.glue_7t)\n  } >ram\n}\n","old_contents":"ENTRY (main)\n\nMEMORY\n{\n\tram : ORIGIN = 0x00218000, LENGTH = 29M\n\trom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n\t.data : \/* Initialized data. *\/\n\t{\n\t\t_DataStart = . ;\n\t\t*(.data)\n\t\t_DataEnd = . ;\n\t} >ram\n\n\t.bss : \/* Uninitialized data. *\/\n\t{\n\t\t_BssStart = . ;\n\t\t*(.bss)\n\t\t*(.sbss)\n\t\t_BssEnd = . ;\n\t} >ram\n\n\t.text : \/* The actual instructions. *\/\n\t{\n\t\t*(.text)\n\t\t*(.got)\n\t\t*(.got.plt)\n\t\t*(.rodata)\n\t\t*(.rodata.str1.4)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t} >ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3b63b925391bd20dfda595af874c10165cdf8091","subject":"linker: place debug header section for CC3235SF","message":"linker: place debug header section for CC3235SF\n\nThe CC3235SF requires a debug header to be placed at the beginning of\ninternal flash, so that the bootloader does not automatically overwrite\nthe flash memory with the program saved in external flash.\n\nSigned-off-by: Vincent Wan <0da4a49376daf88459b96a63301ecd5aff2f3b80@linaro.org>\n","repos":"Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n#ifdef DT_DTCM_BASE_ADDRESS\n    DTCM                  (rw) : ORIGIN = DT_DTCM_BASE_ADDRESS, LENGTH = DT_DTCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#if defined(CONFIG_CC3220SF_DEBUG) || defined(CONFIG_CC3235SF_DEBUG)\n\t\/* Add CC32xx flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\n#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER\n\tKEEP(*(.boot_hdr.conf))\n\t. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;\n\tKEEP(*(.boot_hdr.ivt))\n\tKEEP(*(.boot_hdr.data))\n#ifdef CONFIG_DEVICE_CONFIGURATION_DATA\n\tKEEP(*(.boot_hdr.dcd_data))\n#endif\n#endif\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef DT_DTCM_BASE_ADDRESS\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_bss_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_data_end = .;\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif \/* DT_DTCM_BASE_ADDRESS *\/\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#elif defined(CONFIG_CPU_HAS_NRF_IDAU)\n\t\/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. *\/\n\t#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NSC_ALIGN_END . = ALIGN(0x8000)\n#else\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\tASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))\n\t\t\t == (0x8000 - (__sg_start % 0x8000))\n\t\t&& (0x8000 - (__sg_start % 0x8000)) >= 32\n\t\t&& (0x8000 - (__sg_start % 0x8000)) <= 4096,\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n#ifdef DT_DTCM_BASE_ADDRESS\n    DTCM                  (rw) : ORIGIN = DT_DTCM_BASE_ADDRESS, LENGTH = DT_DTCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\n#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER\n\tKEEP(*(.boot_hdr.conf))\n\t. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;\n\tKEEP(*(.boot_hdr.ivt))\n\tKEEP(*(.boot_hdr.data))\n#ifdef CONFIG_DEVICE_CONFIGURATION_DATA\n\tKEEP(*(.boot_hdr.dcd_data))\n#endif\n#endif\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef DT_DTCM_BASE_ADDRESS\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_bss_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_data_end = .;\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif \/* DT_DTCM_BASE_ADDRESS *\/\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#elif defined(CONFIG_CPU_HAS_NRF_IDAU)\n\t\/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. *\/\n\t#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NSC_ALIGN_END . = ALIGN(0x8000)\n#else\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\tASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))\n\t\t\t == (0x8000 - (__sg_start % 0x8000))\n\t\t&& (0x8000 - (__sg_start % 0x8000)) >= 32\n\t\t&& (0x8000 - (__sg_start % 0x8000)) <= 4096,\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"071a469623a845e85675cb2932b55d97e4e9c542","subject":"arch: arm: fix initial value of _image_ram_start","message":"arch: arm: fix initial value of _image_ram_start\n\nFor all builds, _image_ram_start is initially set to RAM_ADDR,\nbefore it is (possibly) aligned for MPU.\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\n","repos":"galak\/zephyr,ldts\/zephyr,ldts\/zephyr,galak\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,explora26\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,explora26\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,explora26\/zephyr,punitvara\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,explora26\/zephyr,ldts\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\tMPU_ALIGN(__app_ram_size);\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\n\t\t__app_last_address_used = .;\n\n\t\t\/* Align the end of the application memory\n\t\t * with MPU alignment requirement.\n\t\t *\/\n\t\tMPU_ALIGN(__app_ram_size);\n\t\t__app_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n#if defined(CONFIG_NOCACHE_MEMORY)\n\t\/* Non-cached region of RAM *\/\n\tSECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.nocache)\n\t\tKERNEL_INPUT_SECTION(\".nocache.*\")\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\t_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;\n#endif \/* CONFIG_NOCACHE_MEMORY *\/\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tAPP_SHARED_ALIGN;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t\/* Align the end of shared app mem section with the\n\t\t * minimum granularity required by MPU.\n\t\t *\/\n\t\tAPP_SHARED_ALIGN;\n\t\t_app_smem_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\tMPU_ALIGN(__app_ram_size);\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\n\t\t__app_last_address_used = .;\n\n\t\t\/* Align the end of the application memory\n\t\t * with MPU alignment requirement.\n\t\t *\/\n\t\tMPU_ALIGN(__app_ram_size);\n\t\t__app_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n#if defined(CONFIG_NOCACHE_MEMORY)\n\t\/* Non-cached region of RAM *\/\n\tSECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.nocache)\n\t\tKERNEL_INPUT_SECTION(\".nocache.*\")\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\t_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;\n#endif \/* CONFIG_NOCACHE_MEMORY *\/\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tAPP_SHARED_ALIGN;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t\/* Align the end of shared app mem section with the\n\t\t * minimum granularity required by MPU.\n\t\t *\/\n\t\tAPP_SHARED_ALIGN;\n\t\t_app_smem_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7d2aea9ab1daf0b864097109b557d4d06cb52d07","subject":"arm64: linker: Remove IRQ vector table symbols","message":"arm64: linker: Remove IRQ vector table symbols\n\nThe IRQ vector table cannot be used on this architecture.\n\nSigned-off-by: Carlo Caione <ca4506c8c654a4ccf75802e86b5d162c1e96f065@baylibre.com>\n","repos":"zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr","old_file":"include\/zephyr\/arch\/arm64\/scripts\/linker.ld","new_file":"include\/zephyr\/arch\/arm64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#elif defined(CONFIG_ARM_MPU)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n  #define BSS_ALIGN ALIGN(_region_min_align)\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#ifndef BSS_ALIGN\n#define BSS_ALIGN\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    __rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        __text_region_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __text_region_end = .;\n    __text_region_size = __text_region_end - __text_region_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n        __rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    __rodata_region_end = .;\n    __rodata_region_size = __rodata_region_end - __rodata_region_start;\n    __rom_region_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#if defined(CONFIG_ARM_MPU)\n\/*\n * When _app_smem region is empty, alignment is also needed. If there\n * is no alignment, the _app_smem_start used by arm mpu can be lower\n * than __rodata_region_end, and this two regions can overlap.\n * The Armv8-R aarch64 MPU does not allow overlapped regions.\n *\/\n#define EMPTY_APP_SHARED_ALIGN APP_SHARED_ALIGN\n#endif\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n\t__data_region_start = .;\n\t__data_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        __data_end = .;\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#elif defined(CONFIG_ARM_MPU)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n  #define BSS_ALIGN ALIGN(_region_min_align)\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#ifndef BSS_ALIGN\n#define BSS_ALIGN\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    __rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        __text_region_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __text_region_end = .;\n    __text_region_size = __text_region_end - __text_region_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n        __rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    __rodata_region_end = .;\n    __rodata_region_size = __rodata_region_end - __rodata_region_start;\n    __rom_region_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#if defined(CONFIG_ARM_MPU)\n\/*\n * When _app_smem region is empty, alignment is also needed. If there\n * is no alignment, the _app_smem_start used by arm mpu can be lower\n * than __rodata_region_end, and this two regions can overlap.\n * The Armv8-R aarch64 MPU does not allow overlapped regions.\n *\/\n#define EMPTY_APP_SHARED_ALIGN APP_SHARED_ALIGN\n#endif\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n\t__data_region_start = .;\n\t__data_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        __data_end = .;\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"83d4aaf352cb8ee6d0c9492ec5985bed6c78c552","subject":"omit package parameter","message":"omit package parameter\n","repos":"beadsland\/Soma,beadsland\/Soma","old_file":"config.ld","new_file":"config.ld","new_contents":"project     = 'Soma'\nfile        = 'src'\ndescription = 'Lua emulation of Elixir semantics'\nreadme      = 'README.md'\nformat      = 'discount'\ndir         = 'docs'\n","old_contents":"project     = 'Soma'\nfile        = 'src'\npackage     = 'src'\ndescription = 'Lua emulation of Elixir semantics'\nreadme      = 'README.md'\nformat      = 'discount'\ndir         = 'docs'\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"14acaa4a3361403e06b284bf8e1e32ad9cec5457","subject":"Fix typo from Ard's old tree 32-bit ARM patch.","message":"Fix typo from Ard's old tree 32-bit ARM patch.\n\nWe don't need to .data entries; the second one should be .data*.  He's\nsince fixed this in his tree, but I'd already pulled it and pushed to\nmaster.\n\nSigned-off-by: Peter Jones <2e0a021e603479ff81838c00c3b770daca4e0214@redhat.com>\n","repos":"CyanogenMod\/android_external_uefi_shim,android-ia\/platform_external_uefi_shim,rhinstaller\/shim,rhinstaller\/shim,android-ia\/platform_external_uefi_shim,rhinstaller\/shim,CyanogenMod\/android_external_uefi_shim,android-ia\/platform_external_uefi_shim,CyanogenMod\/android_external_uefi_shim","old_file":"elf_arm_efi.lds","new_file":"elf_arm_efi.lds","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS\n{\n  .text 0x0 : {\n    *(.text.head)\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t.*)\n    *(.srodata)\n    *(.rodata*)\n    . = ALIGN(16);\n    _etext = .;\n  }\n  .dynamic  : { *(.dynamic) }\n  .data :\n  {\n   *(.sdata)\n   *(.data)\n   *(.data1)\n   *(.data*)\n   *(.got.plt)\n   *(.got)\n\n   \/* the EFI loader doesn't seem to like a .bss section, so we stick\n      it all into .data: *\/\n   . = ALIGN(16);\n   _bss = .;\n   *(.sbss)\n   *(.scommon)\n   *(.dynbss)\n   *(.bss)\n   *(COMMON)\n   . = ALIGN(16);\n   _bss_end = .;\n  }\n\n   . = ALIGN(4096);\n  .vendor_cert :\n  {\n    *(.vendor_cert)\n  }\n  . = ALIGN(4096);\n\n  .rel.dyn : { *(.rel.dyn) }\n  .rel.plt : { *(.rel.plt) }\n  .rel.got : { *(.rel.got) }\n  .rel.data : { *(.rel.data) *(.rel.data*) }\n  _edata = .;\n  _data_size = . - _etext;\n\n  . = ALIGN(4096);\n  .dynsym   : { *(.dynsym) }\n  . = ALIGN(4096);\n  .dynstr   : { *(.dynstr) }\n  . = ALIGN(4096);\n  \/DISCARD\/ :\n  {\n    *(.rel.reloc)\n    *(.eh_frame)\n    *(.note.GNU-stack)\n  }\n  .comment 0 : { *(.comment) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS\n{\n  .text 0x0 : {\n    *(.text.head)\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t.*)\n    *(.srodata)\n    *(.rodata*)\n    . = ALIGN(16);\n    _etext = .;\n  }\n  .dynamic  : { *(.dynamic) }\n  .data :\n  {\n   *(.sdata)\n   *(.data)\n   *(.data1)\n   *(.data)\n   *(.got.plt)\n   *(.got)\n\n   \/* the EFI loader doesn't seem to like a .bss section, so we stick\n      it all into .data: *\/\n   . = ALIGN(16);\n   _bss = .;\n   *(.sbss)\n   *(.scommon)\n   *(.dynbss)\n   *(.bss)\n   *(COMMON)\n   . = ALIGN(16);\n   _bss_end = .;\n  }\n\n   . = ALIGN(4096);\n  .vendor_cert :\n  {\n    *(.vendor_cert)\n  }\n  . = ALIGN(4096);\n\n  .rel.dyn : { *(.rel.dyn) }\n  .rel.plt : { *(.rel.plt) }\n  .rel.got : { *(.rel.got) }\n  .rel.data : { *(.rel.data) *(.rel.data*) }\n  _edata = .;\n  _data_size = . - _etext;\n\n  . = ALIGN(4096);\n  .dynsym   : { *(.dynsym) }\n  . = ALIGN(4096);\n  .dynstr   : { *(.dynstr) }\n  . = ALIGN(4096);\n  \/DISCARD\/ :\n  {\n    *(.rel.reloc)\n    *(.eh_frame)\n    *(.note.GNU-stack)\n  }\n  .comment 0 : { *(.comment) }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"615703423ef5e2c1129dcba96f52b0198b8041b8","subject":"arch\/x86: always make BSS section MMU page align if X86_MMU","message":"arch\/x86: always make BSS section MMU page align if X86_MMU\n\nIf MMU is enabled, always make the BSS section MMU page aligned.\nAccording to the comments, it is always aligned anyway.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"nashif\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,punitvara\/zephyr,kraj\/zephyr,nashif\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,galak\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,ldts\/zephyr,galak\/zephyr,explora26\/zephyr,kraj\/zephyr,ldts\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,explora26\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,punitvara\/zephyr,finikorg\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,ldts\/zephyr,galak\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,kraj\/zephyr","old_file":"include\/arch\/x86\/linker.ld","new_file":"include\/arch\/x86\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n#ifdef CONFIG_REALMODE\n\t\/* 16-bit sections *\/\n\t. = PHYS_RAM_ADDR;\n\n\tSECTION_PROLOGUE(boot, (OPTIONAL),)\n\t{\n\t*(.boot)\n\t. = ALIGN(16);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\t. = ALIGN(8);\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#ifndef CONFIG_REALMODE\n\t_image_text_start = PHYS_LOAD_ADDR;\n#else\n\t_image_text_start = .;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMMU_PAGE_ALIGN\n#ifdef CONFIG_XIP\n\t\/* Kernel ROM extends to the end of flash. Need to do this to program\n\t * the MMU\n\t *\/\n\t_image_rom_end = _image_rom_start + KB(CONFIG_ROM_SIZE);\n#else\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t_image_rom_end = .;\n#endif\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\t\/* APP SHARED MEMORY REGION *\/\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\tMMU_PAGE_ALIGN\n\t\t_app_smem_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n#ifndef CONFIG_XIP\n\t\tMMU_PAGE_ALIGN\n#endif\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t\tMMU_PAGE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\tMMU_PAGE_ALIGN\n\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n\n#ifdef CONFIG_X86_MMU\n\t\/* Can't really predict the size of this section. Anything after this\n\t * should not be affected if addresses change between builds (currently\n\t * just the gperf tables which is fine).\n\t *\n\t * However, __mmu_tables_start *must* remain stable between builds,\n\t * we can't have anything shifting the memory map beforehand.\n\t *\/\n\tSECTION_DATA_PROLOGUE(mmu_tables, (OPTIONAL),)\n\t{\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu_x86.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n#ifdef CONFIG_REALMODE\n\t\/* 16-bit sections *\/\n\t. = PHYS_RAM_ADDR;\n\n\tSECTION_PROLOGUE(boot, (OPTIONAL),)\n\t{\n\t*(.boot)\n\t. = ALIGN(16);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\t. = ALIGN(8);\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#ifndef CONFIG_REALMODE\n\t_image_text_start = PHYS_LOAD_ADDR;\n#else\n\t_image_text_start = .;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMMU_PAGE_ALIGN\n#ifdef CONFIG_XIP\n\t\/* Kernel ROM extends to the end of flash. Need to do this to program\n\t * the MMU\n\t *\/\n\t_image_rom_end = _image_rom_start + KB(CONFIG_ROM_SIZE);\n#else\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t_image_rom_end = .;\n#endif\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\t\/* APP SHARED MEMORY REGION *\/\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\tMMU_PAGE_ALIGN\n\t\t_app_smem_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n#ifndef CONFIG_XIP\n\t\tMMU_PAGE_ALIGN\n#endif\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t\tMMU_PAGE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * Without Jailhouse, we get the page alignment here for free by\n\t * definition of the beginning of the \"RAMable\" region on the board\n\t * configurations. With Jailhouse, everything falls in RAM and we\n\t * try to glue sections in sequence, thus we have to realign here so\n\t * that gen_mmu.py does not complain.\n\t *\/\n#ifdef CONFIG_JAILHOUSE\n\tMMU_PAGE_ALIGN\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n\n#ifdef CONFIG_X86_MMU\n\t\/* Can't really predict the size of this section. Anything after this\n\t * should not be affected if addresses change between builds (currently\n\t * just the gperf tables which is fine).\n\t *\n\t * However, __mmu_tables_start *must* remain stable between builds,\n\t * we can't have anything shifting the memory map beforehand.\n\t *\/\n\tSECTION_DATA_PROLOGUE(mmu_tables, (OPTIONAL),)\n\t{\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu_x86.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6ff292ea8bc241f741ab9b3ef1887c6cfe7a40da","subject":"base address of 0x80300000","message":"base address of 0x80300000\n","repos":"matildah\/octocabbit","old_file":"src\/kernel.ld","new_file":"src\/kernel.ld","new_contents":"ENTRY(asm_entry)\nSECTIONS\n{\n    . = 0x80300000;\n    .startup : { startup.o(.text) }\n    .text : { *(.text) }\n    .data : { *(.data) }\n    .bss : { *(.bss COMMON) }\n    . = ALIGN(8);\n    . = . + 0x1000; \/* 4 kB for supervisor stack *\/\n    svc_stack = .;\n    . = . + 0x1000; \/* 4 kB for user stack *\/\n    usr_stack = .;\n}\n","old_contents":"ENTRY(asm_entry)\nSECTIONS\n{\n    . = 0x10000;\n    .startup : { startup.o(.text) }\n    .text : { *(.text) }\n    .data : { *(.data) }\n    .bss : { *(.bss COMMON) }\n    . = ALIGN(8);\n    . = . + 0x1000; \/* 4 kB for supervisor stack *\/\n    svc_stack = .;\n    . = . + 0x1000; \/* 4 kB for user stack *\/\n    usr_stack = .;\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"ba64d8281894290b5642474ad9fb27744286701e","subject":"Make kstart the aarch64 entry point","message":"Make kstart the aarch64 entry point\n","repos":"redox-os\/kernel,redox-os\/kernel,redox-os\/kernel","old_file":"linkers\/aarch64.ld","new_file":"linkers\/aarch64.ld","new_contents":"ENTRY(kstart)\nOUTPUT_FORMAT(\"elf64-littleaarch64\", \"elf64-littleaarch64\", \"elf64-littleaarch64\")\n\nKERNEL_OFFSET = 0xFFFFFF0000000000;\n\nSECTIONS {\n    . = KERNEL_OFFSET;\n\n    . += SIZEOF_HEADERS;\n    . = ALIGN(4096);\n\n    .text : AT(ADDR(.text) - KERNEL_OFFSET) {\n        __text_start = .;\n\t*(.early_init.text*)\n\t. = ALIGN(4096);\n        *(.text*)\n\t. = ALIGN(4096);\n        __text_end = .;\n    }\n\n\t.rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) {\n        __rodata_start = .;\n        *(.rodata*)\n\t. = ALIGN(4096);\n        __rodata_end = .;\n    }\n\n    .data : AT(ADDR(.data) - KERNEL_OFFSET) {\n        __data_start = .;\n        *(.data*)\n\t. = ALIGN(4096);\n        __data_end = .;\n        __bss_start = .;\n        *(.bss*)\n\t. = ALIGN(4096);\n        __bss_end = .;\n    }\n\n    .tdata : AT(ADDR(.tdata) - KERNEL_OFFSET) {\n        __tdata_start = .;\n        *(.tdata*)\n\t. = ALIGN(4096);\n        __tdata_end = .;\n        __tbss_start = .;\n        *(.tbss*)\n        . += 8;\n\t. = ALIGN(4096);\n        __tbss_end = .;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ : {\n        *(.comment*)\n        *(.eh_frame*)\n        *(.gcc_except_table*)\n        *(.note*)\n        *(.rel.eh_frame*)\n    }\n}\n","old_contents":"ENTRY(early_init)\nOUTPUT_FORMAT(\"elf64-littleaarch64\", \"elf64-littleaarch64\", \"elf64-littleaarch64\")\n\nKERNEL_OFFSET = 0xFFFFFF0000000000;\n\nSECTIONS {\n    . = KERNEL_OFFSET;\n\n    . += SIZEOF_HEADERS;\n    . = ALIGN(4096);\n\n    .text : AT(ADDR(.text) - KERNEL_OFFSET) {\n        __text_start = .;\n\t*(.early_init.text*)\n\t. = ALIGN(4096);\n        *(.text*)\n\t. = ALIGN(4096);\n        __text_end = .;\n    }\n\n\t.rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) {\n        __rodata_start = .;\n        *(.rodata*)\n\t. = ALIGN(4096);\n        __rodata_end = .;\n    }\n\n    .data : AT(ADDR(.data) - KERNEL_OFFSET) {\n        __data_start = .;\n        *(.data*)\n\t. = ALIGN(4096);\n        __data_end = .;\n        __bss_start = .;\n        *(.bss*)\n\t. = ALIGN(4096);\n        __bss_end = .;\n    }\n\n    .tdata : AT(ADDR(.tdata) - KERNEL_OFFSET) {\n        __tdata_start = .;\n        *(.tdata*)\n\t. = ALIGN(4096);\n        __tdata_end = .;\n        __tbss_start = .;\n        *(.tbss*)\n        . += 8;\n\t. = ALIGN(4096);\n        __tbss_end = .;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ : {\n        *(.comment*)\n        *(.eh_frame*)\n        *(.gcc_except_table*)\n        *(.note*)\n        *(.rel.eh_frame*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e287c650966f1e8a0536c3fb98335edb3ab99984","subject":"Correct the .bss end setting.","message":"Correct the .bss end setting.\n\ngit-svn-id: 43aea61533866f88f23079d48f4f5dc2d5288937@496 1d2547de-c912-0410-9cb9-b8ca96c0e9e2\n","repos":"Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS","old_file":"Demo\/ARM7_LPC2368_Eclipse\/RTOSDemo\/lpc2368.ld","new_file":"Demo\/ARM7_LPC2368_Eclipse\/RTOSDemo\/lpc2368.ld","new_contents":"MEMORY \r\n{\r\n\tflash\t: ORIGIN = 0x00000000, LENGTH = 500K\r\n\tram\t: ORIGIN = 0x40000000, LENGTH = 32K\r\n\tusbram   : ORIGIN = 0x7FD00000, LENGTH = 8K\r\n\tethram   : ORIGIN = 0x7FE00000, LENGTH = 16K\r\n}\r\n\r\n__stack_end__ = 0x40000000 + 32K - 4;\r\n\r\nSECTIONS \r\n{\r\n\t. = 0;\r\n\tstartup : { *(.startup)} >flash\r\n\r\n\tprog : \r\n\t{\r\n\t\t*(.text)\r\n\t\t*(.rodata)\r\n\t\t*(.rodata*)\r\n\t\t*(.glue_7)\r\n\t\t*(.glue_7t)\r\n\t} >flash\r\n\r\n\t__end_of_text__ = .;\r\n\r\n\t.data : \r\n\t{\r\n\t\t__data_beg__ = .;\r\n\t\t__data_beg_src__ = __end_of_text__;\r\n\t\t*(.data)\r\n\t\t__data_end__ = .;\r\n\t} >ram AT>flash\r\n\r\n\t.bss : \r\n\t{\r\n\t\t__bss_beg__ = .;\r\n\t\t*(.bss)\r\n\t} >ram\r\n\r\n\t\/* Align here to ensure that the .bss section occupies space up to\r\n\t_end.  Align after .bss to ensure correct alignment even if the\r\n\t.bss section disappears because there are no input sections.  *\/\r\n\t. = ALIGN(32 \/ 8);\r\n\t_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r\n\r\n\t.usbram (NOLOAD):\r\n\t{\r\n\t__usbram_beg__ = .;\r\n\t*(.dmaram)\r\n\t\t__usbram_end__ = .;\r\n\t} >usbram\r\n\r\n\t.ethram (NOLOAD):\r\n\t{\r\n\t__ethram_beg__ = .;\r\n\t*(.ethram)\r\n\t\t__ethram_end__ = .;\r\n\t} >ethram\r\n\r\n\r\n}\r\n\t. = ALIGN(32 \/ 8);\r\n\t_end = .;\r\n\t\r\n\tPROVIDE (end = .);\r\n\r\n\r\n","old_contents":"MEMORY \r\n{\r\n\tflash\t: ORIGIN = 0x00000000, LENGTH = 500K\r\n\tram\t: ORIGIN = 0x40000000, LENGTH = 32K\r\n\tusbram   : ORIGIN = 0x7FD00000, LENGTH = 8K\r\n\tethram   : ORIGIN = 0x7FE00000, LENGTH = 16K\r\n}\r\n\r\n__stack_end__ = 0x40000000 + 32K - 4;\r\n\r\nSECTIONS \r\n{\r\n\t. = 0;\r\n\tstartup : { *(.startup)} >flash\r\n\r\n\tprog : \r\n\t{\r\n\t\t*(.text)\r\n\t\t*(.rodata)\r\n\t\t*(.rodata*)\r\n\t\t*(.glue_7)\r\n\t\t*(.glue_7t)\r\n\t} >flash\r\n\r\n\t__end_of_text__ = .;\r\n\r\n\t.data : \r\n\t{\r\n\t\t__data_beg__ = .;\r\n\t\t__data_beg_src__ = __end_of_text__;\r\n\t\t*(.data)\r\n\t\t__data_end__ = .;\r\n\t} >ram AT>flash\r\n\r\n\t.bss : \r\n\t{\r\n\t\t__bss_beg__ = .;\r\n\t\t*(.bss)\r\n\t} >ram\r\n\r\n\t\/* Align here to ensure that the .bss section occupies space up to\r\n\t_end.  Align after .bss to ensure correct alignment even if the\r\n\t.bss section disappears because there are no input sections.  *\/\r\n\t. = ALIGN(32 \/ 8);\r\n\r\n\t.usbram (NOLOAD):\r\n\t{\r\n\t__usbram_beg__ = .;\r\n\t*(.dmaram)\r\n\t\t__usbram_end__ = .;\r\n\t} >usbram\r\n\r\n\t.ethram (NOLOAD):\r\n\t{\r\n\t__ethram_beg__ = .;\r\n\t*(.ethram)\r\n\t\t__ethram_end__ = .;\r\n\t} >ethram\r\n\r\n\r\n}\r\n\t. = ALIGN(32 \/ 8);\r\n\t_end = .;\r\n\t_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r\n\tPROVIDE (end = .);\r\n\r\n\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c8280a9a88498473cfd0f18fb5e674d494245894","subject":"Allow to set custom RAM base address for emulator","message":"Allow to set custom RAM base address for emulator\n\nThis is needed when loading the emulator to RAM\nwith an offset.\n","repos":"SpinalHDL\/VexRiscv,SpinalHDL\/VexRiscv,SpinalHDL\/VexRiscv,SpinalHDL\/VexRiscv,SpinalHDL\/VexRiscv","old_file":"src\/main\/c\/common\/ram.ld","new_file":"src\/main\/c\/common\/ram.ld","new_contents":"OUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nMEMORY\n{\n  ram : ORIGIN = DEFINED(__ram_origin) ? __ram_origin : 0x80000000, LENGTH = 64k\n}\n\n\nSECTIONS\n{\n  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  }> ram\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n    *(.note.gnu.build-id)\n  } > ram\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } > ram\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > ram\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > ram\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > ram\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } > ram\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > ram\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } > ram\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } > ram\n\n  .data          :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n  } >ram\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n\n  .stack :\n  {\n    PROVIDE( _heap_end = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } > ram\n}\n","old_contents":"OUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nMEMORY\n{\n  ram : ORIGIN = 0x80000000, LENGTH = 64k\n}\n\n\nSECTIONS\n{\n  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  }> ram\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n    *(.note.gnu.build-id)\n  } > ram\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } > ram\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > ram\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > ram\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > ram\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } > ram\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > ram\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } > ram\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } > ram\n\n  .data          :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n  } >ram\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n\n  .stack :\n  {\n    PROVIDE( _heap_end = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } > ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ebc6bd1606b0abac16f939f78df64173bb8c15e4","subject":"Fix slot0 size in f3disco to avoid writing after end","message":"Fix slot0 size in f3disco to avoid writing after end\n\nSigned-off-by: Fabio Utzig <66676b1ceaf93296e098708c09494361103aa635@apache.org>\n","repos":"mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core","old_file":"hw\/bsp\/stm32f3discovery\/stm32f3discovery.ld","new_file":"hw\/bsp\/stm32f3discovery\/stm32f3discovery.ld","new_contents":"\/**\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n * \n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\nENTRY(Reset_Handler)\n\n\/*\n * Memory map\n *\/\nMEMORY {\n    FLASH (rx): ORIGIN = 0x08004000, LENGTH = 88K\n    CCRAM (rw): ORIGIN = 0x10000000, LENGTH = 8K\n    SRAM  (rw): ORIGIN = 0x20000000, LENGTH = 40K\n}\n\/*\n * Image header size - no bootloader support, no header.\n *\/\n_imghdr_size = 0x20;\n","old_contents":"\/**\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n * \n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\nENTRY(Reset_Handler)\n\n\/*\n * Memory map\n *\/\nMEMORY {\n    FLASH (rx): ORIGIN = 0x08004000, LENGTH = 240K\n    CCRAM (rw): ORIGIN = 0x10000000, LENGTH = 8K\n    SRAM  (rw): ORIGIN = 0x20000000, LENGTH = 40K\n}\n\/*\n * Image header size - no bootloader support, no header.\n *\/\n_imghdr_size = 0x20;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e6f03fcb9b30795e0f1fb5b890d478f5c1758089","subject":"add first linker setting","message":"add first linker setting\n","repos":"takuyaohashi\/tos","old_file":"test\/bsp\/lpc4357\/link.ld","new_file":"test\/bsp\/lpc4357\/link.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nMEMORY\n{\n\tRAM(wxai) : ORIGIN = 0x10000000, LENGTH = 0x8000\n}\nSECTIONS\n{\n\t.text : {\n\t      *(.vector)\n\t      *(.text .rodata)\n\t} > RAM\n\n\t.data : { *(.data) } > RAM\n\n\t.bss : {\n\t     _bss_start = .;\n\t     *(.bss)\n\t     _bss_end = .;\n\t} > RAM\n\t.stack : {\n\t\t. = . + 0x1000;\n\t\t. = ALIGN(4);\n\t\t_stack_top = .;\n\t\t. = . + 0x1000;\n\t\t. = ALIGN(4);\n\t\t_irq_stack_top = .;\n\t} > RAM\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nMEMORY\n{\n\tRAM(wxai) : ORIGIN = 0x10000000, LENGTH = 0x8000\n}\nSECTIONS\n{\n\t\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e1147ec787b177b1126d4984676804a443a8f295","subject":"cc2538: Set the type of the .nrdata output section to NOLOAD","message":"cc2538: Set the type of the .nrdata output section to NOLOAD\n\nThe .nrdata section is volatile, so its initialization must be controlled by the\napplication, and not be automatically done by the startup code. It should\nneither be zeroed like .bss, nor be initialized from data in flash memory like\n.data. This was already supposed to be the case, but the output section type of\n.nrdata was not set to NOLOAD, causing the generated ELF .nrdata section header\nto be of type PROGBITS instead of NOBITS, i.e. load data was generated to be\nprogrammed in RAM, thus producing huge unprogrammable .bin files.\n\nSigned-off-by: Beno\u00eet Th\u00e9baudeau <835bc8b01b82c0117127b72626b289641d7633e2@advansee.com>\n","repos":"bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,bluerover\/6lbr,arurke\/contiki","old_file":"cpu\/cc2538\/cc2538.lds","new_file":"cpu\/cc2538\/cc2538.lds","new_contents":"\/*\n * Copyright (c) 2013, Texas Instruments Incorporated - http:\/\/www.ti.com\/\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\/*\n * cc2538 linker configuration file. This is not the actual file used at link\n * stage. Rather, it is used as input for the auto-generation of the actual\n * ld script, which is called cc2538.ld and will be in the project directory\n *\/\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n#define NRSRAM_START    0x20000000\n#define NRSRAM_LEN      0x00004000\n#define SRAM_START      0x20004000\n#define SRAM_LEN        0x00004000\n#else\n#define SRAM_START      0x20000000\n#define SRAM_LEN        0x00008000\n#endif\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x200000, LENGTH = 0x0007FFD4\n    FLASH_CCA (RX) : ORIGIN = 0x0027FFD4, LENGTH = 44\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    NRSRAM (RWX) : ORIGIN = NRSRAM_START, LENGTH = NRSRAM_LEN\n#endif\n    SRAM (RWX) : ORIGIN = SRAM_START, LENGTH = SRAM_LEN\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH= 0\n\n    .data :\n    {\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > SRAM AT > FLASH\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n    } > FLASH\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    .nrdata (NOLOAD) :\n    {\n        _nrdata = .;\n        *(.nrdata*)\n        _enrdata = .;\n    } > NRSRAM\n#endif\n\n    .flashcca :\n    {\n        KEEP(*(.flashcca))\n    } > FLASH_CCA\n}\n","old_contents":"\/*\n * Copyright (c) 2013, Texas Instruments Incorporated - http:\/\/www.ti.com\/\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\/*\n * cc2538 linker configuration file. This is not the actual file used at link\n * stage. Rather, it is used as input for the auto-generation of the actual\n * ld script, which is called cc2538.ld and will be in the project directory\n *\/\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n#define NRSRAM_START    0x20000000\n#define NRSRAM_LEN      0x00004000\n#define SRAM_START      0x20004000\n#define SRAM_LEN        0x00004000\n#else\n#define SRAM_START      0x20000000\n#define SRAM_LEN        0x00008000\n#endif\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x200000, LENGTH = 0x0007FFD4\n    FLASH_CCA (RX) : ORIGIN = 0x0027FFD4, LENGTH = 44\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    NRSRAM (RWX) : ORIGIN = NRSRAM_START, LENGTH = NRSRAM_LEN\n#endif\n    SRAM (RWX) : ORIGIN = SRAM_START, LENGTH = SRAM_LEN\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH= 0\n\n    .data :\n    {\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > SRAM AT > FLASH\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n    } > FLASH\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    .nrdata :\n    {\n        _nrdata = .;\n        *(.nrdata*)\n        _enrdata = .;\n    } > NRSRAM\n#endif\n\n    .flashcca :\n    {\n        KEEP(*(.flashcca))\n    } > FLASH_CCA\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"51f50060f3b0960614c51a8d9599bfec035a1a22","subject":"Make linker script simpler; remove fini_array section","message":"Make linker script simpler; remove fini_array section\n","repos":"Mrokkk\/objective-kernel,Mrokkk\/objective-kernel","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(_start)\n\n__kernel_phys = 0x00100000;\n__kernel_virt = 0xC0100000;\n\n__kernel_offset = __kernel_virt - __kernel_phys;\n\nSECTIONS {\n\n    . = __kernel_phys;\n\n    .unpagged BLOCK(4K) : ALIGN(4K) {\n        __unpagged_start = .;\n        KEEP(*(.multiboot))\n        KEEP(*(.text.boot))\n        __unpagged_end = .;\n    }\n\n    . += __kernel_offset;\n\n    . = ALIGN(4K);\n    .text BLOCK(4K) : AT(ADDR(.text) - __kernel_offset) {\n        __text_start = .;\n        *(.text)\n        __text_end = .;\n    }\n\n    . = ALIGN(4K);\n    .rodata BLOCK(4K) : AT(ADDR(.rodata) - __kernel_offset) {\n        *(.rodata)\n    }\n\n    .init_array : AT(ADDR(.init_array) - __kernel_offset) {\n        __init_array_start = .;\n        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n        KEEP (*(.init_array .ctors))\n        __init_array_end = .;\n    }\n\n    . = ALIGN(4K);\n    .data BLOCK(4K) : AT(ADDR(.data) - __kernel_offset) {\n        __data_start = .;\n        *(.data)\n        __data_end = .;\n    }\n\n    . = ALIGN(4K);\n    .bss BLOCK(4K) : AT(ADDR(.bss) - __kernel_offset) {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.stack)\n        __bss_end = .;\n    }\n\n    . = ALIGN(4K);\n\n    __heap_start = .;\n\n}\n\n","old_contents":"ENTRY(_start)\n\n__kernel_phys = 0x00100000;\n__kernel_virt = 0xC0100000;\n\n__kernel_offset = __kernel_virt - __kernel_phys;\n\nSECTIONS {\n\n    . = __kernel_phys;\n\n    .unpagged BLOCK(4K) : ALIGN(4K) {\n        __unpagged_start = .;\n        KEEP(*(.multiboot))\n        KEEP(*(.text.boot))\n        __unpagged_end = .;\n    }\n\n    . += __kernel_offset;\n\n    . = ALIGN(4K);\n    .text BLOCK(4K) : AT(ADDR(.text) - __kernel_offset) {\n        __text_start = .;\n        *(.text)\n        __text_end = .;\n    }\n\n    . = ALIGN(4K);\n    .rodata BLOCK(4K) : AT(ADDR(.rodata) - __kernel_offset) {\n        *(.rodata)\n    }\n\n    .init_array : AT(ADDR(.init_array) - __kernel_offset) {\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n        KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n        PROVIDE_HIDDEN (__init_array_end = .);\n    }\n\n    .fini_array : AT(ADDR(.fini_array) - __kernel_offset) {\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n        KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n    }\n\n    . = ALIGN(4K);\n    .data BLOCK(4K) : AT(ADDR(.data) - __kernel_offset) {\n        __data_start = .;\n        *(.data)\n        __data_end = .;\n    }\n\n    . = ALIGN(4K);\n    .bss BLOCK(4K) : AT(ADDR(.bss) - __kernel_offset) {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.stack)\n        __bss_end = .;\n    }\n\n    . = ALIGN(4K);\n\n    __heap_start = .;\n\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"525123329bf5952da88ed44097ac3b0acce0ba3e","subject":"Skips linking components from the CS3 HAL that are not needed for the pic32mx.","message":"Skips linking components from the CS3 HAL that are not needed for the pic32mx.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/microchip-pic32mx-duinomitemega\/target.ld","new_file":"boards\/microchip-pic32mx-duinomitemega\/target.ld","new_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 64K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_userboot (rx) : ORIGIN = 0xBD000000, LENGTH = 0x1000\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0xBD001000, LENGTH = 512K - 4K \/*we skipped the first page to allow for the interrupt vector table. There is a lot of free space there, but linking needs to flow around existing absolute sections there. *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0xBFC00000, LENGTH = 0x0 \/* Don't allow stuff in the boot flash, there is a bootloader there *\/\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** TEMPORARY: located at end of bootflash for now (this is \"debug page\")...\r\n** 0xBFC03000-(0x10 config registers + 0x200+ (64 vectors * x20))= 0xBFC025F0\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0xBD000000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\n\/* EXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) *\/\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 9k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** First thing in  flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n  } >PIC32MX_flash_userboot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; \/* DRN updated this; seems correct... *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","old_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 64K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_userboot (rx) : ORIGIN = 0xBD000000, LENGTH = 0x1000\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0xBD001000, LENGTH = 512K - 4K \/*we skipped the first page to allow for the interrupt vector table. There is a lot of free space there, but linking needs to flow around existing absolute sections there. *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0xBFC00000, LENGTH = 0x0 \/* Don't allow stuff in the boot flash, there is a bootloader there *\/\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** TEMPORARY: located at end of bootflash for now (this is \"debug page\")...\r\n** 0xBFC03000-(0x10 config registers + 0x200+ (64 vectors * x20))= 0xBFC025F0\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0xBD000000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 9k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** First thing in  flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n  } >PIC32MX_flash_userboot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; \/* DRN updated this; seems correct... *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"5760fc041f3459178b4fecd2a5b447d52605f781","subject":"adjusted LD RAM for new nrf module","message":"adjusted LD RAM for new nrf module\n","repos":"electronut\/blebot","old_file":"nrf51_breakout\/s110\/armgcc\/ble_app_uart_gcc_nrf51.ld","new_file":"nrf51_breakout\/s110\/armgcc\/ble_app_uart_gcc_nrf51.ld","new_contents":"\/* Linker script to configure memory regions. *\/\r\n\r\nSEARCH_DIR(.)\r\nGROUP(-lgcc -lc -lnosys)\r\n\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x18000, LENGTH = 0x28000\r\n  RAM (rwx) :  ORIGIN = 0x20002000, LENGTH = 0x6000\r\n}\r\n\r\nINCLUDE \"gcc_nrf51_common.ld\"\r\n","old_contents":"\/* Linker script to configure memory regions. *\/\r\n\r\nSEARCH_DIR(.)\r\nGROUP(-lgcc -lc -lnosys)\r\n\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x18000, LENGTH = 0x28000\r\n  RAM (rwx) :  ORIGIN = 0x20002000, LENGTH = 0x2000\r\n}\r\n\r\nINCLUDE \"gcc_nrf51_common.ld\"\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c2fa1633227cd4a6286f0b3243329b5df57b0b9e","subject":"reserved topmost 32 bytes of RAM used by IAP functions","message":"reserved topmost 32 bytes of RAM used by IAP functions\n\nNXP LPC176x\/5x User Manual UM10360 Rev 4.1:\r\n32.3.2.8 RAM used by IAP command handler\r\nFlash programming commands use the top 32 bytes of on-chip RAM. The maximum stack \r\nusage in the user allocated stack space is 128 bytes and it grows downwards.","repos":"pradeep-gr\/mbed-os5-onsemi,nRFMesh\/mbed-os,betzw\/mbed-os,fahhem\/mbed-os,mikaleppanen\/mbed-os,kl-cruz\/mbed-os,YarivCol\/mbed-os,catiedev\/mbed-os,fahhem\/mbed-os,bcostm\/mbed-os,ryankurte\/mbed-os,mmorenobarm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,mbedmicro\/mbed,YarivCol\/mbed-os,karsev\/mbed-os,mbedmicro\/mbed,mmorenobarm\/mbed-os,HeadsUpDisplayInc\/mbed,screamerbg\/mbed,monkiineko\/mbed-os,andcor02\/mbed-os,mmorenobarm\/mbed-os,catiedev\/mbed-os,catiedev\/mbed-os,screamerbg\/mbed,Archcady\/mbed-os,karsev\/mbed-os,HeadsUpDisplayInc\/mbed,catiedev\/mbed-os,pradeep-gr\/mbed-os5-onsemi,catiedev\/mbed-os,adamgreen\/mbed,adamgreen\/mbed,karsev\/mbed-os,arostm\/mbed-os,netzimme\/mbed-os,mikaleppanen\/mbed-os,nRFMesh\/mbed-os,c1728p9\/mbed-os,monkiineko\/mbed-os,fahhem\/mbed-os,netzimme\/mbed-os,mazimkhan\/mbed-os,adamgreen\/mbed,kjbracey-arm\/mbed,mmorenobarm\/mbed-os,betzw\/mbed-os,HeadsUpDisplayInc\/mbed,mazimkhan\/mbed-os,infinnovation\/mbed-os,karsev\/mbed-os,NXPmicro\/mbed,monkiineko\/mbed-os,pradeep-gr\/mbed-os5-onsemi,andcor02\/mbed-os,adamgreen\/mbed,svogl\/mbed-os,netzimme\/mbed-os,fahhem\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,mbedmicro\/mbed,monkiineko\/mbed-os,nRFMesh\/mbed-os,CalSol\/mbed,bcostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,andcor02\/mbed-os,svogl\/mbed-os,Archcady\/mbed-os,screamerbg\/mbed,NXPmicro\/mbed,nRFMesh\/mbed-os,HeadsUpDisplayInc\/mbed,svogl\/mbed-os,kl-cruz\/mbed-os,mazimkhan\/mbed-os,infinnovation\/mbed-os,pradeep-gr\/mbed-os5-onsemi,adamgreen\/mbed,arostm\/mbed-os,CalSol\/mbed,ryankurte\/mbed-os,YarivCol\/mbed-os,screamerbg\/mbed,mikaleppanen\/mbed-os,mazimkhan\/mbed-os,netzimme\/mbed-os,kjbracey-arm\/mbed,YarivCol\/mbed-os,netzimme\/mbed-os,bcostm\/mbed-os,andcor02\/mbed-os,netzimme\/mbed-os,betzw\/mbed-os,kl-cruz\/mbed-os,adamgreen\/mbed,mikaleppanen\/mbed-os,kl-cruz\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,ryankurte\/mbed-os,c1728p9\/mbed-os,fahhem\/mbed-os,HeadsUpDisplayInc\/mbed,YarivCol\/mbed-os,CalSol\/mbed,arostm\/mbed-os,arostm\/mbed-os,nRFMesh\/mbed-os,kjbracey-arm\/mbed,svogl\/mbed-os,CalSol\/mbed,NXPmicro\/mbed,mmorenobarm\/mbed-os,arostm\/mbed-os,arostm\/mbed-os,andcor02\/mbed-os,Archcady\/mbed-os,monkiineko\/mbed-os,fahhem\/mbed-os,andcor02\/mbed-os,kl-cruz\/mbed-os,bcostm\/mbed-os,NXPmicro\/mbed,CalSol\/mbed,screamerbg\/mbed,mbedmicro\/mbed,bcostm\/mbed-os,ryankurte\/mbed-os,Archcady\/mbed-os,NXPmicro\/mbed,Archcady\/mbed-os,nRFMesh\/mbed-os,mazimkhan\/mbed-os,betzw\/mbed-os,mazimkhan\/mbed-os,bcostm\/mbed-os,kl-cruz\/mbed-os,mbedmicro\/mbed,betzw\/mbed-os,ryankurte\/mbed-os,svogl\/mbed-os,mikaleppanen\/mbed-os,infinnovation\/mbed-os,monkiineko\/mbed-os,Archcady\/mbed-os,mmorenobarm\/mbed-os,karsev\/mbed-os,mikaleppanen\/mbed-os,screamerbg\/mbed,infinnovation\/mbed-os,betzw\/mbed-os,infinnovation\/mbed-os,ryankurte\/mbed-os,svogl\/mbed-os,NXPmicro\/mbed,HeadsUpDisplayInc\/mbed,catiedev\/mbed-os,infinnovation\/mbed-os,CalSol\/mbed,YarivCol\/mbed-os,kjbracey-arm\/mbed,karsev\/mbed-os","old_file":"targets\/TARGET_NXP\/TARGET_LPC176X\/device\/TOOLCHAIN_GCC_ARM\/TARGET_XBED_LPC1768\/XBED_LPC1768.ld","new_file":"targets\/TARGET_NXP\/TARGET_LPC176X\/device\/TOOLCHAIN_GCC_ARM\/TARGET_XBED_LPC1768\/XBED_LPC1768.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00002000, LENGTH = 504K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8 - 32)  \/* topmost 32 bytes used by IAP functions *\/\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Code can explicitly ask for data to be \n       placed in these higher RAM banks where\n       they will be left uninitialized. \n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00002000, LENGTH = 504K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Code can explicitly ask for data to be \n       placed in these higher RAM banks where\n       they will be left uninitialized. \n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"828274956b104c22fa21924a6d6166cf8c709169","subject":"updated s130 linker script","message":"updated s130 linker script\n","repos":"Tech4Race\/nrf5x-base,lab11\/nrf5x-base,Tech4Race\/nrf5x-base,lab11\/nrf5x-base,Tech4Race\/nrf5x-base,lab11\/nrf5x-base,Tech4Race\/nrf5x-base,lab11\/nrf5x-base","old_file":"make\/ld\/gcc_nrf51_s130_1.0.0_32_256.ld","new_file":"make\/ld\/gcc_nrf51_s130_1.0.0_32_256.ld","new_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0 + 108K + 4K, LENGTH = 256K - 112K \/* 112 kB is taken by S130, 144 kB for app. *\/\n  RAM (rwx) : ORIGIN = 0x20000000 + 10K, LENGTH = 32K - 10K \/* 10 kB is taken by S130, 22 kB for app. *\/\n}\nINCLUDE \"gcc_nrf51_common.ld\"\n","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x18000, LENGTH = 0x28000\n  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x6000\n}\nINCLUDE \"gcc_nrf51_common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a6f1a35a183b80204fba0f6f76c388cdc6044653","subject":"Let LDoc try to use Discount","message":"Let LDoc try to use Discount\n","repos":"Kazuo256\/luxproject","old_file":"config.ld","new_file":"config.ld","new_contents":"\nproject = \"LUX\"\n\ndescription = \"A Lua Utility eXTension library\"\n\nfile = \"lib\"\ndir = \"doc\"\n\nexamples = \"examples\"\nformat = \"discount\"\n\n","old_contents":"\nproject = \"LUX\"\n\nfile = \"lib\"\n\ndir = \"doc\"\n\nexamples = \"examples\"\n\nformat = \"markdown\"\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0a281969f4d84a22fb3a0e8e513233e7b483678d","subject":"sections .eh_frame and .comment in ELF being discarded","message":"sections .eh_frame and .comment in ELF being discarded\n","repos":"m-rinaldi\/emuk86,m-rinaldi\/emuk86","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\")\nENTRY(_startup)\nSTARTUP(startup.o)\n\nSECTIONS \n{\n    \/DISCARD\/ : {\n        *(.eh_frame)\n        *(.comment)\n    }\n\n    \/*          VMA                 LMA           *\/\n    .text.start (0xc0000000)    :   AT(0x00100000) {\n        startup.o(.text)\n    }\n\n    .text : ALIGN(0x1000) {\n        KERNEL_START        = .;\n        KERNEL_TEXT_START   = .;\n            *(.text)\n        KERNEL_TEXT_END     = .;\n    }\n\n    .data : ALIGN(0x1000) {\n        KERNEL_DATA_START   = .;\n            *(.data)\n        KERNEL_DATA_END     = .;\n    }\n\n    .bss : ALIGN(0x1000) {\n        KERNEL_BSS_START    = .;\n            *(.bss)\n        KERNEL_BSS_END      = .;\n\n    }\n  \n    \/* make sure a free page is left in between to detect illegal accesses *\/\n    . += 4K;\n    \n    \/* the kernel stack *\/\n    .stack : ALIGN(0x1000) {\n        KERNEL_STACK_START  = .;\n        KERNEL_STACK_BOTTOM = .;\n            . += 4K;\n        KERNEL_STACK_END    = .;\n        KERNEL_STACK_TOP    = .;\n    }\n    KERNEL_END              = .;\n}\n\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\")\nENTRY(_startup)\nSTARTUP(startup.o)\n\nSECTIONS \n{\n    \/*          VMA                 LMA           *\/\n    .text.start (0xc0000000)    :   AT(0x00100000) {\n        startup.o(.text)\n    }\n\n    .text : ALIGN(0x1000) {\n        KERNEL_START        = .;\n        KERNEL_TEXT_START   = .;\n            *(.text)\n        KERNEL_TEXT_END     = .;\n    }\n\n    .data : ALIGN(0x1000) {\n        KERNEL_DATA_START   = .;\n            *(.data)\n        KERNEL_DATA_END     = .;\n    }\n\n    .bss : ALIGN(0x1000) {\n        KERNEL_BSS_START    = .;\n            *(.bss)\n        KERNEL_BSS_END      = .;\n\n    }\n  \n    \/* make sure a free page is left in between to detect illegal accesses *\/\n    . += 4K;\n    \n    \/* the kernel stack *\/\n    .stack : ALIGN(0x1000) {\n        KERNEL_STACK_START  = .;\n        KERNEL_STACK_BOTTOM = .;\n            . += 4K;\n        KERNEL_STACK_END    = .;\n        KERNEL_STACK_TOP    = .;\n    }\n    KERNEL_END              = .;\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"505e184ee5707fced4c07351a65235248ee26537","subject":"cpu\/nrf51822: changed ISR stack size to 512 byte","message":"cpu\/nrf51822: changed ISR stack size to 512 byte\n","repos":"luciotorre\/RIOT,altairpearl\/RIOT,AnonMall\/RIOT,adrianghc\/RIOT,sumanpanchal\/RIOT,ximus\/RIOT,MonsterCode8000\/RIOT,rajma996\/RIOT,gbarnett\/RIOT,josephnoir\/RIOT,sgso\/RIOT,hamilton-mote\/RIOT-OS,Lexandro92\/RIOT-CoAP,jremmert-phytec-iot\/RIOT,cladmi\/RIOT,immesys\/RiSyn,d00616\/RIOT,mtausig\/RIOT,bartfaizoltan\/RIOT,EmuxEvans\/RIOT,watr-li\/RIOT,abp719\/RIOT,thiagohd\/RIOT,zhuoshuguo\/RIOT,asanka-code\/RIOT,marcosalm\/RIOT,basilfx\/RIOT,stevenj\/RIOT,haoyangyu\/RIOT,kYc0o\/RIOT,Ell-i\/RIOT,OlegHahm\/RIOT,smlng\/RIOT,lazytech-org\/RIOT,stevenj\/RIOT,katezilla\/RIOT,malosek\/RIOT,TobiasFredersdorf\/RIOT,khhhh\/RIOT,openkosmosorg\/RIOT,ntrtrung\/RIOT,gautric\/RIOT,kushalsingh007\/RIOT,fnack\/RIOT,toonst\/RIOT,rousselk\/RIOT,Hyungsin\/RIOT-OS,alex1818\/RIOT,DipSwitch\/RIOT,luciotorre\/RIOT,rfswarm2\/RIOT,adrianghc\/RIOT,neiljay\/RIOT,BytesGalore\/RIOT,changbiao\/RIOT,arvindpdmn\/RIOT,gbarnett\/RIOT,ant9000\/RIOT,ant9000\/RIOT,OTAkeys\/RIOT,mtausig\/RIOT,arvindpdmn\/RIOT,jhollister\/RIOT,kYc0o\/RIOT,roberthartung\/RIOT,haoyangyu\/RIOT,FrancescoErmini\/RIOT,1blankz7\/RIOT,x3ro\/RIOT,Darredevil\/RIOT,binarylemon\/RIOT,stevenj\/RIOT,alex1818\/RIOT,AnonMall\/RIOT,jbeyerstedt\/RIOT-OTA-update,mtausig\/RIOT,dailab\/RIOT,abp719\/RIOT,LudwigOrtmann\/RIOT,biboc\/RIOT,authmillenon\/RIOT,kbumsik\/RIOT,avmelnikoff\/RIOT,EmuxEvans\/RIOT,JensErdmann\/RIOT,kb2ma\/RIOT,openkosmosorg\/RIOT,koenning\/RIOT,adjih\/RIOT,aeneby\/RIOT,kaleb-himes\/RIOT,abkam07\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,jhollister\/RIOT,kbumsik\/RIOT,basilfx\/RIOT,thiagohd\/RIOT,aeneby\/RIOT,MohmadAyman\/RIOT,RubikonAlpha\/RIOT,l3nko\/RIOT,khhhh\/RIOT,Darredevil\/RIOT,sgso\/RIOT,immesys\/RiSyn,FrancescoErmini\/RIOT,kushalsingh007\/RIOT,l3nko\/RIOT,TobiasFredersdorf\/RIOT,yogo1212\/RIOT,RIOT-OS\/RIOT,patkan\/RIOT,alex1818\/RIOT,d00616\/RIOT,koenning\/RIOT,brettswann\/RIOT,dkm\/RIOT,nsol-nmsu\/RIOT,jhollister\/RIOT,phiros\/RIOT,rfswarm\/RIOT,ks156\/RIOT,phiros\/RIOT,gebart\/RIOT,patkan\/RIOT,x3ro\/RIOT,centurysys\/RIOT,haoyangyu\/RIOT,neumodisch\/RIOT,watr-li\/RIOT,tdautc19841202\/RIOT,katezilla\/RIOT,PSHIVANI\/Riot-Code,foss-for-synopsys-dwc-arc-processors\/RIOT,changbiao\/RIOT,herrfz\/RIOT-old,marcosalm\/RIOT,OlegHahm\/RIOT,smlng\/RIOT,herrfz\/RIOT-old,RBartz\/RIOT,backenklee\/RIOT,kbumsik\/RIOT,adjih\/RIOT,jbeyerstedt\/RIOT-OTA-update,attdona\/RIOT,roberthartung\/RIOT,asanka-code\/RIOT,jferreir\/RIOT,daniel-k\/RIOT,x3ro\/RIOT,aeneby\/RIOT,latsku\/RIOT,Osblouf\/RIOT,mziegert\/RIOT,bartfaizoltan\/RIOT,Osblouf\/RIOT,lebrush\/RIOT,herrfz\/RIOT,tfar\/RIOT,katezilla\/RIOT,LudwigOrtmann\/RIOT,rousselk\/RIOT,koenning\/RIOT,adrianghc\/RIOT,abkam07\/RIOT,ThanhVic\/RIOT,jfischer-phytec-iot\/RIOT,yogo1212\/RIOT,stevenj\/RIOT,TobiasFredersdorf\/RIOT,plushvoxel\/RIOT,dhruvvyas90\/RIOT,RubikonAlpha\/RIOT,Darredevil\/RIOT,luciotorre\/RIOT,Yonezawa-T2\/RIOT,thomaseichinger\/RIOT,kb2ma\/RIOT,mfrey\/RIOT,JensErdmann\/RIOT,gautric\/RIOT,backenklee\/RIOT,hamilton-mote\/RIOT-OS,chris-wood\/RIOT,RIOT-OS\/RIOT,A-Paul\/RIOT,dhruvvyas90\/RIOT,altairpearl\/RIOT,beurdouche\/RIOT,DipSwitch\/RIOT,lazytech-org\/RIOT,rfswarm\/RIOT,binarylemon\/RIOT,OTAkeys\/RIOT,MonsterCode8000\/RIOT,chris-wood\/RIOT,plushvoxel\/RIOT,1blankz7\/RIOT,backenklee\/RIOT,changbiao\/RIOT,abp719\/RIOT,alex1818\/RIOT,yogo1212\/RIOT,bartfaizoltan\/RIOT,centurysys\/RIOT,automote\/RIOT,fnack\/RIOT,DipSwitch\/RIOT,authmillenon\/RIOT,JensErdmann\/RIOT,zhuoshuguo\/RIOT,avmelnikoff\/RIOT,MarkXYang\/RIOT,rajma996\/RIOT,koenning\/RIOT,rfswarm2\/RIOT,authmillenon\/RIOT,dailab\/RIOT,DipSwitch\/RIOT,FrancescoErmini\/RIOT,marcosalm\/RIOT,adrianghc\/RIOT,backenklee\/RIOT,abp719\/RIOT,biboc\/RIOT,A-Paul\/RIOT,jremmert-phytec-iot\/RIOT,rajma996\/RIOT,adrianghc\/RIOT,rakendrathapa\/RIOT,kaleb-himes\/RIOT,lebrush\/RIOT,chris-wood\/RIOT,rfuentess\/RIOT,josephnoir\/RIOT,luciotorre\/RIOT,marcosalm\/RIOT,A-Paul\/RIOT,rajma996\/RIOT,hamilton-mote\/RIOT-OS,avmelnikoff\/RIOT,hamilton-mote\/RIOT-OS,BytesGalore\/RIOT,shady33\/RIOT,phiros\/RIOT,lazytech-org\/RIOT,neiljay\/RIOT,thomaseichinger\/RIOT,basilfx\/RIOT,emmanuelsearch\/RIOT,l3nko\/RIOT,Hyungsin\/RIOT-OS,foss-for-synopsys-dwc-arc-processors\/RIOT,mfrey\/RIOT,ntrtrung\/RIOT,neumodisch\/RIOT,neumodisch\/RIOT,tfar\/RIOT,smlng\/RIOT,toonst\/RIOT,adjih\/RIOT,jasonatran\/RIOT,ks156\/RIOT,brettswann\/RIOT,plushvoxel\/RIOT,herrfz\/RIOT,PSHIVANI\/Riot-Code,luciotorre\/RIOT,RBartz\/RIOT,dkm\/RIOT,l3nko\/RIOT,dkm\/RIOT,mfrey\/RIOT,msolters\/RIOT,MonsterCode8000\/RIOT,centurysys\/RIOT,Josar\/RIOT,FrancescoErmini\/RIOT,lazytech-org\/RIOT,Yonezawa-T2\/RIOT,rfswarm2\/RIOT,cladmi\/RIOT,EmuxEvans\/RIOT,plushvoxel\/RIOT,beurdouche\/RIOT,alex1818\/RIOT,jfischer-phytec-iot\/RIOT,koenning\/RIOT,rfswarm2\/RIOT,smlng\/RIOT,gautric\/RIOT,tfar\/RIOT,tdautc19841202\/RIOT,mziegert\/RIOT,wentaoshang\/RIOT,roberthartung\/RIOT,alex1818\/RIOT,Lexandro92\/RIOT-CoAP,bartfaizoltan\/RIOT,adjih\/RIOT,ximus\/RIOT,ThanhVic\/RIOT,Osblouf\/RIOT,patkan\/RIOT,plushvoxel\/RIOT,Hyungsin\/RIOT-OS,shady33\/RIOT,1blankz7\/RIOT,ant9000\/RIOT,gebart\/RIOT,attdona\/RIOT,brettswann\/RIOT,immesys\/RiSyn,RBartz\/RIOT,beurdouche\/RIOT,yogo1212\/RIOT,nsol-nmsu\/RIOT,AnonMall\/RIOT,katezilla\/RIOT,dhruvvyas90\/RIOT,BytesGalore\/RIOT,RBartz\/RIOT,alignan\/RIOT,kaspar030\/RIOT,toonst\/RIOT,jasonatran\/RIOT,MarkXYang\/RIOT,jasonatran\/RIOT,marcosalm\/RIOT,LudwigOrtmann\/RIOT,jremmert-phytec-iot\/RIOT,kb2ma\/RIOT,cladmi\/RIOT,biboc\/RIOT,LudwigOrtmann\/RIOT,openkosmosorg\/RIOT,alignan\/RIOT,centurysys\/RIOT,thiagohd\/RIOT,attdona\/RIOT,kerneltask\/RIOT,BytesGalore\/RIOT,toonst\/RIOT,rajma996\/RIOT,lebrush\/RIOT,avmelnikoff\/RIOT,herrfz\/RIOT,benoit-canet\/RIOT,RubikonAlpha\/RIOT,jhollister\/RIOT,emmanuelsearch\/RIOT,asanka-code\/RIOT,zhuoshuguo\/RIOT,miri64\/RIOT,chris-wood\/RIOT,sumanpanchal\/RIOT,Yonezawa-T2\/RIOT,nsol-nmsu\/RIOT,roberthartung\/RIOT,jbeyerstedt\/RIOT-OTA-update,zhuoshuguo\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,dhruvvyas90\/RIOT,openkosmosorg\/RIOT,shady33\/RIOT,authmillenon\/RIOT,jferreir\/RIOT,RubikonAlpha\/RIOT,rfuentess\/RIOT,mfrey\/RIOT,abkam07\/RIOT,msolters\/RIOT,syin2\/RIOT,rfswarm\/RIOT,rajma996\/RIOT,MonsterCode8000\/RIOT,kYc0o\/RIOT,wentaoshang\/RIOT,immesys\/RiSyn,miri64\/RIOT,ximus\/RIOT,dkm\/RIOT,beurdouche\/RIOT,koenning\/RIOT,DipSwitch\/RIOT,herrfz\/RIOT,haoyangyu\/RIOT,ThanhVic\/RIOT,ntrtrung\/RIOT,MonsterCode8000\/RIOT,x3ro\/RIOT,jasonatran\/RIOT,thiagohd\/RIOT,cladmi\/RIOT,miri64\/RIOT,ThanhVic\/RIOT,aeneby\/RIOT,ThanhVic\/RIOT,x3ro\/RIOT,l3nko\/RIOT,RIOT-OS\/RIOT,tdautc19841202\/RIOT,bartfaizoltan\/RIOT,sgso\/RIOT,sumanpanchal\/RIOT,herrfz\/RIOT-old,kerneltask\/RIOT,ks156\/RIOT,rfswarm\/RIOT,shady33\/RIOT,binarylemon\/RIOT,kerneltask\/RIOT,kaleb-himes\/RIOT,emmanuelsearch\/RIOT,AnonMall\/RIOT,d00616\/RIOT,sgso\/RIOT,gbarnett\/RIOT,Josar\/RIOT,gebart\/RIOT,herrfz\/RIOT,binarylemon\/RIOT,mziegert\/RIOT,altairpearl\/RIOT,altairpearl\/RIOT,jfischer-phytec-iot\/RIOT,brettswann\/RIOT,abp719\/RIOT,gautric\/RIOT,ximus\/RIOT,neumodisch\/RIOT,OTAkeys\/RIOT,biboc\/RIOT,msolters\/RIOT,alignan\/RIOT,dhruvvyas90\/RIOT,OlegHahm\/RIOT,chris-wood\/RIOT,alignan\/RIOT,BytesGalore\/RIOT,jferreir\/RIOT,alignan\/RIOT,basilfx\/RIOT,EmuxEvans\/RIOT,rfswarm\/RIOT,Josar\/RIOT,josephnoir\/RIOT,emmanuelsearch\/RIOT,MohmadAyman\/RIOT,jhollister\/RIOT,latsku\/RIOT,Hyungsin\/RIOT-OS,jfischer-phytec-iot\/RIOT,patkan\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,ks156\/RIOT,arvindpdmn\/RIOT,wentaoshang\/RIOT,RubikonAlpha\/RIOT,authmillenon\/RIOT,malosek\/RIOT,MohmadAyman\/RIOT,Ell-i\/RIOT,mziegert\/RIOT,msolters\/RIOT,Darredevil\/RIOT,khhhh\/RIOT,TobiasFredersdorf\/RIOT,kushalsingh007\/RIOT,jfischer-phytec-iot\/RIOT,zhuoshuguo\/RIOT,attdona\/RIOT,JensErdmann\/RIOT,thiagohd\/RIOT,gautric\/RIOT,rfswarm2\/RIOT,latsku\/RIOT,LudwigOrtmann\/RIOT,EmuxEvans\/RIOT,gebart\/RIOT,gbarnett\/RIOT,toonst\/RIOT,immesys\/RiSyn,sumanpanchal\/RIOT,herrfz\/RIOT,robixnai\/RIOT,lazytech-org\/RIOT,Josar\/RIOT,malosek\/RIOT,malosek\/RIOT,jbeyerstedt\/RIOT-OTA-update,robixnai\/RIOT,LudwigKnuepfer\/RIOT,automote\/RIOT,yogo1212\/RIOT,ks156\/RIOT,robixnai\/RIOT,daniel-k\/RIOT,lebrush\/RIOT,MarkXYang\/RIOT,wentaoshang\/RIOT,bartfaizoltan\/RIOT,benoit-canet\/RIOT,jbeyerstedt\/RIOT-OTA-update,Osblouf\/RIOT,luciotorre\/RIOT,wentaoshang\/RIOT,hamilton-mote\/RIOT-OS,mtausig\/RIOT,neumodisch\/RIOT,changbiao\/RIOT,arvindpdmn\/RIOT,malosek\/RIOT,lebrush\/RIOT,centurysys\/RIOT,jremmert-phytec-iot\/RIOT,LudwigKnuepfer\/RIOT,MonsterCode8000\/RIOT,kerneltask\/RIOT,syin2\/RIOT,watr-li\/RIOT,LudwigKnuepfer\/RIOT,biboc\/RIOT,JensErdmann\/RIOT,chris-wood\/RIOT,wentaoshang\/RIOT,ximus\/RIOT,kb2ma\/RIOT,abkam07\/RIOT,herrfz\/RIOT-old,tdautc19841202\/RIOT,jhollister\/RIOT,kushalsingh007\/RIOT,nsol-nmsu\/RIOT,zhuoshuguo\/RIOT,ntrtrung\/RIOT,automote\/RIOT,1blankz7\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,ThanhVic\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,thiagohd\/RIOT,AnonMall\/RIOT,gebart\/RIOT,backenklee\/RIOT,binarylemon\/RIOT,rfuentess\/RIOT,authmillenon\/RIOT,phiros\/RIOT,robixnai\/RIOT,daniel-k\/RIOT,katezilla\/RIOT,MohmadAyman\/RIOT,khhhh\/RIOT,LudwigOrtmann\/RIOT,kbumsik\/RIOT,d00616\/RIOT,asanka-code\/RIOT,benoit-canet\/RIOT,herrfz\/RIOT-old,OlegHahm\/RIOT,asanka-code\/RIOT,dhruvvyas90\/RIOT,kaleb-himes\/RIOT,tdautc19841202\/RIOT,kerneltask\/RIOT,arvindpdmn\/RIOT,watr-li\/RIOT,ntrtrung\/RIOT,attdona\/RIOT,LudwigKnuepfer\/RIOT,rfswarm\/RIOT,AnonMall\/RIOT,tfar\/RIOT,A-Paul\/RIOT,jferreir\/RIOT,tfar\/RIOT,khhhh\/RIOT,kaleb-himes\/RIOT,kushalsingh007\/RIOT,asanka-code\/RIOT,watr-li\/RIOT,d00616\/RIOT,emmanuelsearch\/RIOT,syin2\/RIOT,smlng\/RIOT,DipSwitch\/RIOT,Lexandro92\/RIOT-CoAP,jremmert-phytec-iot\/RIOT,rakendrathapa\/RIOT,josephnoir\/RIOT,l3nko\/RIOT,dailab\/RIOT,shady33\/RIOT,gbarnett\/RIOT,adjih\/RIOT,fnack\/RIOT,sgso\/RIOT,miri64\/RIOT,yogo1212\/RIOT,Osblouf\/RIOT,haoyangyu\/RIOT,OTAkeys\/RIOT,sumanpanchal\/RIOT,centurysys\/RIOT,rousselk\/RIOT,sgso\/RIOT,MarkXYang\/RIOT,abp719\/RIOT,rakendrathapa\/RIOT,kbumsik\/RIOT,openkosmosorg\/RIOT,kYc0o\/RIOT,abkam07\/RIOT,abkam07\/RIOT,tdautc19841202\/RIOT,Darredevil\/RIOT,benoit-canet\/RIOT,Lexandro92\/RIOT-CoAP,thomaseichinger\/RIOT,Yonezawa-T2\/RIOT,rfuentess\/RIOT,Ell-i\/RIOT,syin2\/RIOT,RIOT-OS\/RIOT,daniel-k\/RIOT,d00616\/RIOT,arvindpdmn\/RIOT,RubikonAlpha\/RIOT,MarkXYang\/RIOT,kb2ma\/RIOT,marcosalm\/RIOT,ximus\/RIOT,daniel-k\/RIOT,phiros\/RIOT,stevenj\/RIOT,msolters\/RIOT,sumanpanchal\/RIOT,neiljay\/RIOT,openkosmosorg\/RIOT,stevenj\/RIOT,fnack\/RIOT,brettswann\/RIOT,MohmadAyman\/RIOT,A-Paul\/RIOT,thomaseichinger\/RIOT,msolters\/RIOT,PSHIVANI\/Riot-Code,fnack\/RIOT,ant9000\/RIOT,dailab\/RIOT,Lexandro92\/RIOT-CoAP,neiljay\/RIOT,benoit-canet\/RIOT,Osblouf\/RIOT,rakendrathapa\/RIOT,robixnai\/RIOT,automote\/RIOT,changbiao\/RIOT,kaspar030\/RIOT,aeneby\/RIOT,dkm\/RIOT,neumodisch\/RIOT,rakendrathapa\/RIOT,jferreir\/RIOT,nsol-nmsu\/RIOT,PSHIVANI\/Riot-Code,altairpearl\/RIOT,binarylemon\/RIOT,Ell-i\/RIOT,PSHIVANI\/Riot-Code,Hyungsin\/RIOT-OS,watr-li\/RIOT,syin2\/RIOT,PSHIVANI\/Riot-Code,mfrey\/RIOT,basilfx\/RIOT,gbarnett\/RIOT,OTAkeys\/RIOT,immesys\/RiSyn,changbiao\/RIOT,patkan\/RIOT,Lexandro92\/RIOT-CoAP,rfuentess\/RIOT,roberthartung\/RIOT,beurdouche\/RIOT,brettswann\/RIOT,kYc0o\/RIOT,kushalsingh007\/RIOT,automote\/RIOT,latsku\/RIOT,neiljay\/RIOT,RIOT-OS\/RIOT,jferreir\/RIOT,thomaseichinger\/RIOT,khhhh\/RIOT,latsku\/RIOT,daniel-k\/RIOT,kaspar030\/RIOT,malosek\/RIOT,attdona\/RIOT,RBartz\/RIOT,altairpearl\/RIOT,Yonezawa-T2\/RIOT,dailab\/RIOT,latsku\/RIOT,mziegert\/RIOT,phiros\/RIOT,FrancescoErmini\/RIOT,rousselk\/RIOT,ant9000\/RIOT,haoyangyu\/RIOT,1blankz7\/RIOT,FrancescoErmini\/RIOT,fnack\/RIOT,Yonezawa-T2\/RIOT,emmanuelsearch\/RIOT,MarkXYang\/RIOT,lebrush\/RIOT,jremmert-phytec-iot\/RIOT,ntrtrung\/RIOT,mtausig\/RIOT,Darredevil\/RIOT,benoit-canet\/RIOT,TobiasFredersdorf\/RIOT,1blankz7\/RIOT,rakendrathapa\/RIOT,miri64\/RIOT,cladmi\/RIOT,JensErdmann\/RIOT,Ell-i\/RIOT,avmelnikoff\/RIOT,EmuxEvans\/RIOT,mziegert\/RIOT,rousselk\/RIOT,Josar\/RIOT,rfswarm2\/RIOT,josephnoir\/RIOT,robixnai\/RIOT,shady33\/RIOT,LudwigKnuepfer\/RIOT,RBartz\/RIOT,automote\/RIOT,MohmadAyman\/RIOT,rousselk\/RIOT,patkan\/RIOT","old_file":"cpu\/nrf51822\/nrf51822qfaa_linkerscript.ld","new_file":"cpu\/nrf51822\/nrf51822qfaa_linkerscript.ld","new_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x00000000, LENGTH = 256K\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 16K\n}\n\n\/* The stack size used by the application. NOTE: you need to adjust  *\/\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x200 ;\n\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x00000000, LENGTH = 256K\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 16K\n}\n\n\/* The stack size used by the application. NOTE: you need to adjust  *\/\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0xa00 ;\n\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"609a9c6b715b80b3b84ef875408e7e3b642c8c9b","subject":"eagle.rom.addr.v6.ld: More symbols from SDK 1.5.0.","message":"eagle.rom.addr.v6.ld: More symbols from SDK 1.5.0.\n","repos":"praemdonck\/micropython,selste\/micropython,dxxb\/micropython,pozetroninc\/micropython,PappaPeppar\/micropython,misterdanb\/micropython,hiway\/micropython,henriknelson\/micropython,MrSurly\/micropython-esp32,oopy\/micropython,deshipu\/micropython,tobbad\/micropython,oopy\/micropython,dmazzella\/micropython,mhoffma\/micropython,hiway\/micropython,PappaPeppar\/micropython,pozetroninc\/micropython,MrSurly\/micropython,tobbad\/micropython,TDAbboud\/micropython,micropython\/micropython-esp32,adafruit\/micropython,mhoffma\/micropython,lowRISC\/micropython,deshipu\/micropython,toolmacher\/micropython,misterdanb\/micropython,emfcamp\/micropython,danicampora\/micropython,TDAbboud\/micropython,ryannathans\/micropython,blazewicz\/micropython,HenrikSolver\/micropython,adafruit\/circuitpython,MrSurly\/micropython,mpalomer\/micropython,pramasoul\/micropython,jmarcelino\/pycom-micropython,misterdanb\/micropython,ganshun666\/micropython,alex-march\/micropython,alex-march\/micropython,chrisdearman\/micropython,tuc-osg\/micropython,pozetroninc\/micropython,tralamazza\/micropython,galenhz\/micropython,swegener\/micropython,lowRISC\/micropython,ganshun666\/micropython,pozetroninc\/micropython,kerneltask\/micropython,mpalomer\/micropython,Timmenem\/micropython,hosaka\/micropython,redbear\/micropython,infinnovation\/micropython,toolmacher\/micropython,dinau\/micropython,alex-robbins\/micropython,deshipu\/micropython,MrSurly\/micropython-esp32,danicampora\/micropython,alex-robbins\/micropython,alex-robbins\/micropython,AriZuu\/micropython,blazewicz\/micropython,toolmacher\/micropython,TDAbboud\/micropython,chrisdearman\/micropython,selste\/micropython,torwag\/micropython,lowRISC\/micropython,pramasoul\/micropython,toolmacher\/micropython,tuc-osg\/micropython,drrk\/micropython,dinau\/micropython,AriZuu\/micropython,mhoffma\/micropython,torwag\/micropython,Timmenem\/micropython,dxxb\/micropython,deshipu\/micropython,matthewelse\/micropython,dinau\/micropython,pfalcon\/micropython,swegener\/micropython,matthewelse\/micropython,matthewelse\/micropython,kerneltask\/micropython,praemdonck\/micropython,mhoffma\/micropython,dmazzella\/micropython,hiway\/micropython,MrSurly\/micropython,bvernoux\/micropython,oopy\/micropython,ryannathans\/micropython,bvernoux\/micropython,micropython\/micropython-esp32,bvernoux\/micropython,infinnovation\/micropython,ganshun666\/micropython,jmarcelino\/pycom-micropython,adafruit\/circuitpython,AriZuu\/micropython,ryannathans\/micropython,adafruit\/micropython,puuu\/micropython,selste\/micropython,lowRISC\/micropython,jmarcelino\/pycom-micropython,infinnovation\/micropython,pramasoul\/micropython,kerneltask\/micropython,mpalomer\/micropython,drrk\/micropython,hiway\/micropython,turbinenreiter\/micropython,toolmacher\/micropython,hosaka\/micropython,redbear\/micropython,SHA2017-badge\/micropython-esp32,alex-robbins\/micropython,deshipu\/micropython,pfalcon\/micropython,cwyark\/micropython,matthewelse\/micropython,hosaka\/micropython,pozetroninc\/micropython,chrisdearman\/micropython,puuu\/micropython,adafruit\/micropython,torwag\/micropython,TDAbboud\/micropython,galenhz\/micropython,drrk\/micropython,jmarcelino\/pycom-micropython,matthewelse\/micropython,dmazzella\/micropython,AriZuu\/micropython,adafruit\/circuitpython,alex-robbins\/micropython,alex-march\/micropython,torwag\/micropython,HenrikSolver\/micropython,AriZuu\/micropython,micropython\/micropython-esp32,oopy\/micropython,alex-march\/micropython,adafruit\/micropython,Peetz0r\/micropython-esp32,SHA2017-badge\/micropython-esp32,pramasoul\/micropython,SHA2017-badge\/micropython-esp32,ryannathans\/micropython,henriknelson\/micropython,swegener\/micropython,Timmenem\/micropython,Peetz0r\/micropython-esp32,PappaPeppar\/micropython,blazewicz\/micropython,infinnovation\/micropython,henriknelson\/micropython,pfalcon\/micropython,misterdanb\/micropython,lowRISC\/micropython,cwyark\/micropython,HenrikSolver\/micropython,chrisdearman\/micropython,danicampora\/micropython,matthewelse\/micropython,tobbad\/micropython,trezor\/micropython,micropython\/micropython-esp32,HenrikSolver\/micropython,drrk\/micropython,danicampora\/micropython,MrSurly\/micropython-esp32,henriknelson\/micropython,praemdonck\/micropython,cwyark\/micropython,turbinenreiter\/micropython,hiway\/micropython,SHA2017-badge\/micropython-esp32,puuu\/micropython,adafruit\/micropython,TDAbboud\/micropython,selste\/micropython,swegener\/micropython,trezor\/micropython,henriknelson\/micropython,cwyark\/micropython,tuc-osg\/micropython,kerneltask\/micropython,danicampora\/micropython,dxxb\/micropython,ganshun666\/micropython,bvernoux\/micropython,praemdonck\/micropython,mhoffma\/micropython,trezor\/micropython,dinau\/micropython,Peetz0r\/micropython-esp32,adafruit\/circuitpython,mpalomer\/micropython,dinau\/micropython,bvernoux\/micropython,selste\/micropython,torwag\/micropython,blazewicz\/micropython,turbinenreiter\/micropython,swegener\/micropython,PappaPeppar\/micropython,tralamazza\/micropython,mpalomer\/micropython,PappaPeppar\/micropython,tralamazza\/micropython,tralamazza\/micropython,turbinenreiter\/micropython,puuu\/micropython,adafruit\/circuitpython,MrSurly\/micropython,turbinenreiter\/micropython,emfcamp\/micropython,ganshun666\/micropython,adafruit\/circuitpython,dxxb\/micropython,Peetz0r\/micropython-esp32,dmazzella\/micropython,emfcamp\/micropython,puuu\/micropython,pfalcon\/micropython,emfcamp\/micropython,kerneltask\/micropython,galenhz\/micropython,emfcamp\/micropython,alex-march\/micropython,chrisdearman\/micropython,praemdonck\/micropython,galenhz\/micropython,misterdanb\/micropython,hosaka\/micropython,Peetz0r\/micropython-esp32,dxxb\/micropython,Timmenem\/micropython,galenhz\/micropython,tobbad\/micropython,blazewicz\/micropython,oopy\/micropython,redbear\/micropython,MrSurly\/micropython-esp32,redbear\/micropython,tobbad\/micropython,Timmenem\/micropython,pfalcon\/micropython,ryannathans\/micropython,redbear\/micropython,drrk\/micropython,hosaka\/micropython,micropython\/micropython-esp32,trezor\/micropython,pramasoul\/micropython,tuc-osg\/micropython,MrSurly\/micropython,MrSurly\/micropython-esp32,tuc-osg\/micropython,jmarcelino\/pycom-micropython,HenrikSolver\/micropython,infinnovation\/micropython,SHA2017-badge\/micropython-esp32,trezor\/micropython,cwyark\/micropython","old_file":"esp8266\/eagle.rom.addr.v6.ld","new_file":"esp8266\/eagle.rom.addr.v6.ld","new_contents":"PROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( ets_run = 0x40000e04 );\nPROVIDE ( ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n","old_contents":"PROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( ets_run = 0x40000e04 );\nPROVIDE ( ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"fec01bc92df2956110bee7eac4fc4bb31463dee8","subject":"more linker script magic","message":"more linker script magic\n","repos":"matildah\/octocabbit","old_file":"src\/kernel.lds","new_file":"src\/kernel.lds","new_contents":"KERNEL_BASE   = 0xf0000000; \/* virtual address *\/\nPHYS_BASE     = 0x80000000; \/* physical address *\/\nKERNEL_OFFSET = KERNEL_BASE - PHYS_BASE;\n\nENTRY(asm_entry)\nSECTIONS\n{\n    . = PHYS_BASE;\n\n    .boot . :\n    {\n        *(.boot.text)\n        *(.boot.rodata)\n        *(.boot.data)\n        . = ALIGN(64K);\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        . = ALIGN(64K);\n        *(.vectors)\n        *(.vectors.text)\n        *(.text)\n    }\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n        . = ALIGN(8);\n        . = . + 0x1000;\n        svc_stack = .;\n        . = . + 0x1000;\n        usr_stack = .;\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n        *(.ARM.attributes)\n    }\n\n}\n","old_contents":"KERNEL_BASE   = 0xf0000000; \/* virtual address *\/\nPHYS_BASE     = 0x80000000; \/* physical address *\/\nKERNEL_OFFSET = KERNEL_BASE - PHYS_BASE;\n\nENTRY(asm_entry)\nSECTIONS\n{\n    . = KERNEL_BASE;\n\n    .startup : { obj\/startup.o(.text) }\n    .text : { *(.text) }\n    .data : { *(.data) }\n    .bss : { *(.bss COMMON) }\n    . = ALIGN(8);\n    . = . + 0x1000; \/* 4 kB for supervisor stack *\/\n    svc_stack = .;\n    . = . + 0x1000; \/* 4 kB for user stack *\/\n    usr_stack = .;\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"d455f120cdbcd2ca4a546df1cbadd2b4bc2bf5e0","subject":"Fix vectors section alignment (#1669)","message":"Fix vectors section alignment (#1669)\n\n***NO_CI***","repos":"nanoframework\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter,nanoframework\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter,Eclo\/nf-interpreter,Eclo\/nf-interpreter","old_file":"targets\/CMSIS-OS\/ChibiOS\/common\/rules_code.ld","new_file":"targets\/CMSIS-OS\/ChibiOS\/common\/rules_code.ld","new_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio.  All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n__nanoImage_start__     = ORIGIN(flash);\n__nanoImage_size__      = LENGTH(flash);\n__nanoImage_end__       = __nanoImage_start__ + __nanoImage_size__;\n__nanoConfig_start__    = ORIGIN(config);\n__nanoConfig_size__     = LENGTH(config);\n__nanoConfig_end__      = __nanoConfig_start__ + __nanoConfig_size__;\n__deployment_start__    = ORIGIN(deployment);\n__deployment_size__     = LENGTH(deployment);\n__deployment_end__      = __deployment_start__ + __deployment_size__;\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .vectors : ALIGN(1024)\n    {\n        KEEP(*(.vectors))\n    } > VECTORS_FLASH AT > VECTORS_FLASH_LMA\n\n    .xtors : ALIGN(4)\n    {\n        __init_array_start = .;\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        __init_array_end = .;\n        __fini_array_start = .;\n        KEEP(*(.fini_array))\n        KEEP(*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n    } > XTORS_FLASH AT > XTORS_FLASH_LMA\n\n    .text : ALIGN(16)\n    {\n        *(.text)\n        *(.text.*)\n        *(.glue_7t)\n        *(.glue_7)\n        *(.gcc*)\n    } > TEXT_FLASH AT > TEXT_FLASH_LMA\n\n    .rodata : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __rodata_base__ = .;\n        *(.rodata)\n        *(.rodata.*)\n        . = ALIGN(4);\n        __rodata_end__ = .;\n    } > RODATA_FLASH AT > RODATA_FLASH_LMA\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n     } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA\n\n    .eh_frame_hdr :\n    {\n        *(.eh_frame_hdr)\n    } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA\n\n    .eh_frame : ONLY_IF_RO\n    {\n        *(.eh_frame)\n    } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA\n}\n","old_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio.  All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n__nanoImage_start__     = ORIGIN(flash);\n__nanoImage_size__      = LENGTH(flash);\n__nanoImage_end__       = __nanoImage_start__ + __nanoImage_size__;\n__nanoConfig_start__    = ORIGIN(config);\n__nanoConfig_size__     = LENGTH(config);\n__nanoConfig_end__      = __nanoConfig_start__ + __nanoConfig_size__;\n__deployment_start__    = ORIGIN(deployment);\n__deployment_size__     = LENGTH(deployment);\n__deployment_end__      = __deployment_start__ + __deployment_size__;\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .vectors : ALIGN(16)\n    {\n        KEEP(*(.vectors))\n    } > VECTORS_FLASH AT > VECTORS_FLASH_LMA\n\n    .xtors : ALIGN(4)\n    {\n        __init_array_start = .;\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        __init_array_end = .;\n        __fini_array_start = .;\n        KEEP(*(.fini_array))\n        KEEP(*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n    } > XTORS_FLASH AT > XTORS_FLASH_LMA\n\n    .text : ALIGN(16)\n    {\n        *(.text)\n        *(.text.*)\n        *(.glue_7t)\n        *(.glue_7)\n        *(.gcc*)\n    } > TEXT_FLASH AT > TEXT_FLASH_LMA\n\n    .rodata : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __rodata_base__ = .;\n        *(.rodata)\n        *(.rodata.*)\n        . = ALIGN(4);\n        __rodata_end__ = .;\n    } > RODATA_FLASH AT > RODATA_FLASH_LMA\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n     } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA\n\n    .eh_frame_hdr :\n    {\n        *(.eh_frame_hdr)\n    } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA\n\n    .eh_frame : ONLY_IF_RO\n    {\n        *(.eh_frame)\n    } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f1db12a816439704aa3d2ff23ecee65d5d11503c","subject":"Add space in linker script","message":"Add space in linker script\n","repos":"olsner\/verdigris,olsner\/verdigris,olsner\/verdigris","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(start32_mboot)\nOUTPUT_FORMAT(binary)\n\nhigh_org = 0xffffffffc0000000;\n\nMEMORY {\n    ram : org = 0x100000, l = 16K\n    high : org = 0xffffffffc0100000, l = 16K\n}\n\nSECTIONS {\n    . = 0x100000;\n\n    .text32 : {\n        start32.o(.text*);\n    } >ram AT>ram\n\n    .text64 (. + high_org) : {\n        *(.text*);\n    } >high AT>ram\n\n    .data32 (. - high_org) : {\n        start32.o(.data*);\n        start32.o(.rodata*);\n    } >ram AT>ram\n\n    .data64 (. + high_org) : {\n        *(.rodata*);\n        *(.data*);\n        PROVIDE(section.data.end = . - 0xffffffffc0000000);\n    } >high AT>ram\n\n    .bss32 (. - high_org) : {\n        start32.o(.bss*);\n    } >ram AT>ram\n\n    .bss64 (. + high_org) : {\n        *(.bss*);\n    } >high AT>ram\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.eh_frame)\n        *(.rel.eh_frame)\n    }\n}\n","old_contents":"ENTRY(start32_mboot)\nOUTPUT_FORMAT(binary)\n\nhigh_org = 0xffffffffc0000000;\n\nMEMORY {\n    ram : org = 0x100000, l = 12K\n    high : org = 0xffffffffc0100000, l = 12K\n}\n\nSECTIONS {\n    . = 0x100000;\n\n    .text32 : {\n        start32.o(.text*);\n    } >ram AT>ram\n\n    .text64 (. + high_org) : {\n        *(.text*);\n    } >high AT>ram\n\n    .data32 (. - high_org) : {\n        start32.o(.data*);\n        start32.o(.rodata*);\n    } >ram AT>ram\n\n    .data64 (. + high_org) : {\n        *(.rodata*);\n        *(.data*);\n        PROVIDE(section.data.end = . - 0xffffffffc0000000);\n    } >high AT>ram\n\n    .bss32 (. - high_org) : {\n        start32.o(.bss*);\n    } >ram AT>ram\n\n    .bss64 (. + high_org) : {\n        *(.bss*);\n    } >high AT>ram\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.eh_frame)\n        *(.rel.eh_frame)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"88af0f5881e49e0804d0f6f4d4a9a4f10c26f6c6","subject":"Fix linker script","message":"Fix linker script\n","repos":"Mrokkk\/objective-kernel,Mrokkk\/objective-kernel","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(_start)\n\n__kernel_phys = 0x00100000;\n__kernel_virt = 0xC0100000;\n\n__kernel_offset = __kernel_virt - __kernel_phys;\n\nSECTIONS {\n\n    . = __kernel_phys;\n\n    .unpagged BLOCK(4K) : ALIGN(4K) {\n        __unpagged_start = .;\n        KEEP(*(.multiboot))\n        KEEP(*(.boot))\n        *multiboot[1-2].cpp.o(.rodata)\n        __unpagged_end = .;\n    }\n\n    . += __kernel_offset;\n\n    . = ALIGN(4K);\n    .text BLOCK(4K) : AT(ADDR(.text) - __kernel_offset) {\n        __text_start = .;\n        *(.text*)\n        *(.gnu.linkonce.*)\n        __text_end = .;\n    }\n\n    . = ALIGN(4K);\n    .rodata BLOCK(4K) : AT(ADDR(.rodata) - __kernel_offset) {\n        KEEP (*(.rodata*))\n    }\n\n    . = ALIGN(4);\n    .preinit_array : AT(ADDR(.preinit_array) - __kernel_offset) {\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP (*(.preinit_array*))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n    }\n\n    . = ALIGN(4);\n    .init_array : AT(ADDR(.init_array) - __kernel_offset) {\n        __init_array_start = .;\n        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array*) SORT_BY_INIT_PRIORITY(.ctors*)))\n        __init_array_end = .;\n    }\n\n    . = ALIGN(4K);\n    .data BLOCK(4K) : AT(ADDR(.data) - __kernel_offset) {\n        __data_start = .;\n        KEEP (*(.data))\n        KEEP (*(.data.*))\n        __data_end = .;\n    }\n\n    . = ALIGN(4K);\n    .bss BLOCK(4K) : AT(ADDR(.bss) - __kernel_offset) {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss*)\n        __bss_end = .;\n    }\n\n    . = ALIGN(4K);\n\n    __heap_start = .;\n\n    \/DISCARD\/ : {\n        *(.dynamic)\n        *(.gnu.hash)\n        *(.dynstr)\n        *(.dynsym)\n        *(.eh_frame)\n        *(.note)\n        *(.comment)\n    }\n}\n\n","old_contents":"ENTRY(_start)\n\n__kernel_phys = 0x00100000;\n__kernel_virt = 0xC0100000;\n\n__kernel_offset = __kernel_virt - __kernel_phys;\n\nSECTIONS {\n\n    . = __kernel_phys;\n\n    .unpagged BLOCK(4K) : ALIGN(4K) {\n        __unpagged_start = .;\n        KEEP(*(.multiboot))\n        KEEP(*(.boot))\n        *multiboot[1-2].cpp.o(.rodata)\n        __unpagged_end = .;\n    }\n\n    . += __kernel_offset;\n\n    . = ALIGN(4K);\n    .text BLOCK(4K) : AT(ADDR(.text) - __kernel_offset) {\n        __text_start = .;\n        *(.text*)\n        *(.gnu.linkonce.*)\n        __text_end = .;\n    }\n\n    . = ALIGN(4K);\n    .rodata BLOCK(4K) : AT(ADDR(.rodata) - __kernel_offset) {\n        KEEP (*(.rodata*))\n    }\n\n    . = ALIGN(4);\n    .preinit_array : AT(ADDR(.preinit_array) - __kernel_offset) {\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP (*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n    }\n\n    . = ALIGN(4);\n    .init_array : AT(ADDR(.init_array) - __kernel_offset) {\n        __init_array_start = .;\n        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n        KEEP (*(.init_array .ctors))\n        __init_array_end = .;\n    }\n\n    . = ALIGN(4K);\n    .data BLOCK(4K) : AT(ADDR(.data) - __kernel_offset) {\n        __data_start = .;\n        KEEP (*(.data))\n        KEEP (*(.data.*))\n        __data_end = .;\n    }\n\n    . = ALIGN(4K);\n    .bss BLOCK(4K) : AT(ADDR(.bss) - __kernel_offset) {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss*)\n        __bss_end = .;\n    }\n\n    . = ALIGN(4K);\n\n    __heap_start = .;\n\n    \/DISCARD\/ : {\n        *(.dynamic)\n        *(.gnu.hash)\n        *(.dynstr)\n        *(.dynsym)\n        *(.eh_frame)\n        *(.note)\n        *(.comment)\n    }\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f3c1acaeea5b26853dc6af005304d3cd1651986a","subject":"riscv: linker: move snippets-ram-sections.ld to ram start","message":"riscv: linker: move snippets-ram-sections.ld to ram start\n\nThis align the RISC-V linker script with ARM linker script.\n(The snippets-ram-sections.ld is included first inside the\nRAMABLE_REGION)\n\nSigned-off-by: Dino Li <338d523ecf3700bd86eb9c34d220f91911d2a18c@ite.com.tw>\n","repos":"galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE);\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_BASE;\n\t_image_ram_start = .;\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE);\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n#if !defined(CONFIG_USERSPACE)\n\t\t _image_ram_start = .;\n#endif \/* CONFIG_USERSPACE *\/\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"456c12e5abaeb99d9ca0ad156611399713535561","subject":"App memory needs to be 8K aligned","message":"App memory needs to be 8K aligned\n","repos":"google\/tock-on-titan,google\/tock-on-titan,google\/tock-on-titan","old_file":"src\/chips\/sam4l\/loader.ld","new_file":"src\/chips\/sam4l\/loader.ld","new_contents":"\/*\n * This file is part of StormLoader, the Storm Bootloader\n *\n * StormLoader is free software: you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation, either version 3 of the License, or\n * (at your option) any later version.\n *\n * StormLoader is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with Foobar.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n *  \n * Copyright 2014, Michael Andersen <m.andersen@eecs.berkeley.edu>\n *\n * This file is largely copied from the Atmel supplied linker scripts\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.) \n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nMEMORY\n{\n  rom (rx)  : ORIGIN = 0x00010000, LENGTH = 0x00020000\n  prog (rx) : ORIGIN = 0x00030000, LENGTH = 0x00040000\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _textstart = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        KEEP (*(.syscalls))\n\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    .apps :\n    {\n        . = ALIGN(4);\n        _sapps = .;\n        KEEP (*(.app.*))\n        _eapps = .;\n    } > prog\n\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n    _textend = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n\n        . = ALIGN(8K);\n        *(.app_memory)\n\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","old_contents":"\/*\n * This file is part of StormLoader, the Storm Bootloader\n *\n * StormLoader is free software: you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation, either version 3 of the License, or\n * (at your option) any later version.\n *\n * StormLoader is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with Foobar.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n *  \n * Copyright 2014, Michael Andersen <m.andersen@eecs.berkeley.edu>\n *\n * This file is largely copied from the Atmel supplied linker scripts\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.) \n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nMEMORY\n{\n  rom (rx)  : ORIGIN = 0x00010000, LENGTH = 0x00020000\n  prog (rx) : ORIGIN = 0x00030000, LENGTH = 0x00040000\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _textstart = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        KEEP (*(.syscalls))\n\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    .apps :\n    {\n        . = ALIGN(4);\n        _sapps = .;\n        KEEP (*(.app.*))\n        _eapps = .;\n    } > prog\n\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n    _textend = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n\n        . = ALIGN(8);\n        *(.app_memory)\n\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5d77db61cbda695af4f19e680940423be49e1074","subject":"Workaround missing symbol","message":"Workaround missing symbol\n","repos":"richo\/zinc,richo\/zinc,richo\/zinc,richo\/zinc,richo\/zinc","old_file":"src\/hal\/lpc43xx\/layout.ld","new_file":"src\/hal\/lpc43xx\/layout.ld","new_contents":"__STACK_BASE  = 0x10002000;\n\nINCLUDE iomem.ld\n\n\/* isr_reserved_1 = 0 - (__STACK_BASE + main + 1 + isr_nmi + 1 + isr_hardfault + 1); *\/\nisr_reserved_1 = 0 - (__STACK_BASE + main + 1 );\n\n_data_load = LOADADDR(.data);\n\nENTRY(main)\n\nMEMORY\n{\n    rom(RX)   : ORIGIN = 0x00000000, LENGTH = 64K\n    ram(WAIL) : ORIGIN = 0x10000000, LENGTH = 0x2000\n}\n\nREGION_ALIAS(\"vectors\", rom);\n\nINCLUDE layout_common.ld\n","old_contents":"__STACK_BASE  = 0x10002000;\n\nINCLUDE iomem.ld\n\nisr_reserved_1 = 0 - (__STACK_BASE + main + 1 + isr_nmi + 1 + isr_hardfault + 1);\n\n_data_load = LOADADDR(.data);\n\nENTRY(main)\n\nMEMORY\n{\n    rom(RX)   : ORIGIN = 0x00000000, LENGTH = 64K\n    ram(WAIL) : ORIGIN = 0x10000000, LENGTH = 0x2000\n}\n\nREGION_ALIAS(\"vectors\", rom);\n\nINCLUDE layout_common.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"73e8afc5b9fa90f9dc63d0d056abbb3fadd6a420","subject":"soc: place constant data from rtc_clk.c into DRAM","message":"soc: place constant data from rtc_clk.c into DRAM\n\nIn release mode, switches in rtc_clk_bbpll_set would be converted to\njump tables. These tables would be placed into .rodata, which caused\nrtc_clk_cpu_freq_set to be unusable while cache is disabled. This\nmanifested itself in crashes when exiting from light sleep:\n\nhttps:\/\/esp32.com\/posting.php?mode=reply&f=13&t=3089#pr14590\n","repos":"www220\/esp-idf,nineisk\/esp-idf,nineisk\/esp-idf,www220\/esp-idf,empoweredhomes\/esp-idf,MIhanguangyi\/esp-idf,mashaoze\/esp-idf,empoweredhomes\/esp-idf,empoweredhomes\/esp-idf,armada-ai\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf,nineisk\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,shukyisme\/esp-idf-kwik,MIhanguangyi\/esp-idf,MIhanguangyi\/esp-idf,MIhanguangyi\/esp-idf,Hermiedapwdrman\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,armada-ai\/esp-idf,ajs124\/esp-idf,MIhanguangyi\/esp-idf,armada-ai\/esp-idf,ajs124\/esp-idf,shukyisme\/esp-idf-kwik,espressif\/esp-idf,espressif\/esp-idf,www220\/esp-idf,ajs124\/esp-idf,shukyisme\/esp-idf-kwik,shukyisme\/esp-idf-kwik,Hermiedapwdrman\/esp-idf,ajs124\/esp-idf,Hermiedapwdrman\/esp-idf,Hermiedapwdrman\/esp-idf,empoweredhomes\/esp-idf,Hermiedapwdrman\/esp-idf,empoweredhomes\/esp-idf,nineisk\/esp-idf,www220\/esp-idf,shukyisme\/esp-idf-kwik,espressif\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap.o(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap_poisoning.o(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libapp_trace.a:(.literal .text .literal.* .text.*)\n    *libxtensa-debug-module.a:eri.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap.o(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap_poisoning.o(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libapp_trace.a:(.literal .text .literal.* .text.*)\n    *libxtensa-debug-module.a:eri.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a3db13b0a251c2143ac7b12f75ff32adbed319c1","subject":"Update link.lds","message":"Update link.lds","repos":"nongxiaoming\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread","old_file":"bsp\/bluetrum\/ab32vg1-ab-prougen\/link.lds","new_file":"bsp\/bluetrum\/ab32vg1-ab-prougen\/link.lds","new_contents":"\/* Define the flash max size *\/\n__max_flash_size = 1024k;\n\n__data_ram_size = 8k;\n__stack_ram_size = 4k;\n__comm_ram_size = 42k;\n__heap_ram_size = 70k;\n\n__base = 0x10000000;\n\n__data_vma = 0x11000;\n__stack_vma = __data_vma + __data_ram_size;\n__comm_vma = __stack_vma + __stack_ram_size;\n__heap_vma = __comm_vma + __comm_ram_size;\n\n__ram1_vma = 0x50000;\n\nMEMORY\n{\n    init            : org = __base,             len = 512\n    flash(rx)       : org = __base + 512,       len = __max_flash_size\n    comm(rx)        : org = __comm_vma,         len = __comm_ram_size\n\n    data            : org = __data_vma,         len = __data_ram_size\n    stack           : org = __stack_vma,        len = __stack_ram_size\n    heap            : org = __heap_vma,         len = __heap_ram_size\n    ram1(rx)        : org = __ram1_vma,         len = 0x7a00\n}\n\nSECTIONS\n{\n    .init : {\n        *(.reset)\n    } > init\n\n    .ram1 __ram1_vma : {\n        \/* section information for initial *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array*))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n        *save-restore.o (.text* .rodata*)\n        *libcpu*cpu*context_gcc.o (.text* .rodata*)\n        *libcpu*cpu*interrupt.o (.text* .rodata*)\n        *libcpu**.o (.rodata*)\n\n        *components*drivers*misc*pin.o(.text*)\n        *components*drivers*misc*adc.o(.text*)\n\n        . = ALIGN(4);\n        *src*ipc.o (.text* .rodata*)\n        *src*irq.o (.text* .rodata*)\n        *src*object.o (.text* .rodata*)\n        *src*thread.o (.text* .rodata*)\n        *src*timer.o (.text* .rodata*)\n        *src*mempool.o (.text* .rodata*)\n        *src*scheduler.o (.text* .rodata*)\n        *src*clock.o (.text* .rodata*)\n        *src*kservice.o (.text* .rodata*)\n        *src*device.o (.text* .rodata*)\n        *src*idle.o (.text* .rodata*)\n        *src*components.o (.text* .rodata*)\n    } > ram1 AT > flash\n\n    .comm __comm_vma : {\n        . = ALIGN(4);\n        KEEP(*(.vector))\n        *(.irq.cache)\n        *(.irq*)\n        *ab32vg1_hal**.o (.text* .rodata*)\n        *drv_gpio.o (.text* .rodata*)\n        *drv_usart.o (.rodata*)\n        EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata*)\n        *(.rela*)\n        *(.data*)\n        *(.sdata*)\n        *(.com_text*)\n    } > comm AT > flash\n\n    .bss (NOLOAD):\n    {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.sbss)\n        *(.buf*)\n        __bss_end = .;\n    } > data\n    __bss_size = __bss_end - __bss_start;\n\n    .stack (NOLOAD) : {\n        __irq_stack_start = .;\n        . = __stack_ram_size;\n        __irq_stack = .;\n    } > stack\n    __irq_stack_size = __irq_stack - __irq_stack_start;\n\n    .heap (NOLOAD) : {\n        __heap_start = .;\n        . = __heap_ram_size;\n        __heap_end = .;\n    } > heap\n\n    .flash : {\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(4);\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*)\n        . = ALIGN(512);\n    } > flash\n}\n\n\/* Calc the lma *\/\n__bank_size = SIZEOF(.flash);\n__comm_lma = LOADADDR(.comm);\n__comm_size = SIZEOF(.comm);\n__ram1_lma = LOADADDR(.ram1);\n__ram1_size = SIZEOF(.ram1);\n","old_contents":"\/* Define the flash max size *\/\n__max_flash_size = 1024k;\n\n__data_ram_size = 8k;\n__stack_ram_size = 4k;\n__comm_ram_size = 42k;\n__heap_ram_size = 70k;\n\n__base = 0x10000000;\n\n__data_vma = 0x11000;\n__stack_vma = __data_vma + __data_ram_size;\n__comm_vma = __stack_vma + __stack_ram_size;\n__heap_vma = __comm_vma + __comm_ram_size;\n\n__ram1_vma = 0x50000;\n\nMEMORY\n{\n    init            : org = __base,             len = 512\n    flash(rx)       : org = __base + 512,       len = __max_flash_size\n    comm(rx)        : org = __comm_vma,         len = __comm_ram_size\n\n    data            : org = __data_vma,         len = __data_ram_size\n    stack           : org = __stack_vma,        len = __stack_ram_size\n    heap            : org = __heap_vma,         len = __heap_ram_size\n    ram1(rx)        : org = __ram1_vma,         len = 0x7a00\n}\n\nSECTIONS\n{\n    .init : {\n        *(.reset)\n    } > init\n\n    .ram1 __ram1_vma : {\n        . = ALIGN(4);\n        \/* section information for initial *\/\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array*))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n        *save-restore.o (.text* .rodata*)\n        *libcpu*cpu*context_gcc.o (.text* .rodata*)\n        *libcpu*cpu*interrupt.o (.text* .rodata*)\n        *libcpu**.o (.rodata*)\n\n        *components*drivers*misc*pin.o(.text*)\n        *components*drivers*misc*adc.o(.text*)\n\n        . = ALIGN(4);\n        *src*ipc.o (.text* .rodata*)\n        *src*irq.o (.text* .rodata*)\n        *src*object.o (.text* .rodata*)\n        *src*thread.o (.text* .rodata*)\n        *src*timer.o (.text* .rodata*)\n        *src*mempool.o (.text* .rodata*)\n        *src*scheduler.o (.text* .rodata*)\n        *src*clock.o (.text* .rodata*)\n        *src*kservice.o (.text* .rodata*)\n        *src*device.o (.text* .rodata*)\n        *src*idle.o (.text* .rodata*)\n        *src*components.o (.text* .rodata*)\n    } > ram1 AT > flash\n\n    .comm __comm_vma : {\n        . = ALIGN(4);\n        KEEP(*(.vector))\n        *(.irq.cache)\n        *(.irq*)\n        \/* *components*src**.o (.text* .rodata*) *\/\n        *ab32vg1_hal**.o (.text* .rodata*)\n        *drv_gpio.o (.text* .rodata*)\n        *drv_usart.o (.rodata*)\n        EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata*)\n        *(.rela*)\n        *(.data*)\n        *(.sdata*)\n        *(.com_text*)\n    } > comm AT > flash\n\n    .bss (NOLOAD):\n    {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.sbss)\n        *(.buf*)\n        __bss_end = .;\n    } > data\n    __bss_size = __bss_end - __bss_start;\n\n    .stack (NOLOAD) : {\n        __irq_stack_start = .;\n        . = __stack_ram_size;\n        __irq_stack = .;\n    } > stack\n    __irq_stack_size = __irq_stack - __irq_stack_start;\n\n    .heap (NOLOAD) : {\n        __heap_start = .;\n        . = __heap_ram_size;\n        __heap_end = .;\n    } > heap\n\n    .flash : {\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(4);\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*)\n        . = ALIGN(512);\n    } > flash\n}\n\n\/* Calc the lma *\/\n__bank_size = SIZEOF(.flash);\n__comm_lma = LOADADDR(.comm);\n__comm_size = SIZEOF(.comm);\n__ram1_lma = LOADADDR(.ram1);\n__ram1_size = SIZEOF(.ram1);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c50119e3e9cf89ee3e139bef1c5b0a0dc12b28f7","subject":"Mark heap start and end in the orex file","message":"Mark heap start and end in the orex file","repos":"ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme","old_file":"orex.ld","new_file":"orex.ld","new_contents":"ENTRY (main)\n\nMEMORY\n{\n  ram : ORIGIN = 0x00000000, LENGTH = 32M\n  rom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n  .heap 0x1000 : \/* Space to futz with *\/\n  {\n    _HeapStart = . ;\n    . = . + 25165824; \/* allocate 24 MB for dynamic memory use *\/\n    _HeapEnd = . ;\n  } >ram\n\n  .data : \/* Initialized data. *\/\n  {\n    _DataStart = . ;\n    *(.data)\n    *(.data.rel.local)\n    _DataEnd = . ;\n  } >ram\n\n  .bss : \/* Uninitialized data. *\/\n  {\n    _BssStart = . ;\n    *(.bss)\n    *(.sbss)\n    _BssEnd = . ;\n  } >ram\n\n  .text : \/* The actual instructions. *\/\n  {\n    *(.text)\n    *(.got)\n    *(.got.plt)\n    *(.rodata)\n    *(.rodata.str1.4)\n    *(.glue_7)\n    *(.glue_7t)\n  } >ram\n}\n","old_contents":"ENTRY (main)\n\nMEMORY\n{\n  ram : ORIGIN = 0x00000000, LENGTH = 32M\n  rom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n  .heap 0x1000 : \/* Space to futz with *\/\n  {\n    . = . + 25165824; \/* allocate 24 MB for dynamic memory use *\/\n  } >ram\n\n  .data : \/* Initialized data. *\/\n  {\n    _DataStart = . ;\n    *(.data)\n    *(.data.rel.local)\n    _DataEnd = . ;\n  } >ram\n\n  .bss : \/* Uninitialized data. *\/\n  {\n    _BssStart = . ;\n    *(.bss)\n    *(.sbss)\n    _BssEnd = . ;\n  } >ram\n\n  .text : \/* The actual instructions. *\/\n  {\n    *(.text)\n    *(.got)\n    *(.got.plt)\n    *(.rodata)\n    *(.rodata.str1.4)\n    *(.glue_7)\n    *(.glue_7t)\n  } >ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c145211d1f9e2ef19e7b4c2b943f68366daa97af","subject":"ARM: arch\/arm\/boot\/bootp\/bootp.lds: Checkpatch cleanup","message":"ARM: arch\/arm\/boot\/bootp\/bootp.lds: Checkpatch cleanup\n\narch\/arm\/boot\/bootp\/bootp.lds:22: ERROR: trailing whitespace\n\nSigned-off-by: Andrea Gelmini <d595b0cb020d8d8634fc74c12e8a61b33dd25dca@gelma.net>\nSigned-off-by: Russell King <f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk>\n","repos":"TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas","old_file":"arch\/arm\/boot\/bootp\/bootp.lds","new_file":"arch\/arm\/boot\/bootp\/bootp.lds","new_contents":"\/*\n *  linux\/arch\/arm\/boot\/bootp\/bootp.lds\n *\n *  Copyright (C) 2000-2002 Russell King\n *\n * This program is free software; you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n *\/\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS\n{\n  . = 0;\n  .text : {\n   _stext = .;\n   *(.start)\n   *(.text)\n   initrd_size = initrd_end - initrd_start;\n   _etext = .;\n  }\n\n  .stab 0 : { *(.stab) }\n  .stabstr 0 : { *(.stabstr) }\n  .stab.excl 0 : { *(.stab.excl) }\n  .stab.exclstr 0 : { *(.stab.exclstr) }\n  .stab.index 0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment 0 : { *(.comment) }\n}\n","old_contents":"\/*\n *  linux\/arch\/arm\/boot\/bootp\/bootp.lds\n *\n *  Copyright (C) 2000-2002 Russell King\n *\n * This program is free software; you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n *\/\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS\n{\n  . = 0;\n  .text : {\n   _stext = .;\n   *(.start)\n   *(.text)\n   initrd_size = initrd_end - initrd_start;\n   _etext = .;\n  }\n  \n  .stab 0 : { *(.stab) }\n  .stabstr 0 : { *(.stabstr) }\n  .stab.excl 0 : { *(.stab.excl) }\n  .stab.exclstr 0 : { *(.stab.exclstr) }\n  .stab.index 0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment 0 : { *(.comment) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"be67e65b52ef590086f9a8ea52c2cb7761ffc6bb","subject":"Add a coment on _sram_origin's usage in elf2tab","message":"Add a coment on _sram_origin's usage in elf2tab\n","repos":"tock\/libtock-rs","old_file":"runtime\/libtock_layout.ld","new_file":"runtime\/libtock_layout.ld","new_contents":"\/* Layout file for Tock process binaries that use libtock-rs. This currently\n * implements static linking, because we do not have a working\n * position-independent relocation solution. This layout works for all\n * platforms libtock-rs supports (ARM and RISC-V).\n *\n * This layout should be included by a script that defines the FLASH and RAM\n * regions for the board as well as TBF_HEADER_SIZE. Here is a an example\n * process binary linker script to get started:\n *     MEMORY {\n *         FLASH (X) : ORIGIN = 0x10000, LENGTH = 0x10000\n *         RAM   (W) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     TBF_HEADER_SIZE = 0x48;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\n * FLASH refers to the area the process binary occupies in flash, including TBF\n * headers. RAM refers to the area the process will have access to in memory.\n * STACK_SIZE is the size of the process' stack (this layout file may round the\n * stack size up for alignment purposes). TBF_HEADER_SIZE must correspond to the\n * --protected-region-size flag passed to elf2tab.\n *\n * This places the flash sections in the following order:\n *     1. .rt_header -- Constants used by runtime initialization.\n *     2. .text      -- Executable code.\n *     3. .rodata    -- Read-only global data (e.g. most string constants).\n *     4. .data      -- Read-write data, copied to RAM at runtime.\n *\n * This places the RAM sections in the following order:\n *     1. .stack -- The stack grows downward. Putting it first gives us\n *                  MPU-based overflow detection.\n *     2. .data  -- Read-write data, initialized by copying from flash.\n *     3. .bss   -- Zero-initialized read-write global data.\n *     4. Heap   -- The heap (optional) comes after .bss and grows upwards to\n *                  the process break.\n *\/\n\n\/* TODO: Should TBF_HEADER_SIZE be configured via a similar mechanism to the\n * stack size? We should see if that is possible.\n *\/\n\n\/* GNU LD looks for `start` as an entry point by default, while LLVM's LLD looks\n * for `_start`. To be compatible with both, we manually specify an entry point.\n *\/\nENTRY(start)\n\nSECTIONS {\n    \/* Sections located in FLASH at runtime.\n     *\/\n\n    \/* Add a section where elf2tab will place the TBF headers, so that the rest\n     * of the FLASH sections are in the right locations. *\/\n    .tbf_header (NOLOAD) : {\n        . = . + TBF_HEADER_SIZE;\n    } > FLASH\n\n    \/* Runtime header. Contains values the linker knows that the runtime needs\n     * to look up.\n     *\/\n    .start ALIGN(4) : {\n        rt_header = .;\n        LONG(start);\n        LONG(ADDR(.bss) + SIZEOF(.bss)); \/* Initial process break *\/\n        LONG(_stack_top);\n        LONG(SIZEOF(.data));\n        LONG(LOADADDR(.data));\n        LONG(ADDR(.data));\n        LONG(SIZEOF(.bss));\n        LONG(ADDR(.bss));\n\n        *(.start)\n    } > FLASH\n\n    \/* Text section -- the application's code. *\/\n    .text ALIGN(4) : {\n        *(.text.*)\n    } > FLASH\n\n    \/* Read-only data section. Contains strings and other global constants. *\/\n    .rodata ALIGN(4) : {\n        *(.rodata.*)\n        \/* .data is placed after .rodata in flash. data_flash_start is used by\n         * AT() to place .data in flash as well as in rt_header.\n         *\/\n        _data_flash_start = .;\n    } > FLASH\n\n    \/* Sections located in RAM at runtime.\n     *\/\n\n    \/* Reserve space for the stack. Aligned to a multiple of 16 bytes for the\n     * RISC-V calling convention:\n     * https:\/\/riscv.org\/wp-content\/uploads\/2015\/01\/riscv-calling.pdf\n     *\/\n    .stack (NOLOAD) : {\n\t\/* _sram_origin is used by elf2tab:\n\t * https:\/\/github.com\/tock\/elf2tab\/blob\/master\/src\/main.rs#L301\n\t *\/\n        _sram_origin = .;\n        KEEP(*(.stack_buffer))\n        . = ALIGN(16);\n        _stack_top = .;  \/* Used in rt_header *\/\n    } > RAM\n\n    \/* Read-write data section. This is deployed as part of FLASH but is copied\n     * into RAM at runtime.\n     *\/\n    .data ALIGN(4) : AT(_data_flash_start) {\n        data_ram_start = .;\n        \/* .sdata is the RISC-V small data section *\/\n        *(.sdata .data)\n        \/* Pad to word alignment so the relocation loop can use word-sized\n         * copies.\n         *\/\n        . = ALIGN(4);\n    } > RAM\n\n    \/* BSS section. These are zero-initialized static variables. This section is\n     * not copied from FLASH into RAM but rather directly initialized, and is\n     * mainly put in this linker script so that we get an error if it overflows\n     * the RAM region.\n     *\/\n    .bss ALIGN(4) (NOLOAD) : {\n        \/* .sbss is the RISC-V small data section *\/\n        *(.sbss .bss.*)\n    } > RAM\n\n    _heap_start = ADDR(.bss) + SIZEOF(.bss);  \/* Used by rt_header *\/\n\n    \/* Sections we do not need. *\/\n    \/DISCARD\/ :\n    {\n      *(.ARM.exidx .eh_frame)\n    }\n}\n","old_contents":"\/* Layout file for Tock process binaries that use libtock-rs. This currently\n * implements static linking, because we do not have a working\n * position-independent relocation solution. This layout works for all\n * platforms libtock-rs supports (ARM and RISC-V).\n *\n * This layout should be included by a script that defines the FLASH and RAM\n * regions for the board as well as TBF_HEADER_SIZE. Here is a an example\n * process binary linker script to get started:\n *     MEMORY {\n *         FLASH (X) : ORIGIN = 0x10000, LENGTH = 0x10000\n *         RAM   (W) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     TBF_HEADER_SIZE = 0x48;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\n * FLASH refers to the area the process binary occupies in flash, including TBF\n * headers. RAM refers to the area the process will have access to in memory.\n * STACK_SIZE is the size of the process' stack (this layout file may round the\n * stack size up for alignment purposes). TBF_HEADER_SIZE must correspond to the\n * --protected-region-size flag passed to elf2tab.\n *\n * This places the flash sections in the following order:\n *     1. .rt_header -- Constants used by runtime initialization.\n *     2. .text      -- Executable code.\n *     3. .rodata    -- Read-only global data (e.g. most string constants).\n *     4. .data      -- Read-write data, copied to RAM at runtime.\n *\n * This places the RAM sections in the following order:\n *     1. .stack -- The stack grows downward. Putting it first gives us\n *                  MPU-based overflow detection.\n *     2. .data  -- Read-write data, initialized by copying from flash.\n *     3. .bss   -- Zero-initialized read-write global data.\n *     4. Heap   -- The heap (optional) comes after .bss and grows upwards to\n *                  the process break.\n *\/\n\n\/* TODO: Should TBF_HEADER_SIZE be configured via a similar mechanism to the\n * stack size? We should see if that is possible.\n *\/\n\n\/* GNU LD looks for `start` as an entry point by default, while LLVM's LLD looks\n * for `_start`. To be compatible with both, we manually specify an entry point.\n *\/\nENTRY(start)\n\nSECTIONS {\n    \/* Sections located in FLASH at runtime.\n     *\/\n\n    \/* Add a section where elf2tab will place the TBF headers, so that the rest\n     * of the FLASH sections are in the right locations. *\/\n    .tbf_header (NOLOAD) : {\n        . = . + TBF_HEADER_SIZE;\n    } > FLASH\n\n    \/* Runtime header. Contains values the linker knows that the runtime needs\n     * to look up.\n     *\/\n    .start ALIGN(4) : {\n        rt_header = .;\n        LONG(start);\n        LONG(ADDR(.bss) + SIZEOF(.bss)); \/* Initial process break *\/\n        LONG(_stack_top);\n        LONG(SIZEOF(.data));\n        LONG(LOADADDR(.data));\n        LONG(ADDR(.data));\n        LONG(SIZEOF(.bss));\n        LONG(ADDR(.bss));\n\n        *(.start)\n    } > FLASH\n\n    \/* Text section -- the application's code. *\/\n    .text ALIGN(4) : {\n        *(.text.*)\n    } > FLASH\n\n    \/* Read-only data section. Contains strings and other global constants. *\/\n    .rodata ALIGN(4) : {\n        *(.rodata.*)\n        \/* .data is placed after .rodata in flash. data_flash_start is used by\n         * AT() to place .data in flash as well as in rt_header.\n         *\/\n        _data_flash_start = .;\n    } > FLASH\n\n    \/* Sections located in RAM at runtime.\n     *\/\n\n    \/* Reserve space for the stack. Aligned to a multiple of 16 bytes for the\n     * RISC-V calling convention:\n     * https:\/\/riscv.org\/wp-content\/uploads\/2015\/01\/riscv-calling.pdf\n     *\/\n    .stack (NOLOAD) : {\n        _sram_origin = .;\n        KEEP(*(.stack_buffer))\n        . = ALIGN(16);\n        _stack_top = .;  \/* Used in rt_header *\/\n    } > RAM\n\n    \/* Read-write data section. This is deployed as part of FLASH but is copied\n     * into RAM at runtime.\n     *\/\n    .data ALIGN(4) : AT(_data_flash_start) {\n        data_ram_start = .;\n        \/* .sdata is the RISC-V small data section *\/\n        *(.sdata .data)\n        \/* Pad to word alignment so the relocation loop can use word-sized\n         * copies.\n         *\/\n        . = ALIGN(4);\n    } > RAM\n\n    \/* BSS section. These are zero-initialized static variables. This section is\n     * not copied from FLASH into RAM but rather directly initialized, and is\n     * mainly put in this linker script so that we get an error if it overflows\n     * the RAM region.\n     *\/\n    .bss ALIGN(4) (NOLOAD) : {\n        \/* .sbss is the RISC-V small data section *\/\n        *(.sbss .bss.*)\n    } > RAM\n\n    _heap_start = ADDR(.bss) + SIZEOF(.bss);  \/* Used by rt_header *\/\n\n    \/* Sections we do not need. *\/\n    \/DISCARD\/ :\n    {\n      *(.ARM.exidx .eh_frame)\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8c4f98d263865d00199fc9b5f7870a0f134c634b","subject":"linker: Fix _vector_end symbol location","message":"linker: Fix _vector_end symbol location\n\nThe 219d5b5adb22 commit is breaking the STM32F0 platforms.\n\nThe problem is that the PR is changing the location the _vector_end\nsymbol is pointing to. These platforms require the symbol to be pointing\nto a location in memory after the IRQ vector table.\n\nFix the issue by introducing a new _vector_end symbol when the IRQ\nvector table is present that points to the correct location.\n\nSigned-off-by: Carlo Caione <ca4506c8c654a4ccf75802e86b5d162c1e96f065@baylibre.com>\n","repos":"finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr","old_file":"include\/zephyr\/linker\/irq-vector-table-section.ld","new_file":"include\/zephyr\/linker\/irq-vector-table-section.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n. = ALIGN(CONFIG_ARCH_IRQ_VECTOR_TABLE_ALIGN);\nKEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\n\/*\n * Some ARM platforms require this symbol to be placed after the IRQ vector\n * table (like STM32F0). The symbol defined here is overriding the one in\n * arch\/arm\/core\/aarch32\/vector_table.ld when the IRQ vector table is enbled.\n *\/\n _vector_end = .;\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n. = ALIGN(CONFIG_ARCH_IRQ_VECTOR_TABLE_ALIGN);\nKEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"81e4fdcf006210545bf50d3174019d48f82bdabb","subject":"Move vtable back to RAM so moderate complexity projects can be built","message":"Move vtable back to RAM so moderate complexity projects can be built\n","repos":"Adam5Wu\/Arduino,Adam5Wu\/Arduino,Adam5Wu\/Arduino,Adam5Wu\/Arduino,Adam5Wu\/Arduino","old_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nEXTERN(core_version)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    *libc.a:(.literal .text .literal.* .text.*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *libstdc++.a:(.literal .text .literal.* .text.*)\n    *liblwip_gcc.a:(.literal .text .literal.* .text.*)\n    *liblwip_src.a:(.literal .text .literal.* .text.*)\n    *liblwip2.a:(.literal .text .literal.* .text.*)\n    *liblwip2_1460.a:(.literal .text .literal.* .text.*)\n    *libaxtls.a:(.literal .text .literal.* .text.*)\n    *libbearssl.a:(.literal .text .literal.* .text.*)\n    *libat.a:(.literal.* .text.*)\n    *libcrypto.a:(.literal.* .text.*)\n    *libespnow.a:(.literal.* .text.*)\n    *libjson.a:(.literal.* .text.*)\n    *liblwip.a:(.literal.* .text.*)\n    *libmesh.a:(.literal.* .text.*)\n    *libnet80211.a:(.literal.* .text.*)\n    *libsmartconfig.a:(.literal.* .text.*)\n    *libssl.a:(.literal.* .text.*)\n    *libupgrade.a:(.literal.* .text.*)\n    *libwpa.a:(.literal.* .text.*)\n    *libwpa2.a:(.literal.* .text.*)\n    *libwps.a:(.literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n\/*    *(.rodata._ZTV*) *\/\/* C++ vtables *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nEXTERN(core_version)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    *libc.a:(.literal .text .literal.* .text.*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *libstdc++.a:(.literal .text .literal.* .text.*)\n    *liblwip_gcc.a:(.literal .text .literal.* .text.*)\n    *liblwip_src.a:(.literal .text .literal.* .text.*)\n    *liblwip2.a:(.literal .text .literal.* .text.*)\n    *liblwip2_1460.a:(.literal .text .literal.* .text.*)\n    *libaxtls.a:(.literal .text .literal.* .text.*)\n    *libbearssl.a:(.literal .text .literal.* .text.*)\n    *libat.a:(.literal.* .text.*)\n    *libcrypto.a:(.literal.* .text.*)\n    *libespnow.a:(.literal.* .text.*)\n    *libjson.a:(.literal.* .text.*)\n    *liblwip.a:(.literal.* .text.*)\n    *libmesh.a:(.literal.* .text.*)\n    *libnet80211.a:(.literal.* .text.*)\n    *libsmartconfig.a:(.literal.* .text.*)\n    *libssl.a:(.literal.* .text.*)\n    *libupgrade.a:(.literal.* .text.*)\n    *libwpa.a:(.literal.* .text.*)\n    *libwpa2.a:(.literal.* .text.*)\n    *libwps.a:(.literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    *(.rodata._ZTV*) \/* C++ vtables *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"06043de5a354df515cc9d62d646e0a479ccf7b9f","subject":"Delete kernel.ld","message":"Delete kernel.ld","repos":"jspaulse\/sugarcat,jspaulse\/sugarcat,jspaulse\/sugarcat","old_file":"config\/vexp_cfg\/kernel.ld","new_file":"config\/vexp_cfg\/kernel.ld","new_contents":"","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_vexpress_boot)\n\nkp_start\t= 0x60000000;\nkv_start \t= 0x80000000;\n\nSECTIONS {\n\t\n\t. = 0x60004000;\n\tk_pgd = .;\n\n\t. = 0x60008000;\n\t\n\t.start_sec : {\n\t\tss_start = .;\n\t\t\n\t\t\/* text *\/\n\t\tbuild\/vexpress_boot.o(.text)\n\t\tbuild\/vexpress_boot_init.o(.text .text.*)\n\t\tbuild\/vexpress_init.o(.text .text.*)\n\t\tbuild\/mach_init_printf.o(.text .text.*)\n\t\t\n\t\t\/* rodata *\/\n\t\tbuild\/vexpress_boot.o(.rodata .rodata.*)\n\t\tbuild\/vexpress_boot_init.o(.rodata .rodata.*)\n\t\tbuild\/vexpress_init.o(.rodata .rodata.*)\n\t\tbuild\/mach_init_printf.o(.rodata .rodata.*)\n\t\t\n\t\t\/* data *\/\n\t\tbuild\/vexpress_boot.o(.data .data.*)\n\t\tbuild\/vexpress_boot_init.o(.data .data.*)\n\t\tbuild\/vexpress_init.o(.data .data.*)\n\t\tbuild\/mach_init_printf.o(.data .data.*)\n\t\t\n\t\t\/* bss *\/\n\t\tss_bss_start = .;\n\t\t\n\t\tbuild\/vexpress_boot.o(.bss .bss.* COMMON)\n\t\tbuild\/vexpress_boot_init.o(.bss .bss.* COMMON)\n\t\tbuild\/vexpress_init.o(.bss .bss.* COMMON)\n\t\tbuild\/mach_init_printf.o(.bss .bss.* COMMON)\n\n\t\tss_bss_end\t= .;\n\t\t\n\t\t\/* kernel stack *\/\n\t\t. = ALIGN(0x1000);\n\t\t. += 0x1000;\n\t\tkern_stack = .;\n\n\t\t. = ALIGN(0x1000);\n\t\tss_end = .;\n\t}\n\t\n\t. = kv_start + (ss_end - kp_start);\n\t\n\tk_start = .;\n\t.text : AT(ss_end) { \n\t\t*(.text .text* .gnu.linkonce.t.*) \n\t}\n\t\n\tPROVIDE(etext = .);\n\t\n\t\/* everything but boot *\/\n    .rodata : { *(.rodata*) } \n    .data : { *(.data*) } \n    .bss : { \n\t\tbss_start = .;\n\t\t*(.bss*) \n\t\tbss_end\t= .;\n\t}\n\t\n\t. = ALIGN(0x1000);\n\tk_end = .;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5c389242ddc32e24cd3ec28f1eac91f54464a8df","subject":"updated ldoc config","message":"updated ldoc config\n","repos":"darkstalker\/LuaTwit","old_file":"config.ld","new_file":"config.ld","new_contents":"project = \"LuaTwit\"\ntitle = \"LuaTwit reference\"\ndescription = \"LuaTwit library\"\nbacktick_references = true\nfile = \"src\"\nexamples = \"examples\"\nformat = \"markdown\"\nplain = true\nreadme = \"README.md\"\n","old_contents":"project = \"LuaTwit\"\ntitle = \"LuaTwit reference\"\ndescription = \"LuaTwit library\"\nbacktick_references = true\nfile = \"src\"\nexamples = \"examples\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7ee7bc8f7891e6dffcd02c871ca6c7958c7a27f0","subject":"fix linker script","message":"fix linker script\n","repos":"jgottula\/justix,jgottula\/justix","old_file":"kern\/kern.ld","new_file":"kern\/kern.ld","new_contents":"OUTPUT_FORMAT(elf32-i386)\n\nKERN_OFFSET = 0x00100000;\n\nSECTIONS {\n\tENTRY(kern_entry)\n\t\n\t.text.init (KERN_OFFSET) : {\n\t_INIT_START = .;\n\t\tsrc\/core\/init.o(.text)\n\t_INIT_END = .;\n\t}\n\t\n\t.text ALIGN (0x1000) : {\n\t_TEXT_START = .;\n\t\t*(.text)\n\t_TEXT_END = .;\n\t}\n\t\n\t.data ALIGN (0x1000) : {\n\t_DATA_START = .;\n\t\t*(.data)\n\t_DATA_END = .;\n\t}\n\t\n\t.rodata ALIGN (0x1000) : {\n\t_RODATA_START = .;\n\t\t*(.rodata)\n\t_RODATA_END = .;\n\t}\n\t\n\t.bss ALIGN (0x1000) : {\n\t_BSS_START = .;\n\t\t*(.bss)\n\t_BSS_END = .;\n\t}\n}\n","old_contents":"OUTPUT_FORMAT(elf32-i386)\n\nKERN_OFFSET = 0x00100000;\n\nSECTIONS {\n\tENTRY(kern_entry)\n\t\n\t.text.start (KERN_OFFSET) : {\n\t_INIT_START = .;\n\t\tsrc\/core\/init.o(.text)\n\t_INIT_END = .;\n\t}\n\t\n\t.text ALIGN (0x1000) : {\n\t_INIT_START = .;\n\t\t*(.text)\n\t_INIT_END = .;\n\t}\n\t\n\t.data ALIGN (0x1000) : {\n\t_DATA_START = .;\n\t\t*(.data)\n\t_DATA_END = .;\n\t}\n\t\n\t.rodata ALIGN (0x1000) : {\n\t_RODATA_START = .;\n\t\t*(.rodata)\n\t_RODATA_END = .;\n\t}\n\t\n\t.bss ALIGN (0x1000) : {\n\t_BSS_START = .;\n\t\t*(.bss)\n\t_BSS_END = .;\n\t}\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"0ad77f2f063b5ea43b6daf62e4005adaeab4790e","subject":"rp2\/memmap_mp.ld: Update for latest SDK.","message":"rp2\/memmap_mp.ld: Update for latest SDK.\n","repos":"pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython","old_file":"ports\/rp2\/memmap_mp.ld","new_file":"ports\/rp2\/memmap_mp.ld","new_contents":"\/* Based on GCC ARM embedded samples.\n   Defines the following symbols for use by code:\n    __exidx_start\n    __exidx_end\n    __etext\n    __data_start__\n    __preinit_array_start\n    __preinit_array_end\n    __init_array_start\n    __init_array_end\n    __fini_array_start\n    __fini_array_end\n    __data_end__\n    __bss_start__\n    __bss_end__\n    __end__\n    end\n    __HeapLimit\n    __StackLimit\n    __StackTop\n    __stack (== StackTop)\n*\/\n\nMEMORY\n{\n    FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k\n    RAM(rwx) : ORIGIN =  0x20000000, LENGTH = 256k\n    SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k\n    SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k\n}\n\nENTRY(_entry_point)\n\nSECTIONS\n{\n    \/* Second stage bootloader is prepended to the image. It must be 256 bytes big\n       and checksummed. It is usually built by the boot_stage2 target\n       in the Raspberry Pi Pico SDK\n    *\/\n\n    .flash_begin : {\n        __flash_binary_start = .;\n    } > FLASH\n\n    .boot2 : {\n        __boot2_start__ = .;\n        KEEP (*(.boot2))\n        __boot2_end__ = .;\n    } > FLASH\n\n    ASSERT(__boot2_end__ - __boot2_start__ == 256,\n        \"ERROR: Pico second stage bootloader must be 256 bytes in size\")\n\n    \/* The second stage will always enter the image at the start of .text.\n       The debugger will use the ELF entry point, which is the _entry_point\n       symbol if present, otherwise defaults to start of .text.\n       This can be used to transfer control back to the bootrom on debugger\n       launches only, to perform proper flash setup.\n    *\/\n\n    .text : {\n        __logical_binary_start = .;\n        KEEP (*(.vectors))\n        KEEP (*(.binary_info_header))\n        __binary_info_header_end = .;\n        KEEP (*(.reset))\n        \/* TODO revisit this now memset\/memcpy\/float in ROM *\/\n        \/* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from\n         * FLASH ... we will include any thing excluded here in .data below by default *\/\n        *(.init)\n        \/* Change for MicroPython... excluse gc.c, parse.c, vm.c from flash *\/\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a: *lib_a-mem*.o *libm.a: *gc.c.obj *vm.c.obj *parse.c.obj) .text*)\n        *(.fini)\n        \/* Pull all c'tors into .text *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n        \/* Followed by destructors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n    .rodata : {\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*)\n        . = ALIGN(4);\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))\n        . = ALIGN(4);\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    \/* Machine inspectable binary information *\/\n    . = ALIGN(4);\n    __binary_info_start = .;\n    .binary_info :\n    {\n        KEEP(*(.binary_info.keep.*))\n        *(.binary_info.*)\n    } > FLASH\n    __binary_info_end = .;\n    . = ALIGN(4);\n\n    \/* End of .text-like segments *\/\n    __etext = .;\n\n   .ram_vector_table (COPY): {\n        *(.ram_vector_table)\n    } > RAM\n\n    .data : {\n        __data_start__ = .;\n        *(vtable)\n\n        *(.time_critical*)\n\n        \/* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM *\/\n        *(.text*)\n        . = ALIGN(4);\n        *(.rodata*)\n        . = ALIGN(4);\n\n        *(.data*)\n\n        . = ALIGN(4);\n        *(.after_data.*)\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__mutex_array_start = .);\n        KEEP(*(SORT(.mutex_array.*)))\n        KEEP(*(.mutex_array))\n        PROVIDE_HIDDEN (__mutex_array_end = .);\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(SORT(.preinit_array.*)))\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM AT> FLASH\n\n    .uninitialized_data (COPY): {\n        . = ALIGN(4);\n        *(.uninitialized_data*)\n    } > RAM\n\n    \/* Start and end symbols must be word-aligned *\/\n    .scratch_x : {\n        __scratch_x_start__ = .;\n        *(.scratch_x.*)\n        . = ALIGN(4);\n        __scratch_x_end__ = .;\n    } > SCRATCH_X AT > FLASH\n    __scratch_x_source__ = LOADADDR(.scratch_x);\n\n    .scratch_y : {\n        __scratch_y_start__ = .;\n        *(.scratch_y.*)\n        . = ALIGN(4);\n        __scratch_y_end__ = .;\n    } > SCRATCH_Y AT > FLASH\n    __scratch_y_source__ = LOADADDR(.scratch_y);\n\n    .bss  : {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack*_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later\n     *\n     * stack1 section may be empty\/missing if platform_launch_core1 is not used *\/\n\n    \/* by default we put core 0 stack at the end of scratch Y, so that if core 1\n     * stack is not used then all of SCRATCH_X is free.\n     *\/\n    .stack1_dummy (COPY):\n    {\n        *(.stack1*)\n    } > SCRATCH_X\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SCRATCH_Y\n\n    .flash_end : {\n        __flash_binary_end = .;\n    } > FLASH\n\n    \/* stack limit is poorly named, but historically is maximum heap ptr *\/\n    __StackLimit = ORIGIN(RAM) + LENGTH(RAM);\n    __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);\n    __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);\n    __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);\n    __StackBottom = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed\")\n\n    ASSERT( __binary_info_header_end - __logical_binary_start <= 256, \"Binary info must be in first 256 bytes of the binary\")\n    \/* todo assert on extra code *\/\n}\n\n","old_contents":"\/* Based on GCC ARM embedded samples.\n   Defines the following symbols for use by code:\n    __exidx_start\n    __exidx_end\n    __etext\n    __data_start__\n    __preinit_array_start\n    __preinit_array_end\n    __init_array_start\n    __init_array_end\n    __fini_array_start\n    __fini_array_end\n    __data_end__\n    __bss_start__\n    __bss_end__\n    __end__\n    end\n    __HeapLimit\n    __StackLimit\n    __StackTop\n    __stack (== StackTop)\n*\/\n\nMEMORY\n{\n    FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k\n    RAM(rwx) : ORIGIN =  0x20000000, LENGTH = 256k\n    SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k\n    SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k\n}\n\nENTRY(_entry_point)\n\nSECTIONS\n{\n    \/* Second stage bootloader is prepended to the image. It must be 256 bytes big\n       and checksummed. It is usually built by the boot_stage2 target\n       in the Pico SDK\n    *\/\n\n    .flash_begin : {\n        __flash_binary_start = .;\n    } > FLASH\n\n    .boot2 : {\n        __boot2_start__ = .;\n        KEEP (*(.boot2))\n        __boot2_end__ = .;\n    } > FLASH\n\n    ASSERT(__boot2_end__ - __boot2_start__ == 256,\n        \"ERROR: Pico second stage bootloader must be 256 bytes in size\")\n\n    \/* The second stage will always enter the image at the start of .text.\n       The debugger will use the ELF entry point, which is the _entry_point\n       symbol if present, otherwise defaults to start of .text.\n       This can be used to transfer control back to the bootrom on debugger\n       launches only, to perform proper flash setup.\n    *\/\n\n    .text : {\n        __reset_start = .;\n        KEEP (*(.reset))\n        . = ALIGN(256);\n        __reset_end = .;\n        ASSERT(__reset_end - __reset_start == 256, \"ERROR: reset section should only be 256 bytes\");\n        KEEP (*(.vectors))\n        \/* TODO revisit this now memset\/memcpy\/float in ROM *\/\n        \/* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from\n         * FLASH ... we will include any thing excluded here in .data below by default *\/\n        *(.init)\n        \/* Change for MicroPython... excluse gc.c, parse.c, vm.c from flash *\/\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a: *lib_a-mem*.o *libm.a: *gc.c.obj *vm.c.obj *parse.c.obj) .text*)\n        *(.fini)\n        \/* Pull all c'tors into .text *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n        \/* Followed by destructors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n    .rodata : {\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*)\n        . = ALIGN(4);\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))\n        . = ALIGN(4);\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    \/* Machine inspectable binary information *\/\n    . = ALIGN(4);\n    __binary_info_start = .;\n    .binary_info :\n    {\n        KEEP(*(.binary_info.keep.*))\n        *(.binary_info.*)\n    } > FLASH\n    __binary_info_end = .;\n    . = ALIGN(4);\n\n    \/* End of .text-like segments *\/\n    __etext = .;\n\n   .ram_vector_table (COPY): {\n        *(.ram_vector_table)\n    } > RAM\n\n    .data : {\n        __data_start__ = .;\n        *(vtable)\n\n        *(.time_critical*)\n\n        \/* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM *\/\n        *(.text*)\n        . = ALIGN(4);\n        *(.rodata*)\n        . = ALIGN(4);\n\n        *(.data*)\n\n        . = ALIGN(4);\n        *(.after_data.*)\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__mutex_array_start = .);\n        KEEP(*(SORT(.mutex_array.*)))\n        KEEP(*(.mutex_array))\n        PROVIDE_HIDDEN (__mutex_array_end = .);\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(SORT(.preinit_array.*)))\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM AT> FLASH\n\n    .uninitialized_data (COPY): {\n        . = ALIGN(4);\n        *(.uninitialized_data*)\n    } > RAM\n\n    \/* Start and end symbols must be word-aligned *\/\n    .scratch_x : {\n        __scratch_x_start__ = .;\n        *(.scratch_x.*)\n        . = ALIGN(4);\n        __scratch_x_end__ = .;\n    } > SCRATCH_X AT > FLASH\n    __scratch_x_source__ = LOADADDR(.scratch_x);\n\n    .scratch_y : {\n        __scratch_y_start__ = .;\n        *(.scratch_y.*)\n        . = ALIGN(4);\n        __scratch_y_end__ = .;\n    } > SCRATCH_Y AT > FLASH\n    __scratch_y_source__ = LOADADDR(.scratch_y);\n\n    .bss  : {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack*_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later\n     *\n     * stack1 section may be empty\/missing if platform_launch_core1 is not used *\/\n\n    \/* by default we put core 0 stack at the end of scratch Y, so that if core 1\n     * stack is not used then all of SCRATCH_X is free.\n     *\/\n    .stack1_dummy (COPY):\n    {\n        *(.stack1*)\n    } > SCRATCH_X\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SCRATCH_Y\n\n    .flash_end : {\n        __flash_binary_end = .;\n    } > FLASH\n\n    \/* stack limit is poorly named, but historically is maximum heap ptr *\/\n    __StackLimit = ORIGIN(RAM) + LENGTH(RAM);\n    __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);\n    __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);\n    __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);\n    __StackBottom = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed\")\n    \/* todo assert on extra code *\/\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7a616ca34c43ba41035b9902efa172fb237c64ad","subject":"Compile network and RTOS with GCC_ARM","message":"Compile network and RTOS with GCC_ARM\n","repos":"Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,kubostech\/KubOS,Psykar\/kubos","old_file":"TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_file":"TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    \/* Code can explicitly ask for data to be\n       placed in these higher RAM banks where\n       they will be left uninitialized.\n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n    \n    \/* .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n        *(.data.$RAM2*)\n        *(.data.$ETH_RAM*)\n       . = ALIGN(4) ;\n    } > ETH_RAM AT>FLASH\n        \n    .bss_RAM2 : ALIGN(4)\n    {\n        *(.bss.$RAM2*)\n        *(.bss.$ETH_RAM*)\n       . = ALIGN(4) ;\n    } > ETH_RAM\n    *\/\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7da47c6982f7ad68c48f24238573e53549aa72a0","subject":"include: scripts: fix typos in priv_stacks.ld","message":"include: scripts: fix typos in priv_stacks.ld\n\nThis commit fixes some (minor) typos in priv_stack.ld linker script.\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\n","repos":"zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,nashif\/zephyr","old_file":"include\/linker\/priv_stacks.ld","new_file":"include\/linker\/priv_stacks.ld","new_contents":"\/*\n * Copyright (c) 2017 Linaro Limited\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#ifdef CONFIG_USERSPACE\n\t\/* Constraints:\n         *\n         * - changes to the size of this section between build phases\n         *   *must not* shift the memory address of any kernel objects,\n         *   since it contains a hashtable of the memory addresses of those\n         *   kernel objects\n         *\n         * - It is OK if this section itself is shifted in between builds; for\n         *   example some arches may precede this section with generated MMU\n         *    page tables which are also unpredictable in size.\n         *\n         * The size of the\n\t * gperf tables is both a function of the number of kernel objects,\n\t * *and* the specific memory addresses being hashed. It is not something\n\t * that can be predicted without actually building and compiling it.\n         *\/\n\tSECTION_DATA_PROLOGUE(priv_stacks,,)\n\t{\n\t*(\".priv_stacks.data*\")\n\n        \/* This is also unpredictable in size, and has the same constraints.\n         * On XIP systems this will get put at the very end of ROM.\n         *\/\n#ifndef CONFIG_XIP\n\t*(\".priv_stacks.rodata*\")\n#endif\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n","old_contents":"\/*\n * Copyright (c) 2017 Linaro Limited\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#ifdef CONFIG_USERSPACE\n\t\/* Constraints:\n         *\n         * - changes to the size of this section between build phases\n         *   *must not* shift the memory address of any kernel obejcts,\n         *   since it contains a hashtable of the memory addresses of those\n         *   kernel objects\n         *\n         * - It is OK if this section itself is shifted in between builds; for\n         *   example some arches may precede this section with generated MMU\n         *    page tables which are also unpredictable in size.\n         *\n         * The size of the\n\t * gperf tables is both a function of the number of kernel objects,\n\t * *and* the specific memory addresses being hashed. It is not something\n\t * that can be predicted without actually building and compling it.\n         *\/\n\tSECTION_DATA_PROLOGUE(priv_stacks,,)\n\t{\n\t*(\".priv_stacks.data*\")\n\n        \/* This is also unpredictable in size, and has the same constraints.\n         * On XIP systems this will get put at the very end of ROM.\n         *\/\n#ifndef CONFIG_XIP\n\t*(\".priv_stacks.rodata*\")\n#endif\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1a779e3dbdc42a347777492881ea0a46cf351380","subject":"[x86_64] add missing colon in linker script oops","message":"[x86_64] add missing colon in linker script\noops\n","repos":"hawkw\/sos-kernel,rachlmac\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .rodata :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot))\n        *(.rodata .rodata.*)\n        . = ALIGN(4K);\n    }\n\n    .text :\n    {\n        *(.text .text.*)\n        . = ALIGN(4K);\n    }\n    .text :\n     {\n       *(.text .text.*)\n       . = ALIGN(4K);\n     }\n\n     .data :\n     {\n       *(.data .data.*)\n       . = ALIGN(4K);\n     }\n\n     .bss :\n     {\n       *(.bss .bss.*)\n       . = ALIGN(4K);\n     }\n\n    .data.rel.ro : ALIGN(4K) {\n       *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n        . = ALIGN(4K);\n    }\n\n    .gcc_except_table : ALIGN(4K) {\n      *(.gcc_except_table)\n      . = ALIGN(4K);\n    }\n}\n","old_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .rodata\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot))\n        *(.rodata .rodata.*)\n        . = ALIGN(4K);\n    }\n\n    .text :\n    {\n        *(.text .text.*)\n        . = ALIGN(4K);\n    }\n    .text :\n     {\n       *(.text .text.*)\n       . = ALIGN(4K);\n     }\n\n     .data :\n     {\n       *(.data .data.*)\n       . = ALIGN(4K);\n     }\n\n     .bss :\n     {\n       *(.bss .bss.*)\n       . = ALIGN(4K);\n     }\n\n    .data.rel.ro : ALIGN(4K) {\n       *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n        . = ALIGN(4K);\n    }\n\n    .gcc_except_table : ALIGN(4K) {\n      *(.gcc_except_table)\n      . = ALIGN(4K);\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"090f8ef7b9286716b967125977d3c38e5dcb686d","subject":"Coalesce all vmm .text* sections into .text, and the same for .data and .bss","message":"Coalesce all vmm .text* sections into .text, and the same for .data and .bss\n","repos":"monocasa\/remu-playground,monocasa\/remu-playground","old_file":"src\/vmm\/Linker.ld","new_file":"src\/vmm\/Linker.ld","new_contents":"ENTRY(__entry_point)\n\nVIRT_BASE = 0xFFFFFFFF80000000;\n\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.boot :\n\t{\n\t\t*(.mbhdr)\n\t\t_loadStart = .;\n\t\t*(.boot)\n\t\t. = ALIGN(4096);\n\t\t__boot_pml4 = .;\n\t\t. += 0x1000;\n\t\t__boot_pml3 = .;\n\t\t. += 0x1000;\n\t\t__boot_pml2 = .;\n\t\t. += 0x1000;\n\n\t\t. += 0x8000;\n\t\t__stack = .;\n\t}\n\n\t. += VIRT_BASE;\n\n\t.text ALIGN(0x1000) : AT(ADDR(.text) - VIRT_BASE)\n\t{\n\t\t*(.text*)\n\t\t*(.gnu.linkonce.t*)\n\t}\n\n\t.data ALIGN(0x1000) : AT(ADDR(.data) - VIRT_BASE)\n\t{\n\t\t*(.data*)\n\t\t*(.gnu.linkonce.d*)\n\t}\n\n\t.rodata ALIGN(0x1000) : AT(ADDR(.rodata) - VIRT_BASE)\n\t{\n\t\t*(.rodata*)\n\t\t*(.gnu.linkonce.r*)\n\t}\n\n\t__load_end = . - VIRT_BASE;\n\n\t.bss ALIGN(0x1000) : AT(ADDR(.bss) - VIRT_BASE)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss*)\n\t\t*(.gnu.linkonce.b*)\n\t}\n\n\t__bss_end = . - VIRT_BASE;\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.comment)\n\t\t*(.eh_frame)\n\t}\n}\n\n","old_contents":"ENTRY(__entry_point)\n\nVIRT_BASE = 0xFFFFFFFF80000000;\n\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.boot :\n\t{\n\t\t*(.mbhdr)\n\t\t_loadStart = .;\n\t\t*(.boot)\n\t\t. = ALIGN(4096);\n\t\t__boot_pml4 = .;\n\t\t. += 0x1000;\n\t\t__boot_pml3 = .;\n\t\t. += 0x1000;\n\t\t__boot_pml2 = .;\n\t\t. += 0x1000;\n\n\t\t. += 0x8000;\n\t\t__stack = .;\n\t}\n\n\t. += VIRT_BASE;\n\n\t.text ALIGN(0x1000) : AT(ADDR(.text) - VIRT_BASE)\n\t{\n\t\t*(.text)\n\t\t*(.gnu.linkonce.t*)\n\t}\n\n\t.data ALIGN(0x1000) : AT(ADDR(.data) - VIRT_BASE)\n\t{\n\t\t*(.data)\n\t\t*(.gnu.linkonce.d*)\n\t}\n\n\t.rodata ALIGN(0x1000) : AT(ADDR(.rodata) - VIRT_BASE)\n\t{\n\t\t*(.rodata*)\n\t\t*(.gnu.linkonce.r*)\n\t}\n\n\t__load_end = . - VIRT_BASE;\n\n\t.bss ALIGN(0x1000) : AT(ADDR(.bss) - VIRT_BASE)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.gnu.linkonce.b*)\n\t}\n\n\t__bss_end = . - VIRT_BASE;\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.comment)\n\t\t*(.eh_frame)\n\t}\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"248968863595fb285b1209927e27c37b06faf857","subject":"nrf\/boards: Update memory.ld to include bootloader offsets.","message":"nrf\/boards: Update memory.ld to include bootloader offsets.\n\nAdding variables that can be set from other linker scripts:\n\n- _bootloader_head_size:\n    Bootloader flash offset in front of the application.\n\n- _bootloader_tail_size:\n    Bootloader offset from the tail of the flash.\n    In case the bootloader is located at the end.\n\n- _bootloader_head_ram_size:\n    Bootloader RAM usage in front of the application.\n\nUpdated calculations of application flash and RAM.\n","repos":"henriknelson\/micropython,bvernoux\/micropython,adafruit\/circuitpython,henriknelson\/micropython,henriknelson\/micropython,henriknelson\/micropython,bvernoux\/micropython,adafruit\/circuitpython,bvernoux\/micropython,adafruit\/circuitpython,bvernoux\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,bvernoux\/micropython,henriknelson\/micropython","old_file":"ports\/nrf\/boards\/memory.ld","new_file":"ports\/nrf\/boards\/memory.ld","new_contents":"\n\/* Flash layout: bootloader_head | softdevice     | application     | filesystem    | bootloader_tail *\/\n\/* RAM layout:   bootloader RAM  | softdevice RAM  | application RAM *\/\n_bootloader_head_size = DEFINED(_bootloader_head_size) ? _bootloader_head_size : 0;\n_bootloader_tail_size = DEFINED(_bootloader_tail_size) ? _bootloader_tail_size : 0;\n_bootloader_head_ram_size = DEFINED(_bootloader_head_ram_size) ? _bootloader_head_ram_size : 0;\n_head_size     = DEFINED(_sd_size) ? _sd_size : _bootloader_head_size;\n_head_ram      = DEFINED(_sd_ram)  ? _sd_ram : _bootloader_head_ram_size;\n_sd_size       = DEFINED(_sd_size) ? _sd_size : 0;\n_sd_ram        = DEFINED(_sd_ram)  ? _sd_ram : 0;\n_fs_size       = DEFINED(_fs_size) ? _fs_size : 64K; \/* TODO: set to 0 if not using the filesystem *\/\n_app_size      = _flash_size - _head_size - _fs_size  - _bootloader_tail_size;\n_app_start     = _head_size;\n_fs_start      = _head_size + _app_size;\n_fs_end        = _fs_start + _fs_size;\n_app_ram_start = 0x20000000 + _head_ram;\n_app_ram_size  = _ram_size - _head_ram;\n_heap_start    = _ebss;\n_heap_end      = _ram_end - _stack_size;\n_heap_size     = _heap_end - _heap_start;\n\nASSERT(_heap_size >= _minimum_heap_size, \"not enough RAM left for heap\")\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_TEXT (rx) : ORIGIN = _app_start,     LENGTH = _app_size     \/* app *\/\n    RAM (xrw)       : ORIGIN = _app_ram_start, LENGTH = _app_ram_size\n}\n","old_contents":"\n\/* Flash layout: softdevice     | application     | filesystem *\/\n\/* RAM layout:   softdevice RAM | application RAM *\/\n\n_ram_start     = DEFINED(_ram_start) ? _ram_start : 0x20000000;\n_flash_start   = DEFINED(_flash_start) ? _flash_start : 0;\n_sd_size       = DEFINED(_sd_size) ? _sd_size : _flash_start;\n_sd_ram        = DEFINED(_sd_ram)  ? _sd_ram : 0;\n_fs_size       = DEFINED(_fs_size) ? _fs_size : 64K; \/* TODO: set to 0 if not using the filesystem *\/\n_app_size      = _flash_size - _sd_size - _fs_size;\n_app_start     = _sd_size;\n_fs_start      = _sd_size + _app_size;\n_fs_end        = _fs_start + _fs_size;\n_app_ram_start = _ram_start + _sd_ram;\n_app_ram_size  = _ram_size - _sd_ram;\n_heap_start    = _ebss;\n_heap_end      = _ram_end - _stack_size;\n_heap_size     = _heap_end - _heap_start;\n\nASSERT(_heap_size >= _minimum_heap_size, \"not enough RAM left for heap\")\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_TEXT (rx) : ORIGIN = _app_start,     LENGTH = _app_size     \/* app *\/\n    RAM (xrw)       : ORIGIN = _app_ram_start, LENGTH = _app_ram_size\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a66cd3078d90b9862d32d7960cb1d2db1d6a9943","subject":"Modified to use a full stack + provide _sstack symbol","message":"Modified to use a full stack + provide _sstack symbol\n","repos":"ve3wwg\/teensy3_lib,ve3wwg\/teensy3_lib","old_file":"teensy3\/mk20dx256_sbrk.ld","new_file":"teensy3\/mk20dx256_sbrk.ld","new_contents":"\/* Teensyduino Core Library\n * http:\/\/www.pjrc.com\/teensy\/\n * Copyright (c) 2013 PJRC.COM, LLC.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * 1. The above copyright notice and this permission notice shall be \n * included in all copies or substantial portions of the Software.\n *\n * 2. If the Software is incorporated into a build system that allows \n * selection among a list of target devices, then similar target\n * devices manufactured by PJRC.COM must be included in the list of\n * target devices and selectable in the same manner.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\/\n\nMEMORY\n{\n\tFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\n\tRAM  (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 64K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 16K;\t\/* Just for testing link *\/\n_minimum_heap_size =  16K;\n\n\/* INCLUDE common.ld *\/\n\n\/* Teensyduino Core Library\n * http:\/\/www.pjrc.com\/teensy\/\n * Copyright (c) 2013 PJRC.COM, LLC.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * 1. The above copyright notice and this permission notice shall be \n * included in all copies or substantial portions of the Software.\n *\n * 2. If the Software is incorporated into a build system that allows \n * selection among a list of target devices, then similar target\n * devices manufactured by PJRC.COM must be included in the list of\n * target devices and selectable in the same manner.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\/\n\nSECTIONS\n{\n\t.text : {\n\t\t. = 0;\n\t\tKEEP(*(.vectors))\n\t\t*(.startup*)\n\t\t\/* TODO: does linker detect startup overflow onto flashconfig? *\/\n\t\t. = 0x400;\n\t\tKEEP(*(.flashconfig*))\n\t\t*(.text*)\n\t\t*(.rodata*)\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init))\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\t} > FLASH = 0xFF\n\n\t.ARM.exidx : {\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > FLASH\n\t_etext = .;\n\n\t.usbdescriptortable (NOLOAD) : {\n\t\t\/* . = ORIGIN(RAM); *\/\n\t\t. = ALIGN(512);\n\t\t*(.usbdescriptortable*)\n\t} > RAM\n\n\t.dmabuffers (NOLOAD) : {\n\t\t. = ALIGN(4);\n\t\t*(.dmabuffers*)\n\t} > RAM\n\n\t.usbbuffers (NOLOAD) : {\n\t\t. = ALIGN(4);\n\t\t*(.usbbuffers*)\n\t} > RAM\n\n\t.data : AT (_etext) {\n\t\t. = ALIGN(4);\n\t\t_sdata = .; \n\t\t*(.data*)\n\t\t. = ALIGN(4);\n\t\t_edata = .; \n\t} > RAM\n\n\t\/*\n\t * _staticfs is the place in flash where the static filesystem which\n\t * is concatenated to the .hex file will wind up.\n\t *\/\n\t_staticfs = LOADADDR(.data) + SIZEOF(.data);\n\n\t.noinit (NOLOAD) : {\n\t\t*(.noinit*)\n\t} > RAM\n\n\t.bss : {\n\t\t. = ALIGN(4);\n\t\t_sbss = .; \n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t\t__bss_end = .;\n\t} > RAM\n\n\t\/* this is to define the start of the heap, and make sure we have a minimum size *\/\n\t.heap :\n\t{\n\t    . = ALIGN(4);\n\t    _heap_start = .;    \/* define a global symbol at heap start *\/\n\t    end = _heap_start;\t\/* wwg: for sbrk() *\/\n\t    . = . + _minimum_heap_size;\n\t} >RAM\n\n\t\/* this just checks there is enough RAM for the stack *\/\n\t.stack :\n\t{\n\t    . = ALIGN(4);\n            _sstack = .;\n\t    . = . + _minimum_stack_size;\n\t    . = ALIGN(4);\n\t} >RAM\n\n\t_test_estack = ORIGIN(RAM) + LENGTH(RAM);\n\t_estack = ORIGIN(RAM) + 64 * 1024;\n}\n","old_contents":"\/* Teensyduino Core Library\n * http:\/\/www.pjrc.com\/teensy\/\n * Copyright (c) 2013 PJRC.COM, LLC.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * 1. The above copyright notice and this permission notice shall be \n * included in all copies or substantial portions of the Software.\n *\n * 2. If the Software is incorporated into a build system that allows \n * selection among a list of target devices, then similar target\n * devices manufactured by PJRC.COM must be included in the list of\n * target devices and selectable in the same manner.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\/\n\nMEMORY\n{\n\tFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\n\tRAM  (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 64K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* INCLUDE common.ld *\/\n\n\/* Teensyduino Core Library\n * http:\/\/www.pjrc.com\/teensy\/\n * Copyright (c) 2013 PJRC.COM, LLC.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * 1. The above copyright notice and this permission notice shall be \n * included in all copies or substantial portions of the Software.\n *\n * 2. If the Software is incorporated into a build system that allows \n * selection among a list of target devices, then similar target\n * devices manufactured by PJRC.COM must be included in the list of\n * target devices and selectable in the same manner.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\/\n\nSECTIONS\n{\n\t.text : {\n\t\t. = 0;\n\t\tKEEP(*(.vectors))\n\t\t*(.startup*)\n\t\t\/* TODO: does linker detect startup overflow onto flashconfig? *\/\n\t\t. = 0x400;\n\t\tKEEP(*(.flashconfig*))\n\t\t*(.text*)\n\t\t*(.rodata*)\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init))\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\t} > FLASH = 0xFF\n\n\t.ARM.exidx : {\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > FLASH\n\t_etext = .;\n\n\t.usbdescriptortable (NOLOAD) : {\n\t\t\/* . = ORIGIN(RAM); *\/\n\t\t. = ALIGN(512);\n\t\t*(.usbdescriptortable*)\n\t} > RAM\n\n\t.dmabuffers (NOLOAD) : {\n\t\t. = ALIGN(4);\n\t\t*(.dmabuffers*)\n\t} > RAM\n\n\t.usbbuffers (NOLOAD) : {\n\t\t. = ALIGN(4);\n\t\t*(.usbbuffers*)\n\t} > RAM\n\n\t.data : AT (_etext) {\n\t\t. = ALIGN(4);\n\t\t_sdata = .; \n\t\t*(.data*)\n\t\t. = ALIGN(4);\n\t\t_edata = .; \n\t} > RAM\n\n\t\/*\n\t * _staticfs is the place in flash where the static filesystem which\n\t * is concatenated to the .hex file will wind up.\n\t *\/\n\t_staticfs = LOADADDR(.data) + SIZEOF(.data);\n\n\t.noinit (NOLOAD) : {\n\t\t*(.noinit*)\n\t} > RAM\n\n\t.bss : {\n\t\t. = ALIGN(4);\n\t\t_sbss = .; \n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t\t__bss_end = .;\n\t} > RAM\n\n\t\/* this is to define the start of the heap, and make sure we have a minimum size *\/\n\t.heap :\n\t{\n\t    . = ALIGN(4);\n\t    _heap_start = .;    \/* define a global symbol at heap start *\/\n\t    end = _heap_start;\t\/* wwg: for sbrk() *\/\n\t    . = . + _minimum_heap_size;\n\t} >RAM\n\n\t\/* this just checks there is enough RAM for the stack *\/\n\t.stack :\n\t{\n\t    . = ALIGN(4);\n\t    . = . + _minimum_stack_size;\n\t    . = ALIGN(4);\n\t} >RAM\n\n\t_estack = ORIGIN(RAM) + LENGTH(RAM);\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"839131b644392576de97a2679d491d71f7a837c9","subject":"Add placeholder cpuid and secrets sections to the ELF kernel.","message":"Add placeholder cpuid and secrets sections to the ELF kernel.\n","repos":"project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak","old_file":"experimental\/oak_baremetal_app_crosvm\/layout.ld","new_file":"experimental\/oak_baremetal_app_crosvm\/layout.ld","new_contents":"\/*\n * Copyright 2022 The Project Oak Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n*\/\n\nENTRY(_start)\n\nPHDRS\n{\n    ram     PT_LOAD FLAGS(5);\n    cpuid   PT_LOAD FLAGS(1 << 23);\n    secrets PT_LOAD FLAGS(1 << 24);\n}\n\nSECTIONS {\n    .boot 0x200000 : {\n        ram_min = .;\n        *(.boot)\n    } : ram\n\n    data_start = .;\n    text_start = .;\n\n    .text : {\n        *(.text .text.*)\n    } : ram\n\n    text_end = .;\n\n    .rodata : {\n        *(.rodata .rodata.*)\n    } : ram\n\n    .data : {\n        *(.data .data.*)\n    } : ram\n\n    data_end = .;\n\n    .bss : {\n        bss_start = .;\n        *(.bss .bss.*)\n        bss_size = . - bss_start;\n    } : ram\n\n    \/* Stack grows down, so stack_start is the upper address in memory. *\/\n    .stack (NOLOAD) : ALIGN(4K) {\n        . += 512K;\n    } : ram\n    stack_start = .;\n\n    .cpuid (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : cpuid\n\n    .secrets (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : secrets\n}\n","old_contents":"\/*\n * Copyright 2022 The Project Oak Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n*\/\n\nENTRY(_start)\n\nPHDRS\n{\n    ram  PT_LOAD FLAGS(5);\n}\n\nSECTIONS {\n    .boot 0x200000 : {\n        ram_min = .;\n        *(.boot)\n    } : ram\n\n    data_start = .;\n    text_start = .;\n\n    .text : {\n        *(.text .text.*)\n    } : ram\n\n    text_end = .;\n\n    .rodata : {\n        *(.rodata .rodata.*)\n    } : ram\n\n    .data : {\n        *(.data .data.*)\n    } : ram\n\n    data_end = .;\n\n    .bss : {\n        bss_start = .;\n        *(.bss .bss.*)\n        bss_size = . - bss_start;\n    }\n\n    \/* Stack grows down, so stack_start is the upper address in memory. *\/\n    .stack (NOLOAD) : ALIGN(4K) {\n        . += 512K;\n    }\n    stack_start = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"aa2d49ae0c32ef1d11b493163473ddd385250f4a","subject":"Move BSS to SRAM2 to increase heap size on ST475 IOT board","message":"Move BSS to SRAM2 to increase heap size on ST475 IOT board\n","repos":"mbedmicro\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os","old_file":"targets\/TARGET_STM\/TARGET_STM32L4\/TARGET_STM32L475xG\/device\/TOOLCHAIN_GCC_ARM\/STM32L475XX.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32L4\/TARGET_STM32L475xG\/device\/TOOLCHAIN_GCC_ARM\/STM32L475XX.ld","new_contents":"#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 1024k\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\nM_CRASH_DATA_RAM_SIZE = 0x100;\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188\n  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .crash_data_ram :\n    {\n        . = ALIGN(8);\n        __CRASH_DATA_RAM__ = .;\n        __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n        KEEP(*(.keep.crash_data_ram))\n        *(.m_crash_data_ram)     \/* This is a user defined section *\/\n        . += M_CRASH_DATA_RAM_SIZE;\n        . = ALIGN(8);\n        __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > SRAM1\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > SRAM1\n\n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > SRAM2\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .);\n        __HeapLimit = .;\n    } > SRAM1\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \/* Check if data + heap exceeds RAM1 limit *\/\n    ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, \"SRAM1 overflow\")\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SRAM2\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n    \/* Check if stack exceeds RAM2 limit *\/\n    ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, \"SRAM2 overflow\")\n    \/* Check if bss exceeds __StackLimit *\/\n    ASSERT(__bss_end__ <= __StackLimit, \"BSS is too big for RAM2\")\n}\n","old_contents":"#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 1024k\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\nM_CRASH_DATA_RAM_SIZE = 0x100;\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188\n  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .crash_data_ram :\n    {\n        . = ALIGN(8);\n        __CRASH_DATA_RAM__ = .;\n        __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n        KEEP(*(.keep.crash_data_ram))\n        *(.m_crash_data_ram)     \/* This is a user defined section *\/\n        . += M_CRASH_DATA_RAM_SIZE;\n        . = ALIGN(8);\n        __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > SRAM1\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > SRAM1\n\n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > SRAM1\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .);\n        __HeapLimit = .;\n    } > SRAM1\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \/* Check if data + heap exceeds RAM1 limit *\/\n    ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, \"SRAM1 overflow\")\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SRAM2\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n    \/* Check if stack exceeds RAM2 limit *\/\n    ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, \"SRAM2 overflow\")\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"59939f086a06a55fffef202195f61c2fd533a554","subject":"sections.ld _end definition based on _end_noinit","message":"sections.ld _end definition based on _end_noinit","repos":"gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins","old_file":"ilg.gnuarmeclipse.templates.stm\/templates\/ldscripts\/sections.ld","new_file":"ilg.gnuarmeclipse.templates.stm\/templates\/ldscripts\/sections.ld","new_contents":"\/*\n * Default linker script for STM32Fxxx.\n *\/\n\n\/*\n * The '__stack' definition is required by crt0, do not remove it.\n *\/\n__stack = ORIGIN(RAM) + LENGTH(RAM);\n\n_estack = __stack; \t\/* STM specific definition *\/\n\n\/*\n * Default stack sizes.\n * These are used by the startup in order to allocate stacks \n * for the different modes.\n *\/\n\n__Stack_Size = 1024 ;\n\nPROVIDE ( _Stack_Size = __Stack_Size ) ;\n\n__Stack_Init = __stack  - __Stack_Size ;\n\n\/*\"PROVIDE\" allows to easily override these values from an object file or the command line. *\/\nPROVIDE ( _Stack_Init = __Stack_Init ) ;\n\n\/*\n * There will be a link error if there is not this amount of \n * RAM free at the end. \n *\/\n_Minimum_Stack_Size = 0x100 ;\n\n\n\/* \n * The entry point is informative, for debuggers and simulators,\n * since the Cortex-M vector points to it anyway.\n *\/\nENTRY(Reset_Handler)\n\n\n\/* Sections Definitions *\/\n\nSECTIONS\n{\n    \/*\n     * For Cortex-M devices, the beginning of the startup code is stored in\n     * the .isr_vector section, which goes to FLASH \n     *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))     \t\/* Interrupt vectors *\/\n        \n        \/* \n         * This section is here for convenience, to store the\n         * startup code at the beginning of the flash area, hoping that\n         * this will increase the readbility of the listing.\n         *\/\n        *(.after_vectors .after_vectors.*)\t\/* Startup code and ISR *\/\n\n        . = ALIGN(4);\n    } >FLASH\n\n    ._inits :\n    {\n        . = ALIGN(4);\n        \n        \/*\n         * These are the old initialisation sections, intended to contain\n         * naked code, with the prologue\/epilogue added by crti.o\/crtn.o\n         * when linking with startup files. The standalone startup code\n         * currently does not run these, better use the init arrays below.\n         *\/\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The preinit code, i.e. an array of pointers to initialisation \n         * functions to be performed before constructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n        \n        \/*\n         * Used to run the SystemInit() before anything else.\n         *\/\n\t\tKEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))\n        \n        \/* \n         * Used for other platform inits.\n         *\/\n\t\tKEEP(*(.preinit_array_platform .preinit_array_platform.*))\n        \n        \/*\n         * The application inits. If you need to enforce some order in \n         * execution, create new sections, as before.\n         *\/\n\t\tKEEP(*(.preinit_array .preinit_array.*))\n\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The init code, i.e. an array of pointers to static constructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The fini code, i.e. an array of pointers to static destructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n        . = ALIGN(4);\n\n    } >FLASH\n\n    \/*\n     * For some STRx devices, the beginning of the startup code\n     * is stored in the .flashtext section, which goes to FLASH.\n     *\/\n    .flashtext :\n    {\n        . = ALIGN(4);\n        *(.flashtext .flashtext.*)\t\/* Startup code *\/\n        . = ALIGN(4);\n    } >FLASH\n \n    \n    \/*\n     * The program code is stored in the .text section, \n     * which goes to FLASH.\n     *\/\n    .text :\n    {\n        . = ALIGN(4);\n\t    \n        *(.text .text.*)\t\t\t\/* all remaining code *\/\n \n        *(.rodata .rodata.*) \t\t\/* read-only data (constants) *\/\n\n\t\tKEEP(*(.eh_frame*))\n\n        *(.glue_7)\n        *(.glue_7t)\n\n    } >FLASH\n\n\t\/* ARM magic sections *\/\n\t.ARM.extab :\n   \t{\n       *(.ARM.extab* .gnu.linkonce.armextab.*)\n   \t} > FLASH\n   \t\n   \t__exidx_start = .;   \t\n   \t.ARM.exidx :\n   \t{\n       *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n   \t} > FLASH\n   \t__exidx_end = .;\n   \t\n    . = ALIGN(4);\n    _etext = .;\n\n\t\/* \n     * This address is used by the startup code to \n     * initialise the .data section.\n     *\/\n    _sidata = _etext;\n    \n    \/* MEMORY_ARRAY *\/\n    .ROarraySection :\n    {\n     \t*(.ROarraySection .ROarraySection.*)                          \n    } >MEMORY_ARRAY\n     \n\n    \/*\n     * The initialised data section.\n     * The program executes knowing that the data is in the RAM\n     * but the loader puts the initial values in the FLASH (inidata).\n     * It is one task of the startup to copy the initial values from \n     * FLASH to RAM.\n     *\/\n    .data  : AT ( _sidata )\n    {\n\t    . = ALIGN(4);\n\n        \/* This is used by the startup code to initialise the .data section *\/\n        _sdata = . ;        \t\/* STM specific definition *\/\n        __data_start__ = . ;\n\n        *(vtable)\n\n        *(.data .data.*)\n\n\t    . = ALIGN(4);\n\n\t    \/* This is used by the startup code to initialise the .data section *\/\n        _edata = . ;        \t\/* STM specific definition *\/\n        __data_end__ = . ;\n\n    } >RAM\n    \n    \n\n    \/*\n     * The uninitialised data section.\n     *\/\n    .bss :\n    {\n\t    . = ALIGN(4);\n        __bss_start__ = .;     \t\/* standard newlib definition *\/\n        _sbss = .;              \/* STM specific definition *\/\n\n        *(.bss .bss.*)\n        *(COMMON)\n        \n\t    . = ALIGN(4);\n        __bss_end__ = .;        \/* standard newlib definition *\/\n        _ebss = . ;             \/* STM specific definition *\/\n    } >RAM\n    \n    .noinit (NOLOAD):\n    {\n\t    . = ALIGN(4);\n        _noinit = .;\n        \n        *(.noinit .noinit.*) \n        \n         . = ALIGN(4) ;\n        _end_noinit = .;   \n    } > RAM\n    \n    PROVIDE ( end = _end_noinit ); \/* was _ebss *\/\n    PROVIDE ( _end = _end_noinit );\n    \n    \/*\n     * The user stack section.\n     * This is just to check that there is enough RAM left for the User\n     *  mode stack. It should generate an error if it's full.\n     *\/\n    ._usrstack :\n    {\n\t    . = ALIGN(4);\n        _susrstack = . ;\n        \n        . = . + _Minimum_Stack_Size ;\n        \n\t    . = ALIGN(4);\n        _eusrstack = . ;\n    } >RAM\n    \n\t.bss_CCMRAM : ALIGN(4)\n\t{\n\t\t*(.bss.CCMRAM .bss.CCMRAM.*)\n\t} > CCMRAM\n   \n    \/*\n     * The FLASH Bank1.\n     * The C or assembly source must explicitly place the code \n     * or data there using the \"section\" attribute.\n     *\/\n    .b1text :\n    {\n        *(.b1text)                   \/* remaining code *\/\n        *(.b1rodata)                 \/* read-only data (constants) *\/\n        *(.b1rodata.*)\n    } >FLASHB1\n    \n    \/*\n     * The EXTMEM.\n     * The C or assembly source must explicitly place the code or data there\n     * using the \"section\" attribute.\n     *\/\n\n    \/* EXTMEM Bank0 *\/\n    .eb0text :\n    {\n        *(.eb0text)                   \/* remaining code *\/\n        *(.eb0rodata)                 \/* read-only data (constants) *\/\n        *(.eb0rodata.*)\n    } >EXTMEMB0\n    \n    \/* EXTMEM Bank1 *\/\n    .eb1text :\n    {\n        *(.eb1text)                   \/* remaining code *\/\n        *(.eb1rodata)                 \/* read-only data (constants) *\/\n        *(.eb1rodata.*)\n    } >EXTMEMB1\n    \n    \/* EXTMEM Bank2 *\/\n    .eb2text :\n    {\n        *(.eb2text)                   \/* remaining code *\/\n        *(.eb2rodata)                 \/* read-only data (constants) *\/\n        *(.eb2rodata.*)\n    } >EXTMEMB2\n    \n    \/* EXTMEM Bank0 *\/\n    .eb3text :\n    {\n        *(.eb3text)                   \/* remaining code *\/\n        *(.eb3rodata)                 \/* read-only data (constants) *\/\n        *(.eb3rodata.*)\n    } >EXTMEMB3\n   \n\n    \n    \/* After that there are only debugging sections. *\/\n    \n    \/* This removes the debugging information from the standard libraries *\/\n    DISCARD :\n    {\n     libc.a ( * )\n     libm.a ( * )\n     libgcc.a ( * )\n     }\n  \n  \n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n       Symbols in the DWARF debugging sections are relative to the beginning\n       of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }    \n}\n","old_contents":"\/*\n * Default linker script for STM32Fxxx.\n *\/\n\n\/*\n * The '__stack' definition is required by crt0, do not remove it.\n *\/\n__stack = ORIGIN(RAM) + LENGTH(RAM);\n\n_estack = __stack; \t\/* STM specific definition *\/\n\n\/*\n * Default stack sizes.\n * These are used by the startup in order to allocate stacks \n * for the different modes.\n *\/\n\n__Stack_Size = 1024 ;\n\nPROVIDE ( _Stack_Size = __Stack_Size ) ;\n\n__Stack_Init = __stack  - __Stack_Size ;\n\n\/*\"PROVIDE\" allows to easily override these values from an object file or the command line. *\/\nPROVIDE ( _Stack_Init = __Stack_Init ) ;\n\n\/*\n * There will be a link error if there is not this amount of \n * RAM free at the end. \n *\/\n_Minimum_Stack_Size = 0x100 ;\n\n\n\/* \n * The entry point is informative, for debuggers and simulators,\n * since the Cortex-M vector points to it anyway.\n *\/\nENTRY(Reset_Handler)\n\n\n\/* Sections Definitions *\/\n\nSECTIONS\n{\n    \/*\n     * For Cortex-M devices, the beginning of the startup code is stored in\n     * the .isr_vector section, which goes to FLASH \n     *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))     \t\/* Interrupt vectors *\/\n        \n        \/* \n         * This section is here for convenience, to store the\n         * startup code at the beginning of the flash area, hoping that\n         * this will increase the readbility of the listing.\n         *\/\n        *(.after_vectors .after_vectors.*)\t\/* Startup code and ISR *\/\n\n        . = ALIGN(4);\n    } >FLASH\n\n    ._inits :\n    {\n        . = ALIGN(4);\n        \n        \/*\n         * These are the old initialisation sections, intended to contain\n         * naked code, with the prologue\/epilogue added by crti.o\/crtn.o\n         * when linking with startup files. The standalone startup code\n         * currently does not run these, better use the init arrays below.\n         *\/\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The preinit code, i.e. an array of pointers to initialisation \n         * functions to be performed before constructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n        \n        \/*\n         * Used to run the SystemInit() before anything else.\n         *\/\n\t\tKEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))\n        \n        \/* \n         * Used for other platform inits.\n         *\/\n\t\tKEEP(*(.preinit_array_platform .preinit_array_platform.*))\n        \n        \/*\n         * The application inits. If you need to enforce some order in \n         * execution, create new sections, as before.\n         *\/\n\t\tKEEP(*(.preinit_array .preinit_array.*))\n\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The init code, i.e. an array of pointers to static constructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The fini code, i.e. an array of pointers to static destructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n        . = ALIGN(4);\n\n    } >FLASH\n\n    \/*\n     * For some STRx devices, the beginning of the startup code\n     * is stored in the .flashtext section, which goes to FLASH.\n     *\/\n    .flashtext :\n    {\n        . = ALIGN(4);\n        *(.flashtext .flashtext.*)\t\/* Startup code *\/\n        . = ALIGN(4);\n    } >FLASH\n \n    \n    \/*\n     * The program code is stored in the .text section, \n     * which goes to FLASH.\n     *\/\n    .text :\n    {\n        . = ALIGN(4);\n\t    \n        *(.text .text.*)\t\t\t\/* all remaining code *\/\n \n        *(.rodata .rodata.*) \t\t\/* read-only data (constants) *\/\n\n\t\tKEEP(*(.eh_frame*))\n\n        *(.glue_7)\n        *(.glue_7t)\n\n    } >FLASH\n\n\t\/* ARM magic sections *\/\n\t.ARM.extab :\n   \t{\n       *(.ARM.extab* .gnu.linkonce.armextab.*)\n   \t} > FLASH\n   \t\n   \t__exidx_start = .;   \t\n   \t.ARM.exidx :\n   \t{\n       *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n   \t} > FLASH\n   \t__exidx_end = .;\n   \t\n    . = ALIGN(4);\n    _etext = .;\n\n\t\/* \n     * This address is used by the startup code to \n     * initialise the .data section.\n     *\/\n    _sidata = _etext;\n    \n    \/* MEMORY_ARRAY *\/\n    .ROarraySection :\n    {\n     \t*(.ROarraySection .ROarraySection.*)                          \n    } >MEMORY_ARRAY\n     \n\n    \/*\n     * The initialised data section.\n     * The program executes knowing that the data is in the RAM\n     * but the loader puts the initial values in the FLASH (inidata).\n     * It is one task of the startup to copy the initial values from \n     * FLASH to RAM.\n     *\/\n    .data  : AT ( _sidata )\n    {\n\t    . = ALIGN(4);\n\n        \/* This is used by the startup code to initialise the .data section *\/\n        _sdata = . ;        \t\/* STM specific definition *\/\n        __data_start__ = . ;\n\n        *(vtable)\n\n        *(.data .data.*)\n\n\t    . = ALIGN(4);\n\n\t    \/* This is used by the startup code to initialise the .data section *\/\n        _edata = . ;        \t\/* STM specific definition *\/\n        __data_end__ = . ;\n\n    } >RAM\n    \n    \n\n    \/*\n     * The uninitialised data section.\n     *\/\n    .bss :\n    {\n\t    . = ALIGN(4);\n        __bss_start__ = .;     \t\/* standard newlib definition *\/\n        _sbss = .;              \/* STM specific definition *\/\n\n        *(.bss .bss.*)\n        *(COMMON)\n        \n\t    . = ALIGN(4);\n        __bss_end__ = .;        \/* standard newlib definition *\/\n        _ebss = . ;             \/* STM specific definition *\/\n    } >RAM\n    \n    .noinit (NOLOAD):\n    {\n\t    . = ALIGN(4);\n        _noinit = .;\n        \n        *(.noinit .noinit.*) \n        \n         . = ALIGN(4) ;\n        _end_noinit = .;   \n    } > RAM\n    \n    PROVIDE ( end = _end_noinit ); \/* was _ebss *\/\n    PROVIDE ( _end = end );\n    \n    \/*\n     * The user stack section.\n     * This is just to check that there is enough RAM left for the User\n     *  mode stack. It should generate an error if it's full.\n     *\/\n    ._usrstack :\n    {\n\t    . = ALIGN(4);\n        _susrstack = . ;\n        \n        . = . + _Minimum_Stack_Size ;\n        \n\t    . = ALIGN(4);\n        _eusrstack = . ;\n    } >RAM\n    \n\t.bss_CCMRAM : ALIGN(4)\n\t{\n\t\t*(.bss.CCMRAM .bss.CCMRAM.*)\n\t} > CCMRAM\n   \n    \/*\n     * The FLASH Bank1.\n     * The C or assembly source must explicitly place the code \n     * or data there using the \"section\" attribute.\n     *\/\n    .b1text :\n    {\n        *(.b1text)                   \/* remaining code *\/\n        *(.b1rodata)                 \/* read-only data (constants) *\/\n        *(.b1rodata.*)\n    } >FLASHB1\n    \n    \/*\n     * The EXTMEM.\n     * The C or assembly source must explicitly place the code or data there\n     * using the \"section\" attribute.\n     *\/\n\n    \/* EXTMEM Bank0 *\/\n    .eb0text :\n    {\n        *(.eb0text)                   \/* remaining code *\/\n        *(.eb0rodata)                 \/* read-only data (constants) *\/\n        *(.eb0rodata.*)\n    } >EXTMEMB0\n    \n    \/* EXTMEM Bank1 *\/\n    .eb1text :\n    {\n        *(.eb1text)                   \/* remaining code *\/\n        *(.eb1rodata)                 \/* read-only data (constants) *\/\n        *(.eb1rodata.*)\n    } >EXTMEMB1\n    \n    \/* EXTMEM Bank2 *\/\n    .eb2text :\n    {\n        *(.eb2text)                   \/* remaining code *\/\n        *(.eb2rodata)                 \/* read-only data (constants) *\/\n        *(.eb2rodata.*)\n    } >EXTMEMB2\n    \n    \/* EXTMEM Bank0 *\/\n    .eb3text :\n    {\n        *(.eb3text)                   \/* remaining code *\/\n        *(.eb3rodata)                 \/* read-only data (constants) *\/\n        *(.eb3rodata.*)\n    } >EXTMEMB3\n   \n\n    \n    \/* After that there are only debugging sections. *\/\n    \n    \/* This removes the debugging information from the standard libraries *\/\n    DISCARD :\n    {\n     libc.a ( * )\n     libm.a ( * )\n     libgcc.a ( * )\n     }\n  \n  \n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n       Symbols in the DWARF debugging sections are relative to the beginning\n       of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }    \n}\n","returncode":0,"stderr":"","license":"epl-1.0","lang":"Linker Script"}
{"commit":"3a560efa49d797836043b2d0e60b70ac6d9d048d","subject":"Change comment to GCC scripts","message":"Change comment to GCC scripts\n\nChange comment to GCC scripts. All GCC linker scrips for STM32L1 have\nspace for BootRAM defined.\n","repos":"andcor02\/mbed-os,adamgreen\/mbed,infinnovation\/mbed-os,Sweet-Peas\/mbed,cvtsi2sd\/mbed-os,jeremybrodt\/mbed,xcrespo\/mbed,karsev\/mbed-os,monkiineko\/mbed-os,fpiot\/mbed-ats,fpiot\/mbed-ats,mazimkhan\/mbed-os,al177\/mbed,ARM-software\/mbed-beetle,K4zuki\/mbed,masaohamanaka\/mbed,ban4jp\/mbed,pradeep-gr\/mbed-os5-onsemi,jrjang\/mbed,DanKupiniak\/mbed,brstew\/MBED-BUILD,devanlai\/mbed,nRFMesh\/mbed-os,dbestm\/mbed,EmuxEvans\/mbed,masaohamanaka\/mbed,alertby\/mbed,kjbracey-arm\/mbed,hwfwgrp\/mbed,maximmbed\/mbed,Sweet-Peas\/mbed,struempelix\/mbed,Archcady\/mbed-os,nabilbendafi\/mbed,xcrespo\/mbed,xcrespo\/mbed,ban4jp\/mbed,rgrover\/mbed,xcrespo\/mbed,al177\/mbed,infinnovation\/mbed-os,pradeep-gr\/mbed-os5-onsemi,RonEld\/mbed,bikeNomad\/mbed,screamerbg\/mbed,rgrover\/mbed,screamerbg\/mbed,fanghuaqi\/mbed,ban4jp\/mbed,fpiot\/mbed-ats,xcrespo\/mbed,pi19404\/mbed,kl-cruz\/mbed-os,dbestm\/mbed,betzw\/mbed-os,kl-cruz\/mbed-os,bentwire\/mbed,bikeNomad\/mbed,netzimme\/mbed-os,YarivCol\/mbed-os,andcor02\/mbed-os,tung7970\/mbed-os,HeadsUpDisplayInc\/mbed,pedromes\/mbed,jrjang\/mbed,ryankurte\/mbed-os,GustavWi\/mbed,mmorenobarm\/mbed-os,hwfwgrp\/mbed,netzimme\/mbed-os,betzw\/mbed-os,tung7970\/mbed-os-1,bikeNomad\/mbed,Tiryoh\/mbed,andreaslarssonublox\/mbed,DanKupiniak\/mbed,kpurusho\/mbed,karsev\/mbed-os,adustm\/mbed,dbestm\/mbed,pradeep-gr\/mbed-os5-onsemi,fvincenzo\/mbed-os,ryankurte\/mbed-os,pedromes\/mbed,mmorenobarm\/mbed-os,wodji\/mbed,larks\/mbed,betzw\/mbed-os,infinnovation\/mbed-os,Shengliang\/mbed,ryankurte\/mbed-os,Willem23\/mbed,kjbracey-arm\/mbed,jferreir\/mbed,Sweet-Peas\/mbed,monkiineko\/mbed-os,bcostm\/mbed-os,mmorenobarm\/mbed-os,CalSol\/mbed,wodji\/mbed,arostm\/mbed-os,pedromes\/mbed,kl-cruz\/mbed-os,ARM-software\/mbed-beetle,jferreir\/mbed,ARM-software\/mbed-beetle,GustavWi\/mbed,RonEld\/mbed,larks\/mbed,mazimkhan\/mbed-os,ban4jp\/mbed,getopenmono\/mbed,j-greffe\/mbed-os,DanKupiniak\/mbed,svogl\/mbed-os,naves-thiago\/mbed-midi,adamgreen\/mbed,andcor02\/mbed-os,DanKupiniak\/mbed,ban4jp\/mbed,fahhem\/mbed-os,andreaslarssonublox\/mbed,NitinBhaskar\/mbed,NitinBhaskar\/mbed,monkiineko\/mbed-os,JasonHow44\/mbed,HeadsUpDisplayInc\/mbed,Archcady\/mbed-os,maximmbed\/mbed,getopenmono\/mbed,sam-geek\/mbed,tung7970\/mbed-os,bikeNomad\/mbed,RonEld\/mbed,tung7970\/mbed-os,Marcomissyou\/mbed,dbestm\/mbed,adamgreen\/mbed,pbrook\/mbed,bulislaw\/mbed-os,YarivCol\/mbed-os,nabilbendafi\/mbed,larks\/mbed,kjbracey-arm\/mbed,kl-cruz\/mbed-os,jpbrucker\/mbed,brstew\/MBED-BUILD,bcostm\/mbed-os,theotherjimmy\/mbed,mbedmicro\/mbed,jferreir\/mbed,autopulated\/mbed,bikeNomad\/mbed,tung7970\/mbed-os-1,geky\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,arostm\/mbed-os,catiedev\/mbed-os,naves-thiago\/mbed-midi,alertby\/mbed,fanghuaqi\/mbed,mazimkhan\/mbed-os,NXPmicro\/mbed,monkiineko\/mbed-os,theotherjimmy\/mbed,getopenmono\/mbed,Tiryoh\/mbed,bulislaw\/mbed-os,fanghuaqi\/mbed,c1728p9\/mbed-os,svogl\/mbed-os,EmuxEvans\/mbed,CalSol\/mbed,Marcomissyou\/mbed,screamerbg\/mbed,al177\/mbed,tung7970\/mbed-os-1,NXPmicro\/mbed,mnlipp\/mbed,Willem23\/mbed,JasonHow44\/mbed,Timmmm\/mbed,mikaleppanen\/mbed-os,theotherjimmy\/mbed,logost\/mbed,K4zuki\/mbed,wodji\/mbed,geky\/mbed,arostm\/mbed-os,theotherjimmy\/mbed,larks\/mbed,RonEld\/mbed,netzimme\/mbed-os,rosterloh\/mbed,hwfwgrp\/mbed,RonEld\/mbed,nvlsianpu\/mbed,netzimme\/mbed-os,mmorenobarm\/mbed-os,rosterloh\/mbed,svastm\/mbed,adustm\/mbed,mikaleppanen\/mbed-os,monkiineko\/mbed-os,jamesadevine\/mbed,mazimkhan\/mbed-os,Timmmm\/mbed,JasonHow44\/mbed,mazimkhan\/mbed-os,bentwire\/mbed,bentwire\/mbed,getopenmono\/mbed,autopulated\/mbed,adustm\/mbed,getopenmono\/mbed,NitinBhaskar\/mbed,naves-thiago\/mbed-midi,NitinBhaskar\/mbed,autopulated\/mbed,autopulated\/mbed,pedromes\/mbed,mmorenobarm\/mbed-os,Sweet-Peas\/mbed,struempelix\/mbed,Shengliang\/mbed,Willem23\/mbed,nvlsianpu\/mbed,catiedev\/mbed-os,NXPmicro\/mbed,svastm\/mbed,svogl\/mbed-os,hwfwgrp\/mbed,GustavWi\/mbed,rgrover\/mbed,bulislaw\/mbed-os,YarivCol\/mbed-os,jrjang\/mbed,pedromes\/mbed,jamesadevine\/mbed,jferreir\/mbed,jamesadevine\/mbed,bulislaw\/mbed-os,JasonHow44\/mbed,logost\/mbed,autopulated\/mbed,fvincenzo\/mbed-os,andreaslarssonublox\/mbed,YarivCol\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,mnlipp\/mbed,alertby\/mbed,pi19404\/mbed,jrjang\/mbed,pi19404\/mbed,maximmbed\/mbed,logost\/mbed,Marcomissyou\/mbed,bcostm\/mbed-os,screamerbg\/mbed,betzw\/mbed-os,struempelix\/mbed,wodji\/mbed,screamerbg\/mbed,CalSol\/mbed,maximmbed\/mbed,j-greffe\/mbed-os,fanghuaqi\/mbed,alertby\/mbed,nvlsianpu\/mbed,j-greffe\/mbed-os,fahhem\/mbed-os,hwfwgrp\/mbed,al177\/mbed,Sweet-Peas\/mbed,bulislaw\/mbed-os,cvtsi2sd\/mbed-os,andcor02\/mbed-os,fahhem\/mbed-os,alertby\/mbed,struempelix\/mbed,cvtsi2sd\/mbed-os,andcor02\/mbed-os,ARM-software\/mbed-beetle,rosterloh\/mbed,svastm\/mbed,nabilbendafi\/mbed,K4zuki\/mbed,fvincenzo\/mbed-os,mnlipp\/mbed,screamerbg\/mbed,bentwire\/mbed,c1728p9\/mbed-os,mnlipp\/mbed,c1728p9\/mbed-os,jpbrucker\/mbed,fvincenzo\/mbed-os,tung7970\/mbed-os,naves-thiago\/mbed-midi,bentwire\/mbed,pradeep-gr\/mbed-os5-onsemi,rosterloh\/mbed,EmuxEvans\/mbed,wodji\/mbed,karsev\/mbed-os,devanlai\/mbed,pbrook\/mbed,fpiot\/mbed-ats,logost\/mbed,c1728p9\/mbed-os,betzw\/mbed-os,Tiryoh\/mbed,HeadsUpDisplayInc\/mbed,jeremybrodt\/mbed,fanghuaqi\/mbed,pi19404\/mbed,Timmmm\/mbed,infinnovation\/mbed-os,kl-cruz\/mbed-os,logost\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,j-greffe\/mbed-os,fahhem\/mbed-os,netzimme\/mbed-os,pradeep-gr\/mbed-os5-onsemi,tung7970\/mbed-os,FranklyDev\/mbed,al177\/mbed,nRFMesh\/mbed-os,masaohamanaka\/mbed,andreaslarssonublox\/mbed,mikaleppanen\/mbed-os,nRFMesh\/mbed-os,monkiineko\/mbed-os,bcostm\/mbed-os,CalSol\/mbed,kjbracey-arm\/mbed,YarivCol\/mbed-os,JasonHow44\/mbed,EmuxEvans\/mbed,HeadsUpDisplayInc\/mbed,j-greffe\/mbed-os,K4zuki\/mbed,devanlai\/mbed,jamesadevine\/mbed,nRFMesh\/mbed-os,struempelix\/mbed,kpurusho\/mbed,j-greffe\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,arostm\/mbed-os,nabilbendafi\/mbed,brstew\/MBED-BUILD,fvincenzo\/mbed-os,JasonHow44\/mbed,fahhem\/mbed-os,bcostm\/mbed-os,jamesadevine\/mbed,jamesadevine\/mbed,geky\/mbed,Willem23\/mbed,jeremybrodt\/mbed,fahhem\/mbed-os,adamgreen\/mbed,brstew\/MBED-BUILD,kpurusho\/mbed,getopenmono\/mbed,bentwire\/mbed,adamgreen\/mbed,logost\/mbed,kl-cruz\/mbed-os,jrjang\/mbed,devanlai\/mbed,bulislaw\/mbed-os,EmuxEvans\/mbed,jrjang\/mbed,infinnovation\/mbed-os,masaohamanaka\/mbed,NXPmicro\/mbed,FranklyDev\/mbed,EmuxEvans\/mbed,GustavWi\/mbed,sam-geek\/mbed,K4zuki\/mbed,svogl\/mbed-os,pi19404\/mbed,infinnovation\/mbed-os,karsev\/mbed-os,catiedev\/mbed-os,pbrook\/mbed,nRFMesh\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,bcostm\/mbed-os,Shengliang\/mbed,jferreir\/mbed,Shengliang\/mbed,jpbrucker\/mbed,sam-geek\/mbed,Tiryoh\/mbed,kpurusho\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,Archcady\/mbed-os,Shengliang\/mbed,Archcady\/mbed-os,jeremybrodt\/mbed,theotherjimmy\/mbed,jferreir\/mbed,c1728p9\/mbed-os,Timmmm\/mbed,mnlipp\/mbed,pradeep-gr\/mbed-os5-onsemi,RonEld\/mbed,nvlsianpu\/mbed,wodji\/mbed,CalSol\/mbed,karsev\/mbed-os,pbrook\/mbed,pbrook\/mbed,mbedmicro\/mbed,nabilbendafi\/mbed,karsev\/mbed-os,ban4jp\/mbed,Archcady\/mbed-os,FranklyDev\/mbed,rosterloh\/mbed,tung7970\/mbed-os-1,al177\/mbed,catiedev\/mbed-os,svastm\/mbed,Marcomissyou\/mbed,jpbrucker\/mbed,dbestm\/mbed,mazimkhan\/mbed-os,mikaleppanen\/mbed-os,naves-thiago\/mbed-midi,ryankurte\/mbed-os,sam-geek\/mbed,nvlsianpu\/mbed,xcrespo\/mbed,rgrover\/mbed,kpurusho\/mbed,kpurusho\/mbed,catiedev\/mbed-os,adustm\/mbed,ryankurte\/mbed-os,geky\/mbed,CalSol\/mbed,larks\/mbed,catiedev\/mbed-os,adustm\/mbed,FranklyDev\/mbed,pi19404\/mbed,NXPmicro\/mbed,mikaleppanen\/mbed-os,adamgreen\/mbed,jpbrucker\/mbed,c1728p9\/mbed-os,tung7970\/mbed-os-1,nRFMesh\/mbed-os,mbedmicro\/mbed,maximmbed\/mbed,rosterloh\/mbed,FranklyDev\/mbed,svastm\/mbed,NXPmicro\/mbed,dbestm\/mbed,fpiot\/mbed-ats,maximmbed\/mbed,sam-geek\/mbed,cvtsi2sd\/mbed-os,devanlai\/mbed,cvtsi2sd\/mbed-os,andcor02\/mbed-os,nabilbendafi\/mbed,andreaslarssonublox\/mbed,Sweet-Peas\/mbed,brstew\/MBED-BUILD,GustavWi\/mbed,mnlipp\/mbed,Marcomissyou\/mbed,brstew\/MBED-BUILD,arostm\/mbed-os,K4zuki\/mbed,geky\/mbed,pedromes\/mbed,Tiryoh\/mbed,autopulated\/mbed,pbrook\/mbed,YarivCol\/mbed-os,Shengliang\/mbed,NitinBhaskar\/mbed,larks\/mbed,naves-thiago\/mbed-midi,alertby\/mbed,Willem23\/mbed,masaohamanaka\/mbed,Timmmm\/mbed,nvlsianpu\/mbed,rgrover\/mbed,ryankurte\/mbed-os,mmorenobarm\/mbed-os,netzimme\/mbed-os,mikaleppanen\/mbed-os,Marcomissyou\/mbed,jpbrucker\/mbed,Archcady\/mbed-os,HeadsUpDisplayInc\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,masaohamanaka\/mbed,fpiot\/mbed-ats,theotherjimmy\/mbed,svogl\/mbed-os,Tiryoh\/mbed,svogl\/mbed-os,arostm\/mbed-os,hwfwgrp\/mbed,cvtsi2sd\/mbed-os,HeadsUpDisplayInc\/mbed,adustm\/mbed,Timmmm\/mbed,jeremybrodt\/mbed,betzw\/mbed-os,struempelix\/mbed,devanlai\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_STM32L1\/TARGET_NUCLEO_L152RE\/TOOLCHAIN_GCC_ARM\/STM32L152XE.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_STM32L1\/TARGET_NUCLEO_L152RE\/TOOLCHAIN_GCC_ARM\/STM32L152XE.ld","new_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  \/* 512KB FLASH, 80KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292\n   * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138\n   *\/\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512k\n  RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x14000-0x13C\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  \/* 512KB FLASH, 80KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292\n   * bytes (0x124) in RAM. But all GCC compilers seem to require BootRAM @0x138\n   *\/\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512k\n  RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x14000-0x13C\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9c70fb1e18e7931867b1e8928c878f33057e493e","subject":"Revert \"linker: common-rom: tweak section naming to feet all linkers\"","message":"Revert \"linker: common-rom: tweak section naming to feet all linkers\"\n\nThis reverts commit fd5fa203b6543670b13d42f7b16f89e4e44bf035.\n\nSigned-off-by: Peter Bigot <a4112a160b558d5427af084318038e19a95979ee@nordicsemi.no>\n","repos":"galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr","old_file":"include\/linker\/common-rom.ld","new_file":"include\/linker\/common-rom.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\tSECTION_PROLOGUE(initlevel,,)\n\t{\n\t\t\/*\n\t\t * link in initialization objects for all objects that are\n\t\t * automatically initialized by the kernel; the objects are\n\t\t * sorted in the order they will be initialized (i.e. ordered\n\t\t * by level, sorted by priority within a level)\n\t\t *\/\n\t\t__init_start = .;\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_1)\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_2)\n\t\tCREATE_OBJ_LEVEL(init, POST_KERNEL)\n\t\tCREATE_OBJ_LEVEL(init, APPLICATION)\n\t\tCREATE_OBJ_LEVEL(init, SMP)\n\t\t__init_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && !defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_NAME)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_PROLOGUE(initlevel_error,,)\n\t{\n\t\tKEEP(*(SORT(.init_[_A-Z0-9]*)))\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\tSECTION_DATA_PROLOGUE(device_handles,,)\n\t{\n\t\t__device_handles_start = .;\n#ifdef LINKER_PASS2\n\t\tKEEP(*(SORT(.__device_handles_pass2)));\n#else \/* LINKER_PASS2 *\/\n\t\tKEEP(*(SORT(.__device_handles_pass1)));\n#endif \/* LINKER_PASS2 *\/\n\t\t__device_handles_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on word\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n#ifdef CONFIG_64BIT\n\t\t. = ALIGN(8);\n\t\t__CTOR_LIST__ = .;\n\t\tQUAD((__CTOR_END__ - __CTOR_LIST__) \/ 8 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tQUAD(0)\n\t\t__CTOR_END__ = .;\n#else\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array,,)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n#ifdef CONFIG_USERSPACE\n\t\/* Build-time assignment of permissions to kernel objects to\n\t * threads declared with K_THREAD_DEFINE()\n\t *\/\n\tZ_ITERABLE_SECTION_ROM(z_object_assignment, 4)\n#endif\n\n\tSECTION_DATA_PROLOGUE(app_shmem_regions,,)\n\t{\n\t\t__app_shmem_regions_start = .;\n\t\tKEEP(*(SORT(.app_regions.*)));\n\t\t__app_shmem_regions_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SOCKETS)\n\tZ_ITERABLE_SECTION_ROM(net_socket_register, 4)\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n\tZ_ITERABLE_SECTION_ROM(ppp_protocol_handler, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_fixed_chan, 4)\n\n#if defined(CONFIG_BT_BREDR)\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_br_fixed_chan, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_gatt_service_static, 4)\n\n#if defined(CONFIG_BT_MESH)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_subnet_cb, 4)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_app_key_cb, 4)\n\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_hb_cb, 4)\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_friend_cb, 4)\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_lpn_cb, 4)\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n\tZ_ITERABLE_SECTION_ROM(ec_host_cmd_handler, 4)\n#endif\n\n#if defined(CONFIG_SETTINGS)\n\tZ_ITERABLE_SECTION_ROM(settings_handler_static, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(k_p4wq_initparam, 4)\n\n#if defined(CONFIG_EMUL)\n\tSECTION_DATA_PROLOGUE(emulators_section,,)\n\t{\n\t\t__emul_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".emulators\")));\n\t\t__emul_list_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_EMUL *\/\n\n#if defined(CONFIG_DNS_SD)\n\tZ_ITERABLE_SECTION_ROM(dns_sd_rec, 4)\n#endif\n\n#if defined(CONFIG_PCIE)\n\tSECTION_DATA_PROLOGUE(irq_alloc,,)\n\t{\n\t\t__irq_alloc_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._irq_alloc*\")));\n\t\t__irq_alloc_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_PCIE *\/\n\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__log_const_start = .;\n\t\tKEEP(*(SORT(.log_const_*)));\n\t\t__log_const_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_backends_sections,,)\n\t{\n\t\t__log_backends_start = .;\n\t\tKEEP(*(\"._log_backend.*\"));\n\t\t__log_backends_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(shell, 4)\n\n\tSECTION_DATA_PROLOGUE(shell_root_cmds_sections,,)\n\t{\n\t\t__shell_root_cmds_start = .;\n\t\tKEEP(*(SORT(.shell_root_cmd_*)));\n\t\t__shell_root_cmds_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(font_entry_sections,,)\n\t{\n\t\t__font_entry_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._cfb_font.*\")))\n\t\t__font_entry_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(tracing_backend, 4)\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\tSECTION_PROLOGUE(initlevel,,)\n\t{\n\t\t\/*\n\t\t * link in initialization objects for all objects that are\n\t\t * automatically initialized by the kernel; the objects are\n\t\t * sorted in the order they will be initialized (i.e. ordered\n\t\t * by level, sorted by priority within a level)\n\t\t *\/\n\t\t__init_start = .;\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_1)\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_2)\n\t\tCREATE_OBJ_LEVEL(init, POST_KERNEL)\n\t\tCREATE_OBJ_LEVEL(init, APPLICATION)\n\t\tCREATE_OBJ_LEVEL(init, SMP)\n\t\t__init_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && !defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_NAME)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_PROLOGUE(initlevel_error,,)\n\t{\n\t\tKEEP(*(SORT(.init_[_A-Z0-9]*)))\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\tSECTION_DATA_PROLOGUE(device_handles,,)\n\t{\n\t\t__device_handles_start = .;\n#ifdef LINKER_PASS2\n\t\tKEEP(*(SORT(.__device_handles_pass2*)));\n#else \/* LINKER_PASS2 *\/\n\t\tKEEP(*(SORT(.__device_handles_pass1*)));\n#endif \/* LINKER_PASS2 *\/\n\t\t__device_handles_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on word\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n#ifdef CONFIG_64BIT\n\t\t. = ALIGN(8);\n\t\t__CTOR_LIST__ = .;\n\t\tQUAD((__CTOR_END__ - __CTOR_LIST__) \/ 8 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tQUAD(0)\n\t\t__CTOR_END__ = .;\n#else\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array,,)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n#ifdef CONFIG_USERSPACE\n\t\/* Build-time assignment of permissions to kernel objects to\n\t * threads declared with K_THREAD_DEFINE()\n\t *\/\n\tZ_ITERABLE_SECTION_ROM(z_object_assignment, 4)\n#endif\n\n\tSECTION_DATA_PROLOGUE(app_shmem_regions,,)\n\t{\n\t\t__app_shmem_regions_start = .;\n\t\tKEEP(*(SORT(.app_regions.*)));\n\t\t__app_shmem_regions_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SOCKETS)\n\tZ_ITERABLE_SECTION_ROM(net_socket_register, 4)\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n\tZ_ITERABLE_SECTION_ROM(ppp_protocol_handler, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_fixed_chan, 4)\n\n#if defined(CONFIG_BT_BREDR)\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_br_fixed_chan, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_gatt_service_static, 4)\n\n#if defined(CONFIG_BT_MESH)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_subnet_cb, 4)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_app_key_cb, 4)\n\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_hb_cb, 4)\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_friend_cb, 4)\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_lpn_cb, 4)\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n\tZ_ITERABLE_SECTION_ROM(ec_host_cmd_handler, 4)\n#endif\n\n#if defined(CONFIG_SETTINGS)\n\tZ_ITERABLE_SECTION_ROM(settings_handler_static, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(k_p4wq_initparam, 4)\n\n#if defined(CONFIG_EMUL)\n\tSECTION_DATA_PROLOGUE(emulators_section,,)\n\t{\n\t\t__emul_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".emulators\")));\n\t\t__emul_list_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_EMUL *\/\n\n#if defined(CONFIG_DNS_SD)\n\tZ_ITERABLE_SECTION_ROM(dns_sd_rec, 4)\n#endif\n\n#if defined(CONFIG_PCIE)\n\tSECTION_DATA_PROLOGUE(irq_alloc,,)\n\t{\n\t\t__irq_alloc_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._irq_alloc*\")));\n\t\t__irq_alloc_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_PCIE *\/\n\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__log_const_start = .;\n\t\tKEEP(*(SORT(.log_const_*)));\n\t\t__log_const_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_backends_sections,,)\n\t{\n\t\t__log_backends_start = .;\n\t\tKEEP(*(\"._log_backend.*\"));\n\t\t__log_backends_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(shell, 4)\n\n\tSECTION_DATA_PROLOGUE(shell_root_cmds_sections,,)\n\t{\n\t\t__shell_root_cmds_start = .;\n\t\tKEEP(*(SORT(.shell_root_cmd_*)));\n\t\t__shell_root_cmds_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(font_entry_sections,,)\n\t{\n\t\t__font_entry_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._cfb_font.*\")))\n\t\t__font_entry_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(tracing_backend, 4)\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"52a4bace6812e1ddfc4b468ab0781a16774d53c2","subject":"bsp:ls2k:uniform coding style, use space for indentation","message":"bsp:ls2k:uniform coding style, use space for indentation\n\nuse space instead of table for indentation in ls2k_ram.lds\n","repos":"nongxiaoming\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread","old_file":"bsp\/ls2kdev\/ls2k_ram.lds","new_file":"bsp\/ls2kdev\/ls2k_ram.lds","new_contents":"\/*\n * Copyright (c) 2006-2020, RT-Thread Development Team\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Change Logs:\n * Date           Author       Notes\n * 2020-04-05     bigmagic  Initial version\n *\/\n\nOUTPUT_ARCH(mips)\nGROUP(-lgcc -lc)\n\nENTRY(_start)\nSECTIONS\n{\n    . = 0xffffffff82000000 ;\n    .text :\n    {\n        __ebase_entry = .;\n        KEEP(*(.exc_vectors))\n        __ebase_end = .;\n        start = .;\n        *(.start);\n            . = ALIGN(4);\t \n            *(.text)\n            *(.text.*)\n            *(.rodata)\n            *(.rodata.*)\n            *(.rodata1)\n            *(.rodata1.*)\n\n\n            \/* section information for finsh shell *\/\n            . = ALIGN(4);\n            __fsymtab_start = .;\n            KEEP(*(FSymTab))\n            __fsymtab_end = .;\n            . = ALIGN(4);\n            __vsymtab_start = .;\n            KEEP(*(VSymTab))\n            __vsymtab_end = .;\n            . = ALIGN(4);\n\n            . = ALIGN(4);\n            __rt_init_start = .;\n            KEEP(*(SORT(.rti_fn*)))\n            __rt_init_end = .;\n            . = ALIGN(4);\n\n            . = ALIGN(4);\n        __rt_utest_tc_tab_start = .;\n        KEEP(*(UtestTcTab))\n        __rt_utest_tc_tab_end = .;\n        . = ALIGN(4);\n    }\n    \n    .eh_frame_hdr : \n    { \n         *(.eh_frame_hdr) \n         *(.eh_frame_entry)\n    }\n    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n\n    . = ALIGN(4);\n    .data : \n    {\n         *(.data)\n         *(.data.*)\n        \n         *(.data1)\n         *(.data1.*)\n\n         . = ALIGN(8);\n         _gp = ABSOLUTE(.);     \/* Base of small data *\/\n         \n         *(.sdata)\n         *(.sdata.*)\n    }\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    }\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    }\n\n    .stack :\n    {\n        . = ALIGN(8);\n        _system_stack_start = .;\n        . = . + 0x1000;\n        _system_stack = .;\n    }\n\n    .sbss : \n    {\n        __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.dynsbss)\n        *(.scommon)\n    }\n\n    .bss :\n    {\n        *(.bss)\n        *(.bss.*)\n        *(.dynbss)\n        *(COMMON)\n        __bss_end = .;\n    }\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * Copyright (c) 2006-2020, RT-Thread Development Team\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Change Logs:\n * Date           Author       Notes\n * 2020-04-05     bigmagic  Initial version\n *\/\n\nOUTPUT_ARCH(mips)\nGROUP(-lgcc -lc)\n\nENTRY(_start)\nSECTIONS\n{\n    . = 0xffffffff82000000 ;\n    .text :\n    {\n        __ebase_entry = .;\n        KEEP(*(.exc_vectors))\n        __ebase_end = .;\n        start = .;\n        *(.start);\n            . = ALIGN(4);\t \n            *(.text)\n            *(.text.*)\n            *(.rodata)\n            *(.rodata.*)\n            *(.rodata1)\n            *(.rodata1.*)\n\n\n            \/* section information for finsh shell *\/\n            . = ALIGN(4);\n            __fsymtab_start = .;\n            KEEP(*(FSymTab))\n            __fsymtab_end = .;\n            . = ALIGN(4);\n            __vsymtab_start = .;\n            KEEP(*(VSymTab))\n            __vsymtab_end = .;\n            . = ALIGN(4);\n\n            . = ALIGN(4);\n            __rt_init_start = .;\n            KEEP(*(SORT(.rti_fn*)))\n            __rt_init_end = .;\n            . = ALIGN(4);\n\n            . = ALIGN(4);\n        __rt_utest_tc_tab_start = .;\n        KEEP(*(UtestTcTab))\n        __rt_utest_tc_tab_end = .;\n        . = ALIGN(4);\n    }\n    \n    .eh_frame_hdr : \n    { \n         *(.eh_frame_hdr) \n         *(.eh_frame_entry)\n    }\n    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n\n    . = ALIGN(4);\n    .data : \n    {\n         *(.data)\n         *(.data.*)\n        \n         *(.data1)\n         *(.data1.*)\n\n         . = ALIGN(8);\n         _gp = ABSOLUTE(.);     \/* Base of small data *\/\n         \n         *(.sdata)\n         *(.sdata.*)\n    }\n\n    . = ALIGN(4);\n\t.ctors :\n\t{\n\t\tPROVIDE(__ctors_start__ = .);\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*(.ctors))\n\t\tPROVIDE(__ctors_end__ = .);\n\t}\n\n\t.dtors :\n\t{\n\t\tPROVIDE(__dtors_start__ = .);\n\t\tKEEP(*(SORT(.dtors.*)))\n\t\tKEEP(*(.dtors))\n\t\tPROVIDE(__dtors_end__ = .);\n\t}\n\n\n\n    .stack :\n    {\n        . = ALIGN(8);\n        _system_stack_start = .;\n        . = . + 0x1000;\n        _system_stack = .;\n    }\n\n    .sbss : \n    {\n        __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.dynsbss)\n        *(.scommon)\n    }\n\n    .bss :\n    {\n        *(.bss)\n        *(.bss.*)\n        *(.dynbss)\n        *(COMMON)\n        __bss_end = .;\n    }\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6a5d2c9f8abcd56578c764ed66e61f32a9a79a54","subject":"Fix NVIC base address","message":"Fix NVIC base address\n\nSomehow this change was lost in the commotion\n","repos":"richo\/zinc,ryankurte\/zinc,phil-opp\/zinc,darayus\/zinc,posborne\/zinc,tempbottle\/zinc,mcoffin\/zinc,richo\/zinc,hackndev\/zinc,mcoffin\/zinc,dirvine\/zinc,ntwyman\/zinc,hackndev\/zinc,ntwyman\/zinc,troplin\/zinc,mcoffin\/zinc,ryankurte\/zinc,hackndev\/zinc,placrosse\/zinc,dirvine\/zinc,gapry\/zinc,dirvine\/zinc,posborne\/zinc,tempbottle\/zinc,phil-opp\/zinc,hugwijst\/zinc,troplin\/zinc,farcaller\/zinc,ntwyman\/zinc,placrosse\/zinc,dirvine\/zinc,gapry\/zinc,farcaller\/zinc,troplin\/zinc,mcoffin\/zinc,phil-opp\/zinc,farcaller\/zinc,hugwijst\/zinc,phil-opp\/zinc,tempbottle\/zinc,tempbottle\/zinc,ryankurte\/zinc,posborne\/zinc,phil-opp\/zinc,placrosse\/zinc,posborne\/zinc,darayus\/zinc,posborne\/zinc,farcaller\/zinc,troplin\/zinc,ntwyman\/zinc,0xc0170\/zinc,dirvine\/zinc,placrosse\/zinc,hackndev\/zinc,placrosse\/zinc,ryankurte\/zinc,richo\/zinc,troplin\/zinc,ntwyman\/zinc,hackndev\/zinc,aethaniel\/zinc,farcaller\/zinc,0xc0170\/zinc,tempbottle\/zinc,aethaniel\/zinc,mcoffin\/zinc,richo\/zinc,ryankurte\/zinc,richo\/zinc","old_file":"src\/zinc\/hal\/cortex_m3\/armmem.ld","new_file":"src\/zinc\/hal\/cortex_m3\/armmem.ld","new_contents":"\/* Zinc, the bare metal stack for rust.\n\/\/ Copyright 2014 Ben Harris <mail@bharr.is>\n\/\/\n\/\/ Licensed under the Apache License, Version 2.0 (the \"License\");\n\/\/ you may not use this file except in compliance with the License.\n\/\/ You may obtain a copy of the License at\n\/\/\n\/\/     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\/\/\n\/\/ Unless required by applicable law or agreed to in writing, software\n\/\/ distributed under the License is distributed on an \"AS IS\" BASIS,\n\/\/ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n\/\/ See the License for the specific language governing permissions and\n\/\/ limitations under the License.\n*\/\n\nPROVIDE(isr_nmi         = isr_default_fault);\nPROVIDE(isr_hardfault   = isr_default_fault);\nPROVIDE(isr_mmfault     = isr_default_fault);\nPROVIDE(isr_busfault    = isr_default_fault);\nPROVIDE(isr_usagefault  = isr_default_fault);\nPROVIDE(isr_svcall      = isr_default_fault);\nPROVIDE(isr_pendsv      = isr_default_fault);\nPROVIDE(isr_systick     = isr_default_fault);\n\narmmem_SYSTICK    = 0xE000E010;\n\narmmem_NVIC       = 0xE000E000;\n\narmmem_SCB_ACTLR  = 0xE000E008;\narmmem_SCB        = 0xE000ED00;\n\narmmem_MPU        = 0xE000ED90;\n","old_contents":"\/* Zinc, the bare metal stack for rust.\n\/\/ Copyright 2014 Ben Harris <mail@bharr.is>\n\/\/\n\/\/ Licensed under the Apache License, Version 2.0 (the \"License\");\n\/\/ you may not use this file except in compliance with the License.\n\/\/ You may obtain a copy of the License at\n\/\/\n\/\/     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\/\/\n\/\/ Unless required by applicable law or agreed to in writing, software\n\/\/ distributed under the License is distributed on an \"AS IS\" BASIS,\n\/\/ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n\/\/ See the License for the specific language governing permissions and\n\/\/ limitations under the License.\n*\/\n\nPROVIDE(isr_nmi         = isr_default_fault);\nPROVIDE(isr_hardfault   = isr_default_fault);\nPROVIDE(isr_mmfault     = isr_default_fault);\nPROVIDE(isr_busfault    = isr_default_fault);\nPROVIDE(isr_usagefault  = isr_default_fault);\nPROVIDE(isr_svcall      = isr_default_fault);\nPROVIDE(isr_pendsv      = isr_default_fault);\nPROVIDE(isr_systick     = isr_default_fault);\n\narmmem_SYSTICK    = 0xE000E010;\n\narmmem_NVIC       = 0xE000E100;\n\narmmem_SCB_ACTLR  = 0xE000E008;\narmmem_SCB        = 0xE000ED00;\n\narmmem_MPU        = 0xE000ED90;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"11431193dbd664e96a2ce2e3a8f5ec7c705889be","subject":"Use question mark instead of asterisk in path for startup.S.o.","message":"Use question mark instead of asterisk in path for startup.S.o.\n\nJussi use asterisk but he suggested question mark is marginally better\nas it would match less possibilities. Long term the use of the '@' in\nmeson needs to be fixed see [issue #24](https:\/\/github.com\/mesonbuild\/meson\/issues\/294)\n","repos":"winksaville\/baremetal-hi,winksaville\/baremetal-hi","old_file":"link.meson.ld","new_file":"link.meson.ld","new_contents":"\nENTRY(_Reset)\nSECTIONS\n{\n  . = 0x10000;\n  \/* TODO: fix meson naming scheme so there its something other\n   * than testit@exe as the linker script doesn't like '@' *\/\n  .startup  . : { testit?exe\/startup.S.o(.text) }\n  .text : { *(.text) }\n  .data : { *(.data) }\n  .bss : { *(.bss COMMON) }\n  . = ALIGN(8);\n  . = . + 0x1000; \/* 4kB stack *\/\n  stack_top = .;\n}\n","old_contents":"ENTRY(_Reset)\nSECTIONS\n{\n  . = 0x10000;\n  .startup  . : { testit*exe\/startup.S.o(.text) }\n  .text : { *(.text) }\n  .data : { *(.data) }\n  .bss : { *(.bss COMMON) }\n  . = ALIGN(8);\n  . = . + 0x1000; \/* 4kB stack *\/\n  stack_top = .;\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"271f99a38daa5420895b97b44fe17d7e967ff70a","subject":" Updating linker script with final bootloader information","message":" Updating linker script with final bootloader information\n","repos":"MickMad\/ArduinoCore-samd,MickMad\/ArduinoCore-samd","old_file":"variants\/arduino_zero\/linker_scripts\/gcc\/flash_with_bootloader.ld","new_file":"variants\/arduino_zero\/linker_scripts\/gcc\/flash_with_bootloader.ld","new_contents":"\/* Linker script to configure memory regions.\n * Need modifying for a specific board.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000+0x2000, LENGTH = 0x00040000-0x2000\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions.\n * Need modifying for a specific board.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"03639216dbccafe798fb4a5cd5517dd11950f1fd","subject":"k20: Fallout from #285","message":"k20: Fallout from #285\n","repos":"richo\/zinc,placrosse\/zinc,ntwyman\/zinc,tempbottle\/zinc,richo\/zinc,phil-opp\/zinc,dirvine\/zinc,phil-opp\/zinc,farcaller\/zinc,dirvine\/zinc,placrosse\/zinc,posborne\/zinc,posborne\/zinc,mcoffin\/zinc,posborne\/zinc,troplin\/zinc,richo\/zinc,ryankurte\/zinc,ntwyman\/zinc,ryankurte\/zinc,hackndev\/zinc,farcaller\/zinc,ntwyman\/zinc,ntwyman\/zinc,phil-opp\/zinc,placrosse\/zinc,mcoffin\/zinc,richo\/zinc,tempbottle\/zinc,farcaller\/zinc,hackndev\/zinc,tempbottle\/zinc,dirvine\/zinc,mcoffin\/zinc,ryankurte\/zinc,tempbottle\/zinc,hackndev\/zinc,dirvine\/zinc,posborne\/zinc,troplin\/zinc,placrosse\/zinc,richo\/zinc,phil-opp\/zinc,farcaller\/zinc,mcoffin\/zinc,phil-opp\/zinc,dirvine\/zinc,posborne\/zinc,tempbottle\/zinc,ntwyman\/zinc,ryankurte\/zinc,hackndev\/zinc,troplin\/zinc,ryankurte\/zinc,placrosse\/zinc,mcoffin\/zinc,troplin\/zinc,hackndev\/zinc,troplin\/zinc,farcaller\/zinc","old_file":"src\/hal\/k20\/layout.ld","new_file":"src\/hal\/k20\/layout.ld","new_contents":"__aeabi_unwind_cpp_pr0 = abort;\n__aeabi_unwind_cpp_pr1 = abort;\n__aeabi_unwind_cpp_pr2 = abort;\n\n\/* FIXME(bgamari): Make stack base configurable? *\/\n__STACK_BASE  = 0x20001FFF;\n\n_data_load = LOADADDR(.data);\n\nINCLUDE iomem.ld\n\nENTRY(main)\n\n\/* For MK20DX32 *\/\nMEMORY\n{\n    VECT (R)      : ORIGIN = 0x00000000, LENGTH = 0x3FC  \/* Vector area *\/\n    FIRC (R)      : ORIGIN = 0x000003FC, LENGTH = 4      \/* Custom IRC user trim *\/\n    FCFG (R)      : ORIGIN = 0x00000400, LENGTH = 16     \/* Flash config *\/\n    FLASH (RX)    : ORIGIN = 0x00000410, LENGTH = 32K - 0x410\n    RAM (WAIL)    : ORIGIN = 0x20000000 - 8K \/ 2, LENGTH = 8K\n}\n\nREGION_ALIAS(\"vectors\", VECT);\nREGION_ALIAS(\"flash_config\", FCFG)\nREGION_ALIAS(\"rom\", FLASH);\nREGION_ALIAS(\"ram\", RAM);\n\nSECTIONS\n{\n    .vector : ALIGN(4)\n    {\n        FILL(0xff)\n\n        KEEP(*(.isr_vector))\n        KEEP(*(.isr_vector_nvic))\n    } > vectors\n\n    .flashcfg : ALIGN(4)\n    {\n        KEEP(*(.flash_configuration))\n    } > flash_config\n\n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        *(.text*)\n        *(.rodata .rodata.*)\n    } > rom\n\n    .data : ALIGN(4)\n    {\n        _data = .;\n\n        *(SORT_BY_ALIGNMENT(.data*))\n        . = ALIGN(4);\n\n        _edata = .;\n    } > ram AT>rom = 0xff\n\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n\n        _ebss = .;\n\n        . += 4;\n\n        __STACK_LIMIT = .;\n\n        . += 4;\n\n        _eglobals = .;\n    } > ram\n\n    \/DISCARD\/ :\n    {\n        *(.glue_7*)  \/* arm-thumb interworking *\/\n        *(.v4_bx)  \/* ARMv4 interworking fixup for missing BX *\/\n        *(.vfp11_veneer)  \/* VFP11 bugfixes s.a. http:\/\/sourceware.org\/ml\/binutils\/2006-12\/msg00196.html *\/\n        *(.iplt .igot.plt)  \/* STT_GNU_IFUNC symbols *\/\n        *(.rel.*)  \/* dynamic relocations *\/\n        *(.ARM.exidx*) \/* index entries for section unwinding *\/\n        *(.ARM.extab*) \/* exception unwinding information *\/\n    }\n}\n\n","old_contents":"\/* FIXME(bgamari): Make stack base configurable? *\/\n__STACK_BASE  = 0x20001FFF;\n\n_data_load = LOADADDR(.data);\n\nINCLUDE iomem.ld\n\nENTRY(main)\n\n\/* For MK20DX32 *\/\nMEMORY\n{\n    VECT (R)      : ORIGIN = 0x00000000, LENGTH = 0x3FC  \/* Vector area *\/\n    FIRC (R)      : ORIGIN = 0x000003FC, LENGTH = 4      \/* Custom IRC user trim *\/\n    FCFG (R)      : ORIGIN = 0x00000400, LENGTH = 16     \/* Flash config *\/\n    FLASH (RX)    : ORIGIN = 0x00000410, LENGTH = 32K - 0x410\n    RAM (WAIL)    : ORIGIN = 0x20000000 - 8K \/ 2, LENGTH = 8K\n}\n\nREGION_ALIAS(\"vectors\", VECT);\nREGION_ALIAS(\"flash_config\", FCFG)\nREGION_ALIAS(\"rom\", FLASH);\nREGION_ALIAS(\"ram\", RAM);\n\nSECTIONS\n{\n    .vector : ALIGN(4)\n    {\n        FILL(0xff)\n\n        KEEP(*(.isr_vector))\n        KEEP(*(.isr_vector_nvic))\n    } > vectors\n\n    .flashcfg : ALIGN(4)\n    {\n        KEEP(*(.flash_configuration))\n    } > flash_config\n\n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        *(.text*)\n        *(.rodata .rodata.*)\n    } > rom\n\n    .data : ALIGN(4)\n    {\n        _data = .;\n\n        *(SORT_BY_ALIGNMENT(.data*))\n        . = ALIGN(4);\n\n        _edata = .;\n    } > ram AT>rom = 0xff\n\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n\n        _ebss = .;\n\n        . += 4;\n\n        __STACK_LIMIT = .;\n\n        . += 4;\n\n        _eglobals = .;\n    } > ram\n\n    \/DISCARD\/ :\n    {\n        *(.glue_7*)  \/* arm-thumb interworking *\/\n        *(.v4_bx)  \/* ARMv4 interworking fixup for missing BX *\/\n        *(.vfp11_veneer)  \/* VFP11 bugfixes s.a. http:\/\/sourceware.org\/ml\/binutils\/2006-12\/msg00196.html *\/\n        *(.iplt .igot.plt)  \/* STT_GNU_IFUNC symbols *\/\n        *(.rel.*)  \/* dynamic relocations *\/\n        *(.ARM.exidx*) \/* index entries for section unwinding *\/\n        *(.ARM.extab*) \/* exception unwinding information *\/\n    }\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"71683cbaa785fdc117ad87f6772564ed6d34c986","subject":"Fix secure linker script","message":"Fix secure linker script\n","repos":"kjbracey-arm\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed","old_file":"targets\/TARGET_ARM_SSG\/TARGET_MUSCA_A1\/TARGET_MUSCA_A1_S\/device\/TOOLCHAIN_GCC_ARM\/musca_s.ld","new_file":"targets\/TARGET_ARM_SSG\/TARGET_MUSCA_A1\/TARGET_MUSCA_A1_S\/device\/TOOLCHAIN_GCC_ARM\/musca_s.ld","new_contents":";\/*\n; * Copyright (c) 2018-2019 ARM Limited\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the \"License\");\n; * you may not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an \"AS IS\" BASIS,\n; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; *\n; * This file is derivative of CMSIS V5.00 gcc_arm.ld\n; *\/\n\n\/*********** WARNING: This is an auto-generated file. Do not edit! ***********\/\n\n\/* Linker script to configure memory regions. *\/\n\/* This file will be run trough the pre-processor. *\/\n\n#include \"..\/..\/..\/partition\/region_defs.h\"\n\n#if !defined(TFM_LVL)\n  #define TFM_LVL   1\n#endif\n\nMEMORY\n{\n  FLASH   (rx)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE\n  RAM     (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE\n  VENEERS (rx)  : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE\n}\n\nHEAP_SIZE = S_HEAP_SIZE;\n__heap_size__  = S_HEAP_SIZE;\n__psp_stack_size__ = S_PSP_STACK_SIZE;\n__msp_init_stack_size__ = S_MSP_STACK_SIZE;\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a)\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .TFM_VECTORS : ALIGN(4)\n    {\n        __vectors_start__ = .;\n        KEEP(*(.vectors))\n        *startup*(.text*)\n        . = ALIGN(4);\n        __vectors_end__ = .;\n    } > FLASH\n\n#if TFM_LVL == 1\n    .copy.table : ALIGN(4)\n    {\n        __copy_table_start__ = .;\n        LONG (LOADADDR(.TFM_DATA))\n        LONG (ADDR(.TFM_DATA))\n        LONG (SIZEOF(.TFM_DATA))\n        __copy_table_end__ = .;\n    } > FLASH\n\n    .zero.table : ALIGN(4)\n    {\n        __zero_table_start__ = .;\n        LONG (ADDR(.TFM_BSS))\n        LONG (SIZEOF(.TFM_BSS))\n        LONG (ADDR(.TFM_SECURE_STACK))\n        LONG (SIZEOF(.TFM_SECURE_STACK))\n        LONG (ADDR(.TFM_UNPRIV_SCRATCH))\n        LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))\n        __zero_table_end__ = .;\n    } > FLASH\n\n#else \/* TFM_LVL == 1 *\/\n    .copy.table : ALIGN(4)\n    {\n        __copy_table_start__ = .;\n        LONG (LOADADDR(.TFM_DATA))\n        LONG (ADDR(.TFM_DATA))\n        LONG (SIZEOF(.TFM_DATA))\n        LONG (LOADADDR(.TFM_UNPRIV_RO_DATA))\n        LONG (ADDR(.TFM_UNPRIV_RO_DATA))\n        LONG (SIZEOF(.TFM_UNPRIV_RO_DATA))\n        LONG (LOADADDR(.TFM_SP_PLATFORM_DATA))\n        LONG (ADDR(.TFM_SP_PLATFORM_DATA))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_DATA))\n        __copy_table_end__ = .;\n    } > FLASH\n\n    .zero.table : ALIGN(4)\n    {\n        __zero_table_start__ = .;\n        LONG (ADDR(.TFM_BSS))\n        LONG (SIZEOF(.TFM_BSS))\n        LONG (ADDR(.TFM_UNPRIV_RO_BSS))\n        LONG (SIZEOF(.TFM_UNPRIV_RO_BSS))\n        LONG (ADDR(.TFM_SP_PLATFORM_BSS))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_BSS))\n        LONG (ADDR(.TFM_SP_PLATFORM_STACK))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_STACK))\n        LONG (ADDR(.TFM_UNPRIV_SCRATCH))\n        LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))\n        __zero_table_end__ = .;\n    } > FLASH\n\n    .TFM_UNPRIV_CODE : ALIGN(32)\n    {\n        *libc_nano*:*(.text*)\n        *libc_nano*:*(.rodata*)\n        *tfm_spm_services.o(.text*)\n        *tfm_spm_services.o(.rodata*)\n        *platform_retarget_dev.o(.text*)\n        *platform_retarget_dev.o(.rodata*)\n        *(SFN)\n        *libgcc*:*(.text*)\n        *libgcc*:*(.rodata*)\n        . = ALIGN(32);\n    } > FLASH\n    Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);\n    Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);\n\n    .TFM_SP_PLATFORM : ALIGN(32)\n    {\n        *tfm_platform*:*(.text*)\n        *tfm_platform*:*(.rodata*)\n        *(TFM_SP_PLATFORM_ATTR_FN)\n        . = ALIGN(32);\n    } > FLASH\n    Image$$TFM_SP_PLATFORM$$RO$$Base = ADDR(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$RO$$Limit = ADDR(.TFM_SP_PLATFORM) + SIZEOF(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$Base = ADDR(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$Limit = ADDR(.TFM_SP_PLATFORM) + SIZEOF(.TFM_SP_PLATFORM);\n\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n#endif \/* TFM_LVL == 1 *\/\n\n    .ER_TFM_CODE :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n         *crtbegin.o(.dtors)\n         *crtbegin?.o(.dtors)\n         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n         *(SORT(.dtors.*))\n         *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    OVERLAY S_DATA_START :\n    {\n        \/* shared_data and msp_stack are overlapping on purpose when\n        * msp_stack is extended until the beginning of RAM, when shared_date\n        * was read out by partitions\n        *\/\n        .tfm_bl2_shared_data\n        {\n            . = ALIGN(32);\n            . += BOOT_TFM_SHARED_DATA_SIZE;\n        }\n\n        .msp_stack\n        {\n            . =  ALIGN(32);\n            . += S_MSP_STACK_SIZE;\n        }\n    } > RAM\n\n    Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);\n\n    .psp_stack :\n    {\n        . =  ALIGN(32);\n        . += S_PSP_STACK_SIZE;\n    } > RAM\n    Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);\n    Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);\n\n#if TFM_LVL == 1\n\n    .heap :\n    {\n        . = ALIGN(8);\n        __end__ = .;\n        PROVIDE(end = .);\n        __HeapBase = .;\n        . += S_HEAP_SIZE;\n        __HeapLimit = .;\n        __heap_limit = .; \/* Add for _sbrk *\/\n    } > RAM\n    Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);\n    Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);\n\n    .TFM_SECURE_STACK :\n    {\n        . = ALIGN(128);\n        . += 0x1000;\n    } > RAM\n    Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);\n    Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);\n\n    .TFM_UNPRIV_SCRATCH :\n    {\n        . = ALIGN(32);\n        . += 0x400;\n    } > RAM\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);\n#else \/* TFM_LVL == 1 *\/\n    .TFM_UNPRIV_RO_DATA :\n    {\n        *\/tfm_spm_services.o(.data*)\n        *\/platform_retarget_dev.o(.data*)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_RO_DATA$$RW$$Base = ADDR(.TFM_UNPRIV_RO_DATA);\n    Image$$TFM_UNPRIV_RO_DATA$$RW$$Limit = ADDR(.TFM_UNPRIV_RO_DATA) + SIZEOF(.TFM_UNPRIV_RO_DATA);\n\n    .TFM_UNPRIV_RO_BSS : ALIGN(32)\n    {\n        *\/tfm_spm_services.o(.bss*)\n        *\/platform_retarget_dev.o(.bss*)\n        *\/tfm_spm_services.o(COMMON)\n        *\/platform_retarget_dev.o(COMMON)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_RO_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_RO_BSS);\n    Image$$TFM_UNPRIV_RO_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_RO_BSS) + SIZEOF(.TFM_UNPRIV_RO_BSS);\n\n    .TFM_UNPRIV_SCRATCH : ALIGN(32)\n    {\n        . += 0x400;\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);\n\n    .TFM_SP_PLATFORM_DATA : ALIGN(32)\n    {\n        *tfm_platform*:*(.data*)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_DATA$$RW$$Base = ADDR(.TFM_SP_PLATFORM_DATA);\n    Image$$TFM_SP_PLATFORM_DATA$$RW$$Limit = ADDR(.TFM_SP_PLATFORM_DATA) + SIZEOF(.TFM_SP_PLATFORM_DATA);\n\n    .TFM_SP_PLATFORM_BSS : ALIGN(32)\n    {\n        *tfm_platform*:*(.bss*)\n        *tfm_platform*:*(COMMON)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_DATA$$ZI$$Base = ADDR(.TFM_SP_PLATFORM_BSS);\n    Image$$TFM_SP_PLATFORM_DATA$$ZI$$Limit = ADDR(.TFM_SP_PLATFORM_BSS) + SIZEOF(.TFM_SP_PLATFORM_BSS);\n\n    .TFM_SP_PLATFORM_STACK : ALIGN(128)\n    {\n        . += 0x0400;\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_STACK$$ZI$$Base = ADDR(.TFM_SP_PLATFORM_STACK);\n    Image$$TFM_SP_PLATFORM_STACK$$ZI$$Limit = ADDR(.TFM_SP_PLATFORM_STACK) + SIZEOF(.TFM_SP_PLATFORM_STACK);\n\n#endif \/* TFM_LVL == 1 *\/\n\n    .TFM_DATA :\n    {\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n\n    } > RAM AT> FLASH\n    Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);\n    Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);\n\n    .TFM_BSS :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);\n    Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);\n\n    Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA);\n    Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS);\n\n    ASSERT(Image$$ER_TFM_DATA$$Limit <= S_DATA_START + S_DATA_SIZE, \"Exceeding secure RAM\")\n\n    \/*\n     * Place the CMSE Veneers (containing the SG instruction) after the code, in a\n     * separate 32 bytes aligned region so that the SAU can programmed to just set\n     * this region as Non-Secure Callable.\n     *\/\n    .gnu.sgstubs : ALIGN(32)\n    {\n        *(.gnu.sgstubs*)\n        . = ALIGN(32);\n    } > VENEERS AT> VENEERS\n    Image$$ER_CODE_CMSE_VENEER$$Base = ADDR(.gnu.sgstubs);\n    Image$$ER_CODE_CMSE_VENEER$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);\n\n    Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START;\n\n    Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START;\n\n    PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);\n}\n","old_contents":";\/*\n; * Copyright (c) 2018-2019 ARM Limited\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the \"License\");\n; * you may not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an \"AS IS\" BASIS,\n; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; *\n; * This file is derivative of CMSIS V5.00 gcc_arm.ld\n; *\/\n\n\/*********** WARNING: This is an auto-generated file. Do not edit! ***********\/\n\n\/* Linker script to configure memory regions. *\/\n\/* This file will be run trough the pre-processor. *\/\n\n#include \"..\/..\/..\/partition\/region_defs.h\"\n\n#if !defined(TFM_LVL)\n  #define TFM_LVL   1\n#endif\n\nMEMORY\n{\n  FLASH   (rx)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE\n  RAM     (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE\n  VENEERS (rx)  : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE\n}\n\nHEAP_SIZE = S_HEAP_SIZE;\n__heap_size__  = S_HEAP_SIZE;\n__psp_stack_size__ = S_PSP_STACK_SIZE;\n__msp_init_stack_size__ = S_MSP_STACK_SIZE;\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a)\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .TFM_VECTORS : ALIGN(4)\n    {\n        __vectors_start__ = .;\n        KEEP(*(.vectors))\n        *startup*(.text*)\n        . = ALIGN(4);\n        __vectors_end__ = .;\n    } > FLASH\n\n#if TFM_LVL == 1\n    .copy.table : ALIGN(4)\n    {\n        __copy_table_start__ = .;\n        LONG (LOADADDR(.TFM_DATA))\n        LONG (ADDR(.TFM_DATA))\n        LONG (SIZEOF(.TFM_DATA))\n        __copy_table_end__ = .;\n    } > FLASH\n\n    .zero.table : ALIGN(4)\n    {\n        __zero_table_start__ = .;\n        LONG (ADDR(.TFM_BSS))\n        LONG (SIZEOF(.TFM_BSS))\n        LONG (ADDR(.TFM_SECURE_STACK))\n        LONG (SIZEOF(.TFM_SECURE_STACK))\n        LONG (ADDR(.TFM_UNPRIV_SCRATCH))\n        LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))\n        __zero_table_end__ = .;\n    } > FLASH\n\n#else \/* TFM_LVL == 1 *\/\n    .copy.table : ALIGN(4)\n    {\n        __copy_table_start__ = .;\n        LONG (LOADADDR(.TFM_DATA))\n        LONG (ADDR(.TFM_DATA))\n        LONG (SIZEOF(.TFM_DATA))\n        LONG (LOADADDR(.TFM_UNPRIV_RO_DATA))\n        LONG (ADDR(.TFM_UNPRIV_RO_DATA))\n        LONG (SIZEOF(.TFM_UNPRIV_RO_DATA))\n        LONG (LOADADDR(.TFM_SP_PLATFORM_DATA))\n        LONG (ADDR(.TFM_SP_PLATFORM_DATA))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_DATA))\n        __copy_table_end__ = .;\n    } > FLASH\n\n    .zero.table : ALIGN(4)\n    {\n        __zero_table_start__ = .;\n        LONG (ADDR(.TFM_BSS))\n        LONG (SIZEOF(.TFM_BSS))\n        LONG (ADDR(.TFM_UNPRIV_RO_BSS))\n        LONG (SIZEOF(.TFM_UNPRIV_RO_BSS))\n        LONG (ADDR(.TFM_SP_PLATFORM_BSS))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_BSS))\n        LONG (ADDR(.TFM_SP_PLATFORM_STACK))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_STACK))\n        LONG (ADDR(.TFM_UNPRIV_SCRATCH))\n        LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))\n        __zero_table_end__ = .;\n    } > FLASH\n\n    .TFM_UNPRIV_CODE : ALIGN(32)\n    {\n        *libc_nano*:*(.text*)\n        *libc_nano*:*(.rodata*)\n        *tfm_spm_services.o(.text*)\n        *tfm_spm_services.o(.rodata*)\n        *platform_retarget_dev.o(.text*)\n        *platform_retarget_dev.o(.rodata*)\n        *(SFN)\n        *libgcc*:*(.text*)\n        *libgcc*:*(.rodata*)\n        . = ALIGN(32);\n    } > FLASH\n    Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);\n    Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);\n\n    .TFM_SP_PLATFORM : ALIGN(32)\n    {\n        *tfm_platform*:*(.text*)\n        *tfm_platform*:*(.rodata*)\n        *(TFM_SP_PLATFORM_ATTR_FN)\n        . = ALIGN(32);\n    } > FLASH\n    Image$$TFM_SP_PLATFORM$$RO$$Base = ADDR(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$RO$$Limit = ADDR(.TFM_SP_PLATFORM) + SIZEOF(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$Base = ADDR(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$Limit = ADDR(.TFM_SP_PLATFORM) + SIZEOF(.TFM_SP_PLATFORM);\n\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n#endif \/* TFM_LVL == 1 *\/\n\n    .ER_TFM_CODE :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n         *crtbegin.o(.dtors)\n         *crtbegin?.o(.dtors)\n         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n         *(SORT(.dtors.*))\n         *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    OVERLAY S_DATA_START :\n    {\n        \/* shared_data and msp_stack are overlapping on purpose when\n        * msp_stack is extended until the beginning of RAM, when shared_date\n        * was read out by partitions\n        *\/\n        .tfm_bl2_shared_data\n        {\n            . = ALIGN(32);\n            . += BOOT_TFM_SHARED_DATA_SIZE;\n        }\n\n        .msp_stack\n        {\n            . =  ALIGN(32);\n            . += S_MSP_STACK_SIZE;\n        }\n    } > RAM\n\n    Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);\n\n    .psp_stack :\n    {\n        . =  ALIGN(32);\n        . += S_PSP_STACK_SIZE;\n    } > RAM\n    Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);\n    Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);\n\n#if TFM_LVL == 1\n\n    .heap :\n    {\n        . = ALIGN(8);\n        __end__ = .;\n        PROVIDE(end = .);\n        __HeapBase = .;\n        . += S_HEAP_SIZE;\n        __HeapLimit = .;\n        __heap_limit = .; \/* Add for _sbrk *\/\n    } > RAM\n    Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);\n    Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);\n\n    .TFM_SECURE_STACK :\n    {\n        . = ALIGN(128);\n        . += 0x1000;\n    } > RAM\n    Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);\n    Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);\n\n    .TFM_UNPRIV_SCRATCH :\n    {\n        . = ALIGN(32);\n        . += 0x400;\n    } > RAM\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);\n#else \/* TFM_LVL == 1 *\/\n    .TFM_UNPRIV_RO_DATA :\n    {\n        *\/tfm_spm_services.o(.data*)\n        *\/platform_retarget_dev.o(.data*)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_RO_DATA$$RW$$Base = ADDR(.TFM_UNPRIV_RO_DATA);\n    Image$$TFM_UNPRIV_RO_DATA$$RW$$Limit = ADDR(.TFM_UNPRIV_RO_DATA) + SIZEOF(.TFM_UNPRIV_RO_DATA);\n\n    .TFM_UNPRIV_RO_BSS : ALIGN(32)\n    {\n        *\/tfm_spm_services.o(.bss*)\n        *\/platform_retarget_dev.o(.bss*)\n        *\/tfm_spm_services.o(COMMON)\n        *\/platform_retarget_dev.o(COMMON)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_RO_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_RO_BSS);\n    Image$$TFM_UNPRIV_RO_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_RO_BSS) + SIZEOF(.TFM_UNPRIV_RO_BSS);\n\n    .TFM_UNPRIV_SCRATCH : ALIGN(32)\n    {\n        . += 0x400;\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);\n\n    .TFM_SP_PLATFORM_DATA : ALIGN(32)\n    {\n        *tfm_platform*:*(.data*)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_DATA$$RW$$Base = ADDR(.TFM_SP_PLATFORM_DATA);\n    Image$$TFM_SP_PLATFORM_DATA$$RW$$Limit = ADDR(.TFM_SP_PLATFORM_DATA) + SIZEOF(.TFM_SP_PLATFORM_DATA);\n\n    .TFM_SP_PLATFORM_BSS : ALIGN(32)\n    {\n        *tfm_platform*:*(.bss*)\n        *tfm_platform*:*(COMMON)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_DATA$$ZI$$Base = ADDR(.TFM_SP_PLATFORM_BSS);\n    Image$$TFM_SP_PLATFORM_DATA$$ZI$$Limit = ADDR(.TFM_SP_PLATFORM_BSS) + SIZEOF(.TFM_SP_PLATFORM_BSS);\n\n    .TFM_SP_PLATFORM_STACK : ALIGN(128)\n    {\n        . += 0x0400;\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_STACK$$ZI$$Base = ADDR(.TFM_SP_PLATFORM_STACK);\n    Image$$TFM_SP_PLATFORM_STACK$$ZI$$Limit = ADDR(.TFM_SP_PLATFORM_STACK) + SIZEOF(.TFM_SP_PLATFORM_STACK);\n\n#endif \/* TFM_LVL == 1 *\/\n\n    .TFM_DATA :\n    {\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n\n    } > RAM AT> FLASH\n    Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);\n    Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);\n\n    .TFM_BSS :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);\n    Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);\n\n    Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA);\n    Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS);\n\n    ASSERT(Image$$ER_TFM_DATA$$Limit <= S_DATA_START + S_DATA_SIZE, \"Exceeding secure RAM\")\n\n    \/*\n     * Place the CMSE Veneers (containing the SG instruction) after the code, in a\n     * separate 32 bytes aligned region so that the SAU can programmed to just set\n     * this region as Non-Secure Callable.\n     *\/\n    .gnu.sgstubs : ALIGN(32)\n    {\n        *(.gnu.sgstubs*)\n        . = ALIGN(32);\n    } > VENEERS AT> VENEERS\n    Image$$ER_CODE_CMSE_VENEER$$Base = ADDR(.gnu.sgstubs);\n    Image$$ER_CODE_CMSE_VENEER$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);\n\n    Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START;\n\n    Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START;\n\n    PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"de74edb5d9c98c00d37ffee70bc00fe27e9c725b","subject":"Bump linker text region size.  Code size has grown.","message":"Bump linker text region size.  Code size has grown.\n\nSome combination of using a different riscv toolchain in CI,\nand the recent TFLM bump.\n\nSigned-off-by: Tim Callahan <ea16a3c075a6a229c9a452aa4faba7441b41c040@google.com>\n","repos":"google\/CFU-Playground,google\/CFU-Playground,google\/CFU-Playground,google\/CFU-Playground","old_file":"common\/_hps\/hps\/ld\/linker.ld","new_file":"common\/_hps\/hps\/ld\/linker.ld","new_contents":"INCLUDE output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE regions.ld\n\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(SORT(.text.start))\n\t\t*(SORT(.text))\n\t\t*(SORT(.stub))\n\t\t*(SORT(.text.*))\n\t\t*(SORT(.gnu.linkonce.t.*))\n\t\t_etext = .;\n\t} > rom\n\n\t.rodata :\n\t{\n\t\t\/*\n\t\t * Align models and large chunks of data into a constant position\n\t\t *\/\n\t\t. = _ftext + 0x81800;\n\t\t_frodata = .;\n\t\tsrc\/models\/*\/*(SORT(.rodata.*))\n\t\tsrc\/conv2d_??.o(SORT(.rodata.*))  \/* specific to hps_accel *\/\n\t\t. = ALIGN(4096);\n\t\t*(SORT(.rodata))\n\t\t*(SORT(.rodata.*))\n\t\t*(SORT(.gnu.linkonce.r.*))\n\t\t*(SORT(.rodata1))\n\t\t*(SORT(.srodata))\n\t\t*(SORT(.srodata.*))\n\t\t. = ALIGN(8);\n\t\t_erodata = .;\n\t} > rom\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(8);\n\t\t_fdata = .;\n\t\t*(SORT(.data))\n\t\t*(SORT(.data.*))\n\t\t*(SORT(.gnu.linkonce.d.*))\n\t\t*(SORT(.data1))\n\t\t*(SORT(.ramtext))\n\t\t*(SORT(.ramtext.*))\n\t\t_gp = ALIGN(16);\n\t\t*(SORT(.sdata))\n\t\t*(SORT(.sdata.*))\n\t\t*(SORT(.gnu.linkonce.s.*))\n\t\t*(SORT(.sdata2))\n\t\t*(SORT(.sdata2.*))\n\t\t_edata = ALIGN(16); \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss : AT (ADDR(.data) + SIZEOF (.data))\n\t{\n\t\t. = ALIGN(16);\n\t\t_fbss = .;\n\t\t*(SORT(.dynsbss))\n\t\t*(SORT(.sbss))\n\t\t*(SORT(.sbss.*))\n\t\t*(SORT(.gnu.linkonce.sb.*))\n\t\t*(SORT(.scommon))\n\t\t*(SORT(.dynbss))\n\t\t*(SORT(.bss))\n\t\t*(SORT(.bss.*))\n\t\t*(SORT(.gnu.linkonce.b.*))\n\t\t*(SORT(COMMON))\n\t\t. = ALIGN(8);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n\n        .arena (NOLOAD) :\n        {\n                _farena = .;\n                *(.arena)\n                _earena = .;\n        } > arena\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","old_contents":"INCLUDE output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE regions.ld\n\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(SORT(.text.start))\n\t\t*(SORT(.text))\n\t\t*(SORT(.stub))\n\t\t*(SORT(.text.*))\n\t\t*(SORT(.gnu.linkonce.t.*))\n\t\t_etext = .;\n\t} > rom\n\n\t.rodata :\n\t{\n\t\t\/*\n\t\t * Align models and large chunks of data into a constant position\n\t\t *\/\n\t\t. = _ftext + 0x81000;\n\t\t_frodata = .;\n\t\tsrc\/models\/*\/*(SORT(.rodata.*))\n\t\tsrc\/conv2d_??.o(SORT(.rodata.*))  \/* specific to hps_accel *\/\n\t\t. = ALIGN(4096);\n\t\t*(SORT(.rodata))\n\t\t*(SORT(.rodata.*))\n\t\t*(SORT(.gnu.linkonce.r.*))\n\t\t*(SORT(.rodata1))\n\t\t*(SORT(.srodata))\n\t\t*(SORT(.srodata.*))\n\t\t. = ALIGN(8);\n\t\t_erodata = .;\n\t} > rom\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(8);\n\t\t_fdata = .;\n\t\t*(SORT(.data))\n\t\t*(SORT(.data.*))\n\t\t*(SORT(.gnu.linkonce.d.*))\n\t\t*(SORT(.data1))\n\t\t*(SORT(.ramtext))\n\t\t*(SORT(.ramtext.*))\n\t\t_gp = ALIGN(16);\n\t\t*(SORT(.sdata))\n\t\t*(SORT(.sdata.*))\n\t\t*(SORT(.gnu.linkonce.s.*))\n\t\t*(SORT(.sdata2))\n\t\t*(SORT(.sdata2.*))\n\t\t_edata = ALIGN(16); \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss : AT (ADDR(.data) + SIZEOF (.data))\n\t{\n\t\t. = ALIGN(16);\n\t\t_fbss = .;\n\t\t*(SORT(.dynsbss))\n\t\t*(SORT(.sbss))\n\t\t*(SORT(.sbss.*))\n\t\t*(SORT(.gnu.linkonce.sb.*))\n\t\t*(SORT(.scommon))\n\t\t*(SORT(.dynbss))\n\t\t*(SORT(.bss))\n\t\t*(SORT(.bss.*))\n\t\t*(SORT(.gnu.linkonce.b.*))\n\t\t*(SORT(COMMON))\n\t\t. = ALIGN(8);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n\n        .arena (NOLOAD) :\n        {\n                _farena = .;\n                *(.arena)\n                _earena = .;\n        } > arena\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a8bf11f1b1dea1a44bdb8b5b204328b673dcbd0d","subject":"use tabs instead of white spaces","message":"use tabs instead of white spaces\n","repos":"RWTH-OS\/eduOS-rs","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nOUTPUT_FORMAT(\"elf64-x86-64\")\nOUTPUT_ARCH(\"i386:x86-64\")\nENTRY(start)\n\nSECTIONS {\n\t\/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n\t. = 1M;\n\n\tkernel_start = .;\n\t.boot :\n\t{\n\t\t\/* This goes first. *\/\n\t\tKEEP(*(.multiboot_header))\n\t}\n\n\t.text ALIGN(4096) : AT(ADDR(.text))\n\t{\n\t\t*(.text)\n\t\t*(.text.*)\n\t}\n\n\t.rodata : AT(ADDR(.rodata))\n\t{\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t}\n\n\t.data ALIGN(4096) : AT(ADDR(.data))\n\t{\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n\n\t.bss ALIGN(4096) : AT(ADDR(.bss))\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t}\n\tkernel_end = .;\n}\n","old_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nOUTPUT_FORMAT(\"elf64-x86-64\")\nOUTPUT_ARCH(\"i386:x86-64\")\nENTRY(start)\n\nSECTIONS {\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n\tkernel_start = .;\n    .boot :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n    }\n\n    .text ALIGN(4096) : AT(ADDR(.text))\n    {\n        *(.text)\n\t\t*(.text.*)\n    }\n\n\t.rodata : AT(ADDR(.rodata))\n\t{\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t}\n\n\t.data ALIGN(4096) : AT(ADDR(.data))\n    {\n        *(.data)\n\t\t*(.data.*)\n    }\n\n\t.bss ALIGN(4096) : AT(ADDR(.bss))\n    {\n\t\t__bss_start = .;\n        *(.bss)\n\t\t*(.bss.*)\n    }\n\tkernel_end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a1b383a604e59218e98b561693a88101e8dc8acb","subject":"support mesh in GCC tool chain","message":"support mesh in GCC tool chain\n","repos":"screamerbg\/mbed,betzw\/mbed-os,netzimme\/mbed-os,theotherjimmy\/mbed,bulislaw\/mbed-os,nvlsianpu\/mbed,Archcady\/mbed-os,theotherjimmy\/mbed,infinnovation\/mbed-os,cvtsi2sd\/mbed-os,NXPmicro\/mbed,karsev\/mbed-os,HeadsUpDisplayInc\/mbed,adamgreen\/mbed,HeadsUpDisplayInc\/mbed,pradeep-gr\/mbed-os5-onsemi,infinnovation\/mbed-os,fanghuaqi\/mbed,RonEld\/mbed,kl-cruz\/mbed-os,bulislaw\/mbed-os,mikaleppanen\/mbed-os,j-greffe\/mbed-os,j-greffe\/mbed-os,c1728p9\/mbed-os,mikaleppanen\/mbed-os,pradeep-gr\/mbed-os5-onsemi,nRFMesh\/mbed-os,infinnovation\/mbed-os,theotherjimmy\/mbed,fahhem\/mbed-os,screamerbg\/mbed,maximmbed\/mbed,Archcady\/mbed-os,netzimme\/mbed-os,YarivCol\/mbed-os,kl-cruz\/mbed-os,nvlsianpu\/mbed,NXPmicro\/mbed,HeadsUpDisplayInc\/mbed,mmorenobarm\/mbed-os,catiedev\/mbed-os,karsev\/mbed-os,RonEld\/mbed,mmorenobarm\/mbed-os,Archcady\/mbed-os,HeadsUpDisplayInc\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,nvlsianpu\/mbed,bulislaw\/mbed-os,arostm\/mbed-os,mbedmicro\/mbed,monkiineko\/mbed-os,mikaleppanen\/mbed-os,netzimme\/mbed-os,arostm\/mbed-os,betzw\/mbed-os,adamgreen\/mbed,mbedmicro\/mbed,cvtsi2sd\/mbed-os,catiedev\/mbed-os,karsev\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,bcostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,adamgreen\/mbed,ryankurte\/mbed-os,monkiineko\/mbed-os,adustm\/mbed,c1728p9\/mbed-os,YarivCol\/mbed-os,screamerbg\/mbed,YarivCol\/mbed-os,ryankurte\/mbed-os,nRFMesh\/mbed-os,bcostm\/mbed-os,arostm\/mbed-os,j-greffe\/mbed-os,catiedev\/mbed-os,CalSol\/mbed,catiedev\/mbed-os,YarivCol\/mbed-os,HeadsUpDisplayInc\/mbed,svogl\/mbed-os,fahhem\/mbed-os,monkiineko\/mbed-os,mmorenobarm\/mbed-os,monkiineko\/mbed-os,karsev\/mbed-os,monkiineko\/mbed-os,bcostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,mazimkhan\/mbed-os,pradeep-gr\/mbed-os5-onsemi,adustm\/mbed,adamgreen\/mbed,adustm\/mbed,cvtsi2sd\/mbed-os,maximmbed\/mbed,NXPmicro\/mbed,maximmbed\/mbed,mmorenobarm\/mbed-os,svogl\/mbed-os,cvtsi2sd\/mbed-os,CalSol\/mbed,theotherjimmy\/mbed,bcostm\/mbed-os,arostm\/mbed-os,RonEld\/mbed,Archcady\/mbed-os,mazimkhan\/mbed-os,screamerbg\/mbed,mazimkhan\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,fahhem\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,maximmbed\/mbed,maximmbed\/mbed,arostm\/mbed-os,netzimme\/mbed-os,bulislaw\/mbed-os,andcor02\/mbed-os,fahhem\/mbed-os,Archcady\/mbed-os,c1728p9\/mbed-os,fanghuaqi\/mbed,kl-cruz\/mbed-os,betzw\/mbed-os,fahhem\/mbed-os,mmorenobarm\/mbed-os,kl-cruz\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,c1728p9\/mbed-os,bcostm\/mbed-os,nRFMesh\/mbed-os,kjbracey-arm\/mbed,netzimme\/mbed-os,svogl\/mbed-os,Archcady\/mbed-os,adamgreen\/mbed,NXPmicro\/mbed,mbedmicro\/mbed,infinnovation\/mbed-os,fanghuaqi\/mbed,andcor02\/mbed-os,nRFMesh\/mbed-os,j-greffe\/mbed-os,c1728p9\/mbed-os,CalSol\/mbed,fanghuaqi\/mbed,fahhem\/mbed-os,j-greffe\/mbed-os,j-greffe\/mbed-os,mazimkhan\/mbed-os,mazimkhan\/mbed-os,nvlsianpu\/mbed,YarivCol\/mbed-os,monkiineko\/mbed-os,HeadsUpDisplayInc\/mbed,adamgreen\/mbed,screamerbg\/mbed,YarivCol\/mbed-os,nvlsianpu\/mbed,mbedmicro\/mbed,kl-cruz\/mbed-os,svogl\/mbed-os,bulislaw\/mbed-os,bcostm\/mbed-os,adustm\/mbed,ryankurte\/mbed-os,catiedev\/mbed-os,CalSol\/mbed,karsev\/mbed-os,nRFMesh\/mbed-os,infinnovation\/mbed-os,RonEld\/mbed,svogl\/mbed-os,betzw\/mbed-os,mazimkhan\/mbed-os,maximmbed\/mbed,pradeep-gr\/mbed-os5-onsemi,betzw\/mbed-os,RonEld\/mbed,netzimme\/mbed-os,NXPmicro\/mbed,nRFMesh\/mbed-os,adustm\/mbed,kjbracey-arm\/mbed,catiedev\/mbed-os,andcor02\/mbed-os,mikaleppanen\/mbed-os,mikaleppanen\/mbed-os,ryankurte\/mbed-os,betzw\/mbed-os,andcor02\/mbed-os,cvtsi2sd\/mbed-os,ryankurte\/mbed-os,theotherjimmy\/mbed,kjbracey-arm\/mbed,CalSol\/mbed,andcor02\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,nvlsianpu\/mbed,NXPmicro\/mbed,ryankurte\/mbed-os,kjbracey-arm\/mbed,CalSol\/mbed,cvtsi2sd\/mbed-os,karsev\/mbed-os,bulislaw\/mbed-os,RonEld\/mbed,theotherjimmy\/mbed,screamerbg\/mbed,c1728p9\/mbed-os,fanghuaqi\/mbed,infinnovation\/mbed-os,mbedmicro\/mbed,mikaleppanen\/mbed-os,andcor02\/mbed-os,mmorenobarm\/mbed-os,adustm\/mbed,arostm\/mbed-os,kl-cruz\/mbed-os,svogl\/mbed-os","old_file":"targets\/TARGET_NUVOTON\/TARGET_NUC472\/device\/TOOLCHAIN_GCC_ARM\/NUC472.ld","new_file":"targets\/TARGET_NUVOTON\/TARGET_NUC472\/device\/TOOLCHAIN_GCC_ARM\/NUC472.ld","new_contents":"\/*\n * Nuvoton NUC472 GCC linker script file\n *\/\n\nStackSize = 0x3000;\n\nMEMORY\n{\n    \n  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400\n  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000\n  RAM_EXTERN (rwx)      : ORIGIN = 0x60000000, LENGTH = 0x00100000\n}\n\n\/**\n * Must match cmsis_nvic.h\n *\/\n__vector_size = 4 * (16 + 142);\n \n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        \/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. *\/\n        . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));\n        __uvisor_bss_end = .;\n    } > RAM_INTERN\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += StackSize - (. - __StackLimit);\n    } > RAM_INTERN\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Relocate vector table in SRAM *\/\n    .isr_vector.reloc (NOLOAD) :\n    {\n        . = ALIGN(1 << LOG2CEIL(__vector_size));\n        PROVIDE(__start_vector_table__ = .);\n        . += __vector_size;\n        PROVIDE(__end_vector_table__ = .);\n    } > RAM_INTERN\n    \n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM_INTERN AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assertions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM_INTERN\n\n    .bss.extern (NOLOAD):\n    {\n        __bss_extern_start__ = .;\n        \/**\n         * Place large .bss* sections into external SRAM if internal SRAM is insufficient.\n         * Such memory arrangement requires initializing .bss.extern section to zero in startup file. Check startup fiile in cmsis-core-* for support or not.\n         *\/\n        *lwip_*.o(.bss*)\n        *lwip_*.o(COMMON)\n        *mesh_system.o(.bss*)\n       __bss_extern_end__ = .;\n    } > RAM_EXTERN\n    \n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM_INTERN\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM_EXTERN) + LENGTH(RAM_EXTERN) - .);\n        __HeapLimit = .;\n    } > RAM_EXTERN\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* Provide physical memory boundaries for uVisor. *\/\n    __uvisor_flash_start = ORIGIN(VECTORS);\n    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n    __uvisor_sram_start = ORIGIN(RAM_INTERN);\n    __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);\n}\n","old_contents":"\/*\n * Nuvoton NUC472 GCC linker script file\n *\/\n\nStackSize = 0x3000;\n\nMEMORY\n{\n    \n  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400\n  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000\n  RAM_EXTERN (rwx)      : ORIGIN = 0x60000000, LENGTH = 0x00100000\n}\n\n\/**\n * Must match cmsis_nvic.h\n *\/\n__vector_size = 4 * (16 + 142);\n \n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        \/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. *\/\n        . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));\n        __uvisor_bss_end = .;\n    } > RAM_INTERN\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += StackSize - (. - __StackLimit);\n    } > RAM_INTERN\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Relocate vector table in SRAM *\/\n    .isr_vector.reloc (NOLOAD) :\n    {\n        . = ALIGN(1 << LOG2CEIL(__vector_size));\n        PROVIDE(__start_vector_table__ = .);\n        . += __vector_size;\n        PROVIDE(__end_vector_table__ = .);\n    } > RAM_INTERN\n    \n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM_INTERN AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assertions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM_INTERN\n\n    .bss.extern (NOLOAD):\n    {\n        __bss_extern_start__ = .;\n        \/**\n         * Place large .bss* sections into external SRAM if internal SRAM is insufficient.\n         * Such memory arrangement requires initializing .bss.extern section to zero in startup file. Check startup fiile in cmsis-core-* for support or not.\n         *\/\n        *lwip_*.o(.bss*)\n        *lwip_*.o(COMMON)\n       __bss_extern_end__ = .;\n    } > RAM_EXTERN\n    \n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM_INTERN\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM_EXTERN) + LENGTH(RAM_EXTERN) - .);\n        __HeapLimit = .;\n    } > RAM_EXTERN\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* Provide physical memory boundaries for uVisor. *\/\n    __uvisor_flash_start = ORIGIN(VECTORS);\n    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n    __uvisor_sram_start = ORIGIN(RAM_INTERN);\n    __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7876375707a7bc59d298a88e1b0dac55610d6d1e","subject":"zephyr: riscv: linker: correct __image_size","message":"zephyr: riscv: linker: correct __image_size\n\nWith CL:3088970, the _image_rom_size has been able to provide\ncorrect image size. So configure __image_size = _image_rom_size;\n\nBRANCH=none\nBUG=b:195954913\nTEST=software sync is successfully.\n\nSigned-off-by: Dino Li <338d523ecf3700bd86eb9c34d220f91911d2a18c@ite.com.tw>\n\nCq-Depend: chromium:3088970\nChange-Id: I23a2f33aa15df7a8469d5591dc8d310d0313be92\nReviewed-on: https:\/\/chromium-review.googlesource.com\/c\/chromiumos\/platform\/ec\/+\/3105912\nTested-by: Dino Li <338d523ecf3700bd86eb9c34d220f91911d2a18c@ite.com.tw>\nReviewed-by: Denis Brockus <6b21e8190fb5e373363fb95271367073a16474ef@chromium.org>\nReviewed-by: Keith Short <f6d578f97033c25f1206cb57d52f358974c82954@chromium.org>\nCommit-Queue: Denis Brockus <6b21e8190fb5e373363fb95271367073a16474ef@chromium.org>\nCommit-Queue: Keith Short <f6d578f97033c25f1206cb57d52f358974c82954@chromium.org>\n","repos":"coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec","old_file":"zephyr\/linker\/image_size.ld","new_file":"zephyr\/linker\/image_size.ld","new_contents":"\/* Copyright 2021 The Chromium OS Authors. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n *\/\n\n#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_R) || \\\n\tdefined(CONFIG_CPU_CORTEX_A)\n__image_size = _flash_used;\n#elif defined(CONFIG_RISCV)\n__image_size = _image_rom_size;\n#else\n\/*\n * Intentionally set to 0. Some components, such as EFS2, need this value.\n * Having it be 0 will make it easier to find and add new cores.\n *\/\n__image_size = 0;\n#endif\n","old_contents":"\/* Copyright 2021 The Chromium OS Authors. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n *\/\n\n#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_R) || \\\n\tdefined(CONFIG_CPU_CORTEX_A)\n__image_size = _flash_used;\n#elif defined(CONFIG_RISCV)\n\/* Firmware binary size is text + rodata + data in rom. *\/\n__image_size = _image_rom_size + (__data_ram_end - __data_ram_start);\n#else\n\/*\n * Intentionally set to 0. Some components, such as EFS2, need this value.\n * Having it be 0 will make it easier to find and add new cores.\n *\/\n__image_size = 0;\n#endif\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"8c1acb036378a1adc0c808e45d7bb08105532da3","subject":"Provide a default for CONFIG_BT_RESERVE_DRAM","message":"Provide a default for CONFIG_BT_RESERVE_DRAM\n\n...when BT is not built\n\nMerges https:\/\/github.com\/espressif\/esp-idf\/pull\/910\n","repos":"armada-ai\/esp-idf,mashaoze\/esp-idf,nineisk\/esp-idf,shukyisme\/esp-idf-kwik,jaracil\/esp-idf,armada-ai\/esp-idf,Hermiedapwdrman\/esp-idf,espressif\/esp-idf,www220\/esp-idf,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,empoweredhomes\/esp-idf,nineisk\/esp-idf,ajs124\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,nineisk\/esp-idf,MIhanguangyi\/esp-idf,espressif\/esp-idf,www220\/esp-idf,shukyisme\/esp-idf-kwik,espressif\/esp-idf,www220\/esp-idf,shukyisme\/esp-idf-kwik,jaracil\/esp-idf,empoweredhomes\/esp-idf,Hermiedapwdrman\/esp-idf,ajs124\/esp-idf,Hermiedapwdrman\/esp-idf,empoweredhomes\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,MIhanguangyi\/esp-idf,ajs124\/esp-idf,armada-ai\/esp-idf,espressif\/esp-idf,Hermiedapwdrman\/esp-idf,nineisk\/esp-idf,Hermiedapwdrman\/esp-idf,empoweredhomes\/esp-idf,MIhanguangyi\/esp-idf,jaracil\/esp-idf,empoweredhomes\/esp-idf,MIhanguangyi\/esp-idf,armada-ai\/esp-idf,MIhanguangyi\/esp-idf,shukyisme\/esp-idf-kwik,jaracil\/esp-idf,ajs124\/esp-idf","old_file":"components\/esp32\/ld\/esp32.ld","new_file":"components\/esp32\/ld\/esp32.ld","new_contents":"\/* ESP32 Linker Script Memory Layout\n\n   This file describes the memory layout (memory blocks) as virtual\n   memory addresses.\n\n   esp32.common.ld contains output sections to link compiler output\n   into these memory blocks.\n\n   ***\n\n   This linker script is passed through the C preprocessor to include\n   configuration options.\n\n   Please use preprocessor features sparingly! Restrict\n   to simple macros with numeric values, and\/or #if\/#endif blocks.\n*\/\n#include \"sdkconfig.h\"\n\n\/* If BT is not built at all *\/\n#ifndef CONFIG_BT_RESERVE_DRAM\n#define CONFIG_BT_RESERVE_DRAM 0\n#endif\n\nMEMORY\n{\n  \/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n  are connected to the data port of the CPU and eg allow bytewise access. *\/\n\n  \/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... *\/\n  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000\n\n  \/* Even though the segment name is iram, it is actually mapped to flash\n  *\/\n  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000-0x18\n\n  \/*\n    (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file\n    which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash\n    cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)\n  *\/\n\n\n  \/* Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n\n     Enabling Bluetooth & Trace Memory features in menuconfig will decrease\n     the amount of RAM available.\n  *\/\n  dram0_0_seg (RW) :                 org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,\n                                     len = 0x50000 - CONFIG_TRACEMEM_RESERVE_DRAM - CONFIG_BT_RESERVE_DRAM\n\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3F400018, len = 0x400000-0x18\n\n  \/* (See iram0_2_seg for meaning of 0x18 offset in the above.) *\/\n\n  \/* RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000\n\n  \/* RTC slow memory (data accessible). Persists over deep sleep.\n\n     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n  *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM\n}\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;\n","old_contents":"\/* ESP32 Linker Script Memory Layout\n\n   This file describes the memory layout (memory blocks) as virtual\n   memory addresses.\n\n   esp32.common.ld contains output sections to link compiler output\n   into these memory blocks.\n\n   ***\n\n   This linker script is passed through the C preprocessor to include\n   configuration options.\n\n   Please use preprocessor features sparingly! Restrict\n   to simple macros with numeric values, and\/or #if\/#endif blocks.\n*\/\n#include \"sdkconfig.h\"\n\nMEMORY\n{\n  \/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n  are connected to the data port of the CPU and eg allow bytewise access. *\/\n\n  \/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... *\/\n  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000\n\n  \/* Even though the segment name is iram, it is actually mapped to flash\n  *\/\n  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000-0x18\n\n  \/*\n    (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file\n    which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash\n    cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)\n  *\/\n\n\n  \/* Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n\n     Enabling Bluetooth & Trace Memory features in menuconfig will decrease\n     the amount of RAM available.\n  *\/\n  dram0_0_seg (RW) :                 org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,\n                                     len = 0x50000 - CONFIG_TRACEMEM_RESERVE_DRAM - CONFIG_BT_RESERVE_DRAM\n\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3F400018, len = 0x400000-0x18\n\n  \/* (See iram0_2_seg for meaning of 0x18 offset in the above.) *\/\n\n  \/* RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000\n\n  \/* RTC slow memory (data accessible). Persists over deep sleep.\n\n     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n  *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM\n}\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"29d88c6c73e837de160917d032fa4210fbc6422a","subject":"arch: arm: cortex-m: linker.ld: do not indent preprocessor directives","message":"arch: arm: cortex-m: linker.ld: do not indent preprocessor directives\n\nWe should not use indentation for pre-processor directives.\nThis commit fixes the indentation in the ARM Cortex-M linker\nscript.\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\n","repos":"finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n#define _DATA_IN_ROM __data_rom_start\n#else\n#define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_TI_CCFG_PRESENT\n#define CCFG_SIZE 88\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\tCCFG_SIZE)\n#define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n#ifdef DT_DTCM_BASE_ADDRESS\n    DTCM                  (rw) : ORIGIN = DT_DTCM_BASE_ADDRESS, LENGTH = DT_DTCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-text-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef DT_DTCM_BASE_ADDRESS\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_bss_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_data_end = .;\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif \/* DT_DTCM_BASE_ADDRESS *\/\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n#ifdef DT_DTCM_BASE_ADDRESS\n    DTCM                  (rw) : ORIGIN = DT_DTCM_BASE_ADDRESS, LENGTH = DT_DTCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-text-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef DT_DTCM_BASE_ADDRESS\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_bss_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_data_end = .;\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif \/* DT_DTCM_BASE_ADDRESS *\/\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ed347494514c314cb4efd12c245aa595303c7ae9","subject":"Set the default PHYS_OFFSET to 0x70000000","message":"Set the default PHYS_OFFSET to 0x70000000\n","repos":"virtualopensystems\/boot-wrapper,virtualopensystems\/boot-wrapper","old_file":"model.lds","new_file":"model.lds","new_contents":"\/*\n * boot.S - simple register setup code for stand-alone Linux booting\n *\n * Copyright (C) 2009 ARM Limited\n *\n * This program is free software; you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nTARGET(binary)\n\nINPUT(.\/uImage)\nINPUT(.\/filesystem.cpio.gz)\nINPUT(.\/boot.o)\n\nPHYS_OFFSET = 0x70000000;\n\nSECTIONS\n{\n\t. = PHYS_OFFSET;\n\t.text : { boot.o }\n\n\t. = PHYS_OFFSET + 0x8000 - 0x40;\n\tkernel = . + 0x40;\n\t.kernel : { .\/uImage }\n\n\t. = PHYS_OFFSET + 0x00800000;\n\tfilesystem = .;\n\t.filesystem : { .\/filesystem.cpio.gz }\n\tfs_size = . - filesystem;\n\n\t.data : { *(.data) }\n\t.bss : { *(.bss) }\n}\n","old_contents":"\/*\n * boot.S - simple register setup code for stand-alone Linux booting\n *\n * Copyright (C) 2009 ARM Limited\n *\n * This program is free software; you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nTARGET(binary)\n\nINPUT(.\/uImage)\nINPUT(.\/filesystem.cpio.gz)\nINPUT(.\/boot.o)\n\nPHYS_OFFSET = 0x00000000;\n\nSECTIONS\n{\n\t. = PHYS_OFFSET;\n\t.text : { boot.o }\n\n\t. = PHYS_OFFSET + 0x8000 - 0x40;\n\tkernel = . + 0x40;\n\t.kernel : { .\/uImage }\n\n\t. = PHYS_OFFSET + 0x00800000;\n\tfilesystem = .;\n\t.filesystem : { .\/filesystem.cpio.gz }\n\tfs_size = . - filesystem;\n\n\t.data : { *(.data) }\n\t.bss : { *(.bss) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"986000492d61f47a584e5d2ad89ce9cf73e4c0c8","subject":"stm32_common: Adjust ldscript memory segment attributes","message":"stm32_common: Adjust ldscript memory segment attributes\n","repos":"neiljay\/RIOT,OTAkeys\/RIOT,cladmi\/RIOT,BytesGalore\/RIOT,RIOT-OS\/RIOT,josephnoir\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,lazytech-org\/RIOT,basilfx\/RIOT,toonst\/RIOT,toonst\/RIOT,BytesGalore\/RIOT,x3ro\/RIOT,ant9000\/RIOT,A-Paul\/RIOT,A-Paul\/RIOT,kYc0o\/RIOT,mtausig\/RIOT,biboc\/RIOT,A-Paul\/RIOT,OlegHahm\/RIOT,BytesGalore\/RIOT,toonst\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,avmelnikoff\/RIOT,OlegHahm\/RIOT,cladmi\/RIOT,kYc0o\/RIOT,kbumsik\/RIOT,BytesGalore\/RIOT,biboc\/RIOT,gebart\/RIOT,josephnoir\/RIOT,lazytech-org\/RIOT,lazytech-org\/RIOT,kbumsik\/RIOT,x3ro\/RIOT,avmelnikoff\/RIOT,aeneby\/RIOT,mtausig\/RIOT,aeneby\/RIOT,cladmi\/RIOT,BytesGalore\/RIOT,kYc0o\/RIOT,biboc\/RIOT,smlng\/RIOT,OTAkeys\/RIOT,A-Paul\/RIOT,lazytech-org\/RIOT,neiljay\/RIOT,toonst\/RIOT,lazytech-org\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,avmelnikoff\/RIOT,authmillenon\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,cladmi\/RIOT,josephnoir\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,mfrey\/RIOT,ant9000\/RIOT,basilfx\/RIOT,basilfx\/RIOT,smlng\/RIOT,basilfx\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,rfuentess\/RIOT,miri64\/RIOT,cladmi\/RIOT,miri64\/RIOT,avmelnikoff\/RIOT,RIOT-OS\/RIOT,smlng\/RIOT,x3ro\/RIOT,neiljay\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,authmillenon\/RIOT,mtausig\/RIOT,mtausig\/RIOT,yogo1212\/RIOT,smlng\/RIOT,mtausig\/RIOT,yogo1212\/RIOT,aeneby\/RIOT,basilfx\/RIOT,ant9000\/RIOT,mfrey\/RIOT,josephnoir\/RIOT,neiljay\/RIOT,biboc\/RIOT,gebart\/RIOT,OTAkeys\/RIOT,toonst\/RIOT,RIOT-OS\/RIOT,kbumsik\/RIOT,smlng\/RIOT,rfuentess\/RIOT,kbumsik\/RIOT,biboc\/RIOT,gebart\/RIOT,A-Paul\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,kbumsik\/RIOT,aeneby\/RIOT,josephnoir\/RIOT,mfrey\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,neiljay\/RIOT,rfuentess\/RIOT,x3ro\/RIOT,yogo1212\/RIOT,avmelnikoff\/RIOT,aeneby\/RIOT,miri64\/RIOT,rfuentess\/RIOT,mfrey\/RIOT,miri64\/RIOT,rfuentess\/RIOT,mfrey\/RIOT,gebart\/RIOT,RIOT-OS\/RIOT,gebart\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,yogo1212\/RIOT","old_file":"cpu\/stm32_common\/ldscripts\/stm32_common.ld","new_file":"cpu\/stm32_common\/ldscripts\/stm32_common.ld","new_contents":"\/*\n * Copyright (C) 2017 Inria\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_cortexm_common\n * @{\n *\n * @file\n * @brief           Memory definitions for the Cortex-M family\n *\n * @author          Francisco Acosta <francisco.acosta@inria.fr>\n *\n * @}\n *\/\n\nccmram_length = DEFINED( ccmram_len ) ? ccmram_len : 0x0 ;\n\nMEMORY\n{\n    ccmram  : ORIGIN = 0x10000000, LENGTH = ccmram_length\n}\n\nINCLUDE cortexm.ld\n","old_contents":"\/*\n * Copyright (C) 2017 Inria\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_cortexm_common\n * @{\n *\n * @file\n * @brief           Memory definitions for the Cortex-M family\n *\n * @author          Francisco Acosta <francisco.acosta@inria.fr>\n *\n * @}\n *\/\n\nccmram_length = DEFINED( ccmram_len ) ? ccmram_len : 0x0 ;\n\nMEMORY\n{\n    ccmram (rwx): ORIGIN = 0x10000000, LENGTH = ccmram_length\n}\n\nINCLUDE cortexm.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"d6fd2fbdd038137838411d1ed41cf1b9d13f7161","subject":"Device: Fixed alignment and comments in GCC linker script for Armv8.1-M device.","message":"Device: Fixed alignment and comments in GCC linker script for Armv8.1-M device.\n\nChange-Id: Ie0dbc4ed6f08ce66a7e1e1003fb7d12dc49c4aa0\n","repos":"ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5","old_file":"Device\/ARM\/ARMv81MML\/Source\/GCC\/gcc_arm.ld","new_file":"Device\/ARM\/ARMv81MML\/Source\/GCC\/gcc_arm.ld","new_contents":"\/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.0.0\n * @date     08. May 2019\n ******************************************************************************\/\n\/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n \n\/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*\/\n\n\/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__ROM_BASE = 0x10000000;\n__ROM_SIZE = 0x00040000;\n\n\/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__RAM_BASE = 0x30000000;\n__RAM_SIZE = 0x00020000;\n\n\/*--------------------- Stack \/ Heap Configuration ---------------------------\n; <h> Stack \/ Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n\/*\n;-------------------- <<< end of configuration section >>> --------------------\n*\/\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.vectors))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\/* SG veneers:\n   All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   must be set, either with the command line option --section-start or in a linker script,\n   to indicate where to place these veneers in memory.\n *\/\n\/*\n    .gnu.sgstubs :\n    {\n        . = ALIGN(32);\n    } > FLASH\n*\/\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n    \/** Add each additional data section here *\/\n    \/*\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n    *\/\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n    \/** Add each additional bss section here *\/\n    \/* \n    LONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__) \n    *\/\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\n\t\/* Location counter can end up 2byte aligned with narrow Thumb code but\n\t   __etext is assumed by startup code to be the LMA of a section in RAM\n\t   which must be 4byte aligned *\/\n\t__etext = ALIGN (4);\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data)\n    *(.data.*)\n        \n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n  \/** \n   * Secondary data section, optional \n   * \n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   *\/\n  \/*\n  __etext2 = ALIGN (4);\n\n\t.data2 : AT (__etext2)\n\t{\n    . = ALIGN(4);\n\t\t__data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n\t\t. = ALIGN(4);\n\t\t__data2_end__ = .;\n\n\t} > RAM \n  *\/\n  \n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n    *(.bss)\n\t\t*(.bss.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n  \/**\n   * Secondary bss section, optional \n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   *\/\n  \/*\n\t.bss2 :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss2_start__ = .;\n    *(.bss2)\n\t\t*(.bss2.*)\n\t\t. = ALIGN(4);\n\t\t__bss2_end__ = .;\n\t} > RAM2\n  *\/\n\n\t.heap :\n\t{\n    . = ALIGN(4);\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t. = . + __HEAP_SIZE;\n    . = ALIGN(4);\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t.stack :\n\t{\n    . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE;\n    . = ALIGN(4);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(4);\n    __StackTop = .;\n\t} > RAM\n  PROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.0.0\n * @date     08. May 2019\n ******************************************************************************\/\n\/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n \n\/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*\/\n\n\/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__ROM_BASE = 0x10000000;\n__ROM_SIZE = 0x00040000;\n\n\/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__RAM_BASE = 0x30000000;\n__RAM_SIZE = 0x00020000;\n\n\/*--------------------- Stack \/ Heap Configuration ---------------------------\n; <h> Stack \/ Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n\/*\n;-------------------- <<< end of configuration section >>> --------------------\n*\/\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.vectors))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\/* SG veneers:\n   All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   must be set, either with the command line option --section-start or in a linker script,\n   to indicate where to place these veneers in memory.\n *\/\n\/*\n    .gnu.sgstubs :\n    {\n        . = ALIGN(32);\n    } > FLASH\n*\/\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n        \/** Add each additional data section here *\/\n        \/*\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n        *\/\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n        \/** Add each additional bss section here *\/\n        \/* \n  \t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__) \n        *\/\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\n\t\/* Location counter can end up 2byte aligned with narrow Thumb code but\n\t   __etext is assumed by startup code to be the LMA of a section in RAM\n\t   which must be 4byte aligned *\/\n\t__etext = ALIGN (4);\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data)\n        *(.data.*)\n        \n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n    \/** \n     * Secondary data section, optional \n     * \n     * Remember to add each additional data section\n     * to the .copy.table above to asure proper\n     * initialization during startup.\n     *\/\n    \/*\n    __etext2 = ALIGN (4);\n\n\t.data2 : AT (__etext2)\n\t{\n        . = ALIGN(4);\n\t\t__data2_start__ = .;\n        *(.data2)\n        *(.data2.*)\n\t\t. = ALIGN(4);\n\t\t__data2_end__ = .;\n\n\t} > RAM \n    *\/\n  \n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n        *(.bss)\n\t\t*(.bss.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n    \/**\n     * Secondary bss section, optional \n     *\n     * Remember to add each additional bss section\n     * to the .zero.table above to asure proper\n     * initialization during startup.\n     *\/\n    \/*\n\t.bss2 :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss2_start__ = .;\n        *(.bss2)\n\t\t*(.bss2.*)\n\t\t. = ALIGN(4);\n\t\t__bss2_end__ = .;\n\t} > RAM2\n    *\/\n\n\t.heap :\n\t{\n        . = ALIGN(4);\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t. = . + __HEAP_SIZE;\n        . = ALIGN(4);\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t.stack :\n\t{\n        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE;\n        . = ALIGN(4);\n        __StackLimit = .;\n        . = . + __STACK_SIZE;\n        . = ALIGN(4);\n        __StackTop = .;\n\t} > RAM\n    PROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"dc39bb6e394b0ae88bb1dc59bde87ad3e7e5e559","subject":"stm32\/boards\/stm32h743.ld: Enable D2 RAM and add eth-buffer section.","message":"stm32\/boards\/stm32h743.ld: Enable D2 RAM and add eth-buffer section.\n","repos":"pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython","old_file":"ports\/stm32\/boards\/stm32h743.ld","new_file":"ports\/stm32\/boards\/stm32h743.ld","new_contents":"\/*\n    GNU linker script for STM32H743\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 128K    \/* sector 0, 128K *\/\n    FLASH_FS (r)    : ORIGIN = 0x08020000, LENGTH = 128K    \/* sector 1, 128K *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K   \/* sectors 6*128 + 8*128 *\/\n    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    \/* Used for storage cache *\/\n    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 512K    \/* AXI SRAM *\/    \n    RAM_D2 (xrw)    : ORIGIN = 0x30000000, LENGTH = 288K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K; \/* tunable *\/\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n\n\/* Define output sections *\/\nSECTIONS\n{\n    .eth_buffers (NOLOAD) : {\n        . = ABSOLUTE(0x30040000);\n        *eth.o*(.bss.eth_dma)\n    } >RAM_D2\n}\n","old_contents":"\/*\n    GNU linker script for STM32H743\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 128K    \/* sector 0, 128K *\/\n    FLASH_FS (r)    : ORIGIN = 0x08020000, LENGTH = 128K    \/* sector 1, 128K *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K   \/* sectors 6*128 + 8*128 *\/\n    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    \/* Used for storage cache *\/\n    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 512K    \/* AXI SRAM *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K; \/* tunable *\/\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ea55a3b2bf0d89cc0c41a34cb0defde3ac7b1c2a","subject":"Removing commented out code","message":"Removing commented out code\n","repos":"jbw3\/OS,jbw3\/OS,jbw3\/OS,jbw3\/OS","old_file":"link.ld","new_file":"link.ld","new_contents":"\/* Link.ld\n * Linker script for the kernel.\n * Original file taken from Bran's Kernel Development\n * tutorials: http:\/\/www.osdever.net\/bkerndev\/index.php.\n *\/\n\nENTRY(start)\nSECTIONS\n{\n  .text 0x100000 :\n  {\n    code = .; _code = .; __code = .;\n    *(.text)\n    . = ALIGN(4096);\n  }\n\n  .data :\n  {\n     data = .; _data = .; __data = .;\n     *(.data)\n     *(.rodata)\n     . = ALIGN(4096);\n  }\n\n  .bss :\n  {\n    bss = .; _bss = .; __bss = .;\n    *(.bss)\n    . = ALIGN(4096);\n  }\n\n  end = .; _end = .; __end = .;\n}\n","old_contents":"\/* Link.ld -- Linker script for the kernel - ensure everything goes in the *\/\n\/*            Correct place.  *\/\n\/*            Original file taken from Bran's Kernel Development *\/\n\/*            tutorials: http:\/\/www.osdever.net\/bkerndev\/index.php. *\/\n\nENTRY(start)\nSECTIONS\n{\n  .text 0x100000 :\n  {\n    code = .; _code = .; __code = .;\n    *(.text)\n    . = ALIGN(4096);\n  }\n\n  .data :\n  {\n     data = .; _data = .; __data = .;\n     *(.data)\n     *(.rodata)\n     . = ALIGN(4096);\n  }\n\n  .bss :\n  {\n    bss = .; _bss = .; __bss = .;\n    *(.bss)\n    . = ALIGN(4096);\n  }\n\n  end = .; _end = .; __end = .;\n}\n\n\/*\nENTRY(start)\nSECTIONS {\n    . = 0x00100000;          \/* the code should be loaded at 1 MB *\n\n    .text ALIGN (0x1000) :   \/* align at 4 KB *\n    {\n        code = .;\n        *(.text)             \/* all text sections from all files *\n    }\n\n    .rodata ALIGN (0x1000) : \/* align at 4 KB *\n    {\n        *(.rodata*)          \/* all read-only data sections from all files *\n    }\n\n    .data ALIGN (0x1000) :   \/* align at 4 KB *\n    {\n        *(.data)             \/* all data sections from all files *\n    }\n\n    .bss ALIGN (0x1000) :    \/* align at 4 KB *\n    {\n        bss = .;\n        *(COMMON)            \/* all COMMON sections from all files *\n        *(.bss)              \/* all bss sections from all files *\n    }\n\n    end = .;\n}\n*\/\n\n\/*\nOUTPUT_FORMAT(\"binary\")\nENTRY(start)\nphys = 0x00100000;\nSECTIONS\n{\n  .text phys : AT(phys) {\n    code = .;\n    *(.text)\n    *(.rodata)\n    . = ALIGN(4096);\n  }\n  .data : AT(phys + (data - code))\n  {\n    data = .;\n    *(.data)\n    . = ALIGN(4096);\n  }\n  .bss : AT(phys + (bss - code))\n  {\n    bss = .;\n    *(.bss)\n    . = ALIGN(4096);\n  }\n  end = .;\n}\n*\/\n\n\/*\nENTRY(start)\nSECTIONS\n{\n  .text 0x100000 :\n  {\n    code = .; _code = .; __code = .;\n    *(.text)\n    . = ALIGN(4096);\n  }\n\n  .data :\n  {\n     data = .; _data = .; __data = .;\n     *(.data)\n     *(.rodata*)\n     . = ALIGN(4096);\n  }\n\n  .bss :\n  {\n    bss = .; _bss = .; __bss = .;\n    *(.bss)\n    . = ALIGN(4096);\n  }\n\n  end = .; _end = .; __end = .;\n  . = ALIGN(4096);\n}\n*\/\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4b4c63f5cff7b8dbe2aa3571f9b7d0df97b5ff58","subject":"Resotre the linker script to utilize the entire memory","message":"Resotre the linker script to utilize the entire memory\n","repos":"gregwym\/ARM-Micro-Kernel,gregwym\/ARM-Micro-Kernel,gregwym\/ARM-Micro-Kernel","old_file":"orex.ld","new_file":"orex.ld","new_contents":"ENTRY (main)\n\nMEMORY\n{\nram : ORIGIN = 0x00000000, LENGTH = 32M\nrom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\ndata : \/* Initialized data. *\/\n{\n_DataStart = . ;\n*(.data)\n_DataEnd = . ;\n} >ram\n\nbss : \/* Uninitialized data. *\/\n{\n_BssStart = . ;\n*(.bss)\n_BssEnd = . ;\n} >ram\n\ntext : \/* The actual instructions. *\/\n{\n*(.text)\n*(.got)\n*(.got.plt)\n*(.rodata)\n*(.glue_7)\n*(.glue_7t)\n} >ram\n}\n","old_contents":"ENTRY (main)\n\nMEMORY\n{\nram : ORIGIN = 0x00001024, LENGTH = 30M\nrom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\ndata : \/* Initialized data. *\/\n{\n_DataStart = . ;\n*(.data)\n_DataEnd = . ;\n} >ram\n\nbss : \/* Uninitialized data. *\/\n{\n_BssStart = . ;\n*(.bss)\n_BssEnd = . ;\n} >ram\n\ntext : \/* The actual instructions. *\/\n{\n*(.text)\n*(.got)\n*(.got.plt)\n*(.rodata)\n*(.glue_7)\n*(.glue_7t)\n} >ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7f0f0b30d3eee87503b732cd639805f6fd094646","subject":"linker scripts: Re-align at \":\"","message":"linker scripts: Re-align at \":\"\n\nWith \"git show -b\" you can verify that this is a whitespace only change\nbecause the diff will be empty.\n","repos":"adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython","old_file":"ports\/litex\/boards\/fomu\/fomu-spi.ld","new_file":"ports\/litex\/boards\/fomu\/fomu-spi.ld","new_contents":"\/*\n    GNU linker script for Fomu\n*\/\n\nENTRY(_start)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)               : ORIGIN = 0x20040000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_FIRMWARE (rx)      : ORIGIN = 0x20040000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    RAM (xrw)                : ORIGIN = 0x10000000, LENGTH = 0x00020000 \/* 128 KiB *\/\n}\n\n\/* top end of the stack *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :  AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n\n        *(.itcm.*)         \/* Instruction Tightly Coupled Memory *\/\n        *(.dtcm_data.*)    \/* Data Tightly Coupled Memory *\/\n\n        *(.text.cmp_lfn)\n        *(.text.qstr_find_strn)\n        *(.text.dcd_edpt_xfer)\n        *(.text.pop_rule)\n        *(.text.ff_wtoupper)\n        *(.text.dir_find)\n        *(.text.push_rule)\n        *(.text.csr_writel)\n        *(.text.csr_readl)\n        *(.text.timer0_ev_pending_write)\n        *(.text.autoreload_tick)\n        *(.text.filesystem_tick)\n        *(.text.usb_background)\n\n        *(.text.dcd_*)\n        *(.text.tud_control_*)\n        *(.text.tud_cdc_n_write_flush)\n        *(.text.tud_task)\n        *(.text.tu_edpt_dir)\n        *(.text.tu_fifo_empty)\n        *(.text.usbd_edpt_busy)\n        *(.text.irq_getmask)\n        *(.text.irq_setmask)\n        *(.text.irq_pending)\n        *(.text._osal_q_lock)\n        *(.text.osal_queue_receive)\n\n        *(.text.mp_obj_get_type)\n        *(.text.mp_parse)\n        *(.text.parse_compile_execute)\n        *(.text.mp_map_lookup)\n        *(.text.mp_execute_bytecode) \/* Note: this function is 7kb *\/\n\n        *(.ramtext)        \/* .text* sections (code) *\/\n        *(.ramtext*)       \/* .text* sections (code) *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n        *(.sdata)          \/* .data sections *\/\n        *(.sdata*)         \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* The program code and other data goes into FLASH_FIRMWARE *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.text.start)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        *(.srodata)        \/* .rodata sections (constants, strings, etc.) *\/\n        *(.srodata*)       \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH_FIRMWARE\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(.dtcm_bss.*)     \/* Data Tightly Coupled Memory *\/\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n    } >RAM\n}\n","old_contents":"\/*\n    GNU linker script for Fomu\n*\/\n\nENTRY(_start)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x20040000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_FIRMWARE (rx)      : ORIGIN = 0x20040000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    RAM (xrw)       : ORIGIN = 0x10000000, LENGTH = 0x00020000 \/* 128 KiB *\/\n}\n\n\/* top end of the stack *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :  AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n\n        *(.itcm.*)         \/* Instruction Tightly Coupled Memory *\/\n        *(.dtcm_data.*)    \/* Data Tightly Coupled Memory *\/\n\n        *(.text.cmp_lfn)\n        *(.text.qstr_find_strn)\n        *(.text.dcd_edpt_xfer)\n        *(.text.pop_rule)\n        *(.text.ff_wtoupper)\n        *(.text.dir_find)\n        *(.text.push_rule)\n        *(.text.csr_writel)\n        *(.text.csr_readl)\n        *(.text.timer0_ev_pending_write)\n        *(.text.autoreload_tick)\n        *(.text.filesystem_tick)\n        *(.text.usb_background)\n\n        *(.text.dcd_*)\n        *(.text.tud_control_*)\n        *(.text.tud_cdc_n_write_flush)\n        *(.text.tud_task)\n        *(.text.tu_edpt_dir)\n        *(.text.tu_fifo_empty)\n        *(.text.usbd_edpt_busy)\n        *(.text.irq_getmask)\n        *(.text.irq_setmask)\n        *(.text.irq_pending)\n        *(.text._osal_q_lock)\n        *(.text.osal_queue_receive)\n\n        *(.text.mp_obj_get_type)\n        *(.text.mp_parse)\n        *(.text.parse_compile_execute)\n        *(.text.mp_map_lookup)\n        *(.text.mp_execute_bytecode) \/* Note: this function is 7kb *\/\n\n        *(.ramtext)        \/* .text* sections (code) *\/\n        *(.ramtext*)       \/* .text* sections (code) *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n        *(.sdata)          \/* .data sections *\/\n        *(.sdata*)         \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* The program code and other data goes into FLASH_FIRMWARE *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.text.start)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        *(.srodata)        \/* .rodata sections (constants, strings, etc.) *\/\n        *(.srodata*)       \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH_FIRMWARE\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(.dtcm_bss.*)     \/* Data Tightly Coupled Memory *\/\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n    } >RAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a2aac528f49a4203eb50b72d2ac2df481d783295","subject":"[M2351] Update GCC linker for NSC Veneer","message":"[M2351] Update GCC linker for NSC Veneer\n","repos":"mbedmicro\/mbed,betzw\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed,betzw\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,c1728p9\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,mbedmicro\/mbed,betzw\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,betzw\/mbed-os,c1728p9\/mbed-os,betzw\/mbed-os,c1728p9\/mbed-os,betzw\/mbed-os,kjbracey-arm\/mbed","old_file":"targets\/TARGET_NUVOTON\/TARGET_M2351\/device\/TOOLCHAIN_GCC_ARM\/M2351.ld","new_file":"targets\/TARGET_NUVOTON\/TARGET_M2351\/device\/TOOLCHAIN_GCC_ARM\/M2351.ld","new_contents":"\/*\n * Nuvoton M2351 GCC linker script file\n *\/\n\nStackSize = 0x800;\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x0003F0000 - 0x00000400\n  NSC_FLASH (rx)        : ORIGIN = 0x0003F000, LENGTH = 0x00080000 - 0x0003F000\n  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00018000 - 0x00000000\n}\n\n\/**\n * Must match cmsis_nvic.h\n *\/\n__vector_size = 4 * (16 + 102);\n\n \n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    \n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        \/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. *\/\n        . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));\n        __uvisor_bss_end = .;\n    } > RAM_INTERN\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    \/* Veneer$$CMSE : *\/\n    .gnu.sgstubs :\n    {\n       __sgstubs_start = .;\n        *(.gnu.sgstubs.*)\n       __sgstubs_end = .;    \n    } > NSC_FLASH \n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += StackSize - (. - __StackLimit);\n    } > RAM_INTERN\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Relocate vector table in SRAM *\/\n    .isr_vector.reloc (NOLOAD) :\n    {\n        . = ALIGN(1 << LOG2CEIL(__vector_size));\n        PROVIDE(__start_vector_table__ = .);\n        . += __vector_size;\n        PROVIDE(__end_vector_table__ = .);\n    } > RAM_INTERN\n    \n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM_INTERN AT>FLASH\n\n    \/* uvisor configuration data *\/   \n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assertions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM_INTERN\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM_INTERN\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);\n        __HeapLimit = .;\n    } > RAM_INTERN\n\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* Provide physical memory boundaries for uVisor. *\/    \n    __uvisor_flash_start = ORIGIN(VECTORS);\n    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n    __uvisor_sram_start = ORIGIN(RAM_INTERN);\n    __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);\n    \n}\n","old_contents":"\/*\n * Nuvoton M2351 GCC linker script file\n *\/\n\nStackSize = 0x800;\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400\n  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00018000 - 0x00000000\n}\n\n\/**\n * Must match cmsis_nvic.h\n *\/\n__vector_size = 4 * (16 + 102);\n\n \n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        \/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. *\/\n        . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));\n        __uvisor_bss_end = .;\n    } > RAM_INTERN\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += StackSize - (. - __StackLimit);\n    } > RAM_INTERN\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Relocate vector table in SRAM *\/\n    .isr_vector.reloc (NOLOAD) :\n    {\n        . = ALIGN(1 << LOG2CEIL(__vector_size));\n        PROVIDE(__start_vector_table__ = .);\n        . += __vector_size;\n        PROVIDE(__end_vector_table__ = .);\n    } > RAM_INTERN\n    \n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM_INTERN AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assertions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM_INTERN\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM_INTERN\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);\n        __HeapLimit = .;\n    } > RAM_INTERN\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* Provide physical memory boundaries for uVisor. *\/\n    __uvisor_flash_start = ORIGIN(VECTORS);\n    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n    __uvisor_sram_start = ORIGIN(RAM_INTERN);\n    __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4566241849255ee5fae0a2467ff374a3d3d40ce0","subject":"Ublox: Fix alignment of execute region to 8-byte boundary","message":"Ublox: Fix alignment of execute region to 8-byte boundary\n\n--legacyalign, --no_legacyalign are deprecated from ARMC6 compiler, in order to\nremove deprecated flags all linker files (GCC and IAR as well to have uniformity)\nshould strictly align to 8-byte boundary\n","repos":"mbedmicro\/mbed,c1728p9\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os,kjbracey-arm\/mbed,andcor02\/mbed-os,c1728p9\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed","old_file":"targets\/TARGET_ublox\/TARGET_HI2110\/device\/TOOLCHAIN_GCC_ARM\/hi2110.ld","new_file":"targets\/TARGET_ublox\/TARGET_HI2110\/device\/TOOLCHAIN_GCC_ARM\/hi2110.ld","new_contents":"\/* mbed Microcontroller Library *\/\n\/* Copyright (c) 2016 u-blox. *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(Reset_Handler)\nMEMORY\n{\n    FLASH_VECTORS : ORIGIN = 0, LENGTH = 192\n    FLASH : ORIGIN = (0 + 192), LENGTH = (0x20000 - 192)\n    RAM_VECTORS : ORIGIN = 0, LENGTH = 128 \/* Reserve space for dynamic vectors mapped to RAM (see cmsis_nvic.c) *\/\n    RAM : ORIGIN = 0x01000000 + 128, LENGTH = 0x5000 - 256\n    IPC_MAILBOX : ORIGIN = (0x01000000 + 128 + 0x5000 - 256), LENGTH = 256\n}\nSECTIONS\n{\n    \/* Vector table in FLASH *\/\n    . = 0;\n    startup :\n    {\n        KEEP (*(.isr_vector))\n    } > FLASH_VECTORS\n    \n    \/* Code and const data *\/\n    .text :\n    {\n        . = ALIGN(8);\n        *(.text)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata)\n        *(.rodata*)\n        \n        KEEP(*(.eh_frame*))\n    } > FLASH\n    \n    .ARM.exidx :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > FLASH\n    \n    __etext = .;\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n    \n    __RAM_START__ = ORIGIN(RAM);\n    __RAM_SIZE__ = LENGTH(RAM);\n    \n    \/* Initialised data *\/\n    .data :\n    {\n        FILL(0xFF)\n        __data_load__ = LOADADDR(.data);\n        __data_start__ = .;\n        *(.data)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n        \n        __data_end__ = .;\n    } > RAM AT > FLASH\n    \n    __data_size__ = __data_end__ - __data_start__;\n    \n    \/* Uninitialised data *\/\n    .bss (NOLOAD):\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n    } > RAM\n    \n    __bss_size__ = __bss_end__ - __bss_start__;\n    \n    .resume (NOLOAD):\n    {\n        . = ALIGN(8);\n        *(preserve)\n    } > RAM\n\n    \/* Heap fills the rest of the space up to the start of the stack *\/\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        __HeapBase = .;\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - Stack_Size; \/* Remember that LENGTH(RAM) is already reduced by the IPC block *\/\n        __HeapLimit = .;\n    } > RAM\n\n    PROVIDE(__heap_start = ADDR(.heap));\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n        \n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (NOLOAD):\n    {\n        __SYSTEM_STACK_START__ = .;\n        *(.stack*)\n        __SYSTEM_STACK_END__ = .;\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM); \/* Remember that LENGTH(RAM) is already reduced by the IPC block *\/\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n    \/* IPC mailboxes at the top of RAM *\/\n    \/* The size of this section (256 bytes) is already taken off the size of RAM so there is no danger of the heap overflowing into it *\/\n    .ipc_mailbox (NOLOAD):\n    {\n        . = ALIGN(8);\n        __ipc_mailbox_start__ = .;\n        *(.ipc_mailbox)\n        *(.ipc_mailbox*)\n        __ipc_mailbox_end__ = .;\n    } > IPC_MAILBOX\n}","old_contents":"\/* mbed Microcontroller Library *\/\n\/* Copyright (c) 2016 u-blox. *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(Reset_Handler)\nMEMORY\n{\n    FLASH_VECTORS : ORIGIN = 0, LENGTH = 192\n    FLASH : ORIGIN = (0 + 192), LENGTH = (0x20000 - 192)\n    RAM_VECTORS : ORIGIN = 0, LENGTH = 128 \/* Reserve space for dynamic vectors mapped to RAM (see cmsis_nvic.c) *\/\n    RAM : ORIGIN = 0x01000000 + 128, LENGTH = 0x5000 - 256\n    IPC_MAILBOX : ORIGIN = (0x01000000 + 128 + 0x5000 - 256), LENGTH = 256\n}\nSECTIONS\n{\n    \/* Vector table in FLASH *\/\n    . = 0;\n    startup :\n    {\n        KEEP (*(.isr_vector))\n    } > FLASH_VECTORS\n    \n    \/* Code and const data *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata)\n        *(.rodata*)\n        \n        KEEP(*(.eh_frame*))\n    } > FLASH\n    \n    .ARM.exidx :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > FLASH\n    \n    __etext = .;\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n    \n    __RAM_START__ = ORIGIN(RAM);\n    __RAM_SIZE__ = LENGTH(RAM);\n    \n    \/* Initialised data *\/\n    .data :\n    {\n        FILL(0xFF)\n        __data_load__ = LOADADDR(.data);\n        __data_start__ = .;\n        *(.data)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n        \n        __data_end__ = .;\n    } > RAM AT > FLASH\n    \n    __data_size__ = __data_end__ - __data_start__;\n    \n    \/* Uninitialised data *\/\n    .bss (NOLOAD):\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    \n    __bss_size__ = __bss_end__ - __bss_start__;\n    \n    .resume (NOLOAD):\n    {\n        . = ALIGN(4);\n        *(preserve)\n    } > RAM\n\n    \/* Heap fills the rest of the space up to the start of the stack *\/\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        __HeapBase = .;\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - Stack_Size; \/* Remember that LENGTH(RAM) is already reduced by the IPC block *\/\n        __HeapLimit = .;\n    } > RAM\n\n    PROVIDE(__heap_start = ADDR(.heap));\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n        \n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (NOLOAD):\n    {\n        __SYSTEM_STACK_START__ = .;\n        *(.stack*)\n        __SYSTEM_STACK_END__ = .;\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM); \/* Remember that LENGTH(RAM) is already reduced by the IPC block *\/\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n    \/* IPC mailboxes at the top of RAM *\/\n    \/* The size of this section (256 bytes) is already taken off the size of RAM so there is no danger of the heap overflowing into it *\/\n    .ipc_mailbox (NOLOAD):\n    {\n        . = ALIGN(4);\n        __ipc_mailbox_start__ = .;\n        *(.ipc_mailbox)\n        *(.ipc_mailbox*)\n        __ipc_mailbox_end__ = .;\n    } > IPC_MAILBOX\n}","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6baedbf80ae8f61bf969a673612578aaec096ac2","subject":"added src folder by accident, removed it again","message":"added src folder by accident, removed it again\n","repos":"prozum\/z-kernel,prozum\/z-kernel","old_file":"src\/link.ld","new_file":"src\/link.ld","new_contents":"","old_contents":"ENTRY(loader)                \/* the name of the entry label *\/\n\nSECTIONS {\n    . = 0x00100000;          \/* the code should be loaded at 1 MB *\/\n\n    .text ALIGN (0x1000) :   \/* align at 4 KB *\/\n    {\n        *(.text)             \/* all text sections from all files *\/\n    }\n\n    .rodata ALIGN (0x1000) : \/* align at 4 KB *\/\n    {\n        *(.rodata*)          \/* all read-only data sections from all files *\/\n    }\n\n    .data ALIGN (0x1000) :   \/* align at 4 KB *\/\n    {\n        *(.data)             \/* all data sections from all files *\/\n    }\n\n    .bss ALIGN (0x1000) :    \/* align at 4 KB *\/\n    {\n        *(COMMON)            \/* all COMMON sections from all files *\/\n        *(.bss)              \/* all bss sections from all files *\/\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"885b4ccbef4f166c05784e01332a0d89f20c8130","subject":"rtl8195am - cleanup gcc linker script","message":"rtl8195am - cleanup gcc linker script\n\nSigned-off-by: Tony Wu <7d96f1423e8ab604e1604a0ea55fe51a076a8533@realtek.com>\n","repos":"mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed","old_file":"targets\/TARGET_Realtek\/TARGET_AMEBA\/TARGET_MCU_RTL8195A\/device\/TOOLCHAIN_GCC_ARM\/rtl8195a.ld","new_file":"targets\/TARGET_Realtek\/TARGET_AMEBA\/TARGET_MCU_RTL8195A\/device\/TOOLCHAIN_GCC_ARM\/rtl8195a.ld","new_contents":"\/*\n * Copyright (c) 2013-2016 Realtek Semiconductor Corp.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nINCLUDE \"rtl8195a_rom.h\"\n\/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).\n   But we can put .data\/.bss of Image2 in this region *\/\nMEMORY\n{\n  TCM (rwx)        : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  DATA_RAM (rwx)   : ORIGIN = 0x10002100, LENGTH = 0x10007000 - 0x10002100\n  SRAM1 (rwx)      : ORIGIN = 0x10007000, LENGTH = 0x10070000 - 0x10007000\n  SRAM2 (rwx)      : ORIGIN = 0x30000000, LENGTH = 2M\n}\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\n\/* Stack sizes: *\/\nStackSize = MBED_BOOT_STACK_SIZE;\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .image2.table :\n    {\n        KEEP(*(SORT(.image2.ram.data*)))\n        KEEP(*(.image2.validate.rodata*))\n    } > SRAM2\n\n    .text.sram1 :\n    {\n        . = ALIGN(8);\n        *rtl8195a_crypto*.o (.text* .rodata*)\n        *mbedtls*.o (.text* .rodata*)\n        *libc.a: (.text* .rodata*)\n        *lib_peripheral_mbed_gcc.a: (.text* .rodata*)\n        *_api*.o (.text* .rodata*)\n        *main*.o (.text* .rodata*)\n    } > SRAM1\n\n    .text.sram2 :\n    {\n        . = ALIGN(8);\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > SRAM2\n    __etext = .;\n\n    .data.sram1 :\n    {\n        . = ALIGN(4);\n        __data_start__ = .;\n        __sram_data_start__ = .;\n        *rtl8195a_crypto*.o (.data*)\n        *mbedtls*.o (.data*)\n        __data_end__ = .;\n        __sram_data_end__ = .;\n    } > SRAM1\n\n    .data.sram2 :\n    {\n        __dram_data_start__ = .;\n        *(vtable)\n        *(.data*)\n        *(.sdram.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        __dram_data_end__ = .;\n    } > SRAM2\n    __image2_end__ = .;\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > SRAM2\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > SRAM2\n    __exidx_end = .;\n\n    .bss.sram1 (NOLOAD) :\n    {\n        __bss_start__ = .;\n        __bss_sram_start__ = .;\n        *rtl8195a_crypto*.o (.bss* COMMON)\n        *mbedtls*.o (.bss* COMMON)\n        *(.bss.thread_stack_main)\n        *lib_peripheral_mbed_gcc.a: (.bss* COMMON)\n        *mbed_boot*.o (.bss* COMMON)\n        __bss_sram_end__ = .;\n        __bss_end__ = .;\n    } > SRAM1\n\n    .bss.sram2 (NOLOAD) :\n    {\n        __bss_dram_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        *(.bdsram.data*)\n        __bss_dram_end__ = .;\n    } > SRAM2\n\n    .bf_data :\n    {\n        __buffer_data_start__ = .;\n        *(.bfsram.data*)\n        __buffer_data_end__ = .;\n    } > SRAM2\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;\n        __HeapLimit = .;\n    } > SRAM1\n    \n    .TCM_overlay (NOLOAD):\n    {\n        __bss_dtcm_start__ = .;\n        *lwip_mem*.o (.bss* COMMON)\n        *lwip_memp*.o (.bss* COMMON)\n        *(.tcm.heap*)\n        __bss_dtcm_end__ = .;\n    } > TCM\n    \n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack)\n        . += StackSize - (. - __StackLimit);\n    } > SRAM1\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);\n    __StackLimit = __StackTop - StackSize;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if reserved stack size is too small *\/\n    ASSERT(StackSize >= SIZEOF(.stack_dummy), \"reserved stack size is too small\")\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM exceeds ram limit\")\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2016 Realtek Semiconductor Corp.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nINCLUDE \"rtl8195a_rom.h\"\n\/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).\n   But we can put .data\/.bss of Image2 in this region *\/\nMEMORY\n{\n  TCM (rwx)        : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  DATA_RAM (rwx)   : ORIGIN = 0x10002100, LENGTH = 0x10007000 - 0x10002100\n  SRAM1 (rwx)      : ORIGIN = 0x10007000, LENGTH = 0x10070000 - 0x10007000\n  SRAM2 (rwx)      : ORIGIN = 0x30000000, LENGTH = 2M\n}\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\n\/* Stack sizes: *\/\nStackSize = MBED_BOOT_STACK_SIZE;\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .image2.table :\n    {\n        KEEP(*(SORT(.image2.ram.data*)))\n        KEEP(*(.image2.validate.rodata*))\n    } > SRAM2\n\n    .text.sram1 :\n    {\n        . = ALIGN(8);\n        *rtl8195a_crypto*.o (.text* .rodata*)\n        *mbedtls*.o (.text* .rodata*)\n        *libc.a: (.text* .rodata*)\n        *lib_peripheral_mbed_gcc.a: (.text* .rodata*)\n        *_api*.o (.text* .rodata*)\n        *main*.o (.text* .rodata*)\n    } > SRAM1\n\n    .text.sram2 :\n    {\n        . = ALIGN(8);\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > SRAM2\n    __etext = .;\n\n    __data_start__ = .;\n\n    .data.sram1 :\n    {\n        . = ALIGN(8);\n        __sram_data_start__ = .;\n        *rtl8195a_crypto*.o (.data*)\n        *mbedtls*.o (.data*)\n        __sram_data_end__ = .;\n    } > SRAM1\n\n    .data.sram2 :\n    {\n        __sdram_data_start__ = .;\n        *(vtable)\n        *(.data*)\n        *(.sdram.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(8);\n\n        __sdram_data_end__ = .;\n        \/* All data end *\/\n    } > SRAM2\n    __data_end__ = .;\n    __image2_end__ = .;\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > SRAM2\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > SRAM2\n    __exidx_end = .;\n\n    .bss.sram1 (NOLOAD) :\n    {\n        __bss_sram_start__ = .;\n        *rtl8195a_crypto*.o (.bss* COMMON)\n        *mbedtls*.o (.bss* COMMON)\n        *(.bss.thread_stack_main)\n        *lib_peripheral_mbed_gcc.a: (.bss* COMMON)\n        *mbed_boot*.o (.bss* COMMON)\n        __bss_sram_end__ = .;\n    } > SRAM1\n\n    .bss.sram2 (NOLOAD) :\n    {\n        __bss_start__ = .;\n        __bss_dram_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        *(.bdsram.data*)\n        __bss_dram_end__ = .;\n        __bss_end__ = .;\n    } > SRAM2\n\n    .bf_data :\n    {\n        __buffer_data_start__ = .;\n        *(.bfsram.data*)\n        __buffer_data_end__ = .;\n    } > SRAM2\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n    . = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;\n        __HeapLimit = .;\n    } > SRAM1\n    \n    .TCM_overlay (NOLOAD):\n    {\n        __bss_dtcm_start__ = .;\n        *lwip_mem*.o (.bss* COMMON)\n        *lwip_memp*.o (.bss* COMMON)\n        *(.tcm.heap*)\n        __bss_dtcm_end__ = .;\n    } > TCM\n    \n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack)\n    . += StackSize - (. - __StackLimit);\n    } > SRAM1\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);\n    __StackLimit = __StackTop - StackSize;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM exceeds ram limit\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"26a1c4520cbb66f1ffed70cba5cffd5c4b1b2446","subject":"Hotel: Fixup linker script's data segment","message":"Hotel: Fixup linker script's data segment\n\nI'm not totally sure why adding `ALIGN(4)` before _edata ensures it\nactually capsures the data segment, but without these magic changes,\n_edata ends up equaling _sdata.\n","repos":"google\/tock-on-titan,google\/tock-on-titan,google\/tock-on-titan","old_file":"src\/chips\/hotel\/linker.ld","new_file":"src\/chips\/hotel\/linker.ld","new_contents":"MEMORY {\n        rom (rx): ORIGIN = 0x44400 LENGTH = 60K\n        ram (w):  ORIGIN = 0x10000 LENGTH = 64K\n}\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\nSECTIONS {\n  .text : {\n    KEEP(*(.vectors))\n    *(.text)\n\n    . = ALIGN(8K);\n    _sapps = .;\n    KEEP(*(.app.*))\n    KEEP(*(.endapp))\n  } > rom\n\n  \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n  PROVIDE_HIDDEN (__exidx_start = .);\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > rom\n  PROVIDE_HIDDEN (__exidx_end = .);\n\n  .rodata : {\n    *(.rodata*)\n  } > rom\n\n  _ero = .;\n\n  .data : AT(_ero) {\n    . = ALIGN(4);\n    _sdata = .;\n    *(.data .data.*)\n    . = ALIGN(4);\n    _edata = .;\n  } > ram\n\n  .bss (NOLOAD) : {\n    . = ALIGN(4);\n    _sbss = .;\n    *(.bss .bss.*)\n    _ebss = .;\n\n    _sstack = .;\n    . = . + __stack_size__;\n    . = ALIGN(8);\n    _estack = .;\n\n    . = ALIGN(8K);\n    *(.app_memory)\n  } > ram\n\n}\n","old_contents":"MEMORY {\n        rom (rx): ORIGIN = 0x44400 LENGTH = 60K\n        ram (w):  ORIGIN = 0x10000 LENGTH = 64K\n}\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\nSECTIONS {\n  .text : {\n    KEEP(*(.vectors))\n    *(.text)\n\n    . = ALIGN(8K);\n    _sapps = .;\n    KEEP(*(.app.*))\n    KEEP(*(.endapp))\n  } > rom\n\n  .rodata : {\n    *(.rodata*)\n  } > rom\n\n  _ero = .;\n\n  .data : AT(_ero) {\n    . = ALIGN(4);\n    _sdata = .;\n    *(.data)\n    _edata = .;\n  } > ram\n\n  .bss (NOLOAD) : {\n    . = ALIGN(4);\n    _sbss = .;\n    *(.bss .bss.*)\n    _ebss = .;\n\n    _sstack = .;\n    . = . + __stack_size__;\n    . = ALIGN(8);\n    _estack = .;\n\n    . = ALIGN(8K);\n    *(.app_memory)\n  } > ram\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"989d823ab9c1f02ad89e3715600123ab00b211b3","subject":"Troy's changes","message":"Troy's changes\n","repos":"boundarydevices\/imx_usb_loader,bwalle\/imx_usb_loader,vstehle\/imx_usb_loader,pacificIT\/imx_usb_loader,Adellica\/imx_usb_loader,lucaceresoli\/imx_usb_loader","old_file":"imx_usb.lds","new_file":"imx_usb.lds","new_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\",\n\t      \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\"\/usr\/i486-linux-gnu\/lib32\"); SEARCH_DIR(\"\/usr\/local\/lib32\"); SEARCH_DIR(\"\/lib32\"); SEARCH_DIR(\"\/usr\/lib32\"); SEARCH_DIR(\"\/usr\/i486-linux-gnu\/lib\"); SEARCH_DIR(\"\/usr\/local\/lib\"); SEARCH_DIR(\"\/lib\"); SEARCH_DIR(\"\/usr\/lib\");\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = SEGMENT_START(\"text-segment\", 0x08048000)); . = SEGMENT_START(\"text-segment\", 0x08048000) + SIZEOF_HEADERS;\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n      *(.rel.ifunc)\n    }\n  .rel.plt        :\n    {\n      *(.rel.plt)\n      PROVIDE_HIDDEN (__rel_iplt_start = .);\n      *(.rel.iplt)\n      PROVIDE_HIDDEN (__rel_iplt_end = .);\n    }\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0x90909090\n  .plt            : { *(.plt) *(.iplt) }\n  .text           :\n  {\n    *(.text.unlikely .text.*_unlikely)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } =0x90909090\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0x90909090\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n  .init_array     :\n  {\n     PROVIDE_HIDDEN (__init_array_start = .);\n     KEEP (*(SORT(.init_array.*)))\n     KEEP (*(.init_array))\n     PROVIDE_HIDDEN (__init_array_end = .);\n  }\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  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{"commit":"eb9d12423092c762ef4b7320386c8658f1a3dad9","subject":"K64F: Add uVisor sections to the linker script","message":"K64F: Add uVisor sections to the linker script\n\nThis commit includes all sections that are just added to the linker\nscript. These changes are backwards-compatible, meaning that they will\nnot affect the existing code.\n\nTargets that do not support uVisor will leave those sections empty.\n","repos":"screamerbg\/mbed,bcostm\/mbed-os,YarivCol\/mbed-os,NXPmicro\/mbed,ryankurte\/mbed-os,arostm\/mbed-os,bulislaw\/mbed-os,jeremybrodt\/mbed,infinnovation\/mbed-os,infinnovation\/mbed-os,NXPmicro\/mbed,CalSol\/mbed,CalSol\/mbed,mbedmicro\/mbed,Archcady\/mbed-os,svastm\/mbed,tung7970\/mbed-os,adamgreen\/mbed,kl-cruz\/mbed-os,YarivCol\/mbed-os,bulislaw\/mbed-os,c1728p9\/mbed-os,svogl\/mbed-os,nvlsianpu\/mbed,catiedev\/mbed-os,Archcady\/mbed-os,netzimme\/mbed-os,andcor02\/mbed-os,maximmbed\/mbed,mikaleppanen\/mbed-os,bulislaw\/mbed-os,CalSol\/mbed,fanghuaqi\/mbed,betzw\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,tung7970\/mbed-os,fvincenzo\/mbed-os,svogl\/mbed-os,cvtsi2sd\/mbed-os,tung7970\/mbed-os,arostm\/mbed-os,svastm\/mbed,mikaleppanen\/mbed-os,betzw\/mbed-os,monkiineko\/mbed-os,fanghuaqi\/mbed,YarivCol\/mbed-os,tung7970\/mbed-os-1,mbedmicro\/mbed,catiedev\/mbed-os,karsev\/mbed-os,c1728p9\/mbed-os,ryankurte\/mbed-os,fvincenzo\/mbed-os,bcostm\/mbed-os,mazimkhan\/mbed-os,theotherjimmy\/mbed,netzimme\/mbed-os,theotherjimmy\/mbed,RonEld\/mbed,infinnovation\/mbed-os,betzw\/mbed-os,fvincenzo\/mbed-os,NXPmicro\/mbed,CalSol\/mbed,kjbracey-arm\/mbed,pradeep-gr\/mbed-os5-onsemi,maximmbed\/mbed,RonEld\/mbed,tung7970\/mbed-os,j-greffe\/mbed-os,betzw\/mbed-os,geky\/mbed,bcostm\/mbed-os,mmorenobarm\/mbed-os,nvlsianpu\/mbed,nRFMesh\/mbed-os,adustm\/mbed,DanKupiniak\/mbed,c1728p9\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,CalSol\/mbed,NXPmicro\/mbed,adustm\/mbed,rgrover\/mbed,bulislaw\/mbed-os,Archcady\/mbed-os,betzw\/mbed-os,kl-cruz\/mbed-os,RonEld\/mbed,HeadsUpDisplayInc\/mbed,tung7970\/mbed-os,andcor02\/mbed-os,fanghuaqi\/mbed,mikaleppanen\/mbed-os,adustm\/mbed,adamgreen\/mbed,mbedmicro\/mbed,j-greffe\/mbed-os,screamerbg\/mbed,cvtsi2sd\/mbed-os,theotherjimmy\/mbed,monkiineko\/mbed-os,fahhem\/mbed-os,karsev\/mbed-os,NXPmicro\/mbed,mbedmicro\/mbed,HeadsUpDisplayInc\/mbed,monkiineko\/mbed-os,andreaslarssonublox\/mbed,rgrover\/mbed,rgrover\/mbed,netzimme\/mbed-os,adamgreen\/mbed,DanKupiniak\/mbed,kjbracey-arm\/mbed,ryankurte\/mbed-os,andreaslarssonublox\/mbed,mazimkhan\/mbed-os,j-greffe\/mbed-os,YarivCol\/mbed-os,tung7970\/mbed-os-1,Archcady\/mbed-os,netzimme\/mbed-os,karsev\/mbed-os,cvtsi2sd\/mbed-os,tung7970\/mbed-os-1,nvlsianpu\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,maximmbed\/mbed,catiedev\/mbed-os,cvtsi2sd\/mbed-os,screamerbg\/mbed,ARM-software\/mbed-beetle,ARM-software\/mbed-beetle,mikaleppanen\/mbed-os,catiedev\/mbed-os,arostm\/mbed-os,kjbracey-arm\/mbed,j-greffe\/mbed-os,j-greffe\/mbed-os,screamerbg\/mbed,maximmbed\/mbed,svogl\/mbed-os,karsev\/mbed-os,nRFMesh\/mbed-os,DanKupiniak\/mbed,mmorenobarm\/mbed-os,screamerbg\/mbed,ARM-software\/mbed-beetle,kl-cruz\/mbed-os,monkiineko\/mbed-os,svogl\/mbed-os,netzimme\/mbed-os,svogl\/mbed-os,infinnovation\/mbed-os,monkiineko\/mbed-os,ARM-software\/mbed-beetle,HeadsUpDisplayInc\/mbed,cvtsi2sd\/mbed-os,monkiineko\/mbed-os,rgrover\/mbed,fanghuaqi\/mbed,andreaslarssonublox\/mbed,pradeep-gr\/mbed-os5-onsemi,tung7970\/mbed-os-1,Archcady\/mbed-os,nRFMesh\/mbed-os,jeremybrodt\/mbed,nRFMesh\/mbed-os,mikaleppanen\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,andreaslarssonublox\/mbed,nRFMesh\/mbed-os,kl-cruz\/mbed-os,andcor02\/mbed-os,jeremybrodt\/mbed,svastm\/mbed,mmorenobarm\/mbed-os,adamgreen\/mbed,geky\/mbed,theotherjimmy\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,pradeep-gr\/mbed-os5-onsemi,j-greffe\/mbed-os,pradeep-gr\/mbed-os5-onsemi,nvlsianpu\/mbed,mmorenobarm\/mbed-os,catiedev\/mbed-os,ryankurte\/mbed-os,kl-cruz\/mbed-os,mazimkhan\/mbed-os,andcor02\/mbed-os,ryankurte\/mbed-os,RonEld\/mbed,HeadsUpDisplayInc\/mbed,svogl\/mbed-os,infinnovation\/mbed-os,fahhem\/mbed-os,catiedev\/mbed-os,bulislaw\/mbed-os,infinnovation\/mbed-os,fahhem\/mbed-os,fahhem\/mbed-os,mmorenobarm\/mbed-os,fvincenzo\/mbed-os,cvtsi2sd\/mbed-os,fahhem\/mbed-os,adustm\/mbed,arostm\/mbed-os,bcostm\/mbed-os,geky\/mbed,HeadsUpDisplayInc\/mbed,mbedmicro\/mbed,jeremybrodt\/mbed,Archcady\/mbed-os,CalSol\/mbed,svastm\/mbed,maximmbed\/mbed,adustm\/mbed,mazimkhan\/mbed-os,YarivCol\/mbed-os,YarivCol\/mbed-os,kjbracey-arm\/mbed,netzimme\/mbed-os,adamgreen\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,screamerbg\/mbed,DanKupiniak\/mbed,bulislaw\/mbed-os,bcostm\/mbed-os,adamgreen\/mbed,svastm\/mbed,c1728p9\/mbed-os,arostm\/mbed-os,mmorenobarm\/mbed-os,nvlsianpu\/mbed,HeadsUpDisplayInc\/mbed,arostm\/mbed-os,RonEld\/mbed,geky\/mbed,c1728p9\/mbed-os,betzw\/mbed-os,ryankurte\/mbed-os,maximmbed\/mbed,pradeep-gr\/mbed-os5-onsemi,NXPmicro\/mbed,mazimkhan\/mbed-os,adustm\/mbed,andcor02\/mbed-os,karsev\/mbed-os,rgrover\/mbed,geky\/mbed,bcostm\/mbed-os,karsev\/mbed-os,fanghuaqi\/mbed,RonEld\/mbed,jeremybrodt\/mbed,mazimkhan\/mbed-os,theotherjimmy\/mbed,andcor02\/mbed-os,nvlsianpu\/mbed,nRFMesh\/mbed-os,kl-cruz\/mbed-os,mikaleppanen\/mbed-os,fvincenzo\/mbed-os,theotherjimmy\/mbed,tung7970\/mbed-os-1,pradeep-gr\/mbed-os5-onsemi,c1728p9\/mbed-os,andreaslarssonublox\/mbed,fahhem\/mbed-os","old_file":"hal\/targets\/cmsis\/TARGET_Freescale\/TARGET_K64F\/TOOLCHAIN_GCC_ARM\/MK64FN1M0xxx12.ld","new_file":"hal\/targets\/cmsis\/TARGET_Freescale\/TARGET_K64F\/TOOLCHAIN_GCC_ARM\/MK64FN1M0xxx12.ld","new_contents":"\/*\n** ###################################################################\n**     Processors:          MK64FN1M0VDC12\n**                          MK64FN1M0VLL12\n**                          MK64FN1M0VLQ12\n**                          MK64FN1M0VMD12\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014\n**     Version:             rev. 2.8, 2015-02-19\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n__ram_vector_table__ = 1;\n\n\/* Heap 1\/4 of ram and stack 1\/8 *\/\n__stack_size__ = 0x8000;\n__heap_size__ = 0x10000;\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    \/* uVisor code and data *\/\n    . = ALIGN(4);\n    __uvisor_main_start = .;\n    *(.uvisor.main)\n    __uvisor_main_end = .;\n\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  \/* Ensure that the uVisor BSS section is put first after the relocated\n   * interrupt table in SRAM. *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: SRAM_OFFSET. *\/\n  __UVISOR_SRAM_OFFSET = 0x400;\n  __UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;\n  ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,\n         \"The ISR relocation region overlaps with the uVisor BSS section.\")\n  .uvisor.bss (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uvisor_bss_start = .;\n\n    \/* protected uvisor main bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_main_start = .;\n    KEEP(*(.keep.uvisor.bss.main))\n    . = ALIGN(32);\n    __uvisor_bss_main_end = .;\n\n    \/* protected uvisor secure boxes bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_boxes_start = .;\n    KEEP(*(.keep.uvisor.bss.boxes))\n    . = ALIGN(32);\n    __uvisor_bss_boxes_end = .;\n\n    . = ALIGN(32);\n    __uvisor_bss_end = .;\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data :\n  {\n    PROVIDE(__etext = LOADADDR(.data));    \/* Define a global symbol at end of code, *\/\n    PROVIDE(__DATA_ROM = LOADADDR(.data)); \/* Symbol is used by startup for data initialization. *\/\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data_2 AT > m_text\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  \/* uVisor configuration section\n   * This section must be located after all other flash regions. *\/\n  .uvisor.secure :\n  {\n    . = ALIGN(32);\n    __uvisor_secure_start = .;\n\n    \/* uVisor secure boxes configuration tables *\/\n    . = ALIGN(32);\n    __uvisor_cfgtbl_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl))\n    . = ALIGN(32);\n    __uvisor_cfgtbl_end = .;\n\n    \/* Pointers to the uVisor secure boxes configuration tables *\/\n    \/* Note: Do not add any further alignment here, as uVisor will need to have\n     * access to the exact list of pointers. *\/\n    __uvisor_cfgtbl_ptr_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n    KEEP(*(.keep.uvisor.cfgtbl_ptr))\n    __uvisor_cfgtbl_ptr_end = .;\n\n    \/* Pointers to all boxes register gateways. These are grouped here to allow\n     * discoverability and firmware verification. *\/\n    __uvisor_register_gateway_ptr_start = .;\n    KEEP(*(.keep.uvisor.register_gateway_ptr))\n    __uvisor_register_gateway_ptr_end = .;\n\n    . = ALIGN(32);\n    __uvisor_secure_end = .;\n  } > m_text\n\n  \/* Uninitialized data section\n   * This region is not initialized by the C\/C++ library and can be used to\n   * store state across soft reboots. *\/\n  .uninitialized (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uninitialized_start = .;\n    *(.uninitialized)\n    KEEP(*(.keep.uninitialized))\n    . = ALIGN(32);\n    __uninitialized_end = .;\n  } > m_data_2\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data_2\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n\n  \/* Provide the physical memory boundaries for uVisor. *\/\n  __uvisor_flash_start = ORIGIN(m_interrupts);\n  __uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);\n  __uvisor_sram_start = ORIGIN(m_data);\n  __uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);\n}\n\n","old_contents":"\/*\n** ###################################################################\n**     Processors:          MK64FN1M0VDC12\n**                          MK64FN1M0VLL12\n**                          MK64FN1M0VLQ12\n**                          MK64FN1M0VMD12\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014\n**     Version:             rev. 2.8, 2015-02-19\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n__ram_vector_table__ = 1;\n\n\/* Heap 1\/4 of ram and stack 1\/8 *\/\n__stack_size__ = 0x8000;\n__heap_size__ = 0x10000;\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data_2\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data_2\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3d99df398b46c7a7f58882930ec5323467853ae7","subject":"\u8868\u8a18\u306e\u5909\u66f4\uff08\u4e2d\u8eab\u306f\u5909\u66f4\u306a\u3057","message":"\u8868\u8a18\u306e\u5909\u66f4\uff08\u4e2d\u8eab\u306f\u5909\u66f4\u306a\u3057\n","repos":"nitkcrbkn\/2016ATeam,nitkcrbkn\/2016BTeam,nitkcrbkn\/2016ATeam,nitkcrbkn\/2016BTeam","old_file":"Drivers\/STM32F103RBTx_FLASH.ld","new_file":"Drivers\/STM32F103RBTx_FLASH.ld","new_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F103RBTx Device with\n**                128KByte FLASH, 20KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n*****************************************************************************\n** @attention\n**\n** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6<\/center><\/h2>\n**\n** Redistribution and use in source and binary forms, with or without modification,\n** are permitted provided that the following conditions are met:\n**   1. Redistributions of source code must retain the above copyright notice,\n**      this list of conditions and the following disclaimer.\n**   2. Redistributions in binary form must reproduce the above copyright notice,\n**      this list of conditions and the following disclaimer in the documentation\n**      and\/or other materials provided with the distribution.\n**   3. Neither the name of Ac6 nor the names of its contributors\n**      may be used to endorse or promote products derived from this software\n**      without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20005000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 128K-1K\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","old_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F103RBTx Device with\n**                128KByte FLASH, 20KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n*****************************************************************************\n** @attention\n**\n** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6<\/center><\/h2>\n**\n** Redistribution and use in source and binary forms, with or without modification,\n** are permitted provided that the following conditions are met:\n**   1. Redistributions of source code must retain the above copyright notice,\n**      this list of conditions and the following disclaimer.\n**   2. Redistributions in binary form must reproduce the above copyright notice,\n**      this list of conditions and the following disclaimer in the documentation\n**      and\/or other materials provided with the distribution.\n**   3. Neither the name of Ac6 nor the names of its contributors\n**      may be used to endorse or promote products derived from this software\n**      without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20005000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 128K-1k\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"923255fa92756a6199487de1577cf0b8621b24ce","subject":"fix(link.ld): Add multiboot header first ! (Fix some bugs)","message":"fix(link.ld): Add multiboot header first ! (Fix some bugs)\n","repos":"Rarioty\/FlowS","old_file":"src\/link.ld","new_file":"src\/link.ld","new_contents":"ENTRY(_start)                   \/* the name of the entry label *\/\n\nSECTIONS {\n    . = 0x00100000;             \/* the code should be loaded at 1MB *\/\n\n    .multiboot :\n    {\n        *(.multiboot)           \/* place multiboot header FIRST ! *\/\n    }\n\n    .text ALIGN (0x1000) :      \/* align at 4 KB *\/\n    {\n        *(.text)                \/* all text sections from all files *\/\n        *(.rodata)              \/* all read-only data sections from all files *\/\n    }\n\n    .data ALIGN (0x1000) :      \/* align at 4 KB *\/\n    {\n        *(.data)                \/* all data sections from all files *\/\n    }\n\n    .bss ALIGN (0x1000) :       \/* align at 4 KB *\/\n    {\n        *(COMMON)               \/* all COMMON sections from all files *\/\n        *(.bss)                 \/* all bss sections from all files *\/\n    }\n}\n","old_contents":"ENTRY(_start)                   \/* the name of the entry label *\/\n\nSECTIONS {\n    . = 0x00100000;             \/* the code should be loaded at 1MB *\/\n\n    .text ALIGN (0x1000) :      \/* align at 4 KB *\/\n    {\n        *(.multiboot)\n        *(.text)                \/* all text sections from all files *\/\n        *(.rodata)              \/* all read-only data sections from all files *\/\n    }\n\n    .data ALIGN (0x1000) :      \/* align at 4 KB *\/\n    {\n        *(.data)                \/* all data sections from all files *\/\n    }\n\n    .bss ALIGN (0x1000) :       \/* align at 4 KB *\/\n    {\n        *(COMMON)               \/* all COMMON sections from all files *\/\n        *(.bss)                 \/* all bss sections from all files *\/\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8c6d2365d71724997c43aa4797c8e3722da7e392","subject":"Remove license header form linker script","message":"Remove license header form linker script\n\nSigned-off-by: Tomasz Jankowski <503a486186d52d88001783868db1a06ad09e4157@gmail.com>\n","repos":"goofacz\/cortex-m-minimal-c,goofacz\/cortex-m-minimal-c","old_file":"cortex_m4.ld","new_file":"cortex_m4.ld","new_contents":"ENTRY(interrupt_reset)\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x0000000, LENGTH = 0x80000\n    STACK (rw): ORIGIN = 0x20004FFC, LENGTH = 0K\n    RAM (rw) : ORIGIN = 0x20010000, LENGTH = 0x10000\n}\n \nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.vector_table))\n        *(.text)\n    } >FLASH\n    \n    .stack :\n    {\n        _STACK_HEAD = .;\n    } >STACK\n}  \n","old_contents":"# This Source Code Form is subject to the terms of the Mozilla Public\n# License, v. 2.0. If a copy of the MPL was not distributed with this\n# file, You can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/.\n\nENTRY(interrupt_reset)\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x0000000, LENGTH = 0x80000\n    STACK (rw): ORIGIN = 0x20004FFC, LENGTH = 0K\n    RAM (rw) : ORIGIN = 0x20010000, LENGTH = 0x10000\n}\n \nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.vector_table))\n        *(.text)\n    } >FLASH\n    \n    .stack :\n    {\n        _STACK_HEAD = .;\n    } >STACK\n}  \n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"46b7d549e588a112aab2639a6e1ece1e02ff9e28","subject":"[Reflection] Update Linux linker script for .swift3_fieldmd, .swift3_assocty","message":"[Reflection] Update Linux linker script for .swift3_fieldmd, .swift3_assocty\n","repos":"djwbrown\/swift,amraboelela\/swift,lorentey\/swift,ahoppen\/swift,tjw\/swift,jckarter\/swift,swiftix\/swift,practicalswift\/swift,allevato\/swift,bitjammer\/swift,allevato\/swift,bitjammer\/swift,apple\/swift,karwa\/swift,shajrawi\/swift,therealbnut\/swift,austinzheng\/swift,jmgc\/swift,benlangmuir\/swift,tardieu\/swift,Jnosh\/swift,gregomni\/swift,IngmarStein\/swift,swiftix\/swift,felix91gr\/swift,milseman\/swift,deyton\/swift,djwbrown\/swift,jmgc\/swift,zisko\/swift,nathawes\/swift,aschwaighofer\/swift,stephentyrone\/swift,danielmartin\/swift,JaSpa\/swift,JaSpa\/swift,deyton\/swift,JGiola\/swift,swiftix\/swift,deyton\/swift,arvedviehweger\/swift,airspeedswift\/swift,tinysun212\/swift-windows,kstaring\/swift,therealbnut\/swift,danielmartin\/swift,gribozavr\/swift,CodaFi\/swift,xwu\/swift,codestergit\/swift,djwbrown\/swift,CodaFi\/swift,arvedviehweger\/swift,OscarSwanros\/swift,aschwaighofer\/swift,ben-ng\/swift,IngmarStein\/swift,CodaFi\/swift,kperryua\/swift,sschiau\/swift,rudkx\/swift,aschwaighofer\/swift,manavgabhawala\/swift,airspeedswift\/swift,codestergit\/swift,tardieu\/swift,return\/swift,sschiau\/swift,shahmishal\/swift,Jnosh\/swift,johnno1962d\/swift,hooman\/swift,manavgabhawala\/swift,xwu\/swift,dreamsxin\/swift,KrishMunot\/swift,roambotics\/swift,shahmishal\/swift,parkera\/swift,stephentyrone\/swift,huonw\/swift,johnno1962d\/swift,devincoughlin\/swift,xedin\/swift,nathawes\/swift,gottesmm\/swift,lorentey\/swift,brentdax\/swift,felix91gr\/swift,Jnosh\/swift,brentdax\/swift,kstaring\/swift,calebd\/swift,calebd\/swift,jtbandes\/swift,russbishop\/swift,huonw\/swift,natecook1000\/swift,ken0nek\/swift,natecook1000\/swift,huonw\/swift,tkremenek\/swift,johnno1962d\/swift,gmilos\/swift,alblue\/swift,return\/swift,shajrawi\/swift,harlanhaskins\/swift,therealbnut\/swift,kperryua\/swift,modocache\/swift,gmilos\/swift,gribozavr\/swift,KrishMunot\/swift,gribozavr\/swift,nathawes\/swift,gmilos\/swift,karwa\/swift,gregomni\/swift,gmilos\/swift,tkremenek\/swift,lorentey\/swift,lorentey\/swift,hooman\/swift,Jnosh\/swift,glessard\/swift,jmgc\/swift,apple\/swift,calebd\/swift,karwa\/swift,felix91gr\/swift,airspeedswift\/swift,danielmartin\/swift,aschwaighofer\/swift,parkera\/swift,milseman\/swift,amraboelela\/swift,JaSpa\/swift,shajrawi\/swift,uasys\/swift,tjw\/swift,jckarter\/swift,alblue\/swift,huonw\/swift,SwiftAndroid\/swift,bitjammer\/swift,codestergit\/swift,parkera\/swift,xedin\/swift,austinzheng\/swift,tinysun212\/swift-windows,aschwaighofer\/swift,nathawes\/swift,parkera\/swift,practicalswift\/swift,manavgabhawala\/swift,airspeedswift\/swift,codestergit\/swift,tardieu\/swift,jmgc\/swift,tjw\/swift,arvedviehweger\/swift,xwu\/swift,johnno1962d\/swift,CodaFi\/swift,hughbe\/swift,arvedviehweger\/swift,therealbnut\/swift,jopamer\/swift,brentdax\/swift,roambotics\/swift,dduan\/swift,JaSpa\/swift,harlanhaskins\/swift,jtbandes\/swift,jopamer\/swift,karwa\/swift,aschwaighofer\/swift,practicalswift\/swift,arvedviehweger\/swift,frootloops\/swift,gottesmm\/swift,rudkx\/swift,dduan\/swift,nathawes\/swift,dreamsxin\/swift,jmgc\/swift,calebd\/swift,shajrawi\/swift,tardieu\/swift,SwiftAndroid\/swift,ahoppen\/swift,shajrawi\/swift,dduan\/swift,sschiau\/swift,calebd\/swift,jtbandes\/swift,stephentyrone\/swift,shahmishal\/swift,hughbe\/swift,return\/swift,KrishMunot\/swift,ben-ng\/swift,natecook1000\/swift,hooman\/swift,modocache\/swift,hooman\/swift,frootloops\/swift,IngmarStein\/swift,airspeedswift\/swift,lorentey\/swift,karwa\/swift,Jnosh\/swift,calebd\/swift,codestergit\/swift,lorentey\/swift,JGiola\/swift,uasys\/swift,nathawes\/swift,ahoppen\/swift,jopamer\/swift,alblue\/swift,kstaring\/swift,deyton\/swift,atrick\/swift,gregomni\/swift,tkremenek\/swift,harlanhaskins\/swift,kstaring\/swift,atrick\/swift,milseman\/swift,swiftix\/swift,huonw\/swift,benlangmuir\/swift,lorentey\/swift,airspeedswift\/swift,austinzheng\/swift,practicalswift\/swift,modocache\/swift,calebd\/swift,gottesmm\/swift,glessard\/swift,parkera\/swift,zisko\/swift,tinysun212\/swift-windows,shahmishal\/swift,modocache\/swift,allevato\/swift,kperryua\/swift,modocache\/swift,roambotics\/swift,ken0nek\/swift,bitjammer\/swift,OscarSwanros\/swift,tkremenek\/swift,kstaring\/swift,xedin\/swift,jmgc\/swift,ken0nek\/swift,uasys\/swift,natecook1000\/swift,austinzheng\/swift,IngmarStein\/swift,bitjammer\/swift,huonw\/swift,JGiola\/swift,jckarter\/swift,benlangmuir\/swift,felix91gr\/swift,russbishop\/swift,modocache\/swift,shajrawi\/swift,xwu\/swift,ben-ng\/swift,gribozavr\/swift,return\/swift,KrishMunot\/swift,codestergit\/swift,devincoughlin\/swift,felix91gr\/swift,uasys\/swift,gottesmm\/swift,jckarter\/swift,danielmartin\/swift,gribozavr\/swift,glessard\/swift,OscarSwanros\/swift,frootloops\/swift,stephentyrone\/swift,frootloops\/swift,tjw\/swift,SwiftAndroid\/swift,swiftix\/swift,jmgc\/swift,sschiau\/swift,sschiau\/swift,deyton\/swift,uasys\/swift,ben-ng\/swift,shahmishal\/swift,ahoppen\/swift,ken0nek\/swift,practicalswift\/swift,kstaring\/swift,SwiftAndroid\/swift,natecook1000\/swift,kperryua\/swift,tardieu\/swift,danielmartin\/swift,rudkx\/swift,allevato\/swift,airspeedswift\/swift,allevato\/swift,russbishop\/swift,arvedviehweger\/swift,ahoppen\/swift,gregomni\/swift,xedin\/swift,jtbandes\/swift,devincoughlin\/swift,amraboelela\/swift,frootloops\/swift,jopamer\/swift,glessard\/swift,CodaFi\/swift,johnno1962d\/swift,tkremenek\/swift,aschwaighofer\/swift,apple\/swift,gmilos\/swift,xwu\/swift,tinysun212\/swift-windows,harlanhaskins\/swift,xedin\/swift,austinzheng\/swift,zisko\/swift,xedin\/swift,tjw\/swift,gribozavr\/swift,OscarSwanros\/swift,ken0nek\/swift,SwiftAndroid\/swift,Jnosh\/swift,gregomni\/swift,dduan\/swift,tkremenek\/swift,danielmartin\/swift,JaSpa\/swift,jopamer\/swift,xwu\/swift,amraboelela\/swift,sschiau\/swift,shajrawi\/swift,djwbrown\/swift,apple\/swift,frootloops\/swift,alblue\/swift,JGiola\/swift,dduan\/swift,jtbandes\/swift,tjw\/swift,KrishMunot\/swift,tardieu\/swift,johnno1962d\/swift,hughbe\/swift,russbishop\/swift,felix91gr\/swift,manavgabhawala\/swift,karwa\/swift,jtbandes\/swift,practicalswift\/swift,harlanhaskins\/swift,natecook1000\/swift,alblue\/swift,devincoughlin\/swift,devincoughlin\/swift,xedin\/swift,bitjammer\/swift,benlangmuir\/swift,JaSpa\/swift,apple\/swift,hughbe\/swift,natecook1000\/swift,harlanhaskins\/swift,djwbrown\/swift,amraboelela\/swift,gmilos\/swift,allevato\/swift,OscarSwanros\/swift,devincoughlin\/swift,ken0nek\/swift,dduan\/swift,gribozavr\/swift,parkera\/swift,ben-ng\/swift,hughbe\/swift,manavgabhawala\/swift,felix91gr\/swift,parkera\/swift,parkera\/swift,huonw\/swift,shahmishal\/swift,djwbrown\/swift,deyton\/swift,austinzheng\/swift,kperryua\/swift,sschiau\/swift,hooman\/swift,manavgabhawala\/swift,xwu\/swift,stephentyrone\/swift,roambotics\/swift,SwiftAndroid\/swift,modocache\/swift,roambotics\/swift,shajrawi\/swift,therealbnut\/swift,zisko\/swift,therealbnut\/swift,KrishMunot\/swift,lorentey\/swift,return\/swift,glessard\/swift,glessard\/swift,milseman\/swift,jckarter\/swift,gregomni\/swift,CodaFi\/swift,jtbandes\/swift,xedin\/swift,JGiola\/swift,danielmartin\/swift,brentdax\/swift,OscarSwanros\/swift,gottesmm\/swift,kperryua\/swift,hughbe\/swift,johnno1962d\/swift,return\/swift,roambotics\/swift,rudkx\/swift,alblue\/swift,arvedviehweger\/swift,alblue\/swift,ken0nek\/swift,SwiftAndroid\/swift,gottesmm\/swift,manavgabhawala\/swift,practicalswift\/swift,russbishop\/swift,practicalswift\/swift,JaSpa\/swift,gribozavr\/swift,austinzheng\/swift,amraboelela\/swift,jckarter\/swift,uasys\/swift,djwbrown\/swift,therealbnut\/swift,benlangmuir\/swift,benlangmuir\/swift,atrick\/swift,russbishop\/swift,frootloops\/swift,jopamer\/swift,milseman\/swift,gottesmm\/swift,OscarSwanros\/swift,devincoughlin\/swift,CodaFi\/swift,atrick\/swift,tardieu\/swift,brentdax\/swift,atrick\/swift,sschiau\/swift,deyton\/swift,tinysun212\/swift-windows,russbishop\/swift,karwa\/swift,allevato\/swift,atrick\/swift,hooman\/swift,brentdax\/swift,swiftix\/swift,stephentyrone\/swift,tjw\/swift,harlanhaskins\/swift,rudkx\/swift,shahmishal\/swift,codestergit\/swift,Jnosh\/swift,jopamer\/swift,return\/swift,amraboelela\/swift,brentdax\/swift,zisko\/swift,tinysun212\/swift-windows,swiftix\/swift,zisko\/swift,IngmarStein\/swift,nathawes\/swift,apple\/swift,stephentyrone\/swift,gmilos\/swift,uasys\/swift,ahoppen\/swift,JGiola\/swift,bitjammer\/swift,rudkx\/swift,ben-ng\/swift,karwa\/swift,ben-ng\/swift,KrishMunot\/swift,devincoughlin\/swift,zisko\/swift,shahmishal\/swift,tkremenek\/swift,IngmarStein\/swift,milseman\/swift,dduan\/swift,IngmarStein\/swift,kperryua\/swift,tinysun212\/swift-windows,kstaring\/swift,hooman\/swift,jckarter\/swift,hughbe\/swift,milseman\/swift","old_file":"stdlib\/public\/runtime\/swift.ld","new_file":"stdlib\/public\/runtime\/swift.ld","new_contents":"SECTIONS\n{\n  .swift3_typeref : { *(.swift3_typeref) },\n  .swift3_reflstr : { *(.swift3_reflstr) },\n  .swift3_fieldmd : { *(.swift3_fieldmd) },\n  .swift3_assocty : { *(.swift3_assocty) },\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","old_contents":"SECTIONS\n{\n  .swift3_typeref : { *(.swift3_typeref) },\n  .swift3_reflstr : { *(.swift3_reflstr) },\n  .swift3_reflect : { *(.swift3_reflect) },\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8ee00d1ff13a8780f6b83c686b5bda218e515c71","subject":"small fix","message":"small fix\n","repos":"ps3dev\/PSL1GHT,ps3dev\/PSL1GHT,ps3dev\/PSL1GHT,ps3dev\/PSL1GHT","old_file":"ppu\/crt\/lv2.ld","new_file":"ppu\/crt\/lv2.ld","new_contents":"OUTPUT_FORMAT(\"elf64-powerpc\", \"elf64-powerpc\", \"elf64-powerpc\")\nOUTPUT_ARCH(powerpc:common64)\n\nENTRY(_start)\n\nPHDRS\n{\n\thdr_text\tPT_LOAD FILEHDR PHDRS\tFLAGS(0x01 | 0x04);\n\thdr_data\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04);\n\thdr_srodata\tPT_LOAD\t\t\t\t\tFLAGS(0x04 | 0x00400000);\n\thdr_sdata\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04 | 0x00200000 | 0x00400000);\n\thdr_rsx\t\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04 | 0x00200000 | 0x00400000 | 0x02000000 | 0x04000000);\n\thdr_tls\t\tPT_TLS\t\t\t\t\tFLAGS(0x04);\n\thdr_param\t0x60000001\t\t\t\tFLAGS(0x00);\n\thdr_prx\t\t0x60000002\t\t\t\tFLAGS(0x00);\n}\n\nSECTIONS\n{\n\tPROVIDE (__executable_start = 0x10000); . = 0x10000 + SIZEOF_HEADERS;\n\t.interp         : { *(.interp) } : hdr_text\n\t.hash           : { *(.hash) }\n\t.dynsym         : { *(.dynsym) }\n\t.dynstr         : { *(.dynstr) }\n\t.gnu.version    : { *(.gnu.version) }\n\t.gnu.version_d  : { *(.gnu.version_d) }\n\t.gnu.version_r  : { *(.gnu.version_r) }\n\t.rel.dyn\t\t:\n\t  {\n\t    *(.rel.init)\n\t    *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n\t    *(.rel.fini)\n\t    *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n\t    *(.rel.data.rel.ro*)\n\t    *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n\t    *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n\t    *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n\t    *(.rel.ctors)\n\t    *(.rel.dtors)\n\t    *(.rel.got)\n\t    *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)\n\t    *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)\n\t    *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)\n\t    *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)\n\t    *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n\t  }\n\n\t.rela.dyn\t\t:\n\t  {\n\t    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The wildcard also means that it\n\t\t   doesn't matter which directory crtbegin.o\n\t\t   is in.  *\/\n\t\tKEEP (*crtbegin.o(.ctors))\n\t\tKEEP (*crtbegin?.o(.ctors))\n\t\t\/* We don't want to include the .ctor section from\n\t\t   the crtend.o file until after the sorted ctors.\n\t\t   The .ctor section from the crtend file contains the\n\t\t   end of ctors marker and it must be last *\/\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t}\n\t.dtors          : {\n\t\tKEEP (*crtbegin.o(.dtors))\n\t\tKEEP (*crtbegin?.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t}\n\t.jcr            : { KEEP (*(.jcr)) }\n\t.data.rel.ro : { *(.data.rel.ro.local*) *(.data.rel.ro*) }\n\t.dynamic        : { *(.dynamic) }\n\n\t.data.sceFStub      : { KEEP (*(.data.sceFStub)) KEEP (*(SORT(.data.sceFStub.*))) }\n\t\n\t.toc1\t\t  : ALIGN(8) { *(.toc1) }\n\t.opd\t\t  : ALIGN(8) { KEEP (*(.opd)) }\n\t.branch_lt\t  : ALIGN(8) { *(.branch_lt) }\n\t.got\t\t  : ALIGN(8) { *(.got .toc) }\n\t.toc.sceStub  : { KEEP (*(.toc.sceStub)) KEEP (*(SORT(.toc.sceStub.*))) }\n\t\n\t\/* Thread Local Storage sections  *\/\n\t.tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } : hdr_data : hdr_tls\n\t.tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } : hdr_data : hdr_tls\n\t\n\t. = ALIGN(256M);\n\n\t.rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } : hdr_srodata\n\t.rodata1        : { *(.rodata1) } : hdr_srodata\n\n\t.spu_image\t\t: { *(.spu_image .spu_image.*) } : hdr_srodata\n\t\n\t. = ALIGN(64K);\n\n\t.data           :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tKEEP (*(.gnu.linkonce.d.*personality*))\n\t\tSORT(CONSTRUCTORS)\n\t} : hdr_sdata\n\t.data1          : { *(.data1) }\n\n  \/* We want the small data sections together, so single-instruction offsets\n     can access them all, and initialized data all before uninitialized, so\n     we can shorten the on-disk segment size.  *\/\n\t.sdata          : {\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t}\n\t_edata = .;\n\tPROVIDE (edata = .);\n\n\t__bss_start = .;\n\t.tocbss\t  : ALIGN(8) { *(.tocbss)}\n\t.sbss           :\n\t{\n\t\tPROVIDE (__sbss_start = .);\n\t\tPROVIDE (___sbss_start = .);\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\tPROVIDE (__sbss_end = .);\n\t\tPROVIDE (___sbss_end = .);\n\t}\n\t.plt            : { *(.plt) }\n\t.bss            :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t\/* Align here to ensure that the .bss section occupies space up to\n\t\t   _end.  Align after .bss to ensure correct alignment even if the\n\t\t   .bss section disappears because there are no input sections.\n\t\t   FIXME: Why do we need it? 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. = 0x10000 + SIZEOF_HEADERS;\n\t.interp         : { *(.interp) } : hdr_text\n\t.hash           : { *(.hash) }\n\t.dynsym         : { *(.dynsym) }\n\t.dynstr         : { *(.dynstr) }\n\t.gnu.version    : { *(.gnu.version) }\n\t.gnu.version_d  : { *(.gnu.version_d) }\n\t.gnu.version_r  : { *(.gnu.version_r) }\n\t.rel.dyn\t\t:\n\t  {\n\t    *(.rel.init)\n\t    *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n\t    *(.rel.fini)\n\t    *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n\t    *(.rel.data.rel.ro*)\n\t    *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n\t    *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n\t    *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n\t    *(.rel.ctors)\n\t    *(.rel.dtors)\n\t    *(.rel.got)\n\t    *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)\n\t    *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)\n\t    *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)\n\t    *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)\n\t    *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n\t  }\n\n\t.rela.dyn\t\t:\n\t  {\n\t    *(.rela.init)\n\t    *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n\t    *(.rela.fini)\n\t    *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n\t    *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n\t    *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n\t    *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n\t    *(.rela.ctors)\n\t    *(.rela.dtors)\n\t    *(.rela.got)\n\t    *(.rela.toc)\n\t    *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)\n\t    *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)\n\t    *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)\n\t    *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)\n\t    *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n\t  }\n\t.rel.plt        : { *(.rel.plt) }\n\t.rela.plt       : { *(.rela.plt) }\n\t.rela.tocbss    : { *(.rela.tocbss) }\n\t.init           : {\n\t\tKEEP (*(.init))\n\t} = 0x60000000\n\t.text           : {\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\tKEEP (*(.text.*personality*))\n\t\t\/* .gnu.warning sections are handled specially by elf32.em.  *\/\n\t\t*(.gnu.warning)\n\t\t*(.sfpr .glink)\n\t} = 0x60000000\n\t.fini           : {\n\t\tKEEP (*(.fini))\n\t} = 0x60000000\n\t.sceStub.text   : {\n\t\t*(.sceStub.text)\n\t\t*(SORT(.sceStub.text.*))\n\t}\n\tPROVIDE (__etext = .);\n\tPROVIDE (_etext = .);\n\tPROVIDE (etext = .);\n\n\t.eh_frame_hdr : { *(.eh_frame_hdr) }\n\t.eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n\t.gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n\n\t.rodata.sceResident : { KEEP (*(.rodata.sceResident)) }\n\t.rodata.sceFNID     : { KEEP (*(.rodata.sceFNID .rodata.sceFNID.*)) }\n\t.rodata.sceVNID     : { KEEP (*(.rodata.sceVNID .rodata.sceVNID.*)) }\n\t.rodata.sceTNID     : { KEEP (*(.rodata.sceTNID .rodata.sceTNID.*)) }\n\t.rodata.sceVStub    : { KEEP (*(.rodata.sceVStub)) KEEP (*(SORT(.rodata.sceVStub.*))) }\n\n\tPROVIDE (__libentstart = .);\n\t.lib.ent.top : { KEEP (*(.lib.ent.top)) }\n\t.lib.ent\t : { KEEP (*(.lib.ent)) }\n\t.lib.ent.btm : { KEEP (*(.lib.ent.btm)) }\n\tPROVIDE (__libentend = .);\n\n\tPROVIDE (__libstubstart = .);\n\t.lib.stub.top : { KEEP (*(.lib.stub.top)) }\n\t.lib.stub\t  : { KEEP (*(.lib.stub)) }\n\t.lib.stub.btm : { KEEP (*(.lib.stub.btm)) }\n\tPROVIDE (__libstubend = .);\n\n\t.ppu_rodata         : { *(.ppu_rodata .ppu_rodata.*) }\n\t.sys_proc_param     : { KEEP (*(.sys_proc_param)) } : hdr_text : hdr_param\n\t.sys_proc_prx_param : { KEEP (*(.sys_proc_prx_param)) } : hdr_text : hdr_prx\n\n\t. = ALIGN(64K);\n\t\n\t.ppu_data           : { *(.ppu_data .ppu_data.*) } : hdr_data\n\t.sdata2             : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }\n\t.sbss2              : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }\n\n\t\/* Exception handling  *\/\n\t.eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n\t.gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n\t\n\t. = ALIGN(64 \/ 8);\n\t\n\t.preinit_array     : {\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\t}\n\t.init_array     : {\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\t}\n\t.fini_array     : {\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\t}\n\t.ctors          : {\n\t\t\/* gcc uses crtbegin.o to find the start of\n\t\t   the constructors, so we make sure it is\n\t\t   first.  Because this is a wildcard, it\n\t\t   doesn't matter if the user does not\n\t\t   actually link against crtbegin.o; the\n\t\t   linker won't look for a file to match a\n\t\t   wildcard.  The wildcard also means that it\n\t\t   doesn't matter which directory crtbegin.o\n\t\t   is in.  *\/\n\t\tKEEP (*crtbegin.o(.ctors))\n\t\tKEEP (*crtbegin?.o(.ctors))\n\t\t\/* We don't want to include the .ctor section from\n\t\t   the crtend.o file until after the sorted ctors.\n\t\t   The .ctor section from the crtend file contains the\n\t\t   end of ctors marker and it must be last *\/\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t}\n\t.dtors          : {\n\t\tKEEP (*crtbegin.o(.dtors))\n\t\tKEEP (*crtbegin?.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t}\n\t.jcr            : { KEEP (*(.jcr)) }\n\t.data.rel.ro : { *(.data.rel.ro.local*) *(.data.rel.ro*) }\n\t.dynamic        : { *(.dynamic) }\n\n\t.data.sceFStub      : { KEEP (*(.data.sceFStub)) KEEP (*(SORT(.data.sceFStub.*))) }\n\t\n\t.toc1\t\t  : ALIGN(8) { *(.toc1) }\n\t.opd\t\t  : ALIGN(8) { KEEP (*(.opd)) }\n\t.branch_lt\t  : ALIGN(8) { *(.branch_lt) }\n\t.got\t\t  : ALIGN(8) { *(.got .toc) }\n\t.toc.sceStub  : { KEEP (*(.toc.sceStub)) KEEP (*(SORT(.toc.sceStub.*))) }\n\t\n\t\/* Thread Local Storage sections  *\/\n\t.tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } : hdr_data : hdr_tls\n\t.tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } : hdr_data : hdr_tls\n\t\n\t. = ALIGN(256M);\n\n\t.rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } : hdr_srodata\n\t.rodata1        : { *(.rodata1) } : hdr_srodata\n\n\t.spu_image\t\t: { *(.spu_image .spu_image.*) } :ph_srodata\n\t\n\t. = ALIGN(64K);\n\n\t.data           :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tKEEP (*(.gnu.linkonce.d.*personality*))\n\t\tSORT(CONSTRUCTORS)\n\t} : hdr_sdata\n\t.data1          : { *(.data1) }\n\n  \/* We want the small data sections together, so single-instruction offsets\n     can access them all, and initialized data all before uninitialized, so\n     we can shorten the on-disk segment size.  *\/\n\t.sdata          : {\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t}\n\t_edata = .;\n\tPROVIDE (edata = .);\n\n\t__bss_start = .;\n\t.tocbss\t  : ALIGN(8) { *(.tocbss)}\n\t.sbss           :\n\t{\n\t\tPROVIDE (__sbss_start = .);\n\t\tPROVIDE (___sbss_start = .);\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\tPROVIDE (__sbss_end = .);\n\t\tPROVIDE (___sbss_end = .);\n\t}\n\t.plt            : { *(.plt) }\n\t.bss            :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t\/* Align here to ensure that the .bss section occupies space up to\n\t\t   _end.  Align after .bss to ensure correct alignment even if the\n\t\t   .bss section disappears because there are no input sections.\n\t\t   FIXME: Why do we need it? When there is no .bss section, we don't\n\t\t   pad the .data section.  *\/\n\t\t. = ALIGN(64 \/ 8);\n\t}\n\t\n\t. = ALIGN(256M);\n\n\t.rsx_image\t: { *(.rsx_*) } :ph_rsx\n\t\t\n\t_end = .;\n\t__end = .;\n\tPROVIDE (end = .);\n\t\n\t. = ALIGN(8);\n\t\n\t\/* Stabs debugging sections.  *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment       0 : { *(.comment) }\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0.  *\/\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\n\t.debug_typenames 0 : { *(.debug_typenames) }\n\t.debug_varnames  0 : { *(.debug_varnames) }\n\t\/* DWARF 3 *\/\n\t.debug_pubtypes 0 : { *(.debug_pubtypes) }\n\t.debug_ranges   0 : { *(.debug_ranges) }\n\t.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n\t\/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"98cf1f4d7f5503b81169f7e56a5354791022f133","subject":"Make the basic launcher work again.","message":"Make the basic launcher work again.","repos":"rbsexton\/gecko,rbsexton\/gecko,rbsexton\/gecko","old_file":"zero\/basic\/launcher\/efm32zg.ld","new_file":"zero\/basic\/launcher\/efm32zg.ld","new_contents":"\/* Linker script for Silicon Labs EFM32ZG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 3.20.12 *\/\r\n\/*                                                                  *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8192\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 4096\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n * \r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.vectors))\r\n    KEEP(*(.jumptable))\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab : \r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(.shareddata)\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap :\r\n  {\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    *(.heap*)\r\n    __HeapLimit = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy :\r\n  {\r\n    *(.stack)\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","old_contents":"\/* Linker script for Silicon Labs EFM32ZG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 3.20.12 *\/\r\n\/*                                                                  *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8192\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 4096\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n * \r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.isr_vector))\r\n    KEEP(*(.jumptable))\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab : \r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(.shareddata)\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap :\r\n  {\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    *(.heap*)\r\n    __HeapLimit = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy :\r\n  {\r\n    *(.stack)\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"266a8fbeeaa33ac37cf1c2c2f7d2c63e61c9c313","subject":"feat(linker): add the address of DMA1","message":"feat(linker): add the address of DMA1\n","repos":"japaric\/discovery.rs,japaric\/discovery.rs","old_file":"registers.ld","new_file":"registers.ld","new_contents":"__TIM7__ = 0x40001400;\n\n__AFIO__ = 0x40010000;\n\n__GPIOA__ = 0x40010800;\n__GPIOB__ = 0x40010C00;\n__GPIOC__ = 0x40011000;\n__GPIOD__ = 0x40011400;\n__GPIOE__ = 0x40011800;\n\n__USART1__ = 0x40013800;\n\n__RCC__ = 0x40021000;\n\n__DMA1__ = 0x40020000;\n\n__NVIC__ = 0xE000E100;\n","old_contents":"__TIM7__ = 0x40001400;\n\n__AFIO__ = 0x40010000;\n\n__GPIOA__ = 0x40010800;\n__GPIOB__ = 0x40010C00;\n__GPIOC__ = 0x40011000;\n__GPIOD__ = 0x40011400;\n__GPIOE__ = 0x40011800;\n\n__USART1__ = 0x40013800;\n\n__RCC__ = 0x40021000;\n\n__NVIC__ = 0xE000E100;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9752943c3c4ffa6a5e95f893906458947bf57289","subject":"update ld add *(.sdk.version)","message":"update ld add *(.sdk.version)\n","repos":"mangelajo\/Arduino,Cloudino\/Cloudino-Arduino-IDE,smily77\/Arduino,noahchense\/Arduino-1,nkolban\/Arduino,mangelajo\/Arduino,weera00\/Arduino,ssvs111\/Arduino,NeuralSpaz\/Arduino,ogahara\/Arduino,EmuxEvans\/Arduino,shiitakeo\/Arduino,weera00\/Arduino,paulmand3l\/Arduino,smily77\/Arduino,jomolinare\/Arduino,tannewt\/Arduino,Cloudino\/Arduino,weera00\/Arduino,spapadim\/Arduino,ssvs111\/Arduino,mateuszdw\/Arduino,EmuxEvans\/Arduino,aichi\/Arduino-2,spapadim\/Arduino,gonium\/Arduino,ogahara\/Arduino,sanyaade-iot\/Arduino-1,sanyaade-iot\/Arduino-1,jomolinare\/Arduino,smily77\/Arduino,Cloudino\/Cloudino-Arduino-IDE,mangelajo\/Arduino,koltegirish\/Arduino,NeuralSpaz\/Arduino,smily77\/Arduino,Cloudino\/Cloudino-Arduino-IDE,mateuszdw\/Arduino,paulo-raca\/ESP8266-Arduino,EmuxEvans\/Arduino,noahchense\/Arduino-1,Cloudino\/Cloudino-Arduino-IDE,tannewt\/Arduino,noahchense\/Arduino-1,myrtleTree33\/Arduino,mateuszdw\/Arduino,NeuralSpaz\/Arduino,shiitakeo\/Arduino,paulmand3l\/Arduino,sanyaade-iot\/Arduino-1,mangelajo\/Arduino,mateuszdw\/Arduino,radut\/Arduino,NeuralSpaz\/Arduino,gonium\/Arduino,paulo-raca\/ESP8266-Arduino,EmuxEvans\/Arduino,radut\/Arduino,shiitakeo\/Arduino,aichi\/Arduino-2,zenmanenergy\/Arduino,leftbrainstrain\/Arduino-ESP8266,smily77\/Arduino,Cloudino\/Cloudino-Arduino-IDE,myrtleTree33\/Arduino,paulo-raca\/ESP8266-Arduino,Cloudino\/Arduino,eeijcea\/Arduino-1,Cloudino\/Arduino,aichi\/Arduino-2,mangelajo\/Arduino,mangelajo\/Arduino,koltegirish\/Arduino,koltegirish\/Arduino,radut\/Arduino,shiitakeo\/Arduino,radut\/Arduino,radut\/Arduino,weera00\/Arduino,leftbrainstrain\/Arduino-ESP8266,ogahara\/Arduino,tannewt\/Arduino,paulmand3l\/Arduino,nkolban\/Arduino,paulo-raca\/ESP8266-Arduino,leftbrainstrain\/Arduino-ESP8266,myrtleTree33\/Arduino,wdoganowski\/Arduino,gonium\/Arduino,ssvs111\/Arduino,eeijcea\/Arduino-1,zenmanenergy\/Arduino,noahchense\/Arduino-1,tannewt\/Arduino,Cloudino\/Arduino,aichi\/Arduino-2,smily77\/Arduino,EmuxEvans\/Arduino,weera00\/Arduino,jomolinare\/Arduino,tannewt\/Arduino,mateuszdw\/Arduino,eeijcea\/Arduino-1,sanyaade-iot\/Arduino-1,koltegirish\/Arduino,paulmand3l\/Arduino,ssvs111\/Arduino,drpjk\/Arduino,jomolinare\/Arduino,smily77\/Arduino,paulo-raca\/ESP8266-Arduino,koltegirish\/Arduino,wdoganowski\/Arduino,NeuralSpaz\/Arduino,jomolinare\/Arduino,shiitakeo\/Arduino,myrtleTree33\/Arduino,nkolban\/Arduino,spapadim\/Arduino,mangelajo\/Arduino,aichi\/Arduino-2,wdoganowski\/Arduino,aichi\/Arduino-2,leftbrainstrain\/Arduino-ESP8266,sanyaade-iot\/Arduino-1,shiitakeo\/Arduino,noahchense\/Arduino-1,mateuszdw\/Arduino,weera00\/Arduino,shiitakeo\/Arduino,wdoganowski\/Arduino,gonium\/Arduino,Cloudino\/Arduino,drpjk\/Arduino,nkolban\/Arduino,wdoganowski\/Arduino,ssvs111\/Arduino,nkolban\/Arduino,Cloudino\/Cloudino-Arduino-IDE,paulmand3l\/Arduino,drpjk\/Arduino,koltegirish\/Arduino,ogahara\/Arduino,mateuszdw\/Arduino,wdoganowski\/Arduino,ogahara\/Arduino,weera00\/Arduino,eeijcea\/Arduino-1,koltegirish\/Arduino,drpjk\/Arduino,leftbrainstrain\/Arduino-ESP8266,ssvs111\/Arduino,spapadim\/Arduino,sanyaade-iot\/Arduino-1,Cloudino\/Cloudino-Arduino-IDE,myrtleTree33\/Arduino,paulmand3l\/Arduino,zenmanenergy\/Arduino,Cloudino\/Arduino,tannewt\/Arduino,tannewt\/Arduino,jomolinare\/Arduino,EmuxEvans\/Arduino,eeijcea\/Arduino-1,spapadim\/Arduino,noahchense\/Arduino-1,spapadim\/Arduino,nkolban\/Arduino,Cloudino\/Arduino,paulo-raca\/ESP8266-Arduino,jomolinare\/Arduino,myrtleTree33\/Arduino,gonium\/Arduino,eeijcea\/Arduino-1,NeuralSpaz\/Arduino,gonium\/Arduino,drpjk\/Arduino,spapadim\/Arduino,nkolban\/Arduino,paulmand3l\/Arduino,leftbrainstrain\/Arduino-ESP8266,drpjk\/Arduino,sanyaade-iot\/Arduino-1,radut\/Arduino,myrtleTree33\/Arduino,eeijcea\/Arduino-1,NeuralSpaz\/Arduino,ogahara\/Arduino,EmuxEvans\/Arduino,drpjk\/Arduino,zenmanenergy\/Arduino,radut\/Arduino,ogahara\/Arduino,paulo-raca\/ESP8266-Arduino,zenmanenergy\/Arduino,zenmanenergy\/Arduino,wdoganowski\/Arduino,ssvs111\/Arduino,zenmanenergy\/Arduino,gonium\/Arduino,aichi\/Arduino-2,noahchense\/Arduino-1,leftbrainstrain\/Arduino-ESP8266","old_file":"hardware\/esp8266com\/esp8266\/tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"hardware\/esp8266com\/esp8266\/tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *spiffs*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *spiffs*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"a9e1a80c2451048bd7a0f3f34ce2f2738d93483c","subject":"Allows the heap to grow all the way to the top of the ram for the stm32f1. THis is needed to allow access to the last 4kbyte of heap.","message":"Allows the heap to grow all the way to the top of the ram for the stm32f1. THis is needed to allow access to the last 4kbyte of heap.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/st-stm32f103rb-cmsis\/target.ld","new_file":"boards\/st-stm32f103rb-cmsis\/target.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\nGROUP(\n libgcc.a\n libc.a\n libstdc++.a\n libm.a\n \/*libcr_newlib_nohost.a*\/\n \/*crti.o\n crtn.o\n crtbegin.o\n crtend.o*\/\n )\n\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x08005000, LENGTH = 108K\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\nPROVIDE(__start_ram = ORIGIN(RAM));\nPROVIDE(__end_ram = ORIGIN(RAM) + LENGTH(RAM));\nEXTERN(ignore_fn);\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(SORT(.rodata*))\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    __data_init_start__ = LOADADDR( .data ) ;\n    ASSERT(__data_init_start__ == __etext, \"Initialized data source inconsistent\")\n        \n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n        __cs3_heap_start = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - 0x200;\n    \/* After FreeRTOS boots the original stack is not needed anymore. *\/\n    __cs3_heap_end = ORIGIN(RAM) + LENGTH(RAM);\n    PROVIDE(__stack = __StackTop);\n    PROVIDE(_estack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\nGROUP(\n libgcc.a\n libc.a\n libstdc++.a\n libm.a\n \/*libcr_newlib_nohost.a*\/\n \/*crti.o\n crtn.o\n crtbegin.o\n crtend.o*\/\n )\n\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x08005000, LENGTH = 108K\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\nPROVIDE(__start_ram = ORIGIN(RAM));\nPROVIDE(__end_ram = ORIGIN(RAM) + LENGTH(RAM));\nEXTERN(ignore_fn);\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(SORT(.rodata*))\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    __data_init_start__ = LOADADDR( .data ) ;\n    ASSERT(__data_init_start__ == __etext, \"Initialized data source inconsistent\")\n        \n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n        __cs3_heap_start = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - 0x200;\n    __cs3_heap_end = __StackLimit;\n    PROVIDE(__stack = __StackTop);\n    PROVIDE(_estack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"91e0bdca37df6cdc501e46a8b358e04cfcaf087d","subject":"Align boot code and data to page boundary","message":"Align boot code and data to page boundary\n\nThis paves the way for us to free the physical pages later\n\nSigned-off-by: Dan Schatzberg <2fd18fbc94e1d251ef5884a6fa05a98ae57788ae@gmail.com>\n","repos":"dschatzberg\/genesis,dschatzberg\/genesis","old_file":"src\/arch\/x86_64\/linkerscript.ld","new_file":"src\/arch\/x86_64\/linkerscript.ld","new_contents":"\/*\n  This file is part of Genesis.\n\n  Genesis is free software: you can redistribute it and\/or modify\n  it under the terms of the GNU Affero General Public License as published by\n  the Free Software Foundation, either version 3 of the License, or\n  (at your option) any later version.\n\n  Genesis is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n  GNU Affero General Public License for more details.\n\n  You should have received a copy of the GNU Affero General Public License\n  along with Genesis.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n*\/\n\nENTRY(boot32)\nOUTPUT_FORMAT(elf64-x86-64)\n\nmb_magic = 0x1badb002;\nmb_flags = 0x3;\nmb_checksum = -(mb_magic + mb_flags);\n\nKERNEL_LMA = 1 << 20;\nKERNEL_PHYS_MAP = 0xFFFFFFFFC0000000;\n\nSECTIONS {\n         \/* Lower half *\/\n         . = KERNEL_LMA;\n\n         .mb_header : {\n           LONG(mb_magic)\n           LONG(mb_flags)\n           LONG(mb_checksum)\n         }\n\n         .boot_data : {\n           *(.boot_data*)\n         }\n\n         .boot_text : {\n           *(.boot_text*)\n         }\n\n         \/* Higher half *\/\n         . = ALIGN(4K) + KERNEL_PHYS_MAP;\n         kbegin = . - KERNEL_PHYS_MAP;\n\n         .text ALIGN(4K) : AT(ADDR(.text) - KERNEL_PHYS_MAP) {\n           btext = .;\n           *(.text*)\n         }\n\n         .rodata ALIGN(4K) : AT(ADDR(.rodata) - KERNEL_PHYS_MAP) {\n           etext = .;\n           bro = .;\n           *(.rodata*)\n         }\n\n         .data ALIGN(4K) : AT(ADDR(.data) - KERNEL_PHYS_MAP) {\n           ero = .;\n           bdata = .;\n           *(.data*)\n         }\n\n         .bss ALIGN(4K) : AT(ADDR(.bss) - KERNEL_PHYS_MAP) {\n           *(COMMON)\n           *(.bss*)\n           *(.gnu.linkonce.b*)\n         }\n\n         kend = ALIGN(4K)  - KERNEL_PHYS_MAP;\n         edata = .;\n\n         .debug_abbrev 0 : { KEEP(*(.debug_abbrev)) }\n         .debug_arranges 0 : { KEEP(*(.debug_arranges)) }\n         .debug_frame 0 : { KEEP(*(.debug_frame)) }\n         .debug_info 0 : { KEEP(*(.debug_info)) }\n         .debug_line 0 : { KEEP(*(.debug_line)) }\n         .debug_loc 0 : { KEEP(*(.debug_loc)) }\n         .debug_macinfo 0 : { KEEP(*(.debug_macinfo)) }\n         .debug_pubnames 0 : { KEEP(*(.debug_pubnames)) }\n         .debug_pubtypes 0 : { KEEP(*(.debug_pubtypes)) }\n         .debug_ranges 0 : { KEEP(*(.debug_ranges)) }\n         .debug_str 0 : { KEEP(*(.debug_str))}\n\n         \/DISCARD\/ : {\n           *(.note*)\n           *(.eh_frame*)\n         }\n}\n","old_contents":"\/*\n  This file is part of Genesis.\n\n  Genesis is free software: you can redistribute it and\/or modify\n  it under the terms of the GNU Affero General Public License as published by\n  the Free Software Foundation, either version 3 of the License, or\n  (at your option) any later version.\n\n  Genesis is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n  GNU Affero General Public License for more details.\n\n  You should have received a copy of the GNU Affero General Public License\n  along with Genesis.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n*\/\n\nENTRY(boot32)\nOUTPUT_FORMAT(elf64-x86-64)\n\nmb_magic = 0x1badb002;\nmb_flags = 0x3;\nmb_checksum = -(mb_magic + mb_flags);\n\nKERNEL_LMA = 1 << 20;\nKERNEL_PHYS_MAP = 0xFFFFFFFFC0000000;\n\nSECTIONS {\n         \/* Lower half *\/\n         . = KERNEL_LMA;\n\n         .mb_header : {\n           LONG(mb_magic)\n           LONG(mb_flags)\n           LONG(mb_checksum)\n         }\n\n         .boot_data : {\n           *(.boot_data*)\n         }\n\n         .boot_text : {\n           *(.boot_text*)\n         }\n\n         \/* Higher half *\/\n         . = . + KERNEL_PHYS_MAP;\n         kbegin = . - KERNEL_PHYS_MAP;\n\n         .text ALIGN(4K) : AT(ADDR(.text) - KERNEL_PHYS_MAP) {\n           btext = .;\n           *(.text*)\n         }\n\n         .rodata ALIGN(4K) : AT(ADDR(.rodata) - KERNEL_PHYS_MAP) {\n           etext = .;\n           bro = .;\n           *(.rodata*)\n         }\n\n         .data ALIGN(4K) : AT(ADDR(.data) - KERNEL_PHYS_MAP) {\n           ero = .;\n           bdata = .;\n           *(.data*)\n         }\n\n         .bss ALIGN(4K) : AT(ADDR(.bss) - KERNEL_PHYS_MAP) {\n           *(COMMON)\n           *(.bss*)\n           *(.gnu.linkonce.b*)\n         }\n\n         kend = ALIGN(4K)  - KERNEL_PHYS_MAP;\n         edata = .;\n\n         .debug_abbrev 0 : { KEEP(*(.debug_abbrev)) }\n         .debug_arranges 0 : { KEEP(*(.debug_arranges)) }\n         .debug_frame 0 : { KEEP(*(.debug_frame)) }\n         .debug_info 0 : { KEEP(*(.debug_info)) }\n         .debug_line 0 : { KEEP(*(.debug_line)) }\n         .debug_loc 0 : { KEEP(*(.debug_loc)) }\n         .debug_macinfo 0 : { KEEP(*(.debug_macinfo)) }\n         .debug_pubnames 0 : { KEEP(*(.debug_pubnames)) }\n         .debug_pubtypes 0 : { KEEP(*(.debug_pubtypes)) }\n         .debug_ranges 0 : { KEEP(*(.debug_ranges)) }\n         .debug_str 0 : { KEEP(*(.debug_str))}\n\n         \/DISCARD\/ : {\n           *(.note*)\n           *(.eh_frame*)\n         }\n}\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"32d81dbe6476b9a85440fbd6de1138970c3dcf13","subject":"Modify the liker script to support the IMGTEC toolchain.","message":"Modify the liker script to support the IMGTEC toolchain.\n","repos":"prplfoundation\/prpl-hypervisor,prplfoundation\/prpl-hypervisor,prplfoundation\/prpl-hypervisor,prplfoundation\/prpl-hypervisor,prplfoundation\/prpl-hypervisor,prplfoundation\/prpl-hypervisor","old_file":"hal\/microchip\/pic32mz.ld","new_file":"hal\/microchip\/pic32mz.ld","new_contents":"\/*\nCopyright (c) 2016, prpl Foundation\n\nPermission to use, copy, modify, and\/or distribute this software for any purpose with or without \nfee is hereby granted, provided that the above copyright notice and this permission notice appear \nin all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE\nINCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE \nFOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM \nLOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, \nARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nThis code was written by Sergio Johann at Embedded System Group (GSE) at PUCRS\/Brazil.\n\n*\/\n\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nENTRY(_entry)\n\n\/* specify HF-RISC memory areas *\/\n\nMEMORY \n{\nflash       (rx)  : ORIGIN = 0x9d000000, LENGTH = 2M    \/* Flash area*\/\nram     (rw!x) : ORIGIN = 0x80000000, LENGTH = 512K \/* RAM area. *\/\n}\n\n\/* define a global symbol _stack  *\/\n\n_stack = ORIGIN(ram) + LENGTH(ram);\n\n\/* now define the output sections  *\/\n\nSECTIONS \n{\n    .text :\n    {\n        *(.exception)\n        . = 0x200;\n        *(.vector0)\n        . = 0x1000;\n        _text = .;\n        *(.text)\n            *(.text.*)\n        _etext = .;\n    } > flash\n\n    .MIPS.abiflags : {\n        __MIPS_abiflags_start = .;\n        *(.MIPS.abiflags)\n        __MIPS_abiflags_end = .;\n    } > flash\n\n    .rodata :\n    {\n        _rodata = .;\n        *(.rodata)\n        *(.rodata.*)\n        _erodata = .;\n    } > flash\n\n    .data : AT (ADDR (.rodata) + SIZEOF (.rodata))\n    {\n        _data = .;\n        *(.data)\n        *(.data.*)\n        _gp = .;\n        *(.sdata)\n        *(.sdata.*)\n        . = ALIGN(16); \n    } > ram\n\n    _edata = .;\n\n    .bss :\n    {\n        _bss_start = .; \n        *(.bss) \n        *(.bss.*)\n        *(.sbss) \n        *(.sbss.*)\n        . = ALIGN(4);\n        _bss_end = . ;\n    } > ram\n\n}\n    _end = .;\n\n","old_contents":"\/*\nCopyright (c) 2016, prpl Foundation\n\nPermission to use, copy, modify, and\/or distribute this software for any purpose with or without \nfee is hereby granted, provided that the above copyright notice and this permission notice appear \nin all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE\nINCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE \nFOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM \nLOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, \nARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nThis code was written by Sergio Johann at Embedded System Group (GSE) at PUCRS\/Brazil.\n\n*\/\n\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nENTRY(_entry)\n\n\/* specify HF-RISC memory areas *\/\n\nMEMORY \n{\nflash       (rx)  : ORIGIN = 0x9d000000, LENGTH = 2M    \/* Flash area*\/\nram     (rw!x) : ORIGIN = 0x80000000, LENGTH = 512K \/* RAM area. *\/\n}\n\n\/* define a global symbol _stack  *\/\n\n_stack = ORIGIN(ram) + LENGTH(ram);\n\n\/* now define the output sections  *\/\n\nSECTIONS \n{\n    .text :\n    {\n        *(.exception)\n        . = 0x200;\n        *(.vector0)\n        . = 0x1000;\n        hal\/microchip\/boot.o\n        _text = .;\n        *(.text)\n            *(.text.*)\n        _etext = .;\n    } > flash\n\n    \/*.MIPS.abiflags : {\n        __MIPS_abiflags_start = .;\n        *(.MIPS.abiflags)\n        __MIPS_abiflags_end = .;\n    } > flash*\/\n\n    .rodata :\n    {\n        _rodata = .;\n        *(.rodata)\n        *(.rodata.*)\n        _erodata = .;\n    } > flash\n\n    .data : AT (ADDR (.rodata) + SIZEOF (.rodata))\n    {\n        _data = .;\n        *(.data)\n        *(.data.*)\n        _gp = .;\n        *(.sdata)\n        *(.sdata.*)\n        . = ALIGN(16); \n    } > ram\n\n    _edata = .;\n\n    .bss :\n    {\n        _bss_start = .; \n        *(.bss) \n        *(.bss.*)\n        *(.sbss) \n        *(.sbss.*)\n        . = ALIGN(4);\n        _bss_end = . ;\n    } > ram\n\n}\n    _end = .;\n\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"d72aedf7b1ef29b3a0c99fd415231b1828ec3076","subject":"Store .rodata in flash by default","message":"Store .rodata in flash by default\n\nCloses #11\n","repos":"urx\/esp-open-rtos,kanflo\/esp-open-rtos,Zaltora\/esp-open-rtos,alainmaes\/esp-open-rtos,DCoJA\/esp-open-rtos,Zaltora\/esp-open-rtos,SuperHouse\/esp-open-rtos,kanflo\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,alainmaes\/esp-open-rtos,Zaltora\/esp-open-rtos,SuperHouse\/esp-open-rtos,urx\/esp-open-rtos,urx\/esp-open-rtos,hawkhsieh\/esp-open-rtos,hawkhsieh\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,mr-nice\/esp-open-rtos,urx\/esp-open-rtos,ourairquality\/esp-open-rtos,someburner\/esp-rtos-tests,someburner\/esp-rtos-tests,SuperHouse\/esp-open-rtos,kanflo\/esp-open-rtos,DCoJA\/esp-open-rtos,Zaltora\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,andree182\/esp-open-rtos,andree182\/esp-open-rtos,andree182\/esp-open-rtos,andree182\/esp-open-rtos,SuperHouse\/esp-open-rtos,Zaltora\/esp-open-rtos,DCoJA\/esp-open-rtos,mr-nice\/esp-open-rtos,UncleRus\/esp-open-rtos,kanflo\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,SuperHouse\/esp-open-rtos,ourairquality\/esp-open-rtos,kanflo\/esp-open-rtos,UncleRus\/esp-open-rtos,alainmaes\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,sheinz\/esp-open-rtos,ourairquality\/esp-open-rtos,alainmaes\/esp-open-rtos,sheinz\/esp-open-rtos,hawkhsieh\/esp-open-rtos,someburner\/esp-rtos-tests,sheinz\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,hawkhsieh\/esp-open-rtos,mr-nice\/esp-open-rtos,UncleRus\/esp-open-rtos,Zaltora\/esp-open-rtos,mr-nice\/esp-open-rtos,kanflo\/esp-open-rtos,UncleRus\/esp-open-rtos,urx\/esp-open-rtos,sheinz\/esp-open-rtos,SuperHouse\/esp-open-rtos,UncleRus\/esp-open-rtos,ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos,urx\/esp-open-rtos,DCoJA\/esp-open-rtos,UncleRus\/esp-open-rtos,someburner\/esp-rtos-tests,chaisme\/esp8266_FreeRTOS,ourairquality\/esp-open-rtos","old_file":"ld\/common.ld","new_file":"ld\/common.ld","new_contents":"\/*\n * Common (OTA and non-OTA) parts for the esp-open-rtos Linker Script\n *\n *\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* FreeRTOS lock functions.\n\n   Rely on a patch to libc that produces weak linked versions of the\n   below symbols. Currently treating locking primitives like universal\n   global critical section rather than individual locks, but this seems\n   OK from the use cases in newlib.\n*\/\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    . = ALIGN (16);\n    *(.vecbase.text)\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* esp-open-rtos compiled source files use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *sdklib*:*(.literal .text .literal.* .text.*)\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    \/* xthal_set_intset() called from PendSV in NMI context *\/\n    *libhal.a:*set_intset.o(.literal .text .literal.* .text.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  \/* rodata in DRAM\n\n     cherry-picked compilation units that need rodata\n     to be in DRAM - anything that may be run while\n     SPI flash is unmapped (ie IRAM functions that are\n     called from interrupt context or spi flash management\n     functions) need their compilation units listed here.\n\n     If you have constant data that is performance-critical,\n     list the compilation unit(s) here as well.\n  *\/\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    \/* Store all of core, libc, freertos .rodata in RAM by default\n       (some parts are necessary, some parts for performance reasons.)\n    *\/\n    *core.a:*(.rodata.* .rodata) *libc.a:*.o(.rodata.* .rodata)\n    *freertos.a:*(.rodata.* .rodata)\n\n    \/* spi flash management rodata needs to be accessed\n       while flash is unmapped. *\/\n    *libmain.a:spi_flash.o(.rodata.* .rodata)\n\n    \/* libpp wdev.o has the NMI handler (sdk_wDev_ProcessFiq)\n       which runs at all times, flash mapped or not. *\/\n    *libpp.a:wdev.o(.rodata.* .rodata)\n\n    _rodata_end = ABSOLUTE(.);\n  } > dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n\n   \/* All data that goes to flash (IROM) ends up in this section *\/\n  .irom0.text : ALIGN(4)\n  {\n    \/*****************************\n     * Actual irom0 text section *\n     *****************************\/\n\n    _irom0_text_start = ABSOLUTE(.);\n    \/* esp-open-rtos compiled code goes into IROM by default\n       (except for libgcc which is matched above.)\n\n       We also link .rodata here in the hope that data is stored near\n       its code on the flash (in practice this doesn't quite happen. :\/)\n    *\/\n    *(.literal .text .literal.* .text.* .rodata .rodata.*)\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom.* .irom.*.* .irom0.*)\n    _irom0_text_end = ABSOLUTE(.);\n\n    \/**************************************************************\n      C++ constructor and destructor tables, properly ordered:\n     **************************************************************\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    \/***********************************\n       C++ exception handlers table:  *\n     **********************************\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n\n    \/***********************************\n     Additional .rodata special sections\n     stored in flash\n     ************************************\/\n    . = ALIGN(4);\n    *(.gnu.linkonce.r.*)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = ALIGN(4);\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n  } > irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","old_contents":"\/*\n * Common (OTA and non-OTA) parts for the esp-open-rtos Linker Script\n *\n *\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* FreeRTOS lock functions.\n\n   Rely on a patch to libc that produces weak linked versions of the\n   below symbols. Currently treating locking primitives like universal\n   global critical section rather than individual locks, but this seems\n   OK from the use cases in newlib.\n*\/\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    . = ALIGN (16);\n    *(.vecbase.text)\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* esp-open-rtos compiled source files use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *sdklib*:*(.literal .text .literal.* .text.*)\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    \/* xthal_set_intset() called from PendSV in NMI context *\/\n    *libhal.a:*set_intset.o(.literal .text .literal.* .text.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    \/* esp-open-rtos compiled code goes into IROM by default\n       (except for libgcc which is matched above.)\n    *\/\n    *(.literal .text .literal.* .text.*)\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom.* .irom.*.* .irom0.*)\n    _irom0_text_end = ABSOLUTE(.);\n\n    \/* Temporary .rodata hacks start here, eventually all rodata will\n    be in irom by default *\/\n    \/* mbedtls rodata *\/\n    *mbedtls.a:*.o(.rodata.* .rodata)\n    \/* actual certificate in example (TEMPORARY HACK) *\/\n    *:cert.o(.rodata.* .rodata)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n\n  } >irom0_0_seg :irom0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"84d85d7f15f775b871328eed583317e61bce079e","subject":"reserve last two pages for constants by shrinking size of flash.ld NVM space","message":"reserve last two pages for constants by shrinking size of flash.ld NVM space\n","repos":"analogdevicesinc\/m1k-fw,analogdevicesinc\/m1k-fw,analogdevicesinc\/m1k-fw,analogdevicesinc\/m1k-fw","old_file":"scripts\/flash.ld","new_file":"scripts\/flash.ld","new_contents":"\/**\n * \\file\n *\n * \\brief Flash Linker script for SAM.\n *\n * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.\n *\n * \\asf_license_start\n *\n * \\page License\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n *    this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n *    this list of conditions and the following disclaimer in the documentation\n *    and\/or other materials provided with the distribution.\n *\n * 3. The name of Atmel may not be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * 4. This software may only be redistributed and used in connection with an\n *    Atmel microcontroller product.\n *\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n * \\asf_license_stop\n *\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n\tflash  (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000-512 \/* Flash, 128K *\/\n\tsram0  (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00004000 \/* Sram0, 16K *\/\n\tsram1  (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 \/* Sram1, 16K *\/\n\/*\trom (rx)    : ORIGIN = ORIGIN(flash), LENGTH = LENGTH(flash) *\/ \/* Flash, 64K *\/\n\/*\tram (rwx)   : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) *\/ \/* sram, 16K *\/\n\trom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00020000-512 \/* Flash, 128K *\/\n\tram (rwx)   : ORIGIN = 0x2007E000, LENGTH = 0x00008000 \/* sram, 32K *\/\n}\n\n\/* The stack size used by the application. NOTE: you need to adjust  *\/\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > flash\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > flash\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","old_contents":"\/**\n * \\file\n *\n * \\brief Flash Linker script for SAM.\n *\n * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.\n *\n * \\asf_license_start\n *\n * \\page License\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n *    this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n *    this list of conditions and the following disclaimer in the documentation\n *    and\/or other materials provided with the distribution.\n *\n * 3. The name of Atmel may not be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * 4. This software may only be redistributed and used in connection with an\n *    Atmel microcontroller product.\n *\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n * \\asf_license_stop\n *\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n\tflash  (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 \/* Flash, 128K *\/\n\tsram0  (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00004000 \/* Sram0, 16K *\/\n\tsram1  (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 \/* Sram1, 16K *\/\n\/*\trom (rx)    : ORIGIN = ORIGIN(flash), LENGTH = LENGTH(flash) *\/ \/* Flash, 64K *\/\n\/*\tram (rwx)   : ORIGIN = ORIGIN( sram1)-LENGTH( sram0), LENGTH = LENGTH( sram0)+LENGTH( sram1) *\/ \/* sram, 16K *\/\n\trom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00020000 \/* Flash, 128K *\/\n\tram (rwx)   : ORIGIN = 0x2007E000, LENGTH = 0x00008000 \/* sram, 32K *\/\n}\n\n\/* The stack size used by the application. NOTE: you need to adjust  *\/\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > flash\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > flash\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"362f5d099f2b6218b902ce098f0b04363fa81283","subject":"config.ld: change configuration for manual -> topics","message":"config.ld: change configuration for manual -> topics\n","repos":"RyanSquared\/FusionScript","old_file":"config.ld","new_file":"config.ld","new_contents":"-- luacheck: ignore\nfile = {'bin', 'fusion'} -- vim:set noet sts=0 sw=3 ts=3 filetype=lua:\ndir = 'docs'\nproject = 'FusionScript'\ndescription = 'The programming language of ultimate dankliness'\ntitle = 'FusionScript &middot; Documentation'\nstyle = 'docs\/style'\ntopics = {\n\t'.topics\/FusionScript.md';\n\t'.topics\/Syntax.md';\n}\nkind_names = {script='Programs'}\nall = true\nformat = 'markdown'\n","old_contents":"-- luacheck: ignore\nfile = {'bin', 'fusion'} -- vim:set noet sts=0 sw=3 ts=3 filetype=lua:\ndir = 'docs'\nproject = 'FusionScript'\ndescription = 'The programming language of ultimate dankliness'\ntitle = 'FusionScript &middot; Documentation'\nstyle = 'docs\/style'\ntopics = {\n\t'.topics\/FusionScript.md';\n\t'.topics\/Syntax.md';\n}\nkind_names = {topic='Manual', script='Programs'}\nall = true\nformat = 'markdown'\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7b9009ca5c25fa8007a55aa16d40727c0313aec7","subject":"bootloader: Fix secure boot & flash encryption functionality","message":"bootloader: Fix secure boot & flash encryption functionality\n\nFixes regression in 3e0ac4db79.\n","repos":"mashaoze\/esp-idf,www220\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf,armada-ai\/esp-idf,armada-ai\/esp-idf,www220\/esp-idf,espressif\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,armada-ai\/esp-idf,www220\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/esp32.bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/esp32.bootloader.ld","new_contents":"\/*\nLinker file used to link the bootloader.\n*\/\n\n\n\/* Simplified memory map for the bootloader\n\n   The main purpose is to make sure the bootloader can load into main memory\n   without overwriting itself.\n*\/\n\nMEMORY\n{\n  \/* I\/O *\/\n  dport0_seg (RW) :                 \torg = 0x3FF00000, len = 0x10\n  \/* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache *\/\n  iram_loader_seg (RWX) :           org = 0x40078000, len = 0x8000  \/* 32KB, APP CPU cache *\/\n  \/* 63kB, IRAM. We skip the first 1k to prevent the entry point being\n     placed into the same range as exception vectors in the app.\n     This leads to idf_monitor decoding ROM bootloader \"entry 0x40080xxx\"\n     message as one of the exception vectors, which looks scary to users.\n  *\/\n  iram_seg (RWX) :                  org = 0x40080400, len = 0xfc00\n  \/* 64k at the end of DRAM, after ROM bootloader stack *\/\n  dram_seg (RW) :                  \torg = 0x3FFF0000, len = 0x10000\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:efuse.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures.o(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.o(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.o(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","old_contents":"\/*\nLinker file used to link the bootloader.\n*\/\n\n\n\/* Simplified memory map for the bootloader\n\n   The main purpose is to make sure the bootloader can load into main memory\n   without overwriting itself.\n*\/\n\nMEMORY\n{\n  \/* I\/O *\/\n  dport0_seg (RW) :                 \torg = 0x3FF00000, len = 0x10\n  \/* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache *\/\n  iram_loader_seg (RWX) :           org = 0x40078000, len = 0x8000  \/* 32KB, APP CPU cache *\/\n  \/* 63kB, IRAM. We skip the first 1k to prevent the entry point being\n     placed into the same range as exception vectors in the app.\n     This leads to idf_monitor decoding ROM bootloader \"entry 0x40080xxx\"\n     message as one of the exception vectors, which looks scary to users.\n  *\/\n  iram_seg (RWX) :                  org = 0x40080400, len = 0xfc00\n  \/* 64k at the end of DRAM, after ROM bootloader stack *\/\n  dram_seg (RW) :                  \torg = 0x3FFF0000, len = 0x10000\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.o(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_loader_seg\n  \n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ed4d48f80dbb8b922c0c7923730f26f0dfe03ef6","subject":"artik053\/scripts : mark .init_array section using KEEP directive","message":"artik053\/scripts : mark .init_array section using KEEP directive\n\nTo mark .init_array section not be eliminated  by garbage\ncollector(--gc-sections), .init_array sections is kept using\nKEEP linker directive\n\nSigned-off-by: Manohara HK <02db916c8fbcb3f412fbcb70556ea7b9f661857a@samsung.com>\n","repos":"jeongchanKim\/TizenRT,JeonginKim\/TizenRT,btheosam\/TizenRT,chanijjani\/TizenRT,an4967\/TizenRT,chanijjani\/TizenRT,jeongarmy\/TizenRT,jeongarmy\/TizenRT,pillip8282\/TizenRT,davidfather\/TizenRT,junmin-kim\/TizenRT,jsdosa\/TizenRT,jeongarmy\/TizenRT,jeongchanKim\/TizenRT,jeongchanKim\/TizenRT,chanijjani\/TizenRT,jsdosa\/TizenRT,lokeshbv\/TizenRT,sunghan-chang\/TizenRT,sunghan-chang\/TizenRT,HONGCHAEHEE\/TizenRT,Samsung\/TizenRT,HONGCHAEHEE\/TizenRT,jeongarmy\/TizenRT,jsdosa\/TizenRT,an4967\/TizenRT,sunghan-chang\/TizenRT,lokeshbv\/TizenRT,HONGCHAEHEE\/TizenRT,btheosam\/TizenRT,davidfather\/TizenRT,btheosam\/TizenRT,davidfather\/TizenRT,davidfather\/TizenRT,jeongchanKim\/TizenRT,davidfather\/TizenRT,jeongarmy\/TizenRT,Samsung\/TizenRT,pillip8282\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,Samsung\/TizenRT,lokeshbv\/TizenRT,chanijjani\/TizenRT,junmin-kim\/TizenRT,sunghan-chang\/TizenRT,jeongchanKim\/TizenRT,lokeshbv\/TizenRT,sunghan-chang\/TizenRT,junmin-kim\/TizenRT,an4967\/TizenRT,HONGCHAEHEE\/TizenRT,JeonginKim\/TizenRT,jsdosa\/TizenRT,lokeshbv\/TizenRT,jeongarmy\/TizenRT,JeonginKim\/TizenRT,btheosam\/TizenRT,JeonginKim\/TizenRT,pillip8282\/TizenRT,HONGCHAEHEE\/TizenRT,pillip8282\/TizenRT,an4967\/TizenRT,btheosam\/TizenRT,junmin-kim\/TizenRT,davidfather\/TizenRT,an4967\/TizenRT,jeongchanKim\/TizenRT,an4967\/TizenRT,junmin-kim\/TizenRT,Samsung\/TizenRT,chanijjani\/TizenRT,junmin-kim\/TizenRT,sunghan-chang\/TizenRT,JeonginKim\/TizenRT,Samsung\/TizenRT,JeonginKim\/TizenRT,chanijjani\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,HONGCHAEHEE\/TizenRT,lokeshbv\/TizenRT,chanijjani\/TizenRT,jeongarmy\/TizenRT,sunghan-chang\/TizenRT,jeongchanKim\/TizenRT,jsdosa\/TizenRT,junmin-kim\/TizenRT,pillip8282\/TizenRT,jsdosa\/TizenRT,an4967\/TizenRT,btheosam\/TizenRT,davidfather\/TizenRT,jsdosa\/TizenRT","old_file":"build\/configs\/artik053\/scripts\/flash.ld","new_file":"build\/configs\/artik053\/scripts\/flash.ld","new_contents":"\/****************************************************************************\n *\n * Copyright 2017 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * configs\/artik053\/scripts\/flash.ld\n *\n *   Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *           Laurent Latil <laurent@latil.nom.fr>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nMEMORY\n{\n\tFLASH\t(rx)\t: ORIGIN = 0x040C8000, LENGTH = 2400K\n\tSRAM\t(rwx)\t: ORIGIN = 0x02023800, LENGTH = 946K\n}\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_stext)\nSECTIONS\n{\n\t.header : {\n\t\t_start = .;\n\t\tLONG((_end - _start) \/ 512);\n\t\tLONG(0);\n\t\tLONG(0x656d6264);\n\t\t. = ALIGN(0x20);\n\t} > FLASH =0x0\n\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > FLASH\n\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\tKEEP(*(.init_array .init_array.*))\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > SRAM AT > FLASH\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > SRAM\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.padding : {\n\t\t. = ALIGN(512);\n\t\t. = . + 1020;\n\t\tLONG(0);\n\t\t_end = .;\n\t} > FLASH =0x0\n}\n","old_contents":"\/****************************************************************************\n *\n * Copyright 2017 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * configs\/artik053\/scripts\/flash.ld\n *\n *   Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *           Laurent Latil <laurent@latil.nom.fr>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nMEMORY\n{\n\tFLASH\t(rx)\t: ORIGIN = 0x040C8000, LENGTH = 2400K\n\tSRAM\t(rwx)\t: ORIGIN = 0x02023800, LENGTH = 946K\n}\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_stext)\nSECTIONS\n{\n\t.header : {\n\t\t_start = .;\n\t\tLONG((_end - _start) \/ 512);\n\t\tLONG(0);\n\t\tLONG(0x656d6264);\n\t\t. = ALIGN(0x20);\n\t} > FLASH =0x0\n\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > FLASH\n\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\t*(.init_array .init_array.*)\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > SRAM AT > FLASH\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > SRAM\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.padding : {\n\t\t. = ALIGN(512);\n\t\t. = . + 1020;\n\t\tLONG(0);\n\t\t_end = .;\n\t} > FLASH =0x0\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ef4623bea195d4a573ee85b320dff82669bfc22d","subject":"Hello there, the development may be back in weeks","message":"Hello there, the development may be back in weeks\n","repos":"IcebergOS\/Cryst,IcebergOS\/frogimine,IcebergOS\/frogimine","old_file":"scripts\/linker.ld","new_file":"scripts\/linker.ld","new_contents":"ENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t\t. = ALIGN(4096);\n\t}\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(4096);\n\t}\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t. = ALIGN(4096);\n\t}\n\t.stab :\n\t{\n\t\t*(.stab)\n\t\t. = ALIGN(4096);\n\t}\n\t.stabstr :\n\t{\n\t\t*(.stabstr)\n\t\t. = ALIGN(4096);\n\t}\n\t\n\t\/DISCARD\/ : { *(.comment) *(.eh_frame) }\n}\n\n","old_contents":"ENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t\t. = ALIGN(4096);\n\t}\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(4096);\n\t}\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t. = ALIGN(4096);\n\t}\n\t.stab :\n\t{\n\t\t*(.stab)\n\t\t. = ALIGN(4096);\n\t}\n\t.stabstr :\n\t{\n\t\t*(.stabstr)\n\t \t. = ALIGN(4096);\n\t}\n\t\n\t\/DISCARD\/ : { *(.comment) *(.eh_frame) }\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2fa156f5314bc1022f54ad729198fe51ecf63888","subject":"Skip calling wrappers from a number of the ROM functions.","message":"Skip calling wrappers from a number of the ROM functions.\n\nA number of the ROM functions were pointing to wrappers that saved and\nrestored the $a0 register, but the functions they called either did\nnot use $a0 or saved and restored $a0 as needed anyway.\n","repos":"ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos","old_file":"ld\/rom.ld","new_file":"ld\/rom.ld","new_contents":"\/* Linker script containing Boot ROM functions for ESP8266\n\n   For more information, see:\n\n   http:\/\/esp8266-re.foogod.com\/wiki\/Boot_ROM\n   https:\/\/github.com\/jcmvbkbc\/esp-elf-rom\/\n*\/\n\nPROVIDE ( SPI_sector_erase = 0x400040c0 );\nPROVIDE ( SPI_page_program = 0x40004174 );\nPROVIDE ( SPI_read_data = 0x400042ac );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( Disable_QMode = 0x40004508 );\n\n\/* When using OTA, Cache_Read_Enable is defined in extras\/rboot-ota so\n   the ROM Cache_Read_Enable isn't picked up from here. However we\n   also provide access to the ROM function in all cases, via the name\n   rom_Cache_Read_Enable *\/\nPROVIDE ( rom_Cache_Read_Enable = 0x40004678 );\nPROVIDE ( Cache_Read_Enable = rom_Cache_Read_Enable );\n\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\n\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\n\n\/* TODO: Nearly everything below here is probably provided by the\n   libc, so never linked in, and can therefore be removed. *\/\n\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\n\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\n\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\n\nPROVIDE ( ETS_INTR_LOCK = 0x40000f74 );\nPROVIDE ( ETS_INTR_UNLOCK = 0x40000f80 );\n","old_contents":"\/* Linker script containing Boot ROM functions for ESP8266\n\n   For more information, see:\n\n   http:\/\/esp8266-re.foogod.com\/wiki\/Boot_ROM\n   https:\/\/github.com\/jcmvbkbc\/esp-elf-rom\/\n*\/\n\nPROVIDE ( SPI_sector_erase = 0x400040c0 );\nPROVIDE ( SPI_page_program = 0x40004174 );\nPROVIDE ( SPI_read_data = 0x400042ac );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( Disable_QMode = 0x40004508 );\n\n\/* When using OTA, Cache_Read_Enable is defined in extras\/rboot-ota so\n   the ROM Cache_Read_Enable isn't picked up from here. However we\n   also provide access to the ROM function in all cases, via the name\n   rom_Cache_Read_Enable *\/\nPROVIDE ( rom_Cache_Read_Enable = 0x40004678 );\nPROVIDE ( Cache_Read_Enable = rom_Cache_Read_Enable );\n\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\n\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\n\n\/* TODO: Nearly everything below here is probably provided by the\n   libc, so never linked in, and can therefore be removed. *\/\n\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\n\nPROVIDE ( bzero = 0x40002ae8 );\nPROVIDE ( memcmp = 0x400018d4 );\nPROVIDE ( memcpy = 0x400018b4 );\nPROVIDE ( memmove = 0x400018c4 );\nPROVIDE ( memset = 0x400018a4 );\n\nPROVIDE ( strcmp = 0x40002aa8 );\nPROVIDE ( strcpy = 0x40002a88 );\nPROVIDE ( strlen = 0x40002ac8 );\nPROVIDE ( strncmp = 0x40002ab8 );\nPROVIDE ( strncpy = 0x40002a98 );\nPROVIDE ( strstr = 0x40002ad8 );\n\nPROVIDE ( ETS_INTR_LOCK = 0x40000f74 );\nPROVIDE ( ETS_INTR_UNLOCK = 0x40000f80 );\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"cee16768667277d4262460d0dcfad5c9cb9ee758","subject":"fix(x86_64\/linker.ld): page align the multiboot header section","message":"fix(x86_64\/linker.ld): page align the multiboot header section\n\n(so that remapping the kernel doesn't go to hell)\n","repos":"hawkw\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel,rachlmac\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .rodata :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n        *(.rodata .rodata.*)\n        . = ALIGN(4K);\n    }\n\n    .text ALIGN(4K) :\n    {\n     \/* NOTE we use KEEP here to prevent the linker from dropping\n        these symbols\n      *\/\n        KEEP(*(.text._start))\n        KEEP(*(.text.arch_init))\n        *(.text .text.*)\n    }\n\n     .data ALIGN(4K) :\n     {\n       *(.data .data.*)\n     }\n\n     .bss ALIGN(4K) :\n     {\n\n        *(.bss .bss.*)\n        . = ALIGN(4K);\n\n        \/* Page-Map Level-4 Table (PML4) *\/\n        pml4_table = .;\n        . += 4K;\n        \/* Page-Directory Pointer Table (PDP) *\/\n        pdp_table = .;\n        . += 4K;\n        \/* Page-Directory Table (PD) *\/\n        pd_table = .;\n        . += 4K;\n\n        stack_base = .;\n        . += 4K * 8;\n        stack_top = .;\n\n        heap_base_addr = .;\n        . += 4K * 2K;\n        heap_top_addr = .;\n     }\n\n    .got :\n    {\n      *(.got)\n      . = ALIGN(4K);\n    }\n\n    .got.plt :\n    {\n      *(.got.plt)\n      . = ALIGN(4K);\n    }\n\n    .data.rel.ro : ALIGN(4K) {\n      *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n      . = ALIGN(4K);\n    }\n\n    .gcc_except_table : ALIGN(4K) {\n      *(.gcc_except_table)\n      . = ALIGN(4K);\n}\n}\n","old_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .rodata :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n        *(.rodata .rodata.*)\n    }\n\n    .text ALIGN(4K) :\n    {\n     \/* NOTE we use KEEP here to prevent the linker from dropping\n        these symbols\n      *\/\n        KEEP(*(.text._start))\n        KEEP(*(.text.arch_init))\n        *(.text .text.*)\n    }\n\n     .data ALIGN(4K) :\n     {\n       *(.data .data.*)\n     }\n\n     .bss ALIGN(4K) :\n     {\n\n        *(.bss .bss.*)\n        . = ALIGN(4K);\n\n        \/* Page-Map Level-4 Table (PML4) *\/\n        pml4_table = .;\n        . += 4096;\n        \/* Page-Directory Pointer Table (PDP) *\/\n        pdp_table = .;\n        . += 4096;\n        \/* Page-Directory Table (PD) *\/\n        pd_table = .;\n        . += 4096;\n\n        stack_base = .;\n        . += 4K * 2;\n        stack_top = .;\n\n        heap_base_addr = .;\n        . += 4K * 2K;\n        heap_top_addr = .;\n     }\n\n    .data.rel.ro : ALIGN(4K) {\n       *(.data.rel.ro.local*)\n       *(.data.rel.ro .data.rel.ro.*)\n    }\n\n    .gcc_except_table : ALIGN(4K) {\n      *(.gcc_except_table)\n      . = ALIGN(4096);\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"70d59c2529a1b2369110c7156bdbbcdb1a4fb51e","subject":"Move .rodata section to mirror area","message":"Move .rodata section to mirror area\n","repos":"msalau\/rl78-samples-R5F104FEAFP,msalau\/rl78-samples-R5F104FEAFP","old_file":"common\/R5F104xE.ld","new_file":"common\/R5F104xE.ld","new_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/G14 R5F104xE, 64k flash, 5.5k ram, 4k data flash *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007c\n\tOPT (r)   : ORIGIN = 0x000c0, LENGTH = 0x00004\n\tROM (r)   : ORIGIN = 0x000d8, LENGTH = 0x0ff28\n\tRAM (w)   : ORIGIN = 0xfe900, LENGTH = 0x015e0\n\tSTACK (w) : ORIGIN = 0xffee0, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n  .opt :\n  {\n    BYTE(0x6e)\n    BYTE(0xff)\n    BYTE(0xe9)\n    BYTE(0x04)\n  } > OPT\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  .rodata (MAX(__romdatastart + __romdatacopysize, 0x2000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > ROM\n\n  .text :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(EXCLUDE_FILE (*crtbegin*.o *crtend*.o) .init))\n    KEEP (*(.fini))\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/G14 R5F104xE, 64k flash, 5.5k ram, 4k data flash *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007c\n\tOPT (r)   : ORIGIN = 0x000c0, LENGTH = 0x00004\n\tROM (r)   : ORIGIN = 0x000d8, LENGTH = 0x0ff28\n\tRAM (w)   : ORIGIN = 0xfe900, LENGTH = 0x015e0\n\tSTACK (w) : ORIGIN = 0xffee0, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n  .opt :\n  {\n    BYTE(0x6e)\n    BYTE(0xff)\n    BYTE(0xe9)\n    BYTE(0x04)\n  } > OPT\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > ROM\n\n  .text :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(EXCLUDE_FILE (*crtbegin*.o *crtend*.o) .init))\n    KEEP (*(.fini))\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"76aec623e5c636472416045d7e422abdb1dbec08","subject":"provide the symbol which signifies end of static data","message":"provide the symbol which signifies end of static data\n","repos":"ayourtch\/ayos,ayourtch\/ayos,ayourtch\/ayos","old_file":"kernel\/kernel64.ld","new_file":"kernel\/kernel64.ld","new_contents":"OUTPUT_FORMAT(\"binary\")\r\nENTRY(main)\r\nSECTIONS\r\n{\r\n\t.text 0x0000000000100000 :\r\n\t{\r\n\t\t*(.text)\r\n\t}\r\n\t.data :\r\n\t{\r\n\t\t*(.data)\r\n\t}\r\n\t.bss :\r\n\t{\r\n\t\t*(.bss)\r\n\t}\r\n\t_end = .;\r\n\tPROVIDE(_end = .);\r\n}\r\n","old_contents":"OUTPUT_FORMAT(\"binary\")\r\nENTRY(main)\r\nSECTIONS\r\n{\r\n\t.text 0x0000000000100000 :\r\n\t{\r\n\t\t*(.text)\r\n\t}\r\n\t.data :\r\n\t{\r\n\t\t*(.data)\r\n\t}\r\n\t.bss :\r\n\t{\r\n\t\t*(.bss)\r\n\t}\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"496e7274980cdeea881f0b22f5f7206035f37884","subject":"update GNU ld script.","message":"update GNU ld script.\n\ngit-svn-id: 839522a79b1d56a78fa446d2fd3a0c499f8e535e@1558 bbd45198-f89e-11dd-88c7-29a3b14d5316\n","repos":"RT-Thread\/rt-thread,zhaojuntao\/rt-thread,yongli3\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,AubrCool\/rt-thread,wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,AubrCool\/rt-thread,igou\/rt-thread,yongli3\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,yongli3\/rt-thread,hezlog\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,yongli3\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,zhaojuntao\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,igou\/rt-thread,igou\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,AubrCool\/rt-thread,weiyuliang\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,AubrCool\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,armink\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,zhaojuntao\/rt-thread,zhaojuntao\/rt-thread,armink\/rt-thread,wolfgangz2013\/rt-thread,yongli3\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,igou\/rt-thread,geniusgogo\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,armink\/rt-thread,FlyLu\/rt-thread,zhaojuntao\/rt-thread,wolfgangz2013\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread","old_file":"bsp\/stm32f107\/stm32_rom.ld","new_file":"bsp\/stm32f107\/stm32_rom.ld","new_contents":"\/*\r\n * linker script for STM32F107 (256kB Flash, 64kB SRAM ) with GNU ld\r\n * bernard.xiong 2009-10-14\r\n *\/\r\n\r\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\r\nMEMORY\r\n{\r\n    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 0x00040000\r\n    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000\r\n}\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        KEEP(*(.isr_vector))            \/* Startup code *\/\r\n        . = ALIGN(4);\r\n        *(.text)                        \/* remaining code *\/\r\n        *(.text.*)                      \/* remaining code *\/\r\n        *(.rodata)                      \/* read-only data (constants) *\/\r\n        *(.rodata*)\r\n        *(.glue_7)\r\n        *(.glue_7t)\r\n        *(.gnu.linkonce.t*)\r\n\r\n        \/* section information for finsh shell *\/\r\n        . = ALIGN(4);\r\n        __fsymtab_start = .;\r\n        KEEP(*(FSymTab))\r\n        __fsymtab_end = .;\r\n        . = ALIGN(4);\r\n        __vsymtab_start = .;\r\n        KEEP(*(VSymTab))\r\n        __vsymtab_end = .;\r\n        . = ALIGN(4);\r\n\r\n        . = ALIGN(4);\r\n        _etext = .;\r\n    } > CODE = 0\r\n\r\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n    __exidx_start = .;\r\n    .ARM.exidx :\r\n    {\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sidata = .;\r\n    } > CODE\r\n    __exidx_end = .;\r\n\r\n    \/* .data section which is used for initialized data *\/\r\n\r\n    .data : AT (_sidata)\r\n    {\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sdata = . ;\r\n\r\n        *(.data)\r\n        *(.data.*)\r\n        *(.gnu.linkonce.d*)\r\n\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _edata = . ;\r\n    } >DATA\r\n\r\n    __bss_start = .;\r\n    .bss :\r\n    {\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _sbss = .;\r\n\r\n        *(.bss)\r\n        *(.bss.*)\r\n        *(COMMON)\r\n\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _ebss = . ;\r\n        _estack = .;\r\n        \r\n        *(.bss.init)\r\n    } > DATA\r\n    __bss_end = .;\r\n\r\n    _end = .;\r\n\r\n    \/* Stabs debugging sections.  *\/\r\n    .stab          0 : { *(.stab) }\r\n    .stabstr       0 : { *(.stabstr) }\r\n    .stab.excl     0 : { *(.stab.excl) }\r\n    .stab.exclstr  0 : { *(.stab.exclstr) }\r\n    .stab.index    0 : { *(.stab.index) }\r\n    .stab.indexstr 0 : { *(.stab.indexstr) }\r\n    .comment       0 : { *(.comment) }\r\n    \/* DWARF debug sections.\r\n     * Symbols in the DWARF debugging sections are relative to the beginning\r\n     * of the section so we begin them at 0.  *\/\r\n    \/* DWARF 1 *\/\r\n    .debug          0 : { *(.debug) }\r\n    .line           0 : { *(.line) }\r\n    \/* GNU DWARF 1 extensions *\/\r\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n    .debug_sfnames  0 : { *(.debug_sfnames) }\r\n    \/* DWARF 1.1 and DWARF 2 *\/\r\n    .debug_aranges  0 : { *(.debug_aranges) }\r\n    .debug_pubnames 0 : { *(.debug_pubnames) }\r\n    \/* DWARF 2 *\/\r\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n    .debug_abbrev   0 : { *(.debug_abbrev) }\r\n    .debug_line     0 : { *(.debug_line) }\r\n    .debug_frame    0 : { *(.debug_frame) }\r\n    .debug_str      0 : { *(.debug_str) }\r\n    .debug_loc      0 : { *(.debug_loc) }\r\n    .debug_macinfo  0 : { *(.debug_macinfo) }\r\n    \/* SGI\/MIPS DWARF 2 extensions *\/\r\n    .debug_weaknames 0 : { *(.debug_weaknames) }\r\n    .debug_funcnames 0 : { *(.debug_funcnames) }\r\n    .debug_typenames 0 : { *(.debug_typenames) }\r\n    .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","old_contents":"\/*\r\n * linker script for STM32F10x with GNU ld\r\n * bernard.xiong 2009-10-14\r\n *\/\r\n\r\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\r\nMEMORY\r\n{\r\n    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 0x00080000\r\n    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000\r\n}\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        KEEP(*(.isr_vector))            \/* Startup code *\/\r\n        . = ALIGN(4);\r\n        *(.text)                        \/* remaining code *\/\r\n        *(.text.*)                      \/* remaining code *\/\r\n        *(.rodata)                      \/* read-only data (constants) *\/\r\n        *(.rodata*)\r\n        *(.glue_7)\r\n        *(.glue_7t)\r\n        *(.gnu.linkonce.t*)\r\n\r\n        \/* section information for finsh shell *\/\r\n        . = ALIGN(4);\r\n        __fsymtab_start = .;\r\n        KEEP(*(FSymTab))\r\n        __fsymtab_end = .;\r\n        . = ALIGN(4);\r\n        __vsymtab_start = .;\r\n        KEEP(*(VSymTab))\r\n        __vsymtab_end = .;\r\n        . = ALIGN(4);\r\n\r\n        . = ALIGN(4);\r\n        _etext = .;\r\n    } > CODE = 0\r\n\r\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n    __exidx_start = .;\r\n    .ARM.exidx :\r\n    {\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sidata = .;\r\n    } > CODE\r\n    __exidx_end = .;\r\n\r\n    \/* .data section which is used for initialized data *\/\r\n\r\n    .data : AT (_sidata)\r\n    {\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sdata = . ;\r\n\r\n        *(.data)\r\n        *(.data.*)\r\n        *(.gnu.linkonce.d*)\r\n\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _edata = . ;\r\n    } >DATA\r\n\r\n    __bss_start = .;\r\n    .bss :\r\n    {\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _sbss = .;\r\n\r\n        *(.bss)\r\n        *(COMMON)\r\n\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _ebss = . ;\r\n        _estack = .;\r\n        \r\n        *(.bss.init)\r\n    } > DATA\r\n    __bss_end = .;\r\n\r\n    _end = .;\r\n\r\n    \/* Stabs debugging sections.  *\/\r\n    .stab          0 : { *(.stab) }\r\n    .stabstr       0 : { *(.stabstr) }\r\n    .stab.excl     0 : { *(.stab.excl) }\r\n    .stab.exclstr  0 : { *(.stab.exclstr) }\r\n    .stab.index    0 : { *(.stab.index) }\r\n    .stab.indexstr 0 : { *(.stab.indexstr) }\r\n    .comment       0 : { *(.comment) }\r\n    \/* DWARF debug sections.\r\n     * Symbols in the DWARF debugging sections are relative to the beginning\r\n     * of the section so we begin them at 0.  *\/\r\n    \/* DWARF 1 *\/\r\n    .debug          0 : { *(.debug) }\r\n    .line           0 : { *(.line) }\r\n    \/* GNU DWARF 1 extensions *\/\r\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n    .debug_sfnames  0 : { *(.debug_sfnames) }\r\n    \/* DWARF 1.1 and DWARF 2 *\/\r\n    .debug_aranges  0 : { *(.debug_aranges) }\r\n    .debug_pubnames 0 : { *(.debug_pubnames) }\r\n    \/* DWARF 2 *\/\r\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n    .debug_abbrev   0 : { *(.debug_abbrev) }\r\n    .debug_line     0 : { *(.debug_line) }\r\n    .debug_frame    0 : { *(.debug_frame) }\r\n    .debug_str      0 : { *(.debug_str) }\r\n    .debug_loc      0 : { *(.debug_loc) }\r\n    .debug_macinfo  0 : { *(.debug_macinfo) }\r\n    \/* SGI\/MIPS DWARF 2 extensions *\/\r\n    .debug_weaknames 0 : { *(.debug_weaknames) }\r\n    .debug_funcnames 0 : { *(.debug_funcnames) }\r\n    .debug_typenames 0 : { *(.debug_typenames) }\r\n    .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6867cd5d86ec7705a8522af4173e6bdf6980dd88","subject":"Correct linker additions","message":"Correct linker additions\n","repos":"the-nw1-group\/acb-modules","old_file":"acb-common\/ldscripts\/m0\/f32r6-acb-module-mem.ld","new_file":"acb-common\/ldscripts\/m0\/f32r6-acb-module-mem.ld","new_contents":"\/*\n * Memory Spaces Definitions.\n *\n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\n * The values below can be addressed in further linker scripts\n * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\n *\/\n\n\/*\n * Location of CBUS module parameter block. This needs to be within the main application code, and after the\n * vector table. non-M0 devices vector tables contain upto 81 entries (324 bytes), plus an additional 16 entries (64\n * bytes) for the exception and core peripherial devices,  and usually have 4K pages (unlike the low density M0 devices\n * that have 1K pages). So the location of the CBUS parameter block needs to be at least 4488 bytes from the nominal\n * application origin (0x08000000). The parameter block is therefore placed at location 0x1188 (4488) after the\n * application origin, so that it's in a common location across all cortex devices.\n *\n * This does mean that this creates a gap in the application image on m0 devices (as they only have a 32 entry vector \n * table, or 128 bytes, with the same set of exception handlers as the other cortex devices, making 192 bytes), in\n * addition to the flash image starting at 3K, rather than 4K. This leaves a gap of 1224 bytes. Therefore we allocate\n * a \"vtor\" flash area, where some routines can be placed. These need to be defined in code, to be placed in the\n * after_vectors section, as the linker won't flow sections around the fixed CBUS module parameters block.\n *\n * Note the offset here, is from the _flash_origin as defined above.\n *\/\n\n\nMEMORY\n{\n  RAM (xrw)         : ORIGIN = 0x200000C0, LENGTH = 5952\n  FLASH_VTOR(rx)    : ORIGIN = 0x08000C00, LENGTH = 4488\n  CBUS_MOD_VARS(rx) : ORIGIN = 0x08001188, LENGTH = 40\n  FLASH (rx)        : ORIGIN = 0x080011B0, LENGTH = 28240\n}\n\n_ram_origin   = ORIGIN(RAM);\n_ram_length   = LENGTH(RAM);\n_ram_lastLocation = _ram_origin + _ram_length;\n\n_flash_origin = ORIGIN(FLASH_VTOR);\n_flash_length = LENGTH(FLASH) + LENGTH(CBUS_MOD_VARS) + LENGTH(FLASH);\n","old_contents":"\/*\n * Memory Spaces Definitions.\n *\n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\n * The values below can be addressed in further linker scripts\n * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\n *\/\n\n\/*\n * Location of CBUS module parameter block. This needs to be within the main application code, and after the\n * vector table. non-M0 devices vector tables contain upto 81 entries (324 bytes), plus an additional 16 entries (64\n * bytes) for the exception and core peripherial devices,  and usually have 4K pages (unlike the low density M0 devices\n * that have 1K pages). So the location of the CBUS parameter block needs to be at least 4488 bytes from the nominal\n * application origin (0x08000000). The parameter block is therefore placed at location 0x1188 (4488) after the\n * application origin, so that it's in a common location across all cortex devices.\n *\n * This does mean that this creates a gap in the application image on m0 devices (as they only have a 32 entry vector \n * table, or 128 bytes, with the same set of exception handlers as the other cortex devices, making 192 bytes), in\n * addition to the flash image starting at 3K, rather than 4K. This leaves a gap of 1224 bytes. Therefore we allocate\n * a \"vtor\" flash area, where some routines can be placed. These need to be defined in code, to be placed in the\n * after_vectors section, as the linker won't flow sections around the fixed CBUS module parameters block.\n *\n * Note the offset here, is from the _flash_origin as defined above.\n *\/\n\n\nMEMORY\n{\n  RAM (xrw)         : ORIGIN = 0x200000C0, LENGTH = 5952\n  FLASH_VTOR(rx)    : ORIGIN = 0x08000C00, LENGTH = 4488\n  CBUS_MOD_VARS(rx) : ORIGIN = 0x08001188, LENGTH = 40\n  FLASH (rx)        : ORIGIN = 0x080011B0, LENGTH = 28240\n}\n\n_ram_origin   = ORIGIN(RAM);\n_ram_length   = LENGTH(RAM);\n_ram_lastLocation = _ram_origin + _ram_length;\n\n_flash_origin = ORIGIN(FLASH);\n_flash_length = LENGTH(FLASH);\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"f053f4b31ac4efd2ed53994388b785b17b79fac7","subject":"fix the size in lds","message":"fix the size in lds\n\n48KB is 0xc000, not 0x30000.\n\nSigned-off-by: Haojian Zhuang <979139d45d262f0480136b0da512e0afa0fe79d3@gmail.com>\n","repos":"96boards-hikey\/l-loader,96boards-hikey\/l-loader","old_file":"l-loader.lds","new_file":"l-loader.lds","new_contents":"\/*\n * Copyright (c) 2014 Linaro Ltd.\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS\n{\n\t. = 0xf9800800;\n\tLLOADER_START = .;\n\n\t.text :\n\t{\n\t\t*(.text)\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN(4):\n\t{\n\t\t*(.data)\n\t}\n\n\t. = ALIGN(4);\n\n\t.bss ALIGN(4):\n\t{\n\t\t*(.bss)\n\t}\n\n\tLLOADER_BL1_BIN = 0xf9802000;\n\n\t\/* bl1.bin (48KB - 8KB) *\/\n\n\tLLOADER_END = 0xf980c000;\n}\n","old_contents":"\/*\n * Copyright (c) 2014 Linaro Ltd.\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS\n{\n\t. = 0xf9800800;\n\tLLOADER_START = .;\n\n\t.text :\n\t{\n\t\t*(.text)\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN(4):\n\t{\n\t\t*(.data)\n\t}\n\n\t. = ALIGN(4);\n\n\t.bss ALIGN(4):\n\t{\n\t\t*(.bss)\n\t}\n\n\tLLOADER_BL1_BIN = 0xf9802000;\n\n\t\/* bl1.bin (48KB - 8KB) *\/\n\n\tLLOADER_END = 0xf9830000;\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"9db8d359b6b5ed51028d96e3aecba56368946f55","subject":"Remove unused linker script","message":"Remove unused linker script\n","repos":"shockkolate\/shockk-os,shockkolate\/shockk-os,shockkolate\/shockk-os","old_file":"link.ld","new_file":"link.ld","new_contents":"","old_contents":"ENTRY(entry)\nSECTIONS\n{\n\t.text BLOCK(512) : ALIGN(512)\n\t{\n\t\t*(.text)\n\t}\n\n\t.rodata BLOCK(512) : ALIGN(512)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t.data BLOCK(512) : ALIGN(512)\n\t{\n\t\t*(.data)\n\t}\n\n\t.bss BLOCK(512) : ALIGN(512)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"97e0aca27d2fd7f781502de97441571d0d56a1b9","subject":"TODOs and comments in linker script","message":"TODOs and comments in linker script\n","repos":"olsner\/os,olsner\/os,olsner\/os,olsner\/os","old_file":"cuser\/linker.ld","new_file":"cuser\/linker.ld","new_contents":"ENTRY(start)\nOUTPUT_FORMAT(binary)\n\nSECTIONS\n{\n\t. = 1M;\n\n\t.text : {\n\t\t*(.start);\n\t\t*(.text*);\n\t\t*(.rodata*);\n\t}\n\t\/* TODO bss: page aligned. (It doesn't get allocated by anything - but\n\t * it's still useful to let linker handle layout of things that the program\n\t * can allocate (e.g. zeropage). *\/\n\t\/* TODO data: We don't make data writeable so we don't really support it. *\/\n\t\/* FWIW, it should be possible to add a small loader shim that maps all\n\t * .bss pages, copies RW-data pages, and calls the actual entry point. *\/\n\t\/DISCARD\/ : {\n\t\t*(.eh_frame);\n\t\t*(.comment);\n\t\t*(.note*);\n\t}\n}\n","old_contents":"ENTRY(start)\nOUTPUT_FORMAT(binary)\n\nSECTIONS\n{\n\t. = 1M;\n\n\t.text : {\n\t\t*(.start);\n\t\t*(.text*);\n\t}\n\t.rodata : {\n\t\t*(.rodata*);\n\t}\n\t\/DISCARD\/ : {\n\t\t*(.eh_frame);\n\t\t*(.comment);\n\t\t*(.note*);\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"877d52431f4d3cda4adea077ffbe88f3fd1755d3","subject":"m68k: Fix --build-id breakage for sun3","message":"m68k: Fix --build-id breakage for sun3\n\nCounterpart of commit 08a3db94f2a36c28278922732bc281c1722ceb18 (\"m68k: Add\nNOTES to init data so its discarded at boot\") for sun3 build.\n\nSigned-off-by: Al Viro <de609eb4d5d70b1d38ec6642adbfc33a2781f63c@zeniv.linux.org.uk>\nSigned-off-by: Geert Uytterhoeven <0da414d9d963da4039c2a0525b1844228075aa58@linux-m68k.org>\n","repos":"TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas","old_file":"arch\/m68k\/kernel\/vmlinux-sun3.lds","new_file":"arch\/m68k\/kernel\/vmlinux-sun3.lds","new_contents":"\/* ld script to make m68k Linux kernel *\/\n\n#include <asm-generic\/vmlinux.lds.h>\n#include <asm\/page.h>\n\nOUTPUT_FORMAT(\"elf32-m68k\", \"elf32-m68k\", \"elf32-m68k\")\nOUTPUT_ARCH(m68k)\nENTRY(_start)\njiffies = jiffies_64 + 4;\nSECTIONS\n{\n  . = 0xE002000;\n  _text = .;\t\t\t\/* Text and read-only data *\/\n  .text : {\n\t*(.text.head)\n\tTEXT_TEXT\n\tSCHED_TEXT\n\tLOCK_TEXT\n\t*(.fixup)\n\t*(.gnu.warning)\n\t} :text = 0x4e75\n\tRODATA\n\n  _etext = .;\t\t\t\/* End of text section *\/\n\n  .data : {\t\t\t\/* Data *\/\n\tDATA_DATA\n\tCONSTRUCTORS\n\t. = ALIGN(16);\t\t\/* Exception table *\/\n\t__start___ex_table = .;\n\t*(__ex_table)\n\t__stop___ex_table = .;\n\t} :data\n  \/* End of data goes *here* so that freeing init code works properly. *\/\n  _edata = .;\n  NOTES\n\n  \/* will be freed after init *\/\n  . = ALIGN(PAGE_SIZE);\t\/* Init code and data *\/\n__init_begin = .;\n\t.init.text : {\n\t\t_sinittext = .;\n\t\tINIT_TEXT\n\t\t_einittext = .;\n\t}\n\t.init.data : { INIT_DATA }\n\t. = ALIGN(16);\n\t__setup_start = .;\n\t.init.setup : { *(.init.setup) }\n\t__setup_end = .;\n\t__initcall_start = .;\n\t.initcall.init : {\n\t\tINITCALLS\n\t}\n\t__initcall_end = .;\n\t__con_initcall_start = .;\n\t.con_initcall.init : { *(.con_initcall.init) }\n\t__con_initcall_end = .;\n\t.m68k_fixup : {\n\t\t__start_fixup = .;\n\t\t*(.m68k_fixup)\n\t\t__stop_fixup = .;\n\t}\n\tSECURITY_INIT\n#ifdef CONFIG_BLK_DEV_INITRD\n\t. = ALIGN(PAGE_SIZE);\n\t__initramfs_start = .;\n\t.init.ramfs : { *(.init.ramfs) }\n\t__initramfs_end = .;\n#endif\n\t. = ALIGN(PAGE_SIZE);\n\t__init_end = .;\n\t.data.init.task : { *(.data.init_task) }\n\n\n  .bss : { *(.bss) }\t\t\/* BSS *\/\n\n  _end = . ;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ : {\n\tEXIT_TEXT\n\tEXIT_DATA\n\t*(.exitcall.exit)\n\t}\n\n  .crap : {\n\t\/* Stabs debugging sections.  *\/\n\t*(.stab)\n\t*(.stabstr)\n\t*(.stab.excl)\n\t*(.stab.exclstr)\n\t*(.stab.index)\n\t*(.stab.indexstr)\n\t*(.comment)\n\t*(.note)\n  }\n\n}\n","old_contents":"\/* ld script to make m68k Linux kernel *\/\n\n#include <asm-generic\/vmlinux.lds.h>\n#include <asm\/page.h>\n\nOUTPUT_FORMAT(\"elf32-m68k\", \"elf32-m68k\", \"elf32-m68k\")\nOUTPUT_ARCH(m68k)\nENTRY(_start)\njiffies = jiffies_64 + 4;\nSECTIONS\n{\n  . = 0xE002000;\n  _text = .;\t\t\t\/* Text and read-only data *\/\n  .text : {\n\t*(.text.head)\n\tTEXT_TEXT\n\tSCHED_TEXT\n\tLOCK_TEXT\n\t*(.fixup)\n\t*(.gnu.warning)\n\t} :text = 0x4e75\n\tRODATA\n\n  _etext = .;\t\t\t\/* End of text section *\/\n\n  .data : {\t\t\t\/* Data *\/\n\tDATA_DATA\n\tCONSTRUCTORS\n\t. = ALIGN(16);\t\t\/* Exception table *\/\n\t__start___ex_table = .;\n\t*(__ex_table)\n\t__stop___ex_table = .;\n\t} :data\n  \/* End of data goes *here* so that freeing init code works properly. *\/\n  _edata = .;\n\n  \/* will be freed after init *\/\n  . = ALIGN(PAGE_SIZE);\t\/* Init code and data *\/\n__init_begin = .;\n\t.init.text : {\n\t\t_sinittext = .;\n\t\tINIT_TEXT\n\t\t_einittext = .;\n\t}\n\t.init.data : { INIT_DATA }\n\t. = ALIGN(16);\n\t__setup_start = .;\n\t.init.setup : { *(.init.setup) }\n\t__setup_end = .;\n\t__initcall_start = .;\n\t.initcall.init : {\n\t\tINITCALLS\n\t}\n\t__initcall_end = .;\n\t__con_initcall_start = .;\n\t.con_initcall.init : { *(.con_initcall.init) }\n\t__con_initcall_end = .;\n\t.m68k_fixup : {\n\t\t__start_fixup = .;\n\t\t*(.m68k_fixup)\n\t\t__stop_fixup = .;\n\t}\n\tSECURITY_INIT\n#ifdef CONFIG_BLK_DEV_INITRD\n\t. = ALIGN(PAGE_SIZE);\n\t__initramfs_start = .;\n\t.init.ramfs : { *(.init.ramfs) }\n\t__initramfs_end = .;\n#endif\n\t. = ALIGN(PAGE_SIZE);\n\t__init_end = .;\n\t.data.init.task : { *(.data.init_task) }\n\n\n  .bss : { *(.bss) }\t\t\/* BSS *\/\n\n  _end = . ;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ : {\n\tEXIT_TEXT\n\tEXIT_DATA\n\t*(.exitcall.exit)\n\t}\n\n  .crap : {\n\t\/* Stabs debugging sections.  *\/\n\t*(.stab)\n\t*(.stabstr)\n\t*(.stab.excl)\n\t*(.stab.exclstr)\n\t*(.stab.index)\n\t*(.stab.indexstr)\n\t*(.comment)\n\t*(.note)\n  }\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f2e4edf51ae5ce0a7e3f10082391c0291e75df81","subject":"x86: set up linker ROM region for MMU","message":"x86: set up linker ROM region for MMU\n\nFor virtual kernels this represents where the kernel\nis loaded in physical memory.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/x86\/memory.ld","new_file":"include\/arch\/x86\/memory.ld","new_contents":"\/*\n * Copyright (c) 2011-2014, Wind River Systems, Inc.\n * Copyright (c) 2019-2020 Intel Corp.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file Directives for linker MEMORY regions for all x86\n *\n * By default, the kernel is linked at its physical address and all addresses\n * are in RAM.\n *\n * If CONFIG_KERNEL_LINK_IN_VIRT is enabled, the kernel is linked at\n * the virtual address space defined by CONFIG_KERNEL_VM_BASE,\n * and CONFIG_KERNEL_VM_SIZE. CONFIG_KERNEL_VM_OFFSET defines the offset of\n * the start of virtual address space to place the kernel. This allows\n * the kernel to have a bigger address space.\n *\n * If CONFIG_XIP is enabled, then another MEMORY region is declared for ROM,\n * and this is where the Zephyr image is booted from. The linker LMAs and VMAs\n * are set up, such that read\/write data\/bss have their VMA addresses\n * in RAM and are copied from flash at boot. Text\/rodata linked in-place in\n * flash.\n *\n * If CONFIG_MMU is enabled, then the ROM region in MEMORY is used to set the\n * LMA for all sections relative to physical address. The virtual address VMAs\n * for all sections are relative to the base virtual address for the kernel.\n * Setting LMAs here helps let QEMU or any other ELF-aware loader know where to\n * physically load the image.\n *\/\n\n#ifndef ARCH_X86_MEMORY_LD\n#define ARCH_X86_MEMORY_LD\n\n#include <autoconf.h>\n#include <devicetree.h>\n#include <sys\/mem_manage.h>\n\n\/* Bounds of physical RAM from DTS *\/\n#define PHYS_RAM_ADDR\t\tDT_REG_ADDR(DT_CHOSEN(zephyr_sram))\n#define PHYS_RAM_SIZE\t\tDT_REG_SIZE(DT_CHOSEN(zephyr_sram))\n\n\/* Virtual base address for the kernel; with CONFIG_MMU this is not necessarily\n * the same as its physical location, although an identity mapping for RAM\n * is still supported by setting CONFIG_KERNEL_VM_BASE=CONFIG_SRAM_BASE_ADDRESS.\n *\/\n#ifdef Z_VM_KERNEL\n#define KERNEL_BASE_ADDR  (CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET)\n#define KERNEL_RAM_SIZE   (CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET)\n#define PHYS_RAM_AVAIL    (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n#else\n#define KERNEL_BASE_ADDR  (PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n#define KERNEL_RAM_SIZE   (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n#endif\n\n\/* \"kernel RAM\" for linker VMA allocations starts at the offset *\/\n\n#ifdef CONFIG_XIP\n  \/* \"ROM\" is flash, we leave rodata and text there and just copy in data.\n   * Board-level DTS must specify a flash region that doesn't overlap with\n   * sram0, so that DT_PHYS_LOAD_ADDR is set.\n   *\/\n  #define FLASH_ROM_SIZE      DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n  #define PHYS_LOAD_ADDR      DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#else\n  \/* Physical RAM location where the kernel image is loaded *\/\n  #define PHYS_LOAD_ADDR      (PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n#endif \/* CONFIG_XIP *\/\n\n#ifdef CONFIG_X86_64\n\/* Locore must be addressable by real mode and so cannot extend past 64K.\n * Skip reserved stuff in the first page\n *\/\n#define LOCORE_BASE         0x1000\n#define LOCORE_SIZE         (0x10000 - LOCORE_BASE)\n\n#if PHYS_RAM_ADDR != CONFIG_KERNEL_VM_BASE\n#error Virtual kernel linking is not yet implemented for 64-bit\n#endif\n#endif \/* CONFIG_X86_64 *\/\n\nMEMORY\n    {\n#if defined(CONFIG_XIP)\n    \/* Address range where the kernel will be installed on a flash part (XIP),\n     * or copied into physical RAM by a loader (MMU)\n     *\/\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = FLASH_ROM_SIZE\n#elif defined(Z_VM_KERNEL)\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_AVAIL\n#endif\n    \/* Linear address range to link the kernel. If non-XIP, everything is\n     * linked in this space. Otherwise, rodata and text are linked at their\n     * physical ROM locations\n     *\/\n    RAM (wx)        : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE\n\n#ifdef CONFIG_X86_64\n    \/* Special low-memory area for bootstrapping other CPUs from real mode *\/\n    LOCORE (wx)     : ORIGIN = LOCORE_BASE, LENGTH = LOCORE_SIZE\n#else\n    \/*\n     * On 32-bit x86, fake memory area for build-time IDT generation data.\n     * 64-bit doesn't use this, interrupts are all manaaged at runtime.\n     *\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 0xFFFF1000, LENGTH = 2K\n#endif \/* !CONFIG_X86_64 *\/\n    }\n#endif \/* ARCH_X86_MEMORY_LD *\/\n","old_contents":"\/*\n * Copyright (c) 2011-2014, Wind River Systems, Inc.\n * Copyright (c) 2019-2020 Intel Corp.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file Directives for linker MEMORY regions for all x86\n *\n * By default, the kernel is linked at its physical address and all addresses\n * are in RAM.\n *\n * If CONFIG_KERNEL_LINK_IN_VIRT is enabled, the kernel is linked at\n * the virtual address space defined by CONFIG_KERNEL_VM_BASE,\n * and CONFIG_KERNEL_VM_SIZE. CONFIG_KERNEL_VM_OFFSET defines the offset of\n * the start of virtual address space to place the kernel. This allows\n * the kernel to have a bigger address space.\n *\n * If CONFIG_XIP is enabled, then another MEMORY region is declared for ROM,\n * and this is where the Zephyr image is booted from. The linker LMAs and VMAs\n * are set up, such that read\/write data\/bss have their VMA addresses\n * in RAM and are copied from flash at boot. Text\/rodata linked in-place in\n * flash.\n *\/\n\n#ifndef ARCH_X86_MEMORY_LD\n#define ARCH_X86_MEMORY_LD\n\n#include <autoconf.h>\n#include <devicetree.h>\n\n\/* Bounds of physical RAM from DTS *\/\n#define PHYS_RAM_ADDR\t\tDT_REG_ADDR(DT_CHOSEN(zephyr_sram))\n#define PHYS_RAM_SIZE\t\tDT_REG_SIZE(DT_CHOSEN(zephyr_sram))\n\n#ifdef CONFIG_KERNEL_LINK_IN_VIRT\n\n\/* Linked at virtual address space *\/\n#define KERNEL_BASE_ADDR\t\\\n\t(CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET)\n#define KERNEL_RAM_SIZE\t\t\\\n\t(CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET)\n\n#else\n\n\/* Linked at physical address *\/\n#define KERNEL_BASE_ADDR\t\\\n\t(PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n#define KERNEL_RAM_SIZE\t\t\\\n\t(PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n\n#endif \/* CONFIG_DEMAND_PAGING *\/\n\n#ifdef CONFIG_XIP\n  \/* \"ROM\" is flash, we leave rodata and text there and just copy in data.\n   * Board-level DTS must specify a flash region that doesn't overlap with\n   * sram0, so that DT_PHYS_LOAD_ADDR is set.\n   *\/\n  #define FLASH_ROM_SIZE      DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n  #define PHYS_LOAD_ADDR      DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif\n\n#ifdef CONFIG_X86_64\n\/* Locore must be addressable by real mode and so cannot extend past 64K.\n * Skip reserved stuff in the first page\n *\/\n#define LOCORE_BASE         0x1000\n#define LOCORE_SIZE         (0x10000 - LOCORE_BASE)\n#endif\n\nMEMORY\n    {\n#if defined(CONFIG_XIP)\n    \/* Address range where the kernel will be installed on a flash part (XIP),\n     * or copied into physical RAM by a loader (MMU)\n     *\/\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = FLASH_ROM_SIZE\n#endif\n    \/* Linear address range to link the kernel. If non-XIP, everything is\n     * linked in this space. Otherwise, rodata and text are linked at their\n     * physical ROM locations\n     *\/\n    RAM (wx)        : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE\n\n#ifdef CONFIG_X86_64\n    \/* Special low-memory area for bootstrapping other CPUs from real mode *\/\n    LOCORE (wx)     : ORIGIN = LOCORE_BASE, LENGTH = LOCORE_SIZE\n#else\n    \/*\n     * On 32-bit x86, fake memory area for build-time IDT generation data.\n     * 64-bit doesn't use this, interrupts are all manaaged at runtime.\n     *\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 0xFFFF1000, LENGTH = 2K\n#endif \/* !CONFIG_X86_64 *\/\n    }\n#endif \/* ARCH_X86_MEMORY_LD *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"aeda220dcbfdb703004cb8afb40557b13bdcaa4c","subject":"solo5: linker.ld moved elf symbols before bss, and added padding","message":"solo5: linker.ld moved elf symbols before bss, and added padding\n","repos":"ingve\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,ingve\/IncludeOS,hioa-cs\/IncludeOS,ingve\/IncludeOS,AndreasAakesson\/IncludeOS,AndreasAakesson\/IncludeOS,mnordsletten\/IncludeOS,ingve\/IncludeOS,hioa-cs\/IncludeOS,alfred-bratterud\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,hioa-cs\/IncludeOS,alfred-bratterud\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,AndreasAakesson\/IncludeOS,alfred-bratterud\/IncludeOS,hioa-cs\/IncludeOS,ingve\/IncludeOS,AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS","old_file":"src\/linker.ld","new_file":"src\/linker.ld","new_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0xA00000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  .multiboot (_ELF_START_ + SIZEOF_HEADERS): {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n  PROVIDE( _TEXT_START_ = . );\n  .text (_TEXT_START_ ) :\n  {\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x10) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array     :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/*\n   * XXX: We need this padding because in solo5 initialization some variables\n   * in the bss are set to non-zero values. So, without the padding the ELFs\n   * symbol table would get modified.\n   *\/\n  . += 0x1000000;\n\n  .bss :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n    . = ALIGN(64 \/ 8);\n  }\n  . = ALIGN(64 \/ 8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n\n}\n","old_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0xA00000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  .multiboot (_ELF_START_ + SIZEOF_HEADERS): {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n  PROVIDE( _TEXT_START_ = . );\n  .text (_TEXT_START_ ) :\n  {\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x10) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array     :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .bss :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n    . = ALIGN(64 \/ 8);\n  }\n  . = ALIGN(64 \/ 8);\n\n  \/*\n   * This has to be moved after the bss because in solo5 initialization some\n   * variables in the bss are set to non-zero values. So, what happens is that\n   * the ELFs symbol table would get modified if it stays at the beginning of\n   * the bss.\n   *\/\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n  . = ALIGN(64 \/ 8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9a6c9449eb20a44da8ffcdef68dc66c704d02372","subject":"fix orex","message":"fix orex\n","repos":"ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme","old_file":"orex.ld","new_file":"orex.ld","new_contents":"ENTRY (main)\n\nMEMORY\n{\n  ram : ORIGIN = 0x00100000, LENGTH = 31M\n  rom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n  .data : \/* Initialized data. *\/\n  {\n    _DataStart = . ;\n    *(.data)\n    *(.data.rel.local)\n    _DataEnd = . ;\n  } >ram\n\n  .bss : \/* Uninitialized data. *\/\n  {\n    _BssStart = . ;\n    *(.bss)\n    *(.sbss)\n    _BssEnd = . ;\n  } >ram\n\n  .text : \/* The actual instructions. *\/\n  {\n    *(.text)\n    *(.got)\n    *(.got.plt)\n    *(.rodata)\n    *(.rodata.str1.4)\n    *(.glue_7)\n    *(.glue_7t)\n  } >ram\n}\n","old_contents":"ENTRY (main)\n\nMEMORY\n{\n  ram : ORIGIN = 0x00200000, LENGTH = 30M\n  rom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n  .data : \/* Initialized data. *\/\n  {\n    _DataStart = . ;\n    *(.data)\n    *(.data.rel.local)\n    _DataEnd = . ;\n  } >ram\n\n  .bss : \/* Uninitialized data. *\/\n  {\n    _BssStart = . ;\n    *(.bss)\n    *(.sbss)\n    _BssEnd = . ;\n  } >ram\n\n  .text : \/* The actual instructions. *\/\n  {\n    *(.text)\n    *(.got)\n    *(.got.plt)\n    *(.rodata)\n    *(.rodata.str1.4)\n    *(.glue_7)\n    *(.glue_7t)\n  } >ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"71561839856811687f9e9e5e692c83c5efe465f2","subject":"arm: fix the VTOR alignment requirement for Baseline Cortex-M","message":"arm: fix the VTOR alignment requirement for Baseline Cortex-M\n\nBaseline Cortex-M requires VTOR to be aligned on 64-word\nboundary. That is because bit-7 of VTOR is also RAZ\/WI.\nThe commit updates the vector table section alignment for\nBaseline Cortex-M to reflect the implementation constraint.\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"arch\/arm\/core\/aarch32\/vector_table.ld","new_file":"arch\/arm\/core\/aarch32\/vector_table.ld","new_contents":"\/*\n * Copyright (c) 2019 - 2020 Nordic Semiconductor ASA\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR)\n\/*\n * In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the\n * exc_vector_table (i.e. _vector_start) during initialization. Therefore,\n * exc_vector_table must respect the alignment requirements of VTOR.TBLOFF\n * described below.\n *\/\n\n#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)\n\/* VTOR bits 0:7 are reserved (RES0). This requires that the base address\n * of the vector table is 64-word aligned.\n *\/\n. = ALIGN( 1 << LOG2CEIL(4 * 64) );\n#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)\n\/* VTOR bits 0:6 are reserved (RES0). This requires that the base address\n * of the vector table is 32-word aligned.\n *\/\n. = ALIGN( 1 << LOG2CEIL(4 * 32) );\n#else\n#error \"Unsupported architecture variant\"\n#endif\n\n\/* When setting TBLOFF in VTOR we must align the offset to the number of\n * exception entries in the vector table. The minimum alignment of 32 words\n * is sufficient for the 16 ARM Core exceptions and up to 16 HW interrupts.\n * For more than 16 HW interrupts, we adjust the alignment by rounding up\n * to the next power of two; this restriction guarantees a functional VTOR\n * setting in any Cortex-M implementation (might not be required in every\n * Cortex-M processor).\n *\/\n. = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );\n#endif\n\n_vector_start = .;\nKEEP(*(.exc_vector_table))\nKEEP(*(\".exc_vector_table.*\"))\n\nKEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\nKEEP(*(.vectors))\n\n_vector_end = .;\n\n#include \"cortex_m\/vector_table_pad.ld\"\n","old_contents":"\/*\n * Copyright (c) 2019 - 2020 Nordic Semiconductor ASA\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR)\n\/*\n * In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the\n * exc_vector_table (i.e. _vector_start) during initialization. Therefore,\n * exc_vector_table must respect the alignment requirements of VTOR.TBLOFF\n * described below.\n *\/\n\n\/* VTOR bits 0:6 are reserved (RES0). This requires that the base address\n * of the vector table is 32-word aligned.\n *\/\n. = ALIGN( 1 << LOG2CEIL(4 * 32) );\n\n\/* When setting TBLOFF in VTOR we must align the offset to the number of\n * exception entries in the vector table. The minimum alignment of 32 words\n * is sufficient for the 16 ARM Core exceptions and up to 16 HW interrupts.\n * For more than 16 HW interrupts, we adjust the alignment by rounding up\n * to the next power of two; this restriction guarantees a functional VTOR\n * setting in any Cortex-M implementation (might not be required in every\n * Cortex-M processor).\n *\/\n. = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );\n#endif\n\n_vector_start = .;\nKEEP(*(.exc_vector_table))\nKEEP(*(\".exc_vector_table.*\"))\n\nKEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\nKEEP(*(.vectors))\n\n_vector_end = .;\n\n#include \"cortex_m\/vector_table_pad.ld\"\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3070526af87790cba503cb7290e2279fc5aa02cd","subject":"updated to lscript from xsdk","message":"updated to lscript from xsdk\n","repos":"schrluka\/cfg_mgmt,schrluka\/cfg_mgmt,schrluka\/cfg_mgmt,schrluka\/cfg_mgmt","old_file":"bm_fw\/lscript.ld","new_file":"bm_fw\/lscript.ld","new_contents":"\/*******************************************************************\/\n\/*                                                                 *\/\n\/* This file is automatically generated by linker script generator.*\/\n\/*                                                                 *\/\n\/* Version:                                 *\/\n\/*                                                                 *\/\n\/* Copyright (c) 2010 Xilinx, Inc.  All rights reserved.           *\/\n\/*                                                                 *\/\n\/* Description : Cortex-A9 Linker Script                          *\/\n\/*                                                                 *\/\n\/*******************************************************************\/\n\/* modified: Lukas Schrittwieser *\/\n\n_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;\n_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;\n\n_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;\n_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;\n_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;\n_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;\n_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;\n\n\/* Define Memories in the system *\/\n\nMEMORY\n{\n   ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x20000000, LENGTH = 128M\n\/*   ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000\n   ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00 *\/\n}\n\n\/* Specify the default entry point to the program *\/\n\nENTRY(_vector_table)\n\n\/* Define the sections, and where they are mapped in memory *\/\n\nSECTIONS\n{\n.text : {\n   KEEP (*(.vectors))\n   *(.boot)\n   *(.text)\n   *(.text.*)\n   *(.gnu.linkonce.t.*)\n   *(.plt)\n   *(.gnu_warning)\n   *(.gcc_execpt_table)\n   *(.glue_7)\n   *(.glue_7t)\n   *(.vfp11_veneer)\n   *(.ARM.extab)\n   *(.gnu.linkonce.armextab.*)\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.init : {\n   KEEP (*(.init))\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.fini : {\n   KEEP (*(.fini))\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.rodata : {\n   __rodata_start = .;\n   *(.rodata)\n   *(.rodata.*)\n   *(.gnu.linkonce.r.*)\n   __rodata_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.rodata1 : {\n   __rodata1_start = .;\n   *(.rodata1)\n   *(.rodata1.*)\n   __rodata1_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.sdata2 : {\n   __sdata2_start = .;\n   *(.sdata2)\n   *(.sdata2.*)\n   *(.gnu.linkonce.s2.*)\n   __sdata2_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.sbss2 : {\n   __sbss2_start = .;\n   *(.sbss2)\n   *(.sbss2.*)\n   *(.gnu.linkonce.sb2.*)\n   __sbss2_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.data : {\n   __data_start = .;\n   *(.data)\n   *(.data.*)\n   *(.gnu.linkonce.d.*)\n   *(.jcr)\n   *(.got)\n   *(.got.plt)\n   __data_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.data1 : {\n   __data1_start = .;\n   *(.data1)\n   *(.data1.*)\n   __data1_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.got : {\n   *(.got)\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.ctors : {\n   __CTOR_LIST__ = .;\n   ___CTORS_LIST___ = .;\n   KEEP (*crtbegin.o(.ctors))\n   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))\n   KEEP (*(SORT(.ctors.*)))\n   KEEP (*(.ctors))\n   __CTOR_END__ = .;\n   ___CTORS_END___ = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.dtors : {\n   __DTOR_LIST__ = .;\n   ___DTORS_LIST___ = .;\n   KEEP (*crtbegin.o(.dtors))\n   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))\n   KEEP (*(SORT(.dtors.*)))\n   KEEP (*(.dtors))\n   __DTOR_END__ = .;\n   ___DTORS_END___ = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.fixup : {\n   __fixup_start = .;\n   *(.fixup)\n   __fixup_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.eh_frame : {\n   *(.eh_frame)\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.eh_framehdr : {\n   __eh_framehdr_start = .;\n   *(.eh_framehdr)\n   __eh_framehdr_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.gcc_except_table : {\n   *(.gcc_except_table)\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.mmu_tbl (ALIGN(16384)) : {\n   __mmu_tbl_start = .;\n   *(.mmu_tbl)\n   __mmu_tbl_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.ARM.exidx : {\n   __exidx_start = .;\n   *(.ARM.exidx*)\n   *(.gnu.linkonce.armexidix.*.*)\n   __exidx_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.preinit_array : {\n   __preinit_array_start = .;\n   KEEP (*(SORT(.preinit_array.*)))\n   KEEP (*(.preinit_array))\n   __preinit_array_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.init_array : {\n   __init_array_start = .;\n   KEEP (*(SORT(.init_array.*)))\n   KEEP (*(.init_array))\n   __init_array_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.fini_array : {\n   __fini_array_start = .;\n   KEEP (*(SORT(.fini_array.*)))\n   KEEP (*(.fini_array))\n   __fini_array_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.ARM.attributes : {\n   __ARM.attributes_start = .;\n   *(.ARM.attributes)\n   __ARM.attributes_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.sdata : {\n   __sdata_start = .;\n   *(.sdata)\n   *(.sdata.*)\n   *(.gnu.linkonce.s.*)\n   __sdata_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.sbss (NOLOAD) : {\n   __sbss_start = .;\n   *(.sbss)\n   *(.sbss.*)\n   *(.gnu.linkonce.sb.*)\n   __sbss_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.tdata : {\n   __tdata_start = .;\n   *(.tdata)\n   *(.tdata.*)\n   *(.gnu.linkonce.td.*)\n   __tdata_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.tbss : {\n   __tbss_start = .;\n   *(.tbss)\n   *(.tbss.*)\n   *(.gnu.linkonce.tb.*)\n   __tbss_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.bss (NOLOAD) : {\n   __bss_start = .;\n   *(.bss)\n   *(.bss.*)\n   *(.gnu.linkonce.b.*)\n   *(COMMON)\n   __bss_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) \/ 2 );\n\n_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) \/ 2 );\n\n\/* Generate Stack and Heap definitions *\/\n\n.heap (NOLOAD) : {\n   . = ALIGN(16);\n   _heap = .;\n   HeapBase = .;\n   _heap_start = .;\n   . += _HEAP_SIZE;\n   _heap_end = .;\n   HeapLimit = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.stack (NOLOAD) : {\n   . = ALIGN(16);\n   _stack_end = .;\n   . += _STACK_SIZE;\n   . = ALIGN(16);\n   _stack = .;\n   __stack = _stack;\n   . = ALIGN(16);\n   _irq_stack_end = .;\n   . += _IRQ_STACK_SIZE;\n   . = ALIGN(16);\n   __irq_stack = .;\n   _supervisor_stack_end = .;\n   . += _SUPERVISOR_STACK_SIZE;\n   . = ALIGN(16);\n   __supervisor_stack = .;\n   _abort_stack_end = .;\n   . += _ABORT_STACK_SIZE;\n   . = ALIGN(16);\n   __abort_stack = .;\n   _fiq_stack_end = .;\n   . += _FIQ_STACK_SIZE;\n   . = ALIGN(16);\n   __fiq_stack = .;\n   _undef_stack_end = .;\n   . += _UNDEF_STACK_SIZE;\n   . = ALIGN(16);\n   __undef_stack = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n_end = .;\n\n\n\/* remoteproc specific stuff *\/\n\/* WARNING: THIS IS CARGO CULT *\/\n\/* Trace buffer should be inside carverout *\/\n   __trace_buffer_start = .;\n   . = . + 0x8000; \/* It should be TRACE_BUFFER_SIZE *\/\n   __trace_buffer_end = .;\n   __elf_end = .; \/* This is size of carveout *\/\n\n\t\/* Linker script has to match Linux dma allocation\n\t * TX buffer has to start at align address but alignment\n\t * is done by dma_alloc_from_coherent and get_order and bitmap_find_free_region functions\n\t * Algorithm is easy 1 << (count position the most significant bit from ((__elf_end - 1) >> (PAGE_SHIFT -1))\n\t *\/\n   \/*. = ALIGN(0x400000);\n\n   __ring_tx_addr = .;\n   . = . + (256 * 16) + (2 *(3+256)); *\/ \/* vring size macro without vring_used_elements *\/\n\n   \/*. = ALIGN(0x1000);*\/ \/* Used buffer must be aligned *\/\n   \/*__ring_tx_addr_used = .;\n   . = . + 4 + (8 * 256); *\/ \/* vring_used structure *\/\n   \/*__ring_tx_addr_used_end = .;\n   . = ALIGN(0x2000);\n\n   __ring_rx_addr = .;\n  . = . + (256 * 16) + (2 *(3+256)); *\/ \/* vring size macro without vring_used_elements *\/\n  \/*. = ALIGN(0x1000);\n  __ring_rx_addr_used = .;*\/ \/* Used buffer must be aligned *\/\n  \/*. = . + 4 + (8 * 256);*\/ \/* vring_used structure *\/\n  \/*__ring_rx_addr_used_end = .;\n  . = ALIGN(0x2000);*\/\n\n}\n\n__elf_len = 0x4000000;","old_contents":"\/*******************************************************************\/\n\/*                                                                 *\/\n\/* This file is automatically generated by linker script generator.*\/\n\/*                                                                 *\/\n\/* Version:                                 *\/\n\/*                                                                 *\/\n\/* Copyright (c) 2010 Xilinx, Inc.  All rights reserved.           *\/\n\/*                                                                 *\/\n\/* Description : Cortex-A9 Linker Script                          *\/\n\/*                                                                 *\/\n\/*******************************************************************\/\n\/*                                                                 *\/\n\/* Modified by Lukas Schrittwieser, (c) 2015                       *\/\n\n\/* increased this from 0x2000 *\/\n_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000;\n\n\/* increased this from 0x2000 *\/\n_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x20000;\n\n_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;\n_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;\n_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;\n_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;\n\n\/* Define Memories in the system *\/\n\nMEMORY\n{\n   \/* highes 64MBytes of DDR memory (512MB total) are resereved for CPU1) *\/\n   ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x1c000000, LENGTH = 64M\n   ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000\n   ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00\n}\n\n\/* Specify the default entry point to the program *\/\n\nENTRY(_vector_table)\n\n\/* Define the sections, and where they are mapped in memory *\/\n\nSECTIONS\n{\n\/* _mem_start = .; *\/\n.text : {\n   *(.vectors)\n   *(.boot)\n   *(.text)\n   *(.text.*)\n   *(.gnu.linkonce.t.*)\n   *(.plt)\n   *(.gnu_warning)\n   *(.gcc_execpt_table)\n   *(.glue_7)\n   *(.glue_7t)\n   *(.vfp11_veneer)\n   *(.ARM.extab)\n   *(.gnu.linkonce.armextab.*)\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.init : {\n   KEEP (*(.init))\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.fini : {\n   KEEP (*(.fini))\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.rodata : {\n   __rodata_start = .;\n   *(.rodata)\n   *(.rodata.*)\n   *(.gnu.linkonce.r.*)\n   __rodata_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.rodata1 : {\n   __rodata1_start = .;\n   *(.rodata1)\n   *(.rodata1.*)\n   __rodata1_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.sdata2 : {\n   __sdata2_start = .;\n   *(.sdata2)\n   *(.sdata2.*)\n   *(.gnu.linkonce.s2.*)\n   __sdata2_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.sbss2 : {\n   __sbss2_start = .;\n   *(.sbss2)\n   *(.sbss2.*)\n   *(.gnu.linkonce.sb2.*)\n   __sbss2_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.data : {\n   __data_start = .;\n   *(.data)\n   *(.data.*)\n   *(.gnu.linkonce.d.*)\n   *(.jcr)\n   *(.got)\n   *(.got.plt)\n   __data_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.data1 : {\n   __data1_start = .;\n   *(.data1)\n   *(.data1.*)\n   __data1_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.got : {\n   *(.got)\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.ctors : {\n   __CTOR_LIST__ = .;\n   ___CTORS_LIST___ = .;\n   KEEP (*crtbegin.o(.ctors))\n   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))\n   KEEP (*(SORT(.ctors.*)))\n   KEEP (*(.ctors))\n   __CTOR_END__ = .;\n   ___CTORS_END___ = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.dtors : {\n   __DTOR_LIST__ = .;\n   ___DTORS_LIST___ = .;\n   KEEP (*crtbegin.o(.dtors))\n   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))\n   KEEP (*(SORT(.dtors.*)))\n   KEEP (*(.dtors))\n   __DTOR_END__ = .;\n   ___DTORS_END___ = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.fixup : {\n   __fixup_start = .;\n   *(.fixup)\n   __fixup_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.eh_frame : {\n   *(.eh_frame)\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.eh_framehdr : {\n   __eh_framehdr_start = .;\n   *(.eh_framehdr)\n   __eh_framehdr_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.gcc_except_table : {\n   *(.gcc_except_table)\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.mmu_tbl (ALIGN(16384)) : {\n   __mmu_tbl_start = .;\n   *(.mmu_tbl)\n   __mmu_tbl_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.ARM.exidx : {\n   __exidx_start = .;\n   *(.ARM.exidx*)\n   *(.gnu.linkonce.armexidix.*.*)\n   __exidx_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.preinit_array : {\n   __preinit_array_start = .;\n   KEEP (*(SORT(.preinit_array.*)))\n   KEEP (*(.preinit_array))\n   __preinit_array_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.init_array : {\n   __init_array_start = .;\n   KEEP (*(SORT(.init_array.*)))\n   KEEP (*(.init_array))\n   __init_array_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.fini_array : {\n   __fini_array_start = .;\n   KEEP (*(SORT(.fini_array.*)))\n   KEEP (*(.fini_array))\n   __fini_array_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.ARM.attributes : {\n   __ARM.attributes_start = .;\n   *(.ARM.attributes)\n   __ARM.attributes_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.sdata : {\n   __sdata_start = .;\n   *(.sdata)\n   *(.sdata.*)\n   *(.gnu.linkonce.s.*)\n   __sdata_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.sbss (NOLOAD) : {\n   __sbss_start = .;\n   *(.sbss)\n   *(.sbss.*)\n   *(.gnu.linkonce.sb.*)\n   __sbss_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.tdata : {\n   __tdata_start = .;\n   *(.tdata)\n   *(.tdata.*)\n   *(.gnu.linkonce.td.*)\n   __tdata_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.tbss : {\n   __tbss_start = .;\n   *(.tbss)\n   *(.tbss.*)\n   *(.gnu.linkonce.tb.*)\n   __tbss_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.bss (NOLOAD) : {\n   __bss_start = .;\n   *(.bss)\n   *(.bss.*)\n   *(.gnu.linkonce.b.*)\n   *(COMMON)\n   __bss_end = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) \/ 2 );\n\n_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) \/ 2 );\n\n\/* Generate Stack and Heap definitions *\/\n\n.heap (NOLOAD) : {\n   . = ALIGN(16);\n   _heap = .;\n   HeapBase = .;\n   _heap_start = .;\n   . += _HEAP_SIZE;\n   _heap_end = .;\n   HeapLimit = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n\n.stack (NOLOAD) : {\n   . = ALIGN(16);\n   _stack_end = .;\n   . += _STACK_SIZE;\n   _stack = .;\n   __stack = _stack;\n   . = ALIGN(16);\n   _irq_stack_end = .;\n   . += _STACK_SIZE;\n   __irq_stack = .;\n   _supervisor_stack_end = .;\n   . += _SUPERVISOR_STACK_SIZE;\n   . = ALIGN(16);\n   __supervisor_stack = .;\n   _abort_stack_end = .;\n   . += _ABORT_STACK_SIZE;\n   . = ALIGN(16);\n   __abort_stack = .;\n   _fiq_stack_end = .;\n   . += _FIQ_STACK_SIZE;\n   . = ALIGN(16);\n   __fiq_stack = .;\n   _undef_stack_end = .;\n   . += _UNDEF_STACK_SIZE;\n   . = ALIGN(16);\n   __undef_stack = .;\n} > ps7_ddr_0_S_AXI_BASEADDR\n_end = .;\n\n\n    \/* REMOTEPROC specific stuff *\/\n    \/* Trace buffer should be inside carverout *\/\n   __trace_buffer_start = .;\n   . = . + 0x8000; \/* It should be TRACE_BUFFER_SIZE *\/\n   __trace_buffer_end = .;\n   __elf_end = .; \/* This is size of carveout *\/\n\n\t\/* Linker script has to match Linux dma allocation\n\t * TX buffer has to start at align address but alignment\n\t * is done by dma_alloc_from_coherent and get_order and bitmap_find_free_region functions\n\t * Algorithm is easy 1 << (count position the most significant bit from ((__elf_end - 1) >> (PAGE_SHIFT -1))\n\t *\/\n   \/*. = ALIGN(0x400000);\n\n   __ring_tx_addr = .;\n   . = . + (256 * 16) + (2 *(3+256)); *\/ \/* vring size macro without vring_used_elements *\/\n\n   \/*. = ALIGN(0x1000);*\/ \/* Used buffer must be aligned *\/\n   \/*__ring_tx_addr_used = .;\n   . = . + 4 + (8 * 256); *\/ \/* vring_used structure *\/\n   \/*__ring_tx_addr_used_end = .;\n   . = ALIGN(0x2000);\n\n   __ring_rx_addr = .;\n  . = . + (256 * 16) + (2 *(3+256)); *\/ \/* vring size macro without vring_used_elements *\/\n  \/*. = ALIGN(0x1000);\n  __ring_rx_addr_used = .;*\/ \/* Used buffer must be aligned *\/\n  \/*. = . + 4 + (8 * 256);*\/ \/* vring_used structure *\/\n  \/*__ring_rx_addr_used_end = .;\n  . = ALIGN(0x2000);*\/\n\n\n\n\n\n}\n\n\n__elf_len = 0x4000000;\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"1cc029a1a38f1e026e4fc8d4c21ffeb43c1b2f08","subject":"[fix][bsp\/thead-smart\/gcc_csky.ld] Correct startup segment description error in link script","message":"[fix][bsp\/thead-smart\/gcc_csky.ld]\nCorrect startup segment description error in link script\n","repos":"geniusgogo\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread","old_file":"bsp\/thead-smart\/gcc_csky.ld","new_file":"bsp\/thead-smart\/gcc_csky.ld","new_contents":"\/*\n * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *   http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/******************************************************************************\n * @file     gcc_csky.h\n * @brief    csky linker file for PHOBOS\n * @version  V1.0\n * @date     02. June 2017\n ******************************************************************************\/\nMEMORY\n{\n    I-SRAM : ORIGIN = 0x0        , LENGTH = 0x40000   \/* I-SRAM  256KB *\/\n    D-SRAM : ORIGIN = 0x20000000 , LENGTH = 0xc0000   \/* D-SRAM  768KB *\/\n    O-SRAM : ORIGIN = 0x50000000 , LENGTH = 0x800000   \/* off-chip SRAM 8MB *\/\n    SRAM   : ORIGIN = 0x60000000 , LENGTH = 0x20000   \/* on-chip SRAM 128KB *\/\n}\n\nPROVIDE (__StackTop = 0x200c0000 - 0x8);\nPROVIDE (Stack_Size = 0x1000);\n\nREGION_ALIAS(\"REGION_TEXT\",    I-SRAM);\nREGION_ALIAS(\"REGION_RODATA\",  I-SRAM);\nREGION_ALIAS(\"REGION_CUSTOM1\", D-SRAM);\nREGION_ALIAS(\"REGION_CUSTOM2\", D-SRAM);\nREGION_ALIAS(\"REGION_DATA\",    D-SRAM);\nREGION_ALIAS(\"REGION_BSS\",     D-SRAM);\n\nENTRY(Reset_Handler)\nSECTIONS\n{\n  .text : AT(ADDR(.text)){\n  . = ALIGN(0x4) ;\n  __stext = . ;\n  KEEP(*startup_gcc.o(*.text*))\n  *(.text)\n  *(.text*)\n  *(.text.*)\n  *(.gnu.warning)\n  *(.stub)\n  *(.gnu.linkonce.t*)\n  *(.glue_7t)\n  *(.glue_7)\n  *(.jcr)\n  *(.init)\n  *(.fini)\n  . = ALIGN (4) ;\n  PROVIDE(__ctbp = .);\n  *(.call_table_data)\n  *(.call_table_text)\n\n\t\/* section information for finsh shell *\/\n\t. = ALIGN(4);\n\t__fsymtab_start = .;\n\tKEEP(*(FSymTab))\n\t__fsymtab_end = .;\n\t. = ALIGN(4);\n\t__vsymtab_start = .;\n\tKEEP(*(VSymTab))\n\t__vsymtab_end = .;\n\t. = ALIGN(4);\n\n\t\/* section information for initial. *\/\n\t. = ALIGN(4);\n\t__rt_init_start = .;\n\tKEEP(*(SORT(.rti_fn*)))\n\t__rt_init_end = .;\n\t. = ALIGN(4);\n  . = ALIGN(0x10) ;\n  __etext = . ;\n } > REGION_TEXT\n .eh_frame_hdr : {\n  *(.eh_frame_hdr)\n } > REGION_TEXT\n .eh_frame : ONLY_IF_RO {\n  KEEP (*(.eh_frame))\n } > REGION_TEXT\n .gcc_except_table : ONLY_IF_RO {\n  *(.gcc_except_table .gcc_except_table.*)\n } > REGION_TEXT\n .rodata :{\n  . = ALIGN(0x4) ;\n  __srodata = .;\n  *(.rdata)\n  *(.rdata*)\n  *(.rdata1)\n  *(.rdata.*)\n  *(.rodata)\n  *(.rodata1)\n  *(.rodata*)\n  *(.rodata.*)\n  *(.srodata*)\n  *(.rodata.str1.4)\n  . = ALIGN(0x4) ;\n  __ctor_start__ = .;\n  KEEP (*(SORT(.ctors.*)))\n  KEEP (*(.ctors))\n  __ctor_end__ = .;\n  KEEP (*(SORT(.dtors.*)))\n  KEEP (*(.dtors))\n  __dtor_end__ = .;\n  . = ALIGN(0x4) ;\n  __erodata = .;\n  __rodata_end__ = .;\n } > REGION_RODATA\n .data : {\n  . = ALIGN(0x4) ;\n  __data_start__ = . ;\n  __sdata = . ;\n  data_start = . ;\n  KEEP(*startup_gcc.o(*.vectors*))\n  *(.got.plt)\n  *(.got)\n  *(.gnu.linkonce.r*)\n  *(.data)\n  *(.data*)\n  *(.data1)\n  *(.data.*)\n  *(.gnu.linkonce.d*)\n  *(.data1)\n  *(.gcc_except_table)\n  *(.gcc_except_table*)\n  __start_init_call = .;\n  *(.initcall.init)\n  __stop_init_call = .;\n  __start_cmd = .;\n  *(.bootloaddata.cmd)\n  . = ALIGN(4) ;\n  __stop_cmd = .;\n  __global_pointer$ = .;\n  *(.sdata)\n  *(.sdata.*)\n  *(.gnu.linkonce.s.*)\n  *(__libc_atexit)\n  *(__libc_subinit)\n  *(__libc_subfreeres)\n  *(.note.ABI-tag)\n  __edata = .;\n  __data_end__ = .;\n  . = ALIGN(0x4) ;\n\n } > REGION_DATA AT > REGION_RODATA\n .eh_frame : ONLY_IF_RW {\n  KEEP (*(.eh_frame))\n } > REGION_DATA AT > REGION_RODATA\n .gcc_except_table : ONLY_IF_RW {\n  *(.gcc_except_table .gcc_except_table.*)\n  __edata = .;\n  __data_end__ = .;\n } > REGION_DATA AT > REGION_RODATA\n\n\n .bss : {\n  . = ALIGN(0x4) ;\n  __sbss = ALIGN(0x4) ;\n  __bss_start__ = . ;\n  *(.dynsbss)\n  *(.sbss)\n  *(.sbss.*)\n  *(.scommon)\n  *(.dynbss)\n  *(.bss)\n  *(.bss.*)\n  *(COMMON)\n  . = ALIGN(0x4) ;\n  __ebss = . ;\n  __end = . ;\n  end = . ;\n  __bss_end__ = .;\n } > REGION_BSS\n  \/* End of uninitalized data segement *\/\n  PROVIDE(end = .);\n}\n","old_contents":"\/*\n * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *   http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/******************************************************************************\n * @file     gcc_csky.h\n * @brief    csky linker file for PHOBOS\n * @version  V1.0\n * @date     02. June 2017\n ******************************************************************************\/\nMEMORY\n{\n    I-SRAM : ORIGIN = 0x0        , LENGTH = 0x40000   \/* I-SRAM  256KB *\/\n    D-SRAM : ORIGIN = 0x20000000 , LENGTH = 0xc0000   \/* D-SRAM  768KB *\/\n    O-SRAM : ORIGIN = 0x50000000 , LENGTH = 0x800000   \/* off-chip SRAM 8MB *\/\n    SRAM   : ORIGIN = 0x60000000 , LENGTH = 0x20000   \/* on-chip SRAM 128KB *\/\n}\n\nPROVIDE (__StackTop = 0x200c0000 - 0x8);\nPROVIDE (Stack_Size = 0x1000);\n\nREGION_ALIAS(\"REGION_TEXT\",    I-SRAM);\nREGION_ALIAS(\"REGION_RODATA\",  I-SRAM);\nREGION_ALIAS(\"REGION_CUSTOM1\", D-SRAM);\nREGION_ALIAS(\"REGION_CUSTOM2\", D-SRAM);\nREGION_ALIAS(\"REGION_DATA\",    D-SRAM);\nREGION_ALIAS(\"REGION_BSS\",     D-SRAM);\n\nENTRY(Reset_Handler)\nSECTIONS\n{\n  .text : AT(ADDR(.text)){\n  . = ALIGN(0x4) ;\n  __stext = . ;\n  KEEP(*startup.o(*.text*))\n  *(.text)\n  *(.text*)\n  *(.text.*)\n  *(.gnu.warning)\n  *(.stub)\n  *(.gnu.linkonce.t*)\n  *(.glue_7t)\n  *(.glue_7)\n  *(.jcr)\n  *(.init)\n  *(.fini)\n  . = ALIGN (4) ;\n  PROVIDE(__ctbp = .);\n  *(.call_table_data)\n  *(.call_table_text)\n\n\t\/* section information for finsh shell *\/\n\t. = ALIGN(4);\n\t__fsymtab_start = .;\n\tKEEP(*(FSymTab))\n\t__fsymtab_end = .;\n\t. = ALIGN(4);\n\t__vsymtab_start = .;\n\tKEEP(*(VSymTab))\n\t__vsymtab_end = .;\n\t. = ALIGN(4);\n\n\t\/* section information for initial. *\/\n\t. = ALIGN(4);\n\t__rt_init_start = .;\n\tKEEP(*(SORT(.rti_fn*)))\n\t__rt_init_end = .;\n\t. = ALIGN(4);\n  . = ALIGN(0x10) ;\n  __etext = . ;\n } > REGION_TEXT\n .eh_frame_hdr : {\n  *(.eh_frame_hdr)\n } > REGION_TEXT\n .eh_frame : ONLY_IF_RO {\n  KEEP (*(.eh_frame))\n } > REGION_TEXT\n .gcc_except_table : ONLY_IF_RO {\n  *(.gcc_except_table .gcc_except_table.*)\n } > REGION_TEXT\n .rodata :{\n  . = ALIGN(0x4) ;\n  __srodata = .;\n  *(.rdata)\n  *(.rdata*)\n  *(.rdata1)\n  *(.rdata.*)\n  *(.rodata)\n  *(.rodata1)\n  *(.rodata*)\n  *(.rodata.*)\n  *(.srodata*)\n  *(.rodata.str1.4)\n  . = ALIGN(0x4) ;\n  __ctor_start__ = .;\n  KEEP (*(SORT(.ctors.*)))\n  KEEP (*(.ctors))\n  __ctor_end__ = .;\n  KEEP (*(SORT(.dtors.*)))\n  KEEP (*(.dtors))\n  __dtor_end__ = .;\n  . = ALIGN(0x4) ;\n  __erodata = .;\n  __rodata_end__ = .;\n } > REGION_RODATA\n .data : {\n  . = ALIGN(0x4) ;\n  __data_start__ = . ;\n  __sdata = . ;\n  data_start = . ;\n  KEEP(*startup_gcc.o(*.vectors*))\n  *(.got.plt)\n  *(.got)\n  *(.gnu.linkonce.r*)\n  *(.data)\n  *(.data*)\n  *(.data1)\n  *(.data.*)\n  *(.gnu.linkonce.d*)\n  *(.data1)\n  *(.gcc_except_table)\n  *(.gcc_except_table*)\n  __start_init_call = .;\n  *(.initcall.init)\n  __stop_init_call = .;\n  __start_cmd = .;\n  *(.bootloaddata.cmd)\n  . = ALIGN(4) ;\n  __stop_cmd = .;\n  __global_pointer$ = .;\n  *(.sdata)\n  *(.sdata.*)\n  *(.gnu.linkonce.s.*)\n  *(__libc_atexit)\n  *(__libc_subinit)\n  *(__libc_subfreeres)\n  *(.note.ABI-tag)\n  __edata = .;\n  __data_end__ = .;\n  . = ALIGN(0x4) ;\n\n } > REGION_DATA AT > REGION_RODATA\n .eh_frame : ONLY_IF_RW {\n  KEEP (*(.eh_frame))\n } > REGION_DATA AT > REGION_RODATA\n .gcc_except_table : ONLY_IF_RW {\n  *(.gcc_except_table .gcc_except_table.*)\n  __edata = .;\n  __data_end__ = .;\n } > REGION_DATA AT > REGION_RODATA\n\n\n .bss : {\n  . = ALIGN(0x4) ;\n  __sbss = ALIGN(0x4) ;\n  __bss_start__ = . ;\n  *(.dynsbss)\n  *(.sbss)\n  *(.sbss.*)\n  *(.scommon)\n  *(.dynbss)\n  *(.bss)\n  *(.bss.*)\n  *(COMMON)\n  . = ALIGN(0x4) ;\n  __ebss = . ;\n  __end = . ;\n  end = . ;\n  __bss_end__ = .;\n } > REGION_BSS\n  \/* End of uninitalized data segement *\/\n  PROVIDE(end = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d6c68f26914bf9508e8b76081d383a5cd432c7b6","subject":"flash.ld: fix mis-aligned .data section","message":"flash.ld: fix mis-aligned .data section\n\nThe end of the .data section in flash must be explicitly word-aligned,\notherwise corruption can occur in a .data section that happens to contain\nnon-word aligned data.\n","repos":"sandeepmistry\/corelibs-arduino101,yashaswini-hanji\/corelibs-arduino101,sandeepmistry\/corelibs-arduino101,SidLeung\/corelibs-arduino101,yashaswini-hanji\/corelibs-arduino101,01org\/corelibs-arduino101,bigdinotech\/corelibs-arduino101,sgbihu\/corelibs-arduino101,sgbihu\/corelibs-arduino101,01org\/corelibs-arduino101,sgbihu\/corelibs-arduino101,bigdinotech\/corelibs-arduino101,SidLeung\/corelibs-arduino101,sandeepmistry\/corelibs-arduino101,01org\/corelibs-arduino101,yashaswini-hanji\/corelibs-arduino101,bigdinotech\/corelibs-arduino101","old_file":"variants\/arduino_101\/linker_scripts\/flash.ld","new_file":"variants\/arduino_101\/linker_scripts\/flash.ld","new_contents":"\/* linker.cmd - Linker command\/script file *\/\n\n\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1) Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2) Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and\/or other materials provided with the distribution.\n *\n * 3) Neither the name of Wind River Systems nor the names of its contributors\n * may be used to endorse or promote products derived from this software without\n * specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\/\n\n\/*\nDESCRIPTION\nLinker script for the Arduino 101 ARC BSPs.\n*\/\n\nOUTPUT_FORMAT(\"elf32-littlearc\", \"elf32-bigarc\", \"elf32-littlearc\")\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = 0x40034000, LENGTH = 152K\n    SRAM                  (wx) : ORIGIN = 0xa800e000, LENGTH = 24K\n    DCCM                  (wx) : ORIGIN = 0x80000000, LENGTH = 8K\n    }\n\n\/* Define default stack size and FIRQ stack size.\n * See below stack section for __stack_start and __firq_stack_start\n *\/\n__stack_size = 2048;\n__firq_stack_size = 1024;\n\n\/* Minimum heap size to allocate\n * Actual heap size might be bigger due to page size alignment *\/\n__HEAP_SIZE_MIN = 8192;\n\/* This should be set to the page size used by the malloc implementation *\/\n__PAGE_SIZE = 4096;\n\nSECTIONS\n    {\n\/* FLASH Start *\/\n\n    text : ALIGN(1024)\n\t{\n\t__text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\tKEEP(*(.int_vector_table))\n\tKEEP(*(\".int_vector_table.*\"))\n\n\t*(.version_header)\n\tKEEP(*(\".version_header*\"))\n\n\t*(.text)\n\t*(\".text.*\")\n\t__text_end = .;\n\t} > FLASH\n\n    ctors :\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __ctor_table_start must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first element of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } > FLASH\n\n    rodata :\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t} > FLASH\n\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n\/* FLASH End *\/\n\n\/* SRAM Start *\/\n\n    datas : AT(__data_rom_start)\n\t{\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t. = ALIGN(4);\n\t} > SRAM\n\n    __data_ram_end = .;\n\n    bss (NOLOAD) :\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n        \/*\n         * BSP clears this memory in words only and doesn't clear any\n         * potential left over bytes.\n\t *\/\n\t__bss_end = ALIGN(4);\n\t} > SRAM\n\n    noinit (NOLOAD) :\n        {\n        \/*\n         * This section is used for non-intialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t\/*\n\t * The seg_rxtx section is used by the Host IO module for\n\t * allocating RX\/TX buffers. If a specific memory location is\n\t * required for these buffers, then a MEMORY definition should be\n\t * made.\n\t *\/\n\t*(.seg_rxtx)\n\t*(\".seg_rxtx.*\")\n        } > SRAM\n\n    heap (NOLOAD) :\n    {\n        . = ALIGN(4);\n        __start_heap = .;\n        . = . + __HEAP_SIZE_MIN;\n        __end_heap = ALIGN(__PAGE_SIZE);\n    } > SRAM\n\n    stack :\n    {\n        . += __firq_stack_size;\n        . = ALIGN(4);\n        __firq_stack_start = .;\n\n        . += __stack_size;\n        . = ALIGN(4);\n        __stack_start = .;\n    } > SRAM\n\n    \/* Define linker symbols *\/\n\n    _end = .; \/* end of image *\/\n\n\/* SRAM End *\/\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\/* DCCM Start *\/\n\/* DCCM End *\/\n\n    }\n","old_contents":"\/* linker.cmd - Linker command\/script file *\/\n\n\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1) Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2) Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and\/or other materials provided with the distribution.\n *\n * 3) Neither the name of Wind River Systems nor the names of its contributors\n * may be used to endorse or promote products derived from this software without\n * specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\/\n\n\/*\nDESCRIPTION\nLinker script for the Arduino 101 ARC BSPs.\n*\/\n\nOUTPUT_FORMAT(\"elf32-littlearc\", \"elf32-bigarc\", \"elf32-littlearc\")\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = 0x40034000, LENGTH = 152K\n    SRAM                  (wx) : ORIGIN = 0xa800e000, LENGTH = 24K\n    DCCM                  (wx) : ORIGIN = 0x80000000, LENGTH = 8K\n    }\n\n\/* Define default stack size and FIRQ stack size.\n * See below stack section for __stack_start and __firq_stack_start\n *\/\n__stack_size = 2048;\n__firq_stack_size = 1024;\n\n\/* Minimum heap size to allocate\n * Actual heap size might be bigger due to page size alignment *\/\n__HEAP_SIZE_MIN = 8192;\n\/* This should be set to the page size used by the malloc implementation *\/\n__PAGE_SIZE = 4096;\n\nSECTIONS\n    {\n\/* FLASH Start *\/\n\n    text : ALIGN(1024)\n\t{\n\t__text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\tKEEP(*(.int_vector_table))\n\tKEEP(*(\".int_vector_table.*\"))\n\n\t*(.version_header)\n\tKEEP(*(\".version_header*\"))\n\n\t*(.text)\n\t*(\".text.*\")\n\t__text_end = .;\n\t} > FLASH\n\n    ctors :\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __ctor_table_start must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first element of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } > FLASH\n\n    rodata :\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t} > FLASH\n\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n\/* FLASH End *\/\n\n\/* SRAM Start *\/\n\n    datas : AT(__data_rom_start)\n\t{\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t} > SRAM\n\n    __data_ram_end = .;\n\n    bss (NOLOAD) :\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n        \/*\n         * BSP clears this memory in words only and doesn't clear any\n         * potential left over bytes.\n\t *\/\n\t__bss_end = ALIGN(4);\n\t} > SRAM\n\n    noinit (NOLOAD) :\n        {\n        \/*\n         * This section is used for non-intialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t\/*\n\t * The seg_rxtx section is used by the Host IO module for\n\t * allocating RX\/TX buffers. If a specific memory location is\n\t * required for these buffers, then a MEMORY definition should be\n\t * made.\n\t *\/\n\t*(.seg_rxtx)\n\t*(\".seg_rxtx.*\")\n        } > SRAM\n\n    heap (NOLOAD) :\n    {\n        . = ALIGN(4);\n        __start_heap = .;\n        . = . + __HEAP_SIZE_MIN;\n        __end_heap = ALIGN(__PAGE_SIZE);\n    } > SRAM\n\n    stack :\n    {\n        . += __firq_stack_size;\n        . = ALIGN(4);\n        __firq_stack_start = .;\n\n        . += __stack_size;\n        . = ALIGN(4);\n        __stack_start = .;\n    } > SRAM\n\n    \/* Define linker symbols *\/\n\n    _end = .; \/* end of image *\/\n\n\/* SRAM End *\/\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\/* DCCM Start *\/\n\/* DCCM End *\/\n\n    }\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"f2e2b6621538dbbc1ee55d418566c8e5fd02d08f","subject":"arch: arm: aarch64: Fix _vector_end symbol placement","message":"arch: arm: aarch64: Fix _vector_end symbol placement\n\nThis commit relocates the `_vector_end` symbol that was previously\nplaced after the OpenOCD sections to before these sections, as the\nOpenOCD debug sections are not part of the \"vector table.\"\n\nSigned-off-by: Stephanos Ioannidis <dc76e9f0c0006e8f919e0c515c66dbba3982f785@stephanos.io>\n","repos":"galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n  \/* If building without MPU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM       (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n        KEEP(*(.vector_relay_table))\n        KEEP(*(\".vector_relay_table.*\"))\n        KEEP(*(.vector_relay_handler))\n        KEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(IRQ_VECTOR_TABLE))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    MPU_ALIGN(_image_rodata_end -_image_rom_start);\n    _image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        *(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n    } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n    #define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#else\n    #define NSC_ALIGN . = ALIGN(4)\n#endif\n\n    #define NSC_ALIGN_END . = ALIGN(4)\n\n    SECTION_PROLOGUE(.gnu.sgstubs,,)\n    {\n        NSC_ALIGN;\n        __sg_start = .;\n        \/* No input section necessary, since the Secure Entry Veneers are\n           automatically placed after the .gnu.sgstubs output section. *\/\n    } GROUP_LINK_IN(ROMABLE_REGION)\n    __sg_end = .;\n    __sg_size = __sg_end - __sg_start;\n    NSC_ALIGN_END;\n    __nsc_size = . - __sg_start;\n\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n  \/* If building without MPU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM       (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n        KEEP(*(.vector_relay_table))\n        KEEP(*(\".vector_relay_table.*\"))\n        KEEP(*(.vector_relay_handler))\n        KEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(IRQ_VECTOR_TABLE))\n\n        KEEP(*(.vectors))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        _vector_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    MPU_ALIGN(_image_rodata_end -_image_rom_start);\n    _image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        *(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n    } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n    #define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#else\n    #define NSC_ALIGN . = ALIGN(4)\n#endif\n\n    #define NSC_ALIGN_END . = ALIGN(4)\n\n    SECTION_PROLOGUE(.gnu.sgstubs,,)\n    {\n        NSC_ALIGN;\n        __sg_start = .;\n        \/* No input section necessary, since the Secure Entry Veneers are\n           automatically placed after the .gnu.sgstubs output section. *\/\n    } GROUP_LINK_IN(ROMABLE_REGION)\n    __sg_end = .;\n    __sg_size = __sg_end - __sg_start;\n    NSC_ALIGN_END;\n    __nsc_size = . - __sg_start;\n\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"40200fa160c2009496890fcb71e822b12626fbd7","subject":"Remove misleading comments.","message":"Remove misleading comments.\n","repos":"rafalcieslak\/mimiker,cahirwpz\/mimiker,dyniec\/mimiker,cahirwpz\/mimiker,dyniec\/mimiker,Darge\/mimiker,Darge\/mimiker,dyniec\/mimiker,rafalcieslak\/mimiker,czapiga\/mimiker,cahirwpz\/mimiker,rafalcieslak\/mimiker,cahirwpz\/wifire-os,czapiga\/mimiker,cahirwpz\/mimiker,rafalcieslak\/mimiker,dyniec\/mimiker,Darge\/mimiker,czapiga\/mimiker,czapiga\/mimiker","old_file":"malta.ld","new_file":"malta.ld","new_contents":"\/* Linker script for OVPsim SmartLoaderLinux firmware. *\/\nOUTPUT_ARCH(mips)\nENTRY(_start)\nPHDRS\n{\n  text PT_LOAD FLAGS(5); \/* read-only, executable *\/\n  data PT_LOAD FLAGS(6); \/* read-write *\/\n}\nSECTIONS\n{\n  \/* RAM is mapped in kseg0 (cacheable) and kseg1 (non-cacheable) *\/\n  _ram = 0x80000000;\n\n  .text 0x80100000:\n  {\n    \/* Exception handlers. *\/\n    _ebase = ABSOLUTE(.);\n    *(.ebase)\n    . = ALIGN(4096);\n    \/* Text and read-only data follows. *\/\n    __text = ABSOLUTE(.);\n    *(.text .text.*)\n    . = ALIGN (4);\n    *(.rodata .rodata.*)\n    __etext = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } : text\n\n  .data ADDR(.text) + SIZEOF (.text):\n  {\n    __data = ABSOLUTE(.);\n    _gp = .;\n    *(.data .data.*)\n    *(.sdata .sdata.*)\n    . = ALIGN(4);\n    __edata = ABSOLUTE(.);\n  } : data\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n    __bss = ABSOLUTE(.);\n    *(.sbss .scommon)\n    *(.bss .bss.*)\n    *(COMMON)\n    . = ALIGN (4);\n    __ebss = ABSOLUTE(.);\n  }\n\n  _end = .;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ :\n  {\n    *(.comment)\n    *(.note)\n    *(.options)\n    *(.pdr)\n    *(.reginfo)\n    *(.gnu.attributes)\n    *(.MIPS.abiflags)\n    *(.MIPS.options)\n  }\n}\n","old_contents":"\/* Linker script for OVPsim SmartLoaderLinux firmware. *\/\nOUTPUT_ARCH(mips)\nENTRY(_start)\nPHDRS\n{\n  text PT_LOAD FLAGS(5); \/* read-only, executable *\/\n  data PT_LOAD FLAGS(6); \/* read-write *\/\n}\nSECTIONS\n{\n  \/* RAM is mapped in kseg0 (cacheable) and kseg1 (non-cacheable) *\/\n  _ram = 0x80000000;\n\n  .text 0x80100000:\n  {\n    \/* Exception handlers. *\/\n    _ebase = ABSOLUTE(.);\n    *(.ebase)\n    . = ALIGN(4096);\n    \/* Execution starts here. *\/\n    __text = ABSOLUTE(.);\n    *(.text .text.*)\n    . = ALIGN (4);\n    *(.rodata .rodata.*)\n    __etext = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } : text\n\n  \/* Data is mapped onto Program Flash and copied to RAM at startup. *\/\n  .data ADDR(.text) + SIZEOF (.text):\n  {\n    __data = ABSOLUTE(.);\n    _gp = .;\n    *(.data .data.*)\n    *(.sdata .sdata.*)\n    . = ALIGN(4);\n    __edata = ABSOLUTE(.);\n  } : data\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n    __bss = ABSOLUTE(.);\n    *(.sbss .scommon)\n    *(.bss .bss.*)\n    *(COMMON)\n    . = ALIGN (4);\n    __ebss = ABSOLUTE(.);\n  }\n\n  _end = .;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ :\n  {\n    *(.comment)\n    *(.note)\n    *(.options)\n    *(.pdr)\n    *(.reginfo)\n    *(.gnu.attributes)\n    *(.MIPS.abiflags)\n    *(.MIPS.options)\n  }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"4d3996f9e0e872f28fecf7c3026aaa818021bd3e","subject":"updated linker script","message":"updated linker script\n","repos":"stateos\/IntrOS-STM32F3Discovery,stateos\/IntrOS-STM32F3Discovery","old_file":"startup\/STM32F3\/GNUCC\/script.ld","new_file":"startup\/STM32F3\/GNUCC\/script.ld","new_contents":"\/*******************************************************************************\n@file     stm32f3xx.ld\n@author   Rajmund Szymanski\n@date     28.02.2017\n@brief    Linker script for STM32F303VC device with 256KB FLASH and 48KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 256k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   8k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  48k\n}\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__heap_start = LOADADDR(.proc_stack);\n\t__heap_end   = __ram_end - __proc_stack_size;\n\n\t__proc_stack_start = __heap_end;\n\t__proc_stack_end   = __ram_end;\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n\tPROVIDE(__process_stack_end   = __proc_stack_end);\n}\n","old_contents":"\/*******************************************************************************\n@file     stm32f3xx.ld\n@author   Rajmund Szymanski\n@date     02.01.2017\n@brief    Linker script for STM32F303VC device with 256KB FLASH and 48KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 256k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   8k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  48k\n}\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t. = ABSOLUTE(__ram_end - __proc_stack_size);\n\t\t__heap_end = .;\n\t} > RAM\n\n\t__heap_size = SIZEOF(.heap);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"9cdf7d0f74630872aa5001c7cd07c4a9e80b075d","subject":"config.ld: add configuration for additional topics","message":"config.ld: add configuration for additional topics\n","repos":"RyanSquared\/FusionScript","old_file":"config.ld","new_file":"config.ld","new_contents":"-- luacheck: ignore\nfile = {'bin', 'fusion'} -- vim:set noet sts=0 sw=3 ts=3 filetype=lua:\ndir = 'docs'\nproject = 'FusionScript'\ndescription = 'The programming language of ultimate dankliness'\ntitle = 'FusionScript &middot; Documentation'\nstyle = '!pale'\ntopics = {\n\t'docs\/_topics\/FusionScript.md';\n\t'docs\/_topics\/Syntax.md';\n}\nkind_names = {topic='Manual', script='Programs'}\nall = true\nformat = 'markdown'\n","old_contents":"-- luacheck: ignore\nfile = {'bin', 'fusion'} -- vim:set noet sts=0 sw=3 ts=3 filetype=lua:\ndir = 'docs'\nproject = 'FusionScript'\ndescription = 'The programming language of ultimate dankliness'\ntitle = 'FusionScript &middot; Documentation'\nstyle = '!pale'\nreadme = 'README.md'\nall = true\nformat = 'markdown'\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"bbbb4cd2a5c202e3a8edf2665bde9592cae84d66","subject":"Fixed linker layout for isr table","message":"Fixed linker layout for isr table","repos":"farcaller\/arm-demos,farcaller\/arm-demos,farcaller\/arm-demos,farcaller\/arm-demos","old_file":"04-hello-world\/platform\/protoboard\/layout.ld","new_file":"04-hello-world\/platform\/protoboard\/layout.ld","new_contents":"_stack_base = 0x10002000;\n_boot_checksum = 0 - (_stack_base + main + 1 + isr_nmi + 1 + isr_hardfault + 1);\n\nENTRY(main)\n\nMEMORY\n{\n    rom(RX)   : ORIGIN = 0x00000000, LENGTH = 0x8000\n    ram(WAIL) : ORIGIN = 0x10000000, LENGTH = 0x2000\n}\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        KEEP(*(.isr_vector_nvic))\n        *(.text*)\n    } > rom\n}\n","old_contents":"_stack_base = 0x10002000;\n_boot_checksum = 0 - (_stack_base + main + 1 + (hang + 1) * 5);\n\nENTRY(main)\n\nMEMORY\n{\n    rom(RX)   : ORIGIN = 0x00000000, LENGTH = 0x8000\n    ram(WAIL) : ORIGIN = 0x10000000, LENGTH = 0x2000\n}\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n    } > rom\n}\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"0a1c2a3f54f1debde4e60a1554027cad3a8f9602","subject":"RAM\u3092\u4fee\u6b63","message":"RAM\u3092\u4fee\u6b63\n","repos":"taniho0707\/Ikaru,taniho0707\/Ikaru","old_file":"STM32F412CGUx_FLASH.ld","new_file":"STM32F412CGUx_FLASH.ld","new_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F412CGUx Device with\n**                1024KByte FLASH, 256KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n*****************************************************************************\n** @attention\n**\n** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6<\/center><\/h2>\n**\n** Redistribution and use in source and binary forms, with or without modification,\n** are permitted provided that the following conditions are met:\n**   1. Redistributions of source code must retain the above copyright notice,\n**      this list of conditions and the following disclaimer.\n**   2. Redistributions in binary form must reproduce the above copyright notice,\n**      this list of conditions and the following disclaimer in the documentation\n**      and\/or other materials provided with the distribution.\n**   3. Neither the name of Ac6 nor the names of its contributors\n**      may be used to endorse or promote products derived from this software\n**      without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20040000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x31000;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x7000; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 256K\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","old_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F412CGUx Device with\n**                1024KByte FLASH, 256KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n*****************************************************************************\n** @attention\n**\n** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6<\/center><\/h2>\n**\n** Redistribution and use in source and binary forms, with or without modification,\n** are permitted provided that the following conditions are met:\n**   1. Redistributions of source code must retain the above copyright notice,\n**      this list of conditions and the following disclaimer.\n**   2. Redistributions in binary form must reproduce the above copyright notice,\n**      this list of conditions and the following disclaimer in the documentation\n**      and\/or other materials provided with the distribution.\n**   3. Neither the name of Ac6 nor the names of its contributors\n**      may be used to endorse or promote products derived from this software\n**      without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20040000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size  = 0x24000;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x10000; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 256K\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"838c45f26f3cb040757ed2748d41ea801f0534aa","subject":"make multiboot load_end_addr work","message":"make multiboot load_end_addr work\n","repos":"bnoordhuis\/marnix","old_file":"multiboot.ld","new_file":"multiboot.ld","new_contents":"OUTPUT_FORMAT (elf32-i386)\nOUTPUT_ARCH (i386)\n\nSECTIONS\n{\n  . = SIZEOF_HEADERS;\n\n  .multiboot ALIGN(16) :\n  {\n    LONG(0x1BADB002);               \/* multiboot magic *\/\n    LONG(0x10003);                  \/* align | meminfo | address *\/\n    LONG(-(0x1BADB002 + 0x10003));  \/* checksum *\/\n\n    \/* address *\/\n    LONG(ADDR(.multiboot));\n    LONG(ADDR(.text));\n    LONG(ADDR(.data) + SIZEOF(.data));\n    LONG(ADDR(.bss) + SIZEOF(.bss));\n    LONG(kern_init);\n  }\n\n  .text 0x100000 :\n  {\n    *(.text)\n  }\n\n  .rodata ALIGN (4096) :\n  {\n    *(.rodata*)\n  }\n\n  .data :\n  {\n    *(.data*)\n  }\n\n  .bss :\n  {\n    *(COMMON)\n    *(.bss*)\n\n    . = ALIGN(4096);\n    __kern_stack = . + 32768;\n  }\n}\n","old_contents":"OUTPUT_FORMAT (elf32-i386)\nOUTPUT_ARCH (i386)\n\nSECTIONS\n{\n  . = SIZEOF_HEADERS;\n\n  .multiboot ALIGN(16) :\n  {\n    LONG(0x1BADB002);               \/* multiboot magic *\/\n    LONG(0x10003);                  \/* align | meminfo | address *\/\n    LONG(-(0x1BADB002 + 0x10003));  \/* checksum *\/\n\n    \/* address *\/\n    LONG(ADDR(.multiboot));\n    LONG(ADDR(.text));\n    \/* LONG(ADDR(.data) + SIZEOF(.data)); *\/\n    LONG(0);\n    LONG(ADDR(.bss) + SIZEOF(.bss));\n    LONG(kern_init);\n  }\n\n  .text 0x100000 :\n  {\n    *(.text)\n  }\n\n  .rodata ALIGN (4096) :\n  {\n    *(.rodata*)\n  }\n\n  .data ALIGN (4096) :\n  {\n    *(.data*)\n  }\n\n  .bss ALIGN (4096) :\n  {\n    __bss_start = .;\n    *(COMMON)\n    *(.bss*)\n    __bss_end = .;\n    __kern_stack = . + 32768;\n  }\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"76cdffa988724914a9d20d817a611c274c14a818","subject":"updated linker scripts","message":"updated linker scripts\n","repos":"insidegui\/flux,insidegui\/flux,nickbjohnson4224\/rhombus,nickbjohnson4224\/rhombus","old_file":"kernel\/src\/link.ld","new_file":"kernel\/src\/link.ld","new_contents":"ENTRY(start)\nOUTPUT_FORMAT(elf32-i386)\n\nSECTIONS {\n\t. = 0xFF100000;\n\n\t.text : AT(ADDR(.text) - 0xFF000000) {\n\t\t*(.text)\n\t\t*(.rodata*)\n\t}\n\n\t.data : AT(ADDR(.data) - 0xFF000000) {\n\t\t*(.data)\n\t}\n\n\t.pdata ALIGN (0x1000) : AT(ADDR(.pdata) - 0xFF000000) {\n\t\t*(.pdata)\n\t}\n\n\t.tdata ALIGN (0x1000) : AT(ADDR(.tdata) - 0xFF000000) {\n\t\tSTART_OF_TEMP = .;\n\t\t*(.tdata)\n\t}\n\n\t.ttext : AT(ADDR(.ttext) - 0xFF000000) {\n\t\t*(.ttext)\n\t\t. = ALIGN(0x1000);\n\t\tEND_OF_TEMP = .;\n\t}\n\n\t.bss : AT(ADDR(.bss) - 0xFF000000) {\n\t\t_sbss = .;\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t_ebss = .;\n\t}\n\n\tend = .; _end = .; __end = .;\n}\n\n","old_contents":"ENTRY(start)\nOUTPUT_FORMAT(elf32-i386)\n\nSECTIONS {\n\t. = 0xF8100000;\n\n\t.text : AT(ADDR(.text) - 0xF8000000) {\n\t\t*(.text)\n\t\t*(.rodata*)\n\t}\n\n\t.data : AT(ADDR(.data) - 0xF8000000) {\n\t\t*(.data)\n\t}\n\n\t.pdata ALIGN (0x1000) : AT(ADDR(.pdata) - 0xF8000000) {\n\t\t*(.pdata)\n\t}\n\n\t.tdata ALIGN (0x1000) : AT(ADDR(.tdata) - 0xF8000000) {\n\t\tSTART_OF_TEMP = .;\n\t\t*(.tdata)\n\t}\n\n\t.ttext : AT(ADDR(.ttext) - 0xF8000000) {\n\t\t*(.ttext)\n\t\t. = ALIGN(0x1000);\n\t\tEND_OF_TEMP = .;\n\t}\n\n\t.bss : AT(ADDR(.bss) - 0xF8000000) {\n\t\t_sbss = .;\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t_ebss = .;\n\t}\n\n\tend = .; _end = .; __end = .;\n}\n\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"481304f126d03ebad0a6afd4a6647278a408b9d8","subject":"Modified linker script to include an end symbol","message":"Modified linker script to include an end symbol\n","repos":"mvdnes\/element76","old_file":"link.ld","new_file":"link.ld","new_contents":"\/*\n *  link.ld\n *\/\nOUTPUT_FORMAT(elf32-i386)\nENTRY(start)\nSECTIONS\n{\n\t. = 0x100000;\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.bootstrap_stack)\n\t\t*(.text)\n\t\t. = ALIGN(4096);\n\t\tKEEP(*(.multiboot))\n\t}\n\t.data :\n\t{\n\t\t*(.data)\n\t\t. = ALIGN(4096);\n\t}\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t. = ALIGN(4096);\n\t}\n\tend = .;\n}\n","old_contents":"\/*\n *  link.ld\n *\/\nOUTPUT_FORMAT(elf32-i386)\nENTRY(start)\nSECTIONS\n {\n   . = 0x100000;\n   .multiboot : { *(.multiboot) KEEP(*(.multiboot)) }\n   .text : { *(.bootstrap_stack) *(.text) }\n   .data : { *(.data) }\n   .bss  : { *(.bss)  }\n }\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"04e1084b2248bb706cdd0016f4ff08b37a136057","subject":"move braces around in link.ld","message":"move braces around in link.ld","repos":"blin00\/os","old_file":"link.ld","new_file":"link.ld","new_contents":"ENTRY(_start)\n\nSECTIONS {\n    \/* load at 1 MB *\/\n    . = 0x00100000;\n    \/* align each section to 4 KB *\/\n    .text ALIGN(0x1000): {\n        *(.multiboot)\n        *(.text)\n    }\n\n    .rodata ALIGN(0x1000): {\n        *(.rodata)\n    }\n\n    .data ALIGN(0x1000): {\n        *(.data)\n    }\n\n    .bss ALIGN(0x1000): {\n        *(COMMON)\n        *(.bss)\n    }\n\n    . = ALIGN(0x1000);\n\n    _kernel_end = .;\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS {\n    \/* load at 1 MB *\/\n    . = 0x00100000;\n    \/* align each section to 4 KB *\/\n    .text ALIGN(0x1000): {\n        *(.multiboot)\n        *(.text)\n    }\n\n    .rodata ALIGN(0x1000):\n    {\n        *(.rodata)\n    }\n\n    .data ALIGN(0x1000):\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(0x1000):\n    {\n        *(COMMON)\n        *(.bss)\n    }\n\n    . = ALIGN(0x1000);\n\n    _kernel_end = .;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f71c0699a5093a6483203c8f2d9b94b872b4db84","subject":"esp8266: Put utils.o to FlashROM.","message":"esp8266: Put utils.o to FlashROM.\n","repos":"dxxb\/micropython,chrisdearman\/micropython,pfalcon\/micropython,matthewelse\/micropython,jmarcelino\/pycom-micropython,deshipu\/micropython,AriZuu\/micropython,alex-march\/micropython,toolmacher\/micropython,bvernoux\/micropython,micropython\/micropython-esp32,MrSurly\/micropython,micropython\/micropython-esp32,adafruit\/micropython,misterdanb\/micropython,pramasoul\/micropython,henriknelson\/micropython,henriknelson\/micropython,swegener\/micropython,micropython\/micropython-esp32,HenrikSolver\/micropython,pfalcon\/micropython,lowRISC\/micropython,trezor\/micropython,oopy\/micropython,Peetz0r\/micropython-esp32,adafruit\/circuitpython,infinnovation\/micropython,pramasoul\/micropython,mpalomer\/micropython,lowRISC\/micropython,cwyark\/micropython,matthewelse\/micropython,hosaka\/micropython,turbinenreiter\/micropython,matthewelse\/micropython,ganshun666\/micropython,Peetz0r\/micropython-esp32,ganshun666\/micropython,deshipu\/micropython,dxxb\/micropython,tobbad\/micropython,kerneltask\/micropython,lowRISC\/micropython,swegener\/micropython,tuc-osg\/micropython,praemdonck\/micropython,infinnovation\/micropython,PappaPeppar\/micropython,MrSurly\/micropython,praemdonck\/micropython,chrisdearman\/micropython,pramasoul\/micropython,PappaPeppar\/micropython,hiway\/micropython,MrSurly\/micropython,jmarcelino\/pycom-micropython,pozetroninc\/micropython,redbear\/micropython,alex-robbins\/micropython,ryannathans\/micropython,drrk\/micropython,alex-robbins\/micropython,MrSurly\/micropython-esp32,HenrikSolver\/micropython,oopy\/micropython,cwyark\/micropython,tuc-osg\/micropython,MrSurly\/micropython-esp32,alex-robbins\/micropython,oopy\/micropython,TDAbboud\/micropython,kerneltask\/micropython,Timmenem\/micropython,deshipu\/micropython,drrk\/micropython,deshipu\/micropython,swegener\/micropython,mhoffma\/micropython,jmarcelino\/pycom-micropython,tobbad\/micropython,MrSurly\/micropython,selste\/micropython,toolmacher\/micropython,Peetz0r\/micropython-esp32,chrisdearman\/micropython,henriknelson\/micropython,emfcamp\/micropython,alex-march\/micropython,MrSurly\/micropython-esp32,SHA2017-badge\/micropython-esp32,misterdanb\/micropython,trezor\/micropython,praemdonck\/micropython,pfalcon\/micropython,tuc-osg\/micropython,jmarcelino\/pycom-micropython,Peetz0r\/micropython-esp32,adafruit\/micropython,blazewicz\/micropython,trezor\/micropython,dmazzella\/micropython,mhoffma\/micropython,emfcamp\/micropython,adafruit\/circuitpython,toolmacher\/micropython,pozetroninc\/micropython,cwyark\/micropython,kerneltask\/micropython,swegener\/micropython,puuu\/micropython,redbear\/micropython,ryannathans\/micropython,dxxb\/micropython,turbinenreiter\/micropython,mhoffma\/micropython,blazewicz\/micropython,blazewicz\/micropython,micropython\/micropython-esp32,turbinenreiter\/micropython,Timmenem\/micropython,mhoffma\/micropython,henriknelson\/micropython,hiway\/micropython,torwag\/micropython,kerneltask\/micropython,misterdanb\/micropython,trezor\/micropython,oopy\/micropython,mpalomer\/micropython,Timmenem\/micropython,drrk\/micropython,hiway\/micropython,PappaPeppar\/micropython,hiway\/micropython,pozetroninc\/micropython,matthewelse\/micropython,selste\/micropython,pfalcon\/micropython,cwyark\/micropython,TDAbboud\/micropython,HenrikSolver\/micropython,AriZuu\/micropython,jmarcelino\/pycom-micropython,PappaPeppar\/micropython,tralamazza\/micropython,chrisdearman\/micropython,hiway\/micropython,torwag\/micropython,dmazzella\/micropython,SHA2017-badge\/micropython-esp32,redbear\/micropython,AriZuu\/micropython,torwag\/micropython,SHA2017-badge\/micropython-esp32,lowRISC\/micropython,blazewicz\/micropython,SHA2017-badge\/micropython-esp32,trezor\/micropython,adafruit\/circuitpython,redbear\/micropython,matthewelse\/micropython,selste\/micropython,emfcamp\/micropython,infinnovation\/micropython,emfcamp\/micropython,dinau\/micropython,praemdonck\/micropython,TDAbboud\/micropython,lowRISC\/micropython,micropython\/micropython-esp32,ryannathans\/micropython,pramasoul\/micropython,mpalomer\/micropython,PappaPeppar\/micropython,hosaka\/micropython,hosaka\/micropython,bvernoux\/micropython,emfcamp\/micropython,alex-robbins\/micropython,puuu\/micropython,Timmenem\/micropython,bvernoux\/micropython,adafruit\/circuitpython,adafruit\/micropython,torwag\/micropython,mpalomer\/micropython,pramasoul\/micropython,swegener\/micropython,tobbad\/micropython,mpalomer\/micropython,adafruit\/circuitpython,mhoffma\/micropython,puuu\/micropython,alex-march\/micropython,kerneltask\/micropython,ryannathans\/micropython,HenrikSolver\/micropython,tralamazza\/micropython,adafruit\/micropython,Timmenem\/micropython,toolmacher\/micropython,puuu\/micropython,henriknelson\/micropython,turbinenreiter\/micropython,alex-march\/micropython,AriZuu\/micropython,tuc-osg\/micropython,alex-robbins\/micropython,tobbad\/micropython,pozetroninc\/micropython,MrSurly\/micropython,ganshun666\/micropython,dmazzella\/micropython,ganshun666\/micropython,selste\/micropython,alex-march\/micropython,pfalcon\/micropython,tralamazza\/micropython,bvernoux\/micropython,redbear\/micropython,dmazzella\/micropython,puuu\/micropython,dinau\/micropython,AriZuu\/micropython,tobbad\/micropython,chrisdearman\/micropython,cwyark\/micropython,hosaka\/micropython,dxxb\/micropython,dinau\/micropython,hosaka\/micropython,MrSurly\/micropython-esp32,blazewicz\/micropython,praemdonck\/micropython,SHA2017-badge\/micropython-esp32,deshipu\/micropython,pozetroninc\/micropython,toolmacher\/micropython,matthewelse\/micropython,misterdanb\/micropython,selste\/micropython,dxxb\/micropython,tuc-osg\/micropython,misterdanb\/micropython,TDAbboud\/micropython,infinnovation\/micropython,dinau\/micropython,ryannathans\/micropython,Peetz0r\/micropython-esp32,oopy\/micropython,infinnovation\/micropython,adafruit\/circuitpython,drrk\/micropython,tralamazza\/micropython,dinau\/micropython,torwag\/micropython,MrSurly\/micropython-esp32,bvernoux\/micropython,ganshun666\/micropython,HenrikSolver\/micropython,turbinenreiter\/micropython,drrk\/micropython,TDAbboud\/micropython,adafruit\/micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"562cd84678190f978c4e6921a587d4a269172371","subject":"Change SRAM mapping and increase SRAM allocated to ARC core -increase SRAM to 40K -change SRAM start address -increase heap size to 16K -this change is needed for BLE scan for SensorTag","message":"Change SRAM mapping and increase SRAM allocated to ARC core\n-increase SRAM to 40K\n-change SRAM start address\n-increase heap size to 16K\n-this change is needed for BLE scan for SensorTag\n","repos":"bigdinotech\/corelibs-arduino101,sandeepmistry\/corelibs-arduino101,sgbihu\/corelibs-arduino101,bigdinotech\/corelibs-arduino101,sgbihu\/corelibs-arduino101,sandeepmistry\/corelibs-arduino101,bigdinotech\/corelibs-arduino101,01org\/corelibs-arduino101,01org\/corelibs-arduino101,sandeepmistry\/corelibs-arduino101,01org\/corelibs-arduino101,sgbihu\/corelibs-arduino101","old_file":"variants\/arduino_101\/linker_scripts\/flash.ld","new_file":"variants\/arduino_101\/linker_scripts\/flash.ld","new_contents":"\/* linker.cmd - Linker command\/script file *\/\n\n\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1) Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2) Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and\/or other materials provided with the distribution.\n *\n * 3) Neither the name of Wind River Systems nor the names of its contributors\n * may be used to endorse or promote products derived from this software without\n * specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\/\n\n\/*\nDESCRIPTION\nLinker script for the Arduino 101 ARC BSPs.\n*\/\n\nOUTPUT_FORMAT(\"elf32-littlearc\", \"elf32-bigarc\", \"elf32-littlearc\")\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = 0x40034000, LENGTH = 152K\n    SRAM                  (wx) : ORIGIN = 0xa800a000, LENGTH = 40K\n    DCCM                  (wx) : ORIGIN = 0x80000000, LENGTH = 8K\n    }\n\n\/* Define default stack size and FIRQ stack size.\n * See below stack section for __stack_start and __firq_stack_start\n *\/\n__stack_size = 2048;\n__firq_stack_size = 1024;\n\n\/* Minimum heap size to allocate\n * Actual heap size might be bigger due to page size alignment *\/\n__HEAP_SIZE_MIN = 16384;\n\/* This should be set to the page size used by the malloc implementation *\/\n__PAGE_SIZE = 4096;\n\nSECTIONS\n    {\n\/* FLASH Start *\/\n\n    text : ALIGN(1024)\n\t{\n\t__text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\tKEEP(*(.int_vector_table))\n\tKEEP(*(\".int_vector_table.*\"))\n\n\t*(.version_header)\n\tKEEP(*(\".version_header*\"))\n\n\t*(.text)\n\t*(\".text.*\")\n\t__text_end = .;\n\t} > FLASH\n\n    ctors :\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __ctor_table_start must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first element of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } > FLASH\n\n    rodata :\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t} > FLASH\n\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n\/* FLASH End *\/\n\n\/* SRAM Start *\/\n\n    datas : AT(__data_rom_start)\n\t{\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t. = ALIGN(4);\n\t} > SRAM\n\n    __data_ram_end = .;\n\n    bss (NOLOAD) :\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n        \/*\n         * BSP clears this memory in words only and doesn't clear any\n         * potential left over bytes.\n\t *\/\n\t__bss_end = ALIGN(4);\n\t} > SRAM\n\n    noinit (NOLOAD) :\n        {\n        \/*\n         * This section is used for non-intialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t\/*\n\t * The seg_rxtx section is used by the Host IO module for\n\t * allocating RX\/TX buffers. If a specific memory location is\n\t * required for these buffers, then a MEMORY definition should be\n\t * made.\n\t *\/\n\t*(.seg_rxtx)\n\t*(\".seg_rxtx.*\")\n        } > SRAM\n\n    heap (NOLOAD) :\n    {\n        . = ALIGN(4);\n        __start_heap = .;\n        . = . + __HEAP_SIZE_MIN;\n        __end_heap = ALIGN(__PAGE_SIZE);\n    } > SRAM\n\n    stack :\n    {\n        . += __firq_stack_size;\n        . = ALIGN(4);\n        __firq_stack_start = .;\n\n        . += __stack_size;\n        . = ALIGN(4);\n        __stack_start = .;\n    } > SRAM\n\n    \/* Define linker symbols *\/\n\n    _end = .; \/* end of image *\/\n\n\/* SRAM End *\/\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\/* DCCM Start *\/\n\/* DCCM End *\/\n\n    }\n","old_contents":"\/* linker.cmd - Linker command\/script file *\/\n\n\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1) Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2) Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and\/or other materials provided with the distribution.\n *\n * 3) Neither the name of Wind River Systems nor the names of its contributors\n * may be used to endorse or promote products derived from this software without\n * specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\/\n\n\/*\nDESCRIPTION\nLinker script for the Arduino 101 ARC BSPs.\n*\/\n\nOUTPUT_FORMAT(\"elf32-littlearc\", \"elf32-bigarc\", \"elf32-littlearc\")\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = 0x40034000, LENGTH = 152K\n    SRAM                  (wx) : ORIGIN = 0xa800e000, LENGTH = 24K\n    DCCM                  (wx) : ORIGIN = 0x80000000, LENGTH = 8K\n    }\n\n\/* Define default stack size and FIRQ stack size.\n * See below stack section for __stack_start and __firq_stack_start\n *\/\n__stack_size = 2048;\n__firq_stack_size = 1024;\n\n\/* Minimum heap size to allocate\n * Actual heap size might be bigger due to page size alignment *\/\n__HEAP_SIZE_MIN = 8192;\n\/* This should be set to the page size used by the malloc implementation *\/\n__PAGE_SIZE = 4096;\n\nSECTIONS\n    {\n\/* FLASH Start *\/\n\n    text : ALIGN(1024)\n\t{\n\t__text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\tKEEP(*(.int_vector_table))\n\tKEEP(*(\".int_vector_table.*\"))\n\n\t*(.version_header)\n\tKEEP(*(\".version_header*\"))\n\n\t*(.text)\n\t*(\".text.*\")\n\t__text_end = .;\n\t} > FLASH\n\n    ctors :\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __ctor_table_start must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first element of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } > FLASH\n\n    rodata :\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t} > FLASH\n\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n\/* FLASH End *\/\n\n\/* SRAM Start *\/\n\n    datas : AT(__data_rom_start)\n\t{\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t. = ALIGN(4);\n\t} > SRAM\n\n    __data_ram_end = .;\n\n    bss (NOLOAD) :\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n        \/*\n         * BSP clears this memory in words only and doesn't clear any\n         * potential left over bytes.\n\t *\/\n\t__bss_end = ALIGN(4);\n\t} > SRAM\n\n    noinit (NOLOAD) :\n        {\n        \/*\n         * This section is used for non-intialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t\/*\n\t * The seg_rxtx section is used by the Host IO module for\n\t * allocating RX\/TX buffers. If a specific memory location is\n\t * required for these buffers, then a MEMORY definition should be\n\t * made.\n\t *\/\n\t*(.seg_rxtx)\n\t*(\".seg_rxtx.*\")\n        } > SRAM\n\n    heap (NOLOAD) :\n    {\n        . = ALIGN(4);\n        __start_heap = .;\n        . = . + __HEAP_SIZE_MIN;\n        __end_heap = ALIGN(__PAGE_SIZE);\n    } > SRAM\n\n    stack :\n    {\n        . += __firq_stack_size;\n        . = ALIGN(4);\n        __firq_stack_start = .;\n\n        . += __stack_size;\n        . = ALIGN(4);\n        __stack_start = .;\n    } > SRAM\n\n    \/* Define linker symbols *\/\n\n    _end = .; \/* end of image *\/\n\n\/* SRAM End *\/\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\/* DCCM Start *\/\n\/* DCCM End *\/\n\n    }\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"0de729572b70dca479cf4627b01e08c03e24d7ba","subject":"cc2538: Word-align .data LMA","message":"cc2538: Word-align .data LMA\n\nIn order to be fast, the reset_handler() function uses word accesses to\ninitialize the .data output section. However, most toolchains do not\nautomatically force the alignment of an output section LMA to use the\nmaximum alignment of all its input sections. Because of that, assuming\nthat .data contains some words, the LMA of the .data output section was\nnot word-aligned in some cases, resulting in an initialization performed\nusing slow unaligned word accesses.\n\nThis commit forces the alignment of the LMA of the .data output section\nwith a word boundary in order to always use fast aligned word accesses\nto read the .data load area.\n\nNote that this solution is better than using ALIGN_WITH_INPUT, both\nbecause the latter is a new feature incompatible with older toolchains,\nand because it could create a big gap between _etext and the LMA of\n.data if strongly-aligned data were added to .data, although only a word\nalignment is required here.\n\nThe same considerations apply to the VMA of .data. However, it is\nalready automatically word-aligned, both because .data contains words,\nand because the end VMA of the previous output section (.socdata) is\nword-aligned. Moreover, if the VMA of .data were forcibly word-aligned,\nthen a filled gap could appear at the beginning of this section if\nstrongly-aligned data were added to it, thus wasting flash memory.\nConsequently, it's better not to change anything for the VMA of .data,\nall the more it's very unlikely that it does not contain any word and\nthat the end VMA of .socdata becomes non-word-aligned, and this would\nonly result in a slower initialization.\n\nSigned-off-by: Beno\u00eet Th\u00e9baudeau <b3efeb72fa9d3102885911404c5fbece843f6c8f@gmail.com>\n","repos":"MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,bluerover\/6lbr","old_file":"cpu\/cc2538\/cc2538.lds","new_file":"cpu\/cc2538\/cc2538.lds","new_contents":"\/*\n * Copyright (c) 2013, Texas Instruments Incorporated - http:\/\/www.ti.com\/\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\/*\n * cc2538 linker configuration file. This is not the actual file used at link\n * stage. Rather, it is used as input for the auto-generation of the actual\n * ld script, which is called cc2538.ld and will be in the project directory\n *\/\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n#define NRSRAM_START    0x20000000\n#define NRSRAM_LEN      0x00004000\n#define SRAM_START      0x20004000\n#define SRAM_LEN        0x00004000\n#else\n#define SRAM_START      0x20000000\n#define SRAM_LEN        0x00008000\n#endif\n\n#ifdef FLASH_CONF_ORIGIN\n#define FLASH_ORIGIN    FLASH_CONF_ORIGIN\n#else\n#error FLASH_CONF_ORIGIN is not specified. Please define FLASH_CONF_ORIGIN in contiki-conf.h.\n#endif\n\n#ifdef FLASH_CONF_SIZE\n#define FLASH_SIZE      FLASH_CONF_SIZE\n#else\n#error FLASH_CONF_SIZE is not specified. Please define FLASH_CONF_SIZE in contiki-conf.h.\n#endif\n\n#define FLASH_CCA_LENGTH 44\n#define FLASH_LENGTH     (FLASH_SIZE - FLASH_CCA_LENGTH)\n#define FLASH_CCA_ORIGIN (FLASH_ORIGIN + FLASH_LENGTH)\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = FLASH_LENGTH\n    FLASH_CCA (RX) : ORIGIN = FLASH_CCA_ORIGIN, LENGTH = FLASH_CCA_LENGTH\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    NRSRAM (RWX) : ORIGIN = NRSRAM_START, LENGTH = NRSRAM_LEN\n#endif\n    SRAM (RWX) : ORIGIN = SRAM_START, LENGTH = SRAM_LEN\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH= 0\n\n    .socdata (NOLOAD) :\n    {\n        *(.udma_channel_control_table)\n    } > SRAM\n\n    .data : ALIGN(4)\n    {\n        _data = .;\n        *(.data*)\n        _edata = .;\n    } > SRAM AT > FLASH\n    _ldata = LOADADDR(.data);\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n    } > FLASH\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    .nrdata (NOLOAD) :\n    {\n        _nrdata = .;\n        *(.nrdata*)\n        _enrdata = .;\n    } > NRSRAM\n#endif\n\n    .flashcca :\n    {\n        KEEP(*(.flashcca))\n    } > FLASH_CCA\n}\n","old_contents":"\/*\n * Copyright (c) 2013, Texas Instruments Incorporated - http:\/\/www.ti.com\/\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\/*\n * cc2538 linker configuration file. This is not the actual file used at link\n * stage. Rather, it is used as input for the auto-generation of the actual\n * ld script, which is called cc2538.ld and will be in the project directory\n *\/\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n#define NRSRAM_START    0x20000000\n#define NRSRAM_LEN      0x00004000\n#define SRAM_START      0x20004000\n#define SRAM_LEN        0x00004000\n#else\n#define SRAM_START      0x20000000\n#define SRAM_LEN        0x00008000\n#endif\n\n#ifdef FLASH_CONF_ORIGIN\n#define FLASH_ORIGIN    FLASH_CONF_ORIGIN\n#else\n#error FLASH_CONF_ORIGIN is not specified. Please define FLASH_CONF_ORIGIN in contiki-conf.h.\n#endif\n\n#ifdef FLASH_CONF_SIZE\n#define FLASH_SIZE      FLASH_CONF_SIZE\n#else\n#error FLASH_CONF_SIZE is not specified. Please define FLASH_CONF_SIZE in contiki-conf.h.\n#endif\n\n#define FLASH_CCA_LENGTH 44\n#define FLASH_LENGTH     (FLASH_SIZE - FLASH_CCA_LENGTH)\n#define FLASH_CCA_ORIGIN (FLASH_ORIGIN + FLASH_LENGTH)\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = FLASH_LENGTH\n    FLASH_CCA (RX) : ORIGIN = FLASH_CCA_ORIGIN, LENGTH = FLASH_CCA_LENGTH\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    NRSRAM (RWX) : ORIGIN = NRSRAM_START, LENGTH = NRSRAM_LEN\n#endif\n    SRAM (RWX) : ORIGIN = SRAM_START, LENGTH = SRAM_LEN\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH= 0\n\n    .socdata (NOLOAD) :\n    {\n        *(.udma_channel_control_table)\n    } > SRAM\n\n    .data :\n    {\n        _data = .;\n        *(.data*)\n        _edata = .;\n    } > SRAM AT > FLASH\n    _ldata = LOADADDR(.data);\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n    } > FLASH\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    .nrdata (NOLOAD) :\n    {\n        _nrdata = .;\n        *(.nrdata*)\n        _enrdata = .;\n    } > NRSRAM\n#endif\n\n    .flashcca :\n    {\n        KEEP(*(.flashcca))\n    } > FLASH_CCA\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"54c161d5883f90cf3ab3c8d693705de0caa7b7d1","subject":"removed junk from flash.lds","message":"removed junk from flash.lds\n","repos":"RoboJackets\/robocup-software,JNeiger\/robocup-software,RoboJackets\/robocup-software,JNeiger\/robocup-software,JNeiger\/robocup-software,RoboJackets\/robocup-software,JNeiger\/robocup-software,JNeiger\/robocup-software,RoboJackets\/robocup-software","old_file":"firmware\/robot\/cpu\/at91sam7s256\/flash.lds","new_file":"firmware\/robot\/cpu\/at91sam7s256\/flash.lds","new_contents":"\/* ----------------------------------------------------------------------------\n *         ATMEL Microcontroller Software Support\n * ----------------------------------------------------------------------------\n * Copyright (c) 2008, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\n\/*------------------------------------------------------------------------------\n *      Linker script for running in internal Flash on the AT91SAM7S64.\n *----------------------------------------------------------------------------*\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(entry)\n\nMEMORY\n{\n    sram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x10000\n    flash (RX) : ORIGIN = 0x100000, LENGTH = 0x40000\n}\n\nSECTIONS\n{  \n    .fixed :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n\t\t*(.startup)\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n\t\t_sbuild_id = .;\n\t\t*(.note.gnu.build-id)\n        . = ALIGN(4);\n\t\t_ebuild_id = .;\n        _efixed = .;\n    } >flash\n\n\n    .relocate : AT (_efixed)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.vectors)\n        *(.ramfunc)\n        *(.data)\n\t\t\n\t\t\/* Reflashing code is stored in flash after relocate when not in use, but will be\n\t\t* copied to SRAM.  It doesn't actually matter where in SRAM this goes\n\t\t* as long as it doesn't hit the stack.  When reflash runs, the rest\n\t\t* of the system is unrecoverable and interrupts are off so collisions\n\t\t* (except for the stack) are irrelevant.\n\t\t* \n\t\t* FIXME - This keeps reflash in RAM all the time.  I want it to overlap data\/bss\n\t\t* so we don't waste space when not reflashing.  Can you force ld to overlap?\n\t\t*\/\n\t\t*(.reflash)\n\t\t\n        . = ALIGN(4);\n        _erelocate = .;\n    } >sram\n\n\/*\n\t.reflash : AT(_efixed + _erelocate - _srelocate)\n\t{\n        . = ALIGN(4);\n\t\t_sreflash = .;\n\t\t*(.reflash)\n\t\t. = ALIGN(4);\n\t\t_ereflash = .;\n\t} >sram\n\t*\/\n\t\n    .bss (NOLOAD) : {\n        _szero = .;\n        *(.bss)\n\t\t*(COMMON)\n        . = ALIGN(4);\n        _ezero = .;\n    } >sram\n    \n    _sstack = 0x204000;\n}\nend = .;\n\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         ATMEL Microcontroller Software Support\n * ----------------------------------------------------------------------------\n * Copyright (c) 2008, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\n\/*------------------------------------------------------------------------------\n *      Linker script for running in internal Flash on the AT91SAM7S64.\n *----------------------------------------------------------------------------*\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(entry)\n\nMEMORY\n{\n    sram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x10000\n    flash (RX) : ORIGIN = 0x100000, LENGTH = 0x40000\n}\n\nSECTIONS\n{  \n    .fixed :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n\t\t*(.startup)\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n\t\t_sbuild_id = .;\n\t\t*(.note.gnu.build-id)\n        . = ALIGN(4);\n\t\t_ebuild_id = .;\n        _efixed = .;\n\n        \n\n        \/*\n        PROVIDE_HIDDEN (__exidx_start = .);\n        .ARM.exidx :\n        {\n            *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        }\n        PROVIDE_HIDDEN (__exidx_end = .);\n        *\/\n\n\n\n    } >flash\n\n    .ARM.extab 0 : { *(.ARM.extab) }\n    .ARM.exidx 0 : { *(.ARM.exidx) }\n\n    \/*\n    Stolen from: www.state-machine.com\/arm\/Building_bare-metal_ARM_with_GNU.pdf.\n    Not entirely sure yet if it will work...\n    \n    .ARM.exidx :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } >sram;\n    _etext = .;\n    *\/\n\n    \n\n    .relocate : AT (_efixed)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.vectors)\n        *(.ramfunc)\n        *(.data)\n\t\t\n\t\t\/* Reflashing code is stored in flash after relocate when not in use, but will be\n\t\t* copied to SRAM.  It doesn't actually matter where in SRAM this goes\n\t\t* as long as it doesn't hit the stack.  When reflash runs, the rest\n\t\t* of the system is unrecoverable and interrupts are off so collisions\n\t\t* (except for the stack) are irrelevant.\n\t\t* \n\t\t* FIXME - This keeps reflash in RAM all the time.  I want it to overlap data\/bss\n\t\t* so we don't waste space when not reflashing.  Can you force ld to overlap?\n\t\t*\/\n\t\t*(.reflash)\n\t\t\n        . = ALIGN(4);\n        _erelocate = .;\n    } >sram\n\n\/*\n\t.reflash : AT(_efixed + _erelocate - _srelocate)\n\t{\n        . = ALIGN(4);\n\t\t_sreflash = .;\n\t\t*(.reflash)\n\t\t. = ALIGN(4);\n\t\t_ereflash = .;\n\t} >sram\n\t*\/\n\t\n    .bss (NOLOAD) : {\n        _szero = .;\n        *(.bss)\n\t\t*(COMMON)\n        . = ALIGN(4);\n        _ezero = .;\n    } >sram\n    \n    _sstack = 0x204000;\n}\nend = .;\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"15516ed0ef148051fd752a62df3e29ccd09fa457","subject":"linker: riscv: Relocate .eh_frame symbol","message":"linker: riscv: Relocate .eh_frame symbol\n\nThe .eh_frame symbol was causing __data_rom_start to contain the wrong\noffset into the ROM, resulting in corrupt data copied into RAM by\n_data_copy(). Fix by placing the .eh_frame in the .text section as is\ndone in include\/arch\/x86\/linker.ld\n\nSigned-off-by: Nathaniel Graff <e7e2d91f1deb937cded6d6fc8e8292f24ce08299@sifive.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,explora26\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,galak\/zephyr,kraj\/zephyr,finikorg\/zephyr,ldts\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,ldts\/zephyr,nashif\/zephyr,punitvara\/zephyr,galak\/zephyr,kraj\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,kraj\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,kraj\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,nashif\/zephyr,ldts\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,kraj\/zephyr,ldts\/zephyr,nashif\/zephyr,explora26\/zephyr,Vudentz\/zephyr,explora26\/zephyr","old_file":"include\/arch\/riscv32\/common\/linker.ld","new_file":"include\/arch\/riscv32\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv32 platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <soc.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nMEMORY\n{\n    ROM (rx)  : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE\n    RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n    GROUP_START(ROM)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROM)\n\n    GROUP_END(ROM)\n\n    GROUP_START(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\t\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(\".noinit.*\")\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n     GROUP_END(RAMABLE_REGION)\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv32 platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <soc.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nMEMORY\n{\n    ROM (rx)  : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE\n    RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n    GROUP_START(ROM)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROM)\n\n    GROUP_END(ROM)\n\n    GROUP_START(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\t\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(\".noinit.*\")\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n     GROUP_END(RAMABLE_REGION)\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"233bd25b000f92fc4bbe181fa48edcd72808de8e","subject":"BaseTools GCC: move AutoGen.obj contents to .text section","message":"BaseTools GCC: move AutoGen.obj contents to .text section\n\nAll AutoGen.obj files consist of global GUID definitions, fixed\nand patchable PCDs and other data that is essentially read-only at\nruntime but has not been declared as such for various reasons.\n\nBy moving these contents to .text we achieve two things:\n- global GUIDs and other data items which must be constant for correct\n  program operation can no longer be modified, for instance, when\n  running a DXE_RUNTIME_MODULE binary under the OS with the Properties\n  Table feature for memory protection enabled;\n- the .data section becomes smaller, and may be dropped completely for\n  many XIP modules, which reduces wasted FV space if the PE\/COFF section\n  alignment is large.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>\nTested-by: Liming Gao <liming.gao@intel.com>\nTested-by: Leif Lindholm <leif.lindholm@linaro.org>\n\ngit-svn-id: 3158a46dfd52e07d1fda3e32e1ab2e353a00b20f@18137 6f19259b-4bc3-4df7-8a09-765794883524\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"BaseTools\/Scripts\/GccBase.lds","new_file":"BaseTools\/Scripts\/GccBase.lds","new_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are constant from the POV of the program,\r\n     * but most of its contents end up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     *\/\r\n    *:AutoGen.obj(.data .data.* .bss .bss.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.* *COM*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n  }\r\n}\r\n","old_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.* *COM*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"7b3ce0160e72efb90332e9c104a0727151b2b468","subject":"esp32\/esp32.custom_common.ld: Update to follow changes in IDF.","message":"esp32\/esp32.custom_common.ld: Update to follow changes in IDF.\n\nThis change follows the change in ESP IDF where the .data section is put\nbefore the .bss section, to reduce chance of bootloader having an issue\nwhen loading an application with a large .data section.\n","repos":"micropython\/micropython-esp32,SHA2017-badge\/micropython-esp32,SHA2017-badge\/micropython-esp32,Peetz0r\/micropython-esp32,Peetz0r\/micropython-esp32,Peetz0r\/micropython-esp32,micropython\/micropython-esp32,Peetz0r\/micropython-esp32,MrSurly\/micropython-esp32,MrSurly\/micropython-esp32,Peetz0r\/micropython-esp32,SHA2017-badge\/micropython-esp32,MrSurly\/micropython-esp32,micropython\/micropython-esp32,MrSurly\/micropython-esp32,micropython\/micropython-esp32,SHA2017-badge\/micropython-esp32,MrSurly\/micropython-esp32,micropython\/micropython-esp32,SHA2017-badge\/micropython-esp32","old_file":"esp32\/esp32.custom_common.ld","new_file":"esp32\/esp32.custom_common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *esp32\/panic.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *esp32\/panic.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a0c26dcaf47d706a6c2c3f98a662299ce88b6a90","subject":"config.ld: change configuration for add'l topics","message":"config.ld: change configuration for add'l topics\n","repos":"RyanSquared\/FusionScript","old_file":"config.ld","new_file":"config.ld","new_contents":"-- luacheck: ignore\nfile = {'bin', 'fusion'} -- vim:set noet sts=0 sw=3 ts=3 filetype=lua:\ndir = 'docs'\nproject = 'FusionScript'\ndescription = 'The programming language of ultimate dankliness'\ntitle = 'FusionScript &middot; Documentation'\nstyle = '!pale'\ntopics = {\n\t'.topics\/FusionScript.md';\n\t'.topics\/Syntax.md';\n}\nkind_names = {topic='Manual', script='Programs'}\nall = true\nformat = 'markdown'\n","old_contents":"-- luacheck: ignore\nfile = {'bin', 'fusion'} -- vim:set noet sts=0 sw=3 ts=3 filetype=lua:\ndir = 'docs'\nproject = 'FusionScript'\ndescription = 'The programming language of ultimate dankliness'\ntitle = 'FusionScript &middot; Documentation'\nstyle = '!pale'\ntopics = {\n\t'docs\/_topics\/FusionScript.md';\n\t'docs\/_topics\/Syntax.md';\n}\nkind_names = {topic='Manual', script='Programs'}\nall = true\nformat = 'markdown'\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"02f80303d4d4ddbd18e645080301338f7a06cad4","subject":"comment userland_layout.ld","message":"comment userland_layout.ld\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    int got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    int data_size;\n         *    uint32_t bss_start;\n         *    int bss_size;\n         *    uint32_t reldata_start;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_sbss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n    } > FLASH =0xFF\n\n\n\/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    _sbss = .;\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += STACK_SIZE;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += APP_HEAP_SIZE;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += KERNEL_HEAP_SIZE;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        LONG(LOADADDR(.got) - _text);\n        LONG(_got);\n        LONG(SIZEOF(.got));\n        LONG(LOADADDR(.data) - _text);\n        LONG(_data);\n        LONG(SIZEOF(.data));\n        LONG(_sbss);\n        LONG(SIZEOF(.bss));\n        LONG(LOADADDR(.endsec) - _text);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n    } > FLASH =0xFF\n\n\n\/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    _sbss = .;\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += STACK_SIZE;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += APP_HEAP_SIZE;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += KERNEL_HEAP_SIZE;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"65eca9890d06469ec4028d01722964a45a39dfdf","subject":"add output section `other` to guarantee `kernel_end_symbol_table_entry` is really at the end","message":"add output section `other` to guarantee `kernel_end_symbol_table_entry` is really at the end\n","repos":"phil-opp\/rustos-experiment","old_file":"arch\/x86_64\/assembly\/linker.ld","new_file":"arch\/x86_64\/assembly\/linker.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"unknown","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3a5374eef5f1db4c7ba5d423b4dc49091487f4ad","subject":"Enable `not_luadoc` option in config.ld to silence LDoc warning","message":"Enable `not_luadoc` option in config.ld to silence LDoc warning\n","repos":"craigbarnes\/lua-gumbo,craigbarnes\/lua-gumbo,craigbarnes\/lua-gumbo","old_file":"config.ld","new_file":"config.ld","new_contents":"project     = \"lua-gumbo\"\ntitle       = \"lua-gumbo\"\ndescription = \"Lua bindings for the Gumbo HTML5 parsing library\"\nno_summary  = true\nnot_luadoc  = true\nformat      = \"markdown\"\ndir         = \"docs\"\nfile        = \"lgumbo.c\"\nreadme      = \"README.md\"\nexamples    = {\"examples\/outline.lua\", \"test.lua\"}\n","old_contents":"project     = \"lua-gumbo\"\ntitle       = \"lua-gumbo\"\ndescription = \"Lua bindings for the Gumbo HTML5 parsing library\"\nno_summary  = true\nformat      = \"markdown\"\ndir         = \"docs\"\nfile        = \"lgumbo.c\"\nreadme      = \"README.md\"\nexamples    = {\"examples\/outline.lua\", \"test.lua\"}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"aa15ae94a9266340cbf0e366610d16d7f1e0d0bb","subject":"soc: riscv32: openisa_rv32m1: Link .srodata section","message":"soc: riscv32: openisa_rv32m1: Link .srodata section\n\nApply a similar fix to commit 0289a410baa07d79c2ceaa426e3d4c106f9dd273\nto the openisa_rv32m1 linker script for handling .srodata sections.\n\nOtherwise we get oprhan read-only data section.  Fix this by adding\nthe .srodata section to the RISC-V linker script.\n\nSigned-off-by: Kumar Gala <a5e5248af4cd4f0ed8c515f61d40a6e2db46a66e@linaro.org>\n","repos":"finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,ldts\/zephyr,nashif\/zephyr,ldts\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,ldts\/zephyr","old_file":"soc\/riscv32\/openisa_rv32m1\/linker.ld","new_file":"soc\/riscv32\/openisa_rv32m1\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n * Copyright (c) 2018 Foundries.io Ltd\n *\n * This file is based on:\n *\n * - include\/arch\/arm\/cortex_m\/scripts\/linker.ld\n * - include\/arch\/riscv32\/common\/linker.ld\n * - include\/arch\/riscv32\/pulpino\/linker.ld\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/*\n * Extra efforts would need to be taken to ensure the IRQ handlers are within\n * jumping distance of the vector table in non-XIP builds, so avoid them.\n *\/\n#define ROMABLE_REGION              ROM\n#define RAMABLE_REGION              RAM\n\n#define ROM_BASE CONFIG_RISCV32_RV32M1_ROM_BASE_ADDR\n#define ROM_SIZE CONFIG_RISCV32_RV32M1_ROM_SIZE\n#define RAM_BASE CONFIG_RISCV32_RV32M1_RAM_BASE_ADDR\n#define RAM_SIZE CONFIG_RISCV32_RV32M1_RAM_SIZE\n#define VECTOR_BASE CONFIG_RISCV32_RV32M1_VECTOR_BASE_ADDR\n#define VECTOR_SIZE CONFIG_RISCV32_RV32M1_VECTOR_SIZE\n\nMEMORY\n    {\n    ROM (rx)      : ORIGIN = ROM_BASE,    LENGTH = ROM_SIZE\n    \/*\n     * Each RISC-V core on this chip (RI5CY and ZERO-RISCY) has\n     * a vector table at the end of its flash bank. They are relocatable\n     * at runtime, but we need to put the reset vectors in hardcoded places.\n     *\n     * (The Arm core vector tables are at the beginning of each\n     * flash bank.)\n     *\/\n    VECTORS (rx)  : ORIGIN = VECTOR_BASE, LENGTH = VECTOR_SIZE\n    RAM (rwx)     : ORIGIN = RAM_BASE,    LENGTH = RAM_SIZE\n    \/*\n     * Special section, not included in the final binary, used\n     * to generate interrupt tables. See include\/linker\/intlist.ld.\n     *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROM)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t. = ALIGN(4);\n\n\t\/*\n\t * Respect for CONFIG_TEXT_SECTION_OFFSET is mandatory\n\t * for MCUboot support, so .reset.* and .exception.*\n\t * must come after that offset from ROM_BASE.\n\t *\/\n\tKEEP(*(.reset.*))\n\tKEEP(*(\".exception.entry.*\")) \/* contains __irq_wrapper *\/\n\t*(\".exception.other.*\")\n\n\tKEEP(*(.openocd_debug))\n\tKEEP(*(\".openocd_debug.*\"))\n\n\t_image_text_start = .;\n\t*(.text .text.*)\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROM)\n\n    _image_text_end = .;\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t. = ALIGN(4);\n\t*(.srodata)\n\t*(\".srodata.*\")\n\t*(.rodata)\n\t*(.rodata.*)\n\t*(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_end = .;\n    _image_rom_end = .;\n\n    \/* The vector table goes into core-dependent flash locations. *\/\n    SECTION_PROLOGUE(vectors,,)\n\t{\n\t_vector_start = .;\n\tKEEP(*(.vectors.*))\n\t} GROUP_LINK_IN(VECTORS)\n    _vector_end = .;\n\n    GROUP_END(ROM)\n\n    GROUP_START(RAM)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t. = ALIGN(4);\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(.data.*)\n\t*(.gnu.linkonce.s.*)\n\n\t\/* https:\/\/groups.google.com\/a\/groups.riscv.org\/d\/msg\/sw-dev\/60IdaZj27dY\/TKT3hbNlAgAJ *\/\n\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    __data_ram_end = .;\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\/*\n\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t * a multiple of 4 bytes, so it can be cleared in words.\n\t *\/\n\t . = ALIGN(4);\n\t __bss_start = .;\n\n\t *(.bss .bss.*)\n\t *(.sbss .sbss.*)\n\t COMMON_SYMBOLS\n\n\t \/* Ensure 4 byte alignment for the entire section. *\/\n\t . = ALIGN(4);\n\t  __bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t *(.noinit .noinit.*)\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n     GROUP_END(RAM)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n\/* Bogus section, post-processed during the build to initialize interrupts. *\/\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n    \/*\n     * Pulpino toolchains emit these sections; we don't care about them,\n     * but need to avoid build system warnings about orphaned sections.\n     *\/\n    SECTION_PROLOGUE(.Pulp_Chip.Info,,)\n\t{\n\t\t*(.Pulp_Chip.*)\n\t}\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n * Copyright (c) 2018 Foundries.io Ltd\n *\n * This file is based on:\n *\n * - include\/arch\/arm\/cortex_m\/scripts\/linker.ld\n * - include\/arch\/riscv32\/common\/linker.ld\n * - include\/arch\/riscv32\/pulpino\/linker.ld\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/*\n * Extra efforts would need to be taken to ensure the IRQ handlers are within\n * jumping distance of the vector table in non-XIP builds, so avoid them.\n *\/\n#define ROMABLE_REGION              ROM\n#define RAMABLE_REGION              RAM\n\n#define ROM_BASE CONFIG_RISCV32_RV32M1_ROM_BASE_ADDR\n#define ROM_SIZE CONFIG_RISCV32_RV32M1_ROM_SIZE\n#define RAM_BASE CONFIG_RISCV32_RV32M1_RAM_BASE_ADDR\n#define RAM_SIZE CONFIG_RISCV32_RV32M1_RAM_SIZE\n#define VECTOR_BASE CONFIG_RISCV32_RV32M1_VECTOR_BASE_ADDR\n#define VECTOR_SIZE CONFIG_RISCV32_RV32M1_VECTOR_SIZE\n\nMEMORY\n    {\n    ROM (rx)      : ORIGIN = ROM_BASE,    LENGTH = ROM_SIZE\n    \/*\n     * Each RISC-V core on this chip (RI5CY and ZERO-RISCY) has\n     * a vector table at the end of its flash bank. They are relocatable\n     * at runtime, but we need to put the reset vectors in hardcoded places.\n     *\n     * (The Arm core vector tables are at the beginning of each\n     * flash bank.)\n     *\/\n    VECTORS (rx)  : ORIGIN = VECTOR_BASE, LENGTH = VECTOR_SIZE\n    RAM (rwx)     : ORIGIN = RAM_BASE,    LENGTH = RAM_SIZE\n    \/*\n     * Special section, not included in the final binary, used\n     * to generate interrupt tables. See include\/linker\/intlist.ld.\n     *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROM)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t. = ALIGN(4);\n\n\t\/*\n\t * Respect for CONFIG_TEXT_SECTION_OFFSET is mandatory\n\t * for MCUboot support, so .reset.* and .exception.*\n\t * must come after that offset from ROM_BASE.\n\t *\/\n\tKEEP(*(.reset.*))\n\tKEEP(*(\".exception.entry.*\")) \/* contains __irq_wrapper *\/\n\t*(\".exception.other.*\")\n\n\tKEEP(*(.openocd_debug))\n\tKEEP(*(\".openocd_debug.*\"))\n\n\t_image_text_start = .;\n\t*(.text .text.*)\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROM)\n\n    _image_text_end = .;\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t. = ALIGN(4);\n\t*(.rodata)\n\t*(.rodata.*)\n\t*(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_end = .;\n    _image_rom_end = .;\n\n    \/* The vector table goes into core-dependent flash locations. *\/\n    SECTION_PROLOGUE(vectors,,)\n\t{\n\t_vector_start = .;\n\tKEEP(*(.vectors.*))\n\t} GROUP_LINK_IN(VECTORS)\n    _vector_end = .;\n\n    GROUP_END(ROM)\n\n    GROUP_START(RAM)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t. = ALIGN(4);\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(.data.*)\n\t*(.gnu.linkonce.s.*)\n\n\t\/* https:\/\/groups.google.com\/a\/groups.riscv.org\/d\/msg\/sw-dev\/60IdaZj27dY\/TKT3hbNlAgAJ *\/\n\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    __data_ram_end = .;\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\/*\n\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t * a multiple of 4 bytes, so it can be cleared in words.\n\t *\/\n\t . = ALIGN(4);\n\t __bss_start = .;\n\n\t *(.bss .bss.*)\n\t *(.sbss .sbss.*)\n\t COMMON_SYMBOLS\n\n\t \/* Ensure 4 byte alignment for the entire section. *\/\n\t . = ALIGN(4);\n\t  __bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t *(.noinit .noinit.*)\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n     GROUP_END(RAM)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n\/* Bogus section, post-processed during the build to initialize interrupts. *\/\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n    \/*\n     * Pulpino toolchains emit these sections; we don't care about them,\n     * but need to avoid build system warnings about orphaned sections.\n     *\/\n    SECTION_PROLOGUE(.Pulp_Chip.Info,,)\n\t{\n\t\t*(.Pulp_Chip.*)\n\t}\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2677008817e056eb73f7ed3e60687da1997f5c28","subject":"fw_reload_test: Setup linker script to write the app code after the bootloader.","message":"fw_reload_test: Setup linker script to write the app code after the\nbootloader.\n\nWe additionally ditch the flash config section. As two apps can't manage\nthis at the same time.\n","repos":"andrewparlane\/kinetis_test_projects,andrewparlane\/kinetis_test_projects","old_file":"frdm_k66f_board\/fw_reload_test\/kds\/settings\/MK66FN2M0xxx18_flash_app.ld","new_file":"frdm_k66f_board\/fw_reload_test\/kds\/settings\/MK66FN2M0xxx18_flash_app.ld","new_contents":"\/*\n** ###################################################################\n**     Processors:          MK66FN2M0VLQ18\n**                          MK66FN2M0VMD18\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015\n**     Version:             rev. 3.0, 2015-03-25\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/*\n   NOTE: This has been modified to place the app after the bootloader\n         Make sure that the value used in the origin and length fields\n         for program flash sections is the same as in the bootloader\n\n         Additionally we scrap the flash config section. That is managed\n         by the bootloader and not the app\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00008000 + 0x00000000,  LENGTH = 0x00000400\n  m_text                (RX)  : ORIGIN = 0x00008000 + 0x00000400,  LENGTH = 0x00200000 - (0x00008000 + 0x400)\n  m_data                (RW)  : ORIGIN = 0x1FFF0000,               LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000,               LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n}\n\n","old_contents":"\/*\n** ###################################################################\n**     Processors:          MK66FN2M0VLQ18\n**                          MK66FN2M0VMD18\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015\n**     Version:             rev. 3.0, 2015-03-25\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x001FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5691c4411a520338bcc06fb66887560d42d2fc84","subject":"Delete linker.ld","message":"Delete linker.ld","repos":"NETponents\/HiveOS,NETponents\/HiveOS","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 1M;\n\n\t\/* First put the multiboot header, as it is required to be put very early\n\t   early in the image or the bootloader won't recognize the file format.\n\t   Next we'll put the .text section. *\/\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t}\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"bf9f9f05edc45e41e549633c27bae49cd2bc9652","subject":"Sync linker scripts","message":"Sync linker scripts\n","repos":"tock\/libtock-rs","old_file":"layout.ld","new_file":"layout.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\nSTACK_SIZE = 2048;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 0x0040000\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0010000\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\nSTACK_SIZE = 2048;\nAPP_HEAP_SIZE = 1024;\nKERNEL_HEAP_SIZE = 1024;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 0x0040000\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0010000\n}\n\nSECTIONS {\n    \/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n\n    \/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n    } > SRAM\n\n    \/*\n     * __NOTE__: The following symbols are used only to hint to elf2tbf how much\n     * total memory to request from the OS.\n     *\/\n    .stack :\n    {\n        . += STACK_SIZE;\n    } > SRAM\n\n    .app_heap :\n    {\n        . += APP_HEAP_SIZE;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        . += KERNEL_HEAP_SIZE;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2264422f941554feed8011340253fa90965baedb","subject":"Fix inconsistent comments in ld script.","message":"Fix inconsistent comments in ld script.\n","repos":"lorenzo-stoakes\/haxv6,lorenzo-stoakes\/haxv6,lorenzo-stoakes\/haxv6,lorenzo-stoakes\/haxv6","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"\/*\n * Simple linker script for the JOS kernel.\n * See the GNU ld 'info' manual (\"info ld\") to learn the syntax.\n *\/\n\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSECTIONS\n{\n\t\/*\n\t * Link the kernel at this address: \".\" means the current address must be\n\t * equal to KERNLINK.\n\t *\/\n\t. = 0x80100000;\n\n\t.text : AT(0x100000) {\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t}\n\n\tPROVIDE(etext = .);\t\/* Define the 'etext' symbol to this value *\/\n\n\t.rodata : {\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t}\n\n\t\/* Include debugging information in kernel memory *\/\n\t.stab : {\n\t\tPROVIDE(__STAB_BEGIN__ = .);\n\t\t*(.stab);\n\t\tPROVIDE(__STAB_END__ = .);\n\t\tBYTE(0)\t\t\/* Force the linker to allocate space for this section *\/\n\t}\n\n\t.stabstr : {\n\t\tPROVIDE(__STABSTR_BEGIN__ = .);\n\t\t*(.stabstr);\n\t\tPROVIDE(__STABSTR_END__ = .);\n\t\tBYTE(0)\t\t\/* Force the linker to allocate space for this section *\/\n\t}\n\n\t\/* Adjust the address for the data segment to the next page *\/\n\t. = ALIGN(0x1000);\n\n\n\t\/*\n\t * Conventionally, Unix linkers provide pseudo-symbols etext, edata, and\n\t * end, at the end of the text, data, and bss. For the kernel mapping, we\n\t * need the address at the beginning of the data section, but that's not\n\t * one of the conventional symbols, because the convention started before\n\t * there was a read-only rodata section between text and data.\n\t *\/\n\tPROVIDE(data = .);\n\n\t\/* The data segment *\/\n\t.data : {\n\t\t*(.data)\n\t}\n\n\tPROVIDE(edata = .);\n\n\t.bss : {\n\t\t*(.bss)\n\t}\n\n\tPROVIDE(end = .);\n\n\t\/DISCARD\/ : {\n\t\t*(.eh_frame .note.GNU-stack)\n\t}\n}\n","old_contents":"\/* Simple linker script for the JOS kernel.\n   See the GNU ld 'info' manual (\"info ld\") to learn the syntax. *\/\n\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSECTIONS\n{\n\t\/* Link the kernel at this address: \".\" means the current address *\/\n        \/* Must be equal to KERNLINK *\/\n\t. = 0x80100000;\n\n\t.text : AT(0x100000) {\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t}\n\n\tPROVIDE(etext = .);\t\/* Define the 'etext' symbol to this value *\/\n\n\t.rodata : {\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t}\n\n\t\/* Include debugging information in kernel memory *\/\n\t.stab : {\n\t\tPROVIDE(__STAB_BEGIN__ = .);\n\t\t*(.stab);\n\t\tPROVIDE(__STAB_END__ = .);\n\t\tBYTE(0)\t\t\/* Force the linker to allocate space\n\t\t\t\t   for this section *\/\n\t}\n\n\t.stabstr : {\n\t\tPROVIDE(__STABSTR_BEGIN__ = .);\n\t\t*(.stabstr);\n\t\tPROVIDE(__STABSTR_END__ = .);\n\t\tBYTE(0)\t\t\/* Force the linker to allocate space\n\t\t\t\t   for this section *\/\n\t}\n\n\t\/* Adjust the address for the data segment to the next page *\/\n\t. = ALIGN(0x1000);\n\n\t\/* Conventionally, Unix linkers provide pseudo-symbols\n\t * etext, edata, and end, at the end of the text, data, and bss.\n\t * For the kernel mapping, we need the address at the beginning\n\t * of the data section, but that's not one of the conventional\n\t * symbols, because the convention started before there was a\n\t * read-only rodata section between text and data. *\/\n\tPROVIDE(data = .);\n\n\t\/* The data segment *\/\n\t.data : {\n\t\t*(.data)\n\t}\n\n\tPROVIDE(edata = .);\n\n\t.bss : {\n\t\t*(.bss)\n\t}\n\n\tPROVIDE(end = .);\n\n\t\/DISCARD\/ : {\n\t\t*(.eh_frame .note.GNU-stack)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8cdc8e4ad6aeefa74cf84401b91b1d9495fcb1ec","subject":"linker.ld: Swapped .init.text and .text sections","message":"linker.ld: Swapped .init.text and .text sections\n","repos":"akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix","old_file":"linker.ld","new_file":"linker.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    . = 0x00100000;\n    .setup :\n    {\n    __start_setup = .;\n        *(.setup)\n        *(.setup.data)\n        boot\/boot.o(.bss)\n        boot\/boot.o(COMMON)\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf) \n    {\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n        *(.text)\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    . = 0x00100000;\n    .setup :\n    {\n    __start_setup = .;\n        *(.setup)\n        *(.setup.data)\n        boot\/boot.o(.bss)\n        boot\/boot.o(COMMON)\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf) \n    {\n        *(.text)\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"abdbdb1a5c03f7889c6b19f7288f12c568d37da6","subject":"move libm to flash (.irom0.text) saves 3544 Byte in ram see #104","message":"move libm to flash (.irom0.text)\nsaves 3544 Byte in ram\nsee #104\n","repos":"gonium\/Arduino,piersoft\/esp8266-Arduino,mattvenn\/Arduino,gonium\/Arduino,tannewt\/Arduino,plinioseniore\/Arduino,Cloudino\/Cloudino-Arduino-IDE,sanyaade-iot\/Arduino-1,Cloudino\/Arduino,probonopd\/Arduino,smily77\/Arduino,eeijcea\/Arduino-1,koltegirish\/Arduino,mc-hamster\/esp8266-Arduino,probonopd\/Arduino,mc-hamster\/esp8266-Arduino,aichi\/Arduino-2,myrtleTree33\/Arduino,drpjk\/Arduino,myrtleTree33\/Arduino,danielchalef\/Arduino,NeuralSpaz\/Arduino,toddtreece\/esp8266-Arduino,paulmand3l\/Arduino,zenmanenergy\/Arduino,myrtleTree33\/Arduino,leftbrainstrain\/Arduino-ESP8266,mattvenn\/Arduino,weera00\/Arduino,mangelajo\/Arduino,jomolinare\/Arduino,Cloudino\/Cloudino-Arduino-IDE,paulo-raca\/ESP8266-Arduino,spapadim\/Arduino,mateuszdw\/Arduino,spapadim\/Arduino,jomolinare\/Arduino,tannewt\/Arduino,nkolban\/Arduino,noahchense\/Arduino-1,raimohanska\/Arduino,raimohanska\/Arduino,noahchense\/Arduino-1,plinioseniore\/Arduino,Cloudino\/Cloudino-Arduino-IDE,mangelajo\/Arduino,mboufos\/esp8266-Arduino,danielchalef\/Arduino,fungxu\/Arduino,leftbrainstrain\/Arduino-ESP8266,radut\/Arduino,EmuxEvans\/Arduino,benwolfe\/esp8266-Arduino,piersoft\/esp8266-Arduino,mc-hamster\/esp8266-Arduino,shiitakeo\/Arduino,weera00\/Arduino,shiitakeo\/Arduino,wdoganowski\/Arduino,myrtleTree33\/Arduino,piersoft\/esp8266-Arduino,mangelajo\/Arduino,nkolban\/Arduino,weera00\/Arduino,NeuralSpaz\/Arduino,wdoganowski\/Arduino,jomolinare\/Arduino,jomolinare\/Arduino,toddtreece\/esp8266-Arduino,mateuszdw\/Arduino,drpjk\/Arduino,leftbrainstrain\/Arduino-ESP8266,zenmanenergy\/Arduino,mangelajo\/Arduino,myrtleTree33\/Arduino,benwolfe\/esp8266-Arduino,plaintea\/esp8266-Arduino,tannewt\/Arduino,plaintea\/esp8266-Arduino,benwolfe\/esp8266-Arduino,leftbrainstrain\/Arduino-ESP8266,nkolban\/Arduino,piersoft\/esp8266-Arduino,drpjk\/Arduino,SmartArduino\/Arduino-1,paulmand3l\/Arduino,ogahara\/Arduino,adafruit\/ESP8266-Arduino,NeuralSpaz\/Arduino,koltegirish\/Arduino,danielchalef\/Arduino,mateuszdw\/Arduino,adafruit\/ESP8266-Arduino,shiitakeo\/Arduino,ssvs111\/Arduino,koltegirish\/Arduino,smily77\/Arduino,drpjk\/Arduino,ssvs111\/Arduino,EmuxEvans\/Arduino,Cloudino\/Arduino,andrealmeidadomingues\/Arduino,EmuxEvans\/Arduino,mboufos\/esp8266-Arduino,wdoganowski\/Arduino,raimohanska\/Arduino,EmuxEvans\/Arduino,plinioseniore\/Arduino,tannewt\/Arduino,mateuszdw\/Arduino,plinioseniore\/Arduino,weera00\/Arduino,ssvs111\/Arduino,leftbrainstrain\/Arduino-ESP8266,Alfredynho\/AgroSis,gonium\/Arduino,andrealmeidadomingues\/Arduino,leftbrainstrain\/Arduino-ESP8266,tannewt\/Arduino,raimohanska\/Arduino,ssvs111\/Arduino,smily77\/Arduino,nkolban\/Arduino,weera00\/Arduino,fungxu\/Arduino,Cloudino\/Arduino,mc-hamster\/esp8266-Arduino,probonopd\/Arduino,SmartArduino\/Arduino-1,smily77\/Arduino,danielchalef\/Arduino,andrealmeidadomingues\/Arduino,SmartArduino\/Arduino-1,ogahara\/Arduino,sanyaade-iot\/Arduino-1,spapadim\/Arduino,eeijcea\/Arduino-1,toddtreece\/esp8266-Arduino,adafruit\/ESP8266-Arduino,paulmand3l\/Arduino,paulmand3l\/Arduino,noahchense\/Arduino-1,Cloudino\/Arduino,mattvenn\/Arduino,radut\/Arduino,tannewt\/Arduino,sanyaade-iot\/Arduino-1,spapadim\/Arduino,nkolban\/Arduino,plaintea\/esp8266-Arduino,mattvenn\/Arduino,eeijcea\/Arduino-1,aichi\/Arduino-2,Cloudino\/Arduino,koltegirish\/Arduino,andrealmeidadomingues\/Arduino,NeuralSpaz\/Arduino,zenmanenergy\/Arduino,drpjk\/Arduino,plaintea\/esp8266-Arduino,plinioseniore\/Arduino,ssvs111\/Arduino,mattvenn\/Arduino,koltegirish\/Arduino,mateuszdw\/Arduino,Alfredynho\/AgroSis,eeijcea\/Arduino-1,NeuralSpaz\/Arduino,Cloudino\/Arduino,SmartArduino\/Arduino-1,shiitakeo\/Arduino,EmuxEvans\/Arduino,fungxu\/Arduino,Protoneer\/Arduino,probonopd\/Arduino,Cloudino\/Cloudino-Arduino-IDE,myrtleTree33\/Arduino,wdoganowski\/Arduino,Protoneer\/Arduino,EmuxEvans\/Arduino,myrtleTree33\/Arduino,smily77\/Arduino,noahchense\/Arduino-1,Protoneer\/Arduino,radut\/Arduino,zenmanenergy\/Arduino,aichi\/Arduino-2,paulo-raca\/ESP8266-Arduino,EmuxEvans\/Arduino,ogahara\/Arduino,Protoneer\/Arduino,sanyaade-iot\/Arduino-1,NeuralSpaz\/Arduino,Alfredynho\/AgroSis,zenmanenergy\/Arduino,ogahara\/Arduino,wdoganowski\/Arduino,fungxu\/Arduino,zenmanenergy\/Arduino,sanyaade-iot\/Arduino-1,benwolfe\/esp8266-Arduino,radut\/Arduino,eeijcea\/Arduino-1,paulo-raca\/ESP8266-Arduino,Cloudino\/Cloudino-Arduino-IDE,adafruit\/ESP8266-Arduino,plinioseniore\/Arduino,noahchense\/Arduino-1,gonium\/Arduino,zenmanenergy\/Arduino,nkolban\/Arduino,radut\/Arduino,aichi\/Arduino-2,fungxu\/Arduino,mateuszdw\/Arduino,smily77\/Arduino,mangelajo\/Arduino,andrealmeidadomingues\/Arduino,mangelajo\/Arduino,ssvs111\/Arduino,probonopd\/Arduino,mboufos\/esp8266-Arduino,adafruit\/ESP8266-Arduino,Protoneer\/Arduino,paulo-raca\/ESP8266-Arduino,eeijcea\/Arduino-1,ssvs111\/Arduino,mc-hamster\/esp8266-Arduino,Protoneer\/Arduino,koltegirish\/Arduino,jomolinare\/Arduino,tannewt\/Arduino,gonium\/Arduino,shiitakeo\/Arduino,paulmand3l\/Arduino,SmartArduino\/Arduino-1,SmartArduino\/Arduino-1,radut\/Arduino,Alfredynho\/AgroSis,Alfredynho\/AgroSis,spapadim\/Arduino,paulmand3l\/Arduino,mateuszdw\/Arduino,shiitakeo\/Arduino,Protoneer\/Arduino,mattvenn\/Arduino,raimohanska\/Arduino,mboufos\/esp8266-Arduino,nkolban\/Arduino,mangelajo\/Arduino,gonium\/Arduino,mattvenn\/Arduino,wdoganowski\/Arduino,piersoft\/esp8266-Arduino,adafruit\/ESP8266-Arduino,shiitakeo\/Arduino,noahchense\/Arduino-1,andrealmeidadomingues\/Arduino,jomolinare\/Arduino,Alfredynho\/AgroSis,wdoganowski\/Arduino,ogahara\/Arduino,raimohanska\/Arduino,plinioseniore\/Arduino,adafruit\/ESP8266-Arduino,sanyaade-iot\/Arduino-1,spapadim\/Arduino,aichi\/Arduino-2,fungxu\/Arduino,ogahara\/Arduino,paulmand3l\/Arduino,paulo-raca\/ESP8266-Arduino,NeuralSpaz\/Arduino,spapadim\/Arduino,Cloudino\/Cloudino-Arduino-IDE,weera00\/Arduino,leftbrainstrain\/Arduino-ESP8266,gonium\/Arduino,weera00\/Arduino,Cloudino\/Cloudino-Arduino-IDE,paulo-raca\/ESP8266-Arduino,Cloudino\/Arduino,danielchalef\/Arduino,probonopd\/Arduino,drpjk\/Arduino,Alfredynho\/AgroSis,probonopd\/Arduino,aichi\/Arduino-2,sanyaade-iot\/Arduino-1,paulo-raca\/ESP8266-Arduino,koltegirish\/Arduino,mboufos\/esp8266-Arduino,ogahara\/Arduino,andrealmeidadomingues\/Arduino,jomolinare\/Arduino,drpjk\/Arduino,noahchense\/Arduino-1,danielchalef\/Arduino,danielchalef\/Arduino,fungxu\/Arduino,benwolfe\/esp8266-Arduino,radut\/Arduino,eeijcea\/Arduino-1,smily77\/Arduino,SmartArduino\/Arduino-1,raimohanska\/Arduino,aichi\/Arduino-2,plaintea\/esp8266-Arduino","old_file":"hardware\/tools\/esp8266\/sdk\/ld\/eagle.app.v6.ld","new_file":"hardware\/tools\/esp8266\/sdk\/ld\/eagle.app.v6.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x8000\n  irom0_0_seg :                       \torg = 0x40240000, len = 0x32000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n\t*libm.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x8000\n  irom0_0_seg :                       \torg = 0x40240000, len = 0x32000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"b1c5169ff176e4e15e65263c2e4c64570fb8571f","subject":"\u62d2\u7edd\u628a\u4e00\u6574\u884c\u6d6a\u8d39\u5728\u5de6\u5927\u62ec\u53f7\u4e0a","message":"\u62d2\u7edd\u628a\u4e00\u6574\u884c\u6d6a\u8d39\u5728\u5de6\u5927\u62ec\u53f7\u4e0a\n","repos":"IcebergOS\/frogimine,satgo1546\/frogimine,IcebergOS\/Cryst,IcebergOS\/frogimine,satgo1546\/frogimine","old_file":"linker.ld","new_file":"linker.ld","new_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS {\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 1M;\n\n\t\/* First put the multiboot header, as it is required to be put very early\n\t   early in the image or the bootloader won't recognize the file format.\n\t   Next we'll put the .text section. *\/\n\t.text BLOCK(4K) : ALIGN(4K) {\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K) {\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K) {\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K) {\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t}\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","old_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 1M;\n\n\t\/* First put the multiboot header, as it is required to be put very early\n\t   early in the image or the bootloader won't recognize the file format.\n\t   Next we'll put the .text section. *\/\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t}\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"187b5fb88879b514e95f57fac092987a6f9e36a3","subject":"ld: Remove unused .data sections at link time","message":"ld: Remove unused .data sections at link time\n\nReduces static RAM, code size.\n","repos":"shukyisme\/esp-idf-kwik,empoweredhomes\/esp-idf,armada-ai\/esp-idf,armada-ai\/esp-idf,MIhanguangyi\/esp-idf,ajs124\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf,MIhanguangyi\/esp-idf,espressif\/esp-idf,nineisk\/esp-idf,mashaoze\/esp-idf,jaracil\/esp-idf,nineisk\/esp-idf,jaracil\/esp-idf,Hermiedapwdrman\/esp-idf,dschaefer\/esp-idf,Hermiedapwdrman\/esp-idf,empoweredhomes\/esp-idf,dschaefer\/esp-idf,shukyisme\/esp-idf-kwik,nineisk\/esp-idf,www220\/esp-idf,dschaefer\/esp-idf,jaracil\/esp-idf,empoweredhomes\/esp-idf,espressif\/esp-idf,dschaefer\/esp-idf,empoweredhomes\/esp-idf,mashaoze\/esp-idf,shukyisme\/esp-idf-kwik,MIhanguangyi\/esp-idf,mashaoze\/esp-idf,jaracil\/esp-idf,ajs124\/esp-idf,MIhanguangyi\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,ajs124\/esp-idf,Hermiedapwdrman\/esp-idf,www220\/esp-idf,Hermiedapwdrman\/esp-idf,espressif\/esp-idf,armada-ai\/esp-idf,MIhanguangyi\/esp-idf,ajs124\/esp-idf,mashaoze\/esp-idf,empoweredhomes\/esp-idf,www220\/esp-idf,shukyisme\/esp-idf-kwik,espressif\/esp-idf,nineisk\/esp-idf,Hermiedapwdrman\/esp-idf,shukyisme\/esp-idf-kwik,dschaefer\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libesp32.a:heap_alloc_caps.o(.literal .text .literal.* .text.*)\n    *libapp_trace.a:(.literal .text .literal.* .text.*)\n    *libxtensa-debug-module.a:eri.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libesp32.a:heap_alloc_caps.o(.literal .text .literal.* .text.*)\n    *libapp_trace.a:(.literal .text .literal.* .text.*)\n    *libxtensa-debug-module.a:eri.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6b97fa838235b5f19a1baff9a94409a189dacc2d","subject":"stm32f1x_cl: Fix stm32f107 linker script","message":"stm32f1x_cl: Fix stm32f107 linker script\n\nThis is a critical fix which adds inclusion of the entire data\/bss\nsection to the output ELF file.  Without it, the BSS section will not\nbe zeroed out\n","repos":"bluerover\/6lbr,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki,bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr","old_file":"cpu\/arm\/stm32f1x_cl\/STM32F107VCT.ld","new_file":"cpu\/arm\/stm32f1x_cl\/STM32F107VCT.ld","new_contents":"MEMORY\n{\n  CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256K\n  DATA (xrw) : ORIGIN = 0x20000000, LENGTH = 64K\n}\n\n\/* Section Definitions *\/\n\nEXTERN (vector_table)\nENTRY(reset_handler)\nSECTIONS\n{\n\n\/* Make sure the vector table is at address 0 *\/\n\n   .text : {\n   \t   *(.vectors)\n\t   *(.text*)\n\t   . = ALIGN(4);\n\t   *(.rodata*)\n\t   . = ALIGN(4);\n   } >CODE\n\n   . = ALIGN(4);\n   _etext = . ;\n   PROVIDE (etext = .);\n\n  .data :\n  {\n    _data = . ;\n    *(.data*)\n    . = ALIGN(4);\n    _edata = . ;\n    PROVIDE (_edata = .);\n  } >DATA AT >CODE\n  _data_loadaddr = LOADADDR(.data);\n\n\/* .bss section which is used for uninitialized data *\/\n\n  .bss :\n  {\n    __bss_start = . ;\n    __bss_start__ = . ;\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    _ebss = . ;\n  } >DATA\n  . = ALIGN(4);\n\n   _end = .;\n  PROVIDE (_end = .);\n}\nPROVIDE(_stack = ORIGIN(DATA) + LENGTH(DATA));\n","old_contents":"MEMORY\n{\n  CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256K\n  DATA (xrw) : ORIGIN = 0x20000000, LENGTH = 64K\n}\n\n\/* Section Definitions *\/\n\nEXTERN (vector_table)\nENTRY(reset_handler)\nSECTIONS\n{\n\n\/* Make sure the vector table is at address 0 *\/\n\n   .text : {\n   \t   *(.vectors)\n\t   *(.text*)\n\t   . = ALIGN(4);\n\t   *(.rodata*)\n\t   . = ALIGN(4);\n   } >CODE\n\n   . = ALIGN(4);\n   _etext = . ;\n   PROVIDE (etext = .);\n\n  .data :\n  {\n    _data = . ;\n    *(.data)\n    . = ALIGN(4);\n    _edata = . ;\n    PROVIDE (_edata = .);\n  } >DATA AT >CODE\n  _data_loadaddr = LOADADDR(.data);\n\n\/* .bss section which is used for uninitialized data *\/\n\n  .bss :\n  {\n    __bss_start = . ;\n    __bss_start__ = . ;\n    *(.bss)\n    *(COMMON)\n    . = ALIGN(4);\n    _ebss = . ;\n  } >DATA\n  . = ALIGN(4);\n\n   _end = .;\n  PROVIDE (_end = .);\n}\nPROVIDE(_stack = ORIGIN(DATA) + LENGTH(DATA));\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"b4403311cf2eaf42eb2d882d1d4b9d9fcc3ad18f","subject":"modify flash_ld for c++","message":"modify flash_ld for c++\n\nWithout 'KEEP' expression,\nC++ features don't work out.\n\nSigned-off-by: jaesick.shin <0c15f419be0b798d814c9433c3dc372b1d1c1c73@samsung.com>\n","repos":"chanijjani\/TizenRT,jeongarmy\/TizenRT,junmin-kim\/TizenRT,JeonginKim\/TizenRT,junmin-kim\/TizenRT,pillip8282\/TizenRT,jeongarmy\/TizenRT,jsdosa\/TizenRT,JeonginKim\/TizenRT,Samsung\/TizenRT,HONGCHAEHEE\/TizenRT,jeongarmy\/TizenRT,davidfather\/TizenRT,jeongchanKim\/TizenRT,jsdosa\/TizenRT,jeongchanKim\/TizenRT,lokeshbv\/TizenRT,jsdosa\/TizenRT,an4967\/TizenRT,an4967\/TizenRT,Samsung\/TizenRT,HONGCHAEHEE\/TizenRT,an4967\/TizenRT,jeongchanKim\/TizenRT,HONGCHAEHEE\/TizenRT,junmin-kim\/TizenRT,lokeshbv\/TizenRT,jsdosa\/TizenRT,Samsung\/TizenRT,btheosam\/TizenRT,sunghan-chang\/TizenRT,chanijjani\/TizenRT,junmin-kim\/TizenRT,jeongchanKim\/TizenRT,junmin-kim\/TizenRT,chanijjani\/TizenRT,chanijjani\/TizenRT,JeonginKim\/TizenRT,an4967\/TizenRT,btheosam\/TizenRT,davidfather\/TizenRT,btheosam\/TizenRT,jsdosa\/TizenRT,sunghan-chang\/TizenRT,jeongchanKim\/TizenRT,lokeshbv\/TizenRT,btheosam\/TizenRT,sunghan-chang\/TizenRT,pillip8282\/TizenRT,pillip8282\/TizenRT,sunghan-chang\/TizenRT,pillip8282\/TizenRT,HONGCHAEHEE\/TizenRT,Samsung\/TizenRT,pillip8282\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT,JeonginKim\/TizenRT,jeongarmy\/TizenRT,HONGCHAEHEE\/TizenRT,jeongarmy\/TizenRT,davidfather\/TizenRT,jeongchanKim\/TizenRT,pillip8282\/TizenRT,chanijjani\/TizenRT,davidfather\/TizenRT,btheosam\/TizenRT,Samsung\/TizenRT,JeonginKim\/TizenRT,davidfather\/TizenRT,chanijjani\/TizenRT,sunghan-chang\/TizenRT,davidfather\/TizenRT,Samsung\/TizenRT,chanijjani\/TizenRT,btheosam\/TizenRT,jsdosa\/TizenRT,an4967\/TizenRT,jsdosa\/TizenRT,junmin-kim\/TizenRT,jeongarmy\/TizenRT,davidfather\/TizenRT,lokeshbv\/TizenRT,jeongchanKim\/TizenRT,junmin-kim\/TizenRT,an4967\/TizenRT,lokeshbv\/TizenRT,lokeshbv\/TizenRT,HONGCHAEHEE\/TizenRT,pillip8282\/TizenRT,sunghan-chang\/TizenRT,JeonginKim\/TizenRT,Samsung\/TizenRT,an4967\/TizenRT","old_file":"build\/configs\/artik055s\/scripts\/flash.ld","new_file":"build\/configs\/artik055s\/scripts\/flash.ld","new_contents":"\/****************************************************************************\n *\n * Copyright 2017 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * configs\/artik055s\/scripts\/flash.ld\n *\n *   Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *           Laurent Latil <laurent@latil.nom.fr>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nMEMORY\n{\n\tFLASH\t(rx)\t: ORIGIN = 0x040C8000, LENGTH = 2400K\n\tSRAM\t(rwx)\t: ORIGIN = 0x02023800, LENGTH = 946K\n}\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_stext)\nSECTIONS\n{\n\t.header : {\n\t\t_start = .;\n\t\tLONG((_end - _start) \/ 512);\n\t\tLONG(0);\n\t\tLONG(0x656d6264);\n\t\t. = ALIGN(0x20);\n\t} > FLASH =0x0\n\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > FLASH\n\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\tKEEP(*(.init_array .init_array.*))\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > SRAM AT > FLASH\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > SRAM\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.padding : {\n\t\t. = ALIGN(512);\n\t\t. = . + 1020;\n\t\tLONG(0);\n\t\t_end = .;\n\t} > FLASH =0x0\n}\n","old_contents":"\/****************************************************************************\n *\n * Copyright 2017 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * configs\/artik055s\/scripts\/flash.ld\n *\n *   Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *           Laurent Latil <laurent@latil.nom.fr>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nMEMORY\n{\n\tFLASH\t(rx)\t: ORIGIN = 0x040C8000, LENGTH = 2400K\n\tSRAM\t(rwx)\t: ORIGIN = 0x02023800, LENGTH = 946K\n}\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_stext)\nSECTIONS\n{\n\t.header : {\n\t\t_start = .;\n\t\tLONG((_end - _start) \/ 512);\n\t\tLONG(0);\n\t\tLONG(0x656d6264);\n\t\t. = ALIGN(0x20);\n\t} > FLASH =0x0\n\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > FLASH\n\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\t*(.init_array .init_array.*)\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > SRAM AT > FLASH\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > SRAM\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.padding : {\n\t\t. = ALIGN(512);\n\t\t. = . + 1020;\n\t\tLONG(0);\n\t\t_end = .;\n\t} > FLASH =0x0\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"67f1ee53439c10876ed23c691b1c68e0a71869f6","subject":"Resolve including directory issue in GCC linker script for Ameba","message":"Resolve including directory issue in GCC linker script for Ameba\n\nShould not make assumption of specific directory when include .h from\nlinker script\n","repos":"mbedmicro\/mbed,mazimkhan\/mbed-os,HeadsUpDisplayInc\/mbed,andcor02\/mbed-os,nRFMesh\/mbed-os,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,Archcady\/mbed-os,betzw\/mbed-os,mazimkhan\/mbed-os,catiedev\/mbed-os,catiedev\/mbed-os,kjbracey-arm\/mbed,CalSol\/mbed,nRFMesh\/mbed-os,ryankurte\/mbed-os,c1728p9\/mbed-os,catiedev\/mbed-os,catiedev\/mbed-os,svogl\/mbed-os,andcor02\/mbed-os,infinnovation\/mbed-os,YarivCol\/mbed-os,nRFMesh\/mbed-os,YarivCol\/mbed-os,CalSol\/mbed,CalSol\/mbed,mazimkhan\/mbed-os,andcor02\/mbed-os,YarivCol\/mbed-os,ryankurte\/mbed-os,karsev\/mbed-os,karsev\/mbed-os,mbedmicro\/mbed,betzw\/mbed-os,CalSol\/mbed,betzw\/mbed-os,karsev\/mbed-os,karsev\/mbed-os,Archcady\/mbed-os,YarivCol\/mbed-os,ryankurte\/mbed-os,svogl\/mbed-os,HeadsUpDisplayInc\/mbed,c1728p9\/mbed-os,infinnovation\/mbed-os,andcor02\/mbed-os,betzw\/mbed-os,YarivCol\/mbed-os,betzw\/mbed-os,catiedev\/mbed-os,betzw\/mbed-os,ryankurte\/mbed-os,kjbracey-arm\/mbed,Archcady\/mbed-os,c1728p9\/mbed-os,Archcady\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os,infinnovation\/mbed-os,nRFMesh\/mbed-os,mazimkhan\/mbed-os,CalSol\/mbed,mazimkhan\/mbed-os,c1728p9\/mbed-os,svogl\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,karsev\/mbed-os,svogl\/mbed-os,Archcady\/mbed-os,CalSol\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,mazimkhan\/mbed-os,nRFMesh\/mbed-os,Archcady\/mbed-os,infinnovation\/mbed-os,karsev\/mbed-os,nRFMesh\/mbed-os,catiedev\/mbed-os,HeadsUpDisplayInc\/mbed,mbedmicro\/mbed,svogl\/mbed-os,ryankurte\/mbed-os,kjbracey-arm\/mbed,ryankurte\/mbed-os,HeadsUpDisplayInc\/mbed,svogl\/mbed-os,infinnovation\/mbed-os,infinnovation\/mbed-os,c1728p9\/mbed-os,YarivCol\/mbed-os","old_file":"targets\/TARGET_Realtek\/TARGET_AMEBA\/TARGET_RTL8195A\/device\/TOOLCHAIN_GCC_ARM\/rtl8195a.ld","new_file":"targets\/TARGET_Realtek\/TARGET_AMEBA\/TARGET_RTL8195A\/device\/TOOLCHAIN_GCC_ARM\/rtl8195a.ld","new_contents":"\/*\n * Copyright (c) 2013-2016 Realtek Semiconductor Corp.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nINCLUDE \"rtl8195a_rom.h\"\n\/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).\n   But we can put .data\/.bss of Image2 in this region *\/\nMEMORY\n{\n  TCM (rwx)        : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  DATA_RAM (rwx)   : ORIGIN = 0x10002100, LENGTH = 0x10007000 - 0x10002100\n  SRAM1 (rwx)      : ORIGIN = 0x10007000, LENGTH = 0x10070000 - 0x10007000\n  SRAM2 (rwx)      : ORIGIN = 0x30000000, LENGTH = 2M\n}\n\n\/* Stack sizes: *\/\nStackSize = 0x1000;\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .image2.table :\n    {\n        KEEP(*(SORT(.image2.ram.data*)))\n        KEEP(*(.image2.validate.rodata*))\n    } > SRAM2\n\n    .text.sram1 :\n    {\n        . = ALIGN(4);\n        *rtl8195a_crypto.o (.text* .rodata*)\n        *mbedtls*.o (.text* .rodata*)\n        *libc.a: (.text* .rodata*)\n        *Ticker.o (.text*)\n        *Timeout.o (.text*)\n        *TimerEvent.o (.text*)\n        *mbed_ticker_api.o (.text*)\n        *mbed_critical.o (.text*)\n        *us_ticker.o (.text*)\n        \n        *lib_peripheral_mbed_gcc.a: (.text*)\n        \n    } > SRAM1\n\n    .text.sram2 :\n    {\n        . = ALIGN(4);\n        *(.mon.ram.text*)\n        *(.hal.flash.text*)\n        *(.hal.sdrc.text*)\n        *(.hal.gpio.text*)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > SRAM2\n    __etext = .;\n\n    __data_start__ = .;\n\n    .data.sram1 :\n    {\n        . = ALIGN(4);\n        __sram_data_start__ = .;\n        *rtl8195a_crypto*.o (.data*)\n        *mbedtls*.o (.data*)\n        __sram_data_end__ = .;\n    } > SRAM1\n\n    .data.sram2 :\n    {\n        __sdram_data_start__ = .;\n        *(vtable)\n        *(.data*)\n        *(.sdram.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n\n        __sdram_data_end__ = .;\n        \/* All data end *\/\n    } > SRAM2\n    __data_end__ = .;\n    __image2_end__ = .;\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > SRAM2\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > SRAM2\n    __exidx_end = .;\n\n    .bss.sram1 (NOLOAD) :\n    {\n        __bss_sram_start__ = .;\n        *rtl8195a_crypto.o (.bss* COMMON)\n        *mbedtls*.o (.bss* COMMON)\n        *(.bss.thread_stack_main)\n        __bss_sram_end__ = .;\n    } > SRAM1\n\n    .bss.sram2 (NOLOAD) :\n    {\n        __bss_start__ = .;\n        __bss_dram_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        *(.bdsram.data*)\n        __bss_dram_end__ = .;\n        __bss_end__ = .;\n    } > SRAM2\n\n    .bf_data :\n    {\n        __buffer_data_start__ = .;\n        *(.bfsram.data*)\n        __buffer_data_end__ = .;\n    } > SRAM2\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n    . = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;\n        __HeapLimit = .;\n    } > SRAM1\n    \n    .TCM_overlay :\n    {\n        __bss_dtcm_start__ = .;\n        *lwip_mem.o (.bss*)\n        *lwip_memp.o (.bss*)\n        *(.tcm.heap*)\n        __bss_dtcm_end__ = .;\n    } > TCM\n    \n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack)\n    . += StackSize - (. - __StackLimit);\n    } > SRAM1\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM exceeds ram limit\")\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2016 Realtek Semiconductor Corp.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nINCLUDE \"mbed-os\/targets\/TARGET_Realtek\/TARGET_AMEBA\/TARGET_RTL8195A\/device\/TOOLCHAIN_GCC_ARM\/rtl8195a_rom.h\"\n\/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).\n   But we can put .data\/.bss of Image2 in this region *\/\nMEMORY\n{\n  TCM (rwx)        : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  DATA_RAM (rwx)   : ORIGIN = 0x10002100, LENGTH = 0x10007000 - 0x10002100\n  SRAM1 (rwx)      : ORIGIN = 0x10007000, LENGTH = 0x10070000 - 0x10007000\n  SRAM2 (rwx)      : ORIGIN = 0x30000000, LENGTH = 2M\n}\n\n\/* Stack sizes: *\/\nStackSize = 0x1000;\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .image2.table :\n    {\n        KEEP(*(SORT(.image2.ram.data*)))\n        KEEP(*(.image2.validate.rodata*))\n    } > SRAM2\n\n    .text.sram1 :\n    {\n        . = ALIGN(4);\n        *rtl8195a_crypto.o (.text* .rodata*)\n        *mbedtls*.o (.text* .rodata*)\n        *libc.a: (.text* .rodata*)\n        *Ticker.o (.text*)\n        *Timeout.o (.text*)\n        *TimerEvent.o (.text*)\n        *mbed_ticker_api.o (.text*)\n        *mbed_critical.o (.text*)\n        *us_ticker.o (.text*)\n        \n        *lib_peripheral_mbed_gcc.a: (.text*)\n        \n    } > SRAM1\n\n    .text.sram2 :\n    {\n        . = ALIGN(4);\n        *(.mon.ram.text*)\n        *(.hal.flash.text*)\n        *(.hal.sdrc.text*)\n        *(.hal.gpio.text*)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > SRAM2\n    __etext = .;\n\n    __data_start__ = .;\n\n    .data.sram1 :\n    {\n        . = ALIGN(4);\n        __sram_data_start__ = .;\n        *rtl8195a_crypto*.o (.data*)\n        *mbedtls*.o (.data*)\n        __sram_data_end__ = .;\n    } > SRAM1\n\n    .data.sram2 :\n    {\n        __sdram_data_start__ = .;\n        *(vtable)\n        *(.data*)\n        *(.sdram.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n\n        __sdram_data_end__ = .;\n        \/* All data end *\/\n    } > SRAM2\n    __data_end__ = .;\n    __image2_end__ = .;\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > SRAM2\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > SRAM2\n    __exidx_end = .;\n\n    .bss.sram1 (NOLOAD) :\n    {\n        __bss_sram_start__ = .;\n        *rtl8195a_crypto.o (.bss* COMMON)\n        *mbedtls*.o (.bss* COMMON)\n        *(.bss.thread_stack_main)\n        __bss_sram_end__ = .;\n    } > SRAM1\n\n    .bss.sram2 (NOLOAD) :\n    {\n        __bss_start__ = .;\n        __bss_dram_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        *(.bdsram.data*)\n        __bss_dram_end__ = .;\n        __bss_end__ = .;\n    } > SRAM2\n\n    .bf_data :\n    {\n        __buffer_data_start__ = .;\n        *(.bfsram.data*)\n        __buffer_data_end__ = .;\n    } > SRAM2\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n    . = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;\n        __HeapLimit = .;\n    } > SRAM1\n    \n    .TCM_overlay :\n    {\n        __bss_dtcm_start__ = .;\n        *lwip_mem.o (.bss*)\n        *lwip_memp.o (.bss*)\n        *(.tcm.heap*)\n        __bss_dtcm_end__ = .;\n    } > TCM\n    \n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack)\n    . += StackSize - (. - __StackLimit);\n    } > SRAM1\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM exceeds ram limit\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a0d5f8efd71e55fc7ebe272e2a3d62eace2f5e5d","subject":"add .data and .bss segments to picosoc","message":"add .data and .bss segments to picosoc\n\nadded .data and .bss segments to picosoc firmware linker script so that static variables may be used.","repos":"cliffordwolf\/picorv32,cliffordwolf\/picorv32,cliffordwolf\/picorv32,cliffordwolf\/picorv32","old_file":"picosoc\/sections.lds","new_file":"picosoc\/sections.lds","new_contents":"SECTIONS {\n\t.memory : {\n\t\tsram = 0;\n\t\t*(.data);\n\t\t*(.bss);\n\t\t. = 0x100000;\n\t\tstart*(.text);\n\t\t*(.text);\n\t\t*(*);\n\t}\n}\n","old_contents":"SECTIONS {\n\t.memory : {\n\t\tsram = 0;\n\t\t. = 0x100000;\n\t\tstart*(.text);\n\t\t*(.text);\n\t\t*(*);\n\t}\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"fc2623e8c27ea5c79772bf907d597b46f0b317a7","subject":"Do not version overridden symbols.","message":"Do not version overridden symbols.\n\nVersioning overridden symbols kills the ability to LD_PRELOAD the\nlibrary. Oops!\n\nSigned-off-by: Gergely Nagy <6780fac3b38619ac20422286e4110a70dbba2203@balabit.hu>\n","repos":"deirf\/libumberlog","old_file":"lib\/libcee-syslog.ld","new_file":"lib\/libcee-syslog.ld","new_contents":"LIBCEE_SYSLOG_0.1.0 {\n\tglobal:\n        # Our own symbols\n          cee_format;\n          cee_vformat;\n          cee_syslog;\n          cee_vsyslog;\n          cee_legacy_syslog;\n          cee_legacy_vsyslog;\n          cee_openlog;\n          cee_setlogmask;\n\n\tlocal:\n        # Inherited from elsewhere, but should not be exported\n          facilitynames;\n          prioritynames;\n};\n","old_contents":"LIBCEE_SYSLOG_0.1.0 {\n\tglobal:\n        # Our own symbols\n          cee_format;\n          cee_vformat;\n          cee_syslog;\n          cee_vsyslog;\n          cee_legacy_syslog;\n          cee_legacy_vsyslog;\n          cee_openlog;\n          cee_setlogmask;\n        # Overrides\n          syslog;\n          vsyslog;\n          openlog;\n          setlogmask;\n\n\tlocal:\n        # Inherited from elsewhere, but should not be exported\n          facilitynames;\n          prioritynames;\n};\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"9b677e2ed7a82d4ec814b04a03362aa445d1ec14","subject":"Move arduino library into OCRAM","message":"Move arduino library into OCRAM\n\nCurrently, Arduino sketches are right at the limit for m_text. Move the\narduino library (importantly, the bundled one) to ocram.\n\nChange-Id: I677817901fb3d94508e931319016e9bce76b3a6c\nGitOrigin-RevId: 5942f7ba5ca1ef8b0b7638d6afa86973c2d21aac\n","repos":"google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro","old_file":"libs\/nxp\/rt1176-sdk\/MIMXRT1176xxxxx_cm7_ram.ld","new_file":"libs\/nxp\/rt1176-sdk\/MIMXRT1176xxxxx_cm7_ram.ld","new_contents":"\/*\r\n** ###################################################################\r\n**     Processors:          MIMXRT1176AVM8A_cm7\r\n**                          MIMXRT1176CVM8A_cm7\r\n**                          MIMXRT1176DVMAA_cm7\r\n**\r\n**     Compiler:            GNU C Compiler\r\n**     Reference manual:    IMXRT1170RM, Rev E, 12\/2019\r\n**     Version:             rev. 0.1, 2018-03-05\r\n**     Build:               b200828\r\n**\r\n**     Abstract:\r\n**         Linker file for the GNU C Compiler\r\n**\r\n**     Copyright 2016 Freescale Semiconductor, Inc.\r\n**     Copyright 2016-2020 NXP\r\n**     All rights reserved.\r\n**\r\n**     SPDX-License-Identifier: BSD-3-Clause\r\n**\r\n**     http:                 www.nxp.com\r\n**     mail:                 support@nxp.com\r\n**\r\n** ###################################################################\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x01000000;\r\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\r\nRPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;\r\n\r\n\/*\r\n * Valid memory regions:\r\n * 0x00000000 - 0x0003FFFF (256KB)\r\n * 0x20000000 - 0x2003FFFF (256KB)\r\n * 0x20240000 - 0x202BFFFF (512KB)\r\n * 0x202C0000 - 0x2033FFFF (512KB)\r\n *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\n  m_interrupts          (RX)  : ORIGIN = 0x00000800, LENGTH = 0x00000400\r\n  m_text                (RX)  : ORIGIN = 0x00000c00, LENGTH = 0x0003F400\r\n  m_stack               (RX)  : ORIGIN = 0x20000000, LENGTH = STACK_SIZE\r\n  m_data                (RW)  : ORIGIN = 0x20000000 + STACK_SIZE, LENGTH = 0x00040000 - STACK_SIZE\r\n  m_ocram               (RX)  : ORIGIN = 0x20240000, LENGTH = 0x00080000\r\n  rpmsg_sh_mem          (RW)  : ORIGIN = 0x202C0000, LENGTH = RPMSG_SHMEM_SIZE\r\n  m_heap                (RW)  : ORIGIN = 0x80000000, LENGTH = HEAP_SIZE\r\n  m_sdram               (RX)  : ORIGIN = 0x80000000 + HEAP_SIZE, LENGTH = 0x03000000 - HEAP_SIZE\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  __NCACHE_REGION_START = ORIGIN(rpmsg_sh_mem);\r\n  __NCACHE_REGION_SIZE  = LENGTH(rpmsg_sh_mem);\r\n\r\n  \/* NOINIT section for rpmsg_sh_mem *\/\r\n  .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)\r\n  {\r\n     __RPMSG_SH_MEM_START__ = .;\r\n     *(.noinit.$rpmsg_sh_mem*)\r\n     . = ALIGN(4) ;\r\n     __RPMSG_SH_MEM_END__ = .;\r\n  } > rpmsg_sh_mem\r\n\r\n  \/* section for storing the secondary core image *\/\r\n  .core1_code :\r\n  {\r\n     . = ALIGN(4) ;\r\n    KEEP (*(.core1_code))\r\n     *(.core1_code*)\r\n     . = ALIGN(4) ;\r\n  } > m_sdram\r\n\r\n  \/* The startup code goes first into internal RAM *\/\r\n  .interrupts :\r\n  {\r\n    __VECTOR_TABLE = .;\r\n    __Vectors = .;\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))     \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } > m_interrupts\r\n\r\n  .curl :\r\n  {\r\n     . = ALIGN(4);\r\n     __curl_start = .;\r\n     *liblibs_curl.a:*(.text .text*)\r\n     *liblibs_curl.a:*(.data .data*)\r\n     *liblibs_curl.a:*(.rodata .rodata*)\r\n     __curl_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .mbedtls :\r\n  {\r\n     . = ALIGN(4);\r\n     __mbedtls_start = .;\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.rodata .rodata*)\r\n     __mbedtls_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .lwip :\r\n  {\r\n     . = ALIGN(4);\r\n     __lwip_start = .;\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.rodata .rodata*)\r\n     __lwip_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .wiced :\r\n  {\r\n     . = ALIGN(4);\r\n     __wiced_start = .;\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.rodata .rodata*)\r\n     *libwicedble.a:*(.text .text*)\r\n     *libwicedble.a:*(.data .data*)\r\n     *libwicedble.a:*(.rodata .rodata*)\r\n     __wiced_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .tensorflow :\r\n  {\r\n     . = ALIGN(4);\r\n     __tensorflow_start = .;\r\n     *liblibs_tensorflow-m7.a:*(.text .text*)\r\n     *liblibs_tensorflow-m7.a:*(.data .data*)\r\n     *liblibs_tensorflow-m7.a:*(.rodata .rodata*)\r\n     __tensorflow_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .arduino :\r\n  {\r\n     . = ALIGN(4);\r\n     __arduino_start = .;\r\n     *liblibs_arduino.a:*(.text .text*)\r\n     *liblibs_arduino.a:*(.data .data*)\r\n     *liblibs_arduino.a:*(.rodata .rodata*)\r\n     __arduino_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .arduino_bundled :\r\n  {\r\n     . = ALIGN(4);\r\n     __arduino_bundled_start = .;\r\n     *liblibs_arduino_bundled.a:*(.text .text*)\r\n     *liblibs_arduino_bundled.a:*(.data .data*)\r\n     *liblibs_arduino_bundled.a:*(.rodata .rodata*)\r\n     __arduino_bundled_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  \/* The program code and other data goes into internal RAM *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)                 \/* .text sections (code) *\/\r\n    *(.text*)                \/* .text* sections (code) *\/\r\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\r\n    KEEP(*(.rodata.debug))\r\n    *(.glue_7)               \/* glue arm to thumb code *\/\r\n    *(.glue_7t)              \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._settings_handler_static :\r\n  {\r\n    . = ALIGN(4);\r\n    _settings_handler_static_list_start = .;\r\n    KEEP(*(SORT(._settings_handler_static.static.*)))\r\n    _settings_handler_static_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._bt_gatt_service_static :\r\n  {\r\n    . = ALIGN(4);\r\n    _bt_gatt_service_static_list_start = .;\r\n    KEEP(*(SORT(._bt_gatt_service_static.static.*)))\r\n    _bt_gatt_service_static_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._bt_l2cap_fixed_chan :\r\n  {\r\n    . = ALIGN(4);\r\n    _bt_l2cap_fixed_chan_list_start = .;\r\n    KEEP(*(SORT(._bt_l2cap_fixed_chan.static.*)))\r\n    _bt_l2cap_fixed_chan_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > m_text\r\n\r\n  .ARM :\r\n  {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } > m_text\r\n\r\n .ctors :\r\n  {\r\n    __CTOR_LIST__ = .;\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       from the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    __CTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .dtors :\r\n  {\r\n    __DTOR_LIST__ = .;\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    __DTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .preinit_array :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } > m_text\r\n\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } > m_text\r\n\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } > m_text\r\n\r\n  __etext = .;    \/* define a global symbol at end of code *\/\r\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\r\n\r\n  __VECTOR_RAM = ORIGIN(m_interrupts);\r\n  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;\r\n\r\n  .data : AT(__DATA_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __DATA_RAM = .;\r\n    __data_start__ = .;      \/* create a global symbol at data start *\/\r\n    *(m_usb_dma_init_data)\r\n    *(.data)                 \/* .data sections *\/\r\n    *(.data*)                \/* .data* sections *\/\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    _net_buf_pool_list = .;\r\n    KEEP(*(SORT(._net_buf_pool*)))\r\n    . = ALIGN(4);\r\n    __data_end__ = .;        \/* define a global symbol at data end *\/\r\n  } > m_data\r\n  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);\r\n  .ncache.init : AT(__NDATA_ROM)\r\n  {\r\n    __noncachedata_start__ = .;   \/* create a global symbol at ncache data start *\/\r\n    *(NonCacheable.init)\r\n    . = ALIGN(4);\r\n    __noncachedata_init_end__ = .;   \/* create a global symbol at initialized ncache data end *\/\r\n  } > m_data\r\n  . = __noncachedata_init_end__;\r\n  .ncache :\r\n  {\r\n    *(NonCacheable)\r\n    . = ALIGN(4);\r\n    __noncachedata_end__ = .;     \/* define a global symbol at ncache data end *\/\r\n  } > m_data\r\n  __SDRAM_ROM = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);\r\n  .sdram_data : AT(__SDRAM_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_data_start__ = .;\r\n    KEEP(*(.sdram_data*))\r\n    . = ALIGN(4);\r\n    __sdram_data_end__ = .;\r\n  } > m_sdram\r\n\r\n  \/* Uninitialized data section *\/\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss section *\/\r\n    . = ALIGN(4);\r\n    __START_BSS = .;\r\n    __bss_start__ = .;\r\n    *(m_usb_dma_noninit_data)\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n    __END_BSS = .;\r\n  } > m_data\r\n  __DATA_END = __SDRAM_ROM;\r\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\r\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\r\n\r\n  .sdram_bss (NOLOAD) :\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_bss_start__ = .;\r\n    *(.sdram_bss*)\r\n    . = ALIGN(4);\r\n    __sdram_bss_end__ = .;\r\n  } > m_sdram\r\n\r\n  .heap :\r\n  {\r\n    . = ALIGN(8);\r\n    __end__ = .;\r\n    PROVIDE(end = .);\r\n    __HeapBase = .;\r\n    . += HEAP_SIZE;\r\n    __HeapLimit = .;\r\n    __heap_limit = .; \/* Add for _sbrk *\/\r\n  } > m_heap\r\n\r\n  .stack :\r\n  {\r\n    . = ALIGN(8);\r\n    . += STACK_SIZE;\r\n  } > m_stack\r\n\r\n  \/* Initializes stack on the end of block *\/\r\n  __StackTop   = ORIGIN(m_stack) + LENGTH(m_stack);\r\n  __StackLimit = __StackTop - STACK_SIZE;\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n\r\n","old_contents":"\/*\r\n** ###################################################################\r\n**     Processors:          MIMXRT1176AVM8A_cm7\r\n**                          MIMXRT1176CVM8A_cm7\r\n**                          MIMXRT1176DVMAA_cm7\r\n**\r\n**     Compiler:            GNU C Compiler\r\n**     Reference manual:    IMXRT1170RM, Rev E, 12\/2019\r\n**     Version:             rev. 0.1, 2018-03-05\r\n**     Build:               b200828\r\n**\r\n**     Abstract:\r\n**         Linker file for the GNU C Compiler\r\n**\r\n**     Copyright 2016 Freescale Semiconductor, Inc.\r\n**     Copyright 2016-2020 NXP\r\n**     All rights reserved.\r\n**\r\n**     SPDX-License-Identifier: BSD-3-Clause\r\n**\r\n**     http:                 www.nxp.com\r\n**     mail:                 support@nxp.com\r\n**\r\n** ###################################################################\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x01000000;\r\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\r\nRPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;\r\n\r\n\/*\r\n * Valid memory regions:\r\n * 0x00000000 - 0x0003FFFF (256KB)\r\n * 0x20000000 - 0x2003FFFF (256KB)\r\n * 0x20240000 - 0x202BFFFF (512KB)\r\n * 0x202C0000 - 0x2033FFFF (512KB)\r\n *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\n  m_interrupts          (RX)  : ORIGIN = 0x00000800, LENGTH = 0x00000400\r\n  m_text                (RX)  : ORIGIN = 0x00000c00, LENGTH = 0x0003F400\r\n  m_stack               (RX)  : ORIGIN = 0x20000000, LENGTH = STACK_SIZE\r\n  m_data                (RW)  : ORIGIN = 0x20000000 + STACK_SIZE, LENGTH = 0x00040000 - STACK_SIZE\r\n  m_ocram               (RX)  : ORIGIN = 0x20240000, LENGTH = 0x00080000\r\n  rpmsg_sh_mem          (RW)  : ORIGIN = 0x202C0000, LENGTH = RPMSG_SHMEM_SIZE\r\n  m_heap                (RW)  : ORIGIN = 0x80000000, LENGTH = HEAP_SIZE\r\n  m_sdram               (RX)  : ORIGIN = 0x80000000 + HEAP_SIZE, LENGTH = 0x03000000 - HEAP_SIZE\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  __NCACHE_REGION_START = ORIGIN(rpmsg_sh_mem);\r\n  __NCACHE_REGION_SIZE  = LENGTH(rpmsg_sh_mem);\r\n\r\n  \/* NOINIT section for rpmsg_sh_mem *\/\r\n  .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)\r\n  {\r\n     __RPMSG_SH_MEM_START__ = .;\r\n     *(.noinit.$rpmsg_sh_mem*)\r\n     . = ALIGN(4) ;\r\n     __RPMSG_SH_MEM_END__ = .;\r\n  } > rpmsg_sh_mem\r\n\r\n  \/* section for storing the secondary core image *\/\r\n  .core1_code :\r\n  {\r\n     . = ALIGN(4) ;\r\n    KEEP (*(.core1_code))\r\n     *(.core1_code*)\r\n     . = ALIGN(4) ;\r\n  } > m_sdram\r\n\r\n  \/* The startup code goes first into internal RAM *\/\r\n  .interrupts :\r\n  {\r\n    __VECTOR_TABLE = .;\r\n    __Vectors = .;\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))     \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } > m_interrupts\r\n\r\n  .curl :\r\n  {\r\n     . = ALIGN(4);\r\n     __curl_start = .;\r\n     *liblibs_curl.a:*(.text .text*)\r\n     *liblibs_curl.a:*(.data .data*)\r\n     *liblibs_curl.a:*(.rodata .rodata*)\r\n     __curl_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .mbedtls :\r\n  {\r\n     . = ALIGN(4);\r\n     __mbedtls_start = .;\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.rodata .rodata*)\r\n     __mbedtls_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .lwip :\r\n  {\r\n     . = ALIGN(4);\r\n     __lwip_start = .;\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.rodata .rodata*)\r\n     __lwip_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .wiced :\r\n  {\r\n     . = ALIGN(4);\r\n     __wiced_start = .;\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.rodata .rodata*)\r\n     *libwicedble.a:*(.text .text*)\r\n     *libwicedble.a:*(.data .data*)\r\n     *libwicedble.a:*(.rodata .rodata*)\r\n     __wiced_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .tensorflow :\r\n  {\r\n     . = ALIGN(4);\r\n     __tensorflow_start = .;\r\n     *liblibs_tensorflow-m7.a:*(.text .text*)\r\n     *liblibs_tensorflow-m7.a:*(.data .data*)\r\n     *liblibs_tensorflow-m7.a:*(.rodata .rodata*)\r\n     __tensorflow_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n\r\n  \/* The program code and other data goes into internal RAM *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)                 \/* .text sections (code) *\/\r\n    *(.text*)                \/* .text* sections (code) *\/\r\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\r\n    KEEP(*(.rodata.debug))\r\n    *(.glue_7)               \/* glue arm to thumb code *\/\r\n    *(.glue_7t)              \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._settings_handler_static :\r\n  {\r\n    . = ALIGN(4);\r\n    _settings_handler_static_list_start = .;\r\n    KEEP(*(SORT(._settings_handler_static.static.*)))\r\n    _settings_handler_static_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._bt_gatt_service_static :\r\n  {\r\n    . = ALIGN(4);\r\n    _bt_gatt_service_static_list_start = .;\r\n    KEEP(*(SORT(._bt_gatt_service_static.static.*)))\r\n    _bt_gatt_service_static_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._bt_l2cap_fixed_chan :\r\n  {\r\n    . = ALIGN(4);\r\n    _bt_l2cap_fixed_chan_list_start = .;\r\n    KEEP(*(SORT(._bt_l2cap_fixed_chan.static.*)))\r\n    _bt_l2cap_fixed_chan_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > m_text\r\n\r\n  .ARM :\r\n  {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } > m_text\r\n\r\n .ctors :\r\n  {\r\n    __CTOR_LIST__ = .;\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       from the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    __CTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .dtors :\r\n  {\r\n    __DTOR_LIST__ = .;\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    __DTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .preinit_array :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } > m_text\r\n\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } > m_text\r\n\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } > m_text\r\n\r\n  __etext = .;    \/* define a global symbol at end of code *\/\r\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\r\n\r\n  __VECTOR_RAM = ORIGIN(m_interrupts);\r\n  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;\r\n\r\n  .data : AT(__DATA_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __DATA_RAM = .;\r\n    __data_start__ = .;      \/* create a global symbol at data start *\/\r\n    *(m_usb_dma_init_data)\r\n    *(.data)                 \/* .data sections *\/\r\n    *(.data*)                \/* .data* sections *\/\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    _net_buf_pool_list = .;\r\n    KEEP(*(SORT(._net_buf_pool*)))\r\n    . = ALIGN(4);\r\n    __data_end__ = .;        \/* define a global symbol at data end *\/\r\n  } > m_data\r\n  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);\r\n  .ncache.init : AT(__NDATA_ROM)\r\n  {\r\n    __noncachedata_start__ = .;   \/* create a global symbol at ncache data start *\/\r\n    *(NonCacheable.init)\r\n    . = ALIGN(4);\r\n    __noncachedata_init_end__ = .;   \/* create a global symbol at initialized ncache data end *\/\r\n  } > m_data\r\n  . = __noncachedata_init_end__;\r\n  .ncache :\r\n  {\r\n    *(NonCacheable)\r\n    . = ALIGN(4);\r\n    __noncachedata_end__ = .;     \/* define a global symbol at ncache data end *\/\r\n  } > m_data\r\n  __SDRAM_ROM = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);\r\n  .sdram_data : AT(__SDRAM_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_data_start__ = .;\r\n    KEEP(*(.sdram_data*))\r\n    . = ALIGN(4);\r\n    __sdram_data_end__ = .;\r\n  } > m_sdram\r\n\r\n  \/* Uninitialized data section *\/\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss section *\/\r\n    . = ALIGN(4);\r\n    __START_BSS = .;\r\n    __bss_start__ = .;\r\n    *(m_usb_dma_noninit_data)\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n    __END_BSS = .;\r\n  } > m_data\r\n  __DATA_END = __SDRAM_ROM;\r\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\r\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\r\n\r\n  .sdram_bss (NOLOAD) :\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_bss_start__ = .;\r\n    *(.sdram_bss*)\r\n    . = ALIGN(4);\r\n    __sdram_bss_end__ = .;\r\n  } > m_sdram\r\n\r\n  .heap :\r\n  {\r\n    . = ALIGN(8);\r\n    __end__ = .;\r\n    PROVIDE(end = .);\r\n    __HeapBase = .;\r\n    . += HEAP_SIZE;\r\n    __HeapLimit = .;\r\n    __heap_limit = .; \/* Add for _sbrk *\/\r\n  } > m_heap\r\n\r\n  .stack :\r\n  {\r\n    . = ALIGN(8);\r\n    . += STACK_SIZE;\r\n  } > m_stack\r\n\r\n  \/* Initializes stack on the end of block *\/\r\n  __StackTop   = ORIGIN(m_stack) + LENGTH(m_stack);\r\n  __StackLimit = __StackTop - STACK_SIZE;\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"80dbab1e70d253ce1d9e4980b35871ecd5e74578","subject":"esp8266\/boards: Move py\/pairheap.c code from iRAM to iROM.","message":"esp8266\/boards: Move py\/pairheap.c code from iRAM to iROM.\n\nIt doesn't need to be in iRAM.\n","repos":"pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython","old_file":"ports\/esp8266\/boards\/esp8266_common.ld","new_file":"ports\/esp8266\/boards\/esp8266_common.ld","new_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* Vendor SDK in v2.1.0-7-gb8fd588 started to build these with\n           -ffunction-sections -fdata-sections, and require routing to\n           irom via linker:\n           https:\/\/github.com\/espressif\/ESP8266_NONOS_SDK\/commit\/b8fd588a33f0319dc135523b51655e97b483b205\n         *\/\n\n        *libcrypto.a:(.literal.* .text.*)\n        *libnet80211.a:(.literal.* .text.*)\n        *libwpa.a:(.literal.* .text.*)\n        *libwpa2.a:(.literal.* .text.*)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/pairheap*.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/profile*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *lib\/axtls\/*.o(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/littlefs\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/printf.o*(.literal*, .text*)\n        *lib\/utils\/sys_stdio_mphal.o*(.literal*, .text*)\n        *lib\/utils\/pyexec.o*(.literal*, .text*)\n        *lib\/utils\/stdout_helpers.o*(.literal*, .text*)\n        *lib\/utils\/interrupt_char.o*(.literal*, .text*)\n        *drivers\/bus\/*.o(.literal* .text*)\n\n        build-*\/main.o(.literal* .text*)\n        *fatfs_port.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build-*\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"boards\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* Vendor SDK in v2.1.0-7-gb8fd588 started to build these with\n           -ffunction-sections -fdata-sections, and require routing to\n           irom via linker:\n           https:\/\/github.com\/espressif\/ESP8266_NONOS_SDK\/commit\/b8fd588a33f0319dc135523b51655e97b483b205\n         *\/\n\n        *libcrypto.a:(.literal.* .text.*)\n        *libnet80211.a:(.literal.* .text.*)\n        *libwpa.a:(.literal.* .text.*)\n        *libwpa2.a:(.literal.* .text.*)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/profile*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *lib\/axtls\/*.o(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/littlefs\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/printf.o*(.literal*, .text*)\n        *lib\/utils\/sys_stdio_mphal.o*(.literal*, .text*)\n        *lib\/utils\/pyexec.o*(.literal*, .text*)\n        *lib\/utils\/stdout_helpers.o*(.literal*, .text*)\n        *lib\/utils\/interrupt_char.o*(.literal*, .text*)\n        *drivers\/bus\/*.o(.literal* .text*)\n\n        build-*\/main.o(.literal* .text*)\n        *fatfs_port.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build-*\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"boards\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"73f4a52361c8e41c9d6f773c98c788dd386550d4","subject":"Target_ONSEMI:  Setup heap limit and size","message":"Target_ONSEMI:  Setup heap limit and size\n","repos":"mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed","old_file":"targets\/TARGET_ONSEMI\/TARGET_NCS36510\/device\/TOOLCHAIN_GCC_ARM\/NCS36510.ld","new_file":"targets\/TARGET_ONSEMI\/TARGET_NCS36510\/device\/TOOLCHAIN_GCC_ARM\/NCS36510.ld","new_contents":"\/*\n * NCS36510 ARM GCC linker script file\n *\/\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\nMEMORY {\n    FIB (rx)              : ORIGIN = 0x00002000, LENGTH = 0x00000800\n    TRIM (rx)             : ORIGIN = 0x00002800, LENGTH = 0x00000800\n    VECTORS (rx)          : ORIGIN = 0x00003000, LENGTH = 0x00000090\n    FLASH (rx)            : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90\n    RAM (rwx)             : ORIGIN = 0x3FFF4090, LENGTH = 48K - 0x90 \/* 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 *\/\n}\n\n    \/* Linker script to place sections and symbol values. Should be used together\n     * with other linker script that defines memory regions FLASH and RAM.\n     * It references following symbols, which must be defined in code:\n     * _reset_init : Entry of reset handler\n     *\n     * It defines following symbols, which code can use without definition:\n     * __exidx_start\n     * __exidx_end\n     * __etext\n     * __data_start__\n     * __preinit_array_start\n     * __preinit_array_end\n     * __init_array_start\n     * __init_array_end\n     * __fini_array_start\n     * __fini_array_end\n     * __data_end__\n     * __bss_start__\n     * __bss_end__\n     * __end__\n     * end\n     * __HeapLimit\n     * __StackLimit\n     * __StackTop\n     * __stack\n     *\/\n    ENTRY(Reset_Handler)\n\n    SECTIONS {\n    .fib :\n    {\n        KEEP(*(.fib))\n    } > FIB\n\n    .trim :\n    {\n        KEEP(*(.trim))\n    } > TRIM\n\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        . = ALIGN(8);\n    } > VECTORS\n\n\n.text :\n    {\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n.ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n.ARM.exidx :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > FLASH\n\n.data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM AT>FLASH\n\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += STACK_SIZE - (. - __StackLimit);\n    } > RAM\n\n    \/* Set stack top to end of RAM *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n}\n","old_contents":"\/*\n * NCS36510 ARM GCC linker script file\n *\/\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\nMEMORY {\n    FIB (rx)              : ORIGIN = 0x00002000, LENGTH = 0x00000800\n    TRIM (rx)             : ORIGIN = 0x00002800, LENGTH = 0x00000800\n    VECTORS (rx)          : ORIGIN = 0x00003000, LENGTH = 0x00000090\n    FLASH (rx)            : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90\n    RAM (rwx)             : ORIGIN = 0x3FFF4090, LENGTH = 48K - 0x90 \/* 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 *\/\n}\n\n    \/* Linker script to place sections and symbol values. Should be used together\n     * with other linker script that defines memory regions FLASH and RAM.\n     * It references following symbols, which must be defined in code:\n     * _reset_init : Entry of reset handler\n     *\n     * It defines following symbols, which code can use without definition:\n     * __exidx_start\n     * __exidx_end\n     * __etext\n     * __data_start__\n     * __preinit_array_start\n     * __preinit_array_end\n     * __init_array_start\n     * __init_array_end\n     * __fini_array_start\n     * __fini_array_end\n     * __data_end__\n     * __bss_start__\n     * __bss_end__\n     * __end__\n     * end\n     * __HeapLimit\n     * __StackLimit\n     * __StackTop\n     * __stack\n     *\/\n    ENTRY(Reset_Handler)\n\n    SECTIONS {\n    .fib :\n    {\n        KEEP(*(.fib))\n    } > FIB\n\n    .trim :\n    {\n        KEEP(*(.trim))\n    } > TRIM\n\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        . = ALIGN(8);\n    } > VECTORS\n\n\n.text :\n    {\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n.ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n.ARM.exidx :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > FLASH\n\n.data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM AT>FLASH\n\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += 0x800;\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += STACK_SIZE - (. - __StackLimit);\n    } > RAM\n\n    \/* Set stack top to end of RAM *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cd13e25bb325a419ad5ca3c4192051e3fefa7242","subject":"arch: arm: aarch32: linker file fix for OCM","message":"arch: arm: aarch32: linker file fix for OCM\n\nFix the mapping of the sections to be located in the On-Chip\nMemory so that the OCM memory region name always matches that\nof the chosen OCM DT node's memory-region attribute.\n\nSigned-off-by: Immo Birnbaum <9d53277017f7b972042afc81794f782b84cac388@weidmueller.com>\n","repos":"galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_a_r\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_a_r\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A and Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/devicetree_regions.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#elif defined(CONFIG_ARM_AARCH32_MMU)\n_region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\n#define BSS_ALIGN ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_ocm), rw)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n    __rom_region_start = ROM_ADDR;\n#else\n    __rom_region_start = RAM_ADDR;\n#endif\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        . = ALIGN(_region_min_align);\n        __text_region_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#include <linker\/kobject-text.ld>\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n    . = ALIGN(_region_min_align);\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    . = ALIGN(_region_min_align);\n    __rodata_region_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n#include <linker\/cplusplus-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n\n        \/*\n         * RODATA must be the last section so that the size of the entire read\n         * only area will be filled to a power of 2.\n         *\/\n        MPU_ALIGN(ABSOLUTE(.) - __rom_region_start);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    __rodata_region_end = .;\n    __rom_region_end = .;\n    MPU_ALIGN(__rodata_region_end - __rom_region_start);\n    _image_rom_end_order = (LOG2CEIL(__rom_region_end) - 1) << 1;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_region_start = .;\n        __data_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n        __data_end = .;\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    . = ALIGN(_region_min_align);\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ocm), okay)\nGROUP_START(OCM)\n\n\tSECTION_PROLOGUE(_OCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__ocm_start = .;\n\t\t__ocm_bss_start = .;\n\t\t*(.ocm_bss)\n\t\t*(\".ocm_bss.*\")\n\t\t__ocm_bss_end = .;\n\t} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ocm)))\n\n\tSECTION_PROLOGUE(_OCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__ocm_data_start = .;\n\t\t*(.ocm_data)\n\t\t*(\".ocm_data.*\")\n\t\t__ocm_data_end = .;\n\t} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ocm)))\n\n  __ocm_end = .;\n  __ocm_size = __ocm_end - __ocm_start;\n\nGROUP_END(OCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A and Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/devicetree_regions.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#elif defined(CONFIG_ARM_AARCH32_MMU)\n_region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\n#define BSS_ALIGN ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_ocm), rw)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n    __rom_region_start = ROM_ADDR;\n#else\n    __rom_region_start = RAM_ADDR;\n#endif\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        . = ALIGN(_region_min_align);\n        __text_region_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#include <linker\/kobject-text.ld>\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n    . = ALIGN(_region_min_align);\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    . = ALIGN(_region_min_align);\n    __rodata_region_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n#include <linker\/cplusplus-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n\n        \/*\n         * RODATA must be the last section so that the size of the entire read\n         * only area will be filled to a power of 2.\n         *\/\n        MPU_ALIGN(ABSOLUTE(.) - __rom_region_start);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    __rodata_region_end = .;\n    __rom_region_end = .;\n    MPU_ALIGN(__rodata_region_end - __rom_region_start);\n    _image_rom_end_order = (LOG2CEIL(__rom_region_end) - 1) << 1;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_region_start = .;\n        __data_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n        __data_end = .;\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    . = ALIGN(_region_min_align);\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ocm), okay)\nGROUP_START(OCM)\n\n\tSECTION_PROLOGUE(_OCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__ocm_start = .;\n\t\t__ocm_bss_start = .;\n\t\t*(.ocm_bss)\n\t\t*(\".ocm_bss.*\")\n\t\t__ocm_bss_end = .;\n\t} GROUP_LINK_IN(OCM)\n\n\tSECTION_PROLOGUE(_OCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__ocm_data_start = .;\n\t\t*(.ocm_data)\n\t\t*(\".ocm_data.*\")\n\t\t__ocm_data_end = .;\n\t} GROUP_LINK_IN(OCM)\n\n  __ocm_end = .;\n  __ocm_size = __ocm_end - __ocm_start;\n\nGROUP_END(OCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"21ba6531cbab1d5948fa51bff54dfd5326021b39","subject":"add some unused memory until I can figure out what's using so much","message":"add some unused memory until I can figure out what's using so much\n","repos":"benemorius\/openOBC-devboard,benemorius\/openOBC-devboard","old_file":"lpc17xx.ld","new_file":"lpc17xx.ld","new_contents":"\/*Copyright (C) 2011 by Sagar G V, Thejasvi M V\r\n\r\nPermission is hereby granted, free of charge, to any person obtaining a copy\r\nof this software and associated documentation files (the \"Software\"), to deal\r\nin the Software without restriction, including without limitation the rights\r\nto use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\r\ncopies of the Software, and to permit persons to whom the Software is\r\nfurnished to do so, subject to the following conditions:\r\n\r\nThe above copyright notice and this permission notice shall be included in\r\nall copies or substantial portions of the Software.\r\n\r\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\r\nTHE SOFTWARE.*\/\r\n\r\nOUTPUT_FORMAT (\"elf32-littlearm\")\r\nENTRY(Reset_Handler)\r\nSEARCH_DIR(.)\r\n\r\nMEMORY\r\n{\r\n        \/* LPC1768 : 512k ROM + 64k SRAM *\/\r\n        \/*------------------------------ *\/\r\n\r\n\t\/* On-chip ROM is a readable (r), executable region (x) *\/\r\n\t\/* On-chip SRAM is a readable (r), writable (w) and *\/\r\n\t\/* executable region (x) *\/\r\n\r\n\t\/* Main ROM region - 512k for LPC1768 *\/\r\n\tIROM (rx) : ORIGIN = 0x00000000, LENGTH = 512k\r\n\r\n\t\/* local static RAM - 32k for LPC1768 *\/\r\n\tIRAM0 (rwx) : ORIGIN = 0x10000000, LENGTH = 32k\r\n\r\n\t\/* AHB SRAM - 16k for LPC1768 - often used for USB *\/\r\n\tIRAM1 (rwx) : ORIGIN = 0x2007C000, LENGTH = 16k\r\n\tIRAM2 (rwx) : ORIGIN = 0x20080000, LENGTH = 16k\r\n}\r\n\r\n\/* SECTION command : Define mapping of input sections *\/\r\n\/* into output sections. *\/\r\n\r\nSECTIONS\r\n{\r\n\t\/******************************************\/\r\n\t\/* code section *\/\r\n\r\n        \/* \"normal\" code *\/\r\n\t\r\n\t.text :\r\n\t{\r\n\t\tKEEP(*(.isr_vector .isr_vector.*))\r\n\t\t*(.text .text.*)\r\n\t\t*(.gnu.linkonce.t.*)\r\n\t\t*(.glue_7)\r\n\t\t*(.glue_7t)\r\n\t\t*(.gcc_except_table)\r\n\t\t*(.rodata .rodata*)\r\n\t\t*(.gnu.linkonce.r.*)\r\n\t\t. = ALIGN(4);\r\n\t\tKEEP(*(.init))\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\t__preinit_array_start = .;\r\n\t\tKEEP (*(.preinit_array))\r\n\t\t__preinit_array_end = .;\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\t__init_array_start = .;\r\n\t\tKEEP (*(SORT(.init_array.*)))\r\n\t\tKEEP (*(.init_array))\r\n\t\t__init_array_end = .;\r\n\t\t\r\n\t\t. = ALIGN(0x4);\r\n\t\tKEEP (*crtbegin.o(.ctors))\r\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n\t\tKEEP (*(SORT(.ctors.*)))\r\n\t\tKEEP (*crtend.o(.ctors))\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\tKEEP(*(.fini))\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\t__fini_array_start = .;\r\n\t\tKEEP (*(.fini_array))\r\n\t\tKEEP (*(SORT(.fini_array.*)))\r\n\t\t__fini_array_end = .;\r\n\t\t\r\n\r\n\t\t. = ALIGN(0x4);\r\n\t\tKEEP (*crtbegin.o(.dtors))\r\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n\t\tKEEP (*(SORT(.dtors.*)))\r\n\t\tKEEP (*crtend.o(.dtors))\r\n\t\t\r\n\t\t\/* End Of .text section *\/\r\n\t\t_etext = .;\r\n                _sifastcode = .;\r\n\t\t\t\t\r\n\t} >IROM\r\n\r\n\t\r\n\t__exidx_start = .;\r\n\t.ARM.exidx :\r\n\t{\r\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\t} >IROM\r\n\t__exidx_end = .;\r\n\t\r\n        \/**************************************************\/\r\n        \/* fastcode - copied at startup & executed in RAM *\/\r\n\r\n        .fastcode :\r\n        {\r\n          . = ALIGN (4);\r\n          _sfastcode = . ;\r\n\r\n          *(.glue_7t) *(.glue_7)\r\n          *(.fastcode)\r\n          \r\n          \/* add other modules here ... *\/\r\n\r\n          . = ALIGN (4);\r\n          _efastcode = . ;\r\n          _sidata = .;\r\n        } >IRAM2 AT>IROM\r\n\r\n\t\/******************************************\/\r\n\t\/* This used for USB RAM section *\/\r\n\t.usb_ram (NOLOAD):\r\n\t{\r\n\t\t*.o (USB_RAM)\r\n\t} > IRAM1\r\n\r\n        \/******************************************\/\r\n\t\/* data section *\/\r\n\t.data :\r\n  \t{\r\n        \t_sidata = LOADADDR (.data);\r\n  \t\t. = ALIGN(4);\r\n\t\t_sdata = .;\r\n\r\n\t\t*(vtable vtable.*)\r\n\t\t*(.data .data.*)\r\n\t\t*(.gnu.linkonce.d*)\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t_edata = . ;\r\n\t} >IRAM2 AT>IROM\r\n\r\n\t\/******************************************\/\r\n\t\/* For no-init variables section *\/\r\n\t.bss (NOLOAD) :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t_sbss = . ;\r\n\r\n\t\t*(.bss .bss.*)\r\n\t\t*(.gnu.linkonce.b*)\r\n\t\t*(COMMON)\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t_ebss = . ;\r\n\t} >IRAM2\r\n\r\n\t\/******************************************\/\r\n\t\/* For stack section *\/\r\n  \t.stackarea (NOLOAD) :\r\n  \t{\r\n\t    . = ALIGN(8);\r\n\t    _sstack = .;\r\n\r\n\t\t*(.stackarea .stackarea.*)\r\n\r\n\t\t. = ALIGN(8);\r\n\t\t_estack = .;\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t_end = . ;\r\n\t\tPROVIDE (end = .);\r\n\r\n  \t} > IRAM0\r\n\t_stack = ORIGIN(IRAM0) + LENGTH(IRAM0);\r\n\r\n\r\n\t\/******************************************\/\r\n\t\/* Stabs debugging sections.  *\/\r\n\t.stab          0 : { *(.stab) }\r\n\t.stabstr       0 : { *(.stabstr) }\r\n\t.stab.excl     0 : { *(.stab.excl) }\r\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\r\n\t.stab.index    0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t\/* .comment       0 : { *(.comment) } *\/\r\n\t\/* DWARF debug sections.\r\n\t Symbols in the DWARF debugging sections are relative to the beginning\r\n\t of the section so we begin them at 0.  *\/\r\n\t\/* DWARF 1 *\/\r\n\t.debug          0 : { *(.debug) }\r\n\t.line           0 : { *(.line) }\r\n\t\/* GNU DWARF 1 extensions *\/\r\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\r\n\t\/* DWARF 1.1 and DWARF 2 *\/\r\n\t.debug_aranges  0 : { *(.debug_aranges) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t\/* DWARF 2 *\/\r\n\t.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\r\n\t.debug_line     0 : { *(.debug_line) }\r\n\t.debug_frame    0 : { *(.debug_frame) }\r\n\t.debug_str      0 : { *(.debug_str) }\r\n\t.debug_loc      0 : { *(.debug_loc) }\r\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\r\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\r\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\r\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\r\n\t.debug_typenames 0 : { *(.debug_typenames) }\r\n\t.debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","old_contents":"\/*Copyright (C) 2011 by Sagar G V, Thejasvi M V\r\n\r\nPermission is hereby granted, free of charge, to any person obtaining a copy\r\nof this software and associated documentation files (the \"Software\"), to deal\r\nin the Software without restriction, including without limitation the rights\r\nto use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\r\ncopies of the Software, and to permit persons to whom the Software is\r\nfurnished to do so, subject to the following conditions:\r\n\r\nThe above copyright notice and this permission notice shall be included in\r\nall copies or substantial portions of the Software.\r\n\r\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\r\nTHE SOFTWARE.*\/\r\n\r\nOUTPUT_FORMAT (\"elf32-littlearm\")\r\nENTRY(Reset_Handler)\r\nSEARCH_DIR(.)\r\n\r\nMEMORY\r\n{\r\n        \/* LPC1768 : 512k ROM + 64k SRAM *\/\r\n        \/*------------------------------ *\/\r\n\r\n\t\/* On-chip ROM is a readable (r), executable region (x) *\/\r\n\t\/* On-chip SRAM is a readable (r), writable (w) and *\/\r\n\t\/* executable region (x) *\/\r\n\r\n\t\/* Main ROM region - 512k for LPC1768 *\/\r\n\tIROM (rx) : ORIGIN = 0x00000000, LENGTH = 512k\r\n\r\n\t\/* local static RAM - 32k for LPC1768 *\/\r\n\tIRAM0 (rwx) : ORIGIN = 0x10000000, LENGTH = 32k\r\n\r\n\t\/* AHB SRAM - 16k for LPC1768 - often used for USB *\/\r\n\tIRAM1 (rwx) : ORIGIN = 0x2007C000, LENGTH = 16k\r\n\tIRAM2 (rwx) : ORIGIN = 0x20080000, LENGTH = 16k\r\n}\r\n\r\n\/* SECTION command : Define mapping of input sections *\/\r\n\/* into output sections. *\/\r\n\r\nSECTIONS\r\n{\r\n\t\/******************************************\/\r\n\t\/* code section *\/\r\n\r\n        \/* \"normal\" code *\/\r\n\t\r\n\t.text :\r\n\t{\r\n\t\tKEEP(*(.isr_vector .isr_vector.*))\r\n\t\t*(.text .text.*)\r\n\t\t*(.gnu.linkonce.t.*)\r\n\t\t*(.glue_7)\r\n\t\t*(.glue_7t)\r\n\t\t*(.gcc_except_table)\r\n\t\t*(.rodata .rodata*)\r\n\t\t*(.gnu.linkonce.r.*)\r\n\t\t. = ALIGN(4);\r\n\t\tKEEP(*(.init))\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\t__preinit_array_start = .;\r\n\t\tKEEP (*(.preinit_array))\r\n\t\t__preinit_array_end = .;\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\t__init_array_start = .;\r\n\t\tKEEP (*(SORT(.init_array.*)))\r\n\t\tKEEP (*(.init_array))\r\n\t\t__init_array_end = .;\r\n\t\t\r\n\t\t. = ALIGN(0x4);\r\n\t\tKEEP (*crtbegin.o(.ctors))\r\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n\t\tKEEP (*(SORT(.ctors.*)))\r\n\t\tKEEP (*crtend.o(.ctors))\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\tKEEP(*(.fini))\r\n\t\t\r\n\t\t. = ALIGN(4);\r\n\t\t__fini_array_start = .;\r\n\t\tKEEP (*(.fini_array))\r\n\t\tKEEP (*(SORT(.fini_array.*)))\r\n\t\t__fini_array_end = .;\r\n\t\t\r\n\r\n\t\t. = ALIGN(0x4);\r\n\t\tKEEP (*crtbegin.o(.dtors))\r\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n\t\tKEEP (*(SORT(.dtors.*)))\r\n\t\tKEEP (*crtend.o(.dtors))\r\n\t\t\r\n\t\t\/* End Of .text section *\/\r\n\t\t_etext = .;\r\n                _sifastcode = .;\r\n\t\t\t\t\r\n\t} >IROM\r\n\r\n\t\r\n\t__exidx_start = .;\r\n\t.ARM.exidx :\r\n\t{\r\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\t} >IROM\r\n\t__exidx_end = .;\r\n\t\r\n        \/**************************************************\/\r\n        \/* fastcode - copied at startup & executed in RAM *\/\r\n\r\n        .fastcode :\r\n        {\r\n          . = ALIGN (4);\r\n          _sfastcode = . ;\r\n\r\n          *(.glue_7t) *(.glue_7)\r\n          *(.fastcode)\r\n          \r\n          \/* add other modules here ... *\/\r\n\r\n          . = ALIGN (4);\r\n          _efastcode = . ;\r\n          _sidata = .;\r\n        } >IRAM0 AT>IROM\r\n\r\n\t\/******************************************\/\r\n\t\/* This used for USB RAM section *\/\r\n\t.usb_ram (NOLOAD):\r\n\t{\r\n\t\t*.o (USB_RAM)\r\n\t} > IRAM1\r\n\r\n        \/******************************************\/\r\n\t\/* data section *\/\r\n\t.data :\r\n  \t{\r\n        \t_sidata = LOADADDR (.data);\r\n  \t\t. = ALIGN(4);\r\n\t\t_sdata = .;\r\n\r\n\t\t*(vtable vtable.*)\r\n\t\t*(.data .data.*)\r\n\t\t*(.gnu.linkonce.d*)\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t_edata = . ;\r\n\t} >IRAM0 AT>IROM\r\n\r\n\t\/******************************************\/\r\n\t\/* For no-init variables section *\/\r\n\t.bss (NOLOAD) :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t_sbss = . ;\r\n\r\n\t\t*(.bss .bss.*)\r\n\t\t*(.gnu.linkonce.b*)\r\n\t\t*(COMMON)\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t_ebss = . ;\r\n\t} >IRAM0\r\n\r\n\t\/******************************************\/\r\n\t\/* For stack section *\/\r\n  \t.stackarea (NOLOAD) :\r\n  \t{\r\n\t    . = ALIGN(8);\r\n\t    _sstack = .;\r\n\r\n\t\t*(.stackarea .stackarea.*)\r\n\r\n\t\t. = ALIGN(8);\r\n\t\t_estack = .;\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t_end = . ;\r\n\t\tPROVIDE (end = .);\r\n\r\n  \t} > IRAM0\r\n\t_stack = ORIGIN(IRAM0) + LENGTH(IRAM0);\r\n\r\n\r\n\t\/******************************************\/\r\n\t\/* Stabs debugging sections.  *\/\r\n\t.stab          0 : { *(.stab) }\r\n\t.stabstr       0 : { *(.stabstr) }\r\n\t.stab.excl     0 : { *(.stab.excl) }\r\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\r\n\t.stab.index    0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t\/* .comment       0 : { *(.comment) } *\/\r\n\t\/* DWARF debug sections.\r\n\t Symbols in the DWARF debugging sections are relative to the beginning\r\n\t of the section so we begin them at 0.  *\/\r\n\t\/* DWARF 1 *\/\r\n\t.debug          0 : { *(.debug) }\r\n\t.line           0 : { *(.line) }\r\n\t\/* GNU DWARF 1 extensions *\/\r\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\r\n\t\/* DWARF 1.1 and DWARF 2 *\/\r\n\t.debug_aranges  0 : { *(.debug_aranges) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t\/* DWARF 2 *\/\r\n\t.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\r\n\t.debug_line     0 : { *(.debug_line) }\r\n\t.debug_frame    0 : { *(.debug_frame) }\r\n\t.debug_str      0 : { *(.debug_str) }\r\n\t.debug_loc      0 : { *(.debug_loc) }\r\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\r\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\r\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\r\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\r\n\t.debug_typenames 0 : { *(.debug_typenames) }\r\n\t.debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f99bb0bcbf563e4f7787d1d288c922a28243b271","subject":"Humm, this might be important.","message":"Humm, this might be important.\n","repos":"thejpster\/launchpad-rs,thejpster\/launchpad-rs,thejpster\/bare-metal-arm-rust,thejpster\/bare-metal-arm-rust","old_file":"lm4f120.ld","new_file":"lm4f120.ld","new_contents":"\/*\n* Copyright (c) 2012, Mauro Scomparin\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*     * Redistributions of source code must retain the above copyright\n*       notice, this list of conditions and the following disclaimer.\n*     * Redistributions in binary form must reproduce the above copyright\n*       notice, this list of conditions and the following disclaimer in the\n*       documentation and\/or other materials provided with the distribution.\n*     * Neither the name of Mauro Scomparin nor the\n*       names of its contributors may be used to endorse or promote products\n*       derived from this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY Mauro Scomparin ``AS IS'' AND ANY\n* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL Mauro Scomparin BE LIABLE FOR ANY\n* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*\n* Author:   Mauro Scomparin <http:\/\/scompoprojects.wordpress.com>.\n* Author:   Jonathan Pallant <http:\/\/railwayelectronics.blogspot.com>.\n* Description:  Linker description file for LM4FXXX microcontrollers.\n*\/\n\n\/*\n* Memory definition:\n* FLASH:  start point 0x00,   lenght 0x40000.\n* SRAM:   start point 0x20000000  length 0x8000.\n*   VAR:    enough to hold .data and .bss\n*   HEAP:   All the remaining space, up to...\n*   STACK:  start point 0x20007000  length 0x1000.\n*\/\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\n_stack_size = 0x1000;\n\n\/* # Entry point = reset vector *\/\nENTRY(Reset);\nEXTERN(__RESET_VECTOR);\n\n\/*\n* Sections definitions:\n*\n* .text     - machine instructions.\n* .data     - initialized data defined in the program.\n* .bss      - un-initialized global and static variables (to be initialized to 0 before starting main).\n*\/\nSECTIONS\n{\n    \/* This section it's the code, containing the NVIC Vector table that must start at 0x0\n     *   Look at the LM4F120H5QR datasheet for details. (Table 2-8. Exception Types)\n     *\/\n\n    .vector_table : {\n        \/* Initial Stack Pointer (SP) value *\/\n        LONG(_stack_top);\n\n        \/* Reset vector *\/\n        KEEP(*(.vector_table.reset_vector));\n\n        \/* Exceptions *\/\n        KEEP(*(.vector_table.exceptions));\n    } > FLASH\n\n    .text :\n    {\n        *(.text .text.*)         \/* This contains most of the executable code. *\/\n        *(.rodata .rodata.*)     \/* Read only data (const variables) *\/\n        . = ALIGN(4);\n    } > FLASH\n\n    \/* Don't need these *\/\n    \/DISCARD\/ : {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    }\n\n    _data_start_flash = ALIGN(8);\n\n    \/*\n     * .data segment must be placed in RAM but it's originally stored in FLASH\n     * So I set the data segment in ram, but I specify the load address with the AT\n     * keyword to set that right after the .text section.\n     * (Look at the LD documentation. (Optional Section Attributes))\n     * Thanks https:\/\/github.com\/utzig for the hints!\n     *\/\n    .data : AT (_data_start_flash)\n    {\n        . = ALIGN(4);\n        _data_start = ABSOLUTE(.);  \/* An index to the beginning of .data segment. *\/\n        *(.data*)         \/* Initialised program data *\/\n        . = ALIGN(4);\n        _data_end = ABSOLUTE(.);    \/* And another index to the end of .data segment. *\/\n    } > SRAM\n\n    \/*\n    * .bss contains the unitialized variables and must be set as 0x0 during runtime.\n    * It should be loaded in RAM and particular care should be taken initializing them in the startup file.\n    *\/\n    .bss :\n    {\n        . = ALIGN(4);\n       _bss_start = ABSOLUTE(.);  \/* This is an index to the beginning of .bss segment. *\/\n        *(.bss*)                  \/* The un-initialized data should go there.  *\/\n        . = ALIGN(4);\n        _bss_end = ABSOLUTE(.);   \/* End index for .bss segment *\/\n    } > SRAM\n\n    _heap_start = .;\n    _heap_end = ORIGIN(SRAM) + LENGTH(SRAM) - _stack_size;\n    _stack_bottom = _heap_end;\n    _stack_top = ORIGIN(SRAM) + LENGTH(SRAM);\n}\n","old_contents":"\/*\n* Copyright (c) 2012, Mauro Scomparin\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*     * Redistributions of source code must retain the above copyright\n*       notice, this list of conditions and the following disclaimer.\n*     * Redistributions in binary form must reproduce the above copyright\n*       notice, this list of conditions and the following disclaimer in the\n*       documentation and\/or other materials provided with the distribution.\n*     * Neither the name of Mauro Scomparin nor the\n*       names of its contributors may be used to endorse or promote products\n*       derived from this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY Mauro Scomparin ``AS IS'' AND ANY\n* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL Mauro Scomparin BE LIABLE FOR ANY\n* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*\n* Author:   Mauro Scomparin <http:\/\/scompoprojects.wordpress.com>.\n* Author:   Jonathan Pallant <http:\/\/railwayelectronics.blogspot.com>.\n* Description:  Linker description file for LM4FXXX microcontrollers.\n*\/\n\n\/*\n* Memory definition:\n* FLASH:  start point 0x00,   lenght 0x40000.\n* SRAM:   start point 0x20000000  length 0x8000.\n*   VAR:    enough to hold .data and .bss\n*   HEAP:   All the remaining space, up to...\n*   STACK:  start point 0x20007000  length 0x1000.\n*\/\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\n_stack_size = 0x1000;\n\n\/* # Entry point = reset vector *\/\nENTRY(Reset);\n\n\/*\n* Sections definitions:\n*\n* .text     - machine instructions.\n* .data     - initialized data defined in the program.\n* .bss      - un-initialized global and static variables (to be initialized to 0 before starting main).\n*\/\nSECTIONS\n{\n    \/* This section it's the code, containing the NVIC Vector table that must start at 0x0\n     *   Look at the LM4F120H5QR datasheet for details. (Table 2-8. Exception Types)\n     *\/\n\n    .vector_table : {\n        \/* Initial Stack Pointer (SP) value *\/\n        LONG(_stack_top);\n\n        \/* Reset vector *\/\n        KEEP(*(.vector_table.reset_vector));\n\n        \/* Exceptions *\/\n        KEEP(*(.vector_table.exceptions));\n    } > FLASH\n\n    .text :\n    {\n        *(.text .text.*)         \/* This contains most of the executable code. *\/\n        *(.rodata .rodata.*)     \/* Read only data (const variables) *\/\n        . = ALIGN(4);\n    } > FLASH\n\n    \/* Don't need these *\/\n    \/DISCARD\/ : {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    }\n\n    _data_start_flash = ALIGN(8);\n\n    \/*\n     * .data segment must be placed in RAM but it's originally stored in FLASH\n     * So I set the data segment in ram, but I specify the load address with the AT\n     * keyword to set that right after the .text section.\n     * (Look at the LD documentation. (Optional Section Attributes))\n     * Thanks https:\/\/github.com\/utzig for the hints!\n     *\/\n    .data : AT (_data_start_flash)\n    {\n        . = ALIGN(4);\n        _data_start = ABSOLUTE(.);  \/* An index to the beginning of .data segment. *\/\n        *(.data*)         \/* Initialised program data *\/\n        . = ALIGN(4);\n        _data_end = ABSOLUTE(.);    \/* And another index to the end of .data segment. *\/\n    } > SRAM\n\n    \/*\n    * .bss contains the unitialized variables and must be set as 0x0 during runtime.\n    * It should be loaded in RAM and particular care should be taken initializing them in the startup file.\n    *\/\n    .bss :\n    {\n        . = ALIGN(4);\n       _bss_start = ABSOLUTE(.);  \/* This is an index to the beginning of .bss segment. *\/\n        *(.bss*)                  \/* The un-initialized data should go there.  *\/\n        . = ALIGN(4);\n        _bss_end = ABSOLUTE(.);   \/* End index for .bss segment *\/\n    } > SRAM\n\n    _heap_start = .;\n    _heap_end = ORIGIN(SRAM) + LENGTH(SRAM) - _stack_size;\n    _stack_bottom = _heap_end;\n    _stack_top = ORIGIN(SRAM) + LENGTH(SRAM);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"d2eb85eef828cd73e617afaa7c92b9166d0397ab","subject":"Fix typo in comment","message":"Fix typo in comment\n","repos":"payne92\/bare-metal-arm,mbains\/bare-metal-arm,payne92\/bare-metal-arm,mbains\/bare-metal-arm,firebitsbr\/bare-metal-arm,payne92\/bare-metal-arm,firebitsbr\/bare-metal-arm","old_file":"mkl25z4.ld","new_file":"mkl25z4.ld","new_contents":"\/**************************************************************************\/\r\n\/* Configure memory regions *\/\r\nMEMORY\r\n{\r\n  VECTORS (rx)      : ORIGIN = 0x0,         LENGTH = 0x00c0\r\n  FLASHCFG (rx)     : ORIGIN = 0x00000400,  LENGTH = 0x00000010\r\n  FLASH (rx)        : ORIGIN = 0x00000410,  LENGTH = 128K - 0x410\r\n  RAM  (rwx)        : ORIGIN = 0x1FFFF000,  LENGTH = 16K\r\n}\r\n\r\n\/* Config Libraries *\/\r\nGROUP(libgcc.a libc.a libm.a libnosys.a)\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   _reset_init : Entry of reset handler\r\n * \r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(_reset_init)\r\n\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into INTERNAL_FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    __vector_table = .;\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))\r\n    . = ALIGN(4);\r\n  } > VECTORS\r\n\r\n  .cfmprotect :\r\n  {\r\n    . = ALIGN(4);\r\n        KEEP(*(.cfmconfig))     \/* Flash Configuration Field (FCF) *\/\r\n    . = ALIGN(4);\r\n  } > FLASHCFG\r\n\r\n    .text :\r\n    {\r\n        *(.text*)\r\n\r\n        KEEP(*(.init))\r\n        KEEP(*(.fini))\r\n\r\n        \/* .ctors *\/\r\n        *crtbegin.o(.ctors)\r\n        *crtbegin?.o(.ctors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n        *(SORT(.ctors.*))\r\n        *(.ctors)\r\n\r\n        \/* .dtors *\/\r\n        *crtbegin.o(.dtors)\r\n        *crtbegin?.o(.dtors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n        *(SORT(.dtors.*))\r\n        *(.dtors)\r\n\r\n        *(.rodata*)\r\n\r\n        KEEP(*(.eh_frame*))\r\n    } > FLASH\r\n\r\n    .ARM.extab : \r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > FLASH\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx :\r\n    {\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n    __exidx_end = .;\r\n\r\n    __etext = .;\r\n        \r\n    .data : AT (__etext)\r\n    {\r\n        __data_start__ = .;\r\n        *(vtable)\r\n        *(.data*)\r\n\r\n        . = ALIGN(4);\r\n        \/* preinit data *\/\r\n        PROVIDE_HIDDEN (__preinit_array_start = .);\r\n        KEEP(*(.preinit_array))\r\n        PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* init data *\/\r\n        PROVIDE_HIDDEN (__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n\r\n        . = ALIGN(4);\r\n        \/* finit data *\/\r\n        PROVIDE_HIDDEN (__fini_array_start = .);\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        KEEP(*(.fini_array))\r\n        PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* All data end *\/\r\n        __data_end__ = .;\r\n\r\n    } > RAM\r\n\r\n    .bss :\r\n    {\r\n        __bss_start__ = .;\r\n        *(.bss*)\r\n        *(COMMON)\r\n        __bss_end__ = .;\r\n    } > RAM\r\n    \r\n    .heap :\r\n    {\r\n        __end__ = .;\r\n        end = __end__;\r\n        __heap_start = .;\r\n        *(.heap*)\r\n        __heap_end = .;\r\n    } > RAM\r\n\r\n    \/* Set stack top to end of RAM *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - 1k;\r\n    PROVIDE(__stack = __StackTop);\r\n    \r\n    \/* Check if data + heap + stack exceeds RAM limit *\/\r\n    ASSERT(__StackLimit >= __heap_end, \"region RAM overflowed with stack\")\r\n}","old_contents":"\/**************************************************************************\/\r\n\/* Configure memory regions *\/\r\nMEMORY\r\n{\r\n  VECTORS (rx)      : ORIGIN = 0x0,         LENGTH = 0x00c0\r\n  FLASHCFG (rx)     : ORIGIN = 0x00000400,  LENGTH = 0x00000010\r\n  FLASH (rx)        : ORIGIN = 0x00000410,  LENGTH = 128K - 0x410\r\n  RAM  (rwx)        : ORIGIN = 0x1FFFF000,  LENGTH = 16K\r\n}\r\n\r\n\/* Config Libraries *\/\r\nGROUP(libgcc.a libc.a libm.a libnosys.a)\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n * \r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(_reset_init)\r\n\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into INTERNAL_FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    __vector_table = .;\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))\r\n    . = ALIGN(4);\r\n  } > VECTORS\r\n\r\n  .cfmprotect :\r\n  {\r\n    . = ALIGN(4);\r\n        KEEP(*(.cfmconfig))     \/* Flash Configuration Field (FCF) *\/\r\n    . = ALIGN(4);\r\n  } > FLASHCFG\r\n\r\n    .text :\r\n    {\r\n        *(.text*)\r\n\r\n        KEEP(*(.init))\r\n        KEEP(*(.fini))\r\n\r\n        \/* .ctors *\/\r\n        *crtbegin.o(.ctors)\r\n        *crtbegin?.o(.ctors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n        *(SORT(.ctors.*))\r\n        *(.ctors)\r\n\r\n        \/* .dtors *\/\r\n        *crtbegin.o(.dtors)\r\n        *crtbegin?.o(.dtors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n        *(SORT(.dtors.*))\r\n        *(.dtors)\r\n\r\n        *(.rodata*)\r\n\r\n        KEEP(*(.eh_frame*))\r\n    } > FLASH\r\n\r\n    .ARM.extab : \r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > FLASH\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx :\r\n    {\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n    __exidx_end = .;\r\n\r\n    __etext = .;\r\n        \r\n    .data : AT (__etext)\r\n    {\r\n        __data_start__ = .;\r\n        *(vtable)\r\n        *(.data*)\r\n\r\n        . = ALIGN(4);\r\n        \/* preinit data *\/\r\n        PROVIDE_HIDDEN (__preinit_array_start = .);\r\n        KEEP(*(.preinit_array))\r\n        PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* init data *\/\r\n        PROVIDE_HIDDEN (__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n\r\n        . = ALIGN(4);\r\n        \/* finit data *\/\r\n        PROVIDE_HIDDEN (__fini_array_start = .);\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        KEEP(*(.fini_array))\r\n        PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* All data end *\/\r\n        __data_end__ = .;\r\n\r\n    } > RAM\r\n\r\n    .bss :\r\n    {\r\n        __bss_start__ = .;\r\n        *(.bss*)\r\n        *(COMMON)\r\n        __bss_end__ = .;\r\n    } > RAM\r\n    \r\n    .heap :\r\n    {\r\n        __end__ = .;\r\n        end = __end__;\r\n        __heap_start = .;\r\n        *(.heap*)\r\n        __heap_end = .;\r\n    } > RAM\r\n\r\n    \/* Set stack top to end of RAM *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - 1k;\r\n    PROVIDE(__stack = __StackTop);\r\n    \r\n    \/* Check if data + heap + stack exceeds RAM limit *\/\r\n    ASSERT(__StackLimit >= __heap_end, \"region RAM overflowed with stack\")\r\n}","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5fa401fbba7b2ed1f558c0bf951c3dee297d46f3","subject":"Reduce heap and stack","message":"Reduce heap and stack\n","repos":"bigclownlabs\/bc-core-module-sdk,bigclownlabs\/bc-core-module-sdk,bigclownlabs\/bc-core-module-sdk","old_file":"sys\/lkr\/stm32l083cz.ld","new_file":"sys\/lkr\/stm32l083cz.ld","new_contents":"\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20005000;    \/* end of RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x200;  \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 192K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data :\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20005000;    \/* end of RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x400;  \/* required amount of heap  *\/\n_Min_Stack_Size = 0x800; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 192K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data :\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"892adc6e91d15975d622c2b30bd60595653097e2","subject":"nrf52840: remove align instructions from gcc linker for ARM.extab exidx sections","message":"nrf52840: remove align instructions from gcc linker for ARM.extab exidx sections\n","repos":"andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed","old_file":"targets\/TARGET_NORDIC\/TARGET_NRF5x\/TARGET_NRF52\/TARGET_MCU_NRF52840\/device\/TOOLCHAIN_GCC_ARM\/NRF52840.ld","new_file":"targets\/TARGET_NORDIC\/TARGET_NRF5x\/TARGET_NRF52\/TARGET_MCU_NRF52840\/device\/TOOLCHAIN_GCC_ARM\/NRF52840.ld","new_contents":"\/*\n * Copyright (c) 2015 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\n\n\/* Default to no softdevice *\/\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x0\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x100000\n#endif\n\n#if !defined(MBED_RAM_START)\n  #define MBED_RAM_START 0x20000000\n  #define MBED_RAM_SIZE 0x40000\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x800\n#endif\n\n#define MBED_RAM0_START MBED_RAM_START\n#define MBED_RAM0_SIZE  0x100\n\n#define MBED_CRASH_REPORT_RAM_START (MBED_RAM0_START + MBED_RAM0_SIZE)\n#define MBED_CRASH_REPORT_RAM_SIZE  0x100\n\n#define MBED_RAM1_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)\n#define MBED_RAM1_SIZE  (MBED_RAM_SIZE - (MBED_RAM0_SIZE + MBED_CRASH_REPORT_RAM_SIZE))\n\nMEMORY\n{\n  FLASH (rx)     : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  RAM_NVIC (rwx) : ORIGIN = MBED_RAM0_START, LENGTH = MBED_RAM0_SIZE\n  RAM_CRASH_DATA (rwx) : ORIGIN = MBED_CRASH_REPORT_RAM_START, LENGTH = MBED_CRASH_REPORT_RAM_SIZE\n  RAM (rwx)      : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE\n}\n\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with the other linker script that defines memory regions FLASH and RAM.\n * It references the following symbols that must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines the following symbols that the code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.Vectors))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .sdh_soc_observers :\n    {\n        PROVIDE(__start_sdh_soc_observers = .);\n        KEEP(*(SORT(.sdh_soc_observers*)))\n        PROVIDE(__stop_sdh_soc_observers = .);\n    } > FLASH\n\n    .sdh_stack_observers :\n    {\n        PROVIDE(__start_sdh_stack_observers = .);\n        KEEP(*(SORT(.sdh_stack_observers*)))\n        PROVIDE(__stop_sdh_stack_observers = .);\n    } > FLASH\n\n    .sdh_req_observers :\n    {\n        PROVIDE(__start_sdh_req_observers = .);\n        KEEP(*(SORT(.sdh_req_observers*)))\n        PROVIDE(__stop_sdh_req_observers = .);\n    } > FLASH\n\n    .sdh_state_observers :\n    {\n        PROVIDE(__start_sdh_state_observers = .);\n        KEEP(*(SORT(.sdh_state_observers*)))\n        PROVIDE(__stop_sdh_state_observers = .);\n    } > FLASH\n\n    .sdh_ble_observers :\n    {\n        PROVIDE(__start_sdh_ble_observers = .);\n        KEEP(*(SORT(.sdh_ble_observers*)))\n        PROVIDE(__stop_sdh_ble_observers = .);\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(8);\n        PROVIDE(__start_fs_data = .);\n        KEEP(*(.fs_data))\n        PROVIDE(__stop_fs_data = .);\n\n        *(.jcr)\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    __edata = .;\n\n    .nvictable (NOLOAD) :\n    {\n      PROVIDE(__start_nvictable = .);\n      KEEP(*(.nvictable))\n      PROVIDE(__stop_nvictable = .);\n    } > RAM_NVIC\n    \n    .crash_data_ram :\n    {\n      . = ALIGN(8);\n      __CRASH_DATA_RAM__ = .;\n      __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n      KEEP(*(.keep.crash_data_ram))\n      *(.m_crash_data_ram)     \/* This is a user defined section *\/\n      . += MBED_CRASH_REPORT_RAM_SIZE;\n      . = ALIGN(8);\n      __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > RAM_CRASH_DATA\n\n    .noinit (NOLOAD) :\n    {\n      PROVIDE(__start_noinit = .);\n      KEEP(*(.noinit))\n      PROVIDE(__stop_noinit = .);\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n\n        \/* Expand the heap to reach the stack boundary. *\/\n        ASSERT(. <= (ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE), \"heap region overflowed into stack\");\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_start = ADDR(.heap));\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n\n    \/* .stack_dummy section does not contain any symbols. It is only\n     * used for the linker script to calculate the size of stack sections\n     * and assign values to stack symbols later. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*)\n        . = ORIGIN(RAM) + LENGTH(RAM);\n    } > RAM\n\n    \/* Set the stack top to the end of RAM and move down the stack limit by\n     * the size of the stack_dummy section. *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n}\n","old_contents":"\/*\n * Copyright (c) 2015 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\n\n\/* Default to no softdevice *\/\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x0\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x100000\n#endif\n\n#if !defined(MBED_RAM_START)\n  #define MBED_RAM_START 0x20000000\n  #define MBED_RAM_SIZE 0x40000\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x800\n#endif\n\n#define MBED_RAM0_START MBED_RAM_START\n#define MBED_RAM0_SIZE  0x100\n\n#define MBED_CRASH_REPORT_RAM_START (MBED_RAM0_START + MBED_RAM0_SIZE)\n#define MBED_CRASH_REPORT_RAM_SIZE  0x100\n\n#define MBED_RAM1_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)\n#define MBED_RAM1_SIZE  (MBED_RAM_SIZE - (MBED_RAM0_SIZE + MBED_CRASH_REPORT_RAM_SIZE))\n\nMEMORY\n{\n  FLASH (rx)     : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  RAM_NVIC (rwx) : ORIGIN = MBED_RAM0_START, LENGTH = MBED_RAM0_SIZE\n  RAM_CRASH_DATA (rwx) : ORIGIN = MBED_CRASH_REPORT_RAM_START, LENGTH = MBED_CRASH_REPORT_RAM_SIZE\n  RAM (rwx)      : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE\n}\n\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with the other linker script that defines memory regions FLASH and RAM.\n * It references the following symbols that must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines the following symbols that the code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.Vectors))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .sdh_soc_observers :\n    {\n        PROVIDE(__start_sdh_soc_observers = .);\n        KEEP(*(SORT(.sdh_soc_observers*)))\n        PROVIDE(__stop_sdh_soc_observers = .);\n    } > FLASH\n\n    .sdh_stack_observers :\n    {\n        PROVIDE(__start_sdh_stack_observers = .);\n        KEEP(*(SORT(.sdh_stack_observers*)))\n        PROVIDE(__stop_sdh_stack_observers = .);\n    } > FLASH\n\n    .sdh_req_observers :\n    {\n        PROVIDE(__start_sdh_req_observers = .);\n        KEEP(*(SORT(.sdh_req_observers*)))\n        PROVIDE(__stop_sdh_req_observers = .);\n    } > FLASH\n\n    .sdh_state_observers :\n    {\n        PROVIDE(__start_sdh_state_observers = .);\n        KEEP(*(SORT(.sdh_state_observers*)))\n        PROVIDE(__stop_sdh_state_observers = .);\n    } > FLASH\n\n    .sdh_ble_observers :\n    {\n        PROVIDE(__start_sdh_ble_observers = .);\n        KEEP(*(SORT(.sdh_ble_observers*)))\n        PROVIDE(__stop_sdh_ble_observers = .);\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(8);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(8);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(8);\n        PROVIDE(__start_fs_data = .);\n        KEEP(*(.fs_data))\n        PROVIDE(__stop_fs_data = .);\n\n        *(.jcr)\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    __edata = .;\n\n    .nvictable (NOLOAD) :\n    {\n      PROVIDE(__start_nvictable = .);\n      KEEP(*(.nvictable))\n      PROVIDE(__stop_nvictable = .);\n    } > RAM_NVIC\n    \n    .crash_data_ram :\n    {\n      . = ALIGN(8);\n      __CRASH_DATA_RAM__ = .;\n      __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n      KEEP(*(.keep.crash_data_ram))\n      *(.m_crash_data_ram)     \/* This is a user defined section *\/\n      . += MBED_CRASH_REPORT_RAM_SIZE;\n      . = ALIGN(8);\n      __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > RAM_CRASH_DATA\n\n    .noinit (NOLOAD) :\n    {\n      PROVIDE(__start_noinit = .);\n      KEEP(*(.noinit))\n      PROVIDE(__stop_noinit = .);\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n\n        \/* Expand the heap to reach the stack boundary. *\/\n        ASSERT(. <= (ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE), \"heap region overflowed into stack\");\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_start = ADDR(.heap));\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n\n    \/* .stack_dummy section does not contain any symbols. It is only\n     * used for the linker script to calculate the size of stack sections\n     * and assign values to stack symbols later. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*)\n        . = ORIGIN(RAM) + LENGTH(RAM);\n    } > RAM\n\n    \/* Set the stack top to the end of RAM and move down the stack limit by\n     * the size of the stack_dummy section. *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"22ec9c8d76b4278a2fff1b5ba6e1f9b622551307","subject":"added a search directory for libgcc for unix environment","message":"added a search directory for libgcc for unix environment\n\ngit-svn-id: e73c8432560a29173e2a5a19c6413d8f5aa32dee@14 78f6c469-4e3a-0410-bca2-dfd793a85426\n","repos":"samueldotj\/AceOS,samueldotj\/AceOS,samueldotj\/AceOS,samueldotj\/AceOS","old_file":"src\/kernel\/kernel.ld","new_file":"src\/kernel\/kernel.ld","new_contents":"\r\nSEARCH_DIR(\"\/usr\/lib\/gcc\/i686-pc-cygwin\/3.4.4\/\")\r\nSEARCH_DIR(\"\/usr\/lib\/gcc\/i386-redhat-linux\/4.1.1\/\")\r\nkernel_virtual_address =  0x100000;\r\nENTRY (_KernelEntry)\r\nSECTIONS\r\n{\r\n\t.text  kernel_virtual_address :\r\n\t{\r\n\t\t*(.text)\r\n\t}\r\n\t.bss :\r\n    {\r\n\t\t__bss_start__ = . ;\r\n        _sbss = .;\r\n        *(.bss)\r\n        *(COMMON)\r\n\r\n        . = ALIGN(4096);\r\n        _ebss = .;\r\n        __bss_end__ = . ;\r\n\r\n\t}\r\n}\r\n\r\n\r\n\r\n","old_contents":"\r\nSEARCH_DIR(\"\/usr\/lib\/gcc\/i686-pc-cygwin\/3.4.4\/\")\r\nkernel_virtual_address =  0x100000;\r\nENTRY (_KernelEntry)\r\nSECTIONS\r\n{\r\n\t.text  kernel_virtual_address :\r\n\t{\r\n\t\t*(.text)\r\n\t}\r\n\t.bss :\r\n    {\r\n\t\t__bss_start__ = . ;\r\n        _sbss = .;\r\n        *(.bss)\r\n        *(COMMON)\r\n\r\n        . = ALIGN(4096);\r\n        _ebss = .;\r\n        __bss_end__ = . ;\r\n\r\n\t}\r\n}\r\n\r\n\r\n\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"74d086cdd693f3bcbb66e8dd3832cd576ea4ad63","subject":"cpu\/riscv_common: add flash_writable section to linker script","message":"cpu\/riscv_common: add flash_writable section to linker script\n","repos":"OlegHahm\/RIOT,kaspar030\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,ant9000\/RIOT,miri64\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,miri64\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,kYc0o\/RIOT,miri64\/RIOT,miri64\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT","old_file":"cpu\/riscv_common\/ldscripts\/riscv_base.ld","new_file":"cpu\/riscv_common\/ldscripts\/riscv_base.ld","new_contents":"\/*\n * Copyright (C) 2017, 2019   Ken Rabold\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_riscv_common\n * @{\n *\n * @file\n * @brief           Common linker directives for the RISC-V CPU\n *\n * @author          Ken Rabold\n *\n * @}\n *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nPHDRS\n{\n  flash PT_LOAD;\n  ram_init PT_LOAD;\n  ram PT_NULL;\n  tls PT_TLS;\n}\n\nSECTIONS\n{\n  __stack_size     = DEFINED(__stack_size) ? __stack_size : 256;\n\n  \/* Populate information about rom size *\/\n  _srom = ORIGIN(rom);\n  _erom = ORIGIN(rom) + LENGTH(rom);\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash AT>flash :flash\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >flash AT>flash :flash\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >flash AT>flash :flash\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    KEEP (*(SORT(.roxfa.*)))\n  } >flash AT>flash :flash\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash AT>flash :flash\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash AT>flash :flash\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash AT>flash :flash\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash AT>flash :flash\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash AT>flash :flash\n\n  \/*\n   * TLS relocations are offsets relative to the address\n   * of the first TLS symbol. That means we just need to\n   * allocate them all together so that the TLS region\n   * is compact when allocated for each thread.\n   *\/\n\n  \/*\n   * TLS initialization data is loaded into ROM so that\n   * each thread can get its values initialized from there\n   * at startup\n   *\/\n  .tdata :\n  {\n       __tdata_start = .;\n      *(.tdata .tdata.* .gnu.linkonce.td.*)\n      __tdata_end = .;\n  } >flash AT>flash :tls\n  __tdata_source = LOADADDR(.tdata);\n  __tdata_size = SIZEOF(.tdata);\n\n  \/*\n   * TLS zeroed data is relocated as if it immediately followed\n   * the tdata values. However, the linker 'magically' erases the\n   * memory allocation so that no ROM is consumed by this\n   * section\n   *\/\n  .tbss :\n  {\n      *(.tbss .tbss.* .gnu.linkonce.tb.*)\n      *(.tcommon)\n      __tbss_end = .;\n  } >flash : tls\n  __tls_size = __tbss_end - __tdata_start;\n  __tbss_size = __tls_size - __tdata_size;\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash AT>flash :flash\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash :ram_init\n\n  .data          :\n  {\n    *(.ramfunc .ramfunc.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n    KEEP (*(SORT(.xfa.*)))\n  } >ram AT>flash :ram_init\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram AT>ram :ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n  PROVIDE( _sheap = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _eheap = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram AT>ram :ram\n\n  .flash_writable (NOLOAD) : {\n    KEEP(*(SORT(.flash_writable.*)))\n  } > rom\n\n  .end_fw (NOLOAD) : ALIGN(4) {\n    _end_fw = . ;\n  } > rom\n}\n","old_contents":"\/*\n * Copyright (C) 2017, 2019   Ken Rabold\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_riscv_common\n * @{\n *\n * @file\n * @brief           Common linker directives for the RISC-V CPU\n *\n * @author          Ken Rabold\n *\n * @}\n *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nPHDRS\n{\n  flash PT_LOAD;\n  ram_init PT_LOAD;\n  ram PT_NULL;\n  tls PT_TLS;\n}\n\nSECTIONS\n{\n  __stack_size     = DEFINED(__stack_size) ? __stack_size : 256;\n\n  \/* Populate information about rom size *\/\n  _srom = ORIGIN(rom);\n  _erom = ORIGIN(rom) + LENGTH(rom);\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash AT>flash :flash\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >flash AT>flash :flash\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >flash AT>flash :flash\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    KEEP (*(SORT(.roxfa.*)))\n  } >flash AT>flash :flash\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash AT>flash :flash\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash AT>flash :flash\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash AT>flash :flash\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash AT>flash :flash\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash AT>flash :flash\n\n  \/*\n   * TLS relocations are offsets relative to the address\n   * of the first TLS symbol. That means we just need to\n   * allocate them all together so that the TLS region\n   * is compact when allocated for each thread.\n   *\/\n\n  \/*\n   * TLS initialization data is loaded into ROM so that\n   * each thread can get its values initialized from there\n   * at startup\n   *\/\n  .tdata :\n  {\n       __tdata_start = .;\n      *(.tdata .tdata.* .gnu.linkonce.td.*)\n      __tdata_end = .;\n  } >flash AT>flash :tls\n  __tdata_source = LOADADDR(.tdata);\n  __tdata_size = SIZEOF(.tdata);\n\n  \/*\n   * TLS zeroed data is relocated as if it immediately followed\n   * the tdata values. However, the linker 'magically' erases the\n   * memory allocation so that no ROM is consumed by this\n   * section\n   *\/\n  .tbss :\n  {\n      *(.tbss .tbss.* .gnu.linkonce.tb.*)\n      *(.tcommon)\n      __tbss_end = .;\n  } >flash : tls\n  __tls_size = __tbss_end - __tdata_start;\n  __tbss_size = __tls_size - __tdata_size;\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash AT>flash :flash\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash :ram_init\n\n  .data          :\n  {\n    *(.ramfunc .ramfunc.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n    KEEP (*(SORT(.xfa.*)))\n  } >ram AT>flash :ram_init\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram AT>ram :ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n  PROVIDE( _sheap = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _eheap = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram AT>ram :ram\n\n  .end_fw (NOLOAD) : ALIGN(4) {\n    _end_fw = . ;\n  } > rom\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"fc074146478612887ae818aaf67f5751552381af","subject":"Begin and end address of the cibyl strtab","message":"Begin and end address of the cibyl strtab\n\n","repos":"SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl","old_file":"build\/linker-qemu.lds","new_file":"build\/linker-qemu.lds","new_contents":"OUTPUT_ARCH(mips)\nENTRY(__qemu_start)\n\nSECTIONS\n{\n       \t. = 0x80000180;\n       \t.text ALIGN(4)  : { *(.init.exception) }\n       \t. = 0x80010000;\n       \t.text ALIGN(4)  : { *(.init) *(.text) *(.text.*) }\n\n\t\/* Data directly after the text *\/\n       \t.data ALIGN(16) : { *(.data0) *(.data) *(.rodata.str1.4)  *(.rodata.cst4) *(.rodata.cst8) *(.reginfo) }\n       \t.rodata ALIGN(16) : { *(.rodata) *(.rodata.*) }\n\tPROVIDE(__ctors_begin = .);\n\t.ctors ALIGN(4): { *(.ctors) }\n\tPROVIDE(__ctors_end = .);\n\tPROVIDE(__dtors_begin = .);\n\t.dtors ALIGN(4): { *(.dtors) }\n\tPROVIDE(__dtors_end = .);\n       \t.bss  ALIGN(16) : { *(.bss) *(.scommon) *(.sbss) }\n       \tPROVIDE(__edata = .);\n\n\t\/* The string table with the system call names *\/\n\t. = 0xff000000;\n\tPROVIDE(__cibylstrtab_begin = .);\n       \t.cibylstrtab : { *(.cibylstrtab) }\n\tPROVIDE(__cibylstrtab_end = .);\n}\n","old_contents":"OUTPUT_ARCH(mips)\nENTRY(__qemu_start)\n\nSECTIONS\n{\n       \t. = 0x80000180;\n       \t.text ALIGN(4)  : { *(.init.exception) }\n       \t. = 0x80010000;\n       \t.text ALIGN(4)  : { *(.init) *(.text) *(.text.*) }\n\n\t\/* Data directly after the text *\/\n       \t.data ALIGN(16) : { *(.data0) *(.data) *(.rodata.str1.4)  *(.rodata.cst4) *(.rodata.cst8) *(.reginfo) }\n       \t.rodata ALIGN(16) : { *(.rodata) *(.rodata.*) }\n\tPROVIDE(__ctors_begin = .);\n\t.ctors ALIGN(4): { *(.ctors) }\n\tPROVIDE(__ctors_end = .);\n\tPROVIDE(__dtors_begin = .);\n\t.dtors ALIGN(4): { *(.dtors) }\n\tPROVIDE(__dtors_end = .);\n       \t.bss  ALIGN(16) : { *(.bss) *(.scommon) *(.sbss) }\n       \tPROVIDE(__edata = .);\n\n\t\/* The string table with the system call names *\/\n\t. = 0xff000000;\n       \t.cibylstrtab : { *(.cibylstrtab) }\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"48b98214ae3d85589ae0d5774bf57bfcf62f3929","subject":"openthread: enable ot_cli on esp32h2","message":"openthread: enable ot_cli on esp32h2\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/soc\/esp32c3\/ld\/esp32c3.peripherals.ld","new_file":"components\/soc\/esp32c3\/ld\/esp32c3.peripherals.ld","new_contents":"PROVIDE ( UART0 = 0x60000000 );\nPROVIDE ( UART1 = 0x60010000 );\nPROVIDE ( SPIMEM1 = 0x60002000 );\nPROVIDE ( SPIMEM0 = 0x60003000 );\nPROVIDE ( GPIO = 0x60004000 );\nPROVIDE ( SIGMADELTA = 0x60004f00 );\nPROVIDE ( RTCCNTL = 0x60008000 );\nPROVIDE ( RTCIO = 0x60008400 );\nPROVIDE ( HINF = 0x6000B000 );\nPROVIDE ( I2S0  = 0x6002d000 );\nPROVIDE ( I2C0  = 0x60013000 );\nPROVIDE ( UHCI0  = 0x60014000 );\nPROVIDE ( UHCI1  = 0x6000c000 );\nPROVIDE ( HOST = 0x60015000 );\nPROVIDE ( RMT = 0x60016000 );\nPROVIDE ( RMTMEM = 0x60016400 );\nPROVIDE ( SLC = 0x60018000 );\nPROVIDE ( LEDC = 0x60019000 );\nPROVIDE ( TIMERG0 = 0x6001F000 );\nPROVIDE ( TIMERG1 = 0x60020000 );\nPROVIDE ( SYSTIMER = 0x60023000 );\nPROVIDE ( GPSPI2  = 0x60024000 );\nPROVIDE ( GPSPI3  = 0x60025000 );\nPROVIDE ( SYSCON = 0x60026000 );\nPROVIDE ( TWAI   = 0x6002B000 );\nPROVIDE ( GPSPI4 = 0x60037000 );\nPROVIDE ( APB_SARADC = 0x60040000 );\nPROVIDE ( USB_SERIAL_JTAG = 0x60043000 );\nPROVIDE ( GDMA    = 0x6003F000 );\nPROVIDE ( IEEE802154 = 0x60047000 );\n","old_contents":"PROVIDE ( UART0 = 0x60000000 );\nPROVIDE ( UART1 = 0x60010000 );\nPROVIDE ( SPIMEM1 = 0x60002000 );\nPROVIDE ( SPIMEM0 = 0x60003000 );\nPROVIDE ( GPIO = 0x60004000 );\nPROVIDE ( SIGMADELTA = 0x60004f00 );\nPROVIDE ( RTCCNTL = 0x60008000 );\nPROVIDE ( RTCIO = 0x60008400 );\nPROVIDE ( HINF = 0x6000B000 );\nPROVIDE ( I2S0  = 0x6002d000 );\nPROVIDE ( I2C0  = 0x60013000 );\nPROVIDE ( UHCI0  = 0x60014000 );\nPROVIDE ( UHCI1  = 0x6000c000 );\nPROVIDE ( HOST = 0x60015000 );\nPROVIDE ( RMT = 0x60016000 );\nPROVIDE ( RMTMEM = 0x60016400 );\nPROVIDE ( SLC = 0x60018000 );\nPROVIDE ( LEDC = 0x60019000 );\nPROVIDE ( TIMERG0 = 0x6001F000 );\nPROVIDE ( TIMERG1 = 0x60020000 );\nPROVIDE ( SYSTIMER = 0x60023000 );\nPROVIDE ( GPSPI2  = 0x60024000 );\nPROVIDE ( GPSPI3  = 0x60025000 );\nPROVIDE ( SYSCON = 0x60026000 );\nPROVIDE ( TWAI   = 0x6002B000 );\nPROVIDE ( GPSPI4 = 0x60037000 );\nPROVIDE ( APB_SARADC = 0x60040000 );\nPROVIDE ( USB_SERIAL_JTAG = 0x60043000 );\nPROVIDE ( GDMA    = 0x6003F000 );\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e6dfae0fea0153ef6f8f943c23e30b436660f40e","subject":"soc\/intel_adsp: Fix linker warning","message":"soc\/intel_adsp: Fix linker warning\n\nThe linker will emit a warning condition when a section with a\ndeclared alignment doesn't naturally start on that alignment (which\nbegets the question of why the declared alignment syntax exists at\nall...).\n\nDo the alignment for .bss between the sections instead as a simple\nworkaround.\n\nNote that this alignment isn't architecturally required, as current\nZephyr targets don't use the page-aligned pseudo-MMU on this hardware;\nthe only requirement is alignment to the 64 byte cache stride.  It\nshould work to pack .bss tightly.  But when I try that, I get an error\nfrom the rimage tool, which is apparently unprepared for\nnon-4k-aligned sections?\n\nSigned-off-by: Andy Ross <c70f9a6bf6ee0cd69c8af4ce5e6b131945769315@intel.com>\nSigned-off-by: Anas Nashif <0d9952ec84ac43c159f6b7e7ed99a9080c00dd6e@intel.com>\n","repos":"galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v15\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v15\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LPRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LPRAM_BASE,\n\tlen = LPRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n  *\/\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LPRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LPRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LPRAM_BASE,\n\tlen = LPRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n  *\/\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  .bss SEGSTART_UNCACHED (NOLOAD) : ALIGN(4096)\n  {\n    . = ALIGN(4096);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LPRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"212ac0ac634d4779e39a89c50f792cadb4f42bf5","subject":"Rename heap to brk and enlarge size.","message":"Rename heap to brk and enlarge size.\n","repos":"krinkinmu\/auos,krinkinmu\/auos,krinkinmu\/auos,krinkinmu\/auos","old_file":"kernel\/arch\/x86\/boot\/kernel.ld","new_file":"kernel\/arch\/x86\/boot\/kernel.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nPAGE_OFFSET = 0xC0000000;\nPAGE_SIZE   = 0x00001000;\n\nSECTIONS\n{\n\t\/* GRUB will load kernel in memory starting from 1Mb *\/\n\t. = 1M;\n\t.header    : { *(.header) }\n\n\t. += PAGE_OFFSET;\n\t__kernel_begin = .;\n\t.bootstrap : AT(ADDR(.bootstrap) - PAGE_OFFSET) { *(.bootstrap) }\n\n\t.text   : { *(.text)   *(.text.*) }\n\t.rodata : { *(.rodata) *(.rodata.*) }\n\t.data   : { *(.data)   *(.data.*) }\n\n\t. = ALIGN(PAGE_SIZE);\n\t__bss_begin = .;\n\t.bss : { *(.bss) }\n\t. = ALIGN(PAGE_SIZE);\n\t__heap_begin = .;\n\t.brk : { . += 1M; }\n\t__heap_end = .;\n\t__bss_end = .;\n\t__kernel_end = .;\n\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\t.debug_info    0 : { *(.debug_info) }\n\t.debug_abbrev  0 : { *(.debug_abbrev) }\n\t.debug_line    0 : { *(.debug_line) }\n        .debug_str     0 : { *(.debug_str) }\n\n\t\/DISCARD\/ : { *(.eh_frame .note.* .comment) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nPAGE_OFFSET = 0xC0000000;\nPAGE_SIZE   = 0x00001000;\n\nSECTIONS\n{\n\t\/* GRUB will load kernel in memory starting from 1Mb *\/\n\t. = 1M;\n\t.header    : { *(.header) }\n\n\t. += PAGE_OFFSET;\n\t__kernel_begin = .;\n\t.bootstrap : AT(ADDR(.bootstrap) - PAGE_OFFSET) { *(.bootstrap) }\n\n\t.text   : { *(.text)   *(.text.*) }\n\t.rodata : { *(.rodata) *(.rodata.*) }\n\t.data   : { *(.data)   *(.data.*) }\n\n\t. = ALIGN(PAGE_SIZE);\n\t__bss_begin = .;\n\t.bss : { *(.bss) }\n\t__bss_end = .;\n\n\t. = ALIGN(PAGE_SIZE);\n\t__heap_begin = .;\n\t.heap : { . += 64 * 1024; }\n\t__heap_end = .;\n\n\t__kernel_end = .;\n\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\t.debug_info    0 : { *(.debug_info) }\n\t.debug_abbrev  0 : { *(.debug_abbrev) }\n\t.debug_line    0 : { *(.debug_line) }\n        .debug_str     0 : { *(.debug_str) }\n\n\t\/DISCARD\/ : { *(.eh_frame .note.* .comment) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"566c4663439c726ec3eb22ca8f985d6cc552f9e8","subject":"soc: intel_adsp\/cavs_v20: correct linker syntax for old binutils","message":"soc: intel_adsp\/cavs_v20: correct linker syntax for old binutils\n\nApplying similar changes to cavs_v20 as in commit\n8bc4539cec63fd747c923e79d1aa60221e4961ce:\n\n  Older binutils, like the (nine-year-old!) 2.23 version that powers\n  many Cadence XCC toolchains, happen not to support the \"~\" operator to\n  perform bitwise negation.  And they generate an absolutely hilarious\n  series of inscrutable error messages when they try to tell you this\n  fairly simple fact.\n\n  Just fold it into the constant.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v20\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v20\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n * (Note clumsy syntax because XCC doesn't understand the \"~\" operator)\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & 0xdfffffff) \/* == ~0x20000000 *\/\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs20_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs20_adsp);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .cached :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n\n  . = SEGSTART_UNCACHED;\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  .bss (NOLOAD) : ALIGN(4096)\n  {\n    . = ALIGN(4096);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n  . = SEGSTART_UNCACHED;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs20_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs20_adsp);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .cached :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n\n  . = SEGSTART_UNCACHED;\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  .bss (NOLOAD) : ALIGN(4096)\n  {\n    . = ALIGN(4096);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n  . = SEGSTART_UNCACHED;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"57513948c9484ad2f22982290dac6d6b5440766a","subject":"Move stack near BSS so it doesn't take up space in the .bin","message":"Move stack near BSS so it doesn't take up space in the .bin\n","repos":"arurke\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki","old_file":"cpu\/mc1322x\/mc1322x.lds","new_file":"cpu\/mc1322x\/mc1322x.lds","new_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(\"=\/usr\/local\/lib\"); SEARCH_DIR(\"=\/lib\"); SEARCH_DIR(\"=\/usr\/lib\");\nSECTIONS\n{\n\nSYS_STACK_SIZE = 1024;\nIRQ_STACK_SIZE = 256;\nFIQ_STACK_SIZE = 256;\nSVC_STACK_SIZE = 256;\nABT_STACK_SIZE = 16;\nUND_STACK_SIZE = 16;\nHEAP_SIZE = 1024;\n\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x00400000); . = 0x00400000;\n  .text           :\n  {\n    *start*.o\t(.text)\n    *(.irq)\t\t\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  } =0\n\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n      *(.rela.ctors)\n      *(.rela.dtors)\n      *(.rela.got)\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n    }\n  .rel.plt        : { *(.rel.plt) }\n  .rela.plt       : { *(.rela.plt) }\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0\n  .plt            : { *(.plt) }\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n\n\/*  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); *\/\n\n\t. = ALIGN(4);\n\t. = DATA_SEGMENT_ALIGN(4,4); \n\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n  .init_array     :\n  {\n     PROVIDE_HIDDEN (__init_array_start = .);\n     KEEP (*(SORT(.init_array.*)))\n     KEEP (*(.init_array))\n     PROVIDE_HIDDEN (__init_array_end = .);\n  }\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .jcr            : { KEEP (*(.jcr)) } \n  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }\n  .dynamic        : { *(.dynamic) } \n  . = DATA_SEGMENT_RELRO_END (0, .);  \n  .got            : { *(.got.plt) *(.got) }\n  .data           :\n  {\n    __data_start = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .data1          : { *(.data1) }\n  _edata = .; PROVIDE (edata = .);\n\n\t.stack : {\n\t\t__stack_start__ = . ;\n\n\t\t. += IRQ_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__irq_stack_top__ = . ;\n\n\t\t. += FIQ_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__fiq_stack_top__ = . ;\n\n\t\t. += SVC_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__svc_stack_top__ = . ;\n\n\t\t. += ABT_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__abt_stack_top__ = . ;\n\n\t\t. += UND_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__und_stack_top__ = . ;\n\n\t\t. += SYS_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__sys_stack_top__ = . ;\n\n\t\t__stack_end__ = .;\n\t}\n\n\n  __bss_start = .;\n  __bss_start__ = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.\n      FIXME: Why do we need it? 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We want to adjust up to\n     the same address within the page on the next page up.  *\/\n\n\/*  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); *\/\n\n\t. = ALIGN(4);\n\t. = DATA_SEGMENT_ALIGN(4,4); \n\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n  .init_array     :\n  {\n     PROVIDE_HIDDEN (__init_array_start = .);\n     KEEP (*(SORT(.init_array.*)))\n     KEEP (*(.init_array))\n     PROVIDE_HIDDEN (__init_array_end = .);\n  }\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .jcr            : { KEEP (*(.jcr)) } \n  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }\n  .dynamic        : { *(.dynamic) } \n  . = DATA_SEGMENT_RELRO_END (0, .);  \n  .got            : { *(.got.plt) *(.got) }\n  .data           :\n  {\n    __data_start = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .data1          : { *(.data1) }\n  _edata = .; PROVIDE (edata = .);\n  __bss_start = .;\n  __bss_start__ = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.\n      FIXME: Why do we need it? When there is no .bss section, we don't\n      pad the .data section.  *\/\n   . = ALIGN(. != 0 ? 32 \/ 8 : 1);\n  }\n  _bss_end__ = . ; __bss_end__ = . ;\n  . = ALIGN(32 \/ 8);\n\n   .heap : {\n                __heap_start__ = . ;\n                *(.heap);\n                . += HEAP_SIZE;\n                . = ALIGN (4);\n                __heap_end__ = . ;\n   }\n\n\n  . = ALIGN(32 \/ 8);\n  __end__ = . ;\n  _end = .; PROVIDE (end = .);\n  . = DATA_SEGMENT_END (.);\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"5d8591bc0fbaeb6deda6ee478577e9c4d9b10c2b","subject":"module: set ksymtab\/kcrctab* section addresses to 0x0","message":"module: set ksymtab\/kcrctab* section addresses to 0x0\n\nThese __ksymtab*\/__kcrctab* sections currently have non-zero addresses.\nNon-zero section addresses in a relocatable ELF confuse GDB and it ends\nup not relocating all symbols when add-symbol-file is used on modules\nwhich have exports.  The kernel's module loader does not care about\nthese addresses, so let's just set them to zero.\n\n Before:\n\n  $ readelf -S lib\/notifier-error-inject.ko   | grep 'Name\\| __ksymtab_gpl'\n    [Nr] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al\n    [ 8] __ksymtab_gpl     PROGBITS        0000000c 0001b4 000010 00   A  0   0  4\n\n  (gdb) add-symbol-file lib\/notifier-error-inject.ko 0x500000 -s .bss 0x700000\n  add symbol table from file \"lib\/notifier-error-inject.ko\" at\n     .text_addr = 0x500000\n     .bss_addr = 0x700000\n  (gdb) p &notifier_err_inject_dir\n  $3 = (struct dentry **) 0x0\n\n After:\n\n  $ readelf -S lib\/notifier-error-inject.ko   | grep 'Name\\| __ksymtab_gpl'\n    [Nr] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al\n    [ 8] __ksymtab_gpl     PROGBITS        00000000 0001b4 000010 00   A  0   0  4\n\n  (gdb) add-symbol-file lib\/notifier-error-inject.ko 0x500000 -s .bss 0x700000\n  add symbol table from file \"lib\/notifier-error-inject.ko\" at\n     .text_addr = 0x500000\n     .bss_addr = 0x700000\n  (gdb) p &notifier_err_inject_dir\n  $3 = (struct dentry **) 0x700000\n\nSigned-off-by: Rabin Vincent <b8c38523cce7640aaeed4045bf245272d3b467e3@axis.com>\nSigned-off-by: Rusty Russell <df9728c9e5104131c08c7adb03af425394842596@rustcorp.com.au>\n","repos":"KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs","old_file":"scripts\/module-common.lds","new_file":"scripts\/module-common.lds","new_contents":"","old_contents":"","returncode":0,"stderr":"unknown","license":"mit","lang":"Linker Script"}
{"commit":"a1ccc149f9c61f8871ff450321aabe6e1451116b","subject":"deleted unnecessary linker script","message":"deleted unnecessary linker script","repos":"Lowl3v3l\/myos_64","old_file":"arch\/x86_64\/link.ld","new_file":"arch\/x86_64\/link.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"unknown","license":"mit","lang":"Linker Script"}
{"commit":"8afc52e7bc8d39cd80bdeec03b42f706bc40ee0a","subject":"add some explicit debug sections to linker script","message":"add some explicit debug sections to linker script\n","repos":"chrisy\/freertos-test,chrisy\/freertos-test,chrisy\/freertos-test","old_file":"src\/platform\/STM32F103ZE.ld","new_file":"src\/platform\/STM32F103ZE.ld","new_contents":"\/** Linker script for STM32F103ZE\n * vim: set softtabstop=4 shiftwidth=4 tabstop=4 expandtab:\n * \\file src\/platform\/STM32F1032E.ld\n *\n * This file is distributed under the terms of the MIT License.\n * See the LICENSE file at the top of this tree, or if it is missing a copy can\n * be found at http:\/\/opensource.org\/licenses\/MIT\n *\/\n\nMEMORY\n{\n    flash (rx)  : ORIGIN = 0x08000000, LENGTH = 512K\n    ram   (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\n    stack (rw)  : ORIGIN = 0x20010000, LENGTH = 0K\n}\n\nENTRY(_crt0_init)\n\nSECTIONS\n{\n    . = 0;\n\n    .nvic_vector :\n    {\n        *(vectors)  \/* Vector table *\/\n    } >flash\n\n    .info :\n    {\n        *(info)     \/* Text info *\/\n    } >flash\n\n    .text :\n    {\n        *(.text)    \/* Program code *\/\n        *(.text.*)\n        *(.rodata)  \/* Read only data *\/\n        *(.rodata.*)\n        _mm_datai_start = .;\n    } >flash\n\n    .data :\n    {\n        . = ALIGN(4);\n        _mm_data_start = .;\n        *(.data)    \/* Data memory *\/\n        *(.data.*)\n        _mm_data_end = .;\n    } >ram AT >flash\n\n    .data_init :\n    {\n        . = ALIGN(4);\n        _mm_datai_end = .;\n    } >flash\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _mm_bss_start = .;\n        *(.bss)     \/* BSS is zero-filled at runtime *\/\n        *(.bss.*)\n        *(COMMON)\n        _mm_bss_end = .;\n    } >ram\n\n    .heap :\n    {\n        . = ALIGN(4);\n        _mm_heap_start = .;\n    } >ram\n\n    .stack :\n    {\n        _mm_heap_end = .;\n        _mm_stack_top = .;\n    } >stack\n\n      \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end ) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  \/* DWARF Extension.  *\/\n  .debug_macro    0 : { *(.debug_macro) }\n\n}\n\n","old_contents":"\/** Linker script for STM32F103ZE\n * vim: set softtabstop=4 shiftwidth=4 tabstop=4 expandtab:\n * \\file src\/platform\/STM32F1032E.ld\n *\n * This file is distributed under the terms of the MIT License.\n * See the LICENSE file at the top of this tree, or if it is missing a copy can\n * be found at http:\/\/opensource.org\/licenses\/MIT\n *\/\n\nMEMORY\n{\n    flash (rx)  : ORIGIN = 0x08000000, LENGTH = 512K\n    ram   (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\n    stack (rw)  : ORIGIN = 0x20010000, LENGTH = 0K\n}\n\nENTRY(_crt0_init)\n\nSECTIONS\n{\n    . = 0;\n\n    .nvic_vector :\n    {\n        *(vectors)  \/* Vector table *\/\n    } >flash\n\n    .info :\n    {\n        *(info)     \/* Text info *\/\n    } >flash\n\n    .text :\n    {\n        *(.text)    \/* Program code *\/\n        *(.text.*)\n        *(.rodata)  \/* Read only data *\/\n        *(.rodata.*)\n        _mm_datai_start = .;\n    } >flash\n\n    .data :\n    {\n        . = ALIGN(4);\n        _mm_data_start = .;\n        *(.data)    \/* Data memory *\/\n        *(.data.*)\n        _mm_data_end = .;\n    } >ram AT >flash\n\n    .data_init :\n    {\n        . = ALIGN(4);\n        _mm_datai_end = .;\n    } >flash\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _mm_bss_start = .;\n        *(.bss)     \/* BSS is zero-filled at runtime *\/\n        *(.bss.*)\n        *(COMMON)\n        _mm_bss_end = .;\n    } >ram\n\n    .heap :\n    {\n        . = ALIGN(4);\n        _mm_heap_start = .;\n    } >ram\n\n    .stack :\n    {\n        _mm_heap_end = .;\n        _mm_stack_top = .;\n    } >stack\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b0de416682d74ae35fb68ad5be3021694260d36a","subject":"x86: Adjust UEFI header size","message":"x86: Adjust UEFI header size\n\nThe UEFI GenFw program inserts headers ahead of the code in the UEFI\nbinary.  The linker script adjusts the starting address of the .text\nsection to account for that.  This prevents the symbols from being\nperturbed.  This patch accounts for a recent change in the size of the\nheaders added by the GenFw program.\n","repos":"arurke\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki","old_file":"cpu\/x86\/quarkX1000.ld","new_file":"cpu\/x86\/quarkX1000.ld","new_contents":"\/*\n * Copyright (C) 2015, Intel Corporation. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\nOUTPUT_FORMAT(\"elf32-i386\")\n\nENTRY(start)\n\nSECTIONS {\n    \/*\n       OS-Dev Wiki says it is common for kernels to start at 1M. Addresses before that\n       are used by BIOS\/EFI, the bootloader and memory-mapped I\/O.\n\n       The UEFI GenFw program inserts a 0x220-byte offset between the image base and\n       the .text section.  We add that same offset here to align the symbols in the\n       UEFI DLL with those in the final UEFI binary to make debugging easier.  We also\n       apply 32-byte alignments to sections rather than more conventional 4K-byte\n       alignments to avoid symbols being shifted from the intermediate DLL to the\n       final UEFI image as would occur if the GenFw program shifted the .text section\n       from a higher, 4K-aligned offset to the 0x220-byte offset from the image base.\n       Such shifting may make debugging more difficult by preventing the DLL from\n       being a directly-useful source of symbol information.  The debugging symbols\n       are not included in the final UEFI image.  The GenFw program uses a minimum\n       section alignment of 32 bytes, so smaller alignment granularities may also\n       result in symbol perturbation.\n    *\/\n    . = 1M + 0x220;\n\n    .text ALIGN (32) :\n    {\n        KEEP(*(.multiboot))\n        *(.text*)\n    }\n\n    .rodata ALIGN (32) :\n    {\n        *(.rodata*)\n\n        _sdata_shared_isr = .;\n        KEEP(*(.shared_isr_data*))\n        _edata_shared_isr = .;\n    }\n\n    .data ALIGN (32) :\n    {\n        *(.data*)\n    }\n\n    .bss ALIGN (32) :\n    {\n        *(COMMON)\n        *(.bss*)\n    }\n}\n","old_contents":"\/*\n * Copyright (C) 2015, Intel Corporation. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\nOUTPUT_FORMAT(\"elf32-i386\")\n\nENTRY(start)\n\nSECTIONS {\n    \/*\n       OS-Dev Wiki says it is common for kernels to start at 1M. Addresses before that\n       are used by BIOS\/EFI, the bootloader and memory-mapped I\/O.\n\n       The UEFI GenFw program inserts a 0x240-byte offset between the image base and\n       the .text section.  We add that same offset here to align the symbols in the\n       UEFI DLL with those in the final UEFI binary to make debugging easier.  We also\n       apply 32-byte alignments to sections rather than more conventional 4K-byte\n       alignments to avoid symbols being shifted from the intermediate DLL to the\n       final UEFI image as would occur if the GenFw program shifted the .text section\n       from a higher, 4K-aligned offset to the 0x240-byte offset from the image base.\n       Such shifting may make debugging more difficult by preventing the DLL from\n       being a directly-useful source of symbol information.  The debugging symbols\n       are not included in the final UEFI image.  The GenFw program uses a minimum\n       section alignment of 32 bytes, so smaller alignment granularities may also\n       result in symbol perturbation.\n    *\/\n    . = 1M + 0x240;\n\n    .text ALIGN (32) :\n    {\n        KEEP(*(.multiboot))\n        *(.text*)\n    }\n\n    .rodata ALIGN (32) :\n    {\n        *(.rodata*)\n\n        _sdata_shared_isr = .;\n        KEEP(*(.shared_isr_data*))\n        _edata_shared_isr = .;\n    }\n\n    .data ALIGN (32) :\n    {\n        *(.data*)\n    }\n\n    .bss ALIGN (32) :\n    {\n        *(COMMON)\n        *(.bss*)\n    }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"18630efa6c1b4c587905afec6e1ee5effc307347","subject":"align kernel to 2MB, include section .text.startup","message":"align kernel to 2MB, include section .text.startup\n","repos":"stlankes\/HermitCore,RWTH-OS\/HermitCore,stlankes\/HermitCore,stlankes\/HermitCore,stlankes\/HermitCore,RWTH-OS\/HermitCore,stlankes\/HermitCore,RWTH-OS\/HermitCore,RWTH-OS\/HermitCore,RWTH-OS\/HermitCore,RWTH-OS\/HermitCore,stlankes\/HermitCore","old_file":"hermit\/link.ld","new_file":"hermit\/link.ld","new_contents":"OUTPUT_FORMAT(\"elf64-x86-64\")\nOUTPUT_ARCH(\"i386:x86-64\")\nENTRY(start)\nphys = (2 << 20);\n\nSECTIONS\n{\n  kernel_start =  phys; \n  .mboot phys : AT(ADDR(.mboot)) {\n    *(.mboot)\n    . = ALIGN((1 << 12));\n    *(.kmsg)\n  }\n  .text ALIGN(4096) : AT(ADDR(.text)) {\n    *(.text)\n    *(.text.startup)\n  }\n  .rodata ALIGN(4096) : AT(ADDR(.rodata)) {\n    *(.rodata)\n    *(.rodata.*)\n  }\n  .data ALIGN(4096) : AT(ADDR(.data)) {\n    *(.data)\n  }\n  .bss ALIGN(4096) : AT(ADDR(.bss)) {\n    bss_start = .;\n    *(.bss)\n  }\n  bss_end = .;\n  kernel_end = .;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf64-x86-64\")\nOUTPUT_ARCH(\"i386:x86-64\")\nENTRY(start)\nphys = 0x1400000;\n\nSECTIONS\n{\n  kernel_start =  phys; \n  .mboot phys : AT(ADDR(.mboot)) {\n    *(.mboot)\n    . = ALIGN((1 << 12));\n    *(.kmsg)\n  }\n  .text ALIGN(4096) : AT(ADDR(.text)) {\n    *(.text)\n  }\n  .rodata ALIGN(4096) : AT(ADDR(.rodata)) {\n    *(.rodata)\n    *(.rodata.*)\n  }\n  .data ALIGN(4096) : AT(ADDR(.data)) {\n    *(.data)\n  }\n  .bss ALIGN(4096) : AT(ADDR(.bss)) {\n    bss_start = .;\n    *(.bss)\n  }\n  bss_end = .;\n  kernel_end = .;\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"20edfb73cbe5223e15216b0a7d9d22fea8525dab","subject":"Bump code size to accommodate TFLM updates.","message":"Bump code size to accommodate TFLM updates.\n\nSigned-off-by: Tim Callahan <ea16a3c075a6a229c9a452aa4faba7441b41c040@google.com>\n","repos":"google\/CFU-Playground,google\/CFU-Playground,google\/CFU-Playground,google\/CFU-Playground","old_file":"common\/_hps\/hps\/ld\/linker.ld","new_file":"common\/_hps\/hps\/ld\/linker.ld","new_contents":"INCLUDE output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE regions.ld\n\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(SORT(.text.start))\n\t\t*(SORT(.text))\n\t\t*(SORT(.stub))\n\t\t*(SORT(.text.*))\n\t\t*(SORT(.gnu.linkonce.t.*))\n\t\t_etext = .;\n\t} > rom\n\n\t.rodata :\n\t{\n\t\t\/*\n\t\t * Align models and large chunks of data into a constant position\n\t\t *\/\n\t\t. = _ftext + 0x84000;\n\t\t_frodata = .;\n\t\tsrc\/models\/*\/*(SORT(.rodata.*))\n\t\tsrc\/conv2d_??.o(SORT(.rodata.*))  \/* specific to hps_accel *\/\n\t\t. = ALIGN(4096);\n\t\t*(SORT(.rodata))\n\t\t*(SORT(.rodata.*))\n\t\t*(SORT(.gnu.linkonce.r.*))\n\t\t*(SORT(.rodata1))\n\t\t*(SORT(.srodata))\n\t\t*(SORT(.srodata.*))\n\t\t. = ALIGN(8);\n\t\t_erodata = .;\n\t} > rom\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(8);\n\t\t_fdata = .;\n\t\t*(SORT(.data))\n\t\t*(SORT(.data.*))\n\t\t*(SORT(.gnu.linkonce.d.*))\n\t\t*(SORT(.data1))\n\t\t*(SORT(.ramtext))\n\t\t*(SORT(.ramtext.*))\n\t\t_gp = ALIGN(16);\n\t\t*(SORT(.sdata))\n\t\t*(SORT(.sdata.*))\n\t\t*(SORT(.gnu.linkonce.s.*))\n\t\t*(SORT(.sdata2))\n\t\t*(SORT(.sdata2.*))\n\t\t_edata = ALIGN(16); \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss : AT (ADDR(.data) + SIZEOF (.data))\n\t{\n\t\t. = ALIGN(16);\n\t\t_fbss = .;\n\t\t*(SORT(.dynsbss))\n\t\t*(SORT(.sbss))\n\t\t*(SORT(.sbss.*))\n\t\t*(SORT(.gnu.linkonce.sb.*))\n\t\t*(SORT(.scommon))\n\t\t*(SORT(.dynbss))\n\t\t*(SORT(.bss))\n\t\t*(SORT(.bss.*))\n\t\t*(SORT(.gnu.linkonce.b.*))\n\t\t*(SORT(COMMON))\n\t\t. = ALIGN(8);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n\n        .arena (NOLOAD) :\n        {\n                _farena = .;\n                *(.arena)\n                _earena = .;\n        } > arena\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","old_contents":"INCLUDE output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE regions.ld\n\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(SORT(.text.start))\n\t\t*(SORT(.text))\n\t\t*(SORT(.stub))\n\t\t*(SORT(.text.*))\n\t\t*(SORT(.gnu.linkonce.t.*))\n\t\t_etext = .;\n\t} > rom\n\n\t.rodata :\n\t{\n\t\t\/*\n\t\t * Align models and large chunks of data into a constant position\n\t\t *\/\n\t\t. = _ftext + 0x81800;\n\t\t_frodata = .;\n\t\tsrc\/models\/*\/*(SORT(.rodata.*))\n\t\tsrc\/conv2d_??.o(SORT(.rodata.*))  \/* specific to hps_accel *\/\n\t\t. = ALIGN(4096);\n\t\t*(SORT(.rodata))\n\t\t*(SORT(.rodata.*))\n\t\t*(SORT(.gnu.linkonce.r.*))\n\t\t*(SORT(.rodata1))\n\t\t*(SORT(.srodata))\n\t\t*(SORT(.srodata.*))\n\t\t. = ALIGN(8);\n\t\t_erodata = .;\n\t} > rom\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(8);\n\t\t_fdata = .;\n\t\t*(SORT(.data))\n\t\t*(SORT(.data.*))\n\t\t*(SORT(.gnu.linkonce.d.*))\n\t\t*(SORT(.data1))\n\t\t*(SORT(.ramtext))\n\t\t*(SORT(.ramtext.*))\n\t\t_gp = ALIGN(16);\n\t\t*(SORT(.sdata))\n\t\t*(SORT(.sdata.*))\n\t\t*(SORT(.gnu.linkonce.s.*))\n\t\t*(SORT(.sdata2))\n\t\t*(SORT(.sdata2.*))\n\t\t_edata = ALIGN(16); \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss : AT (ADDR(.data) + SIZEOF (.data))\n\t{\n\t\t. = ALIGN(16);\n\t\t_fbss = .;\n\t\t*(SORT(.dynsbss))\n\t\t*(SORT(.sbss))\n\t\t*(SORT(.sbss.*))\n\t\t*(SORT(.gnu.linkonce.sb.*))\n\t\t*(SORT(.scommon))\n\t\t*(SORT(.dynbss))\n\t\t*(SORT(.bss))\n\t\t*(SORT(.bss.*))\n\t\t*(SORT(.gnu.linkonce.b.*))\n\t\t*(SORT(COMMON))\n\t\t. = ALIGN(8);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n\n        .arena (NOLOAD) :\n        {\n                _farena = .;\n                *(.arena)\n                _earena = .;\n        } > arena\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f470efa1134733a1a3f9dfaa3d8b24aff40600c6","subject":"Add an sbss section to the linker script","message":"Add an sbss section to the linker script","repos":"ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme","old_file":"orex.ld","new_file":"orex.ld","new_contents":"ENTRY (main)\n\nMEMORY\n{\n\tram : ORIGIN = 0x00218000, LENGTH = 29M\n\trom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n\t.data : \/* Initialized data. *\/\n\t{\n\t\t_DataStart = . ;\n\t\t*(.data)\n\t\t_DataEnd = . ;\n\t} >ram\n\n\t.bss : \/* Uninitialized data. *\/\n\t{\n\t\t_BssStart = . ;\n\t\t*(.bss)\n\t\t*(.sbss)\n\t\t_BssEnd = . ;\n\t} >ram\n\n\t.text : \/* The actual instructions. *\/\n\t{\n\t\t*(.text)\n\t\t*(.got)\n\t\t*(.got.plt)\n\t\t*(.rodata)\n\t\t*(.rodata.str1.4)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t} >ram\n}\n","old_contents":"ENTRY (main)\n\nMEMORY\n{\n\tram : ORIGIN = 0x00218000, LENGTH = 29M\n\trom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n\t.data : \/* Initialized data. *\/\n\t{\n\t\t_DataStart = . ;\n\t\t*(.data)\n\t\t_DataEnd = . ;\n\t} >ram\n\n\t.bss : \/* Uninitialized data. *\/\n\t{\n\t\t_BssStart = . ;\n\t\t*(.bss)\n\t\t_BssEnd = . ;\n\t} >ram\n\n\t.text : \/* The actual instructions. *\/\n\t{\n\t\t*(.text)\n\t\t*(.got)\n\t\t*(.got.plt)\n\t\t*(.rodata)\n\t\t*(.rodata.str1.4)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t} >ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"d2ea3e715dd4a859e4977746cd8c89625c698991","subject":"soc: esp32: linker: exclude smp source from rom area","message":"soc: esp32: linker: exclude smp source from rom area\n\nSMP support might not work if esp_mp.c initialization code\nis placed in ROM area. This fix that scenario.\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg\n#define RAMABLE_REGION_1 dram0_1_seg\n#define RODATA_REGION drom0_0_seg\n#define IRAM_REGION iram0_0_seg\n#define FLASH_CODE_REGION irom0_0_seg\n\n#define ROMABLE_REGION ROM\n\n#ifdef CONFIG_FLASH_SIZE\n#define ROM_SIZE CONFIG_FLASH_SIZE\n#else\n#define ROM_SIZE 0x400000\n#endif\n\n#ifdef CONFIG_BOOTLOADER_ESP_IDF\n#define IROM_SEG_ORG 0x400D0020\n#define IROM_SEG_LEN 0x330000-0x20\n#define IROM_SEG_ALIGN 0x4\n#else\n#define IROM_SEG_ORG 0x400D0000\n#define IROM_SEG_LEN 0x330000\n#define IROM_SEG_ALIGN 0x10000\n#endif\n\nMEMORY\n{\n  mcuboot_hdr (RX): org = 0x0, len = 0x20\n  metadata (RX): org = 0x20, len = 0x20\n  ROM (RX): org = 0x40, len = ROM_SIZE - 0x40\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE5230, len = 0x1BCB0 - 0xEE0 \/* skip data for APP CPU initialization usage *\/\n\n  \/* DROM is the first segment placed in generated binary.\n   * MCUboot binary for ESP32 has image header of 0x20 bytes.\n   * Additional load header of 0x20 bytes are appended to the image.\n   * Hence, an offset of 0x40 is added to DROM segment origin.\n   *\/\n  drom0_0_seg(R): org = 0x3F400040, len = 0x400000 - 0x40\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n  \/* Reserve space for MCUboot header in the binary *\/\n  .mcuboot_header :\n  {\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n  } > mcuboot_hdr\n  .metadata :\n  {\n    \/* Magic byte for load header *\/\n    LONG(0xace637d3)\n\n    \/* Application entry point address *\/\n    KEEP(*(.entry_addr))\n\n    \/* IRAM metadata:\n     * - Destination address (VMA) for IRAM region\n     * - Flash offset (LMA) for start of IRAM region\n     * - Size of IRAM region\n     *\/\n\n    LONG(ADDR(\".iram0.vectors\"))\n    LONG(LOADADDR(\".iram0.vectors\"))\n    LONG(LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - LOADADDR(\".iram0.vectors\"))\n\n    \/* DRAM metadata:\n     * - Destination address (VMA) for DRAM region\n     * - Flash offset (LMA) for start of DRAM region\n     * - Size of DRAM region\n     *\/\n\n    LONG(ADDR(\".dram0.data\"))\n    LONG(LOADADDR(\".dram0.data\"))\n    LONG(LOADADDR(\".dummy.dram.data\") + SIZEOF(\".dummy.dram.data\") - LOADADDR(\".dram0.data\"))\n  } > metadata\n\n#include <linker\/rel-sections.ld>\n  _image_drom_start = LOADADDR(_RODATA_SECTION_NAME);\n  _image_drom_size = LOADADDR(_RODATA_SECTION_NAME) + SIZEOF(_RODATA_SECTION_NAME) - _image_drom_start;\n  _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);\n\n  \/* NOTE: .rodata section should be the first section in the linker script and no\n   * other section should appear before .rodata section. This is the requirement\n   * to align ROM section to 64K page offset.\n   * Adding .rodata as first section helps to reduce size of generated binary by\n   * few kBs.\n   *\/\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    . = ALIGN(4);\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.*) .rodata)\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.*) .rodata.*)\n\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)\n\n  _image_dram_start = LOADADDR(\".dram0.data\");\n  _image_dram_size = LOADADDR(\".dummy.dram.data\") + SIZEOF(\".dummy.dram.data\") - _image_dram_start;\n  _image_dram_vaddr = ADDR(\".dram0.data\");\n\n  #include <snippets-sections.ld>\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libzephyr.a:loader.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    . = ALIGN(4);\n    _dram_data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  #pragma push_macro(\"GROUP_ROM_LINK_IN\")\n  #pragma push_macro(\"ITERABLE_SECTION_ROM\")\n  #undef GROUP_ROM_LINK_IN\n  #undef ITERABLE_SECTION_ROM\n  #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN\n  #define ITERABLE_SECTION_ROM(x,y)\n  #include <linker\/common-rom.ld>\n  #pragma pop_macro(\"GROUP_ROM_LINK_IN\")\n  #pragma pop_macro(\"ITERABLE_SECTION_ROM\")\n\n  #include <snippets-data-sections.ld>\n  #include <linker\/common-ram.ld>\n  #include <snippets-ram-sections.ld>\n\n  __shell_root_cmds_start = __esp_shell_root_cmds_start;\n  __shell_root_cmds_end = __esp_shell_root_cmds_end;\n\n  .dummy.dram.data :\n  {\n    . = ALIGN(4);\n    #include <snippets-rwdata.ld>\n    . = ALIGN(4);\n    _data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  _image_iram_start = LOADADDR(\".iram0.vectors\");\n  _image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start;\n  _image_iram_vaddr = ADDR(\".iram0.vectors\");\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:loader.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(rtc_slow_seg)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    \/* Buffer for system heap should be placed in dram0_0_seg *\/\n    *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap)\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(.noinit.*)\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n  _image_irom_start = LOADADDR(\".flash.text\");\n  _image_irom_size = LOADADDR(\".flash.text\") + SIZEOF(\".flash.text\") - _image_irom_start;\n  _image_irom_vaddr = ADDR(\".flash.text\");\n\n  .flash.text : ALIGN(IROM_SEG_ALIGN)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    . = ALIGN(4);\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg\n#define RAMABLE_REGION_1 dram0_1_seg\n#define RODATA_REGION drom0_0_seg\n#define IRAM_REGION iram0_0_seg\n#define FLASH_CODE_REGION irom0_0_seg\n\n#define ROMABLE_REGION ROM\n\n#ifdef CONFIG_FLASH_SIZE\n#define ROM_SIZE CONFIG_FLASH_SIZE\n#else\n#define ROM_SIZE 0x400000\n#endif\n\n#ifdef CONFIG_BOOTLOADER_ESP_IDF\n#define IROM_SEG_ORG 0x400D0020\n#define IROM_SEG_LEN 0x330000-0x20\n#define IROM_SEG_ALIGN 0x4\n#else\n#define IROM_SEG_ORG 0x400D0000\n#define IROM_SEG_LEN 0x330000\n#define IROM_SEG_ALIGN 0x10000\n#endif\n\nMEMORY\n{\n  mcuboot_hdr (RX): org = 0x0, len = 0x20\n  metadata (RX): org = 0x20, len = 0x20\n  ROM (RX): org = 0x40, len = ROM_SIZE - 0x40\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE5230, len = 0x1BCB0 - 0xEE0 \/* skip data for APP CPU initialization usage *\/\n\n  \/* DROM is the first segment placed in generated binary.\n   * MCUboot binary for ESP32 has image header of 0x20 bytes.\n   * Additional load header of 0x20 bytes are appended to the image.\n   * Hence, an offset of 0x40 is added to DROM segment origin.\n   *\/\n  drom0_0_seg(R): org = 0x3F400040, len = 0x400000 - 0x40\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n  \/* Reserve space for MCUboot header in the binary *\/\n  .mcuboot_header :\n  {\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n  } > mcuboot_hdr\n  .metadata :\n  {\n    \/* Magic byte for load header *\/\n    LONG(0xace637d3)\n\n    \/* Application entry point address *\/\n    KEEP(*(.entry_addr))\n\n    \/* IRAM metadata:\n     * - Destination address (VMA) for IRAM region\n     * - Flash offset (LMA) for start of IRAM region\n     * - Size of IRAM region\n     *\/\n\n    LONG(ADDR(\".iram0.vectors\"))\n    LONG(LOADADDR(\".iram0.vectors\"))\n    LONG(LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - LOADADDR(\".iram0.vectors\"))\n\n    \/* DRAM metadata:\n     * - Destination address (VMA) for DRAM region\n     * - Flash offset (LMA) for start of DRAM region\n     * - Size of DRAM region\n     *\/\n\n    LONG(ADDR(\".dram0.data\"))\n    LONG(LOADADDR(\".dram0.data\"))\n    LONG(LOADADDR(\".dummy.dram.data\") + SIZEOF(\".dummy.dram.data\") - LOADADDR(\".dram0.data\"))\n  } > metadata\n\n#include <linker\/rel-sections.ld>\n  _image_drom_start = LOADADDR(_RODATA_SECTION_NAME);\n  _image_drom_size = LOADADDR(_RODATA_SECTION_NAME) + SIZEOF(_RODATA_SECTION_NAME) - _image_drom_start;\n  _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);\n\n  \/* NOTE: .rodata section should be the first section in the linker script and no\n   * other section should appear before .rodata section. This is the requirement\n   * to align ROM section to 64K page offset.\n   * Adding .rodata as first section helps to reduce size of generated binary by\n   * few kBs.\n   *\/\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    . = ALIGN(4);\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.*) .rodata)\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.*) .rodata.*)\n\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)\n\n  _image_dram_start = LOADADDR(\".dram0.data\");\n  _image_dram_size = LOADADDR(\".dummy.dram.data\") + SIZEOF(\".dummy.dram.data\") - _image_dram_start;\n  _image_dram_vaddr = ADDR(\".dram0.data\");\n\n  #include <snippets-sections.ld>\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libzephyr.a:loader.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    . = ALIGN(4);\n    _dram_data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  #pragma push_macro(\"GROUP_ROM_LINK_IN\")\n  #pragma push_macro(\"ITERABLE_SECTION_ROM\")\n  #undef GROUP_ROM_LINK_IN\n  #undef ITERABLE_SECTION_ROM\n  #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN\n  #define ITERABLE_SECTION_ROM(x,y)\n  #include <linker\/common-rom.ld>\n  #pragma pop_macro(\"GROUP_ROM_LINK_IN\")\n  #pragma pop_macro(\"ITERABLE_SECTION_ROM\")\n\n  #include <snippets-data-sections.ld>\n  #include <linker\/common-ram.ld>\n  #include <snippets-ram-sections.ld>\n\n  __shell_root_cmds_start = __esp_shell_root_cmds_start;\n  __shell_root_cmds_end = __esp_shell_root_cmds_end;\n\n  .dummy.dram.data :\n  {\n    . = ALIGN(4);\n    #include <snippets-rwdata.ld>\n    . = ALIGN(4);\n    _data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  _image_iram_start = LOADADDR(\".iram0.vectors\");\n  _image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start;\n  _image_iram_vaddr = ADDR(\".iram0.vectors\");\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:loader.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(rtc_slow_seg)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    \/* Buffer for system heap should be placed in dram0_0_seg *\/\n    *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap)\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(.noinit.*)\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n  _image_irom_start = LOADADDR(\".flash.text\");\n  _image_irom_size = LOADADDR(\".flash.text\") + SIZEOF(\".flash.text\") - _image_irom_start;\n  _image_irom_vaddr = ADDR(\".flash.text\");\n\n  .flash.text : ALIGN(IROM_SEG_ALIGN)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    . = ALIGN(4);\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f84da831f05dff6ba7e67b5d42a63e413531a148","subject":"Fix linker script bug. Always link against interrupt handlers!","message":"Fix linker script bug. Always link against interrupt handlers!\n","repos":"cahirwpz\/mimiker,Darge\/mimiker,dyniec\/mimiker,Darge\/mimiker,rafalcieslak\/mimiker,czapiga\/mimiker,dyniec\/mimiker,czapiga\/mimiker,cahirwpz\/mimiker,rafalcieslak\/mimiker,cahirwpz\/mimiker,czapiga\/mimiker,dyniec\/mimiker,rafalcieslak\/mimiker,Darge\/mimiker,dyniec\/mimiker,czapiga\/mimiker,rafalcieslak\/mimiker,cahirwpz\/wifire-os,cahirwpz\/mimiker","old_file":"malta.ld","new_file":"malta.ld","new_contents":"\/* Linker script for OVPsim SmartLoaderLinux firmware. *\/\nOUTPUT_ARCH(mips)\nENTRY(_start)\nPHDRS\n{\n  text PT_LOAD FLAGS(5); \/* read-only, executable *\/\n  data PT_LOAD FLAGS(6); \/* read-write *\/\n}\nPROVIDE(__tlb_stride_length = 1);\nSECTIONS\n{\n  \/* RAM is mapped in kseg0 (cacheable) and kseg1 (non-cacheable) *\/\n  _ram = 0x80000000;\n\n  .text 0x80100000:\n  {\n    \/* Exception handlers. *\/\n    _ebase = ABSOLUTE(.);\n    intr.o (.ebase)\n    . = ALIGN(4096);\n    \/* Text and read-only data follows. *\/\n    __text = ABSOLUTE(.);\n    *(.text .text.*)\n    . = ALIGN (4);\n    *(.rodata .rodata.*)\n    __etext = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } : text\n\n  .data ADDR(.text) + SIZEOF (.text):\n  {\n    __data = ABSOLUTE(.);\n    _gp = .;\n    *(.data .data.*)\n    *(.sdata .sdata.*)\n    *(.eh_frame .eh_frame.*)\n    . = ALIGN(4);\n    __edata = ABSOLUTE(.);\n  } : data\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n    __bss = ABSOLUTE(.);\n    *(.sbss .scommon)\n    *(.bss .bss.*)\n    *(COMMON)\n    . = ALIGN (4);\n    __ebss = ABSOLUTE(.);\n  }\n\n  _end = .;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ :\n  {\n    *(.comment)\n    *(.note)\n    *(.options)\n    *(.pdr)\n    *(.reginfo)\n    *(.gnu.attributes)\n    *(.MIPS.abiflags)\n    *(.MIPS.options)\n  }\n}\n","old_contents":"\/* Linker script for OVPsim SmartLoaderLinux firmware. *\/\nOUTPUT_ARCH(mips)\nENTRY(_start)\nPHDRS\n{\n  text PT_LOAD FLAGS(5); \/* read-only, executable *\/\n  data PT_LOAD FLAGS(6); \/* read-write *\/\n}\nPROVIDE(__tlb_stride_length = 1);\nSECTIONS\n{\n  \/* RAM is mapped in kseg0 (cacheable) and kseg1 (non-cacheable) *\/\n  _ram = 0x80000000;\n\n  .text 0x80100000:\n  {\n    \/* Exception handlers. *\/\n    _ebase = ABSOLUTE(.);\n    *(.ebase)\n    . = ALIGN(4096);\n    \/* Text and read-only data follows. *\/\n    __text = ABSOLUTE(.);\n    *(.text .text.*)\n    . = ALIGN (4);\n    *(.rodata .rodata.*)\n    __etext = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } : text\n\n  .data ADDR(.text) + SIZEOF (.text):\n  {\n    __data = ABSOLUTE(.);\n    _gp = .;\n    *(.data .data.*)\n    *(.sdata .sdata.*)\n    *(.eh_frame .eh_frame.*)\n    . = ALIGN(4);\n    __edata = ABSOLUTE(.);\n  } : data\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n    __bss = ABSOLUTE(.);\n    *(.sbss .scommon)\n    *(.bss .bss.*)\n    *(COMMON)\n    . = ALIGN (4);\n    __ebss = ABSOLUTE(.);\n  }\n\n  _end = .;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ :\n  {\n    *(.comment)\n    *(.note)\n    *(.options)\n    *(.pdr)\n    *(.reginfo)\n    *(.gnu.attributes)\n    *(.MIPS.abiflags)\n    *(.MIPS.options)\n  }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"bf87f000d3919bab2712e51abfad8fe174341a83","subject":"ld: flash: add user stack","message":"ld: flash: add user stack\n","repos":"raphui\/rnk,raphui\/rnk,raphui\/rnk,raphui\/rnk","old_file":"flash_sam7s.lds","new_file":"flash_sam7s.lds","new_contents":"\/* ----------------------------------------------------------------------------\r\n *         ATMEL Microcontroller Software Support\r\n * ----------------------------------------------------------------------------\r\n * Copyright (c) 2008, Atmel Corporation\r\n *\r\n * All rights reserved.\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * - Redistributions of source code must retain the above copyright notice,\r\n * this list of conditions and the disclaimer below.\r\n *\r\n * Atmel's name may not be used to endorse or promote products derived from\r\n * this software without specific prior written permission.\r\n *\r\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\r\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n * ----------------------------------------------------------------------------\r\n *\/\r\n\r\n\/*------------------------------------------------------------------------------\r\n *      Linker script for running in internal Flash on the AT91SAM7S256.\r\n *----------------------------------------------------------------------------*\/\r\n\r\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(entry)\r\n\r\nMEMORY\r\n{\r\n    sram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x10000\r\n    flash (RX) : ORIGIN = 0x100000, LENGTH = 0x40000\r\n}\r\n\r\nSECTIONS\r\n{  \r\n    .fixed :\r\n    {\r\n        . = ALIGN(4);\r\n        _sfixed = .;\r\n        *(.text*)\r\n        *(.rodata*)\r\n        . = ALIGN(4);\r\n        _efixed = .;\r\n    } >flash\r\n\r\n    .relocate : AT (_efixed)\r\n    {\r\n        . = ALIGN(4);\r\n        _srelocate = .;\r\n        *(.vectors)\r\n        *(.ramfunc)\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        _erelocate = .;\r\n    } >sram\r\n\r\n    .bss (NOLOAD) : {\r\n        _szero = .;\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        _ezero = .;\r\n    } >sram\r\n    \r\n    _sstack = 0x210000;\r\n    _ustack = 0x2E0000;\r\n}\r\nend = .;\r\n\r\n","old_contents":"\/* ----------------------------------------------------------------------------\r\n *         ATMEL Microcontroller Software Support\r\n * ----------------------------------------------------------------------------\r\n * Copyright (c) 2008, Atmel Corporation\r\n *\r\n * All rights reserved.\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * - Redistributions of source code must retain the above copyright notice,\r\n * this list of conditions and the disclaimer below.\r\n *\r\n * Atmel's name may not be used to endorse or promote products derived from\r\n * this software without specific prior written permission.\r\n *\r\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\r\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n * ----------------------------------------------------------------------------\r\n *\/\r\n\r\n\/*------------------------------------------------------------------------------\r\n *      Linker script for running in internal Flash on the AT91SAM7S256.\r\n *----------------------------------------------------------------------------*\/\r\n\r\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(entry)\r\n\r\nMEMORY\r\n{\r\n    sram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x10000\r\n    flash (RX) : ORIGIN = 0x100000, LENGTH = 0x40000\r\n}\r\n\r\nSECTIONS\r\n{  \r\n    .fixed :\r\n    {\r\n        . = ALIGN(4);\r\n        _sfixed = .;\r\n        *(.text*)\r\n        *(.rodata*)\r\n        . = ALIGN(4);\r\n        _efixed = .;\r\n    } >flash\r\n\r\n    .relocate : AT (_efixed)\r\n    {\r\n        . = ALIGN(4);\r\n        _srelocate = .;\r\n        *(.vectors)\r\n        *(.ramfunc)\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        _erelocate = .;\r\n    } >sram\r\n\r\n    .bss (NOLOAD) : {\r\n        _szero = .;\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        _ezero = .;\r\n    } >sram\r\n    \r\n    _sstack = 0x210000;\r\n}\r\nend = .;\r\n\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"17833793cbad82bfbeea0e1c29d674f51f293a38","subject":"link script adjustments","message":"link script adjustments\n","repos":"ps3dev\/PSL1GHT,ps3dev\/PSL1GHT,ps3dev\/PSL1GHT,ps3dev\/PSL1GHT","old_file":"ppu\/crt\/lv2.ld","new_file":"ppu\/crt\/lv2.ld","new_contents":"OUTPUT_FORMAT(\"elf64-powerpc\", \"elf64-powerpc\", \"elf64-powerpc\")\nOUTPUT_ARCH(powerpc:common64)\n\nENTRY(_start)\n\nPHDRS\n{\n\thdr_text\tPT_LOAD FILEHDR PHDRS\tFLAGS(0x01 | 0x04);\n\thdr_data\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04);\n\thdr_srodata\tPT_LOAD\t\t\t\t\tFLAGS(0x04 | 0x00400000);\n\thdr_sdata\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04 | 0x00200000 | 0x00400000);\n\thdr_rsx\t\tPT_LOAD\t\t\t\t\tFLAGS(0x02 | 0x04 | 0x00200000 | 0x00400000 | 0x02000000 | 0x04000000);\n\thdr_tls\t\tPT_TLS\t\t\t\t\tFLAGS(0x04);\n\thdr_param\t0x60000001\t\t\t\tFLAGS(0x00);\n\thdr_prx\t\t0x60000002\t\t\t\tFLAGS(0x00);\n}\n\nSECTIONS\n{\n\tPROVIDE (__executable_start = 0x10000); . = 0x10000 + SIZEOF_HEADERS;\n\t.interp         : { *(.interp) } : hdr_text\n\t.hash           : { *(.hash) }\n\t.dynsym         : { *(.dynsym) }\n\t.dynstr         : { *(.dynstr) }\n\t.gnu.version    : { *(.gnu.version) }\n\t.gnu.version_d  : { *(.gnu.version_d) }\n\t.gnu.version_r  : { *(.gnu.version_r) }\n\t.rel.dyn\t\t:\n\t  {\n\t    *(.rel.init)\n\t    *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n\t    *(.rel.fini)\n\t    *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n\t    *(.rel.data.rel.ro*)\n\t    *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n\t    *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n\t    *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n\t    *(.rel.ctors)\n\t    *(.rel.dtors)\n\t    *(.rel.got)\n\t    *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)\n\t    *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)\n\t    *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)\n\t    *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)\n\t    *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n\t  }\n\n\t.rela.dyn\t\t:\n\t  {\n\t    *(.rela.init)\n\t    *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n\t    *(.rela.fini)\n\t    *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n\t    *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n\t    *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n\t    *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n\t    *(.rela.ctors)\n\t    *(.rela.dtors)\n\t    *(.rela.got)\n\t    *(.rela.toc)\n\t    *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)\n\t    *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)\n\t    *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)\n\t    *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)\n\t    *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n\t  }\n\t.rel.plt        : { *(.rel.plt) }\n\t.rela.plt       : { *(.rela.plt) }\n\t.rela.tocbss    : { *(.rela.tocbss) }\n\t.init           : {\n\t\tKEEP (*(.init))\n\t} = 0x60000000\n\t.text           : {\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\tKEEP (*(.text.*personality*))\n\t\t\/* .gnu.warning sections are handled specially by elf32.em.  *\/\n\t\t*(.gnu.warning)\n\t\t*(.sfpr .glink)\n\t} = 0x60000000\n\t.fini           : {\n\t\tKEEP (*(.fini))\n\t} = 0x60000000\n\t.sceStub.text   : {\n\t\t*(.sceStub.text)\n\t\t*(SORT(.sceStub.text.*))\n\t}\n\tPROVIDE (__etext = .);\n\tPROVIDE (_etext = .);\n\tPROVIDE (etext = .);\n\n\t.eh_frame_hdr : { *(.eh_frame_hdr) }\n\t.eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n\t.gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n\n\t.rodata.sceResident : { KEEP (*(.rodata.sceResident)) }\n\t.rodata.sceFNID     : { KEEP (*(.rodata.sceFNID .rodata.sceFNID.*)) }\n\t.rodata.sceVNID     : { KEEP (*(.rodata.sceVNID .rodata.sceVNID.*)) }\n\t.rodata.sceTNID     : { KEEP (*(.rodata.sceTNID .rodata.sceTNID.*)) }\n\t.rodata.sceVStub    : { KEEP (*(.rodata.sceVStub)) KEEP (*(SORT(.rodata.sceVStub.*))) }\n\n\tPROVIDE (__libentstart = .);\n\t.lib.ent.top : { KEEP (*(.lib.ent.top)) }\n\t.lib.ent\t : { KEEP (*(.lib.ent)) }\n\t.lib.ent.btm : { KEEP (*(.lib.ent.btm)) }\n\tPROVIDE (__libentend = .);\n\n\tPROVIDE (__libstubstart = .);\n\t.lib.stub.top : { KEEP (*(.lib.stub.top)) }\n\t.lib.stub\t  : { KEEP (*(.lib.stub)) }\n\t.lib.stub.btm : { KEEP (*(.lib.stub.btm)) }\n\tPROVIDE (__libstubend = .);\n\n\t.ppu_rodata         : { *(.ppu_rodata .ppu_rodata.*) }\n\t.sys_proc_param     : { KEEP (*(.sys_proc_param)) } : hdr_text : hdr_param\n\t.sys_proc_prx_param : { KEEP (*(.sys_proc_prx_param)) } : hdr_text : hdr_prx\n\n\t. = ALIGN(64K);\n\t\n\t.ppu_data           : { *(.ppu_data .ppu_data.*) } : hdr_data\n\t.sdata2             : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }\n\t.sbss2              : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }\n\n\t\/* Exception handling  *\/\n\t.eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n\t.gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n\t\n\t. = ALIGN(64 \/ 8);\n\t\n\t.preinit_array     : {\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\t}\n\t.init_array     : {\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\t}\n\t.fini_array     : {\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\t}\n\t.ctors          : {\n\t\t\/* gcc uses crtbegin.o to find the start of\n\t\t   the constructors, so we make sure it is\n\t\t   first.  Because this is a wildcard, it\n\t\t   doesn't matter if the user does not\n\t\t   actually link against crtbegin.o; the\n\t\t   linker won't look for a file to match a\n\t\t   wildcard.  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When there is no .bss section, we don't\n\t\t   pad the .data section.  *\/\n\t\t. = ALIGN(. != 0 ? 64 \/ 8 : 1);\n\t}\n\t. = ALIGN(64 \/ 8);\n\t. = ALIGN(64 \/ 8);\n\t_end = .; PROVIDE (end = .);\n\t. = DATA_SEGMENT_END (.);\n\t\/* Stabs debugging sections.  *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment       0 : { *(.comment) }\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0.  *\/\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\n\t.debug_typenames 0 : { *(.debug_typenames) }\n\t.debug_varnames  0 : { *(.debug_varnames) }\n\t\/* DWARF 3 *\/\n\t.debug_pubtypes 0 : { *(.debug_pubtypes) }\n\t.debug_ranges   0 : { *(.debug_ranges) }\n\t.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n\t\/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"83c4d2a2019555ef8c6e74885496563c6e171225","subject":"Deleted original model.lds (it will be autogenerated).","message":"Deleted original model.lds (it will be autogenerated).\n","repos":"virtualopensystems\/boot-wrapper,virtualopensystems\/boot-wrapper","old_file":"model.lds","new_file":"model.lds","new_contents":"","old_contents":"\/*\n * boot.S - simple register setup code for stand-alone Linux booting\n *\n * Copyright (C) 2009 ARM Limited\n *\n * This program is free software; you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nTARGET(binary)\n\nINPUT(.\/uImage)\nINPUT(.\/filesystem.cpio.gz)\nINPUT(.\/boot.o)\n\nPHYS_OFFSET = 0x70000000;\n\nSECTIONS\n{\n\t. = PHYS_OFFSET;\n\t.text : { boot.o }\n\n\t. = PHYS_OFFSET + 0x8000 - 0x40;\n\tkernel = . + 0x40;\n\t.kernel : { .\/uImage }\n\n\t. = PHYS_OFFSET + 0x00800000;\n\tfilesystem = .;\n\t.filesystem : { .\/filesystem.cpio.gz }\n\tfs_size = . - filesystem;\n\n\t.data : { *(.data) }\n\t.bss : { *(.bss) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"de7332a386dda45e1df40183dcca2184c143b3e0","subject":"Erroneously commited a different nrf51dk.ld","message":"Erroneously commited a different nrf51dk.ld\n","repos":"mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,IMGJulian\/incubator-mynewt-core,mlaz\/mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,wes3\/incubator-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,wes3\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,wes3\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core","old_file":"hw\/bsp\/nrf51dk\/nrf51dk.ld","new_file":"hw\/bsp\/nrf51dk\/nrf51dk.ld","new_contents":"\/* Linker script for Nordic Semiconductor nRF5 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00008000, LENGTH = 0x1b800\n  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x8000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __bssnz_start__\n *   __bssnz_end__\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .imghdr (NOLOAD):\n    {\n    \t. = . + 0x20;\n    } > FLASH\n\n    .text :\n    {\n        __isr_vector_start = .;\n        KEEP(*(.isr_vector))\n        __isr_vector_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    \/* Keep first in RAM, as well as in bootloader *\/\n    .vector_relocation :\n    {\n        . = ALIGN(4);\n        __vector_tbl_reloc__ = .;\n        . = . + (__isr_vector_end - __isr_vector_start);\n        . = ALIGN(4);\n    } > RAM\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        *(.preinit_array)\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        *(SORT(.init_array.*))\n        *(.init_array)\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    \/* Heap starts after BSS *\/\n    __HeapBase = .;\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Top of head is the bottom of the stack *\/\n    __HeapLimit = __StackLimit;\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","old_contents":"\/* Linker script for Nordic Semiconductor nRF5 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000\n  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x8000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __bssnz_start__\n *   __bssnz_end__\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        __isr_vector_start = .;\n        KEEP(*(.isr_vector))\n        __isr_vector_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    \/* Keep first in RAM, as well as in bootloader *\/\n    .vector_relocation :\n    {\n        . = ALIGN(4);\n        __vector_tbl_reloc__ = .;\n        . = . + (__isr_vector_end - __isr_vector_start);\n        . = ALIGN(4);\n    } > RAM\n            \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        *(.preinit_array)\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        *(SORT(.init_array.*))\n        *(.init_array)\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    \/* Heap starts after BSS *\/\n    __HeapBase = .;\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Top of head is the bottom of the stack *\/\n    __HeapLimit = __StackLimit;\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"98fb50a086f33a85279decbf6fdffcee3d04b25f","subject":"Remove comment from linker file","message":"Remove comment from linker file\n","repos":"redox-os\/kernel,AleVul\/kernel,redox-os\/kernel,AleVul\/kernel,redox-os\/kernel","old_file":"linkers\/x86_64.ld","new_file":"linkers\/x86_64.ld","new_contents":"ENTRY(kstart)\nOUTPUT_FORMAT(elf64-x86-64)\n\nKERNEL_OFFSET = 0xffffff0000100000;\n\nSECTIONS {\n    . = KERNEL_OFFSET;\n\n    . += SIZEOF_HEADERS;\n    . = ALIGN(4096);\n\n    .text : AT(ADDR(.text) - KERNEL_OFFSET) {\n        __text_start = .;\n        *(.text*)\n\t\t. = ALIGN(4096);\n        __text_end = .;\n    }\n\n\t.rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) {\n        __rodata_start = .;\n        *(.rodata*)\n\t\t. = ALIGN(4096);\n        __rodata_end = .;\n    }\n\n    .data : AT(ADDR(.data) - KERNEL_OFFSET) {\n        __data_start = .;\n        *(.data*)\n\t\t. = ALIGN(4096);\n        __data_end = .;\n        __bss_start = .;\n        *(.bss*)\n        . = ALIGN(4096);\n        __bss_end = .;\n    }\n\n    .tdata : AT(ADDR(.tdata) - KERNEL_OFFSET) {\n        __tdata_start = .;\n        *(.tdata*)\n        . = ALIGN(4096);\n        __tdata_end = .;\n        __tbss_start = .;\n        *(.tbss*)\n        . += 8;\n        . = ALIGN(4096);\n        __tbss_end = .;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ : {\n        *(.comment*)\n        *(.eh_frame*)\n        *(.gcc_except_table*)\n        *(.note*)\n        *(.rel.eh_frame*)\n    }\n}\n","old_contents":"ENTRY(kstart)\nOUTPUT_FORMAT(elf64-x86-64)\n\nKERNEL_OFFSET = 0xffffff0000100000;\n\/* KERNEL_OFFSET = 0x100000; *\/\n\nSECTIONS {\n    . = KERNEL_OFFSET;\n\n    . += SIZEOF_HEADERS;\n    . = ALIGN(4096);\n\n    .text : AT(ADDR(.text) - KERNEL_OFFSET) {\n        __text_start = .;\n        *(.text*)\n\t\t. = ALIGN(4096);\n        __text_end = .;\n    }\n\n\t.rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) {\n        __rodata_start = .;\n        *(.rodata*)\n\t\t. = ALIGN(4096);\n        __rodata_end = .;\n    }\n\n    .data : AT(ADDR(.data) - KERNEL_OFFSET) {\n        __data_start = .;\n        *(.data*)\n\t\t. = ALIGN(4096);\n        __data_end = .;\n        __bss_start = .;\n        *(.bss*)\n        . = ALIGN(4096);\n        __bss_end = .;\n    }\n\n    .tdata : AT(ADDR(.tdata) - KERNEL_OFFSET) {\n        __tdata_start = .;\n        *(.tdata*)\n        . = ALIGN(4096);\n        __tdata_end = .;\n        __tbss_start = .;\n        *(.tbss*)\n        . += 8;\n        . = ALIGN(4096);\n        __tbss_end = .;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ : {\n        *(.comment*)\n        *(.eh_frame*)\n        *(.gcc_except_table*)\n        *(.note*)\n        *(.rel.eh_frame*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ccfccae3bca29b235c51ffbd8be05c3071fad637","subject":"x86: intel64: don't drop debug sections","message":"x86: intel64: don't drop debug sections\n\nPull in a header specifically for suppressing orphan section\nmessages.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/x86\/intel64\/linker.ld","new_file":"include\/arch\/x86\/intel64\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corp.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION RAM\n#define RAMABLE_REGION RAM\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\t\/*\n\t * The \"locore\" must be in the 64K of RAM, so that 16-bit code (with\n\t * segment registers == 0x0000) and 32\/64-bit code agree on addresses.\n\t * ... there is no 16-bit code yet, but there will be when we add SMP.\n\t *\/\n\n\t.locore 0x8000 : ALIGN(16)\n\t{\n\t_locore_start = .;\n\t*(.locore)\n\t*(.locore.*)\n\t*(.tss)\n\t_locore_end = .;\n\t}\n\n\t\/*\n\t * The rest of the system is loaded in \"normal\" memory (typically\n\t * placed above 1MB to avoid the by memory hole at 0x90000-0xFFFFF).\n\t *\/\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_rom_start = .;\n\t*(.text)\n\t*(.text.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_rodata_start = .;\n\n\t*(.rodata)\n\t*(.rodata.*)\n\n\t#include <snippets-rodata.ld>\n\n\t#ifdef CONFIG_CUSTOM_RODATA_LD\n\t#include <custom-rodata.ld>\n\t#endif \/* CONFIG_CUSTOM_RODATA_LD *\/\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\t_image_rom_end = .;\n\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_ram_start = .;\n\t*(.data)\n\t*(.data.*)\n\t#include <snippets-rwdata.ld>\n\t#ifdef CONFIG_CUSTOM_RWDATA_LD\n\t#include <custom-rwdata.ld>\n\t#endif \/* CONFIG_CUSTOM_RWDATA_LD *\/\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <snippets-ram-sections.ld>\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t__bss_start = .;\n\t*(.bss)\n\t*(.bss.*)\n\t*(COMMON)\n\t. = ALIGN(4);\t\/* so __bss_num_dwords is exact *\/\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_dwords = (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t*(.noinit)\n\t*(.noinit.*)\n\t#include <snippets-noinit.ld>\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <snippets-sections.ld>\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n#include <custom-sections.ld>\n#endif \/* CONFIG_CUSTOM_SECTIONS_LD *\/\n\n\t. = ALIGN(8);\n\t_image_ram_end = .;\n\t_end = .;\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ :\n\t{\n\t*(.got)\n\t*(.got.plt)\n\t*(.igot)\n\t*(.igot.plt)\n\t*(.iplt)\n\t*(.plt)\n\t*(.note.GNU-stack)\n\t*(.rel.*)\n\t*(.rela.*)\n\t}\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corp.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION RAM\n#define RAMABLE_REGION RAM\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\t\/*\n\t * The \"locore\" must be in the 64K of RAM, so that 16-bit code (with\n\t * segment registers == 0x0000) and 32\/64-bit code agree on addresses.\n\t * ... there is no 16-bit code yet, but there will be when we add SMP.\n\t *\/\n\n\t.locore 0x8000 : ALIGN(16)\n\t{\n\t_locore_start = .;\n\t*(.locore)\n\t*(.locore.*)\n\t*(.tss)\n\t_locore_end = .;\n\t}\n\n\t\/*\n\t * The rest of the system is loaded in \"normal\" memory (typically\n\t * placed above 1MB to avoid the by memory hole at 0x90000-0xFFFFF).\n\t *\/\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_rom_start = .;\n\t*(.text)\n\t*(.text.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_rodata_start = .;\n\n\t*(.rodata)\n\t*(.rodata.*)\n\n\t#include <snippets-rodata.ld>\n\n\t#ifdef CONFIG_CUSTOM_RODATA_LD\n\t#include <custom-rodata.ld>\n\t#endif \/* CONFIG_CUSTOM_RODATA_LD *\/\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\t_image_rom_end = .;\n\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_ram_start = .;\n\t*(.data)\n\t*(.data.*)\n\t#include <snippets-rwdata.ld>\n\t#ifdef CONFIG_CUSTOM_RWDATA_LD\n\t#include <custom-rwdata.ld>\n\t#endif \/* CONFIG_CUSTOM_RWDATA_LD *\/\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <snippets-ram-sections.ld>\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t__bss_start = .;\n\t*(.bss)\n\t*(.bss.*)\n\t*(COMMON)\n\t. = ALIGN(4);\t\/* so __bss_num_dwords is exact *\/\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_dwords = (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t*(.noinit)\n\t*(.noinit.*)\n\t#include <snippets-noinit.ld>\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <snippets-sections.ld>\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n#include <custom-sections.ld>\n#endif \/* CONFIG_CUSTOM_SECTIONS_LD *\/\n\n\t. = ALIGN(8);\n\t_image_ram_end = .;\n\t_end = .;\n\n\t\/DISCARD\/ :\n\t{\n\t*(.comment*)\n\t*(.debug*)\n\t*(.got)\n\t*(.got.plt)\n\t*(.igot)\n\t*(.igot.plt)\n\t*(.iplt)\n\t*(.plt)\n\t*(.note.GNU-stack)\n\t*(.rel.*)\n\t*(.rela.*)\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6e654020a254dd3316eea55af39e2a65b21fc741","subject":"Add some previously unknown linker sections (e.g. from DWARF 3) ---  scripts\/sections_FLASH.ld | 17 ++++++++++++++---  1 file changed, 14 insertions(+), 3 deletions(-)","message":"Add some previously unknown linker sections (e.g. from DWARF 3)\n---\n scripts\/sections_FLASH.ld | 17 ++++++++++++++---\n 1 file changed, 14 insertions(+), 3 deletions(-)\n","repos":"peteflorence\/crazyflie-tools,blandry\/crazyflie-tools,blandry\/crazyflie-tools,peteflorence\/crazyflie-tools,peteflorence\/crazyflie-tools,blandry\/crazyflie-tools,blandry\/crazyflie-tools,peteflorence\/crazyflie-tools","old_file":"scripts\/sections_FLASH.ld","new_file":"scripts\/sections_FLASH.ld","new_contents":"\/*\r\nCommon part of the linker scripts for STR71x devices in FLASH mode\r\n(that is, the FLASH is seen at 0)\r\nCopyright RAISONANCE 2005\r\nYou can use, modify and distribute thisfile freely, but without any waranty.\r\n*\/\r\n\r\n\r\nMEMORY {\r\n       UNEXPECTED_SECTIONS : ORIGIN = 0xffffffff, LENGTH = 0\r\n}\r\n\r\n\/* Sections Definitions *\/\r\n\r\nSECTIONS\r\n{\r\n    \/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH *\/\r\n    .isr_vector :\r\n    {\r\n\t. = ALIGN(4);\r\n        KEEP(*(.isr_vector))            \/* Startup code *\/\r\n\t. = ALIGN(4);\r\n    } >FLASH\r\n \r\n    \/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH *\/\r\n    .flashtext :\r\n    {\r\n\t. = ALIGN(4);\r\n        *(.flashtext)            \/* Startup code *\/\r\n\t. = ALIGN(4);\r\n    } >FLASH\r\n \r\n    \r\n    \/* the program code is stored in the .text section, which goes to Flash *\/\r\n    .text :\r\n    {\r\n\t    . = ALIGN(4);\r\n\t    \r\n        *(.text)                   \/* remaining code *\/\r\n        *(.text.*)                 \/* remaining code *\/\r\n        *(.rodata)                 \/* read-only data (constants) *\/\r\n        *(.rodata*)\r\n        *(.glue_7)\r\n        *(.glue_7t)\r\n        *(.vfp11_veneer)\r\n        *(.v4_bx)\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n        \r\n        \/* Some stuff of CodeSourcery? *\/\r\n        KEEP (*(.init))\r\n        KEEP (*(.fini))\r\n        KEEP(*(.eh_frame))\r\n\r\n        \/* Parameters and log system datas *\/\r\n        . = ALIGN(4);\r\n        _param_start = .;\r\n        KEEP(*(.param))\r\n        KEEP(*(.param.*))\r\n        _param_stop = .;\r\n        . = ALIGN(4);\r\n        _log_start = .;\r\n        KEEP(*(.log))\r\n        KEEP(*(.log.*))\r\n        _log_stop = .;\r\n        \r\n        \r\n\t    . = ALIGN(4);\r\n   \t _etext = .;\r\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\r\n   \t \/* _sidata = _etext; *\/\r\n    } >FLASH\r\n\r\n    .libc :\r\n    {\r\n      . = ALIGN(4);\r\n      *(.ARM.exidx*)\r\n      . = ALIGN(4);\r\n      \r\n      _elibc = .;\r\n      _sidata = _elibc;\r\n    } >FLASH\r\n \r\n    \/* for some LPC devices, there is a FLASH patch to place at a specified address *\/\r\n    .flashpatch :\r\n    {\r\n\t. = ALIGN(4);\r\n        KEEP(*(.flashpatch))            \/* flashpatch data *\/\r\n\t. = ALIGN(4);\r\n    } >FLASHPATCH\r\n    \r\n    \/* for some LPC devices, there is a FLASH patch to place at a specified address\r\n    and then there is the rest of the flash *\/\r\n    .endflash :\r\n    {\r\n\t. = ALIGN(4);\r\n        *(.endflash)            \/* endflash code *\/\r\n\t. = ALIGN(4);\r\n    } >ENDFLASH\r\n\r\n    \/* This is the initialized data section\r\n    The program executes knowing that the data is in the RAM\r\n    but the loader puts the initial values in the FLASH (inidata).\r\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\r\n    .data  : AT ( _sidata )\r\n    {\r\n\t    . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sdata = . ;\r\n        \r\n        *(.data)\r\n        *(.data.*)\r\n        *(.RAMtext)\r\n\r\n\t    . = ALIGN(4);\r\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\r\n   \t _edata = . ;\r\n    } >RAM\r\n    \r\n    \r\n\r\n    \/* This is the uninitialized data section *\/\r\n    .bss :\r\n    {\r\n\t    . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _sbss = .;\r\n        \r\n        *(.bss)\r\n        *(.bss.*)\r\n        *(COMMON)\r\n        \r\n\t    . = ALIGN(4);\r\n\t    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n   \t _ebss = . ;\r\n    } >RAM\r\n    \r\n    PROVIDE ( end = _ebss );\r\n    PROVIDE ( _end = _ebss );\r\n    \r\n    \/* This is the user stack section \r\n    This is just to check that there is enough RAM left for the User mode stack\r\n    It should generate an error if it's full.\r\n     *\/\r\n    ._usrstack :\r\n    {\r\n\t    . = ALIGN(4);\r\n        _susrstack = . ;\r\n        \r\n        . = . + _Minimum_Stack_Size ;\r\n        \r\n\t    . = ALIGN(4);\r\n        _eusrstack = . ;\r\n    } >RAM\r\n    \r\n\r\n   \r\n    \/* this is the FLASH Bank1 *\/\r\n    \/* the C or assembly source must explicitly place the code or data there\r\n    using the \"section\" attribute *\/\r\n    .b1text :\r\n    {\r\n        *(.b1text)                   \/* remaining code *\/\r\n        *(.b1rodata)                 \/* read-only data (constants) *\/\r\n        *(.b1rodata*)\r\n    } >FLASHB1\r\n    \r\n    \/* this is the EXTMEM *\/\r\n    \/* the C or assembly source must explicitly place the code or data there\r\n    using the \"section\" attribute *\/\r\n    \r\n    \/* EXTMEM Bank0 *\/\r\n    .eb0text :\r\n    {\r\n        *(.eb0text)                   \/* remaining code *\/\r\n        *(.eb0rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb0rodata*)\r\n    } >EXTMEMB0\r\n    \r\n    \/* EXTMEM Bank1 *\/\r\n    .eb1text :\r\n    {\r\n        *(.eb1text)                   \/* remaining code *\/\r\n        *(.eb1rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb1rodata*)\r\n    } >EXTMEMB1\r\n    \r\n    \/* EXTMEM Bank2 *\/\r\n    .eb2text :\r\n    {\r\n        *(.eb2text)                   \/* remaining code *\/\r\n        *(.eb2rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb2rodata*)\r\n    } >EXTMEMB2\r\n    \r\n    \/* EXTMEM Bank0 *\/\r\n    .eb3text :\r\n    {\r\n        *(.eb3text)                   \/* remaining code *\/\r\n        *(.eb3rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb3rodata*)\r\n    } >EXTMEMB3\r\n    \r\n    __exidx_start = .;\r\n    __exidx_end = .;\r\n    \r\n    \/* after that it's only debugging information. *\/\r\n    \r\n    \/* remove the debugging information from the standard libraries *\/\r\n    \/DISCARD\/ :\r\n    {\r\n     libc.a ( * )\r\n     libm.a ( * )\r\n     libgcc.a ( * )\r\n     }\r\n\r\n    \/* Stabs debugging sections.  *\/\r\n    .stab          0 : { *(.stab) }\r\n    .stabstr       0 : { *(.stabstr) }\r\n    .stab.excl     0 : { *(.stab.excl) }\r\n    .stab.exclstr  0 : { *(.stab.exclstr) }\r\n    .stab.index    0 : { *(.stab.index) }\r\n    .stab.indexstr 0 : { *(.stab.indexstr) }\r\n    .comment       0 : { *(.comment) }\r\n    \/* DWARF debug sections.\r\n       Symbols in the DWARF debugging sections are relative to the beginning\r\n       of the section so we begin them at 0.  *\/\r\n    \/* DWARF 1 *\/\r\n    .debug          0 : { *(.debug) }\r\n    .line           0 : { *(.line) }\r\n    \/* GNU DWARF 1 extensions *\/\r\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n    .debug_sfnames  0 : { *(.debug_sfnames) }\r\n    \/* DWARF 1.1 and DWARF 2 *\/\r\n    .debug_aranges  0 : { *(.debug_aranges) }\r\n    .debug_pubnames 0 : { *(.debug_pubnames) }\r\n    \/* DWARF 2 *\/\r\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n    .debug_abbrev   0 : { *(.debug_abbrev) }\r\n    .debug_line     0 : { *(.debug_line) }\r\n    .debug_frame    0 : { *(.debug_frame) }\r\n    .debug_str      0 : { *(.debug_str) }\r\n    .debug_loc      0 : { *(.debug_loc) }\r\n    .debug_macinfo  0 : { *(.debug_macinfo) }\r\n    \/* SGI\/MIPS DWARF 2 extensions *\/\r\n    .debug_weaknames 0 : { *(.debug_weaknames) }\r\n    .debug_funcnames 0 : { *(.debug_funcnames) }\r\n    .debug_typenames 0 : { *(.debug_typenames) }\r\n    .debug_varnames  0 : { *(.debug_varnames) }\r\n    \/* DWARF 3 *\/\r\n    .debug_pubtypes 0 : { *(.debug_pubtypes) }\r\n    .debug_ranges   0 : { *(.debug_ranges) }\r\n    \/* DWARF extension *\/\r\n    .debug_macro    0 : { *(.debug_macro) }\r\n    .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }\r\n    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\r\n    \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\r\n\r\n    .unexpected_sections : { *(*) } > UNEXPECTED_SECTIONS\r\n}\r\n\r\n\r\n\r\n","old_contents":"\/*\r\nCommon part of the linker scripts for STR71x devices in FLASH mode\r\n(that is, the FLASH is seen at 0)\r\nCopyright RAISONANCE 2005\r\nYou can use, modify and distribute thisfile freely, but without any waranty.\r\n*\/\r\n\r\n\r\nMEMORY {\r\n       UNEXPECTED_SECTIONS : ORIGIN = 0xffffffff, LENGTH = 0\r\n}\r\n\r\n\/* Sections Definitions *\/\r\n\r\nSECTIONS\r\n{\r\n    \/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH *\/\r\n    .isr_vector :\r\n    {\r\n\t. = ALIGN(4);\r\n        KEEP(*(.isr_vector))            \/* Startup code *\/\r\n\t. = ALIGN(4);\r\n    } >FLASH\r\n \r\n    \/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH *\/\r\n    .flashtext :\r\n    {\r\n\t. = ALIGN(4);\r\n        *(.flashtext)            \/* Startup code *\/\r\n\t. = ALIGN(4);\r\n    } >FLASH\r\n \r\n    \r\n    \/* the program code is stored in the .text section, which goes to Flash *\/\r\n    .text :\r\n    {\r\n\t    . = ALIGN(4);\r\n\t    \r\n        *(.text)                   \/* remaining code *\/\r\n        *(.text.*)                 \/* remaining code *\/\r\n        *(.rodata)                 \/* read-only data (constants) *\/\r\n        *(.rodata*)\r\n        *(.glue_7)\r\n        *(.glue_7t)\r\n        \r\n        \/* Some stuff of CodeSourcery? *\/\r\n        *(.init)\r\n        *(.fini)\r\n        *(.eh_frame)\r\n\r\n        \/* Parameters and log system datas *\/\r\n        . = ALIGN(4);\r\n        _param_start = .;\r\n        KEEP(*(.param))\r\n        KEEP(*(.param.*))\r\n        _param_stop = .;\r\n        . = ALIGN(4);\r\n        _log_start = .;\r\n        KEEP(*(.log))\r\n        KEEP(*(.log.*))\r\n        _log_stop = .;\r\n        \r\n        \r\n\t    . = ALIGN(4);\r\n   \t _etext = .;\r\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\r\n   \t \/* _sidata = _etext; *\/\r\n    } >FLASH\r\n\r\n    .libc :\r\n    {\r\n      . = ALIGN(4);\r\n      *(.ARM.exidx*)\r\n      . = ALIGN(4);\r\n      \r\n      _elibc = .;\r\n      _sidata = _elibc;\r\n    } >FLASH\r\n \r\n    \/* for some LPC devices, there is a FLASH patch to place at a specified address *\/\r\n    .flashpatch :\r\n    {\r\n\t. = ALIGN(4);\r\n        KEEP(*(.flashpatch))            \/* flashpatch data *\/\r\n\t. = ALIGN(4);\r\n    } >FLASHPATCH\r\n    \r\n    \/* for some LPC devices, there is a FLASH patch to place at a specified address\r\n    and then there is the rest of the flash *\/\r\n    .endflash :\r\n    {\r\n\t. = ALIGN(4);\r\n        *(.endflash)            \/* endflash code *\/\r\n\t. = ALIGN(4);\r\n    } >ENDFLASH\r\n\r\n    \/* This is the initialized data section\r\n    The program executes knowing that the data is in the RAM\r\n    but the loader puts the initial values in the FLASH (inidata).\r\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\r\n    .data  : AT ( _sidata )\r\n    {\r\n\t    . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sdata = . ;\r\n        \r\n        *(.data)\r\n        *(.data.*)\r\n        *(.RAMtext)\r\n\r\n\t    . = ALIGN(4);\r\n\t    \/* This is used by the startup in order to initialize the .data secion *\/\r\n   \t _edata = . ;\r\n    } >RAM\r\n    \r\n    \r\n\r\n    \/* This is the uninitialized data section *\/\r\n    .bss :\r\n    {\r\n\t    . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _sbss = .;\r\n        \r\n        *(.bss)\r\n        *(.bss.*)\r\n        *(COMMON)\r\n        \r\n\t    . = ALIGN(4);\r\n\t    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n   \t _ebss = . ;\r\n    } >RAM\r\n    \r\n    PROVIDE ( end = _ebss );\r\n    PROVIDE ( _end = _ebss );\r\n    \r\n    \/* This is the user stack section \r\n    This is just to check that there is enough RAM left for the User mode stack\r\n    It should generate an error if it's full.\r\n     *\/\r\n    ._usrstack :\r\n    {\r\n\t    . = ALIGN(4);\r\n        _susrstack = . ;\r\n        \r\n        . = . + _Minimum_Stack_Size ;\r\n        \r\n\t    . = ALIGN(4);\r\n        _eusrstack = . ;\r\n    } >RAM\r\n    \r\n\r\n   \r\n    \/* this is the FLASH Bank1 *\/\r\n    \/* the C or assembly source must explicitly place the code or data there\r\n    using the \"section\" attribute *\/\r\n    .b1text :\r\n    {\r\n        *(.b1text)                   \/* remaining code *\/\r\n        *(.b1rodata)                 \/* read-only data (constants) *\/\r\n        *(.b1rodata*)\r\n    } >FLASHB1\r\n    \r\n    \/* this is the EXTMEM *\/\r\n    \/* the C or assembly source must explicitly place the code or data there\r\n    using the \"section\" attribute *\/\r\n    \r\n    \/* EXTMEM Bank0 *\/\r\n    .eb0text :\r\n    {\r\n        *(.eb0text)                   \/* remaining code *\/\r\n        *(.eb0rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb0rodata*)\r\n    } >EXTMEMB0\r\n    \r\n    \/* EXTMEM Bank1 *\/\r\n    .eb1text :\r\n    {\r\n        *(.eb1text)                   \/* remaining code *\/\r\n        *(.eb1rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb1rodata*)\r\n    } >EXTMEMB1\r\n    \r\n    \/* EXTMEM Bank2 *\/\r\n    .eb2text :\r\n    {\r\n        *(.eb2text)                   \/* remaining code *\/\r\n        *(.eb2rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb2rodata*)\r\n    } >EXTMEMB2\r\n    \r\n    \/* EXTMEM Bank0 *\/\r\n    .eb3text :\r\n    {\r\n        *(.eb3text)                   \/* remaining code *\/\r\n        *(.eb3rodata)                 \/* read-only data (constants) *\/\r\n        *(.eb3rodata*)\r\n    } >EXTMEMB3\r\n    \r\n    __exidx_start = .;\r\n    __exidx_end = .;\r\n    \r\n    \/* after that it's only debugging information. *\/\r\n    \r\n    \/* remove the debugging information from the standard libraries *\/\r\n    \/DISCARD\/ :\r\n    {\r\n     libc.a ( * )\r\n     libm.a ( * )\r\n     libgcc.a ( * )\r\n     }\r\n\r\n    \/* Stabs debugging sections.  *\/\r\n    .stab          0 : { *(.stab) }\r\n    .stabstr       0 : { *(.stabstr) }\r\n    .stab.excl     0 : { *(.stab.excl) }\r\n    .stab.exclstr  0 : { *(.stab.exclstr) }\r\n    .stab.index    0 : { *(.stab.index) }\r\n    .stab.indexstr 0 : { *(.stab.indexstr) }\r\n    .comment       0 : { *(.comment) }\r\n    \/* DWARF debug sections.\r\n       Symbols in the DWARF debugging sections are relative to the beginning\r\n       of the section so we begin them at 0.  *\/\r\n    \/* DWARF 1 *\/\r\n    .debug          0 : { *(.debug) }\r\n    .line           0 : { *(.line) }\r\n    \/* GNU DWARF 1 extensions *\/\r\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n    .debug_sfnames  0 : { *(.debug_sfnames) }\r\n    \/* DWARF 1.1 and DWARF 2 *\/\r\n    .debug_aranges  0 : { *(.debug_aranges) }\r\n    .debug_pubnames 0 : { *(.debug_pubnames) }\r\n    \/* DWARF 2 *\/\r\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n    .debug_abbrev   0 : { *(.debug_abbrev) }\r\n    .debug_line     0 : { *(.debug_line) }\r\n    .debug_frame    0 : { *(.debug_frame) }\r\n    .debug_str      0 : { *(.debug_str) }\r\n    .debug_loc      0 : { *(.debug_loc) }\r\n    .debug_macinfo  0 : { *(.debug_macinfo) }\r\n    \/* SGI\/MIPS DWARF 2 extensions *\/\r\n    .debug_weaknames 0 : { *(.debug_weaknames) }\r\n    .debug_funcnames 0 : { *(.debug_funcnames) }\r\n    .debug_typenames 0 : { *(.debug_typenames) }\r\n    .debug_varnames  0 : { *(.debug_varnames) }\r\n\r\n    .unexpected_sections : { *(*) } > UNEXPECTED_SECTIONS\r\n}\r\n\r\n\r\n\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2c5c6032b1d11b110834c85106bf19d6393a5243","subject":"Allow got\/data sections to be empty in linker script check","message":"Allow got\/data sections to be empty in linker script check\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got < _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data < _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b12c4df624da8b23fbd88d19817e33ebc1e7b0dd","subject":"Increase ram size for unit tests to 16M.","message":"Increase ram size for unit tests to 16M.\n","repos":"PW-Sat2\/PWSat2OBC,PW-Sat2\/PWSat2OBC,PW-Sat2\/PWSat2OBC,PW-Sat2\/PWSat2OBC","old_file":"unit_tests\/base\/linker.ld","new_file":"unit_tests\/base\/linker.ld","new_contents":"\/* Linker script for Silicon Labs EFM32GG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 4.1.0 *\/\r\n\/*                                                                  *\/\r\n\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 20480K\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 16384K\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.vectors))\r\n    __Vectors_End = .;\r\n    __Vectors_Size = __Vectors_End - __Vectors;\r\n    __end__ = .;\r\n\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  \/* To copy multiple ROM to RAM sections,\r\n   * uncomment .copy.table section and,\r\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .copy.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __copy_table_start__ = .;\r\n    LONG (__etext)\r\n    LONG (__data_start__)\r\n    LONG (__data_end__ - __data_start__)\r\n    LONG (__etext2)\r\n    LONG (__data2_start__)\r\n    LONG (__data2_end__ - __data2_start__)\r\n    __copy_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  \/* To clear multiple BSS sections,\r\n   * uncomment .zero.table section and,\r\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .zero.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __zero_table_start__ = .;\r\n    LONG (__bss_start__)\r\n    LONG (__bss_end__ - __bss_start__)\r\n    LONG (__bss2_start__)\r\n    LONG (__bss2_end__ - __bss2_start__)\r\n    __zero_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap (COPY):\r\n  {\r\n    __HeapBase = .;\r\n    PROVIDE(heap_low = .);\r\n    . = . + 16K;\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    KEEP(*(.heap*))\r\n    __HeapLimit = .;\r\n    PROVIDE(heap_top = .);\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy (COPY):\r\n  {\r\n    KEEP(*(.stack*))\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","old_contents":"\/* Linker script for Silicon Labs EFM32GG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 4.1.0 *\/\r\n\/*                                                                  *\/\r\n\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 20480K\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 8192K\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.vectors))\r\n    __Vectors_End = .;\r\n    __Vectors_Size = __Vectors_End - __Vectors;\r\n    __end__ = .;\r\n\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  \/* To copy multiple ROM to RAM sections,\r\n   * uncomment .copy.table section and,\r\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .copy.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __copy_table_start__ = .;\r\n    LONG (__etext)\r\n    LONG (__data_start__)\r\n    LONG (__data_end__ - __data_start__)\r\n    LONG (__etext2)\r\n    LONG (__data2_start__)\r\n    LONG (__data2_end__ - __data2_start__)\r\n    __copy_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  \/* To clear multiple BSS sections,\r\n   * uncomment .zero.table section and,\r\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .zero.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __zero_table_start__ = .;\r\n    LONG (__bss_start__)\r\n    LONG (__bss_end__ - __bss_start__)\r\n    LONG (__bss2_start__)\r\n    LONG (__bss2_end__ - __bss2_start__)\r\n    __zero_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap (COPY):\r\n  {\r\n    __HeapBase = .;\r\n    PROVIDE(heap_low = .);\r\n    . = . + 16K;\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    KEEP(*(.heap*))\r\n    __HeapLimit = .;\r\n    PROVIDE(heap_top = .);\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy (COPY):\r\n  {\r\n    KEEP(*(.stack*))\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"7fe29dcee96fed12d8f028cebb1bd6d6a9daacbc","subject":"soc: intel_s1000: change cached regions to write-through","message":"soc: intel_s1000: change cached regions to write-through\n\nThe i2s_cavs.c driver manipulates cache lines before commencing\nany DMA transfers. With write-back cache, if the DMA receive\nbuffer is not aligned to the cache lines, the data around\nthe buffer will be invalidated and may never written to memory.\nSince the driver takes an external memory slab as buffer and\nthere is no easy way to force cache line alignment on\nthe application side, set the cached region to write-through\nto avoid potential issue.\n\nFixes #13223\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"finikorg\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,ldts\/zephyr,Vudentz\/zephyr,ldts\/zephyr,nashif\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr","old_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <generated_dts_board.h>\n#include \"memory.h\"\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-through\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-through\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_s1000 = 0x1212fff2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    . = CONFIG_TEXT_SECTION_OFFSET;\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <generated_dts_board.h>\n#include \"memory.h\"\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-back\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_s1000 = 0x4242fff2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    . = CONFIG_TEXT_SECTION_OFFSET;\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7f4a31794e1111393f0bbf3c505c6fced566bd46","subject":"subsys: app_memory: Fixed incorrect linker syntax.","message":"subsys: app_memory: Fixed incorrect linker syntax.\n\nAny calculation based on linker variables shouldn't be inside\nsections.\nAlso added the linker macro needed for the shared memory.\n\nSigned-off-by: Adithya Baglody <06b44f6fa9a97a2b955c2d2cd070279967447860@intel.com>\n","repos":"explora26\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,ldts\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,punitvara\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,finikorg\/zephyr,ldts\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,ldts\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,explora26\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,ldts\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,punitvara\/zephyr,explora26\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN . = ALIGN(4);\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t_app_smem_end = .;\n\t\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t_app_smem_end = .;\n\t\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2c79ab4962976af3a856a3f68a1ddcea0544d483","subject":"mc1322x: increase the heap to 4K","message":"mc1322x: increase the heap to 4K\n","repos":"MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,arurke\/contiki","old_file":"cpu\/mc1322x\/mc1322x.lds","new_file":"cpu\/mc1322x\/mc1322x.lds","new_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\n\nMEMORY\n  {\n    ram (rwx) : org = 0x00400000, l = 96K\n  }\n\nSECTIONS\n{\n\nSYS_STACK_SIZE = 1024;\nIRQ_STACK_SIZE = 256;\nFIQ_STACK_SIZE = 256;\nSVC_STACK_SIZE = 256;\nABT_STACK_SIZE = 16;\nUND_STACK_SIZE = 16;\nHEAP_SIZE = 4096;\n\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x00400000); . = 0x00400000;\n  .text           :\n  {\n    *(.start)\n    *(.irq)\t\t\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  } =0\n\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n      *(.rela.ctors)\n      *(.rela.dtors)\n      *(.rela.got)\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n    }\n  .rel.plt        : { *(.rel.plt) }\n  .rela.plt       : { *(.rela.plt) }\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0\n  .plt            : { *(.plt) }\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n\n\/*  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); *\/\n\n\t. = ALIGN(4);\n\t. = DATA_SEGMENT_ALIGN(4,4); \n\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n  .init_array     :\n  {\n     PROVIDE_HIDDEN (__init_array_start = .);\n     KEEP (*(SORT(.init_array.*)))\n     KEEP (*(.init_array))\n     PROVIDE_HIDDEN (__init_array_end = .);\n  }\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  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{"commit":"52526932a864d970ae859b6bc636cec160e6e7d5","subject":"Revert \"hide symbols from statically linked stdlibc++\"","message":"Revert \"hide symbols from statically linked stdlibc++\"\n\nThis reverts commit bbb47c5082e5d6cc084ab2b2c6ec6cbf95aa8254.\n","repos":"mapycz\/python-mapnik,mapycz\/python-mapnik","old_file":"debian\/mapnik.lds","new_file":"debian\/mapnik.lds","new_contents":"","old_contents":"{\n    global:\n        *mapnik*;\n        datasource_name;\n        on_plugin_load;\n        create;\n\n        \/* https:\/\/gcc.gnu.org\/bugzilla\/show_bug.cgi?id=82172 *\/\n        _ZNSs4_Rep20_S_empty_rep_storageE;\n\n    local: *;\n};\n\n\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"a6a0a952428a209f6160ddb33627dc34aafb8337","subject":"Fix linker script","message":"Fix linker script\n","repos":"RustOS-Fork-Holding-Ground\/RustOS,ryanra\/RustOS","old_file":"src\/linker.ld","new_file":"src\/linker.ld","new_contents":"\/* Taken verbatim from http:\/\/wiki.osdev.org\/Bare_Bones *\/\n\/* The bootloader will look at this image and start execution at the symbol\n *designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n *kernel image. *\/\nSECTIONS\n{\n  \/* VGA, cannot use section for this *\/\n  . = 0xb8000;\n  vga_buffer = .;\n  . += 80 * 24 * 2;\n\n  \/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n   *loaded at by the bootloader. *\/\n  . = 1M;\n\n  \/* First put the multiboot header, as it is required to be put very early\n   * early in the image or the bootloader won't recognize the file format.\n   * Next we'll put the .text section. *\/\n  .text BLOCK(4K) : ALIGN(4K)\n  {\n    *(.multiboot)\n    *(.text)\n  }\n\n  \/* Read-only data. *\/\n  .rodata BLOCK(4K) : ALIGN(4K)\n  {\n    *(.rodata)\n  }\n\n  \/* Read-write data (initialized) *\/\n  .data BLOCK(4K) : ALIGN(4K)\n  {\n    *(.data)\n  }\n\n  \/* Read-write data (uninitialized) and stack *\/\n  .bss BLOCK(4K) : ALIGN(4K)\n  {\n    *(COMMON)\n    *(.bss)\n    *(.bootstrap_stack)\n  }\n\n  \/* The compiler may produce other sections, by default it will put them in\n   *a segment with the same name. Simply add stuff here as needed. *\/\n}\n","old_contents":"\/* Taken verbatim from http:\/\/wiki.osdev.org\/Bare_Bones *\/\n\/* The bootloader will look at this image and start execution at the symbol\n *designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n *kernel image. *\/\nSECTIONS\n{\n  \/* VGA Buffer *\/\n  .vga 0xb8000 : {\n    vga_buffer = .;\n    . += 80 * 24 * 2;\n  }\n\n  \/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n   *loaded at by the bootloader. *\/\n  . = 1M;\n\n  \/* First put the multiboot header, as it is required to be put very early\n   * early in the image or the bootloader won't recognize the file format.\n   * Next we'll put the .text section. *\/\n  .text BLOCK(4K) : ALIGN(4K)\n  {\n    *(.multiboot)\n    *(.text)\n  }\n\n  \/* Read-only data. *\/\n  .rodata BLOCK(4K) : ALIGN(4K)\n  {\n    *(.rodata)\n  }\n\n  \/* Read-write data (initialized) *\/\n  .data BLOCK(4K) : ALIGN(4K)\n  {\n    *(.data)\n  }\n\n  \/* Read-write data (uninitialized) and stack *\/\n  .bss BLOCK(4K) : ALIGN(4K)\n  {\n    *(COMMON)\n    *(.bss)\n    *(.bootstrap_stack)\n  }\n\n  \/* The compiler may produce other sections, by default it will put them in\n   *a segment with the same name. Simply add stuff here as needed. *\/\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1f9ae483b9dc302dda086984c817a474e38d3721","subject":"sam4l: move app binaries to text segment instead of data","message":"sam4l: move app binaries to text segment instead of data\n","repos":"google\/tock-on-titan,google\/tock-on-titan,google\/tock-on-titan","old_file":"src\/chips\/sam4l\/loader.ld","new_file":"src\/chips\/sam4l\/loader.ld","new_contents":"\/*\n * This file is part of StormLoader, the Storm Bootloader\n *\n * StormLoader is free software: you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation, either version 3 of the License, or\n * (at your option) any later version.\n *\n * StormLoader is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with Foobar.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n *  \n * Copyright 2014, Michael Andersen <m.andersen@eecs.berkeley.edu>\n *\n * This file is largely copied from the Atmel supplied linker scripts\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.) \n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nMEMORY\n{\n  rom (rx)  : ORIGIN = 0x00010000, LENGTH = 0x00070000\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _textstart = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        KEEP (*(.syscalls))\n\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _sapps = .;\n        *(.app.*)\n        _eapps = .;\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n    _textend = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n\n        . = ALIGN(8);\n        *(.app_memory)\n\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","old_contents":"\/*\n * This file is part of StormLoader, the Storm Bootloader\n *\n * StormLoader is free software: you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation, either version 3 of the License, or\n * (at your option) any later version.\n *\n * StormLoader is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with Foobar.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n *  \n * Copyright 2014, Michael Andersen <m.andersen@eecs.berkeley.edu>\n *\n * This file is largely copied from the Atmel supplied linker scripts\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.) \n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nMEMORY\n{\n  rom (rx)  : ORIGIN = 0x00010000, LENGTH = 0x00070000\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _textstart = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        KEEP (*(.syscalls))\n\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n    _textend = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n\n        . = ALIGN(4);\n        _sapps = .;\n        *(.app.*)\n        _eapps = .;\n\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n\n        . = ALIGN(8);\n        *(.app_memory)\n\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"808604214b1dd2067da08587032038f90adad046","subject":"mark ORIGIN(SRAM) in the linker script","message":"mark ORIGIN(SRAM) in the linker script\n\nThis generates a symbol that elf2tab uses to check for fixed addresses.\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to\n\t\t * mark the first address in the SRAM memory. Since ELF files do\n\t\t * not really need to specify this address as they only care about\n\t\t * loading into flash, we need to manually mark this address for\n\t\t * elf2tab. elf2tab will use it to add a fixed address header in the\n\t\t * TBF header if needed.\n\t\t *\/\n\t    _SRAM_ORIGIN = .;\n\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"279a95783e06e807997a15c4b9c85235d8a5766e","subject":"ld: move vector table into its own section","message":"ld: move vector table into its own section\n","repos":"japaric\/cu,japaric\/cu","old_file":"common.ld","new_file":"common.ld","new_contents":"__DATA_LOAD = LOADADDR(.data);\n\nSECTIONS\n{\n  .vector_table :\n  {\n    link_stack_pointer_start = .;\n    LONG(ORIGIN(SRAM) + LENGTH(SRAM))\n    link_stack_pointer_end = .;\n    link_reset_start = .;\n    KEEP(*(.reset))\n    link_reset_end = .;\n    link_exceptions_start = .;\n    KEEP(*(.exceptions))\n    link_exceptions_end = .;\n    link_interrupts_start = .;\n    KEEP(*(.interrupts))\n    link_interrupts_end = .;\n  } > FLASH\n\n  .text :\n  {\n    *(.text*)\n  } > FLASH\n\n  .data : ALIGN(4)\n  {\n    __DATA_START = .;\n    *(.data*)\n    . = ALIGN(4);\n    __DATA_END = .;\n  } > SRAM AT > FLASH\n\n  \/DISCARD\/ :\n  {\n    *(.ARM.exidx*)\n    *(.note.gnu.build-id*)\n  }\n}\n\n\/* Sanity checks *\/\nASSERT(link_stack_pointer_start == ORIGIN(FLASH), \"initial stack pointer value not where expected\");\nASSERT(link_reset_start - ORIGIN(FLASH) == 4, \"reset not where expected\");\nASSERT(link_exceptions_start - ORIGIN(FLASH) == 8, \"exceptions not where expected\");\nASSERT(link_interrupts_start - ORIGIN(FLASH) == 0x40, \"interrupts not where expected\");\nASSERT(link_stack_pointer_start < link_stack_pointer_end, \"initial stack pointer value not linked in\");\nASSERT(link_reset_start < link_reset_end, \"reset not linked in\");\nASSERT(link_exceptions_start < link_exceptions_end, \"exceptions not linked in\");\nASSERT( link_interrupts_start < link_interrupts_end, \"interrupts not linked in\");\n","old_contents":"__DATA_LOAD = LOADADDR(.data);\n\nSECTIONS\n{\n  .text : ALIGN(4)\n  {\n    link_stack_pointer_start = .;\n    LONG(ORIGIN(SRAM) + LENGTH(SRAM))\n    link_stack_pointer_end = .;\n    link_reset_start = .;\n    KEEP(*(.reset))\n    link_reset_end = .;\n    link_exceptions_start = .;\n    KEEP(*(.exceptions))\n    link_exceptions_end = .;\n    link_interrupts_start = .;\n    KEEP(*(.interrupts))\n    link_interrupts_end = .;\n    *(.text*)\n  } > FLASH\n\n  .data : ALIGN(4)\n  {\n    __DATA_START = .;\n    *(.data*)\n    . = ALIGN(4);\n    __DATA_END = .;\n  } > SRAM AT > FLASH\n\n  \/DISCARD\/ :\n  {\n    *(.ARM.exidx*)\n    *(.note.gnu.build-id*)\n  }\n}\n\n\/* Sanity checks *\/\nASSERT(link_stack_pointer_start == ORIGIN(FLASH), \"initial stack pointer value not where expected\");\nASSERT(link_reset_start - ORIGIN(FLASH) == 4, \"reset not where expected\");\nASSERT(link_exceptions_start - ORIGIN(FLASH) == 8, \"exceptions not where expected\");\nASSERT(link_interrupts_start - ORIGIN(FLASH) == 0x40, \"interrupts not where expected\");\nASSERT(link_stack_pointer_start < link_stack_pointer_end, \"initial stack pointer value not linked in\");\nASSERT(link_reset_start < link_reset_end, \"reset not linked in\");\nASSERT(link_exceptions_start < link_exceptions_end, \"exceptions not linked in\");\nASSERT( link_interrupts_start < link_interrupts_end, \"interrupts not linked in\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7defe62dfc320f419b4f359e7a6ac02cebff4895","subject":"Hide JPEG symbols on Darwin (to align with Linux)","message":"Hide JPEG symbols on Darwin (to align with Linux)\n","repos":"tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-tensorflow\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,paolodedios\/tensorflow,tensorflow\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,gautam1858\/tensorflow,Intel-Corporation\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,paolodedios\/tensorflow,paolodedios\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,yongtang\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,yongtang\/tensorflow,Intel-tensorflow\/tensorflow,gautam1858\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,paolodedios\/tensorflow,gautam1858\/tensorflow,yongtang\/tensorflow,yongtang\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow,karllessard\/tensorflow,yongtang\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,paolodedios\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,paolodedios\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-Corporation\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-Corporation\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,Intel-Corporation\/tensorflow,gautam1858\/tensorflow,Intel-Corporation\/tensorflow,gautam1858\/tensorflow,karllessard\/tensorflow,Intel-tensorflow\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,karllessard\/tensorflow,paolodedios\/tensorflow","old_file":"tensorflow\/tf_private_symbols.lds","new_file":"tensorflow\/tf_private_symbols.lds","new_contents":"jpeg_*\njinit_*\njdiv_round_up\njround_up\njzero_far\njcopy_*\njsimd_*\nhwloc_*\n*mlir*\n","old_contents":"*mlir*","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5b4389cf46acff8c9439456068ef0d9fae3ef34e","subject":"cpu\/esp32: update of ld script for littlefs*","message":"cpu\/esp32: update of ld script for littlefs*\n\nDuring the write access to the SPI flash, the IROM cache is not available and only code from the IRAM can be executed. Therefore, the code of file system implementations which access the SPI flash must reside in IRAM.","repos":"smlng\/RIOT,yogo1212\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,yogo1212\/RIOT,smlng\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,smlng\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,authmillenon\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,smlng\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,miri64\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,ant9000\/RIOT,authmillenon\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,basilfx\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,miri64\/RIOT,yogo1212\/RIOT,smlng\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,OTAkeys\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,yogo1212\/RIOT,kaspar030\/RIOT","old_file":"cpu\/esp32\/ld\/esp32.common.ld","new_file":"cpu\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *littlefs.a:*(.literal .text .literal.* .text.*)\n    *littlefs2.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of RIOT ports that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"8be113e4bd84f222b551f4e3646261e719f3f284","subject":"[fix] Update LDoc config (#5231)","message":"[fix] Update LDoc config (#5231)\n\nFollow-up to #5217.","repos":"Markismus\/koreader,koreader\/koreader,Hzj-jie\/koreader,poire-z\/koreader,koreader\/koreader,Frenzie\/koreader,NiLuJe\/koreader,NiLuJe\/koreader,mihailim\/koreader,mwoz123\/koreader,poire-z\/koreader,pazos\/koreader,Frenzie\/koreader","old_file":"doc\/config.ld","new_file":"doc\/config.ld","new_contents":"project = 'KOReader'\ndescription = 'Multi-platform ebook reader'\nfull_description = 'An ebook reader application supports PDF, DJVU, EPUB, FB2 and many more formats, running on Kindle, Kobo, PocketBook, Ubuntu Touch and Android devices.'\ntitle = 'KOReader Documentation'\ndir = 'html'\nstyle = '!fixed'\nuse_markdown_titles = true\ntopics = {\n    '..\/README.md',\n    '.\/Collaborating_with_Git.md',\n    '.\/DataStore.md',\n    '.\/Development_guide.md',\n    '.\/Events.md',\n    '.\/Hacking.md',\n    '.\/Porting.md',\n    '.\/Unit_tests.md',\n}\npackage = ''\nformat = 'markdown'\nsort_modules = true\nfile = {\n    '..\/frontend',\n    '..\/base\/ffi',\n}\n","old_contents":"project = 'KOReader'\ndescription = 'Multi-platform ebook reader'\nfull_description = 'An ebook reader application supports PDF, DJVU, EPUB, FB2 and many more formats, running on Kindle, Kobo, PocketBook, Ubuntu Touch and Android devices.'\ntitle = 'KOReader Documentation'\ndir = 'html'\nstyle = '!fixed'\nuse_markdown_titles = true\ntopics = {\n    '..\/README.md',\n    '.\/Collaborating with Git.md',\n    '.\/DataStore.md',\n    '.\/Development guide.md',\n    '.\/Events.md',\n    '.\/Hacking.md',\n    '.\/Porting.md',\n    '.\/Unit tests.md',\n}\npackage = ''\nformat = 'markdown'\nsort_modules = true\nfile = {\n    '..\/frontend',\n    '..\/base\/ffi',\n}\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"ddf6a279a5107c7d3389fa9c4fb38626ef463143","subject":"\u30b9\u30bf\u30c3\u30af\u306e\u30dd\u30a4\u30f3\u30bf\u30fc\u3092\u518d\u3073\u4fee\u6b63","message":"\u30b9\u30bf\u30c3\u30af\u306e\u30dd\u30a4\u30f3\u30bf\u30fc\u3092\u518d\u3073\u4fee\u6b63\n","repos":"hirakuni45\/R8C,hirakuni45\/R8C,hirakuni45\/R8C","old_file":"M120AN\/m120an.ld","new_file":"M120AN\/m120an.ld","new_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x0300, LENGTH = 0x0400\n\tROM (r)  : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVVEC (r) : ORIGIN = 0xFED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x07C0;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x0300, LENGTH = 0x0480\n\tROM (r)  : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVVEC (r) : ORIGIN = 0xFED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0740;\n\t\t_isp_init = 0x0780;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"ca39c7edd7c0793fbb7d52425f7c2e8eb8a90131","subject":"soc: esp32: linker: Fix backtrace for Invalid cache access exception","message":"soc: esp32: linker: Fix backtrace for Invalid cache access exception\n\nThis change moves .rodata for panic handler and fatal.c into DRAM\nMoves panic handler and its dependent functions into IRAM\n\nSigned-off-by: Shubham Kulkarni <1478dde7897089bf180c3c690a61b19b869e8abd@espressif.com>\n","repos":"zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\n\/* Global symbols required for espressif hal build *\/\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( esp32_rom_ets_printf = ets_printf );\nPROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );\n\n\/* __udivdi3 is exported using assignment, which declares strong symbols *\/\n__udivdi3 = 0x4000cff8;\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *  - Reserve memory region for BT controller library from ROM\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x30000\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n#if defined(CONFIG_NET_SOCKETS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_socket_register);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(settings_handler_static);\n    . = ALIGN(4);\n#endif\n\n    . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\n\/* Global symbols required for espressif hal build *\/\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( esp32_rom_ets_printf = ets_printf );\nPROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *  - Reserve memory region for BT controller library from ROM\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x30000\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#if defined(CONFIG_NET_SOCKETS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_socket_register);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(settings_handler_static);\n    . = ALIGN(4);\n#endif\n\n    . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"36f78fe05bdc1d6ffddef18b23a6f6bed9a47e04","subject":"Switches target.ld to the board directory.","message":"Switches target.ld to the board directory.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"applications\/bootloader\/targets\/nonos.xtensa.esp8266-32mbit\/target.ld","new_file":"applications\/bootloader\/targets\/nonos.xtensa.esp8266-32mbit\/target.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"c6ca24c584a5c93898e5abe43199ce27dec429d2","subject":"Removing blank space","message":"Removing blank space\n","repos":"tock\/libtock-rs","old_file":"boards\/layout_imxrt1050.ld","new_file":"boards\/layout_imxrt1050.ld","new_contents":"\/* Layout for the iMX.RT1050 board, used by the examples in this repository. *\/\n\nMEMORY {\n  \/* The application region is 64 bytes (0x40) *\/\n  FLASH (rx) : ORIGIN = 0x63002040, LENGTH = 0xFFFFC0\n  SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 112K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 8K;\n\nINCLUDE layout_generic.ld\n","old_contents":"\/* Layout for the iMX.RT1050 board, used by the examples in this repository. *\/\n\nMEMORY {\n  \/* The application region is 64 bytes (0x40) *\/\n  FLASH (rx) : ORIGIN = 0x63002040, LENGTH = 0xFFFFC0\n  SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 112K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 8K;\n\nINCLUDE layout_generic.ld\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"76267051eed2ffe1035a7c1ec41ee4db8792fc0f","subject":"soc: nxp_imx: Fix type in linker.ld","message":"soc: nxp_imx: Fix type in linker.ld\n\nFix typo where DT_REG_ADDR was used istead of DT_REG_SIZE in\nlinker script for i.MX RT socs and their ITCM and DTCM memories.\n\nSigned-off-by: Arvid Ros\u00e9n <54d6aadf1451517834b2b1daeb4f76a706da418f@softube.com>\n","repos":"Vudentz\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr","old_file":"soc\/arm\/nxp_imx\/rt\/linker.ld","new_file":"soc\/arm\/nxp_imx\/rt\/linker.ld","new_contents":"\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n #include <autoconf.h>\n #include <devicetree.h>\n\nMEMORY\n     {\n#if (DT_MMIO_SRAM_20200000_SIZE > 0) && !defined(CONFIG_DATA_OCRAM)\n        OCRAM  (wx) : ORIGIN = DT_MMIO_SRAM_20200000_BASE_ADDRESS, LENGTH = DT_MMIO_SRAM_20200000_SIZE\n#endif\n#if (DT_MMIO_SRAM_80000000_SIZE > 0) && !defined(CONFIG_DATA_SEMC)\n        SDRAM  (wx) : ORIGIN = DT_MMIO_SRAM_80000000_BASE_ADDRESS, LENGTH = DT_MMIO_SRAM_80000000_SIZE\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm)) > 0) && !defined(CONFIG_DATA_DTCM)\n        DTCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_dtcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm))\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_itcm)) > 0) && !defined(CONFIG_CODE_ITCM)\n        ITCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_itcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_itcm))\n#endif\n     }\n\n#include <arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld>\n","old_contents":"\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n #include <autoconf.h>\n #include <devicetree.h>\n\nMEMORY\n     {\n#if (DT_MMIO_SRAM_20200000_SIZE > 0) && !defined(CONFIG_DATA_OCRAM)\n        OCRAM  (wx) : ORIGIN = DT_MMIO_SRAM_20200000_BASE_ADDRESS, LENGTH = DT_MMIO_SRAM_20200000_SIZE\n#endif\n#if (DT_MMIO_SRAM_80000000_SIZE > 0) && !defined(CONFIG_DATA_SEMC)\n        SDRAM  (wx) : ORIGIN = DT_MMIO_SRAM_80000000_BASE_ADDRESS, LENGTH = DT_MMIO_SRAM_80000000_SIZE\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm)) > 0) && !defined(CONFIG_DATA_DTCM)\n        DTCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_dtcm)), LENGTH = DT_REG_ADDR(DT_INST(0, nxp_imx_dtcm))\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_itcm)) > 0) && !defined(CONFIG_CODE_ITCM)\n        ITCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_itcm)), LENGTH = DT_REG_ADDR(DT_INST(0, nxp_imx_itcm))\n#endif\n     }\n\n#include <arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld>\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a3205b8c9cabc77b0212d718066d8f42bc444617","subject":"Add correct scatter file values for STM32F4 target","message":"Add correct scatter file values for STM32F4 target\n\nChange-Id: Iee3b278d7cfa98b348d0d908bf62a21fcdcf1ace\n","repos":"paolodedios\/tensorflow,aam-at\/tensorflow,gautam1858\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,petewarden\/tensorflow,freedomtan\/tensorflow,yongtang\/tensorflow,freedomtan\/tensorflow,karllessard\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,annarev\/tensorflow,tensorflow\/tensorflow,petewarden\/tensorflow,cxxgtxy\/tensorflow,Intel-Corporation\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,freedomtan\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,aam-at\/tensorflow,annarev\/tensorflow,karllessard\/tensorflow,gautam1858\/tensorflow,gautam1858\/tensorflow,paolodedios\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow,sarvex\/tensorflow,paolodedios\/tensorflow,Intel-Corporation\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,sarvex\/tensorflow,Intel-tensorflow\/tensorflow,frreiss\/tensorflow-fred,Intel-Corporation\/tensorflow,freedomtan\/tensorflow,karllessard\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_saved_model,aam-at\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,aam-at\/tensorflow,aam-at\/tensorflow,gautam1858\/tensorflow,cxxgtxy\/tensorflow,petewarden\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,cxxgtxy\/tensorflow,freedomtan\/tensorflow,paolodedios\/tensorflow,paolodedios\/tensorflow,aam-at\/tensorflow,annarev\/tensorflow,yongtang\/tensorflow,aam-at\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,karllessard\/tensorflow,gautam1858\/tensorflow,cxxgtxy\/tensorflow,annarev\/tensorflow,Intel-Corporation\/tensorflow,frreiss\/tensorflow-fred,yongtang\/tensorflow,annarev\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,annarev\/tensorflow,Intel-tensorflow\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,petewarden\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,petewarden\/tensorflow,sarvex\/tensorflow,sarvex\/tensorflow,Intel-tensorflow\/tensorflow,aam-at\/tensorflow,paolodedios\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,gautam1858\/tensorflow,freedomtan\/tensorflow,frreiss\/tensorflow-fred,aam-at\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow,yongtang\/tensorflow,sarvex\/tensorflow,frreiss\/tensorflow-fred,karllessard\/tensorflow,karllessard\/tensorflow,freedomtan\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow,cxxgtxy\/tensorflow,frreiss\/tensorflow-fred,gautam1858\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-Corporation\/tensorflow,frreiss\/tensorflow-fred,Intel-Corporation\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,frreiss\/tensorflow-fred,Intel-tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,yongtang\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,paolodedios\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_tf_optimizer,petewarden\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-Corporation\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow,sarvex\/tensorflow,gautam1858\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,petewarden\/tensorflow,petewarden\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,cxxgtxy\/tensorflow,annarev\/tensorflow,sarvex\/tensorflow,gautam1858\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,yongtang\/tensorflow,freedomtan\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,paolodedios\/tensorflow,paolodedios\/tensorflow,cxxgtxy\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,tensorflow\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,sarvex\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,freedomtan\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,petewarden\/tensorflow","old_file":"tensorflow\/lite\/micro\/tools\/make\/targets\/stm32f4\/stm32f4.lds","new_file":"tensorflow\/lite\/micro\/tools\/make\/targets\/stm32f4\/stm32f4.lds","new_contents":"\/* Copyright 2020 Google Inc. All Rights Reserved.\n\nCopyright 2020 The TensorFlow Authors. All Rights Reserved.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n==============================================================================*\/\n\n\/* Define main entry point *\/\nENTRY(_main)\n\n\/* 256K of RAM and 2048K of FLASH. Source: *\/\n\/* https:\/\/github.com\/renode\/renode\/blob\/master\/platforms\/cpus\/stm32f4.repl*\/\nMEMORY {\n RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K\n FLASH (rx) : ORIGIN = 0x8000000, LENGTH =  2048K\n}\n\n\/* Compute where the stack ends rather than hard coding it *\/\n_ld_stack_end_addr = ORIGIN(RAM) + LENGTH(RAM);\n_ld_min_stack_size = 0x200;\n\nSECTIONS {\n\n\/* interrupt vector goes to top of flash *\/\n\n.interrupt_vector : {\n  . = ALIGN(4);\n  KEEP(*(.interrupt_vector))\n  . = ALIGN(4);\n} >FLASH\n\n\/* read only .text and .rodata go to flash *\/\n\n.text : {\n  . = ALIGN(4);\n  KEEP(*(.text.interrupt_handler))\n  *(.text*)\n} >FLASH\n\n.rodata : {\n  . = ALIGN(4);\n  *(.rodata*)\n  . = ALIGN(4);\n} >FLASH\n\n\/* read mwrite data needs to be stored in flash but copied to ram *\/\n.data : {\n  . = ALIGN(4);\n  _ld_data_load_dest_start = .; \/* export where to load from *\/\n  *(.data*)\n  . = ALIGN(4);\n  _ld_data_load_dest_stop = .; \/* export where to load from *\/\n} >RAM AT> FLASH\n_ld_data_load_source = LOADADDR(.data);\n\n\/* unitialized data section needs zero initialization *\/\n.bss :\n{\n  . = ALIGN(4);\n  _ld_bss_data_start = .;\n  *(.bss*)\n  . = ALIGN(4);\n  _ld_bss_data_stop = .;\n} >RAM\n\n._user_heap_stack :\n{\n  . = ALIGN(8);\n  . += _ld_min_stack_size;\n  PROVIDE(end = .);\n  . = ALIGN(8);\n} >RAM\n\n\/DISCARD\/ :\n{\n  libc.a (*)\n  libm.a (*)\n  libgcc.a (*)\n}\n\n}  \/* SECTIONS *\/\n","old_contents":"\/* Copyright 2020 Google Inc. All Rights Reserved.\n\nCopyright 2020 The TensorFlow Authors. All Rights Reserved.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n==============================================================================*\/\n\n\/* Copied and modified from: tensorflow\/lite\/micro\/tools\/make\/targets\/bluepill\/bluepill.lds\n\n*\/\n\n\/*\n * 0x00000000 - 0x07ffffff - aliased to flash or sys memory depending on BOOT jumpers.\n * 0x08000000 - 0x0801ffff - Flash.\n * 0x1ffff000 - 0x1ffff7ff - Boot firmware in system memory.\n * 0x1ffff800 - 0x1fffffff - Option bytes.\n * 0x20000000 - 0x20004fff - SRAM.\n * 0x40000000 - 0x40023400 - Peripherals\n *\/\n\n\/* Define main entry point *\/\nENTRY(_main)\n\n\/* 32K of RAM and 256K of FLASH *\/\nMEMORY {\nRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K\nFLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K\n}\n\n\/* Compute where the stack ends rather than hard coding it *\/\n_ld_stack_end_addr = ORIGIN(RAM) + LENGTH(RAM);\n_ld_min_stack_size = 0x200;\n\nSECTIONS {\n\n\/* interrupt vector goes to top of flash *\/\n\n.interrupt_vector : {\n  . = ALIGN(4);\n  KEEP(*(.interrupt_vector))\n  . = ALIGN(4);\n} >FLASH\n\n\/* read only .text and .rodata go to flash *\/\n\n.text : {\n  . = ALIGN(4);\n  KEEP(*(.text.interrupt_handler))\n  *(.text*)\n} >FLASH\n\n.rodata : {\n  . = ALIGN(4);\n  *(.rodata*)\n  . = ALIGN(4);\n} >FLASH\n\n\/* read mwrite data needs to be stored in flash but copied to ram *\/\n.data : {\n  . = ALIGN(4);\n  _ld_data_load_dest_start = .; \/* export where to load from *\/\n  *(.data*)\n  . = ALIGN(4);\n  _ld_data_load_dest_stop = .; \/* export where to load from *\/\n} >RAM AT> FLASH\n_ld_data_load_source = LOADADDR(.data);\n\n\/* unitialized data section needs zero initialization *\/\n.bss :\n{\n  . = ALIGN(4);\n  _ld_bss_data_start = .;\n  *(.bss*)\n  . = ALIGN(4);\n  _ld_bss_data_stop = .;\n} >RAM\n\n._user_heap_stack :\n{\n  . = ALIGN(8);\n  . += _ld_min_stack_size;\n  PROVIDE(end = .);\n  . = ALIGN(8);\n} >RAM\n\n\/DISCARD\/ :\n{\n  libc.a (*)\n  libm.a (*)\n  libgcc.a (*)\n}\n\n}  \/* SECTIONS *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d69b72017b4d33be8f0866aadfa482cf34eca709","subject":"Remove extra line from lpc\/iomem","message":"Remove extra line from lpc\/iomem\n","repos":"richo\/zinc,ntwyman\/zinc,mcoffin\/zinc,tempbottle\/zinc,phil-opp\/zinc,placrosse\/zinc,gapry\/zinc,hackndev\/zinc,posborne\/zinc,ryankurte\/zinc,tempbottle\/zinc,hackndev\/zinc,troplin\/zinc,mcoffin\/zinc,0xc0170\/zinc,ntwyman\/zinc,placrosse\/zinc,tempbottle\/zinc,placrosse\/zinc,aethaniel\/zinc,richo\/zinc,troplin\/zinc,hackndev\/zinc,richo\/zinc,ntwyman\/zinc,posborne\/zinc,farcaller\/zinc,darayus\/zinc,farcaller\/zinc,hugwijst\/zinc,hackndev\/zinc,tempbottle\/zinc,phil-opp\/zinc,farcaller\/zinc,hugwijst\/zinc,flxo\/zinc,troplin\/zinc,mcoffin\/zinc,aethaniel\/zinc,phil-opp\/zinc,posborne\/zinc,dirvine\/zinc,farcaller\/zinc,posborne\/zinc,ntwyman\/zinc,troplin\/zinc,hackndev\/zinc,0xc0170\/zinc,gapry\/zinc,darayus\/zinc,mcoffin\/zinc,ryankurte\/zinc,ryankurte\/zinc,dirvine\/zinc,ryankurte\/zinc,phil-opp\/zinc,dirvine\/zinc,placrosse\/zinc,phil-opp\/zinc,richo\/zinc,mcoffin\/zinc,tempbottle\/zinc,troplin\/zinc,ntwyman\/zinc,flxo\/zinc,dirvine\/zinc,richo\/zinc,farcaller\/zinc,dirvine\/zinc,posborne\/zinc,placrosse\/zinc,ryankurte\/zinc","old_file":"src\/hal\/lpc17xx\/iomem.ld","new_file":"src\/hal\/lpc17xx\/iomem.ld","new_contents":"INCLUDE .\/src\/hal\/cortex_m3\/armmem.ld\n\nPROVIDE(isr_wdt           = isr_default_fault);\nPROVIDE(isr_timer_0       = isr_default_fault);\nPROVIDE(isr_timer_1       = isr_default_fault);\nPROVIDE(isr_timer_2       = isr_default_fault);\nPROVIDE(isr_timer_3       = isr_default_fault);\nPROVIDE(isr_uart_0        = isr_default_fault);\nPROVIDE(isr_uart_1        = isr_default_fault);\nPROVIDE(isr_uart_2        = isr_default_fault);\nPROVIDE(isr_uart_3        = isr_default_fault);\nPROVIDE(isr_pwm_1         = isr_default_fault);\nPROVIDE(isr_i2c_0         = isr_default_fault);\nPROVIDE(isr_i2c_1         = isr_default_fault);\nPROVIDE(isr_i2c_2         = isr_default_fault);\nPROVIDE(isr_spi           = isr_default_fault);\nPROVIDE(isr_ssp_0         = isr_default_fault);\nPROVIDE(isr_ssp_1         = isr_default_fault);\nPROVIDE(isr_pll_0         = isr_default_fault);\nPROVIDE(isr_rtc           = isr_default_fault);\nPROVIDE(isr_eint_0        = isr_default_fault);\nPROVIDE(isr_eint_1        = isr_default_fault);\nPROVIDE(isr_eint_2        = isr_default_fault);\nPROVIDE(isr_eint_3        = isr_default_fault);\nPROVIDE(isr_adc           = isr_default_fault);\nPROVIDE(isr_bod           = isr_default_fault);\nPROVIDE(isr_usb           = isr_default_fault);\nPROVIDE(isr_can           = isr_default_fault);\nPROVIDE(isr_dma           = isr_default_fault);\nPROVIDE(isr_i2s           = isr_default_fault);\nPROVIDE(isr_enet          = isr_default_fault);\nPROVIDE(isr_rit           = isr_default_fault);\nPROVIDE(isr_mcpwm         = isr_default_fault);\nPROVIDE(isr_qei           = isr_default_fault);\nPROVIDE(isr_pll_1         = isr_default_fault);\nPROVIDE(isr_usb_activity  = isr_default_fault);\nPROVIDE(isr_can_activity  = isr_default_fault);\n\niomem_GPIO0     = 0x2009C000;\niomem_GPIO1     = 0x2009C020;\niomem_GPIO2     = 0x2009C040;\niomem_GPIO3     = 0x2009C060;\niomem_GPIO4     = 0x2009C080;\n\niomem_TIMER0    = 0x40004000;\niomem_TIMER1    = 0x40008000;\n\niomem_UART0     = 0x4000C000;\n\niomem_PINSEL0   = 0x4002C000;\niomem_PINSEL1   = 0x4002C004;\niomem_PINSEL2   = 0x4002C008;\niomem_PINSEL3   = 0x4002C00C;\niomem_PINSEL4   = 0x4002C010;\niomem_PINSEL7   = 0x4002C01C;\niomem_PINSEL9   = 0x4002C024;\niomem_PINSEL10  = 0x4002C028;\n\niomem_SSP1      = 0x40030000;\niomem_SSP0      = 0x40088000;\n\niomem_TIMER2    = 0x40090000;\niomem_TIMER3    = 0x40094000;\n\niomem_UART2     = 0x40098000;\niomem_UART3     = 0x4009C000;\n\niomem_FLASHCFG  = 0x400FC000;\n\niomem_PLL0CON   = 0x400FC080;\niomem_PLL0CFG   = 0x400FC084;\niomem_PLL0STAT  = 0x400FC088;\niomem_PLL0FEED  = 0x400FC08C;\n\niomem_PCONP     = 0x400FC0C4;\n\niomem_CCLKCFG   = 0x400FC104;\niomem_CLKSRCSEL = 0x400FC10C;\n\niomem_PCLKSEL0  = 0x400FC1A8;\niomem_PCLKSEL1  = 0x400FC1AC;\n\niomem_SCS       = 0x400FC1A0;\n","old_contents":"INCLUDE .\/src\/hal\/cortex_m3\/armmem.ld\n\nPROVIDE(isr_nmi           = isr_default_fault);\nPROVIDE(isr_wdt           = isr_default_fault);\nPROVIDE(isr_timer_0       = isr_default_fault);\nPROVIDE(isr_timer_1       = isr_default_fault);\nPROVIDE(isr_timer_2       = isr_default_fault);\nPROVIDE(isr_timer_3       = isr_default_fault);\nPROVIDE(isr_uart_0        = isr_default_fault);\nPROVIDE(isr_uart_1        = isr_default_fault);\nPROVIDE(isr_uart_2        = isr_default_fault);\nPROVIDE(isr_uart_3        = isr_default_fault);\nPROVIDE(isr_pwm_1         = isr_default_fault);\nPROVIDE(isr_i2c_0         = isr_default_fault);\nPROVIDE(isr_i2c_1         = isr_default_fault);\nPROVIDE(isr_i2c_2         = isr_default_fault);\nPROVIDE(isr_spi           = isr_default_fault);\nPROVIDE(isr_ssp_0         = isr_default_fault);\nPROVIDE(isr_ssp_1         = isr_default_fault);\nPROVIDE(isr_pll_0         = isr_default_fault);\nPROVIDE(isr_rtc           = isr_default_fault);\nPROVIDE(isr_eint_0        = isr_default_fault);\nPROVIDE(isr_eint_1        = isr_default_fault);\nPROVIDE(isr_eint_2        = isr_default_fault);\nPROVIDE(isr_eint_3        = isr_default_fault);\nPROVIDE(isr_adc           = isr_default_fault);\nPROVIDE(isr_bod           = isr_default_fault);\nPROVIDE(isr_usb           = isr_default_fault);\nPROVIDE(isr_can           = isr_default_fault);\nPROVIDE(isr_dma           = isr_default_fault);\nPROVIDE(isr_i2s           = isr_default_fault);\nPROVIDE(isr_enet          = isr_default_fault);\nPROVIDE(isr_rit           = isr_default_fault);\nPROVIDE(isr_mcpwm         = isr_default_fault);\nPROVIDE(isr_qei           = isr_default_fault);\nPROVIDE(isr_pll_1         = isr_default_fault);\nPROVIDE(isr_usb_activity  = isr_default_fault);\nPROVIDE(isr_can_activity  = isr_default_fault);\n\niomem_GPIO0     = 0x2009C000;\niomem_GPIO1     = 0x2009C020;\niomem_GPIO2     = 0x2009C040;\niomem_GPIO3     = 0x2009C060;\niomem_GPIO4     = 0x2009C080;\n\niomem_TIMER0    = 0x40004000;\niomem_TIMER1    = 0x40008000;\n\niomem_UART0     = 0x4000C000;\n\niomem_PINSEL0   = 0x4002C000;\niomem_PINSEL1   = 0x4002C004;\niomem_PINSEL2   = 0x4002C008;\niomem_PINSEL3   = 0x4002C00C;\niomem_PINSEL4   = 0x4002C010;\niomem_PINSEL7   = 0x4002C01C;\niomem_PINSEL9   = 0x4002C024;\niomem_PINSEL10  = 0x4002C028;\n\niomem_SSP1      = 0x40030000;\niomem_SSP0      = 0x40088000;\n\niomem_TIMER2    = 0x40090000;\niomem_TIMER3    = 0x40094000;\n\niomem_UART2     = 0x40098000;\niomem_UART3     = 0x4009C000;\n\niomem_FLASHCFG  = 0x400FC000;\n\niomem_PLL0CON   = 0x400FC080;\niomem_PLL0CFG   = 0x400FC084;\niomem_PLL0STAT  = 0x400FC088;\niomem_PLL0FEED  = 0x400FC08C;\n\niomem_PCONP     = 0x400FC0C4;\n\niomem_CCLKCFG   = 0x400FC104;\niomem_CLKSRCSEL = 0x400FC10C;\n\niomem_PCLKSEL0  = 0x400FC1A8;\niomem_PCLKSEL1  = 0x400FC1AC;\n\niomem_SCS       = 0x400FC1A0;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"fb5b9adb2dac139598e27d132649b6caa76aef3f","subject":"nrf\/boards\/common.ld: Add ENTRY(Reset_Handler) in linker script.","message":"nrf\/boards\/common.ld: Add ENTRY(Reset_Handler) in linker script.\n\nIt's not strictly needed but can be helpful when using a debugger.\n","repos":"pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython","old_file":"ports\/nrf\/boards\/common.ld","new_file":"ports\/nrf\/boards\/common.ld","new_contents":"ENTRY(Reset_Handler)\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n        *(.text)             \/* .text sections (code) *\/\n        *(.text*)            \/* .text* sections (code) *\/\n        *(.rodata)           \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)          \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/      \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/      \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;          \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n\n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n\n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT>FLASH_TEXT\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\/* Define heap and stack areas *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n","old_contents":"\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n        *(.text)             \/* .text sections (code) *\/\n        *(.text*)            \/* .text* sections (code) *\/\n        *(.rodata)           \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)          \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/      \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/      \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;          \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n\n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n\n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT>FLASH_TEXT\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\/* Define heap and stack areas *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7cbe74adb1f15e5472bee91264dd145e7f4a5a01","subject":"intel_adsp: cavs: Add variables used in coredump","message":"intel_adsp: cavs: Add variables used in coredump\n\nIn order to coredump dump the ram memory, it is necessary that we define\nin the linker scripts two variable to indicate the start and the end of\nthe ram area. Adding these variables to cavs linker script.\n\nSigned-off-by: Flavio Ceolin <979b9165500b0741b9d0500e2efd74fc1547bff7@intel.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <zephyr\/devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <zephyr\/linker\/sections.h>\n#include <cavs-vectors.h>\n#include <adsp_memory.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n    _imr_end = .;\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int6_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int6_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_ram_start = .;\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.initcall)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <zephyr\/linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <zephyr\/linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n    _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  \/* Heap start and end markers.  Mostly unused, though newlib likes them *\/\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n    _image_ram_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <zephyr\/devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <zephyr\/linker\/sections.h>\n#include <cavs-vectors.h>\n#include <adsp_memory.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n    _imr_end = .;\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int6_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int6_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.initcall)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <zephyr\/linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <zephyr\/linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n    _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  \/* Heap start and end markers.  Mostly unused, though newlib likes them *\/\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"639cc4f3d22020eaa1faa24e5d691dcc7626fc8c","subject":"page-aligned various sections","message":"page-aligned various sections\n","repos":"CRust-OS\/CRust-OS,CRust-OS\/CRust-OS,CRust-OS\/CRust-OS,CRust-OS\/CRust-OS","old_file":"crust.lds","new_file":"crust.lds","new_contents":"ENTRY(_start)\nSECTIONS {\n    .bss : ALIGN(0x1000) {\n        HYPERCALL_PAGE = .;\n        . += 0x1000;\n        STACK_TOP = .;\n        . += 0x2000;\n        STACK_BOTTOM = .;\n        *(.bss);\n        *(.bss.*);\n    }\n    .text : ALIGN(0x1000) {\n        *(.text);\n        *(.text.*);\n    }\n    .data : ALIGN(0x1000) {\n        *(.data);\n        *(.data.*);\n    }\n    .note : {\n        *(.note);\n        *(.note.*);\n    }\n}\n","old_contents":"ENTRY(_start)\nSECTIONS {\n    .bss : ALIGN(0x1000) {\n        HYPERCALL_PAGE = .;\n        . += 0x1000;\n        STACK_TOP = .;\n        . += 0x2000;\n        STACK_BOTTOM = .;\n        *(.bss);\n        *(.bss.*);\n    }\n    .text : {\n        *(.text);\n        *(.text.*);\n    }\n    .data : {\n        *(.data);\n        *(.data.*);\n    }\n    .note : {\n        *(.note);\n        *(.note.*);\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"964bf935a39498e7224657787b0be277279d2bae","subject":"esp8266\/esp8266_common.ld: Put .text of more libs into .irom0.text .","message":"esp8266\/esp8266_common.ld: Put .text of more libs into .irom0.text .\n\nRecent vendor SDKs ship libs with code in .text section, which previously\nwas going into .irom0.text. Adjust the linker script to route these\nsections back to iROM (follows upstream change).\n","repos":"torwag\/micropython,ryannathans\/micropython,ryannathans\/micropython,lowRISC\/micropython,pfalcon\/micropython,dmazzella\/micropython,swegener\/micropython,adafruit\/circuitpython,AriZuu\/micropython,torwag\/micropython,selste\/micropython,lowRISC\/micropython,AriZuu\/micropython,kerneltask\/micropython,blazewicz\/micropython,henriknelson\/micropython,MrSurly\/micropython,pozetroninc\/micropython,pozetroninc\/micropython,kerneltask\/micropython,kerneltask\/micropython,MrSurly\/micropython,tobbad\/micropython,pozetroninc\/micropython,trezor\/micropython,adafruit\/circuitpython,bvernoux\/micropython,blazewicz\/micropython,MrSurly\/micropython,MrSurly\/micropython,AriZuu\/micropython,adafruit\/circuitpython,tralamazza\/micropython,pfalcon\/micropython,adafruit\/micropython,lowRISC\/micropython,henriknelson\/micropython,pramasoul\/micropython,kerneltask\/micropython,adafruit\/micropython,infinnovation\/micropython,selste\/micropython,infinnovation\/micropython,infinnovation\/micropython,blazewicz\/micropython,adafruit\/micropython,tobbad\/micropython,pfalcon\/micropython,pozetroninc\/micropython,selste\/micropython,infinnovation\/micropython,pozetroninc\/micropython,ryannathans\/micropython,bvernoux\/micropython,AriZuu\/micropython,ryannathans\/micropython,AriZuu\/micropython,torwag\/micropython,bvernoux\/micropython,swegener\/micropython,adafruit\/micropython,adafruit\/circuitpython,pramasoul\/micropython,trezor\/micropython,lowRISC\/micropython,torwag\/micropython,ryannathans\/micropython,tralamazza\/micropython,tralamazza\/micropython,trezor\/micropython,torwag\/micropython,adafruit\/micropython,MrSurly\/micropython,tobbad\/micropython,adafruit\/circuitpython,pramasoul\/micropython,swegener\/micropython,swegener\/micropython,trezor\/micropython,infinnovation\/micropython,lowRISC\/micropython,tralamazza\/micropython,kerneltask\/micropython,adafruit\/circuitpython,bvernoux\/micropython,pramasoul\/micropython,henriknelson\/micropython,blazewicz\/micropython,blazewicz\/micropython,dmazzella\/micropython,bvernoux\/micropython,swegener\/micropython,dmazzella\/micropython,dmazzella\/micropython,pfalcon\/micropython,henriknelson\/micropython,pramasoul\/micropython,pfalcon\/micropython,selste\/micropython,henriknelson\/micropython,tobbad\/micropython,trezor\/micropython,selste\/micropython,tobbad\/micropython","old_file":"ports\/esp8266\/esp8266_common.ld","new_file":"ports\/esp8266\/esp8266_common.ld","new_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* Vendor SDK in v2.1.0-7-gb8fd588 started to build these with\n           -ffunction-sections -fdata-sections, and require routing to\n           irom via linker:\n           https:\/\/github.com\/espressif\/ESP8266_NONOS_SDK\/commit\/b8fd588a33f0319dc135523b51655e97b483b205\n         *\/\n\n        *libcrypto.a:(.literal.* .text.*)\n        *libnet80211.a:(.literal.* .text.*)\n        *libwpa.a:(.literal.* .text.*)\n        *libwpa2.a:(.literal.* .text.*)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* 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*py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        build\/main.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        build\/main.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"304a96d7d611f6d585b2a6be504b19ef92b50c4c","subject":"esp8266: Put more literal and text obj data in irom0_0_seg.","message":"esp8266: Put more literal and text obj data in irom0_0_seg.\n\nWith newer versions of esp_iot_sdk the iram1_0_seg started to overflow.\nNow it doesn't.\n\nAddresses issue #1254.\n","repos":"vitiral\/micropython,deshipu\/micropython,hosaka\/micropython,Timmenem\/micropython,MrSurly\/micropython,hosaka\/micropython,noahchense\/micropython,turbinenreiter\/micropython,matthewelse\/micropython,ericsnowcurrently\/micropython,xyb\/micropython,mgyenik\/micropython,neilh10\/micropython,alex-march\/micropython,rubencabrera\/micropython,jlillest\/micropython,skybird6672\/micropython,toolmacher\/micropython,jmarcelino\/pycom-micropython,cloudformdesign\/micropython,neilh10\/micropython,mgyenik\/micropython,danicampora\/micropython,Peetz0r\/micropython-esp32,misterdanb\/micropython,ruffy91\/micropython,praemdonck\/micropython,deshipu\/micropython,pozetroninc\/micropython,ericsnowcurrently\/micropython,ernesto-g\/micropython,adafruit\/micropython,noahwilliamsson\/micropython,dmazzella\/micropython,tdautc19841202\/micropython,EcmaXp\/micropython,xyb\/micropython,MrSurly\/micropython,xuxiaoxin\/micropython,kostyll\/micropython,dinau\/micropython,emfcamp\/micropython,infinnovation\/micropython,feilongfl\/micropython,alex-robbins\/micropython,ceramos\/micropython,skybird6672\/micropython,mhoffma\/micropython,xyb\/micropython,danicampora\/micropython,suda\/micropython,deshipu\/micropython,noahchense\/micropython,PappaPeppar\/micropython,jlillest\/micropython,PappaPeppar\/micropython,adamkh\/micropython,danicampora\/micropython,dhylands\/micropython,mhoffma\/micropython,noahchense\/micropython,jlillest\/micropython,torwag\/micropython,noahwilliamsson\/micropython,tralamazza\/micropython,torwag\/micropython,pfalcon\/micropython,ceramos\/micropython,vriera\/micropython,supergis\/micropython,Timmenem\/micropython,galenhz\/micropython,supergis\/micropython,xuxiaoxin\/micropython,ernesto-g\/micropython,ganshun666\/micropython,Peetz0r\/micropython-esp32,xhat\/micropython,alex-robbins\/micropython,HenrikSolver\/micropython,henriknelson\/micropython,vitiral\/micropython,lowRISC\/micropython,hiway\/micropython,bvernoux\/micropython,pfalcon\/micropython,dxxb\/micropython,puuu\/micropython,ceramos\/micropython,torwag\/micropython,vriera\/micropython,utopiaprince\/micropython,cloudformdesign\/micropython,Peetz0r\/micropython-esp32,kostyll\/micropython,dhylands\/micropython,turbinenreiter\/micropython,MrSurly\/micropython,EcmaXp\/micropython,dmazzella\/micropython,adamkh\/micropython,skybird6672\/micropython,xuxiaoxin\/micropython,misterdanb\/micropython,hiway\/micropython,ahotam\/micropython,ryannathans\/micropython,dmazzella\/micropython,chrisdearman\/micropython,lowRISC\/micropython,pozetroninc\/micropython,ryannathans\/micropython,alex-robbins\/micropython,mianos\/micropython,blazewicz\/micropython,ruffy91\/micropython,toolmacher\/micropython,tdautc19841202\/micropython,cnoviello\/micropython,ChuckM\/micropython,mpalomer\/micropython,tobbad\/micropython,puuu\/micropython,hosaka\/micropython,adafruit\/micropython,supergis\/micropython,feilongfl\/micropython,infinnovation\/micropython,oopy\/micropython,dhylands\/micropython,HenrikSolver\/micropython,blmorris\/micropython,ganshun666\/micropython,turbinenreiter\/micropython,ceramos\/micropython,lbattraw\/micropython,tralamazza\/micropython,tobbad\/micropython,stonegithubs\/micropython,ChuckM\/micropython,martinribelotta\/micropython,kostyll\/micropython,adafruit\/circuitpython,emfcamp\/micropython,jlillest\/micropython,cwyark\/micropython,SHA2017-badge\/micropython-esp32,alex-robbins\/micropython,infinnovation\/micropython,drrk\/micropython,turbinenreiter\/micropython,ceramos\/micropython,omtinez\/micropython,mianos\/micropython,neilh10\/micropython,xuxiaoxin\/micropython,pramasoul\/micropython,mgyenik\/micropython,tobbad\/micropython,noahwilliamsson\/micropython,pfalcon\/micropython,ahotam\/micropython,redbear\/micropython,misterdanb\/micropython,MrSurly\/micropython,hiway\/micropython,hosaka\/micropython,tralamazza\/micropython,swegener\/micropython,emfcamp\/micropython,selste\/micropython,alex-march\/micropython,matthewelse\/micropython,mpalomer\/micropython,dxxb\/micropython,suda\/micropython,cnoviello\/micropython,Timmenem\/micropython,bvernoux\/micropython,jlillest\/micropython,vitiral\/micropython,omtinez\/micropython,kerneltask\/micropython,henriknelson\/micropython,ganshun666\/micropython,adafruit\/circuitpython,redbear\/micropython,oopy\/micropython,adamkh\/micropython,HenrikSolver\/micropython,mgyenik\/micropython,dinau\/micropython,trezor\/micropython,mianos\/micropython,feilongfl\/micropython,torwag\/micropython,redbear\/micropython,tdautc19841202\/micropython,MrSurly\/micropython-esp32,xhat\/micropython,micropython\/micropython-esp32,torwag\/micropython,lbattraw\/micropython,suda\/micropython,emfcamp\/micropython,drrk\/micropython,tobbad\/micropython,supergis\/micropython,adamkh\/micropython,pramasoul\/micropython,SHA2017-badge\/micropython-esp32,cwyark\/micropython,TDAbboud\/micropython,oopy\/micropython,danicampora\/micropython,ahotam\/micropython,selste\/micropython,bvernoux\/micropython,jimkmc\/micropython,omtinez\/micropython,dinau\/micropython,cwyark\/micropython,ericsnowcurrently\/micropython,noahwilliamsson\/micropython,mhoffma\/micropython,orionrobots\/micropython,adafruit\/micropython,PappaPeppar\/micropython,cnoviello\/micropython,firstval\/micropython,blazewicz\/micropython,puuu\/micropython,stonegithubs\/micropython,MrSurly\/micropython-esp32,rubencabrera\/micropython,orionrobots\/micropython,ryannathans\/micropython,TDAbboud\/micropython,swegener\/micropython,ruffy91\/micropython,adamkh\/micropython,toolmacher\/micropython,Timmenem\/micropython,drrk\/micropython,firstval\/micropython,redbear\/micropython,AriZuu\/micropython,adafruit\/micropython,oopy\/micropython,matthewelse\/micropython,mianos\/micropython,Peetz0r\/micropython-esp32,slzatz\/micropython,ericsnowcurrently\/micropython,heisewangluo\/micropython,dhylands\/micropython,jimkmc\/micropython,swegener\/micropython,vriera\/micropython,mpalomer\/micropython,tuc-osg\/micropython,ernesto-g\/micropython,jimkmc\/micropython,MrSurly\/micropython-esp32,orionrobots\/micropython,xhat\/micropython,trezor\/micropython,micropython\/micropython-esp32,rubencabrera\/micropython,kostyll\/micropython,kerneltask\/micropython,pozetroninc\/micropython,lowRISC\/micropython,firstval\/micropython,slzatz\/micropython,orionrobots\/micropython,martinribelotta\/micropython,tuc-osg\/micropython,micropython\/micropython-esp32,mianos\/micropython,mhoffma\/micropython,deshipu\/micropython,feilongfl\/micropython,hiway\/micropython,martinribelotta\/micropython,pfalcon\/micropython,noahchense\/micropython,blazewicz\/micropython,deshipu\/micropython,micropython\/micropython-esp32,vriera\/micropython,praemdonck\/micropython,vitiral\/micropython,jimkmc\/micropython,MrSurly\/micropython-esp32,mpalomer\/micropython,xyb\/micropython,martinribelotta\/micropython,cnoviello\/micropython,vitiral\/micropython,chrisdearman\/micropython,kerneltask\/micropython,xhat\/micropython,galenhz\/micropython,ganshun666\/micropython,ernesto-g\/micropython,AriZuu\/micropython,danicampora\/micropython,galenhz\/micropython,trezor\/micropython,blazewicz\/micropython,Timmenem\/micropython,tuc-osg\/micropython,dinau\/micropython,pramasoul\/micropython,slzatz\/micropython,swegener\/micropython,mpalomer\/micropython,micropython\/micropython-esp32,tobbad\/micropython,TDAbboud\/micropython,dxxb\/micropython,kostyll\/micropython,drrk\/micropython,SHA2017-badge\/micropython-esp32,alex-march\/micropython,chrisdearman\/micropython,blazewicz\/micropython,AriZuu\/micropython,tdautc19841202\/micropython,adafruit\/circuitpython,ruffy91\/micropython,slzatz\/micropython,ChuckM\/micropython,cloudformdesign\/micropython,galenhz\/micropython,stonegithubs\/micropython,stonegithubs\/micropython,blmorris\/micropython,kerneltask\/micropython,lbattraw\/micropython,jmarcelino\/pycom-micropython,MrSurly\/micropython,puuu\/micropython,cwyark\/micropython,utopiaprince\/micropython,stonegithubs\/micropython,adafruit\/micropython,matthewelse\/micropython,heisewangluo\/micropython,tralamazza\/micropython,jmarcelino\/pycom-micropython,alex-robbins\/micropython,trezor\/micropython,selste\/micropython,matthewelse\/micropython,SHA2017-badge\/micropython-esp32,slzatz\/micropython,dhylands\/micropython,chrisdearman\/micropython,pramasoul\/micropython,drrk\/micropython,emfcamp\/micropython,praemdonck\/micropython,praemdonck\/micropython,misterdanb\/micropython,praemdonck\/micropython,lowRISC\/micropython,AriZuu\/micropython,matthewelse\/micropython,blmorris\/micropython,ruffy91\/micropython,PappaPeppar\/micropython,ernesto-g\/micropython,redbear\/micropython,ahotam\/micropython,oopy\/micropython,supergis\/micropython,heisewangluo\/micropython,firstval\/micropython,rubencabrera\/micropython,adafruit\/circuitpython,HenrikSolver\/micropython,swegener\/micropython,mhoffma\/micropython,utopiaprince\/micropython,noahwilliamsson\/micropython,ChuckM\/micropython,infinnovation\/micropython,HenrikSolver\/micropython,lbattraw\/micropython,PappaPeppar\/micropython,misterdanb\/micropython,ChuckM\/micropython,noahchense\/micropython,utopiaprince\/micropython,martinribelotta\/micropython,ryannathans\/micropython,lowRISC\/micropython,omtinez\/micropython,skybird6672\/micropython,pramasoul\/micropython,ryannathans\/micropython,cloudformdesign\/micropython,trezor\/micropython,bvernoux\/micropython,tdautc19841202\/micropython,SHA2017-badge\/micropython-esp32,jmarcelino\/pycom-micropython,xuxiaoxin\/micropython,blmorris\/micropython,xyb\/micropython,blmorris\/micropython,henriknelson\/micropython,toolmacher\/micropython,MrSurly\/micropython-esp32,bvernoux\/micropython,TDAbboud\/micropython,tuc-osg\/micropython,orionrobots\/micropython,skybird6672\/micropython,alex-march\/micropython,puuu\/micropython,selste\/micropython,dxxb\/micropython,EcmaXp\/micropython,kerneltask\/micropython,utopiaprince\/micropython,ganshun666\/micropython,turbinenreiter\/micropython,AriZuu\/micropython,henriknelson\/micropython,firstval\/micropython,adafruit\/circuitpython,jimkmc\/micropython,EcmaXp\/micropython,lbattraw\/micropython,rubencabrera\/micropython,pozetroninc\/micropython,cwyark\/micropython,cnoviello\/micropython,dinau\/micropython,heisewangluo\/micropython,xhat\/micropython,cloudformdesign\/micropython,suda\/micropython,neilh10\/micropython,pozetroninc\/micropython,henriknelson\/micropython,toolmacher\/micropython,EcmaXp\/micropython,tuc-osg\/micropython,galenhz\/micropython,adafruit\/circuitpython,alex-march\/micropython,dmazzella\/micropython,pfalcon\/micropython,neilh10\/micropython,heisewangluo\/micropython,TDAbboud\/micropython,chrisdearman\/micropython,mgyenik\/micropython,Peetz0r\/micropython-esp32,ericsnowcurrently\/micropython,omtinez\/micropython,vriera\/micropython,hiway\/micropython,suda\/micropython,hosaka\/micropython,ahotam\/micropython,dxxb\/micropython,feilongfl\/micropython,infinnovation\/micropython,selste\/micropython,jmarcelino\/pycom-micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n        *py\/*.o*(.literal* .text*)\n        *pyexec.o(.literal*, .text*)\n        *readline.o(.literal*, .text*)\n        *pybstdio.o(.literal*, .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *py\/*.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *py\/*.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *py\/*.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n        *py\/*.o*(.literal* .text*)\n        *pyexec.o(.literal*, .text*)\n        *readline.o(.literal*, .text*)\n        *pybstdio.o(.literal*, .text*)\n        *modpyb.o(.literal*, .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *modesp.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *py\/*.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *py\/*.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *py\/*.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"10480b0e537df0b9d429db3ceb58215dbe579ce6","subject":"Fix comments in S110 linker script.","message":"Fix comments in S110 linker script.\n","repos":"jf87\/nrf51-pure-gcc-setup","old_file":"template\/gcc_nrf51_s110.ld","new_file":"template\/gcc_nrf51_s110.ld","new_contents":"\/* Linker script to configure memory regions. *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x14000, LENGTH = 0x26000 \/* 80 kB is taken by S110, 176 kB for app. *\/\r\n  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 \/* 8 kB is taken by S110,8 kB for app. *\/\r\n}\r\nINCLUDE \"gcc_nrf51_common.ld\"\r\n","old_contents":"\/* Linker script to configure memory regions. *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x14000, LENGTH = 0x26000 \/* 128k, 128k is taken by S110 *\/\r\n  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 \/* 8k, 8k is taken by S110 *\/\r\n}\r\nINCLUDE \"gcc_nrf51_common.ld\"\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"efc07fd1613ee14392631115616c14c1de9c54ec","subject":"[v3s]change ld file, put memcpy and memset to 32k first","message":"[v3s]change ld file, put memcpy and memset to 32k first\n","repos":"xboot\/xboot,xboot\/xboot","old_file":"src\/arch\/arm32\/mach-licheepi\/xboot.ld","new_file":"src\/arch\/arm32\/mach-licheepi\/xboot.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(_start)\r\n\r\nSTACK_UND_SIZE = 0x40000;\r\nSTACK_ABT_SIZE = 0x40000;\r\nSTACK_IRQ_SIZE = 0x40000;\r\nSTACK_FIQ_SIZE = 0x40000;\r\nSTACK_SRV_SIZE = 0x100000;\r\n\r\nMEMORY\r\n{\r\n\tram  : org = 0x40000000, len = 16M\r\n\tdma  : org = 0x41000000, len = 16M\r\n\theap : org = 0x42000000, len = 32M\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tPROVIDE(__image_start = .);\r\n\t\tPROVIDE(__text_start = .);\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/start.o (.text)\r\n\t\t.obj\/arch\/arm32\/lib\/memcpy.o (.text)\r\n\t\t.obj\/arch\/arm32\/lib\/memset.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/sys-uart.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/sys-clock.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/sys-dram.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/sys-spi-flash.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/sys-copyself.o (.text)\r\n\t\t*(.text*)\r\n\t\t*(.init.text)\r\n\t\t*(.exit.text)\r\n\t\t*(.glue*)\r\n\t\t*(.note.gnu.build-id)\r\n\t\tPROVIDE(__text_end = .);\r\n\t} > ram\r\n\r\n\t.initcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE(__initcall_end = .);\r\n\t} > ram\r\n\r\n\t.exitcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE(__exitcall_end = .);\r\n\t} > ram\r\n\r\n\t.ksymtab ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE(__ksymtab_end = .);\r\n\t} > ram\r\n\r\n\t.romdisk ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE(__romdisk_end = .);\r\n\t} > ram\r\n\r\n\t.rodata ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__rodata_start = .);\r\n\t\t*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\r\n\t\tPROVIDE(__rodata_end = .);\r\n\t} > ram\r\n\r\n\t.data_shadow ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__data_shadow_start = .);\r\n\t\tPROVIDE(__data_shadow_end = (. + SIZEOF(.data)));\r\n\t\tPROVIDE(__image_end = __data_shadow_end);\r\n\t} > ram\r\n\r\n\t.data : AT(ADDR(.data_shadow))\r\n\t{\r\n\t\tPROVIDE(__data_start = .);\t\r\n\t\t*(.data*)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE(__data_end = .);\r\n\t} > ram\r\n\r\n\t.ARM.exidx ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__exidx_start = .);\r\n\t\t*(.ARM.exidx*)\r\n\t\tPROVIDE (__exidx_end = .);\r\n\t} > ram\r\n\r\n\t.ARM.extab ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__extab_start = .);\r\n\t\t*(.ARM.extab*)\r\n\t\tPROVIDE (__extab_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__bss_start = .);\r\n\t\t*(.bss*)\r\n\t\t*(.sbss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__bss_end = .);\r\n\t} > ram\r\n\r\n\t.stack ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__stack_start = .);\r\n\t\tPROVIDE(__stack_und_start = .);\r\n\t\t. += STACK_UND_SIZE;\r\n\t\tPROVIDE(__stack_und_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_abt_start = .);\r\n\t\t. += STACK_ABT_SIZE;\r\n\t\tPROVIDE(__stack_abt_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_irq_start = .);\r\n\t\t. += STACK_IRQ_SIZE;\r\n\t\tPROVIDE(__stack_irq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_fiq_start = .);\r\n\t\t. += STACK_FIQ_SIZE;\r\n\t\tPROVIDE(__stack_fiq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_srv_start = .);\r\n\t\t. += STACK_SRV_SIZE;\r\n\t\tPROVIDE(__stack_srv_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_end = .);\r\n\t} > ram\r\n\r\n\t.dma ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__dma_start = ORIGIN(dma));\r\n\t\tPROVIDE(__dma_end = ORIGIN(dma) + LENGTH(dma));\r\n\t} > dma\r\n\r\n\t.heap ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__heap_start = ORIGIN(heap));\r\n\t\tPROVIDE(__heap_end = ORIGIN(heap) + LENGTH(heap));\r\n\t} > heap\r\n\r\n\t.stab 0 : { *(.stab) }\r\n\t.stabstr 0 : { *(.stabstr) }\r\n\t.stab.excl 0 : { *(.stab.excl) }\r\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\r\n\t.stab.index 0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment 0 : { *(.comment) }\r\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\r\n\t.debug_info 0 : { *(.debug_info) }\r\n\t.debug_line 0 : { *(.debug_line) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t.debug_aranges 0 : { *(.debug_aranges) }\r\n}\r\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(_start)\r\n\r\nSTACK_UND_SIZE = 0x40000;\r\nSTACK_ABT_SIZE = 0x40000;\r\nSTACK_IRQ_SIZE = 0x40000;\r\nSTACK_FIQ_SIZE = 0x40000;\r\nSTACK_SRV_SIZE = 0x100000;\r\n\r\nMEMORY\r\n{\r\n\tram  : org = 0x40000000, len = 16M\r\n\tdma  : org = 0x41000000, len = 16M\r\n\theap : org = 0x42000000, len = 32M\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tPROVIDE(__image_start = .);\r\n\t\tPROVIDE(__text_start = .);\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/start.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/sys-uart.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/sys-clock.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/sys-dram.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/sys-spi-flash.o (.text)\r\n\t\t.obj\/arch\/arm32\/mach-licheepi\/sys-copyself.o (.text)\r\n\t\t*(.text*)\r\n\t\t*(.init.text)\r\n\t\t*(.exit.text)\r\n\t\t*(.glue*)\r\n\t\t*(.note.gnu.build-id)\r\n\t\tPROVIDE(__text_end = .);\r\n\t} > ram\r\n\r\n\t.initcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE(__initcall_end = .);\r\n\t} > ram\r\n\r\n\t.exitcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE(__exitcall_end = .);\r\n\t} > ram\r\n\r\n\t.ksymtab ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE(__ksymtab_end = .);\r\n\t} > ram\r\n\r\n\t.romdisk ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE(__romdisk_end = .);\r\n\t} > ram\r\n\r\n\t.rodata ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__rodata_start = .);\r\n\t\t*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\r\n\t\tPROVIDE(__rodata_end = .);\r\n\t} > ram\r\n\r\n\t.data_shadow ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__data_shadow_start = .);\r\n\t\tPROVIDE(__data_shadow_end = (. + SIZEOF(.data)));\r\n\t\tPROVIDE(__image_end = __data_shadow_end);\r\n\t} > ram\r\n\r\n\t.data : AT(ADDR(.data_shadow))\r\n\t{\r\n\t\tPROVIDE(__data_start = .);\t\r\n\t\t*(.data*)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE(__data_end = .);\r\n\t} > ram\r\n\r\n\t.ARM.exidx ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__exidx_start = .);\r\n\t\t*(.ARM.exidx*)\r\n\t\tPROVIDE (__exidx_end = .);\r\n\t} > ram\r\n\r\n\t.ARM.extab ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__extab_start = .);\r\n\t\t*(.ARM.extab*)\r\n\t\tPROVIDE (__extab_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__bss_start = .);\r\n\t\t*(.bss*)\r\n\t\t*(.sbss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__bss_end = .);\r\n\t} > ram\r\n\r\n\t.stack ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__stack_start = .);\r\n\t\tPROVIDE(__stack_und_start = .);\r\n\t\t. += STACK_UND_SIZE;\r\n\t\tPROVIDE(__stack_und_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_abt_start = .);\r\n\t\t. += STACK_ABT_SIZE;\r\n\t\tPROVIDE(__stack_abt_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_irq_start = .);\r\n\t\t. += STACK_IRQ_SIZE;\r\n\t\tPROVIDE(__stack_irq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_fiq_start = .);\r\n\t\t. += STACK_FIQ_SIZE;\r\n\t\tPROVIDE(__stack_fiq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_srv_start = .);\r\n\t\t. += STACK_SRV_SIZE;\r\n\t\tPROVIDE(__stack_srv_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__stack_end = .);\r\n\t} > ram\r\n\r\n\t.dma ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__dma_start = ORIGIN(dma));\r\n\t\tPROVIDE(__dma_end = ORIGIN(dma) + LENGTH(dma));\r\n\t} > dma\r\n\r\n\t.heap ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__heap_start = ORIGIN(heap));\r\n\t\tPROVIDE(__heap_end = ORIGIN(heap) + LENGTH(heap));\r\n\t} > heap\r\n\r\n\t.stab 0 : { *(.stab) }\r\n\t.stabstr 0 : { *(.stabstr) }\r\n\t.stab.excl 0 : { *(.stab.excl) }\r\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\r\n\t.stab.index 0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment 0 : { *(.comment) }\r\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\r\n\t.debug_info 0 : { *(.debug_info) }\r\n\t.debug_line 0 : { *(.debug_line) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t.debug_aranges 0 : { *(.debug_aranges) }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"aa5242aa4214b4bacb89ac9b161f4ba142dfcad1","subject":"RAM region shifted by 0xC0 for vectors","message":"RAM region shifted by 0xC0 for vectors\n","repos":"kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS","old_file":"TARGET_Freescale\/TARGET_KL25Z\/TOOLCHAIN_GCC_ARM\/MKL25Z4.ld","new_file":"TARGET_Freescale\/TARGET_KL25Z\/TOOLCHAIN_GCC_ARM\/MKL25Z4.ld","new_contents":"\/*\n * KL25Z ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH_PROTECTION\t(rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410\n  RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 16K - 0xC0\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        *(.text.Reset_Handler)\n        *(.text.System_Init)\n         . = ALIGN(4);\n    } > VECTORS\n\n    .flash_protect :\n    {\n        KEEP(*(.kinetis_flash_config_field))\n         . = ALIGN(4);\n    } > FLASH_PROTECTION\n\n    .text :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/*\n * KL25Z ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS\t(rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH_PROTECTION\t(rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410\n  RAM (rwx) : ORIGIN = 0x1FFFF000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        *(.text.Reset_Handler)\n        *(.text.System_Init)\n         . = ALIGN(4);\n    } > VECTORS\n\n    .flash_protect :\n    {\n        KEEP(*(.kinetis_flash_config_field))\n         . = ALIGN(4);\n    } > FLASH_PROTECTION\n\n    .text :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        \/* vectors come here, shift 0xc0 *\/\n        . = . + 0xC0;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"de8ae5d9b59dbb57eb54463d481abf068641e34c","subject":"cleaned up formatting of necco's cleese.ld","message":"cleaned up formatting of necco's cleese.ld\n","repos":"jtauber\/cleese,jtauber\/cleese,jtauber\/cleese","old_file":"necco\/lib\/bochs\/cleese.ld","new_file":"necco\/lib\/bochs\/cleese.ld","new_contents":"\nENTRY(entry)\n\nLS_Phys = 0x100000; \/* 1 meg = load (physical) address *\/\nLS_Virt = 0x100000; \/* 1 meg = virtual address *\/\n\nSECTIONS\n{\n    .text LS_Virt : AT(LS_Phys)\n    {\n        LS_Code = .;\n        \n        \/* symbols to mark start of code segment *\/\n        code = .;\n        \n        \/* kernel code *\/\n        *(.text)\n        \n        \/* .rodata is the ELF constant data section *\/\n        *(.rodata*)\n        \n        . = ALIGN(4096);\n    }\n    \n    .data : AT(LS_Phys + (LS_Data - LS_Code))\n    {\n        LS_Data = .;\n        \n        \/* symbols to mark start of data segment *\/\n        data = .;\n        \n        \/* kernel data *\/\n        *(.data)\n        \n        . = ALIGN(4096);\n    }\n    \n    .bss : AT(LS_Phys + (LS_Bss - LS_Code))\n    {\n        LS_Bss = .;\n        \n        \/* symbols to mark start of BSS segment *\/\n        bss = .;\n        \n        \/* kernel BSS *\/\n        *(.bss)\n        \n        \/* \"common\" variables *\/\n        *(COMMON)\n        \n        . = ALIGN(4096);\n    }\n    \n    \/* symbols to mark end of kernel *\/\n    end = .;\n    _end = .;\n}\n","old_contents":"\nENTRY(entry)\n\nLS_Phys = 0x100000; \/* 1 meg = load (physical) address *\/\nLS_Virt = 0x100000; \/* 1 meg = virtual address *\/\n\nSECTIONS\n{\n\t.text LS_Virt : AT(LS_Phys)\n\t{\n\t\tLS_Code = .;\n\n\t\t\/* symbols to mark start of code segment *\/\n\t\tcode = .;\n\t\t_code = .;\n\n\t\t\/* kernel code *\/\n\t\t*(.text)\n\n\t\t\/* .rodata is the ELF constant data section *\/\n\t\t*(.rodata*)\n\n\t\t. = ALIGN(4096);\n\t}\n\n\t.data : AT(LS_Phys + (LS_Data - LS_Code))\n\t{\n\t\tLS_Data = .;\n\n\t\t\/* symbols to mark start of data segment *\/\n\t\tdata = .;\n\t\t_data = .;\n\n\t\t\/* kernel data *\/\n\t\t*(.data)\n\n\t\t. = ALIGN(4096);\n\t}\n\n\t.bss : AT(LS_Phys + (LS_Bss - LS_Code))\n\t{\n\t\tLS_Bss = .;\n\n\t\t\/* symbols to mark start of BSS segment *\/\n\t\tbss = .;\n\t\t_bss = .;\n\n\t\t\/* kernel BSS *\/\n\t\t*(.bss)\n\n\t\t\/* \"common\" variables *\/\n\t\t*(COMMON)\n\n\t\t. = ALIGN(4096);\n\t}\n\n\t\/* symbols to mark end of kernel *\/\n\tend = .; _end = .;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"66cba66b52705934b277c680888fec26cbd6beb0","subject":"Added end symbol.","message":"Added end symbol.\n","repos":"duckinator\/dux,duckinator\/dux,duckinator\/dux","old_file":"src\/kernel\/link.ld","new_file":"src\/kernel\/link.ld","new_contents":"ENTRY(_start)\n\nSECTIONS {\n\t. = 0x100000;\n\n\t.text : ALIGN (0x1000) {\n\t\t*(.mboot)\n\t\t*(.text)\n\t}\n\n\t.rodata ALIGN (0x1000) : {\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN (0x1000) : {\n\t\t*(.data)\n\t}\n\n\t.bss ALIGN (0x1000) : {\n\t\tsbss = .;\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\tebss = .;\n\t}\n\n\tend = .;\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS {\n\t. = 0x100000;\n\n\t.text : ALIGN (0x1000) {\n\t\t*(.mboot)\n\t\t*(.text)\n\t}\n\n\t.rodata ALIGN (0x1000) : {\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN (0x1000) : {\n\t\t*(.data)\n\t}\n\n\t.bss ALIGN (0x1000) : {\n\t\tsbss = .;\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\tebss = .;\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"314aa755ed3af01dc42d77587752a32a883972ed","subject":"Remove vkGetInstanceProcAddr from exported symbols on Android","message":"Remove vkGetInstanceProcAddr from exported symbols on Android\n\nAndroid only allows access to the ICD's functions, through the Vulkan\nLoader interface functions.\n\nThis was causing direct access to vkGetPhysicalDeviceSurfaceFormatsKHR,\nwhile Android's libvulkan must override it to provide an implementation\nbased on AHardwareBuffer, which affects things like wide-gamut support.\n\nBug: b\/182576189\nBug: b\/148822450\nChange-Id: I64fd5a601f92beca186696d2cd09eee1a09b8ce9\nReviewed-on: https:\/\/swiftshader-review.googlesource.com\/c\/SwiftShader\/+\/53608\nReviewed-by: Jason Macnak <76caa58940b8c6785e996f522e85b625ac7c7baa@google.com>\nReviewed-by: Chris Forbes <c3279c50043e18e9442c1ae071cafa0e7a4ca967@google.com>\nTested-by: Nicolas Capens <51edc787c30f24c4904e8ffbb5523c3a9f7a451d@google.com>\n","repos":"bkaradzic\/SwiftShader,google\/swiftshader,bkaradzic\/SwiftShader,google\/swiftshader,google\/swiftshader,bkaradzic\/SwiftShader,bkaradzic\/SwiftShader,bkaradzic\/SwiftShader","old_file":"src\/Vulkan\/android_vk_swiftshader.lds","new_file":"src\/Vulkan\/android_vk_swiftshader.lds","new_contents":"# For Android, we must not export anything other than loader-related API\n{\nglobal:\n\t# Loader-ICD interface functions\n\tvk_icdGetInstanceProcAddr;\n\tvk_icdNegotiateLoaderICDInterfaceVersion;\n\n\t# Android HAL module info object\n\tHMI;\n\nlocal:\n\t*;\n};\n\n","old_contents":"# For Android, we must not export anything other than loader-related API\n{\nglobal:\n\tvkGetInstanceProcAddr;\n\n\t# Loader-ICD interface functions\n\tvk_icdGetInstanceProcAddr;\n\tvk_icdNegotiateLoaderICDInterfaceVersion;\n\n\t# Android HAL module info object\n\tHMI;\n\nlocal:\n\t*;\n};\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"99eb25d0df8a83bfc1a58cbf63479815f68e437f","subject":"Updated copyright notice in linker script.","message":"Updated copyright notice in linker script.\n","repos":"grahamedgecombe\/arc,grahamedgecombe\/arc,grahamedgecombe\/arc","old_file":"arc.lds","new_file":"arc.lds","new_contents":"\/*\n * Copyright (c) 2011-2012 Graham Edgecombe <graham@grahamedgecombe.com>\n *\n * Permission to use, copy, modify, and\/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\/\n\nOUTPUT_FORMAT(elf64-x86-64)\nENTRY(start)\n\nPAGE_SIZE  = 0x1000;\nKERNEL_VMA = 0xFFFF800000000000;\nUPPER_MEM  = 0x100000;\n\nSECTIONS\n{\n  . = UPPER_MEM;\n  _start = . + KERNEL_VMA;\n\n  .init :\n  {\n    *(.init.lower)\n  }\n\n  . += KERNEL_VMA;\n\n  .text ALIGN(PAGE_SIZE) : AT(ADDR(.text) - KERNEL_VMA)\n  {\n    *(.init.higher)\n    *(.text)\n  }\n\n  .data ALIGN(PAGE_SIZE) : AT(ADDR(.data) - KERNEL_VMA)\n  {\n    *(.data)\n  }\n\n  .rodata ALIGN(PAGE_SIZE) : AT(ADDR(.rodata) - KERNEL_VMA)\n  {\n    *(.rodata)\n  }\n\n  .bss ALIGN(PAGE_SIZE) : AT(ADDR(.bss) - KERNEL_VMA)\n  {\n    *(.bss)\n  }\n\n  _end = .;\n\n  \/DISCARD\/ :\n  {\n    *(.comment)\n  }\n}\n\n","old_contents":"\/*\n * Copyright (c) 2011 Graham Edgecombe <graham@grahamedgecombe.com>\n *\n * Permission to use, copy, modify, and\/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\/\n\nOUTPUT_FORMAT(elf64-x86-64)\nENTRY(start)\n\nPAGE_SIZE  = 0x1000;\nKERNEL_VMA = 0xFFFF800000000000;\nUPPER_MEM  = 0x100000;\n\nSECTIONS\n{\n  . = UPPER_MEM;\n  _start = . + KERNEL_VMA;\n\n  .init :\n  {\n    *(.init.lower)\n  }\n\n  . += KERNEL_VMA;\n\n  .text ALIGN(PAGE_SIZE) : AT(ADDR(.text) - KERNEL_VMA)\n  {\n    *(.init.higher)\n    *(.text)\n  }\n\n  .data ALIGN(PAGE_SIZE) : AT(ADDR(.data) - KERNEL_VMA)\n  {\n    *(.data)\n  }\n\n  .rodata ALIGN(PAGE_SIZE) : AT(ADDR(.rodata) - KERNEL_VMA)\n  {\n    *(.rodata)\n  }\n\n  .bss ALIGN(PAGE_SIZE) : AT(ADDR(.bss) - KERNEL_VMA)\n  {\n    *(.bss)\n  }\n\n  _end = .;\n\n  \/DISCARD\/ :\n  {\n    *(.comment)\n  }\n}\n\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"4906f185c7e353cbbecaaa822ca4e41db50ab220","subject":"linker: move .tbss \/ .tdata down to .bss to avoid gaps","message":"linker: move .tbss \/ .tdata down to .bss to avoid gaps\n","repos":"AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,ingve\/IncludeOS,alfred-bratterud\/IncludeOS,hioa-cs\/IncludeOS,ingve\/IncludeOS,alfred-bratterud\/IncludeOS,mnordsletten\/IncludeOS,ingve\/IncludeOS,AndreasAakesson\/IncludeOS,alfred-bratterud\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,ingve\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,ingve\/IncludeOS,alfred-bratterud\/IncludeOS,AnnikaH\/IncludeOS,hioa-cs\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0x200000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  . = _ELF_START_;\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n\n  .text ALIGN(0x1000):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x1000) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  _EXEC_END_ = .;\n  _READONLY_START_ = .;\n  .config ALIGN(0x1000) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n  _READONLY_END_ = .;\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .tdata :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.* .gnu.linkonce.td.*)\n    _TDATA_END_ = .;\n  }\n\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)\n    _TBSS_END_ = .;\n  }\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","old_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0x200000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  . = _ELF_START_;\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n\n  .text ALIGN(0x1000):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x1000) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  _EXEC_END_ = .;\n  _READONLY_START_ = .;\n  .config ALIGN(0x1000) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n  _READONLY_END_ = .;\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7de1dcbe09f9591705028709dc25bd955881f038","subject":"[kernel] fix unresolved merge conflict in linker script","message":"[kernel] fix unresolved merge conflict in linker script\n","repos":"rachlmac\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel,hawkw\/sos-kernel","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .rodata :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n        *(.rodata .rodata.*)\n        . = ALIGN(4K);\n    }\n\n    .text :\n     {\n       *(.text .text.*)\n       . = ALIGN(4K);\n     }\n\n     .data :\n     {\n       *(.data .data.*)\n       . = ALIGN(4K);\n     }\n\n     .bss :\n     {\n       *(.bss .bss.*)\n       . = ALIGN(4K);\n     }\n\n    .data.rel.ro : ALIGN(4K) {\n       *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n        . = ALIGN(4K);\n    }\n\n    .gcc_except_table : ALIGN(4K) {\n      *(.gcc_except_table)\n      . = ALIGN(4K);\n    }\n}\n","old_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .rodata :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n        *(.rodata .rodata.*)\n        . = ALIGN(4K);\n    }\n\n    .text :\n<<<<<<< HEAD\n    {\n        *(.text .text.*)\n        . = ALIGN(4K);\n    }\n=======\n     {\n       *(.text .text.*)\n       . = ALIGN(4K);\n     }\n>>>>>>> origin\/master\n\n     .data :\n     {\n       *(.data .data.*)\n       . = ALIGN(4K);\n     }\n\n     .bss :\n     {\n       *(.bss .bss.*)\n       . = ALIGN(4K);\n     }\n\n    .data.rel.ro : ALIGN(4K) {\n       *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n        . = ALIGN(4K);\n    }\n\n    .gcc_except_table : ALIGN(4K) {\n      *(.gcc_except_table)\n      . = ALIGN(4K);\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8484467fdd33b317669565966577236f9f438676","subject":"GCC Bootloader support","message":"GCC Bootloader support\n","repos":"infinnovation\/mbed-os,c1728p9\/mbed-os,bcostm\/mbed-os,YarivCol\/mbed-os,c1728p9\/mbed-os,kjbracey-arm\/mbed,Archcady\/mbed-os,ryankurte\/mbed-os,YarivCol\/mbed-os,pradeep-gr\/mbed-os5-onsemi,svogl\/mbed-os,betzw\/mbed-os,NXPmicro\/mbed,CalSol\/mbed,CalSol\/mbed,monkiineko\/mbed-os,andcor02\/mbed-os,Archcady\/mbed-os,bcostm\/mbed-os,NXPmicro\/mbed,bcostm\/mbed-os,monkiineko\/mbed-os,mbedmicro\/mbed,nRFMesh\/mbed-os,mbedmicro\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,karsev\/mbed-os,ryankurte\/mbed-os,Archcady\/mbed-os,andcor02\/mbed-os,fahhem\/mbed-os,fahhem\/mbed-os,pradeep-gr\/mbed-os5-onsemi,HeadsUpDisplayInc\/mbed,ryankurte\/mbed-os,betzw\/mbed-os,CalSol\/mbed,CalSol\/mbed,fahhem\/mbed-os,infinnovation\/mbed-os,svogl\/mbed-os,mazimkhan\/mbed-os,bcostm\/mbed-os,nRFMesh\/mbed-os,ryankurte\/mbed-os,infinnovation\/mbed-os,monkiineko\/mbed-os,monkiineko\/mbed-os,kjbracey-arm\/mbed,infinnovation\/mbed-os,NXPmicro\/mbed,mazimkhan\/mbed-os,catiedev\/mbed-os,mbedmicro\/mbed,Archcady\/mbed-os,HeadsUpDisplayInc\/mbed,mazimkhan\/mbed-os,andcor02\/mbed-os,pradeep-gr\/mbed-os5-onsemi,betzw\/mbed-os,c1728p9\/mbed-os,mazimkhan\/mbed-os,andcor02\/mbed-os,HeadsUpDisplayInc\/mbed,andcor02\/mbed-os,monkiineko\/mbed-os,nRFMesh\/mbed-os,CalSol\/mbed,svogl\/mbed-os,NXPmicro\/mbed,betzw\/mbed-os,HeadsUpDisplayInc\/mbed,fahhem\/mbed-os,pradeep-gr\/mbed-os5-onsemi,YarivCol\/mbed-os,c1728p9\/mbed-os,bcostm\/mbed-os,infinnovation\/mbed-os,nRFMesh\/mbed-os,mazimkhan\/mbed-os,catiedev\/mbed-os,CalSol\/mbed,pradeep-gr\/mbed-os5-onsemi,Archcady\/mbed-os,mbedmicro\/mbed,catiedev\/mbed-os,YarivCol\/mbed-os,infinnovation\/mbed-os,catiedev\/mbed-os,monkiineko\/mbed-os,YarivCol\/mbed-os,ryankurte\/mbed-os,mbedmicro\/mbed,fahhem\/mbed-os,karsev\/mbed-os,karsev\/mbed-os,kjbracey-arm\/mbed,karsev\/mbed-os,svogl\/mbed-os,kjbracey-arm\/mbed,svogl\/mbed-os,fahhem\/mbed-os,karsev\/mbed-os,andcor02\/mbed-os,betzw\/mbed-os,catiedev\/mbed-os,NXPmicro\/mbed,ryankurte\/mbed-os,svogl\/mbed-os,bcostm\/mbed-os,nRFMesh\/mbed-os,karsev\/mbed-os,catiedev\/mbed-os,nRFMesh\/mbed-os,YarivCol\/mbed-os,NXPmicro\/mbed,HeadsUpDisplayInc\/mbed,mazimkhan\/mbed-os,Archcady\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed","old_file":"targets\/TARGET_STM\/TARGET_STM32L1\/TARGET_XDOT_L151CC\/device\/TOOLCHAIN_GCC_ARM\/STM32L151XC.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32L1\/TARGET_XDOT_L151CC\/device\/TOOLCHAIN_GCC_ARM\/STM32L151XC.ld","new_contents":"\/* Linker script to configure memory regions. *\/\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 256k\n#endif\nMEMORY\n{\n  \/* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292\n   * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138\n   *\/\n  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\nMEMORY\n{\n  \/* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292\n   * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138\n   *\/\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k\n  RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"16d2db9ca7ea8a49c5cb7ba346200872b071f4e6","subject":"\tCorrected peripheral memory size.","message":"\tCorrected peripheral memory size.\n","repos":"masilvabustos\/CabbageOS,masilvabustos\/CabbageOS","old_file":"lib\/ldscripts\/stm32f100xb.ld","new_file":"lib\/ldscripts\/stm32f100xb.ld","new_contents":"\nMEMORY {\n\tFLASH : \tORIGIN = 0x08000000, LENGTH = 128K\n\tSRAM : \t\tORIGIN = 0x20000000, LENGTH = 8K\n\tPERIPH : \tORIGIN = 0x40000000, LENGTH = 512M\n}\n\nINCLUDE stm32f100xx.ld\n\n","old_contents":"\nMEMORY {\n\tFLASH : \tORIGIN = 0x08000000, LENGTH = 128K\n\tSRAM : \t\tORIGIN = 0x20000000, LENGTH = 8K\n\tPERIPH : \tORIGIN = 0x40000000, LENGTH = 0x24300\n}\n\nINCLUDE stm32f100xx.ld\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"0e4d4fa67f3436bc5ebe6e1d4325e668cd8b3fc1","subject":"include\/linker: .object_access.* should be in ROM","message":"include\/linker: .object_access.* should be in ROM\n\n.object_access.* sections should be with\n\nGROUP_LINK_IN(ROMABLE_REGION) as other sections in\ncommon-rom.ld\n\nFixes #15481\n\nSigned-off-by: Wayne Ren <d5c6d7c4aa45e53f819f17870783d153a32ba7d0@synopsys.com>\nSigned-off-by: Anas Nashif <0d9952ec84ac43c159f6b7e7ed99a9080c00dd6e@intel.com>\n","repos":"finikorg\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/linker\/common-rom.ld","new_file":"include\/linker\/common-rom.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#if defined(CONFIG_GEN_ISR_TABLES) && !defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t*(SW_ISR_TABLE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on 4 byte\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array,,)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n#ifdef CONFIG_USERSPACE\n\t\/* Build-time assignment of permissions to kernel objects to\n\t * threads declared with K_THREAD_DEFINE()\n\t *\/\n\tSECTION_PROLOGUE(object_access,,)\n\t{\n\t\t__object_access_start = .;\n\t\tKEEP(*(\".object_access.*\"))\n\t\t__object_access_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(app_shmem_regions,,)\n\t{\n\t\t__app_shmem_regions_start = .;\n\t\tKEEP(*(SORT(\".app_regions.*\")));\n\t\t__app_shmem_regions_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE (devconfig,,)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(net_l2,,)\n\t{\n\t\t__net_l2_start = .;\n\t\t*(\".net_l2.init\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.init*\")))\n\t\t__net_l2_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_BT_SETTINGS)\n\tSECTION_DATA_PROLOGUE(_bt_settings_area,,SUBALIGN(4))\n\t{\n\t\t_bt_settings_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._bt_settings.static.*\")))\n\t\t_bt_settings_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__log_const_start = .;\n\t\tKEEP(*(SORT(.log_const_*)));\n\t\t__log_const_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_backends_sections,,)\n\t{\n\t\t__log_backends_start = .;\n\t\tKEEP(*(\".log_backends\"));\n\t\t__log_backends_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(shell_root_cmds_sections,,)\n\t{\n\t\t__shell_root_cmds_start = .;\n\t\tKEEP(*(SORT(.shell_root_cmd_*)));\n\t\t__shell_root_cmds_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(font_entry_sections,,)\n\t{\n\t\t__font_entry_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".font_entry.*\")))\n\t\t__font_entry_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_COVERAGE_GCOV\n\t\/* Section needed by gcov when coverage is turned on.*\/\n\tSECTION_PROLOGUE (gcov,,)\n\t{\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array*))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif  \/* CONFIG_COVERAGE_GCOV *\/\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#if defined(CONFIG_GEN_ISR_TABLES) && !defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t*(SW_ISR_TABLE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on 4 byte\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array,,)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n#ifdef CONFIG_USERSPACE\n\t\/* Build-time assignment of permissions to kernel objects to\n\t * threads declared with K_THREAD_DEFINE()\n\t *\/\n\tSECTION_PROLOGUE(object_access,,)\n\t{\n\t\t__object_access_start = .;\n\t\tKEEP(*(\".object_access.*\"))\n\t\t__object_access_end = .;\n\t}\n#endif\n\n\tSECTION_PROLOGUE(app_shmem_regions,,)\n\t{\n\t\t__app_shmem_regions_start = .;\n\t\tKEEP(*(SORT(\".app_regions.*\")));\n\t\t__app_shmem_regions_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE (devconfig,,)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(net_l2,,)\n\t{\n\t\t__net_l2_start = .;\n\t\t*(\".net_l2.init\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.init*\")))\n\t\t__net_l2_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_BT_SETTINGS)\n\tSECTION_DATA_PROLOGUE(_bt_settings_area,,SUBALIGN(4))\n\t{\n\t\t_bt_settings_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._bt_settings.static.*\")))\n\t\t_bt_settings_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__log_const_start = .;\n\t\tKEEP(*(SORT(.log_const_*)));\n\t\t__log_const_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_backends_sections,,)\n\t{\n\t\t__log_backends_start = .;\n\t\tKEEP(*(\".log_backends\"));\n\t\t__log_backends_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(shell_root_cmds_sections,,)\n\t{\n\t\t__shell_root_cmds_start = .;\n\t\tKEEP(*(SORT(.shell_root_cmd_*)));\n\t\t__shell_root_cmds_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(font_entry_sections,,)\n\t{\n\t\t__font_entry_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".font_entry.*\")))\n\t\t__font_entry_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_COVERAGE_GCOV\n\t\/* Section needed by gcov when coverage is turned on.*\/\n\tSECTION_PROLOGUE (gcov,,)\n\t{\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array*))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif  \/* CONFIG_COVERAGE_GCOV *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2d95fcb9cf3329ca6b62a22da1468d385cc54547","subject":"Onsemi: Fix alignment of execute region to 8-byte boundary","message":"Onsemi: Fix alignment of execute region to 8-byte boundary\n\n--legacyalign, --no_legacyalign are deprecated from ARMC6 compiler, in order to\nremove deprecated flags all linker files (GCC and IAR as well to have uniformity)\nshould strictly align to 8-byte boundary\n","repos":"mbedmicro\/mbed,c1728p9\/mbed-os,c1728p9\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,c1728p9\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os,kjbracey-arm\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed","old_file":"targets\/TARGET_ONSEMI\/TARGET_NCS36510\/device\/TOOLCHAIN_GCC_ARM\/NCS36510.ld","new_file":"targets\/TARGET_ONSEMI\/TARGET_NCS36510\/device\/TOOLCHAIN_GCC_ARM\/NCS36510.ld","new_contents":"\/*\n * NCS36510 ARM GCC linker script file\n *\/\n\nMEMORY {\n    FIB (rx)              : ORIGIN = 0x00002000, LENGTH = 0x00000800\n    TRIM (rx)             : ORIGIN = 0x00002800, LENGTH = 0x00000800\n    VECTORS (rx)          : ORIGIN = 0x00003000, LENGTH = 0x00000090\n    FLASH (rx)            : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90\n    RAM (rwx)             : ORIGIN = 0x3FFF4090, LENGTH = 48K - 0x90 \/* 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 *\/\n}\n\n    \/* Linker script to place sections and symbol values. Should be used together\n     * with other linker script that defines memory regions FLASH and RAM.\n     * It references following symbols, which must be defined in code:\n     * _reset_init : Entry of reset handler\n     *\n     * It defines following symbols, which code can use without definition:\n     * __exidx_start\n     * __exidx_end\n     * __etext\n     * __data_start__\n     * __preinit_array_start\n     * __preinit_array_end\n     * __init_array_start\n     * __init_array_end\n     * __fini_array_start\n     * __fini_array_end\n     * __data_end__\n     * __bss_start__\n     * __bss_end__\n     * __end__\n     * end\n     * __HeapLimit\n     * __StackLimit\n     * __StackTop\n     * __stack\n     *\/\n    ENTRY(Reset_Handler)\n\n    SECTIONS {\n    .fib :\n    {\n        KEEP(*(.fib))\n    } > FIB\n\n    .trim :\n    {\n        KEEP(*(.trim))\n    } > TRIM\n\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        . = ALIGN(8);\n    } > VECTORS\n\n\n.text :\n    {\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n.ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n.ARM.exidx :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > FLASH\n\n.data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM AT>FLASH\n\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += 0x800;\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += 0x800 - (. - __StackLimit);\n    } > RAM\n\n    \/* Set stack top to end of RAM *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack);\n    PROVIDE(__stack = __StackTop);\n\n}\n","old_contents":"\/*\n * NCS36510 ARM GCC linker script file\n *\/\n\nMEMORY {\n    FIB (rx)              : ORIGIN = 0x00002000, LENGTH = 0x00000800\n    TRIM (rx)             : ORIGIN = 0x00002800, LENGTH = 0x00000800\n    VECTORS (rx)          : ORIGIN = 0x00003000, LENGTH = 0x00000090\n    FLASH (rx)            : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90\n    RAM (rwx)             : ORIGIN = 0x3FFF4090, LENGTH = 48K - 0x90 \/* 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 *\/\n}\n\n    \/* Linker script to place sections and symbol values. Should be used together\n     * with other linker script that defines memory regions FLASH and RAM.\n     * It references following symbols, which must be defined in code:\n     * _reset_init : Entry of reset handler\n     *\n     * It defines following symbols, which code can use without definition:\n     * __exidx_start\n     * __exidx_end\n     * __etext\n     * __data_start__\n     * __preinit_array_start\n     * __preinit_array_end\n     * __init_array_start\n     * __init_array_end\n     * __fini_array_start\n     * __fini_array_end\n     * __data_end__\n     * __bss_start__\n     * __bss_end__\n     * __end__\n     * end\n     * __HeapLimit\n     * __StackLimit\n     * __StackTop\n     * __stack\n     *\/\n    ENTRY(Reset_Handler)\n\n    SECTIONS {\n    .fib :\n    {\n        KEEP(*(.fib))\n    } > FIB\n\n    .trim :\n    {\n        KEEP(*(.trim))\n    } > TRIM\n\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        . = ALIGN(4);\n    } > VECTORS\n\n\n.text :\n    {\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n.ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n.ARM.exidx :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > FLASH\n\n.data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM AT>FLASH\n\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n\n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += 0x800;\n        __HeapLimit = .;\n    } > RAM\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += 0x800 - (. - __StackLimit);\n    } > RAM\n\n    \/* Set stack top to end of RAM *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack);\n    PROVIDE(__stack = __StackTop);\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cd92af1cab47ea34f52f5c3c005e8389ace7b374","subject":"linker: kobject-text.ld: avoid backwards location counter","message":"linker: kobject-text.ld: avoid backwards location counter\n\nwhen kobject text area is greater than CONFIG_KOBJECT_TEXT_AREA,\nthere will be location counter backwards, change it to assert to\nprompt configuring CONFIG_KOBJECT_TEXT_AREA larger.\n\nFixes: #16307.\n\nSigned-off-by: Wentong Wu <a92ffab6ab5ff780cf36418e13a69a97399df0f5@intel.com>\n","repos":"Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr","old_file":"include\/linker\/kobject-text.ld","new_file":"include\/linker\/kobject-text.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#ifdef CONFIG_USERSPACE\n\t\/* We need to reserve room for the gperf generated hash functions.\n\t * Fortunately, unlike the data tables, the size of the code is\n\t * reasonably predictable.\n\t *\n\t * The linker will error out complaining that the location pointer\n\t * is moving backwards if the reserved room isn't large enough.\n\t *\/\n\t_kobject_text_area_start = .;\n\t*(\".kobject_data.text*\")\n\t_kobject_text_area_end = .;\n\t_kobject_text_area_used = _kobject_text_area_end - _kobject_text_area_start;\n#ifndef LINKER_PASS2\n#ifdef CONFIG_DYNAMIC_OBJECTS\n\tPROVIDE(z_object_gperf_find = .);\n\tPROVIDE(z_object_gperf_wordlist_foreach = .);\n#else\n\tPROVIDE(z_object_find = .);\n\tPROVIDE(z_object_wordlist_foreach = .);\n#endif\n#endif\n\n\t\/* In a valid build the MAX function will always evaluate to the\n\tsecond argument below, but to give the user a good error message\n\twhen the area overflows we need to temporarily corrupt the\n\tlocation counter, and then detect the overflow with an assertion\n\tlater on. *\/\n\n\t. = MAX(., _kobject_text_area_start + CONFIG_KOBJECT_TEXT_AREA);\n\n\tASSERT(\n\t\tCONFIG_KOBJECT_TEXT_AREA >= _kobject_text_area_used,\n\"The configuration system has incorrectly set\n'CONFIG_KOBJECT_TEXT_AREA' to\nCONFIG_KOBJECT_TEXT_AREA, which is not big enough. You must\nthrough Kconfig either disable 'CONFIG_USERSPACE', or set\n'CONFIG_KOBJECT_TEXT_AREA' to a value larger than\nCONFIG_KOBJECT_TEXT_AREA.\"\n\t\t);\n#endif \/* CONFIG_USERSPACE *\/\n\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#ifdef CONFIG_USERSPACE\n\t\/* We need to reserve room for the gperf generated hash functions.\n\t * Fortunately, unlike the data tables, the size of the code is\n\t * reasonably predictable.\n\t *\n\t * The linker will error out complaining that the location pointer\n\t * is moving backwards if the reserved room isn't large enough.\n\t *\/\n\t_kobject_text_area_start = .;\n\t*(\".kobject_data.text*\")\n\t_kobject_text_area_end = .;\n#ifndef LINKER_PASS2\n#ifdef CONFIG_DYNAMIC_OBJECTS\n\tPROVIDE(z_object_gperf_find = .);\n\tPROVIDE(z_object_gperf_wordlist_foreach = .);\n#else\n\tPROVIDE(z_object_find = .);\n\tPROVIDE(z_object_wordlist_foreach = .);\n#endif\n#endif\n\t. += CONFIG_KOBJECT_TEXT_AREA - (_kobject_text_area_end - _kobject_text_area_start);\n#endif \/* CONFIG_USERSPACE *\/\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"37388bb965e0cbdefc1bf864497fa9c7543501ed","subject":"Delete linker_flash.ld","message":"Delete linker_flash.ld","repos":"jsyk\/PIP-Watch,jsyk\/PIP-Watch,jsyk\/PIP-Watch","old_file":"epd_driver_basic_stm32f101_sw\/prj\/linker_flash.ld","new_file":"epd_driver_basic_stm32f101_sw\/prj\/linker_flash.ld","new_contents":"","old_contents":"MEMORY\r\n{\r\n    RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 10K\r\n    FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K\r\n}\r\n\r\nSECTIONS\r\n{\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        KEEP(*(.interrupt_vector))\r\n        *(.text)\r\n        *(.text*)\r\n        *(.rodata)\r\n        *(.rodata*)\r\n        . = ALIGN(4);\r\n    } > FLASH\r\n\r\n    _data_flash = .;\r\n\r\n    .data : AT ( _data_flash )\r\n    {\r\n        . = ALIGN(4);\r\n        _data_begin = .;\r\n        *(.data)\r\n        *(.data*)\r\n        . = ALIGN(4);\r\n        _data_end = .;\r\n    } > RAM\r\n\r\n    .bss :\r\n    {\r\n        _bss_begin = .;\r\n        __bss_start__ = _bss_begin;\r\n        *(.bss)\r\n        *(.bss*)\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _bss_end = .;\r\n        __bss_end__ = _bss_end;\r\n    } > RAM\r\n\r\n    _stack_size = 1024;\r\n    _stack_end = ORIGIN(RAM)+LENGTH(RAM);\r\n    _stack_begin = _stack_end - _stack_size;\r\n    . = _stack_begin;\r\n    ._stack :\r\n    {\r\n        . = . + _stack_size;\r\n    } > RAM\r\n\r\n}\r\n\r\nENTRY(handler_reset);\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"83c04fa31dc2f0946ec68f4e8fdee21ae6c2b6bb","subject":"fix(esp8266): Fix and clean up link file","message":"fix(esp8266): Fix and clean up link file\n","repos":"espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK","old_file":"components\/esp8266\/ld\/esp8266.common.ld","new_file":"components\/esp8266\/ld\/esp8266.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\n#include \"sdkconfig.h\"\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  \/* RTC memory holds user's data\/rodata *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data .rtc.data.*)\n    *(.rtc.rodata .rtc.rodata.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    LONG(_text_start)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.iram1 .iram1.*)\n    *libspi_flash.a:spi_flash_raw.o(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n#ifdef CONFIG_LWIP_GLOBAL_DATA_LINK_IRAM\n    *liblwip.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_TCPIP_ADAPTER_GLOBAL_DATA_LINK_IRAM\n    *libtcpip_adapter.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_ESP8266_CORE_GLOBAL_DATA_LINK_IRAM\n    *libcore.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_FREERTOS_GLOBAL_DATA_LINK_IRAM\n    *libfreertos.a:tasks.o(.bss .data .bss.* .data.* COMMON)\n    *libfreertos.a:timers.o(.bss .data .bss.* .data.* COMMON)\n    *libfreertos.a:freertos_hooks.o(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_LINK_ETS_PRINTF_TO_IRAM\n    *libesp8266.a:ets_printf.o(.literal .text .literal.* .text.* .rodata.* .rodata)\n#endif\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data .data.*)\n    *(.dram0 .dram0.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2 .sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *libpp.a:(.rodata.* .rodata)\n    *liblog.a:(.rodata.* .rodata)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss .sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2 .sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.user.data .user.data.*)\n    *(.rodata.* .rodata .irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n    *(.rodata2.* .rodata2 .literal2.* .literal2 .text2.* .text2)\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n}\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\n#include \"sdkconfig.h\"\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  \/* RTC memory holds user's data\/rodata *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    LONG(_text_start)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.iram1 .iram1.*)\n    *libspi_flash.a:spi_flash_raw.o(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n#ifdef CONFIG_LWIP_GLOBAL_DATA_LINK_IRAM\n    *liblwip.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_TCPIP_ADAPTER_GLOBAL_DATA_LINK_IRAM\n    *libtcpip_adapter.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_ESP8266_CORE_GLOBAL_DATA_LINK_IRAM\n    *libcore.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_FREERTOS_GLOBAL_DATA_LINK_IRAM\n    *libfreertos.a:tasks.o(.bss .data .bss.* .data.* COMMON)\n    *libfreertos.a:timers.o(.bss .data .bss.* .data.* COMMON)\n    *libfreertos.a:freertos_hooks.o(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_LINK_ETS_PRINTF_TO_IRAM\n    *libesp8266.a:ets_printf.o(.literal .text .literal.* .text.* .rodata.* .rodata)\n#endif\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.dram0. .dram0.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *libpp.a:(.rodata.* .rodata)\n    *liblog.a:(.rodata.* .rodata)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.user.data)\n    *(.rodata.* .rodata .irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n    *(.rodata2.* .rodata2 .literal2.* .literal2 .text2.* .text2)\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b333be1f724cf334e08b9a3f012f93dda022b42c","subject":"Update to match codesigner's expectations: define the symbol start with the value of the reset handler.","message":"Update to match codesigner's expectations: define the symbol\nstart with the value of the reset handler.\n","repos":"google\/tock-on-titan,google\/tock-on-titan,google\/tock-on-titan","old_file":"hotel\/layout.ld","new_file":"hotel\/layout.ld","new_contents":"MEMORY {\n        rom (rx): ORIGIN = 0x44400 LENGTH = 256K\n        ram (w):  ORIGIN = 0x10000 LENGTH = 64K\n}\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\nSECTIONS {\n  .text : {\n    KEEP(*(.vectors))\n    KEEP(*(.irqs))\n    *(.text)\n    \/* codesigner needs start to be defined.\n     * add 1 to set bit 0 (T-bit\/Thumb mode). *\/\n    start = reset_handler + 1;\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > rom\n\n  .apps 0x54000 :\n  {\n    _sapps = .;\n    KEEP(*(.app.*))\n    LONG(0) \/* Marks the end of the app list with a sentinel value. *\/\n    . = 64K;\n  } > rom\n\n  \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n  PROVIDE_HIDDEN (__exidx_start = .);\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > rom\n  PROVIDE_HIDDEN (__exidx_end = .);\n\n  .rodata : {\n    *(.rodata*)\n  } > rom\n\n  _ero = .;\n\n  .data : AT(_ero) {\n    . = ALIGN(4);\n    _sdata = .;\n    *(.data .data.*)\n    . = ALIGN(4);\n    _edata = .;\n  } > ram\n\n  .bss (NOLOAD) : {\n    . = ALIGN(4);\n    _sbss = .;\n    *(.bss .bss.*)\n    _ebss = .;\n\n    _sstack = .;\n    . = . + __stack_size__;\n    . = ALIGN(8);\n    _estack = .;\n\n    . = ALIGN(8K);\n    *(.app_memory)\n  } > ram\n\n}\n","old_contents":"MEMORY {\n        rom (rx): ORIGIN = 0x44400 LENGTH = 256K\n        ram (w):  ORIGIN = 0x10000 LENGTH = 64K\n}\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\nSECTIONS {\n  .text : {\n    KEEP(*(.vectors))\n    KEEP(*(.irqs))\n    *(.text)\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > rom\n\n  .apps 0x54000 :\n  {\n    _sapps = .;\n    KEEP(*(.app.*))\n    LONG(0) \/* Marks the end of the app list with a sentinel value. *\/\n    . = 64K;\n  } > rom\n\n  \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n  PROVIDE_HIDDEN (__exidx_start = .);\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > rom\n  PROVIDE_HIDDEN (__exidx_end = .);\n\n  .rodata : {\n    *(.rodata*)\n  } > rom\n\n  _ero = .;\n\n  .data : AT(_ero) {\n    . = ALIGN(4);\n    _sdata = .;\n    *(.data .data.*)\n    . = ALIGN(4);\n    _edata = .;\n  } > ram\n\n  .bss (NOLOAD) : {\n    . = ALIGN(4);\n    _sbss = .;\n    *(.bss .bss.*)\n    _ebss = .;\n\n    _sstack = .;\n    . = . + __stack_size__;\n    . = ALIGN(8);\n    _estack = .;\n\n    . = ALIGN(8K);\n    *(.app_memory)\n  } > ram\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"30be3d911b2f3045e2032623b04ed1822bf976e5","subject":"add SRAM limits to ld script","message":"add SRAM limits to ld script\n","repos":"sinneb\/wakefield,sinneb\/wakefield,sinneb\/wakefield,thi-ng\/ws-ldn-12,thi-ng\/ws-ldn-12","old_file":"make\/devices\/stm32f746.ld","new_file":"make\/devices\/stm32f746.ld","new_contents":"\/*\n * Default linker script for Cortex-M (it includes specifics for STM32F[34]xx).\n * Based on GNU ARM Eclipse & STM32F7Cube templates\n *\/\n\n\/* Boot entry (defined in startup_stm32f746xx.s) *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY {\n  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 320K\n  \/*\n   * SRAM starts at 0xC0000000, but we reserve memory\n   * for two LCD screen buffers (800 * 480 * 4 * 2)\n   *\/\n  SRAM (xrw)  : ORIGIN = 0xC02EE000, LENGTH = 5192K\n}\n\n\/* Highest address of the user mode stack *\/\n__stack = ORIGIN(RAM) + LENGTH(RAM);\n_estack = __stack; \/* STM specific *\/\n\n\/* Define SRAM region limits *\/\n_sram_start = ORIGIN(SRAM);\n_sram_end = ORIGIN(SRAM) + LENGTH(SRAM);\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Define output sections *\/\nSECTIONS {\n  \/*\n   * For Cortex-M devices, the beginning of the startup code is stored in\n   * the .isr_vector section, which goes to FLASH.\n   *\/\n  .isr_vector : ALIGN(4) {\n    KEEP(*(.isr_vector)) \/* ISR jump table *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* Program code and other data goes into FLASH *\/\n  .text : ALIGN(4) {\n    *(.text .text.*)\n    \/*\n\t\t * Stub sections generated by the linker, to glue together\n\t\t * ARM and Thumb code. .glue_7 is used for ARM code calling\n\t\t * Thumb code, and .glue_7t is used for Thumb code calling\n\t\t * ARM code. Apparently always generated by the linker, for some\n\t\t * architectures, so better leave them here.\n\t\t *\/\n    *(.glue_7 .glue_7t)\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data (constants, strings, etc.) goes into FLASH *\/\n  .rodata : ALIGN(4) {\n    *(.rodata .rodata*)\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab : ALIGN(4) {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } >FLASH\n\n  .ARM : ALIGN(4) {\n    __exidx_start = .;\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array : {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n\n  .init_array : {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n\n  .fini_array : {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : ALIGN(4) {\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  .bss (NOLOAD) : ALIGN(4) {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss .bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack : ALIGN(8) {\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n * Default linker script for Cortex-M (it includes specifics for STM32F[34]xx).\n * Based on GNU ARM Eclipse & STM32F7Cube templates\n *\/\n\n\/* Boot entry (defined in startup_stm32f746xx.s) *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY {\n  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 320K\n  \/*\n   * SRAM starts at 0xC0000000, but we reserve memory\n   * for two LCD screen buffers (800 * 480 * 4 * 2)\n   *\/\n  SRAM (xrw)  : ORIGIN = 0xC02EE000, LENGTH = 5192K\n}\n\n\/* Highest address of the user mode stack *\/\n__stack = ORIGIN(RAM) + LENGTH(RAM);\n_estack = __stack; \/* STM specific *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Define output sections *\/\nSECTIONS {\n  \/*\n   * For Cortex-M devices, the beginning of the startup code is stored in\n   * the .isr_vector section, which goes to FLASH.\n   *\/\n  .isr_vector : ALIGN(4) {\n    KEEP(*(.isr_vector)) \/* ISR jump table *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* Program code and other data goes into FLASH *\/\n  .text : ALIGN(4) {\n    *(.text .text.*)\n    \/*\n\t\t * Stub sections generated by the linker, to glue together\n\t\t * ARM and Thumb code. .glue_7 is used for ARM code calling\n\t\t * Thumb code, and .glue_7t is used for Thumb code calling\n\t\t * ARM code. Apparently always generated by the linker, for some\n\t\t * architectures, so better leave them here.\n\t\t *\/\n    *(.glue_7 .glue_7t)\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data (constants, strings, etc.) goes into FLASH *\/\n  .rodata : ALIGN(4) {\n    *(.rodata .rodata*)\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab : ALIGN(4) {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } >FLASH\n\n  .ARM : ALIGN(4) {\n    __exidx_start = .;\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array : {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n\n  .init_array : {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n\n  .fini_array : {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : ALIGN(4) {\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  .bss (NOLOAD) : ALIGN(4) {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss .bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack : ALIGN(8) {\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f1b261e8dd10b991f82cdbfd2bc504fbab211eb1","subject":"fix huge .bin file outputs","message":"fix huge .bin file outputs\n","repos":"madcowswe\/ODrive,madcowswe\/ODrive,madcowswe\/ODrive,madcowswe\/ODriveFirmware,madcowswe\/ODriveFirmware,madcowswe\/ODrive,madcowswe\/ODrive,madcowswe\/ODriveFirmware,madcowswe\/ODriveFirmware","old_file":"Firmware\/Board\/v3\/STM32F405RGTx_FLASH.ld","new_file":"Firmware\/Board\/v3\/STM32F405RGTx_FLASH.ld","new_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F405RGTx Device with\n**                1024KByte FLASH, 128KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Ac6.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Ac6 permit registered System Workbench for MCU users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the System Workbench for MCU toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20020000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x3C00;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x800; \/* required amount of stack *\/\n_heap_end_max = _estack - _Min_Stack_Size;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\nCCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 768K\nNVM (r)         : ORIGIN = 0x80C0000, LENGTH = 256K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  _siccmram = LOADADDR(.ccmram);\n\n  \/* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section,\n  * the startup code needs to be modified to copy the init-values.\n  * Oskar: Added NOLOAD to remove this section from .bin outputs\n  *\/\n  .ccmram (NOLOAD):\n  {\n    . = ALIGN(4);\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\n  } >CCMRAM \/*AT> FLASH*\/\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","old_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F405RGTx Device with\n**                1024KByte FLASH, 128KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Ac6.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Ac6 permit registered System Workbench for MCU users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the System Workbench for MCU toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20020000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x3C00;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x800; \/* required amount of stack *\/\n_heap_end_max = _estack - _Min_Stack_Size;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\nCCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 768K\nNVM (r)         : ORIGIN = 0x80C0000, LENGTH = 256K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  _siccmram = LOADADDR(.ccmram);\n\n  \/* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section,\n  * the startup code needs to be modified to copy the init-values.  \n  *\/\n  .ccmram :\n  {\n    . = ALIGN(4);\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\n  } >CCMRAM \/*AT> FLASH*\/\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"431c99465c94c4e798463d02fa434014e8c2ae2d","subject":"switch.ld: Merge .crt0 into .text","message":"switch.ld: Merge .crt0 into .text\n","repos":"switchbrew\/libnx","old_file":"nx\/switch.ld","new_file":"nx\/switch.ld","new_contents":"OUTPUT_ARCH(aarch64)\nENTRY(_start)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(5) \/* Read | Execute *\/;\n\trodata PT_LOAD FLAGS(4) \/* Read *\/;\n\tdata   PT_LOAD FLAGS(6) \/* Read | Write *\/;\n\tdyn    PT_DYNAMIC;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\tPROVIDE(__start__ = 0x0);\n\t. = __start__;\n\t__code_start = . ;\n\n\t.text :\n\t{\n\t\tKEEP (*(.crt0))\n\t\t*(.text.unlikely .text.*_unlikely .text.unlikely.*)\n\t\t*(.text.exit .text.exit.*)\n\t\t*(.text.startup .text.startup.*)\n\t\t*(.text.hot .text.hot.*)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.init :\n\t{\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.plt :\n\t{\n\t\t*(.plt)\n\t\t*(.iplt)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.fini :\n\t{\n\t\tKEEP( *(.fini) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t\/* =========== RODATA section =========== *\/\n\t. = ALIGN(0x1000);\n\t__rodata_start = . ;\n\n\t.nx-module-name : { KEEP (*(.nx-module-name)) } :rodata\n\n\t.rodata :\n\t{\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(8);\n\t} :rodata\n\n\t.eh_frame_hdr     : { __eh_frame_hdr_start = .; *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) __eh_frame_hdr_end = .; } :rodata\n\t.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata\n\t.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata\n\t.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata\n\n\t.dynamic           : { *(.dynamic) } :rodata :dyn\n\t.dynsym            : { *(.dynsym) } :rodata\n\t.dynstr            : { *(.dynstr) } :rodata\n\t.rela.dyn          : { *(.rela.*) } :rodata\n\t.interp            : { *(.interp) } :rodata\n\t.hash              : { *(.hash) } :rodata\n\t.gnu.hash          : { *(.gnu.hash) } :rodata\n\t.gnu.version       : { *(.gnu.version) } :rodata\n\t.gnu.version_d     : { *(.gnu.version_d) } :rodata\n\t.gnu.version_r     : { *(.gnu.version_r) } :rodata\n\t.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata\n\n\t\/* =========== DATA section =========== *\/\n\t. = ALIGN(0x1000);\n\t__data_start = . ;\n\n\t.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data\n\t.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data\n\t.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data\n\t.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data\n\n\t.tdata ALIGN(8) :\n\t{\n\t\t__tdata_lma = .;\n\t\t*(.tdata .tdata.* .gnu.linkonce.td.*)\n\t\t. = ALIGN(8);\n\t\t__tdata_lma_end = .;\n\t} :data\n\n\t.tbss ALIGN(8) :\n\t{\n\t\t*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)\n\t\t. = ALIGN(8);\n\t} :data\n\n\t.preinit_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\t} :data\n\n\t.init_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__init_array_start = .);\n\t\tKEEP( *(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)) )\n\t\tKEEP( *(.init_array .ctors) )\n\t\tPROVIDE (__init_array_end = .);\n\t} :data\n\n\t.fini_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__fini_array_start = .);\n\t\tKEEP( *(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)) )\n\t\tKEEP( *(.fini_array .dtors) )\n\t\tPROVIDE (__fini_array_end = .);\n\t} :data\n\n\t__got_start__ = .;\n\n\t.got            : { *(.got) *(.igot) } :data\n\t.got.plt        : { *(.got.plt)  *(.igot.plt) } :data\n\n\t__got_end__ = .;\n\n\t.data ALIGN(8) :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tSORT(CONSTRUCTORS)\n\t} :data\n\n\t__bss_start__ = .;\n\t.bss ALIGN(8) :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\n\t\t\/* Reserve space for the TLS segment of the main thread *\/\n\t\t__tls_start = .;\n\t\t. += + SIZEOF(.tdata) + SIZEOF(.tbss);\n\t\t__tls_end = .;\n\t} : data\n\t__bss_end__ = .;\n\n\t__end__ = ABSOLUTE(.) ;\n\n\t. = ALIGN(0x1000);\n\t__argdata__ = ABSOLUTE(.) ;\n\n\t\/* ==================\n\t   ==== Metadata ====\n\t   ================== *\/\n\n\t\/* Discard sections that difficult post-processing *\/\n\t\/DISCARD\/ : { *(.group .comment .note) }\n\n\t\/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n}\n","old_contents":"OUTPUT_ARCH(aarch64)\nENTRY(_start)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(5) \/* Read | Execute *\/;\n\trodata PT_LOAD FLAGS(4) \/* Read *\/;\n\tdata   PT_LOAD FLAGS(6) \/* Read | Write *\/;\n\tdyn    PT_DYNAMIC;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\tPROVIDE(__start__ = 0x0);\n\t. = __start__;\n\t__code_start = . ;\n\n\t.crt0 :\n\t{\n\t\tKEEP (*(.crt0))\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.init :\n\t{\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.plt :\n\t{\n\t\t*(.plt)\n\t\t*(.iplt)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.text :\n\t{\n\t\t*(.text.unlikely .text.*_unlikely .text.unlikely.*)\n\t\t*(.text.exit .text.exit.*)\n\t\t*(.text.startup .text.startup.*)\n\t\t*(.text.hot .text.hot.*)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.fini :\n\t{\n\t\tKEEP( *(.fini) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t\/* =========== RODATA section =========== *\/\n\t. = ALIGN(0x1000);\n\t__rodata_start = . ;\n\n\t.nx-module-name : { KEEP (*(.nx-module-name)) } :rodata\n\n\t.rodata :\n\t{\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(8);\n\t} :rodata\n\n\t.eh_frame_hdr     : { __eh_frame_hdr_start = .; *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) __eh_frame_hdr_end = .; } :rodata\n\t.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata\n\t.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata\n\t.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata\n\n\t.dynamic           : { *(.dynamic) } :rodata :dyn\n\t.dynsym            : { *(.dynsym) } :rodata\n\t.dynstr            : { *(.dynstr) } :rodata\n\t.rela.dyn          : { *(.rela.*) } :rodata\n\t.interp            : { *(.interp) } :rodata\n\t.hash              : { *(.hash) } :rodata\n\t.gnu.hash          : { *(.gnu.hash) } :rodata\n\t.gnu.version       : { *(.gnu.version) } :rodata\n\t.gnu.version_d     : { *(.gnu.version_d) } :rodata\n\t.gnu.version_r     : { *(.gnu.version_r) } :rodata\n\t.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata\n\n\t\/* =========== DATA section =========== *\/\n\t. = ALIGN(0x1000);\n\t__data_start = . ;\n\n\t.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data\n\t.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data\n\t.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data\n\t.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data\n\n\t.tdata ALIGN(8) :\n\t{\n\t\t__tdata_lma = .;\n\t\t*(.tdata .tdata.* .gnu.linkonce.td.*)\n\t\t. = ALIGN(8);\n\t\t__tdata_lma_end = .;\n\t} :data\n\n\t.tbss ALIGN(8) :\n\t{\n\t\t*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)\n\t\t. = ALIGN(8);\n\t} :data\n\n\t.preinit_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\t} :data\n\n\t.init_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__init_array_start = .);\n\t\tKEEP( *(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)) )\n\t\tKEEP( *(.init_array .ctors) )\n\t\tPROVIDE (__init_array_end = .);\n\t} :data\n\n\t.fini_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__fini_array_start = .);\n\t\tKEEP( *(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)) )\n\t\tKEEP( *(.fini_array .dtors) )\n\t\tPROVIDE (__fini_array_end = .);\n\t} :data\n\n\t__got_start__ = .;\n\n\t.got            : { *(.got) *(.igot) } :data\n\t.got.plt        : { *(.got.plt)  *(.igot.plt) } :data\n\n\t__got_end__ = .;\n\n\t.data ALIGN(8) :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tSORT(CONSTRUCTORS)\n\t} :data\n\n\t__bss_start__ = .;\n\t.bss ALIGN(8) :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\n\t\t\/* Reserve space for the TLS segment of the main thread *\/\n\t\t__tls_start = .;\n\t\t. += + SIZEOF(.tdata) + SIZEOF(.tbss);\n\t\t__tls_end = .;\n\t} : data\n\t__bss_end__ = .;\n\n\t__end__ = ABSOLUTE(.) ;\n\n\t. = ALIGN(0x1000);\n\t__argdata__ = ABSOLUTE(.) ;\n\n\t\/* ==================\n\t   ==== Metadata ====\n\t   ================== *\/\n\n\t\/* Discard sections that difficult post-processing *\/\n\t\/DISCARD\/ : { *(.group .comment .note) }\n\n\t\/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"2469d864a3a78ff82d8d651a36da451ec2c33b4c","subject":"Update LPC1768.ld linker script to work with net stack.","message":"Update LPC1768.ld linker script to work with net stack.\n\nThe original script assigned memory ranges to USB_RAM and ETH_RAM but\nit never placed any section data in those regions.  I added clauses\ntowards the bottom of the script to place data that the programmer\nhas marked for the AHBSRAM0 and AHBSRAM1 sections into these regions\nof RAM.  Previously the data destined for these sections was being\nplaced in the lower 32K RAM bank and overflowing it at link time.\n\nI also added a few Image$$ linker symbols to mimic those used by the\nonline compiler.  I have had samples in the past which took advantage\nof these to display static memory statistics for each SRAM region.\n\nI also changed LENGTH=0x7F38 to LENGTH=(32K - 0xC8) to make it more\nconsistent with the sizing of the other regions in this script which\nuse human readable K sizing information.  The 0xC8 subtraction reflects\nthe starting offset of 0xC8 for this region.\n","repos":"Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos","old_file":"TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_file":"TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Code can explicitly ask for data to be \n       placed in these higher RAM banks where\n       they will be left uninitialized. \n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7debf3f4898c27fe155261683786af43bbb00469","subject":"[IA64] minios: Fix ctor and dtor sections.","message":"[IA64] minios: Fix ctor and dtor sections.\n\nSigned-off-by: Dietmar Hahn <920241d11b17e2f8a8a4ba9c87c3918c54fb747d@fujitsu-siemens.com>\n","repos":"rowhit\/xen-minios,rowhit\/xen-minios,rowhit\/xen-minios","old_file":"arch\/ia64\/minios-ia64.lds","new_file":"arch\/ia64\/minios-ia64.lds","new_contents":"OUTPUT_FORMAT(\"elf64-ia64-little\")\nOUTPUT_ARCH(ia64)\n\nENTRY(phys_start)\n\nPHDRS\n{\n  code PT_LOAD;\n  data PT_LOAD;\n}\n\nSECTIONS\n{\n\n  phys_start = _start - (((5<<(61))+0x100000000) - (1 << 20));\n\n  code : { } :code\n  . = ((5<<(61))+0x100000000);\n\n  _text = .;\n\n  .text : AT(ADDR(.text) - (((5<<(61))+0x100000000) - (1 << 20)))\n  {\n    *(.text)\n  }\n\n  _etext = .;\n\n  data : { } :data\n  .data : AT(ADDR(.data) - (((5<<(61))+0x100000000) - (1 << 20)))\n  { *(.data) \n  }\n\n  .sdata : AT(ADDR(.sdata) - (((5<<(61))+0x100000000) - (1 << 20)))\n        { *(.sdata) *(.sdata1) *(.srdata) }\n\n  .rodata : AT(ADDR(.rodata) - (((5<<(61))+0x100000000) - (1 << 20)))\n  { *(.rodata) }\n\n  .rodata.str1.8 : AT(ADDR(.rodata.str1.8) - (((5<<(61))+0x100000000) - (1 << 20)))\n  { *(.rodata.str1.8) }\n\n  \/* newlib initialization functions *\/\n  . = ALIGN(64 \/ 8);\n  PROVIDE (__preinit_array_start = .);\n  .preinit_array     : { *(.preinit_array) }\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { *(.init_array) }\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { *(.fini_array) }\n  PROVIDE (__fini_array_end = .);\n\n  .ctors : AT(ADDR(.ctors) - (((5<<(61))+0x100000000) - (1 << 20)))\n\t{\n        __CTOR_LIST__ = .;\n        QUAD((__CTOR_END__ - __CTOR_LIST__) \/ 8 - 2)\n        *(.ctors)\n\tCONSTRUCTORS\n        QUAD(0)\n        __CTOR_END__ = .;\n        }\n\n  .dtors : AT(ADDR(.dtors) - (((5<<(61))+0x100000000) - (1 << 20)))\n        {\n        __DTOR_LIST__ = .;\n        QUAD((__DTOR_END__ - __DTOR_LIST__) \/ 8 - 2)\n        *(.dtors)\n        QUAD(0)\n        __DTOR_END__ = .;\n        }\n\n  .IA_64.unwind_info : AT(ADDR(.IA_64.unwind_info) - (((5<<(61))+0x100000000) - (1 << 20)))\n  { *(.IA_64.unwind_info) }\n\n  .IA_64.unwind : AT(ADDR(.IA_64.unwind) - (((5<<(61))+0x100000000) - (1 << 20)))\n  { *(.IA_64.unwind) }\n\n  .bss : AT(ADDR(.bss) - (((5<<(61))+0x100000000) - (1 << 20)))\n  {\n    *(.bss)\n    *(.app.bss)\n  }\n\n  _end = .;\n\n}\n","old_contents":"OUTPUT_FORMAT(\"elf64-ia64-little\")\nOUTPUT_ARCH(ia64)\n\nENTRY(phys_start)\n\nPHDRS\n{\n  code PT_LOAD;\n  data PT_LOAD;\n}\n\nSECTIONS\n{\n\n  phys_start = _start - (((5<<(61))+0x100000000) - (1 << 20));\n\n  code : { } :code\n  . = ((5<<(61))+0x100000000);\n\n  _text = .;\n\n  .text : AT(ADDR(.text) - (((5<<(61))+0x100000000) - (1 << 20)))\n  {\n    *(.text)\n  }\n\n  _etext = .;\n\n  data : { } :data\n  .data : AT(ADDR(.data) - (((5<<(61))+0x100000000) - (1 << 20)))\n  { *(.data) \n  }\n\n  .sdata : AT(ADDR(.sdata) - (((5<<(61))+0x100000000) - (1 << 20)))\n        { *(.sdata) *(.sdata1) *(.srdata) }\n\n  .rodata : AT(ADDR(.rodata) - (((5<<(61))+0x100000000) - (1 << 20)))\n  { *(.rodata) }\n\n  .rodata.str1.8 : AT(ADDR(.rodata.str1.8) - (((5<<(61))+0x100000000) - (1 << 20)))\n  { *(.rodata.str1.8) }\n\n  \/* newlib initialization functions *\/\n  . = ALIGN(64 \/ 8);\n  PROVIDE (__preinit_array_start = .);\n  .preinit_array     : { *(.preinit_array) }\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { *(.init_array) }\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { *(.fini_array) }\n  PROVIDE (__fini_array_end = .);\n\n  .ctors : {\n        __CTOR_LIST__ = .;\n        QUAD((__CTOR_END__ - __CTOR_LIST__) \/ 8 - 2)\n        *(.ctors)\n\tCONSTRUCTORS\n        QUAD(0)\n        __CTOR_END__ = .;\n        }\n\n  .dtors : {\n        __DTOR_LIST__ = .;\n        QUAD((__DTOR_END__ - __DTOR_LIST__) \/ 8 - 2)\n        *(.dtors)\n        QUAD(0)\n        __DTOR_END__ = .;\n        }\n\n  .IA_64.unwind_info : AT(ADDR(.IA_64.unwind_info) - (((5<<(61))+0x100000000) - (1 << 20)))\n  { *(.IA_64.unwind_info) }\n\n  .IA_64.unwind : AT(ADDR(.IA_64.unwind) - (((5<<(61))+0x100000000) - (1 << 20)))\n  { *(.IA_64.unwind) }\n\n  .bss : AT(ADDR(.bss) - (((5<<(61))+0x100000000) - (1 << 20)))\n  {\n    *(.bss)\n    *(.app.bss)\n  }\n\n  _end = .;\n\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"3fd8180c5fde9976daedcba60109b1102298c79d","subject":"keloader.ld tab-formating error","message":"keloader.ld tab-formating error\n","repos":"fiinix00\/CSharpKernel,fiinix00\/CSharpKernel,fiinix00\/CSharpKernel,fiinix00\/CSharpKernel","old_file":"Kernel\/keloader.ld","new_file":"Kernel\/keloader.ld","new_contents":"ENTRY(_start)\n\nSECTIONS\n{\n\tstart = 0; _start = start; __start = start;\n\t.text 0x10200: \n\t{ \n\t\tkcode = .; _kcode = .; __kcode = .;\n\t\t\tKernel\\keloader.o(.text*)\n\t\tkcode_end = .; _kcode_end = .; __kcode_end = .;\t\n\t}\n\n\t. = ALIGN(4096);\n\n\t.data . :\n\t{\n\t\tkdata = .; _kdata = .; __kdata = .;\n\t\t\tKernel\\keloader.o(.data)\n\t\t\tKernel\\keloader.o(.rodata)\n\t\tkdata_end = .; _kdata_end = .; __kdata_end = .;\n\t}\n\n\t. = ALIGN(4096);\n\n\t.bss . :\n\t{\n\t\tkbss = .; _kbss = .; __kbss = .;\n\t\t\tKernel\\keloader.o(.bss)\n\t\tkbss_end = .; _kbss_end = .; __kbss_end = .;    \n\t}\n\n\t. = ALIGN(4096);\n\n\t.text . :\n\t{\n\t\tcode = .; _code = .; __code = .;\n\t\t\tKernel\\cmain.o(.text*)\t\n\t\tcode_end = .; _code_end = .; __code_end = .;\n\t}\n\n\t. = ALIGN(4096);\n\n\tend = .; _end = .; __end = .;\n\n\t\/DISCARD\/ : {\n\t\t*(.note*);\n\t\t*(.iplt*);\n\t\t*(.igot*);\n\t\t\n\t\t*(.comment);\n\t}\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS\n{\n\tstart = 0; _start = start; __start = start;\n\t.text 0x10200: \n\t{ \n\t\tkcode = .; _kcode = .; __kcode = .;\n\t\t\tKernel\\keloader.o(.text*)\n\t\tkcode_end = .; _kcode_end = .; __kcode_end = .;\t\n\t}\n\n\t. = ALIGN(4096);\n\n\t.data . :\n\t{\n\t\tkdata = .; _kdata = .; __kdata = .;\n\t\t\tKernel\\keloader.o(.data)\n\t\t\tKernel\\keloader.o(.rodata)\n\t\tkdata_end = .; _kdata_end = .; __kdata_end = .;\n\t}\n\n\t. = ALIGN(4096);\n\n\t.bss . :\n    {\n        kbss = .; _kbss = .; __kbss = .;\n\t\t\tKernel\\keloader.o(.bss)\n\t\tkbss_end = .; _kbss_end = .; __kbss_end = .;    \n    }\n\n\t. = ALIGN(4096);\n\n\t.text . :\n\t{\n\t\tcode = .; _code = .; __code = .;\n\t\t\tKernel\\cmain.o(.text*)\t\n\t\tcode_end = .; _code_end = .; __code_end = .;\n\t}\n\n\t. = ALIGN(4096);\n\n\tend = .; _end = .; __end = .;\n\n\t\/DISCARD\/ : {\n\t\t*(.note*);\n\t\t*(.iplt*);\n\t\t*(.igot*);\n\t\t\n\t\t*(.comment);\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8348517bbba5964b8addec295478a5652940fbc0","subject":"Fixed section names in linker script for TEENSY3_1 when using GCC_ARM","message":"Fixed section names in linker script for TEENSY3_1 when using GCC_ARM\n","repos":"mazimkhan\/mbed-os,alertby\/mbed,pbrook\/mbed,mazimkhan\/mbed-os,infinnovation\/mbed-os,pradeep-gr\/mbed-os5-onsemi,kl-cruz\/mbed-os,ryankurte\/mbed-os,nabilbendafi\/mbed,Timmmm\/mbed,jferreir\/mbed,NXPmicro\/mbed,masaohamanaka\/mbed,geky\/mbed,pedromes\/mbed,fahhem\/mbed-os,svastm\/mbed,Shengliang\/mbed,hwfwgrp\/mbed,rosterloh\/mbed,rgrover\/mbed,pedromes\/mbed,NXPmicro\/mbed,betzw\/mbed-os,ryankurte\/mbed-os,naves-thiago\/mbed-midi,monkiineko\/mbed-os,DanKupiniak\/mbed,bcostm\/mbed-os,betzw\/mbed-os,mikaleppanen\/mbed-os,monkiineko\/mbed-os,brstew\/MBED-BUILD,andreaslarssonublox\/mbed,tung7970\/mbed-os,ban4jp\/mbed,nvlsianpu\/mbed,betzw\/mbed-os,mazimkhan\/mbed-os,nabilbendafi\/mbed,Shengliang\/mbed,fahhem\/mbed-os,getopenmono\/mbed,RonEld\/mbed,jpbrucker\/mbed,svogl\/mbed-os,monkiineko\/mbed-os,adamgreen\/mbed,jrjang\/mbed,fpiot\/mbed-ats,kl-cruz\/mbed-os,EmuxEvans\/mbed,nRFMesh\/mbed-os,bentwire\/mbed,JasonHow44\/mbed,Tiryoh\/mbed,getopenmono\/mbed,YarivCol\/mbed-os,Timmmm\/mbed,wodji\/mbed,pi19404\/mbed,infinnovation\/mbed-os,tung7970\/mbed-os,catiedev\/mbed-os,Shengliang\/mbed,hwfwgrp\/mbed,bikeNomad\/mbed,JasonHow44\/mbed,dbestm\/mbed,ryankurte\/mbed-os,jamesadevine\/mbed,logost\/mbed,fvincenzo\/mbed-os,Timmmm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,mazimkhan\/mbed-os,andcor02\/mbed-os,bcostm\/mbed-os,j-greffe\/mbed-os,EmuxEvans\/mbed,arostm\/mbed-os,bikeNomad\/mbed,xcrespo\/mbed,maximmbed\/mbed,bentwire\/mbed,fanghuaqi\/mbed,alertby\/mbed,bentwire\/mbed,karsev\/mbed-os,arostm\/mbed-os,Marcomissyou\/mbed,fpiot\/mbed-ats,bcostm\/mbed-os,cvtsi2sd\/mbed-os,ryankurte\/mbed-os,Archcady\/mbed-os,dbestm\/mbed,JasonHow44\/mbed,al177\/mbed,c1728p9\/mbed-os,pedromes\/mbed,bentwire\/mbed,RonEld\/mbed,Tiryoh\/mbed,RonEld\/mbed,jpbrucker\/mbed,jrjang\/mbed,mikaleppanen\/mbed-os,rgrover\/mbed,jeremybrodt\/mbed,ban4jp\/mbed,HeadsUpDisplayInc\/mbed,Marcomissyou\/mbed,JasonHow44\/mbed,struempelix\/mbed,bulislaw\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,mnlipp\/mbed,karsev\/mbed-os,screamerbg\/mbed,YarivCol\/mbed-os,maximmbed\/mbed,devanlai\/mbed,logost\/mbed,fahhem\/mbed-os,pi19404\/mbed,catiedev\/mbed-os,devanlai\/mbed,mmorenobarm\/mbed-os,larks\/mbed,brstew\/MBED-BUILD,kpurusho\/mbed,mmorenobarm\/mbed-os,Sweet-Peas\/mbed,Tiryoh\/mbed,ban4jp\/mbed,NXPmicro\/mbed,karsev\/mbed-os,fpiot\/mbed-ats,nabilbendafi\/mbed,jeremybrodt\/mbed,rosterloh\/mbed,alertby\/mbed,xcrespo\/mbed,bcostm\/mbed-os,CalSol\/mbed,netzimme\/mbed-os,CalSol\/mbed,NXPmicro\/mbed,fvincenzo\/mbed-os,nvlsianpu\/mbed,kpurusho\/mbed,c1728p9\/mbed-os,Timmmm\/mbed,rgrover\/mbed,autopulated\/mbed,bulislaw\/mbed-os,jamesadevine\/mbed,larks\/mbed,j-greffe\/mbed-os,autopulated\/mbed,nabilbendafi\/mbed,brstew\/MBED-BUILD,adustm\/mbed,larks\/mbed,nRFMesh\/mbed-os,hwfwgrp\/mbed,kl-cruz\/mbed-os,struempelix\/mbed,HeadsUpDisplayInc\/mbed,svastm\/mbed,catiedev\/mbed-os,xcrespo\/mbed,jferreir\/mbed,mnlipp\/mbed,EmuxEvans\/mbed,catiedev\/mbed-os,pedromes\/mbed,theotherjimmy\/mbed,nRFMesh\/mbed-os,mbedmicro\/mbed,brstew\/MBED-BUILD,EmuxEvans\/mbed,screamerbg\/mbed,Timmmm\/mbed,devanlai\/mbed,adustm\/mbed,kl-cruz\/mbed-os,cvtsi2sd\/mbed-os,fahhem\/mbed-os,larks\/mbed,nvlsianpu\/mbed,tung7970\/mbed-os-1,K4zuki\/mbed,hwfwgrp\/mbed,YarivCol\/mbed-os,bikeNomad\/mbed,RonEld\/mbed,masaohamanaka\/mbed,Archcady\/mbed-os,c1728p9\/mbed-os,infinnovation\/mbed-os,tung7970\/mbed-os-1,mbedmicro\/mbed,adustm\/mbed,kl-cruz\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,screamerbg\/mbed,jferreir\/mbed,pbrook\/mbed,monkiineko\/mbed-os,rosterloh\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,Shengliang\/mbed,fanghuaqi\/mbed,betzw\/mbed-os,tung7970\/mbed-os,karsev\/mbed-os,rgrover\/mbed,maximmbed\/mbed,nRFMesh\/mbed-os,dbestm\/mbed,jeremybrodt\/mbed,autopulated\/mbed,netzimme\/mbed-os,adamgreen\/mbed,nRFMesh\/mbed-os,jferreir\/mbed,alertby\/mbed,c1728p9\/mbed-os,ban4jp\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed,rosterloh\/mbed,jpbrucker\/mbed,Sweet-Peas\/mbed,tung7970\/mbed-os-1,YarivCol\/mbed-os,brstew\/MBED-BUILD,pradeep-gr\/mbed-os5-onsemi,Shengliang\/mbed,Archcady\/mbed-os,DanKupiniak\/mbed,theotherjimmy\/mbed,geky\/mbed,jeremybrodt\/mbed,bikeNomad\/mbed,pi19404\/mbed,getopenmono\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,theotherjimmy\/mbed,getopenmono\/mbed,EmuxEvans\/mbed,j-greffe\/mbed-os,bulislaw\/mbed-os,kpurusho\/mbed,nvlsianpu\/mbed,wodji\/mbed,kpurusho\/mbed,mnlipp\/mbed,al177\/mbed,tung7970\/mbed-os-1,xcrespo\/mbed,DanKupiniak\/mbed,YarivCol\/mbed-os,arostm\/mbed-os,fvincenzo\/mbed-os,tung7970\/mbed-os-1,nRFMesh\/mbed-os,screamerbg\/mbed,larks\/mbed,mnlipp\/mbed,dbestm\/mbed,ryankurte\/mbed-os,fvincenzo\/mbed-os,Tiryoh\/mbed,devanlai\/mbed,logost\/mbed,bikeNomad\/mbed,maximmbed\/mbed,YarivCol\/mbed-os,getopenmono\/mbed,Marcomissyou\/mbed,fpiot\/mbed-ats,al177\/mbed,Sweet-Peas\/mbed,pedromes\/mbed,Marcomissyou\/mbed,arostm\/mbed-os,fahhem\/mbed-os,jeremybrodt\/mbed,naves-thiago\/mbed-midi,netzimme\/mbed-os,netzimme\/mbed-os,wodji\/mbed,svastm\/mbed,svogl\/mbed-os,ryankurte\/mbed-os,hwfwgrp\/mbed,RonEld\/mbed,monkiineko\/mbed-os,cvtsi2sd\/mbed-os,nabilbendafi\/mbed,autopulated\/mbed,HeadsUpDisplayInc\/mbed,masaohamanaka\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,CalSol\/mbed,theotherjimmy\/mbed,K4zuki\/mbed,EmuxEvans\/mbed,catiedev\/mbed-os,logost\/mbed,mmorenobarm\/mbed-os,struempelix\/mbed,ban4jp\/mbed,infinnovation\/mbed-os,pradeep-gr\/mbed-os5-onsemi,jamesadevine\/mbed,andcor02\/mbed-os,jferreir\/mbed,pbrook\/mbed,kpurusho\/mbed,andcor02\/mbed-os,adamgreen\/mbed,jpbrucker\/mbed,larks\/mbed,pedromes\/mbed,bcostm\/mbed-os,j-greffe\/mbed-os,fanghuaqi\/mbed,dbestm\/mbed,andreaslarssonublox\/mbed,naves-thiago\/mbed-midi,bulislaw\/mbed-os,jrjang\/mbed,screamerbg\/mbed,nvlsianpu\/mbed,devanlai\/mbed,autopulated\/mbed,struempelix\/mbed,adustm\/mbed,jferreir\/mbed,mbedmicro\/mbed,rgrover\/mbed,mazimkhan\/mbed-os,nvlsianpu\/mbed,monkiineko\/mbed-os,svogl\/mbed-os,logost\/mbed,ARM-software\/mbed-beetle,bentwire\/mbed,CalSol\/mbed,mmorenobarm\/mbed-os,CalSol\/mbed,rosterloh\/mbed,karsev\/mbed-os,jrjang\/mbed,jrjang\/mbed,pbrook\/mbed,cvtsi2sd\/mbed-os,fanghuaqi\/mbed,svogl\/mbed-os,struempelix\/mbed,Sweet-Peas\/mbed,dbestm\/mbed,bentwire\/mbed,netzimme\/mbed-os,mbedmicro\/mbed,cvtsi2sd\/mbed-os,logost\/mbed,j-greffe\/mbed-os,hwfwgrp\/mbed,ban4jp\/mbed,mmorenobarm\/mbed-os,masaohamanaka\/mbed,NXPmicro\/mbed,fvincenzo\/mbed-os,Marcomissyou\/mbed,naves-thiago\/mbed-midi,K4zuki\/mbed,kpurusho\/mbed,j-greffe\/mbed-os,mikaleppanen\/mbed-os,HeadsUpDisplayInc\/mbed,masaohamanaka\/mbed,K4zuki\/mbed,K4zuki\/mbed,catiedev\/mbed-os,Archcady\/mbed-os,ARM-software\/mbed-beetle,HeadsUpDisplayInc\/mbed,theotherjimmy\/mbed,geky\/mbed,brstew\/MBED-BUILD,c1728p9\/mbed-os,pi19404\/mbed,al177\/mbed,infinnovation\/mbed-os,wodji\/mbed,xcrespo\/mbed,JasonHow44\/mbed,c1728p9\/mbed-os,getopenmono\/mbed,Sweet-Peas\/mbed,autopulated\/mbed,nabilbendafi\/mbed,adamgreen\/mbed,pbrook\/mbed,theotherjimmy\/mbed,alertby\/mbed,pradeep-gr\/mbed-os5-onsemi,ARM-software\/mbed-beetle,al177\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,mikaleppanen\/mbed-os,pi19404\/mbed,svogl\/mbed-os,pbrook\/mbed,andreaslarssonublox\/mbed,DanKupiniak\/mbed,bulislaw\/mbed-os,mmorenobarm\/mbed-os,geky\/mbed,adamgreen\/mbed,jpbrucker\/mbed,bcostm\/mbed-os,svogl\/mbed-os,kl-cruz\/mbed-os,maximmbed\/mbed,infinnovation\/mbed-os,Shengliang\/mbed,Timmmm\/mbed,struempelix\/mbed,tung7970\/mbed-os,pradeep-gr\/mbed-os5-onsemi,karsev\/mbed-os,mikaleppanen\/mbed-os,andcor02\/mbed-os,mazimkhan\/mbed-os,cvtsi2sd\/mbed-os,fpiot\/mbed-ats,arostm\/mbed-os,NXPmicro\/mbed,geky\/mbed,fanghuaqi\/mbed,screamerbg\/mbed,Tiryoh\/mbed,tung7970\/mbed-os,svastm\/mbed,maximmbed\/mbed,pi19404\/mbed,jrjang\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,adamgreen\/mbed,mnlipp\/mbed,andcor02\/mbed-os,rosterloh\/mbed,wodji\/mbed,al177\/mbed,HeadsUpDisplayInc\/mbed,wodji\/mbed,mnlipp\/mbed,alertby\/mbed,andreaslarssonublox\/mbed,pradeep-gr\/mbed-os5-onsemi,jamesadevine\/mbed,ARM-software\/mbed-beetle,xcrespo\/mbed,jamesadevine\/mbed,JasonHow44\/mbed,mikaleppanen\/mbed-os,jpbrucker\/mbed,masaohamanaka\/mbed,RonEld\/mbed,naves-thiago\/mbed-midi,Tiryoh\/mbed,K4zuki\/mbed,arostm\/mbed-os,betzw\/mbed-os,adustm\/mbed,andreaslarssonublox\/mbed,fpiot\/mbed-ats,adustm\/mbed,fahhem\/mbed-os,Marcomissyou\/mbed,naves-thiago\/mbed-midi,Sweet-Peas\/mbed,Archcady\/mbed-os,bulislaw\/mbed-os,CalSol\/mbed,jamesadevine\/mbed,devanlai\/mbed,betzw\/mbed-os,Archcady\/mbed-os,svastm\/mbed,netzimme\/mbed-os","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_Freescale\/TARGET_K20XX\/TARGET_TEENSY3_1\/TOOLCHAIN_GCC_ARM\/MK20DX256.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_Freescale\/TARGET_K20XX\/TARGET_TEENSY3_1\/TOOLCHAIN_GCC_ARM\/MK20DX256.ld","new_contents":"\/*\n * K20DX256 ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH_PROTECTION\t(rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410\n  RAM (rwx) : ORIGIN = 0x1FFF81C0, LENGTH = 64K - 0x1C0\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        . = 0;\n        __isr_vector = .;\n        KEEP(*(.isr_vector))\n        *(.text.Reset_Handler)\n        *(.text.SystemInit)\n         . = ALIGN(4);\n    } > VECTORS\n\n    .flash_protect :\n    {\n        KEEP(*(.kinetis_flash_config_field))\n         . = ALIGN(4);\n    } > FLASH_PROTECTION\n\n    .text :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/*\n * K20DX256 ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH_PROTECTION\t(rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410\n  RAM (rwx) : ORIGIN = 0x1FFF81C0, LENGTH = 64K - 0x1C0\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        *(.text.Reset_Handler)\n        *(.text.System_Init)\n         . = ALIGN(4);\n    } > VECTORS\n\n    .flash_protect :\n    {\n        KEEP(*(.kinetis_flash_config_field))\n         . = ALIGN(4);\n    } > FLASH_PROTECTION\n\n    .text :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"86c7bb204117dc869a075539437d61118539b652","subject":"Remove whitespaces from ld script","message":"Remove whitespaces from ld script\n","repos":"iabdalkader\/openmv,iabdalkader\/openmv,kwagyeman\/openmv,tianzhihen\/openmv,tianzhihen\/openmv,tianzhihen\/openmv,SmartArduino\/openmv,iabdalkader\/openmv,SmartArduino\/openmv,openmv\/openmv,openmv\/openmv,kwagyeman\/openmv,kwagyeman\/openmv,openmv\/openmv,SmartArduino\/openmv,tianzhihen\/openmv,SmartArduino\/openmv,kwagyeman\/openmv,iabdalkader\/openmv,openmv\/openmv","old_file":"src\/stm32f4xx.ld","new_file":"src\/stm32f4xx.ld","new_contents":"\/**\n *  Linker script for STM32F4xx Devices with 1MB FLASH, 192KB RAM (64KB CCM)\n *\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K\n  FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 512K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n  CCM (w!rx)      : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Highest address of the user mode stack *\/\n_estack     = 0x10010000; \/* Stack is allocated on CCM block *\/\n\n_ram_end   = 0x10010000; \/* 64KB CCM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_stack_size = 0x1000; \/* required amount of stack *\/\n_heap_size  = 0x8000; \/* required amount of heap *\/\n_cache_size = 0x4000; \/* required amount of cache *\/\n\n_main_ram_start = 0x20000000;\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH_ISR\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n    _exit = .;\n  } >FLASH_TEXT\n\n  .ARM.extab   : {\n      *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } >FLASH_TEXT\n\n  .ARM : {\n  __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH_TEXT\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH_TEXT\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH_TEXT\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH_TEXT\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    _ram_start = .;\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >CCM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >CCM\n\n  ._heap :\n  {\n    . = ALIGN(4);\n    _heap_start = .;\n    . = . + _heap_size;\n    . = ALIGN(4);\n    _heap_end  = .;\n  } >CCM\n\n  \/* Make sure there is enough RAM left for the stack *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _cache_size;\n    . = . + _stack_size;\n    . = ALIGN(4);\n  } >CCM\n\n  \/* Remove information from the standard libraries *\/\n  \/*\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n  *\/\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/**\n *  Linker script for STM32F4xx Devices with 1MB FLASH, 192KB RAM (64KB CCM)\n *\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K \n  FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 512K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n  CCM (w!rx)      : ORIGIN = 0x10000000, LENGTH = 64K                   \n}\n\n\/* Highest address of the user mode stack *\/\n_estack     = 0x10010000; \/* Stack is allocated on CCM block *\/\n\n_ram_end   = 0x10010000; \/* 64KB CCM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_stack_size = 0x1000; \/* required amount of stack *\/\n_heap_size  = 0x8000; \/* required amount of heap *\/\n_cache_size = 0x4000; \/* required amount of cache *\/\n\n_main_ram_start = 0x20000000;\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH_ISR\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n    _exit = .;\n  } >FLASH_TEXT\n\n  .ARM.extab   : {\n      *(.ARM.extab* .gnu.linkonce.armextab.*) \n  } >FLASH_TEXT\n\n  .ARM : {\n  __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH_TEXT\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH_TEXT\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH_TEXT\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH_TEXT\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    _ram_start = .;\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >CCM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >CCM\n\n  ._heap :\n  {\n    . = ALIGN(4);\n    _heap_start = .;\n    . = . + _heap_size;\n    . = ALIGN(4);\n    _heap_end  = .;\n  } >CCM\n\n  \/* Make sure there is enough RAM left for the stack *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _cache_size;\n    . = . + _stack_size;\n    . = ALIGN(4);\n  } >CCM\n\n  \/* Remove information from the standard libraries *\/\n  \/*\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n  *\/\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"6c3f9bd4850eb7fd76bdc1551af2d4ddf7200e2c","subject":"reserved topmost 32 bytes of RAM used by IAP functions","message":"reserved topmost 32 bytes of RAM used by IAP functions\n\nNXP LPC176x\/5x User Manual UM10360 Rev 4.1:\r\n32.3.2.8 RAM used by IAP command handler\r\nFlash programming commands use the top 32 bytes of on-chip RAM. The maximum stack \r\nusage in the user allocated stack space is 128 bytes and it grows downwards.","repos":"mikaleppanen\/mbed-os,mbedmicro\/mbed,Archcady\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,mmorenobarm\/mbed-os,catiedev\/mbed-os,andcor02\/mbed-os,pradeep-gr\/mbed-os5-onsemi,betzw\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,svogl\/mbed-os,mazimkhan\/mbed-os,Archcady\/mbed-os,adamgreen\/mbed,netzimme\/mbed-os,YarivCol\/mbed-os,bcostm\/mbed-os,fahhem\/mbed-os,NXPmicro\/mbed,CalSol\/mbed,mbedmicro\/mbed,arostm\/mbed-os,ryankurte\/mbed-os,HeadsUpDisplayInc\/mbed,monkiineko\/mbed-os,mmorenobarm\/mbed-os,kjbracey-arm\/mbed,NXPmicro\/mbed,netzimme\/mbed-os,HeadsUpDisplayInc\/mbed,catiedev\/mbed-os,mmorenobarm\/mbed-os,Archcady\/mbed-os,catiedev\/mbed-os,karsev\/mbed-os,kl-cruz\/mbed-os,betzw\/mbed-os,kl-cruz\/mbed-os,karsev\/mbed-os,infinnovation\/mbed-os,karsev\/mbed-os,arostm\/mbed-os,c1728p9\/mbed-os,monkiineko\/mbed-os,kjbracey-arm\/mbed,nRFMesh\/mbed-os,ryankurte\/mbed-os,svogl\/mbed-os,betzw\/mbed-os,kl-cruz\/mbed-os,NXPmicro\/mbed,kjbracey-arm\/mbed,HeadsUpDisplayInc\/mbed,fahhem\/mbed-os,netzimme\/mbed-os,screamerbg\/mbed,netzimme\/mbed-os,screamerbg\/mbed,infinnovation\/mbed-os,monkiineko\/mbed-os,betzw\/mbed-os,mikaleppanen\/mbed-os,NXPmicro\/mbed,pradeep-gr\/mbed-os5-onsemi,adamgreen\/mbed,svogl\/mbed-os,mmorenobarm\/mbed-os,karsev\/mbed-os,kjbracey-arm\/mbed,arostm\/mbed-os,CalSol\/mbed,mazimkhan\/mbed-os,screamerbg\/mbed,karsev\/mbed-os,YarivCol\/mbed-os,ryankurte\/mbed-os,ryankurte\/mbed-os,arostm\/mbed-os,nRFMesh\/mbed-os,infinnovation\/mbed-os,infinnovation\/mbed-os,YarivCol\/mbed-os,adamgreen\/mbed,CalSol\/mbed,netzimme\/mbed-os,c1728p9\/mbed-os,pradeep-gr\/mbed-os5-onsemi,catiedev\/mbed-os,HeadsUpDisplayInc\/mbed,mazimkhan\/mbed-os,monkiineko\/mbed-os,Archcady\/mbed-os,mbedmicro\/mbed,CalSol\/mbed,bcostm\/mbed-os,netzimme\/mbed-os,mazimkhan\/mbed-os,NXPmicro\/mbed,c1728p9\/mbed-os,Archcady\/mbed-os,ryankurte\/mbed-os,infinnovation\/mbed-os,fahhem\/mbed-os,bcostm\/mbed-os,screamerbg\/mbed,fahhem\/mbed-os,nRFMesh\/mbed-os,monkiineko\/mbed-os,screamerbg\/mbed,pradeep-gr\/mbed-os5-onsemi,kl-cruz\/mbed-os,fahhem\/mbed-os,bcostm\/mbed-os,nRFMesh\/mbed-os,adamgreen\/mbed,bcostm\/mbed-os,adamgreen\/mbed,YarivCol\/mbed-os,c1728p9\/mbed-os,arostm\/mbed-os,mikaleppanen\/mbed-os,svogl\/mbed-os,screamerbg\/mbed,pradeep-gr\/mbed-os5-onsemi,mazimkhan\/mbed-os,kl-cruz\/mbed-os,infinnovation\/mbed-os,nRFMesh\/mbed-os,mmorenobarm\/mbed-os,adamgreen\/mbed,andcor02\/mbed-os,NXPmicro\/mbed,mbedmicro\/mbed,YarivCol\/mbed-os,kl-cruz\/mbed-os,betzw\/mbed-os,YarivCol\/mbed-os,Archcady\/mbed-os,catiedev\/mbed-os,mikaleppanen\/mbed-os,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,CalSol\/mbed,karsev\/mbed-os,andcor02\/mbed-os,mikaleppanen\/mbed-os,CalSol\/mbed,HeadsUpDisplayInc\/mbed,svogl\/mbed-os,andcor02\/mbed-os,pradeep-gr\/mbed-os5-onsemi,catiedev\/mbed-os,betzw\/mbed-os,arostm\/mbed-os,nRFMesh\/mbed-os,svogl\/mbed-os,mazimkhan\/mbed-os,fahhem\/mbed-os,bcostm\/mbed-os,mmorenobarm\/mbed-os,ryankurte\/mbed-os,monkiineko\/mbed-os,mikaleppanen\/mbed-os","old_file":"targets\/TARGET_NXP\/TARGET_LPC176X\/device\/TOOLCHAIN_GCC_CR\/LPC1768.ld","new_file":"targets\/TARGET_NXP\/TARGET_LPC176X\/device\/TOOLCHAIN_GCC_CR\/LPC1768.ld","new_contents":"\/* mbed - LPC1768 linker script\n * Based linker script generated by Code Red Technologies Red Suite 4.1\n *\/\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 \/* 512k *\/\n  RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F18 \/* 32k (topmost 32 bytes used by IAP functions) *\/\n  RamAHB_USB (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x4000 \/* 16k *\/\n  RamAHB_Eth (rwx) : ORIGIN = 0x20080000, LENGTH = 0x4000 \/* 16k *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash512 = 0x0 + 0x80000;\n  __top_RamLoc32 = 0x10000000 + 0x8000;\n  __top_RamAHB32 = 0x2007c000 + 0x8000;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/ \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data)) ;\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2)) ;\n        LONG(  SIZEOF(.data_RAM2));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        \/* End C++ *\/\n    } > MFlash512\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this.\n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash512\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash512\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n        *(.data.$RAM2*)\n        *(.data.$RamAHB32*)\n       . = ALIGN(4) ;\n    } > RamAHB_USB AT>MFlash512\n    \n    \/* MAIN DATA SECTION *\/\n\n    .uninit_RESERVED(NOLOAD) : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n    } > RamLoc32\n\n    .data : ALIGN(4)\n    {\n        FILL(0xff)\n        _data = .;\n        *(vtable)\n        *(.data*)\n        . = ALIGN(4) ;\n        _edata = .;\n    } > RamLoc32 AT>MFlash512\n\n    \n    .bss_RAM2(NOLOAD) : ALIGN(4)\n    {\n        *(.bss.$RAM2*)\n        *(.bss.$RamAHB32*)\n        *(AHBSRAM0)\n       . = ALIGN(4) ;\n    } > RamAHB_USB\n\n    .bss_RAM3(NOLOAD) : ALIGN(4)\n    {\n        *(AHBSRAM1)\n       . = ALIGN(4) ;\n    } > RamAHB_Eth\n    \/* MAIN BSS SECTION *\/\n    .bss(NOLOAD) : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > RamLoc32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_RamLoc32 - 0);\n}\n","old_contents":"\/* mbed - LPC1768 linker script\n * Based linker script generated by Code Red Technologies Red Suite 4.1\n *\/\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 \/* 512k *\/\n  RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 \/* 32k *\/\n  RamAHB_USB (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x4000 \/* 16k *\/\n  RamAHB_Eth (rwx) : ORIGIN = 0x20080000, LENGTH = 0x4000 \/* 16k *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash512 = 0x0 + 0x80000;\n  __top_RamLoc32 = 0x10000000 + 0x8000;\n  __top_RamAHB32 = 0x2007c000 + 0x8000;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/ \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data)) ;\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2)) ;\n        LONG(  SIZEOF(.data_RAM2));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        \/* End C++ *\/\n    } > MFlash512\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this.\n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash512\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash512\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n        *(.data.$RAM2*)\n        *(.data.$RamAHB32*)\n       . = ALIGN(4) ;\n    } > RamAHB_USB AT>MFlash512\n    \n    \/* MAIN DATA SECTION *\/\n\n    .uninit_RESERVED(NOLOAD) : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n    } > RamLoc32\n\n    .data : ALIGN(4)\n    {\n        FILL(0xff)\n        _data = .;\n        *(vtable)\n        *(.data*)\n        . = ALIGN(4) ;\n        _edata = .;\n    } > RamLoc32 AT>MFlash512\n\n    \n    .bss_RAM2(NOLOAD) : ALIGN(4)\n    {\n        *(.bss.$RAM2*)\n        *(.bss.$RamAHB32*)\n        *(AHBSRAM0)\n       . = ALIGN(4) ;\n    } > RamAHB_USB\n\n    .bss_RAM3(NOLOAD) : ALIGN(4)\n    {\n        *(AHBSRAM1)\n       . = ALIGN(4) ;\n    } > RamAHB_Eth\n    \/* MAIN BSS SECTION *\/\n    .bss(NOLOAD) : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > RamLoc32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_RamLoc32 - 0);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"fa856597048d93bb25ba014c2f9926cd805b7db4","subject":"\u30ea\u30bb\u30c3\u30c8\u6642\u3001\u30b9\u30bf\u30c3\u30af\u30a2\u30c9\u30ec\u30b9\u306e\u4fee\u6b63","message":"\u30ea\u30bb\u30c3\u30c8\u6642\u3001\u30b9\u30bf\u30c3\u30af\u30a2\u30c9\u30ec\u30b9\u306e\u4fee\u6b63\n","repos":"hirakuni45\/R8C,hirakuni45\/R8C,hirakuni45\/R8C","old_file":"M120AN\/m120an.ld","new_file":"M120AN\/m120an.ld","new_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w) : ORIGIN = 0x0300, LENGTH = 0x0480\n\tROM (r) : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x07E0-1;\n\t\t_isp_init = 0x0800-1;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vec : {\n    *(.vec)\n  } > VEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w) : ORIGIN = 0x0300, LENGTH = 0x0480\n\tROM (r) : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x07E0;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vec : {\n    *(.vec)\n  } > VEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"960e97834fab1ec9b5c764087f5e5972fb81ba2a","subject":"x86: linker: Maintain 4K alignment for application memory.","message":"x86: linker: Maintain 4K alignment for application memory.\n\nWhen MMU is enabled and the SOC we are running doesn't have\nexecute in-place(XIP) the final image will be a monolith which\nsits in RAM. In such situations we need to maintain the alignment\nfor application memory. If not maintained the MMU boot tables\nwill not be configured properly.\n\nSigned-off-by: Adithya Baglody <06b44f6fa9a97a2b955c2d2cd070279967447860@intel.com>\n","repos":"zephyriot\/zephyr,kraj\/zephyr,mbolivar\/zephyr,finikorg\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,mbolivar\/zephyr,ldts\/zephyr,explora26\/zephyr,mbolivar\/zephyr,GiulianoFranchetto\/zephyr,zephyriot\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,explora26\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,nashif\/zephyr,Vudentz\/zephyr,explora26\/zephyr,ldts\/zephyr,Vudentz\/zephyr,explora26\/zephyr,ldts\/zephyr,kraj\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,kraj\/zephyr,mbolivar\/zephyr,nashif\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,mbolivar\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,galak\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,punitvara\/zephyr,zephyriot\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,punitvara\/zephyr,ldts\/zephyr,galak\/zephyr,kraj\/zephyr,zephyriot\/zephyr,kraj\/zephyr","old_file":"include\/arch\/x86\/linker.ld","new_file":"include\/arch\/x86\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n#ifdef CONFIG_JAILHOUSE\n\t\/* 16-bit sections *\/\n\t. = PHYS_RAM_ADDR;\n\n\tSECTION_PROLOGUE(boot, (OPTIONAL),)\n\t{\n\t*(.boot)\n\t. = ALIGN(16);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\t. = ALIGN(8);\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#ifndef CONFIG_JAILHOUSE\n\t_image_text_start = PHYS_LOAD_ADDR;\n#else\n\t_image_text_start = .;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMMU_PAGE_ALIGN\n#ifdef CONFIG_XIP\n\t\/* Kernel ROM extends to the end of flash. Need to do this to program\n\t * the MMU\n\t *\/\n\t_image_rom_end = _image_rom_start + KB(CONFIG_ROM_SIZE);\n#else\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t_image_rom_end = .;\n#endif\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n#ifndef CONFIG_XIP\n\t\tMMU_PAGE_ALIGN\n#endif\n\t\t_image_ram_start = .;\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t\tMMU_PAGE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * Without Jailhouse, we get the page alignment here for free by\n\t * definition of the beginning of the \"RAMable\" region on the board\n\t * configurations. With Jailhouse, everything falls in RAM and we\n\t * try to glue sections in sequence, thus we have to realign here so\n\t * that gen_mmu.py does not complain.\n\t *\/\n#ifdef CONFIG_JAILHOUSE\n\tMMU_PAGE_ALIGN\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n\n#ifdef CONFIG_X86_MMU\n\t\/* Can't really predict the size of this section. Anything after this\n\t * should not be affected if addresses change between builds (currently\n\t * just the gperf tables which is fine).\n\t *\n\t * However, __mmu_tables_start *must* remain stable between builds,\n\t * we can't have anything shifting the memory map beforehand.\n\t *\/\n\tSECTION_DATA_PROLOGUE(mmu_tables, (OPTIONAL),)\n\t{\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#include <linker\/kobject.ld>\n\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu_x86.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n#ifdef CONFIG_JAILHOUSE\n\t\/* 16-bit sections *\/\n\t. = PHYS_RAM_ADDR;\n\n\tSECTION_PROLOGUE(boot, (OPTIONAL),)\n\t{\n\t*(.boot)\n\t. = ALIGN(16);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\t. = ALIGN(8);\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#ifndef CONFIG_JAILHOUSE\n\t_image_text_start = PHYS_LOAD_ADDR;\n#else\n\t_image_text_start = .;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMMU_PAGE_ALIGN\n#ifdef CONFIG_XIP\n\t\/* Kernel ROM extends to the end of flash. Need to do this to program\n\t * the MMU\n\t *\/\n\t_image_rom_end = _image_rom_start + KB(CONFIG_ROM_SIZE);\n#else\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t_image_rom_end = .;\n#endif\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t_image_ram_start = .;\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t\tMMU_PAGE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * Without Jailhouse, we get the page alignment here for free by\n\t * definition of the beginning of the \"RAMable\" region on the board\n\t * configurations. With Jailhouse, everything falls in RAM and we\n\t * try to glue sections in sequence, thus we have to realign here so\n\t * that gen_mmu.py does not complain.\n\t *\/\n#ifdef CONFIG_JAILHOUSE\n\tMMU_PAGE_ALIGN\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n\n#ifdef CONFIG_X86_MMU\n\t\/* Can't really predict the size of this section. Anything after this\n\t * should not be affected if addresses change between builds (currently\n\t * just the gperf tables which is fine).\n\t *\n\t * However, __mmu_tables_start *must* remain stable between builds,\n\t * we can't have anything shifting the memory map beforehand.\n\t *\/\n\tSECTION_DATA_PROLOGUE(mmu_tables, (OPTIONAL),)\n\t{\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#include <linker\/kobject.ld>\n\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu_x86.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c8d7dcc8976e987854cd38a1dbb134a3fed01d90","subject":"linker: rename the section for emulators","message":"linker: rename the section for emulators\n\nThe linker section for emulators (emulation drivers) is\nincorrectly named \"log_const_sections\" possibly due to\nsimply copy-and-paste error. This section has nothing to\ndo with logging, so rename the emulators section.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr","old_file":"include\/linker\/common-rom.ld","new_file":"include\/linker\/common-rom.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\tSECTION_PROLOGUE(initlevel,,)\n\t{\n\t\t\/*\n\t\t * link in initialization objects for all objects that are\n\t\t * automatically initialized by the kernel; the objects are\n\t\t * sorted in the order they will be initialized (i.e. ordered\n\t\t * by level, sorted by priority within a level)\n\t\t *\/\n\t\t__init_start = .;\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_1)\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_2)\n\t\tCREATE_OBJ_LEVEL(init, POST_KERNEL)\n\t\tCREATE_OBJ_LEVEL(init, APPLICATION)\n\t\tCREATE_OBJ_LEVEL(init, SMP)\n\t\t__init_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && !defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_NAME)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_PROLOGUE(initlevel_error,,)\n\t{\n\t\tKEEP(*(SORT(.init_[_A-Z0-9]*)))\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on word\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n#ifdef CONFIG_64BIT\n\t\t. = ALIGN(8);\n\t\t__CTOR_LIST__ = .;\n\t\tQUAD((__CTOR_END__ - __CTOR_LIST__) \/ 8 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tQUAD(0)\n\t\t__CTOR_END__ = .;\n#else\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array,,)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n#ifdef CONFIG_USERSPACE\n\t\/* Build-time assignment of permissions to kernel objects to\n\t * threads declared with K_THREAD_DEFINE()\n\t *\/\n\tZ_ITERABLE_SECTION_ROM(z_object_assignment, 4)\n#endif\n\n\tSECTION_DATA_PROLOGUE(app_shmem_regions,,)\n\t{\n\t\t__app_shmem_regions_start = .;\n\t\tKEEP(*(SORT(.app_regions.*)));\n\t\t__app_shmem_regions_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SOCKETS)\n\tZ_ITERABLE_SECTION_ROM(net_socket_register, 4)\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n\tZ_ITERABLE_SECTION_ROM(ppp_protocol_handler, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_fixed_chan, 4)\n\n#if defined(CONFIG_BT_BREDR)\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_br_fixed_chan, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_gatt_service_static, 4)\n\n#if defined(CONFIG_BT_MESH)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_subnet_cb, 4)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_app_key_cb, 4)\n\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_hb_cb, 4)\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_friend_cb, 4)\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_lpn_cb, 4)\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n\tZ_ITERABLE_SECTION_ROM(ec_host_cmd_handler, 4)\n#endif\n\n#if defined(CONFIG_SETTINGS)\n\tZ_ITERABLE_SECTION_ROM(settings_handler_static, 4)\n#endif\n\n#if defined(CONFIG_EMUL)\n\tSECTION_DATA_PROLOGUE(emulators_section,,)\n\t{\n\t\t__emul_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".emulators\")));\n\t\t__emul_list_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_EMUL *\/\n\n#if defined(CONFIG_DNS_SD)\n\tZ_ITERABLE_SECTION_ROM(dns_sd_rec, 4)\n#endif\n\n#if defined(CONFIG_PCIE)\n\tSECTION_DATA_PROLOGUE(irq_alloc,,)\n\t{\n\t\t__irq_alloc_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._irq_alloc*\")));\n\t\t__irq_alloc_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_PCIE *\/\n\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__log_const_start = .;\n\t\tKEEP(*(SORT(.log_const_*)));\n\t\t__log_const_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_backends_sections,,)\n\t{\n\t\t__log_backends_start = .;\n\t\tKEEP(*(\"._log_backend.*\"));\n\t\t__log_backends_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(shell, 4)\n\n\tSECTION_DATA_PROLOGUE(shell_root_cmds_sections,,)\n\t{\n\t\t__shell_root_cmds_start = .;\n\t\tKEEP(*(SORT(.shell_root_cmd_*)));\n\t\t__shell_root_cmds_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(font_entry_sections,,)\n\t{\n\t\t__font_entry_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._cfb_font.*\")))\n\t\t__font_entry_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(tracing_backend, 4)\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\tSECTION_PROLOGUE(initlevel,,)\n\t{\n\t\t\/*\n\t\t * link in initialization objects for all objects that are\n\t\t * automatically initialized by the kernel; the objects are\n\t\t * sorted in the order they will be initialized (i.e. ordered\n\t\t * by level, sorted by priority within a level)\n\t\t *\/\n\t\t__init_start = .;\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_1)\n\t\tCREATE_OBJ_LEVEL(init, PRE_KERNEL_2)\n\t\tCREATE_OBJ_LEVEL(init, POST_KERNEL)\n\t\tCREATE_OBJ_LEVEL(init, APPLICATION)\n\t\tCREATE_OBJ_LEVEL(init, SMP)\n\t\t__init_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && !defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_NAME)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_PROLOGUE(initlevel_error,,)\n\t{\n\t\tKEEP(*(SORT(.init_[_A-Z0-9]*)))\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,)\n\t{\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below,\n\t\t * hence symbol __CTOR_LIST__ must be aligned on word\n\t\t * boundary.  To align with the C++ standard, the first elment\n\t\t * of the array contains the number of actual constructors. The\n\t\t * last element is NULL.\n\t\t *\/\n#ifdef CONFIG_64BIT\n\t\t. = ALIGN(8);\n\t\t__CTOR_LIST__ = .;\n\t\tQUAD((__CTOR_END__ - __CTOR_LIST__) \/ 8 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tQUAD(0)\n\t\t__CTOR_END__ = .;\n#else\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array,,)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n#ifdef CONFIG_USERSPACE\n\t\/* Build-time assignment of permissions to kernel objects to\n\t * threads declared with K_THREAD_DEFINE()\n\t *\/\n\tZ_ITERABLE_SECTION_ROM(z_object_assignment, 4)\n#endif\n\n\tSECTION_DATA_PROLOGUE(app_shmem_regions,,)\n\t{\n\t\t__app_shmem_regions_start = .;\n\t\tKEEP(*(SORT(.app_regions.*)));\n\t\t__app_shmem_regions_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SOCKETS)\n\tZ_ITERABLE_SECTION_ROM(net_socket_register, 4)\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n\tZ_ITERABLE_SECTION_ROM(ppp_protocol_handler, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_fixed_chan, 4)\n\n#if defined(CONFIG_BT_BREDR)\n\tZ_ITERABLE_SECTION_ROM(bt_l2cap_br_fixed_chan, 4)\n#endif\n\n\tZ_ITERABLE_SECTION_ROM(bt_gatt_service_static, 4)\n\n#if defined(CONFIG_BT_MESH)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_subnet_cb, 4)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_app_key_cb, 4)\n\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_hb_cb, 4)\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_friend_cb, 4)\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n\tZ_ITERABLE_SECTION_ROM(bt_mesh_lpn_cb, 4)\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n\tZ_ITERABLE_SECTION_ROM(ec_host_cmd_handler, 4)\n#endif\n\n#if defined(CONFIG_SETTINGS)\n\tZ_ITERABLE_SECTION_ROM(settings_handler_static, 4)\n#endif\n\n#if defined(CONFIG_EMUL)\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__emul_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".emulators\")));\n\t\t__emul_list_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_EMUL *\/\n\n#if defined(CONFIG_DNS_SD)\n\tZ_ITERABLE_SECTION_ROM(dns_sd_rec, 4)\n#endif\n\n#if defined(CONFIG_PCIE)\n\tSECTION_DATA_PROLOGUE(irq_alloc,,)\n\t{\n\t\t__irq_alloc_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._irq_alloc*\")));\n\t\t__irq_alloc_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_PCIE *\/\n\n\tSECTION_DATA_PROLOGUE(log_const_sections,,)\n\t{\n\t\t__log_const_start = .;\n\t\tKEEP(*(SORT(.log_const_*)));\n\t\t__log_const_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_backends_sections,,)\n\t{\n\t\t__log_backends_start = .;\n\t\tKEEP(*(\"._log_backend.*\"));\n\t\t__log_backends_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(shell, 4)\n\n\tSECTION_DATA_PROLOGUE(shell_root_cmds_sections,,)\n\t{\n\t\t__shell_root_cmds_start = .;\n\t\tKEEP(*(SORT(.shell_root_cmd_*)));\n\t\t__shell_root_cmds_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(font_entry_sections,,)\n\t{\n\t\t__font_entry_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._cfb_font.*\")))\n\t\t__font_entry_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_ROM(tracing_backend, 4)\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"56d4e835b97ec94e4f865c1b8274fc3fe84b4e49","subject":"linker: esp32: remove libhal dependency","message":"linker: esp32: remove libhal dependency\n\nlibhal.a is not used and can be removed from linker\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\n\/* Global symbols required for espressif hal build *\/\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\nPROVIDE ( phy_get_romfuncs = 0x40004100 );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );\nPROVIDE ( g_rom_flashchip = 0x3ffae270 );\nPROVIDE ( SPI0 = 0x3ff43000 );\nPROVIDE ( SPI1 = 0x3ff42fff );\nPROVIDE ( SPI2 = 0x3ff64fff );\nPROVIDE ( SPI3 = 0x3ff65fff );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( esp32_rom_ets_printf = ets_printf );\nPROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );\nPROVIDE ( TIMERG0 = 0x3ff5F000 );\nPROVIDE ( TIMERG1 = 0x3ff60000 );\n\n\/* __udivdi3 is exported using assignment, which declares strong symbols *\/\n__udivdi3 = 0x4000cff8;\n__umoddi3 = 0x4000d280;\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *  - Reserve memory region for BT controller library from ROM\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x30000\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n#if defined(CONFIG_NET_SOCKETS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_socket_register);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(settings_handler_static);\n    . = ALIGN(4);\n#endif\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\n\/* Global symbols required for espressif hal build *\/\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\nPROVIDE ( phy_get_romfuncs = 0x40004100 );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );\nPROVIDE ( g_rom_flashchip = 0x3ffae270 );\nPROVIDE ( SPI0 = 0x3ff43000 );\nPROVIDE ( SPI1 = 0x3ff42fff );\nPROVIDE ( SPI2 = 0x3ff64fff );\nPROVIDE ( SPI3 = 0x3ff65fff );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( esp32_rom_ets_printf = ets_printf );\nPROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );\nPROVIDE ( TIMERG0 = 0x3ff5F000 );\nPROVIDE ( TIMERG1 = 0x3ff60000 );\n\n\/* __udivdi3 is exported using assignment, which declares strong symbols *\/\n__udivdi3 = 0x4000cff8;\n__umoddi3 = 0x4000d280;\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *  - Reserve memory region for BT controller library from ROM\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x30000\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n#if defined(CONFIG_NET_SOCKETS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_socket_register);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(settings_handler_static);\n    . = ALIGN(4);\n#endif\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b7f27e4749fc81ceee01c6d9a70269bbcb2cbba6","subject":"Exclude example files.","message":"Exclude example files.\n","repos":"jinq0123\/grpc-lua,jinq0123\/grpc-lua,jinq0123\/grpc-lua","old_file":"doc\/ldoc\/config.ld","new_file":"doc\/ldoc\/config.ld","new_contents":"project='grpc-lua'\ntitle='grpc-lua documentation'\ndescription='The Lua gRPC binding'\nformat='discount'\nbacktick_references=false\nfile={\n    '..\/..\/src',\n    exclude = {\n    }\n}\ndir='html'\n-- readme='doc.md'\nstyle='!pale'\nexamples = {\n    '..\/..\/examples',\n    exclude = {\n        '..\/..\/examples\/route_guide\/inspect.lua-3.1.0',\n        '..\/..\/examples\/route_guide\/json.lua-0.1.0',\n    }\n}\nsort_modules=true\nconvert_opt=true\n","old_contents":"project='grpc-lua'\ntitle='grpc-lua documentation'\ndescription='The Lua gRPC binding'\nformat='discount'\nbacktick_references=false\nfile={\n    '..\/..\/src',\n    exclude = {\n    }\n}\ndir='html'\n-- readme='doc.md'\nstyle='!pale'\nexamples = {\n    '..\/..\/examples',\n}\nsort_modules=true\nconvert_opt=true\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c56572b7e5a90d69d544b748ebdba31be1f86ed0","subject":"use discount","message":"use discount\n","repos":"bakins\/stardust,bakins\/stardust,bakins\/stardust","old_file":"config.ld","new_file":"config.ld","new_contents":"file = 'lib'\nexamples = { 'examples' }\ndir = 'docs'\nreadme = \"README.md\"\nformat = 'discount'","old_contents":"file = 'lib'\nexamples = { 'examples' }\ndir = 'docs'\nreadme = \"README.md\"\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b88bb2c1eb5e033b664f2641bc26403947d79413","subject":"linker: make sram origin symbol","message":"linker: make sram origin symbol\n\nThis allows elf2tab to determine what the start of RAM address is.\n","repos":"tock\/libtock-rs","old_file":"layout_generic.ld","new_file":"layout_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * Currently, due to incomplete ROPI-RWPI support in rustc (see\n * https:\/\/github.com\/tock\/libtock-rs\/issues\/28), this layout implements static\n * linking. An application init script must define the FLASH and SRAM address\n * ranges as well as MPU_MIN_ALIGN before including this layout file.\n *\n * Here is a an example application linker script to get started:\n *     MEMORY {\n *         \/* FLASH memory region must start immediately *after* the Tock\n *          * Binary Format headers, which means you need to offset the\n *          * beginning of FLASH memory region relative to where the\n *          * application is loaded.\n *         FLASH (rx) : ORIGIN = 0x10030, LENGTH = 0x0FFD0\n *         SRAM (RWX) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     STACK_SIZE = 2048;\n *     MPU_MIN_ALIGN = 8K;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n        \/* Pad the header out to a multiple of 32 bytes so there is not a gap\n         * between the header and subsequent .data section. It's unclear why,\n         * but LLD is aligning sections to a multiple of 32 bytes. *\/\n        . = ALIGN(32);\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _etext = .;\n    } > FLASH =0xFF\n\n    \/* Application stack *\/\n    .stack (NOLOAD) :\n    {\n        \/* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to\n         * mark the first address in the SRAM memory. Since ELF files do\n         * not really need to specify this address as they only care about\n         * loading into flash, we need to manually mark this address for\n         * elf2tab. elf2tab will use it to add a fixed address header in the\n         * TBF header if needed.\n         *\/\n        _SRAM_ORIGIN = .;\n\n        . = . + STACK_SIZE;\n\n\t_stack_top_unaligned = .;\n        . = ALIGN(8);\n\t_stack_top_aligned = .;\n    } > SRAM\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data : AT (_etext)\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss* .sbss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT((_stack_top_aligned - _stack_top_unaligned) == 0, \"\nSTACK_SIZE must be 8 byte multiple\")\n","old_contents":"\/* Userland Generic Layout\n *\n * Currently, due to incomplete ROPI-RWPI support in rustc (see\n * https:\/\/github.com\/tock\/libtock-rs\/issues\/28), this layout implements static\n * linking. An application init script must define the FLASH and SRAM address\n * ranges as well as MPU_MIN_ALIGN before including this layout file.\n *\n * Here is a an example application linker script to get started:\n *     MEMORY {\n *         \/* FLASH memory region must start immediately *after* the Tock\n *          * Binary Format headers, which means you need to offset the\n *          * beginning of FLASH memory region relative to where the\n *          * application is loaded.\n *         FLASH (rx) : ORIGIN = 0x10030, LENGTH = 0x0FFD0\n *         SRAM (RWX) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     STACK_SIZE = 2048;\n *     MPU_MIN_ALIGN = 8K;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n        \/* Pad the header out to a multiple of 32 bytes so there is not a gap\n         * between the header and subsequent .data section. It's unclear why,\n         * but LLD is aligning sections to a multiple of 32 bytes. *\/\n        . = ALIGN(32);\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _etext = .;\n    } > FLASH =0xFF\n\n    \/* Application stack *\/\n    .stack (NOLOAD) :\n    {\n        . = . + STACK_SIZE;\n\n\t_stack_top_unaligned = .;\n        . = ALIGN(8);\n\t_stack_top_aligned = .;\n    } > SRAM\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data : AT (_etext)\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss* .sbss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT((_stack_top_aligned - _stack_top_unaligned) == 0, \"\nSTACK_SIZE must be 8 byte multiple\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7f324b16465db2c9486f0a1c18710cf2444b53b1","subject":"Include provenance in k20::iomem","message":"Include provenance in k20::iomem\n","repos":"placrosse\/zinc,farcaller\/zinc,richo\/zinc,ryankurte\/zinc,troplin\/zinc,darayus\/zinc,placrosse\/zinc,farcaller\/zinc,mcoffin\/zinc,richo\/zinc,mcoffin\/zinc,posborne\/zinc,ntwyman\/zinc,troplin\/zinc,hugwijst\/zinc,phil-opp\/zinc,phil-opp\/zinc,richo\/zinc,gapry\/zinc,phil-opp\/zinc,mcoffin\/zinc,0xc0170\/zinc,posborne\/zinc,richo\/zinc,darayus\/zinc,ntwyman\/zinc,posborne\/zinc,aethaniel\/zinc,placrosse\/zinc,0xc0170\/zinc,farcaller\/zinc,tempbottle\/zinc,hugwijst\/zinc,posborne\/zinc,hackndev\/zinc,farcaller\/zinc,mcoffin\/zinc,dirvine\/zinc,ntwyman\/zinc,gapry\/zinc,phil-opp\/zinc,dirvine\/zinc,dirvine\/zinc,dirvine\/zinc,troplin\/zinc,placrosse\/zinc,richo\/zinc,mcoffin\/zinc,troplin\/zinc,hackndev\/zinc,dirvine\/zinc,aethaniel\/zinc,tempbottle\/zinc,phil-opp\/zinc,ryankurte\/zinc,ryankurte\/zinc,farcaller\/zinc,ryankurte\/zinc,troplin\/zinc,hackndev\/zinc,ntwyman\/zinc,tempbottle\/zinc,placrosse\/zinc,tempbottle\/zinc,hackndev\/zinc,hackndev\/zinc,tempbottle\/zinc,posborne\/zinc,ryankurte\/zinc,ntwyman\/zinc","old_file":"src\/zinc\/hal\/k20\/iomem.ld","new_file":"src\/zinc\/hal\/k20\/iomem.ld","new_contents":"INCLUDE .\/src\/zinc\/hal\/cortex_m3\/armmem.ld\n\nPROVIDE(isr_dma_0           = isr_default_fault);\nPROVIDE(isr_dma_1           = isr_default_fault);\nPROVIDE(isr_dma_2           = isr_default_fault);\nPROVIDE(isr_dma_3           = isr_default_fault);\nPROVIDE(isr_dma_4           = isr_default_fault);\nPROVIDE(isr_dma_5           = isr_default_fault);\nPROVIDE(isr_dma_6           = isr_default_fault);\nPROVIDE(isr_dma_7           = isr_default_fault);\nPROVIDE(isr_dma_8           = isr_default_fault);\nPROVIDE(isr_dma_9           = isr_default_fault);\nPROVIDE(isr_dma_10          = isr_default_fault);\nPROVIDE(isr_dma_11          = isr_default_fault);\nPROVIDE(isr_dma_12          = isr_default_fault);\nPROVIDE(isr_dma_13          = isr_default_fault);\nPROVIDE(isr_dma_14          = isr_default_fault);\nPROVIDE(isr_dma_15          = isr_default_fault);\nPROVIDE(isr_dma_err         = isr_default_fault);\nPROVIDE(isr_flash_complete  = isr_default_fault);\nPROVIDE(isr_flash_collision = isr_default_fault);\nPROVIDE(isr_low_volt        = isr_default_fault);\nPROVIDE(isr_llwu            = isr_default_fault);\nPROVIDE(isr_wdt             = isr_default_fault);\nPROVIDE(isr_i2c_0           = isr_default_fault);\nPROVIDE(isr_i2c_1           = isr_default_fault);\nPROVIDE(isr_spi_0           = isr_default_fault);\nPROVIDE(isr_spi_1           = isr_default_fault);\nPROVIDE(isr_can_0_msg       = isr_default_fault);\nPROVIDE(isr_can_0_bus       = isr_default_fault);\nPROVIDE(isr_can_0_err       = isr_default_fault);\nPROVIDE(isr_can_0_tx        = isr_default_fault);\nPROVIDE(isr_can_0_rx        = isr_default_fault);\nPROVIDE(isr_can_0_wake      = isr_default_fault);\nPROVIDE(isr_i2s_0_tx        = isr_default_fault);\nPROVIDE(isr_i2s_0_rx        = isr_default_fault);\nPROVIDE(isr_uart_0_lon      = isr_default_fault);\nPROVIDE(isr_uart_0_stat     = isr_default_fault);\nPROVIDE(isr_uart_0_err      = isr_default_fault);\nPROVIDE(isr_uart_1_stat     = isr_default_fault);\nPROVIDE(isr_uart_1_err      = isr_default_fault);\nPROVIDE(isr_uart_2_stat     = isr_default_fault);\nPROVIDE(isr_uart_2_err      = isr_default_fault);\nPROVIDE(isr_adc_0           = isr_default_fault);\nPROVIDE(isr_adc_1           = isr_default_fault);\nPROVIDE(isr_cmp_0           = isr_default_fault);\nPROVIDE(isr_cmp_1           = isr_default_fault);\nPROVIDE(isr_cmp_2           = isr_default_fault);\nPROVIDE(isr_ftm_0           = isr_default_fault);\nPROVIDE(isr_ftm_1           = isr_default_fault);\nPROVIDE(isr_ftm_2           = isr_default_fault);\nPROVIDE(ist_cmt             = isr_default_fault);\nPROVIDE(isr_rtc_alarm       = isr_default_fault);\nPROVIDE(isr_rtc_tick        = isr_default_fault);\nPROVIDE(isr_pit_0           = isr_default_fault);\nPROVIDE(isr_pit_1           = isr_default_fault);\nPROVIDE(isr_pit_2           = isr_default_fault);\nPROVIDE(isr_pit_3           = isr_default_fault);\nPROVIDE(isr_pdb             = isr_default_fault);\nPROVIDE(isr_usb             = isr_default_fault);\nPROVIDE(isr_usb_dcd         = isr_default_fault);\nPROVIDE(isr_dac_0           = isr_default_fault);\nPROVIDE(isr_tsi             = isr_default_fault);\nPROVIDE(isr_mcg             = isr_default_fault);\nPROVIDE(isr_lptimer         = isr_default_fault);\nPROVIDE(isr_port_a          = isr_default_fault);\nPROVIDE(isr_port_b          = isr_default_fault);\nPROVIDE(isr_port_c          = isr_default_fault);\nPROVIDE(isr_port_d          = isr_default_fault);\nPROVIDE(isr_port_e          = isr_default_fault);\nPROVIDE(isr_soft            = isr_default_fault);\n\n# This originated from the Freescale K20 Sub-Family Reference Manual\n# Document number K20P48M50SF0RM, Rev. 2\n\nk20_iomem_PERIPH0   = 0x40000000;\n\nk20_iomem_CROSSBAR  = 0x40004000;\n\nk20_iomem_DMACON    = 0x40008000;\nk20_iomem_DMATCD    = 0x40009000;\n\nk20_iomem_FLASHCON  = 0x4001F000;\nk20_iomem_FLASH     = 0x40020000;\nk20_iomem_DMAMUX0   = 0x40021000;\n\nk20_iomem_CAN0      = 0x40024000;\n\nk20_iomem_SPI0      = 0x4002C000;\nk20_iomem_SPI1      = 0x4002D000;\nk20_iomem_I2S0      = 0x4002F000;\n\nk20_iomem_CRC       = 0x40032000;\n\nk20_iomem_USBDCD    = 0x40035000;\nk20_iomem_PDB       = 0x40036000;\nk20_iomem_PIT       = 0x40037000;\nk20_iomem_FTM0      = 0x40038000;\nk20_iomem_FTM1      = 0x40039000;\n\nk20_iomem_ADC0      = 0x4003B000;\n\nk20_iomem_RTC       = 0x4003D000;\nk20_iomem_VBAT      = 0x4003E000;\n\nk20_iomem_LPTMR     = 0x40040000;\nk20_iomem_SYSREG    = 0x40041000;\n\nk20_iomem_TSI       = 0x40045000;\n\nk20_iomem_SIM       = 0x40047000;\nk20_iomem_PORTA     = 0x40049000;\nk20_iomem_PORTB     = 0x4004A000;\nk20_iomem_PORTC     = 0x4004B000;\nk20_iomem_PORTD     = 0x4004C000;\nk20_iomem_PORTE     = 0x4004D000;\n\nk20_iomem_WDINT     = 0x40052000;\n\nk20_iomem_WDEXT     = 0x40061000;\nk20_iomem_CMT       = 0x40062000;\n\nk20_iomem_MCG       = 0x40064000;\nk20_iomem_OSC       = 0x40065000;\nk20_iomem_I2C0      = 0x40066000;\nk20_iomem_I2C1      = 0x40067000;\n\nk20_iomem_UART0     = 0x4006A000;\nk20_iomem_UART1     = 0x4006B000;\nk20_iomem_UART2     = 0x4006C000;\n\nk20_iomem_USB       = 0x40072000;\nk20_iomem_CMP       = 0x40073000;\nk20_iomem_VREF      = 0x40074000;\n\nk20_iomem_LLWU      = 0x4007C000;\nk20_iomem_PMC       = 0x4007D000;\nk20_iomem_SMC       = 0x4007E000;\nk20_iomem_RCM       = 0x4007F000;\n\n\nk20_iomem_PERIPH1   = 0x40080000;\n\nk20_iomem_FTM2      = 0x400B8000;\n\nk20_iomem_ADC1      = 0x400BB000;\n\nk20_iomem_DAC0      = 0x400CC000;\n\nk20_iomem_GPIOA     = 0x400ff000;\nk20_iomem_GPIOB     = 0x400ff040;\nk20_iomem_GPIOC     = 0x400ff080;\nk20_iomem_GPIOD     = 0x400ff0C0;\nk20_iomem_GPIOE     = 0x400ff100;\n\nk20_iomem_WDOG      = 0x40052000;\n","old_contents":"INCLUDE .\/src\/zinc\/hal\/cortex_m3\/armmem.ld\n\nPROVIDE(isr_dma_0           = isr_default_fault);\nPROVIDE(isr_dma_1           = isr_default_fault);\nPROVIDE(isr_dma_2           = isr_default_fault);\nPROVIDE(isr_dma_3           = isr_default_fault);\nPROVIDE(isr_dma_4           = isr_default_fault);\nPROVIDE(isr_dma_5           = isr_default_fault);\nPROVIDE(isr_dma_6           = isr_default_fault);\nPROVIDE(isr_dma_7           = isr_default_fault);\nPROVIDE(isr_dma_8           = isr_default_fault);\nPROVIDE(isr_dma_9           = isr_default_fault);\nPROVIDE(isr_dma_10          = isr_default_fault);\nPROVIDE(isr_dma_11          = isr_default_fault);\nPROVIDE(isr_dma_12          = isr_default_fault);\nPROVIDE(isr_dma_13          = isr_default_fault);\nPROVIDE(isr_dma_14          = isr_default_fault);\nPROVIDE(isr_dma_15          = isr_default_fault);\nPROVIDE(isr_dma_err         = isr_default_fault);\nPROVIDE(isr_flash_complete  = isr_default_fault);\nPROVIDE(isr_flash_collision = isr_default_fault);\nPROVIDE(isr_low_volt        = isr_default_fault);\nPROVIDE(isr_llwu            = isr_default_fault);\nPROVIDE(isr_wdt             = isr_default_fault);\nPROVIDE(isr_i2c_0           = isr_default_fault);\nPROVIDE(isr_i2c_1           = isr_default_fault);\nPROVIDE(isr_spi_0           = isr_default_fault);\nPROVIDE(isr_spi_1           = isr_default_fault);\nPROVIDE(isr_can_0_msg       = isr_default_fault);\nPROVIDE(isr_can_0_bus       = isr_default_fault);\nPROVIDE(isr_can_0_err       = isr_default_fault);\nPROVIDE(isr_can_0_tx        = isr_default_fault);\nPROVIDE(isr_can_0_rx        = isr_default_fault);\nPROVIDE(isr_can_0_wake      = isr_default_fault);\nPROVIDE(isr_i2s_0_tx        = isr_default_fault);\nPROVIDE(isr_i2s_0_rx        = isr_default_fault);\nPROVIDE(isr_uart_0_lon      = isr_default_fault);\nPROVIDE(isr_uart_0_stat     = isr_default_fault);\nPROVIDE(isr_uart_0_err      = isr_default_fault);\nPROVIDE(isr_uart_1_stat     = isr_default_fault);\nPROVIDE(isr_uart_1_err      = isr_default_fault);\nPROVIDE(isr_uart_2_stat     = isr_default_fault);\nPROVIDE(isr_uart_2_err      = isr_default_fault);\nPROVIDE(isr_adc_0           = isr_default_fault);\nPROVIDE(isr_adc_1           = isr_default_fault);\nPROVIDE(isr_cmp_0           = isr_default_fault);\nPROVIDE(isr_cmp_1           = isr_default_fault);\nPROVIDE(isr_cmp_2           = isr_default_fault);\nPROVIDE(isr_ftm_0           = isr_default_fault);\nPROVIDE(isr_ftm_1           = isr_default_fault);\nPROVIDE(isr_ftm_2           = isr_default_fault);\nPROVIDE(ist_cmt             = isr_default_fault);\nPROVIDE(isr_rtc_alarm       = isr_default_fault);\nPROVIDE(isr_rtc_tick        = isr_default_fault);\nPROVIDE(isr_pit_0           = isr_default_fault);\nPROVIDE(isr_pit_1           = isr_default_fault);\nPROVIDE(isr_pit_2           = isr_default_fault);\nPROVIDE(isr_pit_3           = isr_default_fault);\nPROVIDE(isr_pdb             = isr_default_fault);\nPROVIDE(isr_usb             = isr_default_fault);\nPROVIDE(isr_usb_dcd         = isr_default_fault);\nPROVIDE(isr_dac_0           = isr_default_fault);\nPROVIDE(isr_tsi             = isr_default_fault);\nPROVIDE(isr_mcg             = isr_default_fault);\nPROVIDE(isr_lptimer         = isr_default_fault);\nPROVIDE(isr_port_a          = isr_default_fault);\nPROVIDE(isr_port_b          = isr_default_fault);\nPROVIDE(isr_port_c          = isr_default_fault);\nPROVIDE(isr_port_d          = isr_default_fault);\nPROVIDE(isr_port_e          = isr_default_fault);\nPROVIDE(isr_soft            = isr_default_fault);\n\nk20_iomem_PERIPH0   = 0x40000000;\n\nk20_iomem_CROSSBAR  = 0x40004000;\n\nk20_iomem_DMACON    = 0x40008000;\nk20_iomem_DMATCD    = 0x40009000;\n\nk20_iomem_FLASHCON  = 0x4001F000;\nk20_iomem_FLASH     = 0x40020000;\nk20_iomem_DMAMUX0   = 0x40021000;\n\nk20_iomem_CAN0      = 0x40024000;\n\nk20_iomem_SPI0      = 0x4002C000;\nk20_iomem_SPI1      = 0x4002D000;\nk20_iomem_I2S0      = 0x4002F000;\n\nk20_iomem_CRC       = 0x40032000;\n\nk20_iomem_USBDCD    = 0x40035000;\nk20_iomem_PDB       = 0x40036000;\nk20_iomem_PIT       = 0x40037000;\nk20_iomem_FTM0      = 0x40038000;\nk20_iomem_FTM1      = 0x40039000;\n\nk20_iomem_ADC0      = 0x4003B000;\n\nk20_iomem_RTC       = 0x4003D000;\nk20_iomem_VBAT      = 0x4003E000;\n\nk20_iomem_LPTMR     = 0x40040000;\nk20_iomem_SYSREG    = 0x40041000;\n\nk20_iomem_TSI       = 0x40045000;\n\nk20_iomem_SIM       = 0x40047000;\nk20_iomem_PORTA     = 0x40049000;\nk20_iomem_PORTB     = 0x4004A000;\nk20_iomem_PORTC     = 0x4004B000;\nk20_iomem_PORTD     = 0x4004C000;\nk20_iomem_PORTE     = 0x4004D000;\n\nk20_iomem_WDINT     = 0x40052000;\n\nk20_iomem_WDEXT     = 0x40061000;\nk20_iomem_CMT       = 0x40062000;\n\nk20_iomem_MCG       = 0x40064000;\nk20_iomem_OSC       = 0x40065000;\nk20_iomem_I2C0      = 0x40066000;\nk20_iomem_I2C1      = 0x40067000;\n\nk20_iomem_UART0     = 0x4006A000;\nk20_iomem_UART1     = 0x4006B000;\nk20_iomem_UART2     = 0x4006C000;\n\nk20_iomem_USB       = 0x40072000;\nk20_iomem_CMP       = 0x40073000;\nk20_iomem_VREF      = 0x40074000;\n\nk20_iomem_LLWU      = 0x4007C000;\nk20_iomem_PMC       = 0x4007D000;\nk20_iomem_SMC       = 0x4007E000;\nk20_iomem_RCM       = 0x4007F000;\n\n\nk20_iomem_PERIPH1   = 0x40080000;\n\nk20_iomem_FTM2      = 0x400B8000;\n\nk20_iomem_ADC1      = 0x400BB000;\n\nk20_iomem_DAC0      = 0x400CC000;\n\nk20_iomem_GPIOA     = 0x400ff000;\nk20_iomem_GPIOB     = 0x400ff040;\nk20_iomem_GPIOC     = 0x400ff080;\nk20_iomem_GPIOD     = 0x400ff0C0;\nk20_iomem_GPIOE     = 0x400ff100;\n\nk20_iomem_WDOG      = 0x40052000;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6ce6dbea64fd311cb6b32ea0e7736de5b65ece0b","subject":".init sections added to the linker script","message":".init sections added to the linker script\n","repos":"akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix","old_file":"linker.ld","new_file":"linker.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\n\nSECTIONS\n{\n    . = 0x00100000;\n    .text ALIGN (0x1000) :\n    {\n    __start_cs_kernel = .;\n        *(.text)\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n    __end_cs_kernel = .;\n    }\n\n    .rodata ALIGN (0x1000) :\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        *(.data)\n    }\n\n    .bss :\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n}\n","old_contents":"ENTRY (loader)\n\nSECTIONS\n{\n    . = 0x00100000;\n\n    .text ALIGN (0x1000) :\n    {\n        *(.text)\n    }\n\n    .rodata ALIGN (0x1000) :\n    {\n        *(.rodata*)\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        *(.data)\n    }\n\n    .bss :\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"956bffbec2b72b4cda353e90f38c4b457191291d","subject":"Fix stack alignment in user programs","message":"Fix stack alignment in user programs\n","repos":"olsner\/os,olsner\/os,olsner\/os,olsner\/os","old_file":"cuser\/linker.ld","new_file":"cuser\/linker.ld","new_contents":"ENTRY(start)\n\nSECTIONS\n{\n\t. = 1M;\n\n\t.text : {\n\t\t\/* GCC expects the stack to be 16-byte aligned. It is 1MB-aligned\n\t\t * already, *but* the alignment that gcc is talking about is *before*\n\t\t * a return address is pushed by a 'call'. So, misalign the stack by\n\t\t * pushing a qword in place of the return address. *\/\n\t\t\/* 0x6a 0x00 = push byte 0 *\/\n\t\tSHORT(0x6a);\n\t\t*(.start);\n\t\t*(.text*);\n\t\t*(.rodata*);\n\t}\n\t\/* 1MB of .text and initialized .data should be enough for anyone. *\/\n\t. = 2M;\n\tPROVIDE(__bss_start = .);\n\t.data : AT( ADDR(.text) + SIZEOF(.text) ) {\n\t\tPROVIDE(__data_lma = LOADADDR(.data));\n\t\tPROVIDE(__data_vma = .);\n\t\t. += SIZEOF(.data);\n\t\t*(.data*);\n\t\tPROVIDE(__data_lma_end = LOADADDR(.data) + SIZEOF(.data));\n\t}\n\t\/* Note that none of these get loaded properly unless the program does it\n\t * by itself.\n\t * 1. Map __bss_start .. __bss_end as read-writeable zero-init memory\n\t * 2. Copy __data_size bytes from __data_lma to __data_vma. \n\t * __data_vma is inside the bss range just allocated. *\/\n\t.bss : {\n\t\t*(.bss*);\n\t}\n\tPROVIDE(__bss_end = ALIGN(4096));\n\tPROVIDE(__data_size = SIZEOF(.data));\n\t.placeholder (NOLOAD) : {\n\t\t*(SORT_BY_ALIGNMENT(.placeholder*));\n\t}\n\t\/DISCARD\/ : {\n\t\t*(.eh_frame);\n\t\t*(.comment);\n\t\t*(.note*);\n\t}\n}\n","old_contents":"ENTRY(start)\n\nSECTIONS\n{\n\t. = 1M;\n\n\t.text : {\n\t\t*(.start);\n\t\t*(.text*);\n\t\t*(.rodata*);\n\t}\n\t\/* 1MB of .text and initialized .data should be enough for anyone. *\/\n\t. = 2M;\n\tPROVIDE(__bss_start = .);\n\t.data : AT( ADDR(.text) + SIZEOF(.text) ) {\n\t\tPROVIDE(__data_lma = LOADADDR(.data));\n\t\tPROVIDE(__data_vma = .);\n\t\t. += SIZEOF(.data);\n\t\t*(.data*);\n\t\tPROVIDE(__data_lma_end = LOADADDR(.data) + SIZEOF(.data));\n\t}\n\t\/* Note that none of these get loaded properly unless the program does it\n\t * by itself.\n\t * 1. Map __bss_start .. __bss_end as read-writeable zero-init memory\n\t * 2. Copy __data_size bytes from __data_lma to __data_vma. \n\t * __data_vma is inside the bss range just allocated. *\/\n\t.bss : {\n\t\t*(.bss*);\n\t}\n\tPROVIDE(__bss_end = ALIGN(4096));\n\tPROVIDE(__data_size = SIZEOF(.data));\n\t.placeholder (NOLOAD) : {\n\t\t*(SORT_BY_ALIGNMENT(.placeholder*));\n\t}\n\t\/DISCARD\/ : {\n\t\t*(.eh_frame);\n\t\t*(.comment);\n\t\t*(.note*);\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"95a091f962734f8aaf260bb3c25a363d551baef9","subject":"arch: arm: ensure shared mem and app sram MPU regions don't overlap","message":"arch: arm: ensure shared mem and app sram MPU regions don't overlap\n\nThis commit contributes a patch to the Arm Cortex-M linker\nscript, which guarantees that the linker sections for shared\nmemory and the application memory will have sufficient padding\nin between, so that the latter will start from an address that\nis 32-byte aligned. This is required for ensuring that the MPU\nregions defined using the start and end addresses of the two\nsections will not overlap. The patch targets ARMv8-M MPU with\nno requirement for power-of-two alignment and size.\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\n","repos":"zephyrproject-rtos\/zephyr,ldts\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,ldts\/zephyr,galak\/zephyr,nashif\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,nashif\/zephyr,ldts\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,galak\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,explora26\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,punitvara\/zephyr,finikorg\/zephyr,punitvara\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,punitvara\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN . = ALIGN(4);\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t\/* 32-byte align end of app shared area to make MPU friendly *\/\n\t\t. = ALIGN(_app_data_align);\n\t\t_app_smem_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN . = ALIGN(4);\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t_app_smem_end = .;\n\t\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d0424bf7303a3fa2a4a2114f1eac573d9972af63","subject":"linker: arm: Split out application from kernel","message":"linker: arm: Split out application from kernel\n\nThis patch splits out the application data and bss from the\nrest of the kernel.  Choosing CONFIG_APPLICATION_MEMORY will\nresult in the application and kernel being split.\n\nSigned-off-by: Andy Gross <4ba87047449f5700e8758e3b1af36e94376c2fff@linaro.org>\n","repos":"Vudentz\/zephyr,rsalveti\/zephyr,ldts\/zephyr,Vudentz\/zephyr,aceofall\/zephyr-iotos,explora26\/zephyr,zephyrproject-rtos\/zephyr,rsalveti\/zephyr,mbolivar\/zephyr,runchip\/zephyr-cc3220,runchip\/zephyr-cc3220,Vudentz\/zephyr,mbolivar\/zephyr,ldts\/zephyr,fbsder\/zephyr,holtmann\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyriot\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,GiulianoFranchetto\/zephyr,rsalveti\/zephyr,Vudentz\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,ldts\/zephyr,aceofall\/zephyr-iotos,Vudentz\/zephyr,rsalveti\/zephyr,ldts\/zephyr,aceofall\/zephyr-iotos,fbsder\/zephyr,finikorg\/zephyr,nashif\/zephyr,runchip\/zephyr-cc3220,explora26\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,explora26\/zephyr,holtmann\/zephyr,zephyriot\/zephyr,mbolivar\/zephyr,zephyriot\/zephyr,fbsder\/zephyr,holtmann\/zephyr,fbsder\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,punitvara\/zephyr,fbsder\/zephyr,rsalveti\/zephyr,holtmann\/zephyr,aceofall\/zephyr-iotos,punitvara\/zephyr,runchip\/zephyr-cc3220,galak\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,GiulianoFranchetto\/zephyr,aceofall\/zephyr-iotos,zephyrproject-rtos\/zephyr,finikorg\/zephyr,punitvara\/zephyr,kraj\/zephyr,mbolivar\/zephyr,ldts\/zephyr,punitvara\/zephyr,kraj\/zephyr,runchip\/zephyr-cc3220,holtmann\/zephyr,kraj\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE CONFIG_SRAM_SIZE * 1K\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n    __data_rom_start = .;    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\n\t\/* Put all the stacks here in the kernel noinit *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\t__kernel_ram_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\t_image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE CONFIG_SRAM_SIZE * 1K\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n    __data_rom_start = .;    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\tCOMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n\n\t_image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d666baf88b5315f9c45b0de15fe54cf6d2316bb6","subject":"linker.ld: using temp includeos linker.ld","message":"linker.ld: using temp includeos linker.ld\n","repos":"mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,hioa-cs\/IncludeOS,ingve\/IncludeOS,AnnikaH\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,AnnikaH\/IncludeOS,ingve\/IncludeOS,AndreasAakesson\/IncludeOS,alfred-bratterud\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,alfred-bratterud\/IncludeOS,alfred-bratterud\/IncludeOS,ingve\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,ingve\/IncludeOS,AndreasAakesson\/IncludeOS,ingve\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS","old_file":"src\/linker.ld","new_file":"src\/linker.ld","new_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0xA00000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  .multiboot (_ELF_START_ + SIZEOF_HEADERS): {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n  PROVIDE( _TEXT_START_ = . );\n  .text (_TEXT_START_ ) :\n  {\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x10) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array     :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/* XXX: We shouldn't have to do this. *\/\n  . = ALIGN(0x100000);\n\n  .bss :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n    . = ALIGN(64 \/ 8);\n  }\n  . = ALIGN(64 \/ 8);\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS {\n    . = 0x100000;\n    PROVIDE ( _ELF_START_ = .);\n    PROVIDE ( _LOAD_START_ = _ELF_START_);\n\n    .multiboot (_ELF_START_ + SIZEOF_HEADERS): {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n    }\n\n    \/* Code *\/\n    _stext = .;\n\n    PROVIDE( _TEXT_START_ = . );\n    .text (_TEXT_START_ ) :\n    {\n        *(.text)\n        *(.text.*)\n    }\n    PROVIDE( _TEXT_END_ = . );\n\n    . = ALIGN(0x1000);\n    _etext = .;\n\n    \/* Read-only data *\/\n    .rodata :\n    {\n        _RODATA_START_ = .;\n        *(.rodata)\n        *(.rodata.*)\n        _RODATA_END_ = .;\n    }\n\n\n    \/* For stack unwinding (exception handling)  *\/\n    .eh_frame_hdr ALIGN(0x8):\n    {\n      KEEP(*(.eh_frame_hdr*))\n    }\n\n    .eh_frame :\n    {\n        PROVIDE (__eh_frame_start = .);\n        *(.eh_frame)\n    }\n\n    . = ALIGN(0x1000);\n    _erodata = .;\n\n    \/* Read-write data (initialized) *\/\n    .got :\n    {\n        *(.got.plt)\n        *(.got)\n    }\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n    }\n\n    _edata = .;\n\n    . = ALIGN(0x1000);\n\n    .elf_symbols : {\n      _ELF_SYM_START_ = .;\n      LONG (0);\n    }\n\n    \/* XXX: We shouldn't have to do this. *\/\n    . = ALIGN(0x100000);\n\n    \/* Read-write data (uninitialized) *\/\n    .bss :\n    {\n        _BSS_START_ = .;\n        *(.bss .bss.* .gnu.linkonce.b.*)\n        *(COMMON)\n        _BSS_END_ = .;\n    }\n\n    . = ALIGN(0x1000);\n    _ebss = .;\n    _end = .;\n\n    PROVIDE (_ELF_END_ = .);\n    PROVIDE (_LOAD_END_ = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a9d7d2a0a4885600ae7124f81f5e937ca7a35bf0","subject":"Fix for linking error in monolitic build","message":"Fix for linking error in monolitic build\n\n","repos":"BrewPi\/firmware,BrewPi\/firmware,BrewPi\/firmware,BrewPi\/firmware,BrewPi\/firmware,BrewPi\/firmware,BrewPi\/firmware,BrewPi\/firmware","old_file":"platform\/spark\/firmware\/hal\/src\/photon\/wiced\/platform\/MCU\/STM32F2xx\/GCC\/app_no_bootloader.ld","new_file":"platform\/spark\/firmware\/hal\/src\/photon\/wiced\/platform\/MCU\/STM32F2xx\/GCC\/app_no_bootloader.ld","new_contents":"\/*\n * Copyright (c) 2015 Broadcom\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without modification,\n * are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice, this\n * list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright notice, this\n * list of conditions and the following disclaimer in the documentation and\/or\n * other materials provided with the distribution.\n *\n * 3. Neither the name of Broadcom nor the names of other contributors to this\n * software may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * 4. This software may not be used as a standalone product, and may only be used as\n * incorporated in your product or device that incorporates Broadcom wireless connectivity\n * products and solely for the purpose of enabling the functionalities of such Broadcom products.\n *\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n * ANY WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT, ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\nreset_handler = _start;\n\nENTRY( _start );\n\n\/* Include memory map *\/\nINCLUDE memory_no_bootloader.ld\n\nSECTIONS\n{\n\n    .vectors :\n    {\n        link_module_start = .;\n        link_interrupt_vectors_location = .;\n        KEEP(*(*.interrupt_vector_table))\n        link_interrupt_vectors_location_end = .;\n    }>APP_FLASH  AT> APP_FLASH\n\n    interrupt_vectors_length = link_interrupt_vectors_location_end - link_interrupt_vectors_location;\n\n    .module_info :\n    {\n        . = ALIGN(4);\n        link_module_info_start = .;\n        KEEP(*.o(.modinfo.module_info))\n        link_module_info_end = .;\n    }>APP_FLASH  AT> APP_FLASH\n\n    .text :\n    {\n        . = ALIGN(4);\n        link_code_location = .;\n        KEEP(*(.text.irq ))\n        *(.text .text.* .gnu.linkonce.t.*)\n        link_code_end = .;\n\n        . = ALIGN(0x4);\n\n        link_const_variable_data_location = .;\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\n        link_const_variable_data_end = .;\n\n        . = ALIGN(0x4);\n\n        link_constructors_location = .;\n        link_early_startup_begin = .;\n        KEEP(*.o(.early_startup.*))\n        link_early_startup_end = .;\n        KEEP(*(.preinit_array))\n        KEEP(*(.init_array))\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        link_constructors_end = .;\n\n        . = ALIGN(0x4);\n\n        link_destructors_location = .;\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        link_destructors_end = .;\n\n        . = ALIGN(16);\n\n    }>APP_FLASH  AT> APP_FLASH\n\n    \/*\n     * The .ARM.exidx and .ARM.extab sections are used for C++ exception handling.\n     * It is located here for completeness. Bare-metal ARM projects\n     * typically cannot afford the overhead associated with C++\n     * exceptions handling.\n     *\/\n    .ARM.exidx :\n    {\n        __exidx_start = ALIGN(4);\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > APP_FLASH  AT> APP_FLASH\n\n    .ARM.extab :\n    {\n        __extab_start = ALIGN(4);\n        *(.ARM.extab*)\n        __extab_end = .;\n    } > APP_FLASH  AT> APP_FLASH\n\n    .ram_vectors : \/* Ram VTOR table - must be 512 byte-aligned *\/\n    {\n        link_ram_interrupt_vectors_location = .;\n        . = . + interrupt_vectors_length;\n        link_ram_interrupt_vectors_location_end = .;\n    }> SRAM\n\n    .fast : \/* This section contains code that is run from RAM after being loaded from flash - functions can be put in this section with the C attribute: __attribute__ ((section (\".fast\"))) *\/\n    {\n        link_run_from_ram_code_flash_location = LOADADDR( .fast ); \/* This is the location in flash of the code *\/\n        link_run_from_ram_code_ram_location = .;\n        *(.fast .fast.* .text.fastcode)\n        link_run_from_ram_code_ram_end = .;\n    }> SRAM AT> APP_FLASH\n\n    .data : \/* Contains the non-zero initialised global variables *\/\n    {\n        link_global_data_initial_values = LOADADDR( .data ); \/* This is the location in flash of the initial values of global variables *\/\n        link_global_data_start = .;\n        *(.data*)\n        link_global_data_end = .;\n        . = ALIGN(., 4);\n    }> SRAM AT> APP_FLASH\n\n\n    .bss : \/* Zero initialised memory used for zero initialised variables *\/\n    {\n        link_bss_location = ALIGN(., 4);\n        *(.bss*)\n        *(COMMON)\n        link_bss_end = .;\n        . = ALIGN(., 4);\n    }> SRAM AT> SRAM\n\n    .stack : \/* Contains the initial stack *\/\n    {\n        link_stack_location = ALIGN(., 4);\n        *(.stack)\n        . = ALIGN(MAX(link_stack_location + __STACKSIZE__ , .), 4);\n        link_stack_end = .;\n    }> SRAM AT> SRAM\n\n    INCLUDE backup_ram_user.ld\n    INCLUDE backup_ram_system.ld\n\n    link_heap_location = _heap;\n    link_heap_location_end = _eheap;\n \n    \/DISCARD\/ :\n    {\n        *(.ARM.attributes*)\n        *(.comment)\n        *(.init)\n        *(.preinit)\n        *(.fini)\n        *(.fini_array)\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n        *(.gnu.linkonce.armextab.*)\n        *(.v4_bx)\n        *(.vfp11_veneer)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n        *(.glue*)\n    }\n\n    .module_info_suffix :\n    {\n        . = ALIGN(., 4) ;\n        link_module_info_suffix_start = .;\n        KEEP(*.o(.modinfo.module_info_suffix))\n        link_module_info_suffix_end = .;\n    }>APP_FLASH AT> APP_FLASH\n\n    .module_end :\n    {\n        link_module_end = .;\n    }> APP_FLASH AT>APP_FLASH\n\n    .module_info_crc :\n    {\n        link_module_info_crc_start = .;\n        KEEP(*.o(.modinfo.module_info_crc))\n        link_module_info_crc_end = .;\n    }>APP_FLASH AT> APP_FLASH\n\n\n}\n\n\/* Declare libc Heap to start at end of allocated RAM *\/\n\nPROVIDE( _heap = link_stack_end );\n\n\/* End of the heap is top of RAM, aligned 8 byte *\/\n\nPROVIDE( _eheap = ALIGN( ORIGIN( SRAM ) + LENGTH( SRAM ) - 8, 8 ) );\n\n\/* ThreadX aliases *\/\nPROVIDE( __RAM_segment_used_end__ = link_stack_end );\nPROVIDE( __tx_free_memory_start = link_stack_end );\nPROVIDE( __tx_vectors = link_interrupt_vectors_location );\n\nPROVIDE( dct1_start_addr_loc     = ORIGIN( DCT1_FLASH ));\nPROVIDE( dct1_size_loc           = LENGTH( DCT1_FLASH ));\nPROVIDE( dct2_start_addr_loc     = ORIGIN( DCT2_FLASH ));\nPROVIDE( dct2_size_loc           = LENGTH( DCT2_FLASH ));\n\nPROVIDE( VTOR_Length = interrupt_vectors_length );\n\nASSERT( link_ram_interrupt_vectors_location == ORIGIN( SRAM ), \"RAM Interrupt table should be at start of RAM\" );\nASSERT( ( link_ram_interrupt_vectors_location_end - link_ram_interrupt_vectors_location ) == VTOR_Length, \"Expected RAM VTOR table to be same length as VTOR Flash\" );\n\nINCLUDE module_export.ld\n\nASSERT ( link_module_info_start < link_module_info_end, \"module info not linked\" );\nASSERT ( link_module_info_suffix_start < link_module_info_suffix_end, \"module info suffix not linked\" );\nASSERT ( link_module_info_crc_start < link_module_info_crc_end, \"module info crc not linked\" );\n\nASSERT ( mono_module_info == link_module_info_start, \"module info start not where expected\" );\nASSERT ( mono_module_info_end == link_module_info_end, \"module info end not where expected\" );\n\nASSERT ( link_early_startup_begin != link_early_startup_end, \"no early startup functions linked\" );\n","old_contents":"\/*\n * Copyright (c) 2015 Broadcom\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without modification,\n * are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice, this\n * list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright notice, this\n * list of conditions and the following disclaimer in the documentation and\/or\n * other materials provided with the distribution.\n *\n * 3. Neither the name of Broadcom nor the names of other contributors to this\n * software may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * 4. This software may not be used as a standalone product, and may only be used as\n * incorporated in your product or device that incorporates Broadcom wireless connectivity\n * products and solely for the purpose of enabling the functionalities of such Broadcom products.\n *\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n * ANY WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT, ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\nreset_handler = _start;\n\nENTRY( _start );\n\n\/* Include memory map *\/\nINCLUDE memory_no_bootloader.ld\n\nSECTIONS\n{\n\n    .vectors :\n    {\n        link_module_start = .;\n        link_interrupt_vectors_location = .;\n        KEEP(*(*.interrupt_vector_table))\n        link_interrupt_vectors_location_end = .;\n    }>APP_FLASH  AT> APP_FLASH\n\n    interrupt_vectors_length = link_interrupt_vectors_location_end - link_interrupt_vectors_location;\n\n    .module_info :\n    {\n        . = ALIGN(4);\n        link_module_info_start = .;\n        KEEP(*.o(.modinfo.module_info))\n        link_module_info_end = .;\n    }>APP_FLASH  AT> APP_FLASH\n\n    .text :\n    {\n        . = ALIGN(4);\n        link_code_location = .;\n        KEEP(*(.text.irq ))\n        *(.text .text.* .gnu.linkonce.t.*)\n        link_code_end = .;\n\n        . = ALIGN(0x4);\n\n        link_const_variable_data_location = .;\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\n        link_const_variable_data_end = .;\n\n        . = ALIGN(0x4);\n\n        link_constructors_location = .;\n        link_early_startup_begin = .;\n        KEEP(*.o(.early_startup.*))\n        link_early_startup_end = .;\n        KEEP(*(.preinit_array))\n        KEEP(*(.init_array))\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        link_constructors_end = .;\n\n        . = ALIGN(0x4);\n\n        link_destructors_location = .;\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        link_destructors_end = .;\n\n        . = ALIGN(16);\n\n    }>APP_FLASH  AT> APP_FLASH\n\n    \/*\n     * The .ARM.exidx and .ARM.extab sections are used for C++ exception handling.\n     * It is located here for completeness. Bare-metal ARM projects\n     * typically cannot afford the overhead associated with C++\n     * exceptions handling.\n     *\/\n    .ARM.exidx :\n    {\n        __exidx_start = ALIGN(4);\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > APP_FLASH  AT> APP_FLASH\n\n    .ARM.extab :\n    {\n        __extab_start = ALIGN(4);\n        *(.ARM.extab*)\n        __extab_end = .;\n    } > APP_FLASH  AT> APP_FLASH\n\n    .ram_vectors : \/* Ram VTOR table - must be 512 byte-aligned *\/\n    {\n        link_ram_interrupt_vectors_location = .;\n        . = . + interrupt_vectors_length;\n        link_ram_interrupt_vectors_location_end = .;\n    }> SRAM\n\n    .fast : \/* This section contains code that is run from RAM after being loaded from flash - functions can be put in this section with the C attribute: __attribute__ ((section (\".fast\"))) *\/\n    {\n        link_run_from_ram_code_flash_location = LOADADDR( .fast ); \/* This is the location in flash of the code *\/\n        link_run_from_ram_code_ram_location = .;\n        *(.fast .fast.* .text.fastcode)\n        link_run_from_ram_code_ram_end = .;\n    }> SRAM AT> APP_FLASH\n\n    .data : \/* Contains the non-zero initialised global variables *\/\n    {\n        link_global_data_initial_values = LOADADDR( .data ); \/* This is the location in flash of the initial values of global variables *\/\n        link_global_data_start = .;\n        *(.data*)\n        link_global_data_end = .;\n        . = ALIGN(., 4);\n    }> SRAM AT> APP_FLASH\n\n\n    .bss : \/* Zero initialised memory used for zero initialised variables *\/\n    {\n        link_bss_location = ALIGN(., 4);\n        *(.bss*)\n        *(COMMON)\n        link_bss_end = .;\n        . = ALIGN(., 4);\n    }> SRAM AT> SRAM\n\n    .stack : \/* Contains the initial stack *\/\n    {\n        link_stack_location = ALIGN(., 4);\n        *(.stack)\n        . = ALIGN(MAX(link_stack_location + __STACKSIZE__ , .), 4);\n        link_stack_end = .;\n    }> SRAM AT> SRAM\n\n    INCLUDE backup_ram_user.ld\n    INCLUDE backup_ram_system.ld\n\n    \/DISCARD\/ :\n    {\n        *(.ARM.attributes*)\n        *(.comment)\n        *(.init)\n        *(.preinit)\n        *(.fini)\n        *(.fini_array)\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n        *(.gnu.linkonce.armextab.*)\n        *(.v4_bx)\n        *(.vfp11_veneer)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n        *(.glue*)\n    }\n\n    .module_info_suffix :\n    {\n        . = ALIGN(., 4) ;\n        link_module_info_suffix_start = .;\n        KEEP(*.o(.modinfo.module_info_suffix))\n        link_module_info_suffix_end = .;\n    }>APP_FLASH AT> APP_FLASH\n\n    .module_end :\n    {\n        link_module_end = .;\n    }> APP_FLASH AT>APP_FLASH\n\n    .module_info_crc :\n    {\n        link_module_info_crc_start = .;\n        KEEP(*.o(.modinfo.module_info_crc))\n        link_module_info_crc_end = .;\n    }>APP_FLASH AT> APP_FLASH\n\n\n}\n\n\/* Declare libc Heap to start at end of allocated RAM *\/\n\nPROVIDE( _heap = link_stack_end );\n\n\/* End of the heap is top of RAM, aligned 8 byte *\/\n\nPROVIDE( _eheap = ALIGN( ORIGIN( SRAM ) + LENGTH( SRAM ) - 8, 8 ) );\n\n\/* ThreadX aliases *\/\nPROVIDE( __RAM_segment_used_end__ = link_stack_end );\nPROVIDE( __tx_free_memory_start = link_stack_end );\nPROVIDE( __tx_vectors = link_interrupt_vectors_location );\n\nPROVIDE( dct1_start_addr_loc     = ORIGIN( DCT1_FLASH ));\nPROVIDE( dct1_size_loc           = LENGTH( DCT1_FLASH ));\nPROVIDE( dct2_start_addr_loc     = ORIGIN( DCT2_FLASH ));\nPROVIDE( dct2_size_loc           = LENGTH( DCT2_FLASH ));\n\nPROVIDE( VTOR_Length = interrupt_vectors_length );\n\nASSERT( link_ram_interrupt_vectors_location == ORIGIN( SRAM ), \"RAM Interrupt table should be at start of RAM\" );\nASSERT( ( link_ram_interrupt_vectors_location_end - link_ram_interrupt_vectors_location ) == VTOR_Length, \"Expected RAM VTOR table to be same length as VTOR Flash\" );\n\nINCLUDE module_export.ld\n\nASSERT ( link_module_info_start < link_module_info_end, \"module info not linked\" );\nASSERT ( link_module_info_suffix_start < link_module_info_suffix_end, \"module info suffix not linked\" );\nASSERT ( link_module_info_crc_start < link_module_info_crc_end, \"module info crc not linked\" );\n\nASSERT ( mono_module_info == link_module_info_start, \"module info start not where expected\" );\nASSERT ( mono_module_info_end == link_module_info_end, \"module info end not where expected\" );\n\nASSERT ( link_early_startup_begin != link_early_startup_end, \"no early startup functions linked\" );\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"92360664506347141fab5224b26403f8c93199e0","subject":"Locate kernel in right place","message":"Locate kernel in right place\n","repos":"tailix\/kernelmq,tailix\/kernelmq","old_file":"arch\/linker.ld","new_file":"arch\/linker.ld","new_contents":"OUTPUT_ARCH(\"i386\")\nENTRY(_start)\n\n_kernel_offset = 0xC0000000; \/* 3 GB *\/\n\n_kernel_phys_base = 4M;\n_kernel_virt_base = (_kernel_phys_base + _kernel_offset);\n\nSECTIONS\n{\n    . = _kernel_phys_base;\n\n    .text BLOCK(4K) : ALIGN(4K)\n    {\n        *(.multiboot)\n        *(.text)\n    }\n\n    .rodata BLOCK(4K) : ALIGN(4K)\n    {\n        *(.rodata)\n    }\n\n    .data BLOCK(4K) : ALIGN(4K)\n    {\n        *(.data)\n    }\n\n    .bss BLOCK(4K) : ALIGN(4K)\n    {\n        *(COMMON)\n        *(.bss)\n    }\n}\n","old_contents":"OUTPUT_ARCH(\"i386\")\nENTRY(_start)\n\n_kernel_offset = 0xC0000000; \/* 3 GB *\/\n\n_kernel_phys_base = 4M;\n_kernel_virt_base = (_kernel_phys_base + _kernel_offset);\n\nSECTIONS\n{\n    . = 1M;\n\n    .text BLOCK(4K) : ALIGN(4K)\n    {\n        *(.multiboot)\n        *(.text)\n    }\n\n    .rodata BLOCK(4K) : ALIGN(4K)\n    {\n        *(.rodata)\n    }\n\n    .data BLOCK(4K) : ALIGN(4K)\n    {\n        *(.data)\n    }\n\n    .bss BLOCK(4K) : ALIGN(4K)\n    {\n        *(COMMON)\n        *(.bss)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3e7a245c4637670a120048897a194711b2c8d53f","subject":"[BSP][K210]utest support","message":"[BSP][K210]utest support\n","repos":"hezlog\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,AubrCool\/rt-thread,weiyuliang\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,RT-Thread\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread","old_file":"bsp\/k210\/link.lds","new_file":"bsp\/k210\/link.lds","new_contents":"\/*\n * Copyright (c) 2006-2018, RT-Thread Development Team\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Change Logs:\n * Date           Author       Notes\n *\/\n\nINCLUDE \"link_stacksize.lds\"\n\n\/*\n * The OUTPUT_ARCH command specifies the machine architecture where the\n * argument is one of the names used in the Kendryte library.\n *\/\nOUTPUT_ARCH( \"riscv\" )\n\nMEMORY\n{\n   \/* 6M SRAM *\/\n   SRAM : ORIGIN = 0x80000000, LENGTH = 0x600000\n}\n\nENTRY(_start)\nSECTIONS\n{\n    . = 0x80000000 ;\n\n    \/* __STACKSIZE__ = 4096; *\/\n\n    .start :\n    {\n        *(.start);\n    } > SRAM\n\n    . = ALIGN(8);\n\n    .text : \n    {\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n     \n        \/* section information for finsh shell *\/\n        . = ALIGN(8);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(8);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(8);\n\n        \/* section information for initial. *\/\n        . = ALIGN(8);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(8);\n\n        __rt_utest_tc_tab_start = .;\n        KEEP(*(UtestTcTab))\n        __rt_utest_tc_tab_end = .;\n\n        . = ALIGN(8);\n        _etext = .;\n    } > SRAM\n\n    .eh_frame_hdr : \n    { \n         *(.eh_frame_hdr) \n         *(.eh_frame_entry)\n    } > SRAM\n    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM\n\n    . = ALIGN(8);\n\n    .data : \n    {\n        *(.data)\n        *(.data.*)\n    \n        *(.data1)\n        *(.data1.*)\n\n        . = ALIGN(8);\n        PROVIDE( __global_pointer$ = . + 0x800 );\n\n        *(.sdata)\n        *(.sdata.*)\n    } > SRAM\n\n    \/* stack for dual core *\/\n    .stack :\n    {\n        . = ALIGN(64);\n        __stack_start__ = .;\n\n        . += __STACKSIZE__;\n        __stack_cpu0 = .;\n\n        . += __STACKSIZE__;\n        __stack_cpu1 = .;\n    } > SRAM\n\n    .sbss : \n    {\n    __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.dynsbss)\n        *(.scommon)\n    } > SRAM\n\n    .bss :\n    {\n        *(.bss)\n        *(.bss.*)\n        *(.dynbss)\n        *(COMMON)\n    __bss_end = .;\n    } > SRAM\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * Copyright (c) 2006-2018, RT-Thread Development Team\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Change Logs:\n * Date           Author       Notes\n *\/\n\nINCLUDE \"link_stacksize.lds\"\n\n\/*\n * The OUTPUT_ARCH command specifies the machine architecture where the\n * argument is one of the names used in the Kendryte library.\n *\/\nOUTPUT_ARCH( \"riscv\" )\n\nMEMORY\n{\n   \/* 6M SRAM *\/\n   SRAM : ORIGIN = 0x80000000, LENGTH = 0x600000\n}\n\nENTRY(_start)\nSECTIONS\n{\n    . = 0x80000000 ;\n\n    \/* __STACKSIZE__ = 4096; *\/\n\n    .start :\n    {\n        *(.start);\n    } > SRAM\n\n    . = ALIGN(4);\n\n    .text : \n    {\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n     \n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        _etext = .;\n    } > SRAM\n\n    .eh_frame_hdr : \n    { \n         *(.eh_frame_hdr) \n         *(.eh_frame_entry)\n    } > SRAM\n    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM\n\n    . = ALIGN(4);\n\n    .data : \n    {\n        *(.data)\n        *(.data.*)\n    \n        *(.data1)\n        *(.data1.*)\n\n        . = ALIGN(8);\n        PROVIDE( __global_pointer$ = . + 0x800 );\n\n        *(.sdata)\n        *(.sdata.*)\n    } > SRAM\n\n    \/* stack for dual core *\/\n    .stack :\n    {\n        . = ALIGN(64);\n        __stack_start__ = .;\n\n        . += __STACKSIZE__;\n        __stack_cpu0 = .;\n\n        . += __STACKSIZE__;\n        __stack_cpu1 = .;\n    } > SRAM\n\n    .sbss : \n    {\n    __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.dynsbss)\n        *(.scommon)\n    } > SRAM\n\n    .bss :\n    {\n        *(.bss)\n        *(.bss.*)\n        *(.dynbss)\n        *(COMMON)\n    __bss_end = .;\n    } > SRAM\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"651098ac00ddd9eaaa1025fe36dd0425142cea82","subject":"Back track","message":"Back track\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/src\/gcc_arm_flash.ld","new_file":"ARM\/src\/gcc_arm_flash.ld","new_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t\n\t\t\/* At addr zero is the stack pointer *\/\n\t\t\/*LONG(__StackTop);*\/\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect*))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\t\/* in case security config is not defined, fill in default *\/\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xfffffffe);\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : \n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n\n   \t\/* calculate size to take full range from .data to .bss in case other data sections\n   \t   were inserted in between from outside of this file *\/\n   \t__data_size__ = SIZEOF(.data);\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","old_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t\n\t\t\/* At addr zero is the stack pointer *\/\n\t\t\/*LONG(__StackTop);*\/\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect*))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\t\/* in case security config is not defined, fill in default *\/\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xfffffffe);\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : \n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n\n   \t\/* calculate size to take full range from .data to .bss in case other data sections\n   \t   were inserted in between from outside of this file *\/\n   \t__data_size__ = __bss_start__ - __data_start__; \/*SIZEOF(.data);*\/\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"05de9f853a95cd578318cf94833422ebae7a6496","subject":"[53050-correct-typo-in-linker-script] typo in linker script","message":"[53050-correct-typo-in-linker-script] typo in linker script\n\nthough it did not appear to affect operation, this was an improperly\nformatted hex value\n","repos":"PDXostc\/can_firewall_software,PDXostc\/can_firewall_software","old_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-avr32\", \"elf32-avr32\",\n\t      \"elf32-avr32\")\nOUTPUT_ARCH(avr32:uc)\nENTRY(_start)\nSEARCH_DIR(\"\/home\/toolsbuild\/jenkins-knuth\/workspace\/avr32-gnu-toolchain\/avr32-gnu-toolchain-win32_x86\/avr32\/lib\");\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY\n{\n    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K-10K-8K\n\t\tFLASHRSVD (rxai!w) : ORIGIN = 0x80000000+512K-10K-8K, LENGTH = 10K\n    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC\n    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512\n    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512\n    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8\n    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8\n    HSBRAM (wxa!ri) : ORIGIN = 0xA0000000, LENGTH = 4K\n}\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;\n\t\/* Next line should not be necessary for use of flash for storing rules *\/\n\t\/* .flash_rsvd : { *(.flash_rsvd) } >FLASHRSVD AT>FLASHRSVD *\/\n  .interp         : { *(.interp) } >FLASH AT>FLASH\n  .reset : {  *(.reset) } >FLASH AT>FLASH\n  .hash           : { *(.hash) } >FLASH AT>FLASH\n  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH\n  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH\n  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH\n  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH\n  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH\n  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH\n  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH\n  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH\n  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH\n  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH\n  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH\n  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH\n  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH\n  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH\n  .init           :\n  {\n    KEEP (*(.init))\n  } >FLASH AT>FLASH =0xd703d703\n  .plt            : { *(.plt) } >FLASH AT>FLASH\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } >FLASH AT>FLASH =0xd703d703\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } >FLASH AT>FLASH =0xd703d703\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH\n  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH\n  .dalign\t: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH\n  PROVIDE (_data = ORIGIN(CPUSRAM));\n  . = ORIGIN(CPUSRAM);\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  PROVIDE (__preinit_array_start = ALIGN(32 \/ 8));\n  .preinit_array     : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >CPUSRAM AT>FLASH\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >CPUSRAM AT>FLASH\n  .jcr            : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH\n  .dynamic        : { *(.dynamic) } >CPUSRAM AT>FLASH\n  .got            : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH\n  .data           :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  } >CPUSRAM AT>FLASH\n  .data1          : { *(.data1) } >CPUSRAM AT>FLASH\n  .balign\t: { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(8);\n  } >CPUSRAM\n  . = ALIGN(8);\n  _end = .;\n  PROVIDE (end = .);\n  __heap_start__ = ALIGN(8);\n  . = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;\n  __heap_end__ = .;\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :\n  {\n    _stack = .;\n    *(.stack)\n    . = _stack_size;\n    _estack = .;\n  } >CPUSRAM\n  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE\n  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE\n\t.flash : { *(.flash .flash.*) } >FLASH AT>FLASH\n\t.flash_rsvd : { *(.flash_rsvd .flash_rsvd.*) } >FLASHRSVD AT>FLASHRSVD\n  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE\n  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE\n  .hsb_ram_loc : { *(.hsb_ram_loc .hsb_ram_loc.*)  } >HSBRAM AT>HSBRAM\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-avr32\", \"elf32-avr32\",\n\t      \"elf32-avr32\")\nOUTPUT_ARCH(avr32:uc)\nENTRY(_start)\nSEARCH_DIR(\"\/home\/toolsbuild\/jenkins-knuth\/workspace\/avr32-gnu-toolchain\/avr32-gnu-toolchain-win32_x86\/avr32\/lib\");\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY\n{\n    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K-10K-8K\n\t\tFLASHRSVD (rxai!w) : ORIGIN = 0x80000000+512K-10K-8K, LENGTH = 10K\n    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC\n    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512\n    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512\n    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8\n    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8\n    HSBRAM (wxa!ri) : ORIGIN = 0XA0000000, LENGTH = 4K\n}\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;\n\t\/* Next line should not be necessary for use of flash for storing rules *\/\n\t\/* .flash_rsvd : { *(.flash_rsvd) } >FLASHRSVD AT>FLASHRSVD *\/\n  .interp         : { *(.interp) } >FLASH AT>FLASH\n  .reset : {  *(.reset) } >FLASH AT>FLASH\n  .hash           : { *(.hash) } >FLASH AT>FLASH\n  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH\n  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH\n  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH\n  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH\n  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH\n  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH\n  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH\n  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH\n  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH\n  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH\n  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH\n  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH\n  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH\n  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH\n  .init           :\n  {\n    KEEP (*(.init))\n  } >FLASH AT>FLASH =0xd703d703\n  .plt            : { *(.plt) } >FLASH AT>FLASH\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } >FLASH AT>FLASH =0xd703d703\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } >FLASH AT>FLASH =0xd703d703\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH\n  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH\n  .dalign\t: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH\n  PROVIDE (_data = ORIGIN(CPUSRAM));\n  . = ORIGIN(CPUSRAM);\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  PROVIDE (__preinit_array_start = ALIGN(32 \/ 8));\n  .preinit_array     : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >CPUSRAM AT>FLASH\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >CPUSRAM AT>FLASH\n  .jcr            : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH\n  .dynamic        : { *(.dynamic) } >CPUSRAM AT>FLASH\n  .got            : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH\n  .data           :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  } >CPUSRAM AT>FLASH\n  .data1          : { *(.data1) } >CPUSRAM AT>FLASH\n  .balign\t: { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(8);\n  } >CPUSRAM\n  . = ALIGN(8);\n  _end = .;\n  PROVIDE (end = .);\n  __heap_start__ = ALIGN(8);\n  . = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;\n  __heap_end__ = .;\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :\n  {\n    _stack = .;\n    *(.stack)\n    . = _stack_size;\n    _estack = .;\n  } >CPUSRAM\n  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE\n  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE\n\t.flash : { *(.flash .flash.*) } >FLASH AT>FLASH\n\t.flash_rsvd : { *(.flash_rsvd .flash_rsvd.*) } >FLASHRSVD AT>FLASHRSVD\n  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE\n  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE\n  .hsb_ram_loc : { *(.hsb_ram_loc .hsb_ram_loc.*)  } >HSBRAM AT>HSBRAM\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"66bf96edc7b0f5ca0633555e051abaa25264ddb6","subject":"Reference errata in to nrf52 linker script.","message":"Reference errata in to nrf52 linker script.\n","repos":"andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,wes3\/incubator-mynewt-core,wes3\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,IMGJulian\/incubator-mynewt-core,mlaz\/mynewt-core,wes3\/incubator-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core","old_file":"hw\/bsp\/nrf52pdk\/nrf52pdk.ld","new_file":"hw\/bsp\/nrf52pdk\/nrf52pdk.ld","new_contents":"\/**\n * Copyright (c) 2015 Runtime Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n *   http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script for Nordic Semiconductor nRF5 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000\n  CODE_RAM (rwx) : ORIGIN = 0x8000000, LENGTH = 0x8000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __nzbss_start__\n *   __nzbss_end__\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        __isr_vector_start = .;\n        KEEP(*(.isr_vector))\n        __isr_vector_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .vector_relocation :\n    {\n        . = ALIGN(4);\n        __vector_tbl_reloc__ = .;\n        . = . + (__isr_vector_end - __isr_vector_start);\n        . = ALIGN(4);\n    } > RAM\n            \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        *(.preinit_array)\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        *(SORT(.init_array.*))\n        *(.init_array)\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    \/* Heap starts after BSS *\/\n    __HeapBase = .;\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Top of head is the bottom of the stack *\/\n    __HeapLimit = __StackLimit;\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\n\n    \/* Non-zeroed BSS.  This section is similar to BSS, with the following two\n     * caveats:\n     *    1. It does not get zeroed at init-time.\n     *    2. You cannot use it as source memory for EasyDMA.\n     *\n     * This section exists because of a hardware defect; see errata 33 and 34\n     * in STM32F40x errata sheet.\n     *\/\n    .nzbss :\n    {\n        . = ALIGN(4);\n        __nzbss_start__ = .;\n        *(.nzbss*)\n        . = ALIGN(4);\n        __nzbss_end__ = .;\n    } > CODE_RAM\n}\n\n","old_contents":"\/**\n * Copyright (c) 2015 Runtime Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n *   http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script for Nordic Semiconductor nRF5 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000\n  CODE_RAM (rwx) : ORIGIN = 0x8000000, LENGTH = 0x8000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __nzbss_start__\n *   __nzbss_end__\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        __isr_vector_start = .;\n        KEEP(*(.isr_vector))\n        __isr_vector_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .vector_relocation :\n    {\n        . = ALIGN(4);\n        __vector_tbl_reloc__ = .;\n        . = . + (__isr_vector_end - __isr_vector_start);\n        . = ALIGN(4);\n    } > RAM\n            \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        *(.preinit_array)\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        *(SORT(.init_array.*))\n        *(.init_array)\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    \/* Heap starts after BSS *\/\n    __HeapBase = .;\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Top of head is the bottom of the stack *\/\n    __HeapLimit = __StackLimit;\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\n\n    \/* Non-zeroed BSS.  This section is similar to BSS, with the following two\n     * caveats:\n     *    1. It does not get zeroed at init-time.\n     *    2. You cannot use it as source memory for EasyDMA.\n     *\/\n    .nzbss :\n    {\n        . = ALIGN(4);\n        __nzbss_start__ = .;\n        *(.nzbss*)\n        . = ALIGN(4);\n        __nzbss_end__ = .;\n    } > CODE_RAM\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"93e9e3ad9035fdd1086ad0b3b9881712c179a1e6","subject":"Fix end of line","message":"Fix end of line\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/mimxrt10xx\/linking\/flash\/W25Q128JV.ld","new_file":"ports\/mimxrt10xx\/linking\/flash\/W25Q128JV.ld","new_contents":"_ld_flash_size = 16M;\n","old_contents":"_ld_flash_size = 16M;","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2743b8d16548bcdf2a58f153171dedf45dad4eaf","subject":"topics replace softlinks","message":"topics replace softlinks\n","repos":"beadsland\/Soma,beadsland\/Soma","old_file":"config.ld","new_file":"config.ld","new_contents":"project     = 'Soma'\nfile        = 'src'\ndescription = 'Lua emulation of Elixir semantics'\ntopics      = { 'README.md', \n                'LICENSE.md', 'NOTICE.md', 'TODO.md', 'CHANGELOG.md' }\nformat      = 'discount'\ndir         = 'docs'\n","old_contents":"project     = 'Soma'\nfile        = 'src'\ndescription = 'Lua emulation of Elixir semantics'\ntopics      = { 'README.md', \n                'LICENSE.md', 'NOTICE.md', 'TODO.md' }\nformat      = 'discount'\ndir         = 'docs'\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"025ec0def26a78bbd22597557a80bba4d8a30dfd","subject":"Do not discard .debug section","message":"Do not discard .debug section\n\nDo not discard the .debug section. If the builder would like to discard\nthis section, they can do so explicitly with objcopy.\n","repos":"redox-os\/kernel,AleVul\/kernel,redox-os\/kernel,AleVul\/kernel,redox-os\/kernel","old_file":"linkers\/x86_64.ld","new_file":"linkers\/x86_64.ld","new_contents":"ENTRY(kstart)\nOUTPUT_FORMAT(elf64-x86-64)\n\nKERNEL_OFFSET = 0xffffff0000100000;\n\/* KERNEL_OFFSET = 0x100000; *\/\n\nSECTIONS {\n    . = KERNEL_OFFSET;\n\n    . += SIZEOF_HEADERS;\n    . = ALIGN(4096);\n\n    .text : AT(ADDR(.text) - KERNEL_OFFSET) {\n        __text_start = .;\n        *(.text*)\n\t\t. = ALIGN(4096);\n        __text_end = .;\n    }\n\n\t.rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) {\n        __rodata_start = .;\n        *(.rodata*)\n\t\t. = ALIGN(4096);\n        __rodata_end = .;\n    }\n\n    .data : AT(ADDR(.data) - KERNEL_OFFSET) {\n        __data_start = .;\n        *(.data*)\n\t\t. = ALIGN(4096);\n        __data_end = .;\n        __bss_start = .;\n        *(.bss*)\n        . = ALIGN(4096);\n        __bss_end = .;\n    }\n\n    .tdata : AT(ADDR(.tdata) - KERNEL_OFFSET) {\n        __tdata_start = .;\n        *(.tdata*)\n        . = ALIGN(4096);\n        __tdata_end = .;\n        __tbss_start = .;\n        *(.tbss*)\n        . += 8;\n        . = ALIGN(4096);\n        __tbss_end = .;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ : {\n        *(.comment*)\n        *(.eh_frame*)\n        *(.gcc_except_table*)\n        *(.note*)\n        *(.rel.eh_frame*)\n    }\n}\n","old_contents":"ENTRY(kstart)\nOUTPUT_FORMAT(elf64-x86-64)\n\nKERNEL_OFFSET = 0xffffff0000100000;\n\/* KERNEL_OFFSET = 0x100000; *\/\n\nSECTIONS {\n    . = KERNEL_OFFSET;\n\n    . += SIZEOF_HEADERS;\n    . = ALIGN(4096);\n\n    .text : AT(ADDR(.text) - KERNEL_OFFSET) {\n        __text_start = .;\n        *(.text*)\n\t\t. = ALIGN(4096);\n        __text_end = .;\n    }\n\n\t.rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) {\n        __rodata_start = .;\n        *(.rodata*)\n\t\t. = ALIGN(4096);\n        __rodata_end = .;\n    }\n\n    .data : AT(ADDR(.data) - KERNEL_OFFSET) {\n        __data_start = .;\n        *(.data*)\n\t\t. = ALIGN(4096);\n        __data_end = .;\n        __bss_start = .;\n        *(.bss*)\n        . = ALIGN(4096);\n        __bss_end = .;\n    }\n\n    .tdata : AT(ADDR(.tdata) - KERNEL_OFFSET) {\n        __tdata_start = .;\n        *(.tdata*)\n        . = ALIGN(4096);\n        __tdata_end = .;\n        __tbss_start = .;\n        *(.tbss*)\n        . += 8;\n        . = ALIGN(4096);\n        __tbss_end = .;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ : {\n        *(.comment*)\n        *(.debug*)\n        *(.eh_frame*)\n        *(.gcc_except_table*)\n        *(.note*)\n        *(.rel.eh_frame*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"97d92789ec335374f2b57293df44a01604e3afbc","subject":"Fixed: The issue of interrupt vector remapping for GCC_ARM LPC1114","message":"Fixed: The issue of interrupt vector remapping for GCC_ARM LPC1114\n","repos":"tung7970\/mbed-os,logost\/mbed,mmorenobarm\/mbed-os,Archcady\/mbed-os,alertby\/mbed,karsev\/mbed-os,Archcady\/mbed-os,j-greffe\/mbed-os,CalSol\/mbed,rgrover\/mbed,Timmmm\/mbed,rosterloh\/mbed,getopenmono\/mbed,EmuxEvans\/mbed,tung7970\/mbed-os-1,kl-cruz\/mbed-os,nabilbendafi\/mbed,pedromes\/mbed,tung7970\/mbed-os-1,kpurusho\/mbed,Tiryoh\/mbed,devanlai\/mbed,rgrover\/mbed,FranklyDev\/mbed,masaohamanaka\/mbed,catiedev\/mbed-os,ryankurte\/mbed-os,cvtsi2sd\/mbed-os,al177\/mbed,mnlipp\/mbed,jamesadevine\/mbed,adamgreen\/mbed,naves-thiago\/mbed-midi,nabilbendafi\/mbed,tung7970\/mbed-os-1,RonEld\/mbed,svastm\/mbed,NXPmicro\/mbed,adamgreen\/mbed,mazimkhan\/mbed-os,rosterloh\/mbed,nvlsianpu\/mbed,nRFMesh\/mbed-os,nRFMesh\/mbed-os,xcrespo\/mbed,getopenmono\/mbed,K4zuki\/mbed,hwfwgrp\/mbed,Timmmm\/mbed,larks\/mbed,maximmbed\/mbed,nvlsianpu\/mbed,masaohamanaka\/mbed,Sweet-Peas\/mbed,NitinBhaskar\/mbed,monkiineko\/mbed-os,jferreir\/mbed,svastm\/mbed,xcrespo\/mbed,logost\/mbed,pedromes\/mbed,brstew\/MBED-BUILD,cvtsi2sd\/mbed-os,Timmmm\/mbed,dbestm\/mbed,nvlsianpu\/mbed,Marcomissyou\/mbed,mmorenobarm\/mbed-os,monkiineko\/mbed-os,arostm\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,netzimme\/mbed-os,catiedev\/mbed-os,monkiineko\/mbed-os,getopenmono\/mbed,fahhem\/mbed-os,sg-\/mbed-drivers,fanghuaqi\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,autopulated\/mbed,mmorenobarm\/mbed-os,bcostm\/mbed-os,YarivCol\/mbed-os,wodji\/mbed,fpiot\/mbed-ats,monkiineko\/mbed-os,fahhem\/mbed-os,pradeep-gr\/mbed-os5-onsemi,mnlipp\/mbed,bulislaw\/mbed-os,jferreir\/mbed,rosterloh\/mbed,masaohamanaka\/mbed,nRFMesh\/mbed-os,bikeNomad\/mbed,jpbrucker\/mbed,theotherjimmy\/mbed,YarivCol\/mbed-os,getopenmono\/mbed,ryankurte\/mbed-os,kpurusho\/mbed,mikaleppanen\/mbed-os,larks\/mbed,autopulated\/mbed,al177\/mbed,mikaleppanen\/mbed-os,infinnovation\/mbed-os,Shengliang\/mbed,getopenmono\/mbed,RonEld\/mbed,iriark01\/mbed-drivers,mnlipp\/mbed,Sweet-Peas\/mbed,mmorenobarm\/mbed-os,jrjang\/mbed,pi19404\/mbed,mikaleppanen\/mbed-os,kpurusho\/mbed,ban4jp\/mbed,Tiryoh\/mbed,FranklyDev\/mbed,geky\/mbed,infinnovation\/mbed-os,xcrespo\/mbed,theotherjimmy\/mbed,mnlipp\/mbed,adustm\/mbed,pbrook\/mbed,mikaleppanen\/mbed-os,xcrespo\/mbed,Marcomissyou\/mbed,betzw\/mbed-os,adustm\/mbed,theotherjimmy\/mbed,jrjang\/mbed,HeadsUpDisplayInc\/mbed,masaohamanaka\/mbed,YarivCol\/mbed-os,svogl\/mbed-os,fpiot\/mbed-ats,ban4jp\/mbed,Shengliang\/mbed,EmuxEvans\/mbed,GustavWi\/mbed,mnlipp\/mbed,kl-cruz\/mbed-os,Marcomissyou\/mbed,larks\/mbed,c1728p9\/mbed-os,JasonHow44\/mbed,bikeNomad\/mbed,jferreir\/mbed,bikeNomad\/mbed,bulislaw\/mbed-os,geky\/mbed,autopulated\/mbed,tung7970\/mbed-os-1,jrjang\/mbed,Sweet-Peas\/mbed,andcor02\/mbed-os,struempelix\/mbed,autopulated\/mbed,bremoran\/mbed-drivers,jamesadevine\/mbed,al177\/mbed,NordicSemiconductor\/mbed,kl-cruz\/mbed-os,jferreir\/mbed,pbrook\/mbed,jamesadevine\/mbed,theotherjimmy\/mbed,adamgreen\/mbed,jpbrucker\/mbed,bcostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,andcor02\/mbed-os,andreaslarssonublox\/mbed,fahhem\/mbed-os,CalSol\/mbed,c1728p9\/mbed-os,arostm\/mbed-os,sam-geek\/mbed,RonEld\/mbed,wodji\/mbed,brstew\/MBED-BUILD,Marcomissyou\/mbed,FranklyDev\/mbed,bulislaw\/mbed-os,logost\/mbed,adamgreen\/mbed,pradeep-gr\/mbed-os5-onsemi,YarivCol\/mbed-os,Willem23\/mbed,mikaleppanen\/mbed-os,adamgreen\/mbed,hwfwgrp\/mbed,alertby\/mbed,bcostm\/mbed-os,mazimkhan\/mbed-os,CalSol\/mbed,Willem23\/mbed,karsev\/mbed-os,catiedev\/mbed-os,infinnovation\/mbed-os,dbestm\/mbed,ban4jp\/mbed,dbestm\/mbed,Archcady\/mbed-os,nRFMesh\/mbed-os,naves-thiago\/mbed-midi,svastm\/mbed,DanKupiniak\/mbed,struempelix\/mbed,pi19404\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,fpiot\/mbed-ats,cvtsi2sd\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,HeadsUpDisplayInc\/mbed,kjbracey-arm\/mbed,jeremybrodt\/mbed,wodji\/mbed,hwfwgrp\/mbed,fanghuaqi\/mbed,RonEld\/mbed,hwfwgrp\/mbed,mbedmicro\/mbed,xcrespo\/mbed,rosterloh\/mbed,screamerbg\/mbed,betzw\/mbed-os,pbrook\/mbed,ARM-software\/mbed-beetle,pedromes\/mbed,j-greffe\/mbed-os,NXPmicro\/mbed,Tiryoh\/mbed,Archcady\/mbed-os,masaohamanaka\/mbed,arostm\/mbed-os,maximmbed\/mbed,fvincenzo\/mbed-os,jeremybrodt\/mbed,cvtsi2sd\/mbed-os,bentwire\/mbed,betzw\/mbed-os,Shengliang\/mbed,xcrespo\/mbed,betzw\/mbed-os,infinnovation\/mbed-os,NXPmicro\/mbed,rgrover\/mbed,catiedev\/mbed-os,RonEld\/mbed,YarivCol\/mbed-os,bentwire\/mbed,K4zuki\/mbed,GustavWi\/mbed,fanghuaqi\/mbed,jferreir\/mbed,andcor02\/mbed-os,arostm\/mbed-os,alertby\/mbed,adustm\/mbed,JasonHow44\/mbed,EmuxEvans\/mbed,bremoran\/mbed-drivers,K4zuki\/mbed,DanKupiniak\/mbed,c1728p9\/mbed-os,Tiryoh\/mbed,larks\/mbed,arostm\/mbed-os,YarivCol\/mbed-os,kpurusho\/mbed,svogl\/mbed-os,jamesadevine\/mbed,brstew\/MBED-BUILD,jpbrucker\/mbed,maximmbed\/mbed,HeadsUpDisplayInc\/mbed,kjbracey-arm\/mbed,infinnovation\/mbed-os,dbestm\/mbed,Sweet-Peas\/mbed,screamerbg\/mbed,nabilbendafi\/mbed,CalSol\/mbed,al177\/mbed,maximmbed\/mbed,tung7970\/mbed-os,FranklyDev\/mbed,wodji\/mbed,Timmmm\/mbed,NordicSemiconductor\/mbed,cvtsi2sd\/mbed-os,svastm\/mbed,autopulated\/mbed,pi19404\/mbed,netzimme\/mbed-os,tung7970\/mbed-os-1,andreaslarssonublox\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,j-greffe\/mbed-os,struempelix\/mbed,NitinBhaskar\/mbed,fvincenzo\/mbed-os,rosterloh\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,logost\/mbed,Sweet-Peas\/mbed,getopenmono\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,bentwire\/mbed,pbrook\/mbed,andreaslarssonublox\/mbed,NordicSemiconductor\/mbed,Shengliang\/mbed,jeremybrodt\/mbed,infinnovation\/mbed-os,iriark01\/mbed-drivers,struempelix\/mbed,adustm\/mbed,maximmbed\/mbed,kl-cruz\/mbed-os,netzimme\/mbed-os,monkiineko\/mbed-os,nvlsianpu\/mbed,hwfwgrp\/mbed,Timmmm\/mbed,larks\/mbed,pedromes\/mbed,jpbrucker\/mbed,EmuxEvans\/mbed,bentwire\/mbed,svogl\/mbed-os,karsev\/mbed-os,fahhem\/mbed-os,karsev\/mbed-os,ban4jp\/mbed,NitinBhaskar\/mbed,andcor02\/mbed-os,monkiineko\/mbed-os,jamesadevine\/mbed,nvlsianpu\/mbed,bcostm\/mbed-os,RonEld\/mbed,pradeep-gr\/mbed-os5-onsemi,pi19404\/mbed,ban4jp\/mbed,Shengliang\/mbed,svogl\/mbed-os,Marcomissyou\/mbed,autopulated\/mbed,bulislaw\/mbed-os,dbestm\/mbed,ryankurte\/mbed-os,jeremybrodt\/mbed,mazimkhan\/mbed-os,netzimme\/mbed-os,screamerbg\/mbed,tung7970\/mbed-os,kl-cruz\/mbed-os,DanKupiniak\/mbed,fvincenzo\/mbed-os,bikeNomad\/mbed,nabilbendafi\/mbed,screamerbg\/mbed,masaohamanaka\/mbed,jamesadevine\/mbed,alertby\/mbed,nabilbendafi\/mbed,tung7970\/mbed-os,NXPmicro\/mbed,bcostm\/mbed-os,JasonHow44\/mbed,pedromes\/mbed,alertby\/mbed,kpurusho\/mbed,JasonHow44\/mbed,jpbrucker\/mbed,K4zuki\/mbed,EmuxEvans\/mbed,j-greffe\/mbed-os,GustavWi\/mbed,kpurusho\/mbed,al177\/mbed,kl-cruz\/mbed-os,DanKupiniak\/mbed,fvincenzo\/mbed-os,devanlai\/mbed,JasonHow44\/mbed,mikaleppanen\/mbed-os,bikeNomad\/mbed,ARM-software\/mbed-beetle,mmorenobarm\/mbed-os,naves-thiago\/mbed-midi,theotherjimmy\/mbed,kjbracey-arm\/mbed,brstew\/MBED-BUILD,andcor02\/mbed-os,GustavWi\/mbed,fpiot\/mbed-ats,GustavWi\/mbed,mazimkhan\/mbed-os,pi19404\/mbed,Willem23\/mbed,nvlsianpu\/mbed,devanlai\/mbed,mbedmicro\/mbed,fahhem\/mbed-os,c1728p9\/mbed-os,adustm\/mbed,dbestm\/mbed,hwfwgrp\/mbed,pi19404\/mbed,Willem23\/mbed,catiedev\/mbed-os,CalSol\/mbed,al177\/mbed,devanlai\/mbed,jeremybrodt\/mbed,bentwire\/mbed,pbrook\/mbed,andreaslarssonublox\/mbed,j-greffe\/mbed-os,karsev\/mbed-os,screamerbg\/mbed,ARM-software\/mbed-beetle,arostm\/mbed-os,ARM-software\/mbed-beetle,screamerbg\/mbed,Archcady\/mbed-os,Timmmm\/mbed,tung7970\/mbed-os,NitinBhaskar\/mbed,geky\/mbed,Tiryoh\/mbed,netzimme\/mbed-os,adamgreen\/mbed,sam-geek\/mbed,c1728p9\/mbed-os,wodji\/mbed,jferreir\/mbed,fanghuaqi\/mbed,fanghuaqi\/mbed,pbrook\/mbed,NXPmicro\/mbed,pedromes\/mbed,sam-geek\/mbed,fpiot\/mbed-ats,logost\/mbed,wodji\/mbed,NordicSemiconductor\/mbed,NitinBhaskar\/mbed,sg-\/mbed-drivers,devanlai\/mbed,betzw\/mbed-os,bcostm\/mbed-os,bulislaw\/mbed-os,cvtsi2sd\/mbed-os,jrjang\/mbed,Archcady\/mbed-os,brstew\/MBED-BUILD,Tiryoh\/mbed,rgrover\/mbed,HeadsUpDisplayInc\/mbed,geky\/mbed,nabilbendafi\/mbed,ryankurte\/mbed-os,Willem23\/mbed,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,mazimkhan\/mbed-os,catiedev\/mbed-os,naves-thiago\/mbed-midi,karsev\/mbed-os,jrjang\/mbed,naves-thiago\/mbed-midi,mazimkhan\/mbed-os,geky\/mbed,EmuxEvans\/mbed,0xc0170\/mbed-drivers,svogl\/mbed-os,j-greffe\/mbed-os,nRFMesh\/mbed-os,logost\/mbed,nRFMesh\/mbed-os,0xc0170\/mbed-drivers,svastm\/mbed,fvincenzo\/mbed-os,rosterloh\/mbed,CalSol\/mbed,svogl\/mbed-os,struempelix\/mbed,alertby\/mbed,netzimme\/mbed-os,Marcomissyou\/mbed,sam-geek\/mbed,jrjang\/mbed,andcor02\/mbed-os,JasonHow44\/mbed,c1728p9\/mbed-os,pradeep-gr\/mbed-os5-onsemi,larks\/mbed,adustm\/mbed,K4zuki\/mbed,mnlipp\/mbed,sam-geek\/mbed,maximmbed\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,andreaslarssonublox\/mbed,rgrover\/mbed,mmorenobarm\/mbed-os,fahhem\/mbed-os,theotherjimmy\/mbed,naves-thiago\/mbed-midi,FranklyDev\/mbed,mbedmicro\/mbed,jpbrucker\/mbed,bentwire\/mbed,Sweet-Peas\/mbed,Shengliang\/mbed,NXPmicro\/mbed,fpiot\/mbed-ats,mbedmicro\/mbed,ryankurte\/mbed-os,bulislaw\/mbed-os,struempelix\/mbed,ban4jp\/mbed,K4zuki\/mbed,devanlai\/mbed,brstew\/MBED-BUILD,ryankurte\/mbed-os","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC11XX\/TOOLCHAIN_GCC_ARM\/LPC1114.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC11XX\/TOOLCHAIN_GCC_ARM\/LPC1114.ld","new_contents":"\/* Linker script for mbed LPC1114 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K\n  RAM (rwx) :  ORIGIN = 0x100000C0, LENGTH = 0x0F40\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n\t\t. = 0x200;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for mbed LPC1114 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K\n  RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 2K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b956132ca87d2cc2fa20aaa929bdca538e642afa","subject":"zephyr: riscv: use __rom_region_size for image size","message":"zephyr: riscv: use __rom_region_size for image size\n\n_image_rom_size was renamed to __rom_region_size in v2.7.  We\nbackported this to our v2.6 branches, so switch the name ahead of time\nso we're prepared for the v2.7 uprev.\n\nBUG=b:198824039\nBRANCH=none\nTEST=compile hayato EC with zephyr v2.7\n\nSigned-off-by: Jack Rosenthal <d3f605bef1867f59845d4ce6e4f83b8dc9e4e0ae@chromium.org>\nChange-Id: Iae6e7008d729f77cd66ed1a35e93001511d9cea8\nReviewed-on: https:\/\/chromium-review.googlesource.com\/c\/chromiumos\/platform\/ec\/+\/3163562\nCommit-Queue: Denis Brockus <6b21e8190fb5e373363fb95271367073a16474ef@chromium.org>\nReviewed-by: Denis Brockus <6b21e8190fb5e373363fb95271367073a16474ef@chromium.org>\n","repos":"coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec","old_file":"zephyr\/linker\/image_size.ld","new_file":"zephyr\/linker\/image_size.ld","new_contents":"\/* Copyright 2021 The Chromium OS Authors. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n *\/\n\n#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_R) || \\\n\tdefined(CONFIG_CPU_CORTEX_A)\n__image_size = _flash_used;\n#elif defined(CONFIG_RISCV)\n__image_size = __rom_region_size;\n#else\n\/*\n * Intentionally set to 0. Some components, such as EFS2, need this value.\n * Having it be 0 will make it easier to find and add new cores.\n *\/\n__image_size = 0;\n#endif\n","old_contents":"\/* Copyright 2021 The Chromium OS Authors. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n *\/\n\n#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_R) || \\\n\tdefined(CONFIG_CPU_CORTEX_A)\n__image_size = _flash_used;\n#elif defined(CONFIG_RISCV)\n__image_size = _image_rom_size;\n#else\n\/*\n * Intentionally set to 0. Some components, such as EFS2, need this value.\n * Having it be 0 will make it easier to find and add new cores.\n *\/\n__image_size = 0;\n#endif\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"a415a58db5dd76910322f2e808057d20b8cfccf2","subject":"fix(esp8266): Update link parameter for MR !792","message":"fix(esp8266): Update link parameter for MR !792\n","repos":"espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK","old_file":"components\/esp8266\/ld\/esp8266.ld","new_file":"components\/esp8266\/ld\/esp8266.ld","new_contents":"\/* user1.bin @ 0x1000, user2.bin @ 0x10000 *\/\n\n\/* Flash Map (1024KB + 1024KB), support 2MB\/4MB SPI Flash *\/\n\/* |..|........................|.....|.....|..|........................|.....|....|                        *\/\n\/* ^  ^                        ^     ^     ^  ^                        ^     ^                             *\/\n\/* |_boot start(0x0000)        |     |     |_pad start(0x100000)       |     |                             *\/\n\/*    |_user1 start(0x1000)    |_user1 end    |_user2 start(0x101000)  |_user2 end                         *\/\n\/*                                   |_system param symmetric area(0xfb000)  |_system param area(0x1fb000) *\/\n\n\/* NOTICE: *\/ \n\/* 1. You can change irom0 len, but MUST make sure user1 end not overlap system param symmetric area. *\/\n\/* 2. Space between user1 end and pad start can be used as user param area.                           *\/\n\/* 3. Space between user2 end and system param area can be used as user param area.                   *\/\n\/* 4. Don't change any other seg.                                                                     *\/\n\/* 5. user1.bin and user2.bin are same in this mode, so upgrade only need one of them.                *\/\n\n#include \"sdkconfig.h\"\n\nMEMORY\n{\n  dport0_0_seg :    org = 0x3FF00000, len = 0x10\n\n  \/* All .data\/.bss\/heap are in this segment. *\/\n  dram0_0_seg  :    org = 0x3FFE8000, len = 0x18000\n\n  \/* Functions which are critical should be put in this segment. *\/\n  iram1_0_seg  :    org = 0x40100000, len = CONFIG_SOC_IRAM_SIZE\n\n  \/* It is actually mapped to flash. *\/\n  irom0_0_seg  :    org = 0x40200010 + APP_OFFSET, len = APP_SIZE - 0x10\n\n  \/* RTC memory, persists over deep sleep. *\/\n  rtc_seg      :    org = 0x60001200, len = 0x200\n}\n","old_contents":"\/* user1.bin @ 0x1000, user2.bin @ 0x10000 *\/\n\n\/* Flash Map (1024KB + 1024KB), support 2MB\/4MB SPI Flash *\/\n\/* |..|........................|.....|.....|..|........................|.....|....|                        *\/\n\/* ^  ^                        ^     ^     ^  ^                        ^     ^                             *\/\n\/* |_boot start(0x0000)        |     |     |_pad start(0x100000)       |     |                             *\/\n\/*    |_user1 start(0x1000)    |_user1 end    |_user2 start(0x101000)  |_user2 end                         *\/\n\/*                                   |_system param symmetric area(0xfb000)  |_system param area(0x1fb000) *\/\n\n\/* NOTICE: *\/ \n\/* 1. You can change irom0 len, but MUST make sure user1 end not overlap system param symmetric area. *\/\n\/* 2. Space between user1 end and pad start can be used as user param area.                           *\/\n\/* 3. Space between user2 end and system param area can be used as user param area.                   *\/\n\/* 4. Don't change any other seg.                                                                     *\/\n\/* 5. user1.bin and user2.bin are same in this mode, so upgrade only need one of them.                *\/\n\n#include \"sdkconfig.h\"\n\nMEMORY\n{\n  dport0_0_seg :    org = 0x3FF00000, len = 0x10\n\n  \/* All .data\/.bss\/heap are in this segment. *\/\n  dram0_0_seg  :    org = 0x3FFE8000, len = 0x18000\n\n  \/* Functions which are critical should be put in this segment. *\/\n  iram1_0_seg  :    org = 0x40100000, len = CONFIG_SOC_IRAM_SIZE\n\n  \/* It is actually mapped to flash. *\/\n  irom0_0_seg  :    org = 0x40200010 + APP_OFFSET, len = APP_SIZE - 0x10 - APP_OFFSET\n\n  \/* RTC memory, persists over deep sleep. *\/\n  rtc_seg      :    org = 0x60001200, len = 0x200\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"0d2553a028b38abbe176fbdb7c79655b42835294","subject":"Removed test code","message":"Removed test code\n","repos":"ve3wwg\/teensy3_lib,ve3wwg\/teensy3_lib","old_file":"teensy3\/mk20dx256_sbrk.ld","new_file":"teensy3\/mk20dx256_sbrk.ld","new_contents":"\/* Teensyduino Core Library\n * http:\/\/www.pjrc.com\/teensy\/\n * Copyright (c) 2013 PJRC.COM, LLC.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * 1. The above copyright notice and this permission notice shall be \n * included in all copies or substantial portions of the Software.\n *\n * 2. If the Software is incorporated into a build system that allows \n * selection among a list of target devices, then similar target\n * devices manufactured by PJRC.COM must be included in the list of\n * target devices and selectable in the same manner.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\/\n\nMEMORY\n{\n\tFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\n\tRAM  (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 64K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 16K;\t\/* Just for testing link *\/\n_minimum_heap_size =  16K;\n\n\/* INCLUDE common.ld *\/\n\n\/* Teensyduino Core Library\n * http:\/\/www.pjrc.com\/teensy\/\n * Copyright (c) 2013 PJRC.COM, LLC.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * 1. The above copyright notice and this permission notice shall be \n * included in all copies or substantial portions of the Software.\n *\n * 2. If the Software is incorporated into a build system that allows \n * selection among a list of target devices, then similar target\n * devices manufactured by PJRC.COM must be included in the list of\n * target devices and selectable in the same manner.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\/\n\nSECTIONS\n{\n\t.text : {\n\t\t. = 0;\n\t\tKEEP(*(.vectors))\n\t\t*(.startup*)\n\t\t\/* TODO: does linker detect startup overflow onto flashconfig? *\/\n\t\t. = 0x400;\n\t\tKEEP(*(.flashconfig*))\n\t\t*(.text*)\n\t\t*(.rodata*)\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init))\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\t} > FLASH = 0xFF\n\n\t.ARM.exidx : {\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > FLASH\n\t_etext = .;\n\n\t.usbdescriptortable (NOLOAD) : {\n\t\t\/* . = ORIGIN(RAM); *\/\n\t\t. = ALIGN(512);\n\t\t*(.usbdescriptortable*)\n\t} > RAM\n\n\t.dmabuffers (NOLOAD) : {\n\t\t. = ALIGN(4);\n\t\t*(.dmabuffers*)\n\t} > RAM\n\n\t.usbbuffers (NOLOAD) : {\n\t\t. = ALIGN(4);\n\t\t*(.usbbuffers*)\n\t} > RAM\n\n\t.data : AT (_etext) {\n\t\t. = ALIGN(4);\n\t\t_sdata = .; \n\t\t*(.data*)\n\t\t. = ALIGN(4);\n\t\t_edata = .; \n\t} > RAM\n\n\t\/*\n\t * _staticfs is the place in flash where the static filesystem which\n\t * is concatenated to the .hex file will wind up.\n\t *\/\n\t_staticfs = LOADADDR(.data) + SIZEOF(.data);\n\n\t.noinit (NOLOAD) : {\n\t\t*(.noinit*)\n\t} > RAM\n\n\t.bss : {\n\t\t. = ALIGN(4);\n\t\t_sbss = .; \n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t\t__bss_end = .;\n\t} > RAM\n\n\t\/* this is to define the start of the heap, and make sure we have a minimum size *\/\n\t.heap :\n\t{\n\t    . = ALIGN(4);\n\t    _heap_start = .;    \/* define a global symbol at heap start *\/\n\t    end = _heap_start;\t\/* wwg: for sbrk() *\/\n\t    . = . + _minimum_heap_size;\n\t} >RAM\n\n\t\/* this just checks there is enough RAM for the stack *\/\n\t.stack :\n\t{\n\t    . = ALIGN(4);\n            _sstack = .;\n\t    . = . + _minimum_stack_size;\n\t    . = ALIGN(4);\n\t} >RAM\n\n\t_estack = ORIGIN(RAM) + 64 * 1024;\n}\n","old_contents":"\/* Teensyduino Core Library\n * http:\/\/www.pjrc.com\/teensy\/\n * Copyright (c) 2013 PJRC.COM, LLC.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * 1. The above copyright notice and this permission notice shall be \n * included in all copies or substantial portions of the Software.\n *\n * 2. If the Software is incorporated into a build system that allows \n * selection among a list of target devices, then similar target\n * devices manufactured by PJRC.COM must be included in the list of\n * target devices and selectable in the same manner.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\/\n\nMEMORY\n{\n\tFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\n\tRAM  (rwx) : ORIGIN = 0x1FFF8000, LENGTH = 64K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 16K;\t\/* Just for testing link *\/\n_minimum_heap_size =  16K;\n\n\/* INCLUDE common.ld *\/\n\n\/* Teensyduino Core Library\n * http:\/\/www.pjrc.com\/teensy\/\n * Copyright (c) 2013 PJRC.COM, LLC.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * 1. The above copyright notice and this permission notice shall be \n * included in all copies or substantial portions of the Software.\n *\n * 2. If the Software is incorporated into a build system that allows \n * selection among a list of target devices, then similar target\n * devices manufactured by PJRC.COM must be included in the list of\n * target devices and selectable in the same manner.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\/\n\nSECTIONS\n{\n\t.text : {\n\t\t. = 0;\n\t\tKEEP(*(.vectors))\n\t\t*(.startup*)\n\t\t\/* TODO: does linker detect startup overflow onto flashconfig? *\/\n\t\t. = 0x400;\n\t\tKEEP(*(.flashconfig*))\n\t\t*(.text*)\n\t\t*(.rodata*)\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init))\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\t} > FLASH = 0xFF\n\n\t.ARM.exidx : {\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > FLASH\n\t_etext = .;\n\n\t.usbdescriptortable (NOLOAD) : {\n\t\t\/* . = ORIGIN(RAM); *\/\n\t\t. = ALIGN(512);\n\t\t*(.usbdescriptortable*)\n\t} > RAM\n\n\t.dmabuffers (NOLOAD) : {\n\t\t. = ALIGN(4);\n\t\t*(.dmabuffers*)\n\t} > RAM\n\n\t.usbbuffers (NOLOAD) : {\n\t\t. = ALIGN(4);\n\t\t*(.usbbuffers*)\n\t} > RAM\n\n\t.data : AT (_etext) {\n\t\t. = ALIGN(4);\n\t\t_sdata = .; \n\t\t*(.data*)\n\t\t. = ALIGN(4);\n\t\t_edata = .; \n\t} > RAM\n\n\t\/*\n\t * _staticfs is the place in flash where the static filesystem which\n\t * is concatenated to the .hex file will wind up.\n\t *\/\n\t_staticfs = LOADADDR(.data) + SIZEOF(.data);\n\n\t.noinit (NOLOAD) : {\n\t\t*(.noinit*)\n\t} > RAM\n\n\t.bss : {\n\t\t. = ALIGN(4);\n\t\t_sbss = .; \n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t\t__bss_end = .;\n\t} > RAM\n\n\t\/* this is to define the start of the heap, and make sure we have a minimum size *\/\n\t.heap :\n\t{\n\t    . = ALIGN(4);\n\t    _heap_start = .;    \/* define a global symbol at heap start *\/\n\t    end = _heap_start;\t\/* wwg: for sbrk() *\/\n\t    . = . + _minimum_heap_size;\n\t} >RAM\n\n\t\/* this just checks there is enough RAM for the stack *\/\n\t.stack :\n\t{\n\t    . = ALIGN(4);\n            _sstack = .;\n\t    . = . + _minimum_stack_size;\n\t    . = ALIGN(4);\n\t} >RAM\n\n\t_test_estack = ORIGIN(RAM) + LENGTH(RAM);\n\t_estack = ORIGIN(RAM) + 64 * 1024;\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"f158c30a95664895c7fd562d9bcc1cadd8b30e13","subject":"Fix linker file for STM32F746","message":"Fix linker file for STM32F746\n\n- BSS didn't fit on ram3, moved to ram1\n\nSigned-off-by: Jos\u00e9 Sim\u00f5es <1616ff7a83d123f98f8f38fa2524eab406644781@eclo.solutions>\n","repos":"Eclo\/nf-interpreter,nanoframework\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter,Eclo\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter,nanoframework\/nf-interpreter","old_file":"targets\/CMSIS-OS\/ChibiOS\/ST_NUCLEO144_F746ZG\/nanoCLR\/STM32F746xG_CLR-DEBUG.ld","new_file":"targets\/CMSIS-OS\/ChibiOS\/ST_NUCLEO144_F746ZG\/nanoCLR\/STM32F746xG_CLR-DEBUG.ld","new_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n\/*\n * STM32F746xG generic setup.\n * \n * RAM0 - Data, Heap.\n * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.\n *\n * Notes:\n * BSS is placed in DTCM RAM in order to simplify DMA buffers management.\n *\/\nMEMORY\n{\n    flash       : org = 0x08010000, len = 1M - 32k - 32k - 512k     \/* flash size less the space reserved for nanoBooter, configuration block and application deployment*\/\n    flash_itcm  : org = 0x00210000, len = 1M - 32k - 32k - 512k\n    config      : org = 0x08008000, len = 32k                       \/* space reserved for configuration block *\/\n    deployment  : org = 0x08080000, len = 512k                      \/* space reserved for application deployment *\/\n    ramvt       : org = 0x00000000, len = 0                         \/* initial RAM address is reserved for a copy of the vector table *\/\n    ram0        : org = 0x20010000, len = 256k                      \/* SRAM1 + SRAM2 *\/\n    ram1        : org = 0x20010000, len = 240k                      \/* SRAM1 *\/\n    ram2        : org = 0x2004C000, len = 16k                       \/* SRAM2 *\/\n    ram3        : org = 0x20000000, len = 64k                       \/* DTCM-RAM *\/\n    ram4        : org = 0x00000000, len = 16k                       \/* ITCM-RAM *\/\n    ram5        : org = 0x40024000, len = 4k                        \/* BCKP SRAM *\/\n    ram6        : org = 0x00000000, len = 0\n    ram7        : org = 0x00000000, len = 0\n}\n\n\/* For each data\/text section two region are defined, a virtual region\n   and a load region (_LMA suffix).*\/\n\n\/* Flash region to be used for exception vectors.*\/\nREGION_ALIAS(\"VECTORS_FLASH\", flash_itcm);\nREGION_ALIAS(\"VECTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for constructors and destructors.*\/\nREGION_ALIAS(\"XTORS_FLASH\", flash_itcm);\nREGION_ALIAS(\"XTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for code text.*\/\nREGION_ALIAS(\"TEXT_FLASH\", flash_itcm);\nREGION_ALIAS(\"TEXT_FLASH_LMA\", flash);\n\n\/* Flash region to be used for read only data.*\/\nREGION_ALIAS(\"RODATA_FLASH\", flash);\nREGION_ALIAS(\"RODATA_FLASH_LMA\", flash);\n\n\/* Flash region to be used for various.*\/\nREGION_ALIAS(\"VARIOUS_FLASH\", flash_itcm);\nREGION_ALIAS(\"VARIOUS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for RAM(n) initialization data.*\/\nREGION_ALIAS(\"RAM_INIT_FLASH_LMA\", flash);\n\n\/* RAM region to be used for Main stack. This stack accommodates the processing\n   of all exceptions and interrupts.*\/\nREGION_ALIAS(\"MAIN_STACK_RAM\", ram3);\n\n\/* RAM region to be used for the process stack. This is the stack used by\n   the main() function.*\/\nREGION_ALIAS(\"PROCESS_STACK_RAM\", ram3);\n\n\/* RAM region to be used for data segment.*\/\nREGION_ALIAS(\"DATA_RAM\", ram0);\nREGION_ALIAS(\"DATA_RAM_LMA\", flash);\n\n\/* RAM region to be used for BSS segment.*\/\nREGION_ALIAS(\"BSS_RAM\", ram1);\n\n\/* RAM region to be used for the default heap.*\/\nREGION_ALIAS(\"HEAP_RAM\", ram3);\n\n\/* RAM region to be used for the nanoFramework CLR managed heap.*\/\nREGION_ALIAS(\"CLR_MANAGED_HEAP_RAM\", ram0);\n\n\/* rules inclusion.*\/\nINCLUDE rules_stacks.ld\n\n\/*===========================================================================*\/\n\/* Custom sections for STM32F7xx.                                            *\/\n\/*===========================================================================*\/\n\n\/* RAM region to be used for nocache segment.*\/\nREGION_ALIAS(\"NOCACHE_RAM\", ram3);\n\n\/* RAM region to be used for eth segment.*\/\nREGION_ALIAS(\"ETH_RAM\", ram3);\n\nSECTIONS\n{\n    \/* Special section for non cache-able areas.*\/\n    .nocache (NOLOAD) : ALIGN(4)\n    {\n        __nocache_base__ = .;\n        *(.nocache)\n        *(.nocache.*)\n        *(.bss.__nocache_*)\n        . = ALIGN(4);\n        __nocache_end__ = .;\n    } > NOCACHE_RAM\n\n    \/* Special section for Ethernet DMA non cache-able areas.*\/\n    .eth (NOLOAD) : ALIGN(4)\n    {\n        __eth_base__ = .;\n        *(.eth)\n        *(.eth.*)\n        *(.bss.__eth_*)\n        . = ALIGN(4);\n        __eth_end__ = .;\n    } > ETH_RAM\n}\n\n\/* Code rules inclusion.*\/\nINCLUDE rules_code.ld\n\n\/* Data rules inclusion.*\/\nINCLUDE rules_data.ld\n\n\/* nanoCLR rules inclusion.*\/\nINCLUDE rules_clr.ld\n","old_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n\/*\n * STM32F746xG generic setup.\n * \n * RAM0 - Data, Heap.\n * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.\n *\n * Notes:\n * BSS is placed in DTCM RAM in order to simplify DMA buffers management.\n *\/\nMEMORY\n{\n    flash       : org = 0x08010000, len = 1M - 32k - 32k - 512k     \/* flash size less the space reserved for nanoBooter, configuration block and application deployment*\/\n    flash_itcm  : org = 0x00210000, len = 1M - 32k - 32k - 512k\n    config      : org = 0x08008000, len = 32k                       \/* space reserved for configuration block *\/\n    deployment  : org = 0x08080000, len = 512k                      \/* space reserved for application deployment *\/\n    ramvt       : org = 0x00000000, len = 0                         \/* initial RAM address is reserved for a copy of the vector table *\/\n    ram0        : org = 0x20010000, len = 256k                      \/* SRAM1 + SRAM2 *\/\n    ram1        : org = 0x20010000, len = 240k                      \/* SRAM1 *\/\n    ram2        : org = 0x2004C000, len = 16k                       \/* SRAM2 *\/\n    ram3        : org = 0x20000000, len = 64k                       \/* DTCM-RAM *\/\n    ram4        : org = 0x00000000, len = 16k                       \/* ITCM-RAM *\/\n    ram5        : org = 0x40024000, len = 4k                        \/* BCKP SRAM *\/\n    ram6        : org = 0x00000000, len = 0\n    ram7        : org = 0x00000000, len = 0\n}\n\n\/* For each data\/text section two region are defined, a virtual region\n   and a load region (_LMA suffix).*\/\n\n\/* Flash region to be used for exception vectors.*\/\nREGION_ALIAS(\"VECTORS_FLASH\", flash_itcm);\nREGION_ALIAS(\"VECTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for constructors and destructors.*\/\nREGION_ALIAS(\"XTORS_FLASH\", flash_itcm);\nREGION_ALIAS(\"XTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for code text.*\/\nREGION_ALIAS(\"TEXT_FLASH\", flash_itcm);\nREGION_ALIAS(\"TEXT_FLASH_LMA\", flash);\n\n\/* Flash region to be used for read only data.*\/\nREGION_ALIAS(\"RODATA_FLASH\", flash);\nREGION_ALIAS(\"RODATA_FLASH_LMA\", flash);\n\n\/* Flash region to be used for various.*\/\nREGION_ALIAS(\"VARIOUS_FLASH\", flash_itcm);\nREGION_ALIAS(\"VARIOUS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for RAM(n) initialization data.*\/\nREGION_ALIAS(\"RAM_INIT_FLASH_LMA\", flash);\n\n\/* RAM region to be used for Main stack. This stack accommodates the processing\n   of all exceptions and interrupts.*\/\nREGION_ALIAS(\"MAIN_STACK_RAM\", ram3);\n\n\/* RAM region to be used for the process stack. This is the stack used by\n   the main() function.*\/\nREGION_ALIAS(\"PROCESS_STACK_RAM\", ram3);\n\n\/* RAM region to be used for data segment.*\/\nREGION_ALIAS(\"DATA_RAM\", ram0);\nREGION_ALIAS(\"DATA_RAM_LMA\", flash);\n\n\/* RAM region to be used for BSS segment.*\/\nREGION_ALIAS(\"BSS_RAM\", ram3);\n\n\/* RAM region to be used for the default heap.*\/\nREGION_ALIAS(\"HEAP_RAM\", ram3);\n\n\/* RAM region to be used for the nanoFramework CLR managed heap.*\/\nREGION_ALIAS(\"CLR_MANAGED_HEAP_RAM\", ram0);\n\n\/* rules inclusion.*\/\nINCLUDE rules_stacks.ld\n\n\/*===========================================================================*\/\n\/* Custom sections for STM32F7xx.                                            *\/\n\/*===========================================================================*\/\n\n\/* RAM region to be used for nocache segment.*\/\nREGION_ALIAS(\"NOCACHE_RAM\", ram3);\n\n\/* RAM region to be used for eth segment.*\/\nREGION_ALIAS(\"ETH_RAM\", ram3);\n\nSECTIONS\n{\n    \/* Special section for non cache-able areas.*\/\n    .nocache (NOLOAD) : ALIGN(4)\n    {\n        __nocache_base__ = .;\n        *(.nocache)\n        *(.nocache.*)\n        *(.bss.__nocache_*)\n        . = ALIGN(4);\n        __nocache_end__ = .;\n    } > NOCACHE_RAM\n\n    \/* Special section for Ethernet DMA non cache-able areas.*\/\n    .eth (NOLOAD) : ALIGN(4)\n    {\n        __eth_base__ = .;\n        *(.eth)\n        *(.eth.*)\n        *(.bss.__eth_*)\n        . = ALIGN(4);\n        __eth_end__ = .;\n    } > ETH_RAM\n}\n\n\/* Code rules inclusion.*\/\nINCLUDE rules_code.ld\n\n\/* Data rules inclusion.*\/\nINCLUDE rules_data.ld\n\n\/* nanoCLR rules inclusion.*\/\nINCLUDE rules_clr.ld\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7e65182674db108609cb49c51807522472338ae5","subject":"fxe.ld: fix ctor\/dtor table size detection","message":"fxe.ld: fix ctor\/dtor table size detection\n","repos":"fincs\/FeOS-v2,fincs\/FeOS-v2,fincs\/FeOS-v2,fincs\/FeOS-v2","old_file":"sdk\/bin\/fxe.ld","new_file":"sdk\/bin\/fxe.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(0x100005) \/* Shared | Read | Execute *\/;\n\trodata PT_LOAD FLAGS(0x100004) \/* Shared | Read *\/;\n\tshared PT_LOAD FLAGS(0x100006) \/* Shared | Read | Write *\/;\n\tdata   PT_LOAD FLAGS(0x6)      \/* Read | Write *\/;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\n\t. = __modulebase;\n\t__start__ = . ;\n\n\t.text ALIGN(4) :\n\t{\n\t\t\/* .init *\/\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(4);\n\n\t\t\/* .text *\/\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t\/* *(.imp.*) *\/ \/* Let ld do it for us and preserve section names *\/\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.stub)\n\t\t*(.gnu.warning)\n\t\t*(.gnu.linkonce.t*)\n\t\t. = ALIGN(4);\n\t} : code\n\n\t\/* =========== RODATA section =========== *\/\n\n\t. = ALIGN(0x1000);\n\n\t.rodata ALIGN(4) :\n\t{\n\t\t*(.rodata)\n\t\t*(.roda)\n\t\t*(.rodata.*)\n\t\t*all.rodata*(*)\n\t\t*(.gnu.linkonce.r*)\n\t\tSORT(CONSTRUCTORS)\n\t\t. = ALIGN(4);\n\t} : rodata\n\n\t.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } : rodata\n\tARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } : rodata\n\n\t.ctor_table ALIGN(4) :\n\t{\n\t\t__feos_init_array = . ;\n\t\tKEEP( *(SORT(.preinit_array.*)) )\n\t\tKEEP( *(.preinit_array) )\n\t\tKEEP( *(SORT(.init_array.*)) )\n\t\tKEEP( *(.init_array) )\n\t\tKEEP( *(SORT(.ctors.*)) )\n\t\tKEEP( *(.ctors) )\n\t\t__feos_init_array_end = . ;\n\t} : rodata\n\n\t.dtor_table ALIGN(4) :\n\t{\n\t\t__feos_fini_array = . ;\n\t\tKEEP( *(SORT(.dtors.*)) )\n\t\tKEEP( *(.dtors) )\n\t\tKEEP( *(SORT(.fini_array.*)) )\n\t\tKEEP( *(.fini_array) )\n\t\t__feos_fini_array_end = . ;\n\t} : rodata\n\n\t\/* =========== SHARED section =========== *\/\n\n\t. = ALIGN(0x1000);\n\n\t.sdata ALIGN(4) :\n\t{\n\t\t*(.sdata)\n\t\t. = ALIGN(4);\n\t} : shared\n\n\t.sbss ALIGN(4) :\n\t{\n\t\t*(.sbss)\n\t\t. = ALIGN(4);\n\t} : shared\n\n\t\/* =========== DATA section =========== *\/\n\n\t. = ALIGN(0x1000);\n\n\t.data ALIGN(4) :\n\t{\n\t\t*(.data)\n\t\t*(.data.*)\n\t\t*(.gnu.linkonce.d*)\n\t\tCONSTRUCTORS\n\t\t. = ALIGN(4);\n\t} : data\n\n\t.bss ALIGN(4) :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t\t*(.gnu.linkonce.b*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t} : data\n\n\t__end__ = ABSOLUTE(.) ;\n\n\t\/* ==================\n\t   ==== Metadata ====\n\t   ================== *\/\n\n\t\/* Discard sections that difficult post-processing *\/\n\t\/DISCARD\/ : { *(.group .comment .note) }\n\n\t\/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(0x100005) \/* Shared | Read | Execute *\/;\n\trodata PT_LOAD FLAGS(0x100004) \/* Shared | Read *\/;\n\tshared PT_LOAD FLAGS(0x100006) \/* Shared | Read | Write *\/;\n\tdata   PT_LOAD FLAGS(0x6)      \/* Read | Write *\/;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\n\t. = __modulebase;\n\t__start__ = . ;\n\n\t.text ALIGN(4) :\n\t{\n\t\t\/* .init *\/\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(4);\n\n\t\t\/* .text *\/\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t\/* *(.imp.*) *\/ \/* Let ld do it for us and preserve section names *\/\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.stub)\n\t\t*(.gnu.warning)\n\t\t*(.gnu.linkonce.t*)\n\t\t. = ALIGN(4);\n\t} : code\n\n\t\/* =========== RODATA section =========== *\/\n\n\t. = ALIGN(0x1000);\n\n\t.rodata ALIGN(4) :\n\t{\n\t\t*(.rodata)\n\t\t*(.roda)\n\t\t*(.rodata.*)\n\t\t*all.rodata*(*)\n\t\t*(.gnu.linkonce.r*)\n\t\tSORT(CONSTRUCTORS)\n\t\t. = ALIGN(4);\n\t} : rodata\n\n\t.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } : rodata\n\tARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } : rodata\n\n\t.ctor_table ALIGN(4) :\n\t{\n\t\t__feos_init_array =  . ;\n\t\tKEEP( *(SORT(.preinit_array.*)) )\n\t\tKEEP( *(.preinit_array) )\n\t\tKEEP( *(SORT(.init_array.*)) )\n\t\tKEEP( *(.init_array) )\n\t\tKEEP( *(SORT(.ctors.*)) )\n\t\tKEEP( *(.ctors) )\n\t\t__feos_init_size = (. - __feos_init_array) \/ 4 ;\n\t} : rodata\n\n\t.dtor_table ALIGN(4) :\n\t{\n\t\t__feos_fini_array =  . ;\n\t\tKEEP( *(SORT(.dtors.*)) )\n\t\tKEEP( *(.dtors) )\n\t\tKEEP( *(SORT(.fini_array.*)) )\n\t\tKEEP( *(.fini_array) )\n\t\t__feos_fini_size = (. - __feos_fini_array) \/ 4 ;\n\t} : rodata\n\n\t\/* =========== SHARED section =========== *\/\n\n\t. = ALIGN(0x1000);\n\n\t.sdata ALIGN(4) :\n\t{\n\t\t*(.sdata)\n\t\t. = ALIGN(4);\n\t} : shared\n\n\t.sbss ALIGN(4) :\n\t{\n\t\t*(.sbss)\n\t\t. = ALIGN(4);\n\t} : shared\n\n\t\/* =========== DATA section =========== *\/\n\n\t. = ALIGN(0x1000);\n\n\t.data ALIGN(4) :\n\t{\n\t\t*(.data)\n\t\t*(.data.*)\n\t\t*(.gnu.linkonce.d*)\n\t\tCONSTRUCTORS\n\t\t. = ALIGN(4);\n\t} : data\n\n\t.bss ALIGN(4) :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t\t*(.gnu.linkonce.b*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t} : data\n\n\t__end__ = ABSOLUTE(.) ;\n\n\t\/* ==================\n\t   ==== Metadata ====\n\t   ================== *\/\n\n\t\/* Discard sections that difficult post-processing *\/\n\t\/DISCARD\/ : { *(.group .comment .note) }\n\n\t\/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ba889eeb9e99500736a1aec38f38645a335bd5a1","subject":"bsp: fomu: fix linker script overlap","message":"bsp: fomu: fix linker script overlap\n\nThe end of the data section was overlapping the start of the bss.\n\nSigned-off-by: Sean Cross <d7e19930cc1f42c2d0781f4d9e6f1fe5891bf9cf@xobs.io>\n","repos":"hathach\/tinyusb,hathach\/tinyusb,hathach\/tinyusb","old_file":"hw\/bsp\/fomu\/fomu.ld","new_file":"hw\/bsp\/fomu\/fomu.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littleriscv\")\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nMEMORY {\n\tcsr : ORIGIN = 0x60000000, LENGTH = 0x01000000\n\tvexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100\n\tsram : ORIGIN = 0x10000000, LENGTH = 0x00020000\n\trom : ORIGIN = 0x2001a000, LENGTH = 0x00200000 - 0x1a000\n}\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(.text.start)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t_etext = .;\n\t} > rom\n\n\t.rodata :\n\t{\n\t\t. = ALIGN(4);\n\t\t_frodata = .;\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.rodata1)\n\t\t*(.srodata)\n\t\t. = ALIGN(4);\n\t\t_erodata = .;\n\t} > rom\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(4);\n\t\t_fdata = .;\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t\t_gp = ALIGN(16);\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.* .sdata2 .sdata2.*)\n\t\t. = ALIGN(16);\n\t\t_edata = .; \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss :\n\t{\n\t\t_fbss = .;\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t\t_end = .;\n        PROVIDE(end = .);\n\t} > sram\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","old_contents":"OUTPUT_FORMAT(\"elf32-littleriscv\")\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nMEMORY {\n\tcsr : ORIGIN = 0x60000000, LENGTH = 0x01000000\n\tvexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100\n\tsram : ORIGIN = 0x10000000, LENGTH = 0x00020000\n\trom : ORIGIN = 0x2001a000, LENGTH = 0x00200000 - 0x1a000\n}\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(.text.start)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t_etext = .;\n\t} > rom\n\n\t.rodata :\n\t{\n\t\t. = ALIGN(4);\n\t\t_frodata = .;\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.rodata1)\n\t\t*(.srodata)\n\t\t_erodata = .;\n\t} > rom\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(4);\n\t\t_fdata = .;\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t\t_gp = ALIGN(16);\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.* .sdata2 .sdata2.*)\n\t\t_edata = ALIGN(16); \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fbss = .;\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t\t_end = .;\n        PROVIDE(end = .);\n\t} > sram\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2445b4766153d2aab8afd598f529c4f10b418a73","subject":"Add aligned .got and .got.plt sections to linker script","message":"Add aligned .got and .got.plt sections to linker script\n","repos":"phil-opp\/blog_os,phil-opp\/blog_os,phil-opp\/blogOS,phil-opp\/blog_os,phil-opp\/blog_os,phil-opp\/blogOS","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/*\nCopyright 2015 Philipp Oppermann. See the README.md\nfile at the top-level directory of this distribution.\n\nLicensed under the Apache License, Version 2.0 <LICENSE-APACHE or\nhttp:\/\/www.apache.org\/licenses\/LICENSE-2.0> or the MIT license\n<LICENSE-MIT or http:\/\/opensource.org\/licenses\/MIT>, at your\noption. This file may not be copied, modified, or distributed\nexcept according to those terms.\n*\/\n\nENTRY(start)\n\nSECTIONS {\n  . = 1M;\n\n  .rodata :\n  {\n    \/* ensure that the multiboot header is at the beginning *\/\n    KEEP(*(.multiboot_header))\n    *(.rodata .rodata.*)\n    . = ALIGN(4K);\n  }\n\n  .text :\n  {\n    *(.text .text.*)\n    . = ALIGN(4K);\n  }\n\n  .data :\n  {\n    *(.data .data.*)\n    . = ALIGN(4K);\n  }\n\n  .bss :\n  {\n    *(.bss .bss.*)\n    . = ALIGN(4K);\n  }\n\n  .got :\n  {\n    *(.got)\n    . = ALIGN(4K);\n  }\n\n  .got.plt :\n  {\n    *(.got.plt)\n    . = ALIGN(4K);\n  }\n\n  .data.rel.ro : ALIGN(4K) {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n    . = ALIGN(4K);\n  }\n\n  .gcc_except_table : ALIGN(4K) {\n    *(.gcc_except_table)\n    . = ALIGN(4K);\n  }\n}\n","old_contents":"\/*\nCopyright 2015 Philipp Oppermann. See the README.md\nfile at the top-level directory of this distribution.\n\nLicensed under the Apache License, Version 2.0 <LICENSE-APACHE or\nhttp:\/\/www.apache.org\/licenses\/LICENSE-2.0> or the MIT license\n<LICENSE-MIT or http:\/\/opensource.org\/licenses\/MIT>, at your\noption. This file may not be copied, modified, or distributed\nexcept according to those terms.\n*\/\n\nENTRY(start)\n\nSECTIONS {\n  . = 1M;\n\n  .rodata :\n  {\n    \/* ensure that the multiboot header is at the beginning *\/\n    KEEP(*(.multiboot_header))\n    *(.rodata .rodata.*)\n    . = ALIGN(4K);\n  }\n\n  .text :\n  {\n    *(.text .text.*)\n    . = ALIGN(4K);\n  }\n\n  .data :\n  {\n    *(.data .data.*)\n    . = ALIGN(4K);\n  }\n\n  .bss :\n  {\n    *(.bss .bss.*)\n    . = ALIGN(4K);\n  }\n\n  .data.rel.ro : ALIGN(4K) {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n    . = ALIGN(4K);\n  }\n\n  .gcc_except_table : ALIGN(4K) {\n    *(.gcc_except_table)\n    . = ALIGN(4K);\n  }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8d8d6d9a6a088777fdac0cc33d0045decf081556","subject":"riscv: linker: fix PMP support on non-XIP system.","message":"riscv: linker: fix PMP support on non-XIP system.\n\nOn non-XIP system, RAM region overlaps ROM region which cause PMP region\noverlapping. Padding RAM region by adding a output section to update\nthe next free address of RAM region.\n\nSigned-off-by: Jim Shu <1635390bb889c4cdee38f53a57b0915ac07d9bd9@andestech.com>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"aa7a55b6ddab33d4c876b14124a16dc72afce539","subject":"Update LPC1768.ld linker script to work with net stack.","message":"Update LPC1768.ld linker script to work with net stack.\n\nThe original script assigned memory ranges to USB_RAM and ETH_RAM but\nit never placed any section data in those regions.  I added clauses\ntowards the bottom of the script to place data that the programmer\nhas marked for the AHBSRAM0 and AHBSRAM1 sections into these regions\nof RAM.  Previously the data destined for these sections was being\nplaced in the lower 32K RAM bank and overflowing it at link time.\n\nI also added a few Image$$ linker symbols to mimic those used by the\nonline compiler.  I have had samples in the past which took advantage\nof these to display static memory statistics for each SRAM region.\n\nI also changed LENGTH=0x7F38 to LENGTH=(32K - 0xC8) to make it more\nconsistent with the sizing of the other regions in this script which\nuse human readable K sizing information.  The 0xC8 subtraction reflects\nthe starting offset of 0xC8 for this region.\n","repos":"pedromes\/mbed,NordicSemiconductor\/mbed,iriark01\/mbed-drivers,fpiot\/mbed-ats,pradeep-gr\/mbed-os5-onsemi,fvincenzo\/mbed-os,Shengliang\/mbed,pi19404\/mbed,catiedev\/mbed-os,DanKupiniak\/mbed,RonEld\/mbed,kpurusho\/mbed,bulislaw\/mbed-os,getopenmono\/mbed,adustm\/mbed,rosterloh\/mbed,netzimme\/mbed-os,dbestm\/mbed,netzimme\/mbed-os,netzimme\/mbed-os,fanghuaqi\/mbed,K4zuki\/mbed,Tiryoh\/mbed,Archcady\/mbed-os,al177\/mbed,pradeep-gr\/mbed-os5-onsemi,naves-thiago\/mbed-midi,YarivCol\/mbed-os,adamgreen\/mbed,nabilbendafi\/mbed,cvtsi2sd\/mbed-os,bentwire\/mbed,sam-geek\/mbed,fahhem\/mbed-os,HeadsUpDisplayInc\/mbed,tung7970\/mbed-os-1,mikaleppanen\/mbed-os,nabilbendafi\/mbed,hwfwgrp\/mbed,mikaleppanen\/mbed-os,adustm\/mbed,kjbracey-arm\/mbed,K4zuki\/mbed,fpiot\/mbed-ats,kl-cruz\/mbed-os,dbestm\/mbed,RonEld\/mbed,jpbrucker\/mbed,jpbrucker\/mbed,jrjang\/mbed,Timmmm\/mbed,jamesadevine\/mbed,JasonHow44\/mbed,al177\/mbed,Sweet-Peas\/mbed,NXPmicro\/mbed,struempelix\/mbed,RonEld\/mbed,j-greffe\/mbed-os,al177\/mbed,andreaslarssonublox\/mbed,fanghuaqi\/mbed,al177\/mbed,cvtsi2sd\/mbed-os,RonEld\/mbed,j-greffe\/mbed-os,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,screamerbg\/mbed,andcor02\/mbed-os,Sweet-Peas\/mbed,nvlsianpu\/mbed,getopenmono\/mbed,adamgreen\/mbed,mmorenobarm\/mbed-os,svastm\/mbed,tung7970\/mbed-os,geky\/mbed,svogl\/mbed-os,rgrover\/mbed,jrjang\/mbed,Tiryoh\/mbed,nvlsianpu\/mbed,jrjang\/mbed,Sweet-Peas\/mbed,struempelix\/mbed,tung7970\/mbed-os,ryankurte\/mbed-os,kl-cruz\/mbed-os,larks\/mbed,brstew\/MBED-BUILD,nRFMesh\/mbed-os,mazimkhan\/mbed-os,alertby\/mbed,xcrespo\/mbed,Archcady\/mbed-os,naves-thiago\/mbed-midi,bentwire\/mbed,betzw\/mbed-os,NXPmicro\/mbed,alertby\/mbed,Shengliang\/mbed,tung7970\/mbed-os,screamerbg\/mbed,rgrover\/mbed,HeadsUpDisplayInc\/mbed,devanlai\/mbed,arostm\/mbed-os,maximmbed\/mbed,fanghuaqi\/mbed,j-greffe\/mbed-os,nvlsianpu\/mbed,naves-thiago\/mbed-midi,bentwire\/mbed,ban4jp\/mbed,bentwire\/mbed,mazimkhan\/mbed-os,svogl\/mbed-os,naves-thiago\/mbed-midi,ARM-software\/mbed-beetle,autopulated\/mbed,xcrespo\/mbed,rgrover\/mbed,netzimme\/mbed-os,CalSol\/mbed,bulislaw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,jeremybrodt\/mbed,Tiryoh\/mbed,masaohamanaka\/mbed,andcor02\/mbed-os,kpurusho\/mbed,pi19404\/mbed,jamesadevine\/mbed,pbrook\/mbed,tung7970\/mbed-os-1,maximmbed\/mbed,getopenmono\/mbed,Shengliang\/mbed,alertby\/mbed,tung7970\/mbed-os-1,HeadsUpDisplayInc\/mbed,kl-cruz\/mbed-os,ban4jp\/mbed,NitinBhaskar\/mbed,theotherjimmy\/mbed,kpurusho\/mbed,bcostm\/mbed-os,c1728p9\/mbed-os,mazimkhan\/mbed-os,Sweet-Peas\/mbed,kl-cruz\/mbed-os,c1728p9\/mbed-os,GustavWi\/mbed,rosterloh\/mbed,NordicSemiconductor\/mbed,getopenmono\/mbed,wodji\/mbed,geky\/mbed,jferreir\/mbed,RonEld\/mbed,ban4jp\/mbed,autopulated\/mbed,dbestm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,dbestm\/mbed,struempelix\/mbed,cvtsi2sd\/mbed-os,fvincenzo\/mbed-os,adustm\/mbed,wodji\/mbed,mbedmicro\/mbed,nRFMesh\/mbed-os,rosterloh\/mbed,wodji\/mbed,mnlipp\/mbed,ban4jp\/mbed,tung7970\/mbed-os,svastm\/mbed,NitinBhaskar\/mbed,theotherjimmy\/mbed,nvlsianpu\/mbed,mnlipp\/mbed,kjbracey-arm\/mbed,j-greffe\/mbed-os,naves-thiago\/mbed-midi,nabilbendafi\/mbed,xcrespo\/mbed,fahhem\/mbed-os,betzw\/mbed-os,monkiineko\/mbed-os,nabilbendafi\/mbed,infinnovation\/mbed-os,catiedev\/mbed-os,pedromes\/mbed,logost\/mbed,bentwire\/mbed,karsev\/mbed-os,kjbracey-arm\/mbed,mnlipp\/mbed,arostm\/mbed-os,c1728p9\/mbed-os,jrjang\/mbed,andreaslarssonublox\/mbed,nRFMesh\/mbed-os,Tiryoh\/mbed,bentwire\/mbed,adustm\/mbed,larks\/mbed,karsev\/mbed-os,andreaslarssonublox\/mbed,tung7970\/mbed-os-1,GustavWi\/mbed,NXPmicro\/mbed,fahhem\/mbed-os,K4zuki\/mbed,EmuxEvans\/mbed,devanlai\/mbed,Willem23\/mbed,jferreir\/mbed,Archcady\/mbed-os,devanlai\/mbed,CalSol\/mbed,EmuxEvans\/mbed,CalSol\/mbed,bulislaw\/mbed-os,JasonHow44\/mbed,rosterloh\/mbed,monkiineko\/mbed-os,adamgreen\/mbed,monkiineko\/mbed-os,DanKupiniak\/mbed,Marcomissyou\/mbed,karsev\/mbed-os,c1728p9\/mbed-os,masaohamanaka\/mbed,ryankurte\/mbed-os,theotherjimmy\/mbed,jrjang\/mbed,jeremybrodt\/mbed,pedromes\/mbed,adustm\/mbed,fahhem\/mbed-os,sam-geek\/mbed,mbedmicro\/mbed,jamesadevine\/mbed,Archcady\/mbed-os,HeadsUpDisplayInc\/mbed,fahhem\/mbed-os,jpbrucker\/mbed,pbrook\/mbed,YarivCol\/mbed-os,bikeNomad\/mbed,bikeNomad\/mbed,nabilbendafi\/mbed,svogl\/mbed-os,alertby\/mbed,nvlsianpu\/mbed,Marcomissyou\/mbed,jferreir\/mbed,adamgreen\/mbed,EmuxEvans\/mbed,kpurusho\/mbed,pradeep-gr\/mbed-os5-onsemi,mazimkhan\/mbed-os,jpbrucker\/mbed,pbrook\/mbed,Marcomissyou\/mbed,RonEld\/mbed,sg-\/mbed-drivers,pedromes\/mbed,EmuxEvans\/mbed,NXPmicro\/mbed,alertby\/mbed,mazimkhan\/mbed-os,jrjang\/mbed,K4zuki\/mbed,brstew\/MBED-BUILD,rosterloh\/mbed,geky\/mbed,jpbrucker\/mbed,mmorenobarm\/mbed-os,autopulated\/mbed,Archcady\/mbed-os,sam-geek\/mbed,CalSol\/mbed,sam-geek\/mbed,jferreir\/mbed,K4zuki\/mbed,getopenmono\/mbed,karsev\/mbed-os,c1728p9\/mbed-os,pedromes\/mbed,bikeNomad\/mbed,jferreir\/mbed,Marcomissyou\/mbed,brstew\/MBED-BUILD,tung7970\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,NitinBhaskar\/mbed,svastm\/mbed,brstew\/MBED-BUILD,larks\/mbed,Tiryoh\/mbed,mmorenobarm\/mbed-os,dbestm\/mbed,monkiineko\/mbed-os,DanKupiniak\/mbed,cvtsi2sd\/mbed-os,struempelix\/mbed,JasonHow44\/mbed,j-greffe\/mbed-os,brstew\/MBED-BUILD,Timmmm\/mbed,NXPmicro\/mbed,Archcady\/mbed-os,kpurusho\/mbed,bcostm\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,logost\/mbed,GustavWi\/mbed,ban4jp\/mbed,mikaleppanen\/mbed-os,geky\/mbed,autopulated\/mbed,xcrespo\/mbed,logost\/mbed,autopulated\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,K4zuki\/mbed,FranklyDev\/mbed,mmorenobarm\/mbed-os,ARM-software\/mbed-beetle,bremoran\/mbed-drivers,fvincenzo\/mbed-os,bcostm\/mbed-os,jpbrucker\/mbed,ryankurte\/mbed-os,YarivCol\/mbed-os,FranklyDev\/mbed,andcor02\/mbed-os,larks\/mbed,dbestm\/mbed,HeadsUpDisplayInc\/mbed,brstew\/MBED-BUILD,fpiot\/mbed-ats,FranklyDev\/mbed,svastm\/mbed,fahhem\/mbed-os,karsev\/mbed-os,hwfwgrp\/mbed,pbrook\/mbed,larks\/mbed,NitinBhaskar\/mbed,jamesadevine\/mbed,bulislaw\/mbed-os,pbrook\/mbed,struempelix\/mbed,bcostm\/mbed-os,EmuxEvans\/mbed,masaohamanaka\/mbed,rgrover\/mbed,fanghuaqi\/mbed,catiedev\/mbed-os,mnlipp\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,pi19404\/mbed,mikaleppanen\/mbed-os,mbedmicro\/mbed,tung7970\/mbed-os-1,screamerbg\/mbed,betzw\/mbed-os,NordicSemiconductor\/mbed,fvincenzo\/mbed-os,rosterloh\/mbed,Marcomissyou\/mbed,al177\/mbed,pedromes\/mbed,hwfwgrp\/mbed,EmuxEvans\/mbed,bikeNomad\/mbed,catiedev\/mbed-os,mmorenobarm\/mbed-os,svogl\/mbed-os,Sweet-Peas\/mbed,bulislaw\/mbed-os,jeremybrodt\/mbed,alertby\/mbed,autopulated\/mbed,YarivCol\/mbed-os,hwfwgrp\/mbed,devanlai\/mbed,kjbracey-arm\/mbed,maximmbed\/mbed,mikaleppanen\/mbed-os,catiedev\/mbed-os,Tiryoh\/mbed,nRFMesh\/mbed-os,screamerbg\/mbed,karsev\/mbed-os,maximmbed\/mbed,bcostm\/mbed-os,pbrook\/mbed,jamesadevine\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,Shengliang\/mbed,wodji\/mbed,svogl\/mbed-os,pradeep-gr\/mbed-os5-onsemi,pi19404\/mbed,masaohamanaka\/mbed,masaohamanaka\/mbed,NordicSemiconductor\/mbed,hwfwgrp\/mbed,sg-\/mbed-drivers,betzw\/mbed-os,infinnovation\/mbed-os,JasonHow44\/mbed,adamgreen\/mbed,wodji\/mbed,mikaleppanen\/mbed-os,JasonHow44\/mbed,YarivCol\/mbed-os,logost\/mbed,wodji\/mbed,bulislaw\/mbed-os,arostm\/mbed-os,ARM-software\/mbed-beetle,CalSol\/mbed,Willem23\/mbed,theotherjimmy\/mbed,c1728p9\/mbed-os,geky\/mbed,adamgreen\/mbed,andreaslarssonublox\/mbed,screamerbg\/mbed,devanlai\/mbed,jeremybrodt\/mbed,infinnovation\/mbed-os,arostm\/mbed-os,ryankurte\/mbed-os,mnlipp\/mbed,Willem23\/mbed,kl-cruz\/mbed-os,fpiot\/mbed-ats,Marcomissyou\/mbed,NitinBhaskar\/mbed,mbedmicro\/mbed,andreaslarssonublox\/mbed,HeadsUpDisplayInc\/mbed,xcrespo\/mbed,pi19404\/mbed,Timmmm\/mbed,maximmbed\/mbed,al177\/mbed,logost\/mbed,cvtsi2sd\/mbed-os,catiedev\/mbed-os,Timmmm\/mbed,fanghuaqi\/mbed,nRFMesh\/mbed-os,mbedmicro\/mbed,betzw\/mbed-os,getopenmono\/mbed,GustavWi\/mbed,screamerbg\/mbed,Sweet-Peas\/mbed,fpiot\/mbed-ats,devanlai\/mbed,iriark01\/mbed-drivers,monkiineko\/mbed-os,YarivCol\/mbed-os,infinnovation\/mbed-os,Willem23\/mbed,ban4jp\/mbed,nvlsianpu\/mbed,FranklyDev\/mbed,arostm\/mbed-os,sam-geek\/mbed,nabilbendafi\/mbed,struempelix\/mbed,infinnovation\/mbed-os,andcor02\/mbed-os,bremoran\/mbed-drivers,cvtsi2sd\/mbed-os,adustm\/mbed,0xc0170\/mbed-drivers,andcor02\/mbed-os,j-greffe\/mbed-os,masaohamanaka\/mbed,Willem23\/mbed,JasonHow44\/mbed,CalSol\/mbed,monkiineko\/mbed-os,infinnovation\/mbed-os,fpiot\/mbed-ats,rgrover\/mbed,svogl\/mbed-os,netzimme\/mbed-os,mnlipp\/mbed,kpurusho\/mbed,Shengliang\/mbed,theotherjimmy\/mbed,nRFMesh\/mbed-os,NXPmicro\/mbed,mmorenobarm\/mbed-os,Timmmm\/mbed,mazimkhan\/mbed-os,svastm\/mbed,0xc0170\/mbed-drivers,ryankurte\/mbed-os,theotherjimmy\/mbed,ryankurte\/mbed-os,ARM-software\/mbed-beetle,hwfwgrp\/mbed,pi19404\/mbed,bikeNomad\/mbed,FranklyDev\/mbed,arostm\/mbed-os,bcostm\/mbed-os,DanKupiniak\/mbed,kl-cruz\/mbed-os,maximmbed\/mbed,xcrespo\/mbed,andcor02\/mbed-os,Shengliang\/mbed,fvincenzo\/mbed-os,netzimme\/mbed-os,Timmmm\/mbed,larks\/mbed,GustavWi\/mbed,naves-thiago\/mbed-midi,jamesadevine\/mbed,logost\/mbed,jeremybrodt\/mbed,jferreir\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Code can explicitly ask for data to be \n       placed in these higher RAM banks where\n       they will be left uninitialized. \n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"55102a754e04b12a20cda7dbbe92baa85dc86a06","subject":"[k210]temp fix dma size for k210","message":"[k210]temp fix dma size for k210\n","repos":"xboot\/xboot,xboot\/xboot","old_file":"src\/arch\/riscv64\/mach-k210\/xboot.ld","new_file":"src\/arch\/riscv64\/mach-k210\/xboot.ld","new_contents":"OUTPUT_FORMAT(\"elf64-littleriscv\", \"elf64-littleriscv\", \"elf64-littleriscv\")\r\nOUTPUT_ARCH(riscv)\r\nENTRY(_start)\r\n\r\nSTACK_SIZE = 0x40000 * 2;\r\n\r\nMEMORY\r\n{\r\n\tram  : org = 0x80000000, len = 4M\r\n\tdma  : org = 0x40400000, len = 0M\r\n\theap : org = 0x80400000, len = 2M\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tPROVIDE(__image_start = .);\r\n\t\tPROVIDE(__text_start = .);\r\n\t\t.obj\/arch\/riscv64\/mach-k210\/start.o (.text*)\r\n\t\t.obj\/arch\/riscv64\/lib\/memcpy.o (.text*)\r\n\t\t.obj\/arch\/riscv64\/lib\/memset.o (.text*)\r\n\t\t.obj\/arch\/riscv64\/mach-k210\/sys-smp.o (.text*)\r\n\t\t.obj\/arch\/riscv64\/mach-k210\/sys-clock.o (.text*)\r\n\t\t.obj\/arch\/riscv64\/mach-k210\/sys-uart.o (.text*)\r\n\t\t*(.text*)\r\n\t\t*(.init.text)\r\n\t\t*(.exit.text)\r\n\t\t*(.iplt)\r\n\t\t*(.note.gnu.build-id)\r\n\t\tPROVIDE(__text_end = .);\r\n\t} > ram\r\n\r\n\t.initcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE(__initcall_end = .);\r\n\t} > ram\r\n\r\n\t.exitcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE(__exitcall_end = .);\r\n\t} > ram\r\n\r\n\t.ksymtab ALIGN(16) :\r\n\t{\r\n\t\tPROVIDE(__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE(__ksymtab_end = .);\r\n\t} > ram\r\n\r\n\t.romdisk ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE(__romdisk_end = .);\r\n\t} > ram\r\n\r\n\t.rodata ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__rodata_start = .);\r\n\t\t*(.rodata*)\r\n\t\t*(.srodata*)\r\n\t\tPROVIDE(__rodata_end = .);\r\n\t} > ram\r\n\r\n\t.data ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__data_start = .);\r\n\t\tPROVIDE(__global_pointer$ = . + 0x800);\r\n\t\t*(.sdata*)\r\n\t\t*(.data*)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE(__data_end = .);\r\n\t\tPROVIDE(__image_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__bss_start = .);\r\n\t\t*(.bss*)\r\n\t\t*(.sbss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__bss_end = .);\r\n\t} > ram\r\n\r\n\t.stack ALIGN(16) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__stack_start = .);\r\n\t\t. += STACK_SIZE;\r\n\t\t. = ALIGN(16);\r\n\t\tPROVIDE(__stack_end = .);\r\n\t} > ram\r\n\r\n\t.dma ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__dma_start = ORIGIN(dma));\r\n\t\tPROVIDE(__dma_end = ORIGIN(dma) + LENGTH(dma));\r\n\t} > dma\r\n\r\n\t.heap ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__heap_start = ORIGIN(heap));\r\n\t\tPROVIDE(__heap_end = ORIGIN(heap) + LENGTH(heap));\r\n\t} > heap\r\n\r\n\t\/DISCARD\/ : { *(.dynsym) }\r\n\t\/DISCARD\/ : { *(.dynstr*) }\r\n\t\/DISCARD\/ : { *(.dynamic*) }\r\n\t\/DISCARD\/ : { *(.plt*) }\r\n\t\/DISCARD\/ : { *(.interp*) }\r\n\t\/DISCARD\/ : { *(.gnu*) }\r\n}\r\n","old_contents":"OUTPUT_FORMAT(\"elf64-littleriscv\", \"elf64-littleriscv\", \"elf64-littleriscv\")\r\nOUTPUT_ARCH(riscv)\r\nENTRY(_start)\r\n\r\nSTACK_SIZE = 0x40000 * 2;\r\n\r\nMEMORY\r\n{\r\n\tram  : org = 0x80000000, len = 3M\r\n\tdma  : org = 0x40300000, len = 1M\r\n\theap : org = 0x80400000, len = 2M\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tPROVIDE(__image_start = .);\r\n\t\tPROVIDE(__text_start = .);\r\n\t\t.obj\/arch\/riscv64\/mach-k210\/start.o (.text*)\r\n\t\t.obj\/arch\/riscv64\/lib\/memcpy.o (.text*)\r\n\t\t.obj\/arch\/riscv64\/lib\/memset.o (.text*)\r\n\t\t.obj\/arch\/riscv64\/mach-k210\/sys-smp.o (.text*)\r\n\t\t.obj\/arch\/riscv64\/mach-k210\/sys-clock.o (.text*)\r\n\t\t.obj\/arch\/riscv64\/mach-k210\/sys-uart.o (.text*)\r\n\t\t*(.text*)\r\n\t\t*(.init.text)\r\n\t\t*(.exit.text)\r\n\t\t*(.iplt)\r\n\t\t*(.note.gnu.build-id)\r\n\t\tPROVIDE(__text_end = .);\r\n\t} > ram\r\n\r\n\t.initcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE(__initcall_end = .);\r\n\t} > ram\r\n\r\n\t.exitcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE(__exitcall_end = .);\r\n\t} > ram\r\n\r\n\t.ksymtab ALIGN(16) :\r\n\t{\r\n\t\tPROVIDE(__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE(__ksymtab_end = .);\r\n\t} > ram\r\n\r\n\t.romdisk ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE(__romdisk_end = .);\r\n\t} > ram\r\n\r\n\t.rodata ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__rodata_start = .);\r\n\t\t*(.rodata*)\r\n\t\t*(.srodata*)\r\n\t\tPROVIDE(__rodata_end = .);\r\n\t} > ram\r\n\r\n\t.data ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__data_start = .);\r\n\t\tPROVIDE(__global_pointer$ = . + 0x800);\r\n\t\t*(.sdata*)\r\n\t\t*(.data*)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE(__data_end = .);\r\n\t\tPROVIDE(__image_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__bss_start = .);\r\n\t\t*(.bss*)\r\n\t\t*(.sbss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__bss_end = .);\r\n\t} > ram\r\n\r\n\t.stack ALIGN(16) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__stack_start = .);\r\n\t\t. += STACK_SIZE;\r\n\t\t. = ALIGN(16);\r\n\t\tPROVIDE(__stack_end = .);\r\n\t} > ram\r\n\r\n\t.dma ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__dma_start = ORIGIN(dma));\r\n\t\tPROVIDE(__dma_end = ORIGIN(dma) + LENGTH(dma));\r\n\t} > dma\r\n\r\n\t.heap ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__heap_start = ORIGIN(heap));\r\n\t\tPROVIDE(__heap_end = ORIGIN(heap) + LENGTH(heap));\r\n\t} > heap\r\n\r\n\t\/DISCARD\/ : { *(.dynsym) }\r\n\t\/DISCARD\/ : { *(.dynstr*) }\r\n\t\/DISCARD\/ : { *(.dynamic*) }\r\n\t\/DISCARD\/ : { *(.plt*) }\r\n\t\/DISCARD\/ : { *(.interp*) }\r\n\t\/DISCARD\/ : { *(.gnu*) }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3cf41b8728a39d1e0d3ee7ae1a1be5f4ecf3b8d9","subject":"BaseTools: GCC: move most AutoGen.obj contents back to .data section","message":"BaseTools: GCC: move most AutoGen.obj contents back to .data section\n\nThe generated AutoGen.c files mostly contain read-only data, but due to\nlacking annotations, all of it is emitted into the .data section by the\ncompiler.\n\nGiven that GUIDs are UEFI's gaffer tape, having writable GUIDs is a\nsecurity hazard, and this was the main rationale for putting AutoGen.obj\nin the .text section. However, as it turns out, patchable PCDs are emitted\nthere as well, which can legally be modified at runtime.\n\nSo update the wildcard pattern to only match g...Guid sections, and move\neverything else back to .data (Note that this relies on -fdata-sections,\nwithout that option, everything is emitted into .data)\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org>\nTested-by: Laszlo Ersek <7437296077edea1cb64451c122c4dac071f0cfbc@redhat.com>\nReviewed-by: Liming Gao <6480311aeeb4b006862f6d13ebabddc03f51e507@intel.com>\nFixes: 233bd25b000f92fc4bbe181fa48edcd72808de8e\n[7437296077edea1cb64451c122c4dac071f0cfbc@redhat.com: add reference to previous commit being fixed up]\nSigned-off-by: Laszlo Ersek <7437296077edea1cb64451c122c4dac071f0cfbc@redhat.com>\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"BaseTools\/Scripts\/GccBase.lds","new_file":"BaseTools\/Scripts\/GccBase.lds","new_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are mostly constant from the POV of the\r\n     * program, but most of it ends up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     * Unfortunately, we cannot pull it into the .text section entirely, since\r\n     * patchable PCDs are also emitted here, but we can at least move all of the\r\n     * emitted GUIDs here.\r\n     *\/\r\n    *:AutoGen.obj(.data.g*Guid)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela (INFO) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/*\r\n   * Retain the GNU build id but in a non-allocatable section so GenFw\r\n   * does not copy it into the PE\/COFF image.\r\n   *\/\r\n  .build-id (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","old_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are constant from the POV of the program,\r\n     * but most of its contents end up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     *\/\r\n    *:AutoGen.obj(.data .data.* .bss .bss.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela (INFO) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/*\r\n   * Retain the GNU build id but in a non-allocatable section so GenFw\r\n   * does not copy it into the PE\/COFF image.\r\n   *\/\r\n  .build-id (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"719d0fb94eecfb6bf478ab416799db883d57175b","subject":"Update linker script for split heap support","message":"Update linker script for split heap support\n\nTo have the flexibilty in application; to use any of the section\n(data\/bss\/heap) without updating linker script in every use case,\nfollowing decisions are made:\n\n1. Fixed size and small sections moved to SRAM2 (32K)\n    Vectors\n    Crash data\n    Stack\n    Remaining section - Heap memory\n2. Large memory space should be used for variable sections\n   Data\n   BSS\n   Heap - Remaining section\n\nHeap is moved to the end of both sections as GCC allocates till 4K boundary,\nif end of heap is not aligned to 4K, that chunk of memory will go unutilized\n","repos":"mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os","old_file":"targets\/TARGET_STM\/TARGET_STM32L4\/TARGET_STM32L475xG\/device\/TOOLCHAIN_GCC_ARM\/STM32L475XX.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32L4\/TARGET_STM32L475xG\/device\/TOOLCHAIN_GCC_ARM\/STM32L475XX.ld","new_contents":"#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 1024k\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\nM_CRASH_DATA_RAM_SIZE = 0x100;\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188\n  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .crash_data_ram :\n    {\n        . = ALIGN(8);\n        __CRASH_DATA_RAM__ = .;\n        __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n        KEEP(*(.keep.crash_data_ram))\n        *(.m_crash_data_ram)     \/* This is a user defined section *\/\n        . += M_CRASH_DATA_RAM_SIZE;\n        . = ALIGN(8);\n        __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > SRAM2\n\n     \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the isr stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += STACK_SIZE - (. - __StackLimit);\n    } > SRAM2\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    _estack = __StackTop;\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n    } > SRAM1\n\n    \/* Check if bss exceeds SRAM1 *\/\n    ASSERT(__data_end__ <= (ORIGIN(SRAM1)+LENGTH(SRAM1)), \".data is too big for SRAM1\")\n\n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > SRAM1\n\n    \/* Check if bss exceeds SRAM1 *\/\n    ASSERT(__bss_end__ <= (ORIGIN(SRAM1)+LENGTH(SRAM1)), \"BSS is too big for SRAM1\")\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        __mbed_sbrk_start_0 = .;\n        end = __end__;\n        *(.heap*)\n        . = (ORIGIN(SRAM2) + LENGTH(SRAM2));\n        __mbed_krbs_start_0 = .;\n        __mbed_sbrk_start = __bss_end__;\n        . = (ORIGIN(SRAM1) + LENGTH(SRAM1));\n        __mbed_krbs_start = .;\n        __HeapLimit = .;\n    } > SRAM2\n}\n","old_contents":"#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 1024k\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\nM_CRASH_DATA_RAM_SIZE = 0x100;\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188\n  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .crash_data_ram :\n    {\n        . = ALIGN(8);\n        __CRASH_DATA_RAM__ = .;\n        __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n        KEEP(*(.keep.crash_data_ram))\n        *(.m_crash_data_ram)     \/* This is a user defined section *\/\n        . += M_CRASH_DATA_RAM_SIZE;\n        . = ALIGN(8);\n        __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > SRAM1\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > SRAM1\n\n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > SRAM2\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .);\n        __HeapLimit = .;\n    } > SRAM1\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \/* Check if data + heap exceeds RAM1 limit *\/\n    ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, \"SRAM1 overflow\")\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n        . += (ORIGIN(SRAM2) + STACK_SIZE - .);\n        __mbed_sbrk_start_0 = .;\n        . += (ORIGIN(SRAM2) + LENGTH(SRAM2) - .);\n        __mbed_krbs_start_0 = .;\n    } > SRAM2\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n    \/* Check if stack exceeds RAM2 limit *\/\n    ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, \"SRAM2 overflow\")\n    \/* Check if bss exceeds __StackLimit *\/\n    ASSERT(__bss_end__ <= __StackLimit, \"BSS is too big for RAM2\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6afd651f1e268e7eabecd42802e404e57be7d4c2","subject":"esp8266\/esp8266.ld: Put axTLS to FlashROM.","message":"esp8266\/esp8266.ld: Put axTLS to FlashROM.\n","repos":"bvernoux\/micropython,misterdanb\/micropython,deshipu\/micropython,redbear\/micropython,pozetroninc\/micropython,bvernoux\/micropython,ryannathans\/micropython,kerneltask\/micropython,TDAbboud\/micropython,tuc-osg\/micropython,alex-robbins\/micropython,adafruit\/micropython,tobbad\/micropython,PappaPeppar\/micropython,drrk\/micropython,dmazzella\/micropython,Peetz0r\/micropython-esp32,swegener\/micropython,kerneltask\/micropython,pfalcon\/micropython,cwyark\/micropython,Peetz0r\/micropython-esp32,adafruit\/circuitpython,SHA2017-badge\/micropython-esp32,cwyark\/micropython,selste\/micropython,alex-march\/micropython,oopy\/micropython,SHA2017-badge\/micropython-esp32,TDAbboud\/micropython,hosaka\/micropython,pozetroninc\/micropython,hiway\/micropython,ryannathans\/micropython,drrk\/micropython,jmarcelino\/pycom-micropython,ryannathans\/micropython,dmazzella\/micropython,mhoffma\/micropython,redbear\/micropython,mhoffma\/micropython,matthewelse\/micropython,praemdonck\/micropython,selste\/micropython,HenrikSolver\/micropython,puuu\/micropython,PappaPeppar\/micropython,MrSurly\/micropython,kerneltask\/micropython,emfcamp\/micropython,micropython\/micropython-esp32,pramasoul\/micropython,deshipu\/micropython,hiway\/micropython,dxxb\/micropython,adafruit\/circuitpython,alex-robbins\/micropython,bvernoux\/micropython,lowRISC\/micropython,selste\/micropython,dinau\/micropython,puuu\/micropython,mhoffma\/micropython,deshipu\/micropython,henriknelson\/micropython,jmarcelino\/pycom-micropython,matthewelse\/micropython,dxxb\/micropython,toolmacher\/micropython,cwyark\/micropython,torwag\/micropython,dmazzella\/micropython,puuu\/micropython,drrk\/micropython,tuc-osg\/micropython,PappaPeppar\/micropython,Peetz0r\/micropython-esp32,blazewicz\/micropython,chrisdearman\/micropython,mpalomer\/micropython,emfcamp\/micropython,swegener\/micropython,turbinenreiter\/micropython,micropython\/micropython-esp32,tralamazza\/micropython,tuc-osg\/micropython,tralamazza\/micropython,pfalcon\/micropython,HenrikSolver\/micropython,hosaka\/micropython,MrSurly\/micropython-esp32,SHA2017-badge\/micropython-esp32,tobbad\/micropython,trezor\/micropython,oopy\/micropython,adafruit\/micropython,ganshun666\/micropython,AriZuu\/micropython,misterdanb\/micropython,torwag\/micropython,drrk\/micropython,tuc-osg\/micropython,trezor\/micropython,lowRISC\/micropython,ganshun666\/micropython,AriZuu\/micropython,praemdonck\/micropython,infinnovation\/micropython,puuu\/micropython,PappaPeppar\/micropython,adafruit\/circuitpython,AriZuu\/micropython,selste\/micropython,HenrikSolver\/micropython,redbear\/micropython,adafruit\/circuitpython,dxxb\/micropython,dinau\/micropython,chrisdearman\/micropython,alex-march\/micropython,drrk\/micropython,MrSurly\/micropython-esp32,bvernoux\/micropython,mhoffma\/micropython,hiway\/micropython,blazewicz\/micropython,trezor\/micropython,ryannathans\/micropython,lowRISC\/micropython,jmarcelino\/pycom-micropython,mpalomer\/micropython,pozetroninc\/micropython,alex-robbins\/micropython,alex-march\/micropython,pfalcon\/micropython,adafruit\/micropython,mpalomer\/micropython,adafruit\/circuitpython,hosaka\/micropython,lowRISC\/micropython,micropython\/micropython-esp32,Timmenem\/micropython,kerneltask\/micropython,SHA2017-badge\/micropython-esp32,turbinenreiter\/micropython,misterdanb\/micropython,kerneltask\/micropython,deshipu\/micropython,emfcamp\/micropython,dinau\/micropython,torwag\/micropython,pozetroninc\/micropython,turbinenreiter\/micropython,jmarcelino\/pycom-micropython,torwag\/micropython,hosaka\/micropython,micropython\/micropython-esp32,alex-march\/micropython,tobbad\/micropython,chrisdearman\/micropython,matthewelse\/micropython,TDAbboud\/micropython,misterdanb\/micropython,Timmenem\/micropython,MrSurly\/micropython-esp32,hiway\/micropython,MrSurly\/micropython,MrSurly\/micropython,chrisdearman\/micropython,dxxb\/micropython,tobbad\/micropython,henriknelson\/micropython,puuu\/micropython,adafruit\/micropython,MrSurly\/micropython-esp32,Timmenem\/micropython,infinnovation\/micropython,lowRISC\/micropython,pramasoul\/micropython,matthewelse\/micropython,micropython\/micropython-esp32,SHA2017-badge\/micropython-esp32,swegener\/micropython,Peetz0r\/micropython-esp32,turbinenreiter\/micropython,toolmacher\/micropython,blazewicz\/micropython,PappaPeppar\/micropython,toolmacher\/micropython,dmazzella\/micropython,AriZuu\/micropython,pfalcon\/micropython,alex-robbins\/micropython,praemdonck\/micropython,blazewicz\/micropython,tobbad\/micropython,deshipu\/micropython,matthewelse\/micropython,pozetroninc\/micropython,toolmacher\/micropython,TDAbboud\/micropython,MrSurly\/micropython-esp32,tralamazza\/micropython,Timmenem\/micropython,trezor\/micropython,pramasoul\/micropython,jmarcelino\/pycom-micropython,praemdonck\/micropython,pramasoul\/micropython,oopy\/micropython,MrSurly\/micropython,swegener\/micropython,ryannathans\/micropython,adafruit\/circuitpython,swegener\/micropython,redbear\/micropython,mpalomer\/micropython,HenrikSolver\/micropython,tuc-osg\/micropython,henriknelson\/micropython,dinau\/micropython,MrSurly\/micropython,torwag\/micropython,dinau\/micropython,AriZuu\/micropython,alex-march\/micropython,oopy\/micropython,pfalcon\/micropython,praemdonck\/micropython,misterdanb\/micropython,dxxb\/micropython,henriknelson\/micropython,mpalomer\/micropython,redbear\/micropython,ganshun666\/micropython,selste\/micropython,blazewicz\/micropython,mhoffma\/micropython,ganshun666\/micropython,turbinenreiter\/micropython,alex-robbins\/micropython,henriknelson\/micropython,infinnovation\/micropython,tralamazza\/micropython,infinnovation\/micropython,trezor\/micropython,Timmenem\/micropython,HenrikSolver\/micropython,bvernoux\/micropython,hiway\/micropython,TDAbboud\/micropython,emfcamp\/micropython,adafruit\/micropython,oopy\/micropython,pramasoul\/micropython,cwyark\/micropython,matthewelse\/micropython,ganshun666\/micropython,toolmacher\/micropython,emfcamp\/micropython,hosaka\/micropython,chrisdearman\/micropython,infinnovation\/micropython,cwyark\/micropython,Peetz0r\/micropython-esp32","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40209000, len = 0x80000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybuart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40209000, len = 0x80000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybuart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0a4fb243dcb9cc9f3e2908c8e9042d8e16700a3b","subject":"Let's use both flash banks for now.","message":"Let's use both flash banks for now.\n","repos":"google\/tock-on-titan,google\/tock-on-titan,google\/tock-on-titan","old_file":"golf2\/chip_layout.ld","new_file":"golf2\/chip_layout.ld","new_contents":"\/* Copyright 2018 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Note: modifications to prog and appram should be reflected in\n   userspace\/layout.ld or Rust userspace (and tests) will fail. *\/\nMEMORY\n{\n  rom (rx)     : ORIGIN = 0x00044400, LENGTH = 0x00031c00\n  prog (rx)    : ORIGIN = 0x00076000, LENGTH = 0x00040000\n  ram (rwx)    : ORIGIN = 0x00010000, LENGTH = 0x00004000\n  appram (rwx) : ORIGIN = 0x00014000, LENGTH = 0x0000c000\n}\n\nMPU_MIN_ALIGN = 8K;\n","old_contents":"\/* Copyright 2018 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Note: modifications to prog and appram should be reflected in\n   userspace\/layout.ld or Rust userspace (and tests) will fail. *\/\nMEMORY\n{\n  rom (rx)     : ORIGIN = 0x00044400, LENGTH = 0x00031c00\n  prog (rx)    : ORIGIN = 0x00076000, LENGTH = 0x00010000\n  ram (rwx)    : ORIGIN = 0x00010000, LENGTH = 0x00004000\n  appram (rwx) : ORIGIN = 0x00014000, LENGTH = 0x0000c000\n}\n\nMPU_MIN_ALIGN = 8K;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6117a20bef98cddd34ab512945fd8b93a2b783ae","subject":"[build] Make the kernel linker script to set section paddrs","message":"[build] Make the kernel linker script to set section paddrs\n\nBy setting correctly the physical address of the program headers,\nnow qemu can correctly load the exOS kernel this way:\n\n   qemu-system-i386 -m 256 -kernel .\/build\/elf_kernel_stripped\n\nClearly, this is not enough since also the ramdisk has to be loaded too.\n","repos":"vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs","old_file":"kernel\/arch\/i386\/linker_script.ld","new_file":"kernel\/arch\/i386\/linker_script.ld","new_contents":"\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib32\");\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib\");\n\nkernel_base_va = 0xC0000000;\nkernel_paddr   = 0x00100000;\n\nSECTIONS\n{\n  . = SEGMENT_START(\"text-segment\", kernel_base_va + kernel_paddr);\n\n  .text : AT(kernel_paddr)\n  {\n    code = .;\n    *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    *(.text.exit .text.exit.*)\n    *(.text.startup .text.startup.*)\n    *(.text.hot .text.hot.*)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    . = ALIGN(4096);\n  }\n\n  .data : AT(kernel_paddr + (data - code))\n  {\n    data = .;\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN(4096);\n  }\n\n  .bss : AT(kernel_paddr + (bss - code))\n  {\n    bss = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n  }\n\n  . = ALIGN(4);\n  _end = .;\n\n  \/DISCARD\/ : { *(.eh_frame*) }\n\n}\n\n\n","old_contents":"\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib32\");\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib\");\n\nkernel_base_va = 0xC0000000;\n\nSECTIONS\n{\n  . = SEGMENT_START(\"text-segment\", kernel_base_va + 0x100000);\n\n  .text :\n  {\n    *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    *(.text.exit .text.exit.*)\n    *(.text.startup .text.startup.*)\n    *(.text.hot .text.hot.*)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    . = ALIGN(4096);\n  }\n\n  .data :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN(4096);\n  }\n\n  .bss :\n  {\n   *(.bss .bss.* .gnu.linkonce.b.*)\n  }\n\n  . = ALIGN(4);\n  _end = .;\n\n  \/DISCARD\/ : { *(.eh_frame*) }\n\n}\n\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"e636279fe07898c5cfd0d33197cdf79f42f76b96","subject":"esp8266: Move more rodata to irom section.","message":"esp8266: Move more rodata to irom section.\n\nrodata can only go in iram\/irom if it's accessed only using word loads\n(ie no byte or half-word access).\n","repos":"matthewelse\/micropython,cloudformdesign\/micropython,emfcamp\/micropython,slzatz\/micropython,feilongfl\/micropython,oopy\/micropython,dxxb\/micropython,cnoviello\/micropython,tuc-osg\/micropython,kostyll\/micropython,cloudformdesign\/micropython,SHA2017-badge\/micropython-esp32,danicampora\/micropython,lowRISC\/micropython,tdautc19841202\/micropython,MrSurly\/micropython-esp32,HenrikSolver\/micropython,jmarcelino\/pycom-micropython,dhylands\/micropython,blmorris\/micropython,xhat\/micropython,ahotam\/micropython,martinribelotta\/micropython,ganshun666\/micropython,puuu\/micropython,MrSurly\/micropython,ruffy91\/micropython,mgyenik\/micropython,cwyark\/micropython,chrisdearman\/micropython,puuu\/micropython,aethaniel\/micropython,jmarcelino\/pycom-micropython,vriera\/micropython,TDAbboud\/micropython,jlillest\/micropython,kerneltask\/micropython,Vogtinator\/micropython,mpalomer\/micropython,supergis\/micropython,PappaPeppar\/micropython,pramasoul\/micropython,adafruit\/micropython,mianos\/micropython,cloudformdesign\/micropython,jimkmc\/micropython,AriZuu\/micropython,dxxb\/micropython,SungEun-Steve-Kim\/test-mp,suda\/micropython,feilongfl\/micropython,adamkh\/micropython,noahchense\/micropython,adafruit\/circuitpython,xhat\/micropython,praemdonck\/micropython,Peetz0r\/micropython-esp32,hiway\/micropython,hiway\/micropython,ryannathans\/micropython,blmorris\/micropython,pozetroninc\/micropython,firstval\/micropython,ahotam\/micropython,stonegithubs\/micropython,skybird6672\/micropython,Vogtinator\/micropython,misterdanb\/micropython,dxxb\/micropython,redbear\/micropython,Timmenem\/micropython,mpalomer\/micropython,bvernoux\/micropython,warner83\/micropython,SungEun-Steve-Kim\/test-mp,selste\/micropython,deshipu\/micropython,ceramos\/micropython,swegener\/micropython,puuu\/micropython,KISSMonX\/micropython,hosaka\/micropython,toolmacher\/micropython,utopiaprince\/micropython,KISSMonX\/micropython,neilh10\/micropython,AriZuu\/micropython,lowRISC\/micropython,praemdonck\/micropython,pfalcon\/micropython,xyb\/micropython,xuxiaoxin\/micropython,noahwilliamsson\/micropython,adafruit\/micropython,skybird6672\/micropython,misterdanb\/micropython,suda\/micropython,kerneltask\/micropython,cnoviello\/micropython,noahwilliamsson\/micropython,pramasoul\/micropython,ernesto-g\/micropython,MrSurly\/micropython-esp32,tdautc19841202\/micropython,kerneltask\/micropython,trezor\/micropython,kostyll\/micropython,blazewicz\/micropython,lbattraw\/micropython,infinnovation\/micropython,mianos\/micropython,skybird6672\/micropython,blmorris\/micropython,cloudformdesign\/micropython,redbear\/micropython,cnoviello\/micropython,orionrobots\/micropython,ganshun666\/micropython,heisewangluo\/micropython,tuc-osg\/micropython,pozetroninc\/micropython,vriera\/micropython,adafruit\/micropython,slzatz\/micropython,henriknelson\/micropython,trezor\/micropython,xuxiaoxin\/micropython,feilongfl\/micropython,henriknelson\/micropython,jimkmc\/micropython,orionrobots\/micropython,firstval\/micropython,adafruit\/circuitpython,matthewelse\/micropython,vriera\/micropython,emfcamp\/micropython,bvernoux\/micropython,matthewelse\/micropython,AriZuu\/micropython,ceramos\/micropython,paul-xxx\/micropython,selste\/micropython,slzatz\/micropython,hosaka\/micropython,rubencabrera\/micropython,jmarcelino\/pycom-micropython,trezor\/micropython,dinau\/micropython,noahwilliamsson\/micropython,tralamazza\/micropython,omtinez\/micropython,turbinenreiter\/micropython,redbear\/micropython,pramasoul\/micropython,blmorris\/micropython,PappaPeppar\/micropython,orionrobots\/micropython,toolmacher\/micropython,tralamazza\/micropython,ernesto-g\/micropython,supergis\/micropython,KISSMonX\/micropython,mpalomer\/micropython,redbear\/micropython,ruffy91\/micropython,ceramos\/micropython,kostyll\/micropython,PappaPeppar\/micropython,chrisdearman\/micropython,noahchense\/micropython,dinau\/micropython,ChuckM\/micropython,cloudformdesign\/micropython,EcmaXp\/micropython,blazewicz\/micropython,adafruit\/circuitpython,ericsnowcurrently\/micropython,vitiral\/micropython,emfcamp\/micropython,suda\/micropython,toolmacher\/micropython,paul-xxx\/micropython,alex-march\/micropython,dmazzella\/micropython,tuc-osg\/micropython,praemdonck\/micropython,oopy\/micropython,feilongfl\/micropython,dhylands\/micropython,adamkh\/micropython,micropython\/micropython-esp32,firstval\/micropython,oopy\/micropython,matthewelse\/micropython,alex-march\/micropython,tuc-osg\/micropython,alex-march\/micropython,galenhz\/micropython,swegener\/micropython,Peetz0r\/micropython-esp32,micropython\/micropython-esp32,omtinez\/micropython,paul-xxx\/micropython,ernesto-g\/micropython,AriZuu\/micropython,omtinez\/micropython,dhylands\/micropython,ChuckM\/micropython,ChuckM\/micropython,noahwilliamsson\/micropython,ceramos\/micropython,mhoffma\/micropython,warner83\/micropython,rubencabrera\/micropython,tobbad\/micropython,selste\/micropython,mianos\/micropython,deshipu\/micropython,redbear\/micropython,rubencabrera\/micropython,xyb\/micropython,mpalomer\/micropython,vitiral\/micropython,aethaniel\/micropython,jlillest\/micropython,noahchense\/micropython,xyb\/micropython,micropython\/micropython-esp32,omtinez\/micropython,feilongfl\/micropython,swegener\/micropython,alex-march\/micropython,chrisdearman\/micropython,EcmaXp\/micropython,kostyll\/micropython,torwag\/micropython,warner83\/micropython,EcmaXp\/micropython,MrSurly\/micropython-esp32,HenrikSolver\/micropython,KISSMonX\/micropython,ryannathans\/micropython,pozetroninc\/micropython,oopy\/micropython,blazewicz\/micropython,slzatz\/micropython,micropython\/micropython-esp32,toolmacher\/micropython,MrSurly\/micropython,cwyark\/micropython,pramasoul\/micropython,jimkmc\/micropython,xuxiaoxin\/micropython,stonegithubs\/micropython,alex-robbins\/micropython,mianos\/micropython,mhoffma\/micropython,dhylands\/micropython,trezor\/micropython,bvernoux\/micropython,torwag\/micropython,swegener\/micropython,paul-xxx\/micropython,mhoffma\/micropython,praemdonck\/micropython,selste\/micropython,adamkh\/micropython,neilh10\/micropython,torwag\/micropython,alex-robbins\/micropython,utopiaprince\/micropython,heisewangluo\/micropython,noahchense\/micropython,tobbad\/micropython,toolmacher\/micropython,cnoviello\/micropython,jlillest\/micropython,xyb\/micropython,warner83\/micropython,Timmenem\/micropython,Timmenem\/micropython,cwyark\/micropython,ahotam\/micropython,firstval\/micropython,Peetz0r\/micropython-esp32,adafruit\/circuitpython,blazewicz\/micropython,adafruit\/micropython,mgyenik\/micropython,TDAbboud\/micropython,PappaPeppar\/micropython,xyb\/micropython,adafruit\/circuitpython,KISSMonX\/micropython,martinribelotta\/micropython,drrk\/micropython,stonegithubs\/micropython,skybird6672\/micropython,neilh10\/micropython,dhylands\/micropython,omtinez\/micropython,martinribelotta\/micropython,hiway\/micropython,lowRISC\/micropython,drrk\/micropython,hosaka\/micropython,tobbad\/micropython,HenrikSolver\/micropython,skybird6672\/micropython,ganshun666\/micropython,ryannathans\/micropython,hiway\/micropython,ruffy91\/micropython,misterdanb\/micropython,paul-xxx\/micropython,aethaniel\/micropython,ruffy91\/micropython,infinnovation\/micropython,Peetz0r\/micropython-esp32,vriera\/micropython,kerneltask\/micropython,TDAbboud\/micropython,pfalcon\/micropython,pfalcon\/micropython,trezor\/micropython,ruffy91\/micropython,lbattraw\/micropython,MrSurly\/micropython,Peetz0r\/micropython-esp32,tralamazza\/micropython,pramasoul\/micropython,chrisdearman\/micropython,Vogtinator\/micropython,noahchense\/micropython,lbattraw\/micropython,ericsnowcurrently\/micropython,ChuckM\/micropython,EcmaXp\/micropython,dinau\/micropython,SHA2017-badge\/micropython-esp32,mpalomer\/micropython,oopy\/micropython,adamkh\/micropython,stonegithubs\/micropython,Timmenem\/micropython,jlillest\/micropython,tdautc19841202\/micropython,alex-march\/micropython,vitiral\/micropython,galenhz\/micropython,cwyark\/micropython,suda\/micropython,Vogtinator\/micropython,SungEun-Steve-Kim\/test-mp,utopiaprince\/micropython,ganshun666\/micropython,orionrobots\/micropython,selste\/micropython,heisewangluo\/micropython,mhoffma\/micropython,puuu\/micropython,dxxb\/micropython,dmazzella\/micropython,tralamazza\/micropython,utopiaprince\/micropython,ganshun666\/micropython,blmorris\/micropython,SungEun-Steve-Kim\/test-mp,jimkmc\/micropython,swegener\/micropython,supergis\/micropython,bvernoux\/micropython,emfcamp\/micropython,cnoviello\/micropython,blazewicz\/micropython,xuxiaoxin\/micropython,ernesto-g\/micropython,galenhz\/micropython,dmazzella\/micropython,SHA2017-badge\/micropython-esp32,ernesto-g\/micropython,TDAbboud\/micropython,SHA2017-badge\/micropython-esp32,lowRISC\/micropython,infinnovation\/micropython,EcmaXp\/micropython,hosaka\/micropython,torwag\/micropython,aethaniel\/micropython,cwyark\/micropython,alex-robbins\/micropython,mianos\/micropython,vitiral\/micropython,PappaPeppar\/micropython,galenhz\/micropython,rubencabrera\/micropython,supergis\/micropython,dinau\/micropython,pfalcon\/micropython,heisewangluo\/micropython,tdautc19841202\/micropython,HenrikSolver\/micropython,stonegithubs\/micropython,pfalcon\/micropython,emfcamp\/micropython,lbattraw\/micropython,dxxb\/micropython,xhat\/micropython,jmarcelino\/pycom-micropython,ericsnowcurrently\/micropython,MrSurly\/micropython,utopiaprince\/micropython,misterdanb\/micropython,turbinenreiter\/micropython,ahotam\/micropython,tdautc19841202\/micropython,bvernoux\/micropython,firstval\/micropython,deshipu\/micropython,deshipu\/micropython,suda\/micropython,rubencabrera\/micropython,MrSurly\/micropython,TDAbboud\/micropython,deshipu\/micropython,warner83\/micropython,tuc-osg\/micropython,adafruit\/micropython,HenrikSolver\/micropython,lbattraw\/micropython,SHA2017-badge\/micropython-esp32,ryannathans\/micropython,MrSurly\/micropython-esp32,turbinenreiter\/micropython,drrk\/micropython,jmarcelino\/pycom-micropython,galenhz\/micropython,mgyenik\/micropython,henriknelson\/micropython,puuu\/micropython,alex-robbins\/micropython,infinnovation\/micropython,turbinenreiter\/micropython,adamkh\/micropython,hosaka\/micropython,vitiral\/micropython,martinribelotta\/micropython,turbinenreiter\/micropython,kerneltask\/micropython,matthewelse\/micropython,danicampora\/micropython,martinribelotta\/micropython,matthewelse\/micropython,misterdanb\/micropython,alex-robbins\/micropython,neilh10\/micropython,chrisdearman\/micropython,praemdonck\/micropython,danicampora\/micropython,aethaniel\/micropython,infinnovation\/micropython,danicampora\/micropython,noahwilliamsson\/micropython,jimkmc\/micropython,henriknelson\/micropython,slzatz\/micropython,ceramos\/micropython,micropython\/micropython-esp32,mgyenik\/micropython,tobbad\/micropython,torwag\/micropython,danicampora\/micropython,mgyenik\/micropython,MrSurly\/micropython-esp32,pozetroninc\/micropython,ahotam\/micropython,dmazzella\/micropython,ericsnowcurrently\/micropython,neilh10\/micropython,ericsnowcurrently\/micropython,AriZuu\/micropython,xhat\/micropython,lowRISC\/micropython,tobbad\/micropython,hiway\/micropython,mhoffma\/micropython,jlillest\/micropython,henriknelson\/micropython,SungEun-Steve-Kim\/test-mp,xhat\/micropython,dinau\/micropython,xuxiaoxin\/micropython,Vogtinator\/micropython,supergis\/micropython,ChuckM\/micropython,heisewangluo\/micropython,drrk\/micropython,adafruit\/circuitpython,pozetroninc\/micropython,Timmenem\/micropython,drrk\/micropython,vriera\/micropython,kostyll\/micropython,orionrobots\/micropython,ryannathans\/micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x40000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n        *py\/*.o*(.literal* .text*)\n        *pyexec.o(.literal*, .text*)\n        *readline.o(.literal*, .text*)\n        *pybstdio.o(.literal*, .text*)\n        *modpyb.o(.literal*, .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *py\/*.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *py\/*.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *py\/*.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x40000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n        *py*.o*(.literal* .text*)\n        *gccollect.o*(.literal* .text*)\n        *gchelper.o*(.literal* .text*)\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        *qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*)\n        \/*\n        can't put these here for some reason...\n        *builtin.o(.rodata.mp_builtin_*_obj)\n        *parse.o(.rodata.rule_*)\n        *\/\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5b91a00da3c2218f36545d12b5543b10ca2afe73","subject":"STM32H747_CM4: add RAM_D3 memory section","message":"STM32H747_CM4: add RAM_D3 memory section\n","repos":"mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed","old_file":"targets\/TARGET_STM\/TARGET_STM32H7\/TARGET_STM32H747xI\/TARGET_STM32H747xI_CM4\/TOOLCHAIN_GCC_ARM\/STM32H747xI_CM4.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32H7\/TARGET_STM32H747xI\/TARGET_STM32H747xI_CM4\/TOOLCHAIN_GCC_ARM\/STM32H747xI_CM4.ld","new_contents":"\/* Linker script to configure memory regions. *\/\n\/*\n * SPDX-License-Identifier: BSD-3-Clause\n ******************************************************************************\n * @attention\n *\n * Copyright (c) 2016-2020 STMicroelectronics.\n * All rights reserved.\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n *                        opensource.org\/licenses\/BSD-3-Clause\n *\n ******************************************************************************\n*\/\n\n#include \"..\/cmsis_nvic.h\"\n\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START  MBED_ROM_START\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE  MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)\n    \/* This value is normally defined by the tools\n       to 0x1000 for bare metal and 0x400 for RTOS *\/\n    #define MBED_CONF_TARGET_BOOT_STACK_SIZE  0x400\n#endif\n\n\/* Round up VECTORS_SIZE to 8 bytes *\/\n#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)\n\nMEMORY\n{\n    FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n    RAM (rwx)    : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE\n    RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    \/* Uninitialized data section\n     * This region is not initialized by the C\/C++ library and can be used to\n     * store state across soft reboots. *\/\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        PROVIDE(end = .);\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\/*\n * SPDX-License-Identifier: BSD-3-Clause\n ******************************************************************************\n * @attention\n *\n * Copyright (c) 2016-2020 STMicroelectronics.\n * All rights reserved.\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n *                        opensource.org\/licenses\/BSD-3-Clause\n *\n ******************************************************************************\n*\/\n\n#include \"..\/cmsis_nvic.h\"\n\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START  MBED_ROM_START\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE  MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)\n    \/* This value is normally defined by the tools\n       to 0x1000 for bare metal and 0x400 for RTOS *\/\n    #define MBED_CONF_TARGET_BOOT_STACK_SIZE  0x400\n#endif\n\n\/* Round up VECTORS_SIZE to 8 bytes *\/\n#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)\n\nMEMORY\n{\n    FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n    RAM (rwx)    : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    \/* Uninitialized data section\n     * This region is not initialized by the C\/C++ library and can be used to\n     * store state across soft reboots. *\/\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        PROVIDE(end = .);\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5e10feeaeb6f0a239f9b3b7a3017575645be5568","subject":"Fix whitespace in linker file","message":"Fix whitespace in linker file\n","repos":"redox-os\/kernel,redox-os\/kernel,redox-os\/kernel","old_file":"linkers\/x86_64.ld","new_file":"linkers\/x86_64.ld","new_contents":"ENTRY(kstart)\nOUTPUT_FORMAT(elf64-x86-64)\n\nKERNEL_OFFSET = 0xFFFF800000100000;\n\nSECTIONS {\n    . = KERNEL_OFFSET;\n\n    . += SIZEOF_HEADERS;\n    . = ALIGN(4096);\n\n    .text : AT(ADDR(.text) - KERNEL_OFFSET) {\n        __text_start = .;\n        *(.text*)\n        . = ALIGN(4096);\n        __text_end = .;\n    }\n\n    .rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) {\n        __rodata_start = .;\n        *(.rodata*)\n        . = ALIGN(4096);\n        __rodata_end = .;\n    }\n\n    .data : AT(ADDR(.data) - KERNEL_OFFSET) {\n        __data_start = .;\n        *(.data*)\n        . = ALIGN(4096);\n        __data_end = .;\n        __bss_start = .;\n        *(.bss*)\n        . = ALIGN(4096);\n        __bss_end = .;\n    }\n\n    .tdata : AT(ADDR(.tdata) - KERNEL_OFFSET) {\n        __tdata_start = .;\n        *(.tdata*)\n        . = ALIGN(4096);\n        __tdata_end = .;\n        __tbss_start = .;\n        *(.tbss*)\n        . += 8;\n        . = ALIGN(4096);\n        __tbss_end = .;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ : {\n        *(.comment*)\n        *(.eh_frame*)\n        *(.gcc_except_table*)\n        *(.note*)\n        *(.rel.eh_frame*)\n    }\n}\n","old_contents":"ENTRY(kstart)\nOUTPUT_FORMAT(elf64-x86-64)\n\nKERNEL_OFFSET = 0xFFFF800000100000;\n\nSECTIONS {\n    . = KERNEL_OFFSET;\n\n    . += SIZEOF_HEADERS;\n    . = ALIGN(4096);\n\n    .text : AT(ADDR(.text) - KERNEL_OFFSET) {\n        __text_start = .;\n        *(.text*)\n\t\t. = ALIGN(4096);\n        __text_end = .;\n    }\n\n\t.rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) {\n        __rodata_start = .;\n        *(.rodata*)\n\t\t. = ALIGN(4096);\n        __rodata_end = .;\n    }\n\n    .data : AT(ADDR(.data) - KERNEL_OFFSET) {\n        __data_start = .;\n        *(.data*)\n\t\t. = ALIGN(4096);\n        __data_end = .;\n        __bss_start = .;\n        *(.bss*)\n        . = ALIGN(4096);\n        __bss_end = .;\n    }\n\n    .tdata : AT(ADDR(.tdata) - KERNEL_OFFSET) {\n        __tdata_start = .;\n        *(.tdata*)\n        . = ALIGN(4096);\n        __tdata_end = .;\n        __tbss_start = .;\n        *(.tbss*)\n        . += 8;\n        . = ALIGN(4096);\n        __tbss_end = .;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ : {\n        *(.comment*)\n        *(.eh_frame*)\n        *(.gcc_except_table*)\n        *(.note*)\n        *(.rel.eh_frame*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"118173013f41a4f661bdb9baa88fb147e346ce75","subject":"stmhal\/boards\/stm32f405.ld: Increase FLASH_TEXT to end of 1MiB flash.","message":"stmhal\/boards\/stm32f405.ld: Increase FLASH_TEXT to end of 1MiB flash.\n\nAnd and FLASH_FS, and use \"K\" values instead of hex numbers for lengths.\n\nThe increase of FLASH_TEXT is to allow more frozen bytecode for a\nparticular user's project.  It's not used for anything else.\n","repos":"blazewicz\/micropython,ryannathans\/micropython,MrSurly\/micropython-esp32,pramasoul\/micropython,AriZuu\/micropython,micropython\/micropython-esp32,tralamazza\/micropython,TDAbboud\/micropython,pozetroninc\/micropython,selste\/micropython,AriZuu\/micropython,chrisdearman\/micropython,henriknelson\/micropython,selste\/micropython,deshipu\/micropython,ryannathans\/micropython,MrSurly\/micropython,adafruit\/circuitpython,Timmenem\/micropython,pozetroninc\/micropython,torwag\/micropython,infinnovation\/micropython,dmazzella\/micropython,PappaPeppar\/micropython,selste\/micropython,alex-robbins\/micropython,tobbad\/micropython,adafruit\/micropython,pramasoul\/micropython,Timmenem\/micropython,AriZuu\/micropython,henriknelson\/micropython,torwag\/micropython,MrSurly\/micropython-esp32,henriknelson\/micropython,lowRISC\/micropython,tralamazza\/micropython,blazewicz\/micropython,swegener\/micropython,MrSurly\/micropython,TDAbboud\/micropython,tralamazza\/micropython,MrSurly\/micropython-esp32,SHA2017-badge\/micropython-esp32,lowRISC\/micropython,Timmenem\/micropython,pfalcon\/micropython,HenrikSolver\/micropython,TDAbboud\/micropython,deshipu\/micropython,bvernoux\/micropython,henriknelson\/micropython,torwag\/micropython,oopy\/micropython,deshipu\/micropython,bvernoux\/micropython,dmazzella\/micropython,ryannathans\/micropython,kerneltask\/micropython,AriZuu\/micropython,ryannathans\/micropython,blazewicz\/micropython,blazewicz\/micropython,henriknelson\/micropython,tobbad\/micropython,trezor\/micropython,alex-robbins\/micropython,adafruit\/circuitpython,chrisdearman\/micropython,swegener\/micropython,bvernoux\/micropython,pfalcon\/micropython,MrSurly\/micropython,MrSurly\/micropython,SHA2017-badge\/micropython-esp32,infinnovation\/micropython,PappaPeppar\/micropython,selste\/micropython,adafruit\/circuitpython,adafruit\/micropython,micropython\/micropython-esp32,bvernoux\/micropython,swegener\/micropython,chrisdearman\/micropython,adafruit\/circuitpython,PappaPeppar\/micropython,alex-robbins\/micropython,infinnovation\/micropython,oopy\/micropython,trezor\/micropython,pramasoul\/micropython,torwag\/micropython,infinnovation\/micropython,adafruit\/micropython,kerneltask\/micropython,adafruit\/micropython,trezor\/micropython,bvernoux\/micropython,deshipu\/micropython,tobbad\/micropython,ryannathans\/micropython,pfalcon\/micropython,trezor\/micropython,MrSurly\/micropython,MrSurly\/micropython-esp32,MrSurly\/micropython-esp32,tobbad\/micropython,alex-robbins\/micropython,tralamazza\/micropython,adafruit\/micropython,blazewicz\/micropython,selste\/micropython,SHA2017-badge\/micropython-esp32,dmazzella\/micropython,kerneltask\/micropython,TDAbboud\/micropython,adafruit\/circuitpython,torwag\/micropython,infinnovation\/micropython,AriZuu\/micropython,pfalcon\/micropython,SHA2017-badge\/micropython-esp32,alex-robbins\/micropython,SHA2017-badge\/micropython-esp32,TDAbboud\/micropython,pramasoul\/micropython,dmazzella\/micropython,HenrikSolver\/micropython,PappaPeppar\/micropython,pozetroninc\/micropython,pfalcon\/micropython,micropython\/micropython-esp32,HenrikSolver\/micropython,chrisdearman\/micropython,swegener\/micropython,lowRISC\/micropython,trezor\/micropython,Timmenem\/micropython,lowRISC\/micropython,HenrikSolver\/micropython,deshipu\/micropython,oopy\/micropython,pozetroninc\/micropython,pozetroninc\/micropython,oopy\/micropython,chrisdearman\/micropython,swegener\/micropython,Timmenem\/micropython,pramasoul\/micropython,micropython\/micropython-esp32,kerneltask\/micropython,HenrikSolver\/micropython,kerneltask\/micropython,micropython\/micropython-esp32,oopy\/micropython,tobbad\/micropython,adafruit\/circuitpython,lowRISC\/micropython,PappaPeppar\/micropython","old_file":"stmhal\/boards\/stm32f405.ld","new_file":"stmhal\/boards\/stm32f405.ld","new_contents":"\/*\n    GNU linker script for STM32F405\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K \/* entire flash *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K \/* sector 0 *\/\n    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 112K \/* sectors 1,2,3,4 are for filesystem *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 896K \/* sectors 5,6,7,8,9,10,11 *\/\n    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 64K\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define common sections and symbols *\/\nINCLUDE common.ld\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = 0x2001c000; \/* tunable *\/\n","old_contents":"\/*\n    GNU linker script for STM32F405\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 \/* sector 0, 16 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x080000 \/* sectors 5,6,7,8, 4*128KiB = 512 KiB (could increase it more) *\/\n    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 0x010000 \/* 64 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x020000 \/* 128 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define common sections and symbols *\/\nINCLUDE common.ld\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = 0x2001c000; \/* tunable *\/\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"52afe53883047bf2f5c9c999c33601b84394cb3e","subject":"improve linker script","message":"improve linker script\n\n - explicitly DISCARD .note and .comment section, so they don't appear\n   in `ld -M` output\n - add some asterisks to support input objects created with\n   `-ffunction-sections` and `-fdata-sections`\n","repos":"Zirias\/clang-libdos,Zirias\/clang-libdos","old_file":"com.ld","new_file":"com.ld","new_contents":"OUTPUT_FORMAT(binary)\nSECTIONS\n{\n    . = 0x0100;\n    .text :\n    {\n\t*(.text*);\n    }\n    .data :\n    {\n\t*(.data*);\n\t*(.rodata*);\n\t*(COMMON);\n\t*(.bss*);\n    }\n    \/DISCARD\/ :\n    {\n\t*(.note*);\n\t*(.comment*);\n    }\n    _heap = ALIGN(4);\n}\n\n","old_contents":"OUTPUT_FORMAT(binary)\nSECTIONS\n{\n    . = 0x0100;\n    .text :\n    {\n\t*(.text);\n    }\n    .data :\n    {\n\t*(.data);\n\t*(.rodata);\n\t*(COMMON);\n\t*(.bss);\n    }\n    _heap = ALIGN(4);\n}\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"f743435328bde6396cc9411d9070e17b9e6b0a26","subject":"Working build","message":"Working build\n","repos":"ideepuraj\/bare-metal-arm,ideepuraj\/bare-metal-arm","old_file":"README.ld","new_file":"README.ld","new_contents":"","old_contents":"bare-metal-arm\n==============\n\nA fork of the baremetal runtime example for the FRDM-KL25Z by Andrew Payne. \n\nCurrently configured as an eclipse project with hard coded paths to the toolchain. This will be fixed in due course.\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ab4d18a137c82aea546f4a1ec8044284f8a233cb","subject":"[bsp\/taihu] fix the link error","message":"[bsp\/taihu] fix the link error\n\nThe taihu.lds hardcoded the path of start_gcc.o. Change it as the layout\nof build\/ has change by commit a03816ef9aa583bb.\n","repos":"wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,RT-Thread\/rt-thread,yongli3\/rt-thread,AubrCool\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,yongli3\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,zhaojuntao\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,AubrCool\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,yongli3\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,igou\/rt-thread,wolfgangz2013\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,zhaojuntao\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,weiyuliang\/rt-thread,igou\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,zhaojuntao\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,igou\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,weiyuliang\/rt-thread,ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,igou\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,FlyLu\/rt-thread","old_file":"bsp\/taihu\/taihu.lds","new_file":"bsp\/taihu\/taihu.lds","new_contents":"OUTPUT_ARCH(powerpc)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nSECTIONS\n{\n  .resetvec 0xFFFFFFFC :\n  {\n    *(.resetvec)\n  } = 0xffff\n\n  \/* Read-only sections, merged into text segment: *\/\n  . = + SIZEOF_HEADERS;\n  .interp : { *(.interp) }\n  .hash          : { *(.hash)           }\n  .dynsym        : { *(.dynsym)         }\n  .dynstr        : { *(.dynstr)         }\n  .rel.text      : { *(.rel.text)       }\n  .rela.text     : { *(.rela.text)      }\n  .rel.data      : { *(.rel.data)       }\n  .rela.data     : { *(.rela.data)      }\n  .rel.rodata    : { *(.rel.rodata)     }\n  .rela.rodata   : { *(.rela.rodata)    }\n  .rel.got       : { *(.rel.got)        }\n  .rela.got      : { *(.rela.got)       }\n  .rel.ctors     : { *(.rel.ctors)      }\n  .rela.ctors    : { *(.rela.ctors)     }\n  .rel.dtors     : { *(.rel.dtors)      }\n  .rela.dtors    : { *(.rela.dtors)     }\n  .rel.bss       : { *(.rel.bss)        }\n  .rela.bss      : { *(.rela.bss)       }\n  .rel.plt       : { *(.rel.plt)        }\n  .rela.plt      : { *(.rela.plt)       }\n  \/* .init          : { *(.init)           } *\/\n  .plt : { *(.plt) }\n\n  .text      :\n  {\n    KEEP(build\/kernel\/libcpu\/ppc\/ppc405\/start_gcc.o (.text))\n\n    *(.text)\n    *(.fixup)\n    *(.got1)\n  }\n  _etext = .;\n  PROVIDE (etext = .);\n  .rodata    :\n  {\n    *(.eh_frame)\n    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\n    \/* section information for finsh shell *\/\n    . = ALIGN(4);\n    __fsymtab_start = .;\n    KEEP(*(FSymTab))\n    __fsymtab_end = .;\n    . = ALIGN(4);\n    __vsymtab_start = .;\n    KEEP(*(VSymTab))\n    __vsymtab_end = .;\n  }\n  .fini      : { *(.fini)    } =0\n  .ctors     : { *(.ctors)   }\n  .dtors     : { *(.dtors)   }\n\n  \/* Read-write section, merged into data segment: *\/\n  . = (. + 0x00FF) & 0xFFFFFF00;\n  _erotext = .;\n  PROVIDE (erotext = .);\n  .reloc   :\n  {\n    *(.got)\n    _GOT2_TABLE_ = .;\n    *(.got2)\n    _FIXUP_TABLE_ = .;\n    *(.fixup)\n  }\n  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;\n  __fixup_entries = (. - _FIXUP_TABLE_)>>2;\n\n  .data    :\n  {\n    *(.data)\n    *(.data1)\n    *(.sdata)\n    *(.sdata2)\n    *(.dynamic)\n    CONSTRUCTORS\n  }\n  _edata  =  .;\n  PROVIDE (edata = .);\n\n  . = .;\n  __start___ex_table = .;\n  __ex_table : { *(__ex_table) }\n  __stop___ex_table = .;\n\n  . = ALIGN(256);\n  __init_begin = .;\n  .text.init : { *(.text.init) }\n  .data.init : { *(.data.init) }\n  . = ALIGN(256);\n  __init_end = .;\n\n  __bss_start = .;\n  .bss (NOLOAD)       :\n  {\n   *(.sbss) *(.scommon)\n   *(.dynbss)\n   *(.bss)\n   *(COMMON)\n   . = ALIGN(4);\n  }\n  __bss_end = .;\n\n  . = ALIGN(256);\n\n  PROVIDE(__stack_bottom = .);\n  . += 0x100000; \/* 1MB *\/\n  PROVIDE(__stack_top = .);\n\n  . = ALIGN(256);\n  PROVIDE (__heap_start = .);\n  . += 0x500000; \/* 5MB *\/\n  PROVIDE(__heap_end = .);\n\n  _end = . ;\n  PROVIDE (end = .);\n}\n","old_contents":"OUTPUT_ARCH(powerpc)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nSECTIONS\n{\n  .resetvec 0xFFFFFFFC :\n  {\n    *(.resetvec)\n  } = 0xffff\n\n  \/* Read-only sections, merged into text segment: *\/\n  . = + SIZEOF_HEADERS;\n  .interp : { *(.interp) }\n  .hash          : { *(.hash)           }\n  .dynsym        : { *(.dynsym)         }\n  .dynstr        : { *(.dynstr)         }\n  .rel.text      : { *(.rel.text)       }\n  .rela.text     : { *(.rela.text)      }\n  .rel.data      : { *(.rel.data)       }\n  .rela.data     : { *(.rela.data)      }\n  .rel.rodata    : { *(.rel.rodata)     }\n  .rela.rodata   : { *(.rela.rodata)    }\n  .rel.got       : { *(.rel.got)        }\n  .rela.got      : { *(.rela.got)       }\n  .rel.ctors     : { *(.rel.ctors)      }\n  .rela.ctors    : { *(.rela.ctors)     }\n  .rel.dtors     : { *(.rel.dtors)      }\n  .rela.dtors    : { *(.rela.dtors)     }\n  .rel.bss       : { *(.rel.bss)        }\n  .rela.bss      : { *(.rela.bss)       }\n  .rel.plt       : { *(.rel.plt)        }\n  .rela.plt      : { *(.rela.plt)       }\n  \/* .init          : { *(.init)           } *\/\n  .plt : { *(.plt) }\n\n  .text      :\n  {\n    KEEP(build\/libcpu\/ppc\/ppc405\/start_gcc.o (.text))\n\n    *(.text)\n    *(.fixup)\n    *(.got1)\n  }\n  _etext = .;\n  PROVIDE (etext = .);\n  .rodata    :\n  {\n    *(.eh_frame)\n    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\n    \/* section information for finsh shell *\/\n    . = ALIGN(4);\n    __fsymtab_start = .;\n    KEEP(*(FSymTab))\n    __fsymtab_end = .;\n    . = ALIGN(4);\n    __vsymtab_start = .;\n    KEEP(*(VSymTab))\n    __vsymtab_end = .;\n  }\n  .fini      : { *(.fini)    } =0\n  .ctors     : { *(.ctors)   }\n  .dtors     : { *(.dtors)   }\n\n  \/* Read-write section, merged into data segment: *\/\n  . = (. + 0x00FF) & 0xFFFFFF00;\n  _erotext = .;\n  PROVIDE (erotext = .);\n  .reloc   :\n  {\n    *(.got)\n    _GOT2_TABLE_ = .;\n    *(.got2)\n    _FIXUP_TABLE_ = .;\n    *(.fixup)\n  }\n  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;\n  __fixup_entries = (. - _FIXUP_TABLE_)>>2;\n\n  .data    :\n  {\n    *(.data)\n    *(.data1)\n    *(.sdata)\n    *(.sdata2)\n    *(.dynamic)\n    CONSTRUCTORS\n  }\n  _edata  =  .;\n  PROVIDE (edata = .);\n\n  . = .;\n  __start___ex_table = .;\n  __ex_table : { *(__ex_table) }\n  __stop___ex_table = .;\n\n  . = ALIGN(256);\n  __init_begin = .;\n  .text.init : { *(.text.init) }\n  .data.init : { *(.data.init) }\n  . = ALIGN(256);\n  __init_end = .;\n\n  __bss_start = .;\n  .bss (NOLOAD)       :\n  {\n   *(.sbss) *(.scommon)\n   *(.dynbss)\n   *(.bss)\n   *(COMMON)\n   . = ALIGN(4);\n  }\n  __bss_end = .;\n\n  . = ALIGN(256);\n\n  PROVIDE(__stack_bottom = .);\n  . += 0x100000; \/* 1MB *\/\n  PROVIDE(__stack_top = .);\n\n  . = ALIGN(256);\n  PROVIDE (__heap_start = .);\n  . += 0x500000; \/* 5MB *\/\n  PROVIDE(__heap_end = .);\n\n  _end = . ;\n  PROVIDE (end = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"88f624f412a75b24a58c26692812e4510736abcd","subject":"examples: Small fix in comment.","message":"examples: Small fix in comment.\n","repos":"ziutek\/emgo,ziutek\/emgo,ziutek\/emgo,ziutek\/emgo","old_file":"egpath\/src\/stm32\/examples\/nucleo-f411re\/rtc\/script.ld","new_file":"egpath\/src\/stm32\/examples\/nucleo-f411re\/rtc\/script.ld","new_contents":"\/* Stack size: 6 KB *\/\nStackLog2 = 13; \/* 8 KB *\/\nStackFrac = 6;  \/* 6\/8 *\/\n\n\/* Two gorutines, 3 stacks. *\/\nMaxTasks = 2;\n\nINCLUDE stm32\/f411\nINCLUDE stm32\/loadram\nINCLUDE noos-cortexm\n\n","old_contents":"\/* Stack size: 6 KB *\/\nStackLog2 = 13; \/* 8 KB *\/\nStackFrac = 6;  \/* 6\/8 *\/\n\n\/* One stack, without gorutines *\/\nMaxTasks = 2;\n\nINCLUDE stm32\/f411\nINCLUDE stm32\/loadram\nINCLUDE noos-cortexm\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"1bcb12c59dcfb830ffb9b8db7305720c83cb17ac","subject":"doc: fix LDoc manual page custom_see_handler pattern.","message":"doc: fix LDoc manual page custom_see_handler pattern.\n\n* ext\/posix\/config.ld (custom_see_handler): Add a missing closing\n`%)`.\n(upat): Pull the format string up per LDoc documentation.\n\nSigned-off-by: Gary V. Vaughan <f9023000f29773649f3850298becb9544b5fd6a9@gnu.org>\n","repos":"zevv\/luaposix,snegovick\/luaposix,rrthomas\/luaposix,jimmyharris\/luaposix,rrthomas\/luaposix,ardje\/luaposix,jimmyharris\/luaposix,ardje\/luaposix,zevv\/luaposix,snegovick\/luaposix,luaposix\/luaposix","old_file":"ext\/posix\/config.ld","new_file":"ext\/posix\/config.ld","new_contents":"-- -*- lua -*-\nfile = 'posix.c'\nproject = 'luaposix'\ndescription = 'POSIX bindings for Lua'\n\ntparam_alias 'string'\ntparam_alias 'int'\ntparam_alias 'bool'\n\nlocal upat = \"http:\/\/www.kernel.org\/doc\/man-pages\/online\/pages\/man%s\/%s.%s.html\"\ncustom_see_handler('^([%w_]+)%((%d)%)$',function(name,section)\n    local url = upat:format(section,name,section)\n    local name = name .. '(' .. section .. ')'\n    return name, url\nend)\n\nexamples = 'examples'\n\nformat = 'discount'\n","old_contents":"-- -*- lua -*-\nfile = 'posix.c'\nproject = 'luaposix'\ndescription = 'POSIX bindings for Lua'\n\ntparam_alias 'string'\ntparam_alias 'int'\ntparam_alias 'bool'\n\ncustom_see_handler('^([%w_]+)%((%d)$',function(name,section)\n    local url = (\"http:\/\/www.kernel.org\/doc\/man-pages\/online\/pages\/man%s\/%s.%s.html\"):format(section,name,section)\n    local name = name .. '(' ..section..')'\n    return name, url\nend)\n\nexamples = 'examples'\n\nformat = 'discount'\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c0dacba80f3c7490f36dda3fa2c7b0df842c8bcf","subject":"remove comment confusing py tools","message":"remove comment confusing py tools\n","repos":"adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/stm32f4\/boards\/STM32F401.ld","new_file":"ports\/stm32f4\/boards\/STM32F401.ld","new_contents":"\/*\n    GNU linker script for STM32F401 with bootloader (from Meowbit Micropython)\n    Doesn't work: \n\n    Traceback (most recent call last):\n  File \"..\/..\/tools\/build_memory_info.py\", line 64, in <module>\n    regions[region] = int(eval(space))\n  File \"<string>\", line 1, in <module>\nNameError: name 'FLASH_ISR' is not defined\n*\/\n\n\/* Specify the memory areas *\/\n\/*     FLASH_FS (rx)   : ORIGIN = 0x08020000, LENGTH = 128K *\/\n\/* sectors 5 128K *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08010000, LENGTH = 512K - 64K \/* entire flash *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08010000, LENGTH = 64K \/* sector 4, sec 0~3 reserved for booloader *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 384K \/* sectors 5, 6,7 are 128K *\/\n    RAM (xrw)       : ORIGIN = 0x20000194, LENGTH = 96K - 0x194\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K; \/* tunable *\/\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n\nENTRY(Reset_Handler)\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        \/* This first flash block is 16K annd the isr vectors only take up\n           about 400 bytes. So we pull in a couple of object files to pad it\n           out. *\/\n\n        . = ALIGN(4);\n\n        \/* NOTE: If you update the list of files contained in .isr_vector,\n                 then be sure to also update smhal\/Makefile where it forcibly\n           builds each of these files with -Os *\/\n\n        *\/ff.o(.text*)\n        *\/vfs_fat_*.o(.text*)\n        *\/py\/formatfloat.o(.text*)\n        *\/py\/parsenum.o(.text*)\n        *\/py\/mpprint.o(.text*)\n\n        *\/py\/compile.o(.text*)\n        *\/py\/objset.o(.text*)\n        *\/py\/mpz.o(.text*)\n        *\/py\/vm.o(.text*)\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n\n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT> FLASH_TEXT\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_heap_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n    GNU linker script for STM32F401 with bootloader (from Meowbit Micropython)\n    Doesn't work: \n\n    Traceback (most recent call last):\n  File \"..\/..\/tools\/build_memory_info.py\", line 64, in <module>\n    regions[region] = int(eval(space))\n  File \"<string>\", line 1, in <module>\nNameError: name 'FLASH_ISR' is not defined\n*\/\n\n\/* Specify the memory areas *\/\n\/*     FLASH_FS (rx)   : ORIGIN = 0x08020000, LENGTH = 128K *\/\n\/* sectors 5 128K *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08010000, LENGTH = 512K - 64K \/* entire flash *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08010000, LENGTH = 64K \/* sector 4, sec 0~3 reserved for booloader *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 384K \/* sectors 5, 6,7 are 128K *\/\n    RAM (xrw)       : ORIGIN = 0x20000194, LENGTH = 96K - 0x194\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K; \/* tunable *\/\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n\n\/* Memory layout for internal flash storage configuration:\n\n    FLASH_ISR   .isr_vector\n\n    FLASH_TEXT  .text\n    FLASH_TEXT  .data\n\n    RAM         .data\n    RAM         .bss\n    RAM         .heap\n    RAM         .stack\n*\/\n\nENTRY(Reset_Handler)\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        \/* This first flash block is 16K annd the isr vectors only take up\n           about 400 bytes. So we pull in a couple of object files to pad it\n           out. *\/\n\n        . = ALIGN(4);\n\n        \/* NOTE: If you update the list of files contained in .isr_vector,\n                 then be sure to also update smhal\/Makefile where it forcibly\n           builds each of these files with -Os *\/\n\n        *\/ff.o(.text*)\n        *\/vfs_fat_*.o(.text*)\n        *\/py\/formatfloat.o(.text*)\n        *\/py\/parsenum.o(.text*)\n        *\/py\/mpprint.o(.text*)\n\n        *\/py\/compile.o(.text*)\n        *\/py\/objset.o(.text*)\n        *\/py\/mpz.o(.text*)\n        *\/py\/vm.o(.text*)\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n\n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT> FLASH_TEXT\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_heap_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c9c489d3023ffb084a7c34b89b0fb55ffd2ca632","subject":"Shrink the memory region to avoid affacting RedBoot","message":"Shrink the memory region to avoid affacting RedBoot\n","repos":"gregwym\/PollingTrainControlPanel,gregwym\/PollingTrainControlPanel,gregwym\/PollingTrainControlPanel","old_file":"orex.ld","new_file":"orex.ld","new_contents":"ENTRY (main)\n\nMEMORY\n{\nram : ORIGIN = 0x00001024, LENGTH = 30M\nrom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\ndata : \/* Initialized data. *\/\n{\n_DataStart = . ;\n*(.data)\n_DataEnd = . ;\n} >ram\n\nbss : \/* Uninitialized data. *\/\n{\n_BssStart = . ;\n*(.bss)\n_BssEnd = . ;\n} >ram\n\ntext : \/* The actual instructions. *\/\n{\n*(.text)\n*(.got)\n*(.got.plt)\n*(.rodata)\n*(.glue_7)\n*(.glue_7t)\n} >ram\n}\n","old_contents":"ENTRY (main)\n\nMEMORY\n{\nram : ORIGIN = 0x00000000, LENGTH = 32M\nrom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\ndata : \/* Initialized data. *\/\n{\n_DataStart = . ;\n*(.data)\n_DataEnd = . ;\n} >ram\n\nbss : \/* Uninitialized data. *\/\n{\n_BssStart = . ;\n*(.bss)\n_BssEnd = . ;\n} >ram\n\ntext : \/* The actual instructions. *\/\n{\n*(.text)\n*(.got)\n*(.got.plt)\n*(.rodata)\n*(.glue_7)\n*(.glue_7t)\n} >ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"1ef0e3c91a28a5b4236c38631101b34ad52c9b0a","subject":"THE KERNEL STARTS AFTER THE FIRST MEGABYTE","message":"THE KERNEL STARTS AFTER THE FIRST MEGABYTE","repos":"ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme","old_file":"orex.ld","new_file":"orex.ld","new_contents":"ENTRY (main)\n\nMEMORY\n{\n  ram : ORIGIN = 0x00100000, LENGTH = 31M\n  rom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n  .data : \/* Initialized data. *\/\n  {\n    _DataStart = . ;\n    *(.data.kern)\n    _DataKernEnd = . ;\n    *(.data)\n    *(.data.rel.local)\n    _DataEnd = . ;\n  } >ram\n\n  .bss : \/* Uninitialized data. *\/\n  {\n    _BssStart = . ;\n    *(.bss)\n    *(.sbss)\n    _BssEnd = . ;\n  } >ram\n\n  .text ALIGN(0x100): \t\/* The actual instructions.          *\/\n  {\t\t      \t\/* Alignment ensures that data will  *\/\n    _TextStart = . ;\t\/* not get loaded into the icache    *\/\n    *(.text.kern)\n    _TextKernEnd = . ;\n    *(.text)\n    *(.rodata)\n    *(.rodata.str1.4)\n    *(.glue_7)\n    *(.glue_7t)\n    _TextEnd = . ;\n  } >ram\n}\n","old_contents":"ENTRY (main)\n\nMEMORY\n{\n  ram : ORIGIN = 0x00000000, LENGTH = 32M\n  rom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n  .data 0x100000: \/* Initialized data. *\/\n  {\n    _DataStart = . ;\n    *(.data.kern)\n    _DataKernEnd = . ;\n    *(.data)\n    *(.data.rel.local)\n    _DataEnd = . ;\n  } >ram\n\n  .bss : \/* Uninitialized data. *\/\n  {\n    _BssStart = . ;\n    *(.bss)\n    *(.sbss)\n    _BssEnd = . ;\n  } >ram\n\n  .text ALIGN(0x100): \t\/* The actual instructions.          *\/\n  {\t\t      \t\/* Alignment ensures that data will  *\/\t\n    _TextStart = . ;\t\/* not get loaded into the icache    *\/\n    *(.text.kern)\n    _TextKernEnd = . ;\n    *(.text)\n    *(.rodata)\n    *(.rodata.str1.4)\n    *(.glue_7)\n    *(.glue_7t)\n    _TextEnd = . ;\n  } >ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0cffa6be81636565750f31714efbf7727768db86","subject":"Sort .text section to reduce fill on nRF","message":"Sort .text section to reduce fill on nRF\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/nrf\/boards\/common.template.ld","new_file":"ports\/nrf\/boards\/common.template.ld","new_contents":"\/*\n    GNU linker script for NRF52840 w\/ s140 6.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = ${FLASH_SIZE} \/* entire flash *\/\n    \/* nRF SoftDevice *\/\n    FLASH_MBR (rx)  : ORIGIN = ${MBR_START_ADDR}, LENGTH = ${MBR_SIZE}\n    FLASH_SD (rx)   : ORIGIN = ${SD_FLASH_START_ADDR}, LENGTH = ${SD_FLASH_SIZE}\n    FLASH_ISR (rx)  : ORIGIN = ${ISR_START_ADDR}, LENGTH = ${ISR_SIZE}\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_BLE_CONFIG (r) : ORIGIN = ${CIRCUITPY_BLE_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_BLE_CONFIG_SIZE}\n    FLASH_NVM (r)   : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n    FLASH_FATFS (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_BOOTLOADER (rx) : ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n    FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}\n\n\n    \/* SoftDevice RAM must start at the beginning of RAM: 0x2000000 (RAM_START_ADDR).\n       On nRF52840, the first 64kB of RAM is composed of 8 8kB RAM blocks. Above those is\n       RAM block 8, which is 192kB.\n       If SPIM3_BUFFER_RAM_SIZE is 8kB, as opposed to zero, it must be in the first 64kB of RAM.\n       So the amount of RAM reserved for the SoftDevice must be no more than 56kB.\n    *\/\n    RAM (xrw)       : ORIGIN = ${RAM_START_ADDR}, LENGTH = ${RAM_SIZE}\n    SD_RAM (rw)     : ORIGIN = ${SOFTDEVICE_RAM_START_ADDR}, LENGTH = ${SOFTDEVICE_RAM_SIZE}\n    SPIM3_RAM (rw)  : ORIGIN = ${SPIM3_BUFFER_RAM_START_ADDR}, LENGTH = ${SPIM3_BUFFER_RAM_SIZE}\n    APP_RAM (xrw)   : ORIGIN = ${APP_RAM_START_ADDR}, LENGTH = ${APP_RAM_SIZE}\n}\n\n\/* produce a link error if there is not this amount of RAM available *\/\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(APP_RAM) + LENGTH(APP_RAM);*\/\n_estack = ORIGIN(APP_RAM) + LENGTH(APP_RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(APP_RAM) + LENGTH(APP_RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\n\/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. *\/\n_spim3_ram = ORIGIN(SPIM3_RAM);\n_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(SPIM3_RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.text))           \/* .text sections (code) *\/\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.text*))          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_FIRMWARE\n\n    \/* used by the startup to initialize data *\/\n    _sidata = .;\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.data))           \/* .data sections *\/\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.data*))          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >APP_RAM\n\n    \/* Zero-initialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss))\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >APP_RAM\n\n    \/* Uninitialized data section\n    Data placed into this section will remain unchanged across reboots. *\/\n    .uninitialized (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _suninitialized = .; \/* define a global symbol at uninitialized start; currently unused *\/\n        *(.uninitialized)\n        *(.uninitialized*)\n\n        . = ALIGN(4);\n        _euninitialized = .; \/* define a global symbol at uninitialized end; currently unused *\/\n    } >APP_RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\t      PROVIDE ( end = . );\n\t      PROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >APP_RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >APP_RAM\n\n    \/* Remove exception unwinding information, since CircuitPython\n       does not support this GCC feature. *\/\n    \/DISCARD\/ :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.ARM.exidx*)\n    }\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n    GNU linker script for NRF52840 w\/ s140 6.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = ${FLASH_SIZE} \/* entire flash *\/\n    \/* nRF SoftDevice *\/\n    FLASH_MBR (rx)  : ORIGIN = ${MBR_START_ADDR}, LENGTH = ${MBR_SIZE}\n    FLASH_SD (rx)   : ORIGIN = ${SD_FLASH_START_ADDR}, LENGTH = ${SD_FLASH_SIZE}\n    FLASH_ISR (rx)  : ORIGIN = ${ISR_START_ADDR}, LENGTH = ${ISR_SIZE}\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_BLE_CONFIG (r) : ORIGIN = ${CIRCUITPY_BLE_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_BLE_CONFIG_SIZE}\n    FLASH_NVM (r)   : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n    FLASH_FATFS (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_BOOTLOADER (rx) : ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n    FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}\n\n\n    \/* SoftDevice RAM must start at the beginning of RAM: 0x2000000 (RAM_START_ADDR).\n       On nRF52840, the first 64kB of RAM is composed of 8 8kB RAM blocks. Above those is\n       RAM block 8, which is 192kB.\n       If SPIM3_BUFFER_RAM_SIZE is 8kB, as opposed to zero, it must be in the first 64kB of RAM.\n       So the amount of RAM reserved for the SoftDevice must be no more than 56kB.\n    *\/\n    RAM (xrw)       : ORIGIN = ${RAM_START_ADDR}, LENGTH = ${RAM_SIZE}\n    SD_RAM (rw)     : ORIGIN = ${SOFTDEVICE_RAM_START_ADDR}, LENGTH = ${SOFTDEVICE_RAM_SIZE}\n    SPIM3_RAM (rw)  : ORIGIN = ${SPIM3_BUFFER_RAM_START_ADDR}, LENGTH = ${SPIM3_BUFFER_RAM_SIZE}\n    APP_RAM (xrw)   : ORIGIN = ${APP_RAM_START_ADDR}, LENGTH = ${APP_RAM_SIZE}\n}\n\n\/* produce a link error if there is not this amount of RAM available *\/\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(APP_RAM) + LENGTH(APP_RAM);*\/\n_estack = ORIGIN(APP_RAM) + LENGTH(APP_RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(APP_RAM) + LENGTH(APP_RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\n\/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. *\/\n_spim3_ram = ORIGIN(SPIM3_RAM);\n_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(SPIM3_RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_FIRMWARE\n\n    \/* used by the startup to initialize data *\/\n    _sidata = .;\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >APP_RAM\n\n    \/* Zero-initialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >APP_RAM\n\n    \/* Uninitialized data section\n    Data placed into this section will remain unchanged across reboots. *\/\n    .uninitialized (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _suninitialized = .; \/* define a global symbol at uninitialized start; currently unused *\/\n        *(.uninitialized)\n        *(.uninitialized*)\n\n        . = ALIGN(4);\n        _euninitialized = .; \/* define a global symbol at uninitialized end; currently unused *\/\n    } >APP_RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\t      PROVIDE ( end = . );\n\t      PROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >APP_RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >APP_RAM\n\n    \/* Remove exception unwinding information, since CircuitPython\n       does not support this GCC feature. *\/\n    \/DISCARD\/ :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.ARM.exidx*)\n    }\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2d9d8fcc5b874b464ec964d6833abb5d6c7b132b","subject":"Update LPC11U68.ld","message":"Update LPC11U68.ld\n","repos":"Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos","old_file":"TARGET_NXP\/TARGET_LPC11U6X\/TOOLCHAIN_GCC_CR\/TARGET_LPC11U68\/LPC11U68.ld","new_file":"TARGET_NXP\/TARGET_LPC11U6X\/TOOLCHAIN_GCC_CR\/TARGET_LPC11U68\/LPC11U68.ld","new_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC11U68\n * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Sat Jun 14 15:26:54 JST 2014\n *\/\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\/*GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)*\/\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 \/* 32K bytes *\/\n  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 \/* 2K bytes *\/\n  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_32 = 0x10000000+0x100 + 0x8000-0x100;\n  __top_Ram1_2 = 0x20000000 + 0x800;\n  __top_Ram2USB_2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n\t\t*(.text.ResetISR)\n        *(.text.SystemInit)\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \/* possible MTB section for Ram1_2 *\/\n    .mtb_buffer_RAM2 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM2*))\n        KEEP(*(.mtb.$RAM1_2*))\n    } > Ram1_2 \n    \n    \/* DATA section for Ram1_2 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_2)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 AT>MFlash256\n    \/* possible MTB section for Ram2USB_2 *\/\n    .mtb_buffer_RAM3 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM3*))\n        KEEP(*(.mtb.$RAM2USB_2*))\n    } > Ram2USB_2 \n    \n    \/* DATA section for Ram2USB_2 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2USB_2)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/\n    \n    \/* Default MTB section *\/\n    .mtb_buffer_default (NOLOAD) :\n    {\n       KEEP(*(.mtb*))\n    } > Ram0_32 \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_32\n\n\t\n\t\/* Main DATA section (Ram0_32) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_32 AT>MFlash256\n\n    \/* BSS section for Ram1_2 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2\n    \/* BSS section for Ram2USB_2 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_32\n        \n    \/* NOINIT section for Ram1_2 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 \n    \/* NOINIT section for Ram2USB_2 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_32 - 0);\n}\n","old_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC11U68\n * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Sat Jun 14 15:26:54 JST 2014\n *\/\n\nGROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 \/* 32K bytes *\/\n  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 \/* 2K bytes *\/\n  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_32 = 0x10000000 + 0x8000;\n  __top_Ram1_2 = 0x20000000 + 0x800;\n  __top_Ram2USB_2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        __vectors_start__ = ABSOLUTE(.) ;\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \/* possible MTB section for Ram1_2 *\/\n    .mtb_buffer_RAM2 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM2*))\n        KEEP(*(.mtb.$RAM1_2*))\n    } > Ram1_2 \n    \n    \/* DATA section for Ram1_2 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_2)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 AT>MFlash256\n    \/* possible MTB section for Ram2USB_2 *\/\n    .mtb_buffer_RAM3 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM3*))\n        KEEP(*(.mtb.$RAM2USB_2*))\n    } > Ram2USB_2 \n    \n    \/* DATA section for Ram2USB_2 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2USB_2)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/\n    \n    \/* Default MTB section *\/\n    .mtb_buffer_default (NOLOAD) :\n    {\n       KEEP(*(.mtb*))\n    } > Ram0_32 \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_32\n\n\t\n\t\/* Main DATA section (Ram0_32) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_32 AT>MFlash256\n\n    \/* BSS section for Ram1_2 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2\n    \/* BSS section for Ram2USB_2 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_32\n        \n    \/* NOINIT section for Ram1_2 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 \n    \/* NOINIT section for Ram2USB_2 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_32 - 0);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"17de68b4b0f28e6944a8e60373bb449e90b92016","subject":"append bss section","message":"append bss section\n","repos":"tjjh89017\/arm-slave,tjjh89017\/arm-slave","old_file":"src\/kernel.ld","new_file":"src\/kernel.ld","new_contents":"OUTPUT_ARCH(arm)\nENTRY(_start)\n\nENTRY_SVC_STACK_SIZE = 0x1000;\n\nSECTIONS\n{\n\t. = 0x10000;\n\t.start_section : {\n\t\tboot.o(.text .text.*)\n\t\tstart.o(.text .text.*)\n\n\t\tboot.o(.rodata .rodata.*)\n\t\tstart.o(.rodata .rodata.*)\n\n\t\tboot.o(.data .data.*)\n\t\tstart.o(.data .data.*)\n\n\t\tPROVIDE(boot_data_start = .);\n\t\tPROVIDE(boot_bss_start = .);\n\n\t\tboot.o(.bss .bss.* COMMON)\n\t\tstart.o(.bss .bss.* COMMON)\n\n\t\t. = ALIGN(0x1000);\n\t\tPROVIDE(boot_bss_end = .);\n\n\t\t\/* define a stack for boot *\/\n\t\t. += ENTRY_SVC_STACK_SIZE;\n\t\tPROVIDE(svc_stack = .);\n\n\t\t. = ALIGN(0x4000);\n\t\t\/* for kernel page table *\/\n\t\tPROVIDE(_kernel_pgd = .);\n\t\t. += 0x4000;\n\n\t\t\/* for user page table *\/\n\t\tPROVIDE(_user_pgd = .);\n\t\t. += 0x1000;\n\n\t\tPROVIDE(boot_data_end = .);\n\t}\n\n\t. = ALIGN(0x1000);\n\n\tPROVIDE(data_start = .);\n\t.data : {\n\t\t*(.data .data.*)\n\t}\n\tPROVIDE(data_end = .);\n\tPROVIDE(bss_start = .);\n\t.bss : {\n\t\t*(.bss .bss.* COMMON)\n\t}\n\tPROVIDE(bss_end = .);\n\n\t. = ALIGN(0x1000);\n\tPROVIDE(end = .);\n}\n","old_contents":"OUTPUT_ARCH(arm)\nENTRY(_start)\n\nENTRY_SVC_STACK_SIZE = 0x1000;\n\nSECTIONS\n{\n\t. = 0x10000;\n\t.start_section : {\n\t\tboot.o(.text .text.*)\n\t\tstart.o(.text .text.*)\n\n\t\tboot.o(.rodata .rodata.*)\n\t\tstart.o(.rodata .rodata.*)\n\n\t\tboot.o(.data .data.*)\n\t\tstart.o(.data .data.*)\n\n\t\tPROVIDE(boot_data_start = .);\n\t\tPROVIDE(boot_bss_start = .);\n\n\t\tboot.o(.bss .bss.* COMMON)\n\t\tstart.o(.bss .bss.* COMMON)\n\n\t\t. = ALIGN(0x1000);\n\t\tPROVIDE(boot_bss_end = .);\n\n\t\t\/* define a stack for boot *\/\n\t\t. += ENTRY_SVC_STACK_SIZE;\n\t\tPROVIDE(svc_stack = .);\n\n\t\t. = ALIGN(0x4000);\n\t\t\/* for kernel page table *\/\n\t\tPROVIDE(_kernel_pgd = .);\n\t\t. += 0x4000;\n\n\t\t\/* for user page table *\/\n\t\tPROVIDE(_user_pgd = .);\n\t\t. += 0x1000;\n\n\t\tPROVIDE(boot_data_end = .);\n\t}\n\n\t. = ALIGN(0x1000);\n\n\tPROVIDE(data_start = .);\n\n\tPROVIDE(data_end = .);\n\tPROVIDE(bss_start = .);\n\n\tPROVIDE(bss_end = .);\n\n\t. = ALIGN(0x1000);\n\tPROVIDE(end = .);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5e96070c27ecd0901c4501666d1f5b274adadf94","subject":"linker script: Remove KEEP from RAM-resident sections","message":"linker script: Remove KEEP from RAM-resident sections\n\nReduce RAM usage when not all data\/bss sections in source files were used.\n","repos":"hwmaier\/esp-idf,mashaoze\/esp-idf,MIhanguangyi\/esp-idf,wmpluto\/esp-idf,www220\/esp-idf,dantonets\/Pingzee-ESP32,Hermiedapwdrman\/esp-idf,MIhanguangyi\/esp-idf,jaracil\/esp-idf,armada-ai\/esp-idf,empoweredhomes\/esp-idf,empoweredhomes\/esp-idf,armada-ai\/esp-idf,www220\/esp-idf,wmpluto\/esp-idf,nineisk\/esp-idf,hwmaier\/esp-idf,tidyjiang8\/esp-idf-zh,empoweredhomes\/esp-idf,dschaefer\/esp-idf,www220\/esp-idf,nineisk\/esp-idf,dschaefer\/esp-idf,dantonets\/Pingzee-ESP32,espressif\/esp-idf,tidyjiang8\/esp-idf-zh,ajs124\/esp-idf,ajs124\/esp-idf,mashaoze\/esp-idf,Hermiedapwdrman\/esp-idf,daiyinger\/esp-idf,Hermiedapwdrman\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf,nineisk\/esp-idf,tidyjiang8\/esp-idf-zh,espressif\/esp-idf,armada-ai\/esp-idf,dschaefer\/esp-idf,dantonets\/Pingzee-ESP32,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,icamgo\/esp-idf,Hermiedapwdrman\/esp-idf,daiyinger\/esp-idf,shukyisme\/esp-idf-kwik,icamgo\/esp-idf,dschaefer\/esp-idf,dantonets\/Pingzee-ESP32,espressif\/esp-idf,wmpluto\/esp-idf,empoweredhomes\/esp-idf,shukyisme\/esp-idf-kwik,jaracil\/esp-idf,empoweredhomes\/esp-idf,hwmaier\/esp-idf,armada-ai\/esp-idf,MIhanguangyi\/esp-idf,MIhanguangyi\/esp-idf,icamgo\/esp-idf,jaracil\/esp-idf,shukyisme\/esp-idf-kwik,daiyinger\/esp-idf,nineisk\/esp-idf,icamgo\/esp-idf,MIhanguangyi\/esp-idf,shukyisme\/esp-idf-kwik,espressif\/esp-idf,jaracil\/esp-idf,hwmaier\/esp-idf,tidyjiang8\/esp-idf-zh,ajs124\/esp-idf,www220\/esp-idf,ajs124\/esp-idf,wmpluto\/esp-idf,www220\/esp-idf,Hermiedapwdrman\/esp-idf,tidyjiang8\/esp-idf-zh,daiyinger\/esp-idf,dschaefer\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    KEEP(*(.bss))\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c0a94cda073ef18aa2bc820e6e01a38e6db11d01","subject":"px4-same70xplained-v1:Ensure _ebss will be 4 byte aligned","message":"px4-same70xplained-v1:Ensure _ebss will be 4 byte aligned\n","repos":"acfloria\/Firmware,krbeverx\/Firmware,dagar\/Firmware,jlecoeur\/Firmware,dagar\/Firmware,mje-nz\/PX4-Firmware,krbeverx\/Firmware,Aerotenna\/Firmware,acfloria\/Firmware,krbeverx\/Firmware,dagar\/Firmware,Aerotenna\/Firmware,PX4\/Firmware,mcgill-robotics\/Firmware,mcgill-robotics\/Firmware,jlecoeur\/Firmware,dagar\/Firmware,jlecoeur\/Firmware,mje-nz\/PX4-Firmware,dagar\/Firmware,PX4\/Firmware,Aerotenna\/Firmware,acfloria\/Firmware,mcgill-robotics\/Firmware,krbeverx\/Firmware,acfloria\/Firmware,dagar\/Firmware,jlecoeur\/Firmware,krbeverx\/Firmware,mje-nz\/PX4-Firmware,krbeverx\/Firmware,Aerotenna\/Firmware,mcgill-robotics\/Firmware,dagar\/Firmware,Aerotenna\/Firmware,mcgill-robotics\/Firmware,acfloria\/Firmware,jlecoeur\/Firmware,jlecoeur\/Firmware,PX4\/Firmware,mcgill-robotics\/Firmware,mje-nz\/PX4-Firmware,Aerotenna\/Firmware,mcgill-robotics\/Firmware,PX4\/Firmware,mje-nz\/PX4-Firmware,jlecoeur\/Firmware,mje-nz\/PX4-Firmware,mje-nz\/PX4-Firmware,acfloria\/Firmware,jlecoeur\/Firmware,acfloria\/Firmware,PX4\/Firmware,krbeverx\/Firmware,PX4\/Firmware,PX4\/Firmware,Aerotenna\/Firmware","old_file":"nuttx-configs\/px4-same70xplained-v1\/scripts\/flash-sram.ld","new_file":"nuttx-configs\/px4-same70xplained-v1\/scripts\/flash-sram.ld","new_contents":"\/****************************************************************************\n * configs\/same70-xplained\/scripts\/flash-sram.ld\n *\n *   Copyright (C) 2015 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The SAME70Q21 has 2048Kb of FLASH beginning at address 0x0040:0000 and\n * 384Kb of SRAM beginining at 0x2040:0000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0400:0000 address range (Assuming that ITCM is not enable).\n *\/\n\nMEMORY\n{\n\tflash (rx) : ORIGIN = 0x00400000, LENGTH = 2048K\n\tsram (rwx) : ORIGIN = 0x20400000, LENGTH = 384K\n}\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nENTRY(_stext)\n\nSECTIONS\n{\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > flash\n\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\t*(.init_array .init_array.*)\n\t\t_einit = ABSOLUTE(.);\n\t} > flash\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > flash\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > flash\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > sram AT > flash\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > sram\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n}\n","old_contents":"\/****************************************************************************\n * configs\/same70-xplained\/scripts\/flash-sram.ld\n *\n *   Copyright (C) 2015 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The SAME70Q21 has 2048Kb of FLASH beginning at address 0x0040:0000 and\n * 384Kb of SRAM beginining at 0x2040:0000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0400:0000 address range (Assuming that ITCM is not enable).\n *\/\n\nMEMORY\n{\n\tflash (rx) : ORIGIN = 0x00400000, LENGTH = 2048K\n\tsram (rwx) : ORIGIN = 0x20400000, LENGTH = 384K\n}\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nENTRY(_stext)\n\nSECTIONS\n{\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > flash\n\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\t*(.init_array .init_array.*)\n\t\t_einit = ABSOLUTE(.);\n\t} > flash\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > flash\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > flash\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > sram AT > flash\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t_ebss = ABSOLUTE(.);\n\t} > sram\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"5b1bc13b394977438a5092fcf2a5b0503d3ba17a","subject":"Fix linker issue for Sketches > 32k","message":"Fix linker issue for Sketches > 32k\n","repos":"qtonthat\/Energia,radiolok\/Energia,DavidUser\/Energia,cevatbostancioglu\/Energia,bobintornado\/Energia,radiolok\/Energia,vigneshmanix\/Energia,NoPinky\/Energia,qtonthat\/Energia,croberts15\/Energia,croberts15\/Energia,martianmartin\/Energia,brianonn\/Energia,NoPinky\/Energia,danielohh\/Energia,dvdvideo1234\/Energia,martianmartin\/Energia,DavidUser\/Energia,vigneshmanix\/Energia,DavidUser\/Energia,vigneshmanix\/Energia,brianonn\/Energia,vigneshmanix\/Energia,sanyaade-iot\/Energia,bobintornado\/Energia,battosai30\/Energia,radiolok\/Energia,dvdvideo1234\/Energia,battosai30\/Energia,martianmartin\/Energia,cevatbostancioglu\/Energia,qtonthat\/Energia,bobintornado\/Energia,danielohh\/Energia,danielohh\/Energia,DavidUser\/Energia,brianonn\/Energia,battosai30\/Energia,bobintornado\/Energia,radiolok\/Energia,martianmartin\/Energia,croberts15\/Energia,danielohh\/Energia,danielohh\/Energia,NoPinky\/Energia,dvdvideo1234\/Energia,dvdvideo1234\/Energia,danielohh\/Energia,NoPinky\/Energia,cevatbostancioglu\/Energia,croberts15\/Energia,bobintornado\/Energia,sanyaade-iot\/Energia,vigneshmanix\/Energia,radiolok\/Energia,brianonn\/Energia,danielohh\/Energia,brianonn\/Energia,qtonthat\/Energia,croberts15\/Energia,dvdvideo1234\/Energia,cevatbostancioglu\/Energia,cevatbostancioglu\/Energia,brianonn\/Energia,battosai30\/Energia,NoPinky\/Energia,martianmartin\/Energia,sanyaade-iot\/Energia,battosai30\/Energia,qtonthat\/Energia,vigneshmanix\/Energia,NoPinky\/Energia,DavidUser\/Energia,NoPinky\/Energia,brianonn\/Energia,martianmartin\/Energia,qtonthat\/Energia,martianmartin\/Energia,DavidUser\/Energia,dvdvideo1234\/Energia,cevatbostancioglu\/Energia,sanyaade-iot\/Energia,radiolok\/Energia,bobintornado\/Energia,vigneshmanix\/Energia,sanyaade-iot\/Energia,sanyaade-iot\/Energia,bobintornado\/Energia,radiolok\/Energia,qtonthat\/Energia,battosai30\/Energia,croberts15\/Energia,dvdvideo1234\/Energia,battosai30\/Energia,croberts15\/Energia,DavidUser\/Energia,sanyaade-iot\/Energia,cevatbostancioglu\/Energia","old_file":"hardware\/lm4f\/cores\/lm4f\/lm4fcpp.ld","new_file":"hardware\/lm4f\/cores\/lm4f\/lm4fcpp.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"unknown","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"97d46143e282dd639ab0c6b05f05d52b5526f21b","subject":"Reduce binary size by cutting aligments","message":"Reduce binary size by cutting aligments\n","repos":"Dentosal\/rust_os,Dentosal\/rust_os,Dentosal\/rust_os","old_file":"buildsystem\/linker.ld","new_file":"buildsystem\/linker.ld","new_contents":"OUTPUT_FORMAT(\"elf64-x86-64\") \/* FLAT BINARY DOES NOT WORK, ELF WORKS *\/\nENTRY(start)\n\nSECTIONS {\n  . = 0x0000000000010000;\n\n  .entry :\n  {\n    \/* ensure that the kernel entry code is at the beginning *\/\n    *(.entry)\n  }\n  .text : ALIGN(0x200)\n  {\n    *(.text .text.*)\n  }\n  .rodata : ALIGN(0x200)\n  {\n    *(.rodata .rodata.*)\n  }\n\n  .data : ALIGN(0x200)\n  {\n    *(.data .data.*)\n  }\n\n  .data.rel.ro : ALIGN(0x200)\n  {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n  }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf64-x86-64\") \/* FLAT BINARY DOES NOT WORK, ELF WORKS *\/\nENTRY(start)\n\nSECTIONS {\n  . = 0x0000000000010000;\n\n  .entry :\n  {\n    \/* ensure that the kernel entry code is at the beginning *\/\n    *(.entry)\n  }\n  .text : ALIGN(0x1000)\n  {\n    *(.text .text.*)\n  }\n  .rodata : ALIGN(0x1000)\n  {\n    *(.rodata .rodata.*)\n  }\n\n  .data : ALIGN(0x1000)\n  {\n    *(.data .data.*)\n  }\n\n  .data.rel.ro : ALIGN(0x1000)\n  {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n  }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5acf6f9819ebb9ba075f2c4abc041056ed253a99","subject":"ldoc now expects markdown formatting.","message":"ldoc now expects markdown formatting.\n","repos":"drcforbin\/rwte,drcforbin\/rwte,drcforbin\/rwte,drcforbin\/rwte","old_file":"config.ld","new_file":"config.ld","new_contents":"-- ldoc config file\n\nfile = {\n    \"src\/lua\/logging.cpp\",\n    \"src\/lua\/term.cpp\",\n    \"src\/lua\/window.cpp\"\n}\n\nproject = \"rwte\"\ntitle = \"rwte Lua Documentation\"\ndescription = \"rwte lua\"\n\ndir = \"docs\"\nformat = \"markdown\"\ntopics = {}\n","old_contents":"-- ldoc config file\n\nfile = {\n    \"src\/lua\/logging.cpp\",\n    \"src\/lua\/term.cpp\",\n    \"src\/lua\/window.cpp\"\n}\n\nproject = \"rwte\"\ntitle = \"rwte Lua Documentation\"\ndescription = \"rwte lua\"\n\ndir = \"docs\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2bd871df2a2f2376b04a7d853eecbcab7a50b575","subject":"sparc: add _image_rodata_start\/end to linker script","message":"sparc: add _image_rodata_start\/end to linker script\n\nThis adds the _image_rodata_start and _image_rodata_end\nsymbols to SPARC's arch linker script.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/sparc\/linker.ld","new_file":"include\/arch\/sparc\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019-2020 Cobham Gaisler AB\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file for SPARC\n *\/\n\n#include <soc.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t\/* Trap table alignment required by SPARC V8 specification. *\/\n\t\t. = ALIGN(0x1000);\n\t\t_image_text_start = .;\n\n\t\t*(.text.traptable)\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.stub)\n\t\t*(.gnu.linkonce.t.*)\n\t} GROUP_LINK_IN(REGION_TEXT)\n\n    _image_text_end = .;\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(8);\n\t\t *(.rodata)\n\t\t *(.rodata.*)\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.rodata1)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n\t} GROUP_LINK_IN(REGION_RODATA)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n\n    _image_rom_end = .;\n\n    __data_rom_start = .;\n\n\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(8);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(.data.*)\n\t\t *(.gnu.linkonce.d.*)\n\t\tSORT(CONSTRUCTORS)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(REGION_DATA_VMA, REGION_DATA_LMA)\n\n#include <linker\/common-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.dynbss)\n\t\t *(.bss)\n\t\t *(.bss.*)\n\t\t *(.gnu.linkonce.b.*)\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_LINK_IN(REGION_BSS)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(.noinit.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n\t} GROUP_LINK_IN(REGION_BSS)\n\n#include <linker\/cplusplus-ram.ld>\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n    \/DISCARD\/ : { *(.gnu_debuglink) }\n    \/DISCARD\/ : { *(.gnu.lto_*) }\n\n    SECTION_PROLOGUE(.gnu.attributes, 0,)\n\t{\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","old_contents":"\/*\n * Copyright (c) 2019-2020 Cobham Gaisler AB\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file for SPARC\n *\/\n\n#include <soc.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t\/* Trap table alignment required by SPARC V8 specification. *\/\n\t\t. = ALIGN(0x1000);\n\t\t_image_text_start = .;\n\n\t\t*(.text.traptable)\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.stub)\n\t\t*(.gnu.linkonce.t.*)\n\t} GROUP_LINK_IN(REGION_TEXT)\n\n    _image_text_end = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(8);\n\t\t *(.rodata)\n\t\t *(.rodata.*)\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.rodata1)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n\t} GROUP_LINK_IN(REGION_RODATA)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rom_end = .;\n    __data_rom_start = .;\n\n\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(8);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(.data.*)\n\t\t *(.gnu.linkonce.d.*)\n\t\tSORT(CONSTRUCTORS)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(REGION_DATA_VMA, REGION_DATA_LMA)\n\n#include <linker\/common-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.dynbss)\n\t\t *(.bss)\n\t\t *(.bss.*)\n\t\t *(.gnu.linkonce.b.*)\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_LINK_IN(REGION_BSS)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(.noinit.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n\t} GROUP_LINK_IN(REGION_BSS)\n\n#include <linker\/cplusplus-ram.ld>\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n    \/DISCARD\/ : { *(.gnu_debuglink) }\n    \/DISCARD\/ : { *(.gnu.lto_*) }\n\n    SECTION_PROLOGUE(.gnu.attributes, 0,)\n\t{\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"491d6dae5541247dff7de0a3cc812102311719eb","subject":"Don't align all the sections, just the user-code and text.","message":"Don't align all the sections, just the user-code and text.","repos":"sam-truscott\/tinker-kernel,sam-truscott\/tinker-kernel","old_file":"src\/arch\/ppc32\/gdb_sim\/linker.ld","new_file":"src\/arch\/ppc32\/gdb_sim\/linker.ld","new_contents":"\/*\n *\n * SOS Source Code\n * __________________\n *\n *  [2009] - [2013] Samuel Steven Truscott\n *  All Rights Reserved.\n *\/\n \n\/* http:\/\/www.redhat.com\/docs\/manuals\/enterprise\/RHEL-4-Manual\/gnu-linker\/memory.html *\/\nENTRY (__kernel_start)\n\n__VECTOR_SIZE = 0xF00;\n__VECTOR_STACK_SIZE = 0x1000;\n\nMEMORY \n{\n\tRAM : ORIGIN = 0x00000000, LENGTH = 0x8000000 \/* 128MB *\/\n\t\/* FLASH : ORIGIN = 0xFE000000, LENGTH = 0xetc *\/\n}\n\nSECTIONS{\n    \n    \/* interrupt vector table *\/\n    .ivt 0x100 (NOLOAD) : {\n        __ivt = .;\n        *(.vectors)\n        . += __VECTOR_SIZE;\n    } > RAM\n    \n    .ivt_stack 0x1000 (NOLOAD) : {\n        __ivt_stack = .;\n        . += __VECTOR_STACK_SIZE;\n        __ivt_stack_end = .;\n    } > RAM\n    \n    \/* Small Block Started by Symbol *\/\n    .sbss ALIGN (0x1000): {\n        *(.sbss)\n    }>RAM\n    \n        \/* Block Started by Symbol *\/\n    .bss ALIGN (0x1000) : {\n        *(COMMON)\n        *(.bss)\n    }>RAM\n    \n    \/* read only data *\/\n    .rodata ALIGN (0x1000) : {\n        *(.rodata)\n        *(.rodata*)\n        *(.eh_frame)\n        *(.eh_frame_hdr)\n    }>RAM\n    \n    \/* static data *\/\n    .sdata ALIGN (0x4) : {\n        *(.sdata)\n    }>RAM\n    \n    \/* data *\/\n    .data ALIGN (0x4) : {\n        *(.data.*)\n        *(.got2)\n        *(.fixup)\n    }>RAM\n   \n\t\/* code *\/\n    .text ALIGN (0x4) : {\n        __text = .;\n    \t*(.boot)\n    \t*(.vector_code)\n    \t. = ALIGN(4);\n        *(.text)\n        __text_end = .;\n    }>RAM\n    \n    .user_text ALIGN (0x1000) :\n    {\n        __user_text = .;\n        *(.user_text)\n        _euser_text = ALIGN(0x1000);\n    }\n        \n    .user_data ALIGN (0x4) :\n    {\n        __user_data = .;\n        *(.user_data)\n        __euser = ALIGN(0x1000);\n    }>RAM\n    \n    .dynsym ALIGN (0x1000) : { *(.dynsym) }>RAM\n    .dynstr ALIGN (0x1000) : { *(.dynstr) }>RAM\n    .hash   ALIGN (0x1000) : { *(.hash)   }>RAM\n    \n    .memory_pool ALIGN (0x1000) (NOLOAD) : {\n    \tend = .;\n    }>RAM\n    \n    .page_table 0x7F00000 (NOLOAD) : {\n        *(.page_table)\n    }>RAM\n}\n","old_contents":"\/*\n *\n * SOS Source Code\n * __________________\n *\n *  [2009] - [2013] Samuel Steven Truscott\n *  All Rights Reserved.\n *\/\n \n\/* http:\/\/www.redhat.com\/docs\/manuals\/enterprise\/RHEL-4-Manual\/gnu-linker\/memory.html *\/\nENTRY (__kernel_start)\n\n__VECTOR_SIZE = 0xF00;\n__VECTOR_STACK_SIZE = 0x1000;\n\nMEMORY \n{\n\tRAM : ORIGIN = 0x00000000, LENGTH = 0x8000000 \/* 128MB *\/\n\t\/* FLASH : ORIGIN = 0xFE000000, LENGTH = 0xetc *\/\n}\n\nSECTIONS{\n    \n    \/* interrupt vector table *\/\n    .ivt 0x100 (NOLOAD) : {\n        __ivt = .;\n        *(.vectors)\n        . += __VECTOR_SIZE;\n    } > RAM\n    \n    .ivt_stack 0x1000 (NOLOAD) : {\n        __ivt_stack = .;\n        . += __VECTOR_STACK_SIZE;\n        __ivt_stack_end = .;\n    } > RAM\n    \n    \/* Small Block Started by Symbol *\/\n    .sbss ALIGN (0x1000): {\n        *(.sbss)\n    }>RAM\n    \n    \/* read only data *\/\n    .rodata ALIGN (0x1000) : {\n        *(.rodata)\n        *(.rodata*)\n        *(.eh_frame)\n        *(.eh_frame_hdr)\n    }>RAM\n\n    \/* Block Started by Symbol *\/\n    .bss ALIGN (0x1000) : {\n        *(COMMON)\n        *(.bss)\n    }>RAM\n    \n    \/* static data *\/\n    .sdata ALIGN (0x1000) : {\n        *(.sdata)\n    }>RAM\n    \n    \/* data *\/\n    .data ALIGN (0x1000) : {\n        *(.data.*)\n        *(.got2)\n        *(.fixup)\n    }>RAM\n   \n\t\/* code *\/\n    .text ALIGN (0x1000) : {\n        __text = .;\n    \t*(.boot)\n    \t*(.vector_code)\n    \t. = ALIGN(4);\n        *(.text)\n        __text_end = .;\n    }>RAM\n    \n    .user_text ALIGN (0x1000) :\n    {\n        __user_text = .;\n        *(.user_text)\n        _euser_text = ALIGN(0x1000);\n    }\n        \n    .user_data ALIGN (0x1000) :\n    {\n        __user_data = .;\n        *(.user_data)\n        __euser = ALIGN(0x1000);\n    }>RAM\n    \n    .dynsym ALIGN (0x1000) : { *(.dynsym) }>RAM\n    .dynstr ALIGN (0x1000) : { *(.dynstr) }>RAM\n    .hash   ALIGN (0x1000) : { *(.hash)   }>RAM\n    \n    .memory_pool ALIGN (0x1000) (NOLOAD) : {\n    \tend = .;\n    }>RAM\n    \n    .page_table 0x7F00000 (NOLOAD) : {\n        *(.page_table)\n    }>RAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2ef67d03f1eab12da7c7fd170526caa2ba13ea86","subject":"linker.ld: This comment doesn't make sense, remove","message":"linker.ld: This comment doesn't make sense, remove\n","repos":"akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix","old_file":"linker.ld","new_file":"linker.ld","new_contents":"\/************************************************************************\n *   Copyright (c) 2012 \u00c1kos Kov\u00e1cs - Akosix operating system\n *              http:\/\/akoskovacs.github.com\/Akosix\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION\n * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n ************************************************************************\/\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    . = 0x00100000;\n    .multiboot_header :\n    {\n    __start_multiboot_header = .;\n        boot\/multiboot.o\n    __end_multiboot_header = .;\n    }\n\n    \/* This stage the paging is still\n     *  not enabled (physical = virtual).\n     *\/\n    . = 0x00100000;\n    .setup :\n    {\n    __start_setup = .;\n        boot\/boot.o\n        boot\/pgsetup.o\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    \/* The following code and data has to be mapped after\n     * the first 3GB address space, giving the kernel 1GB usable\n     * address space.\n     *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf)\n    {\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n        *(.text)\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n\n    .note ALIGN(page_size) : AT(ADDR(.note) - hhalf)\n    {\n        *(.note.gnu.build-id)\n    }\n}\n","old_contents":"\/************************************************************************\n *   Copyright (c) 2012 \u00c1kos Kov\u00e1cs - Akosix operating system\n *              http:\/\/akoskovacs.github.com\/Akosix\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n * \n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, \n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE\n * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION\n * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n ************************************************************************\/\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    \/* The multiboot header must be \n     * in the first 8192 bytes in the image,\n     * therefore 4096 (0x1000) will be fine.\n     *\/\n    . = 0x00001000;\n    .multiboot_header :\n    {\n    __start_multiboot_header = .;\n        boot\/multiboot.o\n    __end_multiboot_header = .;\n    }\n\n    \/* This stage the paging is still \n     *  not enabled (physical = virtual).\n     *\/\n    . = 0x00100000;\n    .setup :\n    {\n    __start_setup = .;\n        boot\/boot.o\n        boot\/pgsetup.o\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    \/* The following code and data has to be mapped after \n     * the first 3GB address space, giving the kernel 1GB usable\n     * address space. \n     *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf) \n    {\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n        *(.text)\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n\n    .note ALIGN(page_size) : AT(ADDR(.note) - hhalf)\n    {\n        *(.note.gnu.build-id)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"1826036a8363de825668185c3d5b4efd2820d353","subject":"cc3200: Increase main stack size to 2K.","message":"cc3200: Increase main stack size to 2K.\n\nIncreasing it from 1K to 2K gives more freedom to the callback\nhandlers, before this, simply nesting a function call into a\nprintf would cause a stack overflow.\n","repos":"emfcamp\/micropython,feilongfl\/micropython,HenrikSolver\/micropython,vriera\/micropython,ernesto-g\/micropython,jimkmc\/micropython,puuu\/micropython,orionrobots\/micropython,mianos\/micropython,chrisdearman\/micropython,infinnovation\/micropython,adafruit\/circuitpython,ceramos\/micropython,jmarcelino\/pycom-micropython,turbinenreiter\/micropython,Peetz0r\/micropython-esp32,dinau\/micropython,cnoviello\/micropython,heisewangluo\/micropython,dmazzella\/micropython,tdautc19841202\/micropython,kostyll\/micropython,ganshun666\/micropython,mpalomer\/micropython,blmorris\/micropython,blazewicz\/micropython,slzatz\/micropython,MrSurly\/micropython,ChuckM\/micropython,galenhz\/micropython,misterdanb\/micropython,matthewelse\/micropython,PappaPeppar\/micropython,dxxb\/micropython,vitiral\/micropython,oopy\/micropython,alex-march\/micropython,oopy\/micropython,alex-robbins\/micropython,rubencabrera\/micropython,ernesto-g\/micropython,bvernoux\/micropython,noahwilliamsson\/micropython,suda\/micropython,tralamazza\/micropython,dxxb\/micropython,ericsnowcurrently\/micropython,SHA2017-badge\/micropython-esp32,Peetz0r\/micropython-esp32,pramasoul\/micropython,ryannathans\/micropython,kerneltask\/micropython,toolmacher\/micropython,heisewangluo\/micropython,redbear\/micropython,ryannathans\/micropython,mhoffma\/micropython,pozetroninc\/micropython,supergis\/micropython,galenhz\/micropython,cwyark\/micropython,TDAbboud\/micropython,tdautc19841202\/micropython,kostyll\/micropython,mianos\/micropython,firstval\/micropython,torwag\/micropython,trezor\/micropython,chrisdearman\/micropython,selste\/micropython,SHA2017-badge\/micropython-esp32,lbattraw\/micropython,suda\/micropython,dhylands\/micropython,EcmaXp\/micropython,dinau\/micropython,puuu\/micropython,dhylands\/micropython,noahchense\/micropython,blmorris\/micropython,MrSurly\/micropython-esp32,swegener\/micropython,lowRISC\/micropython,tdautc19841202\/micropython,micropython\/micropython-esp32,AriZuu\/micropython,mgyenik\/micropython,skybird6672\/micropython,paul-xxx\/micropython,adafruit\/circuitpython,cnoviello\/micropython,galenhz\/micropython,paul-xxx\/micropython,selste\/micropython,emfcamp\/micropython,omtinez\/micropython,noahwilliamsson\/micropython,dxxb\/micropython,alex-march\/micropython,jlillest\/micropython,ruffy91\/micropython,Timmenem\/micropython,henriknelson\/micropython,cnoviello\/micropython,dinau\/micropython,heisewangluo\/micropython,alex-robbins\/micropython,pozetroninc\/micropython,danicampora\/micropython,jmarcelino\/pycom-micropython,xyb\/micropython,drrk\/micropython,HenrikSolver\/micropython,torwag\/micropython,turbinenreiter\/micropython,emfcamp\/micropython,oopy\/micropython,ryannathans\/micropython,supergis\/micropython,lbattraw\/micropython,redbear\/micropython,mgyenik\/micropython,infinnovation\/micropython,neilh10\/micropython,ceramos\/micropython,AriZuu\/micropython,mianos\/micropython,noahwilliamsson\/micropython,feilongfl\/micropython,ganshun666\/micropython,cnoviello\/micropython,torwag\/micropython,mpalomer\/micropython,alex-march\/micropython,MrSurly\/micropython,ernesto-g\/micropython,omtinez\/micropython,Timmenem\/micropython,hiway\/micropython,cloudformdesign\/micropython,torwag\/micropython,heisewangluo\/micropython,ernesto-g\/micropython,noahchense\/micropython,alex-march\/micropython,dxxb\/micropython,blazewicz\/micropython,suda\/micropython,xyb\/micropython,torwag\/micropython,mianos\/micropython,rubencabrera\/micropython,stonegithubs\/micropython,swegener\/micropython,xhat\/micropython,EcmaXp\/micropython,ericsnowcurrently\/micropython,noahchense\/micropython,deshipu\/micropython,swegener\/micropython,orionrobots\/micropython,orionrobots\/micropython,xyb\/micropython,vriera\/micropython,cloudformdesign\/micropython,toolmacher\/micropython,rubencabrera\/micropython,praemdonck\/micropython,tdautc19841202\/micropython,toolmacher\/micropython,jimkmc\/micropython,tuc-osg\/micropython,xyb\/micropython,cloudformdesign\/micropython,kerneltask\/micropython,ganshun666\/micropython,TDAbboud\/micropython,xhat\/micropython,dhylands\/micropython,paul-xxx\/micropython,jmarcelino\/pycom-micropython,rubencabrera\/micropython,utopiaprince\/micropython,SHA2017-badge\/micropython-esp32,mhoffma\/micropython,adamkh\/micropython,ruffy91\/micropython,tuc-osg\/micropython,suda\/micropython,cloudformdesign\/micropython,toolmacher\/micropython,puuu\/micropython,ChuckM\/micropython,hosaka\/micropython,selste\/micropython,ericsnowcurrently\/micropython,bvernoux\/micropython,lowRISC\/micropython,lbattraw\/micropython,tralamazza\/micropython,noahchense\/micropython,utopiaprince\/micropython,matthewelse\/micropython,kerneltask\/micropython,jlillest\/micropython,mhoffma\/micropython,dmazzella\/micropython,ruffy91\/micropython,suda\/micropython,kostyll\/micropython,EcmaXp\/micropython,jimkmc\/micropython,neilh10\/micropython,skybird6672\/micropython,redbear\/micropython,dhylands\/micropython,danicampora\/micropython,xyb\/micropython,hiway\/micropython,Peetz0r\/micropython-esp32,hosaka\/micropython,AriZuu\/micropython,ruffy91\/micropython,pfalcon\/micropython,ceramos\/micropython,MrSurly\/micropython-esp32,Peetz0r\/micropython-esp32,xuxiaoxin\/micropython,blmorris\/micropython,adafruit\/micropython,blazewicz\/micropython,henriknelson\/micropython,tobbad\/micropython,henriknelson\/micropython,skybird6672\/micropython,skybird6672\/micropython,galenhz\/micropython,henriknelson\/micropython,hiway\/micropython,toolmacher\/micropython,ahotam\/micropython,misterdanb\/micropython,mhoffma\/micropython,lowRISC\/micropython,kerneltask\/micropython,martinribelotta\/micropython,heisewangluo\/micropython,bvernoux\/micropython,MrSurly\/micropython-esp32,jimkmc\/micropython,turbinenreiter\/micropython,utopiaprince\/micropython,adamkh\/micropython,slzatz\/micropython,vitiral\/micropython,hiway\/micropython,HenrikSolver\/micropython,praemdonck\/micropython,ChuckM\/micropython,tuc-osg\/micropython,alex-robbins\/micropython,matthewelse\/micropython,infinnovation\/micropython,vitiral\/micropython,infinnovation\/micropython,alex-robbins\/micropython,orionrobots\/micropython,utopiaprince\/micropython,AriZuu\/micropython,henriknelson\/micropython,PappaPeppar\/micropython,adafruit\/micropython,turbinenreiter\/micropython,utopiaprince\/micropython,MrSurly\/micropython,stonegithubs\/micropython,ruffy91\/micropython,adamkh\/micropython,misterdanb\/micropython,cwyark\/micropython,blmorris\/micropython,MrSurly\/micropython,mpalomer\/micropython,cwyark\/micropython,supergis\/micropython,alex-march\/micropython,ceramos\/micropython,deshipu\/micropython,noahwilliamsson\/micropython,slzatz\/micropython,ceramos\/micropython,MrSurly\/micropython-esp32,swegener\/micropython,pramasoul\/micropython,dxxb\/micropython,danicampora\/micropython,jlillest\/micropython,omtinez\/micropython,tobbad\/micropython,matthewelse\/micropython,tdautc19841202\/micropython,neilh10\/micropython,blmorris\/micropython,selste\/micropython,deshipu\/micropython,trezor\/micropython,xuxiaoxin\/micropython,alex-robbins\/micropython,trezor\/micropython,paul-xxx\/micropython,omtinez\/micropython,adamkh\/micropython,ernesto-g\/micropython,jmarcelino\/pycom-micropython,neilh10\/micropython,xhat\/micropython,hosaka\/micropython,adafruit\/micropython,redbear\/micropython,vitiral\/micropython,ericsnowcurrently\/micropython,feilongfl\/micropython,stonegithubs\/micropython,martinribelotta\/micropython,chrisdearman\/micropython,cwyark\/micropython,Timmenem\/micropython,adafruit\/circuitpython,stonegithubs\/micropython,pozetroninc\/micropython,xuxiaoxin\/micropython,TDAbboud\/micropython,lbattraw\/micropython,drrk\/micropython,stonegithubs\/micropython,ChuckM\/micropython,trezor\/micropython,kostyll\/micropython,ahotam\/micropython,AriZuu\/micropython,tralamazza\/micropython,xhat\/micropython,turbinenreiter\/micropython,ahotam\/micropython,pfalcon\/micropython,vriera\/micropython,tobbad\/micropython,pfalcon\/micropython,redbear\/micropython,warner83\/micropython,HenrikSolver\/micropython,ganshun666\/micropython,tralamazza\/micropython,martinribelotta\/micropython,noahchense\/micropython,selste\/micropython,vriera\/micropython,cloudformdesign\/micropython,micropython\/micropython-esp32,infinnovation\/micropython,micropython\/micropython-esp32,emfcamp\/micropython,ganshun666\/micropython,tuc-osg\/micropython,galenhz\/micropython,pramasoul\/micropython,oopy\/micropython,praemdonck\/micropython,swegener\/micropython,firstval\/micropython,cwyark\/micropython,puuu\/micropython,matthewelse\/micropython,lowRISC\/micropython,martinribelotta\/micropython,slzatz\/micropython,danicampora\/micropython,noahwilliamsson\/micropython,jlillest\/micropython,praemdonck\/micropython,dinau\/micropython,praemdonck\/micropython,Timmenem\/micropython,neilh10\/micropython,chrisdearman\/micropython,mpalomer\/micropython,SHA2017-badge\/micropython-esp32,pramasoul\/micropython,Peetz0r\/micropython-esp32,kostyll\/micropython,warner83\/micropython,matthewelse\/micropython,martinribelotta\/micropython,MrSurly\/micropython,PappaPeppar\/micropython,adafruit\/circuitpython,mgyenik\/micropython,ChuckM\/micropython,vriera\/micropython,slzatz\/micropython,pozetroninc\/micropython,micropython\/micropython-esp32,paul-xxx\/micropython,mpalomer\/micropython,adafruit\/circuitpython,pramasoul\/micropython,SHA2017-badge\/micropython-esp32,pozetroninc\/micropython,jimkmc\/micropython,xuxiaoxin\/micropython,ryannathans\/micropython,hosaka\/micropython,adafruit\/micropython,firstval\/micropython,mianos\/micropython,mhoffma\/micropython,EcmaXp\/micropython,tuc-osg\/micropython,chrisdearman\/micropython,supergis\/micropython,omtinez\/micropython,warner83\/micropython,pfalcon\/micropython,mgyenik\/micropython,misterdanb\/micropython,HenrikSolver\/micropython,lbattraw\/micropython,kerneltask\/micropython,dmazzella\/micropython,mgyenik\/micropython,EcmaXp\/micropython,TDAbboud\/micropython,vitiral\/micropython,danicampora\/micropython,deshipu\/micropython,blazewicz\/micropython,tobbad\/micropython,feilongfl\/micropython,hiway\/micropython,PappaPeppar\/micropython,ryannathans\/micropython,misterdanb\/micropython,PappaPeppar\/micropython,rubencabrera\/micropython,bvernoux\/micropython,drrk\/micropython,xuxiaoxin\/micropython,trezor\/micropython,adafruit\/circuitpython,adafruit\/micropython,hosaka\/micropython,emfcamp\/micropython,tobbad\/micropython,MrSurly\/micropython-esp32,drrk\/micropython,micropython\/micropython-esp32,oopy\/micropython,jlillest\/micropython,lowRISC\/micropython,warner83\/micropython,skybird6672\/micropython,puuu\/micropython,bvernoux\/micropython,ericsnowcurrently\/micropython,pfalcon\/micropython,dinau\/micropython,adamkh\/micropython,dmazzella\/micropython,firstval\/micropython,drrk\/micropython,supergis\/micropython,blazewicz\/micropython,ahotam\/micropython,deshipu\/micropython,TDAbboud\/micropython,warner83\/micropython,cnoviello\/micropython,jmarcelino\/pycom-micropython,ahotam\/micropython,dhylands\/micropython,orionrobots\/micropython,xhat\/micropython,feilongfl\/micropython,firstval\/micropython,Timmenem\/micropython","old_file":"cc3200\/application.lds","new_file":"cc3200\/application.lds","new_contents":"\/*\n * This file is part of the Micro Python project, http:\/\/micropython.org\/\n *\n * The MIT License (MIT)\n *\n * Copyright (c) 2015 Daniel Campora\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\/\n\n__stack_size__    = 2K;       \/* interrupts are handled within this stack *\/\n__min_heap_size__ = 8K;\n__rtos_heap_size  = 16K;\n\nMEMORY\n{\n    SRAMB (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000\n    SRAM  (rwx) : ORIGIN = 0x20004000, LENGTH = 0x0003C000\n}\n\nENTRY(ResetISR)\n\nSECTIONS\n{  \n    \/* place the FreeRTOS heap (the micropython stack will live here) *\/\n    .rtos_heap (NOLOAD) :\n    {\n        . = ALIGN(8);\n        *(.rtos_heap*)\n        . = ALIGN(8);\n    } > SRAMB\n\n    .text :\n    {\n        _text = .;\n        KEEP(*(.intvecs))\n        *(.text*)\n        *(.rodata*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(8);\n    } > SRAM\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n        _etext = .;\n    } > SRAM\n\n    .data :\n    {\n        . = ALIGN(8);\n        _data = .;\n        *(.data*)\n        . = ALIGN(8);\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        . = ALIGN(8);\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        _ebss = .;\n    } > SRAM\n\n    \/* place here functions that are only called during boot up, *\/\n    \/* that way, we can re-use this area for the micropython heap *\/\n    .boot :\n    {\n        . = ALIGN(8);\n        _boot = .;\n        *(.boot*)\n        . = ALIGN(8);\n        _eboot = .;\n    } > SRAM\n     \n    \/* allocate the micropython heap *\/\n    .heap :\n    {\n        . = ALIGN(8);\n        _heap = .;\n        . = . + __min_heap_size__;\n        . = . + (ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ - ABSOLUTE(.));\n        . = ALIGN(8);\n        _eheap = .;\n    } > SRAM\n\n    \/* allocate the main stack *\/\n    .stack ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ :\n    {\n        . = ALIGN(8);\n        _stack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > SRAM\n}\n","old_contents":"\/*\n * This file is part of the Micro Python project, http:\/\/micropython.org\/\n *\n * The MIT License (MIT)\n *\n * Copyright (c) 2015 Daniel Campora\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\/\n\n__stack_size__    = 1K;       \/* interrupts are handled within this stack *\/\n__min_heap_size__ = 8K;\n__rtos_heap_size  = 16K;\n\nMEMORY\n{\n    SRAMB (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000\n    SRAM  (rwx) : ORIGIN = 0x20004000, LENGTH = 0x0003C000\n}\n\nENTRY(ResetISR)\n\nSECTIONS\n{  \n    \/* place the FreeRTOS heap (the micropython stack will live here) *\/\n    .rtos_heap (NOLOAD) :\n    {\n        . = ALIGN(8);\n        *(.rtos_heap*)\n        . = ALIGN(8);\n    } > SRAMB\n\n    .text :\n    {\n        _text = .;\n        KEEP(*(.intvecs))\n        *(.text*)\n        *(.rodata*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(8);\n    } > SRAM\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n        _etext = .;\n    } > SRAM\n\n    .data :\n    {\n        . = ALIGN(8);\n        _data = .;\n        *(.data*)\n        . = ALIGN(8);\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        . = ALIGN(8);\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        _ebss = .;\n    } > SRAM\n\n    \/* place here functions that are only called during boot up, *\/\n    \/* that way, we can re-use this area for the micropython heap *\/\n    .boot :\n    {\n        . = ALIGN(8);\n        _boot = .;\n        *(.boot*)\n        . = ALIGN(8);\n        _eboot = .;\n    } > SRAM\n     \n    \/* allocate the micropython heap *\/\n    .heap :\n    {\n        . = ALIGN(8);\n        _heap = .;\n        . = . + __min_heap_size__;\n        . = . + (ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ - ABSOLUTE(.));\n        . = ALIGN(8);\n        _eheap = .;\n    } > SRAM\n\n    \/* allocate the main stack *\/\n    .stack ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ :\n    {\n        . = ALIGN(8);\n        _stack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > SRAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b51e02a1051cca9931bbc9cf35db7d772029e68b","subject":"nrf51822: Keep .app.* sections","message":"nrf51822: Keep .app.* sections\n\nThis fix is similar to one found on sam4l loader script.\n","repos":"google\/tock-on-titan,google\/tock-on-titan,google\/tock-on-titan","old_file":"src\/chips\/nrf51822\/loader.ld","new_file":"src\/chips\/nrf51822\/loader.ld","new_contents":"\/*\n * This file is part of StormLoader, the Storm Bootloader\n *\n * StormLoader is free software: you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation, either version 3 of the License, or\n * (at your option) any later version.\n *\n * StormLoader is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with Foobar.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n *\n * Copyright 2014, Michael Andersen <m.andersen@eecs.berkeley.edu>\n *\n * This file is largely copied from the Atmel supplied linker scripts\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.) \n\nMEMORY\n{\n  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 256K\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _textstart = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        KEEP (*(.syscalls))\n\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _sapps = .;\n        KEEP (*(.app.*))\n        _eapps = .;\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n    _textend = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n\n        . = ALIGN(8);\n        *(.app_memory)\n\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","old_contents":"\/*\n * This file is part of StormLoader, the Storm Bootloader\n *\n * StormLoader is free software: you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation, either version 3 of the License, or\n * (at your option) any later version.\n *\n * StormLoader is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with Foobar.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n *\n * Copyright 2014, Michael Andersen <m.andersen@eecs.berkeley.edu>\n *\n * This file is largely copied from the Atmel supplied linker scripts\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.) \n\nMEMORY\n{\n  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 256K\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _textstart = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        KEEP (*(.syscalls))\n\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _sapps = .;\n        *(.app.*)\n        _eapps = .;\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n    _textend = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n\n        . = ALIGN(8);\n        *(.app_memory)\n\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9f8b788fe556579684d7f888e7196002f2fc8e00","subject":"esp8266: Switch floating-point arith routines to BootROM.","message":"esp8266: Switch floating-point arith routines to BootROM.\n","repos":"adafruit\/micropython,adafruit\/circuitpython,tobbad\/micropython,blazewicz\/micropython,ryannathans\/micropython,kerneltask\/micropython,PappaPeppar\/micropython,matthewelse\/micropython,tralamazza\/micropython,kerneltask\/micropython,mhoffma\/micropython,turbinenreiter\/micropython,dxxb\/micropython,turbinenreiter\/micropython,blazewicz\/micropython,torwag\/micropython,Timmenem\/micropython,dxxb\/micropython,dinau\/micropython,cwyark\/micropython,kerneltask\/micropython,alex-march\/micropython,hiway\/micropython,PappaPeppar\/micropython,alex-robbins\/micropython,alex-march\/micropython,torwag\/micropython,infinnovation\/micropython,hiway\/micropython,TDAbboud\/micropython,hosaka\/micropython,trezor\/micropython,lowRISC\/micropython,oopy\/micropython,torwag\/micropython,alex-robbins\/micropython,chrisdearman\/micropython,tuc-osg\/micropython,hiway\/micropython,SHA2017-badge\/micropython-esp32,alex-robbins\/micropython,torwag\/micropython,henriknelson\/micropython,matthewelse\/micropython,ganshun666\/micropython,emfcamp\/micropython,MrSurly\/micropython,AriZuu\/micropython,hiway\/micropython,jmarcelino\/pycom-micropython,dxxb\/micropython,toolmacher\/micropython,dmazzella\/micropython,redbear\/micropython,tuc-osg\/micropython,alex-robbins\/micropython,pfalcon\/micropython,tralamazza\/micropython,pramasoul\/micropython,dinau\/micropython,MrSurly\/micropython-esp32,Timmenem\/micropython,AriZuu\/micropython,TDAbboud\/micropython,pramasoul\/micropython,micropython\/micropython-esp32,Peetz0r\/micropython-esp32,pozetroninc\/micropython,alex-march\/micropython,PappaPeppar\/micropython,ryannathans\/micropython,HenrikSolver\/micropython,jmarcelino\/pycom-micropython,ryannathans\/micropython,henriknelson\/micropython,turbinenreiter\/micropython,MrSurly\/micropython-esp32,ryannathans\/micropython,tobbad\/micropython,alex-march\/micropython,Timmenem\/micropython,hosaka\/micropython,dinau\/micropython,blazewicz\/micropython,TDAbboud\/micropython,deshipu\/micropython,bvernoux\/micropython,tralamazza\/micropython,selste\/micropython,cwyark\/micropython,micropython\/micropython-esp32,chrisdearman\/micropython,mhoffma\/micropython,turbinenreiter\/micropython,cwyark\/micropython,adafruit\/circuitpython,henriknelson\/micropython,matthewelse\/micropython,deshipu\/micropython,tralamazza\/micropython,redbear\/micropython,SHA2017-badge\/micropython-esp32,bvernoux\/micropython,bvernoux\/micropython,selste\/micropython,lowRISC\/micropython,ganshun666\/micropython,adafruit\/circuitpython,Peetz0r\/micropython-esp32,Peetz0r\/micropython-esp32,tobbad\/micropython,matthewelse\/micropython,redbear\/micropython,infinnovation\/micropython,MrSurly\/micropython,swegener\/micropython,blazewicz\/micropython,pramasoul\/micropython,oopy\/micropython,cwyark\/micropython,trezor\/micropython,oopy\/micropython,MrSurly\/micropython-esp32,chrisdearman\/micropython,dinau\/micropython,adafruit\/micropython,Peetz0r\/micropython-esp32,emfcamp\/micropython,tuc-osg\/micropython,TDAbboud\/micropython,chrisdearman\/micropython,pozetroninc\/micropython,emfcamp\/micropython,cwyark\/micropython,redbear\/micropython,oopy\/micropython,jmarcelino\/pycom-micropython,pramasoul\/micropython,puuu\/micropython,SHA2017-badge\/micropython-esp32,selste\/micropython,adafruit\/circuitpython,swegener\/micropython,toolmacher\/micropython,AriZuu\/micropython,Timmenem\/micropython,mhoffma\/micropython,tuc-osg\/micropython,ryannathans\/micropython,alex-march\/micropython,tobbad\/micropython,hosaka\/micropython,henriknelson\/micropython,emfcamp\/micropython,toolmacher\/micropython,toolmacher\/micropython,dxxb\/micropython,henriknelson\/micropython,alex-robbins\/micropython,trezor\/micropython,redbear\/micropython,micropython\/micropython-esp32,Peetz0r\/micropython-esp32,bvernoux\/micropython,deshipu\/micropython,selste\/micropython,mhoffma\/micropython,deshipu\/micropython,MrSurly\/micropython,infinnovation\/micropython,pfalcon\/micropython,hiway\/micropython,PappaPeppar\/micropython,MrSurly\/micropython-esp32,adafruit\/micropython,infinnovation\/micropython,pozetroninc\/micropython,hosaka\/micropython,pfalcon\/micropython,puuu\/micropython,adafruit\/micropython,pozetroninc\/micropython,PappaPeppar\/micropython,AriZuu\/micropython,ganshun666\/micropython,lowRISC\/micropython,chrisdearman\/micropython,Timmenem\/micropython,tobbad\/micropython,matthewelse\/micropython,adafruit\/circuitpython,puuu\/micropython,emfcamp\/micropython,turbinenreiter\/micropython,kerneltask\/micropython,lowRISC\/micropython,HenrikSolver\/micropython,HenrikSolver\/micropython,lowRISC\/micropython,SHA2017-badge\/micropython-esp32,MrSurly\/micropython-esp32,micropython\/micropython-esp32,adafruit\/micropython,swegener\/micropython,swegener\/micropython,MrSurly\/micropython,dinau\/micropython,selste\/micropython,deshipu\/micropython,puuu\/micropython,pfalcon\/micropython,mhoffma\/micropython,puuu\/micropython,HenrikSolver\/micropython,toolmacher\/micropython,adafruit\/circuitpython,SHA2017-badge\/micropython-esp32,pfalcon\/micropython,torwag\/micropython,kerneltask\/micropython,AriZuu\/micropython,tuc-osg\/micropython,matthewelse\/micropython,pozetroninc\/micropython,jmarcelino\/pycom-micropython,TDAbboud\/micropython,pramasoul\/micropython,trezor\/micropython,dxxb\/micropython,bvernoux\/micropython,dmazzella\/micropython,blazewicz\/micropython,ganshun666\/micropython,dmazzella\/micropython,infinnovation\/micropython,HenrikSolver\/micropython,jmarcelino\/pycom-micropython,hosaka\/micropython,trezor\/micropython,oopy\/micropython,swegener\/micropython,micropython\/micropython-esp32,MrSurly\/micropython,ganshun666\/micropython,dmazzella\/micropython","old_file":"esp8266\/eagle.rom.addr.v6.ld","new_file":"esp8266\/eagle.rom.addr.v6.ld","new_contents":"PROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\n__adddf3 = 0x4000c538;\n__addsf3 = 0x4000c180;\n__divdf3 = 0x4000cb94;\n__divdi3 = 0x4000ce60;\n__divsi3 = 0x4000dc88;\n__extendsfdf2 = 0x4000cdfc;\n__fixdfsi = 0x4000ccb8;\n__fixunsdfsi = 0x4000cd00;\n__fixunssfsi = 0x4000c4c4;\n__floatsidf = 0x4000e2f0;\n__floatsisf = 0x4000e2ac;\n__floatunsidf = 0x4000e2e8;\n__floatunsisf = 0x4000e2a4;\n__muldf3 = 0x4000c8f0;\n__muldi3 = 0x40000650;\n__mulsf3 = 0x4000c3dc;\n__subdf3 = 0x4000c688;\n__subsf3 = 0x4000c268;\n__truncdfsf2 = 0x4000cd5c;\n__udivdi3 = 0x4000d310;\n__udivsi3 = 0x4000e21c;\n__umoddi3 = 0x4000d770;\n__umodsi3 = 0x4000e268;\n__umulsidi3 = 0x4000dcf0;\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( _ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( _ets_run = 0x40000e04 );\nPROVIDE ( _ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( _ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( _ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n","old_contents":"PROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\n__divdi3 = 0x4000ce60;\n__divsi3 = 0x4000dc88;\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\n__muldi3 = 0x40000650;\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\n__udivdi3 = 0x4000d310;\n__udivsi3 = 0x4000e21c;\n__umoddi3 = 0x4000d770;\n__umodsi3 = 0x4000e268;\n__umulsidi3 = 0x4000dcf0;\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( _ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( _ets_run = 0x40000e04 );\nPROVIDE ( _ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( _ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( _ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"fd8b526f7c3a9ea801a8ba6f04d91c7eaa145ffe","subject":"add two APIs into esp32beta.rom.spiflash.ld to fix compile error","message":"add two APIs into esp32beta.rom.spiflash.ld to fix compile error\n\nWhen config flash mode as QIO mode, the error that esp_rom_spiflash_wait_idle\nand esp_rom_spiflash_config_readmode are undefined happens when compile, so\nadd these two APIs to fix the error.\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32s2beta\/ld\/esp32s2beta.rom.spiflash.ld","new_file":"components\/esp_rom\/esp32s2beta\/ld\/esp32s2beta.rom.spiflash.ld","new_contents":"\/*\n\tSPI flash driver function, compatibility names.\n*\/\n\n\nPROVIDE ( cache_ibus_mmu_set_rom = cache_ibus_mmu_set );\nPROVIDE ( Cache_Read_Disable_rom = Cache_Read_Disable );\nPROVIDE ( Cache_Read_Enable_rom = Cache_Read_Enable );\nPROVIDE ( cache_dbus_mmu_set_rom = cache_dbus_mmu_set );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = dummy_len_plus);\nPROVIDE ( g_ticks_per_us_pro = g_ticks_per_us );\nPROVIDE ( g_rom_flashchip = SPI_flashchip_data );\nPROVIDE ( g_rom_spiflash_chip = SPI_flashchip_data );\nPROVIDE ( esp_rom_spiflash_config_param = SPIParamCfg );\nPROVIDE ( esp_rom_spiflash_read = SPIRead );\nPROVIDE ( esp_rom_spiflash_read_status = SPI_read_status );\nPROVIDE ( esp_rom_spiflash_read_statushigh = SPI_read_status_high );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = SPI_user_command_read );\nPROVIDE ( esp_rom_spiflash_write = SPIWrite );\nPROVIDE ( esp_rom_spiflash_write_encrypted_disable = SPI_Write_Encrypt_Disable );\nPROVIDE ( esp_rom_spiflash_write_encrypted_enable = SPI_Write_Encrypt_Enable );\nPROVIDE ( esp_rom_spiflash_config_clk = SPIClkConfig );\nPROVIDE ( esp_rom_spiflash_select_qio_pins = SelectSpiQIO );\nPROVIDE ( esp_rom_spiflash_unlock = SPIUnlock );\nPROVIDE ( esp_rom_spiflash_erase_sector = SPIEraseSector );\nPROVIDE ( esp_rom_spiflash_wait_idle = SPI_Wait_Idle );\nPROVIDE ( esp_rom_spiflash_config_readmode = SPIReadModeCnfig );\n","old_contents":"\/*\n\tSPI flash driver function, compatibility names.\n*\/\n\n\nPROVIDE ( cache_ibus_mmu_set_rom = cache_ibus_mmu_set );\nPROVIDE ( Cache_Read_Disable_rom = Cache_Read_Disable );\nPROVIDE ( Cache_Read_Enable_rom = Cache_Read_Enable );\nPROVIDE ( cache_dbus_mmu_set_rom = cache_dbus_mmu_set );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = dummy_len_plus);\nPROVIDE ( g_ticks_per_us_pro = g_ticks_per_us );\nPROVIDE ( g_rom_flashchip = SPI_flashchip_data );\nPROVIDE ( g_rom_spiflash_chip = SPI_flashchip_data );\nPROVIDE ( esp_rom_spiflash_config_param = SPIParamCfg );\nPROVIDE ( esp_rom_spiflash_read = SPIRead );\nPROVIDE ( esp_rom_spiflash_read_status = SPI_read_status );\nPROVIDE ( esp_rom_spiflash_read_statushigh = SPI_read_status_high );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = SPI_user_command_read );\nPROVIDE ( esp_rom_spiflash_write = SPIWrite );\nPROVIDE ( esp_rom_spiflash_write_encrypted_disable = SPI_Write_Encrypt_Disable );\nPROVIDE ( esp_rom_spiflash_write_encrypted_enable = SPI_Write_Encrypt_Enable );\nPROVIDE ( esp_rom_spiflash_config_clk = SPIClkConfig );\nPROVIDE ( esp_rom_spiflash_select_qio_pins = SelectSpiQIO );\nPROVIDE ( esp_rom_spiflash_unlock = SPIUnlock );\nPROVIDE ( esp_rom_spiflash_erase_sector = SPIEraseSector );\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b4f1b8b71c7212c3e7ce64081c39eceafb9e1e8e","subject":"Tidied up the linker.","message":"Tidied up the linker.\n\nWhen I use some libc stuff, I'll be able to see if we need the DISCARD\nsection or not.\n","repos":"dancollins\/libnarm,dancollins\/libnarm,dancollins\/libnarm","old_file":"examples\/blinky\/stm32f051k8_flash.ld","new_file":"examples\/blinky\/stm32f051k8_flash.ld","new_contents":"\/*   Copyright 2015 Dan Collins & Tim Dawson\r\n *\r\n *   Licensed under the Apache License, Version 2.0 (the \"License\");\r\n *   you may not use this file except in compliance with the License.\r\n *   You may obtain a copy of the License at\r\n *\r\n *       http:\/\/www.apache.org\/licenses\/LICENSE-2.0\r\n *\r\n *   Unless required by applicable law or agreed to in writing, software\r\n *   distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *   See the License for the specific language governing permissions and\r\n *   limitations under the License.\r\n *\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\n\/* Point this to the end of RAM *\/\r\n_estack = 0x20001FFF;\r\n\r\n\/* This will create a linker error if the heap and stack wont fit in RAM *\/\r\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\r\n\r\n\/* Specify the address for flash and RAM *\/\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K\r\n\tRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  \/* Make sure the first thing in flash is our vector table! *\/\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    \/* This is the actual application code *\/\r\n    *(.text)\r\n    *(.text*)\r\n    \/* XXX: These sections will be empty in ARM Cortex projects, but we need\r\n     * them to satisfy the linker? *\/\r\n    *(.glue_7)\r\n    *(.glue_7t)\r\n    \/* These are for exceptions, which aren't used in C. However, it would\r\n     * have data into a C++ project. *\/\r\n    *(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    \/* This just points to the end of the text section *\/\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n  } >FLASH\r\n\r\n  \/* This is where we store all the initialised variables. The startup script\r\n   * will copy this data out into the RAM. This is for read-only data. *\/\r\n  .rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.rodata)\r\n    *(.rodata*)\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  \/* XXX: This has something to do with loop unwinding? I couldn't find much\r\n   * information, but everyone seems to have this. So do we! *\/\r\n  .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n  .ARM : {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } >FLASH\r\n\r\n  \/* This points to the data section for the startup script *\/\r\n  _sidata = LOADADDR(.data);\r\n\r\n  \/* This is where we store all the initialised variables. The startup script\r\n   * will copy this data out into the RAM. *\/\r\n  .data :\r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .; \/* Start of the data section *\/\r\n    *(.data)\r\n    *(.data*)\r\n\r\n    . = ALIGN(4);\r\n    _edata = .; \/* End of the data section *\/\r\n  } >RAM AT> FLASH\r\n\r\n\r\n  \/* This is where we store uninitialised data. It will get zeroed by the\r\n   * start up script *\/\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    _sbss = .; \/* Start of the uninitialised data section *\/\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .; \/* End of the uninitialised data section *\/\r\n    __bss_end__ = _ebss;\r\n  } >RAM\r\n\r\n  \/* We use this to ensure that the user heap wont collide with the stack *\/\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(4);\r\n  } >RAM\r\n\r\n  \/* XXX: What? *\/\r\n  \/* Remove information from the standard libraries *\/\r\n  \/DISCARD\/ :\r\n  {\r\n    libc.a ( * )\r\n    libm.a ( * )\r\n    libgcc.a ( * )\r\n  }\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n","old_contents":"\/*   Copyright 2015 Dan Collins & Tim Dawson\r\n *\r\n *   Licensed under the Apache License, Version 2.0 (the \"License\");\r\n *   you may not use this file except in compliance with the License.\r\n *   You may obtain a copy of the License at\r\n *\r\n *       http:\/\/www.apache.org\/licenses\/LICENSE-2.0\r\n *\r\n *   Unless required by applicable law or agreed to in writing, software\r\n *   distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *   See the License for the specific language governing permissions and\r\n *   limitations under the License.\r\n *\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\n\/* Point this to the end of RAM *\/\r\n_estack = 0x20001FFF;\r\n\r\n\/* This will create a linker error if the heap and stack wont fit in RAM *\/\r\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\r\n\r\n\/* Specify the address for flash and RAM *\/\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K\r\n\tRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  \/* Make sure the first thing in flash is our vector table! *\/\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    \/* This is the actual application code *\/\r\n    *(.text)\r\n    *(.text*)\r\n    \/* XXX: These sections will be empty in ARM Cortex projects, but we need\r\n     * them to satisfy the linker? *\/\r\n    *(.glue_7)\r\n    *(.glue_7t)\r\n    \/* These are for exceptions, which aren't used in C. However, it would\r\n     * have data into a C++ project. *\/\r\n    *(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    \/* This just points to the end of the text section *\/\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n  } >FLASH\r\n\r\n  \/* This is where we store all the initialised variables. The startup script\r\n   * will copy this data out into the RAM. This is for read-only data. *\/\r\n  .rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.rodata)\r\n    *(.rodata*)\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  \/* XXX: This has something to do with loop unwinding? I couldn't find much\r\n   * information, but everyone seems to have this. So do we! *\/\r\n  .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n  .ARM : {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } >FLASH\r\n\r\n\/* XXX: This stuff is for ELF. Pretty sure we don't need it, and we'll delete it\r\n * when compilation succeeds without it *\/\r\n\/*\r\n  .preinit_array:\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } >FLASH\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } >FLASH\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } >FLASH\r\n*\/\r\n\r\n  \/* This points to the data section for the startup script *\/\r\n  _sidata = LOADADDR(.data);\r\n\r\n  \/* This is where we store all the initialised variables. The startup script\r\n   * will copy this data out into the RAM. *\/\r\n  .data :\r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .; \/* Start of the data section *\/\r\n    *(.data)\r\n    *(.data*)\r\n\r\n    . = ALIGN(4);\r\n    _edata = .; \/* End of the data section *\/\r\n  } >RAM AT> FLASH\r\n\r\n\r\n  \/* This is where we store uninitialised data. It will get zeroed by the\r\n   * start up script *\/\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    _sbss = .; \/* Start of the uninitialised data section *\/\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .; \/* End of the uninitialised data section *\/\r\n    __bss_end__ = _ebss;\r\n  } >RAM\r\n\r\n  \/* We use this to ensure that the user heap wont collide with the stack *\/\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(4);\r\n  } >RAM\r\n\r\n  \/* XXX: What? *\/\r\n  \/* Remove information from the standard libraries *\/\r\n  \/DISCARD\/ :\r\n  {\r\n    libc.a ( * )\r\n    libm.a ( * )\r\n    libgcc.a ( * )\r\n  }\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bb5f2e507c9cbb738e8753cbf38ef05281262ad0","subject":"Added undefined Default_Handler assertion in stm32f100xx.ld","message":"Added undefined Default_Handler assertion in stm32f100xx.ld\n","repos":"masilvabustos\/CabbageOS,masilvabustos\/CabbageOS","old_file":"hw\/stm32f100xx.ld","new_file":"hw\/stm32f100xx.ld","new_contents":"\n\nASSERT(DEFINED(Default_Handler), \"Default_Handler not defined!\")\n\nSECTIONS {\n\t\n\t__end_of_ram__ = ALIGN(ORIGIN(SRAM) + LENGTH(SRAM), 4) ;\n\n\t.cm3.isr_vector ORIGIN(FLASH) : {\n\t\tLONG(__end_of_ram__)\n\t\t\/* ARM Thumb interwork requires the LSB to be set.\t*\n\t\t * (Can ld do this automatically?) \t\t\t*\/ \t\t\t\n\t\tLONG(_start \t\t| 1)\n\t\tPROVIDE(Default_Handler\t\t= _start);\n\t\tPROVIDE(NMI_Handler \t\t= Default_Handler);\n\t\tPROVIDE(HardFault_Handler \t= Default_Handler);\n \t\tPROVIDE(MemManage_Handler \t= Default_Handler);\n\t\tPROVIDE(BusFault_Handler \t= Default_Handler);\n\t\tPROVIDE(SVC_Handler\t\t= Default_Handler);\n\t\tPROVIDE(PendSV_Handler \t\t= Default_Handler);\n\t\tPROVIDE(SysTick_Handler \t= Default_Handler);\n\t\tLONG(NMI_Handler \t| 1)\n\t\tLONG(HardFault_Handler \t| 1)\n\t\tLONG(MemManage_Handler \t| 1)\n\t\tLONG(BusFault_Handler \t| 1)\n\t\t\/*LONG(UsageFault_Handler | 1)*\/\n\t\t. = 0x2c ; \/* Reserved *\/\n\t\tLONG(SVC_Handler \t| 1)\n\t\t\/*LONG(DebugMon_Handler\t| 1)*\/\n\t\t. = 0x38 ; \/* Reserved *\/\n\t\tLONG(PendSV_Handler\t| 1)\n\t\tLONG(SysTick_Handler\t| 1)\n\t\t\n\t\t. = 0x40 ;\n\t\t* (.irqsr_vector)\n\t\t\n\t\t. = 0x134 ;\n\n\t} > FLASH\n\n\n\t.text : { \n\t\t. = ALIGN(4) ;\n\t\t* (.text) \n\t} > FLASH\n\t\n\t__data_lma__ = . ;\n\t.data : AT(__data_lma__) { \n\t\t__data_vma__ = . ;\n\t\t* (.data) \n\t} > SRAM\n\t__init_data_end = . ;\n\n\t.bss : {\n\t\t* (.bss)\n\t} > SRAM\n\n\t__brk = . ;\n\n\t.stm32f100xx.peripherals_registers : {\n\n\t\t\/* TODO: Add remaing registers *\/\n\t\t. = 0x10800 ;\n\t\tGPIOA_CRL \t= . + 0x00 ;\n\t\tGPIOA_CRH \t= . + 0x04 ;\n\t\tGPIOA_IDR \t= . + 0x08 ;\n\t\tGPIOA_ODR \t= . + 0x0C ;\n\t\tGPIOA_BSRR \t= . + 0x10 ;\n\t\tGPIOA_BRR\t= . + 0x14 ;\n\t\tGPIOA_LCKR\t= . + 0x18 ;\n\t\t\n\t\t. = 0x11000 ;\n\t\tGPIOC_CRL \t= . + 0x00 ;\n\t\tGPIOC_CRH \t= . + 0x04 ;\n\t\tGPIOC_IDR \t= . + 0x08 ;\n\t\tGPIOC_ODR \t= . + 0x0C ;\n\t\tGPIOC_BSRR \t= . + 0x10 ;\n\t\tGPIOC_BRR\t= . + 0x14 ;\n\t\tGPIOC_LCKR\t= . + 0x18 ;\n\n\t\t. = 0x21000 ;\n\t\tRCC_CR\t\t= . + 0x00 ;\n\t\tRCC_CFGR\t= . + 0x04 ;\n\t\tRCC_CIR\t\t= . + 0x08 ;\n\t\tRCC_APB2RSTR\t= . + 0x0C ;\n\t\tRCC_APB1RSTR \t= . + 0x10 ;\n\t\tRCC_AHBENR\t= . + 0x14 ;\n\t\tRCC_APB2ENR\t= . + 0x18 ;\n\t\tRCC_APB1ENR\t= . + 0x1C ;\n\t\tRCC_BDCR\t= . + 0x20 ;\n\t\tRCC_CSR\t\t= . + 0x24 ;\n\t\tRCC_CFGR2\t= . + 0x2C ;\n\n\n\t} > PERIPH\n\n\t.stm32f100xx.peripherals_bitband_alias 0x42000000 : {\n\n\t\t. \t\t= (RCC_APB2ENR \t- ORIGIN(PERIPH)) * 32 ;\n\t\tIOPCEN\t\t=  . +  4 * 4 ;\n\n\t} > PERIPH\t\n}\n\n","old_contents":"\nINPUT(hw.o)\n\nSECTIONS {\n\t\n\t__end_of_ram__ = ALIGN(ORIGIN(SRAM) + LENGTH(SRAM), 4) ;\n\n\t.cm3.isr_vector ORIGIN(FLASH) : {\n\t\tLONG(__end_of_ram__)\n\t\t\/* ARM Thumb interwork requires the LSB to be set.\t*\n\t\t * (Can ld do this automatically?) \t\t\t*\/ \t\t\t\n\t\tLONG(_start \t\t| 1)\n\t\t\/*PROVIDE(Default_Handler\t\t= _start);*\/\n\t\tPROVIDE(NMI_Handler \t\t= Default_Handler);\n\t\tPROVIDE(HardFault_Handler \t= Default_Handler);\n \t\tPROVIDE(MemManage_Handler \t= Default_Handler);\n\t\tPROVIDE(BusFault_Handler \t= Default_Handler);\n\t\tPROVIDE(SVC_Handler\t\t= Default_Handler);\n\t\tPROVIDE(PendSV_Handler \t\t= Default_Handler);\n\t\tPROVIDE(SysTick_Handler \t= Default_Handler);\n\t\tLONG(NMI_Handler \t| 1)\n\t\tLONG(HardFault_Handler \t| 1)\n\t\tLONG(MemManage_Handler \t| 1)\n\t\tLONG(BusFault_Handler \t| 1)\n\t\t\/*LONG(UsageFault_Handler | 1)*\/\n\t\t. = 0x2c ; \/* Reserved *\/\n\t\tLONG(SVC_Handler \t| 1)\n\t\t\/*LONG(DebugMon_Handler\t| 1)*\/\n\t\t. = 0x38 ; \/* Reserved *\/\n\t\tLONG(PendSV_Handler\t| 1)\n\t\tLONG(SysTick_Handler\t| 1)\n\t\t\n\t\t. = 0x40 ;\n\t\t* (.irqsr_vector)\n\t\t\n\t\t. = 0x134 ;\n\n\t} > FLASH\n\n\n\t.text : { \n\t\t. = ALIGN(4) ;\n\t\t* (.text) \n\t} > FLASH\n\t\n\t__data_lma__ = . ;\n\t.data : AT(__data_lma__) { \n\t\t__data_vma__ = . ;\n\t\t* (.data) \n\t} > SRAM\n\t__init_data_end = . ;\n\n\t.bss : {\n\t\t* (.bss)\n\t} > SRAM\n\n\t__brk = . ;\n\n\t.stm32f100xx.peripherals_registers : {\n\n\t\t\/* TODO: Add remaing registers *\/\n\t\t. = 0x10800 ;\n\t\tGPIOA_CRL \t= . + 0x00 ;\n\t\tGPIOA_CRH \t= . + 0x04 ;\n\t\tGPIOA_IDR \t= . + 0x08 ;\n\t\tGPIOA_ODR \t= . + 0x0C ;\n\t\tGPIOA_BSRR \t= . + 0x10 ;\n\t\tGPIOA_BRR\t= . + 0x14 ;\n\t\tGPIOA_LCKR\t= . + 0x18 ;\n\t\t\n\t\t. = 0x11000 ;\n\t\tGPIOC_CRL \t= . + 0x00 ;\n\t\tGPIOC_CRH \t= . + 0x04 ;\n\t\tGPIOC_IDR \t= . + 0x08 ;\n\t\tGPIOC_ODR \t= . + 0x0C ;\n\t\tGPIOC_BSRR \t= . + 0x10 ;\n\t\tGPIOC_BRR\t= . + 0x14 ;\n\t\tGPIOC_LCKR\t= . + 0x18 ;\n\n\t\t. = 0x21000 ;\n\t\tRCC_CR\t\t= . + 0x00 ;\n\t\tRCC_CFGR\t= . + 0x04 ;\n\t\tRCC_CIR\t\t= . + 0x08 ;\n\t\tRCC_APB2RSTR\t= . + 0x0C ;\n\t\tRCC_APB1RSTR \t= . + 0x10 ;\n\t\tRCC_AHBENR\t= . + 0x14 ;\n\t\tRCC_APB2ENR\t= . + 0x18 ;\n\t\tRCC_APB1ENR\t= . + 0x1C ;\n\t\tRCC_BDCR\t= . + 0x20 ;\n\t\tRCC_CSR\t\t= . + 0x24 ;\n\t\tRCC_CFGR2\t= . + 0x2C ;\n\n\n\t} > PERIPH\n\n\t.stm32f100xx.peripherals_bitband_alias 0x42000000 : {\n\n\t\t. \t\t= (RCC_APB2ENR \t- ORIGIN(PERIPH)) * 32 ;\n\t\tIOPCEN\t\t=  . +  4 * 4 ;\n\n\t} > PERIPH\t\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"b2a7920d75278fcfa3d57019cf1efd296e049f8b","subject":"A little clean nosys.lds","message":"A little clean nosys.lds","repos":"vrxfile\/embox-trik,abusalimov\/embox,Kakadu\/embox,embox\/embox,embox\/embox,mike2390\/embox,gzoom13\/embox,Kefir0192\/embox,Kefir0192\/embox,embox\/embox,Kefir0192\/embox,mike2390\/embox,mike2390\/embox,embox\/embox,vrxfile\/embox-trik,vrxfile\/embox-trik,gzoom13\/embox,Kefir0192\/embox,gzoom13\/embox,abusalimov\/embox,abusalimov\/embox,vrxfile\/embox-trik,gzoom13\/embox,Kakadu\/embox,gzoom13\/embox,Kakadu\/embox,vrxfile\/embox-trik,Kefir0192\/embox,embox\/embox,embox\/embox,mike2390\/embox,Kakadu\/embox,mike2390\/embox,abusalimov\/embox,Kakadu\/embox,mike2390\/embox,gzoom13\/embox,Kakadu\/embox,Kefir0192\/embox,vrxfile\/embox-trik,abusalimov\/embox,Kefir0192\/embox,gzoom13\/embox,abusalimov\/embox,mike2390\/embox,Kakadu\/embox,vrxfile\/embox-trik","old_file":"src\/kernel\/nosys.lds","new_file":"src\/kernel\/nosys.lds","new_contents":"\nPROVIDE(irq_dispatch = nosys);\n\nPROVIDE(timer_init = nosys);\nPROVIDE(timer_set = nosys);\nPROVIDE(timer_close = nosys);\nPROVIDE(timers_off = nosys);\nPROVIDE(usleep = nosys);\n","old_contents":"\nPROVIDE(irq_dispatch = nosys);\n\nPROVIDE(printk = nosys);\n\nPROVIDE(timer_init = nosys);\nPROVIDE(timer_set = nosys);\nPROVIDE(timer_close = nosys);\nPROVIDE(timers_off = nosys);\nPROVIDE(usleep = nosys);\n\n\/* XXX remove from here. -- Eldar\nPROVIDE(uart_init = nosys);\n*\/\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"35ed1e445cdf06de130b1cbee882026927587a42","subject":"Add a message for rt_header and _start","message":"Add a message for rt_header and _start\n","repos":"tock\/libtock-rs","old_file":"runtime\/libtock_layout.ld","new_file":"runtime\/libtock_layout.ld","new_contents":"\/* Layout file for Tock process binaries that use libtock-rs. This currently\n * implements static linking, because we do not have a working\n * position-independent relocation solution. This layout works for all\n * platforms libtock-rs supports (ARM and RISC-V).\n *\n * This layout should be included by a script that defines the FLASH and RAM\n * regions for the board as well as TBF_HEADER_SIZE. Here is a an example\n * process binary linker script to get started:\n *     MEMORY {\n *         FLASH (X) : ORIGIN = 0x10000, LENGTH = 0x10000\n *         RAM   (W) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     TBF_HEADER_SIZE = 0x48;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\n * FLASH refers to the area the process binary occupies in flash, including TBF\n * headers. RAM refers to the area the process will have access to in memory.\n * STACK_SIZE is the size of the process' stack (this layout file may round the\n * stack size up for alignment purposes). TBF_HEADER_SIZE must correspond to the\n * --protected-region-size flag passed to elf2tab.\n *\n * This places the flash sections in the following order:\n *     1. .rt_header -- Constants used by runtime initialization.\n *     2. .text      -- Executable code.\n *     3. .rodata    -- Read-only global data (e.g. most string constants).\n *     4. .data      -- Read-write data, copied to RAM at runtime.\n *\n * This places the RAM sections in the following order:\n *     1. .stack -- The stack grows downward. Putting it first gives us\n *                  MPU-based overflow detection.\n *     2. .data  -- Read-write data, initialized by copying from flash.\n *     3. .bss   -- Zero-initialized read-write global data.\n *     4. Heap   -- The heap (optional) comes after .bss and grows upwards to\n *                  the process break.\n *\/\n\n\/* TODO: Should TBF_HEADER_SIZE be configured via a similar mechanism to the\n * stack size? We should see if that is possible.\n *\/\n\n\/* GNU LD looks for `start` as an entry point by default, while LLVM's LLD looks\n * for `_start`. To be compatible with both, we manually specify an entry point.\n *\/\nENTRY(start)\n\nSECTIONS {\n    \/* Sections located in FLASH at runtime.\n     *\/\n\n    \/* Add a section where elf2tab will place the TBF headers, so that the rest\n     * of the FLASH sections are in the right locations. *\/\n    .tbf_header (NOLOAD) : {\n        . = . + TBF_HEADER_SIZE;\n    } > FLASH\n\n    \/* Runtime header. Contains values the linker knows that the runtime needs\n     * to look up.\n     *\/\n    .start ALIGN(4) : {\n        \/* We combine rt_header and _start into a single section. If we don't,\n         * elf2tab does not parse the ELF file correctly for unknown reasons.\n         *\/\n        rt_header = .;\n        LONG(start);\n        LONG(ADDR(.bss) + SIZEOF(.bss)); \/* Initial process break *\/\n        LONG(_stack_top);\n        LONG(SIZEOF(.data));\n        LONG(LOADADDR(.data));\n        LONG(ADDR(.data));\n        LONG(SIZEOF(.bss));\n        LONG(ADDR(.bss));\n\n        *(.start)\n    } > FLASH\n\n    \/* Text section -- the application's code. *\/\n    .text ALIGN(4) : {\n        *(.text.*)\n    } > FLASH\n\n    \/* Read-only data section. Contains strings and other global constants. *\/\n    .rodata ALIGN(4) : {\n        *(.rodata.*)\n        \/* .data is placed after .rodata in flash. data_flash_start is used by\n         * AT() to place .data in flash as well as in rt_header.\n         *\/\n        _data_flash_start = .;\n    } > FLASH\n\n    \/* Sections located in RAM at runtime.\n     *\/\n\n    \/* Reserve space for the stack. Aligned to a multiple of 16 bytes for the\n     * RISC-V calling convention:\n     * https:\/\/riscv.org\/wp-content\/uploads\/2015\/01\/riscv-calling.pdf\n     *\/\n    .stack (NOLOAD) : {\n\t\/* _sram_origin is used by elf2tab:\n\t * https:\/\/github.com\/tock\/elf2tab\/blob\/master\/src\/main.rs#L301\n\t *\/\n        _sram_origin = .;\n        KEEP(*(.stack_buffer))\n        . = ALIGN(16);\n        _stack_top = .;  \/* Used in rt_header *\/\n    } > RAM\n\n    \/* Read-write data section. This is deployed as part of FLASH but is copied\n     * into RAM at runtime.\n     *\/\n    .data ALIGN(4) : AT(_data_flash_start) {\n        data_ram_start = .;\n        \/* .sdata is the RISC-V small data section *\/\n        *(.sdata .data)\n        \/* Pad to word alignment so the relocation loop can use word-sized\n         * copies.\n         *\/\n        . = ALIGN(4);\n    } > RAM\n\n    \/* BSS section. These are zero-initialized static variables. This section is\n     * not copied from FLASH into RAM but rather directly initialized, and is\n     * mainly put in this linker script so that we get an error if it overflows\n     * the RAM region.\n     *\/\n    .bss ALIGN(4) (NOLOAD) : {\n        \/* .sbss is the RISC-V small data section *\/\n        *(.sbss .bss.*)\n    } > RAM\n\n    _heap_start = ADDR(.bss) + SIZEOF(.bss);  \/* Used by rt_header *\/\n\n    \/* Sections we do not need. *\/\n    \/DISCARD\/ :\n    {\n      *(.ARM.exidx .eh_frame)\n    }\n}\n","old_contents":"\/* Layout file for Tock process binaries that use libtock-rs. This currently\n * implements static linking, because we do not have a working\n * position-independent relocation solution. This layout works for all\n * platforms libtock-rs supports (ARM and RISC-V).\n *\n * This layout should be included by a script that defines the FLASH and RAM\n * regions for the board as well as TBF_HEADER_SIZE. Here is a an example\n * process binary linker script to get started:\n *     MEMORY {\n *         FLASH (X) : ORIGIN = 0x10000, LENGTH = 0x10000\n *         RAM   (W) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     TBF_HEADER_SIZE = 0x48;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\n * FLASH refers to the area the process binary occupies in flash, including TBF\n * headers. RAM refers to the area the process will have access to in memory.\n * STACK_SIZE is the size of the process' stack (this layout file may round the\n * stack size up for alignment purposes). TBF_HEADER_SIZE must correspond to the\n * --protected-region-size flag passed to elf2tab.\n *\n * This places the flash sections in the following order:\n *     1. .rt_header -- Constants used by runtime initialization.\n *     2. .text      -- Executable code.\n *     3. .rodata    -- Read-only global data (e.g. most string constants).\n *     4. .data      -- Read-write data, copied to RAM at runtime.\n *\n * This places the RAM sections in the following order:\n *     1. .stack -- The stack grows downward. Putting it first gives us\n *                  MPU-based overflow detection.\n *     2. .data  -- Read-write data, initialized by copying from flash.\n *     3. .bss   -- Zero-initialized read-write global data.\n *     4. Heap   -- The heap (optional) comes after .bss and grows upwards to\n *                  the process break.\n *\/\n\n\/* TODO: Should TBF_HEADER_SIZE be configured via a similar mechanism to the\n * stack size? We should see if that is possible.\n *\/\n\n\/* GNU LD looks for `start` as an entry point by default, while LLVM's LLD looks\n * for `_start`. To be compatible with both, we manually specify an entry point.\n *\/\nENTRY(start)\n\nSECTIONS {\n    \/* Sections located in FLASH at runtime.\n     *\/\n\n    \/* Add a section where elf2tab will place the TBF headers, so that the rest\n     * of the FLASH sections are in the right locations. *\/\n    .tbf_header (NOLOAD) : {\n        . = . + TBF_HEADER_SIZE;\n    } > FLASH\n\n    \/* Runtime header. Contains values the linker knows that the runtime needs\n     * to look up.\n     *\/\n    .start ALIGN(4) : {\n        rt_header = .;\n        LONG(start);\n        LONG(ADDR(.bss) + SIZEOF(.bss)); \/* Initial process break *\/\n        LONG(_stack_top);\n        LONG(SIZEOF(.data));\n        LONG(LOADADDR(.data));\n        LONG(ADDR(.data));\n        LONG(SIZEOF(.bss));\n        LONG(ADDR(.bss));\n\n        *(.start)\n    } > FLASH\n\n    \/* Text section -- the application's code. *\/\n    .text ALIGN(4) : {\n        *(.text.*)\n    } > FLASH\n\n    \/* Read-only data section. Contains strings and other global constants. *\/\n    .rodata ALIGN(4) : {\n        *(.rodata.*)\n        \/* .data is placed after .rodata in flash. data_flash_start is used by\n         * AT() to place .data in flash as well as in rt_header.\n         *\/\n        _data_flash_start = .;\n    } > FLASH\n\n    \/* Sections located in RAM at runtime.\n     *\/\n\n    \/* Reserve space for the stack. Aligned to a multiple of 16 bytes for the\n     * RISC-V calling convention:\n     * https:\/\/riscv.org\/wp-content\/uploads\/2015\/01\/riscv-calling.pdf\n     *\/\n    .stack (NOLOAD) : {\n\t\/* _sram_origin is used by elf2tab:\n\t * https:\/\/github.com\/tock\/elf2tab\/blob\/master\/src\/main.rs#L301\n\t *\/\n        _sram_origin = .;\n        KEEP(*(.stack_buffer))\n        . = ALIGN(16);\n        _stack_top = .;  \/* Used in rt_header *\/\n    } > RAM\n\n    \/* Read-write data section. This is deployed as part of FLASH but is copied\n     * into RAM at runtime.\n     *\/\n    .data ALIGN(4) : AT(_data_flash_start) {\n        data_ram_start = .;\n        \/* .sdata is the RISC-V small data section *\/\n        *(.sdata .data)\n        \/* Pad to word alignment so the relocation loop can use word-sized\n         * copies.\n         *\/\n        . = ALIGN(4);\n    } > RAM\n\n    \/* BSS section. These are zero-initialized static variables. This section is\n     * not copied from FLASH into RAM but rather directly initialized, and is\n     * mainly put in this linker script so that we get an error if it overflows\n     * the RAM region.\n     *\/\n    .bss ALIGN(4) (NOLOAD) : {\n        \/* .sbss is the RISC-V small data section *\/\n        *(.sbss .bss.*)\n    } > RAM\n\n    _heap_start = ADDR(.bss) + SIZEOF(.bss);  \/* Used by rt_header *\/\n\n    \/* Sections we do not need. *\/\n    \/DISCARD\/ :\n    {\n      *(.ARM.exidx .eh_frame)\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"82e89add619603d8f73e00c0ad8ab2bc5e6f393f","subject":"STM32H7 : use RAM instead of DTCMRAM (GCC_ARM toolchain)","message":"STM32H7 : use RAM instead of DTCMRAM (GCC_ARM toolchain)\n","repos":"andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed","old_file":"targets\/TARGET_STM\/TARGET_STM32H7\/TARGET_STM32H743xI\/device\/TOOLCHAIN_GCC_ARM\/STM32H743xI.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32H7\/TARGET_STM32H743xI\/device\/TOOLCHAIN_GCC_ARM\/STM32H743xI.ld","new_contents":"\/* Linker script to configure memory regions. *\/\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 2048K\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\nM_CRASH_DATA_RAM_SIZE = 0x100;\n\nMEMORY\n{ \n  FLASH (rx)     : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  DTCMRAM (rwx)  : ORIGIN = 0x20000298, LENGTH = 128K-0x298\n  RAM (xrw)      : ORIGIN = 0x24000000, LENGTH = 512K\n  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K\n  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K\n  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .crash_data_ram :\n    {\n        . = ALIGN(8);\n        __CRASH_DATA_RAM__ = .;\n        __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n        KEEP(*(.keep.crash_data_ram))\n        *(.m_crash_data_ram)     \/* This is a user defined section *\/\n        . += M_CRASH_DATA_RAM_SIZE;\n        . = ALIGN(8);\n        __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > DTCMRAM\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n    .lwip_sec (NOLOAD) : {\n        . = ABSOLUTE(0x30040000);\n        *(.RxDecripSection) \n        \n        . = ABSOLUTE(0x30040100);\n        *(.TxDecripSection)\n        \n        . = ABSOLUTE(0x30040400);\n        *(.RxArraySection) \n\n        . = ABSOLUTE(0x30044000);\n        *(.ethusbram) \n\n    } >RAM_D2 AT> FLASH\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 2048K\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\nM_CRASH_DATA_RAM_SIZE = 0x100;\n\nMEMORY\n{ \n  FLASH (rx)     : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  DTCMRAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 128K\n  RAM (xrw)      : ORIGIN = 0x24000298, LENGTH = 512K - 0x298  \/* end = 0x24080000 *\/\n  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K\n  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K\n  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .crash_data_ram :\n    {\n        . = ALIGN(8);\n        __CRASH_DATA_RAM__ = .;\n        __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n        KEEP(*(.keep.crash_data_ram))\n        *(.m_crash_data_ram)     \/* This is a user defined section *\/\n        . += M_CRASH_DATA_RAM_SIZE;\n        . = ALIGN(8);\n        __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > RAM\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n    .lwip_sec (NOLOAD) : {\n        . = ABSOLUTE(0x30040000);\n        *(.RxDecripSection) \n        \n        . = ABSOLUTE(0x30040100);\n        *(.TxDecripSection)\n        \n        . = ABSOLUTE(0x30040400);\n        *(.RxArraySection) \n\n        . = ABSOLUTE(0x30044000);\n        *(.ethusbram) \n\n    } >RAM_D2 AT> FLASH\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"307c8ebdef77546a9c1083d65699b94b83727624","subject":"Fix \/ clean up linker script for iCEbreaker (solves TFLM unit test inconsistency).","message":"Fix \/ clean up linker script for iCEbreaker (solves TFLM unit test inconsistency).\n","repos":"google\/CFU-Playground,google\/CFU-Playground,google\/CFU-Playground,google\/CFU-Playground","old_file":"common\/_common_soc\/1bitsquared_icebreaker\/ld\/linker.ld","new_file":"common\/_common_soc\/1bitsquared_icebreaker\/ld\/linker.ld","new_contents":"INCLUDE output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE regions.ld\n\n\nSECTIONS\n{\n    \/* .data first to take precedence for explicit code we want in SRAM. *\/\n    .data : AT (_erodata) \/* Loaded in spiflash but runtime copied to SRAM. *\/\n    {\n        . = ALIGN(4);\n        _fdata = .;  \/* Start of .data in SRAM, copied to in crt0. *\/\n\n        *(.ramtext .ramtext*)\n\n        \/* \n         * We need to ensure .data starts at > 0, otherwise a pointer to the\n         * first element of .data will be mistaken for a nullptr.\n         *\/\n        . = MAX(., 0x4); \n\n        *(.data .data*)\n        *(.sdata .sdata*)\n\n        . = ALIGN(4);\n        _edata = .;  \/* End of .data in SRAM, end of copying in crt0. *\/\n    } > sram\n\n    \/* Start .text at 4 byte boundary after gateware. *\/\n    _ftext = (ORIGIN(spiflash) + 0x30000 + 3) & ~3;\n    .text _ftext :\n    {\n        *(.text.start)\n        *(.text .text*)\n    } > spiflash\n\n    .rodata :\n    {\n        *(.rodata .rodata*)\n        *(.srodata .srodata*)\n\n        . = ALIGN(4);\n        _erodata = .;  \/* Start of .data in spiflash, copied from in crt0. *\/\n    } > spiflash\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _fbss = .;  \/* Start of zeroing in crt0. *\/\n\n        *(.bss .bss*)\n        *(.sbss .sbss*)\n\n        *(COMMON)\n        \n        . = ALIGN(4);\n        _ebss = .;  \/* End of zeroing in crt0. *\/\n    } > sram\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","old_contents":"INCLUDE output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE regions.ld\n\n\nSECTIONS\n{\n\t.reserved :\n\t{\n\t\t\/* Space reserved for gateware, shouldn't step on it. *\/\n\t\t. += 0x30000;\n\t} > spiflash\n\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(.text.start)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t_etext = .;\n\t} > spiflash\n\n\t.rodata :\n\t{\n\t\t. = ALIGN(8);\n\t\t_frodata = .;\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.rodata1)\n\t\t*(.srodata .srodata.*)\n\t\t. = ALIGN(8);\n\t\t_erodata = .;\n\t} > spiflash\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(8);\n\t\t_fdata = .;\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t\t*(.ramtext .ramtext.*)\n\t\t_gp = ALIGN(16);\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.* .sdata2 .sdata2.*)\n\t\t_edata = ALIGN(16); \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss : AT (ADDR(.data) + SIZEOF (.data))\n\t{\n\t\t. = ALIGN(16);\n\t\t_fbss = .;\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1e0d868b0c5826faf5a37cf5eac7b750efc9c352","subject":"Linkscript: place .dynamic section into its own PT_DYNAMIC segment","message":"Linkscript: place .dynamic section into its own PT_DYNAMIC segment\n","repos":"switchbrew\/libnx","old_file":"buildscripts\/lib\/switch.ld","new_file":"buildscripts\/lib\/switch.ld","new_contents":"OUTPUT_ARCH(aarch64)\nENTRY(_start)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(5) \/* Read | Execute *\/;\n\trodata PT_LOAD FLAGS(4) \/* Read *\/;\n\tdata   PT_LOAD FLAGS(6) \/* Read | Write *\/;\n\tdyn    PT_DYNAMIC;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\tPROVIDE(__start__ = 0x0);\n\t. = __start__;\n\n\t.crt0 :\n\t{\n\t\tKEEP (*(.crt0))\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.init :\n\t{\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.plt :\n\t{\n\t\t*(.plt)\n\t\t*(.iplt)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.text :\n\t{\n\t\t*(.text.unlikely .text.*_unlikely .text.unlikely.*)\n\t\t*(.text.exit .text.exit.*)\n\t\t*(.text.startup .text.startup.*)\n\t\t*(.text.hot .text.hot.*)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.fini :\n\t{\n\t\tKEEP( *(.fini) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t\/* =========== RODATA section =========== *\/\n\t. = ALIGN(0x1000);\n\n\t.rodata :\n\t{\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(8);\n\t} :rodata\n\n\t.eh_frame_hdr     : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } :rodata\n\t.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata\n\t.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata\n\t.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata\n\n\t.dynamic           : { *(.dynamic) } :rodata :dyn\n\t.interp            : { *(.interp) } :rodata\n\t.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata\n\t.hash              : { *(.hash) } :rodata\n\t.gnu.hash          : { *(.gnu.hash) } :rodata\n\t.gnu.version       : { *(.gnu.version) } :rodata\n\t.gnu.version_d     : { *(.gnu.version_d) } :rodata\n\t.gnu.version_r     : { *(.gnu.version_r) } :rodata\n\t.dynsym            : { *(.dynsym) } :rodata\n\t.dynstr            : { *(.dynstr) } :rodata\n\t.rela.dyn          : { *(.rela.*) } :rodata\n\n\t\/* =========== DATA section =========== *\/\n\t. = ALIGN(0x1000);\n\n\t.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data\n\t.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data\n\t.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data\n\t.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data\n\n\t.tdata ALIGN(8) :\n\t{\n\t\t__tdata_lma = .;\n\t\t*(.tdata .tdata.* .gnu.linkonce.td.*)\n\t\t. = ALIGN(8);\n\t\t__tdata_lma_end = .;\n\t} :data\n\n\t.tbss ALIGN(8) :\n\t{\n\t\t*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)\n\t\t. = ALIGN(8);\n\t} :data\n\n\t.preinit_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\t} :data\n\n\t.init_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\t} :data\n\n\t.fini_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__fini_array_start = .);\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tPROVIDE (__fini_array_end = .);\n\t} :data\n\n\t.ctors ALIGN(8) :\n\t{\n\t\tKEEP (*crtbegin.o(.ctors)) \/* MUST be first -- GCC requires it *\/\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t} :data\n\n\t.dtors ALIGN(8) :\n\t{\n\t\tKEEP (*crtbegin.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t} :data\n\n\t__got_start__ = .;\n\n\t.got            : { *(.got) *(.igot) } :data\n\t.got.plt        : { *(.got.plt)  *(.igot.plt) } :data\n\n\t__got_end__ = .;\n\n\t.data ALIGN(8) :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tSORT(CONSTRUCTORS)\n\t} :data\n\n\t__bss_start__ = .;\n\t.bss ALIGN(8) :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\n\t\t\/* Reserve space for the TLS segment of the main thread *\/\n\t\t__tls_start = .;\n\t\t. += + SIZEOF(.tdata) + SIZEOF(.tbss);\n\t\t__tls_end = .;\n\t} : data\n\t__bss_end__ = .;\n\n\t__end__ = ABSOLUTE(.) ;\n\n\t\/* ==================\n\t   ==== Metadata ====\n\t   ================== *\/\n\n\t\/* Discard sections that difficult post-processing *\/\n\t\/DISCARD\/ : { *(.group .comment .note) }\n\n\t\/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n}\n","old_contents":"OUTPUT_ARCH(aarch64)\nENTRY(_start)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(5) \/* Read | Execute *\/;\n\trodata PT_LOAD FLAGS(4) \/* Read *\/;\n\tdata   PT_LOAD FLAGS(6) \/* Read | Write *\/;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\tPROVIDE(__start__ = 0x0);\n\t. = __start__;\n\n\t.crt0 :\n\t{\n\t\tKEEP (*(.crt0))\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.init :\n\t{\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.plt :\n\t{\n\t\t*(.plt)\n\t\t*(.iplt)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.text :\n\t{\n\t\t*(.text.unlikely .text.*_unlikely .text.unlikely.*)\n\t\t*(.text.exit .text.exit.*)\n\t\t*(.text.startup .text.startup.*)\n\t\t*(.text.hot .text.hot.*)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.fini :\n\t{\n\t\tKEEP( *(.fini) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t\/* =========== RODATA section =========== *\/\n\t. = ALIGN(0x1000);\n\n\t.rodata :\n\t{\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(8);\n\t} :rodata\n\n\t.eh_frame_hdr     : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } :rodata\n\t.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata\n\t.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata\n\t.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata\n\n\t.interp            : { *(.interp) } :rodata\n\t.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata\n\t.hash              : { *(.hash) } :rodata\n\t.gnu.hash          : { *(.gnu.hash) } :rodata\n\t.gnu.version       : { *(.gnu.version) } :rodata\n\t.gnu.version_d     : { *(.gnu.version_d) } :rodata\n\t.gnu.version_r     : { *(.gnu.version_r) } :rodata\n\t.dynsym            : { *(.dynsym) } :rodata\n\t.dynstr            : { *(.dynstr) } :rodata\n\t.rela.dyn          : { *(.rela.*) } :rodata\n\n\t\/* =========== DATA section =========== *\/\n\t. = ALIGN(0x1000);\n\n\t.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data\n\t.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data\n\t.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data\n\t.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data\n\n\t.tdata ALIGN(8) :\n\t{\n\t\t__tdata_lma = .;\n\t\t*(.tdata .tdata.* .gnu.linkonce.td.*)\n\t\t. = ALIGN(8);\n\t\t__tdata_lma_end = .;\n\t} :data\n\n\t.tbss ALIGN(8) :\n\t{\n\t\t*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)\n\t\t. = ALIGN(8);\n\t} :data\n\n\t.preinit_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\t} :data\n\n\t.init_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\t} :data\n\n\t.fini_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__fini_array_start = .);\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tPROVIDE (__fini_array_end = .);\n\t} :data\n\n\t.ctors ALIGN(8) :\n\t{\n\t\tKEEP (*crtbegin.o(.ctors)) \/* MUST be first -- GCC requires it *\/\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t} :data\n\n\t.dtors ALIGN(8) :\n\t{\n\t\tKEEP (*crtbegin.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t} :data\n\n\t__got_start__ = .;\n\n\t.got            : { *(.got) *(.igot) } :data\n\t.got.plt        : { *(.got.plt)  *(.igot.plt) } :data\n\n\t__got_end__ = .;\n\n\t.data ALIGN(8) :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tSORT(CONSTRUCTORS)\n\t} :data\n\n\t.dynamic ALIGN(8) :\n\t{\n\t\t*(.dynamic)\n\t} :data\n\n\t__bss_start__ = .;\n\t.bss ALIGN(8) :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\n\t\t\/* Reserve space for the TLS segment of the main thread *\/\n\t\t__tls_start = .;\n\t\t. += + SIZEOF(.tdata) + SIZEOF(.tbss);\n\t\t__tls_end = .;\n\t} : data\n\t__bss_end__ = .;\n\n\t__end__ = ABSOLUTE(.) ;\n\n\t\/* ==================\n\t   ==== Metadata ====\n\t   ================== *\/\n\n\t\/* Discard sections that difficult post-processing *\/\n\t\/DISCARD\/ : { *(.group .comment .note) }\n\n\t\/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"a59eb2d60753e2acaa2404064e16d689dd69a954","subject":"update c3 bootloader ld addr info","message":"update c3 bootloader ld addr info\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/ld\/esp32c3\/bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/ld\/esp32c3\/bootloader.ld","new_contents":"\/** Simplified memory map for the bootloader.\n *  Make sure the bootloader can load into main memory without overwriting itself.\n *  We put 2nd bootloader in the high address space (before ROM stack\/data\/bss).\n *  See memory usage for ROM bootloader at the end of this file.\n *\/\n\nMEMORY\n{\n  iram_seg (RWX) :                  org = 0x403CE000, len = 0x2000\n  iram_loader_seg (RWX) :           org = 0x403D0000, len = 0x6000\n  dram_seg (RW) :                   org = 0x3FCD6000, len = 0x4000\n}\n\n\/* Default entry point: *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)\n    *libbootloader_support.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _dram_start = ABSOLUTE(.);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/* C++ constructor and destructor tables, properly ordered: *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _dram_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/** CPU will try to prefetch up to 16 bytes of\n      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow\n      * safe access to up to 16 bytes after the last real instruction, add\n      * dummy bytes to ensure this\n      *\/\n    . += 16;\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n\n\n\/**\n *  Appendix: Memory Usage of ROM bootloader\n *\n *  +--------+--------------+------+ 0x3FCC_AE00\n *  |        ^              |\n *  |        |              |\n *  |        | data\/bss     |\n *  |        |              |\n *  |        v              |\n *  +------------------------------+ 0x3FCD_C710\n *  |        ^              |\n *  |        |              |\n *  |        | stack        |\n *  |        |              |\n *  |        v              |\n *  +------------------------------+ 0x3FCD_E710\n *\/\n","old_contents":"\/** Simplified memory map for the bootloader.\n *  Make sure the bootloader can load into main memory without overwriting itself.\n *  We put 2nd bootloader in the high address space (before ROM stack\/data\/bss).\n *  See memory usage for ROM bootloader at the end of this file.\n *\/\n\nMEMORY\n{\n  iram_seg (RWX) :                  org = 0x403CE000, len = 0x2000\n  iram_loader_seg (RWX) :           org = 0x403D0000, len = 0x6000\n  dram_seg (RW) :                   org = 0x3FCD6000, len = 0x4000\n}\n\n\/* Default entry point: *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)\n    *libbootloader_support.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _dram_start = ABSOLUTE(.);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/* C++ constructor and destructor tables, properly ordered: *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _dram_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/** CPU will try to prefetch up to 16 bytes of\n      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow\n      * safe access to up to 16 bytes after the last real instruction, add\n      * dummy bytes to ensure this\n      *\/\n    . += 16;\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n\n\n\/**\n *  Appendix: Memory Usage of ROM bootloader\n *\n *  +--------+--------------+------+ 0x3FCC_B000\n *  |        ^              |\n *  |        |              |\n *  |        | data\/bss     |\n *  |        |              |\n *  |        v              |\n *  +------------------------------+ 0x3FCD_C910\n *  |        ^              |\n *  |        |              |\n *  |        | stack        |\n *  |        |              |\n *  |        v              |\n *  +------------------------------+ 0x3FCD_E910\n *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"811a373f62aadbafca5e72f24462ab835290474c","subject":"update ld add *(.sdk.version)","message":"update ld add *(.sdk.version)\n","repos":"drpjk\/Arduino,leftbrainstrain\/Arduino-ESP8266,leftbrainstrain\/Arduino-ESP8266,Cloudino\/Cloudino-Arduino-IDE,mateuszdw\/Arduino,sanyaade-iot\/Arduino-1,Protoneer\/Arduino,Protoneer\/Arduino,NeuralSpaz\/Arduino,danielchalef\/Arduino,ogahara\/Arduino,radut\/Arduino,Cloudino\/Cloudino-Arduino-IDE,spapadim\/Arduino,paulo-raca\/ESP8266-Arduino,nkolban\/Arduino,wdoganowski\/Arduino,spapadim\/Arduino,drpjk\/Arduino,myrtleTree33\/Arduino,Cloudino\/Cloudino-Arduino-IDE,sanyaade-iot\/Arduino-1,mattvenn\/Arduino,mateuszdw\/Arduino,aichi\/Arduino-2,eeijcea\/Arduino-1,jomolinare\/Arduino,NeuralSpaz\/Arduino,paulmand3l\/Arduino,paulo-raca\/ESP8266-Arduino,Cloudino\/Arduino,myrtleTree33\/Arduino,radut\/Arduino,shiitakeo\/Arduino,wdoganowski\/Arduino,aichi\/Arduino-2,ogahara\/Arduino,zenmanenergy\/Arduino,shiitakeo\/Arduino,NeuralSpaz\/Arduino,nkolban\/Arduino,Cloudino\/Arduino,Alfredynho\/AgroSis,paulo-raca\/ESP8266-Arduino,NeuralSpaz\/Arduino,sanyaade-iot\/Arduino-1,zenmanenergy\/Arduino,jomolinare\/Arduino,mateuszdw\/Arduino,noahchense\/Arduino-1,tannewt\/Arduino,Protoneer\/Arduino,nkolban\/Arduino,paulo-raca\/ESP8266-Arduino,koltegirish\/Arduino,spapadim\/Arduino,EmuxEvans\/Arduino,shiitakeo\/Arduino,ogahara\/Arduino,mattvenn\/Arduino,weera00\/Arduino,tannewt\/Arduino,adafruit\/ESP8266-Arduino,Alfredynho\/AgroSis,ssvs111\/Arduino,jomolinare\/Arduino,koltegirish\/Arduino,smily77\/Arduino,sanyaade-iot\/Arduino-1,Protoneer\/Arduino,mangelajo\/Arduino,EmuxEvans\/Arduino,noahchense\/Arduino-1,danielchalef\/Arduino,spapadim\/Arduino,weera00\/Arduino,drpjk\/Arduino,fungxu\/Arduino,EmuxEvans\/Arduino,leftbrainstrain\/Arduino-ESP8266,eeijcea\/Arduino-1,weera00\/Arduino,adafruit\/ESP8266-Arduino,Cloudino\/Arduino,Cloudino\/Arduino,wdoganowski\/Arduino,wdoganowski\/Arduino,radut\/Arduino,koltegirish\/Arduino,danielchalef\/Arduino,raimohanska\/Arduino,raimohanska\/Arduino,shiitakeo\/Arduino,Alfredynho\/AgroSis,mattvenn\/Arduino,myrtleTree33\/Arduino,Alfredynho\/AgroSis,nkolban\/Arduino,eeijcea\/Arduino-1,noahchense\/Arduino-1,Cloudino\/Arduino,danielchalef\/Arduino,Cloudino\/Cloudino-Arduino-IDE,radut\/Arduino,aichi\/Arduino-2,noahchense\/Arduino-1,NeuralSpaz\/Arduino,koltegirish\/Arduino,ssvs111\/Arduino,ssvs111\/Arduino,paulmand3l\/Arduino,tannewt\/Arduino,sanyaade-iot\/Arduino-1,jomolinare\/Arduino,raimohanska\/Arduino,ssvs111\/Arduino,spapadim\/Arduino,Cloudino\/Cloudino-Arduino-IDE,raimohanska\/Arduino,mangelajo\/Arduino,koltegirish\/Arduino,Alfredynho\/AgroSis,aichi\/Arduino-2,jomolinare\/Arduino,zenmanenergy\/Arduino,adafruit\/ESP8266-Arduino,EmuxEvans\/Arduino,ogahara\/Arduino,Alfredynho\/AgroSis,aichi\/Arduino-2,fungxu\/Arduino,weera00\/Arduino,paulo-raca\/ESP8266-Arduino,jomolinare\/Arduino,danielchalef\/Arduino,leftbrainstrain\/Arduino-ESP8266,weera00\/Arduino,paulo-raca\/ESP8266-Arduino,noahchense\/Arduino-1,paulo-raca\/ESP8266-Arduino,zenmanenergy\/Arduino,tannewt\/Arduino,wdoganowski\/Arduino,ssvs111\/Arduino,paulmand3l\/Arduino,paulmand3l\/Arduino,raimohanska\/Arduino,adafruit\/ESP8266-Arduino,shiitakeo\/Arduino,EmuxEvans\/Arduino,raimohanska\/Arduino,mateuszdw\/Arduino,gonium\/Arduino,gonium\/Arduino,mattvenn\/Arduino,gonium\/Arduino,Cloudino\/Arduino,mangelajo\/Arduino,mateuszdw\/Arduino,aichi\/Arduino-2,NeuralSpaz\/Arduino,radut\/Arduino,shiitakeo\/Arduino,Cloudino\/Arduino,paulmand3l\/Arduino,mattvenn\/Arduino,tannewt\/Arduino,zenmanenergy\/Arduino,EmuxEvans\/Arduino,gonium\/Arduino,leftbrainstrain\/Arduino-ESP8266,paulmand3l\/Arduino,mateuszdw\/Arduino,Protoneer\/Arduino,nkolban\/Arduino,spapadim\/Arduino,ssvs111\/Arduino,leftbrainstrain\/Arduino-ESP8266,mangelajo\/Arduino,weera00\/Arduino,spapadim\/Arduino,drpjk\/Arduino,danielchalef\/Arduino,nkolban\/Arduino,Cloudino\/Cloudino-Arduino-IDE,wdoganowski\/Arduino,smily77\/Arduino,EmuxEvans\/Arduino,drpjk\/Arduino,NeuralSpaz\/Arduino,noahchense\/Arduino-1,myrtleTree33\/Arduino,paulmand3l\/Arduino,mattvenn\/Arduino,radut\/Arduino,fungxu\/Arduino,Protoneer\/Arduino,Cloudino\/Cloudino-Arduino-IDE,eeijcea\/Arduino-1,myrtleTree33\/Arduino,Protoneer\/Arduino,ogahara\/Arduino,eeijcea\/Arduino-1,fungxu\/Arduino,ogahara\/Arduino,wdoganowski\/Arduino,adafruit\/ESP8266-Arduino,myrtleTree33\/Arduino,mateuszdw\/Arduino,mattvenn\/Arduino,smily77\/Arduino,mangelajo\/Arduino,drpjk\/Arduino,shiitakeo\/Arduino,fungxu\/Arduino,koltegirish\/Arduino,aichi\/Arduino-2,eeijcea\/Arduino-1,smily77\/Arduino,gonium\/Arduino,tannewt\/Arduino,smily77\/Arduino,mangelajo\/Arduino,smily77\/Arduino,nkolban\/Arduino,raimohanska\/Arduino,sanyaade-iot\/Arduino-1,ssvs111\/Arduino,mangelajo\/Arduino,leftbrainstrain\/Arduino-ESP8266,smily77\/Arduino,jomolinare\/Arduino,myrtleTree33\/Arduino,Alfredynho\/AgroSis,adafruit\/ESP8266-Arduino,gonium\/Arduino,gonium\/Arduino,koltegirish\/Arduino,drpjk\/Arduino,eeijcea\/Arduino-1,danielchalef\/Arduino,ogahara\/Arduino,fungxu\/Arduino,adafruit\/ESP8266-Arduino,sanyaade-iot\/Arduino-1,fungxu\/Arduino,radut\/Arduino,weera00\/Arduino,tannewt\/Arduino,zenmanenergy\/Arduino,zenmanenergy\/Arduino,noahchense\/Arduino-1","old_file":"hardware\/esp8266com\/esp8266\/tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"hardware\/esp8266com\/esp8266\/tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *spiffs*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *spiffs*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"1cb754c62895bade3defd3278a8fea9cea9d5438","subject":"boards: qemu_x86_tiny: pin logging subsys code and data","message":"boards: qemu_x86_tiny: pin logging subsys code and data\n\nThis pins the logging subsys code and data so logging can be\nused with demand paging.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"boards\/x86\/qemu_x86\/qemu_x86_tiny.ld","new_file":"boards\/x86\/qemu_x86\/qemu_x86_tiny.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n * Copyright (c) 2021 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <autoconf.h>\n#include <devicetree.h>\n#include <offsets.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n#include <sys\/util.h>\n#include <sys\/mem_manage.h>\n\n\n\/* Bounds of physical RAM from DTS *\/\n#define PHYS_RAM_ADDR\t\t\tDT_REG_ADDR(DT_CHOSEN(zephyr_sram))\n#define PHYS_RAM_SIZE\t\t\tDT_REG_SIZE(DT_CHOSEN(zephyr_sram))\n\n\/* Bounds of flash from DTS *\/\n#define FLASH_ROM_ADDR\t\t\tDT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define FLASH_ROM_SIZE\t\t\tDT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n\n\/* Virtual base address for the kernel; with CONFIG_MMU this is not necessarily\n * the same as its physical location, although an identity mapping for RAM\n * is still supported by setting CONFIG_KERNEL_VM_BASE=CONFIG_SRAM_BASE_ADDRESS.\n *\/\n#ifdef Z_VM_KERNEL\n\n#define KERNEL_BASE_ADDR \\\n\t(CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET)\n\n#define KERNEL_RAM_SIZE \\\n\t(CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET)\n\n#define PHYS_RAM_AVAIL \\\n\t(PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n\n#else\n\n#define KERNEL_BASE_ADDR\t\t(PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n#define KERNEL_RAM_SIZE\t\t\t(PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n\n#endif\n\n\/* \"kernel RAM\" for linker VMA allocations starts at the offset *\/\n\n\/* Physical RAM location where the kernel image is loaded *\/\n#define PHYS_LOAD_ADDR\t\t\t(PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n\n#ifdef CONFIG_USERSPACE\n#define SMEM_PARTITION_ALIGN(size)\tMMU_PAGE_ALIGN_PERM\n#define APP_SHARED_ALIGN\t\tMMU_PAGE_ALIGN_PERM\n#endif\n\nMEMORY\n    {\n#if defined(Z_VM_KERNEL)\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_AVAIL\n#endif\n    RAM (wx)        : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n    FLASH (rw)      : ORIGIN = FLASH_ROM_ADDR, LENGTH = FLASH_ROM_SIZE\n#endif\n\n    \/*\n     * On 32-bit x86, fake memory area for build-time IDT generation data.\n     *\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 0xFFFF1000, LENGTH = 2K\n    }\n\n#if defined(Z_VM_KERNEL)\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_MMU\n\t#define MMU_PAGE_ALIGN\t\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n\n#undef SECTION_PROLOGUE\n#define SECTION_PROLOGUE(name, options, align) \\\n        name options : ALIGN_WITH_INPUT align\n\n#undef SECTION_DATA_PROLOGUE\n#define SECTION_DATA_PROLOGUE(name, options, align) \\\n        name options : ALIGN_WITH_INPUT align\n\n#undef GROUP_ROM_LINK_IN\n#define GROUP_ROM_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#undef GROUP_DATA_LINK_IN\n#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#undef GROUP_NOLOAD_LINK_IN\n#define GROUP_NOLOAD_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#endif\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN_PERM\tMMU_PAGE_ALIGN\n#else\n\t#define MMU_PAGE_ALIGN_PERM\n#endif\n\n\/* For all source files under arch\/x86\/. *\/\n#define LIB_ARCH_X86_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libarch__x86__core.a.a:(.##lsect)\t\t\t\t\\\n\t*libarch__x86__core.a:(.##lsect##.*)\n\n#ifdef CONFIG_MINIMAL_LIBC\n\/* For all source files under lib\/libc\/minimal\/.\n * These files includes, for example, math and string functions.\n *\/\n#define LIB_C_IN_SECT(lsect)\t\t\t\t\t\t\\\n\t*liblib__libc__minimal.a:(.##lsect)\t\t\t\t\\\n\t*liblib__libc__minimal.a:(.##lsect##.*)\n\n#endif \/* CONFIG_MINIMAL_LIBC *\/\n\n#ifdef CONFIG_NEWLIB_LIBC\n\/* For Newlib libc-hook.c. *\/\n#define LIB_C_IN_SECT(lsect)\t\t\t\t\t\t\\\n\t*liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect)\t\t\\\n\t*liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect##.*)\n\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n\/*\n * For drivers that are usually used (e.g. serial)\n *\/\n#define LIB_DRIVERS_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libdrivers__serial.a:(.##lsect)\t\t\t\t\\\n\t*libdrivers__serial.a:(.##lsect##.*)\t\t\t\t\\\n\t*hpet.c.obj(.##lsect)\t\t\t\t\t\t\\\n\t*hpet.c.obj(.##lsect##.*)\t\t\t\t\t\\\n\t*intc_ioapic.c.obj(.##lsect)\t\t\t\t\t\\\n\t*intc_ioapic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*intc_loapic.c.obj(.##lsect)\t\t\t\t\t\\\n\t*intc_loapic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*intc_system_apic.c.obj(.##lsect)\t\t\t\t\\\n\t*intc_system_apic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*rand32_timer.c.obj(.##lsect)\t\t\t\t\t\\\n\t*rand32_timer.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*uart_console.c.obj(.##lsect)\t\t\t\t\t\\\n\t*uart_console.c.obj(.##lsect##.*)\n\n\/* For all source files under kernel\/. and kernel related files *\/\n#define LIB_KERNEL_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libkernel.a:(.##lsect)\t\t\t\t\t\t\\\n\t*libkernel.a:(.##lsect##.*)\t\t\t\t\t\\\n\t*libsubsys__demand_paging__*.a:(.##lsect)\t\t\t\\\n\t*libsubsys__demand_paging__*.a:(.##lsect##.*)\n\n\/* For particular file packaged in libzephyr.a. *\/\n#define LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, objfile)\t\t\t\\\n\t*libzephyr.a:objfile.c.obj(.##lsect)\t\t\t\t\\\n\t*libzephyr.a:objfile.c.obj(.##lsect##.*)\n\n\/* For source files under lib\/os\/ with commonly used functions. *\/\n#define LIB_ZEPHYR_IN_SECT(lsect)\t\t\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, assert)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, bitarray)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_complete)\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_nano)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, configs)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap-validate)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, mutex)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, notify)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, printk)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sem)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, stdout_console)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sys_clock_init)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, rb)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, thread_entry)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, work_q)\n\n\/*\n * Catch all for all internal\/external kernel functions\n * as they are usually defined as \"static inline\" where\n * they are attached to the source which uses them.\n * Hence the need to specify them here so they can be pinned.\n *\/\n#define ZEPHYR_KERNEL_FUNCS_IN_SECT\t\t\t\t\t\\\n\t*(.text.atomic_*)\t\t\t\t\t\t\\\n\t*(.text.k_*)\t\t\t\t\t\t\t\\\n\t*(.text.sys_*_bit)\t\t\t\t\t\t\\\n\t*(.text.sys_bitfield_*)\t\t\t\t\t\t\\\n\t*(.text.sys_clock_hw_cycles_per_sec)\t\t\t\t\\\n\t*(.text.sys_cache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_dcache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_icache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_mutex_*)\t\t\t\t\t\t\\\n\t*(.text.sys_notify_*)\t\t\t\t\t\t\\\n\t*(.text.sys_dlist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_slist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_sflist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_sfnode_*)\t\t\t\t\t\t\\\n\t*(.text.sys_io_*)\t\t\t\t\t\t\\\n\t*(.text.sys_in*)\t\t\t\t\t\t\\\n\t*(.text.sys_out*)\t\t\t\t\t\t\\\n\t*(.text.sys_read*)\t\t\t\t\t\t\\\n\t*(.text.sys_write*)\t\t\t\t\t\t\\\n\t*(.text.sys_get_be*)\t\t\t\t\t\t\\\n\t*(.text.sys_get_le*)\t\t\t\t\t\t\\\n\t*(.text.sys_put_be*)\t\t\t\t\t\t\\\n\t*(.text.sys_put_le*)\t\t\t\t\t\t\\\n\t*(.text.sys_mem_swap)\t\t\t\t\t\t\\\n\t*(.text.sys_memcpy_swap)\t\t\t\t\t\\\n\t*(.text.z_*)\n\n\/* For logging subsys *\/\n#define LIB_SUBSYS_LOGGING_IN_SECT(lsect)\t\t\t\t\\\n\t*log_*.c.obj(.##lsect)\t\t\t\t\t\t\\\n\t*log_*.c.obj(.##lsect.*)\t\t\t\t\t\\\n\t*mpsc_pbuf.c.obj(.##lsect)\t\t\t\t\t\\\n\t*mpsc_pbuf.c.obj(.##lsect.*)\n\nepoint = Z_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY);\nENTRY(epoint)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n#ifdef CONFIG_LINKER_USE_BOOT_SECTION\n\n\tSECTION_PROLOGUE(boot.text,,)\n\t{\n#include <snippets-rom-start.ld>\n\n\t\tMMU_PAGE_ALIGN\n\t\tlnkr_boot_start = .;\n\t\tz_mapped_start = .;\n\n\t\tlnkr_boot_text_start = .;\n\n\t\tKEEP(*(.boot_text.__start))\n\t\t*(.boot_text)\n\t\t*(.boot_text.*)\n\n\t\t*(.text.k_mem_paging_backing_store_init)\n\t\t*(.text.k_mem_paging_eviction_init)\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_text_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.rodata,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_rodata_start = .;\n\n\t\t*(.boot_rodata)\n\t\t*(.boot_rodata.*)\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_rodata_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.data,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_data_start = .;\n\n\t\t*(.boot_data)\n\t\t*(.boot_data.*)\n\n\t\tlnkr_boot_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.bss, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_bss_start = .;\n\n\t\t*(.boot_bss)\n\t\t*(.boot_bss.*)\n\n\t\tlnkr_boot_bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.noinit, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_noinit_start = .;\n\n\t\t*(.boot_noinit)\n\t\t*(.boot_noinit.*)\n\n\t\tlnkr_boot_noinit_end = .;\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_boot_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tlnkr_boot_text_size = lnkr_boot_text_end - lnkr_boot_text_start;\n\tlnkr_boot_rodata_size = lnkr_boot_rodata_end - lnkr_boot_rodata_start;\n\tlnkr_boot_data_size = lnkr_boot_data_end - lnkr_boot_data_start;\n\tlnkr_boot_bss_size = lnkr_boot_bss_end - lnkr_boot_bss_start;\n\tlnkr_boot_noinit_size = lnkr_boot_noinit_end - lnkr_boot_noinit_start;\n\n#endif \/* CONFIG_LINKER_USE_BOOT_SECTION *\/\n\n#ifdef CONFIG_LINKER_USE_PINNED_SECTION\n\n\tSECTION_PROLOGUE(pinned.text,,)\n\t{\n#ifndef CONFIG_LINKER_USE_BOOT_SECTION\n#include <snippets-rom-start.ld>\n#endif\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_pinned_start = .;\n\n#ifndef CONFIG_LINKER_USE_BOOT_SECTION\n\t\tz_mapped_start = .;\n#endif\n\n\t\tlnkr_pinned_text_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(text)\n\t\tLIB_ARCH_X86_IN_SECT(text)\n\t\t*(.text._OffsetAbsSyms)\n\n\t\t*(.pinned_text)\n\t\t*(.pinned_text.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(text)\n\t\tLIB_C_IN_SECT(text)\n\t\tLIB_DRIVERS_IN_SECT(text)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(text)\n\n\t\t*_divdi3.o(.text)\n\t\t*_udivdi3.o(.text)\n\t\t*_udivmoddi4.o(.text)\n\t\t*_umoddi3.o(.text)\n\t\t*_popcountsi2.o(.text)\n\n\t\t*(.gnu.linkonce.t.exc_*)\n\n\t\t*(.text.*.constprop)\n\t\t*(.text.*.constprop.*)\n\n#ifdef CONFIG_NEWLIB_LIBC\n\t\t*libc.a:(.text)\n\t\t*libc.a:(.text.*)\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n\t\tZEPHYR_KERNEL_FUNCS_IN_SECT\n\n#include <linker\/kobject-text.ld>\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_text_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tMMU_PAGE_ALIGN_PERM\n\n\tlnkr_pinned_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n\tSECTION_PROLOGUE(pinned.rodata,,)\n\t{\n#include <arch\/x86\/ia32\/scripts\/static_intr.ld>\n\n\t\tLIB_KERNEL_IN_SECT(rodata)\n\t\tLIB_ARCH_X86_IN_SECT(rodata)\n\n\t\t*(.pinned_rodata)\n\t\t*(.pinned_rodata.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(rodata)\n\t\tLIB_C_IN_SECT(rodata)\n\t\tLIB_DRIVERS_IN_SECT(rodata)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(rodata)\n\n\t\t\/* Static strings *\/\n\t\t*(.rodata.str*.*)\n\t\t*(.rodata.*.str*.*)\n\n#ifdef CONFIG_NEWLIB_LIBC\n\t\t*libc.a:(.rodata)\n\t\t*libc.a:(.rodata.*)\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_rodata_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(pinned.data,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_data_start = .;\n\n\t\t. = ALIGN(4);\n\n#include <arch\/x86\/ia32\/scripts\/shared_kernel_pages.ld>\n#include <arch\/x86\/ia32\/scripts\/dynamic_intr.ld>\n\n\t\tLIB_KERNEL_IN_SECT(data)\n\t\tLIB_ARCH_X86_IN_SECT(data)\n\n\t\t*(.pinned_data)\n\t\t*(.pinned_data.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(data)\n\t\tLIB_C_IN_SECT(data)\n\t\tLIB_DRIVERS_IN_SECT(data)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(data)\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n#include <linker\/kobject-data.ld>\n\n\tlnkr_pinned_data_end = .;\n\n\tSECTION_PROLOGUE(pinned.bss, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_pinned_bss_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(bss)\n\t\tLIB_ARCH_X86_IN_SECT(bss)\n\n\t\t*(.pinned_bss)\n\t\t*(.pinned_bss.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(bss)\n\t\tLIB_C_IN_SECT(bss)\n\t\tLIB_DRIVERS_IN_SECT(bss)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(bss)\n\n\t\tlnkr_pinned_bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t\/* PINNED APP SHARED MEMORY REGION *\/\n#include <app_smem_pinned.ld>\n\n\t_app_smem_pinned_size = _app_smem_pinned_end - _app_smem_pinned_start;\n\t_app_smem_pinned_num_words = _app_smem_pinned_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(pinned.noinit, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_pinned_noinit_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(noinit)\n\t\tLIB_ARCH_X86_IN_SECT(noinit)\n\n\t\t*(.pinned_noinit)\n\t\t*(.pinned_noinit.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(noinit)\n\t\tLIB_C_IN_SECT(noinit)\n\t\tLIB_DRIVERS_IN_SECT(noinit)\n\t\tLIB_SUBSYS_LOGGING_IN_SECT(noinit)\n\n#ifdef CONFIG_ZTEST\n\t\t\/* For tests\/kernel\/mem_slab\/ tests *\/\n\t\t*(.noinit.*.k_mem_slab_buf_*)\n\n\t\t\/* For tests\/kernel\/mem_heap tests *\/\n\t\t*(.noinit.*.kheap_buf_*)\n\n\t\t\/* Pin ztest_thread_stack.\n\t\t * This must be done or else double fault\n\t\t * may arise: testing exceptions while\n\t\t * page fault for the ztest stack.\n\t\t *\/\n\t\t*libsubsys__testsuite__ztest.a:(.noinit.*)\n#endif\n\n\t\tlnkr_pinned_noinit_end = .;\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_pinned_end = .;\n\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tlnkr_pinned_text_size = lnkr_pinned_text_end - lnkr_pinned_text_start;\n\tlnkr_pinned_rodata_size = lnkr_pinned_rodata_end - lnkr_pinned_rodata_start;\n\tlnkr_pinned_data_size = lnkr_pinned_data_end - lnkr_pinned_data_start;\n\tlnkr_pinned_bss_size = lnkr_pinned_bss_end - lnkr_pinned_bss_start;\n\tlnkr_pinned_noinit_size = lnkr_pinned_noinit_end - lnkr_pinned_noinit_start;\n\n#endif \/* CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n\/* From now on, put symbols into FLASH *\/\n#undef ROMABLE_REGION\n#define ROMABLE_REGION\tFLASH\n\n\t\/* This is to align the following sections in flash\n\t * to their corresponding virtual addresses.\n\t * In other words, the offset from start of flash\n\t * for these sections would be the same from start of\n\t * their virtual addresses. This provides a simple and\n\t * direct mapping from backing store.\n\t *\/\n\tflash_load_offset :\n\t{\n\t\t. = FLASH_ROM_ADDR + (lnkr_pinned_end - KERNEL_BASE_ADDR);\n\t} > FLASH AT > FLASH\n\n#endif\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \\\n    !defined(CONFIG_LINKER_USE_PINNED_SECTION)\n\tz_mapped_start = .;\n#endif\n\n#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \\\n    !defined(CONFIG_LINKER_USE_PINNED_SECTION)\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n#endif\n\n\t\/* Needs KEEP() as ENTRY() is given a physical address *\/\n\tKEEP(*(.text.__start))\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <linker\/kobject-text.ld>\n#endif\n\n\tMMU_PAGE_ALIGN_PERM\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__text_region_end = .;\n\t__text_region_size = __text_region_end - __text_region_start;\n\t__rodata_region_start = .;\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n#endif\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <arch\/x86\/ia32\/scripts\/static_intr.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n#endif\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t__rodata_region_end = .;\n\t__rodata_region_size = __rodata_region_end - __rodata_region_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN_PERM\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n#include <linker\/common-noinit.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <arch\/x86\/ia32\/scripts\/dynamic_intr.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <arch\/x86\/ia32\/scripts\/shared_kernel_pages.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/cplusplus-ram.ld>\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <linker\/common-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <linker\/kobject-data.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;\n\n\tz_mapped_end = .;\n\tz_mapped_size = z_mapped_end - z_mapped_start;\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_ZEPHYR_FINAL\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n * Copyright (c) 2021 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <autoconf.h>\n#include <devicetree.h>\n#include <offsets.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n#include <sys\/util.h>\n#include <sys\/mem_manage.h>\n\n\n\/* Bounds of physical RAM from DTS *\/\n#define PHYS_RAM_ADDR\t\t\tDT_REG_ADDR(DT_CHOSEN(zephyr_sram))\n#define PHYS_RAM_SIZE\t\t\tDT_REG_SIZE(DT_CHOSEN(zephyr_sram))\n\n\/* Bounds of flash from DTS *\/\n#define FLASH_ROM_ADDR\t\t\tDT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define FLASH_ROM_SIZE\t\t\tDT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n\n\/* Virtual base address for the kernel; with CONFIG_MMU this is not necessarily\n * the same as its physical location, although an identity mapping for RAM\n * is still supported by setting CONFIG_KERNEL_VM_BASE=CONFIG_SRAM_BASE_ADDRESS.\n *\/\n#ifdef Z_VM_KERNEL\n\n#define KERNEL_BASE_ADDR \\\n\t(CONFIG_KERNEL_VM_BASE + CONFIG_KERNEL_VM_OFFSET)\n\n#define KERNEL_RAM_SIZE \\\n\t(CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET)\n\n#define PHYS_RAM_AVAIL \\\n\t(PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n\n#else\n\n#define KERNEL_BASE_ADDR\t\t(PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n#define KERNEL_RAM_SIZE\t\t\t(PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)\n\n#endif\n\n\/* \"kernel RAM\" for linker VMA allocations starts at the offset *\/\n\n\/* Physical RAM location where the kernel image is loaded *\/\n#define PHYS_LOAD_ADDR\t\t\t(PHYS_RAM_ADDR + CONFIG_SRAM_OFFSET)\n\n#ifdef CONFIG_USERSPACE\n#define SMEM_PARTITION_ALIGN(size)\tMMU_PAGE_ALIGN_PERM\n#define APP_SHARED_ALIGN\t\tMMU_PAGE_ALIGN_PERM\n#endif\n\nMEMORY\n    {\n#if defined(Z_VM_KERNEL)\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_AVAIL\n#endif\n    RAM (wx)        : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n    FLASH (rw)      : ORIGIN = FLASH_ROM_ADDR, LENGTH = FLASH_ROM_SIZE\n#endif\n\n    \/*\n     * On 32-bit x86, fake memory area for build-time IDT generation data.\n     *\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 0xFFFF1000, LENGTH = 2K\n    }\n\n#if defined(Z_VM_KERNEL)\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_MMU\n\t#define MMU_PAGE_ALIGN\t\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n\n#undef SECTION_PROLOGUE\n#define SECTION_PROLOGUE(name, options, align) \\\n        name options : ALIGN_WITH_INPUT align\n\n#undef SECTION_DATA_PROLOGUE\n#define SECTION_DATA_PROLOGUE(name, options, align) \\\n        name options : ALIGN_WITH_INPUT align\n\n#undef GROUP_ROM_LINK_IN\n#define GROUP_ROM_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#undef GROUP_DATA_LINK_IN\n#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#undef GROUP_NOLOAD_LINK_IN\n#define GROUP_NOLOAD_LINK_IN(vregion, lregion) > vregion AT > lregion\n\n#endif\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN_PERM\tMMU_PAGE_ALIGN\n#else\n\t#define MMU_PAGE_ALIGN_PERM\n#endif\n\n\/* For all source files under arch\/x86\/. *\/\n#define LIB_ARCH_X86_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libarch__x86__core.a.a:(.##lsect)\t\t\t\t\\\n\t*libarch__x86__core.a:(.##lsect##.*)\n\n#ifdef CONFIG_MINIMAL_LIBC\n\/* For all source files under lib\/libc\/minimal\/.\n * These files includes, for example, math and string functions.\n *\/\n#define LIB_C_IN_SECT(lsect)\t\t\t\t\t\t\\\n\t*liblib__libc__minimal.a:(.##lsect)\t\t\t\t\\\n\t*liblib__libc__minimal.a:(.##lsect##.*)\n\n#endif \/* CONFIG_MINIMAL_LIBC *\/\n\n#ifdef CONFIG_NEWLIB_LIBC\n\/* For Newlib libc-hook.c. *\/\n#define LIB_C_IN_SECT(lsect)\t\t\t\t\t\t\\\n\t*liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect)\t\t\\\n\t*liblib__libc__newlib.a:libc-hooks.c.obj(.##lsect##.*)\n\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n\/*\n * For drivers that are usually used (e.g. serial)\n *\/\n#define LIB_DRIVERS_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libdrivers__serial.a:(.##lsect)\t\t\t\t\\\n\t*libdrivers__serial.a:(.##lsect##.*)\t\t\t\t\\\n\t*hpet.c.obj(.##lsect)\t\t\t\t\t\t\\\n\t*hpet.c.obj(.##lsect##.*)\t\t\t\t\t\\\n\t*intc_ioapic.c.obj(.##lsect)\t\t\t\t\t\\\n\t*intc_ioapic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*intc_loapic.c.obj(.##lsect)\t\t\t\t\t\\\n\t*intc_loapic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*intc_system_apic.c.obj(.##lsect)\t\t\t\t\\\n\t*intc_system_apic.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*rand32_timer.c.obj(.##lsect)\t\t\t\t\t\\\n\t*rand32_timer.c.obj(.##lsect##.*)\t\t\t\t\\\n\t*uart_console.c.obj(.##lsect)\t\t\t\t\t\\\n\t*uart_console.c.obj(.##lsect##.*)\n\n\/* For all source files under kernel\/. and kernel related files *\/\n#define LIB_KERNEL_IN_SECT(lsect)\t\t\t\t\t\\\n\t*libkernel.a:(.##lsect)\t\t\t\t\t\t\\\n\t*libkernel.a:(.##lsect##.*)\t\t\t\t\t\\\n\t*libsubsys__demand_paging__*.a:(.##lsect)\t\t\t\\\n\t*libsubsys__demand_paging__*.a:(.##lsect##.*)\n\n\/* For particular file packaged in libzephyr.a. *\/\n#define LIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, objfile)\t\t\t\\\n\t*libzephyr.a:objfile.c.obj(.##lsect)\t\t\t\t\\\n\t*libzephyr.a:objfile.c.obj(.##lsect##.*)\n\n\/* For source files under lib\/os\/ with commonly used functions. *\/\n#define LIB_ZEPHYR_IN_SECT(lsect)\t\t\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, assert)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, bitarray)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_complete)\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, cbprintf_nano)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, configs)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, heap-validate)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, mutex)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, notify)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, printk)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sem)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, stdout_console)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, sys_clock_init)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, rb)\t\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, thread_entry)\t\t\\\n\tLIB_ZEPHYR_OBJECT_FILE_IN_SECT(lsect, work_q)\n\n\/*\n * Catch all for all internal\/external kernel functions\n * as they are usually defined as \"static inline\" where\n * they are attached to the source which uses them.\n * Hence the need to specify them here so they can be pinned.\n *\/\n#define ZEPHYR_KERNEL_FUNCS_IN_SECT\t\t\t\t\t\\\n\t*(.text.atomic_*)\t\t\t\t\t\t\\\n\t*(.text.k_*)\t\t\t\t\t\t\t\\\n\t*(.text.sys_*_bit)\t\t\t\t\t\t\\\n\t*(.text.sys_bitfield_*)\t\t\t\t\t\t\\\n\t*(.text.sys_clock_hw_cycles_per_sec)\t\t\t\t\\\n\t*(.text.sys_cache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_dcache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_icache_*)\t\t\t\t\t\t\\\n\t*(.text.sys_mutex_*)\t\t\t\t\t\t\\\n\t*(.text.sys_notify_*)\t\t\t\t\t\t\\\n\t*(.text.sys_dlist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_slist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_sflist_*)\t\t\t\t\t\t\\\n\t*(.text.sys_sfnode_*)\t\t\t\t\t\t\\\n\t*(.text.sys_io_*)\t\t\t\t\t\t\\\n\t*(.text.sys_in*)\t\t\t\t\t\t\\\n\t*(.text.sys_out*)\t\t\t\t\t\t\\\n\t*(.text.sys_read*)\t\t\t\t\t\t\\\n\t*(.text.sys_write*)\t\t\t\t\t\t\\\n\t*(.text.sys_get_be*)\t\t\t\t\t\t\\\n\t*(.text.sys_get_le*)\t\t\t\t\t\t\\\n\t*(.text.sys_put_be*)\t\t\t\t\t\t\\\n\t*(.text.sys_put_le*)\t\t\t\t\t\t\\\n\t*(.text.sys_mem_swap)\t\t\t\t\t\t\\\n\t*(.text.sys_memcpy_swap)\t\t\t\t\t\\\n\t*(.text.z_*)\n\nepoint = Z_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY);\nENTRY(epoint)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n#ifdef CONFIG_LINKER_USE_BOOT_SECTION\n\n\tSECTION_PROLOGUE(boot.text,,)\n\t{\n#include <snippets-rom-start.ld>\n\n\t\tMMU_PAGE_ALIGN\n\t\tlnkr_boot_start = .;\n\t\tz_mapped_start = .;\n\n\t\tlnkr_boot_text_start = .;\n\n\t\tKEEP(*(.boot_text.__start))\n\t\t*(.boot_text)\n\t\t*(.boot_text.*)\n\n\t\t*(.text.k_mem_paging_backing_store_init)\n\t\t*(.text.k_mem_paging_eviction_init)\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_text_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.rodata,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_rodata_start = .;\n\n\t\t*(.boot_rodata)\n\t\t*(.boot_rodata.*)\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_boot_rodata_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.data,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_data_start = .;\n\n\t\t*(.boot_data)\n\t\t*(.boot_data.*)\n\n\t\tlnkr_boot_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.bss, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_bss_start = .;\n\n\t\t*(.boot_bss)\n\t\t*(.boot_bss.*)\n\n\t\tlnkr_boot_bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(boot.noinit, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_boot_noinit_start = .;\n\n\t\t*(.boot_noinit)\n\t\t*(.boot_noinit.*)\n\n\t\tlnkr_boot_noinit_end = .;\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_boot_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tlnkr_boot_text_size = lnkr_boot_text_end - lnkr_boot_text_start;\n\tlnkr_boot_rodata_size = lnkr_boot_rodata_end - lnkr_boot_rodata_start;\n\tlnkr_boot_data_size = lnkr_boot_data_end - lnkr_boot_data_start;\n\tlnkr_boot_bss_size = lnkr_boot_bss_end - lnkr_boot_bss_start;\n\tlnkr_boot_noinit_size = lnkr_boot_noinit_end - lnkr_boot_noinit_start;\n\n#endif \/* CONFIG_LINKER_USE_BOOT_SECTION *\/\n\n#ifdef CONFIG_LINKER_USE_PINNED_SECTION\n\n\tSECTION_PROLOGUE(pinned.text,,)\n\t{\n#ifndef CONFIG_LINKER_USE_BOOT_SECTION\n#include <snippets-rom-start.ld>\n#endif\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_pinned_start = .;\n\n#ifndef CONFIG_LINKER_USE_BOOT_SECTION\n\t\tz_mapped_start = .;\n#endif\n\n\t\tlnkr_pinned_text_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(text)\n\t\tLIB_ARCH_X86_IN_SECT(text)\n\t\t*(.text._OffsetAbsSyms)\n\n\t\t*(.pinned_text)\n\t\t*(.pinned_text.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(text)\n\t\tLIB_C_IN_SECT(text)\n\t\tLIB_DRIVERS_IN_SECT(text)\n\n\t\t*_divdi3.o(.text)\n\t\t*_udivdi3.o(.text)\n\t\t*_udivmoddi4.o(.text)\n\t\t*_umoddi3.o(.text)\n\t\t*_popcountsi2.o(.text)\n\n\t\t*(.gnu.linkonce.t.exc_*)\n\n\t\t*(.text.*.constprop)\n\t\t*(.text.*.constprop.*)\n\n#ifdef CONFIG_NEWLIB_LIBC\n\t\t*libc.a:(.text)\n\t\t*libc.a:(.text.*)\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n\t\tZEPHYR_KERNEL_FUNCS_IN_SECT\n\n#include <linker\/kobject-text.ld>\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_text_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tMMU_PAGE_ALIGN_PERM\n\n\tlnkr_pinned_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n\tSECTION_PROLOGUE(pinned.rodata,,)\n\t{\n#include <arch\/x86\/ia32\/scripts\/static_intr.ld>\n\n\t\tLIB_KERNEL_IN_SECT(rodata)\n\t\tLIB_ARCH_X86_IN_SECT(rodata)\n\n\t\t*(.pinned_rodata)\n\t\t*(.pinned_rodata.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(rodata)\n\t\tLIB_C_IN_SECT(rodata)\n\t\tLIB_DRIVERS_IN_SECT(rodata)\n\n\t\t\/* Static strings *\/\n\t\t*(.rodata.str*.*)\n\t\t*(.rodata.*.str*.*)\n\n#ifdef CONFIG_NEWLIB_LIBC\n\t\t*libc.a:(.rodata)\n\t\t*libc.a:(.rodata.*)\n#endif \/* CONFIG_NEWLIB_LIBC *\/\n\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_rodata_end = .;\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(pinned.data,,)\n\t{\n\t\tMMU_PAGE_ALIGN_PERM\n\n\t\tlnkr_pinned_data_start = .;\n\n\t\t. = ALIGN(4);\n\n#include <arch\/x86\/ia32\/scripts\/shared_kernel_pages.ld>\n#include <arch\/x86\/ia32\/scripts\/dynamic_intr.ld>\n\n\t\tLIB_KERNEL_IN_SECT(data)\n\t\tLIB_ARCH_X86_IN_SECT(data)\n\n\t\t*(.pinned_data)\n\t\t*(.pinned_data.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(data)\n\t\tLIB_C_IN_SECT(data)\n\t\tLIB_DRIVERS_IN_SECT(data)\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n#include <linker\/kobject-data.ld>\n\n\tlnkr_pinned_data_end = .;\n\n\tSECTION_PROLOGUE(pinned.bss, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_pinned_bss_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(bss)\n\t\tLIB_ARCH_X86_IN_SECT(bss)\n\n\t\t*(.pinned_bss)\n\t\t*(.pinned_bss.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(bss)\n\t\tLIB_C_IN_SECT(bss)\n\t\tLIB_DRIVERS_IN_SECT(bss)\n\n\t\tlnkr_pinned_bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t\/* PINNED APP SHARED MEMORY REGION *\/\n#include <app_smem_pinned.ld>\n\n\t_app_smem_pinned_size = _app_smem_pinned_end - _app_smem_pinned_start;\n\t_app_smem_pinned_num_words = _app_smem_pinned_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(pinned.noinit, (NOLOAD),)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tlnkr_pinned_noinit_start = .;\n\n\t\tLIB_KERNEL_IN_SECT(noinit)\n\t\tLIB_ARCH_X86_IN_SECT(noinit)\n\n\t\t*(.pinned_noinit)\n\t\t*(.pinned_noinit.*)\n\n\t\tLIB_ZEPHYR_IN_SECT(noinit)\n\t\tLIB_C_IN_SECT(noinit)\n\t\tLIB_DRIVERS_IN_SECT(noinit)\n\n#ifdef CONFIG_ZTEST\n\t\t\/* For tests\/kernel\/mem_slab\/ tests *\/\n\t\t*(.noinit.*.k_mem_slab_buf_*)\n\n\t\t\/* For tests\/kernel\/mem_heap tests *\/\n\t\t*(.noinit.*.kheap_buf_*)\n\n\t\t\/* Pin ztest_thread_stack.\n\t\t * This must be done or else double fault\n\t\t * may arise: testing exceptions while\n\t\t * page fault for the ztest stack.\n\t\t *\/\n\t\t*libsubsys__testsuite__ztest.a:(.noinit.*)\n#endif\n\n\t\tlnkr_pinned_noinit_end = .;\n\n\t\tMMU_PAGE_ALIGN\n\n\t\tlnkr_pinned_end = .;\n\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tlnkr_pinned_text_size = lnkr_pinned_text_end - lnkr_pinned_text_start;\n\tlnkr_pinned_rodata_size = lnkr_pinned_rodata_end - lnkr_pinned_rodata_start;\n\tlnkr_pinned_data_size = lnkr_pinned_data_end - lnkr_pinned_data_start;\n\tlnkr_pinned_bss_size = lnkr_pinned_bss_end - lnkr_pinned_bss_start;\n\tlnkr_pinned_noinit_size = lnkr_pinned_noinit_end - lnkr_pinned_noinit_start;\n\n#endif \/* CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n#if defined(CONFIG_DEMAND_PAGING) && !defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)\n\/* From now on, put symbols into FLASH *\/\n#undef ROMABLE_REGION\n#define ROMABLE_REGION\tFLASH\n\n\t\/* This is to align the following sections in flash\n\t * to their corresponding virtual addresses.\n\t * In other words, the offset from start of flash\n\t * for these sections would be the same from start of\n\t * their virtual addresses. This provides a simple and\n\t * direct mapping from backing store.\n\t *\/\n\tflash_load_offset :\n\t{\n\t\t. = FLASH_ROM_ADDR + (lnkr_pinned_end - KERNEL_BASE_ADDR);\n\t} > FLASH AT > FLASH\n\n#endif\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \\\n    !defined(CONFIG_LINKER_USE_PINNED_SECTION)\n\tz_mapped_start = .;\n#endif\n\n#if !defined(CONFIG_LINKER_USE_BOOT_SECTION) || \\\n    !defined(CONFIG_LINKER_USE_PINNED_SECTION)\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n#endif\n\n\t\/* Needs KEEP() as ENTRY() is given a physical address *\/\n\tKEEP(*(.text.__start))\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <linker\/kobject-text.ld>\n#endif\n\n\tMMU_PAGE_ALIGN_PERM\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__text_region_end = .;\n\t__text_region_size = __text_region_end - __text_region_start;\n\t__rodata_region_start = .;\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n#endif\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <arch\/x86\/ia32\/scripts\/static_intr.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n#endif\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t__rodata_region_end = .;\n\t__rodata_region_size = __rodata_region_end - __rodata_region_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN_PERM\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n#include <linker\/common-noinit.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <arch\/x86\/ia32\/scripts\/dynamic_intr.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <arch\/x86\/ia32\/scripts\/shared_kernel_pages.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/cplusplus-ram.ld>\n\n#ifndef CONFIG_LINKER_USE_PINNED_SECTION\n#include <linker\/common-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <linker\/kobject-data.ld>\n#endif \/* !CONFIG_LINKER_USE_PINNED_SECTION *\/\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;\n\n\tz_mapped_end = .;\n\tz_mapped_size = z_mapped_end - z_mapped_start;\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_ZEPHYR_FINAL\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"af57b156c3f7bd6244d8d1cd6439c831259dc2eb","subject":"cpu\/lpc23xx: add support for thread-local storage","message":"cpu\/lpc23xx: add support for thread-local storage\n","repos":"kaspar030\/RIOT,OTAkeys\/RIOT,authmillenon\/RIOT,authmillenon\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,OTAkeys\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,kYc0o\/RIOT,miri64\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,ant9000\/RIOT,kaspar030\/RIOT","old_file":"cpu\/lpc23xx\/ldscripts\/lpc23xx.ld","new_file":"cpu\/lpc23xx\/ldscripts\/lpc23xx.ld","new_contents":"\/*\n * Copyright 2013, Freie Universitaet Berlin (FUB). All rights reserved.\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/* specify the LPC23XX memory areas (see LPC2387 datasheet page 15)  *\/\nMEMORY\n{\n    rom (rx)            : ORIGIN = 0,          LENGTH = 504K    \/* FLASH ROM 512kByte without ISP bootloader*\/\n    infomem             : ORIGIN = 0x0007D000, LENGTH = 4K      \/* Last sector in FLASH ROM for config data *\/\n    ram_battery         : ORIGIN = 0xE0084000, LENGTH = 2K      \/* Battery RAM                              *\/\n    ram (w!rx)          : ORIGIN = 0x40000000, LENGTH = 64K     \/* LOCAL ON-CHIP STATIC RAM                 *\/\n    ram_usb             : ORIGIN = 0x7FD00000, LENGTH = 16K     \/* USB RAM  !!! first 1024 bytes are occupied from GPDMA for MCI *\/\n    ram_ethernet        : ORIGIN = 0x7FE00000, LENGTH = 16K     \/* ethernet RAM                             *\/\n}\n\n\/* now define the output sections  *\/\nSECTIONS\n{\n    .text :                             \/* collect all sections that should go into FLASH after startup  *\/\n    {\n        KEEP(*(.vectors))               \/* Exception Vectors and branch table >= 64 bytes *\/\n        . = ALIGN(64);\n        KEEP(*(.init))\n        KEEP(*(.init0))                 \/* Start here after reset.  *\/\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/*\n     * TLS relocations are offsets relative to the address\n     * of the first TLS symbol. That means we just need to\n     * allocate them all together so that the TLS region\n     * is compact when allocated for each thread.\n     *\/\n\n    \/*\n     * TLS initialization data is loaded into ROM so that\n     * each thread can get its values initialized from there\n     * at startup\n     *\/\n    .tdata :\n    {\n         __tdata_start = .;\n        *(.tdata .tdata.* .gnu.linkonce.td.*)\n        __tdata_end = .;\n    } > rom\n    __tdata_source = LOADADDR(.tdata);\n    __tdata_size = SIZEOF(.tdata);\n\n    \/*\n     * TLS zeroed data is relocated as if it immediately followed\n     * the tdata values. However, the linker 'magically' erases the\n     * memory allocation so that no ROM is consumed by this\n     * section\n     *\/\n    .tbss :\n    {\n        *(.tbss .tbss.* .gnu.linkonce.tb.*)\n        *(.tcommon)\n        __tbss_end = .;\n    } > rom\n    __tls_size = __tbss_end - __tdata_start;\n    __tbss_size = __tls_size - __tdata_size;\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .config :\n    {\n        *(.configmem)\n        . = ALIGN(256);\n    } > infomem\n\n\/**************************************************************************\n * RAM\n **************************************************************************\/\n\n    \/*\n     * Stacks\n     *\/\n    .stack (NOLOAD) :\n    {\n        PROVIDE(__stack_start = .);\n        KEEP (*(.usr_stack))\n        __stack_usr_start = .;\n        KEEP (*(.und_stack))\n        __stack_und_start = .;\n        KEEP (*(.fiq_stack))\n        __stack_fiq_start = .;\n        KEEP (*(.irq_stack))\n        __stack_irq_start = .;\n        KEEP (*(.abt_stack))\n        __stack_abt_start = .;\n        KEEP (*(.svc_stack))\n        __stack_svc_start = .;\n\n        PROVIDE(__stack_end = .);\n    } > ram\n\n    .relocate :\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        KEEP (*(.openocd .openocd.*))\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram AT> rom\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        PROVIDE(__fiq_handler = .);\n        *(.fiq)\n        *(.noinit)\n        . = ALIGN(4);\n        __noinit_end = .;\n    }  > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n\n    .heap1 ALIGN(4) (NOLOAD) :\n    {\n        _sheap1 = ORIGIN(ram_ethernet);\n        _eheap1 = ORIGIN(ram_ethernet) + LENGTH(ram_ethernet);\n    } > ram_ethernet\n\n    . = ORIGIN(ram_usb);\n    .usbdata (NOLOAD) :                 \/* USB RAM section, may be used otherwise if USB is disabled *\/\n    {\n        *(.usbdata)\n    } > ram_usb\n\n    .heap2 ALIGN(4) (NOLOAD) :\n    {\n        _sheap2 = . ;\n        _eheap2 = ORIGIN(ram_usb) + LENGTH(ram_usb);\n    } > ram_usb\n\n    _sbackup_data_load = LOADADDR(.backup.data);\n    .backup.data :  ALIGN(4) {\n        _sbackup_data = .;\n        *(.backup.data)\n        _ebackup_data = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > ram_battery AT> rom\n\n    .backup.bss (NOLOAD) : ALIGN(4) {\n        _sbackup_bss = .;\n        *(.backup.bss)\n        _ebackup_bss = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > ram_battery\n\n    .heap3 (NOLOAD) : ALIGN(4) {\n        _sheap3 = . ;\n        _eheap3 = ORIGIN(ram_battery) + LENGTH(ram_battery);\n    } > ram_battery\n}\n","old_contents":"\/*\n * Copyright 2013, Freie Universitaet Berlin (FUB). All rights reserved.\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/* specify the LPC23XX memory areas (see LPC2387 datasheet page 15)  *\/\nMEMORY\n{\n    rom (rx)            : ORIGIN = 0,          LENGTH = 504K    \/* FLASH ROM 512kByte without ISP bootloader*\/\n    infomem             : ORIGIN = 0x0007D000, LENGTH = 4K      \/* Last sector in FLASH ROM for config data *\/\n    ram_battery         : ORIGIN = 0xE0084000, LENGTH = 2K      \/* Battery RAM                              *\/\n    ram (w!rx)          : ORIGIN = 0x40000000, LENGTH = 64K     \/* LOCAL ON-CHIP STATIC RAM                 *\/\n    ram_usb             : ORIGIN = 0x7FD00000, LENGTH = 16K     \/* USB RAM  !!! first 1024 bytes are occupied from GPDMA for MCI *\/\n    ram_ethernet        : ORIGIN = 0x7FE00000, LENGTH = 16K     \/* ethernet RAM                             *\/\n}\n\n\/* now define the output sections  *\/\nSECTIONS\n{\n    .text :                             \/* collect all sections that should go into FLASH after startup  *\/\n    {\n        KEEP(*(.vectors))               \/* Exception Vectors and branch table >= 64 bytes *\/\n        . = ALIGN(64);\n        KEEP(*(.init))\n        KEEP(*(.init0))                 \/* Start here after reset.  *\/\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .config :\n    {\n        *(.configmem)\n        . = ALIGN(256);\n    } > infomem\n\n\/**************************************************************************\n * RAM\n **************************************************************************\/\n\n    \/*\n     * Stacks\n     *\/\n    .stack (NOLOAD) :\n    {\n        PROVIDE(__stack_start = .);\n        KEEP (*(.usr_stack))\n        __stack_usr_start = .;\n        KEEP (*(.und_stack))\n        __stack_und_start = .;\n        KEEP (*(.fiq_stack))\n        __stack_fiq_start = .;\n        KEEP (*(.irq_stack))\n        __stack_irq_start = .;\n        KEEP (*(.abt_stack))\n        __stack_abt_start = .;\n        KEEP (*(.svc_stack))\n        __stack_svc_start = .;\n\n        PROVIDE(__stack_end = .);\n    } > ram\n\n    .relocate :\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        KEEP (*(.openocd .openocd.*))\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram AT> rom\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        PROVIDE(__fiq_handler = .);\n        *(.fiq)\n        *(.noinit)\n        . = ALIGN(4);\n        __noinit_end = .;\n    }  > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n\n    .heap1 ALIGN(4) (NOLOAD) :\n    {\n        _sheap1 = ORIGIN(ram_ethernet);\n        _eheap1 = ORIGIN(ram_ethernet) + LENGTH(ram_ethernet);\n    } > ram_ethernet\n\n    . = ORIGIN(ram_usb);\n    .usbdata (NOLOAD) :                 \/* USB RAM section, may be used otherwise if USB is disabled *\/\n    {\n        *(.usbdata)\n    } > ram_usb\n\n    .heap2 ALIGN(4) (NOLOAD) :\n    {\n        _sheap2 = . ;\n        _eheap2 = ORIGIN(ram_usb) + LENGTH(ram_usb);\n    } > ram_usb\n\n    _sbackup_data_load = LOADADDR(.backup.data);\n    .backup.data :  ALIGN(4) {\n        _sbackup_data = .;\n        *(.backup.data)\n        _ebackup_data = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > ram_battery AT> rom\n\n    .backup.bss (NOLOAD) : ALIGN(4) {\n        _sbackup_bss = .;\n        *(.backup.bss)\n        _ebackup_bss = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > ram_battery\n\n    .heap3 (NOLOAD) : ALIGN(4) {\n        _sheap3 = . ;\n        _eheap3 = ORIGIN(ram_battery) + LENGTH(ram_battery);\n    } > ram_battery\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"f51fd275d8aaa5889ee3f31b749f6a85753c80d2","subject":"*** empty log message ***","message":"*** empty log message ***\n","repos":"adplug\/adplug,adplug\/adplug","old_file":"test\/loudness.lds","new_file":"test\/loudness.lds","new_contents":"","old_contents":"\u0000\u0000C\u0005@\u0000\u0002\u0000\u0001\u0001\u0002\u0002\u0001\u0000\u0000\t\u0000!)b\u0000\u0001?\u0003\f\u0000\u0000\u0000\u0000\u0018_\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000>x\u0000\u0000\u0000\u0000!)b\u0000\u00018\u0003\f\u0000\u0000\u0000\u0001\u0018_\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000>d\u0000\u0000\u0000\u0000\u0001?4\u0000\u00018\u0000\u0000\u0000\u0000\u0000\u0000\f\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000&0\u0000\u0000\u0000.\u0002\u0000:\u0002\u0000\u0000\u0000\u0000\u0010\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u00002`@\u0000\u0000\u0000\u0000?\u0000\u0001?\u0000\u0006\f\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\f\u0000\u0000\u0000\u0000\u0000\u0000\u0000x\u0000\u0000\u0000\u0000\u0001?\u0002\u0002?\u0016\u0000\u000f\n\u0004\u0000\u0000\u0000\u0000\u0000\u0000\u001c\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000p\u0000\u0000\u0000\u0000\u0001?\u0003\u000f=\u0003\u000e\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000`\u0000\u0000\u0000\u0000\u0002?\u0015\u0001\u000f?4\u0000\u000e\u0000\u0000\u0000\u0003\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000`\u0000\u0000\u0000\u0000\u0001?<\u0001\u0000?\u0000\u000e\u0010\t\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000vh\u0000\u0000\u0000\u0001\u0000\u0004\u0000\u0000`\u0000\u0000\u0000\u0000\u0000\u0000\b\u0001\u0000 \u0001\u0000\u0001\u0000p\u0001\u00008\u0001\u0000\u0001\u0005>\u0000H\u0000\u0000J\u0000\u0000\u0000H\u0000\u0000J\u0000\u0000\u0000H\u0000\u0000J\u0000\u0000\u0000H\u0000\u0000\u0000E\u0000\u0000\u0000H\u0002\u0000E\u0000\u0000\u0000C\u0000\u0000\u0000C\u0000\u0000\u0000E\u0000\u0000\u0000A\u0000\u0000\u0000@\u0000\u0000\u0000>\u000b\u0000\u0000J\u0000\u0000\u0000J\u0001,\u0000J\u0001\u0018\u0000J\u0002\u0000\u0001\u0000\u0001L\u0000\u0001M\u0000\u0000\u0001L\u0000\u0001M\u0000\u0000\u0001L\u0000\u0001M\u0000\u0000\u0001L\u0000\u0000\u0001J\u0000\u0000\u0001L\u0002\u0001L\u0000\u0000\u0001M\u0000\u0000\u0001M\u0000\u0000\u0001L\u0000\u0000\u0001J\u0000\u0000\u0001H\u0000\u0000\u0001E\u000b\u0000\u0001>\u0000\u0000\u00012\u0001,\u00012\u0001\u0018\u00012\u0002\u0000\u0002\u0002\"\u0004\u0002\"\u0002\u0002\"\u0000\u0000\u0002!\u0000\u0000\u0002\"\u0000\u0000\u0002$\u0004\u0002$\u0002\u0002!\u0000\u0000\u0002$\u0002\u0002&\u000b\u0000\u0002","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"87baf75a8138005ab2d66f17b5f5b49767547080","subject":"Required linker script changes for the beagleboard target to work with the ARM7 PhysicalMemoryManager","message":"Required linker script changes for the beagleboard target to work with the ARM7 PhysicalMemoryManager\n","repos":"jmolloy\/pedigree,jmolloy\/pedigree,jmolloy\/pedigree,jmolloy\/pedigree,jmolloy\/pedigree,jmolloy\/pedigree,jmolloy\/pedigree","old_file":"src\/system\/kernel\/link-arm-beagle.ld","new_file":"src\/system\/kernel\/link-arm-beagle.ld","new_contents":"\/* Link.ld -- Linker script for the kernel - ensure everything goes in the *\/\n\/*            Correct place.  *\/\nOUTPUT_ARCH(arm)\nENTRY(start)\nSECTIONS\n{\n    . = 0x80100000;\n    __start = .;\n    \n    .init :\n    {\n        . = ALIGN(4096);\n        init = .; _init = .; __init = .;\n        *(.init.text);\n        *(.init.data);\n    }\n    \n    .text :\n    {\n        . = ALIGN(4096);\n        code = .; _code = .; __code = .;\n        *(.text*);\n    }\n\n    .ctors :\n    {\n        . = ALIGN(4096);\n        start_ctors = .;\n        *(.init_array);\n        *(.ctors);\n        end_ctors = .;\n    }\n\n    .data :\n    {\n        \n        . = ALIGN(4096);\n        data = .; _data = .; __data = .;\n        *(.data);\n        *(.rodata*);\n    }\n\n    .bss :\n    {\n        . = ALIGN(4096);\n        bss = .; _bss = .; __bss = .;\n        *(.asm.bss);\n        *(.bss*);\n        *(.sbss);\n    }\n\n  \/DISCARD\/ : { *(.comment) *(.eh_frame) *(.debug_abbrev) *(.debug_info) *(.debug_line) *(.debug_loc) *(.debug_pubnames) *(.debug_aranges) *(.debug_str) *(.debug_macinfo) *(.debug_ranges) *(.stab) *(.stabstr) }\n\n    . = ALIGN(4096);\n    end = .; _end = .; __end = .;\n}\n","old_contents":"\/* Link.ld -- Linker script for the kernel - ensure everything goes in the *\/\n\/*            Correct place.  *\/\nOUTPUT_ARCH(arm)\nENTRY(start)\nSECTIONS\n{\n    . = 0x80100000;\n    .text :\n    {\n        code = .; _code = .; __code = .;\n        *(.text*)\n        . = ALIGN(4096);\n    }\n\n    .data :\n    {\n        start_ctors = .;\n        *(.ctors)\n        end_ctors = .;\n        \n\n        data = .; _data = .; __data = .;\n        *(.data)\n        *(.rodata*)\n        \n        . = ALIGN(4096);\n        \n    \t__strtab = .;\n\t    *(.strtab)\n    \t__strtab_end = .;\n    }\n\n    .bss :\n    {\n        bss = .; _bss = .; __bss = .;\n        *(.bss)\n        *(.sbss)\n        . = ALIGN(4096);\n    }\n\n    \/DISCARD\/ : { *(.comment) }\n\n    end = .; _end = .; __end = .;\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"ad0bf94f772d28d12986bd17552575442147f9f7","subject":"linker: esp32: fix empty iterable symbols","message":"linker: esp32: fix empty iterable symbols\n\nZ_ITERABLE_SECTION_ROM symbols were empty, meaning\nthat those symbols were not taking place in the linker script.\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n#if defined(CONFIG_NET_SOCKETS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_socket_register);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(settings_handler_static);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_BT_BREDR)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(bt_l2cap_br_fixed_chan);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE(bt_mesh_subnet_cb);\n    Z_LINK_ITERABLE(bt_mesh_app_key_cb);\n    Z_LINK_ITERABLE(bt_mesh_hb_cb);\n#endif\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(bt_gatt_service_static);\n    . = ALIGN(4);\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(bt_l2cap_fixed_chan);\n    . = ALIGN(4);\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"771f71e3513d2c4688c027b0def54c8042a50bc8","subject":"Update S210 linker script for S210 3.0.0.","message":"Update S210 linker script for S210 3.0.0.\n","repos":"jf87\/nrf51-pure-gcc-setup","old_file":"template\/gcc_nrf51_s210.ld","new_file":"template\/gcc_nrf51_s210.ld","new_contents":"\/* Linker script to configure memory regions. *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0xC000, LENGTH = 0x34000 \/* 48 kB is taken by S210, 80 kB for app. *\/\r\n  RAM (rwx) : ORIGIN = 0x20000900, LENGTH = 0x3700 \/* 2.25 kB is taken by S210, 13.75 kB for app.  *\/\r\n}\r\nINCLUDE \"gcc_nrf51_common.ld\"\r\n","old_contents":"\/* Linker script to configure memory regions. *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0xA000, LENGTH = 0x36000 \/* 128k, 128k is taken by S110 *\/\r\n  RAM (rwx) : ORIGIN = 0x20000800, LENGTH = 0x3800 \/* 8k, 8k is taken by S110 *\/\r\n}\r\nINCLUDE \"gcc_nrf51_common.ld\"\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"7f9f9a17c9bfdbe4d2d275357d46adbab8bd3b29","subject":"bss section in regular kernel section required COMMON.","message":"bss section in regular kernel section required COMMON.\n","repos":"jspaulse\/sugarcat,jspaulse\/sugarcat,jspaulse\/sugarcat","old_file":"source\/mach\/vexpress_a9\/kernel.ld","new_file":"source\/mach\/vexpress_a9\/kernel.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_vexpress_boot)\n\n\/*\n * specify the physical start & virtual start\n * where the kernel will reside in memory\n *\/\nkp_start\t= 0x60000000;\nkv_start \t= 0x80000000;\n\nSECTIONS {\n    . = kp_start; \t\t\/* physical start *\/\n    \n    \/* define region for kern pgd *\/\n    . += 0x4000;\t\t\/* . = 0x60004000; *\/\n    k_pgd = .;\n    . += 0x4000;\t\t\/* . = 0x60008000; *\/\n    \n    \/*\n     * lm_init is the initialization section\n     * for low memory; this region will be consumed\n     * once initialization is complete\n     *\/\n    .lm_init : {\n\tlmi_start = .;\n\t\t\n\t\/* text *\/\n\tbuild\/vexpress_boot.o(.text)\t\t\t\/* vexpress_boot.s *\/\n\tbuild\/vexpress_boot_init.o(.text .text.*)\t\/* vexpress_boot_init.c *\/\n\tbuild\/vexpress_init.o(.text .text.*)\t\t\n\tbuild\/mach_init_printf.o(.text .text.*)\n\t\t\n\t\/* rodata *\/\n\tbuild\/vexpress_boot.o(.rodata .rodata.*)\n\tbuild\/vexpress_boot_init.o(.rodata .rodata.*)\n\tbuild\/vexpress_init.o(.rodata .rodata.*)\n\tbuild\/mach_init_printf.o(.rodata .rodata.*)\n\t\t\n\t\/* data *\/\n\tbuild\/vexpress_boot.o(.data .data.*)\n\tbuild\/vexpress_boot_init.o(.data .data.*)\n\tbuild\/vexpress_init.o(.data .data.*)\n\tbuild\/mach_init_printf.o(.data .data.*)\n\t\t\n\t\/* bss *\/\n\tlmi_bss_start \t= .;\n\tbuild\/vexpress_boot.o(.bss .bss.* COMMON)\n\tbuild\/vexpress_boot_init.o(.bss .bss.* COMMON)\n\tbuild\/vexpress_init.o(.bss .bss.* COMMON)\n\tbuild\/mach_init_printf.o(.bss .bss.* COMMON)\n\tlmi_bss_end\t= .;\n\t. = ALIGN(0x1000);\n\t\n\t\/* k_stack *\/\n\t. += 0x1000;\n\tk_stack = .;\n\n\t\/* align to page *\/\n\t. = ALIGN(0x1000);\n\tlmi_end = .;\n    }\n    \n    \/*\n     * start of high memory (technically, still low physically)\n     * this is where the majority of the kernel resides \n     *\/\n    . = kv_start + (lmi_end - kp_start);\n\n    \/*\n     * init region of main kernel;\n     * this exists in high memory but will be consumed\n     * once init is completed\n     *\/\n    .hm_init : AT(lmi_end) {\n\thmi_start \t= .;\n\t\n\tbuild\/kernel_init.o(.text .text.*)\t\t\/* kernel_init.c .text \t*\/\n\tbuild\/kernel_init.o(.rodata .rodata.*)\t\t\/* kernel_init.c .rodata *\/\n\tbuild\/kernel_init.o(.data .data.*)\t\t\/* kernel_init.c .data \t*\/\n\t\n\thmi_bss_start \t= .;\t\n\tbuild\/vexpress_init.o(.bss .bss.* COMMON)\t\/* kernel_init.c .bss\t*\/\n\thmi_bss_end\t= .;\n\t\n\t\/* align to page *\/\n\t. = ALIGN(0x1000);\n\thmi_end\t\t= .;\n    }\n    \n    \/*\n     * this is where the rest of the kernel resides\n     * the initialization routines will be consumed and\n     * only this portion of the kernel will remain.\n     *\/\n    k_start = .;\n    .text : AT((kp_start + (hmi_end - kv_start))) { \n\t*(.text .text* .gnu.linkonce.t.*) \n    }\n    \n    .rodata : { *(.rodata*) } \n    .data : { *(.data*) } \n    .bss : { \n\tk_bss_start \t= .;\n\t*(.bss .bss.* COMMON) \n\tk_bss_end\t= .;\n    }\n\t\n    . = ALIGN(0x1000);\n    k_end = .;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_vexpress_boot)\n\n\/*\n * specify the physical start & virtual start\n * where the kernel will reside in memory\n *\/\nkp_start\t= 0x60000000;\nkv_start \t= 0x80000000;\n\nSECTIONS {\n    . = kp_start; \t\t\/* physical start *\/\n    \n    \/* define region for kern pgd *\/\n    . += 0x4000;\t\t\/* . = 0x60004000; *\/\n    k_pgd = .;\n    . += 0x4000;\t\t\/* . = 0x60008000; *\/\n    \n    \/*\n     * lm_init is the initialization section\n     * for low memory; this region will be consumed\n     * once initialization is complete\n     *\/\n    .lm_init : {\n\tlmi_start = .;\n\t\t\n\t\/* text *\/\n\tbuild\/vexpress_boot.o(.text)\t\t\t\/* vexpress_boot.s *\/\n\tbuild\/vexpress_boot_init.o(.text .text.*)\t\/* vexpress_boot_init.c *\/\n\tbuild\/vexpress_init.o(.text .text.*)\t\t\n\tbuild\/mach_init_printf.o(.text .text.*)\n\t\t\n\t\/* rodata *\/\n\tbuild\/vexpress_boot.o(.rodata .rodata.*)\n\tbuild\/vexpress_boot_init.o(.rodata .rodata.*)\n\tbuild\/vexpress_init.o(.rodata .rodata.*)\n\tbuild\/mach_init_printf.o(.rodata .rodata.*)\n\t\t\n\t\/* data *\/\n\tbuild\/vexpress_boot.o(.data .data.*)\n\tbuild\/vexpress_boot_init.o(.data .data.*)\n\tbuild\/vexpress_init.o(.data .data.*)\n\tbuild\/mach_init_printf.o(.data .data.*)\n\t\t\n\t\/* bss *\/\n\tlmi_bss_start \t= .;\n\tbuild\/vexpress_boot.o(.bss .bss.* COMMON)\n\tbuild\/vexpress_boot_init.o(.bss .bss.* COMMON)\n\tbuild\/vexpress_init.o(.bss .bss.* COMMON)\n\tbuild\/mach_init_printf.o(.bss .bss.* COMMON)\n\tlmi_bss_end\t= .;\n\t. = ALIGN(0x1000);\n\t\n\t\/* k_stack *\/\n\t. += 0x1000;\n\tk_stack = .;\n\n\t\/* align to page *\/\n\t. = ALIGN(0x1000);\n\tlmi_end = .;\n    }\n    \n    \/*\n     * start of high memory (technically, still low physically)\n     * this is where the majority of the kernel resides \n     *\/\n    . = kv_start + (lmi_end - kp_start);\n    \n    \/*\n     * init region of main kernel;\n     * this exists in high memory but will be consumed\n     * once init is completed\n     *\/\n    .hm_init : AT(lmi_end) {\n\thmi_start \t= .;\n\t\n\tbuild\/kernel_init.o(.text .text.*)\t\t\/* kernel_init.c .text \t*\/\n\tbuild\/kernel_init.o(.rodata .rodata.*)\t\t\/* kernel_init.c .rodata *\/\n\tbuild\/kernel_init.o(.data .data.*)\t\t\/* kernel_init.c .data \t*\/\n\t\n\thmi_bss_start \t= .;\t\n\tbuild\/vexpress_init.o(.bss .bss.* COMMON)\t\/* kernel_init.c .bss\t*\/\n\thmi_bss_end\t= .;\n\t\n\t\/* align to page *\/\n\t. = ALIGN(0x1000);\n\thmi_end\t\t= .;\n    }\n    \n    \/*\n     * this is where the rest of the kernel resides\n     * the initialization routines will be consumed and\n     * only this portion of the kernel will remain.\n     *\/\n    k_start = .;\n    .text : AT((kp_start + (hmi_end - kv_start))) { \n\t*(.text .text* .gnu.linkonce.t.*) \n    }\n    \n    .rodata : { *(.rodata*) } \n    .data : { *(.data*) } \n    .bss : { \n\tk_bss_start \t= .;\n\t*(.bss*) \n\tk_bss_end\t= .;\n    }\n\t\n    . = ALIGN(0x1000);\n    k_end = .;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c112e06e4aea559ee60892a2cb0fc73819fd169b","subject":"- new 3.0.6 kernel load script","message":"- new 3.0.6 kernel load script\n","repos":"0x7678\/openss7,kerr-huang\/openss7,openss7\/openss7,kerr-huang\/openss7,0x7678\/openss7,openss7\/openss7,0x7678\/openss7,0x7678\/openss7,kerr-huang\/openss7,kerr-huang\/openss7,openss7\/openss7,0x7678\/openss7,openss7\/openss7,openss7\/openss7,0x7678\/openss7,openss7\/openss7,0x7678\/openss7,openss7\/openss7,kerr-huang\/openss7,kerr-huang\/openss7,kerr-huang\/openss7,0x7678\/openss7,kerr-huang\/openss7,openss7\/openss7","old_file":"scripts\/hot.lds","new_file":"scripts\/hot.lds","new_contents":"SECTIONS\n{\n\t\/DISCARD\/\t\t: { *(.discard) }\n\n\t.text\t\t\t: { *(.text.streams.hot.put)\n\t\t\t\t    *(.text.streams.hot.write)\n\t\t\t\t    *(.text.streams.hot.out)\n\t\t\t\t    *(.text.streams.hot)\n\t\t\t\t    *(.text.streams.hot.in)\n\t\t\t\t    *(.text.streams.hot.read)\n\t\t\t\t    *(.text.streams.hot.get)\n\t\t\t\t    *(.text)\n\t\t\t\t    *(.text.streams.unlikely) }\n\/*\n\t.text.unlikely\t\t: { *(.text.streams.unlikely)\t\t*(.text.unlikely)\t}\n *\/\n\t__ksymtab\t\t: { *(SORT(___ksymtab+*))\t\t*(__ksymtab)\t\t}\n\t__ksymtab_gpl\t\t: { *(SORT(___ksymtab_gpl+*))\t\t*(__ksymtab_gpl)\t}\n\t__ksymtab_unused\t: { *(SORT(___ksymtab_unused+*))\t*(__ksymtab_unused)\t}\n\t__ksymtab_unused_gpl\t: { *(SORT(___ksymtab_unused_gpl+*))\t*(__ksymtab_unused_gpl)\t}\n\t__ksymtab_gpl_future\t: { *(SORT(___ksymtab_gpl_future+*))\t*(__ksymtab_gpl_future)\t}\n\t__kcrctab\t\t: { *(SORT(___kcrctab+*))\t\t*(__kcrctab)\t\t}\n\t__kcrctab_gpl\t\t: { *(SORT(___kcrctab_gpl+*))\t\t*(__kcrctab_gpl)\t}\n\t__kcrctab_unused\t: { *(SORT(___kcrctab_unused+*))\t*(__kcrctab_unused)\t}\n\t__kcrctab_unused_gpl\t: { *(SORT(___kcrctab_unused_gpl+*))\t*(__kcrctab_unused_gpl)\t}\n\t__kcrctab_gpl_future\t: { *(SORT(___kcrctab_gpl_future+*))\t*(__kcrctab_gpl_future)\t}\n}\n","old_contents":"SECTIONS\n{\n\t.text :\n\t{\n\t\t*(.text.streams.hot.put)\n\t\t*(.text.streams.hot.write)\n\t\t*(.text.streams.hot.out)\n\t\t*(.text.streams.hot)\n\t\t*(.text.streams.hot.in)\n\t\t*(.text.streams.hot.read)\n\t\t*(.text.streams.hot.get)\n\t\t*(.text)\n\t\t*(.text.streams.unlikely)\n\t}\n}\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"6afea0e81c55a91879e349fc5ed14824915276e7","subject":"linker scripts: Add explicit symbols for _iram_start and _flash_cache_start","message":"linker scripts: Add explicit symbols for _iram_start and _flash_cache_start\n\nThis is to avoid confusion when idf_monitor prints the first symbol in each section, ie \"WindowOverflow4\" or similar,\nwhen bootloader prints the section mapping address.\n\nCloses #447 https:\/\/github.com\/espressif\/esp-idf\/issues\/447\n","repos":"dantonets\/Pingzee-ESP32,shukyisme\/esp-idf-kwik,dantonets\/Pingzee-ESP32,tidyjiang8\/esp-idf-zh,armada-ai\/esp-idf,www220\/esp-idf,empoweredhomes\/esp-idf,empoweredhomes\/esp-idf,tidyjiang8\/esp-idf-zh,Hermiedapwdrman\/esp-idf,MIhanguangyi\/esp-idf,shukyisme\/esp-idf-kwik,tidyjiang8\/esp-idf-zh,mashaoze\/esp-idf,dschaefer\/esp-idf,dschaefer\/esp-idf,MIhanguangyi\/esp-idf,MIhanguangyi\/esp-idf,jaracil\/esp-idf,espressif\/esp-idf,shukyisme\/esp-idf-kwik,espressif\/esp-idf,MIhanguangyi\/esp-idf,tidyjiang8\/esp-idf-zh,nineisk\/esp-idf,www220\/esp-idf,Hermiedapwdrman\/esp-idf,jaracil\/esp-idf,armada-ai\/esp-idf,armada-ai\/esp-idf,ajs124\/esp-idf,empoweredhomes\/esp-idf,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,jaracil\/esp-idf,wmpluto\/esp-idf,hwmaier\/esp-idf,nineisk\/esp-idf,mashaoze\/esp-idf,Hermiedapwdrman\/esp-idf,ajs124\/esp-idf,ajs124\/esp-idf,hwmaier\/esp-idf,armada-ai\/esp-idf,empoweredhomes\/esp-idf,shukyisme\/esp-idf-kwik,dantonets\/Pingzee-ESP32,ajs124\/esp-idf,nineisk\/esp-idf,espressif\/esp-idf,jaracil\/esp-idf,wmpluto\/esp-idf,hwmaier\/esp-idf,espressif\/esp-idf,www220\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,dschaefer\/esp-idf,empoweredhomes\/esp-idf,tidyjiang8\/esp-idf-zh,MIhanguangyi\/esp-idf,Hermiedapwdrman\/esp-idf,wmpluto\/esp-idf,dschaefer\/esp-idf,www220\/esp-idf,Hermiedapwdrman\/esp-idf,nineisk\/esp-idf,dantonets\/Pingzee-ESP32,wmpluto\/esp-idf,hwmaier\/esp-idf,dschaefer\/esp-idf,mashaoze\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *librtc_clk.a:(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libcore.a:ets_timer.o(.literal .text .literal.* .text.*)\n    *libnet80211.a:ieee80211_misc.o(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libcoexist.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *librtc_clk.a:(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libcore.a:ets_timer.o(.literal .text .literal.* .text.*)\n    *libnet80211.a:ieee80211_misc.o(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libcoexist.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8784887dd5912a3368885fd12fed1213940cb727","subject":"Got it working. End of stack was too big","message":"Got it working. End of stack was too big\n","repos":"timbrom\/lightshow,timbrom\/lightshow,timbrom\/lightshow","old_file":"lightshow.ld","new_file":"lightshow.ld","new_contents":"\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n_estack = 0x20010000;\n\nMEMORY\n{\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 192K\n    rom (rx)    : ORIGIN = 0x08000000, LENGTH = 1024K\n}\n\nSECTIONS\n{\n    . = 0x0;\n\n    .text :\n    {\n        *(.isr_vector)\n        *(.text)\n    } >rom\n\n    .rodata :\n    {\n        . = ALIGN(4);\n        *(.rodata)\n        . = ALIGN(4);\n    } >rom\n\n    . = 0x20000000;\n    _sidata = LOADADDR(.data);\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.data)\n        . = ALIGN(4);\n        _edata = .;\n    } >ram AT > rom\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        __bss_start__ = .;\n        *(.bss)\n        . = ALIGN(4);\n        _ebss = .;\n        __bss_end__ = .;\n    } >ram\n}\n\n","old_contents":"\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n_estack = 0x20030000;\n\nMEMORY\n{\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 192K\n    rom (rx)    : ORIGIN = 0x08000000, LENGTH = 1024K\n}\n\nSECTIONS\n{\n    . = 0x0;\n\n    .text :\n    {\n        *(.isr_vector)\n        *(.text)\n    } >rom\n\n    .rodata :\n    {\n        . = ALIGN(4);\n        *(.rodata)\n        . = ALIGN(4);\n    } >rom\n\n    . = 0x20000000;\n    _sidata = LOADADDR(.data);\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.data)\n        . = ALIGN(4);\n        _edata = .;\n    } >ram AT > rom\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        __bss_start__ = .;\n        *(.bss)\n        . = ALIGN(4);\n        _ebss = .;\n        __bss_end__ = .;\n    } >ram\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a54fa4eb8ecdb923f392697b3d52f1a771a6aa68","subject":"arch: riscv: common: linker: Add itcm & dtcm sections","message":"arch: riscv: common: linker: Add itcm & dtcm sections\n\nThe current riscv linker script don't have sections for\nData & Instruction Tightly Coupled Memory.  Add itcm and\ndtcm sections to make it available.  All sections were\n8 byte align to keep compatible with rv64 SoCs.\n\nSigned-off-by: Gerson Fernando Budke <0ad1c92223f8f375c46e39c6141096f3d30896b4@gmail.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n\t_image_rodata_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end - _image_rom_start);\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n\t_image_rodata_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end - _image_rom_start);\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"71c396cab1a6d2afaafdbcc76e26b2481e7039f1","subject":"STM32WB: update GCC linker script to match with master","message":"STM32WB: update GCC linker script to match with master\n","repos":"mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed","old_file":"targets\/TARGET_STM\/TARGET_STM32WB\/TARGET_STM32WB55xG\/device\/TOOLCHAIN_GCC_ARM\/stm32wb55xx.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32WB\/TARGET_STM32WB55xG\/device\/TOOLCHAIN_GCC_ARM\/stm32wb55xx.ld","new_contents":"#if !defined(MBED_APP_START)\n#define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n#define MBED_APP_SIZE 512K\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\n\/* Linker script to configure memory regions. *\/\n\/* Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM1 (192K) *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  RAM1 (rwx)  : ORIGIN = 0x2000013C, LENGTH = 192K - 0x13C\n  RAM2a (rw)  : ORIGIN = 0x20030000, LENGTH = 10K\n  RAM2b (rw)  : ORIGIN = 0x20038000, LENGTH = 20K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM1\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM1\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . = ORIGIN(RAM1) + LENGTH(RAM1) - STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM1\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM1\n\n    .ble_stby_mem (NOLOAD) :\n    {\n      *(MAPPING_TABLE);\n      *(MB_MEM1);\n    } >RAM2a\n\n    .ble_shared_no_ret (NOLOAD) :\n    {\n      *(MB_MEM2);\n    } >RAM2b\n\n    \/* Set stack top to end of RAM1, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM1) + LENGTH(RAM1);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM1 limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM1 overflowed with stack\")\n}\n","old_contents":"#if !defined(MBED_APP_START)\n#define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n#define MBED_APP_SIZE 512K\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\n\/* Linker script to configure memory regions. *\/\n\/* Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM1 (192K) *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  RAM1 (rwx)  : ORIGIN = 0x2000013C, LENGTH = 192K - 0x13C\n  RAM2a (rw)  : ORIGIN = 0x20030000, LENGTH = 10K\n  RAM2b (rw)  : ORIGIN = 0x20038000, LENGTH = 20K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM1\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM1\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM1\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM1\n\n    .ble_stby_mem (NOLOAD) :\n    {\n      *(MAPPING_TABLE);\n      *(MB_MEM1);\n    } >RAM2a\n\n    .ble_shared_no_ret (NOLOAD) :\n    {\n      *(MB_MEM2);\n    } >RAM2b\n\n    \/* Set stack top to end of RAM1, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM1) + LENGTH(RAM1);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM1 limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM1 overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6242bb8f0ccded8e0814c3c6c7a4e23bfa2846d7","subject":"feat(esp8266): Link script add dram0.* attribute","message":"feat(esp8266): Link script add dram0.* attribute\n","repos":"espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK","old_file":"components\/esp8266\/ld\/esp8266.common.ld","new_file":"components\/esp8266\/ld\/esp8266.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\n#include \"sdkconfig.h\"\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  \/* RTC memory holds user's data\/rodata *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    LONG(_text_start)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.iram1 .iram1.*)\n    *libspi_flash.a:spi_flash_raw.o(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n#ifdef CONFIG_LWIP_GLOBAL_DATA_LINK_IRAM\n    *liblwip.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_TCPIP_ADAPTER_GLOBAL_DATA_LINK_IRAM\n    *libtcpip_adapter.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_ESP8266_CORE_GLOBAL_DATA_LINK_IRAM\n    *libcore.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_FREERTOS_GLOBAL_DATA_LINK_IRAM\n    *libfreertos.a:tasks.o(.bss .data .bss.* .data.* COMMON)\n    *libfreertos.a:timers.o(.bss .data .bss.* .data.* COMMON)\n    *libfreertos.a:freertos_hooks.o(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_LINK_ETS_PRINTF_TO_IRAM\n    *libesp8266.a:ets_printf.o(.literal .text .literal.* .text.* .rodata.* .rodata)\n#endif\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.dram0. .dram0.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *libpp.a:(.rodata.* .rodata)\n    *liblog.a:(.rodata.* .rodata)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.user.data)\n    *(.rodata.* .rodata .irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n    *(.rodata2.* .rodata2 .literal2.* .literal2 .text2.* .text2)\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n}\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\n#include \"sdkconfig.h\"\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  \/* RTC memory holds user's data\/rodata *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    LONG(_text_start)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.iram1 .iram1.*)\n    *libspi_flash.a:spi_flash_raw.o(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n#ifdef CONFIG_LWIP_GLOBAL_DATA_LINK_IRAM\n    *liblwip.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_TCPIP_ADAPTER_GLOBAL_DATA_LINK_IRAM\n    *libtcpip_adapter.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_ESP8266_CORE_GLOBAL_DATA_LINK_IRAM\n    *libcore.a:(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_FREERTOS_GLOBAL_DATA_LINK_IRAM\n    *libfreertos.a:tasks.o(.bss .data .bss.* .data.* COMMON)\n    *libfreertos.a:timers.o(.bss .data .bss.* .data.* COMMON)\n    *libfreertos.a:freertos_hooks.o(.bss .data .bss.* .data.* COMMON)\n#endif\n\n#ifdef CONFIG_LINK_ETS_PRINTF_TO_IRAM\n    *libesp8266.a:ets_printf.o(.literal .text .literal.* .text.* .rodata.* .rodata)\n#endif\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.dram0)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *libpp.a:(.rodata.* .rodata)\n    *liblog.a:(.rodata.* .rodata)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.user.data)\n    *(.rodata.* .rodata .irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n    *(.rodata2.* .rodata2 .literal2.* .literal2 .text2.* .text2)\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"165868c46cd990078d4f92eb304af1325741dcb4","subject":"[bsp] insert keep section .rti_fn* in GCC link file","message":"[bsp] insert keep section .rti_fn* in GCC link file\n","repos":"wolfgangz2013\/rt-thread,FlyLu\/rt-thread,yongli3\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,AubrCool\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread,wolfgangz2013\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,igou\/rt-thread,igou\/rt-thread,weety\/rt-thread,AubrCool\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,wolfgangz2013\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,yongli3\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,zhaojuntao\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,igou\/rt-thread,yongli3\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,yongli3\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,zhaojuntao\/rt-thread,AubrCool\/rt-thread,zhaojuntao\/rt-thread,weiyuliang\/rt-thread,AubrCool\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,yongli3\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread","old_file":"bsp\/frdm-k64f\/K64FN1M0xxx12.ld","new_file":"bsp\/frdm-k64f\/K64FN1M0xxx12.ld","new_contents":"\/*\n * K64F ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  FLASH (rx)            : ORIGIN = 0x00000410, LENGTH = 0x00100000 - 0x00000410\n  RAM (rwx)             : ORIGIN = 0x1FFF0198, LENGTH = 0x00040000 - 0x00000198\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        *(.text.Reset_Handler)\n        *(.text.System_Init)\n         . = ALIGN(4);\n    } > VECTORS\n\n    .flash_protect :\n    {\n        KEEP(*(.kinetis_flash_config_field))\n         . = ALIGN(4);\n    } > FLASH_PROTECTION\n\n    .text :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        _etext = .;\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n    __bss_start = .;\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    __bss_end = .;\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","old_contents":"\/*\n * K64F ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  FLASH (rx)            : ORIGIN = 0x00000410, LENGTH = 0x00100000 - 0x00000410\n  RAM (rwx)             : ORIGIN = 0x1FFF0198, LENGTH = 0x00040000 - 0x00000198\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        *(.text.Reset_Handler)\n        *(.text.System_Init)\n         . = ALIGN(4);\n    } > VECTORS\n\n    .flash_protect :\n    {\n        KEEP(*(.kinetis_flash_config_field))\n         . = ALIGN(4);\n    } > FLASH_PROTECTION\n\n    .text :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        _etext = .;\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n    __bss_start = .;\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    __bss_end = .;\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"872d60fae32e19f449f587eedae43cdda9f8bbc8","subject":"Add IPV4 in NUC472 target","message":"Add IPV4 in NUC472 target\n","repos":"betzw\/mbed-os,HeadsUpDisplayInc\/mbed,andreaslarssonublox\/mbed,NXPmicro\/mbed,c1728p9\/mbed-os,svastm\/mbed,c1728p9\/mbed-os,jeremybrodt\/mbed,screamerbg\/mbed,fahhem\/mbed-os,theotherjimmy\/mbed,monkiineko\/mbed-os,andreaslarssonublox\/mbed,ryankurte\/mbed-os,j-greffe\/mbed-os,adamgreen\/mbed,screamerbg\/mbed,Archcady\/mbed-os,mazimkhan\/mbed-os,cvtsi2sd\/mbed-os,bcostm\/mbed-os,jeremybrodt\/mbed,mmorenobarm\/mbed-os,fanghuaqi\/mbed,adamgreen\/mbed,geky\/mbed,tung7970\/mbed-os,svogl\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,monkiineko\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,mmorenobarm\/mbed-os,adustm\/mbed,NXPmicro\/mbed,j-greffe\/mbed-os,nvlsianpu\/mbed,NXPmicro\/mbed,bcostm\/mbed-os,jeremybrodt\/mbed,mbedmicro\/mbed,catiedev\/mbed-os,adustm\/mbed,ryankurte\/mbed-os,netzimme\/mbed-os,jeremybrodt\/mbed,nvlsianpu\/mbed,karsev\/mbed-os,infinnovation\/mbed-os,geky\/mbed,catiedev\/mbed-os,mikaleppanen\/mbed-os,arostm\/mbed-os,karsev\/mbed-os,RonEld\/mbed,RonEld\/mbed,cvtsi2sd\/mbed-os,geky\/mbed,svogl\/mbed-os,adamgreen\/mbed,nRFMesh\/mbed-os,fvincenzo\/mbed-os,fvincenzo\/mbed-os,YarivCol\/mbed-os,svogl\/mbed-os,catiedev\/mbed-os,nvlsianpu\/mbed,tung7970\/mbed-os-1,CalSol\/mbed,mikaleppanen\/mbed-os,bcostm\/mbed-os,Archcady\/mbed-os,YarivCol\/mbed-os,pradeep-gr\/mbed-os5-onsemi,fahhem\/mbed-os,YarivCol\/mbed-os,kl-cruz\/mbed-os,pradeep-gr\/mbed-os5-onsemi,CalSol\/mbed,HeadsUpDisplayInc\/mbed,adustm\/mbed,betzw\/mbed-os,theotherjimmy\/mbed,karsev\/mbed-os,betzw\/mbed-os,catiedev\/mbed-os,andcor02\/mbed-os,tung7970\/mbed-os-1,karsev\/mbed-os,kl-cruz\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,andcor02\/mbed-os,RonEld\/mbed,pradeep-gr\/mbed-os5-onsemi,kjbracey-arm\/mbed,cvtsi2sd\/mbed-os,infinnovation\/mbed-os,ryankurte\/mbed-os,theotherjimmy\/mbed,maximmbed\/mbed,arostm\/mbed-os,ryankurte\/mbed-os,kl-cruz\/mbed-os,infinnovation\/mbed-os,maximmbed\/mbed,mmorenobarm\/mbed-os,arostm\/mbed-os,j-greffe\/mbed-os,nvlsianpu\/mbed,betzw\/mbed-os,bulislaw\/mbed-os,nvlsianpu\/mbed,betzw\/mbed-os,c1728p9\/mbed-os,bulislaw\/mbed-os,theotherjimmy\/mbed,NXPmicro\/mbed,ryankurte\/mbed-os,mbedmicro\/mbed,adustm\/mbed,adustm\/mbed,fahhem\/mbed-os,infinnovation\/mbed-os,adustm\/mbed,andcor02\/mbed-os,screamerbg\/mbed,maximmbed\/mbed,Archcady\/mbed-os,netzimme\/mbed-os,maximmbed\/mbed,j-greffe\/mbed-os,svogl\/mbed-os,fvincenzo\/mbed-os,netzimme\/mbed-os,YarivCol\/mbed-os,fanghuaqi\/mbed,mikaleppanen\/mbed-os,HeadsUpDisplayInc\/mbed,karsev\/mbed-os,mazimkhan\/mbed-os,j-greffe\/mbed-os,j-greffe\/mbed-os,mbedmicro\/mbed,mmorenobarm\/mbed-os,andcor02\/mbed-os,bulislaw\/mbed-os,tung7970\/mbed-os-1,tung7970\/mbed-os,mikaleppanen\/mbed-os,nRFMesh\/mbed-os,fanghuaqi\/mbed,monkiineko\/mbed-os,pradeep-gr\/mbed-os5-onsemi,fahhem\/mbed-os,CalSol\/mbed,tung7970\/mbed-os,kjbracey-arm\/mbed,andcor02\/mbed-os,ryankurte\/mbed-os,c1728p9\/mbed-os,YarivCol\/mbed-os,andreaslarssonublox\/mbed,tung7970\/mbed-os-1,monkiineko\/mbed-os,CalSol\/mbed,pradeep-gr\/mbed-os5-onsemi,kjbracey-arm\/mbed,fahhem\/mbed-os,netzimme\/mbed-os,nRFMesh\/mbed-os,adamgreen\/mbed,maximmbed\/mbed,cvtsi2sd\/mbed-os,svastm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,theotherjimmy\/mbed,nvlsianpu\/mbed,bulislaw\/mbed-os,NXPmicro\/mbed,screamerbg\/mbed,adamgreen\/mbed,nRFMesh\/mbed-os,HeadsUpDisplayInc\/mbed,andreaslarssonublox\/mbed,adamgreen\/mbed,bcostm\/mbed-os,theotherjimmy\/mbed,arostm\/mbed-os,mazimkhan\/mbed-os,infinnovation\/mbed-os,netzimme\/mbed-os,Archcady\/mbed-os,infinnovation\/mbed-os,RonEld\/mbed,cvtsi2sd\/mbed-os,screamerbg\/mbed,fahhem\/mbed-os,mazimkhan\/mbed-os,mmorenobarm\/mbed-os,maximmbed\/mbed,andcor02\/mbed-os,kl-cruz\/mbed-os,geky\/mbed,catiedev\/mbed-os,CalSol\/mbed,tung7970\/mbed-os,cvtsi2sd\/mbed-os,pradeep-gr\/mbed-os5-onsemi,monkiineko\/mbed-os,NXPmicro\/mbed,mikaleppanen\/mbed-os,arostm\/mbed-os,RonEld\/mbed,bulislaw\/mbed-os,CalSol\/mbed,andreaslarssonublox\/mbed,mbedmicro\/mbed,nRFMesh\/mbed-os,svastm\/mbed,YarivCol\/mbed-os,svogl\/mbed-os,screamerbg\/mbed,kjbracey-arm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,svastm\/mbed,fvincenzo\/mbed-os,jeremybrodt\/mbed,mikaleppanen\/mbed-os,c1728p9\/mbed-os,karsev\/mbed-os,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,Archcady\/mbed-os,fvincenzo\/mbed-os,catiedev\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,svogl\/mbed-os,netzimme\/mbed-os,kl-cruz\/mbed-os,mazimkhan\/mbed-os,nRFMesh\/mbed-os,Archcady\/mbed-os,betzw\/mbed-os,mmorenobarm\/mbed-os,bcostm\/mbed-os,geky\/mbed,RonEld\/mbed,mazimkhan\/mbed-os,tung7970\/mbed-os,tung7970\/mbed-os-1,monkiineko\/mbed-os,bulislaw\/mbed-os,fanghuaqi\/mbed,bcostm\/mbed-os,svastm\/mbed,kl-cruz\/mbed-os,arostm\/mbed-os,fanghuaqi\/mbed","old_file":"hal\/targets\/cmsis\/TARGET_NUVOTON\/TARGET_NUC472\/TARGET_NUMAKER_PFM_NUC472\/TOOLCHAIN_GCC_ARM\/NUC472.ld","new_file":"hal\/targets\/cmsis\/TARGET_NUVOTON\/TARGET_NUC472\/TARGET_NUMAKER_PFM_NUC472\/TOOLCHAIN_GCC_ARM\/NUC472.ld","new_contents":"\/*\n * Nuvoton NUC472 GCC linker script file\n *\/\n\nStackSize = 0x3000;\n\nMEMORY\n{\n    \n  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400\n  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000\n  RAM_EXTERN (rwx)      : ORIGIN = 0x60000000, LENGTH = 0x00100000\n}\n\n\/**\n * Must match cmsis_nvic.h\n *\/\n__vector_size = 4 * (16 + 142);\n \n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        \/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. *\/\n        . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));\n        __uvisor_bss_end = .;\n    } > RAM_INTERN\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += StackSize - (. - __StackLimit);\n    } > RAM_INTERN\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Relocate vector table in SRAM *\/\n    .isr_vector.reloc (NOLOAD) :\n    {\n        . = ALIGN(1 << LOG2CEIL(__vector_size));\n        PROVIDE(__start_vector_table__ = .);\n        . += __vector_size;\n        PROVIDE(__end_vector_table__ = .);\n    } > RAM_INTERN\n    \n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM_INTERN AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assertions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM_INTERN\n\n    .bss.extern (NOLOAD):\n    {\n        __bss_extern_start__ = .;\n        \/**\n         * Place large .bss* sections into external SRAM if internal SRAM is insufficient.\n         * Such memory arrangement requires initializing .bss.extern section to zero in startup file. Check startup fiile in cmsis-core-* for support or not.\n         *\/\n        *lwip_*.o(.bss*)\n        *lwip_*.o(COMMON)\n       __bss_extern_end__ = .;\n    } > RAM_EXTERN\n    \n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM_INTERN\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM_EXTERN) + LENGTH(RAM_EXTERN) - .);\n        __HeapLimit = .;\n    } > RAM_EXTERN\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* Provide physical memory boundaries for uVisor. *\/\n    __uvisor_flash_start = ORIGIN(VECTORS);\n    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n    __uvisor_sram_start = ORIGIN(RAM_INTERN);\n    __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);\n}\n","old_contents":"\/*\n * Nuvoton NUC472 GCC linker script file\n *\/\n\nStackSize = 0x3000;\n\nMEMORY\n{\n    \n  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400\n  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000\n  RAM_EXTERN (rwx)      : ORIGIN = 0x60000000, LENGTH = 0x00100000\n}\n\n\/**\n * Must match cmsis_nvic.h\n *\/\n__vector_size = 4 * (16 + 142);\n \n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    \/* ensure that uvisor bss is at the beginning of memory *\/\n    .uvisor.bss (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uvisor_bss_start = .;\n\n        \/* protected uvisor main bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_main_start = .;\n        KEEP(*(.keep.uvisor.bss.main))\n        . = ALIGN(32);\n        __uvisor_bss_main_end = .;\n\n        \/* protected uvisor secure boxes bss *\/\n        . = ALIGN(32);\n        __uvisor_bss_boxes_start = .;\n        KEEP(*(.keep.uvisor.bss.boxes))\n        . = ALIGN(32);\n        __uvisor_bss_boxes_end = .;\n\n        \/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. *\/\n        . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));\n        __uvisor_bss_end = .;\n    } > RAM_INTERN\n\n    .text :\n    {\n        \/* uVisor code and data *\/\n        . = ALIGN(4);\n        __uvisor_main_start = .;\n        *(.uvisor.main)\n        __uvisor_main_end = .;\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += StackSize - (. - __StackLimit);\n    } > RAM_INTERN\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Relocate vector table in SRAM *\/\n    .isr_vector.reloc (NOLOAD) :\n    {\n        . = ALIGN(1 << LOG2CEIL(__vector_size));\n        PROVIDE(__start_vector_table__ = .);\n        . += __vector_size;\n        PROVIDE(__end_vector_table__ = .);\n    } > RAM_INTERN\n    \n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM_INTERN AT>FLASH\n\n    \/* uvisor configuration data *\/\n    .uvisor.secure :\n    {\n        . = ALIGN(32);\n        __uvisor_secure_start = .;\n\n        \/* uvisor secure boxes configuration tables *\/\n        . = ALIGN(32);\n        __uvisor_cfgtbl_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl))\n        . = ALIGN(32);\n        __uvisor_cfgtbl_end = .;\n\n        \/* pointers to uvisor secure boxes configuration tables *\/\n        \/* note: no further alignment here, we need to have the exact list of pointers *\/\n        __uvisor_cfgtbl_ptr_start = .;\n        KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n        KEEP(*(.keep.uvisor.cfgtbl_ptr))\n        __uvisor_cfgtbl_ptr_end = .;\n\n        \/* the following symbols are kept for backward compatibility and will be soon\n         * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)\n         * will need to use uVisor 0.8.x or above, or the security assertions will halt the\n         * system *\/\n        \/************************\/\n        __uvisor_data_src = .;\n        __uvisor_data_start = .;\n        __uvisor_data_end = .;\n        \/************************\/\n\n        . = ALIGN(32);\n        __uvisor_secure_end = .;\n    } >FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM_INTERN\n\n    .bss.extern (NOLOAD):\n    {\n        __bss_extern_start__ = .;\n        \/**\n         * Place large .bss* sections into external SRAM if internal SRAM is insufficient.\n         * Such memory arrangement requires initializing .bss.extern section to zero in startup file. Check startup fiile in cmsis-core-* for support or not.\n         *\/\n        *lwip_*.o(.bss*)\n        *lwip_*.o(COMMON)\n        __bss_extern_end__ = .;\n    } > RAM_EXTERN\n    \n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM_INTERN\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM_EXTERN) + LENGTH(RAM_EXTERN) - .);\n        __HeapLimit = .;\n    } > RAM_EXTERN\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n    \/* Provide physical memory boundaries for uVisor. *\/\n    __uvisor_flash_start = ORIGIN(VECTORS);\n    __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n    __uvisor_sram_start = ORIGIN(RAM_INTERN);\n    __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f7005105e94f5ba03de5b9794fce1dc8f8d9b247","subject":"xtensa: esp32: place .rodata into DRAM","message":"xtensa: esp32: place .rodata into DRAM\n\nUntil ESP32\u2019s flash cache is utilized, .rodata must be stored in RAM.\n\nSigned-off-by: Leandro Pereira <51c7437a02b34df685e6b4ecb2e9bca23efe2e1a@intel.com>\n","repos":"punitvara\/zephyr,punitvara\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,fractalclone\/zephyr-riscv,ldts\/zephyr,rsalveti\/zephyr,kraj\/zephyr,GiulianoFranchetto\/zephyr,rsalveti\/zephyr,fbsder\/zephyr,fractalclone\/zephyr-riscv,aceofall\/zephyr-iotos,finikorg\/zephyr,holtmann\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,finikorg\/zephyr,kraj\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,holtmann\/zephyr,runchip\/zephyr-cc3220,runchip\/zephyr-cc3220,explora26\/zephyr,kraj\/zephyr,fractalclone\/zephyr-riscv,fbsder\/zephyr,zephyriot\/zephyr,GiulianoFranchetto\/zephyr,rsalveti\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,runchip\/zephyr-cc3220,aceofall\/zephyr-iotos,ldts\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,kraj\/zephyr,explora26\/zephyr,zephyriot\/zephyr,fractalclone\/zephyr-riscv,holtmann\/zephyr,galak\/zephyr,mbolivar\/zephyr,fbsder\/zephyr,ldts\/zephyr,punitvara\/zephyr,explora26\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,zephyriot\/zephyr,rsalveti\/zephyr,zephyriot\/zephyr,mbolivar\/zephyr,Vudentz\/zephyr,kraj\/zephyr,rsalveti\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,explora26\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,aceofall\/zephyr-iotos,zephyriot\/zephyr,holtmann\/zephyr,aceofall\/zephyr-iotos,fbsder\/zephyr,Vudentz\/zephyr,holtmann\/zephyr,runchip\/zephyr-cc3220,ldts\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,aceofall\/zephyr-iotos,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,mbolivar\/zephyr,punitvara\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3220,fractalclone\/zephyr-riscv,nashif\/zephyr,nashif\/zephyr,mbolivar\/zephyr","old_file":"arch\/xtensa\/soc\/esp32\/linker.ld","new_file":"arch\/xtensa\/soc\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define ROMABLE_REGION iram0_0_seg :iram0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\nPROVIDE ( uart_tx_one_char = 0x40009200 );\nPROVIDE ( uart_rx_one_char = 0x400092d0 );\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  iram0_2_seg(RX): org = 0x400D0018, len = 0x330000\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x50000\n  drom0_0_seg(R): org = 0x3F400010, len = 0x800000\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n}\n\nPHDRS\n{\n  iram0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n#include <linker\/common-rom.ld>\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(4))\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define ROMABLE_REGION iram0_0_seg :iram0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\nPROVIDE ( uart_tx_one_char = 0x40009200 );\nPROVIDE ( uart_rx_one_char = 0x400092d0 );\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  iram0_2_seg(RX): org = 0x400D0018, len = 0x330000\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x50000\n  drom0_0_seg(R): org = 0x3F400010, len = 0x800000\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n}\n\nPHDRS\n{\n  iram0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n#include <linker\/common-rom.ld>\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(4))\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f89b852c1d8aa8f43646a87df9fb5c940719369a","subject":"cpu\/lpc2387: clean up lpc2387.ld","message":"cpu\/lpc2387: clean up lpc2387.ld\n\nClean up the linkerfile and bring it more in line with cortexm_base.ld\n(so far only for the ROM part)\n\nAs a bonus, tests\/cpp_ctors works now.\n","repos":"kYc0o\/RIOT,mtausig\/RIOT,mtausig\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,yogo1212\/RIOT,jasonatran\/RIOT,toonst\/RIOT,smlng\/RIOT,RIOT-OS\/RIOT,x3ro\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,josephnoir\/RIOT,OTAkeys\/RIOT,aeneby\/RIOT,authmillenon\/RIOT,mtausig\/RIOT,kYc0o\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,miri64\/RIOT,miri64\/RIOT,aeneby\/RIOT,toonst\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,x3ro\/RIOT,yogo1212\/RIOT,x3ro\/RIOT,aeneby\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,aeneby\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,smlng\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,toonst\/RIOT,OlegHahm\/RIOT,aeneby\/RIOT,toonst\/RIOT,basilfx\/RIOT,kYc0o\/RIOT,smlng\/RIOT,basilfx\/RIOT,toonst\/RIOT,OTAkeys\/RIOT,josephnoir\/RIOT,miri64\/RIOT,mtausig\/RIOT,josephnoir\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,mtausig\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,smlng\/RIOT,x3ro\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,ant9000\/RIOT,authmillenon\/RIOT,basilfx\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,josephnoir\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,josephnoir\/RIOT,OTAkeys\/RIOT,smlng\/RIOT","old_file":"cpu\/lpc2387\/ldscripts\/lpc2387.ld","new_file":"cpu\/lpc2387\/ldscripts\/lpc2387.ld","new_contents":"\/*\n * Copyright 2013, Freie Universitaet Berlin (FUB). All rights reserved.\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/* specify the LPC2387 memory areas (see LPC2387 datasheet page 15)  *\/\nMEMORY\n{\n    rom (rx)            : ORIGIN = 0,          LENGTH = 504K    \/* FLASH ROM 512kByte without ISP bootloader*\/\n    infomem             : ORIGIN = 0x0007D000, LENGTH = 4K      \/* Last sector in FLASH ROM for config data *\/\n    ram_battery         : ORIGIN = 0xE0084000, LENGTH = 2K      \/* Battery RAM                              *\/\n    ram (w!rx)          : ORIGIN = 0x40000000, LENGTH = 64K     \/* LOCAL ON-CHIP STATIC RAM                 *\/\n    ram_usb             : ORIGIN = 0x7FD00000, LENGTH = 16K     \/* USB RAM  !!! first 1024 bytes are occupied from GPDMA for MCI *\/\n    ram_ethernet        : ORIGIN = 0x7FE00000, LENGTH = 16K     \/* ethernet RAM                             *\/\n}\n\n__stack_und_size = 4;           \/* stack for \"undefined instruction\" interrupts             *\/\n__stack_abt_size = 4;           \/* stack for \"abort\" interrupts                             *\/\n__stack_fiq_size = 64;          \/* stack for \"FIQ\" interrupts                               *\/\n__stack_irq_size = 400;         \/* stack for \"IRQ\" normal interrupts                        *\/\n__stack_svc_size = 400;         \/* stack for \"SVC\" supervisor mode                          *\/\n__stack_usr_size = 4096;        \/* stack for user operation (kernel init)                   *\/\n__stack_size = __stack_und_size + __stack_abt_size + __stack_fiq_size + __stack_irq_size + __stack_svc_size + __stack_usr_size;\n\n\/* now define the output sections  *\/\nSECTIONS\n{\n    .text :                             \/* collect all sections that should go into FLASH after startup  *\/\n    {\n        KEEP(*(.vectors))               \/* Exception Vectors and branch table >= 64 bytes *\/\n        . = ALIGN(64);\n        KEEP(*(.init))\n        KEEP(*(.init0))                 \/* Start here after reset.  *\/\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .config :\n    {\n        *(.configmem)\n        . = ALIGN(256);\n    } >infomem\n\n    \/**************************************************************************\n     * RAM\n     **************************************************************************\/\n\n    \/*\n     * collect all zero initialized sections that go into RAM\n     *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);                   \/* ensure data is aligned so relocation can use 4-byte operations *\/\n        __bss_start = .;                \/* define a global symbol marking the start of the .bss section *\/\n        *(.bss*)                        \/* all .bss sections  *\/\n        *(COMMON)\n    } > ram                             \/* put all the above in RAM (it will be cleared in the startup code *\/\n    . = ALIGN(4);                       \/* ensure data is aligned so relocation can use 4-byte operations *\/\n    __bss_end = . ;                     \/* define a global symbol marking the end of the .bss section *\/\n\n    \/*\n     * collect all initialized .data sections that go into RAM\n     * initial values get placed at the end of .text in flash\n     *\/\n    .data :\n    {\n        . = ALIGN(4);                   \/* ensure data is aligned so relocation can use 4-byte operations *\/\n        _data = .;                      \/* create a global symbol marking the start of the .data section  *\/\n        *(.data .data.*)                \/* all .data sections  *\/\n        *(.gnu.linkonce.d*)\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n            PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n            KEEP(*(.init_array))\n            PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n            KEEP(*(.fini_array))\n            PROVIDE_HIDDEN (__fini_array_end = .);\n    } >ram AT > rom                     \/* put all the above into RAM (but load the LMA copy into FLASH) *\/\n    . = ALIGN(4);                       \/* ensure data is aligned so relocation can use 4-byte operations *\/\n    _edata = .;                         \/* define a global symbol marking the end of the .data section  *\/\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        PROVIDE(__fiq_handler = .);\n        *(.fiq)\n        *(.noinit)\n    }  > ram\n    . = ALIGN(4);\n    __noinit_end = .;\n\n    _end = .;                           \/* define a global symbol marking the end of application RAM *\/\n\n    __heap1_size = ORIGIN(ram) + LENGTH(ram) - . - __stack_size;\n    .heap1 (NOLOAD) :\n    {\n        PROVIDE(_sheap = .);\n        . = . + __heap1_size;\n        PROVIDE(_eheap = .);\n    } > ram\n\n    \/*\n     * Stacks\n     *\/\n    .stack (NOLOAD) :\n    {\n        PROVIDE(__stack_start = .);\n\n        . = . + __stack_usr_size;\n        __stack_usr_start = .;\n        . = . + __stack_und_size;\n        __stack_und_start = .;\n        . = . + __stack_fiq_size;\n        __stack_fiq_start = .;\n        . = . + __stack_irq_size;\n        __stack_irq_start = .;\n        . = . + __stack_abt_size;\n        __stack_abt_start = .;\n        . = . + __stack_svc_size;\n        __stack_svc_start = .;\n\n        PROVIDE(__stack_end = .);\n    } > ram\n\n    __heap2_size = LENGTH(ram_ethernet);\n    .heap2 (NOLOAD) :\n    {\n        PROVIDE(__heap2_start = . );\n        . = . + __heap2_size;\n        PROVIDE(__heap2_max = .);       \/* _heap shall always be < _heap_max *\/\n    } > ram_ethernet\n\n    . = ORIGIN(ram_usb);\n    .usbdata (NOLOAD) :                 \/* USB RAM section, may be used otherwise if USB is disabled *\/\n    {\n        *(.usbdata)\n    } > ram_usb\n\n    .heap3 ALIGN(0x1000) (NOLOAD) :\n    {\n        __heap3_size = ORIGIN(ram_usb) + LENGTH(ram_usb) - ABSOLUTE(.);\n        PROVIDE(__heap3_start = . );\n        . += __heap3_size;\n        PROVIDE(__heap3_max = .);\n    } > ram_usb\n    __heap_size = SIZEOF(.heap3);\n\n    .backup.bss (NOLOAD) : ALIGN(4) {\n        _sbackup_bss = .;\n        *(.backup.bss)\n        _ebackup_bss = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > ram_battery\n\n    _sbackup_data_load = LOADADDR(.backup.data);\n    .backup.data : ALIGN(4) {\n        _sbackup_data = .;\n        *(.backup.data)\n        _ebackup_data = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > ram_battery AT> rom\n}\n","old_contents":"\/*\n * Copyright 2013, Freie Universitaet Berlin (FUB). All rights reserved.\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/* specify the LPC2387 memory areas (see LPC2387 datasheet page 15)  *\/\nMEMORY\n{\n    flash (rx)          : ORIGIN = 0,          LENGTH = 504K    \/* FLASH ROM 512kByte without ISP bootloader*\/\n    infomem             : ORIGIN = 0x0007D000, LENGTH = 4K      \/* Last sector in FLASH ROM for config data *\/\n    ram_battery         : ORIGIN = 0xE0084000, LENGTH = 2K      \/* Battery RAM                              *\/\n    ram (w!rx)          : ORIGIN = 0x40000000, LENGTH = 64K     \/* LOCAL ON-CHIP STATIC RAM                 *\/\n    ram_usb             : ORIGIN = 0x7FD00000, LENGTH = 16K     \/* USB RAM  !!! first 1024 bytes are occupied from GPDMA for MCI *\/\n    ram_ethernet        : ORIGIN = 0x7FE00000, LENGTH = 16K     \/* ethernet RAM                             *\/\n}\n\n__stack_und_size = 4;           \/* stack for \"undefined instruction\" interrupts             *\/\n__stack_abt_size = 4;           \/* stack for \"abort\" interrupts                             *\/\n__stack_fiq_size = 64;          \/* stack for \"FIQ\" interrupts                               *\/\n__stack_irq_size = 400;         \/* stack for \"IRQ\" normal interrupts                        *\/\n__stack_svc_size = 400;         \/* stack for \"SVC\" supervisor mode                          *\/\n__stack_usr_size = 4096;        \/* stack for user operation (kernel init)                   *\/\n__stack_size = __stack_und_size + __stack_abt_size + __stack_fiq_size + __stack_irq_size + __stack_svc_size + __stack_usr_size;\n\n\/* now define the output sections  *\/\nSECTIONS\n{\n    .text :                             \/* collect all sections that should go into FLASH after startup  *\/\n    {\n        KEEP(*(.vectors))               \/* Exception Vectors and branch table >= 64 bytes *\/\n        . = ALIGN(64);\n        KEEP(*(.init))\n        KEEP(*(.init0))                 \/* Start here after reset.  *\/\n        KEEP(*(.init1))\n        KEEP(*(.init2))                 \/* Copy data loop  *\/\n        KEEP(*(.init3))\n        KEEP(*(.init4))                 \/* Clear bss  *\/\n        KEEP(*(.init5))\n        KEEP(*(.init6))                 \/* C++ constructors.  *\/\n        KEEP(*(.init7))\n        KEEP(*(.init8))\n        KEEP(*(.init9))                 \/* Call main().  *\/\n        *(.text)                        \/* all .text sections (code)  *\/\n        *(.text.*)\n        *(.gnu.linkonce.t.*)\n\n        . = ALIGN(4);\n        __commands_start = .;\n        KEEP(*(.commands))              \/* command table *\/\n        __commands_end = .;\n        . = ALIGN(4);\n        __cfgspec_start = .;\n        KEEP(*(.cfgspec))               \/* configuration spec table *\/\n        __cfgspec_end = .;\n        . = ALIGN(4);\n\n        __ctors_start = .;\n            PROVIDE(_os_ctor_start = .);\n            KEEP(*(.ctors));\n            KEEP(*(.init_array))\n            PROVIDE(_os_ctor_end = .);\n        __ctors_end = .;\n            KEEP(*(.dtors));\n            LONG (0);\n\n\n        *(.rodata .rodata.*)            \/* all .rodata sections (constants, strings, etc.)  *\/\n        *(.gnu.linkonce.r.*)\n        *(.glue_7)                      \/* all .glue_7 sections, see https:\/\/gcc.gnu.org\/ml\/gcc-help\/2009-03\/msg00306.html *\/\n        *(.glue_7t)                     \/* all .glue_7t sections *\/\n\n        KEEP(*(.fini9))\n        KEEP(*(.fini8))\n        KEEP(*(.fini7))\n        KEEP(*(.fini6))                     \/* C++ destructors.  *\/\n        KEEP(*(.fini5))\n        KEEP(*(.fini4))\n        KEEP(*(.fini3))\n        KEEP(*(.fini2))\n        KEEP(*(.fini1))\n        KEEP(*(.fini0))                     \/* Infinite loop after program termination.  *\/\n        KEEP(*(.fini))\n\n        *(.gcc_except_table)\n\n    } >flash                            \/* put all the above into FLASH *\/\n    . = ALIGN(4);\n\n    \/* The .extab, .exidx sections are used for C++ exception handling *\/\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > flash\n\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > flash\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    .eh_frame_hdr :\n    {\n        *(.eh_frame_hdr)\n    } > flash\n\n    .eh_frame : ONLY_IF_RO\n    {\n        KEEP (*(.eh_frame))\n    } > flash\n\n    .gcc_except_table : ONLY_IF_RO\n    {\n        *(.gcc_except_table .gcc_except_table.*)\n    } > flash\n\n\/*\n    .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } > sram_u AT > flash\n    .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } > sram_u AT > flash\n*\/\n\n    _etext = . ;                        \/* define a global symbol _etext just after the last code byte *\/\n\n    .config :\n    {\n        *(.configmem)\n        . = ALIGN(256);\n    } >infomem\n    . = ALIGN(4);\n\n    \/**************************************************************************\n     * RAM\n     **************************************************************************\/\n\n\n    .ctors (NOLOAD) :\n    {\n        . = ALIGN(4096);\n        start_ctors = .;\n        *(.init_array);\n        *(.ctors);\n        end_ctors = .;\n    } >ram\n\n    .dtors (NOLOAD) :\n    {\n        . = ALIGN(4096);\n        start_dtors = .;\n        *(.fini_array);\n        *(.dtors);\n        end_dtors = .;\n    } >ram\n\n    \/*\n     * collect all zero initialized sections that go into RAM\n     *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);                   \/* ensure data is aligned so relocation can use 4-byte operations *\/\n        __bss_start = .;                \/* define a global symbol marking the start of the .bss section *\/\n        *(.bss*)                        \/* all .bss sections  *\/\n        *(COMMON)\n    } > ram                             \/* put all the above in RAM (it will be cleared in the startup code *\/\n    . = ALIGN(4);                       \/* ensure data is aligned so relocation can use 4-byte operations *\/\n    __bss_end = . ;                     \/* define a global symbol marking the end of the .bss section *\/\n\n    \/*\n     * collect all initialized .data sections that go into RAM\n     * initial values get placed at the end of .text in flash\n     *\/\n    .data :\n    {\n        . = ALIGN(4);                   \/* ensure data is aligned so relocation can use 4-byte operations *\/\n        _data = .;                      \/* create a global symbol marking the start of the .data section  *\/\n        *(.data .data.*)                \/* all .data sections  *\/\n        *(.gnu.linkonce.d*)\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n            PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n            KEEP(*(.init_array))\n            PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n            KEEP(*(.fini_array))\n            PROVIDE_HIDDEN (__fini_array_end = .);\n    } >ram AT > flash                   \/* put all the above into RAM (but load the LMA copy into FLASH) *\/\n    . = ALIGN(4);                       \/* ensure data is aligned so relocation can use 4-byte operations *\/\n    _edata = .;                         \/* define a global symbol marking the end of the .data section  *\/\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        PROVIDE(__fiq_handler = .);\n        *(.fiq)\n        *(.noinit)\n    }  > ram\n    . = ALIGN(4);\n    __noinit_end = .;\n\n    \/*\n     * Exception frames (newer linker versions generate these but they use of\n     * most of the RAM.\n     *\/\n    \/DISCARD\/ :                         \/* discard exception frames *\/\n    {\n        *(.eh_*)\n    }\n\n    \/* to enable exception frames *\/\n    \/*\n    .eh_frame :\n    {\n         KEEP (*(.eh_frame))\n    } > ram\n    . = ALIGN(4);\n    *\/\n\n    _end = .;                           \/* define a global symbol marking the end of application RAM *\/\n\n    __heap1_size = ORIGIN(ram) + LENGTH(ram) - . - __stack_size;\n    .heap1 (NOLOAD) :\n    {\n        PROVIDE(_sheap = .);\n        . = . + __heap1_size;\n        PROVIDE(_eheap = .);\n    } > ram\n\n    \/*\n     * Stacks\n     *\/\n    .stack (NOLOAD) :\n    {\n        PROVIDE(__stack_start = .);\n\n        . = . + __stack_usr_size;\n        __stack_usr_start = .;\n        . = . + __stack_und_size;\n        __stack_und_start = .;\n        . = . + __stack_fiq_size;\n        __stack_fiq_start = .;\n        . = . + __stack_irq_size;\n        __stack_irq_start = .;\n        . = . + __stack_abt_size;\n        __stack_abt_start = .;\n        . = . + __stack_svc_size;\n        __stack_svc_start = .;\n\n        PROVIDE(__stack_end = .);\n    } > ram\n\n    __heap2_size = LENGTH(ram_ethernet);\n    .heap2 (NOLOAD) :\n    {\n        PROVIDE(__heap2_start = . );\n        . = . + __heap2_size;\n        PROVIDE(__heap2_max = .);       \/* _heap shall always be < _heap_max *\/\n    } > ram_ethernet\n\n    . = ORIGIN(ram_usb);\n    .usbdata (NOLOAD) :                 \/* USB RAM section, may be used otherwise if USB is disabled *\/\n    {\n        *(.usbdata)\n    } > ram_usb\n\n    .heap3 ALIGN(0x1000) (NOLOAD) :\n    {\n        __heap3_size = ORIGIN(ram_usb) + LENGTH(ram_usb) - ABSOLUTE(.);\n        PROVIDE(__heap3_start = . );\n        . += __heap3_size;\n        PROVIDE(__heap3_max = .);\n    } > ram_usb\n    __heap_size = SIZEOF(.heap3);\n\n    .backup.bss (NOLOAD) : ALIGN(4) {\n        _sbackup_bss = .;\n        *(.backup.bss)\n        _ebackup_bss = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > ram_battery\n\n    _sbackup_data_load = LOADADDR(.backup.data);\n    .backup.data : ALIGN(4) {\n        _sbackup_data = .;\n        *(.backup.data)\n        _ebackup_data = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > ram_battery AT> flash\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"5b11cf42eab7ad4dec58e07eee1780dc1f2fd89b","subject":"Update heap size","message":"Update heap size\n","repos":"bigclownlabs\/bc-core-module-sdk,bigclownlabs\/bc-core-module-sdk,bigclownlabs\/bc-core-module-sdk","old_file":"sys\/lkr\/stm32l083cz.ld","new_file":"sys\/lkr\/stm32l083cz.ld","new_contents":"\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20005000;    \/* end of RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x100;  \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 192K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data :\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20005000;    \/* end of RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x200;  \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 192K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data :\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"88d3cd582ededf4023039f5515e6ca8912682b24","subject":"esp8266\/eagle.rom.addr.v6.ld: Add Enable_QMode symbol from SDK 2.0.0.","message":"esp8266\/eagle.rom.addr.v6.ld: Add Enable_QMode symbol from SDK 2.0.0.\n","repos":"pramasoul\/micropython,bvernoux\/micropython,torwag\/micropython,SHA2017-badge\/micropython-esp32,turbinenreiter\/micropython,chrisdearman\/micropython,blazewicz\/micropython,PappaPeppar\/micropython,deshipu\/micropython,dmazzella\/micropython,henriknelson\/micropython,chrisdearman\/micropython,lowRISC\/micropython,HenrikSolver\/micropython,tobbad\/micropython,pozetroninc\/micropython,HenrikSolver\/micropython,alex-robbins\/micropython,ryannathans\/micropython,MrSurly\/micropython-esp32,swegener\/micropython,kerneltask\/micropython,pramasoul\/micropython,cwyark\/micropython,alex-march\/micropython,kerneltask\/micropython,SHA2017-badge\/micropython-esp32,redbear\/micropython,bvernoux\/micropython,AriZuu\/micropython,oopy\/micropython,puuu\/micropython,tralamazza\/micropython,ganshun666\/micropython,AriZuu\/micropython,tobbad\/micropython,selste\/micropython,SHA2017-badge\/micropython-esp32,selste\/micropython,PappaPeppar\/micropython,Timmenem\/micropython,MrSurly\/micropython-esp32,lowRISC\/micropython,tralamazza\/micropython,micropython\/micropython-esp32,MrSurly\/micropython,pramasoul\/micropython,adafruit\/micropython,tobbad\/micropython,tuc-osg\/micropython,henriknelson\/micropython,infinnovation\/micropython,selste\/micropython,PappaPeppar\/micropython,hosaka\/micropython,adafruit\/micropython,henriknelson\/micropython,torwag\/micropython,chrisdearman\/micropython,turbinenreiter\/micropython,trezor\/micropython,hiway\/micropython,jmarcelino\/pycom-micropython,ganshun666\/micropython,jmarcelino\/pycom-micropython,torwag\/micropython,matthewelse\/micropython,oopy\/micropython,adafruit\/circuitpython,hosaka\/micropython,jmarcelino\/pycom-micropython,pozetroninc\/micropython,turbinenreiter\/micropython,puuu\/micropython,hosaka\/micropython,cwyark\/micropython,pfalcon\/micropython,alex-march\/micropython,swegener\/micropython,blazewicz\/micropython,swegener\/micropython,TDAbboud\/micropython,toolmacher\/micropython,matthewelse\/micropython,MrSurly\/micropython,alex-march\/micropython,adafruit\/circuitpython,tuc-osg\/micropython,tobbad\/micropython,lowRISC\/micropython,TDAbboud\/micropython,micropython\/micropython-esp32,matthewelse\/micropython,AriZuu\/micropython,trezor\/micropython,chrisdearman\/micropython,blazewicz\/micropython,puuu\/micropython,pfalcon\/micropython,ryannathans\/micropython,hosaka\/micropython,alex-robbins\/micropython,dxxb\/micropython,redbear\/micropython,TDAbboud\/micropython,tobbad\/micropython,hosaka\/micropython,kerneltask\/micropython,infinnovation\/micropython,oopy\/micropython,infinnovation\/micropython,dxxb\/micropython,mhoffma\/micropython,AriZuu\/micropython,pfalcon\/micropython,Peetz0r\/micropython-esp32,bvernoux\/micropython,Timmenem\/micropython,alex-march\/micropython,MrSurly\/micropython-esp32,dxxb\/micropython,matthewelse\/micropython,adafruit\/circuitpython,cwyark\/micropython,lowRISC\/micropython,ganshun666\/micropython,pfalcon\/micropython,hiway\/micropython,dmazzella\/micropython,Timmenem\/micropython,kerneltask\/micropython,bvernoux\/micropython,selste\/micropython,redbear\/micropython,lowRISC\/micropython,ryannathans\/micropython,deshipu\/micropython,infinnovation\/micropython,MrSurly\/micropython,deshipu\/micropython,MrSurly\/micropython,PappaPeppar\/micropython,pramasoul\/micropython,micropython\/micropython-esp32,ryannathans\/micropython,adafruit\/micropython,mhoffma\/micropython,MrSurly\/micropython-esp32,blazewicz\/micropython,cwyark\/micropython,micropython\/micropython-esp32,turbinenreiter\/micropython,dmazzella\/micropython,kerneltask\/micropython,swegener\/micropython,toolmacher\/micropython,TDAbboud\/micropython,Peetz0r\/micropython-esp32,adafruit\/circuitpython,alex-robbins\/micropython,Peetz0r\/micropython-esp32,deshipu\/micropython,HenrikSolver\/micropython,toolmacher\/micropython,henriknelson\/micropython,Peetz0r\/micropython-esp32,redbear\/micropython,redbear\/micropython,adafruit\/micropython,adafruit\/circuitpython,infinnovation\/micropython,tuc-osg\/micropython,tuc-osg\/micropython,mhoffma\/micropython,trezor\/micropython,HenrikSolver\/micropython,toolmacher\/micropython,bvernoux\/micropython,pozetroninc\/micropython,MrSurly\/micropython-esp32,henriknelson\/micropython,oopy\/micropython,ganshun666\/micropython,selste\/micropython,pozetroninc\/micropython,alex-march\/micropython,tralamazza\/micropython,SHA2017-badge\/micropython-esp32,jmarcelino\/pycom-micropython,adafruit\/micropython,swegener\/micropython,ganshun666\/micropython,torwag\/micropython,HenrikSolver\/micropython,Timmenem\/micropython,Timmenem\/micropython,AriZuu\/micropython,MrSurly\/micropython,Peetz0r\/micropython-esp32,SHA2017-badge\/micropython-esp32,hiway\/micropython,toolmacher\/micropython,TDAbboud\/micropython,deshipu\/micropython,dmazzella\/micropython,trezor\/micropython,alex-robbins\/micropython,tralamazza\/micropython,turbinenreiter\/micropython,torwag\/micropython,pfalcon\/micropython,adafruit\/circuitpython,trezor\/micropython,micropython\/micropython-esp32,alex-robbins\/micropython,puuu\/micropython,cwyark\/micropython,chrisdearman\/micropython,mhoffma\/micropython,hiway\/micropython,matthewelse\/micropython,dxxb\/micropython,pozetroninc\/micropython,oopy\/micropython,tuc-osg\/micropython,matthewelse\/micropython,dxxb\/micropython,puuu\/micropython,PappaPeppar\/micropython,ryannathans\/micropython,blazewicz\/micropython,jmarcelino\/pycom-micropython,pramasoul\/micropython,mhoffma\/micropython,hiway\/micropython","old_file":"esp8266\/eagle.rom.addr.v6.ld","new_file":"esp8266\/eagle.rom.addr.v6.ld","new_contents":"PROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\n__adddf3 = 0x4000c538;\n__addsf3 = 0x4000c180;\n__divdf3 = 0x4000cb94;\n__divdi3 = 0x4000ce60;\n__divsi3 = 0x4000dc88;\n__extendsfdf2 = 0x4000cdfc;\n__fixdfsi = 0x4000ccb8;\n__fixunsdfsi = 0x4000cd00;\n__fixunssfsi = 0x4000c4c4;\n__floatsidf = 0x4000e2f0;\n__floatsisf = 0x4000e2ac;\n__floatunsidf = 0x4000e2e8;\n__floatunsisf = 0x4000e2a4;\n__muldf3 = 0x4000c8f0;\n__muldi3 = 0x40000650;\n__mulsf3 = 0x4000c3dc;\n__subdf3 = 0x4000c688;\n__subsf3 = 0x4000c268;\n__truncdfsf2 = 0x4000cd5c;\n__udivdi3 = 0x4000d310;\n__udivsi3 = 0x4000e21c;\n__umoddi3 = 0x4000d770;\n__umodsi3 = 0x4000e268;\n__umulsidi3 = 0x4000dcf0;\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( _ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( _ets_run = 0x40000e04 );\nPROVIDE ( _ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( _ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( _ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n","old_contents":"PROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\n__adddf3 = 0x4000c538;\n__addsf3 = 0x4000c180;\n__divdf3 = 0x4000cb94;\n__divdi3 = 0x4000ce60;\n__divsi3 = 0x4000dc88;\n__extendsfdf2 = 0x4000cdfc;\n__fixdfsi = 0x4000ccb8;\n__fixunsdfsi = 0x4000cd00;\n__fixunssfsi = 0x4000c4c4;\n__floatsidf = 0x4000e2f0;\n__floatsisf = 0x4000e2ac;\n__floatunsidf = 0x4000e2e8;\n__floatunsisf = 0x4000e2a4;\n__muldf3 = 0x4000c8f0;\n__muldi3 = 0x40000650;\n__mulsf3 = 0x4000c3dc;\n__subdf3 = 0x4000c688;\n__subsf3 = 0x4000c268;\n__truncdfsf2 = 0x4000cd5c;\n__udivdi3 = 0x4000d310;\n__udivsi3 = 0x4000e21c;\n__umoddi3 = 0x4000d770;\n__umodsi3 = 0x4000e268;\n__umulsidi3 = 0x4000dcf0;\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( _ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( _ets_run = 0x40000e04 );\nPROVIDE ( _ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( _ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( _ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"d800ed187756c734458d269b1bf0dbfe554ad4f1","subject":"esp8266\/esp8266_common.ld: Put mp_keyboard_interrupt in iRAM.","message":"esp8266\/esp8266_common.ld: Put mp_keyboard_interrupt in iRAM.\n\nThis function may be called from a UART IRQ, which may interrupt the system\nwhen it is erasing\/reading\/writing flash.  In such a case all code\nexecuting from the IRQ must be in iRAM (because the SPI flash is busy), so\nput mp_keyboard_interrupt in iRAM so ctrl-C can be caught during flash\naccess.\n\nThis patch also takes get_fattime out of iRAM and puts it in iROM to make\nspace for mp_keyboard_interrupt.  There's no real need to have get_fattime\nin iRAM because it calls other functions in iROM.\n\nFixes issue #3897.\n","repos":"tralamazza\/micropython,swegener\/micropython,trezor\/micropython,henriknelson\/micropython,pfalcon\/micropython,kerneltask\/micropython,bvernoux\/micropython,trezor\/micropython,bvernoux\/micropython,swegener\/micropython,adafruit\/circuitpython,tralamazza\/micropython,trezor\/micropython,adafruit\/circuitpython,pramasoul\/micropython,henriknelson\/micropython,MrSurly\/micropython,kerneltask\/micropython,bvernoux\/micropython,pfalcon\/micropython,pfalcon\/micropython,tobbad\/micropython,adafruit\/circuitpython,pozetroninc\/micropython,MrSurly\/micropython,adafruit\/circuitpython,selste\/micropython,henriknelson\/micropython,trezor\/micropython,tobbad\/micropython,tralamazza\/micropython,pozetroninc\/micropython,henriknelson\/micropython,tobbad\/micropython,pfalcon\/micropython,selste\/micropython,adafruit\/circuitpython,pfalcon\/micropython,swegener\/micropython,tobbad\/micropython,tralamazza\/micropython,swegener\/micropython,MrSurly\/micropython,selste\/micropython,bvernoux\/micropython,selste\/micropython,adafruit\/circuitpython,bvernoux\/micropython,selste\/micropython,pramasoul\/micropython,pramasoul\/micropython,pramasoul\/micropython,pozetroninc\/micropython,henriknelson\/micropython,trezor\/micropython,swegener\/micropython,pozetroninc\/micropython,MrSurly\/micropython,kerneltask\/micropython,pramasoul\/micropython,kerneltask\/micropython,kerneltask\/micropython,MrSurly\/micropython,tobbad\/micropython,pozetroninc\/micropython","old_file":"ports\/esp8266\/esp8266_common.ld","new_file":"ports\/esp8266\/esp8266_common.ld","new_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* Vendor SDK in v2.1.0-7-gb8fd588 started to build these with\n           -ffunction-sections -fdata-sections, and require routing to\n           irom via linker:\n           https:\/\/github.com\/espressif\/ESP8266_NONOS_SDK\/commit\/b8fd588a33f0319dc135523b51655e97b483b205\n         *\/\n\n        *libcrypto.a:(.literal.* .text.*)\n        *libnet80211.a:(.literal.* .text.*)\n        *libwpa.a:(.literal.* .text.*)\n        *libwpa2.a:(.literal.* .text.*)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/printf.o*(.literal*, .text*)\n        *lib\/utils\/sys_stdio_mphal.o*(.literal*, .text*)\n        *lib\/utils\/pyexec.o*(.literal*, .text*)\n        *lib\/utils\/stdout_helpers.o*(.literal*, .text*)\n        *lib\/utils\/interrupt_char.o*(.literal.mp_hal_set_interrupt_char, .text.mp_hal_set_interrupt_char)\n        *drivers\/bus\/*.o(.literal* .text*)\n\n        build\/main.o(.literal* .text*)\n        *fatfs_port.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* Vendor SDK in v2.1.0-7-gb8fd588 started to build these with\n           -ffunction-sections -fdata-sections, and require routing to\n           irom via linker:\n           https:\/\/github.com\/espressif\/ESP8266_NONOS_SDK\/commit\/b8fd588a33f0319dc135523b51655e97b483b205\n         *\/\n\n        *libcrypto.a:(.literal.* .text.*)\n        *libnet80211.a:(.literal.* .text.*)\n        *libwpa.a:(.literal.* .text.*)\n        *libwpa2.a:(.literal.* .text.*)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n        *drivers\/bus\/*.o(.literal* .text*)\n\n        build\/main.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8d52e5439f0a3e947432162abeb82a1446df2754","subject":"[NUCLEO_F401RE] enhance gcc ld file","message":"[NUCLEO_F401RE] enhance gcc ld file\n","repos":"maximmbed\/mbed,CalSol\/mbed,arostm\/mbed-os,monkiineko\/mbed-os,maximmbed\/mbed,K4zuki\/mbed,pi19404\/mbed,karsev\/mbed-os,kl-cruz\/mbed-os,andreaslarssonublox\/mbed,dbestm\/mbed,nRFMesh\/mbed-os,CalSol\/mbed,Archcady\/mbed-os,pi19404\/mbed,rosterloh\/mbed,svogl\/mbed-os,c1728p9\/mbed-os,j-greffe\/mbed-os,svastm\/mbed,larks\/mbed,ban4jp\/mbed,al177\/mbed,K4zuki\/mbed,infinnovation\/mbed-os,K4zuki\/mbed,sam-geek\/mbed,jrjang\/mbed,ryankurte\/mbed-os,fpiot\/mbed-ats,kpurusho\/mbed,cvtsi2sd\/mbed-os,jferreir\/mbed,JasonHow44\/mbed,andcor02\/mbed-os,FranklyDev\/mbed,NitinBhaskar\/mbed,devanlai\/mbed,pradeep-gr\/mbed-os5-onsemi,pradeep-gr\/mbed-os5-onsemi,xcrespo\/mbed,hwfwgrp\/mbed,iriark01\/mbed-drivers,cvtsi2sd\/mbed-os,c1728p9\/mbed-os,infinnovation\/mbed-os,geky\/mbed,jeremybrodt\/mbed,andcor02\/mbed-os,DanKupiniak\/mbed,brstew\/MBED-BUILD,c1728p9\/mbed-os,bikeNomad\/mbed,NXPmicro\/mbed,ARM-software\/mbed-beetle,wodji\/mbed,fvincenzo\/mbed-os,nabilbendafi\/mbed,mbedmicro\/mbed,jpbrucker\/mbed,alertby\/mbed,theotherjimmy\/mbed,svogl\/mbed-os,adamgreen\/mbed,adustm\/mbed,jrjang\/mbed,jeremybrodt\/mbed,kl-cruz\/mbed-os,j-greffe\/mbed-os,bremoran\/mbed-drivers,fahhem\/mbed-os,andreaslarssonublox\/mbed,jpbrucker\/mbed,kjbracey-arm\/mbed,bikeNomad\/mbed,nRFMesh\/mbed-os,logost\/mbed,bremoran\/mbed-drivers,netzimme\/mbed-os,svogl\/mbed-os,HeadsUpDisplayInc\/mbed,netzimme\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,Sweet-Peas\/mbed,Tiryoh\/mbed,getopenmono\/mbed,JasonHow44\/mbed,jferreir\/mbed,Shengliang\/mbed,tung7970\/mbed-os-1,mikaleppanen\/mbed-os,arostm\/mbed-os,nabilbendafi\/mbed,struempelix\/mbed,RonEld\/mbed,catiedev\/mbed-os,jamesadevine\/mbed,mmorenobarm\/mbed-os,struempelix\/mbed,nabilbendafi\/mbed,Sweet-Peas\/mbed,bikeNomad\/mbed,betzw\/mbed-os,andcor02\/mbed-os,pbrook\/mbed,adustm\/mbed,geky\/mbed,ban4jp\/mbed,pedromes\/mbed,Willem23\/mbed,ARM-software\/mbed-beetle,fahhem\/mbed-os,bikeNomad\/mbed,jamesadevine\/mbed,Sweet-Peas\/mbed,Tiryoh\/mbed,fanghuaqi\/mbed,mbedmicro\/mbed,svastm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,rosterloh\/mbed,pedromes\/mbed,adamgreen\/mbed,RonEld\/mbed,Willem23\/mbed,DanKupiniak\/mbed,mikaleppanen\/mbed-os,kl-cruz\/mbed-os,ryankurte\/mbed-os,getopenmono\/mbed,mazimkhan\/mbed-os,bulislaw\/mbed-os,NXPmicro\/mbed,fahhem\/mbed-os,karsev\/mbed-os,monkiineko\/mbed-os,K4zuki\/mbed,NitinBhaskar\/mbed,bentwire\/mbed,jrjang\/mbed,jamesadevine\/mbed,EmuxEvans\/mbed,pedromes\/mbed,nabilbendafi\/mbed,pbrook\/mbed,adamgreen\/mbed,hwfwgrp\/mbed,netzimme\/mbed-os,xcrespo\/mbed,bcostm\/mbed-os,mnlipp\/mbed,struempelix\/mbed,svogl\/mbed-os,FranklyDev\/mbed,Archcady\/mbed-os,mnlipp\/mbed,maximmbed\/mbed,Timmmm\/mbed,sg-\/mbed-drivers,al177\/mbed,CalSol\/mbed,naves-thiago\/mbed-midi,mikaleppanen\/mbed-os,xcrespo\/mbed,kl-cruz\/mbed-os,logost\/mbed,GustavWi\/mbed,theotherjimmy\/mbed,HeadsUpDisplayInc\/mbed,adustm\/mbed,fpiot\/mbed-ats,j-greffe\/mbed-os,YarivCol\/mbed-os,nRFMesh\/mbed-os,Timmmm\/mbed,jpbrucker\/mbed,pradeep-gr\/mbed-os5-onsemi,wodji\/mbed,CalSol\/mbed,RonEld\/mbed,masaohamanaka\/mbed,tung7970\/mbed-os-1,bikeNomad\/mbed,nvlsianpu\/mbed,betzw\/mbed-os,screamerbg\/mbed,EmuxEvans\/mbed,JasonHow44\/mbed,pi19404\/mbed,adustm\/mbed,masaohamanaka\/mbed,ban4jp\/mbed,mnlipp\/mbed,kjbracey-arm\/mbed,getopenmono\/mbed,struempelix\/mbed,c1728p9\/mbed-os,karsev\/mbed-os,logost\/mbed,bcostm\/mbed-os,dbestm\/mbed,Archcady\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,NitinBhaskar\/mbed,mmorenobarm\/mbed-os,jferreir\/mbed,fanghuaqi\/mbed,maximmbed\/mbed,screamerbg\/mbed,brstew\/MBED-BUILD,devanlai\/mbed,catiedev\/mbed-os,jpbrucker\/mbed,svogl\/mbed-os,maximmbed\/mbed,brstew\/MBED-BUILD,bentwire\/mbed,struempelix\/mbed,mikaleppanen\/mbed-os,fpiot\/mbed-ats,infinnovation\/mbed-os,catiedev\/mbed-os,Marcomissyou\/mbed,NitinBhaskar\/mbed,logost\/mbed,karsev\/mbed-os,Shengliang\/mbed,adamgreen\/mbed,hwfwgrp\/mbed,Tiryoh\/mbed,maximmbed\/mbed,GustavWi\/mbed,NXPmicro\/mbed,pradeep-gr\/mbed-os5-onsemi,pedromes\/mbed,Tiryoh\/mbed,fpiot\/mbed-ats,kpurusho\/mbed,ARM-software\/mbed-beetle,NXPmicro\/mbed,Archcady\/mbed-os,tung7970\/mbed-os,kpurusho\/mbed,andcor02\/mbed-os,pradeep-gr\/mbed-os5-onsemi,struempelix\/mbed,cvtsi2sd\/mbed-os,fvincenzo\/mbed-os,tung7970\/mbed-os,pbrook\/mbed,rgrover\/mbed,Archcady\/mbed-os,bentwire\/mbed,rosterloh\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,fpiot\/mbed-ats,HeadsUpDisplayInc\/mbed,naves-thiago\/mbed-midi,nvlsianpu\/mbed,monkiineko\/mbed-os,arostm\/mbed-os,catiedev\/mbed-os,mikaleppanen\/mbed-os,karsev\/mbed-os,Timmmm\/mbed,devanlai\/mbed,mbedmicro\/mbed,Sweet-Peas\/mbed,al177\/mbed,jrjang\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,Archcady\/mbed-os,bcostm\/mbed-os,Willem23\/mbed,jrjang\/mbed,DanKupiniak\/mbed,andreaslarssonublox\/mbed,GustavWi\/mbed,rgrover\/mbed,infinnovation\/mbed-os,fahhem\/mbed-os,alertby\/mbed,ban4jp\/mbed,hwfwgrp\/mbed,0xc0170\/mbed-drivers,karsev\/mbed-os,mazimkhan\/mbed-os,YarivCol\/mbed-os,tung7970\/mbed-os-1,naves-thiago\/mbed-midi,nRFMesh\/mbed-os,theotherjimmy\/mbed,adamgreen\/mbed,EmuxEvans\/mbed,dbestm\/mbed,Timmmm\/mbed,Willem23\/mbed,devanlai\/mbed,rosterloh\/mbed,screamerbg\/mbed,naves-thiago\/mbed-midi,CalSol\/mbed,fahhem\/mbed-os,bentwire\/mbed,Tiryoh\/mbed,Marcomissyou\/mbed,andreaslarssonublox\/mbed,GustavWi\/mbed,fvincenzo\/mbed-os,brstew\/MBED-BUILD,mazimkhan\/mbed-os,EmuxEvans\/mbed,andcor02\/mbed-os,getopenmono\/mbed,geky\/mbed,nRFMesh\/mbed-os,tung7970\/mbed-os,betzw\/mbed-os,Marcomissyou\/mbed,naves-thiago\/mbed-midi,nvlsianpu\/mbed,Marcomissyou\/mbed,fanghuaqi\/mbed,ryankurte\/mbed-os,mmorenobarm\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,mikaleppanen\/mbed-os,jeremybrodt\/mbed,YarivCol\/mbed-os,HeadsUpDisplayInc\/mbed,kpurusho\/mbed,cvtsi2sd\/mbed-os,bcostm\/mbed-os,pedromes\/mbed,bcostm\/mbed-os,wodji\/mbed,monkiineko\/mbed-os,c1728p9\/mbed-os,netzimme\/mbed-os,Shengliang\/mbed,svogl\/mbed-os,brstew\/MBED-BUILD,kpurusho\/mbed,kl-cruz\/mbed-os,mmorenobarm\/mbed-os,alertby\/mbed,pbrook\/mbed,tung7970\/mbed-os,jpbrucker\/mbed,ryankurte\/mbed-os,arostm\/mbed-os,nabilbendafi\/mbed,nvlsianpu\/mbed,Shengliang\/mbed,logost\/mbed,pi19404\/mbed,svastm\/mbed,wodji\/mbed,jpbrucker\/mbed,adamgreen\/mbed,betzw\/mbed-os,rosterloh\/mbed,monkiineko\/mbed-os,tung7970\/mbed-os,screamerbg\/mbed,geky\/mbed,Shengliang\/mbed,theotherjimmy\/mbed,RonEld\/mbed,screamerbg\/mbed,ARM-software\/mbed-beetle,netzimme\/mbed-os,bulislaw\/mbed-os,Timmmm\/mbed,RonEld\/mbed,sg-\/mbed-drivers,alertby\/mbed,Marcomissyou\/mbed,pedromes\/mbed,Shengliang\/mbed,screamerbg\/mbed,rosterloh\/mbed,nvlsianpu\/mbed,wodji\/mbed,fanghuaqi\/mbed,bulislaw\/mbed-os,hwfwgrp\/mbed,pi19404\/mbed,adustm\/mbed,pi19404\/mbed,larks\/mbed,K4zuki\/mbed,fpiot\/mbed-ats,sam-geek\/mbed,Timmmm\/mbed,catiedev\/mbed-os,NXPmicro\/mbed,cvtsi2sd\/mbed-os,rgrover\/mbed,getopenmono\/mbed,al177\/mbed,ban4jp\/mbed,brstew\/MBED-BUILD,sam-geek\/mbed,xcrespo\/mbed,kpurusho\/mbed,larks\/mbed,andcor02\/mbed-os,j-greffe\/mbed-os,devanlai\/mbed,mnlipp\/mbed,FranklyDev\/mbed,NitinBhaskar\/mbed,sam-geek\/mbed,autopulated\/mbed,nRFMesh\/mbed-os,ryankurte\/mbed-os,fahhem\/mbed-os,bulislaw\/mbed-os,0xc0170\/mbed-drivers,cvtsi2sd\/mbed-os,jferreir\/mbed,theotherjimmy\/mbed,bentwire\/mbed,alertby\/mbed,bentwire\/mbed,kl-cruz\/mbed-os,theotherjimmy\/mbed,jamesadevine\/mbed,jrjang\/mbed,al177\/mbed,devanlai\/mbed,nvlsianpu\/mbed,jeremybrodt\/mbed,jferreir\/mbed,mbedmicro\/mbed,iriark01\/mbed-drivers,fvincenzo\/mbed-os,YarivCol\/mbed-os,dbestm\/mbed,xcrespo\/mbed,masaohamanaka\/mbed,mbedmicro\/mbed,JasonHow44\/mbed,YarivCol\/mbed-os,bcostm\/mbed-os,mmorenobarm\/mbed-os,bulislaw\/mbed-os,betzw\/mbed-os,YarivCol\/mbed-os,mmorenobarm\/mbed-os,FranklyDev\/mbed,ryankurte\/mbed-os,autopulated\/mbed,autopulated\/mbed,larks\/mbed,Tiryoh\/mbed,monkiineko\/mbed-os,mnlipp\/mbed,adustm\/mbed,autopulated\/mbed,masaohamanaka\/mbed,rgrover\/mbed,fanghuaqi\/mbed,jferreir\/mbed,catiedev\/mbed-os,kjbracey-arm\/mbed,Marcomissyou\/mbed,fvincenzo\/mbed-os,HeadsUpDisplayInc\/mbed,getopenmono\/mbed,pbrook\/mbed,arostm\/mbed-os,ban4jp\/mbed,larks\/mbed,mazimkhan\/mbed-os,infinnovation\/mbed-os,jamesadevine\/mbed,j-greffe\/mbed-os,svastm\/mbed,FranklyDev\/mbed,masaohamanaka\/mbed,Sweet-Peas\/mbed,j-greffe\/mbed-os,GustavWi\/mbed,c1728p9\/mbed-os,hwfwgrp\/mbed,JasonHow44\/mbed,EmuxEvans\/mbed,infinnovation\/mbed-os,naves-thiago\/mbed-midi,al177\/mbed,masaohamanaka\/mbed,alertby\/mbed,mazimkhan\/mbed-os,bulislaw\/mbed-os,larks\/mbed,Willem23\/mbed,sam-geek\/mbed,rgrover\/mbed,mnlipp\/mbed,NXPmicro\/mbed,CalSol\/mbed,andreaslarssonublox\/mbed,wodji\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,DanKupiniak\/mbed,HeadsUpDisplayInc\/mbed,EmuxEvans\/mbed,kjbracey-arm\/mbed,Sweet-Peas\/mbed,pbrook\/mbed,netzimme\/mbed-os,tung7970\/mbed-os-1,geky\/mbed,K4zuki\/mbed,autopulated\/mbed,xcrespo\/mbed,jamesadevine\/mbed,tung7970\/mbed-os-1,mazimkhan\/mbed-os,svastm\/mbed,dbestm\/mbed,autopulated\/mbed,RonEld\/mbed,JasonHow44\/mbed,nabilbendafi\/mbed,jeremybrodt\/mbed,arostm\/mbed-os,dbestm\/mbed,logost\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_NUCLEO_F401RE\/TOOLCHAIN_GCC_ARM\/NUCLEO_F401RE.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_NUCLEO_F401RE\/TOOLCHAIN_GCC_ARM\/NUCLEO_F401RE.ld","new_contents":"\/* Linker script for STM32F407 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K\n\/*  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K *\/\n  RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 96k - 0x194\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","old_contents":"\/* Linker script for STM32F407 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K\n\/*  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K *\/\n  RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 0x17E6C\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4eb58212aca1c4f2bac7cab7fd43eee23d7d0ffd","subject":"Remove duplicate definitions","message":"Remove duplicate definitions\n","repos":"zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder","old_file":"include\/esp8266\/ld\/eagle.rom.addr.v6.ld","new_file":"include\/esp8266\/ld\/eagle.rom.addr.v6.ld","new_contents":"PROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( ets_run = 0x40000e04 );\nPROVIDE ( ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n\nPROVIDE ( SPI_sector_erase = 0x400040c0 );\nPROVIDE ( SPI_page_program = 0x40004174 );\nPROVIDE ( SPI_read_data = 0x400042ac );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( Disable_QMode = 0x40004508 );\n","old_contents":"PROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( ets_run = 0x40000e04 );\nPROVIDE ( ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n\nPROVIDE ( SPI_sector_erase = 0x400040c0 );\nPROVIDE ( SPI_page_program = 0x40004174 );\nPROVIDE ( SPI_read_data = 0x400042ac );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( Disable_QMode = 0x40004508 );\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"fdb23d848d1fbc7ffc098700ca37a489069388c0","subject":"soc: esp32s2: Fix symbol placement in linker script","message":"soc: esp32s2: Fix symbol placement in linker script\n\nCreating static libraries for drivers moves some symbols out of IRAM.\nThis change fixes it.\n\nSigned-off-by: Shubham Kulkarni <1478dde7897089bf180c3c690a61b19b869e8abd@espressif.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"soc\/xtensa\/esp32s2\/linker.ld","new_file":"soc\/xtensa\/esp32s2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32s2 platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAM_IRAM_START    0x40020000\n#define RAM_DRAM_START    0x3ffb0000\n\n#define DATA_RAM_END      0x3ffe0000  \/* 2nd stage bootloader iram_loader_seg starts at SRAM block 14 (reclaimed after app boots) *\/\n\n#define IRAM_ORG    (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define DRAM_ORG    (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define I_D_RAM_SIZE   DATA_RAM_END - DRAM_ORG\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = IRAM_ORG, len = I_D_RAM_SIZE\n  irom0_0_seg(RX): org = 0x40080020, len = 0x780000-0x20\n  dram0_0_seg(RW): org = DRAM_ORG, len = I_D_RAM_SIZE\n  drom0_0_seg(R): org = 0x3f000020, len = 0x3f0000-0x20\n  rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x2000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    _iram_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n  } GROUP_LINK_IN(IRAM_REGION)\n\n   .dram0_reserved_for_iram (NOLOAD):\n  {\n   . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } > dram0_0_seg\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_condvar);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef ITERABLE_SECTION_RAM_GC_ALLOWED\n#define ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef ITERABLE_SECTION_RAM\n#define ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","old_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32s2 platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAM_IRAM_START    0x40020000\n#define RAM_DRAM_START    0x3ffb0000\n\n#define DATA_RAM_END      0x3ffe0000  \/* 2nd stage bootloader iram_loader_seg starts at SRAM block 14 (reclaimed after app boots) *\/\n\n#define IRAM_ORG    (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define DRAM_ORG    (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define I_D_RAM_SIZE   DATA_RAM_END - DRAM_ORG\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = IRAM_ORG, len = I_D_RAM_SIZE\n  irom0_0_seg(RX): org = 0x40080020, len = 0x780000-0x20\n  dram0_0_seg(RW): org = DRAM_ORG, len = I_D_RAM_SIZE\n  drom0_0_seg(R): org = 0x3f000020, len = 0x3f0000-0x20\n  rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x2000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    _iram_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n  } GROUP_LINK_IN(IRAM_REGION)\n\n   .dram0_reserved_for_iram (NOLOAD):\n  {\n   . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } > dram0_0_seg\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_condvar);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef ITERABLE_SECTION_RAM_GC_ALLOWED\n#define ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef ITERABLE_SECTION_RAM\n#define ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f8e18d892faae6d6ec3d19744d1b35e2c606fac2","subject":"Leave only some parts of SDK in iram (#1710)","message":"Leave only some parts of SDK in iram (#1710)\n\nLeave only some parts of SDK in IRAM","repos":"nodemcu\/nodemcu-firmware,FrankX0\/nodemcu-firmware,karrots\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,FelixPe\/nodemcu-firmware,jmattsson\/nodemcu-firmware,eku\/nodemcu-firmware,djphoenix\/nodemcu-firmware,oyooyo\/nodemcu-firmware,nodemcu\/nodemcu-firmware,jmattsson\/nodemcu-firmware,devsaurus\/nodemcu-firmware,fetchbot\/nodemcu-firmware,nwf\/nodemcu-firmware,nwf\/nodemcu-firmware,jmattsson\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,fetchbot\/nodemcu-firmware,TerryE\/nodemcu-firmware,FelixPe\/nodemcu-firmware,djphoenix\/nodemcu-firmware,karrots\/nodemcu-firmware,TerryE\/nodemcu-firmware,vsky279\/nodemcu-firmware,devsaurus\/nodemcu-firmware,jmattsson\/nodemcu-firmware,FelixPe\/nodemcu-firmware,dnc40085\/nodemcu-firmware,vsky279\/nodemcu-firmware,jmattsson\/nodemcu-firmware,fetchbot\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,oyooyo\/nodemcu-firmware,TerryE\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,dnc40085\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,TerryE\/nodemcu-firmware,karrots\/nodemcu-firmware,FrankX0\/nodemcu-firmware,FrankX0\/nodemcu-firmware,dnc40085\/nodemcu-firmware,eku\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,vsky279\/nodemcu-firmware,djphoenix\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,nodemcu\/nodemcu-firmware,FelixPe\/nodemcu-firmware,nwf\/nodemcu-firmware,djphoenix\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,nwf\/nodemcu-firmware,eku\/nodemcu-firmware,devsaurus\/nodemcu-firmware,oyooyo\/nodemcu-firmware,devsaurus\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,FelixPe\/nodemcu-firmware,dnc40085\/nodemcu-firmware,nodemcu\/nodemcu-firmware,vsky279\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,nodemcu\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,devsaurus\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,nwf\/nodemcu-firmware,vsky279\/nodemcu-firmware,TerryE\/nodemcu-firmware,karrots\/nodemcu-firmware,FrankX0\/nodemcu-firmware,karrots\/nodemcu-firmware,dnc40085\/nodemcu-firmware,oyooyo\/nodemcu-firmware,FrankX0\/nodemcu-firmware,fetchbot\/nodemcu-firmware,eku\/nodemcu-firmware","old_file":"ld\/nodemcu.ld","new_file":"ld\/nodemcu.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40210000, len = 0xD0000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(user_start_trampoline)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \n    \/* SDK libraries that used in bootup process, interruption handling\n     * and other ways where flash cache (iROM) is unavailable: *\/\n    *libmain.a:*(.literal .text)\n    *libnet80211.a:*(.literal .text)\n    *libphy.a:*(.literal .text)\n    *libpp.a:*(.literal .text)\n    *libgcc.a:*(.literal .text)\n    \n    \/* Following SDK libraries have .text sections, but not included in iRAM: *\/\n    \/* *libat.a:*(.literal .text) - not used anywhere in NodeMCU *\/\n    \/* *libcrypto.a:*(.literal .text) - tested that safe to keep in iROM *\/\n    \/* *libdriver.a:*(.literal .text) - not used anywhere in NodeMCU *\/\n    \/* *libespnow.a:*(.literal .text) - not used anywhere in NodeMCU *\/\n    \/* *libmesh.a:*(.literal .text) - not used anywhere in NodeMCU *\/\n    \/* *liblwip_536.a:*(.literal .text) - source-based library used instead *\/\n    \/* *libpwm.a:*(.literal .text) - our own implementation used instead *\/\n    \/* *libwpa.a:*(.literal .text) - tested that safe to keep in iROM *\/\n    \/* *libwps.a:*(.literal .text) - tested that safe to keep in iROM *\/\n\n    *(.iram.text .iram0.text)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    \n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    *(.rodata.dram .rodata.dram*)\n\n    *(.gnu.linkonce.r.*)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(0x1000)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.servercert.flash)\n    *(.clientcert.flash)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal .text .literal.* .text.*)\n    *(.rodata*)\n    *(.sdk.version)\n\n    \/* Link-time arrays containing the defs for the included modules *\/\n    . = ALIGN(4);\n    lua_libs = ABSOLUTE(.);\n    \/* Allow either empty define or defined-to-1 to include the module *\/\n    KEEP(*(.lua_libs))\n    LONG(0) LONG(0) \/* Null-terminate the array *\/\n    lua_rotable = ABSOLUTE(.);\n    KEEP(*(.lua_rotable))\n    LONG(0) LONG(0) \/* Null-terminate the array *\/\n\n    \/* SDK doesn't use libc functions, and are therefore safe to put in flash *\/\n    *\/libc.a:*.o(.text* .literal*)\n    \/* end libc functions *\/\n\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_used_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr =0xffffffff\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40210000, len = 0xD0000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(user_start_trampoline)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \n    *sdk\/esp_iot_sdk_*lib\/lib*.a:*(.literal .text)\n\n    *(.iram.text .iram0.text)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    \n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    *(.rodata.dram .rodata.dram*)\n\n    *(.gnu.linkonce.r.*)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(0x1000)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.servercert.flash)\n    *(.clientcert.flash)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal .text .literal.* .text.*)\n    *(.rodata*)\n    *(.sdk.version)\n\n    \/* Link-time arrays containing the defs for the included modules *\/\n    . = ALIGN(4);\n    lua_libs = ABSOLUTE(.);\n    \/* Allow either empty define or defined-to-1 to include the module *\/\n    KEEP(*(.lua_libs))\n    LONG(0) LONG(0) \/* Null-terminate the array *\/\n    lua_rotable = ABSOLUTE(.);\n    KEEP(*(.lua_rotable))\n    LONG(0) LONG(0) \/* Null-terminate the array *\/\n\n    \/* SDK doesn't use libc functions, and are therefore safe to put in flash *\/\n    *\/libc.a:*.o(.text* .literal*)\n    \/* end libc functions *\/\n\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_used_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr =0xffffffff\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"91ba0393817470a277365944d0e66dcc5b89c8b8","subject":"riscv: linker: add support for FLASH_LOAD_OFFSET","message":"riscv: linker: add support for FLASH_LOAD_OFFSET\n\nThis allows board to re-configure ROM_BASE address while building\nfirmware image.\n\nFor example, a board need to build two firmware images. And the images\nare put into one flash and required to work independent:\n\nconfig FLASH_LOAD_OFFSET\n    default 0 if FIRST_IMAGE\n    default 0x80000 if SECOND_IMAGE\n\nSigned-off-by: Dino Li <338d523ecf3700bd86eb9c34d220f91911d2a18c@ite.com.tw>\n","repos":"galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n\t_image_rodata_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end - _image_rom_start);\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n\t_image_rodata_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end - _image_rom_start);\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"68450304831d20657f9d9f14621cd185b0de1a66","subject":"Update linker script for SDK 1.1.0","message":"Update linker script for SDK 1.1.0\n\nException vectors have moved into .text.\n","repos":"edog1973\/Arduino,Juppit\/Arduino,quertenmont\/Arduino,martinayotte\/ESP8266-Arduino,edog1973\/Arduino,gguuss\/Arduino,CanTireInnovations\/Arduino,Cloudino\/Cloudino-Arduino-IDE,NextDevBoard\/Arduino,wemos\/Arduino,Cloudino\/Arduino,martinayotte\/ESP8266-Arduino,toastedcode\/esp8266-Arduino,KaloNK\/Arduino,Adam5Wu\/Arduino,edog1973\/Arduino,toastedcode\/esp8266-Arduino,NullMedia\/Arduino,sticilface\/Arduino,Lan-Hekary\/Arduino,CanTireInnovations\/Arduino,Cloudino\/Arduino,wemos\/Arduino,Cloudino\/Arduino,lrmoreno007\/Arduino,lrmoreno007\/Arduino,hallard\/Arduino,Adam5Wu\/Arduino,CanTireInnovations\/Arduino,me-no-dev\/Arduino,esp8266\/Arduino,chrisfraser\/Arduino,Juppit\/Arduino,chrisfraser\/Arduino,sticilface\/Arduino,sticilface\/Arduino,Cloudino\/Cloudino-Arduino-IDE,hallard\/Arduino,quertenmont\/Arduino,me-no-dev\/Arduino,Adam5Wu\/Arduino,toastedcode\/esp8266-Arduino,esp8266\/Arduino,NullMedia\/Arduino,hallard\/Arduino,esp8266\/Arduino,lrmoreno007\/Arduino,Cloudino\/Arduino,Lan-Hekary\/Arduino,Links2004\/Arduino,Juppit\/Arduino,edog1973\/Arduino,quertenmont\/Arduino,jes\/Arduino,KaloNK\/Arduino,chrisfraser\/Arduino,NullMedia\/Arduino,hallard\/Arduino,esp8266\/Arduino,Cloudino\/Cloudino-Arduino-IDE,Links2004\/Arduino,gguuss\/Arduino,Juppit\/Arduino,Cloudino\/Cloudino-Arduino-IDE,KaloNK\/Arduino,me-no-dev\/Arduino,Cloudino\/Cloudino-Arduino-IDE,Lan-Hekary\/Arduino,NextDevBoard\/Arduino,NullMedia\/Arduino,me-no-dev\/Arduino,KaloNK\/Arduino,NextDevBoard\/Arduino,Lan-Hekary\/Arduino,KaloNK\/Arduino,Juppit\/Arduino,NextDevBoard\/Arduino,gguuss\/Arduino,hallard\/Arduino,Cloudino\/Arduino,gguuss\/Arduino,Links2004\/Arduino,NextDevBoard\/Arduino,NullMedia\/Arduino,chrisfraser\/Arduino,Adam5Wu\/Arduino,quertenmont\/Arduino,CanTireInnovations\/Arduino,sticilface\/Arduino,Links2004\/Arduino,gguuss\/Arduino,toastedcode\/esp8266-Arduino,CanTireInnovations\/Arduino,Cloudino\/Arduino,jes\/Arduino,edog1973\/Arduino,chrisfraser\/Arduino,martinayotte\/ESP8266-Arduino,quertenmont\/Arduino,martinayotte\/ESP8266-Arduino,Cloudino\/Cloudino-Arduino-IDE,lrmoreno007\/Arduino,wemos\/Arduino,lrmoreno007\/Arduino,jes\/Arduino,CanTireInnovations\/Arduino,esp8266\/Arduino,wemos\/Arduino,me-no-dev\/Arduino,toastedcode\/esp8266-Arduino,martinayotte\/ESP8266-Arduino,jes\/Arduino,jes\/Arduino,Adam5Wu\/Arduino,Lan-Hekary\/Arduino,sticilface\/Arduino,wemos\/Arduino,Cloudino\/Cloudino-Arduino-IDE,Links2004\/Arduino,CanTireInnovations\/Arduino,Cloudino\/Arduino","old_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *spiffs*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *spiffs*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"b01e1b390f1a94525256ea93d17fb8a804f7187c","subject":"User progs were overwriting kernel","message":"User progs were overwriting kernel\n","repos":"stelfer\/nubbin,stelfer\/nubbin","old_file":"kernel\/asm\/os-image.elf_x86_64.ld","new_file":"kernel\/asm\/os-image.elf_x86_64.ld","new_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nboot_paddr   = 0x007c00;\t\t\/* boot offset *\/\nkernel_paddr = 0x100000;\nkernel_vaddr = 0xffffffff00100000;\n\nkernel_pos   = 0x001000;\t\t\/* physical position in output *\/\n\/* kernel_off   = - kernel_vaddr + kernel_pos + boot_paddr; *\/\n\npage_table_paddr   = 0x00200000;\nkernel_stack_paddr = 0x005fffff;\nkernel_size = SIZEOF(.kernel);\n\nuser_vaddr = 0x100000;\n\nSECTIONS\n{\n\t.boot-setup boot_paddr :\n\t{\n\t\t*(.boot)\n\t\t_setup_paddr = .;\n\t\t*(.setup)\n\t}\n\n\t.kernel kernel_vaddr : AT(boot_paddr + kernel_pos)\n\t{\n\t\t*.ko(.text)\n\t\t*.ko(.data*)\n\t\t*.ko(.rodata*)\n\t\t*.ko(COMMON*)\n\t\t*.ko(.bss*)\n\t}\n\n\t.user user_vaddr + SIZEOF(.kernel): AT(LOADADDR(.kernel) + SIZEOF(.kernel))\n\t{\n\t\t*.o(.text)\n\t\t*.o(.data*)\n\t\t*.o(.rodata*)\n\t\t*.o(COMMON*)\n\t\t*.o(.bss*)\n\t}\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.eh_frame)\n\t\t*(.comment)\n\t}\n}\n","old_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nboot_paddr   = 0x007c00;\t\t\/* boot offset *\/\nkernel_paddr = 0x100000;\nkernel_vaddr = 0xffffffff00100000;\n\nkernel_pos   = 0x001000;\t\t\/* physical position in output *\/\n\/* kernel_off   = - kernel_vaddr + kernel_pos + boot_paddr; *\/\n\npage_table_paddr   = 0x00200000;\nkernel_stack_paddr = 0x005fffff;\nkernel_size = SIZEOF(.kernel);\n\nuser_vaddr = 0x100000;\n\nSECTIONS\n{\n\t.boot-setup boot_paddr :\n\t{\n\t\t*(.boot)\n\t\t_setup_paddr = .;\n\t\t*(.setup)\n\t}\n\n\t.kernel kernel_vaddr : AT(boot_paddr + kernel_pos)\n\t{\n\t\t*.ko(.text)\n\t\t*.ko(.data*)\n\t\t*.ko(.rodata*)\n\t\t*.ko(COMMON*)\n\t\t*.ko(.bss*)\n\t}\n\n\t.user user_vaddr : AT(LOADADDR(.kernel) + SIZEOF(.kernel))\n\t{\n\t\t*.o(.text)\n\t\t*.o(.data*)\n\t\t*.o(.rodata*)\n\t\t*.o(COMMON*)\n\t\t*.o(.bss*)\n\t}\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.eh_frame)\n\t\t*(.comment)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"13ef690192173f5c33fa577983f7c5069732f3bc","subject":"aarch64: linker: Remove unused symbols and sections","message":"aarch64: linker: Remove unused symbols and sections\n\nRemove unused symbols and related sections from the linker script. In\nparticular CONFIG_IS_BOOTLOADER and CONFIG_CODE_DATA_RELOCATION are not\ncurrently supported on AArch64.\n\nSigned-off-by: Carlo Caione <ca4506c8c654a4ccf75802e86b5d162c1e96f065@baylibre.com>\n","repos":"Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e55d025f59970e3880da3a797b9bb0da85d86bbe","subject":"\u30b9\u30bf\u30c3\u30af\u9818\u57df\u306e\u4fee\u6b63","message":"\u30b9\u30bf\u30c3\u30af\u9818\u57df\u306e\u4fee\u6b63\n","repos":"hirakuni45\/R8C,hirakuni45\/R8C,hirakuni45\/R8C","old_file":"M120AN\/m120an.ld","new_file":"M120AN\/m120an.ld","new_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x0300, LENGTH = 0x0400\n\tROM (r)  : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVVEC (r) : ORIGIN = 0xFED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0780;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x0300, LENGTH = 0x0400\n\tROM (r)  : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVVEC (r) : ORIGIN = 0xFED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x07C0;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"e0d0e3727f7dabdbc60c1f107067a8a801a9618e","subject":"Remove unused linker define","message":"Remove unused linker define\n","repos":"timtomch\/BlinkyPendant,timtomch\/BlinkyPendant,Blinkinlabs\/BlinkyPendant,timtomch\/BlinkyPendant,Blinkinlabs\/BlinkyPendant,Blinkinlabs\/BlinkyPendant","old_file":"bootloader\/mk20dx128.ld","new_file":"bootloader\/mk20dx128.ld","new_contents":"","old_contents":"\/*\n * FC-Boot linker script.\n *\n *   - Early startup code runs out of flash\n *   - Everything else runs out of RAM\n *   - All flash after the first 4K page is reserved for application use\n *   - The last 4 bytes of RAM are used as our boot token\n *\/\n\n\nMEMORY\n{\n    BOOT_FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 4K\n    APP_FLASH (rx) : ORIGIN = 0x00001000, LENGTH = 124K\n    RAM (rwx) : ORIGIN = 0x1FFFE000, LENGTH = 16K\n    FLEXRAM (rwx) : ORIGIN = 0x14000000, LENGTH = 2K\n}\n\nSECTIONS\n{\n    .flash : {\n        . = 0;\n        KEEP(*(.vectors))\n        *(.startup*)\n        . = 0x400;\n        KEEP(*(.flashconfig*))\n    } > BOOT_FLASH = 0xFF\n    _eflash = .;\n\n    .apptext (NOLOAD) : {\n        . = ORIGIN(APP_FLASH);\n        *(.appvectors)\n    } > APP_FLASH = 0xFF\n\n    .usbdescriptortable (NOLOAD) : {\n        . = ALIGN(512);\n        *(.usbdescriptortable*)\n    } > RAM\n\n    .dmabuffers (NOLOAD) : {\n        . = ALIGN(4);\n        *(.dmabuffers*)\n    } > RAM\n\n    .usbbuffers (NOLOAD) : {\n        . = ALIGN(4);\n        *(.usbbuffers*)\n    } > RAM\n\n    .flexram (NOLOAD) : {\n        . = ALIGN(4);\n        *(.flexram*)\n    } > FLEXRAM\n\n    \/* Combined data and text, after relocation *\/\n    .dtext : AT (_eflash) {\n        . = ALIGN(4);\n        _sdtext = .; \n        *(.text*)\n        *(.rodata*)\n        *(.data*)\n        . = ALIGN(4);\n        _edtext = .; \n    } > RAM\n\n    .noinit (NOLOAD) : {\n        *(.noinit*)\n    } > RAM\n\n    .bss : {\n        . = ALIGN(4);\n        _sbss = .; \n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n        __bss_end = .;\n    } > RAM\n\n    _estack = ORIGIN(RAM) + LENGTH(RAM) - 4;\n    boot_token = _estack;\n}\n\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"76155ea820f54d9aa74d3975962f51a612d6a25f","subject":"cpu\/stm32l4\/ldscripts: fix stm32l476rg cpuid","message":"cpu\/stm32l4\/ldscripts: fix stm32l476rg cpuid\n","repos":"kaspar030\/RIOT,neiljay\/RIOT,BytesGalore\/RIOT,x3ro\/RIOT,yogo1212\/RIOT,syin2\/RIOT,ant9000\/RIOT,dkm\/RIOT,gautric\/RIOT,Josar\/RIOT,hamilton-mote\/RIOT-OS,josephnoir\/RIOT,kYc0o\/RIOT,rfuentess\/RIOT,yogo1212\/RIOT,avmelnikoff\/RIOT,Ell-i\/RIOT,adrianghc\/RIOT,LudwigOrtmann\/RIOT,dailab\/RIOT,toonst\/RIOT,aeneby\/RIOT,A-Paul\/RIOT,aeneby\/RIOT,thomaseichinger\/RIOT,kYc0o\/RIOT,neiljay\/RIOT,kaleb-himes\/RIOT,jfischer-phytec-iot\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,immesys\/RiSyn,Josar\/RIOT,rfuentess\/RIOT,OTAkeys\/RIOT,ks156\/RIOT,biboc\/RIOT,x3ro\/RIOT,Hyungsin\/RIOT-OS,jfischer-phytec-iot\/RIOT,avmelnikoff\/RIOT,kerneltask\/RIOT,kaspar030\/RIOT,LudwigOrtmann\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,mtausig\/RIOT,miri64\/RIOT,mtausig\/RIOT,gautric\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,toonst\/RIOT,adrianghc\/RIOT,aeneby\/RIOT,gautric\/RIOT,immesys\/RiSyn,dailab\/RIOT,LudwigKnuepfer\/RIOT,syin2\/RIOT,josephnoir\/RIOT,kYc0o\/RIOT,kaleb-himes\/RIOT,smlng\/RIOT,x3ro\/RIOT,kerneltask\/RIOT,smlng\/RIOT,BytesGalore\/RIOT,adjih\/RIOT,plushvoxel\/RIOT,neiljay\/RIOT,cladmi\/RIOT,basilfx\/RIOT,cladmi\/RIOT,OTAkeys\/RIOT,kerneltask\/RIOT,Josar\/RIOT,adrianghc\/RIOT,Ell-i\/RIOT,basilfx\/RIOT,dkm\/RIOT,jfischer-phytec-iot\/RIOT,hamilton-mote\/RIOT-OS,LudwigOrtmann\/RIOT,authmillenon\/RIOT,ant9000\/RIOT,rfuentess\/RIOT,immesys\/RiSyn,LudwigKnuepfer\/RIOT,roberthartung\/RIOT,yogo1212\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,neumodisch\/RIOT,avmelnikoff\/RIOT,mfrey\/RIOT,jasonatran\/RIOT,kerneltask\/RIOT,hamilton-mote\/RIOT-OS,authmillenon\/RIOT,smlng\/RIOT,cladmi\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,gebart\/RIOT,lazytech-org\/RIOT,kaspar030\/RIOT,biboc\/RIOT,ks156\/RIOT,Ell-i\/RIOT,adrianghc\/RIOT,kbumsik\/RIOT,gebart\/RIOT,jfischer-phytec-iot\/RIOT,neiljay\/RIOT,A-Paul\/RIOT,dkm\/RIOT,RIOT-OS\/RIOT,ks156\/RIOT,lazytech-org\/RIOT,syin2\/RIOT,adjih\/RIOT,roberthartung\/RIOT,LudwigOrtmann\/RIOT,toonst\/RIOT,OTAkeys\/RIOT,plushvoxel\/RIOT,ant9000\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,roberthartung\/RIOT,A-Paul\/RIOT,beurdouche\/RIOT,kbumsik\/RIOT,neumodisch\/RIOT,rfuentess\/RIOT,lazytech-org\/RIOT,plushvoxel\/RIOT,Hyungsin\/RIOT-OS,cladmi\/RIOT,immesys\/RiSyn,LudwigOrtmann\/RIOT,thomaseichinger\/RIOT,Hyungsin\/RIOT-OS,toonst\/RIOT,hamilton-mote\/RIOT-OS,beurdouche\/RIOT,immesys\/RiSyn,neumodisch\/RIOT,immesys\/RiSyn,x3ro\/RIOT,adrianghc\/RIOT,dailab\/RIOT,thomaseichinger\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,mfrey\/RIOT,kerneltask\/RIOT,A-Paul\/RIOT,BytesGalore\/RIOT,lazytech-org\/RIOT,basilfx\/RIOT,authmillenon\/RIOT,LudwigKnuepfer\/RIOT,gebart\/RIOT,jasonatran\/RIOT,jfischer-phytec-iot\/RIOT,ks156\/RIOT,plushvoxel\/RIOT,neiljay\/RIOT,dailab\/RIOT,hamilton-mote\/RIOT-OS,basilfx\/RIOT,thomaseichinger\/RIOT,beurdouche\/RIOT,toonst\/RIOT,kaleb-himes\/RIOT,cladmi\/RIOT,Josar\/RIOT,syin2\/RIOT,josephnoir\/RIOT,dkm\/RIOT,mtausig\/RIOT,jasonatran\/RIOT,LudwigOrtmann\/RIOT,aeneby\/RIOT,Ell-i\/RIOT,biboc\/RIOT,kaspar030\/RIOT,Josar\/RIOT,neumodisch\/RIOT,aeneby\/RIOT,beurdouche\/RIOT,kYc0o\/RIOT,mfrey\/RIOT,neumodisch\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,LudwigKnuepfer\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,OTAkeys\/RIOT,Ell-i\/RIOT,rfuentess\/RIOT,thomaseichinger\/RIOT,adjih\/RIOT,mtausig\/RIOT,avmelnikoff\/RIOT,ks156\/RIOT,adjih\/RIOT,kaleb-himes\/RIOT,beurdouche\/RIOT,gebart\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,miri64\/RIOT,lazytech-org\/RIOT,yogo1212\/RIOT,smlng\/RIOT,kbumsik\/RIOT,dailab\/RIOT,jasonatran\/RIOT,Hyungsin\/RIOT-OS,OlegHahm\/RIOT,kaleb-himes\/RIOT,roberthartung\/RIOT,mfrey\/RIOT,authmillenon\/RIOT,gautric\/RIOT,LudwigKnuepfer\/RIOT,josephnoir\/RIOT,Hyungsin\/RIOT-OS,BytesGalore\/RIOT,RIOT-OS\/RIOT,plushvoxel\/RIOT,BytesGalore\/RIOT,OlegHahm\/RIOT,josephnoir\/RIOT,dkm\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,syin2\/RIOT,smlng\/RIOT,kaspar030\/RIOT,biboc\/RIOT,gebart\/RIOT,roberthartung\/RIOT,kbumsik\/RIOT,RIOT-OS\/RIOT,avmelnikoff\/RIOT,mfrey\/RIOT,mtausig\/RIOT,basilfx\/RIOT,kbumsik\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,kYc0o\/RIOT,gautric\/RIOT,adjih\/RIOT,A-Paul\/RIOT,biboc\/RIOT,neumodisch\/RIOT","old_file":"cpu\/stm32l4\/ldscripts\/stm32l476rg.ld","new_file":"cpu\/stm32l4\/ldscripts\/stm32l476rg.ld","new_contents":"\/*\n * Copyright (C) 2017 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_stm32l4\n * @{\n *\n * @file\n * @brief           Memory definitions for the STM32L476RG\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x08000000, LENGTH = 1024K\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 128K\n    cpuid (r)   : ORIGIN = 0x1fff7590, LENGTH = 12\n}\n\n_cpuid_address = ORIGIN(cpuid);\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2017 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_stm32l4\n * @{\n *\n * @file\n * @brief           Memory definitions for the STM32L476RG\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x08000000, LENGTH = 1024K\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 128K\n    cpuid (r)   : ORIGIN = 0x1ff80050, LENGTH = 12\n}\n\n_cpuid_address = ORIGIN(cpuid);\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"a82e3c7ddb4dc269838e980d7613e8d835864855","subject":"docs(ldoc) update description to reflect 3.X support","message":"docs(ldoc) update description to reflect 3.X support\n","repos":"thibaultCha\/lua-cassandra,thibaultCha\/lua-cassandra","old_file":"docs\/config.ld","new_file":"docs\/config.ld","new_contents":"project = \"lua-cassandra\"\ntitle = \"lua-cassandra documentation\"\ndescription = \"A pure Lua client library for Apache Cassandra\"\nreadme = \"doc\/README.md\"\nformat = \"markdown\"\nstyle = true -- use custom ldoc.css\nkind_names = {topic = \"Manual\"}\nexamples = {\"doc\/examples\"}\n","old_contents":"project = \"lua-cassandra\"\ntitle = \"lua-cassandra documentation\"\ndescription = \"A pure Lua client library for Apache Cassandra (2.x)\"\nreadme = \"doc\/README.md\"\nformat = \"markdown\"\nstyle = true -- use custom ldoc.css\nkind_names={topic = \"Manual\"}\nexamples = {\"doc\/examples\"}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"51abe2a832a4eb5e5312c4a18e79cc4b9d97ec26","subject":"fix linker script bug","message":"fix linker script bug\n\nincorrect name\n","repos":"PDXostc\/can_firewall_software,PDXostc\/can_firewall_software","old_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-avr32\", \"elf32-avr32\",\n\t      \"elf32-avr32\")\nOUTPUT_ARCH(avr32:uc)\nENTRY(_start)\nSEARCH_DIR(\"\/home\/toolsbuild\/jenkins-knuth\/workspace\/avr32-gnu-toolchain\/avr32-gnu-toolchain-win32_x86\/avr32\/lib\");\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY\n{\n    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K-10K-8K\n\t\tFLASHRSVD (rxai!w) : ORIGIN = 0x80000000+512K-10K-8K, LENGTH = 10K\n    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC\n    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512\n    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512\n    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8\n    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8\n}\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;\n\t\/* Next line should not be necessary for use of flash for storing rules *\/\n\t\/* .flash_rsvd : { *(.flash_rsvd) } >FLASHRSVD AT>FLASHRSVD *\/\n  .interp         : { *(.interp) } >FLASH AT>FLASH\n  .reset : {  *(.reset) } >FLASH AT>FLASH\n  .hash           : { *(.hash) } >FLASH AT>FLASH\n  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH\n  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH\n  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH\n  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH\n  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH\n  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH\n  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH\n  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH\n  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH\n  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH\n  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH\n  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH\n  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH\n  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH\n  .init           :\n  {\n    KEEP (*(.init))\n  } >FLASH AT>FLASH =0xd703d703\n  .plt            : { *(.plt) } >FLASH AT>FLASH\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } >FLASH AT>FLASH =0xd703d703\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } >FLASH AT>FLASH =0xd703d703\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH\n  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH\n  .dalign\t: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH\n  PROVIDE (_data = ORIGIN(CPUSRAM));\n  . = ORIGIN(CPUSRAM);\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  PROVIDE (__preinit_array_start = ALIGN(32 \/ 8));\n  .preinit_array     : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >CPUSRAM AT>FLASH\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >CPUSRAM AT>FLASH\n  .jcr            : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH\n  .dynamic        : { *(.dynamic) } >CPUSRAM AT>FLASH\n  .got            : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH\n  .data           :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  } >CPUSRAM AT>FLASH\n  .data1          : { *(.data1) } >CPUSRAM AT>FLASH\n  .balign\t: { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(8);\n  } >CPUSRAM\n  . = ALIGN(8);\n  _end = .;\n  PROVIDE (end = .);\n  __heap_start__ = ALIGN(8);\n  . = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;\n  __heap_end__ = .;\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :\n  {\n    _stack = .;\n    *(.stack)\n    . = _stack_size;\n    _estack = .;\n  } >CPUSRAM\n  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE\n  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE\n\t.flash : { *(.flash .flash.*) } >FLASH AT>FLASH\n\t.flash_rsvd : { *(.flash_rsvd .flash_rsvd.*) } >FLASHRSVD AT>FLASHRSVD\n  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE\n  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-avr32\", \"elf32-avr32\",\n\t      \"elf32-avr32\")\nOUTPUT_ARCH(avr32:uc)\nENTRY(_start)\nSEARCH_DIR(\"\/home\/toolsbuild\/jenkins-knuth\/workspace\/avr32-gnu-toolchain\/avr32-gnu-toolchain-win32_x86\/avr32\/lib\");\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY\n{\n    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K-10K-8K\n\t\tFLASHRSVD (rxai!w) : ORIGIN = 0x80000000+512K-10K-8K, LENGTH = 10K\n    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC\n    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512\n    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512\n    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8\n    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8\n}\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;\n\t\/* Next line should not be necessary for use of flash for storing rules *\/\n\t\/* .flash-rsvd : { *(.flash-rsvd) } >FLASHRSVD AT>FLASHRSVD *\/\n  .interp         : { *(.interp) } >FLASH AT>FLASH\n  .reset : {  *(.reset) } >FLASH AT>FLASH\n  .hash           : { *(.hash) } >FLASH AT>FLASH\n  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH\n  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH\n  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH\n  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH\n  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH\n  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH\n  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH\n  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH\n  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH\n  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH\n  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH\n  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH\n  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH\n  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH\n  .init           :\n  {\n    KEEP (*(.init))\n  } >FLASH AT>FLASH =0xd703d703\n  .plt            : { *(.plt) } >FLASH AT>FLASH\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } >FLASH AT>FLASH =0xd703d703\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } >FLASH AT>FLASH =0xd703d703\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH\n  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH\n  .dalign\t: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH\n  PROVIDE (_data = ORIGIN(CPUSRAM));\n  . = ORIGIN(CPUSRAM);\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  PROVIDE (__preinit_array_start = ALIGN(32 \/ 8));\n  .preinit_array     : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >CPUSRAM AT>FLASH\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >CPUSRAM AT>FLASH\n  .jcr            : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH\n  .dynamic        : { *(.dynamic) } >CPUSRAM AT>FLASH\n  .got            : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH\n  .data           :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  } >CPUSRAM AT>FLASH\n  .data1          : { *(.data1) } >CPUSRAM AT>FLASH\n  .balign\t: { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(8);\n  } >CPUSRAM\n  . = ALIGN(8);\n  _end = .;\n  PROVIDE (end = .);\n  __heap_start__ = ALIGN(8);\n  . = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;\n  __heap_end__ = .;\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :\n  {\n    _stack = .;\n    *(.stack)\n    . = _stack_size;\n    _estack = .;\n  } >CPUSRAM\n  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE\n  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE\n\t.flash : { *(.flash .flash.*) } >FLASH AT>FLASH\n\t.flash-rsvd : { *(.flash-rsvd .flash-rsvd.*) } >FLASHRSVD AT>FLASHRSVD\n  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE\n  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"5162183872f78f787c5e6624e5fef1be955e5caf","subject":"kernel: Delete obsolete h1\/chip_layout.ld","message":"kernel: Delete obsolete h1\/chip_layout.ld\n","repos":"google\/tock-on-titan,google\/tock-on-titan,google\/tock-on-titan","old_file":"kernel\/h1\/chip_layout.ld","new_file":"kernel\/h1\/chip_layout.ld","new_contents":"","old_contents":"\/* Copyright 2018 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nROM_ORIGIN  = 0x44400;\nROM_LENGTH  = 0x20000;\nPROG_ORIGIN = 0x64400;\nPROG_LENGTH = 0x20000;\nRAM_ORIGIN  = 0x10000;\nRAM_LENGTH  = 0x10000;\n\nMPU_MIN_ALIGN=8K;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"58e413afce78e97c37fe97db92e60039e1145344","subject":"cpu\/cc2538: add eh_frame section to the linkerscript","message":"cpu\/cc2538: add eh_frame section to the linkerscript\n\nFixes linker errors on some toolchains, for example:\n  ld: foo.elf section `.eh_frame' will not fit in region `cca'\n  ld: region `cca' overflowed by 40 bytes\n","repos":"marcosalm\/RIOT,DipSwitch\/RIOT,benoit-canet\/RIOT,Lexandro92\/RIOT-CoAP,plushvoxel\/RIOT,Yonezawa-T2\/RIOT,gbarnett\/RIOT,OTAkeys\/RIOT,automote\/RIOT,changbiao\/RIOT,arvindpdmn\/RIOT,jfischer-phytec-iot\/RIOT,Josar\/RIOT,nsol-nmsu\/RIOT,khhhh\/RIOT,authmillenon\/RIOT,adjih\/RIOT,bartfaizoltan\/RIOT,jhollister\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,jferreir\/RIOT,brettswann\/RIOT,gbarnett\/RIOT,centurysys\/RIOT,kushalsingh007\/RIOT,kb2ma\/RIOT,jremmert-phytec-iot\/RIOT,A-Paul\/RIOT,shady33\/RIOT,alex1818\/RIOT,phiros\/RIOT,LudwigKnuepfer\/RIOT,Ell-i\/RIOT,tdautc19841202\/RIOT,phiros\/RIOT,backenklee\/RIOT,EmuxEvans\/RIOT,MohmadAyman\/RIOT,robixnai\/RIOT,Osblouf\/RIOT,ntrtrung\/RIOT,alignan\/RIOT,watr-li\/RIOT,immesys\/RiSyn,adjih\/RIOT,kbumsik\/RIOT,beurdouche\/RIOT,bartfaizoltan\/RIOT,jremmert-phytec-iot\/RIOT,binarylemon\/RIOT,dkm\/RIOT,altairpearl\/RIOT,latsku\/RIOT,ThanhVic\/RIOT,DipSwitch\/RIOT,abp719\/RIOT,automote\/RIOT,miri64\/RIOT,syin2\/RIOT,herrfz\/RIOT,beurdouche\/RIOT,rfswarm\/RIOT,MohmadAyman\/RIOT,ks156\/RIOT,thiagohd\/RIOT,thomaseichinger\/RIOT,LudwigOrtmann\/RIOT,ThanhVic\/RIOT,tdautc19841202\/RIOT,patkan\/RIOT,jfischer-phytec-iot\/RIOT,lazytech-org\/RIOT,altairpearl\/RIOT,l3nko\/RIOT,abkam07\/RIOT,rfuentess\/RIOT,LudwigKnuepfer\/RIOT,thomaseichinger\/RIOT,robixnai\/RIOT,nsol-nmsu\/RIOT,haoyangyu\/RIOT,ThanhVic\/RIOT,smlng\/RIOT,rfswarm\/RIOT,beurdouche\/RIOT,fnack\/RIOT,katezilla\/RIOT,basilfx\/RIOT,smlng\/RIOT,adjih\/RIOT,watr-li\/RIOT,zhuoshuguo\/RIOT,asanka-code\/RIOT,beurdouche\/RIOT,kb2ma\/RIOT,luciotorre\/RIOT,kaleb-himes\/RIOT,gbarnett\/RIOT,marcosalm\/RIOT,jasonatran\/RIOT,adrianghc\/RIOT,MarkXYang\/RIOT,stevenj\/RIOT,malosek\/RIOT,zhuoshuguo\/RIOT,mtausig\/RIOT,dailab\/RIOT,LudwigKnuepfer\/RIOT,alex1818\/RIOT,gebart\/RIOT,patkan\/RIOT,OTAkeys\/RIOT,RubikonAlpha\/RIOT,adrianghc\/RIOT,zhuoshuguo\/RIOT,centurysys\/RIOT,dhruvvyas90\/RIOT,LudwigOrtmann\/RIOT,changbiao\/RIOT,AnonMall\/RIOT,kYc0o\/RIOT,abp719\/RIOT,khhhh\/RIOT,MonsterCode8000\/RIOT,koenning\/RIOT,AnonMall\/RIOT,automote\/RIOT,lebrush\/RIOT,beurdouche\/RIOT,altairpearl\/RIOT,lazytech-org\/RIOT,msolters\/RIOT,malosek\/RIOT,sgso\/RIOT,1blankz7\/RIOT,mtausig\/RIOT,dkm\/RIOT,jbeyerstedt\/RIOT-OTA-update,benoit-canet\/RIOT,biboc\/RIOT,ximus\/RIOT,syin2\/RIOT,attdona\/RIOT,jremmert-phytec-iot\/RIOT,toonst\/RIOT,abp719\/RIOT,gebart\/RIOT,haoyangyu\/RIOT,RIOT-OS\/RIOT,kushalsingh007\/RIOT,dhruvvyas90\/RIOT,tfar\/RIOT,rakendrathapa\/RIOT,biboc\/RIOT,kbumsik\/RIOT,x3ro\/RIOT,tfar\/RIOT,MarkXYang\/RIOT,toonst\/RIOT,ximus\/RIOT,watr-li\/RIOT,tdautc19841202\/RIOT,kb2ma\/RIOT,gautric\/RIOT,BytesGalore\/RIOT,daniel-k\/RIOT,MohmadAyman\/RIOT,JensErdmann\/RIOT,changbiao\/RIOT,jremmert-phytec-iot\/RIOT,sgso\/RIOT,openkosmosorg\/RIOT,jremmert-phytec-iot\/RIOT,Yonezawa-T2\/RIOT,centurysys\/RIOT,sumanpanchal\/RIOT,ntrtrung\/RIOT,Osblouf\/RIOT,jhollister\/RIOT,herrfz\/RIOT,rakendrathapa\/RIOT,msolters\/RIOT,rfswarm2\/RIOT,gbarnett\/RIOT,brettswann\/RIOT,backenklee\/RIOT,cladmi\/RIOT,kerneltask\/RIOT,Josar\/RIOT,adrianghc\/RIOT,sgso\/RIOT,rfswarm2\/RIOT,FrancescoErmini\/RIOT,toonst\/RIOT,katezilla\/RIOT,sgso\/RIOT,JensErdmann\/RIOT,LudwigOrtmann\/RIOT,arvindpdmn\/RIOT,avmelnikoff\/RIOT,khhhh\/RIOT,mtausig\/RIOT,Lexandro92\/RIOT-CoAP,alex1818\/RIOT,JensErdmann\/RIOT,stevenj\/RIOT,basilfx\/RIOT,fnack\/RIOT,daniel-k\/RIOT,dailab\/RIOT,Ell-i\/RIOT,bartfaizoltan\/RIOT,thiagohd\/RIOT,herrfz\/RIOT-old,tdautc19841202\/RIOT,basilfx\/RIOT,dkm\/RIOT,rakendrathapa\/RIOT,Osblouf\/RIOT,stevenj\/RIOT,d00616\/RIOT,daniel-k\/RIOT,thomaseichinger\/RIOT,jbeyerstedt\/RIOT-OTA-update,Darredevil\/RIOT,kerneltask\/RIOT,kerneltask\/RIOT,hamilton-mote\/RIOT-OS,roberthartung\/RIOT,daniel-k\/RIOT,marcosalm\/RIOT,l3nko\/RIOT,asanka-code\/RIOT,ThanhVic\/RIOT,d00616\/RIOT,lebrush\/RIOT,jhollister\/RIOT,chris-wood\/RIOT,jbeyerstedt\/RIOT-OTA-update,MonsterCode8000\/RIOT,alex1818\/RIOT,jfischer-phytec-iot\/RIOT,abp719\/RIOT,nsol-nmsu\/RIOT,openkosmosorg\/RIOT,avmelnikoff\/RIOT,jasonatran\/RIOT,gebart\/RIOT,wentaoshang\/RIOT,Josar\/RIOT,tfar\/RIOT,gautric\/RIOT,malosek\/RIOT,robixnai\/RIOT,ant9000\/RIOT,RubikonAlpha\/RIOT,1blankz7\/RIOT,herrfz\/RIOT,centurysys\/RIOT,kYc0o\/RIOT,patkan\/RIOT,mfrey\/RIOT,attdona\/RIOT,1blankz7\/RIOT,plushvoxel\/RIOT,rakendrathapa\/RIOT,PSHIVANI\/Riot-Code,chris-wood\/RIOT,daniel-k\/RIOT,wentaoshang\/RIOT,biboc\/RIOT,brettswann\/RIOT,RBartz\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,1blankz7\/RIOT,jbeyerstedt\/RIOT-OTA-update,josephnoir\/RIOT,luciotorre\/RIOT,rfswarm2\/RIOT,kerneltask\/RIOT,alignan\/RIOT,yogo1212\/RIOT,wentaoshang\/RIOT,bartfaizoltan\/RIOT,neiljay\/RIOT,Yonezawa-T2\/RIOT,benoit-canet\/RIOT,1blankz7\/RIOT,koenning\/RIOT,kb2ma\/RIOT,smlng\/RIOT,immesys\/RiSyn,dkm\/RIOT,chris-wood\/RIOT,msolters\/RIOT,Hyungsin\/RIOT-OS,dhruvvyas90\/RIOT,neumodisch\/RIOT,hamilton-mote\/RIOT-OS,dailab\/RIOT,khhhh\/RIOT,thomaseichinger\/RIOT,lazytech-org\/RIOT,Ell-i\/RIOT,ximus\/RIOT,Lexandro92\/RIOT-CoAP,latsku\/RIOT,Darredevil\/RIOT,koenning\/RIOT,basilfx\/RIOT,neiljay\/RIOT,adjih\/RIOT,koenning\/RIOT,binarylemon\/RIOT,thiagohd\/RIOT,miri64\/RIOT,attdona\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,neumodisch\/RIOT,rfuentess\/RIOT,mziegert\/RIOT,rakendrathapa\/RIOT,lazytech-org\/RIOT,biboc\/RIOT,josephnoir\/RIOT,Hyungsin\/RIOT-OS,gebart\/RIOT,biboc\/RIOT,DipSwitch\/RIOT,kYc0o\/RIOT,altairpearl\/RIOT,OlegHahm\/RIOT,marcosalm\/RIOT,sumanpanchal\/RIOT,avmelnikoff\/RIOT,x3ro\/RIOT,aeneby\/RIOT,herrfz\/RIOT-old,MonsterCode8000\/RIOT,herrfz\/RIOT-old,mziegert\/RIOT,plushvoxel\/RIOT,abkam07\/RIOT,l3nko\/RIOT,MarkXYang\/RIOT,dhruvvyas90\/RIOT,gautric\/RIOT,rousselk\/RIOT,bartfaizoltan\/RIOT,mfrey\/RIOT,EmuxEvans\/RIOT,roberthartung\/RIOT,RubikonAlpha\/RIOT,mfrey\/RIOT,ThanhVic\/RIOT,AnonMall\/RIOT,kaspar030\/RIOT,shady33\/RIOT,asanka-code\/RIOT,lebrush\/RIOT,ks156\/RIOT,Lexandro92\/RIOT-CoAP,MohmadAyman\/RIOT,binarylemon\/RIOT,Yonezawa-T2\/RIOT,BytesGalore\/RIOT,attdona\/RIOT,watr-li\/RIOT,kushalsingh007\/RIOT,lebrush\/RIOT,cladmi\/RIOT,alex1818\/RIOT,TobiasFredersdorf\/RIOT,Osblouf\/RIOT,d00616\/RIOT,malosek\/RIOT,A-Paul\/RIOT,avmelnikoff\/RIOT,miri64\/RIOT,EmuxEvans\/RIOT,PSHIVANI\/Riot-Code,RubikonAlpha\/RIOT,thiagohd\/RIOT,kb2ma\/RIOT,abkam07\/RIOT,A-Paul\/RIOT,authmillenon\/RIOT,robixnai\/RIOT,MonsterCode8000\/RIOT,backenklee\/RIOT,marcosalm\/RIOT,robixnai\/RIOT,syin2\/RIOT,EmuxEvans\/RIOT,katezilla\/RIOT,fnack\/RIOT,luciotorre\/RIOT,sumanpanchal\/RIOT,ximus\/RIOT,kaspar030\/RIOT,rfswarm2\/RIOT,latsku\/RIOT,authmillenon\/RIOT,khhhh\/RIOT,kaleb-himes\/RIOT,rajma996\/RIOT,sumanpanchal\/RIOT,RBartz\/RIOT,bartfaizoltan\/RIOT,shady33\/RIOT,smlng\/RIOT,gbarnett\/RIOT,shady33\/RIOT,roberthartung\/RIOT,aeneby\/RIOT,alex1818\/RIOT,toonst\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,OlegHahm\/RIOT,haoyangyu\/RIOT,PSHIVANI\/Riot-Code,alignan\/RIOT,openkosmosorg\/RIOT,OTAkeys\/RIOT,phiros\/RIOT,l3nko\/RIOT,authmillenon\/RIOT,dkm\/RIOT,neumodisch\/RIOT,mziegert\/RIOT,OTAkeys\/RIOT,robixnai\/RIOT,automote\/RIOT,backenklee\/RIOT,sgso\/RIOT,d00616\/RIOT,phiros\/RIOT,x3ro\/RIOT,binarylemon\/RIOT,neiljay\/RIOT,jferreir\/RIOT,cladmi\/RIOT,haoyangyu\/RIOT,AnonMall\/RIOT,phiros\/RIOT,stevenj\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,immesys\/RiSyn,malosek\/RIOT,hamilton-mote\/RIOT-OS,Osblouf\/RIOT,PSHIVANI\/Riot-Code,JensErdmann\/RIOT,immesys\/RiSyn,immesys\/RiSyn,A-Paul\/RIOT,asanka-code\/RIOT,zhuoshuguo\/RIOT,miri64\/RIOT,rfswarm2\/RIOT,luciotorre\/RIOT,thiagohd\/RIOT,josephnoir\/RIOT,roberthartung\/RIOT,neiljay\/RIOT,rajma996\/RIOT,LudwigKnuepfer\/RIOT,wentaoshang\/RIOT,EmuxEvans\/RIOT,aeneby\/RIOT,kushalsingh007\/RIOT,ntrtrung\/RIOT,Darredevil\/RIOT,altairpearl\/RIOT,mtausig\/RIOT,arvindpdmn\/RIOT,RubikonAlpha\/RIOT,attdona\/RIOT,arvindpdmn\/RIOT,chris-wood\/RIOT,TobiasFredersdorf\/RIOT,herrfz\/RIOT,DipSwitch\/RIOT,changbiao\/RIOT,benoit-canet\/RIOT,changbiao\/RIOT,alignan\/RIOT,openkosmosorg\/RIOT,OlegHahm\/RIOT,Ell-i\/RIOT,mtausig\/RIOT,changbiao\/RIOT,toonst\/RIOT,MonsterCode8000\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,brettswann\/RIOT,l3nko\/RIOT,RBartz\/RIOT,PSHIVANI\/Riot-Code,MarkXYang\/RIOT,mziegert\/RIOT,malosek\/RIOT,binarylemon\/RIOT,altairpearl\/RIOT,syin2\/RIOT,rousselk\/RIOT,kaspar030\/RIOT,Osblouf\/RIOT,openkosmosorg\/RIOT,centurysys\/RIOT,ximus\/RIOT,RIOT-OS\/RIOT,zhuoshuguo\/RIOT,gautric\/RIOT,dailab\/RIOT,aeneby\/RIOT,basilfx\/RIOT,abp719\/RIOT,msolters\/RIOT,FrancescoErmini\/RIOT,jfischer-phytec-iot\/RIOT,daniel-k\/RIOT,jhollister\/RIOT,shady33\/RIOT,jhollister\/RIOT,PSHIVANI\/Riot-Code,dhruvvyas90\/RIOT,sumanpanchal\/RIOT,Hyungsin\/RIOT-OS,kbumsik\/RIOT,neumodisch\/RIOT,roberthartung\/RIOT,Hyungsin\/RIOT-OS,MarkXYang\/RIOT,chris-wood\/RIOT,jferreir\/RIOT,FrancescoErmini\/RIOT,ant9000\/RIOT,l3nko\/RIOT,gebart\/RIOT,rfuentess\/RIOT,kaleb-himes\/RIOT,kushalsingh007\/RIOT,abkam07\/RIOT,cladmi\/RIOT,arvindpdmn\/RIOT,JensErdmann\/RIOT,herrfz\/RIOT,shady33\/RIOT,patkan\/RIOT,katezilla\/RIOT,haoyangyu\/RIOT,ant9000\/RIOT,tfar\/RIOT,RBartz\/RIOT,abkam07\/RIOT,rajma996\/RIOT,kaspar030\/RIOT,luciotorre\/RIOT,kbumsik\/RIOT,ks156\/RIOT,haoyangyu\/RIOT,cladmi\/RIOT,wentaoshang\/RIOT,rajma996\/RIOT,lebrush\/RIOT,d00616\/RIOT,A-Paul\/RIOT,attdona\/RIOT,luciotorre\/RIOT,ant9000\/RIOT,kushalsingh007\/RIOT,avmelnikoff\/RIOT,yogo1212\/RIOT,kYc0o\/RIOT,jhollister\/RIOT,LudwigKnuepfer\/RIOT,msolters\/RIOT,watr-li\/RIOT,OlegHahm\/RIOT,brettswann\/RIOT,sgso\/RIOT,smlng\/RIOT,FrancescoErmini\/RIOT,mziegert\/RIOT,khhhh\/RIOT,sumanpanchal\/RIOT,benoit-canet\/RIOT,RBartz\/RIOT,RIOT-OS\/RIOT,phiros\/RIOT,Darredevil\/RIOT,patkan\/RIOT,mziegert\/RIOT,aeneby\/RIOT,d00616\/RIOT,x3ro\/RIOT,tdautc19841202\/RIOT,TobiasFredersdorf\/RIOT,lebrush\/RIOT,latsku\/RIOT,jferreir\/RIOT,watr-li\/RIOT,1blankz7\/RIOT,plushvoxel\/RIOT,EmuxEvans\/RIOT,lazytech-org\/RIOT,tfar\/RIOT,neumodisch\/RIOT,LudwigOrtmann\/RIOT,kaleb-himes\/RIOT,RubikonAlpha\/RIOT,binarylemon\/RIOT,yogo1212\/RIOT,RIOT-OS\/RIOT,ntrtrung\/RIOT,ThanhVic\/RIOT,thiagohd\/RIOT,ntrtrung\/RIOT,tdautc19841202\/RIOT,fnack\/RIOT,automote\/RIOT,jferreir\/RIOT,yogo1212\/RIOT,josephnoir\/RIOT,kYc0o\/RIOT,Darredevil\/RIOT,asanka-code\/RIOT,Ell-i\/RIOT,rajma996\/RIOT,FrancescoErmini\/RIOT,Josar\/RIOT,hamilton-mote\/RIOT-OS,rousselk\/RIOT,authmillenon\/RIOT,AnonMall\/RIOT,BytesGalore\/RIOT,koenning\/RIOT,rfswarm\/RIOT,plushvoxel\/RIOT,gautric\/RIOT,jferreir\/RIOT,AnonMall\/RIOT,wentaoshang\/RIOT,marcosalm\/RIOT,fnack\/RIOT,MonsterCode8000\/RIOT,mfrey\/RIOT,RIOT-OS\/RIOT,ks156\/RIOT,zhuoshuguo\/RIOT,kbumsik\/RIOT,rfswarm2\/RIOT,mfrey\/RIOT,herrfz\/RIOT,kaleb-himes\/RIOT,nsol-nmsu\/RIOT,hamilton-mote\/RIOT-OS,DipSwitch\/RIOT,kerneltask\/RIOT,OTAkeys\/RIOT,latsku\/RIOT,jbeyerstedt\/RIOT-OTA-update,jasonatran\/RIOT,Lexandro92\/RIOT-CoAP,nsol-nmsu\/RIOT,stevenj\/RIOT,RBartz\/RIOT,ant9000\/RIOT,herrfz\/RIOT-old,rajma996\/RIOT,TobiasFredersdorf\/RIOT,openkosmosorg\/RIOT,stevenj\/RIOT,patkan\/RIOT,katezilla\/RIOT,kaspar030\/RIOT,Hyungsin\/RIOT-OS,Darredevil\/RIOT,adrianghc\/RIOT,neumodisch\/RIOT,rfswarm\/RIOT,asanka-code\/RIOT,Lexandro92\/RIOT-CoAP,abp719\/RIOT,rousselk\/RIOT,BytesGalore\/RIOT,rfuentess\/RIOT,dhruvvyas90\/RIOT,authmillenon\/RIOT,adrianghc\/RIOT,josephnoir\/RIOT,rakendrathapa\/RIOT,MarkXYang\/RIOT,x3ro\/RIOT,MohmadAyman\/RIOT,brettswann\/RIOT,rfuentess\/RIOT,FrancescoErmini\/RIOT,latsku\/RIOT,BytesGalore\/RIOT,DipSwitch\/RIOT,gbarnett\/RIOT,miri64\/RIOT,Josar\/RIOT,backenklee\/RIOT,rfswarm\/RIOT,TobiasFredersdorf\/RIOT,jremmert-phytec-iot\/RIOT,koenning\/RIOT,rousselk\/RIOT,neiljay\/RIOT,ks156\/RIOT,rousselk\/RIOT,LudwigOrtmann\/RIOT,LudwigOrtmann\/RIOT,alignan\/RIOT,adjih\/RIOT,jasonatran\/RIOT,syin2\/RIOT,dailab\/RIOT,automote\/RIOT,MohmadAyman\/RIOT,herrfz\/RIOT-old,JensErdmann\/RIOT,jfischer-phytec-iot\/RIOT,benoit-canet\/RIOT,fnack\/RIOT,Yonezawa-T2\/RIOT,abkam07\/RIOT,immesys\/RiSyn,arvindpdmn\/RIOT,yogo1212\/RIOT,thomaseichinger\/RIOT,ntrtrung\/RIOT,centurysys\/RIOT,jasonatran\/RIOT,Yonezawa-T2\/RIOT,ximus\/RIOT,rfswarm\/RIOT,chris-wood\/RIOT,msolters\/RIOT","old_file":"cpu\/cc2538\/cc2538_linkerscript.ld","new_file":"cpu\/cc2538\/cc2538_linkerscript.ld","new_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Define the default stack size for interrupt mode. As no context is\n   saved on this stack and ISRs are supposed to be short, it can be fairly\n   small. 512 byte should be a save assumption here *\/\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x200; \/* 512 byte *\/\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    .flashcca :\n    {\n        KEEP(*(.flashcca))\n    } > cca\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Define the default stack size for interrupt mode. As no context is\n   saved on this stack and ISRs are supposed to be short, it can be fairly\n   small. 512 byte should be a save assumption here *\/\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x200; \/* 512 byte *\/\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    .flashcca :\n    {\n        KEEP(*(.flashcca))\n    } > cca\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"87e06756a59bf51fa7dc7ac2aab14d3137ca155c","subject":"cortexm_common: move the stack to the bottom of RAM","message":"cortexm_common: move the stack to the bottom of RAM\n","repos":"kerneltask\/RIOT,kaleb-himes\/RIOT,backenklee\/RIOT,avmelnikoff\/RIOT,rajma996\/RIOT,OTAkeys\/RIOT,altairpearl\/RIOT,adrianghc\/RIOT,jfischer-phytec-iot\/RIOT,gebart\/RIOT,beurdouche\/RIOT,altairpearl\/RIOT,immesys\/RiSyn,plushvoxel\/RIOT,jfischer-phytec-iot\/RIOT,thomaseichinger\/RIOT,smlng\/RIOT,adrianghc\/RIOT,kb2ma\/RIOT,brettswann\/RIOT,adrianghc\/RIOT,gautric\/RIOT,d00616\/RIOT,kerneltask\/RIOT,cladmi\/RIOT,neumodisch\/RIOT,kb2ma\/RIOT,hamilton-mote\/RIOT-OS,lazytech-org\/RIOT,gautric\/RIOT,kaspar030\/RIOT,katezilla\/RIOT,wentaoshang\/RIOT,jremmert-phytec-iot\/RIOT,cladmi\/RIOT,tfar\/RIOT,authmillenon\/RIOT,adjih\/RIOT,jremmert-phytec-iot\/RIOT,gautric\/RIOT,A-Paul\/RIOT,neumodisch\/RIOT,backenklee\/RIOT,immesys\/RiSyn,jbeyerstedt\/RIOT-OTA-update,ant9000\/RIOT,jremmert-phytec-iot\/RIOT,lazytech-org\/RIOT,Ell-i\/RIOT,kerneltask\/RIOT,tfar\/RIOT,biboc\/RIOT,toonst\/RIOT,backenklee\/RIOT,tfar\/RIOT,katezilla\/RIOT,x3ro\/RIOT,altairpearl\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,TobiasFredersdorf\/RIOT,backenklee\/RIOT,jasonatran\/RIOT,ks156\/RIOT,gautric\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,Josar\/RIOT,wentaoshang\/RIOT,aeneby\/RIOT,hamilton-mote\/RIOT-OS,rfuentess\/RIOT,josephnoir\/RIOT,kbumsik\/RIOT,adjih\/RIOT,wentaoshang\/RIOT,roberthartung\/RIOT,Ell-i\/RIOT,Ell-i\/RIOT,syin2\/RIOT,toonst\/RIOT,d00616\/RIOT,Hyungsin\/RIOT-OS,thomaseichinger\/RIOT,dkm\/RIOT,kYc0o\/RIOT,neumodisch\/RIOT,gebart\/RIOT,rajma996\/RIOT,miri64\/RIOT,neumodisch\/RIOT,jremmert-phytec-iot\/RIOT,LudwigKnuepfer\/RIOT,ks156\/RIOT,rfuentess\/RIOT,gebart\/RIOT,jasonatran\/RIOT,jbeyerstedt\/RIOT-OTA-update,josephnoir\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,katezilla\/RIOT,RIOT-OS\/RIOT,plushvoxel\/RIOT,d00616\/RIOT,A-Paul\/RIOT,mtausig\/RIOT,plushvoxel\/RIOT,rfuentess\/RIOT,Josar\/RIOT,lazytech-org\/RIOT,lazytech-org\/RIOT,beurdouche\/RIOT,kbumsik\/RIOT,jfischer-phytec-iot\/RIOT,lazytech-org\/RIOT,syin2\/RIOT,LudwigOrtmann\/RIOT,LudwigOrtmann\/RIOT,d00616\/RIOT,ant9000\/RIOT,alignan\/RIOT,avmelnikoff\/RIOT,LudwigOrtmann\/RIOT,x3ro\/RIOT,dkm\/RIOT,adrianghc\/RIOT,thomaseichinger\/RIOT,katezilla\/RIOT,rajma996\/RIOT,d00616\/RIOT,kYc0o\/RIOT,toonst\/RIOT,yogo1212\/RIOT,biboc\/RIOT,cladmi\/RIOT,plushvoxel\/RIOT,TobiasFredersdorf\/RIOT,yogo1212\/RIOT,dkm\/RIOT,avmelnikoff\/RIOT,avmelnikoff\/RIOT,syin2\/RIOT,kaspar030\/RIOT,brettswann\/RIOT,kb2ma\/RIOT,ant9000\/RIOT,authmillenon\/RIOT,altairpearl\/RIOT,miri64\/RIOT,neumodisch\/RIOT,A-Paul\/RIOT,x3ro\/RIOT,biboc\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,d00616\/RIOT,backenklee\/RIOT,OlegHahm\/RIOT,tfar\/RIOT,biboc\/RIOT,thomaseichinger\/RIOT,BytesGalore\/RIOT,OTAkeys\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,neiljay\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,basilfx\/RIOT,immesys\/RiSyn,kaleb-himes\/RIOT,rajma996\/RIOT,kerneltask\/RIOT,beurdouche\/RIOT,mfrey\/RIOT,x3ro\/RIOT,yogo1212\/RIOT,neiljay\/RIOT,authmillenon\/RIOT,OlegHahm\/RIOT,ks156\/RIOT,OTAkeys\/RIOT,aeneby\/RIOT,neiljay\/RIOT,kaleb-himes\/RIOT,LudwigOrtmann\/RIOT,mtausig\/RIOT,yogo1212\/RIOT,adjih\/RIOT,alignan\/RIOT,dailab\/RIOT,plushvoxel\/RIOT,mtausig\/RIOT,tfar\/RIOT,adrianghc\/RIOT,rajma996\/RIOT,syin2\/RIOT,immesys\/RiSyn,kaleb-himes\/RIOT,miri64\/RIOT,roberthartung\/RIOT,A-Paul\/RIOT,LudwigKnuepfer\/RIOT,kYc0o\/RIOT,BytesGalore\/RIOT,biboc\/RIOT,rfuentess\/RIOT,alignan\/RIOT,mfrey\/RIOT,authmillenon\/RIOT,hamilton-mote\/RIOT-OS,dailab\/RIOT,gebart\/RIOT,josephnoir\/RIOT,kaleb-himes\/RIOT,smlng\/RIOT,jbeyerstedt\/RIOT-OTA-update,Ell-i\/RIOT,kaspar030\/RIOT,Hyungsin\/RIOT-OS,aeneby\/RIOT,dailab\/RIOT,x3ro\/RIOT,kaspar030\/RIOT,Hyungsin\/RIOT-OS,A-Paul\/RIOT,gautric\/RIOT,LudwigKnuepfer\/RIOT,LudwigKnuepfer\/RIOT,josephnoir\/RIOT,mfrey\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,cladmi\/RIOT,brettswann\/RIOT,brettswann\/RIOT,BytesGalore\/RIOT,hamilton-mote\/RIOT-OS,roberthartung\/RIOT,kbumsik\/RIOT,wentaoshang\/RIOT,avmelnikoff\/RIOT,adjih\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,miri64\/RIOT,BytesGalore\/RIOT,alignan\/RIOT,rfuentess\/RIOT,RIOT-OS\/RIOT,Hyungsin\/RIOT-OS,wentaoshang\/RIOT,basilfx\/RIOT,LudwigOrtmann\/RIOT,ant9000\/RIOT,smlng\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,brettswann\/RIOT,TobiasFredersdorf\/RIOT,kerneltask\/RIOT,smlng\/RIOT,rajma996\/RIOT,alignan\/RIOT,dkm\/RIOT,BytesGalore\/RIOT,gebart\/RIOT,LudwigOrtmann\/RIOT,LudwigKnuepfer\/RIOT,Josar\/RIOT,mfrey\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,neumodisch\/RIOT,jasonatran\/RIOT,Ell-i\/RIOT,smlng\/RIOT,basilfx\/RIOT,beurdouche\/RIOT,neiljay\/RIOT,neiljay\/RIOT,jbeyerstedt\/RIOT-OTA-update,authmillenon\/RIOT,brettswann\/RIOT,dailab\/RIOT,TobiasFredersdorf\/RIOT,jbeyerstedt\/RIOT-OTA-update,Hyungsin\/RIOT-OS,kb2ma\/RIOT,roberthartung\/RIOT,altairpearl\/RIOT,Josar\/RIOT,dailab\/RIOT,TobiasFredersdorf\/RIOT,toonst\/RIOT,immesys\/RiSyn,beurdouche\/RIOT,jremmert-phytec-iot\/RIOT,altairpearl\/RIOT,mtausig\/RIOT,jremmert-phytec-iot\/RIOT,kbumsik\/RIOT,adjih\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,katezilla\/RIOT,kb2ma\/RIOT,Josar\/RIOT,RIOT-OS\/RIOT,thomaseichinger\/RIOT,roberthartung\/RIOT,dkm\/RIOT,cladmi\/RIOT,toonst\/RIOT,basilfx\/RIOT,jfischer-phytec-iot\/RIOT,aeneby\/RIOT,aeneby\/RIOT,mfrey\/RIOT,ks156\/RIOT,OTAkeys\/RIOT,syin2\/RIOT,kbumsik\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,kaspar030\/RIOT,wentaoshang\/RIOT,ant9000\/RIOT,authmillenon\/RIOT,josephnoir\/RIOT,hamilton-mote\/RIOT-OS,mtausig\/RIOT,immesys\/RiSyn,ks156\/RIOT,jfischer-phytec-iot\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information abour ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information abour ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"348a7a6be9fa8e2f0e5442bb27a5a3bbb6e4bad2","subject":"Stop-gap fix to linker script to accomodate C++ linker sectioning.","message":"Stop-gap fix to linker script to accomodate C++ linker sectioning.\n","repos":"scott-linder\/pios,scott-linder\/pios","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"\/* \n * Kernel linker script \n *\n * This is largely cherry-picked from the Linux kernel sources and the\n * \"Baking Pi\" tutorial series by the University of Cambridge\n *\n * XXX: There is probably a lot left to be desired in here, but as long as it\n * gets us a working kernel it is fine for now.\n *\n * Authors:\n *  Scott Linder\n *\/\n\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS {\n\n    . = 0;\n    .init 0x0000 : {\n        *(.init)\n    }\n\n    \/* Space for ATAGS and stack here *\/\n\n    .text 0x8000 : {\n        *(.text)\n        *(.text.*)\n    }\n\n    .rodata : {\n        *(.rodata)\n    }\n\n    .data : {\n        *(.data)\n    }\n\n    \/DISCARD\/ : {\n        *(*)\n    }\n}\n","old_contents":"\/* \n * Kernel linker script \n *\n * This is largely cherry-picked from the Linux kernel sources and the\n * \"Baking Pi\" tutorial series by the University of Cambridge\n *\n * XXX: There is probably a lot left to be desired in here, but as long as it\n * gets us a working kernel it is fine for now.\n *\n * Authors:\n *  Scott Linder\n *\/\n\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS {\n\n    . = 0;\n    .init 0x0000 : {\n        *(.init)\n    }\n\n    \/* Space for ATAGS and stack here *\/\n\n    .text 0x8000 : {\n        *(.text)\n    }\n\n    .rodata : {\n        *(.rodata)\n    }\n\n    .data : {\n        *(.data)\n    }\n\n    \/DISCARD\/ : {\n        *(*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"1c0ffe453f213af16ab28f1d43618ad4f963ffa6","subject":"Cleanup userland_generic.ld","message":"Cleanup userland_generic.ld\n\nCleaned up a few of the comments, removed unused symbols and...\nimprotantly... made sure the text segment ends on a 4-byte aligned\nboundary. RODATA can be non-word aligned (e.g. if there is an odd-sized\nstring), and if there's nothing to align it afterwards, it can end up\nplacing the RAM sections in non-word-aligned flash. On Cortex-M0 this\ncauses a fault when doing relocation since Cortex-M0 can only do\nword-aligned memory loads.\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n\n    \/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n    } > SRAM\n\n    \/*\n     * __NOTE__: The following symbols are used only to hint to elf2tbf how much\n     * total memory to request from the OS.\n     *\/\n    .stack :\n    {\n        . += STACK_SIZE;\n    } > SRAM\n\n    .app_heap :\n    {\n        . += APP_HEAP_SIZE;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        . += KERNEL_HEAP_SIZE;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_sbss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n    } > FLASH =0xFF\n\n\n\/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    _sbss = .;\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += STACK_SIZE;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += APP_HEAP_SIZE;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += KERNEL_HEAP_SIZE;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"28f10f80ee7e56eb777c60acc0164930476bda05","subject":"Specify ram limit to prevent overflow","message":"Specify ram limit to prevent overflow\n","repos":"alexchandel\/rustboot,perlun\/rustboot,pczarn\/rustboot,wbthomason\/ironkernel","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(start)\nOUTPUT_FORMAT(binary)\n\nMEMORY {\n    ram : org = 0x7e00, l = 32K\n}\n\nSECTIONS {\n    . = 0x7e00;\n\n    .text : {\n        runtime.o(.text)\n        *(.text)\n        *(.gnu.linkonce.t*)\n    } >ram\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.eh_frame)\n        *(.rel.eh_frame)\n    }\n}\n","old_contents":"ENTRY(start)\nOUTPUT_FORMAT(binary)\n\nSECTIONS {\n    . = 0x7e00;\n\n    .text : {\n        runtime.o(.text)\n        *(.text)\n        *(.gnu.linkonce.t*)\n    }\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.eh_frame)\n        *(.rel.eh_frame)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"6a1d4676a6657a83e0f5c3f76bee0e9af8b658e1","subject":"x86: Make selection of address of NDKS in linker script between PAE and normal paging nicer","message":"x86: Make selection of address of NDKS in linker script between PAE and normal paging nicer\n","repos":"zhicheng\/seL4,cmr\/seL4,zhicheng\/seL4,zhicheng\/seL4,cmr\/seL4,cmr\/seL4","old_file":"src\/plat\/pc99\/linker.lds","new_file":"src\/plat\/pc99\/linker.lds","new_contents":"\/*\n * Copyright 2014, General Dynamics C4 Systems\n *\n * This software may be distributed and modified according to the terms of\n * the GNU General Public License version 2. Note that NO WARRANTY is provided.\n * See \"LICENSE_GPLv2.txt\" for details.\n *\n * @TAG(GD_GPL)\n *\/\n\n#include <config.h>\n\nENTRY(_start)\n\n\/* WARNING: constants also defined in plat\/machine\/hardware.h *\/\nPADDR_BASE = 0x00000000;\nPADDR_LOAD = 0x00100000;\nKERNEL_BASE  = 0xe0000000;\nKERNEL_OFFSET = KERNEL_BASE - PADDR_BASE;\n#ifdef CONFIG_PAE_PAGING\nNDKS_BASE = 0xffe01000;\n#else\nNDKS_BASE = 0xffc01000;\n#endif\n\nSECTIONS\n{\n    \/* load kernel to 1M to avoid the famous IA-32 memory holes below *\/\n    . = PADDR_LOAD;\n\n    \/* code\/data only needed during bootstrapping, linked to physical addresses *\/\n\n    .phys . :\n    {\n        *(.mbh)\n        *(.phys.text)\n        _boot_stack_bottom = .;\n        . = . + 2K;\n        . = ALIGN(4K);\n        _boot_stack_top = .;\n        *(.phys)\n        *(.phys.*)\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .boot . : AT(ADDR(.boot) - KERNEL_OFFSET)\n    {\n        *(.boot.text)\n        *(.boot.glob)\n        . = ALIGN(4K);\n    }\n\n    ki_boot_end = .;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        *(.text)\n    }\n\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .glob . : AT(ADDR(.glob) - KERNEL_OFFSET)\n    {\n        *(.glob)\n    }\n    \n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n    }\n\n    . = ALIGN(4K);\n    ki_end = .;\n\n    \/* The NDKS section is allocated and mapped per node in boot_sys.c *\/\n\n    .ndks NDKS_BASE (DSECT) :\n    {\n        _ndks_start = .;\n\n        \/*\n         * Due to stupid ld behaviour, we can't simply allocate the stack here\n         * using \". = . + ALIGN(4K)\" because that makes .ndks appear in the\n         * program headers of the ELF file (which is wrong).\n         *\n         * Instead, we define the stack in C in the .ndks.stack section, which\n         * makes it appear here.\n         *\/\n        _kernel_stack_bottom = .;\n        *(.ndks.stack)\n        _kernel_stack_top = .;\n\n        *(.boot.node)\n        *(.bss)\n        *(COMMON)\n        _ndks_end = .;\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n    }\n}\n","old_contents":"\/*\n * Copyright 2014, General Dynamics C4 Systems\n *\n * This software may be distributed and modified according to the terms of\n * the GNU General Public License version 2. Note that NO WARRANTY is provided.\n * See \"LICENSE_GPLv2.txt\" for details.\n *\n * @TAG(GD_GPL)\n *\/\n\n#include <config.h>\n\nENTRY(_start)\n\n\/* WARNING: constants also defined in plat\/machine\/hardware.h *\/\nPADDR_BASE = 0x00000000;\nPADDR_LOAD = 0x00100000;\nKERNEL_BASE  = 0xe0000000;\nKERNEL_OFFSET = KERNEL_BASE - PADDR_BASE;\n\nSECTIONS\n{\n    \/* load kernel to 1M to avoid the famous IA-32 memory holes below *\/\n    . = PADDR_LOAD;\n\n    \/* code\/data only needed during bootstrapping, linked to physical addresses *\/\n\n    .phys . :\n    {\n        *(.mbh)\n        *(.phys.text)\n        _boot_stack_bottom = .;\n        . = . + 2K;\n        . = ALIGN(4K);\n        _boot_stack_top = .;\n        *(.phys)\n        *(.phys.*)\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .boot . : AT(ADDR(.boot) - KERNEL_OFFSET)\n    {\n        *(.boot.text)\n        *(.boot.glob)\n        . = ALIGN(4K);\n    }\n\n    ki_boot_end = .;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        *(.text)\n    }\n\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .glob . : AT(ADDR(.glob) - KERNEL_OFFSET)\n    {\n        *(.glob)\n    }\n    \n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n    }\n\n    . = ALIGN(4K);\n    ki_end = .;\n\n    \/* The NDKS section is allocated and mapped per node in boot_sys.c *\/\n\n#ifdef CONFIG_PAE_PAGING\n    .ndks 0xffe01000 (DSECT) :\n#else\n    .ndks 0xffc01000 (DSECT) :\n#endif\n    {\n        _ndks_start = .;\n\n        \/*\n         * Due to stupid ld behaviour, we can't simply allocate the stack here\n         * using \". = . + ALIGN(4K)\" because that makes .ndks appear in the\n         * program headers of the ELF file (which is wrong).\n         *\n         * Instead, we define the stack in C in the .ndks.stack section, which\n         * makes it appear here.\n         *\/\n        _kernel_stack_bottom = .;\n        *(.ndks.stack)\n        _kernel_stack_top = .;\n\n        *(.boot.node)\n        *(.bss)\n        *(COMMON)\n        _ndks_end = .;\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n    }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"7fa9bf25dc5f50507796a459cc91a3d58dc4e675","subject":"Fix issue in linker script generated by TrueStudio for STM32F0.","message":"Fix issue in linker script generated by TrueStudio for STM32F0.\n","repos":"FreeRTOS\/FreeRTOS-Kernel,FreeRTOS\/FreeRTOS-Kernel","old_file":"Demo\/CORTEX_STM32F100_Atollic\/stm32_flash.ld","new_file":"Demo\/CORTEX_STM32F100_Atollic\/stm32_flash.ld","new_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F100RB Device with\n**                128KByte FLASH, 8KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  This file may be distributed and used with the FreeRTOS example project \n**  for Atollic TrueSTUDIO only. \n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20002000;    \/* end of 8K RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x80; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 8K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  PROVIDE ( end = _ebss );\n  PROVIDE ( _end = _ebss );\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\n  .memory_b1_text :\n  {\n    *(.mb1text)        \/* .mb1text sections (code) *\/\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\n    *(.mb1rodata)      \/* read-only data (constants) *\/\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F100RB Device with\n**                128KByte FLASH, 8KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  This file may be distributed and used with the FreeRTOS example project \n**  for Atollic TrueSTUDIO only. \n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20002000;    \/* end of 8K RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x80; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 8K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  PROVIDE ( end = _ebss );\n  PROVIDE ( _end = _ebss );\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\n  .memory_b1_text :\n  {\n    *(.mb1text)        \/* .mb1text sections (code) *\/\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\n    *(.mb1rodata)      \/* read-only data (constants) *\/\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a06aad02b41082f504cbc787e2261c47135322c8","subject":"cleaned up linker script","message":"cleaned up linker script\n","repos":"tsion\/oos,tsion\/oos,fasterthanlime\/oos,fasterthanlime\/oos","old_file":"Src\/Kernel\/Linker.ld","new_file":"Src\/Kernel\/Linker.ld","new_contents":"ENTRY(_start)\n\nSECTIONS {\n    \/* 0x100000 = 1 MB. The kernel must be above 1 MB in order for GRUB to be able to load it. *\/\n    . = 0x100000;\n\n    .text ALIGN (0x1000) : {\n        *(.text)\n    }\n\n    .rodata ALIGN (0x1000) : {\n        *(.rodata)\n    }\n\n    .data ALIGN (0x1000) : {\n        *(.data)\n    }\n\n    .bss ALIGN (0x1000) : {\n        *(COMMON)\n        *(.bss)\n    }\n\n    kernelEnd = .;\n}\n\n","old_contents":"ENTRY(_start)\n\nSECTIONS {\n\t. = 0x100000;\n\n\t.text : ALIGN (0x1000) {\n\t\t*(.mboot)\n\t\t*(.text)\n\t}\n\n\t.rodata ALIGN (0x1000) : {\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN (0x1000) : {\n\t\t*(.data)\n\t}\n\n\t.bss ALIGN (0x1000) : {\n\t\tsbss = .;\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\tebss = .;\n\t}\n\n\tend = .;\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a8de3056203268143f9a016357daa7e67a7041fc","subject":"esp_wifi: Add softap pmf support for 8684.","message":"esp_wifi: Add softap pmf support for 8684.\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.ld","new_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.ld","new_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum 6c4d0f3a9f2d0c93477024a1a8f13746\n *\n * Compatible with ROM where ECO version equal or greater to 0.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\nrtc_get_wakeup_cause = 0x40000020;\nrtc_select_apb_bridge = 0x40000024;\nrtc_unhold_all_pads = 0x40000028;\nets_is_print_boot = 0x4000002c;\nets_printf = 0x40000030;\nets_install_putc1 = 0x40000034;\nets_install_uart_printf = 0x40000038;\nets_install_putc2 = 0x4000003c;\nPROVIDE( ets_delay_us = 0x40000040 );\nets_get_stack_info = 0x40000044;\nets_install_lock = 0x40000048;\nets_backup_dma_copy = 0x4000004c;\nets_apb_backup_init_lock_func = 0x40000050;\nUartRxString = 0x40000054;\nuart_tx_one_char = 0x40000058;\nuart_tx_one_char2 = 0x4000005c;\nuart_rx_one_char = 0x40000060;\nuart_rx_one_char_block = 0x40000064;\nuart_rx_readbuff = 0x40000068;\nuartAttach = 0x4000006c;\nuart_tx_flush = 0x40000070;\nuart_tx_wait_idle = 0x40000074;\nuart_div_modify = 0x40000078;\nets_write_char_uart = 0x4000007c;\nuart_tx_switch = 0x40000080;\nmultofup = 0x40000084;\nsoftware_reset = 0x40000088;\nsoftware_reset_cpu = 0x4000008c;\nassist_debug_clock_enable = 0x40000090;\nassist_debug_record_enable = 0x40000094;\nclear_super_wdt_reset_flag = 0x40000098;\ndisable_default_watchdog = 0x4000009c;\nsend_packet = 0x400000a0;\nrecv_packet = 0x400000a4;\nGetUartDevice = 0x400000a8;\nUartDwnLdProc = 0x400000ac;\nUart_Init = 0x400000b0;\nets_set_user_start = 0x400000b4;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff4fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000b8;\nmz_free = 0x400000bc;\ntdefl_compress = 0x400000c0;\ntdefl_compress_buffer = 0x400000c4;\ntdefl_compress_mem_to_heap = 0x400000c8;\ntdefl_compress_mem_to_mem = 0x400000cc;\ntdefl_compress_mem_to_output = 0x400000d0;\ntdefl_get_adler32 = 0x400000d4;\ntdefl_get_prev_return_status = 0x400000d8;\ntdefl_init = 0x400000dc;\ntdefl_write_image_to_png_file_in_memory = 0x400000e0;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000e4;\ntinfl_decompress = 0x400000e8;\ntinfl_decompress_mem_to_callback = 0x400000ec;\ntinfl_decompress_mem_to_heap = 0x400000f0;\ntinfl_decompress_mem_to_mem = 0x400000f4;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x400000f8 );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x400000fc );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000100 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000104 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000108 );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x4000010c );\nPROVIDE( _esp_rom_spiflash_erase_sector = 0x40000110 );\nPROVIDE( _esp_rom_spiflash_erase_block = 0x40000114 );\nPROVIDE( _esp_rom_spiflash_write = 0x40000118 );\nPROVIDE( _esp_rom_spiflash_read = 0x4000011c );\nPROVIDE( _esp_rom_spiflash_unlock = 0x40000120 );\nPROVIDE( _SPIEraseArea = 0x40000124 );\nPROVIDE( _SPI_write_enable = 0x40000128 );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x4000012c );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000130 );\nPROVIDE( esp_rom_spiflash_write = 0x40000134 );\nPROVIDE( esp_rom_spiflash_read = 0x40000138 );\nPROVIDE( esp_rom_spiflash_unlock = 0x4000013c );\nPROVIDE( SPIEraseArea = 0x40000140 );\nPROVIDE( SPI_write_enable = 0x40000144 );\nPROVIDE( esp_rom_spiflash_config_param = 0x40000148 );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x4000014c );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000150 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000154 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x40000158 );\nPROVIDE( esp_rom_spi_flash_update_id = 0x4000015c );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000160 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000164 );\nPROVIDE( esp_rom_spiflash_read_status = 0x40000168 );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x4000016c );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000170 );\nPROVIDE( spi_flash_attach = 0x40000174 );\nPROVIDE( spi_flash_get_chip_size = 0x40000178 );\nPROVIDE( spi_flash_guard_set = 0x4000017c );\nPROVIDE( spi_flash_guard_get = 0x40000180 );\nPROVIDE( spi_flash_read_encrypted = 0x40000184 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x40000188 );\nPROVIDE( spi_flash_mmap_page_num_init = 0x4000018c );\nPROVIDE( spi_flash_mmap = 0x40000190 );\nPROVIDE( spi_flash_mmap_pages = 0x40000194 );\nPROVIDE( spi_flash_munmap = 0x40000198 );\nPROVIDE( spi_flash_mmap_dump = 0x4000019c );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001a0 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001a4 );\nPROVIDE( spi_flash_cache2phys = 0x400001a8 );\nPROVIDE( spi_flash_phys2cache = 0x400001ac );\nPROVIDE( spi_flash_disable_cache = 0x400001b0 );\nPROVIDE( spi_flash_restore_cache = 0x400001b4 );\nPROVIDE( spi_flash_cache_enabled = 0x400001b8 );\nPROVIDE( spi_flash_enable_cache = 0x400001bc );\nPROVIDE( spi_cache_mode_switch = 0x400001c0 );\nPROVIDE( spi_common_set_dummy_output = 0x400001c4 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001c8 );\nPROVIDE( esp_rom_spi_set_address_bit_len = 0x400001cc );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001d0 );\nPROVIDE( SPILock = 0x400001d4 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001d8 );\nPROVIDE( SPI_Common_Command = 0x400001dc );\nPROVIDE( SPI_WakeUp = 0x400001e0 );\nPROVIDE( SPI_block_erase = 0x400001e4 );\nPROVIDE( SPI_chip_erase = 0x400001e8 );\nPROVIDE( SPI_init = 0x400001ec );\nPROVIDE( SPI_page_program = 0x400001f0 );\nPROVIDE( SPI_read_data = 0x400001f4 );\nPROVIDE( SPI_sector_erase = 0x400001f8 );\nPROVIDE( SelectSpiFunction = 0x400001fc );\nPROVIDE( SetSpiDrvs = 0x40000200 );\nPROVIDE( Wait_SPI_Idle = 0x40000204 );\nPROVIDE( spi_dummy_len_fix = 0x40000208 );\nPROVIDE( Disable_QMode = 0x4000020c );\nPROVIDE( Enable_QMode = 0x40000210 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group hal_soc\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x40000214 );\nPROVIDE( spi_flash_hal_device_config = 0x40000218 );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x4000021c );\nPROVIDE( spi_flash_hal_common_command = 0x40000220 );\nPROVIDE( spi_flash_hal_read = 0x40000224 );\nPROVIDE( spi_flash_hal_erase_chip = 0x40000228 );\nPROVIDE( spi_flash_hal_erase_sector = 0x4000022c );\nPROVIDE( spi_flash_hal_erase_block = 0x40000230 );\nPROVIDE( spi_flash_hal_program_page = 0x40000234 );\nPROVIDE( spi_flash_hal_set_write_protect = 0x40000238 );\nPROVIDE( spi_flash_hal_host_idle = 0x4000023c );\nPROVIDE( spi_flash_hal_check_status = 0x40000240 );\nPROVIDE( spi_flash_hal_setup_read_suspend = 0x40000244 );\nPROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x40000248 );\nPROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x4000024c );\nPROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000250 );\nPROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000254 );\nPROVIDE( spi_flash_hal_resume = 0x40000258 );\nPROVIDE( spi_flash_hal_suspend = 0x4000025c );\nPROVIDE( spi_flash_encryption_hal_enable = 0x40000260 );\nPROVIDE( spi_flash_encryption_hal_disable = 0x40000264 );\nPROVIDE( spi_flash_encryption_hal_prepare = 0x40000268 );\nPROVIDE( spi_flash_encryption_hal_done = 0x4000026c );\nPROVIDE( spi_flash_encryption_hal_destroy = 0x40000270 );\nPROVIDE( spi_flash_encryption_hal_check = 0x40000274 );\nPROVIDE( wdt_hal_init = 0x40000278 );\nPROVIDE( wdt_hal_deinit = 0x4000027c );\nPROVIDE( wdt_hal_config_stage = 0x40000280 );\nPROVIDE( wdt_hal_write_protect_disable = 0x40000284 );\nPROVIDE( wdt_hal_write_protect_enable = 0x40000288 );\nPROVIDE( wdt_hal_enable = 0x4000028c );\nPROVIDE( wdt_hal_disable = 0x40000290 );\nPROVIDE( wdt_hal_handle_intr = 0x40000294 );\nPROVIDE( wdt_hal_feed = 0x40000298 );\nPROVIDE( wdt_hal_set_flashboot_en = 0x4000029c );\nPROVIDE( wdt_hal_is_enabled = 0x400002a0 );\nPROVIDE( systimer_hal_init = 0x400002a4 );\nPROVIDE( systimer_hal_get_counter_value = 0x400002a8 );\nPROVIDE( systimer_hal_get_time = 0x400002ac );\nPROVIDE( systimer_hal_set_alarm_target = 0x400002b0 );\nPROVIDE( systimer_hal_set_alarm_period = 0x400002b4 );\nPROVIDE( systimer_hal_get_alarm_value = 0x400002b8 );\nPROVIDE( systimer_hal_enable_alarm_int = 0x400002bc );\nPROVIDE( systimer_hal_on_apb_freq_update = 0x400002c0 );\nPROVIDE( systimer_hal_counter_value_advance = 0x400002c4 );\nPROVIDE( systimer_hal_enable_counter = 0x400002c8 );\nPROVIDE( systimer_hal_select_alarm_mode = 0x400002cc );\nPROVIDE( systimer_hal_connect_alarm_counter = 0x400002d0 );\nPROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d4 );\n\n\n\/***************************************\n Group heap\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( tlsf_create = 0x400002d8 );\nPROVIDE( tlsf_create_with_pool = 0x400002dc );\nPROVIDE( tlsf_get_pool = 0x400002e0 );\nPROVIDE( tlsf_add_pool = 0x400002e4 );\nPROVIDE( tlsf_remove_pool = 0x400002e8 );\nPROVIDE( tlsf_malloc = 0x400002ec );\nPROVIDE( tlsf_memalign = 0x400002f0 );\nPROVIDE( tlsf_memalign_offs = 0x400002f4 );\nPROVIDE( tlsf_realloc = 0x400002f8 );\nPROVIDE( tlsf_free = 0x400002fc );\nPROVIDE( tlsf_block_size = 0x40000300 );\nPROVIDE( tlsf_size = 0x40000304 );\nPROVIDE( tlsf_align_size = 0x40000308 );\nPROVIDE( tlsf_block_size_min = 0x4000030c );\nPROVIDE( tlsf_block_size_max = 0x40000310 );\nPROVIDE( tlsf_pool_overhead = 0x40000314 );\nPROVIDE( tlsf_alloc_overhead = 0x40000318 );\nPROVIDE( tlsf_walk_pool = 0x4000031c );\nPROVIDE( tlsf_check = 0x40000320 );\nPROVIDE( tlsf_check_pool = 0x40000324 );\nPROVIDE( tlsf_poison_fill_pfunc_set = 0x40000328 );\nPROVIDE( multi_heap_get_block_address_impl = 0x4000032c );\nPROVIDE( multi_heap_get_allocated_size_impl = 0x40000330 );\nPROVIDE( multi_heap_register_impl = 0x40000334 );\nPROVIDE( multi_heap_set_lock = 0x40000338 );\nPROVIDE( multi_heap_mutex_init = 0x4000033c );\nPROVIDE( multi_heap_internal_lock = 0x40000340 );\nPROVIDE( multi_heap_internal_unlock = 0x40000344 );\nPROVIDE( multi_heap_get_first_block = 0x40000348 );\nPROVIDE( multi_heap_get_next_block = 0x4000034c );\nPROVIDE( multi_heap_is_free = 0x40000350 );\nPROVIDE( multi_heap_malloc_impl = 0x40000354 );\nPROVIDE( multi_heap_free_impl = 0x40000358 );\nPROVIDE( multi_heap_realloc_impl = 0x4000035c );\nPROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000360 );\nPROVIDE( multi_heap_aligned_alloc_impl = 0x40000364 );\nPROVIDE( multi_heap_check = 0x40000368 );\nPROVIDE( multi_heap_dump = 0x4000036c );\nPROVIDE( multi_heap_free_size_impl = 0x40000370 );\nPROVIDE( multi_heap_minimum_free_size_impl = 0x40000374 );\nPROVIDE( multi_heap_get_info_impl = 0x40000378 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x4000037c );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x40000380 );\nPROVIDE( spi_flash_chip_generic_write = 0x40000384 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000388 );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x4000038c );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000390 );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000394 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x40000398 );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x4000039c );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x400003a0 );\nPROVIDE( spi_flash_chip_generic_page_program = 0x400003a4 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003a8 );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003ac );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x400003b0 );\nPROVIDE( spi_flash_chip_generic_yield = 0x400003b4 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x400003b8 );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x400003bc );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c0 );\nPROVIDE( spi_flash_chip_generic_read = 0x400003c4 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003c8 );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003cc );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d0 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d4 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003d8 );\nPROVIDE( spi_flash_common_set_io_mode = 0x400003dc );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e0 );\nPROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e4 );\nPROVIDE( spi_flash_chip_generic_get_caps = 0x400003e8 );\nPROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003ec );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f0 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400003f4 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003f8 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );\nPROVIDE( spi_flash_encryption = 0x3fcdffe4 );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x400003fc );\nPROVIDE( memspi_host_read_status_hs = 0x40000400 );\nPROVIDE( memspi_host_flush_cache = 0x40000404 );\nPROVIDE( memspi_host_erase_chip = 0x40000408 );\nPROVIDE( memspi_host_erase_sector = 0x4000040c );\nPROVIDE( memspi_host_erase_block = 0x40000410 );\nPROVIDE( memspi_host_program_page = 0x40000414 );\nPROVIDE( memspi_host_read = 0x40000418 );\nPROVIDE( memspi_host_set_write_protect = 0x4000041c );\nPROVIDE( memspi_host_set_max_read_len = 0x40000420 );\nPROVIDE( memspi_host_read_data_slicer = 0x40000424 );\nPROVIDE( memspi_host_write_data_slicer = 0x40000428 );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x4000042c );\nPROVIDE( esp_flash_read_id = 0x40000430 );\nPROVIDE( esp_flash_get_size = 0x40000434 );\nPROVIDE( esp_flash_erase_chip = 0x40000438 );\nPROVIDE( esp_flash_erase_region = 0x4000043c );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000440 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000444 );\nPROVIDE( esp_flash_get_protectable_regions = 0x40000448 );\nPROVIDE( esp_flash_get_protected_region = 0x4000044c );\nPROVIDE( esp_flash_set_protected_region = 0x40000450 );\nPROVIDE( esp_flash_read = 0x40000454 );\nPROVIDE( esp_flash_write = 0x40000458 );\nPROVIDE( esp_flash_write_encrypted = 0x4000045c );\nPROVIDE( esp_flash_read_encrypted = 0x40000460 );\nPROVIDE( esp_flash_get_io_mode = 0x40000464 );\nPROVIDE( esp_flash_set_io_mode = 0x40000468 );\nPROVIDE( spi_flash_boot_attach = 0x4000046c );\nPROVIDE( esp_flash_read_chip_id = 0x40000470 );\nPROVIDE( detect_spi_flash_chip = 0x40000474 );\nPROVIDE( esp_rom_spiflash_write_disable = 0x40000478 );\nPROVIDE( esp_flash_suspend_cmd_init = 0x4000047c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe0 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffdc );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400006dc );\nPROVIDE( Cache_Get_Mode = 0x400006e0 );\nPROVIDE( Cache_Address_Through_IBus = 0x400006e4 );\nPROVIDE( Cache_Address_Through_DBus = 0x400006e8 );\nPROVIDE( Cache_Set_Default_Mode = 0x400006ec );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f0 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400006f4 );\nPROVIDE( MMU_Set_Page_Mode = 0x400006f8 );\nPROVIDE( MMU_Get_Page_Mode = 0x400006fc );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x40000700 );\nPROVIDE( Cache_Op_Addr = 0x40000704 );\nPROVIDE( Cache_Invalidate_Addr = 0x40000708 );\nPROVIDE( Cache_Invalidate_ICache_All = 0x4000070c );\nPROVIDE( Cache_Mask_All = 0x40000710 );\nPROVIDE( Cache_UnMask_Dram0 = 0x40000714 );\nPROVIDE( Cache_Disable_ICache = 0x40000718 );\nPROVIDE( Cache_Enable_ICache = 0x4000071c );\nPROVIDE( Cache_Suspend_ICache = 0x40000720 );\nPROVIDE( Cache_Resume_ICache = 0x40000724 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x40000728 );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x4000072c );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000730 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x40000734 );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x40000738 );\nPROVIDE( Cache_Owner_Init = 0x4000073c );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000740 );\nPROVIDE( Cache_MMU_Init = 0x40000744 );\nPROVIDE( Cache_Ibus_MMU_Set = 0x40000748 );\nPROVIDE( Cache_Dbus_MMU_Set = 0x4000074c );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000750 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x40000754 );\nPROVIDE( Cache_Get_Virtual_Addr = 0x40000758 );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x4000075c );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000760 );\nPROVIDE( Cache_Get_Memory_value = 0x40000764 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd0 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x40000768;\nets_get_cpu_frequency = 0x4000076c;\nets_update_cpu_frequency = 0x40000770;\nets_get_printf_channel = 0x40000774;\nets_get_xtal_div = 0x40000778;\nets_set_xtal_div = 0x4000077c;\nets_get_xtal_freq = 0x40000780;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x40000784;\ngpio_matrix_in = 0x40000788;\ngpio_matrix_out = 0x4000078c;\ngpio_output_disable = 0x40000790;\ngpio_output_enable = 0x40000794;\ngpio_output_set = 0x40000798;\ngpio_pad_hold = 0x4000079c;\ngpio_pad_input_disable = 0x400007a0;\ngpio_pad_input_enable = 0x400007a4;\ngpio_pad_pulldown = 0x400007a8;\ngpio_pad_pullup = 0x400007ac;\ngpio_pad_select_gpio = 0x400007b0;\ngpio_pad_set_drv = 0x400007b4;\ngpio_pad_unhold = 0x400007b8;\ngpio_pin_wakeup_disable = 0x400007bc;\ngpio_pin_wakeup_enable = 0x400007c0;\ngpio_bypass_matrix_in = 0x400007c4;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400007c8;\nesprv_intc_int_set_threshold = 0x400007cc;\nesprv_intc_int_enable = 0x400007d0;\nesprv_intc_int_disable = 0x400007d4;\nesprv_intc_int_set_type = 0x400007d8;\nPROVIDE( intr_handler_set = 0x400007dc );\nintr_matrix_set = 0x400007e0;\nets_intr_lock = 0x400007e4;\nets_intr_unlock = 0x400007e8;\nets_isr_attach = 0x400007ec;\nets_isr_mask = 0x400007f0;\nets_isr_unmask = 0x400007f4;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\ncrc32_le = 0x400007f8;\ncrc16_le = 0x400007fc;\ncrc8_le = 0x40000800;\ncrc32_be = 0x40000804;\ncrc16_be = 0x40000808;\ncrc8_be = 0x4000080c;\nesp_crc8 = 0x40000810;\nets_sha_enable = 0x40000814;\nets_sha_disable = 0x40000818;\nets_sha_get_state = 0x4000081c;\nets_sha_init = 0x40000820;\nets_sha_process = 0x40000824;\nets_sha_starts = 0x40000828;\nets_sha_update = 0x4000082c;\nets_sha_finish = 0x40000830;\nets_sha_clone = 0x40000834;\n\/* Data (.data, .bss, .rodata) *\/\ncrc32_le_table_ptr = 0x3ff4fff8;\ncrc16_le_table_ptr = 0x3ff4fff4;\ncrc8_le_table_ptr = 0x3ff4fff0;\ncrc32_be_table_ptr = 0x3ff4ffec;\ncrc16_be_table_ptr = 0x3ff4ffe8;\ncrc8_be_table_ptr = 0x3ff4ffe4;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x40000838;\nets_efuse_program = 0x4000083c;\nets_efuse_clear_program_registers = 0x40000840;\nets_efuse_write_key = 0x40000844;\nets_efuse_get_read_register_address = 0x40000848;\nets_efuse_get_key_purpose = 0x4000084c;\nets_efuse_key_block_unused = 0x40000850;\nets_efuse_find_unused_key_block = 0x40000854;\nets_efuse_rs_calculate = 0x40000858;\nets_efuse_count_unused_key_blocks = 0x4000085c;\nets_efuse_secure_boot_enabled = 0x40000860;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000864;\nets_efuse_cache_encryption_enabled = 0x40000868;\nets_efuse_download_modes_disabled = 0x4000086c;\nets_efuse_find_purpose = 0x40000870;\nets_efuse_force_send_resume = 0x40000874;\nets_efuse_get_flash_delay_us = 0x40000878;\nets_efuse_get_mac = 0x4000087c;\nets_efuse_get_uart_print_control = 0x40000880;\nets_efuse_direct_boot_mode_disabled = 0x40000884;\nets_efuse_security_download_modes_enabled = 0x40000888;\nets_efuse_set_timing = 0x4000088c;\nets_efuse_jtag_disabled = 0x40000890;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_ecdsa_verify = 0x40000894;\nets_secure_boot_verify_bootloader_with_keys = 0x40000898;\nets_secure_boot_verify_signature = 0x4000089c;\nets_secure_boot_read_key_digests = 0x400008a0;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Data (.data, .bss, .rodata) *\/\ng_uart_print = 0x3fcdffc9;\ng_usb_print = 0x3fcdffc8;\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nble_controller_rom_data_init = 0x40000a14;\nble_osi_coex_funcs_register = 0x40000a18;\nbt_rf_coex_cfg_get_default = 0x40000a1c;\nbt_rf_coex_dft_pti_get_default = 0x40000a20;\nbt_rf_coex_hooks_p_set = 0x40000a24;\nr__os_mbuf_copypkthdr = 0x40000a28;\nr__os_msys_find_pool = 0x40000a2c;\nr_ble_controller_get_rom_compile_version = 0x40000a30;\nr_ble_hci_ram_hs_acl_tx = 0x40000a34;\nr_ble_hci_ram_hs_cmd_tx = 0x40000a38;\nr_ble_hci_ram_ll_acl_tx = 0x40000a3c;\nr_ble_hci_ram_ll_evt_tx = 0x40000a40;\nr_ble_hci_ram_reset = 0x40000a44;\nr_ble_hci_ram_set_acl_free_cb = 0x40000a48;\nr_ble_hci_trans_acl_buf_alloc = 0x40000a4c;\nr_ble_hci_trans_buf_alloc = 0x40000a50;\nr_ble_hci_trans_buf_free = 0x40000a54;\nr_ble_hci_trans_cfg_hs = 0x40000a58;\nr_ble_hci_trans_cfg_ll = 0x40000a5c;\nr_ble_hci_trans_deinit = 0x40000a60;\nr_ble_hci_trans_env_init = 0x40000a64;\nr_ble_hci_trans_init = 0x40000a68;\nr_ble_hci_uart_acl_tx = 0x40000a6c;\nr_ble_hci_uart_cmdevt_tx = 0x40000a70;\nr_ble_hci_uart_config = 0x40000a74;\nr_ble_hci_uart_free_pkt = 0x40000a78;\nr_ble_hci_uart_hs_acl_tx = 0x40000a7c;\nr_ble_hci_uart_hs_cmd_tx = 0x40000a80;\nr_ble_hci_uart_ll_acl_tx = 0x40000a84;\nr_ble_hci_uart_ll_evt_tx = 0x40000a88;\nr_ble_hci_uart_rx_acl = 0x40000a8c;\nr_ble_hci_uart_rx_char = 0x40000a90;\nr_ble_hci_uart_rx_cmd = 0x40000a94;\nr_ble_hci_uart_rx_evt = 0x40000a98;\nr_ble_hci_uart_rx_evt_cb = 0x40000a9c;\nr_ble_hci_uart_rx_le_evt = 0x40000aa0;\nr_ble_hci_uart_rx_pkt_type = 0x40000aa4;\nr_ble_hci_uart_rx_skip_acl = 0x40000aa8;\nr_ble_hci_uart_rx_skip_cmd = 0x40000aac;\nr_ble_hci_uart_rx_skip_evt = 0x40000ab0;\nr_ble_hci_uart_rx_sync_loss = 0x40000ab4;\nr_ble_hci_uart_set_acl_free_cb = 0x40000ab8;\nr_ble_hci_uart_sync_lost = 0x40000abc;\nr_ble_hci_uart_trans_reset = 0x40000ac0;\nr_ble_hci_uart_tx_char = 0x40000ac4;\nr_ble_hci_uart_tx_pkt_type = 0x40000ac8;\nr_ble_hw_driver_deinit = 0x40000acc;\nr_ble_hw_driver_env_init = 0x40000ad0;\nr_ble_hw_encrypt_block = 0x40000ad4;\nr_ble_hw_get_public_addr = 0x40000ad8;\nr_ble_hw_get_static_addr = 0x40000adc;\nr_ble_hw_periodiclist_add = 0x40000ae0;\nr_ble_hw_periodiclist_clear = 0x40000ae4;\nr_ble_hw_periodiclist_rmv = 0x40000ae8;\nr_ble_hw_resolv_list_cur_entry = 0x40000aec;\nr_ble_hw_resolv_list_match = 0x40000af0;\nr_ble_hw_resolv_list_set = 0x40000af4;\nr_ble_hw_rng_init = 0x40000af8;\nr_ble_hw_rng_start = 0x40000afc;\nr_ble_hw_rng_stop = 0x40000b00;\nr_ble_hw_rx_local_is_rpa = 0x40000b04;\nr_ble_hw_whitelist_add = 0x40000b08;\nr_ble_hw_whitelist_clear = 0x40000b0c;\nr_ble_hw_whitelist_dev_num = 0x40000b10;\nr_ble_hw_whitelist_get_base = 0x40000b14;\nr_ble_hw_whitelist_rmv = 0x40000b18;\nr_ble_hw_whitelist_search = 0x40000b1c;\nr_ble_hw_whitelist_sort = 0x40000b20;\nr_ble_ll_acl_data_in = 0x40000b24;\nr_ble_ll_addr_is_id = 0x40000b28;\nr_ble_ll_addr_subtype = 0x40000b2c;\nr_ble_ll_adv_active_chanset_clear = 0x40000b30;\nr_ble_ll_adv_active_chanset_is_pri = 0x40000b34;\nr_ble_ll_adv_active_chanset_is_sec = 0x40000b38;\nr_ble_ll_adv_active_chanset_set_pri = 0x40000b3c;\nr_ble_ll_adv_active_chanset_set_sec = 0x40000b40;\nr_ble_ll_adv_aux_calculate = 0x40000b44;\nr_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000b48;\nr_ble_ll_adv_aux_pdu_make = 0x40000b4c;\nr_ble_ll_adv_aux_scannable_pdu_make = 0x40000b50;\nr_ble_ll_adv_aux_scannable_pdu_payload_len = 0x40000b54;\nr_ble_ll_adv_aux_schedule = 0x40000b58;\nr_ble_ll_adv_aux_schedule_first = 0x40000b5c;\nr_ble_ll_adv_aux_schedule_next = 0x40000b60;\nr_ble_ll_adv_aux_scheduled = 0x40000b64;\nr_ble_ll_adv_aux_set_start_time = 0x40000b68;\nr_ble_ll_adv_aux_txed = 0x40000b6c;\nr_ble_ll_adv_can_chg_whitelist = 0x40000b70;\nr_ble_ll_adv_chk_rpa_timeout = 0x40000b74;\nr_ble_ll_adv_clear_all = 0x40000b78;\nr_ble_ll_adv_coex_dpc_calc_pti_update_itvl = 0x40000b7c;\nr_ble_ll_adv_coex_dpc_process_pri = 0x40000b80;\nr_ble_ll_adv_coex_dpc_process_sec = 0x40000b84;\nr_ble_ll_adv_coex_dpc_pti_get = 0x40000b88;\nr_ble_ll_adv_coex_dpc_update = 0x40000b8c;\nr_ble_ll_adv_coex_dpc_update_on_adv_start = 0x40000b90;\nr_ble_ll_adv_coex_dpc_update_on_aux_scheduled = 0x40000b94;\nr_ble_ll_adv_coex_dpc_update_on_data_updated = 0x40000b98;\nr_ble_ll_adv_coex_dpc_update_on_event_end = 0x40000b9c;\nr_ble_ll_adv_coex_dpc_update_on_event_scheduled = 0x40000ba0;\nr_ble_ll_adv_conn_req_rxd = 0x40000ba4;\nr_ble_ll_adv_deinit = 0x40000ba8;\nr_ble_ll_adv_done = 0x40000bac;\nr_ble_ll_adv_drop_event = 0x40000bb0;\nr_ble_ll_adv_enabled = 0x40000bb4;\nr_ble_ll_adv_env_init = 0x40000bb8;\nr_ble_ll_adv_event_done = 0x40000bbc;\nr_ble_ll_adv_event_rmvd_from_sched = 0x40000bc0;\nr_ble_ll_adv_ext_estimate_data_itvl = 0x40000bc4;\nr_ble_ll_adv_ext_set_adv_data = 0x40000bc8;\nr_ble_ll_adv_ext_set_enable = 0x40000bcc;\nr_ble_ll_adv_ext_set_param = 0x40000bd0;\nr_ble_ll_adv_ext_set_scan_rsp = 0x40000bd4;\nr_ble_ll_adv_final_chan = 0x40000bd8;\nr_ble_ll_adv_first_chan = 0x40000bdc;\nr_ble_ll_adv_flags_clear = 0x40000be0;\nr_ble_ll_adv_flags_set = 0x40000be4;\nr_ble_ll_adv_get_local_rpa = 0x40000be8;\nr_ble_ll_adv_get_peer_rpa = 0x40000bec;\nr_ble_ll_adv_get_sec_pdu_len = 0x40000bf0;\nr_ble_ll_adv_halt = 0x40000bf4;\nr_ble_ll_adv_hci_set_random_addr = 0x40000bf8;\nr_ble_ll_adv_init = 0x40000bfc;\nr_ble_ll_adv_legacy_pdu_make = 0x40000c00;\nr_ble_ll_adv_make_done = 0x40000c04;\nr_ble_ll_adv_pdu_make = 0x40000c08;\nr_ble_ll_adv_periodic_check_data_itvl = 0x40000c0c;\nr_ble_ll_adv_periodic_done = 0x40000c10;\nr_ble_ll_adv_periodic_enable = 0x40000c14;\nr_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c18;\nr_ble_ll_adv_periodic_event_done = 0x40000c1c;\nr_ble_ll_adv_periodic_rmvd_from_sched = 0x40000c20;\nr_ble_ll_adv_periodic_schedule_first = 0x40000c24;\nr_ble_ll_adv_periodic_schedule_next = 0x40000c28;\nr_ble_ll_adv_periodic_send_sync_ind = 0x40000c2c;\nr_ble_ll_adv_periodic_set_data = 0x40000c30;\nr_ble_ll_adv_periodic_set_info_transfer = 0x40000c34;\nr_ble_ll_adv_periodic_set_param = 0x40000c38;\nr_ble_ll_adv_put_aux_ptr = 0x40000c3c;\nr_ble_ll_adv_put_syncinfo = 0x40000c40;\nr_ble_ll_adv_rd_max_adv_data_len = 0x40000c44;\nr_ble_ll_adv_rd_sup_adv_sets = 0x40000c48;\nr_ble_ll_adv_read_txpwr = 0x40000c4c;\nr_ble_ll_adv_remove = 0x40000c50;\nr_ble_ll_adv_reschedule_event = 0x40000c54;\nr_ble_ll_adv_reschedule_periodic_event = 0x40000c58;\nr_ble_ll_adv_reset = 0x40000c5c;\nr_ble_ll_adv_rpa_timeout = 0x40000c60;\nr_ble_ll_adv_rpa_update = 0x40000c64;\nr_ble_ll_adv_rx_isr_end = 0x40000c68;\nr_ble_ll_adv_rx_isr_start = 0x40000c6c;\nr_ble_ll_adv_rx_pkt_in = 0x40000c70;\nr_ble_ll_adv_rx_req = 0x40000c74;\nr_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c78;\nr_ble_ll_adv_scan_rsp_pdu_make = 0x40000c7c;\nr_ble_ll_adv_scheduled = 0x40000c80;\nr_ble_ll_adv_sec_done = 0x40000c84;\nr_ble_ll_adv_sec_event_done = 0x40000c88;\nr_ble_ll_adv_secondary_tx_start_cb = 0x40000c8c;\nr_ble_ll_adv_send_conn_comp_ev = 0x40000c90;\nr_ble_ll_adv_set_adv_data = 0x40000c94;\nr_ble_ll_adv_set_adv_params = 0x40000c98;\nr_ble_ll_adv_set_enable = 0x40000c9c;\nr_ble_ll_adv_set_random_addr = 0x40000ca0;\nr_ble_ll_adv_set_scan_rsp_data = 0x40000ca4;\nr_ble_ll_adv_set_sched = 0x40000ca8;\nr_ble_ll_adv_sm_deinit = 0x40000cac;\nr_ble_ll_adv_sm_event_init = 0x40000cb0;\nr_ble_ll_adv_sm_event_restore = 0x40000cb4;\nr_ble_ll_adv_sm_event_store = 0x40000cb8;\nr_ble_ll_adv_sm_find_configured = 0x40000cbc;\nr_ble_ll_adv_sm_get = 0x40000cc0;\nr_ble_ll_adv_sm_init = 0x40000cc4;\nr_ble_ll_adv_sm_reset = 0x40000cc8;\nr_ble_ll_adv_sm_start = 0x40000ccc;\nr_ble_ll_adv_sm_start_periodic = 0x40000cd0;\nr_ble_ll_adv_sm_stop = 0x40000cd4;\nr_ble_ll_adv_sm_stop_limit_reached = 0x40000cd8;\nr_ble_ll_adv_sm_stop_periodic = 0x40000cdc;\nr_ble_ll_adv_sm_stop_timeout = 0x40000ce0;\nr_ble_ll_adv_sync_calculate = 0x40000ce4;\nr_ble_ll_adv_sync_get_pdu_len = 0x40000ce8;\nr_ble_ll_adv_sync_next_scheduled = 0x40000cec;\nr_ble_ll_adv_sync_pdu_make = 0x40000cf0;\nr_ble_ll_adv_sync_schedule = 0x40000cf4;\nr_ble_ll_adv_sync_tx_done = 0x40000cf8;\nr_ble_ll_adv_sync_tx_end = 0x40000cfc;\nr_ble_ll_adv_sync_tx_start_cb = 0x40000d00;\nr_ble_ll_adv_tx_done = 0x40000d04;\nr_ble_ll_adv_tx_start_cb = 0x40000d08;\nr_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d0c;\nr_ble_ll_adv_update_data_mbuf = 0x40000d10;\nr_ble_ll_adv_update_did = 0x40000d14;\nr_ble_ll_adv_update_periodic_data = 0x40000d18;\nr_ble_ll_adv_wfr_timer_exp = 0x40000d1c;\nr_ble_ll_arr_pool_init = 0x40000d20;\nr_ble_ll_auth_pyld_tmo_event_send = 0x40000d24;\nr_ble_ll_aux_scan_cb = 0x40000d28;\nr_ble_ll_aux_scan_drop = 0x40000d2c;\nr_ble_ll_aux_scan_drop_event_cb = 0x40000d30;\nr_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d34;\nr_ble_ll_calc_session_key = 0x40000d38;\nr_ble_ll_calc_ticks_per_slot = 0x40000d3c;\nr_ble_ll_calc_us_convert_tick_unit = 0x40000d40;\nr_ble_ll_check_scan_params = 0x40000d44;\nr_ble_ll_chk_txrx_octets = 0x40000d48;\nr_ble_ll_chk_txrx_time = 0x40000d4c;\nr_ble_ll_conn_adjust_pyld_len = 0x40000d50;\nr_ble_ll_conn_auth_pyld_timer_cb = 0x40000d54;\nr_ble_ll_conn_auth_pyld_timer_start = 0x40000d58;\nr_ble_ll_conn_calc_dci = 0x40000d5c;\nr_ble_ll_conn_calc_dci_csa1 = 0x40000d60;\nr_ble_ll_conn_calc_itvl_ticks = 0x40000d64;\nr_ble_ll_conn_can_send_next_pdu = 0x40000d68;\nr_ble_ll_conn_chk_csm_flags = 0x40000d6c;\nr_ble_ll_conn_chk_phy_upd_start = 0x40000d70;\nr_ble_ll_conn_coex_dpc_process = 0x40000d74;\nr_ble_ll_conn_coex_dpc_pti_get = 0x40000d78;\nr_ble_ll_conn_coex_dpc_update = 0x40000d7c;\nr_ble_ll_conn_coex_dpc_update_on_event_scheduled = 0x40000d80;\nr_ble_ll_conn_comp_event_send = 0x40000d84;\nr_ble_ll_conn_connect_ind_pdu_make = 0x40000d88;\nr_ble_ll_conn_create = 0x40000d8c;\nr_ble_ll_conn_create_cancel = 0x40000d90;\nr_ble_ll_conn_created = 0x40000d94;\nr_ble_ll_conn_cth_flow_alloc_credit = 0x40000d98;\nr_ble_ll_conn_cth_flow_enable = 0x40000d9c;\nr_ble_ll_conn_cth_flow_error_fn = 0x40000da0;\nr_ble_ll_conn_cth_flow_free_credit = 0x40000da4;\nr_ble_ll_conn_cth_flow_have_credit = 0x40000da8;\nr_ble_ll_conn_cth_flow_is_enabled = 0x40000dac;\nr_ble_ll_conn_cth_flow_process_cmd = 0x40000db0;\nr_ble_ll_conn_cth_flow_set_buffers = 0x40000db4;\nr_ble_ll_conn_cur_pducb = 0x40000db8;\nr_ble_ll_conn_current_sm_over = 0x40000dbc;\nr_ble_ll_conn_end = 0x40000dc0;\nr_ble_ll_conn_enqueue_pkt = 0x40000dc4;\nr_ble_ll_conn_env_init = 0x40000dc8;\nr_ble_ll_conn_event_end = 0x40000dcc;\nr_ble_ll_conn_event_end_timer_cb = 0x40000dd0;\nr_ble_ll_conn_event_halt = 0x40000dd4;\nr_ble_ll_conn_event_is_over = 0x40000dd8;\nr_ble_ll_conn_event_start_cb = 0x40000ddc;\nr_ble_ll_conn_ext_master_init = 0x40000de0;\nr_ble_ll_conn_ext_set_params = 0x40000de4;\nr_ble_ll_conn_find_active_conn = 0x40000de8;\nr_ble_ll_conn_get_anchor = 0x40000dec;\nr_ble_ll_conn_get_ce_end_time = 0x40000df0;\nr_ble_ll_conn_get_new_pdu = 0x40000df4;\nr_ble_ll_conn_get_next_sched_time = 0x40000df8;\nr_ble_ll_conn_halt = 0x40000dfc;\nr_ble_ll_conn_hcc_params_set_fallback = 0x40000e00;\nr_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000e04;\nr_ble_ll_conn_hci_chk_conn_params = 0x40000e08;\nr_ble_ll_conn_hci_chk_scan_params = 0x40000e0c;\nr_ble_ll_conn_hci_disconnect_cmd = 0x40000e10;\nr_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000e14;\nr_ble_ll_conn_hci_le_ltk_reply = 0x40000e18;\nr_ble_ll_conn_hci_le_rd_phy = 0x40000e1c;\nr_ble_ll_conn_hci_le_set_phy = 0x40000e20;\nr_ble_ll_conn_hci_le_start_encrypt = 0x40000e24;\nr_ble_ll_conn_hci_param_nrr = 0x40000e28;\nr_ble_ll_conn_hci_param_rr = 0x40000e2c;\nr_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000e30;\nr_ble_ll_conn_hci_rd_chan_map = 0x40000e34;\nr_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000e38;\nr_ble_ll_conn_hci_rd_rssi = 0x40000e3c;\nr_ble_ll_conn_hci_read_rem_features = 0x40000e40;\nr_ble_ll_conn_hci_set_chan_class = 0x40000e44;\nr_ble_ll_conn_hci_set_data_len = 0x40000e48;\nr_ble_ll_conn_hci_update = 0x40000e4c;\nr_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000e50;\nr_ble_ll_conn_init_pending_aux_conn_rsp = 0x40000e54;\nr_ble_ll_conn_init_phy = 0x40000e58;\nr_ble_ll_conn_init_wfr_timer_exp = 0x40000e5c;\nr_ble_ll_conn_is_empty_pdu = 0x40000e60;\nr_ble_ll_conn_is_lru = 0x40000e64;\nr_ble_ll_conn_master_common_init = 0x40000e68;\nr_ble_ll_conn_master_init = 0x40000e6c;\nr_ble_ll_conn_module_deinit = 0x40000e70;\nr_ble_ll_conn_module_init = 0x40000e74;\nr_ble_ll_conn_module_reset = 0x40000e78;\nr_ble_ll_conn_new_pducb = 0x40000e7c;\nr_ble_ll_conn_next_event = 0x40000e80;\nr_ble_ll_conn_num_comp_pkts_event_send = 0x40000e84;\nr_ble_ll_conn_process_conn_params = 0x40000e88;\nr_ble_ll_conn_recv_ack = 0x40000e8c;\nr_ble_ll_conn_reset_pending_aux_conn_rsp = 0x40000e90;\nr_ble_ll_conn_rx_data_pdu = 0x40000e94;\nr_ble_ll_conn_rx_isr_end = 0x40000e98;\nr_ble_ll_conn_rx_isr_start = 0x40000e9c;\nr_ble_ll_conn_rxend_unencrypt = 0x40000ea0;\nr_ble_ll_conn_set_csa = 0x40000ea4;\nr_ble_ll_conn_set_global_chanmap = 0x40000ea8;\nr_ble_ll_conn_set_md_flag = 0x40000eac;\nr_ble_ll_conn_set_phy = 0x40000eb0;\nr_ble_ll_conn_set_slave_flow_control = 0x40000eb4;\nr_ble_ll_conn_set_txpwr_by_handle = 0x40000eb8;\nr_ble_ll_conn_set_unknown_rx_octets = 0x40000ebc;\nr_ble_ll_conn_slave_start = 0x40000ec0;\nr_ble_ll_conn_sm_get = 0x40000ec4;\nr_ble_ll_conn_sm_new = 0x40000ec8;\nr_ble_ll_conn_sm_npl_deinit = 0x40000ecc;\nr_ble_ll_conn_sm_npl_init = 0x40000ed0;\nr_ble_ll_conn_start_rx_encrypt = 0x40000ed4;\nr_ble_ll_conn_start_rx_unencrypt = 0x40000ed8;\nr_ble_ll_conn_timeout = 0x40000edc;\nr_ble_ll_conn_tx_pdu = 0x40000ee0;\nr_ble_ll_conn_tx_pkt_in = 0x40000ee4;\nr_ble_ll_conn_txend_encrypt = 0x40000ee8;\nr_ble_ll_conn_update_conn_params = 0x40000eec;\nr_ble_ll_conn_update_eff_data_len = 0x40000ef0;\nr_ble_ll_conn_update_new_pdu_len = 0x40000ef4;\nr_ble_ll_conn_wait_txend = 0x40000ef8;\nr_ble_ll_conn_wfr_timer_exp = 0x40000efc;\nr_ble_ll_copy_data = 0x40000f00;\nr_ble_ll_count_rx_adv_pdus = 0x40000f04;\nr_ble_ll_count_rx_stats = 0x40000f08;\nr_ble_ll_ctrl_chanmap_req_make = 0x40000f0c;\nr_ble_ll_ctrl_chk_proc_start = 0x40000f10;\nr_ble_ll_ctrl_conn_param_pdu_make = 0x40000f14;\nr_ble_ll_ctrl_conn_param_pdu_proc = 0x40000f18;\nr_ble_ll_ctrl_conn_param_reply = 0x40000f1c;\nr_ble_ll_ctrl_conn_upd_make = 0x40000f20;\nr_ble_ll_ctrl_datalen_upd_make = 0x40000f24;\nr_ble_ll_ctrl_enc_allowed_pdu = 0x40000f28;\nr_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000f2c;\nr_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40000f30;\nr_ble_ll_ctrl_enc_req_make = 0x40000f34;\nr_ble_ll_ctrl_find_new_phy = 0x40000f38;\nr_ble_ll_ctrl_initiate_dle = 0x40000f3c;\nr_ble_ll_ctrl_is_start_enc_rsp = 0x40000f40;\nr_ble_ll_ctrl_is_terminate_ind = 0x40000f44;\nr_ble_ll_ctrl_len_proc = 0x40000f48;\nr_ble_ll_ctrl_phy_from_phy_mask = 0x40000f4c;\nr_ble_ll_ctrl_phy_req_rsp_make = 0x40000f50;\nr_ble_ll_ctrl_phy_tx_transition_get = 0x40000f54;\nr_ble_ll_ctrl_phy_update_cancel = 0x40000f58;\nr_ble_ll_ctrl_phy_update_ind_make = 0x40000f5c;\nr_ble_ll_ctrl_phy_update_proc_complete = 0x40000f60;\nr_ble_ll_ctrl_proc_init = 0x40000f64;\nr_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000f68;\nr_ble_ll_ctrl_proc_start = 0x40000f6c;\nr_ble_ll_ctrl_proc_stop = 0x40000f70;\nr_ble_ll_ctrl_proc_unk_rsp = 0x40000f74;\nr_ble_ll_ctrl_proc_with_instant_initiated = 0x40000f78;\nr_ble_ll_ctrl_rej_ext_ind_make = 0x40000f7c;\nr_ble_ll_ctrl_reject_ind_send = 0x40000f80;\nr_ble_ll_ctrl_rx_chanmap_req = 0x40000f84;\nr_ble_ll_ctrl_rx_conn_param_req = 0x40000f88;\nr_ble_ll_ctrl_rx_conn_param_rsp = 0x40000f8c;\nr_ble_ll_ctrl_rx_conn_update = 0x40000f90;\nr_ble_ll_ctrl_rx_enc_req = 0x40000f94;\nr_ble_ll_ctrl_rx_enc_rsp = 0x40000f98;\nr_ble_ll_ctrl_rx_feature_req = 0x40000f9c;\nr_ble_ll_ctrl_rx_feature_rsp = 0x40000fa0;\nr_ble_ll_ctrl_rx_pause_enc_req = 0x40000fa4;\nr_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000fa8;\nr_ble_ll_ctrl_rx_pdu = 0x40000fac;\nr_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000fb0;\nr_ble_ll_ctrl_rx_phy_req = 0x40000fb4;\nr_ble_ll_ctrl_rx_phy_rsp = 0x40000fb8;\nr_ble_ll_ctrl_rx_phy_update_ind = 0x40000fbc;\nr_ble_ll_ctrl_rx_ping_rsp = 0x40000fc0;\nr_ble_ll_ctrl_rx_reject_ind = 0x40000fc4;\nr_ble_ll_ctrl_rx_start_enc_req = 0x40000fc8;\nr_ble_ll_ctrl_rx_start_enc_rsp = 0x40000fcc;\nr_ble_ll_ctrl_rx_version_ind = 0x40000fd0;\nr_ble_ll_ctrl_start_enc_send = 0x40000fd4;\nr_ble_ll_ctrl_start_rsp_timer = 0x40000fd8;\nr_ble_ll_ctrl_terminate_start = 0x40000fdc;\nr_ble_ll_ctrl_tx_done = 0x40000fe0;\nr_ble_ll_ctrl_update_features = 0x40000fe4;\nr_ble_ll_ctrl_version_ind_make = 0x40000fe8;\nr_ble_ll_data_buffer_overflow = 0x40000fec;\nr_ble_ll_deinit = 0x40000ff0;\nr_ble_ll_disconn_comp_event_send = 0x40000ff4;\nr_ble_ll_dtm_calculate_itvl = 0x40000ff8;\nr_ble_ll_dtm_ctx_free = 0x40000ffc;\nr_ble_ll_dtm_deinit = 0x40001000;\nr_ble_ll_dtm_end_test = 0x40001004;\nr_ble_ll_dtm_ev_rx_restart_cb = 0x40001008;\nr_ble_ll_dtm_ev_tx_resched_cb = 0x4000100c;\nr_ble_ll_dtm_init = 0x40001010;\nr_ble_ll_dtm_reset = 0x40001014;\nr_ble_ll_dtm_rx_create_ctx = 0x40001018;\nr_ble_ll_dtm_rx_isr_end = 0x4000101c;\nr_ble_ll_dtm_rx_isr_start = 0x40001020;\nr_ble_ll_dtm_rx_pkt_in = 0x40001024;\nr_ble_ll_dtm_rx_sched_cb = 0x40001028;\nr_ble_ll_dtm_rx_start = 0x4000102c;\nr_ble_ll_dtm_rx_test = 0x40001030;\nr_ble_ll_dtm_set_next = 0x40001034;\nr_ble_ll_dtm_tx_create_ctx = 0x40001038;\nr_ble_ll_dtm_tx_done = 0x4000103c;\nr_ble_ll_dtm_tx_sched_cb = 0x40001040;\nr_ble_ll_dtm_tx_test = 0x40001044;\nr_ble_ll_dtm_wfr_timer_exp = 0x40001048;\nr_ble_ll_env_init = 0x4000104c;\nr_ble_ll_event_comp_pkts = 0x40001050;\nr_ble_ll_event_dbuf_overflow = 0x40001054;\nr_ble_ll_event_rx_pkt = 0x40001058;\nr_ble_ll_event_send = 0x4000105c;\nr_ble_ll_event_tx_pkt = 0x40001060;\nr_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40001064;\nr_ble_ll_ext_conn_create = 0x40001068;\nr_ble_ll_ext_scan_coex_dpc_process = 0x4000106c;\nr_ble_ll_ext_scan_coex_dpc_pti_get = 0x40001070;\nr_ble_ll_ext_scan_coex_dpc_update = 0x40001074;\nr_ble_ll_ext_scan_coex_dpc_update_on_start = 0x40001078;\nr_ble_ll_ext_scan_parse_adv_info = 0x4000107c;\nr_ble_ll_ext_scan_parse_aux_ptr = 0x40001080;\nr_ble_ll_flush_pkt_queue = 0x40001084;\nr_ble_ll_generic_data_init = 0x40001088;\nr_ble_ll_get_addr_type = 0x4000108c;\nr_ble_ll_get_chan_to_scan = 0x40001090;\nr_ble_ll_get_our_devaddr = 0x40001094;\nr_ble_ll_get_tx_pwr_compensation = 0x40001098;\nr_ble_ll_hci_acl_rx = 0x4000109c;\nr_ble_ll_hci_adv_mode_ext = 0x400010a0;\nr_ble_ll_hci_adv_set_enable = 0x400010a4;\nr_ble_ll_hci_cb_host_buf_size = 0x400010a8;\nr_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x400010ac;\nr_ble_ll_hci_cb_set_event_mask = 0x400010b0;\nr_ble_ll_hci_cb_set_event_mask2 = 0x400010b4;\nr_ble_ll_hci_chk_phy_masks = 0x400010b8;\nr_ble_ll_hci_cmd_proc = 0x400010bc;\nr_ble_ll_hci_cmd_rx = 0x400010c0;\nr_ble_ll_hci_ctlr_bb_cmd_proc = 0x400010c4;\nr_ble_ll_hci_deinit = 0x400010c8;\nr_ble_ll_hci_disconnect = 0x400010cc;\nr_ble_ll_hci_dtm_rx_test = 0x400010d0;\nr_ble_ll_hci_dtm_rx_test_v2 = 0x400010d4;\nr_ble_ll_hci_dtm_tx_test = 0x400010d8;\nr_ble_ll_hci_dtm_tx_test_ext = 0x400010dc;\nr_ble_ll_hci_dtm_tx_test_v2 = 0x400010e0;\nr_ble_ll_hci_dtm_tx_test_v2_ext = 0x400010e4;\nr_ble_ll_hci_env_init = 0x400010e8;\nr_ble_ll_hci_ev_conn_update = 0x400010ec;\nr_ble_ll_hci_ev_databuf_overflow = 0x400010f0;\nr_ble_ll_hci_ev_datalen_chg = 0x400010f4;\nr_ble_ll_hci_ev_encrypt_chg = 0x400010f8;\nr_ble_ll_hci_ev_hw_err = 0x400010fc;\nr_ble_ll_hci_ev_le_csa = 0x40001100;\nr_ble_ll_hci_ev_ltk_req = 0x40001104;\nr_ble_ll_hci_ev_phy_update = 0x40001108;\nr_ble_ll_hci_ev_rd_rem_used_feat = 0x4000110c;\nr_ble_ll_hci_ev_rd_rem_ver = 0x40001110;\nr_ble_ll_hci_ev_rem_conn_parm_req = 0x40001114;\nr_ble_ll_hci_ev_send_adv_set_terminated = 0x40001118;\nr_ble_ll_hci_ev_send_scan_req_recv = 0x4000111c;\nr_ble_ll_hci_ev_send_scan_timeout = 0x40001120;\nr_ble_ll_hci_ev_send_vendor_err = 0x40001124;\nr_ble_ll_hci_event_send = 0x40001128;\nr_ble_ll_hci_ext_scan_set_enable = 0x4000112c;\nr_ble_ll_hci_get_num_cmd_pkts = 0x40001130;\nr_ble_ll_hci_info_params_cmd_proc = 0x40001134;\nr_ble_ll_hci_init = 0x40001138;\nr_ble_ll_hci_is_event_enabled = 0x4000113c;\nr_ble_ll_hci_is_le_event_enabled = 0x40001140;\nr_ble_ll_hci_le_cmd_proc = 0x40001144;\nr_ble_ll_hci_le_cmd_send_cmd_status = 0x40001148;\nr_ble_ll_hci_le_encrypt = 0x4000114c;\nr_ble_ll_hci_le_rand = 0x40001150;\nr_ble_ll_hci_le_rd_max_data_len = 0x40001154;\nr_ble_ll_hci_le_rd_sugg_data_len = 0x40001158;\nr_ble_ll_hci_le_read_bufsize = 0x4000115c;\nr_ble_ll_hci_le_read_local_features = 0x40001160;\nr_ble_ll_hci_le_read_supp_states = 0x40001164;\nr_ble_ll_hci_le_set_def_phy = 0x40001168;\nr_ble_ll_hci_le_wr_sugg_data_len = 0x4000116c;\nr_ble_ll_hci_link_ctrl_cmd_proc = 0x40001170;\nr_ble_ll_hci_npl_init = 0x40001174;\nr_ble_ll_hci_rd_bd_addr = 0x40001178;\nr_ble_ll_hci_rd_local_supp_cmd = 0x4000117c;\nr_ble_ll_hci_rd_local_supp_feat = 0x40001180;\nr_ble_ll_hci_rd_local_version = 0x40001184;\nr_ble_ll_hci_scan_set_enable = 0x40001188;\nr_ble_ll_hci_send_adv_report = 0x4000118c;\nr_ble_ll_hci_send_dir_adv_report = 0x40001190;\nr_ble_ll_hci_send_ext_adv_report = 0x40001194;\nr_ble_ll_hci_send_legacy_ext_adv_report = 0x40001198;\nr_ble_ll_hci_send_noop = 0x4000119c;\nr_ble_ll_hci_set_adv_data = 0x400011a0;\nr_ble_ll_hci_set_le_event_mask = 0x400011a4;\nr_ble_ll_hci_set_scan_rsp_data = 0x400011a8;\nr_ble_ll_hci_status_params_cmd_proc = 0x400011ac;\nr_ble_ll_hci_vs_cmd_proc = 0x400011b0;\nr_ble_ll_hci_vs_rd_static_addr = 0x400011b4;\nr_ble_ll_hw_err_timer_cb = 0x400011b8;\nr_ble_ll_hw_error = 0x400011bc;\nr_ble_ll_init = 0x400011c0;\nr_ble_ll_init_alloc_conn_comp_ev = 0x400011c4;\nr_ble_ll_init_get_conn_comp_ev = 0x400011c8;\nr_ble_ll_init_rx_isr_end = 0x400011cc;\nr_ble_ll_init_rx_isr_start = 0x400011d0;\nr_ble_ll_init_rx_pkt_in = 0x400011d4;\nr_ble_ll_is_addr_empty = 0x400011d8;\nr_ble_ll_is_controller_busy = 0x400011dc;\nr_ble_ll_is_on_resolv_list = 0x400011e0;\nr_ble_ll_is_our_devaddr = 0x400011e4;\nr_ble_ll_is_rpa = 0x400011e8;\nr_ble_ll_is_valid_adv_mode = 0x400011ec;\nr_ble_ll_is_valid_own_addr_type = 0x400011f0;\nr_ble_ll_is_valid_public_addr = 0x400011f4;\nr_ble_ll_is_valid_random_addr = 0x400011f8;\nr_ble_ll_mbuf_init = 0x400011fc;\nr_ble_ll_misc_options_set = 0x40001200;\nr_ble_ll_pdu_max_tx_octets_get = 0x40001204;\nr_ble_ll_pdu_tx_time_get = 0x40001208;\nr_ble_ll_per_adv_coex_dpc_calc_pti_update_itvl = 0x4000120c;\nr_ble_ll_per_adv_coex_dpc_process = 0x40001210;\nr_ble_ll_per_adv_coex_dpc_pti_get = 0x40001214;\nr_ble_ll_per_adv_coex_dpc_update = 0x40001218;\nr_ble_ll_per_adv_coex_dpc_update_on_data_updated = 0x4000121c;\nr_ble_ll_per_adv_coex_dpc_update_on_scheduled = 0x40001220;\nr_ble_ll_per_adv_coex_dpc_update_on_start = 0x40001224;\nr_ble_ll_phy_to_phy_mode = 0x40001228;\nr_ble_ll_process_rx_data = 0x4000122c;\nr_ble_ll_qa_enable = 0x40001230;\nr_ble_ll_rand = 0x40001234;\nr_ble_ll_rand_data_get = 0x40001238;\nr_ble_ll_rand_deinit = 0x4000123c;\nr_ble_ll_rand_env_init = 0x40001240;\nr_ble_ll_rand_init = 0x40001244;\nr_ble_ll_rand_prand_get = 0x40001248;\nr_ble_ll_rand_sample = 0x4000124c;\nr_ble_ll_rand_start = 0x40001250;\nr_ble_ll_read_rf_path_compensation = 0x40001254;\nr_ble_ll_read_supp_features = 0x40001258;\nr_ble_ll_read_supp_states = 0x4000125c;\nr_ble_ll_read_tx_power = 0x40001260;\nr_ble_ll_reset = 0x40001264;\nr_ble_ll_resolv_clear_all_pl_bit = 0x40001268;\nr_ble_ll_resolv_clear_all_wl_bit = 0x4000126c;\nr_ble_ll_resolv_deinit = 0x40001270;\nr_ble_ll_resolv_enable_cmd = 0x40001274;\nr_ble_ll_resolv_enabled = 0x40001278;\nr_ble_ll_resolv_env_init = 0x4000127c;\nr_ble_ll_resolv_gen_priv_addr = 0x40001280;\nr_ble_ll_resolv_gen_rpa = 0x40001284;\nr_ble_ll_resolv_get_addr_pointer = 0x40001288;\nr_ble_ll_resolv_get_entry = 0x4000128c;\nr_ble_ll_resolv_get_index = 0x40001290;\nr_ble_ll_resolv_get_irk_pointer = 0x40001294;\nr_ble_ll_resolv_get_list = 0x40001298;\nr_ble_ll_resolv_get_priv_addr = 0x4000129c;\nr_ble_ll_resolv_get_rpa_tmo = 0x400012a0;\nr_ble_ll_resolv_init = 0x400012a4;\nr_ble_ll_resolv_irk_nonzero = 0x400012a8;\nr_ble_ll_resolv_list_add = 0x400012ac;\nr_ble_ll_resolv_list_chg_allowed = 0x400012b0;\nr_ble_ll_resolv_list_clr = 0x400012b4;\nr_ble_ll_resolv_list_find = 0x400012b8;\nr_ble_ll_resolv_list_read_size = 0x400012bc;\nr_ble_ll_resolv_list_reset = 0x400012c0;\nr_ble_ll_resolv_list_rmv = 0x400012c4;\nr_ble_ll_resolv_local_addr_rd = 0x400012c8;\nr_ble_ll_resolv_peer_addr_rd = 0x400012cc;\nr_ble_ll_resolv_peer_rpa_any = 0x400012d0;\nr_ble_ll_resolv_reset = 0x400012d4;\nr_ble_ll_resolv_rpa = 0x400012d8;\nr_ble_ll_resolv_rpa_timer_cb = 0x400012dc;\nr_ble_ll_resolv_set_local_rpa = 0x400012e0;\nr_ble_ll_resolv_set_peer_rpa = 0x400012e4;\nr_ble_ll_resolv_set_rpa_tmo = 0x400012e8;\nr_ble_ll_resolve_set_priv_mode = 0x400012ec;\nr_ble_ll_rfmgmt_controller_sleep_en = 0x400012f0;\nr_ble_ll_rfmgmt_deinit = 0x400012f4;\nr_ble_ll_rfmgmt_disable = 0x400012f8;\nr_ble_ll_rfmgmt_enable = 0x400012fc;\nr_ble_ll_rfmgmt_enable_now = 0x40001300;\nr_ble_ll_rfmgmt_init = 0x40001304;\nr_ble_ll_rfmgmt_is_enabled = 0x40001308;\nr_ble_ll_rfmgmt_release = 0x4000130c;\nr_ble_ll_rfmgmt_release_ev = 0x40001310;\nr_ble_ll_rfmgmt_reset = 0x40001314;\nr_ble_ll_rfmgmt_scan_changed = 0x40001318;\nr_ble_ll_rfmgmt_sched_changed = 0x4000131c;\nr_ble_ll_rfmgmt_set_sleep_cb = 0x40001320;\nr_ble_ll_rfmgmt_ticks_to_enabled = 0x40001324;\nr_ble_ll_rfmgmt_timer_exp = 0x40001328;\nr_ble_ll_rfmgmt_timer_reschedule = 0x4000132c;\nr_ble_ll_rx_end = 0x40001330;\nr_ble_ll_rx_pdu_in = 0x40001334;\nr_ble_ll_rx_pkt_in = 0x40001338;\nr_ble_ll_rx_start = 0x4000133c;\nr_ble_ll_rxpdu_alloc = 0x40001340;\nr_ble_ll_scan_add_scan_rsp_adv = 0x40001344;\nr_ble_ll_scan_adv_decode_addr = 0x40001348;\nr_ble_ll_scan_aux_data_free = 0x4000134c;\nr_ble_ll_scan_aux_data_ref = 0x40001350;\nr_ble_ll_scan_aux_data_unref = 0x40001354;\nr_ble_ll_scan_can_chg_whitelist = 0x40001358;\nr_ble_ll_scan_check_periodic_sync = 0x4000135c;\nr_ble_ll_scan_chk_resume = 0x40001360;\nr_ble_ll_scan_clean_cur_aux_data = 0x40001364;\nr_ble_ll_scan_common_init = 0x40001368;\nr_ble_ll_scan_continue_en = 0x4000136c;\nr_ble_ll_scan_deinit = 0x40001370;\nr_ble_ll_scan_dup_check_ext = 0x40001374;\nr_ble_ll_scan_dup_check_legacy = 0x40001378;\nr_ble_ll_scan_dup_move_to_head = 0x4000137c;\nr_ble_ll_scan_dup_new = 0x40001380;\nr_ble_ll_scan_dup_update_ext = 0x40001384;\nr_ble_ll_scan_dup_update_legacy = 0x40001388;\nr_ble_ll_scan_duration_period_timers_restart = 0x4000138c;\nr_ble_ll_scan_duration_timer_cb = 0x40001390;\nr_ble_ll_scan_enabled = 0x40001394;\nr_ble_ll_scan_end_adv_evt = 0x40001398;\nr_ble_ll_scan_env_init = 0x4000139c;\nr_ble_ll_scan_event_proc = 0x400013a0;\nr_ble_ll_scan_ext_adv_init = 0x400013a4;\nr_ble_ll_scan_ext_initiator_start = 0x400013a8;\nr_ble_ll_scan_get_addr_data_from_legacy = 0x400013ac;\nr_ble_ll_scan_get_addr_from_ext_adv = 0x400013b0;\nr_ble_ll_scan_get_cur_sm = 0x400013b4;\nr_ble_ll_scan_get_ext_adv_report = 0x400013b8;\nr_ble_ll_scan_get_local_rpa = 0x400013bc;\nr_ble_ll_scan_get_next_adv_prim_chan = 0x400013c0;\nr_ble_ll_scan_get_pdu_data = 0x400013c4;\nr_ble_ll_scan_get_peer_rpa = 0x400013c8;\nr_ble_ll_scan_halt = 0x400013cc;\nr_ble_ll_scan_has_sent_scan_req = 0x400013d0;\nr_ble_ll_scan_have_rxd_scan_rsp = 0x400013d4;\nr_ble_ll_scan_init = 0x400013d8;\nr_ble_ll_scan_initiator_start = 0x400013dc;\nr_ble_ll_scan_interrupted = 0x400013e0;\nr_ble_ll_scan_interrupted_event_cb = 0x400013e4;\nr_ble_ll_scan_is_inside_window = 0x400013e8;\nr_ble_ll_scan_move_window_to = 0x400013ec;\nr_ble_ll_scan_npl_init = 0x400013f0;\nr_ble_ll_scan_npl_reset = 0x400013f4;\nr_ble_ll_scan_npl_restore = 0x400013f8;\nr_ble_ll_scan_npl_store = 0x400013fc;\nr_ble_ll_scan_parse_ext_hdr = 0x40001400;\nr_ble_ll_scan_period_timer_cb = 0x40001404;\nr_ble_ll_scan_record_new_adv = 0x40001408;\nr_ble_ll_scan_refresh_nrpa = 0x4000140c;\nr_ble_ll_scan_req_backoff = 0x40001410;\nr_ble_ll_scan_reset = 0x40001414;\nr_ble_ll_scan_rx_filter = 0x40001418;\nr_ble_ll_scan_rx_isr_end = 0x4000141c;\nr_ble_ll_scan_rx_isr_on_aux = 0x40001420;\nr_ble_ll_scan_rx_isr_on_legacy = 0x40001424;\nr_ble_ll_scan_rx_isr_start = 0x40001428;\nr_ble_ll_scan_rx_pkt_in = 0x4000142c;\nr_ble_ll_scan_rx_pkt_in_on_aux = 0x40001430;\nr_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001434;\nr_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001438;\nr_ble_ll_scan_rxed = 0x4000143c;\nr_ble_ll_scan_sched_remove = 0x40001440;\nr_ble_ll_scan_send_adv_report = 0x40001444;\nr_ble_ll_scan_send_truncated = 0x40001448;\nr_ble_ll_scan_set_enable = 0x4000144c;\nr_ble_ll_scan_set_peer_rpa = 0x40001450;\nr_ble_ll_scan_set_scan_params = 0x40001454;\nr_ble_ll_scan_sm_start = 0x40001458;\nr_ble_ll_scan_sm_stop = 0x4000145c;\nr_ble_ll_scan_start = 0x40001460;\nr_ble_ll_scan_time_hci_to_ticks = 0x40001464;\nr_ble_ll_scan_timer_cb = 0x40001468;\nr_ble_ll_scan_update_aux_data = 0x4000146c;\nr_ble_ll_scan_wfr_timer_exp = 0x40001470;\nr_ble_ll_scan_whitelist_enabled = 0x40001474;\nr_ble_ll_sched_adv_new = 0x40001478;\nr_ble_ll_sched_adv_resched_pdu = 0x4000147c;\nr_ble_ll_sched_adv_reschedule = 0x40001480;\nr_ble_ll_sched_aux_scan = 0x40001484;\nr_ble_ll_sched_conn_overlap = 0x40001488;\nr_ble_ll_sched_conn_reschedule = 0x4000148c;\nr_ble_ll_sched_deinit = 0x40001490;\nr_ble_ll_sched_dtm = 0x40001494;\nr_ble_ll_sched_env_init = 0x40001498;\nr_ble_ll_sched_execute_item = 0x4000149c;\nr_ble_ll_sched_init = 0x400014a0;\nr_ble_ll_sched_insert_if_empty = 0x400014a4;\nr_ble_ll_sched_is_overlap = 0x400014a8;\nr_ble_ll_sched_master_new = 0x400014ac;\nr_ble_ll_sched_next_time = 0x400014b0;\nr_ble_ll_sched_overlaps_current = 0x400014b4;\nr_ble_ll_sched_periodic_adv = 0x400014b8;\nr_ble_ll_sched_rmv_elem = 0x400014bc;\nr_ble_ll_sched_rmv_elem_type = 0x400014c0;\nr_ble_ll_sched_run = 0x400014c4;\nr_ble_ll_sched_scan_req_over_aux_ptr = 0x400014c8;\nr_ble_ll_sched_slave_new = 0x400014cc;\nr_ble_ll_sched_stop = 0x400014d0;\nr_ble_ll_sched_sync = 0x400014d4;\nr_ble_ll_sched_sync_overlaps_current = 0x400014d8;\nr_ble_ll_sched_sync_reschedule = 0x400014dc;\nr_ble_ll_set_default_privacy_mode = 0x400014e0;\nr_ble_ll_set_default_sync_transfer_params = 0x400014e4;\nr_ble_ll_set_ext_scan_params = 0x400014e8;\nr_ble_ll_set_host_feat = 0x400014ec;\nr_ble_ll_set_public_addr = 0x400014f0;\nr_ble_ll_set_random_addr = 0x400014f4;\nr_ble_ll_set_sync_transfer_params = 0x400014f8;\nr_ble_ll_slave_rx_isr_end = 0x400014fc;\nr_ble_ll_state_get = 0x40001500;\nr_ble_ll_state_set = 0x40001504;\nr_ble_ll_sync_adjust_ext_hdr = 0x40001508;\nr_ble_ll_sync_cancel = 0x4000150c;\nr_ble_ll_sync_cancel_complete_event = 0x40001510;\nr_ble_ll_sync_chain_start_cb = 0x40001514;\nr_ble_ll_sync_check_acad = 0x40001518;\nr_ble_ll_sync_check_failed = 0x4000151c;\nr_ble_ll_sync_coex_dpc_process = 0x40001520;\nr_ble_ll_sync_coex_dpc_pti_get = 0x40001524;\nr_ble_ll_sync_coex_dpc_update = 0x40001528;\nr_ble_ll_sync_create = 0x4000152c;\nr_ble_ll_sync_current_sm_over = 0x40001530;\nr_ble_ll_sync_deinit = 0x40001534;\nr_ble_ll_sync_enabled = 0x40001538;\nr_ble_ll_sync_env_init = 0x4000153c;\nr_ble_ll_sync_est_event_failed = 0x40001540;\nr_ble_ll_sync_est_event_success = 0x40001544;\nr_ble_ll_sync_established = 0x40001548;\nr_ble_ll_sync_event_end = 0x4000154c;\nr_ble_ll_sync_event_start_cb = 0x40001550;\nr_ble_ll_sync_filter_enabled = 0x40001554;\nr_ble_ll_sync_find = 0x40001558;\nr_ble_ll_sync_get_cur_sm = 0x4000155c;\nr_ble_ll_sync_get_event_end_time = 0x40001560;\nr_ble_ll_sync_get_handle = 0x40001564;\nr_ble_ll_sync_halt = 0x40001568;\nr_ble_ll_sync_has_been_reported = 0x4000156c;\nr_ble_ll_sync_info_event = 0x40001570;\nr_ble_ll_sync_init = 0x40001574;\nr_ble_ll_sync_list_add = 0x40001578;\nr_ble_ll_sync_list_clear = 0x4000157c;\nr_ble_ll_sync_list_empty = 0x40001580;\nr_ble_ll_sync_list_get_free = 0x40001584;\nr_ble_ll_sync_list_remove = 0x40001588;\nr_ble_ll_sync_list_search = 0x4000158c;\nr_ble_ll_sync_list_size = 0x40001590;\nr_ble_ll_sync_lost_event = 0x40001594;\nr_ble_ll_sync_next_event = 0x40001598;\nr_ble_ll_sync_on_list = 0x4000159c;\nr_ble_ll_sync_parse_aux_ptr = 0x400015a0;\nr_ble_ll_sync_parse_ext_hdr = 0x400015a4;\nr_ble_ll_sync_periodic_ind = 0x400015a8;\nr_ble_ll_sync_phy_mode_to_aux_phy = 0x400015ac;\nr_ble_ll_sync_phy_mode_to_hci = 0x400015b0;\nr_ble_ll_sync_put_syncinfo = 0x400015b4;\nr_ble_ll_sync_reserve = 0x400015b8;\nr_ble_ll_sync_reset = 0x400015bc;\nr_ble_ll_sync_reset_sm = 0x400015c0;\nr_ble_ll_sync_rmvd_from_sched = 0x400015c4;\nr_ble_ll_sync_rx_isr_end = 0x400015c8;\nr_ble_ll_sync_rx_isr_start = 0x400015cc;\nr_ble_ll_sync_rx_pkt_in = 0x400015d0;\nr_ble_ll_sync_schedule_chain = 0x400015d4;\nr_ble_ll_sync_send_per_adv_rpt = 0x400015d8;\nr_ble_ll_sync_send_sync_ind = 0x400015dc;\nr_ble_ll_sync_send_truncated_per_adv_rpt = 0x400015e0;\nr_ble_ll_sync_sm_clear = 0x400015e4;\nr_ble_ll_sync_terminate = 0x400015e8;\nr_ble_ll_sync_transfer = 0x400015ec;\nr_ble_ll_sync_transfer_get = 0x400015f0;\nr_ble_ll_sync_transfer_received = 0x400015f4;\nr_ble_ll_sync_wfr_timer_exp = 0x400015f8;\nr_ble_ll_task = 0x400015fc;\nr_ble_ll_trace_set_func = 0x40001600;\nr_ble_ll_trace_u32 = 0x40001604;\nr_ble_ll_trace_u32x2 = 0x40001608;\nr_ble_ll_trace_u32x3 = 0x4000160c;\nr_ble_ll_tx_flat_mbuf_pducb = 0x40001610;\nr_ble_ll_tx_mbuf_pducb = 0x40001614;\nr_ble_ll_tx_pkt_in = 0x40001618;\nr_ble_ll_update_max_tx_octets_phy_mode = 0x4000161c;\nr_ble_ll_usecs_to_ticks_round_up = 0x40001620;\nr_ble_ll_utils_calc_access_addr = 0x40001624;\nr_ble_ll_utils_calc_dci_csa2 = 0x40001628;\nr_ble_ll_utils_calc_num_used_chans = 0x4000162c;\nr_ble_ll_utils_calc_window_widening = 0x40001630;\nr_ble_ll_utils_csa2_perm = 0x40001634;\nr_ble_ll_utils_csa2_prng = 0x40001638;\nr_ble_ll_utils_remapped_channel = 0x4000163c;\nr_ble_ll_wfr_timer_exp = 0x40001640;\nr_ble_ll_whitelist_add = 0x40001644;\nr_ble_ll_whitelist_chg_allowed = 0x40001648;\nr_ble_ll_whitelist_clear = 0x4000164c;\nr_ble_ll_whitelist_read_size = 0x40001650;\nr_ble_ll_whitelist_rmv = 0x40001654;\nr_ble_ll_whitelist_search = 0x40001658;\nr_ble_ll_write_rf_path_compensation = 0x4000165c;\nr_ble_phy_access_addr_get = 0x40001660;\nr_ble_phy_bb_bug_is_triggered = 0x40001664;\nr_ble_phy_calculate_rxtx_ifs = 0x40001668;\nr_ble_phy_calculate_rxwindow = 0x4000166c;\nr_ble_phy_calculate_txrx_ifs = 0x40001670;\nr_ble_phy_config_access_addr = 0x40001674;\nr_ble_phy_data_make = 0x40001678;\nr_ble_phy_disable = 0x4000167c;\nr_ble_phy_disable_irq = 0x40001680;\nr_ble_phy_disable_whitening = 0x40001684;\nr_ble_phy_enable_scan_seq_immediately = 0x40001688;\nr_ble_phy_enable_whitening = 0x4000168c;\nr_ble_phy_encrypt_disable = 0x40001690;\nr_ble_phy_env_init = 0x40001694;\nr_ble_phy_get_current_phy = 0x40001698;\nr_ble_phy_get_packet_counter = 0x4000169c;\nr_ble_phy_get_packet_status = 0x400016a0;\nr_ble_phy_get_pyld_time_offset = 0x400016a4;\nr_ble_phy_get_rx_phy_mode = 0x400016a8;\nr_ble_phy_init = 0x400016ac;\nr_ble_phy_isr = 0x400016b0;\nr_ble_phy_max_data_pdu_pyld = 0x400016b4;\nr_ble_phy_mode_config = 0x400016b8;\nr_ble_phy_mode_convert = 0x400016bc;\nr_ble_phy_mode_write = 0x400016c0;\nr_ble_phy_module_deinit = 0x400016c4;\nr_ble_phy_module_init = 0x400016c8;\nr_ble_phy_monitor_bb_sync = 0x400016cc;\nr_ble_phy_need_to_report = 0x400016d0;\nr_ble_phy_pkt_received = 0x400016d4;\nr_ble_phy_reset_bb_monitor = 0x400016d8;\nr_ble_phy_resolv_list_disable = 0x400016dc;\nr_ble_phy_resolv_list_enable = 0x400016e0;\nr_ble_phy_restart_sequence = 0x400016e4;\nr_ble_phy_rfclk_disable = 0x400016e8;\nr_ble_phy_rfclk_enable = 0x400016ec;\nr_ble_phy_rx_is_expected = 0x400016f0;\nr_ble_phy_rxpdu_copy = 0x400016f4;\nr_ble_phy_scan_set_start_time = 0x400016f8;\nr_ble_phy_seq_encrypt_enable = 0x400016fc;\nr_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001700;\nr_ble_phy_sequence_adv_end = 0x40001704;\nr_ble_phy_sequence_copy_rx_flags = 0x40001708;\nr_ble_phy_sequence_end_isr = 0x4000170c;\nr_ble_phy_sequence_get_mode = 0x40001710;\nr_ble_phy_sequence_get_state = 0x40001714;\nr_ble_phy_sequence_init_end = 0x40001718;\nr_ble_phy_sequence_is_running = 0x4000171c;\nr_ble_phy_sequence_is_waiting_rsp = 0x40001720;\nr_ble_phy_sequence_isr_copy_data = 0x40001724;\nr_ble_phy_sequence_master_end = 0x40001728;\nr_ble_phy_sequence_rx_end_isr = 0x4000172c;\nr_ble_phy_sequence_scan_end = 0x40001730;\nr_ble_phy_sequence_single_end = 0x40001734;\nr_ble_phy_sequence_slave_end = 0x40001738;\nr_ble_phy_sequence_tx_end_invoke = 0x4000173c;\nr_ble_phy_sequence_update_conn_params = 0x40001740;\nr_ble_phy_set_adv_sequence = 0x40001744;\nr_ble_phy_set_coex_pti = 0x40001748;\nr_ble_phy_set_dev_address = 0x4000174c;\nr_ble_phy_set_master_sequence = 0x40001750;\nr_ble_phy_set_rx_pwr_compensation = 0x40001754;\nr_ble_phy_set_rxhdr_flags = 0x40001758;\nr_ble_phy_set_rxhdr_info = 0x4000175c;\nr_ble_phy_set_scan_sequence = 0x40001760;\nr_ble_phy_set_single_packet_rx_sequence = 0x40001764;\nr_ble_phy_set_single_packet_tx_sequence = 0x40001768;\nr_ble_phy_set_slave_sequence = 0x4000176c;\nr_ble_phy_set_txend_cb = 0x40001770;\nr_ble_phy_setchan = 0x40001774;\nr_ble_phy_slave_set_start_time = 0x40001778;\nr_ble_phy_state_get = 0x4000177c;\nr_ble_phy_timer_config_start_time = 0x40001780;\nr_ble_phy_timer_start_now = 0x40001784;\nr_ble_phy_timer_stop = 0x40001788;\nr_ble_phy_tx_set_start_time = 0x4000178c;\nr_ble_phy_txpower_round = 0x40001790;\nr_ble_phy_txpwr_set = 0x40001794;\nr_ble_phy_wfr_enable = 0x40001798;\nr_ble_phy_xcvr_state_get = 0x4000179c;\nr_ble_plf_set_log_level = 0x400017a0;\nr_ble_rtc_wake_up_cpu_init = 0x400017a4;\nr_ble_rtc_wake_up_state_clr = 0x400017a8;\nr_bleonly_os_tick_init = 0x400017ac;\nr_bt_rf_coex_cfg_set = 0x400017b0;\nr_bt_rf_coex_coded_txrx_time_upper_lim = 0x400017b4;\nr_bt_rf_coex_dft_pti_set = 0x400017b8;\nr_bt_rf_coex_hook_deinit = 0x400017bc;\nr_bt_rf_coex_hook_init = 0x400017c0;\nr_bt_rf_coex_hook_st_set = 0x400017c4;\nr_bt_rf_coex_hooks_p_set_default = 0x400017c8;\nr_btdm_disable_adv_delay = 0x400017cc;\nr_btdm_switch_phy_coded = 0x400017d0;\nr_esp_wait_disabled = 0x400017d4;\nr_get_be16 = 0x400017d8;\nr_get_be24 = 0x400017dc;\nr_get_be32 = 0x400017e0;\nr_get_be64 = 0x400017e4;\nr_get_le16 = 0x400017e8;\nr_get_le24 = 0x400017ec;\nr_get_le32 = 0x400017f0;\nr_get_le64 = 0x400017f4;\nr_get_local_irk_offset = 0x400017f8;\nr_get_local_rpa_offset = 0x400017fc;\nr_get_max_skip = 0x40001800;\nr_get_peer_id_offset = 0x40001804;\nr_get_peer_irk_offset = 0x40001808;\nr_get_peer_rpa_offset = 0x4000180c;\nr_hal_os_tick_read_tick = 0x40001810;\nr_hal_os_tick_set_exp_tick = 0x40001814;\nr_hal_rtc_intr_init = 0x40001818;\nr_hal_rtc_irq_handler = 0x4000181c;\nr_hal_timer_deinit = 0x40001820;\nr_hal_timer_disable_irq = 0x40001824;\nr_hal_timer_env_init = 0x40001828;\nr_hal_timer_init = 0x4000182c;\nr_hal_timer_process = 0x40001830;\nr_hal_timer_read = 0x40001834;\nr_hal_timer_read_tick = 0x40001838;\nr_hal_timer_set_cb = 0x4000183c;\nr_hal_timer_set_exp_tick = 0x40001840;\nr_hal_timer_start = 0x40001844;\nr_hal_timer_start_at = 0x40001848;\nr_hal_timer_stop = 0x4000184c;\nr_hal_timer_task_start = 0x40001850;\nr_ll_assert = 0x40001854;\nr_mem_init_mbuf_pool = 0x40001858;\nr_mem_malloc_mbuf_pool = 0x4000185c;\nr_mem_malloc_mbufpkt_pool = 0x40001860;\nr_mem_malloc_mempool = 0x40001864;\nr_mem_malloc_mempool_ext = 0x40001868;\nr_mem_malloc_mempool_gen = 0x4000186c;\nr_mem_pullup_obj = 0x40001870;\nr_mem_split_frag = 0x40001874;\nr_os_cputime_delay_ticks = 0x40001878;\nr_os_cputime_delay_usecs = 0x4000187c;\nr_os_cputime_get32 = 0x40001880;\nr_os_cputime_ticks_to_usecs = 0x40001884;\nr_os_cputime_timer_init = 0x40001888;\nr_os_cputime_timer_relative = 0x4000188c;\nr_os_cputime_timer_start = 0x40001890;\nr_os_cputime_timer_stop = 0x40001894;\nr_os_cputime_usecs_to_ticks = 0x40001898;\nr_os_mbuf_adj = 0x4000189c;\nr_os_mbuf_append = 0x400018a0;\nr_os_mbuf_appendfrom = 0x400018a4;\nr_os_mbuf_cmpf = 0x400018a8;\nr_os_mbuf_cmpm = 0x400018ac;\nr_os_mbuf_concat = 0x400018b0;\nr_os_mbuf_copydata = 0x400018b4;\nr_os_mbuf_copyinto = 0x400018b8;\nr_os_mbuf_dup = 0x400018bc;\nr_os_mbuf_extend = 0x400018c0;\nr_os_mbuf_free = 0x400018c4;\nr_os_mbuf_free_chain = 0x400018c8;\nr_os_mbuf_get = 0x400018cc;\nr_os_mbuf_get_pkthdr = 0x400018d0;\nr_os_mbuf_len = 0x400018d4;\nr_os_mbuf_off = 0x400018d8;\nr_os_mbuf_pack_chains = 0x400018dc;\nr_os_mbuf_pool_init = 0x400018e0;\nr_os_mbuf_prepend = 0x400018e4;\nr_os_mbuf_prepend_pullup = 0x400018e8;\nr_os_mbuf_pullup = 0x400018ec;\nr_os_mbuf_trim_front = 0x400018f0;\nr_os_mbuf_widen = 0x400018f4;\nr_os_memblock_from = 0x400018f8;\nr_os_memblock_get = 0x400018fc;\nr_os_memblock_put = 0x40001900;\nr_os_memblock_put_from_cb = 0x40001904;\nr_os_mempool_clear = 0x40001908;\nr_os_mempool_ext_clear = 0x4000190c;\nr_os_mempool_ext_init = 0x40001910;\nr_os_mempool_info_get_next = 0x40001914;\nr_os_mempool_init = 0x40001918;\nr_os_mempool_init_internal = 0x4000191c;\nr_os_mempool_is_sane = 0x40001920;\nr_os_mempool_module_init = 0x40001924;\nr_os_mempool_unregister = 0x40001928;\nr_os_mqueue_get = 0x4000192c;\nr_os_mqueue_init = 0x40001930;\nr_os_mqueue_put = 0x40001934;\nr_os_msys_count = 0x40001938;\nr_os_msys_get = 0x4000193c;\nr_os_msys_get_pkthdr = 0x40001940;\nr_os_msys_num_free = 0x40001944;\nr_os_msys_register = 0x40001948;\nr_os_msys_reset = 0x4000194c;\nr_os_tick_idle = 0x40001950;\nr_pri_phy_valid = 0x40001954;\nr_put_be16 = 0x40001958;\nr_put_be24 = 0x4000195c;\nr_put_be32 = 0x40001960;\nr_put_be64 = 0x40001964;\nr_put_le16 = 0x40001968;\nr_put_le24 = 0x4000196c;\nr_put_le32 = 0x40001970;\nr_put_le64 = 0x40001974;\nr_rtc0_timer_handler = 0x40001978;\nr_rtc1_timer_handler = 0x4000197c;\nr_sdkconfig_get_opts = 0x40001980;\nr_sdkconfig_set_opts = 0x40001984;\nr_sec_phy_valid = 0x40001988;\nr_sub24 = 0x4000198c;\nr_swap_buf = 0x40001990;\nr_swap_in_place = 0x40001994;\n\/* Data (.data, .bss, .rodata) *\/\nble_hci_uart_reset_cmd = 0x3ff4ffe0;\nble_hci_trans_env_p = 0x3fcdffc4;\nble_hci_trans_mode = 0x3fcdfeb8;\nble_ll_adv_env_p = 0x3fcdffc0;\nble_ll_conn_env_p = 0x3fcdffbc;\ng_ble_ll_conn_cth_flow = 0x3fcdffb4;\ng_ble_ll_conn_cth_flow_error_ev = 0x3fcdffb0;\ng_ble_ll_ctrl_pkt_lengths_ro = 0x3ff4ffbc;\nble_ll_dtm_module_env_p = 0x3fcdffac;\nchannel_rf_to_index = 0x3ff4ff94;\ng_ble_ll_dtm_prbs15_data = 0x3ff4fe94;\ng_ble_ll_dtm_prbs9_data = 0x3ff4fd94;\nble_ll_hci_env_p = 0x3fcdffa8;\nble_ll_rand_env_p = 0x3fcdffa4;\nble_ll_resolv_env_p = 0x3fcdffa0;\ng_ble_ll_resolve_hdr = 0x3fcdff98;\ng_device_mode_default = 0x3fcdfeb6;\ng_ble_ll_rfmgmt_data = 0x3fcdff50;\ng_ble_sleep_enter_cb = 0x3fcdff4c;\ng_ble_sleep_exit_cb = 0x3fcdff48;\ng_rfclk_enabled = 0x3fcdff44;\nble_ll_scan_env_p = 0x3fcdff40;\nble_ll_sched_env_p = 0x3fcdff3c;\ng_ble_ll_supp_cmds_ro = 0x3ff4fd64;\nble_ll_sync_env_p = 0x3fcdff38;\ng_ble_sca_ppm_tbl_ro = 0x3ff4fd54;\nble_ll_env_p = 0x3fcdff34;\ng_ble_ll_pdu_header_tx_time_ro = 0x3ff4fd4c;\npriv_config_opts = 0x3fcdfea0;\nble_hci_trans_funcs_ptr = 0x3fcdff30;\nr_ble_stub_funcs_ptr = 0x3fcdff2c;\nr_ext_funcs_p = 0x3fcdff28;\nr_npl_funcs = 0x3fcdff24;\nble_hw_env_p = 0x3fcdff20;\nalready_inited.10221 = 0x3fcdff1c;\nble_phy_module_env_p = 0x3fcdff18;\ng_ble_phy_chan_freq_ro = 0x3ff4fd24;\ng_ble_phy_mode_pkt_start_off_ro = 0x3ff4fd1c;\ng_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fd0c;\ng_ble_phy_t_rxaddrdelay_ro = 0x3ff4fd08;\ng_ble_phy_t_rxenddelay_ro = 0x3ff4fd04;\ng_ble_phy_t_txdelay_ro = 0x3ff4fd00;\ng_ble_phy_t_txenddelay_ro = 0x3ff4fcfc;\ng_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcec;\nhal_timer_env_p = 0x3fcdff14;\ng_hal_os_tick = 0x3fcdff08;\nr_osi_coex_funcs_p = 0x3fcdff04;\nbt_rf_coex_hooks = 0x3fcdfefc;\nbt_rf_coex_hooks_p = 0x3fcdfef8;\ncoex_hook_st_group_tab = 0x3ff4fce0;\ncoex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcdc;\ns_ble_act_count_by_group = 0x3fcdfef4;\ns_ble_coex_st_map = 0x3fcdfee0;\nbt_rf_coex_cfg_cb = 0x3fcdfec4;\nbt_rf_coex_cfg_p = 0x3fcdfec0;\nbt_rf_coex_cfg_rom = 0x3ff4fcc0;\nbt_rf_coex_pti_dft_p = 0x3fcdfebc;\nbt_rf_coex_pti_dft_rom = 0x3fcdfe60;\nconn_dynamic_pti_param_rom = 0x3ff4fca8;\nconn_phy_coded_max_data_time_param_rom = 0x3ff4fca4;\next_adv_dynamic_pti_param_rom = 0x3ff4fc70;\next_scan_dynamic_param_rom = 0x3ff4fc38;\nlegacy_adv_dynamic_pti_param_rom = 0x3ff4fc18;\nper_adv_dynamic_pti_param_rom = 0x3ff4fbfc;\nsync_dynamic_param_rom = 0x3ff4fbe4;\ng_ble_plf_log_level = 0x3fcdfe5c;\ng_msys_pool_list = 0x3fcdfe54;\ng_os_mempool_list = 0x3fcdfe4c;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x40001998;\nRC_GetBlockAckTime = 0x4000199c;\nebuf_list_remove = 0x400019a0;\nesf_buf_alloc = 0x400019a4;\nesf_buf_alloc_dynamic = 0x400019a8;\nesf_buf_recycle = 0x400019ac;\nGetAccess = 0x400019b0;\nhal_mac_is_low_rate_enabled = 0x400019b4;\nhal_mac_tx_get_blockack = 0x400019b8;\nhal_mac_tx_set_ppdu = 0x400019bc;\nic_get_trc = 0x400019c0;\nic_mac_deinit = 0x400019c4;\nic_mac_init = 0x400019c8;\nic_interface_enabled = 0x400019cc;\nis_lmac_idle = 0x400019d0;\nlmacAdjustTimestamp = 0x400019d4;\nlmacDiscardAgedMSDU = 0x400019d8;\nlmacDiscardMSDU = 0x400019dc;\nlmacEndFrameExchangeSequence = 0x400019e0;\nlmacIsIdle = 0x400019e4;\nlmacIsLongFrame = 0x400019e8;\nlmacMSDUAged = 0x400019ec;\nlmacPostTxComplete = 0x400019f0;\nlmacProcessAllTxTimeout = 0x400019f4;\nlmacProcessCollisions = 0x400019f8;\nlmacProcessRxSucData = 0x400019fc;\nlmacReachLongLimit = 0x40001a00;\nlmacReachShortLimit = 0x40001a04;\nlmacRecycleMPDU = 0x40001a08;\nlmacRxDone = 0x40001a0c;\nlmacSetTxFrame = 0x40001a10;\nlmacTxDone = 0x40001a14;\nlmacTxFrame = 0x40001a18;\nmac_tx_set_duration = 0x40001a1c;\nmac_tx_set_htsig = 0x40001a20;\nmac_tx_set_plcp0 = 0x40001a24;\nmac_tx_set_plcp1 = 0x40001a28;\nmac_tx_set_plcp2 = 0x40001a2c;\npm_check_state = 0x40001a30;\npm_disable_dream_timer = 0x40001a34;\npm_disable_sleep_delay_timer = 0x40001a38;\npm_dream = 0x40001a3c;\npm_mac_wakeup = 0x40001a40;\npm_mac_sleep = 0x40001a44;\npm_enable_active_timer = 0x40001a48;\npm_enable_sleep_delay_timer = 0x40001a4c;\npm_local_tsf_process = 0x40001a50;\npm_set_beacon_filter = 0x40001a54;\npm_is_in_wifi_slice_threshold = 0x40001a58;\npm_is_waked = 0x40001a5c;\npm_keep_alive = 0x40001a60;\npm_on_beacon_rx = 0x40001a64;\npm_on_data_rx = 0x40001a68;\npm_on_tbtt = 0x40001a6c;\npm_parse_beacon = 0x40001a70;\npm_process_tim = 0x40001a74;\npm_rx_beacon_process = 0x40001a78;\npm_rx_data_process = 0x40001a7c;\npm_sleep = 0x40001a80;\npm_sleep_for = 0x40001a84;\npm_tbtt_process = 0x40001a88;\nppAMPDU2Normal = 0x40001a8c;\nppAssembleAMPDU = 0x40001a90;\nppCalFrameTimes = 0x40001a94;\nppCalSubFrameLength = 0x40001a98;\nppCalTxAMPDULength = 0x40001a9c;\nppCheckTxAMPDUlength = 0x40001aa0;\nppDequeueRxq_Locked = 0x40001aa4;\nppDequeueTxQ = 0x40001aa8;\nppEmptyDelimiterLength = 0x40001aac;\nppEnqueueRxq = 0x40001ab0;\nppEnqueueTxDone = 0x40001ab4;\nppGetTxQFirstAvail_Locked = 0x40001ab8;\nppGetTxframe = 0x40001abc;\nppMapTxQueue = 0x40001ac0;\nppProcTxSecFrame = 0x40001ac4;\nppProcessRxPktHdr = 0x40001ac8;\nppProcessTxQ = 0x40001acc;\nppRecordBarRRC = 0x40001ad0;\nlmacRequestTxopQueue = 0x40001ad4;\nlmacReleaseTxopQueue = 0x40001ad8;\nppRecycleAmpdu = 0x40001adc;\nppRecycleRxPkt = 0x40001ae0;\nppResortTxAMPDU = 0x40001ae4;\nppResumeTxAMPDU = 0x40001ae8;\n\/* ppRxFragmentProc = 0x40001aec; *\/\nppRxPkt = 0x40001af0;\nppRxProtoProc = 0x40001af4;\nppSearchTxQueue = 0x40001af8;\nppSearchTxframe = 0x40001afc;\nppSelectNextQueue = 0x40001b00;\nppSubFromAMPDU = 0x40001b04;\nppTask = 0x40001b08;\nppTxPkt = 0x40001b0c;\nppTxProtoProc = 0x40001b10;\nppTxqUpdateBitmap = 0x40001b14;\npp_coex_tx_request = 0x40001b18;\npp_hdrsize = 0x40001b1c;\npp_post = 0x40001b20;\npp_process_hmac_waiting_txq = 0x40001b24;\nrcGetAmpduSched = 0x40001b28;\nrcUpdateRxDone = 0x40001b2c;\nrc_get_trc = 0x40001b30;\nrc_get_trc_by_index = 0x40001b34;\nrcAmpduLowerRate = 0x40001b38;\nrcampduuprate = 0x40001b3c;\nrcClearCurAMPDUSched = 0x40001b40;\nrcClearCurSched = 0x40001b44;\nrcClearCurStat = 0x40001b48;\nrcGetSched = 0x40001b4c;\nrcLowerSched = 0x40001b50;\nrcSetTxAmpduLimit = 0x40001b54;\nrcTxUpdatePer = 0x40001b58;\nrcUpdateAckSnr = 0x40001b5c;\nrcUpdateRate = 0x40001b60;\nrcUpdateTxDone = 0x40001b64;\nrcUpdateTxDoneAmpdu2 = 0x40001b68;\nrcUpSched = 0x40001b6c;\nrssi_margin = 0x40001b70;\nrx11NRate2AMPDULimit = 0x40001b74;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001b78;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001b7c;\ntrc_calc_duration = 0x40001b80;\ntrc_isTxAmpduOperational = 0x40001b84;\ntrc_onAmpduOp = 0x40001b88;\nTRC_PER_IS_GOOD = 0x40001b8c;\ntrc_SetTxAmpduState = 0x40001b90;\ntrc_tid_isTxAmpduOperational = 0x40001b94;\ntrcAmpduSetState = 0x40001b98;\nwDevCheckBlockError = 0x40001b9c;\nwDev_AppendRxBlocks = 0x40001ba0;\nwDev_DiscardFrame = 0x40001ba4;\nwDev_GetNoiseFloor = 0x40001ba8;\nwDev_IndicateAmpdu = 0x40001bac;\nwDev_IndicateFrame = 0x40001bb0;\nwdev_bank_store = 0x40001bb4;\nwdev_bank_load = 0x40001bb8;\nwdev_mac_reg_load = 0x40001bbc;\nwdev_mac_reg_store = 0x40001bc0;\nwdev_mac_special_reg_load = 0x40001bc4;\nwdev_mac_special_reg_store = 0x40001bc8;\nwdev_mac_wakeup = 0x40001bcc;\nwdev_mac_sleep = 0x40001bd0;\nwDev_ProcessFiq = 0x40001bd4;\nwDev_ProcessRxSucData = 0x40001bd8;\nwdevProcessRxSucDataAll = 0x40001bdc;\nwdev_csi_len_align = 0x40001be0;\nppDequeueTxDone_Locked = 0x40001be4;\nppProcTxDone = 0x40001be8;\npm_tx_data_done_process = 0x40001bec;\nconfig_is_cache_tx_buf_enabled = 0x40001bf0;\nppMapWaitTxq = 0x40001bf4;\nppProcessWaitingQueue = 0x40001bf8;\nppDisableQueue = 0x40001bfc;\npm_allow_tx = 0x40001c00;\nwdev_is_data_in_rxlist = 0x40001c04;\nppProcTxCallback = 0x40001c08;\npm_is_open = 0x40001c0c;\npm_wake_up = 0x40001c10;\npm_wake_done = 0x40001c14;\npm_disable_disconnected_sleep_delay_timer = 0x40001c18;\npm_enable_disconnected_sleep_delay_timer = 0x40001c1c;\nhal_mac_get_txq_state = 0x40001c20;\nhal_mac_clr_txq_state = 0x40001c24;\nhal_mac_tx_set_cca = 0x40001c28;\nhal_mac_set_txq_invalid = 0x40001c2c;\nhal_mac_txq_disable = 0x40001c30;\nhal_mac_is_txq_enabled = 0x40001c34;\nhal_mac_get_txq_pmd = 0x40001c38;\nlmacDiscardFrameExchangeSequence = 0x40001c3c;\nlmacDisableTransmit = 0x40001c40;\nlmacProcessTxTimeout = 0x40001c44;\nlmacProcessTxSuccess = 0x40001c48;\nlmacProcessCollision = 0x40001c4c;\nlmacProcessTxRtsError = 0x40001c50;\nlmacProcessCtsTimeout = 0x40001c54;\nlmacProcessTxComplete = 0x40001c58;\nlmacProcessAckTimeout = 0x40001c5c;\nlmacProcessTxError = 0x40001c60;\nlmacProcessTxseckiderr = 0x40001c64;\nrcReachRetryLimit = 0x40001c68;\nlmacProcessShortRetryFail = 0x40001c6c;\nlmacEndRetryAMPDUFail = 0x40001c70;\nppFillAMPDUBar = 0x40001c74;\nrcGetRate = 0x40001c78;\nppReSendBar = 0x40001c7c;\nlmacProcessLongRetryFail = 0x40001c80;\nlmacRetryTxFrame = 0x40001c84;\nlmacProcessCollisions_task = 0x40001c88;\nlmacProcessTxopQComplete = 0x40001c8c;\nlmacInitAc = 0x40001c90;\nlmacInit = 0x40001c94;\nmac_tx_set_txop_q = 0x40001c98;\nhal_init = 0x40001c9c;\nhal_mac_rx_set_policy = 0x40001ca0;\nhal_mac_set_bssid = 0x40001ca4;\nmac_rx_policy_init = 0x40001ca8;\nmac_txrx_init = 0x40001cac;\nmac_rxbuf_init = 0x40001cb0;\nmac_last_rxbuf_init = 0x40001cb4;\nhal_attenna_init = 0x40001cb8;\nhal_timer_update_by_rtc = 0x40001cbc;\nhal_coex_pti_init = 0x40001cc0;\nlmac_stop_hw_txq = 0x40001cc4;\nppDirectRecycleAmpdu = 0x40001cc8;\nesp_wifi_internal_set_rts = 0x40001ccc;\nesp_wifi_internal_get_rts = 0x40001cd0;\nppTxFragmentProc = 0x40001cd4;\nesf_buf_setup = 0x40001cd8;\nhal_agreement_add_rx_ba = 0x40001cdc;\nhal_agreement_del_rx_ba = 0x40001ce0;\nhal_crypto_set_key_entry = 0x40001ce4;\nhal_crypto_get_key_entry = 0x40001ce8;\nhal_crypto_clr_key_entry = 0x40001cec;\nconfig_get_wifi_task_stack_size = 0x40001cf0;\npp_create_task = 0x40001cf4;\nhal_set_sta_tsf_wakeup = 0x40001cf8;\nhal_set_rx_beacon_pti = 0x40001cfc;\npm_start = 0x40001d00;\npm_stop = 0x40001d04;\nhal_disable_sta_tbtt = 0x40001d08;\nppCalTxopDur = 0x40001d0c;\nwDev_IndicateCtrlFrame = 0x40001d10;\nhal_enable_sta_tbtt = 0x40001d14;\nhal_set_sta_tbtt = 0x40001d18;\npm_update_next_tbtt = 0x40001d1c;\npm_set_sleep_type = 0x40001d20;\nwDev_Rxbuf_Init = 0x40001d24;\nwDev_Rxbuf_Deinit = 0x40001d28;\nppCalTkipMic = 0x40001d2c;\n\/\/wDev_SnifferRxData = 0x40001d30;\nhal_crypto_enable = 0x40001d34;\nhal_crypto_disable = 0x40001d38;\nwDev_Insert_KeyEntry = 0x40001d3c;\nwDev_remove_KeyEntry = 0x40001d40;\nrc_enable_trc = 0x40001d44;\nrc_set_per_conn_fix_rate = 0x40001d48;\nwdev_csi_rx_process = 0x40001d4c;\nwDev_SnifferRxAmpdu = 0x40001d50;\nhal_mac_tsf_reset = 0x40001d54;\ndbg_lmac_statis_dump = 0x40001d58;\ndbg_lmac_rxtx_statis_dump = 0x40001d5c;\ndbg_lmac_hw_statis_dump = 0x40001d60;\ndbg_lmac_diag_statis_dump = 0x40001d64;\ndbg_lmac_ps_statis_dump = 0x40001d68;\npp_timer_do_process = 0x40001d6c;\nrcUpdateAMPDUParam = 0x40001d70;\nrcUpdatePhyMode = 0x40001d74;\nrcGetHighestRateIdx = 0x40001d78;\npm_tx_null_data_done_process = 0x40001d7c;\npm_tx_data_process = 0x40001d80;\npm_attach = 0x40001d84;\npm_coex_schm_process = 0x40001d88;\nppInitTxq = 0x40001d8c;\npp_attach = 0x40001d90;\npp_deattach = 0x40001d94;\npm_on_probe_resp_rx = 0x40001d98;\nhal_set_sta_tsf = 0x40001d9c;\nic_update_sta_tsf = 0x40001da0;\nic_tx_pkt = 0x40001da4;\npm_send_probe_stop = 0x40001da8;\nsta_pm_phy_ref_release = 0x40001dac;\nsta_pm_phy_ref_acquire = 0x40001db0;\npm_send_probe_start = 0x40001db4;\npm_on_coex_schm_process_restart = 0x40001db8;\nhal_mac_set_rxq_policy = 0x40001dbc;\nhal_sniffer_enable = 0x40001dc0;\nhal_sniffer_disable = 0x40001dc4;\nhal_sniffer_rx_set_promis = 0x40001dc8;\nhal_sniffer_rx_clr_statistics = 0x40001dcc;\nhal_sniffer_set_promis_misc_pkt = 0x40001dd0;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff4fbe0;\npTxRx = 0x3fcdfe48;\nlmacConfMib_ptr = 0x3fcdfe44;\nour_wait_eb = 0x3fcdfe40;\nour_tx_eb = 0x3fcdfe3c;\npp_wdev_funcs = 0x3fcdfe38;\ng_osi_funcs_p = 0x3fcdfe34;\nwDevCtrl_ptr = 0x3fcdfe30;\ng_wdev_last_desc_reset_ptr = 0x3ff4fbdc;\nwDevMacSleep_ptr = 0x3fcdfe2c;\ng_lmac_cnt_ptr = 0x3fcdfe28;\nour_controls_ptr = 0x3ff4fbd8;\npp_sig_cnt_ptr = 0x3fcdfe24;\ng_eb_list_desc_ptr = 0x3fcdfe20;\ns_fragment_ptr = 0x3fcdfe1c;\nif_ctrl_ptr = 0x3fcdfe18;\ng_intr_lock_mux = 0x3fcdfe14;\ng_wifi_global_lock = 0x3fcdfe10;\ns_wifi_queue = 0x3fcdfe0c;\npp_task_hdl = 0x3fcdfe08;\ns_pp_task_create_sem = 0x3fcdfe04;\ns_pp_task_del_sem = 0x3fcdfe00;\ng_wifi_menuconfig_ptr = 0x3fcdfdfc;\nxphyQueue = 0x3fcdfdf8;\nap_no_lr_ptr = 0x3fcdfdf4;\nrc11BSchedTbl_ptr = 0x3fcdfdf0;\nrc11NSchedTbl_ptr = 0x3fcdfdec;\nrcLoRaSchedTbl_ptr = 0x3fcdfde8;\nBasicOFDMSched_ptr = 0x3fcdfde4;\ntrc_ctl_ptr = 0x3fcdfde0;\ng_pm_cnt_ptr = 0x3fcdfddc;\ng_pm_ptr = 0x3fcdfdd8;\ng_pm_cfg_ptr = 0x3fcdfdd4;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdfdd0;\ng_txop_queue_status_ptr = 0x3fcdfdcc;\ng_mac_sleep_en_ptr = 0x3fcdfdc8;\ng_mesh_is_root_ptr = 0x3fcdfdc4;\ng_mesh_topology_ptr = 0x3fcdfdc0;\ng_mesh_init_ps_type_ptr = 0x3fcdfdbc;\ng_mesh_is_started_ptr = 0x3fcdfdb8;\ng_config_func = 0x3fcdfdb4;\ng_net80211_tx_func = 0x3fcdfdb0;\ng_timer_func = 0x3fcdfdac;\ns_michael_mic_failure_cb = 0x3fcdfda8;\nwifi_sta_rx_probe_req = 0x3fcdfda4;\ng_tx_done_cb_func = 0x3fcdfda0;\ng_per_conn_trc = 0x3fcdfd84;\ns_encap_amsdu_func = 0x3fcdfd80;\nbars = 0x3fcdfce0;\neb_txdesc_space = 0x3fcdfc50;\neb_space = 0x3fcdfbb0;\ng_pd_mac_in_light_sleep = 0x3fcdfbac;\ns_fix_rate_mask = 0x3fcdfba8;\ns_fix_rate = 0x3fcdfba0;\ng_wdev_csi_rx = 0x3fcdfb9c;\ng_wdev_csi_rx_ctx = 0x3fcdfb98;\nBcnSendTick = 0x3fcdfb94;\ng_pp_timer_info_ptr = 0x3fcdfb90;\nrcP2P11NSchedTbl_ptr = 0x3fcdfb8c;\nrcP2P11GSchedTbl_ptr = 0x3fcdfb88;\nrc11GSchedTbl_ptr = 0x3fcdfb84;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001dd4;\nampdu_dispatch = 0x40001dd8;\nampdu_dispatch_all = 0x40001ddc;\nampdu_dispatch_as_many_as_possible = 0x40001de0;\nampdu_dispatch_movement = 0x40001de4;\nampdu_dispatch_upto = 0x40001de8;\nchm_is_at_home_channel = 0x40001dec;\ncnx_node_is_existing = 0x40001df0;\ncnx_node_search = 0x40001df4;\nic_ebuf_recycle_rx = 0x40001df8;\nic_ebuf_recycle_tx = 0x40001dfc;\nic_reset_rx_ba = 0x40001e00;\nieee80211_align_eb = 0x40001e04;\nieee80211_ampdu_reorder = 0x40001e08;\nieee80211_ampdu_start_age_timer = 0x40001e0c;\nieee80211_encap_esfbuf = 0x40001e10;\nieee80211_is_tx_allowed = 0x40001e14;\nieee80211_output_pending_eb = 0x40001e18;\nieee80211_output_process = 0x40001e1c;\nieee80211_set_tx_desc = 0x40001e20;\nsta_input = 0x40001e24;\nwifi_get_macaddr = 0x40001e28;\nwifi_rf_phy_disable = 0x40001e2c;\nwifi_rf_phy_enable = 0x40001e30;\nic_ebuf_alloc = 0x40001e34;\nieee80211_classify = 0x40001e38;\nieee80211_copy_eb_header = 0x40001e3c;\nieee80211_recycle_cache_eb = 0x40001e40;\nieee80211_search_node = 0x40001e44;\nroundup2 = 0x40001e48;\nieee80211_crypto_encap = 0x40001e4c;\nieee80211_crypto_decap = 0x40001e50;\nieee80211_decap = 0x40001e54;\nieee80211_set_tx_pti = 0x40001e58;\nwifi_is_started = 0x40001e5c;\nieee80211_gettid = 0x40001e60;\nieee80211_ccmp_decrypt = 0x40001e64;\nccmp_encap = 0x40001e6c;\nccmp_decap = 0x40001e70;\ntkip_encap = 0x40001e74;\ntkip_decap = 0x40001e78;\nwep_encap = 0x40001e7c;\nwep_decap = 0x40001e80;\ndbg_hmac_rxtx_statis_dump = 0x40001e84;\ndbg_hmac_statis_dump = 0x40001e88;\nieee80211_send_action_vendor_spec = 0x40001e8c;\nieee80211_send_mgmt = 0x40001e90;\nieee80211_auth_construct = 0x40001e94;\nieee80211_vnd_lora_ie_size = 0x40001ea0;\nieee80211_vnd_ie_size = 0x40001ea4;\nieee80211_add_ssid = 0x40001ea8;\nieee80211_add_rates = 0x40001eac;\nieee80211_add_xrates = 0x40001eb0;\nieee80211_is_ht_cipher = 0x40001eb4;\nieee80211_assoc_req_construct = 0x40001eb8;\nieee80211_setup_lr_rates = 0x40001ec0;\nieee80211_ht_node_init = 0x40001ec4;\nieee80211_is_support_rate = 0x40001ec8;\nieee80211_setup_rates = 0x40001ecc;\nieee80211_is_lr_only = 0x40001ed0;\nieee80211_setup_phy_mode = 0x40001ed4;\nieee80211_sta_is_connected = 0x40001ed8;\ncurrent_task_is_wifi_task = 0x40001edc;\nwifi_get_init_state = 0x40001ee0;\nieee80211_timer_process = 0x40001ee4;\ncnx_coexist_timeout = 0x40001ee8;\nsta_recv_mgmt = 0x40001eec;\nieee80211_send_setup = 0x40001ef0;\nieee80211_send_probereq = 0x40001ef4;\nsta_auth_open = 0x40001ef8;\nsta_auth_shared = 0x40001efc;\nsta_auth_sae = 0x40001f00;\ncnx_coexist_timeout_process = 0x40001f04;\nieee80211_alloc_challenge = 0x40001f08;\ncnx_assoc_timeout = 0x40001f0c;\nieee80211_vnd_ie_set = 0x40001f10;\nieee80211_vnd_lora_ie_set = 0x40001f14;\nieee80211_add_wme_param = 0x40001f18;\nieee80211_add_dsparams = 0x40001f1c;\nieee80211_add_csa = 0x40001f20;\nieee80211_add_extcap = 0x40001f24;\nieee80211_regdomain_get_country = 0x40001f28;\nieee80211_add_countryie = 0x40001f2c;\nieee80211_alloc_proberesp = 0x40001f30;\nieee80211_amsdu_adjust_head = 0x40001f34;\nieee80211_amsdu_adjust_last_length = 0x40001f38;\nieee80211_amsdu_send_check = 0x40001f3c;\nieee80211_amsdu_encap_check = 0x40001f40;\nieee80211_amsdu_length_check = 0x40001f44;\nieee80211_encap_amsdu = 0x40001f48;\nieee80211_output_raw_process = 0x40001f4c;\nesp_wifi_80211_tx = 0x40001f50;\nieee80211_raw_frame_sanity_check = 0x40001f54;\nieee80211_crypto_aes_128_cmac_encrypt = 0x40001f58;\nieee80211_crypto_aes_128_cmac_decrypt = 0x40001f5c;\nieee80211_alloc_tx_buf = 0x40001f60;\nieee80211_output_do = 0x40001f64;\nieee80211_send_nulldata = 0x40001f68;\nieee80211_setup_robust_mgmtframe = 0x40001f6c;\nieee80211_encap_null_data = 0x40001f74;\nieee80211_send_deauth = 0x40001f78;\nieee80211_alloc_deauth = 0x40001f7c;\nieee80211_send_proberesp = 0x40001f80;\nieee80211_tx_mgt_cb = 0x40001f84;\nieee80211_getcapinfo = 0x40001f88;\nsta_rx_csa = 0x40001f8c;\nsta_send_sa_query_req = 0x40001f90;\nsta_send_sa_query_resp = 0x40001f94;\nsta_recv_sa_query_req = 0x40001f98;\nsta_recv_sa_query_resp = 0x40001f9c;\nieee80211_parse_beacon = 0x40001fa0;\nieee80211_set_max_rate = 0x40001fa4;\nic_set_sta = 0x40001fa8;\nieee80211_match_security = 0x40001fac;\nieee80211_parse_wpa = 0x40001fb0;\nieee80211_parse_rsn = 0x40001fb4;\nieee80211_add_assoc_req_ies = 0x40001fb8;\nieee80211_add_probe_req_ies = 0x40001fbc;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdfb80;\ng_scan = 0x3fcdfb7c;\ng_chm = 0x3fcdfb78;\ng_ic_ptr = 0x3fcdfb74;\ng_hmac_cnt_ptr = 0x3fcdfb50;\ng_tx_cacheq_ptr = 0x3fcdfb70;\ns_netstack_free = 0x3fcdfb6c;\nmesh_rxcb = 0x3fcdfb68;\nsta_rxcb = 0x3fcdfb64;\nccmp_ptr = 0x3fcdfb60;\ns_wifi_nvs_ptr = 0x3fcdfb5c;\ntkip_ptr = 0x3fcdfb58;\nwep_ptr = 0x3fcdfb54;\ng_hmac_cnt_ptr = 0x3fcdfb50;\ng_misc_nvs = 0x3fcdfb4c;\ns_wifi_init_state = 0x3fcdfb1c;\ns_wifi_task_hdl = 0x3fcdfb48;\nin_rssi_adjust = 0x3fcdfb44;\nrssi_saved = 0x3fcdfb3c;\nrssi_index = 0x3fcdfb38;\ns_sa_query_retries = 0x3fcdfb34;\ns_sa_query_success = 0x3fcdfb31;\ng_sta_connected_flag = 0x3fcdfb30;\nwpa_crypto_funcs_ptr = 0x3fcdfb2c;\ns_netstack_ref = 0x3fcdfb28;\nsta_csa_timer_ptr = 0x3fcdfb24;\ns_trans_id = 0x3fcdfb20;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x40001fc0;\ncoex_bt_release = 0x40001fc4;\ncoex_bt_request = 0x40001fc8;\ncoex_core_ble_conn_dyn_prio_get = 0x40001fcc;\ncoex_core_event_duration_get = 0x40001fd0;\ncoex_core_pti_get = 0x40001fd4;\ncoex_core_release = 0x40001fd8;\ncoex_core_request = 0x40001fdc;\ncoex_core_status_get = 0x40001fe0;\ncoex_core_timer_idx_get = 0x40001fe4;\ncoex_event_duration_get = 0x40001fe8;\ncoex_hw_timer_disable = 0x40001fec;\ncoex_hw_timer_enable = 0x40001ff0;\ncoex_hw_timer_set = 0x40001ff4;\ncoex_schm_interval_set = 0x40001ff8;\ncoex_schm_lock = 0x40001ffc;\ncoex_schm_unlock = 0x40002000;\ncoex_status_get = 0x40002004;\ncoex_wifi_release = 0x40002008;\nesp_coex_ble_conn_dynamic_prio_get = 0x4000200c;\ncoex_hw_timer_tick_get = 0x40002010;\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdfb18;\ncoex_pti_tab_ptr = 0x3fcdfb14;\ncoex_schm_env_ptr = 0x3fcdfb10;\ncoexist_funcs = 0x3fcdfb0c;\ng_coa_funcs_p = 0x3fcdfb08;\ng_coex_param_ptr = 0x3fcdfb04;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_param_addr = 0x40002014;\nphy_get_romfuncs = 0x40002018;\nchip729_phyrom_version = 0x4000201c;\nchip729_phyrom_version_num = 0x40002020;\nrom_get_bias_ref_code = 0x40002024;\nget_rc_dout = 0x40002028;\nrc_cal = 0x4000202c;\nphy_analog_delay_cal = 0x40002030;\nRFChannelSel = 0x40002034;\nphy_change_channel = 0x40002038;\nphy_set_most_tpw = 0x4000203c;\nphy_rx_rifs_en = 0x40002040;\nphy_get_most_tpw = 0x40002044;\nesp_tx_state_out = 0x40002048;\nphy_get_adc_rand = 0x4000204c;\nphy_internal_delay = 0x40002050;\nphy_ftm_comp = 0x40002054;\nphy_11p_set = 0x40002058;\nphy_current_level_set = 0x4000205c;\nphy_bbpll_en_usb = 0x40002060;\nphy_bt_power_track = 0x40002064;\nrom_enter_critical_phy = 0x40002068;\nrom_exit_critical_phy = 0x4000206c;\nrom_bb_bss_cbw40 = 0x40002070;\nrom_set_chan_reg = 0x40002074;\nabs_temp = 0x40002078;\nset_chan_cal_interp = 0x4000207c;\nloopback_mode_en = 0x40002080;\nget_data_sat = 0x40002084;\nphy_byte_to_word = 0x40002088;\nphy_get_rx_freq = 0x4000208c;\ni2c_master_reset = 0x40002090;\nchan14_mic_enable = 0x40002094;\nchan14_mic_cfg = 0x40002098;\nset_adc_rand = 0x4000209c;\nwr_rf_freq_mem = 0x400020a0;\nfreq_i2c_write_set = 0x400020a4;\nwrite_pll_cap_mem = 0x400020a8;\nget_rf_freq_cap = 0x400020ac;\nget_rf_freq_init = 0x400020b0;\nfreq_get_i2c_data = 0x400020b4;\nfreq_i2c_data_write = 0x400020b8;\nset_chan_freq_hw_init = 0x400020bc;\nphy_en_hw_set_freq = 0x400020c0;\nphy_dis_hw_set_freq = 0x400020c4;\nregister_chipv7_phy_init_param = 0x400020c8;\nphy_reg_init = 0x400020cc;\nphy_xpd_rf = 0x400020d0;\nphy_close_rf = 0x400020d4;\nrf_cal_data_recovery = 0x400020d8;\nrf_cal_data_backup = 0x400020dc;\nphy_rfcal_data_check = 0x400020e0;\nrom_pwdet_sar2_init = 0x400020e4;\nrom_en_pwdet = 0x400020e8;\nrom_get_sar_sig_ref = 0x400020ec;\nrom_pwdet_tone_start = 0x400020f0;\nrom_get_tone_sar_dout = 0x400020f4;\nrom_get_fm_sar_dout = 0x400020f8;\nrom_txtone_linear_pwr = 0x400020fc;\nrom_get_power_db = 0x40002100;\nrom_meas_tone_pwr_db = 0x40002104;\nrom_pkdet_vol_start = 0x40002108;\nrom_read_sar_dout = 0x4000210c;\nrom_read_sar2_code = 0x40002110;\nrom_get_sar2_vol = 0x40002114;\nrom_get_pll_vol = 0x40002118;\nrom_tx_pwctrl_bg_init = 0x4000211c;\nrom_phy_pwdet_always_en = 0x40002120;\nrom_phy_pwdet_onetime_en = 0x40002124;\nlinear_to_db = 0x40002128;\nrom_get_pll_ref_code = 0x4000212c;\nmhz2ieee = 0x40002130;\nchan_to_freq = 0x40002134;\nrestart_cal = 0x40002138;\nwrite_rfpll_sdm = 0x4000213c;\nwait_rfpll_cal_end = 0x40002140;\nrfpll_set_freq = 0x40002144;\nset_rf_freq_offset = 0x40002148;\nset_channel_rfpll_freq = 0x4000214c;\nset_rfpll_freq = 0x40002150;\nphy_set_freq = 0x40002154;\ncorrect_rfpll_offset = 0x40002158;\nset_chan_freq_sw_start = 0x4000215c;\npll_vol_cal = 0x40002160;\nwrite_pll_cap = 0x40002164;\nread_pll_cap = 0x40002168;\nchip_v7_set_chan_misc = 0x4000216c;\nchip_v7_set_chan = 0x40002170;\nchip_v7_set_chan_offset = 0x40002174;\nchip_v7_set_chan_ana = 0x40002178;\nset_chanfreq = 0x4000217c;\ngen_rx_gain_table = 0x40002180;\nwr_rx_gain_mem = 0x40002184;\nset_rx_gain_param = 0x40002188;\nset_rx_gain_table = 0x4000218c;\nbt_track_pll_cap = 0x40002190;\nwifi_track_pll_cap = 0x40002194;\nphy_param_track = 0x40002198;\ntxpwr_correct = 0x4000219c;\ntxpwr_cal_track = 0x400021a0;\ntx_pwctrl_background = 0x400021a4;\nbt_track_tx_power = 0x400021a8;\nwifi_track_tx_power = 0x400021ac;\nbt_txdc_cal = 0x400021b0;\nbt_txiq_cal = 0x400021b4;\ntxiq_cal_init = 0x400021b8;\nget_txcap_data = 0x400021bc;\ntxdc_cal_init = 0x400021c0;\ntxdc_cal_v70 = 0x400021c4;\ntxiq_get_mis_pwr = 0x400021c8;\ntxiq_cover = 0x400021cc;\nrfcal_txiq = 0x400021d0;\nget_power_atten = 0x400021d4;\npwdet_ref_code = 0x400021d8;\npwdet_code_cal = 0x400021dc;\nrfcal_txcap = 0x400021e0;\ntx_cap_init = 0x400021e4;\nrfcal_pwrctrl = 0x400021e8;\ntx_pwctrl_init_cal = 0x400021ec;\ntx_pwctrl_init = 0x400021f0;\nbt_tx_pwctrl_init = 0x400021f4;\nbt_txpwr_freq = 0x400021f8;\nrom_get_i2c_read_mask = 0x400021fc;\nrom_get_i2c_mst0_mask = 0x40002200;\nrom_get_i2c_hostid = 0x40002204;\nrom_chip_i2c_readReg_org = 0x40002208;\nrom_chip_i2c_readReg = 0x4000220c;\nrom_i2c_paral_set_mst0 = 0x40002210;\nrom_i2c_paral_set_read = 0x40002214;\nrom_i2c_paral_read = 0x40002218;\nrom_i2c_paral_write = 0x4000221c;\nrom_i2c_paral_write_num = 0x40002220;\nrom_i2c_paral_write_mask = 0x40002224;\nrom_i2c_readReg = 0x40002228;\nrom_chip_i2c_writeReg = 0x4000222c;\nrom_i2c_writeReg = 0x40002230;\nrom_i2c_readReg_Mask = 0x40002234;\nrom_i2c_writeReg_Mask = 0x40002238;\nrom_set_txcap_reg = 0x4000223c;\ni2c_sar2_init_code = 0x40002240;\nphy_i2c_init1 = 0x40002244;\nphy_i2c_init2 = 0x40002248;\nphy_get_i2c_data = 0x4000224c;\nbias_reg_set = 0x40002250;\ni2c_bbpll_set = 0x40002254;\nrom_pbus_force_mode = 0x40002258;\nrom_pbus_rd_addr = 0x4000225c;\nrom_pbus_rd_shift = 0x40002260;\nrom_pbus_force_test = 0x40002264;\nrom_pbus_rd = 0x40002268;\nrom_pbus_debugmode = 0x4000226c;\nrom_pbus_workmode = 0x40002270;\nrom_pbus_set_rxgain = 0x40002274;\nrom_pbus_xpd_rx_off = 0x40002278;\nrom_pbus_xpd_rx_on = 0x4000227c;\nrom_pbus_xpd_tx_off = 0x40002280;\nrom_pbus_xpd_tx_on = 0x40002284;\nrom_pbus_set_dco = 0x40002288;\nrom_set_loopback_gain = 0x4000228c;\nrom_txcal_debuge_mode = 0x40002290;\nrom_txcal_work_mode = 0x40002294;\nset_pbus_mem = 0x40002298;\nrom_disable_agc = 0x4000229c;\nrom_enable_agc = 0x400022a0;\nrom_disable_wifi_agc = 0x400022a4;\nrom_enable_wifi_agc = 0x400022a8;\nrom_write_gain_mem = 0x400022ac;\nrom_bb_bss_cbw40_dig = 0x400022b0;\nrom_cbw2040_cfg = 0x400022b4;\nrom_mac_tx_chan_offset = 0x400022b8;\nrom_tx_paon_set = 0x400022bc;\nrom_i2cmst_reg_init = 0x400022c0;\nrom_bt_gain_offset = 0x400022c4;\nrom_fe_reg_init = 0x400022c8;\nrom_mac_enable_bb = 0x400022cc;\nrom_bb_wdg_cfg = 0x400022d0;\nrom_fe_txrx_reset = 0x400022d4;\nrom_set_rx_comp = 0x400022d8;\nrom_write_chan_freq = 0x400022dc;\nrom_agc_reg_init = 0x400022e0;\nrom_bb_reg_init = 0x400022e4;\nrom_write_txrate_power_offset = 0x400022e8;\nrom_open_i2c_xpd = 0x400022ec;\nphy_disable_cca = 0x400022f0;\nphy_enable_cca = 0x400022f4;\nforce_txon = 0x400022f8;\ntxiq_set_reg = 0x400022fc;\nrxiq_set_reg = 0x40002300;\nrx_gain_force = 0x40002304;\nset_txclk_en = 0x40002308;\nset_rxclk_en = 0x4000230c;\nstart_tx_tone_step = 0x40002310;\nstop_tx_tone = 0x40002314;\nbb_wdg_test_en = 0x40002318;\nnoise_floor_auto_set = 0x4000231c;\nread_hw_noisefloor = 0x40002320;\nset_cca = 0x40002324;\nset_rx_sense = 0x40002328;\nphy_rx11blr_cfg = 0x4000232c;\nbb_wdt_rst_enable = 0x40002330;\nbb_wdt_int_enable = 0x40002334;\nbb_wdt_timeout_clear = 0x40002338;\nbb_wdt_get_status = 0x4000233c;\nwifi_rifs_mode_en = 0x40002340;\nphy_chan_filt_set = 0x40002344;\niq_corr_enable = 0x40002348;\nbt_tx_dig_gain = 0x4000234c;\nwifi_tx_dig_reg = 0x40002350;\nwifi_agc_sat_gain = 0x40002354;\nphy_bbpll_cal = 0x40002358;\nphy_xpd_tsens = 0x4000235c;\nphy_freq_mem_backup = 0x40002360;\nphy_ant_init = 0x40002364;\nphy_set_bbfreq_init = 0x40002368;\nwifi_fbw_sel = 0x4000236c;\nphy_rx_sense_set = 0x40002370;\nant_dft_cfg = 0x40002374;\nant_wifitx_cfg = 0x40002378;\nant_wifirx_cfg = 0x4000237c;\nant_bttx_cfg = 0x40002380;\ntx_state_set = 0x40002384;\nphy_chan_dump_cfg = 0x40002388;\nphy_enable_low_rate = 0x4000238c;\nphy_disable_low_rate = 0x40002390;\nphy_close_pa = 0x40002394;\nbt_filter_reg = 0x40002398;\nphy_freq_correct = 0x4000239c;\nset_pbus_reg = 0x400023a0;\nphy_dig_reg_backup = 0x400023a4;\niq_est_enable = 0x400023a8;\niq_est_disable = 0x400023ac;\ndc_iq_est = 0x400023b0;\nset_cal_rxdc = 0x400023b4;\nrxiq_get_mis = 0x400023b8;\nrxiq_cover_mg_mp = 0x400023bc;\nrfcal_rxiq = 0x400023c0;\nget_rfcal_rxiq_data = 0x400023c4;\npbus_rx_dco_cal = 0x400023c8;\nrxdc_est_min = 0x400023cc;\npbus_rx_dco_cal_1step = 0x400023d0;\nset_rx_gain_cal_iq = 0x400023d4;\nset_rx_gain_cal_dc = 0x400023d8;\nspur_reg_write_one_tone = 0x400023dc;\nspur_cal = 0x400023e0;\nspur_coef_cfg = 0x400023e4;\nrom_tester_wifi_cali = 0x400023e8;\nesp_recover_efuse_data = 0x400023ec;\nrom_temp_to_power = 0x400023f0;\ntsens_read_init = 0x400023f4;\ncode_to_temp = 0x400023f8;\ntsens_index_to_dac = 0x400023fc;\ntsens_index_to_offset = 0x40002400;\ntsens_dac_cal = 0x40002404;\ntsens_code_read = 0x40002408;\ntsens_temp_read = 0x4000240c;\nget_temp_init = 0x40002410;\nrom_txbbgain_to_index = 0x40002414;\nrom_index_to_txbbgain = 0x40002418;\nrom_bt_index_to_bb = 0x4000241c;\nrom_bt_bb_to_index = 0x40002420;\nrom_bt_get_tx_gain = 0x40002424;\nrom_get_tx_gain_value = 0x40002428;\nrom_wifi_get_tx_gain = 0x4000242c;\nrom_set_tx_gain_mem = 0x40002430;\nrom_get_rate_fcc_index = 0x40002434;\nrom_get_chan_target_power = 0x40002438;\nrom_wifi_tx_dig_gain = 0x4000243c;\nrom_wifi_set_tx_gain = 0x40002440;\nrom_bt_set_tx_gain = 0x40002444;\nwifi_11g_rate_chg = 0x40002448;\nbt_chan_pwr_interp = 0x4000244c;\nbt_tx_gain_init = 0x40002450;\n\/* Data (.data, .bss, .rodata) *\/\nphy_param_rom = 0x3fcdfb00;\n\n\n\/***************************************\n Group rom_btbb\n ***************************************\/\n\n\/* Functions *\/\nbt_agc_gain_offset = 0x40002454;\nbt_agc_gain_max = 0x40002458;\nbt_set_rx_comp = 0x4000245c;\nbt_agc_gain_set = 0x40002460;\nbt_agc_rssi_thresh = 0x40002464;\nbt_agc_target_set = 0x40002468;\nbt_agc_restart_set = 0x4000246c;\nbt_agc_recorrect_set = 0x40002470;\nbt_agc_detect_set = 0x40002474;\nbt_bb_rx_correlator_set = 0x40002478;\nbt_bb_rx_dpo_set = 0x4000247c;\nbt_bb_rx_filter_sel = 0x40002480;\nbt_bb_rx_set1 = 0x40002484;\nbt_bb_v2_rx_set = 0x40002488;\nbt_bb_v2_tx_set = 0x4000248c;\nbt_bb_tx_cca_period = 0x40002490;\nbt_bb_tx_cca_fifo_reset = 0x40002494;\nbt_bb_tx_cca_fifo_empty = 0x40002498;\nbt_bb_tx_cca_fifo_full = 0x4000249c;\nbt_bb_tx_cca_fifo_count = 0x400024a0;\nbt_bb_tx_cca_fifo_read = 0x400024a4;\ncoex_pti_v2 = 0x400024a8;\nbt_bb_set_le_tx_on_delay = 0x400024ac;\nbt_bb_set_corr_thresh_le = 0x400024b0;\n","old_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum 6c4d0f3a9f2d0c93477024a1a8f13746\n *\n * Compatible with ROM where ECO version equal or greater to 0.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\nrtc_get_wakeup_cause = 0x40000020;\nrtc_select_apb_bridge = 0x40000024;\nrtc_unhold_all_pads = 0x40000028;\nets_is_print_boot = 0x4000002c;\nets_printf = 0x40000030;\nets_install_putc1 = 0x40000034;\nets_install_uart_printf = 0x40000038;\nets_install_putc2 = 0x4000003c;\nPROVIDE( ets_delay_us = 0x40000040 );\nets_get_stack_info = 0x40000044;\nets_install_lock = 0x40000048;\nets_backup_dma_copy = 0x4000004c;\nets_apb_backup_init_lock_func = 0x40000050;\nUartRxString = 0x40000054;\nuart_tx_one_char = 0x40000058;\nuart_tx_one_char2 = 0x4000005c;\nuart_rx_one_char = 0x40000060;\nuart_rx_one_char_block = 0x40000064;\nuart_rx_readbuff = 0x40000068;\nuartAttach = 0x4000006c;\nuart_tx_flush = 0x40000070;\nuart_tx_wait_idle = 0x40000074;\nuart_div_modify = 0x40000078;\nets_write_char_uart = 0x4000007c;\nuart_tx_switch = 0x40000080;\nmultofup = 0x40000084;\nsoftware_reset = 0x40000088;\nsoftware_reset_cpu = 0x4000008c;\nassist_debug_clock_enable = 0x40000090;\nassist_debug_record_enable = 0x40000094;\nclear_super_wdt_reset_flag = 0x40000098;\ndisable_default_watchdog = 0x4000009c;\nsend_packet = 0x400000a0;\nrecv_packet = 0x400000a4;\nGetUartDevice = 0x400000a8;\nUartDwnLdProc = 0x400000ac;\nUart_Init = 0x400000b0;\nets_set_user_start = 0x400000b4;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff4fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000b8;\nmz_free = 0x400000bc;\ntdefl_compress = 0x400000c0;\ntdefl_compress_buffer = 0x400000c4;\ntdefl_compress_mem_to_heap = 0x400000c8;\ntdefl_compress_mem_to_mem = 0x400000cc;\ntdefl_compress_mem_to_output = 0x400000d0;\ntdefl_get_adler32 = 0x400000d4;\ntdefl_get_prev_return_status = 0x400000d8;\ntdefl_init = 0x400000dc;\ntdefl_write_image_to_png_file_in_memory = 0x400000e0;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000e4;\ntinfl_decompress = 0x400000e8;\ntinfl_decompress_mem_to_callback = 0x400000ec;\ntinfl_decompress_mem_to_heap = 0x400000f0;\ntinfl_decompress_mem_to_mem = 0x400000f4;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x400000f8 );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x400000fc );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000100 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000104 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000108 );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x4000010c );\nPROVIDE( _esp_rom_spiflash_erase_sector = 0x40000110 );\nPROVIDE( _esp_rom_spiflash_erase_block = 0x40000114 );\nPROVIDE( _esp_rom_spiflash_write = 0x40000118 );\nPROVIDE( _esp_rom_spiflash_read = 0x4000011c );\nPROVIDE( _esp_rom_spiflash_unlock = 0x40000120 );\nPROVIDE( _SPIEraseArea = 0x40000124 );\nPROVIDE( _SPI_write_enable = 0x40000128 );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x4000012c );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000130 );\nPROVIDE( esp_rom_spiflash_write = 0x40000134 );\nPROVIDE( esp_rom_spiflash_read = 0x40000138 );\nPROVIDE( esp_rom_spiflash_unlock = 0x4000013c );\nPROVIDE( SPIEraseArea = 0x40000140 );\nPROVIDE( SPI_write_enable = 0x40000144 );\nPROVIDE( esp_rom_spiflash_config_param = 0x40000148 );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x4000014c );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000150 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000154 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x40000158 );\nPROVIDE( esp_rom_spi_flash_update_id = 0x4000015c );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000160 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000164 );\nPROVIDE( esp_rom_spiflash_read_status = 0x40000168 );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x4000016c );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000170 );\nPROVIDE( spi_flash_attach = 0x40000174 );\nPROVIDE( spi_flash_get_chip_size = 0x40000178 );\nPROVIDE( spi_flash_guard_set = 0x4000017c );\nPROVIDE( spi_flash_guard_get = 0x40000180 );\nPROVIDE( spi_flash_read_encrypted = 0x40000184 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x40000188 );\nPROVIDE( spi_flash_mmap_page_num_init = 0x4000018c );\nPROVIDE( spi_flash_mmap = 0x40000190 );\nPROVIDE( spi_flash_mmap_pages = 0x40000194 );\nPROVIDE( spi_flash_munmap = 0x40000198 );\nPROVIDE( spi_flash_mmap_dump = 0x4000019c );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001a0 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001a4 );\nPROVIDE( spi_flash_cache2phys = 0x400001a8 );\nPROVIDE( spi_flash_phys2cache = 0x400001ac );\nPROVIDE( spi_flash_disable_cache = 0x400001b0 );\nPROVIDE( spi_flash_restore_cache = 0x400001b4 );\nPROVIDE( spi_flash_cache_enabled = 0x400001b8 );\nPROVIDE( spi_flash_enable_cache = 0x400001bc );\nPROVIDE( spi_cache_mode_switch = 0x400001c0 );\nPROVIDE( spi_common_set_dummy_output = 0x400001c4 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001c8 );\nPROVIDE( esp_rom_spi_set_address_bit_len = 0x400001cc );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001d0 );\nPROVIDE( SPILock = 0x400001d4 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001d8 );\nPROVIDE( SPI_Common_Command = 0x400001dc );\nPROVIDE( SPI_WakeUp = 0x400001e0 );\nPROVIDE( SPI_block_erase = 0x400001e4 );\nPROVIDE( SPI_chip_erase = 0x400001e8 );\nPROVIDE( SPI_init = 0x400001ec );\nPROVIDE( SPI_page_program = 0x400001f0 );\nPROVIDE( SPI_read_data = 0x400001f4 );\nPROVIDE( SPI_sector_erase = 0x400001f8 );\nPROVIDE( SelectSpiFunction = 0x400001fc );\nPROVIDE( SetSpiDrvs = 0x40000200 );\nPROVIDE( Wait_SPI_Idle = 0x40000204 );\nPROVIDE( spi_dummy_len_fix = 0x40000208 );\nPROVIDE( Disable_QMode = 0x4000020c );\nPROVIDE( Enable_QMode = 0x40000210 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group hal_soc\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x40000214 );\nPROVIDE( spi_flash_hal_device_config = 0x40000218 );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x4000021c );\nPROVIDE( spi_flash_hal_common_command = 0x40000220 );\nPROVIDE( spi_flash_hal_read = 0x40000224 );\nPROVIDE( spi_flash_hal_erase_chip = 0x40000228 );\nPROVIDE( spi_flash_hal_erase_sector = 0x4000022c );\nPROVIDE( spi_flash_hal_erase_block = 0x40000230 );\nPROVIDE( spi_flash_hal_program_page = 0x40000234 );\nPROVIDE( spi_flash_hal_set_write_protect = 0x40000238 );\nPROVIDE( spi_flash_hal_host_idle = 0x4000023c );\nPROVIDE( spi_flash_hal_check_status = 0x40000240 );\nPROVIDE( spi_flash_hal_setup_read_suspend = 0x40000244 );\nPROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x40000248 );\nPROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x4000024c );\nPROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000250 );\nPROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000254 );\nPROVIDE( spi_flash_hal_resume = 0x40000258 );\nPROVIDE( spi_flash_hal_suspend = 0x4000025c );\nPROVIDE( spi_flash_encryption_hal_enable = 0x40000260 );\nPROVIDE( spi_flash_encryption_hal_disable = 0x40000264 );\nPROVIDE( spi_flash_encryption_hal_prepare = 0x40000268 );\nPROVIDE( spi_flash_encryption_hal_done = 0x4000026c );\nPROVIDE( spi_flash_encryption_hal_destroy = 0x40000270 );\nPROVIDE( spi_flash_encryption_hal_check = 0x40000274 );\nPROVIDE( wdt_hal_init = 0x40000278 );\nPROVIDE( wdt_hal_deinit = 0x4000027c );\nPROVIDE( wdt_hal_config_stage = 0x40000280 );\nPROVIDE( wdt_hal_write_protect_disable = 0x40000284 );\nPROVIDE( wdt_hal_write_protect_enable = 0x40000288 );\nPROVIDE( wdt_hal_enable = 0x4000028c );\nPROVIDE( wdt_hal_disable = 0x40000290 );\nPROVIDE( wdt_hal_handle_intr = 0x40000294 );\nPROVIDE( wdt_hal_feed = 0x40000298 );\nPROVIDE( wdt_hal_set_flashboot_en = 0x4000029c );\nPROVIDE( wdt_hal_is_enabled = 0x400002a0 );\nPROVIDE( systimer_hal_init = 0x400002a4 );\nPROVIDE( systimer_hal_get_counter_value = 0x400002a8 );\nPROVIDE( systimer_hal_get_time = 0x400002ac );\nPROVIDE( systimer_hal_set_alarm_target = 0x400002b0 );\nPROVIDE( systimer_hal_set_alarm_period = 0x400002b4 );\nPROVIDE( systimer_hal_get_alarm_value = 0x400002b8 );\nPROVIDE( systimer_hal_enable_alarm_int = 0x400002bc );\nPROVIDE( systimer_hal_on_apb_freq_update = 0x400002c0 );\nPROVIDE( systimer_hal_counter_value_advance = 0x400002c4 );\nPROVIDE( systimer_hal_enable_counter = 0x400002c8 );\nPROVIDE( systimer_hal_select_alarm_mode = 0x400002cc );\nPROVIDE( systimer_hal_connect_alarm_counter = 0x400002d0 );\nPROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d4 );\n\n\n\/***************************************\n Group heap\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( tlsf_create = 0x400002d8 );\nPROVIDE( tlsf_create_with_pool = 0x400002dc );\nPROVIDE( tlsf_get_pool = 0x400002e0 );\nPROVIDE( tlsf_add_pool = 0x400002e4 );\nPROVIDE( tlsf_remove_pool = 0x400002e8 );\nPROVIDE( tlsf_malloc = 0x400002ec );\nPROVIDE( tlsf_memalign = 0x400002f0 );\nPROVIDE( tlsf_memalign_offs = 0x400002f4 );\nPROVIDE( tlsf_realloc = 0x400002f8 );\nPROVIDE( tlsf_free = 0x400002fc );\nPROVIDE( tlsf_block_size = 0x40000300 );\nPROVIDE( tlsf_size = 0x40000304 );\nPROVIDE( tlsf_align_size = 0x40000308 );\nPROVIDE( tlsf_block_size_min = 0x4000030c );\nPROVIDE( tlsf_block_size_max = 0x40000310 );\nPROVIDE( tlsf_pool_overhead = 0x40000314 );\nPROVIDE( tlsf_alloc_overhead = 0x40000318 );\nPROVIDE( tlsf_walk_pool = 0x4000031c );\nPROVIDE( tlsf_check = 0x40000320 );\nPROVIDE( tlsf_check_pool = 0x40000324 );\nPROVIDE( tlsf_poison_fill_pfunc_set = 0x40000328 );\nPROVIDE( multi_heap_get_block_address_impl = 0x4000032c );\nPROVIDE( multi_heap_get_allocated_size_impl = 0x40000330 );\nPROVIDE( multi_heap_register_impl = 0x40000334 );\nPROVIDE( multi_heap_set_lock = 0x40000338 );\nPROVIDE( multi_heap_mutex_init = 0x4000033c );\nPROVIDE( multi_heap_internal_lock = 0x40000340 );\nPROVIDE( multi_heap_internal_unlock = 0x40000344 );\nPROVIDE( multi_heap_get_first_block = 0x40000348 );\nPROVIDE( multi_heap_get_next_block = 0x4000034c );\nPROVIDE( multi_heap_is_free = 0x40000350 );\nPROVIDE( multi_heap_malloc_impl = 0x40000354 );\nPROVIDE( multi_heap_free_impl = 0x40000358 );\nPROVIDE( multi_heap_realloc_impl = 0x4000035c );\nPROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000360 );\nPROVIDE( multi_heap_aligned_alloc_impl = 0x40000364 );\nPROVIDE( multi_heap_check = 0x40000368 );\nPROVIDE( multi_heap_dump = 0x4000036c );\nPROVIDE( multi_heap_free_size_impl = 0x40000370 );\nPROVIDE( multi_heap_minimum_free_size_impl = 0x40000374 );\nPROVIDE( multi_heap_get_info_impl = 0x40000378 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x4000037c );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x40000380 );\nPROVIDE( spi_flash_chip_generic_write = 0x40000384 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000388 );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x4000038c );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000390 );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000394 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x40000398 );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x4000039c );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x400003a0 );\nPROVIDE( spi_flash_chip_generic_page_program = 0x400003a4 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003a8 );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003ac );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x400003b0 );\nPROVIDE( spi_flash_chip_generic_yield = 0x400003b4 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x400003b8 );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x400003bc );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c0 );\nPROVIDE( spi_flash_chip_generic_read = 0x400003c4 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003c8 );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003cc );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d0 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d4 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003d8 );\nPROVIDE( spi_flash_common_set_io_mode = 0x400003dc );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e0 );\nPROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e4 );\nPROVIDE( spi_flash_chip_generic_get_caps = 0x400003e8 );\nPROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003ec );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f0 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400003f4 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003f8 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );\nPROVIDE( spi_flash_encryption = 0x3fcdffe4 );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x400003fc );\nPROVIDE( memspi_host_read_status_hs = 0x40000400 );\nPROVIDE( memspi_host_flush_cache = 0x40000404 );\nPROVIDE( memspi_host_erase_chip = 0x40000408 );\nPROVIDE( memspi_host_erase_sector = 0x4000040c );\nPROVIDE( memspi_host_erase_block = 0x40000410 );\nPROVIDE( memspi_host_program_page = 0x40000414 );\nPROVIDE( memspi_host_read = 0x40000418 );\nPROVIDE( memspi_host_set_write_protect = 0x4000041c );\nPROVIDE( memspi_host_set_max_read_len = 0x40000420 );\nPROVIDE( memspi_host_read_data_slicer = 0x40000424 );\nPROVIDE( memspi_host_write_data_slicer = 0x40000428 );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x4000042c );\nPROVIDE( esp_flash_read_id = 0x40000430 );\nPROVIDE( esp_flash_get_size = 0x40000434 );\nPROVIDE( esp_flash_erase_chip = 0x40000438 );\nPROVIDE( esp_flash_erase_region = 0x4000043c );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000440 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000444 );\nPROVIDE( esp_flash_get_protectable_regions = 0x40000448 );\nPROVIDE( esp_flash_get_protected_region = 0x4000044c );\nPROVIDE( esp_flash_set_protected_region = 0x40000450 );\nPROVIDE( esp_flash_read = 0x40000454 );\nPROVIDE( esp_flash_write = 0x40000458 );\nPROVIDE( esp_flash_write_encrypted = 0x4000045c );\nPROVIDE( esp_flash_read_encrypted = 0x40000460 );\nPROVIDE( esp_flash_get_io_mode = 0x40000464 );\nPROVIDE( esp_flash_set_io_mode = 0x40000468 );\nPROVIDE( spi_flash_boot_attach = 0x4000046c );\nPROVIDE( esp_flash_read_chip_id = 0x40000470 );\nPROVIDE( detect_spi_flash_chip = 0x40000474 );\nPROVIDE( esp_rom_spiflash_write_disable = 0x40000478 );\nPROVIDE( esp_flash_suspend_cmd_init = 0x4000047c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe0 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffdc );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400006dc );\nPROVIDE( Cache_Get_Mode = 0x400006e0 );\nPROVIDE( Cache_Address_Through_IBus = 0x400006e4 );\nPROVIDE( Cache_Address_Through_DBus = 0x400006e8 );\nPROVIDE( Cache_Set_Default_Mode = 0x400006ec );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f0 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400006f4 );\nPROVIDE( MMU_Set_Page_Mode = 0x400006f8 );\nPROVIDE( MMU_Get_Page_Mode = 0x400006fc );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x40000700 );\nPROVIDE( Cache_Op_Addr = 0x40000704 );\nPROVIDE( Cache_Invalidate_Addr = 0x40000708 );\nPROVIDE( Cache_Invalidate_ICache_All = 0x4000070c );\nPROVIDE( Cache_Mask_All = 0x40000710 );\nPROVIDE( Cache_UnMask_Dram0 = 0x40000714 );\nPROVIDE( Cache_Disable_ICache = 0x40000718 );\nPROVIDE( Cache_Enable_ICache = 0x4000071c );\nPROVIDE( Cache_Suspend_ICache = 0x40000720 );\nPROVIDE( Cache_Resume_ICache = 0x40000724 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x40000728 );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x4000072c );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000730 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x40000734 );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x40000738 );\nPROVIDE( Cache_Owner_Init = 0x4000073c );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000740 );\nPROVIDE( Cache_MMU_Init = 0x40000744 );\nPROVIDE( Cache_Ibus_MMU_Set = 0x40000748 );\nPROVIDE( Cache_Dbus_MMU_Set = 0x4000074c );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000750 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x40000754 );\nPROVIDE( Cache_Get_Virtual_Addr = 0x40000758 );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x4000075c );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000760 );\nPROVIDE( Cache_Get_Memory_value = 0x40000764 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd0 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x40000768;\nets_get_cpu_frequency = 0x4000076c;\nets_update_cpu_frequency = 0x40000770;\nets_get_printf_channel = 0x40000774;\nets_get_xtal_div = 0x40000778;\nets_set_xtal_div = 0x4000077c;\nets_get_xtal_freq = 0x40000780;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x40000784;\ngpio_matrix_in = 0x40000788;\ngpio_matrix_out = 0x4000078c;\ngpio_output_disable = 0x40000790;\ngpio_output_enable = 0x40000794;\ngpio_output_set = 0x40000798;\ngpio_pad_hold = 0x4000079c;\ngpio_pad_input_disable = 0x400007a0;\ngpio_pad_input_enable = 0x400007a4;\ngpio_pad_pulldown = 0x400007a8;\ngpio_pad_pullup = 0x400007ac;\ngpio_pad_select_gpio = 0x400007b0;\ngpio_pad_set_drv = 0x400007b4;\ngpio_pad_unhold = 0x400007b8;\ngpio_pin_wakeup_disable = 0x400007bc;\ngpio_pin_wakeup_enable = 0x400007c0;\ngpio_bypass_matrix_in = 0x400007c4;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400007c8;\nesprv_intc_int_set_threshold = 0x400007cc;\nesprv_intc_int_enable = 0x400007d0;\nesprv_intc_int_disable = 0x400007d4;\nesprv_intc_int_set_type = 0x400007d8;\nPROVIDE( intr_handler_set = 0x400007dc );\nintr_matrix_set = 0x400007e0;\nets_intr_lock = 0x400007e4;\nets_intr_unlock = 0x400007e8;\nets_isr_attach = 0x400007ec;\nets_isr_mask = 0x400007f0;\nets_isr_unmask = 0x400007f4;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\ncrc32_le = 0x400007f8;\ncrc16_le = 0x400007fc;\ncrc8_le = 0x40000800;\ncrc32_be = 0x40000804;\ncrc16_be = 0x40000808;\ncrc8_be = 0x4000080c;\nesp_crc8 = 0x40000810;\nets_sha_enable = 0x40000814;\nets_sha_disable = 0x40000818;\nets_sha_get_state = 0x4000081c;\nets_sha_init = 0x40000820;\nets_sha_process = 0x40000824;\nets_sha_starts = 0x40000828;\nets_sha_update = 0x4000082c;\nets_sha_finish = 0x40000830;\nets_sha_clone = 0x40000834;\n\/* Data (.data, .bss, .rodata) *\/\ncrc32_le_table_ptr = 0x3ff4fff8;\ncrc16_le_table_ptr = 0x3ff4fff4;\ncrc8_le_table_ptr = 0x3ff4fff0;\ncrc32_be_table_ptr = 0x3ff4ffec;\ncrc16_be_table_ptr = 0x3ff4ffe8;\ncrc8_be_table_ptr = 0x3ff4ffe4;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x40000838;\nets_efuse_program = 0x4000083c;\nets_efuse_clear_program_registers = 0x40000840;\nets_efuse_write_key = 0x40000844;\nets_efuse_get_read_register_address = 0x40000848;\nets_efuse_get_key_purpose = 0x4000084c;\nets_efuse_key_block_unused = 0x40000850;\nets_efuse_find_unused_key_block = 0x40000854;\nets_efuse_rs_calculate = 0x40000858;\nets_efuse_count_unused_key_blocks = 0x4000085c;\nets_efuse_secure_boot_enabled = 0x40000860;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000864;\nets_efuse_cache_encryption_enabled = 0x40000868;\nets_efuse_download_modes_disabled = 0x4000086c;\nets_efuse_find_purpose = 0x40000870;\nets_efuse_force_send_resume = 0x40000874;\nets_efuse_get_flash_delay_us = 0x40000878;\nets_efuse_get_mac = 0x4000087c;\nets_efuse_get_uart_print_control = 0x40000880;\nets_efuse_direct_boot_mode_disabled = 0x40000884;\nets_efuse_security_download_modes_enabled = 0x40000888;\nets_efuse_set_timing = 0x4000088c;\nets_efuse_jtag_disabled = 0x40000890;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_ecdsa_verify = 0x40000894;\nets_secure_boot_verify_bootloader_with_keys = 0x40000898;\nets_secure_boot_verify_signature = 0x4000089c;\nets_secure_boot_read_key_digests = 0x400008a0;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Data (.data, .bss, .rodata) *\/\ng_uart_print = 0x3fcdffc9;\ng_usb_print = 0x3fcdffc8;\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nble_controller_rom_data_init = 0x40000a14;\nble_osi_coex_funcs_register = 0x40000a18;\nbt_rf_coex_cfg_get_default = 0x40000a1c;\nbt_rf_coex_dft_pti_get_default = 0x40000a20;\nbt_rf_coex_hooks_p_set = 0x40000a24;\nr__os_mbuf_copypkthdr = 0x40000a28;\nr__os_msys_find_pool = 0x40000a2c;\nr_ble_controller_get_rom_compile_version = 0x40000a30;\nr_ble_hci_ram_hs_acl_tx = 0x40000a34;\nr_ble_hci_ram_hs_cmd_tx = 0x40000a38;\nr_ble_hci_ram_ll_acl_tx = 0x40000a3c;\nr_ble_hci_ram_ll_evt_tx = 0x40000a40;\nr_ble_hci_ram_reset = 0x40000a44;\nr_ble_hci_ram_set_acl_free_cb = 0x40000a48;\nr_ble_hci_trans_acl_buf_alloc = 0x40000a4c;\nr_ble_hci_trans_buf_alloc = 0x40000a50;\nr_ble_hci_trans_buf_free = 0x40000a54;\nr_ble_hci_trans_cfg_hs = 0x40000a58;\nr_ble_hci_trans_cfg_ll = 0x40000a5c;\nr_ble_hci_trans_deinit = 0x40000a60;\nr_ble_hci_trans_env_init = 0x40000a64;\nr_ble_hci_trans_init = 0x40000a68;\nr_ble_hci_uart_acl_tx = 0x40000a6c;\nr_ble_hci_uart_cmdevt_tx = 0x40000a70;\nr_ble_hci_uart_config = 0x40000a74;\nr_ble_hci_uart_free_pkt = 0x40000a78;\nr_ble_hci_uart_hs_acl_tx = 0x40000a7c;\nr_ble_hci_uart_hs_cmd_tx = 0x40000a80;\nr_ble_hci_uart_ll_acl_tx = 0x40000a84;\nr_ble_hci_uart_ll_evt_tx = 0x40000a88;\nr_ble_hci_uart_rx_acl = 0x40000a8c;\nr_ble_hci_uart_rx_char = 0x40000a90;\nr_ble_hci_uart_rx_cmd = 0x40000a94;\nr_ble_hci_uart_rx_evt = 0x40000a98;\nr_ble_hci_uart_rx_evt_cb = 0x40000a9c;\nr_ble_hci_uart_rx_le_evt = 0x40000aa0;\nr_ble_hci_uart_rx_pkt_type = 0x40000aa4;\nr_ble_hci_uart_rx_skip_acl = 0x40000aa8;\nr_ble_hci_uart_rx_skip_cmd = 0x40000aac;\nr_ble_hci_uart_rx_skip_evt = 0x40000ab0;\nr_ble_hci_uart_rx_sync_loss = 0x40000ab4;\nr_ble_hci_uart_set_acl_free_cb = 0x40000ab8;\nr_ble_hci_uart_sync_lost = 0x40000abc;\nr_ble_hci_uart_trans_reset = 0x40000ac0;\nr_ble_hci_uart_tx_char = 0x40000ac4;\nr_ble_hci_uart_tx_pkt_type = 0x40000ac8;\nr_ble_hw_driver_deinit = 0x40000acc;\nr_ble_hw_driver_env_init = 0x40000ad0;\nr_ble_hw_encrypt_block = 0x40000ad4;\nr_ble_hw_get_public_addr = 0x40000ad8;\nr_ble_hw_get_static_addr = 0x40000adc;\nr_ble_hw_periodiclist_add = 0x40000ae0;\nr_ble_hw_periodiclist_clear = 0x40000ae4;\nr_ble_hw_periodiclist_rmv = 0x40000ae8;\nr_ble_hw_resolv_list_cur_entry = 0x40000aec;\nr_ble_hw_resolv_list_match = 0x40000af0;\nr_ble_hw_resolv_list_set = 0x40000af4;\nr_ble_hw_rng_init = 0x40000af8;\nr_ble_hw_rng_start = 0x40000afc;\nr_ble_hw_rng_stop = 0x40000b00;\nr_ble_hw_rx_local_is_rpa = 0x40000b04;\nr_ble_hw_whitelist_add = 0x40000b08;\nr_ble_hw_whitelist_clear = 0x40000b0c;\nr_ble_hw_whitelist_dev_num = 0x40000b10;\nr_ble_hw_whitelist_get_base = 0x40000b14;\nr_ble_hw_whitelist_rmv = 0x40000b18;\nr_ble_hw_whitelist_search = 0x40000b1c;\nr_ble_hw_whitelist_sort = 0x40000b20;\nr_ble_ll_acl_data_in = 0x40000b24;\nr_ble_ll_addr_is_id = 0x40000b28;\nr_ble_ll_addr_subtype = 0x40000b2c;\nr_ble_ll_adv_active_chanset_clear = 0x40000b30;\nr_ble_ll_adv_active_chanset_is_pri = 0x40000b34;\nr_ble_ll_adv_active_chanset_is_sec = 0x40000b38;\nr_ble_ll_adv_active_chanset_set_pri = 0x40000b3c;\nr_ble_ll_adv_active_chanset_set_sec = 0x40000b40;\nr_ble_ll_adv_aux_calculate = 0x40000b44;\nr_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000b48;\nr_ble_ll_adv_aux_pdu_make = 0x40000b4c;\nr_ble_ll_adv_aux_scannable_pdu_make = 0x40000b50;\nr_ble_ll_adv_aux_scannable_pdu_payload_len = 0x40000b54;\nr_ble_ll_adv_aux_schedule = 0x40000b58;\nr_ble_ll_adv_aux_schedule_first = 0x40000b5c;\nr_ble_ll_adv_aux_schedule_next = 0x40000b60;\nr_ble_ll_adv_aux_scheduled = 0x40000b64;\nr_ble_ll_adv_aux_set_start_time = 0x40000b68;\nr_ble_ll_adv_aux_txed = 0x40000b6c;\nr_ble_ll_adv_can_chg_whitelist = 0x40000b70;\nr_ble_ll_adv_chk_rpa_timeout = 0x40000b74;\nr_ble_ll_adv_clear_all = 0x40000b78;\nr_ble_ll_adv_coex_dpc_calc_pti_update_itvl = 0x40000b7c;\nr_ble_ll_adv_coex_dpc_process_pri = 0x40000b80;\nr_ble_ll_adv_coex_dpc_process_sec = 0x40000b84;\nr_ble_ll_adv_coex_dpc_pti_get = 0x40000b88;\nr_ble_ll_adv_coex_dpc_update = 0x40000b8c;\nr_ble_ll_adv_coex_dpc_update_on_adv_start = 0x40000b90;\nr_ble_ll_adv_coex_dpc_update_on_aux_scheduled = 0x40000b94;\nr_ble_ll_adv_coex_dpc_update_on_data_updated = 0x40000b98;\nr_ble_ll_adv_coex_dpc_update_on_event_end = 0x40000b9c;\nr_ble_ll_adv_coex_dpc_update_on_event_scheduled = 0x40000ba0;\nr_ble_ll_adv_conn_req_rxd = 0x40000ba4;\nr_ble_ll_adv_deinit = 0x40000ba8;\nr_ble_ll_adv_done = 0x40000bac;\nr_ble_ll_adv_drop_event = 0x40000bb0;\nr_ble_ll_adv_enabled = 0x40000bb4;\nr_ble_ll_adv_env_init = 0x40000bb8;\nr_ble_ll_adv_event_done = 0x40000bbc;\nr_ble_ll_adv_event_rmvd_from_sched = 0x40000bc0;\nr_ble_ll_adv_ext_estimate_data_itvl = 0x40000bc4;\nr_ble_ll_adv_ext_set_adv_data = 0x40000bc8;\nr_ble_ll_adv_ext_set_enable = 0x40000bcc;\nr_ble_ll_adv_ext_set_param = 0x40000bd0;\nr_ble_ll_adv_ext_set_scan_rsp = 0x40000bd4;\nr_ble_ll_adv_final_chan = 0x40000bd8;\nr_ble_ll_adv_first_chan = 0x40000bdc;\nr_ble_ll_adv_flags_clear = 0x40000be0;\nr_ble_ll_adv_flags_set = 0x40000be4;\nr_ble_ll_adv_get_local_rpa = 0x40000be8;\nr_ble_ll_adv_get_peer_rpa = 0x40000bec;\nr_ble_ll_adv_get_sec_pdu_len = 0x40000bf0;\nr_ble_ll_adv_halt = 0x40000bf4;\nr_ble_ll_adv_hci_set_random_addr = 0x40000bf8;\nr_ble_ll_adv_init = 0x40000bfc;\nr_ble_ll_adv_legacy_pdu_make = 0x40000c00;\nr_ble_ll_adv_make_done = 0x40000c04;\nr_ble_ll_adv_pdu_make = 0x40000c08;\nr_ble_ll_adv_periodic_check_data_itvl = 0x40000c0c;\nr_ble_ll_adv_periodic_done = 0x40000c10;\nr_ble_ll_adv_periodic_enable = 0x40000c14;\nr_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c18;\nr_ble_ll_adv_periodic_event_done = 0x40000c1c;\nr_ble_ll_adv_periodic_rmvd_from_sched = 0x40000c20;\nr_ble_ll_adv_periodic_schedule_first = 0x40000c24;\nr_ble_ll_adv_periodic_schedule_next = 0x40000c28;\nr_ble_ll_adv_periodic_send_sync_ind = 0x40000c2c;\nr_ble_ll_adv_periodic_set_data = 0x40000c30;\nr_ble_ll_adv_periodic_set_info_transfer = 0x40000c34;\nr_ble_ll_adv_periodic_set_param = 0x40000c38;\nr_ble_ll_adv_put_aux_ptr = 0x40000c3c;\nr_ble_ll_adv_put_syncinfo = 0x40000c40;\nr_ble_ll_adv_rd_max_adv_data_len = 0x40000c44;\nr_ble_ll_adv_rd_sup_adv_sets = 0x40000c48;\nr_ble_ll_adv_read_txpwr = 0x40000c4c;\nr_ble_ll_adv_remove = 0x40000c50;\nr_ble_ll_adv_reschedule_event = 0x40000c54;\nr_ble_ll_adv_reschedule_periodic_event = 0x40000c58;\nr_ble_ll_adv_reset = 0x40000c5c;\nr_ble_ll_adv_rpa_timeout = 0x40000c60;\nr_ble_ll_adv_rpa_update = 0x40000c64;\nr_ble_ll_adv_rx_isr_end = 0x40000c68;\nr_ble_ll_adv_rx_isr_start = 0x40000c6c;\nr_ble_ll_adv_rx_pkt_in = 0x40000c70;\nr_ble_ll_adv_rx_req = 0x40000c74;\nr_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c78;\nr_ble_ll_adv_scan_rsp_pdu_make = 0x40000c7c;\nr_ble_ll_adv_scheduled = 0x40000c80;\nr_ble_ll_adv_sec_done = 0x40000c84;\nr_ble_ll_adv_sec_event_done = 0x40000c88;\nr_ble_ll_adv_secondary_tx_start_cb = 0x40000c8c;\nr_ble_ll_adv_send_conn_comp_ev = 0x40000c90;\nr_ble_ll_adv_set_adv_data = 0x40000c94;\nr_ble_ll_adv_set_adv_params = 0x40000c98;\nr_ble_ll_adv_set_enable = 0x40000c9c;\nr_ble_ll_adv_set_random_addr = 0x40000ca0;\nr_ble_ll_adv_set_scan_rsp_data = 0x40000ca4;\nr_ble_ll_adv_set_sched = 0x40000ca8;\nr_ble_ll_adv_sm_deinit = 0x40000cac;\nr_ble_ll_adv_sm_event_init = 0x40000cb0;\nr_ble_ll_adv_sm_event_restore = 0x40000cb4;\nr_ble_ll_adv_sm_event_store = 0x40000cb8;\nr_ble_ll_adv_sm_find_configured = 0x40000cbc;\nr_ble_ll_adv_sm_get = 0x40000cc0;\nr_ble_ll_adv_sm_init = 0x40000cc4;\nr_ble_ll_adv_sm_reset = 0x40000cc8;\nr_ble_ll_adv_sm_start = 0x40000ccc;\nr_ble_ll_adv_sm_start_periodic = 0x40000cd0;\nr_ble_ll_adv_sm_stop = 0x40000cd4;\nr_ble_ll_adv_sm_stop_limit_reached = 0x40000cd8;\nr_ble_ll_adv_sm_stop_periodic = 0x40000cdc;\nr_ble_ll_adv_sm_stop_timeout = 0x40000ce0;\nr_ble_ll_adv_sync_calculate = 0x40000ce4;\nr_ble_ll_adv_sync_get_pdu_len = 0x40000ce8;\nr_ble_ll_adv_sync_next_scheduled = 0x40000cec;\nr_ble_ll_adv_sync_pdu_make = 0x40000cf0;\nr_ble_ll_adv_sync_schedule = 0x40000cf4;\nr_ble_ll_adv_sync_tx_done = 0x40000cf8;\nr_ble_ll_adv_sync_tx_end = 0x40000cfc;\nr_ble_ll_adv_sync_tx_start_cb = 0x40000d00;\nr_ble_ll_adv_tx_done = 0x40000d04;\nr_ble_ll_adv_tx_start_cb = 0x40000d08;\nr_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d0c;\nr_ble_ll_adv_update_data_mbuf = 0x40000d10;\nr_ble_ll_adv_update_did = 0x40000d14;\nr_ble_ll_adv_update_periodic_data = 0x40000d18;\nr_ble_ll_adv_wfr_timer_exp = 0x40000d1c;\nr_ble_ll_arr_pool_init = 0x40000d20;\nr_ble_ll_auth_pyld_tmo_event_send = 0x40000d24;\nr_ble_ll_aux_scan_cb = 0x40000d28;\nr_ble_ll_aux_scan_drop = 0x40000d2c;\nr_ble_ll_aux_scan_drop_event_cb = 0x40000d30;\nr_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d34;\nr_ble_ll_calc_session_key = 0x40000d38;\nr_ble_ll_calc_ticks_per_slot = 0x40000d3c;\nr_ble_ll_calc_us_convert_tick_unit = 0x40000d40;\nr_ble_ll_check_scan_params = 0x40000d44;\nr_ble_ll_chk_txrx_octets = 0x40000d48;\nr_ble_ll_chk_txrx_time = 0x40000d4c;\nr_ble_ll_conn_adjust_pyld_len = 0x40000d50;\nr_ble_ll_conn_auth_pyld_timer_cb = 0x40000d54;\nr_ble_ll_conn_auth_pyld_timer_start = 0x40000d58;\nr_ble_ll_conn_calc_dci = 0x40000d5c;\nr_ble_ll_conn_calc_dci_csa1 = 0x40000d60;\nr_ble_ll_conn_calc_itvl_ticks = 0x40000d64;\nr_ble_ll_conn_can_send_next_pdu = 0x40000d68;\nr_ble_ll_conn_chk_csm_flags = 0x40000d6c;\nr_ble_ll_conn_chk_phy_upd_start = 0x40000d70;\nr_ble_ll_conn_coex_dpc_process = 0x40000d74;\nr_ble_ll_conn_coex_dpc_pti_get = 0x40000d78;\nr_ble_ll_conn_coex_dpc_update = 0x40000d7c;\nr_ble_ll_conn_coex_dpc_update_on_event_scheduled = 0x40000d80;\nr_ble_ll_conn_comp_event_send = 0x40000d84;\nr_ble_ll_conn_connect_ind_pdu_make = 0x40000d88;\nr_ble_ll_conn_create = 0x40000d8c;\nr_ble_ll_conn_create_cancel = 0x40000d90;\nr_ble_ll_conn_created = 0x40000d94;\nr_ble_ll_conn_cth_flow_alloc_credit = 0x40000d98;\nr_ble_ll_conn_cth_flow_enable = 0x40000d9c;\nr_ble_ll_conn_cth_flow_error_fn = 0x40000da0;\nr_ble_ll_conn_cth_flow_free_credit = 0x40000da4;\nr_ble_ll_conn_cth_flow_have_credit = 0x40000da8;\nr_ble_ll_conn_cth_flow_is_enabled = 0x40000dac;\nr_ble_ll_conn_cth_flow_process_cmd = 0x40000db0;\nr_ble_ll_conn_cth_flow_set_buffers = 0x40000db4;\nr_ble_ll_conn_cur_pducb = 0x40000db8;\nr_ble_ll_conn_current_sm_over = 0x40000dbc;\nr_ble_ll_conn_end = 0x40000dc0;\nr_ble_ll_conn_enqueue_pkt = 0x40000dc4;\nr_ble_ll_conn_env_init = 0x40000dc8;\nr_ble_ll_conn_event_end = 0x40000dcc;\nr_ble_ll_conn_event_end_timer_cb = 0x40000dd0;\nr_ble_ll_conn_event_halt = 0x40000dd4;\nr_ble_ll_conn_event_is_over = 0x40000dd8;\nr_ble_ll_conn_event_start_cb = 0x40000ddc;\nr_ble_ll_conn_ext_master_init = 0x40000de0;\nr_ble_ll_conn_ext_set_params = 0x40000de4;\nr_ble_ll_conn_find_active_conn = 0x40000de8;\nr_ble_ll_conn_get_anchor = 0x40000dec;\nr_ble_ll_conn_get_ce_end_time = 0x40000df0;\nr_ble_ll_conn_get_new_pdu = 0x40000df4;\nr_ble_ll_conn_get_next_sched_time = 0x40000df8;\nr_ble_ll_conn_halt = 0x40000dfc;\nr_ble_ll_conn_hcc_params_set_fallback = 0x40000e00;\nr_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000e04;\nr_ble_ll_conn_hci_chk_conn_params = 0x40000e08;\nr_ble_ll_conn_hci_chk_scan_params = 0x40000e0c;\nr_ble_ll_conn_hci_disconnect_cmd = 0x40000e10;\nr_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000e14;\nr_ble_ll_conn_hci_le_ltk_reply = 0x40000e18;\nr_ble_ll_conn_hci_le_rd_phy = 0x40000e1c;\nr_ble_ll_conn_hci_le_set_phy = 0x40000e20;\nr_ble_ll_conn_hci_le_start_encrypt = 0x40000e24;\nr_ble_ll_conn_hci_param_nrr = 0x40000e28;\nr_ble_ll_conn_hci_param_rr = 0x40000e2c;\nr_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000e30;\nr_ble_ll_conn_hci_rd_chan_map = 0x40000e34;\nr_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000e38;\nr_ble_ll_conn_hci_rd_rssi = 0x40000e3c;\nr_ble_ll_conn_hci_read_rem_features = 0x40000e40;\nr_ble_ll_conn_hci_set_chan_class = 0x40000e44;\nr_ble_ll_conn_hci_set_data_len = 0x40000e48;\nr_ble_ll_conn_hci_update = 0x40000e4c;\nr_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000e50;\nr_ble_ll_conn_init_pending_aux_conn_rsp = 0x40000e54;\nr_ble_ll_conn_init_phy = 0x40000e58;\nr_ble_ll_conn_init_wfr_timer_exp = 0x40000e5c;\nr_ble_ll_conn_is_empty_pdu = 0x40000e60;\nr_ble_ll_conn_is_lru = 0x40000e64;\nr_ble_ll_conn_master_common_init = 0x40000e68;\nr_ble_ll_conn_master_init = 0x40000e6c;\nr_ble_ll_conn_module_deinit = 0x40000e70;\nr_ble_ll_conn_module_init = 0x40000e74;\nr_ble_ll_conn_module_reset = 0x40000e78;\nr_ble_ll_conn_new_pducb = 0x40000e7c;\nr_ble_ll_conn_next_event = 0x40000e80;\nr_ble_ll_conn_num_comp_pkts_event_send = 0x40000e84;\nr_ble_ll_conn_process_conn_params = 0x40000e88;\nr_ble_ll_conn_recv_ack = 0x40000e8c;\nr_ble_ll_conn_reset_pending_aux_conn_rsp = 0x40000e90;\nr_ble_ll_conn_rx_data_pdu = 0x40000e94;\nr_ble_ll_conn_rx_isr_end = 0x40000e98;\nr_ble_ll_conn_rx_isr_start = 0x40000e9c;\nr_ble_ll_conn_rxend_unencrypt = 0x40000ea0;\nr_ble_ll_conn_set_csa = 0x40000ea4;\nr_ble_ll_conn_set_global_chanmap = 0x40000ea8;\nr_ble_ll_conn_set_md_flag = 0x40000eac;\nr_ble_ll_conn_set_phy = 0x40000eb0;\nr_ble_ll_conn_set_slave_flow_control = 0x40000eb4;\nr_ble_ll_conn_set_txpwr_by_handle = 0x40000eb8;\nr_ble_ll_conn_set_unknown_rx_octets = 0x40000ebc;\nr_ble_ll_conn_slave_start = 0x40000ec0;\nr_ble_ll_conn_sm_get = 0x40000ec4;\nr_ble_ll_conn_sm_new = 0x40000ec8;\nr_ble_ll_conn_sm_npl_deinit = 0x40000ecc;\nr_ble_ll_conn_sm_npl_init = 0x40000ed0;\nr_ble_ll_conn_start_rx_encrypt = 0x40000ed4;\nr_ble_ll_conn_start_rx_unencrypt = 0x40000ed8;\nr_ble_ll_conn_timeout = 0x40000edc;\nr_ble_ll_conn_tx_pdu = 0x40000ee0;\nr_ble_ll_conn_tx_pkt_in = 0x40000ee4;\nr_ble_ll_conn_txend_encrypt = 0x40000ee8;\nr_ble_ll_conn_update_conn_params = 0x40000eec;\nr_ble_ll_conn_update_eff_data_len = 0x40000ef0;\nr_ble_ll_conn_update_new_pdu_len = 0x40000ef4;\nr_ble_ll_conn_wait_txend = 0x40000ef8;\nr_ble_ll_conn_wfr_timer_exp = 0x40000efc;\nr_ble_ll_copy_data = 0x40000f00;\nr_ble_ll_count_rx_adv_pdus = 0x40000f04;\nr_ble_ll_count_rx_stats = 0x40000f08;\nr_ble_ll_ctrl_chanmap_req_make = 0x40000f0c;\nr_ble_ll_ctrl_chk_proc_start = 0x40000f10;\nr_ble_ll_ctrl_conn_param_pdu_make = 0x40000f14;\nr_ble_ll_ctrl_conn_param_pdu_proc = 0x40000f18;\nr_ble_ll_ctrl_conn_param_reply = 0x40000f1c;\nr_ble_ll_ctrl_conn_upd_make = 0x40000f20;\nr_ble_ll_ctrl_datalen_upd_make = 0x40000f24;\nr_ble_ll_ctrl_enc_allowed_pdu = 0x40000f28;\nr_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000f2c;\nr_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40000f30;\nr_ble_ll_ctrl_enc_req_make = 0x40000f34;\nr_ble_ll_ctrl_find_new_phy = 0x40000f38;\nr_ble_ll_ctrl_initiate_dle = 0x40000f3c;\nr_ble_ll_ctrl_is_start_enc_rsp = 0x40000f40;\nr_ble_ll_ctrl_is_terminate_ind = 0x40000f44;\nr_ble_ll_ctrl_len_proc = 0x40000f48;\nr_ble_ll_ctrl_phy_from_phy_mask = 0x40000f4c;\nr_ble_ll_ctrl_phy_req_rsp_make = 0x40000f50;\nr_ble_ll_ctrl_phy_tx_transition_get = 0x40000f54;\nr_ble_ll_ctrl_phy_update_cancel = 0x40000f58;\nr_ble_ll_ctrl_phy_update_ind_make = 0x40000f5c;\nr_ble_ll_ctrl_phy_update_proc_complete = 0x40000f60;\nr_ble_ll_ctrl_proc_init = 0x40000f64;\nr_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000f68;\nr_ble_ll_ctrl_proc_start = 0x40000f6c;\nr_ble_ll_ctrl_proc_stop = 0x40000f70;\nr_ble_ll_ctrl_proc_unk_rsp = 0x40000f74;\nr_ble_ll_ctrl_proc_with_instant_initiated = 0x40000f78;\nr_ble_ll_ctrl_rej_ext_ind_make = 0x40000f7c;\nr_ble_ll_ctrl_reject_ind_send = 0x40000f80;\nr_ble_ll_ctrl_rx_chanmap_req = 0x40000f84;\nr_ble_ll_ctrl_rx_conn_param_req = 0x40000f88;\nr_ble_ll_ctrl_rx_conn_param_rsp = 0x40000f8c;\nr_ble_ll_ctrl_rx_conn_update = 0x40000f90;\nr_ble_ll_ctrl_rx_enc_req = 0x40000f94;\nr_ble_ll_ctrl_rx_enc_rsp = 0x40000f98;\nr_ble_ll_ctrl_rx_feature_req = 0x40000f9c;\nr_ble_ll_ctrl_rx_feature_rsp = 0x40000fa0;\nr_ble_ll_ctrl_rx_pause_enc_req = 0x40000fa4;\nr_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000fa8;\nr_ble_ll_ctrl_rx_pdu = 0x40000fac;\nr_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000fb0;\nr_ble_ll_ctrl_rx_phy_req = 0x40000fb4;\nr_ble_ll_ctrl_rx_phy_rsp = 0x40000fb8;\nr_ble_ll_ctrl_rx_phy_update_ind = 0x40000fbc;\nr_ble_ll_ctrl_rx_ping_rsp = 0x40000fc0;\nr_ble_ll_ctrl_rx_reject_ind = 0x40000fc4;\nr_ble_ll_ctrl_rx_start_enc_req = 0x40000fc8;\nr_ble_ll_ctrl_rx_start_enc_rsp = 0x40000fcc;\nr_ble_ll_ctrl_rx_version_ind = 0x40000fd0;\nr_ble_ll_ctrl_start_enc_send = 0x40000fd4;\nr_ble_ll_ctrl_start_rsp_timer = 0x40000fd8;\nr_ble_ll_ctrl_terminate_start = 0x40000fdc;\nr_ble_ll_ctrl_tx_done = 0x40000fe0;\nr_ble_ll_ctrl_update_features = 0x40000fe4;\nr_ble_ll_ctrl_version_ind_make = 0x40000fe8;\nr_ble_ll_data_buffer_overflow = 0x40000fec;\nr_ble_ll_deinit = 0x40000ff0;\nr_ble_ll_disconn_comp_event_send = 0x40000ff4;\nr_ble_ll_dtm_calculate_itvl = 0x40000ff8;\nr_ble_ll_dtm_ctx_free = 0x40000ffc;\nr_ble_ll_dtm_deinit = 0x40001000;\nr_ble_ll_dtm_end_test = 0x40001004;\nr_ble_ll_dtm_ev_rx_restart_cb = 0x40001008;\nr_ble_ll_dtm_ev_tx_resched_cb = 0x4000100c;\nr_ble_ll_dtm_init = 0x40001010;\nr_ble_ll_dtm_reset = 0x40001014;\nr_ble_ll_dtm_rx_create_ctx = 0x40001018;\nr_ble_ll_dtm_rx_isr_end = 0x4000101c;\nr_ble_ll_dtm_rx_isr_start = 0x40001020;\nr_ble_ll_dtm_rx_pkt_in = 0x40001024;\nr_ble_ll_dtm_rx_sched_cb = 0x40001028;\nr_ble_ll_dtm_rx_start = 0x4000102c;\nr_ble_ll_dtm_rx_test = 0x40001030;\nr_ble_ll_dtm_set_next = 0x40001034;\nr_ble_ll_dtm_tx_create_ctx = 0x40001038;\nr_ble_ll_dtm_tx_done = 0x4000103c;\nr_ble_ll_dtm_tx_sched_cb = 0x40001040;\nr_ble_ll_dtm_tx_test = 0x40001044;\nr_ble_ll_dtm_wfr_timer_exp = 0x40001048;\nr_ble_ll_env_init = 0x4000104c;\nr_ble_ll_event_comp_pkts = 0x40001050;\nr_ble_ll_event_dbuf_overflow = 0x40001054;\nr_ble_ll_event_rx_pkt = 0x40001058;\nr_ble_ll_event_send = 0x4000105c;\nr_ble_ll_event_tx_pkt = 0x40001060;\nr_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40001064;\nr_ble_ll_ext_conn_create = 0x40001068;\nr_ble_ll_ext_scan_coex_dpc_process = 0x4000106c;\nr_ble_ll_ext_scan_coex_dpc_pti_get = 0x40001070;\nr_ble_ll_ext_scan_coex_dpc_update = 0x40001074;\nr_ble_ll_ext_scan_coex_dpc_update_on_start = 0x40001078;\nr_ble_ll_ext_scan_parse_adv_info = 0x4000107c;\nr_ble_ll_ext_scan_parse_aux_ptr = 0x40001080;\nr_ble_ll_flush_pkt_queue = 0x40001084;\nr_ble_ll_generic_data_init = 0x40001088;\nr_ble_ll_get_addr_type = 0x4000108c;\nr_ble_ll_get_chan_to_scan = 0x40001090;\nr_ble_ll_get_our_devaddr = 0x40001094;\nr_ble_ll_get_tx_pwr_compensation = 0x40001098;\nr_ble_ll_hci_acl_rx = 0x4000109c;\nr_ble_ll_hci_adv_mode_ext = 0x400010a0;\nr_ble_ll_hci_adv_set_enable = 0x400010a4;\nr_ble_ll_hci_cb_host_buf_size = 0x400010a8;\nr_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x400010ac;\nr_ble_ll_hci_cb_set_event_mask = 0x400010b0;\nr_ble_ll_hci_cb_set_event_mask2 = 0x400010b4;\nr_ble_ll_hci_chk_phy_masks = 0x400010b8;\nr_ble_ll_hci_cmd_proc = 0x400010bc;\nr_ble_ll_hci_cmd_rx = 0x400010c0;\nr_ble_ll_hci_ctlr_bb_cmd_proc = 0x400010c4;\nr_ble_ll_hci_deinit = 0x400010c8;\nr_ble_ll_hci_disconnect = 0x400010cc;\nr_ble_ll_hci_dtm_rx_test = 0x400010d0;\nr_ble_ll_hci_dtm_rx_test_v2 = 0x400010d4;\nr_ble_ll_hci_dtm_tx_test = 0x400010d8;\nr_ble_ll_hci_dtm_tx_test_ext = 0x400010dc;\nr_ble_ll_hci_dtm_tx_test_v2 = 0x400010e0;\nr_ble_ll_hci_dtm_tx_test_v2_ext = 0x400010e4;\nr_ble_ll_hci_env_init = 0x400010e8;\nr_ble_ll_hci_ev_conn_update = 0x400010ec;\nr_ble_ll_hci_ev_databuf_overflow = 0x400010f0;\nr_ble_ll_hci_ev_datalen_chg = 0x400010f4;\nr_ble_ll_hci_ev_encrypt_chg = 0x400010f8;\nr_ble_ll_hci_ev_hw_err = 0x400010fc;\nr_ble_ll_hci_ev_le_csa = 0x40001100;\nr_ble_ll_hci_ev_ltk_req = 0x40001104;\nr_ble_ll_hci_ev_phy_update = 0x40001108;\nr_ble_ll_hci_ev_rd_rem_used_feat = 0x4000110c;\nr_ble_ll_hci_ev_rd_rem_ver = 0x40001110;\nr_ble_ll_hci_ev_rem_conn_parm_req = 0x40001114;\nr_ble_ll_hci_ev_send_adv_set_terminated = 0x40001118;\nr_ble_ll_hci_ev_send_scan_req_recv = 0x4000111c;\nr_ble_ll_hci_ev_send_scan_timeout = 0x40001120;\nr_ble_ll_hci_ev_send_vendor_err = 0x40001124;\nr_ble_ll_hci_event_send = 0x40001128;\nr_ble_ll_hci_ext_scan_set_enable = 0x4000112c;\nr_ble_ll_hci_get_num_cmd_pkts = 0x40001130;\nr_ble_ll_hci_info_params_cmd_proc = 0x40001134;\nr_ble_ll_hci_init = 0x40001138;\nr_ble_ll_hci_is_event_enabled = 0x4000113c;\nr_ble_ll_hci_is_le_event_enabled = 0x40001140;\nr_ble_ll_hci_le_cmd_proc = 0x40001144;\nr_ble_ll_hci_le_cmd_send_cmd_status = 0x40001148;\nr_ble_ll_hci_le_encrypt = 0x4000114c;\nr_ble_ll_hci_le_rand = 0x40001150;\nr_ble_ll_hci_le_rd_max_data_len = 0x40001154;\nr_ble_ll_hci_le_rd_sugg_data_len = 0x40001158;\nr_ble_ll_hci_le_read_bufsize = 0x4000115c;\nr_ble_ll_hci_le_read_local_features = 0x40001160;\nr_ble_ll_hci_le_read_supp_states = 0x40001164;\nr_ble_ll_hci_le_set_def_phy = 0x40001168;\nr_ble_ll_hci_le_wr_sugg_data_len = 0x4000116c;\nr_ble_ll_hci_link_ctrl_cmd_proc = 0x40001170;\nr_ble_ll_hci_npl_init = 0x40001174;\nr_ble_ll_hci_rd_bd_addr = 0x40001178;\nr_ble_ll_hci_rd_local_supp_cmd = 0x4000117c;\nr_ble_ll_hci_rd_local_supp_feat = 0x40001180;\nr_ble_ll_hci_rd_local_version = 0x40001184;\nr_ble_ll_hci_scan_set_enable = 0x40001188;\nr_ble_ll_hci_send_adv_report = 0x4000118c;\nr_ble_ll_hci_send_dir_adv_report = 0x40001190;\nr_ble_ll_hci_send_ext_adv_report = 0x40001194;\nr_ble_ll_hci_send_legacy_ext_adv_report = 0x40001198;\nr_ble_ll_hci_send_noop = 0x4000119c;\nr_ble_ll_hci_set_adv_data = 0x400011a0;\nr_ble_ll_hci_set_le_event_mask = 0x400011a4;\nr_ble_ll_hci_set_scan_rsp_data = 0x400011a8;\nr_ble_ll_hci_status_params_cmd_proc = 0x400011ac;\nr_ble_ll_hci_vs_cmd_proc = 0x400011b0;\nr_ble_ll_hci_vs_rd_static_addr = 0x400011b4;\nr_ble_ll_hw_err_timer_cb = 0x400011b8;\nr_ble_ll_hw_error = 0x400011bc;\nr_ble_ll_init = 0x400011c0;\nr_ble_ll_init_alloc_conn_comp_ev = 0x400011c4;\nr_ble_ll_init_get_conn_comp_ev = 0x400011c8;\nr_ble_ll_init_rx_isr_end = 0x400011cc;\nr_ble_ll_init_rx_isr_start = 0x400011d0;\nr_ble_ll_init_rx_pkt_in = 0x400011d4;\nr_ble_ll_is_addr_empty = 0x400011d8;\nr_ble_ll_is_controller_busy = 0x400011dc;\nr_ble_ll_is_on_resolv_list = 0x400011e0;\nr_ble_ll_is_our_devaddr = 0x400011e4;\nr_ble_ll_is_rpa = 0x400011e8;\nr_ble_ll_is_valid_adv_mode = 0x400011ec;\nr_ble_ll_is_valid_own_addr_type = 0x400011f0;\nr_ble_ll_is_valid_public_addr = 0x400011f4;\nr_ble_ll_is_valid_random_addr = 0x400011f8;\nr_ble_ll_mbuf_init = 0x400011fc;\nr_ble_ll_misc_options_set = 0x40001200;\nr_ble_ll_pdu_max_tx_octets_get = 0x40001204;\nr_ble_ll_pdu_tx_time_get = 0x40001208;\nr_ble_ll_per_adv_coex_dpc_calc_pti_update_itvl = 0x4000120c;\nr_ble_ll_per_adv_coex_dpc_process = 0x40001210;\nr_ble_ll_per_adv_coex_dpc_pti_get = 0x40001214;\nr_ble_ll_per_adv_coex_dpc_update = 0x40001218;\nr_ble_ll_per_adv_coex_dpc_update_on_data_updated = 0x4000121c;\nr_ble_ll_per_adv_coex_dpc_update_on_scheduled = 0x40001220;\nr_ble_ll_per_adv_coex_dpc_update_on_start = 0x40001224;\nr_ble_ll_phy_to_phy_mode = 0x40001228;\nr_ble_ll_process_rx_data = 0x4000122c;\nr_ble_ll_qa_enable = 0x40001230;\nr_ble_ll_rand = 0x40001234;\nr_ble_ll_rand_data_get = 0x40001238;\nr_ble_ll_rand_deinit = 0x4000123c;\nr_ble_ll_rand_env_init = 0x40001240;\nr_ble_ll_rand_init = 0x40001244;\nr_ble_ll_rand_prand_get = 0x40001248;\nr_ble_ll_rand_sample = 0x4000124c;\nr_ble_ll_rand_start = 0x40001250;\nr_ble_ll_read_rf_path_compensation = 0x40001254;\nr_ble_ll_read_supp_features = 0x40001258;\nr_ble_ll_read_supp_states = 0x4000125c;\nr_ble_ll_read_tx_power = 0x40001260;\nr_ble_ll_reset = 0x40001264;\nr_ble_ll_resolv_clear_all_pl_bit = 0x40001268;\nr_ble_ll_resolv_clear_all_wl_bit = 0x4000126c;\nr_ble_ll_resolv_deinit = 0x40001270;\nr_ble_ll_resolv_enable_cmd = 0x40001274;\nr_ble_ll_resolv_enabled = 0x40001278;\nr_ble_ll_resolv_env_init = 0x4000127c;\nr_ble_ll_resolv_gen_priv_addr = 0x40001280;\nr_ble_ll_resolv_gen_rpa = 0x40001284;\nr_ble_ll_resolv_get_addr_pointer = 0x40001288;\nr_ble_ll_resolv_get_entry = 0x4000128c;\nr_ble_ll_resolv_get_index = 0x40001290;\nr_ble_ll_resolv_get_irk_pointer = 0x40001294;\nr_ble_ll_resolv_get_list = 0x40001298;\nr_ble_ll_resolv_get_priv_addr = 0x4000129c;\nr_ble_ll_resolv_get_rpa_tmo = 0x400012a0;\nr_ble_ll_resolv_init = 0x400012a4;\nr_ble_ll_resolv_irk_nonzero = 0x400012a8;\nr_ble_ll_resolv_list_add = 0x400012ac;\nr_ble_ll_resolv_list_chg_allowed = 0x400012b0;\nr_ble_ll_resolv_list_clr = 0x400012b4;\nr_ble_ll_resolv_list_find = 0x400012b8;\nr_ble_ll_resolv_list_read_size = 0x400012bc;\nr_ble_ll_resolv_list_reset = 0x400012c0;\nr_ble_ll_resolv_list_rmv = 0x400012c4;\nr_ble_ll_resolv_local_addr_rd = 0x400012c8;\nr_ble_ll_resolv_peer_addr_rd = 0x400012cc;\nr_ble_ll_resolv_peer_rpa_any = 0x400012d0;\nr_ble_ll_resolv_reset = 0x400012d4;\nr_ble_ll_resolv_rpa = 0x400012d8;\nr_ble_ll_resolv_rpa_timer_cb = 0x400012dc;\nr_ble_ll_resolv_set_local_rpa = 0x400012e0;\nr_ble_ll_resolv_set_peer_rpa = 0x400012e4;\nr_ble_ll_resolv_set_rpa_tmo = 0x400012e8;\nr_ble_ll_resolve_set_priv_mode = 0x400012ec;\nr_ble_ll_rfmgmt_controller_sleep_en = 0x400012f0;\nr_ble_ll_rfmgmt_deinit = 0x400012f4;\nr_ble_ll_rfmgmt_disable = 0x400012f8;\nr_ble_ll_rfmgmt_enable = 0x400012fc;\nr_ble_ll_rfmgmt_enable_now = 0x40001300;\nr_ble_ll_rfmgmt_init = 0x40001304;\nr_ble_ll_rfmgmt_is_enabled = 0x40001308;\nr_ble_ll_rfmgmt_release = 0x4000130c;\nr_ble_ll_rfmgmt_release_ev = 0x40001310;\nr_ble_ll_rfmgmt_reset = 0x40001314;\nr_ble_ll_rfmgmt_scan_changed = 0x40001318;\nr_ble_ll_rfmgmt_sched_changed = 0x4000131c;\nr_ble_ll_rfmgmt_set_sleep_cb = 0x40001320;\nr_ble_ll_rfmgmt_ticks_to_enabled = 0x40001324;\nr_ble_ll_rfmgmt_timer_exp = 0x40001328;\nr_ble_ll_rfmgmt_timer_reschedule = 0x4000132c;\nr_ble_ll_rx_end = 0x40001330;\nr_ble_ll_rx_pdu_in = 0x40001334;\nr_ble_ll_rx_pkt_in = 0x40001338;\nr_ble_ll_rx_start = 0x4000133c;\nr_ble_ll_rxpdu_alloc = 0x40001340;\nr_ble_ll_scan_add_scan_rsp_adv = 0x40001344;\nr_ble_ll_scan_adv_decode_addr = 0x40001348;\nr_ble_ll_scan_aux_data_free = 0x4000134c;\nr_ble_ll_scan_aux_data_ref = 0x40001350;\nr_ble_ll_scan_aux_data_unref = 0x40001354;\nr_ble_ll_scan_can_chg_whitelist = 0x40001358;\nr_ble_ll_scan_check_periodic_sync = 0x4000135c;\nr_ble_ll_scan_chk_resume = 0x40001360;\nr_ble_ll_scan_clean_cur_aux_data = 0x40001364;\nr_ble_ll_scan_common_init = 0x40001368;\nr_ble_ll_scan_continue_en = 0x4000136c;\nr_ble_ll_scan_deinit = 0x40001370;\nr_ble_ll_scan_dup_check_ext = 0x40001374;\nr_ble_ll_scan_dup_check_legacy = 0x40001378;\nr_ble_ll_scan_dup_move_to_head = 0x4000137c;\nr_ble_ll_scan_dup_new = 0x40001380;\nr_ble_ll_scan_dup_update_ext = 0x40001384;\nr_ble_ll_scan_dup_update_legacy = 0x40001388;\nr_ble_ll_scan_duration_period_timers_restart = 0x4000138c;\nr_ble_ll_scan_duration_timer_cb = 0x40001390;\nr_ble_ll_scan_enabled = 0x40001394;\nr_ble_ll_scan_end_adv_evt = 0x40001398;\nr_ble_ll_scan_env_init = 0x4000139c;\nr_ble_ll_scan_event_proc = 0x400013a0;\nr_ble_ll_scan_ext_adv_init = 0x400013a4;\nr_ble_ll_scan_ext_initiator_start = 0x400013a8;\nr_ble_ll_scan_get_addr_data_from_legacy = 0x400013ac;\nr_ble_ll_scan_get_addr_from_ext_adv = 0x400013b0;\nr_ble_ll_scan_get_cur_sm = 0x400013b4;\nr_ble_ll_scan_get_ext_adv_report = 0x400013b8;\nr_ble_ll_scan_get_local_rpa = 0x400013bc;\nr_ble_ll_scan_get_next_adv_prim_chan = 0x400013c0;\nr_ble_ll_scan_get_pdu_data = 0x400013c4;\nr_ble_ll_scan_get_peer_rpa = 0x400013c8;\nr_ble_ll_scan_halt = 0x400013cc;\nr_ble_ll_scan_has_sent_scan_req = 0x400013d0;\nr_ble_ll_scan_have_rxd_scan_rsp = 0x400013d4;\nr_ble_ll_scan_init = 0x400013d8;\nr_ble_ll_scan_initiator_start = 0x400013dc;\nr_ble_ll_scan_interrupted = 0x400013e0;\nr_ble_ll_scan_interrupted_event_cb = 0x400013e4;\nr_ble_ll_scan_is_inside_window = 0x400013e8;\nr_ble_ll_scan_move_window_to = 0x400013ec;\nr_ble_ll_scan_npl_init = 0x400013f0;\nr_ble_ll_scan_npl_reset = 0x400013f4;\nr_ble_ll_scan_npl_restore = 0x400013f8;\nr_ble_ll_scan_npl_store = 0x400013fc;\nr_ble_ll_scan_parse_ext_hdr = 0x40001400;\nr_ble_ll_scan_period_timer_cb = 0x40001404;\nr_ble_ll_scan_record_new_adv = 0x40001408;\nr_ble_ll_scan_refresh_nrpa = 0x4000140c;\nr_ble_ll_scan_req_backoff = 0x40001410;\nr_ble_ll_scan_reset = 0x40001414;\nr_ble_ll_scan_rx_filter = 0x40001418;\nr_ble_ll_scan_rx_isr_end = 0x4000141c;\nr_ble_ll_scan_rx_isr_on_aux = 0x40001420;\nr_ble_ll_scan_rx_isr_on_legacy = 0x40001424;\nr_ble_ll_scan_rx_isr_start = 0x40001428;\nr_ble_ll_scan_rx_pkt_in = 0x4000142c;\nr_ble_ll_scan_rx_pkt_in_on_aux = 0x40001430;\nr_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001434;\nr_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001438;\nr_ble_ll_scan_rxed = 0x4000143c;\nr_ble_ll_scan_sched_remove = 0x40001440;\nr_ble_ll_scan_send_adv_report = 0x40001444;\nr_ble_ll_scan_send_truncated = 0x40001448;\nr_ble_ll_scan_set_enable = 0x4000144c;\nr_ble_ll_scan_set_peer_rpa = 0x40001450;\nr_ble_ll_scan_set_scan_params = 0x40001454;\nr_ble_ll_scan_sm_start = 0x40001458;\nr_ble_ll_scan_sm_stop = 0x4000145c;\nr_ble_ll_scan_start = 0x40001460;\nr_ble_ll_scan_time_hci_to_ticks = 0x40001464;\nr_ble_ll_scan_timer_cb = 0x40001468;\nr_ble_ll_scan_update_aux_data = 0x4000146c;\nr_ble_ll_scan_wfr_timer_exp = 0x40001470;\nr_ble_ll_scan_whitelist_enabled = 0x40001474;\nr_ble_ll_sched_adv_new = 0x40001478;\nr_ble_ll_sched_adv_resched_pdu = 0x4000147c;\nr_ble_ll_sched_adv_reschedule = 0x40001480;\nr_ble_ll_sched_aux_scan = 0x40001484;\nr_ble_ll_sched_conn_overlap = 0x40001488;\nr_ble_ll_sched_conn_reschedule = 0x4000148c;\nr_ble_ll_sched_deinit = 0x40001490;\nr_ble_ll_sched_dtm = 0x40001494;\nr_ble_ll_sched_env_init = 0x40001498;\nr_ble_ll_sched_execute_item = 0x4000149c;\nr_ble_ll_sched_init = 0x400014a0;\nr_ble_ll_sched_insert_if_empty = 0x400014a4;\nr_ble_ll_sched_is_overlap = 0x400014a8;\nr_ble_ll_sched_master_new = 0x400014ac;\nr_ble_ll_sched_next_time = 0x400014b0;\nr_ble_ll_sched_overlaps_current = 0x400014b4;\nr_ble_ll_sched_periodic_adv = 0x400014b8;\nr_ble_ll_sched_rmv_elem = 0x400014bc;\nr_ble_ll_sched_rmv_elem_type = 0x400014c0;\nr_ble_ll_sched_run = 0x400014c4;\nr_ble_ll_sched_scan_req_over_aux_ptr = 0x400014c8;\nr_ble_ll_sched_slave_new = 0x400014cc;\nr_ble_ll_sched_stop = 0x400014d0;\nr_ble_ll_sched_sync = 0x400014d4;\nr_ble_ll_sched_sync_overlaps_current = 0x400014d8;\nr_ble_ll_sched_sync_reschedule = 0x400014dc;\nr_ble_ll_set_default_privacy_mode = 0x400014e0;\nr_ble_ll_set_default_sync_transfer_params = 0x400014e4;\nr_ble_ll_set_ext_scan_params = 0x400014e8;\nr_ble_ll_set_host_feat = 0x400014ec;\nr_ble_ll_set_public_addr = 0x400014f0;\nr_ble_ll_set_random_addr = 0x400014f4;\nr_ble_ll_set_sync_transfer_params = 0x400014f8;\nr_ble_ll_slave_rx_isr_end = 0x400014fc;\nr_ble_ll_state_get = 0x40001500;\nr_ble_ll_state_set = 0x40001504;\nr_ble_ll_sync_adjust_ext_hdr = 0x40001508;\nr_ble_ll_sync_cancel = 0x4000150c;\nr_ble_ll_sync_cancel_complete_event = 0x40001510;\nr_ble_ll_sync_chain_start_cb = 0x40001514;\nr_ble_ll_sync_check_acad = 0x40001518;\nr_ble_ll_sync_check_failed = 0x4000151c;\nr_ble_ll_sync_coex_dpc_process = 0x40001520;\nr_ble_ll_sync_coex_dpc_pti_get = 0x40001524;\nr_ble_ll_sync_coex_dpc_update = 0x40001528;\nr_ble_ll_sync_create = 0x4000152c;\nr_ble_ll_sync_current_sm_over = 0x40001530;\nr_ble_ll_sync_deinit = 0x40001534;\nr_ble_ll_sync_enabled = 0x40001538;\nr_ble_ll_sync_env_init = 0x4000153c;\nr_ble_ll_sync_est_event_failed = 0x40001540;\nr_ble_ll_sync_est_event_success = 0x40001544;\nr_ble_ll_sync_established = 0x40001548;\nr_ble_ll_sync_event_end = 0x4000154c;\nr_ble_ll_sync_event_start_cb = 0x40001550;\nr_ble_ll_sync_filter_enabled = 0x40001554;\nr_ble_ll_sync_find = 0x40001558;\nr_ble_ll_sync_get_cur_sm = 0x4000155c;\nr_ble_ll_sync_get_event_end_time = 0x40001560;\nr_ble_ll_sync_get_handle = 0x40001564;\nr_ble_ll_sync_halt = 0x40001568;\nr_ble_ll_sync_has_been_reported = 0x4000156c;\nr_ble_ll_sync_info_event = 0x40001570;\nr_ble_ll_sync_init = 0x40001574;\nr_ble_ll_sync_list_add = 0x40001578;\nr_ble_ll_sync_list_clear = 0x4000157c;\nr_ble_ll_sync_list_empty = 0x40001580;\nr_ble_ll_sync_list_get_free = 0x40001584;\nr_ble_ll_sync_list_remove = 0x40001588;\nr_ble_ll_sync_list_search = 0x4000158c;\nr_ble_ll_sync_list_size = 0x40001590;\nr_ble_ll_sync_lost_event = 0x40001594;\nr_ble_ll_sync_next_event = 0x40001598;\nr_ble_ll_sync_on_list = 0x4000159c;\nr_ble_ll_sync_parse_aux_ptr = 0x400015a0;\nr_ble_ll_sync_parse_ext_hdr = 0x400015a4;\nr_ble_ll_sync_periodic_ind = 0x400015a8;\nr_ble_ll_sync_phy_mode_to_aux_phy = 0x400015ac;\nr_ble_ll_sync_phy_mode_to_hci = 0x400015b0;\nr_ble_ll_sync_put_syncinfo = 0x400015b4;\nr_ble_ll_sync_reserve = 0x400015b8;\nr_ble_ll_sync_reset = 0x400015bc;\nr_ble_ll_sync_reset_sm = 0x400015c0;\nr_ble_ll_sync_rmvd_from_sched = 0x400015c4;\nr_ble_ll_sync_rx_isr_end = 0x400015c8;\nr_ble_ll_sync_rx_isr_start = 0x400015cc;\nr_ble_ll_sync_rx_pkt_in = 0x400015d0;\nr_ble_ll_sync_schedule_chain = 0x400015d4;\nr_ble_ll_sync_send_per_adv_rpt = 0x400015d8;\nr_ble_ll_sync_send_sync_ind = 0x400015dc;\nr_ble_ll_sync_send_truncated_per_adv_rpt = 0x400015e0;\nr_ble_ll_sync_sm_clear = 0x400015e4;\nr_ble_ll_sync_terminate = 0x400015e8;\nr_ble_ll_sync_transfer = 0x400015ec;\nr_ble_ll_sync_transfer_get = 0x400015f0;\nr_ble_ll_sync_transfer_received = 0x400015f4;\nr_ble_ll_sync_wfr_timer_exp = 0x400015f8;\nr_ble_ll_task = 0x400015fc;\nr_ble_ll_trace_set_func = 0x40001600;\nr_ble_ll_trace_u32 = 0x40001604;\nr_ble_ll_trace_u32x2 = 0x40001608;\nr_ble_ll_trace_u32x3 = 0x4000160c;\nr_ble_ll_tx_flat_mbuf_pducb = 0x40001610;\nr_ble_ll_tx_mbuf_pducb = 0x40001614;\nr_ble_ll_tx_pkt_in = 0x40001618;\nr_ble_ll_update_max_tx_octets_phy_mode = 0x4000161c;\nr_ble_ll_usecs_to_ticks_round_up = 0x40001620;\nr_ble_ll_utils_calc_access_addr = 0x40001624;\nr_ble_ll_utils_calc_dci_csa2 = 0x40001628;\nr_ble_ll_utils_calc_num_used_chans = 0x4000162c;\nr_ble_ll_utils_calc_window_widening = 0x40001630;\nr_ble_ll_utils_csa2_perm = 0x40001634;\nr_ble_ll_utils_csa2_prng = 0x40001638;\nr_ble_ll_utils_remapped_channel = 0x4000163c;\nr_ble_ll_wfr_timer_exp = 0x40001640;\nr_ble_ll_whitelist_add = 0x40001644;\nr_ble_ll_whitelist_chg_allowed = 0x40001648;\nr_ble_ll_whitelist_clear = 0x4000164c;\nr_ble_ll_whitelist_read_size = 0x40001650;\nr_ble_ll_whitelist_rmv = 0x40001654;\nr_ble_ll_whitelist_search = 0x40001658;\nr_ble_ll_write_rf_path_compensation = 0x4000165c;\nr_ble_phy_access_addr_get = 0x40001660;\nr_ble_phy_bb_bug_is_triggered = 0x40001664;\nr_ble_phy_calculate_rxtx_ifs = 0x40001668;\nr_ble_phy_calculate_rxwindow = 0x4000166c;\nr_ble_phy_calculate_txrx_ifs = 0x40001670;\nr_ble_phy_config_access_addr = 0x40001674;\nr_ble_phy_data_make = 0x40001678;\nr_ble_phy_disable = 0x4000167c;\nr_ble_phy_disable_irq = 0x40001680;\nr_ble_phy_disable_whitening = 0x40001684;\nr_ble_phy_enable_scan_seq_immediately = 0x40001688;\nr_ble_phy_enable_whitening = 0x4000168c;\nr_ble_phy_encrypt_disable = 0x40001690;\nr_ble_phy_env_init = 0x40001694;\nr_ble_phy_get_current_phy = 0x40001698;\nr_ble_phy_get_packet_counter = 0x4000169c;\nr_ble_phy_get_packet_status = 0x400016a0;\nr_ble_phy_get_pyld_time_offset = 0x400016a4;\nr_ble_phy_get_rx_phy_mode = 0x400016a8;\nr_ble_phy_init = 0x400016ac;\nr_ble_phy_isr = 0x400016b0;\nr_ble_phy_max_data_pdu_pyld = 0x400016b4;\nr_ble_phy_mode_config = 0x400016b8;\nr_ble_phy_mode_convert = 0x400016bc;\nr_ble_phy_mode_write = 0x400016c0;\nr_ble_phy_module_deinit = 0x400016c4;\nr_ble_phy_module_init = 0x400016c8;\nr_ble_phy_monitor_bb_sync = 0x400016cc;\nr_ble_phy_need_to_report = 0x400016d0;\nr_ble_phy_pkt_received = 0x400016d4;\nr_ble_phy_reset_bb_monitor = 0x400016d8;\nr_ble_phy_resolv_list_disable = 0x400016dc;\nr_ble_phy_resolv_list_enable = 0x400016e0;\nr_ble_phy_restart_sequence = 0x400016e4;\nr_ble_phy_rfclk_disable = 0x400016e8;\nr_ble_phy_rfclk_enable = 0x400016ec;\nr_ble_phy_rx_is_expected = 0x400016f0;\nr_ble_phy_rxpdu_copy = 0x400016f4;\nr_ble_phy_scan_set_start_time = 0x400016f8;\nr_ble_phy_seq_encrypt_enable = 0x400016fc;\nr_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001700;\nr_ble_phy_sequence_adv_end = 0x40001704;\nr_ble_phy_sequence_copy_rx_flags = 0x40001708;\nr_ble_phy_sequence_end_isr = 0x4000170c;\nr_ble_phy_sequence_get_mode = 0x40001710;\nr_ble_phy_sequence_get_state = 0x40001714;\nr_ble_phy_sequence_init_end = 0x40001718;\nr_ble_phy_sequence_is_running = 0x4000171c;\nr_ble_phy_sequence_is_waiting_rsp = 0x40001720;\nr_ble_phy_sequence_isr_copy_data = 0x40001724;\nr_ble_phy_sequence_master_end = 0x40001728;\nr_ble_phy_sequence_rx_end_isr = 0x4000172c;\nr_ble_phy_sequence_scan_end = 0x40001730;\nr_ble_phy_sequence_single_end = 0x40001734;\nr_ble_phy_sequence_slave_end = 0x40001738;\nr_ble_phy_sequence_tx_end_invoke = 0x4000173c;\nr_ble_phy_sequence_update_conn_params = 0x40001740;\nr_ble_phy_set_adv_sequence = 0x40001744;\nr_ble_phy_set_coex_pti = 0x40001748;\nr_ble_phy_set_dev_address = 0x4000174c;\nr_ble_phy_set_master_sequence = 0x40001750;\nr_ble_phy_set_rx_pwr_compensation = 0x40001754;\nr_ble_phy_set_rxhdr_flags = 0x40001758;\nr_ble_phy_set_rxhdr_info = 0x4000175c;\nr_ble_phy_set_scan_sequence = 0x40001760;\nr_ble_phy_set_single_packet_rx_sequence = 0x40001764;\nr_ble_phy_set_single_packet_tx_sequence = 0x40001768;\nr_ble_phy_set_slave_sequence = 0x4000176c;\nr_ble_phy_set_txend_cb = 0x40001770;\nr_ble_phy_setchan = 0x40001774;\nr_ble_phy_slave_set_start_time = 0x40001778;\nr_ble_phy_state_get = 0x4000177c;\nr_ble_phy_timer_config_start_time = 0x40001780;\nr_ble_phy_timer_start_now = 0x40001784;\nr_ble_phy_timer_stop = 0x40001788;\nr_ble_phy_tx_set_start_time = 0x4000178c;\nr_ble_phy_txpower_round = 0x40001790;\nr_ble_phy_txpwr_set = 0x40001794;\nr_ble_phy_wfr_enable = 0x40001798;\nr_ble_phy_xcvr_state_get = 0x4000179c;\nr_ble_plf_set_log_level = 0x400017a0;\nr_ble_rtc_wake_up_cpu_init = 0x400017a4;\nr_ble_rtc_wake_up_state_clr = 0x400017a8;\nr_bleonly_os_tick_init = 0x400017ac;\nr_bt_rf_coex_cfg_set = 0x400017b0;\nr_bt_rf_coex_coded_txrx_time_upper_lim = 0x400017b4;\nr_bt_rf_coex_dft_pti_set = 0x400017b8;\nr_bt_rf_coex_hook_deinit = 0x400017bc;\nr_bt_rf_coex_hook_init = 0x400017c0;\nr_bt_rf_coex_hook_st_set = 0x400017c4;\nr_bt_rf_coex_hooks_p_set_default = 0x400017c8;\nr_btdm_disable_adv_delay = 0x400017cc;\nr_btdm_switch_phy_coded = 0x400017d0;\nr_esp_wait_disabled = 0x400017d4;\nr_get_be16 = 0x400017d8;\nr_get_be24 = 0x400017dc;\nr_get_be32 = 0x400017e0;\nr_get_be64 = 0x400017e4;\nr_get_le16 = 0x400017e8;\nr_get_le24 = 0x400017ec;\nr_get_le32 = 0x400017f0;\nr_get_le64 = 0x400017f4;\nr_get_local_irk_offset = 0x400017f8;\nr_get_local_rpa_offset = 0x400017fc;\nr_get_max_skip = 0x40001800;\nr_get_peer_id_offset = 0x40001804;\nr_get_peer_irk_offset = 0x40001808;\nr_get_peer_rpa_offset = 0x4000180c;\nr_hal_os_tick_read_tick = 0x40001810;\nr_hal_os_tick_set_exp_tick = 0x40001814;\nr_hal_rtc_intr_init = 0x40001818;\nr_hal_rtc_irq_handler = 0x4000181c;\nr_hal_timer_deinit = 0x40001820;\nr_hal_timer_disable_irq = 0x40001824;\nr_hal_timer_env_init = 0x40001828;\nr_hal_timer_init = 0x4000182c;\nr_hal_timer_process = 0x40001830;\nr_hal_timer_read = 0x40001834;\nr_hal_timer_read_tick = 0x40001838;\nr_hal_timer_set_cb = 0x4000183c;\nr_hal_timer_set_exp_tick = 0x40001840;\nr_hal_timer_start = 0x40001844;\nr_hal_timer_start_at = 0x40001848;\nr_hal_timer_stop = 0x4000184c;\nr_hal_timer_task_start = 0x40001850;\nr_ll_assert = 0x40001854;\nr_mem_init_mbuf_pool = 0x40001858;\nr_mem_malloc_mbuf_pool = 0x4000185c;\nr_mem_malloc_mbufpkt_pool = 0x40001860;\nr_mem_malloc_mempool = 0x40001864;\nr_mem_malloc_mempool_ext = 0x40001868;\nr_mem_malloc_mempool_gen = 0x4000186c;\nr_mem_pullup_obj = 0x40001870;\nr_mem_split_frag = 0x40001874;\nr_os_cputime_delay_ticks = 0x40001878;\nr_os_cputime_delay_usecs = 0x4000187c;\nr_os_cputime_get32 = 0x40001880;\nr_os_cputime_ticks_to_usecs = 0x40001884;\nr_os_cputime_timer_init = 0x40001888;\nr_os_cputime_timer_relative = 0x4000188c;\nr_os_cputime_timer_start = 0x40001890;\nr_os_cputime_timer_stop = 0x40001894;\nr_os_cputime_usecs_to_ticks = 0x40001898;\nr_os_mbuf_adj = 0x4000189c;\nr_os_mbuf_append = 0x400018a0;\nr_os_mbuf_appendfrom = 0x400018a4;\nr_os_mbuf_cmpf = 0x400018a8;\nr_os_mbuf_cmpm = 0x400018ac;\nr_os_mbuf_concat = 0x400018b0;\nr_os_mbuf_copydata = 0x400018b4;\nr_os_mbuf_copyinto = 0x400018b8;\nr_os_mbuf_dup = 0x400018bc;\nr_os_mbuf_extend = 0x400018c0;\nr_os_mbuf_free = 0x400018c4;\nr_os_mbuf_free_chain = 0x400018c8;\nr_os_mbuf_get = 0x400018cc;\nr_os_mbuf_get_pkthdr = 0x400018d0;\nr_os_mbuf_len = 0x400018d4;\nr_os_mbuf_off = 0x400018d8;\nr_os_mbuf_pack_chains = 0x400018dc;\nr_os_mbuf_pool_init = 0x400018e0;\nr_os_mbuf_prepend = 0x400018e4;\nr_os_mbuf_prepend_pullup = 0x400018e8;\nr_os_mbuf_pullup = 0x400018ec;\nr_os_mbuf_trim_front = 0x400018f0;\nr_os_mbuf_widen = 0x400018f4;\nr_os_memblock_from = 0x400018f8;\nr_os_memblock_get = 0x400018fc;\nr_os_memblock_put = 0x40001900;\nr_os_memblock_put_from_cb = 0x40001904;\nr_os_mempool_clear = 0x40001908;\nr_os_mempool_ext_clear = 0x4000190c;\nr_os_mempool_ext_init = 0x40001910;\nr_os_mempool_info_get_next = 0x40001914;\nr_os_mempool_init = 0x40001918;\nr_os_mempool_init_internal = 0x4000191c;\nr_os_mempool_is_sane = 0x40001920;\nr_os_mempool_module_init = 0x40001924;\nr_os_mempool_unregister = 0x40001928;\nr_os_mqueue_get = 0x4000192c;\nr_os_mqueue_init = 0x40001930;\nr_os_mqueue_put = 0x40001934;\nr_os_msys_count = 0x40001938;\nr_os_msys_get = 0x4000193c;\nr_os_msys_get_pkthdr = 0x40001940;\nr_os_msys_num_free = 0x40001944;\nr_os_msys_register = 0x40001948;\nr_os_msys_reset = 0x4000194c;\nr_os_tick_idle = 0x40001950;\nr_pri_phy_valid = 0x40001954;\nr_put_be16 = 0x40001958;\nr_put_be24 = 0x4000195c;\nr_put_be32 = 0x40001960;\nr_put_be64 = 0x40001964;\nr_put_le16 = 0x40001968;\nr_put_le24 = 0x4000196c;\nr_put_le32 = 0x40001970;\nr_put_le64 = 0x40001974;\nr_rtc0_timer_handler = 0x40001978;\nr_rtc1_timer_handler = 0x4000197c;\nr_sdkconfig_get_opts = 0x40001980;\nr_sdkconfig_set_opts = 0x40001984;\nr_sec_phy_valid = 0x40001988;\nr_sub24 = 0x4000198c;\nr_swap_buf = 0x40001990;\nr_swap_in_place = 0x40001994;\n\/* Data (.data, .bss, .rodata) *\/\nble_hci_uart_reset_cmd = 0x3ff4ffe0;\nble_hci_trans_env_p = 0x3fcdffc4;\nble_hci_trans_mode = 0x3fcdfeb8;\nble_ll_adv_env_p = 0x3fcdffc0;\nble_ll_conn_env_p = 0x3fcdffbc;\ng_ble_ll_conn_cth_flow = 0x3fcdffb4;\ng_ble_ll_conn_cth_flow_error_ev = 0x3fcdffb0;\ng_ble_ll_ctrl_pkt_lengths_ro = 0x3ff4ffbc;\nble_ll_dtm_module_env_p = 0x3fcdffac;\nchannel_rf_to_index = 0x3ff4ff94;\ng_ble_ll_dtm_prbs15_data = 0x3ff4fe94;\ng_ble_ll_dtm_prbs9_data = 0x3ff4fd94;\nble_ll_hci_env_p = 0x3fcdffa8;\nble_ll_rand_env_p = 0x3fcdffa4;\nble_ll_resolv_env_p = 0x3fcdffa0;\ng_ble_ll_resolve_hdr = 0x3fcdff98;\ng_device_mode_default = 0x3fcdfeb6;\ng_ble_ll_rfmgmt_data = 0x3fcdff50;\ng_ble_sleep_enter_cb = 0x3fcdff4c;\ng_ble_sleep_exit_cb = 0x3fcdff48;\ng_rfclk_enabled = 0x3fcdff44;\nble_ll_scan_env_p = 0x3fcdff40;\nble_ll_sched_env_p = 0x3fcdff3c;\ng_ble_ll_supp_cmds_ro = 0x3ff4fd64;\nble_ll_sync_env_p = 0x3fcdff38;\ng_ble_sca_ppm_tbl_ro = 0x3ff4fd54;\nble_ll_env_p = 0x3fcdff34;\ng_ble_ll_pdu_header_tx_time_ro = 0x3ff4fd4c;\npriv_config_opts = 0x3fcdfea0;\nble_hci_trans_funcs_ptr = 0x3fcdff30;\nr_ble_stub_funcs_ptr = 0x3fcdff2c;\nr_ext_funcs_p = 0x3fcdff28;\nr_npl_funcs = 0x3fcdff24;\nble_hw_env_p = 0x3fcdff20;\nalready_inited.10221 = 0x3fcdff1c;\nble_phy_module_env_p = 0x3fcdff18;\ng_ble_phy_chan_freq_ro = 0x3ff4fd24;\ng_ble_phy_mode_pkt_start_off_ro = 0x3ff4fd1c;\ng_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fd0c;\ng_ble_phy_t_rxaddrdelay_ro = 0x3ff4fd08;\ng_ble_phy_t_rxenddelay_ro = 0x3ff4fd04;\ng_ble_phy_t_txdelay_ro = 0x3ff4fd00;\ng_ble_phy_t_txenddelay_ro = 0x3ff4fcfc;\ng_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcec;\nhal_timer_env_p = 0x3fcdff14;\ng_hal_os_tick = 0x3fcdff08;\nr_osi_coex_funcs_p = 0x3fcdff04;\nbt_rf_coex_hooks = 0x3fcdfefc;\nbt_rf_coex_hooks_p = 0x3fcdfef8;\ncoex_hook_st_group_tab = 0x3ff4fce0;\ncoex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcdc;\ns_ble_act_count_by_group = 0x3fcdfef4;\ns_ble_coex_st_map = 0x3fcdfee0;\nbt_rf_coex_cfg_cb = 0x3fcdfec4;\nbt_rf_coex_cfg_p = 0x3fcdfec0;\nbt_rf_coex_cfg_rom = 0x3ff4fcc0;\nbt_rf_coex_pti_dft_p = 0x3fcdfebc;\nbt_rf_coex_pti_dft_rom = 0x3fcdfe60;\nconn_dynamic_pti_param_rom = 0x3ff4fca8;\nconn_phy_coded_max_data_time_param_rom = 0x3ff4fca4;\next_adv_dynamic_pti_param_rom = 0x3ff4fc70;\next_scan_dynamic_param_rom = 0x3ff4fc38;\nlegacy_adv_dynamic_pti_param_rom = 0x3ff4fc18;\nper_adv_dynamic_pti_param_rom = 0x3ff4fbfc;\nsync_dynamic_param_rom = 0x3ff4fbe4;\ng_ble_plf_log_level = 0x3fcdfe5c;\ng_msys_pool_list = 0x3fcdfe54;\ng_os_mempool_list = 0x3fcdfe4c;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x40001998;\nRC_GetBlockAckTime = 0x4000199c;\nebuf_list_remove = 0x400019a0;\nesf_buf_alloc = 0x400019a4;\nesf_buf_alloc_dynamic = 0x400019a8;\nesf_buf_recycle = 0x400019ac;\nGetAccess = 0x400019b0;\nhal_mac_is_low_rate_enabled = 0x400019b4;\nhal_mac_tx_get_blockack = 0x400019b8;\nhal_mac_tx_set_ppdu = 0x400019bc;\nic_get_trc = 0x400019c0;\nic_mac_deinit = 0x400019c4;\nic_mac_init = 0x400019c8;\nic_interface_enabled = 0x400019cc;\nis_lmac_idle = 0x400019d0;\nlmacAdjustTimestamp = 0x400019d4;\nlmacDiscardAgedMSDU = 0x400019d8;\nlmacDiscardMSDU = 0x400019dc;\nlmacEndFrameExchangeSequence = 0x400019e0;\nlmacIsIdle = 0x400019e4;\nlmacIsLongFrame = 0x400019e8;\nlmacMSDUAged = 0x400019ec;\nlmacPostTxComplete = 0x400019f0;\nlmacProcessAllTxTimeout = 0x400019f4;\nlmacProcessCollisions = 0x400019f8;\nlmacProcessRxSucData = 0x400019fc;\nlmacReachLongLimit = 0x40001a00;\nlmacReachShortLimit = 0x40001a04;\nlmacRecycleMPDU = 0x40001a08;\nlmacRxDone = 0x40001a0c;\nlmacSetTxFrame = 0x40001a10;\nlmacTxDone = 0x40001a14;\nlmacTxFrame = 0x40001a18;\nmac_tx_set_duration = 0x40001a1c;\nmac_tx_set_htsig = 0x40001a20;\nmac_tx_set_plcp0 = 0x40001a24;\nmac_tx_set_plcp1 = 0x40001a28;\nmac_tx_set_plcp2 = 0x40001a2c;\npm_check_state = 0x40001a30;\npm_disable_dream_timer = 0x40001a34;\npm_disable_sleep_delay_timer = 0x40001a38;\npm_dream = 0x40001a3c;\npm_mac_wakeup = 0x40001a40;\npm_mac_sleep = 0x40001a44;\npm_enable_active_timer = 0x40001a48;\npm_enable_sleep_delay_timer = 0x40001a4c;\npm_local_tsf_process = 0x40001a50;\npm_set_beacon_filter = 0x40001a54;\npm_is_in_wifi_slice_threshold = 0x40001a58;\npm_is_waked = 0x40001a5c;\npm_keep_alive = 0x40001a60;\npm_on_beacon_rx = 0x40001a64;\npm_on_data_rx = 0x40001a68;\npm_on_tbtt = 0x40001a6c;\npm_parse_beacon = 0x40001a70;\npm_process_tim = 0x40001a74;\npm_rx_beacon_process = 0x40001a78;\npm_rx_data_process = 0x40001a7c;\npm_sleep = 0x40001a80;\npm_sleep_for = 0x40001a84;\npm_tbtt_process = 0x40001a88;\nppAMPDU2Normal = 0x40001a8c;\nppAssembleAMPDU = 0x40001a90;\nppCalFrameTimes = 0x40001a94;\nppCalSubFrameLength = 0x40001a98;\nppCalTxAMPDULength = 0x40001a9c;\nppCheckTxAMPDUlength = 0x40001aa0;\nppDequeueRxq_Locked = 0x40001aa4;\nppDequeueTxQ = 0x40001aa8;\nppEmptyDelimiterLength = 0x40001aac;\nppEnqueueRxq = 0x40001ab0;\nppEnqueueTxDone = 0x40001ab4;\nppGetTxQFirstAvail_Locked = 0x40001ab8;\nppGetTxframe = 0x40001abc;\nppMapTxQueue = 0x40001ac0;\nppProcTxSecFrame = 0x40001ac4;\nppProcessRxPktHdr = 0x40001ac8;\nppProcessTxQ = 0x40001acc;\nppRecordBarRRC = 0x40001ad0;\nlmacRequestTxopQueue = 0x40001ad4;\nlmacReleaseTxopQueue = 0x40001ad8;\nppRecycleAmpdu = 0x40001adc;\nppRecycleRxPkt = 0x40001ae0;\nppResortTxAMPDU = 0x40001ae4;\nppResumeTxAMPDU = 0x40001ae8;\n\/* ppRxFragmentProc = 0x40001aec; *\/\nppRxPkt = 0x40001af0;\nppRxProtoProc = 0x40001af4;\nppSearchTxQueue = 0x40001af8;\nppSearchTxframe = 0x40001afc;\nppSelectNextQueue = 0x40001b00;\nppSubFromAMPDU = 0x40001b04;\nppTask = 0x40001b08;\nppTxPkt = 0x40001b0c;\nppTxProtoProc = 0x40001b10;\nppTxqUpdateBitmap = 0x40001b14;\npp_coex_tx_request = 0x40001b18;\npp_hdrsize = 0x40001b1c;\npp_post = 0x40001b20;\npp_process_hmac_waiting_txq = 0x40001b24;\nrcGetAmpduSched = 0x40001b28;\nrcUpdateRxDone = 0x40001b2c;\nrc_get_trc = 0x40001b30;\nrc_get_trc_by_index = 0x40001b34;\nrcAmpduLowerRate = 0x40001b38;\nrcampduuprate = 0x40001b3c;\nrcClearCurAMPDUSched = 0x40001b40;\nrcClearCurSched = 0x40001b44;\nrcClearCurStat = 0x40001b48;\nrcGetSched = 0x40001b4c;\nrcLowerSched = 0x40001b50;\nrcSetTxAmpduLimit = 0x40001b54;\nrcTxUpdatePer = 0x40001b58;\nrcUpdateAckSnr = 0x40001b5c;\nrcUpdateRate = 0x40001b60;\nrcUpdateTxDone = 0x40001b64;\nrcUpdateTxDoneAmpdu2 = 0x40001b68;\nrcUpSched = 0x40001b6c;\nrssi_margin = 0x40001b70;\nrx11NRate2AMPDULimit = 0x40001b74;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001b78;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001b7c;\ntrc_calc_duration = 0x40001b80;\ntrc_isTxAmpduOperational = 0x40001b84;\ntrc_onAmpduOp = 0x40001b88;\nTRC_PER_IS_GOOD = 0x40001b8c;\ntrc_SetTxAmpduState = 0x40001b90;\ntrc_tid_isTxAmpduOperational = 0x40001b94;\ntrcAmpduSetState = 0x40001b98;\nwDevCheckBlockError = 0x40001b9c;\nwDev_AppendRxBlocks = 0x40001ba0;\nwDev_DiscardFrame = 0x40001ba4;\nwDev_GetNoiseFloor = 0x40001ba8;\nwDev_IndicateAmpdu = 0x40001bac;\nwDev_IndicateFrame = 0x40001bb0;\nwdev_bank_store = 0x40001bb4;\nwdev_bank_load = 0x40001bb8;\nwdev_mac_reg_load = 0x40001bbc;\nwdev_mac_reg_store = 0x40001bc0;\nwdev_mac_special_reg_load = 0x40001bc4;\nwdev_mac_special_reg_store = 0x40001bc8;\nwdev_mac_wakeup = 0x40001bcc;\nwdev_mac_sleep = 0x40001bd0;\nwDev_ProcessFiq = 0x40001bd4;\nwDev_ProcessRxSucData = 0x40001bd8;\nwdevProcessRxSucDataAll = 0x40001bdc;\nwdev_csi_len_align = 0x40001be0;\nppDequeueTxDone_Locked = 0x40001be4;\nppProcTxDone = 0x40001be8;\npm_tx_data_done_process = 0x40001bec;\nconfig_is_cache_tx_buf_enabled = 0x40001bf0;\nppMapWaitTxq = 0x40001bf4;\nppProcessWaitingQueue = 0x40001bf8;\nppDisableQueue = 0x40001bfc;\npm_allow_tx = 0x40001c00;\nwdev_is_data_in_rxlist = 0x40001c04;\nppProcTxCallback = 0x40001c08;\npm_is_open = 0x40001c0c;\npm_wake_up = 0x40001c10;\npm_wake_done = 0x40001c14;\npm_disable_disconnected_sleep_delay_timer = 0x40001c18;\npm_enable_disconnected_sleep_delay_timer = 0x40001c1c;\nhal_mac_get_txq_state = 0x40001c20;\nhal_mac_clr_txq_state = 0x40001c24;\nhal_mac_tx_set_cca = 0x40001c28;\nhal_mac_set_txq_invalid = 0x40001c2c;\nhal_mac_txq_disable = 0x40001c30;\nhal_mac_is_txq_enabled = 0x40001c34;\nhal_mac_get_txq_pmd = 0x40001c38;\nlmacDiscardFrameExchangeSequence = 0x40001c3c;\nlmacDisableTransmit = 0x40001c40;\nlmacProcessTxTimeout = 0x40001c44;\nlmacProcessTxSuccess = 0x40001c48;\nlmacProcessCollision = 0x40001c4c;\nlmacProcessTxRtsError = 0x40001c50;\nlmacProcessCtsTimeout = 0x40001c54;\nlmacProcessTxComplete = 0x40001c58;\nlmacProcessAckTimeout = 0x40001c5c;\nlmacProcessTxError = 0x40001c60;\nlmacProcessTxseckiderr = 0x40001c64;\nrcReachRetryLimit = 0x40001c68;\nlmacProcessShortRetryFail = 0x40001c6c;\nlmacEndRetryAMPDUFail = 0x40001c70;\nppFillAMPDUBar = 0x40001c74;\nrcGetRate = 0x40001c78;\nppReSendBar = 0x40001c7c;\nlmacProcessLongRetryFail = 0x40001c80;\nlmacRetryTxFrame = 0x40001c84;\nlmacProcessCollisions_task = 0x40001c88;\nlmacProcessTxopQComplete = 0x40001c8c;\nlmacInitAc = 0x40001c90;\nlmacInit = 0x40001c94;\nmac_tx_set_txop_q = 0x40001c98;\nhal_init = 0x40001c9c;\nhal_mac_rx_set_policy = 0x40001ca0;\nhal_mac_set_bssid = 0x40001ca4;\nmac_rx_policy_init = 0x40001ca8;\nmac_txrx_init = 0x40001cac;\nmac_rxbuf_init = 0x40001cb0;\nmac_last_rxbuf_init = 0x40001cb4;\nhal_attenna_init = 0x40001cb8;\nhal_timer_update_by_rtc = 0x40001cbc;\nhal_coex_pti_init = 0x40001cc0;\nlmac_stop_hw_txq = 0x40001cc4;\nppDirectRecycleAmpdu = 0x40001cc8;\nesp_wifi_internal_set_rts = 0x40001ccc;\nesp_wifi_internal_get_rts = 0x40001cd0;\nppTxFragmentProc = 0x40001cd4;\nesf_buf_setup = 0x40001cd8;\nhal_agreement_add_rx_ba = 0x40001cdc;\nhal_agreement_del_rx_ba = 0x40001ce0;\nhal_crypto_set_key_entry = 0x40001ce4;\nhal_crypto_get_key_entry = 0x40001ce8;\nhal_crypto_clr_key_entry = 0x40001cec;\nconfig_get_wifi_task_stack_size = 0x40001cf0;\npp_create_task = 0x40001cf4;\nhal_set_sta_tsf_wakeup = 0x40001cf8;\nhal_set_rx_beacon_pti = 0x40001cfc;\npm_start = 0x40001d00;\npm_stop = 0x40001d04;\nhal_disable_sta_tbtt = 0x40001d08;\nppCalTxopDur = 0x40001d0c;\nwDev_IndicateCtrlFrame = 0x40001d10;\nhal_enable_sta_tbtt = 0x40001d14;\nhal_set_sta_tbtt = 0x40001d18;\npm_update_next_tbtt = 0x40001d1c;\npm_set_sleep_type = 0x40001d20;\nwDev_Rxbuf_Init = 0x40001d24;\nwDev_Rxbuf_Deinit = 0x40001d28;\nppCalTkipMic = 0x40001d2c;\n\/\/wDev_SnifferRxData = 0x40001d30;\nhal_crypto_enable = 0x40001d34;\nhal_crypto_disable = 0x40001d38;\nwDev_Insert_KeyEntry = 0x40001d3c;\nwDev_remove_KeyEntry = 0x40001d40;\nrc_enable_trc = 0x40001d44;\nrc_set_per_conn_fix_rate = 0x40001d48;\nwdev_csi_rx_process = 0x40001d4c;\nwDev_SnifferRxAmpdu = 0x40001d50;\nhal_mac_tsf_reset = 0x40001d54;\ndbg_lmac_statis_dump = 0x40001d58;\ndbg_lmac_rxtx_statis_dump = 0x40001d5c;\ndbg_lmac_hw_statis_dump = 0x40001d60;\ndbg_lmac_diag_statis_dump = 0x40001d64;\ndbg_lmac_ps_statis_dump = 0x40001d68;\npp_timer_do_process = 0x40001d6c;\nrcUpdateAMPDUParam = 0x40001d70;\nrcUpdatePhyMode = 0x40001d74;\nrcGetHighestRateIdx = 0x40001d78;\npm_tx_null_data_done_process = 0x40001d7c;\npm_tx_data_process = 0x40001d80;\npm_attach = 0x40001d84;\npm_coex_schm_process = 0x40001d88;\nppInitTxq = 0x40001d8c;\npp_attach = 0x40001d90;\npp_deattach = 0x40001d94;\npm_on_probe_resp_rx = 0x40001d98;\nhal_set_sta_tsf = 0x40001d9c;\nic_update_sta_tsf = 0x40001da0;\nic_tx_pkt = 0x40001da4;\npm_send_probe_stop = 0x40001da8;\nsta_pm_phy_ref_release = 0x40001dac;\nsta_pm_phy_ref_acquire = 0x40001db0;\npm_send_probe_start = 0x40001db4;\npm_on_coex_schm_process_restart = 0x40001db8;\nhal_mac_set_rxq_policy = 0x40001dbc;\nhal_sniffer_enable = 0x40001dc0;\nhal_sniffer_disable = 0x40001dc4;\nhal_sniffer_rx_set_promis = 0x40001dc8;\nhal_sniffer_rx_clr_statistics = 0x40001dcc;\nhal_sniffer_set_promis_misc_pkt = 0x40001dd0;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff4fbe0;\npTxRx = 0x3fcdfe48;\nlmacConfMib_ptr = 0x3fcdfe44;\nour_wait_eb = 0x3fcdfe40;\nour_tx_eb = 0x3fcdfe3c;\npp_wdev_funcs = 0x3fcdfe38;\ng_osi_funcs_p = 0x3fcdfe34;\nwDevCtrl_ptr = 0x3fcdfe30;\ng_wdev_last_desc_reset_ptr = 0x3ff4fbdc;\nwDevMacSleep_ptr = 0x3fcdfe2c;\ng_lmac_cnt_ptr = 0x3fcdfe28;\nour_controls_ptr = 0x3ff4fbd8;\npp_sig_cnt_ptr = 0x3fcdfe24;\ng_eb_list_desc_ptr = 0x3fcdfe20;\ns_fragment_ptr = 0x3fcdfe1c;\nif_ctrl_ptr = 0x3fcdfe18;\ng_intr_lock_mux = 0x3fcdfe14;\ng_wifi_global_lock = 0x3fcdfe10;\ns_wifi_queue = 0x3fcdfe0c;\npp_task_hdl = 0x3fcdfe08;\ns_pp_task_create_sem = 0x3fcdfe04;\ns_pp_task_del_sem = 0x3fcdfe00;\ng_wifi_menuconfig_ptr = 0x3fcdfdfc;\nxphyQueue = 0x3fcdfdf8;\nap_no_lr_ptr = 0x3fcdfdf4;\nrc11BSchedTbl_ptr = 0x3fcdfdf0;\nrc11NSchedTbl_ptr = 0x3fcdfdec;\nrcLoRaSchedTbl_ptr = 0x3fcdfde8;\nBasicOFDMSched_ptr = 0x3fcdfde4;\ntrc_ctl_ptr = 0x3fcdfde0;\ng_pm_cnt_ptr = 0x3fcdfddc;\ng_pm_ptr = 0x3fcdfdd8;\ng_pm_cfg_ptr = 0x3fcdfdd4;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdfdd0;\ng_txop_queue_status_ptr = 0x3fcdfdcc;\ng_mac_sleep_en_ptr = 0x3fcdfdc8;\ng_mesh_is_root_ptr = 0x3fcdfdc4;\ng_mesh_topology_ptr = 0x3fcdfdc0;\ng_mesh_init_ps_type_ptr = 0x3fcdfdbc;\ng_mesh_is_started_ptr = 0x3fcdfdb8;\ng_config_func = 0x3fcdfdb4;\ng_net80211_tx_func = 0x3fcdfdb0;\ng_timer_func = 0x3fcdfdac;\ns_michael_mic_failure_cb = 0x3fcdfda8;\nwifi_sta_rx_probe_req = 0x3fcdfda4;\ng_tx_done_cb_func = 0x3fcdfda0;\ng_per_conn_trc = 0x3fcdfd84;\ns_encap_amsdu_func = 0x3fcdfd80;\nbars = 0x3fcdfce0;\neb_txdesc_space = 0x3fcdfc50;\neb_space = 0x3fcdfbb0;\ng_pd_mac_in_light_sleep = 0x3fcdfbac;\ns_fix_rate_mask = 0x3fcdfba8;\ns_fix_rate = 0x3fcdfba0;\ng_wdev_csi_rx = 0x3fcdfb9c;\ng_wdev_csi_rx_ctx = 0x3fcdfb98;\nBcnSendTick = 0x3fcdfb94;\ng_pp_timer_info_ptr = 0x3fcdfb90;\nrcP2P11NSchedTbl_ptr = 0x3fcdfb8c;\nrcP2P11GSchedTbl_ptr = 0x3fcdfb88;\nrc11GSchedTbl_ptr = 0x3fcdfb84;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001dd4;\nampdu_dispatch = 0x40001dd8;\nampdu_dispatch_all = 0x40001ddc;\nampdu_dispatch_as_many_as_possible = 0x40001de0;\nampdu_dispatch_movement = 0x40001de4;\nampdu_dispatch_upto = 0x40001de8;\nchm_is_at_home_channel = 0x40001dec;\ncnx_node_is_existing = 0x40001df0;\ncnx_node_search = 0x40001df4;\nic_ebuf_recycle_rx = 0x40001df8;\nic_ebuf_recycle_tx = 0x40001dfc;\nic_reset_rx_ba = 0x40001e00;\nieee80211_align_eb = 0x40001e04;\nieee80211_ampdu_reorder = 0x40001e08;\nieee80211_ampdu_start_age_timer = 0x40001e0c;\nieee80211_encap_esfbuf = 0x40001e10;\nieee80211_is_tx_allowed = 0x40001e14;\nieee80211_output_pending_eb = 0x40001e18;\nieee80211_output_process = 0x40001e1c;\nieee80211_set_tx_desc = 0x40001e20;\nsta_input = 0x40001e24;\nwifi_get_macaddr = 0x40001e28;\nwifi_rf_phy_disable = 0x40001e2c;\nwifi_rf_phy_enable = 0x40001e30;\nic_ebuf_alloc = 0x40001e34;\nieee80211_classify = 0x40001e38;\nieee80211_copy_eb_header = 0x40001e3c;\nieee80211_recycle_cache_eb = 0x40001e40;\nieee80211_search_node = 0x40001e44;\nroundup2 = 0x40001e48;\nieee80211_crypto_encap = 0x40001e4c;\nieee80211_crypto_decap = 0x40001e50;\nieee80211_decap = 0x40001e54;\nieee80211_set_tx_pti = 0x40001e58;\nwifi_is_started = 0x40001e5c;\nieee80211_gettid = 0x40001e60;\nieee80211_ccmp_decrypt = 0x40001e64;\nieee80211_ccmp_encrypt = 0x40001e68;\nccmp_encap = 0x40001e6c;\nccmp_decap = 0x40001e70;\ntkip_encap = 0x40001e74;\ntkip_decap = 0x40001e78;\nwep_encap = 0x40001e7c;\nwep_decap = 0x40001e80;\ndbg_hmac_rxtx_statis_dump = 0x40001e84;\ndbg_hmac_statis_dump = 0x40001e88;\nieee80211_send_action_vendor_spec = 0x40001e8c;\nieee80211_send_mgmt = 0x40001e90;\nieee80211_auth_construct = 0x40001e94;\nieee80211_deauth_construct = 0x40001e98;\nieee80211_disassoc_construct = 0x40001e9c;\nieee80211_vnd_lora_ie_size = 0x40001ea0;\nieee80211_vnd_ie_size = 0x40001ea4;\nieee80211_add_ssid = 0x40001ea8;\nieee80211_add_rates = 0x40001eac;\nieee80211_add_xrates = 0x40001eb0;\nieee80211_is_ht_cipher = 0x40001eb4;\nieee80211_assoc_req_construct = 0x40001eb8;\nieee80211_assoc_resp_construct = 0x40001ebc;\nieee80211_setup_lr_rates = 0x40001ec0;\nieee80211_ht_node_init = 0x40001ec4;\nieee80211_is_support_rate = 0x40001ec8;\nieee80211_setup_rates = 0x40001ecc;\nieee80211_is_lr_only = 0x40001ed0;\nieee80211_setup_phy_mode = 0x40001ed4;\nieee80211_sta_is_connected = 0x40001ed8;\ncurrent_task_is_wifi_task = 0x40001edc;\nwifi_get_init_state = 0x40001ee0;\nieee80211_timer_process = 0x40001ee4;\ncnx_coexist_timeout = 0x40001ee8;\nsta_recv_mgmt = 0x40001eec;\nieee80211_send_setup = 0x40001ef0;\nieee80211_send_probereq = 0x40001ef4;\nsta_auth_open = 0x40001ef8;\nsta_auth_shared = 0x40001efc;\nsta_auth_sae = 0x40001f00;\ncnx_coexist_timeout_process = 0x40001f04;\nieee80211_alloc_challenge = 0x40001f08;\ncnx_assoc_timeout = 0x40001f0c;\nieee80211_vnd_ie_set = 0x40001f10;\nieee80211_vnd_lora_ie_set = 0x40001f14;\nieee80211_add_wme_param = 0x40001f18;\nieee80211_add_dsparams = 0x40001f1c;\nieee80211_add_csa = 0x40001f20;\nieee80211_add_extcap = 0x40001f24;\nieee80211_regdomain_get_country = 0x40001f28;\nieee80211_add_countryie = 0x40001f2c;\nieee80211_alloc_proberesp = 0x40001f30;\nieee80211_amsdu_adjust_head = 0x40001f34;\nieee80211_amsdu_adjust_last_length = 0x40001f38;\nieee80211_amsdu_send_check = 0x40001f3c;\nieee80211_amsdu_encap_check = 0x40001f40;\nieee80211_amsdu_length_check = 0x40001f44;\nieee80211_encap_amsdu = 0x40001f48;\nieee80211_output_raw_process = 0x40001f4c;\nesp_wifi_80211_tx = 0x40001f50;\nieee80211_raw_frame_sanity_check = 0x40001f54;\nieee80211_crypto_aes_128_cmac_encrypt = 0x40001f58;\nieee80211_crypto_aes_128_cmac_decrypt = 0x40001f5c;\nieee80211_alloc_tx_buf = 0x40001f60;\nieee80211_output_do = 0x40001f64;\nieee80211_send_nulldata = 0x40001f68;\nieee80211_setup_robust_mgmtframe = 0x40001f6c;\nieee80211_mgmt_output = 0x40001f70;\nieee80211_encap_null_data = 0x40001f74;\nieee80211_send_deauth = 0x40001f78;\nieee80211_alloc_deauth = 0x40001f7c;\nieee80211_send_proberesp = 0x40001f80;\nieee80211_tx_mgt_cb = 0x40001f84;\nieee80211_getcapinfo = 0x40001f88;\nsta_rx_csa = 0x40001f8c;\nsta_send_sa_query_req = 0x40001f90;\nsta_send_sa_query_resp = 0x40001f94;\nsta_recv_sa_query_req = 0x40001f98;\nsta_recv_sa_query_resp = 0x40001f9c;\nieee80211_parse_beacon = 0x40001fa0;\nieee80211_set_max_rate = 0x40001fa4;\nic_set_sta = 0x40001fa8;\nieee80211_match_security = 0x40001fac;\nieee80211_parse_wpa = 0x40001fb0;\nieee80211_parse_rsn = 0x40001fb4;\nieee80211_add_assoc_req_ies = 0x40001fb8;\nieee80211_add_probe_req_ies = 0x40001fbc;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdfb80;\ng_scan = 0x3fcdfb7c;\ng_chm = 0x3fcdfb78;\ng_ic_ptr = 0x3fcdfb74;\ng_hmac_cnt_ptr = 0x3fcdfb50;\ng_tx_cacheq_ptr = 0x3fcdfb70;\ns_netstack_free = 0x3fcdfb6c;\nmesh_rxcb = 0x3fcdfb68;\nsta_rxcb = 0x3fcdfb64;\nccmp_ptr = 0x3fcdfb60;\ns_wifi_nvs_ptr = 0x3fcdfb5c;\ntkip_ptr = 0x3fcdfb58;\nwep_ptr = 0x3fcdfb54;\ng_hmac_cnt_ptr = 0x3fcdfb50;\ng_misc_nvs = 0x3fcdfb4c;\ns_wifi_init_state = 0x3fcdfb1c;\ns_wifi_task_hdl = 0x3fcdfb48;\nin_rssi_adjust = 0x3fcdfb44;\nrssi_saved = 0x3fcdfb3c;\nrssi_index = 0x3fcdfb38;\ns_sa_query_retries = 0x3fcdfb34;\ns_sa_query_success = 0x3fcdfb31;\ng_sta_connected_flag = 0x3fcdfb30;\nwpa_crypto_funcs_ptr = 0x3fcdfb2c;\ns_netstack_ref = 0x3fcdfb28;\nsta_csa_timer_ptr = 0x3fcdfb24;\ns_trans_id = 0x3fcdfb20;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x40001fc0;\ncoex_bt_release = 0x40001fc4;\ncoex_bt_request = 0x40001fc8;\ncoex_core_ble_conn_dyn_prio_get = 0x40001fcc;\ncoex_core_event_duration_get = 0x40001fd0;\ncoex_core_pti_get = 0x40001fd4;\ncoex_core_release = 0x40001fd8;\ncoex_core_request = 0x40001fdc;\ncoex_core_status_get = 0x40001fe0;\ncoex_core_timer_idx_get = 0x40001fe4;\ncoex_event_duration_get = 0x40001fe8;\ncoex_hw_timer_disable = 0x40001fec;\ncoex_hw_timer_enable = 0x40001ff0;\ncoex_hw_timer_set = 0x40001ff4;\ncoex_schm_interval_set = 0x40001ff8;\ncoex_schm_lock = 0x40001ffc;\ncoex_schm_unlock = 0x40002000;\ncoex_status_get = 0x40002004;\ncoex_wifi_release = 0x40002008;\nesp_coex_ble_conn_dynamic_prio_get = 0x4000200c;\ncoex_hw_timer_tick_get = 0x40002010;\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdfb18;\ncoex_pti_tab_ptr = 0x3fcdfb14;\ncoex_schm_env_ptr = 0x3fcdfb10;\ncoexist_funcs = 0x3fcdfb0c;\ng_coa_funcs_p = 0x3fcdfb08;\ng_coex_param_ptr = 0x3fcdfb04;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_param_addr = 0x40002014;\nphy_get_romfuncs = 0x40002018;\nchip729_phyrom_version = 0x4000201c;\nchip729_phyrom_version_num = 0x40002020;\nrom_get_bias_ref_code = 0x40002024;\nget_rc_dout = 0x40002028;\nrc_cal = 0x4000202c;\nphy_analog_delay_cal = 0x40002030;\nRFChannelSel = 0x40002034;\nphy_change_channel = 0x40002038;\nphy_set_most_tpw = 0x4000203c;\nphy_rx_rifs_en = 0x40002040;\nphy_get_most_tpw = 0x40002044;\nesp_tx_state_out = 0x40002048;\nphy_get_adc_rand = 0x4000204c;\nphy_internal_delay = 0x40002050;\nphy_ftm_comp = 0x40002054;\nphy_11p_set = 0x40002058;\nphy_current_level_set = 0x4000205c;\nphy_bbpll_en_usb = 0x40002060;\nphy_bt_power_track = 0x40002064;\nrom_enter_critical_phy = 0x40002068;\nrom_exit_critical_phy = 0x4000206c;\nrom_bb_bss_cbw40 = 0x40002070;\nrom_set_chan_reg = 0x40002074;\nabs_temp = 0x40002078;\nset_chan_cal_interp = 0x4000207c;\nloopback_mode_en = 0x40002080;\nget_data_sat = 0x40002084;\nphy_byte_to_word = 0x40002088;\nphy_get_rx_freq = 0x4000208c;\ni2c_master_reset = 0x40002090;\nchan14_mic_enable = 0x40002094;\nchan14_mic_cfg = 0x40002098;\nset_adc_rand = 0x4000209c;\nwr_rf_freq_mem = 0x400020a0;\nfreq_i2c_write_set = 0x400020a4;\nwrite_pll_cap_mem = 0x400020a8;\nget_rf_freq_cap = 0x400020ac;\nget_rf_freq_init = 0x400020b0;\nfreq_get_i2c_data = 0x400020b4;\nfreq_i2c_data_write = 0x400020b8;\nset_chan_freq_hw_init = 0x400020bc;\nphy_en_hw_set_freq = 0x400020c0;\nphy_dis_hw_set_freq = 0x400020c4;\nregister_chipv7_phy_init_param = 0x400020c8;\nphy_reg_init = 0x400020cc;\nphy_xpd_rf = 0x400020d0;\nphy_close_rf = 0x400020d4;\nrf_cal_data_recovery = 0x400020d8;\nrf_cal_data_backup = 0x400020dc;\nphy_rfcal_data_check = 0x400020e0;\nrom_pwdet_sar2_init = 0x400020e4;\nrom_en_pwdet = 0x400020e8;\nrom_get_sar_sig_ref = 0x400020ec;\nrom_pwdet_tone_start = 0x400020f0;\nrom_get_tone_sar_dout = 0x400020f4;\nrom_get_fm_sar_dout = 0x400020f8;\nrom_txtone_linear_pwr = 0x400020fc;\nrom_get_power_db = 0x40002100;\nrom_meas_tone_pwr_db = 0x40002104;\nrom_pkdet_vol_start = 0x40002108;\nrom_read_sar_dout = 0x4000210c;\nrom_read_sar2_code = 0x40002110;\nrom_get_sar2_vol = 0x40002114;\nrom_get_pll_vol = 0x40002118;\nrom_tx_pwctrl_bg_init = 0x4000211c;\nrom_phy_pwdet_always_en = 0x40002120;\nrom_phy_pwdet_onetime_en = 0x40002124;\nlinear_to_db = 0x40002128;\nrom_get_pll_ref_code = 0x4000212c;\nmhz2ieee = 0x40002130;\nchan_to_freq = 0x40002134;\nrestart_cal = 0x40002138;\nwrite_rfpll_sdm = 0x4000213c;\nwait_rfpll_cal_end = 0x40002140;\nrfpll_set_freq = 0x40002144;\nset_rf_freq_offset = 0x40002148;\nset_channel_rfpll_freq = 0x4000214c;\nset_rfpll_freq = 0x40002150;\nphy_set_freq = 0x40002154;\ncorrect_rfpll_offset = 0x40002158;\nset_chan_freq_sw_start = 0x4000215c;\npll_vol_cal = 0x40002160;\nwrite_pll_cap = 0x40002164;\nread_pll_cap = 0x40002168;\nchip_v7_set_chan_misc = 0x4000216c;\nchip_v7_set_chan = 0x40002170;\nchip_v7_set_chan_offset = 0x40002174;\nchip_v7_set_chan_ana = 0x40002178;\nset_chanfreq = 0x4000217c;\ngen_rx_gain_table = 0x40002180;\nwr_rx_gain_mem = 0x40002184;\nset_rx_gain_param = 0x40002188;\nset_rx_gain_table = 0x4000218c;\nbt_track_pll_cap = 0x40002190;\nwifi_track_pll_cap = 0x40002194;\nphy_param_track = 0x40002198;\ntxpwr_correct = 0x4000219c;\ntxpwr_cal_track = 0x400021a0;\ntx_pwctrl_background = 0x400021a4;\nbt_track_tx_power = 0x400021a8;\nwifi_track_tx_power = 0x400021ac;\nbt_txdc_cal = 0x400021b0;\nbt_txiq_cal = 0x400021b4;\ntxiq_cal_init = 0x400021b8;\nget_txcap_data = 0x400021bc;\ntxdc_cal_init = 0x400021c0;\ntxdc_cal_v70 = 0x400021c4;\ntxiq_get_mis_pwr = 0x400021c8;\ntxiq_cover = 0x400021cc;\nrfcal_txiq = 0x400021d0;\nget_power_atten = 0x400021d4;\npwdet_ref_code = 0x400021d8;\npwdet_code_cal = 0x400021dc;\nrfcal_txcap = 0x400021e0;\ntx_cap_init = 0x400021e4;\nrfcal_pwrctrl = 0x400021e8;\ntx_pwctrl_init_cal = 0x400021ec;\ntx_pwctrl_init = 0x400021f0;\nbt_tx_pwctrl_init = 0x400021f4;\nbt_txpwr_freq = 0x400021f8;\nrom_get_i2c_read_mask = 0x400021fc;\nrom_get_i2c_mst0_mask = 0x40002200;\nrom_get_i2c_hostid = 0x40002204;\nrom_chip_i2c_readReg_org = 0x40002208;\nrom_chip_i2c_readReg = 0x4000220c;\nrom_i2c_paral_set_mst0 = 0x40002210;\nrom_i2c_paral_set_read = 0x40002214;\nrom_i2c_paral_read = 0x40002218;\nrom_i2c_paral_write = 0x4000221c;\nrom_i2c_paral_write_num = 0x40002220;\nrom_i2c_paral_write_mask = 0x40002224;\nrom_i2c_readReg = 0x40002228;\nrom_chip_i2c_writeReg = 0x4000222c;\nrom_i2c_writeReg = 0x40002230;\nrom_i2c_readReg_Mask = 0x40002234;\nrom_i2c_writeReg_Mask = 0x40002238;\nrom_set_txcap_reg = 0x4000223c;\ni2c_sar2_init_code = 0x40002240;\nphy_i2c_init1 = 0x40002244;\nphy_i2c_init2 = 0x40002248;\nphy_get_i2c_data = 0x4000224c;\nbias_reg_set = 0x40002250;\ni2c_bbpll_set = 0x40002254;\nrom_pbus_force_mode = 0x40002258;\nrom_pbus_rd_addr = 0x4000225c;\nrom_pbus_rd_shift = 0x40002260;\nrom_pbus_force_test = 0x40002264;\nrom_pbus_rd = 0x40002268;\nrom_pbus_debugmode = 0x4000226c;\nrom_pbus_workmode = 0x40002270;\nrom_pbus_set_rxgain = 0x40002274;\nrom_pbus_xpd_rx_off = 0x40002278;\nrom_pbus_xpd_rx_on = 0x4000227c;\nrom_pbus_xpd_tx_off = 0x40002280;\nrom_pbus_xpd_tx_on = 0x40002284;\nrom_pbus_set_dco = 0x40002288;\nrom_set_loopback_gain = 0x4000228c;\nrom_txcal_debuge_mode = 0x40002290;\nrom_txcal_work_mode = 0x40002294;\nset_pbus_mem = 0x40002298;\nrom_disable_agc = 0x4000229c;\nrom_enable_agc = 0x400022a0;\nrom_disable_wifi_agc = 0x400022a4;\nrom_enable_wifi_agc = 0x400022a8;\nrom_write_gain_mem = 0x400022ac;\nrom_bb_bss_cbw40_dig = 0x400022b0;\nrom_cbw2040_cfg = 0x400022b4;\nrom_mac_tx_chan_offset = 0x400022b8;\nrom_tx_paon_set = 0x400022bc;\nrom_i2cmst_reg_init = 0x400022c0;\nrom_bt_gain_offset = 0x400022c4;\nrom_fe_reg_init = 0x400022c8;\nrom_mac_enable_bb = 0x400022cc;\nrom_bb_wdg_cfg = 0x400022d0;\nrom_fe_txrx_reset = 0x400022d4;\nrom_set_rx_comp = 0x400022d8;\nrom_write_chan_freq = 0x400022dc;\nrom_agc_reg_init = 0x400022e0;\nrom_bb_reg_init = 0x400022e4;\nrom_write_txrate_power_offset = 0x400022e8;\nrom_open_i2c_xpd = 0x400022ec;\nphy_disable_cca = 0x400022f0;\nphy_enable_cca = 0x400022f4;\nforce_txon = 0x400022f8;\ntxiq_set_reg = 0x400022fc;\nrxiq_set_reg = 0x40002300;\nrx_gain_force = 0x40002304;\nset_txclk_en = 0x40002308;\nset_rxclk_en = 0x4000230c;\nstart_tx_tone_step = 0x40002310;\nstop_tx_tone = 0x40002314;\nbb_wdg_test_en = 0x40002318;\nnoise_floor_auto_set = 0x4000231c;\nread_hw_noisefloor = 0x40002320;\nset_cca = 0x40002324;\nset_rx_sense = 0x40002328;\nphy_rx11blr_cfg = 0x4000232c;\nbb_wdt_rst_enable = 0x40002330;\nbb_wdt_int_enable = 0x40002334;\nbb_wdt_timeout_clear = 0x40002338;\nbb_wdt_get_status = 0x4000233c;\nwifi_rifs_mode_en = 0x40002340;\nphy_chan_filt_set = 0x40002344;\niq_corr_enable = 0x40002348;\nbt_tx_dig_gain = 0x4000234c;\nwifi_tx_dig_reg = 0x40002350;\nwifi_agc_sat_gain = 0x40002354;\nphy_bbpll_cal = 0x40002358;\nphy_xpd_tsens = 0x4000235c;\nphy_freq_mem_backup = 0x40002360;\nphy_ant_init = 0x40002364;\nphy_set_bbfreq_init = 0x40002368;\nwifi_fbw_sel = 0x4000236c;\nphy_rx_sense_set = 0x40002370;\nant_dft_cfg = 0x40002374;\nant_wifitx_cfg = 0x40002378;\nant_wifirx_cfg = 0x4000237c;\nant_bttx_cfg = 0x40002380;\ntx_state_set = 0x40002384;\nphy_chan_dump_cfg = 0x40002388;\nphy_enable_low_rate = 0x4000238c;\nphy_disable_low_rate = 0x40002390;\nphy_close_pa = 0x40002394;\nbt_filter_reg = 0x40002398;\nphy_freq_correct = 0x4000239c;\nset_pbus_reg = 0x400023a0;\nphy_dig_reg_backup = 0x400023a4;\niq_est_enable = 0x400023a8;\niq_est_disable = 0x400023ac;\ndc_iq_est = 0x400023b0;\nset_cal_rxdc = 0x400023b4;\nrxiq_get_mis = 0x400023b8;\nrxiq_cover_mg_mp = 0x400023bc;\nrfcal_rxiq = 0x400023c0;\nget_rfcal_rxiq_data = 0x400023c4;\npbus_rx_dco_cal = 0x400023c8;\nrxdc_est_min = 0x400023cc;\npbus_rx_dco_cal_1step = 0x400023d0;\nset_rx_gain_cal_iq = 0x400023d4;\nset_rx_gain_cal_dc = 0x400023d8;\nspur_reg_write_one_tone = 0x400023dc;\nspur_cal = 0x400023e0;\nspur_coef_cfg = 0x400023e4;\nrom_tester_wifi_cali = 0x400023e8;\nesp_recover_efuse_data = 0x400023ec;\nrom_temp_to_power = 0x400023f0;\ntsens_read_init = 0x400023f4;\ncode_to_temp = 0x400023f8;\ntsens_index_to_dac = 0x400023fc;\ntsens_index_to_offset = 0x40002400;\ntsens_dac_cal = 0x40002404;\ntsens_code_read = 0x40002408;\ntsens_temp_read = 0x4000240c;\nget_temp_init = 0x40002410;\nrom_txbbgain_to_index = 0x40002414;\nrom_index_to_txbbgain = 0x40002418;\nrom_bt_index_to_bb = 0x4000241c;\nrom_bt_bb_to_index = 0x40002420;\nrom_bt_get_tx_gain = 0x40002424;\nrom_get_tx_gain_value = 0x40002428;\nrom_wifi_get_tx_gain = 0x4000242c;\nrom_set_tx_gain_mem = 0x40002430;\nrom_get_rate_fcc_index = 0x40002434;\nrom_get_chan_target_power = 0x40002438;\nrom_wifi_tx_dig_gain = 0x4000243c;\nrom_wifi_set_tx_gain = 0x40002440;\nrom_bt_set_tx_gain = 0x40002444;\nwifi_11g_rate_chg = 0x40002448;\nbt_chan_pwr_interp = 0x4000244c;\nbt_tx_gain_init = 0x40002450;\n\/* Data (.data, .bss, .rodata) *\/\nphy_param_rom = 0x3fcdfb00;\n\n\n\/***************************************\n Group rom_btbb\n ***************************************\/\n\n\/* Functions *\/\nbt_agc_gain_offset = 0x40002454;\nbt_agc_gain_max = 0x40002458;\nbt_set_rx_comp = 0x4000245c;\nbt_agc_gain_set = 0x40002460;\nbt_agc_rssi_thresh = 0x40002464;\nbt_agc_target_set = 0x40002468;\nbt_agc_restart_set = 0x4000246c;\nbt_agc_recorrect_set = 0x40002470;\nbt_agc_detect_set = 0x40002474;\nbt_bb_rx_correlator_set = 0x40002478;\nbt_bb_rx_dpo_set = 0x4000247c;\nbt_bb_rx_filter_sel = 0x40002480;\nbt_bb_rx_set1 = 0x40002484;\nbt_bb_v2_rx_set = 0x40002488;\nbt_bb_v2_tx_set = 0x4000248c;\nbt_bb_tx_cca_period = 0x40002490;\nbt_bb_tx_cca_fifo_reset = 0x40002494;\nbt_bb_tx_cca_fifo_empty = 0x40002498;\nbt_bb_tx_cca_fifo_full = 0x4000249c;\nbt_bb_tx_cca_fifo_count = 0x400024a0;\nbt_bb_tx_cca_fifo_read = 0x400024a4;\ncoex_pti_v2 = 0x400024a8;\nbt_bb_set_le_tx_on_delay = 0x400024ac;\nbt_bb_set_corr_thresh_le = 0x400024b0;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a31d07ba259e7aa9ba96d42ece064d4e7a689928","subject":"move rodata segment of libphy.a to dram","message":"move rodata segment of libphy.a to dram\n\n1. rodata segment of libphy.a(about 1200B) can be accessed by ISRs, so put it into DRAM\n","repos":"armada-ai\/esp-idf,Hermiedapwdrman\/esp-idf,www220\/esp-idf,Hermiedapwdrman\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,www220\/esp-idf,Hermiedapwdrman\/esp-idf,mashaoze\/esp-idf,Hermiedapwdrman\/esp-idf,Hermiedapwdrman\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf,espressif\/esp-idf,www220\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap.o(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap_poisoning.o(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libapp_trace.a:(.literal .text .literal.* .text.*)\n    *libxtensa-debug-module.a:eri.o(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap.o(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap_poisoning.o(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libapp_trace.a:(.literal .text .literal.* .text.*)\n    *libxtensa-debug-module.a:eri.o(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6e66d22055c9d2ee77ab371b3482fffeeba29d24","subject":"don't place CCM init data into flash","message":"don't place CCM init data into flash\n","repos":"madcowswe\/ODriveFirmware,madcowswe\/ODrive,madcowswe\/ODrive,madcowswe\/ODriveFirmware,madcowswe\/ODrive,madcowswe\/ODriveFirmware,madcowswe\/ODriveFirmware,madcowswe\/ODrive,madcowswe\/ODrive","old_file":"Firmware\/Board\/v3\/STM32F405RGTx_FLASH.ld","new_file":"Firmware\/Board\/v3\/STM32F405RGTx_FLASH.ld","new_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F405RGTx Device with\n**                1024KByte FLASH, 128KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Ac6.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Ac6 permit registered System Workbench for MCU users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the System Workbench for MCU toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20020000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x3C00;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x800; \/* required amount of stack *\/\n_heap_end_max = _estack - _Min_Stack_Size;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\nCCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 768K\nNVM (r)         : ORIGIN = 0x80C0000, LENGTH = 256K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  _siccmram = LOADADDR(.ccmram);\n\n  \/* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section,\n  * the startup code needs to be modified to copy the init-values.  \n  *\/\n  .ccmram :\n  {\n    . = ALIGN(4);\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\n  } >CCMRAM \/*AT> FLASH*\/\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","old_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F405RGTx Device with\n**                1024KByte FLASH, 128KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Ac6.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Ac6 permit registered System Workbench for MCU users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the System Workbench for MCU toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20020000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x3C00;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x800; \/* required amount of stack *\/\n_heap_end_max = _estack - _Min_Stack_Size;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\nCCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 768K\nNVM (r)         : ORIGIN = 0x80C0000, LENGTH = 256K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  _siccmram = LOADADDR(.ccmram);\n\n  \/* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section,\n  * the startup code needs to be modified to copy the init-values.  \n  *\/\n  .ccmram :\n  {\n    . = ALIGN(4);\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\n  } >CCMRAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5bca32442c97833a560ef6d51bb2821936e75c09","subject":"ld: stm32f401: fix typo unwinding table","message":"ld: stm32f401: fix typo unwinding table\n","repos":"raphui\/rnk,raphui\/rnk,raphui\/rnk,raphui\/rnk","old_file":"stm32_401.ld","new_file":"stm32_401.ld","new_contents":"MEMORY\n{\n    sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 96K\n    flash (RX) : ORIGIN = 0x08000000, LENGTH = 512K\n}\n\nSECTIONS\n{  \n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        PROVIDE(stext = .);\n        KEEP(*(.isr_vector))\n        *(.text .text.*)        \n        *(.rodata .rodata.*)        \n        *(.gnu.linkonce.t.*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.r.*)\n        . = ALIGN(4);\n        _etext = .;\n\t\t_sidata = _etext;\n        PROVIDE(etext = .);   \n     \t\t_fini = . ;\n\t\t\t\t*(.fini)\n\n    } >flash\n\n    .data : AT (_etext)\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.ramfunc .ramfunc.* .fastrun .fastrun.*)\n        *(.data .data.*)\n        *(.gnu.linkonce.d.*)\n        . = ALIGN(4);\n        _edata = .;\n    } >flash\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > flash\n \n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > flash\n    __exidx_end = .;\n\n    PROVIDE( flash_used_size = SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.ARM.extab) + SIZEOF(.ARM.exidx) );\n\t\t\n    .bss (NOLOAD) : {\n\t\t. = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n        *(.bss .bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN(4);        \n        _ebss = .;\n    } >sram\n    \n    end = .;\n    PROVIDE( _estack = 0x20017000 );\n}\n\n","old_contents":"MEMORY\n{\n    sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 96K\n    flash (RX) : ORIGIN = 0x08000000, LENGTH = 512K\n}\n\nSECTIONS\n{  \n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        PROVIDE(stext = .);\n        KEEP(*(.isr_vector))\n        *(.text .text.*)        \n        *(.rodata .rodata.*)        \n        *(.gnu.linkonce.t.*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.r.*)\n        . = ALIGN(4);\n        _etext = .;\n\t\t_sidata = _etext;\n        PROVIDE(etext = .);   \n     \t\t_fini = . ;\n\t\t\t\t*(.fini)\n\n    } >flash\n\n    .data : AT (_etext)\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.ramfunc .ramfunc.* .fastrun .fastrun.*)\n        *(.data .data.*)\n        *(.gnu.linkonce.d.*)\n        . = ALIGN(4);\n        _edata = .;\n    } >flash\n\t\t\n    .ARM.extab : AT (_edata)\n    {\n        *(.ARM.extab*)\n    } >flash\n\t\n    .ARM.exidx :\n    {\n        __exidx_start = .;\n\t*(.ARM.exidx*)\n\t__exidx_end = .;\n    } >flash\n\n    PROVIDE( flash_used_size = SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.ARM.extab) + SIZEOF(.ARM.exidx) );\n\t\t\n    .bss (NOLOAD) : {\n\t\t. = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n        *(.bss .bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN(4);        \n        _ebss = .;\n    } >sram\n    \n    end = .;\n    PROVIDE( _estack = 0x20017000 );\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"66532fd56702b6bb6aadcb37dd121bbdf4936f4f","subject":"don't need entry _start","message":"don't need entry _start\n","repos":"bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki,muffinator\/libmc1322x,arurke\/contiki,bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki,muffinator\/libmc1322x,bluerover\/6lbr,malvira\/libmc1322x,MohamedSeliem\/contiki,malvira\/libmc1322x,MohamedSeliem\/contiki,arurke\/contiki,bluerover\/6lbr","old_file":"mc1322x.lds","new_file":"mc1322x.lds","new_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(\"=\/usr\/local\/lib\"); SEARCH_DIR(\"=\/lib\"); SEARCH_DIR(\"=\/usr\/lib\");\nSECTIONS\n{\n\nSYS_STACK_SIZE = 1024;\nIRQ_STACK_SIZE = 256;\nFIQ_STACK_SIZE = 256;\nSVC_STACK_SIZE = 256;\nABT_STACK_SIZE = 16;\nUND_STACK_SIZE = 16;\nHEAP_SIZE = 1024;\n\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x00400000); . = 0x00400000;\n  .text           :\n  {\n    *start.o\t(.text)\n    *(.irq)\t\t\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  } =0\n\n\t.stack : {\n\t\t__stack_start__ = . ;\n\n\t\t. += IRQ_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__irq_stack_top__ = . ;\n\n\t\t. += FIQ_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__fiq_stack_top__ = . ;\n\n\t\t. += SVC_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__svc_stack_top__ = . ;\n\n\t\t. += ABT_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__abt_stack_top__ = . ;\n\n\t\t. += UND_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__und_stack_top__ = . ;\n\n\t\t. += SYS_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__sys_stack_top__ = . ;\n\n\t\t__stack_end__ = .;\n\t}\t\n\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n      *(.rela.ctors)\n      *(.rela.dtors)\n      *(.rela.got)\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n    }\n  .rel.plt        : { *(.rel.plt) }\n  .rela.plt       : { *(.rela.plt) }\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0\n  .plt            : { *(.plt) }\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n\n\/*  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); *\/\n\n\t. = ALIGN(4);\n\t. = DATA_SEGMENT_ALIGN(4,4); \n\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n  .init_array     :\n  {\n     PROVIDE_HIDDEN (__init_array_start = .);\n     KEEP (*(SORT(.init_array.*)))\n     KEEP (*(.init_array))\n     PROVIDE_HIDDEN (__init_array_end = .);\n  }\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .jcr            : { KEEP (*(.jcr)) } \n  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }\n  .dynamic        : { *(.dynamic) } \n  . = DATA_SEGMENT_RELRO_END (0, .);  \n  .got            : { *(.got.plt) *(.got) }\n  .data           :\n  {\n    __data_start = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .data1          : { *(.data1) }\n  _edata = .; PROVIDE (edata = .);\n  __bss_start = .;\n  __bss_start__ = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.\n      FIXME: Why do we need it? When there is no .bss section, we don't\n      pad the .data section.  *\/\n   . = ALIGN(. != 0 ? 32 \/ 8 : 1);\n  }\n  _bss_end__ = . ; __bss_end__ = . ;\n  . = ALIGN(32 \/ 8);\n\n   .heap : {\n                __heap_start__ = . ;\n                *(.heap);\n                . += HEAP_SIZE;\n                . = ALIGN (4);\n                __heap_end__ = . ;\n   }\n\n\n  . = ALIGN(32 \/ 8);\n  __end__ = . ;\n  _end = .; PROVIDE (end = .);\n  . = DATA_SEGMENT_END (.);\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","old_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSEARCH_DIR(\"=\/usr\/local\/lib\"); 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Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  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{"commit":"034b5213a656bd887dd220d2b28d07fb5a193c30","subject":"more ram for S140","message":"more ram for S140\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52840\/src\/s140_nrf52840_xxaa.ld","new_file":"ARM\/Nordic\/nRF52840\/src\/s140_nrf52840_xxaa.ld","new_contents":"\/* Linker script to configure memory regions. *\/\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\t\/* nRF52840 has 1MB Flash (0x100000), 256KB RAM (0x40000) *\/\r\n\t\r\n\tFLASH (rx) : ORIGIN = 0x27000, LENGTH = 0xd9000\r\n\tRAM (rwx) :  ORIGIN = 0x20003300, LENGTH = 0x3CD00\r\n\r\n\t\/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n\t*  from application to bootloader when using buttonless DFU OTA.\r\n\t*\/\r\n\tNOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n\t\/** Location of bootloader setting in flash. *\/\r\n\tBOOTLOADER_SETTINGS (rw) : ORIGIN = 0x000FF000, LENGTH = 0x1000\r\n}\r\n\r\n\r\nSECTIONS\r\n{\r\n\t\/* Place the bootloader settings page in flash. *\/\r\n\t.bootloaderSettings(NOLOAD) :\r\n\t{\r\n\r\n\t} > BOOTLOADER_SETTINGS\r\n\r\n\t\/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n\t.noinit(NOLOAD) :\r\n\t{\r\n\r\n\t} > NOINIT\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.pwr_mgmt_data :\r\n\t{\r\n\t\tPROVIDE(__start_pwr_mgmt_data = .);\r\n\t\tKEEP(*(SORT(.pwr_mgmt_data*)))\r\n\t\tPROVIDE(__stop_pwr_mgmt_data = .);\r\n\t} > FLASH\r\n\t\r\n\t.log_const_data :\r\n\t{\r\n\t  \tPROVIDE(__start_log_const_data = .);\r\n\t  \tKEEP(*(.log_const_data))\r\n\t  \tPROVIDE(__stop_log_const_data = .);\r\n\t} > FLASH\r\n\t\r\n    .crypto_data :\r\n    {\r\n        PROVIDE(__start_crypto_data = .);\r\n        KEEP(*(SORT(.crypto_data*)))\r\n        PROVIDE(__stop_crypto_data = .);\r\n    } > FLASH\r\n\t\r\n\t.cli_command :\r\n\t{\r\n\t\tPROVIDE(__start_cli_command = .);\r\n\t\tKEEP(*(.cli_command))\r\n\t\tPROVIDE(__stop_cli_command = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_stack_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_stack_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_stack_observers*)))\r\n\t\tPROVIDE(__stop_sdh_stack_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_req_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_req_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_req_observers*)))\r\n\t\tPROVIDE(__stop_sdh_req_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_state_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_state_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_state_observers*)))\r\n\t\tPROVIDE(__stop_sdh_state_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_ant_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_ant_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_ant_observers*)))\r\n\t\tPROVIDE(__stop_sdh_ant_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_ble_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_ble_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_ble_observers*)))\r\n\t\tPROVIDE(__stop_sdh_ble_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_soc_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_soc_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_soc_observers*)))\r\n\t\tPROVIDE(__stop_sdh_soc_observers = .);\r\n\t} > FLASH\r\n    .nrf_queue :\r\n  {\r\n    PROVIDE(__start_nrf_queue = .);\r\n    KEEP(*(.nrf_queue))\r\n    PROVIDE(__stop_nrf_queue = .);\r\n  } > FLASH\r\n} INSERT AFTER .text\r\n\r\nSECTIONS\r\n{\r\n\t. = ALIGN(4);\r\n\t.svc_data :\r\n\t{\r\n\t\tPROVIDE(__start_svc_data = .);\r\n\t\tKEEP(*(.svc_data))\r\n\t\tPROVIDE(__stop_svc_data = .);\r\n\t} > RAM AT > FLASH\r\n\t\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n\t\r\n\t.log_dynamic_data :\r\n\t{\r\n\t\tPROVIDE(__start_log_dynamic_data = .);\r\n\t\tKEEP(*(.log_dynamic_data))\r\n\t\tPROVIDE(__stop_log_dynamic_data = .);\r\n\t} > RAM AT > FLASH\r\n\t.cli_sorted_cmd_ptrs :\r\n\t{\r\n\t\tPROVIDE(__start_cli_sorted_cmd_ptrs = .);\r\n\t\tKEEP(*(.cli_sorted_cmd_ptrs))\r\n\t\tPROVIDE(__stop_cli_sorted_cmd_ptrs = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"\r\n","old_contents":"\/* Linker script to configure memory regions. *\/\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52840\/CMSIS\/Release\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\t\/* nRF52840 has 1MB Flash (0x100000), 256KB RAM (0x40000) *\/\r\n\t\r\n\tFLASH (rx) : ORIGIN = 0x27000, LENGTH = 0xd9000\r\n\tRAM (rwx) :  ORIGIN = 0x20002900, LENGTH = 0x3d700\r\n\r\n\t\/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n\t*  from application to bootloader when using buttonless DFU OTA.\r\n\t*\/\r\n\tNOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n\t\/** Location of bootloader setting in flash. *\/\r\n\tBOOTLOADER_SETTINGS (rw) : ORIGIN = 0x000FF000, LENGTH = 0x1000\r\n}\r\n\r\n\r\nSECTIONS\r\n{\r\n\t\/* Place the bootloader settings page in flash. *\/\r\n\t.bootloaderSettings(NOLOAD) :\r\n\t{\r\n\r\n\t} > BOOTLOADER_SETTINGS\r\n\r\n\t\/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n\t.noinit(NOLOAD) :\r\n\t{\r\n\r\n\t} > NOINIT\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.pwr_mgmt_data :\r\n\t{\r\n\t\tPROVIDE(__start_pwr_mgmt_data = .);\r\n\t\tKEEP(*(SORT(.pwr_mgmt_data*)))\r\n\t\tPROVIDE(__stop_pwr_mgmt_data = .);\r\n\t} > FLASH\r\n\t\r\n\t.log_const_data :\r\n\t{\r\n\t  \tPROVIDE(__start_log_const_data = .);\r\n\t  \tKEEP(*(.log_const_data))\r\n\t  \tPROVIDE(__stop_log_const_data = .);\r\n\t} > FLASH\r\n\t\r\n    .crypto_data :\r\n    {\r\n        PROVIDE(__start_crypto_data = .);\r\n        KEEP(*(SORT(.crypto_data*)))\r\n        PROVIDE(__stop_crypto_data = .);\r\n    } > FLASH\r\n\t\r\n\t.cli_command :\r\n\t{\r\n\t\tPROVIDE(__start_cli_command = .);\r\n\t\tKEEP(*(.cli_command))\r\n\t\tPROVIDE(__stop_cli_command = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_stack_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_stack_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_stack_observers*)))\r\n\t\tPROVIDE(__stop_sdh_stack_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_req_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_req_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_req_observers*)))\r\n\t\tPROVIDE(__stop_sdh_req_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_state_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_state_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_state_observers*)))\r\n\t\tPROVIDE(__stop_sdh_state_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_ant_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_ant_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_ant_observers*)))\r\n\t\tPROVIDE(__stop_sdh_ant_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_ble_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_ble_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_ble_observers*)))\r\n\t\tPROVIDE(__stop_sdh_ble_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_soc_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_soc_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_soc_observers*)))\r\n\t\tPROVIDE(__stop_sdh_soc_observers = .);\r\n\t} > FLASH\r\n    .nrf_queue :\r\n  {\r\n    PROVIDE(__start_nrf_queue = .);\r\n    KEEP(*(.nrf_queue))\r\n    PROVIDE(__stop_nrf_queue = .);\r\n  } > FLASH\r\n} INSERT AFTER .text\r\n\r\nSECTIONS\r\n{\r\n\t. = ALIGN(4);\r\n\t.svc_data :\r\n\t{\r\n\t\tPROVIDE(__start_svc_data = .);\r\n\t\tKEEP(*(.svc_data))\r\n\t\tPROVIDE(__stop_svc_data = .);\r\n\t} > RAM AT > FLASH\r\n\t\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n\t\r\n\t.log_dynamic_data :\r\n\t{\r\n\t\tPROVIDE(__start_log_dynamic_data = .);\r\n\t\tKEEP(*(.log_dynamic_data))\r\n\t\tPROVIDE(__stop_log_dynamic_data = .);\r\n\t} > RAM AT > FLASH\r\n\t.cli_sorted_cmd_ptrs :\r\n\t{\r\n\t\tPROVIDE(__start_cli_sorted_cmd_ptrs = .);\r\n\t\tKEEP(*(.cli_sorted_cmd_ptrs))\r\n\t\tPROVIDE(__stop_cli_sorted_cmd_ptrs = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"5aa6b80b64365842496460f36f3894ef31fa9eae","subject":"layout.ld: Introduce `.stack` section","message":"layout.ld: Introduce `.stack` section\n\nRemove `STACK_SIZE` from `.data` section (as its generating improper\nrelocations) and introduce a seperate `.stack` section.\n\nTell the linker that in `FLASH` region, `.data` section is starting at\n`_etext`.\n\nSigned-off-by: Rajiv Ranganath <4acda8d1ee7b6cc93e786e53408b868c7be3fe76@atihita.com>\n","repos":"tock\/libtock-rs","old_file":"layout.ld","new_file":"layout.ld","new_contents":"\/* Userland Generic Layout\n *\n * Currently, due to incomplete ROPI-RWPI support in rustc (see\n * https:\/\/github.com\/tock\/libtock-rs\/issues\/28), this layout implements static\n * linking. An application init script must define the FLASH and SRAM address\n * ranges as well as MPU_MIN_ALIGN before including this layout file.\n *\n * Here is a an example application linker script to get started:\n *     MEMORY {\n *         \/* FLASH memory region must start immediately *after* the Tock\n *          * Binary Format headers, which means you need to offset the\n *          * beginning of FLASH memory region relative to where the\n *          * application is loaded.\n *         FLASH (rx) : ORIGIN = 0x10030, LENGTH = 0x0FFD0\n *         SRAM (RWX) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     STACK_SIZE = 2048;\n *     MPU_MIN_ALIGN = 8K;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n        \/* Pad the header out to a multiple of 32 bytes so there is not a gap\n         * between the header and subsequent .data section. It's unclear why,\n         * but LLD is aligning sections to a multiple of 32 bytes. *\/\n        . = ALIGN(32);\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _etext = .;\n    } > FLASH =0xFF\n\n    \/* Application stack *\/\n    .stack :\n    {\n        . = . + STACK_SIZE;\n\n\t_stack_top_unaligned = .;\n        . = ALIGN(8);\n\t_stack_top_aligned = .;\n    } > SRAM\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data : AT (_etext)\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT((_stack_top_aligned - _stack_top_unaligned) == 0, \"\nSTACK_SIZE must be 8 byte multiple\")\n","old_contents":"\/* Userland Generic Layout\n *\n * Currently, due to incomplete ROPI-RWPI support in rustc (see\n * https:\/\/github.com\/tock\/libtock-rs\/issues\/28), this layout implements static\n * linking. An application init script must define the FLASH and SRAM address\n * ranges as well as MPU_MIN_ALIGN before including this layout file.\n *\n * Here is a an example application linker script to get started:\n *     MEMORY {\n *         \/* FLASH memory region must start immediately *after* the Tock\n *          * Binary Format headers, which means you need to offset the\n *          * beginning of FLASH memory region relative to where the\n *          * application is loaded.\n *         FLASH (rx) : ORIGIN = 0x10030, LENGTH = 0x0FFD0\n *         SRAM (RWX) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     MPU_MIN_ALIGN = 8K;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\/\n\nSTACK_SIZE = 2048;\n\nENTRY(_start)\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n        \/* Pad the header out to a multiple of 32 bytes so there is not a gap\n         * between the header and subsequent .data section. It's unclear why,\n         * but LLD is aligning sections to a multiple of 32 bytes. *\/\n        . = ALIGN(32);\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        \/* Account for MPU alignment and the stack *\/\n        . = ALIGN(MPU_MIN_ALIGN);\n        . = . + STACK_SIZE;\n        . = ALIGN(8); \/* The stack is aligned to a multiple of 8 bytes. *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"24ece752a5261985ea3298e1ac655d9666c69f89","subject":"[EFR32] Loader script: Flash length fixed. (#21884)","message":"[EFR32] Loader script: Flash length fixed. (#21884)\n\n","repos":"project-chip\/connectedhomeip,project-chip\/connectedhomeip,project-chip\/connectedhomeip,project-chip\/connectedhomeip,project-chip\/connectedhomeip,project-chip\/connectedhomeip","old_file":"examples\/platform\/efr32\/ldscripts\/efr32mg24.ld","new_file":"examples\/platform\/efr32\/ldscripts\/efr32mg24.ld","new_contents":"\/*\n *\n *    Copyright (c) 2021 Project CHIP Authors\n *    All rights reserved.\n *\n *    Licensed under the Apache License, Version 2.0 (the \"License\");\n *    you may not use this file except in compliance with the License.\n *    You may obtain a copy of the License at\n *\n *        http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n *    Unless required by applicable law or agreed to in writing, software\n *    distributed under the License is distributed on an \"AS IS\" BASIS,\n *    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n *    See the License for the specific language governing permissions and\n *    limitations under the License.\n *\/\n\/***************************************************************************\/\/**\n * @file     gcc_EFR32MG24.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n * Linker script for Silicon Labs EFR32MG24 devices\n *******************************************************************************\n * # License\n * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com <\/b>\n *******************************************************************************\n *\n * SPDX-License-Identifier: Zlib\n * \n * The licensor of this software is Silicon Laboratories Inc.\n * \n * This software is provided 'as-is', without any express or implied\n * warranty. In no event will the authors be held liable for any damages\n * arising from the use of this software.\n * \n * Permission is granted to anyone to use this software for any purpose,\n * including commercial applications, and to alter it and redistribute it\n * freely, subject to the following restrictions:\n * \n * 1. The origin of this software must not be misrepresented; you must not\n *    claim that you wrote the original software. If you use this software\n *    in a product, an acknowledgment in the product documentation would be\n *    appreciated but is not required.\n * 2. Altered source versions must be plainly marked as such, and must not be\n *    misrepresented as being the original software.\n * 3. This notice may not be removed or altered from any source distribution.\n *\n ******************************************************************************\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x08006000, LENGTH = 0x17A000\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x40000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n *\/\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    \/* .ctors *\/\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    \/* .dtors *\/\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) \/ 4)\n\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    __zero_table_end__ = .;\n    __etext = ALIGN(4);\n  } > FLASH\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data*)\n    . = ALIGN (4);\n    PROVIDE (__ram_func_section_start = .);\n    *(.ram)\n    PROVIDE (__ram_func_section_end = .);\n\n    . = ALIGN(4);\n    \/* preinit data *\/\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    \/* init data *\/\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    \/* finit data *\/\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    \/* All data end *\/\n    __data_end__ = .;\n\n  } > RAM\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  .heap (COPY):\n  {\n    __HeapBase = .;\n    __end__ = .;\n    end = __end__;\n    _end = __end__;\n    KEEP(*(.heap*))\n    __HeapLimit = .;\n  } > RAM\n\n  __main_flash_end__ = ORIGIN(FLASH) + LENGTH(FLASH);\n\n  \/* .stack_dummy section doesn't contains any symbols. It is only\n   * used for linker to calculate size of stack sections, and assign\n   * values to stack symbols later *\/\n  .stack_dummy (COPY):\n  {\n    KEEP(*(.stack*))\n \/* KEEP(*(.stackseal*))*\/\n  } > RAM\n\n  \/* Set stack top to end of RAM, and stack limit move down by\n   * size of stack_dummy section *\/\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n  PROVIDE(__stack = __StackTop);\n\n   .nvm (DSECT) : {\n    KEEP(*(.simee*))\n  } > FLASH\n\n  \/* Last page of flash is reserved for the manufacturing token space *\/\n  linker_nvm_end = __main_flash_end__ - 8192;\n  linker_nvm_begin = linker_nvm_end - SIZEOF(.nvm);\n  linker_nvm_size = SIZEOF(.nvm);\n  __nvm3Base = linker_nvm_begin;\n  __attestation_credentials_base = linker_nvm_end;\n\n  \/* Check if data + heap + stack exceeds RAM limit *\/\n  \/*ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")*\/\n  ASSERT( (linker_nvm_begin + SIZEOF(.nvm)) <= __main_flash_end__, \"NVM3 is excessing the flash size !\")\n\n  \/* Check if FLASH usage exceeds FLASH size *\/\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\n}\n","old_contents":"\/*\n *\n *    Copyright (c) 2021 Project CHIP Authors\n *    All rights reserved.\n *\n *    Licensed under the Apache License, Version 2.0 (the \"License\");\n *    you may not use this file except in compliance with the License.\n *    You may obtain a copy of the License at\n *\n *        http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n *    Unless required by applicable law or agreed to in writing, software\n *    distributed under the License is distributed on an \"AS IS\" BASIS,\n *    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n *    See the License for the specific language governing permissions and\n *    limitations under the License.\n *\/\n\/***************************************************************************\/\/**\n * @file     gcc_EFR32MG24.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n * Linker script for Silicon Labs EFR32MG24 devices\n *******************************************************************************\n * # License\n * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com <\/b>\n *******************************************************************************\n *\n * SPDX-License-Identifier: Zlib\n * \n * The licensor of this software is Silicon Laboratories Inc.\n * \n * This software is provided 'as-is', without any express or implied\n * warranty. In no event will the authors be held liable for any damages\n * arising from the use of this software.\n * \n * Permission is granted to anyone to use this software for any purpose,\n * including commercial applications, and to alter it and redistribute it\n * freely, subject to the following restrictions:\n * \n * 1. The origin of this software must not be misrepresented; you must not\n *    claim that you wrote the original software. If you use this software\n *    in a product, an acknowledgment in the product documentation would be\n *    appreciated but is not required.\n * 2. Altered source versions must be plainly marked as such, and must not be\n *    misrepresented as being the original software.\n * 3. This notice may not be removed or altered from any source distribution.\n *\n ******************************************************************************\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x08006000, LENGTH = 0x178000\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 0x40000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n *\/\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    \/* .ctors *\/\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    \/* .dtors *\/\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) \/ 4)\n\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    __zero_table_end__ = .;\n    __etext = ALIGN(4);\n  } > FLASH\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data*)\n    . = ALIGN (4);\n    PROVIDE (__ram_func_section_start = .);\n    *(.ram)\n    PROVIDE (__ram_func_section_end = .);\n\n    . = ALIGN(4);\n    \/* preinit data *\/\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    \/* init data *\/\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    \/* finit data *\/\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    \/* All data end *\/\n    __data_end__ = .;\n\n  } > RAM\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  .heap (COPY):\n  {\n    __HeapBase = .;\n    __end__ = .;\n    end = __end__;\n    _end = __end__;\n    KEEP(*(.heap*))\n    __HeapLimit = .;\n  } > RAM\n\n  __main_flash_end__ = ORIGIN(FLASH) + LENGTH(FLASH);\n\n  \/* .stack_dummy section doesn't contains any symbols. It is only\n   * used for linker to calculate size of stack sections, and assign\n   * values to stack symbols later *\/\n  .stack_dummy (COPY):\n  {\n    KEEP(*(.stack*))\n \/* KEEP(*(.stackseal*))*\/\n  } > RAM\n\n  \/* Set stack top to end of RAM, and stack limit move down by\n   * size of stack_dummy section *\/\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n  PROVIDE(__stack = __StackTop);\n\n   .nvm (DSECT) : {\n    KEEP(*(.simee*))\n  } > FLASH\n\n  \/* Last page of flash is reserved for the manufacturing token space *\/\n  linker_nvm_end = __main_flash_end__ - 8192;\n  linker_nvm_begin = linker_nvm_end - SIZEOF(.nvm);\n  linker_nvm_size = SIZEOF(.nvm);\n  __nvm3Base = linker_nvm_begin;\n  __attestation_credentials_base = linker_nvm_end;\n\n  \/* Check if data + heap + stack exceeds RAM limit *\/\n  \/*ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")*\/\n  ASSERT( (linker_nvm_begin + SIZEOF(.nvm)) <= __main_flash_end__, \"NVM3 is excessing the flash size !\")\n\n  \/* Check if FLASH usage exceeds FLASH size *\/\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"70412928decd91179c55bacc4b5155ce47f31faf","subject":"esp32: fix placement of .rtc_noinit","message":"esp32: fix placement of .rtc_noinit\n\nWhen CONFIG_ESP32_RTCDATA_IN_FAST_MEM is enabled, .rtc_noinit should\nbe in RTC_FAST memory, same as .rtc.data\n","repos":"armada-ai\/esp-idf,www220\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf,armada-ai\/esp-idf,espressif\/esp-idf,www220\/esp-idf,espressif\/esp-idf,armada-ai\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.*(.literal .text .literal.* .text.*)\n    _rtc_text_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n  \n  \/*\n    This section is required to skip rtc.text area because rtc_iram_seg and \n    rtc_data_seg are reflect the same address space on different buses.\n  *\/\n  .rtc.dummy :\n  {\n    _rtc_dummy_start = ABSOLUTE(.);\n    _rtc_fast_start = ABSOLUTE(.);\n    . = SIZEOF(.rtc.text);\n    _rtc_dummy_end = ABSOLUTE(.);\n  } > rtc_data_seg\n\n  \/* This section located in RTC FAST Memory area. \n     It holds data marked with RTC_FAST_ATTR attribute. \n     See the file \"esp_attr.h\" for more information.\n  *\/\n  .rtc.force_fast :\n  {\n    . = ALIGN(4);\n    _rtc_force_fast_start = ABSOLUTE(.);\n    *(.rtc.force_fast .rtc.force_fast.*)\n    . = ALIGN(4) ;\n    _rtc_force_fast_end = ABSOLUTE(.);\n  } > rtc_data_seg\n\n  \/* RTC data section holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c and the data marked with\n     RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.\n     The memory location of the data is dependent on \n     CONFIG_ESP32_RTCDATA_IN_FAST_MEM option.\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_data_location\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.*(.bss .bss.*)\n    *rtc_wake_stub*.*(COMMON)\n    *(.rtc.bss)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_data_location\n\n  \/* This section holds data that should not be initialized at power up \n     and will be retained during deep sleep.\n     User data marked with RTC_NOINIT_ATTR will be placed\n     into this section. See the file \"esp_attr.h\" for more information. \n\t The memory location of the data is dependent on \n     CONFIG_ESP32_RTCDATA_IN_FAST_MEM option.\n  *\/\n  .rtc_noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _rtc_noinit_start = ABSOLUTE(.);\n    *(.rtc_noinit .rtc_noinit.*)\n    . = ALIGN(4) ;\n    _rtc_noinit_end = ABSOLUTE(.);\n  } > rtc_data_location\n\n  \/* This section located in RTC SLOW Memory area. \n     It holds data marked with RTC_SLOW_ATTR attribute. \n     See the file \"esp_attr.h\" for more information.\n  *\/\n  .rtc.force_slow :\n  {\n    . = ALIGN(4);\n    _rtc_force_slow_start = ABSOLUTE(.);\n    *(.rtc.force_slow .rtc.force_slow.*)\n    . = ALIGN(4) ;\n    _rtc_force_slow_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Get size of rtc slow data based on rtc_data_location alias *\/\n  _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) \n                        ? (_rtc_force_slow_end - _rtc_data_start) \n                        : (_rtc_force_slow_end - _rtc_force_slow_start);\n\n  _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) \n                        ? (_rtc_force_fast_end - _rtc_fast_start) \n                        : (_rtc_noinit_end - _rtc_fast_start);\n  \n  ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),\n          \"RTC_SLOW segment data does not fit.\")\n          \n  ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),\n          \"RTC_FAST segment data does not fit.\")\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    _iram_start = ABSOLUTE(.);\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap.*(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap_poisoning.*(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.*(.literal .text .literal.* .text.*)\n    *libapp_trace.a:(.literal .text .literal.* .text.*)\n    *libxtensa-debug-module.a:eri.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n    _iram_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    _bt_data_start = ABSOLUTE(.);\n    *libbt.a:(.data .data.*)\n    . = ALIGN (4);\n    _bt_data_end = ABSOLUTE(.);\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.*(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.*(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.*(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.*(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } > dram0_0_seg\n\n  \/*This section holds data that should not be initialized at power up.\n    The section located in Internal SRAM memory region. The macro _NOINIT\n    can be used as attribute to place data into this section.\n    See the esp_attr.h file for more information.\n  *\/\n  .noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _noinit_start = ABSOLUTE(.);\n    *(.noinit .noinit.*) \n    . = ALIGN(4) ;\n    _noinit_end = ABSOLUTE(.);\n  } > dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    _bt_bss_start = ABSOLUTE(.);\n    *libbt.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _bt_bss_end = ABSOLUTE(.);\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    \/* The heap starts right after end of this section *\/\n    _heap_start = ABSOLUTE(.);\n  } > dram0_0_seg\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n          \n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    \/* Addresses of memory regions reserved via\n       SOC_RESERVE_MEMORY_REGION() *\/\n    soc_reserved_memory_region_start = ABSOLUTE(.);\n    KEEP (*(.reserved_memory_address))\n    soc_reserved_memory_region_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.*(.literal .text .literal.* .text.*)\n    _rtc_text_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n  \n  \/*\n    This section is required to skip rtc.text area because rtc_iram_seg and \n    rtc_data_seg are reflect the same address space on different buses.\n  *\/\n  .rtc.dummy :\n  {\n    _rtc_dummy_start = ABSOLUTE(.);\n    _rtc_fast_start = ABSOLUTE(.);\n    . = SIZEOF(.rtc.text);\n    _rtc_dummy_end = ABSOLUTE(.);\n  } > rtc_data_seg\n\n  \/* This section located in RTC FAST Memory area. \n     It holds data marked with RTC_FAST_ATTR attribute. \n     See the file \"esp_attr.h\" for more information.\n  *\/\n  .rtc.force_fast :\n  {\n    . = ALIGN(4);\n    _rtc_force_fast_start = ABSOLUTE(.);\n    *(.rtc.force_fast .rtc.force_fast.*)\n    . = ALIGN(4) ;\n    _rtc_force_fast_end = ABSOLUTE(.);\n  } > rtc_data_seg\n\n  \/* RTC data section holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c and the data marked with\n     RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.\n     The memory location of the data dependent on \n     CONFIG_ESP32_RTCDATA_IN_FAST_MEM option.\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_data_location\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.*(.bss .bss.*)\n    *rtc_wake_stub*.*(COMMON)\n    *(.rtc.bss)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_data_location\n\n  \/* This section located in RTC SLOW Memory area. \n     It holds data marked with RTC_SLOW_ATTR attribute. \n     See the file \"esp_attr.h\" for more information.\n  *\/\n  .rtc.force_slow :\n  {\n    . = ALIGN(4);\n    _rtc_force_slow_start = ABSOLUTE(.);\n    *(.rtc.force_slow .rtc.force_slow.*)\n    . = ALIGN(4) ;\n    _rtc_force_slow_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* This section holds data that should not be initialized at power up \n     and will be retained during deep sleep. The section located in \n     RTC SLOW Memory area. User data marked with RTC_NOINIT_ATTR will be placed\n     into this section. See the file \"esp_attr.h\" for more information.\n  *\/\n  .rtc_noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _rtc_noinit_start = ABSOLUTE(.);\n    *(.rtc_noinit .rtc_noinit.*)\n    . = ALIGN(4) ;\n    _rtc_noinit_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Get size of rtc slow data based on rtc_data_location alias *\/\n  _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) \n                        ? (_rtc_noinit_end - _rtc_data_start) \n                        : (_rtc_noinit_end - _rtc_force_slow_start);\n\n  _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) \n                        ? (_rtc_force_fast_end - _rtc_fast_start) \n                        : (_rtc_bss_end - _rtc_fast_start);\n  \n  ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),\n          \"RTC_SLOW segment data does not fit.\")\n          \n  ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),\n          \"RTC_FAST segment data does not fit.\")\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    _iram_start = ABSOLUTE(.);\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap.*(.literal .text .literal.* .text.*)\n    *libheap.a:multi_heap_poisoning.*(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.*(.literal .text .literal.* .text.*)\n    *libapp_trace.a:(.literal .text .literal.* .text.*)\n    *libxtensa-debug-module.a:eri.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n    _iram_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    _bt_data_start = ABSOLUTE(.);\n    *libbt.a:(.data .data.*)\n    . = ALIGN (4);\n    _bt_data_end = ABSOLUTE(.);\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.*(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.*(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.*(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.*(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } > dram0_0_seg\n\n  \/*This section holds data that should not be initialized at power up.\n    The section located in Internal SRAM memory region. The macro _NOINIT\n    can be used as attribute to place data into this section.\n    See the esp_attr.h file for more information.\n  *\/\n  .noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _noinit_start = ABSOLUTE(.);\n    *(.noinit .noinit.*) \n    . = ALIGN(4) ;\n    _noinit_end = ABSOLUTE(.);\n  } > dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    _bt_bss_start = ABSOLUTE(.);\n    *libbt.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _bt_bss_end = ABSOLUTE(.);\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    \/* The heap starts right after end of this section *\/\n    _heap_start = ABSOLUTE(.);\n  } > dram0_0_seg\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n          \n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    \/* Addresses of memory regions reserved via\n       SOC_RESERVE_MEMORY_REGION() *\/\n    soc_reserved_memory_region_start = ABSOLUTE(.);\n    KEEP (*(.reserved_memory_address))\n    soc_reserved_memory_region_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4c7bde43113f5173741cba6cef1c011739917671","subject":"x86: 32-bit: set ENTRY properly","message":"x86: 32-bit: set ENTRY properly\n\nThe entry point is at a physical memory location; use the\nphysical instead of virtual address of the start symbol.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/x86\/ia32\/linker.ld","new_file":"include\/arch\/x86\/ia32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <sys\/util.h>\n#include <sys\/mem_manage.h>\n\n#include <linker\/linker-tool.h>\n\n#if defined(CONFIG_XIP) || defined(Z_VM_KERNEL)\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_MMU\n\t#define MMU_PAGE_ALIGN\t\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN_PERM\tMMU_PAGE_ALIGN\n#else\n\t#define MMU_PAGE_ALIGN_PERM\n#endif\n\nepoint = Z_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY);\nENTRY(epoint)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n#ifdef CONFIG_XIP\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n#ifndef CONFIG_XIP\n\tz_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t\/* Needs KEEP() as ENTRY() is given a physical address *\/\n\tKEEP(*(.text_start))\n\tKEEP(*(\".text_start.*\"))\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame_hdr)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n#ifdef CONFIG_XIP\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n#endif\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n\tMMU_PAGE_ALIGN\n\tz_mapped_start = .;\n#endif\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN_PERM\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN_PERM\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN_PERM\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n#include <linker\/common-noinit.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif \/* LINKER_PASS2 *\/\n\n\tz_interrupt_vectors_allocated = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_vectors_alloc))\n#else\n\t. += (CONFIG_IDT_NUM_VECTORS + 7) \/ 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_X86_KPTI\n\tMMU_PAGE_ALIGN_PERM\n\tz_shared_kernel_page_start = .;\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. IDT, GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\/\n#endif \/* CONFIG_X86_KPTI *\/\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_KPTI\n\tz_trampoline_stack_start = .;\n\tMMU_PAGE_ALIGN_PERM\n\tz_trampoline_stack_end = .;\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_trampoline_stack_end - z_trampoline_stack_start >= 40,\n\t\t\"trampoline stack too small\");\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;\n\n\tz_mapped_end = .;\n\tz_mapped_size = z_mapped_end - z_mapped_start;\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <sys\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#if defined(CONFIG_XIP) || defined(Z_VM_KERNEL)\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_MMU\n\t#define MMU_PAGE_ALIGN\t\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN_PERM\tMMU_PAGE_ALIGN\n#else\n\t#define MMU_PAGE_ALIGN_PERM\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n#ifdef CONFIG_XIP\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n#ifndef CONFIG_XIP\n\tz_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame_hdr)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n#ifdef CONFIG_XIP\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n#endif\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n\tMMU_PAGE_ALIGN\n\tz_mapped_start = .;\n#endif\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN_PERM\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN_PERM\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN_PERM\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n#include <linker\/common-noinit.ld>\n\n\tMMU_PAGE_ALIGN_PERM\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif \/* LINKER_PASS2 *\/\n\n\tz_interrupt_vectors_allocated = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_vectors_alloc))\n#else\n\t. += (CONFIG_IDT_NUM_VECTORS + 7) \/ 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_X86_KPTI\n\tMMU_PAGE_ALIGN_PERM\n\tz_shared_kernel_page_start = .;\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. IDT, GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\/\n#endif \/* CONFIG_X86_KPTI *\/\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_KPTI\n\tz_trampoline_stack_start = .;\n\tMMU_PAGE_ALIGN_PERM\n\tz_trampoline_stack_end = .;\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_trampoline_stack_end - z_trampoline_stack_start >= 40,\n\t\t\"trampoline stack too small\");\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;\n\n\tz_mapped_end = .;\n\tz_mapped_size = z_mapped_end - z_mapped_start;\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c65e5c88b8ec805d40a4b040a56569f8b1aa8bab","subject":"stm32\/boards\/stm32f429.ld: Increase uPy heap size by 64k for F429 MCU.","message":"stm32\/boards\/stm32f429.ld: Increase uPy heap size by 64k for F429 MCU.\n\nThe F429 has 256k total RAM, with 64k already set aside for flash write\ncache, so the uPy heap can be increased this much.\n","repos":"henriknelson\/micropython,selste\/micropython,pramasoul\/micropython,pozetroninc\/micropython,pramasoul\/micropython,MrSurly\/micropython,henriknelson\/micropython,MrSurly\/micropython,trezor\/micropython,trezor\/micropython,bvernoux\/micropython,henriknelson\/micropython,bvernoux\/micropython,tobbad\/micropython,tobbad\/micropython,pramasoul\/micropython,trezor\/micropython,adafruit\/circuitpython,pfalcon\/micropython,kerneltask\/micropython,selste\/micropython,adafruit\/circuitpython,selste\/micropython,adafruit\/circuitpython,bvernoux\/micropython,tobbad\/micropython,selste\/micropython,pfalcon\/micropython,pozetroninc\/micropython,kerneltask\/micropython,pozetroninc\/micropython,selste\/micropython,tobbad\/micropython,pfalcon\/micropython,tobbad\/micropython,pozetroninc\/micropython,bvernoux\/micropython,henriknelson\/micropython,trezor\/micropython,henriknelson\/micropython,MrSurly\/micropython,bvernoux\/micropython,pramasoul\/micropython,kerneltask\/micropython,pfalcon\/micropython,adafruit\/circuitpython,kerneltask\/micropython,pfalcon\/micropython,adafruit\/circuitpython,trezor\/micropython,pozetroninc\/micropython,kerneltask\/micropython,adafruit\/circuitpython,pramasoul\/micropython,MrSurly\/micropython,MrSurly\/micropython","old_file":"ports\/stm32\/boards\/stm32f429.ld","new_file":"ports\/stm32\/boards\/stm32f429.ld","new_contents":"\/*\n    GNU linker script for STM32F429i-Discovery kit with external 8MByte SDRam\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K \/* entire flash *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K \/* sector 0, 16 KiB *\/\n    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 112K \/* sectors 1-4: 3*16K+64K *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 896K \/* sectors 5-11 are 128K *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K\n    SDRAM(xrw)      : ORIGIN = 0xC0000000, LENGTH = 8192K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = 0x2002c000; \/* tunable *\/\n","old_contents":"\/*\n    GNU linker script for STM32F429i-Discovery kit with external 8MByte SDRam\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K \/* entire flash *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K \/* sector 0, 16 KiB *\/\n    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 112K \/* sectors 1-4: 3*16K+64K *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 896K \/* sectors 5-11 are 128K *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K\n    SDRAM(xrw)      : ORIGIN = 0xC0000000, LENGTH = 8192K\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = 0x2001c000; \/* tunable *\/\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"81b41f0184fee5ffbf68680c963411c0f03bad73","subject":"Temporary expansion on flash size of the 11c24 target.","message":"Temporary expansion on flash size of the 11c24 target.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/nxp-lpc11C24-lpcxpresso\/target.ld","new_file":"boards\/nxp-lpc11C24-lpcxpresso\/target.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(ResetISR)\nSEARCH_DIR(.)\n\nGROUP(\n libgcc.a\n libc_s.a\n libstdc++_s.a\n libm.a\n crti.o\n crtn.o\n crtbegin.o\n crtend.o\n)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  \/*MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x08000  \/*32k *\/\n  MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 \/* 64k TEMPORARY *\/\n  \/* Top 32 bytes is used by the flash writing firmware. 0x50..0xb8 by the ROM CAN drivers. 0 to 0x50 is used by the *\/\n\n  RamLoc8 (rwx) : ORIGIN = 0x10000100, LENGTH = 0x1ee0 \/* 7k *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash32 = ORIGIN(MFlash32) + LENGTH(MFlash32);\n  __top_RamLoc8 = ORIGIN(RamLoc8) + LENGTH(RamLoc8);\n\n  \/* The cortex-m0 FreeRTOS is not using the original stack once the scheduler\n  has started, so we have no reason to reserve the top of RAM. *\/\n  __cs3_heap_end = __top_RamLoc8;\n\n  __start_ram = ORIGIN(RamLoc8);\n  __end_ram = __top_RamLoc8;\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data)) ;\n        LONG(  SIZEOF(.data));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(SORT(.text*))\n\t*(.rodata)\n        *(SORT(.rodata.*))\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        \/* End C++ *\/\n\t\n\t__text_section_guard = .;\n\tLONG( 0 );\n    } > MFlash32\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash32\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash32\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \n    \/* MAIN DATA SECTION *\/\n    \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > RamLoc8\n\n    \/* It seems that in order for LPCXpresso to properly flash the data\n    section, an alignment of 256 bytes is necessary. Otherwise the separate\n    flashing of the data section will corrupt the end of the text section. *\/\n    .data : ALIGN(256)\n    {\n        FILL(0xff)\n        _data = .;\n        *(vtable)\n\t__impure_data_start = .;\n\t*(.data.impure_data)\n\t__impure_data_end = .;\n        *(.data*)\n\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n        . = ALIGN (4);\n\n        _edata = .;\n    } > RamLoc8 AT>MFlash32\n\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n    } > RamLoc8\n        \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > RamLoc8\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(__cs3_heap_start = .);\n    \/* This pointer will be written to the SP register at reset. *\/\n    PROVIDE(_vStackTop = __top_RamLoc8);\n\n    PROVIDE(__impure_data_size = __impure_data_end - __impure_data_start);\n\n}\n\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(ResetISR)\nSEARCH_DIR(.)\n\nGROUP(\n libgcc.a\n libc_s.a\n libstdc++_s.a\n libm.a\n crti.o\n crtn.o\n crtbegin.o\n crtend.o\n)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x08000  \/*32k *\/\n  \/*MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 \/* 64k TEMPORARY *\/\n  \/* Top 32 bytes is used by the flash writing firmware. 0x50..0xb8 by the ROM CAN drivers. 0 to 0x50 is used by the *\/\n\n  RamLoc8 (rwx) : ORIGIN = 0x10000100, LENGTH = 0x1ee0 \/* 7k *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash32 = ORIGIN(MFlash32) + LENGTH(MFlash32);\n  __top_RamLoc8 = ORIGIN(RamLoc8) + LENGTH(RamLoc8);\n\n  \/* The cortex-m0 FreeRTOS is not using the original stack once the scheduler\n  has started, so we have no reason to reserve the top of RAM. *\/\n  __cs3_heap_end = __top_RamLoc8;\n\n  __start_ram = ORIGIN(RamLoc8);\n  __end_ram = __top_RamLoc8;\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data)) ;\n        LONG(  SIZEOF(.data));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(SORT(.text*))\n\t*(.rodata)\n        *(SORT(.rodata.*))\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        \/* End C++ *\/\n\t\n\t__text_section_guard = .;\n\tLONG( 0 );\n    } > MFlash32\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash32\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash32\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \n    \/* MAIN DATA SECTION *\/\n    \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > RamLoc8\n\n    \/* It seems that in order for LPCXpresso to properly flash the data\n    section, an alignment of 256 bytes is necessary. Otherwise the separate\n    flashing of the data section will corrupt the end of the text section. *\/\n    .data : ALIGN(256)\n    {\n        FILL(0xff)\n        _data = .;\n        *(vtable)\n\t__impure_data_start = .;\n\t*(.data.impure_data)\n\t__impure_data_end = .;\n        *(.data*)\n\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n        . = ALIGN (4);\n\n        _edata = .;\n    } > RamLoc8 AT>MFlash32\n\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n    } > RamLoc8\n        \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > RamLoc8\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(__cs3_heap_start = .);\n    \/* This pointer will be written to the SP register at reset. *\/\n    PROVIDE(_vStackTop = __top_RamLoc8);\n\n    PROVIDE(__impure_data_size = __impure_data_end - __impure_data_start);\n\n}\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"1ef117eece53112a8b0212e3a2d3b7e6c2992ae2","subject":"factory.lds: remove empty line","message":"factory.lds: remove empty line\n","repos":"gdelugre\/shell-factory,gdelugre\/shell-factory,gdelugre\/shell-factory","old_file":"factory.lds","new_file":"factory.lds","new_contents":"\/* \n * Linker script for generating shell-factory targets with -N.\n *\/\nSECTIONS\n{\n    PROVIDE (__executable_start = SEGMENT_START(\"text-segment\", 0x400000));\n    . = SEGMENT_START(\"text-segment\", 0x400000) + SIZEOF_HEADERS;\n\n    \/*\n     * The executable code.\n     *\/\n    .text               : { *(.text .text.* .gnu.linkonce.t.*) }\n    PROVIDE(__etext = .);\n    PROVIDE(_etext = .);\n    PROVIDE(etext = .);\n\n    \/* \n     * Constant data.\n     * Merge into the text section.\n     *\/\n    .rodata             : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n\n    \/*\n     * Non-constant data.\n     * Pushed inside the data segment which should be adjacent to text.\n     *\/\n\n    .data               : { *(.data .data.* .gnu.linkonce.d.*) }\n    PROVIDE(edata = .);\n\n    \/*\n     * Uninitialized data. Bound to the data segment, should not take any space.\n     *\/\n    __bss_start = .;\n    .bss                : { *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) }\n\n    _end = .;\n    PROVIDE (end = .);\n\n    \/DISCARD\/           : { *(.note.*) }\n}\n","old_contents":"\/* \n * Linker script for generating shell-factory targets with -N.\n *\/\nSECTIONS\n{\n\n    PROVIDE (__executable_start = SEGMENT_START(\"text-segment\", 0x400000));\n    . = SEGMENT_START(\"text-segment\", 0x400000) + SIZEOF_HEADERS;\n\n    \/*\n     * The executable code.\n     *\/\n    .text               : { *(.text .text.* .gnu.linkonce.t.*) }\n    PROVIDE(__etext = .);\n    PROVIDE(_etext = .);\n    PROVIDE(etext = .);\n\n    \/* \n     * Constant data.\n     * Merge into the text section.\n     *\/\n    .rodata             : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n\n    \/*\n     * Non-constant data.\n     * Pushed inside the data segment which should be adjacent to text.\n     *\/\n\n    .data               : { *(.data .data.* .gnu.linkonce.d.*) }\n    PROVIDE(edata = .);\n\n    \/*\n     * Uninitialized data. Bound to the data segment, should not take any space.\n     *\/\n    __bss_start = .;\n    .bss                : { *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) }\n\n    _end = .;\n    PROVIDE (end = .);\n\n    \/DISCARD\/           : { *(.note.*) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a12dd31564e2eb24b731243166b55277cd4a50d6","subject":"Fix var name for config block (#641)","message":"Fix var name for config block (#641)\n\n","repos":"Eclo\/nf-interpreter,nanoframework\/nf-interpreter,nanoframework\/nf-interpreter,Eclo\/nf-interpreter,Eclo\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter,nanoframework\/nf-interpreter","old_file":"targets\/CMSIS-OS\/ChibiOS\/common\/rules_data.ld","new_file":"targets\/CMSIS-OS\/ChibiOS\/common\/rules_data.ld","new_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio.  All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n__ram0_start__          = ORIGIN(ram0);\n__ram0_size__           = LENGTH(ram0);\n__ram0_end__            = __ram0_start__ + __ram0_size__;\n__ram1_start__          = ORIGIN(ram1);\n__ram1_size__           = LENGTH(ram1);\n__ram1_end__            = __ram1_start__ + __ram1_size__;\n__ram2_start__          = ORIGIN(ram2);\n__ram2_size__           = LENGTH(ram2);\n__ram2_end__            = __ram2_start__ + __ram2_size__;\n__ram3_start__          = ORIGIN(ram3);\n__ram3_size__           = LENGTH(ram3);\n__ram3_end__            = __ram3_start__ + __ram3_size__;\n__ram4_start__          = ORIGIN(ram4);\n__ram4_size__           = LENGTH(ram4);\n__ram4_end__            = __ram4_start__ + __ram4_size__;\n__ram5_start__          = ORIGIN(ram5);\n__ram5_size__           = LENGTH(ram5);\n__ram5_end__            = __ram5_start__ + __ram5_size__;\n__ram6_start__          = ORIGIN(ram6);\n__ram6_size__           = LENGTH(ram6);\n__ram6_end__            = __ram6_start__ + __ram6_size__;\n__ram7_start__          = ORIGIN(ram7);\n__ram7_size__           = LENGTH(ram7);\n__ram7_end__            = __ram7_start__ + __ram7_size__;\n\n__nanoImage_start__     = ORIGIN(flash);\n__nanoImage_size__      = LENGTH(flash);\n__nanoImage_end__       = __nanoImage_start__ + __nanoImage_size__;\n__nanoConfig_start__    = ORIGIN(config);\n__nanoConfig_size__     = LENGTH(config);\n__nanoConfig_end__      = __nanoConfig_start__ + __nanoConfig_size__;\n__deployment_start__    = ORIGIN(deployment);\n__deployment_size__     = LENGTH(deployment);\n__deployment_end__      = __deployment_start__ + __deployment_size__;\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .data : ALIGN(4)\n    {\n        . = ALIGN(4);\n        PROVIDE(_textdata = LOADADDR(.data));\n        PROVIDE(_data = .);\n        _textdata_start = LOADADDR(.data);\n        _data_start = .;\n        *(.data)\n        *(.data.*)\n        *(.ramtext)\n        . = ALIGN(4);\n        PROVIDE(_edata = .);\n        _data_end = .;\n    } > DATA_RAM AT > DATA_RAM_LMA\n\n    .bss (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        _bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _bss_end = .;\n        PROVIDE(end = .);\n    } > BSS_RAM\n\n    .ram0_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram0_init_text__ = LOADADDR(.ram0_init);\n        __ram0_init__ = .;\n        KEEP(*(.ram0_init))\n        KEEP(*(.ram0_init.*))\n        . = ALIGN(4);\n    } > ram0 AT > RAM_INIT_FLASH_LMA\n\n    .ram0 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram0_clear__ = .;\n        *(.ram0_clear)\n        *(.ram0_clear.*)\n        . = ALIGN(4);\n        __ram0_noinit__ = .;\n        *(.ram0)\n        *(.ram0.*)\n        . = ALIGN(4);\n        __ram0_free__ = .;\n    } > ram0\n\n    .ram1_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram1_init_text__ = LOADADDR(.ram1_init);\n        __ram1_init__ = .;\n        KEEP(*(.ram1_init))\n        KEEP(*(.ram1_init.*))\n        . = ALIGN(4);\n    } > ram1 AT > RAM_INIT_FLASH_LMA\n\n    .ram1 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram1_clear__ = .;\n        *(.ram1_clear)\n        *(.ram1_clear.*)\n        . = ALIGN(4);\n        __ram1_noinit__ = .;\n        *(.ram1)\n        *(.ram1.*)\n        . = ALIGN(4);\n        __ram1_free__ = .;\n    } > ram1\n\n    .ram2_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram2_init_text__ = LOADADDR(.ram2_init);\n        __ram2_init__ = .;\n        KEEP(*(.ram2_init))\n        KEEP(*(.ram2_init.*))\n        . = ALIGN(4);\n    } > ram2 AT > RAM_INIT_FLASH_LMA\n\n    .ram2 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram2_clear__ = .;\n        *(.ram2_clear)\n        *(.ram2_clear.*)\n        . = ALIGN(4);\n        __ram2_noinit__ = .;\n        *(.ram2)\n        *(.ram2.*)\n        . = ALIGN(4);\n        __ram2_free__ = .;\n    } > ram2\n\n    .ram3_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram3_init_text__ = LOADADDR(.ram3_init);\n        __ram3_init__ = .;\n        KEEP(*(.ram3_init))\n        KEEP(*(.ram3_init.*))\n        . = ALIGN(4);\n    } > ram3 AT > RAM_INIT_FLASH_LMA\n\n    .ram3 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram3_clear__ = .;\n        *(.ram3_clear)\n        *(.ram3_clear.*)\n        . = ALIGN(4);\n        __ram3_noinit__ = .;\n        *(.ram3)\n        *(.ram3.*)\n        . = ALIGN(4);\n        __ram3_free__ = .;\n    } > ram3\n\n    .ram4_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram4_init_text__ = LOADADDR(.ram4_init);\n        __ram4_init__ = .;\n        KEEP(*(.ram4_init))\n        KEEP(*(.ram4_init.*))\n        . = ALIGN(4);\n    } > ram4 AT > RAM_INIT_FLASH_LMA\n\n    .ram4 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram4_clear__ = .;\n        *(.ram4_clear)\n        *(.ram4_clear.*)\n        . = ALIGN(4);\n        __ram4_noinit__ = .;\n        *(.ram4)\n        *(.ram4.*)\n        . = ALIGN(4);\n        __ram4_free__ = .;\n    } > ram4\n\n    .ram5_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram5_init_text__ = LOADADDR(.ram5_init);\n        __ram5_init__ = .;\n        KEEP(*(.ram5_init))\n        KEEP(*(.ram5_init.*))\n        . = ALIGN(4);\n    } > ram5 AT > RAM_INIT_FLASH_LMA\n\n    .ram5 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram5_clear__ = .;\n        *(.ram5_clear)\n        *(.ram5_clear.*)\n        . = ALIGN(4);\n        __ram5_noinit__ = .;\n        *(.ram5)\n        *(.ram5.*)\n        . = ALIGN(4);\n        __ram5_free__ = .;\n    } > ram5\n\n    .ram6_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram6_init_text__ = LOADADDR(.ram6_init);\n        __ram6_init__ = .;\n        KEEP(*(.ram6_init))\n        KEEP(*(.ram6_init.*))\n        . = ALIGN(4);\n    } > ram6 AT > RAM_INIT_FLASH_LMA\n\n    .ram6 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram6_clear__ = .;\n        *(.ram6_clear)\n        *(.ram6_clear.*)\n        . = ALIGN(4);\n        __ram6_noinit__ = .;\n        *(.ram6)\n        *(.ram6.*)\n        . = ALIGN(4);\n        __ram6_free__ = .;\n    } > ram6\n\n    .ram7_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram7_init_text__ = LOADADDR(.ram7_init);\n        __ram7_init__ = .;\n        KEEP(*(.ram7_init))\n        KEEP(*(.ram7_init.*))\n        . = ALIGN(4);\n    } > ram7 AT > RAM_INIT_FLASH_LMA\n\n    .ram7 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram7_clear__ = .;\n        *(.ram7_clear)\n        *(.ram7_clear.*)\n        . = ALIGN(4);\n        __ram7_noinit__ = .;\n        *(.ram7)\n        *(.ram7.*)\n        . = ALIGN(4);\n        __ram7_free__ = .;\n    } > ram7\n\n    \/* The default heap uses the (statically) unused part of a RAM section.*\/\n    .heap (NOLOAD) :\n    {\n        . = ALIGN(8);\n        __heap_base__ = .;\n        . += __crt_heap_size__;\n        . = ALIGN(8);\n        __heap_end__ = .;\n    } > HEAP_RAM\n}\n","old_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio.  All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n__ram0_start__          = ORIGIN(ram0);\n__ram0_size__           = LENGTH(ram0);\n__ram0_end__            = __ram0_start__ + __ram0_size__;\n__ram1_start__          = ORIGIN(ram1);\n__ram1_size__           = LENGTH(ram1);\n__ram1_end__            = __ram1_start__ + __ram1_size__;\n__ram2_start__          = ORIGIN(ram2);\n__ram2_size__           = LENGTH(ram2);\n__ram2_end__            = __ram2_start__ + __ram2_size__;\n__ram3_start__          = ORIGIN(ram3);\n__ram3_size__           = LENGTH(ram3);\n__ram3_end__            = __ram3_start__ + __ram3_size__;\n__ram4_start__          = ORIGIN(ram4);\n__ram4_size__           = LENGTH(ram4);\n__ram4_end__            = __ram4_start__ + __ram4_size__;\n__ram5_start__          = ORIGIN(ram5);\n__ram5_size__           = LENGTH(ram5);\n__ram5_end__            = __ram5_start__ + __ram5_size__;\n__ram6_start__          = ORIGIN(ram6);\n__ram6_size__           = LENGTH(ram6);\n__ram6_end__            = __ram6_start__ + __ram6_size__;\n__ram7_start__          = ORIGIN(ram7);\n__ram7_size__           = LENGTH(ram7);\n__ram7_end__            = __ram7_start__ + __ram7_size__;\n\n__nanoImage_start__     = ORIGIN(flash);\n__nanoImage_size__      = LENGTH(flash);\n__nanoImage_end__       = __nanoImage_start__ + __nanoImage_size__;\n__nanoConfig_start__    = ORIGIN(config);\n__nanoConfig_size__     = LENGTH(config);\n__nanoConfig_end__      = __nanoImage_start__ + __nanoConfig_size__;\n__deployment_start__    = ORIGIN(deployment);\n__deployment_size__     = LENGTH(deployment);\n__deployment_end__      = __deployment_start__ + __deployment_size__;\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .data : ALIGN(4)\n    {\n        . = ALIGN(4);\n        PROVIDE(_textdata = LOADADDR(.data));\n        PROVIDE(_data = .);\n        _textdata_start = LOADADDR(.data);\n        _data_start = .;\n        *(.data)\n        *(.data.*)\n        *(.ramtext)\n        . = ALIGN(4);\n        PROVIDE(_edata = .);\n        _data_end = .;\n    } > DATA_RAM AT > DATA_RAM_LMA\n\n    .bss (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        _bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _bss_end = .;\n        PROVIDE(end = .);\n    } > BSS_RAM\n\n    .ram0_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram0_init_text__ = LOADADDR(.ram0_init);\n        __ram0_init__ = .;\n        KEEP(*(.ram0_init))\n        KEEP(*(.ram0_init.*))\n        . = ALIGN(4);\n    } > ram0 AT > RAM_INIT_FLASH_LMA\n\n    .ram0 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram0_clear__ = .;\n        *(.ram0_clear)\n        *(.ram0_clear.*)\n        . = ALIGN(4);\n        __ram0_noinit__ = .;\n        *(.ram0)\n        *(.ram0.*)\n        . = ALIGN(4);\n        __ram0_free__ = .;\n    } > ram0\n\n    .ram1_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram1_init_text__ = LOADADDR(.ram1_init);\n        __ram1_init__ = .;\n        KEEP(*(.ram1_init))\n        KEEP(*(.ram1_init.*))\n        . = ALIGN(4);\n    } > ram1 AT > RAM_INIT_FLASH_LMA\n\n    .ram1 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram1_clear__ = .;\n        *(.ram1_clear)\n        *(.ram1_clear.*)\n        . = ALIGN(4);\n        __ram1_noinit__ = .;\n        *(.ram1)\n        *(.ram1.*)\n        . = ALIGN(4);\n        __ram1_free__ = .;\n    } > ram1\n\n    .ram2_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram2_init_text__ = LOADADDR(.ram2_init);\n        __ram2_init__ = .;\n        KEEP(*(.ram2_init))\n        KEEP(*(.ram2_init.*))\n        . = ALIGN(4);\n    } > ram2 AT > RAM_INIT_FLASH_LMA\n\n    .ram2 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram2_clear__ = .;\n        *(.ram2_clear)\n        *(.ram2_clear.*)\n        . = ALIGN(4);\n        __ram2_noinit__ = .;\n        *(.ram2)\n        *(.ram2.*)\n        . = ALIGN(4);\n        __ram2_free__ = .;\n    } > ram2\n\n    .ram3_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram3_init_text__ = LOADADDR(.ram3_init);\n        __ram3_init__ = .;\n        KEEP(*(.ram3_init))\n        KEEP(*(.ram3_init.*))\n        . = ALIGN(4);\n    } > ram3 AT > RAM_INIT_FLASH_LMA\n\n    .ram3 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram3_clear__ = .;\n        *(.ram3_clear)\n        *(.ram3_clear.*)\n        . = ALIGN(4);\n        __ram3_noinit__ = .;\n        *(.ram3)\n        *(.ram3.*)\n        . = ALIGN(4);\n        __ram3_free__ = .;\n    } > ram3\n\n    .ram4_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram4_init_text__ = LOADADDR(.ram4_init);\n        __ram4_init__ = .;\n        KEEP(*(.ram4_init))\n        KEEP(*(.ram4_init.*))\n        . = ALIGN(4);\n    } > ram4 AT > RAM_INIT_FLASH_LMA\n\n    .ram4 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram4_clear__ = .;\n        *(.ram4_clear)\n        *(.ram4_clear.*)\n        . = ALIGN(4);\n        __ram4_noinit__ = .;\n        *(.ram4)\n        *(.ram4.*)\n        . = ALIGN(4);\n        __ram4_free__ = .;\n    } > ram4\n\n    .ram5_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram5_init_text__ = LOADADDR(.ram5_init);\n        __ram5_init__ = .;\n        KEEP(*(.ram5_init))\n        KEEP(*(.ram5_init.*))\n        . = ALIGN(4);\n    } > ram5 AT > RAM_INIT_FLASH_LMA\n\n    .ram5 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram5_clear__ = .;\n        *(.ram5_clear)\n        *(.ram5_clear.*)\n        . = ALIGN(4);\n        __ram5_noinit__ = .;\n        *(.ram5)\n        *(.ram5.*)\n        . = ALIGN(4);\n        __ram5_free__ = .;\n    } > ram5\n\n    .ram6_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram6_init_text__ = LOADADDR(.ram6_init);\n        __ram6_init__ = .;\n        KEEP(*(.ram6_init))\n        KEEP(*(.ram6_init.*))\n        . = ALIGN(4);\n    } > ram6 AT > RAM_INIT_FLASH_LMA\n\n    .ram6 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram6_clear__ = .;\n        *(.ram6_clear)\n        *(.ram6_clear.*)\n        . = ALIGN(4);\n        __ram6_noinit__ = .;\n        *(.ram6)\n        *(.ram6.*)\n        . = ALIGN(4);\n        __ram6_free__ = .;\n    } > ram6\n\n    .ram7_init : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram7_init_text__ = LOADADDR(.ram7_init);\n        __ram7_init__ = .;\n        KEEP(*(.ram7_init))\n        KEEP(*(.ram7_init.*))\n        . = ALIGN(4);\n    } > ram7 AT > RAM_INIT_FLASH_LMA\n\n    .ram7 (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN(4);\n        __ram7_clear__ = .;\n        *(.ram7_clear)\n        *(.ram7_clear.*)\n        . = ALIGN(4);\n        __ram7_noinit__ = .;\n        *(.ram7)\n        *(.ram7.*)\n        . = ALIGN(4);\n        __ram7_free__ = .;\n    } > ram7\n\n    \/* The default heap uses the (statically) unused part of a RAM section.*\/\n    .heap (NOLOAD) :\n    {\n        . = ALIGN(8);\n        __heap_base__ = .;\n        . += __crt_heap_size__;\n        . = ALIGN(8);\n        __heap_end__ = .;\n    } > HEAP_RAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"62400bd07faaf7d4d2e3df5e01269f1f210cafae","subject":"Move stack near BSS so it doesn't take up space in the .bin","message":"Move stack near BSS so it doesn't take up space in the .bin\n","repos":"bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,bluerover\/6lbr,malvira\/libmc1322x,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,malvira\/libmc1322x,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,muffinator\/libmc1322x,MohamedSeliem\/contiki,arurke\/contiki,muffinator\/libmc1322x,MohamedSeliem\/contiki,bluerover\/6lbr","old_file":"mc1322x.lds","new_file":"mc1322x.lds","new_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS\n{\n\nSYS_STACK_SIZE = 1024;\nIRQ_STACK_SIZE = 256;\nFIQ_STACK_SIZE = 256;\nSVC_STACK_SIZE = 256;\nABT_STACK_SIZE = 16;\nUND_STACK_SIZE = 16;\nHEAP_SIZE = 1024;\n\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x00400000); . = 0x00400000;\n  .text           :\n  {\n    *(.start)\n    *(.irq)\t\t\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  } =0\n\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n      *(.rela.ctors)\n      *(.rela.dtors)\n      *(.rela.got)\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n    }\n  .rel.plt        : { *(.rel.plt) }\n  .rela.plt       : { *(.rela.plt) }\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0\n  .plt            : { *(.plt) }\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n\n\/*  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); *\/\n\n\t. = ALIGN(4);\n\t. = DATA_SEGMENT_ALIGN(4,4); \n\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n  .init_array     :\n  {\n     PROVIDE_HIDDEN (__init_array_start = .);\n     KEEP (*(SORT(.init_array.*)))\n     KEEP (*(.init_array))\n     PROVIDE_HIDDEN (__init_array_end = .);\n  }\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .jcr            : { KEEP (*(.jcr)) } \n  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }\n  .dynamic        : { *(.dynamic) } \n  . = DATA_SEGMENT_RELRO_END (0, .);  \n  .got            : { *(.got.plt) *(.got) }\n  .data           :\n  {\n    __data_start = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .data1          : { *(.data1) }\n  _edata = .; PROVIDE (edata = .);\n\n\t.stack : {\n\t\t__stack_start__ = . ;\n\n\t\t. += IRQ_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__irq_stack_top__ = . ;\n\n\t\t. += FIQ_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__fiq_stack_top__ = . ;\n\n\t\t. += SVC_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__svc_stack_top__ = . ;\n\n\t\t. += ABT_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__abt_stack_top__ = . ;\n\n\t\t. += UND_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__und_stack_top__ = . ;\n\n\t\t. += SYS_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__sys_stack_top__ = . ;\n\n\t\t__stack_end__ = .;\n\t}\n\n\n  __bss_start = .;\n  __bss_start__ = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.\n      FIXME: Why do we need it? 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Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.\n      FIXME: Why do we need it? When there is no .bss section, we don't\n      pad the .data section.  *\/\n   . = ALIGN(. != 0 ? 32 \/ 8 : 1);\n  }\n  _bss_end__ = . ; __bss_end__ = . ;\n  . = ALIGN(32 \/ 8);\n\n   .heap : {\n                __heap_start__ = . ;\n                *(.heap);\n                . += HEAP_SIZE;\n                . = ALIGN (4);\n                __heap_end__ = . ;\n   }\n\n\n  . = ALIGN(32 \/ 8);\n  __end__ = . ;\n  _end = .; PROVIDE (end = .);\n  . = DATA_SEGMENT_END (.);\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"33bb4747c8a6f82a7b817e80d989d58deb266e0b","subject":"updated linker script","message":"updated linker script\n","repos":"stateos\/IntrOS,stateos\/IntrOS,stateos\/IntrOS","old_file":"startup\/STM32F4\/GNUCC\/script.ld","new_file":"startup\/STM32F4\/GNUCC\/script.ld","new_contents":"\/*******************************************************************************\n@file     stm32f4xx.ld\n@author   Rajmund Szymanski\n@date     28.02.2017\n@brief    Linker script for STM32F407VG device with 1024KB FLASH and 192KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 1024k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   64k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  128k\n\/*\tAUX (rwx) : ORIGIN = 0x2001C000, LENGTH =   16k\n*\/\tBKP (rwx) : ORIGIN = 0x40024000, LENGTH =    4k\n}\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__heap_start = LOADADDR(.proc_stack);\n\t__heap_end   = __ram_end - __proc_stack_size;\n\n\t__proc_stack_start = __heap_end;\n\t__proc_stack_end   = __ram_end;\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n\tPROVIDE(__process_stack_end   = __proc_stack_end);\n}\n","old_contents":"\/*******************************************************************************\n@file     stm32f4xx.ld\n@author   Rajmund Szymanski\n@date     02.01.2017\n@brief    Linker script for STM32F407VG device with 1024KB FLASH and 192KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 1024k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   64k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  128k\n\/*\tAUX (rwx) : ORIGIN = 0x2001C000, LENGTH =   16k\n*\/\tBKP (rwx) : ORIGIN = 0x40024000, LENGTH =    4k\n}\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t. = ABSOLUTE(__ram_end - __proc_stack_size);\n\t\t__heap_end = .;\n\t} > RAM\n\n\t__heap_size = SIZEOF(.heap);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8376ce7a79b8a3c41fe7b5c18deb2447d8dbecb8","subject":"Modified K66F flash ld file to only use one RAM memory region.","message":"Modified K66F flash ld file to only use one RAM memory region.\n\n- This prevents issues with running out of RAM while linking.\n- It's possible that an object could straddle the 0x2000_0000 RAM region\n  boundary, but as long as only aligned accesses are used there should\n  be no problems.\n","repos":"flit\/modular,flit\/modular,flit\/modular,flit\/modular,flit\/modular","old_file":"src\/devices\/MK66F18\/gcc\/MK66FN2M0xxx18_flash.ld","new_file":"src\/devices\/MK66F18\/gcc\/MK66FN2M0xxx18_flash.ld","new_contents":"\/*\n** ###################################################################\n**     Processors:          MK66FN2M0VLQ18\n**                          MK66FN2M0VMD18\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015\n**     Version:             rev. 3.0, 2015-03-25\n**     Build:               b160112\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2016 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x001FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00040000\n\/*  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000 *\/\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n  } > m_data \/*_2*\/\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n  } > m_data \/*_2*\/\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n\/*  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2); *\/\n  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n}\n\n","old_contents":"\/*\n** ###################################################################\n**     Processors:          MK66FN2M0VLQ18\n**                          MK66FN2M0VMD18\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015\n**     Version:             rev. 3.0, 2015-03-25\n**     Build:               b160112\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2016 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x001FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"e0bcf9f959bad92d72cfe56ed9d0650b07919856","subject":"xtensa: cavs: add uncached ram sections to cavs25 linker script","message":"xtensa: cavs: add uncached ram sections to cavs25 linker script\n\nAlign cavs25 with cavs15\/18 and add memory segment for uncached mapping\nof the SRAM to linker script. Assign sections to uncached and cached\nsegments as done in cavs15\/18.\n\nSigned-off-by: Kai Vehmanen <7c1f7969959c2510655bc0fc9c602f735b2254b7@linux.intel.com>\n","repos":"finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v25\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v25\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n\n  lpsram_alt_reset_vec_seg :\n        org = LP_SRAM_ALT_RESET_VEC_BASE,\n        len = LP_SRAM_ALT_RESET_VEC_SIZE\n  lpsram_alt_reset_int_vec_seg :\n        org = LP_SRAM_ALT_RESET_INT_VEC_BASE,\n        len = LP_SRAM_ALT_RESET_INT_VEC_SIZE\n  lpsram_code_seg :\n        org = LP_SRAM_CODE_BASE,\n        len = LP_SRAM_CODE_SIZE\n  lpsram_mem :\n        org = LP_SRAM_START,\n        len = LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n\n  lpsram_mem_phdr PT_LOAD;\n  sram_alt_fw_reset_vec_phdr PT_LOAD;\n  sram_alt_fw_reset_vec_int_phdr PT_LOAD;\n  lpsram_code_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\nEXTERN(_LpsramHeader)\nEXTERN(_AltResetVector)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs25_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .AlternateResetVector.text : ALIGN(64)\n  {\n    _alternate_reset_vector_start = ABSOLUTE(.);\n    KEEP (*(*.AlternateResetVector.text))\n    . = ALIGN(16);\n    _alternate_reset_vector_start_end = ABSOLUTE(.);\n  } >lpsram_alt_reset_vec_seg AT> ram : sram_alt_fw_reset_vec_phdr\n\n  .AlternateResetL2IntVector.text : ALIGN(16)\n  {\n    _alternate_reset_l2_int_vector_start = ABSOLUTE(.);\n    KEEP (*(*.AlternateResetL2IntVector.text))\n    . = ALIGN(16);\n    _alternate_reset_l2_int_vector_end = ABSOLUTE(.);\n  } >lpsram_alt_reset_int_vec_seg AT> ram : sram_alt_fw_reset_vec_int_phdr\n\n  .LpsramCode.text : ALIGN(16)\n  {\n    _lpsram_code_start = ABSOLUTE(.);\n    KEEP (*(*.LpsramCode.text))\n    . = ALIGN(16);\n    _lpsram_code_end = ABSOLUTE(.);\n  } >lpsram_code_seg AT> ram : lpsram_code_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n  . = SEGSTART_UNCACHED;\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n\n#include <linker\/common-ram.ld>\n\n  .AltBootManifest SEGSTART_CACHED : ALIGN(8)\n  {\n    \/* Single entry of strorage manifest\n     * consist of 3 items. Entries array\n     * is preceded by a single dword with\n     * entries count. *\/\n    _loader_storage_manifest_start = ABSOLUTE(.);\n    \/* Number of entries*\/\n    LONG(3);\n    \/* Entry 1 *\/\n    LONG(LOADADDR(.AlternateResetVector.text));\n    LONG(ADDR(.AlternateResetVector.text));\n    LONG(SIZEOF(.AlternateResetVector.text));\n    \/* Entry 2 *\/\n    LONG(LOADADDR(.AlternateResetL2IntVector.text));\n    LONG(ADDR(.AlternateResetL2IntVector.text));\n    LONG(SIZEOF(.AlternateResetL2IntVector.text));\n\t\/* Entry 3 *\/\n\tLONG(LOADADDR(.LpsramCode.text));\n    LONG(ADDR(.LpsramCode.text));\n    LONG(SIZEOF(.LpsramCode.text));\n\t_loader_storage_manifest_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n  . = SEGSTART_UNCACHED;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#define LP_SRAM_REGION lpram\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n\n  lpsram_alt_reset_vec_seg :\n        org = LP_SRAM_ALT_RESET_VEC_BASE,\n        len = LP_SRAM_ALT_RESET_VEC_SIZE\n  lpsram_alt_reset_int_vec_seg :\n        org = LP_SRAM_ALT_RESET_INT_VEC_BASE,\n        len = LP_SRAM_ALT_RESET_INT_VEC_SIZE\n  lpsram_code_seg :\n        org = LP_SRAM_CODE_BASE,\n        len = LP_SRAM_CODE_SIZE\n  lpsram_mem :\n        org = LP_SRAM_START,\n        len = LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n\n  lpsram_mem_phdr PT_LOAD;\n  sram_alt_fw_reset_vec_phdr PT_LOAD;\n  sram_alt_fw_reset_vec_int_phdr PT_LOAD;\n  lpsram_code_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\nEXTERN(_LpsramHeader)\nEXTERN(_AltResetVector)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n#ifndef CONFIG_SMP\n_memmap_cacheattr_intel_cavs25_adsp = 0xFF42FFF2;\n#else\n\/*\n * FIXME: Make 0xA0000000 - 0xBFFFFFFF to bypass cache under SMP\n * since there is no data cache manipulation for spinlock, kernel\n * object, scheduler, etc...\n *\/\n_memmap_cacheattr_intel_cavs25_adsp = 0xFF22FFF2;\n#endif\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .AlternateResetVector.text : ALIGN(64)\n  {\n    _alternate_reset_vector_start = ABSOLUTE(.);\n    KEEP (*(*.AlternateResetVector.text))\n    . = ALIGN(16);\n    _alternate_reset_vector_start_end = ABSOLUTE(.);\n  } >lpsram_alt_reset_vec_seg AT> ram : sram_alt_fw_reset_vec_phdr\n\n  .AlternateResetL2IntVector.text : ALIGN(16)\n  {\n    _alternate_reset_l2_int_vector_start = ABSOLUTE(.);\n    KEEP (*(*.AlternateResetL2IntVector.text))\n    . = ALIGN(16);\n    _alternate_reset_l2_int_vector_end = ABSOLUTE(.);\n  } >lpsram_alt_reset_int_vec_seg AT> ram : sram_alt_fw_reset_vec_int_phdr\n\n  .LpsramCode.text : ALIGN(16)\n  {\n    _lpsram_code_start = ABSOLUTE(.);\n    KEEP (*(*.LpsramCode.text))\n    . = ALIGN(16);\n    _lpsram_code_end = ABSOLUTE(.);\n  } >lpsram_code_seg AT> ram : lpsram_code_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .cached :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .AltBootManifest : ALIGN(8)\n  {\n    \/* Single entry of strorage manifest\n     * consist of 3 items. Entries array\n     * is preceded by a single dword with\n     * entries count. *\/\n    _loader_storage_manifest_start = ABSOLUTE(.);\n    \/* Number of entries*\/\n    LONG(3);\n    \/* Entry 1 *\/\n    LONG(LOADADDR(.AlternateResetVector.text));\n    LONG(ADDR(.AlternateResetVector.text));\n    LONG(SIZEOF(.AlternateResetVector.text));\n    \/* Entry 2 *\/\n    LONG(LOADADDR(.AlternateResetL2IntVector.text));\n    LONG(ADDR(.AlternateResetL2IntVector.text));\n    LONG(SIZEOF(.AlternateResetL2IntVector.text));\n\t\/* Entry 3 *\/\n\tLONG(LOADADDR(.LpsramCode.text));\n    LONG(ADDR(.LpsramCode.text));\n    LONG(SIZEOF(.LpsramCode.text));\n\t_loader_storage_manifest_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  .bss (NOLOAD) : ALIGN(4096)\n  {\n    . = ALIGN(4096);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"82cd648b9b3ac9f9328acc30d391e31d546c1d23","subject":"x86: don't shift data addresses between builds","message":"x86: don't shift data addresses between builds\n\nInserting the IDT results in any data afterwards being shifted.\nWe want the memory addresses between the zephyr_prebuilt.elf\nand zephyr.elf to be as close as possible. Insert some dummy\ndata in the linker script the same size as the gen_idt data\nstructures. Needed for forthcoming patches which generate MMU\npage tables at build time.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"fractalclone\/zephyr-riscv,ldts\/zephyr,sharronliu\/zephyr,ldts\/zephyr,sharronliu\/zephyr,mbolivar\/zephyr,fractalclone\/zephyr-riscv,Vudentz\/zephyr,kraj\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,runchip\/zephyr-cc3220,fbsder\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,punitvara\/zephyr,zephyriot\/zephyr,finikorg\/zephyr,galak\/zephyr,punitvara\/zephyr,kraj\/zephyr,rsalveti\/zephyr,runchip\/zephyr-cc3220,kraj\/zephyr,aceofall\/zephyr-iotos,finikorg\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,fractalclone\/zephyr-riscv,sharronliu\/zephyr,rsalveti\/zephyr,finikorg\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,zephyriot\/zephyr,nashif\/zephyr,galak\/zephyr,explora26\/zephyr,sharronliu\/zephyr,fbsder\/zephyr,punitvara\/zephyr,runchip\/zephyr-cc3220,mbolivar\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,Vudentz\/zephyr,explora26\/zephyr,Vudentz\/zephyr,explora26\/zephyr,kraj\/zephyr,explora26\/zephyr,fbsder\/zephyr,holtmann\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,aceofall\/zephyr-iotos,holtmann\/zephyr,runchip\/zephyr-cc3220,aceofall\/zephyr-iotos,fbsder\/zephyr,kraj\/zephyr,Vudentz\/zephyr,holtmann\/zephyr,ldts\/zephyr,fractalclone\/zephyr-riscv,rsalveti\/zephyr,GiulianoFranchetto\/zephyr,zephyriot\/zephyr,aceofall\/zephyr-iotos,fractalclone\/zephyr-riscv,finikorg\/zephyr,explora26\/zephyr,Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,runchip\/zephyr-cc3220,aceofall\/zephyr-iotos,rsalveti\/zephyr,rsalveti\/zephyr,punitvara\/zephyr,holtmann\/zephyr,sharronliu\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,galak\/zephyr,holtmann\/zephyr,finikorg\/zephyr,mbolivar\/zephyr,fbsder\/zephyr,zephyriot\/zephyr,mbolivar\/zephyr,galak\/zephyr","old_file":"include\/arch\/x86\/linker.ld","new_file":"include\/arch\/x86\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n#define MMU_PAGE_SIZE KB(4)\n\n#include <linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROMABLE_REGION start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\t*(.top_of_image_ram)\n\t*(.top_of_image_ram.*)\n\t*(.data)\n\t*(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\tCOMMON_SYMBOLS\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n#ifdef CONFIG_XIP\n\t\/*\n\t * Ensure linker keeps sections in correct order, despite the fact\n\t * the previous section specified a load address and this no-load\n\t * section doesn't.\n\t *\/\n\t  GROUP_FOLLOWS_AT(RAMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t*(.noinit)\n\t*(\".noinit.*\")\n\n\t*(.bottom_of_image_ram)\n\t*(.bottom_of_image_ram.*)\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t. = ALIGN(MMU_PAGE_SIZE);\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n#define MMU_PAGE_SIZE KB(4)\n\n#include <linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n\tKEEP(*(staticIdt))\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n\tKEEP(*(irq_int_vector_map))\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROMABLE_REGION start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\t*(.top_of_image_ram)\n\t*(.top_of_image_ram.*)\n\t*(.data)\n\t*(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\tCOMMON_SYMBOLS\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n#ifdef CONFIG_XIP\n\t\/*\n\t * Ensure linker keeps sections in correct order, despite the fact\n\t * the previous section specified a load address and this no-load\n\t * section doesn't.\n\t *\/\n\t  GROUP_FOLLOWS_AT(RAMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t*(.noinit)\n\t*(\".noinit.*\")\n\n\t*(.bottom_of_image_ram)\n\t*(.bottom_of_image_ram.*)\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t. = ALIGN(MMU_PAGE_SIZE);\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ebdcba70020fbcfc0e4db7d4bb1d4cdcf7969c8e","subject":"x86: linker.ld: support __kernel sections","message":"x86: linker.ld: support __kernel sections\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"aceofall\/zephyr-iotos,Vudentz\/zephyr,fbsder\/zephyr,Vudentz\/zephyr,ldts\/zephyr,mbolivar\/zephyr,ldts\/zephyr,mbolivar\/zephyr,runchip\/zephyr-cc3220,Vudentz\/zephyr,punitvara\/zephyr,fbsder\/zephyr,punitvara\/zephyr,explora26\/zephyr,zephyriot\/zephyr,Vudentz\/zephyr,zephyriot\/zephyr,galak\/zephyr,nashif\/zephyr,explora26\/zephyr,Vudentz\/zephyr,galak\/zephyr,kraj\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,fbsder\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,nashif\/zephyr,runchip\/zephyr-cc3220,mbolivar\/zephyr,rsalveti\/zephyr,fbsder\/zephyr,fbsder\/zephyr,ldts\/zephyr,nashif\/zephyr,explora26\/zephyr,mbolivar\/zephyr,nashif\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,kraj\/zephyr,explora26\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,aceofall\/zephyr-iotos,aceofall\/zephyr-iotos,galak\/zephyr,runchip\/zephyr-cc3220,aceofall\/zephyr-iotos,rsalveti\/zephyr,galak\/zephyr,finikorg\/zephyr,punitvara\/zephyr,finikorg\/zephyr,nashif\/zephyr,rsalveti\/zephyr,aceofall\/zephyr-iotos,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3220,kraj\/zephyr,GiulianoFranchetto\/zephyr,rsalveti\/zephyr,kraj\/zephyr,runchip\/zephyr-cc3220,mbolivar\/zephyr,galak\/zephyr,zephyriot\/zephyr,rsalveti\/zephyr,finikorg\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/x86\/linker.ld","new_file":"include\/arch\/x86\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROMABLE_REGION start addr *\/\n\n\t\/* This align directive needs to be after __data_rom_start or XIP\n\t * won't be copying the data from the right LMA\n\t *\/\n\tMMU_PAGE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n#endif\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\t\/* All stacks go in kernel's noinit, regardless of where they\n\t * were defined.\n\t *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\t__kernel_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tMMU_PAGE_ALIGN\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROMABLE_REGION start addr *\/\n\n\t\/* This align directive needs to be after __data_rom_start or XIP\n\t * won't be copying the data from the right LMA\n\t *\/\n\tMMU_PAGE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n#endif\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\n\t\/* All stacks go in kernel's noinit, regardless of where they\n\t * were defined.\n\t *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\t__kernel_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tMMU_PAGE_ALIGN\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"931f5a7ed412bb9c5fe4256ae9ba40197dc180c9","subject":"","message":"\n\ngit-svn-id: https:\/\/chibios.svn.sourceforge.net\/svnroot\/chibios\/trunk@452 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"demos\/ARMCM3-STM32F103-GCC\/ch.ld","new_file":"demos\/ARMCM3-STM32F103-GCC\/ch.ld","new_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * ST32F103 memory setup.\r\n *\/\r\n__main_stack_size__\t= 0x0200;\r\n__process_stack_size__\t= 0x0100;\r\n__stacks_total_size__\t= __main_stack_size__ + __process_stack_size__;\r\n\r\nMEMORY\r\n{\r\n\tflash : org = 0x08000000, len = 128k\r\n\tram : org = 0x20000000, len = 20k\r\n}\r\n\r\n__ram_start__\t\t= ORIGIN(ram);\r\n__ram_size__\t\t= LENGTH(ram);\r\n__ram_end__\t\t= __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n\t. = 0;\r\n\r\n\t.text :\r\n\t{\r\n\t\t_text = .;\r\n\t\tKEEP(*(vectors));\r\n                *(.text)\r\n\t\t*(.text.*);\r\n\t\t*(.rodata);\r\n\t\t*(.rodata.*);\r\n\t\t*(.glue_7t);\r\n\t\t*(.glue_7);\r\n\t\t*(.gcc*);\r\n\t\t*(.ctors);\r\n\t\t*(.dtors);\r\n\t\t. = ALIGN(4);\r\n\t\t_etext = .;\r\n\t} > flash\r\n\r\n\t_textdata = _etext;\r\n\r\n\t.data :\r\n\t{\r\n\t\t_data = .;\r\n\t\t*(.data)\r\n\t\t. = ALIGN(4);\r\n\t\t*(.data.*)\r\n\t\t. = ALIGN(4);\r\n\t\t*(.ramtext)\r\n\t\t. = ALIGN(4);\r\n\t\t_edata = .;\r\n\t} > ram AT > flash\r\n\r\n\t.bss :\r\n\t{\r\n\t\t_bss_start = .;\r\n\t\t*(.bss)\r\n\t\t. = ALIGN(4);\r\n\t\t*(.bss.*)\r\n\t\t. = ALIGN(4);\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(4);\r\n\t\t_bss_end = .;\r\n\t} > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end \t\t\t= .;\r\n\r\n__heap_base__\t\t= _end;\r\n__heap_end__\t\t= __ram_end__ - __stacks_total_size__;\r\n","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * ST32F103 memory setup.\r\n *\/\r\n__main_stack_size__\t= 0x0200;\r\n__process_stack_size__\t= 0x0100;\r\n__stacks_total_size__\t= __main_stack_size__ + __process_stack_size__;\r\n\r\nMEMORY\r\n{\r\n\tflash : org = 0x08000000, len = 128k\r\n\tram : org = 0x20000000, len = 20k\r\n}\r\n\r\n__ram_start__\t\t= ORIGIN(ram);\r\n__ram_size__\t\t= LENGTH(ram);\r\n__ram_end__\t\t= __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n\t. = 0;\r\n\r\n\t.text :\r\n\t{\r\n\t\t_text = .;\r\n\t\tKEEP(*(INTVEC));\r\n                *(.text)\r\n\t\t*(.text.*);\r\n\t\t*(.rodata);\r\n\t\t*(.rodata.*);\r\n\t\t*(.glue_7t);\r\n\t\t*(.glue_7);\r\n\t\t*(.gcc*);\r\n\t\t*(.ctors);\r\n\t\t*(.dtors);\r\n\t\t. = ALIGN(4);\r\n\t\t_etext = .;\r\n\t} > flash\r\n\r\n\t_textdata = _etext;\r\n\r\n\t.data :\r\n\t{\r\n\t\t_data = .;\r\n\t\t*(.data)\r\n\t\t. = ALIGN(4);\r\n\t\t*(.data.*)\r\n\t\t. = ALIGN(4);\r\n\t\t*(.ramtext)\r\n\t\t. = ALIGN(4);\r\n\t\t_edata = .;\r\n\t} > ram AT > flash\r\n\r\n\t.bss :\r\n\t{\r\n\t\t_bss_start = .;\r\n\t\t*(.bss)\r\n\t\t. = ALIGN(4);\r\n\t\t*(.bss.*)\r\n\t\t. = ALIGN(4);\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(4);\r\n\t\t_bss_end = .;\r\n\t} > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end \t\t\t= .;\r\n\r\n__heap_base__\t\t= _end;\r\n__heap_end__\t\t= __ram_end__ - __stacks_total_size__;\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"24ae9032acb79c3c61b00c88bdc50faf8169aca5","subject":"nucleo boot linker script; only have 16k of space for bootloader.","message":"nucleo boot linker script; only have 16k of space for bootloader.\n","repos":"andrzej-kaczmarek\/apache-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,mlaz\/mynewt-core,wes3\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,wes3\/incubator-mynewt-core","old_file":"hw\/bsp\/nucleo-f401re\/boot-nucleo-f401re.ld","new_file":"hw\/bsp\/nucleo-f401re\/boot-nucleo-f401re.ld","new_contents":"\/**\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n * \n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\n \n\/* Linker script for STM32F401 when running the boot loader *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 16K\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __coredata_start__\n *   __coredata_end__\n *   __corebss_start__\n *   __corebss_end__\n *   __ecoredata\n *   __ecorebss\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        __vector_tbl_reloc__ = .;\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n\n    __exidx_end = .;\n\n    . = ALIGN(8);\n    __etext = .;\n\n    .coredata : AT (__etext)\n    {\n        __coredata_start__ = .;\n        *(.data.core)\n        . = ALIGN(8);\n        __coredata_end__ = .;\n    } > RAM\n\n    __ecoredata = __etext + SIZEOF(.coredata);\n\n    .data : AT (__ecoredata)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .corebss (NOLOAD):\n    {\n        . = ALIGN(4);\n        __corebss_start__ = .;\n        *(.bss.core)\n        . = ALIGN(4);\n        __corebss_end__ = .;\n        *(.corebss*)\n        *(.bss.core.nz)\n        . = ALIGN(4);\n        __ecorebss = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    \n    __HeapBase = .;\n    __HeapLimit = ORIGIN(RAM) + LENGTH(RAM);\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM; stack limit is bottom of stack *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n}\n\n","old_contents":"\/**\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n * \n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\n \n\/* Linker script for STM32F401 when running code from SRAM *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __coredata_start__\n *   __coredata_end__\n *   __corebss_start__\n *   __corebss_end__\n *   __ecoredata\n *   __ecorebss\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        __vector_tbl_reloc__ = .;\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n\n    __exidx_end = .;\n\n    . = ALIGN(8);\n    __etext = .;\n\n    .coredata : AT (__etext)\n    {\n        __coredata_start__ = .;\n        *(.data.core)\n        . = ALIGN(8);\n        __coredata_end__ = .;\n    } > RAM\n\n    __ecoredata = __etext + SIZEOF(.coredata);\n\n    .data : AT (__ecoredata)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .corebss (NOLOAD):\n    {\n        . = ALIGN(4);\n        __corebss_start__ = .;\n        *(.bss.core)\n        . = ALIGN(4);\n        __corebss_end__ = .;\n        *(.corebss*)\n        *(.bss.core.nz)\n        . = ALIGN(4);\n        __ecorebss = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    \n    __HeapBase = .;\n    __HeapLimit = ORIGIN(RAM) + LENGTH(RAM);\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM; stack limit is bottom of stack *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"34d94036690a0b3b9c225a5eb3a2291e16f6fb92","subject":"Separates .rodata section in two-seg.ld","message":"Separates .rodata section in two-seg.ld\n\nSigned-off-by: Piyush Itankar <4a4ff89c9da587217bb1deb9fbe4ebeb84f02484@google.com>\nChange-Id: I9196ea846319f7757b84c487fcc558e686038fc6\n","repos":"google\/esh,google\/esh","old_file":"shell\/scatter\/two-seg.ld","new_file":"shell\/scatter\/two-seg.ld","new_contents":"\/**\n * Copyright 2022 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n **\/\n\nMEMORY\n{\n    \/**\n     * Use the SRAM base and Size provided by the user in the Makefile\n     * __RAM_BASE__ and __RAM_SIZE__ will be dynamically replaced during the build.\n     *\/\n    ROM (rx) : ORIGIN = __ROM_BASE__, LENGTH = __ROM_SIZE__\n    RAM (rwx) : ORIGIN = __RAM_BASE__, LENGTH = __RAM_SIZE__\n}\n\nSECTIONS\n{\n    .text : {\n        _text = .;\n\n        *(.init*)\n        *(.text*)\n\n        _etext = .;\n    } > ROM AT> ROM\n\n    .data : {\n        _data = .;\n\n        . = ALIGN(8);\n        *(.data*)\n\n        _edata = .;\n    } > RAM AT> ROM\n\n    .rodata : {\n        \/* start: Command table for the shell *\/\n        . = ALIGN(8);\n        __CMD_TABLE_START__ = .;\n        *(.cmd_list*)\n        __AUTO_TABLE_START__ = .;\n        *(.auto_list*)\n        *(.cmd_end*)\n        \/* end: Command table for the shell *\/\n\n        *(.rodata*)\n    } > ROM AT> ROM\n\n    .bss : {\n        _bss = .;\n        . = ALIGN(8);\n        *(.bss*)\n        _ebss = .;\n    } > RAM AT> RAM\n\n    PROVIDE(_STACK_TOP_ = ORIGIN(RAM) + LENGTH(RAM) - 4);\n}\n","old_contents":"\/**\n * Copyright 2022 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n **\/\n\nMEMORY\n{\n    \/**\n     * Use the SRAM base and Size provided by the user in the Makefile\n     * __RAM_BASE__ and __RAM_SIZE__ will be dynamically replaced during the build.\n     *\/\n    ROM (rx) : ORIGIN = __ROM_BASE__, LENGTH = __ROM_SIZE__\n    RAM (rwx) : ORIGIN = __RAM_BASE__, LENGTH = __RAM_SIZE__\n}\n\nSECTIONS\n{\n    .text : {\n        _text = .;\n\n        *(.init*)\n        *(.text*)\n\n        \/* start: Command table for the shell *\/\n        . = ALIGN(8);\n        __CMD_TABLE_START__ = .;\n        *(.cmd_list*)\n        __AUTO_TABLE_START__ = .;\n        *(.auto_list*)\n        *(.cmd_end*)\n        \/* end: Command table for the shell *\/\n\n        *(.rodata*)\n        _etext = .;\n    } > ROM AT> ROM\n\n    .data : {\n        _data = .;\n        . = ALIGN(8);\n        *(.data*)\n        _edata = .;\n    } > RAM AT> ROM\n\n    .bss : {\n        _bss = .;\n        . = ALIGN(8);\n        *(.bss*)\n        _ebss = .;\n    } > RAM AT> RAM\n\n    PROVIDE(_STACK_TOP_ = ORIGIN(RAM) + LENGTH(RAM) - 4);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bb077a3d82dcf9890cbccab4df69e54392f13bf3","subject":"soc: esp32c3: linker changes to enable newlibc and cpp","message":"soc: esp32c3: linker changes to enable newlibc and cpp\n\nAdds linker changes to enable cpp and newlibc code.\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr","old_file":"soc\/riscv\/esp32c3\/linker.ld","new_file":"soc\/riscv\/esp32c3\/linker.ld","new_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32c3 platform.\n *\/\n\n#include <zephyr\/devicetree.h>\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg\n#define RODATA_REGION drom0_0_seg\n#define IRAM_REGION  iram0_0_seg\n#define FLASH_CODE_REGION irom0_0_seg\n\n#define ROMABLE_REGION ROM\n\n#define SRAM_IRAM_START     0x4037C000\n#define SRAM_DRAM_START     0x3FC7C000\n#define ICACHE_SIZE         0x4000 \/* ICache size is fixed to 16KB on ESP32-C3 *\/\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n#ifdef CONFIG_FLASH_SIZE\n#define FLASH_SIZE CONFIG_FLASH_SIZE\n#else\n#define FLASH_SIZE 0x400000\n#endif\n\n#ifdef CONFIG_BOOTLOADER_ESP_IDF\n#define IROM_SEG_ORG 0x42000020\n#define IROM_SEG_LEN (FLASH_SIZE-0x20)\n#define IROM_SEG_ALIGN 0x4\n#else\n#define IROM_SEG_ORG 0x42000000\n#define IROM_SEG_LEN FLASH_SIZE\n#define IROM_SEG_ALIGN 0x10000\n#endif\n\n\/* Global symbols required for espressif hal build *\/\nMEMORY\n{\n  mcuboot_hdr (RX): org = 0x0, len = 0x20\n  metadata (RX): org = 0x20, len = 0x20\n  ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40\n\n  iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN\n\n  drom0_0_seg (R) : org = 0x3C000040, len = FLASH_SIZE - 0x40\n  dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE\n\n  rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000\n\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\n\/*  Default entry point:  *\/\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n  \/* Reserve space for MCUboot header in the binary *\/\n  .mcuboot_header :\n  {\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n  } > mcuboot_hdr\n  .metadata :\n  {\n    \/* Magic byte for load header *\/\n    LONG(0xace637d3)\n\n    \/* Application entry point address *\/\n    KEEP(*(.entry_addr))\n\n    \/* IRAM metadata:\n     * - Destination address (VMA) for IRAM region\n     * - Flash offset (LMA) for start of IRAM region\n     * - Size of IRAM region\n     *\/\n    LONG(ADDR(.iram0.text))\n    LONG(LOADADDR(.iram0.text))\n    LONG(SIZEOF(.iram0.text))\n\n    \/* DRAM metadata:\n     * - Destination address (VMA) for DRAM region\n     * - Flash offset (LMA) for start of DRAM region\n     * - Size of DRAM region\n     *\/\n    LONG(ADDR(.dram0.data))\n    LONG(LOADADDR(.dram0.data))\n    LONG(LOADADDR(.dummy.dram.data) + SIZEOF(.dummy.dram.data) - LOADADDR(.dram0.data))\n  } > metadata\n\n#include <zephyr\/linker\/rel-sections.ld>\n  _image_drom_start = LOADADDR(_RODATA_SECTION_NAME);\n  _image_drom_size = LOADADDR(_RODATA_SECTION_NAME) + SIZEOF(_RODATA_SECTION_NAME) - _image_drom_start;\n  _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);\n\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    *(.rodata_desc .rodata_desc.*)\n    *(.rodata_custom_desc .rodata_custom_desc.*)\n\n    __rodata_region_start = .;\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    . = ALIGN(4);\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libdrivers__flash.a:spi_flash_rom_patch.*) .rodata)\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libdrivers__flash.a:spi_flash_rom_patch.*) .rodata.*)\n\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n\n    \/* C++ exception handlers table: *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    __rodata_region_end = .;\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    *(.srodata)\n    *(.srodata.*)\n    *(.rodata)\n    *(.rodata.*)\n    *(.rodata_wlog)\n    *(.rodata_wlog*)\n    _thread_local_end = ABSOLUTE(.);\n    _rodata_reserved_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)\n\n  \/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA.\n   * Executing directly from LMA is not possible. *\/\n  #pragma push_macro(\"GROUP_ROM_LINK_IN\")\n  #undef GROUP_ROM_LINK_IN\n  #define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion\n  #include <zephyr\/linker\/common-rom\/common-rom-cpp.ld>\n  #include <zephyr\/linker\/common-rom\/common-rom-kernel-devices.ld>\n  #include <zephyr\/linker\/common-rom\/common-rom-net.ld>\n  #include <zephyr\/linker\/common-rom\/common-rom-bt.ld>\n  #include <zephyr\/linker\/common-rom\/common-rom-debug.ld>\n  #include <zephyr\/linker\/common-rom\/common-rom-misc.ld>\n  #pragma pop_macro(\"GROUP_ROM_LINK_IN\")\n\n  .iram0.text : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _iram_start = ABSOLUTE(.);\n    _init_start = ABSOLUTE(.);\n\n    KEEP(*(.exception_vectors.text));\n    . = ALIGN(256);\n\n    _invalid_pc_placeholder = ABSOLUTE(.);\n\n    _iram_text_start = ABSOLUTE(.);\n\n    KEEP(*(.exception.entry*)); \/* contains __irq_wrapper *\/\n    *(.exception.other*)\n    . = ALIGN(4);\n\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    . = ALIGN(4);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:loader.*(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n    . = ALIGN(4);\n    _init_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  .dram0.dummy (NOLOAD):\n  {\n    \/**\n    * This section is required to skip .iram0.text area because iram0_0_seg and\n    * dram0_0_seg reflect the same address space on different buses.\n    *\/\n    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN(4);\n    *(.noinit)\n    *(.noinit.*)\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  #include <snippets-sections.ld>\n\n  .dram0.data :\n  {\n    . = ALIGN(4);\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n#ifdef CONFIG_RISCV_GP\n    __global_pointer$ = . + 0x800;\n#endif \/* CONFIG_RISCV_GP *\/\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n\n    \/* All dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libzephyr.a:loader.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n    *libdrivers__flash.a:spi_flash_rom_patch.*(.rodata  .rodata.*)\n\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    . = ALIGN(4);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  #include <zephyr\/linker\/cplusplus-rom.ld>\n  #include <zephyr\/linker\/thread-local-storage.ld>\n  #include <snippets-data-sections.ld>\n  #include <zephyr\/linker\/common-ram.ld>\n  #include <snippets-ram-sections.ld>\n  #include <zephyr\/linker\/cplusplus-ram.ld>\n\n  \/* logging sections should be placed in RAM area to avoid flash cache disabled issues *\/\n  #pragma push_macro(\"GROUP_ROM_LINK_IN\")\n  #undef GROUP_ROM_LINK_IN\n  #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN\n  #include <zephyr\/linker\/common-rom\/common-rom-logging.ld>\n  #pragma pop_macro(\"GROUP_ROM_LINK_IN\")\n\n  .dummy.dram.data :\n  {\n    . = ALIGN(4);\n    #include <snippets-rwdata.ld>\n    _end = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  .iram0.text_end (NOLOAD) :\n  {\n    \/* C3 memprot requires 512 B alignment for split lines *\/\n    . = ALIGN (16);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .iram0.data :\n  {\n    . = ALIGN(16);\n    *(.iram.data)\n    *(.iram.data*)\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  .iram0.bss (NOLOAD) :\n  {\n    . = ALIGN(16);\n    *(.iram.bss)\n    *(.iram.bss*)\n\n    . = ALIGN(16);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  _image_irom_start = LOADADDR(.flash.text);\n  _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;\n  _image_irom_vaddr = ADDR(.flash.text);\n\n  .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN)\n  {\n    . = SIZEOF(_RODATA_SECTION_NAME);\n    . = ALIGN(0x10000) + 0x20;\n    _rodata_reserved_start = .;\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  .flash.text : ALIGN(IROM_SEG_ALIGN)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/** CPU will try to prefetch up to 16 bytes of\n      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow\n      * safe access to up to 16 bytes after the last real instruction, add\n      * dummy bytes to ensure this\n      *\/\n    . += 16;\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/**\n     * Similar to _iram_start, this symbol goes here so it is\n     * resolved by addr2line in preference to the first symbol in\n     * the flash.text segment.\n     *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)\n\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)\n\n  \/* This section is required to skip rtc.text area because the text and\n   * data segments reflect the same address space on different buses.\n   *\/\n  .rtc.dummy (NOLOAD):\n  {\n    . = SIZEOF(.rtc.text);\n  } GROUP_LINK_IN(rtc_iram_seg)\n\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)\n\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(rtc_iram_seg)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n\n#include <zephyr\/linker\/debug-sections.ld>\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  SECTION_PROLOGUE(.riscv.attributes, 0,)\n    {\n    KEEP(*(.riscv.attributes))\n    KEEP(*(.gnu.attributes))\n    }\n}\n","old_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32c3 platform.\n *\/\n\n#include <zephyr\/devicetree.h>\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg\n#define RODATA_REGION drom0_0_seg\n#define IRAM_REGION  iram0_0_seg\n#define FLASH_CODE_REGION irom0_0_seg\n\n#define ROMABLE_REGION ROM\n\n#define SRAM_IRAM_START     0x4037C000\n#define SRAM_DRAM_START     0x3FC7C000\n#define ICACHE_SIZE         0x4000 \/* ICache size is fixed to 16KB on ESP32-C3 *\/\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n#ifdef CONFIG_FLASH_SIZE\n#define FLASH_SIZE CONFIG_FLASH_SIZE\n#else\n#define FLASH_SIZE 0x400000\n#endif\n\n#ifdef CONFIG_BOOTLOADER_ESP_IDF\n#define IROM_SEG_ORG 0x42000020\n#define IROM_SEG_LEN (FLASH_SIZE-0x20)\n#define IROM_SEG_ALIGN 0x4\n#else\n#define IROM_SEG_ORG 0x42000000\n#define IROM_SEG_LEN FLASH_SIZE\n#define IROM_SEG_ALIGN 0x10000\n#endif\n\n\/* Global symbols required for espressif hal build *\/\nMEMORY\n{\n  mcuboot_hdr (RX): org = 0x0, len = 0x20\n  metadata (RX): org = 0x20, len = 0x20\n  ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40\n\n  iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN\n\n  drom0_0_seg (R) : org = 0x3C000040, len = FLASH_SIZE - 0x40\n  dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE\n\n  rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000\n\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\n\/*  Default entry point:  *\/\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n  \/* Reserve space for MCUboot header in the binary *\/\n  .mcuboot_header :\n  {\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n  } > mcuboot_hdr\n  .metadata :\n  {\n    \/* Magic byte for load header *\/\n    LONG(0xace637d3)\n\n    \/* Application entry point address *\/\n    KEEP(*(.entry_addr))\n\n    \/* IRAM metadata:\n     * - Destination address (VMA) for IRAM region\n     * - Flash offset (LMA) for start of IRAM region\n     * - Size of IRAM region\n     *\/\n    LONG(ADDR(.iram0.text))\n    LONG(LOADADDR(.iram0.text))\n    LONG(SIZEOF(.iram0.text))\n\n    \/* DRAM metadata:\n     * - Destination address (VMA) for DRAM region\n     * - Flash offset (LMA) for start of DRAM region\n     * - Size of DRAM region\n     *\/\n    LONG(ADDR(.dram0.data))\n    LONG(LOADADDR(.dram0.data))\n    LONG(LOADADDR(.dummy.dram.data) + SIZEOF(.dummy.dram.data) - LOADADDR(.dram0.data))\n  } > metadata\n\n#include <zephyr\/linker\/rel-sections.ld>\n  _image_drom_start = LOADADDR(_RODATA_SECTION_NAME);\n  _image_drom_size = LOADADDR(_RODATA_SECTION_NAME) + SIZEOF(_RODATA_SECTION_NAME) - _image_drom_start;\n  _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);\n\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    *(.rodata_desc .rodata_desc.*)\n    *(.rodata_custom_desc .rodata_custom_desc.*)\n\n    __rodata_region_start = .;\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    . = ALIGN(4);\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libdrivers__flash.a:spi_flash_rom_patch.*) .rodata)\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libdrivers__flash.a:spi_flash_rom_patch.*) .rodata.*)\n\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*\n     * C++ constructor and destructor tables\n     * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.\n     *\n     * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.\n     * But the init_priority sections will be sorted for iteration in ascending order during startup.\n     * The rest of the init_array sections is sorted for iteration in descending order during startup, however.\n     * Hence a different section is generated for the init_priority functions which is iterated in\n     * ascending order during startup. The corresponding code can be found in startup.c.\n     *\/\n    __init_priority_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))\n    __init_priority_array_end = ABSOLUTE(.);\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/* C++ exception handlers table: *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    __rodata_region_end = .;\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    *(.srodata)\n    *(\".srodata.*\")\n    *(.rodata)\n    *(.rodata.*)\n    *(.rodata_wlog)\n    *(.rodata_wlog*)\n    _thread_local_end = ABSOLUTE(.);\n    _rodata_reserved_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)\n\n  \/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA.\n   * Executing directly from LMA is not possible. *\/\n  #pragma push_macro(\"GROUP_ROM_LINK_IN\")\n  #undef GROUP_ROM_LINK_IN\n  #define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion\n  #include \"linker\/common-rom\/common-rom-kernel-devices.ld\"\n  #include \"linker\/common-rom\/common-rom-cpp.ld\"\n  #include \"linker\/common-rom\/common-rom-net.ld\"\n  #include \"linker\/common-rom\/common-rom-bt.ld\"\n  #include \"linker\/common-rom\/common-rom-debug.ld\"\n  #include \"linker\/common-rom\/common-rom-misc.ld\"\n  #pragma pop_macro(\"GROUP_ROM_LINK_IN\")\n\n  .iram0.text : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _iram_start = ABSOLUTE(.);\n    _init_start = ABSOLUTE(.);\n\n    KEEP(*(.exception_vectors.text));\n    . = ALIGN(256);\n\n    _invalid_pc_placeholder = ABSOLUTE(.);\n\n    _iram_text_start = ABSOLUTE(.);\n\n    KEEP(*(.exception.entry*)); \/* contains __irq_wrapper *\/\n    *(.exception.other*)\n    . = ALIGN(4);\n\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    . = ALIGN(4);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:loader.*(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n    . = ALIGN(4);\n    _init_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  .dram0.dummy (NOLOAD):\n  {\n    \/**\n    * This section is required to skip .iram0.text area because iram0_0_seg and\n    * dram0_0_seg reflect the same address space on different buses.\n    *\/\n    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN(4);\n    *(.noinit)\n    *(.noinit.*)\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  #include <snippets-sections.ld>\n\n  .dram0.data :\n  {\n    . = ALIGN(4);\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n#ifdef CONFIG_RISCV_GP\n    __global_pointer$ = . + 0x800;\n#endif \/* CONFIG_RISCV_GP *\/\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n\n    \/* All dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libzephyr.a:loader.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n    *libdrivers__flash.a:spi_flash_rom_patch.*(.rodata  .rodata.*)\n\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    . = ALIGN(4);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  #include <snippets-data-sections.ld>\n  #include <zephyr\/linker\/common-ram.ld>\n  #include <snippets-ram-sections.ld>\n\n  \/* logging sections should be placed in RAM area to avoid flash cache disabled issues *\/\n  #pragma push_macro(\"GROUP_ROM_LINK_IN\")\n  #undef GROUP_ROM_LINK_IN\n  #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN\n  #include \"linker\/common-rom\/common-rom-logging.ld\"\n  #pragma pop_macro(\"GROUP_ROM_LINK_IN\")\n\n  .dummy.dram.data :\n  {\n    . = ALIGN(4);\n    #include <snippets-rwdata.ld>\n    _data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  .iram0.text_end (NOLOAD) :\n  {\n    \/* C3 memprot requires 512 B alignment for split lines *\/\n    . = ALIGN (16);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .iram0.data :\n  {\n    . = ALIGN(16);\n    *(.iram.data)\n    *(.iram.data*)\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  .iram0.bss (NOLOAD) :\n  {\n    . = ALIGN(16);\n    *(.iram.bss)\n    *(.iram.bss*)\n\n    . = ALIGN(16);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  _image_irom_start = LOADADDR(.flash.text);\n  _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;\n  _image_irom_vaddr = ADDR(.flash.text);\n\n  .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN)\n  {\n    . = SIZEOF(_RODATA_SECTION_NAME);\n    . = ALIGN(0x10000) + 0x20;\n    _rodata_reserved_start = .;\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  .flash.text : ALIGN(IROM_SEG_ALIGN)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/** CPU will try to prefetch up to 16 bytes of\n      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow\n      * safe access to up to 16 bytes after the last real instruction, add\n      * dummy bytes to ensure this\n      *\/\n    . += 16;\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/**\n     * Similar to _iram_start, this symbol goes here so it is\n     * resolved by addr2line in preference to the first symbol in\n     * the flash.text segment.\n     *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)\n\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)\n\n  \/* This section is required to skip rtc.text area because the text and\n   * data segments reflect the same address space on different buses.\n   *\/\n  .rtc.dummy (NOLOAD):\n  {\n    . = SIZEOF(.rtc.text);\n  } GROUP_LINK_IN(rtc_iram_seg)\n\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)\n\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(rtc_iram_seg)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n\n#include <zephyr\/linker\/debug-sections.ld>\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  SECTION_PROLOGUE(.riscv.attributes, 0,)\n    {\n    KEEP(*(.riscv.attributes))\n    KEEP(*(.gnu.attributes))\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5399d4e301ebc502ec49895ca3db893a24582e5c","subject":"Added a few additional sections to the linker script and reorganized the text section","message":"Added a few additional sections to the linker script and reorganized the text section\n","repos":"StevenLaabs\/PeakOS,StevenLaabs\/PeakOS","old_file":"kernel\/arch\/i386\/linker.ld","new_file":"kernel\/arch\/i386\/linker.ld","new_contents":"ENTRY(_boot_start)\n\nSECTIONS {\n\t. = 0x1M;\n\n\t.text ALIGN(4k) : {\n\t\t\/* Put multiboot header at the beginning of memory so it is recognized *\/\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* .data is Read-write data that is initialized *\/\n\t.data ALIGN(4k) : {\n\t\t*(.data)\n\t}\t\n\n\t\/* .bss is Read-write data that is uninitialized and stack *\/\n\t.bss ALIGN(4k) : {\n\t\t*(.bss)\n\t}\n}\n","old_contents":"ENTRY(_boot_start)\n\nSECTIONS {\n\t. = 0x100000;\n\n\t.multiboot : {\n\t\t*(.multiboot)\n\t}\n\n\t.text : {\n\t\t*(.text)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b0d73a252286788107aabb7941960443a525c2a2","subject":"Add comments to boot linker script.","message":"Add comments to boot linker script.\n","repos":"IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core","old_file":"hw\/bsp\/stm32f7discovery\/boot-stm32f7discovery.ld","new_file":"hw\/bsp\/stm32f7discovery\/boot-stm32f7discovery.ld","new_contents":"\/*\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n *\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) :  ORIGIN = 0x08000000, LENGTH = 32K  \/* FLASHAXI_BASE *\/\n  ITCM (rx)  :  ORIGIN = 0x00000000, LENGTH = 16K  \/* RAMITCM_BASE *\/\n  DTCM (rwx) :  ORIGIN = 0x20000000, LENGTH = 64K  \/* RAMDTCM_BASE *\/\n  RAM (rwx)  :  ORIGIN = 0x20020000, LENGTH = 256K \/* SRAM1_BASE *\/\n}\n\n\/* The bootloader does not contain an image header *\/\n_imghdr_size = 0x0;\n","old_contents":"\/*\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n *\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) :  ORIGIN = 0x08000000, LENGTH = 32K\n  ITCM (rx)  :  ORIGIN = 0x00000000, LENGTH = 16K\n  DTCM (rwx) :  ORIGIN = 0x20000000, LENGTH = 128K\n  RAM (rwx)  :  ORIGIN = 0x20020000, LENGTH = 512K\n}\n\n\/* The bootloader does not contain an image header *\/\n_imghdr_size = 0x0;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"49941733c62b58b45bca4f8e4a4a15170b111866","subject":"boards: esp32: linker: move libraries and reserve DRAM regions","message":"boards: esp32: linker: move libraries and reserve DRAM regions\n\nFix issues with restoring symbols from common ld templates\nWorkaround esptool linker sections limit\nMove kernel library into IRAM\nImprove UDP throughput\n\nSigned-off-by: Shubham Kulkarni <1478dde7897089bf180c3c690a61b19b869e8abd@espressif.com>\n","repos":"Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\n\/* Global symbols required for espressif hal build *\/\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( crc32_le = 0x4005cfec );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( esp32_rom_ets_printf = ets_printf );\nPROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *  - Reserve memory region for BT controller library from ROM\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x30000\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#if defined(CONFIG_NET_SOCKETS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_socket_register);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(settings_handler_static);\n    . = ALIGN(4);\n#endif\n\n    . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define ROMABLE_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n#define FLASH_DATA_REGION drom0_0_seg :drom0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\n\/* Global symbols required for espressif hal build *\/\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( esp32_rom_ets_printf = ets_printf );\nPROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x50000\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  SECTION_DATA_PROLOGUE(log_static_section,,)\n  {\n    __log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __log_const_end = .;\n\n    __log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __log_backends_end = .;\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(shell_static_section,,)\n {\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __shell_root_cmds_end = .;\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(FLASH_DATA_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d711e15a8d1da94a7bfad1d150ebb5a3196b6805","subject":"Bump ROM size to 1024k when linking, as it's known to work.","message":"Bump ROM size to 1024k when linking, as it's known to work.\n","repos":"ComputerNerd\/libfxcg-copyleft,Jonimoose\/libfxcg,Jonimoose\/libfxcg,ComputerNerd\/libfxcg-copyleft,Forty-Bot\/libfxcg,Forty-Bot\/libfxcg,Jonimoose\/libfxcg,Forty-Bot\/libfxcg,ComputerNerd\/libfxcg-copyleft,ComputerNerd\/libfxcg-copyleft,Forty-Bot\/libfxcg","old_file":"toolchain\/prizm.ld","new_file":"toolchain\/prizm.ld","new_contents":"OUTPUT_FORMAT(binary)\r\nOUTPUT_ARCH(sh3)\r\n \r\n\/* Entry point.  Not really important here, since doing binary output *\/\r\nENTRY(initialize)\r\n \r\nMEMORY\r\n{\r\n        \/* Loads code at 300000, skips g3a header *\/\r\n        rom (rx) : o = 0x00300000, l = 1024k\r\n        ram (rwx) : o = 0x08100004, l = 64k  \/* pretty safe guess *\/\r\n}\r\n \r\nSECTIONS\r\n{\r\n        \/* Code, in ROM *\/\r\n        .text : {\r\n                *(.pretext)     \/* init stuff *\/\r\n                *(.text)\r\n                *(.text.*)\r\n        } > rom\r\n       \r\n        \/* Read-only data, in ROM *\/\r\n        .rodata : {\r\n                *(.rodata)\r\n                *(.rodata.*)\r\n        } > rom\r\n       \r\n        \/* RW initialized data, VMA in RAM but LMA in ROM *\/\r\n        .data : {\r\n                _datald = LOADADDR(.data) ;\r\n                _sdata = . ;\r\n                *(.data)\r\n                *(.data.*);\r\n                _edata = . ;\r\n        } >ram AT>rom\r\n       \r\n        \/* Uninitialized data (fill with 0), in RAM *\/\r\n        .bss : {\r\n                _bbss = . ;\r\n                *(.bss) *(COMMON);\r\n                _ebss = . ;\r\n        } >ram\r\n}\r\n","old_contents":"OUTPUT_FORMAT(binary)\r\nOUTPUT_ARCH(sh3)\r\n \r\n\/* Entry point.  Not really important here, since doing binary output *\/\r\nENTRY(initialize)\r\n \r\nMEMORY\r\n{\r\n        \/* Loads code at 300000, skips g3a header *\/\r\n        rom (rx) : o = 0x00300000, l = 512k\r\n        ram (rwx) : o = 0x08100004, l = 64k  \/* pretty safe guess *\/\r\n}\r\n \r\nSECTIONS\r\n{\r\n        \/* Code, in ROM *\/\r\n        .text : {\r\n                *(.pretext)     \/* init stuff *\/\r\n                *(.text)\r\n                *(.text.*)\r\n        } > rom\r\n       \r\n        \/* Read-only data, in ROM *\/\r\n        .rodata : {\r\n                *(.rodata)\r\n                *(.rodata.*)\r\n        } > rom\r\n       \r\n        \/* RW initialized data, VMA in RAM but LMA in ROM *\/\r\n        .data : {\r\n                _datald = LOADADDR(.data) ;\r\n                _sdata = . ;\r\n                *(.data)\r\n                *(.data.*);\r\n                _edata = . ;\r\n        } >ram AT>rom\r\n       \r\n        \/* Uninitialized data (fill with 0), in RAM *\/\r\n        .bss : {\r\n                _bbss = . ;\r\n                *(.bss) *(COMMON);\r\n                _ebss = . ;\r\n        } >ram\r\n}","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"046fc62e0243af9cd6a32064fcedb8dc6f8d5b34","subject":"Added flash boundary variables to STM32F334 linker script","message":"Added flash boundary variables to STM32F334 linker script\n","repos":"cvra\/can-bootloader,cvra\/can-bootloader,cvra\/can-bootloader,cvra\/can-bootloader","old_file":"platform\/nucleo-board-stm32f334r8\/linkerscript.ld","new_file":"platform\/nucleo-board-stm32f334r8\/linkerscript.ld","new_contents":"\/*\n * Linker file for the STM32F334R8 microcontroller\n * http:\/\/www.st.com\/en\/microcontrollers\/stm32f334r8.html\n *\n * 64K flash memory, 12K RAM, 4K CCRAM\n * Flash page size: 2K (= 0x800)\n *\n * TODO: Complete section definitions below with definitions for CCRAM \n *\/\n\nMEMORY\n{\n    FLASH_TEXT    (RX) : ORIGIN = 0x08000000, LENGTH = 20K\n    FLASH_CONFIG1 (RX) : ORIGIN = 0x08005000, LENGTH = 2K\n    FLASH_CONFIG2 (RX) : ORIGIN = 0x08005800, LENGTH = 2K\n    FLASH_APP     (RX) : ORIGIN = 0x08006000, LENGTH = 40K\n    RAM          (RWX) : ORIGIN = 0x20000000, LENGTH = 12K\n    CCRAM        (RWX) : ORIGIN = 0x10000000, LENGTH = 4K\n}\n\nREGION_ALIAS(\"REGION_TEXT\",   FLASH_TEXT);\nREGION_ALIAS(\"REGION_RODATA\", FLASH_TEXT);\nREGION_ALIAS(\"REGION_DATA\",   RAM);\nREGION_ALIAS(\"REGION_BSS\",    RAM);\nREGION_ALIAS(\"REGION_NOINIT\", RAM);\n\nEXTERN(vector_table)\n\nENTRY(reset_handler)\n\nSECTIONS\n{\n    \/* flash memory boundaries *\/\n    flash_begin = ORIGIN(FLASH_TEXT);\n    flash_end = ORIGIN(FLASH_APP) + LENGTH(FLASH_APP);\n\n    \/* config flash page *\/\n    config_page1 = ORIGIN(FLASH_CONFIG1);\n    config_page2 = ORIGIN(FLASH_CONFIG2);\n\n    \/* application in flash *\/\n    application_address = ORIGIN(FLASH_APP);\n    application_size = LENGTH(FLASH_APP);\n\n    .text :\n    {\n        *(.vectors) \/* vector_table *\/\n\n        _stext = .;\n\n        CREATE_OBJECT_SYMBOLS\n\n        *(.text .text.*)        \/* Program code *\/\n        *(.gnu.linkonce.t.*)\n\n\n        *(.plt)\n        *(.gnu.warning)\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\n\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _etext = .;\n    } > REGION_TEXT\n\n    .rodata :\n    {\n        . = ALIGN(4);\n        KEEP(*(.rodata.keep .rodata.keep.*))\n        *(.rodata .rodata.*)    \/* Read only data *\/\n        . = ALIGN(4);\n    } > REGION_RODATA\n\n    \/*\n     * .ARM.exidx exception unwinding; mandated by ARM's C++ ABI\n     *\/\n    __exidx_start = .;\n    .ARM.exidx :\n      {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n      } > REGION_RODATA\n    __exidx_end = .;\n\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        _data = _sdata;\n\n        *(.got.plt) *(.got)\n\n        *(.data .data.*)        \/* Data memory *\/\n        *(.gnu.linkonce.d.*)\n\n        . = ALIGN(4);\n        *(.fastrun .fastrun.*)  \/* Functions in RAM *\/\n\n        . = ALIGN(4);\n        _edata = .;\n    } > REGION_DATA AT > REGION_RODATA\n    _ldata = LOADADDR(.data);\n    _data_loadaddr = _ldata;\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n\n        *(.bss .bss.*)          \/* Zero-filled data memory *\/\n        *(.gnu.linkonce.b.*)\n\n        . = ALIGN(4);\n        _ebss = .;\n    } > REGION_BSS\n\n    .noinit :\n    {\n        _snoinit = .;\n        . = ALIGN(4);\n\n        *(.noinit .noinit.*)\n\n        . = ALIGN(4);\n        _enoinit = .;\n    } > REGION_NOINIT\n\n    . = ALIGN(8);\n    _sheap = .;\n    _sstack = .;\n\n    \/* default stack at the end of RAM *\/\n    _eram = ORIGIN(RAM) + LENGTH(RAM);\n    _eheap = _eram;\n    _estack = _eram;\n    _stack = _eram;\n\n    \/*\n     * Debugging sections\n     *\/\n    .stab 0 (NOLOAD) : { *(.stab) }\n    .stabstr 0 (NOLOAD) : { *(.stabstr) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n\n    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n    .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n * Linker file for the STM32F334R8 microcontroller\n * http:\/\/www.st.com\/en\/microcontrollers\/stm32f334r8.html\n *\n * 64K flash memory, 12K RAM, 4K CCRAM\n * Flash page size: 2K (= 0x800)\n *\n * TODO: Complete section definitions below with definitions for CCRAM \n *\/\n\nMEMORY\n{\n    FLASH_TEXT    (RX) : ORIGIN = 0x08000000, LENGTH = 20K\n    FLASH_CONFIG1 (RX) : ORIGIN = 0x08005000, LENGTH = 2K\n    FLASH_CONFIG2 (RX) : ORIGIN = 0x08005800, LENGTH = 2K\n    FLASH_APP     (RX) : ORIGIN = 0x08006000, LENGTH = 40K\n    RAM          (RWX) : ORIGIN = 0x20000000, LENGTH = 12K\n    CCRAM        (RWX) : ORIGIN = 0x10000000, LENGTH = 4K\n}\n\nREGION_ALIAS(\"REGION_TEXT\",   FLASH_TEXT);\nREGION_ALIAS(\"REGION_RODATA\", FLASH_TEXT);\nREGION_ALIAS(\"REGION_DATA\",   RAM);\nREGION_ALIAS(\"REGION_BSS\",    RAM);\nREGION_ALIAS(\"REGION_NOINIT\", RAM);\n\nEXTERN(vector_table)\n\nENTRY(reset_handler)\n\nSECTIONS\n{\n    \/* config flash page *\/\n    config_page1 = ORIGIN(FLASH_CONFIG1);\n    config_page2 = ORIGIN(FLASH_CONFIG2);\n\n    \/* application in flash *\/\n    application_address = ORIGIN(FLASH_APP);\n    application_size = LENGTH(FLASH_APP);\n\n    .text :\n    {\n        *(.vectors) \/* vector_table *\/\n\n        _stext = .;\n\n        CREATE_OBJECT_SYMBOLS\n\n        *(.text .text.*)        \/* Program code *\/\n        *(.gnu.linkonce.t.*)\n\n\n        *(.plt)\n        *(.gnu.warning)\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\n\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _etext = .;\n    } > REGION_TEXT\n\n    .rodata :\n    {\n        . = ALIGN(4);\n        KEEP(*(.rodata.keep .rodata.keep.*))\n        *(.rodata .rodata.*)    \/* Read only data *\/\n        . = ALIGN(4);\n    } > REGION_RODATA\n\n    \/*\n     * .ARM.exidx exception unwinding; mandated by ARM's C++ ABI\n     *\/\n    __exidx_start = .;\n    .ARM.exidx :\n      {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n      } > REGION_RODATA\n    __exidx_end = .;\n\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        _data = _sdata;\n\n        *(.got.plt) *(.got)\n\n        *(.data .data.*)        \/* Data memory *\/\n        *(.gnu.linkonce.d.*)\n\n        . = ALIGN(4);\n        *(.fastrun .fastrun.*)  \/* Functions in RAM *\/\n\n        . = ALIGN(4);\n        _edata = .;\n    } > REGION_DATA AT > REGION_RODATA\n    _ldata = LOADADDR(.data);\n    _data_loadaddr = _ldata;\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n\n        *(.bss .bss.*)          \/* Zero-filled data memory *\/\n        *(.gnu.linkonce.b.*)\n\n        . = ALIGN(4);\n        _ebss = .;\n    } > REGION_BSS\n\n    .noinit :\n    {\n        _snoinit = .;\n        . = ALIGN(4);\n\n        *(.noinit .noinit.*)\n\n        . = ALIGN(4);\n        _enoinit = .;\n    } > REGION_NOINIT\n\n    . = ALIGN(8);\n    _sheap = .;\n    _sstack = .;\n\n    \/* default stack at the end of RAM *\/\n    _eram = ORIGIN(RAM) + LENGTH(RAM);\n    _eheap = _eram;\n    _estack = _eram;\n    _stack = _eram;\n\n    \/*\n     * Debugging sections\n     *\/\n    .stab 0 (NOLOAD) : { *(.stab) }\n    .stabstr 0 (NOLOAD) : { *(.stabstr) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n\n    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n    .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"4846ff83a2bf042837fea49fae29e5ba296bee2c","subject":"chang _estack","message":"chang _estack\n","repos":"abing1991\/myproject,abing1991\/myproject,abing1991\/myproject","old_file":"build\/target\/stm32_flash.ld","new_file":"build\/target\/stm32_flash.ld","new_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F103VB Device with\n**                64KByte FLASH, 20KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the Atollic TrueSTUDIO(R) toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20004000;    \/* end of 20K RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 1024;  \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 64K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 64K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .ARM.attributes : { *(.ARM.attributes) } > FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  PROVIDE ( end = _ebss );\n  PROVIDE ( _end = _ebss );\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n}\n","old_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F103VB Device with\n**                64KByte FLASH, 20KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the Atollic TrueSTUDIO(R) toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20010000;    \/* end of 20K RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 1024;  \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 64K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .ARM.attributes : { *(.ARM.attributes) } > FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  PROVIDE ( end = _ebss );\n  PROVIDE ( _end = _ebss );\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"85479d1523f75b41c1a4cd29c532cbf6f7c8a979","subject":"aarch64: linker: Align end symbols","message":"aarch64: linker: Align end symbols\n\nThe end symbols and especially z_mapped_end must be aligned to the MMU\npage size.\n\nSigned-off-by: Carlo Caione <ca4506c8c654a4ccf75802e86b5d162c1e96f065@baylibre.com>\n","repos":"nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cfa5245b9ff559a2d5226c529d4d60d63acc4b79","subject":"LPC8xx: reduce stack sizes","message":"LPC8xx: reduce stack sizes\n\ngit-svn-id: 30f789d7039adee4ab6dc5f7dbec2df9251e516b@5535 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"os\/ports\/GCC\/ARMCMx\/LPC8xx\/ld\/LPC812.ld","new_file":"os\/ports\/GCC\/ARMCMx\/LPC8xx\/ld\/LPC812.ld","new_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011,2012,2013 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * LPC812 memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0100;\r\n__process_stack_size__  = 0x0100;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x00000000, len = 16k\r\n    ram : org = 0x10000000, len = 4k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nENTRY(ResetHandler)\r\n\r\nSECTIONS\r\n{\r\n    . = 0;\r\n    _text = .;\r\n\r\n    startup : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        KEEP(*(vectors))\r\n    } > flash\r\n\r\n    constructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE(__init_array_end = .);\r\n    } > flash\r\n\r\n    destructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__fini_array_start = .);\r\n        KEEP(*(.fini_array))\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        PROVIDE(__fini_array_end = .);\r\n    } > flash\r\n\r\n    .text : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        *(.text.startup.*)\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n    } > flash\r\n\r\n    .ARM.extab :\r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > flash\r\n\r\n    .ARM.exidx : {\r\n        PROVIDE(__exidx_start = .);\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n        PROVIDE(__exidx_end = .);\r\n     } > flash\r\n\r\n    .eh_frame_hdr :\r\n    {\r\n        *(.eh_frame_hdr)\r\n    } > flash\r\n\r\n    .eh_frame : ONLY_IF_RO\r\n    {\r\n        *(.eh_frame)\r\n    } > flash\r\n    \r\n    .textalign : ONLY_IF_RO\r\n    {\r\n        . = ALIGN(8);\r\n    } > flash\r\n\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .stacks :\r\n    {\r\n        . = ALIGN(8);\r\n        __main_stack_base__ = .;\r\n        . += __main_stack_size__;\r\n        . = ALIGN(8);\r\n        __main_stack_end__ = .;\r\n        __process_stack_base__ = .;\r\n        __main_thread_stack_base__ = .;\r\n        . += __process_stack_size__;\r\n        . = ALIGN(8);\r\n        __process_stack_end__ = .;\r\n        __main_thread_stack_end__ = .;\r\n    } > ram\r\n\r\n    .data :\r\n    {\r\n        . = ALIGN(4);\r\n        PROVIDE(_data = .);\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        PROVIDE(_edata = .);\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        . = ALIGN(4);\r\n        PROVIDE(_bss_start = .);\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        PROVIDE(_bss_end = .);\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__;\r\n","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011,2012,2013 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * LPC812 memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0200;\r\n__process_stack_size__  = 0x0200;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x00000000, len = 16k\r\n    ram : org = 0x10000000, len = 4k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nENTRY(ResetHandler)\r\n\r\nSECTIONS\r\n{\r\n    . = 0;\r\n    _text = .;\r\n\r\n    startup : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        KEEP(*(vectors))\r\n    } > flash\r\n\r\n    constructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE(__init_array_end = .);\r\n    } > flash\r\n\r\n    destructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__fini_array_start = .);\r\n        KEEP(*(.fini_array))\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        PROVIDE(__fini_array_end = .);\r\n    } > flash\r\n\r\n    .text : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        *(.text.startup.*)\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n    } > flash\r\n\r\n    .ARM.extab :\r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > flash\r\n\r\n    .ARM.exidx : {\r\n        PROVIDE(__exidx_start = .);\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n        PROVIDE(__exidx_end = .);\r\n     } > flash\r\n\r\n    .eh_frame_hdr :\r\n    {\r\n        *(.eh_frame_hdr)\r\n    } > flash\r\n\r\n    .eh_frame : ONLY_IF_RO\r\n    {\r\n        *(.eh_frame)\r\n    } > flash\r\n    \r\n    .textalign : ONLY_IF_RO\r\n    {\r\n        . = ALIGN(8);\r\n    } > flash\r\n\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .stacks :\r\n    {\r\n        . = ALIGN(8);\r\n        __main_stack_base__ = .;\r\n        . += __main_stack_size__;\r\n        . = ALIGN(8);\r\n        __main_stack_end__ = .;\r\n        __process_stack_base__ = .;\r\n        __main_thread_stack_base__ = .;\r\n        . += __process_stack_size__;\r\n        . = ALIGN(8);\r\n        __process_stack_end__ = .;\r\n        __main_thread_stack_end__ = .;\r\n    } > ram\r\n\r\n    .data :\r\n    {\r\n        . = ALIGN(4);\r\n        PROVIDE(_data = .);\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        PROVIDE(_edata = .);\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        . = ALIGN(4);\r\n        PROVIDE(_bss_start = .);\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        PROVIDE(_bss_end = .);\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__;\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bb11776e30a9f97ca807aa38a6eeeba5a7192f44","subject":"Hide two inherited symbols with the version script.","message":"Hide two inherited symbols with the version script.\n\nWe inherit facilitynames and prioritynames from syslog.h, but they\nshould not be exported by us.\n\nSigned-off-by: Gergely Nagy <6780fac3b38619ac20422286e4110a70dbba2203@balabit.hu>\n","repos":"deirf\/libumberlog","old_file":"lib\/libcee-syslog.ld","new_file":"lib\/libcee-syslog.ld","new_contents":"LIBCEE_SYSLOG_0.1.0 {\n\tglobal:\n        # Our own symbols\n          cee_format;\n          cee_vformat;\n          cee_syslog;\n          cee_vsyslog;\n          cee_legacy_syslog;\n          cee_legacy_vsyslog;\n          cee_openlog;\n          cee_setlogmask;\n        # Overrides\n          syslog;\n          vsyslog;\n          openlog;\n          setlogmask;\n\n\tlocal:\n        # Inherited from elsewhere, but should not be exported\n          facilitynames;\n          prioritynames;\n};\n","old_contents":"LIBCEE_SYSLOG_0.1.0 {\n\tglobal:\n        # Our own symbols\n          cee_format;\n          cee_vformat;\n          cee_syslog;\n          cee_vsyslog;\n          cee_legacy_syslog;\n          cee_legacy_vsyslog;\n          cee_openlog;\n          cee_setlogmask;\n        # Overrides\n          syslog;\n          vsyslog;\n          openlog;\n          setlogmask;\n};\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"55967c433d9891cd21cac745c037ac38f9df3088","subject":"Fix linker script's boot size to match bsp.yml","message":"Fix linker script's boot size to match bsp.yml\n","repos":"andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core","old_file":"hw\/bsp\/stm32f4discovery\/boot-stm32f4discovery.ld","new_file":"hw\/bsp\/stm32f4discovery\/boot-stm32f4discovery.ld","new_contents":"\/*\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n *\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) :  ORIGIN = 0x08000000, LENGTH = 16K\n  CCM (rwx) :   ORIGIN = 0x10000000, LENGTH = 64K\n  RAM (rwx) :   ORIGIN = 0x20000000, LENGTH = 128K\n}\n\n\/* The bootloader does not contain an image header *\/\n_imghdr_size = 0x0;\n","old_contents":"\/*\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n *\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K\n  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K\n}\n\n\/* The bootloader does not contain an image header *\/\n_imghdr_size = 0x0;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"db1b6772592b436ab7bcaaa18493123e3af6d6d3","subject":"Temp stack was misaligned by 1 byte(!?)","message":"Temp stack was misaligned by 1 byte(!?)\n","repos":"stelfer\/nubbin,stelfer\/nubbin","old_file":"kernel\/asm\/os-image.elf_x86_64.ld","new_file":"kernel\/asm\/os-image.elf_x86_64.ld","new_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nboot_paddr   \t   = 0x007c00;\t\t\/* boot offset *\/\nkernel_paddr       = 0x100000;\nkernel_vaddr_off   = 0xffffffff00000000;\nkernel_vaddr \t   = kernel_vaddr_off + kernel_paddr;\nkernel_pos   \t   = 0x001000;\t\t\/* physical position in output *\/\nkernel_stack_paddr = 0xa00000;\nkernel_size \t   = SIZEOF(.kernel);\nuser_vaddr \t   = 0x600000;\nuser_size\t   = SIZEOF(.user);\nuser_pos \t   = kernel_pos + _user_start;\nkdata_base\t   = 0x00200000;\nidt_paddr\t   = 0x00201000;\npercpu_paddr\t   = 0x00202000;\npercpu_tbl_paddr   = 0x00202000;\ngdt_paddr \t   = 0x00203000;\npage_table_paddr   = 0x00400000;\nuser_paddr\t   = 0x00600000;\n\ncpu_stack_size     = 0x400;\n\nSECTIONS\n{\n\t.boot-setup boot_paddr :\n\t{\n\t\t*(.boot)\n\t\tsetup_pos = .;\n\t\t*(.setup)\n\t}\n\n\t.kernel kernel_vaddr : AT(boot_paddr + kernel_pos)\n\t{\n\t\t*.ko(.text)\n\t\t*.ko(.data*)\n\t\t*.ko(.rodata*)\n\t\t*.ko(COMMON*)\n\t\t*.ko(.bss*)\n\t\t\/*\n\t\t * We need to align the start of user to 512 so that we can load\n\t\t * it cleanly as an ATA LSB \n\t\t *\/\n\t\t_user_start = ALIGN(512) - kernel_vaddr;\n\t}\n\n\t.user user_vaddr : AT(LOADADDR(.kernel) + _user_start)\n\t{\n\t\t*.o(.text)\n\t\t*.o(.data*)\n\t\t*.o(.rodata*)\n\t\t*.o(COMMON*)\n\t\t*.o(.bss*)\n\t}\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.eh_frame)\n\t\t*(.comment)\n\t}\n}\n","old_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nboot_paddr   \t   = 0x007c00;\t\t\/* boot offset *\/\nkernel_paddr       = 0x100000;\nkernel_vaddr_off   = 0xffffffff00000000;\nkernel_vaddr \t   = kernel_vaddr_off + kernel_paddr;\nkernel_pos   \t   = 0x001000;\t\t\/* physical position in output *\/\nkernel_stack_paddr = 0x009fffff;\nkernel_size \t   = SIZEOF(.kernel);\nuser_vaddr \t   = 0x600000;\nuser_size\t   = SIZEOF(.user);\nuser_pos \t   = kernel_pos + _user_start;\nkdata_base\t   = 0x00200000;\nidt_paddr\t   = 0x00201000;\npercpu_paddr\t   = 0x00202000;\npercpu_tbl_paddr   = 0x00202000;\ngdt_paddr \t   = 0x00203000;\npage_table_paddr   = 0x00400000;\nuser_paddr\t   = 0x00600000;\n\ncpu_stack_size     = 0x400;\n\nSECTIONS\n{\n\t.boot-setup boot_paddr :\n\t{\n\t\t*(.boot)\n\t\tsetup_pos = .;\n\t\t*(.setup)\n\t}\n\n\t.kernel kernel_vaddr : AT(boot_paddr + kernel_pos)\n\t{\n\t\t*.ko(.text)\n\t\t*.ko(.data*)\n\t\t*.ko(.rodata*)\n\t\t*.ko(COMMON*)\n\t\t*.ko(.bss*)\n\t\t\/*\n\t\t * We need to align the start of user to 512 so that we can load\n\t\t * it cleanly as an ATA LSB \n\t\t *\/\n\t\t_user_start = ALIGN(512) - kernel_vaddr;\n\t}\n\n\t.user user_vaddr : AT(LOADADDR(.kernel) + _user_start)\n\t{\n\t\t*.o(.text)\n\t\t*.o(.data*)\n\t\t*.o(.rodata*)\n\t\t*.o(COMMON*)\n\t\t*.o(.bss*)\n\t}\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.eh_frame)\n\t\t*(.comment)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"320d574eddfff821090cbd3bfe0589519c017ba7","subject":"Updated link.ld to fix tabbing + add stuff for tests","message":"Updated link.ld to fix tabbing + add stuff for tests\n","repos":"duckinator\/dux,duckinator\/dux,duckinator\/dux","old_file":"src\/metodo\/boot\/i386\/link.ld","new_file":"src\/metodo\/boot\/i386\/link.ld","new_contents":"ENTRY(_start)\n\nSECTIONS {\n\t. = 0x100000;\n\tstart = .;\n\n\t.debug_info : {\n\t\tdebug_info_start = .;\n\t\t*(.debug_info)\n\t\tdebug_info_end = .;\n\t}\n\n\t.text : ALIGN (0x1000) {\n\t\t*(.mboot)\n\t\t*(.text)\n\t}\n\n\t.rodata ALIGN (0x1000) : {\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN (0x1000) : {\n\t\t*(.data)\n\t\tstart_initial_tests = .;\n\t\t*(initial_tests)\n\t\tend_initial_tests = .;\n\t\tstart_other_tests = .;\n\t\t*(other_tests*)\n\t\tend_other_tests = .;\n\t}\n\n\t.bss ALIGN (0x1000) : {\n\t\tsbss = .;\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\tebss = .;\n\t}\n\n\tend = .;\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS {\n\t. = 0x100000;\n\tstart = .;\n\n  .debug_info : {\n    debug_info_start = .;\n    *(.debug_info)\n    debug_info_end = .;\n  }\n\n\t.text : ALIGN (0x1000) {\n\t\t*(.mboot)\n\t\t*(.text)\n\t}\n\n\t.rodata ALIGN (0x1000) : {\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN (0x1000) : {\n\t\t*(.data)\n\t}\n\n\t.bss ALIGN (0x1000) : {\n\t\tsbss = .;\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\tebss = .;\n\t}\n\n\tend = .;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b0563b6f4a8a928edcb8ce8a13a7e0043aebaa62","subject":"linker: make _sram_origin lowercase","message":"linker: make _sram_origin lowercase\n\nCo-authored-by: Pat Pannuto <6364fafe2fb638c2c195524856b7e850805ec613@gmail.com>","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to\n\t\t * mark the first address in the SRAM memory. Since ELF files do\n\t\t * not really need to specify this address as they only care about\n\t\t * loading into flash, we need to manually mark this address for\n\t\t * elf2tab. elf2tab will use it to add a fixed address header in the\n\t\t * TBF header if needed.\n\t\t *\/\n\t    _sram_origin = .;\n\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to\n\t\t * mark the first address in the SRAM memory. Since ELF files do\n\t\t * not really need to specify this address as they only care about\n\t\t * loading into flash, we need to manually mark this address for\n\t\t * elf2tab. elf2tab will use it to add a fixed address header in the\n\t\t * TBF header if needed.\n\t\t *\/\n\t    _SRAM_ORIGIN = .;\n\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"741672f6422150657aa2533483c592d0c8feddca","subject":"move to libm to flash in case of future use","message":"move to libm to flash in case of future use\n","repos":"devicehive\/esp8266-firmware,devicehive\/esp8266-firmware,devicehive\/esp8266-firmware,devicehive\/esp8266-firmware,devicehive\/esp8266-firmware","old_file":"firmware-src\/devicehive.ld","new_file":"firmware-src\/devicehive.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40210000, len = 0x58000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libmbedtls.a:(.literal .text .literal.* .text.*)\n\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/sdk\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40210000, len = 0x58000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    *libmbedtls.a:(.literal .text .literal.* .text.*)\n\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/sdk\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ef50545808afbe7a6958cf2843669a5ec1ad3190","subject":"arch: arm: cortex_r: Add userspace support for non-XIP builds","message":"arch: arm: cortex_r: Add userspace support for non-XIP builds\n\nWhen running non-XIP, userspace threads need to be able to read .text in\norder to execute code.  Cortex-R needs to setup an MPU entry to allow\nthis, but it must be aligned to a power of 2.  The linker scripts for\nother archs follow this same pattern of aligning the location counter,\nbut outside of an input section.  The linker ignores this and places the\nnext input section at the LMA of the end of the previous input section.\nAvoid this problem by make RODATA the last ROM section.  The MPU_ALIGN\ncan be moved inside the RODATA input section and correctly pad the\nentire ROM section out to a power of 2 boundary.\n\n_image_rom_end_order contains the power of 2 alignment which allow the\nsoc to set the MPU configuration statically based on the size of the ROM\nsections instead of having to do it dynamically.\n\nSigned-off-by: Bradley Bolen <a46f022a58b40f08f87b914d58da7dec46dba40c@lexmark.com>\n","repos":"galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_a_r\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_a_r\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A and Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n    _image_rom_start = ROM_ADDR;\n#else\n    _image_rom_start = RAM_ADDR;\n#endif\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n#include <linker\/cplusplus-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n\n        \/*\n         * RODATA must be the last section so that the size of the entire read\n         * only area will be filled to a power of 2.\n         *\/\n        MPU_ALIGN(ABSOLUTE(.) - _image_rom_start);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_end = .;\n    _image_rom_end = .;\n    _image_rom_end_order = (LOG2CEIL(_image_rom_end) - 1) << 1;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A and Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    MPU_ALIGN(_image_rodata_end -_image_rom_start);\n    _image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c64663265dd3b43ec5d952d99b3f6ec474fdcd2d","subject":"Stack location is pinned to the top of RAM.  Reduce RAM footprint.","message":"Stack location is pinned to the top of RAM.  Reduce RAM footprint.","repos":"rbsexton\/gecko,rbsexton\/gecko,rbsexton\/gecko","old_file":"tiny\/bringup\/launcher\/efm32tg.ld","new_file":"tiny\/bringup\/launcher\/efm32tg.ld","new_contents":"\/* Linker script for Silicon Labs EFM32TG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 4.1.0 *\/\r\n\/*                                                                  *\/\r\n\r\nMEMORY\r\n{\r\n  \/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144 *\/\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8192\r\n  \/* RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768 *\/\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 1024\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.vectors))\r\n    __Vectors_End = .;\r\n    __Vectors_Size = __Vectors_End - __Vectors;\r\n    __end__ = .;\r\n\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  \/* To copy multiple ROM to RAM sections,\r\n   * uncomment .copy.table section and,\r\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .copy.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __copy_table_start__ = .;\r\n    LONG (__etext)\r\n    LONG (__data_start__)\r\n    LONG (__data_end__ - __data_start__)\r\n    LONG (__etext2)\r\n    LONG (__data2_start__)\r\n    LONG (__data2_end__ - __data2_start__)\r\n    __copy_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  \/* To clear multiple BSS sections,\r\n   * uncomment .zero.table section and,\r\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .zero.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __zero_table_start__ = .;\r\n    LONG (__bss_start__)\r\n    LONG (__bss_end__ - __bss_start__)\r\n    LONG (__bss2_start__)\r\n    LONG (__bss2_end__ - __bss2_start__)\r\n    __zero_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy (COPY):\r\n  {\r\n    KEEP(*(.stack*))\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","old_contents":"\/* Linker script for Silicon Labs EFM32TG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 4.1.0 *\/\r\n\/*                                                                  *\/\r\n\r\nMEMORY\r\n{\r\n  \/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144 *\/\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8192\r\n  \/* RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768 *\/\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 2048 + 512\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.vectors))\r\n    __Vectors_End = .;\r\n    __Vectors_Size = __Vectors_End - __Vectors;\r\n    __end__ = .;\r\n\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  \/* To copy multiple ROM to RAM sections,\r\n   * uncomment .copy.table section and,\r\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .copy.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __copy_table_start__ = .;\r\n    LONG (__etext)\r\n    LONG (__data_start__)\r\n    LONG (__data_end__ - __data_start__)\r\n    LONG (__etext2)\r\n    LONG (__data2_start__)\r\n    LONG (__data2_end__ - __data2_start__)\r\n    __copy_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  \/* To clear multiple BSS sections,\r\n   * uncomment .zero.table section and,\r\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .zero.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __zero_table_start__ = .;\r\n    LONG (__bss_start__)\r\n    LONG (__bss_end__ - __bss_start__)\r\n    LONG (__bss2_start__)\r\n    LONG (__bss2_end__ - __bss2_start__)\r\n    __zero_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy (COPY):\r\n  {\r\n    KEEP(*(.stack*))\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"46fdf9f5821cf4211cbc1c5b0028116a94f775f6","subject":"Changed link script. STM32F103C8 has 20K of flash","message":"Changed link script. STM32F103C8 has 20K of flash\n","repos":"yangosoft\/stm32f103c8-board,yangosoft\/stm32f103c8-board","old_file":"code\/freertos_stm32f103\/stm32f103c8.ld","new_file":"code\/freertos_stm32f103\/stm32f103c8.ld","new_contents":"\n\n\/* Define memory regions. 20K of flash*\/\nMEMORY\n{\n\trom (rx) : ORIGIN = 0x08000000, LENGTH = 64K\n\tram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\nINCLUDE libopencm3_stm32f1.ld\n","old_contents":"\n\n\/* Define memory regions. *\/\nMEMORY\n{\n\trom (rx) : ORIGIN = 0x08000000, LENGTH = 64K\n\tram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\nINCLUDE libopencm3_stm32f1.ld","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"31f9292f90e48c4418b41d2d1382d87c00169a72","subject":"feat: disable mbedtls rom code on master","message":"feat: disable mbedtls rom code on master\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.mbedtls.ld","new_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.mbedtls.ld","new_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.mbedtls.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group rom_mbedtls\n ***************************************\/\n\n\/* Functions *\/\nmbedtls_md5_starts_ret = 0x40002be4;\nmbedtls_md5_update_ret = 0x40002be8;\nmbedtls_md5_finish_ret = 0x40002bec;\n\/* Data (.data, .bss, .rodata) *\/\n","old_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.mbedtls.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group rom_mbedtls\n ***************************************\/\n\n\/* Functions *\/\nmbedtls_aes_init = 0x40002664;\nssl_write_client_hello = 0x40002668;\nssl_parse_server_hello = 0x4000266c;\nssl_parse_server_key_exchange = 0x40002670;\nssl_parse_certificate_request = 0x40002674;\nssl_parse_server_hello_done = 0x40002678;\nssl_write_client_key_exchange = 0x4000267c;\nssl_write_certificate_verify = 0x40002680;\nssl_parse_new_session_ticket = 0x40002684;\nmbedtls_aes_free = 0x40002688;\nmbedtls_aes_setkey_enc = 0x4000268c;\nmbedtls_aes_setkey_dec = 0x40002690;\nmbedtls_aes_crypt_ecb = 0x40002694;\nmbedtls_aes_crypt_cbc = 0x40002698;\nmbedtls_internal_aes_encrypt = 0x4000269c;\nmbedtls_internal_aes_decrypt = 0x400026a0;\nmbedtls_asn1_get_len = 0x400026a4;\nmbedtls_asn1_get_tag = 0x400026a8;\nmbedtls_asn1_get_bool = 0x400026ac;\nmbedtls_asn1_get_int = 0x400026b0;\nmbedtls_asn1_get_bitstring = 0x400026b4;\nmbedtls_asn1_get_bitstring_null = 0x400026b8;\nmbedtls_asn1_get_sequence_of = 0x400026bc;\nmbedtls_asn1_get_mpi = 0x400026c0;\nmbedtls_asn1_get_alg = 0x400026c4;\nmbedtls_asn1_get_alg_null = 0x400026c8;\nmbedtls_asn1_write_len = 0x400026cc;\nmbedtls_asn1_write_tag = 0x400026d0;\nmbedtls_asn1_write_mpi = 0x400026d4;\nmbedtls_base64_decode = 0x400026d8;\nmbedtls_mpi_init = 0x400026dc;\nmbedtls_mpi_free = 0x400026e0;\nmbedtls_mpi_grow = 0x400026e4;\nmbedtls_mpi_shrink = 0x400026e8;\nmbedtls_mpi_copy = 0x400026ec;\nmbedtls_mpi_safe_cond_assign = 0x400026f0;\nmbedtls_mpi_safe_cond_swap = 0x400026f4;\nmbedtls_mpi_lset = 0x400026f8;\nmbedtls_mpi_get_bit = 0x400026fc;\nmbedtls_mpi_set_bit = 0x40002700;\nmbedtls_mpi_lsb = 0x40002704;\nmbedtls_mpi_bitlen = 0x40002708;\nmbedtls_mpi_size = 0x4000270c;\nmbedtls_mpi_read_binary = 0x40002710;\nmbedtls_mpi_write_binary = 0x40002714;\nmbedtls_mpi_shift_l = 0x40002718;\nmbedtls_mpi_shift_r = 0x4000271c;\nmbedtls_mpi_cmp_abs = 0x40002720;\nmbedtls_mpi_cmp_mpi = 0x40002724;\nmbedtls_mpi_lt_mpi_ct = 0x40002728;\nmbedtls_mpi_cmp_int = 0x4000272c;\nmbedtls_mpi_add_abs = 0x40002730;\nmbedtls_mpi_sub_abs = 0x40002734;\nmbedtls_mpi_add_mpi = 0x40002738;\nmbedtls_mpi_sub_mpi = 0x4000273c;\nmbedtls_mpi_add_int = 0x40002740;\nmbedtls_mpi_sub_int = 0x40002744;\nmbedtls_mpi_mul_mpi = 0x40002748;\nmbedtls_mpi_mul_int = 0x4000274c;\nmbedtls_mpi_div_mpi = 0x40002750;\nmbedtls_mpi_div_int = 0x40002754;\nmbedtls_mpi_mod_mpi = 0x40002758;\nmbedtls_mpi_mod_int = 0x4000275c;\nmbedtls_mpi_exp_mod = 0x40002760;\nmbedtls_mpi_fill_random = 0x40002764;\nmbedtls_mpi_gcd = 0x40002768;\nmbedtls_mpi_inv_mod = 0x4000276c;\nmbedtls_mpi_is_prime_ext = 0x40002770;\nmbedtls_ccm_star_encrypt_and_tag = 0x40002774;\nmbedtls_ccm_star_auth_decrypt = 0x40002778;\nmbedtls_cipher_init = 0x4000277c;\nmbedtls_cipher_set_padding_mode = 0x40002780;\nmbedtls_cipher_reset = 0x40002784;\nmbedtls_cipher_finish = 0x40002788;\nmbedtls_cipher_crypt = 0x4000278c;\nmbedtls_cipher_cmac_starts = 0x40002790;\nmbedtls_cipher_cmac_update = 0x40002794;\nmbedtls_cipher_cmac_finish = 0x40002798;\nmbedtls_ctr_drbg_init = 0x4000279c;\nmbedtls_ctr_drbg_seed = 0x400027a0;\nmbedtls_ctr_drbg_free = 0x400027a4;\nmbedtls_ctr_drbg_reseed = 0x400027a8;\nmbedtls_ctr_drbg_random_with_add = 0x400027ac;\nmbedtls_ctr_drbg_random = 0x400027b0;\nmbedtls_dhm_init = 0x400027b4;\nmbedtls_dhm_read_params = 0x400027b8;\nmbedtls_dhm_make_public = 0x400027bc;\nmbedtls_dhm_calc_secret = 0x400027c0;\nmbedtls_dhm_free = 0x400027c4;\nmbedtls_ecdh_init = 0x400027c8;\nmbedtls_ecdh_setup = 0x400027cc;\nmbedtls_ecdh_free = 0x400027d0;\nmbedtls_ecdh_read_params = 0x400027d4;\nmbedtls_ecdh_get_params = 0x400027d8;\nmbedtls_ecdh_make_public = 0x400027dc;\nmbedtls_ecdh_calc_secret = 0x400027e0;\nmbedtls_ecdh_enable_restart = 0x400027e4;\nmbedtls_ecdsa_write_signature = 0x400027e8;\nmbedtls_ecdsa_write_signature_restartable = 0x400027ec;\nmbedtls_ecdsa_read_signature = 0x400027f0;\nmbedtls_ecdsa_read_signature_restartable = 0x400027f4;\nmbedtls_ecdsa_from_keypair = 0x400027f8;\nmbedtls_ecdsa_init = 0x400027fc;\nmbedtls_ecdsa_free = 0x40002800;\nmbedtls_ecdsa_restart_init = 0x40002804;\nmbedtls_ecdsa_restart_free = 0x40002808;\nmbedtls_ecjpake_init = 0x4000280c;\nmbedtls_ecjpake_check = 0x40002810;\nmbedtls_ecjpake_write_round_one = 0x40002814;\nmbedtls_ecjpake_read_round_one = 0x40002818;\nmbedtls_ecjpake_write_round_two = 0x4000281c;\nmbedtls_ecjpake_read_round_two = 0x40002820;\nmbedtls_ecjpake_derive_secret = 0x40002824;\nmbedtls_ecjpake_free = 0x40002828;\nmbedtls_ecp_check_budget = 0x4000282c;\nmbedtls_ecp_restart_is_enabled = 0x40002830;\nmbedtls_ecp_curve_list = 0x40002834;\nmbedtls_ecp_grp_id_list = 0x40002838;\nmbedtls_ecp_curve_info_from_grp_id = 0x4000283c;\nmbedtls_ecp_curve_info_from_tls_id = 0x40002840;\nmbedtls_ecp_point_init = 0x40002844;\nmbedtls_ecp_group_init = 0x40002848;\nmbedtls_ecp_keypair_init = 0x4000284c;\nmbedtls_ecp_point_free = 0x40002850;\nmbedtls_ecp_group_free = 0x40002854;\nmbedtls_ecp_keypair_free = 0x40002858;\nmbedtls_ecp_restart_init = 0x4000285c;\nmbedtls_ecp_restart_free = 0x40002860;\nmbedtls_ecp_copy = 0x40002864;\nmbedtls_ecp_group_copy = 0x40002868;\nmbedtls_ecp_set_zero = 0x4000286c;\nmbedtls_ecp_is_zero = 0x40002870;\nmbedtls_ecp_point_cmp = 0x40002874;\nmbedtls_ecp_point_write_binary = 0x40002878;\nmbedtls_ecp_point_read_binary = 0x4000287c;\nmbedtls_ecp_tls_read_point = 0x40002880;\nmbedtls_ecp_tls_write_point = 0x40002884;\nmbedtls_ecp_group_load = 0x40002888;\nmbedtls_ecp_tls_read_group = 0x4000288c;\nmbedtls_ecp_tls_read_group_id = 0x40002890;\nmbedtls_ecp_tls_write_group = 0x40002894;\nmbedtls_ecp_mul = 0x40002898;\nmbedtls_ecp_mul_restartable = 0x4000289c;\nmbedtls_ecp_muladd = 0x400028a0;\nmbedtls_ecp_muladd_restartable = 0x400028a4;\nmbedtls_ecp_check_pubkey = 0x400028a8;\nmbedtls_ecp_check_privkey = 0x400028ac;\nmbedtls_ecp_gen_privkey = 0x400028b0;\nmbedtls_ecp_gen_keypair_base = 0x400028b4;\nmbedtls_ecp_check_pub_priv = 0x400028b8;\nmbedtls_entropy_add_source = 0x400028bc;\nmbedtls_entropy_func = 0x400028c0;\nmbedtls_gcm_crypt_and_tag = 0x400028c4;\nmbedtls_gcm_starts = 0x400028c8;\nmbedtls_gcm_update = 0x400028cc;\nmbedtls_gcm_finish = 0x400028d0;\nmbedtls_hmac_drbg_init = 0x400028d4;\nmbedtls_hmac_drbg_seed_buf = 0x400028d8;\nmbedtls_hmac_drbg_update_ret = 0x400028dc;\nmbedtls_hmac_drbg_reseed = 0x400028e0;\nmbedtls_hmac_drbg_random_with_add = 0x400028e4;\nmbedtls_hmac_drbg_random = 0x400028e8;\nmbedtls_hmac_drbg_free = 0x400028ec;\nmbedtls_md_list = 0x400028f0;\nmbedtls_md_init = 0x400028f4;\nmbedtls_md_free = 0x400028f8;\nmbedtls_md_setup = 0x400028fc;\nmbedtls_md_clone = 0x40002900;\nmbedtls_md_get_size = 0x40002904;\nmbedtls_md_get_type = 0x40002908;\nmbedtls_md_starts = 0x4000290c;\nmbedtls_md_update = 0x40002910;\nmbedtls_md_finish = 0x40002914;\nmbedtls_md = 0x40002918;\nmbedtls_md_hmac_starts = 0x4000291c;\nmbedtls_md_hmac_update = 0x40002920;\nmbedtls_md_hmac_finish = 0x40002924;\nmbedtls_md_hmac_reset = 0x40002928;\nmbedtls_oid_get_x509_ext_type = 0x4000292c;\nmbedtls_oid_get_pk_alg = 0x40002930;\nmbedtls_oid_get_ec_grp = 0x40002934;\nmbedtls_oid_get_sig_alg = 0x40002938;\nmbedtls_oid_get_md_alg = 0x4000293c;\nmbedtls_oid_get_md_hmac = 0x40002940;\nmbedtls_oid_get_oid_by_md = 0x40002944;\nmbedtls_oid_get_cipher_alg = 0x40002948;\nmbedtls_oid_get_pkcs12_pbe_alg = 0x4000294c;\nmbedtls_pem_init = 0x40002950;\nmbedtls_pem_free = 0x40002954;\nmbedtls_pkcs12_pbe_sha1_rc4_128 = 0x40002958;\nmbedtls_pkcs12_pbe = 0x4000295c;\nmbedtls_pkcs12_derivation = 0x40002960;\nmbedtls_pkcs5_pbes2 = 0x40002964;\nmbedtls_pkcs5_pbkdf2_hmac = 0x40002968;\nmbedtls_pk_info_from_type = 0x4000296c;\nmbedtls_pk_init = 0x40002970;\nmbedtls_pk_free = 0x40002974;\nmbedtls_pk_restart_init = 0x40002978;\nmbedtls_pk_restart_free = 0x4000297c;\nmbedtls_pk_setup = 0x40002980;\nmbedtls_pk_can_do = 0x40002984;\nmbedtls_pk_verify = 0x40002988;\nmbedtls_pk_verify_restartable = 0x4000298c;\nmbedtls_pk_verify_ext = 0x40002990;\nmbedtls_pk_sign_restartable = 0x40002994;\nmbedtls_pk_encrypt = 0x40002998;\nmbedtls_pk_get_type = 0x4000299c;\nmbedtls_pk_parse_subpubkey = 0x400029a0;\nmbedtls_rsa_init = 0x400029a4;\nmbedtls_rsa_import = 0x400029a8;\nmbedtls_rsa_import_raw = 0x400029ac;\nmbedtls_rsa_complete = 0x400029b0;\nmbedtls_rsa_set_padding = 0x400029b4;\nmbedtls_rsa_get_len = 0x400029b8;\nmbedtls_rsa_check_pubkey = 0x400029bc;\nmbedtls_rsa_check_privkey = 0x400029c0;\nmbedtls_rsa_check_pub_priv = 0x400029c4;\nmbedtls_rsa_public = 0x400029c8;\nmbedtls_rsa_private = 0x400029cc;\nmbedtls_rsa_pkcs1_encrypt = 0x400029d0;\nmbedtls_rsa_rsaes_pkcs1_v15_encrypt = 0x400029d4;\nmbedtls_rsa_rsaes_oaep_encrypt = 0x400029d8;\nmbedtls_rsa_pkcs1_decrypt = 0x400029dc;\nmbedtls_rsa_rsaes_pkcs1_v15_decrypt = 0x400029e0;\nmbedtls_rsa_rsaes_oaep_decrypt = 0x400029e4;\nmbedtls_rsa_pkcs1_sign = 0x400029e8;\nmbedtls_rsa_rsassa_pkcs1_v15_sign = 0x400029ec;\nmbedtls_rsa_rsassa_pss_sign = 0x400029f0;\nmbedtls_rsa_pkcs1_verify = 0x400029f4;\nmbedtls_rsa_rsassa_pkcs1_v15_verify = 0x400029f8;\nmbedtls_rsa_rsassa_pss_verify = 0x400029fc;\nmbedtls_rsa_rsassa_pss_verify_ext = 0x40002a00;\nmbedtls_rsa_free = 0x40002a04;\nmbedtls_rsa_deduce_primes = 0x40002a08;\nmbedtls_rsa_deduce_private_exponent = 0x40002a0c;\nmbedtls_rsa_deduce_crt = 0x40002a10;\nmbedtls_rsa_validate_params = 0x40002a14;\nmbedtls_rsa_validate_crt = 0x40002a18;\nmbedtls_sha1_init = 0x40002a1c;\nmbedtls_sha1_free = 0x40002a20;\nmbedtls_sha1_clone = 0x40002a24;\nmbedtls_sha1_starts_ret = 0x40002a28;\nmbedtls_sha1_finish_ret = 0x40002a2c;\nmbedtls_sha256_init = 0x40002a30;\nmbedtls_sha256_free = 0x40002a34;\nmbedtls_sha256_clone = 0x40002a38;\nmbedtls_sha256_starts_ret = 0x40002a3c;\nmbedtls_sha256_finish_ret = 0x40002a40;\nmbedtls_sha256_ret = 0x40002a44;\nmbedtls_sha512_init = 0x40002a48;\nmbedtls_sha512_free = 0x40002a4c;\nmbedtls_sha512_clone = 0x40002a50;\nmbedtls_sha512_starts_ret = 0x40002a54;\nmbedtls_sha512_update_ret = 0x40002a58;\nmbedtls_sha512_finish_ret = 0x40002a5c;\nmbedtls_internal_sha512_process = 0x40002a60;\nmbedtls_sha512_ret = 0x40002a64;\nmbedtls_ssl_conf_endpoint = 0x40002a68;\nmbedtls_ssl_conf_transport = 0x40002a6c;\nmbedtls_ssl_set_bio = 0x40002a70;\nmbedtls_ssl_conf_dh_param_bin = 0x40002a74;\nmbedtls_ssl_get_max_frag_len = 0x40002a78;\nmbedtls_ssl_get_max_out_record_payload = 0x40002a7c;\nmbedtls_ssl_handshake = 0x40002a80;\nmbedtls_ssl_handshake_step = 0x40002a84;\nmbedtls_ssl_renegotiate = 0x40002a88;\nmbedtls_ssl_send_alert_message = 0x40002a8c;\nmbedtls_ssl_config_defaults = 0x40002a90;\nmbedtls_ssl_session_init = 0x40002a94;\nmbedtls_ssl_session_free = 0x40002a98;\nmbedtls_ssl_transform_free = 0x40002a9c;\nmbedtls_ssl_handshake_free = 0x40002aa0;\nmbedtls_ssl_handshake_client_step = 0x40002aa4;\nmbedtls_ssl_handshake_wrapup = 0x40002aa8;\nmbedtls_ssl_derive_keys = 0x40002aac;\nmbedtls_ssl_handle_message_type = 0x40002ab0;\nmbedtls_ssl_prepare_handshake_record = 0x40002ab4;\nmbedtls_ssl_update_handshake_status = 0x40002ab8;\nmbedtls_ssl_read_record = 0x40002abc;\nmbedtls_ssl_fetch_input = 0x40002ac0;\nmbedtls_ssl_write_handshake_msg = 0x40002ac4;\nmbedtls_ssl_write_record = 0x40002ac8;\nmbedtls_ssl_flush_output = 0x40002acc;\nmbedtls_ssl_parse_certificate = 0x40002ad0;\nmbedtls_ssl_write_certificate = 0x40002ad4;\nmbedtls_ssl_parse_change_cipher_spec = 0x40002ad8;\nmbedtls_ssl_write_change_cipher_spec = 0x40002adc;\nmbedtls_ssl_parse_finished = 0x40002ae0;\nmbedtls_ssl_write_finished = 0x40002ae4;\nmbedtls_ssl_optimize_checksum = 0x40002ae8;\nmbedtls_ssl_psk_derive_premaster = 0x40002aec;\nmbedtls_ssl_sig_from_pk = 0x40002af0;\nmbedtls_ssl_pk_alg_from_sig = 0x40002af4;\nmbedtls_ssl_md_alg_from_hash = 0x40002af8;\nmbedtls_ssl_hash_from_md_alg = 0x40002afc;\nmbedtls_ssl_check_curve = 0x40002b00;\nmbedtls_ssl_check_sig_hash = 0x40002b04;\nmbedtls_ssl_write_version = 0x40002b08;\nmbedtls_ssl_read_version = 0x40002b0c;\nmbedtls_ssl_get_key_exchange_md_ssl_tls = 0x40002b10;\nmbedtls_ssl_get_key_exchange_md_tls1_2 = 0x40002b14;\nmbedtls_ssl_cf_hmac = 0x40002b18;\nmbedtls_ssl_cf_memcpy_offset = 0x40002b1c;\nmbedtls_x509_crt_parse_der = 0x40002b20;\nmbedtls_x509_crt_verify_restartable = 0x40002b24;\nmbedtls_x509_crt_check_key_usage = 0x40002b28;\nmbedtls_x509_crt_check_extended_key_usage = 0x40002b2c;\nmbedtls_x509_crt_is_revoked = 0x40002b30;\nmbedtls_x509_crt_init = 0x40002b34;\nmbedtls_x509_crt_free = 0x40002b38;\nmbedtls_x509_crt_restart_init = 0x40002b3c;\nmbedtls_x509_crt_restart_free = 0x40002b40;\nmbedtls_x509_get_name = 0x40002b44;\nmbedtls_x509_get_alg_null = 0x40002b48;\nmbedtls_x509_get_alg = 0x40002b4c;\nmbedtls_x509_get_rsassa_pss_params = 0x40002b50;\nmbedtls_x509_get_sig = 0x40002b54;\nmbedtls_x509_get_sig_alg = 0x40002b58;\nmbedtls_x509_get_time = 0x40002b5c;\nmbedtls_x509_get_serial = 0x40002b60;\nmbedtls_x509_get_ext = 0x40002b64;\nmbedtls_aes_xts_init = 0x40002b68;\nmbedtls_aes_xts_free = 0x40002b6c;\nmbedtls_aes_xts_setkey_enc = 0x40002b70;\nmbedtls_aes_xts_setkey_dec = 0x40002b74;\nmbedtls_aes_crypt_xts = 0x40002b78;\nmbedtls_aes_crypt_cfb128 = 0x40002b7c;\nmbedtls_aes_crypt_ofb = 0x40002b80;\nmbedtls_aes_crypt_ctr = 0x40002b84;\nmbedtls_arc4_init = 0x40002b88;\nmbedtls_arc4_free = 0x40002b8c;\nmbedtls_arc4_setup = 0x40002b90;\nmbedtls_arc4_crypt = 0x40002b94;\nmbedtls_ccm_init = 0x40002b98;\nmbedtls_ccm_setkey = 0x40002b9c;\nmbedtls_ccm_free = 0x40002ba0;\nmbedtls_ccm_encrypt_and_tag = 0x40002ba4;\nmbedtls_ccm_auth_decrypt = 0x40002ba8;\nmbedtls_dhm_make_params = 0x40002bac;\nmbedtls_dhm_set_group = 0x40002bb0;\nmbedtls_dhm_read_public = 0x40002bb4;\nmbedtls_ecdh_make_params = 0x40002bb8;\nmbedtls_ecdh_read_public = 0x40002bbc;\nmbedtls_entropy_init = 0x40002bc0;\nmbedtls_entropy_free = 0x40002bc4;\nmbedtls_gcm_init = 0x40002bc8;\nmbedtls_gcm_setkey = 0x40002bcc;\nmbedtls_gcm_auth_decrypt = 0x40002bd0;\nmbedtls_gcm_free = 0x40002bd4;\nmbedtls_md5_init = 0x40002bd8;\nmbedtls_md5_free = 0x40002bdc;\nmbedtls_md5_clone = 0x40002be0;\nmbedtls_md5_starts_ret = 0x40002be4;\nmbedtls_md5_update_ret = 0x40002be8;\nmbedtls_md5_finish_ret = 0x40002bec;\nmbedtls_internal_md5_process = 0x40002bf0;\nmbedtls_md5_ret = 0x40002bf4;\nmbedtls_pk_get_bitlen = 0x40002bf8;\nmbedtls_pk_sign = 0x40002bfc;\nmbedtls_pk_decrypt = 0x40002c00;\nmbedtls_pk_parse_key = 0x40002c04;\nmbedtls_sha1_ret = 0x40002c08;\nmbedtls_ssl_init = 0x40002c0c;\nmbedtls_ssl_setup = 0x40002c10;\nmbedtls_ssl_conf_authmode = 0x40002c14;\nmbedtls_ssl_conf_rng = 0x40002c18;\nmbedtls_ssl_conf_ca_chain = 0x40002c1c;\nmbedtls_ssl_conf_own_cert = 0x40002c20;\nmbedtls_ssl_read = 0x40002c24;\nmbedtls_ssl_write = 0x40002c28;\nmbedtls_ssl_config_init = 0x40002c2c;\nmbedtls_ssl_sig_hash_set_find = 0x40002c30;\nmbedtls_ssl_sig_hash_set_add = 0x40002c34;\nmbedtls_ssl_sig_hash_set_const_hash = 0x40002c38;\nmbedtls_ssl_sig_from_pk_alg = 0x40002c3c;\nmbedtls_ssl_set_calc_verify_md = 0x40002c40;\nmbedtls_x509_crt_parse = 0x40002c44;\n\/* Data (.data, .bss, .rodata) *\/\np_osi_mbedtls_rom_funcs = 0x3fcdfaa0;\nmbedtls_x509_crt_profile_default = 0x3ff4fba4;\nmbedtls_x509_crt_profile_suiteb = 0x3ff4fb94;\naes_FSb_ptr = 0x3fcdfa9c;\nAES_RT0_ptr = 0x3fcdfa98;\nAES_RT1_ptr = 0x3fcdfa94;\nAES_RT2_ptr = 0x3fcdfa90;\nAES_RT3_ptr = 0x3fcdfa8c;\nAES_FT0_ptr = 0x3fcdfa88;\nAES_FT1_ptr = 0x3fcdfa84;\nAES_FT2_ptr = 0x3fcdfa80;\nAES_FT3_ptr = 0x3fcdfa7c;\nbignum_small_prime_ptr = 0x3fcdfa78;\nsha512_K_ptr = 0x3fcdfa74;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"49831a3aca206733e39a36644804a2cb8615591d","subject":"Update linker script.","message":"Update linker script.\n","repos":"basilfx\/EFM2Riot,basilfx\/EFM2Riot,basilfx\/EFM2Riot,basilfx\/EFM2Riot,basilfx\/EFM2Riot","old_file":"efm2riot\/templates\/cpu\/family\/ldscripts\/cpu.ld","new_file":"efm2riot\/templates\/cpu\/family\/ldscripts\/cpu.ld","new_contents":"\/*\n * Copyright (C) 2015-2017 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_{{ family }}\n * @{\n *\n * @file\n * @brief           Memory definitions for the {{ cpu|upper }} CPU\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n * @author          Bas Stottelaar <basstottelaar@gmail.com>\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = {{ flash_base|hex(8) }}, LENGTH = {{ flash_size }}\n    ram (rwx)   : ORIGIN = {{ sram_base|hex(8) }}, LENGTH = {{ sram_size }}\n}\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2016 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_{{ family }}\n * @{\n *\n * @file\n * @brief           Memory definitions for the {{ cpu|upper }} CPU\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x00000000, LENGTH = {{ flash_size }}\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = {{ sram_size }}\n}\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0bf25499dbe79f091ea5f00cc15fd97698414218","subject":"Add .got and .got.plt sections to data segment in linker (#11)","message":"Add .got and .got.plt sections to data segment in linker (#11)\n\n- The GOT and PLT need to be copied into their correct location at\r\n  startup, so bundle them in the same section with .data (which is\r\n  already copied in the same way).","repos":"google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro","old_file":"libs\/nxp\/rt1176-sdk\/MIMXRT1176xxxxx_cm7_ram.ld","new_file":"libs\/nxp\/rt1176-sdk\/MIMXRT1176xxxxx_cm7_ram.ld","new_contents":"\/*\r\n** ###################################################################\r\n**     Processors:          MIMXRT1176AVM8A_cm7\r\n**                          MIMXRT1176CVM8A_cm7\r\n**                          MIMXRT1176DVMAA_cm7\r\n**\r\n**     Compiler:            GNU C Compiler\r\n**     Reference manual:    IMXRT1170RM, Rev E, 12\/2019\r\n**     Version:             rev. 0.1, 2018-03-05\r\n**     Build:               b200828\r\n**\r\n**     Abstract:\r\n**         Linker file for the GNU C Compiler\r\n**\r\n**     Copyright 2016 Freescale Semiconductor, Inc.\r\n**     Copyright 2016-2020 NXP\r\n**     All rights reserved.\r\n**\r\n**     SPDX-License-Identifier: BSD-3-Clause\r\n**\r\n**     http:                 www.nxp.com\r\n**     mail:                 support@nxp.com\r\n**\r\n** ###################################################################\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x01000000;\r\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\r\nRPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;\r\nNCACHE_SIZE = 0x8000;\r\n\r\n\/*\r\n * Valid memory regions:\r\n * 0x00000000 - 0x0003FFFF (256KB)\r\n * 0x20000000 - 0x2003FFFF (256KB)\r\n * 0x20240000 - 0x202BFFFF (512KB)\r\n * 0x202C0000 - 0x2033FFFF (512KB)\r\n *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\n  m_interrupts          (RX)  : ORIGIN = 0x00000800, LENGTH = 0x00000400\r\n  m_text                (RX)  : ORIGIN = 0x00000c00, LENGTH = 0x0003F400\r\n  m_ncache              (RW)  : ORIGIN = 0x20000000, LENGTH = NCACHE_SIZE\r\n  m_data                (RW)  : ORIGIN = 0x20000000 + NCACHE_SIZE, LENGTH = 0x00040000 - NCACHE_SIZE\r\n  m_ocram               (RX)  : ORIGIN = 0x20240000, LENGTH = 0x00080000\r\n  rpmsg_sh_mem          (RW)  : ORIGIN = 0x202C0000, LENGTH = RPMSG_SHMEM_SIZE\r\n  m_heap                (RW)  : ORIGIN = 0x80000000, LENGTH = HEAP_SIZE\r\n  m_sdram               (RX)  : ORIGIN = 0x80000000 + HEAP_SIZE, LENGTH = 0x03000000 - HEAP_SIZE\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  __NCACHE_REGION_START = ORIGIN(m_ncache);\r\n  __NCACHE_REGION_SIZE  = LENGTH(m_ncache);\r\n\r\n  __RPMSG_SH_MEM_START = ORIGIN(rpmsg_sh_mem);\r\n  __RPMSG_SH_MEM_SIZE  = LENGTH(rpmsg_sh_mem);\r\n\r\n  \/* NOINIT section for rpmsg_sh_mem *\/\r\n  .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)\r\n  {\r\n     __RPMSG_SH_MEM_START__ = .;\r\n     *(.noinit.$rpmsg_sh_mem*)\r\n     . = ALIGN(4) ;\r\n     __RPMSG_SH_MEM_END__ = .;\r\n  } > rpmsg_sh_mem\r\n\r\n  \/* section for storing the secondary core image *\/\r\n  .core1_code :\r\n  {\r\n     . = ALIGN(4) ;\r\n    KEEP (*(.core1_code))\r\n     *(.core1_code*)\r\n     . = ALIGN(4) ;\r\n  } > m_sdram\r\n\r\n  \/* The startup code goes first into internal RAM *\/\r\n  .interrupts :\r\n  {\r\n    __VECTOR_TABLE = .;\r\n    __Vectors = .;\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))     \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } > m_interrupts\r\n\r\n  .a71ch :\r\n  {\r\n     . = ALIGN(4);\r\n     __a71ch_start = .;\r\n     *liblibs_a71ch.a:*(.text .text*)\r\n     *liblibs_a71ch.a:*(.data .data*)\r\n     *liblibs_a71ch.a:*(.rodata .rodata*)\r\n     __a71ch_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .curl :\r\n  {\r\n     . = ALIGN(4);\r\n     __curl_start = .;\r\n     *liblibs_curl.a:*(.text .text*)\r\n     *liblibs_curl.a:*(.data .data*)\r\n     *liblibs_curl.a:*(.rodata .rodata*)\r\n     __curl_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .mbedtls :\r\n  {\r\n     . = ALIGN(4);\r\n     __mbedtls_start = .;\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.rodata .rodata*)\r\n     __mbedtls_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .lwip :\r\n  {\r\n     . = ALIGN(4);\r\n     __lwip_start = .;\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.rodata .rodata*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_httpd.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_httpd.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_httpd.a:*(.rodata .rodata*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_mdns.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_mdns.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_mdns.a:*(.rodata .rodata*)\r\n     __lwip_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .wiced :\r\n  {\r\n     . = ALIGN(4);\r\n     __wiced_start = .;\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.rodata .rodata*)\r\n     __wiced_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .tensorflow :\r\n  {\r\n     . = ALIGN(4);\r\n     __tensorflow_start = .;\r\n     *liblibs_tensorflow-m7.a:*(.text .text*)\r\n     *liblibs_tensorflow-m7.a:*(.data .data*)\r\n     *liblibs_tensorflow-m7.a:*(.rodata .rodata*)\r\n     *liblibs_kissfft-m7.a*:*(.text .text*)\r\n     *liblibs_kissfft-m7.a*:*(.data .data*)\r\n     *liblibs_kissfft-m7.a*:*(.rodata .rodata*)\r\n     __tensorflow_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .arduino :\r\n  {\r\n     . = ALIGN(4);\r\n     __arduino_start = .;\r\n     *liblibs_arduino_coral_micro_bundled.a:*(.text .text*)\r\n     *liblibs_arduino_coral_micro_bundled.a:*(.data .data*)\r\n     *liblibs_arduino_coral_micro_bundled.a:*(.rodata .rodata*)\r\n     *liblibs_arduino_coral_micro_poe_bundled.a:*(.text .text*)\r\n     *liblibs_arduino_coral_micro_poe_bundled.a:*(.data .data*)\r\n     *liblibs_arduino_coral_micro_poe_bundled.a:*(.rodata .rodata*)\r\n     *liblibs_arduino_coral_micro_wifi_bundled.a:*(.text .text*)\r\n     *liblibs_arduino_coral_micro_wifi_bundled.a:*(.data .data*)\r\n     *liblibs_arduino_coral_micro_wifi_bundled.a:*(.rodata .rodata*)\r\n     __arduino_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .libjpeg :\r\n  {\r\n     . = ALIGN(4);\r\n     __libjpeg_start = .;\r\n     *liblibs_libjpeg.a:*(.text .text*)\r\n     *liblibs_libjpeg.a:*(.data .data*)\r\n     *liblibs_libjpeg.a:*(.rodata .rodata*)\r\n     __libjpeg_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .edgefast_bluetooth_text :\r\n  {\r\n    . = ALIGN(4);\r\n    __edgefast_bluetooth_text_start__ = .;\r\n    *libedgefast_bluetooth_internal.a:*(.text .text*)\r\n    *lib_crypto_m7.a:*(.text .text*)\r\n    *libethermind_ble_protocol.a:*(.text .text*)\r\n    *libethermind_ble_gatt.a:*(.text .text*)\r\n    *libethermind_ble_core.a:*(.text .text*)\r\n    *libethermind_ble_util.a:*(.text .text*)\r\n    __edgefast_bluetooth_text_end__ = .;\r\n    . = ALIGN(4);\r\n  } > m_sdram\r\n\r\n  .edgefast_bluetooth_data :\r\n  {\r\n    . = ALIGN(4);\r\n    __edgefast_bluetooth_data_start__ = .;\r\n    *libedgefast_bluetooth_internal.a:*(.data .data*)\r\n    *lib_crypto_m7.a:*(.data .data*)\r\n    *libethermind_ble_protocol.a:*(.data .data*)\r\n    *libethermind_ble_gatt.a:*(.data .data*)\r\n    *libethermind_ble_core.a:*(.data .data*)\r\n    *libethermind_ble_util.a:*(.data .data*)\r\n    __edgefast_bluetooth_data_end__ = .;\r\n    . = ALIGN(4);\r\n  } > m_sdram\r\n\r\n  .edgefast_bluetooth_rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    __edgefast_bluetooth_rodata_start__ = .;\r\n    *libedgefast_bluetooth_internal.a:*(.rodata .rodata*)\r\n    *lib_crypto_m7.a:*(.rodata .rodata*)\r\n    *libethermind_ble_protocol.a:*(.rodata .rodata*)\r\n    *libethermind_ble_gatt.a:*(.rodata .rodata*)\r\n    *libethermind_ble_core.a:*(.rodata .rodata*)\r\n    *libethermind_ble_util.a:*(.rodata .rodata*)\r\n    __edgefast_bluetooth_rodata_end__ = .;\r\n    . = ALIGN(4);\r\n  } > m_sdram\r\n\r\n  \/* The program code and other data goes into internal RAM *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)                 \/* .text sections (code) *\/\r\n    *(.text*)                \/* .text* sections (code) *\/\r\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\r\n    KEEP(*(.rodata.debug))\r\n    *(.glue_7)               \/* glue arm to thumb code *\/\r\n    *(.glue_7t)              \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._settings_handler_static :\r\n  {\r\n    . = ALIGN(4);\r\n    _settings_handler_static_list_start = .;\r\n    KEEP(*(SORT(._settings_handler_static.static.*)))\r\n    _settings_handler_static_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._bt_gatt_service_static :\r\n  {\r\n    . = ALIGN(4);\r\n    _bt_gatt_service_static_list_start = .;\r\n    KEEP(*(SORT(._bt_gatt_service_static.static.*)))\r\n    _bt_gatt_service_static_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._bt_l2cap_fixed_chan :\r\n  {\r\n    . = ALIGN(4);\r\n    _bt_l2cap_fixed_chan_list_start = .;\r\n    KEEP(*(SORT(._bt_l2cap_fixed_chan.static.*)))\r\n    _bt_l2cap_fixed_chan_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > m_text\r\n\r\n  .ARM :\r\n  {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } > m_text\r\n\r\n .ctors :\r\n  {\r\n    __CTOR_LIST__ = .;\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       from the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    __CTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .dtors :\r\n  {\r\n    __DTOR_LIST__ = .;\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    __DTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .preinit_array :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } > m_text\r\n\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } > m_text\r\n\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } > m_text\r\n\r\n  __etext = .;    \/* define a global symbol at end of code *\/\r\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\r\n\r\n  __VECTOR_RAM = ORIGIN(m_interrupts);\r\n  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;\r\n\r\n  .data : AT(__DATA_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __DATA_RAM = .;\r\n    __data_start__ = .;      \/* create a global symbol at data start *\/\r\n    *(m_usb_dma_init_data)\r\n    *(.data)                 \/* .data sections *\/\r\n    *(.data*)                \/* .data* sections *\/\r\n    *(.got)\r\n    *(.got*)\r\n    *(.got.plt)\r\n    *(.got.plt*)\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    _net_buf_pool_list = .;\r\n    KEEP(*(SORT(._net_buf_pool*)))\r\n    . = ALIGN(4);\r\n    __data_end__ = .;        \/* define a global symbol at data end *\/\r\n  } > m_data\r\n  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);\r\n  .ncache.init : AT(__NDATA_ROM)\r\n  {\r\n    __noncachedata_start__ = .;   \/* create a global symbol at ncache data start *\/\r\n    *(NonCacheable.init)\r\n    . = ALIGN(4);\r\n    __noncachedata_init_end__ = .;   \/* create a global symbol at initialized ncache data end *\/\r\n  } > m_ncache\r\n  . = __noncachedata_init_end__;\r\n  .ncache :\r\n  {\r\n    *(NonCacheable)\r\n    . = ALIGN(4);\r\n    __noncachedata_end__ = .;     \/* define a global symbol at ncache data end *\/\r\n  } > m_ncache\r\n  __SDRAM_ROM = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);\r\n  .sdram_data : AT(__SDRAM_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_data_start__ = .;\r\n    KEEP(*(.sdram_data*))\r\n    . = ALIGN(4);\r\n    __sdram_data_end__ = .;\r\n  } > m_sdram\r\n\r\n  \/* Uninitialized data section *\/\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss section *\/\r\n    . = ALIGN(4);\r\n    __START_BSS = .;\r\n    __bss_start__ = .;\r\n    *(m_usb_dma_noninit_data)\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n    __END_BSS = .;\r\n  } > m_data\r\n  __DATA_END = __SDRAM_ROM;\r\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\r\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\r\n\r\n  .sdram_bss (NOLOAD) :\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_bss_start__ = .;\r\n    *(.sdram_bss*)\r\n    \/* edgefast_bluetooth_bss *\/\r\n    *lib_crypto_m7.a:*(.bss .bss*)\r\n    *libedgefast_bluetooth_internal.a:*(.bss .bss*)\r\n    *libethermind_ble_protocol.a:*(.bss .bss*)\r\n    *libethermind_ble_gatt.a:*(.bss .bss*)\r\n    *libethermind_ble_core.a:*(.bss .bss*)\r\n    *libethermind_ble_util.a:*(.bss .bss*)\r\n    . = ALIGN(4);\r\n    __sdram_bss_end__ = .;\r\n  } > m_sdram\r\n\r\n  .heap :\r\n  {\r\n    . = ALIGN(8);\r\n    __end__ = .;\r\n    PROVIDE(end = .);\r\n    __HeapBase = .;\r\n    . += HEAP_SIZE;\r\n    __HeapLimit = .;\r\n    __heap_limit = .; \/* Add for _sbrk *\/\r\n  } > m_heap\r\n\r\n  .stack :\r\n  {\r\n    . = ALIGN(8);\r\n    . += STACK_SIZE;\r\n  } > m_data\r\n\r\n  \/* Initializes stack on the end of block *\/\r\n  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);\r\n  __StackLimit = __StackTop - STACK_SIZE;\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n\r\n","old_contents":"\/*\r\n** ###################################################################\r\n**     Processors:          MIMXRT1176AVM8A_cm7\r\n**                          MIMXRT1176CVM8A_cm7\r\n**                          MIMXRT1176DVMAA_cm7\r\n**\r\n**     Compiler:            GNU C Compiler\r\n**     Reference manual:    IMXRT1170RM, Rev E, 12\/2019\r\n**     Version:             rev. 0.1, 2018-03-05\r\n**     Build:               b200828\r\n**\r\n**     Abstract:\r\n**         Linker file for the GNU C Compiler\r\n**\r\n**     Copyright 2016 Freescale Semiconductor, Inc.\r\n**     Copyright 2016-2020 NXP\r\n**     All rights reserved.\r\n**\r\n**     SPDX-License-Identifier: BSD-3-Clause\r\n**\r\n**     http:                 www.nxp.com\r\n**     mail:                 support@nxp.com\r\n**\r\n** ###################################################################\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x01000000;\r\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\r\nRPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;\r\nNCACHE_SIZE = 0x8000;\r\n\r\n\/*\r\n * Valid memory regions:\r\n * 0x00000000 - 0x0003FFFF (256KB)\r\n * 0x20000000 - 0x2003FFFF (256KB)\r\n * 0x20240000 - 0x202BFFFF (512KB)\r\n * 0x202C0000 - 0x2033FFFF (512KB)\r\n *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\n  m_interrupts          (RX)  : ORIGIN = 0x00000800, LENGTH = 0x00000400\r\n  m_text                (RX)  : ORIGIN = 0x00000c00, LENGTH = 0x0003F400\r\n  m_ncache              (RW)  : ORIGIN = 0x20000000, LENGTH = NCACHE_SIZE\r\n  m_data                (RW)  : ORIGIN = 0x20000000 + NCACHE_SIZE, LENGTH = 0x00040000 - NCACHE_SIZE\r\n  m_ocram               (RX)  : ORIGIN = 0x20240000, LENGTH = 0x00080000\r\n  rpmsg_sh_mem          (RW)  : ORIGIN = 0x202C0000, LENGTH = RPMSG_SHMEM_SIZE\r\n  m_heap                (RW)  : ORIGIN = 0x80000000, LENGTH = HEAP_SIZE\r\n  m_sdram               (RX)  : ORIGIN = 0x80000000 + HEAP_SIZE, LENGTH = 0x03000000 - HEAP_SIZE\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  __NCACHE_REGION_START = ORIGIN(m_ncache);\r\n  __NCACHE_REGION_SIZE  = LENGTH(m_ncache);\r\n\r\n  __RPMSG_SH_MEM_START = ORIGIN(rpmsg_sh_mem);\r\n  __RPMSG_SH_MEM_SIZE  = LENGTH(rpmsg_sh_mem);\r\n\r\n  \/* NOINIT section for rpmsg_sh_mem *\/\r\n  .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)\r\n  {\r\n     __RPMSG_SH_MEM_START__ = .;\r\n     *(.noinit.$rpmsg_sh_mem*)\r\n     . = ALIGN(4) ;\r\n     __RPMSG_SH_MEM_END__ = .;\r\n  } > rpmsg_sh_mem\r\n\r\n  \/* section for storing the secondary core image *\/\r\n  .core1_code :\r\n  {\r\n     . = ALIGN(4) ;\r\n    KEEP (*(.core1_code))\r\n     *(.core1_code*)\r\n     . = ALIGN(4) ;\r\n  } > m_sdram\r\n\r\n  \/* The startup code goes first into internal RAM *\/\r\n  .interrupts :\r\n  {\r\n    __VECTOR_TABLE = .;\r\n    __Vectors = .;\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))     \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } > m_interrupts\r\n\r\n  .a71ch :\r\n  {\r\n     . = ALIGN(4);\r\n     __a71ch_start = .;\r\n     *liblibs_a71ch.a:*(.text .text*)\r\n     *liblibs_a71ch.a:*(.data .data*)\r\n     *liblibs_a71ch.a:*(.rodata .rodata*)\r\n     __a71ch_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .curl :\r\n  {\r\n     . = ALIGN(4);\r\n     __curl_start = .;\r\n     *liblibs_curl.a:*(.text .text*)\r\n     *liblibs_curl.a:*(.data .data*)\r\n     *liblibs_curl.a:*(.rodata .rodata*)\r\n     __curl_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .mbedtls :\r\n  {\r\n     . = ALIGN(4);\r\n     __mbedtls_start = .;\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk-mbedtls.a:*(.rodata .rodata*)\r\n     __mbedtls_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .lwip :\r\n  {\r\n     . = ALIGN(4);\r\n     __lwip_start = .;\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_lwip.a:*(.rodata .rodata*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_httpd.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_httpd.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_httpd.a:*(.rodata .rodata*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_mdns.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_mdns.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_lwip_mdns.a:*(.rodata .rodata*)\r\n     __lwip_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .wiced :\r\n  {\r\n     . = ALIGN(4);\r\n     __wiced_start = .;\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.text .text*)\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.data .data*)\r\n     *liblibs_nxp_rt1176-sdk_wiced.a:*(.rodata .rodata*)\r\n     __wiced_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .tensorflow :\r\n  {\r\n     . = ALIGN(4);\r\n     __tensorflow_start = .;\r\n     *liblibs_tensorflow-m7.a:*(.text .text*)\r\n     *liblibs_tensorflow-m7.a:*(.data .data*)\r\n     *liblibs_tensorflow-m7.a:*(.rodata .rodata*)\r\n     *liblibs_kissfft-m7.a*:*(.text .text*)\r\n     *liblibs_kissfft-m7.a*:*(.data .data*)\r\n     *liblibs_kissfft-m7.a*:*(.rodata .rodata*)\r\n     __tensorflow_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .arduino :\r\n  {\r\n     . = ALIGN(4);\r\n     __arduino_start = .;\r\n     *liblibs_arduino_coral_micro_bundled.a:*(.text .text*)\r\n     *liblibs_arduino_coral_micro_bundled.a:*(.data .data*)\r\n     *liblibs_arduino_coral_micro_bundled.a:*(.rodata .rodata*)\r\n     *liblibs_arduino_coral_micro_poe_bundled.a:*(.text .text*)\r\n     *liblibs_arduino_coral_micro_poe_bundled.a:*(.data .data*)\r\n     *liblibs_arduino_coral_micro_poe_bundled.a:*(.rodata .rodata*)\r\n     *liblibs_arduino_coral_micro_wifi_bundled.a:*(.text .text*)\r\n     *liblibs_arduino_coral_micro_wifi_bundled.a:*(.data .data*)\r\n     *liblibs_arduino_coral_micro_wifi_bundled.a:*(.rodata .rodata*)\r\n     __arduino_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .libjpeg :\r\n  {\r\n     . = ALIGN(4);\r\n     __libjpeg_start = .;\r\n     *liblibs_libjpeg.a:*(.text .text*)\r\n     *liblibs_libjpeg.a:*(.data .data*)\r\n     *liblibs_libjpeg.a:*(.rodata .rodata*)\r\n     __libjpeg_end = .;\r\n     . = ALIGN(4);\r\n  } > m_ocram\r\n\r\n  .edgefast_bluetooth_text :\r\n  {\r\n    . = ALIGN(4);\r\n    __edgefast_bluetooth_text_start__ = .;\r\n    *libedgefast_bluetooth_internal.a:*(.text .text*)\r\n    *lib_crypto_m7.a:*(.text .text*)\r\n    *libethermind_ble_protocol.a:*(.text .text*)\r\n    *libethermind_ble_gatt.a:*(.text .text*)\r\n    *libethermind_ble_core.a:*(.text .text*)\r\n    *libethermind_ble_util.a:*(.text .text*)\r\n    __edgefast_bluetooth_text_end__ = .;\r\n    . = ALIGN(4);\r\n  } > m_sdram\r\n\r\n  .edgefast_bluetooth_data :\r\n  {\r\n    . = ALIGN(4);\r\n    __edgefast_bluetooth_data_start__ = .;\r\n    *libedgefast_bluetooth_internal.a:*(.data .data*)\r\n    *lib_crypto_m7.a:*(.data .data*)\r\n    *libethermind_ble_protocol.a:*(.data .data*)\r\n    *libethermind_ble_gatt.a:*(.data .data*)\r\n    *libethermind_ble_core.a:*(.data .data*)\r\n    *libethermind_ble_util.a:*(.data .data*)\r\n    __edgefast_bluetooth_data_end__ = .;\r\n    . = ALIGN(4);\r\n  } > m_sdram\r\n\r\n  .edgefast_bluetooth_rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    __edgefast_bluetooth_rodata_start__ = .;\r\n    *libedgefast_bluetooth_internal.a:*(.rodata .rodata*)\r\n    *lib_crypto_m7.a:*(.rodata .rodata*)\r\n    *libethermind_ble_protocol.a:*(.rodata .rodata*)\r\n    *libethermind_ble_gatt.a:*(.rodata .rodata*)\r\n    *libethermind_ble_core.a:*(.rodata .rodata*)\r\n    *libethermind_ble_util.a:*(.rodata .rodata*)\r\n    __edgefast_bluetooth_rodata_end__ = .;\r\n    . = ALIGN(4);\r\n  } > m_sdram\r\n\r\n  \/* The program code and other data goes into internal RAM *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)                 \/* .text sections (code) *\/\r\n    *(.text*)                \/* .text* sections (code) *\/\r\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\r\n    KEEP(*(.rodata.debug))\r\n    *(.glue_7)               \/* glue arm to thumb code *\/\r\n    *(.glue_7t)              \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._settings_handler_static :\r\n  {\r\n    . = ALIGN(4);\r\n    _settings_handler_static_list_start = .;\r\n    KEEP(*(SORT(._settings_handler_static.static.*)))\r\n    _settings_handler_static_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._bt_gatt_service_static :\r\n  {\r\n    . = ALIGN(4);\r\n    _bt_gatt_service_static_list_start = .;\r\n    KEEP(*(SORT(._bt_gatt_service_static.static.*)))\r\n    _bt_gatt_service_static_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  ._bt_l2cap_fixed_chan :\r\n  {\r\n    . = ALIGN(4);\r\n    _bt_l2cap_fixed_chan_list_start = .;\r\n    KEEP(*(SORT(._bt_l2cap_fixed_chan.static.*)))\r\n    _bt_l2cap_fixed_chan_list_end = .;\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > m_text\r\n\r\n  .ARM :\r\n  {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } > m_text\r\n\r\n .ctors :\r\n  {\r\n    __CTOR_LIST__ = .;\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       from the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    __CTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .dtors :\r\n  {\r\n    __DTOR_LIST__ = .;\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    __DTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .preinit_array :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } > m_text\r\n\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } > m_text\r\n\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } > m_text\r\n\r\n  __etext = .;    \/* define a global symbol at end of code *\/\r\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\r\n\r\n  __VECTOR_RAM = ORIGIN(m_interrupts);\r\n  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;\r\n\r\n  .data : AT(__DATA_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __DATA_RAM = .;\r\n    __data_start__ = .;      \/* create a global symbol at data start *\/\r\n    *(m_usb_dma_init_data)\r\n    *(.data)                 \/* .data sections *\/\r\n    *(.data*)                \/* .data* sections *\/\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    _net_buf_pool_list = .;\r\n    KEEP(*(SORT(._net_buf_pool*)))\r\n    . = ALIGN(4);\r\n    __data_end__ = .;        \/* define a global symbol at data end *\/\r\n  } > m_data\r\n  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);\r\n  .ncache.init : AT(__NDATA_ROM)\r\n  {\r\n    __noncachedata_start__ = .;   \/* create a global symbol at ncache data start *\/\r\n    *(NonCacheable.init)\r\n    . = ALIGN(4);\r\n    __noncachedata_init_end__ = .;   \/* create a global symbol at initialized ncache data end *\/\r\n  } > m_ncache\r\n  . = __noncachedata_init_end__;\r\n  .ncache :\r\n  {\r\n    *(NonCacheable)\r\n    . = ALIGN(4);\r\n    __noncachedata_end__ = .;     \/* define a global symbol at ncache data end *\/\r\n  } > m_ncache\r\n  __SDRAM_ROM = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);\r\n  .sdram_data : AT(__SDRAM_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_data_start__ = .;\r\n    KEEP(*(.sdram_data*))\r\n    . = ALIGN(4);\r\n    __sdram_data_end__ = .;\r\n  } > m_sdram\r\n\r\n  \/* Uninitialized data section *\/\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss section *\/\r\n    . = ALIGN(4);\r\n    __START_BSS = .;\r\n    __bss_start__ = .;\r\n    *(m_usb_dma_noninit_data)\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n    __END_BSS = .;\r\n  } > m_data\r\n  __DATA_END = __SDRAM_ROM;\r\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\r\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\r\n\r\n  .sdram_bss (NOLOAD) :\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_bss_start__ = .;\r\n    *(.sdram_bss*)\r\n    \/* edgefast_bluetooth_bss *\/\r\n    *lib_crypto_m7.a:*(.bss .bss*)\r\n    *libedgefast_bluetooth_internal.a:*(.bss .bss*)\r\n    *libethermind_ble_protocol.a:*(.bss .bss*)\r\n    *libethermind_ble_gatt.a:*(.bss .bss*)\r\n    *libethermind_ble_core.a:*(.bss .bss*)\r\n    *libethermind_ble_util.a:*(.bss .bss*)\r\n    . = ALIGN(4);\r\n    __sdram_bss_end__ = .;\r\n  } > m_sdram\r\n\r\n  .heap :\r\n  {\r\n    . = ALIGN(8);\r\n    __end__ = .;\r\n    PROVIDE(end = .);\r\n    __HeapBase = .;\r\n    . += HEAP_SIZE;\r\n    __HeapLimit = .;\r\n    __heap_limit = .; \/* Add for _sbrk *\/\r\n  } > m_heap\r\n\r\n  .stack :\r\n  {\r\n    . = ALIGN(8);\r\n    . += STACK_SIZE;\r\n  } > m_data\r\n\r\n  \/* Initializes stack on the end of block *\/\r\n  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);\r\n  __StackLimit = __StackTop - STACK_SIZE;\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d60c8496e343fbc932c3492e6cdc78b8c99c9217","subject":"soc\/intel_adsp: Put initial stack into the CPU0 interrupt stack","message":"soc\/intel_adsp: Put initial stack into the CPU0 interrupt stack\n\nZephyr's normal architecture is to do all initialization in the\ninterrupt stacks.  The CAVS code was traditionally written to start\nthe stack at the end of HP-SRAM, where it has no protection against\noverlap with other uses (e.g. MP startup used the same region for\nstacks and saw cache collisions, and the SOF heap lives in this area\ntoo).  Put it where Zephyr expects and we'll have fewer surprises.\n\nSigned-off-by: Andy Ross <c70f9a6bf6ee0cd69c8af4ce5e6b131945769315@intel.com>\n","repos":"nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v15\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v15\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n  *\/\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n\n  \/* Initial\/boot stack lives in the CPU0 interrupt stack *\/\n  __stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n  *\/\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9aae07d2bee166a7c337189e4c9dbb223b7fa237","subject":"binfmt\/libelf : place holder to keep user space heap object pointer","message":"binfmt\/libelf : place holder to keep user space heap object pointer\n\nUserspace memory allocator is statically linked to each application\nand hence it would leverage the allocator to use per app heap object\nwhich would be initialized during binary load time.\n\nSigned-off-by: Manohara HK <02db916c8fbcb3f412fbcb70556ea7b9f661857a@samsung.com>\n","repos":"junmin-kim\/TizenRT,pillip8282\/TizenRT,jeongchanKim\/TizenRT,chanijjani\/TizenRT,davidfather\/TizenRT,chanijjani\/TizenRT,junmin-kim\/TizenRT,jeongchanKim\/TizenRT,junmin-kim\/TizenRT,jeongchanKim\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT,an4967\/TizenRT,jeongarmy\/TizenRT,chanijjani\/TizenRT,jeongarmy\/TizenRT,sunghan-chang\/TizenRT,an4967\/TizenRT,pillip8282\/TizenRT,jeongarmy\/TizenRT,jeongchanKim\/TizenRT,jsdosa\/TizenRT,an4967\/TizenRT,jeongchanKim\/TizenRT,davidfather\/TizenRT,jeongchanKim\/TizenRT,sunghan-chang\/TizenRT,sunghan-chang\/TizenRT,junmin-kim\/TizenRT,chanijjani\/TizenRT,an4967\/TizenRT,sunghan-chang\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,junmin-kim\/TizenRT,junmin-kim\/TizenRT,Samsung\/TizenRT,Samsung\/TizenRT,pillip8282\/TizenRT,sunghan-chang\/TizenRT,pillip8282\/TizenRT,jeongarmy\/TizenRT,jsdosa\/TizenRT,Samsung\/TizenRT,davidfather\/TizenRT,jsdosa\/TizenRT,chanijjani\/TizenRT,sunghan-chang\/TizenRT,davidfather\/TizenRT,jeongarmy\/TizenRT,pillip8282\/TizenRT,chanijjani\/TizenRT,an4967\/TizenRT,an4967\/TizenRT,pillip8282\/TizenRT,jsdosa\/TizenRT,jsdosa\/TizenRT,junmin-kim\/TizenRT,davidfather\/TizenRT,davidfather\/TizenRT,Samsung\/TizenRT,Samsung\/TizenRT,davidfather\/TizenRT,Samsung\/TizenRT,chanijjani\/TizenRT,jeongarmy\/TizenRT,jsdosa\/TizenRT,jeongchanKim\/TizenRT,an4967\/TizenRT,jsdosa\/TizenRT","old_file":"os\/binfmt\/libelf\/gnu-elf.ld","new_file":"os\/binfmt\/libelf\/gnu-elf.ld","new_contents":"\/****************************************************************************\n *\n * Copyright 2019 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * os\/binfmt\/libelf\/gnu-elf.ld\n *\n *   Copyright (C) 2012 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nSECTIONS\n{\n  .text 0x00000000 :\n    {\n      _stext = . ;\n      \/* Place holder to keep the heap object at the top\n       * 4 bytes is reserved at the top of the text segment,\n       * which can be used to place user heap object, which\n       * eventually used by user space memory allocator\n       *\/\n      LONG(0);\n      *(.text)\n      *(.text.*)\n      *(.gnu.warning)\n      *(.stub)\n      *(.glue_7)\n      *(.glue_7t)\n      *(.jcr)\n\n      \/* C++ support:  The .init and .fini sections contain specific logic\n       * to manage static constructors and destructors.\n       *\/\n\n      *(.gnu.linkonce.t.*)\n      *(.init)             \/* Old ABI *\/\n      *(.fini)             \/* Old ABI *\/\n      _etext = . ;\n    }\n\n  .rodata :\n    {\n      _srodata = . ;\n      *(.rodata)\n      *(.rodata1)\n      *(.rodata.*)\n      *(.gnu.linkonce.r*)\n      _erodata = . ;\n    }\n\n  .data :\n    {\n      _sdata = . ;\n      *(.data)\n      *(.data1)\n      *(.data.*)\n      *(.gnu.linkonce.d*)\n      _edata = . ;\n    }\n\n  \/* C++ support. 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See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * os\/binfmt\/libelf\/gnu-elf.ld\n *\n *   Copyright (C) 2012 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nSECTIONS\n{\n  .text 0x00000000 :\n    {\n      _stext = . ;\n      *(.text)\n      *(.text.*)\n      *(.gnu.warning)\n      *(.stub)\n      *(.glue_7)\n      *(.glue_7t)\n      *(.jcr)\n\n      \/* C++ support:  The .init and .fini sections contain specific logic\n       * to manage static constructors and destructors.\n       *\/\n\n      *(.gnu.linkonce.t.*)\n      *(.init)             \/* Old ABI *\/\n      *(.fini)             \/* Old ABI *\/\n      _etext = . ;\n    }\n\n  .rodata :\n    {\n      _srodata = . ;\n      *(.rodata)\n      *(.rodata1)\n      *(.rodata.*)\n      *(.gnu.linkonce.r*)\n      _erodata = . ;\n    }\n\n  .data :\n    {\n      _sdata = . ;\n      *(.data)\n      *(.data1)\n      *(.data.*)\n      *(.gnu.linkonce.d*)\n      _edata = . ;\n    }\n\n  \/* C++ support. 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{"commit":"b5285a5fff55542f6ee9c6430c48de2cd4b0e034","subject":"Change alignment of Bootloader data section","message":"Change alignment of Bootloader data section\n\nUse 0x0400 rather than 0x1000 for aligning the Bootloader data section.\nMakes Bootloader .bin size smaller and helps with a seeprom 128k boundary\nproblem.\n\nChange-Id: I3e4f02213f704db22fdc875a2325352aae483cdf\nRTC: 152752\nReviewed-on: http:\/\/ralgit01.raleigh.ibm.com\/gerrit1\/23802\nTested-by: Jenkins Server\nTested-by: FSP CI Jenkins\nReviewed-by: Daniel M. Crowell <912029ca9254ac7b5854e56910561d682e1fa2d0@us.ibm.com>\nReviewed-by: Andrew J. Geissler <c46de238cd554860f0bd4010b1729f1323facd9c@us.ibm.com>\nReviewed-by: William G. Hoffa <7dd6aa5e78423995d9d7c7ecada5b77ee07f88cc@us.ibm.com>\n","repos":"open-power\/hostboot,open-power\/hostboot,open-power\/hostboot,open-power\/hostboot,open-power\/hostboot","old_file":"src\/bootloader.ld","new_file":"src\/bootloader.ld","new_contents":"\/* IBM_PROLOG_BEGIN_TAG                                                   *\/\n\/* This is an automatically generated prolog.                             *\/\n\/*                                                                        *\/\n\/* $Source: src\/bootloader.ld $                                           *\/\n\/*                                                                        *\/\n\/* OpenPOWER HostBoot Project                                             *\/\n\/*                                                                        *\/\n\/* Contributors Listed Below - COPYRIGHT 2015,2016                        *\/\n\/* [+] Google Inc.                                                        *\/\n\/* [+] International Business Machines Corp.                              *\/\n\/*                                                                        *\/\n\/*                                                                        *\/\n\/* Licensed under the Apache License, Version 2.0 (the \"License\");        *\/\n\/* you may not use this file except in compliance with the License.       *\/\n\/* You may obtain a copy of the License at                                *\/\n\/*                                                                        *\/\n\/*     http:\/\/www.apache.org\/licenses\/LICENSE-2.0                         *\/\n\/*                                                                        *\/\n\/* Unless required by applicable law or agreed to in writing, software    *\/\n\/* distributed under the License is distributed on an \"AS IS\" BASIS,      *\/\n\/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        *\/\n\/* implied. See the License for the specific language governing           *\/\n\/* permissions and limitations under the License.                         *\/\n\/*                                                                        *\/\n\/* IBM_PROLOG_END_TAG                                                     *\/\nbase_load_address = 0x00000000;\nsbe_hb_structures = 0x00000004;\n\/* @TODO-RTC:138273-Support multiple nodes using relative HRMOR *\/\n\/* Text section offset = 12KB (space reserved for exception vectors)      *\/\ntext_load_address = 0x00003000;\n\nSECTIONS\n{\n    . = base_load_address;\n\n    . = sbe_hb_structures;\n\n    . = text_load_address;\n    .text ALIGN(0x0020): {\n        *(.text.intvects)\n        *(.text.bootloaderasm)\n        *(.text)\n        *(.text._*)\n        *(.text.*)\n    }\n\n    .rodata ALIGN(0x8): {\n        __minimum_data_start_addr = ALIGN(0x400);\n        ctor_start_address = .;\n        *(.ctors)\n        *(.ctors.*)\n        ctor_end_address = .;\n        *(.rodata)\n        *(.rodata.*)\n        . = ALIGN(8);\n        toc_load_address = .;\n        *(.toc)\n        *(.opd)\n        *(.got)\n        *(.plt)\n        *(.data.rel.ro.*)\n        *(.data.*traceData_codeInfo*)\n\n        . = __minimum_data_start_addr > . ? __minimum_data_start_addr : .;\n    }\n\n    .data ALIGN(0x8): {\n        data_load_address = .;\n        *(.data)\n        *(.data.*)\n\n        *(.bss)\n        *(.bss.*)\n\n    }\n\n    end_load_address = .;\n\n    .rela : {\n        *(.rela.*)\n    }\n\n    .dynsym : { *(.dynsym) }\n    .dynstr : { *(.dynstr) }\n    .hash : { *(.hash) }\n    .gnu.hash : { *(.gnu.hash) }\n    .eh_frame : { *(.eh_frame) }\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.gnu.attributes)\n        *(.dtors)\n        *(.interp)\n    }\n}\n\n\n","old_contents":"\/* IBM_PROLOG_BEGIN_TAG                                                   *\/\n\/* This is an automatically generated prolog.                             *\/\n\/*                                                                        *\/\n\/* $Source: src\/bootloader.ld $                                           *\/\n\/*                                                                        *\/\n\/* OpenPOWER HostBoot Project                                             *\/\n\/*                                                                        *\/\n\/* Contributors Listed Below - COPYRIGHT 2015,2016                        *\/\n\/* [+] Google Inc.                                                        *\/\n\/* [+] International Business Machines Corp.                              *\/\n\/*                                                                        *\/\n\/*                                                                        *\/\n\/* Licensed under the Apache License, Version 2.0 (the \"License\");        *\/\n\/* you may not use this file except in compliance with the License.       *\/\n\/* You may obtain a copy of the License at                                *\/\n\/*                                                                        *\/\n\/*     http:\/\/www.apache.org\/licenses\/LICENSE-2.0                         *\/\n\/*                                                                        *\/\n\/* Unless required by applicable law or agreed to in writing, software    *\/\n\/* distributed under the License is distributed on an \"AS IS\" BASIS,      *\/\n\/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        *\/\n\/* implied. See the License for the specific language governing           *\/\n\/* permissions and limitations under the License.                         *\/\n\/*                                                                        *\/\n\/* IBM_PROLOG_END_TAG                                                     *\/\nbase_load_address = 0x00000000;\nsbe_hb_structures = 0x00000004;\n\/* @TODO-RTC:138273-Support multiple nodes using relative HRMOR *\/\n\/* Text section offset = 12KB (space reserved for exception vectors)      *\/\ntext_load_address = 0x00003000;\n\nSECTIONS\n{\n    . = base_load_address;\n\n    . = sbe_hb_structures;\n\n    . = text_load_address;\n    .text ALIGN(0x0020): {\n        *(.text.intvects)\n        *(.text.bootloaderasm)\n        *(.text)\n        *(.text._*)\n        *(.text.*)\n    }\n\n    .rodata ALIGN(0x8): {\n        __minimum_data_start_addr = ALIGN(0x1000);\n        ctor_start_address = .;\n        *(.ctors)\n        *(.ctors.*)\n        ctor_end_address = .;\n        *(.rodata)\n        *(.rodata.*)\n        . = ALIGN(8);\n        toc_load_address = .;\n        *(.toc)\n        *(.opd)\n        *(.got)\n        *(.plt)\n        *(.data.rel.ro.*)\n        *(.data.*traceData_codeInfo*)\n\n        . = __minimum_data_start_addr > . ? __minimum_data_start_addr : .;\n    }\n\n    .data ALIGN(0x8): {\n        data_load_address = .;\n        *(.data)\n        *(.data.*)\n\n        *(.bss)\n        *(.bss.*)\n\n    }\n\n    end_load_address = .;\n\n    .rela : {\n        *(.rela.*)\n    }\n\n    .dynsym : { *(.dynsym) }\n    .dynstr : { *(.dynstr) }\n    .hash : { *(.hash) }\n    .gnu.hash : { *(.gnu.hash) }\n    .eh_frame : { *(.eh_frame) }\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.gnu.attributes)\n        *(.dtors)\n        *(.interp)\n    }\n}\n\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a5a6912b0ed34247ec9df89b3db302df37213e58","subject":"Fix Musca-A1 gcc linker","message":"Fix Musca-A1 gcc linker\n\nWas broken since 3e3af70afcb8e86df95355d0ff083c98756da6e3\n\nSigned-off-by: Gabor Abonyi <e4198cbaaa2c2532d1747e522da7f23726de9d53@arm.com>\n","repos":"mbedmicro\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed","old_file":"targets\/TARGET_ARM_SSG\/TARGET_MUSCA_A1\/TARGET_MUSCA_A1_S\/device\/TOOLCHAIN_GCC_ARM\/musca_s.ld","new_file":"targets\/TARGET_ARM_SSG\/TARGET_MUSCA_A1\/TARGET_MUSCA_A1_S\/device\/TOOLCHAIN_GCC_ARM\/musca_s.ld","new_contents":";\/*\n; * Copyright (c) 2018-2019 ARM Limited\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the \"License\");\n; * you may not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an \"AS IS\" BASIS,\n; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; *\n; * This file is derivative of CMSIS V5.00 gcc_arm.ld\n; *\/\n\n\/*********** WARNING: This is an auto-generated file. Do not edit! ***********\/\n\n\/* Linker script to configure memory regions. *\/\n\/* This file will be run trough the pre-processor. *\/\n\n#include \"..\/..\/..\/partition\/region_defs.h\"\n\n#if !defined(TFM_LVL)\n  #define TFM_LVL   1\n#endif\n\nMEMORY\n{\n  FLASH   (rx)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE\n  RAM     (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE\n  VENEERS (rx)  : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE\n}\n\nHEAP_SIZE = S_HEAP_SIZE;\n__heap_size__  = S_HEAP_SIZE;\n__psp_stack_size__ = S_PSP_STACK_SIZE;\n__msp_init_stack_size__ = S_MSP_STACK_SIZE;\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a)\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .TFM_VECTORS : ALIGN(4)\n    {\n        __vectors_start__ = .;\n        KEEP(*(.vectors))\n        *startup*(.text*)\n        . = ALIGN(4);\n        __vectors_end__ = .;\n    } > FLASH\n\n#if TFM_LVL == 1\n    .copy.table : ALIGN(4)\n    {\n        __copy_table_start__ = .;\n        LONG (LOADADDR(.TFM_DATA))\n        LONG (ADDR(.TFM_DATA))\n        LONG (SIZEOF(.TFM_DATA))\n        __copy_table_end__ = .;\n    } > FLASH\n\n    .zero.table : ALIGN(4)\n    {\n        __zero_table_start__ = .;\n        LONG (ADDR(.TFM_BSS))\n        LONG (SIZEOF(.TFM_BSS))\n        LONG (ADDR(.TFM_SECURE_STACK))\n        LONG (SIZEOF(.TFM_SECURE_STACK))\n        LONG (ADDR(.TFM_UNPRIV_SCRATCH))\n        LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))\n        __zero_table_end__ = .;\n    } > FLASH\n\n#else \/* TFM_LVL == 1 *\/\n    .copy.table : ALIGN(4)\n    {\n        __copy_table_start__ = .;\n        LONG (LOADADDR(.TFM_DATA))\n        LONG (ADDR(.TFM_DATA))\n        LONG (SIZEOF(.TFM_DATA))\n        LONG (LOADADDR(.TFM_UNPRIV_RO_DATA))\n        LONG (ADDR(.TFM_UNPRIV_RO_DATA))\n        LONG (SIZEOF(.TFM_UNPRIV_RO_DATA))\n        LONG (LOADADDR(.TFM_SP_PLATFORM_DATA))\n        LONG (ADDR(.TFM_SP_PLATFORM_DATA))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_DATA))\n        __copy_table_end__ = .;\n    } > FLASH\n\n    .zero.table : ALIGN(4)\n    {\n        __zero_table_start__ = .;\n        LONG (ADDR(.TFM_BSS))\n        LONG (SIZEOF(.TFM_BSS))\n        LONG (ADDR(.TFM_UNPRIV_RO_BSS))\n        LONG (SIZEOF(.TFM_UNPRIV_RO_BSS))\n        LONG (ADDR(.TFM_SP_PLATFORM_BSS))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_BSS))\n        LONG (ADDR(.TFM_SP_PLATFORM_STACK))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_STACK))\n        LONG (ADDR(.TFM_UNPRIV_SCRATCH))\n        LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))\n        __zero_table_end__ = .;\n    } > FLASH\n\n    .TFM_UNPRIV_CODE : ALIGN(32)\n    {\n        *libc_nano*:*(.text*)\n        *libc_nano*:*(.rodata*)\n        *tfm_spm_services.o(.text*)\n        *tfm_spm_services.o(.rodata*)\n        *platform_retarget_dev.o(.text*)\n        *platform_retarget_dev.o(.rodata*)\n        *(SFN)\n        *libgcc*:*(.text*)\n        *libgcc*:*(.rodata*)\n        . = ALIGN(32);\n    } > FLASH\n    Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);\n    Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);\n\n    .TFM_SP_PLATFORM : ALIGN(32)\n    {\n        *tfm_platform*:*(.text*)\n        *tfm_platform*:*(.rodata*)\n        *(TFM_SP_PLATFORM_ATTR_FN)\n        . = ALIGN(32);\n    } > FLASH\n    Image$$TFM_SP_PLATFORM$$RO$$Base = ADDR(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$RO$$Limit = ADDR(.TFM_SP_PLATFORM) + SIZEOF(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$Base = ADDR(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$Limit = ADDR(.TFM_SP_PLATFORM) + SIZEOF(.TFM_SP_PLATFORM);\n\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n#endif \/* TFM_LVL == 1 *\/\n\n    .ER_TFM_CODE :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n         *crtbegin.o(.dtors)\n         *crtbegin?.o(.dtors)\n         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n         *(SORT(.dtors.*))\n         *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    OVERLAY S_DATA_START :\n    {\n        \/* shared_data and msp_stack are overlapping on purpose when\n        * msp_stack is extended until the beginning of RAM, when shared_date\n        * was read out by partitions\n        *\/\n        .tfm_bl2_shared_data\n        {\n            . = ALIGN(32);\n            . += BOOT_TFM_SHARED_DATA_SIZE;\n        }\n\n        .msp_stack\n        {\n            . =  ALIGN(32);\n            . += S_MSP_STACK_SIZE;\n        }\n    } > RAM\n\n    Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);\n\n    .psp_stack :\n    {\n        . =  ALIGN(32);\n        . += S_PSP_STACK_SIZE;\n    } > RAM\n    Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);\n    Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);\n\n#if TFM_LVL == 1\n\n    .heap :\n    {\n        . = ALIGN(8);\n        __end__ = .;\n        PROVIDE(end = .);\n        __HeapBase = .;\n        . += S_HEAP_SIZE;\n        __HeapLimit = .;\n        __heap_limit = .; \/* Add for _sbrk *\/\n    } > RAM\n    Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);\n    Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);\n\n    .TFM_SECURE_STACK :\n    {\n        . = ALIGN(128);\n        . += 0x1000;\n    } > RAM\n    Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);\n    Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);\n\n    .TFM_UNPRIV_SCRATCH :\n    {\n        . = ALIGN(32);\n        . += 0x400;\n    } > RAM\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);\n#else \/* TFM_LVL == 1 *\/\n    .TFM_UNPRIV_RO_DATA :\n    {\n        *\/tfm_spm_services.o(.data*)\n        *\/platform_retarget_dev.o(.data*)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_RO_DATA$$RW$$Base = ADDR(.TFM_UNPRIV_RO_DATA);\n    Image$$TFM_UNPRIV_RO_DATA$$RW$$Limit = ADDR(.TFM_UNPRIV_RO_DATA) + SIZEOF(.TFM_UNPRIV_RO_DATA);\n\n    .TFM_UNPRIV_RO_BSS : ALIGN(32)\n    {\n        *\/tfm_spm_services.o(.bss*)\n        *\/platform_retarget_dev.o(.bss*)\n        *\/tfm_spm_services.o(COMMON)\n        *\/platform_retarget_dev.o(COMMON)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_RO_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_RO_BSS);\n    Image$$TFM_UNPRIV_RO_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_RO_BSS) + SIZEOF(.TFM_UNPRIV_RO_BSS);\n\n    .TFM_UNPRIV_SCRATCH : ALIGN(32)\n    {\n        . += 0x400;\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);\n\n    .TFM_SP_PLATFORM_DATA : ALIGN(32)\n    {\n        *tfm_platform*:*(.data*)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_DATA$$RW$$Base = ADDR(.TFM_SP_PLATFORM_DATA);\n    Image$$TFM_SP_PLATFORM_DATA$$RW$$Limit = ADDR(.TFM_SP_PLATFORM_DATA) + SIZEOF(.TFM_SP_PLATFORM_DATA);\n\n    .TFM_SP_PLATFORM_BSS : ALIGN(32)\n    {\n        *tfm_platform*:*(.bss*)\n        *tfm_platform*:*(COMMON)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_DATA$$ZI$$Base = ADDR(.TFM_SP_PLATFORM_BSS);\n    Image$$TFM_SP_PLATFORM_DATA$$ZI$$Limit = ADDR(.TFM_SP_PLATFORM_BSS) + SIZEOF(.TFM_SP_PLATFORM_BSS);\n\n    .TFM_SP_PLATFORM_STACK : ALIGN(128)\n    {\n        . += 0x0400;\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_STACK$$ZI$$Base = ADDR(.TFM_SP_PLATFORM_STACK);\n    Image$$TFM_SP_PLATFORM_STACK$$ZI$$Limit = ADDR(.TFM_SP_PLATFORM_STACK) + SIZEOF(.TFM_SP_PLATFORM_STACK);\n\n#endif \/* TFM_LVL == 1 *\/\n\n    .TFM_DATA :\n    {\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n\n    } > RAM AT> FLASH\n    Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);\n    Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);\n\n    .TFM_BSS :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);\n    Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);\n\n    Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA);\n    Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS);\n\n    ASSERT(Image$$ER_TFM_DATA$$Limit <= S_DATA_START + S_DATA_SIZE, \"Exceeding secure RAM\")\n\n    \/*\n     * Place the CMSE Veneers (containing the SG instruction) after the code, in a\n     * separate 32 bytes aligned region so that the SAU can programmed to just set\n     * this region as Non-Secure Callable.\n     *\/\n    .gnu.sgstubs : ALIGN(32)\n    {\n        *(.gnu.sgstubs*)\n        . = ALIGN(32);\n    } > VENEERS AT> VENEERS\n    Image$$ER_CODE_CMSE_VENEER$$Base = ADDR(.gnu.sgstubs);\n    Image$$ER_CODE_CMSE_VENEER$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);\n\n    Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START;\n\n    Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START;\n\n    PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);\n    PROVIDE(__StackTop = __stack);\n    PROVIDE(__StackLimit = __StackTop - SIZEOF(.psp_stack));\n}\n","old_contents":";\/*\n; * Copyright (c) 2018-2019 ARM Limited\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the \"License\");\n; * you may not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an \"AS IS\" BASIS,\n; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; *\n; * This file is derivative of CMSIS V5.00 gcc_arm.ld\n; *\/\n\n\/*********** WARNING: This is an auto-generated file. Do not edit! ***********\/\n\n\/* Linker script to configure memory regions. *\/\n\/* This file will be run trough the pre-processor. *\/\n\n#include \"..\/..\/..\/partition\/region_defs.h\"\n\n#if !defined(TFM_LVL)\n  #define TFM_LVL   1\n#endif\n\nMEMORY\n{\n  FLASH   (rx)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE\n  RAM     (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE\n  VENEERS (rx)  : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE\n}\n\nHEAP_SIZE = S_HEAP_SIZE;\n__heap_size__  = S_HEAP_SIZE;\n__psp_stack_size__ = S_PSP_STACK_SIZE;\n__msp_init_stack_size__ = S_MSP_STACK_SIZE;\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a)\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .TFM_VECTORS : ALIGN(4)\n    {\n        __vectors_start__ = .;\n        KEEP(*(.vectors))\n        *startup*(.text*)\n        . = ALIGN(4);\n        __vectors_end__ = .;\n    } > FLASH\n\n#if TFM_LVL == 1\n    .copy.table : ALIGN(4)\n    {\n        __copy_table_start__ = .;\n        LONG (LOADADDR(.TFM_DATA))\n        LONG (ADDR(.TFM_DATA))\n        LONG (SIZEOF(.TFM_DATA))\n        __copy_table_end__ = .;\n    } > FLASH\n\n    .zero.table : ALIGN(4)\n    {\n        __zero_table_start__ = .;\n        LONG (ADDR(.TFM_BSS))\n        LONG (SIZEOF(.TFM_BSS))\n        LONG (ADDR(.TFM_SECURE_STACK))\n        LONG (SIZEOF(.TFM_SECURE_STACK))\n        LONG (ADDR(.TFM_UNPRIV_SCRATCH))\n        LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))\n        __zero_table_end__ = .;\n    } > FLASH\n\n#else \/* TFM_LVL == 1 *\/\n    .copy.table : ALIGN(4)\n    {\n        __copy_table_start__ = .;\n        LONG (LOADADDR(.TFM_DATA))\n        LONG (ADDR(.TFM_DATA))\n        LONG (SIZEOF(.TFM_DATA))\n        LONG (LOADADDR(.TFM_UNPRIV_RO_DATA))\n        LONG (ADDR(.TFM_UNPRIV_RO_DATA))\n        LONG (SIZEOF(.TFM_UNPRIV_RO_DATA))\n        LONG (LOADADDR(.TFM_SP_PLATFORM_DATA))\n        LONG (ADDR(.TFM_SP_PLATFORM_DATA))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_DATA))\n        __copy_table_end__ = .;\n    } > FLASH\n\n    .zero.table : ALIGN(4)\n    {\n        __zero_table_start__ = .;\n        LONG (ADDR(.TFM_BSS))\n        LONG (SIZEOF(.TFM_BSS))\n        LONG (ADDR(.TFM_UNPRIV_RO_BSS))\n        LONG (SIZEOF(.TFM_UNPRIV_RO_BSS))\n        LONG (ADDR(.TFM_SP_PLATFORM_BSS))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_BSS))\n        LONG (ADDR(.TFM_SP_PLATFORM_STACK))\n        LONG (SIZEOF(.TFM_SP_PLATFORM_STACK))\n        LONG (ADDR(.TFM_UNPRIV_SCRATCH))\n        LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))\n        __zero_table_end__ = .;\n    } > FLASH\n\n    .TFM_UNPRIV_CODE : ALIGN(32)\n    {\n        *libc_nano*:*(.text*)\n        *libc_nano*:*(.rodata*)\n        *tfm_spm_services.o(.text*)\n        *tfm_spm_services.o(.rodata*)\n        *platform_retarget_dev.o(.text*)\n        *platform_retarget_dev.o(.rodata*)\n        *(SFN)\n        *libgcc*:*(.text*)\n        *libgcc*:*(.rodata*)\n        . = ALIGN(32);\n    } > FLASH\n    Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);\n    Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);\n\n    .TFM_SP_PLATFORM : ALIGN(32)\n    {\n        *tfm_platform*:*(.text*)\n        *tfm_platform*:*(.rodata*)\n        *(TFM_SP_PLATFORM_ATTR_FN)\n        . = ALIGN(32);\n    } > FLASH\n    Image$$TFM_SP_PLATFORM$$RO$$Base = ADDR(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$RO$$Limit = ADDR(.TFM_SP_PLATFORM) + SIZEOF(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$Base = ADDR(.TFM_SP_PLATFORM);\n    Image$$TFM_SP_PLATFORM$$Limit = ADDR(.TFM_SP_PLATFORM) + SIZEOF(.TFM_SP_PLATFORM);\n\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n#endif \/* TFM_LVL == 1 *\/\n\n    .ER_TFM_CODE :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n         *crtbegin.o(.dtors)\n         *crtbegin?.o(.dtors)\n         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n         *(SORT(.dtors.*))\n         *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    OVERLAY S_DATA_START :\n    {\n        \/* shared_data and msp_stack are overlapping on purpose when\n        * msp_stack is extended until the beginning of RAM, when shared_date\n        * was read out by partitions\n        *\/\n        .tfm_bl2_shared_data\n        {\n            . = ALIGN(32);\n            . += BOOT_TFM_SHARED_DATA_SIZE;\n        }\n\n        .msp_stack\n        {\n            . =  ALIGN(32);\n            . += S_MSP_STACK_SIZE;\n        }\n    } > RAM\n\n    Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);\n\n    .psp_stack :\n    {\n        . =  ALIGN(32);\n        . += S_PSP_STACK_SIZE;\n    } > RAM\n    Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);\n    Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);\n\n#if TFM_LVL == 1\n\n    .heap :\n    {\n        . = ALIGN(8);\n        __end__ = .;\n        PROVIDE(end = .);\n        __HeapBase = .;\n        . += S_HEAP_SIZE;\n        __HeapLimit = .;\n        __heap_limit = .; \/* Add for _sbrk *\/\n    } > RAM\n    Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap);\n    Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);\n\n    .TFM_SECURE_STACK :\n    {\n        . = ALIGN(128);\n        . += 0x1000;\n    } > RAM\n    Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);\n    Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);\n\n    .TFM_UNPRIV_SCRATCH :\n    {\n        . = ALIGN(32);\n        . += 0x400;\n    } > RAM\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);\n#else \/* TFM_LVL == 1 *\/\n    .TFM_UNPRIV_RO_DATA :\n    {\n        *\/tfm_spm_services.o(.data*)\n        *\/platform_retarget_dev.o(.data*)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_RO_DATA$$RW$$Base = ADDR(.TFM_UNPRIV_RO_DATA);\n    Image$$TFM_UNPRIV_RO_DATA$$RW$$Limit = ADDR(.TFM_UNPRIV_RO_DATA) + SIZEOF(.TFM_UNPRIV_RO_DATA);\n\n    .TFM_UNPRIV_RO_BSS : ALIGN(32)\n    {\n        *\/tfm_spm_services.o(.bss*)\n        *\/platform_retarget_dev.o(.bss*)\n        *\/tfm_spm_services.o(COMMON)\n        *\/platform_retarget_dev.o(COMMON)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_RO_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_RO_BSS);\n    Image$$TFM_UNPRIV_RO_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_RO_BSS) + SIZEOF(.TFM_UNPRIV_RO_BSS);\n\n    .TFM_UNPRIV_SCRATCH : ALIGN(32)\n    {\n        . += 0x400;\n    } > RAM AT> FLASH\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);\n    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);\n\n    .TFM_SP_PLATFORM_DATA : ALIGN(32)\n    {\n        *tfm_platform*:*(.data*)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_DATA$$RW$$Base = ADDR(.TFM_SP_PLATFORM_DATA);\n    Image$$TFM_SP_PLATFORM_DATA$$RW$$Limit = ADDR(.TFM_SP_PLATFORM_DATA) + SIZEOF(.TFM_SP_PLATFORM_DATA);\n\n    .TFM_SP_PLATFORM_BSS : ALIGN(32)\n    {\n        *tfm_platform*:*(.bss*)\n        *tfm_platform*:*(COMMON)\n        . = ALIGN(32);\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_DATA$$ZI$$Base = ADDR(.TFM_SP_PLATFORM_BSS);\n    Image$$TFM_SP_PLATFORM_DATA$$ZI$$Limit = ADDR(.TFM_SP_PLATFORM_BSS) + SIZEOF(.TFM_SP_PLATFORM_BSS);\n\n    .TFM_SP_PLATFORM_STACK : ALIGN(128)\n    {\n        . += 0x0400;\n    } > RAM AT> FLASH\n    Image$$TFM_SP_PLATFORM_STACK$$ZI$$Base = ADDR(.TFM_SP_PLATFORM_STACK);\n    Image$$TFM_SP_PLATFORM_STACK$$ZI$$Limit = ADDR(.TFM_SP_PLATFORM_STACK) + SIZEOF(.TFM_SP_PLATFORM_STACK);\n\n#endif \/* TFM_LVL == 1 *\/\n\n    .TFM_DATA :\n    {\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n\n    } > RAM AT> FLASH\n    Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);\n    Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);\n\n    .TFM_BSS :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);\n    Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);\n\n    Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA);\n    Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS);\n\n    ASSERT(Image$$ER_TFM_DATA$$Limit <= S_DATA_START + S_DATA_SIZE, \"Exceeding secure RAM\")\n\n    \/*\n     * Place the CMSE Veneers (containing the SG instruction) after the code, in a\n     * separate 32 bytes aligned region so that the SAU can programmed to just set\n     * this region as Non-Secure Callable.\n     *\/\n    .gnu.sgstubs : ALIGN(32)\n    {\n        *(.gnu.sgstubs*)\n        . = ALIGN(32);\n    } > VENEERS AT> VENEERS\n    Image$$ER_CODE_CMSE_VENEER$$Base = ADDR(.gnu.sgstubs);\n    Image$$ER_CODE_CMSE_VENEER$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);\n\n    Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START;\n\n    Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START;\n\n    PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1d802028cf9383e412b2290ee76450f1790c720c","subject":"NUCLEO_L476RG: GCC_ARM ld file fix","message":"NUCLEO_L476RG: GCC_ARM ld file fix\n\nFollowing\nMerge pull request #4063 from LMESTM\/17q2_L4_bootloader\nthe NUCLEO_L476RG binairies could not boot anymore.\n\nThe change done in #4063 was derived from work on NUCLEO_L429ZI target\nwhich supports uvisor. The VECTORS defintiion is introduced as part of\nuvisor support and requires further changes in ld file which were missing.\nAs uvisor is not considered yet, we remove VECTORS for now and will\nintroduce only when needed.\n","repos":"nRFMesh\/mbed-os,c1728p9\/mbed-os,monkiineko\/mbed-os,andcor02\/mbed-os,catiedev\/mbed-os,mbedmicro\/mbed,HeadsUpDisplayInc\/mbed,karsev\/mbed-os,adamgreen\/mbed,YarivCol\/mbed-os,bcostm\/mbed-os,CalSol\/mbed,mbedmicro\/mbed,ryankurte\/mbed-os,ryankurte\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,pradeep-gr\/mbed-os5-onsemi,c1728p9\/mbed-os,Archcady\/mbed-os,fahhem\/mbed-os,andcor02\/mbed-os,karsev\/mbed-os,adamgreen\/mbed,nRFMesh\/mbed-os,fahhem\/mbed-os,svogl\/mbed-os,ryankurte\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,svogl\/mbed-os,mbedmicro\/mbed,Archcady\/mbed-os,fahhem\/mbed-os,infinnovation\/mbed-os,c1728p9\/mbed-os,YarivCol\/mbed-os,fahhem\/mbed-os,betzw\/mbed-os,svogl\/mbed-os,YarivCol\/mbed-os,YarivCol\/mbed-os,bcostm\/mbed-os,nRFMesh\/mbed-os,fahhem\/mbed-os,c1728p9\/mbed-os,bcostm\/mbed-os,Archcady\/mbed-os,catiedev\/mbed-os,Archcady\/mbed-os,infinnovation\/mbed-os,CalSol\/mbed,andcor02\/mbed-os,HeadsUpDisplayInc\/mbed,betzw\/mbed-os,monkiineko\/mbed-os,svogl\/mbed-os,Archcady\/mbed-os,pradeep-gr\/mbed-os5-onsemi,adamgreen\/mbed,mazimkhan\/mbed-os,catiedev\/mbed-os,c1728p9\/mbed-os,pradeep-gr\/mbed-os5-onsemi,nRFMesh\/mbed-os,karsev\/mbed-os,monkiineko\/mbed-os,ryankurte\/mbed-os,CalSol\/mbed,pradeep-gr\/mbed-os5-onsemi,betzw\/mbed-os,NXPmicro\/mbed,HeadsUpDisplayInc\/mbed,svogl\/mbed-os,CalSol\/mbed,mazimkhan\/mbed-os,infinnovation\/mbed-os,catiedev\/mbed-os,mazimkhan\/mbed-os,Archcady\/mbed-os,infinnovation\/mbed-os,karsev\/mbed-os,adamgreen\/mbed,kjbracey-arm\/mbed,c1728p9\/mbed-os,kjbracey-arm\/mbed,mazimkhan\/mbed-os,CalSol\/mbed,monkiineko\/mbed-os,adamgreen\/mbed,andcor02\/mbed-os,bcostm\/mbed-os,mbedmicro\/mbed,fahhem\/mbed-os,HeadsUpDisplayInc\/mbed,infinnovation\/mbed-os,catiedev\/mbed-os,nRFMesh\/mbed-os,HeadsUpDisplayInc\/mbed,pradeep-gr\/mbed-os5-onsemi,NXPmicro\/mbed,monkiineko\/mbed-os,NXPmicro\/mbed,betzw\/mbed-os,NXPmicro\/mbed,betzw\/mbed-os,HeadsUpDisplayInc\/mbed,YarivCol\/mbed-os,monkiineko\/mbed-os,karsev\/mbed-os,betzw\/mbed-os,mazimkhan\/mbed-os,nRFMesh\/mbed-os,NXPmicro\/mbed,adamgreen\/mbed,ryankurte\/mbed-os,YarivCol\/mbed-os,karsev\/mbed-os,NXPmicro\/mbed,bcostm\/mbed-os,catiedev\/mbed-os,svogl\/mbed-os,CalSol\/mbed,mazimkhan\/mbed-os,kjbracey-arm\/mbed,pradeep-gr\/mbed-os5-onsemi,infinnovation\/mbed-os,bcostm\/mbed-os,ryankurte\/mbed-os","old_file":"targets\/TARGET_STM\/TARGET_STM32L4\/TARGET_STM32L476xG\/device\/TOOLCHAIN_GCC_ARM\/STM32L476XX.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32L4\/TARGET_STM32L476xG\/device\/TOOLCHAIN_GCC_ARM\/STM32L476XX.ld","new_contents":"#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 2048k\n#endif\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188\n  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > SRAM1\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > SRAM1\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > SRAM1\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SRAM1\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 2048k\n#endif\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x400\n  FLASH (rx)   : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400\n  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188\n  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > SRAM1\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > SRAM1\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > SRAM1\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SRAM1\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f4dc5ac565d6e2cbcaa2dc43f1122e2364b70ecc","subject":"linker: Use a different macro to set vma for the noinit section","message":"linker: Use a different macro to set vma for the noinit section\n\nThe two macros are the same in this context. But an SoC may\nredefine the GROUP_LINK_IN() macro which could introduce an\nunintended change in this part of the linker script.\n\nSigned-off-by: Andriy Gelman <9b800b50c068448b0612a5bdc33ac199b44926a7@gmail.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr","old_file":"include\/zephyr\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_file":"include\/zephyr\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/devicetree_regions.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGIONS()\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t__rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\t. = ALIGN(4);\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__text_region_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - ADDR(rom_start));\n\t__rom_region_end = __rom_region_start + . - ADDR(rom_start);\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    GROUP_START(DATA_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_region_start = .;\n\t__data_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\t__data_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    \/* Sections generated from 'zephyr,memory-region' nodes *\/\n    LINKER_DT_SECTIONS()\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/devicetree_regions.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGIONS()\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t__rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\t. = ALIGN(4);\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__text_region_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - ADDR(rom_start));\n\t__rom_region_end = __rom_region_start + . - ADDR(rom_start);\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    GROUP_START(DATA_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_region_start = .;\n\t__data_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\t__data_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    \/* Sections generated from 'zephyr,memory-region' nodes *\/\n    LINKER_DT_SECTIONS()\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"56f84b60edd241eff9260ec7130e6dc48d1e77d4","subject":"tests: fix some issues when enabling coverage for qemu_x86_64","message":"tests: fix some issues when enabling coverage for qemu_x86_64\n\nFix some issues in linker.ld when enabling coverage report feature\nfor qemu_x86_64 platform:\n1. Fix the gcov record data should not be in BSS section.\n2. Fix some test case crash due to lack of memory page align before\ngcov rodata.\n\nSigned-off-by: Enjia Mai <233e651694b7770d0f980a273a8e4a6f7e2a84d4@intel.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/x86\/intel64\/linker.ld","new_file":"include\/arch\/x86\/intel64\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corp.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION RAM\n#define RAMABLE_REGION RAM\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\t\/*\n\t * The \"locore\" must be in the 64K of RAM, so that 16-bit code (with\n\t * segment registers == 0x0000) and 32\/64-bit code agree on addresses.\n\t * ... there is no 16-bit code yet, but there will be when we add SMP.\n\t *\/\n\n\t.locore : ALIGN(16)\n\t{\n\t_locore_start = .;\n\t*(.locore)\n\t*(.locore.*)\n\tMMU_PAGE_ALIGN\n\t_locore_end = .;\n\n\t_lorodata_start = .;\n\t*(.lorodata)\n\tMMU_PAGE_ALIGN\n\t_lodata_start = .;\n\n\t*(.lodata)\n\n#ifdef CONFIG_X86_KPTI\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\n\t * On x86-64 the IDT is in rodata and doesn't need to be in the\n\t * trampoline page.\n\t *\/\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_start = .;\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t*(.tss)\n\t*(.gdt)\n\n#ifdef CONFIG_X86_KPTI\n\t*(.trampolines)\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\tMMU_PAGE_ALIGN\n\t_lodata_end = .;\n\t} > LOCORE\n\n\t_locore_size = _lorodata_start - _locore_start;\n\t_lorodata_size = _lodata_start - _lorodata_start;\n\t_lodata_size = _lodata_end - _lodata_start;\n\n\t\/*\n\t * The rest of the system is loaded in \"normal\" memory (typically\n\t * placed above 1MB to avoid the by memory hole at 0x90000-0xFFFFF).\n\t *\/\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_rom_start = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(.text.*)\n\n\t#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n\t#include <linker\/common-rom.ld>\n\t#include <linker\/thread-local-storage.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t*(.rodata)\n\t*(.rodata.*)\n\n\tMMU_PAGE_ALIGN\n\t#include <snippets-rodata.ld>\n\n#ifdef CONFIG_X86_MMU\n\t. = ALIGN(8);\n\t_mmu_region_list_start = .;\n\tKEEP(*(\"._mmu_region.static.*\"))\n\t_mmu_region_list_end = .;\n#endif \/* CONFIG_X86_MMU *\/\n\n\t#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\t_image_rom_end = .;\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\/* This should be put here before BSS section, otherwise the .bss.__gcov will\n * be put in BSS section. That causes gcov not work properly *\/\n#include <snippets-ram-sections.ld>\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\tMMU_PAGE_ALIGN\n#ifndef CONFIG_USERSPACE\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\t*(.bss)\n\t*(.bss.*)\n\t*(COMMON)\n\t. = ALIGN(4);\t\/* so __bss_num_dwords is exact *\/\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_dwords = (__bss_end - __bss_start) >> 2;\n\n#include <linker\/common-noinit.ld>\n\n#include <snippets-sections.ld>\n\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t*(.data)\n\t*(.data.*)\n\t#include <snippets-rwdata.ld>\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <linker\/kobject.ld>\n\n\t_image_ram_end = .;\n\t_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ :\n\t{\n\t*(.got)\n\t*(.got.plt)\n\t*(.igot)\n\t*(.igot.plt)\n\t*(.iplt)\n\t*(.plt)\n\t*(.note.GNU-stack)\n\t*(.rel.*)\n\t*(.rela.*)\n\t}\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corp.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION RAM\n#define RAMABLE_REGION RAM\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\t\/*\n\t * The \"locore\" must be in the 64K of RAM, so that 16-bit code (with\n\t * segment registers == 0x0000) and 32\/64-bit code agree on addresses.\n\t * ... there is no 16-bit code yet, but there will be when we add SMP.\n\t *\/\n\n\t.locore : ALIGN(16)\n\t{\n\t_locore_start = .;\n\t*(.locore)\n\t*(.locore.*)\n\tMMU_PAGE_ALIGN\n\t_locore_end = .;\n\n\t_lorodata_start = .;\n\t*(.lorodata)\n\tMMU_PAGE_ALIGN\n\t_lodata_start = .;\n\n\t*(.lodata)\n\n#ifdef CONFIG_X86_KPTI\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\n\t * On x86-64 the IDT is in rodata and doesn't need to be in the\n\t * trampoline page.\n\t *\/\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_start = .;\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t*(.tss)\n\t*(.gdt)\n\n#ifdef CONFIG_X86_KPTI\n\t*(.trampolines)\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\tMMU_PAGE_ALIGN\n\t_lodata_end = .;\n\t} > LOCORE\n\n\t_locore_size = _lorodata_start - _locore_start;\n\t_lorodata_size = _lodata_start - _lorodata_start;\n\t_lodata_size = _lodata_end - _lodata_start;\n\n\t\/*\n\t * The rest of the system is loaded in \"normal\" memory (typically\n\t * placed above 1MB to avoid the by memory hole at 0x90000-0xFFFFF).\n\t *\/\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_rom_start = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(.text.*)\n\n\t#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n\t#include <linker\/common-rom.ld>\n\t#include <linker\/thread-local-storage.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t*(.rodata)\n\t*(.rodata.*)\n\n\t#include <snippets-rodata.ld>\n\n#ifdef CONFIG_X86_MMU\n\t. = ALIGN(8);\n\t_mmu_region_list_start = .;\n\tKEEP(*(\"._mmu_region.static.*\"))\n\t_mmu_region_list_end = .;\n#endif \/* CONFIG_X86_MMU *\/\n\n\t#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\t_image_rom_end = .;\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\tMMU_PAGE_ALIGN\n#ifndef CONFIG_USERSPACE\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\t*(.bss)\n\t*(.bss.*)\n\t*(COMMON)\n\t. = ALIGN(4);\t\/* so __bss_num_dwords is exact *\/\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_dwords = (__bss_end - __bss_start) >> 2;\n\n#include <linker\/common-noinit.ld>\n\n#include <snippets-sections.ld>\n\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t*(.data)\n\t*(.data.*)\n\t#include <snippets-rwdata.ld>\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <snippets-ram-sections.ld>\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <linker\/kobject.ld>\n\n\t_image_ram_end = .;\n\t_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ :\n\t{\n\t*(.got)\n\t*(.got.plt)\n\t*(.igot)\n\t*(.igot.plt)\n\t*(.iplt)\n\t*(.plt)\n\t*(.note.GNU-stack)\n\t*(.rel.*)\n\t*(.rela.*)\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6648c4b0d1a79a59f97e36e337587f34be4e9024","subject":"Fixes a bug in the ld filefor the pic32mx that caused .data to be loaded from the wrong address.","message":"Fixes a bug in the ld filefor the pic32mx that caused .data to be loaded from the wrong address.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/microchip-pic32mx-duinomitemega\/target.ld","new_file":"boards\/microchip-pic32mx-duinomitemega\/target.ld","new_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 64K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_userboot (rx) : ORIGIN = 0xBD000000, LENGTH = 0x1000\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0xBD001000, LENGTH = 512K - 4K \/*we skipped the first page to allow for the interrupt vector table. There is a lot of free space there, but linking needs to flow around existing absolute sections there. *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0xBFC00000, LENGTH = 0x0 \/* Don't allow stuff in the boot flash, there is a bootloader there *\/\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** TEMPORARY: located at end of bootflash for now (this is \"debug page\")...\r\n** 0xBFC03000-(0x10 config registers + 0x200+ (64 vectors * x20))= 0xBFC025F0\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0xBD000000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 9k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** First thing in  flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n  } >PIC32MX_flash_userboot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; \/* DRN updated this; seems correct... *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","old_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 64K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_userboot (rx) : ORIGIN = 0xBD000000, LENGTH = 0x1000\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0xBD001000, LENGTH = 512K - 4K \/*we skipped the first page to allow for the interrupt vector table. There is a lot of free space there, but linking needs to flow around existing absolute sections there. *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0xBFC00000, LENGTH = 0x0 \/* Don't allow stuff in the boot flash, there is a bootloader there *\/\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** TEMPORARY: located at end of bootflash for now (this is \"debug page\")...\r\n** 0xBFC03000-(0x10 config registers + 0x200+ (64 vectors * x20))= 0xBFC025F0\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0xBD000000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 9k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** First thing in  flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n  } >PIC32MX_flash_userboot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  __cs3_region_init_ram = _etext; \/* DRN updated this; seems correct... *\/\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"82fd3dcec01bd4599a401226116e2be1e85b6425","subject":"Moved userland later in memory as if we load it at 0x10000 right now, it'll overwrite the kernel (oops?) TODO: relocate :(","message":"Moved userland later in memory as if we load it at 0x10000 right now, it'll overwrite the kernel (oops?) TODO: relocate :(\n","repos":"SimonGustavsson\/nox,SimonGustavsson\/nox","old_file":"userland\/userland.ld","new_file":"userland\/userland.ld","new_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 0x20000;\n\n    LD_KERNEL_START = .;\n\n    \/* Kernel code *\/\n\t.text :\n\t{\n        *(.text.start)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata ALIGN(4):\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data ALIGN(4):\n\t{\n\t\t*(.data)\n\t}\n\n    LD_KERNEL_DATA_END = .;\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss ALIGN(4):\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t}\n\n    LD_KERNEL_END = .;\n\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","old_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 0x10000;\n\n    LD_KERNEL_START = .;\n\n    \/* Kernel code *\/\n\t.text :\n\t{\n        *(.text.start)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata ALIGN(4):\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data ALIGN(4):\n\t{\n\t\t*(.data)\n\t}\n\n    LD_KERNEL_DATA_END = .;\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss ALIGN(4):\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t}\n\n    LD_KERNEL_END = .;\n\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2f16c46918fd10328ac5361da2e10a22de64f833","subject":"Alignment fix for global symbols fixes #97","message":"Alignment fix for global symbols fixes #97\n","repos":"cliffordwolf\/picorv32,cliffordwolf\/picorv32,cliffordwolf\/picorv32,cliffordwolf\/picorv32","old_file":"picosoc\/sections.lds","new_file":"picosoc\/sections.lds","new_contents":"MEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00100000, LENGTH = 0x400000 \/* entire flash, 4 MiB *\/\n    RAM (xrw)       : ORIGIN = 0x00000000, LENGTH = 0x000400 \/* 1 KB *\/\n}\n\nSECTIONS {\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        *(.srodata)        \/* .rodata sections (constants, strings, etc.) *\/\n        *(.srodata*)       \/* .rodata* sections (constants, strings, etc.) *\/\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH\n\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        . = ALIGN(4);\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n        *(.sdata)           \/* .sdata sections *\/\n        *(.sdata*)          \/* .sdata* sections *\/\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n    } >RAM\n}\n","old_contents":"MEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00100000, LENGTH = 0x400000 \/* entire flash, 4 MiB *\/\n    RAM (xrw)       : ORIGIN = 0x00000000, LENGTH = 0x000400 \/* 1 KB *\/\n}\n\nSECTIONS {\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        *(.srodata)        \/* .rodata sections (constants, strings, etc.) *\/\n        *(.srodata*)       \/* .rodata* sections (constants, strings, etc.) *\/\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH\n\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        . = ALIGN(4);\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n        *(.sdata)           \/* .sdata sections *\/\n        *(.sdata*)          \/* .sdata* sections *\/\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n    } >RAM\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"5240291080d42b3ba4764a2d2cb407470e396cc3","subject":"[arm] force 4 byte alignment of data segments in the linkscript","message":"[arm] force 4 byte alignment of data segments in the linkscript\n","repos":"DooMLoRD\/android_bootable_bootloader_lk,jsr-d9\/android_kernel_lk,GCrean\/lk,travisg\/lk,chirayudesai\/android_bootable_bootloader_lk,CanarySolutions\/little-kernel,idor\/dk50-bootable_bootloader_lk,Blefish\/android_bootable_bootloader_lk,nvll\/lk,hanjae\/lumiab0,srodrig1\/lk,Foxda-Tech\/polaris-bootable-bootloader-lk,chirayudesai\/android_bootable_bootloader_lk,jsr-d10\/android_bootable_bootloader_lk,xndcn\/moboot-for-veer,skabet\/lk,RonGokhale\/android_lk_bootloader,M1cha\/mi2_lk,xndcn\/moboot-for-veer,hanjae\/lumiab0,zhuotong\/mi2_lk_NoEmmc,ianloic\/lk,Foxda-Tech\/argo8-bootable-bootloader-lk,ErikCorryGoogle\/lk,mozilla-b2g\/fairphone2_kernel_lk,nvll\/lk,t2m-foxfone\/kernel_lk,detule\/lk-g2-spr,beidl\/lk_umia,ianloic\/lk,t2m-foxfone\/kernel_lk,littlekernel\/lk,RonGokhale\/android_lk_bootloader,mozilla-b2g\/fairphone2_kernel_lk,grub4android\/lk,M1cha\/mi2_lk,M1cha\/android_bootable_bootloader_lk,lg-devs\/g2-bootloader,littlekernel\/lk,M1cha\/mi2_lk,skabet\/lk,thornbirdblue\/codeaurora_lk,beidl\/lk_umia,utilite2\/lk,efidroid\/lk,zhuotong\/mi2_lk_NoEmmc,mozilla-b2g\/kernel_lk,M1cha\/lktris,sndnvaps\/lk,jsr-d10\/android_bootable_bootloader_lk,Foxda-Tech\/polaris-bootable-bootloader-lk,skabet\/lk,Foxda-Tech\/polaris-bootable-bootloader-lk,lg-devs\/g2-bootloader,M1cha\/lk,hanjae\/lumiab0,minglun-tsai\/lk,CanarySolutions\/little-kernel,GCrean\/lk,grub4android\/lk,thornbirdblue\/codeaurora_lk,efidroid\/lk,jcsullins\/moboot,jsr-d9\/android_kernel_lk,utilite2\/lk,travisg\/lk,travisg\/lk,M1cha\/lktris,Blefish\/android_bootable_bootloader_lk,pablomarx\/lk,littlekernel\/lk,M1cha\/lk,srodrig1\/lk,Foxda-Tech\/argo8-bootable-bootloader-lk,beidl\/lk_umia,RonGokhale\/android_lk_bootloader,M1cha\/lk,jbott\/lk_gee,grub4android\/lk,srodrig1\/lk,t2m-foxfone\/android_kernel_lk,MiCode\/mi2_lk,beidl\/lk_umia,utilite2\/lk,jcsullins\/moboot,M1cha\/android_bootable_bootloader_lk,oubeichen\/lk-v500,DooMLoRD\/android_bootable_bootloader_lk,ErikCorryGoogle\/lk,zhuotong\/mi2_lk_NoEmmc,my4ndr0id\/android_bootable_bootloader_lk,M1cha\/lktris,mozilla-b2g\/kernel_lk,Redmi-dev\/android_bootable_lk,Foxda-Tech\/argo8-bootable-bootloader-lk,utilite2\/lk,minglun-tsai\/lk,sndnvaps\/lk,Foxda-Tech\/argo8-bootable-bootloader-lk,M1cha\/mi2_lk,jcsullins\/moboot,jsr-d10\/android_bootable_bootloader_lk,lg-devs\/g2-bootloader,M1cha\/lktris,pablomarx\/lk,grub4android\/lk,idor\/dk50-bootable_bootloader_lk,sndnvaps\/lk,hollanderic\/lkstuff,t2m-foxfone\/android_kernel_lk,hanjae\/lumiab0,Redmi-dev\/android_bootable_lk,pablomarx\/lk,mozilla-b2g\/fairphone2_kernel_lk,Redmi-dev\/android_bootable_lk,beidl\/lk_umia,minglun-tsai\/lk,M1cha\/mi2_lk,M1cha\/android_bootable_bootloader_lk,hanjae\/lumiab0,GCrean\/lk,Blefish\/android_bootable_bootloader_lk,lg-devs\/g2-bootloader,nvll\/lk,pichina\/lk,MiCode\/mi2_lk,detule\/lk-g2-spr,CanarySolutions\/little-kernel,mozilla-b2g\/kernel_lk,srodrig1\/lk,skabet\/lk,mozilla-b2g\/fairphone2_kernel_lk,DooMLoRD\/android_bootable_bootloader_lk,jbott\/lk_gee,M1cha\/android_bootable_bootloader_lk,chirayudesai\/android_bootable_bootloader_lk,Foxda-Tech\/polaris-bootable-bootloader-lk,t2m-foxfone\/kernel_lk,grub4android\/lk,detule\/lk-g2-spr,thornbirdblue\/codeaurora_lk,jsr-d9\/android_kernel_lk,t2m-foxfone\/android_kernel_lk,Foxda-Tech\/polaris-bootable-bootloader-lk,jsr-d10\/android_bootable_bootloader_lk,jsr-d9\/android_kernel_lk,jcsullins\/moboot,skabet\/lk,DooMLoRD\/android_bootable_bootloader_lk,M1cha\/lk,t2m-foxfone\/kernel_lk,mozilla-b2g\/kernel_lk,M1cha\/lktris,GCrean\/lk,t2m-foxfone\/android_kernel_lk,my4ndr0id\/android_bootable_bootloader_lk,jcsullins\/moboot,sndnvaps\/lk,minglun-tsai\/lk,M1cha\/android_bootable_bootloader_lk,CanarySolutions\/little-kernel,xndcn\/moboot-for-veer,pablomarx\/lk,Foxda-Tech\/argo8-bootable-bootloader-lk,ianloic\/lk,Blefish\/android_bootable_bootloader_lk,srodrig1\/lk,nvll\/lk,hollanderic\/lkstuff,efidroid\/lk,Redmi-dev\/android_bootable_lk,oubeichen\/lk-v500,utilite2\/lk,detule\/lk-g2-spr,MiCode\/mi2_lk,jcsullins\/moboot,idor\/dk50-bootable_bootloader_lk,xndcn\/moboot-for-veer,hollanderic\/lkstuff,pichina\/lk,ErikCorryGoogle\/lk,M1cha\/lk,MiCode\/mi2_lk,ianloic\/lk,chirayudesai\/android_bootable_bootloader_lk,travisg\/lk,zhuotong\/mi2_lk_NoEmmc,t2m-foxfone\/kernel_lk,jbott\/lk_gee,jbott\/lk_gee,chirayudesai\/android_bootable_bootloader_lk,thornbirdblue\/codeaurora_lk,detule\/lk-g2-spr,mozilla-b2g\/kernel_lk,pablomarx\/lk,oubeichen\/lk-v500,thornbirdblue\/codeaurora_lk,jsr-d10\/android_bootable_bootloader_lk,zhuotong\/mi2_lk_NoEmmc,littlekernel\/lk,efidroid\/lk,MiCode\/mi2_lk,oubeichen\/lk-v500,my4ndr0id\/android_bootable_bootloader_lk,idor\/dk50-bootable_bootloader_lk,idor\/dk50-bootable_bootloader_lk,my4ndr0id\/android_bootable_bootloader_lk,pichina\/lk,lg-devs\/g2-bootloader,t2m-foxfone\/android_kernel_lk,M1cha\/android_bootable_bootloader_lk,GCrean\/lk,jbott\/lk_gee,Blefish\/android_bootable_bootloader_lk,efidroid\/lk,ErikCorryGoogle\/lk,xndcn\/moboot-for-veer,nvll\/lk,hollanderic\/lkstuff,RonGokhale\/android_lk_bootloader,pichina\/lk,sndnvaps\/lk,CanarySolutions\/little-kernel,pichina\/lk,my4ndr0id\/android_bootable_bootloader_lk,oubeichen\/lk-v500,jsr-d9\/android_kernel_lk,Redmi-dev\/android_bootable_lk,RonGokhale\/android_lk_bootloader,mozilla-b2g\/fairphone2_kernel_lk,DooMLoRD\/android_bootable_bootloader_lk","old_file":"arch\/arm\/system-onesegment.ld","new_file":"arch\/arm\/system-onesegment.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\nENTRY(_start)\nSECTIONS\n{\n\t. = %MEMBASE%;\n\n\t.interp : { *(.interp) }\n\t.hash : { *(.hash) }\n\t.dynsym : { *(.dynsym) }\n\t.dynstr : { *(.dynstr) }\n\t.rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) }\n\t.rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) }\n\t.rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) }\n\t.rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) }\n\t.rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }\n\t.rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }\n\t.rel.got : { *(.rel.got) }\n\t.rela.got : { *(.rela.got) }\n\t.rel.ctors : { *(.rel.ctors) }\n\t.rela.ctors : { *(.rela.ctors) }\n\t.rel.dtors : { *(.rel.dtors) }\n\t.rela.dtors : { *(.rela.dtors) }\n\t.rel.init : { *(.rel.init) }\n\t.rela.init : { *(.rela.init) }\n\t.rel.fini : { *(.rel.fini) }\n\t.rela.fini : { *(.rela.fini) }\n\t.rel.bss : { *(.rel.bss) }\n\t.rela.bss : { *(.rela.bss) }\n\t.rel.plt : { *(.rel.plt) }\n\t.rela.plt : { *(.rela.plt) }\n\t.init : { *(.init) } =0x9090\n\t.plt : { *(.plt) }\n\n\t\/* text\/read-only data *\/\n\t.text :\t{ *(.text .text.* .glue_7* .gnu.linkonce.t.*) } =0x9090\n\n\t.rodata : { \n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(4);\n\t\t__commands_start = .;\n\t\tKEEP (*(.commands))\n\t\t__commands_end = .;\n\t\t. = ALIGN(4); \n\t\t__rodata_end = . ;\t\t\n\t}\n\n\t\/* writable data  *\/\n\t__data_start_rom = .;\t\/* in one segment binaries, the rom data address is on top of the ram data address *\/\n\t__data_start = .;\n\t.data : SUBALIGN(4) { *(.data .data.* .gnu.linkonce.d.*) }\n\n\t__ctor_list = .;\n\t.ctors : { *(.ctors) }\n\t__ctor_end = .;\n\t__dtor_list = .;\n\t.dtors : { *(.dtors) }\n\t__dtor_end = .;\n\t.got : { *(.got.plt) *(.got) }\n\t.dynamic : { *(.dynamic) }\n\n\t__data_end = .;\n\n\t\/* unintialized data (in same segment as writable data) *\/\n\t. = ALIGN(4);\n\t__bss_start = .;\n\t.bss : { *(.bss .bss.*) }\n\n\t. = ALIGN(4); \n\t_end = .;\n\n\t. = %MEMBASE% + %MEMSIZE%;\n\t_end_of_ram = .;\n\n\t\/* Strip unnecessary stuff *\/\n\t\/DISCARD\/ : { *(.comment .note .eh_frame) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\nENTRY(_start)\nSECTIONS\n{\n\t. = %MEMBASE%;\n\n\t.interp : { *(.interp) }\n\t.hash : { *(.hash) }\n\t.dynsym : { *(.dynsym) }\n\t.dynstr : { *(.dynstr) }\n\t.rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) }\n\t.rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) }\n\t.rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) }\n\t.rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) }\n\t.rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }\n\t.rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }\n\t.rel.got : { *(.rel.got) }\n\t.rela.got : { *(.rela.got) }\n\t.rel.ctors : { *(.rel.ctors) }\n\t.rela.ctors : { *(.rela.ctors) }\n\t.rel.dtors : { *(.rel.dtors) }\n\t.rela.dtors : { *(.rela.dtors) }\n\t.rel.init : { *(.rel.init) }\n\t.rela.init : { *(.rela.init) }\n\t.rel.fini : { *(.rel.fini) }\n\t.rela.fini : { *(.rela.fini) }\n\t.rel.bss : { *(.rel.bss) }\n\t.rela.bss : { *(.rela.bss) }\n\t.rel.plt : { *(.rel.plt) }\n\t.rela.plt : { *(.rela.plt) }\n\t.init : { *(.init) } =0x9090\n\t.plt : { *(.plt) }\n\n\t\/* text\/read-only data *\/\n\t.text :\t{ *(.text .text.* .glue_7* .gnu.linkonce.t.*) } =0x9090\n\n\t.rodata : { \n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(4);\n\t\t__commands_start = .;\n\t\tKEEP (*(.commands))\n\t\t__commands_end = .;\n\t\t. = ALIGN(4); \n\t\t__rodata_end = . ;\t\t\n\t}\n\n\t\/* writable data  *\/\n\t__data_start_rom = .;\t\/* in one segment binaries, the rom data address is on top of the ram data address *\/\n\t__data_start = .;\n\t.data : { *(.data .data.* .gnu.linkonce.d.*) }\n\n\t__ctor_list = .;\n\t.ctors : { *(.ctors) }\n\t__ctor_end = .;\n\t__dtor_list = .;\n\t.dtors : { *(.dtors) }\n\t__dtor_end = .;\n\t.got : { *(.got.plt) *(.got) }\n\t.dynamic : { *(.dynamic) }\n\n\t__data_end = .;\n\n\t\/* unintialized data (in same segment as writable data) *\/\n\t. = ALIGN(4);\n\t__bss_start = .;\n\t.bss : { *(.bss .bss.*) }\n\n\t. = ALIGN(4); \n\t_end = .;\n\n\t. = %MEMBASE% + %MEMSIZE%;\n\t_end_of_ram = .;\n\n\t\/* Strip unnecessary stuff *\/\n\t\/DISCARD\/ : { *(.comment .note .eh_frame) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"d8b8a20c05df3ab067512b3fb44140e374e44fab","subject":"feat(ld): Export low level function address","message":"feat(ld): Export low level function address\n\nIn rom, these functions are wrapped, modify to use these functions directly.\n\ninternal: 45cbd694\n","repos":"espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK","old_file":"ld\/eagle.rom.addr.v6.ld","new_file":"ld\/eagle.rom.addr.v6.ld","new_contents":"PROVIDE ( SPI_sector_erase = 0x400040c0 );\nPROVIDE ( SPI_page_program = 0x40004174 );\nPROVIDE ( SPI_read_data = 0x400042ac );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( Disable_QMode = 0x40004508 );\n\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\n\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\n\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\n\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\n\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\n\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );","old_contents":"PROVIDE ( SPI_sector_erase = 0x400040c0 );\nPROVIDE ( SPI_page_program = 0x40004174 );\nPROVIDE ( SPI_read_data = 0x400042ac );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( Disable_QMode = 0x40004508 );\n\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\n\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\n\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\n\nPROVIDE ( bzero = 0x40002ae8 );\nPROVIDE ( memcmp = 0x400018d4 );\nPROVIDE ( memcpy = 0x400018b4 );\nPROVIDE ( memmove = 0x400018c4 );\nPROVIDE ( memset = 0x400018a4 );\n\nPROVIDE ( strcmp = 0x40002aa8 );\nPROVIDE ( strcpy = 0x40002a88 );\nPROVIDE ( strlen = 0x40002ac8 );\nPROVIDE ( strncmp = 0x40002ab8 );\nPROVIDE ( strncpy = 0x40002a98 );\nPROVIDE ( strstr = 0x40002ad8 );\n\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"97d46bae6a0dca2f8829044dd27052df230c4c3f","subject":"nrf5\/boards: decrease size of ISR region from 4k to 1k in custom feather52 linker script to get some more flash space.","message":"nrf5\/boards: decrease size of ISR region from 4k to 1k in custom feather52 linker script to get some more flash space.\n","repos":"adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,tralamazza\/micropython,adafruit\/circuitpython,tralamazza\/micropython,tralamazza\/micropython,adafruit\/micropython,adafruit\/micropython","old_file":"nrf5\/boards\/feather52\/custom_nrf52832_dfu_app.ld","new_file":"nrf5\/boards\/feather52\/custom_nrf52832_dfu_app.ld","new_contents":"\/*\n    GNU linker script for NRF52 w\/ s132 2.0.1 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x0001c000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x0001c400, LENGTH = 0x026c00 \/* 152 KiB - APP - ISR *\/\n    RAM (xrw)       : ORIGIN = 0x200039c0, LENGTH = 0x0c640  \/* 49.5 KiB, give 8KiB headroom for softdevice *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20007000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52 w\/ s132 2.0.1 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x0001c000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x0001d000, LENGTH = 0x026000 \/* 152 KiB - APP - ISR *\/\n    RAM (xrw)       : ORIGIN = 0x200039c0, LENGTH = 0x0c640  \/* 49.5 KiB, give 8KiB headroom for softdevice *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20007000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0289a410baa07d79c2ceaa426e3d4c106f9dd273","subject":"riscv32: linker: Link .srodata section","message":"riscv32: linker: Link .srodata section\n\nBuilding tests\/kernel\/common\/kernel.common with the new crosstools\nSDK-ng resulted in an orphan short read-only data section. Fix this by\nadding the .srodata section to the RISC-V linker script.\n\nSigned-off-by: Nathaniel Graff <e7e2d91f1deb937cded6d6fc8e8292f24ce08299@sifive.com>\n","repos":"GiulianoFranchetto\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,explora26\/zephyr,ldts\/zephyr,galak\/zephyr,finikorg\/zephyr,explora26\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,Vudentz\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,explora26\/zephyr,ldts\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr","old_file":"include\/arch\/riscv32\/common\/linker.ld","new_file":"include\/arch\/riscv32\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv32 platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <soc.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(\".noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv32 platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <soc.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(\".noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"59a7a44406989c6e9193949490635dda0343f3d3","subject":"Update stm32f042x4.ld","message":"Update stm32f042x4.ld","repos":"rksdna\/swamp-m0,rksdna\/swamp,rksdna\/swamp","old_file":"kernel\/target\/stm32f042x4.ld","new_file":"kernel\/target\/stm32f042x4.ld","new_contents":"\/*\r\n * STM32F042x4 linker script\r\n * Copyright (c) 2016 rksdna\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * in the Software without restriction, including without limitation the rights\r\n * to use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\r\n * copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n * The above copyright notice and this permission notice shall be included in\r\n * all copies or substantial portions of the Software.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\r\n * THE SOFTWARE.\r\n *\/\r\n\r\nENTRY(startup_handler)\r\n\r\nMEMORY\r\n{\r\n\tsram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K\r\n\tflash (rx) : ORIGIN = 0x08000000, LENGTH = 16K\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\t*(.startup)\r\n\t\t*(.text*)\r\n\t\t*(.rodata*)\r\n\t\t. = ALIGN(4);\r\n\t} > flash\r\n\ttext_section_end = .;\r\n\r\n\t.data : AT (text_section_end)\r\n\t{\r\n\t\tdata_section_begin = .;\r\n\t\t*(.data*)\r\n\t\t. = ALIGN(4);\r\n\t} > sram\r\n\tdata_section_end = .;\r\n\r\n\t.bss :\r\n\t{\r\n\t\tbss_section_begin = .;\r\n\t\t*(.bss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(4);\r\n\t} > sram\r\n\tbss_section_end = .;\r\n\r\n\tstack_section_end = ORIGIN(sram) + LENGTH(sram);\r\n}\r\n\r\n","old_contents":"\/*\r\n * STM32F042x4 linker script\r\n * Copyright (c) 2016 Andrey Skrypka, Vladimir Trofimov\r\n *\r\n * Permission is hereby granted, free of charge, to any person obtaining a copy\r\n * of this software and associated documentation files (the \"Software\"), to deal\r\n * in the Software without restriction, including without limitation the rights\r\n * to use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\r\n * copies of the Software, and to permit persons to whom the Software is\r\n * furnished to do so, subject to the following conditions:\r\n *\r\n * The above copyright notice and this permission notice shall be included in\r\n * all copies or substantial portions of the Software.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\r\n * THE SOFTWARE.\r\n *\/\r\n\r\nENTRY(startup_handler)\r\n\r\nMEMORY\r\n{\r\n\tsram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K\r\n\tflash (rx) : ORIGIN = 0x08000000, LENGTH = 16K\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\t*(.startup)\r\n\t\t*(.text*)\r\n\t\t*(.rodata*)\r\n\t\t. = ALIGN(4);\r\n\t} > flash\r\n\ttext_section_end = .;\r\n\r\n\t.data : AT (text_section_end)\r\n\t{\r\n\t\tdata_section_begin = .;\r\n\t\t*(.data*)\r\n\t\t. = ALIGN(4);\r\n\t} > sram\r\n\tdata_section_end = .;\r\n\r\n\t.bss :\r\n\t{\r\n\t\tbss_section_begin = .;\r\n\t\t*(.bss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(4);\r\n\t} > sram\r\n\tbss_section_end = .;\r\n\r\n\tstack_section_end = ORIGIN(sram) + LENGTH(sram);\r\n}\r\n\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"386efe1e0f3f66c28a150d9e84aac46ca32c8d80","subject":"Sync: Add support for FT psk(3d5ca7ee)","message":"Sync: Add support for FT psk(3d5ca7ee)\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.ld","new_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.ld","new_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\nrtc_get_wakeup_cause = 0x40000020;\nrtc_select_apb_bridge = 0x40000024;\nrtc_unhold_all_pads = 0x40000028;\nets_is_print_boot = 0x4000002c;\nets_vprintf = 0x40000030;\nets_printf = 0x40000034;\nets_install_putc1 = 0x40000038;\nets_install_uart_printf = 0x4000003c;\nets_install_putc2 = 0x40000040;\nets_delay_us = 0x40000044;\nets_get_stack_info = 0x40000048;\nets_install_lock = 0x4000004c;\nUartRxString = 0x40000050;\nUartGetCmdLn = 0x40000054;\nuart_tx_one_char = 0x40000058;\nuart_tx_one_char2 = 0x4000005c;\nuart_rx_one_char = 0x40000060;\nuart_rx_one_char_block = 0x40000064;\nuart_rx_readbuff = 0x40000068;\nuartAttach = 0x4000006c;\nuart_tx_flush = 0x40000070;\nuart_tx_wait_idle = 0x40000074;\nuart_div_modify = 0x40000078;\nets_write_char_uart = 0x4000007c;\nuart_tx_switch = 0x40000080;\nmultofup = 0x40000084;\nsoftware_reset = 0x40000088;\nsoftware_reset_cpu = 0x4000008c;\nassist_debug_clock_enable = 0x40000090;\nassist_debug_record_enable = 0x40000094;\nclear_super_wdt_reset_flag = 0x40000098;\ndisable_default_watchdog = 0x4000009c;\nsend_packet = 0x400000a0;\nrecv_packet = 0x400000a4;\nGetUartDevice = 0x400000a8;\nUartDwnLdProc = 0x400000ac;\nGetSecurityInfoProc = 0x400000b0;\nUart_Init = 0x400000b4;\nets_set_user_start = 0x400000b8;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff4fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000bc;\nmz_free = 0x400000c0;\ntdefl_compress = 0x400000c4;\ntdefl_compress_buffer = 0x400000c8;\ntdefl_compress_mem_to_heap = 0x400000cc;\ntdefl_compress_mem_to_mem = 0x400000d0;\ntdefl_compress_mem_to_output = 0x400000d4;\ntdefl_get_adler32 = 0x400000d8;\ntdefl_get_prev_return_status = 0x400000dc;\ntdefl_init = 0x400000e0;\ntdefl_write_image_to_png_file_in_memory = 0x400000e4;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000e8;\ntinfl_decompress = 0x400000ec;\ntinfl_decompress_mem_to_callback = 0x400000f0;\ntinfl_decompress_mem_to_heap = 0x400000f4;\ntinfl_decompress_mem_to_mem = 0x400000f8;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 );\nPROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 );\nPROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 );\nPROVIDE( _esp_rom_spiflash_write = 0x4000011c );\nPROVIDE( _esp_rom_spiflash_read = 0x40000120 );\nPROVIDE( _esp_rom_spiflash_unlock = 0x40000124 );\nPROVIDE( _SPIEraseArea = 0x40000128 );\nPROVIDE( _SPI_write_enable = 0x4000012c );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000134 );\nPROVIDE( esp_rom_spiflash_write = 0x40000138 );\nPROVIDE( esp_rom_spiflash_read = 0x4000013c );\nPROVIDE( esp_rom_spiflash_unlock = 0x40000140 );\nPROVIDE( SPIEraseArea = 0x40000144 );\nPROVIDE( SPI_write_enable = 0x40000148 );\nPROVIDE( esp_rom_spiflash_config_param = 0x4000014c );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c );\nPROVIDE( esp_rom_spi_flash_update_id = 0x40000160 );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000164 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 );\nPROVIDE( esp_rom_spiflash_read_status = 0x4000016c );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000174 );\nPROVIDE( spi_flash_attach = 0x40000178 );\nPROVIDE( spi_flash_get_chip_size = 0x4000017c );\nPROVIDE( spi_flash_guard_set = 0x40000180 );\nPROVIDE( spi_flash_guard_get = 0x40000184 );\nPROVIDE( spi_flash_read_encrypted = 0x40000188 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x4000018c );\nPROVIDE( spi_flash_mmap_page_num_init = 0x40000190 );\nPROVIDE( spi_flash_mmap = 0x40000194 );\nPROVIDE( spi_flash_mmap_pages = 0x40000198 );\nPROVIDE( spi_flash_munmap = 0x4000019c );\nPROVIDE( spi_flash_mmap_dump = 0x400001a0 );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );\nPROVIDE( spi_flash_cache2phys = 0x400001ac );\nPROVIDE( spi_flash_phys2cache = 0x400001b0 );\nPROVIDE( spi_flash_disable_cache = 0x400001b4 );\nPROVIDE( spi_flash_restore_cache = 0x400001b8 );\nPROVIDE( spi_flash_cache_enabled = 0x400001bc );\nPROVIDE( spi_flash_enable_cache = 0x400001c0 );\nPROVIDE( spi_cache_mode_switch = 0x400001c4 );\nPROVIDE( spi_common_set_dummy_output = 0x400001c8 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001cc );\nPROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 );\nPROVIDE( SPILock = 0x400001d8 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001dc );\nPROVIDE( SPI_Common_Command = 0x400001e0 );\nPROVIDE( SPI_WakeUp = 0x400001e4 );\nPROVIDE( SPI_block_erase = 0x400001e8 );\nPROVIDE( SPI_chip_erase = 0x400001ec );\nPROVIDE( SPI_init = 0x400001f0 );\nPROVIDE( SPI_page_program = 0x400001f4 );\nPROVIDE( SPI_read_data = 0x400001f8 );\nPROVIDE( SPI_sector_erase = 0x400001fc );\nPROVIDE( SelectSpiFunction = 0x40000200 );\nPROVIDE( SetSpiDrvs = 0x40000204 );\nPROVIDE( Wait_SPI_Idle = 0x40000208 );\nPROVIDE( spi_dummy_len_fix = 0x4000020c );\nPROVIDE( Disable_QMode = 0x40000210 );\nPROVIDE( Enable_QMode = 0x40000214 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group hal_soc\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 );\nPROVIDE( spi_flash_hal_device_config = 0x4000021c );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 );\nPROVIDE( spi_flash_hal_common_command = 0x40000224 );\nPROVIDE( spi_flash_hal_read = 0x40000228 );\nPROVIDE( spi_flash_hal_erase_chip = 0x4000022c );\nPROVIDE( spi_flash_hal_erase_sector = 0x40000230 );\nPROVIDE( spi_flash_hal_erase_block = 0x40000234 );\nPROVIDE( spi_flash_hal_program_page = 0x40000238 );\nPROVIDE( spi_flash_hal_set_write_protect = 0x4000023c );\nPROVIDE( spi_flash_hal_host_idle = 0x40000240 );\nPROVIDE( spi_flash_hal_check_status = 0x40000244 );\nPROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 );\nPROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c );\nPROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 );\nPROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 );\nPROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 );\nPROVIDE( spi_flash_hal_resume = 0x4000025c );\nPROVIDE( spi_flash_hal_suspend = 0x40000260 );\nPROVIDE( spi_flash_encryption_hal_enable = 0x40000264 );\nPROVIDE( spi_flash_encryption_hal_disable = 0x40000268 );\nPROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c );\nPROVIDE( spi_flash_encryption_hal_done = 0x40000270 );\nPROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 );\nPROVIDE( spi_flash_encryption_hal_check = 0x40000278 );\nPROVIDE( wdt_hal_init = 0x4000027c );\nPROVIDE( wdt_hal_deinit = 0x40000280 );\nPROVIDE( wdt_hal_config_stage = 0x40000284 );\nPROVIDE( wdt_hal_write_protect_disable = 0x40000288 );\nPROVIDE( wdt_hal_write_protect_enable = 0x4000028c );\nPROVIDE( wdt_hal_enable = 0x40000290 );\nPROVIDE( wdt_hal_disable = 0x40000294 );\nPROVIDE( wdt_hal_handle_intr = 0x40000298 );\nPROVIDE( wdt_hal_feed = 0x4000029c );\nPROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 );\nPROVIDE( wdt_hal_is_enabled = 0x400002a4 );\nPROVIDE( systimer_hal_init = 0x400002a8 );\nPROVIDE( systimer_hal_get_counter_value = 0x400002ac );\nPROVIDE( systimer_hal_get_time = 0x400002b0 );\nPROVIDE( systimer_hal_set_alarm_target = 0x400002b4 );\nPROVIDE( systimer_hal_set_alarm_period = 0x400002b8 );\nPROVIDE( systimer_hal_get_alarm_value = 0x400002bc );\nPROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 );\nPROVIDE( systimer_hal_on_apb_freq_update = 0x400002c4 );\nPROVIDE( systimer_hal_counter_value_advance = 0x400002c8 );\nPROVIDE( systimer_hal_enable_counter = 0x400002cc );\nPROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 );\nPROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 );\nPROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 );\n\n\n\/***************************************\n Group heap\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( tlsf_create = 0x400002dc );\nPROVIDE( tlsf_create_with_pool = 0x400002e0 );\nPROVIDE( tlsf_get_pool = 0x400002e4 );\nPROVIDE( tlsf_add_pool = 0x400002e8 );\nPROVIDE( tlsf_remove_pool = 0x400002ec );\nPROVIDE( tlsf_malloc = 0x400002f0 );\nPROVIDE( tlsf_memalign = 0x400002f4 );\nPROVIDE( tlsf_memalign_offs = 0x400002f8 );\nPROVIDE( tlsf_realloc = 0x400002fc );\nPROVIDE( tlsf_free = 0x40000300 );\nPROVIDE( tlsf_block_size = 0x40000304 );\nPROVIDE( tlsf_size = 0x40000308 );\nPROVIDE( tlsf_align_size = 0x4000030c );\nPROVIDE( tlsf_block_size_min = 0x40000310 );\nPROVIDE( tlsf_block_size_max = 0x40000314 );\nPROVIDE( tlsf_pool_overhead = 0x40000318 );\nPROVIDE( tlsf_alloc_overhead = 0x4000031c );\nPROVIDE( tlsf_walk_pool = 0x40000320 );\nPROVIDE( tlsf_check = 0x40000324 );\nPROVIDE( tlsf_check_pool = 0x40000328 );\nPROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c );\nPROVIDE( multi_heap_get_block_address_impl = 0x40000330 );\nPROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 );\nPROVIDE( multi_heap_register_impl = 0x40000338 );\nPROVIDE( multi_heap_set_lock = 0x4000033c );\nPROVIDE( multi_heap_os_funcs_init = 0x40000340 );\nPROVIDE( multi_heap_internal_lock = 0x40000344 );\nPROVIDE( multi_heap_internal_unlock = 0x40000348 );\nPROVIDE( multi_heap_get_first_block = 0x4000034c );\nPROVIDE( multi_heap_get_next_block = 0x40000350 );\nPROVIDE( multi_heap_is_free = 0x40000354 );\nPROVIDE( multi_heap_malloc_impl = 0x40000358 );\nPROVIDE( multi_heap_free_impl = 0x4000035c );\nPROVIDE( multi_heap_realloc_impl = 0x40000360 );\nPROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 );\nPROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 );\nPROVIDE( multi_heap_check = 0x4000036c );\nPROVIDE( multi_heap_dump = 0x40000370 );\nPROVIDE( multi_heap_free_size_impl = 0x40000374 );\nPROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 );\nPROVIDE( multi_heap_get_info_impl = 0x4000037c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x40000380 );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 );\nPROVIDE( spi_flash_chip_generic_write = 0x40000388 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000398 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 );\nPROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 );\nPROVIDE( spi_flash_chip_generic_yield = 0x400003b8 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 );\nPROVIDE( spi_flash_chip_generic_read = 0x400003c8 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc );\nPROVIDE( spi_flash_common_set_io_mode = 0x400003e0 );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 );\nPROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 );\nPROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec );\nPROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400003f8 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );\nPROVIDE( spi_flash_encryption = 0x3fcdffe4 );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x40000400 );\nPROVIDE( memspi_host_read_status_hs = 0x40000404 );\nPROVIDE( memspi_host_flush_cache = 0x40000408 );\nPROVIDE( memspi_host_erase_chip = 0x4000040c );\nPROVIDE( memspi_host_erase_sector = 0x40000410 );\nPROVIDE( memspi_host_erase_block = 0x40000414 );\nPROVIDE( memspi_host_program_page = 0x40000418 );\nPROVIDE( memspi_host_read = 0x4000041c );\nPROVIDE( memspi_host_set_write_protect = 0x40000420 );\nPROVIDE( memspi_host_set_max_read_len = 0x40000424 );\nPROVIDE( memspi_host_read_data_slicer = 0x40000428 );\nPROVIDE( memspi_host_write_data_slicer = 0x4000042c );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x40000430 );\nPROVIDE( esp_flash_read_id = 0x40000434 );\nPROVIDE( esp_flash_get_size = 0x40000438 );\nPROVIDE( esp_flash_erase_chip = 0x4000043c );\nPROVIDE( esp_flash_erase_region = 0x40000440 );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000444 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000448 );\nPROVIDE( esp_flash_get_protectable_regions = 0x4000044c );\nPROVIDE( esp_flash_get_protected_region = 0x40000450 );\nPROVIDE( esp_flash_set_protected_region = 0x40000454 );\nPROVIDE( esp_flash_read = 0x40000458 );\nPROVIDE( esp_flash_write = 0x4000045c );\nPROVIDE( esp_flash_write_encrypted = 0x40000460 );\nPROVIDE( esp_flash_read_encrypted = 0x40000464 );\nPROVIDE( esp_flash_get_io_mode = 0x40000468 );\nPROVIDE( esp_flash_set_io_mode = 0x4000046c );\nPROVIDE( spi_flash_boot_attach = 0x40000470 );\nPROVIDE( esp_flash_read_chip_id = 0x40000474 );\nPROVIDE( detect_spi_flash_chip = 0x40000478 );\nPROVIDE( esp_rom_spiflash_write_disable = 0x4000047c );\nPROVIDE( esp_flash_suspend_cmd_init = 0x40000480 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe0 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffdc );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 );\nPROVIDE( Cache_Get_Mode = 0x400006e4 );\nPROVIDE( Cache_Address_Through_IBus = 0x400006e8 );\nPROVIDE( Cache_Address_Through_DBus = 0x400006ec );\nPROVIDE( Cache_Set_Default_Mode = 0x400006f0 );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400006f8 );\nPROVIDE( MMU_Set_Page_Mode = 0x400006fc );\nPROVIDE( MMU_Get_Page_Mode = 0x40000700 );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x40000704 );\nPROVIDE( Cache_Op_Addr = 0x40000708 );\nPROVIDE( Cache_Invalidate_Addr = 0x4000070c );\nPROVIDE( Cache_Invalidate_ICache_All = 0x40000710 );\nPROVIDE( Cache_Mask_All = 0x40000714 );\nPROVIDE( Cache_UnMask_Dram0 = 0x40000718 );\nPROVIDE( Cache_Disable_ICache = 0x4000071c );\nPROVIDE( Cache_Enable_ICache = 0x40000720 );\nPROVIDE( Cache_Suspend_ICache = 0x40000724 );\nPROVIDE( Cache_Resume_ICache = 0x40000728 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x4000072c );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x40000730 );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000734 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x40000738 );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x4000073c );\nPROVIDE( Cache_Owner_Init = 0x40000740 );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000744 );\nPROVIDE( Cache_MMU_Init = 0x40000748 );\nPROVIDE( Cache_Ibus_MMU_Set = 0x4000074c );\nPROVIDE( Cache_Dbus_MMU_Set = 0x40000750 );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000754 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x40000758 );\nPROVIDE( Cache_Get_Virtual_Addr = 0x4000075c );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x40000760 );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000764 );\nPROVIDE( Cache_Get_Memory_value = 0x40000768 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd0 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x4000076c;\nets_get_cpu_frequency = 0x40000770;\nets_update_cpu_frequency = 0x40000774;\nets_get_printf_channel = 0x40000778;\nets_get_xtal_div = 0x4000077c;\nets_set_xtal_div = 0x40000780;\nets_get_xtal_freq = 0x40000784;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x40000788;\ngpio_matrix_in = 0x4000078c;\ngpio_matrix_out = 0x40000790;\ngpio_output_disable = 0x40000794;\ngpio_output_enable = 0x40000798;\ngpio_output_set = 0x4000079c;\ngpio_pad_hold = 0x400007a0;\ngpio_pad_input_disable = 0x400007a4;\ngpio_pad_input_enable = 0x400007a8;\ngpio_pad_pulldown = 0x400007ac;\ngpio_pad_pullup = 0x400007b0;\ngpio_pad_select_gpio = 0x400007b4;\ngpio_pad_set_drv = 0x400007b8;\ngpio_pad_unhold = 0x400007bc;\ngpio_pin_wakeup_disable = 0x400007c0;\ngpio_pin_wakeup_enable = 0x400007c4;\ngpio_bypass_matrix_in = 0x400007c8;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400007cc;\nesprv_intc_int_set_threshold = 0x400007d0;\nesprv_intc_int_enable = 0x400007d4;\nesprv_intc_int_disable = 0x400007d8;\nesprv_intc_int_set_type = 0x400007dc;\nPROVIDE( intr_handler_set = 0x400007e0 );\nintr_matrix_set = 0x400007e4;\nets_intr_lock = 0x400007e8;\nets_intr_unlock = 0x400007ec;\nets_isr_attach = 0x400007f0;\nets_isr_mask = 0x400007f4;\nets_isr_unmask = 0x400007f8;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\ncrc32_le = 0x400007fc;\ncrc16_le = 0x40000800;\ncrc8_le = 0x40000804;\ncrc32_be = 0x40000808;\ncrc16_be = 0x4000080c;\ncrc8_be = 0x40000810;\nesp_crc8 = 0x40000814;\nets_sha_enable = 0x40000818;\nets_sha_disable = 0x4000081c;\nets_sha_get_state = 0x40000820;\nets_sha_init = 0x40000824;\nets_sha_process = 0x40000828;\nets_sha_starts = 0x4000082c;\nets_sha_update = 0x40000830;\nets_sha_finish = 0x40000834;\nets_sha_clone = 0x40000838;\n\/* Data (.data, .bss, .rodata) *\/\ncrc32_le_table_ptr = 0x3ff4fff8;\ncrc16_le_table_ptr = 0x3ff4fff4;\ncrc8_le_table_ptr = 0x3ff4fff0;\ncrc32_be_table_ptr = 0x3ff4ffec;\ncrc16_be_table_ptr = 0x3ff4ffe8;\ncrc8_be_table_ptr = 0x3ff4ffe4;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x4000083c;\nets_efuse_program = 0x40000840;\nets_efuse_clear_program_registers = 0x40000844;\nets_efuse_write_key = 0x40000848;\nets_efuse_get_read_register_address = 0x4000084c;\nets_efuse_get_key_purpose = 0x40000850;\nets_efuse_key_block_unused = 0x40000854;\nets_efuse_find_unused_key_block = 0x40000858;\nets_efuse_rs_calculate = 0x4000085c;\nets_efuse_count_unused_key_blocks = 0x40000860;\nets_efuse_secure_boot_enabled = 0x40000864;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000868;\nets_efuse_cache_encryption_enabled = 0x4000086c;\nets_efuse_download_modes_disabled = 0x40000870;\nets_efuse_find_purpose = 0x40000874;\nets_efuse_force_send_resume = 0x40000878;\nets_efuse_get_flash_delay_us = 0x4000087c;\nets_efuse_get_mac = 0x40000880;\nets_efuse_get_uart_print_control = 0x40000884;\nets_efuse_direct_boot_mode_disabled = 0x40000888;\nets_efuse_security_download_modes_enabled = 0x4000088c;\nets_efuse_set_timing = 0x40000890;\nets_efuse_jtag_disabled = 0x40000894;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_ecdsa_verify = 0x40000898;\nets_secure_boot_verify_bootloader_with_keys = 0x4000089c;\nets_secure_boot_verify_signature = 0x400008a0;\nets_secure_boot_read_key_digests = 0x400008a4;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Data (.data, .bss, .rodata) *\/\ng_uart_print = 0x3fcdffc9;\ng_usb_print = 0x3fcdffc8;\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nble_controller_rom_data_init = 0x40000aa8;\nble_osi_coex_funcs_register = 0x40000aac;\nbt_rf_coex_cfg_get_default = 0x40000ab0;\nbt_rf_coex_dft_pti_get_default = 0x40000ab4;\nbt_rf_coex_hooks_p_set = 0x40000ab8;\nr__os_mbuf_copypkthdr = 0x40000abc;\nr__os_msys_find_pool = 0x40000ac0;\nr_ble_controller_get_rom_compile_version = 0x40000ac4;\nr_ble_hci_ram_hs_acl_tx = 0x40000ac8;\nr_ble_hci_ram_hs_cmd_tx = 0x40000acc;\nr_ble_hci_ram_ll_acl_tx = 0x40000ad0;\nr_ble_hci_ram_ll_evt_tx = 0x40000ad4;\nr_ble_hci_ram_reset = 0x40000ad8;\nr_ble_hci_ram_set_acl_free_cb = 0x40000adc;\nr_ble_hci_trans_acl_buf_alloc = 0x40000ae0;\nr_ble_hci_trans_buf_alloc = 0x40000ae4;\nr_ble_hci_trans_buf_free = 0x40000ae8;\nr_ble_hci_trans_cfg_hs = 0x40000aec;\nr_ble_hci_trans_cfg_ll = 0x40000af0;\nr_ble_hci_trans_deinit = 0x40000af4;\nr_ble_hci_trans_env_init = 0x40000af8;\nr_ble_hci_trans_init = 0x40000afc;\nr_ble_hci_uart_acl_tx = 0x40000b00;\nr_ble_hci_uart_cmdevt_tx = 0x40000b04;\nr_ble_hci_uart_config = 0x40000b08;\nr_ble_hci_uart_free_pkt = 0x40000b0c;\nr_ble_hci_uart_hs_acl_tx = 0x40000b10;\nr_ble_hci_uart_hs_cmd_tx = 0x40000b14;\nr_ble_hci_uart_ll_acl_tx = 0x40000b18;\nr_ble_hci_uart_ll_evt_tx = 0x40000b1c;\nr_ble_hci_uart_rx_acl = 0x40000b20;\nr_ble_hci_uart_rx_char = 0x40000b24;\nr_ble_hci_uart_rx_cmd = 0x40000b28;\nr_ble_hci_uart_rx_evt = 0x40000b2c;\nr_ble_hci_uart_rx_evt_cb = 0x40000b30;\nr_ble_hci_uart_rx_le_evt = 0x40000b34;\nr_ble_hci_uart_rx_pkt_type = 0x40000b38;\nr_ble_hci_uart_rx_skip_acl = 0x40000b3c;\nr_ble_hci_uart_rx_skip_cmd = 0x40000b40;\nr_ble_hci_uart_rx_skip_evt = 0x40000b44;\nr_ble_hci_uart_rx_sync_loss = 0x40000b48;\nr_ble_hci_uart_set_acl_free_cb = 0x40000b4c;\nr_ble_hci_uart_sync_lost = 0x40000b50;\nr_ble_hci_uart_trans_reset = 0x40000b54;\nr_ble_hci_uart_tx_char = 0x40000b58;\nr_ble_hci_uart_tx_pkt_type = 0x40000b5c;\nr_ble_hw_driver_deinit = 0x40000b60;\nr_ble_hw_driver_env_init = 0x40000b64;\nr_ble_hw_encrypt_block = 0x40000b68;\nr_ble_hw_get_public_addr = 0x40000b6c;\nr_ble_hw_get_static_addr = 0x40000b70;\nr_ble_hw_periodiclist_add = 0x40000b74;\nr_ble_hw_periodiclist_clear = 0x40000b78;\nr_ble_hw_periodiclist_rmv = 0x40000b7c;\nr_ble_hw_resolv_list_cur_entry = 0x40000b80;\nr_ble_hw_resolv_list_get_cur_entry = 0x40000b84;\nr_ble_hw_resolv_list_set = 0x40000b88;\nr_ble_hw_rng_init = 0x40000b8c;\nr_ble_hw_rng_start = 0x40000b90;\nr_ble_hw_rng_stop = 0x40000b94;\nr_ble_hw_rx_local_is_resolved = 0x40000b98;\nr_ble_hw_rx_local_is_rpa = 0x40000b9c;\nr_ble_hw_whitelist_add = 0x40000ba0;\nr_ble_hw_whitelist_clear = 0x40000ba4;\nr_ble_hw_whitelist_dev_num = 0x40000ba8;\nr_ble_hw_whitelist_get_base = 0x40000bac;\nr_ble_hw_whitelist_rmv = 0x40000bb0;\nr_ble_hw_whitelist_search = 0x40000bb4;\nr_ble_hw_whitelist_sort = 0x40000bb8;\nr_ble_ll_acl_data_in = 0x40000bbc;\nr_ble_ll_addr_is_id = 0x40000bc0;\nr_ble_ll_addr_subtype = 0x40000bc4;\nr_ble_ll_adv_active_chanset_clear = 0x40000bc8;\nr_ble_ll_adv_active_chanset_is_pri = 0x40000bcc;\nr_ble_ll_adv_active_chanset_is_sec = 0x40000bd0;\nr_ble_ll_adv_active_chanset_set_pri = 0x40000bd4;\nr_ble_ll_adv_active_chanset_set_sec = 0x40000bd8;\nr_ble_ll_adv_aux_calculate = 0x40000bdc;\nr_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000be0;\nr_ble_ll_adv_aux_pdu_make = 0x40000be4;\nr_ble_ll_adv_aux_scannable_pdu_make = 0x40000be8;\nr_ble_ll_adv_aux_txed = 0x40000bec;\nr_ble_ll_adv_can_chg_whitelist = 0x40000bf0;\nr_ble_ll_adv_chk_rpa_timeout = 0x40000bf4;\nr_ble_ll_adv_clear_all = 0x40000bf8;\nr_ble_ll_adv_conn_req_rxd = 0x40000bfc;\nr_ble_ll_adv_deinit = 0x40000c00;\nr_ble_ll_adv_enabled = 0x40000c04;\nr_ble_ll_adv_env_init = 0x40000c08;\nr_ble_ll_adv_ext_set_adv_data = 0x40000c0c;\nr_ble_ll_adv_ext_set_enable = 0x40000c10;\nr_ble_ll_adv_ext_set_param = 0x40000c14;\nr_ble_ll_adv_ext_set_scan_rsp = 0x40000c18;\nr_ble_ll_adv_final_chan = 0x40000c1c;\nr_ble_ll_adv_first_chan = 0x40000c20;\nr_ble_ll_adv_flags_clear = 0x40000c24;\nr_ble_ll_adv_flags_set = 0x40000c28;\nr_ble_ll_adv_get_chan_num = 0x40000c2c;\nr_ble_ll_adv_get_local_rpa = 0x40000c30;\nr_ble_ll_adv_get_peer_rpa = 0x40000c34;\nr_ble_ll_adv_hci_set_random_addr = 0x40000c38;\nr_ble_ll_adv_init = 0x40000c3c;\nr_ble_ll_adv_legacy_pdu_make = 0x40000c40;\nr_ble_ll_adv_next_chan = 0x40000c44;\nr_ble_ll_adv_pdu_make = 0x40000c48;\nr_ble_ll_adv_periodic_check_data_itvl = 0x40000c4c;\nr_ble_ll_adv_periodic_enable = 0x40000c50;\nr_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c54;\nr_ble_ll_adv_periodic_send_sync_ind = 0x40000c58;\nr_ble_ll_adv_periodic_set_data = 0x40000c5c;\nr_ble_ll_adv_periodic_set_info_transfer = 0x40000c60;\nr_ble_ll_adv_periodic_set_param = 0x40000c64;\nr_ble_ll_adv_pre_process = 0x40000c68;\nr_ble_ll_adv_put_acad_chM_update_ind = 0x40000c6c;\nr_ble_ll_adv_put_aux_ptr = 0x40000c70;\nr_ble_ll_adv_put_syncinfo = 0x40000c74;\nr_ble_ll_adv_rd_max_adv_data_len = 0x40000c78;\nr_ble_ll_adv_rd_sup_adv_sets = 0x40000c7c;\nr_ble_ll_adv_read_txpwr = 0x40000c80;\nr_ble_ll_adv_remove = 0x40000c84;\nr_ble_ll_adv_reset = 0x40000c88;\nr_ble_ll_adv_rpa_timeout = 0x40000c8c;\nr_ble_ll_adv_rpa_update = 0x40000c90;\nr_ble_ll_adv_rx_pkt_in = 0x40000c94;\nr_ble_ll_adv_scan_req_rxd = 0x40000c98;\nr_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c;\nr_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0;\nr_ble_ll_adv_scheduled = 0x40000ca4;\nr_ble_ll_adv_send_conn_comp_ev = 0x40000ca8;\nr_ble_ll_adv_set_adv_data = 0x40000cac;\nr_ble_ll_adv_set_adv_params = 0x40000cb0;\nr_ble_ll_adv_set_enable = 0x40000cb4;\nr_ble_ll_adv_set_random_addr = 0x40000cb8;\nr_ble_ll_adv_set_scan_rsp_data = 0x40000cbc;\nr_ble_ll_adv_set_sched = 0x40000cc0;\nr_ble_ll_adv_sm_deinit = 0x40000cc4;\nr_ble_ll_adv_sm_event_init = 0x40000cc8;\nr_ble_ll_adv_sm_find_configured = 0x40000ccc;\nr_ble_ll_adv_sm_get = 0x40000cd0;\nr_ble_ll_adv_sm_init = 0x40000cd4;\nr_ble_ll_adv_sm_reset = 0x40000cd8;\nr_ble_ll_adv_sm_start = 0x40000cdc;\nr_ble_ll_adv_sm_start_periodic = 0x40000ce0;\nr_ble_ll_adv_sm_stop = 0x40000ce4;\nr_ble_ll_adv_sm_stop_limit_reached = 0x40000ce8;\nr_ble_ll_adv_sm_stop_periodic = 0x40000cec;\nr_ble_ll_adv_sm_stop_timeout = 0x40000cf0;\nr_ble_ll_adv_sync_calculate = 0x40000cf4;\nr_ble_ll_adv_sync_get_pdu_len = 0x40000cf8;\nr_ble_ll_adv_sync_pdu_make = 0x40000cfc;\nr_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d00;\nr_ble_ll_adv_update_data_mbuf = 0x40000d04;\nr_ble_ll_adv_update_did = 0x40000d08;\nr_ble_ll_adv_update_periodic_data = 0x40000d0c;\nr_ble_ll_arr_pool_init = 0x40000d10;\nr_ble_ll_auth_pyld_tmo_event_send = 0x40000d14;\nr_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d18;\nr_ble_ll_calc_session_key = 0x40000d1c;\nr_ble_ll_calc_ticks_per_slot = 0x40000d20;\nr_ble_ll_check_scan_params = 0x40000d24;\nr_ble_ll_chk_txrx_octets = 0x40000d28;\nr_ble_ll_chk_txrx_time = 0x40000d2c;\nr_ble_ll_conn_adjust_pyld_len = 0x40000d30;\nr_ble_ll_conn_auth_pyld_timer_cb = 0x40000d34;\nr_ble_ll_conn_auth_pyld_timer_start = 0x40000d38;\nr_ble_ll_conn_calc_dci = 0x40000d3c;\nr_ble_ll_conn_calc_dci_csa1 = 0x40000d40;\nr_ble_ll_conn_calc_itvl_ticks = 0x40000d44;\nr_ble_ll_conn_chk_csm_flags = 0x40000d48;\nr_ble_ll_conn_chk_phy_upd_start = 0x40000d4c;\nr_ble_ll_conn_comp_event_send = 0x40000d50;\nr_ble_ll_conn_connect_ind_pdu_make = 0x40000d54;\nr_ble_ll_conn_create = 0x40000d58;\nr_ble_ll_conn_create_cancel = 0x40000d5c;\nr_ble_ll_conn_created = 0x40000d60;\nr_ble_ll_conn_cth_flow_enable = 0x40000d64;\nr_ble_ll_conn_cth_flow_error_fn = 0x40000d68;\nr_ble_ll_conn_cth_flow_have_credit = 0x40000d6c;\nr_ble_ll_conn_cth_flow_is_enabled = 0x40000d70;\nr_ble_ll_conn_cth_flow_process_cmd = 0x40000d74;\nr_ble_ll_conn_cth_flow_set_buffers = 0x40000d78;\nr_ble_ll_conn_enqueue_pkt = 0x40000d7c;\nr_ble_ll_conn_env_init = 0x40000d80;\nr_ble_ll_conn_ext_master_init = 0x40000d84;\nr_ble_ll_conn_find_active_conn = 0x40000d88;\nr_ble_ll_conn_get_active_conn = 0x40000d8c;\nr_ble_ll_conn_get_anchor = 0x40000d90;\nr_ble_ll_conn_hcc_params_set_fallback = 0x40000d94;\nr_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000d98;\nr_ble_ll_conn_hci_chk_conn_params = 0x40000d9c;\nr_ble_ll_conn_hci_chk_scan_params = 0x40000da0;\nr_ble_ll_conn_hci_disconnect_cmd = 0x40000da4;\nr_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000da8;\nr_ble_ll_conn_hci_le_ltk_reply = 0x40000dac;\nr_ble_ll_conn_hci_le_rd_phy = 0x40000db0;\nr_ble_ll_conn_hci_le_set_phy = 0x40000db4;\nr_ble_ll_conn_hci_le_start_encrypt = 0x40000db8;\nr_ble_ll_conn_hci_param_nrr = 0x40000dbc;\nr_ble_ll_conn_hci_param_rr = 0x40000dc0;\nr_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000dc4;\nr_ble_ll_conn_hci_rd_chan_map = 0x40000dc8;\nr_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000dcc;\nr_ble_ll_conn_hci_rd_rssi = 0x40000dd0;\nr_ble_ll_conn_hci_read_rem_features = 0x40000dd4;\nr_ble_ll_conn_hci_set_chan_class = 0x40000dd8;\nr_ble_ll_conn_hci_set_data_len = 0x40000ddc;\nr_ble_ll_conn_hci_update = 0x40000de0;\nr_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000de4;\nr_ble_ll_conn_init_phy = 0x40000de8;\nr_ble_ll_conn_is_dev_connected = 0x40000dec;\nr_ble_ll_conn_is_empty_pdu = 0x40000df0;\nr_ble_ll_conn_is_lru = 0x40000df4;\nr_ble_ll_conn_master_init = 0x40000df8;\nr_ble_ll_conn_module_deinit = 0x40000dfc;\nr_ble_ll_conn_module_init = 0x40000e00;\nr_ble_ll_conn_module_reset = 0x40000e04;\nr_ble_ll_conn_next_event = 0x40000e08;\nr_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c;\nr_ble_ll_conn_prepare_tx_pdu = 0x40000e10;\nr_ble_ll_conn_process_conn_params = 0x40000e14;\nr_ble_ll_conn_req_peer_sca = 0x40000e18;\nr_ble_ll_conn_rx_data_pdu = 0x40000e1c;\nr_ble_ll_conn_set_csa = 0x40000e20;\nr_ble_ll_conn_set_ext_con_params = 0x40000e24;\nr_ble_ll_conn_set_global_chanmap = 0x40000e28;\nr_ble_ll_conn_set_phy = 0x40000e2c;\nr_ble_ll_conn_set_txpwr_by_handle = 0x40000e30;\nr_ble_ll_conn_set_unknown_rx_octets = 0x40000e34;\nr_ble_ll_conn_slave_start = 0x40000e38;\nr_ble_ll_conn_sm_get = 0x40000e3c;\nr_ble_ll_conn_sm_new = 0x40000e40;\nr_ble_ll_conn_sm_npl_deinit = 0x40000e44;\nr_ble_ll_conn_sm_npl_init = 0x40000e48;\nr_ble_ll_conn_tx_pkt_in = 0x40000e4c;\nr_ble_ll_conn_update_eff_data_len = 0x40000e50;\nr_ble_ll_ctrl_chanmap_req_make = 0x40000e54;\nr_ble_ll_ctrl_chk_proc_start = 0x40000e58;\nr_ble_ll_ctrl_conn_param_pdu_make = 0x40000e5c;\nr_ble_ll_ctrl_conn_param_pdu_proc = 0x40000e60;\nr_ble_ll_ctrl_conn_param_reply = 0x40000e64;\nr_ble_ll_ctrl_conn_upd_make = 0x40000e68;\nr_ble_ll_ctrl_datalen_upd_make = 0x40000e6c;\nr_ble_ll_ctrl_enc_allowed_pdu = 0x40000e70;\nr_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000e74;\nr_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40000e78;\nr_ble_ll_ctrl_enc_req_make = 0x40000e7c;\nr_ble_ll_ctrl_find_new_phy = 0x40000e80;\nr_ble_ll_ctrl_initiate_dle = 0x40000e84;\nr_ble_ll_ctrl_len_proc = 0x40000e88;\nr_ble_ll_ctrl_min_used_chan_rsp = 0x40000e8c;\nr_ble_ll_ctrl_phy_from_phy_mask = 0x40000e90;\nr_ble_ll_ctrl_phy_req_rsp_make = 0x40000e94;\nr_ble_ll_ctrl_phy_tx_transition_get = 0x40000e98;\nr_ble_ll_ctrl_phy_update_cancel = 0x40000e9c;\nr_ble_ll_ctrl_phy_update_ind_make = 0x40000ea0;\nr_ble_ll_ctrl_phy_update_proc_complete = 0x40000ea4;\nr_ble_ll_ctrl_proc_init = 0x40000ea8;\nr_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000eac;\nr_ble_ll_ctrl_proc_start = 0x40000eb0;\nr_ble_ll_ctrl_proc_stop = 0x40000eb4;\nr_ble_ll_ctrl_proc_unk_rsp = 0x40000eb8;\nr_ble_ll_ctrl_proc_with_instant_initiated = 0x40000ebc;\nr_ble_ll_ctrl_rej_ext_ind_make = 0x40000ec0;\nr_ble_ll_ctrl_reject_ind_send = 0x40000ec4;\nr_ble_ll_ctrl_rx_chanmap_req = 0x40000ec8;\nr_ble_ll_ctrl_rx_conn_param_req = 0x40000ecc;\nr_ble_ll_ctrl_rx_conn_param_rsp = 0x40000ed0;\nr_ble_ll_ctrl_rx_conn_update = 0x40000ed4;\nr_ble_ll_ctrl_rx_enc_req = 0x40000ed8;\nr_ble_ll_ctrl_rx_enc_rsp = 0x40000edc;\nr_ble_ll_ctrl_rx_feature_req = 0x40000ee0;\nr_ble_ll_ctrl_rx_feature_rsp = 0x40000ee4;\nr_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8;\nr_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec;\nr_ble_ll_ctrl_rx_pdu = 0x40000ef0;\nr_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4;\nr_ble_ll_ctrl_rx_phy_req = 0x40000ef8;\nr_ble_ll_ctrl_rx_phy_rsp = 0x40000efc;\nr_ble_ll_ctrl_rx_phy_update_ind = 0x40000f00;\nr_ble_ll_ctrl_rx_ping_rsp = 0x40000f04;\nr_ble_ll_ctrl_rx_reject_ind = 0x40000f08;\nr_ble_ll_ctrl_rx_sca_req = 0x40000f0c;\nr_ble_ll_ctrl_rx_sca_rsp = 0x40000f10;\nr_ble_ll_ctrl_rx_start_enc_req = 0x40000f14;\nr_ble_ll_ctrl_rx_start_enc_rsp = 0x40000f18;\nr_ble_ll_ctrl_rx_version_ind = 0x40000f1c;\nr_ble_ll_ctrl_sca_req_rsp_make = 0x40000f20;\nr_ble_ll_ctrl_start_enc_send = 0x40000f24;\nr_ble_ll_ctrl_start_rsp_timer = 0x40000f28;\nr_ble_ll_ctrl_terminate_start = 0x40000f2c;\nr_ble_ll_ctrl_tx_done = 0x40000f30;\nr_ble_ll_ctrl_update_features = 0x40000f34;\nr_ble_ll_ctrl_version_ind_make = 0x40000f38;\nr_ble_ll_data_buffer_overflow = 0x40000f3c;\nr_ble_ll_deinit = 0x40000f40;\nr_ble_ll_disconn_comp_event_send = 0x40000f44;\nr_ble_ll_env_init = 0x40000f48;\nr_ble_ll_event_comp_pkts = 0x40000f4c;\nr_ble_ll_event_dbuf_overflow = 0x40000f50;\nr_ble_ll_event_send = 0x40000f54;\nr_ble_ll_event_tx_pkt = 0x40000f58;\nr_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40000f5c;\nr_ble_ll_ext_conn_create = 0x40000f60;\nr_ble_ll_ext_scan_parse_adv_info = 0x40000f64;\nr_ble_ll_ext_scan_parse_aux_ptr = 0x40000f68;\nr_ble_ll_flush_pkt_queue = 0x40000f6c;\nr_ble_ll_generate_dh_key_v1 = 0x40000f70;\nr_ble_ll_generate_dh_key_v2 = 0x40000f74;\nr_ble_ll_generic_data_init = 0x40000f78;\nr_ble_ll_get_addr_type = 0x40000f7c;\nr_ble_ll_get_chan_to_scan = 0x40000f80;\nr_ble_ll_get_our_devaddr = 0x40000f84;\nr_ble_ll_get_tx_pwr_compensation = 0x40000f88;\nr_ble_ll_hci_acl_rx = 0x40000f8c;\nr_ble_ll_hci_adv_mode_ext = 0x40000f90;\nr_ble_ll_hci_adv_set_enable = 0x40000f94;\nr_ble_ll_hci_cb_host_buf_size = 0x40000f98;\nr_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x40000f9c;\nr_ble_ll_hci_cb_set_event_mask = 0x40000fa0;\nr_ble_ll_hci_cb_set_event_mask2 = 0x40000fa4;\nr_ble_ll_hci_chk_phy_masks = 0x40000fa8;\nr_ble_ll_hci_cmd_proc = 0x40000fac;\nr_ble_ll_hci_cmd_rx = 0x40000fb0;\nr_ble_ll_hci_ctlr_bb_cmd_proc = 0x40000fb4;\nr_ble_ll_hci_deinit = 0x40000fb8;\nr_ble_ll_hci_disconnect = 0x40000fbc;\nr_ble_ll_hci_env_init = 0x40000fc0;\nr_ble_ll_hci_ev_conn_update = 0x40000fc4;\nr_ble_ll_hci_ev_databuf_overflow = 0x40000fc8;\nr_ble_ll_hci_ev_datalen_chg = 0x40000fcc;\nr_ble_ll_hci_ev_encrypt_chg = 0x40000fd0;\nr_ble_ll_hci_ev_hw_err = 0x40000fd4;\nr_ble_ll_hci_ev_le_csa = 0x40000fd8;\nr_ble_ll_hci_ev_ltk_req = 0x40000fdc;\nr_ble_ll_hci_ev_phy_update = 0x40000fe0;\nr_ble_ll_hci_ev_rd_rem_used_feat = 0x40000fe4;\nr_ble_ll_hci_ev_rd_rem_ver = 0x40000fe8;\nr_ble_ll_hci_ev_rem_conn_parm_req = 0x40000fec;\nr_ble_ll_hci_ev_sca_update = 0x40000ff0;\nr_ble_ll_hci_ev_send_adv_set_terminated = 0x40000ff4;\nr_ble_ll_hci_ev_send_scan_req_recv = 0x40000ff8;\nr_ble_ll_hci_ev_send_scan_timeout = 0x40000ffc;\nr_ble_ll_hci_ev_send_vendor_err = 0x40001000;\nr_ble_ll_hci_event_send = 0x40001004;\nr_ble_ll_hci_ext_scan_set_enable = 0x40001008;\nr_ble_ll_hci_get_num_cmd_pkts = 0x4000100c;\nr_ble_ll_hci_info_params_cmd_proc = 0x40001010;\nr_ble_ll_hci_init = 0x40001014;\nr_ble_ll_hci_init_support_cmd_base_on_lmp_ver = 0x40001018;\nr_ble_ll_hci_is_event_enabled = 0x4000101c;\nr_ble_ll_hci_is_le_event_enabled = 0x40001020;\nr_ble_ll_hci_le_cmd_proc = 0x40001024;\nr_ble_ll_hci_le_cmd_send_cmd_status = 0x40001028;\nr_ble_ll_hci_le_encrypt = 0x4000102c;\nr_ble_ll_hci_le_rand = 0x40001030;\nr_ble_ll_hci_le_rd_max_data_len = 0x40001034;\nr_ble_ll_hci_le_rd_sugg_data_len = 0x40001038;\nr_ble_ll_hci_le_read_bufsize = 0x4000103c;\nr_ble_ll_hci_le_read_local_features = 0x40001040;\nr_ble_ll_hci_le_read_supp_states = 0x40001044;\nr_ble_ll_hci_le_set_def_phy = 0x40001048;\nr_ble_ll_hci_le_wr_sugg_data_len = 0x4000104c;\nr_ble_ll_hci_link_ctrl_cmd_proc = 0x40001050;\nr_ble_ll_hci_npl_init = 0x40001054;\nr_ble_ll_hci_post_gen_dhkey_cmp_evt = 0x40001058;\nr_ble_ll_hci_post_rd_p256_pubkey_cmp_evt = 0x4000105c;\nr_ble_ll_hci_rd_bd_addr = 0x40001060;\nr_ble_ll_hci_rd_local_supp_cmd = 0x40001064;\nr_ble_ll_hci_rd_local_supp_feat = 0x40001068;\nr_ble_ll_hci_rd_local_version = 0x4000106c;\nr_ble_ll_hci_scan_set_enable = 0x40001070;\nr_ble_ll_hci_send_adv_report = 0x40001074;\nr_ble_ll_hci_send_dir_adv_report = 0x40001078;\nr_ble_ll_hci_send_ext_adv_report = 0x4000107c;\nr_ble_ll_hci_send_legacy_ext_adv_report = 0x40001080;\nr_ble_ll_hci_send_noop = 0x40001084;\nr_ble_ll_hci_set_adv_data = 0x40001088;\nr_ble_ll_hci_set_le_event_mask = 0x4000108c;\nr_ble_ll_hci_set_scan_rsp_data = 0x40001090;\nr_ble_ll_hci_status_params_cmd_proc = 0x40001094;\nr_ble_ll_hci_vs_cmd_proc = 0x40001098;\nr_ble_ll_hci_vs_rd_static_addr = 0x4000109c;\nr_ble_ll_hw_err_timer_cb = 0x400010a0;\nr_ble_ll_hw_error = 0x400010a4;\nr_ble_ll_init = 0x400010a8;\nr_ble_ll_init_alloc_conn_comp_ev = 0x400010ac;\nr_ble_ll_init_get_conn_comp_ev = 0x400010b0;\nr_ble_ll_init_rx_pkt_in = 0x400010b4;\nr_ble_ll_is_addr_empty = 0x400010b8;\nr_ble_ll_is_controller_busy = 0x400010bc;\nr_ble_ll_is_on_resolv_list = 0x400010c0;\nr_ble_ll_is_our_devaddr = 0x400010c4;\nr_ble_ll_is_rpa = 0x400010c8;\nr_ble_ll_is_valid_adv_mode = 0x400010cc;\nr_ble_ll_is_valid_own_addr_type = 0x400010d0;\nr_ble_ll_is_valid_public_addr = 0x400010d4;\nr_ble_ll_is_valid_random_addr = 0x400010d8;\nr_ble_ll_mbuf_init = 0x400010dc;\nr_ble_ll_misc_options_set = 0x400010e0;\nr_ble_ll_modify_sca = 0x400010e4;\nr_ble_ll_modify_sca_action = 0x400010e8;\nr_ble_ll_pdu_max_tx_octets_get = 0x400010ec;\nr_ble_ll_pdu_tx_time_get = 0x400010f0;\nr_ble_ll_phy_to_phy_mode = 0x400010f4;\nr_ble_ll_qa_enable = 0x400010f8;\nr_ble_ll_rand = 0x400010fc;\nr_ble_ll_rand_data_get = 0x40001100;\nr_ble_ll_rand_deinit = 0x40001104;\nr_ble_ll_rand_env_init = 0x40001108;\nr_ble_ll_rand_init = 0x4000110c;\nr_ble_ll_rand_prand_get = 0x40001110;\nr_ble_ll_rand_sample = 0x40001114;\nr_ble_ll_rand_start = 0x40001118;\nr_ble_ll_read_local_p256_pub_key = 0x4000111c;\nr_ble_ll_read_rf_path_compensation = 0x40001120;\nr_ble_ll_read_supp_features = 0x40001124;\nr_ble_ll_read_supp_states = 0x40001128;\nr_ble_ll_read_tx_power = 0x4000112c;\nr_ble_ll_reset = 0x40001130;\nr_ble_ll_resolv_clear_all_pl_bit = 0x40001134;\nr_ble_ll_resolv_clear_all_wl_bit = 0x40001138;\nr_ble_ll_resolv_deinit = 0x4000113c;\nr_ble_ll_resolv_enable_cmd = 0x40001140;\nr_ble_ll_resolv_enabled = 0x40001144;\nr_ble_ll_resolv_env_init = 0x40001148;\nr_ble_ll_resolv_gen_priv_addr = 0x4000114c;\nr_ble_ll_resolv_gen_rpa = 0x40001150;\nr_ble_ll_resolv_get_addr_pointer = 0x40001154;\nr_ble_ll_resolv_get_index = 0x40001158;\nr_ble_ll_resolv_get_irk_pointer = 0x4000115c;\nr_ble_ll_resolv_get_list = 0x40001160;\nr_ble_ll_resolv_get_priv_addr = 0x40001164;\nr_ble_ll_resolv_get_rpa_tmo = 0x40001168;\nr_ble_ll_resolv_init = 0x4000116c;\nr_ble_ll_resolv_irk_nonzero = 0x40001170;\nr_ble_ll_resolv_list_add = 0x40001174;\nr_ble_ll_resolv_list_chg_allowed = 0x40001178;\nr_ble_ll_resolv_list_clr = 0x4000117c;\nr_ble_ll_resolv_list_find = 0x40001180;\nr_ble_ll_resolv_list_read_size = 0x40001184;\nr_ble_ll_resolv_list_reset = 0x40001188;\nr_ble_ll_resolv_list_rmv = 0x4000118c;\nr_ble_ll_resolv_local_addr_rd = 0x40001190;\nr_ble_ll_resolv_peer_addr_rd = 0x40001194;\nr_ble_ll_resolv_peer_rpa_any = 0x40001198;\nr_ble_ll_resolv_reset = 0x4000119c;\nr_ble_ll_resolv_rpa = 0x400011a0;\nr_ble_ll_resolv_rpa_timer_cb = 0x400011a4;\nr_ble_ll_resolv_set_local_rpa = 0x400011a8;\nr_ble_ll_resolv_set_peer_rpa = 0x400011ac;\nr_ble_ll_resolv_set_rpa_tmo = 0x400011b0;\nr_ble_ll_resolve_set_priv_mode = 0x400011b4;\nr_ble_ll_rxpdu_alloc = 0x400011b8;\nr_ble_ll_scan_add_scan_rsp_adv = 0x400011bc;\nr_ble_ll_scan_adv_decode_addr = 0x400011c0;\nr_ble_ll_scan_aux_data_ref = 0x400011c4;\nr_ble_ll_scan_aux_data_unref = 0x400011c8;\nr_ble_ll_scan_can_chg_whitelist = 0x400011cc;\nr_ble_ll_scan_check_periodic_sync = 0x400011d0;\nr_ble_ll_scan_classify_filter_aux_init = 0x400011d4;\nr_ble_ll_scan_classify_filter_init = 0x400011d8;\nr_ble_ll_scan_common_init = 0x400011dc;\nr_ble_ll_scan_continue_en = 0x400011e0;\nr_ble_ll_scan_deinit = 0x400011e4;\nr_ble_ll_scan_dup_check_ext = 0x400011e8;\nr_ble_ll_scan_dup_check_legacy = 0x400011ec;\nr_ble_ll_scan_dup_move_to_head = 0x400011f0;\nr_ble_ll_scan_dup_new = 0x400011f4;\nr_ble_ll_scan_dup_update_ext = 0x400011f8;\nr_ble_ll_scan_dup_update_legacy = 0x400011fc;\nr_ble_ll_scan_enabled = 0x40001200;\nr_ble_ll_scan_end_adv_evt = 0x40001204;\nr_ble_ll_scan_env_init = 0x40001208;\nr_ble_ll_scan_ext_initiator_start = 0x4000120c;\nr_ble_ll_scan_get_addr_data_from_legacy = 0x40001210;\nr_ble_ll_scan_get_addr_from_ext_adv = 0x40001214;\nr_ble_ll_scan_get_cur_sm = 0x40001218;\nr_ble_ll_scan_get_ext_adv_report = 0x4000121c;\nr_ble_ll_scan_get_local_rpa = 0x40001220;\nr_ble_ll_scan_get_next_adv_prim_chan = 0x40001224;\nr_ble_ll_scan_get_peer_rpa = 0x40001228;\nr_ble_ll_scan_have_rxd_scan_rsp = 0x4000122c;\nr_ble_ll_scan_init = 0x40001230;\nr_ble_ll_scan_initiator_start = 0x40001234;\nr_ble_ll_scan_is_inside_window = 0x40001238;\nr_ble_ll_scan_move_window_to = 0x4000123c;\nr_ble_ll_scan_npl_reset = 0x40001240;\nr_ble_ll_scan_parse_auxptr = 0x40001244;\nr_ble_ll_scan_parse_ext_hdr = 0x40001248;\nr_ble_ll_scan_pre_process = 0x4000124c;\nr_ble_ll_scan_record_new_adv = 0x40001250;\nr_ble_ll_scan_refresh_nrpa = 0x40001254;\nr_ble_ll_scan_reset = 0x40001258;\nr_ble_ll_scan_rx_pkt_in = 0x4000125c;\nr_ble_ll_scan_rx_pkt_in_on_aux = 0x40001260;\nr_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001264;\nr_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268;\nr_ble_ll_scan_rxed = 0x4000126c;\nr_ble_ll_scan_send_adv_report = 0x40001270;\nr_ble_ll_scan_send_truncated = 0x40001274;\nr_ble_ll_scan_set_enable = 0x40001278;\nr_ble_ll_scan_set_peer_rpa = 0x4000127c;\nr_ble_ll_scan_set_perfer_addr = 0x40001280;\nr_ble_ll_scan_set_scan_params = 0x40001284;\nr_ble_ll_scan_sm_start = 0x40001288;\nr_ble_ll_scan_sm_stop = 0x4000128c;\nr_ble_ll_scan_time_hci_to_ticks = 0x40001290;\nr_ble_ll_scan_update_aux_data = 0x40001294;\nr_ble_ll_scan_whitelist_enabled = 0x40001298;\nr_ble_ll_set_default_privacy_mode = 0x4000129c;\nr_ble_ll_set_default_sync_transfer_params = 0x400012a0;\nr_ble_ll_set_ext_scan_params = 0x400012a4;\nr_ble_ll_set_host_feat = 0x400012a8;\nr_ble_ll_set_public_addr = 0x400012ac;\nr_ble_ll_set_random_addr = 0x400012b0;\nr_ble_ll_set_sync_transfer_params = 0x400012b4;\nr_ble_ll_state_get = 0x400012b8;\nr_ble_ll_state_set = 0x400012bc;\nr_ble_ll_sync_adjust_ext_hdr = 0x400012c0;\nr_ble_ll_sync_cancel = 0x400012c4;\nr_ble_ll_sync_cancel_complete_event = 0x400012c8;\nr_ble_ll_sync_check_acad = 0x400012cc;\nr_ble_ll_sync_check_failed = 0x400012d0;\nr_ble_ll_sync_create = 0x400012d4;\nr_ble_ll_sync_deinit = 0x400012d8;\nr_ble_ll_sync_enabled = 0x400012dc;\nr_ble_ll_sync_env_init = 0x400012e0;\nr_ble_ll_sync_est_event_failed = 0x400012e4;\nr_ble_ll_sync_est_event_success = 0x400012e8;\nr_ble_ll_sync_established = 0x400012ec;\nr_ble_ll_sync_filter_enabled = 0x400012f0;\nr_ble_ll_sync_find = 0x400012f4;\nr_ble_ll_sync_get_cur_sm = 0x400012f8;\nr_ble_ll_sync_get_handle = 0x400012fc;\nr_ble_ll_sync_get_sm = 0x40001300;\nr_ble_ll_sync_info_event = 0x40001304;\nr_ble_ll_sync_init = 0x40001308;\nr_ble_ll_sync_list_add = 0x4000130c;\nr_ble_ll_sync_list_clear = 0x40001310;\nr_ble_ll_sync_list_empty = 0x40001314;\nr_ble_ll_sync_list_get_free = 0x40001318;\nr_ble_ll_sync_list_remove = 0x4000131c;\nr_ble_ll_sync_list_search = 0x40001320;\nr_ble_ll_sync_list_size = 0x40001324;\nr_ble_ll_sync_lost_event = 0x40001328;\nr_ble_ll_sync_next_event = 0x4000132c;\nr_ble_ll_sync_on_list = 0x40001330;\nr_ble_ll_sync_parse_ext_hdr = 0x40001334;\nr_ble_ll_sync_periodic_ind = 0x40001338;\nr_ble_ll_sync_phy_mode_to_aux_phy = 0x4000133c;\nr_ble_ll_sync_phy_mode_to_hci = 0x40001340;\nr_ble_ll_sync_put_syncinfo = 0x40001344;\nr_ble_ll_sync_receive_enable = 0x40001348;\nr_ble_ll_sync_reserve = 0x4000134c;\nr_ble_ll_sync_reset = 0x40001350;\nr_ble_ll_sync_reset_sm = 0x40001354;\nr_ble_ll_sync_rx_pkt_in = 0x40001358;\nr_ble_ll_sync_send_per_adv_rpt = 0x4000135c;\nr_ble_ll_sync_send_sync_ind = 0x40001360;\nr_ble_ll_sync_send_truncated_per_adv_rpt = 0x40001364;\nr_ble_ll_sync_sm_clear = 0x40001368;\nr_ble_ll_sync_terminate = 0x4000136c;\nr_ble_ll_sync_transfer = 0x40001370;\nr_ble_ll_sync_transfer_get = 0x40001374;\nr_ble_ll_sync_transfer_received = 0x40001378;\nr_ble_ll_task = 0x4000137c;\nr_ble_ll_trace_set_func = 0x40001380;\nr_ble_ll_trace_u32 = 0x40001384;\nr_ble_ll_trace_u32x2 = 0x40001388;\nr_ble_ll_trace_u32x3 = 0x4000138c;\nr_ble_ll_tx_flat_mbuf_pducb = 0x40001390;\nr_ble_ll_tx_mbuf_pducb = 0x40001394;\nr_ble_ll_tx_pkt_in = 0x40001398;\nr_ble_ll_update_max_tx_octets_phy_mode = 0x4000139c;\nr_ble_ll_usecs_to_ticks_round_up = 0x400013a0;\nr_ble_ll_utils_calc_access_addr = 0x400013a4;\nr_ble_ll_utils_calc_dci_csa2 = 0x400013a8;\nr_ble_ll_utils_calc_num_used_chans = 0x400013ac;\nr_ble_ll_utils_calc_window_widening = 0x400013b0;\nr_ble_ll_utils_csa2_perm = 0x400013b4;\nr_ble_ll_utils_csa2_prng = 0x400013b8;\nr_ble_ll_utils_remapped_channel = 0x400013bc;\nr_ble_ll_whitelist_add = 0x400013c0;\nr_ble_ll_whitelist_chg_allowed = 0x400013c4;\nr_ble_ll_whitelist_clear = 0x400013c8;\nr_ble_ll_whitelist_read_size = 0x400013cc;\nr_ble_ll_whitelist_rmv = 0x400013d0;\nr_ble_ll_whitelist_search = 0x400013d4;\nr_ble_ll_write_rf_path_compensation = 0x400013d8;\nr_ble_lll_adv_aux_scannable_pdu_payload_len = 0x400013dc;\nr_ble_lll_adv_aux_schedule = 0x400013e0;\nr_ble_lll_adv_aux_schedule_first = 0x400013e4;\nr_ble_lll_adv_aux_schedule_next = 0x400013e8;\nr_ble_lll_adv_aux_scheduled = 0x400013ec;\nr_ble_lll_adv_aux_set_start_time = 0x400013f0;\nr_ble_lll_adv_coex_dpc_calc_pti_update_itvl = 0x400013f4;\nr_ble_lll_adv_coex_dpc_process_pri = 0x400013f8;\nr_ble_lll_adv_coex_dpc_process_sec = 0x400013fc;\nr_ble_lll_adv_coex_dpc_pti_get = 0x40001400;\nr_ble_lll_adv_coex_dpc_update = 0x40001404;\nr_ble_lll_adv_coex_dpc_update_on_adv_start = 0x40001408;\nr_ble_lll_adv_coex_dpc_update_on_aux_scheduled = 0x4000140c;\nr_ble_lll_adv_coex_dpc_update_on_data_updated = 0x40001410;\nr_ble_lll_adv_coex_dpc_update_on_event_end = 0x40001414;\nr_ble_lll_adv_coex_dpc_update_on_event_scheduled = 0x40001418;\nr_ble_lll_adv_done = 0x4000141c;\nr_ble_lll_adv_drop_event = 0x40001420;\nr_ble_lll_adv_event_done = 0x40001424;\nr_ble_lll_adv_event_rmvd_from_sched = 0x40001428;\nr_ble_lll_adv_ext_estimate_data_itvl = 0x4000142c;\nr_ble_lll_adv_get_sec_pdu_len = 0x40001430;\nr_ble_lll_adv_halt = 0x40001434;\nr_ble_lll_adv_make_done = 0x40001438;\nr_ble_lll_adv_periodic_done = 0x4000143c;\nr_ble_lll_adv_periodic_event_done = 0x40001440;\nr_ble_lll_adv_periodic_rmvd_from_sched = 0x40001444;\nr_ble_lll_adv_periodic_schedule_first = 0x40001448;\nr_ble_lll_adv_periodic_schedule_next = 0x4000144c;\nr_ble_lll_adv_periodic_start = 0x40001450;\nr_ble_lll_adv_periodic_stop = 0x40001454;\nr_ble_lll_adv_pri_schedule_tx_pdu = 0x40001458;\nr_ble_lll_adv_reschedule_event = 0x4000145c;\nr_ble_lll_adv_reschedule_periodic_event = 0x40001460;\nr_ble_lll_adv_rx_pkt_isr = 0x40001464;\nr_ble_lll_adv_sec_done = 0x40001468;\nr_ble_lll_adv_sec_event_done = 0x4000146c;\nr_ble_lll_adv_sec_schedule_next_aux = 0x40001470;\nr_ble_lll_adv_secondary_tx_start_cb = 0x40001474;\nr_ble_lll_adv_sm_deinit = 0x40001478;\nr_ble_lll_adv_sm_event_init = 0x4000147c;\nr_ble_lll_adv_sm_event_restore = 0x40001480;\nr_ble_lll_adv_sm_event_store = 0x40001484;\nr_ble_lll_adv_sm_init = 0x40001488;\nr_ble_lll_adv_sm_reset = 0x4000148c;\nr_ble_lll_adv_start = 0x40001490;\nr_ble_lll_adv_stop = 0x40001494;\nr_ble_lll_adv_sync_next_scheduled = 0x40001498;\nr_ble_lll_adv_sync_schedule = 0x4000149c;\nr_ble_lll_adv_sync_tx_done = 0x400014a0;\nr_ble_lll_adv_sync_tx_end = 0x400014a4;\nr_ble_lll_adv_sync_tx_start_cb = 0x400014a8;\nr_ble_lll_adv_tx_done = 0x400014ac;\nr_ble_lll_adv_tx_start_cb = 0x400014b0;\nr_ble_lll_adv_update_rsp_offset = 0x400014b4;\nr_ble_lll_aux_scan_cb = 0x400014b8;\nr_ble_lll_aux_scan_drop = 0x400014bc;\nr_ble_lll_aux_scan_drop_event_cb = 0x400014c0;\nr_ble_lll_calc_us_convert_tick_unit = 0x400014c4;\nr_ble_lll_conn_append_tx_buffer = 0x400014c8;\nr_ble_lll_conn_can_send_next_pdu = 0x400014cc;\nr_ble_lll_conn_check_opcode_matched = 0x400014d0;\nr_ble_lll_conn_coex_dpc_process = 0x400014d4;\nr_ble_lll_conn_coex_dpc_pti_get = 0x400014d8;\nr_ble_lll_conn_coex_dpc_update = 0x400014dc;\nr_ble_lll_conn_coex_dpc_update_on_event_end = 0x400014e0;\nr_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4;\nr_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8;\nr_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec;\nr_ble_lll_conn_cth_flow_free_credit = 0x400014f0;\nr_ble_lll_conn_current_sm_over = 0x400014f4;\nr_ble_lll_conn_end = 0x400014f8;\nr_ble_lll_conn_env_deinit = 0x400014fc;\nr_ble_lll_conn_env_init = 0x40001500;\nr_ble_lll_conn_event_end = 0x40001504;\nr_ble_lll_conn_event_end_timer_cb = 0x40001508;\nr_ble_lll_conn_event_halt = 0x4000150c;\nr_ble_lll_conn_event_is_over = 0x40001510;\nr_ble_lll_conn_event_start_cb = 0x40001514;\nr_ble_lll_conn_free_rx_mbuf = 0x40001518;\nr_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c;\nr_ble_lll_conn_get_ce_end_time = 0x40001520;\nr_ble_lll_conn_get_next_sched_time = 0x40001524;\nr_ble_lll_conn_get_rx_mbuf = 0x40001528;\nr_ble_lll_conn_halt = 0x4000152c;\nr_ble_lll_conn_master_common_init = 0x40001530;\nr_ble_lll_conn_master_new = 0x40001534;\nr_ble_lll_conn_module_deinit = 0x40001538;\nr_ble_lll_conn_module_init = 0x4000153c;\nr_ble_lll_conn_module_reset = 0x40001540;\nr_ble_lll_conn_no_mem_evt_pre_cb = 0x40001544;\nr_ble_lll_conn_pre_process = 0x40001548;\nr_ble_lll_conn_process_acked_pdu = 0x4000154c;\nr_ble_lll_conn_process_in_isr = 0x40001550;\nr_ble_lll_conn_recv_ack = 0x40001554;\nr_ble_lll_conn_recv_valid_packet = 0x40001558;\nr_ble_lll_conn_reset_pending_sched = 0x4000155c;\nr_ble_lll_conn_rx_pkt_isr = 0x40001560;\nr_ble_lll_conn_sched_next_anchor = 0x40001564;\nr_ble_lll_conn_sched_next_event = 0x40001568;\nr_ble_lll_conn_set_slave_flow_control = 0x4000156c;\nr_ble_lll_conn_slave_new = 0x40001570;\nr_ble_lll_conn_sm_new = 0x40001574;\nr_ble_lll_conn_sm_npl_deinit = 0x40001578;\nr_ble_lll_conn_sm_npl_init = 0x4000157c;\nr_ble_lll_conn_superversion_timer_cb = 0x40001580;\nr_ble_lll_conn_timeout = 0x40001584;\nr_ble_lll_conn_update_anchor = 0x40001588;\nr_ble_lll_conn_update_conn_ind_params = 0x4000158c;\nr_ble_lll_conn_update_encryption = 0x40001590;\nr_ble_lll_conn_update_tx_buffer = 0x40001594;\nr_ble_lll_deinit = 0x40001598;\nr_ble_lll_dtm_calculate_itvl = 0x4000159c;\nr_ble_lll_dtm_ctx_free = 0x400015a0;\nr_ble_lll_dtm_deinit = 0x400015a4;\nr_ble_lll_dtm_end_test = 0x400015a8;\nr_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;\nr_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;\nr_ble_lll_dtm_init = 0x400015b4;\nr_ble_lll_dtm_reset = 0x400015b8;\nr_ble_lll_dtm_rx_create_ctx = 0x400015bc;\nr_ble_lll_dtm_rx_isr_end = 0x400015c0;\nr_ble_lll_dtm_rx_isr_start = 0x400015c4;\nr_ble_lll_dtm_rx_pkt_in = 0x400015c8;\nr_ble_lll_dtm_rx_sched_cb = 0x400015cc;\nr_ble_lll_dtm_rx_start = 0x400015d0;\nr_ble_lll_dtm_rx_test = 0x400015d4;\nr_ble_lll_dtm_set_next = 0x400015d8;\nr_ble_lll_dtm_tx_create_ctx = 0x400015dc;\nr_ble_lll_dtm_tx_done = 0x400015e0;\nr_ble_lll_dtm_tx_sched_cb = 0x400015e4;\nr_ble_lll_dtm_tx_test = 0x400015e8;\nr_ble_lll_dtm_wfr_timer_exp = 0x400015ec;\nr_ble_lll_event_rx_pkt = 0x400015f0;\nr_ble_lll_ext_scan_coex_dpc_process = 0x400015f4;\nr_ble_lll_ext_scan_coex_dpc_pti_get = 0x400015f8;\nr_ble_lll_ext_scan_coex_dpc_update = 0x400015fc;\nr_ble_lll_ext_scan_coex_dpc_update_on_start = 0x40001600;\nr_ble_lll_hci_dtm_rx_test = 0x40001604;\nr_ble_lll_hci_dtm_rx_test_v2 = 0x40001608;\nr_ble_lll_hci_dtm_tx_test = 0x4000160c;\nr_ble_lll_hci_dtm_tx_test_ext = 0x40001610;\nr_ble_lll_hci_dtm_tx_test_v2 = 0x40001614;\nr_ble_lll_hci_dtm_tx_test_v2_ext = 0x40001618;\nr_ble_lll_init = 0x4000161c;\nr_ble_lll_init_pre_process = 0x40001620;\nr_ble_lll_init_rx_pkt_isr = 0x40001624;\nr_ble_lll_per_adv_coex_dpc_calc_pti_update_itvl = 0x40001628;\nr_ble_lll_per_adv_coex_dpc_process = 0x4000162c;\nr_ble_lll_per_adv_coex_dpc_pti_get = 0x40001630;\nr_ble_lll_per_adv_coex_dpc_update = 0x40001634;\nr_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638;\nr_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c;\nr_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640;\nr_ble_lll_reset = 0x40001644;\nr_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;\nr_ble_lll_rfmgmt_deinit = 0x4000164c;\nr_ble_lll_rfmgmt_disable = 0x40001650;\nr_ble_lll_rfmgmt_enable = 0x40001654;\nr_ble_lll_rfmgmt_enable_now = 0x40001658;\nr_ble_lll_rfmgmt_init = 0x4000165c;\nr_ble_lll_rfmgmt_is_enabled = 0x40001660;\nr_ble_lll_rfmgmt_release = 0x40001664;\nr_ble_lll_rfmgmt_release_ev = 0x40001668;\nr_ble_lll_rfmgmt_reset = 0x4000166c;\nr_ble_lll_rfmgmt_scan_changed = 0x40001670;\nr_ble_lll_rfmgmt_sched_changed = 0x40001674;\nr_ble_lll_rfmgmt_set_sleep_cb = 0x40001678;\nr_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c;\nr_ble_lll_rfmgmt_timer_exp = 0x40001680;\nr_ble_lll_rfmgmt_timer_reschedule = 0x40001684;\nr_ble_lll_rx_pdu_in = 0x40001688;\nr_ble_lll_rx_pkt_in = 0x4000168c;\nr_ble_lll_rx_pkt_isr = 0x40001690;\nr_ble_lll_scan_abort_aux_sched = 0x40001694;\nr_ble_lll_scan_aux_data_free = 0x40001698;\nr_ble_lll_scan_chk_resume = 0x4000169c;\nr_ble_lll_scan_clean_cur_aux_data = 0x400016a0;\nr_ble_lll_scan_coex_event_cb = 0x400016a4;\nr_ble_lll_scan_common_init = 0x400016a8;\nr_ble_lll_scan_deinit = 0x400016ac;\nr_ble_lll_scan_duration_period_timers_restart = 0x400016b0;\nr_ble_lll_scan_duration_period_timers_stop = 0x400016b4;\nr_ble_lll_scan_duration_timer_cb = 0x400016b8;\nr_ble_lll_scan_event_proc = 0x400016bc;\nr_ble_lll_scan_ext_adv_init = 0x400016c0;\nr_ble_lll_scan_halt = 0x400016c4;\nr_ble_lll_scan_has_sent_scan_req = 0x400016c8;\nr_ble_lll_scan_init = 0x400016cc;\nr_ble_lll_scan_npl_init = 0x400016d0;\nr_ble_lll_scan_npl_reset = 0x400016d4;\nr_ble_lll_scan_npl_restore = 0x400016d8;\nr_ble_lll_scan_npl_store = 0x400016dc;\nr_ble_lll_scan_period_timer_cb = 0x400016e0;\nr_ble_lll_scan_process_adv_in_isr = 0x400016e4;\nr_ble_lll_scan_process_rsp_in_isr = 0x400016e8;\nr_ble_lll_scan_req_backoff = 0x400016ec;\nr_ble_lll_scan_restart = 0x400016f0;\nr_ble_lll_scan_rx_isr_on_aux = 0x400016f4;\nr_ble_lll_scan_rx_isr_on_legacy = 0x400016f8;\nr_ble_lll_scan_rx_pkt_isr = 0x400016fc;\nr_ble_lll_scan_sched_next_aux = 0x40001700;\nr_ble_lll_scan_sched_remove = 0x40001704;\nr_ble_lll_scan_start = 0x40001708;\nr_ble_lll_scan_start_rx = 0x4000170c;\nr_ble_lll_scan_stop = 0x40001710;\nr_ble_lll_scan_targeta_is_matched = 0x40001714;\nr_ble_lll_scan_timer_cb = 0x40001718;\nr_ble_lll_sched_adv_new = 0x4000171c;\nr_ble_lll_sched_adv_resched_pdu = 0x40001720;\nr_ble_lll_sched_adv_reschedule = 0x40001724;\nr_ble_lll_sched_aux_scan = 0x40001728;\nr_ble_lll_sched_conn_overlap = 0x4000172c;\nr_ble_lll_sched_conn_reschedule = 0x40001730;\nr_ble_lll_sched_deinit = 0x40001734;\nr_ble_lll_sched_dtm = 0x40001738;\nr_ble_lll_sched_env_init = 0x4000173c;\nr_ble_lll_sched_execute_check = 0x40001740;\nr_ble_lll_sched_execute_item = 0x40001744;\nr_ble_lll_sched_init = 0x40001748;\nr_ble_lll_sched_insert_if_empty = 0x4000174c;\nr_ble_lll_sched_is_overlap = 0x40001750;\nr_ble_lll_sched_master_new = 0x40001754;\nr_ble_lll_sched_next_time = 0x40001758;\nr_ble_lll_sched_overlaps_current = 0x4000175c;\nr_ble_lll_sched_periodic_adv = 0x40001760;\nr_ble_lll_sched_rmv_elem = 0x40001764;\nr_ble_lll_sched_rmv_elem_type = 0x40001768;\nr_ble_lll_sched_run = 0x4000176c;\nr_ble_lll_sched_scan_req_over_aux_ptr = 0x40001770;\nr_ble_lll_sched_slave_new = 0x40001774;\nr_ble_lll_sched_stop = 0x40001778;\nr_ble_lll_sched_sync = 0x4000177c;\nr_ble_lll_sched_sync_overlaps_current = 0x40001780;\nr_ble_lll_sched_sync_reschedule = 0x40001784;\nr_ble_lll_sync_chain_start_cb = 0x40001788;\nr_ble_lll_sync_coex_dpc_process = 0x4000178c;\nr_ble_lll_sync_coex_dpc_pti_get = 0x40001790;\nr_ble_lll_sync_coex_dpc_update = 0x40001794;\nr_ble_lll_sync_current_sm_over = 0x40001798;\nr_ble_lll_sync_deinit = 0x4000179c;\nr_ble_lll_sync_event_end = 0x400017a0;\nr_ble_lll_sync_event_end_cb = 0x400017a4;\nr_ble_lll_sync_event_start_cb = 0x400017a8;\nr_ble_lll_sync_get_event_end_time = 0x400017ac;\nr_ble_lll_sync_halt = 0x400017b0;\nr_ble_lll_sync_init = 0x400017b4;\nr_ble_lll_sync_new = 0x400017b8;\nr_ble_lll_sync_reset = 0x400017bc;\nr_ble_lll_sync_reset_sm = 0x400017c0;\nr_ble_lll_sync_rmvd_from_sched = 0x400017c4;\nr_ble_lll_sync_rx_pkt_isr = 0x400017c8;\nr_ble_lll_sync_schedule_chain = 0x400017cc;\nr_ble_lll_sync_stop = 0x400017d0;\nr_ble_lll_sync_trnasfer_sched = 0x400017d4;\nr_ble_phy_access_addr_get = 0x400017d8;\nr_ble_phy_calculate_rxtx_ifs = 0x400017dc;\nr_ble_phy_calculate_rxwindow = 0x400017e0;\nr_ble_phy_calculate_txrx_ifs = 0x400017e4;\nr_ble_phy_check_bb_status = 0x400017e8;\nr_ble_phy_complete_rx_info = 0x400017ec;\nr_ble_phy_config_access_addr = 0x400017f0;\nr_ble_phy_data_make = 0x400017f4;\nr_ble_phy_disable = 0x400017f8;\nr_ble_phy_disable_irq = 0x400017fc;\nr_ble_phy_disable_whitening = 0x40001800;\nr_ble_phy_enable_whitening = 0x40001804;\nr_ble_phy_encrypt_disable = 0x40001808;\nr_ble_phy_env_init = 0x4000180c;\nr_ble_phy_get_current_phy = 0x40001810;\nr_ble_phy_get_packet_counter = 0x40001814;\nr_ble_phy_get_packet_status = 0x40001818;\nr_ble_phy_get_pyld_time_offset = 0x4000181c;\nr_ble_phy_get_rx_phy_mode = 0x40001820;\nr_ble_phy_get_seq_end_st = 0x40001824;\nr_ble_phy_init = 0x40001828;\nr_ble_phy_isr = 0x4000182c;\nr_ble_phy_max_data_pdu_pyld = 0x40001830;\nr_ble_phy_mode_config = 0x40001834;\nr_ble_phy_mode_convert = 0x40001838;\nr_ble_phy_mode_write = 0x4000183c;\nr_ble_phy_module_deinit = 0x40001840;\nr_ble_phy_module_init = 0x40001844;\nr_ble_phy_monitor_bb_sync = 0x40001848;\nr_ble_phy_reset_bb_monitor = 0x4000184c;\nr_ble_phy_resolv_list_disable = 0x40001850;\nr_ble_phy_resolv_list_enable = 0x40001854;\nr_ble_phy_restart_sequence = 0x40001858;\nr_ble_phy_rx_set_start_time_forcibly = 0x4000185c;\nr_ble_phy_rxpdu_copy = 0x40001860;\nr_ble_phy_seq_encrypt_enable = 0x40001864;\nr_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001868;\nr_ble_phy_sequence_end_isr = 0x4000186c;\nr_ble_phy_sequence_get_mode = 0x40001870;\nr_ble_phy_sequence_is_running = 0x40001874;\nr_ble_phy_sequence_is_waiting_rsp = 0x40001878;\nr_ble_phy_sequence_single_end = 0x4000187c;\nr_ble_phy_sequence_tx_end_invoke = 0x40001880;\nr_ble_phy_sequence_update_conn_ind_params = 0x40001884;\nr_ble_phy_set_adv_mode = 0x40001888;\nr_ble_phy_set_coex_pti = 0x4000188c;\nr_ble_phy_set_conn_ind_pdu = 0x40001890;\nr_ble_phy_set_conn_mode = 0x40001894;\nr_ble_phy_set_dev_address = 0x40001898;\nr_ble_phy_set_rx_pwr_compensation = 0x4000189c;\nr_ble_phy_set_rxhdr = 0x400018a0;\nr_ble_phy_set_scan_mode = 0x400018a4;\nr_ble_phy_set_sequence_mode = 0x400018a8;\nr_ble_phy_set_single_packet_rx_sequence = 0x400018ac;\nr_ble_phy_set_single_packet_tx_sequence = 0x400018b0;\nr_ble_phy_set_tx_rx_transition = 0x400018b4;\nr_ble_phy_set_txend_cb = 0x400018b8;\nr_ble_phy_setchan = 0x400018bc;\nr_ble_phy_start_rx_immediately = 0x400018c0;\nr_ble_phy_state_get = 0x400018c4;\nr_ble_phy_timer_config_start_time = 0x400018c8;\nr_ble_phy_timer_start_now = 0x400018cc;\nr_ble_phy_timer_stop = 0x400018d0;\nr_ble_phy_tx_set_start_time = 0x400018d4;\nr_ble_phy_txpower_round = 0x400018d8;\nr_ble_phy_txpwr_set = 0x400018dc;\nr_ble_phy_update_conn_sequence = 0x400018e0;\nr_ble_phy_update_encryption = 0x400018e4;\nr_ble_phy_update_ifs = 0x400018e8;\nr_ble_phy_xcvr_state_get = 0x400018ec;\nr_ble_plf_set_log_level = 0x400018f0;\nr_ble_rtc_wake_up_cpu_init = 0x400018f4;\nr_ble_rtc_wake_up_state_clr = 0x400018f8;\nr_ble_vendor_hci_register = 0x400018fc;\nr_bt_rf_coex_cfg_set = 0x40001900;\nr_bt_rf_coex_coded_txrx_time_upper_lim = 0x40001904;\nr_bt_rf_coex_dft_pti_set = 0x40001908;\nr_bt_rf_coex_hook_deinit = 0x4000190c;\nr_bt_rf_coex_hook_init = 0x40001910;\nr_bt_rf_coex_hook_st_set = 0x40001914;\nr_bt_rf_coex_hooks_p_set_default = 0x40001918;\nr_btdm_disable_adv_delay = 0x4000191c;\nr_btdm_switch_phy_coded = 0x40001920;\nr_esp_wait_disabled = 0x40001924;\nr_get_be16 = 0x40001928;\nr_get_be24 = 0x4000192c;\nr_get_be32 = 0x40001930;\nr_get_be64 = 0x40001934;\nr_get_le16 = 0x40001938;\nr_get_le24 = 0x4000193c;\nr_get_le32 = 0x40001940;\nr_get_le64 = 0x40001944;\nr_get_local_irk_offset = 0x40001948;\nr_get_local_rpa_offset = 0x4000194c;\nr_get_max_skip = 0x40001950;\nr_get_peer_id_offset = 0x40001954;\nr_get_peer_irk_offset = 0x40001958;\nr_get_peer_rpa_offset = 0x4000195c;\nr_hal_rtc_intr_init = 0x40001960;\nr_hal_rtc_irq_handler = 0x40001964;\nr_hal_timer_deinit = 0x40001968;\nr_hal_timer_disable_irq = 0x4000196c;\nr_hal_timer_env_init = 0x40001970;\nr_hal_timer_init = 0x40001974;\nr_hal_timer_process = 0x40001978;\nr_hal_timer_read = 0x4000197c;\nr_hal_timer_read_tick = 0x40001980;\nr_hal_timer_set_cb = 0x40001984;\nr_hal_timer_set_exp_tick = 0x40001988;\nr_hal_timer_start = 0x4000198c;\nr_hal_timer_start_at = 0x40001990;\nr_hal_timer_stop = 0x40001994;\nr_hal_timer_task_start = 0x40001998;\nr_ll_assert = 0x4000199c;\nr_mem_init_mbuf_pool = 0x400019a0;\nr_mem_malloc_mbuf_pool = 0x400019a4;\nr_mem_malloc_mbufpkt_pool = 0x400019a8;\nr_mem_malloc_mempool = 0x400019ac;\nr_mem_malloc_mempool_ext = 0x400019b0;\nr_mem_malloc_mempool_gen = 0x400019b4;\nr_mem_pullup_obj = 0x400019b8;\nr_mem_split_frag = 0x400019bc;\nr_os_cputime_get32 = 0x400019c0;\nr_os_cputime_ticks_to_usecs = 0x400019c4;\nr_os_cputime_timer_init = 0x400019c8;\nr_os_cputime_timer_relative = 0x400019cc;\nr_os_cputime_timer_start = 0x400019d0;\nr_os_cputime_timer_stop = 0x400019d4;\nr_os_cputime_usecs_to_ticks = 0x400019d8;\nr_os_mbuf_adj = 0x400019dc;\nr_os_mbuf_append = 0x400019e0;\nr_os_mbuf_appendfrom = 0x400019e4;\nr_os_mbuf_cmpf = 0x400019e8;\nr_os_mbuf_cmpm = 0x400019ec;\nr_os_mbuf_concat = 0x400019f0;\nr_os_mbuf_copydata = 0x400019f4;\nr_os_mbuf_copyinto = 0x400019f8;\nr_os_mbuf_dup = 0x400019fc;\nr_os_mbuf_extend = 0x40001a00;\nr_os_mbuf_free = 0x40001a04;\nr_os_mbuf_free_chain = 0x40001a08;\nr_os_mbuf_get = 0x40001a0c;\nr_os_mbuf_get_pkthdr = 0x40001a10;\nr_os_mbuf_leadingspace = 0x40001a14;\nr_os_mbuf_len = 0x40001a18;\nr_os_mbuf_off = 0x40001a1c;\nr_os_mbuf_pack_chains = 0x40001a20;\nr_os_mbuf_pool_init = 0x40001a24;\nr_os_mbuf_prepend = 0x40001a28;\nr_os_mbuf_prepend_pullup = 0x40001a2c;\nr_os_mbuf_pullup = 0x40001a30;\nr_os_mbuf_trailingspace = 0x40001a34;\nr_os_mbuf_trim_front = 0x40001a38;\nr_os_mbuf_widen = 0x40001a3c;\nr_os_memblock_from = 0x40001a40;\nr_os_memblock_get = 0x40001a44;\nr_os_memblock_put = 0x40001a48;\nr_os_memblock_put_from_cb = 0x40001a4c;\nr_os_mempool_clear = 0x40001a50;\nr_os_mempool_ext_clear = 0x40001a54;\nr_os_mempool_ext_init = 0x40001a58;\nr_os_mempool_info_get_next = 0x40001a5c;\nr_os_mempool_init = 0x40001a60;\nr_os_mempool_init_internal = 0x40001a64;\nr_os_mempool_is_sane = 0x40001a68;\nr_os_mempool_module_init = 0x40001a6c;\nr_os_mempool_unregister = 0x40001a70;\nr_os_mqueue_get = 0x40001a74;\nr_os_mqueue_init = 0x40001a78;\nr_os_mqueue_put = 0x40001a7c;\nr_os_msys_count = 0x40001a80;\nr_os_msys_get = 0x40001a84;\nr_os_msys_get_pkthdr = 0x40001a88;\nr_os_msys_num_free = 0x40001a8c;\nr_os_msys_register = 0x40001a90;\nr_os_msys_reset = 0x40001a94;\nr_pri_phy_valid = 0x40001a98;\nr_put_be16 = 0x40001a9c;\nr_put_be24 = 0x40001aa0;\nr_put_be32 = 0x40001aa4;\nr_put_be64 = 0x40001aa8;\nr_put_le16 = 0x40001aac;\nr_put_le24 = 0x40001ab0;\nr_put_le32 = 0x40001ab4;\nr_put_le64 = 0x40001ab8;\nr_rtc0_timer_handler = 0x40001abc;\nr_sdkconfig_get_opts = 0x40001ac0;\nr_sdkconfig_set_opts = 0x40001ac4;\nr_sec_phy_valid = 0x40001ac8;\nr_swap_buf = 0x40001acc;\nr_swap_in_place = 0x40001ad0;\n\/* Data (.data, .bss, .rodata) *\/\nble_lll_dtm_module_env_p = 0x3fcdffc4;\ng_ble_lll_dtm_prbs15_data = 0x3ff4fee4;\ng_ble_lll_dtm_prbs9_data = 0x3ff4fde4;\ng_channel_rf_to_index = 0x3ff4fdbc;\ng_ble_lll_rfmgmt_data = 0x3fcdff7c;\ng_ble_sleep_enter_cb = 0x3fcdff78;\ng_ble_sleep_exit_cb = 0x3fcdff74;\nble_lll_sched_env_p = 0x3fcdff70;\nble_ll_env_p = 0x3fcdff6c;\ng_ble_ll_pdu_header_tx_time_ro = 0x3ff4fdb4;\nble_ll_adv_env_p = 0x3fcdff68;\nble_ll_conn_env_p = 0x3fcdff64;\nble_ll_conn_required_phy_mask = 0x3ff4fdb0;\nble_ll_valid_conn_phy_mask = 0x3ff4fdaf;\ng_ble_ll_ctrl_pkt_lengths_ro = 0x3ff4fd8c;\nble_ll_hci_env_p = 0x3fcdff60;\ng_debug_le_private_key = 0x3ff4fd6c;\ng_ecc_key = 0x3fcdfefc;\nble_ll_rand_env_p = 0x3fcdfef8;\nble_ll_resolv_env_p = 0x3fcdfef4;\ng_ble_ll_resolve_hdr = 0x3fcdfeec;\ng_device_mode_default = 0x3fcdfe68;\nble_ll_scan_classify_filter_aux_check_cb = 0x3fcdfee8;\nble_ll_scan_classify_filter_check_cb = 0x3fcdfee4;\nble_ll_scan_env_p = 0x3fcdfee0;\ng_ble_ll_supp_cmds_ro = 0x3ff4fd3c;\nble_ll_sync_env_p = 0x3fcdfedc;\ng_ble_sca_ppm_tbl_ro = 0x3ff4fd2c;\npriv_config_opts = 0x3fcdfe48;\nble_hci_uart_reset_cmd = 0x3ff4fd28;\nble_hci_trans_env_p = 0x3fcdfed8;\nble_hci_trans_mode = 0x3fcdfe44;\nble_hci_trans_funcs_ptr = 0x3fcdfed4;\nr_ble_lll_stub_funcs_ptr = 0x3fcdfed0;\nr_ble_stub_funcs_ptr = 0x3fcdfecc;\nr_ext_funcs_p = 0x3fcdfec8;\nr_npl_funcs = 0x3fcdfec4;\nble_hw_env_p = 0x3fcdfec0;\nble_phy_module_env_p = 0x3fcdfebc;\ng_ble_phy_chan_freq_ro = 0x3ff4fd00;\ng_ble_phy_mode_pkt_start_off_ro = 0x3ff4fcf8;\ng_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fce8;\ng_ble_phy_t_rxaddrdelay_ro = 0x3ff4fce4;\ng_ble_phy_t_rxenddelay_ro = 0x3ff4fce0;\ng_ble_phy_t_txdelay_ro = 0x3ff4fcdc;\ng_ble_phy_t_txenddelay_ro = 0x3ff4fcd8;\ng_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcc8;\nhal_timer_env_p = 0x3fcdfeb8;\nr_osi_coex_funcs_p = 0x3fcdfeb4;\nbt_rf_coex_hooks = 0x3fcdfeac;\nbt_rf_coex_hooks_p = 0x3fcdfea8;\ncoex_hook_st_group_tab = 0x3ff4fcbc;\ncoex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcb8;\ns_ble_act_count_by_group = 0x3fcdfea4;\ns_ble_coex_st_map = 0x3fcdfe90;\nbt_rf_coex_cfg_cb = 0x3fcdfe74;\nbt_rf_coex_cfg_p = 0x3fcdfe70;\nbt_rf_coex_cfg_rom = 0x3ff4fc9c;\nbt_rf_coex_pti_dft_p = 0x3fcdfe6c;\nbt_rf_coex_pti_dft_rom = 0x3fcdfe04;\nconn_dynamic_pti_param_rom = 0x3ff4fc84;\nconn_phy_coded_max_data_time_param_rom = 0x3ff4fc80;\next_adv_dynamic_pti_param_rom = 0x3ff4fc4c;\next_scan_dynamic_param_rom = 0x3ff4fc14;\nlegacy_adv_dynamic_pti_param_rom = 0x3ff4fbf4;\nper_adv_dynamic_pti_param_rom = 0x3ff4fbd8;\nsync_dynamic_param_rom = 0x3ff4fbc0;\ng_ble_plf_log_level = 0x3fcdfe00;\ng_msys_pool_list = 0x3fcdfdf8;\ng_os_mempool_list = 0x3fcdfdf0;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x40001ad4;\nRC_GetBlockAckTime = 0x40001ad8;\nebuf_list_remove = 0x40001adc;\nesf_buf_alloc = 0x40001ae0;\nesf_buf_alloc_dynamic = 0x40001ae4;\nesf_buf_recycle = 0x40001ae8;\nGetAccess = 0x40001aec;\nhal_mac_is_low_rate_enabled = 0x40001af0;\nhal_mac_tx_get_blockack = 0x40001af4;\nhal_mac_tx_set_ppdu = 0x40001af8;\nic_get_trc = 0x40001afc;\nic_mac_deinit = 0x40001b00;\nic_mac_init = 0x40001b04;\nic_interface_enabled = 0x40001b08;\nis_lmac_idle = 0x40001b0c;\nlmacAdjustTimestamp = 0x40001b10;\nlmacDiscardAgedMSDU = 0x40001b14;\nlmacDiscardMSDU = 0x40001b18;\nlmacEndFrameExchangeSequence = 0x40001b1c;\nlmacIsIdle = 0x40001b20;\nlmacIsLongFrame = 0x40001b24;\nlmacMSDUAged = 0x40001b28;\nlmacPostTxComplete = 0x40001b2c;\nlmacProcessAllTxTimeout = 0x40001b30;\nlmacProcessCollisions = 0x40001b34;\nlmacProcessRxSucData = 0x40001b38;\nlmacReachLongLimit = 0x40001b3c;\nlmacReachShortLimit = 0x40001b40;\nlmacRecycleMPDU = 0x40001b44;\nlmacRxDone = 0x40001b48;\nlmacSetTxFrame = 0x40001b4c;\nlmacTxDone = 0x40001b50;\nlmacTxFrame = 0x40001b54;\nmac_tx_set_duration = 0x40001b58;\nmac_tx_set_htsig = 0x40001b5c;\nmac_tx_set_plcp0 = 0x40001b60;\nmac_tx_set_plcp1 = 0x40001b64;\nmac_tx_set_plcp2 = 0x40001b68;\npm_check_state = 0x40001b6c;\npm_disable_dream_timer = 0x40001b70;\npm_disable_sleep_delay_timer = 0x40001b74;\npm_dream = 0x40001b78;\npm_mac_wakeup = 0x40001b7c;\npm_mac_sleep = 0x40001b80;\npm_enable_active_timer = 0x40001b84;\npm_enable_sleep_delay_timer = 0x40001b88;\npm_local_tsf_process = 0x40001b8c;\npm_set_beacon_filter = 0x40001b90;\npm_is_in_wifi_slice_threshold = 0x40001b94;\npm_is_waked = 0x40001b98;\npm_keep_alive = 0x40001b9c;\npm_on_beacon_rx = 0x40001ba0;\npm_on_data_rx = 0x40001ba4;\npm_on_tbtt = 0x40001ba8;\npm_parse_beacon = 0x40001bac;\npm_process_tim = 0x40001bb0;\npm_rx_beacon_process = 0x40001bb4;\npm_rx_data_process = 0x40001bb8;\npm_sleep = 0x40001bbc;\npm_sleep_for = 0x40001bc0;\npm_tbtt_process = 0x40001bc4;\nppAMPDU2Normal = 0x40001bc8;\nppAssembleAMPDU = 0x40001bcc;\nppCalFrameTimes = 0x40001bd0;\nppCalSubFrameLength = 0x40001bd4;\nppCalTxAMPDULength = 0x40001bd8;\nppCheckTxAMPDUlength = 0x40001bdc;\nppDequeueRxq_Locked = 0x40001be0;\nppDequeueTxQ = 0x40001be4;\nppEmptyDelimiterLength = 0x40001be8;\nppEnqueueRxq = 0x40001bec;\nppEnqueueTxDone = 0x40001bf0;\nppGetTxQFirstAvail_Locked = 0x40001bf4;\nppGetTxframe = 0x40001bf8;\nppMapTxQueue = 0x40001bfc;\nppProcTxSecFrame = 0x40001c00;\nppProcessRxPktHdr = 0x40001c04;\nppProcessTxQ = 0x40001c08;\nppRecordBarRRC = 0x40001c0c;\nlmacRequestTxopQueue = 0x40001c10;\nlmacReleaseTxopQueue = 0x40001c14;\nppRecycleAmpdu = 0x40001c18;\nppRecycleRxPkt = 0x40001c1c;\nppResortTxAMPDU = 0x40001c20;\nppResumeTxAMPDU = 0x40001c24;\nppRxFragmentProc = 0x40001c28;\nppRxPkt = 0x40001c2c;\nppRxProtoProc = 0x40001c30;\nppSearchTxQueue = 0x40001c34;\nppSearchTxframe = 0x40001c38;\nppSelectNextQueue = 0x40001c3c;\nppSubFromAMPDU = 0x40001c40;\nppTask = 0x40001c44;\nppTxPkt = 0x40001c48;\nppTxProtoProc = 0x40001c4c;\nppTxqUpdateBitmap = 0x40001c50;\npp_coex_tx_request = 0x40001c54;\npp_hdrsize = 0x40001c58;\npp_post = 0x40001c5c;\npp_process_hmac_waiting_txq = 0x40001c60;\nrcGetAmpduSched = 0x40001c64;\nrcUpdateRxDone = 0x40001c68;\nrc_get_trc = 0x40001c6c;\nrc_get_trc_by_index = 0x40001c70;\nrcAmpduLowerRate = 0x40001c74;\nrcampduuprate = 0x40001c78;\nrcClearCurAMPDUSched = 0x40001c7c;\nrcClearCurSched = 0x40001c80;\nrcClearCurStat = 0x40001c84;\nrcGetSched = 0x40001c88;\nrcLowerSched = 0x40001c8c;\nrcSetTxAmpduLimit = 0x40001c90;\nrcTxUpdatePer = 0x40001c94;\nrcUpdateAckSnr = 0x40001c98;\nrcUpdateRate = 0x40001c9c;\nrcUpdateTxDone = 0x40001ca0;\nrcUpdateTxDoneAmpdu2 = 0x40001ca4;\nrcUpSched = 0x40001ca8;\nrssi_margin = 0x40001cac;\nrx11NRate2AMPDULimit = 0x40001cb0;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001cb4;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001cb8;\ntrc_calc_duration = 0x40001cbc;\ntrc_isTxAmpduOperational = 0x40001cc0;\ntrc_onAmpduOp = 0x40001cc4;\nTRC_PER_IS_GOOD = 0x40001cc8;\ntrc_SetTxAmpduState = 0x40001ccc;\ntrc_tid_isTxAmpduOperational = 0x40001cd0;\ntrcAmpduSetState = 0x40001cd4;\nwDevCheckBlockError = 0x40001cd8;\nwDev_AppendRxBlocks = 0x40001cdc;\nwDev_DiscardFrame = 0x40001ce0;\nwDev_GetNoiseFloor = 0x40001ce4;\nwDev_IndicateAmpdu = 0x40001ce8;\nwDev_IndicateFrame = 0x40001cec;\nwdev_mac_reg_load = 0x40001cf0;\nwdev_mac_reg_store = 0x40001cf4;\nwdev_mac_special_reg_load = 0x40001cf8;\nwdev_mac_special_reg_store = 0x40001cfc;\nwdev_mac_wakeup = 0x40001d00;\nwdev_mac_sleep = 0x40001d04;\nwDev_ProcessFiq = 0x40001d08;\nwDev_ProcessRxSucData = 0x40001d0c;\nwdevProcessRxSucDataAll = 0x40001d10;\nwdev_csi_len_align = 0x40001d14;\nppDequeueTxDone_Locked = 0x40001d18;\nppProcTxDone = 0x40001d1c;\npm_tx_data_done_process = 0x40001d20;\nconfig_is_cache_tx_buf_enabled = 0x40001d24;\nppMapWaitTxq = 0x40001d28;\nppProcessWaitingQueue = 0x40001d2c;\nppDisableQueue = 0x40001d30;\npm_allow_tx = 0x40001d34;\nwdev_is_data_in_rxlist = 0x40001d38;\nppProcTxCallback = 0x40001d3c;\npm_is_open = 0x40001d40;\npm_wake_up = 0x40001d44;\npm_wake_done = 0x40001d48;\npm_disable_disconnected_sleep_delay_timer = 0x40001d4c;\npm_enable_disconnected_sleep_delay_timer = 0x40001d50;\nhal_mac_get_txq_state = 0x40001d54;\nhal_mac_clr_txq_state = 0x40001d58;\nhal_mac_tx_set_cca = 0x40001d5c;\nhal_mac_set_txq_invalid = 0x40001d60;\nhal_mac_txq_disable = 0x40001d64;\nhal_mac_is_txq_enabled = 0x40001d68;\nhal_mac_get_txq_pmd = 0x40001d6c;\nlmacDiscardFrameExchangeSequence = 0x40001d70;\nlmacDisableTransmit = 0x40001d74;\nlmacProcessTxTimeout = 0x40001d78;\nlmacProcessTxSuccess = 0x40001d7c;\nlmacProcessCollision = 0x40001d80;\nlmacProcessTxRtsError = 0x40001d84;\nlmacProcessCtsTimeout = 0x40001d88;\nlmacProcessTxComplete = 0x40001d8c;\nlmacProcessAckTimeout = 0x40001d90;\nlmacProcessTxError = 0x40001d94;\nlmacProcessTxseckiderr = 0x40001d98;\nrcReachRetryLimit = 0x40001d9c;\nlmacProcessShortRetryFail = 0x40001da0;\nlmacEndRetryAMPDUFail = 0x40001da4;\nppFillAMPDUBar = 0x40001da8;\nrcGetRate = 0x40001dac;\nppReSendBar = 0x40001db0;\nlmacProcessLongRetryFail = 0x40001db4;\nlmacRetryTxFrame = 0x40001db8;\nlmacProcessCollisions_task = 0x40001dbc;\nlmacProcessTxopQComplete = 0x40001dc0;\nlmacInitAc = 0x40001dc4;\nlmacInit = 0x40001dc8;\nmac_tx_set_txop_q = 0x40001dcc;\nhal_init = 0x40001dd0;\nhal_mac_rx_set_policy = 0x40001dd4;\nhal_mac_set_bssid = 0x40001dd8;\nmac_rx_policy_init = 0x40001ddc;\nmac_txrx_init = 0x40001de0;\nmac_rxbuf_init = 0x40001de4;\nmac_last_rxbuf_init = 0x40001de8;\nhal_attenna_init = 0x40001dec;\nhal_timer_update_by_rtc = 0x40001df0;\nhal_coex_pti_init = 0x40001df4;\nlmac_stop_hw_txq = 0x40001df8;\nppDirectRecycleAmpdu = 0x40001dfc;\nesp_wifi_internal_set_rts = 0x40001e00;\nesp_wifi_internal_get_rts = 0x40001e04;\nppTxFragmentProc = 0x40001e08;\nesf_buf_setup = 0x40001e0c;\nhal_agreement_add_rx_ba = 0x40001e10;\nhal_agreement_del_rx_ba = 0x40001e14;\nhal_crypto_set_key_entry = 0x40001e18;\nhal_crypto_get_key_entry = 0x40001e1c;\nhal_crypto_clr_key_entry = 0x40001e20;\nconfig_get_wifi_task_stack_size = 0x40001e24;\npp_create_task = 0x40001e28;\nhal_set_sta_tsf_wakeup = 0x40001e2c;\nhal_set_rx_beacon_pti = 0x40001e30;\npm_start = 0x40001e34;\npm_stop = 0x40001e38;\nhal_disable_sta_tbtt = 0x40001e3c;\nppCalTxopDur = 0x40001e40;\nwDev_IndicateCtrlFrame = 0x40001e44;\nhal_enable_sta_tbtt = 0x40001e48;\nhal_set_sta_tbtt = 0x40001e4c;\npm_update_next_tbtt = 0x40001e50;\npm_set_sleep_type = 0x40001e54;\nwDev_Rxbuf_Init = 0x40001e58;\nwDev_Rxbuf_Deinit = 0x40001e5c;\nppCalTkipMic = 0x40001e60;\nwDev_SnifferRxData = 0x40001e64;\nhal_crypto_enable = 0x40001e68;\nhal_crypto_disable = 0x40001e6c;\nwDev_Insert_KeyEntry = 0x40001e70;\nwDev_remove_KeyEntry = 0x40001e74;\nrc_enable_trc = 0x40001e78;\nrc_set_per_conn_fix_rate = 0x40001e7c;\nwdev_csi_rx_process = 0x40001e80;\nwDev_SnifferRxAmpdu = 0x40001e84;\nhal_mac_tsf_reset = 0x40001e88;\ndbg_lmac_statis_dump = 0x40001e8c;\ndbg_lmac_rxtx_statis_dump = 0x40001e90;\ndbg_lmac_hw_statis_dump = 0x40001e94;\ndbg_lmac_diag_statis_dump = 0x40001e98;\ndbg_lmac_ps_statis_dump = 0x40001e9c;\npp_timer_do_process = 0x40001ea0;\nrcUpdateAMPDUParam = 0x40001ea4;\nrcUpdatePhyMode = 0x40001ea8;\nrcGetHighestRateIdx = 0x40001eac;\npm_tx_null_data_done_process = 0x40001eb0;\npm_tx_data_process = 0x40001eb4;\npm_attach = 0x40001eb8;\npm_coex_schm_process = 0x40001ebc;\nppInitTxq = 0x40001ec0;\npp_attach = 0x40001ec4;\npp_deattach = 0x40001ec8;\npm_on_probe_resp_rx = 0x40001ecc;\nhal_set_sta_tsf = 0x40001ed0;\nic_update_sta_tsf = 0x40001ed4;\nic_tx_pkt = 0x40001ed8;\npm_send_probe_stop = 0x40001edc;\npm_send_probe_start = 0x40001ee0;\npm_on_coex_schm_process_restart = 0x40001ee4;\nhal_mac_set_rxq_policy = 0x40001ee8;\nhal_sniffer_enable = 0x40001eec;\nhal_sniffer_disable = 0x40001ef0;\nhal_sniffer_rx_set_promis = 0x40001ef4;\nhal_sniffer_rx_clr_statistics = 0x40001ef8;\nhal_sniffer_set_promis_misc_pkt = 0x40001efc;\ntsf_hal_set_tsf_enable = 0x40001f00;\ntsf_hal_set_tsf_disable = 0x40001f04;\ntsf_hal_is_tsf_enabled = 0x40001f08;\ntsf_hal_set_modem_wakeup_early_time = 0x40001f0c;\ntsf_hal_get_counter_value = 0x40001f10;\ntsf_hal_set_counter_value = 0x40001f14;\ntsf_hal_get_time = 0x40001f18;\ntsf_hal_set_time = 0x40001f1c;\ntsf_hal_set_tbtt_enable = 0x40001f20;\ntsf_hal_set_tbtt_disable = 0x40001f24;\ntsf_hal_set_tbtt_intr_enable = 0x40001f28;\ntsf_hal_set_tbtt_intr_disable = 0x40001f2c;\ntsf_hal_set_tbtt_soc_wakeup_enable = 0x40001f30;\ntsf_hal_set_tbtt_soc_wakeup_disable = 0x40001f34;\ntsf_hal_set_tbtt_start_time = 0x40001f38;\ntsf_hal_set_tbtt_early_time = 0x40001f3c;\ntsf_hal_set_tbtt_interval = 0x40001f40;\ntsf_hal_get_tbtt_interval = 0x40001f44;\ntsf_hal_set_timer_enable = 0x40001f48;\ntsf_hal_set_timer_disable = 0x40001f4c;\ntsf_hal_set_timer_target = 0x40001f50;\ntsf_hal_get_timer_target = 0x40001f54;\ntsf_hal_set_timer_intr_enable = 0x40001f58;\ntsf_hal_set_timer_intr_disable = 0x40001f5c;\ntsf_hal_set_timer_soc_wakeup_enable = 0x40001f60;\ntsf_hal_set_timer_soc_wakeup_disable = 0x40001f64;\npm_disconnected_wake = 0x40001f68;\npm_get_connectionless_status = 0x40001f6c;\npm_update_by_connectionless_status = 0x40001f70;\npm_connectionless_wake_interval_timeout_process = 0x40001f74;\npm_connectionless_wake_window_timeout_process = 0x40001f78;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff4fbbc;\npTxRx = 0x3fcdfdec;\nlmacConfMib_ptr = 0x3fcdfde8;\nour_wait_eb = 0x3fcdfde4;\nour_tx_eb = 0x3fcdfde0;\npp_wdev_funcs = 0x3fcdfddc;\ng_osi_funcs_p = 0x3fcdfdd8;\nwDevCtrl_ptr = 0x3fcdfdd4;\ng_wdev_last_desc_reset_ptr = 0x3ff4fbb8;\nwDevMacSleep_ptr = 0x3fcdfdd0;\ng_lmac_cnt_ptr = 0x3fcdfdcc;\nour_controls_ptr = 0x3ff4fbb4;\npp_sig_cnt_ptr = 0x3fcdfdc8;\ng_eb_list_desc_ptr = 0x3fcdfdc4;\ns_fragment_ptr = 0x3fcdfdc0;\nif_ctrl_ptr = 0x3fcdfdbc;\ng_intr_lock_mux = 0x3fcdfdb8;\ng_wifi_global_lock = 0x3fcdfdb4;\ns_wifi_queue = 0x3fcdfdb0;\npp_task_hdl = 0x3fcdfdac;\ns_pp_task_create_sem = 0x3fcdfda8;\ns_pp_task_del_sem = 0x3fcdfda4;\ng_wifi_menuconfig_ptr = 0x3fcdfda0;\nxphyQueue = 0x3fcdfd9c;\nap_no_lr_ptr = 0x3fcdfd98;\nrc11BSchedTbl_ptr = 0x3fcdfd94;\nrc11NSchedTbl_ptr = 0x3fcdfd90;\nrcLoRaSchedTbl_ptr = 0x3fcdfd8c;\nBasicOFDMSched_ptr = 0x3fcdfd88;\ntrc_ctl_ptr = 0x3fcdfd84;\ng_pm_cnt_ptr = 0x3fcdfd80;\ng_pm_ptr = 0x3fcdfd7c;\ng_pm_cfg_ptr = 0x3fcdfd78;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdfd74;\ng_txop_queue_status_ptr = 0x3fcdfd70;\ng_mac_sleep_en_ptr = 0x3fcdfd6c;\ng_mesh_is_root_ptr = 0x3fcdfd68;\ng_mesh_topology_ptr = 0x3fcdfd64;\ng_mesh_init_ps_type_ptr = 0x3fcdfd60;\ng_mesh_is_started_ptr = 0x3fcdfd5c;\ng_config_func = 0x3fcdfd58;\ng_net80211_tx_func = 0x3fcdfd54;\ng_timer_func = 0x3fcdfd50;\ns_michael_mic_failure_cb = 0x3fcdfd4c;\nwifi_sta_rx_probe_req = 0x3fcdfd48;\ng_tx_done_cb_func = 0x3fcdfd44;\ng_per_conn_trc = 0x3fcdfd28;\ns_encap_amsdu_func = 0x3fcdfd24;\nbars = 0x3fcdfc84;\neb_txdesc_space = 0x3fcdfbf4;\neb_space = 0x3fcdfb54;\ng_pd_mac_in_light_sleep = 0x3fcdfb50;\ns_fix_rate_mask = 0x3fcdfb4c;\ns_fix_rate = 0x3fcdfb44;\ng_wdev_csi_rx = 0x3fcdfb40;\ng_wdev_csi_rx_ctx = 0x3fcdfb3c;\nBcnSendTick = 0x3fcdfb38;\ng_pp_timer_info_ptr = 0x3fcdfb34;\nrcP2P11NSchedTbl_ptr = 0x3fcdfb30;\nrcP2P11GSchedTbl_ptr = 0x3fcdfb2c;\nrc11GSchedTbl_ptr = 0x3fcdfb28;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001f7c;\nampdu_dispatch = 0x40001f80;\nampdu_dispatch_all = 0x40001f84;\nampdu_dispatch_as_many_as_possible = 0x40001f88;\nampdu_dispatch_movement = 0x40001f8c;\nampdu_dispatch_upto = 0x40001f90;\nchm_is_at_home_channel = 0x40001f94;\ncnx_node_is_existing = 0x40001f98;\ncnx_node_search = 0x40001f9c;\nic_ebuf_recycle_rx = 0x40001fa0;\nic_ebuf_recycle_tx = 0x40001fa4;\nic_reset_rx_ba = 0x40001fa8;\nieee80211_align_eb = 0x40001fac;\nieee80211_ampdu_reorder = 0x40001fb0;\nieee80211_ampdu_start_age_timer = 0x40001fb4;\nieee80211_encap_esfbuf = 0x40001fb8;\nieee80211_is_tx_allowed = 0x40001fbc;\nieee80211_output_pending_eb = 0x40001fc0;\nieee80211_output_process = 0x40001fc4;\nieee80211_set_tx_desc = 0x40001fc8;\nsta_input = 0x40001fcc;\nwifi_get_macaddr = 0x40001fd0;\nwifi_rf_phy_disable = 0x40001fd4;\nwifi_rf_phy_enable = 0x40001fd8;\nic_ebuf_alloc = 0x40001fdc;\nieee80211_classify = 0x40001fe0;\nieee80211_copy_eb_header = 0x40001fe4;\nieee80211_recycle_cache_eb = 0x40001fe8;\nieee80211_search_node = 0x40001fec;\nroundup2 = 0x40001ff0;\nieee80211_crypto_encap = 0x40001ff4;\nieee80211_crypto_decap = 0x40001ff8;\nieee80211_decap = 0x40001ffc;\nieee80211_set_tx_pti = 0x40002000;\nwifi_is_started = 0x40002004;\nieee80211_gettid = 0x40002008;\nieee80211_ccmp_decrypt = 0x4000200c;\nieee80211_ccmp_encrypt = 0x40002010;\nccmp_encap = 0x40002014;\nccmp_decap = 0x40002018;\ntkip_encap = 0x4000201c;\ntkip_decap = 0x40002020;\nwep_encap = 0x40002024;\nwep_decap = 0x40002028;\ndbg_hmac_rxtx_statis_dump = 0x4000202c;\ndbg_hmac_statis_dump = 0x40002030;\nieee80211_send_action_vendor_spec = 0x40002034;\nieee80211_send_mgmt = 0x40002038;\nieee80211_deauth_construct = 0x40002040;\nieee80211_disassoc_construct = 0x40002044;\nieee80211_vnd_lora_ie_size = 0x40002048;\nieee80211_vnd_ie_size = 0x4000204c;\nieee80211_add_ssid = 0x40002050;\nieee80211_add_rates = 0x40002054;\nieee80211_add_xrates = 0x40002058;\nieee80211_is_ht_cipher = 0x4000205c;\nieee80211_assoc_req_construct = 0x40002060;\nieee80211_assoc_resp_construct = 0x40002064;\nieee80211_setup_lr_rates = 0x40002068;\nieee80211_ht_node_init = 0x4000206c;\nieee80211_is_support_rate = 0x40002070;\nieee80211_setup_rates = 0x40002074;\nieee80211_is_lr_only = 0x40002078;\nieee80211_setup_phy_mode = 0x4000207c;\nieee80211_sta_is_connected = 0x40002080;\ncurrent_task_is_wifi_task = 0x40002084;\nwifi_get_init_state = 0x40002088;\nieee80211_timer_process = 0x4000208c;\ncnx_coexist_timeout = 0x40002090;\nsta_recv_mgmt = 0x40002094;\nieee80211_send_setup = 0x40002098;\nieee80211_send_probereq = 0x4000209c;\nsta_auth_shared = 0x400020a4;\nsta_auth_sae = 0x400020a8;\ncnx_coexist_timeout_process = 0x400020ac;\nieee80211_alloc_challenge = 0x400020b0;\ncnx_assoc_timeout = 0x400020b4;\nieee80211_vnd_ie_set = 0x400020b8;\nieee80211_vnd_lora_ie_set = 0x400020bc;\nieee80211_add_wme_param = 0x400020c0;\nieee80211_add_dsparams = 0x400020c4;\nieee80211_add_csa = 0x400020c8;\nieee80211_add_extcap = 0x400020cc;\nieee80211_regdomain_get_country = 0x400020d0;\nieee80211_add_countryie = 0x400020d4;\nieee80211_amsdu_adjust_head = 0x400020dc;\nieee80211_amsdu_adjust_last_length = 0x400020e0;\nieee80211_amsdu_send_check = 0x400020e4;\nieee80211_amsdu_encap_check = 0x400020e8;\nieee80211_amsdu_length_check = 0x400020ec;\nieee80211_encap_amsdu = 0x400020f0;\nieee80211_output_raw_process = 0x400020f4;\nesp_wifi_80211_tx = 0x400020f8;\nieee80211_raw_frame_sanity_check = 0x400020fc;\nieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;\nieee80211_crypto_aes_128_cmac_decrypt = 0x40002104;\nieee80211_alloc_tx_buf = 0x40002108;\nieee80211_output_do = 0x4000210c;\nieee80211_send_nulldata = 0x40002110;\nieee80211_setup_robust_mgmtframe = 0x40002114;\nieee80211_mgmt_output = 0x40002118;\nieee80211_encap_null_data = 0x4000211c;\nieee80211_send_deauth = 0x40002120;\nieee80211_alloc_deauth = 0x40002124;\nieee80211_send_proberesp = 0x40002128;\nieee80211_tx_mgt_cb = 0x4000212c;\nieee80211_getcapinfo = 0x40002130;\nsta_rx_csa = 0x40002134;\nsta_send_sa_query_req = 0x40002138;\nsta_send_sa_query_resp = 0x4000213c;\nsta_recv_sa_query_req = 0x40002140;\nsta_recv_sa_query_resp = 0x40002144;\nieee80211_parse_beacon = 0x40002148;\nieee80211_set_max_rate = 0x4000214c;\nic_set_sta = 0x40002150;\nieee80211_match_security = 0x40002154;\nieee80211_parse_wpa = 0x40002158;\nieee80211_add_assoc_req_ies = 0x40002160;\nieee80211_add_probe_req_ies = 0x40002164;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdfb24;\ng_scan = 0x3fcdfb20;\ng_chm = 0x3fcdfb1c;\ng_ic_ptr = 0x3fcdfb18;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_tx_cacheq_ptr = 0x3fcdfb14;\ns_netstack_free = 0x3fcdfb10;\nmesh_rxcb = 0x3fcdfb0c;\nsta_rxcb = 0x3fcdfb08;\nccmp_ptr = 0x3fcdfb04;\ns_wifi_nvs_ptr = 0x3fcdfb00;\ntkip_ptr = 0x3fcdfafc;\nwep_ptr = 0x3fcdfaf8;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_misc_nvs = 0x3fcdfaf0;\ns_wifi_init_state = 0x3fcdfac0;\ns_wifi_task_hdl = 0x3fcdfaec;\nin_rssi_adjust = 0x3fcdfae8;\nrssi_saved = 0x3fcdfae0;\nrssi_index = 0x3fcdfadc;\ns_sa_query_retries = 0x3fcdfad8;\ns_sa_query_success = 0x3fcdfad5;\ng_sta_connected_flag = 0x3fcdfad4;\nwpa_crypto_funcs_ptr = 0x3fcdfad0;\ns_netstack_ref = 0x3fcdfacc;\nsta_csa_timer_ptr = 0x3fcdfac8;\ns_trans_id = 0x3fcdfac4;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x40002168;\ncoex_bt_release = 0x4000216c;\ncoex_bt_request = 0x40002170;\ncoex_core_ble_conn_dyn_prio_get = 0x40002174;\ncoex_core_event_duration_get = 0x40002178;\ncoex_core_pti_get = 0x4000217c;\ncoex_core_release = 0x40002180;\ncoex_core_request = 0x40002184;\ncoex_core_status_get = 0x40002188;\ncoex_core_timer_idx_get = 0x4000218c;\ncoex_event_duration_get = 0x40002190;\ncoex_hw_timer_disable = 0x40002194;\ncoex_hw_timer_enable = 0x40002198;\ncoex_hw_timer_set = 0x4000219c;\ncoex_schm_interval_set = 0x400021a0;\ncoex_schm_lock = 0x400021a4;\ncoex_schm_unlock = 0x400021a8;\ncoex_status_get = 0x400021ac;\ncoex_wifi_release = 0x400021b0;\nesp_coex_ble_conn_dynamic_prio_get = 0x400021b4;\ncoex_hw_timer_tick_get = 0x400021b8;\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdfabc;\ncoex_pti_tab_ptr = 0x3fcdfab8;\ncoex_schm_env_ptr = 0x3fcdfab4;\ncoexist_funcs = 0x3fcdfab0;\ng_coa_funcs_p = 0x3fcdfaac;\ng_coex_param_ptr = 0x3fcdfaa8;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_param_addr = 0x400021bc;\nphy_get_romfuncs = 0x400021c0;\nchip729_phyrom_version = 0x400021c4;\nchip729_phyrom_version_num = 0x400021c8;\nrom_get_rc_dout = 0x400021cc;\nrc_cal = 0x400021d0;\nphy_analog_delay_cal = 0x400021d4;\nphy_rx_rifs_en = 0x400021d8;\nphy_current_level_set = 0x400021dc;\nphy_bbpll_en_usb = 0x400021e0;\nphy_bt_power_track = 0x400021e4;\nphy_xpd_tsens = 0x400021e8;\nbb_wdt_rst_enable = 0x400021ec;\nbb_wdt_int_enable = 0x400021f0;\nbb_wdt_timeout_clear = 0x400021f4;\nbb_wdt_get_status = 0x400021f8;\nrom_enter_critical_phy = 0x400021fc;\nrom_exit_critical_phy = 0x40002200;\nrom_bb_bss_cbw40 = 0x40002204;\nrom_set_chan_reg = 0x40002208;\nabs_temp = 0x4000220c;\nset_chan_cal_interp = 0x40002210;\nloopback_mode_en = 0x40002214;\nget_data_sat = 0x40002218;\nphy_byte_to_word = 0x4000221c;\nphy_get_rx_freq = 0x40002220;\ni2c_master_reset = 0x40002224;\nchan14_mic_enable = 0x40002228;\nchan14_mic_cfg = 0x4000222c;\nset_adc_rand = 0x40002230;\nphy_set_most_tpw = 0x40002234;\nphy_get_most_tpw = 0x40002238;\nesp_tx_state_out = 0x4000223c;\nphy_get_adc_rand = 0x40002240;\nphy_internal_delay = 0x40002244;\nphy_ftm_comp = 0x40002248;\nphy_11p_set = 0x4000224c;\nphy_freq_mem_backup = 0x40002250;\nant_dft_cfg = 0x40002254;\nant_wifitx_cfg = 0x40002258;\nant_wifirx_cfg = 0x4000225c;\nant_bttx_cfg = 0x40002260;\nant_btrx_cfg = 0x40002264;\nphy_chan_dump_cfg = 0x40002268;\nphy_enable_low_rate = 0x4000226c;\nphy_disable_low_rate = 0x40002270;\nphy_dig_reg_backup = 0x40002274;\nphy_chan_filt_set = 0x40002278;\nphy_rx11blr_cfg = 0x4000227c;\nset_cca = 0x40002280;\nset_rx_sense = 0x40002284;\nrx_gain_force = 0x40002288;\nrom_phy_en_hw_set_freq = 0x4000228c;\nrom_phy_dis_hw_set_freq = 0x40002290;\nwr_rf_freq_mem = 0x40002294;\nfreq_i2c_write_set = 0x40002298;\nwrite_pll_cap_mem = 0x4000229c;\npll_dac_mem_update = 0x400022a0;\npll_cap_mem_update = 0x400022a4;\nget_rf_freq_cap = 0x400022a8;\nget_rf_freq_init = 0x400022ac;\nfreq_get_i2c_data = 0x400022b0;\nfreq_i2c_data_write = 0x400022b4;\nset_chan_freq_hw_init = 0x400022b8;\nset_chan_freq_sw_start = 0x400022bc;\nrom_get_i2c_read_mask = 0x400022c0;\nrom_get_i2c_mst0_mask = 0x400022c4;\nrom_get_i2c_hostid = 0x400022c8;\nrom_chip_i2c_readReg_org = 0x400022cc;\nrom_chip_i2c_readReg = 0x400022d0;\nrom_i2c_paral_set_mst0 = 0x400022d4;\nrom_i2c_paral_set_read = 0x400022d8;\nrom_i2c_paral_read = 0x400022dc;\nrom_i2c_paral_write = 0x400022e0;\nrom_i2c_paral_write_num = 0x400022e4;\nrom_i2c_paral_write_mask = 0x400022e8;\nrom_i2c_readReg = 0x400022ec;\nrom_chip_i2c_writeReg = 0x400022f0;\nrom_i2c_writeReg = 0x400022f4;\nrom_i2c_readReg_Mask = 0x400022f8;\nrom_i2c_writeReg_Mask = 0x400022fc;\nrom_set_txcap_reg = 0x40002300;\ni2c_sar2_init_code = 0x40002304;\nphy_i2c_init1 = 0x40002308;\nphy_i2c_init2 = 0x4000230c;\nphy_get_i2c_data = 0x40002310;\nbias_reg_set = 0x40002314;\ni2c_rc_cal_set = 0x40002318;\ni2c_bbpll_set = 0x4000231c;\nrom_phy_xpd_rf = 0x40002320;\nphy_wakeup_init_rom = 0x40002324;\nregister_chipv7_phy_init_param = 0x40002328;\nphy_reg_init = 0x4000232c;\nphy_close_rf_rom = 0x40002330;\nrom_pbus_force_mode = 0x40002334;\nrom_pbus_rd_addr = 0x40002338;\nrom_pbus_rd_shift = 0x4000233c;\nrom_pbus_force_test = 0x40002340;\nrom_pbus_rd = 0x40002344;\nrom_pbus_debugmode = 0x40002348;\nrom_pbus_workmode = 0x4000234c;\nrom_pbus_set_rxgain = 0x40002350;\nrom_pbus_xpd_rx_off = 0x40002354;\nrom_pbus_xpd_rx_on = 0x40002358;\nrom_pbus_xpd_tx_off = 0x4000235c;\nrom_pbus_xpd_tx_on = 0x40002360;\nrom_pbus_set_dco = 0x40002364;\nrom_set_loopback_gain = 0x40002368;\nrom_txcal_debuge_mode = 0x4000236c;\nrom_txcal_work_mode = 0x40002370;\nset_pbus_mem = 0x40002374;\nrom_pwdet_sar2_init = 0x40002378;\nrom_en_pwdet = 0x4000237c;\nrom_get_sar_sig_ref = 0x40002380;\nrom_pwdet_tone_start = 0x40002384;\nrom_get_tone_sar_dout = 0x40002388;\nrom_get_fm_sar_dout = 0x4000238c;\nrom_txtone_linear_pwr = 0x40002390;\nrom_get_power_db = 0x40002394;\nrom_meas_tone_pwr_db = 0x40002398;\nrom_pkdet_vol_start = 0x4000239c;\nrom_read_sar_dout = 0x400023a0;\nrom_read_sar2_code = 0x400023a4;\nrom_get_sar2_vol = 0x400023a8;\nrom_get_pll_vol = 0x400023ac;\nrom_tx_pwctrl_bg_init = 0x400023b0;\nrom_phy_pwdet_always_en = 0x400023b4;\nrom_phy_pwdet_onetime_en = 0x400023b8;\nlinear_to_db = 0x400023bc;\nrom_disable_agc = 0x400023c0;\nrom_enable_agc = 0x400023c4;\nrom_disable_wifi_agc = 0x400023c8;\nrom_enable_wifi_agc = 0x400023cc;\nrom_write_gain_mem = 0x400023d0;\nrom_bb_bss_cbw40_dig = 0x400023d4;\nrom_cbw2040_cfg = 0x400023d8;\nrom_mac_tx_chan_offset = 0x400023dc;\nrom_tx_paon_set = 0x400023e0;\nrom_i2cmst_reg_init = 0x400023e4;\nrom_bt_gain_offset = 0x400023e8;\nrom_fe_reg_init = 0x400023ec;\nrom_mac_enable_bb = 0x400023f0;\nrom_bb_wdg_cfg = 0x400023f4;\nrom_fe_txrx_reset = 0x400023f8;\nrom_set_rx_comp = 0x400023fc;\nrom_write_chan_freq = 0x40002400;\nrom_agc_reg_init = 0x40002404;\nrom_bb_reg_init = 0x40002408;\nrom_write_txrate_power_offset = 0x4000240c;\nrom_open_i2c_xpd = 0x40002410;\nrom_txiq_set_reg = 0x40002414;\nrom_rxiq_set_reg = 0x40002418;\nrom_phy_bbpll_cal = 0x4000241c;\nphy_disable_cca = 0x40002420;\nphy_enable_cca = 0x40002424;\nforce_txon = 0x40002428;\nset_txclk_en = 0x4000242c;\nset_rxclk_en = 0x40002430;\nstart_tx_tone_step = 0x40002434;\nstop_tx_tone = 0x40002438;\nbb_wdg_test_en = 0x4000243c;\nnoise_floor_auto_set = 0x40002440;\nread_hw_noisefloor = 0x40002444;\niq_corr_enable = 0x40002448;\nbt_tx_dig_gain = 0x4000244c;\nwifi_tx_dig_reg = 0x40002450;\nwifi_agc_sat_gain = 0x40002454;\nphy_ant_init = 0x40002458;\nphy_set_bbfreq_init = 0x4000245c;\nwifi_fbw_sel = 0x40002460;\nphy_rx_sense_set = 0x40002464;\ntx_state_set = 0x40002468;\nphy_close_pa = 0x4000246c;\nbt_filter_reg = 0x40002470;\nphy_freq_correct = 0x40002474;\nset_pbus_reg = 0x40002478;\nwifi_rifs_mode_en = 0x4000247c;\nrfagc_disable = 0x40002480;\nrom_restart_cal = 0x40002484;\nrom_write_rfpll_sdm = 0x40002488;\nrom_wait_rfpll_cal_end = 0x4000248c;\nrom_rfpll_set_freq = 0x40002490;\nrom_rfpll_cap_init_cal = 0x40002494;\nrom_set_rfpll_freq = 0x40002498;\nrom_write_pll_cap = 0x4000249c;\nrom_read_pll_cap = 0x400024a0;\nmhz2ieee = 0x400024a4;\nchan_to_freq = 0x400024a8;\nset_rf_freq_offset = 0x400024ac;\nset_channel_rfpll_freq = 0x400024b0;\nrfpll_cap_correct = 0x400024b4;\nphy_set_freq = 0x400024b8;\ncorrect_rfpll_offset = 0x400024bc;\npll_vol_cal = 0x400024c0;\nchip_v7_set_chan_misc = 0x400024c4;\nchip_v7_set_chan = 0x400024c8;\nchip_v7_set_chan_offset = 0x400024cc;\nchip_v7_set_chan_ana = 0x400024d0;\nset_chanfreq = 0x400024d4;\nrom_rxiq_cover_mg_mp = 0x400024d8;\nrom_rfcal_rxiq = 0x400024dc;\nrom_get_rfcal_rxiq_data = 0x400024e0;\nrom_pbus_rx_dco_cal = 0x400024e4;\nrom_rxdc_est_min = 0x400024e8;\nrom_pbus_rx_dco_cal_1step = 0x400024ec;\nrom_set_lb_txiq = 0x400024f0;\nrom_set_rx_gain_cal_iq = 0x400024f4;\nrom_set_rx_gain_cal_dc = 0x400024f8;\niq_est_enable = 0x400024fc;\niq_est_disable = 0x40002500;\ndc_iq_est = 0x40002504;\nset_cal_rxdc = 0x40002508;\nrxiq_get_mis = 0x4000250c;\nspur_reg_write_one_tone = 0x40002510;\nspur_cal = 0x40002514;\nspur_coef_cfg = 0x40002518;\ngen_rx_gain_table = 0x4000251c;\nwr_rx_gain_mem = 0x40002520;\nset_rx_gain_param = 0x40002524;\nset_rx_gain_table = 0x40002528;\nrom_tester_wifi_cali = 0x4000252c;\nesp_recover_efuse_data = 0x40002530;\nbt_track_pll_cap = 0x40002534;\nrfpll_cap_track = 0x40002538;\nphy_param_track = 0x4000253c;\ntxpwr_correct = 0x40002540;\ntxpwr_cal_track = 0x40002544;\ntx_pwctrl_background = 0x40002548;\nbt_track_tx_power = 0x4000254c;\nwifi_track_tx_power = 0x40002550;\nrom_code_to_temp = 0x40002554;\nrom_tsens_index_to_dac = 0x40002558;\nrom_tsens_index_to_offset = 0x4000255c;\nrom_tsens_dac_cal = 0x40002560;\nrom_tsens_code_read = 0x40002564;\nrom_tsens_temp_read = 0x40002568;\nrom_temp_to_power = 0x4000256c;\ntsens_read_init = 0x40002570;\nget_temp_init = 0x40002574;\nrom_txiq_cover = 0x40002578;\nrom_rfcal_txiq = 0x4000257c;\nrom_get_power_atten = 0x40002580;\nrom_tx_pwctrl_init_cal = 0x40002584;\nbt_txdc_cal = 0x40002588;\nbt_txiq_cal = 0x4000258c;\ntxiq_cal_init = 0x40002590;\ntxdc_cal_init = 0x40002594;\ntxdc_cal_v70 = 0x40002598;\ntxiq_get_mis_pwr = 0x4000259c;\npwdet_ref_code = 0x400025a0;\npwdet_code_cal = 0x400025a4;\nrfcal_txcap = 0x400025a8;\ntx_cap_init = 0x400025ac;\nrfcal_pwrctrl = 0x400025b0;\ntx_pwctrl_init = 0x400025b4;\nbt_tx_pwctrl_init = 0x400025b8;\nbt_txpwr_freq = 0x400025bc;\nrom_txbbgain_to_index = 0x400025c0;\nrom_index_to_txbbgain = 0x400025c4;\nrom_bt_index_to_bb = 0x400025c8;\nrom_bt_bb_to_index = 0x400025cc;\nrom_bt_get_tx_gain = 0x400025d0;\nrom_get_tx_gain_value = 0x400025d4;\nrom_wifi_get_tx_gain = 0x400025d8;\nrom_set_tx_gain_mem = 0x400025dc;\nrom_get_rate_fcc_index = 0x400025e0;\nrom_get_chan_target_power = 0x400025e4;\nrom_wifi_tx_dig_gain = 0x400025e8;\nrom_wifi_set_tx_gain = 0x400025ec;\nrom_bt_set_tx_gain = 0x400025f0;\nwifi_11g_rate_chg = 0x400025f4;\nbt_chan_pwr_interp = 0x400025f8;\nbt_tx_gain_init = 0x400025fc;\n\/* Data (.data, .bss, .rodata) *\/\nphy_param_rom = 0x3fcdfaa4;\n\n\n\/***************************************\n Group rom_btbb\n ***************************************\/\n\n\/* Functions *\/\nbt_agc_gain_offset = 0x40002600;\nbt_agc_gain_max = 0x40002604;\nbt_set_rx_comp = 0x40002608;\nbt_agc_gain_set = 0x4000260c;\nbt_agc_rssi_thresh = 0x40002610;\nbt_agc_target_set = 0x40002614;\nbt_agc_restart_set = 0x40002618;\nbt_agc_recorrect_set = 0x4000261c;\nbt_agc_detect_set = 0x40002620;\nbt_bb_rx_correlator_set = 0x40002624;\nbt_bb_rx_dpo_set = 0x40002628;\nbt_bb_rx_filter_sel = 0x4000262c;\nbt_bb_rx_set1 = 0x40002630;\nbt_bb_v2_rx_set = 0x40002634;\nbt_bb_v2_tx_set = 0x40002638;\nbt_bb_tx_cca_set = 0x4000263c;\nbt_bb_tx_cca_period = 0x40002640;\nbt_bb_tx_cca_fifo_reset = 0x40002644;\nbt_bb_tx_cca_fifo_empty = 0x40002648;\nbt_bb_tx_cca_fifo_full = 0x4000264c;\nbt_bb_tx_cca_fifo_count = 0x40002650;\nbt_bb_tx_cca_fifo_read = 0x40002654;\ncoex_pti_v2 = 0x40002658;\nbt_bb_set_le_tx_on_delay = 0x4000265c;\nbt_bb_set_corr_thresh_le = 0x40002660;\n","old_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\nrtc_get_wakeup_cause = 0x40000020;\nrtc_select_apb_bridge = 0x40000024;\nrtc_unhold_all_pads = 0x40000028;\nets_is_print_boot = 0x4000002c;\nets_vprintf = 0x40000030;\nets_printf = 0x40000034;\nets_install_putc1 = 0x40000038;\nets_install_uart_printf = 0x4000003c;\nets_install_putc2 = 0x40000040;\nets_delay_us = 0x40000044;\nets_get_stack_info = 0x40000048;\nets_install_lock = 0x4000004c;\nUartRxString = 0x40000050;\nUartGetCmdLn = 0x40000054;\nuart_tx_one_char = 0x40000058;\nuart_tx_one_char2 = 0x4000005c;\nuart_rx_one_char = 0x40000060;\nuart_rx_one_char_block = 0x40000064;\nuart_rx_readbuff = 0x40000068;\nuartAttach = 0x4000006c;\nuart_tx_flush = 0x40000070;\nuart_tx_wait_idle = 0x40000074;\nuart_div_modify = 0x40000078;\nets_write_char_uart = 0x4000007c;\nuart_tx_switch = 0x40000080;\nmultofup = 0x40000084;\nsoftware_reset = 0x40000088;\nsoftware_reset_cpu = 0x4000008c;\nassist_debug_clock_enable = 0x40000090;\nassist_debug_record_enable = 0x40000094;\nclear_super_wdt_reset_flag = 0x40000098;\ndisable_default_watchdog = 0x4000009c;\nsend_packet = 0x400000a0;\nrecv_packet = 0x400000a4;\nGetUartDevice = 0x400000a8;\nUartDwnLdProc = 0x400000ac;\nGetSecurityInfoProc = 0x400000b0;\nUart_Init = 0x400000b4;\nets_set_user_start = 0x400000b8;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff4fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000bc;\nmz_free = 0x400000c0;\ntdefl_compress = 0x400000c4;\ntdefl_compress_buffer = 0x400000c8;\ntdefl_compress_mem_to_heap = 0x400000cc;\ntdefl_compress_mem_to_mem = 0x400000d0;\ntdefl_compress_mem_to_output = 0x400000d4;\ntdefl_get_adler32 = 0x400000d8;\ntdefl_get_prev_return_status = 0x400000dc;\ntdefl_init = 0x400000e0;\ntdefl_write_image_to_png_file_in_memory = 0x400000e4;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000e8;\ntinfl_decompress = 0x400000ec;\ntinfl_decompress_mem_to_callback = 0x400000f0;\ntinfl_decompress_mem_to_heap = 0x400000f4;\ntinfl_decompress_mem_to_mem = 0x400000f8;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 );\nPROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 );\nPROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 );\nPROVIDE( _esp_rom_spiflash_write = 0x4000011c );\nPROVIDE( _esp_rom_spiflash_read = 0x40000120 );\nPROVIDE( _esp_rom_spiflash_unlock = 0x40000124 );\nPROVIDE( _SPIEraseArea = 0x40000128 );\nPROVIDE( _SPI_write_enable = 0x4000012c );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000134 );\nPROVIDE( esp_rom_spiflash_write = 0x40000138 );\nPROVIDE( esp_rom_spiflash_read = 0x4000013c );\nPROVIDE( esp_rom_spiflash_unlock = 0x40000140 );\nPROVIDE( SPIEraseArea = 0x40000144 );\nPROVIDE( SPI_write_enable = 0x40000148 );\nPROVIDE( esp_rom_spiflash_config_param = 0x4000014c );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c );\nPROVIDE( esp_rom_spi_flash_update_id = 0x40000160 );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000164 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 );\nPROVIDE( esp_rom_spiflash_read_status = 0x4000016c );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000174 );\nPROVIDE( spi_flash_attach = 0x40000178 );\nPROVIDE( spi_flash_get_chip_size = 0x4000017c );\nPROVIDE( spi_flash_guard_set = 0x40000180 );\nPROVIDE( spi_flash_guard_get = 0x40000184 );\nPROVIDE( spi_flash_read_encrypted = 0x40000188 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x4000018c );\nPROVIDE( spi_flash_mmap_page_num_init = 0x40000190 );\nPROVIDE( spi_flash_mmap = 0x40000194 );\nPROVIDE( spi_flash_mmap_pages = 0x40000198 );\nPROVIDE( spi_flash_munmap = 0x4000019c );\nPROVIDE( spi_flash_mmap_dump = 0x400001a0 );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );\nPROVIDE( spi_flash_cache2phys = 0x400001ac );\nPROVIDE( spi_flash_phys2cache = 0x400001b0 );\nPROVIDE( spi_flash_disable_cache = 0x400001b4 );\nPROVIDE( spi_flash_restore_cache = 0x400001b8 );\nPROVIDE( spi_flash_cache_enabled = 0x400001bc );\nPROVIDE( spi_flash_enable_cache = 0x400001c0 );\nPROVIDE( spi_cache_mode_switch = 0x400001c4 );\nPROVIDE( spi_common_set_dummy_output = 0x400001c8 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001cc );\nPROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 );\nPROVIDE( SPILock = 0x400001d8 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001dc );\nPROVIDE( SPI_Common_Command = 0x400001e0 );\nPROVIDE( SPI_WakeUp = 0x400001e4 );\nPROVIDE( SPI_block_erase = 0x400001e8 );\nPROVIDE( SPI_chip_erase = 0x400001ec );\nPROVIDE( SPI_init = 0x400001f0 );\nPROVIDE( SPI_page_program = 0x400001f4 );\nPROVIDE( SPI_read_data = 0x400001f8 );\nPROVIDE( SPI_sector_erase = 0x400001fc );\nPROVIDE( SelectSpiFunction = 0x40000200 );\nPROVIDE( SetSpiDrvs = 0x40000204 );\nPROVIDE( Wait_SPI_Idle = 0x40000208 );\nPROVIDE( spi_dummy_len_fix = 0x4000020c );\nPROVIDE( Disable_QMode = 0x40000210 );\nPROVIDE( Enable_QMode = 0x40000214 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group hal_soc\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 );\nPROVIDE( spi_flash_hal_device_config = 0x4000021c );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 );\nPROVIDE( spi_flash_hal_common_command = 0x40000224 );\nPROVIDE( spi_flash_hal_read = 0x40000228 );\nPROVIDE( spi_flash_hal_erase_chip = 0x4000022c );\nPROVIDE( spi_flash_hal_erase_sector = 0x40000230 );\nPROVIDE( spi_flash_hal_erase_block = 0x40000234 );\nPROVIDE( spi_flash_hal_program_page = 0x40000238 );\nPROVIDE( spi_flash_hal_set_write_protect = 0x4000023c );\nPROVIDE( spi_flash_hal_host_idle = 0x40000240 );\nPROVIDE( spi_flash_hal_check_status = 0x40000244 );\nPROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 );\nPROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c );\nPROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 );\nPROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 );\nPROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 );\nPROVIDE( spi_flash_hal_resume = 0x4000025c );\nPROVIDE( spi_flash_hal_suspend = 0x40000260 );\nPROVIDE( spi_flash_encryption_hal_enable = 0x40000264 );\nPROVIDE( spi_flash_encryption_hal_disable = 0x40000268 );\nPROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c );\nPROVIDE( spi_flash_encryption_hal_done = 0x40000270 );\nPROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 );\nPROVIDE( spi_flash_encryption_hal_check = 0x40000278 );\nPROVIDE( wdt_hal_init = 0x4000027c );\nPROVIDE( wdt_hal_deinit = 0x40000280 );\nPROVIDE( wdt_hal_config_stage = 0x40000284 );\nPROVIDE( wdt_hal_write_protect_disable = 0x40000288 );\nPROVIDE( wdt_hal_write_protect_enable = 0x4000028c );\nPROVIDE( wdt_hal_enable = 0x40000290 );\nPROVIDE( wdt_hal_disable = 0x40000294 );\nPROVIDE( wdt_hal_handle_intr = 0x40000298 );\nPROVIDE( wdt_hal_feed = 0x4000029c );\nPROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 );\nPROVIDE( wdt_hal_is_enabled = 0x400002a4 );\nPROVIDE( systimer_hal_init = 0x400002a8 );\nPROVIDE( systimer_hal_get_counter_value = 0x400002ac );\nPROVIDE( systimer_hal_get_time = 0x400002b0 );\nPROVIDE( systimer_hal_set_alarm_target = 0x400002b4 );\nPROVIDE( systimer_hal_set_alarm_period = 0x400002b8 );\nPROVIDE( systimer_hal_get_alarm_value = 0x400002bc );\nPROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 );\nPROVIDE( systimer_hal_on_apb_freq_update = 0x400002c4 );\nPROVIDE( systimer_hal_counter_value_advance = 0x400002c8 );\nPROVIDE( systimer_hal_enable_counter = 0x400002cc );\nPROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 );\nPROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 );\nPROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 );\n\n\n\/***************************************\n Group heap\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( tlsf_create = 0x400002dc );\nPROVIDE( tlsf_create_with_pool = 0x400002e0 );\nPROVIDE( tlsf_get_pool = 0x400002e4 );\nPROVIDE( tlsf_add_pool = 0x400002e8 );\nPROVIDE( tlsf_remove_pool = 0x400002ec );\nPROVIDE( tlsf_malloc = 0x400002f0 );\nPROVIDE( tlsf_memalign = 0x400002f4 );\nPROVIDE( tlsf_memalign_offs = 0x400002f8 );\nPROVIDE( tlsf_realloc = 0x400002fc );\nPROVIDE( tlsf_free = 0x40000300 );\nPROVIDE( tlsf_block_size = 0x40000304 );\nPROVIDE( tlsf_size = 0x40000308 );\nPROVIDE( tlsf_align_size = 0x4000030c );\nPROVIDE( tlsf_block_size_min = 0x40000310 );\nPROVIDE( tlsf_block_size_max = 0x40000314 );\nPROVIDE( tlsf_pool_overhead = 0x40000318 );\nPROVIDE( tlsf_alloc_overhead = 0x4000031c );\nPROVIDE( tlsf_walk_pool = 0x40000320 );\nPROVIDE( tlsf_check = 0x40000324 );\nPROVIDE( tlsf_check_pool = 0x40000328 );\nPROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c );\nPROVIDE( multi_heap_get_block_address_impl = 0x40000330 );\nPROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 );\nPROVIDE( multi_heap_register_impl = 0x40000338 );\nPROVIDE( multi_heap_set_lock = 0x4000033c );\nPROVIDE( multi_heap_os_funcs_init = 0x40000340 );\nPROVIDE( multi_heap_internal_lock = 0x40000344 );\nPROVIDE( multi_heap_internal_unlock = 0x40000348 );\nPROVIDE( multi_heap_get_first_block = 0x4000034c );\nPROVIDE( multi_heap_get_next_block = 0x40000350 );\nPROVIDE( multi_heap_is_free = 0x40000354 );\nPROVIDE( multi_heap_malloc_impl = 0x40000358 );\nPROVIDE( multi_heap_free_impl = 0x4000035c );\nPROVIDE( multi_heap_realloc_impl = 0x40000360 );\nPROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 );\nPROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 );\nPROVIDE( multi_heap_check = 0x4000036c );\nPROVIDE( multi_heap_dump = 0x40000370 );\nPROVIDE( multi_heap_free_size_impl = 0x40000374 );\nPROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 );\nPROVIDE( multi_heap_get_info_impl = 0x4000037c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x40000380 );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 );\nPROVIDE( spi_flash_chip_generic_write = 0x40000388 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000398 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 );\nPROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 );\nPROVIDE( spi_flash_chip_generic_yield = 0x400003b8 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 );\nPROVIDE( spi_flash_chip_generic_read = 0x400003c8 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc );\nPROVIDE( spi_flash_common_set_io_mode = 0x400003e0 );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 );\nPROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 );\nPROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec );\nPROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400003f8 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );\nPROVIDE( spi_flash_encryption = 0x3fcdffe4 );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x40000400 );\nPROVIDE( memspi_host_read_status_hs = 0x40000404 );\nPROVIDE( memspi_host_flush_cache = 0x40000408 );\nPROVIDE( memspi_host_erase_chip = 0x4000040c );\nPROVIDE( memspi_host_erase_sector = 0x40000410 );\nPROVIDE( memspi_host_erase_block = 0x40000414 );\nPROVIDE( memspi_host_program_page = 0x40000418 );\nPROVIDE( memspi_host_read = 0x4000041c );\nPROVIDE( memspi_host_set_write_protect = 0x40000420 );\nPROVIDE( memspi_host_set_max_read_len = 0x40000424 );\nPROVIDE( memspi_host_read_data_slicer = 0x40000428 );\nPROVIDE( memspi_host_write_data_slicer = 0x4000042c );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x40000430 );\nPROVIDE( esp_flash_read_id = 0x40000434 );\nPROVIDE( esp_flash_get_size = 0x40000438 );\nPROVIDE( esp_flash_erase_chip = 0x4000043c );\nPROVIDE( esp_flash_erase_region = 0x40000440 );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000444 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000448 );\nPROVIDE( esp_flash_get_protectable_regions = 0x4000044c );\nPROVIDE( esp_flash_get_protected_region = 0x40000450 );\nPROVIDE( esp_flash_set_protected_region = 0x40000454 );\nPROVIDE( esp_flash_read = 0x40000458 );\nPROVIDE( esp_flash_write = 0x4000045c );\nPROVIDE( esp_flash_write_encrypted = 0x40000460 );\nPROVIDE( esp_flash_read_encrypted = 0x40000464 );\nPROVIDE( esp_flash_get_io_mode = 0x40000468 );\nPROVIDE( esp_flash_set_io_mode = 0x4000046c );\nPROVIDE( spi_flash_boot_attach = 0x40000470 );\nPROVIDE( esp_flash_read_chip_id = 0x40000474 );\nPROVIDE( detect_spi_flash_chip = 0x40000478 );\nPROVIDE( esp_rom_spiflash_write_disable = 0x4000047c );\nPROVIDE( esp_flash_suspend_cmd_init = 0x40000480 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe0 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffdc );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 );\nPROVIDE( Cache_Get_Mode = 0x400006e4 );\nPROVIDE( Cache_Address_Through_IBus = 0x400006e8 );\nPROVIDE( Cache_Address_Through_DBus = 0x400006ec );\nPROVIDE( Cache_Set_Default_Mode = 0x400006f0 );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400006f8 );\nPROVIDE( MMU_Set_Page_Mode = 0x400006fc );\nPROVIDE( MMU_Get_Page_Mode = 0x40000700 );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x40000704 );\nPROVIDE( Cache_Op_Addr = 0x40000708 );\nPROVIDE( Cache_Invalidate_Addr = 0x4000070c );\nPROVIDE( Cache_Invalidate_ICache_All = 0x40000710 );\nPROVIDE( Cache_Mask_All = 0x40000714 );\nPROVIDE( Cache_UnMask_Dram0 = 0x40000718 );\nPROVIDE( Cache_Disable_ICache = 0x4000071c );\nPROVIDE( Cache_Enable_ICache = 0x40000720 );\nPROVIDE( Cache_Suspend_ICache = 0x40000724 );\nPROVIDE( Cache_Resume_ICache = 0x40000728 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x4000072c );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x40000730 );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000734 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x40000738 );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x4000073c );\nPROVIDE( Cache_Owner_Init = 0x40000740 );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000744 );\nPROVIDE( Cache_MMU_Init = 0x40000748 );\nPROVIDE( Cache_Ibus_MMU_Set = 0x4000074c );\nPROVIDE( Cache_Dbus_MMU_Set = 0x40000750 );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000754 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x40000758 );\nPROVIDE( Cache_Get_Virtual_Addr = 0x4000075c );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x40000760 );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000764 );\nPROVIDE( Cache_Get_Memory_value = 0x40000768 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd0 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x4000076c;\nets_get_cpu_frequency = 0x40000770;\nets_update_cpu_frequency = 0x40000774;\nets_get_printf_channel = 0x40000778;\nets_get_xtal_div = 0x4000077c;\nets_set_xtal_div = 0x40000780;\nets_get_xtal_freq = 0x40000784;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x40000788;\ngpio_matrix_in = 0x4000078c;\ngpio_matrix_out = 0x40000790;\ngpio_output_disable = 0x40000794;\ngpio_output_enable = 0x40000798;\ngpio_output_set = 0x4000079c;\ngpio_pad_hold = 0x400007a0;\ngpio_pad_input_disable = 0x400007a4;\ngpio_pad_input_enable = 0x400007a8;\ngpio_pad_pulldown = 0x400007ac;\ngpio_pad_pullup = 0x400007b0;\ngpio_pad_select_gpio = 0x400007b4;\ngpio_pad_set_drv = 0x400007b8;\ngpio_pad_unhold = 0x400007bc;\ngpio_pin_wakeup_disable = 0x400007c0;\ngpio_pin_wakeup_enable = 0x400007c4;\ngpio_bypass_matrix_in = 0x400007c8;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400007cc;\nesprv_intc_int_set_threshold = 0x400007d0;\nesprv_intc_int_enable = 0x400007d4;\nesprv_intc_int_disable = 0x400007d8;\nesprv_intc_int_set_type = 0x400007dc;\nPROVIDE( intr_handler_set = 0x400007e0 );\nintr_matrix_set = 0x400007e4;\nets_intr_lock = 0x400007e8;\nets_intr_unlock = 0x400007ec;\nets_isr_attach = 0x400007f0;\nets_isr_mask = 0x400007f4;\nets_isr_unmask = 0x400007f8;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\ncrc32_le = 0x400007fc;\ncrc16_le = 0x40000800;\ncrc8_le = 0x40000804;\ncrc32_be = 0x40000808;\ncrc16_be = 0x4000080c;\ncrc8_be = 0x40000810;\nesp_crc8 = 0x40000814;\nets_sha_enable = 0x40000818;\nets_sha_disable = 0x4000081c;\nets_sha_get_state = 0x40000820;\nets_sha_init = 0x40000824;\nets_sha_process = 0x40000828;\nets_sha_starts = 0x4000082c;\nets_sha_update = 0x40000830;\nets_sha_finish = 0x40000834;\nets_sha_clone = 0x40000838;\n\/* Data (.data, .bss, .rodata) *\/\ncrc32_le_table_ptr = 0x3ff4fff8;\ncrc16_le_table_ptr = 0x3ff4fff4;\ncrc8_le_table_ptr = 0x3ff4fff0;\ncrc32_be_table_ptr = 0x3ff4ffec;\ncrc16_be_table_ptr = 0x3ff4ffe8;\ncrc8_be_table_ptr = 0x3ff4ffe4;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x4000083c;\nets_efuse_program = 0x40000840;\nets_efuse_clear_program_registers = 0x40000844;\nets_efuse_write_key = 0x40000848;\nets_efuse_get_read_register_address = 0x4000084c;\nets_efuse_get_key_purpose = 0x40000850;\nets_efuse_key_block_unused = 0x40000854;\nets_efuse_find_unused_key_block = 0x40000858;\nets_efuse_rs_calculate = 0x4000085c;\nets_efuse_count_unused_key_blocks = 0x40000860;\nets_efuse_secure_boot_enabled = 0x40000864;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000868;\nets_efuse_cache_encryption_enabled = 0x4000086c;\nets_efuse_download_modes_disabled = 0x40000870;\nets_efuse_find_purpose = 0x40000874;\nets_efuse_force_send_resume = 0x40000878;\nets_efuse_get_flash_delay_us = 0x4000087c;\nets_efuse_get_mac = 0x40000880;\nets_efuse_get_uart_print_control = 0x40000884;\nets_efuse_direct_boot_mode_disabled = 0x40000888;\nets_efuse_security_download_modes_enabled = 0x4000088c;\nets_efuse_set_timing = 0x40000890;\nets_efuse_jtag_disabled = 0x40000894;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_ecdsa_verify = 0x40000898;\nets_secure_boot_verify_bootloader_with_keys = 0x4000089c;\nets_secure_boot_verify_signature = 0x400008a0;\nets_secure_boot_read_key_digests = 0x400008a4;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Data (.data, .bss, .rodata) *\/\ng_uart_print = 0x3fcdffc9;\ng_usb_print = 0x3fcdffc8;\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nble_controller_rom_data_init = 0x40000aa8;\nble_osi_coex_funcs_register = 0x40000aac;\nbt_rf_coex_cfg_get_default = 0x40000ab0;\nbt_rf_coex_dft_pti_get_default = 0x40000ab4;\nbt_rf_coex_hooks_p_set = 0x40000ab8;\nr__os_mbuf_copypkthdr = 0x40000abc;\nr__os_msys_find_pool = 0x40000ac0;\nr_ble_controller_get_rom_compile_version = 0x40000ac4;\nr_ble_hci_ram_hs_acl_tx = 0x40000ac8;\nr_ble_hci_ram_hs_cmd_tx = 0x40000acc;\nr_ble_hci_ram_ll_acl_tx = 0x40000ad0;\nr_ble_hci_ram_ll_evt_tx = 0x40000ad4;\nr_ble_hci_ram_reset = 0x40000ad8;\nr_ble_hci_ram_set_acl_free_cb = 0x40000adc;\nr_ble_hci_trans_acl_buf_alloc = 0x40000ae0;\nr_ble_hci_trans_buf_alloc = 0x40000ae4;\nr_ble_hci_trans_buf_free = 0x40000ae8;\nr_ble_hci_trans_cfg_hs = 0x40000aec;\nr_ble_hci_trans_cfg_ll = 0x40000af0;\nr_ble_hci_trans_deinit = 0x40000af4;\nr_ble_hci_trans_env_init = 0x40000af8;\nr_ble_hci_trans_init = 0x40000afc;\nr_ble_hci_uart_acl_tx = 0x40000b00;\nr_ble_hci_uart_cmdevt_tx = 0x40000b04;\nr_ble_hci_uart_config = 0x40000b08;\nr_ble_hci_uart_free_pkt = 0x40000b0c;\nr_ble_hci_uart_hs_acl_tx = 0x40000b10;\nr_ble_hci_uart_hs_cmd_tx = 0x40000b14;\nr_ble_hci_uart_ll_acl_tx = 0x40000b18;\nr_ble_hci_uart_ll_evt_tx = 0x40000b1c;\nr_ble_hci_uart_rx_acl = 0x40000b20;\nr_ble_hci_uart_rx_char = 0x40000b24;\nr_ble_hci_uart_rx_cmd = 0x40000b28;\nr_ble_hci_uart_rx_evt = 0x40000b2c;\nr_ble_hci_uart_rx_evt_cb = 0x40000b30;\nr_ble_hci_uart_rx_le_evt = 0x40000b34;\nr_ble_hci_uart_rx_pkt_type = 0x40000b38;\nr_ble_hci_uart_rx_skip_acl = 0x40000b3c;\nr_ble_hci_uart_rx_skip_cmd = 0x40000b40;\nr_ble_hci_uart_rx_skip_evt = 0x40000b44;\nr_ble_hci_uart_rx_sync_loss = 0x40000b48;\nr_ble_hci_uart_set_acl_free_cb = 0x40000b4c;\nr_ble_hci_uart_sync_lost = 0x40000b50;\nr_ble_hci_uart_trans_reset = 0x40000b54;\nr_ble_hci_uart_tx_char = 0x40000b58;\nr_ble_hci_uart_tx_pkt_type = 0x40000b5c;\nr_ble_hw_driver_deinit = 0x40000b60;\nr_ble_hw_driver_env_init = 0x40000b64;\nr_ble_hw_encrypt_block = 0x40000b68;\nr_ble_hw_get_public_addr = 0x40000b6c;\nr_ble_hw_get_static_addr = 0x40000b70;\nr_ble_hw_periodiclist_add = 0x40000b74;\nr_ble_hw_periodiclist_clear = 0x40000b78;\nr_ble_hw_periodiclist_rmv = 0x40000b7c;\nr_ble_hw_resolv_list_cur_entry = 0x40000b80;\nr_ble_hw_resolv_list_get_cur_entry = 0x40000b84;\nr_ble_hw_resolv_list_set = 0x40000b88;\nr_ble_hw_rng_init = 0x40000b8c;\nr_ble_hw_rng_start = 0x40000b90;\nr_ble_hw_rng_stop = 0x40000b94;\nr_ble_hw_rx_local_is_resolved = 0x40000b98;\nr_ble_hw_rx_local_is_rpa = 0x40000b9c;\nr_ble_hw_whitelist_add = 0x40000ba0;\nr_ble_hw_whitelist_clear = 0x40000ba4;\nr_ble_hw_whitelist_dev_num = 0x40000ba8;\nr_ble_hw_whitelist_get_base = 0x40000bac;\nr_ble_hw_whitelist_rmv = 0x40000bb0;\nr_ble_hw_whitelist_search = 0x40000bb4;\nr_ble_hw_whitelist_sort = 0x40000bb8;\nr_ble_ll_acl_data_in = 0x40000bbc;\nr_ble_ll_addr_is_id = 0x40000bc0;\nr_ble_ll_addr_subtype = 0x40000bc4;\nr_ble_ll_adv_active_chanset_clear = 0x40000bc8;\nr_ble_ll_adv_active_chanset_is_pri = 0x40000bcc;\nr_ble_ll_adv_active_chanset_is_sec = 0x40000bd0;\nr_ble_ll_adv_active_chanset_set_pri = 0x40000bd4;\nr_ble_ll_adv_active_chanset_set_sec = 0x40000bd8;\nr_ble_ll_adv_aux_calculate = 0x40000bdc;\nr_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000be0;\nr_ble_ll_adv_aux_pdu_make = 0x40000be4;\nr_ble_ll_adv_aux_scannable_pdu_make = 0x40000be8;\nr_ble_ll_adv_aux_txed = 0x40000bec;\nr_ble_ll_adv_can_chg_whitelist = 0x40000bf0;\nr_ble_ll_adv_chk_rpa_timeout = 0x40000bf4;\nr_ble_ll_adv_clear_all = 0x40000bf8;\nr_ble_ll_adv_conn_req_rxd = 0x40000bfc;\nr_ble_ll_adv_deinit = 0x40000c00;\nr_ble_ll_adv_enabled = 0x40000c04;\nr_ble_ll_adv_env_init = 0x40000c08;\nr_ble_ll_adv_ext_set_adv_data = 0x40000c0c;\nr_ble_ll_adv_ext_set_enable = 0x40000c10;\nr_ble_ll_adv_ext_set_param = 0x40000c14;\nr_ble_ll_adv_ext_set_scan_rsp = 0x40000c18;\nr_ble_ll_adv_final_chan = 0x40000c1c;\nr_ble_ll_adv_first_chan = 0x40000c20;\nr_ble_ll_adv_flags_clear = 0x40000c24;\nr_ble_ll_adv_flags_set = 0x40000c28;\nr_ble_ll_adv_get_chan_num = 0x40000c2c;\nr_ble_ll_adv_get_local_rpa = 0x40000c30;\nr_ble_ll_adv_get_peer_rpa = 0x40000c34;\nr_ble_ll_adv_hci_set_random_addr = 0x40000c38;\nr_ble_ll_adv_init = 0x40000c3c;\nr_ble_ll_adv_legacy_pdu_make = 0x40000c40;\nr_ble_ll_adv_next_chan = 0x40000c44;\nr_ble_ll_adv_pdu_make = 0x40000c48;\nr_ble_ll_adv_periodic_check_data_itvl = 0x40000c4c;\nr_ble_ll_adv_periodic_enable = 0x40000c50;\nr_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c54;\nr_ble_ll_adv_periodic_send_sync_ind = 0x40000c58;\nr_ble_ll_adv_periodic_set_data = 0x40000c5c;\nr_ble_ll_adv_periodic_set_info_transfer = 0x40000c60;\nr_ble_ll_adv_periodic_set_param = 0x40000c64;\nr_ble_ll_adv_pre_process = 0x40000c68;\nr_ble_ll_adv_put_acad_chM_update_ind = 0x40000c6c;\nr_ble_ll_adv_put_aux_ptr = 0x40000c70;\nr_ble_ll_adv_put_syncinfo = 0x40000c74;\nr_ble_ll_adv_rd_max_adv_data_len = 0x40000c78;\nr_ble_ll_adv_rd_sup_adv_sets = 0x40000c7c;\nr_ble_ll_adv_read_txpwr = 0x40000c80;\nr_ble_ll_adv_remove = 0x40000c84;\nr_ble_ll_adv_reset = 0x40000c88;\nr_ble_ll_adv_rpa_timeout = 0x40000c8c;\nr_ble_ll_adv_rpa_update = 0x40000c90;\nr_ble_ll_adv_rx_pkt_in = 0x40000c94;\nr_ble_ll_adv_scan_req_rxd = 0x40000c98;\nr_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c;\nr_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0;\nr_ble_ll_adv_scheduled = 0x40000ca4;\nr_ble_ll_adv_send_conn_comp_ev = 0x40000ca8;\nr_ble_ll_adv_set_adv_data = 0x40000cac;\nr_ble_ll_adv_set_adv_params = 0x40000cb0;\nr_ble_ll_adv_set_enable = 0x40000cb4;\nr_ble_ll_adv_set_random_addr = 0x40000cb8;\nr_ble_ll_adv_set_scan_rsp_data = 0x40000cbc;\nr_ble_ll_adv_set_sched = 0x40000cc0;\nr_ble_ll_adv_sm_deinit = 0x40000cc4;\nr_ble_ll_adv_sm_event_init = 0x40000cc8;\nr_ble_ll_adv_sm_find_configured = 0x40000ccc;\nr_ble_ll_adv_sm_get = 0x40000cd0;\nr_ble_ll_adv_sm_init = 0x40000cd4;\nr_ble_ll_adv_sm_reset = 0x40000cd8;\nr_ble_ll_adv_sm_start = 0x40000cdc;\nr_ble_ll_adv_sm_start_periodic = 0x40000ce0;\nr_ble_ll_adv_sm_stop = 0x40000ce4;\nr_ble_ll_adv_sm_stop_limit_reached = 0x40000ce8;\nr_ble_ll_adv_sm_stop_periodic = 0x40000cec;\nr_ble_ll_adv_sm_stop_timeout = 0x40000cf0;\nr_ble_ll_adv_sync_calculate = 0x40000cf4;\nr_ble_ll_adv_sync_get_pdu_len = 0x40000cf8;\nr_ble_ll_adv_sync_pdu_make = 0x40000cfc;\nr_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d00;\nr_ble_ll_adv_update_data_mbuf = 0x40000d04;\nr_ble_ll_adv_update_did = 0x40000d08;\nr_ble_ll_adv_update_periodic_data = 0x40000d0c;\nr_ble_ll_arr_pool_init = 0x40000d10;\nr_ble_ll_auth_pyld_tmo_event_send = 0x40000d14;\nr_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d18;\nr_ble_ll_calc_session_key = 0x40000d1c;\nr_ble_ll_calc_ticks_per_slot = 0x40000d20;\nr_ble_ll_check_scan_params = 0x40000d24;\nr_ble_ll_chk_txrx_octets = 0x40000d28;\nr_ble_ll_chk_txrx_time = 0x40000d2c;\nr_ble_ll_conn_adjust_pyld_len = 0x40000d30;\nr_ble_ll_conn_auth_pyld_timer_cb = 0x40000d34;\nr_ble_ll_conn_auth_pyld_timer_start = 0x40000d38;\nr_ble_ll_conn_calc_dci = 0x40000d3c;\nr_ble_ll_conn_calc_dci_csa1 = 0x40000d40;\nr_ble_ll_conn_calc_itvl_ticks = 0x40000d44;\nr_ble_ll_conn_chk_csm_flags = 0x40000d48;\nr_ble_ll_conn_chk_phy_upd_start = 0x40000d4c;\nr_ble_ll_conn_comp_event_send = 0x40000d50;\nr_ble_ll_conn_connect_ind_pdu_make = 0x40000d54;\nr_ble_ll_conn_create = 0x40000d58;\nr_ble_ll_conn_create_cancel = 0x40000d5c;\nr_ble_ll_conn_created = 0x40000d60;\nr_ble_ll_conn_cth_flow_enable = 0x40000d64;\nr_ble_ll_conn_cth_flow_error_fn = 0x40000d68;\nr_ble_ll_conn_cth_flow_have_credit = 0x40000d6c;\nr_ble_ll_conn_cth_flow_is_enabled = 0x40000d70;\nr_ble_ll_conn_cth_flow_process_cmd = 0x40000d74;\nr_ble_ll_conn_cth_flow_set_buffers = 0x40000d78;\nr_ble_ll_conn_enqueue_pkt = 0x40000d7c;\nr_ble_ll_conn_env_init = 0x40000d80;\nr_ble_ll_conn_ext_master_init = 0x40000d84;\nr_ble_ll_conn_find_active_conn = 0x40000d88;\nr_ble_ll_conn_get_active_conn = 0x40000d8c;\nr_ble_ll_conn_get_anchor = 0x40000d90;\nr_ble_ll_conn_hcc_params_set_fallback = 0x40000d94;\nr_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000d98;\nr_ble_ll_conn_hci_chk_conn_params = 0x40000d9c;\nr_ble_ll_conn_hci_chk_scan_params = 0x40000da0;\nr_ble_ll_conn_hci_disconnect_cmd = 0x40000da4;\nr_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000da8;\nr_ble_ll_conn_hci_le_ltk_reply = 0x40000dac;\nr_ble_ll_conn_hci_le_rd_phy = 0x40000db0;\nr_ble_ll_conn_hci_le_set_phy = 0x40000db4;\nr_ble_ll_conn_hci_le_start_encrypt = 0x40000db8;\nr_ble_ll_conn_hci_param_nrr = 0x40000dbc;\nr_ble_ll_conn_hci_param_rr = 0x40000dc0;\nr_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000dc4;\nr_ble_ll_conn_hci_rd_chan_map = 0x40000dc8;\nr_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000dcc;\nr_ble_ll_conn_hci_rd_rssi = 0x40000dd0;\nr_ble_ll_conn_hci_read_rem_features = 0x40000dd4;\nr_ble_ll_conn_hci_set_chan_class = 0x40000dd8;\nr_ble_ll_conn_hci_set_data_len = 0x40000ddc;\nr_ble_ll_conn_hci_update = 0x40000de0;\nr_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000de4;\nr_ble_ll_conn_init_phy = 0x40000de8;\nr_ble_ll_conn_is_dev_connected = 0x40000dec;\nr_ble_ll_conn_is_empty_pdu = 0x40000df0;\nr_ble_ll_conn_is_lru = 0x40000df4;\nr_ble_ll_conn_master_init = 0x40000df8;\nr_ble_ll_conn_module_deinit = 0x40000dfc;\nr_ble_ll_conn_module_init = 0x40000e00;\nr_ble_ll_conn_module_reset = 0x40000e04;\nr_ble_ll_conn_next_event = 0x40000e08;\nr_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c;\nr_ble_ll_conn_prepare_tx_pdu = 0x40000e10;\nr_ble_ll_conn_process_conn_params = 0x40000e14;\nr_ble_ll_conn_req_peer_sca = 0x40000e18;\nr_ble_ll_conn_rx_data_pdu = 0x40000e1c;\nr_ble_ll_conn_set_csa = 0x40000e20;\nr_ble_ll_conn_set_ext_con_params = 0x40000e24;\nr_ble_ll_conn_set_global_chanmap = 0x40000e28;\nr_ble_ll_conn_set_phy = 0x40000e2c;\nr_ble_ll_conn_set_txpwr_by_handle = 0x40000e30;\nr_ble_ll_conn_set_unknown_rx_octets = 0x40000e34;\nr_ble_ll_conn_slave_start = 0x40000e38;\nr_ble_ll_conn_sm_get = 0x40000e3c;\nr_ble_ll_conn_sm_new = 0x40000e40;\nr_ble_ll_conn_sm_npl_deinit = 0x40000e44;\nr_ble_ll_conn_sm_npl_init = 0x40000e48;\nr_ble_ll_conn_tx_pkt_in = 0x40000e4c;\nr_ble_ll_conn_update_eff_data_len = 0x40000e50;\nr_ble_ll_ctrl_chanmap_req_make = 0x40000e54;\nr_ble_ll_ctrl_chk_proc_start = 0x40000e58;\nr_ble_ll_ctrl_conn_param_pdu_make = 0x40000e5c;\nr_ble_ll_ctrl_conn_param_pdu_proc = 0x40000e60;\nr_ble_ll_ctrl_conn_param_reply = 0x40000e64;\nr_ble_ll_ctrl_conn_upd_make = 0x40000e68;\nr_ble_ll_ctrl_datalen_upd_make = 0x40000e6c;\nr_ble_ll_ctrl_enc_allowed_pdu = 0x40000e70;\nr_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000e74;\nr_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40000e78;\nr_ble_ll_ctrl_enc_req_make = 0x40000e7c;\nr_ble_ll_ctrl_find_new_phy = 0x40000e80;\nr_ble_ll_ctrl_initiate_dle = 0x40000e84;\nr_ble_ll_ctrl_len_proc = 0x40000e88;\nr_ble_ll_ctrl_min_used_chan_rsp = 0x40000e8c;\nr_ble_ll_ctrl_phy_from_phy_mask = 0x40000e90;\nr_ble_ll_ctrl_phy_req_rsp_make = 0x40000e94;\nr_ble_ll_ctrl_phy_tx_transition_get = 0x40000e98;\nr_ble_ll_ctrl_phy_update_cancel = 0x40000e9c;\nr_ble_ll_ctrl_phy_update_ind_make = 0x40000ea0;\nr_ble_ll_ctrl_phy_update_proc_complete = 0x40000ea4;\nr_ble_ll_ctrl_proc_init = 0x40000ea8;\nr_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000eac;\nr_ble_ll_ctrl_proc_start = 0x40000eb0;\nr_ble_ll_ctrl_proc_stop = 0x40000eb4;\nr_ble_ll_ctrl_proc_unk_rsp = 0x40000eb8;\nr_ble_ll_ctrl_proc_with_instant_initiated = 0x40000ebc;\nr_ble_ll_ctrl_rej_ext_ind_make = 0x40000ec0;\nr_ble_ll_ctrl_reject_ind_send = 0x40000ec4;\nr_ble_ll_ctrl_rx_chanmap_req = 0x40000ec8;\nr_ble_ll_ctrl_rx_conn_param_req = 0x40000ecc;\nr_ble_ll_ctrl_rx_conn_param_rsp = 0x40000ed0;\nr_ble_ll_ctrl_rx_conn_update = 0x40000ed4;\nr_ble_ll_ctrl_rx_enc_req = 0x40000ed8;\nr_ble_ll_ctrl_rx_enc_rsp = 0x40000edc;\nr_ble_ll_ctrl_rx_feature_req = 0x40000ee0;\nr_ble_ll_ctrl_rx_feature_rsp = 0x40000ee4;\nr_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8;\nr_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec;\nr_ble_ll_ctrl_rx_pdu = 0x40000ef0;\nr_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4;\nr_ble_ll_ctrl_rx_phy_req = 0x40000ef8;\nr_ble_ll_ctrl_rx_phy_rsp = 0x40000efc;\nr_ble_ll_ctrl_rx_phy_update_ind = 0x40000f00;\nr_ble_ll_ctrl_rx_ping_rsp = 0x40000f04;\nr_ble_ll_ctrl_rx_reject_ind = 0x40000f08;\nr_ble_ll_ctrl_rx_sca_req = 0x40000f0c;\nr_ble_ll_ctrl_rx_sca_rsp = 0x40000f10;\nr_ble_ll_ctrl_rx_start_enc_req = 0x40000f14;\nr_ble_ll_ctrl_rx_start_enc_rsp = 0x40000f18;\nr_ble_ll_ctrl_rx_version_ind = 0x40000f1c;\nr_ble_ll_ctrl_sca_req_rsp_make = 0x40000f20;\nr_ble_ll_ctrl_start_enc_send = 0x40000f24;\nr_ble_ll_ctrl_start_rsp_timer = 0x40000f28;\nr_ble_ll_ctrl_terminate_start = 0x40000f2c;\nr_ble_ll_ctrl_tx_done = 0x40000f30;\nr_ble_ll_ctrl_update_features = 0x40000f34;\nr_ble_ll_ctrl_version_ind_make = 0x40000f38;\nr_ble_ll_data_buffer_overflow = 0x40000f3c;\nr_ble_ll_deinit = 0x40000f40;\nr_ble_ll_disconn_comp_event_send = 0x40000f44;\nr_ble_ll_env_init = 0x40000f48;\nr_ble_ll_event_comp_pkts = 0x40000f4c;\nr_ble_ll_event_dbuf_overflow = 0x40000f50;\nr_ble_ll_event_send = 0x40000f54;\nr_ble_ll_event_tx_pkt = 0x40000f58;\nr_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40000f5c;\nr_ble_ll_ext_conn_create = 0x40000f60;\nr_ble_ll_ext_scan_parse_adv_info = 0x40000f64;\nr_ble_ll_ext_scan_parse_aux_ptr = 0x40000f68;\nr_ble_ll_flush_pkt_queue = 0x40000f6c;\nr_ble_ll_generate_dh_key_v1 = 0x40000f70;\nr_ble_ll_generate_dh_key_v2 = 0x40000f74;\nr_ble_ll_generic_data_init = 0x40000f78;\nr_ble_ll_get_addr_type = 0x40000f7c;\nr_ble_ll_get_chan_to_scan = 0x40000f80;\nr_ble_ll_get_our_devaddr = 0x40000f84;\nr_ble_ll_get_tx_pwr_compensation = 0x40000f88;\nr_ble_ll_hci_acl_rx = 0x40000f8c;\nr_ble_ll_hci_adv_mode_ext = 0x40000f90;\nr_ble_ll_hci_adv_set_enable = 0x40000f94;\nr_ble_ll_hci_cb_host_buf_size = 0x40000f98;\nr_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x40000f9c;\nr_ble_ll_hci_cb_set_event_mask = 0x40000fa0;\nr_ble_ll_hci_cb_set_event_mask2 = 0x40000fa4;\nr_ble_ll_hci_chk_phy_masks = 0x40000fa8;\nr_ble_ll_hci_cmd_proc = 0x40000fac;\nr_ble_ll_hci_cmd_rx = 0x40000fb0;\nr_ble_ll_hci_ctlr_bb_cmd_proc = 0x40000fb4;\nr_ble_ll_hci_deinit = 0x40000fb8;\nr_ble_ll_hci_disconnect = 0x40000fbc;\nr_ble_ll_hci_env_init = 0x40000fc0;\nr_ble_ll_hci_ev_conn_update = 0x40000fc4;\nr_ble_ll_hci_ev_databuf_overflow = 0x40000fc8;\nr_ble_ll_hci_ev_datalen_chg = 0x40000fcc;\nr_ble_ll_hci_ev_encrypt_chg = 0x40000fd0;\nr_ble_ll_hci_ev_hw_err = 0x40000fd4;\nr_ble_ll_hci_ev_le_csa = 0x40000fd8;\nr_ble_ll_hci_ev_ltk_req = 0x40000fdc;\nr_ble_ll_hci_ev_phy_update = 0x40000fe0;\nr_ble_ll_hci_ev_rd_rem_used_feat = 0x40000fe4;\nr_ble_ll_hci_ev_rd_rem_ver = 0x40000fe8;\nr_ble_ll_hci_ev_rem_conn_parm_req = 0x40000fec;\nr_ble_ll_hci_ev_sca_update = 0x40000ff0;\nr_ble_ll_hci_ev_send_adv_set_terminated = 0x40000ff4;\nr_ble_ll_hci_ev_send_scan_req_recv = 0x40000ff8;\nr_ble_ll_hci_ev_send_scan_timeout = 0x40000ffc;\nr_ble_ll_hci_ev_send_vendor_err = 0x40001000;\nr_ble_ll_hci_event_send = 0x40001004;\nr_ble_ll_hci_ext_scan_set_enable = 0x40001008;\nr_ble_ll_hci_get_num_cmd_pkts = 0x4000100c;\nr_ble_ll_hci_info_params_cmd_proc = 0x40001010;\nr_ble_ll_hci_init = 0x40001014;\nr_ble_ll_hci_init_support_cmd_base_on_lmp_ver = 0x40001018;\nr_ble_ll_hci_is_event_enabled = 0x4000101c;\nr_ble_ll_hci_is_le_event_enabled = 0x40001020;\nr_ble_ll_hci_le_cmd_proc = 0x40001024;\nr_ble_ll_hci_le_cmd_send_cmd_status = 0x40001028;\nr_ble_ll_hci_le_encrypt = 0x4000102c;\nr_ble_ll_hci_le_rand = 0x40001030;\nr_ble_ll_hci_le_rd_max_data_len = 0x40001034;\nr_ble_ll_hci_le_rd_sugg_data_len = 0x40001038;\nr_ble_ll_hci_le_read_bufsize = 0x4000103c;\nr_ble_ll_hci_le_read_local_features = 0x40001040;\nr_ble_ll_hci_le_read_supp_states = 0x40001044;\nr_ble_ll_hci_le_set_def_phy = 0x40001048;\nr_ble_ll_hci_le_wr_sugg_data_len = 0x4000104c;\nr_ble_ll_hci_link_ctrl_cmd_proc = 0x40001050;\nr_ble_ll_hci_npl_init = 0x40001054;\nr_ble_ll_hci_post_gen_dhkey_cmp_evt = 0x40001058;\nr_ble_ll_hci_post_rd_p256_pubkey_cmp_evt = 0x4000105c;\nr_ble_ll_hci_rd_bd_addr = 0x40001060;\nr_ble_ll_hci_rd_local_supp_cmd = 0x40001064;\nr_ble_ll_hci_rd_local_supp_feat = 0x40001068;\nr_ble_ll_hci_rd_local_version = 0x4000106c;\nr_ble_ll_hci_scan_set_enable = 0x40001070;\nr_ble_ll_hci_send_adv_report = 0x40001074;\nr_ble_ll_hci_send_dir_adv_report = 0x40001078;\nr_ble_ll_hci_send_ext_adv_report = 0x4000107c;\nr_ble_ll_hci_send_legacy_ext_adv_report = 0x40001080;\nr_ble_ll_hci_send_noop = 0x40001084;\nr_ble_ll_hci_set_adv_data = 0x40001088;\nr_ble_ll_hci_set_le_event_mask = 0x4000108c;\nr_ble_ll_hci_set_scan_rsp_data = 0x40001090;\nr_ble_ll_hci_status_params_cmd_proc = 0x40001094;\nr_ble_ll_hci_vs_cmd_proc = 0x40001098;\nr_ble_ll_hci_vs_rd_static_addr = 0x4000109c;\nr_ble_ll_hw_err_timer_cb = 0x400010a0;\nr_ble_ll_hw_error = 0x400010a4;\nr_ble_ll_init = 0x400010a8;\nr_ble_ll_init_alloc_conn_comp_ev = 0x400010ac;\nr_ble_ll_init_get_conn_comp_ev = 0x400010b0;\nr_ble_ll_init_rx_pkt_in = 0x400010b4;\nr_ble_ll_is_addr_empty = 0x400010b8;\nr_ble_ll_is_controller_busy = 0x400010bc;\nr_ble_ll_is_on_resolv_list = 0x400010c0;\nr_ble_ll_is_our_devaddr = 0x400010c4;\nr_ble_ll_is_rpa = 0x400010c8;\nr_ble_ll_is_valid_adv_mode = 0x400010cc;\nr_ble_ll_is_valid_own_addr_type = 0x400010d0;\nr_ble_ll_is_valid_public_addr = 0x400010d4;\nr_ble_ll_is_valid_random_addr = 0x400010d8;\nr_ble_ll_mbuf_init = 0x400010dc;\nr_ble_ll_misc_options_set = 0x400010e0;\nr_ble_ll_modify_sca = 0x400010e4;\nr_ble_ll_modify_sca_action = 0x400010e8;\nr_ble_ll_pdu_max_tx_octets_get = 0x400010ec;\nr_ble_ll_pdu_tx_time_get = 0x400010f0;\nr_ble_ll_phy_to_phy_mode = 0x400010f4;\nr_ble_ll_qa_enable = 0x400010f8;\nr_ble_ll_rand = 0x400010fc;\nr_ble_ll_rand_data_get = 0x40001100;\nr_ble_ll_rand_deinit = 0x40001104;\nr_ble_ll_rand_env_init = 0x40001108;\nr_ble_ll_rand_init = 0x4000110c;\nr_ble_ll_rand_prand_get = 0x40001110;\nr_ble_ll_rand_sample = 0x40001114;\nr_ble_ll_rand_start = 0x40001118;\nr_ble_ll_read_local_p256_pub_key = 0x4000111c;\nr_ble_ll_read_rf_path_compensation = 0x40001120;\nr_ble_ll_read_supp_features = 0x40001124;\nr_ble_ll_read_supp_states = 0x40001128;\nr_ble_ll_read_tx_power = 0x4000112c;\nr_ble_ll_reset = 0x40001130;\nr_ble_ll_resolv_clear_all_pl_bit = 0x40001134;\nr_ble_ll_resolv_clear_all_wl_bit = 0x40001138;\nr_ble_ll_resolv_deinit = 0x4000113c;\nr_ble_ll_resolv_enable_cmd = 0x40001140;\nr_ble_ll_resolv_enabled = 0x40001144;\nr_ble_ll_resolv_env_init = 0x40001148;\nr_ble_ll_resolv_gen_priv_addr = 0x4000114c;\nr_ble_ll_resolv_gen_rpa = 0x40001150;\nr_ble_ll_resolv_get_addr_pointer = 0x40001154;\nr_ble_ll_resolv_get_index = 0x40001158;\nr_ble_ll_resolv_get_irk_pointer = 0x4000115c;\nr_ble_ll_resolv_get_list = 0x40001160;\nr_ble_ll_resolv_get_priv_addr = 0x40001164;\nr_ble_ll_resolv_get_rpa_tmo = 0x40001168;\nr_ble_ll_resolv_init = 0x4000116c;\nr_ble_ll_resolv_irk_nonzero = 0x40001170;\nr_ble_ll_resolv_list_add = 0x40001174;\nr_ble_ll_resolv_list_chg_allowed = 0x40001178;\nr_ble_ll_resolv_list_clr = 0x4000117c;\nr_ble_ll_resolv_list_find = 0x40001180;\nr_ble_ll_resolv_list_read_size = 0x40001184;\nr_ble_ll_resolv_list_reset = 0x40001188;\nr_ble_ll_resolv_list_rmv = 0x4000118c;\nr_ble_ll_resolv_local_addr_rd = 0x40001190;\nr_ble_ll_resolv_peer_addr_rd = 0x40001194;\nr_ble_ll_resolv_peer_rpa_any = 0x40001198;\nr_ble_ll_resolv_reset = 0x4000119c;\nr_ble_ll_resolv_rpa = 0x400011a0;\nr_ble_ll_resolv_rpa_timer_cb = 0x400011a4;\nr_ble_ll_resolv_set_local_rpa = 0x400011a8;\nr_ble_ll_resolv_set_peer_rpa = 0x400011ac;\nr_ble_ll_resolv_set_rpa_tmo = 0x400011b0;\nr_ble_ll_resolve_set_priv_mode = 0x400011b4;\nr_ble_ll_rxpdu_alloc = 0x400011b8;\nr_ble_ll_scan_add_scan_rsp_adv = 0x400011bc;\nr_ble_ll_scan_adv_decode_addr = 0x400011c0;\nr_ble_ll_scan_aux_data_ref = 0x400011c4;\nr_ble_ll_scan_aux_data_unref = 0x400011c8;\nr_ble_ll_scan_can_chg_whitelist = 0x400011cc;\nr_ble_ll_scan_check_periodic_sync = 0x400011d0;\nr_ble_ll_scan_classify_filter_aux_init = 0x400011d4;\nr_ble_ll_scan_classify_filter_init = 0x400011d8;\nr_ble_ll_scan_common_init = 0x400011dc;\nr_ble_ll_scan_continue_en = 0x400011e0;\nr_ble_ll_scan_deinit = 0x400011e4;\nr_ble_ll_scan_dup_check_ext = 0x400011e8;\nr_ble_ll_scan_dup_check_legacy = 0x400011ec;\nr_ble_ll_scan_dup_move_to_head = 0x400011f0;\nr_ble_ll_scan_dup_new = 0x400011f4;\nr_ble_ll_scan_dup_update_ext = 0x400011f8;\nr_ble_ll_scan_dup_update_legacy = 0x400011fc;\nr_ble_ll_scan_enabled = 0x40001200;\nr_ble_ll_scan_end_adv_evt = 0x40001204;\nr_ble_ll_scan_env_init = 0x40001208;\nr_ble_ll_scan_ext_initiator_start = 0x4000120c;\nr_ble_ll_scan_get_addr_data_from_legacy = 0x40001210;\nr_ble_ll_scan_get_addr_from_ext_adv = 0x40001214;\nr_ble_ll_scan_get_cur_sm = 0x40001218;\nr_ble_ll_scan_get_ext_adv_report = 0x4000121c;\nr_ble_ll_scan_get_local_rpa = 0x40001220;\nr_ble_ll_scan_get_next_adv_prim_chan = 0x40001224;\nr_ble_ll_scan_get_peer_rpa = 0x40001228;\nr_ble_ll_scan_have_rxd_scan_rsp = 0x4000122c;\nr_ble_ll_scan_init = 0x40001230;\nr_ble_ll_scan_initiator_start = 0x40001234;\nr_ble_ll_scan_is_inside_window = 0x40001238;\nr_ble_ll_scan_move_window_to = 0x4000123c;\nr_ble_ll_scan_npl_reset = 0x40001240;\nr_ble_ll_scan_parse_auxptr = 0x40001244;\nr_ble_ll_scan_parse_ext_hdr = 0x40001248;\nr_ble_ll_scan_pre_process = 0x4000124c;\nr_ble_ll_scan_record_new_adv = 0x40001250;\nr_ble_ll_scan_refresh_nrpa = 0x40001254;\nr_ble_ll_scan_reset = 0x40001258;\nr_ble_ll_scan_rx_pkt_in = 0x4000125c;\nr_ble_ll_scan_rx_pkt_in_on_aux = 0x40001260;\nr_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001264;\nr_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268;\nr_ble_ll_scan_rxed = 0x4000126c;\nr_ble_ll_scan_send_adv_report = 0x40001270;\nr_ble_ll_scan_send_truncated = 0x40001274;\nr_ble_ll_scan_set_enable = 0x40001278;\nr_ble_ll_scan_set_peer_rpa = 0x4000127c;\nr_ble_ll_scan_set_perfer_addr = 0x40001280;\nr_ble_ll_scan_set_scan_params = 0x40001284;\nr_ble_ll_scan_sm_start = 0x40001288;\nr_ble_ll_scan_sm_stop = 0x4000128c;\nr_ble_ll_scan_time_hci_to_ticks = 0x40001290;\nr_ble_ll_scan_update_aux_data = 0x40001294;\nr_ble_ll_scan_whitelist_enabled = 0x40001298;\nr_ble_ll_set_default_privacy_mode = 0x4000129c;\nr_ble_ll_set_default_sync_transfer_params = 0x400012a0;\nr_ble_ll_set_ext_scan_params = 0x400012a4;\nr_ble_ll_set_host_feat = 0x400012a8;\nr_ble_ll_set_public_addr = 0x400012ac;\nr_ble_ll_set_random_addr = 0x400012b0;\nr_ble_ll_set_sync_transfer_params = 0x400012b4;\nr_ble_ll_state_get = 0x400012b8;\nr_ble_ll_state_set = 0x400012bc;\nr_ble_ll_sync_adjust_ext_hdr = 0x400012c0;\nr_ble_ll_sync_cancel = 0x400012c4;\nr_ble_ll_sync_cancel_complete_event = 0x400012c8;\nr_ble_ll_sync_check_acad = 0x400012cc;\nr_ble_ll_sync_check_failed = 0x400012d0;\nr_ble_ll_sync_create = 0x400012d4;\nr_ble_ll_sync_deinit = 0x400012d8;\nr_ble_ll_sync_enabled = 0x400012dc;\nr_ble_ll_sync_env_init = 0x400012e0;\nr_ble_ll_sync_est_event_failed = 0x400012e4;\nr_ble_ll_sync_est_event_success = 0x400012e8;\nr_ble_ll_sync_established = 0x400012ec;\nr_ble_ll_sync_filter_enabled = 0x400012f0;\nr_ble_ll_sync_find = 0x400012f4;\nr_ble_ll_sync_get_cur_sm = 0x400012f8;\nr_ble_ll_sync_get_handle = 0x400012fc;\nr_ble_ll_sync_get_sm = 0x40001300;\nr_ble_ll_sync_info_event = 0x40001304;\nr_ble_ll_sync_init = 0x40001308;\nr_ble_ll_sync_list_add = 0x4000130c;\nr_ble_ll_sync_list_clear = 0x40001310;\nr_ble_ll_sync_list_empty = 0x40001314;\nr_ble_ll_sync_list_get_free = 0x40001318;\nr_ble_ll_sync_list_remove = 0x4000131c;\nr_ble_ll_sync_list_search = 0x40001320;\nr_ble_ll_sync_list_size = 0x40001324;\nr_ble_ll_sync_lost_event = 0x40001328;\nr_ble_ll_sync_next_event = 0x4000132c;\nr_ble_ll_sync_on_list = 0x40001330;\nr_ble_ll_sync_parse_ext_hdr = 0x40001334;\nr_ble_ll_sync_periodic_ind = 0x40001338;\nr_ble_ll_sync_phy_mode_to_aux_phy = 0x4000133c;\nr_ble_ll_sync_phy_mode_to_hci = 0x40001340;\nr_ble_ll_sync_put_syncinfo = 0x40001344;\nr_ble_ll_sync_receive_enable = 0x40001348;\nr_ble_ll_sync_reserve = 0x4000134c;\nr_ble_ll_sync_reset = 0x40001350;\nr_ble_ll_sync_reset_sm = 0x40001354;\nr_ble_ll_sync_rx_pkt_in = 0x40001358;\nr_ble_ll_sync_send_per_adv_rpt = 0x4000135c;\nr_ble_ll_sync_send_sync_ind = 0x40001360;\nr_ble_ll_sync_send_truncated_per_adv_rpt = 0x40001364;\nr_ble_ll_sync_sm_clear = 0x40001368;\nr_ble_ll_sync_terminate = 0x4000136c;\nr_ble_ll_sync_transfer = 0x40001370;\nr_ble_ll_sync_transfer_get = 0x40001374;\nr_ble_ll_sync_transfer_received = 0x40001378;\nr_ble_ll_task = 0x4000137c;\nr_ble_ll_trace_set_func = 0x40001380;\nr_ble_ll_trace_u32 = 0x40001384;\nr_ble_ll_trace_u32x2 = 0x40001388;\nr_ble_ll_trace_u32x3 = 0x4000138c;\nr_ble_ll_tx_flat_mbuf_pducb = 0x40001390;\nr_ble_ll_tx_mbuf_pducb = 0x40001394;\nr_ble_ll_tx_pkt_in = 0x40001398;\nr_ble_ll_update_max_tx_octets_phy_mode = 0x4000139c;\nr_ble_ll_usecs_to_ticks_round_up = 0x400013a0;\nr_ble_ll_utils_calc_access_addr = 0x400013a4;\nr_ble_ll_utils_calc_dci_csa2 = 0x400013a8;\nr_ble_ll_utils_calc_num_used_chans = 0x400013ac;\nr_ble_ll_utils_calc_window_widening = 0x400013b0;\nr_ble_ll_utils_csa2_perm = 0x400013b4;\nr_ble_ll_utils_csa2_prng = 0x400013b8;\nr_ble_ll_utils_remapped_channel = 0x400013bc;\nr_ble_ll_whitelist_add = 0x400013c0;\nr_ble_ll_whitelist_chg_allowed = 0x400013c4;\nr_ble_ll_whitelist_clear = 0x400013c8;\nr_ble_ll_whitelist_read_size = 0x400013cc;\nr_ble_ll_whitelist_rmv = 0x400013d0;\nr_ble_ll_whitelist_search = 0x400013d4;\nr_ble_ll_write_rf_path_compensation = 0x400013d8;\nr_ble_lll_adv_aux_scannable_pdu_payload_len = 0x400013dc;\nr_ble_lll_adv_aux_schedule = 0x400013e0;\nr_ble_lll_adv_aux_schedule_first = 0x400013e4;\nr_ble_lll_adv_aux_schedule_next = 0x400013e8;\nr_ble_lll_adv_aux_scheduled = 0x400013ec;\nr_ble_lll_adv_aux_set_start_time = 0x400013f0;\nr_ble_lll_adv_coex_dpc_calc_pti_update_itvl = 0x400013f4;\nr_ble_lll_adv_coex_dpc_process_pri = 0x400013f8;\nr_ble_lll_adv_coex_dpc_process_sec = 0x400013fc;\nr_ble_lll_adv_coex_dpc_pti_get = 0x40001400;\nr_ble_lll_adv_coex_dpc_update = 0x40001404;\nr_ble_lll_adv_coex_dpc_update_on_adv_start = 0x40001408;\nr_ble_lll_adv_coex_dpc_update_on_aux_scheduled = 0x4000140c;\nr_ble_lll_adv_coex_dpc_update_on_data_updated = 0x40001410;\nr_ble_lll_adv_coex_dpc_update_on_event_end = 0x40001414;\nr_ble_lll_adv_coex_dpc_update_on_event_scheduled = 0x40001418;\nr_ble_lll_adv_done = 0x4000141c;\nr_ble_lll_adv_drop_event = 0x40001420;\nr_ble_lll_adv_event_done = 0x40001424;\nr_ble_lll_adv_event_rmvd_from_sched = 0x40001428;\nr_ble_lll_adv_ext_estimate_data_itvl = 0x4000142c;\nr_ble_lll_adv_get_sec_pdu_len = 0x40001430;\nr_ble_lll_adv_halt = 0x40001434;\nr_ble_lll_adv_make_done = 0x40001438;\nr_ble_lll_adv_periodic_done = 0x4000143c;\nr_ble_lll_adv_periodic_event_done = 0x40001440;\nr_ble_lll_adv_periodic_rmvd_from_sched = 0x40001444;\nr_ble_lll_adv_periodic_schedule_first = 0x40001448;\nr_ble_lll_adv_periodic_schedule_next = 0x4000144c;\nr_ble_lll_adv_periodic_start = 0x40001450;\nr_ble_lll_adv_periodic_stop = 0x40001454;\nr_ble_lll_adv_pri_schedule_tx_pdu = 0x40001458;\nr_ble_lll_adv_reschedule_event = 0x4000145c;\nr_ble_lll_adv_reschedule_periodic_event = 0x40001460;\nr_ble_lll_adv_rx_pkt_isr = 0x40001464;\nr_ble_lll_adv_sec_done = 0x40001468;\nr_ble_lll_adv_sec_event_done = 0x4000146c;\nr_ble_lll_adv_sec_schedule_next_aux = 0x40001470;\nr_ble_lll_adv_secondary_tx_start_cb = 0x40001474;\nr_ble_lll_adv_sm_deinit = 0x40001478;\nr_ble_lll_adv_sm_event_init = 0x4000147c;\nr_ble_lll_adv_sm_event_restore = 0x40001480;\nr_ble_lll_adv_sm_event_store = 0x40001484;\nr_ble_lll_adv_sm_init = 0x40001488;\nr_ble_lll_adv_sm_reset = 0x4000148c;\nr_ble_lll_adv_start = 0x40001490;\nr_ble_lll_adv_stop = 0x40001494;\nr_ble_lll_adv_sync_next_scheduled = 0x40001498;\nr_ble_lll_adv_sync_schedule = 0x4000149c;\nr_ble_lll_adv_sync_tx_done = 0x400014a0;\nr_ble_lll_adv_sync_tx_end = 0x400014a4;\nr_ble_lll_adv_sync_tx_start_cb = 0x400014a8;\nr_ble_lll_adv_tx_done = 0x400014ac;\nr_ble_lll_adv_tx_start_cb = 0x400014b0;\nr_ble_lll_adv_update_rsp_offset = 0x400014b4;\nr_ble_lll_aux_scan_cb = 0x400014b8;\nr_ble_lll_aux_scan_drop = 0x400014bc;\nr_ble_lll_aux_scan_drop_event_cb = 0x400014c0;\nr_ble_lll_calc_us_convert_tick_unit = 0x400014c4;\nr_ble_lll_conn_append_tx_buffer = 0x400014c8;\nr_ble_lll_conn_can_send_next_pdu = 0x400014cc;\nr_ble_lll_conn_check_opcode_matched = 0x400014d0;\nr_ble_lll_conn_coex_dpc_process = 0x400014d4;\nr_ble_lll_conn_coex_dpc_pti_get = 0x400014d8;\nr_ble_lll_conn_coex_dpc_update = 0x400014dc;\nr_ble_lll_conn_coex_dpc_update_on_event_end = 0x400014e0;\nr_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4;\nr_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8;\nr_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec;\nr_ble_lll_conn_cth_flow_free_credit = 0x400014f0;\nr_ble_lll_conn_current_sm_over = 0x400014f4;\nr_ble_lll_conn_end = 0x400014f8;\nr_ble_lll_conn_env_deinit = 0x400014fc;\nr_ble_lll_conn_env_init = 0x40001500;\nr_ble_lll_conn_event_end = 0x40001504;\nr_ble_lll_conn_event_end_timer_cb = 0x40001508;\nr_ble_lll_conn_event_halt = 0x4000150c;\nr_ble_lll_conn_event_is_over = 0x40001510;\nr_ble_lll_conn_event_start_cb = 0x40001514;\nr_ble_lll_conn_free_rx_mbuf = 0x40001518;\nr_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c;\nr_ble_lll_conn_get_ce_end_time = 0x40001520;\nr_ble_lll_conn_get_next_sched_time = 0x40001524;\nr_ble_lll_conn_get_rx_mbuf = 0x40001528;\nr_ble_lll_conn_halt = 0x4000152c;\nr_ble_lll_conn_master_common_init = 0x40001530;\nr_ble_lll_conn_master_new = 0x40001534;\nr_ble_lll_conn_module_deinit = 0x40001538;\nr_ble_lll_conn_module_init = 0x4000153c;\nr_ble_lll_conn_module_reset = 0x40001540;\nr_ble_lll_conn_no_mem_evt_pre_cb = 0x40001544;\nr_ble_lll_conn_pre_process = 0x40001548;\nr_ble_lll_conn_process_acked_pdu = 0x4000154c;\nr_ble_lll_conn_process_in_isr = 0x40001550;\nr_ble_lll_conn_recv_ack = 0x40001554;\nr_ble_lll_conn_recv_valid_packet = 0x40001558;\nr_ble_lll_conn_reset_pending_sched = 0x4000155c;\nr_ble_lll_conn_rx_pkt_isr = 0x40001560;\nr_ble_lll_conn_sched_next_anchor = 0x40001564;\nr_ble_lll_conn_sched_next_event = 0x40001568;\nr_ble_lll_conn_set_slave_flow_control = 0x4000156c;\nr_ble_lll_conn_slave_new = 0x40001570;\nr_ble_lll_conn_sm_new = 0x40001574;\nr_ble_lll_conn_sm_npl_deinit = 0x40001578;\nr_ble_lll_conn_sm_npl_init = 0x4000157c;\nr_ble_lll_conn_superversion_timer_cb = 0x40001580;\nr_ble_lll_conn_timeout = 0x40001584;\nr_ble_lll_conn_update_anchor = 0x40001588;\nr_ble_lll_conn_update_conn_ind_params = 0x4000158c;\nr_ble_lll_conn_update_encryption = 0x40001590;\nr_ble_lll_conn_update_tx_buffer = 0x40001594;\nr_ble_lll_deinit = 0x40001598;\nr_ble_lll_dtm_calculate_itvl = 0x4000159c;\nr_ble_lll_dtm_ctx_free = 0x400015a0;\nr_ble_lll_dtm_deinit = 0x400015a4;\nr_ble_lll_dtm_end_test = 0x400015a8;\nr_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;\nr_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;\nr_ble_lll_dtm_init = 0x400015b4;\nr_ble_lll_dtm_reset = 0x400015b8;\nr_ble_lll_dtm_rx_create_ctx = 0x400015bc;\nr_ble_lll_dtm_rx_isr_end = 0x400015c0;\nr_ble_lll_dtm_rx_isr_start = 0x400015c4;\nr_ble_lll_dtm_rx_pkt_in = 0x400015c8;\nr_ble_lll_dtm_rx_sched_cb = 0x400015cc;\nr_ble_lll_dtm_rx_start = 0x400015d0;\nr_ble_lll_dtm_rx_test = 0x400015d4;\nr_ble_lll_dtm_set_next = 0x400015d8;\nr_ble_lll_dtm_tx_create_ctx = 0x400015dc;\nr_ble_lll_dtm_tx_done = 0x400015e0;\nr_ble_lll_dtm_tx_sched_cb = 0x400015e4;\nr_ble_lll_dtm_tx_test = 0x400015e8;\nr_ble_lll_dtm_wfr_timer_exp = 0x400015ec;\nr_ble_lll_event_rx_pkt = 0x400015f0;\nr_ble_lll_ext_scan_coex_dpc_process = 0x400015f4;\nr_ble_lll_ext_scan_coex_dpc_pti_get = 0x400015f8;\nr_ble_lll_ext_scan_coex_dpc_update = 0x400015fc;\nr_ble_lll_ext_scan_coex_dpc_update_on_start = 0x40001600;\nr_ble_lll_hci_dtm_rx_test = 0x40001604;\nr_ble_lll_hci_dtm_rx_test_v2 = 0x40001608;\nr_ble_lll_hci_dtm_tx_test = 0x4000160c;\nr_ble_lll_hci_dtm_tx_test_ext = 0x40001610;\nr_ble_lll_hci_dtm_tx_test_v2 = 0x40001614;\nr_ble_lll_hci_dtm_tx_test_v2_ext = 0x40001618;\nr_ble_lll_init = 0x4000161c;\nr_ble_lll_init_pre_process = 0x40001620;\nr_ble_lll_init_rx_pkt_isr = 0x40001624;\nr_ble_lll_per_adv_coex_dpc_calc_pti_update_itvl = 0x40001628;\nr_ble_lll_per_adv_coex_dpc_process = 0x4000162c;\nr_ble_lll_per_adv_coex_dpc_pti_get = 0x40001630;\nr_ble_lll_per_adv_coex_dpc_update = 0x40001634;\nr_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638;\nr_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c;\nr_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640;\nr_ble_lll_reset = 0x40001644;\nr_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;\nr_ble_lll_rfmgmt_deinit = 0x4000164c;\nr_ble_lll_rfmgmt_disable = 0x40001650;\nr_ble_lll_rfmgmt_enable = 0x40001654;\nr_ble_lll_rfmgmt_enable_now = 0x40001658;\nr_ble_lll_rfmgmt_init = 0x4000165c;\nr_ble_lll_rfmgmt_is_enabled = 0x40001660;\nr_ble_lll_rfmgmt_release = 0x40001664;\nr_ble_lll_rfmgmt_release_ev = 0x40001668;\nr_ble_lll_rfmgmt_reset = 0x4000166c;\nr_ble_lll_rfmgmt_scan_changed = 0x40001670;\nr_ble_lll_rfmgmt_sched_changed = 0x40001674;\nr_ble_lll_rfmgmt_set_sleep_cb = 0x40001678;\nr_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c;\nr_ble_lll_rfmgmt_timer_exp = 0x40001680;\nr_ble_lll_rfmgmt_timer_reschedule = 0x40001684;\nr_ble_lll_rx_pdu_in = 0x40001688;\nr_ble_lll_rx_pkt_in = 0x4000168c;\nr_ble_lll_rx_pkt_isr = 0x40001690;\nr_ble_lll_scan_abort_aux_sched = 0x40001694;\nr_ble_lll_scan_aux_data_free = 0x40001698;\nr_ble_lll_scan_chk_resume = 0x4000169c;\nr_ble_lll_scan_clean_cur_aux_data = 0x400016a0;\nr_ble_lll_scan_coex_event_cb = 0x400016a4;\nr_ble_lll_scan_common_init = 0x400016a8;\nr_ble_lll_scan_deinit = 0x400016ac;\nr_ble_lll_scan_duration_period_timers_restart = 0x400016b0;\nr_ble_lll_scan_duration_period_timers_stop = 0x400016b4;\nr_ble_lll_scan_duration_timer_cb = 0x400016b8;\nr_ble_lll_scan_event_proc = 0x400016bc;\nr_ble_lll_scan_ext_adv_init = 0x400016c0;\nr_ble_lll_scan_halt = 0x400016c4;\nr_ble_lll_scan_has_sent_scan_req = 0x400016c8;\nr_ble_lll_scan_init = 0x400016cc;\nr_ble_lll_scan_npl_init = 0x400016d0;\nr_ble_lll_scan_npl_reset = 0x400016d4;\nr_ble_lll_scan_npl_restore = 0x400016d8;\nr_ble_lll_scan_npl_store = 0x400016dc;\nr_ble_lll_scan_period_timer_cb = 0x400016e0;\nr_ble_lll_scan_process_adv_in_isr = 0x400016e4;\nr_ble_lll_scan_process_rsp_in_isr = 0x400016e8;\nr_ble_lll_scan_req_backoff = 0x400016ec;\nr_ble_lll_scan_restart = 0x400016f0;\nr_ble_lll_scan_rx_isr_on_aux = 0x400016f4;\nr_ble_lll_scan_rx_isr_on_legacy = 0x400016f8;\nr_ble_lll_scan_rx_pkt_isr = 0x400016fc;\nr_ble_lll_scan_sched_next_aux = 0x40001700;\nr_ble_lll_scan_sched_remove = 0x40001704;\nr_ble_lll_scan_start = 0x40001708;\nr_ble_lll_scan_start_rx = 0x4000170c;\nr_ble_lll_scan_stop = 0x40001710;\nr_ble_lll_scan_targeta_is_matched = 0x40001714;\nr_ble_lll_scan_timer_cb = 0x40001718;\nr_ble_lll_sched_adv_new = 0x4000171c;\nr_ble_lll_sched_adv_resched_pdu = 0x40001720;\nr_ble_lll_sched_adv_reschedule = 0x40001724;\nr_ble_lll_sched_aux_scan = 0x40001728;\nr_ble_lll_sched_conn_overlap = 0x4000172c;\nr_ble_lll_sched_conn_reschedule = 0x40001730;\nr_ble_lll_sched_deinit = 0x40001734;\nr_ble_lll_sched_dtm = 0x40001738;\nr_ble_lll_sched_env_init = 0x4000173c;\nr_ble_lll_sched_execute_check = 0x40001740;\nr_ble_lll_sched_execute_item = 0x40001744;\nr_ble_lll_sched_init = 0x40001748;\nr_ble_lll_sched_insert_if_empty = 0x4000174c;\nr_ble_lll_sched_is_overlap = 0x40001750;\nr_ble_lll_sched_master_new = 0x40001754;\nr_ble_lll_sched_next_time = 0x40001758;\nr_ble_lll_sched_overlaps_current = 0x4000175c;\nr_ble_lll_sched_periodic_adv = 0x40001760;\nr_ble_lll_sched_rmv_elem = 0x40001764;\nr_ble_lll_sched_rmv_elem_type = 0x40001768;\nr_ble_lll_sched_run = 0x4000176c;\nr_ble_lll_sched_scan_req_over_aux_ptr = 0x40001770;\nr_ble_lll_sched_slave_new = 0x40001774;\nr_ble_lll_sched_stop = 0x40001778;\nr_ble_lll_sched_sync = 0x4000177c;\nr_ble_lll_sched_sync_overlaps_current = 0x40001780;\nr_ble_lll_sched_sync_reschedule = 0x40001784;\nr_ble_lll_sync_chain_start_cb = 0x40001788;\nr_ble_lll_sync_coex_dpc_process = 0x4000178c;\nr_ble_lll_sync_coex_dpc_pti_get = 0x40001790;\nr_ble_lll_sync_coex_dpc_update = 0x40001794;\nr_ble_lll_sync_current_sm_over = 0x40001798;\nr_ble_lll_sync_deinit = 0x4000179c;\nr_ble_lll_sync_event_end = 0x400017a0;\nr_ble_lll_sync_event_end_cb = 0x400017a4;\nr_ble_lll_sync_event_start_cb = 0x400017a8;\nr_ble_lll_sync_get_event_end_time = 0x400017ac;\nr_ble_lll_sync_halt = 0x400017b0;\nr_ble_lll_sync_init = 0x400017b4;\nr_ble_lll_sync_new = 0x400017b8;\nr_ble_lll_sync_reset = 0x400017bc;\nr_ble_lll_sync_reset_sm = 0x400017c0;\nr_ble_lll_sync_rmvd_from_sched = 0x400017c4;\nr_ble_lll_sync_rx_pkt_isr = 0x400017c8;\nr_ble_lll_sync_schedule_chain = 0x400017cc;\nr_ble_lll_sync_stop = 0x400017d0;\nr_ble_lll_sync_trnasfer_sched = 0x400017d4;\nr_ble_phy_access_addr_get = 0x400017d8;\nr_ble_phy_calculate_rxtx_ifs = 0x400017dc;\nr_ble_phy_calculate_rxwindow = 0x400017e0;\nr_ble_phy_calculate_txrx_ifs = 0x400017e4;\nr_ble_phy_check_bb_status = 0x400017e8;\nr_ble_phy_complete_rx_info = 0x400017ec;\nr_ble_phy_config_access_addr = 0x400017f0;\nr_ble_phy_data_make = 0x400017f4;\nr_ble_phy_disable = 0x400017f8;\nr_ble_phy_disable_irq = 0x400017fc;\nr_ble_phy_disable_whitening = 0x40001800;\nr_ble_phy_enable_whitening = 0x40001804;\nr_ble_phy_encrypt_disable = 0x40001808;\nr_ble_phy_env_init = 0x4000180c;\nr_ble_phy_get_current_phy = 0x40001810;\nr_ble_phy_get_packet_counter = 0x40001814;\nr_ble_phy_get_packet_status = 0x40001818;\nr_ble_phy_get_pyld_time_offset = 0x4000181c;\nr_ble_phy_get_rx_phy_mode = 0x40001820;\nr_ble_phy_get_seq_end_st = 0x40001824;\nr_ble_phy_init = 0x40001828;\nr_ble_phy_isr = 0x4000182c;\nr_ble_phy_max_data_pdu_pyld = 0x40001830;\nr_ble_phy_mode_config = 0x40001834;\nr_ble_phy_mode_convert = 0x40001838;\nr_ble_phy_mode_write = 0x4000183c;\nr_ble_phy_module_deinit = 0x40001840;\nr_ble_phy_module_init = 0x40001844;\nr_ble_phy_monitor_bb_sync = 0x40001848;\nr_ble_phy_reset_bb_monitor = 0x4000184c;\nr_ble_phy_resolv_list_disable = 0x40001850;\nr_ble_phy_resolv_list_enable = 0x40001854;\nr_ble_phy_restart_sequence = 0x40001858;\nr_ble_phy_rx_set_start_time_forcibly = 0x4000185c;\nr_ble_phy_rxpdu_copy = 0x40001860;\nr_ble_phy_seq_encrypt_enable = 0x40001864;\nr_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001868;\nr_ble_phy_sequence_end_isr = 0x4000186c;\nr_ble_phy_sequence_get_mode = 0x40001870;\nr_ble_phy_sequence_is_running = 0x40001874;\nr_ble_phy_sequence_is_waiting_rsp = 0x40001878;\nr_ble_phy_sequence_single_end = 0x4000187c;\nr_ble_phy_sequence_tx_end_invoke = 0x40001880;\nr_ble_phy_sequence_update_conn_ind_params = 0x40001884;\nr_ble_phy_set_adv_mode = 0x40001888;\nr_ble_phy_set_coex_pti = 0x4000188c;\nr_ble_phy_set_conn_ind_pdu = 0x40001890;\nr_ble_phy_set_conn_mode = 0x40001894;\nr_ble_phy_set_dev_address = 0x40001898;\nr_ble_phy_set_rx_pwr_compensation = 0x4000189c;\nr_ble_phy_set_rxhdr = 0x400018a0;\nr_ble_phy_set_scan_mode = 0x400018a4;\nr_ble_phy_set_sequence_mode = 0x400018a8;\nr_ble_phy_set_single_packet_rx_sequence = 0x400018ac;\nr_ble_phy_set_single_packet_tx_sequence = 0x400018b0;\nr_ble_phy_set_tx_rx_transition = 0x400018b4;\nr_ble_phy_set_txend_cb = 0x400018b8;\nr_ble_phy_setchan = 0x400018bc;\nr_ble_phy_start_rx_immediately = 0x400018c0;\nr_ble_phy_state_get = 0x400018c4;\nr_ble_phy_timer_config_start_time = 0x400018c8;\nr_ble_phy_timer_start_now = 0x400018cc;\nr_ble_phy_timer_stop = 0x400018d0;\nr_ble_phy_tx_set_start_time = 0x400018d4;\nr_ble_phy_txpower_round = 0x400018d8;\nr_ble_phy_txpwr_set = 0x400018dc;\nr_ble_phy_update_conn_sequence = 0x400018e0;\nr_ble_phy_update_encryption = 0x400018e4;\nr_ble_phy_update_ifs = 0x400018e8;\nr_ble_phy_xcvr_state_get = 0x400018ec;\nr_ble_plf_set_log_level = 0x400018f0;\nr_ble_rtc_wake_up_cpu_init = 0x400018f4;\nr_ble_rtc_wake_up_state_clr = 0x400018f8;\nr_ble_vendor_hci_register = 0x400018fc;\nr_bt_rf_coex_cfg_set = 0x40001900;\nr_bt_rf_coex_coded_txrx_time_upper_lim = 0x40001904;\nr_bt_rf_coex_dft_pti_set = 0x40001908;\nr_bt_rf_coex_hook_deinit = 0x4000190c;\nr_bt_rf_coex_hook_init = 0x40001910;\nr_bt_rf_coex_hook_st_set = 0x40001914;\nr_bt_rf_coex_hooks_p_set_default = 0x40001918;\nr_btdm_disable_adv_delay = 0x4000191c;\nr_btdm_switch_phy_coded = 0x40001920;\nr_esp_wait_disabled = 0x40001924;\nr_get_be16 = 0x40001928;\nr_get_be24 = 0x4000192c;\nr_get_be32 = 0x40001930;\nr_get_be64 = 0x40001934;\nr_get_le16 = 0x40001938;\nr_get_le24 = 0x4000193c;\nr_get_le32 = 0x40001940;\nr_get_le64 = 0x40001944;\nr_get_local_irk_offset = 0x40001948;\nr_get_local_rpa_offset = 0x4000194c;\nr_get_max_skip = 0x40001950;\nr_get_peer_id_offset = 0x40001954;\nr_get_peer_irk_offset = 0x40001958;\nr_get_peer_rpa_offset = 0x4000195c;\nr_hal_rtc_intr_init = 0x40001960;\nr_hal_rtc_irq_handler = 0x40001964;\nr_hal_timer_deinit = 0x40001968;\nr_hal_timer_disable_irq = 0x4000196c;\nr_hal_timer_env_init = 0x40001970;\nr_hal_timer_init = 0x40001974;\nr_hal_timer_process = 0x40001978;\nr_hal_timer_read = 0x4000197c;\nr_hal_timer_read_tick = 0x40001980;\nr_hal_timer_set_cb = 0x40001984;\nr_hal_timer_set_exp_tick = 0x40001988;\nr_hal_timer_start = 0x4000198c;\nr_hal_timer_start_at = 0x40001990;\nr_hal_timer_stop = 0x40001994;\nr_hal_timer_task_start = 0x40001998;\nr_ll_assert = 0x4000199c;\nr_mem_init_mbuf_pool = 0x400019a0;\nr_mem_malloc_mbuf_pool = 0x400019a4;\nr_mem_malloc_mbufpkt_pool = 0x400019a8;\nr_mem_malloc_mempool = 0x400019ac;\nr_mem_malloc_mempool_ext = 0x400019b0;\nr_mem_malloc_mempool_gen = 0x400019b4;\nr_mem_pullup_obj = 0x400019b8;\nr_mem_split_frag = 0x400019bc;\nr_os_cputime_get32 = 0x400019c0;\nr_os_cputime_ticks_to_usecs = 0x400019c4;\nr_os_cputime_timer_init = 0x400019c8;\nr_os_cputime_timer_relative = 0x400019cc;\nr_os_cputime_timer_start = 0x400019d0;\nr_os_cputime_timer_stop = 0x400019d4;\nr_os_cputime_usecs_to_ticks = 0x400019d8;\nr_os_mbuf_adj = 0x400019dc;\nr_os_mbuf_append = 0x400019e0;\nr_os_mbuf_appendfrom = 0x400019e4;\nr_os_mbuf_cmpf = 0x400019e8;\nr_os_mbuf_cmpm = 0x400019ec;\nr_os_mbuf_concat = 0x400019f0;\nr_os_mbuf_copydata = 0x400019f4;\nr_os_mbuf_copyinto = 0x400019f8;\nr_os_mbuf_dup = 0x400019fc;\nr_os_mbuf_extend = 0x40001a00;\nr_os_mbuf_free = 0x40001a04;\nr_os_mbuf_free_chain = 0x40001a08;\nr_os_mbuf_get = 0x40001a0c;\nr_os_mbuf_get_pkthdr = 0x40001a10;\nr_os_mbuf_leadingspace = 0x40001a14;\nr_os_mbuf_len = 0x40001a18;\nr_os_mbuf_off = 0x40001a1c;\nr_os_mbuf_pack_chains = 0x40001a20;\nr_os_mbuf_pool_init = 0x40001a24;\nr_os_mbuf_prepend = 0x40001a28;\nr_os_mbuf_prepend_pullup = 0x40001a2c;\nr_os_mbuf_pullup = 0x40001a30;\nr_os_mbuf_trailingspace = 0x40001a34;\nr_os_mbuf_trim_front = 0x40001a38;\nr_os_mbuf_widen = 0x40001a3c;\nr_os_memblock_from = 0x40001a40;\nr_os_memblock_get = 0x40001a44;\nr_os_memblock_put = 0x40001a48;\nr_os_memblock_put_from_cb = 0x40001a4c;\nr_os_mempool_clear = 0x40001a50;\nr_os_mempool_ext_clear = 0x40001a54;\nr_os_mempool_ext_init = 0x40001a58;\nr_os_mempool_info_get_next = 0x40001a5c;\nr_os_mempool_init = 0x40001a60;\nr_os_mempool_init_internal = 0x40001a64;\nr_os_mempool_is_sane = 0x40001a68;\nr_os_mempool_module_init = 0x40001a6c;\nr_os_mempool_unregister = 0x40001a70;\nr_os_mqueue_get = 0x40001a74;\nr_os_mqueue_init = 0x40001a78;\nr_os_mqueue_put = 0x40001a7c;\nr_os_msys_count = 0x40001a80;\nr_os_msys_get = 0x40001a84;\nr_os_msys_get_pkthdr = 0x40001a88;\nr_os_msys_num_free = 0x40001a8c;\nr_os_msys_register = 0x40001a90;\nr_os_msys_reset = 0x40001a94;\nr_pri_phy_valid = 0x40001a98;\nr_put_be16 = 0x40001a9c;\nr_put_be24 = 0x40001aa0;\nr_put_be32 = 0x40001aa4;\nr_put_be64 = 0x40001aa8;\nr_put_le16 = 0x40001aac;\nr_put_le24 = 0x40001ab0;\nr_put_le32 = 0x40001ab4;\nr_put_le64 = 0x40001ab8;\nr_rtc0_timer_handler = 0x40001abc;\nr_sdkconfig_get_opts = 0x40001ac0;\nr_sdkconfig_set_opts = 0x40001ac4;\nr_sec_phy_valid = 0x40001ac8;\nr_swap_buf = 0x40001acc;\nr_swap_in_place = 0x40001ad0;\n\/* Data (.data, .bss, .rodata) *\/\nble_lll_dtm_module_env_p = 0x3fcdffc4;\ng_ble_lll_dtm_prbs15_data = 0x3ff4fee4;\ng_ble_lll_dtm_prbs9_data = 0x3ff4fde4;\ng_channel_rf_to_index = 0x3ff4fdbc;\ng_ble_lll_rfmgmt_data = 0x3fcdff7c;\ng_ble_sleep_enter_cb = 0x3fcdff78;\ng_ble_sleep_exit_cb = 0x3fcdff74;\nble_lll_sched_env_p = 0x3fcdff70;\nble_ll_env_p = 0x3fcdff6c;\ng_ble_ll_pdu_header_tx_time_ro = 0x3ff4fdb4;\nble_ll_adv_env_p = 0x3fcdff68;\nble_ll_conn_env_p = 0x3fcdff64;\nble_ll_conn_required_phy_mask = 0x3ff4fdb0;\nble_ll_valid_conn_phy_mask = 0x3ff4fdaf;\ng_ble_ll_ctrl_pkt_lengths_ro = 0x3ff4fd8c;\nble_ll_hci_env_p = 0x3fcdff60;\ng_debug_le_private_key = 0x3ff4fd6c;\ng_ecc_key = 0x3fcdfefc;\nble_ll_rand_env_p = 0x3fcdfef8;\nble_ll_resolv_env_p = 0x3fcdfef4;\ng_ble_ll_resolve_hdr = 0x3fcdfeec;\ng_device_mode_default = 0x3fcdfe68;\nble_ll_scan_classify_filter_aux_check_cb = 0x3fcdfee8;\nble_ll_scan_classify_filter_check_cb = 0x3fcdfee4;\nble_ll_scan_env_p = 0x3fcdfee0;\ng_ble_ll_supp_cmds_ro = 0x3ff4fd3c;\nble_ll_sync_env_p = 0x3fcdfedc;\ng_ble_sca_ppm_tbl_ro = 0x3ff4fd2c;\npriv_config_opts = 0x3fcdfe48;\nble_hci_uart_reset_cmd = 0x3ff4fd28;\nble_hci_trans_env_p = 0x3fcdfed8;\nble_hci_trans_mode = 0x3fcdfe44;\nble_hci_trans_funcs_ptr = 0x3fcdfed4;\nr_ble_lll_stub_funcs_ptr = 0x3fcdfed0;\nr_ble_stub_funcs_ptr = 0x3fcdfecc;\nr_ext_funcs_p = 0x3fcdfec8;\nr_npl_funcs = 0x3fcdfec4;\nble_hw_env_p = 0x3fcdfec0;\nble_phy_module_env_p = 0x3fcdfebc;\ng_ble_phy_chan_freq_ro = 0x3ff4fd00;\ng_ble_phy_mode_pkt_start_off_ro = 0x3ff4fcf8;\ng_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fce8;\ng_ble_phy_t_rxaddrdelay_ro = 0x3ff4fce4;\ng_ble_phy_t_rxenddelay_ro = 0x3ff4fce0;\ng_ble_phy_t_txdelay_ro = 0x3ff4fcdc;\ng_ble_phy_t_txenddelay_ro = 0x3ff4fcd8;\ng_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcc8;\nhal_timer_env_p = 0x3fcdfeb8;\nr_osi_coex_funcs_p = 0x3fcdfeb4;\nbt_rf_coex_hooks = 0x3fcdfeac;\nbt_rf_coex_hooks_p = 0x3fcdfea8;\ncoex_hook_st_group_tab = 0x3ff4fcbc;\ncoex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcb8;\ns_ble_act_count_by_group = 0x3fcdfea4;\ns_ble_coex_st_map = 0x3fcdfe90;\nbt_rf_coex_cfg_cb = 0x3fcdfe74;\nbt_rf_coex_cfg_p = 0x3fcdfe70;\nbt_rf_coex_cfg_rom = 0x3ff4fc9c;\nbt_rf_coex_pti_dft_p = 0x3fcdfe6c;\nbt_rf_coex_pti_dft_rom = 0x3fcdfe04;\nconn_dynamic_pti_param_rom = 0x3ff4fc84;\nconn_phy_coded_max_data_time_param_rom = 0x3ff4fc80;\next_adv_dynamic_pti_param_rom = 0x3ff4fc4c;\next_scan_dynamic_param_rom = 0x3ff4fc14;\nlegacy_adv_dynamic_pti_param_rom = 0x3ff4fbf4;\nper_adv_dynamic_pti_param_rom = 0x3ff4fbd8;\nsync_dynamic_param_rom = 0x3ff4fbc0;\ng_ble_plf_log_level = 0x3fcdfe00;\ng_msys_pool_list = 0x3fcdfdf8;\ng_os_mempool_list = 0x3fcdfdf0;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x40001ad4;\nRC_GetBlockAckTime = 0x40001ad8;\nebuf_list_remove = 0x40001adc;\nesf_buf_alloc = 0x40001ae0;\nesf_buf_alloc_dynamic = 0x40001ae4;\nesf_buf_recycle = 0x40001ae8;\nGetAccess = 0x40001aec;\nhal_mac_is_low_rate_enabled = 0x40001af0;\nhal_mac_tx_get_blockack = 0x40001af4;\nhal_mac_tx_set_ppdu = 0x40001af8;\nic_get_trc = 0x40001afc;\nic_mac_deinit = 0x40001b00;\nic_mac_init = 0x40001b04;\nic_interface_enabled = 0x40001b08;\nis_lmac_idle = 0x40001b0c;\nlmacAdjustTimestamp = 0x40001b10;\nlmacDiscardAgedMSDU = 0x40001b14;\nlmacDiscardMSDU = 0x40001b18;\nlmacEndFrameExchangeSequence = 0x40001b1c;\nlmacIsIdle = 0x40001b20;\nlmacIsLongFrame = 0x40001b24;\nlmacMSDUAged = 0x40001b28;\nlmacPostTxComplete = 0x40001b2c;\nlmacProcessAllTxTimeout = 0x40001b30;\nlmacProcessCollisions = 0x40001b34;\nlmacProcessRxSucData = 0x40001b38;\nlmacReachLongLimit = 0x40001b3c;\nlmacReachShortLimit = 0x40001b40;\nlmacRecycleMPDU = 0x40001b44;\nlmacRxDone = 0x40001b48;\nlmacSetTxFrame = 0x40001b4c;\nlmacTxDone = 0x40001b50;\nlmacTxFrame = 0x40001b54;\nmac_tx_set_duration = 0x40001b58;\nmac_tx_set_htsig = 0x40001b5c;\nmac_tx_set_plcp0 = 0x40001b60;\nmac_tx_set_plcp1 = 0x40001b64;\nmac_tx_set_plcp2 = 0x40001b68;\npm_check_state = 0x40001b6c;\npm_disable_dream_timer = 0x40001b70;\npm_disable_sleep_delay_timer = 0x40001b74;\npm_dream = 0x40001b78;\npm_mac_wakeup = 0x40001b7c;\npm_mac_sleep = 0x40001b80;\npm_enable_active_timer = 0x40001b84;\npm_enable_sleep_delay_timer = 0x40001b88;\npm_local_tsf_process = 0x40001b8c;\npm_set_beacon_filter = 0x40001b90;\npm_is_in_wifi_slice_threshold = 0x40001b94;\npm_is_waked = 0x40001b98;\npm_keep_alive = 0x40001b9c;\npm_on_beacon_rx = 0x40001ba0;\npm_on_data_rx = 0x40001ba4;\npm_on_tbtt = 0x40001ba8;\npm_parse_beacon = 0x40001bac;\npm_process_tim = 0x40001bb0;\npm_rx_beacon_process = 0x40001bb4;\npm_rx_data_process = 0x40001bb8;\npm_sleep = 0x40001bbc;\npm_sleep_for = 0x40001bc0;\npm_tbtt_process = 0x40001bc4;\nppAMPDU2Normal = 0x40001bc8;\nppAssembleAMPDU = 0x40001bcc;\nppCalFrameTimes = 0x40001bd0;\nppCalSubFrameLength = 0x40001bd4;\nppCalTxAMPDULength = 0x40001bd8;\nppCheckTxAMPDUlength = 0x40001bdc;\nppDequeueRxq_Locked = 0x40001be0;\nppDequeueTxQ = 0x40001be4;\nppEmptyDelimiterLength = 0x40001be8;\nppEnqueueRxq = 0x40001bec;\nppEnqueueTxDone = 0x40001bf0;\nppGetTxQFirstAvail_Locked = 0x40001bf4;\nppGetTxframe = 0x40001bf8;\nppMapTxQueue = 0x40001bfc;\nppProcTxSecFrame = 0x40001c00;\nppProcessRxPktHdr = 0x40001c04;\nppProcessTxQ = 0x40001c08;\nppRecordBarRRC = 0x40001c0c;\nlmacRequestTxopQueue = 0x40001c10;\nlmacReleaseTxopQueue = 0x40001c14;\nppRecycleAmpdu = 0x40001c18;\nppRecycleRxPkt = 0x40001c1c;\nppResortTxAMPDU = 0x40001c20;\nppResumeTxAMPDU = 0x40001c24;\nppRxFragmentProc = 0x40001c28;\nppRxPkt = 0x40001c2c;\nppRxProtoProc = 0x40001c30;\nppSearchTxQueue = 0x40001c34;\nppSearchTxframe = 0x40001c38;\nppSelectNextQueue = 0x40001c3c;\nppSubFromAMPDU = 0x40001c40;\nppTask = 0x40001c44;\nppTxPkt = 0x40001c48;\nppTxProtoProc = 0x40001c4c;\nppTxqUpdateBitmap = 0x40001c50;\npp_coex_tx_request = 0x40001c54;\npp_hdrsize = 0x40001c58;\npp_post = 0x40001c5c;\npp_process_hmac_waiting_txq = 0x40001c60;\nrcGetAmpduSched = 0x40001c64;\nrcUpdateRxDone = 0x40001c68;\nrc_get_trc = 0x40001c6c;\nrc_get_trc_by_index = 0x40001c70;\nrcAmpduLowerRate = 0x40001c74;\nrcampduuprate = 0x40001c78;\nrcClearCurAMPDUSched = 0x40001c7c;\nrcClearCurSched = 0x40001c80;\nrcClearCurStat = 0x40001c84;\nrcGetSched = 0x40001c88;\nrcLowerSched = 0x40001c8c;\nrcSetTxAmpduLimit = 0x40001c90;\nrcTxUpdatePer = 0x40001c94;\nrcUpdateAckSnr = 0x40001c98;\nrcUpdateRate = 0x40001c9c;\nrcUpdateTxDone = 0x40001ca0;\nrcUpdateTxDoneAmpdu2 = 0x40001ca4;\nrcUpSched = 0x40001ca8;\nrssi_margin = 0x40001cac;\nrx11NRate2AMPDULimit = 0x40001cb0;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001cb4;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001cb8;\ntrc_calc_duration = 0x40001cbc;\ntrc_isTxAmpduOperational = 0x40001cc0;\ntrc_onAmpduOp = 0x40001cc4;\nTRC_PER_IS_GOOD = 0x40001cc8;\ntrc_SetTxAmpduState = 0x40001ccc;\ntrc_tid_isTxAmpduOperational = 0x40001cd0;\ntrcAmpduSetState = 0x40001cd4;\nwDevCheckBlockError = 0x40001cd8;\nwDev_AppendRxBlocks = 0x40001cdc;\nwDev_DiscardFrame = 0x40001ce0;\nwDev_GetNoiseFloor = 0x40001ce4;\nwDev_IndicateAmpdu = 0x40001ce8;\nwDev_IndicateFrame = 0x40001cec;\nwdev_mac_reg_load = 0x40001cf0;\nwdev_mac_reg_store = 0x40001cf4;\nwdev_mac_special_reg_load = 0x40001cf8;\nwdev_mac_special_reg_store = 0x40001cfc;\nwdev_mac_wakeup = 0x40001d00;\nwdev_mac_sleep = 0x40001d04;\nwDev_ProcessFiq = 0x40001d08;\nwDev_ProcessRxSucData = 0x40001d0c;\nwdevProcessRxSucDataAll = 0x40001d10;\nwdev_csi_len_align = 0x40001d14;\nppDequeueTxDone_Locked = 0x40001d18;\nppProcTxDone = 0x40001d1c;\npm_tx_data_done_process = 0x40001d20;\nconfig_is_cache_tx_buf_enabled = 0x40001d24;\nppMapWaitTxq = 0x40001d28;\nppProcessWaitingQueue = 0x40001d2c;\nppDisableQueue = 0x40001d30;\npm_allow_tx = 0x40001d34;\nwdev_is_data_in_rxlist = 0x40001d38;\nppProcTxCallback = 0x40001d3c;\npm_is_open = 0x40001d40;\npm_wake_up = 0x40001d44;\npm_wake_done = 0x40001d48;\npm_disable_disconnected_sleep_delay_timer = 0x40001d4c;\npm_enable_disconnected_sleep_delay_timer = 0x40001d50;\nhal_mac_get_txq_state = 0x40001d54;\nhal_mac_clr_txq_state = 0x40001d58;\nhal_mac_tx_set_cca = 0x40001d5c;\nhal_mac_set_txq_invalid = 0x40001d60;\nhal_mac_txq_disable = 0x40001d64;\nhal_mac_is_txq_enabled = 0x40001d68;\nhal_mac_get_txq_pmd = 0x40001d6c;\nlmacDiscardFrameExchangeSequence = 0x40001d70;\nlmacDisableTransmit = 0x40001d74;\nlmacProcessTxTimeout = 0x40001d78;\nlmacProcessTxSuccess = 0x40001d7c;\nlmacProcessCollision = 0x40001d80;\nlmacProcessTxRtsError = 0x40001d84;\nlmacProcessCtsTimeout = 0x40001d88;\nlmacProcessTxComplete = 0x40001d8c;\nlmacProcessAckTimeout = 0x40001d90;\nlmacProcessTxError = 0x40001d94;\nlmacProcessTxseckiderr = 0x40001d98;\nrcReachRetryLimit = 0x40001d9c;\nlmacProcessShortRetryFail = 0x40001da0;\nlmacEndRetryAMPDUFail = 0x40001da4;\nppFillAMPDUBar = 0x40001da8;\nrcGetRate = 0x40001dac;\nppReSendBar = 0x40001db0;\nlmacProcessLongRetryFail = 0x40001db4;\nlmacRetryTxFrame = 0x40001db8;\nlmacProcessCollisions_task = 0x40001dbc;\nlmacProcessTxopQComplete = 0x40001dc0;\nlmacInitAc = 0x40001dc4;\nlmacInit = 0x40001dc8;\nmac_tx_set_txop_q = 0x40001dcc;\nhal_init = 0x40001dd0;\nhal_mac_rx_set_policy = 0x40001dd4;\nhal_mac_set_bssid = 0x40001dd8;\nmac_rx_policy_init = 0x40001ddc;\nmac_txrx_init = 0x40001de0;\nmac_rxbuf_init = 0x40001de4;\nmac_last_rxbuf_init = 0x40001de8;\nhal_attenna_init = 0x40001dec;\nhal_timer_update_by_rtc = 0x40001df0;\nhal_coex_pti_init = 0x40001df4;\nlmac_stop_hw_txq = 0x40001df8;\nppDirectRecycleAmpdu = 0x40001dfc;\nesp_wifi_internal_set_rts = 0x40001e00;\nesp_wifi_internal_get_rts = 0x40001e04;\nppTxFragmentProc = 0x40001e08;\nesf_buf_setup = 0x40001e0c;\nhal_agreement_add_rx_ba = 0x40001e10;\nhal_agreement_del_rx_ba = 0x40001e14;\nhal_crypto_set_key_entry = 0x40001e18;\nhal_crypto_get_key_entry = 0x40001e1c;\nhal_crypto_clr_key_entry = 0x40001e20;\nconfig_get_wifi_task_stack_size = 0x40001e24;\npp_create_task = 0x40001e28;\nhal_set_sta_tsf_wakeup = 0x40001e2c;\nhal_set_rx_beacon_pti = 0x40001e30;\npm_start = 0x40001e34;\npm_stop = 0x40001e38;\nhal_disable_sta_tbtt = 0x40001e3c;\nppCalTxopDur = 0x40001e40;\nwDev_IndicateCtrlFrame = 0x40001e44;\nhal_enable_sta_tbtt = 0x40001e48;\nhal_set_sta_tbtt = 0x40001e4c;\npm_update_next_tbtt = 0x40001e50;\npm_set_sleep_type = 0x40001e54;\nwDev_Rxbuf_Init = 0x40001e58;\nwDev_Rxbuf_Deinit = 0x40001e5c;\nppCalTkipMic = 0x40001e60;\nwDev_SnifferRxData = 0x40001e64;\nhal_crypto_enable = 0x40001e68;\nhal_crypto_disable = 0x40001e6c;\nwDev_Insert_KeyEntry = 0x40001e70;\nwDev_remove_KeyEntry = 0x40001e74;\nrc_enable_trc = 0x40001e78;\nrc_set_per_conn_fix_rate = 0x40001e7c;\nwdev_csi_rx_process = 0x40001e80;\nwDev_SnifferRxAmpdu = 0x40001e84;\nhal_mac_tsf_reset = 0x40001e88;\ndbg_lmac_statis_dump = 0x40001e8c;\ndbg_lmac_rxtx_statis_dump = 0x40001e90;\ndbg_lmac_hw_statis_dump = 0x40001e94;\ndbg_lmac_diag_statis_dump = 0x40001e98;\ndbg_lmac_ps_statis_dump = 0x40001e9c;\npp_timer_do_process = 0x40001ea0;\nrcUpdateAMPDUParam = 0x40001ea4;\nrcUpdatePhyMode = 0x40001ea8;\nrcGetHighestRateIdx = 0x40001eac;\npm_tx_null_data_done_process = 0x40001eb0;\npm_tx_data_process = 0x40001eb4;\npm_attach = 0x40001eb8;\npm_coex_schm_process = 0x40001ebc;\nppInitTxq = 0x40001ec0;\npp_attach = 0x40001ec4;\npp_deattach = 0x40001ec8;\npm_on_probe_resp_rx = 0x40001ecc;\nhal_set_sta_tsf = 0x40001ed0;\nic_update_sta_tsf = 0x40001ed4;\nic_tx_pkt = 0x40001ed8;\npm_send_probe_stop = 0x40001edc;\npm_send_probe_start = 0x40001ee0;\npm_on_coex_schm_process_restart = 0x40001ee4;\nhal_mac_set_rxq_policy = 0x40001ee8;\nhal_sniffer_enable = 0x40001eec;\nhal_sniffer_disable = 0x40001ef0;\nhal_sniffer_rx_set_promis = 0x40001ef4;\nhal_sniffer_rx_clr_statistics = 0x40001ef8;\nhal_sniffer_set_promis_misc_pkt = 0x40001efc;\ntsf_hal_set_tsf_enable = 0x40001f00;\ntsf_hal_set_tsf_disable = 0x40001f04;\ntsf_hal_is_tsf_enabled = 0x40001f08;\ntsf_hal_set_modem_wakeup_early_time = 0x40001f0c;\ntsf_hal_get_counter_value = 0x40001f10;\ntsf_hal_set_counter_value = 0x40001f14;\ntsf_hal_get_time = 0x40001f18;\ntsf_hal_set_time = 0x40001f1c;\ntsf_hal_set_tbtt_enable = 0x40001f20;\ntsf_hal_set_tbtt_disable = 0x40001f24;\ntsf_hal_set_tbtt_intr_enable = 0x40001f28;\ntsf_hal_set_tbtt_intr_disable = 0x40001f2c;\ntsf_hal_set_tbtt_soc_wakeup_enable = 0x40001f30;\ntsf_hal_set_tbtt_soc_wakeup_disable = 0x40001f34;\ntsf_hal_set_tbtt_start_time = 0x40001f38;\ntsf_hal_set_tbtt_early_time = 0x40001f3c;\ntsf_hal_set_tbtt_interval = 0x40001f40;\ntsf_hal_get_tbtt_interval = 0x40001f44;\ntsf_hal_set_timer_enable = 0x40001f48;\ntsf_hal_set_timer_disable = 0x40001f4c;\ntsf_hal_set_timer_target = 0x40001f50;\ntsf_hal_get_timer_target = 0x40001f54;\ntsf_hal_set_timer_intr_enable = 0x40001f58;\ntsf_hal_set_timer_intr_disable = 0x40001f5c;\ntsf_hal_set_timer_soc_wakeup_enable = 0x40001f60;\ntsf_hal_set_timer_soc_wakeup_disable = 0x40001f64;\npm_disconnected_wake = 0x40001f68;\npm_get_connectionless_status = 0x40001f6c;\npm_update_by_connectionless_status = 0x40001f70;\npm_connectionless_wake_interval_timeout_process = 0x40001f74;\npm_connectionless_wake_window_timeout_process = 0x40001f78;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff4fbbc;\npTxRx = 0x3fcdfdec;\nlmacConfMib_ptr = 0x3fcdfde8;\nour_wait_eb = 0x3fcdfde4;\nour_tx_eb = 0x3fcdfde0;\npp_wdev_funcs = 0x3fcdfddc;\ng_osi_funcs_p = 0x3fcdfdd8;\nwDevCtrl_ptr = 0x3fcdfdd4;\ng_wdev_last_desc_reset_ptr = 0x3ff4fbb8;\nwDevMacSleep_ptr = 0x3fcdfdd0;\ng_lmac_cnt_ptr = 0x3fcdfdcc;\nour_controls_ptr = 0x3ff4fbb4;\npp_sig_cnt_ptr = 0x3fcdfdc8;\ng_eb_list_desc_ptr = 0x3fcdfdc4;\ns_fragment_ptr = 0x3fcdfdc0;\nif_ctrl_ptr = 0x3fcdfdbc;\ng_intr_lock_mux = 0x3fcdfdb8;\ng_wifi_global_lock = 0x3fcdfdb4;\ns_wifi_queue = 0x3fcdfdb0;\npp_task_hdl = 0x3fcdfdac;\ns_pp_task_create_sem = 0x3fcdfda8;\ns_pp_task_del_sem = 0x3fcdfda4;\ng_wifi_menuconfig_ptr = 0x3fcdfda0;\nxphyQueue = 0x3fcdfd9c;\nap_no_lr_ptr = 0x3fcdfd98;\nrc11BSchedTbl_ptr = 0x3fcdfd94;\nrc11NSchedTbl_ptr = 0x3fcdfd90;\nrcLoRaSchedTbl_ptr = 0x3fcdfd8c;\nBasicOFDMSched_ptr = 0x3fcdfd88;\ntrc_ctl_ptr = 0x3fcdfd84;\ng_pm_cnt_ptr = 0x3fcdfd80;\ng_pm_ptr = 0x3fcdfd7c;\ng_pm_cfg_ptr = 0x3fcdfd78;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdfd74;\ng_txop_queue_status_ptr = 0x3fcdfd70;\ng_mac_sleep_en_ptr = 0x3fcdfd6c;\ng_mesh_is_root_ptr = 0x3fcdfd68;\ng_mesh_topology_ptr = 0x3fcdfd64;\ng_mesh_init_ps_type_ptr = 0x3fcdfd60;\ng_mesh_is_started_ptr = 0x3fcdfd5c;\ng_config_func = 0x3fcdfd58;\ng_net80211_tx_func = 0x3fcdfd54;\ng_timer_func = 0x3fcdfd50;\ns_michael_mic_failure_cb = 0x3fcdfd4c;\nwifi_sta_rx_probe_req = 0x3fcdfd48;\ng_tx_done_cb_func = 0x3fcdfd44;\ng_per_conn_trc = 0x3fcdfd28;\ns_encap_amsdu_func = 0x3fcdfd24;\nbars = 0x3fcdfc84;\neb_txdesc_space = 0x3fcdfbf4;\neb_space = 0x3fcdfb54;\ng_pd_mac_in_light_sleep = 0x3fcdfb50;\ns_fix_rate_mask = 0x3fcdfb4c;\ns_fix_rate = 0x3fcdfb44;\ng_wdev_csi_rx = 0x3fcdfb40;\ng_wdev_csi_rx_ctx = 0x3fcdfb3c;\nBcnSendTick = 0x3fcdfb38;\ng_pp_timer_info_ptr = 0x3fcdfb34;\nrcP2P11NSchedTbl_ptr = 0x3fcdfb30;\nrcP2P11GSchedTbl_ptr = 0x3fcdfb2c;\nrc11GSchedTbl_ptr = 0x3fcdfb28;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001f7c;\nampdu_dispatch = 0x40001f80;\nampdu_dispatch_all = 0x40001f84;\nampdu_dispatch_as_many_as_possible = 0x40001f88;\nampdu_dispatch_movement = 0x40001f8c;\nampdu_dispatch_upto = 0x40001f90;\nchm_is_at_home_channel = 0x40001f94;\ncnx_node_is_existing = 0x40001f98;\ncnx_node_search = 0x40001f9c;\nic_ebuf_recycle_rx = 0x40001fa0;\nic_ebuf_recycle_tx = 0x40001fa4;\nic_reset_rx_ba = 0x40001fa8;\nieee80211_align_eb = 0x40001fac;\nieee80211_ampdu_reorder = 0x40001fb0;\nieee80211_ampdu_start_age_timer = 0x40001fb4;\nieee80211_encap_esfbuf = 0x40001fb8;\nieee80211_is_tx_allowed = 0x40001fbc;\nieee80211_output_pending_eb = 0x40001fc0;\nieee80211_output_process = 0x40001fc4;\nieee80211_set_tx_desc = 0x40001fc8;\nsta_input = 0x40001fcc;\nwifi_get_macaddr = 0x40001fd0;\nwifi_rf_phy_disable = 0x40001fd4;\nwifi_rf_phy_enable = 0x40001fd8;\nic_ebuf_alloc = 0x40001fdc;\nieee80211_classify = 0x40001fe0;\nieee80211_copy_eb_header = 0x40001fe4;\nieee80211_recycle_cache_eb = 0x40001fe8;\nieee80211_search_node = 0x40001fec;\nroundup2 = 0x40001ff0;\nieee80211_crypto_encap = 0x40001ff4;\nieee80211_crypto_decap = 0x40001ff8;\nieee80211_decap = 0x40001ffc;\nieee80211_set_tx_pti = 0x40002000;\nwifi_is_started = 0x40002004;\nieee80211_gettid = 0x40002008;\nieee80211_ccmp_decrypt = 0x4000200c;\nieee80211_ccmp_encrypt = 0x40002010;\nccmp_encap = 0x40002014;\nccmp_decap = 0x40002018;\ntkip_encap = 0x4000201c;\ntkip_decap = 0x40002020;\nwep_encap = 0x40002024;\nwep_decap = 0x40002028;\ndbg_hmac_rxtx_statis_dump = 0x4000202c;\ndbg_hmac_statis_dump = 0x40002030;\nieee80211_send_action_vendor_spec = 0x40002034;\nieee80211_send_mgmt = 0x40002038;\nieee80211_auth_construct = 0x4000203c;\nieee80211_deauth_construct = 0x40002040;\nieee80211_disassoc_construct = 0x40002044;\nieee80211_vnd_lora_ie_size = 0x40002048;\nieee80211_vnd_ie_size = 0x4000204c;\nieee80211_add_ssid = 0x40002050;\nieee80211_add_rates = 0x40002054;\nieee80211_add_xrates = 0x40002058;\nieee80211_is_ht_cipher = 0x4000205c;\nieee80211_assoc_req_construct = 0x40002060;\nieee80211_assoc_resp_construct = 0x40002064;\nieee80211_setup_lr_rates = 0x40002068;\nieee80211_ht_node_init = 0x4000206c;\nieee80211_is_support_rate = 0x40002070;\nieee80211_setup_rates = 0x40002074;\nieee80211_is_lr_only = 0x40002078;\nieee80211_setup_phy_mode = 0x4000207c;\nieee80211_sta_is_connected = 0x40002080;\ncurrent_task_is_wifi_task = 0x40002084;\nwifi_get_init_state = 0x40002088;\nieee80211_timer_process = 0x4000208c;\ncnx_coexist_timeout = 0x40002090;\nsta_recv_mgmt = 0x40002094;\nieee80211_send_setup = 0x40002098;\nieee80211_send_probereq = 0x4000209c;\nsta_auth_open = 0x400020a0;\nsta_auth_shared = 0x400020a4;\nsta_auth_sae = 0x400020a8;\ncnx_coexist_timeout_process = 0x400020ac;\nieee80211_alloc_challenge = 0x400020b0;\ncnx_assoc_timeout = 0x400020b4;\nieee80211_vnd_ie_set = 0x400020b8;\nieee80211_vnd_lora_ie_set = 0x400020bc;\nieee80211_add_wme_param = 0x400020c0;\nieee80211_add_dsparams = 0x400020c4;\nieee80211_add_csa = 0x400020c8;\nieee80211_add_extcap = 0x400020cc;\nieee80211_regdomain_get_country = 0x400020d0;\nieee80211_add_countryie = 0x400020d4;\nieee80211_alloc_proberesp = 0x400020d8;\nieee80211_amsdu_adjust_head = 0x400020dc;\nieee80211_amsdu_adjust_last_length = 0x400020e0;\nieee80211_amsdu_send_check = 0x400020e4;\nieee80211_amsdu_encap_check = 0x400020e8;\nieee80211_amsdu_length_check = 0x400020ec;\nieee80211_encap_amsdu = 0x400020f0;\nieee80211_output_raw_process = 0x400020f4;\nesp_wifi_80211_tx = 0x400020f8;\nieee80211_raw_frame_sanity_check = 0x400020fc;\nieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;\nieee80211_crypto_aes_128_cmac_decrypt = 0x40002104;\nieee80211_alloc_tx_buf = 0x40002108;\nieee80211_output_do = 0x4000210c;\nieee80211_send_nulldata = 0x40002110;\nieee80211_setup_robust_mgmtframe = 0x40002114;\nieee80211_mgmt_output = 0x40002118;\nieee80211_encap_null_data = 0x4000211c;\nieee80211_send_deauth = 0x40002120;\nieee80211_alloc_deauth = 0x40002124;\nieee80211_send_proberesp = 0x40002128;\nieee80211_tx_mgt_cb = 0x4000212c;\nieee80211_getcapinfo = 0x40002130;\nsta_rx_csa = 0x40002134;\nsta_send_sa_query_req = 0x40002138;\nsta_send_sa_query_resp = 0x4000213c;\nsta_recv_sa_query_req = 0x40002140;\nsta_recv_sa_query_resp = 0x40002144;\nieee80211_parse_beacon = 0x40002148;\nieee80211_set_max_rate = 0x4000214c;\nic_set_sta = 0x40002150;\nieee80211_match_security = 0x40002154;\nieee80211_parse_wpa = 0x40002158;\nieee80211_parse_rsn = 0x4000215c;\nieee80211_add_assoc_req_ies = 0x40002160;\nieee80211_add_probe_req_ies = 0x40002164;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdfb24;\ng_scan = 0x3fcdfb20;\ng_chm = 0x3fcdfb1c;\ng_ic_ptr = 0x3fcdfb18;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_tx_cacheq_ptr = 0x3fcdfb14;\ns_netstack_free = 0x3fcdfb10;\nmesh_rxcb = 0x3fcdfb0c;\nsta_rxcb = 0x3fcdfb08;\nccmp_ptr = 0x3fcdfb04;\ns_wifi_nvs_ptr = 0x3fcdfb00;\ntkip_ptr = 0x3fcdfafc;\nwep_ptr = 0x3fcdfaf8;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_misc_nvs = 0x3fcdfaf0;\ns_wifi_init_state = 0x3fcdfac0;\ns_wifi_task_hdl = 0x3fcdfaec;\nin_rssi_adjust = 0x3fcdfae8;\nrssi_saved = 0x3fcdfae0;\nrssi_index = 0x3fcdfadc;\ns_sa_query_retries = 0x3fcdfad8;\ns_sa_query_success = 0x3fcdfad5;\ng_sta_connected_flag = 0x3fcdfad4;\nwpa_crypto_funcs_ptr = 0x3fcdfad0;\ns_netstack_ref = 0x3fcdfacc;\nsta_csa_timer_ptr = 0x3fcdfac8;\ns_trans_id = 0x3fcdfac4;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x40002168;\ncoex_bt_release = 0x4000216c;\ncoex_bt_request = 0x40002170;\ncoex_core_ble_conn_dyn_prio_get = 0x40002174;\ncoex_core_event_duration_get = 0x40002178;\ncoex_core_pti_get = 0x4000217c;\ncoex_core_release = 0x40002180;\ncoex_core_request = 0x40002184;\ncoex_core_status_get = 0x40002188;\ncoex_core_timer_idx_get = 0x4000218c;\ncoex_event_duration_get = 0x40002190;\ncoex_hw_timer_disable = 0x40002194;\ncoex_hw_timer_enable = 0x40002198;\ncoex_hw_timer_set = 0x4000219c;\ncoex_schm_interval_set = 0x400021a0;\ncoex_schm_lock = 0x400021a4;\ncoex_schm_unlock = 0x400021a8;\ncoex_status_get = 0x400021ac;\ncoex_wifi_release = 0x400021b0;\nesp_coex_ble_conn_dynamic_prio_get = 0x400021b4;\ncoex_hw_timer_tick_get = 0x400021b8;\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdfabc;\ncoex_pti_tab_ptr = 0x3fcdfab8;\ncoex_schm_env_ptr = 0x3fcdfab4;\ncoexist_funcs = 0x3fcdfab0;\ng_coa_funcs_p = 0x3fcdfaac;\ng_coex_param_ptr = 0x3fcdfaa8;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_param_addr = 0x400021bc;\nphy_get_romfuncs = 0x400021c0;\nchip729_phyrom_version = 0x400021c4;\nchip729_phyrom_version_num = 0x400021c8;\nrom_get_rc_dout = 0x400021cc;\nrc_cal = 0x400021d0;\nphy_analog_delay_cal = 0x400021d4;\nphy_rx_rifs_en = 0x400021d8;\nphy_current_level_set = 0x400021dc;\nphy_bbpll_en_usb = 0x400021e0;\nphy_bt_power_track = 0x400021e4;\nphy_xpd_tsens = 0x400021e8;\nbb_wdt_rst_enable = 0x400021ec;\nbb_wdt_int_enable = 0x400021f0;\nbb_wdt_timeout_clear = 0x400021f4;\nbb_wdt_get_status = 0x400021f8;\nrom_enter_critical_phy = 0x400021fc;\nrom_exit_critical_phy = 0x40002200;\nrom_bb_bss_cbw40 = 0x40002204;\nrom_set_chan_reg = 0x40002208;\nabs_temp = 0x4000220c;\nset_chan_cal_interp = 0x40002210;\nloopback_mode_en = 0x40002214;\nget_data_sat = 0x40002218;\nphy_byte_to_word = 0x4000221c;\nphy_get_rx_freq = 0x40002220;\ni2c_master_reset = 0x40002224;\nchan14_mic_enable = 0x40002228;\nchan14_mic_cfg = 0x4000222c;\nset_adc_rand = 0x40002230;\nphy_set_most_tpw = 0x40002234;\nphy_get_most_tpw = 0x40002238;\nesp_tx_state_out = 0x4000223c;\nphy_get_adc_rand = 0x40002240;\nphy_internal_delay = 0x40002244;\nphy_ftm_comp = 0x40002248;\nphy_11p_set = 0x4000224c;\nphy_freq_mem_backup = 0x40002250;\nant_dft_cfg = 0x40002254;\nant_wifitx_cfg = 0x40002258;\nant_wifirx_cfg = 0x4000225c;\nant_bttx_cfg = 0x40002260;\nant_btrx_cfg = 0x40002264;\nphy_chan_dump_cfg = 0x40002268;\nphy_enable_low_rate = 0x4000226c;\nphy_disable_low_rate = 0x40002270;\nphy_dig_reg_backup = 0x40002274;\nphy_chan_filt_set = 0x40002278;\nphy_rx11blr_cfg = 0x4000227c;\nset_cca = 0x40002280;\nset_rx_sense = 0x40002284;\nrx_gain_force = 0x40002288;\nrom_phy_en_hw_set_freq = 0x4000228c;\nrom_phy_dis_hw_set_freq = 0x40002290;\nwr_rf_freq_mem = 0x40002294;\nfreq_i2c_write_set = 0x40002298;\nwrite_pll_cap_mem = 0x4000229c;\npll_dac_mem_update = 0x400022a0;\npll_cap_mem_update = 0x400022a4;\nget_rf_freq_cap = 0x400022a8;\nget_rf_freq_init = 0x400022ac;\nfreq_get_i2c_data = 0x400022b0;\nfreq_i2c_data_write = 0x400022b4;\nset_chan_freq_hw_init = 0x400022b8;\nset_chan_freq_sw_start = 0x400022bc;\nrom_get_i2c_read_mask = 0x400022c0;\nrom_get_i2c_mst0_mask = 0x400022c4;\nrom_get_i2c_hostid = 0x400022c8;\nrom_chip_i2c_readReg_org = 0x400022cc;\nrom_chip_i2c_readReg = 0x400022d0;\nrom_i2c_paral_set_mst0 = 0x400022d4;\nrom_i2c_paral_set_read = 0x400022d8;\nrom_i2c_paral_read = 0x400022dc;\nrom_i2c_paral_write = 0x400022e0;\nrom_i2c_paral_write_num = 0x400022e4;\nrom_i2c_paral_write_mask = 0x400022e8;\nrom_i2c_readReg = 0x400022ec;\nrom_chip_i2c_writeReg = 0x400022f0;\nrom_i2c_writeReg = 0x400022f4;\nrom_i2c_readReg_Mask = 0x400022f8;\nrom_i2c_writeReg_Mask = 0x400022fc;\nrom_set_txcap_reg = 0x40002300;\ni2c_sar2_init_code = 0x40002304;\nphy_i2c_init1 = 0x40002308;\nphy_i2c_init2 = 0x4000230c;\nphy_get_i2c_data = 0x40002310;\nbias_reg_set = 0x40002314;\ni2c_rc_cal_set = 0x40002318;\ni2c_bbpll_set = 0x4000231c;\nrom_phy_xpd_rf = 0x40002320;\nphy_wakeup_init_rom = 0x40002324;\nregister_chipv7_phy_init_param = 0x40002328;\nphy_reg_init = 0x4000232c;\nphy_close_rf_rom = 0x40002330;\nrom_pbus_force_mode = 0x40002334;\nrom_pbus_rd_addr = 0x40002338;\nrom_pbus_rd_shift = 0x4000233c;\nrom_pbus_force_test = 0x40002340;\nrom_pbus_rd = 0x40002344;\nrom_pbus_debugmode = 0x40002348;\nrom_pbus_workmode = 0x4000234c;\nrom_pbus_set_rxgain = 0x40002350;\nrom_pbus_xpd_rx_off = 0x40002354;\nrom_pbus_xpd_rx_on = 0x40002358;\nrom_pbus_xpd_tx_off = 0x4000235c;\nrom_pbus_xpd_tx_on = 0x40002360;\nrom_pbus_set_dco = 0x40002364;\nrom_set_loopback_gain = 0x40002368;\nrom_txcal_debuge_mode = 0x4000236c;\nrom_txcal_work_mode = 0x40002370;\nset_pbus_mem = 0x40002374;\nrom_pwdet_sar2_init = 0x40002378;\nrom_en_pwdet = 0x4000237c;\nrom_get_sar_sig_ref = 0x40002380;\nrom_pwdet_tone_start = 0x40002384;\nrom_get_tone_sar_dout = 0x40002388;\nrom_get_fm_sar_dout = 0x4000238c;\nrom_txtone_linear_pwr = 0x40002390;\nrom_get_power_db = 0x40002394;\nrom_meas_tone_pwr_db = 0x40002398;\nrom_pkdet_vol_start = 0x4000239c;\nrom_read_sar_dout = 0x400023a0;\nrom_read_sar2_code = 0x400023a4;\nrom_get_sar2_vol = 0x400023a8;\nrom_get_pll_vol = 0x400023ac;\nrom_tx_pwctrl_bg_init = 0x400023b0;\nrom_phy_pwdet_always_en = 0x400023b4;\nrom_phy_pwdet_onetime_en = 0x400023b8;\nlinear_to_db = 0x400023bc;\nrom_disable_agc = 0x400023c0;\nrom_enable_agc = 0x400023c4;\nrom_disable_wifi_agc = 0x400023c8;\nrom_enable_wifi_agc = 0x400023cc;\nrom_write_gain_mem = 0x400023d0;\nrom_bb_bss_cbw40_dig = 0x400023d4;\nrom_cbw2040_cfg = 0x400023d8;\nrom_mac_tx_chan_offset = 0x400023dc;\nrom_tx_paon_set = 0x400023e0;\nrom_i2cmst_reg_init = 0x400023e4;\nrom_bt_gain_offset = 0x400023e8;\nrom_fe_reg_init = 0x400023ec;\nrom_mac_enable_bb = 0x400023f0;\nrom_bb_wdg_cfg = 0x400023f4;\nrom_fe_txrx_reset = 0x400023f8;\nrom_set_rx_comp = 0x400023fc;\nrom_write_chan_freq = 0x40002400;\nrom_agc_reg_init = 0x40002404;\nrom_bb_reg_init = 0x40002408;\nrom_write_txrate_power_offset = 0x4000240c;\nrom_open_i2c_xpd = 0x40002410;\nrom_txiq_set_reg = 0x40002414;\nrom_rxiq_set_reg = 0x40002418;\nrom_phy_bbpll_cal = 0x4000241c;\nphy_disable_cca = 0x40002420;\nphy_enable_cca = 0x40002424;\nforce_txon = 0x40002428;\nset_txclk_en = 0x4000242c;\nset_rxclk_en = 0x40002430;\nstart_tx_tone_step = 0x40002434;\nstop_tx_tone = 0x40002438;\nbb_wdg_test_en = 0x4000243c;\nnoise_floor_auto_set = 0x40002440;\nread_hw_noisefloor = 0x40002444;\niq_corr_enable = 0x40002448;\nbt_tx_dig_gain = 0x4000244c;\nwifi_tx_dig_reg = 0x40002450;\nwifi_agc_sat_gain = 0x40002454;\nphy_ant_init = 0x40002458;\nphy_set_bbfreq_init = 0x4000245c;\nwifi_fbw_sel = 0x40002460;\nphy_rx_sense_set = 0x40002464;\ntx_state_set = 0x40002468;\nphy_close_pa = 0x4000246c;\nbt_filter_reg = 0x40002470;\nphy_freq_correct = 0x40002474;\nset_pbus_reg = 0x40002478;\nwifi_rifs_mode_en = 0x4000247c;\nrfagc_disable = 0x40002480;\nrom_restart_cal = 0x40002484;\nrom_write_rfpll_sdm = 0x40002488;\nrom_wait_rfpll_cal_end = 0x4000248c;\nrom_rfpll_set_freq = 0x40002490;\nrom_rfpll_cap_init_cal = 0x40002494;\nrom_set_rfpll_freq = 0x40002498;\nrom_write_pll_cap = 0x4000249c;\nrom_read_pll_cap = 0x400024a0;\nmhz2ieee = 0x400024a4;\nchan_to_freq = 0x400024a8;\nset_rf_freq_offset = 0x400024ac;\nset_channel_rfpll_freq = 0x400024b0;\nrfpll_cap_correct = 0x400024b4;\nphy_set_freq = 0x400024b8;\ncorrect_rfpll_offset = 0x400024bc;\npll_vol_cal = 0x400024c0;\nchip_v7_set_chan_misc = 0x400024c4;\nchip_v7_set_chan = 0x400024c8;\nchip_v7_set_chan_offset = 0x400024cc;\nchip_v7_set_chan_ana = 0x400024d0;\nset_chanfreq = 0x400024d4;\nrom_rxiq_cover_mg_mp = 0x400024d8;\nrom_rfcal_rxiq = 0x400024dc;\nrom_get_rfcal_rxiq_data = 0x400024e0;\nrom_pbus_rx_dco_cal = 0x400024e4;\nrom_rxdc_est_min = 0x400024e8;\nrom_pbus_rx_dco_cal_1step = 0x400024ec;\nrom_set_lb_txiq = 0x400024f0;\nrom_set_rx_gain_cal_iq = 0x400024f4;\nrom_set_rx_gain_cal_dc = 0x400024f8;\niq_est_enable = 0x400024fc;\niq_est_disable = 0x40002500;\ndc_iq_est = 0x40002504;\nset_cal_rxdc = 0x40002508;\nrxiq_get_mis = 0x4000250c;\nspur_reg_write_one_tone = 0x40002510;\nspur_cal = 0x40002514;\nspur_coef_cfg = 0x40002518;\ngen_rx_gain_table = 0x4000251c;\nwr_rx_gain_mem = 0x40002520;\nset_rx_gain_param = 0x40002524;\nset_rx_gain_table = 0x40002528;\nrom_tester_wifi_cali = 0x4000252c;\nesp_recover_efuse_data = 0x40002530;\nbt_track_pll_cap = 0x40002534;\nrfpll_cap_track = 0x40002538;\nphy_param_track = 0x4000253c;\ntxpwr_correct = 0x40002540;\ntxpwr_cal_track = 0x40002544;\ntx_pwctrl_background = 0x40002548;\nbt_track_tx_power = 0x4000254c;\nwifi_track_tx_power = 0x40002550;\nrom_code_to_temp = 0x40002554;\nrom_tsens_index_to_dac = 0x40002558;\nrom_tsens_index_to_offset = 0x4000255c;\nrom_tsens_dac_cal = 0x40002560;\nrom_tsens_code_read = 0x40002564;\nrom_tsens_temp_read = 0x40002568;\nrom_temp_to_power = 0x4000256c;\ntsens_read_init = 0x40002570;\nget_temp_init = 0x40002574;\nrom_txiq_cover = 0x40002578;\nrom_rfcal_txiq = 0x4000257c;\nrom_get_power_atten = 0x40002580;\nrom_tx_pwctrl_init_cal = 0x40002584;\nbt_txdc_cal = 0x40002588;\nbt_txiq_cal = 0x4000258c;\ntxiq_cal_init = 0x40002590;\ntxdc_cal_init = 0x40002594;\ntxdc_cal_v70 = 0x40002598;\ntxiq_get_mis_pwr = 0x4000259c;\npwdet_ref_code = 0x400025a0;\npwdet_code_cal = 0x400025a4;\nrfcal_txcap = 0x400025a8;\ntx_cap_init = 0x400025ac;\nrfcal_pwrctrl = 0x400025b0;\ntx_pwctrl_init = 0x400025b4;\nbt_tx_pwctrl_init = 0x400025b8;\nbt_txpwr_freq = 0x400025bc;\nrom_txbbgain_to_index = 0x400025c0;\nrom_index_to_txbbgain = 0x400025c4;\nrom_bt_index_to_bb = 0x400025c8;\nrom_bt_bb_to_index = 0x400025cc;\nrom_bt_get_tx_gain = 0x400025d0;\nrom_get_tx_gain_value = 0x400025d4;\nrom_wifi_get_tx_gain = 0x400025d8;\nrom_set_tx_gain_mem = 0x400025dc;\nrom_get_rate_fcc_index = 0x400025e0;\nrom_get_chan_target_power = 0x400025e4;\nrom_wifi_tx_dig_gain = 0x400025e8;\nrom_wifi_set_tx_gain = 0x400025ec;\nrom_bt_set_tx_gain = 0x400025f0;\nwifi_11g_rate_chg = 0x400025f4;\nbt_chan_pwr_interp = 0x400025f8;\nbt_tx_gain_init = 0x400025fc;\n\/* Data (.data, .bss, .rodata) *\/\nphy_param_rom = 0x3fcdfaa4;\n\n\n\/***************************************\n Group rom_btbb\n ***************************************\/\n\n\/* Functions *\/\nbt_agc_gain_offset = 0x40002600;\nbt_agc_gain_max = 0x40002604;\nbt_set_rx_comp = 0x40002608;\nbt_agc_gain_set = 0x4000260c;\nbt_agc_rssi_thresh = 0x40002610;\nbt_agc_target_set = 0x40002614;\nbt_agc_restart_set = 0x40002618;\nbt_agc_recorrect_set = 0x4000261c;\nbt_agc_detect_set = 0x40002620;\nbt_bb_rx_correlator_set = 0x40002624;\nbt_bb_rx_dpo_set = 0x40002628;\nbt_bb_rx_filter_sel = 0x4000262c;\nbt_bb_rx_set1 = 0x40002630;\nbt_bb_v2_rx_set = 0x40002634;\nbt_bb_v2_tx_set = 0x40002638;\nbt_bb_tx_cca_set = 0x4000263c;\nbt_bb_tx_cca_period = 0x40002640;\nbt_bb_tx_cca_fifo_reset = 0x40002644;\nbt_bb_tx_cca_fifo_empty = 0x40002648;\nbt_bb_tx_cca_fifo_full = 0x4000264c;\nbt_bb_tx_cca_fifo_count = 0x40002650;\nbt_bb_tx_cca_fifo_read = 0x40002654;\ncoex_pti_v2 = 0x40002658;\nbt_bb_set_le_tx_on_delay = 0x4000265c;\nbt_bb_set_corr_thresh_le = 0x40002660;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"caa7725642d8d4d6405d54805036990649cb983a","subject":"esp8266\/boards: Move py\/pairheap.c code from iRAM to iROM.","message":"esp8266\/boards: Move py\/pairheap.c code from iRAM to iROM.\n\nIt doesn't need to be in iRAM.\n","repos":"tobbad\/micropython,MrSurly\/micropython,pramasoul\/micropython,adafruit\/circuitpython,kerneltask\/micropython,pramasoul\/micropython,tobbad\/micropython,MrSurly\/micropython,bvernoux\/micropython,henriknelson\/micropython,bvernoux\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,bvernoux\/micropython,pramasoul\/micropython,henriknelson\/micropython,MrSurly\/micropython,kerneltask\/micropython,selste\/micropython,henriknelson\/micropython,pramasoul\/micropython,MrSurly\/micropython,kerneltask\/micropython,selste\/micropython,adafruit\/circuitpython,selste\/micropython,selste\/micropython,selste\/micropython,henriknelson\/micropython,bvernoux\/micropython,MrSurly\/micropython,adafruit\/circuitpython,tobbad\/micropython,henriknelson\/micropython,tobbad\/micropython,bvernoux\/micropython,tobbad\/micropython,kerneltask\/micropython,pramasoul\/micropython,kerneltask\/micropython,adafruit\/circuitpython","old_file":"ports\/esp8266\/boards\/esp8266_common.ld","new_file":"ports\/esp8266\/boards\/esp8266_common.ld","new_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* Vendor SDK in v2.1.0-7-gb8fd588 started to build these with\n           -ffunction-sections -fdata-sections, and require routing to\n           irom via linker:\n           https:\/\/github.com\/espressif\/ESP8266_NONOS_SDK\/commit\/b8fd588a33f0319dc135523b51655e97b483b205\n         *\/\n\n        *libcrypto.a:(.literal.* .text.*)\n        *libnet80211.a:(.literal.* .text.*)\n        *libwpa.a:(.literal.* .text.*)\n        *libwpa2.a:(.literal.* .text.*)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/pairheap*.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/profile*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *lib\/axtls\/*.o(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/littlefs\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/printf.o*(.literal*, .text*)\n        *lib\/utils\/sys_stdio_mphal.o*(.literal*, .text*)\n        *lib\/utils\/pyexec.o*(.literal*, .text*)\n        *lib\/utils\/stdout_helpers.o*(.literal*, .text*)\n        *lib\/utils\/interrupt_char.o*(.literal*, .text*)\n        *drivers\/bus\/*.o(.literal* .text*)\n\n        build-*\/main.o(.literal* .text*)\n        *fatfs_port.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build-*\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"boards\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* Vendor SDK in v2.1.0-7-gb8fd588 started to build these with\n           -ffunction-sections -fdata-sections, and require routing to\n           irom via linker:\n           https:\/\/github.com\/espressif\/ESP8266_NONOS_SDK\/commit\/b8fd588a33f0319dc135523b51655e97b483b205\n         *\/\n\n        *libcrypto.a:(.literal.* .text.*)\n        *libnet80211.a:(.literal.* .text.*)\n        *libwpa.a:(.literal.* .text.*)\n        *libwpa2.a:(.literal.* .text.*)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/profile*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *lib\/axtls\/*.o(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/littlefs\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/printf.o*(.literal*, .text*)\n        *lib\/utils\/sys_stdio_mphal.o*(.literal*, .text*)\n        *lib\/utils\/pyexec.o*(.literal*, .text*)\n        *lib\/utils\/stdout_helpers.o*(.literal*, .text*)\n        *lib\/utils\/interrupt_char.o*(.literal*, .text*)\n        *drivers\/bus\/*.o(.literal* .text*)\n\n        build-*\/main.o(.literal* .text*)\n        *fatfs_port.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build-*\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"boards\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0a6907690cfa2d0c23210c16677bb03b02d9af28","subject":"format","message":"format\n","repos":"mbains\/STM32F4Discovery_GCC,mbains\/STM32F4Discovery_GCC","old_file":"stm32_flash.ld","new_file":"stm32_flash.ld","new_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F407VG Device with\n**                1024KByte FLASH, 192KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the Atollic TrueSTUDIO(R) toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20020000;    \/* end of 128K RAM on AHB bus*\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    \/* Should this be _ebss?*\/\n    PROVIDE ( _exit = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\n  .memory_b1_text :\n  {\n    *(.mb1text)        \/* .mb1text sections (code) *\/\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\n    *(.mb1rodata)      \/* read-only data (constants) *\/\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\r\n*****************************************************************************\r\n**\r\n**  File        : stm32_flash.ld\r\n**\r\n**  Abstract    : Linker script for STM32F407VG Device with\r\n**                1024KByte FLASH, 192KByte RAM\r\n**\r\n**                Set heap size, stack size and stack location according\r\n**                to application requirements.\r\n**\r\n**                Set memory bank area and size if external memory is used.\r\n**\r\n**  Target      : STMicroelectronics STM32\r\n**\r\n**  Environment : Atollic TrueSTUDIO(R)\r\n**\r\n**  Distribution: The file is distributed as is, without any warranty\r\n**                of any kind.\r\n**\r\n**  (c)Copyright Atollic AB.\r\n**  You may use this file as-is or modify it according to the needs of your\r\n**  project. Distribution of this file (unmodified or modified) is not\r\n**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the\r\n**  rights to distribute the assembled, compiled & linked contents of this\r\n**  file as part of an application binary file, provided that it is built\r\n**  using the Atollic TrueSTUDIO(R) toolchain.\r\n**\r\n*****************************************************************************\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\n\/* Highest address of the user mode stack *\/\r\n_estack = 0x20020000;    \/* end of 128K RAM on AHB bus*\/\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\r\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K\r\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector)) \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  \/* The program code and other data goes into FLASH *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)           \/* .text sections (code) *\/\r\n    *(.text*)          \/* .text* sections (code) *\/\r\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\r\n    *(.glue_7)         \/* glue arm to thumb code *\/\r\n    *(.glue_7t)        \/* glue thumb to arm code *\/\r\n\t*(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;        \/* define a global symbols at end of code *\/\r\n  } >FLASH\r\n\r\n\r\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n    .ARM : {\r\n    __exidx_start = .;\r\n      *(.ARM.exidx*)\r\n      __exidx_end = .;\r\n    } >FLASH\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } >FLASH\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } >FLASH\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(.fini_array*))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } >FLASH\r\n\r\n  \/* used by the startup to initialize data *\/\r\n  _sidata = .;\r\n\r\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\r\n  .data : AT ( _sidata )\r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .;        \/* create a global symbol at data start *\/\r\n    *(.data)           \/* .data sections *\/\r\n    *(.data*)          \/* .data* sections *\/\r\n\r\n    . = ALIGN(4);\r\n    _edata = .;        \/* define a global symbol at data end *\/\r\n  } >RAM\r\n\r\n  \/* Uninitialized data section *\/\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n    _sbss = .;         \/* define a global symbol at bss start *\/\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .;         \/* define a global symbol at bss end *\/\r\n    __bss_end__ = _ebss;\r\n  } >RAM\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    \/* Should this be _ebss?*\/\r\n    PROVIDE ( _exit = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(4);\r\n  } >RAM\r\n\r\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\r\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\r\n  .memory_b1_text :\r\n  {\r\n    *(.mb1text)        \/* .mb1text sections (code) *\/\r\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\r\n    *(.mb1rodata)      \/* read-only data (constants) *\/\r\n    *(.mb1rodata*)\r\n  } >MEMORY_B1\r\n\r\n  \/* Remove information from the standard libraries *\/\r\n  \/DISCARD\/ :\r\n  {\r\n    libc.a ( * )\r\n    libm.a ( * )\r\n    libgcc.a ( * )\r\n  }\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"cb72db2249a1d0fba25e87b08c2aadeaba059eeb","subject":"fixed wrong __StackTop calculation","message":"fixed wrong __StackTop calculation\n\nStackTop calculation was not adjusted when ram size was increased by using al 3 ram regions.\nThis caused memory allocation failures althogh enough free heap was reported\n","repos":"andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os","old_file":"targets\/TARGET_NXP\/TARGET_LPC15XX\/device\/TOOLCHAIN_GCC_ARM\/LPC1549.ld","new_file":"targets\/TARGET_NXP\/TARGET_LPC15XX\/device\/TOOLCHAIN_GCC_ARM\/LPC1549.ld","new_contents":"\/* Linker script for mbed LPC1549 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  \/* Define each memory region *\/\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\n  Ram0_16 (rwx) : ORIGIN = 0x2000000 + 0x100, LENGTH = (16K - 0x100)\n  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 16K\n  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 4K\n\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > Ram0_16\n\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > Ram0_16\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > Ram0_16\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > Ram0_16\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(Ram0_16) + LENGTH(Ram0_16) + LENGTH(Ram1_16) + LENGTH(Ram2_4);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for mbed LPC1549 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  \/* Define each memory region *\/\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\n  Ram0_16 (rwx) : ORIGIN = 0x2000000 + 0x100, LENGTH = (16K - 0x100)\n  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 16K\n  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 4K\n\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        Image$$RW_IRAM1$$Base = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > Ram0_16\n\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$RW_IRAM1$$ZI$$Limit = . ;\n    } > Ram0_16\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > Ram0_16\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > Ram0_16\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(Ram0_16) + LENGTH(Ram0_16);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"afe93256eb4bdcbf9479a774dad777b68047aae5","subject":"0xCC padding","message":"0xCC padding\n","repos":"CRust-OS\/CRust-OS,CRust-OS\/CRust-OS,CRust-OS\/CRust-OS,CRust-OS\/CRust-OS","old_file":"crust.lds","new_file":"crust.lds","new_contents":"ENTRY(_start)\n\n\/* all sections are padded with 0xCC (int 3, meaning breakpoint) in case we accidentally jump into uninitialized memory *\/\n\nSECTIONS {\n    .bss : ALIGN(0x1000) {\n        HYPERCALL_PAGE = .;\n        . += 0x1000;\n        STACK_TOP = .;\n        . += 0x2000;\n        STACK_BOTTOM = .;\n        *(.bss);\n        *(.bss.*);\n    } = 0xCC \n    .text : ALIGN(0x1000) {\n        *(.text);\n        *(.text.*);\n    } = 0xCC\n    .data : ALIGN(0x1000) {\n        *(.data);\n        *(.data.*);\n    } = 0xCC\n    .note : {\n        *(.note);\n        *(.note.*);\n    }\n}\n","old_contents":"ENTRY(_start)\nSECTIONS {\n    .bss : ALIGN(0x1000) {\n        HYPERCALL_PAGE = .;\n        . += 0x1000;\n        STACK_TOP = .;\n        . += 0x2000;\n        STACK_BOTTOM = .;\n        *(.bss);\n        *(.bss.*);\n    }\n    .text : ALIGN(0x1000) {\n        *(.text);\n        *(.text.*);\n    }\n    .data : ALIGN(0x1000) {\n        *(.data);\n        *(.data.*);\n    }\n    .note : {\n        *(.note);\n        *(.note.*);\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e38fcc95170e3559a17fca37ac2544cf7e6155ed","subject":"kernel linkage editor script fixes","message":"kernel linkage editor script fixes\n\nthe section alignments were very messed up\n","repos":"stoyan-shopov\/dt,stoyan-shopov\/dt","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"MEMORY\n{\n\trom (rx)\t:\tORIGIN = 0x50000, LENGTH = 0xa0000 - 0x50000\n\tram (rwx)\t:\tORIGIN = 0x100000, LENGTH = 0x100000\n}\n\nSECTIONS\n{\n\t.text\t\t: { *(.text) } > rom\n\t.init_startup ALIGN(8) : \n\t{\n\t\t_init_startup\t\t= .;\n\t\t*(.ctors)\n\t\t_init_startup_end\t= .;\n\t} > rom\n\t.x86_idt ALIGN(8)\t: { *(.x86_idt) } > rom\n\t.rodata ALIGN(8)\t: {\n\t\t*(.rodata)\n\t\t_idata_contents_start\t= .;\n\t} > rom\n\n\t.init_pgdir_tab :\n\t{\n\t\t*(.init_pgdir)\n\t} > ram\n\n\t.common-data ALIGN(1024)\t:\n\t{\n\t\t*(.common-data)\n\t} > ram\n\n\t.data ALIGN(1024)\t:\n\t{\n\t\t_data_start\t= .;\n\t\t*(.data)\n\t\t_data_end\t= .;\n\t} > ram AT> rom\n\n\t.bss ALIGN(1024) :\n\t{\n\t\t_bss_start = . ;\n\t\t*(.bss .bss*)\n\t\t_bss_end = . ;\n\t} > ram\n\n\t\/DISCARD\/ : \n\t{\n\t\t\t*(.eh_frame*)\n\t}\n}\n","old_contents":"MEMORY\n{\n\trom (rx)\t:\tORIGIN = 0x50000, LENGTH = 0xa0000 - 0x50000\n\tram (rwx)\t:\tORIGIN = 0x100000, LENGTH = 0x100000\n}\n\nSECTIONS\n{\n\t.text\t\t: { *(.text) } > rom\n\t.\t=\tALIGN(8);\n\t.init_startup : \n\t{\n\t\t_init_startup\t\t= .;\n\t\t*(.ctors)\n\t\t_init_startup_end\t= .;\n\t} > rom\n\t.\t=\tALIGN(8);\n\t.x86_idt\t: { *(.x86_idt) } > rom\n\t.\t=\tALIGN(8);\n\t.rodata\t\t: {\n\t\t*(.rodata)\n\t\t.\t=\tALIGN(8);\n\t\t_idata_contents_start\t= .;\n\t} > rom\n\n\t.init_pgdir_tab\t:\n\t{\n\t\t.\t=\tALIGN(4096);\n\t\t*(.init_pgdir)\n\t} > ram\n\n\t.common-data\t:\n\t{\n\t\t.\t=\tALIGN(4096);\n\t\t*(.common-data)\n\t} > ram\n\n\t.data\t:\n\t{\n\t\t.\t=\tALIGN(4096);\n\t\t_data_start\t= .;\n\t\t*(.data)\n\t\t_data_end\t= .;\n\t} > ram AT> rom\n\n\t.\t=\tALIGN(8);\n\t.bss :\n\t{\n\t\t_bss_start = . ;\n\t\t*(.bss .bss*)\n\t\t_bss_end = . ;\n\t} > ram\n\n\t\/DISCARD\/ : \n\t{\n\t\t\t*(.eh_frame*)\n\t\t\t*(.drectve*)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"111098568ae6191262f3bb301459bee93b075dab","subject":"esp32c3: Reserve RTC memory from bootloader in the app linker script","message":"esp32c3: Reserve RTC memory from bootloader in the app linker script\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp32c3\/ld\/esp32c3.ld","new_file":"components\/esp32c3\/ld\/esp32c3.ld","new_contents":"\/**\n *                    ESP32-C3 Linker Script Memory Layout\n * This file describes the memory layout (memory blocks) by virtual memory addresses.\n * This linker script is passed through the C preprocessor to include configuration options.\n * Please use preprocessor features sparingly!\n * Restrict to simple macros with numeric values, and\/or #if\/#endif blocks.\n *\/\n\n#include \"sdkconfig.h\"\n\n#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC\n#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)\n#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)\n#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)\n#else\n#define ESP_BOOTLOADER_RESERVE_RTC 0\n#endif\n\n#define SRAM_IRAM_START     0x4037C000\n#define SRAM_DRAM_START     0x3FC7C000\n#define ICACHE_SIZE         0x4000 \/* ICache size is fixed to 16KB on ESP32-C3 *\/\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)\n\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n#if CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE\nASSERT((CONFIG_ESP32C3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), \"Fixed static ram data does not fit.\")\n#define DRAM0_0_SEG_LEN CONFIG_ESP3C3_FIXED_STATIC_RAM_SIZE\n#else\n#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE\n#endif \/\/ CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE\nMEMORY\n{\n  \/**\n   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n   *  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n   *  are connected to the data port of the CPU and eg allow byte-wise access.\n   *\/\n\n  \/* IRAM for PRO CPU. *\/\n  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped instruction data *\/\n  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x8000000-0x20\n\n  \/**\n   * (0x20 offset above is a convenience for the app binary image generation.\n   * Flash cache has 64KB pages. The .bin file which is flashed to the chip\n   * has a 0x18 byte file header, and each segment has a 0x08 byte segment\n   * header. Setting this offset makes it simple to meet the flash cache MMU's\n   * constraint that (paddr % 64KB == vaddr % 64KB).)\n   *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.\n   *\/\n  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x8000000-0x20\n\n  \/* (See iram0_2_seg for meaning of 0x20 offset in the above.) *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x50000000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC\n}\n\n#if CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE\n\/* static data ends at defined address *\/\n_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;\n#else\n_static_data_end = _bss_end;\n#endif \/\/ CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000;\n\n_data_seg_org = ORIGIN(rtc_data_seg);\n\n\/**\n *  The lines below define location alias for .rtc.data section\n *  As C3 only has RTC fast memory, this is not configurable like on other targets\n *\/\nREGION_ALIAS(\"rtc_data_seg\", rtc_iram_seg );\nREGION_ALIAS(\"rtc_slow_seg\", rtc_iram_seg );\nREGION_ALIAS(\"rtc_data_location\", rtc_iram_seg );\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  REGION_ALIAS(\"default_code_seg\", iram0_2_seg);\n#else\n  REGION_ALIAS(\"default_code_seg\", iram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  REGION_ALIAS(\"default_rodata_seg\", drom0_0_seg);\n#else\n  REGION_ALIAS(\"default_rodata_seg\", dram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n","old_contents":"\/**\n *                    ESP32-C3 Linker Script Memory Layout\n * This file describes the memory layout (memory blocks) by virtual memory addresses.\n * This linker script is passed through the C preprocessor to include configuration options.\n * Please use preprocessor features sparingly!\n * Restrict to simple macros with numeric values, and\/or #if\/#endif blocks.\n *\/\n\n#include \"sdkconfig.h\"\n\n#define SRAM_IRAM_START     0x4037C000\n#define SRAM_DRAM_START     0x3FC7C000\n#define ICACHE_SIZE         0x4000 \/* ICache size is fixed to 16KB on ESP32-C3 *\/\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)\n\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n#if CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE\nASSERT((CONFIG_ESP32C3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), \"Fixed static ram data does not fit.\")\n#define DRAM0_0_SEG_LEN CONFIG_ESP3C3_FIXED_STATIC_RAM_SIZE\n#else\n#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE\n#endif \/\/ CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE\nMEMORY\n{\n  \/**\n   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n   *  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n   *  are connected to the data port of the CPU and eg allow byte-wise access.\n   *\/\n\n  \/* IRAM for PRO CPU. *\/\n  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped instruction data *\/\n  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x8000000-0x20\n\n  \/**\n   * (0x20 offset above is a convenience for the app binary image generation.\n   * Flash cache has 64KB pages. The .bin file which is flashed to the chip\n   * has a 0x18 byte file header, and each segment has a 0x08 byte segment\n   * header. Setting this offset makes it simple to meet the flash cache MMU's\n   * constraint that (paddr % 64KB == vaddr % 64KB).)\n   *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.\n   *\/\n  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x8000000-0x20\n\n  \/* (See iram0_2_seg for meaning of 0x20 offset in the above.) *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x50000000, len = 0x2000\n}\n\n#if CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE\n\/* static data ends at defined address *\/\n_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;\n#else\n_static_data_end = _bss_end;\n#endif \/\/ CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000;\n\n_data_seg_org = ORIGIN(rtc_data_seg);\n\n\/**\n *  The lines below define location alias for .rtc.data section\n *  As C3 only has RTC fast memory, this is not configurable like on other targets\n *\/\nREGION_ALIAS(\"rtc_data_seg\", rtc_iram_seg );\nREGION_ALIAS(\"rtc_slow_seg\", rtc_iram_seg );\nREGION_ALIAS(\"rtc_data_location\", rtc_iram_seg );\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  REGION_ALIAS(\"default_code_seg\", iram0_2_seg);\n#else\n  REGION_ALIAS(\"default_code_seg\", iram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  REGION_ALIAS(\"default_rodata_seg\", drom0_0_seg);\n#else\n  REGION_ALIAS(\"default_rodata_seg\", dram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f93b3d1947396a41365b4a5500be965899ff8e8e","subject":"arch: arm: fix linker script title comment","message":"arch: arm: fix linker script title comment\n\nFix the title comment in the linker.ld script for ARM, to\nmake it clear that this is the common linker script for all\nCortex-M based platforms.\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\n","repos":"explora26\/zephyr,punitvara\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,Vudentz\/zephyr,ldts\/zephyr,finikorg\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,punitvara\/zephyr,ldts\/zephyr,kraj\/zephyr,kraj\/zephyr,finikorg\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,explora26\/zephyr,explora26\/zephyr,punitvara\/zephyr,kraj\/zephyr,galak\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,punitvara\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,explora26\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,kraj\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,ldts\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n#include <app_data_alignment.ld>\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n#include <app_data_alignment.ld>\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"253e4a8c68439da89e767dfd060d2425936f108a","subject":"updated layout file to use X and W","message":"updated layout file to use X and W\n","repos":"tock\/libtock-rs","old_file":"runtime\/layouts\/microbit_v2.ld","new_file":"runtime\/layouts\/microbit_v2.ld","new_contents":"\/* Layout for the micro:bit v2 board, used by the examples in this repository. *\/\n\nMEMORY {\n  FLASH (X) : ORIGIN = 0x00040000, LENGTH = 256K\n  RAM (W) : ORIGIN = 0x20004000, LENGTH = 112K\n}\n\nTBF_HEADER_SIZE = 0x48;\nINCLUDE libtock_layout.ld\n","old_contents":"\/* Layout for the micro:bit v2 board, used by the examples in this repository. *\/\n\nMEMORY {\n  FLASH (rx) : ORIGIN = 0x00040000, LENGTH = 256K\n  RAM (rwx) : ORIGIN = 0x20004000, LENGTH = 112K\n}\n\nMPU_MIN_ALIGN = 8K;\n\nTBF_HEADER_SIZE = 0x48;\nINCLUDE libtock_layout.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7fbd07114922c1d132e323f7bea14126b336f86e","subject":"added copyright statement","message":"added copyright statement\n","repos":"DavidNorman\/tensorflow,karllessard\/tensorflow,jbedorf\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_saved_model,jhseu\/tensorflow,alsrgv\/tensorflow,hfp\/tensorflow-xsmm,xzturn\/tensorflow,alsrgv\/tensorflow,chemelnucfin\/tensorflow,adit-chandra\/tensorflow,xzturn\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow,theflofly\/tensorflow,apark263\/tensorflow,chemelnucfin\/tensorflow,aam-at\/tensorflow,alsrgv\/tensorflow,petewarden\/tensorflow,ppwwyyxx\/tensorflow,davidzchen\/tensorflow,petewarden\/tensorflow,paolodedios\/tensorflow,chemelnucfin\/tensorflow,jhseu\/tensorflow,yongtang\/tensorflow,jbedorf\/tensorflow,arborh\/tensorflow,xzturn\/tensorflow,hfp\/tensorflow-xsmm,frreiss\/tensorflow-fred,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,alsrgv\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow,ageron\/tensorflow,petewarden\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,ppwwyyxx\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,freedomtan\/tensorflow,adit-chandra\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,cxxgtxy\/tensorflow,Intel-Corporation\/tensorflow,renyi533\/tensorflow,alsrgv\/tensorflow,jbedorf\/tensorflow,ageron\/tensorflow,apark263\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,annarev\/tensorflow,ghchinoy\/tensorflow,gautam1858\/tensorflow,aam-at\/tensorflow,adit-chandra\/tensorflow,arborh\/tensorflow,adit-chandra\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,renyi533\/tensorflow,theflofly\/tensorflow,frreiss\/tensorflow-fred,apark263\/tensorflow,kevin-coder\/tensorflow-fork,DavidNorman\/tensorflow,renyi533\/tensorflow,ageron\/tensorflow,aldian\/tensorflow,xzturn\/tensorflow,arborh\/tensorflow,annarev\/tensorflow,davidzchen\/tensorflow,chemelnucfin\/tensorflow,aldian\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,apark263\/tensorflow,frreiss\/tensorflow-fred,petewarden\/tensorflow,aam-at\/tensorflow,hfp\/tensorflow-xsmm,theflofly\/tensorflow,yongtang\/tensorflow,arborh\/tensorflow,arborh\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-experimental_link_static_libraries_once,alsrgv\/tensorflow,ppwwyyxx\/tensorflow,gunan\/tensorflow,ppwwyyxx\/tensorflow,kevin-coder\/tensorflow-fork,gunan\/tensorflow,gunan\/tensorflow,chemelnucfin\/tensorflow,aldian\/tensorflow,cxxgtxy\/tensorflow,DavidNorman\/tensorflow,Intel-tensorflow\/tensorflow,jbedorf\/tensorflow,jbedorf\/tensorflow,alsrgv\/tensorflow,ageron\/tensorflow,yongtang\/tensorflow,jbedorf\/tensorflow,ghchinoy\/tensorflow,gautam1858\/tensorflow,gunan\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,davidzchen\/tensorflow,frreiss\/tensorflow-fred,xzturn\/tensorflow,yongtang\/tensorflow,theflofly\/tensorflow,jendap\/tensorflow,theflofly\/tensorflow,jhseu\/tensorflow,jendap\/tensorflow,tensorflow\/tensorflow,paolodedios\/tensorflow,jendap\/tensorflow,sarvex\/tensorflow,apark263\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,annarev\/tensorflow,arborh\/tensorflow,davidzchen\/tensorflow,Intel-tensorflow\/tensorflow,ppwwyyxx\/tensorflow,paolodedios\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow,theflofly\/tensorflow,jhseu\/tensorflow,gautam1858\/tensorflow,ageron\/tensorflow,karllessard\/tensorflow,sarvex\/tensorflow,ppwwyyxx\/tensorflow,ghchinoy\/tensorflow,jendap\/tensorflow,hfp\/tensorflow-xsmm,aam-at\/tensorflow,apark263\/tensorflow,ghchinoy\/tensorflow,annarev\/tensorflow,DavidNorman\/tensorflow,annarev\/tensorflow,jendap\/tensorflow,ageron\/tensorflow,DavidNorman\/tensorflow,karllessard\/tensorflow,alsrgv\/tensorflow,gunan\/tensorflow,Intel-Corporation\/tensorflow,aldian\/tensorflow,sarvex\/tensorflow,xzturn\/tensorflow,jhseu\/tensorflow,adit-chandra\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,frreiss\/tensorflow-fred,alsrgv\/tensorflow,yongtang\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_tf_optimizer,xzturn\/tensorflow,ppwwyyxx\/tensorflow,ageron\/tensorflow,davidzchen\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-experimental_link_static_libraries_once,renyi533\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,jendap\/tensorflow,aam-at\/tensorflow,sarvex\/tensorflow,ppwwyyxx\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,petewarden\/tensorflow,gunan\/tensorflow,renyi533\/tensorflow,DavidNorman\/tensorflow,hfp\/tensorflow-xsmm,theflofly\/tensorflow,ageron\/tensorflow,theflofly\/tensorflow,DavidNorman\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow,ghchinoy\/tensorflow,theflofly\/tensorflow,davidzchen\/tensorflow,gunan\/tensorflow,davidzchen\/tensorflow,gautam1858\/tensorflow,karllessard\/tensorflow,yongtang\/tensorflow,freedomtan\/tensorflow,aam-at\/tensorflow,hfp\/tensorflow-xsmm,freedomtan\/tensorflow,ghchinoy\/tensorflow,adit-chandra\/tensorflow,jhseu\/tensorflow,DavidNorman\/tensorflow,Intel-Corporation\/tensorflow,karllessard\/tensorflow,ghchinoy\/tensorflow,ppwwyyxx\/tensorflow,chemelnucfin\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow,yongtang\/tensorflow,apark263\/tensorflow,jendap\/tensorflow,paolodedios\/tensorflow,arborh\/tensorflow,renyi533\/tensorflow,DavidNorman\/tensorflow,ageron\/tensorflow,freedomtan\/tensorflow,freedomtan\/tensorflow,Intel-Corporation\/tensorflow,freedomtan\/tensorflow,adit-chandra\/tensorflow,aldian\/tensorflow,kevin-coder\/tensorflow-fork,kevin-coder\/tensorflow-fork,jbedorf\/tensorflow,tensorflow\/tensorflow,ghchinoy\/tensorflow,annarev\/tensorflow,jendap\/tensorflow,kevin-coder\/tensorflow-fork,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,yongtang\/tensorflow,annarev\/tensorflow,cxxgtxy\/tensorflow,chemelnucfin\/tensorflow,ghchinoy\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,gautam1858\/tensorflow,renyi533\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,aldian\/tensorflow,jhseu\/tensorflow,arborh\/tensorflow,freedomtan\/tensorflow,jbedorf\/tensorflow,jendap\/tensorflow,kevin-coder\/tensorflow-fork,gautam1858\/tensorflow,paolodedios\/tensorflow,renyi533\/tensorflow,ppwwyyxx\/tensorflow,jbedorf\/tensorflow,paolodedios\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gunan\/tensorflow,sarvex\/tensorflow,Intel-tensorflow\/tensorflow,ageron\/tensorflow,DavidNorman\/tensorflow,adit-chandra\/tensorflow,yongtang\/tensorflow,gunan\/tensorflow,aldian\/tensorflow,Intel-tensorflow\/tensorflow,jendap\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,kevin-coder\/tensorflow-fork,freedomtan\/tensorflow,annarev\/tensorflow,cxxgtxy\/tensorflow,theflofly\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,arborh\/tensorflow,kevin-coder\/tensorflow-fork,theflofly\/tensorflow,freedomtan\/tensorflow,petewarden\/tensorflow,Intel-Corporation\/tensorflow,renyi533\/tensorflow,jhseu\/tensorflow,jhseu\/tensorflow,karllessard\/tensorflow,frreiss\/tensorflow-fred,frreiss\/tensorflow-fred,davidzchen\/tensorflow,adit-chandra\/tensorflow,xzturn\/tensorflow,davidzchen\/tensorflow,adit-chandra\/tensorflow,tensorflow\/tensorflow,apark263\/tensorflow,gautam1858\/tensorflow,jhseu\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,gunan\/tensorflow,adit-chandra\/tensorflow,renyi533\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,cxxgtxy\/tensorflow,jhseu\/tensorflow,davidzchen\/tensorflow,arborh\/tensorflow,sarvex\/tensorflow,hfp\/tensorflow-xsmm,tensorflow\/tensorflow-experimental_link_static_libraries_once,chemelnucfin\/tensorflow,jbedorf\/tensorflow,jbedorf\/tensorflow,arborh\/tensorflow,xzturn\/tensorflow,petewarden\/tensorflow,ghchinoy\/tensorflow,aam-at\/tensorflow,ageron\/tensorflow,jhseu\/tensorflow,aam-at\/tensorflow,chemelnucfin\/tensorflow,yongtang\/tensorflow,alsrgv\/tensorflow,aam-at\/tensorflow,apark263\/tensorflow,apark263\/tensorflow,Intel-tensorflow\/tensorflow,jbedorf\/tensorflow,freedomtan\/tensorflow,xzturn\/tensorflow,ghchinoy\/tensorflow,adit-chandra\/tensorflow,gunan\/tensorflow,freedomtan\/tensorflow,kevin-coder\/tensorflow-fork,frreiss\/tensorflow-fred,hfp\/tensorflow-xsmm,ppwwyyxx\/tensorflow,aam-at\/tensorflow,renyi533\/tensorflow,sarvex\/tensorflow,petewarden\/tensorflow,aam-at\/tensorflow,petewarden\/tensorflow,gautam1858\/tensorflow,kevin-coder\/tensorflow-fork,annarev\/tensorflow,freedomtan\/tensorflow,davidzchen\/tensorflow,gautam1858\/tensorflow,frreiss\/tensorflow-fred,arborh\/tensorflow,ageron\/tensorflow,xzturn\/tensorflow,hfp\/tensorflow-xsmm,gunan\/tensorflow,davidzchen\/tensorflow,ghchinoy\/tensorflow,hfp\/tensorflow-xsmm,Intel-tensorflow\/tensorflow,renyi533\/tensorflow,aldian\/tensorflow,chemelnucfin\/tensorflow,Intel-tensorflow\/tensorflow,alsrgv\/tensorflow,theflofly\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,chemelnucfin\/tensorflow,frreiss\/tensorflow-fred,petewarden\/tensorflow,sarvex\/tensorflow,petewarden\/tensorflow,paolodedios\/tensorflow,annarev\/tensorflow,apark263\/tensorflow,gautam1858\/tensorflow,kevin-coder\/tensorflow-fork,hfp\/tensorflow-xsmm,Intel-Corporation\/tensorflow,DavidNorman\/tensorflow,chemelnucfin\/tensorflow,gautam1858\/tensorflow,karllessard\/tensorflow,annarev\/tensorflow,jendap\/tensorflow,DavidNorman\/tensorflow,cxxgtxy\/tensorflow,alsrgv\/tensorflow,aam-at\/tensorflow,xzturn\/tensorflow","old_file":"tensorflow\/lite\/experimental\/micro\/tools\/make\/targets\/ecm3531\/ecm3531.lds","new_file":"tensorflow\/lite\/experimental\/micro\/tools\/make\/targets\/ecm3531\/ecm3531.lds","new_contents":"\/* Copyright 2015 The TensorFlow Authors. All Rights Reserved.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n==============================================================================*\/\n\n\n\/*\n * linker script for use with ECM3531\n * All sections must map to 128KBytes of SRAM beginning at 0x10000000\n *\n *\/\n\n \/*\n  * Indicate to the linker the entry point.\n  *\/\nENTRY(ResetISR)\n\n\/*\n *   SRAM is at 0x10000000 of length 0x00020000\n *\/\nMEMORY\n{\n    SRAM (RWX) : ORIGIN = 0x10000000, LENGTH = 0x00020000\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        . = ALIGN(0x4);\n        *(.text*)\n        . = ALIGN(0x4);\n        *(.rodata*)\n        . = ALIGN(0x4);\n        _etext = .;\n    } > SRAM= 0\n    .dummy :\n    {\n        . = ALIGN(0x4);\n        _eftext = .;\n    } > SRAM\n    .datax :\n    {\n        _datax = .;\n        KEEP(*(.mainStack))\n        . += 12288;\n        _edatax = .;\n        _stack_top = .;\n        . += 4;\n    } > SRAM\n    .data :\n       AT (ADDR(.text) + SIZEOF(.text) ) \n    {\n        _data = .;\n        *(.data*)\n        KEEP(*(.mainHeap))\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n    .ARM.exidx :\n    {\n       *(.ARM.exidx*)\n    }\n\n}\n\n","old_contents":"\/*******************************************************************************\n *\n * Copyright (C) 2018 Eta Compute, Inc\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n ******************************************************************************\/\n\n\n\/*\n * linker script for use with ECM3531\n * All sections must map to 128KBytes of SRAM beginning at 0x10000000\n *\n *\/\n\n \/*\n  * Indicate to the linker the entry point.\n  *\/\nENTRY(ResetISR)\n\n\/*\n *   SRAM is at 0x10000000 of length 0x00020000\n *\/\nMEMORY\n{\n    SRAM (RWX) : ORIGIN = 0x10000000, LENGTH = 0x00020000\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        . = ALIGN(0x4);\n        *(.text*)\n        . = ALIGN(0x4);\n        *(.rodata*)\n        . = ALIGN(0x4);\n        _etext = .;\n    } > SRAM= 0\n    .dummy :\n    {\n        . = ALIGN(0x4);\n        _eftext = .;\n    } > SRAM\n    .datax :\n    {\n        _datax = .;\n        KEEP(*(.mainStack))\n        . += 12288;\n        _edatax = .;\n        _stack_top = .;\n        . += 4;\n    } > SRAM\n    .data :\n       AT (ADDR(.text) + SIZEOF(.text) ) \n    {\n        _data = .;\n        *(.data*)\n        KEEP(*(.mainHeap))\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n    .ARM.exidx :\n    {\n       *(.ARM.exidx*)\n    }\n\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e48b2c681e9d7eaf07f3e1d4125ab24872645f32","subject":"fixed definitions for stack areas","message":"fixed definitions for stack areas\n","repos":"hathach\/tinyusb,hathach\/tinyusb,hathach\/tinyusb","old_file":"hw\/bsp\/gr_citrus\/r5f5631fd.ld","new_file":"hw\/bsp\/gr_citrus\/r5f5631fd.ld","new_contents":"__USTACK_SIZE = 0x00000200;\n__ISTACK_SIZE = 0x00000200;\n\nMEMORY\n{\n\tRAM : ORIGIN = 0x4,        LENGTH = 0x3fffc\n\tROM : ORIGIN = 0xFFE00000, LENGTH = 0x200000\n}\nSECTIONS\n{\n\t.fvectors 0xFFFFFF80: AT(0xFFFFFF80)\n\t{\n\t\tKEEP(*(.fvectors))\n\t} > ROM\n\t.text 0xFFE00000: AT(0xFFE00000)\n\t{\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(P)\n\t\tetext = .;\n\t} > ROM\n\t.rvectors ALIGN(4):\n\t{\n\t\t_rvectors_start = .;\n\t\tKEEP(*(.rvectors))\n\t\t_rvectors_end = .;\n\t} > ROM\n\t.init :\n\t{\n\t\tKEEP(*(.init))\n\t\t__preinit_array_start = .;\n\t\tKEEP(*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t\t__init_array_start = (. + 3) & ~ 3;\n\t\tKEEP(*(.init_array))\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\t__init_array_end = .;\n\t\t__fini_array_start = .;\n\t\tKEEP(*(.fini_array))\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\t} > ROM\n\t.fini :\n\t{\n\t\tKEEP(*(.fini))\n\t} > ROM\n\t.got :\n\t{\n\t\t*(.got)\n\t\t*(.got.plt)\n\t} > ROM\n\t.rodata :\n\t{\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(C_1)\n\t\t*(C_2)\n\t\t*(C)\n\t\t_erodata = .;\n\t} > ROM\n\t.eh_frame_hdr :\n\t{\n\t\t*(.eh_frame_hdr)\n\t} > ROM\n\t.eh_frame :\n\t{\n\t\t*(.eh_frame)\n\t} > ROM\n\t.jcr :\n\t{\n\t\t*(.jcr)\n\t} > ROM\n\t.tors :\n\t{\n\t\t__CTOR_LIST__ = .;\n\t\t. = ALIGN(2);\n\t\t___ctors = .;\n\t\t*(.ctors)\n\t\t___ctors_end = .;\n\t\t__CTOR_END__ = .;\n\t\t__DTOR_LIST__ = .;\n\t\t___dtors = .;\n\t\t*(.dtors)\n\t\t___dtors_end = .;\n\t\t__DTOR_END__ = .;\n\t\t. = ALIGN(2);\n\t\t_mdata = .;\n\t} > ROM\n\t.data : AT(_mdata)\n\t{\n\t\t_data = .;\n\t\t*(.data)\n\t\t*(.data.*)\n\t\t*(D)\n\t\t*(D_1)\n\t\t*(D_2)\n\t\t_edata = .;\n\t} > RAM\n\t.gcc_exc :\n\t{\n\t\t*(.gcc_exc)\n\t} > RAM\n\t.bss :\n\t{\n\t\t_bss = .;\n\t\t*(.bss)\n\t\t*(.bss.**)\n\t\t*(COMMON)\n\t\t*(B)\n\t\t*(B_1)\n\t\t*(B_2)\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > RAM\n\t.ustack :\n\t{\n\t\t. = ALIGN(8);\n\t\t. = . + __USTACK_SIZE;\n\t\tPROVIDE(_ustack = .);\n\t} > RAM\n\t.istack :\n\t{\n\t\t. = ALIGN(8);\n\t\t. = . + __ISTACK_SIZE;\n\t\tPROVIDE(_istack = .);\n\t} > RAM\n}\n","old_contents":"__USTACK_SIZE = 0x00000200;\n__ISTACK_SIZE = 0x00000100;\n\nMEMORY\n{\n\tRAM : ORIGIN = 0x4,        LENGTH = 0x3fffc\n\tROM : ORIGIN = 0xFFE00000, LENGTH = 0x200000\n}\nSECTIONS\n{\n\t.fvectors 0xFFFFFF80: AT(0xFFFFFF80)\n\t{\n\t\tKEEP(*(.fvectors))\n\t} > ROM\n\t.text 0xFFE00000: AT(0xFFE00000)\n\t{\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(P)\n\t\tetext = .;\n\t} > ROM\n\t.rvectors ALIGN(4):\n\t{\n\t\t_rvectors_start = .;\n\t\tKEEP(*(.rvectors))\n\t\t_rvectors_end = .;\n\t} > ROM\n\t.init :\n\t{\n\t\tKEEP(*(.init))\n\t\t__preinit_array_start = .;\n\t\tKEEP(*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t\t__init_array_start = (. + 3) & ~ 3;\n\t\tKEEP(*(.init_array))\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\t__init_array_end = .;\n\t\t__fini_array_start = .;\n\t\tKEEP(*(.fini_array))\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\t} > ROM\n\t.fini :\n\t{\n\t\tKEEP(*(.fini))\n\t} > ROM\n\t.got :\n\t{\n\t\t*(.got)\n\t\t*(.got.plt)\n\t} > ROM\n\t.rodata :\n\t{\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(C_1)\n\t\t*(C_2)\n\t\t*(C)\n\t\t_erodata = .;\n\t} > ROM\n\t.eh_frame_hdr :\n\t{\n\t\t*(.eh_frame_hdr)\n\t} > ROM\n\t.eh_frame :\n\t{\n\t\t*(.eh_frame)\n\t} > ROM\n\t.jcr :\n\t{\n\t\t*(.jcr)\n\t} > ROM\n\t.tors :\n\t{\n\t\t__CTOR_LIST__ = .;\n\t\t. = ALIGN(2);\n\t\t___ctors = .;\n\t\t*(.ctors)\n\t\t___ctors_end = .;\n\t\t__CTOR_END__ = .;\n\t\t__DTOR_LIST__ = .;\n\t\t___dtors = .;\n\t\t*(.dtors)\n\t\t___dtors_end = .;\n\t\t__DTOR_END__ = .;\n\t\t. = ALIGN(2);\n\t\t_mdata = .;\n\t} > ROM\n\t.data : AT(_mdata)\n\t{\n\t\t_data = .;\n\t\t*(.data)\n\t\t*(.data.*)\n\t\t*(D)\n\t\t*(D_1)\n\t\t*(D_2)\n\t\t_edata = .;\n\t} > RAM\n\t.gcc_exc :\n\t{\n\t\t*(.gcc_exc)\n\t} > RAM\n\t.bss :\n\t{\n\t\t_bss = .;\n\t\t*(.bss)\n\t\t*(.bss.**)\n\t\t*(COMMON)\n\t\t*(B)\n\t\t*(B_1)\n\t\t*(B_2)\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > RAM\n\t.ustack (COPY) :\n\t{\n\t\t. = ALIGN(8);\n\t\t. = . + __USTACK_SIZE;\n\t\tPROVIDE(_ustack = .);\n\t} > RAM\n\t.istack (COPY) :\n\t{\n\t\t. = ALIGN(8);\n\t\t. = . + __ISTACK_SIZE;\n\t\tPROVIDE(_istack = .);\n\t} > RAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c230e4280c039b0b709d54e974f63eed358c1c2a","subject":"linker scripts: Limit DROM\/IROM section lengths correctly","message":"linker scripts: Limit DROM\/IROM section lengths correctly\n","repos":"nineisk\/esp-idf,nineisk\/esp-idf,espressif\/esp-idf,ajs124\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,MIhanguangyi\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,Hermiedapwdrman\/esp-idf,empoweredhomes\/esp-idf,nineisk\/esp-idf,nineisk\/esp-idf,armada-ai\/esp-idf,ajs124\/esp-idf,MIhanguangyi\/esp-idf,jaracil\/esp-idf,dschaefer\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,www220\/esp-idf,MIhanguangyi\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,dschaefer\/esp-idf,armada-ai\/esp-idf,dschaefer\/esp-idf,dschaefer\/esp-idf,empoweredhomes\/esp-idf,MIhanguangyi\/esp-idf,Hermiedapwdrman\/esp-idf,shukyisme\/esp-idf-kwik,jaracil\/esp-idf,www220\/esp-idf,Hermiedapwdrman\/esp-idf,mashaoze\/esp-idf,shukyisme\/esp-idf-kwik,jaracil\/esp-idf,Hermiedapwdrman\/esp-idf,ajs124\/esp-idf,www220\/esp-idf,ajs124\/esp-idf,empoweredhomes\/esp-idf,jaracil\/esp-idf,Hermiedapwdrman\/esp-idf,shukyisme\/esp-idf-kwik,dschaefer\/esp-idf,armada-ai\/esp-idf,espressif\/esp-idf,empoweredhomes\/esp-idf,empoweredhomes\/esp-idf,espressif\/esp-idf,MIhanguangyi\/esp-idf,shukyisme\/esp-idf-kwik,shukyisme\/esp-idf-kwik","old_file":"components\/esp32\/ld\/esp32.ld","new_file":"components\/esp32\/ld\/esp32.ld","new_contents":"\/* ESP32 Linker Script Memory Layout\n\n   This file describes the memory layout (memory blocks) as virtual\n   memory addresses.\n\n   esp32.common.ld contains output sections to link compiler output\n   into these memory blocks.\n\n   ***\n\n   This linker script is passed through the C preprocessor to include\n   configuration options.\n\n   Please use preprocessor features sparingly! Restrict\n   to simple macros with numeric values, and\/or #if\/#endif blocks.\n*\/\n#include \"sdkconfig.h\"\n\nMEMORY\n{\n  \/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n  are connected to the data port of the CPU and eg allow bytewise access. *\/\n\n  \/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... *\/\n  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000\n\n  \/* Even though the segment name is iram, it is actually mapped to flash *\/\n  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000-0x18\n\n  \/* Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n\n     Enabling Bluetooth & Trace Memory features in menuconfig will decrease\n     the amount of RAM available.\n  *\/\n  dram0_0_seg (RW) :                 org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,\n                                     len = 0x50000 - CONFIG_TRACEMEM_RESERVE_DRAM - CONFIG_BT_RESERVE_DRAM\n\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3F400018, len = 0x400000-0x18\n\n  \/* RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000\n\n  \/* RTC slow memory (data accessible). Persists over deep sleep.\n\n     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n  *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM\n}\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;\n","old_contents":"\/* ESP32 Linker Script Memory Layout\n\n   This file describes the memory layout (memory blocks) as virtual\n   memory addresses.\n\n   esp32.common.ld contains output sections to link compiler output\n   into these memory blocks.\n\n   ***\n\n   This linker script is passed through the C preprocessor to include\n   configuration options.\n\n   Please use preprocessor features sparingly! Restrict\n   to simple macros with numeric values, and\/or #if\/#endif blocks.\n*\/\n#include \"sdkconfig.h\"\n\nMEMORY\n{\n  \/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n  are connected to the data port of the CPU and eg allow bytewise access. *\/\n\n  \/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... *\/\n  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000\n\n  \/* Even though the segment name is iram, it is actually mapped to flash *\/\n  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000\n\n  \/* Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n\n     Enabling Bluetooth & Trace Memory features in menuconfig will decrease\n     the amount of RAM available.\n  *\/\n  dram0_0_seg (RW) :                 org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,\n                                     len = 0x50000 - CONFIG_TRACEMEM_RESERVE_DRAM - CONFIG_BT_RESERVE_DRAM\n\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3F400018, len = 0x800000\n\n  \/* RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000\n\n  \/* RTC slow memory (data accessible). Persists over deep sleep.\n\n     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n  *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM\n}\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3ee1498b570f892efefacead3227e09b757d983b","subject":"crash data support for NUC472 with gcc_arm","message":"crash data support for NUC472 with gcc_arm\n","repos":"andcor02\/mbed-os,kjbracey-arm\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os","old_file":"targets\/TARGET_NUVOTON\/TARGET_NUC472\/device\/TOOLCHAIN_GCC_ARM\/TARGET_NU_XRAM_SUPPORTED\/NUC472.ld","new_file":"targets\/TARGET_NUVOTON\/TARGET_NUC472\/device\/TOOLCHAIN_GCC_ARM\/TARGET_NU_XRAM_SUPPORTED\/NUC472.ld","new_contents":"\/*\n * Nuvoton NUC472 GCC linker script file\n *\/\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x00000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x00080000\n#endif \n\n#if !defined(MBED_BOOT_STACK_SIZE)\n  #define MBED_BOOT_STACK_SIZE      0x400\n#endif\n\nM_CRASH_DATA_RAM_SIZE = 0x100;\nStackSize = MBED_BOOT_STACK_SIZE;\n\nMEMORY\n{\n    \n  VECTORS (rx)          : ORIGIN = MBED_APP_START, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x00000400\n  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000\n  RAM_EXTERN (rwx)      : ORIGIN = 0x60000000, LENGTH = 0x00100000\n}\n\n\/**\n * Must match cmsis_nvic.h\n *\/\n__vector_size = 4 * (16 + 142);\n \n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(8);\n    } > VECTORS\n\n\n    .text :\n    {\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += StackSize - (. - __StackLimit);\n    } > RAM_INTERN\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Relocate vector table in SRAM *\/\n    .isr_vector.reloc (NOLOAD) :\n    {\n        . = ALIGN(1 << LOG2CEIL(__vector_size));\n        PROVIDE(__start_vector_table__ = .);\n        . += __vector_size;\n        PROVIDE(__end_vector_table__ = .);\n    } > RAM_INTERN\n\n    .crash_data_ram :\n    {\n        . = ALIGN(8);\n        __CRASH_DATA_RAM__ = .;\n        __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n        KEEP(*(.keep.crash_data_ram))\n        *(.m_crash_data_ram)     \/* This is a user defined section *\/\n        . += M_CRASH_DATA_RAM_SIZE;\n        . = ALIGN(8);\n        __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > RAM_INTERN\n\n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM_INTERN AT>FLASH\n\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM_INTERN\n\n    .bss.extern (NOLOAD):\n    {\n        __bss_extern_start__ = .;\n        \/**\n         * Place large .bss* sections into external SRAM if internal SRAM is insufficient.\n         * Such memory arrangement requires initializing .bss.extern section to zero in startup file. Check startup fiile in cmsis-core-* for support or not.\n         *\/\n        *lwip_*.o(.bss*)\n        *lwip_*.o(COMMON)\n        *mesh_system.o(.bss*)\n       __bss_extern_end__ = .;\n    } > RAM_EXTERN\n    \n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM_INTERN\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM_EXTERN) + LENGTH(RAM_EXTERN) - .);\n        __HeapLimit = .;\n    } > RAM_EXTERN\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n}\n","old_contents":"\/*\n * Nuvoton NUC472 GCC linker script file\n *\/\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x00000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x00080000\n#endif \n\n#if !defined(MBED_BOOT_STACK_SIZE)\n  #define MBED_BOOT_STACK_SIZE      0x400\n#endif\n\nStackSize = MBED_BOOT_STACK_SIZE;\n\nMEMORY\n{\n    \n  VECTORS (rx)          : ORIGIN = MBED_APP_START, LENGTH = 0x00000400\n  FLASH (rx)            : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x00000400\n  RAM_INTERN (rwx)      : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000\n  RAM_EXTERN (rwx)      : ORIGIN = 0x60000000, LENGTH = 0x00100000\n}\n\n\/**\n * Must match cmsis_nvic.h\n *\/\n__vector_size = 4 * (16 + 142);\n \n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(8);\n    } > VECTORS\n\n\n    .text :\n    {\n\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    .ARM.exidx :\n    {\n       __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n       __exidx_end = .;\n    } > FLASH\n\n    \/* .stack section doesn't contains any symbols. It is only\n     * used for linker to reserve space for the main stack section\n     * WARNING: .stack should come immediately after the last secure memory\n     * section.  This provides stack overflow detection. *\/\n    .stack (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack*);\n        . += StackSize - (. - __StackLimit);\n    } > RAM_INTERN\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ADDR(.stack) + SIZEOF(.stack);\n    __StackLimit = ADDR(.stack);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Relocate vector table in SRAM *\/\n    .isr_vector.reloc (NOLOAD) :\n    {\n        . = ALIGN(1 << LOG2CEIL(__vector_size));\n        PROVIDE(__start_vector_table__ = .);\n        . += __vector_size;\n        PROVIDE(__end_vector_table__ = .);\n    } > RAM_INTERN\n    \n    .data :\n    {\n        PROVIDE( __etext = LOADADDR(.data) );\n\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        \/* All data end *\/\n        . = ALIGN(32);\n        __data_end__ = .;\n\n    } >RAM_INTERN AT>FLASH\n\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM_INTERN\n\n    .bss.extern (NOLOAD):\n    {\n        __bss_extern_start__ = .;\n        \/**\n         * Place large .bss* sections into external SRAM if internal SRAM is insufficient.\n         * Such memory arrangement requires initializing .bss.extern section to zero in startup file. Check startup fiile in cmsis-core-* for support or not.\n         *\/\n        *lwip_*.o(.bss*)\n        *lwip_*.o(COMMON)\n        *mesh_system.o(.bss*)\n       __bss_extern_end__ = .;\n    } > RAM_EXTERN\n    \n    .bss (NOLOAD):\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM_INTERN\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*);\n        . += (ORIGIN(RAM_EXTERN) + LENGTH(RAM_EXTERN) - .);\n        __HeapLimit = .;\n    } > RAM_EXTERN\n    PROVIDE(__heap_size = SIZEOF(.heap));\n    PROVIDE(__mbed_sbrk_start = ADDR(.heap));\n    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));\n    \n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f017376361c0842d9db38bc4fb85660d1aeb9f32","subject":"linker: use lowercase _sram_origin","message":"linker: use lowercase _sram_origin","repos":"tock\/libtock-rs","old_file":"layout_generic.ld","new_file":"layout_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * Currently, due to incomplete ROPI-RWPI support in rustc (see\n * https:\/\/github.com\/tock\/libtock-rs\/issues\/28), this layout implements static\n * linking. An application init script must define the FLASH and SRAM address\n * ranges as well as MPU_MIN_ALIGN before including this layout file.\n *\n * Here is a an example application linker script to get started:\n *     MEMORY {\n *         \/* FLASH memory region must start immediately *after* the Tock\n *          * Binary Format headers, which means you need to offset the\n *          * beginning of FLASH memory region relative to where the\n *          * application is loaded.\n *         FLASH (rx) : ORIGIN = 0x10030, LENGTH = 0x0FFD0\n *         SRAM (RWX) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     STACK_SIZE = 2048;\n *     MPU_MIN_ALIGN = 8K;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n        \/* Pad the header out to a multiple of 32 bytes so there is not a gap\n         * between the header and subsequent .data section. It's unclear why,\n         * but LLD is aligning sections to a multiple of 32 bytes. *\/\n        . = ALIGN(32);\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _etext = .;\n    } > FLASH =0xFF\n\n    \/* Application stack *\/\n    .stack (NOLOAD) :\n    {\n        \/* elf2tab requires that the `_sram_origin` symbol be present to\n         * mark the first address in the SRAM memory. Since ELF files do\n         * not really need to specify this address as they only care about\n         * loading into flash, we need to manually mark this address for\n         * elf2tab. elf2tab will use it to add a fixed address header in the\n         * TBF header if needed.\n         *\/\n        _sram_origin = .;\n\n        . = . + STACK_SIZE;\n\n\t_stack_top_unaligned = .;\n        . = ALIGN(8);\n\t_stack_top_aligned = .;\n    } > SRAM\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data : AT (_etext)\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss* .sbss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT((_stack_top_aligned - _stack_top_unaligned) == 0, \"\nSTACK_SIZE must be 8 byte multiple\")\n","old_contents":"\/* Userland Generic Layout\n *\n * Currently, due to incomplete ROPI-RWPI support in rustc (see\n * https:\/\/github.com\/tock\/libtock-rs\/issues\/28), this layout implements static\n * linking. An application init script must define the FLASH and SRAM address\n * ranges as well as MPU_MIN_ALIGN before including this layout file.\n *\n * Here is a an example application linker script to get started:\n *     MEMORY {\n *         \/* FLASH memory region must start immediately *after* the Tock\n *          * Binary Format headers, which means you need to offset the\n *          * beginning of FLASH memory region relative to where the\n *          * application is loaded.\n *         FLASH (rx) : ORIGIN = 0x10030, LENGTH = 0x0FFD0\n *         SRAM (RWX) : ORIGIN = 0x20000, LENGTH = 0x10000\n *     }\n *     STACK_SIZE = 2048;\n *     MPU_MIN_ALIGN = 8K;\n *     INCLUDE ..\/libtock-rs\/layout.ld\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n        \/* Pad the header out to a multiple of 32 bytes so there is not a gap\n         * between the header and subsequent .data section. It's unclear why,\n         * but LLD is aligning sections to a multiple of 32 bytes. *\/\n        . = ALIGN(32);\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _etext = .;\n    } > FLASH =0xFF\n\n    \/* Application stack *\/\n    .stack (NOLOAD) :\n    {\n        \/* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to\n         * mark the first address in the SRAM memory. Since ELF files do\n         * not really need to specify this address as they only care about\n         * loading into flash, we need to manually mark this address for\n         * elf2tab. elf2tab will use it to add a fixed address header in the\n         * TBF header if needed.\n         *\/\n        _SRAM_ORIGIN = .;\n\n        . = . + STACK_SIZE;\n\n\t_stack_top_unaligned = .;\n        . = ALIGN(8);\n\t_stack_top_aligned = .;\n    } > SRAM\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data : AT (_etext)\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss* .sbss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT((_stack_top_aligned - _stack_top_unaligned) == 0, \"\nSTACK_SIZE must be 8 byte multiple\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"fa87598c9e292b801326fb751cd18edbb9969ab9","subject":"nRF52 linker script update","message":"nRF52 linker script update\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa.ld","new_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa.ld","new_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x1f000, LENGTH = 0x61000\r\n\tRAM (rwx) :  ORIGIN = 0x20002800, LENGTH = 0x5800\r\n}\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","old_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x1f000, LENGTH = 0x61000\r\n\tRAM (rwx) :  ORIGIN = 0x20002800, LENGTH = 0x5800\r\n}\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"f796fc78d776d489a7759722107c98e37962d060","subject":"moved kernel to 32M offset, which makes it possible to use lower megabytes for some tables","message":"moved kernel to 32M offset, which makes it possible to use lower megabytes for some tables\n","repos":"velikiyv4\/VV4OS,velikiyv4\/VV4OS,vodozhaba\/VV4OS,vodozhaba\/VV4OS","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(_start)\nSECTIONS\n{\n    . = 32M;\n    .text BLOCK(4K) : ALIGN(4K)\n    {\n        *(.multiboot)\n        *(.text)\n    }\n    .rdata BLOCK(4K) : ALIGN(4K)\n    {\n        *(.rdata)\n    }\n    .data BLOCK(4K) : ALIGN(4K)\n    {\n        *(.data)\n    }\n    .bss BLOCK(4K) : ALIGN(4K)\n    {\n        *(COMMON)\n        *(.bss)\n        *(.bootstrap_stack)\n    }\n}\n","old_contents":"ENTRY(_start)\nSECTIONS\n{\n    . = 1M;\n    .text BLOCK(4K) : ALIGN(4K)\n    {\n        *(.multiboot)\n        *(.text)\n    }\n    .rdata BLOCK(4K) : ALIGN(4K)\n    {\n        *(.rdata)\n    }\n    .data BLOCK(4K) : ALIGN(4K)\n    {\n        *(.data)\n    }\n    .bss BLOCK(4K) : ALIGN(4K)\n    {\n        *(COMMON)\n        *(.bss)\n        *(.bootstrap_stack)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f1813e5bccdc34f24cef19f94c4ff550389f1e64","subject":"Remove keep keyword for .heap section","message":"Remove keep keyword for .heap section\n","repos":"mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed","old_file":"targets\/TARGET_Cypress\/TARGET_PSOC6\/TARGET_CY8CPROTO_064_SB\/device\/TOOLCHAIN_GCC_ARM\/cyb06xx7_cm4_dual.ld","new_file":"targets\/TARGET_Cypress\/TARGET_PSOC6\/TARGET_CY8CPROTO_064_SB\/device\/TOOLCHAIN_GCC_ARM\/cyb06xx7_cm4_dual.ld","new_contents":"\/***************************************************************************\/\/**\n* \\file cyb06xx7_cm4_dual.ld\n* \\version 2.50\n*\n* Linker file for the GNU C compiler.\n*\n* The main purpose of the linker script is to describe how the sections in the\n* input files should be mapped into the output file, and to control the memory\n* layout of the output file.\n*\n* \\note The entry point location is fixed and starts at 0x10000000. The valid\n* application image should be placed there.\n*\n* \\note The linker files included with the PDL template projects must be generic\n* and handle all common use cases. Your project may not use every section\n* defined in the linker files. In that case you may see warnings during the\n* build process. In your project, you can simply comment out or remove the\n* relevant code in the linker file.\n*\n********************************************************************************\n* \\copyright\n* Copyright 2016-2019 Cypress Semiconductor Corporation\n* SPDX-License-Identifier: Apache-2.0\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************\/\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nENTRY(Reset_Handler)\n\n#if !defined(MBED_ROM_START)\n  #define MBED_ROM_START    0x10000400\n#endif\n\n\/* MBED_APP_START is being  used by the bootloader build script and\n* will be calculate by the system. Without bootloader the MBED_APP_START\n* is equal to MBED_ROM_START\n*\/\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START MBED_ROM_START\n#endif\n\n#if !defined(MBED_ROM_SIZE)\n  #define MBED_ROM_SIZE     0x000CFC00\n#endif\n\n\/* MBED_APP_SIZE is being  used by the bootloader build script and\n* will be calculate by the system. Without bootloader the MBED_APP_SIZE\n* is equal to MBED_ROM_SIZE\n*\/\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_RAM_START)\n  #define MBED_RAM_START    0x08000000\n#endif\n\n#if !defined(MBED_RAM_SIZE)\n  #define MBED_RAM_SIZE     0x00020000\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\n\/* Force symbol to be entered in the output file as an undefined symbol. Doing\n* this may, for example, trigger linking of additional modules from standard\n* libraries. You may list several symbols for each EXTERN, and you may use\n* EXTERN multiple times. This command has the same effect as the -u command-line\n* option.\n*\/\nEXTERN(Reset_Handler)\n\n\/* The MEMORY section below describes the location and size of blocks of memory in the target.\n* Use this section to specify the memory regions available for allocation.\n*\/\nMEMORY\n{\n    \/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.\n     * You can change the memory allocation by editing the 'ram' and 'flash' regions.\n     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.\n     * Using this memory region for other purposes will lead to unexpected behavior.\n     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',\n     * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.\n     *\/\n    ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE\n    flash             (rx)    : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n\n    \/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.\n     * You can assign sections to this memory region for only one of the cores.\n     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.\n     * Therefore, repurposing this memory region will prevent such middleware from operation.\n     *\/\n    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       \/*  32 KB *\/\n\n    \/* The following regions define device specific memory regions and must not be changed. *\/\n    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        \/* Supervisory flash: User data *\/\n    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        \/* Supervisory flash: Normal Access Restrictions (NAR) *\/\n    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        \/* Supervisory flash: Public Key *\/\n    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        \/* Supervisory flash: Table of Content # 2 *\/\n    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        \/* Supervisory flash: Table of Content # 2 Copy *\/\n    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    \/* 128 MB *\/\n    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     \/*   1 MB *\/\n}\n\n\/* Size and start address of the Cortex-M4 application image *\/\nFLASH_CM4_SIZE   = LENGTH(flash);\nFLASH_CM4_START  = ORIGIN(flash);\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __Vectors_End\n *   __Vectors_Size\n *\/\n\n\nSECTIONS\n{\n    \/* Cortex-M4 application image *\/\n    \/* Places the code in the Execute in Place (XIP) section. See the smif driver\n     *  documentation for details.\n     *\/\n    .cy_xip :\n    {\n        . = ALIGN(4);\n        __cy_xip_start__ = .;\n        KEEP(*(.cy_xip))\n        #if XIP_ENABLE == 1\n        *lwipstack*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)\n        *mbed-cloud-client*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)\n        #endif\n        __cy_xip_end__ = .;\n    } > xip\n\n    .text FLASH_CM4_START :\n    {\n        . = ALIGN(4);\n        __Vectors = . ;\n        KEEP(*(.vectors))\n        . = ALIGN(4);\n        __Vectors_End = .;\n        __Vectors_Size = __Vectors_End - __Vectors;\n        __end__ = .;\n\n        . = ALIGN(4);\n        #if XIP_ENABLE == 1\n        *(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .text .text*)\n        #else\n        *(.text*)\n        #endif\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        \/* Read-only code (constants). *\/\n        #if XIP_ENABLE == 1\n        *(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)\n        #else\n        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)\n        #endif\n\n        KEEP(*(.eh_frame*))\n    } > flash\n\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > flash\n\n    __exidx_start = .;\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > flash\n    __exidx_end = .;\n\n\n    \/* To copy multiple ROM to RAM sections,\n     * uncomment .copy.table section and,\n     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S *\/\n    .copy.table :\n    {\n        . = ALIGN(4);\n        __copy_table_start__ = .;\n\n        \/* Copy interrupt vectors from flash to RAM *\/\n        LONG (__Vectors)                                    \/* From *\/\n        LONG (__ram_vectors_start__)                        \/* To   *\/\n        LONG (__Vectors_End - __Vectors)                    \/* Size *\/\n\n        \/* Copy data section to RAM *\/\n        LONG (__etext)                                      \/* From *\/\n        LONG (__data_start__)                               \/* To   *\/\n        LONG (__data_end__ - __data_start__)                \/* Size *\/\n\n        __copy_table_end__ = .;\n    } > flash\n\n\n    \/* To clear multiple BSS sections,\n     * uncomment .zero.table section and,\n     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S *\/\n    .zero.table :\n    {\n        . = ALIGN(4);\n        __zero_table_start__ = .;\n        LONG (__bss_start__)\n        LONG (__bss_end__ - __bss_start__)\n        __zero_table_end__ = .;\n    } > flash\n\n    __etext =  . ;\n\n\n    .ramVectors (NOLOAD) : ALIGN(8)\n    {\n        __ram_vectors_start__ = .;\n        KEEP(*(.ram_vectors))\n        __ram_vectors_end__   = .;\n    } > ram\n\n\n    .data __ram_vectors_end__ : AT (__etext)\n    {\n        __data_start__ = .;\n\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n\n        KEEP(*(.cy_ramfunc*))\n        . = ALIGN(4);\n\n        __data_end__ = .;\n\n    } > ram\n\n\n    \/* Place variables in the section that should not be initialized during the\n    *  device startup.\n    *\/\n    .noinit (NOLOAD) : ALIGN(8)\n    {\n      KEEP(*(.noinit))\n    } > ram\n\n\n    \/* The uninitialized global or static variables are placed in this section.\n    *\n    * The NOLOAD attribute tells linker that .bss section does not consume\n    * any space in the image. The NOLOAD attribute changes the .bss type to\n    * NOBITS, and that  makes linker to A) not allocate section in memory, and\n    * A) put information to clear the section with all zeros during application\n    * loading.\n    *\n    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.\n    * This  makes linker to A) allocate zeroed section in memory, and B) copy\n    * this section to RAM during application loading.\n    *\/\n    .bss (NOLOAD):\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > ram\n\n\n    .heap (NOLOAD):\n    {\n        __HeapBase = .;\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;\n        __HeapLimit = .;\n    } > ram\n\n    \n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(ram) + LENGTH(ram);\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Used for the digital signature of the secure application and the Bootloader SDK application.\n    * The size of the section depends on the required data size. *\/\n    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :\n    {\n        KEEP(*(.cy_app_signature))\n    } > flash\n\n\n    \/* Emulated EEPROM Flash area *\/\n    .cy_em_eeprom :\n    {\n        KEEP(*(.cy_em_eeprom))\n    } > em_eeprom\n\n\n    \/* Supervisory Flash: User data *\/\n    .cy_sflash_user_data :\n    {\n        KEEP(*(.cy_sflash_user_data))\n    } > sflash_user_data\n\n\n    \/* Supervisory Flash: Normal Access Restrictions (NAR) *\/\n    .cy_sflash_nar :\n    {\n        KEEP(*(.cy_sflash_nar))\n    } > sflash_nar\n\n\n    \/* Supervisory Flash: Public Key *\/\n    .cy_sflash_public_key :\n    {\n        KEEP(*(.cy_sflash_public_key))\n    } > sflash_public_key\n\n\n    \/* Supervisory Flash: Table of Content # 2 *\/\n    .cy_toc_part2 :\n    {\n        KEEP(*(.cy_toc_part2))\n    } > sflash_toc_2\n\n    \n    \/* Supervisory Flash: Table of Content # 2 Copy *\/\n    .cy_rtoc_part2 :\n    {\n        KEEP(*(.cy_rtoc_part2))\n    } > sflash_rtoc_2\n\n\n    \/* eFuse *\/\n    .cy_efuse :\n    {\n        KEEP(*(.cy_efuse))\n    } > efuse\n\n\n    \/* These sections are used for additional metadata (silicon revision,\n    *  Silicon\/JTAG ID, etc.) storage.\n    *\/\n    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE\n}\n\n\n\/* The following symbols used by the cymcuelftool. *\/\n\/* Flash *\/\n__cy_memory_0_start    = 0x10000000;\n__cy_memory_0_length   = 0x00100000;\n__cy_memory_0_row_size = 0x200;\n\n\/* Emulated EEPROM Flash area *\/\n__cy_memory_1_start    = 0x14000000;\n__cy_memory_1_length   = 0x8000;\n__cy_memory_1_row_size = 0x200;\n\n\/* Supervisory Flash *\/\n__cy_memory_2_start    = 0x16000000;\n__cy_memory_2_length   = 0x8000;\n__cy_memory_2_row_size = 0x200;\n\n\/* XIP *\/\n__cy_memory_3_start    = 0x18000000;\n__cy_memory_3_length   = 0x08000000;\n__cy_memory_3_row_size = 0x200;\n\n\/* eFuse *\/\n__cy_memory_4_start    = 0x90700000;\n__cy_memory_4_length   = 0x100000;\n__cy_memory_4_row_size = 1;\n\n\/* EOF *\/\n","old_contents":"\/***************************************************************************\/\/**\n* \\file cyb06xx7_cm4_dual.ld\n* \\version 2.50\n*\n* Linker file for the GNU C compiler.\n*\n* The main purpose of the linker script is to describe how the sections in the\n* input files should be mapped into the output file, and to control the memory\n* layout of the output file.\n*\n* \\note The entry point location is fixed and starts at 0x10000000. The valid\n* application image should be placed there.\n*\n* \\note The linker files included with the PDL template projects must be generic\n* and handle all common use cases. Your project may not use every section\n* defined in the linker files. In that case you may see warnings during the\n* build process. In your project, you can simply comment out or remove the\n* relevant code in the linker file.\n*\n********************************************************************************\n* \\copyright\n* Copyright 2016-2019 Cypress Semiconductor Corporation\n* SPDX-License-Identifier: Apache-2.0\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************\/\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nENTRY(Reset_Handler)\n\n#if !defined(MBED_ROM_START)\n  #define MBED_ROM_START    0x10000400\n#endif\n\n\/* MBED_APP_START is being  used by the bootloader build script and\n* will be calculate by the system. Without bootloader the MBED_APP_START\n* is equal to MBED_ROM_START\n*\/\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START MBED_ROM_START\n#endif\n\n#if !defined(MBED_ROM_SIZE)\n  #define MBED_ROM_SIZE     0x000CFC00\n#endif\n\n\/* MBED_APP_SIZE is being  used by the bootloader build script and\n* will be calculate by the system. Without bootloader the MBED_APP_SIZE\n* is equal to MBED_ROM_SIZE\n*\/\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_RAM_START)\n  #define MBED_RAM_START    0x08000000\n#endif\n\n#if !defined(MBED_RAM_SIZE)\n  #define MBED_RAM_SIZE     0x00020000\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\n\/* Force symbol to be entered in the output file as an undefined symbol. Doing\n* this may, for example, trigger linking of additional modules from standard\n* libraries. You may list several symbols for each EXTERN, and you may use\n* EXTERN multiple times. This command has the same effect as the -u command-line\n* option.\n*\/\nEXTERN(Reset_Handler)\n\n\/* The MEMORY section below describes the location and size of blocks of memory in the target.\n* Use this section to specify the memory regions available for allocation.\n*\/\nMEMORY\n{\n    \/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.\n     * You can change the memory allocation by editing the 'ram' and 'flash' regions.\n     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.\n     * Using this memory region for other purposes will lead to unexpected behavior.\n     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',\n     * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.\n     *\/\n    ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE\n    flash             (rx)    : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n\n    \/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.\n     * You can assign sections to this memory region for only one of the cores.\n     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.\n     * Therefore, repurposing this memory region will prevent such middleware from operation.\n     *\/\n    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       \/*  32 KB *\/\n\n    \/* The following regions define device specific memory regions and must not be changed. *\/\n    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        \/* Supervisory flash: User data *\/\n    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        \/* Supervisory flash: Normal Access Restrictions (NAR) *\/\n    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        \/* Supervisory flash: Public Key *\/\n    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        \/* Supervisory flash: Table of Content # 2 *\/\n    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        \/* Supervisory flash: Table of Content # 2 Copy *\/\n    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    \/* 128 MB *\/\n    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     \/*   1 MB *\/\n}\n\n\/* Size and start address of the Cortex-M4 application image *\/\nFLASH_CM4_SIZE   = LENGTH(flash);\nFLASH_CM4_START  = ORIGIN(flash);\n\n\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __Vectors_End\n *   __Vectors_Size\n *\/\n\n\nSECTIONS\n{\n    \/* Cortex-M4 application image *\/\n    \/* Places the code in the Execute in Place (XIP) section. See the smif driver\n     *  documentation for details.\n     *\/\n    .cy_xip :\n    {\n        . = ALIGN(4);\n        __cy_xip_start__ = .;\n        KEEP(*(.cy_xip))\n        #if XIP_ENABLE == 1\n        *lwipstack*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)\n        *mbed-cloud-client*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)\n        #endif\n        __cy_xip_end__ = .;\n    } > xip\n\n    .text FLASH_CM4_START :\n    {\n        . = ALIGN(4);\n        __Vectors = . ;\n        KEEP(*(.vectors))\n        . = ALIGN(4);\n        __Vectors_End = .;\n        __Vectors_Size = __Vectors_End - __Vectors;\n        __end__ = .;\n\n        . = ALIGN(4);\n        #if XIP_ENABLE == 1\n        *(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .text .text*)\n        #else\n        *(.text*)\n        #endif\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        \/* Read-only code (constants). *\/\n        #if XIP_ENABLE == 1\n        *(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)\n        #else\n        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)\n        #endif\n\n        KEEP(*(.eh_frame*))\n    } > flash\n\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > flash\n\n    __exidx_start = .;\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > flash\n    __exidx_end = .;\n\n\n    \/* To copy multiple ROM to RAM sections,\n     * uncomment .copy.table section and,\n     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S *\/\n    .copy.table :\n    {\n        . = ALIGN(4);\n        __copy_table_start__ = .;\n\n        \/* Copy interrupt vectors from flash to RAM *\/\n        LONG (__Vectors)                                    \/* From *\/\n        LONG (__ram_vectors_start__)                        \/* To   *\/\n        LONG (__Vectors_End - __Vectors)                    \/* Size *\/\n\n        \/* Copy data section to RAM *\/\n        LONG (__etext)                                      \/* From *\/\n        LONG (__data_start__)                               \/* To   *\/\n        LONG (__data_end__ - __data_start__)                \/* Size *\/\n\n        __copy_table_end__ = .;\n    } > flash\n\n\n    \/* To clear multiple BSS sections,\n     * uncomment .zero.table section and,\n     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S *\/\n    .zero.table :\n    {\n        . = ALIGN(4);\n        __zero_table_start__ = .;\n        LONG (__bss_start__)\n        LONG (__bss_end__ - __bss_start__)\n        __zero_table_end__ = .;\n    } > flash\n\n    __etext =  . ;\n\n\n    .ramVectors (NOLOAD) : ALIGN(8)\n    {\n        __ram_vectors_start__ = .;\n        KEEP(*(.ram_vectors))\n        __ram_vectors_end__   = .;\n    } > ram\n\n\n    .data __ram_vectors_end__ : AT (__etext)\n    {\n        __data_start__ = .;\n\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n\n        KEEP(*(.cy_ramfunc*))\n        . = ALIGN(4);\n\n        __data_end__ = .;\n\n    } > ram\n\n\n    \/* Place variables in the section that should not be initialized during the\n    *  device startup.\n    *\/\n    .noinit (NOLOAD) : ALIGN(8)\n    {\n      KEEP(*(.noinit))\n    } > ram\n\n\n    \/* The uninitialized global or static variables are placed in this section.\n    *\n    * The NOLOAD attribute tells linker that .bss section does not consume\n    * any space in the image. The NOLOAD attribute changes the .bss type to\n    * NOBITS, and that  makes linker to A) not allocate section in memory, and\n    * A) put information to clear the section with all zeros during application\n    * loading.\n    *\n    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.\n    * This  makes linker to A) allocate zeroed section in memory, and B) copy\n    * this section to RAM during application loading.\n    *\/\n    .bss (NOLOAD):\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > ram\n\n\n    .heap (NOLOAD):\n    {\n        __HeapBase = .;\n        __end__ = .;\n        end = __end__;\n        KEEP(*(.heap*))\n        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;\n        __HeapLimit = .;\n    } > ram\n\n    \n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(ram) + LENGTH(ram);\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n\n    \/* Used for the digital signature of the secure application and the Bootloader SDK application.\n    * The size of the section depends on the required data size. *\/\n    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :\n    {\n        KEEP(*(.cy_app_signature))\n    } > flash\n\n\n    \/* Emulated EEPROM Flash area *\/\n    .cy_em_eeprom :\n    {\n        KEEP(*(.cy_em_eeprom))\n    } > em_eeprom\n\n\n    \/* Supervisory Flash: User data *\/\n    .cy_sflash_user_data :\n    {\n        KEEP(*(.cy_sflash_user_data))\n    } > sflash_user_data\n\n\n    \/* Supervisory Flash: Normal Access Restrictions (NAR) *\/\n    .cy_sflash_nar :\n    {\n        KEEP(*(.cy_sflash_nar))\n    } > sflash_nar\n\n\n    \/* Supervisory Flash: Public Key *\/\n    .cy_sflash_public_key :\n    {\n        KEEP(*(.cy_sflash_public_key))\n    } > sflash_public_key\n\n\n    \/* Supervisory Flash: Table of Content # 2 *\/\n    .cy_toc_part2 :\n    {\n        KEEP(*(.cy_toc_part2))\n    } > sflash_toc_2\n\n    \n    \/* Supervisory Flash: Table of Content # 2 Copy *\/\n    .cy_rtoc_part2 :\n    {\n        KEEP(*(.cy_rtoc_part2))\n    } > sflash_rtoc_2\n\n\n    \/* eFuse *\/\n    .cy_efuse :\n    {\n        KEEP(*(.cy_efuse))\n    } > efuse\n\n\n    \/* These sections are used for additional metadata (silicon revision,\n    *  Silicon\/JTAG ID, etc.) storage.\n    *\/\n    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE\n}\n\n\n\/* The following symbols used by the cymcuelftool. *\/\n\/* Flash *\/\n__cy_memory_0_start    = 0x10000000;\n__cy_memory_0_length   = 0x00100000;\n__cy_memory_0_row_size = 0x200;\n\n\/* Emulated EEPROM Flash area *\/\n__cy_memory_1_start    = 0x14000000;\n__cy_memory_1_length   = 0x8000;\n__cy_memory_1_row_size = 0x200;\n\n\/* Supervisory Flash *\/\n__cy_memory_2_start    = 0x16000000;\n__cy_memory_2_length   = 0x8000;\n__cy_memory_2_row_size = 0x200;\n\n\/* XIP *\/\n__cy_memory_3_start    = 0x18000000;\n__cy_memory_3_length   = 0x08000000;\n__cy_memory_3_row_size = 0x200;\n\n\/* eFuse *\/\n__cy_memory_4_start    = 0x90700000;\n__cy_memory_4_length   = 0x100000;\n__cy_memory_4_row_size = 1;\n\n\/* EOF *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b569eefd077efe784449ded0086b994d7419f190","subject":"chore: remove linker script","message":"chore: remove linker script\n\nsince we are using LLVM's native UEFI target we don't need a custom linker\nscript\n","repos":"gil0mendes\/Initium,gil0mendes\/Initium,gil0mendes\/Initium","old_file":"platform\/efi\/linker.ld","new_file":"platform\/efi\/linker.ld","new_contents":"","old_contents":"\/**\n * AMD64 EFI loader linker script.\n *\/\n\nOUTPUT_FORMAT(\"elf64-x86-64\")\nOUTPUT_ARCH(\"i386:x86-64\")\nENTRY(_start)\n\nSECTIONS {\n\t. = SIZEOF_HEADERS;\n\t__start = .;\n\n\t.hash : { *(.hash) }\n\t.gnu.hash : { *(.gnu.hash) }\n\n\t. = ALIGN(0x1000);\n  __text_start = .;\n\t.text : {\n\t\t*(.init.text)\n\t\t*(.text)\n\t\t*(.text.*)\n\t}\n\n\t\/* Dummy relocation section for the PE binary so that EFI recognizes as as a relocatable image. *\/\n\t. = ALIGN(0x1000);\n\t.reloc : { *(.reloc) }\n\n\t. = ALIGN(0x1000);\n  __data_start = .;\n\t.data : {\n\t\t\/* Roll the read-only data into the main data section. It would not be write protected even if we put it \n\t\t * separately, and PE  requires page aligned sections so we only waste space by splitting it into another \n\t\t * section. *\/\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(.got)\n\t\t*(.got.plt)\n    \t*(.init.data)\n\t\t*(.data)\n\t\t*(.data.*)\n\n\n        \/* builtins section *\/\n        __builtins_start = .;\n        *(.builtins)\n        __builtins_end = .;\n\t}\n\n\t. = ALIGN(0x1000);\n\t.dynamic : { *(.dynamic) }\n\n\t. = ALIGN(0x1000);\n  .rela.dyn : {\n    *(.rela.init.text .rela.text .rela.text.*)\n    *(.rela.rodata .rela.rodata.*)\n    *(.rela.got)\n    *(.rela.init.data .rela.data .rela.data.* .rela.builtins)\n    *(.rela.bss .rela.bss.*)\n  }\n\n\t. = ALIGN(0x1000);\n  .dynsym : { *(.dynsym) }\n\n\t. = ALIGN(0x1000);\n  .dynstr : { *(.dynstr) }\n\n\t. = ALIGN(0x1000);\n  __bss_start = .;\n\t.bss : {\n\t\t__bss_start = .;\n\t\t*(.dynbss)\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t\t*(COMMON)\n\t\t__bss_end = .;\n\t}\n\n\t. = ALIGN(0x1000);\n\t__end = .;\n\n\t\/DISCARD\/ : {\n\t\t*(.note.*)\n\t\t*(.comment*)\n\t\t*(.eh_frame*)\n\n\t\t\/* Don't need ELF relocations for the dummy PE relocations. *\/\n\t\t*(.rela.reloc)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"fcbec9700cd7af068698bf9abc7d7c021819cabc","subject":"fix link.lds annotation","message":"fix link.lds annotation\n","repos":"nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,weety\/rt-thread,weety\/rt-thread,weety\/rt-thread,armink\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread","old_file":"bsp\/stm32\/stm32f207-st-nucleo\/board\/linker_scripts\/link.lds","new_file":"bsp\/stm32\/stm32f207-st-nucleo\/board\/linker_scripts\/link.lds","new_contents":"\/*\n * linker script for STM32F10x with GNU ld\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k \/* 1024KB flash *\/\n    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  128k \/* 128K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        _etext = .;\n    } > ROM = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > ROM\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >RAM\n\n    .stack : \n    {\n        . = ALIGN(4);\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >RAM\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > RAM\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * linker script for STM32F10x with GNU ld\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k \/* 128KB flash *\/\n    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  128k \/* 20K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        _etext = .;\n    } > ROM = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > ROM\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >RAM\n\n    .stack : \n    {\n        . = ALIGN(4);\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >RAM\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > RAM\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    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\/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"04c445c17eb3494bb89c1231618e8625729e2548","subject":"mc1322x: Replace tabs by spaces","message":"mc1322x: Replace tabs by spaces\n","repos":"rfswarm\/RIOT,automote\/RIOT,dkm\/RIOT,malosek\/RIOT,aeneby\/RIOT,dailab\/RIOT,mziegert\/RIOT,patkan\/RIOT,LudwigOrtmann\/RIOT,MonsterCode8000\/RIOT,rakendrathapa\/RIOT,rfswarm\/RIOT,luciotorre\/RIOT,sgso\/RIOT,luciotorre\/RIOT,jasonatran\/RIOT,automote\/RIOT,rfswarm\/RIOT,automote\/RIOT,phiros\/RIOT,jbeyerstedt\/RIOT-OTA-update,kaspar030\/RIOT,abkam07\/RIOT,jferreir\/RIOT,OlegHahm\/RIOT,toonst\/RIOT,fnack\/RIOT,jferreir\/RIOT,jremmert-phytec-iot\/RIOT,daniel-k\/RIOT,DipSwitch\/RIOT,tfar\/RIOT,binarylemon\/RIOT,shady33\/RIOT,latsku\/RIOT,Ell-i\/RIOT,dhruvvyas90\/RIOT,kb2ma\/RIOT,yogo1212\/RIOT,gautric\/RIOT,openkosmosorg\/RIOT,phiros\/RIOT,attdona\/RIOT,stevenj\/RIOT,adrianghc\/RIOT,BytesGalore\/RIOT,mfrey\/RIOT,arvindpdmn\/RIOT,shady33\/RIOT,Hyungsin\/RIOT-OS,latsku\/RIOT,biboc\/RIOT,gautric\/RIOT,x3ro\/RIOT,kushalsingh007\/RIOT,OlegHahm\/RIOT,openkosmosorg\/RIOT,chris-wood\/RIOT,sumanpanchal\/RIOT,ks156\/RIOT,latsku\/RIOT,MarkXYang\/RIOT,MarkXYang\/RIOT,OlegHahm\/RIOT,biboc\/RIOT,roberthartung\/RIOT,EmuxEvans\/RIOT,plushvoxel\/RIOT,MohmadAyman\/RIOT,brettswann\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,arvindpdmn\/RIOT,dailab\/RIOT,zhuoshuguo\/RIOT,LudwigOrtmann\/RIOT,shady33\/RIOT,BytesGalore\/RIOT,mziegert\/RIOT,alex1818\/RIOT,sgso\/RIOT,aeneby\/RIOT,openkosmosorg\/RIOT,mziegert\/RIOT,smlng\/RIOT,dhruvvyas90\/RIOT,wentaoshang\/RIOT,khhhh\/RIOT,rousselk\/RIOT,brettswann\/RIOT,immesys\/RiSyn,miri64\/RIOT,ThanhVic\/RIOT,phiros\/RIOT,altairpearl\/RIOT,fnack\/RIOT,gebart\/RIOT,mfrey\/RIOT,MohmadAyman\/RIOT,LudwigKnuepfer\/RIOT,authmillenon\/RIOT,wentaoshang\/RIOT,mtausig\/RIOT,latsku\/RIOT,PSHIVANI\/Riot-Code,Yonezawa-T2\/RIOT,patkan\/RIOT,gbarnett\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,x3ro\/RIOT,kaspar030\/RIOT,TobiasFredersdorf\/RIOT,watr-li\/RIOT,immesys\/RiSyn,haoyangyu\/RIOT,FrancescoErmini\/RIOT,MonsterCode8000\/RIOT,changbiao\/RIOT,EmuxEvans\/RIOT,immesys\/RiSyn,EmuxEvans\/RIOT,gbarnett\/RIOT,robixnai\/RIOT,RubikonAlpha\/RIOT,rakendrathapa\/RIOT,Hyungsin\/RIOT-OS,RubikonAlpha\/RIOT,wentaoshang\/RIOT,LudwigOrtmann\/RIOT,MohmadAyman\/RIOT,tdautc19841202\/RIOT,plushvoxel\/RIOT,DipSwitch\/RIOT,latsku\/RIOT,benoit-canet\/RIOT,brettswann\/RIOT,MarkXYang\/RIOT,abkam07\/RIOT,l3nko\/RIOT,FrancescoErmini\/RIOT,lebrush\/RIOT,binarylemon\/RIOT,basilfx\/RIOT,alignan\/RIOT,Darredevil\/RIOT,zhuoshuguo\/RIOT,EmuxEvans\/RIOT,biboc\/RIOT,RIOT-OS\/RIOT,abkam07\/RIOT,haoyangyu\/RIOT,kb2ma\/RIOT,kerneltask\/RIOT,Darredevil\/RIOT,changbiao\/RIOT,miri64\/RIOT,tfar\/RIOT,gebart\/RIOT,haoyangyu\/RIOT,roberthartung\/RIOT,mziegert\/RIOT,rfuentess\/RIOT,centurysys\/RIOT,basilfx\/RIOT,jremmert-phytec-iot\/RIOT,authmillenon\/RIOT,arvindpdmn\/RIOT,plushvoxel\/RIOT,marcosalm\/RIOT,haoyangyu\/RIOT,LudwigOrtmann\/RIOT,d00616\/RIOT,MohmadAyman\/RIOT,stevenj\/RIOT,Lexandro92\/RIOT-CoAP,daniel-k\/RIOT,sgso\/RIOT,lebrush\/RIOT,asanka-code\/RIOT,kbumsik\/RIOT,dhruvvyas90\/RIOT,katezilla\/RIOT,ximus\/RIOT,jremmert-phytec-iot\/RIOT,yogo1212\/RIOT,ant9000\/RIOT,neiljay\/RIOT,kushalsingh007\/RIOT,Darredevil\/RIOT,patkan\/RIOT,zhuoshuguo\/RIOT,ntrtrung\/RIOT,cladmi\/RIOT,Osblouf\/RIOT,benoit-canet\/RIOT,LudwigKnuepfer\/RIOT,katezilla\/RIOT,rfswarm\/RIOT,A-Paul\/RIOT,chris-wood\/RIOT,beurdouche\/RIOT,ThanhVic\/RIOT,luciotorre\/RIOT,arvindpdmn\/RIOT,arvindpdmn\/RIOT,thiagohd\/RIOT,jbeyerstedt\/RIOT-OTA-update,rakendrathapa\/RIOT,gbarnett\/RIOT,ximus\/RIOT,OTAkeys\/RIOT,kushalsingh007\/RIOT,basilfx\/RIOT,altairpearl\/RIOT,zhuoshuguo\/RIOT,attdona\/RIOT,jferreir\/RIOT,dhruvvyas90\/RIOT,asanka-code\/RIOT,plushvoxel\/RIOT,ks156\/RIOT,Josar\/RIOT,kaleb-himes\/RIOT,neumodisch\/RIOT,herrfz\/RIOT,luciotorre\/RIOT,avmelnikoff\/RIOT,alex1818\/RIOT,MonsterCode8000\/RIOT,lebrush\/RIOT,Darredevil\/RIOT,binarylemon\/RIOT,DipSwitch\/RIOT,luciotorre\/RIOT,watr-li\/RIOT,PSHIVANI\/Riot-Code,bartfaizoltan\/RIOT,adjih\/RIOT,robixnai\/RIOT,d00616\/RIOT,EmuxEvans\/RIOT,immesys\/RiSyn,d00616\/RIOT,immesys\/RiSyn,phiros\/RIOT,alignan\/RIOT,Yonezawa-T2\/RIOT,jferreir\/RIOT,gbarnett\/RIOT,khhhh\/RIOT,gebart\/RIOT,thiagohd\/RIOT,cladmi\/RIOT,abkam07\/RIOT,jfischer-phytec-iot\/RIOT,DipSwitch\/RIOT,hamilton-mote\/RIOT-OS,biboc\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,EmuxEvans\/RIOT,kaspar030\/RIOT,ximus\/RIOT,kbumsik\/RIOT,tfar\/RIOT,authmillenon\/RIOT,Lexandro92\/RIOT-CoAP,marcosalm\/RIOT,adrianghc\/RIOT,Darredevil\/RIOT,centurysys\/RIOT,wentaoshang\/RIOT,RubikonAlpha\/RIOT,PSHIVANI\/Riot-Code,adrianghc\/RIOT,dailab\/RIOT,Ell-i\/RIOT,BytesGalore\/RIOT,dhruvvyas90\/RIOT,kaspar030\/RIOT,thomaseichinger\/RIOT,miri64\/RIOT,jbeyerstedt\/RIOT-OTA-update,cladmi\/RIOT,kb2ma\/RIOT,jremmert-phytec-iot\/RIOT,kb2ma\/RIOT,thomaseichinger\/RIOT,marcosalm\/RIOT,yogo1212\/RIOT,josephnoir\/RIOT,khhhh\/RIOT,openkosmosorg\/RIOT,smlng\/RIOT,khhhh\/RIOT,thiagohd\/RIOT,backenklee\/RIOT,kbumsik\/RIOT,Osblouf\/RIOT,mziegert\/RIOT,x3ro\/RIOT,hamilton-mote\/RIOT-OS,x3ro\/RIOT,malosek\/RIOT,rakendrathapa\/RIOT,msolters\/RIOT,FrancescoErmini\/RIOT,kYc0o\/RIOT,MarkXYang\/RIOT,robixnai\/RIOT,beurdouche\/RIOT,jfischer-phytec-iot\/RIOT,d00616\/RIOT,Hyungsin\/RIOT-OS,koenning\/RIOT,lazytech-org\/RIOT,abp719\/RIOT,ThanhVic\/RIOT,RIOT-OS\/RIOT,herrfz\/RIOT,mtausig\/RIOT,fnack\/RIOT,msolters\/RIOT,chris-wood\/RIOT,abp719\/RIOT,centurysys\/RIOT,adrianghc\/RIOT,hamilton-mote\/RIOT-OS,rajma996\/RIOT,ntrtrung\/RIOT,toonst\/RIOT,centurysys\/RIOT,chris-wood\/RIOT,hamilton-mote\/RIOT-OS,l3nko\/RIOT,tdautc19841202\/RIOT,ntrtrung\/RIOT,x3ro\/RIOT,patkan\/RIOT,fnack\/RIOT,stevenj\/RIOT,josephnoir\/RIOT,wentaoshang\/RIOT,dkm\/RIOT,RBartz\/RIOT,RubikonAlpha\/RIOT,RBartz\/RIOT,adjih\/RIOT,abp719\/RIOT,ThanhVic\/RIOT,kYc0o\/RIOT,automote\/RIOT,msolters\/RIOT,basilfx\/RIOT,jremmert-phytec-iot\/RIOT,LudwigKnuepfer\/RIOT,neumodisch\/RIOT,mziegert\/RIOT,khhhh\/RIOT,l3nko\/RIOT,automote\/RIOT,RBartz\/RIOT,altairpearl\/RIOT,chris-wood\/RIOT,JensErdmann\/RIOT,JensErdmann\/RIOT,TobiasFredersdorf\/RIOT,rajma996\/RIOT,bartfaizoltan\/RIOT,alex1818\/RIOT,rousselk\/RIOT,ant9000\/RIOT,herrfz\/RIOT,lebrush\/RIOT,beurdouche\/RIOT,backenklee\/RIOT,lazytech-org\/RIOT,rfuentess\/RIOT,koenning\/RIOT,Lexandro92\/RIOT-CoAP,kerneltask\/RIOT,koenning\/RIOT,katezilla\/RIOT,koenning\/RIOT,katezilla\/RIOT,bartfaizoltan\/RIOT,DipSwitch\/RIOT,asanka-code\/RIOT,stevenj\/RIOT,rousselk\/RIOT,abkam07\/RIOT,kaleb-himes\/RIOT,A-Paul\/RIOT,benoit-canet\/RIOT,adjih\/RIOT,kb2ma\/RIOT,gebart\/RIOT,avmelnikoff\/RIOT,ntrtrung\/RIOT,ant9000\/RIOT,aeneby\/RIOT,miri64\/RIOT,rfuentess\/RIOT,kaleb-himes\/RIOT,gbarnett\/RIOT,gautric\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,openkosmosorg\/RIOT,PSHIVANI\/Riot-Code,kYc0o\/RIOT,herrfz\/RIOT,sgso\/RIOT,yogo1212\/RIOT,rousselk\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,adjih\/RIOT,kushalsingh007\/RIOT,FrancescoErmini\/RIOT,koenning\/RIOT,luciotorre\/RIOT,alex1818\/RIOT,gautric\/RIOT,LudwigOrtmann\/RIOT,roberthartung\/RIOT,roberthartung\/RIOT,watr-li\/RIOT,RBartz\/RIOT,Osblouf\/RIOT,marcosalm\/RIOT,Lexandro92\/RIOT-CoAP,ant9000\/RIOT,fnack\/RIOT,asanka-code\/RIOT,Hyungsin\/RIOT-OS,altairpearl\/RIOT,adjih\/RIOT,sumanpanchal\/RIOT,avmelnikoff\/RIOT,malosek\/RIOT,changbiao\/RIOT,toonst\/RIOT,Josar\/RIOT,ThanhVic\/RIOT,binarylemon\/RIOT,watr-li\/RIOT,sgso\/RIOT,rfswarm\/RIOT,BytesGalore\/RIOT,shady33\/RIOT,sumanpanchal\/RIOT,mfrey\/RIOT,stevenj\/RIOT,Yonezawa-T2\/RIOT,jbeyerstedt\/RIOT-OTA-update,altairpearl\/RIOT,DipSwitch\/RIOT,daniel-k\/RIOT,kerneltask\/RIOT,Osblouf\/RIOT,aeneby\/RIOT,l3nko\/RIOT,TobiasFredersdorf\/RIOT,kaleb-himes\/RIOT,kerneltask\/RIOT,lazytech-org\/RIOT,MonsterCode8000\/RIOT,JensErdmann\/RIOT,stevenj\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,Ell-i\/RIOT,rajma996\/RIOT,neumodisch\/RIOT,neumodisch\/RIOT,Lexandro92\/RIOT-CoAP,gbarnett\/RIOT,gebart\/RIOT,malosek\/RIOT,FrancescoErmini\/RIOT,patkan\/RIOT,Osblouf\/RIOT,backenklee\/RIOT,tfar\/RIOT,rajma996\/RIOT,RIOT-OS\/RIOT,neumodisch\/RIOT,kushalsingh007\/RIOT,lazytech-org\/RIOT,benoit-canet\/RIOT,Josar\/RIOT,miri64\/RIOT,syin2\/RIOT,attdona\/RIOT,JensErdmann\/RIOT,jfischer-phytec-iot\/RIOT,alignan\/RIOT,tdautc19841202\/RIOT,dailab\/RIOT,OTAkeys\/RIOT,ThanhVic\/RIOT,lebrush\/RIOT,authmillenon\/RIOT,benoit-canet\/RIOT,mtausig\/RIOT,binarylemon\/RIOT,syin2\/RIOT,d00616\/RIOT,thiagohd\/RIOT,brettswann\/RIOT,cladmi\/RIOT,smlng\/RIOT,kaspar030\/RIOT,patkan\/RIOT,Hyungsin\/RIOT-OS,jremmert-phytec-iot\/RIOT,tdautc19841202\/RIOT,Yonezawa-T2\/RIOT,MonsterCode8000\/RIOT,msolters\/RIOT,Darredevil\/RIOT,mtausig\/RIOT,tdautc19841202\/RIOT,robixnai\/RIOT,neiljay\/RIOT,MarkXYang\/RIOT,OTAkeys\/RIOT,arvindpdmn\/RIOT,kYc0o\/RIOT,zhuoshuguo\/RIOT,A-Paul\/RIOT,mfrey\/RIOT,smlng\/RIOT,biboc\/RIOT,authmillenon\/RIOT,lebrush\/RIOT,haoyangyu\/RIOT,RubikonAlpha\/RIOT,thiagohd\/RIOT,RIOT-OS\/RIOT,brettswann\/RIOT,gautric\/RIOT,MohmadAyman\/RIOT,katezilla\/RIOT,LudwigKnuepfer\/RIOT,alex1818\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,phiros\/RIOT,binarylemon\/RIOT,hamilton-mote\/RIOT-OS,attdona\/RIOT,benoit-canet\/RIOT,jbeyerstedt\/RIOT-OTA-update,alignan\/RIOT,FrancescoErmini\/RIOT,yogo1212\/RIOT,abp719\/RIOT,mtausig\/RIOT,thomaseichinger\/RIOT,attdona\/RIOT,mfrey\/RIOT,dkm\/RIOT,adrianghc\/RIOT,shady33\/RIOT,asanka-code\/RIOT,brettswann\/RIOT,immesys\/RiSyn,koenning\/RIOT,robixnai\/RIOT,ks156\/RIOT,tfar\/RIOT,roberthartung\/RIOT,zhuoshuguo\/RIOT,ks156\/RIOT,tdautc19841202\/RIOT,rfuentess\/RIOT,phiros\/RIOT,aeneby\/RIOT,yogo1212\/RIOT,PSHIVANI\/Riot-Code,sgso\/RIOT,ntrtrung\/RIOT,Yonezawa-T2\/RIOT,changbiao\/RIOT,backenklee\/RIOT,syin2\/RIOT,LudwigOrtmann\/RIOT,kerneltask\/RIOT,dkm\/RIOT,changbiao\/RIOT,rajma996\/RIOT,rakendrathapa\/RIOT,beurdouche\/RIOT,ntrtrung\/RIOT,haoyangyu\/RIOT,wentaoshang\/RIOT,malosek\/RIOT,jferreir\/RIOT,fnack\/RIOT,JensErdmann\/RIOT,daniel-k\/RIOT,thomaseichinger\/RIOT,plushvoxel\/RIOT,msolters\/RIOT,A-Paul\/RIOT,dkm\/RIOT,marcosalm\/RIOT,watr-li\/RIOT,centurysys\/RIOT,OTAkeys\/RIOT,bartfaizoltan\/RIOT,ximus\/RIOT,kYc0o\/RIOT,A-Paul\/RIOT,rfswarm\/RIOT,thiagohd\/RIOT,shady33\/RIOT,BytesGalore\/RIOT,RubikonAlpha\/RIOT,Ell-i\/RIOT,l3nko\/RIOT,malosek\/RIOT,dailab\/RIOT,jasonatran\/RIOT,syin2\/RIOT,Osblouf\/RIOT,bartfaizoltan\/RIOT,daniel-k\/RIOT,abp719\/RIOT,sumanpanchal\/RIOT,khhhh\/RIOT,kbumsik\/RIOT,rakendrathapa\/RIOT,avmelnikoff\/RIOT,sumanpanchal\/RIOT,abp719\/RIOT,centurysys\/RIOT,ximus\/RIOT,ks156\/RIOT,chris-wood\/RIOT,neiljay\/RIOT,JensErdmann\/RIOT,alex1818\/RIOT,rousselk\/RIOT,avmelnikoff\/RIOT,Josar\/RIOT,lazytech-org\/RIOT,rousselk\/RIOT,TobiasFredersdorf\/RIOT,MarkXYang\/RIOT,d00616\/RIOT,jasonatran\/RIOT,RBartz\/RIOT,LudwigKnuepfer\/RIOT,marcosalm\/RIOT,RIOT-OS\/RIOT,altairpearl\/RIOT,Lexandro92\/RIOT-CoAP,abkam07\/RIOT,msolters\/RIOT,Yonezawa-T2\/RIOT,OTAkeys\/RIOT,syin2\/RIOT,jferreir\/RIOT,sumanpanchal\/RIOT,kushalsingh007\/RIOT,neumodisch\/RIOT,Josar\/RIOT,PSHIVANI\/Riot-Code,kaleb-himes\/RIOT,watr-li\/RIOT,daniel-k\/RIOT,MonsterCode8000\/RIOT,automote\/RIOT,kbumsik\/RIOT,MohmadAyman\/RIOT,openkosmosorg\/RIOT,josephnoir\/RIOT,thomaseichinger\/RIOT,neiljay\/RIOT,beurdouche\/RIOT,robixnai\/RIOT,bartfaizoltan\/RIOT,neiljay\/RIOT,RBartz\/RIOT,toonst\/RIOT,attdona\/RIOT,backenklee\/RIOT,changbiao\/RIOT,latsku\/RIOT,rajma996\/RIOT,basilfx\/RIOT,josephnoir\/RIOT,Ell-i\/RIOT,jfischer-phytec-iot\/RIOT,l3nko\/RIOT,ximus\/RIOT,josephnoir\/RIOT,TobiasFredersdorf\/RIOT,jasonatran\/RIOT,dhruvvyas90\/RIOT,smlng\/RIOT,jfischer-phytec-iot\/RIOT,herrfz\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,alignan\/RIOT,cladmi\/RIOT,asanka-code\/RIOT,herrfz\/RIOT,toonst\/RIOT","old_file":"cpu\/mc1322x\/mc1322x.lds","new_file":"cpu\/mc1322x\/mc1322x.lds","new_contents":"\/* vim: set syntax=rpcgen : *\/\n\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_startup)\n\nMEMORY\n  {\n    ram (rwx) : org = 0x00400000, l = 96K\n  }\n\nSECTIONS\n{\n\nSYS_STACK_SIZE = 1024;\nIRQ_STACK_SIZE = 256;\nFIQ_STACK_SIZE = 256;\nSVC_STACK_SIZE = 256;\nABT_STACK_SIZE = 16;\nUND_STACK_SIZE = 16;\nHEAP_SIZE = 4096;\n\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x00400000); . = 0x00400000;\n  .text           :\n  {\n    *(.startup)\n    *(.irq)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  } =0\n\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* 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Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.\n      FIXME: Why do we need it? When there is no .bss section, we don't\n      pad the .data section.  *\/\n   . = ALIGN(. != 0 ? 32 \/ 8 : 1);\n  }\n  \/* changed from _bss_end__ = . ; __bss_end__ = . ; *\/\n  __bss_end = . ; __bss_end__ = . ;\n  . = ALIGN(32 \/ 8);\n\n   .heap : {\n                __heap_start__ = . ; PROVIDE(__heap_start = .);\n                *(.heap);\n                . += HEAP_SIZE;\n                . = ALIGN (4);\n                __heap_end__ = . ;  PROVIDE(__heap_end = .);\n   }\n\n\n  . = ALIGN(32 \/ 8);\n  __end__ = . ;\n  _end = .; PROVIDE (end = .);\n  . = DATA_SEGMENT_END (.);\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"0c2d94a1cbba8c8ef6e00fafbca46670ffbcc157","subject":"a\/sys\/program.ld: add symbol at address 0.","message":"a\/sys\/program.ld: add symbol at address 0.\n\nDisassembly output expresses unknown addresses relative to the nearest\nsymbol.  This keeps addresses early in the file from being relative to\nwhatever the first function happens to be.\n","repos":"cbiffle\/brittle-kernel,cbiffle\/brittle-kernel,cbiffle\/brittle-kernel,cbiffle\/brittle-kernel","old_file":"a\/sys\/program.ld","new_file":"a\/sys\/program.ld","new_contents":"MEMORY {\n  flatmem : ORIGIN = 0, LENGTH = 4096M\n}\n\nENTRY(_start)\n\nPHDRS {\n  text PT_LOAD;\n  data PT_LOAD;\n}\n\nSECTIONS {\n  .text 0 : {\n    _image_base = .;\n    LONG(_data_end)\n    LONG(_text_end)\n    LONG(_got_end)\n    LONG(_bss_end)\n    LONG(_stack_size)\n    LONG(_start)\n    *(.text*)\n    . = ALIGN(4);\n    *(.rodata*)\n  } >flatmem :text\n\n  .init : ALIGN(2) {\n    KEEP(*(.init_prologue))\n    KEEP(*(.init))\n    KEEP(*(.init_epilogue))\n  } >flatmem\n\n  .preinit_array : ALIGN(4) {\n    _preinit_array_start = .;\n    KEEP(*(.preinit_array))\n    _preinit_array_end = .;\n  } >flatmem\n\n  .init_array : ALIGN(4) {\n    _init_array_start = .;\n    KEEP(*(.init_array))\n    _init_array_end = .;\n    . = ALIGN(4);\n    PROVIDE(_text_end = .);\n  } >flatmem\n\n\n  .data : {\n    _got_start = .;\n    *(.got.plt)\n    *(.got)\n    _got_end = .;\n    . = ALIGN(4);\n    *(.data*)\n    . = ALIGN(4);\n    PROVIDE(_data_end = .);\n  } >flatmem :data\n\n  .bss (NOLOAD) : ALIGN(4) {\n    PROVIDE(_bss_start = .);\n    *(.bss*)\n    . = ALIGN(4);\n    PROVIDE(_bss_end = .);\n  } >flatmem\n}\n","old_contents":"MEMORY {\n  flatmem : ORIGIN = 0, LENGTH = 4096M\n}\n\nENTRY(_start)\n\nPHDRS {\n  text PT_LOAD;\n  data PT_LOAD;\n}\n\nSECTIONS {\n  .text 0 : {\n    LONG(_data_end)\n    LONG(_text_end)\n    LONG(_got_end)\n    LONG(_bss_end)\n    LONG(_stack_size)\n    LONG(_start)\n    *(.text*)\n    . = ALIGN(4);\n    *(.rodata*)\n  } >flatmem :text\n\n  .init : ALIGN(2) {\n    KEEP(*(.init_prologue))\n    KEEP(*(.init))\n    KEEP(*(.init_epilogue))\n  } >flatmem\n\n  .preinit_array : ALIGN(4) {\n    _preinit_array_start = .;\n    KEEP(*(.preinit_array))\n    _preinit_array_end = .;\n  } >flatmem\n\n  .init_array : ALIGN(4) {\n    _init_array_start = .;\n    KEEP(*(.init_array))\n    _init_array_end = .;\n    . = ALIGN(4);\n    PROVIDE(_text_end = .);\n  } >flatmem\n\n\n  .data : {\n    _got_start = .;\n    *(.got.plt)\n    *(.got)\n    _got_end = .;\n    . = ALIGN(4);\n    *(.data*)\n    . = ALIGN(4);\n    PROVIDE(_data_end = .);\n  } >flatmem :data\n\n  .bss (NOLOAD) : ALIGN(4) {\n    PROVIDE(_bss_start = .);\n    *(.bss*)\n    . = ALIGN(4);\n    PROVIDE(_bss_end = .);\n  } >flatmem\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"971970989bbb1de8887d11b0ab8e4f19adbd484f","subject":"zipl\/boot: fix comment in stage3.lds","message":"zipl\/boot: fix comment in stage3.lds\n\nSee STAGE3_STACK_ADDRESS macro.\n\nReviewed-by: Jan H\u00f6ppner <96138615ab4af0813785fa10d283f3d37eca3b78@linux.ibm.com>\nSigned-off-by: Marc Hartmayer <7bafc8cd4e6394916d396e4f8cde69753be8d066@linux.ibm.com>\nSigned-off-by: Jan H\u00f6ppner <96138615ab4af0813785fa10d283f3d37eca3b78@linux.ibm.com>\n","repos":"ibm-s390-tools\/s390-tools,ibm-s390-tools\/s390-tools,ibm-s390-tools\/s390-tools,ibm-s390-tools\/s390-tools","old_file":"zipl\/boot\/stage3.lds","new_file":"zipl\/boot\/stage3.lds","new_contents":"\/*\n * Memory layout for stage 3\n * =========================\n *\n * General memory layout\n * ---------------------\n *\n * 0x0000-0x1fff\tLowcore\n * 0x2000-0x5fff\tMemory allocation (heap)\n * 0x6000-0x8fff\tfree\n * 0x9000-0x9fff        Stage3 parameter\n * 0xa000-0xdfff        Stage3 code + data\n * 0xf000-0xffff        Stack\n *\/\n\nSECTIONS\n{\n  . = 0x0;\n\n  . = 0x2000;\n  __heap_start = .;\n  . = 0x6000;\n  __heap_stop = .;\n\n\n  \/* stage 3 parameter *\/\n  . = 0x9000;\n  _parm_addr = .;\n  . = 0x9008;\n  _initrd_addr = .;\n  . = 0x9010;\n  _initrd_len = .;\n  . = 0x9018;\n  _load_psw = .;\n  . = 0x9020;\n  _extra_parm = .;\n  . = 0x9028;\n  stage3_flags =.;\n  . = 0x9030;\n  _image_len = .;\n  . = 0x9038;\n  _image_addr = .;\n\n  . = 0xa000;\n  .text.start : { *(.text.start) }\n  .text : { *(.text) }\n  __ex_table_start = .;\n  .ex_table : { *(.ex_table) }\n  __ex_table_stop = .;\n  .eh_frame : { *(.eh_frame) }\n\n  __bss_start = .;\n  .bss : { *(.bss) }\n  __bss_stop = .;\n  .rodata : {*(.rodata) }\n  .data : { *(.data) }\n}\n","old_contents":"\/*\n * Memory layout for stage 3\n * =========================\n *\n * General memory layout\n * ---------------------\n *\n * 0x0000-0x1fff\tLowcore\n * 0x2000-0x5fff\tMemory allocation (heap)\n * 0x6000-0x8fff\tfree\n * 0x9000-0x9fff        Stage3 parameter\n * 0xa000-0xdfff        Stage3 code + data\n * 0xe000-0xffff        Stack\n *\/\n\nSECTIONS\n{\n  . = 0x0;\n\n  . = 0x2000;\n  __heap_start = .;\n  . = 0x6000;\n  __heap_stop = .;\n\n\n  \/* stage 3 parameter *\/\n  . = 0x9000;\n  _parm_addr = .;\n  . = 0x9008;\n  _initrd_addr = .;\n  . = 0x9010;\n  _initrd_len = .;\n  . = 0x9018;\n  _load_psw = .;\n  . = 0x9020;\n  _extra_parm = .;\n  . = 0x9028;\n  stage3_flags =.;\n  . = 0x9030;\n  _image_len = .;\n  . = 0x9038;\n  _image_addr = .;\n\n  . = 0xa000;\n  .text.start : { *(.text.start) }\n  .text : { *(.text) }\n  __ex_table_start = .;\n  .ex_table : { *(.ex_table) }\n  __ex_table_stop = .;\n  .eh_frame : { *(.eh_frame) }\n\n  __bss_start = .;\n  .bss : { *(.bss) }\n  __bss_stop = .;\n  .rodata : {*(.rodata) }\n  .data : { *(.data) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"6544f4cb5c743c9a5b0ed72bac63d7dc997d36ea","subject":"Cleanup minor typos","message":"Cleanup minor typos\n","repos":"adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/nrf\/boards\/feather52840\/bluefruit_nrf52840_s140_6.0.0.ld","new_file":"ports\/nrf\/boards\/feather52840\/bluefruit_nrf52840_s140_6.0.0.ld","new_contents":"\/*\n    GNU linker script for NRF52840 w\/S140 6.0.0 SoftDevice\n\n    MEMORY MAP\n    ------------------------------------------------------------------------\n    START ADDR  END ADDR   SIZE    DESCRIPTION\n    ----------  ---------- ------- -----------------------------------------\n    0x000FF000..0x000FFFFF (  4KB) Bootloader Settings\n    0x000FE000..0x000FEFFF (  4KB) Master Boot Record Params\n    0x000F4000..0x000FDFFF ( 40KB) Serial + OTA Bootloader\n\n    0x000F3000..0x000F3FFF ( 4KB ) Private Config Data (Bonding, Keys, etc.)\n    0x000F2000..0x000F2FFF ( 4KB ) User NVM data\n    0x000B2000..0x000F1FFF (256KB) User Filesystem\n\n    0x00025000..0x000B1FFF (564KB) Application Code (including ISR vector)\n    0x00001000..0x00024FFF (144KB) SoftDevice\n    0x00000000..0x00000FFF   (4KB) Master Boot Record\n*\/\n\n\/* Specify the memory areas (S140 6.0.0) *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000\n\n    FLASH_ISR (rx)  : ORIGIN = 0x00025000, LENGTH = 0x001000\n    FLASH_TEXT (rx) : ORIGIN = 0x00026000, LENGTH = 0x08C000\n    FLASH_FATFS (r) : ORIGIN = 0x000B2000, LENGTH = 0x040000\n\n    \/* 0x2000000 - RAM:ORIGIN is reserved for Softdevice *\/\n    RAM (xrw)       : ORIGIN = 0x20004000, LENGTH = 0x20040000 - 0x20004000\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20007000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52 w\/S140 6.0.0 SoftDevice\n\n    MEMORY MAP\n    ------------------------------------------------------------------------\n    START ADDR  END ADDR   SIZE    DESCRIPTION\n    ----------  ---------- ------- -----------------------------------------\n    0x000FF000..0x000FFFFF (  4KB) Bootloader Settings\n    0x000FE000..0x000FEFFF (  4KB) Master Boot Record Params\n    0x000F4000..0x000FDFFF ( 40KB) Serial + OTA Bootloader\n\n    0x000F3000..0x000F3FFF ( 4KB ) Private Config Data (Bonding, Keys, etc.)\n    0x000F2000..0x000F2FFF ( 4KB ) User NVM data\n    0x000B2000..0x000F1FFF (256KB) User Filesystem\n\n    0x00025000..0x000B1FFF (564KB) Application Code (including ISR vector)\n    0x00001000..0x00024FFF (144KB) SoftDevice\n    0x00000000..0x00000FFF   (4KB) Master Boot Record\n*\/\n\n\/* Specify the memory areas (S140 6.0.0) *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000\n\n    FLASH_ISR (rx)  : ORIGIN = 0x00025000, LENGTH = 0x001000\n    FLASH_TEXT (rx) : ORIGIN = 0x00026000, LENGTH = 0x08C000\n    FLASH_FATFS (r) : ORIGIN = 0x000B2000, LENGTH = 0x040000\n\n    \/* 0x2000000 - RAM:ORGIGIN is reserved for Softdevice *\/\n    RAM (xrw)       : ORIGIN = 0x20004000, LENGTH = 0x20040000 - 0x20004000\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20007000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"76d9c54d1ff17ea8592916557c09a0e1c6b353da","subject":"Tidying up","message":"Tidying up\n","repos":"stelfer\/nubbin,stelfer\/nubbin","old_file":"kernel\/asm\/os-image.elf_x86_64.ld","new_file":"kernel\/asm\/os-image.elf_x86_64.ld","new_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nboot_paddr   \t   = 0x007c00;\t\t\/* boot offset *\/\nkernel_paddr       = 0x100000;\nkernel_vaddr_off   = 0xffffffff00000000;\nkernel_vaddr \t   = kernel_vaddr_off + kernel_paddr;\nkernel_pos   \t   = 0x001000;\t\t\/* physical position in output *\/\nkernel_stack_paddr = 0x005fffff;\nkernel_size \t   = SIZEOF(.kernel);\nuser_vaddr \t   = 0x100000;\n\npaddr_base\t   = 0x00200000;\ngdt_paddr\t   = paddr_base;\nidt_paddr\t   = gdt_paddr + 0x1000;\npage_table_paddr   = idt_paddr + 0x2000;\n\n\nSECTIONS\n{\n\t.boot-setup boot_paddr :\n\t{\n\t\t*(.boot)\n\t\t_setup_paddr = .;\n\t\t*(.setup)\n\t}\n\n\t.kernel kernel_vaddr : AT(boot_paddr + kernel_pos)\n\t{\n\t\t*.ko(.text)\n\t\t*.ko(.data*)\n\t\t*.ko(.rodata*)\n\t\t*.ko(COMMON*)\n\t\t*.ko(.bss*)\n\t}\n\n\t.user user_vaddr + SIZEOF(.kernel): AT(LOADADDR(.kernel) + SIZEOF(.kernel))\n\t{\n\t\t*.o(.text)\n\t\t*.o(.data*)\n\t\t*.o(.rodata*)\n\t\t*.o(COMMON*)\n\t\t*.o(.bss*)\n\t}\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.eh_frame)\n\t\t*(.comment)\n\t}\n}\n","old_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nboot_paddr   \t   = 0x007c00;\t\t\/* boot offset *\/\nkernel_paddr       = 0x100000;\nkernel_vaddr_off   = 0xffffffff00000000;\nkernel_vaddr \t   = kernel_vaddr_off + kernel_paddr;\nkernel_pos   \t   = 0x001000;\t\t\/* physical position in output *\/\npage_table_paddr   = 0x00200000;\nkernel_stack_paddr = 0x005fffff;\nkernel_size \t   = SIZEOF(.kernel);\nuser_vaddr \t   = 0x100000;\n\nSECTIONS\n{\n\t.boot-setup boot_paddr :\n\t{\n\t\t*(.boot)\n\t\t_setup_paddr = .;\n\t\t*(.setup)\n\t}\n\n\t.kernel kernel_vaddr : AT(boot_paddr + kernel_pos)\n\t{\n\t\t*.ko(.text)\n\t\t*.ko(.data*)\n\t\t*.ko(.rodata*)\n\t\t*.ko(COMMON*)\n\t\t*.ko(.bss*)\n\t}\n\n\t.user user_vaddr + SIZEOF(.kernel): AT(LOADADDR(.kernel) + SIZEOF(.kernel))\n\t{\n\t\t*.o(.text)\n\t\t*.o(.data*)\n\t\t*.o(.rodata*)\n\t\t*.o(COMMON*)\n\t\t*.o(.bss*)\n\t}\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.eh_frame)\n\t\t*(.comment)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"d4793f88394c66f32d245d81f9d5093b02e7241a","subject":"Removed 4k align for sections","message":"Removed 4k align for sections\n","repos":"stelfer\/nubbin,stelfer\/nubbin","old_file":"kernel\/asm\/kernel.elf_x86_64.ld","new_file":"kernel\/asm\/kernel.elf_x86_64.ld","new_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.setup :\n\t{\n\t\t*(.setup)\n\t}\n\n\t.text :\n\t{\n\t\t*(.text)\n\t}\n\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.rodata*)\n\t}\n\n\t.bss :\n\t{\n\t\t*(COMMON*)\n\t\t*(.bss*)\n\t}\n}\n","old_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.setup :\n\t{\n\t\t*(.setup)\n\t}\n\n\t.text ALIGN (4K):\n\t{\n\t\t*(.text)\n\t}\n\n\t.data ALIGN (4K) :\n\t{\n\t\t*(.data)\n\t\t*(.rodata*)\n\t}\n\n\t.bss ALIGN (4K) :\n\t{\n\t\t*(COMMON*)\n\t\t*(.bss*)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f8f3eebe2f79574b6f9337cdbc3186c1ed7dadfd","subject":"Update linker script","message":"Update linker script\n\n* Add _ram_start variable used for framebuffer.\n* Check for enough space for MP cache.\n* Increase MP's heap size to 32KB.\n","repos":"tianzhihen\/openmv,openmv\/openmv,SmartArduino\/openmv,SmartArduino\/openmv,openmv\/openmv,kwagyeman\/openmv,openmv\/openmv,iabdalkader\/openmv,iabdalkader\/openmv,iabdalkader\/openmv,SmartArduino\/openmv,kwagyeman\/openmv,tianzhihen\/openmv,openmv\/openmv,kwagyeman\/openmv,tianzhihen\/openmv,SmartArduino\/openmv,kwagyeman\/openmv,iabdalkader\/openmv,tianzhihen\/openmv","old_file":"src\/stm32f4xx.ld","new_file":"src\/stm32f4xx.ld","new_contents":"\/**\n *  Linker script for STM32F4xx Devices with 1MB FLASH, 192KB RAM (64KB CCM)\n *\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K \n  FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 512K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n  CCM (w!rx)      : ORIGIN = 0x10000000, LENGTH = 64K                   \n}\n\n\/* Highest address of the user mode stack *\/\n_estack     = 0x10010000; \/* Stack is allocated on CCM block *\/\n\n_ram_end   = 0x10010000; \/* 64KB CCM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_stack_size = 0x1000; \/* required amount of stack *\/\n_heap_size  = 0x8000; \/* required amount of heap *\/\n_cache_size = 0x4000; \/* required amount of cache *\/\n\n_main_ram_start = 0x20000000;\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH_ISR\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n    _exit = .;\n  } >FLASH_TEXT\n\n  .ARM.extab   : {\n      *(.ARM.extab* .gnu.linkonce.armextab.*) \n  } >FLASH_TEXT\n\n  .ARM : {\n  __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH_TEXT\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH_TEXT\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH_TEXT\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH_TEXT\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    _ram_start = .;\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >CCM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >CCM\n\n  ._heap :\n  {\n    . = ALIGN(4);\n    _heap_start = .;\n    . = . + _heap_size;\n    . = ALIGN(4);\n    _heap_end  = .;\n  } >CCM\n\n  \/* Make sure there is enough RAM left for the stack *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _cache_size;\n    . = . + _stack_size;\n    . = ALIGN(4);\n  } >CCM\n\n  \/* Remove information from the standard libraries *\/\n  \/*\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n  *\/\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/**\n *  Linker script for STM32F4xx Devices with 1MB FLASH, 192KB RAM (64KB CCM)\n *\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K \n  FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 512K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n  CCM (w!rx)      : ORIGIN = 0x10000000, LENGTH = 64K                   \n}\n\n\/* Highest address of the user mode stack *\/\n_estack     = 0x10010000; \/* Stack is allocated on CCM block *\/\n\n_ram_start = 0x10000000;\n_ram_end   = 0x10010000; \/* 64KB CCM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_stack_size = 0x1000; \/* required amount of stack *\/\n_heap_size  = 0x4000; \/* required amount of heap *\/\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH_ISR\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n    _exit = .;\n  } >FLASH_TEXT\n\n  .ARM.extab   : {\n      *(.ARM.extab* .gnu.linkonce.armextab.*) \n  } >FLASH_TEXT\n\n  .ARM : {\n  __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH_TEXT\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH_TEXT\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH_TEXT\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH_TEXT\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >CCM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >CCM\n\n  ._heap :\n  {\n    . = ALIGN(4);\n    _heap_start = .;\n    . = . + _heap_size;\n    . = ALIGN(4);\n    _heap_end  = .;\n  } >CCM\n\n  \/* Make sure there is enough RAM left for the stack *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _stack_size;\n    . = ALIGN(4);\n  } >CCM\n\n  \/* Remove information from the standard libraries *\/\n  \/*\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n  *\/\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"56dd192727a1a3313bc437e953d95e2fba16453d","subject":"binfmt\/libelf: add init_section in separated binary linker script","message":"binfmt\/libelf: add init_section in separated binary linker script\n\nTo use C++, init section is required.\n\nSigned-off-by: sunghan-chang <c954e25285721d8faa8b1a5c1ae2ef5a35338d32@samsung.com>\n","repos":"an4967\/TizenRT,chanijjani\/TizenRT,jeongarmy\/TizenRT,jsdosa\/TizenRT,jeongarmy\/TizenRT,an4967\/TizenRT,davidfather\/TizenRT,junmin-kim\/TizenRT,chanijjani\/TizenRT,junmin-kim\/TizenRT,chanijjani\/TizenRT,sunghan-chang\/TizenRT,jsdosa\/TizenRT,chanijjani\/TizenRT,junmin-kim\/TizenRT,pillip8282\/TizenRT,an4967\/TizenRT,pillip8282\/TizenRT,pillip8282\/TizenRT,an4967\/TizenRT,jeongchanKim\/TizenRT,davidfather\/TizenRT,junmin-kim\/TizenRT,davidfather\/TizenRT,an4967\/TizenRT,Samsung\/TizenRT,junmin-kim\/TizenRT,chanijjani\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT,jeongchanKim\/TizenRT,Samsung\/TizenRT,jsdosa\/TizenRT,jeongarmy\/TizenRT,jsdosa\/TizenRT,an4967\/TizenRT,pillip8282\/TizenRT,jeongarmy\/TizenRT,jsdosa\/TizenRT,Samsung\/TizenRT,junmin-kim\/TizenRT,chanijjani\/TizenRT,jsdosa\/TizenRT,Samsung\/TizenRT,Samsung\/TizenRT,jeongchanKim\/TizenRT,sunghan-chang\/TizenRT,sunghan-chang\/TizenRT,chanijjani\/TizenRT,jeongchanKim\/TizenRT,davidfather\/TizenRT,sunghan-chang\/TizenRT,davidfather\/TizenRT,pillip8282\/TizenRT,sunghan-chang\/TizenRT,jeongchanKim\/TizenRT,sunghan-chang\/TizenRT,junmin-kim\/TizenRT,davidfather\/TizenRT,jsdosa\/TizenRT,jeongarmy\/TizenRT,jeongchanKim\/TizenRT,jeongarmy\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,Samsung\/TizenRT,pillip8282\/TizenRT,jeongchanKim\/TizenRT,an4967\/TizenRT,davidfather\/TizenRT","old_file":"os\/binfmt\/libelf\/gnu-elf.ld","new_file":"os\/binfmt\/libelf\/gnu-elf.ld","new_contents":"\/****************************************************************************\n *\n * Copyright 2019 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * os\/binfmt\/libelf\/gnu-elf.ld\n *\n *   Copyright (C) 2012 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nSECTIONS\n{\n  .text 0x00000000 :\n    {\n      _stext = . ;\n      \/* Place holder to keep the heap object at the top\n       * 4 bytes is reserved at the top of the text segment,\n       * which can be used to place user heap object, which\n       * eventually used by user space memory allocator\n       *\/\n      LONG(0);\n      KEEP(*(.userspace))\n      *(.text)\n      *(.text.*)\n      *(.gnu.warning)\n      *(.stub)\n      *(.glue_7)\n      *(.glue_7t)\n      *(.jcr)\n\n      \/* C++ support:  The .init and .fini sections contain specific logic\n       * to manage static constructors and destructors.\n       *\/\n\n      *(.gnu.linkonce.t.*)\n      *(.init)             \/* Old ABI *\/\n      *(.fini)             \/* Old ABI *\/\n      _etext = . ;\n    }\n\n  .init_section :\n    {\n      _sinit = . ;\n      *(.init_array .init_array.*)\n      _einit = . ;\n    }\n\n  .rodata :\n    {\n      _srodata = . ;\n      *(.rodata)\n      *(.rodata1)\n      *(.rodata.*)\n      *(.gnu.linkonce.r*)\n      _erodata = . ;\n      _eronly = .;\n    }\n\n  .data :\n    {\n      _sdata = . ;\n      *(.data)\n      *(.data1)\n      *(.data.*)\n      *(.gnu.linkonce.d*)\n      _edata = . ;\n    }\n\n  \/* C++ support. For each global and static local C++ object,\n   * GCC creates a small subroutine to construct the object. Pointers\n   * to these routines (not the routines themselves) are stored as\n   * simple, linear arrays in the .ctors section of the object file.\n   * Similarly, pointers to global\/static destructor routines are\n   * stored in .dtors.\n   *\/\n\n  .ctors :\n    {\n      _sctors = . ;\n      *(.ctors)       \/* Old ABI:  Unallocated *\/\n      *(.init_array)  \/* New ABI:  Allocated *\/\n      _ectors = . ;\n    }\n\n  .dtors :\n    {\n      _sdtors = . ;\n      *(.dtors)       \/* Old ABI:  Unallocated *\/\n      *(.fini_array)  \/* New ABI:  Allocated *\/\n      _edtors = . ;\n    }\n\n  .bss :\n    {\n      _sbss = . ;\n      *(.bss)\n      *(.bss.*)\n      *(.sbss)\n      *(.sbss.*)\n      *(.gnu.linkonce.b*)\n      *(COMMON)\n      _ebss = . ;\n    }\n\n    \/* Stabs debugging sections.    *\/\n\n    .stab 0 : { *(.stab) }\n    .stabstr 0 : { *(.stabstr) }\n    .stab.excl 0 : { *(.stab.excl) }\n    .stab.exclstr 0 : { *(.stab.exclstr) }\n    .stab.index 0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment 0 : { *(.comment) }\n    .debug_abbrev 0 : { *(.debug_abbrev) }\n    .debug_info 0 : { *(.debug_info) }\n    .debug_line 0 : { *(.debug_line) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    .debug_aranges 0 : { *(.debug_aranges) }\n}\n","old_contents":"\/****************************************************************************\n *\n * Copyright 2019 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * os\/binfmt\/libelf\/gnu-elf.ld\n *\n *   Copyright (C) 2012 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nSECTIONS\n{\n  .text 0x00000000 :\n    {\n      _stext = . ;\n      \/* Place holder to keep the heap object at the top\n       * 4 bytes is reserved at the top of the text segment,\n       * which can be used to place user heap object, which\n       * eventually used by user space memory allocator\n       *\/\n      LONG(0);\n      KEEP(*(.userspace))\n      *(.text)\n      *(.text.*)\n      *(.gnu.warning)\n      *(.stub)\n      *(.glue_7)\n      *(.glue_7t)\n      *(.jcr)\n\n      \/* C++ support:  The .init and .fini sections contain specific logic\n       * to manage static constructors and destructors.\n       *\/\n\n      *(.gnu.linkonce.t.*)\n      *(.init)             \/* Old ABI *\/\n      *(.fini)             \/* Old ABI *\/\n      _etext = . ;\n    }\n\n  .rodata :\n    {\n      _srodata = . ;\n      *(.rodata)\n      *(.rodata1)\n      *(.rodata.*)\n      *(.gnu.linkonce.r*)\n      _erodata = . ;\n      _eronly = .;\n    }\n\n  .data :\n    {\n      _sdata = . ;\n      *(.data)\n      *(.data1)\n      *(.data.*)\n      *(.gnu.linkonce.d*)\n      _edata = . ;\n    }\n\n  \/* C++ support. For each global and static local C++ object,\n   * GCC creates a small subroutine to construct the object. Pointers\n   * to these routines (not the routines themselves) are stored as\n   * simple, linear arrays in the .ctors section of the object file.\n   * Similarly, pointers to global\/static destructor routines are\n   * stored in .dtors.\n   *\/\n\n  .ctors :\n    {\n      _sctors = . ;\n      *(.ctors)       \/* Old ABI:  Unallocated *\/\n      *(.init_array)  \/* New ABI:  Allocated *\/\n      _ectors = . ;\n    }\n\n  .dtors :\n    {\n      _sdtors = . ;\n      *(.dtors)       \/* Old ABI:  Unallocated *\/\n      *(.fini_array)  \/* New ABI:  Allocated *\/\n      _edtors = . ;\n    }\n\n  .bss :\n    {\n      _sbss = . ;\n      *(.bss)\n      *(.bss.*)\n      *(.sbss)\n      *(.sbss.*)\n      *(.gnu.linkonce.b*)\n      *(COMMON)\n      _ebss = . ;\n    }\n\n    \/* Stabs debugging sections.    *\/\n\n    .stab 0 : { *(.stab) }\n    .stabstr 0 : { *(.stabstr) }\n    .stab.excl 0 : { *(.stab.excl) }\n    .stab.exclstr 0 : { *(.stab.exclstr) }\n    .stab.index 0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment 0 : { *(.comment) }\n    .debug_abbrev 0 : { *(.debug_abbrev) }\n    .debug_info 0 : { *(.debug_info) }\n    .debug_line 0 : { *(.debug_line) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    .debug_aranges 0 : { *(.debug_aranges) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5b64c008a41d8c5b4a3ff44d09a4aa117032bca3","subject":"build\/config\/rtl8721csm\/script: modify ldscript for TCP performance","message":"build\/config\/rtl8721csm\/script: modify ldscript for TCP performance\n\nmodify ldscript for network performance(TCP)\n","repos":"jeongarmy\/TizenRT,junmin-kim\/TizenRT,Samsung\/TizenRT,junmin-kim\/TizenRT,jsdosa\/TizenRT,jsdosa\/TizenRT,jeongarmy\/TizenRT,sunghan-chang\/TizenRT,jsdosa\/TizenRT,jsdosa\/TizenRT,sunghan-chang\/TizenRT,jeongchanKim\/TizenRT,jsdosa\/TizenRT,jeongchanKim\/TizenRT,pillip8282\/TizenRT,sunghan-chang\/TizenRT,an4967\/TizenRT,an4967\/TizenRT,an4967\/TizenRT,an4967\/TizenRT,jeongarmy\/TizenRT,pillip8282\/TizenRT,pillip8282\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,Samsung\/TizenRT,sunghan-chang\/TizenRT,junmin-kim\/TizenRT,jeongchanKim\/TizenRT,jeongchanKim\/TizenRT,Samsung\/TizenRT,an4967\/TizenRT,pillip8282\/TizenRT,jeongarmy\/TizenRT,jsdosa\/TizenRT,jeongchanKim\/TizenRT,junmin-kim\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT,pillip8282\/TizenRT,jeongarmy\/TizenRT,Samsung\/TizenRT,junmin-kim\/TizenRT,an4967\/TizenRT,jeongchanKim\/TizenRT,junmin-kim\/TizenRT,jsdosa\/TizenRT,pillip8282\/TizenRT,junmin-kim\/TizenRT,sunghan-chang\/TizenRT,jeongchanKim\/TizenRT,an4967\/TizenRT,Samsung\/TizenRT,jeongarmy\/TizenRT,Samsung\/TizenRT,sunghan-chang\/TizenRT","old_file":"build\/configs\/rtl8721csm\/scripts\/rlx8721d_img2_ns.ld","new_file":"build\/configs\/rtl8721csm\/scripts\/rlx8721d_img2_ns.ld","new_contents":"\/****************************************************************************\n *\n * Copyright 2020 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n *\n *   Copyright (C) 2020 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nOUTPUT_ARCH(arm)\nENTRY(app_start)\n\nMEMORY\n{\n\tIROM (rx) : \t\t\tORIGIN = 0x10100000, LENGTH = 0x1010A000 - 0x10100000\t\/* ROM: 40k *\/\n\tIROM_NS (rx) : \t\t\tORIGIN = 0x1010A000, LENGTH = 0x10140000 - 0x1010A000\t\/* ROM: 216k *\/\n\tDROM_NS (rx) : \t\t\tORIGIN = 0x101C0000, LENGTH = 0x101D4000 - 0x101C0000\t\/* ROM: 80k *\/\n\tDROM (rx) : \t\t\tORIGIN = 0x101D4000, LENGTH = 0x101D8000 - 0x101D4000\t\/* ROM: 16k *\/\n\tROMBSS_RAM_COM (rw)  : \t\tORIGIN = 0x10000000, LENGTH = 0x10001000 - 0x10000000\t\/* ROM BSS COMMON(S & NS both used) RAM: 4K *\/\n\tROMBSS_RAM_NS (rw)  : \t\tORIGIN = 0x10001000, LENGTH = 0x10002000 - 0x10001000\t\/* ROM BSS NS RAM: 4K *\/\n\tRSVD_RAM_NS (rw)  : \t\tORIGIN = 0x10002000, LENGTH = 0x10004000 - 0x10002000\t\/* RSVD RAM: 8K *\/\n\tMSP_RAM_NS (rw)  : \t\tORIGIN = 0x10004000, LENGTH = 0x10005000 - 0x10004000\t\/* MSP_NS RAM: 4K *\/\n\n\tBD_RAM_NS (rwx)  : \t\tORIGIN = 0x10005000, LENGTH = 0x10077000 - 0x10005000\t\/* MAIN RAM NS: 456K *\/\n\tBD_RAM_S (rwx)  : \t\tORIGIN = 0x10077000, LENGTH = 0x1007B000 - 0x10077000\t\/* MAIN RAM S: 16K *\/\n\tBD_RAM_NSC (rwx)  : \t\tORIGIN = 0x1007B000, LENGTH = 0x1007C000 - 0x1007B000\t\/* MAIN RAM NSC: 4K *\/\n\tROMBSS_RAM_S (rwx)  : \t\tORIGIN = 0x1007C000, LENGTH = 0x1007D000 - 0x1007C000\t\/* ROM BSS RAM S: 4K *\/\n\tBOOTLOADER_RAM_S (rwx)  : \tORIGIN = 0x1007D000, LENGTH = 0x1007F000 - 0x1007D000\t\/* BOOT Loader RAM: 8K *\/\n\tMSP_RAM_S (rwx)  : \t\tORIGIN = 0x1007F000, LENGTH = 0x10080000 - 0x1007F000\t\/* MSP_S RAM: 4k *\/\n\tEXTENTION_SRAM (rwx)  : \t\tORIGIN = 0x100E0000, LENGTH = 0x10100000 - 0x100E0000\t\/* EXTENTION SRAM: 128k *\/\n\n\tPSRAM_NS (rwx)  : \t\tORIGIN = 0x02000000, LENGTH = 0x023C0000 - 0x02000000\t\/* PSRAM_NS: 3M 744K*\/\n\tPSRAM_S (rwx)\t:\t\tORIGIN = 0x023C0000, LENGTH = 0x02400000 - 0x023C0000\t\/* PSRAM_S: 256K *\/\n\n\t\/* Flash *\/\n\tKM0_BOOT (rx)  :\t\tORIGIN = 0x08000000+0x20, LENGTH = 0x02000-0x20\t\/* XIPBOOT: 8k, 32 Bytes resvd for header*\/\n\tBACKUP (r) :\t\t\tORIGIN = 0x08002000, LENGTH = 0x1000\t\/* BACKUP: 4K system data in flash *\/\n\tXIPSYS (r) :\t\t\tORIGIN = 0x08003000, LENGTH = 0x1000\t\/* XIPSYS: 4K system data in flash *\/\n\tKM4_BOOT (rx)  :\t\tORIGIN = 0x08004000+0x20, LENGTH = 0x02000-0x20\t\/* XIPBOOT: 8k, 32 Bytes resvd for header*\/\n\tKM0_IMG2 (rx)  : \t\tORIGIN = 0x0C000000+0x20, LENGTH = 0x02000000-0x20\t\/* KM0_IMG2: 32MB, 32 Bytes resvd for header, virtual address *\/\n\tKM4_IMG2 (rx)  : \t\tORIGIN = 0x0E000000+0x20, LENGTH = 0x02000000-0x20\t\/* KM4_IMG2 OTA1: 32MB, 32 Bytes resvd for header,  virtual address *\/\n\tBTRACE (rx) :\t\t\tORIGIN = 0x00800000, LENGTH = 0x00C00000 -0x00800000\t\/* Bluetooth Trace *\/\n\n\t\/* KM0 RAM*\/\n\tKM0_SRAM (rwx)  : \t\tORIGIN = 0x00080000, LENGTH = 0x00090000 - 0x00080000\t\/* KM0 SRAM: 64k *\/\n\tRETENTION_RAM (rwx)  : \t\tORIGIN = 0x000C0000, LENGTH = 0x000C0400 - 0x000C0000\t\/* KM0 Retention SRAM: 1k *\/\n}\n\nSECTIONS\n{\n\t.rom.text : { } > IROM_NS\n\t.rom.rodata : { } > DROM_NS\n\t.hal.rom.bss : { } > ROMBSS_RAM_COM\n\t.hal.ns_rom.bss : { } > ROMBSS_RAM_NS\n\n\t\/* image2: normal image start *\/\n\t.ram_image2.entry :\n\t{\n\t\t__ram_image2_text_start__ = .;\n\t\t__image2_entry_func__ = .;\n\t\tKEEP(*(SORT(.image2.entry.data*)))\n\n\t\t__image2_validate_code__ = .;\n\t\tKEEP(*(.image2.validate.rodata*))\n\n\t} > BD_RAM_NS\n\n\t.ram_image2.text :\n\t{\n\t\t__ram_text_start__ = .;\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.image2.ram.text*)\n\t\t*(.image2.net.ram.text*)\n\t\t\/*os*\/\n\t\t*os_start.o (.text*)\n\t\t*osdep_service.o (.text*)\n\t\t*tizenrt_service.o (.text*)\n\t\t\/*irq(svcall)*\/\n\t\t\/**irq_initialize.o (.text*)*\/\n\t\t*amebad_irq.o (.text*)\n\t\t*up_exception.o (.text*)\n\t\t*up_svcall.o (.text*)\n\t\t*up_switchcontext.o (.text*)\n\t\t*up_copyfullstate.o (.text*)\n\t\t*up_fullcontextrestore.o (.text*)\n\t\t*up_doirq.o (.text*)\n\t\t*irq_dispatch.o (.text*)\n\t\t\/*scheduler(for semphr)*\/\n\t\t*sched_addreadytorun.o (.text*)\n\t\t*sched_addblocked.o (.text*)\n\t\t*sched_addprioritized.o (.text*)\n\t\t*sched_removereadytorun.o (.text*)\n\t\t*sched_removeblocked.o (.text*)\n\t\t*sched_mergepending.o (.text*)\n\t\t*up_blocktask.o (.text*)\n\t\t*up_unblocktask.o (.text*)\n\t\t\/*semphr*\/\n\t\t*sem_wait.o (.text*)\n\t\t*sem_waitirq.o (.text*)\n\t\t*sem_trywait.o (.text*)\n\t\t*sem_tickwait.o (.text*)\n\t\t*sem_timedwait.o (.text*)\n\t\t*sem_post.o (.text*)\n\t\t\/* driver *\/\n\t\t*ethernetif_tizenrt.o (.text*)\n\t\t*lwip_intf_tizenrt.o (.text*)\n\t\t\/*lwip*\/\n\t\t*randm.o (.text*)\n\t\t*netifapi.o (.text*)\n\t\t*snmp_mib2_interfaces.o (.text*)\n\t\t*snmp_raw.o (.text*)\n\t\t*icmp.o (.text*)\n\t\t*ip4.o (.text*)\n\t\t*dhcp.o (.text*)\n\t\t*udp.o (.text*)\n\t\t*snmp_mib2.o (.text*)\n\t\t*etharp.o (.text*)\n\t\t*netmgr_ioctl_lwip.o (.text*)\n\t\t*dhcps.o (.text*)\n\t\t*snmp_traps.o (.text*)\n\t\t*tcp.o (.text*)\n\t\t*net_initialize_netmgr.o (.text*)\n\t\t*def.o (.text*)\n\t\t*nd6.o (.text*)\n\t\t*raw.o (.text*)\n\t\t*tcp_out.o (.text*)\n\t\t*netstack_lwip.o (.text*)\n\t\t*memp.o (.text*)\n\t\t*netdev_wifi.o (.text*)\n\t\t*lwip_md5.o (.text*)\n\t\t*snmp_mib2_udp.o (.text*)\n\t\t*netmgr_ioctl_netmon.o (.text*)\n\t\t*snmp_msg.o (.text*)\n\t\t*sys_arch.o (.text*)\n\t\t*igmp.o (.text*)\n\t\t*api_lib.o (.text*)\n\t\t*pbuf.o (.text*)\n\t\t*netdev_eth.o (.text*)\n\t\t*netdev_stats.o (.text*)\n\t\t*ip4_addr.o (.text*)\n\t\t*mem.o (.text*)\n\t\t*dns.o (.text*)\n\t\t*snmp_threadsync.o (.text*)\n\t\t*netmgr_ioctl_netdev.o (.text*)\n\t\t*snmp_mib2_system.o (.text*)\n\t\t*netdev_lwnl.o (.text*)\n\t\t*ppp_oe.o (.text*)\n\t\t*stats.o (.text*)\n\t\t*api_msg.o (.text*)\n\t\t*netstack_lwnl.o (.text*)\n\t\t*sys.o (.text*)\n\t\t*inet_chksum.o (.text*)\n\t\t*netdb.o (.text*)\n\t\t*net_vfs.o (.text*)\n\t\t*slipif.o (.text*)\n\t\t*ip6_addr.o (.text*)\n\t\t*inet6.o (.text*)\n\t\t*snmp_mib2_snmp.o (.text*)\n\t\t*pap.o (.text*)\n\t\t*netdev_mgr.o (.text*)\n\t\t*snmp_mib2_ip.o (.text*)\n\t\t*netstack.o (.text*)\n\t\t*fsm.o (.text*)\n\t\t*tcp_in.o (.text*)\n\t\t*err.o (.text*)\n\t\t*snmp_netconn.o (.text*)\n\t\t*chpms.o (.text*)\n\t\t*ethernet.o (.text*)\n\t\t*netif.o (.text*)\n\t\t*snmp_mib2_tcp.o (.text*)\n\t\t*ipcp.o (.text*)\n\t\t*chap.o (.text*)\n\t\t*timeouts.o (.text*)\n\t\t*vj.o (.text*)\n\t\t*magic.o (.text*)\n\t\t*ppp.o (.text*)\n\t\t*autoip.o (.text*)\n\t\t*snmp_mib2_icmp.o (.text*)\n\t\t*ip6.o (.text*)\n\t\t*sockets.o (.text*)\n\t\t*ethip6.o (.text*)\n\t\t*snmp_asn1.o (.text*)\n\t\t*netdev_mgr_internal.o (.text*)\n\t\t*snmp_pbuf_stream.o (.text*)\n\t\t*ip4_frag.o (.text*)\n\t\t*netdev_lwip.o (.text*)\n\t\t*bsd_socket_api.o (.text*)\n\t\t*ip6_frag.o (.text*)\n\t\t*init.o (.text*)\n\t\t*mld6.o (.text*)\n\t\t*lcp.o (.text*)\n\t\t*snmp_table.o (.text*)\n\t\t*snmp_core.o (.text*)\n\t\t*auth.o (.text*)\n\t\t*netbuf.o (.text*)\n\t\t*snmp_scalar.o (.text*)\n\t\t*icmp6.o (.text*)\n\t\t*ip.o (.text*)\n\t\t*tcpip.o (.text*)\n\t\t\/*iperf*\/\n\t\t\/* *iperf_tcp.o (.text*) *\/\n\t\t\/* *iperf_timer.o (.text*) *\/\n\t\t\/* *iperf_t_timer.o (.text*) *\/\n\t\t\/* *iperf_units.o (.text*) *\/\n\t\t\/* *iperf_util.o (.text*) *\/\n\t\t\/* *iperf_locale.o (.text*) *\/\n\t\t\/* *iperf_net.o (.text*) *\/\n\t\t\/* *iperf_tcp_info.o (.text*) *\/\n\t\t\/* *iperf_client_api.o (.text*) *\/\n\t\t\/* *iperf_api.o (.text*) *\/\n\t\t\/* *iperf_server_api.o (.text*) *\/\n\t\t\/* *iperf_error.o (.text*) *\/\n\t\t\/* *iperf_main.o (.text*) *\/\n\t\t\/* *iperf_udp.o (.text*) *\/\n\t\t\/* *iperf_server_api.o (.text*) *\/\n\t\t\/* *iperf_api.o (.text*) *\/\n\t\t\/*fs*\/\n\t\t\/**fs_read.o (.text*)\n\t\t*fs_select.o (.text*)\n\t\t*fs_poll.o (.text*)*\/\n\t\t\/*others*\/\n\t\t*lib_vikmemcpy.o (.text*)\n\t\t*dq_rem.o (.text*)\n\t\t*dq_addlast.o (.text*)\n\t\t_etext = ABSOLUTE(.);\n\t\t__ram_text_end__ = .;\n\t} > BD_RAM_NS\n\n\t_eronly = ABSOLUTE(.);\n\n\t.ram_image2.data :\n\t{\n\t\t_sdata = ABSOLUTE(.);\n\t\t__data_start__ = .;\n\t\t*(.data*)\n\t\t__data_end__ = .;\n\t\t_edata = ABSOLUTE(.);\n\t\t__ram_image2_text_end__ = .;\n\t\t. = ALIGN(16);\n\t} > BD_RAM_NS\n\n\t.ram_image2.bss :\n\t{\n\t\t_sbss = ABSOLUTE(.);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t__bss_end__ = .;\n\n\t} > BD_RAM_NS\n\n\t.ram_image2.nocache.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t__ram_nocache_start__ = .;\n\t\t*(.bdsram.data*)\n\t\t. = ALIGN (32);\n\t\t__ram_nocache_end__ = .;\n\t} > BD_RAM_NS\n\n\t.ram_heap.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.bfsram.data*)\n\t\tend = .;\n\t\t_ebss = ABSOLUTE(.);\n\t} > BD_RAM_NS\n\n\n\t.xip_image2.text :\n\t{\n\t\t__flash_text_start__ = .;\n\n\t\t*(.img2_custom_signature*)\n\n\t\t*(.text*)\n\t\/*\t*(.image2.net.ram.text*) *\/\n\t\t*(.rodata*)\n\n\t\t\/* Add This for C++ support *\/\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP(*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\t__init_array_end = .;\n\t\t. = ALIGN(4);\n\t\t__fini_array_start = .;\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\t__fini_array_end = .;\n\t\t\/*-----------------*\/\n\n\t\t. = ALIGN (4);\n\t\t__cmd_table_start__ = .;\n\t\tKEEP(*(.cmd.table.data*))\n\t\t__cmd_table_end__ = .;\n\n\t\t__flash_text_end__ = .;\n\n\t\t. = ALIGN (16);\n\t} > KM4_IMG2\n\n\t\/* Add This for C++ support *\/\n\t.ARM.extab  :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\n\t} > KM4_IMG2\n\n\t.ARM.exidx :\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > KM4_IMG2\n\t\/*-----------------*\/\n\n\t.bluetooth_trace.text :\n\t{\n\t\t__btrace_start__ = .;\n\t\t*(.BTTRACE)\n\t\t__btrace_end__ = .;\n\t} > BTRACE\n\n\t\/* PSRAM_NS image start *\/\n\t.psram_image2.text :\n\t{\n\t\t__psram_image2_text_start__ = .;\n\t\t*(.psram.text*)\n\t\t__psram_image2_text_end__ = .;\n\t} > PSRAM_NS\n\n\t.psram_image2.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.psram.data*)\n\t\t. = ALIGN (32);\n\t\t*(.psram.rodata*)\n\t} > PSRAM_NS\n\n\t.psram_image2.bss :\n\t{\n\t\t. = ALIGN (32);\n\t\t__psram_bss_start__ = .;\n\t\t*(.psram.bss*)\n\t\t__psram_bss_end__ = .;\n\t} > PSRAM_NS\n\n\t.psram_heap.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.psram.heap*)\n\t} > PSRAM_NS\n\t__StackLimit = ABSOLUTE(ORIGIN(BD_RAM_NS) + LENGTH(BD_RAM_NS));\n\t__PsramStackLimit = ABSOLUTE(ORIGIN(PSRAM_NS) + LENGTH(PSRAM_NS));\n}\nSECTIONS\n{\n    __rom_bss_start__ = 0x10000000;\n    ConfigDebugClose = 0x10000000;\n    ConfigDebugBuffer = 0x10000004;\n    ConfigDebugBufferGet = 0x10000008;\n    ConfigDebug = 0x1000000c;\n    rand_first = 0x1000001c;\n    rand_seed = 0x10000020;\n    RBSS_UDELAY_DIV = 0x10000034;\n    flash_init_para = 0x10000038;\n    GDMA_Reg = 0x10000098;\n    PortA_IrqHandler = 0x1000009c;\n    PortA_IrqData = 0x1000011c;\n    PortB_IrqHandler = 0x1000019c;\n    PortB_IrqData = 0x1000021c;\n    IPC_IrqHandler = 0x1000029c;\n    IPC_IrqData = 0x1000031c;\n    IS_FPGA_VERIF = 0x1000039c;\n    crypto_engine = 0x100003a0;\n    __rom_bss_end__ = 0x10000564;\n    __rom_bss_start_ns__ = 0x10001000;\n    NewVectorTable = 0x10001000;\n    UserIrqFunTable = 0x10001140;\n    UserIrqDataTable = 0x10001240;\n    mpu_entry_register = 0x10001340;\n    p_rom_ssl_ram_map = 0x10001348;\n    rom_ssl_ram_map = 0x1000134c;\n    __rom_bss_end_ns__ = 0x1000138c;\n    __rom_bss_start_s__ = 0x1007c000;\n    __ram_start_table_start__ = 0x1007d000;\n    STACK_TOP = 0x1007effc;\n    __vectors_table = 0x1010a000;\n    Reset_Handler = 0x1010a101;\n    NMI_Handler = 0x1010a111;\n    HardFault_Handler = 0x1010a115;\n    MemManage_Handler = 0x1010a119;\n    BusFault_Handler = 0x1010a11d;\n    UsageFault_Handler = 0x1010a121;\n    SecureFault_Handler = 0x1010a125;\n    DiagVSprintf = 0x1010a12d;\n    DiagPrintf = 0x1010a3f5;\n    DiagPrintfD = 0x1010a445;\n    DiagSPrintf = 0x1010a471;\n    DiagSnPrintf = 0x1010a49d;\n    Rand = 0x1010a765;\n    Rand_Arc4 = 0x1010a7f1;\n    RandBytes_Get = 0x1010a825;\n    io_assert_failed = 0x1010a871;\n    BKUP_Write = 0x1010a891;\n    BKUP_Read = 0x1010a8b5;\n    BKUP_Set = 0x1010a8d5;\n    BKUP_Clear = 0x1010a8fd;\n    BOOT_Reason = 0x1010a929;\n    DelayNop = 0x1010a939;\n    DelayUs = 0x1010a949;\n    DelayMs = 0x1010a995;\n    EFUSEPowerSwitch = 0x1010a9a9;\n    EFUSERead8 = 0x1010aa31;\n    EFUSEWrite8 = 0x1010ab1d;\n    EFUSE_PG_Packet = 0x1010ac21;\n    EFUSE_LogicalMap_Read = 0x1010ae99;\n    EFUSE_LogicalMap_Write = 0x1010afad;\n    FLASH_RxData = 0x1010b195;\n    FLASH_TxCmd = 0x1010b29d;\n    FLASH_SW_CS_Control = 0x1010b329;\n    FLASH_SetSpiMode = 0x1010b37d;\n    FLASH_RxCmd = 0x1010b415;\n    FLASH_WaitBusy = 0x1010b479;\n    FLASH_WriteEn = 0x1010b4f9;\n    FLASH_TxData256B = 0x1010b51d;\n    FLASH_TxData12B = 0x1010b60d;\n    FLASH_SetStatus = 0x1010b6ed;\n    FLASH_Erase = 0x1010b70d;\n    FLASH_DeepPowerDown = 0x1010b7b9;\n    FLASH_SetStatusBits = 0x1010b809;\n    FLASH_StructInit_Micron = 0x1010b8dd;\n    FLASH_StructInit_MXIC = 0x1010b98d;\n    FLASH_StructInit_GD = 0x1010ba39;\n    FLASH_StructInit = 0x1010baed;\n    FLASH_Init = 0x1010bba1;\n    GDMA_StructInit = 0x1010bc25;\n    GDMA_SetLLP = 0x1010bc45;\n    GDMA_ClearINTPendingBit = 0x1010bcd9;\n    GDMA_ClearINT = 0x1010bda5;\n    GDMA_INTConfig = 0x1010be75;\n    GDMA_Cmd = 0x1010bf91;\n    GDMA_Init = 0x1010bff9;\n    GDMA_ChCleanAutoReload = 0x1010c14d;\n    GDMA_SetSrcAddr = 0x1010c1d1;\n    GDMA_GetSrcAddr = 0x1010c221;\n    GDMA_GetDstAddr = 0x1010c26d;\n    GDMA_SetDstAddr = 0x1010c2b9;\n    GDMA_SetBlkSize = 0x1010c309;\n    GDMA_GetBlkSize = 0x1010c369;\n    GDMA_ChnlRegister = 0x1010c3b9;\n    GDMA_ChnlUnRegister = 0x1010c401;\n    GDMA_ChnlAlloc = 0x1010c43d;\n    GDMA_ChnlFree = 0x1010c4d9;\n    GDMA_GetIrqNum = 0x1010c565;\n    GPIO_INTMode = 0x1010c5a9;\n    GPIO_INTConfig = 0x1010c641;\n    GPIO_INTHandler = 0x1010c679;\n    GPIO_Direction = 0x1010c721;\n    GPIO_Init = 0x1010c755;\n    GPIO_DeInit = 0x1010c7e1;\n    GPIO_ReadDataBit = 0x1010c84d;\n    GPIO_WriteBit = 0x1010c871;\n    GPIO_PortDirection = 0x1010c8a1;\n    GPIO_PortRead = 0x1010c8c5;\n    GPIO_PortWrite = 0x1010c8d5;\n    GPIO_UserRegIrq = 0x1010c8ed;\n    IPC_INTConfig = 0x1010c925;\n    IPC_IERSet = 0x1010c939;\n    IPC_IERGet = 0x1010c93d;\n    IPC_INTRequest = 0x1010c941;\n    IPC_INTClear = 0x1010c94d;\n    IPC_INTGet = 0x1010c959;\n    IPC_CPUID = 0x1010c95d;\n    IPC_SEMGet = 0x1010c969;\n    IPC_SEMFree = 0x1010c9b9;\n    IPC_INTHandler = 0x1010ca21;\n    IPC_INTUserHandler = 0x1010ca61;\n    LOGUART_StructInit = 0x1010ca9d;\n    LOGUART_Init = 0x1010cab5;\n    LOGUART_PutChar = 0x1010caf5;\n    LOGUART_GetChar = 0x1010cb29;\n    LOGUART_Readable = 0x1010cb45;\n    LOGUART_GetIMR = 0x1010cb59;\n    LOGUART_SetIMR = 0x1010cb65;\n    LOGUART_WaitBusy = 0x1010cb71;\n    LOGUART_SetBaud = 0x1010cb91;\n    mpu_enable = 0x1010cbd5;\n    mpu_disable = 0x1010cbed;\n    mpu_init = 0x1010cc01;\n    mpu_set_mem_attr = 0x1010cc3d;\n    mpu_region_cfg = 0x1010ccb1;\n    mpu_entry_free = 0x1010cdb5;\n    mpu_entry_alloc = 0x1010cdc1;\n    RSIP_Cmd = 0x1010cde9;\n    RSIP_OTF_init = 0x1010ce05;\n    RSIP_OTF_Cmd = 0x1010ce6d;\n    RSIP_OTF_Mask = 0x1010ce81;\n    RSIP_KEY_Request = 0x1010cec9;\n    RSIP_MMU_Config = 0x1010cf0d;\n    RSIP_MMU_Cmd = 0x1010cf31;\n    PAD_DrvStrength = 0x1010cf51;\n    PAD_PullCtrl = 0x1010cf6d;\n    PAD_CMD = 0x1010cf99;\n    Pinmux_Config = 0x1010cfb9;\n    Pinmux_ConfigGet = 0x1010cfd9;\n    Pinmux_UartLogCtrl = 0x1010cfe9;\n    Pinmux_SpicCtrl = 0x1010d03d;\n    simulation_bit_index = 0x1010d181;\n    simulation_stage_set = 0x1010d199;\n    SYSTIMER_Init = 0x1010d1c5;\n    SYSTIMER_TickGet = 0x1010d215;\n    SYSTIMER_GetPassTime = 0x1010d225;\n    RTIM_TimeBaseStructInit = 0x1010d255;\n    RTIM_Cmd = 0x1010d26d;\n    RTIM_GetCount = 0x1010d2f5;\n    RTIM_INTConfig = 0x1010d361;\n    RTIM_INTClear = 0x1010d3f1;\n    RTIM_TimeBaseInit = 0x1010d45d;\n    RTIM_DeInit = 0x1010d595;\n    RTIM_INTClearPendingBit = 0x1010d611;\n    RTIM_GetFlagStatus = 0x1010d685;\n    RTIM_GetINTStatus = 0x1010d75d;\n    UART_DeInit = 0x1010d83d;\n    UART_StructInit = 0x1010d845;\n    UART_BaudParaGetFull = 0x1010d861;\n    UART_BaudParaGet = 0x1010d899;\n    UART_SetBaud = 0x1010d8bd;\n    UART_SetBaudExt = 0x1010d955;\n    UART_SetRxLevel = 0x1010d9cd;\n    UART_RxCmd = 0x1010d9f5;\n    UART_Writable = 0x1010da09;\n    UART_Readable = 0x1010da11;\n    UART_CharPut = 0x1010da19;\n    UART_CharGet = 0x1010da1d;\n    UART_ReceiveData = 0x1010da25;\n    UART_SendData = 0x1010da4d;\n    UART_ReceiveDataTO = 0x1010da75;\n    UART_SendDataTO = 0x1010dab5;\n    UART_RxByteCntClear = 0x1010daf5;\n    UART_RxByteCntGet = 0x1010db01;\n    UART_BreakCtl = 0x1010db09;\n    UART_ClearRxFifo = 0x1010db1d;\n    UART_Init = 0x1010db3d;\n    UART_ClearTxFifo = 0x1010dbe5;\n    UART_INTConfig = 0x1010dbf1;\n    UART_IntStatus = 0x1010dc01;\n    UART_ModemStatusGet = 0x1010dc05;\n    UART_LineStatusGet = 0x1010dc09;\n    UART_WaitBusy = 0x1010dc0d;\n    rtl_crypto_aes_cbc_init = 0x1010dc31;\n    rtl_crypto_aes_cbc_encrypt = 0x1010dc81;\n    rtl_crypto_aes_cbc_decrypt = 0x1010dccd;\n    rtl_crypto_aes_ecb_init = 0x1010dd19;\n    rtl_crypto_aes_ecb_encrypt = 0x1010dd69;\n    rtl_crypto_aes_ecb_decrypt = 0x1010dda1;\n    rtl_crypto_aes_ctr_init = 0x1010ddd9;\n    rtl_crypto_aes_ctr_encrypt = 0x1010de29;\n    rtl_crypto_aes_ctr_decrypt = 0x1010de6d;\n    rtl_crypto_aes_cfb_init = 0x1010deb1;\n    rtl_crypto_aes_cfb_encrypt = 0x1010df01;\n    rtl_crypto_aes_cfb_decrypt = 0x1010df45;\n    rtl_crypto_aes_ofb_init = 0x1010df89;\n    rtl_crypto_aes_ofb_encrypt = 0x1010dfdd;\n    rtl_crypto_aes_ofb_decrypt = 0x1010e021;\n    rtl_crypto_aes_gcm_init = 0x1010e065;\n    rtl_crypto_aes_gcm_encrypt = 0x1010e0b9;\n    rtl_crypto_aes_gcm_decrypt = 0x1010e131;\n    BOOT_ROM_SignatureCheck = 0x1010e1a9;\n    BOOT_ROM_FromFlash = 0x1010e281;\n    BOOT_ROM_InitDebugFlg = 0x1010e38d;\n    BOOT_ROM_ResetVsr = 0x1010e3a9;\n    EXT32K_Cmd = 0x1010e4c9;\n    XTAL_ClkGet = 0x1010e4e9;\n    CPU_ClkSet = 0x1010e501;\n    CPU_ClkGet = 0x1010e515;\n    CRYPTO_MemDump = 0x1010e539;\n    CRYPTO_RegDump = 0x1010e601;\n    CRYPTO_CleanCmdOk = 0x1010e7c1;\n    CRYPTO_ClearAllINT = 0x1010e7f9;\n    CRYPTO_Reset = 0x1010e829;\n    CRYPTO_SetSecurityModeAD = 0x1010e86d;\n    CRYPTO_Init = 0x1010ea49;\n    CRYPTO_ProcessAD = 0x1010ea6d;\n    CRYPTO_SendSeqBuf = 0x1010f681;\n    CRYPTO_CipherInit = 0x1010f799;\n    CRYPTO_CipherEncryptAD = 0x1010f7b9;\n    CRYPTO_CipherDecryptAD = 0x1010f7e9;\n    rtl_crypto_3des_cbc_init = 0x1010f819;\n    rtl_crypto_3des_cbc_encrypt = 0x1010f869;\n    rtl_crypto_3des_cbc_decrypt = 0x1010f8b5;\n    rtl_crypto_3des_ecb_init = 0x1010f901;\n    rtl_crypto_3des_ecb_encrypt = 0x1010f951;\n    rtl_crypto_3des_ecb_decrypt = 0x1010f989;\n    rtl_crypto_3des_cfb_init = 0x1010f9c1;\n    rtl_crypto_3des_cfb_encrypt = 0x1010fa11;\n    rtl_crypto_3des_cfb_decrypt = 0x1010fa49;\n    rtl_crypto_3des_ofb_init = 0x1010fa81;\n    rtl_crypto_3des_ofb_encrypt = 0x1010fad1;\n    rtl_crypto_3des_ofb_decrypt = 0x1010fb09;\n    rtl_crypto_3des_ctr_init = 0x1010fb41;\n    rtl_crypto_3des_ctr_encrypt = 0x1010fb95;\n    rtl_crypto_3des_ctr_decrypt = 0x1010fbcd;\n    rtl_crypto_des_cbc_init = 0x1010fc05;\n    rtl_crypto_des_cbc_encrypt = 0x1010fc59;\n    rtl_crypto_des_cbc_decrypt = 0x1010fcb5;\n    rtl_crypto_des_ecb_init = 0x1010fd11;\n    rtl_crypto_des_ecb_encrypt = 0x1010fd65;\n    rtl_crypto_des_ecb_decrypt = 0x1010fd9d;\n    rtl_crypto_des_cfb_init = 0x1010fdd5;\n    rtl_crypto_des_cfb_encrypt = 0x1010fe29;\n    rtl_crypto_des_cfb_decrypt = 0x1010fe61;\n    rtl_crypto_des_ofb_init = 0x1010fe99;\n    rtl_crypto_des_ofb_encrypt = 0x1010feed;\n    rtl_crypto_des_ofb_decrypt = 0x1010ff25;\n    rtl_crypto_des_ctr_init = 0x1010ff5d;\n    rtl_crypto_des_ctr_encrypt = 0x1010ffb1;\n    rtl_crypto_des_ctr_decrypt = 0x1010ffe9;\n    clear_ns_rom_bss = 0x10110021;\n    RCC_PeriphClockCmd = 0x10110039;\n    RCC_PeriphClockSource_RTC = 0x101100d1;\n    RCC_PeriphClockSource_I2C = 0x1011011d;\n    RCC_PeriphClockSource_QDEC = 0x1011013d;\n    RCC_PeriphClockSource_UART = 0x1011015d;\n    SYSCFG_GetChipInfo = 0x101101d1;\n    INT_HardFault = 0x101101dd;\n    INT_MemManage = 0x101101fd;\n    INT_BusFault = 0x1011021d;\n    INT_UsageFault = 0x1011023d;\n    INT_SecureFault = 0x1011025d;\n    INT_HardFault_C = 0x1011027d;\n    INT_NMI = 0x1011064d;\n    irq_table_init = 0x10110795;\n    \/\/irq_enable = 0x101109d1;\n    \/\/irq_disable = 0x101109ed;\n    \/\/irq_set_priority = 0x10110a11;\n    \/\/irq_get_priority = 0x10110a3d;\n    \/\/irq_set_pending = 0x10110a65;\n    \/\/irq_get_pending = 0x10110a81;\n    \/\/irq_clear_pending = 0x10110aa5;\n    \/\/irq_register = 0x10110ac1;\n    \/\/irq_unregister = 0x10110b0d;\n    _char2num = 0x10110b2d;\n    _2char2dec = 0x10110b5d;\n    _2char2hex = 0x10110bd1;\n    _memchr = 0x10110c39;\n    _memcmp = 0x10110cc9;\n    _memcpy = 0x10110d2d;\n    _memmove = 0x10110dd9;\n    _memset = 0x10110ea1;\n    _vsscanf = 0x10110ffd;\n    _sscanf = 0x101115c1;\n    _stratoi = 0x101115e1;\n    _strcat = 0x10111635;\n    _strchr = 0x10111675;\n    _strcmp = 0x10111745;\n    _strcpy = 0x101117b9;\n    _stricmp = 0x10111805;\n    _strlen = 0x10111839;\n    _strncat = 0x1011189d;\n    _strncmp = 0x101118f9;\n    _strncpy = 0x1011199d;\n    _strnlen = 0x10111a05;\n    _strpbrk = 0x10111a39;\n    _strsep = 0x10111a65;\n    _strstr = 0x10111d25;\n    _strtoull = 0x10111f3d;\n    _strtoll = 0x10111ffd;\n    _strtok = 0x1011201d;\n    __strtok_r = 0x10112029;\n    _strtok_r = 0x1011208d;\n    _strtol_r = 0x10112095;\n    _strtol = 0x101121b1;\n    _strtoul_r = 0x101121b5;\n    _strtoul = 0x101122e9;\n    _strupr = 0x101122ed;\n    CRYPTO_chacha_20 = 0x10112309;\n    rom_ed25519_gen_keypair = 0x101125c5;\n    rom_ed25519_gen_signature = 0x101125c9;\n    rom_ed25519_verify_signature = 0x101125df;\n    rom_ed25519_ge_double_scalarmult_vartime = 0x10113e89;\n    rom_ed25519_ge_frombytes_negate_vartime = 0x10114195;\n    rom_ed25519_ge_p3_tobytes = 0x10114695;\n    rom_ed25519_ge_scalarmult_base = 0x101146df;\n    rom_ed25519_ge_tobytes = 0x10114807;\n    rom_ed25519_crypto_sign_seed_keypair = 0x10114851;\n    rom_ed25519_crypto_sign_verify_detached = 0x101148a9;\n    rom_ed25519_sc_muladd = 0x10114ad5;\n    rom_ed25519_sc_reduce = 0x1011b265;\n    rom_ed25519_crypto_sign_detached = 0x1011c6dd;\n    CRYPTO_poly1305_init = 0x1011ca99;\n    CRYPTO_poly1305_update = 0x1011cb31;\n    CRYPTO_poly1305_finish = 0x1011cba7;\n    rom_sha512_starts = 0x1011cd4d;\n    rom_sha512_update = 0x1011cd51;\n    rom_sha512_finish = 0x1011cd55;\n    rom_sha512 = 0x1011cd59;\n    rom_sha512_hmac_starts = 0x1011cd5d;\n    rom_sha512_hmac_update = 0x1011cdf1;\n    rom_sha512_hmac_finish = 0x1011cdf5;\n    rom_sha512_hmac_reset = 0x1011ce49;\n    rom_sha512_hmac = 0x1011ce65;\n    rom_sha512_hkdf = 0x1011cea1;\n    curve25519_donna = 0x1011dce5;\n    rtl_aes_init = 0x1011e569;\n    rtl_aes_free = 0x1011e579;\n    rtl_aes_setkey_enc = 0x1011e58d;\n    rtl_aes_setkey_dec = 0x1011e7a5;\n    rtl_aes_encrypt = 0x1011e8c1;\n    rtl_aes_decrypt = 0x1011ecf9;\n    rtl_aes_crypt_ecb = 0x1011f145;\n    rtl_aes_crypt_cbc = 0x1011f1c9;\n    rtl_aes_crypt_cfb128 = 0x1011f3d5;\n    rtl_aes_crypt_cfb8 = 0x1011f44b;\n    rtl_aes_crypt_ctr = 0x1011f4b1;\n    rtl_arc4_init = 0x1011f515;\n    rtl_arc4_free = 0x1011f525;\n    rtl_arc4_setup = 0x1011f539;\n    rtl_arc4_crypt = 0x1011f57f;\n    rtl_asn1_get_len = 0x1011f5c5;\n    rtl_asn1_get_tag = 0x1011f661;\n    rtl_asn1_get_bool = 0x1011f689;\n    rtl_asn1_get_int = 0x1011f6b9;\n    rtl_asn1_get_mpi = 0x1011f6ff;\n    rtl_asn1_get_bitstring = 0x1011f725;\n    rtl_asn1_get_bitstring_null = 0x1011f76d;\n    rtl_asn1_get_sequence_of = 0x1011f795;\n    rtl_asn1_get_alg = 0x1011f81d;\n    rtl_asn1_get_alg_null = 0x1011f8a9;\n    rtl_asn1_free_named_data = 0x1011f8ed;\n    rtl_asn1_free_named_data_list = 0x1011f91d;\n    rtl_asn1_find_named_data = 0x1011f941;\n    rtl_asn1_write_len = 0x1011f96d;\n    rtl_asn1_write_tag = 0x1011fa55;\n    rtl_asn1_write_raw_buffer = 0x1011fa71;\n    rtl_asn1_write_mpi = 0x1011faa1;\n    rtl_asn1_write_null = 0x1011fb13;\n    rtl_asn1_write_oid = 0x1011fb39;\n    rtl_asn1_write_algorithm_identifier = 0x1011fb6d;\n    rtl_asn1_write_bool = 0x1011fbbd;\n    rtl_asn1_write_int = 0x1011fbff;\n    rtl_asn1_write_printable_string = 0x1011fc61;\n    rtl_asn1_write_ia5_string = 0x1011fc95;\n    rtl_asn1_write_bitstring = 0x1011fcc9;\n    rtl_asn1_write_octet_string = 0x1011fd3d;\n    rtl_asn1_store_named_data = 0x1011fd71;\n    rtl_base64_encode = 0x1011fe29;\n    rtl_base64_decode = 0x1011ff2d;\n    rtl_mpi_init = 0x10120b19;\n    rtl_mpi_free = 0x10120b27;\n    rtl_mpi_grow = 0x10120b5d;\n    rtl_mpi_shrink = 0x10120bc1;\n    rtl_mpi_copy = 0x10120c41;\n    rtl_mpi_swap = 0x10120c9d;\n    rtl_mpi_safe_cond_assign = 0x10120cc5;\n    rtl_mpi_safe_cond_swap = 0x10120d31;\n    rtl_mpi_lset = 0x10120db3;\n    rtl_mpi_get_bit = 0x10120df1;\n    rtl_mpi_set_bit = 0x10120e11;\n    rtl_mpi_lsb = 0x10120e61;\n    rtl_mpi_bitlen = 0x10120e93;\n    rtl_mpi_size = 0x10120ed3;\n    rtl_mpi_read_binary = 0x10120edf;\n    rtl_mpi_write_binary = 0x10120f47;\n    rtl_mpi_shift_l = 0x10120f91;\n    rtl_mpi_shift_r = 0x1012102d;\n    rtl_mpi_cmp_abs = 0x101210ab;\n    rtl_mpi_cmp_mpi = 0x101211ed;\n    rtl_mpi_cmp_int = 0x10121277;\n    rtl_mpi_add_abs = 0x101212a3;\n    rtl_mpi_sub_abs = 0x10121357;\n    rtl_mpi_add_mpi = 0x101213d5;\n    rtl_mpi_sub_mpi = 0x10121417;\n    rtl_mpi_add_int = 0x1012145b;\n    rtl_mpi_sub_int = 0x10121487;\n    rtl_mpi_mul_mpi = 0x101214b3;\n    rtl_mpi_mul_int = 0x1012158f;\n    rtl_mpi_read_string = 0x101215a9;\n    rtl_mpi_div_mpi = 0x101216c9;\n    rtl_mpi_div_int = 0x10121aeb;\n    rtl_mpi_mod_mpi = 0x10121b15;\n    rtl_mpi_mod_int = 0x10121b75;\n    rtl_mpi_write_string = 0x10121c15;\n    rtl_mpi_exp_mod = 0x10121d6d;\n    rtl_mpi_gcd = 0x101221a5;\n    rtl_mpi_fill_random = 0x101222af;\n    rtl_mpi_inv_mod = 0x101224f9;\n    rtl_mpi_is_prime = 0x101227b5;\n    rtl_mpi_gen_prime = 0x10122809;\n    rtl_ctr_drbg_init = 0x10122ae9;\n    rtl_ctr_drbg_free = 0x10122af9;\n    rtl_ctr_drbg_set_prediction_resistance = 0x10122b17;\n    rtl_ctr_drbg_set_entropy_len = 0x10122b1b;\n    rtl_ctr_drbg_set_reseed_interval = 0x10122b1f;\n    rtl_ctr_drbg_update = 0x10122b23;\n    rtl_ctr_drbg_reseed = 0x10122b47;\n    rtl_ctr_drbg_seed_entropy_len = 0x10122bc5;\n    rtl_ctr_drbg_seed = 0x10122c19;\n    rtl_ctr_drbg_random_with_add = 0x10122c2b;\n    rtl_ctr_drbg_random = 0x10122cf1;\n    rtl_des_init = 0x10122d11;\n    rtl_des_free = 0x10122d1d;\n    rtl_des3_init = 0x10122d25;\n    rtl_des3_free = 0x10122d35;\n    rtl_des_key_set_parity = 0x10122d3f;\n    rtl_des_key_check_key_parity = 0x10122d59;\n    rtl_des_key_check_weak = 0x10122d7d;\n    rtl_des_setkey = 0x10122da9;\n    rtl_des_setkey_enc = 0x101231bb;\n    rtl_des_setkey_dec = 0x101231e5;\n    rtl_des3_set2key_enc = 0x10123239;\n    rtl_des3_set2key_dec = 0x1012327d;\n    rtl_des3_set3key_enc = 0x101232c1;\n    rtl_des3_set3key_dec = 0x101232fd;\n    rtl_des_crypt_ecb = 0x10123339;\n    rtl_des_crypt_cbc = 0x10123541;\n    rtl_des3_crypt_ecb = 0x10123731;\n    rtl_des3_crypt_cbc = 0x10123b81;\n    rtl_dhm_init = 0x10123e01;\n    rtl_dhm_read_params = 0x10123e0d;\n    rtl_dhm_make_params = 0x10123e59;\n    rtl_dhm_read_public = 0x10123f91;\n    rtl_dhm_make_public = 0x10123fb5;\n    rtl_dhm_calc_secret = 0x1012406d;\n    rtl_dhm_free = 0x1012426d;\n    rtl_dhm_parse_dhm = 0x101242cf;\n    rtl_ecdh_gen_public = 0x101243c1;\n    rtl_ecdh_compute_shared = 0x101243c5;\n    rtl_ecdh_init = 0x10124425;\n    rtl_ecdh_free = 0x10124435;\n    rtl_ecdh_make_params = 0x1012447d;\n    rtl_ecdh_read_params = 0x101244ed;\n    rtl_ecdh_get_params = 0x10124515;\n    rtl_ecdh_make_public = 0x10124561;\n    rtl_ecdh_read_public = 0x101245b1;\n    rtl_ecdh_calc_secret = 0x101245dd;\n    rtl_ecdsa_sign = 0x10124693;\n    rtl_ecdsa_sign_det = 0x10124815;\n    rtl_ecdsa_verify = 0x101248bd;\n    rtl_ecdsa_write_signature = 0x101249f9;\n    rtl_ecdsa_write_signature_det = 0x10124a9d;\n    rtl_ecdsa_read_signature = 0x10124abb;\n    rtl_ecdsa_genkey = 0x10124b55;\n    rtl_ecdsa_from_keypair = 0x10124b83;\n    rtl_ecdsa_init = 0x10124bbb;\n    rtl_ecdsa_free = 0x10124bbf;\n    rtl_ecjpake_init = 0x10124ff5;\n    rtl_ecjpake_free = 0x1012504f;\n    rtl_ecjpake_setup = 0x101250a5;\n    rtl_ecjpake_check = 0x101250e9;\n    rtl_ecjpake_read_round_one = 0x10125109;\n    rtl_ecjpake_write_round_one = 0x10125185;\n    rtl_ecjpake_read_round_two = 0x101252ad;\n    rtl_ecjpake_write_round_two = 0x10125365;\n    rtl_ecjpake_derive_secret = 0x101254a1;\n    rtl_ecp_curve_list = 0x10125de9;\n    rtl_ecp_curve_info_from_grp_id = 0x10125df1;\n    rtl_ecp_curve_info_from_tls_id = 0x10125e0d;\n    rtl_ecp_curve_info_from_name = 0x10125e29;\n    rtl_ecp_point_init = 0x10125e51;\n    rtl_ecp_group_init = 0x10125e71;\n    rtl_ecp_keypair_init = 0x10125e81;\n    rtl_ecp_point_free = 0x10125ea1;\n    rtl_ecp_group_free = 0x10125ec1;\n    rtl_ecp_keypair_free = 0x10125f31;\n    rtl_ecp_copy = 0x10125f51;\n    rtl_ecp_group_copy = 0x10125f7d;\n    rtl_ecp_set_zero = 0x10125f83;\n    rtl_ecp_is_zero = 0x10126839;\n    rtl_ecp_point_cmp = 0x1012684b;\n    rtl_ecp_point_read_string = 0x1012687d;\n    rtl_ecp_point_write_binary = 0x101268a9;\n    rtl_ecp_point_read_binary = 0x1012694d;\n    rtl_ecp_tls_read_point = 0x101269b9;\n    rtl_ecp_tls_write_point = 0x101269e9;\n    rtl_ecp_tls_read_group = 0x10126a19;\n    rtl_ecp_tls_write_group = 0x10126a61;\n    rtl_ecp_check_pubkey = 0x10126a99;\n    rtl_ecp_check_privkey = 0x10126c2d;\n    rtl_ecp_mul = 0x10126c9d;\n    rtl_ecp_muladd = 0x1012726f;\n    rtl_ecp_gen_keypair_base = 0x101272d9;\n    rtl_ecp_gen_keypair = 0x101273d9;\n    rtl_ecp_gen_key = 0x101273f1;\n    rtl_ecp_check_pub_priv = 0x10127419;\n    rtl_ecp_group_load = 0x10128519;\n    rtl_hmac_drbg_init = 0x1012893d;\n    rtl_hmac_drbg_update = 0x10128949;\n    rtl_hmac_drbg_seed_buf = 0x101289e5;\n    rtl_hmac_drbg_reseed = 0x10128a35;\n    rtl_hmac_drbg_seed = 0x10128aad;\n    rtl_hmac_drbg_set_prediction_resistance = 0x10128b1d;\n    rtl_hmac_drbg_set_entropy_len = 0x10128b21;\n    rtl_hmac_drbg_set_reseed_interval = 0x10128b25;\n    rtl_hmac_drbg_random_with_add = 0x10128b29;\n    rtl_hmac_drbg_random = 0x10128bdd;\n    rtl_hmac_drbg_free = 0x10128bed;\n    rtl_md_list = 0x10128c09;\n    rtl_md_info_from_string = 0x10128c11;\n    rtl_md_info_from_type = 0x10128ca9;\n    rtl_md_init = 0x10128ced;\n    rtl_md_free = 0x10128cf9;\n    rtl_md_clone = 0x10128d45;\n    rtl_md_setup = 0x10128d6d;\n    rtl_md_init_ctx = 0x10128db5;\n    rtl_md_starts = 0x10128dbb;\n    rtl_md_update = 0x10128dd5;\n    rtl_md_finish = 0x10128df1;\n    rtl_md = 0x10128e0d;\n    rtl_md_hmac_starts = 0x10128e29;\n    rtl_md_hmac_update = 0x10128eed;\n    rtl_md_hmac_finish = 0x10128f0d;\n    rtl_md_hmac_reset = 0x10128f65;\n    rtl_md_hmac = 0x10128f91;\n    rtl_md_process = 0x10128fe5;\n    rtl_md_get_size = 0x10129001;\n    rtl_md_get_type = 0x10129009;\n    rtl_md_get_name = 0x1012900f;\n    rtl_md5_init = 0x1012917d;\n    rtl_md5_free = 0x10129189;\n    rtl_md5_clone = 0x1012919d;\n    rtl_md5_starts = 0x101291a9;\n    rtl_md5_process = 0x101291d5;\n    rtl_md5_update = 0x101298dd;\n    rtl_md5_finish = 0x101298e3;\n    rtl_md5 = 0x10129995;\n    rtl_oid_get_attr_short_name = 0x101299fd;\n    rtl_oid_get_x509_ext_type = 0x10129a35;\n    rtl_oid_get_extended_key_usage = 0x10129a6d;\n    rtl_oid_get_sig_alg_desc = 0x10129aa5;\n    rtl_oid_get_sig_alg = 0x10129abd;\n    rtl_oid_get_oid_by_sig_alg = 0x10129adb;\n    rtl_oid_get_pk_alg = 0x10129b09;\n    rtl_oid_get_oid_by_pk_alg = 0x10129b41;\n    rtl_oid_get_ec_grp = 0x10129b69;\n    rtl_oid_get_oid_by_ec_grp = 0x10129ba1;\n    rtl_oid_get_cipher_alg = 0x10129bc9;\n    rtl_oid_get_md_alg = 0x10129c01;\n    rtl_oid_get_oid_by_md = 0x10129c39;\n    rtl_oid_get_pkcs12_pbe_alg = 0x10129c61;\n    rtl_pem_init = 0x10129e5f;\n    rtl_pem_read_buffer = 0x10129e6d;\n    rtl_pem_free = 0x1012a161;\n    rtl_pem_write_buffer = 0x1012a185;\n    rtl_pk_init = 0x1012a279;\n    rtl_pk_free = 0x1012a283;\n    rtl_pk_info_from_type = 0x1012a2a5;\n    rtl_pk_setup = 0x1012a2d9;\n    rtl_pk_setup_rsa_alt = 0x1012a305;\n    rtl_pk_can_do = 0x1012a351;\n    rtl_pk_verify = 0x1012a361;\n    rtl_pk_sign = 0x1012a3bd;\n    rtl_pk_decrypt = 0x1012a425;\n    rtl_pk_encrypt = 0x1012a451;\n    rtl_pk_check_pair = 0x1012a47d;\n    rtl_pk_get_bitlen = 0x1012a4bd;\n    rtl_pk_verify_ext = 0x1012a4cd;\n    rtl_pk_debug = 0x1012a585;\n    rtl_pk_get_name = 0x1012a5a9;\n    rtl_pk_get_type = 0x1012a5bd;\n    rtl_pk_write_pubkey = 0x1012aa23;\n    rtl_pk_write_pubkey_der = 0x1012aaad;\n    rtl_pk_write_key_der = 0x1012ab7d;\n    rtl_pk_write_pubkey_pem = 0x1012ad79;\n    rtl_pk_write_key_pem = 0x1012adc1;\n    rtl_rsa_init = 0x1012aecd;\n    rtl_rsa_set_padding = 0x1012aeed;\n    rtl_rsa_check_pubkey = 0x1012aef7;\n    rtl_rsa_check_privkey = 0x1012af4d;\n    rtl_rsa_check_pub_priv = 0x1012b169;\n    rtl_rsa_public = 0x1012b1a1;\n    rtl_rsa_private = 0x1012b20f;\n    rtl_rsa_rsaes_oaep_encrypt = 0x1012b465;\n    rtl_rsa_rsaes_pkcs1_v15_encrypt = 0x1012b58d;\n    rtl_rsa_pkcs1_encrypt = 0x1012b675;\n    rtl_rsa_rsaes_oaep_decrypt = 0x1012b6b5;\n    rtl_rsa_rsaes_pkcs1_v15_decrypt = 0x1012b821;\n    rtl_rsa_pkcs1_decrypt = 0x1012b92d;\n    rtl_rsa_rsassa_pss_sign = 0x1012b975;\n    rtl_rsa_rsassa_pkcs1_v15_sign = 0x1012badd;\n    rtl_rsa_pkcs1_sign = 0x1012bc85;\n    rtl_rsa_rsassa_pss_verify_ext = 0x1012bcc9;\n    rtl_rsa_rsassa_pss_verify = 0x1012be75;\n    rtl_rsa_rsassa_pkcs1_v15_verify = 0x1012bea7;\n    rtl_rsa_pkcs1_verify = 0x1012c009;\n    rtl_rsa_free = 0x1012c04d;\n    rtl_rsa_gen_key = 0x1012c0bb;\n    rtl_rsa_copy = 0x1012c261;\n    rtl_sha1_init = 0x1012c365;\n    rtl_sha1_free = 0x1012c371;\n    rtl_sha1_clone = 0x1012c385;\n    rtl_sha1_starts = 0x1012c391;\n    rtl_sha1_process = 0x1012c3c5;\n    rtl_sha1_update = 0x1012d391;\n    rtl_sha1_finish = 0x1012d397;\n    rtl_sha1 = 0x1012d45d;\n    rtl_sha256_init = 0x1012d491;\n    rtl_sha256_free = 0x1012d49d;\n    rtl_sha256_clone = 0x1012d4b1;\n    rtl_sha256_starts = 0x1012d4bd;\n    rtl_sha256_process = 0x1012d55d;\n    rtl_sha256_update = 0x1012dc89;\n    rtl_sha256_finish = 0x1012dc8f;\n    rtl_sha256 = 0x1012dd91;\n    rtl_sha512_init = 0x1012ddc9;\n    rtl_sha512_free = 0x1012ddd5;\n    rtl_sha512_clone = 0x1012dde9;\n    rtl_sha512_starts = 0x1012ddf5;\n    rtl_sha512_process = 0x1012df29;\n    rtl_sha512_update = 0x1012ec7d;\n    rtl_sha512_finish = 0x1012ec83;\n    rtl_sha512 = 0x1012eeb9;\n    __rom_entry_ns_start__ = 0x101c0000;\n    rom_sec_call_ns_entry = 0x101c0000;\n    __rom_entry_ns_end__ = 0x101c0008;\n    SPIC_CALIB_PATTERN = 0x101c0008;\n    PORT_AB = 0x101c0024;\n    armBitRevIndexTable1024 = 0x101c004c;\n    twiddleCoef_1024 = 0x101c0e5c;\n    rtl_sha512_info = 0x101ce344;\n    rtl_sha384_info = 0x101ce374;\n    rtl_sha256_info = 0x101ce3a4;\n    rtl_sha224_info = 0x101ce3d4;\n    rtl_sha1_info = 0x101ce404;\n    rtl_md5_info = 0x101ce434;\n    rtl_rsa_alt_info = 0x101cea78;\n    rtl_ecdsa_info = 0x101ceaa8;\n    rtl_eckeydh_info = 0x101cead8;\n    rtl_eckey_info = 0x101ceb08;\n    rtl_rsa_info = 0x101ceb38;\n    __rom_bss_end_s__ = 0x200f9000;\n}\n","old_contents":"\/****************************************************************************\n *\n * Copyright 2020 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n *\n *   Copyright (C) 2020 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nOUTPUT_ARCH(arm)\nENTRY(app_start)\n\nMEMORY\n{\n\tIROM (rx) : \t\t\tORIGIN = 0x10100000, LENGTH = 0x1010A000 - 0x10100000\t\/* ROM: 40k *\/\n\tIROM_NS (rx) : \t\t\tORIGIN = 0x1010A000, LENGTH = 0x10140000 - 0x1010A000\t\/* ROM: 216k *\/\n\tDROM_NS (rx) : \t\t\tORIGIN = 0x101C0000, LENGTH = 0x101D4000 - 0x101C0000\t\/* ROM: 80k *\/\n\tDROM (rx) : \t\t\tORIGIN = 0x101D4000, LENGTH = 0x101D8000 - 0x101D4000\t\/* ROM: 16k *\/\n\tROMBSS_RAM_COM (rw)  : \t\tORIGIN = 0x10000000, LENGTH = 0x10001000 - 0x10000000\t\/* ROM BSS COMMON(S & NS both used) RAM: 4K *\/\n\tROMBSS_RAM_NS (rw)  : \t\tORIGIN = 0x10001000, LENGTH = 0x10002000 - 0x10001000\t\/* ROM BSS NS RAM: 4K *\/\n\tRSVD_RAM_NS (rw)  : \t\tORIGIN = 0x10002000, LENGTH = 0x10004000 - 0x10002000\t\/* RSVD RAM: 8K *\/\n\tMSP_RAM_NS (rw)  : \t\tORIGIN = 0x10004000, LENGTH = 0x10005000 - 0x10004000\t\/* MSP_NS RAM: 4K *\/\n\n\tBD_RAM_NS (rwx)  : \t\tORIGIN = 0x10005000, LENGTH = 0x10077000 - 0x10005000\t\/* MAIN RAM NS: 456K *\/\n\tBD_RAM_S (rwx)  : \t\tORIGIN = 0x10077000, LENGTH = 0x1007B000 - 0x10077000\t\/* MAIN RAM S: 16K *\/\n\tBD_RAM_NSC (rwx)  : \t\tORIGIN = 0x1007B000, LENGTH = 0x1007C000 - 0x1007B000\t\/* MAIN RAM NSC: 4K *\/\n\tROMBSS_RAM_S (rwx)  : \t\tORIGIN = 0x1007C000, LENGTH = 0x1007D000 - 0x1007C000\t\/* ROM BSS RAM S: 4K *\/\n\tBOOTLOADER_RAM_S (rwx)  : \tORIGIN = 0x1007D000, LENGTH = 0x1007F000 - 0x1007D000\t\/* BOOT Loader RAM: 8K *\/\n\tMSP_RAM_S (rwx)  : \t\tORIGIN = 0x1007F000, LENGTH = 0x10080000 - 0x1007F000\t\/* MSP_S RAM: 4k *\/\n\tEXTENTION_SRAM (rwx)  : \t\tORIGIN = 0x100E0000, LENGTH = 0x10100000 - 0x100E0000\t\/* EXTENTION SRAM: 128k *\/\n\n\tPSRAM_NS (rwx)  : \t\tORIGIN = 0x02000000, LENGTH = 0x023C0000 - 0x02000000\t\/* PSRAM_NS: 3M 744K*\/\n\tPSRAM_S (rwx)\t:\t\tORIGIN = 0x023C0000, LENGTH = 0x02400000 - 0x023C0000\t\/* PSRAM_S: 256K *\/\n\n\t\/* Flash *\/\n\tKM0_BOOT (rx)  :\t\tORIGIN = 0x08000000+0x20, LENGTH = 0x02000-0x20\t\/* XIPBOOT: 8k, 32 Bytes resvd for header*\/\n\tBACKUP (r) :\t\t\tORIGIN = 0x08002000, LENGTH = 0x1000\t\/* BACKUP: 4K system data in flash *\/\n\tXIPSYS (r) :\t\t\tORIGIN = 0x08003000, LENGTH = 0x1000\t\/* XIPSYS: 4K system data in flash *\/\n\tKM4_BOOT (rx)  :\t\tORIGIN = 0x08004000+0x20, LENGTH = 0x02000-0x20\t\/* XIPBOOT: 8k, 32 Bytes resvd for header*\/\n\tKM0_IMG2 (rx)  : \t\tORIGIN = 0x0C000000+0x20, LENGTH = 0x02000000-0x20\t\/* KM0_IMG2: 32MB, 32 Bytes resvd for header, virtual address *\/\n\tKM4_IMG2 (rx)  : \t\tORIGIN = 0x0E000000+0x20, LENGTH = 0x02000000-0x20\t\/* KM4_IMG2 OTA1: 32MB, 32 Bytes resvd for header,  virtual address *\/\n\tBTRACE (rx) :\t\t\tORIGIN = 0x00800000, LENGTH = 0x00C00000 -0x00800000\t\/* Bluetooth Trace *\/\n\n\t\/* KM0 RAM*\/\n\tKM0_SRAM (rwx)  : \t\tORIGIN = 0x00080000, LENGTH = 0x00090000 - 0x00080000\t\/* KM0 SRAM: 64k *\/\n\tRETENTION_RAM (rwx)  : \t\tORIGIN = 0x000C0000, LENGTH = 0x000C0400 - 0x000C0000\t\/* KM0 Retention SRAM: 1k *\/\n}\n\nSECTIONS\n{\n\t.rom.text : { } > IROM_NS\n\t.rom.rodata : { } > DROM_NS\n\t.hal.rom.bss : { } > ROMBSS_RAM_COM\n\t.hal.ns_rom.bss : { } > ROMBSS_RAM_NS\n\n\t\/* image2: normal image start *\/\n\t.ram_image2.entry :\n\t{\n\t\t__ram_image2_text_start__ = .;\n\t\t__image2_entry_func__ = .;\n\t\tKEEP(*(SORT(.image2.entry.data*)))\n\n\t\t__image2_validate_code__ = .;\n\t\tKEEP(*(.image2.validate.rodata*))\n\n\t} > BD_RAM_NS\n\n\t.ram_image2.text :\n\t{\n\t\t__ram_text_start__ = .;\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.image2.ram.text*)\n\t\t*(.image2.net.ram.text*)\n\t\t\/*os*\/\n\t\t*os_start.o (.text*)\n\t\t*osdep_service.o (.text*)\n\t\t*tizenrt_service.o (.text*)\n\t\t\/*irq(svcall)*\/\n\t\t\/**irq_initialize.o (.text*)*\/\n\t\t*amebad_irq.o (.text*)\n\t\t*up_exception.o (.text*)\n\t\t*up_svcall.o (.text*)\n\t\t*up_switchcontext.o (.text*)\n\t\t*up_copyfullstate.o (.text*)\n\t\t*up_fullcontextrestore.o (.text*)\n\t\t*up_doirq.o (.text*)\n\t\t*irq_dispatch.o (.text*)\n\t\t\/*scheduler(for semphr)*\/\n\t\t*sched_addreadytorun.o (.text*)\n\t\t*sched_addblocked.o (.text*)\n\t\t*sched_addprioritized.o (.text*)\n\t\t*sched_removereadytorun.o (.text*)\n\t\t*sched_removeblocked.o (.text*)\n\t\t*sched_mergepending.o (.text*)\n\t\t*up_blocktask.o (.text*)\n\t\t*up_unblocktask.o (.text*)\n\t\t\/*semphr*\/\n\t\t*sem_wait.o (.text*)\n\t\t*sem_waitirq.o (.text*)\n\t\t*sem_trywait.o (.text*)\n\t\t*sem_tickwait.o (.text*)\n\t\t*sem_timedwait.o (.text*)\n\t\t*sem_post.o (.text*)\n\t\t\/*lwip*\/\n\t\t*tcp_in.o (.text*)\n\t\t*tcp_out.o (.text*)\n\t\t*def.o (.text*)\n\t\t*igmp.o (.text*)\n\t\t*pbuf.o (.text*)\n\t\t*inet_chksum.o (.text*)\n\t\t*api_msg.o (.text*)\n\t\t*netbuf.o (.text*)\n\t\t*sys_arch.o (.text*)\n\t\t*ethernetif_tizenrt.o (.text*)\n\t\t*lwip_intf_tizenrt.o (.text*)\n\t\t*timeout.o (.text*)\n\t\t*raw.o (.text*)\n\t\t*mem.o (.text*)\n\t\t*memp.o (.text*)\n\t\t*netif.o (.text*)\n\t\t*ip.o (.text*)\n\t\t*ip4.o (.text*)\n\t\t*ip4_addr.o (.text*)\n\t\t*ip4_frag.o (.text*)\n\t\t*ip6.o (.text*)\n\t\t*ip6_addr.o (.text*)\n\t\t*ip6_frag.o (.text*)\n\t\t*tcp.o (.text*)\n\t\t*udp.o (.text*)\n\t\t*socket.o (.text*)\n\t\t*bsd_socket_api.o (.text*)\n\t\t*tcpip.o (.text*)\n\t\t*ethernet.o (.text*)\n\t\t*etharp.o (.text*)\n\t\t*ethip6.o (.text*)\n\t\t*netdb.o (.text*)\n\t\t*api_lib.o (.text*)\n\t\t*netifapi.o (.text*)\n\t\t\/*iperf*\/\n\t\t*iperf_server_api.o (.text*)\n\t\t*iperf_api.o (.text*)\n\t\t*iperf_tcp.o (.text*)\n\t\t*iperf_net.o (.text*)\n\t\t\/*fs*\/\n\t\t\/**fs_read.o (.text*)\n\t\t*fs_select.o (.text*)\n\t\t*fs_poll.o (.text*)*\/\n\t\t\/*others*\/\n\t\t*lib_vikmemcpy.o (.text*)\n\t\t*dq_rem.o (.text*)\n\t\t*dq_addlast.o (.text*)\n\t\t_etext = ABSOLUTE(.);\n\t\t__ram_text_end__ = .;\n\t} > BD_RAM_NS\n\n\t_eronly = ABSOLUTE(.);\n\n\t.ram_image2.data :\n\t{\n\t\t_sdata = ABSOLUTE(.);\n\t\t__data_start__ = .;\n\t\t*(.data*)\n\t\t__data_end__ = .;\n\t\t_edata = ABSOLUTE(.);\n\t\t__ram_image2_text_end__ = .;\n\t\t. = ALIGN(16);\n\t} > BD_RAM_NS\n\n\t.ram_image2.bss :\n\t{\n\t\t_sbss = ABSOLUTE(.);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t__bss_end__ = .;\n\n\t} > BD_RAM_NS\n\n\t.ram_image2.nocache.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t__ram_nocache_start__ = .;\n\t\t*(.bdsram.data*)\n\t\t. = ALIGN (32);\n\t\t__ram_nocache_end__ = .;\n\t} > BD_RAM_NS\n\n\t.ram_heap.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.bfsram.data*)\n\t\tend = .;\n\t\t_ebss = ABSOLUTE(.);\n\t} > BD_RAM_NS\n\n\n\t.xip_image2.text :\n\t{\n\t\t__flash_text_start__ = .;\n\n\t\t*(.img2_custom_signature*)\n\n\t\t*(.text*)\n\t\/*\t*(.image2.net.ram.text*) *\/\n\t\t*(.rodata*)\n\n\t\t\/* Add This for C++ support *\/\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP(*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\t__init_array_end = .;\n\t\t. = ALIGN(4);\n\t\t__fini_array_start = .;\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\t__fini_array_end = .;\n\t\t\/*-----------------*\/\n\n\t\t. = ALIGN (4);\n\t\t__cmd_table_start__ = .;\n\t\tKEEP(*(.cmd.table.data*))\n\t\t__cmd_table_end__ = .;\n\n\t\t__flash_text_end__ = .;\n\n\t\t. = ALIGN (16);\n\t} > KM4_IMG2\n\n\t\/* Add This for C++ support *\/\n\t.ARM.extab  :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\n\t} > KM4_IMG2\n\n\t.ARM.exidx :\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > KM4_IMG2\n\t\/*-----------------*\/\n\n\t.bluetooth_trace.text :\n\t{\n\t\t__btrace_start__ = .;\n\t\t*(.BTTRACE)\n\t\t__btrace_end__ = .;\n\t} > BTRACE\n\n\t\/* PSRAM_NS image start *\/\n\t.psram_image2.text :\n\t{\n\t\t__psram_image2_text_start__ = .;\n\t\t*(.psram.text*)\n\t\t__psram_image2_text_end__ = .;\n\t} > PSRAM_NS\n\n\t.psram_image2.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.psram.data*)\n\t\t. = ALIGN (32);\n\t\t*(.psram.rodata*)\n\t} > PSRAM_NS\n\n\t.psram_image2.bss :\n\t{\n\t\t. = ALIGN (32);\n\t\t__psram_bss_start__ = .;\n\t\t*(.psram.bss*)\n\t\t__psram_bss_end__ = .;\n\t} > PSRAM_NS\n\n\t.psram_heap.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.psram.heap*)\n\t} > PSRAM_NS\n\t__StackLimit = ABSOLUTE(ORIGIN(BD_RAM_NS) + LENGTH(BD_RAM_NS));\n\t__PsramStackLimit = ABSOLUTE(ORIGIN(PSRAM_NS) + LENGTH(PSRAM_NS));\n}\nSECTIONS\n{\n    __rom_bss_start__ = 0x10000000;\n    ConfigDebugClose = 0x10000000;\n    ConfigDebugBuffer = 0x10000004;\n    ConfigDebugBufferGet = 0x10000008;\n    ConfigDebug = 0x1000000c;\n    rand_first = 0x1000001c;\n    rand_seed = 0x10000020;\n    RBSS_UDELAY_DIV = 0x10000034;\n    flash_init_para = 0x10000038;\n    GDMA_Reg = 0x10000098;\n    PortA_IrqHandler = 0x1000009c;\n    PortA_IrqData = 0x1000011c;\n    PortB_IrqHandler = 0x1000019c;\n    PortB_IrqData = 0x1000021c;\n    IPC_IrqHandler = 0x1000029c;\n    IPC_IrqData = 0x1000031c;\n    IS_FPGA_VERIF = 0x1000039c;\n    crypto_engine = 0x100003a0;\n    __rom_bss_end__ = 0x10000564;\n    __rom_bss_start_ns__ = 0x10001000;\n    NewVectorTable = 0x10001000;\n    UserIrqFunTable = 0x10001140;\n    UserIrqDataTable = 0x10001240;\n    mpu_entry_register = 0x10001340;\n    p_rom_ssl_ram_map = 0x10001348;\n    rom_ssl_ram_map = 0x1000134c;\n    __rom_bss_end_ns__ = 0x1000138c;\n    __rom_bss_start_s__ = 0x1007c000;\n    __ram_start_table_start__ = 0x1007d000;\n    STACK_TOP = 0x1007effc;\n    __vectors_table = 0x1010a000;\n    Reset_Handler = 0x1010a101;\n    NMI_Handler = 0x1010a111;\n    HardFault_Handler = 0x1010a115;\n    MemManage_Handler = 0x1010a119;\n    BusFault_Handler = 0x1010a11d;\n    UsageFault_Handler = 0x1010a121;\n    SecureFault_Handler = 0x1010a125;\n    DiagVSprintf = 0x1010a12d;\n    DiagPrintf = 0x1010a3f5;\n    DiagPrintfD = 0x1010a445;\n    DiagSPrintf = 0x1010a471;\n    DiagSnPrintf = 0x1010a49d;\n    Rand = 0x1010a765;\n    Rand_Arc4 = 0x1010a7f1;\n    RandBytes_Get = 0x1010a825;\n    io_assert_failed = 0x1010a871;\n    BKUP_Write = 0x1010a891;\n    BKUP_Read = 0x1010a8b5;\n    BKUP_Set = 0x1010a8d5;\n    BKUP_Clear = 0x1010a8fd;\n    BOOT_Reason = 0x1010a929;\n    DelayNop = 0x1010a939;\n    DelayUs = 0x1010a949;\n    DelayMs = 0x1010a995;\n    EFUSEPowerSwitch = 0x1010a9a9;\n    EFUSERead8 = 0x1010aa31;\n    EFUSEWrite8 = 0x1010ab1d;\n    EFUSE_PG_Packet = 0x1010ac21;\n    EFUSE_LogicalMap_Read = 0x1010ae99;\n    EFUSE_LogicalMap_Write = 0x1010afad;\n    FLASH_RxData = 0x1010b195;\n    FLASH_TxCmd = 0x1010b29d;\n    FLASH_SW_CS_Control = 0x1010b329;\n    FLASH_SetSpiMode = 0x1010b37d;\n    FLASH_RxCmd = 0x1010b415;\n    FLASH_WaitBusy = 0x1010b479;\n    FLASH_WriteEn = 0x1010b4f9;\n    FLASH_TxData256B = 0x1010b51d;\n    FLASH_TxData12B = 0x1010b60d;\n    FLASH_SetStatus = 0x1010b6ed;\n    FLASH_Erase = 0x1010b70d;\n    FLASH_DeepPowerDown = 0x1010b7b9;\n    FLASH_SetStatusBits = 0x1010b809;\n    FLASH_StructInit_Micron = 0x1010b8dd;\n    FLASH_StructInit_MXIC = 0x1010b98d;\n    FLASH_StructInit_GD = 0x1010ba39;\n    FLASH_StructInit = 0x1010baed;\n    FLASH_Init = 0x1010bba1;\n    GDMA_StructInit = 0x1010bc25;\n    GDMA_SetLLP = 0x1010bc45;\n    GDMA_ClearINTPendingBit = 0x1010bcd9;\n    GDMA_ClearINT = 0x1010bda5;\n    GDMA_INTConfig = 0x1010be75;\n    GDMA_Cmd = 0x1010bf91;\n    GDMA_Init = 0x1010bff9;\n    GDMA_ChCleanAutoReload = 0x1010c14d;\n    GDMA_SetSrcAddr = 0x1010c1d1;\n    GDMA_GetSrcAddr = 0x1010c221;\n    GDMA_GetDstAddr = 0x1010c26d;\n    GDMA_SetDstAddr = 0x1010c2b9;\n    GDMA_SetBlkSize = 0x1010c309;\n    GDMA_GetBlkSize = 0x1010c369;\n    GDMA_ChnlRegister = 0x1010c3b9;\n    GDMA_ChnlUnRegister = 0x1010c401;\n    GDMA_ChnlAlloc = 0x1010c43d;\n    GDMA_ChnlFree = 0x1010c4d9;\n    GDMA_GetIrqNum = 0x1010c565;\n    GPIO_INTMode = 0x1010c5a9;\n    GPIO_INTConfig = 0x1010c641;\n    GPIO_INTHandler = 0x1010c679;\n    GPIO_Direction = 0x1010c721;\n    GPIO_Init = 0x1010c755;\n    GPIO_DeInit = 0x1010c7e1;\n    GPIO_ReadDataBit = 0x1010c84d;\n    GPIO_WriteBit = 0x1010c871;\n    GPIO_PortDirection = 0x1010c8a1;\n    GPIO_PortRead = 0x1010c8c5;\n    GPIO_PortWrite = 0x1010c8d5;\n    GPIO_UserRegIrq = 0x1010c8ed;\n    IPC_INTConfig = 0x1010c925;\n    IPC_IERSet = 0x1010c939;\n    IPC_IERGet = 0x1010c93d;\n    IPC_INTRequest = 0x1010c941;\n    IPC_INTClear = 0x1010c94d;\n    IPC_INTGet = 0x1010c959;\n    IPC_CPUID = 0x1010c95d;\n    IPC_SEMGet = 0x1010c969;\n    IPC_SEMFree = 0x1010c9b9;\n    IPC_INTHandler = 0x1010ca21;\n    IPC_INTUserHandler = 0x1010ca61;\n    LOGUART_StructInit = 0x1010ca9d;\n    LOGUART_Init = 0x1010cab5;\n    LOGUART_PutChar = 0x1010caf5;\n    LOGUART_GetChar = 0x1010cb29;\n    LOGUART_Readable = 0x1010cb45;\n    LOGUART_GetIMR = 0x1010cb59;\n    LOGUART_SetIMR = 0x1010cb65;\n    LOGUART_WaitBusy = 0x1010cb71;\n    LOGUART_SetBaud = 0x1010cb91;\n    mpu_enable = 0x1010cbd5;\n    mpu_disable = 0x1010cbed;\n    mpu_init = 0x1010cc01;\n    mpu_set_mem_attr = 0x1010cc3d;\n    mpu_region_cfg = 0x1010ccb1;\n    mpu_entry_free = 0x1010cdb5;\n    mpu_entry_alloc = 0x1010cdc1;\n    RSIP_Cmd = 0x1010cde9;\n    RSIP_OTF_init = 0x1010ce05;\n    RSIP_OTF_Cmd = 0x1010ce6d;\n    RSIP_OTF_Mask = 0x1010ce81;\n    RSIP_KEY_Request = 0x1010cec9;\n    RSIP_MMU_Config = 0x1010cf0d;\n    RSIP_MMU_Cmd = 0x1010cf31;\n    PAD_DrvStrength = 0x1010cf51;\n    PAD_PullCtrl = 0x1010cf6d;\n    PAD_CMD = 0x1010cf99;\n    Pinmux_Config = 0x1010cfb9;\n    Pinmux_ConfigGet = 0x1010cfd9;\n    Pinmux_UartLogCtrl = 0x1010cfe9;\n    Pinmux_SpicCtrl = 0x1010d03d;\n    simulation_bit_index = 0x1010d181;\n    simulation_stage_set = 0x1010d199;\n    SYSTIMER_Init = 0x1010d1c5;\n    SYSTIMER_TickGet = 0x1010d215;\n    SYSTIMER_GetPassTime = 0x1010d225;\n    RTIM_TimeBaseStructInit = 0x1010d255;\n    RTIM_Cmd = 0x1010d26d;\n    RTIM_GetCount = 0x1010d2f5;\n    RTIM_INTConfig = 0x1010d361;\n    RTIM_INTClear = 0x1010d3f1;\n    RTIM_TimeBaseInit = 0x1010d45d;\n    RTIM_DeInit = 0x1010d595;\n    RTIM_INTClearPendingBit = 0x1010d611;\n    RTIM_GetFlagStatus = 0x1010d685;\n    RTIM_GetINTStatus = 0x1010d75d;\n    UART_DeInit = 0x1010d83d;\n    UART_StructInit = 0x1010d845;\n    UART_BaudParaGetFull = 0x1010d861;\n    UART_BaudParaGet = 0x1010d899;\n    UART_SetBaud = 0x1010d8bd;\n    UART_SetBaudExt = 0x1010d955;\n    UART_SetRxLevel = 0x1010d9cd;\n    UART_RxCmd = 0x1010d9f5;\n    UART_Writable = 0x1010da09;\n    UART_Readable = 0x1010da11;\n    UART_CharPut = 0x1010da19;\n    UART_CharGet = 0x1010da1d;\n    UART_ReceiveData = 0x1010da25;\n    UART_SendData = 0x1010da4d;\n    UART_ReceiveDataTO = 0x1010da75;\n    UART_SendDataTO = 0x1010dab5;\n    UART_RxByteCntClear = 0x1010daf5;\n    UART_RxByteCntGet = 0x1010db01;\n    UART_BreakCtl = 0x1010db09;\n    UART_ClearRxFifo = 0x1010db1d;\n    UART_Init = 0x1010db3d;\n    UART_ClearTxFifo = 0x1010dbe5;\n    UART_INTConfig = 0x1010dbf1;\n    UART_IntStatus = 0x1010dc01;\n    UART_ModemStatusGet = 0x1010dc05;\n    UART_LineStatusGet = 0x1010dc09;\n    UART_WaitBusy = 0x1010dc0d;\n    rtl_crypto_aes_cbc_init = 0x1010dc31;\n    rtl_crypto_aes_cbc_encrypt = 0x1010dc81;\n    rtl_crypto_aes_cbc_decrypt = 0x1010dccd;\n    rtl_crypto_aes_ecb_init = 0x1010dd19;\n    rtl_crypto_aes_ecb_encrypt = 0x1010dd69;\n    rtl_crypto_aes_ecb_decrypt = 0x1010dda1;\n    rtl_crypto_aes_ctr_init = 0x1010ddd9;\n    rtl_crypto_aes_ctr_encrypt = 0x1010de29;\n    rtl_crypto_aes_ctr_decrypt = 0x1010de6d;\n    rtl_crypto_aes_cfb_init = 0x1010deb1;\n    rtl_crypto_aes_cfb_encrypt = 0x1010df01;\n    rtl_crypto_aes_cfb_decrypt = 0x1010df45;\n    rtl_crypto_aes_ofb_init = 0x1010df89;\n    rtl_crypto_aes_ofb_encrypt = 0x1010dfdd;\n    rtl_crypto_aes_ofb_decrypt = 0x1010e021;\n    rtl_crypto_aes_gcm_init = 0x1010e065;\n    rtl_crypto_aes_gcm_encrypt = 0x1010e0b9;\n    rtl_crypto_aes_gcm_decrypt = 0x1010e131;\n    BOOT_ROM_SignatureCheck = 0x1010e1a9;\n    BOOT_ROM_FromFlash = 0x1010e281;\n    BOOT_ROM_InitDebugFlg = 0x1010e38d;\n    BOOT_ROM_ResetVsr = 0x1010e3a9;\n    EXT32K_Cmd = 0x1010e4c9;\n    XTAL_ClkGet = 0x1010e4e9;\n    CPU_ClkSet = 0x1010e501;\n    CPU_ClkGet = 0x1010e515;\n    CRYPTO_MemDump = 0x1010e539;\n    CRYPTO_RegDump = 0x1010e601;\n    CRYPTO_CleanCmdOk = 0x1010e7c1;\n    CRYPTO_ClearAllINT = 0x1010e7f9;\n    CRYPTO_Reset = 0x1010e829;\n    CRYPTO_SetSecurityModeAD = 0x1010e86d;\n    CRYPTO_Init = 0x1010ea49;\n    CRYPTO_ProcessAD = 0x1010ea6d;\n    CRYPTO_SendSeqBuf = 0x1010f681;\n    CRYPTO_CipherInit = 0x1010f799;\n    CRYPTO_CipherEncryptAD = 0x1010f7b9;\n    CRYPTO_CipherDecryptAD = 0x1010f7e9;\n    rtl_crypto_3des_cbc_init = 0x1010f819;\n    rtl_crypto_3des_cbc_encrypt = 0x1010f869;\n    rtl_crypto_3des_cbc_decrypt = 0x1010f8b5;\n    rtl_crypto_3des_ecb_init = 0x1010f901;\n    rtl_crypto_3des_ecb_encrypt = 0x1010f951;\n    rtl_crypto_3des_ecb_decrypt = 0x1010f989;\n    rtl_crypto_3des_cfb_init = 0x1010f9c1;\n    rtl_crypto_3des_cfb_encrypt = 0x1010fa11;\n    rtl_crypto_3des_cfb_decrypt = 0x1010fa49;\n    rtl_crypto_3des_ofb_init = 0x1010fa81;\n    rtl_crypto_3des_ofb_encrypt = 0x1010fad1;\n    rtl_crypto_3des_ofb_decrypt = 0x1010fb09;\n    rtl_crypto_3des_ctr_init = 0x1010fb41;\n    rtl_crypto_3des_ctr_encrypt = 0x1010fb95;\n    rtl_crypto_3des_ctr_decrypt = 0x1010fbcd;\n    rtl_crypto_des_cbc_init = 0x1010fc05;\n    rtl_crypto_des_cbc_encrypt = 0x1010fc59;\n    rtl_crypto_des_cbc_decrypt = 0x1010fcb5;\n    rtl_crypto_des_ecb_init = 0x1010fd11;\n    rtl_crypto_des_ecb_encrypt = 0x1010fd65;\n    rtl_crypto_des_ecb_decrypt = 0x1010fd9d;\n    rtl_crypto_des_cfb_init = 0x1010fdd5;\n    rtl_crypto_des_cfb_encrypt = 0x1010fe29;\n    rtl_crypto_des_cfb_decrypt = 0x1010fe61;\n    rtl_crypto_des_ofb_init = 0x1010fe99;\n    rtl_crypto_des_ofb_encrypt = 0x1010feed;\n    rtl_crypto_des_ofb_decrypt = 0x1010ff25;\n    rtl_crypto_des_ctr_init = 0x1010ff5d;\n    rtl_crypto_des_ctr_encrypt = 0x1010ffb1;\n    rtl_crypto_des_ctr_decrypt = 0x1010ffe9;\n    clear_ns_rom_bss = 0x10110021;\n    RCC_PeriphClockCmd = 0x10110039;\n    RCC_PeriphClockSource_RTC = 0x101100d1;\n    RCC_PeriphClockSource_I2C = 0x1011011d;\n    RCC_PeriphClockSource_QDEC = 0x1011013d;\n    RCC_PeriphClockSource_UART = 0x1011015d;\n    SYSCFG_GetChipInfo = 0x101101d1;\n    INT_HardFault = 0x101101dd;\n    INT_MemManage = 0x101101fd;\n    INT_BusFault = 0x1011021d;\n    INT_UsageFault = 0x1011023d;\n    INT_SecureFault = 0x1011025d;\n    INT_HardFault_C = 0x1011027d;\n    INT_NMI = 0x1011064d;\n    irq_table_init = 0x10110795;\n    \/\/irq_enable = 0x101109d1;\n    \/\/irq_disable = 0x101109ed;\n    \/\/irq_set_priority = 0x10110a11;\n    \/\/irq_get_priority = 0x10110a3d;\n    \/\/irq_set_pending = 0x10110a65;\n    \/\/irq_get_pending = 0x10110a81;\n    \/\/irq_clear_pending = 0x10110aa5;\n    \/\/irq_register = 0x10110ac1;\n    \/\/irq_unregister = 0x10110b0d;\n    _char2num = 0x10110b2d;\n    _2char2dec = 0x10110b5d;\n    _2char2hex = 0x10110bd1;\n    _memchr = 0x10110c39;\n    _memcmp = 0x10110cc9;\n    _memcpy = 0x10110d2d;\n    _memmove = 0x10110dd9;\n    _memset = 0x10110ea1;\n    _vsscanf = 0x10110ffd;\n    _sscanf = 0x101115c1;\n    _stratoi = 0x101115e1;\n    _strcat = 0x10111635;\n    _strchr = 0x10111675;\n    _strcmp = 0x10111745;\n    _strcpy = 0x101117b9;\n    _stricmp = 0x10111805;\n    _strlen = 0x10111839;\n    _strncat = 0x1011189d;\n    _strncmp = 0x101118f9;\n    _strncpy = 0x1011199d;\n    _strnlen = 0x10111a05;\n    _strpbrk = 0x10111a39;\n    _strsep = 0x10111a65;\n    _strstr = 0x10111d25;\n    _strtoull = 0x10111f3d;\n    _strtoll = 0x10111ffd;\n    _strtok = 0x1011201d;\n    __strtok_r = 0x10112029;\n    _strtok_r = 0x1011208d;\n    _strtol_r = 0x10112095;\n    _strtol = 0x101121b1;\n    _strtoul_r = 0x101121b5;\n    _strtoul = 0x101122e9;\n    _strupr = 0x101122ed;\n    CRYPTO_chacha_20 = 0x10112309;\n    rom_ed25519_gen_keypair = 0x101125c5;\n    rom_ed25519_gen_signature = 0x101125c9;\n    rom_ed25519_verify_signature = 0x101125df;\n    rom_ed25519_ge_double_scalarmult_vartime = 0x10113e89;\n    rom_ed25519_ge_frombytes_negate_vartime = 0x10114195;\n    rom_ed25519_ge_p3_tobytes = 0x10114695;\n    rom_ed25519_ge_scalarmult_base = 0x101146df;\n    rom_ed25519_ge_tobytes = 0x10114807;\n    rom_ed25519_crypto_sign_seed_keypair = 0x10114851;\n    rom_ed25519_crypto_sign_verify_detached = 0x101148a9;\n    rom_ed25519_sc_muladd = 0x10114ad5;\n    rom_ed25519_sc_reduce = 0x1011b265;\n    rom_ed25519_crypto_sign_detached = 0x1011c6dd;\n    CRYPTO_poly1305_init = 0x1011ca99;\n    CRYPTO_poly1305_update = 0x1011cb31;\n    CRYPTO_poly1305_finish = 0x1011cba7;\n    rom_sha512_starts = 0x1011cd4d;\n    rom_sha512_update = 0x1011cd51;\n    rom_sha512_finish = 0x1011cd55;\n    rom_sha512 = 0x1011cd59;\n    rom_sha512_hmac_starts = 0x1011cd5d;\n    rom_sha512_hmac_update = 0x1011cdf1;\n    rom_sha512_hmac_finish = 0x1011cdf5;\n    rom_sha512_hmac_reset = 0x1011ce49;\n    rom_sha512_hmac = 0x1011ce65;\n    rom_sha512_hkdf = 0x1011cea1;\n    curve25519_donna = 0x1011dce5;\n    rtl_aes_init = 0x1011e569;\n    rtl_aes_free = 0x1011e579;\n    rtl_aes_setkey_enc = 0x1011e58d;\n    rtl_aes_setkey_dec = 0x1011e7a5;\n    rtl_aes_encrypt = 0x1011e8c1;\n    rtl_aes_decrypt = 0x1011ecf9;\n    rtl_aes_crypt_ecb = 0x1011f145;\n    rtl_aes_crypt_cbc = 0x1011f1c9;\n    rtl_aes_crypt_cfb128 = 0x1011f3d5;\n    rtl_aes_crypt_cfb8 = 0x1011f44b;\n    rtl_aes_crypt_ctr = 0x1011f4b1;\n    rtl_arc4_init = 0x1011f515;\n    rtl_arc4_free = 0x1011f525;\n    rtl_arc4_setup = 0x1011f539;\n    rtl_arc4_crypt = 0x1011f57f;\n    rtl_asn1_get_len = 0x1011f5c5;\n    rtl_asn1_get_tag = 0x1011f661;\n    rtl_asn1_get_bool = 0x1011f689;\n    rtl_asn1_get_int = 0x1011f6b9;\n    rtl_asn1_get_mpi = 0x1011f6ff;\n    rtl_asn1_get_bitstring = 0x1011f725;\n    rtl_asn1_get_bitstring_null = 0x1011f76d;\n    rtl_asn1_get_sequence_of = 0x1011f795;\n    rtl_asn1_get_alg = 0x1011f81d;\n    rtl_asn1_get_alg_null = 0x1011f8a9;\n    rtl_asn1_free_named_data = 0x1011f8ed;\n    rtl_asn1_free_named_data_list = 0x1011f91d;\n    rtl_asn1_find_named_data = 0x1011f941;\n    rtl_asn1_write_len = 0x1011f96d;\n    rtl_asn1_write_tag = 0x1011fa55;\n    rtl_asn1_write_raw_buffer = 0x1011fa71;\n    rtl_asn1_write_mpi = 0x1011faa1;\n    rtl_asn1_write_null = 0x1011fb13;\n    rtl_asn1_write_oid = 0x1011fb39;\n    rtl_asn1_write_algorithm_identifier = 0x1011fb6d;\n    rtl_asn1_write_bool = 0x1011fbbd;\n    rtl_asn1_write_int = 0x1011fbff;\n    rtl_asn1_write_printable_string = 0x1011fc61;\n    rtl_asn1_write_ia5_string = 0x1011fc95;\n    rtl_asn1_write_bitstring = 0x1011fcc9;\n    rtl_asn1_write_octet_string = 0x1011fd3d;\n    rtl_asn1_store_named_data = 0x1011fd71;\n    rtl_base64_encode = 0x1011fe29;\n    rtl_base64_decode = 0x1011ff2d;\n    rtl_mpi_init = 0x10120b19;\n    rtl_mpi_free = 0x10120b27;\n    rtl_mpi_grow = 0x10120b5d;\n    rtl_mpi_shrink = 0x10120bc1;\n    rtl_mpi_copy = 0x10120c41;\n    rtl_mpi_swap = 0x10120c9d;\n    rtl_mpi_safe_cond_assign = 0x10120cc5;\n    rtl_mpi_safe_cond_swap = 0x10120d31;\n    rtl_mpi_lset = 0x10120db3;\n    rtl_mpi_get_bit = 0x10120df1;\n    rtl_mpi_set_bit = 0x10120e11;\n    rtl_mpi_lsb = 0x10120e61;\n    rtl_mpi_bitlen = 0x10120e93;\n    rtl_mpi_size = 0x10120ed3;\n    rtl_mpi_read_binary = 0x10120edf;\n    rtl_mpi_write_binary = 0x10120f47;\n    rtl_mpi_shift_l = 0x10120f91;\n    rtl_mpi_shift_r = 0x1012102d;\n    rtl_mpi_cmp_abs = 0x101210ab;\n    rtl_mpi_cmp_mpi = 0x101211ed;\n    rtl_mpi_cmp_int = 0x10121277;\n    rtl_mpi_add_abs = 0x101212a3;\n    rtl_mpi_sub_abs = 0x10121357;\n    rtl_mpi_add_mpi = 0x101213d5;\n    rtl_mpi_sub_mpi = 0x10121417;\n    rtl_mpi_add_int = 0x1012145b;\n    rtl_mpi_sub_int = 0x10121487;\n    rtl_mpi_mul_mpi = 0x101214b3;\n    rtl_mpi_mul_int = 0x1012158f;\n    rtl_mpi_read_string = 0x101215a9;\n    rtl_mpi_div_mpi = 0x101216c9;\n    rtl_mpi_div_int = 0x10121aeb;\n    rtl_mpi_mod_mpi = 0x10121b15;\n    rtl_mpi_mod_int = 0x10121b75;\n    rtl_mpi_write_string = 0x10121c15;\n    rtl_mpi_exp_mod = 0x10121d6d;\n    rtl_mpi_gcd = 0x101221a5;\n    rtl_mpi_fill_random = 0x101222af;\n    rtl_mpi_inv_mod = 0x101224f9;\n    rtl_mpi_is_prime = 0x101227b5;\n    rtl_mpi_gen_prime = 0x10122809;\n    rtl_ctr_drbg_init = 0x10122ae9;\n    rtl_ctr_drbg_free = 0x10122af9;\n    rtl_ctr_drbg_set_prediction_resistance = 0x10122b17;\n    rtl_ctr_drbg_set_entropy_len = 0x10122b1b;\n    rtl_ctr_drbg_set_reseed_interval = 0x10122b1f;\n    rtl_ctr_drbg_update = 0x10122b23;\n    rtl_ctr_drbg_reseed = 0x10122b47;\n    rtl_ctr_drbg_seed_entropy_len = 0x10122bc5;\n    rtl_ctr_drbg_seed = 0x10122c19;\n    rtl_ctr_drbg_random_with_add = 0x10122c2b;\n    rtl_ctr_drbg_random = 0x10122cf1;\n    rtl_des_init = 0x10122d11;\n    rtl_des_free = 0x10122d1d;\n    rtl_des3_init = 0x10122d25;\n    rtl_des3_free = 0x10122d35;\n    rtl_des_key_set_parity = 0x10122d3f;\n    rtl_des_key_check_key_parity = 0x10122d59;\n    rtl_des_key_check_weak = 0x10122d7d;\n    rtl_des_setkey = 0x10122da9;\n    rtl_des_setkey_enc = 0x101231bb;\n    rtl_des_setkey_dec = 0x101231e5;\n    rtl_des3_set2key_enc = 0x10123239;\n    rtl_des3_set2key_dec = 0x1012327d;\n    rtl_des3_set3key_enc = 0x101232c1;\n    rtl_des3_set3key_dec = 0x101232fd;\n    rtl_des_crypt_ecb = 0x10123339;\n    rtl_des_crypt_cbc = 0x10123541;\n    rtl_des3_crypt_ecb = 0x10123731;\n    rtl_des3_crypt_cbc = 0x10123b81;\n    rtl_dhm_init = 0x10123e01;\n    rtl_dhm_read_params = 0x10123e0d;\n    rtl_dhm_make_params = 0x10123e59;\n    rtl_dhm_read_public = 0x10123f91;\n    rtl_dhm_make_public = 0x10123fb5;\n    rtl_dhm_calc_secret = 0x1012406d;\n    rtl_dhm_free = 0x1012426d;\n    rtl_dhm_parse_dhm = 0x101242cf;\n    rtl_ecdh_gen_public = 0x101243c1;\n    rtl_ecdh_compute_shared = 0x101243c5;\n    rtl_ecdh_init = 0x10124425;\n    rtl_ecdh_free = 0x10124435;\n    rtl_ecdh_make_params = 0x1012447d;\n    rtl_ecdh_read_params = 0x101244ed;\n    rtl_ecdh_get_params = 0x10124515;\n    rtl_ecdh_make_public = 0x10124561;\n    rtl_ecdh_read_public = 0x101245b1;\n    rtl_ecdh_calc_secret = 0x101245dd;\n    rtl_ecdsa_sign = 0x10124693;\n    rtl_ecdsa_sign_det = 0x10124815;\n    rtl_ecdsa_verify = 0x101248bd;\n    rtl_ecdsa_write_signature = 0x101249f9;\n    rtl_ecdsa_write_signature_det = 0x10124a9d;\n    rtl_ecdsa_read_signature = 0x10124abb;\n    rtl_ecdsa_genkey = 0x10124b55;\n    rtl_ecdsa_from_keypair = 0x10124b83;\n    rtl_ecdsa_init = 0x10124bbb;\n    rtl_ecdsa_free = 0x10124bbf;\n    rtl_ecjpake_init = 0x10124ff5;\n    rtl_ecjpake_free = 0x1012504f;\n    rtl_ecjpake_setup = 0x101250a5;\n    rtl_ecjpake_check = 0x101250e9;\n    rtl_ecjpake_read_round_one = 0x10125109;\n    rtl_ecjpake_write_round_one = 0x10125185;\n    rtl_ecjpake_read_round_two = 0x101252ad;\n    rtl_ecjpake_write_round_two = 0x10125365;\n    rtl_ecjpake_derive_secret = 0x101254a1;\n    rtl_ecp_curve_list = 0x10125de9;\n    rtl_ecp_curve_info_from_grp_id = 0x10125df1;\n    rtl_ecp_curve_info_from_tls_id = 0x10125e0d;\n    rtl_ecp_curve_info_from_name = 0x10125e29;\n    rtl_ecp_point_init = 0x10125e51;\n    rtl_ecp_group_init = 0x10125e71;\n    rtl_ecp_keypair_init = 0x10125e81;\n    rtl_ecp_point_free = 0x10125ea1;\n    rtl_ecp_group_free = 0x10125ec1;\n    rtl_ecp_keypair_free = 0x10125f31;\n    rtl_ecp_copy = 0x10125f51;\n    rtl_ecp_group_copy = 0x10125f7d;\n    rtl_ecp_set_zero = 0x10125f83;\n    rtl_ecp_is_zero = 0x10126839;\n    rtl_ecp_point_cmp = 0x1012684b;\n    rtl_ecp_point_read_string = 0x1012687d;\n    rtl_ecp_point_write_binary = 0x101268a9;\n    rtl_ecp_point_read_binary = 0x1012694d;\n    rtl_ecp_tls_read_point = 0x101269b9;\n    rtl_ecp_tls_write_point = 0x101269e9;\n    rtl_ecp_tls_read_group = 0x10126a19;\n    rtl_ecp_tls_write_group = 0x10126a61;\n    rtl_ecp_check_pubkey = 0x10126a99;\n    rtl_ecp_check_privkey = 0x10126c2d;\n    rtl_ecp_mul = 0x10126c9d;\n    rtl_ecp_muladd = 0x1012726f;\n    rtl_ecp_gen_keypair_base = 0x101272d9;\n    rtl_ecp_gen_keypair = 0x101273d9;\n    rtl_ecp_gen_key = 0x101273f1;\n    rtl_ecp_check_pub_priv = 0x10127419;\n    rtl_ecp_group_load = 0x10128519;\n    rtl_hmac_drbg_init = 0x1012893d;\n    rtl_hmac_drbg_update = 0x10128949;\n    rtl_hmac_drbg_seed_buf = 0x101289e5;\n    rtl_hmac_drbg_reseed = 0x10128a35;\n    rtl_hmac_drbg_seed = 0x10128aad;\n    rtl_hmac_drbg_set_prediction_resistance = 0x10128b1d;\n    rtl_hmac_drbg_set_entropy_len = 0x10128b21;\n    rtl_hmac_drbg_set_reseed_interval = 0x10128b25;\n    rtl_hmac_drbg_random_with_add = 0x10128b29;\n    rtl_hmac_drbg_random = 0x10128bdd;\n    rtl_hmac_drbg_free = 0x10128bed;\n    rtl_md_list = 0x10128c09;\n    rtl_md_info_from_string = 0x10128c11;\n    rtl_md_info_from_type = 0x10128ca9;\n    rtl_md_init = 0x10128ced;\n    rtl_md_free = 0x10128cf9;\n    rtl_md_clone = 0x10128d45;\n    rtl_md_setup = 0x10128d6d;\n    rtl_md_init_ctx = 0x10128db5;\n    rtl_md_starts = 0x10128dbb;\n    rtl_md_update = 0x10128dd5;\n    rtl_md_finish = 0x10128df1;\n    rtl_md = 0x10128e0d;\n    rtl_md_hmac_starts = 0x10128e29;\n    rtl_md_hmac_update = 0x10128eed;\n    rtl_md_hmac_finish = 0x10128f0d;\n    rtl_md_hmac_reset = 0x10128f65;\n    rtl_md_hmac = 0x10128f91;\n    rtl_md_process = 0x10128fe5;\n    rtl_md_get_size = 0x10129001;\n    rtl_md_get_type = 0x10129009;\n    rtl_md_get_name = 0x1012900f;\n    rtl_md5_init = 0x1012917d;\n    rtl_md5_free = 0x10129189;\n    rtl_md5_clone = 0x1012919d;\n    rtl_md5_starts = 0x101291a9;\n    rtl_md5_process = 0x101291d5;\n    rtl_md5_update = 0x101298dd;\n    rtl_md5_finish = 0x101298e3;\n    rtl_md5 = 0x10129995;\n    rtl_oid_get_attr_short_name = 0x101299fd;\n    rtl_oid_get_x509_ext_type = 0x10129a35;\n    rtl_oid_get_extended_key_usage = 0x10129a6d;\n    rtl_oid_get_sig_alg_desc = 0x10129aa5;\n    rtl_oid_get_sig_alg = 0x10129abd;\n    rtl_oid_get_oid_by_sig_alg = 0x10129adb;\n    rtl_oid_get_pk_alg = 0x10129b09;\n    rtl_oid_get_oid_by_pk_alg = 0x10129b41;\n    rtl_oid_get_ec_grp = 0x10129b69;\n    rtl_oid_get_oid_by_ec_grp = 0x10129ba1;\n    rtl_oid_get_cipher_alg = 0x10129bc9;\n    rtl_oid_get_md_alg = 0x10129c01;\n    rtl_oid_get_oid_by_md = 0x10129c39;\n    rtl_oid_get_pkcs12_pbe_alg = 0x10129c61;\n    rtl_pem_init = 0x10129e5f;\n    rtl_pem_read_buffer = 0x10129e6d;\n    rtl_pem_free = 0x1012a161;\n    rtl_pem_write_buffer = 0x1012a185;\n    rtl_pk_init = 0x1012a279;\n    rtl_pk_free = 0x1012a283;\n    rtl_pk_info_from_type = 0x1012a2a5;\n    rtl_pk_setup = 0x1012a2d9;\n    rtl_pk_setup_rsa_alt = 0x1012a305;\n    rtl_pk_can_do = 0x1012a351;\n    rtl_pk_verify = 0x1012a361;\n    rtl_pk_sign = 0x1012a3bd;\n    rtl_pk_decrypt = 0x1012a425;\n    rtl_pk_encrypt = 0x1012a451;\n    rtl_pk_check_pair = 0x1012a47d;\n    rtl_pk_get_bitlen = 0x1012a4bd;\n    rtl_pk_verify_ext = 0x1012a4cd;\n    rtl_pk_debug = 0x1012a585;\n    rtl_pk_get_name = 0x1012a5a9;\n    rtl_pk_get_type = 0x1012a5bd;\n    rtl_pk_write_pubkey = 0x1012aa23;\n    rtl_pk_write_pubkey_der = 0x1012aaad;\n    rtl_pk_write_key_der = 0x1012ab7d;\n    rtl_pk_write_pubkey_pem = 0x1012ad79;\n    rtl_pk_write_key_pem = 0x1012adc1;\n    rtl_rsa_init = 0x1012aecd;\n    rtl_rsa_set_padding = 0x1012aeed;\n    rtl_rsa_check_pubkey = 0x1012aef7;\n    rtl_rsa_check_privkey = 0x1012af4d;\n    rtl_rsa_check_pub_priv = 0x1012b169;\n    rtl_rsa_public = 0x1012b1a1;\n    rtl_rsa_private = 0x1012b20f;\n    rtl_rsa_rsaes_oaep_encrypt = 0x1012b465;\n    rtl_rsa_rsaes_pkcs1_v15_encrypt = 0x1012b58d;\n    rtl_rsa_pkcs1_encrypt = 0x1012b675;\n    rtl_rsa_rsaes_oaep_decrypt = 0x1012b6b5;\n    rtl_rsa_rsaes_pkcs1_v15_decrypt = 0x1012b821;\n    rtl_rsa_pkcs1_decrypt = 0x1012b92d;\n    rtl_rsa_rsassa_pss_sign = 0x1012b975;\n    rtl_rsa_rsassa_pkcs1_v15_sign = 0x1012badd;\n    rtl_rsa_pkcs1_sign = 0x1012bc85;\n    rtl_rsa_rsassa_pss_verify_ext = 0x1012bcc9;\n    rtl_rsa_rsassa_pss_verify = 0x1012be75;\n    rtl_rsa_rsassa_pkcs1_v15_verify = 0x1012bea7;\n    rtl_rsa_pkcs1_verify = 0x1012c009;\n    rtl_rsa_free = 0x1012c04d;\n    rtl_rsa_gen_key = 0x1012c0bb;\n    rtl_rsa_copy = 0x1012c261;\n    rtl_sha1_init = 0x1012c365;\n    rtl_sha1_free = 0x1012c371;\n    rtl_sha1_clone = 0x1012c385;\n    rtl_sha1_starts = 0x1012c391;\n    rtl_sha1_process = 0x1012c3c5;\n    rtl_sha1_update = 0x1012d391;\n    rtl_sha1_finish = 0x1012d397;\n    rtl_sha1 = 0x1012d45d;\n    rtl_sha256_init = 0x1012d491;\n    rtl_sha256_free = 0x1012d49d;\n    rtl_sha256_clone = 0x1012d4b1;\n    rtl_sha256_starts = 0x1012d4bd;\n    rtl_sha256_process = 0x1012d55d;\n    rtl_sha256_update = 0x1012dc89;\n    rtl_sha256_finish = 0x1012dc8f;\n    rtl_sha256 = 0x1012dd91;\n    rtl_sha512_init = 0x1012ddc9;\n    rtl_sha512_free = 0x1012ddd5;\n    rtl_sha512_clone = 0x1012dde9;\n    rtl_sha512_starts = 0x1012ddf5;\n    rtl_sha512_process = 0x1012df29;\n    rtl_sha512_update = 0x1012ec7d;\n    rtl_sha512_finish = 0x1012ec83;\n    rtl_sha512 = 0x1012eeb9;\n    __rom_entry_ns_start__ = 0x101c0000;\n    rom_sec_call_ns_entry = 0x101c0000;\n    __rom_entry_ns_end__ = 0x101c0008;\n    SPIC_CALIB_PATTERN = 0x101c0008;\n    PORT_AB = 0x101c0024;\n    armBitRevIndexTable1024 = 0x101c004c;\n    twiddleCoef_1024 = 0x101c0e5c;\n    rtl_sha512_info = 0x101ce344;\n    rtl_sha384_info = 0x101ce374;\n    rtl_sha256_info = 0x101ce3a4;\n    rtl_sha224_info = 0x101ce3d4;\n    rtl_sha1_info = 0x101ce404;\n    rtl_md5_info = 0x101ce434;\n    rtl_rsa_alt_info = 0x101cea78;\n    rtl_ecdsa_info = 0x101ceaa8;\n    rtl_eckeydh_info = 0x101cead8;\n    rtl_eckey_info = 0x101ceb08;\n    rtl_rsa_info = 0x101ceb38;\n    __rom_bss_end_s__ = 0x200f9000;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4aa29552576a4bae7ce7b2b468aec6da6a6a531d","subject":"Wrong mapping","message":"Wrong mapping\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/src\/gcc_arm_flash.ld","new_file":"ARM\/src\/gcc_arm_flash.ld","new_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t\n\t\t\/* At addr zero is the stack pointer *\/\n\t\tLONG(__StackTop);\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector) - SIZEOF(.Version);\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\tFILL(0xff)\n\t\t. = 0x10;\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : \n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n   \t__data_size__ = SIZEOF(.data);\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","old_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t\n\t\t\/* At addr zero is the stack pointer *\/\n\t\tLONG(__StackTop);\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector) - SIZEOF(.Version);\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec 0x400 : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\tFILL(0xff)\n\t\t. = 0x10;\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : \n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n   \t__data_size__ = SIZEOF(.data);\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"aac634404c5d78db835257b7102b9895c0149452","subject":"linker: explicitly place COMMON","message":"linker: explicitly place COMMON\n\nOtherwise it ends up in the malloc arena, which is pretty bad.\n","repos":"abrasive\/satisfier,abrasive\/satisfier,abrasive\/satisfier","old_file":"ldscript.ld","new_file":"ldscript.ld","new_contents":"\/*  Copyright (c) 2015 James Laird-Wah\n *\n * This Source Code Form is subject to the terms of the Mozilla Public\n * License, v. 2.0. If a copy of the MPL was not distributed with this\n * file, you can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/. *\/\n\nOUTPUT_FORMAT(\"elf32-sh\", \"elf32-sh\",\n          \"elf32-sh\")\nOUTPUT_ARCH(sh)\nENTRY(_start)\n\nMEMORY {\n    \/* all of low Work RAM is free for our use, woo *\/\n    work_low (rwx) : org = 0x200000, l = 0x100000\n}\n\nSECTIONS {\n    .ram : {\n        __load_start = .;\n        *(.start);\n        *ashiftrt.o(.text); \/* necessary for the BIOS load *\/\n\n        *(.text);\n        *(.rodata);\n        *(.rodata.*);\n        *(.data);\n        __load_end = .;\n        *(.bss);\n        *(COMMON);\n        __bss_end = .;\n        . = ALIGN(4);\n        __free_ram_begin = .;\n        __free_ram_end = __load_start + 0x100000;\n    } >work_low\n}\n","old_contents":"\/*  Copyright (c) 2015 James Laird-Wah\n *\n * This Source Code Form is subject to the terms of the Mozilla Public\n * License, v. 2.0. If a copy of the MPL was not distributed with this\n * file, you can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/. *\/\n\nOUTPUT_FORMAT(\"elf32-sh\", \"elf32-sh\",\n          \"elf32-sh\")\nOUTPUT_ARCH(sh)\nENTRY(_start)\n\nMEMORY {\n    \/* all of low Work RAM is free for our use, woo *\/\n    work_low (rwx) : org = 0x200000, l = 0x100000\n}\n\nSECTIONS {\n    .ram : {\n        __load_start = .;\n        *(.start);\n        *ashiftrt.o(.text); \/* necessary for the BIOS load *\/\n\n        *(.text);\n        *(.rodata);\n        *(.rodata.*);\n        *(.data);\n        __load_end = .;\n        *(.bss);\n        __bss_end = .;\n        . = ALIGN(4);\n        __free_ram_begin = .;\n        __free_ram_end = __load_start + 0x100000;\n    } >work_low\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"060209240ba3a7fcf6338221417e363c10d6e147","subject":"esp8266: Put new profile code in iROM.","message":"esp8266: Put new profile code in iROM.\n","repos":"tobbad\/micropython,tobbad\/micropython,selste\/micropython,kerneltask\/micropython,pozetroninc\/micropython,henriknelson\/micropython,trezor\/micropython,bvernoux\/micropython,henriknelson\/micropython,bvernoux\/micropython,MrSurly\/micropython,bvernoux\/micropython,trezor\/micropython,adafruit\/circuitpython,pozetroninc\/micropython,bvernoux\/micropython,trezor\/micropython,pramasoul\/micropython,pramasoul\/micropython,henriknelson\/micropython,MrSurly\/micropython,trezor\/micropython,kerneltask\/micropython,bvernoux\/micropython,selste\/micropython,henriknelson\/micropython,kerneltask\/micropython,kerneltask\/micropython,trezor\/micropython,pramasoul\/micropython,MrSurly\/micropython,selste\/micropython,adafruit\/circuitpython,MrSurly\/micropython,tobbad\/micropython,tobbad\/micropython,pozetroninc\/micropython,selste\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,pramasoul\/micropython,pozetroninc\/micropython,adafruit\/circuitpython,MrSurly\/micropython,henriknelson\/micropython,tobbad\/micropython,selste\/micropython,pozetroninc\/micropython,kerneltask\/micropython,pramasoul\/micropython","old_file":"ports\/esp8266\/esp8266_common.ld","new_file":"ports\/esp8266\/esp8266_common.ld","new_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* Vendor SDK in v2.1.0-7-gb8fd588 started to build these with\n           -ffunction-sections -fdata-sections, and require routing to\n           irom via linker:\n           https:\/\/github.com\/espressif\/ESP8266_NONOS_SDK\/commit\/b8fd588a33f0319dc135523b51655e97b483b205\n         *\/\n\n        *libcrypto.a:(.literal.* .text.*)\n        *libnet80211.a:(.literal.* .text.*)\n        *libwpa.a:(.literal.* .text.*)\n        *libwpa2.a:(.literal.* .text.*)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/profile*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *lib\/axtls\/*.o(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/printf.o*(.literal*, .text*)\n        *lib\/utils\/sys_stdio_mphal.o*(.literal*, .text*)\n        *lib\/utils\/pyexec.o*(.literal*, .text*)\n        *lib\/utils\/stdout_helpers.o*(.literal*, .text*)\n        *lib\/utils\/interrupt_char.o*(.literal.mp_hal_set_interrupt_char, .text.mp_hal_set_interrupt_char)\n        *drivers\/bus\/*.o(.literal* .text*)\n\n        build\/main.o(.literal* .text*)\n        *fatfs_port.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* Vendor SDK in v2.1.0-7-gb8fd588 started to build these with\n           -ffunction-sections -fdata-sections, and require routing to\n           irom via linker:\n           https:\/\/github.com\/espressif\/ESP8266_NONOS_SDK\/commit\/b8fd588a33f0319dc135523b51655e97b483b205\n         *\/\n\n        *libcrypto.a:(.literal.* .text.*)\n        *libnet80211.a:(.literal.* .text.*)\n        *libwpa.a:(.literal.* .text.*)\n        *libwpa2.a:(.literal.* .text.*)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *lib\/axtls\/*.o(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/printf.o*(.literal*, .text*)\n        *lib\/utils\/sys_stdio_mphal.o*(.literal*, .text*)\n        *lib\/utils\/pyexec.o*(.literal*, .text*)\n        *lib\/utils\/stdout_helpers.o*(.literal*, .text*)\n        *lib\/utils\/interrupt_char.o*(.literal.mp_hal_set_interrupt_char, .text.mp_hal_set_interrupt_char)\n        *drivers\/bus\/*.o(.literal* .text*)\n\n        build\/main.o(.literal* .text*)\n        *fatfs_port.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4982a3ad323b2caa9cac16a148ee695c4a58d2dd","subject":"esp8266\/esp8266_common.ld: Put .text of more libs into .irom0.text .","message":"esp8266\/esp8266_common.ld: Put .text of more libs into .irom0.text .\n\nRecent vendor SDKs ship libs with code in .text section, which previously\nwas going into .irom0.text. Adjust the linker script to route these\nsections back to iROM (follows upstream change).\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython","old_file":"ports\/esp8266\/esp8266_common.ld","new_file":"ports\/esp8266\/esp8266_common.ld","new_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* Vendor SDK in v2.1.0-7-gb8fd588 started to build these with\n           -ffunction-sections -fdata-sections, and require routing to\n           irom via linker:\n           https:\/\/github.com\/espressif\/ESP8266_NONOS_SDK\/commit\/b8fd588a33f0319dc135523b51655e97b483b205\n         *\/\n\n        *libcrypto.a:(.literal.* .text.*)\n        *libnet80211.a:(.literal.* .text.*)\n        *libwpa.a:(.literal.* .text.*)\n        *libwpa2.a:(.literal.* .text.*)\n\n        \/* we put some specific text in this section *\/\n\n        *common-hal\/*.o*(.literal* .text*)\n        *shared-bindings\/*.o*(.literal* .text*)\n        *shared-module\/*.o*(.literal* .text*)\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        build\/main.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266, common sections and symbols *\/\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\n_firmware_size = ORIGIN(irom0_0_seg) + LENGTH(irom0_0_seg) - 0x40200000;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *common-hal\/*.o*(.literal* .text*)\n        *shared-bindings\/*.o*(.literal* .text*)\n        *shared-module\/*.o*(.literal* .text*)\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/persistentcode*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/reader*.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scheduler.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/oofatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        build\/main.o(.literal* .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *machine_pin.o(.literal*, .text*)\n        *machine_pwm.o(.literal*, .text*)\n        *machine_rtc.o(.literal*, .text*)\n        *machine_adc.o(.literal*, .text*)\n        *machine_uart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachine.o(.literal*, .text*)\n        *machine_wdt.o(.literal*, .text*)\n        *machine_spi.o(.literal*, .text*)\n        *machine_hspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .iram0.literal .iram0.text .iram0.text.*.literal .iram0.text.*)\n        *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0d451969c381e5231a56a04630d3d3e26b269b6a","subject":"cpu\/esp32: place newlib syscalls in IRAM","message":"cpu\/esp32: place newlib syscalls in IRAM\n\n","repos":"yogo1212\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,basilfx\/RIOT,ant9000\/RIOT,smlng\/RIOT,miri64\/RIOT,yogo1212\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,smlng\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,authmillenon\/RIOT,smlng\/RIOT,basilfx\/RIOT,smlng\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,smlng\/RIOT,miri64\/RIOT,kaspar030\/RIOT,miri64\/RIOT,basilfx\/RIOT,basilfx\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,OlegHahm\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,OTAkeys\/RIOT","old_file":"cpu\/esp32\/ld\/esp32.common.ld","new_file":"cpu\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *littlefs.a:*(.literal .text .literal.* .text.*)\n    *littlefs2.a:*(.literal .text .literal.* .text.*)\n    *newlib_syscalls_default.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *syscalls.o(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *littlefs.a:*(.literal .text .literal.* .text.*)\n    *littlefs2.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"606ad8a05d349df43d3bc3c56326e427a72b6a13","subject":"lds: update the file size","message":"lds: update the file size\n\nMake it co-work with arm trust firmware.\n\nSigned-off-by: Haojian Zhuang <979139d45d262f0480136b0da512e0afa0fe79d3@gmail.com>\n","repos":"96boards-hikey\/l-loader,96boards-hikey\/l-loader","old_file":"l-loader.lds","new_file":"l-loader.lds","new_contents":"\/*\n * Copyright (c) 2014 Linaro Ltd.\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS\n{\n\t. = 0xf9800800;\n\tLLOADER_START = .;\n\n\t.text :\n\t{\n\t\t*(.text)\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN(4):\n\t{\n\t\t*(.data)\n\t}\n\n\t. = ALIGN(4);\n\n\t.bss ALIGN(4):\n\t{\n\t\t*(.bss)\n\t}\n\n\tLLOADER_BL1_BIN = 0xf9802000;\n\n\t\/* bl1.bin (48KB + 2KB - 8KB) *\/\n\n\tLLOADER_END = 0xf980c800;\n}\n","old_contents":"\/*\n * Copyright (c) 2014 Linaro Ltd.\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS\n{\n\t. = 0xf9800800;\n\tLLOADER_START = .;\n\n\t.text :\n\t{\n\t\t*(.text)\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN(4):\n\t{\n\t\t*(.data)\n\t}\n\n\t. = ALIGN(4);\n\n\t.bss ALIGN(4):\n\t{\n\t\t*(.bss)\n\t}\n\n\tLLOADER_BL1_BIN = 0xf9802000;\n\n\t\/* bl1.bin (48KB - 8KB) *\/\n\n\tLLOADER_END = 0xf980c000;\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"320e3bfca5f062418bdb209e43c2cd6044a51446","subject":"kern_end == size?","message":"kern_end == size?\n","repos":"ManyThreads\/mythos,ManyThreads\/mythos","old_file":"kernel\/boot\/kernel-amd64-ihk\/boot\/boot.ld","new_file":"kernel\/boot\/kernel-amd64-ihk\/boot\/boot.ld","new_contents":"\/* MIT License -- MyThOS: The Many-Threads Operating System\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without\n * restriction, including without limitation the rights to use, copy,\n * modify, merge, publish, distribute, sublicense, and\/or sell copies\n * of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\n * Copyright 2014 Randolf Rotta, Maik Kr\u00fcger, and contributors, BTU Cottbus-Senftenberg\n *\/\n#include \"boot\/memory-layout.h\"\n\nENTRY(_start_ihk_mythos_)\n\n\/** ELF programm header for the loader.\n *\n * See ftp:\/\/ftp.gnu.org\/old-gnu\/Manuals\/ld-2.9.1\/html_node\/ld_23.html\n * and the ELF ABI defines how this shall be interpreted.\n *\n * Two sections init and kern are defined with type PT_LOAD.\n * PT_LOAD indicates that this segment should be loaded from the file.\n * The sections below are assigned to segments by \":name\" at the\n * end of the section description.\n *\/\nPHDRS\n{\n    kern PT_LOAD;\n    data PT_LOAD;\n}\n\nSECTIONS\n{\n    \/* All following sections will be placed into the upper half\n    kernel address range. Thus, the Virtual Memory Address VMA will be\n    large. But the Load Memory Address LMA has to be in physical addresses still. *\/\n    . = VIRT_ADDR;\n    .text : {\n        *(.text.hot .text.hot.*)\n        *(\".text\" \".text$\" .text .text.* .gnu.linkonce.t.*)\n    } : kern\n\n    .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n    .eh_frame : { *(.eh_frame) }\n    .fixup : { FIXUP_START = .; *(.fixup); FIXUP_END = .; }\n\n    .init_array : {\n      CTORS_START = .;\n      KEEP(*(SORT(.init_array.*)))\n      KEEP(*(.init_array))\n      KEEP(*(SORT(.ctors.*)))\n      KEEP(*(.ctors))\n      CTORS_END = .;\n    }\n\n    . = ALIGN(2M); \/* page aligned *\/\n    \/*PROVIDE (KERN_ROEND = . - VIRT_ADDR);*\/\n\n    .data : {\n      *(.data .data.* .gnu.linkonce.d.*)\n      . = ALIGN(64); \/* cache line aligned *\/\n      CLM_ADDR = .;\n      *(SORT_BY_ALIGNMENT(.kernel_clm.hot))\n      *(SORT_BY_ALIGNMENT(.kernel_clm))\n      . = ALIGN(64); \/* cache line aligned *\/\n      CLM_BLOCKEND = .;\n    } : data\n\n    .bss : {\n      . += MYTHOS_MAX_THREADS*(CLM_BLOCKEND - CLM_ADDR);\n      CLM_END = .;\n      *(.bss .bss.* .gnu.linkonce.b.*)\n    }\n\n    . = ALIGN(4096); \/* page aligned *\/\n\tPROVIDE (VIRT_END = .);\n    . = ALIGN(2M); \/* page aligned *\/\n\tPROVIDE (KERN_END = . - VIRT_ADDR); \/* the SIZE (not physical end of the upper half stuff) *\/\n\n    \/DISCARD\/ :\n    {\n        *(.note.GNU-stack)\n        *(.comment*)\n    }\n}\n","old_contents":"\/* MIT License -- MyThOS: The Many-Threads Operating System\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without\n * restriction, including without limitation the rights to use, copy,\n * modify, merge, publish, distribute, sublicense, and\/or sell copies\n * of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\n * Copyright 2014 Randolf Rotta, Maik Kr\u00fcger, and contributors, BTU Cottbus-Senftenberg\n *\/\n#include \"boot\/memory-layout.h\"\n\nENTRY(_start_ihk_mythos_)\n\n\/** ELF programm header for the loader.\n *\n * See ftp:\/\/ftp.gnu.org\/old-gnu\/Manuals\/ld-2.9.1\/html_node\/ld_23.html\n * and the ELF ABI defines how this shall be interpreted.\n *\n * Two sections init and kern are defined with type PT_LOAD.\n * PT_LOAD indicates that this segment should be loaded from the file.\n * The sections below are assigned to segments by \":name\" at the\n * end of the section description.\n *\/\nPHDRS\n{\n    kern PT_LOAD;\n    data PT_LOAD;\n}\n\nSECTIONS\n{\n    \/* All following sections will be placed into the upper half\n    kernel address range. Thus, the Virtual Memory Address VMA will be\n    large. But the Load Memory Address LMA has to be in physical addresses still. *\/\n    . = VIRT_ADDR;\n    .text : {\n        *(.text.hot .text.hot.*)\n        *(\".text\" \".text$\" .text .text.* .gnu.linkonce.t.*)\n    } : kern\n\n    .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n    .eh_frame : { *(.eh_frame) }\n    .fixup : { FIXUP_START = .; *(.fixup); FIXUP_END = .; }\n\n    .init_array : {\n      CTORS_START = .;\n      KEEP(*(SORT(.init_array.*)))\n      KEEP(*(.init_array))\n      KEEP(*(SORT(.ctors.*)))\n      KEEP(*(.ctors))\n      CTORS_END = .;\n    }\n\n    . = ALIGN(2M); \/* page aligned *\/\n    \/*PROVIDE (KERN_ROEND = . - VIRT_ADDR);*\/\n\n    .data : {\n      *(.data .data.* .gnu.linkonce.d.*)\n      . = ALIGN(64); \/* cache line aligned *\/\n      CLM_ADDR = .;\n      *(SORT_BY_ALIGNMENT(.kernel_clm.hot))\n      *(SORT_BY_ALIGNMENT(.kernel_clm))\n      . = ALIGN(64); \/* cache line aligned *\/\n      CLM_BLOCKEND = .;\n    } : data\n\n    .bss : {\n      . += MYTHOS_MAX_THREADS*(CLM_BLOCKEND - CLM_ADDR);\n      CLM_END = .;\n      *(.bss .bss.* .gnu.linkonce.b.*)\n    }\n\n    . = ALIGN(4096); \/* page aligned *\/\n\tPROVIDE (VIRT_END = .);\n    . = ALIGN(2M); \/* page aligned *\/\n\tPROVIDE (KERN_END = . - VIRT_ADDR); \/* the physical end of the upper half stuff *\/\n\n    \/DISCARD\/ :\n    {\n        *(.note.GNU-stack)\n        *(.comment*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c1dc4a6f6104817f88cfeb316fbccd6c3bd3ceef","subject":"riscv: linker: fix __rom_region_end in non-XIP system","message":"riscv: linker: fix __rom_region_end in non-XIP system\n\nIn non-XIP system, because ROMABLE_REGION == RAMABLE_REGION, setting\n__rom_region_size\/end symbol at linker script end will mistakely\ncontain RAMABLE_REGION in it.\n\nMove __rom_region_end symbol to end of common ROMABLE_REGION (text\nand rodata) instead in non-XIP system.\n\nSigned-off-by: Jim Shu <1635390bb889c4cdee38f53a57b0915ac07d9bd9@andestech.com>\n","repos":"zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"801dd119c23f58dcb6ac05626581f2cf8d60bced","subject":"change linker script for S110 7.0.0-3-alpha size","message":"change linker script for S110 7.0.0-3-alpha size\n","repos":"jf87\/nrf51-pure-gcc-setup","old_file":"template\/gcc_nrf51_s110.ld","new_file":"template\/gcc_nrf51_s110.ld","new_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x15000, LENGTH = 0x2B000 \/* 84 kB is taken by S110, 172 kB for app. *\/\n  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 \/* 8 kB is taken by S110,8 kB for app. *\/\n}\nINCLUDE \"gcc_nrf51_common.ld\"\n","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x14000, LENGTH = 0x2C000 \/* 80 kB is taken by S110, 176 kB for app. *\/\n  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 \/* 8 kB is taken by S110,8 kB for app. *\/\n}\nINCLUDE \"gcc_nrf51_common.ld\"\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"b47931978feffc7739fab7261b81caed1622fc9d","subject":"esp8266: Update the linker script","message":"esp8266: Update the linker script\n\nMoved modesp.o to flash and increased size of the irom0_0_seg segment. The new\nvalue was taken from NodeMCU linker script.\n","repos":"cwyark\/micropython,deshipu\/micropython,alex-march\/micropython,xuxiaoxin\/micropython,tralamazza\/micropython,emfcamp\/micropython,alex-robbins\/micropython,praemdonck\/micropython,drrk\/micropython,suda\/micropython,martinribelotta\/micropython,dinau\/micropython,dhylands\/micropython,jmarcelino\/pycom-micropython,ericsnowcurrently\/micropython,ahotam\/micropython,noahwilliamsson\/micropython,pramasoul\/micropython,xyb\/micropython,jimkmc\/micropython,ernesto-g\/micropython,ryannathans\/micropython,heisewangluo\/micropython,jimkmc\/micropython,tuc-osg\/micropython,mhoffma\/micropython,ahotam\/micropython,pozetroninc\/micropython,EcmaXp\/micropython,adafruit\/circuitpython,adamkh\/micropython,rubencabrera\/micropython,heisewangluo\/micropython,cnoviello\/micropython,xuxiaoxin\/micropython,emfcamp\/micropython,pfalcon\/micropython,noahchense\/micropython,cnoviello\/micropython,mhoffma\/micropython,noahwilliamsson\/micropython,AriZuu\/micropython,mpalomer\/micropython,noahchense\/micropython,mianos\/micropython,swegener\/micropython,MrSurly\/micropython,micropython\/micropython-esp32,HenrikSolver\/micropython,dinau\/micropython,Peetz0r\/micropython-esp32,rubencabrera\/micropython,heisewangluo\/micropython,vriera\/micropython,dinau\/micropython,mpalomer\/micropython,supergis\/micropython,jimkmc\/micropython,TDAbboud\/micropython,utopiaprince\/micropython,dxxb\/micropython,henriknelson\/micropython,jmarcelino\/pycom-micropython,selste\/micropython,kostyll\/micropython,dxxb\/micropython,utopiaprince\/micropython,adafruit\/circuitpython,mhoffma\/micropython,toolmacher\/micropython,pozetroninc\/micropython,tobbad\/micropython,blmorris\/micropython,ruffy91\/micropython,trezor\/micropython,blmorris\/micropython,Timmenem\/micropython,stonegithubs\/micropython,ganshun666\/micropython,praemdonck\/micropython,TDAbboud\/micropython,xuxiaoxin\/micropython,infinnovation\/micropython,bvernoux\/micropython,torwag\/micropython,slzatz\/micropython,vriera\/micropython,danicampora\/micropython,lowRISC\/micropython,torwag\/micropython,tdautc19841202\/micropython,firstval\/micropython,lbattraw\/micropython,dhylands\/micropython,HenrikSolver\/micropython,vriera\/micropython,vitiral\/micropython,micropython\/micropython-esp32,tobbad\/micropython,galenhz\/micropython,micropython\/micropython-esp32,feilongfl\/micropython,neilh10\/micropython,PappaPeppar\/micropython,pramasoul\/micropython,tobbad\/micropython,emfcamp\/micropython,chrisdearman\/micropython,turbinenreiter\/micropython,feilongfl\/micropython,vitiral\/micropython,puuu\/micropython,vitiral\/micropython,Timmenem\/micropython,suda\/micropython,AriZuu\/micropython,hiway\/micropython,kerneltask\/micropython,jimkmc\/micropython,tralamazza\/micropython,neilh10\/micropython,hosaka\/micropython,adafruit\/micropython,slzatz\/micropython,ryannathans\/micropython,infinnovation\/micropython,adamkh\/micropython,EcmaXp\/micropython,neilh10\/micropython,rubencabrera\/micropython,ernesto-g\/micropython,ganshun666\/micropython,bvernoux\/micropython,tuc-osg\/micropython,blmorris\/micropython,pramasoul\/micropython,pozetroninc\/micropython,supergis\/micropython,cnoviello\/micropython,cloudformdesign\/micropython,pfalcon\/micropython,Timmenem\/micropython,praemdonck\/micropython,jlillest\/micropython,deshipu\/micropython,jmarcelino\/pycom-micropython,kostyll\/micropython,ruffy91\/micropython,adafruit\/circuitpython,xhat\/micropython,mgyenik\/micropython,AriZuu\/micropython,dhylands\/micropython,hiway\/micropython,noahchense\/micropython,tdautc19841202\/micropython,alex-robbins\/micropython,omtinez\/micropython,dinau\/micropython,redbear\/micropython,mpalomer\/micropython,vriera\/micropython,mianos\/micropython,lowRISC\/micropython,henriknelson\/micropython,micropython\/micropython-esp32,ganshun666\/micropython,adafruit\/circuitpython,cwyark\/micropython,HenrikSolver\/micropython,AriZuu\/micropython,chrisdearman\/micropython,infinnovation\/micropython,omtinez\/micropython,misterdanb\/micropython,MrSurly\/micropython,tuc-osg\/micropython,oopy\/micropython,deshipu\/micropython,oopy\/micropython,blazewicz\/micropython,MrSurly\/micropython-esp32,matthewelse\/micropython,alex-march\/micropython,dxxb\/micropython,pramasoul\/micropython,galenhz\/micropython,puuu\/micropython,xyb\/micropython,pozetroninc\/micropython,ganshun666\/micropython,cloudformdesign\/micropython,feilongfl\/micropython,mianos\/micropython,utopiaprince\/micropython,puuu\/micropython,SHA2017-badge\/micropython-esp32,TDAbboud\/micropython,hiway\/micropython,jlillest\/micropython,PappaPeppar\/micropython,hiway\/micropython,danicampora\/micropython,blazewicz\/micropython,xhat\/micropython,ceramos\/micropython,SHA2017-badge\/micropython-esp32,adafruit\/micropython,galenhz\/micropython,lowRISC\/micropython,toolmacher\/micropython,tobbad\/micropython,MrSurly\/micropython,dmazzella\/micropython,skybird6672\/micropython,kerneltask\/micropython,hosaka\/micropython,noahchense\/micropython,stonegithubs\/micropython,drrk\/micropython,ericsnowcurrently\/micropython,henriknelson\/micropython,ruffy91\/micropython,ahotam\/micropython,galenhz\/micropython,pozetroninc\/micropython,micropython\/micropython-esp32,torwag\/micropython,heisewangluo\/micropython,ChuckM\/micropython,oopy\/micropython,swegener\/micropython,skybird6672\/micropython,xhat\/micropython,Peetz0r\/micropython-esp32,cloudformdesign\/micropython,MrSurly\/micropython,mgyenik\/micropython,Peetz0r\/micropython-esp32,trezor\/micropython,feilongfl\/micropython,praemdonck\/micropython,ernesto-g\/micropython,SHA2017-badge\/micropython-esp32,cwyark\/micropython,stonegithubs\/micropython,adamkh\/micropython,henriknelson\/micropython,utopiaprince\/micropython,ceramos\/micropython,lowRISC\/micropython,rubencabrera\/micropython,infinnovation\/micropython,turbinenreiter\/micropython,xyb\/micropython,Peetz0r\/micropython-esp32,deshipu\/micropython,puuu\/micropython,mgyenik\/micropython,Peetz0r\/micropython-esp32,ahotam\/micropython,lowRISC\/micropython,skybird6672\/micropython,omtinez\/micropython,kerneltask\/micropython,kostyll\/micropython,turbinenreiter\/micropython,matthewelse\/micropython,tobbad\/micropython,selste\/micropython,swegener\/micropython,bvernoux\/micropython,skybird6672\/micropython,lbattraw\/micropython,suda\/micropython,tralamazza\/micropython,orionrobots\/micropython,mpalomer\/micropython,utopiaprince\/micropython,alex-robbins\/micropython,turbinenreiter\/micropython,redbear\/micropython,toolmacher\/micropython,torwag\/micropython,ganshun666\/micropython,hiway\/micropython,SHA2017-badge\/micropython-esp32,ryannathans\/micropython,ryannathans\/micropython,selste\/micropython,mgyenik\/micropython,noahwilliamsson\/micropython,tdautc19841202\/micropython,chrisdearman\/micropython,omtinez\/micropython,jlillest\/micropython,mgyenik\/micropython,kerneltask\/micropython,stonegithubs\/micropython,tralamazza\/micropython,selste\/micropython,turbinenreiter\/micropython,TDAbboud\/micropython,vitiral\/micropython,hosaka\/micropython,HenrikSolver\/micropython,firstval\/micropython,xhat\/micropython,neilh10\/micropython,henriknelson\/micropython,deshipu\/micropython,orionrobots\/micropython,cnoviello\/micropython,ChuckM\/micropython,swegener\/micropython,bvernoux\/micropython,emfcamp\/micropython,pfalcon\/micropython,chrisdearman\/micropython,firstval\/micropython,hosaka\/micropython,swegener\/micropython,adafruit\/micropython,misterdanb\/micropython,dinau\/micropython,alex-march\/micropython,ceramos\/micropython,Timmenem\/micropython,MrSurly\/micropython-esp32,adamkh\/micropython,cloudformdesign\/micropython,orionrobots\/micropython,toolmacher\/micropython,cwyark\/micropython,danicampora\/micropython,EcmaXp\/micropython,ruffy91\/micropython,jlillest\/micropython,praemdonck\/micropython,pfalcon\/micropython,jmarcelino\/pycom-micropython,puuu\/micropython,tdautc19841202\/micropython,HenrikSolver\/micropython,slzatz\/micropython,slzatz\/micropython,ChuckM\/micropython,ryannathans\/micropython,hosaka\/micropython,xyb\/micropython,redbear\/micropython,pfalcon\/micropython,cwyark\/micropython,matthewelse\/micropython,lbattraw\/micropython,redbear\/micropython,mhoffma\/micropython,drrk\/micropython,blazewicz\/micropython,noahchense\/micropython,ericsnowcurrently\/micropython,kerneltask\/micropython,dhylands\/micropython,noahwilliamsson\/micropython,mhoffma\/micropython,tdautc19841202\/micropython,MrSurly\/micropython-esp32,ceramos\/micropython,mianos\/micropython,EcmaXp\/micropython,dmazzella\/micropython,bvernoux\/micropython,dxxb\/micropython,danicampora\/micropython,mianos\/micropython,supergis\/micropython,skybird6672\/micropython,adamkh\/micropython,trezor\/micropython,firstval\/micropython,jlillest\/micropython,dhylands\/micropython,kostyll\/micropython,trezor\/micropython,suda\/micropython,redbear\/micropython,misterdanb\/micropython,martinribelotta\/micropython,xuxiaoxin\/micropython,martinribelotta\/micropython,drrk\/micropython,AriZuu\/micropython,slzatz\/micropython,ernesto-g\/micropython,torwag\/micropython,PappaPeppar\/micropython,orionrobots\/micropython,EcmaXp\/micropython,adafruit\/micropython,matthewelse\/micropython,stonegithubs\/micropython,cnoviello\/micropython,adafruit\/circuitpython,SHA2017-badge\/micropython-esp32,martinribelotta\/micropython,martinribelotta\/micropython,blazewicz\/micropython,suda\/micropython,neilh10\/micropython,supergis\/micropython,dmazzella\/micropython,ruffy91\/micropython,tuc-osg\/micropython,noahwilliamsson\/micropython,ceramos\/micropython,vitiral\/micropython,oopy\/micropython,Timmenem\/micropython,mpalomer\/micropython,cloudformdesign\/micropython,chrisdearman\/micropython,blmorris\/micropython,drrk\/micropython,heisewangluo\/micropython,dxxb\/micropython,xuxiaoxin\/micropython,danicampora\/micropython,xyb\/micropython,toolmacher\/micropython,pramasoul\/micropython,galenhz\/micropython,MrSurly\/micropython-esp32,xhat\/micropython,blazewicz\/micropython,MrSurly\/micropython,firstval\/micropython,matthewelse\/micropython,infinnovation\/micropython,rubencabrera\/micropython,emfcamp\/micropython,ahotam\/micropython,ChuckM\/micropython,jimkmc\/micropython,selste\/micropython,feilongfl\/micropython,oopy\/micropython,alex-march\/micropython,orionrobots\/micropython,PappaPeppar\/micropython,misterdanb\/micropython,alex-march\/micropython,trezor\/micropython,ericsnowcurrently\/micropython,TDAbboud\/micropython,tuc-osg\/micropython,kostyll\/micropython,matthewelse\/micropython,lbattraw\/micropython,lbattraw\/micropython,ericsnowcurrently\/micropython,ernesto-g\/micropython,supergis\/micropython,adafruit\/micropython,alex-robbins\/micropython,blmorris\/micropython,alex-robbins\/micropython,ChuckM\/micropython,vriera\/micropython,omtinez\/micropython,jmarcelino\/pycom-micropython,MrSurly\/micropython-esp32,PappaPeppar\/micropython,adafruit\/circuitpython,misterdanb\/micropython,dmazzella\/micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n        *py\/*.o*(.literal* .text*)\n        *pyexec.o(.literal*, .text*)\n        *readline.o(.literal*, .text*)\n        *pybstdio.o(.literal*, .text*)\n        *modpyb.o(.literal*, .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *modesp.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *py\/*.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *py\/*.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *py\/*.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x40000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n        *py\/*.o*(.literal* .text*)\n        *pyexec.o(.literal*, .text*)\n        *readline.o(.literal*, .text*)\n        *pybstdio.o(.literal*, .text*)\n        *modpyb.o(.literal*, .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *py\/*.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *py\/*.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *py\/*.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"93dc7edead48e07d026dc4b6c1cceca893c3d1f5","subject":"Grow linker script irom section for 512KB flash chip","message":"Grow linker script irom section for 512KB flash chip\n\nNecessary to fit http_get_ssl example, newlib string functions are\nlarger than espressif SDK implementations.\n","repos":"kanflo\/esp-open-rtos,urx\/esp-open-rtos,DCoJA\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,someburner\/esp-rtos-tests,gpascualg\/esp-open-rtos,Angus71\/esp-open-rtos,ourairquality\/esp-open-rtos,DCoJA\/esp-open-rtos,kamejoko80\/esp-open-rtos,SuperHouse\/esp-open-rtos,sheinz\/esp-open-rtos,Zaltora\/esp-open-rtos,Zaltora\/esp-open-rtos,hawkhsieh\/esp-open-rtos,ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos,andree182\/esp-open-rtos,kanflo\/esp-open-rtos,someburner\/esp-rtos-tests,Angus71\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,sheinz\/esp-open-rtos,jaeh\/esp-open-rtos,UncleRus\/esp-open-rtos,Zaltora\/esp-open-rtos,gpascualg\/esp-open-rtos,DCoJA\/esp-open-rtos,urx\/esp-open-rtos,yesco\/esp-open-rtos,alainmaes\/esp-open-rtos,kanflo\/esp-open-rtos,foogod\/esp-open-rtos,gpascualg\/esp-open-rtos,someburner\/esp-rtos-tests,foogod\/esp-open-rtos,DCoJA\/esp-open-rtos,jaeh\/esp-open-rtos,urx\/esp-open-rtos,UncleRus\/esp-open-rtos,alainmaes\/esp-open-rtos,andree182\/esp-open-rtos,andree182\/esp-open-rtos,ourairquality\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,SuperHouse\/esp-open-rtos,UncleRus\/esp-open-rtos,alainmaes\/esp-open-rtos,mr-nice\/esp-open-rtos,mr-nice\/esp-open-rtos,mr-nice\/esp-open-rtos,foogod\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,Zaltora\/esp-open-rtos,UncleRus\/esp-open-rtos,UncleRus\/esp-open-rtos,mr-nice\/esp-open-rtos,SuperHouse\/esp-open-rtos,SuperHouse\/esp-open-rtos,Zaltora\/esp-open-rtos,kanflo\/esp-open-rtos,hawkhsieh\/esp-open-rtos,alainmaes\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,someburner\/esp-rtos-tests,andree182\/esp-open-rtos,urx\/esp-open-rtos,sheinz\/esp-open-rtos,UncleRus\/esp-open-rtos,Zaltora\/esp-open-rtos,SuperHouse\/esp-open-rtos,hawkhsieh\/esp-open-rtos,SuperHouse\/esp-open-rtos,hawkhsieh\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,urx\/esp-open-rtos,urx\/esp-open-rtos,kanflo\/esp-open-rtos,ourairquality\/esp-open-rtos,kamejoko80\/esp-open-rtos,ourairquality\/esp-open-rtos,sheinz\/esp-open-rtos,kanflo\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,chaisme\/esp8266_FreeRTOS,yesco\/esp-open-rtos","old_file":"ld\/eagle.app.v6.ld","new_file":"ld\/eagle.app.v6.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP .\n\n   Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one.\n*\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x8000\n  irom0_0_seg :                       \torg = 0x40240000, len = 0x7C000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(sdk__DebugExceptionVector)\nEXTERN(sdk__DoubleExceptionVector)\nEXTERN(sdk__KernelExceptionVector)\nEXTERN(sdk__NMIExceptionVector)\nEXTERN(sdk__UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n  \t_UserExceptionVector_literal_start = ABSOLUTE(.);\n  \t*(.UserExceptionVector.literal)\n  \t_UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .iram1.text iram1.literal .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n}\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP .\n\n   Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one.\n*\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x8000\n  irom0_0_seg :                       \torg = 0x40240000, len = 0x3C000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(sdk__DebugExceptionVector)\nEXTERN(sdk__DoubleExceptionVector)\nEXTERN(sdk__KernelExceptionVector)\nEXTERN(sdk__NMIExceptionVector)\nEXTERN(sdk__UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n  \t_UserExceptionVector_literal_start = ABSOLUTE(.);\n  \t*(.UserExceptionVector.literal)\n  \t_UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .iram1.text iram1.literal .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"52d3ae707d7ddb8cf2c06962923226221d281206","subject":"rp2\/memmap_mp.ld: Update for latest SDK.","message":"rp2\/memmap_mp.ld: Update for latest SDK.\n","repos":"bvernoux\/micropython,henriknelson\/micropython,henriknelson\/micropython,henriknelson\/micropython,henriknelson\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,henriknelson\/micropython,bvernoux\/micropython,bvernoux\/micropython,adafruit\/circuitpython,bvernoux\/micropython,adafruit\/circuitpython,bvernoux\/micropython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/rp2\/memmap_mp.ld","new_file":"ports\/rp2\/memmap_mp.ld","new_contents":"\/* Based on GCC ARM embedded samples.\n   Defines the following symbols for use by code:\n    __exidx_start\n    __exidx_end\n    __etext\n    __data_start__\n    __preinit_array_start\n    __preinit_array_end\n    __init_array_start\n    __init_array_end\n    __fini_array_start\n    __fini_array_end\n    __data_end__\n    __bss_start__\n    __bss_end__\n    __end__\n    end\n    __HeapLimit\n    __StackLimit\n    __StackTop\n    __stack (== StackTop)\n*\/\n\nMEMORY\n{\n    FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k\n    RAM(rwx) : ORIGIN =  0x20000000, LENGTH = 256k\n    SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k\n    SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k\n}\n\nENTRY(_entry_point)\n\nSECTIONS\n{\n    \/* Second stage bootloader is prepended to the image. It must be 256 bytes big\n       and checksummed. It is usually built by the boot_stage2 target\n       in the Raspberry Pi Pico SDK\n    *\/\n\n    .flash_begin : {\n        __flash_binary_start = .;\n    } > FLASH\n\n    .boot2 : {\n        __boot2_start__ = .;\n        KEEP (*(.boot2))\n        __boot2_end__ = .;\n    } > FLASH\n\n    ASSERT(__boot2_end__ - __boot2_start__ == 256,\n        \"ERROR: Pico second stage bootloader must be 256 bytes in size\")\n\n    \/* The second stage will always enter the image at the start of .text.\n       The debugger will use the ELF entry point, which is the _entry_point\n       symbol if present, otherwise defaults to start of .text.\n       This can be used to transfer control back to the bootrom on debugger\n       launches only, to perform proper flash setup.\n    *\/\n\n    .text : {\n        __logical_binary_start = .;\n        KEEP (*(.vectors))\n        KEEP (*(.binary_info_header))\n        __binary_info_header_end = .;\n        KEEP (*(.reset))\n        \/* TODO revisit this now memset\/memcpy\/float in ROM *\/\n        \/* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from\n         * FLASH ... we will include any thing excluded here in .data below by default *\/\n        *(.init)\n        \/* Change for MicroPython... excluse gc.c, parse.c, vm.c from flash *\/\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a: *lib_a-mem*.o *libm.a: *gc.c.obj *vm.c.obj *parse.c.obj) .text*)\n        *(.fini)\n        \/* Pull all c'tors into .text *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n        \/* Followed by destructors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n    .rodata : {\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*)\n        . = ALIGN(4);\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))\n        . = ALIGN(4);\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    \/* Machine inspectable binary information *\/\n    . = ALIGN(4);\n    __binary_info_start = .;\n    .binary_info :\n    {\n        KEEP(*(.binary_info.keep.*))\n        *(.binary_info.*)\n    } > FLASH\n    __binary_info_end = .;\n    . = ALIGN(4);\n\n    \/* End of .text-like segments *\/\n    __etext = .;\n\n   .ram_vector_table (COPY): {\n        *(.ram_vector_table)\n    } > RAM\n\n    .data : {\n        __data_start__ = .;\n        *(vtable)\n\n        *(.time_critical*)\n\n        \/* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM *\/\n        *(.text*)\n        . = ALIGN(4);\n        *(.rodata*)\n        . = ALIGN(4);\n\n        *(.data*)\n\n        . = ALIGN(4);\n        *(.after_data.*)\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__mutex_array_start = .);\n        KEEP(*(SORT(.mutex_array.*)))\n        KEEP(*(.mutex_array))\n        PROVIDE_HIDDEN (__mutex_array_end = .);\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(SORT(.preinit_array.*)))\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM AT> FLASH\n\n    .uninitialized_data (COPY): {\n        . = ALIGN(4);\n        *(.uninitialized_data*)\n    } > RAM\n\n    \/* Start and end symbols must be word-aligned *\/\n    .scratch_x : {\n        __scratch_x_start__ = .;\n        *(.scratch_x.*)\n        . = ALIGN(4);\n        __scratch_x_end__ = .;\n    } > SCRATCH_X AT > FLASH\n    __scratch_x_source__ = LOADADDR(.scratch_x);\n\n    .scratch_y : {\n        __scratch_y_start__ = .;\n        *(.scratch_y.*)\n        . = ALIGN(4);\n        __scratch_y_end__ = .;\n    } > SCRATCH_Y AT > FLASH\n    __scratch_y_source__ = LOADADDR(.scratch_y);\n\n    .bss  : {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack*_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later\n     *\n     * stack1 section may be empty\/missing if platform_launch_core1 is not used *\/\n\n    \/* by default we put core 0 stack at the end of scratch Y, so that if core 1\n     * stack is not used then all of SCRATCH_X is free.\n     *\/\n    .stack1_dummy (COPY):\n    {\n        *(.stack1*)\n    } > SCRATCH_X\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SCRATCH_Y\n\n    .flash_end : {\n        __flash_binary_end = .;\n    } > FLASH\n\n    \/* stack limit is poorly named, but historically is maximum heap ptr *\/\n    __StackLimit = ORIGIN(RAM) + LENGTH(RAM);\n    __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);\n    __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);\n    __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);\n    __StackBottom = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed\")\n\n    ASSERT( __binary_info_header_end - __logical_binary_start <= 256, \"Binary info must be in first 256 bytes of the binary\")\n    \/* todo assert on extra code *\/\n}\n\n","old_contents":"\/* Based on GCC ARM embedded samples.\n   Defines the following symbols for use by code:\n    __exidx_start\n    __exidx_end\n    __etext\n    __data_start__\n    __preinit_array_start\n    __preinit_array_end\n    __init_array_start\n    __init_array_end\n    __fini_array_start\n    __fini_array_end\n    __data_end__\n    __bss_start__\n    __bss_end__\n    __end__\n    end\n    __HeapLimit\n    __StackLimit\n    __StackTop\n    __stack (== StackTop)\n*\/\n\nMEMORY\n{\n    FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k\n    RAM(rwx) : ORIGIN =  0x20000000, LENGTH = 256k\n    SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k\n    SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k\n}\n\nENTRY(_entry_point)\n\nSECTIONS\n{\n    \/* Second stage bootloader is prepended to the image. It must be 256 bytes big\n       and checksummed. It is usually built by the boot_stage2 target\n       in the Pico SDK\n    *\/\n\n    .flash_begin : {\n        __flash_binary_start = .;\n    } > FLASH\n\n    .boot2 : {\n        __boot2_start__ = .;\n        KEEP (*(.boot2))\n        __boot2_end__ = .;\n    } > FLASH\n\n    ASSERT(__boot2_end__ - __boot2_start__ == 256,\n        \"ERROR: Pico second stage bootloader must be 256 bytes in size\")\n\n    \/* The second stage will always enter the image at the start of .text.\n       The debugger will use the ELF entry point, which is the _entry_point\n       symbol if present, otherwise defaults to start of .text.\n       This can be used to transfer control back to the bootrom on debugger\n       launches only, to perform proper flash setup.\n    *\/\n\n    .text : {\n        __reset_start = .;\n        KEEP (*(.reset))\n        . = ALIGN(256);\n        __reset_end = .;\n        ASSERT(__reset_end - __reset_start == 256, \"ERROR: reset section should only be 256 bytes\");\n        KEEP (*(.vectors))\n        \/* TODO revisit this now memset\/memcpy\/float in ROM *\/\n        \/* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from\n         * FLASH ... we will include any thing excluded here in .data below by default *\/\n        *(.init)\n        \/* Change for MicroPython... excluse gc.c, parse.c, vm.c from flash *\/\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a: *lib_a-mem*.o *libm.a: *gc.c.obj *vm.c.obj *parse.c.obj) .text*)\n        *(.fini)\n        \/* Pull all c'tors into .text *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n        \/* Followed by destructors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n    .rodata : {\n        *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*)\n        . = ALIGN(4);\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))\n        . = ALIGN(4);\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    \/* Machine inspectable binary information *\/\n    . = ALIGN(4);\n    __binary_info_start = .;\n    .binary_info :\n    {\n        KEEP(*(.binary_info.keep.*))\n        *(.binary_info.*)\n    } > FLASH\n    __binary_info_end = .;\n    . = ALIGN(4);\n\n    \/* End of .text-like segments *\/\n    __etext = .;\n\n   .ram_vector_table (COPY): {\n        *(.ram_vector_table)\n    } > RAM\n\n    .data : {\n        __data_start__ = .;\n        *(vtable)\n\n        *(.time_critical*)\n\n        \/* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM *\/\n        *(.text*)\n        . = ALIGN(4);\n        *(.rodata*)\n        . = ALIGN(4);\n\n        *(.data*)\n\n        . = ALIGN(4);\n        *(.after_data.*)\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__mutex_array_start = .);\n        KEEP(*(SORT(.mutex_array.*)))\n        KEEP(*(.mutex_array))\n        PROVIDE_HIDDEN (__mutex_array_end = .);\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(SORT(.preinit_array.*)))\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM AT> FLASH\n\n    .uninitialized_data (COPY): {\n        . = ALIGN(4);\n        *(.uninitialized_data*)\n    } > RAM\n\n    \/* Start and end symbols must be word-aligned *\/\n    .scratch_x : {\n        __scratch_x_start__ = .;\n        *(.scratch_x.*)\n        . = ALIGN(4);\n        __scratch_x_end__ = .;\n    } > SCRATCH_X AT > FLASH\n    __scratch_x_source__ = LOADADDR(.scratch_x);\n\n    .scratch_y : {\n        __scratch_y_start__ = .;\n        *(.scratch_y.*)\n        . = ALIGN(4);\n        __scratch_y_end__ = .;\n    } > SCRATCH_Y AT > FLASH\n    __scratch_y_source__ = LOADADDR(.scratch_y);\n\n    .bss  : {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack*_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later\n     *\n     * stack1 section may be empty\/missing if platform_launch_core1 is not used *\/\n\n    \/* by default we put core 0 stack at the end of scratch Y, so that if core 1\n     * stack is not used then all of SCRATCH_X is free.\n     *\/\n    .stack1_dummy (COPY):\n    {\n        *(.stack1*)\n    } > SCRATCH_X\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SCRATCH_Y\n\n    .flash_end : {\n        __flash_binary_end = .;\n    } > FLASH\n\n    \/* stack limit is poorly named, but historically is maximum heap ptr *\/\n    __StackLimit = ORIGIN(RAM) + LENGTH(RAM);\n    __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);\n    __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);\n    __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);\n    __StackBottom = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed\")\n    \/* todo assert on extra code *\/\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7c2dfc1558e598e07c015738e984f5c50c3e6c82","subject":"riscv: linker: correct _image_rom_size symbol info","message":"riscv: linker: correct _image_rom_size symbol info\n\nThis makes the _image_rom_size provide correct actual ROM image size.\n\nSigned-off-by: Dino Li <338d523ecf3700bd86eb9c34d220f91911d2a18c@ite.com.tw>\n","repos":"galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n\t_image_rodata_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end - _image_rom_start);\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_image_rom_end = LOADADDR(.last_section);\n_image_rom_size = _image_rom_end - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n\t_image_rodata_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end - _image_rom_start);\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8fd6d5526f4cfb433e25f544db62d09c69788747","subject":"[sw] Modify flash_link.ld for llvm coverage","message":"[sw] Modify flash_link.ld for llvm coverage\n\nWhen code is compiled with coverage enabled, the compiler emits various\nsymbols and sections that are used at runtime to collect coverage data.\nThis change modifies flash_link.ld linker script to preserve these\nsections.\n\nSigned-off-by: Alphan Ulusoy <23b245cc5a07aacf75a9db847b24c67dee1707bf@google.com>\n","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan","old_file":"sw\/device\/exts\/common\/flash_link.ld","new_file":"sw\/device\/exts\/common\/flash_link.ld","new_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * Linker script for an OpenTitan flash binaries.\n *\n * Portions of this file are Ibex-specific.\n *\/\n\nOUTPUT_ARCH(riscv)\nGROUP(-lgcc)\n\n\/**\n * Indicate that there are no dynamic libraries, whatsoever.\n *\/\n__DYNAMIC = 0;\n\n\/**\n * Memory definitions are auto-generated.\n *\/\nINCLUDE hw\/top_earlgrey\/sw\/autogen\/top_earlgrey_memory.ld\n\n\/* Reserving 32 bytes at the top of the RAM for test utils. *\/\n_test_reserved_size = 0x20;\n\n\/**\n * The stack starts at the end of RAM right after the 32 reserved bytes and grows down.\n * It is zeroed out so a size must be provided.\n *\/\n_stack_size = 0x2000 - _test_reserved_size; \/* ~8kb stack *\/\n_stack_start = ORIGIN(ram_main) + LENGTH(ram_main) - _test_reserved_size;\n_stack_end = _stack_start - _stack_size;\n\nSECTIONS {\n  \/**\n   * The flash header. This will eventually contain other stuff, like a\n   * signature, but for now it's just the entry point at offset zero.\n   *\/\n  .flash_header ORIGIN(eflash) : ALIGN(4) {\n    KEEP(*(.flash_header))\n  } > eflash\n\n  \/**\n   * C runtime (CRT) section, containing program initialization code.\n   *\n   * We don't use ENTRY, so the start of |flash| acts as the entrypoint. Since\n   * the CRT is the first thing that needs to run, it goes at the top.\n   *\/\n  .crt : ALIGN(4) {\n    KEEP(*(.crt))\n  } > eflash\n\n  \/**\n   * Ibex interrupt vectors. See 'ibex_interrupt_vectors.S' for more\n   * information.\n   *\/\n  .vectors : {\n    *(.vectors)\n  } > eflash\n\n  \/**\n   * For LLVM profiling. This contains a pointer to the runtime initialization\n   * function that is generated by the compiler. See\n   * 'InstrProfiling::emitInitialization()' in 'InstrProfiling.cpp' and\n   * 'getInstrProfInitFuncName()' in 'InstrProf.h'.\n   *\/\n  .init_array : ALIGN(4) {\n      _init_array_start = .;\n      *(.init_array)\n      *(.init_array.*)\n      . = ALIGN(4);\n      _init_array_end = .;\n  } > eflash\n\n  \/**\n   * Standard text section, containing program code.\n   *\/\n  .text : ALIGN(4) {\n    *(.text)\n    *(.text.*)\n  } > eflash\n\n  \/**\n   * Read-only data section, containing all large compile-time constants, like\n   * strings.\n   *\/\n  .rodata : ALIGN(4) {\n    \/* Small read-only data comes before regular read-only data for the same\n     * reasons as in the data section *\/\n    *(.srodata)\n    *(.srodata.*)\n    *(.rodata)\n    *(.rodata.*)\n\n    \/* Read-only sections for LLVM profiling. *\/\n    KEEP(*(__llvm_covfun))\n    KEEP(*(__llvm_covmap))\n    KEEP(*(__llvm_prf_names))\n  } > eflash\n\n  \/**\n   * \"Intitial data\" section, the initial values of the mutable data section\n   * initialized at runtime.\n   *\/\n  .idata : ALIGN(4) {\n    _data_init_start = .;\n  } > eflash\n\n  \/**\n   * Standard mutable data section, at the bottom of RAM. This will be\n   * initialized from the .idata section at runtime by the CRT.\n   *\/\n  .data ORIGIN(ram_main): AT(_data_init_start) ALIGN(4) {\n    _data_start = .;\n    __global_pointer$ = . + 2048;\n\n    \/* Small data should come before larger data. This helps to ensure small\n     * globals are within 2048 bytes of the value of `gp`, making their accesses\n     * hopefully only take one instruction. *\/\n    *(.sdata)\n    *(.sdata.*)\n\n    \/* Other data will likely need multiple instructions to load, so we're less\n     * concerned about address materialisation taking more than one instruction.\n     *\/\n    *(.data)\n    *(.data.*)\n\n    \/* Sections for LLVM profiling. *\/\n    KEEP(*(__llvm_prf_cnts))\n    KEEP(*(__llvm_prf_data))\n\n    . = ALIGN(4);\n    _data_end = .;\n  } > ram_main\n\n  \/**\n   * Standard BSS section. This will be zeroed at runtime by the CRT.\n   *\/\n  .bss : ALIGN(4) {\n    _bss_start = .;\n    \/* Small BSS comes before regular BSS for the same reasons as in the data\n     * section. *\/\n    *(.sbss)\n    *(.sbss.*)\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    _bss_end = .;\n  } > ram_main\n\n  \/**\n   * STAB debug table.\n   *\/\n  .stab 0x0 (NOLOAD): {\n    *(.stab)\n  }\n\n  \/**\n   * STAB debug strings.\n   *\/\n  .stabstr 0x0 (NOLOAD): {\n    *(.stabstr)\n  }\n\n  \/**\n   * The following sections are used by DV to implement logging in an\n   * alternate way, which enables simulation speed up by completely avoiding\n   * any string format processing or even the actual transmission of log data\n   * to a real peripheral.\n   *\n   * These sections are marked as dummy so that they can still be extracted\n   * using readelf or similar utilities. As such, the content in these sections\n   * is not relevant for the actual SW code and can be safely discarded.\n   *\/\n\n  \/**\n   * The following section contains log fields constructed from the logs using\n   * the log_fields_t struct defined in sw\/device\/lib\/base\/log.h. The size of\n   * each log field is fixed - 20 bytes, which is used as the delimiter.\n   *\/\n  .logs.fields 0x10000 (DSECT): {\n    *(.logs.fields)\n  }\n}\n","old_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * Linker script for an OpenTitan flash binaries.\n *\n * Portions of this file are Ibex-specific.\n *\/\n\nOUTPUT_ARCH(riscv)\nGROUP(-lgcc)\n\n\/**\n * Indicate that there are no dynamic libraries, whatsoever.\n *\/\n__DYNAMIC = 0;\n\n\/**\n * Memory definitions are auto-generated.\n *\/\nINCLUDE hw\/top_earlgrey\/sw\/autogen\/top_earlgrey_memory.ld\n\n\/* Reserving 32 bytes at the top of the RAM for test utils. *\/\n_test_reserved_size = 0x20;\n\n\/**\n * The stack starts at the end of RAM right after the 32 reserved bytes and grows down.\n * It is zeroed out so a size must be provided.\n *\/\n_stack_size = 0x2000 - _test_reserved_size; \/* ~8kb stack *\/\n_stack_start = ORIGIN(ram_main) + LENGTH(ram_main) - _test_reserved_size;\n_stack_end = _stack_start - _stack_size;\n\nSECTIONS {\n  \/**\n   * The flash header. This will eventually contain other stuff, like a\n   * signature, but for now it's just the entry point at offset zero.\n   *\/\n  .flash_header ORIGIN(eflash) : ALIGN(4) {\n    KEEP(*(.flash_header))\n  } > eflash\n\n  \/**\n   * C runtime (CRT) section, containing program initialization code.\n   *\n   * We don't use ENTRY, so the start of |flash| acts as the entrypoint. Since\n   * the CRT is the first thing that needs to run, it goes at the top.\n   *\/\n  .crt : ALIGN(4) {\n    KEEP(*(.crt))\n  } > eflash\n\n  \/**\n   * Ibex interrupt vectors. See 'ibex_interrupt_vectors.S' for more\n   * information.\n   *\/\n  .vectors : {\n    *(.vectors)\n  } > eflash\n\n  \/**\n   * Standard text section, containing program code.\n   *\/\n  .text : ALIGN(4) {\n    *(.text)\n    *(.text.*)\n  } > eflash\n\n  \/**\n   * Read-only data section, containing all large compile-time constants, like\n   * strings.\n   *\/\n  .rodata : ALIGN(4) {\n    \/* Small read-only data comes before regular read-only data for the same\n     * reasons as in the data section *\/\n    *(.srodata)\n    *(.srodata.*)\n    *(.rodata)\n    *(.rodata.*)\n  } > eflash\n\n  \/**\n   * \"Intitial data\" section, the initial values of the mutable data section\n   * initialized at runtime.\n   *\/\n  .idata : ALIGN(4) {\n    _data_init_start = .;\n  } > eflash\n\n  \/**\n   * Standard mutable data section, at the bottom of RAM. This will be\n   * initialized from the .idata section at runtime by the CRT.\n   *\/\n  .data ORIGIN(ram_main): AT(_data_init_start) ALIGN(4) {\n    _data_start = .;\n    __global_pointer$ = . + 2048;\n\n    \/* Small data should come before larger data. This helps to ensure small\n     * globals are within 2048 bytes of the value of `gp`, making their accesses\n     * hopefully only take one instruction. *\/\n    *(.sdata)\n    *(.sdata.*)\n\n    \/* Other data will likely need multiple instructions to load, so we're less\n     * concerned about address materialisation taking more than one instruction.\n     *\/\n    *(.data)\n    *(.data.*)\n    . = ALIGN(4);\n    _data_end = .;\n  } > ram_main\n\n  \/**\n   * Standard BSS section. This will be zeroed at runtime by the CRT.\n   *\/\n  .bss : ALIGN(4) {\n    _bss_start = .;\n    \/* Small BSS comes before regular BSS for the same reasons as in the data\n     * section *\/\n    *(.sbss)\n    *(.sbss.*)\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    _bss_end = .;\n  } > ram_main\n\n  \/**\n   * STAB debug table.\n   *\/\n  .stab 0x0 (NOLOAD): {\n    *(.stab)\n  }\n\n  \/**\n   * STAB debug strings.\n   *\/\n  .stabstr 0x0 (NOLOAD): {\n    *(.stabstr)\n  }\n\n  \/**\n   * The following sections are used by DV to implement logging in an\n   * alternate way, which enables simulation speed up by completely avoiding\n   * any string format processing or even the actual transmission of log data\n   * to a real peripheral.\n   *\n   * These sections are marked as dummy so that they can still be extracted\n   * using readelf or similar utilities. As such, the content in these sections\n   * is not relevant for the actual SW code and can be safely discarded.\n   *\/\n\n  \/**\n   * The following section contains log fields constructed from the logs using\n   * the log_fields_t struct defined in sw\/device\/lib\/base\/log.h. The size of\n   * each log field is fixed - 20 bytes, which is used as the delimiter.\n   *\/\n  .logs.fields 0x10000 (DSECT): {\n    *(.logs.fields)\n  }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a5eddb851ee0cfd5fae5599a7cd5ebb4e0e878a0","subject":"more search path","message":"more search path\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa.ld","new_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa.ld","new_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x1f000, LENGTH = 0x61000\r\n\tRAM (rwx) :  ORIGIN = 0x20002600, LENGTH = 0xda00\r\n\t\/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n\t*  from application to bootloader when using buttonluss DFU OTA.\r\n\t*\/\r\n\tNOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n\t\/** Location of bootloader setting in flash. *\/\r\n\tBOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n}\r\n\r\n\r\nSECTIONS\r\n{\r\n\t\/* Place the bootloader settings page in flash. *\/\r\n\t.bootloaderSettings(NOLOAD) :\r\n\t{\r\n\r\n\t} > BOOTLOADER_SETTINGS\r\n\r\n\t\/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n\t.noinit(NOLOAD) :\r\n\t{\r\n\r\n\t} > NOINIT\r\n}\r\n\r\nSECTIONS\r\n{\r\n  .pwr_mgmt_data :\r\n  {\r\n    PROVIDE(__start_pwr_mgmt_data = .);\r\n    KEEP(*(.pwr_mgmt_data))\r\n    PROVIDE(__stop_pwr_mgmt_data = .);\r\n  } > FLASH\r\n} INSERT AFTER .text\r\n\r\nSECTIONS\r\n{\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","old_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x1f000, LENGTH = 0x61000\r\n\tRAM (rwx) :  ORIGIN = 0x20002600, LENGTH = 0xda00\r\n\t\/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n\t*  from application to bootloader when using buttonluss DFU OTA.\r\n\t*\/\r\n\tNOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n\t\/** Location of bootloader setting in flash. *\/\r\n\tBOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n}\r\n\r\n\r\nSECTIONS\r\n{\r\n\t\/* Place the bootloader settings page in flash. *\/\r\n\t.bootloaderSettings(NOLOAD) :\r\n\t{\r\n\r\n\t} > BOOTLOADER_SETTINGS\r\n\r\n\t\/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n\t.noinit(NOLOAD) :\r\n\t{\r\n\r\n\t} > NOINIT\r\n}\r\n\r\nSECTIONS\r\n{\r\n  .pwr_mgmt_data :\r\n  {\r\n    PROVIDE(__start_pwr_mgmt_data = .);\r\n    KEEP(*(.pwr_mgmt_data))\r\n    PROVIDE(__stop_pwr_mgmt_data = .);\r\n  } > FLASH\r\n} INSERT AFTER .text\r\n\r\nSECTIONS\r\n{\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"484bb0deb9d165390f15e19df9bbf49f68e7fa8e","subject":"slight syntax tweak","message":"slight syntax tweak\n","repos":"embedded2015\/visualizer,embedded2015\/visualizer,embedded2015\/visualizer,embedded2015\/visualizer","old_file":"main.ld","new_file":"main.ld","new_contents":"ENTRY(main)\nMEMORY\n{\n\tFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\nSECTIONS\n{\n\t.text : {\n\t\tKEEP(*(.isr_vector))\n \t\t*(.text)\n \t\t*(.text.*)\n\t\t*(.rodata)\n\t\t_sidata = .;\n\t} >FLASH\n\n\t\/* Initialized data will initially be loaded in FLASH at the end\n\t * of the .text section.\n\t *\/\n\t.data : AT (_sidata) {\n\t\t_sdata = .;\n\t\t*(.data)\t\/* Initialized data *\/\n\t\t_edata = .;\n\t} >RAM\n\n\t.bss : {\n\t\t_sbss = .;\n\t\t*(.bss)         \/* Zero-filled run time allocate data memory *\/\n\t\t_ebss = .;\n\t} >RAM\n    \n    _estack = ORIGIN(RAM) + LENGTH(RAM);\n}  \n","old_contents":"ENTRY(main)\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 20K\n\n}\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n \t\t*(.text)\n \t\t*(.text.*)\n\t\t*(.rodata)\n\t\t_sidata = .;\n\t} >FLASH\n\n\t\/* Initialized data will initially be loaded in FLASH at the end of the .text section. *\/\n    .data : AT (_sidata) \n    {\n\t\t_sdata = .;\n\t\t*(.data)\t\t\/* Initialized data *\/\n\t\t_edata = .;\n\t} >RAM\n\n\t.bss : {\n\t\t_sbss = .;\n\t\t*(.bss)         \/* Zero-filled run time allocate data memory *\/\n\t\t_ebss = .;\n\t} >RAM\n    \n    _estack = ORIGIN(RAM) + LENGTH(RAM);\n }  ","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"b3b583819947cc2d3b151c9fba16fe5f5d1ac0d2","subject":"linker script works!","message":"linker script works!\n","repos":"ckkashyap\/rustix,ckkashyap\/rustix,ckkashyap\/rustix","old_file":"staging\/linker.ld","new_file":"staging\/linker.ld","new_contents":"ENTRY(EntryPoint)\n\n\/*KERNEL_VMA = 0x100000;*\/\nKERNEL_VMA = 0xFFFFFFFF80000000;\n\nSECTIONS\n{\n\n       . = 0x100000;\n\n       .boot :\n       {\n               *(.mbhdr)\n               _loadStart = .;\n               *(.boot)\n               . = ALIGN(4096);\n               Pml4 = .;\n               . += 0x1000;\n               Pdpt = .;\n               . += 0x1000;\n               Pd = .;\n               . += 0x1000;\n               . += 0x8000;\n               Stack = .;\n       }\n\n    . += KERNEL_VMA;\n\n    .text : AT(ADDR(.text) - KERNEL_VMA)\n    {\n        _code = .;\n        *(.text)\n        *(.rodata*)\n        . = ALIGN(4096);\n    }\n\n   .data : AT(ADDR(.data) - KERNEL_VMA)\n   {\n        _data = .;\n        *(.data)\n        . = ALIGN(4096);\n   }\n\n   .eh_frame : AT(ADDR(.eh_frame) - KERNEL_VMA)\n   {\n       _ehframe = .;\n       *(.eh_frame)\n        . = ALIGN(4096);\n   }\n\n\t_loadEnd = . - KERNEL_VMA;\n\n   .bss : AT(ADDR(.bss) - KERNEL_VMA)\n   {\n       _bss = .;\n       *(.bss)\n\n       \/*\n        * You usually need to include generated COMMON symbols\n        * under kernel BSS section or use gcc's -fno-common\n        *\/\n\n        *(COMMON)\n       . = ALIGN(4096);\n   }\n\n\t_bssEnd = . - KERNEL_VMA;\n   _end = .;\n\n   \/DISCARD\/ :\n   {\n        *(.comment)\n   }\n}\n","old_contents":"ENTRY(EntryPoint)\n\nVIRT_BASE = 0xFFFFFFFF80000000;\n\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.boot :\n\t{\n\t\t*(.mbhdr)\n\t\t_loadStart = .;\n\t\t*(.boot)\n\t\t. = ALIGN(4096);\n\t\tPml4 = .;\n\t\t. += 0x1000;\n\t\tPdpt = .;\n\t\t. += 0x1000;\n\t\tPd = .;\n\t\t. += 0x1000;\n\t\t. += 0x8000;\n\t\tStack = .;\n\t}\n\n\t. += VIRT_BASE;\n\n\t.text ALIGN(0x1000) : AT(ADDR(.text) - VIRT_BASE)\n\t{\n\t\t*(.text)\n\t\t*(.gnu.linkonce.t*)\n\t}\n\t\n\t.data ALIGN(0x1000) : AT(ADDR(.data) - VIRT_BASE)\n\t{\n\t\t*(.data)\n\t\t*(.gnu.linkonce.d*)\n\t}\n\t\n\t.rodata ALIGN(0x1000) : AT(ADDR(.rodata) - VIRT_BASE)\n\t{\n\t\t*(.rodata*)\n\t\t*(.gnu.linkonce.r*)\n\t}\n\t\n\t_loadEnd = . - VIRT_BASE;\n\t\n\t.bss ALIGN(0x1000) : AT(ADDR(.bss) - VIRT_BASE)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.gnu.linkonce.b*)\n\t}\n\t\n\t_bssEnd = . - VIRT_BASE;\n\t\n\t\/DISCARD\/ :\n\t{\n\t\t*(.comment)\n\t\t*(.eh_frame)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"fa95da4bdbff029bbc411e2519a996c720895758","subject":"*** empty log message ***","message":"*** empty log message ***\n","repos":"dmitrysmagin\/adplug,dmitrysmagin\/adplug,dmitrysmagin\/adplug","old_file":"test\/loudness.lds","new_file":"test\/loudness.lds","new_contents":"","old_contents":"\u0000\u0000C\u0005@\u0000\u0002\u0000\u0001\u0001\u0002\u0002\u0001\u0000\u0000\t\u0000!)b\u0000\u0001?\u0003\f\u0000\u0000\u0000\u0000\u0018_\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000>x\u0000\u0000\u0000\u0000!)b\u0000\u00018\u0003\f\u0000\u0000\u0000\u0001\u0018_\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000>d\u0000\u0000\u0000\u0000\u0001?4\u0000\u00018\u0000\u0000\u0000\u0000\u0000\u0000\f\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000&0\u0000\u0000\u0000.\u0002\u0000:\u0002\u0000\u0000\u0000\u0000\u0010\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u00002`@\u0000\u0000\u0000\u0000?\u0000\u0001?\u0000\u0006\f\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\f\u0000\u0000\u0000\u0000\u0000\u0000\u0000x\u0000\u0000\u0000\u0000\u0001?\u0002\u0002?\u0016\u0000\u000f\n\u0004\u0000\u0000\u0000\u0000\u0000\u0000\u001c\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000p\u0000\u0000\u0000\u0000\u0001?\u0003\u000f=\u0003\u000e\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000`\u0000\u0000\u0000\u0000\u0002?\u0015\u0001\u000f?4\u0000\u000e\u0000\u0000\u0000\u0003\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000`\u0000\u0000\u0000\u0000\u0001?<\u0001\u0000?\u0000\u000e\u0010\t\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000\u0000vh\u0000\u0000\u0000\u0001\u0000\u0004\u0000\u0000`\u0000\u0000\u0000\u0000\u0000\u0000\b\u0001\u0000 \u0001\u0000\u0001\u0000p\u0001\u00008\u0001\u0000\u0001\u0005>\u0000H\u0000\u0000J\u0000\u0000\u0000H\u0000\u0000J\u0000\u0000\u0000H\u0000\u0000J\u0000\u0000\u0000H\u0000\u0000\u0000E\u0000\u0000\u0000H\u0002\u0000E\u0000\u0000\u0000C\u0000\u0000\u0000C\u0000\u0000\u0000E\u0000\u0000\u0000A\u0000\u0000\u0000@\u0000\u0000\u0000>\u000b\u0000\u0000J\u0000\u0000\u0000J\u0001,\u0000J\u0001\u0018\u0000J\u0002\u0000\u0001\u0000\u0001L\u0000\u0001M\u0000\u0000\u0001L\u0000\u0001M\u0000\u0000\u0001L\u0000\u0001M\u0000\u0000\u0001L\u0000\u0000\u0001J\u0000\u0000\u0001L\u0002\u0001L\u0000\u0000\u0001M\u0000\u0000\u0001M\u0000\u0000\u0001L\u0000\u0000\u0001J\u0000\u0000\u0001H\u0000\u0000\u0001E\u000b\u0000\u0001>\u0000\u0000\u00012\u0001,\u00012\u0001\u0018\u00012\u0002\u0000\u0002\u0002\"\u0004\u0002\"\u0002\u0002\"\u0000\u0000\u0002!\u0000\u0000\u0002\"\u0000\u0000\u0002$\u0004\u0002$\u0002\u0002!\u0000\u0000\u0002$\u0002\u0002&\u000b\u0000\u0002","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"2986e7bb0d650629a6e68b01dbd18409e8d6202a","subject":"Remove unused symbols","message":"Remove unused symbols\n","repos":"simark\/qemu-arm-stuff,simark\/qemu-arm-stuff","old_file":"test.ld","new_file":"test.ld","new_contents":"MEMORY\n{\n  SDRAM (XRW) : ORIGIN = 0x00000000, LENGTH = 0x08000000\n  FLASH (xr)  : ORIGIN = 0x34000000, LENGTH = 0x04000000\n  SRAM (xrw)  : ORIGIN = 0x38000000, LENGTH = 0x04000000\n}\n\nflash_start = ORIGIN(FLASH);\n\nheap_size = 4096;\n\nSECTIONS\n{\n  \/* QEMU has starts executing at 0x10000... *\/\n  . = 0x10000;\n\n\n  .text : {\n    *(.text)\n    *(.text._sbrk)\n  } > SDRAM\n  \n  .data : {\n    *(.data)\n  } > SDRAM\n\n  .bss : {\n    __bss_start__ = .;\n    *(.bss)\n    *(COMMON)\n    __bss_end__ = .;\n  } > SDRAM\n  \n  \n  .heap : {\n    . = . + heap_size;\n    \/* Define \"end\" symbol for the _sbrk implementation from libgloss. *\/\n    end = .;\n  } > SDRAM\n}\n","old_contents":"MEMORY\n{\n  SDRAM (XRW) : ORIGIN = 0x00000000, LENGTH = 0x08000000\n  FLASH (xr)  : ORIGIN = 0x34000000, LENGTH = 0x04000000\n  SRAM (xrw)  : ORIGIN = 0x38000000, LENGTH = 0x04000000\n}\n\nflash_start = ORIGIN(FLASH);\n\nstack_size = 4096;\nheap_size = 4096;\n\n_stack_start = ORIGIN(SRAM) + LENGTH(SRAM);\n_stack_end = _stack_start - stack_size;\n\nSECTIONS\n{\n  \/* QEMU has starts executing at 0x10000... *\/\n  . = 0x10000;\n\n\n  .text : {\n    *(.text)\n    *(.text._sbrk)\n  } > SDRAM\n  \n  .data : {\n    *(.data)\n  } > SDRAM\n\n  .bss : {\n    __bss_start__ = .;\n    *(.bss)\n    *(COMMON)\n    __bss_end__ = .;\n  } > SDRAM\n  \n  \n  .heap : {\n    . = . + heap_size;\n    \/* Define \"end\" symbol for the _sbrk implementation from libgloss. *\/\n    end = .;\n  } > SDRAM\n}\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"92704603851c40c687238dfbfc08b0770d461012","subject":"[arm][cm][linkscripts] add a \"secondstage\" section","message":"[arm][cm][linkscripts] add a \"secondstage\" section\n\nThis provides a way for a platform or target to insert code or\nother secret sauce in front of the vector table for targets that\nneed a second stage loader prepended or something like that.\n","repos":"hollanderic\/lkstuff,littlekernel\/lk,hollanderic\/lkstuff,littlekernel\/lk,littlekernel\/lk,hollanderic\/lkstuff,littlekernel\/lk,hollanderic\/lkstuff","old_file":"arch\/arm\/system-twosegment.ld","new_file":"arch\/arm\/system-twosegment.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\nENTRY(_start)\nSECTIONS\n{\n    . = %ROMBASE%;\n    __rom_start = .;\n\n    \/* text\/read-only data *\/\n    .text : {\n        KEEP(*(.text.boot.secondstage))\n        KEEP(*(.text.boot.vectab1))\n        KEEP(*(.text.boot.vectab2))\n        KEEP(*(.text.boot))\n        *(.text* .sram.text.glue_7* .gnu.linkonce.t.*)\n    }\n\n    .interp : { *(.interp) }\n    .hash : { *(.hash) }\n    .dynsym : { *(.dynsym) }\n    .dynstr : { *(.dynstr) }\n    .rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) }\n    .rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) }\n    .rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) }\n    .rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) }\n    .rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }\n    .rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }\n    .rel.got : { *(.rel.got) }\n    .rela.got : { *(.rela.got) }\n    .rel.ctors : { *(.rel.ctors) }\n    .rela.ctors : { *(.rela.ctors) }\n    .rel.dtors : { *(.rel.dtors) }\n    .rela.dtors : { *(.rela.dtors) }\n    .rel.init : { *(.rel.init) }\n    .rela.init : { *(.rela.init) }\n    .rel.fini : { *(.rel.fini) }\n    .rela.fini : { *(.rela.fini) }\n    .rel.bss : { *(.rel.bss) }\n    .rela.bss : { *(.rela.bss) }\n    .rel.plt : { *(.rel.plt) }\n    .rela.plt : { *(.rela.plt) }\n    .init : { *(.init) } =0x9090\n    .plt : { *(.plt) }\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n    __exidx_end = .;\n\n    .rodata : ALIGN(4) {\n        __rodata_start = .;\n        __fault_handler_table_start = .;\n        KEEP(*(.rodata.fault_handler_table))\n        __fault_handler_table_end = .;\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\n    }\n\n    \/* fake section for .data to anchor off of\n     * needed because extra linker scripts tend to insert sections\n     * just after .rodata\n     *\/\n    .dummy_post_rodata : {\n        \/* end of rodata, start of data area *\/\n        __rodata_end = . ;\n        __rom_end = . ;\n        __data_start_rom = .;\n    }\n\n    \/* in two segment binaries, the data starts at the bottom of ram (MEMBASE)\n     * bump us forward to the start of ram\n     *\/\n    . = %MEMBASE%;\n\n    \/* start .data segment, force the physical address to be AT() __data_start_rom *\/\n    .data : AT ( ADDR (.dummy_post_rodata) + SIZEOF (.dummy_post_rodata) ) ALIGN(4) {\n        __data_start = .;\n        *(.data .data.* .gnu.linkonce.d.*)\n    }\n\n    \/* code that is located in ram *\/\n    .sram.text : ALIGN(4) {\n        KEEP (*(.sram.text*))\n    }\n    .ctors : ALIGN(4) {\n        __ctor_list = .;\n        KEEP(*(.ctors .init_array))\n        __ctor_end = .;\n    }\n    .dtors : ALIGN(4) {\n        __dtor_list = .;\n        KEEP(*(.dtors .fini_array))\n        __dtor_end = .;\n    }\n    .got : { *(.got.plt) *(.got) }\n    .dynamic : { *(.dynamic) }\n\n    \/*\n     * extra linker scripts tend to insert sections just after .data,\n     * so we want to make sure this symbol comes after anything inserted above,\n     * but not aligned to the next section necessarily.\n     *\/\n    .dummy_post_data : {\n        __data_end = .;\n    }\n\n    \/* uninitialized data (in same segment as writable data) *\/\n    .bss : ALIGN(4) {\n        KEEP(*(.bss.prebss.*))\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.bss .bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end = .;\n    }\n\n    _end = .;\n\n    . = %MEMBASE% + %MEMSIZE%;\n    _end_of_ram = .;\n\n    \/* Strip unnecessary stuff *\/\n    \/DISCARD\/ : { *(.comment .note .eh_frame) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\nENTRY(_start)\nSECTIONS\n{\n    . = %ROMBASE%;\n    __rom_start = .;\n\n    \/* text\/read-only data *\/\n    .text : {\n        KEEP(*(.text.boot.vectab1))\n        KEEP(*(.text.boot.vectab2))\n        KEEP(*(.text.boot))\n        *(.text* .sram.text.glue_7* .gnu.linkonce.t.*)\n    }\n\n    .interp : { *(.interp) }\n    .hash : { *(.hash) }\n    .dynsym : { *(.dynsym) }\n    .dynstr : { *(.dynstr) }\n    .rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) }\n    .rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) }\n    .rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) }\n    .rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) }\n    .rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }\n    .rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }\n    .rel.got : { *(.rel.got) }\n    .rela.got : { *(.rela.got) }\n    .rel.ctors : { *(.rel.ctors) }\n    .rela.ctors : { *(.rela.ctors) }\n    .rel.dtors : { *(.rel.dtors) }\n    .rela.dtors : { *(.rela.dtors) }\n    .rel.init : { *(.rel.init) }\n    .rela.init : { *(.rela.init) }\n    .rel.fini : { *(.rel.fini) }\n    .rela.fini : { *(.rela.fini) }\n    .rel.bss : { *(.rel.bss) }\n    .rela.bss : { *(.rela.bss) }\n    .rel.plt : { *(.rel.plt) }\n    .rela.plt : { *(.rela.plt) }\n    .init : { *(.init) } =0x9090\n    .plt : { *(.plt) }\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n    __exidx_end = .;\n\n    .rodata : ALIGN(4) {\n        __rodata_start = .;\n        __fault_handler_table_start = .;\n        KEEP(*(.rodata.fault_handler_table))\n        __fault_handler_table_end = .;\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\n    }\n\n    \/* fake section for .data to anchor off of\n     * needed because extra linker scripts tend to insert sections\n     * just after .rodata\n     *\/\n    .dummy_post_rodata : {\n        \/* end of rodata, start of data area *\/\n        __rodata_end = . ;\n        __rom_end = . ;\n        __data_start_rom = .;\n    }\n\n    \/* in two segment binaries, the data starts at the bottom of ram (MEMBASE)\n     * bump us forward to the start of ram\n     *\/\n    . = %MEMBASE%;\n\n    \/* start .data segment, force the physical address to be AT() __data_start_rom *\/\n    .data : AT ( ADDR (.dummy_post_rodata) + SIZEOF (.dummy_post_rodata) ) ALIGN(4) {\n        __data_start = .;\n        *(.data .data.* .gnu.linkonce.d.*)\n    }\n\n    \/* code that is located in ram *\/\n    .sram.text : ALIGN(4) {\n        KEEP (*(.sram.text*))\n    }\n    .ctors : ALIGN(4) {\n        __ctor_list = .;\n        KEEP(*(.ctors .init_array))\n        __ctor_end = .;\n    }\n    .dtors : ALIGN(4) {\n        __dtor_list = .;\n        KEEP(*(.dtors .fini_array))\n        __dtor_end = .;\n    }\n    .got : { *(.got.plt) *(.got) }\n    .dynamic : { *(.dynamic) }\n\n    \/*\n     * extra linker scripts tend to insert sections just after .data,\n     * so we want to make sure this symbol comes after anything inserted above,\n     * but not aligned to the next section necessarily.\n     *\/\n    .dummy_post_data : {\n        __data_end = .;\n    }\n\n    \/* uninitialized data (in same segment as writable data) *\/\n    .bss : ALIGN(4) {\n        KEEP(*(.bss.prebss.*))\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.bss .bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end = .;\n    }\n\n    _end = .;\n\n    . = %MEMBASE% + %MEMSIZE%;\n    _end_of_ram = .;\n\n    \/* Strip unnecessary stuff *\/\n    \/DISCARD\/ : { *(.comment .note .eh_frame) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7e39ec95975727f5793acba9aa81522c02592de4","subject":"soc: esp32c3: linker script update to support mcuboot","message":"soc: esp32c3: linker script update to support mcuboot\n\nThis change creates XiP image handling and proper\nLMA and VMA regions configurations.\n\nThis also adds common-ram.ld and common-rom.ld sections that\nrequire explicit handling due to image sections limitation\nin esptool.\n\nMove additional drivers into IRAM to protect against\nflash cache disable read\/write operation.\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr","old_file":"soc\/riscv\/esp32c3\/linker.ld","new_file":"soc\/riscv\/esp32c3\/linker.ld","new_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32c3 platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg\n#define RODATA_REGION drom0_0_seg\n#define IRAM_REGION  iram0_0_seg\n#define FLASH_CODE_REGION irom0_0_seg\n\n#define ROMABLE_REGION ROM\n\n#define SRAM_IRAM_START     0x4037C000\n#define SRAM_DRAM_START     0x3FC7C000\n#define ICACHE_SIZE         0x4000 \/* ICache size is fixed to 16KB on ESP32-C3 *\/\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n#ifdef CONFIG_FLASH_SIZE\n#define FLASH_SIZE CONFIG_FLASH_SIZE\n#else\n#define FLASH_SIZE 0x400000\n#endif\n\n#ifdef CONFIG_BOOTLOADER_ESP_IDF\n#define IROM_SEG_ORG 0x42000020\n#define IROM_SEG_LEN (FLASH_SIZE-0x20)\n#define IROM_SEG_ALIGN 0x4\n#else\n#define IROM_SEG_ORG 0x42000000\n#define IROM_SEG_LEN FLASH_SIZE\n#define IROM_SEG_ALIGN 0x10000\n#endif\n\n\/* Global symbols required for espressif hal build *\/\nMEMORY\n{\n  mcuboot_hdr (RX): org = 0x0, len = 0x20\n  metadata (RX): org = 0x20, len = 0x20\n  ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40\n\n  iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN\n\n  drom0_0_seg (R) : org = 0x3C000040, len = FLASH_SIZE - 0x40\n  dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE\n\n  rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000\n\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\n\/*  Default entry point:  *\/\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n  \/* Reserve space for MCUboot header in the binary *\/\n  .mcuboot_header :\n  {\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n  } > mcuboot_hdr\n  .metadata :\n  {\n    \/* Magic byte for load header *\/\n    LONG(0xace637d3)\n\n    \/* Application entry point address *\/\n    KEEP(*(.entry_addr))\n\n    \/* IRAM metadata:\n     * - Destination address (VMA) for IRAM region\n     * - Flash offset (LMA) for start of IRAM region\n     * - Size of IRAM region\n     *\/\n    LONG(ADDR(.iram0.text))\n    LONG(LOADADDR(.iram0.text))\n    LONG(SIZEOF(.iram0.text))\n\n    \/* DRAM metadata:\n     * - Destination address (VMA) for DRAM region\n     * - Flash offset (LMA) for start of DRAM region\n     * - Size of DRAM region\n     *\/\n    LONG(ADDR(.dram0.data))\n    LONG(LOADADDR(.dram0.data))\n    LONG(LOADADDR(.dummy.dram.data) + SIZEOF(.dummy.dram.data) - LOADADDR(.dram0.data))\n  } > metadata\n\n#include <linker\/rel-sections.ld>\n  _image_drom_start = LOADADDR(_RODATA_SECTION_NAME);\n  _image_drom_size = LOADADDR(_RODATA_SECTION_NAME) + SIZEOF(_RODATA_SECTION_NAME) - _image_drom_start;\n  _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);\n\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    *(.rodata_desc .rodata_desc.*)\n    *(.rodata_custom_desc .rodata_custom_desc.*)\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __rodata_region_start = .;\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(EXCLUDE_FILE (*libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.*) .rodata)\n    *(EXCLUDE_FILE (*libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.*) .rodata.*)\n\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*\n     * C++ constructor and destructor tables\n     * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.\n     *\n     * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.\n     * But the init_priority sections will be sorted for iteration in ascending order during startup.\n     * The rest of the init_array sections is sorted for iteration in descending order during startup, however.\n     * Hence a different section is generated for the init_priority functions which is iterated in\n     * ascending order during startup. The corresponding code can be found in startup.c.\n     *\/\n    __init_priority_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))\n    __init_priority_array_end = ABSOLUTE(.);\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/* C++ exception handlers table: *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    __rodata_region_end = .;\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    *(.srodata)\n    *(\".srodata.*\")\n    *(.rodata)\n    *(.rodata.*)\n    *(.rodata_wlog)\n    *(.rodata_wlog*)\n    _thread_local_end = ABSOLUTE(.);\n    _rodata_reserved_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)\n\n  .iram0.text : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _iram_start = ABSOLUTE(.);\n    _init_start = ABSOLUTE(.);\n\n    KEEP(*(.exception_vectors.text));\n    . = ALIGN(256);\n\n    _invalid_pc_placeholder = ABSOLUTE(.);\n\n    _iram_text_start = ABSOLUTE(.);\n\n    KEEP(*(.exception.entry*)); \/* contains __irq_wrapper *\/\n    *(.exception.other*)\n    . = ALIGN(4);\n\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    . = ALIGN(4);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:loader.*(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n    . = ALIGN(4);\n    _init_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  .dram0.dummy (NOLOAD):\n  {\n    \/**\n    * This section is required to skip .iram0.text area because iram0_0_seg and\n    * dram0_0_seg reflect the same address space on different buses.\n    *\/\n    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN(4);\n    *(.noinit)\n    *(.noinit.*)\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  .dram0.data :\n  {\n    . = ALIGN(4);\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n#ifdef CONFIG_RISCV_GP\n    __global_pointer$ = . + 0x800;\n#endif \/* CONFIG_RISCV_GP *\/\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n\n    \/* All dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libzephyr.a:loader.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    . = ALIGN(4);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  #pragma push_macro(\"GROUP_ROM_LINK_IN\")\n  #pragma push_macro(\"ITERABLE_SECTION_ROM\")\n  #undef GROUP_ROM_LINK_IN\n  #undef ITERABLE_SECTION_ROM\n  #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN\n  #define ITERABLE_SECTION_ROM(x,y)\n  #include <linker\/common-rom.ld>\n  #pragma pop_macro(\"GROUP_ROM_LINK_IN\")\n  #pragma pop_macro(\"ITERABLE_SECTION_ROM\")\n  #include <linker\/common-ram.ld>\n\n  __shell_root_cmds_start = __esp_shell_root_cmds_start;\n  __shell_root_cmds_end = __esp_shell_root_cmds_end;\n\n  .dummy.dram.data :\n  {\n    . = ALIGN(4);\n    _data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  .iram0.text_end (NOLOAD) :\n  {\n    \/* C3 memprot requires 512 B alignment for split lines *\/\n    . = ALIGN (16);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .iram0.data :\n  {\n    . = ALIGN(16);\n    *(.iram.data)\n    *(.iram.data*)\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  .iram0.bss (NOLOAD) :\n  {\n    . = ALIGN(16);\n    *(.iram.bss)\n    *(.iram.bss*)\n\n    . = ALIGN(16);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  _image_irom_start = LOADADDR(.flash.text);\n  _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;\n  _image_irom_vaddr = ADDR(.flash.text);\n\n  .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN)\n  {\n    . = SIZEOF(_RODATA_SECTION_NAME);\n    . = ALIGN(0x10000) + 0x20;\n    _rodata_reserved_start = .;\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  .flash.text : ALIGN(IROM_SEG_ALIGN)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/** CPU will try to prefetch up to 16 bytes of\n      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow\n      * safe access to up to 16 bytes after the last real instruction, add\n      * dummy bytes to ensure this\n      *\/\n    . += 16;\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/**\n     * Similar to _iram_start, this symbol goes here so it is\n     * resolved by addr2line in preference to the first symbol in\n     * the flash.text segment.\n     *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)\n\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)\n\n  \/* This section is required to skip rtc.text area because the text and\n   * data segments reflect the same address space on different buses.\n   *\/\n  .rtc.dummy (NOLOAD):\n  {\n    . = SIZEOF(.rtc.text);\n  } GROUP_LINK_IN(rtc_iram_seg)\n\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)\n\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(rtc_iram_seg)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  SECTION_PROLOGUE(.riscv.attributes, 0,)\n    {\n    KEEP(*(.riscv.attributes))\n    KEEP(*(.gnu.attributes))\n    }\n}\n","old_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32c3 platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define IRAM_REGION  iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\n#define SRAM_IRAM_START     0x4037C000\n#define SRAM_DRAM_START     0x3FC7C000\n#define ICACHE_SIZE         0x4000 \/* ICache size is fixed to 16KB on ESP32-C3 *\/\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n\/* Global symbols required for espressif hal build *\/\nMEMORY\n{\n  iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n  irom0_0_seg(RX): org = 0x42000020, len = 0x8000000-0x20\n\n  drom0_0_seg (R) : org = 0x3C000020, len = 0x8000000-0x20\n  dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE\n\n  rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000\n\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(__start)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } > rtc_iram_seg\n\n  \/* This section is required to skip rtc.text area because the text and\n   * data segments reflect the same address space on different buses.\n   *\/\n  .rtc.dummy (NOLOAD):\n  {\n    . = SIZEOF(.rtc.text);\n  } > rtc_iram_seg\n\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n\n  .iram0.text : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _iram_start = ABSOLUTE(.);\n    _iram_text_start = ABSOLUTE(.);\n    _init_start = ABSOLUTE(.);\n    KEEP(*(.exception_vectors.text));\n    . = ALIGN(256);\n\n    KEEP(*(.exception.entry*)); \/* contains __irq_wrapper *\/\n    *(.exception.other*)\n    . = ALIGN(4);\n\n    . = ALIGN (4);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    . = ALIGN(4);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n\n    . = ALIGN(4);\n    _init_end = ABSOLUTE(.);\n    _iram_text_end = ABSOLUTE(.);   *(.srodata)\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  \/**\n   * This section is required to skip .iram0.text area because iram0_0_seg and\n   * dram0_0_seg reflect the same address space on different buses.\n   *\/\n  .dram0.dummy (NOLOAD):\n  {\n    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } > dram0_0_seg\n\n#include <linker\/common-ram.ld>\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n#ifdef CONFIG_RISCV_GP\n    __global_pointer$ = . + 0x800;\n#endif \/* CONFIG_RISCV_GP *\/\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    _end = .;\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  \/* Shared RAM *\/\n  dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  .flash.text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  .flash_rodata_dummy (NOLOAD):\n  {\n    . = SIZEOF(.flash.text);\n    . = ALIGN(0x10000) + 0x20;\n    _rodata_reserved_start = .;\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  .flash.rodata : ALIGN(0x10)\n  {\n    _rodata_start = ABSOLUTE(.);\n    __rodata_region_start = .;\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    *(.rodata_desc .rodata_desc.*)               \/* Should be the first.  App version info.        DO NOT PUT ANYTHING BEFORE IT! *\/\n    *(.rodata_custom_desc .rodata_custom_desc.*) \/* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! *\/\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*\n     * C++ constructor and destructor tables\n     * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.\n     *\n     * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.\n     * But the init_priority sections will be sorted for iteration in ascending order during startup.\n     * The rest of the init_array sections is sorted for iteration in descending order during startup, however.\n     * Hence a different section is generated for the init_priority functions which is iterated in\n     * ascending order during startup. The corresponding code can be found in startup.c.\n     *\/\n    __init_priority_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))\n    __init_priority_array_end = ABSOLUTE(.);\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/* C++ exception handlers table: *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    __rodata_region_end = .;\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    *(.srodata)\n    *(\".srodata.*\")\n    *(.rodata)\n    *(.rodata.*)\n    *(.rodata_wlog)\n    *(.rodata_wlog*)\n    _thread_local_end = ABSOLUTE(.);\n    _rodata_reserved_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n    KEEP(*(.riscv.attributes))\n    KEEP(*(.gnu.attributes))\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8e03e692ed4d420d71e21987ccc40a73b61e8363","subject":"cpu\/esp8266: modified ld file for non-SDK version","message":"cpu\/esp8266: modified ld file for non-SDK version\n\nIntroduction of LoadStoreError handler requires new .UserExceptionTrampoline.tex section in ld script.","repos":"lazytech-org\/RIOT,toonst\/RIOT,lazytech-org\/RIOT,kYc0o\/RIOT,yogo1212\/RIOT,miri64\/RIOT,basilfx\/RIOT,mtausig\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,mtausig\/RIOT,authmillenon\/RIOT,lazytech-org\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,OTAkeys\/RIOT,x3ro\/RIOT,mtausig\/RIOT,aeneby\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,basilfx\/RIOT,smlng\/RIOT,miri64\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,lazytech-org\/RIOT,cladmi\/RIOT,ant9000\/RIOT,rfuentess\/RIOT,basilfx\/RIOT,OTAkeys\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,smlng\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,toonst\/RIOT,kaspar030\/RIOT,yogo1212\/RIOT,josephnoir\/RIOT,kaspar030\/RIOT,mfrey\/RIOT,mfrey\/RIOT,smlng\/RIOT,kYc0o\/RIOT,mtausig\/RIOT,RIOT-OS\/RIOT,mfrey\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,jasonatran\/RIOT,OTAkeys\/RIOT,cladmi\/RIOT,cladmi\/RIOT,cladmi\/RIOT,miri64\/RIOT,mtausig\/RIOT,yogo1212\/RIOT,rfuentess\/RIOT,toonst\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,rfuentess\/RIOT,yogo1212\/RIOT,josephnoir\/RIOT,x3ro\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,x3ro\/RIOT,OTAkeys\/RIOT,aeneby\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,smlng\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,mfrey\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,smlng\/RIOT,jasonatran\/RIOT,cladmi\/RIOT,kYc0o\/RIOT,x3ro\/RIOT,rfuentess\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,basilfx\/RIOT,aeneby\/RIOT,josephnoir\/RIOT,aeneby\/RIOT,josephnoir\/RIOT,lazytech-org\/RIOT,basilfx\/RIOT,rfuentess\/RIOT,toonst\/RIOT,mfrey\/RIOT,OlegHahm\/RIOT,toonst\/RIOT,josephnoir\/RIOT","old_file":"cpu\/esp8266\/ld\/esp8266.riot-os.no_sdk.app.ld","new_file":"cpu\/esp8266\/ld\/esp8266.riot-os.no_sdk.app.ld","new_contents":"\/**\n  * This linker script is a modified version of eagle.app.v6.ld that\n  * was generated from xt-genldscripts.tpp for LSP and shipped with\n  * ESP8266_NONOS_SDK\n  *\/\n\n\/* Linker Script for ld -N *\/\n\nMEMORY\n{\n  dport0_0_seg : org = 0x3FF00000, len = 0x10\n  dram0_0_seg :  org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :  org = 0x40100000, len = 0x8000\n  irom0_0_seg :  org = 0x40210000, len = 0x5C000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(_call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\n\/* ROM variables *\/\n\/* source: disassembly of boot rom at https:\/\/github.com\/trebisky\/esp8266 *\/\nPROVIDE( ets_task_min_prio = 0x3fffc6fc );\nPROVIDE( ets_idle_cb = 0x3fffdab0 );\nPROVIDE( ets_idle_arg = 0x3fffdab4 );\nPROVIDE( ets_task_exec_mask = 0x3fffdab8 );\nPROVIDE( ets_task_tab = 0x3fffdac0 );\nPROVIDE( flashchip = 0x3fffc714 );\nPROVIDE( sdk_flashchip = 0x3fffc718 );\nPROVIDE( ets_phy_mactime = 0x3ff20a00 );\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    \/* TODO put only necessary .rodata to dram\n    *libc.a:*.o(.rodata.* .rodata)\n    *core.a:*(.rodata.* .rodata)\n    *cpu.a:*(.rodata .rodata.*)\n    *\/\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  \/* ETS system memory starts at 0x3FFFC000 which is the top of the heap for the app *\/\n  . = 0x3FFFC000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.UserExceptionTrampoline.text)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* normal code should be in irom0 *\/\n    \/*\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *\/\n\n    \/* RIOT-OS compiled source files that use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *libcrypto.a:*(.literal .text)\n    *libmain.a:*(.literal .text .literal.* .text.*)\n    *libnet80211.a:*(.literal .text)\n    *libpp.a:*(.literal .text .literal.* .text.*)\n    *libphy.a:*(.literal .text .literal.* .text.*)\n    *libwpa.a:*(.literal .text)\n    *libwpa2.a:*(.literal .text)\n    *liblwip.a:*(.literal .text)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    *libgcc.a:*mulsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*divsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*fixsfsi.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memchr.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    enc28j60.a:*(.literal .text .literal.* .text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    *libmbedtls.a:(.literal .text .literal.* .text.*)\n\n    \/* RIOT-OS compiled code goes into IROM by default\n       (except for libgcc which is matched above.) *\/\n    *(.literal .text .literal.* .text.* .rodata .rodata.*)\n\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","old_contents":"\/**\n  * This linker script is a modified version of eagle.app.v6.ld that\n  * was generated from xt-genldscripts.tpp for LSP and shipped with\n  * ESP8266_NONOS_SDK\n  *\/\n\n\/* Linker Script for ld -N *\/\n\nMEMORY\n{\n  dport0_0_seg : org = 0x3FF00000, len = 0x10\n  dram0_0_seg :  org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :  org = 0x40100000, len = 0x8000\n  irom0_0_seg :  org = 0x40210000, len = 0x5C000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(_call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\n\/* ROM variables *\/\n\/* source: disassembly of boot rom at https:\/\/github.com\/trebisky\/esp8266 *\/\nPROVIDE( ets_task_min_prio = 0x3fffc6fc );\nPROVIDE( ets_idle_cb = 0x3fffdab0 );\nPROVIDE( ets_idle_arg = 0x3fffdab4 );\nPROVIDE( ets_task_exec_mask = 0x3fffdab8 );\nPROVIDE( ets_task_tab = 0x3fffdac0 );\nPROVIDE( flashchip = 0x3fffc714 );\nPROVIDE( sdk_flashchip = 0x3fffc718 );\nPROVIDE( ets_phy_mactime = 0x3ff20a00 );\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    \/* TODO put only necessary .rodata to dram\n    *libc.a:*.o(.rodata.* .rodata)\n    *core.a:*(.rodata.* .rodata)\n    *cpu.a:*(.rodata .rodata.*)\n    *\/\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  \/* ETS system memory starts at 0x3FFFC000 which is the top of the heap for the app *\/\n  . = 0x3FFFC000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* normal code should be in irom0 *\/\n    \/*\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *\/\n\n    \/* RIOT-OS compiled source files that use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *libcrypto.a:*(.literal .text)\n    *libmain.a:*(.literal .text .literal.* .text.*)\n    *libnet80211.a:*(.literal .text)\n    *libpp.a:*(.literal .text .literal.* .text.*)\n    *libphy.a:*(.literal .text .literal.* .text.*)\n    *libwpa.a:*(.literal .text)\n    *libwpa2.a:*(.literal .text)\n    *liblwip.a:*(.literal .text)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    *libgcc.a:*mulsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*divsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*fixsfsi.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memchr.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    enc28j60.a:*(.literal .text .literal.* .text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    *libmbedtls.a:(.literal .text .literal.* .text.*)\n\n    \/* RIOT-OS compiled code goes into IROM by default\n       (except for libgcc which is matched above.) *\/\n    *(.literal .text .literal.* .text.* .rodata .rodata.*)\n\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"87083aa8b3d9f9a22d8a1381528f0ef2d62d6adc","subject":"multiboot.ld: start everything at 1M, incl. '.header'","message":"multiboot.ld: start everything at 1M, incl. '.header'\n","repos":"yeputons\/arch-os-boot-assignment-term3,yeputons\/arch-os-boot-assignment-term3","old_file":"multiboot.ld","new_file":"multiboot.ld","new_contents":"OUTPUT_FORMAT(elf32-i386)\nOUTPUT_ARCH(i386)\nENTRY(entry_point)\n\nSECTIONS\n{\n    . = 1M;\n    .header : { .*(.header) }\n    .text : { *(.entry) *(.text) }\n    .data : { *(.data) }\n    .rodata : { *(.rodata) }\n    .bss : { *(.bss) }\n}\n","old_contents":"OUTPUT_FORMAT(elf32-i386)\nOUTPUT_ARCH(i386)\nENTRY(entry_point)\n\nSECTIONS\n{\n    .header : { .*(.header) }\n    . = 1M;\n    .text : { *(.entry) *(.text) }\n    .data : { *(.data) }\n    .rodata : { *(.rodata) }\n    .bss : { *(.bss) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"15f10e363815609592493b6ddb7f156f4acd367c","subject":"[build] minor changes in the kernel linker script","message":"[build] minor changes in the kernel linker script\n","repos":"vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs","old_file":"kernel\/arch\/i386\/linker_script.ld","new_file":"kernel\/arch\/i386\/linker_script.ld","new_contents":"\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib32\");\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib\");\n\nkernel_base_va = 0xC0000000;\n\nSECTIONS\n{\n  . = SEGMENT_START(\"text-segment\", kernel_base_va + 0x100000);\n\n  .text :\n  {\n    *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    *(.text.exit .text.exit.*)\n    *(.text.startup .text.startup.*)\n    *(.text.hot .text.hot.*)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    . = ALIGN(4096);\n  }\n\n  .data :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN(4096);\n  }\n\n  .bss :\n  {\n   *(.bss .bss.* .gnu.linkonce.b.*)\n  }\n\n  . = ALIGN(4);\n  _end = .;\n\n  \/DISCARD\/ : { *(.eh_frame*) }\n\n}\n\n\n","old_contents":"\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib32\");\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib\");\n\nkernel_base_va = 0xC0000000;\n\nSECTIONS\n{\n  . = SEGMENT_START(\"text-segment\", kernel_base_va + 0x100000);\n\n  .text :\n  {\n    *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    *(.text.exit .text.exit.*)\n    *(.text.startup .text.startup.*)\n    *(.text.hot .text.hot.*)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n  }\n\n  .rodata :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n  }\n\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n\n  . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));\n\n  .data :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n  }\n\n  __bss_start = .;\n  .bss :\n  {\n   *(.bss .bss.* .gnu.linkonce.b.*)\n  }\n   __bss_end = .;\n\n  . = ALIGN(32 \/ 8);\n  _end = .;\n  . = DATA_SEGMENT_END (.);\n\n  \/DISCARD\/ : { *(.eh_frame*) }\n\n}\n\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"aee9eda50a83adae9e2dfb73dabec12dd3e34fa4","subject":"armv7-m: Update the common linker script to include subsections","message":"armv7-m: Update the common linker script to include subsections\n","repos":"onkwon\/yaos,onkwon\/yaos,onkwon\/yaos","old_file":"arch\/armv7-m\/common.lds","new_file":"arch\/armv7-m\/common.lds","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\nresched = sys_schedule;\nsystick = systick64;\n\nPROVIDE(_rom_start   = ORIGIN(rom));\nPROVIDE(_rom_size    = LENGTH(rom));\nPROVIDE(_ram_start   = ORIGIN(ram));\nPROVIDE(_ram_size    = LENGTH(ram));\nPROVIDE(_ram_end     = ORIGIN(ram) + LENGTH(ram));\nPROVIDE(_vector_size = 0x200); \/* The minimum alignment is 128 words. *\/\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t*(.vector)\n\t\t*(.vector_irq)\n\t\t\/* TODO: fill irq_handler in here *\/\n\t\tFILL(0xDEAFC0DE);\n\n\t\t. = _vector_size;\n\t\tLONG(0); \/* null sentinel *\/\n\n\t\t*(.text.init)\n\n\t\t. = ALIGN(4);\n\t\t_init_func_list = .;\n\t\t*(.text.init.0)\n\t\t*(.text.init.1)\n\t\t*(.text.init.2)\n\t\t*(.text.init.*)\n\t\tLONG(0);\n\n\t\t*(.text)\n\t\t*(.text.*)\n\n\t\t. = ALIGN(4);\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\n\t\t. = ALIGN(4);\n\t\t_driver_list = .;\n\t\t*(.driver_list)\n\t\tLONG(0);\n\n\t\t. = ALIGN(4);\n\t\t_device_list = .;\n\t\t*(.device_list)\n\t\tLONG(0);\n\n\t\t_shell_cmdlist = .;\n\t\t*(.shell_cmdlist)\n\t\tLONG(0);\n\n\t\t. = ALIGN(4);\n\t\t_etext = .;\n\t} > rom\n\n#ifdef CONFIG_COMMON_IRQ_FRAMEWORK\n\t.data :\n#else\n\t.data _ram_start + _vector_size :\n#endif\n\t{\n\t\t. = ALIGN(4);\n\t\t_data = .;\n\n\t\t*(.data .data.*)\n\t\t*(.iap)\n\n\t\t. = ALIGN(4);\n\t\t_user_task_list = .;\n\t\t*(.user_task_list)\n\t\tLONG(0);\n\n\t\t. = ALIGN(4);\n\t\t_edata = .;\n\t} > ram AT > rom\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t_bss = .;\n\n\t\t*(.bss .bss.*)\n\t\t*(COMMON)\n\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t} > ram AT > rom\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\nresched = sys_schedule;\nsystick = systick64;\n\nPROVIDE(_rom_start   = ORIGIN(rom));\nPROVIDE(_rom_size    = LENGTH(rom));\nPROVIDE(_ram_start   = ORIGIN(ram));\nPROVIDE(_ram_size    = LENGTH(ram));\nPROVIDE(_ram_end     = ORIGIN(ram) + LENGTH(ram));\nPROVIDE(_vector_size = 0x200); \/* The minimum alignment is 128 words. *\/\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t*(.vector)\n\t\t*(.vector_irq)\n\t\t\/* TODO: fill irq_handler in here *\/\n\t\tFILL(0xDEAFC0DE);\n\n\t\t. = _vector_size;\n\t\tLONG(0); \/* null sentinel *\/\n\n\t\t*(.text.init)\n\n\t\t. = ALIGN(4);\n\t\t_init_func_list = .;\n\t\t*(.text.init.0)\n\t\t*(.text.init.1)\n\t\t*(.text.init.2)\n\t\t*(.text.init.*)\n\t\tLONG(0);\n\n\t\t*(.text)\n\t\t*(.text.*)\n\n\t\t. = ALIGN(4);\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\n\t\t. = ALIGN(4);\n\t\t_driver_list = .;\n\t\t*(.driver_list)\n\t\tLONG(0);\n\n\t\t. = ALIGN(4);\n\t\t_device_list = .;\n\t\t*(.device_list)\n\t\tLONG(0);\n\n\t\t_shell_cmdlist = .;\n\t\t*(.shell_cmdlist)\n\t\tLONG(0);\n\n\t\t. = ALIGN(4);\n\t\t_etext = .;\n\t} > rom\n\n#ifdef CONFIG_COMMON_IRQ_FRAMEWORK\n\t.data :\n#else\n\t.data _ram_start + _vector_size :\n#endif\n\t{\n\t\t. = ALIGN(4);\n\t\t_data = .;\n\n\t\t*(.data)\n\t\t*(.iap)\n\n\t\t. = ALIGN(4);\n\t\t_user_task_list = .;\n\t\t*(.user_task_list)\n\t\tLONG(0);\n\n\t\t. = ALIGN(4);\n\t\t_edata = .;\n\t} > ram AT > rom\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t_bss = .;\n\n\t\t*(.bss)\n\t\t*(COMMON)\n\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t} > ram AT > rom\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b6ddeca472cb74f0ef8b6155fddf4821b2f6209e","subject":"feat(ld): Put rodata in libplatforms.a into flash by default","message":"feat(ld): Put rodata in libplatforms.a into flash by default\n\ninternal: c7b64043\n","repos":"espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK,espressif\/ESP8266_RTOS_SDK","old_file":"ld\/eagle.app.v6.common.ld","new_file":"ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *libuser.a:(.rodata.* .rodata)\n    *libcirom.a:(.rodata.* .rodata)\n    *libmbedtls.a:(.rodata.* .rodata)\n    *libssl.a:(.rodata.* .rodata)\n    *libopenssl.a:(.rodata.* .rodata)\n    *libplatforms.a:(.rodata.* .rodata)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *libuser.a:(.rodata.* .rodata)\n    *libcirom.a:(.rodata.* .rodata)\n    *libmbedtls.a:(.rodata.* .rodata)\n    *libssl.a:(.rodata.* .rodata)\n    *libopenssl.a:(.rodata.* .rodata)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"66fb86972d906de559803d48fb79c3675bb5a461","subject":"bootloader: update bootloader memory map","message":"bootloader: update bootloader memory map\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/ld\/esp32c6\/bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/ld\/esp32c6\/bootloader.ld","new_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\/** Simplified memory map for the bootloader.\n *  Make sure the bootloader can load into main memory without overwriting itself.\n *\n *  ESP32-C6 ROM static data usage is as follows:\n *  - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART\/USB\/SPI download mode only\n *  - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup\n *  - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)\n *\n *  The 2nd stage bootloader can take space up to the end of ROM shared\n *  buffers area (0x4087c610).\n *\/\n\n\/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. *\/\niram_dram_offset = 0x0;\n\n\/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,\n * and work out iram_seg and iram_loader_seg addresses from there, backwards.\n *\/\n\n\/* These lengths can be adjusted, if necessary: *\/\nbootloader_usable_dram_end = 0x4087c610;\nbootloader_stack_overhead = 0x2000; \/* For safety margin between bootloader data section and startup stacks *\/\nbootloader_dram_seg_len = 0x5000;\nbootloader_iram_loader_seg_len = 0x7000;\nbootloader_iram_seg_len = 0x2000;\n\n\/* Start of the lower region is determined by region size and the end of the higher region *\/\nbootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;\nbootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;\nbootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset;\nbootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;\n\nMEMORY\n{\n  iram_seg (RWX) :                  org = bootloader_iram_seg_start, len = bootloader_iram_seg_len\n  iram_loader_seg (RWX) :           org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len\n  dram_seg (RW) :                   org = bootloader_dram_seg_start, len = bootloader_dram_seg_len\n}\n\n\/* Default entry point: *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)\n    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)\n    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)\n    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)\n    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _dram_start = ABSOLUTE(.);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.sdata2 .sdata2.* .srodata .srodata.*)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/* C++ constructor and destructor tables, properly ordered: *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _dram_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/** CPU will try to prefetch up to 16 bytes of\n      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow\n      * safe access to up to 16 bytes after the last real instruction, add\n      * dummy bytes to ensure this\n      *\/\n    . += 16;\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n\n\n\/**\n *  Appendix: Memory Usage of ROM bootloader\n *\n * 0x4086ad08 ------------------> _dram0_0_start\n *            |               |\n *            |               |\n *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h\n *            |               |\n *            |               |\n * 0x4087c610 ------------------> __stack_sentry\n *            |               |\n *            |               |   2. Startup pro cpu stack (freed when IDF app is running)\n *            |               |\n * 0x4087e610 ------------------> __stack (pro cpu)\n *            |               |\n *            |               |\n *            |               |   3. Shared memory only used in startup code or nonos\/early boot*\n *            |               |      (can be freed when IDF runs)\n *            |               |\n *            |               |\n * 0x4087f564 ------------------> _dram0_rtos_reserved_start\n *            |               |\n *            |               |\n *            |               |   4. Shared memory used in startup code and when IDF runs\n *            |               |\n *            |               |\n * 0x4087fab0 ------------------> _dram0_rtos_reserved_end\n *            |               |\n * 0x4087fce8 ------------------> _data_start_interface\n *            |               |\n *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)\n *            |               |\n * 0x40880000 ------------------> _data_end_interface\n *\/\n","old_contents":"\/*\n * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\/** Simplified memory map for the bootloader.\n *  Make sure the bootloader can load into main memory without overwriting itself.\n *  We put 2nd bootloader in the high address space (before ROM stack\/data\/bss).\n *  See memory usage for ROM bootloader at the end of this file.\n *\/\n\nMEMORY\n{\n  iram_seg (RWX) :                  org = 0x4086E000, len = 0x2000\n  iram_loader_seg (RWX) :           org = 0x40870000, len = 0x6000\n  dram_seg (RW) :                   org = 0x40876000, len = 0x4000\n}\n\n\/* Default entry point: *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)\n    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)\n    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)\n    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)\n    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _dram_start = ABSOLUTE(.);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.sdata2 .sdata2.* .srodata .srodata.*)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/* C++ constructor and destructor tables, properly ordered: *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _dram_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/** CPU will try to prefetch up to 16 bytes of\n      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow\n      * safe access to up to 16 bytes after the last real instruction, add\n      * dummy bytes to ensure this\n      *\/\n    . += 16;\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n\n\n\/**\n *  Appendix: Memory Usage of ROM bootloader\n *\n *  +--------+--------------+------+ 0x3FCC_AE00\n *  |        ^              |\n *  |        |              |\n *  |        | data\/bss     |\n *  |        |              |\n *  |        v              |\n *  +------------------------------+ 0x3FCD_C710\n *  |        ^              |\n *  |        |              |\n *  |        | stack        |\n *  |        |              |\n *  |        v              |\n *  +------------------------------+ 0x3FCD_E710\n *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"be886eda015f4554974cbfd5f89823ccf917208f","subject":"conifgs\/artik05x : Delete unnecessary file","message":"conifgs\/artik05x : Delete unnecessary file\n\nmemory_layout.ld is not needed in artik.\nSo it deleted.\n","repos":"an4967\/TizenRT,jeongchanKim\/TizenRT,sunghan-chang\/TizenRT,chanijjani\/TizenRT,jeongchanKim\/TizenRT,chanijjani\/TizenRT,Samsung\/TizenRT,sunghan-chang\/TizenRT,jsdosa\/TizenRT,an4967\/TizenRT,chanijjani\/TizenRT,jsdosa\/TizenRT,jeongarmy\/TizenRT,an4967\/TizenRT,davidfather\/TizenRT,junmin-kim\/TizenRT,davidfather\/TizenRT,jeongchanKim\/TizenRT,an4967\/TizenRT,junmin-kim\/TizenRT,Samsung\/TizenRT,an4967\/TizenRT,junmin-kim\/TizenRT,jeongarmy\/TizenRT,sunghan-chang\/TizenRT,jeongchanKim\/TizenRT,pillip8282\/TizenRT,jeongarmy\/TizenRT,jsdosa\/TizenRT,chanijjani\/TizenRT,junmin-kim\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT,jeongchanKim\/TizenRT,davidfather\/TizenRT,pillip8282\/TizenRT,junmin-kim\/TizenRT,chanijjani\/TizenRT,jsdosa\/TizenRT,davidfather\/TizenRT,jeongarmy\/TizenRT,junmin-kim\/TizenRT,sunghan-chang\/TizenRT,chanijjani\/TizenRT,chanijjani\/TizenRT,pillip8282\/TizenRT,pillip8282\/TizenRT,junmin-kim\/TizenRT,davidfather\/TizenRT,Samsung\/TizenRT,jeongchanKim\/TizenRT,jsdosa\/TizenRT,pillip8282\/TizenRT,davidfather\/TizenRT,an4967\/TizenRT,davidfather\/TizenRT,sunghan-chang\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,jsdosa\/TizenRT,Samsung\/TizenRT,jeongarmy\/TizenRT,Samsung\/TizenRT,an4967\/TizenRT,jeongchanKim\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,jsdosa\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT","old_file":"build\/configs\/artik05x\/scripts\/memory_layout.ld","new_file":"build\/configs\/artik05x\/scripts\/memory_layout.ld","new_contents":"","old_contents":"\/* This file is auto-generated based on values from .config file *\/\n\nMEMORY\n{\n  kflash (rx)  : ORIGIN = 0x040C8000, LENGTH = K\n  uflash (rx)  : ORIGIN = 0x00000000, LENGTH = K\n  ksram  (rwx)  : ORIGIN = 0x02023800, LENGTH = 242K\n  usram  (rwx)  : ORIGIN = 0x02060000, LENGTH = 128K\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b89b4e2259ba1ff12ce36f80eedb3090ab9355b9","subject":"cpu\/esp32: place libc functions in IRAM","message":"cpu\/esp32: place libc functions in IRAM\n\n","repos":"smlng\/RIOT,smlng\/RIOT,ant9000\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,authmillenon\/RIOT,ant9000\/RIOT,OTAkeys\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,authmillenon\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,smlng\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,smlng\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,basilfx\/RIOT,miri64\/RIOT,kYc0o\/RIOT,yogo1212\/RIOT,yogo1212\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,basilfx\/RIOT,smlng\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,OTAkeys\/RIOT,basilfx\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT","old_file":"cpu\/esp32\/ld\/esp32.common.ld","new_file":"cpu\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libc.a:*(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *littlefs.a:*(.literal .text .literal.* .text.*)\n    *littlefs2.a:*(.literal .text .literal.* .text.*)\n    *newlib_syscalls_default.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *syscalls.o(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *esp_common.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *littlefs.a:*(.literal .text .literal.* .text.*)\n    *littlefs2.a:*(.literal .text .literal.* .text.*)\n    *newlib_syscalls_default.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *syscalls.o(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *esp_common.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"e42a3245b5ec507694e943ce3027391d27299c00","subject":"Updates panda2 link file: Moves the offset where the automata code will be flashed. Removes unneeded debug declarations. Removes c-style memory mapping segments, because they should not be used. They would conflict with the stack_malloc principles.","message":"Updates panda2 link file:\nMoves the offset where the automata code will be flashed.\nRemoves unneeded debug declarations.\nRemoves c-style memory mapping segments, because they should not be used. They would conflict with the stack_malloc principles.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/nxp-lpc2368-panda2\/target.ld","new_file":"boards\/nxp-lpc2368-panda2\/target.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(entry)\n\n\/*INCLUDE \"testlibmbed_Debug_lib.ld\"*\/\nGROUP(\n libgcc.a\n libc.a\n libstdc++.a\n libm.a\n \/*libcr_newlib_nohost.a*\/\n crti.o\n crtn.o\n crtbegin.o\n crtend.o\n )\n\n\n\/* Memory Definitions: *\/\nMEMORY\n{\n    Flash  (rx)  : ORIGIN = 0x00005000, LENGTH = 460k\n    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 64k\n    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 16k\n    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k\n    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k\n    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k\n}\n\nautomata_code = 0x70000;\n\n\/* Stack sizes: *\/\nUND_Stack_Size = 32;\nABT_Stack_Size = 32;\nFIQ_Stack_Size = 32;\nIRQ_Stack_Size = 0x400;\nSVC_Stack_Size = 0x400;\nSYS_Stack_Size = 0x800; \/*main stack size*\/\n\nStack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;\n\n\/* Stack tops for each mode: *\/\n__stacks_top__ = __ETHRAM_segment_end__;\n__und_stack_top__ = __stacks_top__;\n__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;\n__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;\n__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;\n__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;\n__sys_stack_top__ = __svc_stack_top__ - SVC_Stack_Size ;\n__stacks_min__ = __sys_stack_top__ - SYS_Stack_Size;\n_sym_use_separate_stack_segment = 1;\n\n\/* C-accessible symbols for memory address ranges: *\/\n__FLASH_segment_start__ = ORIGIN( Flash );\n__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );\n__SRAM_segment_start__  = ORIGIN( Ram );\n__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );\n__ETHRAM_segment_start__  = ORIGIN( EthRam );\n__ETHRAM_segment_end__    = ORIGIN( EthRam ) + LENGTH( EthRam );\n__USBRAM_segment_start__  = ORIGIN( UsbRam );\n__USBRAM_segment_end__    = ORIGIN( UsbRam ) + LENGTH( UsbRam );\n\n\n\n\/* This symbol is used by malloc to ensure heap does not run oit of its\nallotted space (e.g. by colliding with stacks, or by reaching the end of the\nram segment. *\/\nPROVIDE(__cs3_heap_end = __SRAM_segment_end__);\n\nSECTIONS\n{\n    \/* first section is .text which is used for code *\/\n    __text_start__ = . ;\n    .text : {\n        __privileged_code_start__ = . ;\n        KEEP( *( .vectors ) )\n        *( .privileged_code )\n    \n        __privileged_code_end__ = .;\n\n        . = ALIGN( 4 ) ;\n        *( .text .text.* .gnu.linkonce.t.* )\n        *( .plt )\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *( .init ) )\n        . = ALIGN( 4 ) ;\n        KEEP( *( .fini ) )\n        . = ALIGN( 4 ) ;\n        __preinit_array_start = . ;\n        KEEP( *( .preinit_array ) )\n        __preinit_array_end = . ;\n        . = ALIGN( 4 ) ;\n        __init_array_start = . ;\n        KEEP( *( SORT( .init_array.* ) ) )\n        KEEP( *( .init_array ) )\n        __init_array_end = . ;\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *crtbegin.o( .ctors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )\n        KEEP( *( SORT( .ctors.* ) ) )\n        KEEP( *crtend.o( .ctors ) )\n        \n        . = ALIGN( 4 ) ;\n        __fini_array_start = . ;\n        KEEP( *( .fini_array ) )\n        KEEP( *( SORT( .fini_array.* ) ) )\n        __fini_array_end = . ;\n        \n        KEEP( *crtbegin.o( .dtors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )\n        KEEP( *( SORT( .dtors.* ) ) )\n        KEEP( *crtend.o( .dtors ) )\n\n        *( .gnu.warning )\n        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )\n\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n        \n        *( .rodata )\n        *(SORT(.rodata.*))\n\t*(SORT(.gnu.linkonce.r.*))\n    } >Flash\n    \n    __exidx_start = . ;\n    .ARM.exidx : {\n        *( .ARM.exidx* .gnu.linkonce.armexidx.* )\n    } >Flash\n    __exidx_end = . ;\n    \n    .text.align : { . = ALIGN( 8 ) ; } >Flash \/* Alignment schenanigans *\/\n    __text_end__ = . ;\n    \n    \/* .bss section -- used for uninitialized data *\/\n    \/* Located at the start of RAM *\/\n    .bss (NOLOAD) : {\n        __bss_start__ = . ;\n        *( .ram_vectors )\n        \n        __user_bss_start__ = . ;\n        *( .user_bss )\n        __user_bss_end__ = . ;\n        \n        *( .shbss )\n        *( .bss .bss.* .gnu.linkonce.b.* )\n        *( COMMON )\n        *( .ram.b )\n        . = ALIGN( 8 ) ;\n        \n        __bss_end__ = . ;\n    } >Ram AT>Flash\n\n    \/* .data section -- used for initialized data *\/\n    .data : {\n\tFILL(0xff)\n        __data_start__ = . ;\n        KEEP( *( .jcr ) )\n        *( .got.plt ) *( .got )\n        *( .shdata )\n        *( .data .data.* .gnu.linkonce.d.* )\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n        . = ALIGN (4);\n\n        *( .ram )\n        . = ALIGN( 8 ) ;\n        __data_end__ = . ;\n    } >Ram AT>Flash\n\n    __data_init_start__ = LOADADDR( .data ) ;\n\n    \/* Heap starts here and grows up in memory *\/\n    . = ALIGN( 8 ) ;\n    __heap_start__ = . ;\n    __cs3_heap_start = .;\n\n\tPROVIDE(_pvHeapStart = .);\n\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(entry)\n\n\/*INCLUDE \"testlibmbed_Debug_lib.ld\"*\/\nGROUP(\n libgcc.a\n libc.a\n libstdc++.a\n libm.a\n \/*libcr_newlib_nohost.a*\/\n crti.o\n crtn.o\n crtbegin.o\n crtend.o\n )\n\n\n\/* Memory Definitions: *\/\nMEMORY\n{\n    Flash  (rx)  : ORIGIN = 0x00005000, LENGTH = 460k\n    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 64k\n    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 16k\n    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k\n    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k\n    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k\n}\n\nautomata_code = 0x78000;\n\n\/* Stack sizes: *\/\nUND_Stack_Size = 32;\nABT_Stack_Size = 32;\nFIQ_Stack_Size = 32;\nIRQ_Stack_Size = 0x400;\nSVC_Stack_Size = 0x400;\nSYS_Stack_Size = 0x800; \/*main stack size*\/\n\nStack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;\n\n\/* Stack tops for each mode: *\/\n__stacks_top__ = __ETHRAM_segment_end__;\n__und_stack_top__ = __stacks_top__;\n__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;\n__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;\n__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;\n__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;\n__sys_stack_top__ = __svc_stack_top__ - SVC_Stack_Size ;\n__stacks_min__ = __sys_stack_top__ - SYS_Stack_Size;\n_sym_use_separate_stack_segment = 1;\n\n\/* C-accessible symbols for memory address ranges: *\/\n__FLASH_segment_start__ = ORIGIN( Flash );\n__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );\n__SRAM_segment_start__  = ORIGIN( Ram );\n__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );\n__ETHRAM_segment_start__  = ORIGIN( EthRam );\n__ETHRAM_segment_end__    = ORIGIN( EthRam ) + LENGTH( EthRam );\n__USBRAM_segment_start__  = ORIGIN( UsbRam );\n__USBRAM_segment_end__    = ORIGIN( UsbRam ) + LENGTH( UsbRam );\n\n\n\n\/* This symbol is used by malloc to ensure heap does not run oit of its\nallotted space (e.g. by colliding with stacks, or by reaching the end of the\nram segment. *\/\nPROVIDE(__cs3_heap_end = __SRAM_segment_end__);\n\nSECTIONS\n{\n    \/* first section is .text which is used for code *\/\n    __text_start__ = . ;\n    .text : {\n        __privileged_code_start__ = . ;\n        KEEP( *( .vectors ) )\n        *( .privileged_code )\n    \n        __privileged_code_end__ = .;\n\n        . = ALIGN( 4 ) ;\n        *( .text .text.* .gnu.linkonce.t.* )\n        *( .plt )\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *( .init ) )\n        . = ALIGN( 4 ) ;\n        KEEP( *( .fini ) )\n        . = ALIGN( 4 ) ;\n        __preinit_array_start = . ;\n        KEEP( *( .preinit_array ) )\n        __preinit_array_end = . ;\n        . = ALIGN( 4 ) ;\n        __init_array_start = . ;\n        KEEP( *( SORT( .init_array.* ) ) )\n        KEEP( *( .init_array ) )\n        __init_array_end = . ;\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *crtbegin.o( .ctors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )\n        KEEP( *( SORT( .ctors.* ) ) )\n        KEEP( *crtend.o( .ctors ) )\n        \n        . = ALIGN( 4 ) ;\n        __fini_array_start = . ;\n        KEEP( *( .fini_array ) )\n        KEEP( *( SORT( .fini_array.* ) ) )\n        __fini_array_end = . ;\n        \n        KEEP( *crtbegin.o( .dtors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )\n        KEEP( *( SORT( .dtors.* ) ) )\n        KEEP( *crtend.o( .dtors ) )\n\n        *( .gnu.warning )\n        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )\n\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n        \n        *( .rodata )\n        *(SORT(.rodata.*))\n\t*(SORT(.gnu.linkonce.r.*))\n    } >Flash\n    \n    __exidx_start = . ;\n    .ARM.exidx : {\n        *( .ARM.exidx* .gnu.linkonce.armexidx.* )\n    } >Flash\n    __exidx_end = . ;\n    \n    .text.align : { . = ALIGN( 8 ) ; } >Flash \/* Alignment schenanigans *\/\n    __text_end__ = . ;\n    \n    \/* .bss section -- used for uninitialized data *\/\n    \/* Located at the start of RAM *\/\n    .bss (NOLOAD) : {\n        __bss_start__ = . ;\n        *( .ram_vectors )\n        \n        __user_bss_start__ = . ;\n        *( .user_bss )\n        __user_bss_end__ = . ;\n        \n        *( .shbss )\n        *( .bss .bss.* .gnu.linkonce.b.* )\n        *( COMMON )\n        *( .ram.b )\n        . = ALIGN( 8 ) ;\n        \n        __bss_end__ = . ;\n    } >Ram AT>Flash\n\n    \/* .data section -- used for initialized data *\/\n    .data : {\n\tFILL(0xff)\n        __data_start__ = . ;\n        KEEP( *( .jcr ) )\n        *( .got.plt ) *( .got )\n        *( .shdata )\n        *( .data .data.* .gnu.linkonce.d.* )\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n        . = ALIGN (4);\n\n        *( .ram )\n        . = ALIGN( 8 ) ;\n        __data_end__ = . ;\n    } >Ram AT>Flash\n\n    __data_init_start__ = LOADADDR( .data ) ;\n\n    \/* Heap starts here and grows up in memory *\/\n    . = ALIGN( 8 ) ;\n    __heap_start__ = . ;\n    __cs3_heap_start = .;\n\n\tPROVIDE(_pvHeapStart = .);\n\t\n    .stab    0 (NOLOAD) : { *(.stab) }\n    .stabstr 0 (NOLOAD) : { *(.stabstr) }\n    \/* DWARF debug sections. *\/\n    \/* Symbols in the DWARF debugging sections are relative to the  *\/\n    \/* beginning of the section so we begin them at 0.              *\/\n    \/* DWARF 1 *\/\n    .debug           0 : { *(.debug) }\n    .line            0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo   0 : { *(.debug_srcinfo) }\n    .debug_sfnames   0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges   0 : { *(.debug_aranges) }\n    .debug_pubnames  0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev    0 : { *(.debug_abbrev) }\n    .debug_line      0 : { *(.debug_line) }\n    .debug_frame     0 : { *(.debug_frame) }\n    .debug_str       0 : { *(.debug_str) }\n    .debug_loc       0 : { *(.debug_loc) }\n    .debug_macinfo   0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n    \/* DWARF 3 *\/\n    .debug_pubtypes  0 : { *(.debug_pubtypes) }\n    .debug_ranges    0 : { *(.debug_ranges) }\n    \n    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }\n    .ARM.attributes     0 : {\n        KEEP( *( .ARM.attributes ) )\n        KEEP( *( .gnu.attributes ) )\n    }\n    \/DISCARD\/             : { *( .note.GNU-stack ) }\n    \n    \/* C data can be defined as being in special purpose RAMs using\n     * __attribute__ ((section (\"ethram\"))) for example. *\/\n    .usbram (NOLOAD):\n    {\n        *( .usbram )\n        *( .usbram.* )\n    } > UsbRam\n    .ethram (NOLOAD):\n    {\n        *( .ethram )\n        *( .ethram.* )\n    } > EthRam\n    .canram (NOLOAD):\n    {\n        *( .canram )\n        *( .canram.* )\n    } > CanRam\n    .batram (NOLOAD):\n    {\n        *( .batram )\n        *( .batram.* )\n    } > BatRam\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"8e65034643a683375f4e9e10108fd04b428c8d1d","subject":"Align sections in linker script","message":"Align sections in linker script\n","repos":"phil-opp\/blog_os,phil-opp\/blog_os,phil-opp\/blogOS,phil-opp\/blog_os,phil-opp\/blogOS,phil-opp\/blog_os","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/*\nCopyright 2015 Philipp Oppermann. See the README.md\nfile at the top-level directory of this distribution.\n\nLicensed under the Apache License, Version 2.0 <LICENSE-APACHE or\nhttp:\/\/www.apache.org\/licenses\/LICENSE-2.0> or the MIT license\n<LICENSE-MIT or http:\/\/opensource.org\/licenses\/MIT>, at your\noption. This file may not be copied, modified, or distributed\nexcept according to those terms.\n*\/\n\nENTRY(start)\n\nSECTIONS {\n  . = 1M;\n\n  .rodata : ALIGN(4K)\n  {\n    \/* ensure that the multiboot header is at the beginning *\/\n    KEEP(*(.multiboot_header))\n    *(.rodata .rodata.*)\n  }\n\n  .text : ALIGN(4K)\n  {\n    *(.text .text.*)\n  }\n\n  .data : ALIGN(4K)\n  {\n    *(.data .data.*)\n  }\n\n  .data.rel.ro : ALIGN(4K) {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n  }\n\n  .gcc_except_table : ALIGN(4K) {\n    *(.gcc_except_table)\n  }\n}\n","old_contents":"\/*\nCopyright 2015 Philipp Oppermann. See the README.md\nfile at the top-level directory of this distribution.\n\nLicensed under the Apache License, Version 2.0 <LICENSE-APACHE or\nhttp:\/\/www.apache.org\/licenses\/LICENSE-2.0> or the MIT license\n<LICENSE-MIT or http:\/\/opensource.org\/licenses\/MIT>, at your\noption. This file may not be copied, modified, or distributed\nexcept according to those terms.\n*\/\n\nENTRY(start)\n\nSECTIONS {\n  . = 1M;\n\n  .boot :\n  {\n    \/* ensure that the multiboot header is at the beginning *\/\n    KEEP(*(.multiboot_header))\n  }\n\n  .text :\n  {\n    *(.text .text.*)\n  }\n\n  .rodata : {\n    *(.rodata .rodata.*)\n  }\n\n  .data.rel.ro : {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n  }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f21c4159578f4acbe73673ac5e5e1858d439b99d","subject":"fix RO area start address","message":"fix RO area start address\n","repos":"hirakuni45\/RL78,hirakuni45\/RL78,hirakuni45\/RL78","old_file":"L1C\/R5F110ME.ld","new_file":"L1C\/R5F110ME.ld","new_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/L1C, 64K Flash, 8K RAM, 8K Data-Flash *\/\n\/* R5F100LEAFB:  64K (0x00000 - 0x0FFFF) \/  8K (0xFDF00 - 0xFFEFF) \/ 8K (0xF1000 - 0xF2FFF) *\/\n\/* DataFlash Library(FDL T04) used self-ram: 0xFAF00 to 0xFAF87 (136 bytes) *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007C\n\tOPT (r)   : ORIGIN = 0x000C0, LENGTH = 0x00004\n\tSEC_ID (r): ORIGIN = 0x000C4, LENGTH = 0x0000A\n\tROM (r)   : ORIGIN = 0x000D8, LENGTH = 0x0FF28\n\tRAM (w)   : ORIGIN = 0xFDF00, LENGTH = 0x01F20\n\tSTACK (w) : ORIGIN = 0xFFE20, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n\n  .opt :\n  {\n    KEEP(*(.opt))\n  } > OPT\n\n  .sec_id :\n  {\n    KEEP(*(.sec_id))\n  } > SEC_ID\n\n  \/* CubeSuite always starts at 0xd8.  *\/\n  .csstart : {\n    *(.csstart)\n  } > ROM\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n\t.rodata (MAX(__romdatastart + __romdatacopysize, 0x3000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    PROVIDE (__ctor_start = .);\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    PROVIDE (__ctor_end = .);\n\n    PROVIDE (__dtor_start = .);\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    PROVIDE (__dtor_end = .);\n  } > ROM\n\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    *(PFDL_COD)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .hightext : {\n    *(.hightext)\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/L1C, 64K Flash, 8K RAM, 8K Data-Flash *\/\n\/* R5F100LEAFB:  64K (0x00000 - 0x0FFFF) \/  8K (0xFDF00 - 0xFFEFF) \/ 8K (0xF1000 - 0xF2FFF) *\/\n\/* DataFlash Library(FDL T04) used self-ram: 0xFAF00 to 0xFAF87 (136 bytes) *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007C\n\tOPT (r)   : ORIGIN = 0x000C0, LENGTH = 0x00004\n\tSEC_ID (r): ORIGIN = 0x000C4, LENGTH = 0x0000A\n\tROM (r)   : ORIGIN = 0x000D8, LENGTH = 0x0FF28\n\tRAM (w)   : ORIGIN = 0xFDF00, LENGTH = 0x01F20\n\tSTACK (w) : ORIGIN = 0xFFE20, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n\n  .opt :\n  {\n    KEEP(*(.opt))\n  } > OPT\n\n  .sec_id :\n  {\n    KEEP(*(.sec_id))\n  } > SEC_ID\n\n  \/* CubeSuite always starts at 0xd8.  *\/\n  .csstart : {\n    *(.csstart)\n  } > ROM\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n\t.rodata (MAX(__romdatastart + __romdatacopysize, 0x2000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    PROVIDE (__ctor_start = .);\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    PROVIDE (__ctor_end = .);\n\n    PROVIDE (__dtor_start = .);\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    PROVIDE (__dtor_end = .);\n  } > ROM\n\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    *(PFDL_COD)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .hightext : {\n    *(.hightext)\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"fb983c7692902a3f75bf6f6f02bc9fa3a5e34609","subject":"nrf5\/boards: Inrease heap size in the nrf52832 w\/s132 bluetooth stack linker script.","message":"nrf5\/boards: Inrease heap size in the nrf52832 w\/s132 bluetooth stack linker script.\n","repos":"adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython,tralamazza\/micropython,tralamazza\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython","old_file":"nrf5\/boards\/nrf52832_512k_64k_s132.ld","new_file":"nrf5\/boards\/nrf52832_512k_64k_s132.ld","new_contents":"\/*\n    GNU linker script for NRF52 w\/ s132 3.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x0001f000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x060000 \/* 396 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x200039c0, LENGTH = 0x0c640  \/* 49.5 KiB, give 8KiB headroom for softdevice *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20007000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52 w\/ s132 3.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x0001f000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x060000 \/* 396 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x200039c0, LENGTH = 0x0c640  \/* 49.5 KiB, give 8KiB headroom for softdevice *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20006000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2521e082564412ce1bf78a378652f4bea19516e5","subject":"Reduce space for initial stack.","message":"Reduce space for initial stack.\n","repos":"mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,mlaz\/mynewt-core,wes3\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,wes3\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,wes3\/incubator-mynewt-core,wes3\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core","old_file":"hw\/bsp\/stm32f3discovery\/stm32f3discovery.ld","new_file":"hw\/bsp\/stm32f3discovery\/stm32f3discovery.ld","new_contents":"\/**\r\n * Copyright (c) 2015 Runtime Inc.\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n * \r\n *   http:\/\/www.apache.org\/licenses\/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\/\r\n\/*\r\n*****************************************************************************\r\n**\r\n**  File        : stm32_flash.ld\r\n**\r\n**  Abstract    : Linker script for STM32F303VC Device with\r\n**                256KByte FLASH, 40KByte RAM\r\n**\r\n**                Set heap size, stack size and stack location according\r\n**                to application requirements.\r\n**\r\n**                Set memory bank area and size if external memory is used.\r\n**\r\n**  Target      : STMicroelectronics STM32\r\n**\r\n**  Environment : Atollic TrueSTUDIO(R)\r\n**\r\n**  Distribution: The file is distributed as is, without any warranty\r\n**                of any kind.\r\n**\r\n**  (c)Copyright Atollic AB.\r\n**  You may use this file as-is or modify it according to the needs of your\r\n**  project. This file may only be built (assembled or compiled and linked)\r\n**  using the Atollic TrueSTUDIO(R) product. The use of this file together\r\n**  with other tools than Atollic TrueSTUDIO(R) is not permitted.\r\n**\r\n*****************************************************************************\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\n\/* Highest address of the user mode stack *\/\r\n_estack = 0x20009FFF;    \/* end of RAM *\/\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x200; \/* required amount of stack *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 256K\r\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 40K\r\nCCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 8K\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    __isr_vector = .;\r\n    KEEP(*(.isr_vector)) \/* Startup code *\/\r\n    __isr_vector_end = .;\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  \/* The program code and other data goes into FLASH *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)           \/* .text sections (code) *\/\r\n    *(.text*)          \/* .text* sections (code) *\/\r\n    *(.glue_7)         \/* glue arm to thumb code *\/\r\n    *(.glue_7t)        \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;        \/* define a global symbols at end of code *\/\r\n  } >FLASH\r\n\r\n  \/* Constant data goes into FLASH *\/\r\n  .rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n  .ARM : {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } >FLASH\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } >FLASH\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } >FLASH\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } >FLASH\r\n\r\n  \/* used by the startup to initialize data *\/\r\n  _sidata = LOADADDR(.data);\r\n\r\n  .vector_relocation :\r\n  {\r\n     . = ALIGN(4);\r\n     __vector_tbl_reloc__ = .;\r\n     . = . + (__isr_vector_end - __isr_vector);\r\n     . = ALIGN(4);\r\n  } > RAM\r\n\r\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\r\n  .data : \r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .;        \/* create a global symbol at data start *\/\r\n    *(.data)           \/* .data sections *\/\r\n    *(.data*)          \/* .data* sections *\/\r\n\r\n    . = ALIGN(4);\r\n    _edata = .;        \/* define a global symbol at data end *\/\r\n  } >RAM AT> FLASH\r\n\r\n  _siccmram = LOADADDR(.ccmram);\r\n\r\n  \/* CCM-RAM section \r\n  * \r\n  * IMPORTANT NOTE! \r\n  * If initialized variables will be placed in this section, \r\n  * the startup code needs to be modified to copy the init-values.  \r\n  *\/\r\n  .ccmram :\r\n  {\r\n    . = ALIGN(4);\r\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\r\n    *(.ccmram)\r\n    *(.ccmram*)\r\n    \r\n    . = ALIGN(4);\r\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\r\n  } >CCMRAM AT> FLASH\r\n\r\n  \r\n  \/* Uninitialized data section *\/\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n    _sbss = .;         \/* define a global symbol at bss start *\/\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .;         \/* define a global symbol at bss end *\/\r\n    __bss_end__ = _ebss;\r\n  } >RAM\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(4);\r\n  } >RAM\r\n\r\n  \r\n\r\n  \/* Remove information from the standard libraries *\/\r\n  \/DISCARD\/ :\r\n  {\r\n    libc.a ( * )\r\n    libm.a ( * )\r\n    libgcc.a ( * )\r\n  }\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n","old_contents":"\/**\r\n * Copyright (c) 2015 Runtime Inc.\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n * \r\n *   http:\/\/www.apache.org\/licenses\/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n *\/\r\n\/*\r\n*****************************************************************************\r\n**\r\n**  File        : stm32_flash.ld\r\n**\r\n**  Abstract    : Linker script for STM32F303VC Device with\r\n**                256KByte FLASH, 40KByte RAM\r\n**\r\n**                Set heap size, stack size and stack location according\r\n**                to application requirements.\r\n**\r\n**                Set memory bank area and size if external memory is used.\r\n**\r\n**  Target      : STMicroelectronics STM32\r\n**\r\n**  Environment : Atollic TrueSTUDIO(R)\r\n**\r\n**  Distribution: The file is distributed as is, without any warranty\r\n**                of any kind.\r\n**\r\n**  (c)Copyright Atollic AB.\r\n**  You may use this file as-is or modify it according to the needs of your\r\n**  project. This file may only be built (assembled or compiled and linked)\r\n**  using the Atollic TrueSTUDIO(R) product. The use of this file together\r\n**  with other tools than Atollic TrueSTUDIO(R) is not permitted.\r\n**\r\n*****************************************************************************\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\n\/* Highest address of the user mode stack *\/\r\n_estack = 0x20009FFF;    \/* end of RAM *\/\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 256K\r\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 40K\r\nCCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 8K\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    __isr_vector = .;\r\n    KEEP(*(.isr_vector)) \/* Startup code *\/\r\n    __isr_vector_end = .;\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  \/* The program code and other data goes into FLASH *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)           \/* .text sections (code) *\/\r\n    *(.text*)          \/* .text* sections (code) *\/\r\n    *(.glue_7)         \/* glue arm to thumb code *\/\r\n    *(.glue_7t)        \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;        \/* define a global symbols at end of code *\/\r\n  } >FLASH\r\n\r\n  \/* Constant data goes into FLASH *\/\r\n  .rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n  .ARM : {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } >FLASH\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } >FLASH\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } >FLASH\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } >FLASH\r\n\r\n  \/* used by the startup to initialize data *\/\r\n  _sidata = LOADADDR(.data);\r\n\r\n  .vector_relocation :\r\n  {\r\n     . = ALIGN(4);\r\n     __vector_tbl_reloc__ = .;\r\n     . = . + (__isr_vector_end - __isr_vector);\r\n     . = ALIGN(4);\r\n  } > RAM\r\n\r\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\r\n  .data : \r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .;        \/* create a global symbol at data start *\/\r\n    *(.data)           \/* .data sections *\/\r\n    *(.data*)          \/* .data* sections *\/\r\n\r\n    . = ALIGN(4);\r\n    _edata = .;        \/* define a global symbol at data end *\/\r\n  } >RAM AT> FLASH\r\n\r\n  _siccmram = LOADADDR(.ccmram);\r\n\r\n  \/* CCM-RAM section \r\n  * \r\n  * IMPORTANT NOTE! \r\n  * If initialized variables will be placed in this section, \r\n  * the startup code needs to be modified to copy the init-values.  \r\n  *\/\r\n  .ccmram :\r\n  {\r\n    . = ALIGN(4);\r\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\r\n    *(.ccmram)\r\n    *(.ccmram*)\r\n    \r\n    . = ALIGN(4);\r\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\r\n  } >CCMRAM AT> FLASH\r\n\r\n  \r\n  \/* Uninitialized data section *\/\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n    _sbss = .;         \/* define a global symbol at bss start *\/\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .;         \/* define a global symbol at bss end *\/\r\n    __bss_end__ = _ebss;\r\n  } >RAM\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(4);\r\n  } >RAM\r\n\r\n  \r\n\r\n  \/* Remove information from the standard libraries *\/\r\n  \/DISCARD\/ :\r\n  {\r\n    libc.a ( * )\r\n    libm.a ( * )\r\n    libgcc.a ( * )\r\n  }\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"aef3cfc332de2b3308c3c001e0bd1687893d345d","subject":"soc: nxp_imx-rt: Convert to new dt macros in linker.ld","message":"soc: nxp_imx-rt: Convert to new dt macros in linker.ld\n\nConvert ocram and sdram regions to use new macro DT_REG_ADDR() and\nDT_REG_SIZE() with DT_NODELABEL to determine the various memories size\nand base address.\n\nSigned-off-by: Kumar Gala <a5e5248af4cd4f0ed8c515f61d40a6e2db46a66e@linaro.org>\n","repos":"finikorg\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/arm\/nxp_imx\/rt\/linker.ld","new_file":"soc\/arm\/nxp_imx\/rt\/linker.ld","new_contents":"\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n #include <autoconf.h>\n #include <devicetree.h>\n\nMEMORY\n     {\n#if (DT_REG_SIZE(DT_NODELABEL(ocram)) > 0) && !defined(CONFIG_DATA_OCRAM)\n        OCRAM  (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ocram)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ocram))\n#endif\n#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !defined(CONFIG_DATA_SEMC)\n        SDRAM  (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_ADDR(DT_NODELABEL(sdram0))\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm)) > 0) && !defined(CONFIG_DATA_DTCM)\n        DTCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_dtcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm))\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_itcm)) > 0) && !defined(CONFIG_CODE_ITCM)\n        ITCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_itcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_itcm))\n#endif\n     }\n\n#include <arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld>\n","old_contents":"\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n #include <autoconf.h>\n #include <devicetree.h>\n\nMEMORY\n     {\n#if (DT_MMIO_SRAM_20200000_SIZE > 0) && !defined(CONFIG_DATA_OCRAM)\n        OCRAM  (wx) : ORIGIN = DT_MMIO_SRAM_20200000_BASE_ADDRESS, LENGTH = DT_MMIO_SRAM_20200000_SIZE\n#endif\n#if (DT_MMIO_SRAM_80000000_SIZE > 0) && !defined(CONFIG_DATA_SEMC)\n        SDRAM  (wx) : ORIGIN = DT_MMIO_SRAM_80000000_BASE_ADDRESS, LENGTH = DT_MMIO_SRAM_80000000_SIZE\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm)) > 0) && !defined(CONFIG_DATA_DTCM)\n        DTCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_dtcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm))\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_itcm)) > 0) && !defined(CONFIG_CODE_ITCM)\n        ITCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_itcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_itcm))\n#endif\n     }\n\n#include <arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld>\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"96facde2d5b04577ab41caa30bf6549dc7a64276","subject":"Fix bullshit in the linker script","message":"Fix bullshit in the linker script\n\nThe \u201cld: error: no memory region specified for loadable section `.bss\u2019\u201d\nproblem was literally because the section was misnamed in the script.\n\nAnd guess what, if we fix .data as well then static variable initialization\nactually works. Hooray for another class-wide misdiagnosis\u2026","repos":"ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme","old_file":"orex.ld","new_file":"orex.ld","new_contents":"ENTRY (main)\n\nMEMORY\n{\n\tram : ORIGIN = 0x00218000, LENGTH = 29M\n\trom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n\t.data : \/* Initialized data. *\/\n\t{\n\t\t_DataStart = . ;\n\t\t*(.data)\n\t\t_DataEnd = . ;\n\t} >ram\n\n\t.bss : \/* Uninitialized data. *\/\n\t{\n\t\t_BssStart = . ;\n\t\t*(.bss)\n\t\t_BssEnd = . ;\n\t} >ram\n\n\t.text : \/* The actual instructions. *\/\n\t{\n\t\t*(.text)\n\t\t*(.got)\n\t\t*(.got.plt)\n\t\t*(.rodata)\n\t\t*(.rodata.str1.4)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t} >ram\n}\n","old_contents":"ENTRY (main)\n\nMEMORY\n{\n\tram : ORIGIN = 0x00218000, LENGTH = 29M\n\trom : ORIGIN = 0x60000000, LENGTH = 8M\n}\n\nSECTIONS\n{\n\tdata : \/* Initialized data. *\/\n\t{\n\t\t_DataStart = . ;\n\t\t*(.data)\n\t\t_DataEnd = . ;\n\t} >ram\n\n\tbss : \/* Uninitialized data. *\/\n\t{\n\t\t_BssStart = . ;\n\t\t*(.bss)\n\t\t_BssEnd = . ;\n\t} >ram\n\n\ttext : \/* The actual instructions. *\/\n\t{\n\t\t*(.text)\n\t\t*(.got)\n\t\t*(.got.plt)\n\t\t*(.rodata)\n\t\t*(.rodata.str1.4)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t} >ram\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c6bf55aadbad9084148c9598af8f44d474295b09","subject":"do not discard .rodata","message":"do not discard .rodata\n","repos":"linkuri267\/mikaos","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"\/******************************************************************************\n*\tkernel.ld\n*\t by Alex Chadwick\n*\n*\tA linker script for generation of raspberry pi kernel images, with C\n*\tcode.\n******************************************************************************\/\n\nSECTIONS {\n\t\/*\n\t* First and formost we need the .init section, containing the code to \n        * be run first. We allow room for the ATAGs and stack and conform to \n        * the bootloader's expectation by putting this code at 0x8000.\n\t*\/\n\t.init 0x8000 : {\n\t\t*(.init)\n\t}\n\t\n\t\n\t\/* \n\t* Next we put the data.\n\t*\/\n\t.data : {\n\t\t*(.data)\n\t\t*.c.o(*)\n\t}\n\t\n\t.rodata : {\n\t\t*(.rodata)\n\t}\n\t\n\t\/* \n\t* Next we put the rest of the code.\n\t*\/\n\t.text : {\n\t\t*.c.o(.text)\n\t\t*(.text)\n\t}\n\n\t\/*\n\t* Finally comes everything else. A fun trick here is to put all other \n\t* sections into this section, which will be discarded by default.\n\t*\/\n\t\/DISCARD\/ : {\n\t\t*(*)\n\t}\n}\n","old_contents":"\/******************************************************************************\n*\tkernel.ld\n*\t by Alex Chadwick\n*\n*\tA linker script for generation of raspberry pi kernel images, with C\n*\tcode.\n******************************************************************************\/\n\nSECTIONS {\n\t\/*\n\t* First and formost we need the .init section, containing the code to \n        * be run first. We allow room for the ATAGs and stack and conform to \n        * the bootloader's expectation by putting this code at 0x8000.\n\t*\/\n\t.init 0x8000 : {\n\t\t*(.init)\n\t}\n\t\n\t\/* \n\t* Next we put the data.\n\t*\/\n\t.data : {\n\t\t*(.data)\n\t\t*.c.o(*)\n\t}\n\t\n\t\/* \n\t* Next we put the rest of the code.\n\t*\/\n\t.text : {\n\t\t*.c.o(.text)\n\t\t*(.text)\n\t}\n\n\t\/*\n\t* Finally comes everything else. A fun trick here is to put all other \n\t* sections into this section, which will be discarded by default.\n\t*\/\n\t\/DISCARD\/ : {\n\t\t*(*)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"41967f999f31a2875d01c8795a8c759baeda08be","subject":"esp32: workaround esptool linker sections limit","message":"esp32: workaround esptool linker sections limit\n\nWhen converting ELF to a flashable image, the esptool can only\nprocess up to 16 ELF sections. Zephyr has been happily grouping\nsimilar objects into linker sections which can easily go over\nesptool's limit. This patch consolidates the kernel, net, log,\nand shell objects into their own sections.\n\nAlso remove the app_noinit section as no one is emitting\nanything into that section, and it's not being used by other\narch\/SoC\/boards in Zephyr.\n\nFixes #20980\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define ROMABLE_REGION iram0_0_seg :iram0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = 0x4000681c );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  iram0_2_seg(RX): org = 0x400D0018, len = 0x330000\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x50000\n  drom0_0_seg(R): org = 0x3F400010, len = 0x800000\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  iram0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  SECTION_DATA_PROLOGUE(log_static_section,,)\n  {\n    __log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __log_const_end = .;\n\n    __log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __log_backends_end = .;\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(shell_static_section,,)\n {\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __shell_root_cmds_end = .;\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(4))\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define ROMABLE_REGION iram0_0_seg :iram0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = 0x4000681c );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  iram0_2_seg(RX): org = 0x400D0018, len = 0x330000\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x50000\n  drom0_0_seg(R): org = 0x3F400010, len = 0x800000\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  iram0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n#include <linker\/common-rom.ld>\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(4))\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n\n   SECTION_DATA_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD),)\n   {\n     . = ALIGN (8);\n     *(.app_noinit)\n     *(\"app_noinit.*\")\n     . = ALIGN (8);\n    _app_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"73be85dd6d7d1dfd8f450bd00cbf96f67f95be02","subject":"nrf52\/boards: Increasing the stack and heap in pca10056 (nrf52840) target from 2k\/32k to 40k\/128k to debug some buffer problems when running large frozen python programs.","message":"nrf52\/boards: Increasing the stack and heap in pca10056 (nrf52840) target from 2k\/32k to 40k\/128k to debug some buffer problems when running large frozen python programs.\n","repos":"tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,tralamazza\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython","old_file":"nrf5\/boards\/nrf52840_aa.ld","new_file":"nrf5\/boards\/nrf52840_aa.ld","new_contents":"\/*\n    GNU linker script for NRF52840 blank w\/ no SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x0FF000 \/* 1020 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x040000 \/* 256 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 40K;\n_minimum_heap_size = 128K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52840 blank w\/ no SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x0FF000 \/* 1020 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x040000 \/* 256 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 32K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20008000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ce6dd9de27a926e77e275de0287ee36fce93ce7f","subject":"Correct terminology in kernel.ld","message":"Correct terminology in kernel.ld\n","repos":"KushOza\/hw2,tehgeekmeister\/xv6,AskDrCatcher\/xv6,gw\/xv6,SajadAzami\/xv6-pm,shtyd\/xv6-lua,prashantkhurana\/OS,yum185\/assign1_partA,romanzhg\/xv6,liyinhgqw\/xv6,Mifnight\/xv6-public,MrHohn\/cs518hw2,myl2821\/xv6-fork,run\/xv6,Royvaknin29\/OS_Ass1,vicionator\/XV6,logangorence\/xv6-public,wkatsak\/xv6,liorderei\/OS_Class,bowlofstew\/xv6-public,sometimesfood\/xv6-public,prashantkhurana\/OS,shining-yang\/xv6,Cealestus\/cmpt332Assignment1,juroland\/xv6,lorenzo-stoakes\/haxv6,chnpmy\/xv6,ManaPoustizadeh\/OS-finalProject,nomadium\/xv6,siddharthv\/xv6,chnpmy\/xv6,jmatth\/xv6,DuskDragon\/xv6,niral28\/hw1,svdamani\/xv6,forwchen\/xv6,garzon\/xv6-public,MrHohn\/cs518hw2,bngabonziza\/xv6-public,lenw\/xv6-public,liorderei\/OS_Class,SajadAzami\/xv6-pm,arianvp\/xv6,Y-liulian\/xv6-public,Cheukyin\/xv6,i\/xv6,leenjewel\/xv6_learn,justodiaz\/xv6,sdimitro\/xv6,baboofei\/v6rt,romanzhg\/xv6,Raysmond\/xv6,avana002\/xv6,CKost\/Authorization,alex0906093\/xv6,kongming92\/6828-xv6,supdizh\/clean_xv6,fintler\/xv6,SanchayanMaity\/xv6-cs450,tehgeekmeister\/xv6,lishuwnc\/Xv6,HugoTian\/xv6,pelhamnicholas\/xv6,lishuwnc\/Xv6,baboofei\/v6rt,xv6-jp\/xv6,TheDude05\/xv6,voytovichs\/xv6-public,imagine4077\/xv6-public,jsommers\/xv6-public,penguiner\/xv6,bowlofstew\/xv6-public,walafc0\/xv6,seckcoder\/mirror-xv6,UIKit0\/Xv6,AskDrCatcher\/xv6,gburd\/xv6,logangorence\/xv6-public,OrangeTide\/xv6-public,chnpmy\/xv6,Mifnight\/xv6-public,davidbalbert\/xv6,film42\/xv6,gco\/xv6,wasabiz\/xv6,DuskDragon\/xv6,bowlofstew\/xv6-public,gmy987\/xv6,tamlok\/xv6,gnosis23\/xv6,ihciah\/xv6,danrods\/xv6Hacks,supdizh\/clean_xv6,MrHohn\/CS-OperatingSystem-hw2,humphreyja\/Xv6,galbenor\/os162-4,romanzhg\/xv6,t3rm1n4l\/xv6,tlerea1\/xv6,UIKit0\/Xv6,guilleiguaran\/xv6,tehgeekmeister\/xv6,nwf\/xv6-public,gw\/xv6,svdamani\/xv6,WeiranFang\/cs518hw3,lord021\/Assignment1,bngabonziza\/xv6-public,siddharthv\/xv6,jsommers\/xv6-public,jeffallen\/xv6,jgome043\/tearos,louisje\/xv6,ManaPoustizadeh\/OS-finalProject,PINK-FL0YD\/xv6-public,lorenzo-stoakes\/haxv6,sometimesfood\/xv6,meilank\/CS416-hw2,robertpd\/xv6,danrods\/xv6Hacks,wangxiayang\/xv6,gburd\/xv6,aquamme\/xv6,MrHohn\/cs518hw3,emaadmanzoor\/xv6,juroland\/xv6,nrahimi\/xv6,raman162\/CS450,galbenor\/os162-4,sdimitro\/xv6,Laaia\/RT-xv6,shyandsy\/xv6,rajma996\/xv6,HugoTian\/xv6,lenw\/xv6-public,WeiranFang\/cs518hw3,emaadmanzoor\/xv6,KushOza\/hw2,AZQ1994\/xv6,ThomasDq\/xv6OS,ThomasDq\/xv6OS,robertpd\/xv6,danluu\/Xv6,avana002\/xv6,konyavic\/xv6,sometimesfood\/xv6-public,Cheukyin\/xv6,sometimesfood\/xv6-public,pablogventura\/xv6-public,lord021\/Assignment2,fintler\/xv6,gmy987\/xv6,louisje\/xv6,danluu\/Xv6,film42\/xv6,liorderei\/OS_Class,UIKit0\/xv6-1,voytovichs\/xv6-public,tamlok\/xv6,robertpd\/xv6,shtyd\/xv6-lua,pekopeko1\/xv6-code,descent\/xv6,WeiranFang\/cs518hw3,yum185\/assign1_partA,nwf\/xv6-public,pablogventura\/xv6-public,wangxiayang\/xv6,arturosevilla\/xv6-turi,guilleiguaran\/xv6,prashantkhurana\/OS,xujunhai1991\/xv6,guilleiguaran\/xv6,SanchayanMaity\/xv6-cs450,forwchen\/xv6,liadgi\/os163,sigma-random\/xv6,codelabs-ch\/xv6-muen,TheMatrixShibe\/tmsv6,CHRISTOPHERDIEHL\/xv6,pekopeko1\/xv6-code,logangorence\/xv6-public,firstblade\/xv6,yubai\/ksm_xv6,alex0906093\/xv6,wangxiayang\/xv6,liyinhgqw\/xv6,raman162\/CS450,gw\/xv6,ZheyuJin\/xv6_reading,phf\/xv6-public,AndreiRO\/xv6,MrHohn\/CS-OperatingSystem-hw2,fintler\/xv6,williamsandrew\/xv6,ThomasDq\/xv6OS,phf\/xv6-public,seckcoder\/mirror-xv6,vicionator\/XV6,MrHohn\/CS-OperatingSystem-hw3,CHRISTOPHERDIEHL\/xv6,pekopeko1\/xv6,gzpan123\/xv6,khalily\/xv6,nrahimi\/xv6,oskarth\/xv6,ManaPoustizadeh\/OS-finalProject,bngabonziza\/xv6,garzon\/xv6-public,run\/xv6,preshshah\/xv6,codelabs-ch\/xv6-muen,OrangeTide\/xv6-public,justodiaz\/xv6,jmatth\/xv6,oskarth\/xv6,preshshah\/xv6,cpehle\/xv6,humphreyja\/Xv6,AskDrCatcher\/xv6,shyandsy\/xv6,UIKit0\/xv6-1,orenherman\/xv6-clone,orenherman\/xv6-clone,Cealestus\/cmpt332Assignment1,RicardoParizotto\/xv6---stride-scheduling,Mifnight\/xv6-public,kongming92\/6828-xv6,jsommers\/xv6-public,penguiner\/xv6,Cheukyin\/xv6,HawxChen\/Offical-Version-xv6,Y-liulian\/xv6-public,f13mash\/xv6,ZheyuJin\/xv6_reading,arianvp\/xv6,ShakhMoves\/Shakh6,nwolovick\/xv6-public,shadowfax-ring\/mit-xv6,ShakhMoves\/Shakh6,ShakhMoves\/Shakh6,jsommers\/xv6-public,PINK-FL0YD\/xv6-public,GautamV\/xv6,bohaoist\/xv6,techno\/xv6-mist32,expertsnipo\/xv6,varunk08\/xv6,sigma-random\/xv6,myl2821\/xv6-fork,junxu\/xv6,supdizh\/clean_xv6,SarthakCodes\/xv6,ckkashyap\/xv6,gmy987\/xv6,roygoldman\/xv6-fsprot,ShakhMoves\/Shakh6,garzon\/xv6-public,svdamani\/xv6,techno\/xv6-mist32,roygoldman\/xv6-sem,nrahimi\/xv6,pablogventura\/xv6-public,ihciah\/XV6-OS,tenstep\/xv6,ahorn\/xv6,penguiner\/xv6,shyandsy\/xv6,bohaoist\/xv6,chrisdew\/xv6,supr\/Xv6,roygoldman\/xv6-fsprot,GautamV\/xv6,gco\/xv6,KushOza\/hw2,gburd\/xv6,nwolovick\/xv6-public,Laaia\/RT-xv6,dswann5\/os_assignment_3,humphreyja\/Xv6,5kg\/xv6,sdharan\/xv6-rcu,MrHohn\/CS-OperatingSystem-hw2,gburd\/xv6,louisje\/xv6,AskDrCatcher\/xv6,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odes\/xv6,williamsandrew\/xv6,sometimesfood\/xv6,bohaoist\/xv6,f13mash\/xv6,film42\/xv6,seckcoder\/mirror-xv6,supdizh\/clean_xv6,arajago6\/Axv6_One,nwolovick\/xv6-public,howerj\/xv6,bngabonziza\/xv6-1,williamsandrew\/xv6,jmatth\/xv6,siddharthv\/xv6,s-rah\/xv6-permissions,gnudeep\/xv6,rlok3000\/xv6,descent\/xv6,gnosis23\/xv6,pekopeko1\/xv6,humphreyja\/Xv6,t3rm1n4l\/xv6,eewayhsu\/xv6,firstblade\/xv6,gnudeep\/xv6,sdharan\/xv6-rcu,garzon\/xv6,shtyd\/xv6-lua,rafamanzo\/ep4-so,phf\/xv6-public,TheMatrixShibe\/tmsv6,kingsizeme\/xv6,ihciah\/XV6-OS,SanchayanMaity\/xv6-cs450,meilank\/CS416-hw1,AZQ1994\/xv6,nullpo-head\/xv6-mips,yum185\/assign1_partA,rafamanzo\/ep2-so-xv6,meilank\/CS416-hw1,siddharthv\/xv6,TheDude05\/xv6,HawxChen\/Offical-Version-xv6,orenherman\/xv6-clone,laisborin\/RT-xv6,Raysmond\/xv6,lorenzo-stoakes\/haxv6,CKost\/Authorization,lorenzo-stoakes\/haxv6,raman162\/CS450,meilank\/CS416-hw2,vicionator\/XV6,danluu\/Xv6,seckcoder\/mirror-xv6,CKost\/Authorization,konyavic\/xv6,justodiaz\/xv6,rlok3000\/xv6,rafamanzo\/ep2-so-xv6,nwf\/xv6-public,CHRISTOPHERDIEHL\/xv6,HugoTian\/xv6,garzon\/xv6,tinti\/xv6-ubuntu,rafamanzo\/ep2-so-xv6,nomadium\/xv6,rafamanzo\/ep4-so,pekopeko1\/xv6,chyka-dev\/xv6-public,lord021\/Assignment1,sdimitro\/xv6,myl2821\/xv6-fork,MrHohn\/CS-OperatingSystem-hw3,t3rm1n4l\/xv6,gnudeep\/xv6,bngabonziza\/xv6-1,panks\/Xv6,aquamme\/xv6,cpehle\/xv6,danluu\/Xv6,niral28\/hw1,davidbalbert\/xv6,lishuwnc\/Xv6,gnosis23\/xv6,emaadmanzoor\/xv6,arcbbb\/xv6,lenw\/xv6-public,meilank\/CS416-hw1,t3rm1n4l\/xv6,arturosevilla\/xv6-turi,sometimesfood\/xv6,tlerea1\/xv6,gw\/xv6,MatanGilead\/myxv6,Cheukyin\/xv6,dswann5\/os_assignment_3,gw\/xv6,5kg\/xv6,khalily\/xv6,prashantkhurana\/OS,film42\/xv6,sdimitro\/xv6,gnudeep\/xv6,yum185\/assign1_partA,msyksphinz\/xv6-mips,pelhamnicholas\/xv6,aquamme\/xv6,yubai\/ksm_xv6,bngabonziza\/xv6-public,TheMatrixShibe\/tmsv6,ZheyuJin\/xv6_reading,Y-liulian\/xv6-public,leenjewel\/xv6_learn,tlerea1\/xv6,tinti\/xv6-ubuntu,lolosssss\/Xv6,rafamanzo\/ep4-so,voytovichs\/xv6-public,nomadium\/xv6,sometimesfood\/xv6,lord021\/Assignment2,chrisdew\/xv6,svdamani\/xv6,SajadAzami\/xv6-pm,xv6-jp\/xv6,i\/xv6,shyandsy\/xv6,wenhuizhang\/xv6-public,reutz19\/xv6_ass4,descent\/xv6,liyinhgqw\/xv6,bngabonziza\/xv6,juroland\/xv6,shtyd\/xv6-lua,davidbalbert\/xv6,ahorn\/xv6,kingsizeme\/xv6,kazunobu-fujii\/xv6,wkatsak\/xv6","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"\/* Simple linker script for the JOS kernel.\n   See the GNU ld 'info' manual (\"info ld\") to learn the syntax. *\/\n\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSECTIONS\n{\n\t\/* Link the kernel at this address: \".\" means the current address *\/\n        \/* Must be equal to KERNLINK *\/\n\t. = 0x80100000;\n\n\t.text : AT(0x100000) {\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t}\n\n\tPROVIDE(etext = .);\t\/* Define the 'etext' symbol to this value *\/\n\n\t.rodata : {\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t}\n\n\t\/* Include debugging information in kernel memory *\/\n\t.stab : {\n\t\tPROVIDE(__STAB_BEGIN__ = .);\n\t\t*(.stab);\n\t\tPROVIDE(__STAB_END__ = .);\n\t\tBYTE(0)\t\t\/* Force the linker to allocate space\n\t\t\t\t   for this section *\/\n\t}\n\n\t.stabstr : {\n\t\tPROVIDE(__STABSTR_BEGIN__ = .);\n\t\t*(.stabstr);\n\t\tPROVIDE(__STABSTR_END__ = .);\n\t\tBYTE(0)\t\t\/* Force the linker to allocate space\n\t\t\t\t   for this section *\/\n\t}\n\n\t\/* Adjust the address for the data segment to the next page *\/\n\t. = ALIGN(0x1000);\n\n\t\/* The data segment *\/\n\t.data : {\n\t\t*(.data)\n\t}\n\n\tPROVIDE(edata = .);\n\n\t.bss : {\n\t\t*(.bss)\n\t}\n\n\tPROVIDE(end = .);\n\n\t\/DISCARD\/ : {\n\t\t*(.eh_frame .note.GNU-stack)\n\t}\n}\n","old_contents":"\/* Simple linker script for the JOS kernel.\n   See the GNU ld 'info' manual (\"info ld\") to learn the syntax. *\/\n\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSECTIONS\n{\n\t\/* Load the kernel at this address: \".\" means the current address *\/\n        \/* Must be equal to KERNLINK *\/\n\t. = 0x80100000;\n\n\t.text : AT(0x100000) {\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t}\n\n\tPROVIDE(etext = .);\t\/* Define the 'etext' symbol to this value *\/\n\n\t.rodata : {\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t}\n\n\t\/* Include debugging information in kernel memory *\/\n\t.stab : {\n\t\tPROVIDE(__STAB_BEGIN__ = .);\n\t\t*(.stab);\n\t\tPROVIDE(__STAB_END__ = .);\n\t\tBYTE(0)\t\t\/* Force the linker to allocate space\n\t\t\t\t   for this section *\/\n\t}\n\n\t.stabstr : {\n\t\tPROVIDE(__STABSTR_BEGIN__ = .);\n\t\t*(.stabstr);\n\t\tPROVIDE(__STABSTR_END__ = .);\n\t\tBYTE(0)\t\t\/* Force the linker to allocate space\n\t\t\t\t   for this section *\/\n\t}\n\n\t\/* Adjust the address for the data segment to the next page *\/\n\t. = ALIGN(0x1000);\n\n\t\/* The data segment *\/\n\t.data : {\n\t\t*(.data)\n\t}\n\n\tPROVIDE(edata = .);\n\n\t.bss : {\n\t\t*(.bss)\n\t}\n\n\tPROVIDE(end = .);\n\n\t\/DISCARD\/ : {\n\t\t*(.eh_frame .note.GNU-stack)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"51b4b5e82f473f3eff5769d5c538739f0770f1cd","subject":"catch stack overflows; heap symbol","message":"catch stack overflows; heap symbol\n","repos":"CRust-OS\/CRust-OS,CRust-OS\/CRust-OS,CRust-OS\/CRust-OS,CRust-OS\/CRust-OS","old_file":"crust.lds","new_file":"crust.lds","new_contents":"ENTRY(_start)\n\n\/* all sections are padded with 0xCC (int 3, meaning breakpoint) in case we accidentally jump into uninitialized memory *\/\n\nSECTIONS {\n    .bss : ALIGN(0x1000) {\n        STACK_TOP = .;\n        . += 0x2000;\n        STACK_BOTTOM = .;\n        HYPERCALL_PAGE = .;\n        . += 0x1000;\n        *(.bss);\n        *(.bss.*);\n    } = 0xCC \n    .text : {\n        *(.text);\n        *(.text.*);\n    } = 0xCC\n    .data : {\n        *(.data);\n        *(.data.*);\n    } = 0xCC\n    .note : {\n        *(.note.Xen);\n    }\n    HEAP = .;\n}\n","old_contents":"ENTRY(_start)\n\n\/* all sections are padded with 0xCC (int 3, meaning breakpoint) in case we accidentally jump into uninitialized memory *\/\n\nSECTIONS {\n    .bss : ALIGN(0x1000) {\n        HYPERCALL_PAGE = .;\n        . += 0x1000;\n        STACK_TOP = .;\n        . += 0x2000;\n        STACK_BOTTOM = .;\n        *(.bss);\n        *(.bss.*);\n    } = 0xCC \n    .text : {\n        *(.text);\n        *(.text.*);\n    } = 0xCC\n    .data : {\n        *(.data);\n        *(.data.*);\n    } = 0xCC\n    .note : {\n        *(.note.Xen);\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"9c3c15f74e07f3e90ab94fd7d5f76b3fd84740f9","subject":"remove file that was moved","message":"remove file that was moved\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"applications\/bootloader\/targets\/nonos.xtensa.esp8266.bracz-deadrail\/bload_target.ld","new_file":"applications\/bootloader\/targets\/nonos.xtensa.esp8266.bracz-deadrail\/bload_target.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"658d89be8cfe9def5c86dbeb8c684aef0c08d5e5","subject":"Apply linker fix as in #12690 to new NUCLEO_G474RE target","message":"Apply linker fix as in #12690 to new NUCLEO_G474RE target\n","repos":"mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed","old_file":"targets\/TARGET_STM\/TARGET_STM32G4\/TARGET_STM32G474xx\/TOOLCHAIN_GCC_ARM\/stm32g474xx.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32G4\/TARGET_STM32G474xx\/TOOLCHAIN_GCC_ARM\/stm32g474xx.ld","new_contents":"\/* Linker script to configure memory regions. *\/\n\/*\n * SPDX-License-Identifier: BSD-3-Clause\n ******************************************************************************\n * @attention\n *\n * Copyright (c) 2016-2020 STMicroelectronics.\n * All rights reserved.\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n *                        opensource.org\/licenses\/BSD-3-Clause\n *\n ******************************************************************************\n*\/\n\n#include \"..\/cmsis_nvic.h\"\n\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START  MBED_ROM_START\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE  MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    \/* This value is normally defined by the tools\n       to 0x1000 for bare metal and 0x400 for RTOS *\/\n    #define MBED_BOOT_STACK_SIZE  0x400\n#endif\n\n\/* Round up VECTORS_SIZE to 8 bytes *\/\n#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)\n\nMEMORY\n{\n    FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n    RAM (rwx)    : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    \/* Uninitialized data section\n     * This region is not initialized by the C\/C++ library and can be used to\n     * store state across soft reboots. *\/\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        PROVIDE(end = .);\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\/*\n * SPDX-License-Identifier: BSD-3-Clause\n ******************************************************************************\n * @attention\n *\n * Copyright (c) 2016-2020 STMicroelectronics.\n * All rights reserved.\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n *                        opensource.org\/licenses\/BSD-3-Clause\n *\n ******************************************************************************\n*\/\n\n#include \"..\/cmsis_nvic.h\"\n\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START  MBED_ROM_START\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE  MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    \/* This value is normally defined by the tools\n       to 0x1000 for bare metal and 0x400 for RTOS *\/\n    #define MBED_BOOT_STACK_SIZE  0x400\n#endif\n\n\/* Round up VECTORS_SIZE to 8 bytes *\/\n#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)\n\nMEMORY\n{\n    FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n    RAM (rwx)    : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    \/* Location counter can end up 2byte aligned with narrow Thumb code but\n       __etext is assumed by startup code to be the LMA of a section in RAM\n       which must be 8-byte aligned *\/\n    __etext = ALIGN (8);\n    _sidata = .;\n    \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    \/* Uninitialized data section\n     * This region is not initialized by the C\/C++ library and can be used to\n     * store state across soft reboots. *\/\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        PROVIDE(end = .);\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6f6dc835d2c9a6080a58fb0164b9b0914e0b652b","subject":"litex: Use FLASH_FIRMWARE instead of FLASH in linker scripts","message":"litex: Use FLASH_FIRMWARE instead of FLASH in linker scripts\n\nfor compatibility with the build_memory_info script\n","repos":"adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython","old_file":"ports\/litex\/boards\/fomu\/fomu-spi.ld","new_file":"ports\/litex\/boards\/fomu\/fomu-spi.ld","new_contents":"\/*\n    GNU linker script for Fomu\n*\/\n\nENTRY(_start)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x20040000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_FIRMWARE (rx)      : ORIGIN = 0x20040000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    RAM (xrw)       : ORIGIN = 0x10000000, LENGTH = 0x00020000 \/* 128 KiB *\/\n}\n\n\/* top end of the stack *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :  AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n\n        *(.itcm.*)         \/* Instruction Tightly Coupled Memory *\/\n        *(.dtcm_data.*)    \/* Data Tightly Coupled Memory *\/\n\n        *(.text.cmp_lfn)\n        *(.text.qstr_find_strn)\n        *(.text.dcd_edpt_xfer)\n        *(.text.pop_rule)\n        *(.text.ff_wtoupper)\n        *(.text.dir_find)\n        *(.text.push_rule)\n        *(.text.csr_writel)\n        *(.text.csr_readl)\n        *(.text.timer0_ev_pending_write)\n        *(.text.autoreload_tick)\n        *(.text.filesystem_tick)\n        *(.text.usb_background)\n\n        *(.text.dcd_*)\n        *(.text.tud_control_*)\n        *(.text.tud_cdc_n_write_flush)\n        *(.text.tud_task)\n        *(.text.tu_edpt_dir)\n        *(.text.tu_fifo_empty)\n        *(.text.usbd_edpt_busy)\n        *(.text.irq_getmask)\n        *(.text.irq_setmask)\n        *(.text.irq_pending)\n        *(.text._osal_q_lock)\n        *(.text.osal_queue_receive)\n\n        *(.text.mp_obj_get_type)\n        *(.text.mp_parse)\n        *(.text.parse_compile_execute)\n        *(.text.mp_map_lookup)\n        *(.text.mp_execute_bytecode) \/* Note: this function is 7kb *\/\n\n        *(.ramtext)        \/* .text* sections (code) *\/\n        *(.ramtext*)       \/* .text* sections (code) *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n        *(.sdata)          \/* .data sections *\/\n        *(.sdata*)         \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* The program code and other data goes into FLASH_FIRMWARE *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.text.start)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        *(.srodata)        \/* .rodata sections (constants, strings, etc.) *\/\n        *(.srodata*)       \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH_FIRMWARE\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(.dtcm_bss.*)     \/* Data Tightly Coupled Memory *\/\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n    } >RAM\n}\n","old_contents":"\/*\n    GNU linker script for Fomu\n*\/\n\nENTRY(_start)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x20040000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    RAM (xrw)       : ORIGIN = 0x10000000, LENGTH = 0x00020000 \/* 128 KiB *\/\n}\n\n\/* top end of the stack *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :  AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n\n        *(.itcm.*)         \/* Instruction Tightly Coupled Memory *\/\n        *(.dtcm_data.*)    \/* Data Tightly Coupled Memory *\/\n\n        *(.text.cmp_lfn)\n        *(.text.qstr_find_strn)\n        *(.text.dcd_edpt_xfer)\n        *(.text.pop_rule)\n        *(.text.ff_wtoupper)\n        *(.text.dir_find)\n        *(.text.push_rule)\n        *(.text.csr_writel)\n        *(.text.csr_readl)\n        *(.text.timer0_ev_pending_write)\n        *(.text.autoreload_tick)\n        *(.text.filesystem_tick)\n        *(.text.usb_background)\n\n        *(.text.dcd_*)\n        *(.text.tud_control_*)\n        *(.text.tud_cdc_n_write_flush)\n        *(.text.tud_task)\n        *(.text.tu_edpt_dir)\n        *(.text.tu_fifo_empty)\n        *(.text.usbd_edpt_busy)\n        *(.text.irq_getmask)\n        *(.text.irq_setmask)\n        *(.text.irq_pending)\n        *(.text._osal_q_lock)\n        *(.text.osal_queue_receive)\n\n        *(.text.mp_obj_get_type)\n        *(.text.mp_parse)\n        *(.text.parse_compile_execute)\n        *(.text.mp_map_lookup)\n        *(.text.mp_execute_bytecode) \/* Note: this function is 7kb *\/\n\n        *(.ramtext)        \/* .text* sections (code) *\/\n        *(.ramtext*)       \/* .text* sections (code) *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n        *(.sdata)          \/* .data sections *\/\n        *(.sdata*)         \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.text.start)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        *(.srodata)        \/* .rodata sections (constants, strings, etc.) *\/\n        *(.srodata*)       \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(.dtcm_bss.*)     \/* Data Tightly Coupled Memory *\/\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n    } >RAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"1c26cc577e052c5caa540d06d72ca7dc78c1b621","subject":"","message":"\n\ngit-svn-id: https:\/\/chibios.svn.sourceforge.net\/svnroot\/chibios\/trunk@3199 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"demos\/ARMCM3-STM32F100-DISCOVERY\/ch.ld","new_file":"demos\/ARMCM3-STM32F100-DISCOVERY\/ch.ld","new_contents":"","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * ST32F100xB memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0400;\r\n__process_stack_size__  = 0x0400;\r\n__stacks_total_size__   = __main_stack_size__ + __process_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x08000000, len = 128k\r\n    ram : org = 0x20000000, len = 8k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n    . = 0;\r\n    _text = .;\r\n\r\n    startup : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        KEEP(*(vectors))\r\n    } > flash\r\n\r\n    constructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE(__init_array_end = .);\r\n    } > flash\r\n\r\n    destructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__fini_array_start = .);\r\n        KEEP(*(.fini_array))\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        PROVIDE(__fini_array_end = .);\r\n    } > flash\r\n\r\n    .text : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        *(.text.startup.*)\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n    } > flash\r\n\r\n    .ARM.extab :\r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > flash\r\n\r\n    .ARM.exidx : {\r\n        PROVIDE(__exidx_start = .);\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n        PROVIDE(__exidx_end = .);\r\n     } > flash\r\n\r\n    .eh_frame_hdr :\r\n    {\r\n        *(.eh_frame_hdr)\r\n    } > flash\r\n\r\n    .eh_frame : ONLY_IF_RO\r\n    {\r\n        *(.eh_frame)\r\n    } > flash\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .data :\r\n    {\r\n        PROVIDE(_data = .);\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        PROVIDE(_edata = .);\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        PROVIDE(_bss_start = .);\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        PROVIDE(_bss_end = .);\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__ - __stacks_total_size__;\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"abf0f07a5a48df90a44a7fc63c24fc7f5532233b","subject":"stmhal: Set entry point for ELF binary debugging","message":"stmhal: Set entry point for ELF binary debugging\n\nWhen loading the ELF binary to the board with a debugger, the debugger\nneeds to know at which point to start executing the code. Currently the\nentry point defaults to the start of the .text section.\n\nSigned-off-by: Sven Wegener <18dc2ed701c57df81c0b5498c13767c232eb398f@stealer.net>\n","repos":"infinnovation\/micropython,henriknelson\/micropython,dmazzella\/micropython,lowRISC\/micropython,blazewicz\/micropython,tuc-osg\/micropython,PappaPeppar\/micropython,KISSMonX\/micropython,MrSurly\/micropython-esp32,pozetroninc\/micropython,pfalcon\/micropython,supergis\/micropython,kerneltask\/micropython,kostyll\/micropython,pramasoul\/micropython,pramasoul\/micropython,vitiral\/micropython,deshipu\/micropython,xyb\/micropython,PappaPeppar\/micropython,ChuckM\/micropython,deshipu\/micropython,cnoviello\/micropython,galenhz\/micropython,ruffy91\/micropython,heisewangluo\/micropython,hosaka\/micropython,stonegithubs\/micropython,swegener\/micropython,omtinez\/micropython,adafruit\/circuitpython,Peetz0r\/micropython-esp32,puuu\/micropython,Peetz0r\/micropython-esp32,Timmenem\/micropython,cloudformdesign\/micropython,HenrikSolver\/micropython,toolmacher\/micropython,neilh10\/micropython,mianos\/micropython,slzatz\/micropython,AriZuu\/micropython,dhylands\/micropython,matthewelse\/micropython,aethaniel\/micropython,lbattraw\/micropython,redbear\/micropython,Vogtinator\/micropython,SungEun-Steve-Kim\/test-mp,turbinenreiter\/micropython,mhoffma\/micropython,martinribelotta\/micropython,utopiaprince\/micropython,slzatz\/micropython,ernesto-g\/micropython,martinribelotta\/micropython,hiway\/micropython,cloudformdesign\/micropython,dxxb\/micropython,jlillest\/micropython,kostyll\/micropython,redbear\/micropython,HenrikSolver\/micropython,redbear\/micropython,cnoviello\/micropython,cloudformdesign\/micropython,SungEun-Steve-Kim\/test-mp,PappaPeppar\/micropython,chrisdearman\/micropython,ceramos\/micropython,alex-march\/micropython,cnoviello\/micropython,methoxid\/micropystat,ChuckM\/micropython,MrSurly\/micropython-esp32,ernesto-g\/micropython,turbinenreiter\/micropython,ganshun666\/micropython,misterdanb\/micropython,noahchense\/micropython,alex-march\/micropython,alex-march\/micropython,matthewelse\/micropython,Vogtinator\/micropython,ruffy91\/micropython,swegener\/micropython,galenhz\/micropython,Vogtinator\/micropython,tdautc19841202\/micropython,xuxiaoxin\/micropython,xyb\/micropython,tobbad\/micropython,jmarcelino\/pycom-micropython,deshipu\/micropython,henriknelson\/micropython,dmazzella\/micropython,blmorris\/micropython,paul-xxx\/micropython,ahotam\/micropython,ganshun666\/micropython,micropython\/micropython-esp32,cwyark\/micropython,MrSurly\/micropython,SungEun-Steve-Kim\/test-mp,lbattraw\/micropython,pozetroninc\/micropython,lowRISC\/micropython,cloudformdesign\/micropython,mpalomer\/micropython,alex-march\/micropython,selste\/micropython,tuc-osg\/micropython,aethaniel\/micropython,kerneltask\/micropython,tdautc19841202\/micropython,ryannathans\/micropython,emfcamp\/micropython,neilh10\/micropython,praemdonck\/micropython,micropython\/micropython-esp32,misterdanb\/micropython,infinnovation\/micropython,MrSurly\/micropython,xyb\/micropython,torwag\/micropython,jmarcelino\/pycom-micropython,stonegithubs\/micropython,cnoviello\/micropython,ernesto-g\/micropython,bvernoux\/micropython,firstval\/micropython,feilongfl\/micropython,supergis\/micropython,neilh10\/micropython,mianos\/micropython,henriknelson\/micropython,noahwilliamsson\/micropython,oopy\/micropython,alex-robbins\/micropython,methoxid\/micropystat,praemdonck\/micropython,heisewangluo\/micropython,chrisdearman\/micropython,selste\/micropython,vriera\/micropython,cwyark\/micropython,firstval\/micropython,dmazzella\/micropython,tralamazza\/micropython,dinau\/micropython,hiway\/micropython,KISSMonX\/micropython,Peetz0r\/micropython-esp32,danicampora\/micropython,dhylands\/micropython,turbinenreiter\/micropython,dxxb\/micropython,matthewelse\/micropython,supergis\/micropython,MrSurly\/micropython-esp32,blazewicz\/micropython,omtinez\/micropython,adafruit\/circuitpython,trezor\/micropython,blmorris\/micropython,xuxiaoxin\/micropython,mhoffma\/micropython,ericsnowcurrently\/micropython,SHA2017-badge\/micropython-esp32,xyb\/micropython,trezor\/micropython,TDAbboud\/micropython,aethaniel\/micropython,ahotam\/micropython,suda\/micropython,adamkh\/micropython,tobbad\/micropython,jimkmc\/micropython,AriZuu\/micropython,ernesto-g\/micropython,skybird6672\/micropython,AriZuu\/micropython,tobbad\/micropython,adafruit\/circuitpython,jimkmc\/micropython,methoxid\/micropystat,dinau\/micropython,feilongfl\/micropython,xuxiaoxin\/micropython,noahchense\/micropython,xyb\/micropython,swegener\/micropython,tdautc19841202\/micropython,Peetz0r\/micropython-esp32,EcmaXp\/micropython,AriZuu\/micropython,ChuckM\/micropython,hiway\/micropython,skybird6672\/micropython,ruffy91\/micropython,matthewelse\/micropython,selste\/micropython,SHA2017-badge\/micropython-esp32,xhat\/micropython,firstval\/micropython,xuxiaoxin\/micropython,TDAbboud\/micropython,paul-xxx\/micropython,danicampora\/micropython,infinnovation\/micropython,chrisdearman\/micropython,adafruit\/micropython,omtinez\/micropython,tralamazza\/micropython,ahotam\/micropython,skybird6672\/micropython,dxxb\/micropython,ganshun666\/micropython,toolmacher\/micropython,mgyenik\/micropython,HenrikSolver\/micropython,xhat\/micropython,MrSurly\/micropython,vitiral\/micropython,oopy\/micropython,stonegithubs\/micropython,noahchense\/micropython,ericsnowcurrently\/micropython,jlillest\/micropython,mianos\/micropython,ericsnowcurrently\/micropython,chrisdearman\/micropython,warner83\/micropython,SHA2017-badge\/micropython-esp32,tuc-osg\/micropython,rubencabrera\/micropython,trezor\/micropython,torwag\/micropython,orionrobots\/micropython,rubencabrera\/micropython,paul-xxx\/micropython,trezor\/micropython,MrSurly\/micropython,deshipu\/micropython,dinau\/micropython,heisewangluo\/micropython,noahwilliamsson\/micropython,praemdonck\/micropython,emfcamp\/micropython,orionrobots\/micropython,TDAbboud\/micropython,HenrikSolver\/micropython,tralamazza\/micropython,drrk\/micropython,lowRISC\/micropython,pozetroninc\/micropython,ryannathans\/micropython,drrk\/micropython,micropython\/micropython-esp32,dhylands\/micropython,mpalomer\/micropython,noahchense\/micropython,adafruit\/micropython,toolmacher\/micropython,micropython\/micropython-esp32,vriera\/micropython,kerneltask\/micropython,micropython\/micropython-esp32,kerneltask\/micropython,mpalomer\/micropython,alex-robbins\/micropython,oopy\/micropython,puuu\/micropython,hosaka\/micropython,matthewelse\/micropython,Vogtinator\/micropython,lbattraw\/micropython,emfcamp\/micropython,mgyenik\/micropython,hiway\/micropython,KISSMonX\/micropython,cwyark\/micropython,lbattraw\/micropython,PappaPeppar\/micropython,redbear\/micropython,adafruit\/circuitpython,xhat\/micropython,tdautc19841202\/micropython,adamkh\/micropython,praemdonck\/micropython,jimkmc\/micropython,Timmenem\/micropython,jlillest\/micropython,orionrobots\/micropython,mgyenik\/micropython,jmarcelino\/pycom-micropython,torwag\/micropython,pramasoul\/micropython,tobbad\/micropython,pfalcon\/micropython,ericsnowcurrently\/micropython,alex-robbins\/micropython,adafruit\/circuitpython,heisewangluo\/micropython,toolmacher\/micropython,MrSurly\/micropython-esp32,warner83\/micropython,puuu\/micropython,HenrikSolver\/micropython,dhylands\/micropython,noahwilliamsson\/micropython,methoxid\/micropystat,infinnovation\/micropython,oopy\/micropython,mianos\/micropython,skybird6672\/micropython,SungEun-Steve-Kim\/test-mp,bvernoux\/micropython,hosaka\/micropython,hosaka\/micropython,swegener\/micropython,omtinez\/micropython,EcmaXp\/micropython,SHA2017-badge\/micropython-esp32,TDAbboud\/micropython,SungEun-Steve-Kim\/test-mp,vitiral\/micropython,jimkmc\/micropython,MrSurly\/micropython-esp32,Vogtinator\/micropython,methoxid\/micropystat,suda\/micropython,Peetz0r\/micropython-esp32,jimkmc\/micropython,Timmenem\/micropython,tuc-osg\/micropython,torwag\/micropython,warner83\/micropython,ahotam\/micropython,cloudformdesign\/micropython,orionrobots\/micropython,neilh10\/micropython,tuc-osg\/micropython,Timmenem\/micropython,mhoffma\/micropython,slzatz\/micropython,kostyll\/micropython,bvernoux\/micropython,martinribelotta\/micropython,stonegithubs\/micropython,matthewelse\/micropython,utopiaprince\/micropython,mpalomer\/micropython,ceramos\/micropython,lowRISC\/micropython,ChuckM\/micropython,toolmacher\/micropython,adafruit\/micropython,warner83\/micropython,jmarcelino\/pycom-micropython,cwyark\/micropython,pfalcon\/micropython,pfalcon\/micropython,utopiaprince\/micropython,vitiral\/micropython,adafruit\/circuitpython,tobbad\/micropython,martinribelotta\/micropython,ceramos\/micropython,dmazzella\/micropython,TDAbboud\/micropython,hosaka\/micropython,martinribelotta\/micropython,drrk\/micropython,kostyll\/micropython,orionrobots\/micropython,rubencabrera\/micropython,selste\/micropython,PappaPeppar\/micropython,ruffy91\/micropython,ericsnowcurrently\/micropython,noahchense\/micropython,dinau\/micropython,galenhz\/micropython,redbear\/micropython,misterdanb\/micropython,jlillest\/micropython,omtinez\/micropython,deshipu\/micropython,swegener\/micropython,oopy\/micropython,cnoviello\/micropython,pramasoul\/micropython,pozetroninc\/micropython,puuu\/micropython,ganshun666\/micropython,firstval\/micropython,turbinenreiter\/micropython,dxxb\/micropython,MrSurly\/micropython,hiway\/micropython,praemdonck\/micropython,torwag\/micropython,kostyll\/micropython,blmorris\/micropython,firstval\/micropython,vriera\/micropython,kerneltask\/micropython,trezor\/micropython,ceramos\/micropython,slzatz\/micropython,AriZuu\/micropython,aethaniel\/micropython,vriera\/micropython,utopiaprince\/micropython,rubencabrera\/micropython,lbattraw\/micropython,ChuckM\/micropython,jmarcelino\/pycom-micropython,emfcamp\/micropython,paul-xxx\/micropython,emfcamp\/micropython,supergis\/micropython,alex-robbins\/micropython,ryannathans\/micropython,puuu\/micropython,feilongfl\/micropython,slzatz\/micropython,danicampora\/micropython,EcmaXp\/micropython,suda\/micropython,dhylands\/micropython,KISSMonX\/micropython,warner83\/micropython,jlillest\/micropython,noahwilliamsson\/micropython,vriera\/micropython,ahotam\/micropython,adafruit\/micropython,blazewicz\/micropython,feilongfl\/micropython,EcmaXp\/micropython,adamkh\/micropython,suda\/micropython,chrisdearman\/micropython,aethaniel\/micropython,blmorris\/micropython,turbinenreiter\/micropython,adamkh\/micropython,selste\/micropython,KISSMonX\/micropython,Timmenem\/micropython,stonegithubs\/micropython,pozetroninc\/micropython,pramasoul\/micropython,noahwilliamsson\/micropython,infinnovation\/micropython,mgyenik\/micropython,mpalomer\/micropython,drrk\/micropython,galenhz\/micropython,pfalcon\/micropython,adamkh\/micropython,drrk\/micropython,henriknelson\/micropython,tralamazza\/micropython,danicampora\/micropython,blazewicz\/micropython,mhoffma\/micropython,SHA2017-badge\/micropython-esp32,paul-xxx\/micropython,alex-robbins\/micropython,feilongfl\/micropython,utopiaprince\/micropython,misterdanb\/micropython,ceramos\/micropython,rubencabrera\/micropython,mianos\/micropython,xuxiaoxin\/micropython,alex-march\/micropython,ryannathans\/micropython,suda\/micropython,neilh10\/micropython,galenhz\/micropython,ryannathans\/micropython,xhat\/micropython,vitiral\/micropython,ruffy91\/micropython,skybird6672\/micropython,supergis\/micropython,mgyenik\/micropython,ganshun666\/micropython,bvernoux\/micropython,heisewangluo\/micropython,xhat\/micropython,ernesto-g\/micropython,dinau\/micropython,adafruit\/micropython,henriknelson\/micropython,cwyark\/micropython,misterdanb\/micropython,bvernoux\/micropython,blazewicz\/micropython,danicampora\/micropython,lowRISC\/micropython,mhoffma\/micropython,EcmaXp\/micropython,tdautc19841202\/micropython,dxxb\/micropython,blmorris\/micropython","old_file":"stmhal\/stm32f405.ld","new_file":"stmhal\/stm32f405.ld","new_contents":"\/*\n    GNU linker script for STM32F405\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 \/* sector 0, 16 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x080000 \/* sectors 5,6,7,8, 4*128KiB = 512 KiB (could increase it more) *\/\n    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 0x010000 \/* 64 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x020000 \/* 128 KiB *\/\n}\n\nENTRY(Reset_Handler)\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x2001c000; \/* tunable *\/\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        \/* This first flash block is 16K annd the isr vectors only take up\n           about 400 bytes. So we pull in a couple of object files to pad it\n           out. *\/\n\n        . = ALIGN(4);\n        *\/ff.o(.text*)\n        *\/stm32f4xx_hal_sd.o(.text*)\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n   \n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n     \n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n        \n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n        \n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT> FLASH_TEXT\n            \n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\tPROVIDE ( end = . );\n\tPROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n    GNU linker script for STM32F405\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 \/* sector 0, 16 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x080000 \/* sectors 5,6,7,8, 4*128KiB = 512 KiB (could increase it more) *\/\n    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 0x010000 \/* 64 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x020000 \/* 128 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x2001c000; \/* tunable *\/\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        \/* This first flash block is 16K annd the isr vectors only take up\n           about 400 bytes. So we pull in a couple of object files to pad it\n           out. *\/\n\n        . = ALIGN(4);\n        *\/ff.o(.text*)\n        *\/stm32f4xx_hal_sd.o(.text*)\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n   \n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n     \n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n        \n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n        \n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT> FLASH_TEXT\n            \n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\tPROVIDE ( end = . );\n\tPROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"541b1e14b731bc50b796fcc6ce9a1381070a253c","subject":"zephyr: linker: riscv: provide __image_size symbol","message":"zephyr: linker: riscv: provide __image_size symbol\n\nThis makes riscv core providing __image_size symbol for\ncalculating hash.\n\nBRANCH=none\nBUG=b:194794622\nTEST=__image_size is equal to ro\/rw binarys' size.\n\nSigned-off-by: Dino Li <338d523ecf3700bd86eb9c34d220f91911d2a18c@ite.com.tw>\nChange-Id: I7ffd8da6d0bb94362cb137458bf9962a5cf69c62\nReviewed-on: https:\/\/chromium-review.googlesource.com\/c\/chromiumos\/platform\/ec\/+\/3066837\nReviewed-by: Denis Brockus <6b21e8190fb5e373363fb95271367073a16474ef@chromium.org>\nReviewed-by: Keith Short <f6d578f97033c25f1206cb57d52f358974c82954@chromium.org>\n","repos":"coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec,coreboot\/chrome-ec","old_file":"zephyr\/linker\/image_size.ld","new_file":"zephyr\/linker\/image_size.ld","new_contents":"\/* Copyright 2021 The Chromium OS Authors. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n *\/\n\n#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_R) || \\\n\tdefined(CONFIG_CPU_CORTEX_A)\n__image_size = _flash_used;\n#elif defined(CONFIG_RISCV)\n\/* Firmware binary size is text + rodata + data in rom. *\/\n__image_size = _image_rom_size + (__data_ram_end - __data_ram_start);\n#else\n\/*\n * Intentionally set to 0. Some components, such as EFS2, need this value.\n * Having it be 0 will make it easier to find and add new cores.\n *\/\n__image_size = 0;\n#endif\n","old_contents":"\/* Copyright 2021 The Chromium OS Authors. All rights reserved.\n * Use of this source code is governed by a BSD-style license that can be\n * found in the LICENSE file.\n *\/\n\n#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_CORTEX_R) || \\\n\tdefined(CONFIG_CPU_CORTEX_A)\n__image_size = _flash_used;\n#else\n\/*\n * Intentionally set to 0. Some components, such as EFS2, need this value.\n * Having it be 0 will make it easier to find and add new cores.\n *\/\n__image_size = 0;\n#endif\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"3e392981d01f95e11a23c9c4b94bd8116cda51aa","subject":"userland: remove unused load_info section from .ld","message":"userland: remove unused load_info section from .ld\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n    } > FLASH =0xFF\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += STACK_SIZE;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += APP_HEAP_SIZE;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += KERNEL_HEAP_SIZE;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Load information, used by runtime to load app *\/\n    .load_info :\n    {\n        KEEP(*(.load_info))\n    } > FLASH =0xFF\n\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n    } > FLASH =0xFF\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += STACK_SIZE;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += APP_HEAP_SIZE;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += KERNEL_HEAP_SIZE;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"aecc516ce9f98ea4b7ce940e9ecbb5a16f4db7e2","subject":"cpu\/esp32: place freertos and periph in IRAM","message":"cpu\/esp32: place freertos and periph in IRAM\n\nThe IRAM is much faster, while the IROM is much slower and can only be accessed via a cache, which is also sometimes disabled, e.g. by the WiFi module or when writing to the flash. Therefore, time-critical code as well as code that has to work even when the cache is disabled must be placed in the IRAM.","repos":"kYc0o\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,miri64\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,miri64\/RIOT,miri64\/RIOT","old_file":"cpu\/esp32\/ld\/esp32.common.ld","new_file":"cpu\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* This section holds data that should not be initialized at power up\n     and will be retained during deep sleep. The section located in\n     RTC SLOW Memory area. User data marked with RTC_NOINIT_ATTR will be placed\n     into this section. See the file \"esp_attr.h\" for more information.\n  *\/\n  .rtc.noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _rtc_noinit_start = ABSOLUTE(.);\n    *(.rtc_noinit .rtc_noinit.*)\n    . = ALIGN(4) ;\n    _rtc_noinit_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  \/* If Bluetooth is not used, this DRAM section can be used as heap *\/\n  . = _data_start_btdm; \/* 0x3ffae6e0 *\/\n  . = ALIGN (4);\n  _sheap1 = ABSOLUTE(.);\n  . = 0x3ffb0000;\n  _eheap1 = ABSOLUTE(.);\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libc.a:*(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa\/*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap\/*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash\/*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core\/*(.literal .text .literal.* .text.*)\n    *littlefs\/*(.literal .text .literal.* .text.*)\n    *littlefs2\/*(.literal .text .literal.* .text.*)\n    *newlib_syscalls_default\/*(.literal .text .literal.* .text.*)\n    *spiffs_fs\/*(.literal .text .literal.* .text.*)\n    *spiffs\/*(.literal .text .literal.* .text.*)\n    *syscalls.o(.literal .text .literal.* .text.*)\n    *vfs\/*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu\/*(.literal .text .literal.* .text.*)\n    *esp_common\/*(.literal .text .literal.* .text.*)\n    *esp_freertos_common\/*(.literal .text .literal.* .text.*)\n    *periph\/*(.literal .text .literal.* .text.*)\n    *esp_periph_common\/*(.literal .text .literal.* .text.*)\n    *mtd\/**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n\n    \/* IRAM can't be used as heap since it only allows 32-bit aligned access *\/\n    \/*\n    . = ALIGN (4);\n    _sheap4 = ABSOLUTE(.);\n    *\/\n  } > iram0_0_seg\n\n  \/* IRAM can't be used as heap since it only allows 32-bit aligned access *\/\n  \/*\n  . = 0x400a0000;\n  _eheap4 = ABSOLUTE(.);\n  *\/\n\n  \/* Starts at 0x3ffb000 if Bluetooth is not enabled, 0x3ffc0000 otherwise *\/\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    KEEP (*(SORT(.xfa.*)))\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* This section holds data that should not be initialized at power up.\n     The section located in Internal SRAM memory region. The macro _NOINIT\n     can be used as attribute to place data into this section.\n     See the esp_attr.h file for more information.\n  *\/\n  .noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _noinit_start = ABSOLUTE(.);\n    __noinit_start = ABSOLUTE(.);\n    *(.noinit .noinit.*)\n    . = ALIGN(4) ;\n    _noinit_end = ABSOLUTE(.);\n    __noinit_end = ABSOLUTE(.);\n  } > dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* Reserved ROM\/ETS data start at 0x3ffe000. *\/\n  . = 0x3ffe0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  \/* Reserved ROM\/ETS data region for PRO CPU: 0x3ffe0000 ... 0x3ffe440 *\/\n  . = 0x3ffe0440;\n  _sheap2 = ABSOLUTE(.);\n  . = 0x3ffe4000;\n  _eheap2 = ABSOLUTE(.);\n\n  \/* Reserved ROM\/ETS data region for APP CPU: 0x3ffe4000 ... 0x3ffe4350 *\/\n  . = 0x3ffe4350;\n  _sheap3 = ABSOLUTE(.);\n  . = 0x40000000;\n  _eheap3 = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    KEEP (*(SORT(.roxfa.*)))\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* This section holds data that should not be initialized at power up\n     and will be retained during deep sleep. The section located in\n     RTC SLOW Memory area. User data marked with RTC_NOINIT_ATTR will be placed\n     into this section. See the file \"esp_attr.h\" for more information.\n  *\/\n  .rtc.noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _rtc_noinit_start = ABSOLUTE(.);\n    *(.rtc_noinit .rtc_noinit.*)\n    . = ALIGN(4) ;\n    _rtc_noinit_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  \/* If Bluetooth is not used, this DRAM section can be used as heap *\/\n  . = _data_start_btdm; \/* 0x3ffae6e0 *\/\n  . = ALIGN (4);\n  _sheap1 = ABSOLUTE(.);\n  . = 0x3ffb0000;\n  _eheap1 = ABSOLUTE(.);\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libc.a:*(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa\/*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap\/*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash\/*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core\/*(.literal .text .literal.* .text.*)\n    *littlefs\/*(.literal .text .literal.* .text.*)\n    *littlefs2\/*(.literal .text .literal.* .text.*)\n    *newlib_syscalls_default\/*(.literal .text .literal.* .text.*)\n    *spiffs_fs\/*(.literal .text .literal.* .text.*)\n    *spiffs\/*(.literal .text .literal.* .text.*)\n    *syscalls.o(.literal .text .literal.* .text.*)\n    *vfs\/*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu\/*(.literal .text .literal.* .text.*)\n    *esp_common\/*(.literal .text .literal.* .text.*)\n    *periph\/*(.literal .text .literal.* .text.*)\n    *mtd\/**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n\n    \/* IRAM can't be used as heap since it only allows 32-bit aligned access *\/\n    \/*\n    . = ALIGN (4);\n    _sheap4 = ABSOLUTE(.);\n    *\/\n  } > iram0_0_seg\n\n  \/* IRAM can't be used as heap since it only allows 32-bit aligned access *\/\n  \/*\n  . = 0x400a0000;\n  _eheap4 = ABSOLUTE(.);\n  *\/\n\n  \/* Starts at 0x3ffb000 if Bluetooth is not enabled, 0x3ffc0000 otherwise *\/\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    KEEP (*(SORT(.xfa.*)))\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* This section holds data that should not be initialized at power up.\n     The section located in Internal SRAM memory region. The macro _NOINIT\n     can be used as attribute to place data into this section.\n     See the esp_attr.h file for more information.\n  *\/\n  .noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _noinit_start = ABSOLUTE(.);\n    __noinit_start = ABSOLUTE(.);\n    *(.noinit .noinit.*)\n    . = ALIGN(4) ;\n    _noinit_end = ABSOLUTE(.);\n    __noinit_end = ABSOLUTE(.);\n  } > dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* Reserved ROM\/ETS data start at 0x3ffe000. *\/\n  . = 0x3ffe0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  \/* Reserved ROM\/ETS data region for PRO CPU: 0x3ffe0000 ... 0x3ffe440 *\/\n  . = 0x3ffe0440;\n  _sheap2 = ABSOLUTE(.);\n  . = 0x3ffe4000;\n  _eheap2 = ABSOLUTE(.);\n\n  \/* Reserved ROM\/ETS data region for APP CPU: 0x3ffe4000 ... 0x3ffe4350 *\/\n  . = 0x3ffe4350;\n  _sheap3 = ABSOLUTE(.);\n  . = 0x40000000;\n  _eheap3 = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    KEEP (*(SORT(.roxfa.*)))\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"0d910597050fa8a91505d861e83272fd7afb91dd","subject":"add Category","message":"add Category","repos":"ggreif\/al4nin,ggreif\/al4nin","old_file":"purgatory\/db\/refs.ld","new_file":"purgatory\/db\/refs.ld","new_contents":"{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.category }\n   @Title { Wikipedia: Category }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Category_(mathematics) }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.free-monoid }\n   @Title { Wikipedia: Free monoid }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Free_monoid }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.groupoid }\n   @Title { Wikipedia: Groupoid }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Groupoid }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.dominoes }\n   @Title { Wikipedia: Dominoes }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Dominoes }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { roundy.darcs2 }\n   @Title { Wikipedia: Darcs }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Darcs }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikibooks.patch }\n   @Title { Wikibooks: Understanding darcs\"\/\"Patch theory }\n   @URL { http:\/\/en.wikibooks.org\/wiki\/Understanding_darcs\/Patch_theory }\n}\n","old_contents":"{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.free-monoid }\n   @Title { Wikipedia: Free monoid }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Free_monoid }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.groupoid }\n   @Title { Wikipedia: Groupoid }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Groupoid }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.dominoes }\n   @Title { Wikipedia: Dominoes }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Dominoes }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { roundy.darcs2 }\n   @Title { Wikipedia: Darcs }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Darcs }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikibooks.patch }\n   @Title { Wikibooks: Understanding darcs\"\/\"Patch theory }\n   @URL { http:\/\/en.wikibooks.org\/wiki\/Understanding_darcs\/Patch_theory }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"d7602a49d8320fd5560385d49485856e6e70617b","subject":"Update the sh4 apps to locate at 0x200000 instead of 0x100000","message":"Update the sh4 apps to locate at 0x200000 instead of 0x100000\n\n\ngit-svn-id: fb278a52ad97f7fbef074986829f2c6a2a3c4b34@621 c25cc9d1-44fa-0310-b259-ad778cb1d433\n","repos":"siraj\/newos,travisg\/newos,zhouxh1023\/newos,siraj\/newos,siraj\/newos,zhouxh1023\/newos,zhouxh1023\/newos,travisg\/newos,dioptre\/newos,dioptre\/newos,dioptre\/newos,travisg\/newos,siraj\/newos","old_file":"apps\/ldscripts\/sh4\/app.ld","new_file":"apps\/ldscripts\/sh4\/app.ld","new_contents":"OUTPUT_FORMAT(\"elf32-shl\", \"elf32-shl\", \"elf32-shl\")\nOUTPUT_ARCH(sh)\n\nENTRY(__start)\nSEARCH_DIR(\"libgcc\");\nSECTIONS\n{\n\t. = 0x00200000 + SIZEOF_HEADERS;\n\n\t\/* text\/read-only data *\/\n\t.text :\t{ *(.text .gnu.linkonce.t.*) }\n\n\t___ctor_list = .;\n\t.ctors : { *(.ctors) }\n\t___ctor_end = .;\n\n  \t.rodata :\n\t{ \n \t\t*(.rodata)\n \t\t. = ALIGN(0x1000);\n \t} =0x9000\n\n\t\/* writable data  *\/\n  \t. = ALIGN(0x1000) + (. & (0x1000 - 1));\n\t___data_start = .;\n\t.data : { *(.data .gnu.linkonce.d.*) }\n\n\t\/* unintialized data (in same segment as writable data) *\/\n\t___bss_start = .;\n\t.bss : { *(.bss) }\n\n\t. = ALIGN(0x1000);\n\t_end = . ;\n\n\t\/* Strip unnecessary stuff *\/\n\t\/DISCARD\/ : { *(.comment .note .eh_frame .dtors) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-shl\", \"elf32-shl\", \"elf32-shl\")\nOUTPUT_ARCH(sh)\n\nENTRY(__start)\nSEARCH_DIR(\"libgcc\");\nSECTIONS\n{\n\t. = 0x00100000 + SIZEOF_HEADERS;\n\n\t\/* text\/read-only data *\/\n\t.text :\t{ *(.text .gnu.linkonce.t.*) }\n\n\t___ctor_list = .;\n\t.ctors : { *(.ctors) }\n\t___ctor_end = .;\n\n  \t.rodata :\n\t{ \n \t\t*(.rodata)\n \t\t. = ALIGN(0x1000);\n \t} =0x9000\n\n\t\/* writable data  *\/\n  \t. = ALIGN(0x1000) + (. & (0x1000 - 1));\n\t___data_start = .;\n\t.data : { *(.data .gnu.linkonce.d.*) }\n\n\t\/* unintialized data (in same segment as writable data) *\/\n\t___bss_start = .;\n\t.bss : { *(.bss) }\n\n\t. = ALIGN(0x1000);\n\t_end = . ;\n\n\t\/* Strip unnecessary stuff *\/\n\t\/DISCARD\/ : { *(.comment .note .eh_frame .dtors) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"4bf973d9f9f2d6f718bc4eac744cd58759ea624f","subject":"Fix misalignment on PrgData","message":"Fix misalignment on PrgData\n","repos":"mbedmicro\/FlashAlgo,mbedmicro\/FlashAlgo,mbedmicro\/FlashAlgo","old_file":"source\/FlashAlgo.ld","new_file":"source\/FlashAlgo.ld","new_contents":"\/* Flash OS Routines\n * Copyright (c) 2009-2015 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\n\/*\n * The PrgCode and PrgData output section names come from the CMSIS-Pack flash algo\n * templates and armlink. It is used here because several tools that work\n * with these flash algos expect this section name.\n *\/\nSECTIONS\n{\n    PrgCode 0 : ALIGN_WITH_INPUT\n    {\n        *(.text*)\n        EXCLUDE_FILE (*FlashDev.o) *(.rodata*)\n        . = ALIGN(16);\n    }\n\n    PrgData : ALIGN_WITH_INPUT\n    {\n        *(.data*)\n        *(.bss*)\n        *(.got*)\n        *(COMMON)\n        . = ALIGN(16);\n    }\n\n    DevDscr :\n    {\n        *FlashDev.o(*)\n    }\n\n    \/DISCARD\/ : {\n        \/* Unused exception related info that only wastes space *\/\n        *(.ARM.exidx);\n        *(.ARM.exidx.*);\n        *(.ARM.extab.*);\n    }\n}\n","old_contents":"\/* Flash OS Routines\n * Copyright (c) 2009-2015 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\n\/*\n * The PrgCode and PrgData output section names come from the CMSIS-Pack flash algo\n * templates and armlink. It is used here because several tools that work\n * with these flash algos expect this section name.\n *\/\nSECTIONS\n{\n    PrgCode 0 :\n    {\n        *(.text*)\n        EXCLUDE_FILE (*FlashDev.o) *(.rodata*)\n    }\n\n    PrgData :\n    {\n        *(.data*)\n        *(.bss*)\n        *(.got*)\n        *(COMMON)\n    }\n\n    DevDscr :\n    {\n        *FlashDev.o(*)\n    }\n\n    \/DISCARD\/ : {\n        \/* Unused exception related info that only wastes space *\/\n        *(.ARM.exidx);\n        *(.ARM.exidx.*);\n        *(.ARM.extab.*);\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"53823f418541796996ebe99711eda85a199677b2","subject":"Double stack size.","message":"Double stack size.\n","repos":"eigenholser\/embedded_programming_intro,eigenholser\/embedded_programming_intro","old_file":"demo\/linker.lds","new_file":"demo\/linker.lds","new_contents":"\/*\n\n *\/\n\/******************************************************************************\n *\n * Default Linker script for the Texas Instruments TM4C123GH6PM\n *\n * This is derived from revision 15071 of the TivaWare Library.\n *\n *****************************************************************************\/\n\nMEMORY\n{\n    FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n    SRAM (WX)  : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\nSTACK_SIZE = 0x400;\nHEAP_SIZE = 0x1000;\n\nREGION_ALIAS(\"REGION_TEXT\", FLASH);\nREGION_ALIAS(\"REGION_BSS\", SRAM);\nREGION_ALIAS(\"REGION_DATA\", SRAM);\nREGION_ALIAS(\"REGION_STACK\", SRAM);\nREGION_ALIAS(\"REGION_HEAP\", SRAM);\nREGION_ALIAS(\"REGION_ARM_EXIDX\", FLASH);\nREGION_ALIAS(\"REGION_ARM_EXTAB\", FLASH);\n\nSECTIONS {\n\n    PROVIDE (_intvecs_base_address = 0x0);\n\n    .intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {\n        KEEP (*(.intvecs))\n        . = ALIGN(0x4);\n    } > REGION_TEXT\n\n    PROVIDE (_vtable_base_address = 0x20000000);\n\n    .vtable (_vtable_base_address) : AT (_vtable_base_address) {\n        KEEP (*(.vtable))\n    } > REGION_DATA\n\n    .text : {\n        CREATE_OBJECT_SYMBOLS\n        *(.text)\n        *(.text.*)\n        . = ALIGN(0x4);\n        KEEP (*(.ctors))\n        . = ALIGN(0x4);\n        KEEP (*(.dtors))\n        . = ALIGN(0x4);\n        __init_array_start = .;\n        KEEP (*(.init_array*))\n        __init_array_end = .;\n        *(.init)\n        *(.fini*)\n    } > REGION_TEXT\n\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata*)\n    } > REGION_TEXT\n\n    .stack : ALIGN(0x4) {\n        __stack_start__ = .;\n        . = . + STACK_SIZE;\n        KEEP(*(.stack))\n        __stack_end__ = .;\n    } > REGION_STACK\n\n    .data : ALIGN (0x4) {\n        __data_load__ = LOADADDR (.data);\n        __data_start__ = .;\n        *(.data)\n        *(.data*)\n        . = ALIGN (0x4);\n        __data_end__ = .;\n    } > REGION_DATA AT> REGION_TEXT\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > REGION_ARM_EXIDX\n\n    .ARM.extab : {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > REGION_ARM_EXTAB\n\n    .bss : {\n        __bss_start__ = .;\n        *(.shbss)\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN (0x4);\n        __bss_end__ = .;\n    } > REGION_BSS\n\n    .heap : {\n        __heap_start__ = .;\n        end = __heap_start__;\n        _end = end;\n        __end = end;\n        KEEP(*(.heap))\n        __heap_end__ = .;\n        __HeapLimit = __heap_end__;\n    } > REGION_HEAP\n\n    \/* Remove information from the standard libraries *\/\n    \/DISCARD\/ : {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n}\n","old_contents":"\/*\n\n *\/\n\/******************************************************************************\n *\n * Default Linker script for the Texas Instruments TM4C123GH6PM\n *\n * This is derived from revision 15071 of the TivaWare Library.\n *\n *****************************************************************************\/\n\nMEMORY\n{\n    FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n    SRAM (WX)  : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\nSTACK_SIZE = 0x200;\nHEAP_SIZE = 0x1000;\n\nREGION_ALIAS(\"REGION_TEXT\", FLASH);\nREGION_ALIAS(\"REGION_BSS\", SRAM);\nREGION_ALIAS(\"REGION_DATA\", SRAM);\nREGION_ALIAS(\"REGION_STACK\", SRAM);\nREGION_ALIAS(\"REGION_HEAP\", SRAM);\nREGION_ALIAS(\"REGION_ARM_EXIDX\", FLASH);\nREGION_ALIAS(\"REGION_ARM_EXTAB\", FLASH);\n\nSECTIONS {\n\n    PROVIDE (_intvecs_base_address = 0x0);\n\n    .intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {\n        KEEP (*(.intvecs))\n        . = ALIGN(0x4);\n    } > REGION_TEXT\n\n    PROVIDE (_vtable_base_address = 0x20000000);\n\n    .vtable (_vtable_base_address) : AT (_vtable_base_address) {\n        KEEP (*(.vtable))\n    } > REGION_DATA\n\n    .text : {\n        CREATE_OBJECT_SYMBOLS\n        *(.text)\n        *(.text.*)\n        . = ALIGN(0x4);\n        KEEP (*(.ctors))\n        . = ALIGN(0x4);\n        KEEP (*(.dtors))\n        . = ALIGN(0x4);\n        __init_array_start = .;\n        KEEP (*(.init_array*))\n        __init_array_end = .;\n        *(.init)\n        *(.fini*)\n    } > REGION_TEXT\n\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata*)\n    } > REGION_TEXT\n\n    .stack : ALIGN(0x4) {\n        __stack_start__ = .;\n        . = . + STACK_SIZE;\n        KEEP(*(.stack))\n        __stack_end__ = .;\n    } > REGION_STACK\n\n    .data : ALIGN (0x4) {\n        __data_load__ = LOADADDR (.data);\n        __data_start__ = .;\n        *(.data)\n        *(.data*)\n        . = ALIGN (0x4);\n        __data_end__ = .;\n    } > REGION_DATA AT> REGION_TEXT\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > REGION_ARM_EXIDX\n\n    .ARM.extab : {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > REGION_ARM_EXTAB\n\n    .bss : {\n        __bss_start__ = .;\n        *(.shbss)\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN (0x4);\n        __bss_end__ = .;\n    } > REGION_BSS\n\n    .heap : {\n        __heap_start__ = .;\n        end = __heap_start__;\n        _end = end;\n        __end = end;\n        KEEP(*(.heap))\n        __heap_end__ = .;\n        __HeapLimit = __heap_end__;\n    } > REGION_HEAP\n\n    \/* Remove information from the standard libraries *\/\n    \/DISCARD\/ : {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f9bcf3940c1198416fde539b19e386629ab69821","subject":"Put config_flash into fixed memory at 0x0800e000","message":"Put config_flash into fixed memory at 0x0800e000\n","repos":"laneboysrc\/nrf24l01-rc,laneboysrc\/nrf24l01-rc,laneboysrc\/nrf24l01-rc","old_file":"stm32f1-nrf24l01-transmitter\/firmware\/stm32f103c8t6.ld","new_file":"stm32f1-nrf24l01-transmitter\/firmware\/stm32f103c8t6.ld","new_contents":"\/* Linker script for AliExpress STM32F103 board (STM32F103C8T6, 64K flash, 20K RAM). *\/\n\nMEMORY\n{\n\trom (rx)  : ORIGIN = 0x08000000, LENGTH = 64K\n\tram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\n\/* Put the transmitter configuration in the upper-most 8 KBytes of flash *\/\nSECTIONS\n{\n    .transmitter_configuration 0x0800e000 :\n    {\n        *(.rodata.config_flash)\n    }\n}\n\n\nINCLUDE libopencm3_stm32f1.ld\n\n\n","old_contents":"\/* Linker script for AliExpress STM32F103 board (STM32F103C8T6, 64K flash, 20K RAM). *\/\n\nMEMORY\n{\n\trom (rx)  : ORIGIN = 0x08000000, LENGTH = 64K\n\tram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\nINCLUDE libopencm3_stm32f1.ld\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"c6e347c06fe2accc43ae288d55deae5ece16c274","subject":"Clean exported symbols (#20608)","message":"Clean exported symbols (#20608)\n\n* linkopts shared\r\n\r\n* try to remove some symbols\r\n\r\n* revert PyInit\r\n\r\n* remove opencensus\r\n\r\n* add suffix\r\n\r\n* try to remove JNI\r\n\r\n* _JNI_On*","repos":"ray-project\/ray,ray-project\/ray,ray-project\/ray,ray-project\/ray,ray-project\/ray,ray-project\/ray,ray-project\/ray,ray-project\/ray","old_file":"src\/ray\/ray_exported_symbols.lds","new_file":"src\/ray\/ray_exported_symbols.lds","new_contents":"# This file defines the C++ symbols that need to be exported (aka ABI, application binary interface).\n# These symbols will be used by other libraries (e.g., streaming).\n# Note: This file is used for macOS only, and should be kept in sync with `ray_version_script.lds`.\n# Ray ABI is not finalized, the exact set of exported (C\/C++) APIs is subject to change.\n# common\n*ray*Language*\n*ray*RayObject*\n*ray*Status*\n*ray*RayFunction*\n*ray*FunctionDescriptorBuilder*\n*ray*TaskArg*\n*ray*TaskOptions*\n*ray*Buffer*\n*ray*LocalMemoryBuffer*\n# util\n*ray*RayLog*\n*ray*RayLogLevel*\n# id\n*ray*MurmurHash64A*\n*ray*JobID*\n*ray*TaskID*\n*ray*ActorID*\n*ray*ObjectID*\n*ray*ObjectReference*\n# Others\n*ray*metrics*\n*ray*stats*\n*ray*rpc*\n*ray*gcs*\n*ray*CoreWorker*\n*ray*PeriodicalRunner*;\n*PyInit__raylet*\n*Java_io_ray*\n_JNI_On*\n*ray*streaming*\n","old_contents":"# This file defines the C++ symbols that need to be exported (aka ABI, application binary interface).\n# These symbols will be used by other libraries (e.g., streaming).\n# Note: This file is used for macOS only, and should be kept in sync with `ray_version_script.lds`.\n# Ray ABI is not finalized, the exact set of exported (C\/C++) APIs is subject to change.\n# common\n*ray*Language*\n*ray*RayObject*\n*ray*Status*\n*ray*RayFunction*\n*ray*FunctionDescriptorBuilder*\n*ray*TaskArg*\n*ray*TaskOptions*\n*ray*Buffer*\n*ray*LocalMemoryBuffer*\n# util\n*ray*RayLog*\n*ray*RayLogLevel*\n# id\n*ray*MurmurHash64A*\n*ray*JobID*\n*ray*TaskID*\n*ray*ActorID*\n*ray*ObjectID*\n*ray*ObjectReference*\n# Others\n*ray*metrics*\n*opencensus*\n*ray*stats*\n*ray*rpc*\n*ray*gcs*\n*ray*CoreWorker*\n*ray*PeriodicalRunner*;\n*PyInit*\n*init_raylet*\n*Java*\n*JNI_*\n*ray*streaming*\n*aligned_free*\n*aligned_malloc*","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a7e3f55a3411575d9aaf461bd507e49cb54f5f2b","subject":"linker script: Put __edata after exported symbols","message":"linker script: Put __edata after exported symbols\n","repos":"SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl","old_file":"build\/linker.lds","new_file":"build\/linker.lds","new_contents":"OUTPUT_ARCH(mips)\nSTARTUP(crt0.o)\nGROUP(-lcrt0 -lc -ljava)\nENTRY(__start)\n\nSECTIONS\n{\n       \t. = 0x1000000;\n       \t.text : ALIGN(4) { *(.init) *(.text) *(.text.*) *(.gnu.linkonce.t.*) }\n       \t. = 0x0;\n       \t.data : ALIGN(16) { *(.data0) *(.data) *(.rodata.str1.4)  *(.rodata.cst4) *(.rodata.cst8) *(.reginfo) }\n       \t.rodata : ALIGN(16) { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) *(.cibylsetjmp) }\n\n\t.ctors : ALIGN(4) {\n\t       PROVIDE(__ctors_begin = .);\n\t       *(.ctors)\n\t       PROVIDE(__ctors_end = .);\n\t}\n\t.dtors : ALIGN(4) {\n\t       PROVIDE(__dtors_begin = .);\n\t       *(.dtors)\n\t       PROVIDE(__dtors_end = .);\n\t}\n       \t.bss : ALIGN(16) {\n\t     *(.bss) *(.scommon) *(.sbss)\n\t}\n\n        \/* Exported symbols (to Java) *\/\n\t.cibylexpsyms : { *(.cibylexpsyms) }\n\tPROVIDE(__edata = .);\n\n\t\/* The string table with the exception names *\/\n\t. = 0xfd000000;\n       \t.cibylexceptionstrs : { *(.cibylexceptionstrs) }\n\n\t\/* The string table with the system call names *\/\n\t. = 0xff000000;\n       \t.cibylstrtab : { *(.cibylstrtab) }\n}\n","old_contents":"OUTPUT_ARCH(mips)\nSTARTUP(crt0.o)\nGROUP(-lcrt0 -lc -ljava)\nENTRY(__start)\n\nSECTIONS\n{\n       \t. = 0x1000000;\n       \t.text : ALIGN(4) { *(.init) *(.text) *(.text.*) *(.gnu.linkonce.t.*) }\n       \t. = 0x0;\n       \t.data : ALIGN(16) { *(.data0) *(.data) *(.rodata.str1.4)  *(.rodata.cst4) *(.rodata.cst8) *(.reginfo) }\n       \t.rodata : ALIGN(16) { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) *(.cibylsetjmp) }\n\n\t.ctors : ALIGN(4) {\n\t       PROVIDE(__ctors_begin = .);\n\t       *(.ctors)\n\t       PROVIDE(__ctors_end = .);\n\t}\n\t.dtors : ALIGN(4) {\n\t       PROVIDE(__dtors_begin = .);\n\t       *(.dtors)\n\t       PROVIDE(__dtors_end = .);\n\t}\n       \t.bss : ALIGN(16) {\n\t     *(.bss) *(.scommon) *(.sbss)\n\t     PROVIDE(__edata = .);\n\t}\n\n        \/* Exported symbols (to Java) *\/\n       \t.cibylexpsyms : { *(.cibylexpsyms) }\n\n\t\/* The string table with the exception names *\/\n\t. = 0xfd000000;\n       \t.cibylexceptionstrs : { *(.cibylexceptionstrs) }\n\n\t\/* The string table with the system call names *\/\n\t. = 0xff000000;\n       \t.cibylstrtab : { *(.cibylstrtab) }\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"fcbc04d8b3671659f10914aac8480cb874b0116c","subject":"Hack the kernel addon linker script to force it to produce a single program segment. This should help us work around a limitation in the kernel loader where it wont load a new binary properly sometimes.","message":"Hack the kernel addon linker script to force it to produce a single\nprogram segment. This should help us work around a limitation in the\nkernel loader where it wont load a new binary properly sometimes.\n\n\ngit-svn-id: fb278a52ad97f7fbef074986829f2c6a2a3c4b34@1130 c25cc9d1-44fa-0310-b259-ad778cb1d433\n","repos":"siraj\/newos,dioptre\/newos,travisg\/newos,travisg\/newos,travisg\/newos,zhouxh1023\/newos,dioptre\/newos,siraj\/newos,zhouxh1023\/newos,zhouxh1023\/newos,dioptre\/newos,siraj\/newos,siraj\/newos","old_file":"kernel\/addons\/ldscripts\/i386\/addon.ld","new_file":"kernel\/addons\/ldscripts\/i386\/addon.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\n\nENTRY(_start)\nSEARCH_DIR(\"libgcc\");\nSECTIONS\n{\n\t. = 0x00000000 + SIZEOF_HEADERS;\n\n\t.interp : { *(.interp) }\n\t.hash : { *(.hash) }\n\t.dynsym : { *(.dynsym) }\n\t.dynstr : { *(.dynstr) }\n\t.rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) }\n\t.rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) }\n\t.rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) }\n\t.rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) }\n\t.rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }\n\t.rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }\n\t.rel.got : { *(.rel.got) }\n\t.rela.got : { *(.rela.got) }\n\t.rel.ctors : { *(.rel.ctors) }\n\t.rela.ctors : { *(.rela.ctors) }\n\t.rel.dtors : { *(.rel.dtors) }\n\t.rela.dtors : { *(.rela.dtors) }\n\t.rel.init : { *(.rel.init) }\n\t.rela.init : { *(.rela.init) }\n\t.rel.fini : { *(.rel.fini) }\n\t.rela.fini : { *(.rela.fini) }\n\t.rel.bss : { *(.rel.bss) }\n\t.rela.bss : { *(.rela.bss) }\n\t.rel.plt : { *(.rel.plt) }\n\t.rela.plt : { *(.rela.plt) }\n\t.init : { *(.init) } =0x9090\n\t.plt : { *(.plt) }\n\n\t\/* text\/read-only data *\/\n\t.text :\t{ *(.text .gnu.linkonce.t.*) } =0x9090\n\n\t.rodata : { *(.rodata) }\n\n\t\/* writable data  *\/\n\t\/* dont align the sections, this will force the binary to have a single\n\t * program header to work around a limitation in the kernel loader\n     *\/\n\/*  \t. = ALIGN(0x1000) + (. & (0x1000 - 1)); *\/\n\t__data_start = .;\n\t.data : { *(.data .gnu.linkonce.d.*) }\n\n\t__ctor_list = .;\n\t.ctors : { *(.ctors) }\n\t__ctor_end = .;\n\t__dtor_list = .;\n\t.dtors : { *(.dtors) }\n\t__dtor_end = .;\n\t.got : { *(.got.plt) *(.got) }\n\t.dynamic : { *(.dynamic) }\n\t\n\t\/* unintialized data (in same segment as writable data) *\/\n\t__bss_start = .;\n\t.bss : { *(.bss) }\n\n\t. = ALIGN(0x1000);\n\t_end = . ;\n\n\t\/* Strip unnecessary stuff *\/\n\t\/DISCARD\/ : { *(.comment .note .eh_frame) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\n\nENTRY(_start)\nSEARCH_DIR(\"libgcc\");\nSECTIONS\n{\n\t. = 0x00000000 + SIZEOF_HEADERS;\n\n\t.interp : { *(.interp) }\n\t.hash : { *(.hash) }\n\t.dynsym : { *(.dynsym) }\n\t.dynstr : { *(.dynstr) }\n\t.rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) }\n\t.rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) }\n\t.rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) }\n\t.rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) }\n\t.rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }\n\t.rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }\n\t.rel.got : { *(.rel.got) }\n\t.rela.got : { *(.rela.got) }\n\t.rel.ctors : { *(.rel.ctors) }\n\t.rela.ctors : { *(.rela.ctors) }\n\t.rel.dtors : { *(.rel.dtors) }\n\t.rela.dtors : { *(.rela.dtors) }\n\t.rel.init : { *(.rel.init) }\n\t.rela.init : { *(.rela.init) }\n\t.rel.fini : { *(.rel.fini) }\n\t.rela.fini : { *(.rela.fini) }\n\t.rel.bss : { *(.rel.bss) }\n\t.rela.bss : { *(.rela.bss) }\n\t.rel.plt : { *(.rel.plt) }\n\t.rela.plt : { *(.rela.plt) }\n\t.init : { *(.init) } =0x9090\n\t.plt : { *(.plt) }\n\n\t\/* text\/read-only data *\/\n\t.text :\t{ *(.text .gnu.linkonce.t.*) } =0x9090\n\n\t.rodata : { *(.rodata) }\n\n\t\/* writable data  *\/\n  \t. = ALIGN(0x1000) + (. & (0x1000 - 1));\n\t__data_start = .;\n\t.data : { *(.data .gnu.linkonce.d.*) }\n\n\t__ctor_list = .;\n\t.ctors : { *(.ctors) }\n\t__ctor_end = .;\n\t__dtor_list = .;\n\t.dtors : { *(.dtors) }\n\t__dtor_end = .;\n\t.got : { *(.got.plt) *(.got) }\n\t.dynamic : { *(.dynamic) }\n\t\n\t\/* unintialized data (in same segment as writable data) *\/\n\t__bss_start = .;\n\t.bss : { *(.bss) }\n\n\t. = ALIGN(0x1000);\n\t_end = . ;\n\n\t\/* Strip unnecessary stuff *\/\n\t\/DISCARD\/ : { *(.comment .note .eh_frame) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"bd7cdf8f7cde47a310b419e0857ec9116fba5c12","subject":"driver: esp32s3 fix UART driver","message":"driver: esp32s3 fix UART driver\n\nFix set UART2 instance to correct base address (esp32s3 has non standard base periph address)\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp32s3\/ld\/esp32s3.peripherals.ld","new_file":"components\/esp32s3\/ld\/esp32s3.peripherals.ld","new_contents":"PROVIDE ( UART0 = 0x60000000 );\nPROVIDE ( SPIMEM1 = 0x60002000 );\nPROVIDE ( SPIMEM0 = 0x60003000 );\nPROVIDE ( GPIO = 0x60004000 );\nPROVIDE ( SIGMADELTA = 0x60004f00 );\nPROVIDE ( RTCCNTL = 0x60008000 );\nPROVIDE ( RTCIO = 0x60008400 );\nPROVIDE ( SENS = 0x60008800 );\nPROVIDE ( HINF = 0x6000B000 );\nPROVIDE ( I2S0 = 0x6000F000 );\nPROVIDE ( UART1 = 0x60010000 );\nPROVIDE ( I2C0 = 0x60013000 );\nPROVIDE ( UHCI0 = 0x60014000 );\nPROVIDE ( UHCI1 = 0x60014000 );\nPROVIDE ( HOST = 0x60015000 );\nPROVIDE ( RMT = 0x60016000 );\nPROVIDE ( RMTMEM = 0x60016800 );\nPROVIDE ( PCNT = 0x60017000 );\nPROVIDE ( SLC = 0x60018000 );\nPROVIDE ( LEDC = 0x60019000 );\nPROVIDE ( MCPWM0 = 0x6001E000 );\nPROVIDE ( MCPWM1 = 0x6002C000 );\nPROVIDE ( MCP = 0x600c3000 );\nPROVIDE ( TIMERG0 = 0x6001F000 );\nPROVIDE ( TIMERG1 = 0x60020000 );\nPROVIDE ( SYS_TIMER = 0x60023000 );\nPROVIDE ( GPSPI2  = 0x60024000 );\nPROVIDE ( GPSPI3  = 0x60025000 );\nPROVIDE ( SYSCON = 0x60026000 );\nPROVIDE ( I2C1 = 0x60027000 );\nPROVIDE ( TWAI = 0x6002B000 );\nPROVIDE ( GPSPI4 = 0x60037000 );\nPROVIDE ( GDMA = 0x6003F000 );\nPROVIDE ( UART2  = 0x6001e000 );\nPROVIDE ( DMA = 0x6003F000 );\nPROVIDE ( APB_SARADC = 0x60040000 );\nPROVIDE ( LCD_CAM    = 0x60041000 );\n","old_contents":"PROVIDE ( UART0 = 0x60000000 );\nPROVIDE ( SPIMEM1 = 0x60002000 );\nPROVIDE ( SPIMEM0 = 0x60003000 );\nPROVIDE ( GPIO = 0x60004000 );\nPROVIDE ( SIGMADELTA = 0x60004f00 );\nPROVIDE ( RTCCNTL = 0x60008000 );\nPROVIDE ( RTCIO = 0x60008400 );\nPROVIDE ( SENS = 0x60008800 );\nPROVIDE ( HINF = 0x6000B000 );\nPROVIDE ( I2S0 = 0x6000F000 );\nPROVIDE ( UART1 = 0x60010000 );\nPROVIDE ( I2C0 = 0x60013000 );\nPROVIDE ( UHCI0 = 0x60014000 );\nPROVIDE ( UHCI1 = 0x60014000 );\nPROVIDE ( HOST = 0x60015000 );\nPROVIDE ( RMT = 0x60016000 );\nPROVIDE ( RMTMEM = 0x60016800 );\nPROVIDE ( PCNT = 0x60017000 );\nPROVIDE ( SLC = 0x60018000 );\nPROVIDE ( LEDC = 0x60019000 );\nPROVIDE ( MCPWM0 = 0x6001E000 );\nPROVIDE ( MCPWM1 = 0x6002C000 );\nPROVIDE ( MCP = 0x600c3000 );\nPROVIDE ( TIMERG0 = 0x6001F000 );\nPROVIDE ( TIMERG1 = 0x60020000 );\nPROVIDE ( SYS_TIMER = 0x60023000 );\nPROVIDE ( GPSPI2  = 0x60024000 );\nPROVIDE ( GPSPI3  = 0x60025000 );\nPROVIDE ( SYSCON = 0x60026000 );\nPROVIDE ( I2C1 = 0x60027000 );\nPROVIDE ( TWAI = 0x6002B000 );\nPROVIDE ( GPSPI4 = 0x60037000 );\nPROVIDE ( GDMA = 0x6003F000 );\nPROVIDE ( UART2  = 0x60010000 );\nPROVIDE ( DMA = 0x6003F000 );\nPROVIDE ( APB_SARADC = 0x60040000 );\nPROVIDE ( LCD_CAM    = 0x60041000 );\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"95e5fec8d0b5bf2792a81e9a6f90d040307283c6","subject":"EFM32GG: Fix GCC_ARM linker script","message":"EFM32GG: Fix GCC_ARM linker script\n\nA copy paste error snuck into the uVisor related updates to the EFM32GG\nlinker script. Fix the error by replacing \"m_data\" with \"RAM\".\n\nFixes: 89641bc7e0ce \"uVisor: Update K64F and EFM32GG linker scripts\"\n","repos":"theotherjimmy\/mbed,karsev\/mbed-os,ryankurte\/mbed-os,Archcady\/mbed-os,nRFMesh\/mbed-os,fanghuaqi\/mbed,nRFMesh\/mbed-os,YarivCol\/mbed-os,kjbracey-arm\/mbed,NXPmicro\/mbed,mmorenobarm\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,NXPmicro\/mbed,Archcady\/mbed-os,Archcady\/mbed-os,fanghuaqi\/mbed,arostm\/mbed-os,betzw\/mbed-os,bulislaw\/mbed-os,mikaleppanen\/mbed-os,ryankurte\/mbed-os,CalSol\/mbed,j-greffe\/mbed-os,mazimkhan\/mbed-os,adamgreen\/mbed,betzw\/mbed-os,c1728p9\/mbed-os,karsev\/mbed-os,c1728p9\/mbed-os,adamgreen\/mbed,bcostm\/mbed-os,mikaleppanen\/mbed-os,adamgreen\/mbed,svogl\/mbed-os,adamgreen\/mbed,cvtsi2sd\/mbed-os,c1728p9\/mbed-os,netzimme\/mbed-os,pradeep-gr\/mbed-os5-onsemi,arostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,nRFMesh\/mbed-os,CalSol\/mbed,betzw\/mbed-os,mmorenobarm\/mbed-os,NXPmicro\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,kl-cruz\/mbed-os,CalSol\/mbed,screamerbg\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,CalSol\/mbed,screamerbg\/mbed,nRFMesh\/mbed-os,mazimkhan\/mbed-os,HeadsUpDisplayInc\/mbed,CalSol\/mbed,catiedev\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,j-greffe\/mbed-os,mbedmicro\/mbed,RonEld\/mbed,mazimkhan\/mbed-os,maximmbed\/mbed,adustm\/mbed,theotherjimmy\/mbed,CalSol\/mbed,HeadsUpDisplayInc\/mbed,ryankurte\/mbed-os,arostm\/mbed-os,betzw\/mbed-os,RonEld\/mbed,ryankurte\/mbed-os,HeadsUpDisplayInc\/mbed,karsev\/mbed-os,catiedev\/mbed-os,bcostm\/mbed-os,infinnovation\/mbed-os,nvlsianpu\/mbed,monkiineko\/mbed-os,betzw\/mbed-os,bcostm\/mbed-os,nvlsianpu\/mbed,bcostm\/mbed-os,arostm\/mbed-os,fanghuaqi\/mbed,screamerbg\/mbed,NXPmicro\/mbed,RonEld\/mbed,infinnovation\/mbed-os,arostm\/mbed-os,HeadsUpDisplayInc\/mbed,kjbracey-arm\/mbed,karsev\/mbed-os,fahhem\/mbed-os,bulislaw\/mbed-os,infinnovation\/mbed-os,andcor02\/mbed-os,mikaleppanen\/mbed-os,adustm\/mbed,arostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,infinnovation\/mbed-os,cvtsi2sd\/mbed-os,kjbracey-arm\/mbed,betzw\/mbed-os,j-greffe\/mbed-os,RonEld\/mbed,theotherjimmy\/mbed,fahhem\/mbed-os,mazimkhan\/mbed-os,monkiineko\/mbed-os,Archcady\/mbed-os,RonEld\/mbed,bulislaw\/mbed-os,nvlsianpu\/mbed,cvtsi2sd\/mbed-os,karsev\/mbed-os,fanghuaqi\/mbed,YarivCol\/mbed-os,netzimme\/mbed-os,mmorenobarm\/mbed-os,mbedmicro\/mbed,Archcady\/mbed-os,c1728p9\/mbed-os,svogl\/mbed-os,andcor02\/mbed-os,nRFMesh\/mbed-os,monkiineko\/mbed-os,mazimkhan\/mbed-os,monkiineko\/mbed-os,YarivCol\/mbed-os,cvtsi2sd\/mbed-os,maximmbed\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,nvlsianpu\/mbed,nRFMesh\/mbed-os,ryankurte\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,netzimme\/mbed-os,nvlsianpu\/mbed,screamerbg\/mbed,ryankurte\/mbed-os,fahhem\/mbed-os,kl-cruz\/mbed-os,pradeep-gr\/mbed-os5-onsemi,mikaleppanen\/mbed-os,kl-cruz\/mbed-os,RonEld\/mbed,cvtsi2sd\/mbed-os,mmorenobarm\/mbed-os,YarivCol\/mbed-os,NXPmicro\/mbed,netzimme\/mbed-os,infinnovation\/mbed-os,kl-cruz\/mbed-os,svogl\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,mbedmicro\/mbed,adustm\/mbed,theotherjimmy\/mbed,andcor02\/mbed-os,adamgreen\/mbed,maximmbed\/mbed,andcor02\/mbed-os,c1728p9\/mbed-os,bulislaw\/mbed-os,j-greffe\/mbed-os,pradeep-gr\/mbed-os5-onsemi,YarivCol\/mbed-os,kl-cruz\/mbed-os,maximmbed\/mbed,fahhem\/mbed-os,NXPmicro\/mbed,fanghuaqi\/mbed,adamgreen\/mbed,fahhem\/mbed-os,j-greffe\/mbed-os,bulislaw\/mbed-os,svogl\/mbed-os,bcostm\/mbed-os,Archcady\/mbed-os,maximmbed\/mbed,monkiineko\/mbed-os,YarivCol\/mbed-os,j-greffe\/mbed-os,catiedev\/mbed-os,mmorenobarm\/mbed-os,svogl\/mbed-os,bcostm\/mbed-os,adustm\/mbed,screamerbg\/mbed,netzimme\/mbed-os,theotherjimmy\/mbed,andcor02\/mbed-os,bulislaw\/mbed-os,adustm\/mbed,nvlsianpu\/mbed,catiedev\/mbed-os,kl-cruz\/mbed-os,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,mikaleppanen\/mbed-os,catiedev\/mbed-os,fahhem\/mbed-os,adustm\/mbed,karsev\/mbed-os,screamerbg\/mbed,mazimkhan\/mbed-os,theotherjimmy\/mbed,mikaleppanen\/mbed-os,mmorenobarm\/mbed-os,cvtsi2sd\/mbed-os,mbedmicro\/mbed,monkiineko\/mbed-os,catiedev\/mbed-os,netzimme\/mbed-os,svogl\/mbed-os,infinnovation\/mbed-os,maximmbed\/mbed,pradeep-gr\/mbed-os5-onsemi,HeadsUpDisplayInc\/mbed,kjbracey-arm\/mbed","old_file":"targets\/TARGET_Silicon_Labs\/TARGET_EFM32\/TARGET_EFM32GG\/device\/TARGET_1024K\/TOOLCHAIN_GCC_ARM\/efm32gg.ld","new_file":"targets\/TARGET_Silicon_Labs\/TARGET_EFM32\/TARGET_EFM32GG\/device\/TARGET_1024K\/TOOLCHAIN_GCC_ARM\/efm32gg.ld","new_contents":"\/* Linker script for Silicon Labs EFM32GG devices *\/\n\/*                                                                  *\/\n\/* This file is subject to the license terms as defined in ARM's    *\/\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\n\/* Example Code.                                                    *\/\n\/*                                                                  *\/\n\/* Silicon Laboratories, Inc. 2015                                  *\/\n\/*                                                                  *\/\n\/* Version 4.2.0 *\/\n\/*                                                                  *\/\n\nSTACK_SIZE = 0x400;\nHEAP_SIZE = 0xC00;\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 131072\n}\n\/* MBED: mbed needs to be able to dynamically set the interrupt vector table.\n * We make room for the table at the very beginning of RAM, i.e. at\n * 0x20000000. We need (16+39) * sizeof(uint32_t) = 220 bytes for EFM32GG *\/\n__vector_size = 0xDC;\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __Vectors_End\n *   __Vectors_Size\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  \/* Note: The uVisor expects the text section at a fixed location, as specified\n               by the porting process configuration parameter: FLASH_OFFSET. *\/\n  __UVISOR_FLASH_OFFSET = 0x100;\n  __UVISOR_FLASH_START = ORIGIN(FLASH) + __UVISOR_FLASH_OFFSET;\n  .text :\n  {\n    KEEP(*(.vectors))\n    __Vectors_End = .;\n    __Vectors_Size = __Vectors_End - __Vectors;\n    __end__ = .;\n\n    \/* uVisor code and data *\/\n    . = __UVISOR_FLASH_OFFSET;\n    . = ALIGN(4);\n    __uvisor_main_start = .;\n    *(.uvisor.main)\n    __uvisor_main_end = .;\n\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    \/* .ctors *\/\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    \/* .dtors *\/\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  \/* To copy multiple ROM to RAM sections,\n   * uncomment .copy.table section and,\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n  \/*\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG (__data_end__ - __data_start__)\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG (__data2_end__ - __data2_start__)\n    __copy_table_end__ = .;\n  } > FLASH\n  *\/\n\n  \/* To clear multiple BSS sections,\n   * uncomment .zero.table section and,\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n  \/*\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    LONG (__bss_start__)\n    LONG (__bss_end__ - __bss_start__)\n    LONG (__bss2_start__)\n    LONG (__bss2_end__ - __bss2_start__)\n    __zero_table_end__ = .;\n  } > FLASH\n  *\/\n\n  \/* uVisor own memory and private box memories\n  \/* If uVisor shares the SRAM with the OS\/app, ensure that this section is\n   * the first one after the VTOR relocation section. *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified\n           by the porting process configuration parameter: SRAM_OFFSET. *\/\n  __UVISOR_SRAM_OFFSET = 0x0;\n  __UVISOR_SRAM_START = ORIGIN(RAM) + __UVISOR_SRAM_OFFSET;\n  .uvisor.bss __UVISOR_SRAM_START (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uvisor_bss_start = .;\n\n    \/* Protected uVisor own BSS section *\/\n    . = ALIGN(32);\n    __uvisor_bss_main_start = .;\n    KEEP(*(.keep.uvisor.bss.main))\n    . = ALIGN(32);\n    __uvisor_bss_main_end = .;\n\n    \/* Protected uVisor boxes' static memories *\/\n    . = ALIGN(32);\n    __uvisor_bss_boxes_start = .;\n    KEEP(*(.keep.uvisor.bss.boxes))\n    . = ALIGN(32);\n    __uvisor_bss_boxes_end = .;\n\n    . = ALIGN(32);\n    __uvisor_bss_end = .;\n  } > RAM\n\n  \/* Heap space for the page allocator\n  \/* If uVisor shares the SRAM with the OS\/app, ensure that this section is\n   * the first one after the uVisor BSS section. Otherwise, ensure it is the\n   * first one after the VTOR relocation section. *\/\n  .page_heap (NOLOAD) :\n  {\n    . = ALIGN(32);\n    __uvisor_page_start = .;\n    KEEP(*(.keep.uvisor.page_heap))\n    . = ALIGN( (1 << LOG2CEIL(LENGTH(RAM))) \/ 8);\n    __uvisor_page_end = .;\n  } > RAM\n\n  .data :\n  {\n    PROVIDE(__etext = LOADADDR(.data));    \/* Define a global symbol at end of code, *\/\n    PROVIDE(__DATA_ROM = LOADADDR(.data)); \/* Symbol is used by startup for data initialization. *\/\n\n    __data_start__ = .;\n    *(\"dma\")\n    PROVIDE( __start_vector_table__ = .);\n    . += __vector_size;\n    PROVIDE( __end_vector_table__ = .);\n    *(vtable)\n    *(.data*)\n    . = ALIGN (4);\n    *(.ram)\n\n    . = ALIGN(4);\n    \/* preinit data *\/\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    \/* init data *\/\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    \/* finit data *\/\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    \/* All data end *\/\n    __data_end__ = .;\n\n  } > RAM AT > FLASH\n\n  \/* uVisor configuration section\n   * This section must be located after all other flash regions. *\/\n  .uvisor.secure :\n  {\n    . = ALIGN(32);\n    __uvisor_secure_start = .;\n\n    \/* uVisor secure boxes configuration tables *\/\n    . = ALIGN(32);\n    __uvisor_cfgtbl_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl))\n    . = ALIGN(32);\n    __uvisor_cfgtbl_end = .;\n\n    \/* Pointers to the uVisor secure boxes configuration tables *\/\n    \/* Note: Do not add any further alignment here, as uVisor will need to\n             have access to the exact list of pointers. *\/\n    __uvisor_cfgtbl_ptr_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n    KEEP(*(.keep.uvisor.cfgtbl_ptr))\n    __uvisor_cfgtbl_ptr_end = .;\n\n    \/* Pointers to all boxes register gateways. These are grouped here to\n       allow discoverability and firmware verification. *\/\n    __uvisor_register_gateway_ptr_start = .;\n    KEEP(*(.keep.uvisor.register_gateway_ptr))\n    __uvisor_register_gateway_ptr_end = .;\n\n    . = ALIGN(32);\n    __uvisor_secure_end = .;\n  } > FLASH\n\n  \/* Uninitialized data section\n   * This region is not initialized by the C\/C++ library and can be used to\n   * store state across soft reboots. *\/\n  .uninitialized (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uninitialized_start = .;\n    *(.uninitialized)\n    KEEP(*(.keep.uninitialized))\n    . = ALIGN(32);\n    __uninitialized_end = .;\n  } > RAM\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM\n\n  .heap (NOLOAD):\n  {\n    __uvisor_heap_start = .;\n    __HeapBase = .;\n    __end__ = .;\n    end = __end__;\n    _end = __end__;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __uvisor_heap_end = .;\n  } > RAM\n\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n  __stack = __StackTop;\n  __StackLimit = __StackTop - STACK_SIZE;\n\n  ASSERT(__StackLimit >= __HeapLimit, \"Region RAM overflowed with stack and heap\")\n\n  \/* Provide physical memory boundaries for uVisor. *\/\n  __uvisor_flash_start = ORIGIN(FLASH);\n  __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n  __uvisor_sram_start = ORIGIN(RAM);\n  __uvisor_sram_end = ORIGIN(RAM) + LENGTH(RAM);\n  __uvisor_public_sram_start = __uvisor_sram_start;\n  __uvisor_public_sram_end = __uvisor_sram_end;\n}\n","old_contents":"\/* Linker script for Silicon Labs EFM32GG devices *\/\n\/*                                                                  *\/\n\/* This file is subject to the license terms as defined in ARM's    *\/\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\n\/* Example Code.                                                    *\/\n\/*                                                                  *\/\n\/* Silicon Laboratories, Inc. 2015                                  *\/\n\/*                                                                  *\/\n\/* Version 4.2.0 *\/\n\/*                                                                  *\/\n\nSTACK_SIZE = 0x400;\nHEAP_SIZE = 0xC00;\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 131072\n}\n\/* MBED: mbed needs to be able to dynamically set the interrupt vector table.\n * We make room for the table at the very beginning of RAM, i.e. at\n * 0x20000000. We need (16+39) * sizeof(uint32_t) = 220 bytes for EFM32GG *\/\n__vector_size = 0xDC;\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __Vectors_End\n *   __Vectors_Size\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  \/* Note: The uVisor expects the text section at a fixed location, as specified\n               by the porting process configuration parameter: FLASH_OFFSET. *\/\n  __UVISOR_FLASH_OFFSET = 0x100;\n  __UVISOR_FLASH_START = ORIGIN(FLASH) + __UVISOR_FLASH_OFFSET;\n  .text :\n  {\n    KEEP(*(.vectors))\n    __Vectors_End = .;\n    __Vectors_Size = __Vectors_End - __Vectors;\n    __end__ = .;\n\n    \/* uVisor code and data *\/\n    . = __UVISOR_FLASH_OFFSET;\n    . = ALIGN(4);\n    __uvisor_main_start = .;\n    *(.uvisor.main)\n    __uvisor_main_end = .;\n\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    \/* .ctors *\/\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    \/* .dtors *\/\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  \/* To copy multiple ROM to RAM sections,\n   * uncomment .copy.table section and,\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n  \/*\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG (__data_end__ - __data_start__)\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG (__data2_end__ - __data2_start__)\n    __copy_table_end__ = .;\n  } > FLASH\n  *\/\n\n  \/* To clear multiple BSS sections,\n   * uncomment .zero.table section and,\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n  \/*\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    LONG (__bss_start__)\n    LONG (__bss_end__ - __bss_start__)\n    LONG (__bss2_start__)\n    LONG (__bss2_end__ - __bss2_start__)\n    __zero_table_end__ = .;\n  } > FLASH\n  *\/\n\n  \/* uVisor own memory and private box memories\n  \/* If uVisor shares the SRAM with the OS\/app, ensure that this section is\n   * the first one after the VTOR relocation section. *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified\n           by the porting process configuration parameter: SRAM_OFFSET. *\/\n  __UVISOR_SRAM_OFFSET = 0x0;\n  __UVISOR_SRAM_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;\n  .uvisor.bss __UVISOR_SRAM_START (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uvisor_bss_start = .;\n\n    \/* Protected uVisor own BSS section *\/\n    . = ALIGN(32);\n    __uvisor_bss_main_start = .;\n    KEEP(*(.keep.uvisor.bss.main))\n    . = ALIGN(32);\n    __uvisor_bss_main_end = .;\n\n    \/* Protected uVisor boxes' static memories *\/\n    . = ALIGN(32);\n    __uvisor_bss_boxes_start = .;\n    KEEP(*(.keep.uvisor.bss.boxes))\n    . = ALIGN(32);\n    __uvisor_bss_boxes_end = .;\n\n    . = ALIGN(32);\n    __uvisor_bss_end = .;\n  } > RAM\n\n  \/* Heap space for the page allocator\n  \/* If uVisor shares the SRAM with the OS\/app, ensure that this section is\n   * the first one after the uVisor BSS section. Otherwise, ensure it is the\n   * first one after the VTOR relocation section. *\/\n  .page_heap (NOLOAD) :\n  {\n    . = ALIGN(32);\n    __uvisor_page_start = .;\n    KEEP(*(.keep.uvisor.page_heap))\n    . = ALIGN( (1 << LOG2CEIL(LENGTH(RAM))) \/ 8);\n    __uvisor_page_end = .;\n  } > RAM\n\n  .data :\n  {\n    PROVIDE(__etext = LOADADDR(.data));    \/* Define a global symbol at end of code, *\/\n    PROVIDE(__DATA_ROM = LOADADDR(.data)); \/* Symbol is used by startup for data initialization. *\/\n\n    __data_start__ = .;\n    *(\"dma\")\n    PROVIDE( __start_vector_table__ = .);\n    . += __vector_size;\n    PROVIDE( __end_vector_table__ = .);\n    *(vtable)\n    *(.data*)\n    . = ALIGN (4);\n    *(.ram)\n\n    . = ALIGN(4);\n    \/* preinit data *\/\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    \/* init data *\/\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    \/* finit data *\/\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    \/* All data end *\/\n    __data_end__ = .;\n\n  } > RAM AT > FLASH\n\n  \/* uVisor configuration section\n   * This section must be located after all other flash regions. *\/\n  .uvisor.secure :\n  {\n    . = ALIGN(32);\n    __uvisor_secure_start = .;\n\n    \/* uVisor secure boxes configuration tables *\/\n    . = ALIGN(32);\n    __uvisor_cfgtbl_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl))\n    . = ALIGN(32);\n    __uvisor_cfgtbl_end = .;\n\n    \/* Pointers to the uVisor secure boxes configuration tables *\/\n    \/* Note: Do not add any further alignment here, as uVisor will need to\n             have access to the exact list of pointers. *\/\n    __uvisor_cfgtbl_ptr_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n    KEEP(*(.keep.uvisor.cfgtbl_ptr))\n    __uvisor_cfgtbl_ptr_end = .;\n\n    \/* Pointers to all boxes register gateways. These are grouped here to\n       allow discoverability and firmware verification. *\/\n    __uvisor_register_gateway_ptr_start = .;\n    KEEP(*(.keep.uvisor.register_gateway_ptr))\n    __uvisor_register_gateway_ptr_end = .;\n\n    . = ALIGN(32);\n    __uvisor_secure_end = .;\n  } > FLASH\n\n  \/* Uninitialized data section\n   * This region is not initialized by the C\/C++ library and can be used to\n   * store state across soft reboots. *\/\n  .uninitialized (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uninitialized_start = .;\n    *(.uninitialized)\n    KEEP(*(.keep.uninitialized))\n    . = ALIGN(32);\n    __uninitialized_end = .;\n  } > RAM\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM\n\n  .heap (NOLOAD):\n  {\n    __uvisor_heap_start = .;\n    __HeapBase = .;\n    __end__ = .;\n    end = __end__;\n    _end = __end__;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __uvisor_heap_end = .;\n  } > RAM\n\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n  __stack = __StackTop;\n  __StackLimit = __StackTop - STACK_SIZE;\n\n  ASSERT(__StackLimit >= __HeapLimit, \"Region RAM overflowed with stack and heap\")\n\n  \/* Provide physical memory boundaries for uVisor. *\/\n  __uvisor_flash_start = ORIGIN(FLASH);\n  __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n  __uvisor_sram_start = ORIGIN(RAM);\n  __uvisor_sram_end = ORIGIN(RAM) + LENGTH(RAM);\n  __uvisor_public_sram_start = __uvisor_sram_start;\n  __uvisor_public_sram_end = __uvisor_sram_end;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8f5a42c61c06d75fe8da3acc47c6f100121ac07f","subject":"Use format=\"discount\" in config.ld","message":"Use format=\"discount\" in config.ld\n","repos":"craigbarnes\/lua-gumbo,craigbarnes\/lua-gumbo,craigbarnes\/lua-gumbo","old_file":"config.ld","new_file":"config.ld","new_contents":"project     = \"lua-gumbo\"\ntitle       = \"lua-gumbo\"\ndescription = \"Lua bindings for the Gumbo HTML5 parsing library\"\nno_summary  = true\nnot_luadoc  = true\nformat      = \"discount\"\ndir         = \"docs\"\nfile        = \"gumbo.c\"\nreadme      = \"README.md\"\nexamples    = {\"example.lua\", \"test.lua\"}\n","old_contents":"project     = \"lua-gumbo\"\ntitle       = \"lua-gumbo\"\ndescription = \"Lua bindings for the Gumbo HTML5 parsing library\"\nno_summary  = true\nnot_luadoc  = true\nformat      = \"markdown\"\ndir         = \"docs\"\nfile        = \"gumbo.c\"\nreadme      = \"README.md\"\nexamples    = {\"example.lua\", \"test.lua\"}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3cc14b2c2b12abfd3c18c5245eaca0fbd5b21b49","subject":"soc: intel_adsp: fix linker script for cavs_v20","message":"soc: intel_adsp: fix linker script for cavs_v20\n\nApply a similar fix for cavs_v20 as was done for other cavs platforms in\ncommit ee7773fb462b (\"soc: intel_adsp: fix linker script for XCC\").\nWithout this fix, cavs_v20 build with fail with 0.13.0 Zephyr SDK.\n\nFixes: 74cc8bee7c56 (\"xtensa: cavs_v20: use uncached addresses to support SMP\")\nBugLink: https:\/\/github.com\/thesofproject\/sof\/issues\/4703\nSigned-off-by: Kai Vehmanen <7c1f7969959c2510655bc0fc9c602f735b2254b7@linux.intel.com>\n","repos":"galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v20\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v20\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * The UNCACHED_RAM_OFFSET will be used before to move the address\n * pointer forward or backward so code and data land in correct\n * region. Remember to align the memory, and be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define UNCACHED_RAM_OFFSET\t0x20000000\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - UNCACHED_RAM_OFFSET,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs20_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs20_adsp);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  \/*\n   * Address pointer here is at cached ram.\n   * So need to go into uncached memory region, hence\n   * the subtraction.\n   *\/\n  segstart_uncached_noinit = ALIGN(64) - UNCACHED_RAM_OFFSET;\n\n  .noinit segstart_uncached_noinit : ALIGN(64)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  \/* Going back into cached memory region. *\/\n  segstart_cached_lit4 = ALIGN(64) + UNCACHED_RAM_OFFSET;\n\n  .lit4 segstart_cached_lit4 : ALIGN(64)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  \/* Going back into cached memory region. *\/\n  segstart_cached_cached = ALIGN(64) + UNCACHED_RAM_OFFSET;\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached segstart_cached_cached :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  \/* Going back into un-cached memory region. *\/\n  segstart_uncached_tm_clone_table = ALIGN(64) - UNCACHED_RAM_OFFSET;\n\n  .tm_clone_table segstart_uncached_tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss ALIGN(64) (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  _end = ALIGN(64);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  segstart_cached_stack = _end + UNCACHED_RAM_OFFSET;\n  . = segstart_cached_stack;\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n  segstart_uncached_lpbuf = ALIGN(4) - UNCACHED_RAM_OFFSET;\n  . = segstart_uncached_lpbuf;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  _heap_sentry = . - UNCACHED_RAM_OFFSET;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs20_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs20_adsp);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .cached :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n\n  . = SEGSTART_UNCACHED;\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  .bss (NOLOAD) : ALIGN(4096)\n  {\n    . = ALIGN(4096);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n  . = SEGSTART_UNCACHED;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"666f713f7d8febf44c66769b84431dfc48000952","subject":"Fixed ram0 start address on linker file (#206)","message":"Fixed ram0 start address on linker file (#206)\n\n- this is for nanoCLR of ST_NUCLEO_F091RC\r\n\r\nSigned-off-by: Jos\u00e9 Sim\u00f5es <1616ff7a83d123f98f8f38fa2524eab406644781@eclo.solutions>","repos":"nanoframework\/nf-interpreter,Eclo\/nf-interpreter,Eclo\/nf-interpreter,Eclo\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter,nanoframework\/nf-interpreter,nanoframework\/nf-interpreter","old_file":"targets\/CMSIS-OS\/ChibiOS\/ST_NUCLEO_F091RC\/nanoCLR\/STM32F091xC.ld","new_file":"targets\/CMSIS-OS\/ChibiOS\/ST_NUCLEO_F091RC\/nanoCLR\/STM32F091xC.ld","new_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio.  All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n\n\/*\n * STM32F091xC memory setup.\n *\/\nMEMORY\n{\n    flash : org = 0x08004000, len = 256k - 0x3FFF \/* flash size less the space reserved for bootloader (1st eight sectors 0x08000000 to 0x08001FFF)*\/\n    ramvt : org = 0x20000000, len = 0xC0        \/* initial RAM address is reserved for a copy of the vector table *\/\n    ram0  : org = 0x200000C0, len = 32k - 0xC0  \/* remaining RAM is free for use *\/\n    ram1  : org = 0x00000000, len = 0\n    ram2  : org = 0x00000000, len = 0\n    ram3  : org = 0x00000000, len = 0\n    ram4  : org = 0x00000000, len = 0\n    ram5  : org = 0x00000000, len = 0\n    ram6  : org = 0x00000000, len = 0\n    ram7  : org = 0x00000000, len = 0\n}\n\n\/* RAM region to be used for Main stack. This stack accommodates the processing\n   of all exceptions and interrupts*\/\nREGION_ALIAS(\"MAIN_STACK_RAM\", ram0);\n\n\/* RAM region to be used for the process stack. This is the stack used by\n   the main() function.*\/\nREGION_ALIAS(\"PROCESS_STACK_RAM\", ram0);\n\n\/* RAM region to be used for data segment.*\/\nREGION_ALIAS(\"DATA_RAM\", ram0);\n\n\/* RAM region to be used for BSS segment.*\/\nREGION_ALIAS(\"BSS_RAM\", ram0);\n\n\/* RAM region to be used for the default heap.*\/\nREGION_ALIAS(\"HEAP_RAM\", ram0);\n\n\/* RAM region to be used for the nanoFramework CLR managed heap.*\/\nREGION_ALIAS(\"CLR_MANAGED_HEAP_RAM\", ram0);\n\nINCLUDE rules.ld\n","old_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio.  All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n\n\/*\n * STM32F091xC memory setup.\n *\/\nMEMORY\n{\n    flash : org = 0x08004000, len = 256k - 0x3FFF \/* flash size less the space reserved for bootloader (1st eight sectors 0x08000000 to 0x08001FFF)*\/\n    ramvt : org = 0x20000000, len = 0xC0        \/* initial RAM address is reserved for a copy of the vector table *\/\n    ram0  : org = 0x20000000, len = 32k - 0xC0  \/* remaining RAM is free for use *\/\n    ram1  : org = 0x00000000, len = 0\n    ram2  : org = 0x00000000, len = 0\n    ram3  : org = 0x00000000, len = 0\n    ram4  : org = 0x00000000, len = 0\n    ram5  : org = 0x00000000, len = 0\n    ram6  : org = 0x00000000, len = 0\n    ram7  : org = 0x00000000, len = 0\n}\n\n\/* RAM region to be used for Main stack. This stack accommodates the processing\n   of all exceptions and interrupts*\/\nREGION_ALIAS(\"MAIN_STACK_RAM\", ram0);\n\n\/* RAM region to be used for the process stack. This is the stack used by\n   the main() function.*\/\nREGION_ALIAS(\"PROCESS_STACK_RAM\", ram0);\n\n\/* RAM region to be used for data segment.*\/\nREGION_ALIAS(\"DATA_RAM\", ram0);\n\n\/* RAM region to be used for BSS segment.*\/\nREGION_ALIAS(\"BSS_RAM\", ram0);\n\n\/* RAM region to be used for the default heap.*\/\nREGION_ALIAS(\"HEAP_RAM\", ram0);\n\n\/* RAM region to be used for the nanoFramework CLR managed heap.*\/\nREGION_ALIAS(\"CLR_MANAGED_HEAP_RAM\", ram0);\n\nINCLUDE rules.ld\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"241f1ac832c23a8c5077ec69df62d743872a7373","subject":"Adjust linker script to new naming convention.","message":"Adjust linker script to new naming convention.\n","repos":"ksejdak\/cosmos,ksejdak\/cosmos,ksejdak\/cosmos","old_file":"board\/beaglebone-black\/beaglebone-black.ld","new_file":"board\/beaglebone-black\/beaglebone-black.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nENTRY(_start)\n\nMEMORY {\n\tddr (rwx)      :      ORIGIN = 0x00000000, LENGTH = 512M       \/* External DDR3 RAM *\/\n    sram (rwx)     :      ORIGIN = 0x402f0400, LENGTH = 32K        \/* Internal on-chip SRAM *\/\n}\n\n_bootStart_va = ORIGIN(sram); \/* Kernel .boot VMA should be the same as LMA, as MMU is not configured. *\/\n_textStart_va = 0x80000000;   \/* Kernel .text starts at 2 GB. *\/\n_stackSize    = 0x1000;       \/* Stak size is 4KB.*\/\n\nSECTIONS {\n    \/* Starup code. *\/\n    .boot _bootStart_va : {\n        _bootStart_pa = .;\n\n        *(.boot)\n\n        _bootEnd_pa = .;\n    } AT > sram\n\n    \/* Kernel code. *\/\n    \/* .text _textStart_va : *\/\n    .text : { \/* TODO: change to above in future. *\/\n        *(.text)                \/* .text sections (code). *\/\n        *(.text*)               \/* .text* sections (code) - this will merge all symbols in .text into one section. *\/\n        *(.glue_7)              \/* Glue arm to thumb code. *\/\n        *(.glue_7t)             \/* Glue thumb to arm code. *\/\n        *(.eh_frame)\n        KEEP (*(.init))\n        KEEP (*(.fini))\n    } AT > sram \/* TODO: change to ddr in future. *\/\n\n    \/* Constructors and destructors. *\/\n\t.ctors : {\n\t\tKEEP (*crtbegin*.o(.ctors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t} AT > sram \/* TODO: change to ddr in future. *\/\n\n\t.dtors : {\n\t\tKEEP (*crtbegin*.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t} AT > sram \/* TODO: change to ddr in future. *\/\n\n    \/* Data. *\/\n\t.data : {\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t} AT > sram = 0\n\t\n\t\/* Read only data *\/\n\t.rodata : ALIGN(8) {\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\n        *(.rodata1)\n    } AT > sram = 0\n\n\t\/* BSS. *\/\n\t.bss : {\n\t\t_bssStart_pa = .;\n\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\n\t\t. = ALIGN(4);\n\t\t_bssEnd_pa = .;\n\t} AT > sram\n\n\t\/* Stack. *\/\n\t.stack : ALIGN(4) {\n        . += _stackSize;\n\t} AT > sram\n\n\t\/* Calculate physical addresses of .bss and .stack for startup code. *\/\n\t_stackStart_pa = _bssEnd_pa + SIZEOF(.stack) - 4;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nENTRY(_start)\n\nMEMORY {\n\tddr (rwx)      :      ORIGIN = 0x00000000, LENGTH = 512M       \/* External DDR3 RAM *\/\n    sram (rwx)     :      ORIGIN = 0x402f0400, LENGTH = 32K        \/* Internal on-chip SRAM *\/\n}\n\n_bootStart_vma = ORIGIN(sram); \/* Kernel .boot VMA should be the same as LMA, as MMU is not configured. *\/\n_textStart_vma = 0x80000000;   \/* Kernel .text starts at 2 GB. *\/\n_stackSize     = 0x1000;       \/* Stak size is 4KB.*\/\n\nSECTIONS {\n    \/* Starup code. *\/\n    .boot _bootStart_vma : {\n        _bootStart_lma = .;\n\n        *(.boot)\n\n        _bootEnd_lma = .;\n    } AT > sram\n\n    \/* Kernel code. *\/\n    \/* .text _textStart_vma : *\/\n    .text : { \/* TODO: change to above in future. *\/\n        _textStart_lma = .;\n\n        *(.text)                \/* .text sections (code). *\/\n        *(.text*)               \/* .text* sections (code) - this will merge all symbols in .text into one section. *\/\n        *(.glue_7)              \/* Glue arm to thumb code. *\/\n        *(.glue_7t)             \/* Glue thumb to arm code. *\/\n        *(.eh_frame)\n        KEEP (*(.init))\n        KEEP (*(.fini))\n\n        _textEnd_lma = .;\n    } AT > sram \/* TODO: change to ddr in future. *\/\n\n    \/* Constructors and destructors. *\/\n\t.ctors : {\n\t\tKEEP (*crtbegin*.o(.ctors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t} AT > sram \/* TODO: change to ddr in future. *\/\n\n\t.dtors : {\n\t\tKEEP (*crtbegin*.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t} AT > sram \/* TODO: change to ddr in future. *\/\n\n    \/* Data. *\/\n\t.data : {\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t} AT > sram = 0\n\t\n\t\/* Read only data *\/\n\t.rodata : ALIGN(8) {\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\n        *(.rodata1)\n    } AT > sram = 0\n\n\t\/* BSS. *\/\n\t.bss : {\n\t\t_bssStart_lma = .;\n\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\n\t\t. = ALIGN(4);\n\t\t_bssEnd_lma = .;\n\t} AT > sram\n\n\t\/* Stack. *\/\n\t.stack : ALIGN(4) {\n        . += _stackSize;\n\t} AT > sram\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"85fdf58e8643d2ab55227cb0a51775680c1bdc73","subject":"Modify PUF memory address.","message":"Modify PUF memory address.\n","repos":"prplfoundation\/prpl-hypervisor,prplfoundation\/prpl-hypervisor,prplfoundation\/prpl-hypervisor,prplfoundation\/prpl-hypervisor,prplfoundation\/prpl-hypervisor,prplfoundation\/prpl-hypervisor","old_file":"bare-metal-apps\/lib\/pic32mz.ld","new_file":"bare-metal-apps\/lib\/pic32mz.ld","new_contents":"OUTPUT_FORMAT(\"elf32-tradlittlemips\")\nENTRY(_entry)\n\nMEMORY \n{\nflash\t\t(rx)   : ORIGIN = 0x9d000000, LENGTH = 128K\t\/* Flash area*\/\nram\t\t(rw!x) : ORIGIN = 0x80000000, LENGTH = 127K\t\/* RAM area. *\/\npuf\t\t(rw!x) : ORIGIN = 0x8001FC00, LENGTH = 1K\t\/* PUF area. *\/\n}\n\n\/* define a global symbol _stack  *\/\n\n_stack = ORIGIN(ram) + LENGTH(ram);\n\n_puf_address = ORIGIN(puf);\n\n\/* now define the output sections  *\/\n\nSECTIONS \n{\n\t.text :\n\t{\n\t\t*(.exception)\n\t\t. = 0x200;\n\t\t*(.vector0)\n\t\t. = 0x1000;\n\t\t_text = .;\n\t\t*(.text)\n\t        *(.text.*)\n\t\t_etext = .;\n\t} > flash\n\n    .MIPS.abiflags : {\n        __MIPS_abiflags_start = .;\n        *(.MIPS.abiflags)\n        __MIPS_abiflags_end = .;\n    } > flash\n\n\t.rodata :\n\t{\n\t\t_rodata = .;\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t_erodata = .;\n\t} > flash\n\n\t.data : AT (ADDR (.rodata) + SIZEOF (.rodata))\n\t{\n\t\t_data = .;\n\t\t*(.data)\n\t\t*(.data.*)\n\t\t_gp = .;\n\t\t*(.sdata)\n\t\t*(.sdata.*)\n\t\t. = ALIGN(16); \n\t} > ram\n\n\t_edata = .;\n\n\t.bss :\n\t{\n\t\t_bss_start = .; \n\t\t*(.bss) \n\t\t*(.bss.*)\n\t\t*(.sbss) \n\t\t*(.sbss.*)\n\t\t. = ALIGN(4);\n\t\t_bss_end = . ;\n\t} > ram\n\n}\n\t_end = .;\n\n","old_contents":"OUTPUT_FORMAT(\"elf32-tradlittlemips\")\nENTRY(_entry)\n\nMEMORY \n{\nflash\t\t(rx)   : ORIGIN = 0x9d000000, LENGTH = 128K\t\/* Flash area*\/\nram\t\t(rw!x) : ORIGIN = 0x80000000, LENGTH = 127K\t\/* RAM area. *\/\npuf\t\t(rw!x) : ORIGIN = 0x8000FC00, LENGTH = 1K\t\/* PUF area. *\/\n}\n\n\/* define a global symbol _stack  *\/\n\n_stack = ORIGIN(ram) + LENGTH(ram);\n\n_puf_address = ORIGIN(puf);\n\n\/* now define the output sections  *\/\n\nSECTIONS \n{\n\t.text :\n\t{\n\t\t*(.exception)\n\t\t. = 0x200;\n\t\t*(.vector0)\n\t\t. = 0x1000;\n\t\t_text = .;\n\t\t*(.text)\n\t        *(.text.*)\n\t\t_etext = .;\n\t} > flash\n\n    .MIPS.abiflags : {\n        __MIPS_abiflags_start = .;\n        *(.MIPS.abiflags)\n        __MIPS_abiflags_end = .;\n    } > flash\n\n\t.rodata :\n\t{\n\t\t_rodata = .;\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t_erodata = .;\n\t} > flash\n\n\t.data : AT (ADDR (.rodata) + SIZEOF (.rodata))\n\t{\n\t\t_data = .;\n\t\t*(.data)\n\t\t*(.data.*)\n\t\t_gp = .;\n\t\t*(.sdata)\n\t\t*(.sdata.*)\n\t\t. = ALIGN(16); \n\t} > ram\n\n\t_edata = .;\n\n\t.bss :\n\t{\n\t\t_bss_start = .; \n\t\t*(.bss) \n\t\t*(.bss.*)\n\t\t*(.sbss) \n\t\t*(.sbss.*)\n\t\t. = ALIGN(4);\n\t\t_bss_end = . ;\n\t} > ram\n\n}\n\t_end = .;\n\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"7b6c0beacb75ebcdb78171e423b2bfcc63a9b2c9","subject":"Change comments","message":"Change comments\n","repos":"tianzhihen\/openmv,kwagyeman\/openmv,kwagyeman\/openmv,tianzhihen\/openmv,iabdalkader\/openmv,openmv\/openmv,SmartArduino\/openmv,openmv\/openmv,kwagyeman\/openmv,iabdalkader\/openmv,openmv\/openmv,iabdalkader\/openmv,iabdalkader\/openmv,kwagyeman\/openmv,SmartArduino\/openmv,openmv\/openmv,tianzhihen\/openmv,SmartArduino\/openmv,tianzhihen\/openmv,SmartArduino\/openmv","old_file":"src\/stm32f4xx.ld","new_file":"src\/stm32f4xx.ld","new_contents":"\/**\n *  Linker script for STM32F4xx Devices with 1MB FLASH, 192KB RAM (64KB CCM)\n *\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K\n  FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 512K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n  CCM (w!rx)      : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Highest address of the user mode stack *\/\n_estack     = 0x10010000; \/* Stack is allocated on CCM block *\/\n\n_ram_end   = 0x10010000; \/* 64KB CCM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_stack_size = 0x1300; \/* required amount of stack *\/\n_heap_size  = 0x8000; \/* required amount of heap *\/\n_cache_size = 0x4000; \/* required amount of cache *\/\n\n_main_ram_start = 0x20000000;\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH_ISR\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n    _exit = .;\n  } >FLASH_TEXT\n\n   \/* used by the startup to initialize data *\/\n   _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    _ram_start = .;\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >CCM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n    _bss_end = _ebss; \/* for gccollect *\/\n  } >CCM\n\n  ._heap :\n  {\n    . = ALIGN(4);\n    _heap_start = .;\n    . = . + _heap_size;\n    . = ALIGN(4);\n    _heap_end  = .;\n  } >CCM\n\n  \/* Make sure there is enough RAM left for the stack *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _cache_size;\n    . = . + _stack_size;\n    . = ALIGN(4);\n  } >CCM\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/**\n *  Linker script for STM32F4xx Devices with 1MB FLASH, 192KB RAM (64KB CCM)\n *\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K\n  FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 512K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n  CCM (w!rx)      : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Highest address of the user mode stack *\/\n_estack     = 0x10010000; \/* Stack is allocated on CCM block *\/\n\n_ram_end   = 0x10010000; \/* 64KB CCM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_stack_size = 0x1300; \/* required amount of stack *\/\n_heap_size  = 0x8000; \/* 0xC800 required amount of heap *\/\n_cache_size = 0x4000; \/* 0x4000 required amount of cache *\/\n\n_main_ram_start = 0x20000000;\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH_ISR\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n    _exit = .;\n  } >FLASH_TEXT\n\n   \/* used by the startup to initialize data *\/\n   _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    _ram_start = .;\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >CCM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n    _bss_end = _ebss; \/* for gccollect *\/\n  } >CCM\n\n  ._heap :\n  {\n    . = ALIGN(4);\n    _heap_start = .;\n    . = . + _heap_size;\n    . = ALIGN(4);\n    _heap_end  = .;\n  } >CCM\n\n  \/* Make sure there is enough RAM left for the stack *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _cache_size;\n    . = . + _stack_size;\n    . = ALIGN(4);\n  } >CCM\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"15d069a7fd90726117cf80a57d02ff7c2bac4308","subject":"The linker script will now put main at address 0 if it exists.","message":"The linker script will now put main at address 0 if it exists.\n","repos":"SebastianBoe\/turborav,SebastianBoe\/turborav,SebastianBoe\/turborav,SebastianBoe\/turborav,SebastianBoe\/turborav","old_file":"hw\/core\/src\/misc\/turborav.ld","new_file":"hw\/core\/src\/misc\/turborav.ld","new_contents":"\/*\n\n    A linker script that fits Turborav's weird memory layout\n    requirements. See MemoryMapUtil.scala for details about the memory\n    layout.\n\n*\/\n\nMEMORY\n{\n    ROM : ORIGIN = 0x00000000, LENGTH = 256M\n    RAM : ORIGIN = 0x10000000, LENGTH = 256M\n}\n\nREGION_ALIAS(\"REGION_TEXT\"  , ROM);\nREGION_ALIAS(\"REGION_RODATA\", ROM);\n\nREGION_ALIAS(\"REGION_DATA\"  , RAM);\nREGION_ALIAS(\"REGION_BSS\"   , RAM);\n\nSECTIONS\n{\n    .text :\n    {\n        *(.text.startup)\n        *(.text)\n    } > REGION_TEXT\n    .rodata :\n    {\n        *(.rodata)\n        rodata_end = .;\n    } > REGION_RODATA\n    .data : AT (rodata_end)\n    {\n        data_start = .;\n        *(.data)\n        data_end = .;\n    } > REGION_DATA\n    data_size = SIZEOF(.data);\n    data_load_start = LOADADDR(.data);\n    .bss :\n    {\n        *(.bss)\n    } > REGION_BSS\n}\n","old_contents":"\/*\n\n    A linker script that fits Turborav's weird memory layout\n    requirements. See MemoryMapUtil.scala for details about the memory\n    layout.\n\n*\/\n\nMEMORY\n{\n    ROM : ORIGIN = 0x00000000, LENGTH = 256M\n    RAM : ORIGIN = 0x10000000, LENGTH = 256M\n}\n\nREGION_ALIAS(\"REGION_TEXT\"  , ROM);\nREGION_ALIAS(\"REGION_RODATA\", ROM);\n\nREGION_ALIAS(\"REGION_DATA\"  , RAM);\nREGION_ALIAS(\"REGION_BSS\"   , RAM);\n\nSECTIONS\n{\n    .text :\n    {\n        *(.text)\n    } > REGION_TEXT\n    .rodata :\n    {\n        *(.rodata)\n        rodata_end = .;\n    } > REGION_RODATA\n    .data : AT (rodata_end)\n    {\n        data_start = .;\n        *(.data)\n        data_end = .;\n    } > REGION_DATA\n    data_size = SIZEOF(.data);\n    data_load_start = LOADADDR(.data);\n    .bss :\n    {\n        *(.bss)\n    } > REGION_BSS\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"a6d1456d8cd22d0ff569069a2d6295fe65f864cd","subject":"template.cortexm: FLASH ORIGIN=0x0","message":"template.cortexm: FLASH ORIGIN=0x0\n","repos":"gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins","old_file":"ilg.gnuarmeclipse.templates.cortexm\/templates\/cortexm_project\/ldscripts\/mem.ld","new_file":"ilg.gnuarmeclipse.templates.cortexm\/templates\/cortexm_project\/ldscripts\/mem.ld","new_contents":"\/*\n * Memory Spaces Definitions.\n *\n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\n * The values below can be addressed in further linker scripts\n * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\n *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = $(CMflashSize)K\n  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = $(CMramSize)K\n\n  \/*\n   * Optional sections; define the origin and length to match\n   * the the specific requirements of your hardware. The zero\n   * length prevents inadvertent allocation.\n   *\/\n  CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 0\n  FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n}\n\n\/*\n * For external ram use something like:\n *  RAM (xrw) : ORIGIN = 0x64000000, LENGTH = 2048K\n *\n * For special RAM areas use something like:\n *  MEMORY_ARRAY (xrw)  : ORIGIN = 0x20002000, LENGTH = 32\n *\/\n","old_contents":"\/*\n * Memory Spaces Definitions.\n *\n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\n * The values below can be addressed in further linker scripts\n * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\n *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = $(CMflashSize)K\n  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = $(CMramSize)K\n\n  \/*\n   * Optional sections; define the origin and length to match\n   * the the specific requirements of your hardware. The zero\n   * length prevents inadvertent allocation.\n   *\/\n  CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 0\n  FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n}\n\n\/*\n * For external ram use something like:\n *  RAM (xrw) : ORIGIN = 0x64000000, LENGTH = 2048K\n *\n * For special RAM areas use something like:\n *  MEMORY_ARRAY (xrw)  : ORIGIN = 0x20002000, LENGTH = 32\n *\/\n","returncode":0,"stderr":"","license":"epl-1.0","lang":"Linker Script"}
{"commit":"d5694711a9bc8329fb536d381d208f6192d51f9e","subject":"Copyright header","message":"Copyright header\n","repos":"hugwijst\/zinc,aethaniel\/zinc,phil-opp\/zinc,mcoffin\/zinc,hackndev\/zinc,mcoffin\/zinc,ntwyman\/zinc,posborne\/zinc,phil-opp\/zinc,troplin\/zinc,mcoffin\/zinc,ntwyman\/zinc,dirvine\/zinc,phil-opp\/zinc,mcoffin\/zinc,posborne\/zinc,posborne\/zinc,hackndev\/zinc,tempbottle\/zinc,placrosse\/zinc,ryankurte\/zinc,dirvine\/zinc,richo\/zinc,ryankurte\/zinc,troplin\/zinc,ntwyman\/zinc,tempbottle\/zinc,richo\/zinc,phil-opp\/zinc,flxo\/zinc,placrosse\/zinc,0xc0170\/zinc,tempbottle\/zinc,hackndev\/zinc,ntwyman\/zinc,0xc0170\/zinc,farcaller\/zinc,farcaller\/zinc,posborne\/zinc,phil-opp\/zinc,ntwyman\/zinc,troplin\/zinc,hackndev\/zinc,ryankurte\/zinc,farcaller\/zinc,darayus\/zinc,richo\/zinc,farcaller\/zinc,placrosse\/zinc,mcoffin\/zinc,gapry\/zinc,dirvine\/zinc,darayus\/zinc,aethaniel\/zinc,hugwijst\/zinc,gapry\/zinc,richo\/zinc,dirvine\/zinc,tempbottle\/zinc,richo\/zinc,farcaller\/zinc,flxo\/zinc,troplin\/zinc,ryankurte\/zinc,placrosse\/zinc,dirvine\/zinc,placrosse\/zinc,troplin\/zinc,tempbottle\/zinc,hackndev\/zinc,posborne\/zinc,ryankurte\/zinc","old_file":"src\/hal\/cortex_m3\/armmem.ld","new_file":"src\/hal\/cortex_m3\/armmem.ld","new_contents":"\/* Zinc, the bare metal stack for rust.\n\/\/ Copyright 2014 Ben Harris <mail@bharr.is>\n\/\/\n\/\/ Licensed under the Apache License, Version 2.0 (the \"License\");\n\/\/ you may not use this file except in compliance with the License.\n\/\/ You may obtain a copy of the License at\n\/\/\n\/\/     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\/\/\n\/\/ Unless required by applicable law or agreed to in writing, software\n\/\/ distributed under the License is distributed on an \"AS IS\" BASIS,\n\/\/ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n\/\/ See the License for the specific language governing permissions and\n\/\/ limitations under the License.\n*\/\n\narmmem_SYSTICK    = 0xE000E010;\n\narmmem_NVIC_ISER  = 0xE000E100;\narmmem_NVIC_ICER  = 0xE000E180;\narmmem_NVIC_ISPR  = 0xE000E200;\narmmem_NVIC_ICPR  = 0xE000E280;\narmmem_NVIC_IABR  = 0xE000E300;\narmmem_NVIC_IPR   = 0xE000E400;\narmmem_NVIC_STIR  = 0xE000EF00;\n\narmmem_SCB_ACTLR  = 0xE000E008;\narmmem_SCB        = 0xE000ED00;\n\narmmem_MPU        = 0xE000ED90;\n","old_contents":"armmem_SYSTICK    = 0xE000E010;\n\narmmem_NVIC_ISER  = 0xE000E100;\narmmem_NVIC_ICER  = 0xE000E180;\narmmem_NVIC_ISPR  = 0xE000E200;\narmmem_NVIC_ICPR  = 0xE000E280;\narmmem_NVIC_IABR  = 0xE000E300;\narmmem_NVIC_IPR   = 0xE000E400;\narmmem_NVIC_STIR  = 0xE000EF00;\n\narmmem_SCB_ACTLR  = 0xE000E008;\narmmem_SCB        = 0xE000ED00;\n\narmmem_MPU        = 0xE000ED90;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3ee626f36ed9c2ad0d259fda164aa2d880f2c436","subject":"espressif: Fix ESP32-C3 support for booting signed apps","message":"espressif: Fix ESP32-C3 support for booting signed apps\n\nSigned-off-by: Gustavo Henrique Nihei <42b1270cfd1a4f11d4db08d9d441d5d8452cd3b6@espressif.com>\n","repos":"ATmobica\/mcuboot,runtimeco\/mcuboot,runtimeco\/mcuboot,ATmobica\/mcuboot,runtimeco\/mcuboot,ATmobica\/mcuboot,runtimeco\/mcuboot,runtimeco\/mcuboot,ATmobica\/mcuboot,ATmobica\/mcuboot","old_file":"boot\/espressif\/port\/esp32c3\/ld\/bootloader.ld","new_file":"boot\/espressif\/port\/esp32c3\/ld\/bootloader.ld","new_contents":"\/*\n * Linker file used to link the bootloader.\n *\/\n\nMEMORY\n{\n  iram_seg (RWX) :                  org = 0x403CB000, len = 0x5000\n  iram_loader_seg (RWX) :           org = 0x403D0000, len = 0x6000\n  dram_seg (RW) :                   org = 0x3FCD6000, len = 0x7000\n}\n\n\/*  Default entry point:  *\/\nENTRY(main);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *libhal.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_flash_config_esp32c3.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)\n    *libhal.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)\n    *libhal.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_panic.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_soc.*(.literal .text .literal.* .text.*)\n    *libhal.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libhal.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libhal.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)\n    *libhal.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libhal.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libhal.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)\n    *libhal.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)\n    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)\n    *libhal.a:esp_efuse_table.*(.literal .text .literal.* .text.*)\n    *libhal.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)\n    *libhal.a:esp_efuse_api.*(.literal .text .literal.* .text.*)\n    *libhal.a:esp_efuse_utility.*(.literal .text .literal.* .text.*)\n    *libhal.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*)\n    *esp_mcuboot.*(.literal .text .literal.* .text.*)\n    *esp_loader.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _dram_start = ABSOLUTE(.);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _dram_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","old_contents":"\/*\n * Linker file used to link the bootloader.\n *\/\n\nMEMORY\n{\n  iram_seg (RWX) :    org = 0x403CA000, len = 0x6000\n  iram_loader_seg (RWX) : org = 0x403D0000, len = 0x2000\n  dram_seg (RW) :     org = 0x3FCD6000, len = 0x6000\n}\n\n\/*  Default entry point:  *\/\nENTRY(main);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *libhal.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libhal.a:bootloader_flash_config_esp32c3.*(.literal .text .literal.* .text.*)\n    *esp_mcuboot.*(.literal .text .literal.* .text.*)\n    *esp_loader.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _dram_start = ABSOLUTE(.);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _dram_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"20ea05cc3190f5cb737e8d862282c9ec3b770001","subject":"Delete STM32F401XE.ld","message":"Delete STM32F401XE.ld\n\nDuplicate file causing collisions when cloning the repo on a case-insensitive OS (e.g. Windows).","repos":"mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed","old_file":"targets\/TARGET_STM\/TARGET_STM32F4\/TARGET_STM32F401xE\/TOOLCHAIN_GCC_ARM\/STM32F401XE.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32F4\/TARGET_STM32F401xE\/TOOLCHAIN_GCC_ARM\/STM32F401XE.ld","new_contents":"","old_contents":"\/* Linker script to configure memory regions. *\/\n\/*\n * SPDX-License-Identifier: BSD-3-Clause\n ******************************************************************************\n * @attention\n *\n * Copyright (c) 2016-2020 STMicroelectronics.\n * All rights reserved.\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n *                        opensource.org\/licenses\/BSD-3-Clause\n *\n ******************************************************************************\n*\/\n\n#include \"..\/cmsis_nvic.h\"\n\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START  MBED_ROM_START\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE  MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)\n    \/* This value is normally defined by the tools\n       to 0x1000 for bare metal and 0x400 for RTOS *\/\n    #define MBED_CONF_TARGET_BOOT_STACK_SIZE  0x400\n#endif\n\n\/* Round up VECTORS_SIZE to 8 bytes *\/\n#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)\n\nMEMORY\n{\n    FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n    RAM (rwx)    : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    \/* Uninitialized data section\n     * This region is not initialized by the C\/C++ library and can be used to\n     * store state across soft reboots. *\/\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        PROVIDE(end = .);\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b7d04f6f5945a650ba150e40d42dfcb99033e2be","subject":"Revert change of managed heap back to external RAM (#702)","message":"Revert change of managed heap back to external RAM (#702)\n\n","repos":"nanoframework\/nf-interpreter,Eclo\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter,Eclo\/nf-interpreter,nanoframework\/nf-interpreter","old_file":"targets\/CMSIS-OS\/ChibiOS\/ST_STM32F429I_DISCOVERY\/nanoCLR\/STM32F429xI_CLR.ld","new_file":"targets\/CMSIS-OS\/ChibiOS\/ST_STM32F429I_DISCOVERY\/nanoCLR\/STM32F429xI_CLR.ld","new_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio.  All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n\/*\n * ST32F429xI memory setup.\n * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.\n *\/\nMEMORY\n{\n    flash       : org = 0x08008000, len = 2M - 32k - 1408k      \/* flash size less the space reserved for nanoBooter and application deployment*\/\n    config      : org = 0x00000000, len = 0                     \/* space reserved for configuration block *\/\n    deployment  : org = 0x080A0000, len = 1408k                 \/* space reserved for application deployment *\/\n    ramvt       : org = 0x00000000, len = 0                     \/* initial RAM address is reserved for a copy of the vector table *\/\n    ram0        : org = 0x20000000, len = 192k                  \/* SRAM1 + SRAM2 + SRAM3 *\/\n    ram1        : org = 0x20000000, len = 112k                  \/* SRAM1 *\/\n    ram2        : org = 0x2001C000, len = 16k                   \/* SRAM2 *\/\n    ram3        : org = 0x20020000, len = 64k                   \/* SRAM3 *\/\n    ram4        : org = 0x10000000, len = 64k                   \/* CCM SRAM *\/\n    ram5        : org = 0x40024000, len = 4k                    \/* BCKP SRAM *\/\n    ram6        : org = 0x00000000, len = 0\n    ram7        : org = 0x00000000, len = 0\n    ext_ram     : org = 0xD0000000, len = 8M                    \/* external SDRAM *\/\n}\n\n\/* For each data\/text section two region are defined, a virtual region\n   and a load region (_LMA suffix).*\/\n\n\/* Flash region to be used for exception vectors.*\/\nREGION_ALIAS(\"VECTORS_FLASH\", flash);\nREGION_ALIAS(\"VECTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for constructors and destructors.*\/\nREGION_ALIAS(\"XTORS_FLASH\", flash);\nREGION_ALIAS(\"XTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for code text.*\/\nREGION_ALIAS(\"TEXT_FLASH\", flash);\nREGION_ALIAS(\"TEXT_FLASH_LMA\", flash);\n\n\/* Flash region to be used for read only data.*\/\nREGION_ALIAS(\"RODATA_FLASH\", flash);\nREGION_ALIAS(\"RODATA_FLASH_LMA\", flash);\n\n\/* Flash region to be used for various.*\/\nREGION_ALIAS(\"VARIOUS_FLASH\", flash);\nREGION_ALIAS(\"VARIOUS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for RAM(n) initialization data.*\/\nREGION_ALIAS(\"RAM_INIT_FLASH_LMA\", flash);\n\n\/* RAM region to be used for Main stack. This stack accommodates the processing\n   of all exceptions and interrupts.*\/\nREGION_ALIAS(\"MAIN_STACK_RAM\", ram0);\n\n\/* RAM region to be used for the process stack. This is the stack used by\n   the main() function.*\/\nREGION_ALIAS(\"PROCESS_STACK_RAM\", ram0);\n\n\/* RAM region to be used for data segment.*\/\nREGION_ALIAS(\"DATA_RAM\", ram0);\nREGION_ALIAS(\"DATA_RAM_LMA\", flash);\n\n\/* RAM region to be used for BSS segment.*\/\nREGION_ALIAS(\"BSS_RAM\", ram0);\n\n\/* RAM region to be used for the default heap.*\/\nREGION_ALIAS(\"HEAP_RAM\", ram4);\n\n\/* RAM region to be used for the nanoFramework CLR managed heap.*\/\nREGION_ALIAS(\"CLR_MANAGED_HEAP_RAM\", ext_ram);\n\nINCLUDE rules.ld\n","old_contents":"\/*\n\/\/\n\/\/ Copyright (c) 2017 The nanoFramework project contributors\n\/\/ Portions Copyright (c) 2006..2015 Giovanni Di Sirio.  All rights reserved.\n\/\/ See LICENSE file in the project root for full license information.\n\/\/\n*\/\n\n\/*\n * ST32F429xI memory setup.\n * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.\n *\/\nMEMORY\n{\n    flash       : org = 0x08008000, len = 2M - 32k - 1408k      \/* flash size less the space reserved for nanoBooter and application deployment*\/\n    config      : org = 0x00000000, len = 0                     \/* space reserved for configuration block *\/\n    deployment  : org = 0x080A0000, len = 1408k                 \/* space reserved for application deployment *\/\n    ramvt       : org = 0x00000000, len = 0                     \/* initial RAM address is reserved for a copy of the vector table *\/\n    ram0        : org = 0x20000000, len = 192k                  \/* SRAM1 + SRAM2 + SRAM3 *\/\n    ram1        : org = 0x20000000, len = 112k                  \/* SRAM1 *\/\n    ram2        : org = 0x2001C000, len = 16k                   \/* SRAM2 *\/\n    ram3        : org = 0x20020000, len = 64k                   \/* SRAM3 *\/\n    ram4        : org = 0x10000000, len = 64k                   \/* CCM SRAM *\/\n    ram5        : org = 0x40024000, len = 4k                    \/* BCKP SRAM *\/\n    ram6        : org = 0x00000000, len = 0\n    ram7        : org = 0x00000000, len = 0\n    ext_ram     : org = 0xD0000000, len = 8M                    \/* external SDRAM *\/\n}\n\n\/* For each data\/text section two region are defined, a virtual region\n   and a load region (_LMA suffix).*\/\n\n\/* Flash region to be used for exception vectors.*\/\nREGION_ALIAS(\"VECTORS_FLASH\", flash);\nREGION_ALIAS(\"VECTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for constructors and destructors.*\/\nREGION_ALIAS(\"XTORS_FLASH\", flash);\nREGION_ALIAS(\"XTORS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for code text.*\/\nREGION_ALIAS(\"TEXT_FLASH\", flash);\nREGION_ALIAS(\"TEXT_FLASH_LMA\", flash);\n\n\/* Flash region to be used for read only data.*\/\nREGION_ALIAS(\"RODATA_FLASH\", flash);\nREGION_ALIAS(\"RODATA_FLASH_LMA\", flash);\n\n\/* Flash region to be used for various.*\/\nREGION_ALIAS(\"VARIOUS_FLASH\", flash);\nREGION_ALIAS(\"VARIOUS_FLASH_LMA\", flash);\n\n\/* Flash region to be used for RAM(n) initialization data.*\/\nREGION_ALIAS(\"RAM_INIT_FLASH_LMA\", flash);\n\n\/* RAM region to be used for Main stack. This stack accommodates the processing\n   of all exceptions and interrupts.*\/\nREGION_ALIAS(\"MAIN_STACK_RAM\", ram0);\n\n\/* RAM region to be used for the process stack. This is the stack used by\n   the main() function.*\/\nREGION_ALIAS(\"PROCESS_STACK_RAM\", ram0);\n\n\/* RAM region to be used for data segment.*\/\nREGION_ALIAS(\"DATA_RAM\", ram0);\nREGION_ALIAS(\"DATA_RAM_LMA\", flash);\n\n\/* RAM region to be used for BSS segment.*\/\nREGION_ALIAS(\"BSS_RAM\", ram0);\n\n\/* RAM region to be used for the default heap.*\/\nREGION_ALIAS(\"HEAP_RAM\", ram4);\n\n\/* RAM region to be used for the nanoFramework CLR managed heap.*\/\nREGION_ALIAS(\"CLR_MANAGED_HEAP_RAM\", ram0);\n\nINCLUDE rules.ld\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5c586ee6b231837c80bbb9439dcc80f476eefb21","subject":"nios2: linker.ld: ensure reset code isn't discarded","message":"nios2: linker.ld: ensure reset code isn't discarded\n\nThis isn't directly referenced by other code in the binary,\nit just sits at a magic memory address. Make sure gc-sections\ndoesn't throw it away.\n\nChange-Id: I1c00a163dbf2eb4866ebadc7f1d70bcc6845b8d1\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"ldts\/zephyr,zephyrproject-rtos\/zephyr,mirzak\/zephyr-os,kraj\/zephyr,ldts\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,nashif\/zephyr,sharronliu\/zephyr,zephyrproject-rtos\/zephyr,fbsder\/zephyr,kraj\/zephyr,finikorg\/zephyr,rsalveti\/zephyr,mirzak\/zephyr-os,mirzak\/zephyr-os,ldts\/zephyr,runchip\/zephyr-cc3220,runchip\/zephyr-cc3220,zephyriot\/zephyr,fbsder\/zephyr,explora26\/zephyr,nashif\/zephyr,aceofall\/zephyr-iotos,holtmann\/zephyr,punitvara\/zephyr,erwango\/zephyr,kraj\/zephyr,bboozzoo\/zephyr,runchip\/zephyr-cc3200,rsalveti\/zephyr,runchip\/zephyr-cc3200,tidyjiang8\/zephyr-doc,mbolivar\/zephyr,finikorg\/zephyr,fractalclone\/zephyr-riscv,Vudentz\/zephyr,ldts\/zephyr,fractalclone\/zephyr-riscv,fbsder\/zephyr,punitvara\/zephyr,runchip\/zephyr-cc3200,aceofall\/zephyr-iotos,Vudentz\/zephyr,holtmann\/zephyr,fbsder\/zephyr,rsalveti\/zephyr,runchip\/zephyr-cc3220,punitvara\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,tidyjiang8\/zephyr-doc,pklazy\/zephyr,rsalveti\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3220,mbolivar\/zephyr,explora26\/zephyr,rsalveti\/zephyr,aceofall\/zephyr-iotos,zephyrproject-rtos\/zephyr,mirzak\/zephyr-os,bboozzoo\/zephyr,kraj\/zephyr,holtmann\/zephyr,galak\/zephyr,mbolivar\/zephyr,aceofall\/zephyr-iotos,bboozzoo\/zephyr,erwango\/zephyr,runchip\/zephyr-cc3220,nashif\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,Vudentz\/zephyr,bigdinotech\/zephyr,bboozzoo\/zephyr,GiulianoFranchetto\/zephyr,erwango\/zephyr,mbolivar\/zephyr,ldts\/zephyr,fbsder\/zephyr,pklazy\/zephyr,pklazy\/zephyr,nashif\/zephyr,zephyriot\/zephyr,explora26\/zephyr,erwango\/zephyr,runchip\/zephyr-cc3200,sharronliu\/zephyr,galak\/zephyr,bigdinotech\/zephyr,runchip\/zephyr-cc3200,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,bboozzoo\/zephyr,galak\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,bigdinotech\/zephyr,zephyrproject-rtos\/zephyr,pklazy\/zephyr,mirzak\/zephyr-os,fractalclone\/zephyr-riscv,sharronliu\/zephyr,tidyjiang8\/zephyr-doc,explora26\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,tidyjiang8\/zephyr-doc,tidyjiang8\/zephyr-doc,Vudentz\/zephyr,finikorg\/zephyr,bigdinotech\/zephyr,explora26\/zephyr,nashif\/zephyr,zephyriot\/zephyr,galak\/zephyr,bigdinotech\/zephyr,sharronliu\/zephyr,zephyriot\/zephyr,finikorg\/zephyr,erwango\/zephyr,sharronliu\/zephyr,holtmann\/zephyr,holtmann\/zephyr,fractalclone\/zephyr-riscv,fractalclone\/zephyr-riscv,pklazy\/zephyr,mbolivar\/zephyr","old_file":"include\/arch\/nios2\/linker.ld","new_file":"include\/arch\/nios2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specfic linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n}\n#endif\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#ifdef CONFIG_CPLUSPLUS\n    SECTION_PROLOGUE(_CTOR_SECTION_NAME, ,)\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __CTOR_LIST__ must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first elment of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT_BY_NAME(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(init_array, (OPTIONAL),)\n        {\n            . = ALIGN(4);\n            __init_array_start = .;\n            KEEP(*(SORT_BY_NAME(\".init_array*\")))\n            __init_array_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(devconfig, (OPTIONAL),)\n        {\n                __devconfig_start = .;\n                *(\".devconfig.*\")\n                KEEP(*(SORT_BY_NAME(\".devconfig*\")))\n                __devconfig_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * XXX any space between _RAM_ADDR and ALT_CPU_EXCEPTION_ADDR is lost,\n     * currently 0x20 bytes\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_AT_PROLOGUE(_EXCEPTION_SECTION_NAME,,, __data_rom_start)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            \/* FIXME these KEEP()s shouldn't be necessary *\/\n            KEEP(*(\".exception.entry.*\"))\n            KEEP(*(\".exception.other.*\"))\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n        *(.data)\n        *(\".data.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(initlevel, (OPTIONAL),)\n        {\n                DEVICE_INIT_SECTIONS()\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_list, (OPTIONAL),)\n        {\n                _k_task_list_start = .;\n                        *(._k_task_list.public.*)\n                        *(._k_task_list.private.*)\n                _k_task_list_idle_start = .;\n                        *(._k_task_list.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n                _k_task_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_ptr, (OPTIONAL),)\n        {\n                _k_task_ptr_start = .;\n                        *(._k_task_ptr.public.*)\n                        *(._k_task_ptr.private.*)\n                        *(._k_task_ptr.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n                _k_task_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_pipe_ptr, (OPTIONAL),)\n        {\n                _k_pipe_ptr_start = .;\n                        *(._k_pipe_ptr.public.*)\n                        *(._k_pipe_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n                _k_pipe_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_mem_map_ptr, (OPTIONAL),)\n        {\n                _k_mem_map_ptr_start = .;\n                        *(._k_mem_map_ptr.public.*)\n                        *(._k_mem_map_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n                _k_mem_map_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_event_list, (OPTIONAL),)\n        {\n                _k_event_list_start = .;\n                        *(._k_event_list.event.*)\n                KEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n                _k_event_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    __data_ram_end = .;\n\n    SECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    __bss_num_words = (__bss_end - __bss_start) >> 2;\n\n    GROUP_END(RAMABLE_REGION)\n\n    }\n\n#if CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specfic linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n}\n#endif\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        *(.reset.*)\n    } GROUP_LINK_IN(RESET)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#ifdef CONFIG_CPLUSPLUS\n    SECTION_PROLOGUE(_CTOR_SECTION_NAME, ,)\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __CTOR_LIST__ must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first elment of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT_BY_NAME(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(init_array, (OPTIONAL),)\n        {\n            . = ALIGN(4);\n            __init_array_start = .;\n            KEEP(*(SORT_BY_NAME(\".init_array*\")))\n            __init_array_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(devconfig, (OPTIONAL),)\n        {\n                __devconfig_start = .;\n                *(\".devconfig.*\")\n                KEEP(*(SORT_BY_NAME(\".devconfig*\")))\n                __devconfig_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * XXX any space between _RAM_ADDR and ALT_CPU_EXCEPTION_ADDR is lost,\n     * currently 0x20 bytes\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_AT_PROLOGUE(_EXCEPTION_SECTION_NAME,,, __data_rom_start)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            \/* FIXME these KEEP()s shouldn't be necessary *\/\n            KEEP(*(\".exception.entry.*\"))\n            KEEP(*(\".exception.other.*\"))\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n        *(.data)\n        *(\".data.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(initlevel, (OPTIONAL),)\n        {\n                DEVICE_INIT_SECTIONS()\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_list, (OPTIONAL),)\n        {\n                _k_task_list_start = .;\n                        *(._k_task_list.public.*)\n                        *(._k_task_list.private.*)\n                _k_task_list_idle_start = .;\n                        *(._k_task_list.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n                _k_task_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_ptr, (OPTIONAL),)\n        {\n                _k_task_ptr_start = .;\n                        *(._k_task_ptr.public.*)\n                        *(._k_task_ptr.private.*)\n                        *(._k_task_ptr.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n                _k_task_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_pipe_ptr, (OPTIONAL),)\n        {\n                _k_pipe_ptr_start = .;\n                        *(._k_pipe_ptr.public.*)\n                        *(._k_pipe_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n                _k_pipe_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_mem_map_ptr, (OPTIONAL),)\n        {\n                _k_mem_map_ptr_start = .;\n                        *(._k_mem_map_ptr.public.*)\n                        *(._k_mem_map_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n                _k_mem_map_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_event_list, (OPTIONAL),)\n        {\n                _k_event_list_start = .;\n                        *(._k_event_list.event.*)\n                KEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n                _k_event_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    __data_ram_end = .;\n\n    SECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    __bss_num_words = (__bss_end - __bss_start) >> 2;\n\n    GROUP_END(RAMABLE_REGION)\n\n    }\n\n#if CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5da8271997bfaf8142d25b7906f4986a40a3d5f2","subject":"move stack to CCMRAM","message":"move stack to CCMRAM\n","repos":"lkesteloot\/alice,lkesteloot\/alice,lkesteloot\/alice,lkesteloot\/alice,lkesteloot\/alice,lkesteloot\/alice","old_file":"alice3\/io_board\/stm32f4\/STM32F415RG_FLASH.ld","new_file":"alice3\/io_board\/stm32f4\/STM32F415RG_FLASH.ld","new_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F417IGHx Device with\n**                1024KByte FLASH, 128KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Ac6.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Ac6 permit registered System Workbench for MCU users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the System Workbench for MCU toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n\/* _estack = 0x2001FFFC; *\/    \/* end of RAM *\/\n_estack = 0x1000FFFC;    \/* end of CCMRAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0xD000;;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400;; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\nCCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  _siccmram = LOADADDR(.ccmram);\n\n  \/* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section,\n  * the startup code needs to be modified to copy the init-values.  \n  *\/\n  .ccmram :\n  {\n    . = ALIGN(4);\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\n  } >CCMRAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  heap_low = .;\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    heap_top = .;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n\n  \/* . = ALIGN(8); *\/\n  \/*heap_low = .; *\/\/* for _sbrk *\/\n  \/*. = . + 0x10000; *\/ \/* 64kB of heap memory *\/\n   \/* heap_top = .; *\/ \/* for _sbrk *\/\n  \/*  . = . + 0x10000; *\/ \/* 64kB of stack memory *\/\n    \/*  stack_top = .; *\/ \/* for startup.s *\/\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","old_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F417IGHx Device with\n**                1024KByte FLASH, 128KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Ac6.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Ac6 permit registered System Workbench for MCU users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the System Workbench for MCU toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x2001FFFC;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0xD000;;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400;; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\nCCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  _siccmram = LOADADDR(.ccmram);\n\n  \/* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section,\n  * the startup code needs to be modified to copy the init-values.  \n  *\/\n  .ccmram :\n  {\n    . = ALIGN(4);\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\n  } >CCMRAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  heap_low = .;\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    heap_top = .;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n\n  \/* . = ALIGN(8); *\/\n  \/*heap_low = .; *\/\/* for _sbrk *\/\n  \/*. = . + 0x10000; *\/ \/* 64kB of heap memory *\/\n   \/* heap_top = .; *\/ \/* for _sbrk *\/\n  \/*  . = . + 0x10000; *\/ \/* 64kB of stack memory *\/\n    \/*  stack_top = .; *\/ \/* for startup.s *\/\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4e830d843ae9271462ad27c1716fd32d30bed280","subject":"esp_wifi: Remove ieee80211_crypto_aes_128_cmac_decrypt from esp32c2 rom","message":"esp_wifi: Remove ieee80211_crypto_aes_128_cmac_decrypt from esp32c2 rom\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.ld","new_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.ld","new_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\nrtc_get_wakeup_cause = 0x40000020;\nrtc_select_apb_bridge = 0x40000024;\nrtc_unhold_all_pads = 0x40000028;\nets_is_print_boot = 0x4000002c;\nets_vprintf = 0x40000030;\nets_printf = 0x40000034;\nets_install_putc1 = 0x40000038;\nets_install_uart_printf = 0x4000003c;\nets_install_putc2 = 0x40000040;\nets_delay_us = 0x40000044;\nets_get_stack_info = 0x40000048;\nets_install_lock = 0x4000004c;\nUartRxString = 0x40000050;\nUartGetCmdLn = 0x40000054;\nuart_tx_one_char = 0x40000058;\nuart_tx_one_char2 = 0x4000005c;\nuart_rx_one_char = 0x40000060;\nuart_rx_one_char_block = 0x40000064;\nuart_rx_readbuff = 0x40000068;\nuartAttach = 0x4000006c;\nuart_tx_flush = 0x40000070;\nuart_tx_wait_idle = 0x40000074;\nuart_div_modify = 0x40000078;\nets_write_char_uart = 0x4000007c;\nuart_tx_switch = 0x40000080;\nmultofup = 0x40000084;\nsoftware_reset = 0x40000088;\nsoftware_reset_cpu = 0x4000008c;\nassist_debug_clock_enable = 0x40000090;\nassist_debug_record_enable = 0x40000094;\nclear_super_wdt_reset_flag = 0x40000098;\ndisable_default_watchdog = 0x4000009c;\nsend_packet = 0x400000a0;\nrecv_packet = 0x400000a4;\nGetUartDevice = 0x400000a8;\nUartDwnLdProc = 0x400000ac;\nGetSecurityInfoProc = 0x400000b0;\nUart_Init = 0x400000b4;\nets_set_user_start = 0x400000b8;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff4fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000bc;\nmz_free = 0x400000c0;\ntdefl_compress = 0x400000c4;\ntdefl_compress_buffer = 0x400000c8;\ntdefl_compress_mem_to_heap = 0x400000cc;\ntdefl_compress_mem_to_mem = 0x400000d0;\ntdefl_compress_mem_to_output = 0x400000d4;\ntdefl_get_adler32 = 0x400000d8;\ntdefl_get_prev_return_status = 0x400000dc;\ntdefl_init = 0x400000e0;\ntdefl_write_image_to_png_file_in_memory = 0x400000e4;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000e8;\ntinfl_decompress = 0x400000ec;\ntinfl_decompress_mem_to_callback = 0x400000f0;\ntinfl_decompress_mem_to_heap = 0x400000f4;\ntinfl_decompress_mem_to_mem = 0x400000f8;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 );\nPROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 );\nPROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 );\nPROVIDE( _esp_rom_spiflash_write = 0x4000011c );\nPROVIDE( _esp_rom_spiflash_read = 0x40000120 );\nPROVIDE( _esp_rom_spiflash_unlock = 0x40000124 );\nPROVIDE( _SPIEraseArea = 0x40000128 );\nPROVIDE( _SPI_write_enable = 0x4000012c );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000134 );\nPROVIDE( esp_rom_spiflash_write = 0x40000138 );\nPROVIDE( esp_rom_spiflash_read = 0x4000013c );\nPROVIDE( esp_rom_spiflash_unlock = 0x40000140 );\nPROVIDE( SPIEraseArea = 0x40000144 );\nPROVIDE( SPI_write_enable = 0x40000148 );\nPROVIDE( esp_rom_spiflash_config_param = 0x4000014c );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c );\nPROVIDE( esp_rom_spi_flash_update_id = 0x40000160 );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000164 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 );\nPROVIDE( esp_rom_spiflash_read_status = 0x4000016c );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000174 );\nPROVIDE( spi_flash_attach = 0x40000178 );\nPROVIDE( spi_flash_get_chip_size = 0x4000017c );\nPROVIDE( spi_flash_guard_set = 0x40000180 );\nPROVIDE( spi_flash_guard_get = 0x40000184 );\nPROVIDE( spi_flash_read_encrypted = 0x40000188 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x4000018c );\nPROVIDE( spi_flash_mmap_page_num_init = 0x40000190 );\nPROVIDE( spi_flash_mmap = 0x40000194 );\nPROVIDE( spi_flash_mmap_pages = 0x40000198 );\nPROVIDE( spi_flash_munmap = 0x4000019c );\nPROVIDE( spi_flash_mmap_dump = 0x400001a0 );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );\nPROVIDE( spi_flash_cache2phys = 0x400001ac );\nPROVIDE( spi_flash_phys2cache = 0x400001b0 );\nPROVIDE( spi_flash_disable_cache = 0x400001b4 );\nPROVIDE( spi_flash_restore_cache = 0x400001b8 );\nPROVIDE( spi_flash_cache_enabled = 0x400001bc );\nPROVIDE( spi_flash_enable_cache = 0x400001c0 );\nPROVIDE( spi_cache_mode_switch = 0x400001c4 );\nPROVIDE( spi_common_set_dummy_output = 0x400001c8 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001cc );\nPROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 );\nPROVIDE( SPILock = 0x400001d8 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001dc );\nPROVIDE( SPI_Common_Command = 0x400001e0 );\nPROVIDE( SPI_WakeUp = 0x400001e4 );\nPROVIDE( SPI_block_erase = 0x400001e8 );\nPROVIDE( SPI_chip_erase = 0x400001ec );\nPROVIDE( SPI_init = 0x400001f0 );\nPROVIDE( SPI_page_program = 0x400001f4 );\nPROVIDE( SPI_read_data = 0x400001f8 );\nPROVIDE( SPI_sector_erase = 0x400001fc );\nPROVIDE( SelectSpiFunction = 0x40000200 );\nPROVIDE( SetSpiDrvs = 0x40000204 );\nPROVIDE( Wait_SPI_Idle = 0x40000208 );\nPROVIDE( spi_dummy_len_fix = 0x4000020c );\nPROVIDE( Disable_QMode = 0x40000210 );\nPROVIDE( Enable_QMode = 0x40000214 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group hal_soc\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 );\nPROVIDE( spi_flash_hal_device_config = 0x4000021c );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 );\nPROVIDE( spi_flash_hal_common_command = 0x40000224 );\nPROVIDE( spi_flash_hal_read = 0x40000228 );\nPROVIDE( spi_flash_hal_erase_chip = 0x4000022c );\nPROVIDE( spi_flash_hal_erase_sector = 0x40000230 );\nPROVIDE( spi_flash_hal_erase_block = 0x40000234 );\nPROVIDE( spi_flash_hal_program_page = 0x40000238 );\nPROVIDE( spi_flash_hal_set_write_protect = 0x4000023c );\nPROVIDE( spi_flash_hal_host_idle = 0x40000240 );\nPROVIDE( spi_flash_hal_check_status = 0x40000244 );\nPROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 );\nPROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c );\nPROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 );\nPROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 );\nPROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 );\nPROVIDE( spi_flash_hal_resume = 0x4000025c );\nPROVIDE( spi_flash_hal_suspend = 0x40000260 );\nPROVIDE( spi_flash_encryption_hal_enable = 0x40000264 );\nPROVIDE( spi_flash_encryption_hal_disable = 0x40000268 );\nPROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c );\nPROVIDE( spi_flash_encryption_hal_done = 0x40000270 );\nPROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 );\nPROVIDE( spi_flash_encryption_hal_check = 0x40000278 );\nPROVIDE( wdt_hal_init = 0x4000027c );\nPROVIDE( wdt_hal_deinit = 0x40000280 );\nPROVIDE( wdt_hal_config_stage = 0x40000284 );\nPROVIDE( wdt_hal_write_protect_disable = 0x40000288 );\nPROVIDE( wdt_hal_write_protect_enable = 0x4000028c );\nPROVIDE( wdt_hal_enable = 0x40000290 );\nPROVIDE( wdt_hal_disable = 0x40000294 );\nPROVIDE( wdt_hal_handle_intr = 0x40000298 );\nPROVIDE( wdt_hal_feed = 0x4000029c );\nPROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 );\nPROVIDE( wdt_hal_is_enabled = 0x400002a4 );\nPROVIDE( systimer_hal_get_counter_value = 0x400002ac );\nPROVIDE( systimer_hal_get_alarm_value = 0x400002bc );\nPROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 );\nPROVIDE( systimer_hal_enable_counter = 0x400002cc );\nPROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 );\nPROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 );\nPROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 );\n\n\/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c *\/\n\/* PROVIDE( systimer_hal_init = 0x400002a8 ); *\/\n\/* PROVIDE( systimer_hal_get_time = 0x400002b0 ); *\/\n\/* PROVIDE( systimer_hal_set_alarm_target = 0x400002b4 ); *\/\n\/* PROVIDE( systimer_hal_set_alarm_period = 0x400002b8 ); *\/\n\/* PROVIDE( systimer_hal_counter_value_advance = 0x400002c8 ); *\/\n\n\n\/***************************************\n Group heap\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( tlsf_create = 0x400002dc );\nPROVIDE( tlsf_create_with_pool = 0x400002e0 );\nPROVIDE( tlsf_get_pool = 0x400002e4 );\nPROVIDE( tlsf_add_pool = 0x400002e8 );\nPROVIDE( tlsf_remove_pool = 0x400002ec );\nPROVIDE( tlsf_malloc = 0x400002f0 );\nPROVIDE( tlsf_memalign = 0x400002f4 );\nPROVIDE( tlsf_memalign_offs = 0x400002f8 );\nPROVIDE( tlsf_realloc = 0x400002fc );\nPROVIDE( tlsf_free = 0x40000300 );\nPROVIDE( tlsf_block_size = 0x40000304 );\nPROVIDE( tlsf_size = 0x40000308 );\nPROVIDE( tlsf_align_size = 0x4000030c );\nPROVIDE( tlsf_block_size_min = 0x40000310 );\nPROVIDE( tlsf_block_size_max = 0x40000314 );\nPROVIDE( tlsf_pool_overhead = 0x40000318 );\nPROVIDE( tlsf_alloc_overhead = 0x4000031c );\nPROVIDE( tlsf_walk_pool = 0x40000320 );\nPROVIDE( tlsf_check = 0x40000324 );\nPROVIDE( tlsf_check_pool = 0x40000328 );\nPROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c );\nPROVIDE( multi_heap_get_block_address_impl = 0x40000330 );\nPROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 );\nPROVIDE( multi_heap_register_impl = 0x40000338 );\nPROVIDE( multi_heap_set_lock = 0x4000033c );\nPROVIDE( multi_heap_os_funcs_init = 0x40000340 );\nPROVIDE( multi_heap_internal_lock = 0x40000344 );\nPROVIDE( multi_heap_internal_unlock = 0x40000348 );\nPROVIDE( multi_heap_get_first_block = 0x4000034c );\nPROVIDE( multi_heap_get_next_block = 0x40000350 );\nPROVIDE( multi_heap_is_free = 0x40000354 );\nPROVIDE( multi_heap_malloc_impl = 0x40000358 );\nPROVIDE( multi_heap_free_impl = 0x4000035c );\nPROVIDE( multi_heap_realloc_impl = 0x40000360 );\nPROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 );\nPROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 );\nPROVIDE( multi_heap_check = 0x4000036c );\nPROVIDE( multi_heap_dump = 0x40000370 );\nPROVIDE( multi_heap_free_size_impl = 0x40000374 );\nPROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 );\nPROVIDE( multi_heap_get_info_impl = 0x4000037c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x40000380 );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 );\nPROVIDE( spi_flash_chip_generic_write = 0x40000388 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000398 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 );\nPROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 );\nPROVIDE( spi_flash_chip_generic_yield = 0x400003b8 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 );\nPROVIDE( spi_flash_chip_generic_read = 0x400003c8 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc );\nPROVIDE( spi_flash_common_set_io_mode = 0x400003e0 );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 );\nPROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 );\nPROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec );\nPROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400003f8 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );\nPROVIDE( spi_flash_encryption = 0x3fcdffe4 );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x40000400 );\nPROVIDE( memspi_host_read_status_hs = 0x40000404 );\nPROVIDE( memspi_host_flush_cache = 0x40000408 );\nPROVIDE( memspi_host_erase_chip = 0x4000040c );\nPROVIDE( memspi_host_erase_sector = 0x40000410 );\nPROVIDE( memspi_host_erase_block = 0x40000414 );\nPROVIDE( memspi_host_program_page = 0x40000418 );\nPROVIDE( memspi_host_read = 0x4000041c );\nPROVIDE( memspi_host_set_write_protect = 0x40000420 );\nPROVIDE( memspi_host_set_max_read_len = 0x40000424 );\nPROVIDE( memspi_host_read_data_slicer = 0x40000428 );\nPROVIDE( memspi_host_write_data_slicer = 0x4000042c );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x40000430 );\nPROVIDE( esp_flash_read_id = 0x40000434 );\nPROVIDE( esp_flash_get_size = 0x40000438 );\nPROVIDE( esp_flash_erase_chip = 0x4000043c );\nPROVIDE( esp_flash_erase_region = 0x40000440 );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000444 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000448 );\nPROVIDE( esp_flash_get_protectable_regions = 0x4000044c );\nPROVIDE( esp_flash_get_protected_region = 0x40000450 );\nPROVIDE( esp_flash_set_protected_region = 0x40000454 );\nPROVIDE( esp_flash_read = 0x40000458 );\nPROVIDE( esp_flash_write = 0x4000045c );\nPROVIDE( esp_flash_write_encrypted = 0x40000460 );\nPROVIDE( esp_flash_read_encrypted = 0x40000464 );\nPROVIDE( esp_flash_get_io_mode = 0x40000468 );\nPROVIDE( esp_flash_set_io_mode = 0x4000046c );\nPROVIDE( spi_flash_boot_attach = 0x40000470 );\nPROVIDE( esp_flash_read_chip_id = 0x40000474 );\nPROVIDE( detect_spi_flash_chip = 0x40000478 );\nPROVIDE( esp_rom_spiflash_write_disable = 0x4000047c );\nPROVIDE( esp_flash_suspend_cmd_init = 0x40000480 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe0 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffdc );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 );\nPROVIDE( Cache_Get_Mode = 0x400006e4 );\nPROVIDE( Cache_Address_Through_IBus = 0x400006e8 );\nPROVIDE( Cache_Address_Through_DBus = 0x400006ec );\nPROVIDE( Cache_Set_Default_Mode = 0x400006f0 );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400006f8 );\nPROVIDE( MMU_Set_Page_Mode = 0x400006fc );\nPROVIDE( MMU_Get_Page_Mode = 0x40000700 );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x40000704 );\nPROVIDE( Cache_Op_Addr = 0x40000708 );\nPROVIDE( Cache_Invalidate_Addr = 0x4000070c );\nPROVIDE( Cache_Invalidate_ICache_All = 0x40000710 );\nPROVIDE( Cache_Mask_All = 0x40000714 );\nPROVIDE( Cache_UnMask_Dram0 = 0x40000718 );\nPROVIDE( Cache_Disable_ICache = 0x4000071c );\nPROVIDE( Cache_Enable_ICache = 0x40000720 );\nPROVIDE( Cache_Suspend_ICache = 0x40000724 );\nPROVIDE( Cache_Resume_ICache = 0x40000728 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x4000072c );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x40000730 );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000734 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x40000738 );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x4000073c );\nPROVIDE( Cache_Owner_Init = 0x40000740 );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000744 );\nPROVIDE( Cache_MMU_Init = 0x40000748 );\nPROVIDE( Cache_Ibus_MMU_Set = 0x4000074c );\nPROVIDE( Cache_Dbus_MMU_Set = 0x40000750 );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000754 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x40000758 );\nPROVIDE( Cache_Get_Virtual_Addr = 0x4000075c );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x40000760 );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000764 );\nPROVIDE( Cache_Get_Memory_value = 0x40000768 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd0 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x4000076c;\nets_get_cpu_frequency = 0x40000770;\nets_update_cpu_frequency = 0x40000774;\nets_get_printf_channel = 0x40000778;\nets_get_xtal_div = 0x4000077c;\nets_set_xtal_div = 0x40000780;\nets_get_xtal_freq = 0x40000784;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x40000788;\ngpio_matrix_in = 0x4000078c;\ngpio_matrix_out = 0x40000790;\ngpio_output_disable = 0x40000794;\ngpio_output_enable = 0x40000798;\ngpio_output_set = 0x4000079c;\ngpio_pad_hold = 0x400007a0;\ngpio_pad_input_disable = 0x400007a4;\ngpio_pad_input_enable = 0x400007a8;\ngpio_pad_pulldown = 0x400007ac;\ngpio_pad_pullup = 0x400007b0;\ngpio_pad_select_gpio = 0x400007b4;\ngpio_pad_set_drv = 0x400007b8;\ngpio_pad_unhold = 0x400007bc;\ngpio_pin_wakeup_disable = 0x400007c0;\ngpio_pin_wakeup_enable = 0x400007c4;\ngpio_bypass_matrix_in = 0x400007c8;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400007cc;\nesprv_intc_int_set_threshold = 0x400007d0;\nesprv_intc_int_enable = 0x400007d4;\nesprv_intc_int_disable = 0x400007d8;\nesprv_intc_int_set_type = 0x400007dc;\nPROVIDE( intr_handler_set = 0x400007e0 );\nintr_matrix_set = 0x400007e4;\nets_intr_lock = 0x400007e8;\nets_intr_unlock = 0x400007ec;\nets_isr_attach = 0x400007f0;\nets_isr_mask = 0x400007f4;\nets_isr_unmask = 0x400007f8;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\ncrc32_le = 0x400007fc;\ncrc16_le = 0x40000800;\ncrc8_le = 0x40000804;\ncrc32_be = 0x40000808;\ncrc16_be = 0x4000080c;\ncrc8_be = 0x40000810;\nesp_crc8 = 0x40000814;\nets_sha_enable = 0x40000818;\nets_sha_disable = 0x4000081c;\nets_sha_get_state = 0x40000820;\nets_sha_init = 0x40000824;\nets_sha_process = 0x40000828;\nets_sha_starts = 0x4000082c;\nets_sha_update = 0x40000830;\nets_sha_finish = 0x40000834;\nets_sha_clone = 0x40000838;\n\/* Data (.data, .bss, .rodata) *\/\ncrc32_le_table_ptr = 0x3ff4fff8;\ncrc16_le_table_ptr = 0x3ff4fff4;\ncrc8_le_table_ptr = 0x3ff4fff0;\ncrc32_be_table_ptr = 0x3ff4ffec;\ncrc16_be_table_ptr = 0x3ff4ffe8;\ncrc8_be_table_ptr = 0x3ff4ffe4;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x4000083c;\nets_efuse_program = 0x40000840;\nets_efuse_clear_program_registers = 0x40000844;\nets_efuse_write_key = 0x40000848;\nets_efuse_get_read_register_address = 0x4000084c;\nets_efuse_get_key_purpose = 0x40000850;\nets_efuse_key_block_unused = 0x40000854;\nets_efuse_find_unused_key_block = 0x40000858;\nets_efuse_rs_calculate = 0x4000085c;\nets_efuse_count_unused_key_blocks = 0x40000860;\nets_efuse_secure_boot_enabled = 0x40000864;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000868;\nets_efuse_cache_encryption_enabled = 0x4000086c;\nets_efuse_download_modes_disabled = 0x40000870;\nets_efuse_find_purpose = 0x40000874;\nets_efuse_force_send_resume = 0x40000878;\nets_efuse_get_flash_delay_us = 0x4000087c;\nets_efuse_get_mac = 0x40000880;\nets_efuse_get_uart_print_control = 0x40000884;\nets_efuse_direct_boot_mode_disabled = 0x40000888;\nets_efuse_security_download_modes_enabled = 0x4000088c;\nets_efuse_set_timing = 0x40000890;\nets_efuse_jtag_disabled = 0x40000894;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_ecdsa_verify = 0x40000898;\nets_secure_boot_verify_bootloader_with_keys = 0x4000089c;\nets_secure_boot_verify_signature = 0x400008a0;\nets_secure_boot_read_key_digests = 0x400008a4;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Data (.data, .bss, .rodata) *\/\ng_uart_print = 0x3fcdffc9;\ng_usb_print = 0x3fcdffc8;\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nble_controller_rom_data_init = 0x40000aa8;\nble_osi_coex_funcs_register = 0x40000aac;\nbt_rf_coex_cfg_get_default = 0x40000ab0;\nbt_rf_coex_dft_pti_get_default = 0x40000ab4;\nbt_rf_coex_hooks_p_set = 0x40000ab8;\nr__os_mbuf_copypkthdr = 0x40000abc;\nr__os_msys_find_pool = 0x40000ac0;\nr_ble_controller_get_rom_compile_version = 0x40000ac4;\nr_ble_hci_ram_hs_acl_tx = 0x40000ac8;\nr_ble_hci_ram_hs_cmd_tx = 0x40000acc;\nr_ble_hci_ram_ll_acl_tx = 0x40000ad0;\nr_ble_hci_ram_ll_evt_tx = 0x40000ad4;\nr_ble_hci_ram_reset = 0x40000ad8;\nr_ble_hci_ram_set_acl_free_cb = 0x40000adc;\nr_ble_hci_trans_acl_buf_alloc = 0x40000ae0;\nr_ble_hci_trans_buf_alloc = 0x40000ae4;\nr_ble_hci_trans_buf_free = 0x40000ae8;\nr_ble_hci_trans_cfg_hs = 0x40000aec;\nr_ble_hci_trans_cfg_ll = 0x40000af0;\nr_ble_hci_trans_deinit = 0x40000af4;\nr_ble_hci_trans_env_init = 0x40000af8;\nr_ble_hci_trans_init = 0x40000afc;\nr_ble_hci_uart_acl_tx = 0x40000b00;\nr_ble_hci_uart_cmdevt_tx = 0x40000b04;\nr_ble_hci_uart_config = 0x40000b08;\nr_ble_hci_uart_free_pkt = 0x40000b0c;\nr_ble_hci_uart_hs_acl_tx = 0x40000b10;\nr_ble_hci_uart_hs_cmd_tx = 0x40000b14;\nr_ble_hci_uart_ll_acl_tx = 0x40000b18;\nr_ble_hci_uart_ll_evt_tx = 0x40000b1c;\nr_ble_hci_uart_rx_acl = 0x40000b20;\nr_ble_hci_uart_rx_char = 0x40000b24;\nr_ble_hci_uart_rx_cmd = 0x40000b28;\nr_ble_hci_uart_rx_evt = 0x40000b2c;\nr_ble_hci_uart_rx_evt_cb = 0x40000b30;\nr_ble_hci_uart_rx_le_evt = 0x40000b34;\nr_ble_hci_uart_rx_pkt_type = 0x40000b38;\nr_ble_hci_uart_rx_skip_acl = 0x40000b3c;\nr_ble_hci_uart_rx_skip_cmd = 0x40000b40;\nr_ble_hci_uart_rx_skip_evt = 0x40000b44;\nr_ble_hci_uart_rx_sync_loss = 0x40000b48;\nr_ble_hci_uart_set_acl_free_cb = 0x40000b4c;\nr_ble_hci_uart_sync_lost = 0x40000b50;\nr_ble_hci_uart_trans_reset = 0x40000b54;\nr_ble_hci_uart_tx_char = 0x40000b58;\nr_ble_hci_uart_tx_pkt_type = 0x40000b5c;\nr_ble_hw_driver_deinit = 0x40000b60;\nr_ble_hw_driver_env_init = 0x40000b64;\nr_ble_hw_encrypt_block = 0x40000b68;\nr_ble_hw_get_public_addr = 0x40000b6c;\nr_ble_hw_get_static_addr = 0x40000b70;\nr_ble_hw_periodiclist_add = 0x40000b74;\nr_ble_hw_periodiclist_clear = 0x40000b78;\nr_ble_hw_periodiclist_rmv = 0x40000b7c;\nr_ble_hw_resolv_list_cur_entry = 0x40000b80;\nr_ble_hw_resolv_list_set = 0x40000b88;\nr_ble_hw_rng_init = 0x40000b8c;\nr_ble_hw_rng_start = 0x40000b90;\nr_ble_hw_rng_stop = 0x40000b94;\nr_ble_hw_rx_local_is_resolved = 0x40000b98;\nr_ble_hw_rx_local_is_rpa = 0x40000b9c;\nr_ble_hw_whitelist_add = 0x40000ba0;\nr_ble_hw_whitelist_clear = 0x40000ba4;\nr_ble_hw_whitelist_dev_num = 0x40000ba8;\nr_ble_hw_whitelist_get_base = 0x40000bac;\nr_ble_hw_whitelist_rmv = 0x40000bb0;\nr_ble_hw_whitelist_search = 0x40000bb4;\nr_ble_hw_whitelist_sort = 0x40000bb8;\nr_ble_ll_acl_data_in = 0x40000bbc;\nr_ble_ll_addr_is_id = 0x40000bc0;\nr_ble_ll_addr_subtype = 0x40000bc4;\nr_ble_ll_adv_active_chanset_clear = 0x40000bc8;\nr_ble_ll_adv_active_chanset_is_pri = 0x40000bcc;\nr_ble_ll_adv_active_chanset_is_sec = 0x40000bd0;\nr_ble_ll_adv_active_chanset_set_pri = 0x40000bd4;\nr_ble_ll_adv_active_chanset_set_sec = 0x40000bd8;\nr_ble_ll_adv_aux_calculate = 0x40000bdc;\nr_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000be0;\nr_ble_ll_adv_aux_pdu_make = 0x40000be4;\nr_ble_ll_adv_aux_scannable_pdu_make = 0x40000be8;\nr_ble_ll_adv_aux_txed = 0x40000bec;\nr_ble_ll_adv_can_chg_whitelist = 0x40000bf0;\nr_ble_ll_adv_chk_rpa_timeout = 0x40000bf4;\nr_ble_ll_adv_clear_all = 0x40000bf8;\nr_ble_ll_adv_conn_req_rxd = 0x40000bfc;\nr_ble_ll_adv_deinit = 0x40000c00;\nr_ble_ll_adv_enabled = 0x40000c04;\nr_ble_ll_adv_ext_set_adv_data = 0x40000c0c;\nr_ble_ll_adv_ext_set_scan_rsp = 0x40000c18;\nr_ble_ll_adv_final_chan = 0x40000c1c;\nr_ble_ll_adv_first_chan = 0x40000c20;\nr_ble_ll_adv_flags_clear = 0x40000c24;\nr_ble_ll_adv_flags_set = 0x40000c28;\nr_ble_ll_adv_get_chan_num = 0x40000c2c;\nr_ble_ll_adv_get_local_rpa = 0x40000c30;\nr_ble_ll_adv_get_peer_rpa = 0x40000c34;\nr_ble_ll_adv_hci_set_random_addr = 0x40000c38;\nr_ble_ll_adv_init = 0x40000c3c;\nr_ble_ll_adv_legacy_pdu_make = 0x40000c40;\nr_ble_ll_adv_next_chan = 0x40000c44;\nr_ble_ll_adv_pdu_make = 0x40000c48;\nr_ble_ll_adv_periodic_check_data_itvl = 0x40000c4c;\nr_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c54;\nr_ble_ll_adv_periodic_send_sync_ind = 0x40000c58;\nr_ble_ll_adv_periodic_set_info_transfer = 0x40000c60;\nr_ble_ll_adv_periodic_set_param = 0x40000c64;\nr_ble_ll_adv_pre_process = 0x40000c68;\nr_ble_ll_adv_put_acad_chM_update_ind = 0x40000c6c;\nr_ble_ll_adv_put_aux_ptr = 0x40000c70;\nr_ble_ll_adv_put_syncinfo = 0x40000c74;\nr_ble_ll_adv_rd_max_adv_data_len = 0x40000c78;\nr_ble_ll_adv_rd_sup_adv_sets = 0x40000c7c;\nr_ble_ll_adv_read_txpwr = 0x40000c80;\nr_ble_ll_adv_rpa_timeout = 0x40000c8c;\nr_ble_ll_adv_rpa_update = 0x40000c90;\nr_ble_ll_adv_scan_req_rxd = 0x40000c98;\nr_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c;\nr_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0;\nr_ble_ll_adv_scheduled = 0x40000ca4;\nr_ble_ll_adv_send_conn_comp_ev = 0x40000ca8;\nr_ble_ll_adv_set_adv_params = 0x40000cb0;\nr_ble_ll_adv_set_enable = 0x40000cb4;\nr_ble_ll_adv_set_random_addr = 0x40000cb8;\nr_ble_ll_adv_sm_deinit = 0x40000cc4;\nr_ble_ll_adv_sm_event_init = 0x40000cc8;\nr_ble_ll_adv_sm_find_configured = 0x40000ccc;\nr_ble_ll_adv_sm_get = 0x40000cd0;\nr_ble_ll_adv_sm_reset = 0x40000cd8;\nr_ble_ll_adv_sm_start = 0x40000cdc;\nr_ble_ll_adv_sm_start_periodic = 0x40000ce0;\nr_ble_ll_adv_sm_stop = 0x40000ce4;\nr_ble_ll_adv_sm_stop_limit_reached = 0x40000ce8;\nr_ble_ll_adv_sm_stop_periodic = 0x40000cec;\nr_ble_ll_adv_sm_stop_timeout = 0x40000cf0;\nr_ble_ll_adv_sync_get_pdu_len = 0x40000cf8;\nr_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d00;\nr_ble_ll_adv_update_data_mbuf = 0x40000d04;\nr_ble_ll_adv_update_did = 0x40000d08;\nr_ble_ll_adv_update_periodic_data = 0x40000d0c;\nr_ble_ll_arr_pool_init = 0x40000d10;\nr_ble_ll_auth_pyld_tmo_event_send = 0x40000d14;\nr_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d18;\nr_ble_ll_calc_session_key = 0x40000d1c;\nr_ble_ll_calc_ticks_per_slot = 0x40000d20;\nr_ble_ll_check_scan_params = 0x40000d24;\nr_ble_ll_chk_txrx_octets = 0x40000d28;\nr_ble_ll_chk_txrx_time = 0x40000d2c;\nr_ble_ll_conn_adjust_pyld_len = 0x40000d30;\nr_ble_ll_conn_auth_pyld_timer_cb = 0x40000d34;\nr_ble_ll_conn_auth_pyld_timer_start = 0x40000d38;\nr_ble_ll_conn_calc_dci = 0x40000d3c;\nr_ble_ll_conn_calc_dci_csa1 = 0x40000d40;\nr_ble_ll_conn_calc_itvl_ticks = 0x40000d44;\nr_ble_ll_conn_chk_csm_flags = 0x40000d48;\nr_ble_ll_conn_chk_phy_upd_start = 0x40000d4c;\nr_ble_ll_conn_comp_event_send = 0x40000d50;\nr_ble_ll_conn_connect_ind_pdu_make = 0x40000d54;\nr_ble_ll_conn_create_cancel = 0x40000d5c;\nr_ble_ll_conn_cth_flow_enable = 0x40000d64;\nr_ble_ll_conn_cth_flow_error_fn = 0x40000d68;\nr_ble_ll_conn_cth_flow_have_credit = 0x40000d6c;\nr_ble_ll_conn_cth_flow_is_enabled = 0x40000d70;\nr_ble_ll_conn_cth_flow_process_cmd = 0x40000d74;\nr_ble_ll_conn_cth_flow_set_buffers = 0x40000d78;\nr_ble_ll_conn_ext_master_init = 0x40000d84;\nr_ble_ll_conn_find_active_conn = 0x40000d88;\nr_ble_ll_conn_get_active_conn = 0x40000d8c;\nr_ble_ll_conn_get_anchor = 0x40000d90;\nr_ble_ll_conn_hcc_params_set_fallback = 0x40000d94;\nr_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000d98;\nr_ble_ll_conn_hci_chk_conn_params = 0x40000d9c;\nr_ble_ll_conn_hci_chk_scan_params = 0x40000da0;\nr_ble_ll_conn_hci_disconnect_cmd = 0x40000da4;\nr_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000da8;\nr_ble_ll_conn_hci_le_ltk_reply = 0x40000dac;\nr_ble_ll_conn_hci_le_rd_phy = 0x40000db0;\nr_ble_ll_conn_hci_le_set_phy = 0x40000db4;\nr_ble_ll_conn_hci_le_start_encrypt = 0x40000db8;\nr_ble_ll_conn_hci_param_nrr = 0x40000dbc;\nr_ble_ll_conn_hci_param_rr = 0x40000dc0;\nr_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000dc4;\nr_ble_ll_conn_hci_rd_chan_map = 0x40000dc8;\nr_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000dcc;\nr_ble_ll_conn_hci_rd_rssi = 0x40000dd0;\nr_ble_ll_conn_hci_read_rem_features = 0x40000dd4;\nr_ble_ll_conn_hci_set_data_len = 0x40000ddc;\nr_ble_ll_conn_hci_update = 0x40000de0;\nr_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000de4;\nr_ble_ll_conn_init_phy = 0x40000de8;\nr_ble_ll_conn_is_empty_pdu = 0x40000df0;\nr_ble_ll_conn_is_lru = 0x40000df4;\nr_ble_ll_conn_master_init = 0x40000df8;\nr_ble_ll_conn_module_reset = 0x40000e04;\nr_ble_ll_conn_next_event = 0x40000e08;\nr_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c;\nr_ble_ll_conn_process_conn_params = 0x40000e14;\nr_ble_ll_conn_req_peer_sca = 0x40000e18;\nr_ble_ll_conn_rx_data_pdu = 0x40000e1c;\nr_ble_ll_conn_set_csa = 0x40000e20;\nr_ble_ll_conn_set_ext_con_params = 0x40000e24;\nr_ble_ll_conn_set_global_chanmap = 0x40000e28;\nr_ble_ll_conn_set_phy = 0x40000e2c;\nr_ble_ll_conn_set_txpwr_by_handle = 0x40000e30;\nr_ble_ll_conn_set_unknown_rx_octets = 0x40000e34;\nr_ble_ll_conn_sm_get = 0x40000e3c;\nr_ble_ll_conn_tx_pkt_in = 0x40000e4c;\nr_ble_ll_conn_update_eff_data_len = 0x40000e50;\nr_ble_ll_ctrl_chanmap_req_make = 0x40000e54;\nr_ble_ll_ctrl_conn_param_pdu_make = 0x40000e5c;\nr_ble_ll_ctrl_conn_param_pdu_proc = 0x40000e60;\nr_ble_ll_ctrl_conn_param_reply = 0x40000e64;\nr_ble_ll_ctrl_datalen_upd_make = 0x40000e6c;\nr_ble_ll_ctrl_enc_allowed_pdu = 0x40000e70;\nr_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000e74;\nr_ble_ll_ctrl_enc_req_make = 0x40000e7c;\nr_ble_ll_ctrl_find_new_phy = 0x40000e80;\nr_ble_ll_ctrl_initiate_dle = 0x40000e84;\nr_ble_ll_ctrl_len_proc = 0x40000e88;\nr_ble_ll_ctrl_min_used_chan_rsp = 0x40000e8c;\nr_ble_ll_ctrl_phy_from_phy_mask = 0x40000e90;\nr_ble_ll_ctrl_phy_req_rsp_make = 0x40000e94;\nr_ble_ll_ctrl_phy_tx_transition_get = 0x40000e98;\nr_ble_ll_ctrl_phy_update_cancel = 0x40000e9c;\nr_ble_ll_ctrl_phy_update_ind_make = 0x40000ea0;\nr_ble_ll_ctrl_phy_update_proc_complete = 0x40000ea4;\nr_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000eac;\nr_ble_ll_ctrl_proc_stop = 0x40000eb4;\nr_ble_ll_ctrl_proc_with_instant_initiated = 0x40000ebc;\nr_ble_ll_ctrl_rej_ext_ind_make = 0x40000ec0;\nr_ble_ll_ctrl_reject_ind_send = 0x40000ec4;\nr_ble_ll_ctrl_rx_chanmap_req = 0x40000ec8;\nr_ble_ll_ctrl_rx_conn_param_req = 0x40000ecc;\nr_ble_ll_ctrl_rx_conn_param_rsp = 0x40000ed0;\nr_ble_ll_ctrl_rx_conn_update = 0x40000ed4;\nr_ble_ll_ctrl_rx_enc_req = 0x40000ed8;\nr_ble_ll_ctrl_rx_enc_rsp = 0x40000edc;\nr_ble_ll_ctrl_rx_feature_req = 0x40000ee0;\nr_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8;\nr_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec;\nr_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4;\nr_ble_ll_ctrl_rx_phy_req = 0x40000ef8;\nr_ble_ll_ctrl_rx_phy_rsp = 0x40000efc;\nr_ble_ll_ctrl_rx_phy_update_ind = 0x40000f00;\nr_ble_ll_ctrl_rx_ping_rsp = 0x40000f04;\nr_ble_ll_ctrl_rx_reject_ind = 0x40000f08;\nr_ble_ll_ctrl_rx_sca_req = 0x40000f0c;\nr_ble_ll_ctrl_rx_sca_rsp = 0x40000f10;\nr_ble_ll_ctrl_rx_start_enc_req = 0x40000f14;\nr_ble_ll_ctrl_rx_start_enc_rsp = 0x40000f18;\nr_ble_ll_ctrl_rx_version_ind = 0x40000f1c;\nr_ble_ll_ctrl_sca_req_rsp_make = 0x40000f20;\nr_ble_ll_ctrl_start_enc_send = 0x40000f24;\nr_ble_ll_ctrl_start_rsp_timer = 0x40000f28;\nr_ble_ll_ctrl_terminate_start = 0x40000f2c;\nr_ble_ll_ctrl_update_features = 0x40000f34;\nr_ble_ll_ctrl_version_ind_make = 0x40000f38;\nr_ble_ll_data_buffer_overflow = 0x40000f3c;\nr_ble_ll_deinit = 0x40000f40;\nr_ble_ll_disconn_comp_event_send = 0x40000f44;\nr_ble_ll_event_comp_pkts = 0x40000f4c;\nr_ble_ll_event_dbuf_overflow = 0x40000f50;\nr_ble_ll_event_send = 0x40000f54;\nr_ble_ll_event_tx_pkt = 0x40000f58;\nr_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40000f5c;\nr_ble_ll_ext_conn_create = 0x40000f60;\nr_ble_ll_ext_scan_parse_adv_info = 0x40000f64;\nr_ble_ll_ext_scan_parse_aux_ptr = 0x40000f68;\nr_ble_ll_flush_pkt_queue = 0x40000f6c;\nr_ble_ll_generate_dh_key_v1 = 0x40000f70;\nr_ble_ll_generate_dh_key_v2 = 0x40000f74;\nr_ble_ll_generic_data_init = 0x40000f78;\nr_ble_ll_get_addr_type = 0x40000f7c;\nr_ble_ll_get_chan_to_scan = 0x40000f80;\nr_ble_ll_get_our_devaddr = 0x40000f84;\nr_ble_ll_get_tx_pwr_compensation = 0x40000f88;\nr_ble_ll_hci_acl_rx = 0x40000f8c;\nr_ble_ll_hci_adv_mode_ext = 0x40000f90;\nr_ble_ll_hci_adv_set_enable = 0x40000f94;\nr_ble_ll_hci_cb_host_buf_size = 0x40000f98;\nr_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x40000f9c;\nr_ble_ll_hci_cb_set_event_mask = 0x40000fa0;\nr_ble_ll_hci_cb_set_event_mask2 = 0x40000fa4;\nr_ble_ll_hci_chk_phy_masks = 0x40000fa8;\nr_ble_ll_hci_cmd_proc = 0x40000fac;\nr_ble_ll_hci_cmd_rx = 0x40000fb0;\nr_ble_ll_hci_ctlr_bb_cmd_proc = 0x40000fb4;\nr_ble_ll_hci_deinit = 0x40000fb8;\nr_ble_ll_hci_disconnect = 0x40000fbc;\nr_ble_ll_hci_env_init = 0x40000fc0;\nr_ble_ll_hci_ev_conn_update = 0x40000fc4;\nr_ble_ll_hci_ev_databuf_overflow = 0x40000fc8;\nr_ble_ll_hci_ev_datalen_chg = 0x40000fcc;\nr_ble_ll_hci_ev_encrypt_chg = 0x40000fd0;\nr_ble_ll_hci_ev_hw_err = 0x40000fd4;\nr_ble_ll_hci_ev_le_csa = 0x40000fd8;\nr_ble_ll_hci_ev_ltk_req = 0x40000fdc;\nr_ble_ll_hci_ev_phy_update = 0x40000fe0;\nr_ble_ll_hci_ev_rd_rem_used_feat = 0x40000fe4;\nr_ble_ll_hci_ev_rd_rem_ver = 0x40000fe8;\nr_ble_ll_hci_ev_rem_conn_parm_req = 0x40000fec;\nr_ble_ll_hci_ev_sca_update = 0x40000ff0;\nr_ble_ll_hci_ev_send_adv_set_terminated = 0x40000ff4;\nr_ble_ll_hci_ev_send_scan_req_recv = 0x40000ff8;\nr_ble_ll_hci_ev_send_scan_timeout = 0x40000ffc;\nr_ble_ll_hci_ev_send_vendor_err = 0x40001000;\nr_ble_ll_hci_event_send = 0x40001004;\nr_ble_ll_hci_ext_scan_set_enable = 0x40001008;\nr_ble_ll_hci_get_num_cmd_pkts = 0x4000100c;\nr_ble_ll_hci_info_params_cmd_proc = 0x40001010;\nr_ble_ll_hci_init = 0x40001014;\nr_ble_ll_hci_init_support_cmd_base_on_lmp_ver = 0x40001018;\nr_ble_ll_hci_is_event_enabled = 0x4000101c;\nr_ble_ll_hci_is_le_event_enabled = 0x40001020;\nr_ble_ll_hci_le_cmd_send_cmd_status = 0x40001028;\nr_ble_ll_hci_le_encrypt = 0x4000102c;\nr_ble_ll_hci_le_rand = 0x40001030;\nr_ble_ll_hci_le_rd_max_data_len = 0x40001034;\nr_ble_ll_hci_le_rd_sugg_data_len = 0x40001038;\nr_ble_ll_hci_le_read_bufsize = 0x4000103c;\nr_ble_ll_hci_le_read_supp_states = 0x40001044;\nr_ble_ll_hci_le_set_def_phy = 0x40001048;\nr_ble_ll_hci_le_wr_sugg_data_len = 0x4000104c;\nr_ble_ll_hci_link_ctrl_cmd_proc = 0x40001050;\nr_ble_ll_hci_npl_init = 0x40001054;\nr_ble_ll_hci_post_gen_dhkey_cmp_evt = 0x40001058;\nr_ble_ll_hci_post_rd_p256_pubkey_cmp_evt = 0x4000105c;\nr_ble_ll_hci_rd_bd_addr = 0x40001060;\nr_ble_ll_hci_rd_local_supp_cmd = 0x40001064;\nr_ble_ll_hci_rd_local_supp_feat = 0x40001068;\nr_ble_ll_hci_rd_local_version = 0x4000106c;\nr_ble_ll_hci_scan_set_enable = 0x40001070;\nr_ble_ll_hci_send_adv_report = 0x40001074;\nr_ble_ll_hci_send_dir_adv_report = 0x40001078;\nr_ble_ll_hci_send_ext_adv_report = 0x4000107c;\nr_ble_ll_hci_send_legacy_ext_adv_report = 0x40001080;\nr_ble_ll_hci_send_noop = 0x40001084;\nr_ble_ll_hci_set_adv_data = 0x40001088;\nr_ble_ll_hci_set_le_event_mask = 0x4000108c;\nr_ble_ll_hci_set_scan_rsp_data = 0x40001090;\nr_ble_ll_hci_status_params_cmd_proc = 0x40001094;\nr_ble_ll_hci_vs_cmd_proc = 0x40001098;\nr_ble_ll_hci_vs_rd_static_addr = 0x4000109c;\nr_ble_ll_hw_err_timer_cb = 0x400010a0;\nr_ble_ll_hw_error = 0x400010a4;\nr_ble_ll_init_alloc_conn_comp_ev = 0x400010ac;\nr_ble_ll_init_get_conn_comp_ev = 0x400010b0;\nr_ble_ll_is_addr_empty = 0x400010b8;\nr_ble_ll_is_controller_busy = 0x400010bc;\nr_ble_ll_is_on_resolv_list = 0x400010c0;\nr_ble_ll_is_our_devaddr = 0x400010c4;\nr_ble_ll_is_rpa = 0x400010c8;\nr_ble_ll_is_valid_adv_mode = 0x400010cc;\nr_ble_ll_is_valid_own_addr_type = 0x400010d0;\nr_ble_ll_is_valid_public_addr = 0x400010d4;\nr_ble_ll_is_valid_random_addr = 0x400010d8;\nr_ble_ll_misc_options_set = 0x400010e0;\nr_ble_ll_modify_sca = 0x400010e4;\nr_ble_ll_modify_sca_action = 0x400010e8;\nr_ble_ll_pdu_max_tx_octets_get = 0x400010ec;\nr_ble_ll_pdu_tx_time_get = 0x400010f0;\nr_ble_ll_phy_to_phy_mode = 0x400010f4;\nr_ble_ll_qa_enable = 0x400010f8;\nr_ble_ll_rand = 0x400010fc;\nr_ble_ll_rand_data_get = 0x40001100;\nr_ble_ll_rand_deinit = 0x40001104;\nr_ble_ll_rand_env_init = 0x40001108;\nr_ble_ll_rand_init = 0x4000110c;\nr_ble_ll_rand_prand_get = 0x40001110;\nr_ble_ll_rand_sample = 0x40001114;\nr_ble_ll_rand_start = 0x40001118;\nr_ble_ll_read_local_p256_pub_key = 0x4000111c;\nr_ble_ll_read_rf_path_compensation = 0x40001120;\nr_ble_ll_read_supp_features = 0x40001124;\nr_ble_ll_read_supp_states = 0x40001128;\nr_ble_ll_reset = 0x40001130;\nr_ble_ll_resolv_clear_all_pl_bit = 0x40001134;\nr_ble_ll_resolv_clear_all_wl_bit = 0x40001138;\nr_ble_ll_resolv_deinit = 0x4000113c;\nr_ble_ll_resolv_enable_cmd = 0x40001140;\nr_ble_ll_resolv_enabled = 0x40001144;\nr_ble_ll_resolv_env_init = 0x40001148;\nr_ble_ll_resolv_gen_rpa = 0x40001150;\nr_ble_ll_resolv_get_addr_pointer = 0x40001154;\nr_ble_ll_resolv_get_index = 0x40001158;\nr_ble_ll_resolv_get_irk_pointer = 0x4000115c;\nr_ble_ll_resolv_get_list = 0x40001160;\nr_ble_ll_resolv_get_priv_addr = 0x40001164;\nr_ble_ll_resolv_get_rpa_tmo = 0x40001168;\nr_ble_ll_resolv_init = 0x4000116c;\nr_ble_ll_resolv_irk_nonzero = 0x40001170;\nr_ble_ll_resolv_list_add = 0x40001174;\nr_ble_ll_resolv_list_chg_allowed = 0x40001178;\nr_ble_ll_resolv_list_clr = 0x4000117c;\nr_ble_ll_resolv_list_find = 0x40001180;\nr_ble_ll_resolv_list_read_size = 0x40001184;\nr_ble_ll_resolv_list_reset = 0x40001188;\nr_ble_ll_resolv_list_rmv = 0x4000118c;\nr_ble_ll_resolv_local_addr_rd = 0x40001190;\nr_ble_ll_resolv_peer_addr_rd = 0x40001194;\nr_ble_ll_resolv_peer_rpa_any = 0x40001198;\nr_ble_ll_resolv_reset = 0x4000119c;\nr_ble_ll_resolv_rpa = 0x400011a0;\nr_ble_ll_resolv_rpa_timer_cb = 0x400011a4;\nr_ble_ll_resolv_set_local_rpa = 0x400011a8;\nr_ble_ll_resolv_set_peer_rpa = 0x400011ac;\nr_ble_ll_resolv_set_rpa_tmo = 0x400011b0;\nr_ble_ll_resolve_set_priv_mode = 0x400011b4;\nr_ble_ll_rxpdu_alloc = 0x400011b8;\nr_ble_ll_scan_add_scan_rsp_adv = 0x400011bc;\nr_ble_ll_scan_adv_decode_addr = 0x400011c0;\nr_ble_ll_scan_aux_data_ref = 0x400011c4;\nr_ble_ll_scan_aux_data_unref = 0x400011c8;\nr_ble_ll_scan_can_chg_whitelist = 0x400011cc;\nr_ble_ll_scan_check_periodic_sync = 0x400011d0;\nr_ble_ll_scan_classify_filter_aux_init = 0x400011d4;\nr_ble_ll_scan_classify_filter_init = 0x400011d8;\nr_ble_ll_scan_common_init = 0x400011dc;\nr_ble_ll_scan_continue_en = 0x400011e0;\nr_ble_ll_scan_dup_check_ext = 0x400011e8;\nr_ble_ll_scan_dup_check_legacy = 0x400011ec;\nr_ble_ll_scan_dup_move_to_head = 0x400011f0;\nr_ble_ll_scan_dup_new = 0x400011f4;\nr_ble_ll_scan_dup_update_ext = 0x400011f8;\nr_ble_ll_scan_dup_update_legacy = 0x400011fc;\nr_ble_ll_scan_enabled = 0x40001200;\nr_ble_ll_scan_end_adv_evt = 0x40001204;\nr_ble_ll_scan_ext_initiator_start = 0x4000120c;\nr_ble_ll_scan_get_addr_data_from_legacy = 0x40001210;\nr_ble_ll_scan_get_addr_from_ext_adv = 0x40001214;\nr_ble_ll_scan_get_cur_sm = 0x40001218;\nr_ble_ll_scan_get_ext_adv_report = 0x4000121c;\nr_ble_ll_scan_get_local_rpa = 0x40001220;\nr_ble_ll_scan_get_next_adv_prim_chan = 0x40001224;\nr_ble_ll_scan_get_peer_rpa = 0x40001228;\nr_ble_ll_scan_have_rxd_scan_rsp = 0x4000122c;\nr_ble_ll_scan_init = 0x40001230;\nr_ble_ll_scan_initiator_start = 0x40001234;\nr_ble_ll_scan_is_inside_window = 0x40001238;\nr_ble_ll_scan_move_window_to = 0x4000123c;\nr_ble_ll_scan_npl_reset = 0x40001240;\nr_ble_ll_scan_parse_auxptr = 0x40001244;\nr_ble_ll_scan_parse_ext_hdr = 0x40001248;\nr_ble_ll_scan_record_new_adv = 0x40001250;\nr_ble_ll_scan_refresh_nrpa = 0x40001254;\nr_ble_ll_scan_reset = 0x40001258;\nr_ble_ll_scan_rx_pkt_in = 0x4000125c;\nr_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268;\nr_ble_ll_scan_rxed = 0x4000126c;\nr_ble_ll_scan_send_adv_report = 0x40001270;\nr_ble_ll_scan_send_truncated = 0x40001274;\nr_ble_ll_scan_set_peer_rpa = 0x4000127c;\nr_ble_ll_scan_set_perfer_addr = 0x40001280;\nr_ble_ll_scan_sm_start = 0x40001288;\nr_ble_ll_scan_sm_stop = 0x4000128c;\nr_ble_ll_scan_time_hci_to_ticks = 0x40001290;\nr_ble_ll_scan_update_aux_data = 0x40001294;\nr_ble_ll_scan_whitelist_enabled = 0x40001298;\nr_ble_ll_set_default_privacy_mode = 0x4000129c;\nr_ble_ll_set_default_sync_transfer_params = 0x400012a0;\nr_ble_ll_set_public_addr = 0x400012ac;\nr_ble_ll_set_random_addr = 0x400012b0;\nr_ble_ll_set_sync_transfer_params = 0x400012b4;\nr_ble_ll_state_get = 0x400012b8;\nr_ble_ll_state_set = 0x400012bc;\nr_ble_ll_sync_adjust_ext_hdr = 0x400012c0;\nr_ble_ll_sync_cancel = 0x400012c4;\nr_ble_ll_sync_cancel_complete_event = 0x400012c8;\nr_ble_ll_sync_check_acad = 0x400012cc;\nr_ble_ll_sync_check_failed = 0x400012d0;\nr_ble_ll_sync_deinit = 0x400012d8;\nr_ble_ll_sync_enabled = 0x400012dc;\nr_ble_ll_sync_env_init = 0x400012e0;\nr_ble_ll_sync_established = 0x400012ec;\nr_ble_ll_sync_filter_enabled = 0x400012f0;\nr_ble_ll_sync_find = 0x400012f4;\nr_ble_ll_sync_get_cur_sm = 0x400012f8;\nr_ble_ll_sync_get_handle = 0x400012fc;\nr_ble_ll_sync_get_sm = 0x40001300;\nr_ble_ll_sync_info_event = 0x40001304;\nr_ble_ll_sync_init = 0x40001308;\nr_ble_ll_sync_list_add = 0x4000130c;\nr_ble_ll_sync_list_clear = 0x40001310;\nr_ble_ll_sync_list_empty = 0x40001314;\nr_ble_ll_sync_list_get_free = 0x40001318;\nr_ble_ll_sync_list_remove = 0x4000131c;\nr_ble_ll_sync_list_search = 0x40001320;\nr_ble_ll_sync_list_size = 0x40001324;\nr_ble_ll_sync_lost_event = 0x40001328;\nr_ble_ll_sync_next_event = 0x4000132c;\nr_ble_ll_sync_on_list = 0x40001330;\nr_ble_ll_sync_periodic_ind = 0x40001338;\nr_ble_ll_sync_phy_mode_to_aux_phy = 0x4000133c;\nr_ble_ll_sync_phy_mode_to_hci = 0x40001340;\nr_ble_ll_sync_reserve = 0x4000134c;\nr_ble_ll_sync_reset = 0x40001350;\nr_ble_ll_sync_reset_sm = 0x40001354;\nr_ble_ll_sync_send_per_adv_rpt = 0x4000135c;\nr_ble_ll_sync_send_sync_ind = 0x40001360;\nr_ble_ll_sync_send_truncated_per_adv_rpt = 0x40001364;\nr_ble_ll_sync_sm_clear = 0x40001368;\nr_ble_ll_sync_terminate = 0x4000136c;\nr_ble_ll_sync_transfer = 0x40001370;\nr_ble_ll_sync_transfer_get = 0x40001374;\nr_ble_ll_sync_transfer_received = 0x40001378;\nr_ble_ll_task = 0x4000137c;\nr_ble_ll_trace_set_func = 0x40001380;\nr_ble_ll_trace_u32 = 0x40001384;\nr_ble_ll_trace_u32x2 = 0x40001388;\nr_ble_ll_trace_u32x3 = 0x4000138c;\nr_ble_ll_tx_flat_mbuf_pducb = 0x40001390;\nr_ble_ll_tx_pkt_in = 0x40001398;\nr_ble_ll_update_max_tx_octets_phy_mode = 0x4000139c;\nr_ble_ll_usecs_to_ticks_round_up = 0x400013a0;\nr_ble_ll_utils_calc_access_addr = 0x400013a4;\nr_ble_ll_utils_calc_dci_csa2 = 0x400013a8;\nr_ble_ll_utils_calc_num_used_chans = 0x400013ac;\nr_ble_ll_utils_calc_window_widening = 0x400013b0;\nr_ble_ll_utils_csa2_perm = 0x400013b4;\nr_ble_ll_utils_csa2_prng = 0x400013b8;\nr_ble_ll_utils_remapped_channel = 0x400013bc;\nr_ble_ll_whitelist_add = 0x400013c0;\nr_ble_ll_whitelist_chg_allowed = 0x400013c4;\nr_ble_ll_whitelist_clear = 0x400013c8;\nr_ble_ll_whitelist_read_size = 0x400013cc;\nr_ble_ll_whitelist_rmv = 0x400013d0;\nr_ble_ll_write_rf_path_compensation = 0x400013d8;\nr_ble_lll_adv_aux_schedule = 0x400013e0;\nr_ble_lll_adv_aux_schedule_first = 0x400013e4;\nr_ble_lll_adv_aux_schedule_next = 0x400013e8;\nr_ble_lll_adv_aux_scheduled = 0x400013ec;\nr_ble_lll_adv_aux_set_start_time = 0x400013f0;\nr_ble_lll_adv_coex_dpc_calc_pti_update_itvl = 0x400013f4;\nr_ble_lll_adv_coex_dpc_process_pri = 0x400013f8;\nr_ble_lll_adv_coex_dpc_process_sec = 0x400013fc;\nr_ble_lll_adv_coex_dpc_pti_get = 0x40001400;\nr_ble_lll_adv_coex_dpc_update = 0x40001404;\nr_ble_lll_adv_coex_dpc_update_on_adv_start = 0x40001408;\nr_ble_lll_adv_coex_dpc_update_on_aux_scheduled = 0x4000140c;\nr_ble_lll_adv_coex_dpc_update_on_data_updated = 0x40001410;\nr_ble_lll_adv_coex_dpc_update_on_event_end = 0x40001414;\nr_ble_lll_adv_coex_dpc_update_on_event_scheduled = 0x40001418;\nr_ble_lll_adv_done = 0x4000141c;\nr_ble_lll_adv_drop_event = 0x40001420;\nr_ble_lll_adv_event_done = 0x40001424;\nr_ble_lll_adv_event_rmvd_from_sched = 0x40001428;\nr_ble_lll_adv_ext_estimate_data_itvl = 0x4000142c;\nr_ble_lll_adv_get_sec_pdu_len = 0x40001430;\nr_ble_lll_adv_make_done = 0x40001438;\nr_ble_lll_adv_periodic_done = 0x4000143c;\nr_ble_lll_adv_periodic_event_done = 0x40001440;\nr_ble_lll_adv_periodic_rmvd_from_sched = 0x40001444;\nr_ble_lll_adv_periodic_schedule_first = 0x40001448;\nr_ble_lll_adv_periodic_start = 0x40001450;\nr_ble_lll_adv_periodic_stop = 0x40001454;\nr_ble_lll_adv_pri_schedule_tx_pdu = 0x40001458;\nr_ble_lll_adv_reschedule_event = 0x4000145c;\nr_ble_lll_adv_reschedule_periodic_event = 0x40001460;\nr_ble_lll_adv_sec_done = 0x40001468;\nr_ble_lll_adv_sec_event_done = 0x4000146c;\nr_ble_lll_adv_sec_schedule_next_aux = 0x40001470;\nr_ble_lll_adv_secondary_tx_start_cb = 0x40001474;\nr_ble_lll_adv_sm_deinit = 0x40001478;\nr_ble_lll_adv_sm_event_init = 0x4000147c;\nr_ble_lll_adv_sm_event_restore = 0x40001480;\nr_ble_lll_adv_sm_event_store = 0x40001484;\nr_ble_lll_adv_sm_init = 0x40001488;\nr_ble_lll_adv_sm_reset = 0x4000148c;\nr_ble_lll_adv_start = 0x40001490;\nr_ble_lll_adv_stop = 0x40001494;\nr_ble_lll_adv_sync_next_scheduled = 0x40001498;\nr_ble_lll_adv_sync_schedule = 0x4000149c;\nr_ble_lll_adv_sync_tx_done = 0x400014a0;\nr_ble_lll_adv_sync_tx_end = 0x400014a4;\nr_ble_lll_adv_sync_tx_start_cb = 0x400014a8;\nr_ble_lll_adv_tx_done = 0x400014ac;\nr_ble_lll_adv_tx_start_cb = 0x400014b0;\nr_ble_lll_adv_update_rsp_offset = 0x400014b4;\nr_ble_lll_aux_scan_cb = 0x400014b8;\nr_ble_lll_aux_scan_drop = 0x400014bc;\nr_ble_lll_aux_scan_drop_event_cb = 0x400014c0;\nr_ble_lll_calc_us_convert_tick_unit = 0x400014c4;\nr_ble_lll_conn_append_tx_buffer = 0x400014c8;\nr_ble_lll_conn_can_send_next_pdu = 0x400014cc;\nr_ble_lll_conn_check_opcode_matched = 0x400014d0;\nr_ble_lll_conn_coex_dpc_process = 0x400014d4;\nr_ble_lll_conn_coex_dpc_pti_get = 0x400014d8;\nr_ble_lll_conn_coex_dpc_update = 0x400014dc;\nr_ble_lll_conn_coex_dpc_update_on_event_end = 0x400014e0;\nr_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4;\nr_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8;\nr_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec;\nr_ble_lll_conn_current_sm_over = 0x400014f4;\nr_ble_lll_conn_env_deinit = 0x400014fc;\nr_ble_lll_conn_env_init = 0x40001500;\nr_ble_lll_conn_event_end = 0x40001504;\nr_ble_lll_conn_event_end_timer_cb = 0x40001508;\nr_ble_lll_conn_event_halt = 0x4000150c;\nr_ble_lll_conn_event_is_over = 0x40001510;\nr_ble_lll_conn_event_start_cb = 0x40001514;\nr_ble_lll_conn_free_rx_mbuf = 0x40001518;\nr_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c;\nr_ble_lll_conn_get_ce_end_time = 0x40001520;\nr_ble_lll_conn_get_next_sched_time = 0x40001524;\nr_ble_lll_conn_halt = 0x4000152c;\nr_ble_lll_conn_master_common_init = 0x40001530;\nr_ble_lll_conn_master_new = 0x40001534;\nr_ble_lll_conn_module_deinit = 0x40001538;\nr_ble_lll_conn_module_reset = 0x40001540;\nr_ble_lll_conn_pre_process = 0x40001548;\nr_ble_lll_conn_process_acked_pdu = 0x4000154c;\nr_ble_lll_conn_recv_ack = 0x40001554;\nr_ble_lll_conn_recv_valid_packet = 0x40001558;\nr_ble_lll_conn_reset_pending_sched = 0x4000155c;\nr_ble_lll_conn_rx_pkt_isr = 0x40001560;\nr_ble_lll_conn_sched_next_anchor = 0x40001564;\nr_ble_lll_conn_sched_next_event = 0x40001568;\nr_ble_lll_conn_set_slave_flow_control = 0x4000156c;\nr_ble_lll_conn_sm_new = 0x40001574;\nr_ble_lll_conn_sm_npl_deinit = 0x40001578;\nr_ble_lll_conn_sm_npl_init = 0x4000157c;\nr_ble_lll_conn_superversion_timer_cb = 0x40001580;\nr_ble_lll_conn_timeout = 0x40001584;\nr_ble_lll_conn_update_anchor = 0x40001588;\nr_ble_lll_conn_update_conn_ind_params = 0x4000158c;\nr_ble_lll_conn_update_tx_buffer = 0x40001594;\nr_ble_lll_deinit = 0x40001598;\nr_ble_lll_dtm_calculate_itvl = 0x4000159c;\nr_ble_lll_dtm_ctx_free = 0x400015a0;\nr_ble_lll_dtm_deinit = 0x400015a4;\nr_ble_lll_dtm_end_test = 0x400015a8;\nr_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;\nr_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;\nr_ble_lll_dtm_init = 0x400015b4;\nr_ble_lll_dtm_reset = 0x400015b8;\nr_ble_lll_dtm_rx_create_ctx = 0x400015bc;\nr_ble_lll_dtm_rx_isr_end = 0x400015c0;\nr_ble_lll_dtm_rx_isr_start = 0x400015c4;\nr_ble_lll_dtm_rx_pkt_in = 0x400015c8;\nr_ble_lll_dtm_rx_sched_cb = 0x400015cc;\nr_ble_lll_dtm_rx_start = 0x400015d0;\nr_ble_lll_dtm_rx_test = 0x400015d4;\nr_ble_lll_dtm_set_next = 0x400015d8;\nr_ble_lll_dtm_tx_done = 0x400015e0;\nr_ble_lll_dtm_tx_sched_cb = 0x400015e4;\nr_ble_lll_dtm_tx_test = 0x400015e8;\nr_ble_lll_dtm_wfr_timer_exp = 0x400015ec;\nr_ble_lll_event_rx_pkt = 0x400015f0;\nr_ble_lll_ext_scan_coex_dpc_process = 0x400015f4;\nr_ble_lll_ext_scan_coex_dpc_pti_get = 0x400015f8;\nr_ble_lll_ext_scan_coex_dpc_update = 0x400015fc;\nr_ble_lll_ext_scan_coex_dpc_update_on_start = 0x40001600;\nr_ble_lll_hci_dtm_rx_test = 0x40001604;\nr_ble_lll_hci_dtm_rx_test_v2 = 0x40001608;\nr_ble_lll_hci_dtm_tx_test = 0x4000160c;\nr_ble_lll_hci_dtm_tx_test_ext = 0x40001610;\nr_ble_lll_hci_dtm_tx_test_v2 = 0x40001614;\nr_ble_lll_hci_dtm_tx_test_v2_ext = 0x40001618;\nr_ble_lll_init = 0x4000161c;\nr_ble_lll_init_pre_process = 0x40001620;\nr_ble_lll_per_adv_coex_dpc_calc_pti_update_itvl = 0x40001628;\nr_ble_lll_per_adv_coex_dpc_process = 0x4000162c;\nr_ble_lll_per_adv_coex_dpc_pti_get = 0x40001630;\nr_ble_lll_per_adv_coex_dpc_update = 0x40001634;\nr_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638;\nr_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c;\nr_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640;\nr_ble_lll_reset = 0x40001644;\nr_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;\nr_ble_lll_rfmgmt_deinit = 0x4000164c;\nr_ble_lll_rfmgmt_disable = 0x40001650;\nr_ble_lll_rfmgmt_enable = 0x40001654;\nr_ble_lll_rfmgmt_enable_now = 0x40001658;\nr_ble_lll_rfmgmt_init = 0x4000165c;\nr_ble_lll_rfmgmt_is_enabled = 0x40001660;\nr_ble_lll_rfmgmt_release = 0x40001664;\nr_ble_lll_rfmgmt_release_ev = 0x40001668;\nr_ble_lll_rfmgmt_reset = 0x4000166c;\nr_ble_lll_rfmgmt_scan_changed = 0x40001670;\nr_ble_lll_rfmgmt_sched_changed = 0x40001674;\nr_ble_lll_rfmgmt_set_sleep_cb = 0x40001678;\nr_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c;\nr_ble_lll_rfmgmt_timer_exp = 0x40001680;\nr_ble_lll_rfmgmt_timer_reschedule = 0x40001684;\nr_ble_lll_rx_pdu_in = 0x40001688;\nr_ble_lll_rx_pkt_in = 0x4000168c;\nr_ble_lll_rx_pkt_isr = 0x40001690;\nr_ble_lll_scan_abort_aux_sched = 0x40001694;\nr_ble_lll_scan_aux_data_free = 0x40001698;\nr_ble_lll_scan_chk_resume = 0x4000169c;\nr_ble_lll_scan_clean_cur_aux_data = 0x400016a0;\nr_ble_lll_scan_coex_event_cb = 0x400016a4;\nr_ble_lll_scan_common_init = 0x400016a8;\nr_ble_lll_scan_deinit = 0x400016ac;\nr_ble_lll_scan_duration_period_timers_restart = 0x400016b0;\nr_ble_lll_scan_duration_period_timers_stop = 0x400016b4;\nr_ble_lll_scan_duration_timer_cb = 0x400016b8;\nr_ble_lll_scan_event_proc = 0x400016bc;\nr_ble_lll_scan_ext_adv_init = 0x400016c0;\nr_ble_lll_scan_halt = 0x400016c4;\nr_ble_lll_scan_has_sent_scan_req = 0x400016c8;\nr_ble_lll_scan_init = 0x400016cc;\nr_ble_lll_scan_npl_init = 0x400016d0;\nr_ble_lll_scan_npl_reset = 0x400016d4;\nr_ble_lll_scan_npl_restore = 0x400016d8;\nr_ble_lll_scan_npl_store = 0x400016dc;\nr_ble_lll_scan_period_timer_cb = 0x400016e0;\nr_ble_lll_scan_process_adv_in_isr = 0x400016e4;\nr_ble_lll_scan_req_backoff = 0x400016ec;\nr_ble_lll_scan_restart = 0x400016f0;\nr_ble_lll_scan_sched_next_aux = 0x40001700;\nr_ble_lll_scan_sched_remove = 0x40001704;\nr_ble_lll_scan_start = 0x40001708;\nr_ble_lll_scan_start_rx = 0x4000170c;\nr_ble_lll_scan_stop = 0x40001710;\nr_ble_lll_scan_timer_cb = 0x40001718;\nr_ble_lll_sched_adv_new = 0x4000171c;\nr_ble_lll_sched_adv_resched_pdu = 0x40001720;\nr_ble_lll_sched_adv_reschedule = 0x40001724;\nr_ble_lll_sched_aux_scan = 0x40001728;\nr_ble_lll_sched_conn_overlap = 0x4000172c;\nr_ble_lll_sched_conn_reschedule = 0x40001730;\nr_ble_lll_sched_deinit = 0x40001734;\nr_ble_lll_sched_dtm = 0x40001738;\nr_ble_lll_sched_env_init = 0x4000173c;\nr_ble_lll_sched_execute_item = 0x40001744;\nr_ble_lll_sched_init = 0x40001748;\nr_ble_lll_sched_insert_if_empty = 0x4000174c;\nr_ble_lll_sched_is_overlap = 0x40001750;\nr_ble_lll_sched_master_new = 0x40001754;\nr_ble_lll_sched_next_time = 0x40001758;\nr_ble_lll_sched_overlaps_current = 0x4000175c;\nr_ble_lll_sched_periodic_adv = 0x40001760;\nr_ble_lll_sched_rmv_elem = 0x40001764;\nr_ble_lll_sched_rmv_elem_type = 0x40001768;\nr_ble_lll_sched_run = 0x4000176c;\nr_ble_lll_sched_scan_req_over_aux_ptr = 0x40001770;\nr_ble_lll_sched_slave_new = 0x40001774;\nr_ble_lll_sched_stop = 0x40001778;\nr_ble_lll_sched_sync = 0x4000177c;\nr_ble_lll_sched_sync_overlaps_current = 0x40001780;\nr_ble_lll_sched_sync_reschedule = 0x40001784;\nr_ble_lll_sync_chain_start_cb = 0x40001788;\nr_ble_lll_sync_coex_dpc_process = 0x4000178c;\nr_ble_lll_sync_coex_dpc_pti_get = 0x40001790;\nr_ble_lll_sync_coex_dpc_update = 0x40001794;\nr_ble_lll_sync_current_sm_over = 0x40001798;\nr_ble_lll_sync_deinit = 0x4000179c;\nr_ble_lll_sync_event_end = 0x400017a0;\nr_ble_lll_sync_event_end_cb = 0x400017a4;\nr_ble_lll_sync_get_event_end_time = 0x400017ac;\nr_ble_lll_sync_halt = 0x400017b0;\nr_ble_lll_sync_init = 0x400017b4;\nr_ble_lll_sync_new = 0x400017b8;\nr_ble_lll_sync_reset = 0x400017bc;\nr_ble_lll_sync_reset_sm = 0x400017c0;\nr_ble_lll_sync_rmvd_from_sched = 0x400017c4;\nr_ble_lll_sync_rx_pkt_isr = 0x400017c8;\nr_ble_lll_sync_schedule_chain = 0x400017cc;\nr_ble_lll_sync_stop = 0x400017d0;\nr_ble_lll_sync_trnasfer_sched = 0x400017d4;\nr_ble_phy_access_addr_get = 0x400017d8;\nr_ble_phy_calculate_rxtx_ifs = 0x400017dc;\nr_ble_phy_calculate_rxwindow = 0x400017e0;\nr_ble_phy_calculate_txrx_ifs = 0x400017e4;\nr_ble_phy_check_bb_status = 0x400017e8;\nr_ble_phy_complete_rx_info = 0x400017ec;\nr_ble_phy_config_access_addr = 0x400017f0;\nr_ble_phy_data_make = 0x400017f4;\nr_ble_phy_disable = 0x400017f8;\nr_ble_phy_disable_irq = 0x400017fc;\nr_ble_phy_disable_whitening = 0x40001800;\nr_ble_phy_enable_whitening = 0x40001804;\nr_ble_phy_encrypt_disable = 0x40001808;\nr_ble_phy_env_init = 0x4000180c;\nr_ble_phy_get_current_phy = 0x40001810;\nr_ble_phy_get_packet_counter = 0x40001814;\nr_ble_phy_get_packet_status = 0x40001818;\nr_ble_phy_get_pyld_time_offset = 0x4000181c;\nr_ble_phy_get_rx_phy_mode = 0x40001820;\nr_ble_phy_get_seq_end_st = 0x40001824;\nr_ble_phy_max_data_pdu_pyld = 0x40001830;\nr_ble_phy_mode_config = 0x40001834;\nr_ble_phy_mode_convert = 0x40001838;\nr_ble_phy_mode_write = 0x4000183c;\nr_ble_phy_module_deinit = 0x40001840;\nr_ble_phy_module_init = 0x40001844;\nr_ble_phy_monitor_bb_sync = 0x40001848;\nr_ble_phy_reset_bb_monitor = 0x4000184c;\nr_ble_phy_resolv_list_disable = 0x40001850;\nr_ble_phy_resolv_list_enable = 0x40001854;\nr_ble_phy_restart_sequence = 0x40001858;\nr_ble_phy_rx_set_start_time_forcibly = 0x4000185c;\nr_ble_phy_rxpdu_copy = 0x40001860;\nr_ble_phy_seq_encrypt_enable = 0x40001864;\nr_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001868;\nr_ble_phy_sequence_end_isr = 0x4000186c;\nr_ble_phy_sequence_get_mode = 0x40001870;\nr_ble_phy_sequence_is_running = 0x40001874;\nr_ble_phy_sequence_is_waiting_rsp = 0x40001878;\nr_ble_phy_sequence_single_end = 0x4000187c;\nr_ble_phy_sequence_tx_end_invoke = 0x40001880;\nr_ble_phy_sequence_update_conn_ind_params = 0x40001884;\nr_ble_phy_set_adv_mode = 0x40001888;\nr_ble_phy_set_coex_pti = 0x4000188c;\nr_ble_phy_set_conn_ind_pdu = 0x40001890;\nr_ble_phy_set_conn_mode = 0x40001894;\nr_ble_phy_set_dev_address = 0x40001898;\nr_ble_phy_set_rx_pwr_compensation = 0x4000189c;\nr_ble_phy_set_scan_mode = 0x400018a4;\nr_ble_phy_set_single_packet_rx_sequence = 0x400018ac;\nr_ble_phy_set_single_packet_tx_sequence = 0x400018b0;\nr_ble_phy_set_tx_rx_transition = 0x400018b4;\nr_ble_phy_set_txend_cb = 0x400018b8;\nr_ble_phy_setchan = 0x400018bc;\nr_ble_phy_start_rx_immediately = 0x400018c0;\nr_ble_phy_state_get = 0x400018c4;\nr_ble_phy_timer_config_start_time = 0x400018c8;\nr_ble_phy_timer_start_now = 0x400018cc;\nr_ble_phy_timer_stop = 0x400018d0;\nr_ble_phy_tx_set_start_time = 0x400018d4;\nr_ble_phy_txpwr_set = 0x400018dc;\nr_ble_phy_update_encryption = 0x400018e4;\nr_ble_phy_update_ifs = 0x400018e8;\nr_ble_phy_xcvr_state_get = 0x400018ec;\nr_ble_plf_set_log_level = 0x400018f0;\nr_ble_rtc_wake_up_cpu_init = 0x400018f4;\nr_ble_rtc_wake_up_state_clr = 0x400018f8;\nr_ble_vendor_hci_register = 0x400018fc;\nr_bt_rf_coex_cfg_set = 0x40001900;\nr_bt_rf_coex_coded_txrx_time_upper_lim = 0x40001904;\nr_bt_rf_coex_dft_pti_set = 0x40001908;\nr_bt_rf_coex_hook_deinit = 0x4000190c;\nr_bt_rf_coex_hook_init = 0x40001910;\nr_bt_rf_coex_hook_st_set = 0x40001914;\nr_bt_rf_coex_hooks_p_set_default = 0x40001918;\nr_btdm_disable_adv_delay = 0x4000191c;\nr_btdm_switch_phy_coded = 0x40001920;\nr_esp_wait_disabled = 0x40001924;\nr_get_be16 = 0x40001928;\nr_get_be24 = 0x4000192c;\nr_get_be32 = 0x40001930;\nr_get_be64 = 0x40001934;\nr_get_le16 = 0x40001938;\nr_get_le24 = 0x4000193c;\nr_get_le32 = 0x40001940;\nr_get_le64 = 0x40001944;\nr_get_local_irk_offset = 0x40001948;\nr_get_local_rpa_offset = 0x4000194c;\nr_get_max_skip = 0x40001950;\nr_get_peer_id_offset = 0x40001954;\nr_get_peer_irk_offset = 0x40001958;\nr_get_peer_rpa_offset = 0x4000195c;\nr_hal_rtc_intr_init = 0x40001960;\nr_hal_rtc_irq_handler = 0x40001964;\nr_hal_timer_deinit = 0x40001968;\nr_hal_timer_disable_irq = 0x4000196c;\nr_hal_timer_env_init = 0x40001970;\nr_hal_timer_process = 0x40001978;\nr_hal_timer_read = 0x4000197c;\nr_hal_timer_read_tick = 0x40001980;\nr_hal_timer_set_cb = 0x40001984;\nr_hal_timer_set_exp_tick = 0x40001988;\nr_hal_timer_start = 0x4000198c;\nr_hal_timer_start_at = 0x40001990;\nr_hal_timer_stop = 0x40001994;\nr_hal_timer_task_start = 0x40001998;\nr_ll_assert = 0x4000199c;\nr_mem_init_mbuf_pool = 0x400019a0;\nr_mem_malloc_mbuf_pool = 0x400019a4;\nr_mem_malloc_mbufpkt_pool = 0x400019a8;\nr_mem_malloc_mempool = 0x400019ac;\nr_mem_malloc_mempool_ext = 0x400019b0;\nr_mem_malloc_mempool_gen = 0x400019b4;\nr_mem_pullup_obj = 0x400019b8;\nr_mem_split_frag = 0x400019bc;\nr_os_cputime_get32 = 0x400019c0;\nr_os_cputime_ticks_to_usecs = 0x400019c4;\nr_os_cputime_timer_init = 0x400019c8;\nr_os_cputime_timer_relative = 0x400019cc;\nr_os_cputime_timer_start = 0x400019d0;\nr_os_cputime_timer_stop = 0x400019d4;\nr_os_cputime_usecs_to_ticks = 0x400019d8;\nr_os_mbuf_adj = 0x400019dc;\nr_os_mbuf_append = 0x400019e0;\nr_os_mbuf_appendfrom = 0x400019e4;\nr_os_mbuf_cmpf = 0x400019e8;\nr_os_mbuf_cmpm = 0x400019ec;\nr_os_mbuf_concat = 0x400019f0;\nr_os_mbuf_copydata = 0x400019f4;\nr_os_mbuf_copyinto = 0x400019f8;\nr_os_mbuf_dup = 0x400019fc;\nr_os_mbuf_extend = 0x40001a00;\nr_os_mbuf_free = 0x40001a04;\nr_os_mbuf_free_chain = 0x40001a08;\nr_os_mbuf_get = 0x40001a0c;\nr_os_mbuf_get_pkthdr = 0x40001a10;\nr_os_mbuf_leadingspace = 0x40001a14;\nr_os_mbuf_len = 0x40001a18;\nr_os_mbuf_off = 0x40001a1c;\nr_os_mbuf_pack_chains = 0x40001a20;\nr_os_mbuf_pool_init = 0x40001a24;\nr_os_mbuf_prepend = 0x40001a28;\nr_os_mbuf_prepend_pullup = 0x40001a2c;\nr_os_mbuf_pullup = 0x40001a30;\nr_os_mbuf_trailingspace = 0x40001a34;\nr_os_mbuf_trim_front = 0x40001a38;\nr_os_mbuf_widen = 0x40001a3c;\nr_os_memblock_from = 0x40001a40;\nr_os_memblock_get = 0x40001a44;\nr_os_memblock_put_from_cb = 0x40001a4c;\nr_os_mempool_clear = 0x40001a50;\nr_os_mempool_ext_clear = 0x40001a54;\nr_os_mempool_ext_init = 0x40001a58;\nr_os_mempool_info_get_next = 0x40001a5c;\nr_os_mempool_init = 0x40001a60;\nr_os_mempool_init_internal = 0x40001a64;\nr_os_mempool_is_sane = 0x40001a68;\nr_os_mempool_module_init = 0x40001a6c;\nr_os_mempool_unregister = 0x40001a70;\nr_os_mqueue_get = 0x40001a74;\nr_os_mqueue_init = 0x40001a78;\nr_os_mqueue_put = 0x40001a7c;\nr_os_msys_count = 0x40001a80;\nr_os_msys_get = 0x40001a84;\nr_os_msys_get_pkthdr = 0x40001a88;\nr_os_msys_num_free = 0x40001a8c;\nr_os_msys_register = 0x40001a90;\nr_os_msys_reset = 0x40001a94;\nr_pri_phy_valid = 0x40001a98;\nr_put_be16 = 0x40001a9c;\nr_put_be24 = 0x40001aa0;\nr_put_be32 = 0x40001aa4;\nr_put_be64 = 0x40001aa8;\nr_put_le16 = 0x40001aac;\nr_put_le24 = 0x40001ab0;\nr_put_le32 = 0x40001ab4;\nr_put_le64 = 0x40001ab8;\nr_rtc0_timer_handler = 0x40001abc;\nr_sdkconfig_get_opts = 0x40001ac0;\nr_sdkconfig_set_opts = 0x40001ac4;\nr_sec_phy_valid = 0x40001ac8;\nr_swap_buf = 0x40001acc;\nr_swap_in_place = 0x40001ad0;\n\/* Data (.data, .bss, .rodata) *\/\nble_lll_dtm_module_env_p = 0x3fcdffc4;\ng_ble_lll_dtm_prbs15_data = 0x3ff4fee4;\ng_ble_lll_dtm_prbs9_data = 0x3ff4fde4;\ng_channel_rf_to_index = 0x3ff4fdbc;\ng_ble_lll_rfmgmt_data = 0x3fcdff7c;\ng_ble_sleep_enter_cb = 0x3fcdff78;\ng_ble_sleep_exit_cb = 0x3fcdff74;\nble_lll_sched_env_p = 0x3fcdff70;\nble_ll_env_p = 0x3fcdff6c;\ng_ble_ll_pdu_header_tx_time_ro = 0x3ff4fdb4;\nble_ll_adv_env_p = 0x3fcdff68;\nble_ll_conn_env_p = 0x3fcdff64;\nble_ll_conn_required_phy_mask = 0x3ff4fdb0;\nble_ll_valid_conn_phy_mask = 0x3ff4fdaf;\nble_ll_hci_env_p = 0x3fcdff60;\ng_debug_le_private_key = 0x3ff4fd6c;\ng_ecc_key = 0x3fcdfefc;\nble_ll_rand_env_p = 0x3fcdfef8;\nble_ll_resolv_env_p = 0x3fcdfef4;\ng_ble_ll_resolve_hdr = 0x3fcdfeec;\ng_device_mode_default = 0x3fcdfe68;\nble_ll_scan_classify_filter_aux_check_cb = 0x3fcdfee8;\nble_ll_scan_classify_filter_check_cb = 0x3fcdfee4;\nble_ll_scan_env_p = 0x3fcdfee0;\ng_ble_ll_supp_cmds_ro = 0x3ff4fd3c;\nble_ll_sync_env_p = 0x3fcdfedc;\ng_ble_sca_ppm_tbl_ro = 0x3ff4fd2c;\npriv_config_opts = 0x3fcdfe48;\nble_hci_uart_reset_cmd = 0x3ff4fd28;\nble_hci_trans_env_p = 0x3fcdfed8;\nble_hci_trans_mode = 0x3fcdfe44;\nble_hci_trans_funcs_ptr = 0x3fcdfed4;\nr_ble_lll_stub_funcs_ptr = 0x3fcdfed0;\nr_ble_stub_funcs_ptr = 0x3fcdfecc;\nr_ext_funcs_p = 0x3fcdfec8;\nr_npl_funcs = 0x3fcdfec4;\nble_hw_env_p = 0x3fcdfec0;\nble_phy_module_env_p = 0x3fcdfebc;\ng_ble_phy_chan_freq_ro = 0x3ff4fd00;\ng_ble_phy_mode_pkt_start_off_ro = 0x3ff4fcf8;\ng_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fce8;\ng_ble_phy_t_rxaddrdelay_ro = 0x3ff4fce4;\ng_ble_phy_t_rxenddelay_ro = 0x3ff4fce0;\ng_ble_phy_t_txdelay_ro = 0x3ff4fcdc;\ng_ble_phy_t_txenddelay_ro = 0x3ff4fcd8;\ng_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcc8;\nhal_timer_env_p = 0x3fcdfeb8;\nr_osi_coex_funcs_p = 0x3fcdfeb4;\nbt_rf_coex_hooks = 0x3fcdfeac;\nbt_rf_coex_hooks_p = 0x3fcdfea8;\ncoex_hook_st_group_tab = 0x3ff4fcbc;\ncoex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcb8;\ns_ble_act_count_by_group = 0x3fcdfea4;\ns_ble_coex_st_map = 0x3fcdfe90;\nbt_rf_coex_cfg_cb = 0x3fcdfe74;\nbt_rf_coex_cfg_p = 0x3fcdfe70;\nbt_rf_coex_cfg_rom = 0x3ff4fc9c;\nbt_rf_coex_pti_dft_p = 0x3fcdfe6c;\nbt_rf_coex_pti_dft_rom = 0x3fcdfe04;\nconn_dynamic_pti_param_rom = 0x3ff4fc84;\nconn_phy_coded_max_data_time_param_rom = 0x3ff4fc80;\next_adv_dynamic_pti_param_rom = 0x3ff4fc4c;\next_scan_dynamic_param_rom = 0x3ff4fc14;\nlegacy_adv_dynamic_pti_param_rom = 0x3ff4fbf4;\nper_adv_dynamic_pti_param_rom = 0x3ff4fbd8;\nsync_dynamic_param_rom = 0x3ff4fbc0;\ng_ble_plf_log_level = 0x3fcdfe00;\ng_msys_pool_list = 0x3fcdfdf8;\ng_os_mempool_list = 0x3fcdfdf0;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x40001ad4;\nRC_GetBlockAckTime = 0x40001ad8;\nebuf_list_remove = 0x40001adc;\nesf_buf_alloc = 0x40001ae0;\nesf_buf_alloc_dynamic = 0x40001ae4;\nesf_buf_recycle = 0x40001ae8;\nGetAccess = 0x40001aec;\nhal_mac_is_low_rate_enabled = 0x40001af0;\nhal_mac_tx_get_blockack = 0x40001af4;\nhal_mac_tx_set_ppdu = 0x40001af8;\nic_get_trc = 0x40001afc;\nic_mac_deinit = 0x40001b00;\nic_mac_init = 0x40001b04;\nic_interface_enabled = 0x40001b08;\nis_lmac_idle = 0x40001b0c;\nlmacAdjustTimestamp = 0x40001b10;\nlmacDiscardAgedMSDU = 0x40001b14;\nlmacDiscardMSDU = 0x40001b18;\nlmacEndFrameExchangeSequence = 0x40001b1c;\nlmacIsIdle = 0x40001b20;\nlmacIsLongFrame = 0x40001b24;\nlmacMSDUAged = 0x40001b28;\nlmacPostTxComplete = 0x40001b2c;\nlmacProcessAllTxTimeout = 0x40001b30;\nlmacProcessCollisions = 0x40001b34;\nlmacProcessRxSucData = 0x40001b38;\nlmacReachLongLimit = 0x40001b3c;\nlmacReachShortLimit = 0x40001b40;\nlmacRecycleMPDU = 0x40001b44;\nlmacRxDone = 0x40001b48;\nlmacSetTxFrame = 0x40001b4c;\nlmacTxDone = 0x40001b50;\nlmacTxFrame = 0x40001b54;\nmac_tx_set_duration = 0x40001b58;\nmac_tx_set_htsig = 0x40001b5c;\nmac_tx_set_plcp0 = 0x40001b60;\nmac_tx_set_plcp1 = 0x40001b64;\nmac_tx_set_plcp2 = 0x40001b68;\npm_check_state = 0x40001b6c;\npm_disable_dream_timer = 0x40001b70;\npm_disable_sleep_delay_timer = 0x40001b74;\npm_dream = 0x40001b78;\npm_mac_wakeup = 0x40001b7c;\npm_mac_sleep = 0x40001b80;\npm_enable_active_timer = 0x40001b84;\npm_enable_sleep_delay_timer = 0x40001b88;\npm_local_tsf_process = 0x40001b8c;\npm_set_beacon_filter = 0x40001b90;\npm_is_in_wifi_slice_threshold = 0x40001b94;\npm_is_waked = 0x40001b98;\npm_keep_alive = 0x40001b9c;\npm_on_beacon_rx = 0x40001ba0;\npm_on_data_rx = 0x40001ba4;\npm_on_tbtt = 0x40001ba8;\npm_parse_beacon = 0x40001bac;\npm_process_tim = 0x40001bb0;\n\/*pm_rx_beacon_process = 0x40001bb4;*\/\npm_rx_data_process = 0x40001bb8;\npm_sleep = 0x40001bbc;\npm_sleep_for = 0x40001bc0;\npm_tbtt_process = 0x40001bc4;\nppAMPDU2Normal = 0x40001bc8;\nppAssembleAMPDU = 0x40001bcc;\nppCalFrameTimes = 0x40001bd0;\nppCalSubFrameLength = 0x40001bd4;\nppCalTxAMPDULength = 0x40001bd8;\nppCheckTxAMPDUlength = 0x40001bdc;\nppDequeueRxq_Locked = 0x40001be0;\nppDequeueTxQ = 0x40001be4;\nppEmptyDelimiterLength = 0x40001be8;\nppEnqueueRxq = 0x40001bec;\nppEnqueueTxDone = 0x40001bf0;\nppGetTxQFirstAvail_Locked = 0x40001bf4;\nppGetTxframe = 0x40001bf8;\nppMapTxQueue = 0x40001bfc;\nppProcTxSecFrame = 0x40001c00;\nppProcessRxPktHdr = 0x40001c04;\nppProcessTxQ = 0x40001c08;\nppRecordBarRRC = 0x40001c0c;\nlmacRequestTxopQueue = 0x40001c10;\nlmacReleaseTxopQueue = 0x40001c14;\nppRecycleAmpdu = 0x40001c18;\nppRecycleRxPkt = 0x40001c1c;\nppResortTxAMPDU = 0x40001c20;\nppResumeTxAMPDU = 0x40001c24;\nppRxFragmentProc = 0x40001c28;\nppRxPkt = 0x40001c2c;\nppRxProtoProc = 0x40001c30;\nppSearchTxQueue = 0x40001c34;\nppSearchTxframe = 0x40001c38;\nppSelectNextQueue = 0x40001c3c;\nppSubFromAMPDU = 0x40001c40;\nppTask = 0x40001c44;\nppTxPkt = 0x40001c48;\nppTxProtoProc = 0x40001c4c;\nppTxqUpdateBitmap = 0x40001c50;\npp_coex_tx_request = 0x40001c54;\npp_hdrsize = 0x40001c58;\npp_post = 0x40001c5c;\npp_process_hmac_waiting_txq = 0x40001c60;\nrcGetAmpduSched = 0x40001c64;\nrcUpdateRxDone = 0x40001c68;\nrc_get_trc = 0x40001c6c;\nrc_get_trc_by_index = 0x40001c70;\nrcAmpduLowerRate = 0x40001c74;\nrcampduuprate = 0x40001c78;\nrcClearCurAMPDUSched = 0x40001c7c;\nrcClearCurSched = 0x40001c80;\nrcClearCurStat = 0x40001c84;\nrcGetSched = 0x40001c88;\nrcLowerSched = 0x40001c8c;\nrcSetTxAmpduLimit = 0x40001c90;\nrcTxUpdatePer = 0x40001c94;\nrcUpdateAckSnr = 0x40001c98;\nrcUpdateRate = 0x40001c9c;\nrcUpdateTxDone = 0x40001ca0;\nrcUpdateTxDoneAmpdu2 = 0x40001ca4;\nrcUpSched = 0x40001ca8;\nrssi_margin = 0x40001cac;\nrx11NRate2AMPDULimit = 0x40001cb0;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001cb4;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001cb8;\ntrc_calc_duration = 0x40001cbc;\ntrc_isTxAmpduOperational = 0x40001cc0;\ntrc_onAmpduOp = 0x40001cc4;\nTRC_PER_IS_GOOD = 0x40001cc8;\ntrc_SetTxAmpduState = 0x40001ccc;\ntrc_tid_isTxAmpduOperational = 0x40001cd0;\ntrcAmpduSetState = 0x40001cd4;\nwDevCheckBlockError = 0x40001cd8;\nwDev_AppendRxBlocks = 0x40001cdc;\nwDev_DiscardFrame = 0x40001ce0;\nwDev_GetNoiseFloor = 0x40001ce4;\nwDev_IndicateAmpdu = 0x40001ce8;\nwDev_IndicateFrame = 0x40001cec;\nwdev_mac_reg_load = 0x40001cf0;\nwdev_mac_reg_store = 0x40001cf4;\nwdev_mac_special_reg_load = 0x40001cf8;\nwdev_mac_special_reg_store = 0x40001cfc;\nwdev_mac_wakeup = 0x40001d00;\nwdev_mac_sleep = 0x40001d04;\nwDev_ProcessFiq = 0x40001d08;\nwDev_ProcessRxSucData = 0x40001d0c;\nwdevProcessRxSucDataAll = 0x40001d10;\nwdev_csi_len_align = 0x40001d14;\nppDequeueTxDone_Locked = 0x40001d18;\nppProcTxDone = 0x40001d1c;\n\/*pm_tx_data_done_process = 0x40001d20;*\/\nconfig_is_cache_tx_buf_enabled = 0x40001d24;\nppMapWaitTxq = 0x40001d28;\nppProcessWaitingQueue = 0x40001d2c;\nppDisableQueue = 0x40001d30;\npm_allow_tx = 0x40001d34;\nwdev_is_data_in_rxlist = 0x40001d38;\nppProcTxCallback = 0x40001d3c;\npm_is_open = 0x40001d40;\npm_wake_up = 0x40001d44;\npm_wake_done = 0x40001d48;\npm_disable_disconnected_sleep_delay_timer = 0x40001d4c;\npm_enable_disconnected_sleep_delay_timer = 0x40001d50;\nhal_mac_get_txq_state = 0x40001d54;\nhal_mac_clr_txq_state = 0x40001d58;\nhal_mac_tx_set_cca = 0x40001d5c;\nhal_mac_set_txq_invalid = 0x40001d60;\nhal_mac_txq_disable = 0x40001d64;\nhal_mac_is_txq_enabled = 0x40001d68;\nhal_mac_get_txq_pmd = 0x40001d6c;\nlmacDiscardFrameExchangeSequence = 0x40001d70;\nlmacDisableTransmit = 0x40001d74;\nlmacProcessTxTimeout = 0x40001d78;\nlmacProcessTxSuccess = 0x40001d7c;\nlmacProcessCollision = 0x40001d80;\nlmacProcessTxRtsError = 0x40001d84;\nlmacProcessCtsTimeout = 0x40001d88;\nlmacProcessTxComplete = 0x40001d8c;\nlmacProcessAckTimeout = 0x40001d90;\nlmacProcessTxError = 0x40001d94;\nlmacProcessTxseckiderr = 0x40001d98;\nrcReachRetryLimit = 0x40001d9c;\nlmacProcessShortRetryFail = 0x40001da0;\nlmacEndRetryAMPDUFail = 0x40001da4;\nppFillAMPDUBar = 0x40001da8;\nrcGetRate = 0x40001dac;\nppReSendBar = 0x40001db0;\nlmacProcessLongRetryFail = 0x40001db4;\nlmacRetryTxFrame = 0x40001db8;\nlmacProcessCollisions_task = 0x40001dbc;\nlmacProcessTxopQComplete = 0x40001dc0;\nlmacInitAc = 0x40001dc4;\nlmacInit = 0x40001dc8;\nmac_tx_set_txop_q = 0x40001dcc;\nhal_init = 0x40001dd0;\nhal_mac_rx_set_policy = 0x40001dd4;\nhal_mac_set_bssid = 0x40001dd8;\nmac_rx_policy_init = 0x40001ddc;\n\/*mac_txrx_init = 0x40001de0;*\/\nmac_rxbuf_init = 0x40001de4;\nmac_last_rxbuf_init = 0x40001de8;\nhal_attenna_init = 0x40001dec;\nhal_timer_update_by_rtc = 0x40001df0;\nhal_coex_pti_init = 0x40001df4;\nlmac_stop_hw_txq = 0x40001df8;\nppDirectRecycleAmpdu = 0x40001dfc;\nesp_wifi_internal_set_rts = 0x40001e00;\nesp_wifi_internal_get_rts = 0x40001e04;\nppTxFragmentProc = 0x40001e08;\n\/*esf_buf_setup = 0x40001e0c;*\/\nhal_agreement_add_rx_ba = 0x40001e10;\nhal_agreement_del_rx_ba = 0x40001e14;\nhal_crypto_set_key_entry = 0x40001e18;\nhal_crypto_get_key_entry = 0x40001e1c;\nhal_crypto_clr_key_entry = 0x40001e20;\nconfig_get_wifi_task_stack_size = 0x40001e24;\npp_create_task = 0x40001e28;\nhal_set_sta_tsf_wakeup = 0x40001e2c;\nhal_set_rx_beacon_pti = 0x40001e30;\npm_start = 0x40001e34;\npm_stop = 0x40001e38;\nhal_disable_sta_tbtt = 0x40001e3c;\nppCalTxopDur = 0x40001e40;\nwDev_IndicateCtrlFrame = 0x40001e44;\nhal_enable_sta_tbtt = 0x40001e48;\nhal_set_sta_tbtt = 0x40001e4c;\npm_update_next_tbtt = 0x40001e50;\npm_set_sleep_type = 0x40001e54;\nwDev_Rxbuf_Init = 0x40001e58;\nwDev_Rxbuf_Deinit = 0x40001e5c;\nppCalTkipMic = 0x40001e60;\nwDev_SnifferRxData = 0x40001e64;\nhal_crypto_enable = 0x40001e68;\nhal_crypto_disable = 0x40001e6c;\nwDev_Insert_KeyEntry = 0x40001e70;\nwDev_remove_KeyEntry = 0x40001e74;\nrc_enable_trc = 0x40001e78;\nrc_set_per_conn_fix_rate = 0x40001e7c;\nwdev_csi_rx_process = 0x40001e80;\nwDev_SnifferRxAmpdu = 0x40001e84;\nhal_mac_tsf_reset = 0x40001e88;\ndbg_lmac_statis_dump = 0x40001e8c;\ndbg_lmac_rxtx_statis_dump = 0x40001e90;\ndbg_lmac_hw_statis_dump = 0x40001e94;\ndbg_lmac_diag_statis_dump = 0x40001e98;\ndbg_lmac_ps_statis_dump = 0x40001e9c;\npp_timer_do_process = 0x40001ea0;\nrcUpdateAMPDUParam = 0x40001ea4;\nrcUpdatePhyMode = 0x40001ea8;\nrcGetHighestRateIdx = 0x40001eac;\npm_tx_null_data_done_process = 0x40001eb0;\npm_tx_data_process = 0x40001eb4;\npm_attach = 0x40001eb8;\npm_coex_schm_process = 0x40001ebc;\nppInitTxq = 0x40001ec0;\npp_attach = 0x40001ec4;\npp_deattach = 0x40001ec8;\npm_on_probe_resp_rx = 0x40001ecc;\nhal_set_sta_tsf = 0x40001ed0;\nic_update_sta_tsf = 0x40001ed4;\nic_tx_pkt = 0x40001ed8;\npm_send_probe_stop = 0x40001edc;\npm_send_probe_start = 0x40001ee0;\npm_on_coex_schm_process_restart = 0x40001ee4;\nhal_mac_set_rxq_policy = 0x40001ee8;\nhal_sniffer_enable = 0x40001eec;\nhal_sniffer_disable = 0x40001ef0;\nhal_sniffer_rx_set_promis = 0x40001ef4;\nhal_sniffer_rx_clr_statistics = 0x40001ef8;\nhal_sniffer_set_promis_misc_pkt = 0x40001efc;\ntsf_hal_set_tsf_enable = 0x40001f00;\ntsf_hal_set_tsf_disable = 0x40001f04;\ntsf_hal_is_tsf_enabled = 0x40001f08;\ntsf_hal_set_modem_wakeup_early_time = 0x40001f0c;\ntsf_hal_get_counter_value = 0x40001f10;\ntsf_hal_set_counter_value = 0x40001f14;\ntsf_hal_get_time = 0x40001f18;\ntsf_hal_set_time = 0x40001f1c;\ntsf_hal_set_tbtt_enable = 0x40001f20;\ntsf_hal_set_tbtt_disable = 0x40001f24;\ntsf_hal_set_tbtt_intr_enable = 0x40001f28;\ntsf_hal_set_tbtt_intr_disable = 0x40001f2c;\ntsf_hal_set_tbtt_soc_wakeup_enable = 0x40001f30;\ntsf_hal_set_tbtt_soc_wakeup_disable = 0x40001f34;\ntsf_hal_set_tbtt_start_time = 0x40001f38;\ntsf_hal_set_tbtt_early_time = 0x40001f3c;\ntsf_hal_set_tbtt_interval = 0x40001f40;\ntsf_hal_get_tbtt_interval = 0x40001f44;\ntsf_hal_set_timer_enable = 0x40001f48;\ntsf_hal_set_timer_disable = 0x40001f4c;\ntsf_hal_set_timer_target = 0x40001f50;\ntsf_hal_get_timer_target = 0x40001f54;\ntsf_hal_set_timer_intr_enable = 0x40001f58;\ntsf_hal_set_timer_intr_disable = 0x40001f5c;\ntsf_hal_set_timer_soc_wakeup_enable = 0x40001f60;\ntsf_hal_set_timer_soc_wakeup_disable = 0x40001f64;\npm_disconnected_wake = 0x40001f68;\npm_get_connectionless_status = 0x40001f6c;\npm_update_by_connectionless_status = 0x40001f70;\npm_connectionless_wake_interval_timeout_process = 0x40001f74;\npm_connectionless_wake_window_timeout_process = 0x40001f78;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff4fbbc;\npTxRx = 0x3fcdfdec;\nlmacConfMib_ptr = 0x3fcdfde8;\nour_wait_eb = 0x3fcdfde4;\nour_tx_eb = 0x3fcdfde0;\npp_wdev_funcs = 0x3fcdfddc;\ng_osi_funcs_p = 0x3fcdfdd8;\nwDevCtrl_ptr = 0x3fcdfdd4;\ng_wdev_last_desc_reset_ptr = 0x3ff4fbb8;\nwDevMacSleep_ptr = 0x3fcdfdd0;\ng_lmac_cnt_ptr = 0x3fcdfdcc;\nour_controls_ptr = 0x3ff4fbb4;\npp_sig_cnt_ptr = 0x3fcdfdc8;\ng_eb_list_desc_ptr = 0x3fcdfdc4;\ns_fragment_ptr = 0x3fcdfdc0;\nif_ctrl_ptr = 0x3fcdfdbc;\ng_intr_lock_mux = 0x3fcdfdb8;\ng_wifi_global_lock = 0x3fcdfdb4;\ns_wifi_queue = 0x3fcdfdb0;\npp_task_hdl = 0x3fcdfdac;\ns_pp_task_create_sem = 0x3fcdfda8;\ns_pp_task_del_sem = 0x3fcdfda4;\ng_wifi_menuconfig_ptr = 0x3fcdfda0;\nxphyQueue = 0x3fcdfd9c;\nap_no_lr_ptr = 0x3fcdfd98;\nrc11BSchedTbl_ptr = 0x3fcdfd94;\nrc11NSchedTbl_ptr = 0x3fcdfd90;\nrcLoRaSchedTbl_ptr = 0x3fcdfd8c;\nBasicOFDMSched_ptr = 0x3fcdfd88;\ntrc_ctl_ptr = 0x3fcdfd84;\ng_pm_cnt_ptr = 0x3fcdfd80;\ng_pm_ptr = 0x3fcdfd7c;\ng_pm_cfg_ptr = 0x3fcdfd78;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdfd74;\ng_txop_queue_status_ptr = 0x3fcdfd70;\ng_mac_sleep_en_ptr = 0x3fcdfd6c;\ng_mesh_is_root_ptr = 0x3fcdfd68;\ng_mesh_topology_ptr = 0x3fcdfd64;\ng_mesh_init_ps_type_ptr = 0x3fcdfd60;\ng_mesh_is_started_ptr = 0x3fcdfd5c;\ng_config_func = 0x3fcdfd58;\ng_net80211_tx_func = 0x3fcdfd54;\ng_timer_func = 0x3fcdfd50;\ns_michael_mic_failure_cb = 0x3fcdfd4c;\nwifi_sta_rx_probe_req = 0x3fcdfd48;\ng_tx_done_cb_func = 0x3fcdfd44;\ng_per_conn_trc = 0x3fcdfd28;\ns_encap_amsdu_func = 0x3fcdfd24;\nbars = 0x3fcdfc84;\neb_txdesc_space = 0x3fcdfbf4;\neb_space = 0x3fcdfb54;\ng_pd_mac_in_light_sleep = 0x3fcdfb50;\ns_fix_rate_mask = 0x3fcdfb4c;\ns_fix_rate = 0x3fcdfb44;\ng_wdev_csi_rx = 0x3fcdfb40;\ng_wdev_csi_rx_ctx = 0x3fcdfb3c;\nBcnSendTick = 0x3fcdfb38;\ng_pp_timer_info_ptr = 0x3fcdfb34;\nrcP2P11NSchedTbl_ptr = 0x3fcdfb30;\nrcP2P11GSchedTbl_ptr = 0x3fcdfb2c;\nrc11GSchedTbl_ptr = 0x3fcdfb28;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001f7c;\nampdu_dispatch = 0x40001f80;\nampdu_dispatch_all = 0x40001f84;\nampdu_dispatch_as_many_as_possible = 0x40001f88;\nampdu_dispatch_movement = 0x40001f8c;\nampdu_dispatch_upto = 0x40001f90;\nchm_is_at_home_channel = 0x40001f94;\ncnx_node_is_existing = 0x40001f98;\ncnx_node_search = 0x40001f9c;\nic_ebuf_recycle_rx = 0x40001fa0;\nic_ebuf_recycle_tx = 0x40001fa4;\nic_reset_rx_ba = 0x40001fa8;\nieee80211_align_eb = 0x40001fac;\nieee80211_ampdu_reorder = 0x40001fb0;\nieee80211_ampdu_start_age_timer = 0x40001fb4;\nieee80211_encap_esfbuf = 0x40001fb8;\nieee80211_is_tx_allowed = 0x40001fbc;\nieee80211_output_pending_eb = 0x40001fc0;\nieee80211_output_process = 0x40001fc4;\nieee80211_set_tx_desc = 0x40001fc8;\n\/*sta_input = 0x40001fcc;*\/\nwifi_get_macaddr = 0x40001fd0;\nwifi_rf_phy_disable = 0x40001fd4;\nwifi_rf_phy_enable = 0x40001fd8;\nic_ebuf_alloc = 0x40001fdc;\nieee80211_classify = 0x40001fe0;\nieee80211_copy_eb_header = 0x40001fe4;\nieee80211_recycle_cache_eb = 0x40001fe8;\nieee80211_search_node = 0x40001fec;\nroundup2 = 0x40001ff0;\nieee80211_crypto_encap = 0x40001ff4;\nieee80211_crypto_decap = 0x40001ff8;\nieee80211_decap = 0x40001ffc;\nieee80211_set_tx_pti = 0x40002000;\nwifi_is_started = 0x40002004;\nieee80211_gettid = 0x40002008;\nieee80211_ccmp_decrypt = 0x4000200c;\nieee80211_ccmp_encrypt = 0x40002010;\nccmp_encap = 0x40002014;\nccmp_decap = 0x40002018;\ntkip_encap = 0x4000201c;\ntkip_decap = 0x40002020;\nwep_encap = 0x40002024;\nwep_decap = 0x40002028;\ndbg_hmac_rxtx_statis_dump = 0x4000202c;\ndbg_hmac_statis_dump = 0x40002030;\nieee80211_send_action_vendor_spec = 0x40002034;\nieee80211_deauth_construct = 0x40002040;\nieee80211_disassoc_construct = 0x40002044;\nieee80211_vnd_lora_ie_size = 0x40002048;\nieee80211_vnd_ie_size = 0x4000204c;\nieee80211_add_ssid = 0x40002050;\nieee80211_add_rates = 0x40002054;\nieee80211_add_xrates = 0x40002058;\nieee80211_is_ht_cipher = 0x4000205c;\nieee80211_assoc_resp_construct = 0x40002064;\nieee80211_setup_lr_rates = 0x40002068;\nieee80211_ht_node_init = 0x4000206c;\nieee80211_is_support_rate = 0x40002070;\nieee80211_setup_rates = 0x40002074;\nieee80211_is_lr_only = 0x40002078;\nieee80211_setup_phy_mode = 0x4000207c;\nieee80211_sta_is_connected = 0x40002080;\ncurrent_task_is_wifi_task = 0x40002084;\nwifi_get_init_state = 0x40002088;\nieee80211_timer_process = 0x4000208c;\ncnx_coexist_timeout = 0x40002090;\n\/* sta_recv_mgmt = 0x40002094;*\/\nieee80211_send_setup = 0x40002098;\nieee80211_send_probereq = 0x4000209c;\nsta_auth_shared = 0x400020a4;\ncnx_coexist_timeout_process = 0x400020ac;\nieee80211_alloc_challenge = 0x400020b0;\ncnx_assoc_timeout = 0x400020b4;\nieee80211_vnd_ie_set = 0x400020b8;\nieee80211_vnd_lora_ie_set = 0x400020bc;\nieee80211_add_wme_param = 0x400020c0;\nieee80211_add_dsparams = 0x400020c4;\nieee80211_add_csa = 0x400020c8;\nieee80211_add_extcap = 0x400020cc;\nieee80211_regdomain_get_country = 0x400020d0;\nieee80211_add_countryie = 0x400020d4;\nieee80211_amsdu_adjust_head = 0x400020dc;\nieee80211_amsdu_adjust_last_length = 0x400020e0;\nieee80211_amsdu_send_check = 0x400020e4;\nieee80211_amsdu_encap_check = 0x400020e8;\nieee80211_amsdu_length_check = 0x400020ec;\nieee80211_encap_amsdu = 0x400020f0;\nieee80211_output_raw_process = 0x400020f4;\nieee80211_raw_frame_sanity_check = 0x400020fc;\nieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;\nieee80211_alloc_tx_buf = 0x40002108;\nieee80211_output_do = 0x4000210c;\nieee80211_send_nulldata = 0x40002110;\nieee80211_setup_robust_mgmtframe = 0x40002114;\nieee80211_mgmt_output = 0x40002118;\nieee80211_encap_null_data = 0x4000211c;\nieee80211_send_deauth = 0x40002120;\nieee80211_alloc_deauth = 0x40002124;\nieee80211_send_proberesp = 0x40002128;\nieee80211_tx_mgt_cb = 0x4000212c;\nieee80211_getcapinfo = 0x40002130;\nsta_rx_csa = 0x40002134;\nsta_recv_sa_query_resp = 0x40002144;\nieee80211_set_max_rate = 0x4000214c;\nic_set_sta = 0x40002150;\nieee80211_parse_wpa = 0x40002158;\nieee80211_add_assoc_req_ies = 0x40002160;\nieee80211_add_probe_req_ies = 0x40002164;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdfb24;\ng_scan = 0x3fcdfb20;\ng_chm = 0x3fcdfb1c;\ng_ic_ptr = 0x3fcdfb18;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_tx_cacheq_ptr = 0x3fcdfb14;\ns_netstack_free = 0x3fcdfb10;\nmesh_rxcb = 0x3fcdfb0c;\nsta_rxcb = 0x3fcdfb08;\nccmp_ptr = 0x3fcdfb04;\ns_wifi_nvs_ptr = 0x3fcdfb00;\ntkip_ptr = 0x3fcdfafc;\nwep_ptr = 0x3fcdfaf8;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_misc_nvs = 0x3fcdfaf0;\ns_wifi_init_state = 0x3fcdfac0;\ns_wifi_task_hdl = 0x3fcdfaec;\nin_rssi_adjust = 0x3fcdfae8;\nrssi_saved = 0x3fcdfae0;\nrssi_index = 0x3fcdfadc;\ns_sa_query_retries = 0x3fcdfad8;\ns_sa_query_success = 0x3fcdfad5;\ng_sta_connected_flag = 0x3fcdfad4;\nwpa_crypto_funcs_ptr = 0x3fcdfad0;\ns_netstack_ref = 0x3fcdfacc;\nsta_csa_timer_ptr = 0x3fcdfac8;\ns_trans_id = 0x3fcdfac4;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x40002168;\ncoex_bt_release = 0x4000216c;\ncoex_bt_request = 0x40002170;\ncoex_core_ble_conn_dyn_prio_get = 0x40002174;\ncoex_core_event_duration_get = 0x40002178;\ncoex_core_pti_get = 0x4000217c;\ncoex_core_release = 0x40002180;\ncoex_core_request = 0x40002184;\ncoex_core_status_get = 0x40002188;\ncoex_core_timer_idx_get = 0x4000218c;\ncoex_event_duration_get = 0x40002190;\ncoex_hw_timer_disable = 0x40002194;\ncoex_hw_timer_enable = 0x40002198;\ncoex_hw_timer_set = 0x4000219c;\ncoex_schm_interval_set = 0x400021a0;\ncoex_schm_lock = 0x400021a4;\ncoex_schm_unlock = 0x400021a8;\ncoex_status_get = 0x400021ac;\ncoex_wifi_release = 0x400021b0;\nesp_coex_ble_conn_dynamic_prio_get = 0x400021b4;\n\/*coex_hw_timer_tick_get = 0x400021b8;*\/\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdfabc;\ncoex_pti_tab_ptr = 0x3fcdfab8;\ncoex_schm_env_ptr = 0x3fcdfab4;\ncoexist_funcs = 0x3fcdfab0;\ng_coa_funcs_p = 0x3fcdfaac;\ng_coex_param_ptr = 0x3fcdfaa8;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_param_addr = 0x400021bc;\nphy_get_romfuncs = 0x400021c0;\nchip729_phyrom_version = 0x400021c4;\nchip729_phyrom_version_num = 0x400021c8;\nrom_get_rc_dout = 0x400021cc;\nrc_cal = 0x400021d0;\nphy_analog_delay_cal = 0x400021d4;\nphy_rx_rifs_en = 0x400021d8;\nphy_current_level_set = 0x400021dc;\nphy_bbpll_en_usb = 0x400021e0;\nphy_bt_power_track = 0x400021e4;\nphy_xpd_tsens = 0x400021e8;\nbb_wdt_rst_enable = 0x400021ec;\nbb_wdt_int_enable = 0x400021f0;\nbb_wdt_timeout_clear = 0x400021f4;\nbb_wdt_get_status = 0x400021f8;\nrom_enter_critical_phy = 0x400021fc;\nrom_exit_critical_phy = 0x40002200;\nrom_bb_bss_cbw40 = 0x40002204;\nrom_set_chan_reg = 0x40002208;\nabs_temp = 0x4000220c;\nset_chan_cal_interp = 0x40002210;\nloopback_mode_en = 0x40002214;\nget_data_sat = 0x40002218;\nphy_byte_to_word = 0x4000221c;\nphy_get_rx_freq = 0x40002220;\ni2c_master_reset = 0x40002224;\nchan14_mic_enable = 0x40002228;\nchan14_mic_cfg = 0x4000222c;\nset_adc_rand = 0x40002230;\nphy_set_most_tpw = 0x40002234;\nphy_get_most_tpw = 0x40002238;\nesp_tx_state_out = 0x4000223c;\nphy_get_adc_rand = 0x40002240;\nphy_internal_delay = 0x40002244;\nphy_ftm_comp = 0x40002248;\nphy_11p_set = 0x4000224c;\nphy_freq_mem_backup = 0x40002250;\nant_dft_cfg = 0x40002254;\nant_wifitx_cfg = 0x40002258;\nant_wifirx_cfg = 0x4000225c;\nant_bttx_cfg = 0x40002260;\nant_btrx_cfg = 0x40002264;\nphy_chan_dump_cfg = 0x40002268;\nphy_enable_low_rate = 0x4000226c;\nphy_disable_low_rate = 0x40002270;\nphy_dig_reg_backup = 0x40002274;\nphy_chan_filt_set = 0x40002278;\nphy_rx11blr_cfg = 0x4000227c;\nset_cca = 0x40002280;\nset_rx_sense = 0x40002284;\nrx_gain_force = 0x40002288;\nrom_phy_en_hw_set_freq = 0x4000228c;\nrom_phy_dis_hw_set_freq = 0x40002290;\nwr_rf_freq_mem = 0x40002294;\nfreq_i2c_write_set = 0x40002298;\nwrite_pll_cap_mem = 0x4000229c;\npll_dac_mem_update = 0x400022a0;\npll_cap_mem_update = 0x400022a4;\nget_rf_freq_cap = 0x400022a8;\nget_rf_freq_init = 0x400022ac;\nfreq_get_i2c_data = 0x400022b0;\nfreq_i2c_data_write = 0x400022b4;\nset_chan_freq_hw_init = 0x400022b8;\nset_chan_freq_sw_start = 0x400022bc;\nrom_get_i2c_read_mask = 0x400022c0;\nrom_get_i2c_mst0_mask = 0x400022c4;\nrom_get_i2c_hostid = 0x400022c8;\nrom_chip_i2c_readReg_org = 0x400022cc;\nrom_chip_i2c_readReg = 0x400022d0;\nrom_i2c_paral_set_mst0 = 0x400022d4;\nrom_i2c_paral_set_read = 0x400022d8;\nrom_i2c_paral_read = 0x400022dc;\nrom_i2c_paral_write = 0x400022e0;\nrom_i2c_paral_write_num = 0x400022e4;\nrom_i2c_paral_write_mask = 0x400022e8;\nrom_i2c_readReg = 0x400022ec;\nrom_chip_i2c_writeReg = 0x400022f0;\nrom_i2c_writeReg = 0x400022f4;\nrom_i2c_readReg_Mask = 0x400022f8;\nrom_i2c_writeReg_Mask = 0x400022fc;\nrom_set_txcap_reg = 0x40002300;\ni2c_sar2_init_code = 0x40002304;\nphy_i2c_init1 = 0x40002308;\nphy_i2c_init2 = 0x4000230c;\nphy_get_i2c_data = 0x40002310;\nbias_reg_set = 0x40002314;\ni2c_rc_cal_set = 0x40002318;\ni2c_bbpll_set = 0x4000231c;\nrom_phy_xpd_rf = 0x40002320;\nphy_wakeup_init_rom = 0x40002324;\nregister_chipv7_phy_init_param = 0x40002328;\nphy_reg_init = 0x4000232c;\nphy_close_rf_rom = 0x40002330;\nrom_pbus_force_mode = 0x40002334;\nrom_pbus_rd_addr = 0x40002338;\nrom_pbus_rd_shift = 0x4000233c;\nrom_pbus_force_test = 0x40002340;\nrom_pbus_rd = 0x40002344;\nrom_pbus_debugmode = 0x40002348;\nrom_pbus_workmode = 0x4000234c;\nrom_pbus_set_rxgain = 0x40002350;\nrom_pbus_xpd_rx_off = 0x40002354;\nrom_pbus_xpd_rx_on = 0x40002358;\nrom_pbus_xpd_tx_off = 0x4000235c;\nrom_pbus_xpd_tx_on = 0x40002360;\nrom_pbus_set_dco = 0x40002364;\nrom_set_loopback_gain = 0x40002368;\nrom_txcal_debuge_mode = 0x4000236c;\nrom_txcal_work_mode = 0x40002370;\nset_pbus_mem = 0x40002374;\nrom_pwdet_sar2_init = 0x40002378;\nrom_en_pwdet = 0x4000237c;\nrom_get_sar_sig_ref = 0x40002380;\nrom_pwdet_tone_start = 0x40002384;\nrom_get_tone_sar_dout = 0x40002388;\nrom_get_fm_sar_dout = 0x4000238c;\nrom_txtone_linear_pwr = 0x40002390;\nrom_get_power_db = 0x40002394;\nrom_meas_tone_pwr_db = 0x40002398;\nrom_pkdet_vol_start = 0x4000239c;\nrom_read_sar_dout = 0x400023a0;\nrom_read_sar2_code = 0x400023a4;\nrom_get_sar2_vol = 0x400023a8;\nrom_get_pll_vol = 0x400023ac;\nrom_tx_pwctrl_bg_init = 0x400023b0;\nrom_phy_pwdet_always_en = 0x400023b4;\nrom_phy_pwdet_onetime_en = 0x400023b8;\nlinear_to_db = 0x400023bc;\nrom_disable_agc = 0x400023c0;\nrom_enable_agc = 0x400023c4;\nrom_disable_wifi_agc = 0x400023c8;\nrom_enable_wifi_agc = 0x400023cc;\nrom_write_gain_mem = 0x400023d0;\nrom_bb_bss_cbw40_dig = 0x400023d4;\nrom_cbw2040_cfg = 0x400023d8;\nrom_mac_tx_chan_offset = 0x400023dc;\nrom_tx_paon_set = 0x400023e0;\nrom_i2cmst_reg_init = 0x400023e4;\nrom_bt_gain_offset = 0x400023e8;\nrom_fe_reg_init = 0x400023ec;\nrom_mac_enable_bb = 0x400023f0;\nrom_bb_wdg_cfg = 0x400023f4;\nrom_fe_txrx_reset = 0x400023f8;\nrom_set_rx_comp = 0x400023fc;\nrom_write_chan_freq = 0x40002400;\nrom_agc_reg_init = 0x40002404;\nrom_bb_reg_init = 0x40002408;\nrom_write_txrate_power_offset = 0x4000240c;\nrom_open_i2c_xpd = 0x40002410;\nrom_txiq_set_reg = 0x40002414;\nrom_rxiq_set_reg = 0x40002418;\nrom_phy_bbpll_cal = 0x4000241c;\nphy_disable_cca = 0x40002420;\nphy_enable_cca = 0x40002424;\nforce_txon = 0x40002428;\nset_txclk_en = 0x4000242c;\nset_rxclk_en = 0x40002430;\nstart_tx_tone_step = 0x40002434;\nstop_tx_tone = 0x40002438;\nbb_wdg_test_en = 0x4000243c;\nnoise_floor_auto_set = 0x40002440;\nread_hw_noisefloor = 0x40002444;\niq_corr_enable = 0x40002448;\nbt_tx_dig_gain = 0x4000244c;\nwifi_tx_dig_reg = 0x40002450;\nwifi_agc_sat_gain = 0x40002454;\nphy_ant_init = 0x40002458;\nphy_set_bbfreq_init = 0x4000245c;\nwifi_fbw_sel = 0x40002460;\nphy_rx_sense_set = 0x40002464;\ntx_state_set = 0x40002468;\nphy_close_pa = 0x4000246c;\nbt_filter_reg = 0x40002470;\nphy_freq_correct = 0x40002474;\nset_pbus_reg = 0x40002478;\nwifi_rifs_mode_en = 0x4000247c;\nrfagc_disable = 0x40002480;\nrom_restart_cal = 0x40002484;\nrom_write_rfpll_sdm = 0x40002488;\nrom_wait_rfpll_cal_end = 0x4000248c;\nrom_rfpll_set_freq = 0x40002490;\nrom_rfpll_cap_init_cal = 0x40002494;\nrom_set_rfpll_freq = 0x40002498;\nrom_write_pll_cap = 0x4000249c;\nrom_read_pll_cap = 0x400024a0;\nmhz2ieee = 0x400024a4;\nchan_to_freq = 0x400024a8;\nset_rf_freq_offset = 0x400024ac;\nset_channel_rfpll_freq = 0x400024b0;\nrfpll_cap_correct = 0x400024b4;\nphy_set_freq = 0x400024b8;\ncorrect_rfpll_offset = 0x400024bc;\npll_vol_cal = 0x400024c0;\nchip_v7_set_chan_misc = 0x400024c4;\nchip_v7_set_chan = 0x400024c8;\nchip_v7_set_chan_offset = 0x400024cc;\nchip_v7_set_chan_ana = 0x400024d0;\nset_chanfreq = 0x400024d4;\nrom_rxiq_cover_mg_mp = 0x400024d8;\nrom_rfcal_rxiq = 0x400024dc;\nrom_get_rfcal_rxiq_data = 0x400024e0;\nrom_pbus_rx_dco_cal = 0x400024e4;\nrom_rxdc_est_min = 0x400024e8;\nrom_pbus_rx_dco_cal_1step = 0x400024ec;\nrom_set_lb_txiq = 0x400024f0;\nrom_set_rx_gain_cal_iq = 0x400024f4;\nrom_set_rx_gain_cal_dc = 0x400024f8;\niq_est_enable = 0x400024fc;\niq_est_disable = 0x40002500;\ndc_iq_est = 0x40002504;\nset_cal_rxdc = 0x40002508;\nrxiq_get_mis = 0x4000250c;\nspur_reg_write_one_tone = 0x40002510;\nspur_cal = 0x40002514;\nspur_coef_cfg = 0x40002518;\ngen_rx_gain_table = 0x4000251c;\nwr_rx_gain_mem = 0x40002520;\nset_rx_gain_param = 0x40002524;\nset_rx_gain_table = 0x40002528;\nrom_tester_wifi_cali = 0x4000252c;\nesp_recover_efuse_data = 0x40002530;\nbt_track_pll_cap = 0x40002534;\nrfpll_cap_track = 0x40002538;\nphy_param_track = 0x4000253c;\ntxpwr_correct = 0x40002540;\ntxpwr_cal_track = 0x40002544;\n\/* tx_pwctrl_background = 0x40002548;*\/\nbt_track_tx_power = 0x4000254c;\nwifi_track_tx_power = 0x40002550;\nrom_code_to_temp = 0x40002554;\nrom_tsens_index_to_dac = 0x40002558;\nrom_tsens_index_to_offset = 0x4000255c;\nrom_tsens_dac_cal = 0x40002560;\nrom_tsens_code_read = 0x40002564;\nrom_tsens_temp_read = 0x40002568;\nrom_temp_to_power = 0x4000256c;\ntsens_read_init = 0x40002570;\nget_temp_init = 0x40002574;\nrom_txiq_cover = 0x40002578;\nrom_rfcal_txiq = 0x4000257c;\nrom_get_power_atten = 0x40002580;\nrom_tx_pwctrl_init_cal = 0x40002584;\nbt_txdc_cal = 0x40002588;\nbt_txiq_cal = 0x4000258c;\ntxiq_cal_init = 0x40002590;\ntxdc_cal_init = 0x40002594;\ntxdc_cal_v70 = 0x40002598;\ntxiq_get_mis_pwr = 0x4000259c;\npwdet_ref_code = 0x400025a0;\npwdet_code_cal = 0x400025a4;\nrfcal_txcap = 0x400025a8;\ntx_cap_init = 0x400025ac;\nrfcal_pwrctrl = 0x400025b0;\ntx_pwctrl_init = 0x400025b4;\nbt_tx_pwctrl_init = 0x400025b8;\nbt_txpwr_freq = 0x400025bc;\nrom_txbbgain_to_index = 0x400025c0;\nrom_index_to_txbbgain = 0x400025c4;\nrom_bt_index_to_bb = 0x400025c8;\nrom_bt_bb_to_index = 0x400025cc;\nrom_bt_get_tx_gain = 0x400025d0;\nrom_get_tx_gain_value = 0x400025d4;\nrom_wifi_get_tx_gain = 0x400025d8;\nrom_set_tx_gain_mem = 0x400025dc;\nrom_get_rate_fcc_index = 0x400025e0;\nrom_get_chan_target_power = 0x400025e4;\nrom_wifi_tx_dig_gain = 0x400025e8;\nrom_wifi_set_tx_gain = 0x400025ec;\nrom_bt_set_tx_gain = 0x400025f0;\nwifi_11g_rate_chg = 0x400025f4;\nbt_chan_pwr_interp = 0x400025f8;\nbt_tx_gain_init = 0x400025fc;\n\/* Data (.data, .bss, .rodata) *\/\nphy_param_rom = 0x3fcdfaa4;\n\n\n\/***************************************\n Group rom_btbb\n ***************************************\/\n\n\/* Functions *\/\nbt_agc_gain_offset = 0x40002600;\nbt_agc_gain_max = 0x40002604;\nbt_set_rx_comp = 0x40002608;\nbt_agc_gain_set = 0x4000260c;\nbt_agc_rssi_thresh = 0x40002610;\nbt_agc_target_set = 0x40002614;\nbt_agc_restart_set = 0x40002618;\nbt_agc_recorrect_set = 0x4000261c;\nbt_agc_detect_set = 0x40002620;\nbt_bb_rx_correlator_set = 0x40002624;\nbt_bb_rx_dpo_set = 0x40002628;\nbt_bb_rx_filter_sel = 0x4000262c;\nbt_bb_rx_set1 = 0x40002630;\nbt_bb_v2_rx_set = 0x40002634;\nbt_bb_v2_tx_set = 0x40002638;\nbt_bb_tx_cca_set = 0x4000263c;\nbt_bb_tx_cca_period = 0x40002640;\nbt_bb_tx_cca_fifo_reset = 0x40002644;\nbt_bb_tx_cca_fifo_empty = 0x40002648;\nbt_bb_tx_cca_fifo_full = 0x4000264c;\nbt_bb_tx_cca_fifo_count = 0x40002650;\nbt_bb_tx_cca_fifo_read = 0x40002654;\ncoex_pti_v2 = 0x40002658;\nbt_bb_set_le_tx_on_delay = 0x4000265c;\nbt_bb_set_corr_thresh_le = 0x40002660;\n","old_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\nrtc_get_wakeup_cause = 0x40000020;\nrtc_select_apb_bridge = 0x40000024;\nrtc_unhold_all_pads = 0x40000028;\nets_is_print_boot = 0x4000002c;\nets_vprintf = 0x40000030;\nets_printf = 0x40000034;\nets_install_putc1 = 0x40000038;\nets_install_uart_printf = 0x4000003c;\nets_install_putc2 = 0x40000040;\nets_delay_us = 0x40000044;\nets_get_stack_info = 0x40000048;\nets_install_lock = 0x4000004c;\nUartRxString = 0x40000050;\nUartGetCmdLn = 0x40000054;\nuart_tx_one_char = 0x40000058;\nuart_tx_one_char2 = 0x4000005c;\nuart_rx_one_char = 0x40000060;\nuart_rx_one_char_block = 0x40000064;\nuart_rx_readbuff = 0x40000068;\nuartAttach = 0x4000006c;\nuart_tx_flush = 0x40000070;\nuart_tx_wait_idle = 0x40000074;\nuart_div_modify = 0x40000078;\nets_write_char_uart = 0x4000007c;\nuart_tx_switch = 0x40000080;\nmultofup = 0x40000084;\nsoftware_reset = 0x40000088;\nsoftware_reset_cpu = 0x4000008c;\nassist_debug_clock_enable = 0x40000090;\nassist_debug_record_enable = 0x40000094;\nclear_super_wdt_reset_flag = 0x40000098;\ndisable_default_watchdog = 0x4000009c;\nsend_packet = 0x400000a0;\nrecv_packet = 0x400000a4;\nGetUartDevice = 0x400000a8;\nUartDwnLdProc = 0x400000ac;\nGetSecurityInfoProc = 0x400000b0;\nUart_Init = 0x400000b4;\nets_set_user_start = 0x400000b8;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff4fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000bc;\nmz_free = 0x400000c0;\ntdefl_compress = 0x400000c4;\ntdefl_compress_buffer = 0x400000c8;\ntdefl_compress_mem_to_heap = 0x400000cc;\ntdefl_compress_mem_to_mem = 0x400000d0;\ntdefl_compress_mem_to_output = 0x400000d4;\ntdefl_get_adler32 = 0x400000d8;\ntdefl_get_prev_return_status = 0x400000dc;\ntdefl_init = 0x400000e0;\ntdefl_write_image_to_png_file_in_memory = 0x400000e4;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000e8;\ntinfl_decompress = 0x400000ec;\ntinfl_decompress_mem_to_callback = 0x400000f0;\ntinfl_decompress_mem_to_heap = 0x400000f4;\ntinfl_decompress_mem_to_mem = 0x400000f8;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 );\nPROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 );\nPROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 );\nPROVIDE( _esp_rom_spiflash_write = 0x4000011c );\nPROVIDE( _esp_rom_spiflash_read = 0x40000120 );\nPROVIDE( _esp_rom_spiflash_unlock = 0x40000124 );\nPROVIDE( _SPIEraseArea = 0x40000128 );\nPROVIDE( _SPI_write_enable = 0x4000012c );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000134 );\nPROVIDE( esp_rom_spiflash_write = 0x40000138 );\nPROVIDE( esp_rom_spiflash_read = 0x4000013c );\nPROVIDE( esp_rom_spiflash_unlock = 0x40000140 );\nPROVIDE( SPIEraseArea = 0x40000144 );\nPROVIDE( SPI_write_enable = 0x40000148 );\nPROVIDE( esp_rom_spiflash_config_param = 0x4000014c );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c );\nPROVIDE( esp_rom_spi_flash_update_id = 0x40000160 );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000164 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 );\nPROVIDE( esp_rom_spiflash_read_status = 0x4000016c );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000174 );\nPROVIDE( spi_flash_attach = 0x40000178 );\nPROVIDE( spi_flash_get_chip_size = 0x4000017c );\nPROVIDE( spi_flash_guard_set = 0x40000180 );\nPROVIDE( spi_flash_guard_get = 0x40000184 );\nPROVIDE( spi_flash_read_encrypted = 0x40000188 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x4000018c );\nPROVIDE( spi_flash_mmap_page_num_init = 0x40000190 );\nPROVIDE( spi_flash_mmap = 0x40000194 );\nPROVIDE( spi_flash_mmap_pages = 0x40000198 );\nPROVIDE( spi_flash_munmap = 0x4000019c );\nPROVIDE( spi_flash_mmap_dump = 0x400001a0 );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );\nPROVIDE( spi_flash_cache2phys = 0x400001ac );\nPROVIDE( spi_flash_phys2cache = 0x400001b0 );\nPROVIDE( spi_flash_disable_cache = 0x400001b4 );\nPROVIDE( spi_flash_restore_cache = 0x400001b8 );\nPROVIDE( spi_flash_cache_enabled = 0x400001bc );\nPROVIDE( spi_flash_enable_cache = 0x400001c0 );\nPROVIDE( spi_cache_mode_switch = 0x400001c4 );\nPROVIDE( spi_common_set_dummy_output = 0x400001c8 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001cc );\nPROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 );\nPROVIDE( SPILock = 0x400001d8 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001dc );\nPROVIDE( SPI_Common_Command = 0x400001e0 );\nPROVIDE( SPI_WakeUp = 0x400001e4 );\nPROVIDE( SPI_block_erase = 0x400001e8 );\nPROVIDE( SPI_chip_erase = 0x400001ec );\nPROVIDE( SPI_init = 0x400001f0 );\nPROVIDE( SPI_page_program = 0x400001f4 );\nPROVIDE( SPI_read_data = 0x400001f8 );\nPROVIDE( SPI_sector_erase = 0x400001fc );\nPROVIDE( SelectSpiFunction = 0x40000200 );\nPROVIDE( SetSpiDrvs = 0x40000204 );\nPROVIDE( Wait_SPI_Idle = 0x40000208 );\nPROVIDE( spi_dummy_len_fix = 0x4000020c );\nPROVIDE( Disable_QMode = 0x40000210 );\nPROVIDE( Enable_QMode = 0x40000214 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group hal_soc\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 );\nPROVIDE( spi_flash_hal_device_config = 0x4000021c );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 );\nPROVIDE( spi_flash_hal_common_command = 0x40000224 );\nPROVIDE( spi_flash_hal_read = 0x40000228 );\nPROVIDE( spi_flash_hal_erase_chip = 0x4000022c );\nPROVIDE( spi_flash_hal_erase_sector = 0x40000230 );\nPROVIDE( spi_flash_hal_erase_block = 0x40000234 );\nPROVIDE( spi_flash_hal_program_page = 0x40000238 );\nPROVIDE( spi_flash_hal_set_write_protect = 0x4000023c );\nPROVIDE( spi_flash_hal_host_idle = 0x40000240 );\nPROVIDE( spi_flash_hal_check_status = 0x40000244 );\nPROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 );\nPROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c );\nPROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 );\nPROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 );\nPROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 );\nPROVIDE( spi_flash_hal_resume = 0x4000025c );\nPROVIDE( spi_flash_hal_suspend = 0x40000260 );\nPROVIDE( spi_flash_encryption_hal_enable = 0x40000264 );\nPROVIDE( spi_flash_encryption_hal_disable = 0x40000268 );\nPROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c );\nPROVIDE( spi_flash_encryption_hal_done = 0x40000270 );\nPROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 );\nPROVIDE( spi_flash_encryption_hal_check = 0x40000278 );\nPROVIDE( wdt_hal_init = 0x4000027c );\nPROVIDE( wdt_hal_deinit = 0x40000280 );\nPROVIDE( wdt_hal_config_stage = 0x40000284 );\nPROVIDE( wdt_hal_write_protect_disable = 0x40000288 );\nPROVIDE( wdt_hal_write_protect_enable = 0x4000028c );\nPROVIDE( wdt_hal_enable = 0x40000290 );\nPROVIDE( wdt_hal_disable = 0x40000294 );\nPROVIDE( wdt_hal_handle_intr = 0x40000298 );\nPROVIDE( wdt_hal_feed = 0x4000029c );\nPROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 );\nPROVIDE( wdt_hal_is_enabled = 0x400002a4 );\nPROVIDE( systimer_hal_get_counter_value = 0x400002ac );\nPROVIDE( systimer_hal_get_alarm_value = 0x400002bc );\nPROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 );\nPROVIDE( systimer_hal_enable_counter = 0x400002cc );\nPROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 );\nPROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 );\nPROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 );\n\n\/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c *\/\n\/* PROVIDE( systimer_hal_init = 0x400002a8 ); *\/\n\/* PROVIDE( systimer_hal_get_time = 0x400002b0 ); *\/\n\/* PROVIDE( systimer_hal_set_alarm_target = 0x400002b4 ); *\/\n\/* PROVIDE( systimer_hal_set_alarm_period = 0x400002b8 ); *\/\n\/* PROVIDE( systimer_hal_counter_value_advance = 0x400002c8 ); *\/\n\n\n\/***************************************\n Group heap\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( tlsf_create = 0x400002dc );\nPROVIDE( tlsf_create_with_pool = 0x400002e0 );\nPROVIDE( tlsf_get_pool = 0x400002e4 );\nPROVIDE( tlsf_add_pool = 0x400002e8 );\nPROVIDE( tlsf_remove_pool = 0x400002ec );\nPROVIDE( tlsf_malloc = 0x400002f0 );\nPROVIDE( tlsf_memalign = 0x400002f4 );\nPROVIDE( tlsf_memalign_offs = 0x400002f8 );\nPROVIDE( tlsf_realloc = 0x400002fc );\nPROVIDE( tlsf_free = 0x40000300 );\nPROVIDE( tlsf_block_size = 0x40000304 );\nPROVIDE( tlsf_size = 0x40000308 );\nPROVIDE( tlsf_align_size = 0x4000030c );\nPROVIDE( tlsf_block_size_min = 0x40000310 );\nPROVIDE( tlsf_block_size_max = 0x40000314 );\nPROVIDE( tlsf_pool_overhead = 0x40000318 );\nPROVIDE( tlsf_alloc_overhead = 0x4000031c );\nPROVIDE( tlsf_walk_pool = 0x40000320 );\nPROVIDE( tlsf_check = 0x40000324 );\nPROVIDE( tlsf_check_pool = 0x40000328 );\nPROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c );\nPROVIDE( multi_heap_get_block_address_impl = 0x40000330 );\nPROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 );\nPROVIDE( multi_heap_register_impl = 0x40000338 );\nPROVIDE( multi_heap_set_lock = 0x4000033c );\nPROVIDE( multi_heap_os_funcs_init = 0x40000340 );\nPROVIDE( multi_heap_internal_lock = 0x40000344 );\nPROVIDE( multi_heap_internal_unlock = 0x40000348 );\nPROVIDE( multi_heap_get_first_block = 0x4000034c );\nPROVIDE( multi_heap_get_next_block = 0x40000350 );\nPROVIDE( multi_heap_is_free = 0x40000354 );\nPROVIDE( multi_heap_malloc_impl = 0x40000358 );\nPROVIDE( multi_heap_free_impl = 0x4000035c );\nPROVIDE( multi_heap_realloc_impl = 0x40000360 );\nPROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 );\nPROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 );\nPROVIDE( multi_heap_check = 0x4000036c );\nPROVIDE( multi_heap_dump = 0x40000370 );\nPROVIDE( multi_heap_free_size_impl = 0x40000374 );\nPROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 );\nPROVIDE( multi_heap_get_info_impl = 0x4000037c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x40000380 );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 );\nPROVIDE( spi_flash_chip_generic_write = 0x40000388 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000398 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 );\nPROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 );\nPROVIDE( spi_flash_chip_generic_yield = 0x400003b8 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 );\nPROVIDE( spi_flash_chip_generic_read = 0x400003c8 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc );\nPROVIDE( spi_flash_common_set_io_mode = 0x400003e0 );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 );\nPROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 );\nPROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec );\nPROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400003f8 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );\nPROVIDE( spi_flash_encryption = 0x3fcdffe4 );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x40000400 );\nPROVIDE( memspi_host_read_status_hs = 0x40000404 );\nPROVIDE( memspi_host_flush_cache = 0x40000408 );\nPROVIDE( memspi_host_erase_chip = 0x4000040c );\nPROVIDE( memspi_host_erase_sector = 0x40000410 );\nPROVIDE( memspi_host_erase_block = 0x40000414 );\nPROVIDE( memspi_host_program_page = 0x40000418 );\nPROVIDE( memspi_host_read = 0x4000041c );\nPROVIDE( memspi_host_set_write_protect = 0x40000420 );\nPROVIDE( memspi_host_set_max_read_len = 0x40000424 );\nPROVIDE( memspi_host_read_data_slicer = 0x40000428 );\nPROVIDE( memspi_host_write_data_slicer = 0x4000042c );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x40000430 );\nPROVIDE( esp_flash_read_id = 0x40000434 );\nPROVIDE( esp_flash_get_size = 0x40000438 );\nPROVIDE( esp_flash_erase_chip = 0x4000043c );\nPROVIDE( esp_flash_erase_region = 0x40000440 );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000444 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000448 );\nPROVIDE( esp_flash_get_protectable_regions = 0x4000044c );\nPROVIDE( esp_flash_get_protected_region = 0x40000450 );\nPROVIDE( esp_flash_set_protected_region = 0x40000454 );\nPROVIDE( esp_flash_read = 0x40000458 );\nPROVIDE( esp_flash_write = 0x4000045c );\nPROVIDE( esp_flash_write_encrypted = 0x40000460 );\nPROVIDE( esp_flash_read_encrypted = 0x40000464 );\nPROVIDE( esp_flash_get_io_mode = 0x40000468 );\nPROVIDE( esp_flash_set_io_mode = 0x4000046c );\nPROVIDE( spi_flash_boot_attach = 0x40000470 );\nPROVIDE( esp_flash_read_chip_id = 0x40000474 );\nPROVIDE( detect_spi_flash_chip = 0x40000478 );\nPROVIDE( esp_rom_spiflash_write_disable = 0x4000047c );\nPROVIDE( esp_flash_suspend_cmd_init = 0x40000480 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe0 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffdc );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 );\nPROVIDE( Cache_Get_Mode = 0x400006e4 );\nPROVIDE( Cache_Address_Through_IBus = 0x400006e8 );\nPROVIDE( Cache_Address_Through_DBus = 0x400006ec );\nPROVIDE( Cache_Set_Default_Mode = 0x400006f0 );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400006f8 );\nPROVIDE( MMU_Set_Page_Mode = 0x400006fc );\nPROVIDE( MMU_Get_Page_Mode = 0x40000700 );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x40000704 );\nPROVIDE( Cache_Op_Addr = 0x40000708 );\nPROVIDE( Cache_Invalidate_Addr = 0x4000070c );\nPROVIDE( Cache_Invalidate_ICache_All = 0x40000710 );\nPROVIDE( Cache_Mask_All = 0x40000714 );\nPROVIDE( Cache_UnMask_Dram0 = 0x40000718 );\nPROVIDE( Cache_Disable_ICache = 0x4000071c );\nPROVIDE( Cache_Enable_ICache = 0x40000720 );\nPROVIDE( Cache_Suspend_ICache = 0x40000724 );\nPROVIDE( Cache_Resume_ICache = 0x40000728 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x4000072c );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x40000730 );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000734 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x40000738 );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x4000073c );\nPROVIDE( Cache_Owner_Init = 0x40000740 );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000744 );\nPROVIDE( Cache_MMU_Init = 0x40000748 );\nPROVIDE( Cache_Ibus_MMU_Set = 0x4000074c );\nPROVIDE( Cache_Dbus_MMU_Set = 0x40000750 );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000754 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x40000758 );\nPROVIDE( Cache_Get_Virtual_Addr = 0x4000075c );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x40000760 );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000764 );\nPROVIDE( Cache_Get_Memory_value = 0x40000768 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd0 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x4000076c;\nets_get_cpu_frequency = 0x40000770;\nets_update_cpu_frequency = 0x40000774;\nets_get_printf_channel = 0x40000778;\nets_get_xtal_div = 0x4000077c;\nets_set_xtal_div = 0x40000780;\nets_get_xtal_freq = 0x40000784;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x40000788;\ngpio_matrix_in = 0x4000078c;\ngpio_matrix_out = 0x40000790;\ngpio_output_disable = 0x40000794;\ngpio_output_enable = 0x40000798;\ngpio_output_set = 0x4000079c;\ngpio_pad_hold = 0x400007a0;\ngpio_pad_input_disable = 0x400007a4;\ngpio_pad_input_enable = 0x400007a8;\ngpio_pad_pulldown = 0x400007ac;\ngpio_pad_pullup = 0x400007b0;\ngpio_pad_select_gpio = 0x400007b4;\ngpio_pad_set_drv = 0x400007b8;\ngpio_pad_unhold = 0x400007bc;\ngpio_pin_wakeup_disable = 0x400007c0;\ngpio_pin_wakeup_enable = 0x400007c4;\ngpio_bypass_matrix_in = 0x400007c8;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400007cc;\nesprv_intc_int_set_threshold = 0x400007d0;\nesprv_intc_int_enable = 0x400007d4;\nesprv_intc_int_disable = 0x400007d8;\nesprv_intc_int_set_type = 0x400007dc;\nPROVIDE( intr_handler_set = 0x400007e0 );\nintr_matrix_set = 0x400007e4;\nets_intr_lock = 0x400007e8;\nets_intr_unlock = 0x400007ec;\nets_isr_attach = 0x400007f0;\nets_isr_mask = 0x400007f4;\nets_isr_unmask = 0x400007f8;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\ncrc32_le = 0x400007fc;\ncrc16_le = 0x40000800;\ncrc8_le = 0x40000804;\ncrc32_be = 0x40000808;\ncrc16_be = 0x4000080c;\ncrc8_be = 0x40000810;\nesp_crc8 = 0x40000814;\nets_sha_enable = 0x40000818;\nets_sha_disable = 0x4000081c;\nets_sha_get_state = 0x40000820;\nets_sha_init = 0x40000824;\nets_sha_process = 0x40000828;\nets_sha_starts = 0x4000082c;\nets_sha_update = 0x40000830;\nets_sha_finish = 0x40000834;\nets_sha_clone = 0x40000838;\n\/* Data (.data, .bss, .rodata) *\/\ncrc32_le_table_ptr = 0x3ff4fff8;\ncrc16_le_table_ptr = 0x3ff4fff4;\ncrc8_le_table_ptr = 0x3ff4fff0;\ncrc32_be_table_ptr = 0x3ff4ffec;\ncrc16_be_table_ptr = 0x3ff4ffe8;\ncrc8_be_table_ptr = 0x3ff4ffe4;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x4000083c;\nets_efuse_program = 0x40000840;\nets_efuse_clear_program_registers = 0x40000844;\nets_efuse_write_key = 0x40000848;\nets_efuse_get_read_register_address = 0x4000084c;\nets_efuse_get_key_purpose = 0x40000850;\nets_efuse_key_block_unused = 0x40000854;\nets_efuse_find_unused_key_block = 0x40000858;\nets_efuse_rs_calculate = 0x4000085c;\nets_efuse_count_unused_key_blocks = 0x40000860;\nets_efuse_secure_boot_enabled = 0x40000864;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000868;\nets_efuse_cache_encryption_enabled = 0x4000086c;\nets_efuse_download_modes_disabled = 0x40000870;\nets_efuse_find_purpose = 0x40000874;\nets_efuse_force_send_resume = 0x40000878;\nets_efuse_get_flash_delay_us = 0x4000087c;\nets_efuse_get_mac = 0x40000880;\nets_efuse_get_uart_print_control = 0x40000884;\nets_efuse_direct_boot_mode_disabled = 0x40000888;\nets_efuse_security_download_modes_enabled = 0x4000088c;\nets_efuse_set_timing = 0x40000890;\nets_efuse_jtag_disabled = 0x40000894;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_ecdsa_verify = 0x40000898;\nets_secure_boot_verify_bootloader_with_keys = 0x4000089c;\nets_secure_boot_verify_signature = 0x400008a0;\nets_secure_boot_read_key_digests = 0x400008a4;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Data (.data, .bss, .rodata) *\/\ng_uart_print = 0x3fcdffc9;\ng_usb_print = 0x3fcdffc8;\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nble_controller_rom_data_init = 0x40000aa8;\nble_osi_coex_funcs_register = 0x40000aac;\nbt_rf_coex_cfg_get_default = 0x40000ab0;\nbt_rf_coex_dft_pti_get_default = 0x40000ab4;\nbt_rf_coex_hooks_p_set = 0x40000ab8;\nr__os_mbuf_copypkthdr = 0x40000abc;\nr__os_msys_find_pool = 0x40000ac0;\nr_ble_controller_get_rom_compile_version = 0x40000ac4;\nr_ble_hci_ram_hs_acl_tx = 0x40000ac8;\nr_ble_hci_ram_hs_cmd_tx = 0x40000acc;\nr_ble_hci_ram_ll_acl_tx = 0x40000ad0;\nr_ble_hci_ram_ll_evt_tx = 0x40000ad4;\nr_ble_hci_ram_reset = 0x40000ad8;\nr_ble_hci_ram_set_acl_free_cb = 0x40000adc;\nr_ble_hci_trans_acl_buf_alloc = 0x40000ae0;\nr_ble_hci_trans_buf_alloc = 0x40000ae4;\nr_ble_hci_trans_buf_free = 0x40000ae8;\nr_ble_hci_trans_cfg_hs = 0x40000aec;\nr_ble_hci_trans_cfg_ll = 0x40000af0;\nr_ble_hci_trans_deinit = 0x40000af4;\nr_ble_hci_trans_env_init = 0x40000af8;\nr_ble_hci_trans_init = 0x40000afc;\nr_ble_hci_uart_acl_tx = 0x40000b00;\nr_ble_hci_uart_cmdevt_tx = 0x40000b04;\nr_ble_hci_uart_config = 0x40000b08;\nr_ble_hci_uart_free_pkt = 0x40000b0c;\nr_ble_hci_uart_hs_acl_tx = 0x40000b10;\nr_ble_hci_uart_hs_cmd_tx = 0x40000b14;\nr_ble_hci_uart_ll_acl_tx = 0x40000b18;\nr_ble_hci_uart_ll_evt_tx = 0x40000b1c;\nr_ble_hci_uart_rx_acl = 0x40000b20;\nr_ble_hci_uart_rx_char = 0x40000b24;\nr_ble_hci_uart_rx_cmd = 0x40000b28;\nr_ble_hci_uart_rx_evt = 0x40000b2c;\nr_ble_hci_uart_rx_evt_cb = 0x40000b30;\nr_ble_hci_uart_rx_le_evt = 0x40000b34;\nr_ble_hci_uart_rx_pkt_type = 0x40000b38;\nr_ble_hci_uart_rx_skip_acl = 0x40000b3c;\nr_ble_hci_uart_rx_skip_cmd = 0x40000b40;\nr_ble_hci_uart_rx_skip_evt = 0x40000b44;\nr_ble_hci_uart_rx_sync_loss = 0x40000b48;\nr_ble_hci_uart_set_acl_free_cb = 0x40000b4c;\nr_ble_hci_uart_sync_lost = 0x40000b50;\nr_ble_hci_uart_trans_reset = 0x40000b54;\nr_ble_hci_uart_tx_char = 0x40000b58;\nr_ble_hci_uart_tx_pkt_type = 0x40000b5c;\nr_ble_hw_driver_deinit = 0x40000b60;\nr_ble_hw_driver_env_init = 0x40000b64;\nr_ble_hw_encrypt_block = 0x40000b68;\nr_ble_hw_get_public_addr = 0x40000b6c;\nr_ble_hw_get_static_addr = 0x40000b70;\nr_ble_hw_periodiclist_add = 0x40000b74;\nr_ble_hw_periodiclist_clear = 0x40000b78;\nr_ble_hw_periodiclist_rmv = 0x40000b7c;\nr_ble_hw_resolv_list_cur_entry = 0x40000b80;\nr_ble_hw_resolv_list_set = 0x40000b88;\nr_ble_hw_rng_init = 0x40000b8c;\nr_ble_hw_rng_start = 0x40000b90;\nr_ble_hw_rng_stop = 0x40000b94;\nr_ble_hw_rx_local_is_resolved = 0x40000b98;\nr_ble_hw_rx_local_is_rpa = 0x40000b9c;\nr_ble_hw_whitelist_add = 0x40000ba0;\nr_ble_hw_whitelist_clear = 0x40000ba4;\nr_ble_hw_whitelist_dev_num = 0x40000ba8;\nr_ble_hw_whitelist_get_base = 0x40000bac;\nr_ble_hw_whitelist_rmv = 0x40000bb0;\nr_ble_hw_whitelist_search = 0x40000bb4;\nr_ble_hw_whitelist_sort = 0x40000bb8;\nr_ble_ll_acl_data_in = 0x40000bbc;\nr_ble_ll_addr_is_id = 0x40000bc0;\nr_ble_ll_addr_subtype = 0x40000bc4;\nr_ble_ll_adv_active_chanset_clear = 0x40000bc8;\nr_ble_ll_adv_active_chanset_is_pri = 0x40000bcc;\nr_ble_ll_adv_active_chanset_is_sec = 0x40000bd0;\nr_ble_ll_adv_active_chanset_set_pri = 0x40000bd4;\nr_ble_ll_adv_active_chanset_set_sec = 0x40000bd8;\nr_ble_ll_adv_aux_calculate = 0x40000bdc;\nr_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000be0;\nr_ble_ll_adv_aux_pdu_make = 0x40000be4;\nr_ble_ll_adv_aux_scannable_pdu_make = 0x40000be8;\nr_ble_ll_adv_aux_txed = 0x40000bec;\nr_ble_ll_adv_can_chg_whitelist = 0x40000bf0;\nr_ble_ll_adv_chk_rpa_timeout = 0x40000bf4;\nr_ble_ll_adv_clear_all = 0x40000bf8;\nr_ble_ll_adv_conn_req_rxd = 0x40000bfc;\nr_ble_ll_adv_deinit = 0x40000c00;\nr_ble_ll_adv_enabled = 0x40000c04;\nr_ble_ll_adv_ext_set_adv_data = 0x40000c0c;\nr_ble_ll_adv_ext_set_scan_rsp = 0x40000c18;\nr_ble_ll_adv_final_chan = 0x40000c1c;\nr_ble_ll_adv_first_chan = 0x40000c20;\nr_ble_ll_adv_flags_clear = 0x40000c24;\nr_ble_ll_adv_flags_set = 0x40000c28;\nr_ble_ll_adv_get_chan_num = 0x40000c2c;\nr_ble_ll_adv_get_local_rpa = 0x40000c30;\nr_ble_ll_adv_get_peer_rpa = 0x40000c34;\nr_ble_ll_adv_hci_set_random_addr = 0x40000c38;\nr_ble_ll_adv_init = 0x40000c3c;\nr_ble_ll_adv_legacy_pdu_make = 0x40000c40;\nr_ble_ll_adv_next_chan = 0x40000c44;\nr_ble_ll_adv_pdu_make = 0x40000c48;\nr_ble_ll_adv_periodic_check_data_itvl = 0x40000c4c;\nr_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c54;\nr_ble_ll_adv_periodic_send_sync_ind = 0x40000c58;\nr_ble_ll_adv_periodic_set_info_transfer = 0x40000c60;\nr_ble_ll_adv_periodic_set_param = 0x40000c64;\nr_ble_ll_adv_pre_process = 0x40000c68;\nr_ble_ll_adv_put_acad_chM_update_ind = 0x40000c6c;\nr_ble_ll_adv_put_aux_ptr = 0x40000c70;\nr_ble_ll_adv_put_syncinfo = 0x40000c74;\nr_ble_ll_adv_rd_max_adv_data_len = 0x40000c78;\nr_ble_ll_adv_rd_sup_adv_sets = 0x40000c7c;\nr_ble_ll_adv_read_txpwr = 0x40000c80;\nr_ble_ll_adv_rpa_timeout = 0x40000c8c;\nr_ble_ll_adv_rpa_update = 0x40000c90;\nr_ble_ll_adv_scan_req_rxd = 0x40000c98;\nr_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c;\nr_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0;\nr_ble_ll_adv_scheduled = 0x40000ca4;\nr_ble_ll_adv_send_conn_comp_ev = 0x40000ca8;\nr_ble_ll_adv_set_adv_params = 0x40000cb0;\nr_ble_ll_adv_set_enable = 0x40000cb4;\nr_ble_ll_adv_set_random_addr = 0x40000cb8;\nr_ble_ll_adv_sm_deinit = 0x40000cc4;\nr_ble_ll_adv_sm_event_init = 0x40000cc8;\nr_ble_ll_adv_sm_find_configured = 0x40000ccc;\nr_ble_ll_adv_sm_get = 0x40000cd0;\nr_ble_ll_adv_sm_reset = 0x40000cd8;\nr_ble_ll_adv_sm_start = 0x40000cdc;\nr_ble_ll_adv_sm_start_periodic = 0x40000ce0;\nr_ble_ll_adv_sm_stop = 0x40000ce4;\nr_ble_ll_adv_sm_stop_limit_reached = 0x40000ce8;\nr_ble_ll_adv_sm_stop_periodic = 0x40000cec;\nr_ble_ll_adv_sm_stop_timeout = 0x40000cf0;\nr_ble_ll_adv_sync_get_pdu_len = 0x40000cf8;\nr_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d00;\nr_ble_ll_adv_update_data_mbuf = 0x40000d04;\nr_ble_ll_adv_update_did = 0x40000d08;\nr_ble_ll_adv_update_periodic_data = 0x40000d0c;\nr_ble_ll_arr_pool_init = 0x40000d10;\nr_ble_ll_auth_pyld_tmo_event_send = 0x40000d14;\nr_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d18;\nr_ble_ll_calc_session_key = 0x40000d1c;\nr_ble_ll_calc_ticks_per_slot = 0x40000d20;\nr_ble_ll_check_scan_params = 0x40000d24;\nr_ble_ll_chk_txrx_octets = 0x40000d28;\nr_ble_ll_chk_txrx_time = 0x40000d2c;\nr_ble_ll_conn_adjust_pyld_len = 0x40000d30;\nr_ble_ll_conn_auth_pyld_timer_cb = 0x40000d34;\nr_ble_ll_conn_auth_pyld_timer_start = 0x40000d38;\nr_ble_ll_conn_calc_dci = 0x40000d3c;\nr_ble_ll_conn_calc_dci_csa1 = 0x40000d40;\nr_ble_ll_conn_calc_itvl_ticks = 0x40000d44;\nr_ble_ll_conn_chk_csm_flags = 0x40000d48;\nr_ble_ll_conn_chk_phy_upd_start = 0x40000d4c;\nr_ble_ll_conn_comp_event_send = 0x40000d50;\nr_ble_ll_conn_connect_ind_pdu_make = 0x40000d54;\nr_ble_ll_conn_create_cancel = 0x40000d5c;\nr_ble_ll_conn_cth_flow_enable = 0x40000d64;\nr_ble_ll_conn_cth_flow_error_fn = 0x40000d68;\nr_ble_ll_conn_cth_flow_have_credit = 0x40000d6c;\nr_ble_ll_conn_cth_flow_is_enabled = 0x40000d70;\nr_ble_ll_conn_cth_flow_process_cmd = 0x40000d74;\nr_ble_ll_conn_cth_flow_set_buffers = 0x40000d78;\nr_ble_ll_conn_ext_master_init = 0x40000d84;\nr_ble_ll_conn_find_active_conn = 0x40000d88;\nr_ble_ll_conn_get_active_conn = 0x40000d8c;\nr_ble_ll_conn_get_anchor = 0x40000d90;\nr_ble_ll_conn_hcc_params_set_fallback = 0x40000d94;\nr_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000d98;\nr_ble_ll_conn_hci_chk_conn_params = 0x40000d9c;\nr_ble_ll_conn_hci_chk_scan_params = 0x40000da0;\nr_ble_ll_conn_hci_disconnect_cmd = 0x40000da4;\nr_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000da8;\nr_ble_ll_conn_hci_le_ltk_reply = 0x40000dac;\nr_ble_ll_conn_hci_le_rd_phy = 0x40000db0;\nr_ble_ll_conn_hci_le_set_phy = 0x40000db4;\nr_ble_ll_conn_hci_le_start_encrypt = 0x40000db8;\nr_ble_ll_conn_hci_param_nrr = 0x40000dbc;\nr_ble_ll_conn_hci_param_rr = 0x40000dc0;\nr_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000dc4;\nr_ble_ll_conn_hci_rd_chan_map = 0x40000dc8;\nr_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000dcc;\nr_ble_ll_conn_hci_rd_rssi = 0x40000dd0;\nr_ble_ll_conn_hci_read_rem_features = 0x40000dd4;\nr_ble_ll_conn_hci_set_data_len = 0x40000ddc;\nr_ble_ll_conn_hci_update = 0x40000de0;\nr_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000de4;\nr_ble_ll_conn_init_phy = 0x40000de8;\nr_ble_ll_conn_is_empty_pdu = 0x40000df0;\nr_ble_ll_conn_is_lru = 0x40000df4;\nr_ble_ll_conn_master_init = 0x40000df8;\nr_ble_ll_conn_module_reset = 0x40000e04;\nr_ble_ll_conn_next_event = 0x40000e08;\nr_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c;\nr_ble_ll_conn_process_conn_params = 0x40000e14;\nr_ble_ll_conn_req_peer_sca = 0x40000e18;\nr_ble_ll_conn_rx_data_pdu = 0x40000e1c;\nr_ble_ll_conn_set_csa = 0x40000e20;\nr_ble_ll_conn_set_ext_con_params = 0x40000e24;\nr_ble_ll_conn_set_global_chanmap = 0x40000e28;\nr_ble_ll_conn_set_phy = 0x40000e2c;\nr_ble_ll_conn_set_txpwr_by_handle = 0x40000e30;\nr_ble_ll_conn_set_unknown_rx_octets = 0x40000e34;\nr_ble_ll_conn_sm_get = 0x40000e3c;\nr_ble_ll_conn_tx_pkt_in = 0x40000e4c;\nr_ble_ll_conn_update_eff_data_len = 0x40000e50;\nr_ble_ll_ctrl_chanmap_req_make = 0x40000e54;\nr_ble_ll_ctrl_conn_param_pdu_make = 0x40000e5c;\nr_ble_ll_ctrl_conn_param_pdu_proc = 0x40000e60;\nr_ble_ll_ctrl_conn_param_reply = 0x40000e64;\nr_ble_ll_ctrl_datalen_upd_make = 0x40000e6c;\nr_ble_ll_ctrl_enc_allowed_pdu = 0x40000e70;\nr_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000e74;\nr_ble_ll_ctrl_enc_req_make = 0x40000e7c;\nr_ble_ll_ctrl_find_new_phy = 0x40000e80;\nr_ble_ll_ctrl_initiate_dle = 0x40000e84;\nr_ble_ll_ctrl_len_proc = 0x40000e88;\nr_ble_ll_ctrl_min_used_chan_rsp = 0x40000e8c;\nr_ble_ll_ctrl_phy_from_phy_mask = 0x40000e90;\nr_ble_ll_ctrl_phy_req_rsp_make = 0x40000e94;\nr_ble_ll_ctrl_phy_tx_transition_get = 0x40000e98;\nr_ble_ll_ctrl_phy_update_cancel = 0x40000e9c;\nr_ble_ll_ctrl_phy_update_ind_make = 0x40000ea0;\nr_ble_ll_ctrl_phy_update_proc_complete = 0x40000ea4;\nr_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000eac;\nr_ble_ll_ctrl_proc_stop = 0x40000eb4;\nr_ble_ll_ctrl_proc_with_instant_initiated = 0x40000ebc;\nr_ble_ll_ctrl_rej_ext_ind_make = 0x40000ec0;\nr_ble_ll_ctrl_reject_ind_send = 0x40000ec4;\nr_ble_ll_ctrl_rx_chanmap_req = 0x40000ec8;\nr_ble_ll_ctrl_rx_conn_param_req = 0x40000ecc;\nr_ble_ll_ctrl_rx_conn_param_rsp = 0x40000ed0;\nr_ble_ll_ctrl_rx_conn_update = 0x40000ed4;\nr_ble_ll_ctrl_rx_enc_req = 0x40000ed8;\nr_ble_ll_ctrl_rx_enc_rsp = 0x40000edc;\nr_ble_ll_ctrl_rx_feature_req = 0x40000ee0;\nr_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8;\nr_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec;\nr_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4;\nr_ble_ll_ctrl_rx_phy_req = 0x40000ef8;\nr_ble_ll_ctrl_rx_phy_rsp = 0x40000efc;\nr_ble_ll_ctrl_rx_phy_update_ind = 0x40000f00;\nr_ble_ll_ctrl_rx_ping_rsp = 0x40000f04;\nr_ble_ll_ctrl_rx_reject_ind = 0x40000f08;\nr_ble_ll_ctrl_rx_sca_req = 0x40000f0c;\nr_ble_ll_ctrl_rx_sca_rsp = 0x40000f10;\nr_ble_ll_ctrl_rx_start_enc_req = 0x40000f14;\nr_ble_ll_ctrl_rx_start_enc_rsp = 0x40000f18;\nr_ble_ll_ctrl_rx_version_ind = 0x40000f1c;\nr_ble_ll_ctrl_sca_req_rsp_make = 0x40000f20;\nr_ble_ll_ctrl_start_enc_send = 0x40000f24;\nr_ble_ll_ctrl_start_rsp_timer = 0x40000f28;\nr_ble_ll_ctrl_terminate_start = 0x40000f2c;\nr_ble_ll_ctrl_update_features = 0x40000f34;\nr_ble_ll_ctrl_version_ind_make = 0x40000f38;\nr_ble_ll_data_buffer_overflow = 0x40000f3c;\nr_ble_ll_deinit = 0x40000f40;\nr_ble_ll_disconn_comp_event_send = 0x40000f44;\nr_ble_ll_event_comp_pkts = 0x40000f4c;\nr_ble_ll_event_dbuf_overflow = 0x40000f50;\nr_ble_ll_event_send = 0x40000f54;\nr_ble_ll_event_tx_pkt = 0x40000f58;\nr_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40000f5c;\nr_ble_ll_ext_conn_create = 0x40000f60;\nr_ble_ll_ext_scan_parse_adv_info = 0x40000f64;\nr_ble_ll_ext_scan_parse_aux_ptr = 0x40000f68;\nr_ble_ll_flush_pkt_queue = 0x40000f6c;\nr_ble_ll_generate_dh_key_v1 = 0x40000f70;\nr_ble_ll_generate_dh_key_v2 = 0x40000f74;\nr_ble_ll_generic_data_init = 0x40000f78;\nr_ble_ll_get_addr_type = 0x40000f7c;\nr_ble_ll_get_chan_to_scan = 0x40000f80;\nr_ble_ll_get_our_devaddr = 0x40000f84;\nr_ble_ll_get_tx_pwr_compensation = 0x40000f88;\nr_ble_ll_hci_acl_rx = 0x40000f8c;\nr_ble_ll_hci_adv_mode_ext = 0x40000f90;\nr_ble_ll_hci_adv_set_enable = 0x40000f94;\nr_ble_ll_hci_cb_host_buf_size = 0x40000f98;\nr_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x40000f9c;\nr_ble_ll_hci_cb_set_event_mask = 0x40000fa0;\nr_ble_ll_hci_cb_set_event_mask2 = 0x40000fa4;\nr_ble_ll_hci_chk_phy_masks = 0x40000fa8;\nr_ble_ll_hci_cmd_proc = 0x40000fac;\nr_ble_ll_hci_cmd_rx = 0x40000fb0;\nr_ble_ll_hci_ctlr_bb_cmd_proc = 0x40000fb4;\nr_ble_ll_hci_deinit = 0x40000fb8;\nr_ble_ll_hci_disconnect = 0x40000fbc;\nr_ble_ll_hci_env_init = 0x40000fc0;\nr_ble_ll_hci_ev_conn_update = 0x40000fc4;\nr_ble_ll_hci_ev_databuf_overflow = 0x40000fc8;\nr_ble_ll_hci_ev_datalen_chg = 0x40000fcc;\nr_ble_ll_hci_ev_encrypt_chg = 0x40000fd0;\nr_ble_ll_hci_ev_hw_err = 0x40000fd4;\nr_ble_ll_hci_ev_le_csa = 0x40000fd8;\nr_ble_ll_hci_ev_ltk_req = 0x40000fdc;\nr_ble_ll_hci_ev_phy_update = 0x40000fe0;\nr_ble_ll_hci_ev_rd_rem_used_feat = 0x40000fe4;\nr_ble_ll_hci_ev_rd_rem_ver = 0x40000fe8;\nr_ble_ll_hci_ev_rem_conn_parm_req = 0x40000fec;\nr_ble_ll_hci_ev_sca_update = 0x40000ff0;\nr_ble_ll_hci_ev_send_adv_set_terminated = 0x40000ff4;\nr_ble_ll_hci_ev_send_scan_req_recv = 0x40000ff8;\nr_ble_ll_hci_ev_send_scan_timeout = 0x40000ffc;\nr_ble_ll_hci_ev_send_vendor_err = 0x40001000;\nr_ble_ll_hci_event_send = 0x40001004;\nr_ble_ll_hci_ext_scan_set_enable = 0x40001008;\nr_ble_ll_hci_get_num_cmd_pkts = 0x4000100c;\nr_ble_ll_hci_info_params_cmd_proc = 0x40001010;\nr_ble_ll_hci_init = 0x40001014;\nr_ble_ll_hci_init_support_cmd_base_on_lmp_ver = 0x40001018;\nr_ble_ll_hci_is_event_enabled = 0x4000101c;\nr_ble_ll_hci_is_le_event_enabled = 0x40001020;\nr_ble_ll_hci_le_cmd_send_cmd_status = 0x40001028;\nr_ble_ll_hci_le_encrypt = 0x4000102c;\nr_ble_ll_hci_le_rand = 0x40001030;\nr_ble_ll_hci_le_rd_max_data_len = 0x40001034;\nr_ble_ll_hci_le_rd_sugg_data_len = 0x40001038;\nr_ble_ll_hci_le_read_bufsize = 0x4000103c;\nr_ble_ll_hci_le_read_supp_states = 0x40001044;\nr_ble_ll_hci_le_set_def_phy = 0x40001048;\nr_ble_ll_hci_le_wr_sugg_data_len = 0x4000104c;\nr_ble_ll_hci_link_ctrl_cmd_proc = 0x40001050;\nr_ble_ll_hci_npl_init = 0x40001054;\nr_ble_ll_hci_post_gen_dhkey_cmp_evt = 0x40001058;\nr_ble_ll_hci_post_rd_p256_pubkey_cmp_evt = 0x4000105c;\nr_ble_ll_hci_rd_bd_addr = 0x40001060;\nr_ble_ll_hci_rd_local_supp_cmd = 0x40001064;\nr_ble_ll_hci_rd_local_supp_feat = 0x40001068;\nr_ble_ll_hci_rd_local_version = 0x4000106c;\nr_ble_ll_hci_scan_set_enable = 0x40001070;\nr_ble_ll_hci_send_adv_report = 0x40001074;\nr_ble_ll_hci_send_dir_adv_report = 0x40001078;\nr_ble_ll_hci_send_ext_adv_report = 0x4000107c;\nr_ble_ll_hci_send_legacy_ext_adv_report = 0x40001080;\nr_ble_ll_hci_send_noop = 0x40001084;\nr_ble_ll_hci_set_adv_data = 0x40001088;\nr_ble_ll_hci_set_le_event_mask = 0x4000108c;\nr_ble_ll_hci_set_scan_rsp_data = 0x40001090;\nr_ble_ll_hci_status_params_cmd_proc = 0x40001094;\nr_ble_ll_hci_vs_cmd_proc = 0x40001098;\nr_ble_ll_hci_vs_rd_static_addr = 0x4000109c;\nr_ble_ll_hw_err_timer_cb = 0x400010a0;\nr_ble_ll_hw_error = 0x400010a4;\nr_ble_ll_init_alloc_conn_comp_ev = 0x400010ac;\nr_ble_ll_init_get_conn_comp_ev = 0x400010b0;\nr_ble_ll_is_addr_empty = 0x400010b8;\nr_ble_ll_is_controller_busy = 0x400010bc;\nr_ble_ll_is_on_resolv_list = 0x400010c0;\nr_ble_ll_is_our_devaddr = 0x400010c4;\nr_ble_ll_is_rpa = 0x400010c8;\nr_ble_ll_is_valid_adv_mode = 0x400010cc;\nr_ble_ll_is_valid_own_addr_type = 0x400010d0;\nr_ble_ll_is_valid_public_addr = 0x400010d4;\nr_ble_ll_is_valid_random_addr = 0x400010d8;\nr_ble_ll_misc_options_set = 0x400010e0;\nr_ble_ll_modify_sca = 0x400010e4;\nr_ble_ll_modify_sca_action = 0x400010e8;\nr_ble_ll_pdu_max_tx_octets_get = 0x400010ec;\nr_ble_ll_pdu_tx_time_get = 0x400010f0;\nr_ble_ll_phy_to_phy_mode = 0x400010f4;\nr_ble_ll_qa_enable = 0x400010f8;\nr_ble_ll_rand = 0x400010fc;\nr_ble_ll_rand_data_get = 0x40001100;\nr_ble_ll_rand_deinit = 0x40001104;\nr_ble_ll_rand_env_init = 0x40001108;\nr_ble_ll_rand_init = 0x4000110c;\nr_ble_ll_rand_prand_get = 0x40001110;\nr_ble_ll_rand_sample = 0x40001114;\nr_ble_ll_rand_start = 0x40001118;\nr_ble_ll_read_local_p256_pub_key = 0x4000111c;\nr_ble_ll_read_rf_path_compensation = 0x40001120;\nr_ble_ll_read_supp_features = 0x40001124;\nr_ble_ll_read_supp_states = 0x40001128;\nr_ble_ll_reset = 0x40001130;\nr_ble_ll_resolv_clear_all_pl_bit = 0x40001134;\nr_ble_ll_resolv_clear_all_wl_bit = 0x40001138;\nr_ble_ll_resolv_deinit = 0x4000113c;\nr_ble_ll_resolv_enable_cmd = 0x40001140;\nr_ble_ll_resolv_enabled = 0x40001144;\nr_ble_ll_resolv_env_init = 0x40001148;\nr_ble_ll_resolv_gen_rpa = 0x40001150;\nr_ble_ll_resolv_get_addr_pointer = 0x40001154;\nr_ble_ll_resolv_get_index = 0x40001158;\nr_ble_ll_resolv_get_irk_pointer = 0x4000115c;\nr_ble_ll_resolv_get_list = 0x40001160;\nr_ble_ll_resolv_get_priv_addr = 0x40001164;\nr_ble_ll_resolv_get_rpa_tmo = 0x40001168;\nr_ble_ll_resolv_init = 0x4000116c;\nr_ble_ll_resolv_irk_nonzero = 0x40001170;\nr_ble_ll_resolv_list_add = 0x40001174;\nr_ble_ll_resolv_list_chg_allowed = 0x40001178;\nr_ble_ll_resolv_list_clr = 0x4000117c;\nr_ble_ll_resolv_list_find = 0x40001180;\nr_ble_ll_resolv_list_read_size = 0x40001184;\nr_ble_ll_resolv_list_reset = 0x40001188;\nr_ble_ll_resolv_list_rmv = 0x4000118c;\nr_ble_ll_resolv_local_addr_rd = 0x40001190;\nr_ble_ll_resolv_peer_addr_rd = 0x40001194;\nr_ble_ll_resolv_peer_rpa_any = 0x40001198;\nr_ble_ll_resolv_reset = 0x4000119c;\nr_ble_ll_resolv_rpa = 0x400011a0;\nr_ble_ll_resolv_rpa_timer_cb = 0x400011a4;\nr_ble_ll_resolv_set_local_rpa = 0x400011a8;\nr_ble_ll_resolv_set_peer_rpa = 0x400011ac;\nr_ble_ll_resolv_set_rpa_tmo = 0x400011b0;\nr_ble_ll_resolve_set_priv_mode = 0x400011b4;\nr_ble_ll_rxpdu_alloc = 0x400011b8;\nr_ble_ll_scan_add_scan_rsp_adv = 0x400011bc;\nr_ble_ll_scan_adv_decode_addr = 0x400011c0;\nr_ble_ll_scan_aux_data_ref = 0x400011c4;\nr_ble_ll_scan_aux_data_unref = 0x400011c8;\nr_ble_ll_scan_can_chg_whitelist = 0x400011cc;\nr_ble_ll_scan_check_periodic_sync = 0x400011d0;\nr_ble_ll_scan_classify_filter_aux_init = 0x400011d4;\nr_ble_ll_scan_classify_filter_init = 0x400011d8;\nr_ble_ll_scan_common_init = 0x400011dc;\nr_ble_ll_scan_continue_en = 0x400011e0;\nr_ble_ll_scan_dup_check_ext = 0x400011e8;\nr_ble_ll_scan_dup_check_legacy = 0x400011ec;\nr_ble_ll_scan_dup_move_to_head = 0x400011f0;\nr_ble_ll_scan_dup_new = 0x400011f4;\nr_ble_ll_scan_dup_update_ext = 0x400011f8;\nr_ble_ll_scan_dup_update_legacy = 0x400011fc;\nr_ble_ll_scan_enabled = 0x40001200;\nr_ble_ll_scan_end_adv_evt = 0x40001204;\nr_ble_ll_scan_ext_initiator_start = 0x4000120c;\nr_ble_ll_scan_get_addr_data_from_legacy = 0x40001210;\nr_ble_ll_scan_get_addr_from_ext_adv = 0x40001214;\nr_ble_ll_scan_get_cur_sm = 0x40001218;\nr_ble_ll_scan_get_ext_adv_report = 0x4000121c;\nr_ble_ll_scan_get_local_rpa = 0x40001220;\nr_ble_ll_scan_get_next_adv_prim_chan = 0x40001224;\nr_ble_ll_scan_get_peer_rpa = 0x40001228;\nr_ble_ll_scan_have_rxd_scan_rsp = 0x4000122c;\nr_ble_ll_scan_init = 0x40001230;\nr_ble_ll_scan_initiator_start = 0x40001234;\nr_ble_ll_scan_is_inside_window = 0x40001238;\nr_ble_ll_scan_move_window_to = 0x4000123c;\nr_ble_ll_scan_npl_reset = 0x40001240;\nr_ble_ll_scan_parse_auxptr = 0x40001244;\nr_ble_ll_scan_parse_ext_hdr = 0x40001248;\nr_ble_ll_scan_record_new_adv = 0x40001250;\nr_ble_ll_scan_refresh_nrpa = 0x40001254;\nr_ble_ll_scan_reset = 0x40001258;\nr_ble_ll_scan_rx_pkt_in = 0x4000125c;\nr_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268;\nr_ble_ll_scan_rxed = 0x4000126c;\nr_ble_ll_scan_send_adv_report = 0x40001270;\nr_ble_ll_scan_send_truncated = 0x40001274;\nr_ble_ll_scan_set_peer_rpa = 0x4000127c;\nr_ble_ll_scan_set_perfer_addr = 0x40001280;\nr_ble_ll_scan_sm_start = 0x40001288;\nr_ble_ll_scan_sm_stop = 0x4000128c;\nr_ble_ll_scan_time_hci_to_ticks = 0x40001290;\nr_ble_ll_scan_update_aux_data = 0x40001294;\nr_ble_ll_scan_whitelist_enabled = 0x40001298;\nr_ble_ll_set_default_privacy_mode = 0x4000129c;\nr_ble_ll_set_default_sync_transfer_params = 0x400012a0;\nr_ble_ll_set_public_addr = 0x400012ac;\nr_ble_ll_set_random_addr = 0x400012b0;\nr_ble_ll_set_sync_transfer_params = 0x400012b4;\nr_ble_ll_state_get = 0x400012b8;\nr_ble_ll_state_set = 0x400012bc;\nr_ble_ll_sync_adjust_ext_hdr = 0x400012c0;\nr_ble_ll_sync_cancel = 0x400012c4;\nr_ble_ll_sync_cancel_complete_event = 0x400012c8;\nr_ble_ll_sync_check_acad = 0x400012cc;\nr_ble_ll_sync_check_failed = 0x400012d0;\nr_ble_ll_sync_deinit = 0x400012d8;\nr_ble_ll_sync_enabled = 0x400012dc;\nr_ble_ll_sync_env_init = 0x400012e0;\nr_ble_ll_sync_established = 0x400012ec;\nr_ble_ll_sync_filter_enabled = 0x400012f0;\nr_ble_ll_sync_find = 0x400012f4;\nr_ble_ll_sync_get_cur_sm = 0x400012f8;\nr_ble_ll_sync_get_handle = 0x400012fc;\nr_ble_ll_sync_get_sm = 0x40001300;\nr_ble_ll_sync_info_event = 0x40001304;\nr_ble_ll_sync_init = 0x40001308;\nr_ble_ll_sync_list_add = 0x4000130c;\nr_ble_ll_sync_list_clear = 0x40001310;\nr_ble_ll_sync_list_empty = 0x40001314;\nr_ble_ll_sync_list_get_free = 0x40001318;\nr_ble_ll_sync_list_remove = 0x4000131c;\nr_ble_ll_sync_list_search = 0x40001320;\nr_ble_ll_sync_list_size = 0x40001324;\nr_ble_ll_sync_lost_event = 0x40001328;\nr_ble_ll_sync_next_event = 0x4000132c;\nr_ble_ll_sync_on_list = 0x40001330;\nr_ble_ll_sync_periodic_ind = 0x40001338;\nr_ble_ll_sync_phy_mode_to_aux_phy = 0x4000133c;\nr_ble_ll_sync_phy_mode_to_hci = 0x40001340;\nr_ble_ll_sync_reserve = 0x4000134c;\nr_ble_ll_sync_reset = 0x40001350;\nr_ble_ll_sync_reset_sm = 0x40001354;\nr_ble_ll_sync_send_per_adv_rpt = 0x4000135c;\nr_ble_ll_sync_send_sync_ind = 0x40001360;\nr_ble_ll_sync_send_truncated_per_adv_rpt = 0x40001364;\nr_ble_ll_sync_sm_clear = 0x40001368;\nr_ble_ll_sync_terminate = 0x4000136c;\nr_ble_ll_sync_transfer = 0x40001370;\nr_ble_ll_sync_transfer_get = 0x40001374;\nr_ble_ll_sync_transfer_received = 0x40001378;\nr_ble_ll_task = 0x4000137c;\nr_ble_ll_trace_set_func = 0x40001380;\nr_ble_ll_trace_u32 = 0x40001384;\nr_ble_ll_trace_u32x2 = 0x40001388;\nr_ble_ll_trace_u32x3 = 0x4000138c;\nr_ble_ll_tx_flat_mbuf_pducb = 0x40001390;\nr_ble_ll_tx_pkt_in = 0x40001398;\nr_ble_ll_update_max_tx_octets_phy_mode = 0x4000139c;\nr_ble_ll_usecs_to_ticks_round_up = 0x400013a0;\nr_ble_ll_utils_calc_access_addr = 0x400013a4;\nr_ble_ll_utils_calc_dci_csa2 = 0x400013a8;\nr_ble_ll_utils_calc_num_used_chans = 0x400013ac;\nr_ble_ll_utils_calc_window_widening = 0x400013b0;\nr_ble_ll_utils_csa2_perm = 0x400013b4;\nr_ble_ll_utils_csa2_prng = 0x400013b8;\nr_ble_ll_utils_remapped_channel = 0x400013bc;\nr_ble_ll_whitelist_add = 0x400013c0;\nr_ble_ll_whitelist_chg_allowed = 0x400013c4;\nr_ble_ll_whitelist_clear = 0x400013c8;\nr_ble_ll_whitelist_read_size = 0x400013cc;\nr_ble_ll_whitelist_rmv = 0x400013d0;\nr_ble_ll_write_rf_path_compensation = 0x400013d8;\nr_ble_lll_adv_aux_schedule = 0x400013e0;\nr_ble_lll_adv_aux_schedule_first = 0x400013e4;\nr_ble_lll_adv_aux_schedule_next = 0x400013e8;\nr_ble_lll_adv_aux_scheduled = 0x400013ec;\nr_ble_lll_adv_aux_set_start_time = 0x400013f0;\nr_ble_lll_adv_coex_dpc_calc_pti_update_itvl = 0x400013f4;\nr_ble_lll_adv_coex_dpc_process_pri = 0x400013f8;\nr_ble_lll_adv_coex_dpc_process_sec = 0x400013fc;\nr_ble_lll_adv_coex_dpc_pti_get = 0x40001400;\nr_ble_lll_adv_coex_dpc_update = 0x40001404;\nr_ble_lll_adv_coex_dpc_update_on_adv_start = 0x40001408;\nr_ble_lll_adv_coex_dpc_update_on_aux_scheduled = 0x4000140c;\nr_ble_lll_adv_coex_dpc_update_on_data_updated = 0x40001410;\nr_ble_lll_adv_coex_dpc_update_on_event_end = 0x40001414;\nr_ble_lll_adv_coex_dpc_update_on_event_scheduled = 0x40001418;\nr_ble_lll_adv_done = 0x4000141c;\nr_ble_lll_adv_drop_event = 0x40001420;\nr_ble_lll_adv_event_done = 0x40001424;\nr_ble_lll_adv_event_rmvd_from_sched = 0x40001428;\nr_ble_lll_adv_ext_estimate_data_itvl = 0x4000142c;\nr_ble_lll_adv_get_sec_pdu_len = 0x40001430;\nr_ble_lll_adv_make_done = 0x40001438;\nr_ble_lll_adv_periodic_done = 0x4000143c;\nr_ble_lll_adv_periodic_event_done = 0x40001440;\nr_ble_lll_adv_periodic_rmvd_from_sched = 0x40001444;\nr_ble_lll_adv_periodic_schedule_first = 0x40001448;\nr_ble_lll_adv_periodic_start = 0x40001450;\nr_ble_lll_adv_periodic_stop = 0x40001454;\nr_ble_lll_adv_pri_schedule_tx_pdu = 0x40001458;\nr_ble_lll_adv_reschedule_event = 0x4000145c;\nr_ble_lll_adv_reschedule_periodic_event = 0x40001460;\nr_ble_lll_adv_sec_done = 0x40001468;\nr_ble_lll_adv_sec_event_done = 0x4000146c;\nr_ble_lll_adv_sec_schedule_next_aux = 0x40001470;\nr_ble_lll_adv_secondary_tx_start_cb = 0x40001474;\nr_ble_lll_adv_sm_deinit = 0x40001478;\nr_ble_lll_adv_sm_event_init = 0x4000147c;\nr_ble_lll_adv_sm_event_restore = 0x40001480;\nr_ble_lll_adv_sm_event_store = 0x40001484;\nr_ble_lll_adv_sm_init = 0x40001488;\nr_ble_lll_adv_sm_reset = 0x4000148c;\nr_ble_lll_adv_start = 0x40001490;\nr_ble_lll_adv_stop = 0x40001494;\nr_ble_lll_adv_sync_next_scheduled = 0x40001498;\nr_ble_lll_adv_sync_schedule = 0x4000149c;\nr_ble_lll_adv_sync_tx_done = 0x400014a0;\nr_ble_lll_adv_sync_tx_end = 0x400014a4;\nr_ble_lll_adv_sync_tx_start_cb = 0x400014a8;\nr_ble_lll_adv_tx_done = 0x400014ac;\nr_ble_lll_adv_tx_start_cb = 0x400014b0;\nr_ble_lll_adv_update_rsp_offset = 0x400014b4;\nr_ble_lll_aux_scan_cb = 0x400014b8;\nr_ble_lll_aux_scan_drop = 0x400014bc;\nr_ble_lll_aux_scan_drop_event_cb = 0x400014c0;\nr_ble_lll_calc_us_convert_tick_unit = 0x400014c4;\nr_ble_lll_conn_append_tx_buffer = 0x400014c8;\nr_ble_lll_conn_can_send_next_pdu = 0x400014cc;\nr_ble_lll_conn_check_opcode_matched = 0x400014d0;\nr_ble_lll_conn_coex_dpc_process = 0x400014d4;\nr_ble_lll_conn_coex_dpc_pti_get = 0x400014d8;\nr_ble_lll_conn_coex_dpc_update = 0x400014dc;\nr_ble_lll_conn_coex_dpc_update_on_event_end = 0x400014e0;\nr_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4;\nr_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8;\nr_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec;\nr_ble_lll_conn_current_sm_over = 0x400014f4;\nr_ble_lll_conn_env_deinit = 0x400014fc;\nr_ble_lll_conn_env_init = 0x40001500;\nr_ble_lll_conn_event_end = 0x40001504;\nr_ble_lll_conn_event_end_timer_cb = 0x40001508;\nr_ble_lll_conn_event_halt = 0x4000150c;\nr_ble_lll_conn_event_is_over = 0x40001510;\nr_ble_lll_conn_event_start_cb = 0x40001514;\nr_ble_lll_conn_free_rx_mbuf = 0x40001518;\nr_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c;\nr_ble_lll_conn_get_ce_end_time = 0x40001520;\nr_ble_lll_conn_get_next_sched_time = 0x40001524;\nr_ble_lll_conn_halt = 0x4000152c;\nr_ble_lll_conn_master_common_init = 0x40001530;\nr_ble_lll_conn_master_new = 0x40001534;\nr_ble_lll_conn_module_deinit = 0x40001538;\nr_ble_lll_conn_module_reset = 0x40001540;\nr_ble_lll_conn_pre_process = 0x40001548;\nr_ble_lll_conn_process_acked_pdu = 0x4000154c;\nr_ble_lll_conn_recv_ack = 0x40001554;\nr_ble_lll_conn_recv_valid_packet = 0x40001558;\nr_ble_lll_conn_reset_pending_sched = 0x4000155c;\nr_ble_lll_conn_rx_pkt_isr = 0x40001560;\nr_ble_lll_conn_sched_next_anchor = 0x40001564;\nr_ble_lll_conn_sched_next_event = 0x40001568;\nr_ble_lll_conn_set_slave_flow_control = 0x4000156c;\nr_ble_lll_conn_sm_new = 0x40001574;\nr_ble_lll_conn_sm_npl_deinit = 0x40001578;\nr_ble_lll_conn_sm_npl_init = 0x4000157c;\nr_ble_lll_conn_superversion_timer_cb = 0x40001580;\nr_ble_lll_conn_timeout = 0x40001584;\nr_ble_lll_conn_update_anchor = 0x40001588;\nr_ble_lll_conn_update_conn_ind_params = 0x4000158c;\nr_ble_lll_conn_update_tx_buffer = 0x40001594;\nr_ble_lll_deinit = 0x40001598;\nr_ble_lll_dtm_calculate_itvl = 0x4000159c;\nr_ble_lll_dtm_ctx_free = 0x400015a0;\nr_ble_lll_dtm_deinit = 0x400015a4;\nr_ble_lll_dtm_end_test = 0x400015a8;\nr_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;\nr_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;\nr_ble_lll_dtm_init = 0x400015b4;\nr_ble_lll_dtm_reset = 0x400015b8;\nr_ble_lll_dtm_rx_create_ctx = 0x400015bc;\nr_ble_lll_dtm_rx_isr_end = 0x400015c0;\nr_ble_lll_dtm_rx_isr_start = 0x400015c4;\nr_ble_lll_dtm_rx_pkt_in = 0x400015c8;\nr_ble_lll_dtm_rx_sched_cb = 0x400015cc;\nr_ble_lll_dtm_rx_start = 0x400015d0;\nr_ble_lll_dtm_rx_test = 0x400015d4;\nr_ble_lll_dtm_set_next = 0x400015d8;\nr_ble_lll_dtm_tx_done = 0x400015e0;\nr_ble_lll_dtm_tx_sched_cb = 0x400015e4;\nr_ble_lll_dtm_tx_test = 0x400015e8;\nr_ble_lll_dtm_wfr_timer_exp = 0x400015ec;\nr_ble_lll_event_rx_pkt = 0x400015f0;\nr_ble_lll_ext_scan_coex_dpc_process = 0x400015f4;\nr_ble_lll_ext_scan_coex_dpc_pti_get = 0x400015f8;\nr_ble_lll_ext_scan_coex_dpc_update = 0x400015fc;\nr_ble_lll_ext_scan_coex_dpc_update_on_start = 0x40001600;\nr_ble_lll_hci_dtm_rx_test = 0x40001604;\nr_ble_lll_hci_dtm_rx_test_v2 = 0x40001608;\nr_ble_lll_hci_dtm_tx_test = 0x4000160c;\nr_ble_lll_hci_dtm_tx_test_ext = 0x40001610;\nr_ble_lll_hci_dtm_tx_test_v2 = 0x40001614;\nr_ble_lll_hci_dtm_tx_test_v2_ext = 0x40001618;\nr_ble_lll_init = 0x4000161c;\nr_ble_lll_init_pre_process = 0x40001620;\nr_ble_lll_per_adv_coex_dpc_calc_pti_update_itvl = 0x40001628;\nr_ble_lll_per_adv_coex_dpc_process = 0x4000162c;\nr_ble_lll_per_adv_coex_dpc_pti_get = 0x40001630;\nr_ble_lll_per_adv_coex_dpc_update = 0x40001634;\nr_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638;\nr_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c;\nr_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640;\nr_ble_lll_reset = 0x40001644;\nr_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;\nr_ble_lll_rfmgmt_deinit = 0x4000164c;\nr_ble_lll_rfmgmt_disable = 0x40001650;\nr_ble_lll_rfmgmt_enable = 0x40001654;\nr_ble_lll_rfmgmt_enable_now = 0x40001658;\nr_ble_lll_rfmgmt_init = 0x4000165c;\nr_ble_lll_rfmgmt_is_enabled = 0x40001660;\nr_ble_lll_rfmgmt_release = 0x40001664;\nr_ble_lll_rfmgmt_release_ev = 0x40001668;\nr_ble_lll_rfmgmt_reset = 0x4000166c;\nr_ble_lll_rfmgmt_scan_changed = 0x40001670;\nr_ble_lll_rfmgmt_sched_changed = 0x40001674;\nr_ble_lll_rfmgmt_set_sleep_cb = 0x40001678;\nr_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c;\nr_ble_lll_rfmgmt_timer_exp = 0x40001680;\nr_ble_lll_rfmgmt_timer_reschedule = 0x40001684;\nr_ble_lll_rx_pdu_in = 0x40001688;\nr_ble_lll_rx_pkt_in = 0x4000168c;\nr_ble_lll_rx_pkt_isr = 0x40001690;\nr_ble_lll_scan_abort_aux_sched = 0x40001694;\nr_ble_lll_scan_aux_data_free = 0x40001698;\nr_ble_lll_scan_chk_resume = 0x4000169c;\nr_ble_lll_scan_clean_cur_aux_data = 0x400016a0;\nr_ble_lll_scan_coex_event_cb = 0x400016a4;\nr_ble_lll_scan_common_init = 0x400016a8;\nr_ble_lll_scan_deinit = 0x400016ac;\nr_ble_lll_scan_duration_period_timers_restart = 0x400016b0;\nr_ble_lll_scan_duration_period_timers_stop = 0x400016b4;\nr_ble_lll_scan_duration_timer_cb = 0x400016b8;\nr_ble_lll_scan_event_proc = 0x400016bc;\nr_ble_lll_scan_ext_adv_init = 0x400016c0;\nr_ble_lll_scan_halt = 0x400016c4;\nr_ble_lll_scan_has_sent_scan_req = 0x400016c8;\nr_ble_lll_scan_init = 0x400016cc;\nr_ble_lll_scan_npl_init = 0x400016d0;\nr_ble_lll_scan_npl_reset = 0x400016d4;\nr_ble_lll_scan_npl_restore = 0x400016d8;\nr_ble_lll_scan_npl_store = 0x400016dc;\nr_ble_lll_scan_period_timer_cb = 0x400016e0;\nr_ble_lll_scan_process_adv_in_isr = 0x400016e4;\nr_ble_lll_scan_req_backoff = 0x400016ec;\nr_ble_lll_scan_restart = 0x400016f0;\nr_ble_lll_scan_sched_next_aux = 0x40001700;\nr_ble_lll_scan_sched_remove = 0x40001704;\nr_ble_lll_scan_start = 0x40001708;\nr_ble_lll_scan_start_rx = 0x4000170c;\nr_ble_lll_scan_stop = 0x40001710;\nr_ble_lll_scan_timer_cb = 0x40001718;\nr_ble_lll_sched_adv_new = 0x4000171c;\nr_ble_lll_sched_adv_resched_pdu = 0x40001720;\nr_ble_lll_sched_adv_reschedule = 0x40001724;\nr_ble_lll_sched_aux_scan = 0x40001728;\nr_ble_lll_sched_conn_overlap = 0x4000172c;\nr_ble_lll_sched_conn_reschedule = 0x40001730;\nr_ble_lll_sched_deinit = 0x40001734;\nr_ble_lll_sched_dtm = 0x40001738;\nr_ble_lll_sched_env_init = 0x4000173c;\nr_ble_lll_sched_execute_item = 0x40001744;\nr_ble_lll_sched_init = 0x40001748;\nr_ble_lll_sched_insert_if_empty = 0x4000174c;\nr_ble_lll_sched_is_overlap = 0x40001750;\nr_ble_lll_sched_master_new = 0x40001754;\nr_ble_lll_sched_next_time = 0x40001758;\nr_ble_lll_sched_overlaps_current = 0x4000175c;\nr_ble_lll_sched_periodic_adv = 0x40001760;\nr_ble_lll_sched_rmv_elem = 0x40001764;\nr_ble_lll_sched_rmv_elem_type = 0x40001768;\nr_ble_lll_sched_run = 0x4000176c;\nr_ble_lll_sched_scan_req_over_aux_ptr = 0x40001770;\nr_ble_lll_sched_slave_new = 0x40001774;\nr_ble_lll_sched_stop = 0x40001778;\nr_ble_lll_sched_sync = 0x4000177c;\nr_ble_lll_sched_sync_overlaps_current = 0x40001780;\nr_ble_lll_sched_sync_reschedule = 0x40001784;\nr_ble_lll_sync_chain_start_cb = 0x40001788;\nr_ble_lll_sync_coex_dpc_process = 0x4000178c;\nr_ble_lll_sync_coex_dpc_pti_get = 0x40001790;\nr_ble_lll_sync_coex_dpc_update = 0x40001794;\nr_ble_lll_sync_current_sm_over = 0x40001798;\nr_ble_lll_sync_deinit = 0x4000179c;\nr_ble_lll_sync_event_end = 0x400017a0;\nr_ble_lll_sync_event_end_cb = 0x400017a4;\nr_ble_lll_sync_get_event_end_time = 0x400017ac;\nr_ble_lll_sync_halt = 0x400017b0;\nr_ble_lll_sync_init = 0x400017b4;\nr_ble_lll_sync_new = 0x400017b8;\nr_ble_lll_sync_reset = 0x400017bc;\nr_ble_lll_sync_reset_sm = 0x400017c0;\nr_ble_lll_sync_rmvd_from_sched = 0x400017c4;\nr_ble_lll_sync_rx_pkt_isr = 0x400017c8;\nr_ble_lll_sync_schedule_chain = 0x400017cc;\nr_ble_lll_sync_stop = 0x400017d0;\nr_ble_lll_sync_trnasfer_sched = 0x400017d4;\nr_ble_phy_access_addr_get = 0x400017d8;\nr_ble_phy_calculate_rxtx_ifs = 0x400017dc;\nr_ble_phy_calculate_rxwindow = 0x400017e0;\nr_ble_phy_calculate_txrx_ifs = 0x400017e4;\nr_ble_phy_check_bb_status = 0x400017e8;\nr_ble_phy_complete_rx_info = 0x400017ec;\nr_ble_phy_config_access_addr = 0x400017f0;\nr_ble_phy_data_make = 0x400017f4;\nr_ble_phy_disable = 0x400017f8;\nr_ble_phy_disable_irq = 0x400017fc;\nr_ble_phy_disable_whitening = 0x40001800;\nr_ble_phy_enable_whitening = 0x40001804;\nr_ble_phy_encrypt_disable = 0x40001808;\nr_ble_phy_env_init = 0x4000180c;\nr_ble_phy_get_current_phy = 0x40001810;\nr_ble_phy_get_packet_counter = 0x40001814;\nr_ble_phy_get_packet_status = 0x40001818;\nr_ble_phy_get_pyld_time_offset = 0x4000181c;\nr_ble_phy_get_rx_phy_mode = 0x40001820;\nr_ble_phy_get_seq_end_st = 0x40001824;\nr_ble_phy_max_data_pdu_pyld = 0x40001830;\nr_ble_phy_mode_config = 0x40001834;\nr_ble_phy_mode_convert = 0x40001838;\nr_ble_phy_mode_write = 0x4000183c;\nr_ble_phy_module_deinit = 0x40001840;\nr_ble_phy_module_init = 0x40001844;\nr_ble_phy_monitor_bb_sync = 0x40001848;\nr_ble_phy_reset_bb_monitor = 0x4000184c;\nr_ble_phy_resolv_list_disable = 0x40001850;\nr_ble_phy_resolv_list_enable = 0x40001854;\nr_ble_phy_restart_sequence = 0x40001858;\nr_ble_phy_rx_set_start_time_forcibly = 0x4000185c;\nr_ble_phy_rxpdu_copy = 0x40001860;\nr_ble_phy_seq_encrypt_enable = 0x40001864;\nr_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001868;\nr_ble_phy_sequence_end_isr = 0x4000186c;\nr_ble_phy_sequence_get_mode = 0x40001870;\nr_ble_phy_sequence_is_running = 0x40001874;\nr_ble_phy_sequence_is_waiting_rsp = 0x40001878;\nr_ble_phy_sequence_single_end = 0x4000187c;\nr_ble_phy_sequence_tx_end_invoke = 0x40001880;\nr_ble_phy_sequence_update_conn_ind_params = 0x40001884;\nr_ble_phy_set_adv_mode = 0x40001888;\nr_ble_phy_set_coex_pti = 0x4000188c;\nr_ble_phy_set_conn_ind_pdu = 0x40001890;\nr_ble_phy_set_conn_mode = 0x40001894;\nr_ble_phy_set_dev_address = 0x40001898;\nr_ble_phy_set_rx_pwr_compensation = 0x4000189c;\nr_ble_phy_set_scan_mode = 0x400018a4;\nr_ble_phy_set_single_packet_rx_sequence = 0x400018ac;\nr_ble_phy_set_single_packet_tx_sequence = 0x400018b0;\nr_ble_phy_set_tx_rx_transition = 0x400018b4;\nr_ble_phy_set_txend_cb = 0x400018b8;\nr_ble_phy_setchan = 0x400018bc;\nr_ble_phy_start_rx_immediately = 0x400018c0;\nr_ble_phy_state_get = 0x400018c4;\nr_ble_phy_timer_config_start_time = 0x400018c8;\nr_ble_phy_timer_start_now = 0x400018cc;\nr_ble_phy_timer_stop = 0x400018d0;\nr_ble_phy_tx_set_start_time = 0x400018d4;\nr_ble_phy_txpwr_set = 0x400018dc;\nr_ble_phy_update_encryption = 0x400018e4;\nr_ble_phy_update_ifs = 0x400018e8;\nr_ble_phy_xcvr_state_get = 0x400018ec;\nr_ble_plf_set_log_level = 0x400018f0;\nr_ble_rtc_wake_up_cpu_init = 0x400018f4;\nr_ble_rtc_wake_up_state_clr = 0x400018f8;\nr_ble_vendor_hci_register = 0x400018fc;\nr_bt_rf_coex_cfg_set = 0x40001900;\nr_bt_rf_coex_coded_txrx_time_upper_lim = 0x40001904;\nr_bt_rf_coex_dft_pti_set = 0x40001908;\nr_bt_rf_coex_hook_deinit = 0x4000190c;\nr_bt_rf_coex_hook_init = 0x40001910;\nr_bt_rf_coex_hook_st_set = 0x40001914;\nr_bt_rf_coex_hooks_p_set_default = 0x40001918;\nr_btdm_disable_adv_delay = 0x4000191c;\nr_btdm_switch_phy_coded = 0x40001920;\nr_esp_wait_disabled = 0x40001924;\nr_get_be16 = 0x40001928;\nr_get_be24 = 0x4000192c;\nr_get_be32 = 0x40001930;\nr_get_be64 = 0x40001934;\nr_get_le16 = 0x40001938;\nr_get_le24 = 0x4000193c;\nr_get_le32 = 0x40001940;\nr_get_le64 = 0x40001944;\nr_get_local_irk_offset = 0x40001948;\nr_get_local_rpa_offset = 0x4000194c;\nr_get_max_skip = 0x40001950;\nr_get_peer_id_offset = 0x40001954;\nr_get_peer_irk_offset = 0x40001958;\nr_get_peer_rpa_offset = 0x4000195c;\nr_hal_rtc_intr_init = 0x40001960;\nr_hal_rtc_irq_handler = 0x40001964;\nr_hal_timer_deinit = 0x40001968;\nr_hal_timer_disable_irq = 0x4000196c;\nr_hal_timer_env_init = 0x40001970;\nr_hal_timer_process = 0x40001978;\nr_hal_timer_read = 0x4000197c;\nr_hal_timer_read_tick = 0x40001980;\nr_hal_timer_set_cb = 0x40001984;\nr_hal_timer_set_exp_tick = 0x40001988;\nr_hal_timer_start = 0x4000198c;\nr_hal_timer_start_at = 0x40001990;\nr_hal_timer_stop = 0x40001994;\nr_hal_timer_task_start = 0x40001998;\nr_ll_assert = 0x4000199c;\nr_mem_init_mbuf_pool = 0x400019a0;\nr_mem_malloc_mbuf_pool = 0x400019a4;\nr_mem_malloc_mbufpkt_pool = 0x400019a8;\nr_mem_malloc_mempool = 0x400019ac;\nr_mem_malloc_mempool_ext = 0x400019b0;\nr_mem_malloc_mempool_gen = 0x400019b4;\nr_mem_pullup_obj = 0x400019b8;\nr_mem_split_frag = 0x400019bc;\nr_os_cputime_get32 = 0x400019c0;\nr_os_cputime_ticks_to_usecs = 0x400019c4;\nr_os_cputime_timer_init = 0x400019c8;\nr_os_cputime_timer_relative = 0x400019cc;\nr_os_cputime_timer_start = 0x400019d0;\nr_os_cputime_timer_stop = 0x400019d4;\nr_os_cputime_usecs_to_ticks = 0x400019d8;\nr_os_mbuf_adj = 0x400019dc;\nr_os_mbuf_append = 0x400019e0;\nr_os_mbuf_appendfrom = 0x400019e4;\nr_os_mbuf_cmpf = 0x400019e8;\nr_os_mbuf_cmpm = 0x400019ec;\nr_os_mbuf_concat = 0x400019f0;\nr_os_mbuf_copydata = 0x400019f4;\nr_os_mbuf_copyinto = 0x400019f8;\nr_os_mbuf_dup = 0x400019fc;\nr_os_mbuf_extend = 0x40001a00;\nr_os_mbuf_free = 0x40001a04;\nr_os_mbuf_free_chain = 0x40001a08;\nr_os_mbuf_get = 0x40001a0c;\nr_os_mbuf_get_pkthdr = 0x40001a10;\nr_os_mbuf_leadingspace = 0x40001a14;\nr_os_mbuf_len = 0x40001a18;\nr_os_mbuf_off = 0x40001a1c;\nr_os_mbuf_pack_chains = 0x40001a20;\nr_os_mbuf_pool_init = 0x40001a24;\nr_os_mbuf_prepend = 0x40001a28;\nr_os_mbuf_prepend_pullup = 0x40001a2c;\nr_os_mbuf_pullup = 0x40001a30;\nr_os_mbuf_trailingspace = 0x40001a34;\nr_os_mbuf_trim_front = 0x40001a38;\nr_os_mbuf_widen = 0x40001a3c;\nr_os_memblock_from = 0x40001a40;\nr_os_memblock_get = 0x40001a44;\nr_os_memblock_put_from_cb = 0x40001a4c;\nr_os_mempool_clear = 0x40001a50;\nr_os_mempool_ext_clear = 0x40001a54;\nr_os_mempool_ext_init = 0x40001a58;\nr_os_mempool_info_get_next = 0x40001a5c;\nr_os_mempool_init = 0x40001a60;\nr_os_mempool_init_internal = 0x40001a64;\nr_os_mempool_is_sane = 0x40001a68;\nr_os_mempool_module_init = 0x40001a6c;\nr_os_mempool_unregister = 0x40001a70;\nr_os_mqueue_get = 0x40001a74;\nr_os_mqueue_init = 0x40001a78;\nr_os_mqueue_put = 0x40001a7c;\nr_os_msys_count = 0x40001a80;\nr_os_msys_get = 0x40001a84;\nr_os_msys_get_pkthdr = 0x40001a88;\nr_os_msys_num_free = 0x40001a8c;\nr_os_msys_register = 0x40001a90;\nr_os_msys_reset = 0x40001a94;\nr_pri_phy_valid = 0x40001a98;\nr_put_be16 = 0x40001a9c;\nr_put_be24 = 0x40001aa0;\nr_put_be32 = 0x40001aa4;\nr_put_be64 = 0x40001aa8;\nr_put_le16 = 0x40001aac;\nr_put_le24 = 0x40001ab0;\nr_put_le32 = 0x40001ab4;\nr_put_le64 = 0x40001ab8;\nr_rtc0_timer_handler = 0x40001abc;\nr_sdkconfig_get_opts = 0x40001ac0;\nr_sdkconfig_set_opts = 0x40001ac4;\nr_sec_phy_valid = 0x40001ac8;\nr_swap_buf = 0x40001acc;\nr_swap_in_place = 0x40001ad0;\n\/* Data (.data, .bss, .rodata) *\/\nble_lll_dtm_module_env_p = 0x3fcdffc4;\ng_ble_lll_dtm_prbs15_data = 0x3ff4fee4;\ng_ble_lll_dtm_prbs9_data = 0x3ff4fde4;\ng_channel_rf_to_index = 0x3ff4fdbc;\ng_ble_lll_rfmgmt_data = 0x3fcdff7c;\ng_ble_sleep_enter_cb = 0x3fcdff78;\ng_ble_sleep_exit_cb = 0x3fcdff74;\nble_lll_sched_env_p = 0x3fcdff70;\nble_ll_env_p = 0x3fcdff6c;\ng_ble_ll_pdu_header_tx_time_ro = 0x3ff4fdb4;\nble_ll_adv_env_p = 0x3fcdff68;\nble_ll_conn_env_p = 0x3fcdff64;\nble_ll_conn_required_phy_mask = 0x3ff4fdb0;\nble_ll_valid_conn_phy_mask = 0x3ff4fdaf;\nble_ll_hci_env_p = 0x3fcdff60;\ng_debug_le_private_key = 0x3ff4fd6c;\ng_ecc_key = 0x3fcdfefc;\nble_ll_rand_env_p = 0x3fcdfef8;\nble_ll_resolv_env_p = 0x3fcdfef4;\ng_ble_ll_resolve_hdr = 0x3fcdfeec;\ng_device_mode_default = 0x3fcdfe68;\nble_ll_scan_classify_filter_aux_check_cb = 0x3fcdfee8;\nble_ll_scan_classify_filter_check_cb = 0x3fcdfee4;\nble_ll_scan_env_p = 0x3fcdfee0;\ng_ble_ll_supp_cmds_ro = 0x3ff4fd3c;\nble_ll_sync_env_p = 0x3fcdfedc;\ng_ble_sca_ppm_tbl_ro = 0x3ff4fd2c;\npriv_config_opts = 0x3fcdfe48;\nble_hci_uart_reset_cmd = 0x3ff4fd28;\nble_hci_trans_env_p = 0x3fcdfed8;\nble_hci_trans_mode = 0x3fcdfe44;\nble_hci_trans_funcs_ptr = 0x3fcdfed4;\nr_ble_lll_stub_funcs_ptr = 0x3fcdfed0;\nr_ble_stub_funcs_ptr = 0x3fcdfecc;\nr_ext_funcs_p = 0x3fcdfec8;\nr_npl_funcs = 0x3fcdfec4;\nble_hw_env_p = 0x3fcdfec0;\nble_phy_module_env_p = 0x3fcdfebc;\ng_ble_phy_chan_freq_ro = 0x3ff4fd00;\ng_ble_phy_mode_pkt_start_off_ro = 0x3ff4fcf8;\ng_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fce8;\ng_ble_phy_t_rxaddrdelay_ro = 0x3ff4fce4;\ng_ble_phy_t_rxenddelay_ro = 0x3ff4fce0;\ng_ble_phy_t_txdelay_ro = 0x3ff4fcdc;\ng_ble_phy_t_txenddelay_ro = 0x3ff4fcd8;\ng_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcc8;\nhal_timer_env_p = 0x3fcdfeb8;\nr_osi_coex_funcs_p = 0x3fcdfeb4;\nbt_rf_coex_hooks = 0x3fcdfeac;\nbt_rf_coex_hooks_p = 0x3fcdfea8;\ncoex_hook_st_group_tab = 0x3ff4fcbc;\ncoex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcb8;\ns_ble_act_count_by_group = 0x3fcdfea4;\ns_ble_coex_st_map = 0x3fcdfe90;\nbt_rf_coex_cfg_cb = 0x3fcdfe74;\nbt_rf_coex_cfg_p = 0x3fcdfe70;\nbt_rf_coex_cfg_rom = 0x3ff4fc9c;\nbt_rf_coex_pti_dft_p = 0x3fcdfe6c;\nbt_rf_coex_pti_dft_rom = 0x3fcdfe04;\nconn_dynamic_pti_param_rom = 0x3ff4fc84;\nconn_phy_coded_max_data_time_param_rom = 0x3ff4fc80;\next_adv_dynamic_pti_param_rom = 0x3ff4fc4c;\next_scan_dynamic_param_rom = 0x3ff4fc14;\nlegacy_adv_dynamic_pti_param_rom = 0x3ff4fbf4;\nper_adv_dynamic_pti_param_rom = 0x3ff4fbd8;\nsync_dynamic_param_rom = 0x3ff4fbc0;\ng_ble_plf_log_level = 0x3fcdfe00;\ng_msys_pool_list = 0x3fcdfdf8;\ng_os_mempool_list = 0x3fcdfdf0;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x40001ad4;\nRC_GetBlockAckTime = 0x40001ad8;\nebuf_list_remove = 0x40001adc;\nesf_buf_alloc = 0x40001ae0;\nesf_buf_alloc_dynamic = 0x40001ae4;\nesf_buf_recycle = 0x40001ae8;\nGetAccess = 0x40001aec;\nhal_mac_is_low_rate_enabled = 0x40001af0;\nhal_mac_tx_get_blockack = 0x40001af4;\nhal_mac_tx_set_ppdu = 0x40001af8;\nic_get_trc = 0x40001afc;\nic_mac_deinit = 0x40001b00;\nic_mac_init = 0x40001b04;\nic_interface_enabled = 0x40001b08;\nis_lmac_idle = 0x40001b0c;\nlmacAdjustTimestamp = 0x40001b10;\nlmacDiscardAgedMSDU = 0x40001b14;\nlmacDiscardMSDU = 0x40001b18;\nlmacEndFrameExchangeSequence = 0x40001b1c;\nlmacIsIdle = 0x40001b20;\nlmacIsLongFrame = 0x40001b24;\nlmacMSDUAged = 0x40001b28;\nlmacPostTxComplete = 0x40001b2c;\nlmacProcessAllTxTimeout = 0x40001b30;\nlmacProcessCollisions = 0x40001b34;\nlmacProcessRxSucData = 0x40001b38;\nlmacReachLongLimit = 0x40001b3c;\nlmacReachShortLimit = 0x40001b40;\nlmacRecycleMPDU = 0x40001b44;\nlmacRxDone = 0x40001b48;\nlmacSetTxFrame = 0x40001b4c;\nlmacTxDone = 0x40001b50;\nlmacTxFrame = 0x40001b54;\nmac_tx_set_duration = 0x40001b58;\nmac_tx_set_htsig = 0x40001b5c;\nmac_tx_set_plcp0 = 0x40001b60;\nmac_tx_set_plcp1 = 0x40001b64;\nmac_tx_set_plcp2 = 0x40001b68;\npm_check_state = 0x40001b6c;\npm_disable_dream_timer = 0x40001b70;\npm_disable_sleep_delay_timer = 0x40001b74;\npm_dream = 0x40001b78;\npm_mac_wakeup = 0x40001b7c;\npm_mac_sleep = 0x40001b80;\npm_enable_active_timer = 0x40001b84;\npm_enable_sleep_delay_timer = 0x40001b88;\npm_local_tsf_process = 0x40001b8c;\npm_set_beacon_filter = 0x40001b90;\npm_is_in_wifi_slice_threshold = 0x40001b94;\npm_is_waked = 0x40001b98;\npm_keep_alive = 0x40001b9c;\npm_on_beacon_rx = 0x40001ba0;\npm_on_data_rx = 0x40001ba4;\npm_on_tbtt = 0x40001ba8;\npm_parse_beacon = 0x40001bac;\npm_process_tim = 0x40001bb0;\n\/*pm_rx_beacon_process = 0x40001bb4;*\/\npm_rx_data_process = 0x40001bb8;\npm_sleep = 0x40001bbc;\npm_sleep_for = 0x40001bc0;\npm_tbtt_process = 0x40001bc4;\nppAMPDU2Normal = 0x40001bc8;\nppAssembleAMPDU = 0x40001bcc;\nppCalFrameTimes = 0x40001bd0;\nppCalSubFrameLength = 0x40001bd4;\nppCalTxAMPDULength = 0x40001bd8;\nppCheckTxAMPDUlength = 0x40001bdc;\nppDequeueRxq_Locked = 0x40001be0;\nppDequeueTxQ = 0x40001be4;\nppEmptyDelimiterLength = 0x40001be8;\nppEnqueueRxq = 0x40001bec;\nppEnqueueTxDone = 0x40001bf0;\nppGetTxQFirstAvail_Locked = 0x40001bf4;\nppGetTxframe = 0x40001bf8;\nppMapTxQueue = 0x40001bfc;\nppProcTxSecFrame = 0x40001c00;\nppProcessRxPktHdr = 0x40001c04;\nppProcessTxQ = 0x40001c08;\nppRecordBarRRC = 0x40001c0c;\nlmacRequestTxopQueue = 0x40001c10;\nlmacReleaseTxopQueue = 0x40001c14;\nppRecycleAmpdu = 0x40001c18;\nppRecycleRxPkt = 0x40001c1c;\nppResortTxAMPDU = 0x40001c20;\nppResumeTxAMPDU = 0x40001c24;\nppRxFragmentProc = 0x40001c28;\nppRxPkt = 0x40001c2c;\nppRxProtoProc = 0x40001c30;\nppSearchTxQueue = 0x40001c34;\nppSearchTxframe = 0x40001c38;\nppSelectNextQueue = 0x40001c3c;\nppSubFromAMPDU = 0x40001c40;\nppTask = 0x40001c44;\nppTxPkt = 0x40001c48;\nppTxProtoProc = 0x40001c4c;\nppTxqUpdateBitmap = 0x40001c50;\npp_coex_tx_request = 0x40001c54;\npp_hdrsize = 0x40001c58;\npp_post = 0x40001c5c;\npp_process_hmac_waiting_txq = 0x40001c60;\nrcGetAmpduSched = 0x40001c64;\nrcUpdateRxDone = 0x40001c68;\nrc_get_trc = 0x40001c6c;\nrc_get_trc_by_index = 0x40001c70;\nrcAmpduLowerRate = 0x40001c74;\nrcampduuprate = 0x40001c78;\nrcClearCurAMPDUSched = 0x40001c7c;\nrcClearCurSched = 0x40001c80;\nrcClearCurStat = 0x40001c84;\nrcGetSched = 0x40001c88;\nrcLowerSched = 0x40001c8c;\nrcSetTxAmpduLimit = 0x40001c90;\nrcTxUpdatePer = 0x40001c94;\nrcUpdateAckSnr = 0x40001c98;\nrcUpdateRate = 0x40001c9c;\nrcUpdateTxDone = 0x40001ca0;\nrcUpdateTxDoneAmpdu2 = 0x40001ca4;\nrcUpSched = 0x40001ca8;\nrssi_margin = 0x40001cac;\nrx11NRate2AMPDULimit = 0x40001cb0;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001cb4;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001cb8;\ntrc_calc_duration = 0x40001cbc;\ntrc_isTxAmpduOperational = 0x40001cc0;\ntrc_onAmpduOp = 0x40001cc4;\nTRC_PER_IS_GOOD = 0x40001cc8;\ntrc_SetTxAmpduState = 0x40001ccc;\ntrc_tid_isTxAmpduOperational = 0x40001cd0;\ntrcAmpduSetState = 0x40001cd4;\nwDevCheckBlockError = 0x40001cd8;\nwDev_AppendRxBlocks = 0x40001cdc;\nwDev_DiscardFrame = 0x40001ce0;\nwDev_GetNoiseFloor = 0x40001ce4;\nwDev_IndicateAmpdu = 0x40001ce8;\nwDev_IndicateFrame = 0x40001cec;\nwdev_mac_reg_load = 0x40001cf0;\nwdev_mac_reg_store = 0x40001cf4;\nwdev_mac_special_reg_load = 0x40001cf8;\nwdev_mac_special_reg_store = 0x40001cfc;\nwdev_mac_wakeup = 0x40001d00;\nwdev_mac_sleep = 0x40001d04;\nwDev_ProcessFiq = 0x40001d08;\nwDev_ProcessRxSucData = 0x40001d0c;\nwdevProcessRxSucDataAll = 0x40001d10;\nwdev_csi_len_align = 0x40001d14;\nppDequeueTxDone_Locked = 0x40001d18;\nppProcTxDone = 0x40001d1c;\n\/*pm_tx_data_done_process = 0x40001d20;*\/\nconfig_is_cache_tx_buf_enabled = 0x40001d24;\nppMapWaitTxq = 0x40001d28;\nppProcessWaitingQueue = 0x40001d2c;\nppDisableQueue = 0x40001d30;\npm_allow_tx = 0x40001d34;\nwdev_is_data_in_rxlist = 0x40001d38;\nppProcTxCallback = 0x40001d3c;\npm_is_open = 0x40001d40;\npm_wake_up = 0x40001d44;\npm_wake_done = 0x40001d48;\npm_disable_disconnected_sleep_delay_timer = 0x40001d4c;\npm_enable_disconnected_sleep_delay_timer = 0x40001d50;\nhal_mac_get_txq_state = 0x40001d54;\nhal_mac_clr_txq_state = 0x40001d58;\nhal_mac_tx_set_cca = 0x40001d5c;\nhal_mac_set_txq_invalid = 0x40001d60;\nhal_mac_txq_disable = 0x40001d64;\nhal_mac_is_txq_enabled = 0x40001d68;\nhal_mac_get_txq_pmd = 0x40001d6c;\nlmacDiscardFrameExchangeSequence = 0x40001d70;\nlmacDisableTransmit = 0x40001d74;\nlmacProcessTxTimeout = 0x40001d78;\nlmacProcessTxSuccess = 0x40001d7c;\nlmacProcessCollision = 0x40001d80;\nlmacProcessTxRtsError = 0x40001d84;\nlmacProcessCtsTimeout = 0x40001d88;\nlmacProcessTxComplete = 0x40001d8c;\nlmacProcessAckTimeout = 0x40001d90;\nlmacProcessTxError = 0x40001d94;\nlmacProcessTxseckiderr = 0x40001d98;\nrcReachRetryLimit = 0x40001d9c;\nlmacProcessShortRetryFail = 0x40001da0;\nlmacEndRetryAMPDUFail = 0x40001da4;\nppFillAMPDUBar = 0x40001da8;\nrcGetRate = 0x40001dac;\nppReSendBar = 0x40001db0;\nlmacProcessLongRetryFail = 0x40001db4;\nlmacRetryTxFrame = 0x40001db8;\nlmacProcessCollisions_task = 0x40001dbc;\nlmacProcessTxopQComplete = 0x40001dc0;\nlmacInitAc = 0x40001dc4;\nlmacInit = 0x40001dc8;\nmac_tx_set_txop_q = 0x40001dcc;\nhal_init = 0x40001dd0;\nhal_mac_rx_set_policy = 0x40001dd4;\nhal_mac_set_bssid = 0x40001dd8;\nmac_rx_policy_init = 0x40001ddc;\n\/*mac_txrx_init = 0x40001de0;*\/\nmac_rxbuf_init = 0x40001de4;\nmac_last_rxbuf_init = 0x40001de8;\nhal_attenna_init = 0x40001dec;\nhal_timer_update_by_rtc = 0x40001df0;\nhal_coex_pti_init = 0x40001df4;\nlmac_stop_hw_txq = 0x40001df8;\nppDirectRecycleAmpdu = 0x40001dfc;\nesp_wifi_internal_set_rts = 0x40001e00;\nesp_wifi_internal_get_rts = 0x40001e04;\nppTxFragmentProc = 0x40001e08;\n\/*esf_buf_setup = 0x40001e0c;*\/\nhal_agreement_add_rx_ba = 0x40001e10;\nhal_agreement_del_rx_ba = 0x40001e14;\nhal_crypto_set_key_entry = 0x40001e18;\nhal_crypto_get_key_entry = 0x40001e1c;\nhal_crypto_clr_key_entry = 0x40001e20;\nconfig_get_wifi_task_stack_size = 0x40001e24;\npp_create_task = 0x40001e28;\nhal_set_sta_tsf_wakeup = 0x40001e2c;\nhal_set_rx_beacon_pti = 0x40001e30;\npm_start = 0x40001e34;\npm_stop = 0x40001e38;\nhal_disable_sta_tbtt = 0x40001e3c;\nppCalTxopDur = 0x40001e40;\nwDev_IndicateCtrlFrame = 0x40001e44;\nhal_enable_sta_tbtt = 0x40001e48;\nhal_set_sta_tbtt = 0x40001e4c;\npm_update_next_tbtt = 0x40001e50;\npm_set_sleep_type = 0x40001e54;\nwDev_Rxbuf_Init = 0x40001e58;\nwDev_Rxbuf_Deinit = 0x40001e5c;\nppCalTkipMic = 0x40001e60;\nwDev_SnifferRxData = 0x40001e64;\nhal_crypto_enable = 0x40001e68;\nhal_crypto_disable = 0x40001e6c;\nwDev_Insert_KeyEntry = 0x40001e70;\nwDev_remove_KeyEntry = 0x40001e74;\nrc_enable_trc = 0x40001e78;\nrc_set_per_conn_fix_rate = 0x40001e7c;\nwdev_csi_rx_process = 0x40001e80;\nwDev_SnifferRxAmpdu = 0x40001e84;\nhal_mac_tsf_reset = 0x40001e88;\ndbg_lmac_statis_dump = 0x40001e8c;\ndbg_lmac_rxtx_statis_dump = 0x40001e90;\ndbg_lmac_hw_statis_dump = 0x40001e94;\ndbg_lmac_diag_statis_dump = 0x40001e98;\ndbg_lmac_ps_statis_dump = 0x40001e9c;\npp_timer_do_process = 0x40001ea0;\nrcUpdateAMPDUParam = 0x40001ea4;\nrcUpdatePhyMode = 0x40001ea8;\nrcGetHighestRateIdx = 0x40001eac;\npm_tx_null_data_done_process = 0x40001eb0;\npm_tx_data_process = 0x40001eb4;\npm_attach = 0x40001eb8;\npm_coex_schm_process = 0x40001ebc;\nppInitTxq = 0x40001ec0;\npp_attach = 0x40001ec4;\npp_deattach = 0x40001ec8;\npm_on_probe_resp_rx = 0x40001ecc;\nhal_set_sta_tsf = 0x40001ed0;\nic_update_sta_tsf = 0x40001ed4;\nic_tx_pkt = 0x40001ed8;\npm_send_probe_stop = 0x40001edc;\npm_send_probe_start = 0x40001ee0;\npm_on_coex_schm_process_restart = 0x40001ee4;\nhal_mac_set_rxq_policy = 0x40001ee8;\nhal_sniffer_enable = 0x40001eec;\nhal_sniffer_disable = 0x40001ef0;\nhal_sniffer_rx_set_promis = 0x40001ef4;\nhal_sniffer_rx_clr_statistics = 0x40001ef8;\nhal_sniffer_set_promis_misc_pkt = 0x40001efc;\ntsf_hal_set_tsf_enable = 0x40001f00;\ntsf_hal_set_tsf_disable = 0x40001f04;\ntsf_hal_is_tsf_enabled = 0x40001f08;\ntsf_hal_set_modem_wakeup_early_time = 0x40001f0c;\ntsf_hal_get_counter_value = 0x40001f10;\ntsf_hal_set_counter_value = 0x40001f14;\ntsf_hal_get_time = 0x40001f18;\ntsf_hal_set_time = 0x40001f1c;\ntsf_hal_set_tbtt_enable = 0x40001f20;\ntsf_hal_set_tbtt_disable = 0x40001f24;\ntsf_hal_set_tbtt_intr_enable = 0x40001f28;\ntsf_hal_set_tbtt_intr_disable = 0x40001f2c;\ntsf_hal_set_tbtt_soc_wakeup_enable = 0x40001f30;\ntsf_hal_set_tbtt_soc_wakeup_disable = 0x40001f34;\ntsf_hal_set_tbtt_start_time = 0x40001f38;\ntsf_hal_set_tbtt_early_time = 0x40001f3c;\ntsf_hal_set_tbtt_interval = 0x40001f40;\ntsf_hal_get_tbtt_interval = 0x40001f44;\ntsf_hal_set_timer_enable = 0x40001f48;\ntsf_hal_set_timer_disable = 0x40001f4c;\ntsf_hal_set_timer_target = 0x40001f50;\ntsf_hal_get_timer_target = 0x40001f54;\ntsf_hal_set_timer_intr_enable = 0x40001f58;\ntsf_hal_set_timer_intr_disable = 0x40001f5c;\ntsf_hal_set_timer_soc_wakeup_enable = 0x40001f60;\ntsf_hal_set_timer_soc_wakeup_disable = 0x40001f64;\npm_disconnected_wake = 0x40001f68;\npm_get_connectionless_status = 0x40001f6c;\npm_update_by_connectionless_status = 0x40001f70;\npm_connectionless_wake_interval_timeout_process = 0x40001f74;\npm_connectionless_wake_window_timeout_process = 0x40001f78;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff4fbbc;\npTxRx = 0x3fcdfdec;\nlmacConfMib_ptr = 0x3fcdfde8;\nour_wait_eb = 0x3fcdfde4;\nour_tx_eb = 0x3fcdfde0;\npp_wdev_funcs = 0x3fcdfddc;\ng_osi_funcs_p = 0x3fcdfdd8;\nwDevCtrl_ptr = 0x3fcdfdd4;\ng_wdev_last_desc_reset_ptr = 0x3ff4fbb8;\nwDevMacSleep_ptr = 0x3fcdfdd0;\ng_lmac_cnt_ptr = 0x3fcdfdcc;\nour_controls_ptr = 0x3ff4fbb4;\npp_sig_cnt_ptr = 0x3fcdfdc8;\ng_eb_list_desc_ptr = 0x3fcdfdc4;\ns_fragment_ptr = 0x3fcdfdc0;\nif_ctrl_ptr = 0x3fcdfdbc;\ng_intr_lock_mux = 0x3fcdfdb8;\ng_wifi_global_lock = 0x3fcdfdb4;\ns_wifi_queue = 0x3fcdfdb0;\npp_task_hdl = 0x3fcdfdac;\ns_pp_task_create_sem = 0x3fcdfda8;\ns_pp_task_del_sem = 0x3fcdfda4;\ng_wifi_menuconfig_ptr = 0x3fcdfda0;\nxphyQueue = 0x3fcdfd9c;\nap_no_lr_ptr = 0x3fcdfd98;\nrc11BSchedTbl_ptr = 0x3fcdfd94;\nrc11NSchedTbl_ptr = 0x3fcdfd90;\nrcLoRaSchedTbl_ptr = 0x3fcdfd8c;\nBasicOFDMSched_ptr = 0x3fcdfd88;\ntrc_ctl_ptr = 0x3fcdfd84;\ng_pm_cnt_ptr = 0x3fcdfd80;\ng_pm_ptr = 0x3fcdfd7c;\ng_pm_cfg_ptr = 0x3fcdfd78;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdfd74;\ng_txop_queue_status_ptr = 0x3fcdfd70;\ng_mac_sleep_en_ptr = 0x3fcdfd6c;\ng_mesh_is_root_ptr = 0x3fcdfd68;\ng_mesh_topology_ptr = 0x3fcdfd64;\ng_mesh_init_ps_type_ptr = 0x3fcdfd60;\ng_mesh_is_started_ptr = 0x3fcdfd5c;\ng_config_func = 0x3fcdfd58;\ng_net80211_tx_func = 0x3fcdfd54;\ng_timer_func = 0x3fcdfd50;\ns_michael_mic_failure_cb = 0x3fcdfd4c;\nwifi_sta_rx_probe_req = 0x3fcdfd48;\ng_tx_done_cb_func = 0x3fcdfd44;\ng_per_conn_trc = 0x3fcdfd28;\ns_encap_amsdu_func = 0x3fcdfd24;\nbars = 0x3fcdfc84;\neb_txdesc_space = 0x3fcdfbf4;\neb_space = 0x3fcdfb54;\ng_pd_mac_in_light_sleep = 0x3fcdfb50;\ns_fix_rate_mask = 0x3fcdfb4c;\ns_fix_rate = 0x3fcdfb44;\ng_wdev_csi_rx = 0x3fcdfb40;\ng_wdev_csi_rx_ctx = 0x3fcdfb3c;\nBcnSendTick = 0x3fcdfb38;\ng_pp_timer_info_ptr = 0x3fcdfb34;\nrcP2P11NSchedTbl_ptr = 0x3fcdfb30;\nrcP2P11GSchedTbl_ptr = 0x3fcdfb2c;\nrc11GSchedTbl_ptr = 0x3fcdfb28;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001f7c;\nampdu_dispatch = 0x40001f80;\nampdu_dispatch_all = 0x40001f84;\nampdu_dispatch_as_many_as_possible = 0x40001f88;\nampdu_dispatch_movement = 0x40001f8c;\nampdu_dispatch_upto = 0x40001f90;\nchm_is_at_home_channel = 0x40001f94;\ncnx_node_is_existing = 0x40001f98;\ncnx_node_search = 0x40001f9c;\nic_ebuf_recycle_rx = 0x40001fa0;\nic_ebuf_recycle_tx = 0x40001fa4;\nic_reset_rx_ba = 0x40001fa8;\nieee80211_align_eb = 0x40001fac;\nieee80211_ampdu_reorder = 0x40001fb0;\nieee80211_ampdu_start_age_timer = 0x40001fb4;\nieee80211_encap_esfbuf = 0x40001fb8;\nieee80211_is_tx_allowed = 0x40001fbc;\nieee80211_output_pending_eb = 0x40001fc0;\nieee80211_output_process = 0x40001fc4;\nieee80211_set_tx_desc = 0x40001fc8;\n\/*sta_input = 0x40001fcc;*\/\nwifi_get_macaddr = 0x40001fd0;\nwifi_rf_phy_disable = 0x40001fd4;\nwifi_rf_phy_enable = 0x40001fd8;\nic_ebuf_alloc = 0x40001fdc;\nieee80211_classify = 0x40001fe0;\nieee80211_copy_eb_header = 0x40001fe4;\nieee80211_recycle_cache_eb = 0x40001fe8;\nieee80211_search_node = 0x40001fec;\nroundup2 = 0x40001ff0;\nieee80211_crypto_encap = 0x40001ff4;\nieee80211_crypto_decap = 0x40001ff8;\nieee80211_decap = 0x40001ffc;\nieee80211_set_tx_pti = 0x40002000;\nwifi_is_started = 0x40002004;\nieee80211_gettid = 0x40002008;\nieee80211_ccmp_decrypt = 0x4000200c;\nieee80211_ccmp_encrypt = 0x40002010;\nccmp_encap = 0x40002014;\nccmp_decap = 0x40002018;\ntkip_encap = 0x4000201c;\ntkip_decap = 0x40002020;\nwep_encap = 0x40002024;\nwep_decap = 0x40002028;\ndbg_hmac_rxtx_statis_dump = 0x4000202c;\ndbg_hmac_statis_dump = 0x40002030;\nieee80211_send_action_vendor_spec = 0x40002034;\nieee80211_deauth_construct = 0x40002040;\nieee80211_disassoc_construct = 0x40002044;\nieee80211_vnd_lora_ie_size = 0x40002048;\nieee80211_vnd_ie_size = 0x4000204c;\nieee80211_add_ssid = 0x40002050;\nieee80211_add_rates = 0x40002054;\nieee80211_add_xrates = 0x40002058;\nieee80211_is_ht_cipher = 0x4000205c;\nieee80211_assoc_resp_construct = 0x40002064;\nieee80211_setup_lr_rates = 0x40002068;\nieee80211_ht_node_init = 0x4000206c;\nieee80211_is_support_rate = 0x40002070;\nieee80211_setup_rates = 0x40002074;\nieee80211_is_lr_only = 0x40002078;\nieee80211_setup_phy_mode = 0x4000207c;\nieee80211_sta_is_connected = 0x40002080;\ncurrent_task_is_wifi_task = 0x40002084;\nwifi_get_init_state = 0x40002088;\nieee80211_timer_process = 0x4000208c;\ncnx_coexist_timeout = 0x40002090;\n\/* sta_recv_mgmt = 0x40002094;*\/\nieee80211_send_setup = 0x40002098;\nieee80211_send_probereq = 0x4000209c;\nsta_auth_shared = 0x400020a4;\ncnx_coexist_timeout_process = 0x400020ac;\nieee80211_alloc_challenge = 0x400020b0;\ncnx_assoc_timeout = 0x400020b4;\nieee80211_vnd_ie_set = 0x400020b8;\nieee80211_vnd_lora_ie_set = 0x400020bc;\nieee80211_add_wme_param = 0x400020c0;\nieee80211_add_dsparams = 0x400020c4;\nieee80211_add_csa = 0x400020c8;\nieee80211_add_extcap = 0x400020cc;\nieee80211_regdomain_get_country = 0x400020d0;\nieee80211_add_countryie = 0x400020d4;\nieee80211_amsdu_adjust_head = 0x400020dc;\nieee80211_amsdu_adjust_last_length = 0x400020e0;\nieee80211_amsdu_send_check = 0x400020e4;\nieee80211_amsdu_encap_check = 0x400020e8;\nieee80211_amsdu_length_check = 0x400020ec;\nieee80211_encap_amsdu = 0x400020f0;\nieee80211_output_raw_process = 0x400020f4;\nieee80211_raw_frame_sanity_check = 0x400020fc;\nieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;\nieee80211_crypto_aes_128_cmac_decrypt = 0x40002104;\nieee80211_alloc_tx_buf = 0x40002108;\nieee80211_output_do = 0x4000210c;\nieee80211_send_nulldata = 0x40002110;\nieee80211_setup_robust_mgmtframe = 0x40002114;\nieee80211_mgmt_output = 0x40002118;\nieee80211_encap_null_data = 0x4000211c;\nieee80211_send_deauth = 0x40002120;\nieee80211_alloc_deauth = 0x40002124;\nieee80211_send_proberesp = 0x40002128;\nieee80211_tx_mgt_cb = 0x4000212c;\nieee80211_getcapinfo = 0x40002130;\nsta_rx_csa = 0x40002134;\nsta_recv_sa_query_resp = 0x40002144;\nieee80211_set_max_rate = 0x4000214c;\nic_set_sta = 0x40002150;\nieee80211_parse_wpa = 0x40002158;\nieee80211_add_assoc_req_ies = 0x40002160;\nieee80211_add_probe_req_ies = 0x40002164;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdfb24;\ng_scan = 0x3fcdfb20;\ng_chm = 0x3fcdfb1c;\ng_ic_ptr = 0x3fcdfb18;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_tx_cacheq_ptr = 0x3fcdfb14;\ns_netstack_free = 0x3fcdfb10;\nmesh_rxcb = 0x3fcdfb0c;\nsta_rxcb = 0x3fcdfb08;\nccmp_ptr = 0x3fcdfb04;\ns_wifi_nvs_ptr = 0x3fcdfb00;\ntkip_ptr = 0x3fcdfafc;\nwep_ptr = 0x3fcdfaf8;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_misc_nvs = 0x3fcdfaf0;\ns_wifi_init_state = 0x3fcdfac0;\ns_wifi_task_hdl = 0x3fcdfaec;\nin_rssi_adjust = 0x3fcdfae8;\nrssi_saved = 0x3fcdfae0;\nrssi_index = 0x3fcdfadc;\ns_sa_query_retries = 0x3fcdfad8;\ns_sa_query_success = 0x3fcdfad5;\ng_sta_connected_flag = 0x3fcdfad4;\nwpa_crypto_funcs_ptr = 0x3fcdfad0;\ns_netstack_ref = 0x3fcdfacc;\nsta_csa_timer_ptr = 0x3fcdfac8;\ns_trans_id = 0x3fcdfac4;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x40002168;\ncoex_bt_release = 0x4000216c;\ncoex_bt_request = 0x40002170;\ncoex_core_ble_conn_dyn_prio_get = 0x40002174;\ncoex_core_event_duration_get = 0x40002178;\ncoex_core_pti_get = 0x4000217c;\ncoex_core_release = 0x40002180;\ncoex_core_request = 0x40002184;\ncoex_core_status_get = 0x40002188;\ncoex_core_timer_idx_get = 0x4000218c;\ncoex_event_duration_get = 0x40002190;\ncoex_hw_timer_disable = 0x40002194;\ncoex_hw_timer_enable = 0x40002198;\ncoex_hw_timer_set = 0x4000219c;\ncoex_schm_interval_set = 0x400021a0;\ncoex_schm_lock = 0x400021a4;\ncoex_schm_unlock = 0x400021a8;\ncoex_status_get = 0x400021ac;\ncoex_wifi_release = 0x400021b0;\nesp_coex_ble_conn_dynamic_prio_get = 0x400021b4;\n\/*coex_hw_timer_tick_get = 0x400021b8;*\/\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdfabc;\ncoex_pti_tab_ptr = 0x3fcdfab8;\ncoex_schm_env_ptr = 0x3fcdfab4;\ncoexist_funcs = 0x3fcdfab0;\ng_coa_funcs_p = 0x3fcdfaac;\ng_coex_param_ptr = 0x3fcdfaa8;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_param_addr = 0x400021bc;\nphy_get_romfuncs = 0x400021c0;\nchip729_phyrom_version = 0x400021c4;\nchip729_phyrom_version_num = 0x400021c8;\nrom_get_rc_dout = 0x400021cc;\nrc_cal = 0x400021d0;\nphy_analog_delay_cal = 0x400021d4;\nphy_rx_rifs_en = 0x400021d8;\nphy_current_level_set = 0x400021dc;\nphy_bbpll_en_usb = 0x400021e0;\nphy_bt_power_track = 0x400021e4;\nphy_xpd_tsens = 0x400021e8;\nbb_wdt_rst_enable = 0x400021ec;\nbb_wdt_int_enable = 0x400021f0;\nbb_wdt_timeout_clear = 0x400021f4;\nbb_wdt_get_status = 0x400021f8;\nrom_enter_critical_phy = 0x400021fc;\nrom_exit_critical_phy = 0x40002200;\nrom_bb_bss_cbw40 = 0x40002204;\nrom_set_chan_reg = 0x40002208;\nabs_temp = 0x4000220c;\nset_chan_cal_interp = 0x40002210;\nloopback_mode_en = 0x40002214;\nget_data_sat = 0x40002218;\nphy_byte_to_word = 0x4000221c;\nphy_get_rx_freq = 0x40002220;\ni2c_master_reset = 0x40002224;\nchan14_mic_enable = 0x40002228;\nchan14_mic_cfg = 0x4000222c;\nset_adc_rand = 0x40002230;\nphy_set_most_tpw = 0x40002234;\nphy_get_most_tpw = 0x40002238;\nesp_tx_state_out = 0x4000223c;\nphy_get_adc_rand = 0x40002240;\nphy_internal_delay = 0x40002244;\nphy_ftm_comp = 0x40002248;\nphy_11p_set = 0x4000224c;\nphy_freq_mem_backup = 0x40002250;\nant_dft_cfg = 0x40002254;\nant_wifitx_cfg = 0x40002258;\nant_wifirx_cfg = 0x4000225c;\nant_bttx_cfg = 0x40002260;\nant_btrx_cfg = 0x40002264;\nphy_chan_dump_cfg = 0x40002268;\nphy_enable_low_rate = 0x4000226c;\nphy_disable_low_rate = 0x40002270;\nphy_dig_reg_backup = 0x40002274;\nphy_chan_filt_set = 0x40002278;\nphy_rx11blr_cfg = 0x4000227c;\nset_cca = 0x40002280;\nset_rx_sense = 0x40002284;\nrx_gain_force = 0x40002288;\nrom_phy_en_hw_set_freq = 0x4000228c;\nrom_phy_dis_hw_set_freq = 0x40002290;\nwr_rf_freq_mem = 0x40002294;\nfreq_i2c_write_set = 0x40002298;\nwrite_pll_cap_mem = 0x4000229c;\npll_dac_mem_update = 0x400022a0;\npll_cap_mem_update = 0x400022a4;\nget_rf_freq_cap = 0x400022a8;\nget_rf_freq_init = 0x400022ac;\nfreq_get_i2c_data = 0x400022b0;\nfreq_i2c_data_write = 0x400022b4;\nset_chan_freq_hw_init = 0x400022b8;\nset_chan_freq_sw_start = 0x400022bc;\nrom_get_i2c_read_mask = 0x400022c0;\nrom_get_i2c_mst0_mask = 0x400022c4;\nrom_get_i2c_hostid = 0x400022c8;\nrom_chip_i2c_readReg_org = 0x400022cc;\nrom_chip_i2c_readReg = 0x400022d0;\nrom_i2c_paral_set_mst0 = 0x400022d4;\nrom_i2c_paral_set_read = 0x400022d8;\nrom_i2c_paral_read = 0x400022dc;\nrom_i2c_paral_write = 0x400022e0;\nrom_i2c_paral_write_num = 0x400022e4;\nrom_i2c_paral_write_mask = 0x400022e8;\nrom_i2c_readReg = 0x400022ec;\nrom_chip_i2c_writeReg = 0x400022f0;\nrom_i2c_writeReg = 0x400022f4;\nrom_i2c_readReg_Mask = 0x400022f8;\nrom_i2c_writeReg_Mask = 0x400022fc;\nrom_set_txcap_reg = 0x40002300;\ni2c_sar2_init_code = 0x40002304;\nphy_i2c_init1 = 0x40002308;\nphy_i2c_init2 = 0x4000230c;\nphy_get_i2c_data = 0x40002310;\nbias_reg_set = 0x40002314;\ni2c_rc_cal_set = 0x40002318;\ni2c_bbpll_set = 0x4000231c;\nrom_phy_xpd_rf = 0x40002320;\nphy_wakeup_init_rom = 0x40002324;\nregister_chipv7_phy_init_param = 0x40002328;\nphy_reg_init = 0x4000232c;\nphy_close_rf_rom = 0x40002330;\nrom_pbus_force_mode = 0x40002334;\nrom_pbus_rd_addr = 0x40002338;\nrom_pbus_rd_shift = 0x4000233c;\nrom_pbus_force_test = 0x40002340;\nrom_pbus_rd = 0x40002344;\nrom_pbus_debugmode = 0x40002348;\nrom_pbus_workmode = 0x4000234c;\nrom_pbus_set_rxgain = 0x40002350;\nrom_pbus_xpd_rx_off = 0x40002354;\nrom_pbus_xpd_rx_on = 0x40002358;\nrom_pbus_xpd_tx_off = 0x4000235c;\nrom_pbus_xpd_tx_on = 0x40002360;\nrom_pbus_set_dco = 0x40002364;\nrom_set_loopback_gain = 0x40002368;\nrom_txcal_debuge_mode = 0x4000236c;\nrom_txcal_work_mode = 0x40002370;\nset_pbus_mem = 0x40002374;\nrom_pwdet_sar2_init = 0x40002378;\nrom_en_pwdet = 0x4000237c;\nrom_get_sar_sig_ref = 0x40002380;\nrom_pwdet_tone_start = 0x40002384;\nrom_get_tone_sar_dout = 0x40002388;\nrom_get_fm_sar_dout = 0x4000238c;\nrom_txtone_linear_pwr = 0x40002390;\nrom_get_power_db = 0x40002394;\nrom_meas_tone_pwr_db = 0x40002398;\nrom_pkdet_vol_start = 0x4000239c;\nrom_read_sar_dout = 0x400023a0;\nrom_read_sar2_code = 0x400023a4;\nrom_get_sar2_vol = 0x400023a8;\nrom_get_pll_vol = 0x400023ac;\nrom_tx_pwctrl_bg_init = 0x400023b0;\nrom_phy_pwdet_always_en = 0x400023b4;\nrom_phy_pwdet_onetime_en = 0x400023b8;\nlinear_to_db = 0x400023bc;\nrom_disable_agc = 0x400023c0;\nrom_enable_agc = 0x400023c4;\nrom_disable_wifi_agc = 0x400023c8;\nrom_enable_wifi_agc = 0x400023cc;\nrom_write_gain_mem = 0x400023d0;\nrom_bb_bss_cbw40_dig = 0x400023d4;\nrom_cbw2040_cfg = 0x400023d8;\nrom_mac_tx_chan_offset = 0x400023dc;\nrom_tx_paon_set = 0x400023e0;\nrom_i2cmst_reg_init = 0x400023e4;\nrom_bt_gain_offset = 0x400023e8;\nrom_fe_reg_init = 0x400023ec;\nrom_mac_enable_bb = 0x400023f0;\nrom_bb_wdg_cfg = 0x400023f4;\nrom_fe_txrx_reset = 0x400023f8;\nrom_set_rx_comp = 0x400023fc;\nrom_write_chan_freq = 0x40002400;\nrom_agc_reg_init = 0x40002404;\nrom_bb_reg_init = 0x40002408;\nrom_write_txrate_power_offset = 0x4000240c;\nrom_open_i2c_xpd = 0x40002410;\nrom_txiq_set_reg = 0x40002414;\nrom_rxiq_set_reg = 0x40002418;\nrom_phy_bbpll_cal = 0x4000241c;\nphy_disable_cca = 0x40002420;\nphy_enable_cca = 0x40002424;\nforce_txon = 0x40002428;\nset_txclk_en = 0x4000242c;\nset_rxclk_en = 0x40002430;\nstart_tx_tone_step = 0x40002434;\nstop_tx_tone = 0x40002438;\nbb_wdg_test_en = 0x4000243c;\nnoise_floor_auto_set = 0x40002440;\nread_hw_noisefloor = 0x40002444;\niq_corr_enable = 0x40002448;\nbt_tx_dig_gain = 0x4000244c;\nwifi_tx_dig_reg = 0x40002450;\nwifi_agc_sat_gain = 0x40002454;\nphy_ant_init = 0x40002458;\nphy_set_bbfreq_init = 0x4000245c;\nwifi_fbw_sel = 0x40002460;\nphy_rx_sense_set = 0x40002464;\ntx_state_set = 0x40002468;\nphy_close_pa = 0x4000246c;\nbt_filter_reg = 0x40002470;\nphy_freq_correct = 0x40002474;\nset_pbus_reg = 0x40002478;\nwifi_rifs_mode_en = 0x4000247c;\nrfagc_disable = 0x40002480;\nrom_restart_cal = 0x40002484;\nrom_write_rfpll_sdm = 0x40002488;\nrom_wait_rfpll_cal_end = 0x4000248c;\nrom_rfpll_set_freq = 0x40002490;\nrom_rfpll_cap_init_cal = 0x40002494;\nrom_set_rfpll_freq = 0x40002498;\nrom_write_pll_cap = 0x4000249c;\nrom_read_pll_cap = 0x400024a0;\nmhz2ieee = 0x400024a4;\nchan_to_freq = 0x400024a8;\nset_rf_freq_offset = 0x400024ac;\nset_channel_rfpll_freq = 0x400024b0;\nrfpll_cap_correct = 0x400024b4;\nphy_set_freq = 0x400024b8;\ncorrect_rfpll_offset = 0x400024bc;\npll_vol_cal = 0x400024c0;\nchip_v7_set_chan_misc = 0x400024c4;\nchip_v7_set_chan = 0x400024c8;\nchip_v7_set_chan_offset = 0x400024cc;\nchip_v7_set_chan_ana = 0x400024d0;\nset_chanfreq = 0x400024d4;\nrom_rxiq_cover_mg_mp = 0x400024d8;\nrom_rfcal_rxiq = 0x400024dc;\nrom_get_rfcal_rxiq_data = 0x400024e0;\nrom_pbus_rx_dco_cal = 0x400024e4;\nrom_rxdc_est_min = 0x400024e8;\nrom_pbus_rx_dco_cal_1step = 0x400024ec;\nrom_set_lb_txiq = 0x400024f0;\nrom_set_rx_gain_cal_iq = 0x400024f4;\nrom_set_rx_gain_cal_dc = 0x400024f8;\niq_est_enable = 0x400024fc;\niq_est_disable = 0x40002500;\ndc_iq_est = 0x40002504;\nset_cal_rxdc = 0x40002508;\nrxiq_get_mis = 0x4000250c;\nspur_reg_write_one_tone = 0x40002510;\nspur_cal = 0x40002514;\nspur_coef_cfg = 0x40002518;\ngen_rx_gain_table = 0x4000251c;\nwr_rx_gain_mem = 0x40002520;\nset_rx_gain_param = 0x40002524;\nset_rx_gain_table = 0x40002528;\nrom_tester_wifi_cali = 0x4000252c;\nesp_recover_efuse_data = 0x40002530;\nbt_track_pll_cap = 0x40002534;\nrfpll_cap_track = 0x40002538;\nphy_param_track = 0x4000253c;\ntxpwr_correct = 0x40002540;\ntxpwr_cal_track = 0x40002544;\n\/* tx_pwctrl_background = 0x40002548;*\/\nbt_track_tx_power = 0x4000254c;\nwifi_track_tx_power = 0x40002550;\nrom_code_to_temp = 0x40002554;\nrom_tsens_index_to_dac = 0x40002558;\nrom_tsens_index_to_offset = 0x4000255c;\nrom_tsens_dac_cal = 0x40002560;\nrom_tsens_code_read = 0x40002564;\nrom_tsens_temp_read = 0x40002568;\nrom_temp_to_power = 0x4000256c;\ntsens_read_init = 0x40002570;\nget_temp_init = 0x40002574;\nrom_txiq_cover = 0x40002578;\nrom_rfcal_txiq = 0x4000257c;\nrom_get_power_atten = 0x40002580;\nrom_tx_pwctrl_init_cal = 0x40002584;\nbt_txdc_cal = 0x40002588;\nbt_txiq_cal = 0x4000258c;\ntxiq_cal_init = 0x40002590;\ntxdc_cal_init = 0x40002594;\ntxdc_cal_v70 = 0x40002598;\ntxiq_get_mis_pwr = 0x4000259c;\npwdet_ref_code = 0x400025a0;\npwdet_code_cal = 0x400025a4;\nrfcal_txcap = 0x400025a8;\ntx_cap_init = 0x400025ac;\nrfcal_pwrctrl = 0x400025b0;\ntx_pwctrl_init = 0x400025b4;\nbt_tx_pwctrl_init = 0x400025b8;\nbt_txpwr_freq = 0x400025bc;\nrom_txbbgain_to_index = 0x400025c0;\nrom_index_to_txbbgain = 0x400025c4;\nrom_bt_index_to_bb = 0x400025c8;\nrom_bt_bb_to_index = 0x400025cc;\nrom_bt_get_tx_gain = 0x400025d0;\nrom_get_tx_gain_value = 0x400025d4;\nrom_wifi_get_tx_gain = 0x400025d8;\nrom_set_tx_gain_mem = 0x400025dc;\nrom_get_rate_fcc_index = 0x400025e0;\nrom_get_chan_target_power = 0x400025e4;\nrom_wifi_tx_dig_gain = 0x400025e8;\nrom_wifi_set_tx_gain = 0x400025ec;\nrom_bt_set_tx_gain = 0x400025f0;\nwifi_11g_rate_chg = 0x400025f4;\nbt_chan_pwr_interp = 0x400025f8;\nbt_tx_gain_init = 0x400025fc;\n\/* Data (.data, .bss, .rodata) *\/\nphy_param_rom = 0x3fcdfaa4;\n\n\n\/***************************************\n Group rom_btbb\n ***************************************\/\n\n\/* Functions *\/\nbt_agc_gain_offset = 0x40002600;\nbt_agc_gain_max = 0x40002604;\nbt_set_rx_comp = 0x40002608;\nbt_agc_gain_set = 0x4000260c;\nbt_agc_rssi_thresh = 0x40002610;\nbt_agc_target_set = 0x40002614;\nbt_agc_restart_set = 0x40002618;\nbt_agc_recorrect_set = 0x4000261c;\nbt_agc_detect_set = 0x40002620;\nbt_bb_rx_correlator_set = 0x40002624;\nbt_bb_rx_dpo_set = 0x40002628;\nbt_bb_rx_filter_sel = 0x4000262c;\nbt_bb_rx_set1 = 0x40002630;\nbt_bb_v2_rx_set = 0x40002634;\nbt_bb_v2_tx_set = 0x40002638;\nbt_bb_tx_cca_set = 0x4000263c;\nbt_bb_tx_cca_period = 0x40002640;\nbt_bb_tx_cca_fifo_reset = 0x40002644;\nbt_bb_tx_cca_fifo_empty = 0x40002648;\nbt_bb_tx_cca_fifo_full = 0x4000264c;\nbt_bb_tx_cca_fifo_count = 0x40002650;\nbt_bb_tx_cca_fifo_read = 0x40002654;\ncoex_pti_v2 = 0x40002658;\nbt_bb_set_le_tx_on_delay = 0x4000265c;\nbt_bb_set_corr_thresh_le = 0x40002660;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"27e00f497a33a362bfb03e89be95afa7f5862122","subject":"x86: 32-bit: set _image_text_start properly","message":"x86: 32-bit: set _image_text_start properly\n\nStrictly speaking, should bee a virtual, not physical address.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/x86\/ia32\/linker.ld","new_file":"include\/arch\/x86\/ia32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <sys\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n#ifdef CONFIG_XIP\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame_hdr)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_X86_MMU\n\t. = ALIGN(4);\n\t_mmu_region_list_start = .;\n\tKEEP(*(\"._mmu_region.static.*\"))\n\t_mmu_region_list_end = .;\n#endif \/* CONFIG_X86_MMU *\/\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n#ifdef CONFIG_XIP\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n#endif\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n#include <linker\/common-noinit.ld>\n\n\tMMU_PAGE_ALIGN\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif \/* LINKER_PASS2 *\/\n\n\tz_interrupt_vectors_allocated = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_vectors_alloc))\n#else\n\t. += (CONFIG_IDT_NUM_VECTORS + 7) \/ 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_X86_KPTI\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_start = .;\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. IDT, GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\/\n#endif \/* CONFIG_X86_KPTI *\/\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_KPTI\n\tz_trampoline_stack_start = .;\n\tMMU_PAGE_ALIGN\n\tz_trampoline_stack_end = .;\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_trampoline_stack_end - z_trampoline_stack_start >= 40,\n\t\t\"trampoline stack too small\");\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <sys\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n#ifdef CONFIG_XIP\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#endif\n\t_image_text_start = PHYS_LOAD_ADDR;\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame_hdr)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_X86_MMU\n\t. = ALIGN(4);\n\t_mmu_region_list_start = .;\n\tKEEP(*(\"._mmu_region.static.*\"))\n\t_mmu_region_list_end = .;\n#endif \/* CONFIG_X86_MMU *\/\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n#ifdef CONFIG_XIP\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n#endif\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n#include <linker\/common-noinit.ld>\n\n\tMMU_PAGE_ALIGN\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif \/* LINKER_PASS2 *\/\n\n\tz_interrupt_vectors_allocated = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_vectors_alloc))\n#else\n\t. += (CONFIG_IDT_NUM_VECTORS + 7) \/ 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_X86_KPTI\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_start = .;\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. IDT, GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\/\n#endif \/* CONFIG_X86_KPTI *\/\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_KPTI\n\tz_trampoline_stack_start = .;\n\tMMU_PAGE_ALIGN\n\tz_trampoline_stack_end = .;\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_trampoline_stack_end - z_trampoline_stack_start >= 40,\n\t\t\"trampoline stack too small\");\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"164b275c2eb2a9d3516b84d92fd9b467000776e8","subject":"Add convert_opt to ldoc config.","message":"Add convert_opt to ldoc config.\n","repos":"leMaik\/RpgPlus","old_file":"docs\/lua-api\/config.ld","new_file":"docs\/lua-api\/config.ld","new_contents":"project = 'RpgPlus'\ndescription = 'RpgPlus Scripting API'\nfull_description = [[\nThese are all available methods for RpgPlus scripts.\n]]\nfile = {'.'}\nformat = 'markdown'\nconvert_opt = true","old_contents":"project = 'RpgPlus'\ndescription = 'RpgPlus Scripting API'\nfull_description = [[\nThese are all available methods for RpgPlus scripts.\n]]\nfile = {'.'}\nformat = 'markdown'","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"02f021068f3394fbbac0ef49f5ee7b42e4118e60","subject":"linker\/common-ram.ld: force input section align","message":"linker\/common-ram.ld: force input section align\n\nThese special kernel sections represent arrays of kernel objects than\nare iterated over at runtime to perform initialization.\n\nThe code expects all the data in these sections to be in the form of an\narray of that section type, with each element sizeof(type) bytes apart.\n\nUnfortunately, the linker sometimes has other plans and in some cases\nwas defaulting to aligning the data to some large power-of-two value,\nsuch as 64 bytes. This causes any attempt to iterate over these sections\nto fail as they are not a proper array.\n\nUse the ld SUBALIGN() directive to force the alignment of these input\nsections to 4 bytes.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"aceofall\/zephyr-iotos,mbolivar\/zephyr,fbsder\/zephyr,mbolivar\/zephyr,kraj\/zephyr,nashif\/zephyr,fbsder\/zephyr,finikorg\/zephyr,nashif\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,holtmann\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,kraj\/zephyr,holtmann\/zephyr,mbolivar\/zephyr,holtmann\/zephyr,explora26\/zephyr,runchip\/zephyr-cc3220,kraj\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3220,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,holtmann\/zephyr,rsalveti\/zephyr,finikorg\/zephyr,aceofall\/zephyr-iotos,explora26\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,fbsder\/zephyr,aceofall\/zephyr-iotos,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,rsalveti\/zephyr,ldts\/zephyr,mbolivar\/zephyr,nashif\/zephyr,mbolivar\/zephyr,zephyriot\/zephyr,ldts\/zephyr,explora26\/zephyr,runchip\/zephyr-cc3220,ldts\/zephyr,galak\/zephyr,aceofall\/zephyr-iotos,punitvara\/zephyr,nashif\/zephyr,rsalveti\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,fbsder\/zephyr,aceofall\/zephyr-iotos,nashif\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,zephyriot\/zephyr,Vudentz\/zephyr,kraj\/zephyr,runchip\/zephyr-cc3220,punitvara\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,fbsder\/zephyr,punitvara\/zephyr,rsalveti\/zephyr,rsalveti\/zephyr,runchip\/zephyr-cc3220,punitvara\/zephyr,holtmann\/zephyr","old_file":"include\/linker\/common-ram.ld","new_file":"include\/linker\/common-ram.ld","new_contents":"\tSECTION_DATA_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_DATA_PROLOGUE(initlevel_error, (OPTIONAL), )\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\tSECTION_DATA_PROLOGUE(initshell, (OPTIONAL),)\n\t{\n\t\tSHELL_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_static_thread_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_static_thread_data_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._static_thread_data.static.*\")))\n\t\t_static_thread_data_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_timer_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_timer_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_timer.static.*\")))\n\t\t_k_timer_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_slab_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mem_slab_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_slab.static.*\")))\n\t\t_k_mem_slab_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\t\t_k_mem_pool_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_pool.static.*\")))\n\t\t_k_mem_pool_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_sem_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_sem_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_sem.static.*\")))\n\t\t_k_sem_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mutex_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mutex_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mutex.static.*\")))\n\t\t_k_mutex_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_alert_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_alert_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_alert.static.*\")))\n\t\t_k_alert_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_queue_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_queue_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_queue.static.*\")))\n\t\t_k_queue_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_stack_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_stack_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_stack.static.*\")))\n\t\t_k_stack_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_msgq_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_msgq_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_msgq.static.*\")))\n\t\t_k_msgq_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mbox_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mbox_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mbox.static.*\")))\n\t\t_k_mbox_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_pipe_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_pipe_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe.static.*\")))\n\t\t_k_pipe_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_work_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_work_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_work.static.*\")))\n\t\t_k_work_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_task_list, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_task_list_start = .;\n\t\t*(._k_task_list.public.*)\n\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_event_list, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_event_list_start = .;\n\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_memory_pool, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t*(._k_memory_pool.struct*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\n\t\t_k_mem_pool_start = .;\n\t\t*(._k_memory_pool.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool*\")))\n\t\t_k_mem_pool_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_start = .;\n\t\t*(\".net_if.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if.*\")))\n\t\t__net_if_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if_event, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_event_start = .;\n\t\t*(\".net_if_event.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if_event.*\")))\n\t\t__net_if_event_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SHELL)\n\tSECTION_DATA_PROLOGUE(net_stack, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_stack_start = .;\n\t\t*(\".net_stack.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_stack*\")))\n\t\t__net_stack_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_NET_SHELL *\/\n\n\tSECTION_DATA_PROLOGUE(net_l2_data, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_l2_data_start = .;\n\t\t*(\".net_l2.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.data*\")))\n\t\t__net_l2_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n","old_contents":"\tSECTION_DATA_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_DATA_PROLOGUE(initlevel_error, (OPTIONAL), )\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\tSECTION_DATA_PROLOGUE(initshell, (OPTIONAL),)\n\t{\n\t\tSHELL_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_static_thread_area, (OPTIONAL),)\n\t{\n\t\t_static_thread_data_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._static_thread_data.static.*\")))\n\t\t_static_thread_data_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_timer_area, (OPTIONAL),)\n\t{\n\t\t_k_timer_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_timer.static.*\")))\n\t\t_k_timer_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_slab_area, (OPTIONAL),)\n\t{\n\t\t_k_mem_slab_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_slab.static.*\")))\n\t\t_k_mem_slab_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_pool_area, (OPTIONAL),)\n\t{\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\t\t_k_mem_pool_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_pool.static.*\")))\n\t\t_k_mem_pool_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_sem_area, (OPTIONAL),)\n\t{\n\t\t_k_sem_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_sem.static.*\")))\n\t\t_k_sem_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mutex_area, (OPTIONAL),)\n\t{\n\t\t_k_mutex_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mutex.static.*\")))\n\t\t_k_mutex_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_alert_area, (OPTIONAL),)\n\t{\n\t\t_k_alert_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_alert.static.*\")))\n\t\t_k_alert_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_queue_area, (OPTIONAL),)\n\t{\n\t\t_k_queue_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_queue.static.*\")))\n\t\t_k_queue_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_stack_area, (OPTIONAL),)\n\t{\n\t\t_k_stack_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_stack.static.*\")))\n\t\t_k_stack_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_msgq_area, (OPTIONAL),)\n\t{\n\t\t_k_msgq_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_msgq.static.*\")))\n\t\t_k_msgq_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mbox_area, (OPTIONAL),)\n\t{\n\t\t_k_mbox_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mbox.static.*\")))\n\t\t_k_mbox_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_pipe_area, (OPTIONAL),)\n\t{\n\t\t_k_pipe_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe.static.*\")))\n\t\t_k_pipe_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_work_area, (OPTIONAL),)\n\t{\n\t\t_k_work_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_work.static.*\")))\n\t\t_k_work_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_task_list, (OPTIONAL),)\n\t{\n\t\t_k_task_list_start = .;\n\t\t*(._k_task_list.public.*)\n\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_event_list, (OPTIONAL),)\n\t{\n\t\t_k_event_list_start = .;\n\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_memory_pool, (OPTIONAL),)\n\t{\n\t\t*(._k_memory_pool.struct*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\n\t\t_k_mem_pool_start = .;\n\t\t*(._k_memory_pool.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool*\")))\n\t\t_k_mem_pool_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area, (OPTIONAL),)\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if, (OPTIONAL),)\n\t{\n\t\t__net_if_start = .;\n\t\t*(\".net_if.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if.*\")))\n\t\t__net_if_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if_event, (OPTIONAL),)\n\t{\n\t\t__net_if_event_start = .;\n\t\t*(\".net_if_event.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if_event.*\")))\n\t\t__net_if_event_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SHELL)\n\tSECTION_DATA_PROLOGUE(net_stack, (OPTIONAL),)\n\t{\n\t\t__net_stack_start = .;\n\t\t*(\".net_stack.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_stack*\")))\n\t\t__net_stack_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_NET_SHELL *\/\n\n\tSECTION_DATA_PROLOGUE(net_l2_data, (OPTIONAL),)\n\t{\n\t\t__net_l2_data_start = .;\n\t\t*(\".net_l2.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.data*\")))\n\t\t__net_l2_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4cba88c7bd961d7b41a5b0ab5df03d3cb9a3368d","subject":"updated linker script file","message":"updated linker script file\n","repos":"stateos\/IntrOS-LM4F120XL,stateos\/IntrOS-LM4F120XL","old_file":"startup\/LM4F\/GNUCC\/script.ld","new_file":"startup\/LM4F\/GNUCC\/script.ld","new_contents":"\/*******************************************************************************\n@file     lm4f120h5qr.ld\n@author   Rajmund Szymanski\n@date     02.01.2017\n@brief    Linker script for LM4F120H5QR device with 256KB FLASH and 32KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x00000000, LENGTH = 256K\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  32K\n}\n\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t. = ABSOLUTE(__ram_end - __proc_stack_size);\n\t\t__heap_end = .;\n\t} > RAM\n\n\t__heap_size = SIZEOF(.heap);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","old_contents":"\/*******************************************************************************\n@file     lm4f120h5qr.ld\n@author   Rajmund Szymanski\n@date     02.01.2017\n@brief    Linker script for LM4F120H5QR device with 256KB FLASH and 32KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x00000000, LENGTH = 256K\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  32K\n}\n\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t. = ABSOLUTE(__ram_end - __proc_stack_size);\n\t\t__heap_end = .;\n\t} > RAM\n\n\t__heap_size = SIZEOF(.heap);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"09267bb147c06ef5350b91034342924a9d9efa05","subject":"stm32\/boards\/stm32f722.ld: Provide memory regions for internal FS.","message":"stm32\/boards\/stm32f722.ld: Provide memory regions for internal FS.\n","repos":"trezor\/micropython,pfalcon\/micropython,pramasoul\/micropython,tobbad\/micropython,bvernoux\/micropython,adafruit\/circuitpython,kerneltask\/micropython,MrSurly\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,MrSurly\/micropython,selste\/micropython,pramasoul\/micropython,trezor\/micropython,bvernoux\/micropython,pozetroninc\/micropython,kerneltask\/micropython,MrSurly\/micropython,pozetroninc\/micropython,bvernoux\/micropython,trezor\/micropython,henriknelson\/micropython,bvernoux\/micropython,pfalcon\/micropython,pfalcon\/micropython,pramasoul\/micropython,kerneltask\/micropython,adafruit\/circuitpython,henriknelson\/micropython,tobbad\/micropython,pfalcon\/micropython,trezor\/micropython,henriknelson\/micropython,selste\/micropython,henriknelson\/micropython,selste\/micropython,pozetroninc\/micropython,adafruit\/circuitpython,pramasoul\/micropython,pramasoul\/micropython,henriknelson\/micropython,trezor\/micropython,MrSurly\/micropython,MrSurly\/micropython,selste\/micropython,selste\/micropython,kerneltask\/micropython,tobbad\/micropython,pozetroninc\/micropython,kerneltask\/micropython,bvernoux\/micropython,pfalcon\/micropython,adafruit\/circuitpython,pozetroninc\/micropython,tobbad\/micropython,tobbad\/micropython","old_file":"ports\/stm32\/boards\/stm32f722.ld","new_file":"ports\/stm32\/boards\/stm32f722.ld","new_contents":"\/*\n    GNU linker script for STM32F722, STM32F723, STM32F732, STM32F733\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K     \/* sector 0, 16K *\/\n    FLASH_FS (r)    : ORIGIN = 0x08004000, LENGTH = 112K    \/* sectors 1-4 3*16KiB 1*64KiB*\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 384K    \/* sectors 5-7 3*128KiB = 384K *\/\n    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 64K     \/* Used for storage cache *\/\n    RAM (xrw)       : ORIGIN = 0x20010000, LENGTH = 192K    \/* SRAM1 = 176K, SRAM2 = 16K *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 32K; \/* tunable *\/\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n","old_contents":"\/*\n    GNU linker script for STM32F722, STM32F723, STM32F732, STM32F733\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 32K     \/* sectors 0,1 *\/\n    FLASH_APP (rx)  : ORIGIN = 0x08008000, LENGTH = 480K    \/* sectors 2-7 *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 256K    \/* DTCM+SRAM1+SRAM2 *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 32K; \/* tunable *\/\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4e6f437063768379b029f87fcb34240a1f81035f","subject":"Add more comments to kernel.ld","message":"Add more comments to kernel.ld","repos":"ICTeam28\/PiFox","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"SECTIONS\n{\n  \/**\n   * Start address of the kernel.\n   *\n   * In QEMU, this is hardcoded to 0x100000 (64Kb).\n   * On the actual device, it can be modified, but it defaults to 0x8000 (32Kb).\n   *\/\n  . = 0x10000;\n\n  \/**\n   * Executable code. \n   * \n   * All text segments are copied here. The first file in the object file\n   * is kernel.s and the first function in kernel.s is the kernel function\n   * which initializes everything, so it gets placed at the start address\n   * by the bootstrap code. After the text segment, padding is added in\n   * order to align the next segment to a page boundary.\n   *\/\n  .text :\n  {\n    *(.text)\n  }\n  . = ALIGN(0x1000);\n\n  \/**\n   * Program data, all .data segments concatenated after each other. Padding\n   * is added afterwards to align the next segment to page boundary.\n   *\/\n  .data :\n  {\n    *(.data)\n  }\n  . = ALIGN(0x1000);\n\n  \/**\n   * Stack spaces. These come after the data from the binary file,\n   * thus they are not actually present in it. They are not loaded,\n   * but the addresses are set up for them after the file. If the\n   * length of the file is x, then the stack addresses are located\n   * at the page boundary after x + 64Kb.\n   *\/\n  . = . + 0x800;\n  stack_svc = .;\n  . = . + 0x800;\n  stack_und = .;\n  . = . + 0x800;\n  stack_abt = .;\n  . = . + 0x800;\n  stack_irq = .;\n  . = . + 0x800;\n  stack_fiq = .;\n  . = . + 0x400000;\n  stack_sys = .;\n\n  \/**\n   * Front buffer. Since this buffer is quite large, around 2Mb in size,\n   * it should not appear in the binary file since it would increase the\n   * time it takes to load the kernel. Thus, the address space it requires\n   * is only defined in the linker script and placed at the end of the\n   * kernel, after all data that is loaded from the binary file.\n   *\/\n  . = . + 640 * 480 * 8;\n  gfx_buffer = .;\n}\n","old_contents":"SECTIONS\n{\n  . = 0x10000;\n\n  \/* Executable code *\/\n  .text :\n  {\n    *(.text)\n  }\n  . = ALIGN(0x1000);\n\n  \/* Data *\/\n  .data :\n  {\n    *(.data)\n  }\n  . = ALIGN(0x1000);\n\n  \/* Stack space *\/\n  . = . + 0x800;\n  stack_svc = .;\n  . = . + 0x800;\n  stack_und = .;\n  . = . + 0x800;\n  stack_abt = .;\n  . = . + 0x800;\n  stack_irq = .;\n  . = . + 0x800;\n  stack_fiq = .;\n  . = . + 0x400000;\n  stack_sys = .;\n\n  \/* Front buffer *\/\n  . = . + 640 * 480 * 8;\n  gfx_buffer = .;\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c60664889bf22416c0d7e5276ca9b1ebd3f56055","subject":"updated linker script","message":"updated linker script\n","repos":"stateos\/IntrOS,stateos\/IntrOS,stateos\/IntrOS","old_file":"startup\/STM32F4\/GNUCC\/script.ld","new_file":"startup\/STM32F4\/GNUCC\/script.ld","new_contents":"\/*******************************************************************************\n@file     stm32f4xx.ld\n@author   Rajmund Szymanski\n@date     28.02.2017\n@brief    Linker script for STM32F407VG device with 1024KB FLASH and 192KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 1024k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   64k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  128k\n\/*\tAUX (rwx) : ORIGIN = 0x2001C000, LENGTH =   16k\n*\/\tBKP (rwx) : ORIGIN = 0x40024000, LENGTH =    4k\n}\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__heap_start = LOADADDR(.proc_stack);\n\t__heap_end   = __ram_end - __proc_stack_size;\n\n\t__proc_stack_start = __heap_end;\n\t__proc_stack_end   = __ram_end;\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n\tPROVIDE(__process_stack_end   = __proc_stack_end);\n}\n","old_contents":"\/*******************************************************************************\n@file     stm32f4xx.ld\n@author   Rajmund Szymanski\n@date     02.01.2017\n@brief    Linker script for STM32F407VG device with 1024KB FLASH and 192KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 1024k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   64k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  128k\n\/*\tAUX (rwx) : ORIGIN = 0x2001C000, LENGTH =   16k\n*\/\tBKP (rwx) : ORIGIN = 0x40024000, LENGTH =    4k\n}\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t. = ABSOLUTE(__ram_end - __proc_stack_size);\n\t\t__heap_end = .;\n\t} > RAM\n\n\t__heap_size = SIZEOF(.heap);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e8f9d7d1073f1fede2e966d535e079e0a932a839","subject":"Align everything to 2M + add explicit offset","message":"Align everything to 2M + add explicit offset\n","repos":"project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak","old_file":"experimental\/oak_baremetal_app_crosvm\/layout.ld","new_file":"experimental\/oak_baremetal_app_crosvm\/layout.ld","new_contents":"\/*\n * Copyright 2022 The Project Oak Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n*\/\n\nENTRY(_start)\n\nPHDRS\n{\n    \/* Note that the permissions flags are currently not respected. *\/\n    \/* Keep the sections here sorted from lowest memory address to largest; crosvm\n     * has a sanity check that expects the section with the lowest address to come\n     * first.\n     *\/\n    \/* Executable text. *\/\n    boot    PT_LOAD FLAGS(4 + 1); \/* PF_R + PF_X *\/\n    text    PT_LOAD FLAGS(4 + 1); \/* PF_R + PF_X *\/\n    \/* Read-only data. *\/\n    rodata  PT_LOAD FLAGS(4); \/* PF_R *\/\n    \/* Initialized read-write data. *\/\n    data    PT_LOAD FLAGS(4 + 2); \/* PF_R + PF_W *\/\n    \/* Uninitialized read-write data. *\/\n    bss     PT_LOAD FLAGS(4 + 2); \/* PF_R + PF_W *\/\n    \/* Special sections for SEV-SNP. *\/\n    cpuid   PT_LOAD FLAGS(1 << 23);\n    secrets PT_LOAD FLAGS(1 << 24);\n}\n\n\/* To set kernel VMA to high memory, set this to 0xFFFFFFFF80000000. *\/\nKERNEL_MEM_START = 0x0;\n\nSECTIONS {\n    \/*\n     * Boot code is executed with identity mapping; the main duty of the boot\n     * code is to set up proper page tables before jumping to the kernel proper.\n     * We place that at 2M (both virtual and physical)\n     *\/\n    .boot 0x200000 : {\n        ram_min = .;\n        *(.boot)\n    } : boot\n\n    \/*\n     * Load the rest of the kernel after KERNEL_MEM_START. The idea is that the initial\n     * boot code should set map KERNEL_MEM_START to physical address 0; therefore, all\n     * VMAs will be LMA + KERNEL_MEM_START.\n     *\/\n    . += KERNEL_MEM_START;\n\n    data_start = .;\n    text_start = .;\n\n    .text ALIGN(2M) : AT(ADDR(.text) - KERNEL_MEM_START) {\n        *(.text .text.*)\n    } : text\n\n    text_end = .;\n\n    .rodata ALIGN(2M) : {\n        *(.rodata .rodata.*)\n    } : rodata\n\n    .data ALIGN(2M) : {\n        *(.data .data.*)\n    } : data\n\n    data_end = .;\n\n    .bss : ALIGN(2M) {\n        bss_start = .;\n        *(.bss .bss.*)\n        bss_size = . - bss_start;\n    } : bss\n\n    \/* Stack grows down, so stack_start is the upper address in memory. *\/\n    .stack (NOLOAD) : ALIGN(2M) {\n        . += 512K;\n    } : bss\n    stack_start = .;\n\n    .cpuid (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : cpuid\n\n    .secrets (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : secrets\n\n    \/DISCARD\/ : {\n        *(.eh_frame*)\n    }\n}\n","old_contents":"\/*\n * Copyright 2022 The Project Oak Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n*\/\n\nENTRY(_start)\n\nPHDRS\n{\n    \/* Note that the permissions flags are currently not respected. *\/\n    \/* Keep the sections here sorted from lowest memory address to largest; crosvm\n     * has a sanity check that expects the section with the lowest address to come\n     * first.\n     *\/\n    \/* Executable text. *\/\n    text    PT_LOAD FLAGS(4 + 1); \/* PF_R + PF_X *\/\n    \/* Read-only data. *\/\n    rodata  PT_LOAD FLAGS(4); \/* PF_R *\/\n    \/* Initialized read-write data. *\/\n    data    PT_LOAD FLAGS(4 + 2); \/* PF_R + PF_W *\/\n    \/* Uninitialized read-write data. *\/\n    bss     PT_LOAD FLAGS(4 + 2); \/* PF_R + PF_W *\/\n    \/* Special sections for SEV-SNP. *\/\n    cpuid   PT_LOAD FLAGS(1 << 23);\n    secrets PT_LOAD FLAGS(1 << 24);\n}\n\nSECTIONS {\n    .boot 0x200000 : {\n        ram_min = .;\n        *(.boot)\n    } : text\n\n    data_start = .;\n    text_start = .;\n\n    .text : {\n        *(.text .text.*)\n    } : text\n\n    text_end = .;\n\n    .rodata : {\n        *(.rodata .rodata.*)\n    } : rodata\n\n    .data : {\n        *(.data .data.*)\n    } : data\n\n    data_end = .;\n\n    .bss : {\n        bss_start = .;\n        *(.bss .bss.*)\n        bss_size = . - bss_start;\n    } : bss\n\n    \/* Stack grows down, so stack_start is the upper address in memory. *\/\n    .stack (NOLOAD) : ALIGN(4K) {\n        . += 512K;\n    } : bss\n    stack_start = .;\n\n    .cpuid (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : cpuid\n\n    .secrets (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : secrets\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"51df685350b1ccc9a16974230a18805e7259c180","subject":"Fix bug with linker script","message":"Fix bug with linker script\n","repos":"batitous\/klipos,batitous\/klipos,batitous\/klipos","old_file":"klipos\/hw\/mcu\/lpc15xx\/lpc1549.ld","new_file":"klipos\/hw\/mcu\/lpc15xx\/lpc1549.ld","new_contents":"\/*\n * generic gcc linker script for LPC1549\n * Taken from Kamal Mostafa <kamal@whence.com>.\n *\n * License: Public Domain\n *\/\n\nMEMORY\n{\n    FLASH (rx)    : ORIGIN = 0x00000000, LENGTH = 256K \n    RAM (rwx)     : ORIGIN = 0x02000000, LENGTH = 16K\n    RAM1 (rwx)    : ORIGIN = 0x02004000, LENGTH = 16K\n    RAM2 (rwx)    : ORIGIN = 0x02008000, LENGTH = 4K\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.isr_vector))\n        KEEP(*(.after_vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH\n\n    .data : \n    {\n        __stack_start__ = .; \/* start of the stack section *\/\n        KEEP(*(.stack))\n         . = ALIGN(4);\n        __stack_end__ = .;   \/* end of the stack section *\/\n\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > RAM AT > FLASH\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > RAM\n\n}\n","old_contents":"\/*\n * generic gcc linker script for LPC1549\n * Taken from Kamal Mostafa <kamal@whence.com>.\n *\n * License: Public Domain\n *\/\n\nMEMORY\n{\n    FLASH (rx)    : ORIGIN = 0x00000000, LENGTH = 256K \n    RAM (rwx)     : ORIGIN = 0x02000000, LENGTH = 16K\n    RAM1 (rwx)    : ORIGIN = 0x02004000, LENGTH = 16K\n    RAM2 (rwx)    : ORIGIN = 0x02008000, LENGTH = 4K\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.isr_vector))\n        KEEP(*(.after_vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH\n\n    .data : AT (ADDR(.text) + SIZEOF(.text))\n    {\n        __stack_start__ = .; \/* start of the stack section *\/\n        KEEP(*(.stack))\n         . = ALIGN(4);\n        __stack_end__ = .;   \/* end of the stack section *\/\n\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > RAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > RAM\n\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"07e026fc0ab2f4cf23f77c499ccc14319315cd0e","subject":"linker: 4k page align text segment","message":"linker: 4k page align text segment\n","repos":"AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,ingve\/IncludeOS,ingve\/IncludeOS,AndreasAakesson\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,ingve\/IncludeOS,alfred-bratterud\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,ingve\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,ingve\/IncludeOS,mnordsletten\/IncludeOS,AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,alfred-bratterud\/IncludeOS","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0xA00000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  . = _ELF_START_;\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n\n  .text ALIGN(0x1000):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x1000) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  .config ALIGN(0x8) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","old_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0xA00000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  . = _ELF_START_;\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n\n  .text ALIGN(0x10):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x10) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  .config ALIGN(0x8) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"63590a9526e8c36312488158e2ed15d32db5d2c2","subject":"update ld add *(.sdk.version)","message":"update ld add *(.sdk.version)\n","repos":"Lan-Hekary\/Arduino,NullMedia\/Arduino,Links2004\/Arduino,Cloudino\/Cloudino-Arduino-IDE,edog1973\/Arduino,wemos\/Arduino,jes\/Arduino,Links2004\/Arduino,lrmoreno007\/Arduino,NullMedia\/Arduino,NullMedia\/Arduino,NextDevBoard\/Arduino,NextDevBoard\/Arduino,Cloudino\/Cloudino-Arduino-IDE,hallard\/Arduino,martinayotte\/ESP8266-Arduino,hallard\/Arduino,KaloNK\/Arduino,NextDevBoard\/Arduino,Cloudino\/Arduino,Adam5Wu\/Arduino,sticilface\/Arduino,Juppit\/Arduino,lrmoreno007\/Arduino,Adam5Wu\/Arduino,Adam5Wu\/Arduino,hallard\/Arduino,NullMedia\/Arduino,sticilface\/Arduino,quertenmont\/Arduino,chrisfraser\/Arduino,esp8266\/Arduino,chrisfraser\/Arduino,NextDevBoard\/Arduino,chrisfraser\/Arduino,me-no-dev\/Arduino,CanTireInnovations\/Arduino,jes\/Arduino,sticilface\/Arduino,Links2004\/Arduino,gguuss\/Arduino,hallard\/Arduino,toastedcode\/esp8266-Arduino,Cloudino\/Arduino,lrmoreno007\/Arduino,Juppit\/Arduino,martinayotte\/ESP8266-Arduino,Cloudino\/Arduino,me-no-dev\/Arduino,CanTireInnovations\/Arduino,gguuss\/Arduino,Links2004\/Arduino,esp8266\/Arduino,martinayotte\/ESP8266-Arduino,gguuss\/Arduino,chrisfraser\/Arduino,CanTireInnovations\/Arduino,me-no-dev\/Arduino,CanTireInnovations\/Arduino,CanTireInnovations\/Arduino,Adam5Wu\/Arduino,quertenmont\/Arduino,Adam5Wu\/Arduino,hallard\/Arduino,lrmoreno007\/Arduino,wemos\/Arduino,gguuss\/Arduino,KaloNK\/Arduino,esp8266\/Arduino,esp8266\/Arduino,sticilface\/Arduino,me-no-dev\/Arduino,Cloudino\/Cloudino-Arduino-IDE,lrmoreno007\/Arduino,gguuss\/Arduino,quertenmont\/Arduino,Cloudino\/Cloudino-Arduino-IDE,jes\/Arduino,Cloudino\/Arduino,Cloudino\/Cloudino-Arduino-IDE,KaloNK\/Arduino,martinayotte\/ESP8266-Arduino,NullMedia\/Arduino,Cloudino\/Arduino,toastedcode\/esp8266-Arduino,Lan-Hekary\/Arduino,toastedcode\/esp8266-Arduino,jes\/Arduino,edog1973\/Arduino,quertenmont\/Arduino,wemos\/Arduino,wemos\/Arduino,CanTireInnovations\/Arduino,Lan-Hekary\/Arduino,martinayotte\/ESP8266-Arduino,KaloNK\/Arduino,Cloudino\/Cloudino-Arduino-IDE,Lan-Hekary\/Arduino,esp8266\/Arduino,Juppit\/Arduino,CanTireInnovations\/Arduino,Links2004\/Arduino,edog1973\/Arduino,KaloNK\/Arduino,Cloudino\/Cloudino-Arduino-IDE,Cloudino\/Arduino,sticilface\/Arduino,Juppit\/Arduino,edog1973\/Arduino,chrisfraser\/Arduino,jes\/Arduino,Lan-Hekary\/Arduino,me-no-dev\/Arduino,Juppit\/Arduino,wemos\/Arduino,edog1973\/Arduino,NextDevBoard\/Arduino,toastedcode\/esp8266-Arduino,quertenmont\/Arduino,toastedcode\/esp8266-Arduino,Cloudino\/Arduino","old_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *spiffs*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *core_esp8266_*.o(.literal*, .text*)\n    *spiffs*.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"563d456f1988dc66399a4f9a31b3ebbb16776ad6","subject":"Now linker script create low and high sections","message":"Now linker script create low and high sections\n","repos":"akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix","old_file":"linker.ld","new_file":"linker.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\n\nSECTIONS\n{\n    . = 0x00100000;\n    .setup ALIGN (0x1000) :\n    {\n        __start_setup = .;\n        *(.setup)\n        *(.setup.data)\n        __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    . += 0xc0000000;\n    .text ALIGN (0x1000) :\n    {\n        *(.text)\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n    }\n\n    .rodata ALIGN (0x1000) :\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        *(.data)\n    }\n\n    .bss :\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\n\nSECTIONS\n{\n    . = 0x00100000;\n    .text ALIGN (0x1000) :\n    {\n    __start_cs_kernel = .;\n        *(.text)\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n    __end_cs_kernel = .;\n    }\n\n    .rodata ALIGN (0x1000) :\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        *(.data)\n    }\n\n    .bss :\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"c0424276648e54776cfc86a38c0a60082882384d","subject":"X1000: x1000_ram.lds: \u4fee\u590d\u8c03\u8bd5\u65f6\u5d29\u6e83\u7684\u95ee\u9898\/Fix crash when debugging.","message":"X1000: x1000_ram.lds: \u4fee\u590d\u8c03\u8bd5\u65f6\u5d29\u6e83\u7684\u95ee\u9898\/Fix crash when debugging.\n\n\u5f53ELF\u6587\u4ef6\u5305\u542b\u5f88\u591agnu_extab*\u5f00\u5934\u7684section\u65f6(>100)\uff0c\u4f1a\u5bfc\u81f4GDB\u5728\u52a0\u8f7d\u64cd\u4f5c\n\u65f6\u5d29\u6e83\u3002\u901a\u8fc7\u521b\u5efa\u4e00\u4e2asection\u6765\u5bf9\u4ee5\u8be5\u540d\u79f0\u5f00\u5934\u7684\u6240\u6709section\u8fdb\u884c\u5206\u7ec4\u53ef\u4ee5\n\u89e3\u51b3\u8be5\u95ee\u9898\u3002\n\nWhen ELF contains many sectios(>100) starting with name gnu_extab*,\nwill causing GDB to crash on load action. Solving the problem by\ncreating a section to group all sections which begin with that name.\n\nSigned-off-by: Zhou Yanjie <17015b8cdc0ca77b55f0bd985068d713e2de996d@zoho.com>\n","repos":"FlyLu\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,weety\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,weety\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread","old_file":"bsp\/x1000\/x1000_ram.lds","new_file":"bsp\/x1000\/x1000_ram.lds","new_contents":"\/*\n * File      : x1000_ram.lds\n * COPYRIGHT (C) 2015, RT-Thread Development Team\n *\n *  This program is free software; you can redistribute it and\/or modify\n *  it under the terms of the GNU General Public License as published by\n *  the Free Software Foundation; either version 2 of the License, or\n *  (at your option) any later version.\n *\n *  This program is distributed in the hope that it will be useful,\n *  but WITHOUT ANY WARRANTY; without even the implied warranty of\n *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *  GNU General Public License for more details.\n *\n *  You should have received a copy of the GNU General Public License along\n *  with this program; if not, write to the Free Software Foundation, Inc.,\n *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n *\n * Change Logs:\n * 2015-12-12     bernard       first version\n *\/\n\nOUTPUT_FORMAT(\"elf32-tradlittlemips\", \"elf32-tradlittlemips\", \"elf32-tradlittlemips\")\nOUTPUT_ARCH(mips)\n\nMEMORY\n{\n   \/* 16M SDRAM *\/\n   DRAM : ORIGIN = 0x80800000, LENGTH = 0x01800000\n   \/* 16K SRAM  *\/\n   IRAM : ORIGIN = 0x80000000, LENGTH = 0x00004000\n}\n\nENTRY(_start)\nSECTIONS\n{\n    .start :\n    {\n        *(.start);\n    } > DRAM\n\n    . = ALIGN(4);\n\n    .text : \n    {\n        *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n        *(.text.exit .text.exit.*)\n        *(.text.startup .text.startup.*)\n        *(.text.hot .text.hot.*)\n        *(.text .stub .text.* .gnu.linkonce.t.*)\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n     \n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n\n        . = ALIGN(4);\n        _etext = .;\n    } > DRAM\n\n    .eh_frame_hdr : \n    { \n         *(.eh_frame_hdr) \n         *(.eh_frame_entry)\n         *(.eh_frame_entry.*)\n    } > DRAM\n    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > DRAM\n\n    . = ALIGN(4);\n    .gnu_extab :\n    {\n        *(.gnu_extab.*)\n    } > DRAM\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    } > DRAM\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    } > DRAM\n\n    .data : \n    {\n     *(.data)\n     *(.data.*)\n    \n     *(.data1)\n     *(.data1.*)\n     \n     . = ALIGN(8);\n     _gp = ABSOLUTE(.);     \/* Base of small data *\/\n     \n     *(.sdata)\n     *(.sdata.*)\n    } > DRAM\n\n    . = ALIGN(4);\n    _iramat = .;\n\n    .iram : AT(_iramat)\n    {\n        _iramstart = .;\n        *(.vectors.1);\n        . = 0x100;\n        *(.vectors.2);\n        . = 0x180;\n        *(.vectors.3);\n        . = 0x200;\n        *(.vectors.4);\n        *(.vectors);\n\n        *(.icode);\n        *(.irodata);\n        *(.idata);\n        KEEP(*(.vectors*))\n        _iramend = .;\n    } > IRAM\n    _iramcopy = LOADADDR(.iram);\n\n    .sbss : \n    {\n    __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.dynsbss)\n        *(.scommon)\n    } > DRAM\n\n    .bss :\n    {\n        *(.bss)\n        *(.bss.*)\n        *(.dynbss)\n        *(COMMON)\n    __bss_end = .;\n    } > DRAM\n    \n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * File      : x1000_ram.lds\n * COPYRIGHT (C) 2015, RT-Thread Development Team\n *\n *  This program is free software; you can redistribute it and\/or modify\n *  it under the terms of the GNU General Public License as published by\n *  the Free Software Foundation; either version 2 of the License, or\n *  (at your option) any later version.\n *\n *  This program is distributed in the hope that it will be useful,\n *  but WITHOUT ANY WARRANTY; without even the implied warranty of\n *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *  GNU General Public License for more details.\n *\n *  You should have received a copy of the GNU General Public License along\n *  with this program; if not, write to the Free Software Foundation, Inc.,\n *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n *\n * Change Logs:\n * 2015-12-12     bernard       first version\n *\/\n\nOUTPUT_FORMAT(\"elf32-tradlittlemips\", \"elf32-tradlittlemips\", \"elf32-tradlittlemips\")\nOUTPUT_ARCH(mips)\n\nMEMORY\n{\n   \/* 16M SDRAM *\/\n   DRAM : ORIGIN = 0x80800000, LENGTH = 0x01800000\n   \/* 16K SRAM  *\/\n   IRAM : ORIGIN = 0x80000000, LENGTH = 0x00004000\n}\n\nENTRY(_start)\nSECTIONS\n{\n    .start :\n    {\n        *(.start);\n    } > DRAM\n\n    . = ALIGN(4);\n\n    .text : \n    {\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n     \n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n\n        . = ALIGN(4);\n        _etext = .;\n    } > DRAM\n\n    .eh_frame_hdr : \n    { \n         *(.eh_frame_hdr) \n         *(.eh_frame_entry)\n         *(.eh_frame_entry.*)\n    } > DRAM\n    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > DRAM\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    } > DRAM\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    } > DRAM\n\n    .data : \n    {\n     *(.data)\n     *(.data.*)\n    \n     *(.data1)\n     *(.data1.*)\n     \n     . = ALIGN(8);\n     _gp = ABSOLUTE(.);     \/* Base of small data *\/\n     \n     *(.sdata)\n     *(.sdata.*)\n    } > DRAM\n\n    . = ALIGN(4);\n    _iramat = .;\n\n    .iram : AT(_iramat)\n    {\n        _iramstart = .;\n        *(.vectors.1);\n        . = 0x100;\n        *(.vectors.2);\n        . = 0x180;\n        *(.vectors.3);\n        . = 0x200;\n        *(.vectors.4);\n        *(.vectors);\n\n        *(.icode);\n        *(.irodata);\n        *(.idata);\n        KEEP(*(.vectors*))\n        _iramend = .;\n    } > IRAM\n    _iramcopy = LOADADDR(.iram);\n\n    .sbss : \n    {\n    __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.dynsbss)\n        *(.scommon)\n    } > DRAM\n\n    .bss :\n    {\n        *(.bss)\n        *(.bss.*)\n        *(.dynbss)\n        *(COMMON)\n    __bss_end = .;\n    } > DRAM\n    \n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ddc25b4bdf05f83c74e3b54ae8e1a38b7634bdf5","subject":"linker: aarch32: simplify memory region generation","message":"linker: aarch32: simplify memory region generation\n\nSimplify the linker script by using the helper macros introduced in\n<linker\/devicetree_regions.h>. The conditional checks on the Kconfig\nsymbols are discarded as their default values are typically set via\nthe status=\"okay\" property of the nodes, and hence the behaviour doesn't\nchange.\n\nSigned-off-by: Jordan Yates <d74a90e280bbad1cc3646781a4e234b467b60fe1@data61.csiro.au>\n","repos":"zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/devicetree_regions.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n#define _DATA_IN_ROM __data_rom_start\n#else\n#define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_HAS_TI_CCFG\n#define CCFG_SIZE 88\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\tCCFG_SIZE)\n#define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_HAS_TI_CCFG\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    DT_REGION_FROM_NODE_STATUS_OKAY(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n    \/* STM32 Core Coupled Memory *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(CCM, rw, DT_CHOSEN(zephyr_ccm))\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* STM32 alternate RAM configurations *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(SDRAM1, rw, DT_NODELABEL(sdram1))\n    DT_REGION_FROM_NODE_STATUS_OKAY(SDRAM2, rw, DT_NODELABEL(sdram2))\n    DT_REGION_FROM_NODE_STATUS_OKAY(BACKUP_SRAM, rw, DT_NODELABEL(backup_sram))\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_HAS_TI_CCFG\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(_TI_CCFG_SECTION_NAME))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n#define _DATA_IN_ROM __data_rom_start\n#else\n#define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_HAS_TI_CCFG\n#define CCFG_SIZE 88\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\tCCFG_SIZE)\n#define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay)\n#define CCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ccm))\n#define CCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ccm))\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\n#define ITCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_itcm))\n#define ITCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_itcm))\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\n#define DTCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm))\n#define DTCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm))\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_HAS_TI_CCFG\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay)\n    CCM                   (rw) : ORIGIN = CCM_ADDR, LENGTH = CCM_SIZE\n#endif\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\n    ITCM                  (rw) : ORIGIN = ITCM_ADDR, LENGTH = ITCM_SIZE\n#endif\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\n    DTCM                  (rw) : ORIGIN = DTCM_ADDR, LENGTH = DTCM_SIZE\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n#ifdef CONFIG_MEMC_STM32_SDRAM\n#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay)\n    SDRAM1                (rw) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram1)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram1))\n#endif\n#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay)\n    SDRAM2                (rw) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram2)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram2))\n#endif\n#endif\n#ifdef CONFIG_STM32_BACKUP_SRAM\n    BACKUP_SRAM           (rw) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(backup_sram)), LENGTH = DT_REG_SIZE(DT_NODELABEL(backup_sram))\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_HAS_TI_CCFG\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(_TI_CCFG_SECTION_NAME))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e94551e2b7ab79c2b41d6e30a7489167689d7b9d","subject":"arch: arm: cortex-m: properly name ROM sections in the linker","message":"arch: arm: cortex-m: properly name ROM sections in the linker\n\nThis commit does the following:\n- renames the 'text' ROM section to 'rom_start', to reflect\n  that this section is the first section of the image.\n- renames the 'TEXT_SECTION_NAME_2' section to 'text', since\n  that section (whose start is pointed by _image_text_start)\n  holds the entire image text section.\n\nThe commit removes the confusion by having multiple ROM sections\nnamed as 'text' in ARM Cortex-M builds.\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\nSigned-off-by: \u00d8yvind R\u00f8nningstad <5f9e1eedbdafebd99226f1498f634e1047455d88@nordicsemi.no>\n","repos":"zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n#define _DATA_IN_ROM __data_rom_start\n#else\n#define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_TI_CCFG_PRESENT\n#define CCFG_SIZE 88\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\tCCFG_SIZE)\n#define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n#ifdef DT_DTCM_BASE_ADDRESS\n    DTCM                  (rw) : ORIGIN = DT_DTCM_BASE_ADDRESS, LENGTH = DT_DTCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-text-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef DT_DTCM_BASE_ADDRESS\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_bss_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_data_end = .;\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif \/* DT_DTCM_BASE_ADDRESS *\/\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n#define _DATA_IN_ROM __data_rom_start\n#else\n#define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_TI_CCFG_PRESENT\n#define CCFG_SIZE 88\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\tCCFG_SIZE)\n#define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n#ifdef DT_DTCM_BASE_ADDRESS\n    DTCM                  (rw) : ORIGIN = DT_DTCM_BASE_ADDRESS, LENGTH = DT_DTCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-text-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef DT_DTCM_BASE_ADDRESS\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_bss_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t} GROUP_LINK_IN(DTCM)\n\n\t__dtcm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_data_end = .;\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif \/* DT_DTCM_BASE_ADDRESS *\/\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"60caed8d549608e972710f9045c0a9e7d973ec86","subject":"soc: esp32c3: Fix symbol placement in linker script","message":"soc: esp32c3: Fix symbol placement in linker script\n\nCreating static libraries for drivers moves some symbols out of IRAM.\nThis change fixes it.\n\nSigned-off-by: Shubham Kulkarni <1478dde7897089bf180c3c690a61b19b869e8abd@espressif.com>\n","repos":"galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/riscv\/esp32c3\/linker.ld","new_file":"soc\/riscv\/esp32c3\/linker.ld","new_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32c3 platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define IRAM_REGION  iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\n#define SRAM_IRAM_START     0x4037C000\n#define SRAM_DRAM_START     0x3FC7C000\n#define ICACHE_SIZE         0x4000 \/* ICache size is fixed to 16KB on ESP32-C3 *\/\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n\/* Global symbols required for espressif hal build *\/\nMEMORY\n{\n  iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n  irom0_0_seg(RX): org = 0x42000020, len = 0x8000000-0x20\n\n  drom0_0_seg (R) : org = 0x3C000020, len = 0x8000000-0x20\n  dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE\n\n  rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000\n\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(__start)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } > rtc_iram_seg\n\n  \/* This section is required to skip rtc.text area because the text and\n   * data segments reflect the same address space on different buses.\n   *\/\n  .rtc.dummy (NOLOAD):\n  {\n    . = SIZEOF(.rtc.text);\n  } > rtc_iram_seg\n\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n\n  .iram0.text : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _iram_start = ABSOLUTE(.);\n    _iram_text_start = ABSOLUTE(.);\n    _init_start = ABSOLUTE(.);\n    KEEP(*(.exception_vectors.text));\n    . = ALIGN(256);\n\n    KEEP(*(.exception.entry*)); \/* contains __irq_wrapper *\/\n    *(.exception.other*)\n    . = ALIGN(4);\n\n    . = ALIGN (4);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    . = ALIGN(4);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    . = ALIGN(4);\n    _init_end = ABSOLUTE(.);\n    _iram_text_end = ABSOLUTE(.);   *(.srodata)\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  \/**\n   * This section is required to skip .iram0.text area because iram0_0_seg and\n   * dram0_0_seg reflect the same address space on different buses.\n   *\/\n  .dram0.dummy (NOLOAD):\n  {\n    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } > dram0_0_seg\n\n#include <linker\/common-ram.ld>\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    __global_pointer$ = . + 0x800;\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    _end = .;\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  \/* Shared RAM *\/\n  dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  .flash.text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  .flash_rodata_dummy (NOLOAD):\n  {\n    . = SIZEOF(.flash.text);\n    . = ALIGN(0x10000) + 0x20;\n    _rodata_reserved_start = .;\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  .flash.rodata : ALIGN(0x10)\n  {\n    _rodata_start = ABSOLUTE(.);\n    _image_rodata_start = .;\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    *(.rodata_desc .rodata_desc.*)               \/* Should be the first.  App version info.        DO NOT PUT ANYTHING BEFORE IT! *\/\n    *(.rodata_custom_desc .rodata_custom_desc.*) \/* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! *\/\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*\n     * C++ constructor and destructor tables\n     * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.\n     *\n     * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.\n     * But the init_priority sections will be sorted for iteration in ascending order during startup.\n     * The rest of the init_array sections is sorted for iteration in descending order during startup, however.\n     * Hence a different section is generated for the init_priority functions which is iterated in\n     * ascending order during startup. The corresponding code can be found in startup.c.\n     *\/\n    __init_priority_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))\n    __init_priority_array_end = ABSOLUTE(.);\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/* C++ exception handlers table: *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_rodata_end = .;\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    *(.srodata)\n    *(\".srodata.*\")\n    *(.rodata)\n    *(.rodata.*)\n    _thread_local_end = ABSOLUTE(.);\n    _rodata_reserved_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n    KEEP(*(.riscv.attributes))\n    KEEP(*(.gnu.attributes))\n\t}\n}\n","old_contents":"\/*\n * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the esp32c3 platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define IRAM_REGION  iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\n#define SRAM_IRAM_START     0x4037C000\n#define SRAM_DRAM_START     0x3FC7C000\n#define ICACHE_SIZE         0x4000 \/* ICache size is fixed to 16KB on ESP32-C3 *\/\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n\/* Global symbols required for espressif hal build *\/\nMEMORY\n{\n  iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n  irom0_0_seg(RX): org = 0x42000020, len = 0x8000000-0x20\n\n  drom0_0_seg (R) : org = 0x3C000020, len = 0x8000000-0x20\n  dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE\n\n  rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000\n\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(__start)\n\n_rom_store_table = 0;\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } > rtc_iram_seg\n\n  \/* This section is required to skip rtc.text area because the text and\n   * data segments reflect the same address space on different buses.\n   *\/\n  .rtc.dummy (NOLOAD):\n  {\n    . = SIZEOF(.rtc.text);\n  } > rtc_iram_seg\n\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_iram_seg\n\n  .iram0.text : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _iram_start = ABSOLUTE(.);\n    _iram_text_start = ABSOLUTE(.);\n    _init_start = ABSOLUTE(.);\n    KEEP(*(.exception_vectors.text));\n    . = ALIGN(256);\n\n    KEEP(*(.exception.entry*)); \/* contains __irq_wrapper *\/\n    *(.exception.other*)\n    . = ALIGN(4);\n\n    . = ALIGN (4);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    . = ALIGN(4);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:esp32c3_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    . = ALIGN(4);\n    _init_end = ABSOLUTE(.);\n    _iram_text_end = ABSOLUTE(.);   *(.srodata)\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  \/**\n   * This section is required to skip .iram0.text area because iram0_0_seg and\n   * dram0_0_seg reflect the same address space on different buses.\n   *\/\n  .dram0.dummy (NOLOAD):\n  {\n    . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;\n  } > dram0_0_seg\n\n#include <linker\/common-ram.ld>\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    __global_pointer$ = . + 0x800;\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    _end = .;\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  \/* Shared RAM *\/\n  dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    __bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    __bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  .flash.text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  .flash_rodata_dummy (NOLOAD):\n  {\n    . = SIZEOF(.flash.text);\n    . = ALIGN(0x10000) + 0x20;\n    _rodata_reserved_start = .;\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n  .flash.rodata : ALIGN(0x10)\n  {\n    _rodata_start = ABSOLUTE(.);\n    _image_rodata_start = .;\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    *(.rodata_desc .rodata_desc.*)               \/* Should be the first.  App version info.        DO NOT PUT ANYTHING BEFORE IT! *\/\n    *(.rodata_custom_desc .rodata_custom_desc.*) \/* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! *\/\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*\n     * C++ constructor and destructor tables\n     * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.\n     *\n     * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.\n     * But the init_priority sections will be sorted for iteration in ascending order during startup.\n     * The rest of the init_array sections is sorted for iteration in descending order during startup, however.\n     * Hence a different section is generated for the init_priority functions which is iterated in\n     * ascending order during startup. The corresponding code can be found in startup.c.\n     *\/\n    __init_priority_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))\n    __init_priority_array_end = ABSOLUTE(.);\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/* C++ exception handlers table: *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_rodata_end = .;\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    *(.srodata)\n    *(\".srodata.*\")\n    *(.rodata)\n    *(.rodata.*)\n    _thread_local_end = ABSOLUTE(.);\n    _rodata_reserved_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n    KEEP(*(.riscv.attributes))\n    KEEP(*(.gnu.attributes))\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a5841373ef85527a02aff523b244097912954f42","subject":"Updated","message":"Updated","repos":"Darkrifts\/UBos,Darkrifts\/UBos","old_file":"linker.ld","new_file":"linker.ld","new_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\nSECTIONS\n{\n\t. = 1M;\n\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\t\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t}\n\n}\n","old_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 1M;\n\n\t\/* First put the multiboot header, as it is required to be put very early\n\t   early in the image or the bootloader won't recognize the file format.\n\t   Next we'll put the .text section. *\/\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t}\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"be68124d9aca4e0259ebf75943960470b4bdeaff","subject":"delete STM32F4xxxG.ld linker script","message":"delete STM32F4xxxG.ld linker script","repos":"CezaryGapinski\/distortos,jasmin-j\/distortos,CezaryGapinski\/distortos,CezaryGapinski\/distortos,DISTORTEC\/distortos,DISTORTEC\/distortos,CezaryGapinski\/distortos,jasmin-j\/distortos,jasmin-j\/distortos,DISTORTEC\/distortos,CezaryGapinski\/distortos,jasmin-j\/distortos,jasmin-j\/distortos,DISTORTEC\/distortos","old_file":"source\/chip\/STMicroelectronics\/STM32F4\/STM32F4xxxG.ld","new_file":"source\/chip\/STMicroelectronics\/STM32F4\/STM32F4xxxG.ld","new_contents":"","old_contents":"\/**\n * \\file\n * \\brief Linker script for STM32F4xxxG chip:\n * - 1MB flash;\n * - 112kB SRAM1;\n * - 16kB SRAM2;\n * - 64kB CCM;\n * - 4kB BKPSRAM;\n *\n * \\author Copyright (C) 2014-2015 Kamil Szczygiel http:\/\/www.distortec.com http:\/\/www.freddiechopin.info\n *\n * \\par License\n * This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of the MPL was not\n * distributed with this file, You can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/.\n *\n * \\date 2015-08-27\n *\/\n\nSEARCH_DIR(.);\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| available memories definitions\n+---------------------------------------------------------------------------------------------------------------------*\/\n\nMEMORY\n{\n\trom (rx)\t\t: org = 0x08000000, len = 1M\n\tram (rwx)\t\t: org = 0x20000000, len = 112k\n\tsram2 (rwx)\t\t: org = 0x2001C000, len = 16k\n\tccm (rw)\t\t: org = 0x10000000, len = 64k\n\tbkpsram (rwx)\t: org = 0x40024000, len = 4k\n}\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| stacks sizes\n+---------------------------------------------------------------------------------------------------------------------*\/\n\n\/* Handler mode (core exceptions \/ interrupts) can use only main stack *\/\n\/* Thread mode can use main stack (default) or process stack - selected in CONTROL special register *\/\n\n__main_stack_size = 2k;\n__process_stack_size = 2k;\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| include generic linker script\n+---------------------------------------------------------------------------------------------------------------------*\/\n\nINCLUDE ARMv7-M.ld\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"08531e4cfcb37faf778b94b628a00298e4625bc3","subject":"Create separate sections with different permissions.","message":"Create separate sections with different permissions.\n","repos":"project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak,project-oak\/oak","old_file":"experimental\/oak_baremetal_app_crosvm\/layout.ld","new_file":"experimental\/oak_baremetal_app_crosvm\/layout.ld","new_contents":"\/*\n * Copyright 2022 The Project Oak Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n*\/\n\nENTRY(_start)\n\nPHDRS\n{\n    \/* Note that the permissions flags are currently not respected. *\/\n    \/* Keep the sections here sorted from lowest memory address to largest; crosvm\n     * has a sanity check that expects the section with the lowest address to come\n     * first.\n     *\/\n    \/* Executable text. *\/\n    text    PT_LOAD FLAGS(4 + 1); \/* PF_R + PF_X *\/\n    \/* Read-only data. *\/\n    rodata  PT_LOAD FLAGS(4); \/* PF_R *\/\n    \/* Initialized read-write data. *\/\n    data    PT_LOAD FLAGS(4 + 2); \/* PF_R + PF_W *\/\n    \/* Uninitialized read-write data. *\/\n    bss     PT_LOAD FLAGS(4 + 2); \/* PF_R + PF_W *\/\n    \/* Special sections for SEV-SNP. *\/\n    cpuid   PT_LOAD FLAGS(1 << 23);\n    secrets PT_LOAD FLAGS(1 << 24);\n}\n\nSECTIONS {\n    .boot 0x200000 : {\n        ram_min = .;\n        *(.boot)\n    } : text\n\n    data_start = .;\n    text_start = .;\n\n    .text : {\n        *(.text .text.*)\n    } : text\n\n    text_end = .;\n\n    .rodata : {\n        *(.rodata .rodata.*)\n    } : rodata\n\n    .data : {\n        *(.data .data.*)\n    } : data\n\n    data_end = .;\n\n    .bss : {\n        bss_start = .;\n        *(.bss .bss.*)\n        bss_size = . - bss_start;\n    } : bss\n\n    \/* Stack grows down, so stack_start is the upper address in memory. *\/\n    .stack (NOLOAD) : ALIGN(4K) {\n        . += 512K;\n    } : bss\n    stack_start = .;\n\n    .cpuid (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : cpuid\n\n    .secrets (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : secrets\n}\n","old_contents":"\/*\n * Copyright 2022 The Project Oak Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n*\/\n\nENTRY(_start)\n\nPHDRS\n{\n    ram     PT_LOAD FLAGS(5);\n    cpuid   PT_LOAD FLAGS(1 << 23);\n    secrets PT_LOAD FLAGS(1 << 24);\n}\n\nSECTIONS {\n    .boot 0x200000 : {\n        ram_min = .;\n        *(.boot)\n    } : ram\n\n    data_start = .;\n    text_start = .;\n\n    .text : {\n        *(.text .text.*)\n    } : ram\n\n    text_end = .;\n\n    .rodata : {\n        *(.rodata .rodata.*)\n    } : ram\n\n    .data : {\n        *(.data .data.*)\n    } : ram\n\n    data_end = .;\n\n    .bss : {\n        bss_start = .;\n        *(.bss .bss.*)\n        bss_size = . - bss_start;\n    } : ram\n\n    \/* Stack grows down, so stack_start is the upper address in memory. *\/\n    .stack (NOLOAD) : ALIGN(4K) {\n        . += 512K;\n    } : ram\n    stack_start = .;\n\n    .cpuid (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : cpuid\n\n    .secrets (NOLOAD) : ALIGN(2M) {\n        . += 4K;\n    } : secrets\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"21ee595f9b60f9276113779fa362aa50a934f27a","subject":"examples\/nucleo-f303re\/usart: Fix script.ld.","message":"examples\/nucleo-f303re\/usart: Fix script.ld.\n","repos":"ziutek\/emgo,ziutek\/emgo,ziutek\/emgo,ziutek\/emgo","old_file":"egpath\/src\/stm32\/examples\/nucleo-f303re\/usart\/script.ld","new_file":"egpath\/src\/stm32\/examples\/nucleo-f303re\/usart\/script.ld","new_contents":"ISRStack  = 64 * 32;\nMainStack = 200 * 32;\nTaskStack = 0;\nMaxTasks  = 1;\n\nINCLUDE stm32\/f303xe\nINCLUDE stm32\/loadram\nINCLUDE noos-cortexm\n\n\/* \nTo run from RAM the BOOT0 pin must be high and nBOOT1 option bit must be\ncleared. To run from Flash change stm32\/loadram to stm32\/loadflash.\n*\/\n","old_contents":"ISRStack = 1024;\nMainStack = 1536;\nTaskStack = 0;\nMaxTasks = 1;\n\nINCLUDE stm32\/f030x4\nINCLUDE stm32\/loadflash\nINCLUDE noos-cortexm\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"10afcdce2e9a49d7a2e54999414e200abc816a3d","subject":"Hex\/Proficnc Cube Yellow: align firmware location in flash memory to be able to use the default bootloader","message":"Hex\/Proficnc Cube Yellow: align firmware location in flash memory to be able to use the default bootloader\n","repos":"krbeverx\/Firmware,acfloria\/Firmware,PX4\/Firmware,acfloria\/Firmware,PX4\/Firmware,acfloria\/Firmware,krbeverx\/Firmware,PX4\/Firmware,acfloria\/Firmware,krbeverx\/Firmware,PX4\/Firmware,acfloria\/Firmware,PX4\/Firmware,krbeverx\/Firmware,acfloria\/Firmware,PX4\/Firmware,acfloria\/Firmware,krbeverx\/Firmware,krbeverx\/Firmware,PX4\/Firmware,krbeverx\/Firmware","old_file":"boards\/hex\/cube-yellow\/nuttx-config\/scripts\/script.ld","new_file":"boards\/hex\/cube-yellow\/nuttx-config\/scripts\/script.ld","new_contents":"\/****************************************************************************\n * scripts\/script.ld\n *\n *   Copyright (C) 2016 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The STM32F765IIT6 has 2048 KiB of main FLASH memory.  This FLASH memory\n * can be accessed from either the AXIM interface at address 0x0800:0000 or\n * from the ITCM interface at address 0x0020:0000.\n *\n * Additional information, including the option bytes, is available at at\n * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).\n *\n * In the STM32F765IIT6, two different boot spaces can be selected through\n * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and\n * BOOT_ADD1 option bytes:\n *\n *   1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].\n *      ST programmed value: Flash on ITCM at 0x0020:0000\n *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].\n *      ST programmed value: System bootloader at 0x0010:0000\n *\n * NuttX does not modify these option byes.  On the unmodified NUCLEO-144\n * board, the BOOT0 pin is at ground so by default, the STM32F765IIT6 will\n * boot from address 0x0020:0000 in ITCM FLASH.\n *\n * The STM32F765IIT6 also has 512 KiB of data SRAM (in addition to ITCM SRAM).\n * SRAM is split up into three blocks:\n *\n *   1) 128 KiB of DTCM SRM beginning at address 0x2000:0000\n *   2) 368 KiB of SRAM1 beginning at address 0x2002:0000\n *   3)  16 KiB of SRAM2 beginning at address 0x2007:c000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0800:0000 address range.\n *\n * Bootloader reserves three 32K banks (2 Mbytes Flash memory single bank)\n * organization (256 bits read width)\n *\/\n\nMEMORY\n{\n    FLASH_ITCM (rx) : ORIGIN = 0x00218000, LENGTH = 1952K\n    FLASH_AXIM (rx) : ORIGIN = 0x08018000, LENGTH = 1952K\n\n    ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 16K\n    DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K\n    SRAM1    (rwx) : ORIGIN = 0x20020000, LENGTH = 368K\n    SRAM2    (rwx) : ORIGIN = 0x2007c000, LENGTH = 16K\n}\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nENTRY(_stext)\n\n\/*\n * Ensure that abort() is present in the final object.  The exception handling\n * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).\n *\/\nEXTERN(abort)\nEXTERN(_bootdelay_signature)\n\nSECTIONS\n{\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t. = ALIGN(32);\n\t\t\/*\n\t\tThis signature provides the bootloader with a way to delay booting\n\t\t*\/\n\t\t_bootdelay_signature = ABSOLUTE(.);\n\t\tFILL(0xffecc2925d7d05c5)\n\t\t. += 8;\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\n\t\t\/*\n\t\t * This is a hack to make the newlib libm __errno() call\n\t\t * use the NuttX get_errno_ptr() function.\n\t\t *\/\n\t\t__errno = get_errno_ptr;\n\t} > FLASH_AXIM\n\n\t\/*\n\t * Init functions (static constructors and the like)\n\t *\/\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\tKEEP(*(.init_array .init_array.*))\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH_AXIM\n\n\t\/*\n\t * Construction data for parameters.\n\t *\/\n\t__param ALIGN(4): {\n\t\t__param_start = ABSOLUTE(.);\n\t\tKEEP(*(__param*))\n\t\t__param_end = ABSOLUTE(.);\n\t} > FLASH_AXIM\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH_AXIM\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH_AXIM\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > SRAM1 AT > FLASH_AXIM\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > SRAM1\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.ramfunc : {\n\t\t_sramfuncs = .;\n\t\t*(.ramfunc  .ramfunc.*)\n\t\t. = ALIGN(4);\n\t\t_eramfuncs = .;\n\t} > ITCM_RAM AT > FLASH_AXIM\n\n\t_framfuncs = LOADADDR(.ramfunc);\n}\n","old_contents":"\/****************************************************************************\n * scripts\/script.ld\n *\n *   Copyright (C) 2016 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The STM32F765IIT6 has 2048 KiB of main FLASH memory.  This FLASH memory\n * can be accessed from either the AXIM interface at address 0x0800:0000 or\n * from the ITCM interface at address 0x0020:0000.\n *\n * Additional information, including the option bytes, is available at at\n * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).\n *\n * In the STM32F765IIT6, two different boot spaces can be selected through\n * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and\n * BOOT_ADD1 option bytes:\n *\n *   1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].\n *      ST programmed value: Flash on ITCM at 0x0020:0000\n *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].\n *      ST programmed value: System bootloader at 0x0010:0000\n *\n * NuttX does not modify these option byes.  On the unmodified NUCLEO-144\n * board, the BOOT0 pin is at ground so by default, the STM32F765IIT6 will\n * boot from address 0x0020:0000 in ITCM FLASH.\n *\n * The STM32F765IIT6 also has 512 KiB of data SRAM (in addition to ITCM SRAM).\n * SRAM is split up into three blocks:\n *\n *   1) 128 KiB of DTCM SRM beginning at address 0x2000:0000\n *   2) 368 KiB of SRAM1 beginning at address 0x2002:0000\n *   3)  16 KiB of SRAM2 beginning at address 0x2007:c000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0800:0000 address range.\n *\n * Bootloader reserves the first 32K bank (2 Mbytes Flash memory single bank)\n * organization (256 bits read width)\n *\/\n\nMEMORY\n{\n    FLASH_ITCM (rx) : ORIGIN = 0x00208000, LENGTH = 2016K\n    FLASH_AXIM (rx) : ORIGIN = 0x08008000, LENGTH = 2016K\n\n    ITCM_RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 16K\n    DTCM_RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K\n    SRAM1    (rwx) : ORIGIN = 0x20020000, LENGTH = 368K\n    SRAM2    (rwx) : ORIGIN = 0x2007c000, LENGTH = 16K\n}\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nENTRY(_stext)\n\n\/*\n * Ensure that abort() is present in the final object.  The exception handling\n * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).\n *\/\nEXTERN(abort)\nEXTERN(_bootdelay_signature)\n\nSECTIONS\n{\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t. = ALIGN(32);\n\t\t\/*\n\t\tThis signature provides the bootloader with a way to delay booting\n\t\t*\/\n\t\t_bootdelay_signature = ABSOLUTE(.);\n\t\tFILL(0xffecc2925d7d05c5)\n\t\t. += 8;\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\n\t\t\/*\n\t\t * This is a hack to make the newlib libm __errno() call\n\t\t * use the NuttX get_errno_ptr() function.\n\t\t *\/\n\t\t__errno = get_errno_ptr;\n\t} > FLASH_AXIM\n\n\t\/*\n\t * Init functions (static constructors and the like)\n\t *\/\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\tKEEP(*(.init_array .init_array.*))\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH_AXIM\n\n\t\/*\n\t * Construction data for parameters.\n\t *\/\n\t__param ALIGN(4): {\n\t\t__param_start = ABSOLUTE(.);\n\t\tKEEP(*(__param*))\n\t\t__param_end = ABSOLUTE(.);\n\t} > FLASH_AXIM\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH_AXIM\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH_AXIM\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > SRAM1 AT > FLASH_AXIM\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > SRAM1\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.ramfunc : {\n\t\t_sramfuncs = .;\n\t\t*(.ramfunc  .ramfunc.*)\n\t\t. = ALIGN(4);\n\t\t_eramfuncs = .;\n\t} > ITCM_RAM AT > FLASH_AXIM\n\n\t_framfuncs = LOADADDR(.ramfunc);\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"5e0119564f94aba38d9051cc7eb7494b2d99366e","subject":"[bsp][w60x] update GCC linker scripts","message":"[bsp][w60x] update GCC linker scripts\n","repos":"FlyLu\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,armink\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,armink\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread,FlyLu\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread","old_file":"bsp\/w60x\/drivers\/linker_scripts\/link.lds","new_file":"bsp\/w60x\/drivers\/linker_scripts\/link.lds","new_contents":"\/* Linker script to configure memory regions. \n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x8010100, LENGTH = 959K    \/* 960K-256B *\/\n    RAM (rw) : ORIGIN = 0x20000000, LENGTH = 0x28000  \/* 160K *\/\n    RAM2 (rw) : ORIGIN = 0x20028000, LENGTH = 0x14000 \/* 80K *\/\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n        \n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        __rtatcmdtab_start = .;\n        KEEP(*(RtAtCmdTab))\n        __rtatcmdtab_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        . = ALIGN(4);\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .stack_dummy (COPY):\n    {\n        . = ALIGN(8);\n        __stack_start__ = .;\n        *(.stack*)\n        __stack_end__ = .;\n    } > RAM\n\n    ._bss :\n    {\n        . = ALIGN(8);\n        __bss2_start__ = .;\n        __bss2_end__ = .;\n    } > RAM2\n\n    .bss __stack_end__ :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM \n\n    ASSERT(__StackTop <= 0x20028000, \"stack address error\")\n}\n","old_contents":"\/* Linker script to configure memory regions. \n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x8010100, LENGTH = 959K    \/* 960K-256B *\/\n    RAM (rw) : ORIGIN = 0x20000000, LENGTH = 0x28000  \/* 160K *\/\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n        \n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        __rtatcmdtab_start = .;\n        KEEP(*(RtAtCmdTab))\n        __rtatcmdtab_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        . = ALIGN(4);\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .stack_dummy (COPY):\n    {\n        . = ALIGN(8);\n        __stack_start__ = .;\n        *(.stack*)\n        __stack_end__ = .;\n    } > RAM\n\n    .bss __stack_end__ :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM \n\n    ASSERT(__StackTop <= 0x20028000, \"stack address error\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9087b12dfbe4267e9fd47e9e03c3b9d2142cdd8b","subject":"Using Linker file from QubeMX software","message":"Using Linker file from QubeMX software\n\nSigned-off-by: Christian Ege <a8fc705480847268478fb419154fd82cc75b19e4@gmail.com>\n","repos":"graugans\/stm32f072-template,graugans\/stm32f072-template","old_file":"linker\/stm32f072_linker.ld","new_file":"linker\/stm32f072_linker.ld","new_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F072RBTx Device with\n**                128KByte FLASH, 16KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n*****************************************************************************\n** @attention\n**\n** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6<\/center><\/h2>\n**\n** Redistribution and use in source and binary forms, with or without modification,\n** are permitted provided that the following conditions are met:\n**   1. Redistributions of source code must retain the above copyright notice,\n**      this list of conditions and the following disclaimer.\n**   2. Redistributions in binary form must reproduce the above copyright notice,\n**      this list of conditions and the following disclaimer in the documentation\n**      and\/or other materials provided with the distribution.\n**   3. Neither the name of Ac6 nor the names of its contributors\n**      may be used to endorse or promote products derived from this software\n**      without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20004000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 128K\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 16K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","old_contents":"\/******************************************************************************\n * This linker file was developed by Hussam Al-Hertani. Please use freely as\n * long as you leave this header in place. The author is not responsible for any\n * damage or liability that this file might cause.\n******************************************************************************\/\n \n\/* Entry Point *\/\nENTRY(Reset_Handler)\n \n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x20000 \/*128K*\/\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x04000 \/*16K*\/\n}\n \n\/* define stack size and heap size here *\/\nstack_size = 800;\n\n \n\/* define beginning and ending of stack *\/\n_stack_start = ORIGIN(RAM)+LENGTH(RAM);\n_stack_end = _stack_start - stack_size;\n_estack = _stack_start;\n \n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n \n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n \n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n \n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n \n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n \n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/*  Used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n \n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n \n    . = ALIGN(4);\n    . = _stack_end;\n    .stack :\n    {\n        . = . + stack_size;\n    } > RAM\n \n    \/* Remove information from the standard libraries *\/\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n \n    .ARM.attributes 0 : { *(.ARM.attributes) }\n    _end = . ;\n}","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ee001e0231f94e6a206fe1367ec8f4412c7c05e2","subject":"Move  large lib_a-svfwprintf to flash","message":"Move  large lib_a-svfwprintf to flash\n\nlib_a-svfwprintf may get included when linking against libstdc++\nThis will overflow IRAM\n\nhttps:\/\/github.com\/SuperHouse\/esp-open-rtos\/issues\/623\n","repos":"urx\/esp-open-rtos,UncleRus\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,ourairquality\/esp-open-rtos,SuperHouse\/esp-open-rtos,ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos,Zaltora\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,Zaltora\/esp-open-rtos,urx\/esp-open-rtos,ourairquality\/esp-open-rtos,Zaltora\/esp-open-rtos,Zaltora\/esp-open-rtos,SuperHouse\/esp-open-rtos,UncleRus\/esp-open-rtos,SuperHouse\/esp-open-rtos,Zaltora\/esp-open-rtos,urx\/esp-open-rtos,UncleRus\/esp-open-rtos,ourairquality\/esp-open-rtos,SuperHouse\/esp-open-rtos,UncleRus\/esp-open-rtos,UncleRus\/esp-open-rtos,UncleRus\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,urx\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,urx\/esp-open-rtos,SuperHouse\/esp-open-rtos,urx\/esp-open-rtos,Zaltora\/esp-open-rtos,ourairquality\/esp-open-rtos,SuperHouse\/esp-open-rtos","old_file":"ld\/program.ld","new_file":"ld\/program.ld","new_contents":"\/* Memory layout for esp-open-rtos when using OTA second stage bootloader *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x08000\n\/* irom0 section, mapped from SPI flash\n  - Origin is offset by 0x2010 to create spacer for second stage bootloader image,\n    header.\n\n  - Length is max 8Mbit of mappable flash, minus start offset\n*\/\n  irom0_0_seg :                       \torg = 0x40202010, len = (1M - 0x2010)\n}\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    . = ALIGN (16);\n    *(.vecbase.text)\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* esp-open-rtos compiled source files use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *sdklib*:*(.literal .text .literal.* .text.*)\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*-printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*-sprintf.o(.literal .text .literal.* .text.*)\n    *libc.a:*-fprintf.o(.literal .text .literal.* .text.*)\n    *libc.a:*-svfprintf.o(.literal .text .literal.* .text.*)\n    *libc.a:*-vfprintf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  \/* rodata in DRAM\n\n     cherry-picked compilation units that need rodata\n     to be in DRAM - anything that may be run while\n     SPI flash is unmapped (ie IRAM functions that are\n     called from interrupt context or spi flash management\n     functions) need their compilation units listed here.\n\n     If you have constant data that is performance-critical,\n     list the compilation unit(s) here as well.\n  *\/\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    \/* Store all of core, libc, freertos .rodata in RAM by default\n       (some parts are necessary, some parts for performance reasons.)\n    *\/\n    *core.a:*(.rodata.* .rodata) *libc.a:*.o(.rodata.* .rodata)\n    *freertos.a:*(.rodata.* .rodata)\n\n    \/* spi flash management rodata needs to be accessed\n       while flash is unmapped. *\/\n    *libmain.a:spi_flash.o(.rodata.* .rodata)\n\n    \/* libpp wdev.o has the NMI handler (sdk_wDev_ProcessFiq)\n       which runs at all times, flash mapped or not. *\/\n    *libpp.a:wdev.o(.rodata.* .rodata)\n\n    _rodata_end = ABSOLUTE(.);\n  } > dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; <-- this value seems a bit odd, stack on sdk_user_start is ~0x3ffffce9 *\/\n\n\n   \/* All data that goes to flash (IROM) ends up in this section *\/\n  .irom0.text : ALIGN(4)\n  {\n    \/*****************************\n     * Actual irom0 text section *\n     *****************************\/\n\n    _irom0_text_start = ABSOLUTE(.);\n    \/* esp-open-rtos compiled code goes into IROM by default\n       (except for libgcc which is matched above.)\n\n       We also link .rodata here in the hope that data is stored near\n       its code on the flash (in practice this doesn't quite happen. :\/)\n    *\/\n    *(.literal .text .literal.* .text.* .rodata .rodata.*)\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom.* .irom.*.* .irom0.*)\n    _irom0_text_end = ABSOLUTE(.);\n\n    \/**************************************************************\n      C++ constructor and destructor tables, properly ordered:\n     **************************************************************\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    \/***********************************\n       C++ exception handlers table:  *\n     **********************************\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n\n    \/***********************************\n     Additional .rodata special sections\n     stored in flash\n     ************************************\/\n    . = ALIGN(4);\n    *(.gnu.linkonce.r.*)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = ALIGN(4);\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n  } > irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","old_contents":"\/* Memory layout for esp-open-rtos when using OTA second stage bootloader *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x08000\n\/* irom0 section, mapped from SPI flash\n  - Origin is offset by 0x2010 to create spacer for second stage bootloader image,\n    header.\n\n  - Length is max 8Mbit of mappable flash, minus start offset\n*\/\n  irom0_0_seg :                       \torg = 0x40202010, len = (1M - 0x2010)\n}\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    . = ALIGN (16);\n    *(.vecbase.text)\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* esp-open-rtos compiled source files use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *sdklib*:*(.literal .text .literal.* .text.*)\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance)\n    *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  \/* rodata in DRAM\n\n     cherry-picked compilation units that need rodata\n     to be in DRAM - anything that may be run while\n     SPI flash is unmapped (ie IRAM functions that are\n     called from interrupt context or spi flash management\n     functions) need their compilation units listed here.\n\n     If you have constant data that is performance-critical,\n     list the compilation unit(s) here as well.\n  *\/\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n    \/* Store all of core, libc, freertos .rodata in RAM by default\n       (some parts are necessary, some parts for performance reasons.)\n    *\/\n    *core.a:*(.rodata.* .rodata) *libc.a:*.o(.rodata.* .rodata)\n    *freertos.a:*(.rodata.* .rodata)\n\n    \/* spi flash management rodata needs to be accessed\n       while flash is unmapped. *\/\n    *libmain.a:spi_flash.o(.rodata.* .rodata)\n\n    \/* libpp wdev.o has the NMI handler (sdk_wDev_ProcessFiq)\n       which runs at all times, flash mapped or not. *\/\n    *libpp.a:wdev.o(.rodata.* .rodata)\n\n    _rodata_end = ABSOLUTE(.);\n  } > dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; <-- this value seems a bit odd, stack on sdk_user_start is ~0x3ffffce9 *\/\n\n\n   \/* All data that goes to flash (IROM) ends up in this section *\/\n  .irom0.text : ALIGN(4)\n  {\n    \/*****************************\n     * Actual irom0 text section *\n     *****************************\/\n\n    _irom0_text_start = ABSOLUTE(.);\n    \/* esp-open-rtos compiled code goes into IROM by default\n       (except for libgcc which is matched above.)\n\n       We also link .rodata here in the hope that data is stored near\n       its code on the flash (in practice this doesn't quite happen. :\/)\n    *\/\n    *(.literal .text .literal.* .text.* .rodata .rodata.*)\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom.* .irom.*.* .irom0.*)\n    _irom0_text_end = ABSOLUTE(.);\n\n    \/**************************************************************\n      C++ constructor and destructor tables, properly ordered:\n     **************************************************************\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    \/***********************************\n       C++ exception handlers table:  *\n     **********************************\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n\n    \/***********************************\n     Additional .rodata special sections\n     stored in flash\n     ************************************\/\n    . = ALIGN(4);\n    *(.gnu.linkonce.r.*)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = ALIGN(4);\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n  } > irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"559cb931703b784bd1d62ec816ffd371c2eff8e0","subject":"Fix m_text section length so that it fits in the 256KB segment","message":"Fix m_text section length so that it fits in the 256KB segment\n\nGitOrigin-RevId: 218cc7792eb6051834926040ae8040e25599535f\n","repos":"google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro","old_file":"libs\/nxp\/rt1176-sdk\/MIMXRT1176xxxxx_cm7_ram.ld","new_file":"libs\/nxp\/rt1176-sdk\/MIMXRT1176xxxxx_cm7_ram.ld","new_contents":"\/*\r\n** ###################################################################\r\n**     Processors:          MIMXRT1176AVM8A_cm7\r\n**                          MIMXRT1176CVM8A_cm7\r\n**                          MIMXRT1176DVMAA_cm7\r\n**\r\n**     Compiler:            GNU C Compiler\r\n**     Reference manual:    IMXRT1170RM, Rev E, 12\/2019\r\n**     Version:             rev. 0.1, 2018-03-05\r\n**     Build:               b200828\r\n**\r\n**     Abstract:\r\n**         Linker file for the GNU C Compiler\r\n**\r\n**     Copyright 2016 Freescale Semiconductor, Inc.\r\n**     Copyright 2016-2020 NXP\r\n**     All rights reserved.\r\n**\r\n**     SPDX-License-Identifier: BSD-3-Clause\r\n**\r\n**     http:                 www.nxp.com\r\n**     mail:                 support@nxp.com\r\n**\r\n** ###################################################################\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x100000;\r\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\r\nRPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;\r\n\r\n\/*\r\n * Valid memory regions:\r\n * 0x00000000 - 0x0003FFFF (256KB)\r\n * 0x20000000 - 0x2003FFFF (256KB)\r\n * 0x20240000 - 0x202BFFFF (512KB)\r\n * 0x202C0000 - 0x2033FFFF (512KB)\r\n *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\n  m_interrupts          (RX)  : ORIGIN = 0x00000800, LENGTH = 0x00000400\r\n  m_text                (RX)  : ORIGIN = 0x00000c00, LENGTH = 0x0003F400\r\n  m_stack               (RX)  : ORIGIN = 0x20000000, LENGTH = STACK_SIZE\r\n  m_data                (RW)  : ORIGIN = 0x20000000 + STACK_SIZE, LENGTH = 0x00040000 - STACK_SIZE\r\n  rpmsg_sh_mem          (RW)  : ORIGIN = 0x202C0000, LENGTH = RPMSG_SHMEM_SIZE\r\n  m_core1_image         (RX)  : ORIGIN = 0x202C0000 + RPMSG_SHMEM_SIZE, LENGTH = 0x80000 - RPMSG_SHMEM_SIZE\r\n  m_sdram               (RW)  : ORIGIN = 0x80000000, LENGTH = 0x02000000\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  __NCACHE_REGION_START = ORIGIN(rpmsg_sh_mem);\r\n  __NCACHE_REGION_SIZE  = LENGTH(rpmsg_sh_mem);\r\n\r\n  \/* NOINIT section for rpmsg_sh_mem *\/\r\n  .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)\r\n  {\r\n     __RPMSG_SH_MEM_START__ = .;\r\n     *(.noinit.$rpmsg_sh_mem*)\r\n     . = ALIGN(4) ;\r\n     __RPMSG_SH_MEM_END__ = .;\r\n  } > rpmsg_sh_mem\r\n\r\n  \/* section for storing the secondary core image *\/\r\n  .core1_code :\r\n  {\r\n     . = ALIGN(4) ;\r\n    KEEP (*(.core1_code))\r\n     *(.core1_code*)\r\n     . = ALIGN(4) ;\r\n  } > m_core1_image\r\n\r\n  \/* The startup code goes first into internal RAM *\/\r\n  .interrupts :\r\n  {\r\n    __VECTOR_TABLE = .;\r\n    __Vectors = .;\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))     \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } > m_interrupts\r\n\r\n  \/* The program code and other data goes into internal RAM *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)                 \/* .text sections (code) *\/\r\n    *(.text*)                \/* .text* sections (code) *\/\r\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\r\n    *(.glue_7)               \/* glue arm to thumb code *\/\r\n    *(.glue_7t)              \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > m_text\r\n\r\n  .ARM :\r\n  {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } > m_text\r\n\r\n .ctors :\r\n  {\r\n    __CTOR_LIST__ = .;\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       from the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    __CTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .dtors :\r\n  {\r\n    __DTOR_LIST__ = .;\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    __DTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .preinit_array :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } > m_text\r\n\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } > m_text\r\n\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } > m_text\r\n\r\n  __etext = .;    \/* define a global symbol at end of code *\/\r\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\r\n\r\n  __VECTOR_RAM = ORIGIN(m_interrupts);\r\n  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;\r\n\r\n  .data : AT(__DATA_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __DATA_RAM = .;\r\n    __data_start__ = .;      \/* create a global symbol at data start *\/\r\n    *(m_usb_dma_init_data)\r\n    *(.data)                 \/* .data sections *\/\r\n    *(.data*)                \/* .data* sections *\/\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    __data_end__ = .;        \/* define a global symbol at data end *\/\r\n  } > m_data\r\n  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);\r\n  .ncache.init : AT(__NDATA_ROM)\r\n  {\r\n    __noncachedata_start__ = .;   \/* create a global symbol at ncache data start *\/\r\n    *(NonCacheable.init)\r\n    . = ALIGN(4);\r\n    __noncachedata_init_end__ = .;   \/* create a global symbol at initialized ncache data end *\/\r\n  } > m_data\r\n  . = __noncachedata_init_end__;\r\n  .ncache :\r\n  {\r\n    *(NonCacheable)\r\n    . = ALIGN(4);\r\n    __noncachedata_end__ = .;     \/* define a global symbol at ncache data end *\/\r\n  } > m_data\r\n  __SDRAM_ROM = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);\r\n  .sdram_data : AT(__SDRAM_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_data_start__ = .;\r\n    KEEP(*(.sdram_data*))\r\n    . = ALIGN(4);\r\n    __sdram_data_end__ = .;\r\n  } > m_sdram\r\n\r\n  \/* Uninitialized data section *\/\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss section *\/\r\n    . = ALIGN(4);\r\n    __START_BSS = .;\r\n    __bss_start__ = .;\r\n    *(m_usb_dma_noninit_data)\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n    __END_BSS = .;\r\n  } > m_data\r\n  __DATA_END = __SDRAM_ROM;\r\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\r\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\r\n\r\n  .sdram_bss (NOLOAD) :\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_bss_start__ = .;\r\n    *(.sdram_bss*)\r\n    . = ALIGN(4);\r\n    __sdram_bss_end__ = .;\r\n  } > m_sdram\r\n\r\n  .heap :\r\n  {\r\n    . = ALIGN(8);\r\n    __end__ = .;\r\n    PROVIDE(end = .);\r\n    __HeapBase = .;\r\n    . += HEAP_SIZE;\r\n    __HeapLimit = .;\r\n    __heap_limit = .; \/* Add for _sbrk *\/\r\n  } > m_sdram\r\n\r\n  .stack :\r\n  {\r\n    . = ALIGN(8);\r\n    . += STACK_SIZE;\r\n  } > m_stack\r\n\r\n  \/* Initializes stack on the end of block *\/\r\n  __StackTop   = ORIGIN(m_stack) + LENGTH(m_stack);\r\n  __StackLimit = __StackTop - STACK_SIZE;\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n\r\n","old_contents":"\/*\r\n** ###################################################################\r\n**     Processors:          MIMXRT1176AVM8A_cm7\r\n**                          MIMXRT1176CVM8A_cm7\r\n**                          MIMXRT1176DVMAA_cm7\r\n**\r\n**     Compiler:            GNU C Compiler\r\n**     Reference manual:    IMXRT1170RM, Rev E, 12\/2019\r\n**     Version:             rev. 0.1, 2018-03-05\r\n**     Build:               b200828\r\n**\r\n**     Abstract:\r\n**         Linker file for the GNU C Compiler\r\n**\r\n**     Copyright 2016 Freescale Semiconductor, Inc.\r\n**     Copyright 2016-2020 NXP\r\n**     All rights reserved.\r\n**\r\n**     SPDX-License-Identifier: BSD-3-Clause\r\n**\r\n**     http:                 www.nxp.com\r\n**     mail:                 support@nxp.com\r\n**\r\n** ###################################################################\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x100000;\r\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\r\nRPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;\r\n\r\n\/*\r\n * Valid memory regions:\r\n * 0x00000000 - 0x0003FFFF (256KB)\r\n * 0x20000000 - 0x2003FFFF (256KB)\r\n * 0x20240000 - 0x202BFFFF (512KB)\r\n * 0x202C0000 - 0x2033FFFF (512KB)\r\n *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\n  m_interrupts          (RX)  : ORIGIN = 0x00000800, LENGTH = 0x00000400\r\n  m_text                (RX)  : ORIGIN = 0x00000c00, LENGTH = 0x0003FC00\r\n  m_stack               (RX)  : ORIGIN = 0x20000000, LENGTH = STACK_SIZE\r\n  m_data                (RW)  : ORIGIN = 0x20000000 + STACK_SIZE, LENGTH = 0x00040000 - STACK_SIZE\r\n  rpmsg_sh_mem          (RW)  : ORIGIN = 0x202C0000, LENGTH = RPMSG_SHMEM_SIZE\r\n  m_core1_image         (RX)  : ORIGIN = 0x202C0000 + RPMSG_SHMEM_SIZE, LENGTH = 0x80000 - RPMSG_SHMEM_SIZE\r\n  m_sdram               (RW)  : ORIGIN = 0x80000000, LENGTH = 0x02000000\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  __NCACHE_REGION_START = ORIGIN(rpmsg_sh_mem);\r\n  __NCACHE_REGION_SIZE  = LENGTH(rpmsg_sh_mem);\r\n\r\n  \/* NOINIT section for rpmsg_sh_mem *\/\r\n  .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)\r\n  {\r\n     __RPMSG_SH_MEM_START__ = .;\r\n     *(.noinit.$rpmsg_sh_mem*)\r\n     . = ALIGN(4) ;\r\n     __RPMSG_SH_MEM_END__ = .;\r\n  } > rpmsg_sh_mem\r\n\r\n  \/* section for storing the secondary core image *\/\r\n  .core1_code :\r\n  {\r\n     . = ALIGN(4) ;\r\n    KEEP (*(.core1_code))\r\n     *(.core1_code*)\r\n     . = ALIGN(4) ;\r\n  } > m_core1_image\r\n\r\n  \/* The startup code goes first into internal RAM *\/\r\n  .interrupts :\r\n  {\r\n    __VECTOR_TABLE = .;\r\n    __Vectors = .;\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector))     \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } > m_interrupts\r\n\r\n  \/* The program code and other data goes into internal RAM *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)                 \/* .text sections (code) *\/\r\n    *(.text*)                \/* .text* sections (code) *\/\r\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\r\n    *(.glue_7)               \/* glue arm to thumb code *\/\r\n    *(.glue_7t)              \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n    . = ALIGN(4);\r\n  } > m_text\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > m_text\r\n\r\n  .ARM :\r\n  {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } > m_text\r\n\r\n .ctors :\r\n  {\r\n    __CTOR_LIST__ = .;\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       from the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    __CTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .dtors :\r\n  {\r\n    __DTOR_LIST__ = .;\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    __DTOR_END__ = .;\r\n  } > m_text\r\n\r\n  .preinit_array :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } > m_text\r\n\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } > m_text\r\n\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } > m_text\r\n\r\n  __etext = .;    \/* define a global symbol at end of code *\/\r\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\r\n\r\n  __VECTOR_RAM = ORIGIN(m_interrupts);\r\n  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;\r\n\r\n  .data : AT(__DATA_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __DATA_RAM = .;\r\n    __data_start__ = .;      \/* create a global symbol at data start *\/\r\n    *(m_usb_dma_init_data)\r\n    *(.data)                 \/* .data sections *\/\r\n    *(.data*)                \/* .data* sections *\/\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    __data_end__ = .;        \/* define a global symbol at data end *\/\r\n  } > m_data\r\n  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);\r\n  .ncache.init : AT(__NDATA_ROM)\r\n  {\r\n    __noncachedata_start__ = .;   \/* create a global symbol at ncache data start *\/\r\n    *(NonCacheable.init)\r\n    . = ALIGN(4);\r\n    __noncachedata_init_end__ = .;   \/* create a global symbol at initialized ncache data end *\/\r\n  } > m_data\r\n  . = __noncachedata_init_end__;\r\n  .ncache :\r\n  {\r\n    *(NonCacheable)\r\n    . = ALIGN(4);\r\n    __noncachedata_end__ = .;     \/* define a global symbol at ncache data end *\/\r\n  } > m_data\r\n  __SDRAM_ROM = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);\r\n  .sdram_data : AT(__SDRAM_ROM)\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_data_start__ = .;\r\n    KEEP(*(.sdram_data*))\r\n    . = ALIGN(4);\r\n    __sdram_data_end__ = .;\r\n  } > m_sdram\r\n\r\n  \/* Uninitialized data section *\/\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss section *\/\r\n    . = ALIGN(4);\r\n    __START_BSS = .;\r\n    __bss_start__ = .;\r\n    *(m_usb_dma_noninit_data)\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n    __END_BSS = .;\r\n  } > m_data\r\n  __DATA_END = __SDRAM_ROM;\r\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\r\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\r\n\r\n  .sdram_bss (NOLOAD) :\r\n  {\r\n    . = ALIGN(4);\r\n    __sdram_bss_start__ = .;\r\n    *(.sdram_bss*)\r\n    . = ALIGN(4);\r\n    __sdram_bss_end__ = .;\r\n  } > m_sdram\r\n\r\n  .heap :\r\n  {\r\n    . = ALIGN(8);\r\n    __end__ = .;\r\n    PROVIDE(end = .);\r\n    __HeapBase = .;\r\n    . += HEAP_SIZE;\r\n    __HeapLimit = .;\r\n    __heap_limit = .; \/* Add for _sbrk *\/\r\n  } > m_sdram\r\n\r\n  .stack :\r\n  {\r\n    . = ALIGN(8);\r\n    . += STACK_SIZE;\r\n  } > m_stack\r\n\r\n  \/* Initializes stack on the end of block *\/\r\n  __StackTop   = ORIGIN(m_stack) + LENGTH(m_stack);\r\n  __StackLimit = __StackTop - STACK_SIZE;\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5d6288dbd615b3b6ab943459f2999155678ebca6","subject":"Removed some files","message":"Removed some files\n","repos":"beyondsociety\/ibox,beyondsociety\/ibox","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"OUTPUT_FORMAT(elf32-i386) \n<<<<<<< HEAD\nOUTPUT_ARCH(i386) \n=======\nOUTPUT_ARCH(i386)\n>>>>>>> 318e2ce31b05692bd1567d580bf24fcf587b11db\nENTRY(start)\n\nSECTIONS\n{\n\t\/* Load kernel at 1MB *\/\n<<<<<<< HEAD\n\t. = 1M;\n\n\t\/* Multiboot Header *\/\n\t.multiboot :\n\t{\n\t\t*(.multiboot)\n\t}\n\t\t\n\t\/* Text section *\/\n\t.text :     \n\t{    \n\t\t*(.text)\n\t}\n         \n\t\/* Read-only data *\/\n\t.rodata :    \n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data :  \n\t{ \n\t\t*(.data)\n\t}\n\t\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss : \n\t{\t\t \n\t\t*(COMMON)\n\t\t*(.bss)\n\t}\n\t\n\t.note.gnu.build-id :\n\t{\n\t\t*(.note.gnu.build-id)\n=======\n    \t. = 1M;\n\n    \t\/* Multiboot header and Text section *\/\n\t.text :  \n    \t{\n        \tkernel_code = .;\n                *(.multiboot)\n\t\t*(.text)\n\t}\n\n    \t\/* Read-only data *\/\n\t.rodata :  \n\t{\n\t    \tkernel_rodata = .;\n\t\t*(.rodata)\n\t}\n\n    \t\/* Read-write data (initialized) *\/\n\t.data :  \n\t{\n\t    \tkernel_data = .;\n\t\t*(.data)\n\t}\n\t\n   \t\/* Read-write data (uninitialized) and stack *\/\n\t.bss :  \n\t{\n\t    \tkernel_bss = .;\t\t \n\t    \t*(COMMON)\n\t\t*(.bss)\n                *(.bootstrap_stack)\n\t}\n\n    \tkernel_end = .;\n\n\t\/DISCARD\/ :\n\t{\n\t\t*(.comment)\t\t\n\t\t*(.eh_frame)\n>>>>>>> 318e2ce31b05692bd1567d580bf24fcf587b11db\n\t}\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"425723f5b384ba75af4b9a6b4e0186f8bf2e99a3","subject":"Rewrite link script from scratch","message":"Rewrite link script from scratch\n\nThis absolves previous licensing issues.\n","repos":"graydon\/rust,aidancully\/rust,aidancully\/rust,graydon\/rust,aidancully\/rust,graydon\/rust,aidancully\/rust,graydon\/rust,graydon\/rust,graydon\/rust,aidancully\/rust,aidancully\/rust","old_file":"src\/librustc_target\/spec\/mipsel_sony_psp_linker_script.ld","new_file":"src\/librustc_target\/spec\/mipsel_sony_psp_linker_script.ld","new_contents":"ENTRY(module_start)\nSECTIONS\n{\n  \/* PRX format requires text to begin at 0 *\/\n  .text 0 : { *(.text .text.*) }\n\n  \/* Sort stubs for convenient ordering *\/\n  .sceStub.text : { *(.sceStub.text) *(SORT(.sceStub.text.*)) }\n\n  \/* Keep these sections around, even though they may appear unused to the linker *\/\n  .lib.ent.top :  { KEEP(*(.lib.ent.top)) }\n  .lib.ent :      { KEEP(*(.lib.ent)) }\n  .lib.ent.btm :  { KEEP(*(.lib.ent.btm)) }\n  .lib.stub.top : { KEEP(*(.lib.stub.top)) }\n  .lib.stub :     { KEEP(*(.lib.stub)) }\n  .lib.stub.btm : { KEEP(*(.lib.stub.btm)) }\n  .eh_frame_hdr : { KEEP(*(.eh_frame_hdr)) }\n\n  \/* Add symbols for LLVM's libunwind *\/\n  __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;\n  __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;\n  .eh_frame :\n  {\n    __eh_frame_start = .;\n    KEEP(*(.eh_frame))\n    __eh_frame_end = .;\n  }\n\n  \/* These are explicitly listed to avoid being merged into .rodata *\/\n  .rodata.sceResident : { *(.rodata.sceResident) }\n  .rodata.sceModuleInfo : { *(.rodata.sceModuleInfo) }\n  \/* Sort NIDs for convenient ordering *\/\n  .rodata.sceNid : { *(.rodata.sceNid) *(SORT(.rodata.sceNid.*)) }\n}\n","old_contents":"\/*\n * Copyright (c) 2005  adresd\n * Copyright (c) 2005  Marcus R. Brown\n * Copyright (c) 2005  James Forshaw\n * Copyright (c) 2005  John Kelley\n * Copyright (c) 2005  Jesper Svennevid\n * All rights reserved.\n * \n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n * 3. The names of the authors may not be used to endorse or promote products\n *    derived from this software without specific prior written permission.\n * \n * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\n * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\nOUTPUT_ARCH(mips:allegrex)\nENTRY(module_start)\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x0); . = 0x0;\n  .interp         : { *(.interp) }\n  .dynamic        : { *(.dynamic) }\n  .hash           : { *(.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }\n  .rel.init       : { *(.rel.init) }\n  .rela.init      : { *(.rela.init) }\n  .rel.fini       : { *(.rel.fini) }\n  .rela.fini      : { *(.rela.fini) }\n  \/* PSP-specific relocations. *\/\n  .rel.sceStub.text   : { *(.rel.sceStub.text) *(SORT(.rel.sceStub.text.*)) }\n  .rel.lib.ent.top    : { *(.rel.lib.ent.top) }\n  .rel.lib.ent        : { *(.rel.lib.ent) }\n  .rel.lib.ent.btm    : { *(.rel.lib.ent.btm) }\n  .rel.lib.stub.top   : { *(.rel.lib.stub.top) }\n  .rel.lib.stub       : { *(.rel.lib.stub) }\n  .rel.lib.stub.btm   : { *(.rel.lib.stub.btm) }\n  .rel.rodata.sceModuleInfo   : { *(.rel.rodata.sceModuleInfo) }\n  .rel.rodata.sceResident     : { *(.rel.rodata.sceResident) }\n  .rel.rodata.sceNid          : { *(.rel.rodata.sceNid) *(SORT(.rel.rodata.sceNid.*)) }\n  .rel.rodata.sceVstub        : { *(.rel.rodata.sceVstub) *(SORT(.rel.rodata.sceVstub.*)) }\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) }\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) }\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }\n  .rel.ctors      : { *(.rel.ctors) }\n  .rela.ctors     : { *(.rela.ctors) }\n  .rel.dtors      : { *(.rel.dtors) }\n  .rela.dtors     : { *(.rela.dtors) }\n  .rel.got        : { *(.rel.got) }\n  .rela.got       : { *(.rela.got) }\n  .rel.sdata      : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }\n  .rela.sdata     : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }\n  .rel.sbss       : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }\n  .rela.sbss      : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }\n  .rel.sdata2     : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }\n  .rela.sdata2    : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }\n  .rel.sbss2      : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }\n  .rela.sbss2     : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }\n  .rel.plt        : { *(.rel.plt) }\n  .rela.plt       : { *(.rela.plt) }\n\n  \/* Start the text section at 0x0 for PRX generation *\/\n  . = 0;\n\n  .text           :\n  {\n    _ftext = . ;\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*) *(.mips16.call.*)\n  } =0\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0\n  .plt            : { *(.plt) }\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0\n  \/* PSP library stub functions. *\/\n  .sceStub.text     : { *(.sceStub.text) *(SORT(.sceStub.text.*)) }\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  \/* PSP library entry table and library stub table. *\/\n  .lib.ent.top    : { *(.lib.ent.top) }\n  .lib.ent        : { *(.lib.ent) }\n  .lib.ent.btm    : { *(.lib.ent.btm) }\n  .lib.stub.top   : { *(.lib.stub.top) }\n  .lib.stub       : { *(.lib.stub) }\n  .lib.stub.btm   : { *(.lib.stub.btm) }\n  \/* PSP read-only data for module info, NIDs, and Vstubs.  The\n     .rodata.sceModuleInfo section must appear before the .rodata section\n     otherwise it would get absorbed into .rodata and the PSP bootloader\n     would be unable to locate the module info structure. *\/\n  .rodata.sceModuleInfo    : { *(.rodata.sceModuleInfo) }\n  .rodata.sceResident      : { *(.rodata.sceResident) }\n  .rodata.sceNid           : { KEEP(*(.rodata.sceNid)) KEEP(*(SORT(.rodata.sceNid.*))) }\n  .rodata.sceVstub         : { *(.rodata.sceVstub) *(SORT(.rodata.sceVstub.*)) }\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .sdata2         : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }\n  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }\n\n  \/* Exception handling  *\/\n  .eh_frame_hdr :\n  {\n    KEEP(*(.eh_frame_hdr))\n  }\n\n  __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0;\n  __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0;\n\n  .eh_frame :\n  {\n    __eh_frame_start = .;\n    KEEP(*(.eh_frame))\n    __eh_frame_end = .;\n  }\n\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n  . = ALIGN(256) + (. & (256 - 1));\n\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  . = ALIGN(32 \/ 8);\n  PROVIDE (__preinit_array_start = .);\n  .preinit_array     : { KEEP (*(.preinit_array)) }\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) }\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) }\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .jcr            : { KEEP (*(.jcr)) }\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }\n  .data           :\n  {\n    _fdata = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  }\n  .data1          : { *(.data1) }\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got            : { *(.got.plt) *(.got) }\n  \/* We want the small data sections together, so single-instruction offsets\n     can access them all, and initialized data all before uninitialized, so\n     we can shorten the on-disk segment size.  *\/\n  .sdata          :\n  {\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n  }\n  .lit8           : { *(.lit8) }\n  .lit4           : { *(.lit4) }\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  _fbss = .;\n  .sbss           :\n  {\n    PROVIDE (__sbss_start = .);\n    PROVIDE (___sbss_start = .);\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    PROVIDE (__sbss_end = .);\n    PROVIDE (___sbss_end = .);\n  }\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(32 \/ 8);\n  }\n  . = ALIGN(32 \/ 8);\n  _end = .;\n  PROVIDE (end = .);\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.comment) *(.pdr) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a51a98f27d916df7cee2c53c7cd25da376379dbd","subject":"","message":"\n\ngit-svn-id: https:\/\/chibios.svn.sourceforge.net\/svnroot\/chibios\/trunk@568 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"demos\/ARMCM3-STM32F103-GCC\/ch.ld","new_file":"demos\/ARMCM3-STM32F103-GCC\/ch.ld","new_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * ST32F103 memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0200;\r\n__process_stack_size__  = 0x0100;\r\n__stacks_total_size__   = __main_stack_size__ + __process_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x08000000, len = 128k\r\n    ram : org = 0x20000000, len = 20k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n    . = 0;\r\n\r\n    .text : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        _text = .;\r\n        KEEP(*(vectors));\r\n        *(.text)\r\n        *(.text.*);\r\n        *(.rodata);\r\n        *(.rodata.*);\r\n        *(.glue_7t);\r\n        *(.glue_7);\r\n        *(.gcc*);\r\n        *(.ctors);\r\n        *(.dtors);\r\n        . = ALIGN(4);\r\n        _etext = .;\r\n    } > flash\r\n\r\n    _textdata = _etext;\r\n\r\n    .data :\r\n    {\r\n        _data = .;\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        _edata = .;\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        _bss_start = .;\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _bss_end = .;\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__ - __stacks_total_size__;\r\n","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * ST32F103 memory setup.\r\n *\/\r\n__main_stack_size__\t= 0x0200;\r\n__process_stack_size__\t= 0x0100;\r\n__stacks_total_size__\t= __main_stack_size__ + __process_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x08000000, len = 128k\r\n    ram : org = 0x20000000, len = 20k\r\n}\r\n\r\n__ram_start__       = ORIGIN(ram);\r\n__ram_size__        = LENGTH(ram);\r\n__ram_end__         = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n    . = 0;\r\n\r\n    .text : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        _text = .;\r\n        KEEP(*(vectors));\r\n        *(.text)\r\n        *(.text.*);\r\n        *(.rodata);\r\n        *(.rodata.*);\r\n        *(.glue_7t);\r\n        *(.glue_7);\r\n        *(.gcc*);\r\n        *(.ctors);\r\n        *(.dtors);\r\n        . = ALIGN(4);\r\n        _etext = .;\r\n    } > flash\r\n\r\n    _textdata = _etext;\r\n\r\n    .data :\r\n    {\r\n        _data = .;\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        _edata = .;\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        _bss_start = .;\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _bss_end = .;\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__ - __stacks_total_size__;\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"db243d092c05d89491c1ecefccac74180da00178","subject":"linker external bss: Align end of ext bss to word boundary","message":"linker external bss: Align end of ext bss to word boundary\n\nTW27954\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp32\/ld\/esp32.extram.bss.ld","new_file":"components\/esp32\/ld\/esp32.extram.bss.ld","new_contents":"\/* This section is only included if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY\n   is set, to link some sections to BSS in PSRAM *\/\n\nSECTIONS\n{\n   \/* external memory bss, from any global variable with EXT_RAM_ATTR attribute*\/\n  .ext_ram.bss (NOLOAD) :\n  {\n    _ext_ram_bss_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    *libnet80211.a:(.dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)\n    *libpp.a:(.dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)\n    *liblwip.a:(.dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)\n    *libbt.a:(EXCLUDE_FILE (libbtdm_app.a) .dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)\n    . = ALIGN(4);\n    _ext_ram_bss_end = ABSOLUTE(.);\n  } > extern_ram_seg\n}\n","old_contents":"\/* This section is only included if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY\n   is set, to link some sections to BSS in PSRAM *\/\n\nSECTIONS\n{\n   \/* external memory bss, from any global variable with EXT_RAM_ATTR attribute*\/\n  .ext_ram.bss (NOLOAD) :\n  {\n    _ext_ram_bss_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    *libnet80211.a:(.dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)\n    *libpp.a:(.dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)\n    *liblwip.a:(.dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)\n    *libbt.a:(EXCLUDE_FILE (libbtdm_app.a) .dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)\n    _ext_ram_bss_end = ABSOLUTE(.);\n  } > extern_ram_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"30b5adbfa3a26d1d7c5a0a9b2931cf3574b75fe5","subject":"configs\/rtl8721csm\/scripts: Modify linker script to move app data to psram","message":"configs\/rtl8721csm\/scripts: Modify linker script to move app data to psram\n\nWhen wifi app is ported to flat build, the SRAM region is overflowing due to\nlarge size of data and bss sections. Hence, the data and bss section of app\nmodules will be moved to PSRAM. Since the app modules are distribulted into\nmany libraries, we will consider only the following libraries which are\nparticular to apps and contain only app related code.\n\nlibapps\nlibiotivity\nlibframework\nlibexternal\n","repos":"junmin-kim\/TizenRT,junmin-kim\/TizenRT,jeongchanKim\/TizenRT,an4967\/TizenRT,jeongchanKim\/TizenRT,sunghan-chang\/TizenRT,an4967\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,jeongchanKim\/TizenRT,jsdosa\/TizenRT,jeongchanKim\/TizenRT,pillip8282\/TizenRT,jsdosa\/TizenRT,an4967\/TizenRT,jsdosa\/TizenRT,jeongarmy\/TizenRT,jeongarmy\/TizenRT,pillip8282\/TizenRT,jsdosa\/TizenRT,pillip8282\/TizenRT,an4967\/TizenRT,an4967\/TizenRT,jeongarmy\/TizenRT,junmin-kim\/TizenRT,jeongarmy\/TizenRT,junmin-kim\/TizenRT,Samsung\/TizenRT,jeongchanKim\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT,an4967\/TizenRT,pillip8282\/TizenRT,sunghan-chang\/TizenRT,an4967\/TizenRT,Samsung\/TizenRT,jsdosa\/TizenRT,junmin-kim\/TizenRT,jeongchanKim\/TizenRT,jsdosa\/TizenRT,junmin-kim\/TizenRT,sunghan-chang\/TizenRT,pillip8282\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT,jeongchanKim\/TizenRT,sunghan-chang\/TizenRT,Samsung\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,junmin-kim\/TizenRT,jsdosa\/TizenRT,Samsung\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT,Samsung\/TizenRT","old_file":"build\/configs\/rtl8721csm\/scripts\/rlx8721d_img2_ns.ld","new_file":"build\/configs\/rtl8721csm\/scripts\/rlx8721d_img2_ns.ld","new_contents":"\/****************************************************************************\n *\n * Copyright 2020 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n *\n *   Copyright (C) 2020 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nOUTPUT_ARCH(arm)\nENTRY(app_start)\n\nMEMORY\n{\n\tIROM (rx) : \t\t\tORIGIN = 0x10100000, LENGTH = 0x1010A000 - 0x10100000\t\/* ROM: 40k *\/\n\tIROM_NS (rx) : \t\t\tORIGIN = 0x1010A000, LENGTH = 0x10140000 - 0x1010A000\t\/* ROM: 216k *\/\n\tDROM_NS (rx) : \t\t\tORIGIN = 0x101C0000, LENGTH = 0x101D4000 - 0x101C0000\t\/* ROM: 80k *\/\n\tDROM (rx) : \t\t\tORIGIN = 0x101D4000, LENGTH = 0x101D8000 - 0x101D4000\t\/* ROM: 16k *\/\n\tROMBSS_RAM_COM (rw)  : \t\tORIGIN = 0x10000000, LENGTH = 0x10001000 - 0x10000000\t\/* ROM BSS COMMON(S & NS both used) RAM: 4K *\/\n\tROMBSS_RAM_NS (rw)  : \t\tORIGIN = 0x10001000, LENGTH = 0x10002000 - 0x10001000\t\/* ROM BSS NS RAM: 4K *\/\n\tRSVD_RAM_NS (rw)  : \t\tORIGIN = 0x10002000, LENGTH = 0x10004000 - 0x10002000\t\/* RSVD RAM: 8K *\/\n\tMSP_RAM_NS (rw)  : \t\tORIGIN = 0x10004000, LENGTH = 0x10005000 - 0x10004000\t\/* MSP_NS RAM: 4K *\/\n\n\tBD_RAM_NS (rwx)  : \t\tORIGIN = 0x10005000, LENGTH = 0x10077000 - 0x10005000\t\/* MAIN RAM NS: 456K *\/\n\tBD_RAM_S (rwx)  : \t\tORIGIN = 0x10077000, LENGTH = 0x1007B000 - 0x10077000\t\/* MAIN RAM S: 16K *\/\n\tBD_RAM_NSC (rwx)  : \t\tORIGIN = 0x1007B000, LENGTH = 0x1007C000 - 0x1007B000\t\/* MAIN RAM NSC: 4K *\/\n\tROMBSS_RAM_S (rwx)  : \t\tORIGIN = 0x1007C000, LENGTH = 0x1007D000 - 0x1007C000\t\/* ROM BSS RAM S: 4K *\/\n\tBOOTLOADER_RAM_S (rwx)  : \tORIGIN = 0x1007D000, LENGTH = 0x1007F000 - 0x1007D000\t\/* BOOT Loader RAM: 8K *\/\n\tMSP_RAM_S (rwx)  : \t\tORIGIN = 0x1007F000, LENGTH = 0x10080000 - 0x1007F000\t\/* MSP_S RAM: 4k *\/\n\tEXTENTION_SRAM (rwx)  : \t\tORIGIN = 0x100E0000, LENGTH = 0x10100000 - 0x100E0000\t\/* EXTENTION SRAM: 128k *\/\n\n\tPSRAM_NS (rwx)  : \t\tORIGIN = 0x02000000, LENGTH = 0x023C0000 - 0x02000000\t\/* PSRAM_NS: 3M 744K*\/\n\tPSRAM_S (rwx)\t:\t\tORIGIN = 0x023C0000, LENGTH = 0x02400000 - 0x023C0000\t\/* PSRAM_S: 256K *\/\n\n\t\/* Flash *\/\n\tKM0_BOOT (rx)  :\t\tORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20\t\/* XIPBOOT: 16k, 32 Bytes resvd for header*\/\n\tBACKUP (r) :\t\t\tORIGIN = 0x08080000, LENGTH = 0x1000\t\/* BACKUP: 4K system data in flash *\/\n\tXIPSYS (r) :\t\t\tORIGIN = 0x08081000, LENGTH = 0x1000\t\/* XIPSYS: 4K system data in flash *\/\n\tKM4_BOOT (rx)  :\t\tORIGIN = 0x08004000+0x20, LENGTH = 0x02000-0x20\t\/* XIPBOOT: 8k, 32 Bytes resvd for header*\/\n\tKM0_IMG2 (rx)  : \t\tORIGIN = 0x0C000000+0x20, LENGTH = 0x02000000-0x20\t\/* KM0_IMG2: 32MB, 32 Bytes resvd for header, virtual address *\/\n\tKM4_IMG2 (rx)  : \t\tORIGIN = 0x0E000000+0x20, LENGTH = 0x02000000-0x20\t\/* KM4_IMG2 OTA1: 32MB, 32 Bytes resvd for header,  virtual address *\/\n\tBTRACE (rx) :\t\t\tORIGIN = 0x00800000, LENGTH = 0x00C00000 -0x00800000\t\/* Bluetooth Trace *\/\n\n\t\/* KM0 RAM*\/\n\tKM0_SRAM (rwx)  : \t\tORIGIN = 0x00080000, LENGTH = 0x00090000 - 0x00080000\t\/* KM0 SRAM: 64k *\/\n\tRETENTION_RAM (rwx)  : \t\tORIGIN = 0x000C0000, LENGTH = 0x000C0400 - 0x000C0000\t\/* KM0 Retention SRAM: 1k *\/\n}\n\nSECTIONS\n{\n\t.rom.text : { } > IROM_NS\n\t.rom.rodata : { } > DROM_NS\n\t.hal.rom.bss : { } > ROMBSS_RAM_COM\n\t.hal.ns_rom.bss : { } > ROMBSS_RAM_NS\n\n\t\/* image2: normal image start *\/\n\t.ram_image2.entry :\n\t{\n\t\t__ram_image2_text_start__ = .;\n\t\t__image2_entry_func__ = .;\n\t\tKEEP(*(SORT(.image2.entry.data*)))\n\n\t\t__image2_validate_code__ = .;\n\t\tKEEP(*(.image2.validate.rodata*))\n\n\t} > BD_RAM_NS\n\n\t.ram_image2.text :\n\t{\n\t\t__ram_text_start__ = .;\n\t\t_stext_ram = ABSOLUTE(.);\n\t\t*(.image2.ram.text*)\n\t\t*(.image2.net.ram.text*)\n\t\t\/*os*\/\n\t\t*os_start.o (.text*)\n\t\t*osdep_service.o (.text*)\n\t\t*tizenrt_service.o (.text*)\n\t\t\/*irq(svcall)*\/\n\t\t\/**irq_initialize.o (.text*)*\/\n\t\t*amebad_irq.o (.text*)\n\t\t*up_exception.o (.text*)\n\t\t*up_svcall.o (.text*)\n\t\t*up_switchcontext.o (.text*)\n\t\t*up_copyfullstate.o (.text*)\n\t\t*up_fullcontextrestore.o (.text*)\n\t\t*up_doirq.o (.text*)\n\t\t*irq_dispatch.o (.text*)\n\t\t\/*scheduler(for semphr)*\/\n\t\t*sched_addreadytorun.o (.text*)\n\t\t*sched_addblocked.o (.text*)\n\t\t*sched_addprioritized.o (.text*)\n\t\t*sched_removereadytorun.o (.text*)\n\t\t*sched_removeblocked.o (.text*)\n\t\t*sched_mergepending.o (.text*)\n\t\t*up_blocktask.o (.text*)\n\t\t*up_unblocktask.o (.text*)\n\t\t\/*semphr*\/\n\t\t*sem_wait.o (.text*)\n\t\t*sem_waitirq.o (.text*)\n\t\t*sem_trywait.o (.text*)\n\t\t*sem_tickwait.o (.text*)\n\t\t*sem_timedwait.o (.text*)\n\t\t*sem_post.o (.text*)\n\t\t\/* driver *\/\n\t\t*ethernetif_tizenrt.o (.text*)\n\t\t*lwip_intf_tizenrt.o (.text*)\n\t\t\/*lwip*\/\n\t\t*randm.o (.text*)\n\t\t*netifapi.o (.text*)\n\t\t*snmp_mib2_interfaces.o (.text*)\n\t\t*snmp_raw.o (.text*)\n\t\t*icmp.o (.text*)\n\t\t*ip4.o (.text*)\n\t\t*dhcp.o (.text*)\n\t\t*udp.o (.text*)\n\t\t*snmp_mib2.o (.text*)\n\t\t*etharp.o (.text*)\n\t\t*netmgr_ioctl_lwip.o (.text*)\n\t\t*dhcps.o (.text*)\n\t\t*snmp_traps.o (.text*)\n\t\t*tcp.o (.text*)\n\t\t*net_initialize_netmgr.o (.text*)\n\t\t*def.o (.text*)\n\t\t*nd6.o (.text*)\n\t\t*raw.o (.text*)\n\t\t*tcp_out.o (.text*)\n\t\t*netstack_lwip.o (.text*)\n\t\t*memp.o (.text*)\n\t\t*netdev_wifi.o (.text*)\n\t\t*lwip_md5.o (.text*)\n\t\t*snmp_mib2_udp.o (.text*)\n\t\t*netmgr_ioctl_netmon.o (.text*)\n\t\t*snmp_msg.o (.text*)\n\t\t*sys_arch.o (.text*)\n\t\t*igmp.o (.text*)\n\t\t*api_lib.o (.text*)\n\t\t*pbuf.o (.text*)\n\t\t*netdev_eth.o (.text*)\n\t\t*netdev_stats.o (.text*)\n\t\t*ip4_addr.o (.text*)\n\t\t*mem.o (.text*)\n\t\t*dns.o (.text*)\n\t\t*snmp_threadsync.o (.text*)\n\t\t*netmgr_ioctl_netdev.o (.text*)\n\t\t*snmp_mib2_system.o (.text*)\n\t\t*netdev_lwnl.o (.text*)\n\t\t*ppp_oe.o (.text*)\n\t\t*stats.o (.text*)\n\t\t*api_msg.o (.text*)\n\t\t*netstack_lwnl.o (.text*)\n\t\t*sys.o (.text*)\n\t\t*inet_chksum.o (.text*)\n\t\t*netdb.o (.text*)\n\t\t*net_vfs.o (.text*)\n\t\t*slipif.o (.text*)\n\t\t*ip6_addr.o (.text*)\n\t\t*inet6.o (.text*)\n\t\t*snmp_mib2_snmp.o (.text*)\n\t\t*pap.o (.text*)\n\t\t*netdev_mgr.o (.text*)\n\t\t*snmp_mib2_ip.o (.text*)\n\t\t*netstack.o (.text*)\n\t\t*fsm.o (.text*)\n\t\t*tcp_in.o (.text*)\n\t\t*err.o (.text*)\n\t\t*snmp_netconn.o (.text*)\n\t\t*chpms.o (.text*)\n\t\t*ethernet.o (.text*)\n\t\t*netif.o (.text*)\n\t\t*snmp_mib2_tcp.o (.text*)\n\t\t*ipcp.o (.text*)\n\t\t*chap.o (.text*)\n\t\t*timeouts.o (.text*)\n\t\t*vj.o (.text*)\n\t\t*magic.o (.text*)\n\t\t*ppp.o (.text*)\n\t\t*autoip.o (.text*)\n\t\t*snmp_mib2_icmp.o (.text*)\n\t\t*ip6.o (.text*)\n\t\t*sockets.o (.text*)\n\t\t*ethip6.o (.text*)\n\t\t*snmp_asn1.o (.text*)\n\t\t*netdev_mgr_internal.o (.text*)\n\t\t*snmp_pbuf_stream.o (.text*)\n\t\t*ip4_frag.o (.text*)\n\t\t*netdev_lwip.o (.text*)\n\t\t*bsd_socket_api.o (.text*)\n\t\t*ip6_frag.o (.text*)\n\t\t*init.o (.text*)\n\t\t*mld6.o (.text*)\n\t\t*lcp.o (.text*)\n\t\t*snmp_table.o (.text*)\n\t\t*snmp_core.o (.text*)\n\t\t*auth.o (.text*)\n\t\t*netbuf.o (.text*)\n\t\t*snmp_scalar.o (.text*)\n\t\t*icmp6.o (.text*)\n\t\t*ip.o (.text*)\n\t\t*tcpip.o (.text*)\n\t\t\/*iperf*\/\n\t\t\/* *iperf_tcp.o (.text*) *\/\n\t\t\/* *iperf_timer.o (.text*) *\/\n\t\t\/* *iperf_t_timer.o (.text*) *\/\n\t\t\/* *iperf_units.o (.text*) *\/\n\t\t\/* *iperf_util.o (.text*) *\/\n\t\t\/* *iperf_locale.o (.text*) *\/\n\t\t\/* *iperf_net.o (.text*) *\/\n\t\t\/* *iperf_tcp_info.o (.text*) *\/\n\t\t\/* *iperf_client_api.o (.text*) *\/\n\t\t\/* *iperf_api.o (.text*) *\/\n\t\t\/* *iperf_server_api.o (.text*) *\/\n\t\t\/* *iperf_error.o (.text*) *\/\n\t\t\/* *iperf_main.o (.text*) *\/\n\t\t\/* *iperf_udp.o (.text*) *\/\n\t\t\/* *iperf_server_api.o (.text*) *\/\n\t\t\/* *iperf_api.o (.text*) *\/\n\t\t\/*fs*\/\n\t\t\/**fs_read.o (.text*)\n\t\t*fs_select.o (.text*)\n\t\t*fs_poll.o (.text*)*\/\n\t\t\/*others*\/\n\t\t*lib_vikmemcpy.o (.text*)\n\t\t*dq_rem.o (.text*)\n\t\t*dq_addlast.o (.text*)\n\t\t_etext_ram = ABSOLUTE(.);\n\t\t__ram_text_end__ = .;\n\t} > BD_RAM_NS\n\n\t_eronly = ABSOLUTE(.);\n\n\t.ram_image2.data :\n\t{\n\t\t_sdata = ABSOLUTE(.);\n\t\t__data_start__ = .;\n\t\t*(EXCLUDE_FILE (*libapps.a:* *libframework.a:* *libiotivity.a:* *libexternal.a:*) .data*)\n\t\t__data_end__ = .;\n\t\t_edata = ABSOLUTE(.);\n\t\t__ram_image2_text_end__ = .;\n\t\t. = ALIGN(16);\n\t} > BD_RAM_NS\n\n\t.ram_image2.bss :\n\t{\n\t\t_sbss = ABSOLUTE(.);\n\t\t__bss_start__ = .;\n\t\t*(EXCLUDE_FILE (*libapps.a:* *libframework.a:* *libiotivity.a:* *libexternal.a:*) .bss*)\n\t\t*(COMMON)\n\t\t__bss_end__ = .;\n\n\t} > BD_RAM_NS\n\n\t.ram_image2.nocache.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t__ram_nocache_start__ = .;\n\t\t*(.bdsram.data*)\n\t\t. = ALIGN (32);\n\t\t__ram_nocache_end__ = .;\n\t} > BD_RAM_NS\n\n\t.ram_heap.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.bfsram.data*)\n\t\tend = .;\n\t\t_ebss = ABSOLUTE(.);\n\t} > BD_RAM_NS\n\n\n\t.xip_image2.text :\n\t{\n\t\t__flash_text_start__ = .;\n\t\t_stext_flash = ABSOLUTE(.);\n\n\t\t*(.img2_custom_signature*)\n\n\t\t*(.text*)\n\t\/*\t*(.image2.net.ram.text*) *\/\n\t\t*(.rodata*)\n\n\t\t\/* Add This for C++ support *\/\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP(*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\t__init_array_end = .;\n\t\t. = ALIGN(4);\n\t\t__fini_array_start = .;\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\t__fini_array_end = .;\n\t\t\/*-----------------*\/\n\n\t\t. = ALIGN (4);\n\t\t__cmd_table_start__ = .;\n\t\tKEEP(*(.cmd.table.data*))\n\t\t__cmd_table_end__ = .;\n\n\t\t_etext_flash = ABSOLUTE(.);\n\t\t__flash_text_end__ = .;\n\n\t\t. = ALIGN (16);\n\t} > KM4_IMG2\n\n\t\/* Add This for C++ support *\/\n\t.ARM.extab  :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\n\t} > KM4_IMG2\n\n\t.ARM.exidx :\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > KM4_IMG2\n\t\/*-----------------*\/\n\n\t.bluetooth_trace.text :\n\t{\n\t\t__btrace_start__ = .;\n\t\t*(.BTTRACE)\n\t\t__btrace_end__ = .;\n\t} > BTRACE\n\n\t\/* PSRAM_NS image start *\/\n\t.psram_image2.text :\n\t{\n\t\t__psram_image2_text_start__ = .;\n\t\t*(.psram.text*)\n\t\t__psram_image2_text_end__ = .;\n\t} > PSRAM_NS\n\n\t.psram_image2.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.psram.data*)\n\t\t. = ALIGN (32);\n\t\t*(.psram.rodata*)\n\t\t*libapps.a:*(.data*)\n\t\t*libiotivity.a:*(.data*)\n\t\t*libexternal.a:*(.data*)\n\t\t*libframework.a:*(.data*)\n\t} > PSRAM_NS\n\n\t.psram_image2.bss :\n\t{\n\t\t. = ALIGN (32);\n\t\t__psram_bss_start__ = .;\n\t\t*(.psram.bss*)\n\t\t*libapps.a:*(.bss*)\n\t\t*libiotivity.a:*(.bss*)\n\t\t*libexternal.a:*(.bss*)\n\t\t*libframework.a:*(.bss*)\n\t\t__psram_bss_end__ = .;\n\t} > PSRAM_NS\n\n\t.psram_heap.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.psram.heap*)\n\t} > PSRAM_NS\n\t__StackLimit = ABSOLUTE(ORIGIN(BD_RAM_NS) + LENGTH(BD_RAM_NS));\n\t__PsramStackLimit = ABSOLUTE(ORIGIN(PSRAM_NS) + LENGTH(PSRAM_NS));\n}\nSECTIONS\n{\n    __rom_bss_start__ = 0x10000000;\n    ConfigDebugClose = 0x10000000;\n    ConfigDebugBuffer = 0x10000004;\n    ConfigDebugBufferGet = 0x10000008;\n    ConfigDebug = 0x1000000c;\n    rand_first = 0x1000001c;\n    rand_seed = 0x10000020;\n    RBSS_UDELAY_DIV = 0x10000034;\n    flash_init_para = 0x10000038;\n    GDMA_Reg = 0x10000098;\n    PortA_IrqHandler = 0x1000009c;\n    PortA_IrqData = 0x1000011c;\n    PortB_IrqHandler = 0x1000019c;\n    PortB_IrqData = 0x1000021c;\n    IPC_IrqHandler = 0x1000029c;\n    IPC_IrqData = 0x1000031c;\n    IS_FPGA_VERIF = 0x1000039c;\n    crypto_engine = 0x100003a0;\n    __rom_bss_end__ = 0x10000564;\n    __rom_bss_start_ns__ = 0x10001000;\n    NewVectorTable = 0x10001000;\n    UserIrqFunTable = 0x10001140;\n    UserIrqDataTable = 0x10001240;\n    mpu_entry_register = 0x10001340;\n    p_rom_ssl_ram_map = 0x10001348;\n    rom_ssl_ram_map = 0x1000134c;\n    __rom_bss_end_ns__ = 0x1000138c;\n    __rom_bss_start_s__ = 0x1007c000;\n    __ram_start_table_start__ = 0x1007d000;\n    STACK_TOP = 0x1007effc;\n    __vectors_table = 0x1010a000;\n    Reset_Handler = 0x1010a101;\n    NMI_Handler = 0x1010a111;\n    HardFault_Handler = 0x1010a115;\n    MemManage_Handler = 0x1010a119;\n    BusFault_Handler = 0x1010a11d;\n    UsageFault_Handler = 0x1010a121;\n    SecureFault_Handler = 0x1010a125;\n    DiagVSprintf = 0x1010a12d;\n    DiagPrintf = 0x1010a3f5;\n    DiagPrintfD = 0x1010a445;\n    DiagSPrintf = 0x1010a471;\n    DiagSnPrintf = 0x1010a49d;\n    Rand = 0x1010a765;\n    Rand_Arc4 = 0x1010a7f1;\n    RandBytes_Get = 0x1010a825;\n    io_assert_failed = 0x1010a871;\n    BKUP_Write = 0x1010a891;\n    BKUP_Read = 0x1010a8b5;\n    BKUP_Set = 0x1010a8d5;\n    BKUP_Clear = 0x1010a8fd;\n    BOOT_Reason = 0x1010a929;\n    DelayNop = 0x1010a939;\n    DelayUs = 0x1010a949;\n    DelayMs = 0x1010a995;\n    EFUSEPowerSwitch = 0x1010a9a9;\n    EFUSERead8 = 0x1010aa31;\n    EFUSEWrite8 = 0x1010ab1d;\n    EFUSE_PG_Packet = 0x1010ac21;\n    EFUSE_LogicalMap_Read = 0x1010ae99;\n    EFUSE_LogicalMap_Write = 0x1010afad;\n    FLASH_RxData = 0x1010b195;\n    FLASH_TxCmd = 0x1010b29d;\n    FLASH_SW_CS_Control = 0x1010b329;\n    FLASH_SetSpiMode = 0x1010b37d;\n    FLASH_RxCmd = 0x1010b415;\n    FLASH_WaitBusy = 0x1010b479;\n    FLASH_WriteEn = 0x1010b4f9;\n    FLASH_TxData256B = 0x1010b51d;\n    FLASH_TxData12B = 0x1010b60d;\n    FLASH_SetStatus = 0x1010b6ed;\n    FLASH_Erase = 0x1010b70d;\n    FLASH_DeepPowerDown = 0x1010b7b9;\n    FLASH_SetStatusBits = 0x1010b809;\n    FLASH_StructInit_Micron = 0x1010b8dd;\n    FLASH_StructInit_MXIC = 0x1010b98d;\n    FLASH_StructInit_GD = 0x1010ba39;\n    FLASH_StructInit = 0x1010baed;\n    FLASH_Init = 0x1010bba1;\n    GDMA_StructInit = 0x1010bc25;\n    GDMA_SetLLP = 0x1010bc45;\n    GDMA_ClearINTPendingBit = 0x1010bcd9;\n    GDMA_ClearINT = 0x1010bda5;\n    GDMA_INTConfig = 0x1010be75;\n    GDMA_Cmd = 0x1010bf91;\n    GDMA_Init = 0x1010bff9;\n    GDMA_ChCleanAutoReload = 0x1010c14d;\n    GDMA_SetSrcAddr = 0x1010c1d1;\n    GDMA_GetSrcAddr = 0x1010c221;\n    GDMA_GetDstAddr = 0x1010c26d;\n    GDMA_SetDstAddr = 0x1010c2b9;\n    GDMA_SetBlkSize = 0x1010c309;\n    GDMA_GetBlkSize = 0x1010c369;\n    GDMA_ChnlRegister = 0x1010c3b9;\n    GDMA_ChnlUnRegister = 0x1010c401;\n    GDMA_ChnlAlloc = 0x1010c43d;\n    GDMA_ChnlFree = 0x1010c4d9;\n    GDMA_GetIrqNum = 0x1010c565;\n    GPIO_INTMode = 0x1010c5a9;\n    GPIO_INTConfig = 0x1010c641;\n    GPIO_INTHandler = 0x1010c679;\n    GPIO_Direction = 0x1010c721;\n    GPIO_Init = 0x1010c755;\n    GPIO_DeInit = 0x1010c7e1;\n    GPIO_ReadDataBit = 0x1010c84d;\n    GPIO_WriteBit = 0x1010c871;\n    GPIO_PortDirection = 0x1010c8a1;\n    GPIO_PortRead = 0x1010c8c5;\n    GPIO_PortWrite = 0x1010c8d5;\n    GPIO_UserRegIrq = 0x1010c8ed;\n    IPC_INTConfig = 0x1010c925;\n    IPC_IERSet = 0x1010c939;\n    IPC_IERGet = 0x1010c93d;\n    IPC_INTRequest = 0x1010c941;\n    IPC_INTClear = 0x1010c94d;\n    IPC_INTGet = 0x1010c959;\n    IPC_CPUID = 0x1010c95d;\n    IPC_SEMGet = 0x1010c969;\n    IPC_SEMFree = 0x1010c9b9;\n    IPC_INTHandler = 0x1010ca21;\n    IPC_INTUserHandler = 0x1010ca61;\n    LOGUART_StructInit = 0x1010ca9d;\n    LOGUART_Init = 0x1010cab5;\n    LOGUART_PutChar = 0x1010caf5;\n    LOGUART_GetChar = 0x1010cb29;\n    LOGUART_Readable = 0x1010cb45;\n    LOGUART_GetIMR = 0x1010cb59;\n    LOGUART_SetIMR = 0x1010cb65;\n    LOGUART_WaitBusy = 0x1010cb71;\n    LOGUART_SetBaud = 0x1010cb91;\n    mpu_enable = 0x1010cbd5;\n    mpu_disable = 0x1010cbed;\n    mpu_init = 0x1010cc01;\n    mpu_set_mem_attr = 0x1010cc3d;\n    mpu_region_cfg = 0x1010ccb1;\n    mpu_entry_free = 0x1010cdb5;\n    mpu_entry_alloc = 0x1010cdc1;\n    RSIP_Cmd = 0x1010cde9;\n    RSIP_OTF_init = 0x1010ce05;\n    RSIP_OTF_Cmd = 0x1010ce6d;\n    RSIP_OTF_Mask = 0x1010ce81;\n    RSIP_KEY_Request = 0x1010cec9;\n    RSIP_MMU_Config = 0x1010cf0d;\n    RSIP_MMU_Cmd = 0x1010cf31;\n    PAD_DrvStrength = 0x1010cf51;\n    PAD_PullCtrl = 0x1010cf6d;\n    PAD_CMD = 0x1010cf99;\n    Pinmux_Config = 0x1010cfb9;\n    Pinmux_ConfigGet = 0x1010cfd9;\n    Pinmux_UartLogCtrl = 0x1010cfe9;\n    Pinmux_SpicCtrl = 0x1010d03d;\n    simulation_bit_index = 0x1010d181;\n    simulation_stage_set = 0x1010d199;\n    SYSTIMER_Init = 0x1010d1c5;\n    SYSTIMER_TickGet = 0x1010d215;\n    SYSTIMER_GetPassTime = 0x1010d225;\n    RTIM_TimeBaseStructInit = 0x1010d255;\n    RTIM_Cmd = 0x1010d26d;\n    RTIM_GetCount = 0x1010d2f5;\n    RTIM_INTConfig = 0x1010d361;\n    RTIM_INTClear = 0x1010d3f1;\n    RTIM_TimeBaseInit = 0x1010d45d;\n    RTIM_DeInit = 0x1010d595;\n    RTIM_INTClearPendingBit = 0x1010d611;\n    RTIM_GetFlagStatus = 0x1010d685;\n    RTIM_GetINTStatus = 0x1010d75d;\n    UART_DeInit = 0x1010d83d;\n    UART_StructInit = 0x1010d845;\n    UART_BaudParaGetFull = 0x1010d861;\n    UART_BaudParaGet = 0x1010d899;\n    UART_SetBaud = 0x1010d8bd;\n    UART_SetBaudExt = 0x1010d955;\n    UART_SetRxLevel = 0x1010d9cd;\n    UART_RxCmd = 0x1010d9f5;\n    UART_Writable = 0x1010da09;\n    UART_Readable = 0x1010da11;\n    UART_CharPut = 0x1010da19;\n    UART_CharGet = 0x1010da1d;\n    UART_ReceiveData = 0x1010da25;\n    UART_SendData = 0x1010da4d;\n    UART_ReceiveDataTO = 0x1010da75;\n    UART_SendDataTO = 0x1010dab5;\n    UART_RxByteCntClear = 0x1010daf5;\n    UART_RxByteCntGet = 0x1010db01;\n    UART_BreakCtl = 0x1010db09;\n    UART_ClearRxFifo = 0x1010db1d;\n    UART_Init = 0x1010db3d;\n    UART_ClearTxFifo = 0x1010dbe5;\n    UART_INTConfig = 0x1010dbf1;\n    UART_IntStatus = 0x1010dc01;\n    UART_ModemStatusGet = 0x1010dc05;\n    UART_LineStatusGet = 0x1010dc09;\n    UART_WaitBusy = 0x1010dc0d;\n    rtl_crypto_aes_cbc_init = 0x1010dc31;\n    rtl_crypto_aes_cbc_encrypt = 0x1010dc81;\n    rtl_crypto_aes_cbc_decrypt = 0x1010dccd;\n    rtl_crypto_aes_ecb_init = 0x1010dd19;\n    rtl_crypto_aes_ecb_encrypt = 0x1010dd69;\n    rtl_crypto_aes_ecb_decrypt = 0x1010dda1;\n    rtl_crypto_aes_ctr_init = 0x1010ddd9;\n    rtl_crypto_aes_ctr_encrypt = 0x1010de29;\n    rtl_crypto_aes_ctr_decrypt = 0x1010de6d;\n    rtl_crypto_aes_cfb_init = 0x1010deb1;\n    rtl_crypto_aes_cfb_encrypt = 0x1010df01;\n    rtl_crypto_aes_cfb_decrypt = 0x1010df45;\n    rtl_crypto_aes_ofb_init = 0x1010df89;\n    rtl_crypto_aes_ofb_encrypt = 0x1010dfdd;\n    rtl_crypto_aes_ofb_decrypt = 0x1010e021;\n    rtl_crypto_aes_gcm_init = 0x1010e065;\n    rtl_crypto_aes_gcm_encrypt = 0x1010e0b9;\n    rtl_crypto_aes_gcm_decrypt = 0x1010e131;\n    BOOT_ROM_SignatureCheck = 0x1010e1a9;\n    BOOT_ROM_FromFlash = 0x1010e281;\n    BOOT_ROM_InitDebugFlg = 0x1010e38d;\n    BOOT_ROM_ResetVsr = 0x1010e3a9;\n    EXT32K_Cmd = 0x1010e4c9;\n    XTAL_ClkGet = 0x1010e4e9;\n    CPU_ClkSet = 0x1010e501;\n    CPU_ClkGet = 0x1010e515;\n    CRYPTO_MemDump = 0x1010e539;\n    CRYPTO_RegDump = 0x1010e601;\n    CRYPTO_CleanCmdOk = 0x1010e7c1;\n    CRYPTO_ClearAllINT = 0x1010e7f9;\n    CRYPTO_Reset = 0x1010e829;\n    CRYPTO_SetSecurityModeAD = 0x1010e86d;\n    CRYPTO_Init = 0x1010ea49;\n    CRYPTO_ProcessAD = 0x1010ea6d;\n    CRYPTO_SendSeqBuf = 0x1010f681;\n    CRYPTO_CipherInit = 0x1010f799;\n    CRYPTO_CipherEncryptAD = 0x1010f7b9;\n    CRYPTO_CipherDecryptAD = 0x1010f7e9;\n    rtl_crypto_3des_cbc_init = 0x1010f819;\n    rtl_crypto_3des_cbc_encrypt = 0x1010f869;\n    rtl_crypto_3des_cbc_decrypt = 0x1010f8b5;\n    rtl_crypto_3des_ecb_init = 0x1010f901;\n    rtl_crypto_3des_ecb_encrypt = 0x1010f951;\n    rtl_crypto_3des_ecb_decrypt = 0x1010f989;\n    rtl_crypto_3des_cfb_init = 0x1010f9c1;\n    rtl_crypto_3des_cfb_encrypt = 0x1010fa11;\n    rtl_crypto_3des_cfb_decrypt = 0x1010fa49;\n    rtl_crypto_3des_ofb_init = 0x1010fa81;\n    rtl_crypto_3des_ofb_encrypt = 0x1010fad1;\n    rtl_crypto_3des_ofb_decrypt = 0x1010fb09;\n    rtl_crypto_3des_ctr_init = 0x1010fb41;\n    rtl_crypto_3des_ctr_encrypt = 0x1010fb95;\n    rtl_crypto_3des_ctr_decrypt = 0x1010fbcd;\n    rtl_crypto_des_cbc_init = 0x1010fc05;\n    rtl_crypto_des_cbc_encrypt = 0x1010fc59;\n    rtl_crypto_des_cbc_decrypt = 0x1010fcb5;\n    rtl_crypto_des_ecb_init = 0x1010fd11;\n    rtl_crypto_des_ecb_encrypt = 0x1010fd65;\n    rtl_crypto_des_ecb_decrypt = 0x1010fd9d;\n    rtl_crypto_des_cfb_init = 0x1010fdd5;\n    rtl_crypto_des_cfb_encrypt = 0x1010fe29;\n    rtl_crypto_des_cfb_decrypt = 0x1010fe61;\n    rtl_crypto_des_ofb_init = 0x1010fe99;\n    rtl_crypto_des_ofb_encrypt = 0x1010feed;\n    rtl_crypto_des_ofb_decrypt = 0x1010ff25;\n    rtl_crypto_des_ctr_init = 0x1010ff5d;\n    rtl_crypto_des_ctr_encrypt = 0x1010ffb1;\n    rtl_crypto_des_ctr_decrypt = 0x1010ffe9;\n    clear_ns_rom_bss = 0x10110021;\n    RCC_PeriphClockCmd = 0x10110039;\n    RCC_PeriphClockSource_RTC = 0x101100d1;\n    RCC_PeriphClockSource_I2C = 0x1011011d;\n    RCC_PeriphClockSource_QDEC = 0x1011013d;\n    RCC_PeriphClockSource_UART = 0x1011015d;\n    SYSCFG_GetChipInfo = 0x101101d1;\n    INT_HardFault = 0x101101dd;\n    INT_MemManage = 0x101101fd;\n    INT_BusFault = 0x1011021d;\n    INT_UsageFault = 0x1011023d;\n    INT_SecureFault = 0x1011025d;\n    INT_HardFault_C = 0x1011027d;\n    INT_NMI = 0x1011064d;\n    irq_table_init = 0x10110795;\n    \/\/irq_enable = 0x101109d1;\n    \/\/irq_disable = 0x101109ed;\n    \/\/irq_set_priority = 0x10110a11;\n    \/\/irq_get_priority = 0x10110a3d;\n    \/\/irq_set_pending = 0x10110a65;\n    \/\/irq_get_pending = 0x10110a81;\n    \/\/irq_clear_pending = 0x10110aa5;\n    \/\/irq_register = 0x10110ac1;\n    \/\/irq_unregister = 0x10110b0d;\n    _char2num = 0x10110b2d;\n    _2char2dec = 0x10110b5d;\n    _2char2hex = 0x10110bd1;\n    _memchr = 0x10110c39;\n    _memcmp = 0x10110cc9;\n    _memcpy = 0x10110d2d;\n    _memmove = 0x10110dd9;\n    _memset = 0x10110ea1;\n    _vsscanf = 0x10110ffd;\n    _sscanf = 0x101115c1;\n    _stratoi = 0x101115e1;\n    _strcat = 0x10111635;\n    _strchr = 0x10111675;\n    _strcmp = 0x10111745;\n    _strcpy = 0x101117b9;\n    _stricmp = 0x10111805;\n    _strlen = 0x10111839;\n    _strncat = 0x1011189d;\n    _strncmp = 0x101118f9;\n    _strncpy = 0x1011199d;\n    _strnlen = 0x10111a05;\n    _strpbrk = 0x10111a39;\n    _strsep = 0x10111a65;\n    _strstr = 0x10111d25;\n    _strtoull = 0x10111f3d;\n    _strtoll = 0x10111ffd;\n    _strtok = 0x1011201d;\n    __strtok_r = 0x10112029;\n    _strtok_r = 0x1011208d;\n    _strtol_r = 0x10112095;\n    _strtol = 0x101121b1;\n    _strtoul_r = 0x101121b5;\n    _strtoul = 0x101122e9;\n    _strupr = 0x101122ed;\n    CRYPTO_chacha_20 = 0x10112309;\n    rom_ed25519_gen_keypair = 0x101125c5;\n    rom_ed25519_gen_signature = 0x101125c9;\n    rom_ed25519_verify_signature = 0x101125df;\n    rom_ed25519_ge_double_scalarmult_vartime = 0x10113e89;\n    rom_ed25519_ge_frombytes_negate_vartime = 0x10114195;\n    rom_ed25519_ge_p3_tobytes = 0x10114695;\n    rom_ed25519_ge_scalarmult_base = 0x101146df;\n    rom_ed25519_ge_tobytes = 0x10114807;\n    rom_ed25519_crypto_sign_seed_keypair = 0x10114851;\n    rom_ed25519_crypto_sign_verify_detached = 0x101148a9;\n    rom_ed25519_sc_muladd = 0x10114ad5;\n    rom_ed25519_sc_reduce = 0x1011b265;\n    rom_ed25519_crypto_sign_detached = 0x1011c6dd;\n    CRYPTO_poly1305_init = 0x1011ca99;\n    CRYPTO_poly1305_update = 0x1011cb31;\n    CRYPTO_poly1305_finish = 0x1011cba7;\n    rom_sha512_starts = 0x1011cd4d;\n    rom_sha512_update = 0x1011cd51;\n    rom_sha512_finish = 0x1011cd55;\n    rom_sha512 = 0x1011cd59;\n    rom_sha512_hmac_starts = 0x1011cd5d;\n    rom_sha512_hmac_update = 0x1011cdf1;\n    rom_sha512_hmac_finish = 0x1011cdf5;\n    rom_sha512_hmac_reset = 0x1011ce49;\n    rom_sha512_hmac = 0x1011ce65;\n    rom_sha512_hkdf = 0x1011cea1;\n    curve25519_donna = 0x1011dce5;\n    rtl_aes_init = 0x1011e569;\n    rtl_aes_free = 0x1011e579;\n    rtl_aes_setkey_enc = 0x1011e58d;\n    rtl_aes_setkey_dec = 0x1011e7a5;\n    rtl_aes_encrypt = 0x1011e8c1;\n    rtl_aes_decrypt = 0x1011ecf9;\n    rtl_aes_crypt_ecb = 0x1011f145;\n    rtl_aes_crypt_cbc = 0x1011f1c9;\n    rtl_aes_crypt_cfb128 = 0x1011f3d5;\n    rtl_aes_crypt_cfb8 = 0x1011f44b;\n    rtl_aes_crypt_ctr = 0x1011f4b1;\n    rtl_arc4_init = 0x1011f515;\n    rtl_arc4_free = 0x1011f525;\n    rtl_arc4_setup = 0x1011f539;\n    rtl_arc4_crypt = 0x1011f57f;\n    rtl_asn1_get_len = 0x1011f5c5;\n    rtl_asn1_get_tag = 0x1011f661;\n    rtl_asn1_get_bool = 0x1011f689;\n    rtl_asn1_get_int = 0x1011f6b9;\n    rtl_asn1_get_mpi = 0x1011f6ff;\n    rtl_asn1_get_bitstring = 0x1011f725;\n    rtl_asn1_get_bitstring_null = 0x1011f76d;\n    rtl_asn1_get_sequence_of = 0x1011f795;\n    rtl_asn1_get_alg = 0x1011f81d;\n    rtl_asn1_get_alg_null = 0x1011f8a9;\n    rtl_asn1_free_named_data = 0x1011f8ed;\n    rtl_asn1_free_named_data_list = 0x1011f91d;\n    rtl_asn1_find_named_data = 0x1011f941;\n    rtl_asn1_write_len = 0x1011f96d;\n    rtl_asn1_write_tag = 0x1011fa55;\n    rtl_asn1_write_raw_buffer = 0x1011fa71;\n    rtl_asn1_write_mpi = 0x1011faa1;\n    rtl_asn1_write_null = 0x1011fb13;\n    rtl_asn1_write_oid = 0x1011fb39;\n    rtl_asn1_write_algorithm_identifier = 0x1011fb6d;\n    rtl_asn1_write_bool = 0x1011fbbd;\n    rtl_asn1_write_int = 0x1011fbff;\n    rtl_asn1_write_printable_string = 0x1011fc61;\n    rtl_asn1_write_ia5_string = 0x1011fc95;\n    rtl_asn1_write_bitstring = 0x1011fcc9;\n    rtl_asn1_write_octet_string = 0x1011fd3d;\n    rtl_asn1_store_named_data = 0x1011fd71;\n    rtl_base64_encode = 0x1011fe29;\n    rtl_base64_decode = 0x1011ff2d;\n    rtl_mpi_init = 0x10120b19;\n    rtl_mpi_free = 0x10120b27;\n    rtl_mpi_grow = 0x10120b5d;\n    rtl_mpi_shrink = 0x10120bc1;\n    rtl_mpi_copy = 0x10120c41;\n    rtl_mpi_swap = 0x10120c9d;\n    rtl_mpi_safe_cond_assign = 0x10120cc5;\n    rtl_mpi_safe_cond_swap = 0x10120d31;\n    rtl_mpi_lset = 0x10120db3;\n    rtl_mpi_get_bit = 0x10120df1;\n    rtl_mpi_set_bit = 0x10120e11;\n    rtl_mpi_lsb = 0x10120e61;\n    rtl_mpi_bitlen = 0x10120e93;\n    rtl_mpi_size = 0x10120ed3;\n    rtl_mpi_read_binary = 0x10120edf;\n    rtl_mpi_write_binary = 0x10120f47;\n    rtl_mpi_shift_l = 0x10120f91;\n    rtl_mpi_shift_r = 0x1012102d;\n    rtl_mpi_cmp_abs = 0x101210ab;\n    rtl_mpi_cmp_mpi = 0x101211ed;\n    rtl_mpi_cmp_int = 0x10121277;\n    rtl_mpi_add_abs = 0x101212a3;\n    rtl_mpi_sub_abs = 0x10121357;\n    rtl_mpi_add_mpi = 0x101213d5;\n    rtl_mpi_sub_mpi = 0x10121417;\n    rtl_mpi_add_int = 0x1012145b;\n    rtl_mpi_sub_int = 0x10121487;\n    rtl_mpi_mul_mpi = 0x101214b3;\n    rtl_mpi_mul_int = 0x1012158f;\n    rtl_mpi_read_string = 0x101215a9;\n    rtl_mpi_div_mpi = 0x101216c9;\n    rtl_mpi_div_int = 0x10121aeb;\n    rtl_mpi_mod_mpi = 0x10121b15;\n    rtl_mpi_mod_int = 0x10121b75;\n    rtl_mpi_write_string = 0x10121c15;\n    rtl_mpi_exp_mod = 0x10121d6d;\n    rtl_mpi_gcd = 0x101221a5;\n    rtl_mpi_fill_random = 0x101222af;\n    rtl_mpi_inv_mod = 0x101224f9;\n    rtl_mpi_is_prime = 0x101227b5;\n    rtl_mpi_gen_prime = 0x10122809;\n    rtl_ctr_drbg_init = 0x10122ae9;\n    rtl_ctr_drbg_free = 0x10122af9;\n    rtl_ctr_drbg_set_prediction_resistance = 0x10122b17;\n    rtl_ctr_drbg_set_entropy_len = 0x10122b1b;\n    rtl_ctr_drbg_set_reseed_interval = 0x10122b1f;\n    rtl_ctr_drbg_update = 0x10122b23;\n    rtl_ctr_drbg_reseed = 0x10122b47;\n    rtl_ctr_drbg_seed_entropy_len = 0x10122bc5;\n    rtl_ctr_drbg_seed = 0x10122c19;\n    rtl_ctr_drbg_random_with_add = 0x10122c2b;\n    rtl_ctr_drbg_random = 0x10122cf1;\n    rtl_des_init = 0x10122d11;\n    rtl_des_free = 0x10122d1d;\n    rtl_des3_init = 0x10122d25;\n    rtl_des3_free = 0x10122d35;\n    rtl_des_key_set_parity = 0x10122d3f;\n    rtl_des_key_check_key_parity = 0x10122d59;\n    rtl_des_key_check_weak = 0x10122d7d;\n    rtl_des_setkey = 0x10122da9;\n    rtl_des_setkey_enc = 0x101231bb;\n    rtl_des_setkey_dec = 0x101231e5;\n    rtl_des3_set2key_enc = 0x10123239;\n    rtl_des3_set2key_dec = 0x1012327d;\n    rtl_des3_set3key_enc = 0x101232c1;\n    rtl_des3_set3key_dec = 0x101232fd;\n    rtl_des_crypt_ecb = 0x10123339;\n    rtl_des_crypt_cbc = 0x10123541;\n    rtl_des3_crypt_ecb = 0x10123731;\n    rtl_des3_crypt_cbc = 0x10123b81;\n    rtl_dhm_init = 0x10123e01;\n    rtl_dhm_read_params = 0x10123e0d;\n    rtl_dhm_make_params = 0x10123e59;\n    rtl_dhm_read_public = 0x10123f91;\n    rtl_dhm_make_public = 0x10123fb5;\n    rtl_dhm_calc_secret = 0x1012406d;\n    rtl_dhm_free = 0x1012426d;\n    rtl_dhm_parse_dhm = 0x101242cf;\n    rtl_ecdh_gen_public = 0x101243c1;\n    rtl_ecdh_compute_shared = 0x101243c5;\n    rtl_ecdh_init = 0x10124425;\n    rtl_ecdh_free = 0x10124435;\n    rtl_ecdh_make_params = 0x1012447d;\n    rtl_ecdh_read_params = 0x101244ed;\n    rtl_ecdh_get_params = 0x10124515;\n    rtl_ecdh_make_public = 0x10124561;\n    rtl_ecdh_read_public = 0x101245b1;\n    rtl_ecdh_calc_secret = 0x101245dd;\n    rtl_ecdsa_sign = 0x10124693;\n    rtl_ecdsa_sign_det = 0x10124815;\n    rtl_ecdsa_verify = 0x101248bd;\n    rtl_ecdsa_write_signature = 0x101249f9;\n    rtl_ecdsa_write_signature_det = 0x10124a9d;\n    rtl_ecdsa_read_signature = 0x10124abb;\n    rtl_ecdsa_genkey = 0x10124b55;\n    rtl_ecdsa_from_keypair = 0x10124b83;\n    rtl_ecdsa_init = 0x10124bbb;\n    rtl_ecdsa_free = 0x10124bbf;\n    rtl_ecjpake_init = 0x10124ff5;\n    rtl_ecjpake_free = 0x1012504f;\n    rtl_ecjpake_setup = 0x101250a5;\n    rtl_ecjpake_check = 0x101250e9;\n    rtl_ecjpake_read_round_one = 0x10125109;\n    rtl_ecjpake_write_round_one = 0x10125185;\n    rtl_ecjpake_read_round_two = 0x101252ad;\n    rtl_ecjpake_write_round_two = 0x10125365;\n    rtl_ecjpake_derive_secret = 0x101254a1;\n    rtl_ecp_curve_list = 0x10125de9;\n    rtl_ecp_curve_info_from_grp_id = 0x10125df1;\n    rtl_ecp_curve_info_from_tls_id = 0x10125e0d;\n    rtl_ecp_curve_info_from_name = 0x10125e29;\n    rtl_ecp_point_init = 0x10125e51;\n    rtl_ecp_group_init = 0x10125e71;\n    rtl_ecp_keypair_init = 0x10125e81;\n    rtl_ecp_point_free = 0x10125ea1;\n    rtl_ecp_group_free = 0x10125ec1;\n    rtl_ecp_keypair_free = 0x10125f31;\n    rtl_ecp_copy = 0x10125f51;\n    rtl_ecp_group_copy = 0x10125f7d;\n    rtl_ecp_set_zero = 0x10125f83;\n    rtl_ecp_is_zero = 0x10126839;\n    rtl_ecp_point_cmp = 0x1012684b;\n    rtl_ecp_point_read_string = 0x1012687d;\n    rtl_ecp_point_write_binary = 0x101268a9;\n    rtl_ecp_point_read_binary = 0x1012694d;\n    rtl_ecp_tls_read_point = 0x101269b9;\n    rtl_ecp_tls_write_point = 0x101269e9;\n    rtl_ecp_tls_read_group = 0x10126a19;\n    rtl_ecp_tls_write_group = 0x10126a61;\n    rtl_ecp_check_pubkey = 0x10126a99;\n    rtl_ecp_check_privkey = 0x10126c2d;\n    rtl_ecp_mul = 0x10126c9d;\n    rtl_ecp_muladd = 0x1012726f;\n    rtl_ecp_gen_keypair_base = 0x101272d9;\n    rtl_ecp_gen_keypair = 0x101273d9;\n    rtl_ecp_gen_key = 0x101273f1;\n    rtl_ecp_check_pub_priv = 0x10127419;\n    rtl_ecp_group_load = 0x10128519;\n    rtl_hmac_drbg_init = 0x1012893d;\n    rtl_hmac_drbg_update = 0x10128949;\n    rtl_hmac_drbg_seed_buf = 0x101289e5;\n    rtl_hmac_drbg_reseed = 0x10128a35;\n    rtl_hmac_drbg_seed = 0x10128aad;\n    rtl_hmac_drbg_set_prediction_resistance = 0x10128b1d;\n    rtl_hmac_drbg_set_entropy_len = 0x10128b21;\n    rtl_hmac_drbg_set_reseed_interval = 0x10128b25;\n    rtl_hmac_drbg_random_with_add = 0x10128b29;\n    rtl_hmac_drbg_random = 0x10128bdd;\n    rtl_hmac_drbg_free = 0x10128bed;\n    rtl_md_list = 0x10128c09;\n    rtl_md_info_from_string = 0x10128c11;\n    rtl_md_info_from_type = 0x10128ca9;\n    rtl_md_init = 0x10128ced;\n    rtl_md_free = 0x10128cf9;\n    rtl_md_clone = 0x10128d45;\n    rtl_md_setup = 0x10128d6d;\n    rtl_md_init_ctx = 0x10128db5;\n    rtl_md_starts = 0x10128dbb;\n    rtl_md_update = 0x10128dd5;\n    rtl_md_finish = 0x10128df1;\n    rtl_md = 0x10128e0d;\n    rtl_md_hmac_starts = 0x10128e29;\n    rtl_md_hmac_update = 0x10128eed;\n    rtl_md_hmac_finish = 0x10128f0d;\n    rtl_md_hmac_reset = 0x10128f65;\n    rtl_md_hmac = 0x10128f91;\n    rtl_md_process = 0x10128fe5;\n    rtl_md_get_size = 0x10129001;\n    rtl_md_get_type = 0x10129009;\n    rtl_md_get_name = 0x1012900f;\n    rtl_md5_init = 0x1012917d;\n    rtl_md5_free = 0x10129189;\n    rtl_md5_clone = 0x1012919d;\n    rtl_md5_starts = 0x101291a9;\n    rtl_md5_process = 0x101291d5;\n    rtl_md5_update = 0x101298dd;\n    rtl_md5_finish = 0x101298e3;\n    rtl_md5 = 0x10129995;\n    rtl_oid_get_attr_short_name = 0x101299fd;\n    rtl_oid_get_x509_ext_type = 0x10129a35;\n    rtl_oid_get_extended_key_usage = 0x10129a6d;\n    rtl_oid_get_sig_alg_desc = 0x10129aa5;\n    rtl_oid_get_sig_alg = 0x10129abd;\n    rtl_oid_get_oid_by_sig_alg = 0x10129adb;\n    rtl_oid_get_pk_alg = 0x10129b09;\n    rtl_oid_get_oid_by_pk_alg = 0x10129b41;\n    rtl_oid_get_ec_grp = 0x10129b69;\n    rtl_oid_get_oid_by_ec_grp = 0x10129ba1;\n    rtl_oid_get_cipher_alg = 0x10129bc9;\n    rtl_oid_get_md_alg = 0x10129c01;\n    rtl_oid_get_oid_by_md = 0x10129c39;\n    rtl_oid_get_pkcs12_pbe_alg = 0x10129c61;\n    rtl_pem_init = 0x10129e5f;\n    rtl_pem_read_buffer = 0x10129e6d;\n    rtl_pem_free = 0x1012a161;\n    rtl_pem_write_buffer = 0x1012a185;\n    rtl_pk_init = 0x1012a279;\n    rtl_pk_free = 0x1012a283;\n    rtl_pk_info_from_type = 0x1012a2a5;\n    rtl_pk_setup = 0x1012a2d9;\n    rtl_pk_setup_rsa_alt = 0x1012a305;\n    rtl_pk_can_do = 0x1012a351;\n    rtl_pk_verify = 0x1012a361;\n    rtl_pk_sign = 0x1012a3bd;\n    rtl_pk_decrypt = 0x1012a425;\n    rtl_pk_encrypt = 0x1012a451;\n    rtl_pk_check_pair = 0x1012a47d;\n    rtl_pk_get_bitlen = 0x1012a4bd;\n    rtl_pk_verify_ext = 0x1012a4cd;\n    rtl_pk_debug = 0x1012a585;\n    rtl_pk_get_name = 0x1012a5a9;\n    rtl_pk_get_type = 0x1012a5bd;\n    rtl_pk_write_pubkey = 0x1012aa23;\n    rtl_pk_write_pubkey_der = 0x1012aaad;\n    rtl_pk_write_key_der = 0x1012ab7d;\n    rtl_pk_write_pubkey_pem = 0x1012ad79;\n    rtl_pk_write_key_pem = 0x1012adc1;\n    rtl_rsa_init = 0x1012aecd;\n    rtl_rsa_set_padding = 0x1012aeed;\n    rtl_rsa_check_pubkey = 0x1012aef7;\n    rtl_rsa_check_privkey = 0x1012af4d;\n    rtl_rsa_check_pub_priv = 0x1012b169;\n    rtl_rsa_public = 0x1012b1a1;\n    rtl_rsa_private = 0x1012b20f;\n    rtl_rsa_rsaes_oaep_encrypt = 0x1012b465;\n    rtl_rsa_rsaes_pkcs1_v15_encrypt = 0x1012b58d;\n    rtl_rsa_pkcs1_encrypt = 0x1012b675;\n    rtl_rsa_rsaes_oaep_decrypt = 0x1012b6b5;\n    rtl_rsa_rsaes_pkcs1_v15_decrypt = 0x1012b821;\n    rtl_rsa_pkcs1_decrypt = 0x1012b92d;\n    rtl_rsa_rsassa_pss_sign = 0x1012b975;\n    rtl_rsa_rsassa_pkcs1_v15_sign = 0x1012badd;\n    rtl_rsa_pkcs1_sign = 0x1012bc85;\n    rtl_rsa_rsassa_pss_verify_ext = 0x1012bcc9;\n    rtl_rsa_rsassa_pss_verify = 0x1012be75;\n    rtl_rsa_rsassa_pkcs1_v15_verify = 0x1012bea7;\n    rtl_rsa_pkcs1_verify = 0x1012c009;\n    rtl_rsa_free = 0x1012c04d;\n    rtl_rsa_gen_key = 0x1012c0bb;\n    rtl_rsa_copy = 0x1012c261;\n    rtl_sha1_init = 0x1012c365;\n    rtl_sha1_free = 0x1012c371;\n    rtl_sha1_clone = 0x1012c385;\n    rtl_sha1_starts = 0x1012c391;\n    rtl_sha1_process = 0x1012c3c5;\n    rtl_sha1_update = 0x1012d391;\n    rtl_sha1_finish = 0x1012d397;\n    rtl_sha1 = 0x1012d45d;\n    rtl_sha256_init = 0x1012d491;\n    rtl_sha256_free = 0x1012d49d;\n    rtl_sha256_clone = 0x1012d4b1;\n    rtl_sha256_starts = 0x1012d4bd;\n    rtl_sha256_process = 0x1012d55d;\n    rtl_sha256_update = 0x1012dc89;\n    rtl_sha256_finish = 0x1012dc8f;\n    rtl_sha256 = 0x1012dd91;\n    rtl_sha512_init = 0x1012ddc9;\n    rtl_sha512_free = 0x1012ddd5;\n    rtl_sha512_clone = 0x1012dde9;\n    rtl_sha512_starts = 0x1012ddf5;\n    rtl_sha512_process = 0x1012df29;\n    rtl_sha512_update = 0x1012ec7d;\n    rtl_sha512_finish = 0x1012ec83;\n    rtl_sha512 = 0x1012eeb9;\n    __rom_entry_ns_start__ = 0x101c0000;\n    rom_sec_call_ns_entry = 0x101c0000;\n    __rom_entry_ns_end__ = 0x101c0008;\n    SPIC_CALIB_PATTERN = 0x101c0008;\n    PORT_AB = 0x101c0024;\n    armBitRevIndexTable1024 = 0x101c004c;\n    twiddleCoef_1024 = 0x101c0e5c;\n    rtl_sha512_info = 0x101ce344;\n    rtl_sha384_info = 0x101ce374;\n    rtl_sha256_info = 0x101ce3a4;\n    rtl_sha224_info = 0x101ce3d4;\n    rtl_sha1_info = 0x101ce404;\n    rtl_md5_info = 0x101ce434;\n    rtl_rsa_alt_info = 0x101cea78;\n    rtl_ecdsa_info = 0x101ceaa8;\n    rtl_eckeydh_info = 0x101cead8;\n    rtl_eckey_info = 0x101ceb08;\n    rtl_rsa_info = 0x101ceb38;\n    __rom_bss_end_s__ = 0x200f9000;\n}\n","old_contents":"\/****************************************************************************\n *\n * Copyright 2020 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *      http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n *\n *   Copyright (C) 2020 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nOUTPUT_ARCH(arm)\nENTRY(app_start)\n\nMEMORY\n{\n\tIROM (rx) : \t\t\tORIGIN = 0x10100000, LENGTH = 0x1010A000 - 0x10100000\t\/* ROM: 40k *\/\n\tIROM_NS (rx) : \t\t\tORIGIN = 0x1010A000, LENGTH = 0x10140000 - 0x1010A000\t\/* ROM: 216k *\/\n\tDROM_NS (rx) : \t\t\tORIGIN = 0x101C0000, LENGTH = 0x101D4000 - 0x101C0000\t\/* ROM: 80k *\/\n\tDROM (rx) : \t\t\tORIGIN = 0x101D4000, LENGTH = 0x101D8000 - 0x101D4000\t\/* ROM: 16k *\/\n\tROMBSS_RAM_COM (rw)  : \t\tORIGIN = 0x10000000, LENGTH = 0x10001000 - 0x10000000\t\/* ROM BSS COMMON(S & NS both used) RAM: 4K *\/\n\tROMBSS_RAM_NS (rw)  : \t\tORIGIN = 0x10001000, LENGTH = 0x10002000 - 0x10001000\t\/* ROM BSS NS RAM: 4K *\/\n\tRSVD_RAM_NS (rw)  : \t\tORIGIN = 0x10002000, LENGTH = 0x10004000 - 0x10002000\t\/* RSVD RAM: 8K *\/\n\tMSP_RAM_NS (rw)  : \t\tORIGIN = 0x10004000, LENGTH = 0x10005000 - 0x10004000\t\/* MSP_NS RAM: 4K *\/\n\n\tBD_RAM_NS (rwx)  : \t\tORIGIN = 0x10005000, LENGTH = 0x10077000 - 0x10005000\t\/* MAIN RAM NS: 456K *\/\n\tBD_RAM_S (rwx)  : \t\tORIGIN = 0x10077000, LENGTH = 0x1007B000 - 0x10077000\t\/* MAIN RAM S: 16K *\/\n\tBD_RAM_NSC (rwx)  : \t\tORIGIN = 0x1007B000, LENGTH = 0x1007C000 - 0x1007B000\t\/* MAIN RAM NSC: 4K *\/\n\tROMBSS_RAM_S (rwx)  : \t\tORIGIN = 0x1007C000, LENGTH = 0x1007D000 - 0x1007C000\t\/* ROM BSS RAM S: 4K *\/\n\tBOOTLOADER_RAM_S (rwx)  : \tORIGIN = 0x1007D000, LENGTH = 0x1007F000 - 0x1007D000\t\/* BOOT Loader RAM: 8K *\/\n\tMSP_RAM_S (rwx)  : \t\tORIGIN = 0x1007F000, LENGTH = 0x10080000 - 0x1007F000\t\/* MSP_S RAM: 4k *\/\n\tEXTENTION_SRAM (rwx)  : \t\tORIGIN = 0x100E0000, LENGTH = 0x10100000 - 0x100E0000\t\/* EXTENTION SRAM: 128k *\/\n\n\tPSRAM_NS (rwx)  : \t\tORIGIN = 0x02000000, LENGTH = 0x023C0000 - 0x02000000\t\/* PSRAM_NS: 3M 744K*\/\n\tPSRAM_S (rwx)\t:\t\tORIGIN = 0x023C0000, LENGTH = 0x02400000 - 0x023C0000\t\/* PSRAM_S: 256K *\/\n\n\t\/* Flash *\/\n\tKM0_BOOT (rx)  :\t\tORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20\t\/* XIPBOOT: 16k, 32 Bytes resvd for header*\/\n\tBACKUP (r) :\t\t\tORIGIN = 0x08080000, LENGTH = 0x1000\t\/* BACKUP: 4K system data in flash *\/\n\tXIPSYS (r) :\t\t\tORIGIN = 0x08081000, LENGTH = 0x1000\t\/* XIPSYS: 4K system data in flash *\/\n\tKM4_BOOT (rx)  :\t\tORIGIN = 0x08004000+0x20, LENGTH = 0x02000-0x20\t\/* XIPBOOT: 8k, 32 Bytes resvd for header*\/\n\tKM0_IMG2 (rx)  : \t\tORIGIN = 0x0C000000+0x20, LENGTH = 0x02000000-0x20\t\/* KM0_IMG2: 32MB, 32 Bytes resvd for header, virtual address *\/\n\tKM4_IMG2 (rx)  : \t\tORIGIN = 0x0E000000+0x20, LENGTH = 0x02000000-0x20\t\/* KM4_IMG2 OTA1: 32MB, 32 Bytes resvd for header,  virtual address *\/\n\tBTRACE (rx) :\t\t\tORIGIN = 0x00800000, LENGTH = 0x00C00000 -0x00800000\t\/* Bluetooth Trace *\/\n\n\t\/* KM0 RAM*\/\n\tKM0_SRAM (rwx)  : \t\tORIGIN = 0x00080000, LENGTH = 0x00090000 - 0x00080000\t\/* KM0 SRAM: 64k *\/\n\tRETENTION_RAM (rwx)  : \t\tORIGIN = 0x000C0000, LENGTH = 0x000C0400 - 0x000C0000\t\/* KM0 Retention SRAM: 1k *\/\n}\n\nSECTIONS\n{\n\t.rom.text : { } > IROM_NS\n\t.rom.rodata : { } > DROM_NS\n\t.hal.rom.bss : { } > ROMBSS_RAM_COM\n\t.hal.ns_rom.bss : { } > ROMBSS_RAM_NS\n\n\t\/* image2: normal image start *\/\n\t.ram_image2.entry :\n\t{\n\t\t__ram_image2_text_start__ = .;\n\t\t__image2_entry_func__ = .;\n\t\tKEEP(*(SORT(.image2.entry.data*)))\n\n\t\t__image2_validate_code__ = .;\n\t\tKEEP(*(.image2.validate.rodata*))\n\n\t} > BD_RAM_NS\n\n\t.ram_image2.text :\n\t{\n\t\t__ram_text_start__ = .;\n\t\t_stext_ram = ABSOLUTE(.);\n\t\t*(.image2.ram.text*)\n\t\t*(.image2.net.ram.text*)\n\t\t\/*os*\/\n\t\t*os_start.o (.text*)\n\t\t*osdep_service.o (.text*)\n\t\t*tizenrt_service.o (.text*)\n\t\t\/*irq(svcall)*\/\n\t\t\/**irq_initialize.o (.text*)*\/\n\t\t*amebad_irq.o (.text*)\n\t\t*up_exception.o (.text*)\n\t\t*up_svcall.o (.text*)\n\t\t*up_switchcontext.o (.text*)\n\t\t*up_copyfullstate.o (.text*)\n\t\t*up_fullcontextrestore.o (.text*)\n\t\t*up_doirq.o (.text*)\n\t\t*irq_dispatch.o (.text*)\n\t\t\/*scheduler(for semphr)*\/\n\t\t*sched_addreadytorun.o (.text*)\n\t\t*sched_addblocked.o (.text*)\n\t\t*sched_addprioritized.o (.text*)\n\t\t*sched_removereadytorun.o (.text*)\n\t\t*sched_removeblocked.o (.text*)\n\t\t*sched_mergepending.o (.text*)\n\t\t*up_blocktask.o (.text*)\n\t\t*up_unblocktask.o (.text*)\n\t\t\/*semphr*\/\n\t\t*sem_wait.o (.text*)\n\t\t*sem_waitirq.o (.text*)\n\t\t*sem_trywait.o (.text*)\n\t\t*sem_tickwait.o (.text*)\n\t\t*sem_timedwait.o (.text*)\n\t\t*sem_post.o (.text*)\n\t\t\/* driver *\/\n\t\t*ethernetif_tizenrt.o (.text*)\n\t\t*lwip_intf_tizenrt.o (.text*)\n\t\t\/*lwip*\/\n\t\t*randm.o (.text*)\n\t\t*netifapi.o (.text*)\n\t\t*snmp_mib2_interfaces.o (.text*)\n\t\t*snmp_raw.o (.text*)\n\t\t*icmp.o (.text*)\n\t\t*ip4.o (.text*)\n\t\t*dhcp.o (.text*)\n\t\t*udp.o (.text*)\n\t\t*snmp_mib2.o (.text*)\n\t\t*etharp.o (.text*)\n\t\t*netmgr_ioctl_lwip.o (.text*)\n\t\t*dhcps.o (.text*)\n\t\t*snmp_traps.o (.text*)\n\t\t*tcp.o (.text*)\n\t\t*net_initialize_netmgr.o (.text*)\n\t\t*def.o (.text*)\n\t\t*nd6.o (.text*)\n\t\t*raw.o (.text*)\n\t\t*tcp_out.o (.text*)\n\t\t*netstack_lwip.o (.text*)\n\t\t*memp.o (.text*)\n\t\t*netdev_wifi.o (.text*)\n\t\t*lwip_md5.o (.text*)\n\t\t*snmp_mib2_udp.o (.text*)\n\t\t*netmgr_ioctl_netmon.o (.text*)\n\t\t*snmp_msg.o (.text*)\n\t\t*sys_arch.o (.text*)\n\t\t*igmp.o (.text*)\n\t\t*api_lib.o (.text*)\n\t\t*pbuf.o (.text*)\n\t\t*netdev_eth.o (.text*)\n\t\t*netdev_stats.o (.text*)\n\t\t*ip4_addr.o (.text*)\n\t\t*mem.o (.text*)\n\t\t*dns.o (.text*)\n\t\t*snmp_threadsync.o (.text*)\n\t\t*netmgr_ioctl_netdev.o (.text*)\n\t\t*snmp_mib2_system.o (.text*)\n\t\t*netdev_lwnl.o (.text*)\n\t\t*ppp_oe.o (.text*)\n\t\t*stats.o (.text*)\n\t\t*api_msg.o (.text*)\n\t\t*netstack_lwnl.o (.text*)\n\t\t*sys.o (.text*)\n\t\t*inet_chksum.o (.text*)\n\t\t*netdb.o (.text*)\n\t\t*net_vfs.o (.text*)\n\t\t*slipif.o (.text*)\n\t\t*ip6_addr.o (.text*)\n\t\t*inet6.o (.text*)\n\t\t*snmp_mib2_snmp.o (.text*)\n\t\t*pap.o (.text*)\n\t\t*netdev_mgr.o (.text*)\n\t\t*snmp_mib2_ip.o (.text*)\n\t\t*netstack.o (.text*)\n\t\t*fsm.o (.text*)\n\t\t*tcp_in.o (.text*)\n\t\t*err.o (.text*)\n\t\t*snmp_netconn.o (.text*)\n\t\t*chpms.o (.text*)\n\t\t*ethernet.o (.text*)\n\t\t*netif.o (.text*)\n\t\t*snmp_mib2_tcp.o (.text*)\n\t\t*ipcp.o (.text*)\n\t\t*chap.o (.text*)\n\t\t*timeouts.o (.text*)\n\t\t*vj.o (.text*)\n\t\t*magic.o (.text*)\n\t\t*ppp.o (.text*)\n\t\t*autoip.o (.text*)\n\t\t*snmp_mib2_icmp.o (.text*)\n\t\t*ip6.o (.text*)\n\t\t*sockets.o (.text*)\n\t\t*ethip6.o (.text*)\n\t\t*snmp_asn1.o (.text*)\n\t\t*netdev_mgr_internal.o (.text*)\n\t\t*snmp_pbuf_stream.o (.text*)\n\t\t*ip4_frag.o (.text*)\n\t\t*netdev_lwip.o (.text*)\n\t\t*bsd_socket_api.o (.text*)\n\t\t*ip6_frag.o (.text*)\n\t\t*init.o (.text*)\n\t\t*mld6.o (.text*)\n\t\t*lcp.o (.text*)\n\t\t*snmp_table.o (.text*)\n\t\t*snmp_core.o (.text*)\n\t\t*auth.o (.text*)\n\t\t*netbuf.o (.text*)\n\t\t*snmp_scalar.o (.text*)\n\t\t*icmp6.o (.text*)\n\t\t*ip.o (.text*)\n\t\t*tcpip.o (.text*)\n\t\t\/*iperf*\/\n\t\t\/* *iperf_tcp.o (.text*) *\/\n\t\t\/* *iperf_timer.o (.text*) *\/\n\t\t\/* *iperf_t_timer.o (.text*) *\/\n\t\t\/* *iperf_units.o (.text*) *\/\n\t\t\/* *iperf_util.o (.text*) *\/\n\t\t\/* *iperf_locale.o (.text*) *\/\n\t\t\/* *iperf_net.o (.text*) *\/\n\t\t\/* *iperf_tcp_info.o (.text*) *\/\n\t\t\/* *iperf_client_api.o (.text*) *\/\n\t\t\/* *iperf_api.o (.text*) *\/\n\t\t\/* *iperf_server_api.o (.text*) *\/\n\t\t\/* *iperf_error.o (.text*) *\/\n\t\t\/* *iperf_main.o (.text*) *\/\n\t\t\/* *iperf_udp.o (.text*) *\/\n\t\t\/* *iperf_server_api.o (.text*) *\/\n\t\t\/* *iperf_api.o (.text*) *\/\n\t\t\/*fs*\/\n\t\t\/**fs_read.o (.text*)\n\t\t*fs_select.o (.text*)\n\t\t*fs_poll.o (.text*)*\/\n\t\t\/*others*\/\n\t\t*lib_vikmemcpy.o (.text*)\n\t\t*dq_rem.o (.text*)\n\t\t*dq_addlast.o (.text*)\n\t\t_etext_ram = ABSOLUTE(.);\n\t\t__ram_text_end__ = .;\n\t} > BD_RAM_NS\n\n\t_eronly = ABSOLUTE(.);\n\n\t.ram_image2.data :\n\t{\n\t\t_sdata = ABSOLUTE(.);\n\t\t__data_start__ = .;\n\t\t*(.data*)\n\t\t__data_end__ = .;\n\t\t_edata = ABSOLUTE(.);\n\t\t__ram_image2_text_end__ = .;\n\t\t. = ALIGN(16);\n\t} > BD_RAM_NS\n\n\t.ram_image2.bss :\n\t{\n\t\t_sbss = ABSOLUTE(.);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t__bss_end__ = .;\n\n\t} > BD_RAM_NS\n\n\t.ram_image2.nocache.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t__ram_nocache_start__ = .;\n\t\t*(.bdsram.data*)\n\t\t. = ALIGN (32);\n\t\t__ram_nocache_end__ = .;\n\t} > BD_RAM_NS\n\n\t.ram_heap.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.bfsram.data*)\n\t\tend = .;\n\t\t_ebss = ABSOLUTE(.);\n\t} > BD_RAM_NS\n\n\n\t.xip_image2.text :\n\t{\n\t\t__flash_text_start__ = .;\n\t\t_stext_flash = ABSOLUTE(.);\n\n\t\t*(.img2_custom_signature*)\n\n\t\t*(.text*)\n\t\/*\t*(.image2.net.ram.text*) *\/\n\t\t*(.rodata*)\n\n\t\t\/* Add This for C++ support *\/\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP(*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\t__init_array_end = .;\n\t\t. = ALIGN(4);\n\t\t__fini_array_start = .;\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\t__fini_array_end = .;\n\t\t\/*-----------------*\/\n\n\t\t. = ALIGN (4);\n\t\t__cmd_table_start__ = .;\n\t\tKEEP(*(.cmd.table.data*))\n\t\t__cmd_table_end__ = .;\n\n\t\t_etext_flash = ABSOLUTE(.);\n\t\t__flash_text_end__ = .;\n\n\t\t. = ALIGN (16);\n\t} > KM4_IMG2\n\n\t\/* Add This for C++ support *\/\n\t.ARM.extab  :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\n\t} > KM4_IMG2\n\n\t.ARM.exidx :\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > KM4_IMG2\n\t\/*-----------------*\/\n\n\t.bluetooth_trace.text :\n\t{\n\t\t__btrace_start__ = .;\n\t\t*(.BTTRACE)\n\t\t__btrace_end__ = .;\n\t} > BTRACE\n\n\t\/* PSRAM_NS image start *\/\n\t.psram_image2.text :\n\t{\n\t\t__psram_image2_text_start__ = .;\n\t\t*(.psram.text*)\n\t\t__psram_image2_text_end__ = .;\n\t} > PSRAM_NS\n\n\t.psram_image2.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.psram.data*)\n\t\t. = ALIGN (32);\n\t\t*(.psram.rodata*)\n\t} > PSRAM_NS\n\n\t.psram_image2.bss :\n\t{\n\t\t. = ALIGN (32);\n\t\t__psram_bss_start__ = .;\n\t\t*(.psram.bss*)\n\t\t__psram_bss_end__ = .;\n\t} > PSRAM_NS\n\n\t.psram_heap.data :\n\t{\n\t\t. = ALIGN (32);\n\t\t*(.psram.heap*)\n\t} > PSRAM_NS\n\t__StackLimit = ABSOLUTE(ORIGIN(BD_RAM_NS) + LENGTH(BD_RAM_NS));\n\t__PsramStackLimit = ABSOLUTE(ORIGIN(PSRAM_NS) + LENGTH(PSRAM_NS));\n}\nSECTIONS\n{\n    __rom_bss_start__ = 0x10000000;\n    ConfigDebugClose = 0x10000000;\n    ConfigDebugBuffer = 0x10000004;\n    ConfigDebugBufferGet = 0x10000008;\n    ConfigDebug = 0x1000000c;\n    rand_first = 0x1000001c;\n    rand_seed = 0x10000020;\n    RBSS_UDELAY_DIV = 0x10000034;\n    flash_init_para = 0x10000038;\n    GDMA_Reg = 0x10000098;\n    PortA_IrqHandler = 0x1000009c;\n    PortA_IrqData = 0x1000011c;\n    PortB_IrqHandler = 0x1000019c;\n    PortB_IrqData = 0x1000021c;\n    IPC_IrqHandler = 0x1000029c;\n    IPC_IrqData = 0x1000031c;\n    IS_FPGA_VERIF = 0x1000039c;\n    crypto_engine = 0x100003a0;\n    __rom_bss_end__ = 0x10000564;\n    __rom_bss_start_ns__ = 0x10001000;\n    NewVectorTable = 0x10001000;\n    UserIrqFunTable = 0x10001140;\n    UserIrqDataTable = 0x10001240;\n    mpu_entry_register = 0x10001340;\n    p_rom_ssl_ram_map = 0x10001348;\n    rom_ssl_ram_map = 0x1000134c;\n    __rom_bss_end_ns__ = 0x1000138c;\n    __rom_bss_start_s__ = 0x1007c000;\n    __ram_start_table_start__ = 0x1007d000;\n    STACK_TOP = 0x1007effc;\n    __vectors_table = 0x1010a000;\n    Reset_Handler = 0x1010a101;\n    NMI_Handler = 0x1010a111;\n    HardFault_Handler = 0x1010a115;\n    MemManage_Handler = 0x1010a119;\n    BusFault_Handler = 0x1010a11d;\n    UsageFault_Handler = 0x1010a121;\n    SecureFault_Handler = 0x1010a125;\n    DiagVSprintf = 0x1010a12d;\n    DiagPrintf = 0x1010a3f5;\n    DiagPrintfD = 0x1010a445;\n    DiagSPrintf = 0x1010a471;\n    DiagSnPrintf = 0x1010a49d;\n    Rand = 0x1010a765;\n    Rand_Arc4 = 0x1010a7f1;\n    RandBytes_Get = 0x1010a825;\n    io_assert_failed = 0x1010a871;\n    BKUP_Write = 0x1010a891;\n    BKUP_Read = 0x1010a8b5;\n    BKUP_Set = 0x1010a8d5;\n    BKUP_Clear = 0x1010a8fd;\n    BOOT_Reason = 0x1010a929;\n    DelayNop = 0x1010a939;\n    DelayUs = 0x1010a949;\n    DelayMs = 0x1010a995;\n    EFUSEPowerSwitch = 0x1010a9a9;\n    EFUSERead8 = 0x1010aa31;\n    EFUSEWrite8 = 0x1010ab1d;\n    EFUSE_PG_Packet = 0x1010ac21;\n    EFUSE_LogicalMap_Read = 0x1010ae99;\n    EFUSE_LogicalMap_Write = 0x1010afad;\n    FLASH_RxData = 0x1010b195;\n    FLASH_TxCmd = 0x1010b29d;\n    FLASH_SW_CS_Control = 0x1010b329;\n    FLASH_SetSpiMode = 0x1010b37d;\n    FLASH_RxCmd = 0x1010b415;\n    FLASH_WaitBusy = 0x1010b479;\n    FLASH_WriteEn = 0x1010b4f9;\n    FLASH_TxData256B = 0x1010b51d;\n    FLASH_TxData12B = 0x1010b60d;\n    FLASH_SetStatus = 0x1010b6ed;\n    FLASH_Erase = 0x1010b70d;\n    FLASH_DeepPowerDown = 0x1010b7b9;\n    FLASH_SetStatusBits = 0x1010b809;\n    FLASH_StructInit_Micron = 0x1010b8dd;\n    FLASH_StructInit_MXIC = 0x1010b98d;\n    FLASH_StructInit_GD = 0x1010ba39;\n    FLASH_StructInit = 0x1010baed;\n    FLASH_Init = 0x1010bba1;\n    GDMA_StructInit = 0x1010bc25;\n    GDMA_SetLLP = 0x1010bc45;\n    GDMA_ClearINTPendingBit = 0x1010bcd9;\n    GDMA_ClearINT = 0x1010bda5;\n    GDMA_INTConfig = 0x1010be75;\n    GDMA_Cmd = 0x1010bf91;\n    GDMA_Init = 0x1010bff9;\n    GDMA_ChCleanAutoReload = 0x1010c14d;\n    GDMA_SetSrcAddr = 0x1010c1d1;\n    GDMA_GetSrcAddr = 0x1010c221;\n    GDMA_GetDstAddr = 0x1010c26d;\n    GDMA_SetDstAddr = 0x1010c2b9;\n    GDMA_SetBlkSize = 0x1010c309;\n    GDMA_GetBlkSize = 0x1010c369;\n    GDMA_ChnlRegister = 0x1010c3b9;\n    GDMA_ChnlUnRegister = 0x1010c401;\n    GDMA_ChnlAlloc = 0x1010c43d;\n    GDMA_ChnlFree = 0x1010c4d9;\n    GDMA_GetIrqNum = 0x1010c565;\n    GPIO_INTMode = 0x1010c5a9;\n    GPIO_INTConfig = 0x1010c641;\n    GPIO_INTHandler = 0x1010c679;\n    GPIO_Direction = 0x1010c721;\n    GPIO_Init = 0x1010c755;\n    GPIO_DeInit = 0x1010c7e1;\n    GPIO_ReadDataBit = 0x1010c84d;\n    GPIO_WriteBit = 0x1010c871;\n    GPIO_PortDirection = 0x1010c8a1;\n    GPIO_PortRead = 0x1010c8c5;\n    GPIO_PortWrite = 0x1010c8d5;\n    GPIO_UserRegIrq = 0x1010c8ed;\n    IPC_INTConfig = 0x1010c925;\n    IPC_IERSet = 0x1010c939;\n    IPC_IERGet = 0x1010c93d;\n    IPC_INTRequest = 0x1010c941;\n    IPC_INTClear = 0x1010c94d;\n    IPC_INTGet = 0x1010c959;\n    IPC_CPUID = 0x1010c95d;\n    IPC_SEMGet = 0x1010c969;\n    IPC_SEMFree = 0x1010c9b9;\n    IPC_INTHandler = 0x1010ca21;\n    IPC_INTUserHandler = 0x1010ca61;\n    LOGUART_StructInit = 0x1010ca9d;\n    LOGUART_Init = 0x1010cab5;\n    LOGUART_PutChar = 0x1010caf5;\n    LOGUART_GetChar = 0x1010cb29;\n    LOGUART_Readable = 0x1010cb45;\n    LOGUART_GetIMR = 0x1010cb59;\n    LOGUART_SetIMR = 0x1010cb65;\n    LOGUART_WaitBusy = 0x1010cb71;\n    LOGUART_SetBaud = 0x1010cb91;\n    mpu_enable = 0x1010cbd5;\n    mpu_disable = 0x1010cbed;\n    mpu_init = 0x1010cc01;\n    mpu_set_mem_attr = 0x1010cc3d;\n    mpu_region_cfg = 0x1010ccb1;\n    mpu_entry_free = 0x1010cdb5;\n    mpu_entry_alloc = 0x1010cdc1;\n    RSIP_Cmd = 0x1010cde9;\n    RSIP_OTF_init = 0x1010ce05;\n    RSIP_OTF_Cmd = 0x1010ce6d;\n    RSIP_OTF_Mask = 0x1010ce81;\n    RSIP_KEY_Request = 0x1010cec9;\n    RSIP_MMU_Config = 0x1010cf0d;\n    RSIP_MMU_Cmd = 0x1010cf31;\n    PAD_DrvStrength = 0x1010cf51;\n    PAD_PullCtrl = 0x1010cf6d;\n    PAD_CMD = 0x1010cf99;\n    Pinmux_Config = 0x1010cfb9;\n    Pinmux_ConfigGet = 0x1010cfd9;\n    Pinmux_UartLogCtrl = 0x1010cfe9;\n    Pinmux_SpicCtrl = 0x1010d03d;\n    simulation_bit_index = 0x1010d181;\n    simulation_stage_set = 0x1010d199;\n    SYSTIMER_Init = 0x1010d1c5;\n    SYSTIMER_TickGet = 0x1010d215;\n    SYSTIMER_GetPassTime = 0x1010d225;\n    RTIM_TimeBaseStructInit = 0x1010d255;\n    RTIM_Cmd = 0x1010d26d;\n    RTIM_GetCount = 0x1010d2f5;\n    RTIM_INTConfig = 0x1010d361;\n    RTIM_INTClear = 0x1010d3f1;\n    RTIM_TimeBaseInit = 0x1010d45d;\n    RTIM_DeInit = 0x1010d595;\n    RTIM_INTClearPendingBit = 0x1010d611;\n    RTIM_GetFlagStatus = 0x1010d685;\n    RTIM_GetINTStatus = 0x1010d75d;\n    UART_DeInit = 0x1010d83d;\n    UART_StructInit = 0x1010d845;\n    UART_BaudParaGetFull = 0x1010d861;\n    UART_BaudParaGet = 0x1010d899;\n    UART_SetBaud = 0x1010d8bd;\n    UART_SetBaudExt = 0x1010d955;\n    UART_SetRxLevel = 0x1010d9cd;\n    UART_RxCmd = 0x1010d9f5;\n    UART_Writable = 0x1010da09;\n    UART_Readable = 0x1010da11;\n    UART_CharPut = 0x1010da19;\n    UART_CharGet = 0x1010da1d;\n    UART_ReceiveData = 0x1010da25;\n    UART_SendData = 0x1010da4d;\n    UART_ReceiveDataTO = 0x1010da75;\n    UART_SendDataTO = 0x1010dab5;\n    UART_RxByteCntClear = 0x1010daf5;\n    UART_RxByteCntGet = 0x1010db01;\n    UART_BreakCtl = 0x1010db09;\n    UART_ClearRxFifo = 0x1010db1d;\n    UART_Init = 0x1010db3d;\n    UART_ClearTxFifo = 0x1010dbe5;\n    UART_INTConfig = 0x1010dbf1;\n    UART_IntStatus = 0x1010dc01;\n    UART_ModemStatusGet = 0x1010dc05;\n    UART_LineStatusGet = 0x1010dc09;\n    UART_WaitBusy = 0x1010dc0d;\n    rtl_crypto_aes_cbc_init = 0x1010dc31;\n    rtl_crypto_aes_cbc_encrypt = 0x1010dc81;\n    rtl_crypto_aes_cbc_decrypt = 0x1010dccd;\n    rtl_crypto_aes_ecb_init = 0x1010dd19;\n    rtl_crypto_aes_ecb_encrypt = 0x1010dd69;\n    rtl_crypto_aes_ecb_decrypt = 0x1010dda1;\n    rtl_crypto_aes_ctr_init = 0x1010ddd9;\n    rtl_crypto_aes_ctr_encrypt = 0x1010de29;\n    rtl_crypto_aes_ctr_decrypt = 0x1010de6d;\n    rtl_crypto_aes_cfb_init = 0x1010deb1;\n    rtl_crypto_aes_cfb_encrypt = 0x1010df01;\n    rtl_crypto_aes_cfb_decrypt = 0x1010df45;\n    rtl_crypto_aes_ofb_init = 0x1010df89;\n    rtl_crypto_aes_ofb_encrypt = 0x1010dfdd;\n    rtl_crypto_aes_ofb_decrypt = 0x1010e021;\n    rtl_crypto_aes_gcm_init = 0x1010e065;\n    rtl_crypto_aes_gcm_encrypt = 0x1010e0b9;\n    rtl_crypto_aes_gcm_decrypt = 0x1010e131;\n    BOOT_ROM_SignatureCheck = 0x1010e1a9;\n    BOOT_ROM_FromFlash = 0x1010e281;\n    BOOT_ROM_InitDebugFlg = 0x1010e38d;\n    BOOT_ROM_ResetVsr = 0x1010e3a9;\n    EXT32K_Cmd = 0x1010e4c9;\n    XTAL_ClkGet = 0x1010e4e9;\n    CPU_ClkSet = 0x1010e501;\n    CPU_ClkGet = 0x1010e515;\n    CRYPTO_MemDump = 0x1010e539;\n    CRYPTO_RegDump = 0x1010e601;\n    CRYPTO_CleanCmdOk = 0x1010e7c1;\n    CRYPTO_ClearAllINT = 0x1010e7f9;\n    CRYPTO_Reset = 0x1010e829;\n    CRYPTO_SetSecurityModeAD = 0x1010e86d;\n    CRYPTO_Init = 0x1010ea49;\n    CRYPTO_ProcessAD = 0x1010ea6d;\n    CRYPTO_SendSeqBuf = 0x1010f681;\n    CRYPTO_CipherInit = 0x1010f799;\n    CRYPTO_CipherEncryptAD = 0x1010f7b9;\n    CRYPTO_CipherDecryptAD = 0x1010f7e9;\n    rtl_crypto_3des_cbc_init = 0x1010f819;\n    rtl_crypto_3des_cbc_encrypt = 0x1010f869;\n    rtl_crypto_3des_cbc_decrypt = 0x1010f8b5;\n    rtl_crypto_3des_ecb_init = 0x1010f901;\n    rtl_crypto_3des_ecb_encrypt = 0x1010f951;\n    rtl_crypto_3des_ecb_decrypt = 0x1010f989;\n    rtl_crypto_3des_cfb_init = 0x1010f9c1;\n    rtl_crypto_3des_cfb_encrypt = 0x1010fa11;\n    rtl_crypto_3des_cfb_decrypt = 0x1010fa49;\n    rtl_crypto_3des_ofb_init = 0x1010fa81;\n    rtl_crypto_3des_ofb_encrypt = 0x1010fad1;\n    rtl_crypto_3des_ofb_decrypt = 0x1010fb09;\n    rtl_crypto_3des_ctr_init = 0x1010fb41;\n    rtl_crypto_3des_ctr_encrypt = 0x1010fb95;\n    rtl_crypto_3des_ctr_decrypt = 0x1010fbcd;\n    rtl_crypto_des_cbc_init = 0x1010fc05;\n    rtl_crypto_des_cbc_encrypt = 0x1010fc59;\n    rtl_crypto_des_cbc_decrypt = 0x1010fcb5;\n    rtl_crypto_des_ecb_init = 0x1010fd11;\n    rtl_crypto_des_ecb_encrypt = 0x1010fd65;\n    rtl_crypto_des_ecb_decrypt = 0x1010fd9d;\n    rtl_crypto_des_cfb_init = 0x1010fdd5;\n    rtl_crypto_des_cfb_encrypt = 0x1010fe29;\n    rtl_crypto_des_cfb_decrypt = 0x1010fe61;\n    rtl_crypto_des_ofb_init = 0x1010fe99;\n    rtl_crypto_des_ofb_encrypt = 0x1010feed;\n    rtl_crypto_des_ofb_decrypt = 0x1010ff25;\n    rtl_crypto_des_ctr_init = 0x1010ff5d;\n    rtl_crypto_des_ctr_encrypt = 0x1010ffb1;\n    rtl_crypto_des_ctr_decrypt = 0x1010ffe9;\n    clear_ns_rom_bss = 0x10110021;\n    RCC_PeriphClockCmd = 0x10110039;\n    RCC_PeriphClockSource_RTC = 0x101100d1;\n    RCC_PeriphClockSource_I2C = 0x1011011d;\n    RCC_PeriphClockSource_QDEC = 0x1011013d;\n    RCC_PeriphClockSource_UART = 0x1011015d;\n    SYSCFG_GetChipInfo = 0x101101d1;\n    INT_HardFault = 0x101101dd;\n    INT_MemManage = 0x101101fd;\n    INT_BusFault = 0x1011021d;\n    INT_UsageFault = 0x1011023d;\n    INT_SecureFault = 0x1011025d;\n    INT_HardFault_C = 0x1011027d;\n    INT_NMI = 0x1011064d;\n    irq_table_init = 0x10110795;\n    \/\/irq_enable = 0x101109d1;\n    \/\/irq_disable = 0x101109ed;\n    \/\/irq_set_priority = 0x10110a11;\n    \/\/irq_get_priority = 0x10110a3d;\n    \/\/irq_set_pending = 0x10110a65;\n    \/\/irq_get_pending = 0x10110a81;\n    \/\/irq_clear_pending = 0x10110aa5;\n    \/\/irq_register = 0x10110ac1;\n    \/\/irq_unregister = 0x10110b0d;\n    _char2num = 0x10110b2d;\n    _2char2dec = 0x10110b5d;\n    _2char2hex = 0x10110bd1;\n    _memchr = 0x10110c39;\n    _memcmp = 0x10110cc9;\n    _memcpy = 0x10110d2d;\n    _memmove = 0x10110dd9;\n    _memset = 0x10110ea1;\n    _vsscanf = 0x10110ffd;\n    _sscanf = 0x101115c1;\n    _stratoi = 0x101115e1;\n    _strcat = 0x10111635;\n    _strchr = 0x10111675;\n    _strcmp = 0x10111745;\n    _strcpy = 0x101117b9;\n    _stricmp = 0x10111805;\n    _strlen = 0x10111839;\n    _strncat = 0x1011189d;\n    _strncmp = 0x101118f9;\n    _strncpy = 0x1011199d;\n    _strnlen = 0x10111a05;\n    _strpbrk = 0x10111a39;\n    _strsep = 0x10111a65;\n    _strstr = 0x10111d25;\n    _strtoull = 0x10111f3d;\n    _strtoll = 0x10111ffd;\n    _strtok = 0x1011201d;\n    __strtok_r = 0x10112029;\n    _strtok_r = 0x1011208d;\n    _strtol_r = 0x10112095;\n    _strtol = 0x101121b1;\n    _strtoul_r = 0x101121b5;\n    _strtoul = 0x101122e9;\n    _strupr = 0x101122ed;\n    CRYPTO_chacha_20 = 0x10112309;\n    rom_ed25519_gen_keypair = 0x101125c5;\n    rom_ed25519_gen_signature = 0x101125c9;\n    rom_ed25519_verify_signature = 0x101125df;\n    rom_ed25519_ge_double_scalarmult_vartime = 0x10113e89;\n    rom_ed25519_ge_frombytes_negate_vartime = 0x10114195;\n    rom_ed25519_ge_p3_tobytes = 0x10114695;\n    rom_ed25519_ge_scalarmult_base = 0x101146df;\n    rom_ed25519_ge_tobytes = 0x10114807;\n    rom_ed25519_crypto_sign_seed_keypair = 0x10114851;\n    rom_ed25519_crypto_sign_verify_detached = 0x101148a9;\n    rom_ed25519_sc_muladd = 0x10114ad5;\n    rom_ed25519_sc_reduce = 0x1011b265;\n    rom_ed25519_crypto_sign_detached = 0x1011c6dd;\n    CRYPTO_poly1305_init = 0x1011ca99;\n    CRYPTO_poly1305_update = 0x1011cb31;\n    CRYPTO_poly1305_finish = 0x1011cba7;\n    rom_sha512_starts = 0x1011cd4d;\n    rom_sha512_update = 0x1011cd51;\n    rom_sha512_finish = 0x1011cd55;\n    rom_sha512 = 0x1011cd59;\n    rom_sha512_hmac_starts = 0x1011cd5d;\n    rom_sha512_hmac_update = 0x1011cdf1;\n    rom_sha512_hmac_finish = 0x1011cdf5;\n    rom_sha512_hmac_reset = 0x1011ce49;\n    rom_sha512_hmac = 0x1011ce65;\n    rom_sha512_hkdf = 0x1011cea1;\n    curve25519_donna = 0x1011dce5;\n    rtl_aes_init = 0x1011e569;\n    rtl_aes_free = 0x1011e579;\n    rtl_aes_setkey_enc = 0x1011e58d;\n    rtl_aes_setkey_dec = 0x1011e7a5;\n    rtl_aes_encrypt = 0x1011e8c1;\n    rtl_aes_decrypt = 0x1011ecf9;\n    rtl_aes_crypt_ecb = 0x1011f145;\n    rtl_aes_crypt_cbc = 0x1011f1c9;\n    rtl_aes_crypt_cfb128 = 0x1011f3d5;\n    rtl_aes_crypt_cfb8 = 0x1011f44b;\n    rtl_aes_crypt_ctr = 0x1011f4b1;\n    rtl_arc4_init = 0x1011f515;\n    rtl_arc4_free = 0x1011f525;\n    rtl_arc4_setup = 0x1011f539;\n    rtl_arc4_crypt = 0x1011f57f;\n    rtl_asn1_get_len = 0x1011f5c5;\n    rtl_asn1_get_tag = 0x1011f661;\n    rtl_asn1_get_bool = 0x1011f689;\n    rtl_asn1_get_int = 0x1011f6b9;\n    rtl_asn1_get_mpi = 0x1011f6ff;\n    rtl_asn1_get_bitstring = 0x1011f725;\n    rtl_asn1_get_bitstring_null = 0x1011f76d;\n    rtl_asn1_get_sequence_of = 0x1011f795;\n    rtl_asn1_get_alg = 0x1011f81d;\n    rtl_asn1_get_alg_null = 0x1011f8a9;\n    rtl_asn1_free_named_data = 0x1011f8ed;\n    rtl_asn1_free_named_data_list = 0x1011f91d;\n    rtl_asn1_find_named_data = 0x1011f941;\n    rtl_asn1_write_len = 0x1011f96d;\n    rtl_asn1_write_tag = 0x1011fa55;\n    rtl_asn1_write_raw_buffer = 0x1011fa71;\n    rtl_asn1_write_mpi = 0x1011faa1;\n    rtl_asn1_write_null = 0x1011fb13;\n    rtl_asn1_write_oid = 0x1011fb39;\n    rtl_asn1_write_algorithm_identifier = 0x1011fb6d;\n    rtl_asn1_write_bool = 0x1011fbbd;\n    rtl_asn1_write_int = 0x1011fbff;\n    rtl_asn1_write_printable_string = 0x1011fc61;\n    rtl_asn1_write_ia5_string = 0x1011fc95;\n    rtl_asn1_write_bitstring = 0x1011fcc9;\n    rtl_asn1_write_octet_string = 0x1011fd3d;\n    rtl_asn1_store_named_data = 0x1011fd71;\n    rtl_base64_encode = 0x1011fe29;\n    rtl_base64_decode = 0x1011ff2d;\n    rtl_mpi_init = 0x10120b19;\n    rtl_mpi_free = 0x10120b27;\n    rtl_mpi_grow = 0x10120b5d;\n    rtl_mpi_shrink = 0x10120bc1;\n    rtl_mpi_copy = 0x10120c41;\n    rtl_mpi_swap = 0x10120c9d;\n    rtl_mpi_safe_cond_assign = 0x10120cc5;\n    rtl_mpi_safe_cond_swap = 0x10120d31;\n    rtl_mpi_lset = 0x10120db3;\n    rtl_mpi_get_bit = 0x10120df1;\n    rtl_mpi_set_bit = 0x10120e11;\n    rtl_mpi_lsb = 0x10120e61;\n    rtl_mpi_bitlen = 0x10120e93;\n    rtl_mpi_size = 0x10120ed3;\n    rtl_mpi_read_binary = 0x10120edf;\n    rtl_mpi_write_binary = 0x10120f47;\n    rtl_mpi_shift_l = 0x10120f91;\n    rtl_mpi_shift_r = 0x1012102d;\n    rtl_mpi_cmp_abs = 0x101210ab;\n    rtl_mpi_cmp_mpi = 0x101211ed;\n    rtl_mpi_cmp_int = 0x10121277;\n    rtl_mpi_add_abs = 0x101212a3;\n    rtl_mpi_sub_abs = 0x10121357;\n    rtl_mpi_add_mpi = 0x101213d5;\n    rtl_mpi_sub_mpi = 0x10121417;\n    rtl_mpi_add_int = 0x1012145b;\n    rtl_mpi_sub_int = 0x10121487;\n    rtl_mpi_mul_mpi = 0x101214b3;\n    rtl_mpi_mul_int = 0x1012158f;\n    rtl_mpi_read_string = 0x101215a9;\n    rtl_mpi_div_mpi = 0x101216c9;\n    rtl_mpi_div_int = 0x10121aeb;\n    rtl_mpi_mod_mpi = 0x10121b15;\n    rtl_mpi_mod_int = 0x10121b75;\n    rtl_mpi_write_string = 0x10121c15;\n    rtl_mpi_exp_mod = 0x10121d6d;\n    rtl_mpi_gcd = 0x101221a5;\n    rtl_mpi_fill_random = 0x101222af;\n    rtl_mpi_inv_mod = 0x101224f9;\n    rtl_mpi_is_prime = 0x101227b5;\n    rtl_mpi_gen_prime = 0x10122809;\n    rtl_ctr_drbg_init = 0x10122ae9;\n    rtl_ctr_drbg_free = 0x10122af9;\n    rtl_ctr_drbg_set_prediction_resistance = 0x10122b17;\n    rtl_ctr_drbg_set_entropy_len = 0x10122b1b;\n    rtl_ctr_drbg_set_reseed_interval = 0x10122b1f;\n    rtl_ctr_drbg_update = 0x10122b23;\n    rtl_ctr_drbg_reseed = 0x10122b47;\n    rtl_ctr_drbg_seed_entropy_len = 0x10122bc5;\n    rtl_ctr_drbg_seed = 0x10122c19;\n    rtl_ctr_drbg_random_with_add = 0x10122c2b;\n    rtl_ctr_drbg_random = 0x10122cf1;\n    rtl_des_init = 0x10122d11;\n    rtl_des_free = 0x10122d1d;\n    rtl_des3_init = 0x10122d25;\n    rtl_des3_free = 0x10122d35;\n    rtl_des_key_set_parity = 0x10122d3f;\n    rtl_des_key_check_key_parity = 0x10122d59;\n    rtl_des_key_check_weak = 0x10122d7d;\n    rtl_des_setkey = 0x10122da9;\n    rtl_des_setkey_enc = 0x101231bb;\n    rtl_des_setkey_dec = 0x101231e5;\n    rtl_des3_set2key_enc = 0x10123239;\n    rtl_des3_set2key_dec = 0x1012327d;\n    rtl_des3_set3key_enc = 0x101232c1;\n    rtl_des3_set3key_dec = 0x101232fd;\n    rtl_des_crypt_ecb = 0x10123339;\n    rtl_des_crypt_cbc = 0x10123541;\n    rtl_des3_crypt_ecb = 0x10123731;\n    rtl_des3_crypt_cbc = 0x10123b81;\n    rtl_dhm_init = 0x10123e01;\n    rtl_dhm_read_params = 0x10123e0d;\n    rtl_dhm_make_params = 0x10123e59;\n    rtl_dhm_read_public = 0x10123f91;\n    rtl_dhm_make_public = 0x10123fb5;\n    rtl_dhm_calc_secret = 0x1012406d;\n    rtl_dhm_free = 0x1012426d;\n    rtl_dhm_parse_dhm = 0x101242cf;\n    rtl_ecdh_gen_public = 0x101243c1;\n    rtl_ecdh_compute_shared = 0x101243c5;\n    rtl_ecdh_init = 0x10124425;\n    rtl_ecdh_free = 0x10124435;\n    rtl_ecdh_make_params = 0x1012447d;\n    rtl_ecdh_read_params = 0x101244ed;\n    rtl_ecdh_get_params = 0x10124515;\n    rtl_ecdh_make_public = 0x10124561;\n    rtl_ecdh_read_public = 0x101245b1;\n    rtl_ecdh_calc_secret = 0x101245dd;\n    rtl_ecdsa_sign = 0x10124693;\n    rtl_ecdsa_sign_det = 0x10124815;\n    rtl_ecdsa_verify = 0x101248bd;\n    rtl_ecdsa_write_signature = 0x101249f9;\n    rtl_ecdsa_write_signature_det = 0x10124a9d;\n    rtl_ecdsa_read_signature = 0x10124abb;\n    rtl_ecdsa_genkey = 0x10124b55;\n    rtl_ecdsa_from_keypair = 0x10124b83;\n    rtl_ecdsa_init = 0x10124bbb;\n    rtl_ecdsa_free = 0x10124bbf;\n    rtl_ecjpake_init = 0x10124ff5;\n    rtl_ecjpake_free = 0x1012504f;\n    rtl_ecjpake_setup = 0x101250a5;\n    rtl_ecjpake_check = 0x101250e9;\n    rtl_ecjpake_read_round_one = 0x10125109;\n    rtl_ecjpake_write_round_one = 0x10125185;\n    rtl_ecjpake_read_round_two = 0x101252ad;\n    rtl_ecjpake_write_round_two = 0x10125365;\n    rtl_ecjpake_derive_secret = 0x101254a1;\n    rtl_ecp_curve_list = 0x10125de9;\n    rtl_ecp_curve_info_from_grp_id = 0x10125df1;\n    rtl_ecp_curve_info_from_tls_id = 0x10125e0d;\n    rtl_ecp_curve_info_from_name = 0x10125e29;\n    rtl_ecp_point_init = 0x10125e51;\n    rtl_ecp_group_init = 0x10125e71;\n    rtl_ecp_keypair_init = 0x10125e81;\n    rtl_ecp_point_free = 0x10125ea1;\n    rtl_ecp_group_free = 0x10125ec1;\n    rtl_ecp_keypair_free = 0x10125f31;\n    rtl_ecp_copy = 0x10125f51;\n    rtl_ecp_group_copy = 0x10125f7d;\n    rtl_ecp_set_zero = 0x10125f83;\n    rtl_ecp_is_zero = 0x10126839;\n    rtl_ecp_point_cmp = 0x1012684b;\n    rtl_ecp_point_read_string = 0x1012687d;\n    rtl_ecp_point_write_binary = 0x101268a9;\n    rtl_ecp_point_read_binary = 0x1012694d;\n    rtl_ecp_tls_read_point = 0x101269b9;\n    rtl_ecp_tls_write_point = 0x101269e9;\n    rtl_ecp_tls_read_group = 0x10126a19;\n    rtl_ecp_tls_write_group = 0x10126a61;\n    rtl_ecp_check_pubkey = 0x10126a99;\n    rtl_ecp_check_privkey = 0x10126c2d;\n    rtl_ecp_mul = 0x10126c9d;\n    rtl_ecp_muladd = 0x1012726f;\n    rtl_ecp_gen_keypair_base = 0x101272d9;\n    rtl_ecp_gen_keypair = 0x101273d9;\n    rtl_ecp_gen_key = 0x101273f1;\n    rtl_ecp_check_pub_priv = 0x10127419;\n    rtl_ecp_group_load = 0x10128519;\n    rtl_hmac_drbg_init = 0x1012893d;\n    rtl_hmac_drbg_update = 0x10128949;\n    rtl_hmac_drbg_seed_buf = 0x101289e5;\n    rtl_hmac_drbg_reseed = 0x10128a35;\n    rtl_hmac_drbg_seed = 0x10128aad;\n    rtl_hmac_drbg_set_prediction_resistance = 0x10128b1d;\n    rtl_hmac_drbg_set_entropy_len = 0x10128b21;\n    rtl_hmac_drbg_set_reseed_interval = 0x10128b25;\n    rtl_hmac_drbg_random_with_add = 0x10128b29;\n    rtl_hmac_drbg_random = 0x10128bdd;\n    rtl_hmac_drbg_free = 0x10128bed;\n    rtl_md_list = 0x10128c09;\n    rtl_md_info_from_string = 0x10128c11;\n    rtl_md_info_from_type = 0x10128ca9;\n    rtl_md_init = 0x10128ced;\n    rtl_md_free = 0x10128cf9;\n    rtl_md_clone = 0x10128d45;\n    rtl_md_setup = 0x10128d6d;\n    rtl_md_init_ctx = 0x10128db5;\n    rtl_md_starts = 0x10128dbb;\n    rtl_md_update = 0x10128dd5;\n    rtl_md_finish = 0x10128df1;\n    rtl_md = 0x10128e0d;\n    rtl_md_hmac_starts = 0x10128e29;\n    rtl_md_hmac_update = 0x10128eed;\n    rtl_md_hmac_finish = 0x10128f0d;\n    rtl_md_hmac_reset = 0x10128f65;\n    rtl_md_hmac = 0x10128f91;\n    rtl_md_process = 0x10128fe5;\n    rtl_md_get_size = 0x10129001;\n    rtl_md_get_type = 0x10129009;\n    rtl_md_get_name = 0x1012900f;\n    rtl_md5_init = 0x1012917d;\n    rtl_md5_free = 0x10129189;\n    rtl_md5_clone = 0x1012919d;\n    rtl_md5_starts = 0x101291a9;\n    rtl_md5_process = 0x101291d5;\n    rtl_md5_update = 0x101298dd;\n    rtl_md5_finish = 0x101298e3;\n    rtl_md5 = 0x10129995;\n    rtl_oid_get_attr_short_name = 0x101299fd;\n    rtl_oid_get_x509_ext_type = 0x10129a35;\n    rtl_oid_get_extended_key_usage = 0x10129a6d;\n    rtl_oid_get_sig_alg_desc = 0x10129aa5;\n    rtl_oid_get_sig_alg = 0x10129abd;\n    rtl_oid_get_oid_by_sig_alg = 0x10129adb;\n    rtl_oid_get_pk_alg = 0x10129b09;\n    rtl_oid_get_oid_by_pk_alg = 0x10129b41;\n    rtl_oid_get_ec_grp = 0x10129b69;\n    rtl_oid_get_oid_by_ec_grp = 0x10129ba1;\n    rtl_oid_get_cipher_alg = 0x10129bc9;\n    rtl_oid_get_md_alg = 0x10129c01;\n    rtl_oid_get_oid_by_md = 0x10129c39;\n    rtl_oid_get_pkcs12_pbe_alg = 0x10129c61;\n    rtl_pem_init = 0x10129e5f;\n    rtl_pem_read_buffer = 0x10129e6d;\n    rtl_pem_free = 0x1012a161;\n    rtl_pem_write_buffer = 0x1012a185;\n    rtl_pk_init = 0x1012a279;\n    rtl_pk_free = 0x1012a283;\n    rtl_pk_info_from_type = 0x1012a2a5;\n    rtl_pk_setup = 0x1012a2d9;\n    rtl_pk_setup_rsa_alt = 0x1012a305;\n    rtl_pk_can_do = 0x1012a351;\n    rtl_pk_verify = 0x1012a361;\n    rtl_pk_sign = 0x1012a3bd;\n    rtl_pk_decrypt = 0x1012a425;\n    rtl_pk_encrypt = 0x1012a451;\n    rtl_pk_check_pair = 0x1012a47d;\n    rtl_pk_get_bitlen = 0x1012a4bd;\n    rtl_pk_verify_ext = 0x1012a4cd;\n    rtl_pk_debug = 0x1012a585;\n    rtl_pk_get_name = 0x1012a5a9;\n    rtl_pk_get_type = 0x1012a5bd;\n    rtl_pk_write_pubkey = 0x1012aa23;\n    rtl_pk_write_pubkey_der = 0x1012aaad;\n    rtl_pk_write_key_der = 0x1012ab7d;\n    rtl_pk_write_pubkey_pem = 0x1012ad79;\n    rtl_pk_write_key_pem = 0x1012adc1;\n    rtl_rsa_init = 0x1012aecd;\n    rtl_rsa_set_padding = 0x1012aeed;\n    rtl_rsa_check_pubkey = 0x1012aef7;\n    rtl_rsa_check_privkey = 0x1012af4d;\n    rtl_rsa_check_pub_priv = 0x1012b169;\n    rtl_rsa_public = 0x1012b1a1;\n    rtl_rsa_private = 0x1012b20f;\n    rtl_rsa_rsaes_oaep_encrypt = 0x1012b465;\n    rtl_rsa_rsaes_pkcs1_v15_encrypt = 0x1012b58d;\n    rtl_rsa_pkcs1_encrypt = 0x1012b675;\n    rtl_rsa_rsaes_oaep_decrypt = 0x1012b6b5;\n    rtl_rsa_rsaes_pkcs1_v15_decrypt = 0x1012b821;\n    rtl_rsa_pkcs1_decrypt = 0x1012b92d;\n    rtl_rsa_rsassa_pss_sign = 0x1012b975;\n    rtl_rsa_rsassa_pkcs1_v15_sign = 0x1012badd;\n    rtl_rsa_pkcs1_sign = 0x1012bc85;\n    rtl_rsa_rsassa_pss_verify_ext = 0x1012bcc9;\n    rtl_rsa_rsassa_pss_verify = 0x1012be75;\n    rtl_rsa_rsassa_pkcs1_v15_verify = 0x1012bea7;\n    rtl_rsa_pkcs1_verify = 0x1012c009;\n    rtl_rsa_free = 0x1012c04d;\n    rtl_rsa_gen_key = 0x1012c0bb;\n    rtl_rsa_copy = 0x1012c261;\n    rtl_sha1_init = 0x1012c365;\n    rtl_sha1_free = 0x1012c371;\n    rtl_sha1_clone = 0x1012c385;\n    rtl_sha1_starts = 0x1012c391;\n    rtl_sha1_process = 0x1012c3c5;\n    rtl_sha1_update = 0x1012d391;\n    rtl_sha1_finish = 0x1012d397;\n    rtl_sha1 = 0x1012d45d;\n    rtl_sha256_init = 0x1012d491;\n    rtl_sha256_free = 0x1012d49d;\n    rtl_sha256_clone = 0x1012d4b1;\n    rtl_sha256_starts = 0x1012d4bd;\n    rtl_sha256_process = 0x1012d55d;\n    rtl_sha256_update = 0x1012dc89;\n    rtl_sha256_finish = 0x1012dc8f;\n    rtl_sha256 = 0x1012dd91;\n    rtl_sha512_init = 0x1012ddc9;\n    rtl_sha512_free = 0x1012ddd5;\n    rtl_sha512_clone = 0x1012dde9;\n    rtl_sha512_starts = 0x1012ddf5;\n    rtl_sha512_process = 0x1012df29;\n    rtl_sha512_update = 0x1012ec7d;\n    rtl_sha512_finish = 0x1012ec83;\n    rtl_sha512 = 0x1012eeb9;\n    __rom_entry_ns_start__ = 0x101c0000;\n    rom_sec_call_ns_entry = 0x101c0000;\n    __rom_entry_ns_end__ = 0x101c0008;\n    SPIC_CALIB_PATTERN = 0x101c0008;\n    PORT_AB = 0x101c0024;\n    armBitRevIndexTable1024 = 0x101c004c;\n    twiddleCoef_1024 = 0x101c0e5c;\n    rtl_sha512_info = 0x101ce344;\n    rtl_sha384_info = 0x101ce374;\n    rtl_sha256_info = 0x101ce3a4;\n    rtl_sha224_info = 0x101ce3d4;\n    rtl_sha1_info = 0x101ce404;\n    rtl_md5_info = 0x101ce434;\n    rtl_rsa_alt_info = 0x101cea78;\n    rtl_ecdsa_info = 0x101ceaa8;\n    rtl_eckeydh_info = 0x101cead8;\n    rtl_eckey_info = 0x101ceb08;\n    rtl_rsa_info = 0x101ceb38;\n    __rom_bss_end_s__ = 0x200f9000;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8bb0d26e868ae95874449e2da5448d78108f1967","subject":"song: remove deleted functions from LD script","message":"song: remove deleted functions from LD script\n","repos":"yusiwen\/libmpdclient,yusiwen\/libmpdclient,sl0th\/libmpdclient,OpenInkpot-archive\/iplinux-libmpdclient,jwise\/libmpdclient,cmende\/libmpdclient,jagleeso\/libmpdclient,cmende\/libmpdclient,sl0th\/libmpdclient,cmende\/libmpdclient,jwise\/libmpdclient,jwise\/libmpdclient,jagleeso\/libmpdclient,psych0tik\/libmpdclient2,yusiwen\/libmpdclient,OpenInkpot-archive\/iplinux-libmpdclient,jagleeso\/libmpdclient,sl0th\/libmpdclient,psych0tik\/libmpdclient2","old_file":"libmpdclient.ld","new_file":"libmpdclient.ld","new_contents":"libmpdclient2 {\nglobal:\n\t\/* mpd\/async.h *\/\n\tmpd_async_new;\n\tmpd_async_free;\n\tmpd_async_get_error;\n\tmpd_async_get_error_message;\n\tmpd_async_get_fd;\n\tmpd_async_events;\n\tmpd_async_io;\n\tmpd_async_send_command_v;\n\tmpd_async_send_command;\n\tmpd_async_recv_line;\n\n\t\/* mpd\/capabilities.h *\/\n\tmpd_send_allowed_commands;\n\tmpd_send_disallowed_commands;\n\tmpd_send_list_url_schemes;\n\tmpd_send_list_tag_types;\n\n\t\/* mpd\/connection.h *\/\n\tmpd_connection_new;\n\tmpd_connection_new_async;\n\tmpd_connection_free;\n\tmpd_connection_set_timeout;\n\tmpd_connection_get_fd;\n\tmpd_connection_get_error;\n\tmpd_connection_get_error_message;\n\tmpd_connection_get_server_error;\n\tmpd_connection_clear_error;\n\tmpd_connection_get_server_version;\n\tmpd_connection_cmp_server_version;\n\n\t\/* mpd\/database.h *\/\n\tmpd_send_list_all;\n\tmpd_send_list_all_meta;\n\tmpd_send_list_meta;\n\tmpd_send_update;\n\tmpd_recv_update_id;\n\tmpd_run_update;\n\n\t\/* mpd\/directory.h *\/\n\tmpd_directory_dup;\n\tmpd_directory_free;\n\tmpd_directory_get_path;\n\tmpd_directory_begin;\n\tmpd_directory_feed;\n\tmpd_recv_directory;\n\n\t\/* mpd\/entity.h *\/\n\tmpd_entity_free;\n\tmpd_entity_get_type;\n\tmpd_entity_get_directory;\n\tmpd_entity_get_song;\n\tmpd_entity_get_playlist;\n\tmpd_entity_begin;\n\tmpd_entity_feed;\n\tmpd_recv_entity;\n\n\t\/* mpd\/idle.h *\/\n\tmpd_idle_name;\n\tmpd_idle_name_parse;\n\tmpd_send_idle;\n\tmpd_send_idle_mask;\n\tmpd_send_noidle;\n\tmpd_idle_parse_pair;\n\tmpd_recv_idle;\n\tmpd_run_idle;\n\tmpd_run_idle_mask;\n\n\t\/* mpd\/list.h *\/\n\tmpd_command_list_begin;\n\tmpd_command_list_end;\n\n\t\/* mpd\/mixer.h *\/\n\tmpd_send_set_volume;\n\tmpd_run_set_volume;\n\n\t\/* mpd\/output.h *\/\n\tmpd_output_begin;\n\tmpd_output_feed;\n\tmpd_output_free;\n\tmpd_output_get_id;\n\tmpd_output_get_name;\n\tmpd_output_get_enabled;\n\tmpd_send_outputs;\n\tmpd_recv_output;\n\tmpd_send_enable_output;\n\tmpd_run_enable_output;\n\tmpd_send_disable_output;\n\tmpd_run_disable_output;\n\n\t\/* mpd\/parser.h *\/\n\tmpd_parser_new;\n\tmpd_parser_free;\n\tmpd_parser_feed;\n\tmpd_parser_is_discrete;\n\tmpd_parser_get_ack;\n\tmpd_parser_get_at;\n\tmpd_parser_get_message;\n\tmpd_parser_get_name;\n\tmpd_parser_get_value;\n\n\t\/* mpd\/password.h *\/\n\tmpd_send_password;\n\tmpd_run_password;\n\n\t\/* mpd\/player.h *\/\n\tmpd_send_current_song;\n\tmpd_run_current_song;\n\tmpd_send_play;\n\tmpd_run_play;\n\tmpd_send_play_pos;\n\tmpd_run_play_pos;\n\tmpd_send_play_id;\n\tmpd_run_play_id;\n\tmpd_send_stop;\n\tmpd_run_stop;\n\tmpd_send_toggle_pause;\n\tmpd_run_toggle_pause;\n\tmpd_send_pause;\n\tmpd_run_pause;\n\tmpd_send_next;\n\tmpd_run_next;\n\tmpd_send_previous;\n\tmpd_run_previous;\n\tmpd_send_seek_pos;\n\tmpd_run_seek_pos;\n\tmpd_send_seek_id;\n\tmpd_run_seek_id;\n\tmpd_send_repeat;\n\tmpd_run_repeat;\n\tmpd_send_random;\n\tmpd_run_random;\n\tmpd_send_single;\n\tmpd_run_single;\n\tmpd_send_consume;\n\tmpd_run_consume;\n\tmpd_send_crossfade;\n\tmpd_run_crossfade;\n\n\t\/* mpd\/playlist.h *\/\n\tmpd_playlist_free;\n\tmpd_playlist_dup;\n\tmpd_playlist_get_path;\n\tmpd_playlist_get_last_modified;\n\tmpd_playlist_begin;\n\tmpd_playlist_feed;\n\tmpd_recv_playlist;\n\tmpd_send_list_playlist;\n\tmpd_send_list_playlist_meta;\n\tmpd_send_playlist_clear;\n\tmpd_run_playlist_clear;\n\tmpd_send_playlist_add;\n\tmpd_run_playlist_add;\n\tmpd_send_playlist_move;\n\tmpd_send_playlist_delete;\n\tmpd_run_playlist_delete;\n\tmpd_send_save;\n\tmpd_run_save;\n\tmpd_send_load;\n\tmpd_run_load;\n\tmpd_send_rename;\n\tmpd_run_rename;\n\tmpd_send_rm;\n\tmpd_run_rm;\n\n\t\/* mpd\/queue.h *\/\n\tmpd_send_list_queue_meta;\n\tmpd_send_get_queue_song_pos;\n\tmpd_send_get_queue_song_id;\n\tmpd_send_queue_changes_meta;\n\tmpd_send_queue_changes_brief;\n\tmpd_recv_queue_change_brief;\n\tmpd_send_add;\n\tmpd_send_add_id;\n\tmpd_recv_song_id;\n\tmpd_run_add_id;\n\tmpd_send_delete;\n\tmpd_send_delete_id;\n\tmpd_send_shuffle;\n\tmpd_run_shuffle;\n\tmpd_send_shuffle_range;\n\tmpd_run_shuffle_range;\n\tmpd_send_clear;\n\tmpd_run_clear;\n\tmpd_send_move;\n\tmpd_run_move;\n\tmpd_send_move_id;\n\tmpd_run_move_id;\n\tmpd_send_swap;\n\tmpd_run_swap;\n\tmpd_send_swap_id;\n\tmpd_run_swap_id;\n\n\t\/* mpd\/recv.h *\/\n\tmpd_recv_pair;\n\tmpd_recv_pair_named;\n\tmpd_return_pair;\n\tmpd_enqueue_pair;\n\n\t\/* mpd\/response.h *\/\n\tmpd_response_finish;\n\tmpd_response_next;\n\n\t\/* mpd\/search.h *\/\n\tmpd_search_db_songs;\n\tmpd_search_playlist_songs;\n\tmpd_search_db_tags;\n\tmpd_count_db_songs;\n\tmpd_search_add_constraint;\n\tmpd_search_commit;\n\tmpd_recv_pair_tag;\n\n\t\/* mpd\/send.h *\/\n\tmpd_send_command;\n\n\t\/* mpd\/song.h *\/\n\tmpd_song_free;\n\tmpd_song_dup;\n\tmpd_song_get_uri;\n\tmpd_song_get_tag;\n\tmpd_song_get_duration;\n\tmpd_song_get_last_modified;\n\tmpd_song_set_pos;\n\tmpd_song_get_pos;\n\tmpd_song_get_id;\n\tmpd_song_begin;\n\tmpd_song_feed;\n\tmpd_recv_song;\n\n\t\/* mpd\/stats.h *\/\n\tmpd_send_stats;\n\tmpd_stats_begin;\n\tmpd_stats_feed;\n\tmpd_recv_stats;\n\tmpd_run_stats;\n\tmpd_stats_free;\n\tmpd_stats_get_number_of_artists;\n\tmpd_stats_get_number_of_albums;\n\tmpd_stats_get_number_of_songs;\n\tmpd_stats_get_uptime;\n\tmpd_stats_get_db_update_time;\n\tmpd_stats_get_play_time;\n\tmpd_stats_get_db_play_time;\n\n\t\/* mpd\/status.h *\/\n\tmpd_status_begin;\n\tmpd_status_feed;\n\tmpd_status_free;\n\tmpd_send_status;\n\tmpd_recv_status;\n\tmpd_run_status;\n\tmpd_status_get_volume;\n\tmpd_status_get_repeat;\n\tmpd_status_get_random;\n\tmpd_status_get_single;\n\tmpd_status_get_consume;\n\tmpd_status_get_queue_length;\n\tmpd_status_get_queue_version;\n\tmpd_status_get_state;\n\tmpd_status_get_crossfade;\n\tmpd_status_get_song_pos;\n\tmpd_status_get_song_id;\n\tmpd_status_get_elapsed_time;\n\tmpd_status_get_total_time;\n\tmpd_status_get_kbit_rate;\n\tmpd_status_get_audio_format;\n\tmpd_status_get_update_id;\n\tmpd_status_get_error;\n\n\t\/* mpd\/tag.h *\/\n\tmpd_tag_name;\n\tmpd_tag_name_parse;\n\nlocal:\n\t*;\n};\n","old_contents":"libmpdclient2 {\nglobal:\n\t\/* mpd\/async.h *\/\n\tmpd_async_new;\n\tmpd_async_free;\n\tmpd_async_get_error;\n\tmpd_async_get_error_message;\n\tmpd_async_get_fd;\n\tmpd_async_events;\n\tmpd_async_io;\n\tmpd_async_send_command_v;\n\tmpd_async_send_command;\n\tmpd_async_recv_line;\n\n\t\/* mpd\/capabilities.h *\/\n\tmpd_send_allowed_commands;\n\tmpd_send_disallowed_commands;\n\tmpd_send_list_url_schemes;\n\tmpd_send_list_tag_types;\n\n\t\/* mpd\/connection.h *\/\n\tmpd_connection_new;\n\tmpd_connection_new_async;\n\tmpd_connection_free;\n\tmpd_connection_set_timeout;\n\tmpd_connection_get_fd;\n\tmpd_connection_get_error;\n\tmpd_connection_get_error_message;\n\tmpd_connection_get_server_error;\n\tmpd_connection_clear_error;\n\tmpd_connection_get_server_version;\n\tmpd_connection_cmp_server_version;\n\n\t\/* mpd\/database.h *\/\n\tmpd_send_list_all;\n\tmpd_send_list_all_meta;\n\tmpd_send_list_meta;\n\tmpd_send_update;\n\tmpd_recv_update_id;\n\tmpd_run_update;\n\n\t\/* mpd\/directory.h *\/\n\tmpd_directory_dup;\n\tmpd_directory_free;\n\tmpd_directory_get_path;\n\tmpd_directory_begin;\n\tmpd_directory_feed;\n\tmpd_recv_directory;\n\n\t\/* mpd\/entity.h *\/\n\tmpd_entity_free;\n\tmpd_entity_get_type;\n\tmpd_entity_get_directory;\n\tmpd_entity_get_song;\n\tmpd_entity_get_playlist;\n\tmpd_entity_begin;\n\tmpd_entity_feed;\n\tmpd_recv_entity;\n\n\t\/* mpd\/idle.h *\/\n\tmpd_idle_name;\n\tmpd_idle_name_parse;\n\tmpd_send_idle;\n\tmpd_send_idle_mask;\n\tmpd_send_noidle;\n\tmpd_idle_parse_pair;\n\tmpd_recv_idle;\n\tmpd_run_idle;\n\tmpd_run_idle_mask;\n\n\t\/* mpd\/list.h *\/\n\tmpd_command_list_begin;\n\tmpd_command_list_end;\n\n\t\/* mpd\/mixer.h *\/\n\tmpd_send_set_volume;\n\tmpd_run_set_volume;\n\n\t\/* mpd\/output.h *\/\n\tmpd_output_begin;\n\tmpd_output_feed;\n\tmpd_output_free;\n\tmpd_output_get_id;\n\tmpd_output_get_name;\n\tmpd_output_get_enabled;\n\tmpd_send_outputs;\n\tmpd_recv_output;\n\tmpd_send_enable_output;\n\tmpd_run_enable_output;\n\tmpd_send_disable_output;\n\tmpd_run_disable_output;\n\n\t\/* mpd\/parser.h *\/\n\tmpd_parser_new;\n\tmpd_parser_free;\n\tmpd_parser_feed;\n\tmpd_parser_is_discrete;\n\tmpd_parser_get_ack;\n\tmpd_parser_get_at;\n\tmpd_parser_get_message;\n\tmpd_parser_get_name;\n\tmpd_parser_get_value;\n\n\t\/* mpd\/password.h *\/\n\tmpd_send_password;\n\tmpd_run_password;\n\n\t\/* mpd\/player.h *\/\n\tmpd_send_current_song;\n\tmpd_run_current_song;\n\tmpd_send_play;\n\tmpd_run_play;\n\tmpd_send_play_pos;\n\tmpd_run_play_pos;\n\tmpd_send_play_id;\n\tmpd_run_play_id;\n\tmpd_send_stop;\n\tmpd_run_stop;\n\tmpd_send_toggle_pause;\n\tmpd_run_toggle_pause;\n\tmpd_send_pause;\n\tmpd_run_pause;\n\tmpd_send_next;\n\tmpd_run_next;\n\tmpd_send_previous;\n\tmpd_run_previous;\n\tmpd_send_seek_pos;\n\tmpd_run_seek_pos;\n\tmpd_send_seek_id;\n\tmpd_run_seek_id;\n\tmpd_send_repeat;\n\tmpd_run_repeat;\n\tmpd_send_random;\n\tmpd_run_random;\n\tmpd_send_single;\n\tmpd_run_single;\n\tmpd_send_consume;\n\tmpd_run_consume;\n\tmpd_send_crossfade;\n\tmpd_run_crossfade;\n\n\t\/* mpd\/playlist.h *\/\n\tmpd_playlist_free;\n\tmpd_playlist_dup;\n\tmpd_playlist_get_path;\n\tmpd_playlist_get_last_modified;\n\tmpd_playlist_begin;\n\tmpd_playlist_feed;\n\tmpd_recv_playlist;\n\tmpd_send_list_playlist;\n\tmpd_send_list_playlist_meta;\n\tmpd_send_playlist_clear;\n\tmpd_run_playlist_clear;\n\tmpd_send_playlist_add;\n\tmpd_run_playlist_add;\n\tmpd_send_playlist_move;\n\tmpd_send_playlist_delete;\n\tmpd_run_playlist_delete;\n\tmpd_send_save;\n\tmpd_run_save;\n\tmpd_send_load;\n\tmpd_run_load;\n\tmpd_send_rename;\n\tmpd_run_rename;\n\tmpd_send_rm;\n\tmpd_run_rm;\n\n\t\/* mpd\/queue.h *\/\n\tmpd_send_list_queue_meta;\n\tmpd_send_get_queue_song_pos;\n\tmpd_send_get_queue_song_id;\n\tmpd_send_queue_changes_meta;\n\tmpd_send_queue_changes_brief;\n\tmpd_recv_queue_change_brief;\n\tmpd_send_add;\n\tmpd_send_add_id;\n\tmpd_recv_song_id;\n\tmpd_run_add_id;\n\tmpd_send_delete;\n\tmpd_send_delete_id;\n\tmpd_send_shuffle;\n\tmpd_run_shuffle;\n\tmpd_send_shuffle_range;\n\tmpd_run_shuffle_range;\n\tmpd_send_clear;\n\tmpd_run_clear;\n\tmpd_send_move;\n\tmpd_run_move;\n\tmpd_send_move_id;\n\tmpd_run_move_id;\n\tmpd_send_swap;\n\tmpd_run_swap;\n\tmpd_send_swap_id;\n\tmpd_run_swap_id;\n\n\t\/* mpd\/recv.h *\/\n\tmpd_recv_pair;\n\tmpd_recv_pair_named;\n\tmpd_return_pair;\n\tmpd_enqueue_pair;\n\n\t\/* mpd\/response.h *\/\n\tmpd_response_finish;\n\tmpd_response_next;\n\n\t\/* mpd\/search.h *\/\n\tmpd_search_db_songs;\n\tmpd_search_playlist_songs;\n\tmpd_search_db_tags;\n\tmpd_count_db_songs;\n\tmpd_search_add_constraint;\n\tmpd_search_commit;\n\tmpd_recv_pair_tag;\n\n\t\/* mpd\/send.h *\/\n\tmpd_send_command;\n\n\t\/* mpd\/song.h *\/\n\tmpd_song_free;\n\tmpd_song_dup;\n\tmpd_song_get_uri;\n\tmpd_song_add_tag;\n\tmpd_song_clear_tag;\n\tmpd_song_get_tag;\n\tmpd_song_get_duration;\n\tmpd_song_get_last_modified;\n\tmpd_song_set_pos;\n\tmpd_song_get_pos;\n\tmpd_song_get_id;\n\tmpd_song_begin;\n\tmpd_song_feed;\n\tmpd_recv_song;\n\n\t\/* mpd\/stats.h *\/\n\tmpd_send_stats;\n\tmpd_stats_begin;\n\tmpd_stats_feed;\n\tmpd_recv_stats;\n\tmpd_run_stats;\n\tmpd_stats_free;\n\tmpd_stats_get_number_of_artists;\n\tmpd_stats_get_number_of_albums;\n\tmpd_stats_get_number_of_songs;\n\tmpd_stats_get_uptime;\n\tmpd_stats_get_db_update_time;\n\tmpd_stats_get_play_time;\n\tmpd_stats_get_db_play_time;\n\n\t\/* mpd\/status.h *\/\n\tmpd_status_begin;\n\tmpd_status_feed;\n\tmpd_status_free;\n\tmpd_send_status;\n\tmpd_recv_status;\n\tmpd_run_status;\n\tmpd_status_get_volume;\n\tmpd_status_get_repeat;\n\tmpd_status_get_random;\n\tmpd_status_get_single;\n\tmpd_status_get_consume;\n\tmpd_status_get_queue_length;\n\tmpd_status_get_queue_version;\n\tmpd_status_get_state;\n\tmpd_status_get_crossfade;\n\tmpd_status_get_song_pos;\n\tmpd_status_get_song_id;\n\tmpd_status_get_elapsed_time;\n\tmpd_status_get_total_time;\n\tmpd_status_get_kbit_rate;\n\tmpd_status_get_audio_format;\n\tmpd_status_get_update_id;\n\tmpd_status_get_error;\n\n\t\/* mpd\/tag.h *\/\n\tmpd_tag_name;\n\tmpd_tag_name_parse;\n\nlocal:\n\t*;\n};\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"8673bbdd555e8fdbae3386b85eccf96f54c8c330","subject":"Update linker script to accommodate for larger CCFG size","message":"Update linker script to accommodate for larger CCFG size\n","repos":"bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,bluerover\/6lbr,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr","old_file":"cpu\/cc26xx\/cc26xx.ld","new_file":"cpu\/cc26xx\/cc26xx.ld","new_contents":"\/*\n * Copyright (c) 2014, Texas Instruments Incorporated - http:\/\/www.ti.com\/\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\n\/* CC26XX linker script *\/\n\n\/* Entry Point *\/\nENTRY(ResetISR)\n\nMEMORY\n{\n    \/* Flash Size 128 KB minus the CCA area below (88 bytes) *\/\n    FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x0001FFA8\n\n    \/*\n     * Customer Configuration Area and Bootloader Backdoor configuration\n     * in flash, up to 88 bytes\n     *\/\n    FLASH_CCFG (RX) : ORIGIN = 0x0001FFA8, LENGTH = 88\n\n    \/* RAM Size 20KB (PG2.1) *\/\n    SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00005000\n}\n\n\/*. Highest address of the stack. Used in startup file .*\/\n_estack = ORIGIN(SRAM) + LENGTH(SRAM); \/* End of SRAM *\/\n\n\/*. Generate a link error if heap and stack don\u2019t fit into RAM .*\/\n_Min_Heap_Size = 0;\n_Min_Stack_Size = 0x100;\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH = 0\n\n    .data :\n    {\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > SRAM AT > FLASH\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n    } > FLASH\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n    .ccfg :\n    {\n        KEEP(*(.ccfg))\n    } > FLASH_CCFG\n\n    \/* User_heap_stack section, used to check that there is enough RAM left *\/\n    ._user_heap_stack :\n    {\n      . = ALIGN(4);\n      . = . + _Min_Heap_Size;\n      . = . + _Min_Stack_Size;\n      . = ALIGN(4);\n    } >SRAM\n}\n","old_contents":"\/*\n * Copyright (c) 2014, Texas Instruments Incorporated - http:\/\/www.ti.com\/\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\n\/* CC26XX linker script *\/\n\n\/* Entry Point *\/\nENTRY(ResetISR)\n\nMEMORY\n{\n    \/* Flash Size 128 KB minus the CCA area below (76 bytes) *\/\n    FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x0001FFAC\n\n    \/*\n     * Customer Configuration Area and Bootloader Backdoor configuration\n     * in flash, up to 80 bytes\n     *\/\n    FLASH_CCFG (RX) : ORIGIN = 0x0001FFAC, LENGTH = 84\n\n    \/* RAM Size 20KB (PG2.1) *\/\n    SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00005000\n}\n\n\/*. Highest address of the stack. Used in startup file .*\/\n_estack = ORIGIN(SRAM) + LENGTH(SRAM); \/* End of SRAM *\/\n\n\/*. Generate a link error if heap and stack don\u2019t fit into RAM .*\/\n_Min_Heap_Size = 0;\n_Min_Stack_Size = 0x100;\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH = 0\n\n    .data :\n    {\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > SRAM AT > FLASH\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n    } > FLASH\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n    .ccfg :\n    {\n        KEEP(*(.ccfg))\n    } > FLASH_CCFG\n\n    \/* User_heap_stack section, used to check that there is enough RAM left *\/\n    ._user_heap_stack :\n    {\n      . = ALIGN(4);\n      . = . + _Min_Heap_Size;\n      . = . + _Min_Stack_Size;\n      . = ALIGN(4);\n    } >SRAM\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"f6ef7bd127ec984244bd0b2a97b995813fe48edc","subject":"fix MX to build with plib","message":"fix MX to build with plib\n","repos":"EmbeddedMan\/chipKIT-core,chipKIT32\/chipkit-core,majenkotech\/chipKIT-core,pontech\/chipKIT-core,UECIDE\/chipKIT-core,adamwolf\/chipKIT-core,UECIDE\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,chipKIT32\/chipkit-core,UECIDE\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,ricklon\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core,chipKIT32\/chipkit-core,adamwolf\/chipKIT-core,pontech\/chipKIT-core,adamwolf\/chipKIT-core,majenkotech\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,pontech\/chipKIT-core,UECIDE\/chipKIT-core,chipKIT32\/chipkit-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,chipKIT32\/chipkit-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,pontech\/chipKIT-core,ricklon\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core,UECIDE\/chipKIT-core","old_file":"pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_file":"pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_contents":"\/************************************************************************\n *\tchipKIT-applicaiton-COMMON.ld\n *\t\n *\tThis is the common part of the linker script shared\n *\tacross all chipKIT PIC32 processors \/ boards.\n *\t\n ************************************************************************\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\n * \tThis library is free software; you can redistribute it and\/or\n *  modify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\t\n *\tThis library is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\n *\tLesser General Public License for more details.\n *\t\n *\tYou should have received a copy of the GNU Lesser General\n *\tPublic License along with this library; if not, write to the\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\n *\tBoston, MA\t02111-1307\tUSA\n *\t\n *\t\n ************************************************************************\n *\tEdit History\n ************************************************************************\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\n ************************************************************************\n *\/\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\nINPUT(\"crtbegin.o\")\nINPUT(\"crtend.o\")\nINPUT(\"crtn.o\")\nOPTIONAL(\"libmchp_peripheral.a\") \n\n\/*************************************************************************\n * Start the layout of memory, the sections...\n *************************************************************************\/\nSECTIONS\n{\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\n  {\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n .image_ptr_table _IMAGE_PTR_TABLE :\n  {\n    LONG(_ebase_address)\t\n    LONG(_image_header_info)\n  } > exception_mem\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n\n  .vector_0 _ebase_address + 0x200 :\n  {\n    _new_vector_0 = . ;\n\tKEEP(*(.vector_new_0))\n    _original_vector_0 = . ;\n\tKEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_new_1))\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_new_2))\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_new_3))\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_new_4))\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_new_5))\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_new_6))\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_new_7))\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_new_8))\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_new_9))\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_new_10))\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_new_11))\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_new_12))\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_new_13))\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_new_14))\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_new_15))\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_new_16))\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_new_17))\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_new_18))\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_new_19))\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_new_20))\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_new_21))\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_new_22))\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_new_23))\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_new_24))\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_new_25))\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_new_26))\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_new_27))\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_new_28))\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_new_29))\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_new_30))\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_new_31))\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_new_32))\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_new_33))\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_new_34))\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_new_35))\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_new_36))\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_new_37))\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_new_38))\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_new_39))\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_new_40))\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_new_41))\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_new_42))\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_new_43))\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_new_44))\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_new_45))\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_new_46))\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_new_47))\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_new_48))\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_new_49))\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_new_50))\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_new_51))\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_new_52))\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_new_53))\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_new_54))\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_new_55))\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_new_56))\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_new_57))\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_new_58))\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_new_59))\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_new_60))\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_new_61))\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_new_62))\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_new_63))\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.stub .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n    *(.gnu.warning)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n    . = ALIGN(4) ;\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  \/* Read-only sections *\/\n  .header_info ALIGN(4) :\n  {\n    _image_header_info = . ;\n    LONG(SIZEOF(.header_info))                 \/* size of this structure       *\/\n    LONG(0xFFFFFFFF)                           \/* bootloader version           *\/\n    KEEP(*(.mpide_version *.mpide_version.*))  \/* MPIDE build version          *\/\n    LONG(0xFFFFFFFF)                           \/* booloader capabilities       *\/\n    LONG(0xFFFFFFFF)                           \/* VID and PID                  *\/\n    LONG(_IMAGE_TYPE)                          \/* image type and options       *\/\n    LONG(_JUMP_ADDR)                           \/* image execution address      *\/\n    LONG(_ebase_address)                       \/* image base address           *\/\n    LONG(_IMAGE_FLASH_SIZE)                    \/* size of image flash used     *\/\n    LONG(ORIGIN(kseg0_eeprom_mem))             \/* eeprom location              *\/\n    LONG(LENGTH(kseg0_eeprom_mem))             \/* eeprom size                  *\/   \n    LONG(ORIGIN(configsfrs))                   \/* config bits location         *\/\n    LONG(LENGTH(configsfrs))                   \/* config bits size             *\/\n    LONG(_ram_header_addr)                     \/* ram header pointer           *\/\n    LONG(SIZEOF(.ram_exchange_data))           \/* ram Header size              *\/\n    LONG(0xFFFFFFFF)                           \/* what the bootloader skips    *\/\n    LONG(_original_vector_0)                   \/* the original vector 0        *\/\n    LONG(_new_vector_0)                        \/* new\/indirect vector 0        *\/\n    LONG(_vector_spacing << 5)                 \/* spacing of both org\/new vec  *\/\n    _image_header_info_end = . ;\n  } > kseg0_program_mem\n  ASSERT (SIZEOF(.header_info) == 76, \"MPIDE Version not specfied correctly\")\n\n  .rodata  ALIGN(4) :\n  {\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n  \n  .ram_exchange_data (NOLOAD) :\n  {\n    _ram_header_addr = . ;\n    . += 8 ;\n  } >kseg1_data_mem\n\n  \/* Persistent data - Use the new C 'persistent' attribute instead. *\/\n  .persist ALIGN(4) (NOLOAD) :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4) ;\n    _persist_end = .;\n  } >kseg1_data_mem\n\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\n\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\n\n  .protected_bootloader ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : 0x0);\n  }\n\n  \/*\n   *  Note that input sections named .data* are not mapped here.\n   *  The best-fit allocator locates them, so that they may flow\n   *  around absolute sections as needed.\n   *\/\n  .data :\n  {\n    _data_begin = . ;\n    *( .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  _data_image_begin = LOADADDR(.data) ;\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(4) ;\n    _sdata_end = . ;\n  } >kseg1_data_mem\n\n  .lit8           :\n  {\n    *(.lit8)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem \n\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    . = ALIGN(4) ;\n    _sbss_end = . ;\n  } >kseg1_data_mem\n\n  .bss   :\n  {\n    *(.dynbss)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n\n  \/*\n   *  The heap and stack are best-fit allocated by the linker after other\n   *  data and bss sections have been allocated.\n   *\/\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\n   * RAM functions are now allocated by the linker. The linker generates\n   * _ramfunc_begin and _bmxdkpba_address symbols depending on the\n   * location of RAM functions.\n   *\/\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n\n    \/* The .pdr section belongs in the absolute section *\/\n    \n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n\n  .gcc_compiled_long32 : { KEEP(*(.gcc_compiled_long32)) }\n  .gcc_compiled_long64 : { KEEP(*(.gcc_compiled_long64)) }\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0  : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) *(.discard) }\n}\n","old_contents":"\/************************************************************************\n *\tchipKIT-applicaiton-COMMON.ld\n *\t\n *\tThis is the common part of the linker script shared\n *\tacross all chipKIT PIC32 processors \/ boards.\n *\t\n ************************************************************************\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\n * \tThis library is free software; you can redistribute it and\/or\n *  modify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\t\n *\tThis library is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\n *\tLesser General Public License for more details.\n *\t\n *\tYou should have received a copy of the GNU Lesser General\n *\tPublic License along with this library; if not, write to the\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\n *\tBoston, MA\t02111-1307\tUSA\n *\t\n *\t\n ************************************************************************\n *\tEdit History\n ************************************************************************\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\n ************************************************************************\n *\/\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\nINPUT(\"crtbegin.o\")\nINPUT(\"crtend.o\")\nINPUT(\"crtn.o\")\nOPTIONAL(\"libmchp_peripheral.a\") \n\n\/*************************************************************************\n * Start the layout of memory, the sections...\n *************************************************************************\/\nSECTIONS\n{\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\n  {\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n .image_ptr_table _IMAGE_PTR_TABLE :\n  {\n    LONG(_ebase_address)\t\n    LONG(_image_header_info)\n  } > exception_mem\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n\n  .vector_0 _ebase_address + 0x200 :\n  {\n    _new_vector_0 = . ;\n\tKEEP(*(.vector_new_0))\n    _original_vector_0 = . ;\n\tKEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_new_1))\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_new_2))\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_new_3))\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_new_4))\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_new_5))\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_new_6))\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_new_7))\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_new_8))\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_new_9))\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_new_10))\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_new_11))\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_new_12))\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_new_13))\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_new_14))\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_new_15))\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_new_16))\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_new_17))\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_new_18))\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_new_19))\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_new_20))\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_new_21))\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_new_22))\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_new_23))\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_new_24))\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_new_25))\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_new_26))\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_new_27))\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_new_28))\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_new_29))\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_new_30))\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_new_31))\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_new_32))\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_new_33))\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_new_34))\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_new_35))\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_new_36))\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_new_37))\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_new_38))\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_new_39))\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_new_40))\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_new_41))\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_new_42))\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_new_43))\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_new_44))\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_new_45))\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_new_46))\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_new_47))\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_new_48))\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_new_49))\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_new_50))\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_new_51))\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_new_52))\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_new_53))\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_new_54))\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_new_55))\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_new_56))\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_new_57))\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_new_58))\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_new_59))\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_new_60))\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_new_61))\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_new_62))\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_new_63))\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n    . = ALIGN(4) ;\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  \/* Read-only sections *\/\n  .header_info ALIGN(4) :\n  {\n    _image_header_info = . ;\n    LONG(SIZEOF(.header_info))                 \/* size of this structure       *\/\n    LONG(0xFFFFFFFF)                           \/* bootloader version           *\/\n    KEEP(*(.mpide_version *.mpide_version.*))  \/* MPIDE build version          *\/\n    LONG(0xFFFFFFFF)                           \/* booloader capabilities       *\/\n    LONG(0xFFFFFFFF)                           \/* VID and PID                  *\/\n    LONG(_IMAGE_TYPE)                          \/* image type and options       *\/\n    LONG(_JUMP_ADDR)                           \/* image execution address      *\/\n    LONG(_ebase_address)                       \/* image base address           *\/\n    LONG(_IMAGE_FLASH_SIZE)                    \/* size of image flash used     *\/\n    LONG(ORIGIN(kseg0_eeprom_mem))             \/* eeprom location              *\/\n    LONG(LENGTH(kseg0_eeprom_mem))             \/* eeprom size                  *\/   \n    LONG(ORIGIN(configsfrs))                   \/* config bits location         *\/\n    LONG(LENGTH(configsfrs))                   \/* config bits size             *\/\n    LONG(_ram_header_addr)                     \/* ram header pointer           *\/\n    LONG(SIZEOF(.ram_exchange_data))           \/* ram Header size              *\/\n    LONG(0xFFFFFFFF)                           \/* what the bootloader skips    *\/\n    LONG(_original_vector_0)                   \/* the original vector 0        *\/\n    LONG(_new_vector_0)                        \/* new\/indirect vector 0        *\/\n    LONG(_vector_spacing << 5)                 \/* spacing of both org\/new vec  *\/\n    _image_header_info_end = . ;\n  } > kseg0_program_mem\n  ASSERT (SIZEOF(.header_info) == 76, \"MPIDE Version not specfied correctly\")\n\n  .rodata  ALIGN(4) :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n  \n  .ram_exchange_data (NOLOAD) :\n  {\n    _ram_header_addr = . ;\n    . += 8 ;\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist ALIGN(4) (NOLOAD) :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4) ;\n    _persist_end = .;\n  } >kseg1_data_mem\n\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\n\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\n\n  .data  _protected_end :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n\n  _data_image_begin = LOADADDR(.data) ;\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(4) ;\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n\n  .lit8           :\n  {\n    *(.lit8)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    . = ALIGN(4) ;\n    _sbss_end = . ;\n  } >kseg1_data_mem\n\n  .bss   :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0  : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"234a8743c9533d1b12d7962802869fe68e83179f","subject":"Fix NMI interrupt handler alignment","message":"Fix NMI interrupt handler alignment\n\nas suggested at http:\/\/www.esp8266.com\/viewtopic.php?f=6&t=4675&start=48#p46002\n","repos":"Adam5Wu\/Arduino,KaloNK\/Arduino,sticilface\/Arduino,Juppit\/Arduino,martinayotte\/ESP8266-Arduino,gguuss\/Arduino,wemos\/Arduino,sticilface\/Arduino,quertenmont\/Arduino,Juppit\/Arduino,esp8266\/Arduino,quertenmont\/Arduino,gguuss\/Arduino,hallard\/Arduino,sticilface\/Arduino,toastedcode\/esp8266-Arduino,quertenmont\/Arduino,Juppit\/Arduino,KaloNK\/Arduino,Juppit\/Arduino,NullMedia\/Arduino,NullMedia\/Arduino,wemos\/Arduino,lrmoreno007\/Arduino,lrmoreno007\/Arduino,KaloNK\/Arduino,martinayotte\/ESP8266-Arduino,jes\/Arduino,hallard\/Arduino,me-no-dev\/Arduino,esp8266\/Arduino,me-no-dev\/Arduino,gguuss\/Arduino,me-no-dev\/Arduino,martinayotte\/ESP8266-Arduino,lrmoreno007\/Arduino,NullMedia\/Arduino,jes\/Arduino,toastedcode\/esp8266-Arduino,me-no-dev\/Arduino,toastedcode\/esp8266-Arduino,Lan-Hekary\/Arduino,me-no-dev\/Arduino,martinayotte\/ESP8266-Arduino,esp8266\/Arduino,lrmoreno007\/Arduino,Lan-Hekary\/Arduino,Lan-Hekary\/Arduino,hallard\/Arduino,Lan-Hekary\/Arduino,toastedcode\/esp8266-Arduino,hallard\/Arduino,quertenmont\/Arduino,esp8266\/Arduino,gguuss\/Arduino,Adam5Wu\/Arduino,hallard\/Arduino,NullMedia\/Arduino,KaloNK\/Arduino,KaloNK\/Arduino,wemos\/Arduino,lrmoreno007\/Arduino,gguuss\/Arduino,Juppit\/Arduino,jes\/Arduino,jes\/Arduino,sticilface\/Arduino,Adam5Wu\/Arduino,esp8266\/Arduino,Adam5Wu\/Arduino,Adam5Wu\/Arduino,wemos\/Arduino,jes\/Arduino,sticilface\/Arduino,Lan-Hekary\/Arduino,NullMedia\/Arduino,wemos\/Arduino,quertenmont\/Arduino,toastedcode\/esp8266-Arduino,martinayotte\/ESP8266-Arduino","old_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"6386bafa813910acfecb2b5f1fad409abdabc550","subject":"[KINETIS] Remove extra licensing terms","message":"[KINETIS] Remove extra licensing terms\n\ngit-svn-id: de15d415ffb1bc5d91a165b5b7d2093897d104a2@7156 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"os\/common\/ports\/ARMCMx\/compilers\/GCC\/ld\/MK20DX128.ld","new_file":"os\/common\/ports\/ARMCMx\/compilers\/GCC\/ld\/MK20DX128.ld","new_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * MK20DX128 memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0400;\r\n__process_stack_size__  = 0x0400;\r\n\r\nENTRY(Reset_Handler)\r\n\r\nMEMORY\r\n{\r\n  flash0   : org = 0x00000000, len = 0xF8\r\n  flashcfg : org = 0x00000400, len = 0x10\r\n  flash    : org = 0x00000410, len = 128k - 0x410\r\n  ram      : org = 0x1FFFE000, len = 16k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n  . = 0;\r\n\r\n  .isr : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    KEEP(*(vectors))\r\n  } > flash0\r\n\r\n  .cfmprotect : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    KEEP(*(.cfmconfig))\r\n  } > flashcfg\r\n\r\n  _text = .;\r\n\r\n  constructors : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    PROVIDE(__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE(__init_array_end = .);\r\n  } > flash\r\n\r\n  destructors : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    PROVIDE(__fini_array_start = .);\r\n    KEEP(*(.fini_array))\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    PROVIDE(__fini_array_end = .);\r\n  } > flash\r\n\r\n  .text : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    *(.text)\r\n    *(.text.*)\r\n    *(.rodata)\r\n    *(.rodata.*)\r\n    *(.glue_7t)\r\n    *(.glue_7)\r\n    *(.gcc*)\r\n  } > flash\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > flash\r\n\r\n  .ARM.exidx : {\r\n    PROVIDE(__exidx_start = .);\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    PROVIDE(__exidx_end = .);\r\n  } > flash\r\n\r\n  .eh_frame_hdr :\r\n  {\r\n    *(.eh_frame_hdr)\r\n  } > flash\r\n\r\n  .eh_frame : ONLY_IF_RO\r\n  {\r\n    *(.eh_frame)\r\n  } > flash\r\n\r\n  .textalign : ONLY_IF_RO\r\n  {\r\n    . = ALIGN(8);\r\n  } > flash\r\n\r\n  _etext = .;\r\n  _textdata = _etext;\r\n\r\n  .stacks :\r\n  {\r\n    . = ALIGN(8);\r\n    __main_stack_base__ = .;\r\n    . += __main_stack_size__;\r\n    . = ALIGN(8);\r\n    __main_stack_end__ = .;\r\n    __process_stack_base__ = .;\r\n    __main_thread_stack_base__ = .;\r\n    . += __process_stack_size__;\r\n    . = ALIGN(8);\r\n    __process_stack_end__ = .;\r\n    __main_thread_stack_end__ = .;\r\n  } > ram\r\n\r\n  .data :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE(_data = .);\r\n    *(.data)\r\n    . = ALIGN(4);\r\n    *(.data.*)\r\n    . = ALIGN(4);\r\n    *(.ramtext)\r\n    . = ALIGN(4);\r\n    PROVIDE(_edata = .);\r\n  } > ram AT > flash\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE(_bss_start = .);\r\n    *(.bss)\r\n    . = ALIGN(4);\r\n    *(.bss.*)\r\n    . = ALIGN(4);\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    PROVIDE(_bss_end = .);\r\n  } > ram\r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__;\r\n","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n\r\n                                      ---\r\n\r\n    A special exception to the GPL can be applied should you wish to distribute\r\n    a combined work that includes ChibiOS\/RT, without being obliged to provide\r\n    the source code for any proprietary components. See the file exception.txt\r\n    for full details of how and when the exception can be applied.\r\n*\/\r\n\r\n\/*\r\n * MK20DX128 memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0400;\r\n__process_stack_size__  = 0x0400;\r\n\r\nENTRY(Reset_Handler)\r\n\r\nMEMORY\r\n{\r\n  flash0   : org = 0x00000000, len = 0xF8\r\n  flashcfg : org = 0x00000400, len = 0x10\r\n  flash    : org = 0x00000410, len = 128k - 0x410\r\n  ram      : org = 0x1FFFE000, len = 16k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n  . = 0;\r\n\r\n  .isr : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    KEEP(*(vectors))\r\n  } > flash0\r\n\r\n  .cfmprotect : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    KEEP(*(.cfmconfig))\r\n  } > flashcfg\r\n\r\n  _text = .;\r\n\r\n  constructors : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    PROVIDE(__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE(__init_array_end = .);\r\n  } > flash\r\n\r\n  destructors : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    PROVIDE(__fini_array_start = .);\r\n    KEEP(*(.fini_array))\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    PROVIDE(__fini_array_end = .);\r\n  } > flash\r\n\r\n  .text : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    *(.text)\r\n    *(.text.*)\r\n    *(.rodata)\r\n    *(.rodata.*)\r\n    *(.glue_7t)\r\n    *(.glue_7)\r\n    *(.gcc*)\r\n  } > flash\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > flash\r\n\r\n  .ARM.exidx : {\r\n    PROVIDE(__exidx_start = .);\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    PROVIDE(__exidx_end = .);\r\n  } > flash\r\n\r\n  .eh_frame_hdr :\r\n  {\r\n    *(.eh_frame_hdr)\r\n  } > flash\r\n\r\n  .eh_frame : ONLY_IF_RO\r\n  {\r\n    *(.eh_frame)\r\n  } > flash\r\n\r\n  .textalign : ONLY_IF_RO\r\n  {\r\n    . = ALIGN(8);\r\n  } > flash\r\n\r\n  _etext = .;\r\n  _textdata = _etext;\r\n\r\n  .stacks :\r\n  {\r\n    . = ALIGN(8);\r\n    __main_stack_base__ = .;\r\n    . += __main_stack_size__;\r\n    . = ALIGN(8);\r\n    __main_stack_end__ = .;\r\n    __process_stack_base__ = .;\r\n    __main_thread_stack_base__ = .;\r\n    . += __process_stack_size__;\r\n    . = ALIGN(8);\r\n    __process_stack_end__ = .;\r\n    __main_thread_stack_end__ = .;\r\n  } > ram\r\n\r\n  .data :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE(_data = .);\r\n    *(.data)\r\n    . = ALIGN(4);\r\n    *(.data.*)\r\n    . = ALIGN(4);\r\n    *(.ramtext)\r\n    . = ALIGN(4);\r\n    PROVIDE(_edata = .);\r\n  } > ram AT > flash\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE(_bss_start = .);\r\n    *(.bss)\r\n    . = ALIGN(4);\r\n    *(.bss.*)\r\n    . = ALIGN(4);\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    PROVIDE(_bss_end = .);\r\n  } > ram\r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__;\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"da30dbea4af4fa92ecec3ee71b1442f2d8129ddb","subject":"Fix comment in linker script","message":"Fix comment in linker script\n","repos":"me-no-dev\/Arduino,wemos\/Arduino,Juppit\/Arduino,Lan-Hekary\/Arduino,Cloudino\/Arduino,Cloudino\/Arduino,Links2004\/Arduino,Adam5Wu\/Arduino,NullMedia\/Arduino,Cloudino\/Arduino,chrisfraser\/Arduino,lrmoreno007\/Arduino,Links2004\/Arduino,KaloNK\/Arduino,me-no-dev\/Arduino,Cloudino\/Arduino,quertenmont\/Arduino,Cloudino\/Arduino,toastedcode\/esp8266-Arduino,jes\/Arduino,esp8266\/Arduino,Cloudino\/Cloudino-Arduino-IDE,Juppit\/Arduino,hallard\/Arduino,NullMedia\/Arduino,chrisfraser\/Arduino,jes\/Arduino,edog1973\/Arduino,chrisfraser\/Arduino,CanTireInnovations\/Arduino,hallard\/Arduino,Lan-Hekary\/Arduino,NullMedia\/Arduino,Links2004\/Arduino,Cloudino\/Cloudino-Arduino-IDE,lrmoreno007\/Arduino,NullMedia\/Arduino,NextDevBoard\/Arduino,gguuss\/Arduino,NextDevBoard\/Arduino,toastedcode\/esp8266-Arduino,Cloudino\/Arduino,Adam5Wu\/Arduino,martinayotte\/ESP8266-Arduino,Cloudino\/Cloudino-Arduino-IDE,martinayotte\/ESP8266-Arduino,wemos\/Arduino,CanTireInnovations\/Arduino,me-no-dev\/Arduino,gguuss\/Arduino,sticilface\/Arduino,CanTireInnovations\/Arduino,Links2004\/Arduino,quertenmont\/Arduino,sticilface\/Arduino,me-no-dev\/Arduino,hallard\/Arduino,sticilface\/Arduino,esp8266\/Arduino,edog1973\/Arduino,KaloNK\/Arduino,wemos\/Arduino,chrisfraser\/Arduino,martinayotte\/ESP8266-Arduino,Cloudino\/Cloudino-Arduino-IDE,wemos\/Arduino,NextDevBoard\/Arduino,esp8266\/Arduino,Adam5Wu\/Arduino,lrmoreno007\/Arduino,gguuss\/Arduino,sticilface\/Arduino,hallard\/Arduino,toastedcode\/esp8266-Arduino,chrisfraser\/Arduino,edog1973\/Arduino,KaloNK\/Arduino,edog1973\/Arduino,Lan-Hekary\/Arduino,jes\/Arduino,esp8266\/Arduino,toastedcode\/esp8266-Arduino,CanTireInnovations\/Arduino,lrmoreno007\/Arduino,gguuss\/Arduino,Cloudino\/Arduino,Adam5Wu\/Arduino,Cloudino\/Cloudino-Arduino-IDE,NextDevBoard\/Arduino,CanTireInnovations\/Arduino,Lan-Hekary\/Arduino,Juppit\/Arduino,gguuss\/Arduino,jes\/Arduino,Juppit\/Arduino,toastedcode\/esp8266-Arduino,martinayotte\/ESP8266-Arduino,Links2004\/Arduino,quertenmont\/Arduino,Cloudino\/Cloudino-Arduino-IDE,esp8266\/Arduino,hallard\/Arduino,Adam5Wu\/Arduino,edog1973\/Arduino,Juppit\/Arduino,martinayotte\/ESP8266-Arduino,wemos\/Arduino,KaloNK\/Arduino,quertenmont\/Arduino,NullMedia\/Arduino,jes\/Arduino,CanTireInnovations\/Arduino,NextDevBoard\/Arduino,sticilface\/Arduino,lrmoreno007\/Arduino,Lan-Hekary\/Arduino,CanTireInnovations\/Arduino,me-no-dev\/Arduino,quertenmont\/Arduino,KaloNK\/Arduino,Cloudino\/Cloudino-Arduino-IDE","old_file":"tools\/sdk\/ld\/eagle.flash.4m1m.ld","new_file":"tools\/sdk\/ld\/eagle.flash.4m1m.ld","new_contents":"\/* Flash Split for 4M chips *\/\n\/* sketch 1019KB *\/\n\/* empty  2048KB *\/\n\/* spiffs 1004KB *\/\n\/* eeprom 20KB *\/\n\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40201010, len = 0xfeff0\n}\n\nPROVIDE ( _SPIFFS_start = 0x40500000 );\nPROVIDE ( _SPIFFS_end = 0x405FB000 );\nPROVIDE ( _SPIFFS_page = 0x100 );\nPROVIDE ( _SPIFFS_block = 0x2000 );\n\nINCLUDE \"..\/ld\/eagle.app.v6.common.ld\"\n","old_contents":"\/* Flash Split for 4M chips *\/\n\/* sketch 1019KB *\/\n\/* spiffs 3052KB *\/\n\/* eeprom 20KB *\/\n\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40201010, len = 0xfeff0\n}\n\nPROVIDE ( _SPIFFS_start = 0x40500000 );\nPROVIDE ( _SPIFFS_end = 0x405FB000 );\nPROVIDE ( _SPIFFS_page = 0x100 );\nPROVIDE ( _SPIFFS_block = 0x2000 );\n\nINCLUDE \"..\/ld\/eagle.app.v6.common.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"49c1b3a1e61b62a0f3b0953aa3b642d98af6037c","subject":"remove space in xboot.ld","message":"remove space in xboot.ld\n","repos":"xboot\/xboot,xboot\/xboot","old_file":"src\/arch\/arm\/mach-realview\/xboot.ld","new_file":"src\/arch\/arm\/mach-realview\/xboot.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(_start)\r\n\r\n\r\nSTACK_FIQ_SIZE \t= 0x0400;\r\nSTACK_IRQ_SIZE \t= 0x0400;\r\nSTACK_ABT_SIZE \t= 0x0400;\r\nSTACK_UND_SIZE \t= 0x0400;\r\nSTACK_SRV_SIZE \t= 0x2000;\r\n\r\n\r\nMEMORY\r\n{\r\n\trom (rx)\t: org = 0x00000000, len = 0x04000000\t\/* 64 MB *\/\r\n\tram (rwx)\t: org = 0x04000000, len = 0x04000000\t\/* 64 MB *\/\r\n}\r\n\r\nSECTIONS\r\n{   \r\n\t.text :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_start = .);\r\n\t\t.obj\/arch\/arm\/mach-realview\/start.o (.text)\r\n\t\t*(.text)\r\n\t\t*(.init.text)\r\n    \t*(.exit.text)\r\n    \t\r\n    \t. = ALIGN(8);\t\r\n\t\tPROVIDE (__initcall_start = .);\r\n\t\t*(.initcall_0.text)\r\n\t\t*(.initcall_0s.text)\r\n\t\t*(.initcall_1.text)\r\n\t\t*(.initcall_1s.text)\r\n\t\t*(.initcall_2.text)\r\n\t\t*(.initcall_2s.text)\r\n\t\t*(.initcall_3.text)\r\n\t\t*(.initcall_3s.text)\r\n\t\t*(.initcall_4.text)\r\n\t\t*(.initcall_4s.text)\r\n\t\t*(.initcall_5.text)\r\n\t\t*(.initcall_5s.text)\r\n\t\t*(.initcall_6.text)\r\n\t\t*(.initcall_6s.text)\r\n\t\t*(.initcall_7.text)\r\n\t\t*(.initcall_7s.text)\r\n\t\t*(.initcall_8.text)\r\n\t\t*(.initcall_8s.text)\r\n\t\t*(.initcall_9.text)\r\n\t\t*(.initcall_9s.text)\r\n\t\tPROVIDE (__initcall_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__exitcall_start = .);\r\n\t\t*(.exitcall_9s.text)\r\n\t\t*(.exitcall_9.text)\r\n\t\t*(.exitcall_8s.text)\r\n\t\t*(.exitcall_8.text)\r\n\t\t*(.exitcall_7s.text)\r\n\t\t*(.exitcall_7.text)\r\n\t\t*(.exitcall_6s.text)\r\n\t\t*(.exitcall_6.text)\r\n\t\t*(.exitcall_5s.text)\r\n\t\t*(.exitcall_5.text)\r\n\t\t*(.exitcall_4s.text)\r\n\t\t*(.exitcall_4.text)\r\n\t\t*(.exitcall_3s.text)\r\n\t\t*(.exitcall_3.text)\r\n\t\t*(.exitcall_2s.text)\r\n\t\t*(.exitcall_2.text)\r\n\t\t*(.exitcall_1s.text)\r\n\t\t*(.exitcall_1.text)\r\n\t\t*(.exitcall_0s.text)\r\n\t\t*(.exitcall_0.text)\r\n\t\tPROVIDE (__exitcall_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__ramdisk_start = .);\r\n\t\t*(.ramdisk)\r\n\t\tPROVIDE (__ramdisk_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\t*(.rodata);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\t*(.glue_7);\r\n\t\t*(.glue_7t);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_end = .);\r\n\t} > rom\r\n\t\r\n\t.data_shadow ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__data_shadow_start = .);\r\n\t\tPROVIDE (__data_shadow_end = (. + SIZEOF (.data)) );\r\n\t} > rom\r\n\t\r\n\t.data : AT ( ADDR (.data_shadow) )\r\n\t{\r\n\t\tPROVIDE (__data_start = .);\t\r\n\t\t*(.data)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE (__data_end = .);\t\t\r\n\t} > ram\r\n\t\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE (__bss_start = .);\r\n\t\t*(.bss)\r\n\t\t*(.bss.*)\r\n\t\t*(.sbss)\r\n\t\t*(COMMON)\r\n\t\tPROVIDE (__bss_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_start = .);\r\n\t\t*(.heap)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_start = .);\r\n\t\tPROVIDE (__stack_fiq_start = .);\r\n\t\t. += STACK_FIQ_SIZE;\r\n\t\tPROVIDE (__stack_fiq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_irq_start = .);\r\n\t\t. += STACK_IRQ_SIZE;\r\n\t\tPROVIDE (__stack_irq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_abt_start = .);\r\n\t\t. += STACK_ABT_SIZE;\r\n\t\tPROVIDE (__stack_abt_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_und_start = .);\r\n\t\t. += STACK_UND_SIZE;\r\n\t\tPROVIDE (__stack_und_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_srv_start = .);\r\n\t\t. += STACK_SRV_SIZE;\r\n\t\tPROVIDE (__stack_srv_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_end = .);\r\n\t} > ram\r\n\r\n\t\/*\r\n\t * Stabs debugging sections.\r\n\t *\/\r\n\t.stab 0 : { *(.stab) }\r\n\t.stabstr 0 : { *(.stabstr) }\r\n\t.stab.excl 0 : { *(.stab.excl) }\r\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\r\n\t.stab.index 0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment 0 : { *(.comment) }\r\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\r\n\t.debug_info 0 : { *(.debug_info) }\r\n\t.debug_line 0 : { *(.debug_line) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t.debug_aranges 0 : { *(.debug_aranges) }\r\n}\r\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(_start)\r\n\r\n\r\nSTACK_FIQ_SIZE \t= 0x0400;\r\nSTACK_IRQ_SIZE \t= 0x0400;\r\nSTACK_ABT_SIZE \t= 0x0400;\r\nSTACK_UND_SIZE \t= 0x0400;\r\nSTACK_SRV_SIZE \t= 0x2000;\r\n\r\n\r\nMEMORY\r\n{\r\n\trom (rx)\t: org = 0x00000000, len = 0x04000000\t\/* 64 MB *\/\r\n\tram (rwx)\t: org = 0x04000000, len = 0x04000000\t\/* 64 MB *\/\r\n}\r\n\r\nSECTIONS\r\n{   \r\n\t.text :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_start = .);\r\n\t\t.obj\/arch\/arm\/mach-realview\/start.o (.text)\r\n\t\t*(.text)\r\n\t\t*(.init.text)\r\n    \t*(.exit.text)\r\n    \t\r\n    \t. = ALIGN(8);\t\r\n\t\tPROVIDE (__initcall_start = .);\r\n\t\t*(.initcall_0.text)\r\n\t\t*(.initcall_0s.text)\r\n\t\t*(.initcall_1.text)\r\n\t\t*(.initcall_1s.text)\r\n\t\t*(.initcall_2.text)\r\n\t\t*(.initcall_2s.text)\r\n\t\t*(.initcall_3.text)\r\n\t\t*(.initcall_3s.text)\r\n\t\t*(.initcall_4.text)\r\n\t\t*(.initcall_4s.text)\r\n\t\t*(.initcall_5.text)\r\n\t\t*(.initcall_5s.text)\r\n\t\t*(.initcall_6.text)\r\n\t\t*(.initcall_6s.text)\r\n\t\t*(.initcall_7.text)\r\n\t\t*(.initcall_7s.text)\r\n\t\t*(.initcall_8.text)\r\n\t\t*(.initcall_8s.text)\r\n\t\t*(.initcall_9.text)\r\n\t\t*(.initcall_9s.text)\r\n\t\tPROVIDE (__initcall_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__exitcall_start = .);\r\n\t\t*(.exitcall_9s.text)\r\n\t\t*(.exitcall_9.text)\r\n\t\t*(.exitcall_8s.text)\r\n\t\t*(.exitcall_8.text)\r\n\t\t*(.exitcall_7s.text)\r\n\t\t*(.exitcall_7.text)\r\n\t\t*(.exitcall_6s.text)\r\n\t\t*(.exitcall_6.text)\r\n\t\t*(.exitcall_5s.text)\r\n\t\t*(.exitcall_5.text)\r\n\t\t*(.exitcall_4s.text)\r\n\t\t*(.exitcall_4.text)\r\n\t\t*(.exitcall_3s.text)\r\n\t\t*(.exitcall_3.text)\r\n\t\t*(.exitcall_2s.text)\r\n\t\t*(.exitcall_2.text)\r\n\t\t*(.exitcall_1s.text)\r\n\t\t*(.exitcall_1.text)\r\n\t\t*(.exitcall_0s.text)\r\n\t\t*(.exitcall_0.text)\r\n\t\tPROVIDE (__exitcall_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__ramdisk_start = .);\r\n\t\t*(.ramdisk)\r\n\t\tPROVIDE (__ramdisk_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\t*(.rodata);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\t*(.glue_7);\r\n\t\t*(.glue_7t);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_end = .);\r\n\t} > rom\r\n\t\r\n\t.data_shadow ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__data_shadow_start = .);\r\n\t\tPROVIDE (__data_shadow_end = (. + SIZEOF (.data)) );\r\n\t} > rom\r\n\t\r\n\t.data : AT ( ADDR (.data_shadow) )\r\n\t{\r\n\t\tPROVIDE (__data_start = .);\t\r\n\t\t*(.data)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE (__data_end = .);\t\t\r\n\t} > ram\r\n\t\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE (__bss_start = .);\r\n\t\t*(.bss)\r\n\t\t*(.bss.*)\r\n\t\t*(.sbss)\r\n\t\t*(COMMON)\r\n\t\tPROVIDE (__bss_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_start = .);\r\n\t\t*(.heap)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_start = .);\r\n\t\tPROVIDE (__stack_fiq_start = .);\r\n\t\t. += STACK_FIQ_SIZE;\r\n\t\tPROVIDE (__stack_fiq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_irq_start = .);\r\n\t\t. += STACK_IRQ_SIZE;\r\n\t\tPROVIDE (__stack_irq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_abt_start = .);\r\n\t\t. += STACK_ABT_SIZE;\r\n\t\tPROVIDE (__stack_abt_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_und_start = .);\r\n\t\t. += STACK_UND_SIZE;\r\n\t\tPROVIDE (__stack_und_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_srv_start = .);\r\n\t\t. += STACK_SRV_SIZE;\r\n\t\tPROVIDE (__stack_srv_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_end = .);\t\t\r\n\t} > ram\r\n\r\n\t\/*\r\n\t * Stabs debugging sections.\r\n\t *\/\r\n\t.stab 0 : { *(.stab) }\r\n\t.stabstr 0 : { *(.stabstr) }\r\n\t.stab.excl 0 : { *(.stab.excl) }\r\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\r\n\t.stab.index 0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment 0 : { *(.comment) }\r\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\r\n\t.debug_info 0 : { *(.debug_info) }\r\n\t.debug_line 0 : { *(.debug_line) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t.debug_aranges 0 : { *(.debug_aranges) }\t\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"97eb9a455e30ba50713f4505e59570ab2e6b9a85","subject":"Issue #102 chose replacement file as official file. Resolved the conflict.","message":"Issue #102 chose replacement file as official file. Resolved the conflict.\n\n\nFormer-commit-id: a95174d04b09b89e937dd68c0c966b7332571c9e\n","repos":"chipKIT32\/chipkit-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core,chipKIT32\/chipkit-core,adamwolf\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,UECIDE\/chipKIT-core,chipKIT32\/chipkit-core,chipKIT32\/chipkit-core,majenkotech\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,UECIDE\/chipKIT-core,ricklon\/chipKIT-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,ricklon\/chipKIT-core,UECIDE\/chipKIT-core,adamwolf\/chipKIT-core,adamwolf\/chipKIT-core,majenkotech\/chipKIT-core,EmbeddedMan\/chipKIT-core,EmbeddedMan\/chipKIT-core,UECIDE\/chipKIT-core,pontech\/chipKIT-core,pontech\/chipKIT-core,pontech\/chipKIT-core,adamwolf\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,chipKIT32\/chipkit-core,UECIDE\/chipKIT-core","old_file":"pic32\/cores\/pic32\/chipKIT-application-32MX460F512L.ld","new_file":"pic32\/cores\/pic32\/chipKIT-application-32MX460F512L.ld","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\n_ebase_address  = 0x9D000000;\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_RESET_ADDR              = 0x9D001000;\n_EEPROM_ADDR             = 0x9D07F000;\n_BEV_EXCPT_ADDR          = 0xBFC00380;\n_DBG_EXCPT_ADDR          = 0xBFC00480;\n_DBG_CODE_ADDR           = 0xBFC02000;\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7E000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 \n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x8000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\nSECTIONS\n{\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg0_program_mem\n  \n  .eeprom_pic32 _EEPROM_ADDR :\n  { \n    . += 0x1000;\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n  .vector_0 _ebase_address + 0x200 :\n  {\n    KEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n\n    _text_end = . ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }>kseg0_program_mem\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n  }>kseg0_program_mem\n\n\n  \/* Read-only sections *\/\n  .rodata   :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } >kseg1_data_mem\n  .data  ALIGN(4)  :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _data_image_begin = LOADADDR(.data) ;\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit8           :\n  {\n    *(.lit8)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    _sbss_end = . ;\n  } >kseg1_data_mem\n  .bss ALIGN(4)  :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  \/DISCARD\/         : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  \/DISCARD\/         : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","old_contents":"<<<<<<< HEAD\n\/* Default linker script, for normal executables *\/\r\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\r\nOUTPUT_ARCH(pic32mx)\r\nENTRY(_reset)\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 0x800) ;\r\nPROVIDE(_min_heap_size = 0x800) ;\r\n\r\n\/*************************************************************************\r\n * Processor-specific object file.  Contains SFR definitions.\r\n *************************************************************************\/\r\nINPUT(\"processor.o\")\r\n\r\n\/*************************************************************************\r\n * For interrupt vector handling\r\n *************************************************************************\/\r\nPROVIDE(_vector_spacing = 0x00000001);\r\n_ebase_address  = 0x9D000000;\r\n\r\n\/*************************************************************************\r\n * Memory Address Equates\r\n *************************************************************************\/\r\n_RESET_ADDR              = 0x9D001000;\r\n_EEPROM_ADDR             = 0x9D07F000;\r\n_BEV_EXCPT_ADDR          = 0xBFC00380;\r\n_DBG_EXCPT_ADDR          = 0xBFC00480;\r\n_DBG_CODE_ADDR           = 0xBFC02000;\r\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\r\n\r\n\/*************************************************************************\r\n * Memory Regions\r\n *\r\n * Memory regions without attributes cannot be used for orphaned sections.\r\n * Only sections specifically assigned to these regions can be allocated\r\n * into these regions.\r\n *************************************************************************\/\r\nMEMORY\r\n{\r\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7E000\r\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\r\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\r\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\r\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0\r\n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\r\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0\r\n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\r\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\r\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\r\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x8000\r\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\r\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\r\n}\r\n\r\nSECTIONS\r\n{\r\n  \/* Boot Sections *\/\r\n  .reset _RESET_ADDR :\r\n  {\r\n    KEEP(*(.reset))\r\n  } > kseg0_program_mem\r\n\r\n  .eeprom_pic32 _EEPROM_ADDR :\r\n  { \r\n    . += 0x1000;\r\n  } > kseg0_eeprom_mem\r\n\r\n  \/DISCARD\/ : { *(.bev_handler) }\r\n\r\n  .app_excpt _GEN_EXCPT_ADDR :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  } > exception_mem\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  .startup :\r\n  {\r\n    KEEP(*(.startup))\r\n  } > kseg0_program_mem\r\n  \/* Code Sections *\/\r\n\r\n  .text  :\r\n  {\r\n    _text_begin = . ;\r\n\r\n    *(.text .stub .text.* .gnu.linkonce.t.*)\r\n    KEEP (*(.text.*personality*))\r\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\r\n    *(.gnu.warning)\r\n    *(.mips16.fn.*)\r\n    *(.mips16.call.*)\r\n\r\n    _text_end = . ;\r\n  } >kseg0_program_mem =0\r\n\r\n   .init      :\r\n  {\r\n\tKEEP (*crti.o(.init))\r\n\tKEEP (*crtbegin.o(.init))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\r\n\tKEEP (*crtend.o(.init))\r\n    KEEP (*crtn.o(.init))\r\n  }  >kseg0_program_mem\r\n\r\n  .fini       :\r\n  {\r\n    KEEP (*(.fini))\r\n  } >kseg0_program_mem\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  }>kseg0_program_mem\r\n  .init_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  }>kseg0_program_mem\r\n  .fini_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  }>kseg0_program_mem\r\n  .ctors        :\r\n  {\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n  }>kseg0_program_mem\r\n  .dtors          :\r\n  {\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n  }>kseg0_program_mem\r\n\r\n  .preinit_array    :\r\n  {\r\n    KEEP (*(.preinit_array))\r\n  }>kseg0_program_mem\r\n\r\n\r\n  \/* Read-only sections *\/\r\n  .rodata   :\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.rodata1)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n  \/*\r\n   * Small initialized constant global and static data can be placed in the\r\n   * .sdata2 section.  This is different from .sdata, which contains small\r\n   * initialized non-constant global and static data.\r\n   *\/\r\n  .sdata2 ALIGN(4)   :\r\n  {\r\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n  \/*\r\n   * Uninitialized constant global and static data (i.e., variables which will\r\n   * always be zero).  Again, this is different from .sbss, which contains\r\n   * small non-initialized, non-constant global and static data.\r\n   *\/\r\n  .sbss2 ALIGN(4)   :\r\n  {\r\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  .dbg_data (NOLOAD) :\r\n  {\r\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\r\n  } >kseg1_data_mem\r\n\r\n  \/* Persistent data *\/\r\n  .persist :\r\n  {\r\n    _persist_begin = .;\r\n    *(.persist .persist.*)\r\n    _persist_end = .;\r\n  } >kseg1_data_mem\r\n  .data   :\r\n  {\r\n    _data_begin = . ;\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    KEEP (*(.gnu.linkonce.d.*personality*))\r\n\r\n    *(.data1)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n  _data_image_begin = LOADADDR(.data) ;\r\n\r\n  . = .;\r\n  _gp = ALIGN(16) + 0x7ff0;\r\n  .got ALIGN(4)   :\r\n  {\r\n     *(.got.plt) *(.got)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n  \/*\r\n   * We want the small data sections together, so single-instruction offsets\r\n   * can access them all, and initialized data all before uninitialized, so\r\n   * we can shorten the on-disk segment size.\r\n   *\/\r\n  .sdata ALIGN(4)   :\r\n  {\r\n    _sdata_begin = . ;\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n    _sdata_end = . ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n  .lit8           :\r\n  {\r\n    *(.lit8)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n  .lit4           :\r\n  {\r\n    *(.lit4)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n  . = ALIGN (4) ;\r\n  _data_end = . ;\r\n  _bss_begin = . ;\r\n  .sbss ALIGN(4)   :\r\n  {\r\n    _sbss_begin = . ;\r\n    *(.dynsbss)\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    _sbss_end = . ;\r\n  } >kseg1_data_mem\r\n  .bss   :\r\n  {\r\n    *(.dynbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    \/*\r\n     * Align here to ensure that the .bss section occupies space up to\r\n     * _end.  Align after .bss to ensure correct alignment even if the\r\n     * .bss section disappears because there are no input sections.\r\n     *\/\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem\r\n  . = ALIGN(4) ;\r\n  _end = . ;\r\n  _bss_end = . ;\r\n  \/* Heap allocating takes a chunk of memory following BSS *\/\r\n  .heap ALIGN(8) :\r\n  {\r\n    _heap = . ;\r\n    . += _min_heap_size ;\r\n    . = ALIGN(8);\r\n  } >kseg1_data_mem\r\n  \/* Stack allocation follows the heap *\/\r\n  .stack ALIGN(8) :\r\n  {\r\n    _splim = . ;\r\n    _SPLIM = . ;\r\n    . += _min_stack_size ;\r\n    . = ALIGN(8);\r\n  } >kseg1_data_mem\r\n  \/*\r\n   * RAM functions go at the end of our stack and heap allocation.\r\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\r\n   *\/\r\n  .ramfunc ALIGN(2K) :\r\n  {\r\n    _ramfunc_begin = . ;\r\n    *(.ramfunc  .ramfunc.*)\r\n    . = ALIGN(4) ;\r\n    _ramfunc_end = . ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\r\n  _ramfunc_length = SIZEOF(.ramfunc) ;\r\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\r\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\r\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\r\n  \/*\r\n   * The actual top of stack should include the gap between the stack\r\n   * section and the beginning of the .ramfunc section caused by the\r\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\r\n   * do not exist, then the top of the stack should point to the end of\r\n   * the data memory.\r\n   *\/\r\n  _stack = (_ramfunc_length > 0)\r\n         ? _ramfunc_begin - 4\r\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\r\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\r\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\r\n    \/* The .pdr section belongs in the absolute section *\/\r\n    \/DISCARD\/ : { *(.pdr) }\r\n    \/* We don't load .reginfo onto the target, so don't locate it\r\n     * in real memory\r\n     *\/\r\n    \/DISCARD\/ : { *(.reginfo) }\r\n  \/* Stabs debugging sections.  *\/\r\n  .stab          0 : { *(.stab) }\r\n  .stabstr       0 : { *(.stabstr) }\r\n  .stab.excl     0 : { *(.stab.excl) }\r\n  .stab.exclstr  0 : { *(.stab.exclstr) }\r\n  .stab.index    0 : { *(.stab.index) }\r\n  .stab.indexstr 0 : { *(.stab.indexstr) }\r\n  .comment       0 : { *(.comment) }\r\n  \/* DWARF debug sections.\r\n     Symbols in the DWARF debugging sections are relative to the beginning\r\n     of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  \/DISCARD\/         : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  \/DISCARD\/         : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n  \/* DWARF 3 *\/\r\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\r\n  .debug_ranges   0 : { *(.debug_ranges) }\r\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\r\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\r\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\r\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\r\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\r\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\r\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\r\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\r\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\r\n  \/DISCARD\/ : { *(.rel.dyn) }\r\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\r\n}\r\n=======\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\n_ebase_address  = 0x9D000000;\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_RESET_ADDR              = 0x9D001000;\n_EEPROM_ADDR             = 0x9D07F000;\n_BEV_EXCPT_ADDR          = 0xBFC00380;\n_DBG_EXCPT_ADDR          = 0xBFC00480;\n_DBG_CODE_ADDR           = 0xBFC02000;\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7E000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 \n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x8000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\nSECTIONS\n{\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg0_program_mem\n  \n  .eeprom_pic32 _EEPROM_ADDR :\n  { \n    . += 0x1000;\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n  .vector_0 _ebase_address + 0x200 :\n  {\n    KEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n\n    _text_end = . ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }>kseg0_program_mem\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n  }>kseg0_program_mem\n\n\n  \/* Read-only sections *\/\n  .rodata   :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } >kseg1_data_mem\n  .data  ALIGN(4)  :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _data_image_begin = LOADADDR(.data) ;\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit8           :\n  {\n    *(.lit8)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    _sbss_end = . ;\n  } >kseg1_data_mem\n  .bss ALIGN(4)  :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  \/DISCARD\/         : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  \/DISCARD\/         : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n>>>>>>> ac5e8802a617589f724301fdf55b00e83df886f3\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"376e1310f6e108662a1c934ac4355b13e86a0fb6","subject":"soc\/intel_adsp_cavs15: Unbreak newlib linkage","message":"soc\/intel_adsp_cavs15: Unbreak newlib linkage\n\nIn commit efa05d1e42da (\"soc\/intel_adsp: Put initial stack into the\nCPU0 interrupt stack\") the \"_end\" symbol was accidentally removed from\nthe linker script.  Newlib needs this to size its heap.\n\nSigned-off-by: Andy Ross <c70f9a6bf6ee0cd69c8af4ce5e6b131945769315@intel.com>\n","repos":"finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v15\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v15\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n  *\/\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n\n  \/* Initial\/boot stack lives in the CPU0 interrupt stack *\/\n  __stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE;\n\n  _end = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n  *\/\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n\n  \/* Initial\/boot stack lives in the CPU0 interrupt stack *\/\n  __stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8397bc7e9fa8606f87690708c381a56c3e971c66","subject":"updated ldoc config to include lualibs.luadoc","message":"updated ldoc config to include lualibs.luadoc\n","repos":"stevedonovan\/Lake,stevedonovan\/Lake,stevedonovan\/Lake,stevedonovan\/Lake","old_file":"config.ld","new_file":"config.ld","new_contents":"file={'lake.luadoc','lakelibs.luadoc'}\nproject = 'lake'\nreadme = 'doc\/index.md'\ndir = 'out'\nformat = 'discount'\nno_return_or_parms=true\n\n","old_contents":"file='lake.luadoc'\r\nproject = 'lake'\r\nreadme = 'doc\/index.md'\r\ndir = 'out'\r\nformat = 'markdown'\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"9559223c7b4cc56506d04de72149cad58a4817a8","subject":"arm64: linker: define z_mapped_* symbols","message":"arm64: linker: define z_mapped_* symbols\n\nAdd linker symbols corresponding to the start and end of the\nmapped Zephyr image. This is not used by the ARM arch yet, but\nis required to compile the core kernel MMU code.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_NAME))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n    z_mapped_size = z_mapped_end - z_mapped_start;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_NAME))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6607f6600d3c8d02874f03e2ecdf2fd461cba95e","subject":"soc: esp32: Linker script updates to boot with MCUboot","message":"soc: esp32: Linker script updates to boot with MCUboot\n\nThis change creates XiP image with proper LMA and VMA to boot with\nMCUboot\n\nSigned-off-by: Shubham Kulkarni <1478dde7897089bf180c3c690a61b19b869e8abd@espressif.com>\n","repos":"finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg\n#define RAMABLE_REGION_1 dram0_1_seg\n#define RODATA_REGION drom0_0_seg\n#define IRAM_REGION iram0_0_seg\n#define FLASH_CODE_REGION irom0_0_seg\n\n#define ROMABLE_REGION ROM\n\n#ifdef CONFIG_FLASH_SIZE\n#define ROM_SIZE CONFIG_FLASH_SIZE\n#else\n#define ROM_SIZE 0x400000\n#endif\n\n#ifdef CONFIG_BOOTLOADER_ESP_IDF\n#define IROM_SEG_ORG 0x400D0020\n#define IROM_SEG_LEN 0x330000-0x20\n#define IROM_SEG_ALIGN 0x4\n#else\n#define IROM_SEG_ORG 0x400D0000\n#define IROM_SEG_LEN 0x330000\n#define IROM_SEG_ALIGN 0x10000\n#endif\n\nMEMORY\n{\n  mcuboot_hdr (RX): org = 0x0, len = 0x20\n  metadata (RX): org = 0x20, len = 0x20\n  ROM (RX): org = 0x40, len = ROM_SIZE - 0x40\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE5230, len = 0x1BCB0 - 0xEE0 \/* skip data for APP CPU initialization usage *\/\n\n  \/* DROM is the first segment placed in generated binary.\n   * MCUboot binary for ESP32 has image header of 0x20 bytes.\n   * Additional load header of 0x20 bytes are appended to the image.\n   * Hence, an offset of 0x40 is added to DROM segment origin.\n   *\/\n  drom0_0_seg(R): org = 0x3F400040, len = 0x400000 - 0x40\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n  \/* Reserve space for MCUboot header in the binary *\/\n  .mcuboot_header :\n  {\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n    QUAD(0x0)\n  } > mcuboot_hdr\n  .metadata :\n  {\n    \/* Magic byte for load header *\/\n    LONG(0xace637d3)\n\n    \/* Application entry point address *\/\n    KEEP(*(.entry_addr))\n\n    \/* IRAM metadata:\n     * - Destination address (VMA) for IRAM region\n     * - Flash offset (LMA) for start of IRAM region\n     * - Size of IRAM region\n     *\/\n\n    LONG(ADDR(\".iram0.vectors\"))\n    LONG(LOADADDR(\".iram0.vectors\"))\n    LONG(LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - LOADADDR(\".iram0.vectors\"))\n\n    \/* DRAM metadata:\n     * - Destination address (VMA) for DRAM region\n     * - Flash offset (LMA) for start of DRAM region\n     * - Size of DRAM region\n     *\/\n\n    LONG(ADDR(\".dram0.data\"))\n    LONG(LOADADDR(\".dram0.data\"))\n    LONG(LOADADDR(\".dummy.dram.data\") + SIZEOF(\".dummy.dram.data\") - LOADADDR(\".dram0.data\"))\n  } > metadata\n\n#include <linker\/rel-sections.ld>\n  _image_drom_start = LOADADDR(_RODATA_SECTION_NAME);\n  _image_drom_size = LOADADDR(_RODATA_SECTION_NAME) + SIZEOF(_RODATA_SECTION_NAME) - _image_drom_start;\n  _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME);\n\n  \/* NOTE: .rodata section should be the first section in the linker script and no\n   * other section should appear before .rodata section. This is the requirement\n   * to align ROM section to 64K page offset.\n   * Adding .rodata as first section helps to reduce size of generated binary by\n   * few kBs.\n   *\/\n  SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.*) .rodata)\n    *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.*) .rodata.*)\n\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)\n\n  _image_dram_start = LOADADDR(\".dram0.data\");\n  _image_dram_size = LOADADDR(\".dummy.dram.data\") + SIZEOF(\".dummy.dram.data\") - _image_dram_start;\n  _image_dram_vaddr = ADDR(\".dram0.data\");\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libzephyr.a:loader.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    . = ALIGN(4);\n    _dram_data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  #pragma push_macro(\"GROUP_ROM_LINK_IN\")\n  #pragma push_macro(\"ITERABLE_SECTION_ROM\")\n  #undef GROUP_ROM_LINK_IN\n  #undef ITERABLE_SECTION_ROM\n  #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN\n  #define ITERABLE_SECTION_ROM(x,y)\n  #include <linker\/common-rom.ld>\n  #pragma pop_macro(\"GROUP_ROM_LINK_IN\")\n  #pragma pop_macro(\"ITERABLE_SECTION_ROM\")\n  #include <linker\/common-ram.ld>\n\n  __shell_root_cmds_start = __esp_shell_root_cmds_start;\n  __shell_root_cmds_end = __esp_shell_root_cmds_end;\n\n  .dummy.dram.data :\n  {\n    . = ALIGN(4);\n    _data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  _image_iram_start = LOADADDR(\".iram0.vectors\");\n  _image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start;\n  _image_iram_vaddr = ADDR(\".iram0.vectors\");\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:loader.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(rtc_slow_seg)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    \/* Buffer for system heap should be placed in dram0_0_seg *\/\n    *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap)\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(.noinit.*)\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n  _image_irom_start = LOADADDR(\".flash.text\");\n  _image_irom_size = LOADADDR(\".flash.text\") + SIZEOF(\".flash.text\") - _image_irom_start;\n  _image_irom_vaddr = ADDR(\".flash.text\");\n\n  .flash.text : ALIGN(IROM_SEG_ALIGN)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    . = ALIGN(4);\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE5230, len = 0x1BCB0 - 0xEE0 \/* skip data for APP CPU initialization usage *\/\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef ITERABLE_SECTION_RAM_GC_ALLOWED\n#define ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef ITERABLE_SECTION_RAM\n#define ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef ITERABLE_SECTION_ROM\n#define ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    \/* Buffer for system heap should be placed in dram0_0_seg *\/\n    *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap)\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(.noinit.*)\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"22507dd4d14d299a4261e7e46c57d45f78f61fac","subject":"CoreValidation: Fixed RAM size in GNU linker script.","message":"CoreValidation: Fixed RAM size in GNU linker script.\n\nChange-Id: Icb0e5c53cd02f67cf918634e36a89ae980e6f7cf\n","repos":"JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5,ARM-software\/CMSIS_5,ARM-software\/CMSIS_5,JonatanAntoni\/CMSIS_5","old_file":"CMSIS\/CoreValidation\/Tests\/config\/core_m\/rtebuild_ns.ld","new_file":"CMSIS\/CoreValidation\/Tests\/config\/core_m\/rtebuild_ns.ld","new_contents":"\/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.0.0\n * @date     20. May 2019\n ******************************************************************************\/\n\/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n \n\/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*\/\n\n\/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__ROM_BASE = 0x00200000;\n__ROM_SIZE = 0x00200000;\n\n\/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__RAM_BASE = 0x20200000;\n__RAM_SIZE = 0x00200000;\n\n\/*--------------------- Stack \/ Heap Configuration ---------------------------\n; <h> Stack \/ Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n\/*\n;-------------------- <<< end of configuration section >>> --------------------\n*\/\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.vectors))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\/* SG veneers:\n   All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   must be set, either with the command line option \u2018--section-start\u2019 or in a linker script,\n   to indicate where to place these veneers in memory.\n *\/\n\/*\n    .gnu.sgstubs :\n    {\n        . = ALIGN(32);\n    } > FLASH\n*\/\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n    \/** Add each additional data section here *\/\n    \/*\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n    *\/\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n    \/** Add each additional bss section here *\/\n    \/* \n    LONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__) \n    *\/\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\n\t\/* Location counter can end up 2byte aligned with narrow Thumb code but\n\t   __etext is assumed by startup code to be the LMA of a section in RAM\n\t   which must be 4byte aligned *\/\n\t__etext = ALIGN (4);\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data)\n    *(.data.*)\n        \n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n  \/** \n   * Secondary data section, optional \n   * \n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   *\/\n  \/*\n  __etext2 = ALIGN (4);\n\n\t.data2 : AT (__etext2)\n\t{\n    . = ALIGN(4);\n\t\t__data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n\t\t. = ALIGN(4);\n\t\t__data2_end__ = .;\n\n\t} > RAM \n  *\/\n  \n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n    *(.bss)\n\t\t*(.bss.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n  \/**\n   * Secondary bss section, optional \n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   *\/\n  \/*\n\t.bss2 :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss2_start__ = .;\n    *(.bss2)\n\t\t*(.bss2.*)\n\t\t. = ALIGN(4);\n\t\t__bss2_end__ = .;\n\t} > RAM2\n  *\/\n\n\t.heap :\n\t{\n    . = ALIGN(4);\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t. = . + __HEAP_SIZE;\n    . = ALIGN(4);\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t.stack :\n\t{\n    . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE;\n    . = ALIGN(4);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(4);\n    __StackTop = .;\n\t} > RAM\n  PROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.0.0\n * @date     20. May 2019\n ******************************************************************************\/\n\/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n \n\/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*\/\n\n\/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__ROM_BASE = 0x00200000;\n__ROM_SIZE = 0x00200000;\n\n\/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__RAM_BASE = 0x20200000;\n__RAM_SIZE = 0x20200000;\n\n\/*--------------------- Stack \/ Heap Configuration ---------------------------\n; <h> Stack \/ Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; <\/h>\n -----------------------------------------------------------------------------*\/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n\/*\n;-------------------- <<< end of configuration section >>> --------------------\n*\/\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.vectors))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\/* SG veneers:\n   All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   must be set, either with the command line option \u2018--section-start\u2019 or in a linker script,\n   to indicate where to place these veneers in memory.\n *\/\n\/*\n    .gnu.sgstubs :\n    {\n        . = ALIGN(32);\n    } > FLASH\n*\/\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n    \/** Add each additional data section here *\/\n    \/*\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n    *\/\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n    \/** Add each additional bss section here *\/\n    \/* \n    LONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__) \n    *\/\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\n\t\/* Location counter can end up 2byte aligned with narrow Thumb code but\n\t   __etext is assumed by startup code to be the LMA of a section in RAM\n\t   which must be 4byte aligned *\/\n\t__etext = ALIGN (4);\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data)\n    *(.data.*)\n        \n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n  \/** \n   * Secondary data section, optional \n   * \n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   *\/\n  \/*\n  __etext2 = ALIGN (4);\n\n\t.data2 : AT (__etext2)\n\t{\n    . = ALIGN(4);\n\t\t__data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n\t\t. = ALIGN(4);\n\t\t__data2_end__ = .;\n\n\t} > RAM \n  *\/\n  \n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n    *(.bss)\n\t\t*(.bss.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n  \/**\n   * Secondary bss section, optional \n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   *\/\n  \/*\n\t.bss2 :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss2_start__ = .;\n    *(.bss2)\n\t\t*(.bss2.*)\n\t\t. = ALIGN(4);\n\t\t__bss2_end__ = .;\n\t} > RAM2\n  *\/\n\n\t.heap :\n\t{\n    . = ALIGN(4);\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t. = . + __HEAP_SIZE;\n    . = ALIGN(4);\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t.stack :\n\t{\n    . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE;\n    . = ALIGN(4);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(4);\n    __StackTop = .;\n\t} > RAM\n  PROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"fed9087274098ed9a5d0b26d431650cfffea9fdb","subject":"nrf: Add flash section for fatfs for no SD pca10056","message":"nrf: Add flash section for fatfs for no SD pca10056\n","repos":"adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/micropython","old_file":"ports\/nrf\/boards\/nrf52840_1M_256k.ld","new_file":"ports\/nrf\/boards\/nrf52840_1M_256k.ld","new_contents":"\/*\n    GNU linker script for NRF52840 blank w\/ no SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x0E6000 \/* 920 KiB *\/\n    FLASH_FATFS (r) : ORIGIN = 0x000E7000, LENGTH = 0x019000 \/* File system 100 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x040000 \/* 256 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 40K;\n_minimum_heap_size = 128K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52840 blank w\/ no SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x0FF000 \/* 1020 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x040000 \/* 256 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 40K;\n_minimum_heap_size = 128K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"74cc8bee7c56948b24a27e92fe59a89f3006015f","subject":"xtensa: cavs_v20: use uncached addresses to support SMP","message":"xtensa: cavs_v20: use uncached addresses to support SMP\n\nSMP support on cAVS is implemented by using uncached addresses for all\nwritable data sections except for stack, i.e. for .data, .bss and\nsome other specialised ones. So far that has been implemented for\ncAVS 1.5\/1.8. This patch does the same for cAVS 2.0.\n\nSigned-off-by: Kai Vehmanen <7c1f7969959c2510655bc0fc9c602f735b2254b7@linux.intel.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v20\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v20\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs20_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs20_adsp);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .cached :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n\n  . = SEGSTART_UNCACHED;\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  .bss (NOLOAD) : ALIGN(4096)\n  {\n    . = ALIGN(4096);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n  . = SEGSTART_UNCACHED;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#define LP_SRAM_REGION lpram\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n#ifndef CONFIG_SMP\n_memmap_cacheattr_intel_cavs20_adsp = 0xFF42FFF2;\n#else\n\/*\n * FIXME: Make 0xA0000000 - 0xBFFFFFFF to bypass cache under SMP\n * since there is no data cache manipulation for spinlock, kernel\n * object, scheduler, etc...\n *\/\n_memmap_cacheattr_intel_cavs20_adsp = 0xFF22FFF2;\n#endif\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs20_adsp);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .cached :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  .bss (NOLOAD) : ALIGN(4096)\n  {\n    . = ALIGN(4096);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1cc35d601b22b4d9b503442cb8dadfd857200652","subject":"x86: linker.ld: implement linker-defs.h changes","message":"x86: linker.ld: implement linker-defs.h changes\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"mbolivar\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3220,galak\/zephyr,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,punitvara\/zephyr,finikorg\/zephyr,aceofall\/zephyr-iotos,nashif\/zephyr,ldts\/zephyr,nashif\/zephyr,aceofall\/zephyr-iotos,rsalveti\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3220,ldts\/zephyr,kraj\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,rsalveti\/zephyr,runchip\/zephyr-cc3220,mbolivar\/zephyr,nashif\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,fbsder\/zephyr,ldts\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,Vudentz\/zephyr,runchip\/zephyr-cc3220,explora26\/zephyr,finikorg\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,runchip\/zephyr-cc3220,punitvara\/zephyr,zephyriot\/zephyr,rsalveti\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,explora26\/zephyr,galak\/zephyr,zephyriot\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,fbsder\/zephyr,ldts\/zephyr,rsalveti\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,finikorg\/zephyr,mbolivar\/zephyr,aceofall\/zephyr-iotos,punitvara\/zephyr,fbsder\/zephyr,rsalveti\/zephyr,galak\/zephyr,kraj\/zephyr,nashif\/zephyr,nashif\/zephyr,ldts\/zephyr,mbolivar\/zephyr,zephyriot\/zephyr","old_file":"include\/arch\/x86\/linker.ld","new_file":"include\/arch\/x86\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n#define MMU_PAGE_SIZE KB(4)\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROMABLE_REGION start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_X86_MMU\n       \/* Page Tables are located here if MMU is enabled.*\/\n\t. = ALIGN(4096);\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n#endif\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\n\t\/* All stacks go in kernel's noinit, regardless of where they\n\t * were defined.\n\t *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\t__kernel_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\t. = ALIGN(MMU_PAGE_SIZE);\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n#define MMU_PAGE_SIZE KB(4)\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROMABLE_REGION start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_X86_MMU\n       \/* Page Tables are located here if MMU is enabled.*\/\n\t. = ALIGN(4096);\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n#endif\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\tKEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\n\t\/* All stacks go in kernel's noinit, regardless of where they\n\t * were defined.\n\t *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\t__kernel_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t. = ALIGN(MMU_PAGE_SIZE);\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a765511d2bd67878e9ddfaf1da16017c63c55988","subject":"mimxrt\/boards: Set __heap_size__ to 0 in MIMXRT1011.ld.","message":"mimxrt\/boards: Set __heap_size__ to 0 in MIMXRT1011.ld.\n\nDo not use the traditional C heap in order to save memory, because the\ntraditional C heap is unused in MicroPython.\n","repos":"pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython","old_file":"ports\/mimxrt\/boards\/MIMXRT1011.ld","new_file":"ports\/mimxrt\/boards\/MIMXRT1011.ld","new_contents":"\/* 24kiB stack. *\/\n__stack_size__ = 0x6000;\n_estack = __StackTop;\n_sstack = __StackLimit;\n\n\/* Do not use the traditional C heap. *\/\n__heap_size__ = 0;\n\n\/* Use second OCRAM bank for GC heap. *\/\n_gc_heap_start = ORIGIN(m_data2);\n_gc_heap_end = ORIGIN(m_data2) + LENGTH(m_data2);\n","old_contents":"\/* 24kiB stack. *\/\n__stack_size__ = 0x6000;\n_estack = __StackTop;\n_sstack = __StackLimit;\n\n\/* Use second OCRAM bank for GC heap. *\/\n_gc_heap_start = ORIGIN(m_data2);\n_gc_heap_end = ORIGIN(m_data2) + LENGTH(m_data2);\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4e90efa79fe477ca9c3644bf71ca04b2cd651ec4","subject":"linker: set __rom_region_end via an offset from __rom_region_start","message":"linker: set __rom_region_end via an offset from __rom_region_start\n\nCurrently __rom_region_end points to the virtual memory address, while\n__rom_region_start points to the load memory address. In most cases the\ntwo address spaces will be the same. In the case of the infineon xmc4xxx\nseries they can be different because flash can be read via a different\ncachable address space.\n\nEvaluate __rom_region_end as an offset from __rom_region_start to fix this\npossible issue.\n\nSigned-off-by: Andriy Gelman <9b800b50c068448b0612a5bdc33ac199b44926a7@gmail.com>\n","repos":"finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"include\/zephyr\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_file":"include\/zephyr\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/devicetree_regions.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGIONS()\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t__rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\t. = ALIGN(4);\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__text_region_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - ADDR(rom_start));\n\t__rom_region_end = __rom_region_start + . - ADDR(rom_start);\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    GROUP_START(DATA_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_region_start = .;\n\t__data_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\t__data_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    \/* Sections generated from 'zephyr,memory-region' nodes *\/\n    LINKER_DT_SECTIONS()\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/devicetree_regions.h>\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    LINKER_DT_REGIONS()\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t__rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t__text_region_start = .;\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\t. = ALIGN(4);\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__text_region_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t__rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - ADDR(rom_start));\n\t__rom_region_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    GROUP_START(DATA_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_region_start = .;\n\t__data_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\t__data_end = .;\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    \/* Sections generated from 'zephyr,memory-region' nodes *\/\n    LINKER_DT_SECTIONS()\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d8bf500be6010e368fdbb6cbec2de1f46edd501f","subject":"Always exports the impure data size.","message":"Always exports the impure data size.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/armv7m\/target.ld","new_file":"boards\/armv7m\/target.ld","new_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(reset_handler)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc)\n\n\/* include device specific memory map *\/\nINCLUDE memory_map.ld\n\n__top_RAM = ORIGIN(RAM) + LENGTH(RAM);\n\n__cs3_heap_end = __top_RAM;\n\n__start_ram = ORIGIN(RAM);\n__end_ram = __top_RAM;\n\nSECTIONS\n{\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.interrupt_vector))\n\n        \/* Makes place for the app header to be filled in by the bootloader\n        checksum program. *\/\n        . = __app_header_offset;\n        QUAD(0); \/* App header: checksum for vector table. *\/\n        QUAD(0);\n        LONG(0); \/* App header: data size *\/\n        QUAD(0); \/* App header: checksum for payload. *\/\n        QUAD(0);\n\n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data)) ;\n        LONG(  SIZEOF(.data));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n\n        *(.after_vectors*)\n\n        *(SORT(.text*))\n        *(.rodata)\n        *(SORT(.rodata.*))\n        . = ALIGN(4);\n\n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        KEEP(*(.fini));\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        \/* End C++ *\/\n\n        __text_section_guard = .;\n        LONG( 0 );\n    } > FLASH\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n    __exidx_start = .;\n\n    .ARM.exidx : ALIGN(4)\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    _etext = .;\n\n\n    \/* MAIN DATA SECTION *\/\n\n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > RAM\n\n    \/* It seems that in order for LPCXpresso to properly flash the data\n    section, an alignment of 256 bytes is necessary. Otherwise the separate\n    flashing of the data section will corrupt the end of the text section. *\/\n    .data : ALIGN(256)\n    {\n        FILL(0xff)\n        _data = .;\n        *(vtable)\n        __impure_data_start = .;\n        *(.data.impure_data)\n        __impure_data_end = .;\n        *(.data*)\n\n        \/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n        . = ALIGN (4);\n\n        _edata = .;\n    } > RAM AT>FLASH\n\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n    } > RAM\n\n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > RAM\n\n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(__cs3_heap_start = .);\n    \/* This pointer will be written to the SP register at reset. *\/\n    PROVIDE(__stack = __top_RAM);\n\n    __impure_data_size = (__impure_data_end - __impure_data_start);\n}\n","old_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(reset_handler)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc)\n\n\/* include device specific memory map *\/\nINCLUDE memory_map.ld\n\n__top_RAM = ORIGIN(RAM) + LENGTH(RAM);\n\n__cs3_heap_end = __top_RAM;\n\n__start_ram = ORIGIN(RAM);\n__end_ram = __top_RAM;\n\nSECTIONS\n{\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.interrupt_vector))\n\n        \/* Makes place for the app header to be filled in by the bootloader\n        checksum program. *\/\n        . = __app_header_offset;\n        QUAD(0); \/* App header: checksum for vector table. *\/\n        QUAD(0);\n        LONG(0); \/* App header: data size *\/\n        QUAD(0); \/* App header: checksum for payload. *\/\n        QUAD(0);\n\n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data)) ;\n        LONG(  SIZEOF(.data));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n\n        *(.after_vectors*)\n\n        *(SORT(.text*))\n        *(.rodata)\n        *(SORT(.rodata.*))\n        . = ALIGN(4);\n\n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        KEEP(*(.fini));\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        \/* End C++ *\/\n\n        __text_section_guard = .;\n        LONG( 0 );\n    } > FLASH\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n    __exidx_start = .;\n\n    .ARM.exidx : ALIGN(4)\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    _etext = .;\n\n\n    \/* MAIN DATA SECTION *\/\n\n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > RAM\n\n    \/* It seems that in order for LPCXpresso to properly flash the data\n    section, an alignment of 256 bytes is necessary. Otherwise the separate\n    flashing of the data section will corrupt the end of the text section. *\/\n    .data : ALIGN(256)\n    {\n        FILL(0xff)\n        _data = .;\n        *(vtable)\n        __impure_data_start = .;\n        *(.data.impure_data)\n        __impure_data_end = .;\n        *(.data*)\n\n        \/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n        . = ALIGN (4);\n\n        _edata = .;\n    } > RAM AT>FLASH\n\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n    } > RAM\n\n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > RAM\n\n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(__cs3_heap_start = .);\n    \/* This pointer will be written to the SP register at reset. *\/\n    PROVIDE(__stack = __top_RAM);\n\n    PROVIDE(__impure_data_size = __impure_data_end - __impure_data_start);\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"ccdcc1119efd8df7560768173749d1937dba309d","subject":"add newlib building support.","message":"add newlib building support.\n\ngit-svn-id: 839522a79b1d56a78fa446d2fd3a0c499f8e535e@1114 bbd45198-f89e-11dd-88c7-29a3b14d5316\n","repos":"wolfgangz2013\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,weety\/rt-thread,yongli3\/rt-thread,nongxiaoming\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,gbcwbz\/rt-thread,RT-Thread\/rt-thread,yongli3\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,AubrCool\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,igou\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,armink\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,yongli3\/rt-thread,hezlog\/rt-thread,igou\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,AubrCool\/rt-thread,yongli3\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,yongli3\/rt-thread,zhaojuntao\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,zhaojuntao\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,yongli3\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,weety\/rt-thread,wolfgangz2013\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,igou\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,zhaojuntao\/rt-thread","old_file":"bsp\/dev3210\/dev3210_ram.lds","new_file":"bsp\/dev3210\/dev3210_ram.lds","new_contents":"\/*\n * File      : jz47xx_ram.lds\n * This file is part of RT-Thread RTOS\n * COPYRIGHT (C) 2010, RT-Thread Development Team\n *\n * The license and distribution terms for this file may be\n * found in the file LICENSE in this distribution or at\n * http:\/\/www.rt-thread.org\/license\/LICENSE\n *\n * Change Logs:\n * Date           Author       Notes\n * 2010-05-17     swkyer       first version\n * 2010-09-04     bernard      move the beginning entry to 0x80200000\n *\/\n\nOUTPUT_ARCH(mips)\nGROUP(-lgcc -lc)\n\nENTRY(_start)\nSECTIONS\n{\n    . = 0x80200000 ;\n\n    .start :\n    {\n        *(.start);\n    }\n\n    . = ALIGN(4);\n    .text : \n    {\n         *(.text)\n         *(.text.*)\n         *(.rodata)\n         *(.rodata.*)\n         *(.rodata1)\n         *(.rodata1.*)\n         \n         \/* section information for finsh shell *\/\n         . = ALIGN(4);\n         __fsymtab_start = .;\n         KEEP(*(FSymTab))\n         __fsymtab_end = .;\n         . = ALIGN(4);\n         __vsymtab_start = .;\n         KEEP(*(VSymTab))\n         __vsymtab_end = .;\n         . = ALIGN(4);\n    }\n\n    . = ALIGN(4);\n    .data : \n    {\n         *(.data)\n         *(.data.*)\n        \n         *(.data1)\n         *(.data1.*)\n         \n         . = ALIGN(8);\n         _gp = ABSOLUTE(.);     \/* Base of small data *\/\n         \n         *(.sdata)\n         *(.sdata.*)\n    }\n\n    .sbss : \n    {\n        __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.dynsbss)\n        *(.scommon)\n    }\n\n    .bss :\n    {\n        *(.bss)\n        *(.bss.*)\n        *(.dynbss)\n        *(COMMON)\n        __bss_end = .;\n    }\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * File      : jz47xx_ram.lds\n * This file is part of RT-Thread RTOS\n * COPYRIGHT (C) 2010, RT-Thread Development Team\n *\n * The license and distribution terms for this file may be\n * found in the file LICENSE in this distribution or at\n * http:\/\/www.rt-thread.org\/license\/LICENSE\n *\n * Change Logs:\n * Date           Author       Notes\n * 2010-05-17     swkyer       first version\n * 2010-09-04     bernard      move the beginning entry to 0x80200000\n *\/\n\nOUTPUT_FORMAT(\"elf32-tradlittlemips\", \"elf32-tradlittlemips\", \"elf32-tradlittlemips\")\nOUTPUT_ARCH(mips)\n\nENTRY(_start)\nSECTIONS\n{\n    . = 0x80200000 ;\n\n    .start :\n    {\n        *(.start);\n    }\n\n    . = ALIGN(4);\n    .text : \n    {\n         *(.text)\n         *(.text.*)\n         *(.rodata)\n         *(.rodata.*)\n         *(.rodata1)\n         *(.rodata1.*)\n         \n         \/* section information for finsh shell *\/\n         . = ALIGN(4);\n         __fsymtab_start = .;\n         KEEP(*(FSymTab))\n         __fsymtab_end = .;\n         . = ALIGN(4);\n         __vsymtab_start = .;\n         KEEP(*(VSymTab))\n         __vsymtab_end = .;\n         . = ALIGN(4);\n    }\n\n    . = ALIGN(4);\n    .data : \n    {\n         *(.data)\n         *(.data.*)\n        \n         *(.data1)\n         *(.data1.*)\n         \n         . = ALIGN(8);\n         _gp = ABSOLUTE(.);     \/* Base of small data *\/\n         \n         *(.sdata)\n         *(.sdata.*)\n    }\n\n    .sbss : \n    {\n        __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.dynsbss)\n        *(.scommon)\n    }\n\n    .bss :\n    {\n        *(.bss)\n        *(.bss.*)\n        *(.dynbss)\n        *(COMMON)\n        __bss_end = .;\n    }\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2c7ec3957d9ce47ae4f6536f38184b0e813c0b70","subject":"Correct linker script for ARM7_AT91SAM7X256_Eclipse demo.","message":"Correct linker script for ARM7_AT91SAM7X256_Eclipse demo.\n","repos":"FreeRTOS\/FreeRTOS-Kernel,FreeRTOS\/FreeRTOS-Kernel","old_file":"Demo\/ARM7_AT91SAM7X256_Eclipse\/RTOSDemo\/atmel-rom.ld","new_file":"Demo\/ARM7_AT91SAM7X256_Eclipse\/RTOSDemo\/atmel-rom.ld","new_contents":"MEMORY \r\n{\r\n\tflash\t: ORIGIN = 0x00100000, LENGTH = 256K\r\n\tram\t\t: ORIGIN = 0x00200000, LENGTH = 64K\r\n}\r\n\r\n__stack_end__ = 0x00200000 + 64K - 4;\r\n\r\nSECTIONS \r\n{\r\n\t. = 0;\r\n\tstartup : { *(.startup)} >flash\r\n\r\n\tprog : \r\n\t{\r\n\t\t*(.text)\r\n\t\t*(.rodata)\r\n\t\t*(.rodata*)\r\n\t\t*(.glue_7)\r\n\t\t*(.glue_7t)\r\n\t} >flash\r\n\r\n\t__end_of_text__ = .;\r\n\t__data_beg_src__ = __end_of_text__;\r\n\r\n\t.data : \r\n\t{\r\n\t\t__data_beg__ = .;\t\t\r\n\t\t*(.data)\r\n\t\t__data_end__ = .;\r\n\t} >ram AT>flash\r\n\r\n\t.bss : \r\n\t{\r\n\t\t__bss_beg__ = .;\r\n\t\t*(.bss)\r\n\t} >ram\r\n\r\n\t. = ALIGN(4);\r\n\t.eh_frame :\r\n\t{\r\n\t\t KEEP (*(.eh_frame))\r\n\t} > ram\r\n\t\r\n\t\/* Align here to ensure that the .bss section occupies space up to\r\n\t_end.  Align after .bss to ensure correct alignment even if the\r\n\t.bss section disappears because there are no input sections.  *\/\r\n\t. = ALIGN(32 \/ 8);\r\n}\r\n\t. = ALIGN(32 \/ 8);\r\n\t_end = .;\r\n\t_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r\n\tPROVIDE (end = .);\r\n\r\n\r\n","old_contents":"MEMORY \r\n{\r\n\tflash\t: ORIGIN = 0x00100000, LENGTH = 256K\r\n\tram\t\t: ORIGIN = 0x00200000, LENGTH = 64K\r\n}\r\n\r\n__stack_end__ = 0x00200000 + 64K - 4;\r\n\r\nSECTIONS \r\n{\r\n\t. = 0;\r\n\tstartup : { *(.startup)} >flash\r\n\r\n\tprog : \r\n\t{\r\n\t\t*(.text)\r\n\t\t*(.rodata)\r\n\t\t*(.rodata*)\r\n\t\t*(.glue_7)\r\n\t\t*(.glue_7t)\r\n\t} >flash\r\n\r\n\t__end_of_text__ = .;\r\n\r\n\t.data : \r\n\t{\r\n\t\t__data_beg__ = .;\r\n\t\t__data_beg_src__ = __end_of_text__;\r\n\t\t*(.data)\r\n\t\t__data_end__ = .;\r\n\t} >ram AT>flash\r\n\r\n\t.bss : \r\n\t{\r\n\t\t__bss_beg__ = .;\r\n\t\t*(.bss)\r\n\t} >ram\r\n\r\n\t. = ALIGN(4);\r\n\t.eh_frame :\r\n\t{\r\n\t\t KEEP (*(.eh_frame))\r\n\t} > ram\r\n\t\r\n\t\/* Align here to ensure that the .bss section occupies space up to\r\n\t_end.  Align after .bss to ensure correct alignment even if the\r\n\t.bss section disappears because there are no input sections.  *\/\r\n\t. = ALIGN(32 \/ 8);\r\n}\r\n\t. = ALIGN(32 \/ 8);\r\n\t_end = .;\r\n\t_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;\r\n\tPROVIDE (end = .);\r\n\r\n\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ba8d9c283a170e8e49b152d49e4ecc646cbddcd9","subject":"fix(linker): The linker wasn't producing .rodata section so we added it at the end of .text section !","message":"fix(linker): The linker wasn't producing .rodata section so we added it at the end of .text section !\n","repos":"Rarioty\/FlowS","old_file":"src\/link.ld","new_file":"src\/link.ld","new_contents":"ENTRY(_start)                   \/* the name of the entry label *\/\n\nSECTIONS {\n    . = 0x00100000;             \/* the code should be loaded at 1MB *\/\n\n    .text ALIGN (0x1000) :      \/* align at 4 KB *\/\n    {\n        *(.multiboot)\n        *(.text)                \/* all text sections from all files *\/\n        *(.rodata)              \/* all read-only data sections from all files *\/\n    }\n\n    .data ALIGN (0x1000) :      \/* align at 4 KB *\/\n    {\n        *(.data)                \/* all data sections from all files *\/\n    }\n\n    .bss ALIGN (0x1000) :       \/* align at 4 KB *\/\n    {\n        *(COMMON)               \/* all COMMON sections from all files *\/\n        *(.bss)                 \/* all bss sections from all files *\/\n    }\n}\n","old_contents":"ENTRY(_start)                   \/* the name of the entry label *\/\n\nSECTIONS {\n    . = 0x00100000;             \/* the code should be loaded at 1MB *\/\n\n    .text ALIGN (0x1000) :      \/* align at 4 KB *\/\n    {\n        *(.text)                \/* all text sections from all files *\/\n    }\n\n    .rodata ALIGN (0x1000) :    \/* align at 4 KB *\/\n    {\n        *(.rodata*)             \/* all read-only data sections from all files *\/\n    }\n\n    .data ALIGN (0x1000) :      \/* align at 4 KB *\/\n    {\n        *(.data)                \/* all data sections from all files *\/\n    }\n\n    .bss ALIGN (0x1000) :       \/* align at 4 KB *\/\n    {\n        *(COMMON)               \/* all COMMON sections from all files *\/\n        *(.bss)                 \/* all bss sections from all files *\/\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"03f71d7c33eeba3722fe2321905874ee3a2c6286","subject":"add section for ARM","message":"add section for ARM\n","repos":"xboot\/xboot,xboot\/xboot","old_file":"src\/arch\/arm32\/mach-realview\/xboot.ld","new_file":"src\/arch\/arm32\/mach-realview\/xboot.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(_start)\r\n\r\n\r\nSTACK_FIQ_SIZE \t= 0x10000;\t\/* 64KB *\/\r\nSTACK_IRQ_SIZE \t= 0x10000;\t\/* 64KB *\/\r\nSTACK_ABT_SIZE \t= 0x10000;\t\/* 64KB *\/\r\nSTACK_UND_SIZE \t= 0x10000;\t\/* 64KB *\/\r\nSTACK_SRV_SIZE \t= 0x100000;\t\/* 1 MB *\/\r\n\r\n\r\nMEMORY\r\n{\r\n\trom (rx)\t: org = 0x70000000, len = 0x04000000\t\/* 64 MB *\/\r\n\tram (rwx)\t: org = 0x74000000, len = 0x0c000000\t\/* 192 MB *\/\r\n}\r\n\r\nSECTIONS\r\n{   \r\n\t.text :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_start = .);\r\n\t\t.obj\/arch\/arm32\/mach-realview\/start.o (.text)\r\n\t\t*(.text)\r\n\t\t*(.text.*)\r\n\t\t*(.init.text)\r\n    \t*(.exit.text)\r\n\r\n    \t. = ALIGN(8);\r\n    \tPROVIDE (__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE (__ksymtab_end = .);\r\n\r\n    \t. = ALIGN(8);\t\r\n\t\tPROVIDE (__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_0s.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_1s.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_2s.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_3s.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_4s.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_5s.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_6s.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_7s.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_8s.text))\r\n\t\tPROVIDE (__initcall_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_8s.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7s.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6s.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5s.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4s.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3s.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2s.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1s.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0s.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE (__exitcall_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE (__romdisk_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\t*(.rodata);\r\n\t\t*(.rodata.*);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\t*(.glue_7);\r\n\t\t*(.glue_7t);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_end = .);\r\n\t} > rom\r\n\r\n\t.data_shadow ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__data_shadow_start = .);\r\n\t\tPROVIDE (__data_shadow_end = (. + SIZEOF (.data)) );\r\n\t} > rom\r\n\r\n\t.data : AT ( ADDR (.data_shadow) )\r\n\t{\r\n\t\tPROVIDE (__data_start = .);\t\r\n\t\t*(.data)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE (__data_end = .);\t\t\r\n\t} > ram\r\n\r\n\t.ARM.exidx :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__exidx_start = .);\r\n\t\t*(.ARM.exidx*)\r\n\t\tPROVIDE (__exidx_end = .);\r\n\t} > ram\r\n\r\n\t.ARM.extab :\r\n\t{\r\n\t\tPROVIDE (__extab_start = .);\r\n\t\t*(.ARM.extab*)\r\n\t\tPROVIDE (__extab_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE (__bss_start = .);\r\n\t\t*(.bss)\r\n\t\t*(.bss.*)\r\n\t\t*(.sbss)\r\n\t\t*(COMMON)\r\n\t\tPROVIDE (__bss_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_start = .);\r\n\t\t*(.heap)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_start = .);\r\n\t\tPROVIDE (__stack_fiq_start = .);\r\n\t\t. += STACK_FIQ_SIZE;\r\n\t\tPROVIDE (__stack_fiq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_irq_start = .);\r\n\t\t. += STACK_IRQ_SIZE;\r\n\t\tPROVIDE (__stack_irq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_abt_start = .);\r\n\t\t. += STACK_ABT_SIZE;\r\n\t\tPROVIDE (__stack_abt_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_und_start = .);\r\n\t\t. += STACK_UND_SIZE;\r\n\t\tPROVIDE (__stack_und_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_srv_start = .);\r\n\t\t. += STACK_SRV_SIZE;\r\n\t\tPROVIDE (__stack_srv_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_end = .);\r\n\t} > ram\r\n\r\n\t\/*\r\n\t * Stabs debugging sections.\r\n\t *\/\r\n\t.stab 0 : { *(.stab) }\r\n\t.stabstr 0 : { *(.stabstr) }\r\n\t.stab.excl 0 : { *(.stab.excl) }\r\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\r\n\t.stab.index 0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment 0 : { *(.comment) }\r\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\r\n\t.debug_info 0 : { *(.debug_info) }\r\n\t.debug_line 0 : { *(.debug_line) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t.debug_aranges 0 : { *(.debug_aranges) }\r\n}\r\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nENTRY(_start)\r\n\r\n\r\nSTACK_FIQ_SIZE \t= 0x10000;\t\/* 64KB *\/\r\nSTACK_IRQ_SIZE \t= 0x10000;\t\/* 64KB *\/\r\nSTACK_ABT_SIZE \t= 0x10000;\t\/* 64KB *\/\r\nSTACK_UND_SIZE \t= 0x10000;\t\/* 64KB *\/\r\nSTACK_SRV_SIZE \t= 0x100000;\t\/* 1 MB *\/\r\n\r\n\r\nMEMORY\r\n{\r\n\trom (rx)\t: org = 0x70000000, len = 0x04000000\t\/* 64 MB *\/\r\n\tram (rwx)\t: org = 0x74000000, len = 0x0c000000\t\/* 192 MB *\/\r\n}\r\n\r\nSECTIONS\r\n{   \r\n\t.text :\r\n\t{\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_start = .);\r\n\t\t.obj\/arch\/arm32\/mach-realview\/start.o (.text)\r\n\t\t*(.text)\r\n\t\t*(.text.*)\r\n\t\t*(.init.text)\r\n    \t*(.exit.text)\r\n\r\n    \t. = ALIGN(8);\r\n    \tPROVIDE (__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE (__ksymtab_end = .);\r\n\r\n    \t. = ALIGN(8);\t\r\n\t\tPROVIDE (__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_0s.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_1s.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_2s.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_3s.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_4s.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_5s.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_6s.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_7s.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_8s.text))\r\n\t\tPROVIDE (__initcall_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_8s.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7s.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6s.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5s.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4s.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3s.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2s.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1s.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0s.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE (__exitcall_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE (__romdisk_end = .);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\t*(.rodata);\r\n\t\t*(.rodata.*);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\t*(.glue_7);\r\n\t\t*(.glue_7t);\r\n\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__text_end = .);\r\n\t} > rom\r\n\r\n\t.data_shadow ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE (__data_shadow_start = .);\r\n\t\tPROVIDE (__data_shadow_end = (. + SIZEOF (.data)) );\r\n\t} > rom\r\n\r\n\t.data : AT ( ADDR (.data_shadow) )\r\n\t{\r\n\t\tPROVIDE (__data_start = .);\t\r\n\t\t*(.data)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE (__data_end = .);\t\t\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE (__bss_start = .);\r\n\t\t*(.bss)\r\n\t\t*(.bss.*)\r\n\t\t*(.sbss)\r\n\t\t*(COMMON)\r\n\t\tPROVIDE (__bss_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_start = .);\r\n\t\t*(.heap)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__heap_end = .);\r\n\t\t\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_start = .);\r\n\t\tPROVIDE (__stack_fiq_start = .);\r\n\t\t. += STACK_FIQ_SIZE;\r\n\t\tPROVIDE (__stack_fiq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_irq_start = .);\r\n\t\t. += STACK_IRQ_SIZE;\r\n\t\tPROVIDE (__stack_irq_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_abt_start = .);\r\n\t\t. += STACK_ABT_SIZE;\r\n\t\tPROVIDE (__stack_abt_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_und_start = .);\r\n\t\t. += STACK_UND_SIZE;\r\n\t\tPROVIDE (__stack_und_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_srv_start = .);\r\n\t\t. += STACK_SRV_SIZE;\r\n\t\tPROVIDE (__stack_srv_end = .);\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE (__stack_end = .);\r\n\t} > ram\r\n\r\n\t\/*\r\n\t * Stabs debugging sections.\r\n\t *\/\r\n\t.stab 0 : { *(.stab) }\r\n\t.stabstr 0 : { *(.stabstr) }\r\n\t.stab.excl 0 : { *(.stab.excl) }\r\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\r\n\t.stab.index 0 : { *(.stab.index) }\r\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\r\n\t.comment 0 : { *(.comment) }\r\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\r\n\t.debug_info 0 : { *(.debug_info) }\r\n\t.debug_line 0 : { *(.debug_line) }\r\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\r\n\t.debug_aranges 0 : { *(.debug_aranges) }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ff81f1460558e22afb7d8e90c050f28bd7544cef","subject":"LPC2368 [GCC_ARM]: Fixed: Compilation and link errors in case  \"SD\" example.","message":"LPC2368 [GCC_ARM]: Fixed: Compilation and link errors in case  \"SD\" example.\n","repos":"Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS","old_file":"TARGET_NXP\/TARGET_LPC23XX\/TOOLCHAIN_GCC_ARM\/LPC2368.ld","new_file":"TARGET_NXP\/TARGET_LPC23XX\/TOOLCHAIN_GCC_ARM\/LPC2368.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(vectors)\n\n\/* Memory Definitions: *\/\nMEMORY\n{\n    Flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 512k\n    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 32k\n    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 8k\n    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k\n    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k\n    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k\n}\n\n\/* Stack sizes: *\/\nUND_Stack_Size = 16;\nSVC_Stack_Size = 512;\nABT_Stack_Size = 16;\nFIQ_Stack_Size = 16;\nIRQ_Stack_Size = 256;\nStack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;\n\n\/* Stack tops for each mode: *\/\n__und_stack_top__ = __stacks_top__;\n__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;\n__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;\n__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;\n__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;\n\n\/* C-accessible symbols for memory address ranges: *\/\n__FLASH_segment_start__ = ORIGIN( Flash );\n__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );\n__SRAM_segment_start__  = ORIGIN( Ram );\n__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );\n\n\/* Stacks (full descending) at top of RAM, grows downward:\n *\n * __stack_min__ is used by the malloc implementation to ensure heap never collides\n * with stack (assuming stack never grows beyond Stack_Size_Total in length) *\/\n__stacks_top__ = __SRAM_segment_end__;\n__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;\n\nSECTIONS\n{\n    \/* first section is .text which is used for code *\/\n    __text_start__ = . ;\n    .text : {\n        __privileged_code_start__ = . ;\n        KEEP( *( .vectors ) )\n        *( .privileged_code )\n    \n        __privileged_code_end__ = .;\n\n        *( .text .text.* .gnu.linkonce.t.* )\n        *( .plt )\n        *( .gnu.warning )\n        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )\n        \n        *( .rodata .rodata.* .gnu.linkonce.r.* )\n        \n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *( .init ) )\n        . = ALIGN( 4 ) ;\n        __preinit_array_start = . ;\n        KEEP( *( .preinit_array ) )\n        __preinit_array_end = . ;\n        . = ALIGN( 4 ) ;\n        __init_array_start = . ;\n        KEEP( *( SORT( .init_array.* ) ) )\n        KEEP( *( .init_array ) )\n        __init_array_end = . ;\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *crtbegin.o( .ctors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )\n        KEEP( *( SORT( .ctors.* ) ) )\n        KEEP( *crtend.o( .ctors ) )\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *( .fini ) )\n        . = ALIGN( 4 ) ;\n        __fini_array_start = . ;\n        KEEP( *( .fini_array ) )\n        KEEP( *( SORT( .fini_array.* ) ) )\n        __fini_array_end = . ;\n        \n        KEEP( *crtbegin.o( .dtors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )\n        KEEP( *( SORT( .dtors.* ) ) )\n        KEEP( *crtend.o( .dtors ) )\n    \n    } >Flash\n    \n    __exidx_start = . ;\n    .ARM.exidx : {\n        *( .ARM.exidx* .gnu.linkonce.armexidx.* )\n    } >Flash\n    __exidx_end = . ;\n    \n    .text.align : { . = ALIGN( 8 ) ; } >Flash \/* Alignment schenanigans *\/\n    __text_end__ = . ;\n    \n    \/* .bss section -- used for uninitialized data *\/\n    \/* Located at the start of RAM *\/\n    .bss (NOLOAD) : {\n        __bss_start__ = . ;\n        *crt0.o( .ram_vectors )\n        \n        __user_bss_start__ = . ;\n        *( .user_bss )\n        __user_bss_end__ = . ;\n        \n        *( .shbss )\n        *( .bss .bss.* .gnu.linkonce.b.* )\n        *( COMMON )\n        *( .ram.b )\n        . = ALIGN( 8 ) ;\n        \n        __bss_end__ = . ;\n    } >Ram AT>Flash\n\n    \/* .data section -- used for initialized data *\/\n    .data : {\n        __data_start__ = . ;\n        KEEP( *( .jcr ) )\n        *( .got.plt ) *( .got )\n        *( .shdata )\n        *( .data .data.* .gnu.linkonce.d.* )\n        *( .ram )\n        . = ALIGN( 8 ) ;\n        __data_end__ = . ;\n    } >Ram AT>Flash\n\n    __data_init_start__ = LOADADDR( .data ) ;\n\n    \/* Heap starts here and grows up in memory *\/\n    . = ALIGN( 8 ) ;\n    __heap_start__ = . ;\n    end = . ;\n    __end__ = . ;\n\n    .stab    0 (NOLOAD) : { *(.stab) }\n    .stabstr 0 (NOLOAD) : { *(.stabstr) }\n    \/* DWARF debug sections. *\/\n    \/* Symbols in the DWARF debugging sections are relative to the  *\/\n    \/* beginning of the section so we begin them at 0.              *\/\n    \/* DWARF 1 *\/\n    .debug           0 : { *(.debug) }\n    .line            0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo   0 : { *(.debug_srcinfo) }\n    .debug_sfnames   0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges   0 : { *(.debug_aranges) }\n    .debug_pubnames  0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev    0 : { *(.debug_abbrev) }\n    .debug_line      0 : { *(.debug_line) }\n    .debug_frame     0 : { *(.debug_frame) }\n    .debug_str       0 : { *(.debug_str) }\n    .debug_loc       0 : { *(.debug_loc) }\n    .debug_macinfo   0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n    \/* DWARF 3 *\/\n    .debug_pubtypes  0 : { *(.debug_pubtypes) }\n    .debug_ranges    0 : { *(.debug_ranges) }\n    \n    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }\n    .ARM.attributes     0 : {\n        KEEP( *( .ARM.attributes ) )\n        KEEP( *( .gnu.attributes ) )\n    }\n    \/DISCARD\/             : { *( .note.GNU-stack ) }\n    \n    \/* C data can be defined as being in special purpose RAMs using\n     * __attribute__ ((section (\"ethram\"))) for example. *\/\n    .usbram (NOLOAD):\n    {\n        *( .usbram )\n        *( .usbram.* )\n    } > UsbRam\n    .ethram (NOLOAD):\n    {\n        *( .ethram )\n        *( .ethram.* )\n    } > EthRam\n    .canram (NOLOAD):\n    {\n        *( .canram )\n        *( .canram.* )\n    } > CanRam\n    .batram (NOLOAD):\n    {\n        *( .batram )\n        *( .batram.* )\n    } > BatRam\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(vectors)\n\n\/* Memory Definitions: *\/\nMEMORY\n{\n    Flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 512k\n    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 32k\n    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 8k\n    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k\n    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k\n    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k\n}\n\n\/* Stack sizes: *\/\nUND_Stack_Size = 16;\nSVC_Stack_Size = 512;\nABT_Stack_Size = 16;\nFIQ_Stack_Size = 16;\nIRQ_Stack_Size = 256;\nStack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;\n\n\/* Stack tops for each mode: *\/\n__und_stack_top__ = __stacks_top__;\n__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;\n__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;\n__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;\n__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;\n\n\/* C-accessible symbols for memory address ranges: *\/\n__FLASH_segment_start__ = ORIGIN( Flash );\n__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );\n__SRAM_segment_start__  = ORIGIN( Ram );\n__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );\n\n\/* Stacks (full descending) at top of RAM, grows downward:\n *\n * __stack_min__ is used by the malloc implementation to ensure heap never collides\n * with stack (assuming stack never grows beyond Stack_Size_Total in length) *\/\n__stacks_top__ = __SRAM_segment_end__;\n__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;\n\nSECTIONS\n{\n    \/* first section is .text which is used for code *\/\n    __text_start__ = . ;\n    .text : {\n        __privileged_code_start__ = . ;\n        KEEP( *( .vectors ) )\n        *( .privileged_code )\n    \n        __privileged_code_end__ = .;\n\n        *( .text .text.* .gnu.linkonce.t.* )\n        *( .plt )\n        *( .gnu.warning )\n        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )\n        \n        *( .rodata .rodata.* .gnu.linkonce.r.* )\n        \n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *( .init ) )\n        . = ALIGN( 4 ) ;\n        __preinit_array_start = . ;\n        KEEP( *( .preinit_array ) )\n        __preinit_array_end = . ;\n        . = ALIGN( 4 ) ;\n        __init_array_start = . ;\n        KEEP( *( SORT( .init_array.* ) ) )\n        KEEP( *( .init_array ) )\n        __init_array_end = . ;\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *crtbegin.o( .ctors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )\n        KEEP( *( SORT( .ctors.* ) ) )\n        KEEP( *crtend.o( .ctors ) )\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *( .fini ) )\n        . = ALIGN( 4 ) ;\n        __fini_array_start = . ;\n        KEEP( *( .fini_array ) )\n        KEEP( *( SORT( .fini_array.* ) ) )\n        __fini_array_end = . ;\n        \n        KEEP( *crtbegin.o( .dtors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )\n        KEEP( *( SORT( .dtors.* ) ) )\n        KEEP( *crtend.o( .dtors ) )\n    \n    } >Flash\n    \n    __exidx_start = . ;\n    .ARM.exidx : {\n        *( .ARM.exidx* .gnu.linkonce.armexidx.* )\n    } >Flash\n    __exidx_end = . ;\n    \n    .text.align : { . = ALIGN( 8 ) ; } >Flash \/* Alignment schenanigans *\/\n    __text_end__ = . ;\n    \n    \/* .bss section -- used for uninitialized data *\/\n    \/* Located at the start of RAM *\/\n    .bss (NOLOAD) : {\n        __bss_start__ = . ;\n        *crt0.o( .ram_vectors )\n        \n        __user_bss_start__ = . ;\n        *( .user_bss )\n        __user_bss_end__ = . ;\n        \n        *( .shbss )\n        *( .bss .bss.* .gnu.linkonce.b.* )\n        *( COMMON )\n        *( .ram.b )\n        . = ALIGN( 8 ) ;\n        \n        __bss_end__ = . ;\n    } >Ram AT>Flash\n\n    \/* .data section -- used for initialized data *\/\n    .data : {\n        __data_start__ = . ;\n        KEEP( *( .jcr ) )\n        *( .got.plt ) *( .got )\n        *( .shdata )\n        *( .data .data.* .gnu.linkonce.d.* )\n        *( .ram )\n        . = ALIGN( 8 ) ;\n        __data_end__ = . ;\n    } >Ram AT>Flash\n\n    __data_init_start__ = LOADADDR( .data ) ;\n\n    \/* Heap starts here and grows up in memory *\/\n    . = ALIGN( 8 ) ;\n    __heap_start__ = . ;\n    end = . ;\n\n    .stab    0 (NOLOAD) : { *(.stab) }\n    .stabstr 0 (NOLOAD) : { *(.stabstr) }\n    \/* DWARF debug sections. *\/\n    \/* Symbols in the DWARF debugging sections are relative to the  *\/\n    \/* beginning of the section so we begin them at 0.              *\/\n    \/* DWARF 1 *\/\n    .debug           0 : { *(.debug) }\n    .line            0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo   0 : { *(.debug_srcinfo) }\n    .debug_sfnames   0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges   0 : { *(.debug_aranges) }\n    .debug_pubnames  0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev    0 : { *(.debug_abbrev) }\n    .debug_line      0 : { *(.debug_line) }\n    .debug_frame     0 : { *(.debug_frame) }\n    .debug_str       0 : { *(.debug_str) }\n    .debug_loc       0 : { *(.debug_loc) }\n    .debug_macinfo   0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n    \/* DWARF 3 *\/\n    .debug_pubtypes  0 : { *(.debug_pubtypes) }\n    .debug_ranges    0 : { *(.debug_ranges) }\n    \n    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }\n    .ARM.attributes     0 : {\n        KEEP( *( .ARM.attributes ) )\n        KEEP( *( .gnu.attributes ) )\n    }\n    \/DISCARD\/             : { *( .note.GNU-stack ) }\n    \n    \/* C data can be defined as being in special purpose RAMs using\n     * __attribute__ ((section (\"ethram\"))) for example. *\/\n    .usbram (NOLOAD):\n    {\n        *( .usbram )\n        *( .usbram.* )\n    } > UsbRam\n    .ethram (NOLOAD):\n    {\n        *( .ethram )\n        *( .ethram.* )\n    } > EthRam\n    .canram (NOLOAD):\n    {\n        *( .canram )\n        *( .canram.* )\n    } > CanRam\n    .batram (NOLOAD):\n    {\n        *( .batram )\n        *( .batram.* )\n    } > BatRam\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9ae85d4a59ee15795bfc34817fe15eb11ded9b36","subject":"Fix comment in linker script","message":"Fix comment in linker script\n","repos":"drpjk\/Arduino,sanyaade-iot\/Arduino-1,weera00\/Arduino,myrtleTree33\/Arduino,spapadim\/Arduino,smily77\/Arduino,sanyaade-iot\/Arduino-1,eeijcea\/Arduino-1,mangelajo\/Arduino,paulmand3l\/Arduino,spapadim\/Arduino,weera00\/Arduino,ssvs111\/Arduino,gonium\/Arduino,drpjk\/Arduino,ogahara\/Arduino,zenmanenergy\/Arduino,gonium\/Arduino,ssvs111\/Arduino,myrtleTree33\/Arduino,mangelajo\/Arduino,paulmand3l\/Arduino,EmuxEvans\/Arduino,mangelajo\/Arduino,ssvs111\/Arduino,ogahara\/Arduino,ssvs111\/Arduino,ogahara\/Arduino,mateuszdw\/Arduino,zenmanenergy\/Arduino,smily77\/Arduino,ogahara\/Arduino,eeijcea\/Arduino-1,sanyaade-iot\/Arduino-1,myrtleTree33\/Arduino,paulmand3l\/Arduino,mateuszdw\/Arduino,smily77\/Arduino,sanyaade-iot\/Arduino-1,drpjk\/Arduino,gonium\/Arduino,zenmanenergy\/Arduino,ssvs111\/Arduino,weera00\/Arduino,ogahara\/Arduino,ogahara\/Arduino,gonium\/Arduino,myrtleTree33\/Arduino,EmuxEvans\/Arduino,mangelajo\/Arduino,drpjk\/Arduino,EmuxEvans\/Arduino,spapadim\/Arduino,EmuxEvans\/Arduino,mateuszdw\/Arduino,weera00\/Arduino,mangelajo\/Arduino,paulmand3l\/Arduino,weera00\/Arduino,gonium\/Arduino,mateuszdw\/Arduino,ssvs111\/Arduino,gonium\/Arduino,eeijcea\/Arduino-1,mateuszdw\/Arduino,smily77\/Arduino,zenmanenergy\/Arduino,smily77\/Arduino,smily77\/Arduino,smily77\/Arduino,spapadim\/Arduino,zenmanenergy\/Arduino,EmuxEvans\/Arduino,EmuxEvans\/Arduino,spapadim\/Arduino,ogahara\/Arduino,leftbrainstrain\/Arduino-ESP8266,sanyaade-iot\/Arduino-1,sanyaade-iot\/Arduino-1,leftbrainstrain\/Arduino-ESP8266,mangelajo\/Arduino,drpjk\/Arduino,EmuxEvans\/Arduino,drpjk\/Arduino,gonium\/Arduino,eeijcea\/Arduino-1,myrtleTree33\/Arduino,leftbrainstrain\/Arduino-ESP8266,myrtleTree33\/Arduino,zenmanenergy\/Arduino,paulmand3l\/Arduino,spapadim\/Arduino,ssvs111\/Arduino,eeijcea\/Arduino-1,mateuszdw\/Arduino,drpjk\/Arduino,eeijcea\/Arduino-1,weera00\/Arduino,mateuszdw\/Arduino,myrtleTree33\/Arduino,zenmanenergy\/Arduino,leftbrainstrain\/Arduino-ESP8266,spapadim\/Arduino,leftbrainstrain\/Arduino-ESP8266,sanyaade-iot\/Arduino-1,leftbrainstrain\/Arduino-ESP8266,paulmand3l\/Arduino,leftbrainstrain\/Arduino-ESP8266,weera00\/Arduino,paulmand3l\/Arduino,eeijcea\/Arduino-1,mangelajo\/Arduino","old_file":"hardware\/esp8266com\/esp8266\/tools\/sdk\/ld\/eagle.flash.4m1m.ld","new_file":"hardware\/esp8266com\/esp8266\/tools\/sdk\/ld\/eagle.flash.4m1m.ld","new_contents":"\/* Flash Split for 4M chips *\/\n\/* sketch 1019KB *\/\n\/* empty  2048KB *\/\n\/* spiffs 1004KB *\/\n\/* eeprom 20KB *\/\n\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40201010, len = 0xfeff0\n}\n\nPROVIDE ( _SPIFFS_start = 0x40500000 );\nPROVIDE ( _SPIFFS_end = 0x405FB000 );\nPROVIDE ( _SPIFFS_page = 0x100 );\nPROVIDE ( _SPIFFS_block = 0x2000 );\n\nINCLUDE \"..\/ld\/eagle.app.v6.common.ld\"\n","old_contents":"\/* Flash Split for 4M chips *\/\n\/* sketch 1019KB *\/\n\/* spiffs 3052KB *\/\n\/* eeprom 20KB *\/\n\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40201010, len = 0xfeff0\n}\n\nPROVIDE ( _SPIFFS_start = 0x40500000 );\nPROVIDE ( _SPIFFS_end = 0x405FB000 );\nPROVIDE ( _SPIFFS_page = 0x100 );\nPROVIDE ( _SPIFFS_block = 0x2000 );\n\nINCLUDE \"..\/ld\/eagle.app.v6.common.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"112372d598b228681aa686ee4b13a5cd8eb60b6e","subject":"update rom bootloader addr info","message":"update rom bootloader addr info\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/ld\/esp32h2\/bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/ld\/esp32h2\/bootloader.ld","new_contents":"\/** Simplified memory map for the bootloader.\n *  Make sure the bootloader can load into main memory without overwriting itself.\n *  We put 2nd bootloader in the high address space (before ROM stack\/data\/bss).\n *  See memory usage for ROM bootloader at the end of this file.\n *\/\n\nMEMORY\n{\n  iram_seg (RWX) :                  org = 0x403CE000, len = 0x2000\n  iram_loader_seg (RWX) :           org = 0x403D0000, len = 0x6000\n  dram_seg (RW) :                   org = 0x3FCD6000, len = 0x4000\n}\n\n\/* Default entry point: *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)\n    *libbootloader_support.a:bootloader_efuse_esp32h2.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _dram_start = ABSOLUTE(.);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/* C++ constructor and destructor tables, properly ordered: *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _dram_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/** CPU will try to prefetch up to 16 bytes of\n      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow\n      * safe access to up to 16 bytes after the last real instruction, add\n      * dummy bytes to ensure this\n      *\/\n    . += 16;\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n\n\/* ESP32H2-TODO: IDF-3466 *\/\n\/**\n *  Appendix: Memory Usage of ROM bootloader\n *\n *  +--------+--------------+------+ 0x3FCC_B900\n *  |        ^              |\n *  |        |              |\n *  |        | data\/bss     |\n *  |        |              |\n *  |        v              |\n *  +------------------------------+ 0x3FCD_D210\n *  |        ^              |\n *  |        |              |\n *  |        | stack        |\n *  |        |              |\n *  |        v              |\n *  +------------------------------+ 0x3FCD_F210\n *\/\n","old_contents":"\/** Simplified memory map for the bootloader.\n *  Make sure the bootloader can load into main memory without overwriting itself.\n *  We put 2nd bootloader in the high address space (before ROM stack\/data\/bss).\n *  See memory usage for ROM bootloader at the end of this file.\n *\/\n\nMEMORY\n{\n  iram_seg (RWX) :                  org = 0x403CE000, len = 0x2000\n  iram_loader_seg (RWX) :           org = 0x403D0000, len = 0x6000\n  dram_seg (RW) :                   org = 0x3FCD6000, len = 0x4000\n}\n\n\/* Default entry point: *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)\n    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)\n    *libbootloader_support.a:bootloader_efuse_esp32h2.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)\n    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _dram_start = ABSOLUTE(.);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/* C++ constructor and destructor tables, properly ordered: *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _dram_end = ABSOLUTE(.);\n  } > dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/** CPU will try to prefetch up to 16 bytes of\n      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow\n      * safe access to up to 16 bytes after the last real instruction, add\n      * dummy bytes to ensure this\n      *\/\n    . += 16;\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n\n\/* ESP32H2-TODO: IDF-3466 *\/\n\/**\n *  Appendix: Memory Usage of ROM bootloader\n *\n *  +--------+--------------+------+ 0x3FCC_B000\n *  |        ^              |\n *  |        |              |\n *  |        | data\/bss     |\n *  |        |              |\n *  |        v              |\n *  +------------------------------+ 0x3FCD_C910\n *  |        ^              |\n *  |        |              |\n *  |        | stack        |\n *  |        |              |\n *  |        v              |\n *  +------------------------------+ 0x3FCD_E910\n *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e170d45dc38b607dd7e6eca4e5554d1078558f99","subject":"Moves the reset_data in ram0.","message":"Moves the reset_data in ram0.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/microchip-pic32mx-generic\/target.ld","new_file":"boards\/microchip-pic32mx-generic\/target.ld","new_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20181017 bracz: Refactor for external included memory map\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\nINCLUDE memory_map.ld\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  \/* tiny part of RAM reserved for startup code *\/\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = ___user_ram_size - 16\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  flash_user (rx) : ORIGIN = 0x9D000000, LENGTH = ___user_flash_size\r\n  \r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  flash_boot (rx) : ORIGIN = 0x9FC00000, LENGTH = ___boot_flash_size - 16\r\n  flash_cfg  (r!x): ORIGIN = 0x9FC00000 + ___boot_flash_size - 16, LENGTH = 16\r\n}\r\n\r\n\/* This include defines region aliases to select whether we are building with bootloader or without. *\/\r\nINCLUDE region.ld\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\n\/* NOT NEEDED -- we have our own entry routine, not using cs3's\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) *\/\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** First thing in  flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n  } >REGION_RESET\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  } >REGION_INT\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text _textoffs :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >REGION_PGM\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >REGION_PGM\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  } >REGION_PGM\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >REGION_PGM\r\n  \r\n  __cs3_region_size_rom = LENGTH(flash_user); \/* just total size of flash *\/\r\n\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>REGION_PGM\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss : ALIGN (8)\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; DRN updated this; seems correct...  bracz: not really. *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","old_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20181017 bracz: Refactor for external included memory map\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\nINCLUDE memory_map.ld\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  \/* tiny part of RAM reserved for startup code *\/\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = ___user_ram_size - 16\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  flash_user (rx) : ORIGIN = 0x9D000000, LENGTH = ___user_flash_size\r\n  \r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  flash_boot (rx) : ORIGIN = 0x9FC00000, LENGTH = ___boot_flash_size - 16\r\n  flash_cfg  (r!x): ORIGIN = 0x9FC00000 + ___boot_flash_size - 16, LENGTH = 16\r\n}\r\n\r\n\/* This include defines region aliases to select whether we are building with bootloader or without. *\/\r\nINCLUDE region.ld\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\n\/* NOT NEEDED -- we have our own entry routine, not using cs3's\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) *\/\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** First thing in  flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n  } >REGION_RESET\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  } >REGION_INT\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  } >REGION_INT\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text _textoffs :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >REGION_PGM\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >REGION_PGM\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  } >REGION_PGM\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >REGION_PGM\r\n  \r\n  __cs3_region_size_rom = LENGTH(flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>REGION_PGM\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss : ALIGN (8)\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; DRN updated this; seems correct...  bracz: not really. *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"dac99329e2280469ce7a505325998ec4df865e30","subject":"added license to sp500 linker script","message":"added license to sp500 linker script\n","repos":"tensorflow\/tensorflow,paolodedios\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_saved_model,annarev\/tensorflow,petewarden\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,karllessard\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_saved_model,annarev\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,petewarden\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow,petewarden\/tensorflow,petewarden\/tensorflow,Intel-tensorflow\/tensorflow,frreiss\/tensorflow-fred,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,annarev\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,sarvex\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-tensorflow\/tensorflow,gautam1858\/tensorflow,sarvex\/tensorflow,frreiss\/tensorflow-fred,petewarden\/tensorflow,karllessard\/tensorflow,Intel-Corporation\/tensorflow,sarvex\/tensorflow,petewarden\/tensorflow,paolodedios\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_saved_model,paolodedios\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-Corporation\/tensorflow,frreiss\/tensorflow-fred,sarvex\/tensorflow,petewarden\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow,karllessard\/tensorflow,karllessard\/tensorflow,annarev\/tensorflow,petewarden\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,yongtang\/tensorflow,karllessard\/tensorflow,frreiss\/tensorflow-fred,yongtang\/tensorflow,karllessard\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,frreiss\/tensorflow-fred,yongtang\/tensorflow,Intel-tensorflow\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,frreiss\/tensorflow-fred,yongtang\/tensorflow,frreiss\/tensorflow-fred,yongtang\/tensorflow,annarev\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-experimental_link_static_libraries_once,paolodedios\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,gautam1858\/tensorflow,annarev\/tensorflow,gautam1858\/tensorflow,karllessard\/tensorflow,Intel-Corporation\/tensorflow,sarvex\/tensorflow,Intel-tensorflow\/tensorflow,gautam1858\/tensorflow,sarvex\/tensorflow,annarev\/tensorflow,frreiss\/tensorflow-fred,karllessard\/tensorflow,annarev\/tensorflow,karllessard\/tensorflow,Intel-Corporation\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,petewarden\/tensorflow,gautam1858\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,frreiss\/tensorflow-fred,annarev\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,yongtang\/tensorflow,Intel-tensorflow\/tensorflow,yongtang\/tensorflow,Intel-Corporation\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow,sarvex\/tensorflow,Intel-tensorflow\/tensorflow,sarvex\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,petewarden\/tensorflow","old_file":"tensorflow\/lite\/micro\/tools\/make\/targets\/ceva\/CEVA_SP500_TFLM.ld","new_file":"tensorflow\/lite\/micro\/tools\/make\/targets\/ceva\/CEVA_SP500_TFLM.ld","new_contents":"\/* Copyright 2019 The TensorFlow Authors. All Rights Reserved.\r\n\r\nLicensed under the Apache License, Version 2.0 (the \"License\");\r\nyou may not use this file except in compliance with the License.\r\nYou may obtain a copy of the License at\r\n\r\n    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\r\n\r\nUnless required by applicable law or agreed to in writing, software\r\ndistributed under the License is distributed on an \"AS IS\" BASIS,\r\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\nSee the License for the specific language governing permissions and\r\nlimitations under the License.\r\n==============================================================================*\/\r\n\r\n\r\nOUTPUT(a.elf)\r\n\r\n\/* By default, program starts from reset address (the default location of the interrupt table) *\/\r\nENTRY(__cxd_inttbl_start)\r\n\r\n\/** Memory configuration parameters.\r\n *  The parameters become application symbols and can be referred from application\r\n *\/\r\n__internal_data_start = DEFINED(__internal_data_start) ? __internal_data_start : 0x00000000;\r\n__internal_data_size  = DEFINED(__internal_data_size ) ? __internal_data_size  : 256k;\r\n__external_start      = DEFINED(__external_start     ) ? __external_start      : 0x20000000;\r\n__external_size       = DEFINED(__external_size      ) ? __external_size       : 0x60000000;\r\n__rom_start           = DEFINED(__rom_start          ) ? __rom_start           : 0xC0000000;\r\n__rom_size            = DEFINED(__rom_size           ) ? __rom_size            : 1024M;\r\n\r\n__malloc_size         = DEFINED(__malloc_size        ) ? __malloc_size         : 16k;\r\n__stack_size          = DEFINED(__stack_size         ) ? __stack_size          : 16k;\r\n__arg_sect_size       = DEFINED(__arg_sect_size      ) ? __arg_sect_size       : 512;\r\n\r\nMEMORY {\r\n    INTERNAL_DATA  (rw) : ORIGIN = __internal_data_start, LENGTH = __internal_data_size\r\n    EXTERNAL      (rwx) : ORIGIN = __external_start     , LENGTH = __external_size\r\n    ROM            (rx) : ORIGIN = __rom_start          , LENGTH = __rom_size\r\n}\r\n\r\nSECTIONS {\r\n    .inttbl : ALIGN(0x20) {\r\n        \/** The interrupt vector table. Contains the NMI\r\n         *  and maskable interrupt handlers\r\n         *\/\r\n        . = 0x0;\r\n        KEEP(*(.inttbl))\r\n        . = ALIGN(0x20);\r\n    \tKEEP(*(.sinttbl))\r\n    } >EXTERNAL\r\n\r\n    .data.internal : ALIGN(0x20) {\r\n        PROVIDE(__data_internal_start = ABSOLUTE(.));\r\n        \/* Don't map any data at address zero to avoid issues with C NULL\r\n         * pointer checks\r\n         *\/\r\n        . += 0x4;\r\n\r\n        PROVIDE(__data_start = ABSOLUTE(.));\r\n        *(.data .data.*)\r\n        PROVIDE(__data_end = ABSOLUTE(.));\r\n        PROVIDE(__data_size = ABSOLUTE(+__data_end - __data_start));\r\n\r\n        PROVIDE(__sdata_start = ABSOLUTE(.));\r\n        *(.sdata .sdata.*)\r\n        PROVIDE(__sdata_end = ABSOLUTE(.));\r\n        PROVIDE(__sdata_size = ABSOLUTE(+__sdata_end - __sdata_start));\r\n\r\n        PROVIDE(__data_internal_end = ABSOLUTE(.));\r\n        PROVIDE(__data_internal_size = ABSOLUTE(__data_internal_end - __data_internal_start));\r\n    } >INTERNAL_DATA\r\n\r\n    .data.internal.clone (NOLOAD) : ALIGN(0x20) {\r\n  \t\tPROVIDE(__data_internal_clone_start = ABSOLUTE(.));\r\n\t\t. = ABSOLUTE(. + __data_internal_size);\r\n  \t} >INTERNAL_DATA\r\n\r\n    .data.internal.ro : ALIGN(0x20) {\r\n        PROVIDE(__data_internal_ro_start = ABSOLUTE(.));\r\n        PROVIDE(__rodata_start = ABSOLUTE(.));\r\n        *(.rodata .rodata.*)\r\n        PROVIDE(__rodata_end = ABSOLUTE(.));\r\n        PROVIDE(__rodata_size = ABSOLUTE(+__rodata_end - __rodata_start));\r\n\r\n        PROVIDE(__data_internal_ro_end = ABSOLUTE(.));\r\n        PROVIDE(__data_internal_ro_size = ABSOLUTE(__data_internal_ro_end - __data_internal_ro_start));\r\n    } >INTERNAL_DATA\r\n\r\n    .cst.call : ALIGN(4) {\r\n        PROVIDE(__cst_call_start = ABSOLUTE(.));\r\n        *(.cst.call)\r\n        PROVIDE(__cst_call_end = ABSOLUTE(.));\r\n    } >INTERNAL_DATA\r\n\r\n    .cst.mov : ALIGN(4) {\r\n        PROVIDE(__cst_mov_start = ABSOLUTE(.));\r\n        *(.cst.mov)\r\n        PROVIDE(__cst_mov_end = ABSOLUTE(.));\r\n    } >INTERNAL_DATA\r\n\r\n    .bss (NOLOAD) : ALIGN(0x20) {\r\n        PROVIDE(__bss_start = ABSOLUTE(.));\r\n        *(.bss .bss.*)\r\n        PROVIDE(__common_start = ABSOLUTE(.));\r\n        *(COMMON)\r\n        PROVIDE(__common_end = ABSOLUTE(.));\r\n        PROVIDE(__common_size = ABSOLUTE(+__common_end - __common_start));\r\n        PROVIDE(__bss_end = ABSOLUTE(.));\r\n        PROVIDE(__bss_size = ABSOLUTE(+__bss_end - __bss_start));\r\n    } >INTERNAL_DATA\r\n\r\n    __STACK_SECT (NOLOAD) : ALIGN(0x10) {\r\n        __stack_start = ABSOLUTE(.);\r\n        . = . + __stack_size;\r\n        __stack_end = ABSOLUTE(.);\r\n    } >INTERNAL_DATA\r\n\r\n    .text : ALIGN(0x20) {\r\n        PROVIDE(__text_start = ABSOLUTE(.));\r\n        \/* The __call_saved* functions need to be placed at low addresses for\r\n         * calling with absolute call instructions\r\n         *\/\r\n        *(.text.__call_saved*)\r\n        *(.text .text.*)\r\n\t\t\/* Program sections in external memory should be aligned to the fetch line width\r\n\t\t*\/\r\n\t\t. = ALIGN(0x20);\r\n        PROVIDE(__text_end = ABSOLUTE(.));\r\n    } >EXTERNAL\r\n\r\n    .data.external : ALIGN(0x20) {\r\n        \/** .data1, .rodata1, .sdata1 are all for large symbols which cannot\r\n         * fit in limited internal memory. We put them in external memory by\r\n         * default. *\/\r\n        PROVIDE(__data_external_start = ABSOLUTE(.));\r\n\r\n        PROVIDE(__data1_start = ABSOLUTE(.));\r\n        *(.data1 .data1.*)\r\n        PROVIDE(__data1_end = ABSOLUTE(.));\r\n\r\n        PROVIDE(__sdata1_start = ABSOLUTE(.));\r\n        *(.sdata1 .sdata1.*)\r\n        PROVIDE(__sdata1_end = ABSOLUTE(.));\r\n        PROVIDE(__sdata1_size = ABSOLUTE(+__sdata1_end - __sdata1_start));\r\n\r\n        PROVIDE(__data_external_end = ABSOLUTE(.));\r\n        PROVIDE(__data_external_size = ABSOLUTE(__data_external_end - __data_external_start));\r\n    } >EXTERNAL\r\n\r\n    .data.external.clone (NOLOAD) : ALIGN(0x20) {\r\n        PROVIDE(__data_external_clone_start = ABSOLUTE(.));\r\n\t\t. = ABSOLUTE(. + __data_external_size);\r\n   } >EXTERNAL\r\n\r\n    .data.external.ro : ALIGN(0x20) {\r\n        \/** .data1, .rodata1, .sdata1 are all for large symbols which cannot\r\n         * fit in limited internal memory. We put them in external memory by\r\n         * default. *\/\r\n        PROVIDE(__data_external_ro_start = ABSOLUTE(.));\r\n\r\n        PROVIDE(__rodata1_start = ABSOLUTE(.));\r\n        *(.rodata1 .rodata1.*)\r\n        PROVIDE(__rodata1_end = ABSOLUTE(.));\r\n        PROVIDE(__rodata1_size = ABSOLUTE(+__rodata1_end - __rodata1_start));\r\n\r\n        \/* Constructors and destructors are called once per program invocation,\r\n         * so are never in the hot path; they shouldn't waste space in limited\r\n         * internal memory so we place them in slower, external memory *\/\r\n\r\n        . = ALIGN(4); \/* constructors must be aligned on a word boundary *\/\r\n        PROVIDE(__init_array_start = ABSOLUTE(.));\r\n        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)));\r\n        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array*) SORT_BY_INIT_PRIORITY(.ctors*)));\r\n        PROVIDE(__init_array_end = ABSOLUTE(.));\r\n\r\n        PROVIDE(__fini_array_start = ABSOLUTE(.));\r\n        \/* destructors are run in reverse order of their priority *\/\r\n        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)));\r\n        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array*) SORT_BY_INIT_PRIORITY(.dtors*)));\r\n        PROVIDE(__fini_array_end = ABSOLUTE(.));\r\n\r\n        PROVIDE(__data_external_ro_end = ABSOLUTE(.));\r\n        PROVIDE(__data_external_ro_size = ABSOLUTE(__data_external_ro_end - __data_external_ro_start));\r\n    } >EXTERNAL\r\n\r\n    .bss1 (NOLOAD) : ALIGN(0x20) {\r\n        \/**\r\n         * `.bss1` is for large zero-initialized symbols that do not fit in\r\n         * internal data\r\n         *\/\r\n        PROVIDE(__bss1_start = ABSOLUTE(.));\r\n        *(.bss1 .bss1.*)\r\n        PROVIDE(__large_common_start = ABSOLUTE(.));\r\n        *(LARGE_COMMON)\r\n        PROVIDE(__large_common_end = ABSOLUTE(.));\r\n        PROVIDE(__large_common_size = ABSOLUTE(+__large_common_end - __large_common_start));\r\n        PROVIDE(__bss1_end = ABSOLUTE(.));\r\n        PROVIDE(__bss1_size = ABSOLUTE(+__bss1_end - __bss1_start));\r\n    } >EXTERNAL\r\n\r\n    \/* Program arguments are loaded by `_start` routine from `__arg_sect_start`.\r\n     * When the user has set a zero size for the section, argc, and argv\r\n     * will be zero and NULL, respectively.\r\n     * Although likely small, they are on the slow path so by default they\r\n     * go at the end of external memory\r\n     *\/\r\n    __ARG_SECT (NOLOAD) : ALIGN(0x4) {\r\n        __arg_sect_start = .;\r\n        . = . + (__arg_sect_size ? __arg_sect_size + 4 : 0);\r\n        __arg_sect_end = .;\r\n    } >EXTERNAL\r\n\r\n    __MALLOC_SECT (NOLOAD) : ALIGN(0x10) {\r\n        PROVIDE(__malloc_start = ABSOLUTE(.));\r\n        . = . + __malloc_size;\r\n        PROVIDE(__malloc_end = ABSOLUTE(.));\r\n    } >EXTERNAL\r\n\r\n    data_internal_loadable_addr = __data_internal_clone_start;\r\n    data_external_loadable_addr = __data_external_clone_start;\r\n\r\n    \/DISCARD\/ : {\r\n        \/* Note:  The CEVA Debugger and Restriction Checker use information \r\n         * stored in the \".note.CEVA-arch\" section. Do NOT discard this section\r\n         * for projects in development phase. This section has no effect on the\r\n         * applications footprint *\/\r\n        *(.comment)\r\n        *(.note.GNU-stack)\r\n        \/* The X-DSP ABI uses a custom relocation format stored in its own\r\n         * section. These are left in the binary by default but are unneeded. *\/\r\n        *(.ceva_reloc)\r\n    }\r\n\r\n}\r\n","old_contents":"OUTPUT(a.elf)\r\n\r\n\/* By default, program starts from reset address (the default location of the interrupt table) *\/\r\nENTRY(__cxd_inttbl_start)\r\n\r\n\/** Memory configuration parameters.\r\n *  The parameters become application symbols and can be referred from application\r\n *\/\r\n__internal_data_start = DEFINED(__internal_data_start) ? __internal_data_start : 0x00000000;\r\n__internal_data_size  = DEFINED(__internal_data_size ) ? __internal_data_size  : 256k;\r\n__external_start      = DEFINED(__external_start     ) ? __external_start      : 0x20000000;\r\n__external_size       = DEFINED(__external_size      ) ? __external_size       : 0x60000000;\r\n__rom_start           = DEFINED(__rom_start          ) ? __rom_start           : 0xC0000000;\r\n__rom_size            = DEFINED(__rom_size           ) ? __rom_size            : 1024M;\r\n\r\n__malloc_size         = DEFINED(__malloc_size        ) ? __malloc_size         : 16k;\r\n__stack_size          = DEFINED(__stack_size         ) ? __stack_size          : 16k;\r\n__arg_sect_size       = DEFINED(__arg_sect_size      ) ? __arg_sect_size       : 512;\r\n\r\nMEMORY {\r\n    INTERNAL_DATA  (rw) : ORIGIN = __internal_data_start, LENGTH = __internal_data_size\r\n    EXTERNAL      (rwx) : ORIGIN = __external_start     , LENGTH = __external_size\r\n    ROM            (rx) : ORIGIN = __rom_start          , LENGTH = __rom_size\r\n}\r\n\r\nSECTIONS {\r\n    .inttbl : ALIGN(0x20) {\r\n        \/** The interrupt vector table. Contains the NMI\r\n         *  and maskable interrupt handlers\r\n         *\/\r\n        . = 0x0;\r\n        KEEP(*(.inttbl))\r\n        . = ALIGN(0x20);\r\n    \tKEEP(*(.sinttbl))\r\n    } >EXTERNAL\r\n\r\n    .data.internal : ALIGN(0x20) {\r\n        PROVIDE(__data_internal_start = ABSOLUTE(.));\r\n        \/* Don't map any data at address zero to avoid issues with C NULL\r\n         * pointer checks\r\n         *\/\r\n        . += 0x4;\r\n\r\n        PROVIDE(__data_start = ABSOLUTE(.));\r\n        *(.data .data.*)\r\n        PROVIDE(__data_end = ABSOLUTE(.));\r\n        PROVIDE(__data_size = ABSOLUTE(+__data_end - __data_start));\r\n\r\n        PROVIDE(__sdata_start = ABSOLUTE(.));\r\n        *(.sdata .sdata.*)\r\n        PROVIDE(__sdata_end = ABSOLUTE(.));\r\n        PROVIDE(__sdata_size = ABSOLUTE(+__sdata_end - __sdata_start));\r\n\r\n        PROVIDE(__data_internal_end = ABSOLUTE(.));\r\n        PROVIDE(__data_internal_size = ABSOLUTE(__data_internal_end - __data_internal_start));\r\n    } >INTERNAL_DATA\r\n\r\n    .data.internal.clone (NOLOAD) : ALIGN(0x20) {\r\n  \t\tPROVIDE(__data_internal_clone_start = ABSOLUTE(.));\r\n\t\t. = ABSOLUTE(. + __data_internal_size);\r\n  \t} >INTERNAL_DATA\r\n\r\n    .data.internal.ro : ALIGN(0x20) {\r\n        PROVIDE(__data_internal_ro_start = ABSOLUTE(.));\r\n        PROVIDE(__rodata_start = ABSOLUTE(.));\r\n        *(.rodata .rodata.*)\r\n        PROVIDE(__rodata_end = ABSOLUTE(.));\r\n        PROVIDE(__rodata_size = ABSOLUTE(+__rodata_end - __rodata_start));\r\n\r\n        PROVIDE(__data_internal_ro_end = ABSOLUTE(.));\r\n        PROVIDE(__data_internal_ro_size = ABSOLUTE(__data_internal_ro_end - __data_internal_ro_start));\r\n    } >INTERNAL_DATA\r\n\r\n    .cst.call : ALIGN(4) {\r\n        PROVIDE(__cst_call_start = ABSOLUTE(.));\r\n        *(.cst.call)\r\n        PROVIDE(__cst_call_end = ABSOLUTE(.));\r\n    } >INTERNAL_DATA\r\n\r\n    .cst.mov : ALIGN(4) {\r\n        PROVIDE(__cst_mov_start = ABSOLUTE(.));\r\n        *(.cst.mov)\r\n        PROVIDE(__cst_mov_end = ABSOLUTE(.));\r\n    } >INTERNAL_DATA\r\n\r\n    .bss (NOLOAD) : ALIGN(0x20) {\r\n        PROVIDE(__bss_start = ABSOLUTE(.));\r\n        *(.bss .bss.*)\r\n        PROVIDE(__common_start = ABSOLUTE(.));\r\n        *(COMMON)\r\n        PROVIDE(__common_end = ABSOLUTE(.));\r\n        PROVIDE(__common_size = ABSOLUTE(+__common_end - __common_start));\r\n        PROVIDE(__bss_end = ABSOLUTE(.));\r\n        PROVIDE(__bss_size = ABSOLUTE(+__bss_end - __bss_start));\r\n    } >INTERNAL_DATA\r\n\r\n    __STACK_SECT (NOLOAD) : ALIGN(0x10) {\r\n        __stack_start = ABSOLUTE(.);\r\n        . = . + __stack_size;\r\n        __stack_end = ABSOLUTE(.);\r\n    } >INTERNAL_DATA\r\n\r\n    .text : ALIGN(0x20) {\r\n        PROVIDE(__text_start = ABSOLUTE(.));\r\n        \/* The __call_saved* functions need to be placed at low addresses for\r\n         * calling with absolute call instructions\r\n         *\/\r\n        *(.text.__call_saved*)\r\n        *(.text .text.*)\r\n\t\t\/* Program sections in external memory should be aligned to the fetch line width\r\n\t\t*\/\r\n\t\t. = ALIGN(0x20);\r\n        PROVIDE(__text_end = ABSOLUTE(.));\r\n    } >EXTERNAL\r\n\r\n    .data.external : ALIGN(0x20) {\r\n        \/** .data1, .rodata1, .sdata1 are all for large symbols which cannot\r\n         * fit in limited internal memory. We put them in external memory by\r\n         * default. *\/\r\n        PROVIDE(__data_external_start = ABSOLUTE(.));\r\n\r\n        PROVIDE(__data1_start = ABSOLUTE(.));\r\n        *(.data1 .data1.*)\r\n        PROVIDE(__data1_end = ABSOLUTE(.));\r\n\r\n        PROVIDE(__sdata1_start = ABSOLUTE(.));\r\n        *(.sdata1 .sdata1.*)\r\n        PROVIDE(__sdata1_end = ABSOLUTE(.));\r\n        PROVIDE(__sdata1_size = ABSOLUTE(+__sdata1_end - __sdata1_start));\r\n\r\n        PROVIDE(__data_external_end = ABSOLUTE(.));\r\n        PROVIDE(__data_external_size = ABSOLUTE(__data_external_end - __data_external_start));\r\n    } >EXTERNAL\r\n\r\n    .data.external.clone (NOLOAD) : ALIGN(0x20) {\r\n        PROVIDE(__data_external_clone_start = ABSOLUTE(.));\r\n\t\t. = ABSOLUTE(. + __data_external_size);\r\n   } >EXTERNAL\r\n\r\n    .data.external.ro : ALIGN(0x20) {\r\n        \/** .data1, .rodata1, .sdata1 are all for large symbols which cannot\r\n         * fit in limited internal memory. We put them in external memory by\r\n         * default. *\/\r\n        PROVIDE(__data_external_ro_start = ABSOLUTE(.));\r\n\r\n        PROVIDE(__rodata1_start = ABSOLUTE(.));\r\n        *(.rodata1 .rodata1.*)\r\n        PROVIDE(__rodata1_end = ABSOLUTE(.));\r\n        PROVIDE(__rodata1_size = ABSOLUTE(+__rodata1_end - __rodata1_start));\r\n\r\n        \/* Constructors and destructors are called once per program invocation,\r\n         * so are never in the hot path; they shouldn't waste space in limited\r\n         * internal memory so we place them in slower, external memory *\/\r\n\r\n        . = ALIGN(4); \/* constructors must be aligned on a word boundary *\/\r\n        PROVIDE(__init_array_start = ABSOLUTE(.));\r\n        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)));\r\n        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array*) SORT_BY_INIT_PRIORITY(.ctors*)));\r\n        PROVIDE(__init_array_end = ABSOLUTE(.));\r\n\r\n        PROVIDE(__fini_array_start = ABSOLUTE(.));\r\n        \/* destructors are run in reverse order of their priority *\/\r\n        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)));\r\n        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array*) SORT_BY_INIT_PRIORITY(.dtors*)));\r\n        PROVIDE(__fini_array_end = ABSOLUTE(.));\r\n\r\n        PROVIDE(__data_external_ro_end = ABSOLUTE(.));\r\n        PROVIDE(__data_external_ro_size = ABSOLUTE(__data_external_ro_end - __data_external_ro_start));\r\n    } >EXTERNAL\r\n\r\n    .bss1 (NOLOAD) : ALIGN(0x20) {\r\n        \/**\r\n         * `.bss1` is for large zero-initialized symbols that do not fit in\r\n         * internal data\r\n         *\/\r\n        PROVIDE(__bss1_start = ABSOLUTE(.));\r\n        *(.bss1 .bss1.*)\r\n        PROVIDE(__large_common_start = ABSOLUTE(.));\r\n        *(LARGE_COMMON)\r\n        PROVIDE(__large_common_end = ABSOLUTE(.));\r\n        PROVIDE(__large_common_size = ABSOLUTE(+__large_common_end - __large_common_start));\r\n        PROVIDE(__bss1_end = ABSOLUTE(.));\r\n        PROVIDE(__bss1_size = ABSOLUTE(+__bss1_end - __bss1_start));\r\n    } >EXTERNAL\r\n\r\n    \/* Program arguments are loaded by `_start` routine from `__arg_sect_start`.\r\n     * When the user has set a zero size for the section, argc, and argv\r\n     * will be zero and NULL, respectively.\r\n     * Although likely small, they are on the slow path so by default they\r\n     * go at the end of external memory\r\n     *\/\r\n    __ARG_SECT (NOLOAD) : ALIGN(0x4) {\r\n        __arg_sect_start = .;\r\n        . = . + (__arg_sect_size ? __arg_sect_size + 4 : 0);\r\n        __arg_sect_end = .;\r\n    } >EXTERNAL\r\n\r\n    __MALLOC_SECT (NOLOAD) : ALIGN(0x10) {\r\n        PROVIDE(__malloc_start = ABSOLUTE(.));\r\n        . = . + __malloc_size;\r\n        PROVIDE(__malloc_end = ABSOLUTE(.));\r\n    } >EXTERNAL\r\n\r\n    data_internal_loadable_addr = __data_internal_clone_start;\r\n    data_external_loadable_addr = __data_external_clone_start;\r\n\r\n    \/DISCARD\/ : {\r\n        \/* Note:  The CEVA Debugger and Restriction Checker use information \r\n         * stored in the \".note.CEVA-arch\" section. Do NOT discard this section\r\n         * for projects in development phase. This section has no effect on the\r\n         * applications footprint *\/\r\n        *(.comment)\r\n        *(.note.GNU-stack)\r\n        \/* The X-DSP ABI uses a custom relocation format stored in its own\r\n         * section. These are left in the binary by default but are unneeded. *\/\r\n        *(.ceva_reloc)\r\n    }\r\n\r\n}","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"01444cbafe0a1d1b894c3e03a3f5e6852b1532e9","subject":"change linker script for S110 7.0.0-3-alpha size","message":"change linker script for S110 7.0.0-3-alpha size\n","repos":"jf87\/nrf51-pure-gcc-setup","old_file":"template\/gcc_nrf51_s110.ld","new_file":"template\/gcc_nrf51_s110.ld","new_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x15000, LENGTH = 0x2B000 \/* 84 kB is taken by S110, 172 kB for app. *\/\n  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 \/* 8 kB is taken by S110,8 kB for app. *\/\n}\nINCLUDE \"gcc_nrf51_common.ld\"\n","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x14000, LENGTH = 0x2C000 \/* 80 kB is taken by S110, 176 kB for app. *\/\n  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 \/* 8 kB is taken by S110,8 kB for app. *\/\n}\nINCLUDE \"gcc_nrf51_common.ld\"\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"494cb16f84c6213551c896dbfff244351237dd40","subject":"Expand space for .text section from 0x80000 to 0x81000.","message":"Expand space for .text section from 0x80000 to 0x81000.\n\nSigned-off-by: Tim Callahan <ea16a3c075a6a229c9a452aa4faba7441b41c040@google.com>\n","repos":"google\/CFU-Playground,google\/CFU-Playground,google\/CFU-Playground,google\/CFU-Playground","old_file":"common\/_hps\/hps\/ld\/linker.ld","new_file":"common\/_hps\/hps\/ld\/linker.ld","new_contents":"INCLUDE output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE regions.ld\n\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(SORT(.text.start))\n\t\t*(SORT(.text))\n\t\t*(SORT(.stub))\n\t\t*(SORT(.text.*))\n\t\t*(SORT(.gnu.linkonce.t.*))\n\t\t_etext = .;\n\t} > rom\n\n\t.rodata :\n\t{\n\t\t\/*\n\t\t * Align models and large chunks of data into a constant position\n\t\t *\/\n\t\t. = _ftext + 0x81000;\n\t\t_frodata = .;\n\t\tsrc\/models\/*\/*(SORT(.rodata.*))\n\t\tsrc\/conv2d_??.o(SORT(.rodata.*))  \/* specific to hps_accel *\/\n\t\t. = ALIGN(4096);\n\t\t*(SORT(.rodata))\n\t\t*(SORT(.rodata.*))\n\t\t*(SORT(.gnu.linkonce.r.*))\n\t\t*(SORT(.rodata1))\n\t\t*(SORT(.srodata))\n\t\t*(SORT(.srodata.*))\n\t\t. = ALIGN(8);\n\t\t_erodata = .;\n\t} > rom\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(8);\n\t\t_fdata = .;\n\t\t*(SORT(.data))\n\t\t*(SORT(.data.*))\n\t\t*(SORT(.gnu.linkonce.d.*))\n\t\t*(SORT(.data1))\n\t\t*(SORT(.ramtext))\n\t\t*(SORT(.ramtext.*))\n\t\t_gp = ALIGN(16);\n\t\t*(SORT(.sdata))\n\t\t*(SORT(.sdata.*))\n\t\t*(SORT(.gnu.linkonce.s.*))\n\t\t*(SORT(.sdata2))\n\t\t*(SORT(.sdata2.*))\n\t\t_edata = ALIGN(16); \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss : AT (ADDR(.data) + SIZEOF (.data))\n\t{\n\t\t. = ALIGN(16);\n\t\t_fbss = .;\n\t\t*(SORT(.dynsbss))\n\t\t*(SORT(.sbss))\n\t\t*(SORT(.sbss.*))\n\t\t*(SORT(.gnu.linkonce.sb.*))\n\t\t*(SORT(.scommon))\n\t\t*(SORT(.dynbss))\n\t\t*(SORT(.bss))\n\t\t*(SORT(.bss.*))\n\t\t*(SORT(.gnu.linkonce.b.*))\n\t\t*(SORT(COMMON))\n\t\t. = ALIGN(8);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n\n        .arena (NOLOAD) :\n        {\n                _farena = .;\n                *(.arena)\n                _earena = .;\n        } > arena\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","old_contents":"INCLUDE output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE regions.ld\n\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(SORT(.text.start))\n\t\t*(SORT(.text))\n\t\t*(SORT(.stub))\n\t\t*(SORT(.text.*))\n\t\t*(SORT(.gnu.linkonce.t.*))\n\t\t_etext = .;\n\t} > rom\n\n\t.rodata :\n\t{\n\t\t\/*\n\t\t * Align models and large chunks of data into a constant position\n\t\t *\/\n\t\t. = _ftext + 0x80000;\n\t\t_frodata = .;\n\t\tsrc\/models\/*\/*(SORT(.rodata.*))\n\t\tsrc\/conv2d_??.o(SORT(.rodata.*))  \/* specific to hps_accel *\/\n\t\t. = ALIGN(4096);\n\t\t*(SORT(.rodata))\n\t\t*(SORT(.rodata.*))\n\t\t*(SORT(.gnu.linkonce.r.*))\n\t\t*(SORT(.rodata1))\n\t\t*(SORT(.srodata))\n\t\t*(SORT(.srodata.*))\n\t\t. = ALIGN(8);\n\t\t_erodata = .;\n\t} > rom\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(8);\n\t\t_fdata = .;\n\t\t*(SORT(.data))\n\t\t*(SORT(.data.*))\n\t\t*(SORT(.gnu.linkonce.d.*))\n\t\t*(SORT(.data1))\n\t\t*(SORT(.ramtext))\n\t\t*(SORT(.ramtext.*))\n\t\t_gp = ALIGN(16);\n\t\t*(SORT(.sdata))\n\t\t*(SORT(.sdata.*))\n\t\t*(SORT(.gnu.linkonce.s.*))\n\t\t*(SORT(.sdata2))\n\t\t*(SORT(.sdata2.*))\n\t\t_edata = ALIGN(16); \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss : AT (ADDR(.data) + SIZEOF (.data))\n\t{\n\t\t. = ALIGN(16);\n\t\t_fbss = .;\n\t\t*(SORT(.dynsbss))\n\t\t*(SORT(.sbss))\n\t\t*(SORT(.sbss.*))\n\t\t*(SORT(.gnu.linkonce.sb.*))\n\t\t*(SORT(.scommon))\n\t\t*(SORT(.dynbss))\n\t\t*(SORT(.bss))\n\t\t*(SORT(.bss.*))\n\t\t*(SORT(.gnu.linkonce.b.*))\n\t\t*(SORT(COMMON))\n\t\t. = ALIGN(8);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n\n        .arena (NOLOAD) :\n        {\n                _farena = .;\n                *(.arena)\n                _earena = .;\n        } > arena\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"64a7594ca3f5f9493a4909edefa4787948b87b68","subject":"doc: Disable custom template and style","message":"doc: Disable custom template and style\n","repos":"hotgloupi\/configure,hotgloupi\/configure,hotgloupi\/configure,hotgloupi\/configure,hotgloupi\/configure","old_file":"doc\/config.ld","new_file":"doc\/config.ld","new_contents":"add_language_extension(\"cpp\", \"c\")\nadd_language_extension(\"hpp\", \"c\")\nfile = {\"..\/src\/lib\/configure\", \"..\/src\/configure\"}\nproject = \"configure\"\npackage = \"configure\"\ndescription = \"Configure your projects' builds\"\none = false\nsort = true\nmerge = true\n--topics = {'..\/README.md'}\nreadme = '..\/README.md'\nkind_names = {topic = 'Manual',}\n-- template = true\n-- style = true\nformat = 'discount'\n","old_contents":"add_language_extension(\"cpp\", \"c\")\nadd_language_extension(\"hpp\", \"c\")\nfile = {\"..\/src\/lib\/configure\", \"..\/src\/configure\"}\nproject = \"configure\"\npackage = \"configure\"\ndescription = \"Configure your projects' builds\"\none = false\nsort = true\nmerge = true\ntopics = {'..\/README.md'}\nkind_names = {topic = 'Manual',}\ntemplate = true\nstyle = true\nformat = 'discount'\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"6ee66d92e76ec8831eac2edd4ec58b07eed89f7a","subject":"[bsp][sam7x] Fix compile error. Increase DATA section size in .ld file.","message":"[bsp][sam7x] Fix compile error. Increase DATA section size in .ld file.\n","repos":"wolfgangz2013\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,yongli3\/rt-thread,yongli3\/rt-thread,geniusgogo\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,wolfgangz2013\/rt-thread,wolfgangz2013\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,FlyLu\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,hezlog\/rt-thread,AubrCool\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,armink\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,AubrCool\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,armink\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,wolfgangz2013\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,igou\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,yongli3\/rt-thread,RT-Thread\/rt-thread,AubrCool\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,yongli3\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread","old_file":"bsp\/sam7x\/sam7x_rom.ld","new_file":"bsp\/sam7x\/sam7x_rom.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nMEMORY\n{\n    CODE (rx) : ORIGIN = 0x00100000, LENGTH = 0x00040000\n    \/* DATA (rw) : ORIGIN = 0x00200000, LENGTH = 0x00010000 *\/\n    DATA (rw) : ORIGIN = 0x00203000, LENGTH = 0x0000D000\n}\nENTRY(_start)\nSECTIONS\n{\n    .text :\n    {\n        *(.init)\n        *(.text)\n        *(.rodata)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n    } > CODE = 0\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    } > CODE\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    } > CODE\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > CODE\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >DATA\n    __data_end = .;\n\n    .noinit :\n    {\n        *(.bss.noinit)\n    } > DATA\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        _estack = .;\n    } > DATA\n    __bss_end = .;\n\n    _end = .;\n\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nMEMORY\n{\n    CODE (rx) : ORIGIN = 0x00100000, LENGTH = 0x00040000\n    \/* DATA (rw) : ORIGIN = 0x00200000, LENGTH = 0x00010000 *\/\n    DATA (rw) : ORIGIN = 0x00204000, LENGTH = 0x0000C000\n}\nENTRY(_start)\nSECTIONS\n{\n    .text :\n    {\n        *(.init)\n        *(.text)\n        *(.rodata)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n    } > CODE = 0\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    } > CODE\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    } > CODE\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > CODE\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >DATA\n    __data_end = .;\n\n    .noinit :\n    {\n        *(.bss.noinit)\n    } > DATA\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        _estack = .;\n    } > DATA\n    __bss_end = .;\n\n    _end = .;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b121c9515d60347b227e22faa8c54474a329a9e0","subject":"stm32\/boards\/stm32h743.ld: Remove include of common.ld.","message":"stm32\/boards\/stm32h743.ld: Remove include of common.ld.\n\nThe relevant common.ld file should now be included explicitly by a\nparticular board.\n","repos":"pozetroninc\/micropython,kerneltask\/micropython,dmazzella\/micropython,selste\/micropython,tralamazza\/micropython,ryannathans\/micropython,henriknelson\/micropython,henriknelson\/micropython,adafruit\/circuitpython,henriknelson\/micropython,adafruit\/circuitpython,adafruit\/micropython,pfalcon\/micropython,pozetroninc\/micropython,adafruit\/circuitpython,trezor\/micropython,trezor\/micropython,bvernoux\/micropython,swegener\/micropython,dmazzella\/micropython,pramasoul\/micropython,bvernoux\/micropython,adafruit\/micropython,MrSurly\/micropython,kerneltask\/micropython,pfalcon\/micropython,swegener\/micropython,tralamazza\/micropython,adafruit\/micropython,tobbad\/micropython,ryannathans\/micropython,ryannathans\/micropython,MrSurly\/micropython,kerneltask\/micropython,tralamazza\/micropython,pfalcon\/micropython,trezor\/micropython,bvernoux\/micropython,trezor\/micropython,adafruit\/micropython,pozetroninc\/micropython,bvernoux\/micropython,pfalcon\/micropython,pozetroninc\/micropython,MrSurly\/micropython,pramasoul\/micropython,adafruit\/circuitpython,dmazzella\/micropython,selste\/micropython,dmazzella\/micropython,ryannathans\/micropython,kerneltask\/micropython,swegener\/micropython,pramasoul\/micropython,pramasoul\/micropython,MrSurly\/micropython,pfalcon\/micropython,adafruit\/circuitpython,tobbad\/micropython,kerneltask\/micropython,selste\/micropython,pramasoul\/micropython,tobbad\/micropython,adafruit\/micropython,bvernoux\/micropython,swegener\/micropython,pozetroninc\/micropython,selste\/micropython,tobbad\/micropython,MrSurly\/micropython,henriknelson\/micropython,tobbad\/micropython,swegener\/micropython,ryannathans\/micropython,selste\/micropython,adafruit\/circuitpython,tralamazza\/micropython,trezor\/micropython,henriknelson\/micropython","old_file":"ports\/stm32\/boards\/stm32h743.ld","new_file":"ports\/stm32\/boards\/stm32h743.ld","new_contents":"\/*\n    GNU linker script for STM32H743\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 128K    \/* sector 0, 128K *\/\n    FLASH_FS (r)    : ORIGIN = 0x08020000, LENGTH = 128K    \/* sector 1, 128K *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K   \/* sectors 6*128 + 8*128 *\/\n    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    \/* Used for storage cache *\/\n    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 512K    \/* AXI SRAM *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = 0x2407C000; \/* tunable *\/\n","old_contents":"\/*\n    GNU linker script for STM32H743\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 128K    \/* sector 0, 128K *\/\n    FLASH_FS (r)    : ORIGIN = 0x08020000, LENGTH = 128K    \/* sector 1, 128K *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K   \/* sectors 6*128 + 8*128 *\/\n    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    \/* Used for storage cache *\/\n    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 512K    \/* AXI SRAM *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define common sections and symbols *\/\nINCLUDE common.ld\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = 0x2407C000; \/* tunable *\/\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"82672bf26dd3c0346b5821228eeac938fc057822","subject":"Move persistent storage into top of the flash","message":"Move persistent storage into top of the flash\n","repos":"laneboysrc\/nrf24l01-rc,laneboysrc\/nrf24l01-rc,laneboysrc\/nrf24l01-rc","old_file":"firmware\/lpc812-nrf24l01-receiver\/receiver.ld","new_file":"firmware\/lpc812-nrf24l01-receiver\/receiver.ld","new_contents":"MEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x4000            \/* 16K *\/\n  RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x1000      \/* 4K *\/\n}\n\nSECTIONS\n{\n    .vectors :\n    {\n        _text = .;\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n    } > FLASH\n\n\n    .text :\n    {\n        KEEP(*(.after_vectors))\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        _etext = .;\n    } > FLASH\n\n\n    .data : AT (_etext)\n    {\n        _data = .;\n        *(.survivors)       \/* 80 bytes that survive reset in LPC81x *\/\n        *(.data*)\n        . = ALIGN(4);\n        _edata = .;\n    } > RAM\n\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n    } > RAM\n\n\n    \/* Use the top-most page in flash to store the persistent data *\/\n    .persistent_data : AT (0x4000 - 64)\n    {\n        KEEP(*(.persistent_data))\n    } > FLASH\n\n\n    \/* The stack starts 32 bytes below to of RAM as those 32 bytes are needed\n     * for the IAR ROM function that we use to write the Flash with persistent\n     * data.\n     *\/\n    _stacktop = ORIGIN(RAM) + LENGTH(RAM) - 32;\n}\n","old_contents":"MEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x4000            \/* 16K *\/\n  RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x1000      \/* 4K *\/\n}\n\nSECTIONS\n{\n    .vectors :\n    {\n        _text = .;\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n    } > FLASH\n\n\n    .persistent_data :\n    {\n        . = ALIGN(64);\n        KEEP(*(.persistent_data))\n        . = ALIGN(64);\n    } > FLASH\n\n\n    .text :\n    {\n        KEEP(*(.after_vectors))\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        _etext = .;\n    } > FLASH\n\n\n    .data : AT (_etext)\n    {\n        _data = .;\n        *(.survivors)       \/* 80 bytes that survive reset in LPC81x *\/\n        *(.data*)\n        . = ALIGN(4);\n        _edata = .;\n    } > RAM\n\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n    } > RAM\n\n\n    \/* The stack starts 32 bytes below to of RAM as those 32 bytes are needed\n     * for the IAR ROM function that we use to write the Flash with persistent\n     * data.\n     *\/\n    _stacktop = ORIGIN(RAM) + LENGTH(RAM) - 32;\n}\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"1588b45a8a15e4d3f1b42f052fc41590e9bec0bb","subject":"Force core_version to be added to compiled binary","message":"Force core_version to be added to compiled binary\n","repos":"gguuss\/Arduino,Juppit\/Arduino,Adam5Wu\/Arduino,wemos\/Arduino,quertenmont\/Arduino,Lan-Hekary\/Arduino,hallard\/Arduino,Lan-Hekary\/Arduino,quertenmont\/Arduino,lrmoreno007\/Arduino,me-no-dev\/Arduino,sticilface\/Arduino,lrmoreno007\/Arduino,Juppit\/Arduino,sticilface\/Arduino,Juppit\/Arduino,hallard\/Arduino,toastedcode\/esp8266-Arduino,toastedcode\/esp8266-Arduino,Adam5Wu\/Arduino,Juppit\/Arduino,sticilface\/Arduino,esp8266\/Arduino,quertenmont\/Arduino,quertenmont\/Arduino,martinayotte\/ESP8266-Arduino,esp8266\/Arduino,toastedcode\/esp8266-Arduino,me-no-dev\/Arduino,jes\/Arduino,hallard\/Arduino,esp8266\/Arduino,Lan-Hekary\/Arduino,gguuss\/Arduino,lrmoreno007\/Arduino,jes\/Arduino,toastedcode\/esp8266-Arduino,toastedcode\/esp8266-Arduino,lrmoreno007\/Arduino,martinayotte\/ESP8266-Arduino,lrmoreno007\/Arduino,esp8266\/Arduino,gguuss\/Arduino,jes\/Arduino,wemos\/Arduino,Lan-Hekary\/Arduino,wemos\/Arduino,sticilface\/Arduino,martinayotte\/ESP8266-Arduino,martinayotte\/ESP8266-Arduino,Adam5Wu\/Arduino,Adam5Wu\/Arduino,quertenmont\/Arduino,me-no-dev\/Arduino,wemos\/Arduino,wemos\/Arduino,Lan-Hekary\/Arduino,jes\/Arduino,gguuss\/Arduino,jes\/Arduino,esp8266\/Arduino,me-no-dev\/Arduino,martinayotte\/ESP8266-Arduino,sticilface\/Arduino,me-no-dev\/Arduino,gguuss\/Arduino,Juppit\/Arduino,hallard\/Arduino,Adam5Wu\/Arduino,hallard\/Arduino","old_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nEXTERN(core_version)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    *libc.a:(.literal .text .literal.* .text.*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    *libc.a:(.literal .text .literal.* .text.*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"37df83d8564c2643d0a472173f894fd318236678","subject":"layout_riscv32.ld: Update the SRAM size to be correct","message":"layout_riscv32.ld: Update the SRAM size to be correct\n\nReduce the size so we don't go over the memory avaliable in the hardware\nor QEMU.\n\nSigned-off-by: Alistair Francis <52ecf00b70a50079ae8d5fa09b9af6904950b63c@wdc.com>\n","repos":"tock\/libtock-rs","old_file":"layout_riscv32.ld","new_file":"layout_riscv32.ld","new_contents":"\/* Layout for the RISC-V 32 boards, used by the examples in this repository. *\/\n\nMEMORY {\n  \/*\n   * The TBF header can change in size so use 0x40 combined with\n   * --protected-region-size with elf2tab to cover a header upto that\n   * size.\n   *\n   * Note that the SRAM address may need to be changed depending on\n   * the kernel binary, check for the actual address of APP_MEMORY!\n   *\/\n  FLASH (rx) : ORIGIN = 0x20430040, LENGTH = 32M\n  SRAM (rwx) : ORIGIN = 0x80002400, LENGTH = 0x1C00\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 1K;\n\nINCLUDE layout_generic.ld\n","old_contents":"\/* Layout for the RISC-V 32 boards, used by the examples in this repository. *\/\n\nMEMORY {\n  \/*\n   * The TBF header can change in size so use 0x40 combined with\n   * --protected-region-size with elf2tab to cover a header upto that\n   * size.\n   *\n   * Note that the SRAM address may need to be changed depending on\n   * the kernel binary, check for the actual address of APP_MEMORY!\n   *\/\n  FLASH (rx) : ORIGIN = 0x20430040, LENGTH = 32M\n  SRAM (rwx) : ORIGIN = 0x80002400, LENGTH = 512K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 1K;\n\nINCLUDE layout_generic.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"634b2bd10213785ec3413a1a146a6a49d5ebe8a8","subject":"update stack size","message":"update stack size\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX71M\/R5F571MF.ld","new_file":"RX71M\/R5F571MF.ld","new_contents":"\/*!\t@file\n\t@brief\tRX71M R5F571MF \u30ea\u30f3\u30ab\u30fc\u30fb\u30b9\u30af\u30ea\u30d7\u30c8\n    @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\t@copyright\tCopyright (C) 2018 Kunihito Hiramatsu @n\n\t\t\t\tReleased under the MIT license @n\n\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX64M chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x0007C000 \/* 512k - (USTACK+ISTACK)(0x2000) *\/\n\tUSTACK (w) : ORIGIN = 0x0007E000, LENGTH = 4 \/* ustack 8192 *\/\n\tISTACK (w) : ORIGIN = 0x00080000, LENGTH = 4 \/* istack 8192 *\/\n\tROM (w)    : ORIGIN = 0xFFE00000, LENGTH = 0x001FFFD0 \/* 2M *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .istack (ORIGIN (ISTACK)) :\n  {\n    PROVIDE (__istack = .);\n    *(.istack)\n  }\n\n  .ustack (ORIGIN (USTACK)) :\n  {\n    PROVIDE (__ustack = .);\n    *(.ustack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*!\t@file\n\t@brief\tRX71M R5F571MF \u30ea\u30f3\u30ab\u30fc\u30fb\u30b9\u30af\u30ea\u30d7\u30c8\n    @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\t@copyright\tCopyright (C) 2017 Kunihito Hiramatsu @n\n\t\t\t\tReleased under the MIT license @n\n\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)   : ORIGIN = 0x00000000, LENGTH = 0x00080000 \/* 512K bytes (+32K) *\/\n\tSTACK (w) : ORIGIN = 0x00080000, LENGTH = 16 \/* top of RAM *\/\n\n\tROM (w)   : ORIGIN = 0xFFE00000, LENGTH = 0x001FFFD0 \/* 2M bytes *\/\n\/* This is the largest RX6000: *\/\n\/*\tROM (w)   : ORIGIN = 0xFFE00000, LENGTH = 0x001FFFD0 *\/ \/* 2Mb *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"f836363343ceff0742d6bd124a1b37c9d00447c0","subject":"cleanup linker","message":"cleanup linker\n","repos":"jezze\/fudge,jezze\/fudge,jezze\/fudge","old_file":"linker-x86.ld","new_file":"linker-x86.ld","new_contents":"ENTRY (loader)\n\nSECTIONS\n{\n\n    . = 0x00100000;\n\n    .text :\n    {\n        *(.text)\n    }\n\n    .rodata ALIGN (0x1000) :\n    {\n        *(.rodata)\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        *(.data)\n    }\n\n    .bss :\n    {\n        *(.bss)\n    }\n\n}\n","old_contents":"ENTRY (loader)\n\nSECTIONS\n{\n\n\t. = 0x00100000;\n\n\t.text :\n\t{\n\t\t*(.text)\n\t}\n\n\t.rodata ALIGN (0x1000) :\n\t{\n\t\t*(.rodata)\n\t}\n\n\t.data ALIGN (0x1000) :\n\t{\n\t\t*(.data)\n\t}\n\n\t.bss :\n\t{\n\t\t*(.bss)\n\t}\n\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3300d2898b637a65cfc0ecf387787c18846c28bf","subject":"nrf51_16k_s130 Fix flash origin for APP_CODE_BASE For details see: http:\/\/infocenter.nordicsemi.com\/index.jsp?topic=%2Fcom.nordic.infocenter.s130.sds%2Fdita%2Fsoftdevices%2Fs130%2Fmem_usage%2Fmem_resource_reqs.html","message":"nrf51_16k_s130 Fix flash origin for APP_CODE_BASE\nFor details see: http:\/\/infocenter.nordicsemi.com\/index.jsp?topic=%2Fcom.nordic.infocenter.s130.sds%2Fdita%2Fsoftdevices%2Fs130%2Fmem_usage%2Fmem_resource_reqs.html\n\nSet the ram start to 0x20002ef8 to be consistent with ATM_STD and IAR linker scripts\n","repos":"betzw\/mbed-os,c1728p9\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,betzw\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,c1728p9\/mbed-os,kjbracey-arm\/mbed,betzw\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,betzw\/mbed-os,mbedmicro\/mbed,betzw\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,betzw\/mbed-os","old_file":"targets\/TARGET_NORDIC\/TARGET_NRF5x\/TARGET_NRF51\/TARGET_MCU_NRF51822_UNIFIED\/device\/TOOLCHAIN_GCC_ARM\/TARGET_MCU_NRF51_16K_S130\/NRF51822.ld","new_file":"targets\/TARGET_NORDIC\/TARGET_NRF5x\/TARGET_NRF51\/TARGET_MCU_NRF51822_UNIFIED\/device\/TOOLCHAIN_GCC_ARM\/TARGET_MCU_NRF51_16K_S130\/NRF51822.ld","new_contents":"\/* Linker script to configure memory regions. *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x24000\n  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0x1108\n}\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.Vectors))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n        \n\t\t. = ALIGN(4);\n\t\tPROVIDE(__start_fs_data = .);\n\t\tKEEP(*(.fs_data))\n\t\tPROVIDE(__stop_fs_data = .);\n\n\t\t*(.jcr)\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n    .noinit :\n    {\n      PROVIDE(__start_noinit = .);\n      KEEP(*(.noinit))\n      PROVIDE(__stop_noinit = .);\n    } > RAM\n    \n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (NOLOAD):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t__HeapBase = .;\n\t\t*(.heap*)\n\t\t. = ORIGIN(RAM) + LENGTH(RAM) - Stack_Size;\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (NOLOAD):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0001C000, LENGTH = 0x24000\n  RAM (rwx) :  ORIGIN = 0x20002800, LENGTH = 0x1800\n}\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.Vectors))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n        \n\t\t. = ALIGN(4);\n\t\tPROVIDE(__start_fs_data = .);\n\t\tKEEP(*(.fs_data))\n\t\tPROVIDE(__stop_fs_data = .);\n\n\t\t*(.jcr)\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n    .noinit :\n    {\n      PROVIDE(__start_noinit = .);\n      KEEP(*(.noinit))\n      PROVIDE(__stop_noinit = .);\n    } > RAM\n    \n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (NOLOAD):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t__HeapBase = .;\n\t\t*(.heap*)\n\t\t. = ORIGIN(RAM) + LENGTH(RAM) - Stack_Size;\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (NOLOAD):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2371176681725884bf7d2c6dc23a507b3ca9b098","subject":"Fix flash origin address.","message":"Fix flash origin address.\n","repos":"charleskorn\/stm32f4-project-template,charleskorn\/stm32f4-project-template,charleskorn\/stm32f4-project-template","old_file":"lib\/stm32f4xx\/src\/stm32f407vg.ld","new_file":"lib\/stm32f4xx\/src\/stm32f407vg.ld","new_contents":"\/* Linker script for STM32F407VG Cortex-M4 ARM MCU *\/\n\/* From http:\/\/tech.munts.com\/MCU\/Frameworks\/ARM\/stm32f4\/stm32f407vg.ld *\/\n\n\/* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp.\t\t*\/\n\/*\t\t\t\t\t\t\t\t\t\t*\/\n\/* Redistribution and use in source and binary forms, with or without\t\t*\/\n\/* modification, are permitted provided that the following conditions are met:\t*\/\n\/*\t\t\t\t\t\t\t\t\t\t*\/\n\/* * Redistributions of source code must retain the above copyright notice,\t*\/\n\/*   this list of conditions and the following disclaimer.\t\t\t*\/\n\/*\t\t\t\t\t\t\t\t\t\t*\/\n\/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\t*\/\n\/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\t*\/\n\/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\t*\/\n\/* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\t*\/\n\/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\t\t*\/\n\/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\t\t*\/\n\/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\t*\/\n\/* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\t*\/\n\/* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\t*\/\n\/* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\t*\/\n\/* POSSIBILITY OF SUCH DAMAGE.\t\t\t\t\t\t\t*\/\n\nMEMORY\n{\n  flash (rx)  : ORIGIN = 0x08000000, LENGTH = 1024K\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K\n  ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n__rom_start__\t= ORIGIN(flash);\n__rom_size__\t= LENGTH(flash);\n__ram_start__\t= ORIGIN(ram);\n__ram_size__\t= LENGTH(ram);\n__ram_end__\t= __ram_start__ + __ram_size__;\n__stack_end__\t= __ram_end__;\t\t\/* Top of RAM *\/\n__stack_size__\t= 16K;\n__stack_start__\t= __stack_end__ - __stack_size__;\n__heap_start__\t= __bss_end__;\t\t\/* Between bss and stack *\/\n__heap_end__\t= __stack_start__;\n__ccm_start__\t= ORIGIN(ccm);\n__ccm_size__\t= LENGTH(ccm);\n\nSECTIONS\n{\n  . = 0;\n\n  .text : {\n  KEEP(*(.startup))\t\t\t\/* Startup code *\/\n  *(.text*)\t\t\t\t\/* Program code *\/\n  KEEP(*(.rodata*))\t\t\t\/* Read only data *\/\n  *(.glue_7)\n  *(.glue_7t)\n  *(.eh_frame)\n  . = ALIGN(4);\n  __ctors_start__ = .;\n  KEEP(*(.init_array))\t\t\t\/* C++ constructors *\/\n  KEEP(*(.ctors))\t\t\t\/* C++ constructors *\/\n  __ctors_end__ = .;\n  . = ALIGN(16);\n  __text_end__ = .;\n  } >flash\n\n  .data : ALIGN(16) {\n  __data_beg__ = .;\t\t\t\/* Used in crt0.S *\/\n  *(.data*)\t\t\t\t\/* Initialized data *\/\n  __data_end__ = .;\t\t\t\/* Used in crt0.S *\/\n  } >ram AT > flash\n\n  .bss (NOLOAD) : ALIGN(16) {\n  __bss_beg__ = .;\t\t\t\/* Used in crt0.S *\/\n  *(.bss*)\t\t\t\t\/* Uninitialized data *\/\n  *(COMMON)\t\t\t\t\/* Common data *\/\n  __bss_end__ = .;\t\t\t\/* Used in crt0.S *\/\n  } >ram\n\n\/* C++ exception unwinding stuff--needed by some toolchains *\/\n\n  .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash\n\n  __exidx_start = .;\n  .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash\n  __exidx_end = .;\n}\n\n\/* Firmware entry point *\/\n\nENTRY(_vectors)\n","old_contents":"\/* Linker script for STM32F407VG Cortex-M4 ARM MCU *\/\n\/* From http:\/\/tech.munts.com\/MCU\/Frameworks\/ARM\/stm32f4\/stm32f407vg.ld *\/\n\n\/* Copyright (C)2013-2016, Philip Munts, President, Munts AM Corp.\t\t*\/\n\/*\t\t\t\t\t\t\t\t\t\t*\/\n\/* Redistribution and use in source and binary forms, with or without\t\t*\/\n\/* modification, are permitted provided that the following conditions are met:\t*\/\n\/*\t\t\t\t\t\t\t\t\t\t*\/\n\/* * Redistributions of source code must retain the above copyright notice,\t*\/\n\/*   this list of conditions and the following disclaimer.\t\t\t*\/\n\/*\t\t\t\t\t\t\t\t\t\t*\/\n\/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\t*\/\n\/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\t*\/\n\/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\t*\/\n\/* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\t*\/\n\/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\t\t*\/\n\/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\t\t*\/\n\/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\t*\/\n\/* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\t*\/\n\/* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\t*\/\n\/* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\t*\/\n\/* POSSIBILITY OF SUCH DAMAGE.\t\t\t\t\t\t\t*\/\n\nMEMORY\n{\n  flash (rx)  : ORIGIN = 0x00000000, LENGTH = 1024K\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K\n  ccm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n__rom_start__\t= ORIGIN(flash);\n__rom_size__\t= LENGTH(flash);\n__ram_start__\t= ORIGIN(ram);\n__ram_size__\t= LENGTH(ram);\n__ram_end__\t= __ram_start__ + __ram_size__;\n__stack_end__\t= __ram_end__;\t\t\/* Top of RAM *\/\n__stack_size__\t= 16K;\n__stack_start__\t= __stack_end__ - __stack_size__;\n__heap_start__\t= __bss_end__;\t\t\/* Between bss and stack *\/\n__heap_end__\t= __stack_start__;\n__ccm_start__\t= ORIGIN(ccm);\n__ccm_size__\t= LENGTH(ccm);\n\nSECTIONS\n{\n  . = 0;\n\n  .text : {\n  KEEP(*(.startup))\t\t\t\/* Startup code *\/\n  *(.text*)\t\t\t\t\/* Program code *\/\n  KEEP(*(.rodata*))\t\t\t\/* Read only data *\/\n  *(.glue_7)\n  *(.glue_7t)\n  *(.eh_frame)\n  . = ALIGN(4);\n  __ctors_start__ = .;\n  KEEP(*(.init_array))\t\t\t\/* C++ constructors *\/\n  KEEP(*(.ctors))\t\t\t\/* C++ constructors *\/\n  __ctors_end__ = .;\n  . = ALIGN(16);\n  __text_end__ = .;\n  } >flash\n\n  .data : ALIGN(16) {\n  __data_beg__ = .;\t\t\t\/* Used in crt0.S *\/\n  *(.data*)\t\t\t\t\/* Initialized data *\/\n  __data_end__ = .;\t\t\t\/* Used in crt0.S *\/\n  } >ram AT > flash\n\n  .bss (NOLOAD) : ALIGN(16) {\n  __bss_beg__ = .;\t\t\t\/* Used in crt0.S *\/\n  *(.bss*)\t\t\t\t\/* Uninitialized data *\/\n  *(COMMON)\t\t\t\t\/* Common data *\/\n  __bss_end__ = .;\t\t\t\/* Used in crt0.S *\/\n  } >ram\n\n\/* C++ exception unwinding stuff--needed by some toolchains *\/\n\n  .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >flash\n\n  __exidx_start = .;\n  .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >flash\n  __exidx_end = .;\n}\n\n\/* Firmware entry point *\/\n\nENTRY(_vectors)\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e2f6bc63ce1c1d56a0d4c5697ec673544411f24e","subject":"add some symbol","message":"add some symbol\n","repos":"tjjh89017\/arm-slave,tjjh89017\/arm-slave","old_file":"src\/kernel.ld","new_file":"src\/kernel.ld","new_contents":"OUTPUT_ARCH(arm)\nENTRY(_start)\n\nENTRY_SVC_STACK_SIZE = 0x1000;\n\nSECTIONS\n{\n\t. = 0x10000;\n\t.start_section : {\n\t\tboot.o(.text .text.*)\n\t\tstart.o(.text .text.*)\n\n\t\tboot.o(.rodata .rodata.*)\n\t\tstart.o(.rodata .rodata.*)\n\n\t\tboot.o(.data .data.*)\n\t\tstart.o(.data .data.*)\n\n\t\tPROVIDE(boot_data_start = .);\n\t\tPROVIDE(boot_bss_start = .);\n\n\t\tboot.o(.bss .bss.* COMMON)\n\t\tstart.o(.bss .bss.* COMMON)\n\n\t\t. = ALIGN(0x1000);\n\t\tPROVIDE(boot_bss_end = .);\n\n\t\t\/* define a stack for boot *\/\n\t\t. += ENTRY_SVC_STACK_SIZE;\n\t\tPROVIDE(svc_stack = .);\n\n\t\t. = ALIGN(0x4000);\n\t\t\/* for kernel page table *\/\n\t\tPROVIDE(_kernel_pgd = .);\n\t\t. += 0x4000;\n\n\t\t\/* for user page table *\/\n\t\tPROVIDE(_user_pgd = .);\n\t\t. += 0x1000;\n\n\t\tPROVIDE(boot_data_end = .);\n\t}\n\n\tPROVIDE(end = .);\n}\n","old_contents":"OUTPUT_ARCH(arm)\nENTRY(_start)\n\nENTRY_SVC_STACK_SIZE = 0x1000;\n\nSECTIONS\n{\n\t. = 0x10000;\n\t.start_section : {\n\t\tboot.o(.text .text.*)\n\t\tstart.o(.text .text.*)\n\n\t\tboot.o(.rodata .rodata.*)\n\t\tstart.o(.rodata .rodata.*)\n\n\t\tboot.o(.data .data.*)\n\t\tstart.o(.data .data.*)\n\n\t\tPROVIDE(boot_data_start = .);\n\t\tPROVIDE(boot_bss_start = .);\n\n\t\tboot.o(.bss .bss.* COMMON)\n\t\tstart.o(.bss .bss.* COMMON)\n\n\t\t. = ALIGN(0x1000);\n\t\tPROVIDE(boot_bss_end = .);\n\n\t\t\/* define a stack for boot *\/\n\t\t. += ENTRY_SVC_STACK_SIZE;\n\t\tPROVIDE(svc_stack = .);\n\n\t\t\/* for kernel page table *\/\n\t\t\/* for user page table *\/\n\n\t\tPROVIDE(boot_data_end = .);\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b822b351c71f4dd9a6abaf8ebf4a642d2f8ef12f","subject":"add paths","message":"add paths\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa_cp.ld","new_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa_cp.ld","new_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x23000, LENGTH = 0x5d000\r\n\tRAM (rwx) :  ORIGIN = 0x20002B00, LENGTH = 0xd500\r\n\t\/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n\t*  from application to bootloader when using buttonluss DFU OTA.\r\n\t*\/\r\n\tNOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n\t\/** Location of bootloader setting in flash. *\/\r\n\tBOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n}\r\n\r\n\r\nSECTIONS\r\n{\r\n\t\/* Place the bootloader settings page in flash. *\/\r\n\t.bootloaderSettings(NOLOAD) :\r\n\t{\r\n\r\n\t} > BOOTLOADER_SETTINGS\r\n\r\n\t\/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n\t.noinit(NOLOAD) :\r\n\t{\r\n\r\n\t} > NOINIT\r\n}\r\n\r\nSECTIONS\r\n{\r\n  .pwr_mgmt_data :\r\n  {\r\n    PROVIDE(__start_pwr_mgmt_data = .);\r\n    KEEP(*(SORT(.pwr_mgmt_data*)))\r\n    PROVIDE(__stop_pwr_mgmt_data = .);\r\n  } > FLASH\r\n  \r\n  .log_const_data :\r\n  {\r\n    PROVIDE(__start_log_const_data = .);\r\n    KEEP(*(.log_const_data))\r\n    PROVIDE(__stop_log_const_data = .);\r\n  } > FLASH\r\n  \r\n  \r\n  .cli_command :\r\n  {\r\n    PROVIDE(__start_cli_command = .);\r\n    KEEP(*(.cli_command))\r\n    PROVIDE(__stop_cli_command = .);\r\n  } > FLASH\r\n\r\n  .sdh_stack_observers :\r\n  {\r\n    PROVIDE(__start_sdh_stack_observers = .);\r\n    KEEP(*(SORT(.sdh_stack_observers*)))\r\n    PROVIDE(__stop_sdh_stack_observers = .);\r\n  } > FLASH\r\n\r\n  .sdh_req_observers :\r\n  {\r\n    PROVIDE(__start_sdh_req_observers = .);\r\n    KEEP(*(SORT(.sdh_req_observers*)))\r\n    PROVIDE(__stop_sdh_req_observers = .);\r\n  } > FLASH\r\n\r\n  .sdh_state_observers :\r\n  {\r\n    PROVIDE(__start_sdh_state_observers = .);\r\n    KEEP(*(SORT(.sdh_state_observers*)))\r\n    PROVIDE(__stop_sdh_state_observers = .);\r\n  } > FLASH\r\n\r\n  .sdh_ant_observers :\r\n  {\r\n    PROVIDE(__start_sdh_ant_observers = .);\r\n    KEEP(*(SORT(.sdh_ant_observers*)))\r\n    PROVIDE(__stop_sdh_ant_observers = .);\r\n  } > FLASH\r\n\r\n  .sdh_ble_observers :\r\n  {\r\n    PROVIDE(__start_sdh_ble_observers = .);\r\n    KEEP(*(SORT(.sdh_ble_observers*)))\r\n    PROVIDE(__stop_sdh_ble_observers = .);\r\n  } > FLASH\r\n\r\n  .sdh_soc_observers :\r\n  {\r\n    PROVIDE(__start_sdh_soc_observers = .);\r\n    KEEP(*(SORT(.sdh_soc_observers*)))\r\n    PROVIDE(__stop_sdh_soc_observers = .);\r\n  } > FLASH\r\n} INSERT AFTER .text\r\n\r\nSECTIONS\r\n{\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nSECTIONS\r\n{\r\n  . = ALIGN(4);\r\n  .svc_data :\r\n  {\r\n    PROVIDE(__start_svc_data = .);\r\n    KEEP(*(.svc_data))\r\n    PROVIDE(__stop_svc_data = .);\r\n  } > RAM AT > FLASH\r\n  \r\n  .fs_data :\r\n  {\r\n    PROVIDE(__start_fs_data = .);\r\n    KEEP(*(.fs_data))\r\n    PROVIDE(__stop_fs_data = .);\r\n  } > RAM AT > FLASH\r\n   .log_dynamic_data :\r\n  {\r\n    PROVIDE(__start_log_dynamic_data = .);\r\n    KEEP(*(.log_dynamic_data))\r\n    PROVIDE(__stop_log_dynamic_data = .);\r\n  } > RAM AT > FLASH\r\n  .cli_sorted_cmd_ptrs :\r\n  {\r\n    PROVIDE(__start_cli_sorted_cmd_ptrs = .);\r\n    KEEP(*(.cli_sorted_cmd_ptrs))\r\n    PROVIDE(__stop_cli_sorted_cmd_ptrs = .);\r\n  } > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","old_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/nRF52\/CMSIS\/Release\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x23000, LENGTH = 0x5d000\r\n\tRAM (rwx) :  ORIGIN = 0x20002B00, LENGTH = 0xd500\r\n\t\/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n\t*  from application to bootloader when using buttonluss DFU OTA.\r\n\t*\/\r\n\tNOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n\t\/** Location of bootloader setting in flash. *\/\r\n\tBOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n}\r\n\r\n\r\nSECTIONS\r\n{\r\n\t\/* Place the bootloader settings page in flash. *\/\r\n\t.bootloaderSettings(NOLOAD) :\r\n\t{\r\n\r\n\t} > BOOTLOADER_SETTINGS\r\n\r\n\t\/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n\t.noinit(NOLOAD) :\r\n\t{\r\n\r\n\t} > NOINIT\r\n}\r\n\r\nSECTIONS\r\n{\r\n  .pwr_mgmt_data :\r\n  {\r\n    PROVIDE(__start_pwr_mgmt_data = .);\r\n    KEEP(*(SORT(.pwr_mgmt_data*)))\r\n    PROVIDE(__stop_pwr_mgmt_data = .);\r\n  } > FLASH\r\n  \r\n  .log_const_data :\r\n  {\r\n    PROVIDE(__start_log_const_data = .);\r\n    KEEP(*(.log_const_data))\r\n    PROVIDE(__stop_log_const_data = .);\r\n  } > FLASH\r\n  \r\n  \r\n  .cli_command :\r\n  {\r\n    PROVIDE(__start_cli_command = .);\r\n    KEEP(*(.cli_command))\r\n    PROVIDE(__stop_cli_command = .);\r\n  } > FLASH\r\n\r\n  .sdh_stack_observers :\r\n  {\r\n    PROVIDE(__start_sdh_stack_observers = .);\r\n    KEEP(*(SORT(.sdh_stack_observers*)))\r\n    PROVIDE(__stop_sdh_stack_observers = .);\r\n  } > FLASH\r\n\r\n  .sdh_req_observers :\r\n  {\r\n    PROVIDE(__start_sdh_req_observers = .);\r\n    KEEP(*(SORT(.sdh_req_observers*)))\r\n    PROVIDE(__stop_sdh_req_observers = .);\r\n  } > FLASH\r\n\r\n  .sdh_state_observers :\r\n  {\r\n    PROVIDE(__start_sdh_state_observers = .);\r\n    KEEP(*(SORT(.sdh_state_observers*)))\r\n    PROVIDE(__stop_sdh_state_observers = .);\r\n  } > FLASH\r\n\r\n  .sdh_ant_observers :\r\n  {\r\n    PROVIDE(__start_sdh_ant_observers = .);\r\n    KEEP(*(SORT(.sdh_ant_observers*)))\r\n    PROVIDE(__stop_sdh_ant_observers = .);\r\n  } > FLASH\r\n\r\n  .sdh_ble_observers :\r\n  {\r\n    PROVIDE(__start_sdh_ble_observers = .);\r\n    KEEP(*(SORT(.sdh_ble_observers*)))\r\n    PROVIDE(__stop_sdh_ble_observers = .);\r\n  } > FLASH\r\n\r\n  .sdh_soc_observers :\r\n  {\r\n    PROVIDE(__start_sdh_soc_observers = .);\r\n    KEEP(*(SORT(.sdh_soc_observers*)))\r\n    PROVIDE(__stop_sdh_soc_observers = .);\r\n  } > FLASH\r\n} INSERT AFTER .text\r\n\r\nSECTIONS\r\n{\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nSECTIONS\r\n{\r\n  . = ALIGN(4);\r\n  .svc_data :\r\n  {\r\n    PROVIDE(__start_svc_data = .);\r\n    KEEP(*(.svc_data))\r\n    PROVIDE(__stop_svc_data = .);\r\n  } > RAM AT > FLASH\r\n  \r\n  .fs_data :\r\n  {\r\n    PROVIDE(__start_fs_data = .);\r\n    KEEP(*(.fs_data))\r\n    PROVIDE(__stop_fs_data = .);\r\n  } > RAM AT > FLASH\r\n   .log_dynamic_data :\r\n  {\r\n    PROVIDE(__start_log_dynamic_data = .);\r\n    KEEP(*(.log_dynamic_data))\r\n    PROVIDE(__stop_log_dynamic_data = .);\r\n  } > RAM AT > FLASH\r\n  .cli_sorted_cmd_ptrs :\r\n  {\r\n    PROVIDE(__start_cli_sorted_cmd_ptrs = .);\r\n    KEEP(*(.cli_sorted_cmd_ptrs))\r\n    PROVIDE(__stop_cli_sorted_cmd_ptrs = .);\r\n  } > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"ed1a47372eb60f96545fe2fe363bda3404af51b3","subject":"Make sure programs goes in PML4T entries > 0","message":"Make sure programs goes in PML4T entries > 0\n","repos":"wichtounet\/thor-os,wichtounet\/thor-os","old_file":"programs\/linker.ld","new_file":"programs\/linker.ld","new_contents":"ENTRY(main)\n\nSECTIONS {\n\t. = 0x8000401000;\n\n\t.text BLOCK(4096) : ALIGN(4096)\n\t{\n\t\t*(.text)\n\t}\n\n\t. = 0x8000601000;\n\n\t.data BLOCK(4096) : ALIGN(4096)\n\t{\n\t\t*(.data)\n\t}\n\n\t.bss BLOCK(4096) : ALIGN(4096)\n\t{\n\t\t*(.bss)\n\t}\n}","old_contents":"ENTRY(main)\n\nSECTIONS {\n\t. = 0x400401000;\n\n\t.text BLOCK(4096) : ALIGN(4096)\n\t{\n\t\t*(.text)\n\t}\n\n\t. = 0x400601000;\n\n\t.data BLOCK(4096) : ALIGN(4096)\n\t{\n\t\t*(.data)\n\t}\n\n\t.bss BLOCK(4096) : ALIGN(4096)\n\t{\n\t\t*(.bss)\n\t}\n}","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"52909ed71568f74993fc4f74bef1bd7f3db03844","subject":"fix linker script so .bss doesn't smash the heap","message":"fix linker script so .bss doesn't smash the heap\n","repos":"Zirias\/clang-libdos,Zirias\/clang-libdos","old_file":"com.ld","new_file":"com.ld","new_contents":"OUTPUT_FORMAT(binary)\nSECTIONS\n{\n    . = 0x0100;\n    .text :\n    {\n\t*(.text);\n    }\n    .data :\n    {\n\t*(.data);\n\t*(.rodata);\n    }\n    .bss :\n    {\n\t*(.bss);\n\tFILL(0x00000000);\n    }\n    _heap = ALIGN(4);\n}\n\n","old_contents":"OUTPUT_FORMAT(binary)\nSECTIONS\n{\n    . = 0x0100;\n    .text :\n    {\n\t*(.text);\n    }\n    .data :\n    {\n\t*(.data);\n\t*(.bss);\n\t*(.rodata);\n    }\n    _heap = ALIGN(4);\n}\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"e9963e2db766ad272888656ac7cab67f89578629","subject":"Provide undefined handlers as Default_Handler alias","message":"Provide undefined handlers as Default_Handler alias\n","repos":"masilvabustos\/CabbageOS,masilvabustos\/CabbageOS","old_file":"hw\/stm32f100xx.ld","new_file":"hw\/stm32f100xx.ld","new_contents":"\nINPUT(hw.o)\n\nSECTIONS {\n\t\n\t__end_of_ram__ = ALIGN(ORIGIN(SRAM) + LENGTH(SRAM), 4) ;\n\n\t.cm3.isr_vector ORIGIN(FLASH) : {\n\t\tLONG(__end_of_ram__)\n\t\t\/* ARM Thumb interwork requires the LSB to be set.\t*\n\t\t * (Can ld do this automatically?) \t\t\t*\/ \t\t\t\n\t\tLONG(_start \t\t| 1)\n\t\t\/*PROVIDE(Default_Handler\t\t= _start);*\/\n\t\tPROVIDE(NMI_Handler \t\t= Default_Handler);\n\t\tPROVIDE(HardFault_Handler \t= Default_Handler);\n \t\tPROVIDE(MemManage_Handler \t= Default_Handler);\n\t\tPROVIDE(BusFault_Handler \t= Default_Handler);\n\t\tPROVIDE(SVC_Handler\t\t= Default_Handler);\n\t\tPROVIDE(PendSV_Handler \t\t= Default_Handler);\n\t\tPROVIDE(SysTick_Handler \t= Default_Handler);\n\t\tLONG(NMI_Handler \t| 1)\n\t\tLONG(HardFault_Handler \t| 1)\n\t\tLONG(MemManage_Handler \t| 1)\n\t\tLONG(BusFault_Handler \t| 1)\n\t\t\/*LONG(UsageFault_Handler | 1)*\/\n\t\t. = 0x2c ; \/* Reserved *\/\n\t\tLONG(SVC_Handler \t| 1)\n\t\t\/*LONG(DebugMon_Handler\t| 1)*\/\n\t\t. = 0x38 ; \/* Reserved *\/\n\t\tLONG(PendSV_Handler\t| 1)\n\t\tLONG(SysTick_Handler\t| 1)\n\t\t\n\t\t. = 0x40 ;\n\t\t* (.irqsr_vector)\n\t\t\n\t\t. = 0x134 ;\n\n\t} > FLASH\n\n\n\t.text : { \n\t\t. = ALIGN(4) ;\n\t\t* (.text) \n\t} > FLASH\n\t\n\t__data_lma__ = . ;\n\t.data : AT(__data_lma__) { \n\t\t__data_vma__ = . ;\n\t\t* (.data) \n\t} > SRAM\n\t__init_data_end = . ;\n\n\t.bss : {\n\t\t* (.bss)\n\t} > SRAM\n\n\t__brk = . ;\n\n\t.stm32f100xx.peripherals_registers : {\n\n\t\t\/* TODO: Add remaing registers *\/\n\t\t. = 0x10800 ;\n\t\tGPIOA_CRL \t= . + 0x00 ;\n\t\tGPIOA_CRH \t= . + 0x04 ;\n\t\tGPIOA_IDR \t= . + 0x08 ;\n\t\tGPIOA_ODR \t= . + 0x0C ;\n\t\tGPIOA_BSRR \t= . + 0x10 ;\n\t\tGPIOA_BRR\t= . + 0x14 ;\n\t\tGPIOA_LCKR\t= . + 0x18 ;\n\t\t\n\t\t. = 0x11000 ;\n\t\tGPIOC_CRL \t= . + 0x00 ;\n\t\tGPIOC_CRH \t= . + 0x04 ;\n\t\tGPIOC_IDR \t= . + 0x08 ;\n\t\tGPIOC_ODR \t= . + 0x0C ;\n\t\tGPIOC_BSRR \t= . + 0x10 ;\n\t\tGPIOC_BRR\t= . + 0x14 ;\n\t\tGPIOC_LCKR\t= . + 0x18 ;\n\n\t\t. = 0x21000 ;\n\t\tRCC_CR\t\t= . + 0x00 ;\n\t\tRCC_CFGR\t= . + 0x04 ;\n\t\tRCC_CIR\t\t= . + 0x08 ;\n\t\tRCC_APB2RSTR\t= . + 0x0C ;\n\t\tRCC_APB1RSTR \t= . + 0x10 ;\n\t\tRCC_AHBENR\t= . + 0x14 ;\n\t\tRCC_APB2ENR\t= . + 0x18 ;\n\t\tRCC_APB1ENR\t= . + 0x1C ;\n\t\tRCC_BDCR\t= . + 0x20 ;\n\t\tRCC_CSR\t\t= . + 0x24 ;\n\t\tRCC_CFGR2\t= . + 0x2C ;\n\n\n\t} > PERIPH\n\n\t.stm32f100xx.peripherals_bitband_alias 0x42000000 : {\n\n\t\t. \t\t= (RCC_APB2ENR \t- ORIGIN(PERIPH)) * 32 ;\n\t\tIOPCEN\t\t=  . +  4 * 4 ;\n\n\t} > PERIPH\t\n}\n\n","old_contents":"\nSECTIONS {\n\t\n\t__end_of_ram__ = ALIGN(ORIGIN(SRAM) + LENGTH(SRAM), 4) ;\n\n\t.cm3.isr_vector ORIGIN(FLASH) : {\n\t\tLONG(__end_of_ram__)\n\t\t\/* ARM Thumb interwork requires the LSB to be set.\t*\n\t\t * (Can ld do this automatically?) \t\t\t*\/ \t\t\t\n\t\tLONG(Reset \t\t| 1)\n\t\tLONG(NMI_Handler \t| 1)\n\t\tLONG(HardFault_Handler \t| 1)\n\t\tLONG(MemManage_Handler \t| 1)\n\t\tLONG(BusFault_Handler \t| 1)\n\t\tLONG(UsageFault_Handler | 1)\n\t\t. = 0x2c ; \/* Reserved *\/\n\t\tLONG(SVC_Handler \t| 1)\n\t\tLONG(DebugMon_Handler\t| 1)\n\t\t. = 0x38 ; \/* Reserved *\/\n\t\tLONG(PendSV_Handler\t| 1)\n\t\tLONG(SysTick_Handler\t| 1)\n\t\t\n\t\t. = 0x40 ;\n\t\t* (.isr_vector)\n\t\t\n\t\t. = 0x134 ;\n\n\t} > FLASH\n\n\n\t.text : { \n\t\t. = ALIGN(4) ;\n\t\t* (.text) \n\t} > FLASH\n\t\n\t__data_lma__ = . ;\n\t.data : AT(__data_lma__) { \n\t\t__data_vma__ = . ;\n\t\t* (.data) \n\t} > SRAM\n\t__init_data_end = . ;\n\n\t.bss : {\n\t\t* (.bss)\n\t} > SRAM\n\n\t__brk = . ;\n\n\t.stm32f100xx.peripherals_registers : {\n\n\t\t\/* TODO: Add remaing registers *\/\n\t\t. = 0x10800 ;\n\t\tGPIOA_CRL \t= . + 0x00 ;\n\t\tGPIOA_CRH \t= . + 0x04 ;\n\t\tGPIOA_IDR \t= . + 0x08 ;\n\t\tGPIOA_ODR \t= . + 0x0C ;\n\t\tGPIOA_BSRR \t= . + 0x10 ;\n\t\tGPIOA_BRR\t= . + 0x14 ;\n\t\tGPIOA_LCKR\t= . + 0x18 ;\n\t\t\n\t\t. = 0x11000 ;\n\t\tGPIOC_CRL \t= . + 0x00 ;\n\t\tGPIOC_CRH \t= . + 0x04 ;\n\t\tGPIOC_IDR \t= . + 0x08 ;\n\t\tGPIOC_ODR \t= . + 0x0C ;\n\t\tGPIOC_BSRR \t= . + 0x10 ;\n\t\tGPIOC_BRR\t= . + 0x14 ;\n\t\tGPIOC_LCKR\t= . + 0x18 ;\n\n\t\t. = 0x21000 ;\n\t\tRCC_CR\t\t= . + 0x00 ;\n\t\tRCC_CFGR\t= . + 0x04 ;\n\t\tRCC_CIR\t\t= . + 0x08 ;\n\t\tRCC_APB2RSTR\t= . + 0x0C ;\n\t\tRCC_APB1RSTR \t= . + 0x10 ;\n\t\tRCC_AHBENR\t= . + 0x14 ;\n\t\tRCC_APB2ENR\t= . + 0x18 ;\n\t\tRCC_APB1ENR\t= . + 0x1C ;\n\t\tRCC_BDCR\t= . + 0x20 ;\n\t\tRCC_CSR\t\t= . + 0x24 ;\n\t\tRCC_CFGR2\t= . + 0x2C ;\n\n\n\t} > PERIPH\n\n\t.stm32f100xx.peripherals_bitband_alias 0x42000000 : {\n\n\t\t. \t\t= (RCC_APB2ENR \t- ORIGIN(PERIPH)) * 32 ;\n\t\tIOPCEN\t\t=  . +  4 * 4 ;\n\n\t} > PERIPH\t\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c730c63f1d5711d0755d37af514a9cae18aa67df","subject":"Update K64F memory map for for larger static data","message":"Update K64F memory map for for larger static data\n\nThe KSDK2 update restricts static data to the first 64K of RAM.\nThis breaks some applications which require more than 64K of\nstatic data.  This patch moves the static data sections\n(bss and data) into the second ram region which is 192K.\n\nChanges taken from similar patches here:\nhttps:\/\/github.com\/ARMmbed\/target-kinetis-k64-gcc\/pull\/5\nhttps:\/\/github.com\/ARMmbed\/target-kinetis-k64-gcc\/pull\/6\n\nPrevious layout\n---------------\n0x1FFF0000 m_data   .interrupts_ram\n0x1FFF0400          data, bss\n0x1FFFFFFF          end of bss\n0x20000000 m_data_2 start of heap, end of stack\n0x2002ffff          end of heap, start of stack\n\nNew layout\n----------\n0x1FFF0000 m_data   .interrupts_ram\n0x1FFF0400          start of unused ram\n0x1FFFFFFF          end of unused ram\n0x20000000 m_data_2 data, bss\n0x200XXXXX          end of bss\n0x200XXXXX+1        start of heap, end of stack\n0x2002ffff          end of heap, start of stack\n","repos":"svastm\/mbed,mmorenobarm\/mbed-os,adustm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,j-greffe\/mbed-os,DanKupiniak\/mbed,pradeep-gr\/mbed-os5-onsemi,fahhem\/mbed-os,CalSol\/mbed,infinnovation\/mbed-os,CalSol\/mbed,bcostm\/mbed-os,svogl\/mbed-os,YarivCol\/mbed-os,bulislaw\/mbed-os,bcostm\/mbed-os,bcostm\/mbed-os,NXPmicro\/mbed,nvlsianpu\/mbed,kjbracey-arm\/mbed,andreaslarssonublox\/mbed,adamgreen\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,betzw\/mbed-os,kl-cruz\/mbed-os,tung7970\/mbed-os-1,nvlsianpu\/mbed,bikeNomad\/mbed,theotherjimmy\/mbed,NXPmicro\/mbed,jeremybrodt\/mbed,nvlsianpu\/mbed,ryankurte\/mbed-os,fanghuaqi\/mbed,catiedev\/mbed-os,mmorenobarm\/mbed-os,adamgreen\/mbed,bulislaw\/mbed-os,jeremybrodt\/mbed,maximmbed\/mbed,karsev\/mbed-os,adamgreen\/mbed,nRFMesh\/mbed-os,bikeNomad\/mbed,DanKupiniak\/mbed,monkiineko\/mbed-os,andcor02\/mbed-os,CalSol\/mbed,fahhem\/mbed-os,mikaleppanen\/mbed-os,RonEld\/mbed,tung7970\/mbed-os-1,pradeep-gr\/mbed-os5-onsemi,nRFMesh\/mbed-os,adamgreen\/mbed,adustm\/mbed,catiedev\/mbed-os,nRFMesh\/mbed-os,pradeep-gr\/mbed-os5-onsemi,bulislaw\/mbed-os,fanghuaqi\/mbed,tung7970\/mbed-os,kjbracey-arm\/mbed,karsev\/mbed-os,RonEld\/mbed,YarivCol\/mbed-os,bulislaw\/mbed-os,tung7970\/mbed-os,fvincenzo\/mbed-os,arostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,DanKupiniak\/mbed,mmorenobarm\/mbed-os,ARM-software\/mbed-beetle,bulislaw\/mbed-os,HeadsUpDisplayInc\/mbed,tung7970\/mbed-os,geky\/mbed,andreaslarssonublox\/mbed,bikeNomad\/mbed,DanKupiniak\/mbed,netzimme\/mbed-os,jeremybrodt\/mbed,geky\/mbed,c1728p9\/mbed-os,screamerbg\/mbed,infinnovation\/mbed-os,svastm\/mbed,mbedmicro\/mbed,bcostm\/mbed-os,tung7970\/mbed-os-1,andreaslarssonublox\/mbed,adustm\/mbed,rgrover\/mbed,jeremybrodt\/mbed,betzw\/mbed-os,mmorenobarm\/mbed-os,adamgreen\/mbed,CalSol\/mbed,fahhem\/mbed-os,Archcady\/mbed-os,bcostm\/mbed-os,netzimme\/mbed-os,ryankurte\/mbed-os,mmorenobarm\/mbed-os,netzimme\/mbed-os,RonEld\/mbed,betzw\/mbed-os,tung7970\/mbed-os-1,radhika-raghavendran\/mbed-os5.1-onsemi,maximmbed\/mbed,fanghuaqi\/mbed,c1728p9\/mbed-os,theotherjimmy\/mbed,cvtsi2sd\/mbed-os,kl-cruz\/mbed-os,kjbracey-arm\/mbed,ryankurte\/mbed-os,rgrover\/mbed,pradeep-gr\/mbed-os5-onsemi,screamerbg\/mbed,svastm\/mbed,karsev\/mbed-os,NXPmicro\/mbed,fvincenzo\/mbed-os,mbedmicro\/mbed,karsev\/mbed-os,tung7970\/mbed-os-1,screamerbg\/mbed,mikaleppanen\/mbed-os,netzimme\/mbed-os,kl-cruz\/mbed-os,andcor02\/mbed-os,Archcady\/mbed-os,bikeNomad\/mbed,nRFMesh\/mbed-os,svogl\/mbed-os,theotherjimmy\/mbed,fahhem\/mbed-os,andreaslarssonublox\/mbed,ARM-software\/mbed-beetle,fanghuaqi\/mbed,theotherjimmy\/mbed,fvincenzo\/mbed-os,svogl\/mbed-os,arostm\/mbed-os,andcor02\/mbed-os,nvlsianpu\/mbed,adustm\/mbed,infinnovation\/mbed-os,svastm\/mbed,infinnovation\/mbed-os,cvtsi2sd\/mbed-os,kl-cruz\/mbed-os,arostm\/mbed-os,netzimme\/mbed-os,cvtsi2sd\/mbed-os,arostm\/mbed-os,tung7970\/mbed-os,mmorenobarm\/mbed-os,c1728p9\/mbed-os,CalSol\/mbed,catiedev\/mbed-os,j-greffe\/mbed-os,svogl\/mbed-os,mbedmicro\/mbed,ARM-software\/mbed-beetle,bikeNomad\/mbed,NXPmicro\/mbed,fvincenzo\/mbed-os,monkiineko\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,kl-cruz\/mbed-os,cvtsi2sd\/mbed-os,mikaleppanen\/mbed-os,betzw\/mbed-os,fvincenzo\/mbed-os,geky\/mbed,mazimkhan\/mbed-os,fahhem\/mbed-os,c1728p9\/mbed-os,nRFMesh\/mbed-os,cvtsi2sd\/mbed-os,fahhem\/mbed-os,ryankurte\/mbed-os,maximmbed\/mbed,bulislaw\/mbed-os,karsev\/mbed-os,fanghuaqi\/mbed,YarivCol\/mbed-os,YarivCol\/mbed-os,YarivCol\/mbed-os,adamgreen\/mbed,rgrover\/mbed,svastm\/mbed,infinnovation\/mbed-os,mazimkhan\/mbed-os,monkiineko\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,CalSol\/mbed,adustm\/mbed,andcor02\/mbed-os,monkiineko\/mbed-os,catiedev\/mbed-os,mikaleppanen\/mbed-os,YarivCol\/mbed-os,andreaslarssonublox\/mbed,HeadsUpDisplayInc\/mbed,svogl\/mbed-os,screamerbg\/mbed,nvlsianpu\/mbed,karsev\/mbed-os,RonEld\/mbed,betzw\/mbed-os,ARM-software\/mbed-beetle,mazimkhan\/mbed-os,jeremybrodt\/mbed,j-greffe\/mbed-os,nRFMesh\/mbed-os,cvtsi2sd\/mbed-os,mikaleppanen\/mbed-os,infinnovation\/mbed-os,svogl\/mbed-os,ryankurte\/mbed-os,tung7970\/mbed-os,Archcady\/mbed-os,RonEld\/mbed,mikaleppanen\/mbed-os,mazimkhan\/mbed-os,RonEld\/mbed,kl-cruz\/mbed-os,monkiineko\/mbed-os,arostm\/mbed-os,NXPmicro\/mbed,Archcady\/mbed-os,j-greffe\/mbed-os,c1728p9\/mbed-os,theotherjimmy\/mbed,catiedev\/mbed-os,monkiineko\/mbed-os,theotherjimmy\/mbed,HeadsUpDisplayInc\/mbed,bcostm\/mbed-os,maximmbed\/mbed,maximmbed\/mbed,adustm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,pradeep-gr\/mbed-os5-onsemi,rgrover\/mbed,j-greffe\/mbed-os,Archcady\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,screamerbg\/mbed,catiedev\/mbed-os,geky\/mbed,arostm\/mbed-os,maximmbed\/mbed,Archcady\/mbed-os,andcor02\/mbed-os,mazimkhan\/mbed-os,netzimme\/mbed-os,j-greffe\/mbed-os,geky\/mbed,nvlsianpu\/mbed,mbedmicro\/mbed,screamerbg\/mbed,ryankurte\/mbed-os,betzw\/mbed-os,mazimkhan\/mbed-os,rgrover\/mbed,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,NXPmicro\/mbed","old_file":"hal\/targets\/cmsis\/TARGET_Freescale\/TARGET_K64F\/TOOLCHAIN_GCC_ARM\/MK64FN1M0xxx12.ld","new_file":"hal\/targets\/cmsis\/TARGET_Freescale\/TARGET_K64F\/TOOLCHAIN_GCC_ARM\/MK64FN1M0xxx12.ld","new_contents":"\/*\n** ###################################################################\n**     Processors:          MK64FN1M0VDC12\n**                          MK64FN1M0VLL12\n**                          MK64FN1M0VLQ12\n**                          MK64FN1M0VMD12\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014\n**     Version:             rev. 2.8, 2015-02-19\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n__ram_vector_table__ = 1;\n\n\/* Heap 1\/4 of ram and stack 1\/8 *\/\n__stack_size__ = 0x8000;\n__heap_size__ = 0x10000;\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data_2\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data_2\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n}\n\n","old_contents":"\/*\n** ###################################################################\n**     Processors:          MK64FN1M0VDC12\n**                          MK64FN1M0VLL12\n**                          MK64FN1M0VLQ12\n**                          MK64FN1M0VMD12\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014\n**     Version:             rev. 2.8, 2015-02-19\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n__ram_vector_table__ = 1;\n\n\/* Heap 1\/4 of ram and stack 1\/8 *\/\n__stack_size__ = 0x8000;\n__heap_size__ = 0x10000;\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4ae4d2f4d100a22e3c71b745c14d484028548de5","subject":"nios2: include .sbss in BSS section","message":"nios2: include .sbss in BSS section\n\nChange-Id: I1165d65ae8505ec79166acc8ebde86611ac50e08\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"fbsder\/zephyr,holtmann\/zephyr,bboozzoo\/zephyr,kraj\/zephyr,mbolivar\/zephyr,mirzak\/zephyr-os,zephyrproject-rtos\/zephyr,rsalveti\/zephyr,finikorg\/zephyr,runchip\/zephyr-cc3220,zephyrproject-rtos\/zephyr,kraj\/zephyr,fractalclone\/zephyr-riscv,fractalclone\/zephyr-riscv,runchip\/zephyr-cc3220,mirzak\/zephyr-os,GiulianoFranchetto\/zephyr,kraj\/zephyr,runchip\/zephyr-cc3220,Vudentz\/zephyr,pklazy\/zephyr,fractalclone\/zephyr-riscv,holtmann\/zephyr,sharronliu\/zephyr,ldts\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,holtmann\/zephyr,aceofall\/zephyr-iotos,aceofall\/zephyr-iotos,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,bigdinotech\/zephyr,runchip\/zephyr-cc3220,Vudentz\/zephyr,rsalveti\/zephyr,galak\/zephyr,mbolivar\/zephyr,pklazy\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,runchip\/zephyr-cc3200,galak\/zephyr,tidyjiang8\/zephyr-doc,bboozzoo\/zephyr,aceofall\/zephyr-iotos,erwango\/zephyr,bboozzoo\/zephyr,finikorg\/zephyr,sharronliu\/zephyr,tidyjiang8\/zephyr-doc,bigdinotech\/zephyr,fractalclone\/zephyr-riscv,sharronliu\/zephyr,pklazy\/zephyr,fbsder\/zephyr,Vudentz\/zephyr,ldts\/zephyr,mbolivar\/zephyr,GiulianoFranchetto\/zephyr,runchip\/zephyr-cc3200,galak\/zephyr,zephyriot\/zephyr,galak\/zephyr,erwango\/zephyr,ldts\/zephyr,pklazy\/zephyr,runchip\/zephyr-cc3200,runchip\/zephyr-cc3200,runchip\/zephyr-cc3220,erwango\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,aceofall\/zephyr-iotos,kraj\/zephyr,rsalveti\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,tidyjiang8\/zephyr-doc,galak\/zephyr,explora26\/zephyr,finikorg\/zephyr,zephyriot\/zephyr,bigdinotech\/zephyr,Vudentz\/zephyr,aceofall\/zephyr-iotos,holtmann\/zephyr,GiulianoFranchetto\/zephyr,zephyriot\/zephyr,rsalveti\/zephyr,ldts\/zephyr,runchip\/zephyr-cc3200,pklazy\/zephyr,sharronliu\/zephyr,rsalveti\/zephyr,bigdinotech\/zephyr,tidyjiang8\/zephyr-doc,fbsder\/zephyr,mbolivar\/zephyr,tidyjiang8\/zephyr-doc,erwango\/zephyr,mirzak\/zephyr-os,bigdinotech\/zephyr,mirzak\/zephyr-os,ldts\/zephyr,kraj\/zephyr,nashif\/zephyr,erwango\/zephyr,holtmann\/zephyr,nashif\/zephyr,punitvara\/zephyr,punitvara\/zephyr,punitvara\/zephyr,explora26\/zephyr,nashif\/zephyr,explora26\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,mbolivar\/zephyr,mirzak\/zephyr-os,fractalclone\/zephyr-riscv,fbsder\/zephyr,bboozzoo\/zephyr,fbsder\/zephyr,bboozzoo\/zephyr,punitvara\/zephyr,zephyriot\/zephyr,finikorg\/zephyr,sharronliu\/zephyr,explora26\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/nios2\/linker.ld","new_file":"include\/arch\/nios2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specfic linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n}\n#endif\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n#ifndef CONFIG_XIP\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#ifdef CONFIG_CPLUSPLUS\n    SECTION_PROLOGUE(_CTOR_SECTION_NAME, ,)\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __CTOR_LIST__ must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first elment of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT_BY_NAME(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(init_array, (OPTIONAL),)\n        {\n            . = ALIGN(4);\n            __init_array_start = .;\n            KEEP(*(SORT_BY_NAME(\".init_array*\")))\n            __init_array_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(devconfig, (OPTIONAL),)\n        {\n                __devconfig_start = .;\n                *(\".devconfig.*\")\n                KEEP(*(SORT_BY_NAME(\".devconfig*\")))\n                __devconfig_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_AT_PROLOGUE(_EXCEPTION_SECTION_NAME,,, __data_rom_start)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n        *(.data)\n        *(\".data.*\")\n\n\tKEEP(*(.isr_irq*))\n\n\t\/* sections for IRQ0-9 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9])))\n\n\t\/* sections for IRQ10-99 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9])))\n\n\t\/* sections for IRQ100-999 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(initlevel, (OPTIONAL),)\n        {\n                DEVICE_INIT_SECTIONS()\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_list, (OPTIONAL),)\n        {\n                _k_task_list_start = .;\n                        *(._k_task_list.public.*)\n                        *(._k_task_list.private.*)\n                _k_task_list_idle_start = .;\n                        *(._k_task_list.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n                _k_task_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_ptr, (OPTIONAL),)\n        {\n                _k_task_ptr_start = .;\n                        *(._k_task_ptr.public.*)\n                        *(._k_task_ptr.private.*)\n                        *(._k_task_ptr.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n                _k_task_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_pipe_ptr, (OPTIONAL),)\n        {\n                _k_pipe_ptr_start = .;\n                        *(._k_pipe_ptr.public.*)\n                        *(._k_pipe_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n                _k_pipe_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_mem_map_ptr, (OPTIONAL),)\n        {\n                _k_mem_map_ptr_start = .;\n                        *(._k_mem_map_ptr.public.*)\n                        *(._k_mem_map_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n                _k_mem_map_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_event_list, (OPTIONAL),)\n        {\n                _k_event_list_start = .;\n                        *(._k_event_list.event.*)\n                KEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n                _k_event_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    __data_ram_end = .;\n\n    SECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.bss)\n        *(.sbss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    __bss_num_words = (__bss_end - __bss_start) >> 2;\n\n    GROUP_END(RAMABLE_REGION)\n\n    }\n\n#if CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specfic linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n}\n#endif\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n#ifndef CONFIG_XIP\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#ifdef CONFIG_CPLUSPLUS\n    SECTION_PROLOGUE(_CTOR_SECTION_NAME, ,)\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __CTOR_LIST__ must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first elment of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT_BY_NAME(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(init_array, (OPTIONAL),)\n        {\n            . = ALIGN(4);\n            __init_array_start = .;\n            KEEP(*(SORT_BY_NAME(\".init_array*\")))\n            __init_array_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(devconfig, (OPTIONAL),)\n        {\n                __devconfig_start = .;\n                *(\".devconfig.*\")\n                KEEP(*(SORT_BY_NAME(\".devconfig*\")))\n                __devconfig_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_AT_PROLOGUE(_EXCEPTION_SECTION_NAME,,, __data_rom_start)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n        *(.data)\n        *(\".data.*\")\n\n\tKEEP(*(.isr_irq*))\n\n\t\/* sections for IRQ0-9 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9])))\n\n\t\/* sections for IRQ10-99 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9])))\n\n\t\/* sections for IRQ100-999 *\/\n\tKEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(initlevel, (OPTIONAL),)\n        {\n                DEVICE_INIT_SECTIONS()\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_list, (OPTIONAL),)\n        {\n                _k_task_list_start = .;\n                        *(._k_task_list.public.*)\n                        *(._k_task_list.private.*)\n                _k_task_list_idle_start = .;\n                        *(._k_task_list.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n                _k_task_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_ptr, (OPTIONAL),)\n        {\n                _k_task_ptr_start = .;\n                        *(._k_task_ptr.public.*)\n                        *(._k_task_ptr.private.*)\n                        *(._k_task_ptr.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n                _k_task_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_pipe_ptr, (OPTIONAL),)\n        {\n                _k_pipe_ptr_start = .;\n                        *(._k_pipe_ptr.public.*)\n                        *(._k_pipe_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n                _k_pipe_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_mem_map_ptr, (OPTIONAL),)\n        {\n                _k_mem_map_ptr_start = .;\n                        *(._k_mem_map_ptr.public.*)\n                        *(._k_mem_map_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n                _k_mem_map_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_event_list, (OPTIONAL),)\n        {\n                _k_event_list_start = .;\n                        *(._k_event_list.event.*)\n                KEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n                _k_event_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    __data_ram_end = .;\n\n    SECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    __bss_num_words = (__bss_end - __bss_start) >> 2;\n\n    GROUP_END(RAMABLE_REGION)\n\n    }\n\n#if CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"98e48828b105d2910310445f92d5b7079ccdadb3","subject":"Fix: Added ALIGN(8) for __etext section. This existed in mbed-6.3.0 version. I have not verified if it is truly needed, but it is better to err on the safe side.","message":"Fix: Added ALIGN(8) for __etext section. This existed in mbed-6.3.0 version. I have not verified if it is truly needed, but it is better to err on the safe side.\n","repos":"mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,mbedmicro\/mbed","old_file":"targets\/TARGET_STM\/TARGET_STM32G4\/TARGET_STM32G431xB\/TOOLCHAIN_GCC_ARM\/stm32g431xb.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32G4\/TARGET_STM32G431xB\/TOOLCHAIN_GCC_ARM\/stm32g431xb.ld","new_contents":"\/* Linker script to configure memory regions. *\/\n\/*\n * SPDX-License-Identifier: BSD-3-Clause\n ******************************************************************************\n * @attention\n *\n * Copyright (c) 2016-2020 STMicroelectronics.\n * All rights reserved.\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n *                        opensource.org\/licenses\/BSD-3-Clause\n *\n ******************************************************************************\n*\/\n\n#include \"..\/cmsis_nvic.h\"\n\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START  MBED_ROM_START\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE  MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)\n    \/* This value is normally defined by the tools\n       to 0x1000 for bare metal and 0x400 for RTOS *\/\n    #define MBED_CONF_TARGET_BOOT_STACK_SIZE  0x400\n#endif\n\n\/* Round up VECTORS_SIZE to 8 bytes *\/\n#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)\n\nMEMORY\n{\n    FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n    RAM (rwx)    : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    \/* Location counter can end up 2byte aligned with narrow Thumb code but\n       __etext is assumed by startup code to be the LMA of a section in RAM\n       which must be 8-byte aligned *\/\n    . = ALIGN(8);\n\n    __etext = .;\n    _sidata = .;\n    \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    \/* Uninitialized data section\n     * This region is not initialized by the C\/C++ library and can be used to\n     * store state across soft reboots. *\/\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        PROVIDE(end = .);\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\/*\n * SPDX-License-Identifier: BSD-3-Clause\n ******************************************************************************\n * @attention\n *\n * Copyright (c) 2016-2020 STMicroelectronics.\n * All rights reserved.\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n *                        opensource.org\/licenses\/BSD-3-Clause\n *\n ******************************************************************************\n*\/\n\n#include \"..\/cmsis_nvic.h\"\n\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START  MBED_ROM_START\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE  MBED_ROM_SIZE\n#endif\n\n#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)\n    \/* This value is normally defined by the tools\n       to 0x1000 for bare metal and 0x400 for RTOS *\/\n    #define MBED_CONF_TARGET_BOOT_STACK_SIZE  0x400\n#endif\n\n\/* Round up VECTORS_SIZE to 8 bytes *\/\n#define VECTORS_SIZE  (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)\n\nMEMORY\n{\n    FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n    RAM (rwx)    : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n    \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    \/* Uninitialized data section\n     * This region is not initialized by the C\/C++ library and can be used to\n     * store state across soft reboots. *\/\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n    \n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        PROVIDE(end = .);\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"83a617261a02bedeee47f7f58f8a02300219af38","subject":"cortexm_common\/ldscript: add _fw_rom_length variable","message":"cortexm_common\/ldscript: add _fw_rom_length variable\n\nIt will help testing if it is taken into account and for defining for outside\nafter.\n","repos":"OlegHahm\/RIOT,toonst\/RIOT,lazytech-org\/RIOT,smlng\/RIOT,toonst\/RIOT,rfuentess\/RIOT,rfuentess\/RIOT,toonst\/RIOT,basilfx\/RIOT,miri64\/RIOT,x3ro\/RIOT,smlng\/RIOT,lazytech-org\/RIOT,ant9000\/RIOT,basilfx\/RIOT,biboc\/RIOT,yogo1212\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,basilfx\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,yogo1212\/RIOT,rfuentess\/RIOT,OlegHahm\/RIOT,biboc\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,avmelnikoff\/RIOT,miri64\/RIOT,avmelnikoff\/RIOT,OTAkeys\/RIOT,mtausig\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,biboc\/RIOT,mfrey\/RIOT,avmelnikoff\/RIOT,RIOT-OS\/RIOT,BytesGalore\/RIOT,miri64\/RIOT,smlng\/RIOT,aeneby\/RIOT,gebart\/RIOT,josephnoir\/RIOT,OTAkeys\/RIOT,aeneby\/RIOT,kbumsik\/RIOT,mtausig\/RIOT,authmillenon\/RIOT,biboc\/RIOT,basilfx\/RIOT,A-Paul\/RIOT,OlegHahm\/RIOT,OTAkeys\/RIOT,biboc\/RIOT,jasonatran\/RIOT,lazytech-org\/RIOT,BytesGalore\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,x3ro\/RIOT,cladmi\/RIOT,kaspar030\/RIOT,cladmi\/RIOT,avmelnikoff\/RIOT,josephnoir\/RIOT,A-Paul\/RIOT,cladmi\/RIOT,josephnoir\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,kbumsik\/RIOT,RIOT-OS\/RIOT,A-Paul\/RIOT,mtausig\/RIOT,kYc0o\/RIOT,lazytech-org\/RIOT,mfrey\/RIOT,kYc0o\/RIOT,kbumsik\/RIOT,mtausig\/RIOT,toonst\/RIOT,ant9000\/RIOT,gebart\/RIOT,kYc0o\/RIOT,gebart\/RIOT,smlng\/RIOT,josephnoir\/RIOT,josephnoir\/RIOT,kYc0o\/RIOT,mfrey\/RIOT,A-Paul\/RIOT,mfrey\/RIOT,aeneby\/RIOT,aeneby\/RIOT,yogo1212\/RIOT,A-Paul\/RIOT,mtausig\/RIOT,yogo1212\/RIOT,smlng\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,lazytech-org\/RIOT,x3ro\/RIOT,x3ro\/RIOT,gebart\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,kbumsik\/RIOT,BytesGalore\/RIOT,BytesGalore\/RIOT,mfrey\/RIOT,kbumsik\/RIOT,basilfx\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,rfuentess\/RIOT,x3ro\/RIOT,authmillenon\/RIOT,cladmi\/RIOT,aeneby\/RIOT,gebart\/RIOT,miri64\/RIOT,rfuentess\/RIOT,BytesGalore\/RIOT,OlegHahm\/RIOT,toonst\/RIOT,OTAkeys\/RIOT,avmelnikoff\/RIOT,cladmi\/RIOT,kaspar030\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm.ld","new_contents":"\/*\n * Copyright (C) 2017 Inria\n *               2018 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_cortexm_common\n * @{\n *\n * @file\n * @brief           Memory definitions for the Cortex-M family\n *\n * @author          Francisco Acosta <francisco.acosta@inria.fr>\n *                  Ga\u00ebtan Harter <gaetan.harter@inria.fr>\n *\n * @}\n *\/\n\n_rom_offset = DEFINED( _rom_offset ) ? _rom_offset : 0x0;\n_fw_rom_length = _rom_length - _rom_offset;\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _fw_rom_length\n    ram (w!rx)  : ORIGIN = _ram_start_addr,               LENGTH = _ram_length\n}\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2017 Inria\n *               2018 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_cortexm_common\n * @{\n *\n * @file\n * @brief           Memory definitions for the Cortex-M family\n *\n * @author          Francisco Acosta <francisco.acosta@inria.fr>\n *                  Ga\u00ebtan Harter <gaetan.harter@inria.fr>\n *\n * @}\n *\/\n\n_rom_offset = DEFINED( _rom_offset ) ? _rom_offset : 0x0;\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _rom_length - _rom_offset\n    ram (w!rx)  : ORIGIN = _ram_start_addr,               LENGTH = _ram_length\n}\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"b6217227b7ed44c213a2b9b119564020a73ae9ef","subject":"ldscript: remove discarding of `ehframe` sections","message":"ldscript: remove discarding of `ehframe` sections\n\nGDB seems to not happy with this, gives error as,\ninternal-error: inline_frame_this_id: Assertion `!frame_id_eq (*this_id, outer_frame_id)' failed\n\nSigned-off-by: Mahavir Jain <934132006b6c9b08831ff9ee396b986615350165@gmail.com>\n","repos":"mahavirj\/tinyos,mahavirj\/tinyos","old_file":"ldscript\/linker.ld","new_file":"ldscript\/linker.ld","new_contents":"\/* the name of the entry label *\/\nENTRY(_start)\n\nSECTIONS {\n\t. = 0xC0100000;          \/* Kernel will execute from 3G + 1M *\/\n\n\t.text ALIGN (0x1000) : AT(0x100000)   \/* align at 4 KB *\/\n\t{\n\t\tcode = .;\n\t\t*(.text*)             \/* all text sections from all files *\/\n\t\t*(.rodata*)          \/* all read-only data sections from all files *\/\n\t}\n\n\t.data ALIGN (0x1000) :   \/* align at 4 KB *\/\n\t{\n\t\tdata = .;\n\t\t*(.data*)             \/* all data sections from all files *\/\n\t}\n\n\t.bss ALIGN (0x1000) :    \/* align at 4 KB *\/\n\t{\n\t\tbss = .;\n\t\t*(COMMON)            \/* all COMMON sections from all files *\/\n\t\t*(.bss*)              \/* all bss sections from all files *\/\n\t}\n\n\tend = .;\n\n}\n","old_contents":"\/* the name of the entry label *\/\nENTRY(_start)\n\nSECTIONS {\n\t. = 0xC0100000;          \/* Kernel will execute from 3G + 1M *\/\n\n\t.text ALIGN (0x1000) : AT(0x100000)   \/* align at 4 KB *\/\n\t{\n\t\tcode = .;\n\t\t*(.text*)             \/* all text sections from all files *\/\n\t\t*(.rodata*)          \/* all read-only data sections from all files *\/\n\t}\n\n\t.data ALIGN (0x1000) :   \/* align at 4 KB *\/\n\t{\n\t\tdata = .;\n\t\t*(.data*)             \/* all data sections from all files *\/\n\t}\n\n\t.bss ALIGN (0x1000) :    \/* align at 4 KB *\/\n\t{\n\t\tbss = .;\n\t\t*(COMMON)            \/* all COMMON sections from all files *\/\n\t\t*(.bss*)              \/* all bss sections from all files *\/\n\t}\n\n\tend = .;\n\n\t\/DISCARD\/ : {\n\t\t*(.eh_frame .note.GNU-stack)\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8385536c41603dc6ca0a9cbdb1ad35bc395e1d40","subject":"fix how start object is linked","message":"fix how start object is linked\n","repos":"bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr,bluerover\/6lbr,arurke\/contiki,arurke\/contiki,arurke\/contiki,arurke\/contiki,bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki","old_file":"cpu\/mc1322x\/mc1322x.lds","new_file":"cpu\/mc1322x\/mc1322x.lds","new_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(\"=\/usr\/local\/lib\"); SEARCH_DIR(\"=\/lib\"); SEARCH_DIR(\"=\/usr\/lib\");\nSECTIONS\n{\n\nSYS_STACK_SIZE = 1024;\nIRQ_STACK_SIZE = 256;\nFIQ_STACK_SIZE = 256;\nSVC_STACK_SIZE = 256;\nABT_STACK_SIZE = 16;\nUND_STACK_SIZE = 16;\nHEAP_SIZE = 1024;\n\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x00400000); . = 0x00400000;\n  .text           :\n  {\n    *(.start)\n    *(.irq)\t\t\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  } =0\n\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n      *(.rela.ctors)\n      *(.rela.dtors)\n      *(.rela.got)\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n    }\n  .rel.plt        : { *(.rel.plt) }\n  .rela.plt       : { *(.rela.plt) }\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0\n  .plt            : { *(.plt) }\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n\n\/*  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); *\/\n\n\t. = ALIGN(4);\n\t. = DATA_SEGMENT_ALIGN(4,4); \n\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n  .init_array     :\n  {\n     PROVIDE_HIDDEN (__init_array_start = .);\n     KEEP (*(SORT(.init_array.*)))\n     KEEP (*(.init_array))\n     PROVIDE_HIDDEN (__init_array_end = .);\n  }\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .jcr            : { KEEP (*(.jcr)) } \n  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }\n  .dynamic        : { *(.dynamic) } \n  . = DATA_SEGMENT_RELRO_END (0, .);  \n  .got            : { *(.got.plt) *(.got) }\n  .data           :\n  {\n    __data_start = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .data1          : { *(.data1) }\n  _edata = .; PROVIDE (edata = .);\n\n\t.stack : {\n\t\t__stack_start__ = . ;\n\n\t\t. += IRQ_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__irq_stack_top__ = . ;\n\n\t\t. += FIQ_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__fiq_stack_top__ = . ;\n\n\t\t. += SVC_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__svc_stack_top__ = . ;\n\n\t\t. += ABT_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__abt_stack_top__ = . ;\n\n\t\t. += UND_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__und_stack_top__ = . ;\n\n\t\t. += SYS_STACK_SIZE;\n\t\t. = ALIGN (4);\n\t\t__sys_stack_top__ = . ;\n\n\t\t__stack_end__ = .;\n\t}\n\n\n  __bss_start = .;\n  __bss_start__ = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.\n      FIXME: Why do we need it? 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{"commit":"78d31cff5c3d1fae34ef3ba92105b62636b7503c","subject":"Fix the flash length to use all of 256K part.","message":"Fix the flash length to use all of 256K part.\n","repos":"kjbracey-arm\/mbed,andcor02\/mbed-os,betzw\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,betzw\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,kjbracey-arm\/mbed,betzw\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,betzw\/mbed-os,kjbracey-arm\/mbed,betzw\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,andcor02\/mbed-os,betzw\/mbed-os,kjbracey-arm\/mbed","old_file":"targets\/TARGET_NORDIC\/TARGET_NRF5x\/TARGET_NRF51\/TARGET_MCU_NRF51822_UNIFIED\/device\/TOOLCHAIN_GCC_ARM\/TARGET_MCU_NRF51_16K_S130\/NRF51822.ld","new_file":"targets\/TARGET_NORDIC\/TARGET_NRF5x\/TARGET_NRF51\/TARGET_MCU_NRF51822_UNIFIED\/device\/TOOLCHAIN_GCC_ARM\/TARGET_MCU_NRF51_16K_S130\/NRF51822.ld","new_contents":"\/* Linker script to configure memory regions. *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x25000\n  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0x1108\n}\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.Vectors))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n        \n\t\t. = ALIGN(4);\n\t\tPROVIDE(__start_fs_data = .);\n\t\tKEEP(*(.fs_data))\n\t\tPROVIDE(__stop_fs_data = .);\n\n\t\t*(.jcr)\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n    .noinit :\n    {\n      PROVIDE(__start_noinit = .);\n      KEEP(*(.noinit))\n      PROVIDE(__stop_noinit = .);\n    } > RAM\n    \n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (NOLOAD):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t__HeapBase = .;\n\t\t*(.heap*)\n\t\t. = ORIGIN(RAM) + LENGTH(RAM) - Stack_Size;\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (NOLOAD):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x24000\n  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0x1108\n}\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.Vectors))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n        \n\t\t. = ALIGN(4);\n\t\tPROVIDE(__start_fs_data = .);\n\t\tKEEP(*(.fs_data))\n\t\tPROVIDE(__stop_fs_data = .);\n\n\t\t*(.jcr)\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n    .noinit :\n    {\n      PROVIDE(__start_noinit = .);\n      KEEP(*(.noinit))\n      PROVIDE(__stop_noinit = .);\n    } > RAM\n    \n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (NOLOAD):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t__HeapBase = .;\n\t\t*(.heap*)\n\t\t. = ORIGIN(RAM) + LENGTH(RAM) - Stack_Size;\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (NOLOAD):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1d59d3afed92543ef0a4d323f9cd0a43ce222b49","subject":"arch: arm: aarch64: linker: Discard plt and got sections","message":"arch: arm: aarch64: linker: Discard plt and got sections\n\nplt and got sections are used for dynamic linking which\nis not supported in Zephyr.\n\nReference: #11953\ncommit 3ba7097e7326 (\"linker: add orphan sections to linker script\")\n\nSigned-off-by: Abhishek Shah <0e3482be2ea27ea3934fa027fcc11e152466b559@broadcom.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n  \/* If building without MPU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM       (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n        KEEP(*(.vector_relay_table))\n        KEEP(*(\".vector_relay_table.*\"))\n        KEEP(*(.vector_relay_handler))\n        KEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(IRQ_VECTOR_TABLE))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    MPU_ALIGN(_image_rodata_end -_image_rom_start);\n    _image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        *(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n    } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n    #define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#else\n    #define NSC_ALIGN . = ALIGN(4)\n#endif\n\n    #define NSC_ALIGN_END . = ALIGN(4)\n\n    SECTION_PROLOGUE(.gnu.sgstubs,,)\n    {\n        NSC_ALIGN;\n        __sg_start = .;\n        \/* No input section necessary, since the Secure Entry Veneers are\n           automatically placed after the .gnu.sgstubs output section. *\/\n    } GROUP_LINK_IN(ROMABLE_REGION)\n    __sg_end = .;\n    __sg_size = __sg_end - __sg_start;\n    NSC_ALIGN_END;\n    __nsc_size = . - __sg_start;\n\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n  \/* If building without MPU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM       (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n        KEEP(*(.vector_relay_table))\n        KEEP(*(\".vector_relay_table.*\"))\n        KEEP(*(.vector_relay_handler))\n        KEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(IRQ_VECTOR_TABLE))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    MPU_ALIGN(_image_rodata_end -_image_rom_start);\n    _image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        *(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n    } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n    #define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#else\n    #define NSC_ALIGN . = ALIGN(4)\n#endif\n\n    #define NSC_ALIGN_END . = ALIGN(4)\n\n    SECTION_PROLOGUE(.gnu.sgstubs,,)\n    {\n        NSC_ALIGN;\n        __sg_start = .;\n        \/* No input section necessary, since the Secure Entry Veneers are\n           automatically placed after the .gnu.sgstubs output section. *\/\n    } GROUP_LINK_IN(ROMABLE_REGION)\n    __sg_end = .;\n    __sg_size = __sg_end - __sg_start;\n    NSC_ALIGN_END;\n    __nsc_size = . - __sg_start;\n\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a51f378ecc75e319bda4280673dfb2d031d1e846","subject":"bugfix: it causes exception that wifi interrupt happens when read\/write flash, if pp_post() is on icache.","message":"bugfix: it causes exception that wifi interrupt happens when read\/write flash, if pp_post() is on icache.\n","repos":"empoweredhomes\/esp-idf,armada-ai\/esp-idf,empoweredhomes\/esp-idf,ajs124\/esp-idf,MIhanguangyi\/esp-idf,Hermiedapwdrman\/esp-idf,tidyjiang8\/esp-idf-zh,tidyjiang8\/esp-idf-zh,MIhanguangyi\/esp-idf,armada-ai\/esp-idf,nineisk\/esp-idf,mashaoze\/esp-idf,nineisk\/esp-idf,Hermiedapwdrman\/esp-idf,wmpluto\/esp-idf,hwmaier\/esp-idf,tidyjiang8\/esp-idf-zh,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,jaracil\/esp-idf,shukyisme\/esp-idf-kwik,dantonets\/Pingzee-ESP32,hwmaier\/esp-idf,wmpluto\/esp-idf,empoweredhomes\/esp-idf,www220\/esp-idf,ajs124\/esp-idf,espressif\/esp-idf,armada-ai\/esp-idf,dantonets\/Pingzee-ESP32,jaracil\/esp-idf,MIhanguangyi\/esp-idf,espressif\/esp-idf,wmpluto\/esp-idf,Hermiedapwdrman\/esp-idf,nineisk\/esp-idf,mashaoze\/esp-idf,MIhanguangyi\/esp-idf,Hermiedapwdrman\/esp-idf,jaracil\/esp-idf,mashaoze\/esp-idf,MIhanguangyi\/esp-idf,dschaefer\/esp-idf,dschaefer\/esp-idf,shukyisme\/esp-idf-kwik,tidyjiang8\/esp-idf-zh,www220\/esp-idf,dschaefer\/esp-idf,dantonets\/Pingzee-ESP32,Hermiedapwdrman\/esp-idf,www220\/esp-idf,shukyisme\/esp-idf-kwik,espressif\/esp-idf,armada-ai\/esp-idf,nineisk\/esp-idf,jaracil\/esp-idf,empoweredhomes\/esp-idf,dschaefer\/esp-idf,hwmaier\/esp-idf,mashaoze\/esp-idf,dschaefer\/esp-idf,wmpluto\/esp-idf,www220\/esp-idf,shukyisme\/esp-idf-kwik,dantonets\/Pingzee-ESP32,www220\/esp-idf,tidyjiang8\/esp-idf-zh,hwmaier\/esp-idf,empoweredhomes\/esp-idf,espressif\/esp-idf,ajs124\/esp-idf,ajs124\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *librtc_clk.a:(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libcore.a:ets_timer.o(.literal .text .literal.* .text.*)\n    *libnet80211.a:ieee80211_misc.o(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libcoexist.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *librtc_clk.a:(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libcore.a:ets_timer.o(.literal .text .literal.* .text.*)\n    *libnet80211.a:ieee80211_misc.o(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libcoexist.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"fa84881098c3899e55b588a0ae74bc116fad2cb9","subject":"Update LPC11U68.ld","message":"Update LPC11U68.ld","repos":"Archcady\/mbed-os,jamesadevine\/mbed,ARM-software\/mbed-beetle,tung7970\/mbed-os-1,larks\/mbed,mmorenobarm\/mbed-os,ban4jp\/mbed,Timmmm\/mbed,adustm\/mbed,jpbrucker\/mbed,HeadsUpDisplayInc\/mbed,j-greffe\/mbed-os,rosterloh\/mbed,catiedev\/mbed-os,Archcady\/mbed-os,catiedev\/mbed-os,jrjang\/mbed,adamgreen\/mbed,NXPmicro\/mbed,Sweet-Peas\/mbed,mnlipp\/mbed,infinnovation\/mbed-os,dbestm\/mbed,getopenmono\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,Shengliang\/mbed,kpurusho\/mbed,hwfwgrp\/mbed,maximmbed\/mbed,larks\/mbed,svastm\/mbed,betzw\/mbed-os,bcostm\/mbed-os,Willem23\/mbed,kpurusho\/mbed,Marcomissyou\/mbed,wodji\/mbed,netzimme\/mbed-os,DanKupiniak\/mbed,mikaleppanen\/mbed-os,bentwire\/mbed,YarivCol\/mbed-os,larks\/mbed,JasonHow44\/mbed,al177\/mbed,EmuxEvans\/mbed,masaohamanaka\/mbed,pradeep-gr\/mbed-os5-onsemi,FranklyDev\/mbed,bcostm\/mbed-os,andcor02\/mbed-os,Sweet-Peas\/mbed,adamgreen\/mbed,Tiryoh\/mbed,kpurusho\/mbed,rosterloh\/mbed,kpurusho\/mbed,bentwire\/mbed,alertby\/mbed,svastm\/mbed,nvlsianpu\/mbed,struempelix\/mbed,GustavWi\/mbed,jrjang\/mbed,infinnovation\/mbed-os,pedromes\/mbed,geky\/mbed,fpiot\/mbed-ats,sam-geek\/mbed,mnlipp\/mbed,nRFMesh\/mbed-os,arostm\/mbed-os,fahhem\/mbed-os,arostm\/mbed-os,xcrespo\/mbed,pradeep-gr\/mbed-os5-onsemi,al177\/mbed,larks\/mbed,logost\/mbed,Shengliang\/mbed,alertby\/mbed,Marcomissyou\/mbed,getopenmono\/mbed,FranklyDev\/mbed,cvtsi2sd\/mbed-os,tung7970\/mbed-os,c1728p9\/mbed-os,pradeep-gr\/mbed-os5-onsemi,bcostm\/mbed-os,screamerbg\/mbed,fvincenzo\/mbed-os,rgrover\/mbed,c1728p9\/mbed-os,hwfwgrp\/mbed,nvlsianpu\/mbed,Timmmm\/mbed,0xc0170\/mbed-drivers,kjbracey-arm\/mbed,mnlipp\/mbed,Shengliang\/mbed,nRFMesh\/mbed-os,naves-thiago\/mbed-midi,HeadsUpDisplayInc\/mbed,mikaleppanen\/mbed-os,ryankurte\/mbed-os,fvincenzo\/mbed-os,fvincenzo\/mbed-os,K4zuki\/mbed,kl-cruz\/mbed-os,sg-\/mbed-drivers,naves-thiago\/mbed-midi,jferreir\/mbed,bremoran\/mbed-drivers,bulislaw\/mbed-os,jrjang\/mbed,jeremybrodt\/mbed,devanlai\/mbed,Willem23\/mbed,j-greffe\/mbed-os,Timmmm\/mbed,dbestm\/mbed,alertby\/mbed,adustm\/mbed,Tiryoh\/mbed,JasonHow44\/mbed,wodji\/mbed,Sweet-Peas\/mbed,Archcady\/mbed-os,mmorenobarm\/mbed-os,ban4jp\/mbed,tung7970\/mbed-os-1,svastm\/mbed,nvlsianpu\/mbed,RonEld\/mbed,sam-geek\/mbed,andreaslarssonublox\/mbed,struempelix\/mbed,kjbracey-arm\/mbed,CalSol\/mbed,pi19404\/mbed,nabilbendafi\/mbed,xcrespo\/mbed,dbestm\/mbed,jferreir\/mbed,adustm\/mbed,netzimme\/mbed-os,jferreir\/mbed,maximmbed\/mbed,rosterloh\/mbed,brstew\/MBED-BUILD,kpurusho\/mbed,jamesadevine\/mbed,JasonHow44\/mbed,betzw\/mbed-os,YarivCol\/mbed-os,devanlai\/mbed,theotherjimmy\/mbed,jeremybrodt\/mbed,jpbrucker\/mbed,Willem23\/mbed,screamerbg\/mbed,adamgreen\/mbed,andcor02\/mbed-os,ryankurte\/mbed-os,pi19404\/mbed,betzw\/mbed-os,c1728p9\/mbed-os,0xc0170\/mbed-drivers,adamgreen\/mbed,bcostm\/mbed-os,al177\/mbed,monkiineko\/mbed-os,HeadsUpDisplayInc\/mbed,NitinBhaskar\/mbed,jrjang\/mbed,al177\/mbed,pi19404\/mbed,bentwire\/mbed,Archcady\/mbed-os,mmorenobarm\/mbed-os,autopulated\/mbed,ban4jp\/mbed,bcostm\/mbed-os,DanKupiniak\/mbed,CalSol\/mbed,bcostm\/mbed-os,getopenmono\/mbed,mnlipp\/mbed,jamesadevine\/mbed,nabilbendafi\/mbed,NitinBhaskar\/mbed,svastm\/mbed,NordicSemiconductor\/mbed,Archcady\/mbed-os,catiedev\/mbed-os,andcor02\/mbed-os,hwfwgrp\/mbed,ryankurte\/mbed-os,getopenmono\/mbed,EmuxEvans\/mbed,pbrook\/mbed,al177\/mbed,nvlsianpu\/mbed,maximmbed\/mbed,andreaslarssonublox\/mbed,devanlai\/mbed,masaohamanaka\/mbed,Timmmm\/mbed,hwfwgrp\/mbed,HeadsUpDisplayInc\/mbed,mnlipp\/mbed,fanghuaqi\/mbed,logost\/mbed,adustm\/mbed,tung7970\/mbed-os-1,autopulated\/mbed,jrjang\/mbed,EmuxEvans\/mbed,fahhem\/mbed-os,andreaslarssonublox\/mbed,EmuxEvans\/mbed,mazimkhan\/mbed-os,c1728p9\/mbed-os,NXPmicro\/mbed,sam-geek\/mbed,bulislaw\/mbed-os,j-greffe\/mbed-os,rosterloh\/mbed,masaohamanaka\/mbed,tung7970\/mbed-os,GustavWi\/mbed,mmorenobarm\/mbed-os,CalSol\/mbed,masaohamanaka\/mbed,arostm\/mbed-os,hwfwgrp\/mbed,pedromes\/mbed,maximmbed\/mbed,getopenmono\/mbed,andreaslarssonublox\/mbed,nvlsianpu\/mbed,betzw\/mbed-os,GustavWi\/mbed,alertby\/mbed,ryankurte\/mbed-os,ARM-software\/mbed-beetle,HeadsUpDisplayInc\/mbed,bulislaw\/mbed-os,RonEld\/mbed,mikaleppanen\/mbed-os,larks\/mbed,theotherjimmy\/mbed,dbestm\/mbed,jamesadevine\/mbed,kl-cruz\/mbed-os,pbrook\/mbed,fpiot\/mbed-ats,Marcomissyou\/mbed,rgrover\/mbed,cvtsi2sd\/mbed-os,wodji\/mbed,mbedmicro\/mbed,fahhem\/mbed-os,fahhem\/mbed-os,nvlsianpu\/mbed,j-greffe\/mbed-os,arostm\/mbed-os,pedromes\/mbed,bulislaw\/mbed-os,jferreir\/mbed,andcor02\/mbed-os,K4zuki\/mbed,CalSol\/mbed,Archcady\/mbed-os,xcrespo\/mbed,mbedmicro\/mbed,masaohamanaka\/mbed,logost\/mbed,fanghuaqi\/mbed,logost\/mbed,iriark01\/mbed-drivers,nRFMesh\/mbed-os,NordicSemiconductor\/mbed,jamesadevine\/mbed,svogl\/mbed-os,nabilbendafi\/mbed,sam-geek\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,rosterloh\/mbed,pedromes\/mbed,autopulated\/mbed,devanlai\/mbed,jpbrucker\/mbed,Tiryoh\/mbed,logost\/mbed,Tiryoh\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,mikaleppanen\/mbed-os,catiedev\/mbed-os,struempelix\/mbed,alertby\/mbed,netzimme\/mbed-os,EmuxEvans\/mbed,svogl\/mbed-os,pi19404\/mbed,wodji\/mbed,naves-thiago\/mbed-midi,andcor02\/mbed-os,NitinBhaskar\/mbed,jeremybrodt\/mbed,JasonHow44\/mbed,Timmmm\/mbed,nabilbendafi\/mbed,naves-thiago\/mbed-midi,jrjang\/mbed,hwfwgrp\/mbed,fanghuaqi\/mbed,fvincenzo\/mbed-os,RonEld\/mbed,nabilbendafi\/mbed,NitinBhaskar\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,monkiineko\/mbed-os,bulislaw\/mbed-os,adamgreen\/mbed,bikeNomad\/mbed,ban4jp\/mbed,bentwire\/mbed,nRFMesh\/mbed-os,Timmmm\/mbed,karsev\/mbed-os,Sweet-Peas\/mbed,devanlai\/mbed,YarivCol\/mbed-os,cvtsi2sd\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,CalSol\/mbed,sg-\/mbed-drivers,kjbracey-arm\/mbed,Shengliang\/mbed,xcrespo\/mbed,karsev\/mbed-os,adustm\/mbed,fpiot\/mbed-ats,DanKupiniak\/mbed,dbestm\/mbed,Sweet-Peas\/mbed,infinnovation\/mbed-os,maximmbed\/mbed,Shengliang\/mbed,fpiot\/mbed-ats,cvtsi2sd\/mbed-os,autopulated\/mbed,infinnovation\/mbed-os,pradeep-gr\/mbed-os5-onsemi,K4zuki\/mbed,Marcomissyou\/mbed,pi19404\/mbed,tung7970\/mbed-os-1,bikeNomad\/mbed,Tiryoh\/mbed,pedromes\/mbed,pradeep-gr\/mbed-os5-onsemi,JasonHow44\/mbed,karsev\/mbed-os,jferreir\/mbed,jferreir\/mbed,jeremybrodt\/mbed,fanghuaqi\/mbed,EmuxEvans\/mbed,screamerbg\/mbed,K4zuki\/mbed,autopulated\/mbed,screamerbg\/mbed,naves-thiago\/mbed-midi,svogl\/mbed-os,mazimkhan\/mbed-os,rgrover\/mbed,bikeNomad\/mbed,kl-cruz\/mbed-os,K4zuki\/mbed,netzimme\/mbed-os,larks\/mbed,Marcomissyou\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,pbrook\/mbed,mnlipp\/mbed,pbrook\/mbed,HeadsUpDisplayInc\/mbed,adamgreen\/mbed,Willem23\/mbed,dbestm\/mbed,bremoran\/mbed-drivers,naves-thiago\/mbed-midi,infinnovation\/mbed-os,alertby\/mbed,catiedev\/mbed-os,brstew\/MBED-BUILD,mikaleppanen\/mbed-os,NordicSemiconductor\/mbed,jpbrucker\/mbed,jpbrucker\/mbed,betzw\/mbed-os,RonEld\/mbed,geky\/mbed,NXPmicro\/mbed,bikeNomad\/mbed,FranklyDev\/mbed,ARM-software\/mbed-beetle,svogl\/mbed-os,screamerbg\/mbed,geky\/mbed,NordicSemiconductor\/mbed,kl-cruz\/mbed-os,mazimkhan\/mbed-os,GustavWi\/mbed,brstew\/MBED-BUILD,infinnovation\/mbed-os,FranklyDev\/mbed,svogl\/mbed-os,mikaleppanen\/mbed-os,kl-cruz\/mbed-os,YarivCol\/mbed-os,Shengliang\/mbed,c1728p9\/mbed-os,mazimkhan\/mbed-os,NitinBhaskar\/mbed,pedromes\/mbed,bulislaw\/mbed-os,tung7970\/mbed-os-1,monkiineko\/mbed-os,theotherjimmy\/mbed,geky\/mbed,bentwire\/mbed,pradeep-gr\/mbed-os5-onsemi,jpbrucker\/mbed,theotherjimmy\/mbed,RonEld\/mbed,pbrook\/mbed,NXPmicro\/mbed,mmorenobarm\/mbed-os,fahhem\/mbed-os,FranklyDev\/mbed,fanghuaqi\/mbed,theotherjimmy\/mbed,struempelix\/mbed,xcrespo\/mbed,tung7970\/mbed-os,pbrook\/mbed,andreaslarssonublox\/mbed,cvtsi2sd\/mbed-os,karsev\/mbed-os,wodji\/mbed,DanKupiniak\/mbed,CalSol\/mbed,fpiot\/mbed-ats,GustavWi\/mbed,svogl\/mbed-os,adustm\/mbed,j-greffe\/mbed-os,jamesadevine\/mbed,maximmbed\/mbed,ban4jp\/mbed,NXPmicro\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,brstew\/MBED-BUILD,karsev\/mbed-os,fahhem\/mbed-os,jeremybrodt\/mbed,arostm\/mbed-os,tung7970\/mbed-os,ryankurte\/mbed-os,mazimkhan\/mbed-os,nRFMesh\/mbed-os,cvtsi2sd\/mbed-os,kl-cruz\/mbed-os,netzimme\/mbed-os,sam-geek\/mbed,monkiineko\/mbed-os,brstew\/MBED-BUILD,rgrover\/mbed,brstew\/MBED-BUILD,mbedmicro\/mbed,j-greffe\/mbed-os,struempelix\/mbed,struempelix\/mbed,Willem23\/mbed,nRFMesh\/mbed-os,mazimkhan\/mbed-os,xcrespo\/mbed,netzimme\/mbed-os,rgrover\/mbed,mmorenobarm\/mbed-os,kpurusho\/mbed,betzw\/mbed-os,catiedev\/mbed-os,masaohamanaka\/mbed,Marcomissyou\/mbed,YarivCol\/mbed-os,NXPmicro\/mbed,autopulated\/mbed,pi19404\/mbed,YarivCol\/mbed-os,devanlai\/mbed,K4zuki\/mbed,screamerbg\/mbed,fvincenzo\/mbed-os,monkiineko\/mbed-os,bikeNomad\/mbed,wodji\/mbed,JasonHow44\/mbed,ban4jp\/mbed,Tiryoh\/mbed,Sweet-Peas\/mbed,bentwire\/mbed,svastm\/mbed,nabilbendafi\/mbed,tung7970\/mbed-os,theotherjimmy\/mbed,monkiineko\/mbed-os,iriark01\/mbed-drivers,al177\/mbed,ryankurte\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os,RonEld\/mbed,karsev\/mbed-os,rosterloh\/mbed,fpiot\/mbed-ats,mbedmicro\/mbed,geky\/mbed,ARM-software\/mbed-beetle,logost\/mbed,arostm\/mbed-os,getopenmono\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC11U6X\/TOOLCHAIN_GCC_ARM\/TARGET_LPC11U68\/LPC11U68.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC11U6X\/TOOLCHAIN_GCC_ARM\/TARGET_LPC11U68\/LPC11U68.ld","new_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC11U68\n * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Sat Jun 14 15:26:54 JST 2014\n *\/\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 \/* 32K bytes *\/\n  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 \/* 2K bytes *\/\n  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_32 = 0x10000000 + 0x8000;\n  __top_Ram1_2 = 0x20000000 + 0x800;\n  __top_Ram2USB_2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        __vectors_start__ = ABSOLUTE(.) ;\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \/* possible MTB section for Ram1_2 *\/\n    .mtb_buffer_RAM2 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM2*))\n        KEEP(*(.mtb.$RAM1_2*))\n    } > Ram1_2 \n    \n    \/* DATA section for Ram1_2 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_2)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 AT>MFlash256\n    \/* possible MTB section for Ram2USB_2 *\/\n    .mtb_buffer_RAM3 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM3*))\n        KEEP(*(.mtb.$RAM2USB_2*))\n    } > Ram2USB_2 \n    \n    \/* DATA section for Ram2USB_2 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2USB_2)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/\n    \n    \/* Default MTB section *\/\n    .mtb_buffer_default (NOLOAD) :\n    {\n       KEEP(*(.mtb*))\n    } > Ram0_32 \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_32\n\n\t\n\t\/* Main DATA section (Ram0_32) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_32 AT>MFlash256\n\n    \/* BSS section for Ram1_2 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2\n    \/* BSS section for Ram2USB_2 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_32\n        \n    \/* NOINIT section for Ram1_2 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 \n    \/* NOINIT section for Ram2USB_2 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_32 - 0);\n}\n","old_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC11U68\n * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Sat Jun 14 15:26:54 JST 2014\n *\/\n\n\/*GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a crti.o crtn.o crtbegin.o crtend.o)*\/\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 \/* 32K bytes *\/\n  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 \/* 2K bytes *\/\n  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_32 = 0x10000000 + 0x8000;\n  __top_Ram1_2 = 0x20000000 + 0x800;\n  __top_Ram2USB_2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        __vectors_start__ = ABSOLUTE(.) ;\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \/* possible MTB section for Ram1_2 *\/\n    .mtb_buffer_RAM2 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM2*))\n        KEEP(*(.mtb.$RAM1_2*))\n    } > Ram1_2 \n    \n    \/* DATA section for Ram1_2 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_2)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 AT>MFlash256\n    \/* possible MTB section for Ram2USB_2 *\/\n    .mtb_buffer_RAM3 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM3*))\n        KEEP(*(.mtb.$RAM2USB_2*))\n    } > Ram2USB_2 \n    \n    \/* DATA section for Ram2USB_2 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2USB_2)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/\n    \n    \/* Default MTB section *\/\n    .mtb_buffer_default (NOLOAD) :\n    {\n       KEEP(*(.mtb*))\n    } > Ram0_32 \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_32\n\n\t\n\t\/* Main DATA section (Ram0_32) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_32 AT>MFlash256\n\n    \/* BSS section for Ram1_2 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2\n    \/* BSS section for Ram2USB_2 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_32\n        \n    \/* NOINIT section for Ram1_2 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 \n    \/* NOINIT section for Ram2USB_2 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_32 - 0);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cf28ccfb06f80d3e219ebcae3e7586fbe8c41e34","subject":"Fixed linker script to allow growing stack+heap.","message":"Fixed linker script to allow growing stack+heap.\n","repos":"PaoloP74\/Arduino,piersoft\/esp8266-Arduino,jomolinare\/Arduino,PeterVH\/Arduino,jomolinare\/Arduino,ccoenen\/Arduino,rcook\/DesignLab,koltegirish\/Arduino,tbowmo\/Arduino,eduardocasarin\/Arduino,andrealmeidadomingues\/Arduino,Chris--A\/Arduino,tannewt\/Arduino,karlitxo\/Arduino,damellis\/Arduino,xxxajk\/Arduino-1,Cloudino\/Arduino,snargledorf\/Arduino,fungxu\/Arduino,henningpohl\/Arduino,bsmr-arduino\/Arduino,bsmr-arduino\/Arduino,leftbrainstrain\/Arduino-ESP8266,kidswong999\/Arduino,eggfly\/arduino,pdNor\/Arduino,danielchalef\/Arduino,adamkh\/Arduino,jaimemaretoli\/Arduino,Gourav2906\/Arduino,Alfredynho\/AgroSis,zenmanenergy\/Arduino,toddtreece\/esp8266-Arduino,adafruit\/ESP8266-Arduino,ashwin713\/Arduino,ForestNymph\/Arduino_sources,plinioseniore\/Arduino,Cloudino\/Arduino,eggfly\/arduino,SmartArduino\/Arduino-1,ektor5\/Arduino,shiitakeo\/Arduino,tannewt\/Arduino,ForestNymph\/Arduino_sources,stevemarple\/Arduino-org,tskurauskas\/Arduino,ikbelkirasan\/Arduino,piersoft\/esp8266-Arduino,fungxu\/Arduino,scdls\/Arduino,ashwin713\/Arduino,radut\/Arduino,paulmand3l\/Arduino,leftbrainstrain\/Arduino-ESP8266,pdNor\/Arduino,tomkrus007\/Arduino,bsmr-arduino\/Arduino,bsmr-arduino\/Arduino,acosinwork\/Arduino,cscenter\/Arduino,zenmanenergy\/Arduino,ntruchsess\/Arduino-1,jabezGit\/Arduino,adafruit\/ESP8266-Arduino,jabezGit\/Arduino,eddyst\/Arduino-SourceCode,sanyaade-iot\/Arduino-1,koltegirish\/Arduino,chaveiro\/Arduino,spapadim\/Arduino,zaiexx\/Arduino,gberl001\/Arduino,jamesrob4\/Arduino,andyvand\/Arduino-1,arunkuttiyara\/Arduino,mc-hamster\/esp8266-Arduino,stevemayhew\/Arduino,nkolban\/Arduino,adafruit\/ESP8266-Arduino,cscenter\/Arduino,lulufei\/Arduino,mc-hamster\/esp8266-Arduino,tbowmo\/Arduino,jmgonzalez00449\/Arduino,gberl001\/Arduino,wayoda\/Arduino,jaej-dev\/Arduino,NaSymbol\/Arduino,scdls\/Arduino,laylthe\/Arduino,PeterVH\/Arduino,gberl001\/Arduino,gberl001\/Arduino,leftbrainstrain\/Arduino-ESP8266,chaveiro\/Arduino,ikbelkirasan\/Arduino,aichi\/Arduino-2,aichi\/Arduino-2,KlaasDeNys\/Arduino,ashwin713\/Arduino,andrealmeidadomingues\/Arduino,shiitakeo\/Arduino,ogferreiro\/Arduino,wilhelmryan\/Arduino,Gourav2906\/Arduino,myrtleTree33\/Arduino,leftbrainstrain\/Arduino-ESP8266,gonium\/Arduino,shiitakeo\/Arduino,ForestNymph\/Arduino_sources,ntruchsess\/Arduino-1,stevemayhew\/Arduino,arunkuttiyara\/Arduino,ektor5\/Arduino,noahchense\/Arduino-1,gonium\/Arduino,henningpohl\/Arduino,andyvand\/Arduino-1,jaej-dev\/Arduino,adafruit\/ESP8266-Arduino,paulo-raca\/ESP8266-Arduino,drpjk\/Arduino,ogferreiro\/Arduino,Cloudino\/Cloudino-Arduino-IDE,NicoHood\/Arduino,laylthe\/Arduino,andyvand\/Arduino-1,wayoda\/Arduino,Protoneer\/Arduino,gberl001\/Arduino,superboonie\/Arduino,Cloudino\/Cloudino-Arduino-IDE,drpjk\/Arduino,mateuszdw\/Arduino,ari-analytics\/Arduino,tskurauskas\/Arduino,ogferreiro\/Arduino,niggor\/Arduino_cc,eddyst\/Arduino-SourceCode,eggfly\/arduino,PeterVH\/Arduino,mangelajo\/Arduino,plinioseniore\/Arduino,fungxu\/Arduino,jaej-dev\/Arduino,superboonie\/Arduino,steamboating\/Arduino,vbextreme\/Arduino,PaoloP74\/Arduino,aichi\/Arduino-2,nandojve\/Arduino,Gourav2906\/Arduino,ssvs111\/Arduino,andrealmeidadomingues\/Arduino,Chris--A\/Arduino,byran\/Arduino,jamesrob4\/Arduino,zaiexx\/Arduino,ccoenen\/Arduino,majenkotech\/Arduino,mangelajo\/Arduino,shannonshsu\/Arduino,xxxajk\/Arduino-1,HCastano\/Arduino,drpjk\/Arduino,Protoneer\/Arduino,chaveiro\/Arduino,Alfredynho\/AgroSis,Alfredynho\/AgroSis,byran\/Arduino,arduino-org\/Arduino,kidswong999\/Arduino,ForestNymph\/Arduino_sources,jaej-dev\/Arduino,nandojve\/Arduino,bsmr-arduino\/Arduino,mateuszdw\/Arduino,kidswong999\/Arduino,garci66\/Arduino,NicoHood\/Arduino,tbowmo\/Arduino,wdoganowski\/Arduino,ogahara\/Arduino,noahchense\/Arduino-1,adamkh\/Arduino,niggor\/Arduino_cc,ntruchsess\/Arduino-1,stevemarple\/Arduino-org,shannonshsu\/Arduino,piersoft\/esp8266-Arduino,spapadim\/Arduino,noahchense\/Arduino-1,Chris--A\/Arduino,Alfredynho\/AgroSis,gurbrinder\/Arduino,leftbrainstrain\/Arduino-ESP8266,mboufos\/esp8266-Arduino,ssvs111\/Arduino,paulo-raca\/ESP8266-Arduino,OpenDevice\/Arduino,arduino-org\/Arduino,plaintea\/esp8266-Arduino,ari-analytics\/Arduino,bigjosh\/Arduino,radut\/Arduino,paulo-raca\/ESP8266-Arduino,stevemayhew\/Arduino,arduino-org\/Arduino,ogahara\/Arduino,mateuszdw\/Arduino,wilhelmryan\/Arduino,niggor\/Arduino_cc,radut\/Arduino,tomkrus007\/Arduino,jaej-dev\/Arduino,ektor5\/Arduino,SmartArduino\/Arduino-1,jabezGit\/Arduino,NaSymbol\/Arduino,garci66\/Arduino,NicoHood\/Arduino,ricklon\/Arduino,gurbrinder\/Arduino,andyvand\/Arduino-1,tbowmo\/Arduino,scdls\/Arduino,raimohanska\/Arduino,wdoganowski\/Arduino,shannonshsu\/Arduino,rcook\/DesignLab,garci66\/Arduino,steamboating\/Arduino,wilhelmryan\/Arduino,mateuszdw\/Arduino,tskurauskas\/Arduino,lukeWal\/Arduino,myrtleTree33\/Arduino,UDOOboard\/Arduino,drpjk\/Arduino,vbextreme\/Arduino,ThoughtWorksIoTGurgaon\/Arduino,noahchense\/Arduino-1,ForestNymph\/Arduino_sources,gurbrinder\/Arduino,shiitakeo\/Arduino,byran\/Arduino,jomolinare\/Arduino,PeterVH\/Arduino,stevemarple\/Arduino-org,stickbreaker\/Arduino,eeijcea\/Arduino-1,tommyli2014\/Arduino,raimohanska\/Arduino,nandojve\/Arduino,mboufos\/esp8266-Arduino,jamesrob4\/Arduino,scdls\/Arduino,tannewt\/Arduino,jmgonzalez00449\/Arduino,tomkrus007\/Arduino,sanyaade-iot\/Arduino-1,mboufos\/esp8266-Arduino,eddyst\/Arduino-SourceCode,benwolfe\/esp8266-Arduino,steamboating\/Arduino,chaveiro\/Arduino,EmuxEvans\/Arduino,jabezGit\/Arduino,zaiexx\/Arduino,arduino-org\/Arduino,superboonie\/Arduino,PeterVH\/Arduino,EmuxEvans\/Arduino,fungxu\/Arduino,gberl001\/Arduino,Cloudino\/Arduino,chaveiro\/Arduino,radut\/Arduino,wdoganowski\/Arduino,jaehong\/Xmegaduino,Gourav2906\/Arduino,chaveiro\/Arduino,adamkh\/Arduino,rcook\/DesignLab,wdoganowski\/Arduino,jabezGit\/Arduino,xxxajk\/Arduino-1,koltegirish\/Arduino,eduardocasarin\/Arduino,bsmr-arduino\/Arduino,ari-analytics\/Arduino,rcook\/DesignLab,onovy\/Arduino,wilhelmryan\/Arduino,damellis\/Arduino,zaiexx\/Arduino,wdoganowski\/Arduino,karlitxo\/Arduino,jmgonzalez00449\/Arduino,jamesrob4\/Arduino,onovy\/Arduino,superboonie\/Arduino,lulufei\/Arduino,sanyaade-iot\/Arduino-1,gestrem\/Arduino,gurbrinder\/Arduino,eeijcea\/Arduino-1,KlaasDeNys\/Arduino,ogahara\/Arduino,HCastano\/Arduino,arduino-org\/Arduino,jaimemaretoli\/Arduino,paulmand3l\/Arduino,henningpohl\/Arduino,acosinwork\/Arduino,adamkh\/Arduino,arduino-org\/Arduino,cscenter\/Arduino,jaehong\/Xmegaduino,nkolban\/Arduino,acosinwork\/Arduino,talhaburak\/Arduino,zaiexx\/Arduino,xxxajk\/Arduino-1,mangelajo\/Arduino,plinioseniore\/Arduino,radut\/Arduino,raimohanska\/Arduino,lulufei\/Arduino,aichi\/Arduino-2,weera00\/Arduino,bigjosh\/Arduino,EmuxEvans\/Arduino,jaimemaretoli\/Arduino,NaSymbol\/Arduino,koltegirish\/Arduino,NeuralSpaz\/Arduino,adamkh\/Arduino,arunkuttiyara\/Arduino,koltegirish\/Arduino,lukeWal\/Arduino,noahchense\/Arduino-1,stickbreaker\/Arduino,fungxu\/Arduino,UDOOboard\/Arduino,paulo-raca\/ESP8266-Arduino,jmgonzalez00449\/Arduino,Cloudino\/Cloudino-Arduino-IDE,tskurauskas\/Arduino,tbowmo\/Arduino,talhaburak\/Arduino,probonopd\/Arduino,me-no-dev\/Arduino-1,pdNor\/Arduino,wilhelmryan\/Arduino,myrtleTree33\/Arduino,smily77\/Arduino,NaSymbol\/Arduino,jmgonzalez00449\/Arduino,gestrem\/Arduino,stickbreaker\/Arduino,probonopd\/Arduino,raimohanska\/Arduino,niggor\/Arduino_cc,laylthe\/Arduino,eduardocasarin\/Arduino,leftbrainstrain\/Arduino-ESP8266,ccoenen\/Arduino,raimohanska\/Arduino,toddtreece\/esp8266-Arduino,NicoHood\/Arduino,majenkotech\/Arduino,kidswong999\/Arduino,plaintea\/esp8266-Arduino,byran\/Arduino,eggfly\/arduino,arunkuttiyara\/Arduino,ThoughtWorksIoTGurgaon\/Arduino,vbextreme\/Arduino,jaehong\/Xmegaduino,plinioseniore\/Arduino,wayoda\/Arduino,ogahara\/Arduino,aichi\/Arduino-2,smily77\/Arduino,niggor\/Arduino_cc,ogferreiro\/Arduino,zederson\/Arduino,lulufei\/Arduino,eeijcea\/Arduino-1,eeijcea\/Arduino-1,NeuralSpaz\/Arduino,acosinwork\/Arduino,zederson\/Arduino,niggor\/Arduino_cc,wdoganowski\/Arduino,gberl001\/Arduino,SmartArduino\/Arduino-1,snargledorf\/Arduino,cscenter\/Arduino,ektor5\/Arduino,Cloudino\/Cloudino-Arduino-IDE,stevemayhew\/Arduino,raimohanska\/Arduino,lulufei\/Arduino,jaimemaretoli\/Arduino,andyvand\/Arduino-1,plaintea\/esp8266-Arduino,gestrem\/Arduino,NicoHood\/Arduino,ogferreiro\/Arduino,PaoloP74\/Arduino,adafruit\/ESP8266-Arduino,nkolban\/Arduino,weera00\/Arduino,mc-hamster\/esp8266-Arduino,weera00\/Arduino,Cloudino\/Cloudino-Arduino-IDE,Alfredynho\/AgroSis,benwolfe\/esp8266-Arduino,toddtreece\/esp8266-Arduino,aichi\/Arduino-2,talhaburak\/Arduino,KlaasDeNys\/Arduino,shannonshsu\/Arduino,mattvenn\/Arduino,sanyaade-iot\/Arduino-1,me-no-dev\/Arduino-1,jaehong\/Xmegaduino,wayoda\/Arduino,jaimemaretoli\/Arduino,bsmr-arduino\/Arduino,probonopd\/Arduino,mateuszdw\/Arduino,tannewt\/Arduino,danielchalef\/Arduino,ntruchsess\/Arduino-1,bigjosh\/Arduino,weera00\/Arduino,eduardocasarin\/Arduino,nkolban\/Arduino,xxxajk\/Arduino-1,PeterVH\/Arduino,ektor5\/Arduino,wayoda\/Arduino,ThoughtWorksIoTGurgaon\/Arduino,ForestNymph\/Arduino_sources,paulo-raca\/ESP8266-Arduino,PaoloP74\/Arduino,lukeWal\/Arduino,PaoloP74\/Arduino,PeterVH\/Arduino,gestrem\/Arduino,ashwin713\/Arduino,arduino-org\/Arduino,danielchalef\/Arduino,xxxajk\/Arduino-1,kidswong999\/Arduino,ogferreiro\/Arduino,tomkrus007\/Arduino,me-no-dev\/Arduino-1,tskurauskas\/Arduino,plinioseniore\/Arduino,byran\/Arduino,zederson\/Arduino,niggor\/Arduino_cc,karlitxo\/Arduino,UDOOboard\/Arduino,HCastano\/Arduino,ssvs111\/Arduino,kidswong999\/Arduino,zaiexx\/Arduino,HCastano\/Arduino,shannonshsu\/Arduino,myrtleTree33\/Arduino,Protoneer\/Arduino,tbowmo\/Arduino,garci66\/Arduino,mboufos\/esp8266-Arduino,bigjosh\/Arduino,lulufei\/Arduino,tommyli2014\/Arduino,arunkuttiyara\/Arduino,andrealmeidadomingues\/Arduino,karlitxo\/Arduino,ricklon\/Arduino,nkolban\/Arduino,zaiexx\/Arduino,acosinwork\/Arduino,superboonie\/Arduino,myrtleTree33\/Arduino,Chris--A\/Arduino,shannonshsu\/Arduino,eddyst\/Arduino-SourceCode,ari-analy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----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n\trom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 \/* Flash, 512K *\/\n\tsram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 \/* sram0, 64K *\/\n\tsram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 \/* sram1, 32K *\/\n\tram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 \/* sram, 96K *\/\n}\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss ALIGN(4) (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n       used for linker to calculate size of stack sections, and assign\n       values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack*)\n    } > ram\n\n    \/* Set stack top to end of ram, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(ram) + LENGTH(ram);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(_sstack = __StackLimit);\n    PROVIDE(_estack = __StackTop);\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n\trom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 \/* Flash, 512K *\/\n\tsram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 \/* sram0, 64K *\/\n\tsram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 \/* sram1, 32K *\/\n\tram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 \/* sram, 96K *\/\n}\n\nRAM_END = 0x20088000 ; \/* There is a way to define this as ram.ORIGIN + ram.LENGTH ? *\/\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n\n    \/* put stack section at the bottom of ram space *\/\n    .stack RAM_END (NOLOAD):\n    {\n        _sstack = .;\n        _estack = .;\n    } > ram\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"1b38494df4887306653d0ccf444c1192c983f2fd","subject":"bootloader: modify bootloader dram start address to 0x3fff0000","message":"bootloader: modify bootloader dram start address to 0x3fff0000\n\nModify bootloader dram_seg from address 0x3ffc0000 to 0x3fff0000, len from\n0x20000 to 0x10000. Please be notified that this is just a workaround for\nfixing app data overwrite bootloader data issue!\n","repos":"icamgo\/esp-idf,www220\/esp-idf,wmpluto\/esp-idf,hwmaier\/esp-idf,wmpluto\/esp-idf,jaracil\/esp-idf,jaracil\/esp-idf,daiyinger\/esp-idf,nineisk\/esp-idf,daiyinger\/esp-idf,Hermiedapwdrman\/esp-idf,tidyjiang8\/esp-idf-zh,daiyinger\/esp-idf,www220\/esp-idf,jaracil\/esp-idf,shukyisme\/esp-idf-kwik,icamgo\/esp-idf,armada-ai\/esp-idf,dschaefer\/esp-idf,daiyinger\/esp-idf,nineisk\/esp-idf,empoweredhomes\/esp-idf,espressif\/esp-idf,jaracil\/esp-idf,espressif\/esp-idf,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,tidyjiang8\/esp-idf-zh,ajs124\/esp-idf,mashaoze\/esp-idf,nineisk\/esp-idf,dschaefer\/esp-idf,MIhanguangyi\/esp-idf,tidyjiang8\/esp-idf-zh,icamgo\/esp-idf,dschaefer\/esp-idf,dschaefer\/esp-idf,shukyisme\/esp-idf-kwik,MIhanguangyi\/esp-idf,Hermiedapwdrman\/esp-idf,mashaoze\/esp-idf,dschaefer\/esp-idf,MIhanguangyi\/esp-idf,empoweredhomes\/esp-idf,armada-ai\/esp-idf,empoweredhomes\/esp-idf,espressif\/esp-idf,nineisk\/esp-idf,wmpluto\/esp-idf,www220\/esp-idf,dantonets\/Pingzee-ESP32,empoweredhomes\/esp-idf,tidyjiang8\/esp-idf-zh,Hermiedapwdrman\/esp-idf,shukyisme\/esp-idf-kwik,ajs124\/esp-idf,MIhanguangyi\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,tidyjiang8\/esp-idf-zh,hwmaier\/esp-idf,MIhanguangyi\/esp-idf,dantonets\/Pingzee-ESP32,Hermiedapwdrman\/esp-idf,Hermiedapwdrman\/esp-idf,hwmaier\/esp-idf,ajs124\/esp-idf,empoweredhomes\/esp-idf,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,espressif\/esp-idf,hwmaier\/esp-idf,dantonets\/Pingzee-ESP32,ajs124\/esp-idf,icamgo\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf,wmpluto\/esp-idf,dantonets\/Pingzee-ESP32,armada-ai\/esp-idf","old_file":"components\/bootloader\/src\/main\/esp32.bootloader.ld","new_file":"components\/bootloader\/src\/main\/esp32.bootloader.ld","new_contents":"\/*\nLinker file used to link the bootloader.\n\n*WARNING* For now this linker dumps everything into IRAM\/DRAM. ToDo: move\nsome\/most stuff to DROM\/IROM.\n\n*\/\n\n\n\/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES  *\/\n\/* The load addresses are defined later using the AT statements. *\/\nMEMORY\n{\n  \/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n  are connected to the data port of the CPU and eg allow bytewise access. *\/\n  dport0_seg (RW) :                 \torg = 0x3FF00000, len = 0x10\t\t\/* IO *\/\n  iram_seg (RWX) :                 \torg = 0x40080000, len = 0x400\t\t\/* 1k of IRAM used by bootloader functions which need to flush\/enable APP CPU cache *\/ \n  iram_pool_1_seg (RWX) :           org = 0x40078000, len = 0x8000    \/* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache *\/\n  dram_seg (RW) :                  \torg = 0x3FFF0000, len = 0x10000\t\t\/* Shared RAM, minus rom bss\/data\/stack.*\/\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n  .iram1.text :\n  {\n    _init_start = ABSOLUTE(.);\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n\t  \/* Code marked as runnning out of IRAM *\/\n\t  _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\t  _iram_text_end = ABSOLUTE(.);\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    KEEP(*(.bss))\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n\n\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n\t*(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram_pool_1.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n\t*(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram_pool_1_seg\n\n}\n","old_contents":"\/*\nLinker file used to link the bootloader.\n\n*WARNING* For now this linker dumps everything into IRAM\/DRAM. ToDo: move\nsome\/most stuff to DROM\/IROM.\n\n*\/\n\n\n\/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES  *\/\n\/* The load addresses are defined later using the AT statements. *\/\nMEMORY\n{\n  \/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n  are connected to the data port of the CPU and eg allow bytewise access. *\/\n  dport0_seg (RW) :                 \torg = 0x3FF00000, len = 0x10\t\t\/* IO *\/\n  iram_seg (RWX) :                 \torg = 0x40080000, len = 0x400\t\t\/* 1k of IRAM used by bootloader functions which need to flush\/enable APP CPU cache *\/ \n  iram_pool_1_seg (RWX) :           org = 0x40078000, len = 0x8000    \/* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache *\/\n  dram_seg (RW) :                  \torg = 0x3FFC0000, len = 0x20000\t\t\/* Shared RAM, minus rom bss\/data\/stack.*\/\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n  .iram1.text :\n  {\n    _init_start = ABSOLUTE(.);\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n\t  \/* Code marked as runnning out of IRAM *\/\n\t  _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\t  _iram_text_end = ABSOLUTE(.);\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    KEEP(*(.bss))\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n\n\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n\t*(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram_pool_1.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n\t*(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram_pool_1_seg\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a47432a01b6a65d06c612092c78a6c5f17e9c0bc","subject":"Fix arch back to i386 as this is what the linker scripts are for (at this time).","message":"Fix arch back to i386 as this is what the linker scripts are for (at this time).\n","repos":"Lucretia\/bare_bones","old_file":"src\/pc\/linker.ld","new_file":"src\/pc\/linker.ld","new_contents":"OUTPUT_FORMAT(elf32-i386)\nSTARTUP(startup.o)\nENTRY (startup)\n\nSECTIONS\n{\n    . = 0x00100000;\n\n    .text : {\n        *(.text)\n    }\n\n    .rodata ALIGN (0x1000) : {\n        *(.rodata)\n    }\n\n    .data ALIGN (0x1000) : {\n        *(.data)\n    }\n\n    .bss : {\n        *(COMMON)\n        *(.bss)\n    }\n\n    .note : {\n    \t  *(.note)\n    }\n\n    .debug : {\n    \t  *(.debug)\n    }\n}\n","old_contents":"OUTPUT_FORMAT(elf32-i586)\nSTARTUP(startup.o)\nENTRY (startup)\n\nSECTIONS\n{\n    . = 0x00100000;\n\n    .text : {\n        *(.text)\n    }\n\n    .rodata ALIGN (0x1000) : {\n        *(.rodata)\n    }\n\n    .data ALIGN (0x1000) : {\n        *(.data)\n    }\n\n    .bss : {\n        *(COMMON)\n        *(.bss)\n    }\n\n    .note : {\n    \t  *(.note)\n    }\n\n    .debug : {\n    \t  *(.debug)\n    }\n}\n","returncode":0,"stderr":"","license":"cc0-1.0","lang":"Linker Script"}
{"commit":"75e575476b8de3836a34c407cd26f9c6e4453cde","subject":"[bsp\/nrf5x] update link.lds","message":"[bsp\/nrf5x] update link.lds\n","repos":"hezlog\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread","old_file":"bsp\/nrf5x\/nrf52832\/board\/linker_scripts\/link.lds","new_file":"bsp\/nrf5x\/nrf52832\/board\/linker_scripts\/link.lds","new_contents":"\/* Linker script to configure memory regions. *\/\n\nMEMORY\n{\n  ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000  \/* 512K FLASH *\/\n  RAM (rw) : ORIGIN = 0x20000000, LENGTH = 0x10000  \/* 64K RAM    *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n\n        . = ALIGN(4);\n        \n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n\n        _etext = .;\n    } > ROM = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > ROM\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >RAM\n\n    .stack : \n    {\n        . = ALIGN(4);\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >RAM\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > RAM\n    __bss_end = .;\n\n    _end = .;\n\n    PROVIDE(__etext = __exidx_end);\n    PROVIDE(__data_start__ = _sdata);\n    PROVIDE(__bss_start__ = __bss_start);\n    PROVIDE(__bss_end__ = __bss_end);\n    PROVIDE(__StackTop = _estack);\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\nMEMORY\n{\n  ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000  \/* 512K FLASH *\/\n  RAM (rw) : ORIGIN = 0x20000000, LENGTH = 0x10000  \/* 64K RAM    *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n\n        . = ALIGN(4);\n        \n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n\n        _etext = .;\n    } > ROM = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > ROM\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >RAM\n\n    .stack : \n    {\n        . = ALIGN(4);\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >RAM\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > RAM\n    __bss_end = .;\n\n    _end = .;\n\n    PROVIDE(__etext = __exidx_end);\n    PROVIDE(__data_start__ = _sdata);\n    PROVIDE(__bss_start__ = __bss_start);\n    PROVIDE(__bss_end__ = __bss_end);\n    PROVIDE(__StackTop = _estack);\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"89abd9a95703ddb017115ed3b5dd233890abc6ee","subject":"Improvements in firmware\/sections.lds","message":"Improvements in firmware\/sections.lds\n","repos":"cliffordwolf\/picorv32,cliffordwolf\/picorv32,cliffordwolf\/picorv32,cliffordwolf\/picorv32","old_file":"firmware\/sections.lds","new_file":"firmware\/sections.lds","new_contents":"\/*\nThis is free and unencumbered software released into the public domain.\n\nAnyone is free to copy, modify, publish, use, compile, sell, or\ndistribute this software, either in source code form or as a compiled\nbinary, for any purpose, commercial or non-commercial, and by any\nmeans.\n*\/\n\nMEMORY {\n\t\/* the memory in the testbench is 64k in size;\n\t * set LENGTH=48k and leave at least 16k for stack *\/\n\tmem : ORIGIN = 0x00000000, LENGTH = 0x0000c000\n}\n\nSECTIONS {\n\t.memory : {\n\t\t. = 0x000000;\n\t\tstart*(.text);\n\t\t*(.text);\n\t\t*(*);\n\t\tend = .;\n\t} > mem\n}\n","old_contents":"\/*\nThis is free and unencumbered software released into the public domain.\n\nAnyone is free to copy, modify, publish, use, compile, sell, or\ndistribute this software, either in source code form or as a compiled\nbinary, for any purpose, commercial or non-commercial, and by any\nmeans.\n*\/\n\nMEMORY {\n\tmem : ORIGIN = 0x00000000, LENGTH = 0x00010000\n}\n\nSECTIONS {\n\t.memory : {\n\t\t. = 0x000000;\n\t\tstart*(.text);\n\t\t*(.text);\n\t\t*(*);\n\t\tend = .;\n\t} > mem\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"f9d8ccec71c19cf5f02edba686fb8243a669bc43","subject":"Use an independent build script that works","message":"Use an independent build script that works\n","repos":"nicholatian\/saturn,nicholatian\/saturn,nicholatian\/saturn","old_file":"util\/gba.ld","new_file":"util\/gba.ld","new_contents":"\nOUTPUT_ARCH(arm)\n\nENTRY(__start)\n\nMEMORY\n{\n    ewram   : ORIGIN = 0x2000000, LENGTH = 256k\n    iwram   : ORIGIN = 0x3000000, LENGTH = 32k\n    io      : ORIGIN = 0x4000000, LENGTH = 1k - 1\n    pal     : ORIGIN = 0x5000000, LENGTH = 1k\n    vram    : ORIGIN = 0x6000000, LENGTH = 96k\n    oam     : ORIGIN = 0x7000000, LENGTH = 1k\n    rom     : ORIGIN = 0x8000000, LENGTH = 32M\n}\n\nSECTIONS\n{\n    .text :\n    {\n        FILL (0xABCD)\n        \n        __text_start = . ;\n        *(.init)\n        *(.text)\n        *(.ctors)\n        *(.dtors)\n        *(.rodata)\n        *(.fini)\n        *(.data)\n        *(COMMON)\n        __text_end  = . ;\n        \n        __bss_start__ = . ;\n        *(.bss)\n        __bss_end__ = . ;\n        _end = __bss_end__ ;\n        __end__ = __bss_end__ ;\n    } >rom = 0xFF\n}\n","old_contents":"\/*****************************************************************************\\\n *                                                                           * \n *   .d8888b.          d8888 88888888888 888     888 8888888b.  888b    888  * \n *  d88P  Y88b        d88888     888     888     888 888   Y88b 8888b   888  * \n *  Y88b.            d88P888     888     888     888 888    888 88888b  888  * \n *   \"Y888b.        d88P 888     888     888     888 888   d88P 888Y88b 888  * \n *      \"Y88b.     d88P  888     888     888     888 8888888P\"  888 Y88b888  * \n *        \"888    d88P   888     888     888     888 888 T88b   888  Y88888  * \n *  Y88b  d88P   d8888888888     888     Y88b. .d88P 888  T88b  888   Y8888  * \n *   \"Y8888P\"   d88P     888     888      \"Y88888P\"  888   T88b 888    Y888  * \n *                                                                           * \n *                                   Saturn                                  * \n *     A general-purpose game engine for the Nintendo\u00ae Game Boy Advance\u2122     * \n *                                                                           * \n *                       Copyright \u00a9 2016  Nicholatian                       * \n *                                                                           * \n *  Licensed under the Apache License, Version 2.0 (the \u201cLicense\u201d); you may  * \n * not use this file except in compliance with the License. You may obtain a * \n *                          copy of the  License at                          * \n *                                                                           * \n *                http:\/\/www.apache.org\/licenses\/LICENSE-2.0                 * \n *                                                                           * \n *    Unless required by applicable law or agreed to in writing, software    * \n * distributed under the License is distributed on an \u201cAS IS\u201d BASIS, WITHOUT * \n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the  * \n *  License for the specific language governing permissions and limitations  * \n *                            under the  License.                            * \n *                                                                           * \n\\*****************************************************************************\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(__start)\n\/* SEARCH_DIR(\/bin\/arm); *\/\n\n\/* The linker script function \"var1 += var2;\" sometimes    *\/\n\/* reports incorrect values in the *.map file but the      *\/\n\/* actual value it calculates is usually, if not always,   *\/\n\/* correct. If you leave out the \". = ALIGN(4);\" at the    *\/\n\/* end of each section then the return value of SIZEOF()   *\/\n\/* is sometimes incorrect and \"var1 += var2;\" appears to   *\/\n\/* not work as well. \"var1 += var2\" style functions are    *\/\n\/* avoided below as a result.                              *\/\n\nMEMORY {\n\n\trom\t: ORIGIN = 0x08000000, LENGTH = 32M\n\tiwram\t: ORIGIN = 0x03000000, LENGTH = 32K\n\tewram\t: ORIGIN = 0x02000000, LENGTH = 256K\n}\n\n__text_start\t=\tORIGIN(rom);\n__eheap_end\t=\tORIGIN(ewram) + LENGTH(ewram);\n__iwram_start\t=\tORIGIN(iwram);\n__iwram_top\t=\tORIGIN(iwram) + LENGTH(iwram);;\n__sp_irq\t=\t__iwram_top - 0x060;\n__sp_usr\t=\t__sp_irq - 0x0a0;\n__irq_flags\t=\t0x03007ff8;\n\nSECTIONS\n{\n\t. = __text_start;\n\t.crt0 :\n\t{\n\t\tKEEP (*(.crt0))\n\t\t. = ALIGN(4);\n\t} >rom =0xff\n\n\n\t.init :\n\t{\n\t\tKEEP (*(SORT_NONE(.init)))\n\t} >rom\n\n\t.plt :\n\t{\n\t\t*(.plt)\n\t\t. = ALIGN(4);   \/* REQUIRED. LD is flaky without it. *\/\n\t} >rom\n\n\t.text  :   \/* ALIGN (4): *\/\n\t{\n\t\t*(EXCLUDE_FILE (*.iwram*) .text)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\tKEEP (*(.text.*personality*))\n\t\t\/* .gnu.warning sections are handled specially by elf32.em.  *\/\n\t\t*(.gnu.warning)\n\t\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer)\n\t\t. = ALIGN(4);  \/* REQUIRED. LD is flaky without it. *\/\n\t} >rom = 0xff\n\n\t__text_end = .;\n\t.fini           :\n\t{\n\t\tKEEP (*(.fini))\n\t\t. = ALIGN(4);  \/* REQUIRED. LD is flaky without it. *\/\n\t} >rom =0\n\n\t.rodata :\n\t{\n\t\t*(.rodata)\n\t\t*all.rodata*(*)\n\t\t*(.roda)\n\t\t*(.rodata.*)\n\t\t*(.gnu.linkonce.r*)\n\t\tSORT(CONSTRUCTORS)\n\t\t. = ALIGN(4);   \/* REQUIRED. LD is flaky without it. *\/\n\t} >rom = 0xff\n\t.ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >rom\n\t__exidx_start = .;\n\t.ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >rom\n\t__exidx_end = .;\n\n\t.ctors :\n\t{\n\t\t\/*\tgcc uses crtbegin.o to find the start of the constructors, so\n\t\t\twe make sure it is first.  Because this is a wildcard, it\n\t\t\tdoesn't matter if the user does not actually link against\n\t\t\tcrtbegin.o; the linker won't look for a file to match a\n\t\t\twildcard.  The wildcard also means that it doesn't matter which\n\t\t\tdirectory crtbegin.o is in.  *\/\n\t\tKEEP (*crtbegin.o(.ctors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t\t. = ALIGN(4);   \/* REQUIRED. LD is flaky without it. *\/\n\t} >rom = 0\n\n\t.dtors :\n\t{\n\t\tKEEP (*crtbegin.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t\t. = ALIGN(4);   \/* REQUIRED. LD is flaky without it. *\/\n\t} >rom = 0\n\n\n\t.eh_frame :\n\t{\n\t\tKEEP (*(.eh_frame))\n\t\t. = ALIGN(4);   \/* REQUIRED. LD is flaky without it. *\/\n\t} >rom = 0\n\n\t.gcc_except_table :\n\t{\n\t\t*(.gcc_except_table)\n\t\t. = ALIGN(4);   \/* REQUIRED. LD is flaky without it. *\/\n\t} >rom = 0\n\n\t__iwram_lma = .;\n\n\t.iwram __iwram_start : AT (__iwram_lma)\n\t{\n\t\t__iwram_start__ = ABSOLUTE(.) ;\n\t\t*(.iwram)\n\t\t*iwram.*(.text)\n\t\t. = ALIGN(4);   \/* REQUIRED. LD is flaky without it. *\/\n\t\t__iwram_end__ = ABSOLUTE(.) ;\n\t} >iwram = 0xff\n\n\t__data_lma = __iwram_lma + SIZEOF(.iwram) ;\n\n\t.bss ALIGN(4) (NOLOAD) :\n\t{\n\t\t__bss_start = ABSOLUTE(.);\n\t\t__bss_start__ = ABSOLUTE(.);\n\t\t*(.dynbss)\n\t\t*(.gnu.linkonce.b*)\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);    \/* REQUIRED. LD is flaky without it. *\/\n\t\t__bss_end__ = ABSOLUTE(.);\n\n\t} AT>iwram\n\n\t.data ALIGN(4) : AT (__data_lma)\n\t{\n\t\t__data_start__ = ABSOLUTE(.);\n\t\t*(.data)\n\t\t*(.data.*)\n\t\t*(.gnu.linkonce.d*)\n\t\tCONSTRUCTORS\n\t\t. = ALIGN(4);\n\t} >iwram = 0xff\n\n\t__preinit_lma = __data_lma + SIZEOF(.data);\n\n\t.preinit_array ALIGN(4)    : AT (__preinit_lma)\n\t{\n\t\t__preinit_array_start = ABSOLUTE(.);\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = ABSOLUTE(.);\n\t} >iwram\n\n\t__init_lma = __preinit_lma + SIZEOF(.preinit_array);\n\n\t.init_array  ALIGN(4)   : AT (__init_lma)\n\t{\n\t\t__init_array_start = ABSOLUTE(.);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = ABSOLUTE(.);\n\t} >iwram\n\n\t__fini_lma = __init_lma + SIZEOF(.init_array);\n\n\t.fini_array  ALIGN(4)   : AT (__fini_lma)\n\t{\n\t\t__fini_array_start = ABSOLUTE(.);\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tKEEP (*(.fini_array))\n  \t\t__fini_array_end = ABSOLUTE(.);\n\t} >iwram\n\n\t__jcr_lma = __fini_lma + SIZEOF(.fini_array);\n\t.jcr        ALIGN(4)    : AT (__jcr_lma) { KEEP (*(.jcr)) } >iwram\n\n\t__data_end__  =  ABSOLUTE(.);\n\t__iwram_overlay_lma = __jcr_lma + SIZEOF(.jcr);\n\n\t__iwram_overlay_start = . ;\n\n\tOVERLAY ALIGN(4) : NOCROSSREFS AT (__iwram_overlay_lma)\n\t{\n\t\t.iwram0 { *(.iwram0) . = ALIGN(4);}\n\t\t.iwram1 { *(.iwram1) . = ALIGN(4);}\n\t\t.iwram2 { *(.iwram2) . = ALIGN(4);}\n\t\t.iwram3 { *(.iwram3) . = ALIGN(4);}\n\t\t.iwram4 { *(.iwram4) . = ALIGN(4);}\n\t\t.iwram5 { *(.iwram5) . = ALIGN(4);}\n\t\t.iwram6 { *(.iwram6) . = ALIGN(4);}\n\t\t.iwram7 { *(.iwram7) . = ALIGN(4);}\n\t\t.iwram8 { *(.iwram8) . = ALIGN(4);}\n\t\t.iwram9 { *(.iwram9) . = ALIGN(4);}\n\t}>iwram = 0xff\n\n\t__iwram_overlay_end = . ;\n\t__ewram_lma = __iwram_overlay_lma + (__iwram_overlay_end - __iwram_overlay_start) ;\n\n\t__iheap_start = . ;\n\n\t__ewram_start = ORIGIN(ewram);\n\t.ewram __ewram_start : AT (__ewram_lma)\n\t{\n\t\t*(.ewram)\n\t\t. = ALIGN(4);  \/* REQUIRED. LD is flaky without it. *\/\n\t\t__ewram_end = ABSOLUTE(.);\n\t}>ewram = 0xff\n\n\t__pad_lma = __ewram_lma + SIZEOF(.ewram);\n\n\t.sbss ALIGN(4)(NOLOAD):\n \t{\n\t\t__sbss_start__ = ABSOLUTE(.);\n \t\t*(.sbss)\n \t\t. = ALIGN(4);\n\t\t__sbss_end__  = ABSOLUTE(.);\n\t\t__end__ = ABSOLUTE(.);\n\t\t__eheap_start = ABSOLUTE(.);\n \t} AT>ewram\n\n\t\/* EZF Advance strips trailing 0xff bytes, add a pad section so nothing important is removed *\/\n\t.pad ALIGN(4) : AT (__pad_lma)\n\t{\n\t\tLONG(0x52416b64)\n\t\tLONG(0x4d)\n\t\t. = ALIGN(4);  \/* REQUIRED. LD is flaky without it. *\/\n\t} = 0xff\n\t__rom_end__ = __pad_lma + SIZEOF(.pad);\n\n\n\t\/* Stabs debugging sections.  *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t\/*\tDWARF debug sections.\n\t\tSymbols in the DWARF debugging sections are relative to the beginning\n\t\tof the section so we begin them at 0.  *\/\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\n\t.debug_typenames 0 : { *(.debug_typenames) }\n\t.debug_varnames  0 : { *(.debug_varnames) }\n\t.stack 0x80000 : { _stack = .; *(.stack) }\n\t\/* These must appear regardless of  .  *\/\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7b4be727fa1e7ccfef55b2f95b16c5552767ca2f","subject":"Cleanup linker script.","message":"Cleanup linker script.\n","repos":"krinkinmu\/auos,krinkinmu\/auos,krinkinmu\/auos,krinkinmu\/auos","old_file":"kernel\/arch\/x86\/boot\/kernel.ld","new_file":"kernel\/arch\/x86\/boot\/kernel.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nPAGE_OFFSET = 0xC0000000;\nPAGE_SIZE   = 0x00001000;\n\nSECTIONS\n{\n\t\/* GRUB will load kernel in memory starting from 1Mb *\/\n\t. = 1M;\n\t.header    : { *(.header) }\n\t.bootstrap : { *(.bootstrap) }\n\n\t. += PAGE_OFFSET;\n\t__kernel_begin = .;\n\n\t.text   : AT(ADDR(.text) - PAGE_OFFSET) { *(.text)   *(.text.*) }\n\t.rodata : { *(.rodata) *(.rodata.*) }\n\t.data   : { *(.data)   *(.data.*) }\n\n\t. = ALIGN(PAGE_SIZE);\n\t__bss_begin = .;\n\t.bss : { *(.bss) }\n\n\t. = ALIGN(PAGE_SIZE);\n\t__heap_begin = .;\n\t.brk : { . += 1M; }\n\t__bss_end = .;\n\t__kernel_end = .;\n\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\t.debug_info    0 : { *(.debug_info) }\n\t.debug_abbrev  0 : { *(.debug_abbrev) }\n\t.debug_line    0 : { *(.debug_line) }\n        .debug_str     0 : { *(.debug_str) }\n\n\t\/DISCARD\/ : { *(.eh_frame .note.* .comment) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nPAGE_OFFSET = 0xC0000000;\nPAGE_SIZE   = 0x00001000;\n\nSECTIONS\n{\n\t\/* GRUB will load kernel in memory starting from 1Mb *\/\n\t. = 1M;\n\t.header    : { *(.header) }\n\n\t. += PAGE_OFFSET;\n\t__kernel_begin = .;\n\t.bootstrap : AT(ADDR(.bootstrap) - PAGE_OFFSET) { *(.bootstrap) }\n\n\t.text   : { *(.text)   *(.text.*) }\n\t.rodata : { *(.rodata) *(.rodata.*) }\n\t.data   : { *(.data)   *(.data.*) }\n\n\t. = ALIGN(PAGE_SIZE);\n\t__bss_begin = .;\n\t.bss : { *(.bss) }\n\t. = ALIGN(PAGE_SIZE);\n\t__heap_begin = .;\n\t.brk : { . += 1M; }\n\t__heap_end = .;\n\t__bss_end = .;\n\t__kernel_end = .;\n\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\t.debug_info    0 : { *(.debug_info) }\n\t.debug_abbrev  0 : { *(.debug_abbrev) }\n\t.debug_line    0 : { *(.debug_line) }\n        .debug_str     0 : { *(.debug_str) }\n\n\t\/DISCARD\/ : { *(.eh_frame .note.* .comment) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"56a98e11d1e936ef9b1a813273742554796879f7","subject":"Move ticker related text to SRAM to fix GCC mbed-os-tests-mbed_drivers-timeout failing issue","message":"Move ticker related text to SRAM to fix GCC mbed-os-tests-mbed_drivers-timeout failing issue\n","repos":"HeadsUpDisplayInc\/mbed,ryankurte\/mbed-os,betzw\/mbed-os,nRFMesh\/mbed-os,mbedmicro\/mbed,YarivCol\/mbed-os,Archcady\/mbed-os,HeadsUpDisplayInc\/mbed,HeadsUpDisplayInc\/mbed,Archcady\/mbed-os,kjbracey-arm\/mbed,nRFMesh\/mbed-os,mazimkhan\/mbed-os,andcor02\/mbed-os,YarivCol\/mbed-os,mazimkhan\/mbed-os,betzw\/mbed-os,infinnovation\/mbed-os,mbedmicro\/mbed,ryankurte\/mbed-os,svogl\/mbed-os,svogl\/mbed-os,YarivCol\/mbed-os,HeadsUpDisplayInc\/mbed,CalSol\/mbed,CalSol\/mbed,karsev\/mbed-os,kjbracey-arm\/mbed,catiedev\/mbed-os,mazimkhan\/mbed-os,catiedev\/mbed-os,Archcady\/mbed-os,mbedmicro\/mbed,infinnovation\/mbed-os,nRFMesh\/mbed-os,CalSol\/mbed,Archcady\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,betzw\/mbed-os,HeadsUpDisplayInc\/mbed,mbedmicro\/mbed,mazimkhan\/mbed-os,betzw\/mbed-os,svogl\/mbed-os,Archcady\/mbed-os,karsev\/mbed-os,YarivCol\/mbed-os,ryankurte\/mbed-os,CalSol\/mbed,nRFMesh\/mbed-os,nRFMesh\/mbed-os,YarivCol\/mbed-os,infinnovation\/mbed-os,karsev\/mbed-os,CalSol\/mbed,catiedev\/mbed-os,betzw\/mbed-os,svogl\/mbed-os,Archcady\/mbed-os,ryankurte\/mbed-os,mazimkhan\/mbed-os,kjbracey-arm\/mbed,mazimkhan\/mbed-os,andcor02\/mbed-os,ryankurte\/mbed-os,andcor02\/mbed-os,infinnovation\/mbed-os,c1728p9\/mbed-os,svogl\/mbed-os,svogl\/mbed-os,c1728p9\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,ryankurte\/mbed-os,YarivCol\/mbed-os,infinnovation\/mbed-os,catiedev\/mbed-os,CalSol\/mbed,catiedev\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os,karsev\/mbed-os,karsev\/mbed-os,betzw\/mbed-os,mbedmicro\/mbed,karsev\/mbed-os,nRFMesh\/mbed-os,c1728p9\/mbed-os,infinnovation\/mbed-os,HeadsUpDisplayInc\/mbed,catiedev\/mbed-os","old_file":"targets\/TARGET_Realtek\/TARGET_AMEBA\/TARGET_RTL8195A\/device\/TOOLCHAIN_GCC_ARM\/rtl8195a.ld","new_file":"targets\/TARGET_Realtek\/TARGET_AMEBA\/TARGET_RTL8195A\/device\/TOOLCHAIN_GCC_ARM\/rtl8195a.ld","new_contents":"\/*\n * Copyright (c) 2013-2016 Realtek Semiconductor Corp.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nINCLUDE \"mbed-os\/targets\/TARGET_Realtek\/TARGET_AMEBA\/TARGET_RTL8195A\/device\/TOOLCHAIN_GCC_ARM\/rtl8195a_rom.h\"\n\/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).\n   But we can put .data\/.bss of Image2 in this region *\/\nMEMORY\n{\n  TCM (rwx)        : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  DATA_RAM (rwx)   : ORIGIN = 0x10002100, LENGTH = 0x10007000 - 0x10002100\n  SRAM1 (rwx)      : ORIGIN = 0x10007000, LENGTH = 0x10070000 - 0x10007000\n  SRAM2 (rwx)      : ORIGIN = 0x30000000, LENGTH = 2M\n}\n\n\/* Stack sizes: *\/\nStackSize = 0x1000;\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .image2.table :\n    {\n        KEEP(*(SORT(.image2.ram.data*)))\n        KEEP(*(.image2.validate.rodata*))\n    } > SRAM2\n\n    .text.sram1 :\n    {\n        . = ALIGN(4);\n        *rtl8195a_crypto.o (.text* .rodata*)\n        *mbedtls*.o (.text* .rodata*)\n        *libc.a: (.text* .rodata*)\n\t\t*Ticker.o (.text*)\n\t\t*Timeout.o (.text*)\n\t\t*TimerEvent.o (.text*)\n\t\t*mbed_ticker_api.o (.text*)\n\t\t*mbed_critical.o (.text*)\n\t\t\n\t\t*us_ticker.o (.text*)\n\t\t*lib_peripheral_mbed_gcc.a: (.text*)\n\t\t\n    } > SRAM1\n\n    .text.sram2 :\n    {\n        . = ALIGN(4);\n        *(.mon.ram.text*)\n        *(.hal.flash.text*)\n        *(.hal.sdrc.text*)\n        *(.hal.gpio.text*)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > SRAM2\n    __etext = .;\n\n    __data_start__ = .;\n\n    .data.sram1 :\n    {\n        . = ALIGN(4);\n        __sram_data_start__ = .;\n        *rtl8195a_crypto*.o (.data*)\n        *mbedtls*.o (.data*)\n        __sram_data_end__ = .;\n    } > SRAM1\n\n    .data.sram2 :\n    {\n        __sdram_data_start__ = .;\n        *(vtable)\n        *(.data*)\n        *(.sdram.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n\n        __sdram_data_end__ = .;\n        \/* All data end *\/\n    } > SRAM2\n    __data_end__ = .;\n    __image2_end__ = .;\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > SRAM2\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > SRAM2\n    __exidx_end = .;\n\n    .bss.sram1 (NOLOAD) :\n    {\n        __bss_sram_start__ = .;\n        *rtl8195a_crypto.o (.bss* COMMON)\n        *mbedtls*.o (.bss* COMMON)\n        *(.bss.thread_stack_main)\n        __bss_sram_end__ = .;\n    } > SRAM1\n\n    .bss.sram2 (NOLOAD) :\n    {\n        __bss_start__ = .;\n        __bss_dram_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        *(.bdsram.data*)\n        __bss_dram_end__ = .;\n        __bss_end__ = .;\n    } > SRAM2\n\n    .bf_data :\n    {\n        __buffer_data_start__ = .;\n        *(.bfsram.data*)\n        __buffer_data_end__ = .;\n    } > SRAM2\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n\t. = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;\n        __HeapLimit = .;\n    } > SRAM1\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack)\n\t. += StackSize - (. - __StackLimit);\n    } > SRAM1\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM exceeds ram limit\")\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2016 Realtek Semiconductor Corp.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nINCLUDE \"mbed-os\/targets\/TARGET_Realtek\/TARGET_AMEBA\/TARGET_RTL8195A\/device\/TOOLCHAIN_GCC_ARM\/rtl8195a_rom.h\"\n\/* DATA_RAM: We cannot put Code(.text) in DATA_RAM, this region is reserved for Image1(boot loader).\n   But we can put .data\/.bss of Image2 in this region *\/\nMEMORY\n{\n  TCM (rwx)        : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  DATA_RAM (rwx)   : ORIGIN = 0x10002100, LENGTH = 0x10007000 - 0x10002100\n  SRAM1 (rwx)      : ORIGIN = 0x10007000, LENGTH = 0x10070000 - 0x10007000\n  SRAM2 (rwx)      : ORIGIN = 0x30000000, LENGTH = 2M\n}\n\n\/* Stack sizes: *\/\nStackSize = 0x1000;\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .image2.table :\n    {\n        KEEP(*(SORT(.image2.ram.data*)))\n        KEEP(*(.image2.validate.rodata*))\n    } > SRAM2\n\n    .text.sram1 :\n    {\n        . = ALIGN(4);\n        *rtl8195a_crypto.o (.text* .rodata*)\n        *mbedtls*.o (.text* .rodata*)\n        *libc.a: (.text* .rodata*)\n    } > SRAM1\n\n    .text.sram2 :\n    {\n        . = ALIGN(4);\n        *(.mon.ram.text*)\n        *(.hal.flash.text*)\n        *(.hal.sdrc.text*)\n        *(.hal.gpio.text*)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > SRAM2\n    __etext = .;\n\n    __data_start__ = .;\n\n    .data.sram1 :\n    {\n        . = ALIGN(4);\n        __sdram_data_start__ = .;\n        *rtl8195a_crypto*.o (.data*)\n        *mbedtls*.o (.data*)\n        *(.sdram.data*)\n        __sdram_data_end__ = .;\n    } > SRAM1\n\n    .data.sram2 :\n    {\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n\n        \/* All data end *\/\n    } > SRAM2\n    __data_end__ = .;\n    __image2_end__ = .;\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > SRAM2\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > SRAM2\n    __exidx_end = .;\n\n    .bss.sram1 (NOLOAD) :\n    {\n        __bss_sram_start__ = .;\n        *rtl8195a_crypto.o (.bss* COMMON)\n        *mbedtls*.o (.bss* COMMON)\n        *(.bss.thread_stack_main)\n        __bss_sram_end__ = .;\n    } > SRAM1\n\n    .bss.sram2 (NOLOAD) :\n    {\n        __bss_start__ = .;\n        __bss_dram_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        *(.bdsram.data*)\n        __bss_dram_end__ = .;\n        __bss_end__ = .;\n    } > SRAM2\n\n    .bf_data :\n    {\n        __buffer_data_start__ = .;\n        *(.bfsram.data*)\n        __buffer_data_end__ = .;\n    } > SRAM2\n\n    .heap (NOLOAD):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n\t. = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;\n        __HeapLimit = .;\n    } > SRAM1\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (NOLOAD):\n    {\n        __StackLimit = .;\n        *(.stack)\n\t. += StackSize - (. - __StackLimit);\n    } > SRAM1\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM exceeds ram limit\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"af4a044e6fe174896176e0dea0fa97dd35130cc5","subject":"soc: stm32wb: Move MB_MEM2 linker section to SRAM1","message":"soc: stm32wb: Move MB_MEM2 linker section to SRAM1\n\nThere was a confusion on MB_MEMx definitions. Both MB_MEM1\/2\nshould be located in SRAM1. Fix this.\n\nSigned-off-by: Erwan Gouriou <de4d967452b83bb0e37525652734e7d9163b6a4c@linaro.org>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr","old_file":"soc\/arm\/st_stm32\/stm32wb\/ipm.ld","new_file":"soc\/arm\/st_stm32\/stm32wb\/ipm.ld","new_contents":"\/*\n * Copyright (c) 2019 Linaro Limited\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n   MAPPING_TABLE (NOLOAD) : {_sMAPPING_TABLE = .; *(MAPPING_TABLE); _eMAPPING_TABLE = .; } >SRAM1\n   MB_MEM1 (NOLOAD) : { _sMB_MEM1 = .; *(MB_MEM1); _eMB_MEM1 = .; } >SRAM1\n   MB_MEM2 (NOLOAD) : { _sMB_MEM2 = .; *(MB_MEM2); _eMB_MEM2 = .; } >SRAM1\n","old_contents":"\/*\n * Copyright (c) 2019 Linaro Limited\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n   MAPPING_TABLE (NOLOAD) : {_sMAPPING_TABLE = .; *(MAPPING_TABLE); _eMAPPING_TABLE = .; } >SRAM1\n   MB_MEM1 (NOLOAD) : { _sMB_MEM1 = .; *(MB_MEM1); _eMB_MEM1 = .; } >SRAM1\n   MB_MEM2 (NOLOAD) : { _sMB_MEM2 = .; *(MB_MEM2); _eMB_MEM2 = .; } >SRAM2\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3cd63205c70a596b1ae9be5b35db034893e64e69","subject":"Don't strip good to have ELF sections","message":"Don't strip good to have ELF sections\n\nSigned-off-by: Dan Printzell <69f25cbe4b2608181d39803083cb5ee0c30f2794@gmail.com>\n","repos":"Vild\/PowerNex","old_file":"loader\/src\/loader.ld","new_file":"loader\/src\/loader.ld","new_contents":"OUTPUT_FORMAT(elf64-x86-64)\nENTRY(start)\n\nPHDRS {\n\tphdr PT_LOAD PHDRS FILEHDR;\n\tload PT_LOAD;\n\ttls PT_TLS;\n}\n\nSECTIONS {\n\t. = 1M;\n\n\t.multiboot : {\n\t\tLONG(0x0) \/* To force the linker to put .multiboot first*\/\n\t\t*(.multiboot)\n\t} :load\n\n\t.text ALIGN(0x1000) : {\n\t\t*(.text .text.*)\n\t} :load\n\n\t.rodata ALIGN(0x1000) : {\n\t\t*(.rodata .rodata.*)\n\t} :load\n\n\t.ctors ALIGN(0x1000) : {\n\t\tCTORS_START = .;\n\t\t*(.ctors .ctors.*)\n\t\tCTORS_END = .;\n\t} :load\n\n\t.dtors ALIGN(0x1000) : {\n\t\tDTORS_START = .;\n\t\t*(.dtors .dtors.*)\n\t\tDTORS_END = .;\n\t} :load\n\n\t.eh_frame ALIGN(0x1000) : {\n\t\t*(.eh_frame .eh_frame.*)\n\t} :load\n\n\t.data ALIGN(0x1000) : {\n\t\t*(.data .data.*)\n\t} :load\n\n\t.bss ALIGN(0x1000) : {\n\t\t*(.bss .bss.*)\n\t} :load\n\n\t.loaderData ALIGN(0x1000) : {\n\t\tloaderData_start = .;\n\t\t*(.loaderData .loaderData.*)\n\t\tloaderData_end = .;\n\t} :load\n\n\t.tdata ALIGN(0x1000) :  {\n\t\tTDATA_START = .;\n\t\t*(.tdata .tdata.*)\n\t\tTDATA_END = .;\n\t} :tls :load\n\n\t.tbss : {\n\t\tTBSS_START = .;\n\t\t*(.tbss .tbss.*)\n\t\tTBSS_END = .;\n\t} :tls :load\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t\t*(.note .note.*)\n\t}\n}\n","old_contents":"OUTPUT_FORMAT(elf64-x86-64)\nENTRY(start)\n\nPHDRS {\n\tphdr PT_LOAD PHDRS FILEHDR;\n\tload PT_LOAD;\n\ttls PT_TLS;\n}\n\nSECTIONS {\n\t. = 1M;\n\n\t.multiboot : {\n\t\tLONG(0x0) \/* To force the linker to put .multiboot first*\/\n\t\t*(.multiboot)\n\t} :load\n\n\t.text ALIGN(0x1000) : {\n\t\t*(.text .text.*)\n\t} :load\n\n\t.rodata ALIGN(0x1000) : {\n\t\t*(.rodata .rodata.*)\n\t} :load\n\n\t.ctors ALIGN(0x1000) : {\n\t\tCTORS_START = .;\n\t\t*(.ctors .ctors.*)\n\t\tCTORS_END = .;\n\t} :load\n\n\t.dtors ALIGN(0x1000) : {\n\t\tDTORS_START = .;\n\t\t*(.dtors .dtors.*)\n\t\tDTORS_END = .;\n\t} :load\n\n\t.eh_frame ALIGN(0x1000) : {\n\t\t*(.eh_frame .eh_frame.*)\n\t} :load\n\n\t.data ALIGN(0x1000) : {\n\t\t*(.data .data.*)\n\t} :load\n\n\t.bss ALIGN(0x1000) : {\n\t\t*(.bss .bss.*)\n\t} :load\n\n\t.loaderData ALIGN(0x1000) : {\n\t\tloaderData_start = .;\n\t\t*(.loaderData .loaderData.*)\n\t\tloaderData_end = .;\n\t} :load\n\n\t.tdata ALIGN(0x1000) :  {\n\t\tTDATA_START = .;\n\t\t*(.tdata .tdata.*)\n\t\tTDATA_END = .;\n\t} :tls :load\n\n\t.tbss : {\n\t\tTBSS_START = .;\n\t\t*(.tbss .tbss.*)\n\t\tTBSS_END = .;\n\t} :tls :load\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t\t*(.note .note.*)\n\t\t*(.rela.*)\n\t\t*(.debug_*)\n\t}\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"5bcb27ae8ffca39bbd317d1abdfdac7debf70fcf","subject":"Export a variable at the end of the kernel","message":"Export a variable at the end of the kernel\n","repos":"awensaunders\/kernel-of-truth,iankronquist\/kernel-of-truth,iankronquist\/kernel-of-truth,iankronquist\/kernel-of-truth,Herbstein\/kernel-of-truth,awensaunders\/kernel-of-truth,Herbstein\/kernel-of-truth,Herbstein\/kernel-of-truth,iankronquist\/kernel-of-truth,iankronquist\/kernel-of-truth,awensaunders\/kernel-of-truth","old_file":"kernel\/arch\/x86\/linker.ld","new_file":"kernel\/arch\/x86\/linker.ld","new_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 1M;\n\n\t\/* First put the multiboot header, as it is required to be put very early\n\t   early in the image or the bootloader won't recognize the file format.\n\t   Next we'll put the .text section. *\/\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t\tkernel_end = .;\n\t}\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","old_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 1M;\n\n\t\/* First put the multiboot header, as it is required to be put very early\n\t   early in the image or the bootloader won't recognize the file format.\n\t   Next we'll put the .text section. *\/\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t}\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"77be96912d299f0b9ac7e5ed765b7917ff9a9721","subject":"[cosmetic] Fix indentation of linker script","message":"[cosmetic] Fix indentation of linker script\n","repos":"vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs","old_file":"kernel\/arch\/i386\/linker_script.ld","new_file":"kernel\/arch\/i386\/linker_script.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"unknown","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"e213d3cac314b9d3dcd552b55b0de204ffda1483","subject":"Fix undefined reference to `sched_check_switch' error on some configs","message":"Fix undefined reference to `sched_check_switch' error on some configs","repos":"vrxfile\/embox-trik,mike2390\/embox,embox\/embox,Kakadu\/embox,Kefir0192\/embox,vrxfile\/embox-trik,gzoom13\/embox,gzoom13\/embox,abusalimov\/embox,Kefir0192\/embox,mike2390\/embox,Kefir0192\/embox,gzoom13\/embox,vrxfile\/embox-trik,embox\/embox,abusalimov\/embox,vrxfile\/embox-trik,vrxfile\/embox-trik,Kakadu\/embox,vrxfile\/embox-trik,Kakadu\/embox,Kakadu\/embox,abusalimov\/embox,mike2390\/embox,mike2390\/embox,Kakadu\/embox,mike2390\/embox,Kefir0192\/embox,Kakadu\/embox,embox\/embox,Kefir0192\/embox,Kefir0192\/embox,gzoom13\/embox,mike2390\/embox,gzoom13\/embox,Kakadu\/embox,gzoom13\/embox,abusalimov\/embox,abusalimov\/embox,abusalimov\/embox,embox\/embox,Kefir0192\/embox,vrxfile\/embox-trik,embox\/embox,mike2390\/embox,gzoom13\/embox,embox\/embox","old_file":"src\/kernel\/nosys.lds","new_file":"src\/kernel\/nosys.lds","new_contents":"\nPROVIDE(diag_init = nosys);\nPROVIDE(diag_getc = nosys);\nPROVIDE(diag_putc = nosys);\n\nPROVIDE(irq_init     = nosys);\nPROVIDE(irq_attach   = nosys);\nPROVIDE(irq_detach   = nosys);\nPROVIDE(irq_dispatch = nosys);\n\nPROVIDE(softirq_init     = nosys);\nPROVIDE(softirq_install  = nosys);\nPROVIDE(softirq_raise    = nosys);\nPROVIDE(softirq_dispatch = nosys);\n\nPROVIDE(sched_policy_current = nosys);\nPROVIDE(__sched_dispatch = nosys);\nPROVIDE(sched_check_switch = nosys);\n\nPROVIDE(printk = nosys);\n\nPROVIDE(timer_init = nosys);\nPROVIDE(set_timer = nosys);\nPROVIDE(close_timer = nosys);\nPROVIDE(timers_off = nosys);\nPROVIDE(irq_func_tmr_1mS = nosys);\nPROVIDE(usleep = nosys);\n\n\/* XXX remove from here. -- Eldar *\/\nPROVIDE(uart_init = nosys);\n","old_contents":"\nPROVIDE(diag_init = nosys);\nPROVIDE(diag_getc = nosys);\nPROVIDE(diag_putc = nosys);\n\nPROVIDE(irq_init     = nosys);\nPROVIDE(irq_attach   = nosys);\nPROVIDE(irq_detach   = nosys);\nPROVIDE(irq_dispatch = nosys);\n\nPROVIDE(softirq_init     = nosys);\nPROVIDE(softirq_install  = nosys);\nPROVIDE(softirq_raise    = nosys);\nPROVIDE(softirq_dispatch = nosys);\n\nPROVIDE(sched_policy_current = nosys);\nPROVIDE(__sched_dispatch = nosys);\n\nPROVIDE(printk = nosys);\n\nPROVIDE(timer_init = nosys);\nPROVIDE(set_timer = nosys);\nPROVIDE(close_timer = nosys);\nPROVIDE(timers_off = nosys);\nPROVIDE(irq_func_tmr_1mS = nosys);\nPROVIDE(usleep = nosys);\n\n\/* XXX remove from here. -- Eldar *\/\nPROVIDE(uart_init = nosys);\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"2bc32350b1eaeb1eacd837f481b343be7ed63e58","subject":"[RISCV] fix bug that .rodata put into IMEM","message":"[RISCV] fix bug that .rodata put into IMEM\n","repos":"chenm001\/x266,chenm001\/x266,chenm001\/x266,chenm001\/x266","old_file":"riscv\/programs\/benchmarks\/common\/test.ld","new_file":"riscv\/programs\/benchmarks\/common\/test.ld","new_contents":"\/*======================================================================*\/\n\/* Proxy kernel linker script                                           *\/\n\/*======================================================================*\/\n\/* This is the linker script used when building the proxy kernel. *\/\n\n\/*----------------------------------------------------------------------*\/\n\/* Setup                                                                *\/\n\/*----------------------------------------------------------------------*\/\n\n\/* The OUTPUT_ARCH command specifies the machine architecture where the\n   argument is one of the names used in the BFD library. More\n   specifically one of the entires in bfd\/cpu-mips.c *\/\nOUTPUT_ARCH( \"riscv\" )\n\n\/*----------------------------------------------------------------------*\/\n\/* Sections                                                             *\/\n\/*----------------------------------------------------------------------*\/\n\nMEMORY\n{\n    rom (RX) : ORIGIN = 0x00000, LENGTH = 0x10000\n    ram (RW) : ORIGIN = 0x10000, LENGTH = 0x20000\n}\n\nSECTIONS\n{\n\n  \/* text: test code section *\/\n  . = 0x100;\n  .text 0x100 : ONLY_IF_RO\n  {\n    crt.o(.text)\n    *(.text*)\n  } > rom\n\n  \/* data segment *\/\n  .data : ONLY_IF_RW\n  {\n    *(.data*)\n  } > ram\n\n  .rodata : ONLY_IF_RO\n  {\n    *(.rodata*)\n  } > ram\n\n  .sdata : ONLY_IF_RW\n  {\n    _gp = . + 0x800;\n    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n  } > ram\n\n  \/* bss segment *\/\n  .sbss : ONLY_IF_RW\n  {\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n  } > ram\n  .bss : { *(.bss) }\n\n  \/* thread-local data segment *\/\n  .tdata : ONLY_IF_RW\n  {\n    _tls_data = .;\n    crt.o(.tdata.begin)\n    *(.tdata)\n    crt.o(.tdata.end)\n  } > ram\n\n  .tbss : ONLY_IF_RW\n  {\n    *(.tbss)\n    crt.o(.tbss.end)\n  } > ram\n\n  \/* End of uninitalized data segement *\/\n  _end = .;\n}\n\n","old_contents":"\/*======================================================================*\/\n\/* Proxy kernel linker script                                           *\/\n\/*======================================================================*\/\n\/* This is the linker script used when building the proxy kernel. *\/\n\n\/*----------------------------------------------------------------------*\/\n\/* Setup                                                                *\/\n\/*----------------------------------------------------------------------*\/\n\n\/* The OUTPUT_ARCH command specifies the machine architecture where the\n   argument is one of the names used in the BFD library. More\n   specifically one of the entires in bfd\/cpu-mips.c *\/\nOUTPUT_ARCH( \"riscv\" )\n\n\/*----------------------------------------------------------------------*\/\n\/* Sections                                                             *\/\n\/*----------------------------------------------------------------------*\/\n\nMEMORY\n{\n    rom (RX) : ORIGIN = 0x00000, LENGTH = 0x10000\n    ram (RW) : ORIGIN = 0x10000, LENGTH = 0x20000\n}\n\nSECTIONS\n{\n\n  \/* text: test code section *\/\n  . = 0x100;\n  .text 0x100 : ONLY_IF_RO\n  {\n    crt.o(.text)\n    *(.text*)\n  } > rom\n\n  \/* data segment *\/\n  .data : ONLY_IF_RW\n  {\n    *(.data)\n  } > ram\n\n  .sdata : ONLY_IF_RW\n  {\n    _gp = . + 0x800;\n    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n  } > ram\n\n  \/* bss segment *\/\n  .sbss : ONLY_IF_RW\n  {\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n  } > ram\n  .bss : { *(.bss) }\n\n  \/* thread-local data segment *\/\n  .tdata : ONLY_IF_RW\n  {\n    _tls_data = .;\n    crt.o(.tdata.begin)\n    *(.tdata)\n    crt.o(.tdata.end)\n  } > ram\n\n  .tbss : ONLY_IF_RW\n  {\n    *(.tbss)\n    crt.o(.tbss.end)\n  } > ram\n\n  \/* End of uninitalized data segement *\/\n  _end = .;\n}\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"89319cd72f8a0114465ab6a29b89ce73b3a982a4","subject":"esp_rom: remove functions which depend on sizeof(struct stat) and all their callers for esp32h2-beta2","message":"esp_rom: remove functions which depend on sizeof(struct stat) and all their callers for esp32h2-beta2\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32h2\/ld\/rev2\/esp32h2.rom.newlib.ld","new_file":"components\/esp_rom\/esp32h2\/ld\/rev2\/esp32h2.rom.newlib.ld","new_contents":"\/*\n * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\/* ROM function interface esp32h2.rom.newlib.ld for esp32h2\n *\n *\n * Generated from .\/target\/esp32h2\/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6\n *\n * Compatible with ROM where ECO version equal or greater to 0.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group newlib\n ***************************************\/\n\n\/* Functions *\/\nesp_rom_newlib_init_common_mutexes = 0x40000494;\nmemset = 0x40000498;\nmemcpy = 0x4000049c;\nmemmove = 0x400004a0;\nmemcmp = 0x400004a4;\nstrcpy = 0x400004a8;\nstrncpy = 0x400004ac;\nstrcmp = 0x400004b0;\nstrncmp = 0x400004b4;\nstrlen = 0x400004b8;\nstrstr = 0x400004bc;\nbzero = 0x400004c0;\nsbrk = 0x400004c8;\nisalnum = 0x400004cc;\nisalpha = 0x400004d0;\nisascii = 0x400004d4;\nisblank = 0x400004d8;\niscntrl = 0x400004dc;\nisdigit = 0x400004e0;\nislower = 0x400004e4;\nisgraph = 0x400004e8;\nisprint = 0x400004ec;\nispunct = 0x400004f0;\nisspace = 0x400004f4;\nisupper = 0x400004f8;\ntoupper = 0x400004fc;\ntolower = 0x40000500;\ntoascii = 0x40000504;\nmemccpy = 0x40000508;\nmemchr = 0x4000050c;\nmemrchr = 0x40000510;\nstrcasecmp = 0x40000514;\nstrcasestr = 0x40000518;\nstrcat = 0x4000051c;\nstrdup = 0x40000520;\nstrchr = 0x40000524;\nstrcspn = 0x40000528;\nstrcoll = 0x4000052c;\nstrlcat = 0x40000530;\nstrlcpy = 0x40000534;\nstrlwr = 0x40000538;\nstrncasecmp = 0x4000053c;\nstrncat = 0x40000540;\nstrndup = 0x40000544;\nstrnlen = 0x40000548;\nstrrchr = 0x4000054c;\nstrsep = 0x40000550;\nstrspn = 0x40000554;\nstrtok_r = 0x40000558;\nstrupr = 0x4000055c;\nlongjmp = 0x40000560;\nsetjmp = 0x40000564;\nabs = 0x40000568;\ndiv = 0x4000056c;\nlabs = 0x40000570;\nldiv = 0x40000574;\nqsort = 0x40000578;\nrand_r = 0x4000057c;\nrand = 0x40000580;\nsrand = 0x40000584;\nutoa = 0x40000588;\nitoa = 0x4000058c;\natoi = 0x40000590;\natol = 0x40000594;\nstrtol = 0x40000598;\nstrtoul = 0x4000059c;\nfflush = 0x400005a0;\n_fflush_r = 0x400005a4;\n_fwalk = 0x400005a8;\n_fwalk_reent = 0x400005ac;\n__swbuf_r = 0x400005b8;\n__swbuf = 0x400005bc;\n_strtod_l = 0x400005c4;\n_strtod_r = 0x400005c8;\nstrtod_l = 0x400005cc;\nstrtod = 0x400005d0;\nstrtof_l = 0x400005d4;\nstrtof = 0x400005d8;\n_strtol_r = 0x400005dc;\nstrtol_l = 0x400005e0;\n_strtoul_r = 0x400005e4;\nstrtoul_l = 0x400005e8;\n__match = 0x400005ec;\n__hexnan = 0x400005f0;\n__hexdig_fun = 0x400005f4;\n__gethex = 0x400005f8;\n_Balloc = 0x400005fc;\n_Bfree = 0x40000600;\n__multadd = 0x40000604;\n__s2b = 0x40000608;\n__hi0bits = 0x4000060c;\n__lo0bits = 0x40000610;\n__i2b = 0x40000614;\n__multiply = 0x40000618;\n__pow5mult = 0x4000061c;\n__lshift = 0x40000620;\n__mcmp = 0x40000624;\n__mdiff = 0x40000628;\n__ulp = 0x4000062c;\n__b2d = 0x40000630;\n__d2b = 0x40000634;\n__ratio = 0x40000638;\n_mprec_log10 = 0x4000063c;\n__copybits = 0x40000640;\n__any_on = 0x40000644;\nasctime = 0x40000648;\nasctime_r = 0x4000064c;\natof = 0x40000650;\natoff = 0x40000654;\n_dtoa_r = 0x40000658;\n_wctomb_r = 0x4000065c;\n__ascii_wctomb = 0x40000660;\n_mbtowc_r = 0x40000664;\n__ascii_mbtowc = 0x40000668;\nputs = 0x4000066c;\nputc = 0x40000670;\nputchar = 0x40000674;\nnan = 0x40000678;\nnanf = 0x4000067c;\n__errno = 0x40000680;\n\/* Data (.data, .bss, .rodata) *\/\nsyscall_table_ptr = 0x3fcdffd4;\n_global_impure_ptr = 0x3fcdffd0;\n","old_contents":"\/*\n * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\/* ROM function interface esp32h2.rom.newlib.ld for esp32h2\n *\n *\n * Generated from .\/target\/esp32h2\/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6\n *\n * Compatible with ROM where ECO version equal or greater to 0.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group newlib\n ***************************************\/\n\n\/* Functions *\/\nesp_rom_newlib_init_common_mutexes = 0x40000494;\nmemset = 0x40000498;\nmemcpy = 0x4000049c;\nmemmove = 0x400004a0;\nmemcmp = 0x400004a4;\nstrcpy = 0x400004a8;\nstrncpy = 0x400004ac;\nstrcmp = 0x400004b0;\nstrncmp = 0x400004b4;\nstrlen = 0x400004b8;\nstrstr = 0x400004bc;\nbzero = 0x400004c0;\n_isatty_r = 0x400004c4;\nsbrk = 0x400004c8;\nisalnum = 0x400004cc;\nisalpha = 0x400004d0;\nisascii = 0x400004d4;\nisblank = 0x400004d8;\niscntrl = 0x400004dc;\nisdigit = 0x400004e0;\nislower = 0x400004e4;\nisgraph = 0x400004e8;\nisprint = 0x400004ec;\nispunct = 0x400004f0;\nisspace = 0x400004f4;\nisupper = 0x400004f8;\ntoupper = 0x400004fc;\ntolower = 0x40000500;\ntoascii = 0x40000504;\nmemccpy = 0x40000508;\nmemchr = 0x4000050c;\nmemrchr = 0x40000510;\nstrcasecmp = 0x40000514;\nstrcasestr = 0x40000518;\nstrcat = 0x4000051c;\nstrdup = 0x40000520;\nstrchr = 0x40000524;\nstrcspn = 0x40000528;\nstrcoll = 0x4000052c;\nstrlcat = 0x40000530;\nstrlcpy = 0x40000534;\nstrlwr = 0x40000538;\nstrncasecmp = 0x4000053c;\nstrncat = 0x40000540;\nstrndup = 0x40000544;\nstrnlen = 0x40000548;\nstrrchr = 0x4000054c;\nstrsep = 0x40000550;\nstrspn = 0x40000554;\nstrtok_r = 0x40000558;\nstrupr = 0x4000055c;\nlongjmp = 0x40000560;\nsetjmp = 0x40000564;\nabs = 0x40000568;\ndiv = 0x4000056c;\nlabs = 0x40000570;\nldiv = 0x40000574;\nqsort = 0x40000578;\nrand_r = 0x4000057c;\nrand = 0x40000580;\nsrand = 0x40000584;\nutoa = 0x40000588;\nitoa = 0x4000058c;\natoi = 0x40000590;\natol = 0x40000594;\nstrtol = 0x40000598;\nstrtoul = 0x4000059c;\nfflush = 0x400005a0;\n_fflush_r = 0x400005a4;\n_fwalk = 0x400005a8;\n_fwalk_reent = 0x400005ac;\n__smakebuf_r = 0x400005b0;\n__swhatbuf_r = 0x400005b4;\n__swbuf_r = 0x400005b8;\n__swbuf = 0x400005bc;\n__swsetup_r = 0x400005c0;\n_strtod_l = 0x400005c4;\n_strtod_r = 0x400005c8;\nstrtod_l = 0x400005cc;\nstrtod = 0x400005d0;\nstrtof_l = 0x400005d4;\nstrtof = 0x400005d8;\n_strtol_r = 0x400005dc;\nstrtol_l = 0x400005e0;\n_strtoul_r = 0x400005e4;\nstrtoul_l = 0x400005e8;\n__match = 0x400005ec;\n__hexnan = 0x400005f0;\n__hexdig_fun = 0x400005f4;\n__gethex = 0x400005f8;\n_Balloc = 0x400005fc;\n_Bfree = 0x40000600;\n__multadd = 0x40000604;\n__s2b = 0x40000608;\n__hi0bits = 0x4000060c;\n__lo0bits = 0x40000610;\n__i2b = 0x40000614;\n__multiply = 0x40000618;\n__pow5mult = 0x4000061c;\n__lshift = 0x40000620;\n__mcmp = 0x40000624;\n__mdiff = 0x40000628;\n__ulp = 0x4000062c;\n__b2d = 0x40000630;\n__d2b = 0x40000634;\n__ratio = 0x40000638;\n_mprec_log10 = 0x4000063c;\n__copybits = 0x40000640;\n__any_on = 0x40000644;\nasctime = 0x40000648;\nasctime_r = 0x4000064c;\natof = 0x40000650;\natoff = 0x40000654;\n_dtoa_r = 0x40000658;\n_wctomb_r = 0x4000065c;\n__ascii_wctomb = 0x40000660;\n_mbtowc_r = 0x40000664;\n__ascii_mbtowc = 0x40000668;\nputs = 0x4000066c;\nputc = 0x40000670;\nputchar = 0x40000674;\nnan = 0x40000678;\nnanf = 0x4000067c;\n__errno = 0x40000680;\n\/* Data (.data, .bss, .rodata) *\/\nsyscall_table_ptr = 0x3fcdffd4;\n_global_impure_ptr = 0x3fcdffd0;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6ae038ca277da1dd547ad6be53b98546930da372","subject":"esp32: linker clean up to support BT","message":"esp32: linker clean up to support BT\n\nBT support requires lots of PROVIDE calls that  cannot\nbe added into this linker file. All necessary includes\nwere moved into hal module to proper handled as needed.\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *  - Reserve memory region for BT controller library from ROM\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x30000\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n#if defined(CONFIG_NET_SOCKETS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_socket_register);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(settings_handler_static);\n    . = ALIGN(4);\n#endif\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\n\/* Global symbols required for espressif hal build *\/\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\nPROVIDE ( phy_get_romfuncs = 0x40004100 );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );\nPROVIDE ( g_rom_flashchip = 0x3ffae270 );\nPROVIDE ( SPI0 = 0x3ff43000 );\nPROVIDE ( SPI1 = 0x3ff42fff );\nPROVIDE ( SPI2 = 0x3ff64fff );\nPROVIDE ( SPI3 = 0x3ff65fff );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( esp32_rom_ets_printf = ets_printf );\nPROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );\nPROVIDE ( TIMERG0 = 0x3ff5F000 );\nPROVIDE ( TIMERG1 = 0x3ff60000 );\n\n\/* __udivdi3 is exported using assignment, which declares strong symbols *\/\n__udivdi3 = 0x4000cff8;\n__umoddi3 = 0x4000d280;\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *  - Reserve memory region for BT controller library from ROM\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x30000\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n#if defined(CONFIG_NET_SOCKETS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_socket_register);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(settings_handler_static);\n    . = ALIGN(4);\n#endif\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a8ece584e5907a05c3aff42f159f346901c850b4","subject":"mro ctrl-zero-h7-oem:Properly configure BDMA","message":"mro ctrl-zero-h7-oem:Properly configure BDMA\n","repos":"acfloria\/Firmware,acfloria\/Firmware,acfloria\/Firmware,acfloria\/Firmware,acfloria\/Firmware,acfloria\/Firmware,acfloria\/Firmware","old_file":"boards\/mro\/ctrl-zero-h7-oem\/nuttx-config\/scripts\/script.ld","new_file":"boards\/mro\/ctrl-zero-h7-oem\/nuttx-config\/scripts\/script.ld","new_contents":"\/****************************************************************************\n * scripts\/script.ld\n *\n *   Copyright (C) 2021 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The board uses an STM32H743XIH6 and has 2048Kb of main FLASH memory.\n * The flash memory is partitioned into a User Flash memory and a System\n * Flash memory. Each of these memories has two banks:\n *\n *   1) User Flash memory:\n *\n *      Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each\n *      Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each\n *\n *   2) System Flash memory:\n *\n *      Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector\n *      Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector\n *\n *   3) User option bytes for user configuration, only in Bank 1.\n *\n * In the STM32H743II, two different boot spaces can be selected through\n * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and\n * BOOT_ADD1 option bytes:\n *\n *   1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].\n *      ST programmed value: Flash memory at 0x0800:0000\n *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].\n *      ST programmed value: System bootloader at 0x1FF0:0000\n *\n * There's a switch on board, the BOOT0 pin is at ground so by default,\n * the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is\n * drepresed, then the boot will be from 0x1FF0:0000\n *\n * The STM32H743ZI also has 1024Kb of data SRAM.\n * SRAM is split up into several blocks and into three power domains:\n *\n *   1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with\n *      0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus\n *\n *      1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000\n *\n *           The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit\n *           DTCM ports. The DTCM-RAM could be used for critical real-time\n *           data, such as interrupt service routines or stack \/ heap memory.\n *           Both DTCM-RAMs can be used in parallel (for load\/store operations)\n *           thanks to the Cortex-M7 dual issue capability.\n *\n *      1.2)  64Kb of ITCM-RAM beginning at address 0x0000:0000\n *\n *           This RAM is connected to ITCM 64-bit interface designed for\n *           execution of critical real-times routines by the CPU.\n *\n *   2) AXI SRAM (D1 domain) accessible by all system masters except BDMA\n *      through D1 domain AXI bus matrix\n *\n *      2.1) 512Kb of SRAM beginning at address 0x2400:0000\n *\n *   3) AHB SRAM (D2 domain) accessible by all system masters except BDMA\n *      through D2 domain AHB bus matrix\n *\n *      3.1) 128Kb of SRAM1 beginning at address 0x3000:0000\n *      3.2) 128Kb of SRAM2 beginning at address 0x3002:0000\n *      3.3)  32Kb of SRAM3 beginning at address 0x3004:0000\n *\n *      SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000\n *\n *   4) AHB SRAM (D3 domain) accessible by most of system masters\n *      through D3 domain AHB bus matrix\n *\n *      4.1)  64Kb of SRAM4 beginning at address 0x3800:0000\n *      4.1)   4Kb of backup RAM beginning at address 0x3880:0000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0800:0000 address range.\n *\/\n\nMEMORY\n{\n\tITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K\n\tFLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K\n\n\tDTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K\n\tDTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K\n\tAXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K \/* D1 domain AXI bus *\/\n\tSRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K \/* D2 domain AHB bus *\/\n\tSRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K \/* D2 domain AHB bus *\/\n\tSRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K \/* D2 domain AHB bus *\/\n\tSRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K \/* D3 domain *\/\n\tBKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K\n}\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nENTRY(_stext)\n\n\/*\n * Ensure that abort() is present in the final object.  The exception handling\n * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).\n *\/\nEXTERN(abort)\nEXTERN(_bootdelay_signature)\n\nSECTIONS\n{\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t. = ALIGN(32);\n\t\t\/*\n\t\tThis signature provides the bootloader with a way to delay booting\n\t\t*\/\n\t\t_bootdelay_signature = ABSOLUTE(.);\n\t\tFILL(0xffecc2925d7d05c5)\n\t\t. += 8;\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\n\t} > FLASH\n\n\t\/*\n\t * Init functions (static constructors and the like)\n\t *\/\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\tKEEP(*(.init_array .init_array.*))\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH\n\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > AXI_SRAM AT > FLASH\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > AXI_SRAM\n\n\t\/* Emit the the D3 power domain section for locating BDMA data *\/\n\t.sram4 (NOLOAD) :\n\t{\n\t} > SRAM4\n\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.ramfunc : {\n\t\t_sramfuncs = .;\n\t\t*(.ramfunc  .ramfunc.*)\n\t\t. = ALIGN(4);\n\t\t_eramfuncs = .;\n\t} > ITCM_RAM AT > FLASH\n\n\t_framfuncs = LOADADDR(.ramfunc);\n}\n","old_contents":"\/****************************************************************************\n * scripts\/script.ld\n *\n *   Copyright (C) 2021 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The board uses an STM32H743XIH6 and has 2048Kb of main FLASH memory.\n * The flash memory is partitioned into a User Flash memory and a System\n * Flash memory. Each of these memories has two banks:\n *\n *   1) User Flash memory:\n *\n *      Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each\n *      Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each\n *\n *   2) System Flash memory:\n *\n *      Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector\n *      Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector\n *\n *   3) User option bytes for user configuration, only in Bank 1.\n *\n * In the STM32H743II, two different boot spaces can be selected through\n * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and\n * BOOT_ADD1 option bytes:\n *\n *   1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].\n *      ST programmed value: Flash memory at 0x0800:0000\n *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].\n *      ST programmed value: System bootloader at 0x1FF0:0000\n *\n * There's a switch on board, the BOOT0 pin is at ground so by default,\n * the STM32 will boot to address 0x0800:0000 in FLASH unless the switch is\n * drepresed, then the boot will be from 0x1FF0:0000\n *\n * The STM32H743ZI also has 1024Kb of data SRAM.\n * SRAM is split up into several blocks and into three power domains:\n *\n *   1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with\n *      0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus\n *\n *      1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000\n *\n *           The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit\n *           DTCM ports. The DTCM-RAM could be used for critical real-time\n *           data, such as interrupt service routines or stack \/ heap memory.\n *           Both DTCM-RAMs can be used in parallel (for load\/store operations)\n *           thanks to the Cortex-M7 dual issue capability.\n *\n *      1.2)  64Kb of ITCM-RAM beginning at address 0x0000:0000\n *\n *           This RAM is connected to ITCM 64-bit interface designed for\n *           execution of critical real-times routines by the CPU.\n *\n *   2) AXI SRAM (D1 domain) accessible by all system masters except BDMA\n *      through D1 domain AXI bus matrix\n *\n *      2.1) 512Kb of SRAM beginning at address 0x2400:0000\n *\n *   3) AHB SRAM (D2 domain) accessible by all system masters except BDMA\n *      through D2 domain AHB bus matrix\n *\n *      3.1) 128Kb of SRAM1 beginning at address 0x3000:0000\n *      3.2) 128Kb of SRAM2 beginning at address 0x3002:0000\n *      3.3)  32Kb of SRAM3 beginning at address 0x3004:0000\n *\n *      SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000\n *\n *   4) AHB SRAM (D3 domain) accessible by most of system masters\n *      through D3 domain AHB bus matrix\n *\n *      4.1)  64Kb of SRAM4 beginning at address 0x3800:0000\n *      4.1)   4Kb of backup RAM beginning at address 0x3880:0000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0800:0000 address range.\n *\/\n\nMEMORY\n{\n\tITCM_RAM  (rwx) : ORIGIN = 0x00000000, LENGTH =   64K\n\tFLASH      (rx) : ORIGIN = 0x08020000, LENGTH = 1920K\n\n\tDTCM1_RAM (rwx) : ORIGIN = 0x20000000, LENGTH =   64K\n\tDTCM2_RAM (rwx) : ORIGIN = 0x20010000, LENGTH =   64K\n\tAXI_SRAM  (rwx) : ORIGIN = 0x24000000, LENGTH =  512K \/* D1 domain AXI bus *\/\n\tSRAM1     (rwx) : ORIGIN = 0x30000000, LENGTH =  128K \/* D2 domain AHB bus *\/\n\tSRAM2     (rwx) : ORIGIN = 0x30020000, LENGTH =  128K \/* D2 domain AHB bus *\/\n\tSRAM3     (rwx) : ORIGIN = 0x30040000, LENGTH =   32K \/* D2 domain AHB bus *\/\n\tSRAM4     (rwx) : ORIGIN = 0x38000000, LENGTH =   64K \/* D3 domain *\/\n\tBKPRAM    (rwx) : ORIGIN = 0x38800000, LENGTH =    4K\n}\n\nOUTPUT_ARCH(arm)\nEXTERN(_vectors)\nENTRY(_stext)\n\n\/*\n * Ensure that abort() is present in the final object.  The exception handling\n * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).\n *\/\nEXTERN(abort)\nEXTERN(_bootdelay_signature)\n\nSECTIONS\n{\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t. = ALIGN(32);\n\t\t\/*\n\t\tThis signature provides the bootloader with a way to delay booting\n\t\t*\/\n\t\t_bootdelay_signature = ABSOLUTE(.);\n\t\tFILL(0xffecc2925d7d05c5)\n\t\t. += 8;\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\n\t} > FLASH\n\n\t\/*\n\t * Init functions (static constructors and the like)\n\t *\/\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\tKEEP(*(.init_array .init_array.*))\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH\n\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > AXI_SRAM AT > FLASH\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > AXI_SRAM\n\n\t\/* Emit the the D3 power domain section for locating BDMA data *\/\n\t.SRAM4 (NOLOAD) :\n\t{\n\t} > SRAM4\n\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.ramfunc : {\n\t\t_sramfuncs = .;\n\t\t*(.ramfunc  .ramfunc.*)\n\t\t. = ALIGN(4);\n\t\t_eramfuncs = .;\n\t} > ITCM_RAM AT > FLASH\n\n\t_framfuncs = LOADADDR(.ramfunc);\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"9ddfec44917e82fb7c1c10d0644ec354f9f2b346","subject":"Update esp8266 arduino linker definition","message":"Update esp8266 arduino linker definition\n","repos":"zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder","old_file":"package\/esp8266\/arduino\/eagle.app.v6.common.ld","new_file":"package\/esp8266\/arduino\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(app_entry)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nEXTERN(core_version)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4); \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* all functional callers are placed in IRAM (including SPI\/IRQ callbacks\/etc) here *\/\n    *(.text._ZNKSt8functionIF*EE*) \/* std::function<any(...)>::operator()() const *\/\n\n    \/* These must be located in internal RAM to prevent far accesses to literal data.\n     *  All of the following libraries are distributed in binary form, so we cannot\n     *  change the compilation options to allow for far accesses to data. *\/\n    *libgcc.a:_*.o(.literal .text .literal.* .text.*)\n    *libmain.a:(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libnet80211.a:wl_chm.o(.text)\n\n    \/* Arduino necessities *\/\n    *libarduino_core.a:*cont.o(.literal* .text*)\n\n    *(.gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n\n    \/* Any compilation units that request to be located in interal RAM *\/\n    *(.iram.literal)\n    *(.iram.text .iram.text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.a(.literal*)\n    *.o(.literal*)\n    *.a(.text*)\n    *.o(.text*)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom0.text* .irom.text .irom.text.*)\n    *libarduino_core.a:*umm_malloc.o(.literal* .text*)\n\n    \/* __FUNCTION__ locals *\/\n    *(.rodata._ZZ*__FUNCTION__)\n    *(.rodata._ZZ*__PRETTY_FUNCTION__)\n    *(.rodata._ZZ*__func__)\n\n    \/* std::* exception strings, in their own section to allow string coalescing *\/\n    *(.irom.exceptiontext)\n\n    \/* c++ typeof IDs, etc. *\/\n    *(.rodata._ZTIN* .rodata._ZTSN10* .rodata._ZTISt* .rodata._ZTSSt*)\n\n    \/* Fundamental type info *\/\n    *(.rodata._ZTIPKc .rodata._ZTIc .rodata._ZTIv .rodata._ZTSv .rodata._ZTSc .rodata._ZTSPKc .rodata._ZTSi .rodata._ZTIi)\n\n    . = ALIGN(4);\n    *(.gcc_except_table .gcc_except_table.*)\n    . = ALIGN(4);\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;  \/* Add a 0 entry to terminate the list *\/\n\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .irom0.other : ALIGN(4) SUBALIGN(4)\n  {\n    _irom0_other_start = ABSOLUTE(.);\n    . = ALIGN (4);\n    *.bin.o(*)\n    . = ALIGN (4);\n    _irom0_other_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(app_entry)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nEXTERN(core_version)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n\n    . = ALIGN(4);\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;  \/* Add a 0 entry to terminate the list *\/\n\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n     _UserExceptionVector_literal_start = ABSOLUTE(.);\n     *(.UserExceptionVector.literal)\n     _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n\n    \/* These must be located in internal RAM to prevent far accesses to literal data.\n     *  All of the following libraries are distributed in binary form, so we cannot\n     *  change the compilation options to allow for far accesses to data. *\/\n    *libgcc.a:_*.o(.literal .text .literal.* .text.*)\n    *libmain.a:(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libnet80211.a:wl_chm.o(.text)\n\n    \/* Arduino necessities *\/\n    *libarduino_core.a:*cont.o(.literal* .text*)\n\n    *(.gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n\n    \/* all functional callers are placed in IRAM (including SPI\/IRQ callbacks\/etc) here *\/\n    *(.text._ZNKSt8functionIF*EE*) \/* std::function<any(...)>::operator()() const *\/\n\n    \/* Any compilation units that request to be located in interal RAM *\/\n    *(.iram.literal)\n    *(.iram.text .iram.text.*)\n\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *.a(.literal*)\n    *.o(.literal*)\n    *.a(.text*)\n    *.o(.text*)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom0.text* .irom.text .irom.text.*)\n\n    \/* __FUNCTION__ locals *\/\n    *(.rodata._ZZ*__FUNCTION__)\n    *(.rodata._ZZ*__PRETTY_FUNCTION__)\n    *(.rodata._ZZ*__func__)\n\n    \/* std::* exception strings, in their own section to allow string coalescing *\/\n    *(.irom.exceptiontext)\n\n    \/* c++ typeof IDs, etc. *\/\n    *(.rodata._ZTIN* .rodata._ZTSN10* .rodata._ZTISt* .rodata._ZTSSt*)\n\n    \/* Fundamental type info *\/\n    *(.rodata._ZTIPKc .rodata._ZTIc .rodata._ZTIv .rodata._ZTSv .rodata._ZTSc .rodata._ZTSPKc .rodata._ZTSi .rodata._ZTIi)\n\n    . = ALIGN(4);\n    *(.gcc_except_table .gcc_except_table.*)\n\n    . = ALIGN (4);\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .irom0.other : ALIGN(4) SUBALIGN(4)\n  {\n    _irom0_other_start = ABSOLUTE(.);\n    *.bin.o(*)\n    . = ALIGN (4);\n    _irom0_other_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2859c7ebd162dd7bd6be3a28ee6f5d7f0df43c0c","subject":"fix the bug that wifi connect fail","message":"fix the bug that wifi connect fail\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32c3\/ld\/esp32c3.rom.ld","new_file":"components\/esp_rom\/esp32c3\/ld\/esp32c3.rom.ld","new_contents":"\/* ROM function interface esp32c3.rom.ld for esp32c3\n *\n *\n * Generated from .\/interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208\n *\n * Compatible with ROM where ECO version equal or greater to 0.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\njtag_cpu_reset_happened = 0x40000020;\nrtc_get_wakeup_cause = 0x40000024;\nrtc_boot_control = 0x40000028;\nrtc_select_apb_bridge = 0x4000002c;\nrtc_unhold_all_pads = 0x40000030;\nset_rtc_memory_crc = 0x40000034;\ncacl_rtc_memory_crc = 0x40000038;\nets_is_print_boot = 0x4000003c;\nets_printf = 0x40000040;\nets_install_putc1 = 0x40000044;\nets_install_uart_printf = 0x40000048;\nets_install_putc2 = 0x4000004c;\nPROVIDE( ets_delay_us = 0x40000050 );\nets_get_stack_info = 0x40000054;\nets_install_lock = 0x40000058;\nets_backup_dma_copy = 0x4000005c;\nets_apb_backup_init_lock_func = 0x40000060;\nUartRxString = 0x40000064;\nuart_tx_one_char = 0x40000068;\nuart_tx_one_char2 = 0x4000006c;\nuart_rx_one_char = 0x40000070;\nuart_rx_one_char_block = 0x40000074;\nuart_rx_readbuff = 0x40000078;\nuartAttach = 0x4000007c;\nuart_tx_flush = 0x40000080;\nuart_tx_wait_idle = 0x40000084;\nuart_div_modify = 0x40000088;\nmultofup = 0x4000008c;\nsoftware_reset = 0x40000090;\nsoftware_reset_cpu = 0x40000094;\nassist_debug_clock_enable = 0x40000098;\nassist_debug_record_enable = 0x4000009c;\nclear_super_wdt_reset_flag = 0x400000a0;\ndisable_default_watchdog = 0x400000a4;\nsend_packet = 0x400000a8;\nrecv_packet = 0x400000ac;\nGetUartDevice = 0x400000b0;\nUartDwnLdProc = 0x400000b4;\nUart_Init = 0x400000b8;\nets_set_user_start = 0x400000bc;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff1fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000c0;\nmz_crc32 = 0x400000c4;\nmz_free = 0x400000c8;\ntdefl_compress = 0x400000cc;\ntdefl_compress_buffer = 0x400000d0;\ntdefl_compress_mem_to_heap = 0x400000d4;\ntdefl_compress_mem_to_mem = 0x400000d8;\ntdefl_compress_mem_to_output = 0x400000dc;\ntdefl_get_adler32 = 0x400000e0;\ntdefl_get_prev_return_status = 0x400000e4;\ntdefl_init = 0x400000e8;\ntdefl_write_image_to_png_file_in_memory = 0x400000ec;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000f0;\ntinfl_decompress = 0x400000f4;\ntinfl_decompress_mem_to_callback = 0x400000f8;\ntinfl_decompress_mem_to_heap = 0x400000fc;\ntinfl_decompress_mem_to_mem = 0x40000100;\n\n\n\/***************************************\n Group tjpgd\n ***************************************\/\n\n\/* Functions *\/\njd_prepare = 0x40000104;\njd_decomp = 0x40000108;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x4000010c );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x40000110 );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000114 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000118 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000011c );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x40000120 );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000124 );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x40000128 );\nPROVIDE( esp_rom_spiflash_write = 0x4000012c );\nPROVIDE( esp_rom_spiflash_read = 0x40000130 );\nPROVIDE( esp_rom_spiflash_config_param = 0x40000134 );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000138 );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x4000013c );\nPROVIDE( esp_rom_spiflash_unlock = 0x40000140 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000144 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x40000148 );\nPROVIDE( esp_rom_spi_flash_update_id = 0x4000014c );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000150 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000154 );\nPROVIDE( esp_rom_spiflash_read_status = 0x40000158 );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x4000015c );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000160 );\nPROVIDE( esp_rom_spiflash_attach = 0x40000164 );\nPROVIDE( spi_flash_get_chip_size = 0x40000168 );\nPROVIDE( spi_flash_guard_set = 0x4000016c );\nPROVIDE( spi_flash_guard_get = 0x40000170 );\nPROVIDE( spi_flash_write_config_set = 0x40000174 );\nPROVIDE( spi_flash_write_config_get = 0x40000178 );\nPROVIDE( spi_flash_safe_write_address_func_set = 0x4000017c );\nPROVIDE( spi_flash_unlock = 0x40000180 );\nPROVIDE( spi_flash_erase_range = 0x40000184 );\nPROVIDE( spi_flash_erase_sector = 0x40000188 );\nPROVIDE( spi_flash_write = 0x4000018c );\nPROVIDE( spi_flash_read = 0x40000190 );\nPROVIDE( spi_flash_write_encrypted = 0x40000194 );\nPROVIDE( spi_flash_read_encrypted = 0x40000198 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x4000019c );\nPROVIDE( spi_flash_mmap_page_num_init = 0x400001a0 );\nPROVIDE( spi_flash_mmap = 0x400001a4 );\nPROVIDE( spi_flash_mmap_pages = 0x400001a8 );\nPROVIDE( spi_flash_munmap = 0x400001ac );\nPROVIDE( spi_flash_mmap_dump = 0x400001b0 );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001b4 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001b8 );\nPROVIDE( spi_flash_cache2phys = 0x400001bc );\nPROVIDE( spi_flash_phys2cache = 0x400001c0 );\nPROVIDE( spi_flash_disable_cache = 0x400001c4 );\nPROVIDE( spi_flash_restore_cache = 0x400001c8 );\nPROVIDE( spi_flash_cache_enabled = 0x400001cc );\nPROVIDE( spi_flash_enable_cache = 0x400001d0 );\nPROVIDE( spi_cache_mode_switch = 0x400001d4 );\nPROVIDE( spi_common_set_dummy_output = 0x400001d8 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001dc );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001e0 );\nPROVIDE( SPIEraseArea = 0x400001e4 );\nPROVIDE( SPILock = 0x400001e8 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001ec );\nPROVIDE( SPI_Common_Command = 0x400001f0 );\nPROVIDE( SPI_WakeUp = 0x400001f4 );\nPROVIDE( SPI_block_erase = 0x400001f8 );\nPROVIDE( SPI_chip_erase = 0x400001fc );\nPROVIDE( SPI_init = 0x40000200 );\nPROVIDE( SPI_page_program = 0x40000204 );\nPROVIDE( SPI_read_data = 0x40000208 );\nPROVIDE( SPI_sector_erase = 0x4000020c );\nPROVIDE( SPI_write_enable = 0x40000210 );\nPROVIDE( SelectSpiFunction = 0x40000214 );\nPROVIDE( SetSpiDrvs = 0x40000218 );\nPROVIDE( Wait_SPI_Idle = 0x4000021c );\nPROVIDE( spi_dummy_len_fix = 0x40000220 );\nPROVIDE( Disable_QMode = 0x40000224 );\nPROVIDE( Enable_QMode = 0x40000228 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group spi_flash_hal\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x4000022c );\nPROVIDE( spi_flash_hal_device_config = 0x40000230 );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000234 );\nPROVIDE( spi_flash_hal_common_command = 0x40000238 );\nPROVIDE( spi_flash_hal_read = 0x4000023c );\nPROVIDE( spi_flash_hal_erase_chip = 0x40000240 );\nPROVIDE( spi_flash_hal_erase_sector = 0x40000244 );\nPROVIDE( spi_flash_hal_erase_block = 0x40000248 );\nPROVIDE( spi_flash_hal_program_page = 0x4000024c );\nPROVIDE( spi_flash_hal_set_write_protect = 0x40000250 );\nPROVIDE( spi_flash_hal_host_idle = 0x40000254 );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x40000258 );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x4000025c );\nPROVIDE( spi_flash_chip_generic_write = 0x40000260 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000264 );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000268 );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x4000026c );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000270 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x40000274 );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x40000278 );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x4000027c );\nPROVIDE( spi_flash_chip_generic_page_program = 0x40000280 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000284 );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000288 );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x4000028c );\nPROVIDE( spi_flash_chip_generic_yield = 0x40000290 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x40000294 );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x40000298 );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x4000029c );\nPROVIDE( spi_flash_chip_generic_read = 0x400002a0 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400002a4 );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400002a8 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400002ac );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400002b0 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400002b4 );\nPROVIDE( spi_flash_common_set_io_mode = 0x400002b8 );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400002bc );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400002c0 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400002c4 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400002c8 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffec );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x400002cc );\nPROVIDE( memspi_host_read_status_hs = 0x400002d0 );\nPROVIDE( memspi_host_flush_cache = 0x400002d4 );\nPROVIDE( memspi_host_erase_chip = 0x400002d8 );\nPROVIDE( memspi_host_erase_sector = 0x400002dc );\nPROVIDE( memspi_host_erase_block = 0x400002e0 );\nPROVIDE( memspi_host_program_page = 0x400002e4 );\nPROVIDE( memspi_host_read = 0x400002e8 );\nPROVIDE( memspi_host_set_write_protect = 0x400002ec );\nPROVIDE( memspi_host_set_max_read_len = 0x400002f0 );\nPROVIDE( memspi_host_read_data_slicer = 0x400002f4 );\nPROVIDE( memspi_host_write_data_slicer = 0x400002f8 );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x400002fc );\nPROVIDE( esp_flash_read_id = 0x40000300 );\nPROVIDE( esp_flash_get_size = 0x40000304 );\nPROVIDE( esp_flash_erase_chip = 0x40000308 );\nPROVIDE( esp_flash_erase_region = 0x4000030c );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000310 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000314 );\nPROVIDE( esp_flash_get_protectable_regions = 0x40000318 );\nPROVIDE( esp_flash_get_protected_region = 0x4000031c );\nPROVIDE( esp_flash_set_protected_region = 0x40000320 );\nPROVIDE( esp_flash_read = 0x40000324 );\nPROVIDE( esp_flash_write = 0x40000328 );\nPROVIDE( esp_flash_write_encrypted = 0x4000032c );\nPROVIDE( esp_flash_read_encrypted = 0x40000330 );\nPROVIDE( esp_flash_get_io_mode = 0x40000334 );\nPROVIDE( esp_flash_set_io_mode = 0x40000338 );\nPROVIDE( spi_flash_boot_attach = 0x4000033c );\nPROVIDE( spi_flash_dump_counters = 0x40000340 );\nPROVIDE( spi_flash_get_counters = 0x40000344 );\nPROVIDE( spi_flash_op_counters_config = 0x40000348 );\nPROVIDE( spi_flash_reset_counters = 0x4000034c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe8 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffe4 );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400004b0 );\nPROVIDE( Cache_Get_Mode = 0x400004b4 );\nPROVIDE( Cache_Address_Through_IBus = 0x400004b8 );\nPROVIDE( Cache_Address_Through_DBus = 0x400004bc );\nPROVIDE( Cache_Set_Default_Mode = 0x400004c0 );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400004c4 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400004c8 );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x400004cc );\nPROVIDE( Cache_Op_Addr = 0x400004d0 );\nPROVIDE( Cache_Invalidate_Addr = 0x400004d4 );\nPROVIDE( Cache_Invalidate_ICache_All = 0x400004d8 );\nPROVIDE( Cache_Mask_All = 0x400004dc );\nPROVIDE( Cache_UnMask_Dram0 = 0x400004e0 );\nPROVIDE( Cache_Suspend_ICache_Autoload = 0x400004e4 );\nPROVIDE( Cache_Resume_ICache_Autoload = 0x400004e8 );\nPROVIDE( Cache_Start_ICache_Preload = 0x400004ec );\nPROVIDE( Cache_ICache_Preload_Done = 0x400004f0 );\nPROVIDE( Cache_End_ICache_Preload = 0x400004f4 );\nPROVIDE( Cache_Config_ICache_Autoload = 0x400004f8 );\nPROVIDE( Cache_Enable_ICache_Autoload = 0x400004fc );\nPROVIDE( Cache_Disable_ICache_Autoload = 0x40000500 );\nPROVIDE( Cache_Enable_ICache_PreLock = 0x40000504 );\nPROVIDE( Cache_Disable_ICache_PreLock = 0x40000508 );\nPROVIDE( Cache_Lock_ICache_Items = 0x4000050c );\nPROVIDE( Cache_Unlock_ICache_Items = 0x40000510 );\nPROVIDE( Cache_Lock_Addr = 0x40000514 );\nPROVIDE( Cache_Unlock_Addr = 0x40000518 );\nPROVIDE( Cache_Disable_ICache = 0x4000051c );\nPROVIDE( Cache_Enable_ICache = 0x40000520 );\nPROVIDE( Cache_Suspend_ICache = 0x40000524 );\nPROVIDE( Cache_Resume_ICache = 0x40000528 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x4000052c );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x40000530 );\nPROVIDE( Cache_Pms_Lock = 0x40000534 );\nPROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000538 );\nPROVIDE( Cache_Ibus_Pms_Set_Attr = 0x4000053c );\nPROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000540 );\nPROVIDE( Cache_Dbus_Pms_Set_Attr = 0x40000544 );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000548 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x4000054c );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x40000550 );\nPROVIDE( Cache_Owner_Init = 0x40000554 );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000558 );\nPROVIDE( Cache_MMU_Init = 0x4000055c );\nPROVIDE( Cache_Ibus_MMU_Set = 0x40000560 );\nPROVIDE( Cache_Dbus_MMU_Set = 0x40000564 );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000568 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x4000056c );\nPROVIDE( Cache_Get_Virtual_Addr = 0x40000570 );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x40000574 );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000578 );\nPROVIDE( Cache_Get_Memory_value = 0x4000057c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd8 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd4 );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x40000580;\nets_get_cpu_frequency = 0x40000584;\nets_update_cpu_frequency = 0x40000588;\nets_get_printf_channel = 0x4000058c;\nets_get_xtal_div = 0x40000590;\nets_set_xtal_div = 0x40000594;\nets_get_xtal_freq = 0x40000598;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x4000059c;\ngpio_matrix_in = 0x400005a0;\ngpio_matrix_out = 0x400005a4;\ngpio_output_disable = 0x400005a8;\ngpio_output_enable = 0x400005ac;\ngpio_output_set = 0x400005b0;\ngpio_pad_hold = 0x400005b4;\ngpio_pad_input_disable = 0x400005b8;\ngpio_pad_input_enable = 0x400005bc;\ngpio_pad_pulldown = 0x400005c0;\ngpio_pad_pullup = 0x400005c4;\ngpio_pad_select_gpio = 0x400005c8;\ngpio_pad_set_drv = 0x400005cc;\ngpio_pad_unhold = 0x400005d0;\ngpio_pin_wakeup_disable = 0x400005d4;\ngpio_pin_wakeup_enable = 0x400005d8;\ngpio_bypass_matrix_in = 0x400005dc;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400005e0;\nesprv_intc_int_set_threshold = 0x400005e4;\nesprv_intc_int_enable = 0x400005e8;\nesprv_intc_int_disable = 0x400005ec;\nesprv_intc_int_set_type = 0x400005f0;\nintr_matrix_set = 0x400005f4;\nets_intr_lock = 0x400005f8;\nets_intr_unlock = 0x400005fc;\nPROVIDE( intr_handler_set = 0x40000600 );\nets_isr_attach = 0x40000604;\nets_isr_mask = 0x40000608;\nets_isr_unmask = 0x4000060c;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\nmd5_vector = 0x40000610;\nMD5Init = 0x40000614;\nMD5Update = 0x40000618;\nMD5Final = 0x4000061c;\nhmac_md5_vector = 0x40000620;\nhmac_md5 = 0x40000624;\ncrc32_le = 0x40000628;\ncrc32_be = 0x4000062c;\ncrc16_le = 0x40000630;\ncrc16_be = 0x40000634;\ncrc8_le = 0x40000638;\ncrc8_be = 0x4000063c;\nesp_crc8 = 0x40000640;\nets_sha_enable = 0x40000644;\nets_sha_disable = 0x40000648;\nets_sha_get_state = 0x4000064c;\nets_sha_init = 0x40000650;\nets_sha_process = 0x40000654;\nets_sha_starts = 0x40000658;\nets_sha_update = 0x4000065c;\nets_sha_finish = 0x40000660;\nets_sha_clone = 0x40000664;\nets_hmac_enable = 0x40000668;\nets_hmac_disable = 0x4000066c;\nets_hmac_calculate_message = 0x40000670;\nets_hmac_calculate_downstream = 0x40000674;\nets_hmac_invalidate_downstream = 0x40000678;\nets_jtag_enable_temporarily = 0x4000067c;\nets_aes_enable = 0x40000680;\nets_aes_disable = 0x40000684;\nets_aes_setkey = 0x40000688;\nets_aes_block = 0x4000068c;\nets_bigint_enable = 0x40000690;\nets_bigint_disable = 0x40000694;\nets_bigint_multiply = 0x40000698;\nets_bigint_modmult = 0x4000069c;\nets_bigint_modexp = 0x400006a0;\nets_bigint_wait_finish = 0x400006a4;\nets_bigint_getz = 0x400006a8;\nets_ds_enable = 0x400006ac;\nets_ds_disable = 0x400006b0;\nets_ds_start_sign = 0x400006b4;\nets_ds_is_busy = 0x400006b8;\nets_ds_finish_sign = 0x400006bc;\nets_ds_encrypt_params = 0x400006c0;\nets_aes_setkey_dec = 0x400006c4;\nets_aes_setkey_enc = 0x400006c8;\nets_mgf1_sha256 = 0x400006cc;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x400006d0;\nets_efuse_program = 0x400006d4;\nets_efuse_clear_program_registers = 0x400006d8;\nets_efuse_write_key = 0x400006dc;\nets_efuse_get_read_register_address = 0x400006e0;\nets_efuse_get_key_purpose = 0x400006e4;\nets_efuse_key_block_unused = 0x400006e8;\nets_efuse_find_unused_key_block = 0x400006ec;\nets_efuse_rs_calculate = 0x400006f0;\nets_efuse_count_unused_key_blocks = 0x400006f4;\nets_efuse_secure_boot_enabled = 0x400006f8;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x400006fc;\nets_efuse_cache_encryption_enabled = 0x40000700;\nets_efuse_download_modes_disabled = 0x40000704;\nets_efuse_find_purpose = 0x40000708;\nets_efuse_flash_opi_5pads_power_sel_vddspi = 0x4000070c;\nets_efuse_force_send_resume = 0x40000710;\nets_efuse_get_flash_delay_us = 0x40000714;\nets_efuse_get_mac = 0x40000718;\nets_efuse_get_spiconfig = 0x4000071c;\nets_efuse_usb_print_is_disabled = 0x40000720;\nets_efuse_get_uart_print_channel = 0x40000724;\nets_efuse_get_uart_print_control = 0x40000728;\nets_efuse_get_wp_pad = 0x4000072c;\nets_efuse_legacy_spi_boot_mode_disabled = 0x40000730;\nets_efuse_security_download_modes_enabled = 0x40000734;\nets_efuse_set_timing = 0x40000738;\nets_efuse_jtag_disabled = 0x4000073c;\nets_efuse_usb_download_mode_disabled = 0x40000740;\nets_efuse_usb_module_disabled = 0x40000744;\nets_efuse_usb_device_disabled = 0x40000748;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_emsa_pss_verify = 0x4000074c;\nets_rsa_pss_verify = 0x40000750;\nets_secure_boot_verify_bootloader_with_keys = 0x40000754;\nets_secure_boot_verify_signature = 0x40000758;\nets_secure_boot_read_key_digests = 0x4000075c;\nets_secure_boot_revoke_public_key_digest = 0x40000760;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( usb_uart_rx_one_char = 0x400008cc );\nPROVIDE( usb_uart_rx_one_char_block = 0x400008d0 );\nPROVIDE( usb_uart_tx_flush = 0x400008d4 );\nPROVIDE( usb_uart_tx_one_char = 0x400008d8 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( g_uart_print = 0x3fcdffd1 );\nPROVIDE( g_usb_print = 0x3fcdffd0 );\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nbt_rf_coex_get_dft_cfg = 0x400008dc;\nbt_rf_coex_hooks_p_set = 0x400008e0;\nbtdm_con_maxevtime_cal_impl = 0x400008e4;\nbtdm_controller_get_compile_version_impl = 0x400008e8;\nbtdm_controller_rom_data_init = 0x400008ec;\nbtdm_dis_privacy_err_report_impl = 0x400008f0;\nbtdm_disable_adv_delay_impl = 0x400008f4;\nbtdm_enable_scan_continue_impl = 0x400008f8;\nbtdm_enable_scan_forever_impl = 0x400008fc;\nbtdm_get_power_state_impl = 0x40000900;\nbtdm_get_prevent_sleep_flag_impl = 0x40000904;\nbtdm_power_state_active_impl = 0x40000908;\nbtdm_switch_phy_coded_impl = 0x4000090c;\nhci_acl_data_handler = 0x40000910;\nhci_disconnect_cmd_handler = 0x40000914;\nhci_le_con_upd_cmd_handler = 0x40000918;\nhci_le_ltk_req_neg_reply_cmd_handler = 0x4000091c;\nhci_le_ltk_req_reply_cmd_handler = 0x40000920;\nhci_le_rd_chnl_map_cmd_handler = 0x40000924;\nhci_le_rd_phy_cmd_handler = 0x40000928;\nhci_le_rd_rem_feats_cmd_handler = 0x4000092c;\nhci_le_rem_con_param_req_neg_reply_cmd_handler = 0x40000930;\nhci_le_rem_con_param_req_reply_cmd_handler = 0x40000934;\nhci_le_set_data_len_cmd_handler = 0x40000938;\nhci_le_set_phy_cmd_handler = 0x4000093c;\nhci_le_start_enc_cmd_handler = 0x40000940;\nhci_rd_auth_payl_to_cmd_handler = 0x40000944;\nhci_rd_rem_ver_info_cmd_handler = 0x40000948;\nhci_rd_rssi_cmd_handler = 0x4000094c;\nhci_rd_tx_pwr_lvl_cmd_handler = 0x40000950;\nhci_vs_set_pref_slave_evt_dur_cmd_handler = 0x40000954;\nhci_vs_set_pref_slave_latency_cmd_handler = 0x40000958;\nhci_wr_auth_payl_to_cmd_handler = 0x4000095c;\nll_channel_map_ind_handler = 0x40000960;\nll_connection_param_req_handler = 0x40000964;\nll_connection_param_rsp_handler = 0x40000968;\nll_connection_update_ind_handler = 0x4000096c;\nll_enc_req_handler = 0x40000970;\nll_enc_rsp_handler = 0x40000974;\nll_feature_req_handler = 0x40000978;\nll_feature_rsp_handler = 0x4000097c;\nll_length_req_handler = 0x40000980;\nll_length_rsp_handler = 0x40000984;\nll_min_used_channels_ind_handler = 0x40000988;\nll_pause_enc_req_handler = 0x4000098c;\nll_pause_enc_rsp_handler = 0x40000990;\nll_phy_req_handler = 0x40000994;\nll_phy_rsp_handler = 0x40000998;\nll_phy_update_ind_handler = 0x4000099c;\nll_ping_req_handler = 0x400009a0;\nll_ping_rsp_handler = 0x400009a4;\nll_slave_feature_req_handler = 0x400009a8;\nll_start_enc_req_handler = 0x400009ac;\nll_start_enc_rsp_handler = 0x400009b0;\nll_terminate_ind_handler = 0x400009b4;\nll_version_ind_handler = 0x400009b8;\nllc_auth_payl_nearly_to_handler = 0x400009bc;\nllc_auth_payl_real_to_handler = 0x400009c0;\nllc_encrypt_ind_handler = 0x400009c4;\nllc_hci_command_handler_wrapper = 0x400009c8;\nllc_ll_connection_param_req_pdu_send = 0x400009cc;\nllc_ll_connection_param_rsp_pdu_send = 0x400009d0;\nllc_ll_connection_update_ind_pdu_send = 0x400009d4;\nllc_ll_enc_req_pdu_send = 0x400009d8;\nllc_ll_enc_rsp_pdu_send = 0x400009dc;\nllc_ll_feature_req_pdu_send = 0x400009e0;\nllc_ll_feature_rsp_pdu_send = 0x400009e4;\nllc_ll_length_req_pdu_send = 0x400009e8;\nllc_ll_length_rsp_pdu_send = 0x400009ec;\nllc_ll_pause_enc_req_pdu_send = 0x400009f0;\nllc_ll_pause_enc_rsp_pdu_send = 0x400009f4;\nllc_ll_phy_req_pdu_send = 0x400009f8;\nllc_ll_phy_rsp_pdu_send = 0x400009fc;\nllc_ll_ping_req_pdu_send = 0x40000a00;\nllc_ll_ping_rsp_pdu_send = 0x40000a04;\nllc_ll_start_enc_req_pdu_send = 0x40000a08;\nllc_ll_start_enc_rsp_pdu_send = 0x40000a0c;\nllc_ll_terminate_ind_pdu_send = 0x40000a10;\nllc_ll_unknown_rsp_pdu_send = 0x40000a14;\nllc_llcp_ch_map_update_ind_pdu_send = 0x40000a18;\nllc_llcp_phy_upd_ind_pdu_send = 0x40000a1c;\nllc_llcp_version_ind_pdu_send = 0x40000a20;\nllc_op_ch_map_upd_ind_handler = 0x40000a24;\nllc_op_con_upd_ind_handler = 0x40000a28;\nllc_op_disconnect_ind_handler = 0x40000a2c;\nllc_op_dl_upd_ind_handler = 0x40000a30;\nllc_op_encrypt_ind_handler = 0x40000a34;\nllc_op_feats_exch_ind_handler = 0x40000a38;\nllc_op_le_ping_ind_handler = 0x40000a3c;\nllc_op_phy_upd_ind_handler = 0x40000a40;\nllc_op_ver_exch_ind_handler = 0x40000a44;\nllc_stopped_ind_handler = 0x40000a48;\nlld_acl_rx_ind_handler = 0x40000a4c;\nlld_acl_tx_cfm_handler = 0x40000a50;\nlld_adv_end_ind_handler = 0x40000a54;\nlld_adv_rep_ind_handler = 0x40000a58;\nlld_ch_map_upd_cfm_handler = 0x40000a5c;\nlld_con_estab_ind_handler = 0x40000a60;\nlld_con_evt_sd_evt_time_set = 0x40000a64;\nlld_con_offset_upd_ind_handler = 0x40000a68;\nlld_con_param_upd_cfm_handler = 0x40000a6c;\nlld_disc_ind_handler = 0x40000a70;\nlld_init_end_ind_handler = 0x40000a74;\nlld_llcp_rx_ind_handler_wrapper = 0x40000a78;\nlld_llcp_tx_cfm_handler = 0x40000a7c;\nlld_per_adv_end_ind_handler = 0x40000a80;\nlld_per_adv_rep_ind_handler = 0x40000a84;\nlld_per_adv_rx_end_ind_handler = 0x40000a88;\nlld_phy_coded_500k_get = 0x40000a8c;\nlld_phy_upd_cfm_handler = 0x40000a90;\nlld_scan_end_ind_handler = 0x40000a94;\nlld_scan_req_ind_handler = 0x40000a98;\nlld_sync_start_req_handler = 0x40000a9c;\nlld_test_end_ind_handler = 0x40000aa0;\nlld_update_rxbuf_handler = 0x40000aa4;\nllm_ch_map_update_ind_handler = 0x40000aa8;\nllm_hci_command_handler_wrapper = 0x40000aac;\nllm_scan_period_to_handler = 0x40000ab0;\nr_Add2SelfBigHex256 = 0x40000ab4;\nr_AddBigHex256 = 0x40000ab8;\nr_AddBigHexModP256 = 0x40000abc;\nr_AddP256 = 0x40000ac0;\nr_AddPdiv2_256 = 0x40000ac4;\nr_GF_Jacobian_Point_Addition256 = 0x40000ac8;\nr_GF_Jacobian_Point_Double256 = 0x40000acc;\nr_GF_Point_Jacobian_To_Affine256 = 0x40000ad0;\nr_MultiplyBigHexByUint32_256 = 0x40000ad4;\nr_MultiplyBigHexModP256 = 0x40000ad8;\nr_MultiplyByU16ModP256 = 0x40000adc;\nr_SubtractBigHex256 = 0x40000ae0;\nr_SubtractBigHexMod256 = 0x40000ae4;\nr_SubtractBigHexUint32_256 = 0x40000ae8;\nr_SubtractFromSelfBigHex256 = 0x40000aec;\nr_SubtractFromSelfBigHexSign256 = 0x40000af0;\nr_aes_alloc = 0x40000af4;\nr_aes_ccm_continue = 0x40000af8;\nr_aes_ccm_process_e = 0x40000afc;\nr_aes_ccm_xor_128_lsb = 0x40000b00;\nr_aes_ccm_xor_128_msb = 0x40000b04;\nr_aes_cmac_continue = 0x40000b08;\nr_aes_cmac_start = 0x40000b0c;\nr_aes_k1_continue = 0x40000b10;\nr_aes_k2_continue = 0x40000b14;\nr_aes_k3_continue = 0x40000b18;\nr_aes_k4_continue = 0x40000b1c;\nr_aes_shift_left_128 = 0x40000b20;\nr_aes_start = 0x40000b24;\nr_aes_xor_128 = 0x40000b28;\nr_assert_err = 0x40000b2c;\nr_assert_param = 0x40000b30;\nr_assert_warn = 0x40000b34;\nr_bigHexInversion256 = 0x40000b38;\nr_ble_sw_cca_check_isr = 0x40000b3c;\nr_ble_util_buf_acl_tx_alloc = 0x40000b40;\nr_ble_util_buf_acl_tx_elt_get = 0x40000b44;\nr_ble_util_buf_acl_tx_free = 0x40000b48;\nr_ble_util_buf_acl_tx_free_in_isr = 0x40000b4c;\nr_ble_util_buf_adv_tx_alloc = 0x40000b50;\nr_ble_util_buf_adv_tx_free = 0x40000b54;\nr_ble_util_buf_adv_tx_free_in_isr = 0x40000b58;\nr_ble_util_buf_env_deinit = 0x40000b5c;\nr_ble_util_buf_env_init = 0x40000b60;\nr_ble_util_buf_get_rx_buf_nb = 0x40000b64;\nr_ble_util_buf_get_rx_buf_size = 0x40000b68;\nr_ble_util_buf_llcp_tx_alloc = 0x40000b6c;\nr_ble_util_buf_llcp_tx_free = 0x40000b70;\nr_ble_util_buf_rx_alloc = 0x40000b74;\nr_ble_util_buf_rx_alloc_in_isr = 0x40000b78;\nr_ble_util_buf_rx_free = 0x40000b7c;\nr_ble_util_buf_rx_free_in_isr = 0x40000b80;\nr_ble_util_buf_set_rx_buf_nb = 0x40000b84;\nr_ble_util_buf_set_rx_buf_size = 0x40000b88;\nr_ble_util_data_rx_buf_reset = 0x40000b8c;\nr_bt_bb_get_intr_mask = 0x40000b90;\nr_bt_bb_intr_clear = 0x40000b94;\nr_bt_bb_intr_mask_set = 0x40000b98;\nr_bt_bb_isr = 0x40000b9c;\nr_bt_rf_coex_cfg_set = 0x40000ba0;\nr_bt_rf_coex_conn_dynamic_pti_en_get = 0x40000ba4;\nr_bt_rf_coex_conn_phy_coded_data_time_limit_en_get = 0x40000ba8;\nr_bt_rf_coex_ext_adv_dynamic_pti_en_get = 0x40000bac;\nr_bt_rf_coex_ext_scan_dynamic_pti_en_get = 0x40000bb0;\nr_bt_rf_coex_legacy_adv_dynamic_pti_en_get = 0x40000bb4;\nr_bt_rf_coex_per_adv_dynamic_pti_en_get = 0x40000bb8;\nr_bt_rf_coex_pti_table_get = 0x40000bbc;\nr_bt_rf_coex_st_param_get = 0x40000bc0;\nr_bt_rf_coex_st_param_set = 0x40000bc4;\nr_bt_rf_coex_sync_scan_dynamic_pti_en_get = 0x40000bc8;\nr_bt_rma_apply_rule_cs_fmt = 0x40000bcc;\nr_bt_rma_apply_rule_cs_idx = 0x40000bd0;\nr_bt_rma_configure = 0x40000bd4;\nr_bt_rma_deregister_rule_cs_fmt = 0x40000bd8;\nr_bt_rma_deregister_rule_cs_idx = 0x40000bdc;\nr_bt_rma_get_ant_by_act = 0x40000be0;\nr_bt_rma_init = 0x40000be4;\nr_bt_rma_register_rule_cs_fmt = 0x40000be8;\nr_bt_rma_register_rule_cs_idx = 0x40000bec;\nr_bt_rtp_apply_rule_cs_fmt = 0x40000bf0;\nr_bt_rtp_apply_rule_cs_idx = 0x40000bf4;\nr_bt_rtp_deregister_rule_cs_fmt = 0x40000bf8;\nr_bt_rtp_deregister_rule_cs_idx = 0x40000bfc;\nr_bt_rtp_get_txpwr_idx_by_act = 0x40000c00;\nr_bt_rtp_init = 0x40000c04;\nr_bt_rtp_register_rule_cs_fmt = 0x40000c08;\nr_bt_rtp_register_rule_cs_idx = 0x40000c0c;\nr_btdm_isr = 0x40000c10;\nr_btdm_task_post = 0x40000c14;\nr_btdm_task_post_from_isr = 0x40000c18;\nr_btdm_task_recycle = 0x40000c1c;\nr_cali_phase_match_p = 0x40000c20;\nr_cmp_abs_time = 0x40000c24;\nr_cmp_dest_id = 0x40000c28;\nr_cmp_timer_id = 0x40000c2c;\nr_co_bdaddr_compare = 0x40000c30;\nr_co_ble_pkt_dur_in_us = 0x40000c34;\nr_co_list_extract = 0x40000c38;\nr_co_list_extract_after = 0x40000c3c;\nr_co_list_extract_sublist = 0x40000c40;\nr_co_list_find = 0x40000c44;\nr_co_list_init = 0x40000c48;\nr_co_list_insert_after = 0x40000c4c;\nr_co_list_insert_before = 0x40000c50;\nr_co_list_merge = 0x40000c54;\nr_co_list_pool_init = 0x40000c58;\nr_co_list_pop_front = 0x40000c5c;\nr_co_list_push_back = 0x40000c60;\nr_co_list_push_back_sublist = 0x40000c64;\nr_co_list_push_front = 0x40000c68;\nr_co_list_size = 0x40000c6c;\nr_co_nb_good_le_channels = 0x40000c70;\nr_co_util_pack = 0x40000c74;\nr_co_util_read_array_size = 0x40000c78;\nr_co_util_unpack = 0x40000c7c;\nr_dbg_env_deinit = 0x40000c80;\nr_dbg_env_init = 0x40000c84;\nr_dbg_platform_reset_complete = 0x40000c88;\nr_dl_upd_proc_start = 0x40000c8c;\nr_dump_data = 0x40000c90;\nr_ecc_abort_key256_generation = 0x40000c94;\nr_ecc_gen_new_public_key = 0x40000c98;\nr_ecc_gen_new_secret_key = 0x40000c9c;\nr_ecc_generate_key256 = 0x40000ca0;\nr_ecc_get_debug_Keys = 0x40000ca4;\nr_ecc_init = 0x40000ca8;\nr_ecc_is_valid_point = 0x40000cac;\nr_ecc_multiplication_event_handler = 0x40000cb0;\nr_ecc_point_multiplication_win_256 = 0x40000cb4;\nr_emi_alloc_em_mapping_by_offset = 0x40000cb8;\nr_emi_base_reg_lut_show = 0x40000cbc;\nr_emi_em_base_reg_show = 0x40000cc0;\nr_emi_free_em_mapping_by_offset = 0x40000cc4;\nr_emi_get_em_mapping_idx_by_offset = 0x40000cc8;\nr_emi_get_mem_addr_by_offset = 0x40000ccc;\nr_emi_overwrite_em_mapping_by_offset = 0x40000cd0;\nr_esp_vendor_hci_command_handler = 0x40000cd4;\nr_get_stack_usage = 0x40000cd8;\nr_h4tl_acl_hdr_rx_evt_handler = 0x40000cdc;\nr_h4tl_cmd_hdr_rx_evt_handler = 0x40000ce0;\nr_h4tl_cmd_pld_rx_evt_handler = 0x40000ce4;\nr_h4tl_eif_io_event_post = 0x40000ce8;\nr_h4tl_eif_register = 0x40000cec;\nr_h4tl_init = 0x40000cf0;\nr_h4tl_out_of_sync = 0x40000cf4;\nr_h4tl_out_of_sync_check = 0x40000cf8;\nr_h4tl_read_hdr = 0x40000cfc;\nr_h4tl_read_next_out_of_sync = 0x40000d00;\nr_h4tl_read_payl = 0x40000d04;\nr_h4tl_read_start = 0x40000d08;\nr_h4tl_rx_acl_hdr_extract = 0x40000d0c;\nr_h4tl_rx_cmd_hdr_extract = 0x40000d10;\nr_h4tl_rx_done = 0x40000d14;\nr_h4tl_start = 0x40000d18;\nr_h4tl_stop = 0x40000d1c;\nr_h4tl_tx_done = 0x40000d20;\nr_h4tl_tx_evt_handler = 0x40000d24;\nr_h4tl_write = 0x40000d28;\nr_hci_acl_tx_data_alloc = 0x40000d2c;\nr_hci_acl_tx_data_received = 0x40000d30;\nr_hci_basic_cmd_send_2_controller = 0x40000d34;\nr_hci_ble_adv_report_filter_check = 0x40000d38;\nr_hci_ble_adv_report_tx_check = 0x40000d3c;\nr_hci_ble_conhdl_register = 0x40000d40;\nr_hci_ble_conhdl_unregister = 0x40000d44;\nr_hci_build_acl_data = 0x40000d48;\nr_hci_build_cc_evt = 0x40000d4c;\nr_hci_build_cs_evt = 0x40000d50;\nr_hci_build_evt = 0x40000d54;\nr_hci_build_le_evt = 0x40000d58;\nr_hci_cmd_get_max_param_size = 0x40000d5c;\nr_hci_cmd_received = 0x40000d60;\nr_hci_cmd_reject = 0x40000d64;\nr_hci_evt_mask_check = 0x40000d68;\nr_hci_evt_mask_set = 0x40000d6c;\nr_hci_fc_acl_buf_size_set = 0x40000d70;\nr_hci_fc_acl_en = 0x40000d74;\nr_hci_fc_acl_packet_sent = 0x40000d78;\nr_hci_fc_check_host_available_nb_acl_packets = 0x40000d7c;\nr_hci_fc_host_nb_acl_pkts_complete = 0x40000d80;\nr_hci_fc_init = 0x40000d84;\nr_hci_look_for_cmd_desc = 0x40000d88;\nr_hci_look_for_evt_desc = 0x40000d8c;\nr_hci_look_for_le_evt_desc = 0x40000d90;\nr_hci_look_for_le_evt_desc_esp = 0x40000d94;\nr_hci_pack_bytes = 0x40000d98;\nr_hci_register_vendor_desc_tab = 0x40000d9c;\nr_hci_send_2_controller = 0x40000da0;\nr_hci_send_2_host = 0x40000da4;\nr_hci_tl_c2h_data_flow_on = 0x40000da8;\nr_hci_tl_cmd_hdr_rx_evt_handler = 0x40000dac;\nr_hci_tl_cmd_pld_rx_evt_handler = 0x40000db0;\nr_hci_tl_get_pkt = 0x40000db4;\nr_hci_tl_hci_pkt_handler = 0x40000db8;\nr_hci_tl_hci_tx_done_evt_handler = 0x40000dbc;\nr_hci_tl_inc_nb_h2c_cmd_pkts = 0x40000dc0;\nr_hci_tl_save_pkt = 0x40000dc4;\nr_hci_tl_send = 0x40000dc8;\nr_hci_tx_done = 0x40000dcc;\nr_hci_tx_start = 0x40000dd0;\nr_hci_tx_trigger = 0x40000dd4;\nr_isValidSecretKey_256 = 0x40000dd8;\nr_ke_check_malloc = 0x40000ddc;\nr_ke_event_callback_set = 0x40000de0;\nr_ke_event_clear = 0x40000de4;\nr_ke_event_flush = 0x40000de8;\nr_ke_event_get = 0x40000dec;\nr_ke_event_get_all = 0x40000df0;\nr_ke_event_init = 0x40000df4;\nr_ke_event_schedule = 0x40000df8;\nr_ke_event_set = 0x40000dfc;\nr_ke_flush = 0x40000e00;\nr_ke_free = 0x40000e04;\nr_ke_handler_search = 0x40000e08;\nr_ke_init = 0x40000e0c;\nr_ke_is_free = 0x40000e10;\nr_ke_malloc = 0x40000e14;\nr_ke_mem_init = 0x40000e18;\nr_ke_mem_is_empty = 0x40000e1c;\nr_ke_mem_is_in_heap = 0x40000e20;\nr_ke_msg_alloc = 0x40000e24;\nr_ke_msg_dest_id_get = 0x40000e28;\nr_ke_msg_discard = 0x40000e2c;\nr_ke_msg_forward = 0x40000e30;\nr_ke_msg_forward_new_id = 0x40000e34;\nr_ke_msg_free = 0x40000e38;\nr_ke_msg_in_queue = 0x40000e3c;\nr_ke_msg_save = 0x40000e40;\nr_ke_msg_send = 0x40000e44;\nr_ke_msg_send_basic = 0x40000e48;\nr_ke_msg_src_id_get = 0x40000e4c;\nr_ke_queue_extract = 0x40000e50;\nr_ke_queue_insert = 0x40000e54;\nr_ke_sleep_check = 0x40000e58;\nr_ke_state_get = 0x40000e5c;\nr_ke_state_set = 0x40000e60;\nr_ke_task_check = 0x40000e64;\nr_ke_task_create = 0x40000e68;\nr_ke_task_delete = 0x40000e6c;\nr_ke_task_handler_get = 0x40000e70;\nr_ke_task_init = 0x40000e74;\nr_ke_task_msg_flush = 0x40000e78;\nr_ke_task_saved_update = 0x40000e7c;\nr_ke_task_schedule = 0x40000e80;\nr_ke_time = 0x40000e84;\nr_ke_time_cmp = 0x40000e88;\nr_ke_time_past = 0x40000e8c;\nr_ke_timer_active = 0x40000e90;\nr_ke_timer_adjust_all = 0x40000e94;\nr_ke_timer_clear = 0x40000e98;\nr_ke_timer_init = 0x40000e9c;\nr_ke_timer_schedule = 0x40000ea0;\nr_ke_timer_set = 0x40000ea4;\nr_led_init = 0x40000ea8;\nr_led_set_all = 0x40000eac;\nr_llc_aes_res_cb = 0x40000eb0;\nr_llc_ch_map_up_proc_err_cb = 0x40000eb4;\nr_llc_cleanup = 0x40000eb8;\nr_llc_cmd_cmp_send = 0x40000ebc;\nr_llc_cmd_stat_send = 0x40000ec0;\nr_llc_con_move_cbk = 0x40000ec4;\nr_llc_con_plan_set_update = 0x40000ec8;\nr_llc_con_upd_param_in_range = 0x40000ecc;\nr_llc_disconnect = 0x40000ed0;\nr_llc_disconnect_end = 0x40000ed4;\nr_llc_disconnect_proc_continue = 0x40000ed8;\nr_llc_disconnect_proc_err_cb = 0x40000edc;\nr_llc_dl_chg_check = 0x40000ee0;\nr_llc_dle_proc_err_cb = 0x40000ee4;\nr_llc_feats_exch_proc_err_cb = 0x40000ee8;\nr_llc_hci_cmd_handler_tab_p_get = 0x40000eec;\nr_llc_hci_command_handler = 0x40000ef0;\nr_llc_hci_con_param_req_evt_send = 0x40000ef4;\nr_llc_hci_con_upd_info_send = 0x40000ef8;\nr_llc_hci_disconnected_dis = 0x40000efc;\nr_llc_hci_dl_upd_info_send = 0x40000f00;\nr_llc_hci_enc_evt_send = 0x40000f04;\nr_llc_hci_feats_info_send = 0x40000f08;\nr_llc_hci_le_phy_upd_cmp_evt_send = 0x40000f0c;\nr_llc_hci_ltk_request_evt_send = 0x40000f10;\nr_llc_hci_nb_cmp_pkts_evt_send = 0x40000f14;\nr_llc_hci_version_info_send = 0x40000f18;\nr_llc_init_term_proc = 0x40000f1c;\nr_llc_iv_skd_rand_gen = 0x40000f20;\nr_llc_le_ping_proc_continue = 0x40000f24;\nr_llc_le_ping_proc_err_cb = 0x40000f28;\nr_llc_le_ping_restart = 0x40000f2c;\nr_llc_le_ping_set = 0x40000f30;\nr_llc_ll_pause_enc_rsp_ack_handler = 0x40000f34;\nr_llc_ll_reject_ind_ack_handler = 0x40000f38;\nr_llc_ll_reject_ind_pdu_send = 0x40000f3c;\nr_llc_ll_start_enc_rsp_ack_handler = 0x40000f40;\nr_llc_ll_terminate_ind_ack = 0x40000f44;\nr_llc_ll_unknown_ind_handler = 0x40000f48;\nr_llc_llcp_send = 0x40000f4c;\nr_llc_llcp_state_set = 0x40000f50;\nr_llc_llcp_trans_timer_set = 0x40000f54;\nr_llc_llcp_tx_check = 0x40000f58;\nr_llc_loc_ch_map_proc_continue = 0x40000f5c;\nr_llc_loc_con_upd_proc_continue = 0x40000f60;\nr_llc_loc_con_upd_proc_err_cb = 0x40000f64;\nr_llc_loc_dl_upd_proc_continue = 0x40000f68;\nr_llc_loc_encrypt_proc_continue = 0x40000f6c;\nr_llc_loc_encrypt_proc_err_cb = 0x40000f70;\nr_llc_loc_feats_exch_proc_continue = 0x40000f74;\nr_llc_loc_phy_upd_proc_continue = 0x40000f78;\nr_llc_loc_phy_upd_proc_err_cb = 0x40000f7c;\nr_llc_msg_handler_tab_p_get = 0x40000f80;\nr_llc_pref_param_compute = 0x40000f84;\nr_llc_proc_collision_check = 0x40000f88;\nr_llc_proc_err_ind = 0x40000f8c;\nr_llc_proc_get = 0x40000f90;\nr_llc_proc_id_get = 0x40000f94;\nr_llc_proc_reg = 0x40000f98;\nr_llc_proc_state_get = 0x40000f9c;\nr_llc_proc_state_set = 0x40000fa0;\nr_llc_proc_timer_pause_set = 0x40000fa4;\nr_llc_proc_timer_set = 0x40000fa8;\nr_llc_proc_unreg = 0x40000fac;\nr_llc_rem_ch_map_proc_continue = 0x40000fb0;\nr_llc_rem_con_upd_proc_continue = 0x40000fb4;\nr_llc_rem_con_upd_proc_err_cb = 0x40000fb8;\nr_llc_rem_dl_upd_proc = 0x40000fbc;\nr_llc_rem_encrypt_proc_continue = 0x40000fc0;\nr_llc_rem_encrypt_proc_err_cb = 0x40000fc4;\nr_llc_rem_phy_upd_proc_continue = 0x40000fc8;\nr_llc_rem_phy_upd_proc_err_cb = 0x40000fcc;\nr_llc_role_get = 0x40000fd0;\nr_llc_sk_gen = 0x40000fd4;\nr_llc_start = 0x40000fd8;\nr_llc_stop = 0x40000fdc;\nr_llc_ver_exch_loc_proc_continue = 0x40000fe0;\nr_llc_ver_proc_err_cb = 0x40000fe4;\nr_llcp_pdu_handler_tab_p_get = 0x40000fe8;\nr_lld_aa_gen = 0x40000fec;\nr_lld_adv_adv_data_set = 0x40000ff0;\nr_lld_adv_adv_data_update = 0x40000ff4;\nr_lld_adv_aux_ch_idx_set = 0x40000ff8;\nr_lld_adv_aux_evt_canceled_cbk = 0x40000ffc;\nr_lld_adv_aux_evt_start_cbk = 0x40001000;\nr_lld_adv_coex_check_ext_adv_synced = 0x40001004;\nr_lld_adv_coex_env_reset = 0x40001008;\nr_lld_adv_duration_update = 0x4000100c;\nr_lld_adv_dynamic_pti_process = 0x40001010;\nr_lld_adv_end = 0x40001014;\nr_lld_adv_evt_canceled_cbk = 0x40001018;\nr_lld_adv_evt_start_cbk = 0x4000101c;\nr_lld_adv_ext_chain_construct = 0x40001020;\nr_lld_adv_ext_pkt_prepare = 0x40001024;\nr_lld_adv_frm_cbk = 0x40001028;\nr_lld_adv_frm_isr = 0x4000102c;\nr_lld_adv_frm_skip_isr = 0x40001030;\nr_lld_adv_init = 0x40001034;\nr_lld_adv_pkt_rx = 0x40001038;\nr_lld_adv_pkt_rx_connect_ind = 0x4000103c;\nr_lld_adv_pkt_rx_send_scan_req_evt = 0x40001040;\nr_lld_adv_rand_addr_update = 0x40001044;\nr_lld_adv_restart = 0x40001048;\nr_lld_adv_scan_rsp_data_set = 0x4000104c;\nr_lld_adv_scan_rsp_data_update = 0x40001050;\nr_lld_adv_set_tx_power = 0x40001054;\nr_lld_adv_start = 0x40001058;\nr_lld_adv_stop = 0x4000105c;\nr_lld_adv_sync_info_set = 0x40001060;\nr_lld_adv_sync_info_update = 0x40001064;\nr_lld_calc_aux_rx = 0x40001068;\nr_lld_cca_alloc = 0x4000106c;\nr_lld_cca_data_reset = 0x40001070;\nr_lld_cca_free = 0x40001074;\nr_lld_ch_assess_data_get = 0x40001078;\nr_lld_ch_idx_get = 0x4000107c;\nr_lld_ch_map_set = 0x40001080;\nr_lld_channel_assess = 0x40001084;\nr_lld_con_activity_act_offset_compute = 0x40001088;\nr_lld_con_activity_offset_compute = 0x4000108c;\nr_lld_con_ch_map_update = 0x40001090;\nr_lld_con_cleanup = 0x40001094;\nr_lld_con_current_tx_power_get = 0x40001098;\nr_lld_con_data_flow_set = 0x4000109c;\nr_lld_con_data_len_update = 0x400010a0;\nr_lld_con_data_tx = 0x400010a4;\nr_lld_con_enc_key_load = 0x400010a8;\nr_lld_con_event_counter_get = 0x400010ac;\nr_lld_con_evt_canceled_cbk = 0x400010b0;\nr_lld_con_evt_duration_min_get = 0x400010b4;\nr_lld_con_evt_max_eff_time_cal = 0x400010b8;\nr_lld_con_evt_sd_evt_time_get = 0x400010bc;\nr_lld_con_evt_start_cbk = 0x400010c0;\nr_lld_con_evt_time_update = 0x400010c4;\nr_lld_con_free_all_tx_buf = 0x400010c8;\nr_lld_con_frm_cbk = 0x400010cc;\nr_lld_con_frm_isr = 0x400010d0;\nr_lld_con_frm_skip_isr = 0x400010d4;\nr_lld_con_init = 0x400010d8;\nr_lld_con_llcp_tx = 0x400010dc;\nr_lld_con_max_lat_calc = 0x400010e0;\nr_lld_con_offset_get = 0x400010e4;\nr_lld_con_param_update = 0x400010e8;\nr_lld_con_phys_update = 0x400010ec;\nr_lld_con_pref_slave_evt_dur_set = 0x400010f0;\nr_lld_con_pref_slave_latency_set = 0x400010f4;\nr_lld_con_rssi_get = 0x400010f8;\nr_lld_con_rx = 0x400010fc;\nr_lld_con_rx_channel_assess = 0x40001100;\nr_lld_con_rx_enc = 0x40001104;\nr_lld_con_rx_isr = 0x40001108;\nr_lld_con_rx_link_info_check = 0x4000110c;\nr_lld_con_rx_llcp_check = 0x40001110;\nr_lld_con_rx_sync_time_update = 0x40001114;\nr_lld_con_sched = 0x40001118;\nr_lld_con_set_tx_power = 0x4000111c;\nr_lld_con_start = 0x40001120;\nr_lld_con_stop = 0x40001124;\nr_lld_con_tx = 0x40001128;\nr_lld_con_tx_enc = 0x4000112c;\nr_lld_con_tx_isr = 0x40001130;\nr_lld_con_tx_len_update = 0x40001134;\nr_lld_con_tx_len_update_for_intv = 0x40001138;\nr_lld_con_tx_len_update_for_rate = 0x4000113c;\nr_lld_con_tx_prog = 0x40001140;\nr_lld_conn_dynamic_pti_process = 0x40001144;\nr_lld_continue_scan_rx_isr_end_process = 0x40001148;\nr_lld_ext_scan_dynamic_pti_process = 0x4000114c;\nr_lld_hw_cca_end_isr = 0x40001150;\nr_lld_hw_cca_evt_handler = 0x40001154;\nr_lld_hw_cca_isr = 0x40001158;\nr_lld_init_cal_anchor_point = 0x4000115c;\nr_lld_init_compute_winoffset = 0x40001160;\nr_lld_init_connect_req_pack = 0x40001164;\nr_lld_init_end = 0x40001168;\nr_lld_init_evt_canceled_cbk = 0x4000116c;\nr_lld_init_evt_start_cbk = 0x40001170;\nr_lld_init_frm_cbk = 0x40001174;\nr_lld_init_frm_eof_isr = 0x40001178;\nr_lld_init_frm_skip_isr = 0x4000117c;\nr_lld_init_init = 0x40001180;\nr_lld_init_process_pkt_rx = 0x40001184;\nr_lld_init_process_pkt_rx_adv_ext_ind = 0x40001188;\nr_lld_init_process_pkt_rx_adv_ind_or_direct_ind = 0x4000118c;\nr_lld_init_process_pkt_rx_aux_connect_rsp = 0x40001190;\nr_lld_init_process_pkt_tx = 0x40001194;\nr_lld_init_process_pkt_tx_cal_con_timestamp = 0x40001198;\nr_lld_init_sched = 0x4000119c;\nr_lld_init_set_tx_power = 0x400011a0;\nr_lld_init_start = 0x400011a4;\nr_lld_init_stop = 0x400011a8;\nr_lld_instant_proc_end = 0x400011ac;\nr_lld_llcp_rx_ind_handler = 0x400011b0;\nr_lld_per_adv_ch_map_update = 0x400011b4;\nr_lld_per_adv_chain_construct = 0x400011b8;\nr_lld_per_adv_cleanup = 0x400011bc;\nr_lld_per_adv_coex_env_reset = 0x400011c0;\nr_lld_per_adv_data_set = 0x400011c4;\nr_lld_per_adv_data_update = 0x400011c8;\nr_lld_per_adv_dynamic_pti_process = 0x400011cc;\nr_lld_per_adv_evt_canceled_cbk = 0x400011d0;\nr_lld_per_adv_evt_start_cbk = 0x400011d4;\nr_lld_per_adv_ext_pkt_prepare = 0x400011d8;\nr_lld_per_adv_frm_cbk = 0x400011dc;\nr_lld_per_adv_frm_isr = 0x400011e0;\nr_lld_per_adv_frm_skip_isr = 0x400011e4;\nr_lld_per_adv_init = 0x400011e8;\nr_lld_per_adv_init_info_get = 0x400011ec;\nr_lld_per_adv_list_add = 0x400011f0;\nr_lld_per_adv_list_rem = 0x400011f4;\nr_lld_per_adv_sched = 0x400011f8;\nr_lld_per_adv_set_tx_power = 0x400011fc;\nr_lld_per_adv_start = 0x40001200;\nr_lld_per_adv_stop = 0x40001204;\nr_lld_per_adv_sync_info_get = 0x40001208;\nr_lld_process_cca_data = 0x4000120c;\nr_lld_ral_search = 0x40001210;\nr_lld_read_clock = 0x40001214;\nr_lld_res_list_add = 0x40001218;\nr_lld_res_list_clear = 0x4000121c;\nr_lld_res_list_is_empty = 0x40001220;\nr_lld_res_list_local_rpa_get = 0x40001224;\nr_lld_res_list_peer_rpa_get = 0x40001228;\nr_lld_res_list_peer_update = 0x4000122c;\nr_lld_res_list_priv_mode_update = 0x40001230;\nr_lld_res_list_rem = 0x40001234;\nr_lld_reset_reg = 0x40001238;\nr_lld_rpa_renew = 0x4000123c;\nr_lld_rpa_renew_evt_canceled_cbk = 0x40001240;\nr_lld_rpa_renew_evt_start_cbk = 0x40001244;\nr_lld_rpa_renew_instant_cbk = 0x40001248;\nr_lld_rxdesc_check = 0x4000124c;\nr_lld_rxdesc_free = 0x40001250;\nr_lld_scan_create_sync = 0x40001254;\nr_lld_scan_create_sync_cancel = 0x40001258;\nr_lld_scan_end = 0x4000125c;\nr_lld_scan_evt_canceled_cbk = 0x40001260;\nr_lld_scan_evt_start_cbk = 0x40001264;\nr_lld_scan_frm_cbk = 0x40001268;\nr_lld_scan_frm_eof_isr = 0x4000126c;\nr_lld_scan_frm_rx_isr = 0x40001270;\nr_lld_scan_frm_skip_isr = 0x40001274;\nr_lld_scan_init = 0x40001278;\nr_lld_scan_params_update = 0x4000127c;\nr_lld_scan_process_pkt_rx = 0x40001280;\nr_lld_scan_process_pkt_rx_adv_rep = 0x40001284;\nr_lld_scan_process_pkt_rx_aux_adv_ind = 0x40001288;\nr_lld_scan_process_pkt_rx_aux_chain_ind = 0x4000128c;\nr_lld_scan_process_pkt_rx_aux_scan_rsp = 0x40001290;\nr_lld_scan_process_pkt_rx_ext_adv = 0x40001294;\nr_lld_scan_process_pkt_rx_ext_adv_ind = 0x40001298;\nr_lld_scan_process_pkt_rx_legacy_adv = 0x4000129c;\nr_lld_scan_restart = 0x400012a0;\nr_lld_scan_sched = 0x400012a4;\nr_lld_scan_set_tx_power = 0x400012a8;\nr_lld_scan_start = 0x400012ac;\nr_lld_scan_stop = 0x400012b0;\nr_lld_scan_sync_accept = 0x400012b4;\nr_lld_scan_sync_info_unpack = 0x400012b8;\nr_lld_scan_trunc_ind = 0x400012bc;\nr_lld_sw_cca_evt_handler = 0x400012c0;\nr_lld_sw_cca_isr = 0x400012c4;\nr_lld_sync_ch_map_update = 0x400012c8;\nr_lld_sync_cleanup = 0x400012cc;\nr_lld_sync_evt_canceled_cbk = 0x400012d0;\nr_lld_sync_evt_start_cbk = 0x400012d4;\nr_lld_sync_frm_cbk = 0x400012d8;\nr_lld_sync_frm_eof_isr = 0x400012dc;\nr_lld_sync_frm_rx_isr = 0x400012e0;\nr_lld_sync_frm_skip_isr = 0x400012e4;\nr_lld_sync_init = 0x400012e8;\nr_lld_sync_process_pkt_rx = 0x400012ec;\nr_lld_sync_process_pkt_rx_aux_sync_ind = 0x400012f0;\nr_lld_sync_process_pkt_rx_pkt_check = 0x400012f4;\nr_lld_sync_scan_dynamic_pti_process = 0x400012f8;\nr_lld_sync_sched = 0x400012fc;\nr_lld_sync_start = 0x40001300;\nr_lld_sync_stop = 0x40001304;\nr_lld_sync_trunc_ind = 0x40001308;\nr_lld_test_cleanup = 0x4000130c;\nr_lld_test_evt_canceled_cbk = 0x40001310;\nr_lld_test_evt_start_cbk = 0x40001314;\nr_lld_test_freq2chnl = 0x40001318;\nr_lld_test_frm_cbk = 0x4000131c;\nr_lld_test_frm_isr = 0x40001320;\nr_lld_test_init = 0x40001324;\nr_lld_test_rx_isr = 0x40001328;\nr_lld_test_set_tx_power = 0x4000132c;\nr_lld_test_start = 0x40001330;\nr_lld_test_stop = 0x40001334;\nr_lld_update_rxbuf = 0x40001338;\nr_lld_update_rxbuf_isr = 0x4000133c;\nr_lld_white_list_add = 0x40001340;\nr_lld_white_list_rem = 0x40001344;\nr_llm_activity_free_get = 0x40001348;\nr_llm_activity_free_set = 0x4000134c;\nr_llm_activity_syncing_get = 0x40001350;\nr_llm_adv_con_len_check = 0x40001354;\nr_llm_adv_hdl_to_id = 0x40001358;\nr_llm_adv_rep_flow_control_check = 0x4000135c;\nr_llm_adv_rep_flow_control_update = 0x40001360;\nr_llm_adv_reports_list_check = 0x40001364;\nr_llm_adv_set_all_release = 0x40001368;\nr_llm_adv_set_dft_params = 0x4000136c;\nr_llm_adv_set_release = 0x40001370;\nr_llm_aes_res_cb = 0x40001374;\nr_llm_ble_update_adv_flow_control = 0x40001378;\nr_llm_ch_map_update = 0x4000137c;\nr_llm_cmd_cmp_send = 0x40001380;\nr_llm_cmd_stat_send = 0x40001384;\nr_llm_dev_list_empty_entry = 0x40001388;\nr_llm_dev_list_search = 0x4000138c;\nr_llm_env_adv_dup_filt_deinit = 0x40001390;\nr_llm_env_adv_dup_filt_init = 0x40001394;\nr_llm_init_ble_adv_report_flow_contol = 0x40001398;\nr_llm_is_dev_connected = 0x4000139c;\nr_llm_is_dev_synced = 0x400013a0;\nr_llm_is_non_con_act_ongoing_check = 0x400013a4;\nr_llm_is_wl_accessible = 0x400013a8;\nr_llm_le_evt_mask_check = 0x400013ac;\nr_llm_le_features_get = 0x400013b0;\nr_llm_link_disc = 0x400013b4;\nr_llm_master_ch_map_get = 0x400013b8;\nr_llm_msg_handler_tab_p_get = 0x400013bc;\nr_llm_no_activity = 0x400013c0;\nr_llm_per_adv_slot_dur = 0x400013c4;\nr_llm_plan_elt_get = 0x400013c8;\nr_llm_rx_path_comp_get = 0x400013cc;\nr_llm_scan_start = 0x400013d0;\nr_llm_scan_sync_acad_attach = 0x400013d4;\nr_llm_scan_sync_acad_detach = 0x400013d8;\nr_llm_send_adv_lost_event_to_host = 0x400013dc;\nr_llm_tx_path_comp_get = 0x400013e0;\nr_misc_deinit = 0x400013e4;\nr_misc_free_em_buf_in_isr = 0x400013e8;\nr_misc_init = 0x400013ec;\nr_misc_msg_handler_tab_p_get = 0x400013f0;\nr_notEqual256 = 0x400013f4;\nr_phy_upd_proc_start = 0x400013f8;\nr_platform_reset = 0x400013fc;\nr_register_esp_vendor_cmd_handler = 0x40001400;\nr_rf_em_init = 0x40001404;\nr_rf_force_agc_enable = 0x40001408;\nr_rf_reg_rd = 0x4000140c;\nr_rf_reg_wr = 0x40001410;\nr_rf_reset = 0x40001414;\nr_rf_rssi_convert = 0x40001418;\nr_rf_rw_v9_le_disable = 0x4000141c;\nr_rf_rw_v9_le_enable = 0x40001420;\nr_rf_sleep = 0x40001424;\nr_rf_txpwr_cs_get = 0x40001428;\nr_rf_txpwr_dbm_get = 0x4000142c;\nr_rf_util_cs_fmt_convert = 0x40001430;\nr_rw_crypto_aes_ccm = 0x40001434;\nr_rw_crypto_aes_encrypt = 0x40001438;\nr_rw_crypto_aes_init = 0x4000143c;\nr_rw_crypto_aes_k1 = 0x40001440;\nr_rw_crypto_aes_k2 = 0x40001444;\nr_rw_crypto_aes_k3 = 0x40001448;\nr_rw_crypto_aes_k4 = 0x4000144c;\nr_rw_crypto_aes_rand = 0x40001450;\nr_rw_crypto_aes_result_handler = 0x40001454;\nr_rw_crypto_aes_s1 = 0x40001458;\nr_rw_cryto_aes_cmac = 0x4000145c;\nr_rw_v9_init_em_radio_table = 0x40001460;\nr_rwble_isr = 0x40001464;\nr_rwble_sleep_enter = 0x40001468;\nr_rwble_sleep_wakeup_end = 0x4000146c;\nr_rwbtdm_isr_wrapper = 0x40001470;\nr_rwip_active_check = 0x40001474;\nr_rwip_aes_encrypt = 0x40001478;\nr_rwip_assert = 0x4000147c;\nr_rwip_crypt_evt_handler = 0x40001480;\nr_rwip_crypt_isr_handler = 0x40001484;\nr_rwip_eif_get = 0x40001488;\nr_rwip_half_slot_2_lpcycles = 0x4000148c;\nr_rwip_hus_2_lpcycles = 0x40001490;\nr_rwip_isr = 0x40001494;\nr_rwip_lpcycles_2_hus = 0x40001498;\nr_rwip_prevent_sleep_clear = 0x4000149c;\nr_rwip_prevent_sleep_set = 0x400014a0;\nr_rwip_schedule = 0x400014a4;\nr_rwip_sleep = 0x400014a8;\nr_rwip_sw_int_handler = 0x400014ac;\nr_rwip_sw_int_req = 0x400014b0;\nr_rwip_time_get = 0x400014b4;\nr_rwip_timer_10ms_handler = 0x400014b8;\nr_rwip_timer_10ms_set = 0x400014bc;\nr_rwip_timer_hs_handler = 0x400014c0;\nr_rwip_timer_hs_set = 0x400014c4;\nr_rwip_timer_hus_handler = 0x400014c8;\nr_rwip_timer_hus_set = 0x400014cc;\nr_rwip_wakeup = 0x400014d0;\nr_rwip_wakeup_end = 0x400014d4;\nr_rwip_wlcoex_set = 0x400014d8;\nr_sch_alarm_clear = 0x400014dc;\nr_sch_alarm_init = 0x400014e0;\nr_sch_alarm_prog = 0x400014e4;\nr_sch_alarm_set = 0x400014e8;\nr_sch_alarm_timer_isr = 0x400014ec;\nr_sch_arb_conflict_check = 0x400014f0;\nr_sch_arb_elt_cancel = 0x400014f4;\nr_sch_arb_event_start_isr = 0x400014f8;\nr_sch_arb_init = 0x400014fc;\nr_sch_arb_insert = 0x40001500;\nr_sch_arb_prog_timer = 0x40001504;\nr_sch_arb_remove = 0x40001508;\nr_sch_arb_sw_isr = 0x4000150c;\nr_sch_plan_chk = 0x40001510;\nr_sch_plan_clock_wrap_offset_update = 0x40001514;\nr_sch_plan_init = 0x40001518;\nr_sch_plan_interval_req = 0x4000151c;\nr_sch_plan_offset_max_calc = 0x40001520;\nr_sch_plan_offset_req = 0x40001524;\nr_sch_plan_position_range_compute = 0x40001528;\nr_sch_plan_rem = 0x4000152c;\nr_sch_plan_req = 0x40001530;\nr_sch_plan_set = 0x40001534;\nr_sch_prog_end_isr = 0x40001538;\nr_sch_prog_init = 0x4000153c;\nr_sch_prog_push = 0x40001540;\nr_sch_prog_rx_isr = 0x40001544;\nr_sch_prog_skip_isr = 0x40001548;\nr_sch_prog_tx_isr = 0x4000154c;\nr_sch_slice_bg_add = 0x40001550;\nr_sch_slice_bg_remove = 0x40001554;\nr_sch_slice_compute = 0x40001558;\nr_sch_slice_fg_add = 0x4000155c;\nr_sch_slice_fg_remove = 0x40001560;\nr_sch_slice_init = 0x40001564;\nr_sch_slice_per_add = 0x40001568;\nr_sch_slice_per_remove = 0x4000156c;\nr_sdk_config_get_bt_sleep_enable = 0x40001570;\nr_sdk_config_get_hl_derived_opts = 0x40001574;\nr_sdk_config_get_opts = 0x40001578;\nr_sdk_config_get_priv_opts = 0x4000157c;\nr_sdk_config_set_bt_sleep_enable = 0x40001580;\nr_sdk_config_set_hl_derived_opts = 0x40001584;\nr_sdk_config_set_opts = 0x40001588;\nr_specialModP256 = 0x4000158c;\nr_unloaded_area_init = 0x40001590;\nr_vhci_flow_off = 0x40001594;\nr_vhci_flow_on = 0x40001598;\nr_vhci_notify_host_send_available = 0x4000159c;\nr_vhci_send_to_host = 0x400015a0;\nr_vnd_hci_command_handler = 0x400015a4;\nr_vshci_init = 0x400015a8;\nvnd_hci_command_handler_wrapper = 0x400015ac;\n\/* Data (.data, .bss, .rodata) *\/\nbt_rf_coex_cfg_p = 0x3fcdffcc;\nbt_rf_coex_hooks_p = 0x3fcdffc8;\nbtdm_env_p = 0x3fcdffc4;\ng_rw_controller_task_handle = 0x3fcdffc0;\ng_rw_init_sem = 0x3fcdffbc;\ng_rw_schd_queue = 0x3fcdffb8;\nlld_init_env = 0x3fcdffb4;\nlld_rpa_renew_env = 0x3fcdffb0;\nlld_scan_env = 0x3fcdffac;\nlld_scan_sync_env = 0x3fcdffa8;\nlld_test_env = 0x3fcdffa4;\np_ble_util_buf_env = 0x3fcdffa0;\np_lld_env = 0x3fcdff9c;\np_llm_env = 0x3fcdff98;\nr_h4tl_eif_p = 0x3fcdff94;\nr_hli_funcs_p = 0x3fcdff90;\nr_ip_funcs_p = 0x3fcdff8c;\nr_modules_funcs_p = 0x3fcdff88;\nr_osi_funcs_p = 0x3fcdff84;\nr_plf_funcs_p = 0x3fcdff80;\nvhci_env_p = 0x3fcdff7c;\naa_gen = 0x3fcdff78;\naes_env = 0x3fcdff6c;\nbt_rf_coex_cfg_cb = 0x3fcdff1c;\nbtdm_pwr_state = 0x3fcdff18;\nbtdm_slp_err = 0x3fcdff14;\necc_env = 0x3fcdff0c;\nesp_handler = 0x3fcdff04;\nesp_vendor_cmd = 0x3fcdfefc;\ng_adv_delay_dis = 0x3fcdfef8;\ng_conflict_elt = 0x3fcdfef4;\ng_eif_api = 0x3fcdfee4;\ng_event_empty = 0x3fcdfed8;\ng_llc_state = 0x3fcdfecc;\ng_llm_state = 0x3fcdfec8;\ng_max_evt_env = 0x3fcdfec4;\ng_misc_state = 0x3fcdfec0;\ng_rma_rule_db = 0x3fcdfea4;\ng_rtp_rule_db = 0x3fcdfe88;\ng_scan_forever = 0x3fcdfe85;\ng_time_msb = 0x3fcdfe84;\nh4tl_env = 0x3fcdfe5c;\nhci_env = 0x3fcdfe38;\nhci_ext_host = 0x3fcdfe34;\nhci_fc_env = 0x3fcdfe2c;\nhci_tl_env = 0x3fcdfe00;\nke_env = 0x3fcdfdd0;\nke_event_env = 0x3fcdfd90;\nke_task_env = 0x3fcdfd14;\nllc_env = 0x3fcdfcec;\nlld_adv_env = 0x3fcdfcc4;\nlld_con_env = 0x3fcdfc9c;\nlld_exp_sync_pos_tab = 0x3fcdfc94;\nlld_per_adv_env = 0x3fcdfc6c;\nlld_sync_env = 0x3fcdfc44;\nllm_le_adv_flow_env = 0x3fcdfc38;\nrw_sleep_enable = 0x3fcdfc34;\nrwble_env = 0x3fcdfc2c;\nrwip_env = 0x3fcdfc10;\nrwip_param = 0x3fcdfc04;\nrwip_prog_delay = 0x3fcdfc00;\nrwip_rf = 0x3fcdfbc8;\nsch_alarm_env = 0x3fcdfbc0;\nsch_arb_env = 0x3fcdfbac;\nsch_plan_env = 0x3fcdfba4;\nsch_prog_env = 0x3fcdfaa0;\nsch_slice_env = 0x3fcdfa40;\nsch_slice_params = 0x3fcdfa38;\ntimer_env = 0x3fcdfa30;\nunloaded_area = 0x3fcdfa2c;\nvshci_state = 0x3fcdfa28;\nTASK_DESC_LLC = 0x3fcdfa1c;\nTASK_DESC_LLM = 0x3fcdfa10;\nTASK_DESC_VSHCI = 0x3fcdfa04;\nco_default_bdaddr = 0x3fcdf9fc;\ndbg_assert_block = 0x3fcdf9f8;\ng_bt_plf_log_level = 0x3fcdf9f4;\nhci_cmd_desc_tab_vs_esp = 0x3fcdf9d0;\nhci_command_handler_tab_esp = 0x3fcdf9b8;\nprivacy_en = 0x3fcdf9b4;\nsdk_cfg_priv_opts = 0x3fcdf96c;\nBasePoint_x_256 = 0x3ff1ffdc;\nBasePoint_y_256 = 0x3ff1ffbc;\nDebugE256PublicKey_x = 0x3ff1ff9c;\nDebugE256PublicKey_y = 0x3ff1ff7c;\nDebugE256SecretKey = 0x3ff1ff5c;\nECC_4Win_Look_up_table = 0x3ff1f7a0;\nLLM_AA_CT1 = 0x3ff1f79c;\nLLM_AA_CT2 = 0x3ff1f798;\nRF_TX_PW_CONV_TBL = 0x3ff1f790;\nTASK_DESC_MISC = 0x3ff1f784;\nadv_evt_prop2type = 0x3ff1f768;\nadv_evt_type2prop = 0x3ff1f760;\naes_cmac_zero = 0x3ff1f750;\naes_k2_salt = 0x3ff1f740;\naes_k3_id64 = 0x3ff1f738;\naes_k3_salt = 0x3ff1f728;\naes_k4_id6 = 0x3ff1f724;\naes_k4_salt = 0x3ff1f714;\nbigHexP256 = 0x3ff1f6e8;\nbyte_tx_time = 0x3ff1f6e0;\nco_null_bdaddr = 0x3ff1f6d8;\nco_phy_mask_to_rate = 0x3ff1f6d0;\nco_phy_mask_to_value = 0x3ff1f6c8;\nco_phy_to_rate = 0x3ff1f6c4;\nco_phy_value_to_mask = 0x3ff1f6c0;\nco_rate_to_byte_dur_us = 0x3ff1f6b8;\nco_rate_to_phy = 0x3ff1f6b0;\nco_rate_to_phy_mask = 0x3ff1f6ac;\nco_sca2ppm = 0x3ff1f69c;\ncoef_B = 0x3ff1f670;\nconnect_req_dur_tab = 0x3ff1f668;\necc_Jacobian_InfinityPoint256 = 0x3ff1f5e4;\nem_base_reg_lut = 0x3ff1f518;\nfixed_tx_time = 0x3ff1f510;\nh4tl_msgtype2hdrlen = 0x3ff1f508;\nhci_cmd_desc_root_tab = 0x3ff1f4d8;\nhci_cmd_desc_tab_ctrl_bb = 0x3ff1f46c;\nhci_cmd_desc_tab_info_par = 0x3ff1f43c;\nhci_cmd_desc_tab_le = 0x3ff1f0a0;\nhci_cmd_desc_tab_lk_ctrl = 0x3ff1f088;\nhci_cmd_desc_tab_stat_par = 0x3ff1f07c;\nhci_cmd_desc_tab_vs = 0x3ff1f040;\nhci_evt_desc_tab = 0x3ff1eff8;\nhci_evt_le_desc_tab = 0x3ff1ef58;\nhci_evt_le_desc_tab_esp = 0x3ff1ef50;\nhci_rsvd_evt_msk = 0x3ff1ef48;\nlld_aux_phy_to_rate = 0x3ff1ef44;\nlld_init_max_aux_dur_tab = 0x3ff1ef3c;\nlld_scan_map_legacy_pdu_to_evt_type = 0x3ff1ef34;\nlld_scan_max_aux_dur_tab = 0x3ff1ef2c;\nlld_sync_max_aux_dur_tab = 0x3ff1ef24;\nllm_local_le_feats = 0x3ff1ef1c;\nllm_local_le_states = 0x3ff1ef14;\nllm_local_supp_cmds = 0x3ff1eeec;\nmaxSecretKey_256 = 0x3ff1eecc;\nmax_data_tx_time = 0x3ff1eec4;\none_bits = 0x3ff1eeb4;\nrwip_coex_cfg = 0x3ff1eeac;\nrwip_priority = 0x3ff1ee94;\nveryBigHexP256 = 0x3ff1ee48;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x400015b0;\nRC_GetBlockAckTime = 0x400015b4;\nebuf_list_remove = 0x400015b8;\nesf_buf_alloc = 0x400015bc;\nesf_buf_alloc_dynamic = 0x400015c0;\nesf_buf_recycle = 0x400015c4;\nGetAccess = 0x400015c8;\nhal_mac_is_low_rate_enabled = 0x400015cc;\nhal_mac_tx_get_blockack = 0x400015d0;\nhal_mac_tx_set_ppdu = 0x400015d4;\nic_get_trc = 0x400015d8;\nic_mac_deinit = 0x400015dc;\nic_mac_init = 0x400015e0;\nic_interface_enabled = 0x400015e4;\nis_lmac_idle = 0x400015e8;\nlmacAdjustTimestamp = 0x400015ec;\nlmacDiscardAgedMSDU = 0x400015f0;\nlmacDiscardMSDU = 0x400015f4;\nlmacEndFrameExchangeSequence = 0x400015f8;\nlmacIsIdle = 0x400015fc;\nlmacIsLongFrame = 0x40001600;\nlmacMSDUAged = 0x40001604;\nlmacPostTxComplete = 0x40001608;\nlmacProcessAllTxTimeout = 0x4000160c;\nlmacProcessCollisions = 0x40001610;\nlmacProcessRxSucData = 0x40001614;\nlmacReachLongLimit = 0x40001618;\nlmacReachShortLimit = 0x4000161c;\nlmacRecycleMPDU = 0x40001620;\nlmacRxDone = 0x40001624;\nlmacSetTxFrame = 0x40001628;\nlmacTxFrame = 0x40001630;\nmac_tx_set_duration = 0x40001634;\nmac_tx_set_htsig = 0x40001638;\nmac_tx_set_plcp0 = 0x4000163c;\nmac_tx_set_plcp1 = 0x40001640;\nmac_tx_set_plcp2 = 0x40001644;\npm_check_state = 0x40001648;\npm_disable_dream_timer = 0x4000164c;\npm_disable_sleep_delay_timer = 0x40001650;\npm_dream = 0x40001654;\npm_mac_wakeup = 0x40001658;\npm_mac_sleep = 0x4000165c;\npm_enable_active_timer = 0x40001660;\npm_enable_sleep_delay_timer = 0x40001664;\npm_local_tsf_process = 0x40001668;\npm_set_beacon_filter = 0x4000166c;\npm_is_in_wifi_slice_threshold = 0x40001670;\npm_is_waked = 0x40001674;\npm_keep_alive = 0x40001678;\npm_on_beacon_rx = 0x4000167c;\npm_on_data_rx = 0x40001680;\npm_on_tbtt = 0x40001684;\npm_parse_beacon = 0x40001688;\npm_process_tim = 0x4000168c;\npm_rx_beacon_process = 0x40001690;\npm_rx_data_process = 0x40001694;\npm_sleep = 0x40001698;\npm_sleep_for = 0x4000169c;\npm_tbtt_process = 0x400016a0;\nppAMPDU2Normal = 0x400016a4;\nppAssembleAMPDU = 0x400016a8;\nppCalFrameTimes = 0x400016ac;\nppCalSubFrameLength = 0x400016b0;\nppCalTxAMPDULength = 0x400016b4;\nppCheckTxAMPDUlength = 0x400016b8;\nppDequeueRxq_Locked = 0x400016bc;\nppDequeueTxQ = 0x400016c0;\nppEmptyDelimiterLength = 0x400016c4;\nppEnqueueRxq = 0x400016c8;\nppEnqueueTxDone = 0x400016cc;\nppGetTxQFirstAvail_Locked = 0x400016d0;\nppGetTxframe = 0x400016d4;\nppMapTxQueue = 0x400016d8;\nppProcTxSecFrame = 0x400016dc;\nppProcessRxPktHdr = 0x400016e0;\nppProcessTxQ = 0x400016e4;\nppRecordBarRRC = 0x400016e8;\nlmacRequestTxopQueue = 0x400016ec;\nlmacReleaseTxopQueue = 0x400016f0;\nppRecycleAmpdu = 0x400016f4;\nppRecycleRxPkt = 0x400016f8;\nppResortTxAMPDU = 0x400016fc;\nppResumeTxAMPDU = 0x40001700;\nppRxFragmentProc = 0x40001704;\nppRxPkt = 0x40001708;\nppRxProtoProc = 0x4000170c;\nppSearchTxQueue = 0x40001710;\nppSearchTxframe = 0x40001714;\nppSelectNextQueue = 0x40001718;\nppSubFromAMPDU = 0x4000171c;\nppTask = 0x40001720;\nppTxPkt = 0x40001724;\nppTxProtoProc = 0x40001728;\nppTxqUpdateBitmap = 0x4000172c;\npp_coex_tx_request = 0x40001730;\npp_hdrsize = 0x40001734;\npp_post = 0x40001738;\npp_process_hmac_waiting_txq = 0x4000173c;\nrcGetAmpduSched = 0x40001740;\nrcUpdateRxDone = 0x40001744;\nrc_get_trc = 0x40001748;\nrc_get_trc_by_index = 0x4000174c;\nrcAmpduLowerRate = 0x40001750;\nrcampduuprate = 0x40001754;\nrcClearCurAMPDUSched = 0x40001758;\nrcClearCurSched = 0x4000175c;\nrcClearCurStat = 0x40001760;\nrcGetSched = 0x40001764;\nrcLowerSched = 0x40001768;\nrcSetTxAmpduLimit = 0x4000176c;\nrcTxUpdatePer = 0x40001770;\nrcUpdateAckSnr = 0x40001774;\nrcUpdateRate = 0x40001778;\nrcUpdateTxDone = 0x4000177c;\nrcUpdateTxDoneAmpdu2 = 0x40001780;\nrcUpSched = 0x40001784;\nrssi_margin = 0x40001788;\nrx11NRate2AMPDULimit = 0x4000178c;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001790;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001794;\ntrc_calc_duration = 0x40001798;\ntrc_isTxAmpduOperational = 0x4000179c;\ntrc_onAmpduOp = 0x400017a0;\nTRC_PER_IS_GOOD = 0x400017a4;\ntrc_SetTxAmpduState = 0x400017a8;\ntrc_tid_isTxAmpduOperational = 0x400017ac;\ntrcAmpduSetState = 0x400017b0;\nwDevCheckBlockError = 0x400017b4;\nwDev_AppendRxBlocks = 0x400017b8;\nwDev_DiscardFrame = 0x400017bc;\nwDev_GetNoiseFloor = 0x400017c0;\nwDev_IndicateAmpdu = 0x400017c4;\nwDev_IndicateFrame = 0x400017c8;\nwdev_bank_store = 0x400017cc;\nwdev_bank_load = 0x400017d0;\nwdev_mac_reg_load = 0x400017d4;\nwdev_mac_reg_store = 0x400017d8;\nwdev_mac_special_reg_load = 0x400017dc;\nwdev_mac_special_reg_store = 0x400017e0;\nwdev_mac_wakeup = 0x400017e4;\nwdev_mac_sleep = 0x400017e8;\nhal_mac_is_dma_enable = 0x400017ec;\nwDev_ProcessFiq = 0x400017f0;\nwDev_ProcessRxSucData = 0x400017f4;\nwdevProcessRxSucDataAll = 0x400017f8;\nwdev_csi_len_align = 0x400017fc;\nppDequeueTxDone_Locked = 0x40001800;\npm_tx_data_done_process = 0x40001808;\nconfig_is_cache_tx_buf_enabled = 0x4000180c;\nppMapWaitTxq = 0x40001810;\nppProcessWaitingQueue = 0x40001814;\nppDisableQueue = 0x40001818;\npm_allow_tx = 0x4000181c;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff1ee44;\npTxRx = 0x3fcdf968;\nlmacConfMib_ptr = 0x3fcdf964;\nour_wait_eb = 0x3fcdf960;\nour_tx_eb = 0x3fcdf95c;\npp_wdev_funcs = 0x3fcdf958;\ng_osi_funcs_p = 0x3fcdf954;\nwDevCtrl_ptr = 0x3fcdf950;\ng_wdev_last_desc_reset_ptr = 0x3ff1ee40;\nwDevMacSleep_ptr = 0x3fcdf94c;\ng_lmac_cnt_ptr = 0x3fcdf948;\nour_controls_ptr = 0x3ff1ee3c;\npp_sig_cnt_ptr = 0x3fcdf944;\ng_eb_list_desc_ptr = 0x3fcdf940;\ns_fragment_ptr = 0x3fcdf93c;\nif_ctrl_ptr = 0x3fcdf938;\ng_intr_lock_mux = 0x3fcdf934;\ng_wifi_global_lock = 0x3fcdf930;\ns_wifi_queue = 0x3fcdf92c;\npp_task_hdl = 0x3fcdf928;\ns_pp_task_create_sem = 0x3fcdf924;\ns_pp_task_del_sem = 0x3fcdf920;\ng_wifi_menuconfig_ptr = 0x3fcdf91c;\nxphyQueue = 0x3fcdf918;\nap_no_lr_ptr = 0x3fcdf914;\nrc11BSchedTbl_ptr = 0x3fcdf910;\nrc11NSchedTbl_ptr = 0x3fcdf90c;\nrcLoRaSchedTbl_ptr = 0x3fcdf908;\nBasicOFDMSched_ptr = 0x3fcdf904;\ntrc_ctl_ptr = 0x3fcdf900;\ng_pm_cnt_ptr = 0x3fcdf8fc;\ng_pm_ptr = 0x3fcdf8f8;\ng_pm_cfg_ptr = 0x3fcdf8f4;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdf8f0;\ng_txop_queue_status_ptr = 0x3fcdf8ec;\ng_mac_sleep_en_ptr = 0x3fcdf8e8;\ng_mesh_is_root_ptr = 0x3fcdf8e4;\ng_mesh_topology_ptr = 0x3fcdf8e0;\ng_mesh_init_ps_type_ptr = 0x3fcdf8dc;\ng_mesh_is_started_ptr = 0x3fcdf8d8;\ng_config_func = 0x3fcdf8d4;\ng_net80211_tx_func = 0x3fcdf8d0;\ng_timer_func = 0x3fcdf8cc;\ns_michael_mic_failure_cb = 0x3fcdf8c8;\nwifi_sta_rx_probe_req = 0x3fcdf8c4;\ng_tx_done_cb_func = 0x3fcdf8c0;\ng_per_conn_trc = 0x3fcdf874;\ns_encap_amsdu_func = 0x3fcdf870;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001820;\nampdu_dispatch = 0x40001824;\nampdu_dispatch_all = 0x40001828;\nampdu_dispatch_as_many_as_possible = 0x4000182c;\nampdu_dispatch_movement = 0x40001830;\nampdu_dispatch_upto = 0x40001834;\nchm_is_at_home_channel = 0x40001838;\ncnx_node_is_existing = 0x4000183c;\ncnx_node_search = 0x40001840;\nic_ebuf_recycle_rx = 0x40001844;\nic_ebuf_recycle_tx = 0x40001848;\nic_reset_rx_ba = 0x4000184c;\nieee80211_align_eb = 0x40001850;\nieee80211_ampdu_reorder = 0x40001854;\nieee80211_ampdu_start_age_timer = 0x40001858;\nieee80211_encap_esfbuf = 0x4000185c;\nieee80211_is_tx_allowed = 0x40001860;\nieee80211_output_pending_eb = 0x40001864;\nieee80211_output_process = 0x40001868;\nieee80211_set_tx_desc = 0x4000186c;\nrom_sta_input = 0x40001870;\nwifi_get_macaddr = 0x40001874;\nwifi_rf_phy_disable = 0x40001878;\nwifi_rf_phy_enable = 0x4000187c;\nic_ebuf_alloc = 0x40001880;\nieee80211_classify = 0x40001884;\nieee80211_copy_eb_header = 0x40001888;\nieee80211_recycle_cache_eb = 0x4000188c;\nieee80211_search_node = 0x40001890;\nroundup2 = 0x40001894;\nieee80211_crypto_encap = 0x40001898;\nieee80211_crypto_decap = 0x4000189c;\nieee80211_decap = 0x400018a0;\nieee80211_set_tx_pti = 0x400018a4;\nwifi_is_started = 0x400018a8;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdf86c;\ng_scan = 0x3fcdf868;\ng_chm = 0x3fcdf864;\ng_ic_ptr = 0x3fcdf860;\ng_hmac_cnt_ptr = 0x3fcdf85c;\ng_tx_cacheq_ptr = 0x3fcdf858;\ns_netstack_free = 0x3fcdf854;\nmesh_rxcb = 0x3fcdf850;\nsta_rxcb = 0x3fcdf84c;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x400018ac;\ncoex_bt_release = 0x400018b0;\ncoex_bt_request = 0x400018b4;\ncoex_core_ble_conn_dyn_prio_get = 0x400018b8;\ncoex_core_event_duration_get = 0x400018bc;\ncoex_core_pti_get = 0x400018c0;\ncoex_core_release = 0x400018c4;\ncoex_core_request = 0x400018c8;\ncoex_core_status_get = 0x400018cc;\ncoex_core_timer_idx_get = 0x400018d0;\ncoex_event_duration_get = 0x400018d4;\ncoex_hw_timer_disable = 0x400018d8;\ncoex_hw_timer_enable = 0x400018dc;\ncoex_hw_timer_set = 0x400018e0;\ncoex_schm_interval_set = 0x400018e4;\ncoex_schm_lock = 0x400018e8;\ncoex_schm_unlock = 0x400018ec;\ncoex_status_get = 0x400018f0;\ncoex_wifi_release = 0x400018f4;\nesp_coex_ble_conn_dynamic_prio_get = 0x400018f8;\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdf848;\ncoex_pti_tab_ptr = 0x3fcdf844;\ncoex_schm_env_ptr = 0x3fcdf840;\ncoexist_funcs = 0x3fcdf83c;\ng_coa_funcs_p = 0x3fcdf838;\ng_coex_param_ptr = 0x3fcdf834;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_get_romfuncs = 0x400018fc;\nrom_abs_temp = 0x40001900;\nrom_bb_bss_cbw40_dig = 0x40001904;\nrom_bb_wdg_test_en = 0x40001908;\nrom_bb_wdt_get_status = 0x4000190c;\nrom_bb_wdt_int_enable = 0x40001910;\nrom_bb_wdt_rst_enable = 0x40001914;\nrom_bb_wdt_timeout_clear = 0x40001918;\nrom_cbw2040_cfg = 0x4000191c;\nrom_check_noise_floor = 0x40001920;\nrom_chip_i2c_readReg = 0x40001924;\nrom_chip_i2c_writeReg = 0x40001928;\nrom_correct_rf_ana_gain = 0x4000192c;\nrom_dc_iq_est = 0x40001930;\nrom_disable_agc = 0x40001934;\nrom_en_pwdet = 0x40001938;\nrom_enable_agc = 0x4000193c;\nrom_get_bbgain_db = 0x40001940;\nrom_get_data_sat = 0x40001944;\nrom_get_i2c_read_mask = 0x40001948;\nrom_get_pwctrl_correct = 0x4000194c;\nrom_get_rf_gain_qdb = 0x40001950;\nrom_i2c_readReg = 0x40001954;\nrom_i2c_readReg_Mask = 0x40001958;\nrom_i2c_writeReg = 0x4000195c;\nrom_i2c_writeReg_Mask = 0x40001960;\nrom_index_to_txbbgain = 0x40001964;\nrom_iq_est_disable = 0x40001968;\nrom_iq_est_enable = 0x4000196c;\nrom_linear_to_db = 0x40001970;\nrom_loopback_mode_en = 0x40001974;\nrom_mhz2ieee = 0x40001978;\nrom_noise_floor_auto_set = 0x4000197c;\nrom_pbus_debugmode = 0x40001980;\nrom_pbus_force_mode = 0x40001984;\nrom_pbus_force_test = 0x40001988;\nrom_pbus_rd = 0x4000198c;\nrom_pbus_rd_addr = 0x40001990;\nrom_pbus_rd_shift = 0x40001994;\nrom_pbus_set_dco = 0x40001998;\nrom_pbus_set_rxgain = 0x4000199c;\nrom_pbus_workmode = 0x400019a0;\nrom_pbus_xpd_rx_off = 0x400019a4;\nrom_pbus_xpd_rx_on = 0x400019a8;\nrom_pbus_xpd_tx_off = 0x400019ac;\n\/* rom_pbus_xpd_tx_on = 0x400019b0; *\/\nrom_phy_byte_to_word = 0x400019b4;\nrom_phy_disable_cca = 0x400019b8;\nrom_phy_enable_cca = 0x400019bc;\nrom_phy_get_noisefloor = 0x400019c0;\nrom_phy_get_rx_freq = 0x400019c4;\nrom_phy_set_bbfreq_init = 0x400019c8;\nrom_pow_usr = 0x400019cc;\nrom_pwdet_sar2_init = 0x400019d0;\nrom_read_hw_noisefloor = 0x400019d4;\nrom_read_sar_dout = 0x400019d8;\nrom_set_cal_rxdc = 0x400019dc;\nrom_set_chan_cal_interp = 0x400019e0;\nrom_set_loopback_gain = 0x400019e4;\nrom_set_noise_floor = 0x400019e8;\nrom_set_rxclk_en = 0x400019ec;\nrom_set_tx_dig_gain = 0x400019f0;\n\/* rom_set_txcap_reg = 0x400019f4; *\/\nrom_set_txclk_en = 0x400019f8;\nrom_spur_cal = 0x400019fc;\nrom_spur_reg_write_one_tone = 0x40001a00;\nrom_target_power_add_backoff = 0x40001a04;\nrom_tx_pwctrl_bg_init = 0x40001a08;\nrom_txbbgain_to_index = 0x40001a0c;\nrom_wifi_11g_rate_chg = 0x40001a10;\nrom_write_gain_mem = 0x40001a14;\nchip726_phyrom_version = 0x40001a18;\nrom_disable_wifi_agc = 0x40001a1c;\nrom_enable_wifi_agc = 0x40001a20;\nrom_set_tx_gain_table = 0x40001a24;\nrom_bt_index_to_bb = 0x40001a28;\nrom_bt_bb_to_index = 0x40001a2c;\nrom_wr_bt_tx_atten = 0x40001a30;\nrom_wr_bt_tx_gain_mem = 0x40001a34;\nrom_spur_coef_cfg = 0x40001a38;\nrom_bb_bss_cbw40 = 0x40001a3c;\nrom_set_cca = 0x40001a40;\nrom_tx_paon_set = 0x40001a44;\nrom_i2cmst_reg_init = 0x40001a48;\nrom_iq_corr_enable = 0x40001a4c;\nrom_fe_reg_init = 0x40001a50;\n\/* rom_agc_reg_init = 0x40001a54; *\/\n\/* rom_bb_reg_init = 0x40001a58; *\/\nrom_mac_enable_bb = 0x40001a5c;\nrom_bb_wdg_cfg = 0x40001a60;\nrom_force_txon = 0x40001a64;\nrom_fe_txrx_reset = 0x40001a68;\nrom_set_rx_comp = 0x40001a6c;\n\/* rom_set_pbus_reg = 0x40001a70; *\/\nrom_write_chan_freq = 0x40001a74;\n\/* rom_phy_xpd_rf = 0x40001a78; *\/\nrom_set_xpd_sar = 0x40001a7c;\nrom_write_dac_gain2 = 0x40001a80;\nrom_rtc_sar2_init = 0x40001a84;\nrom_get_target_power_offset = 0x40001a88;\n\/* rom_write_txrate_power_offset = 0x40001a8c; *\/\nrom_get_rate_fcc_index = 0x40001a90;\nrom_get_rate_target_power = 0x40001a94;\nrom_write_wifi_dig_gain = 0x40001a98;\nrom_bt_correct_rf_ana_gain = 0x40001a9c;\nrom_pkdet_vol_start = 0x40001aa0;\nrom_read_sar2_code = 0x40001aa4;\nrom_get_sar2_vol = 0x40001aa8;\nrom_get_pll_vol = 0x40001aac;\nrom_get_phy_target_power = 0x40001ab0;\n\/* rom_temp_to_power = 0x40001ab4; *\/\nrom_phy_track_pll_cap = 0x40001ab8;\nrom_phy_pwdet_always_en = 0x40001abc;\nrom_phy_pwdet_onetime_en = 0x40001ac0;\nrom_get_i2c_mst0_mask = 0x40001ac4;\nrom_get_i2c_hostid = 0x40001ac8;\nrom_enter_critical_phy = 0x40001acc;\nrom_exit_critical_phy = 0x40001ad0;\nrom_chip_i2c_readReg_org = 0x40001ad4;\nrom_i2c_paral_set_mst0 = 0x40001ad8;\nrom_i2c_paral_set_read = 0x40001adc;\nrom_i2c_paral_read = 0x40001ae0;\nrom_i2c_paral_write = 0x40001ae4;\nrom_i2c_paral_write_num = 0x40001ae8;\nrom_i2c_paral_write_mask = 0x40001aec;\nrom_bb_bss_cbw40_ana = 0x40001af0;\nrom_chan_to_freq = 0x40001af4;\n\/* rom_open_i2c_xpd = 0x40001af8; *\/\nrom_dac_rate_set = 0x40001afc;\n\/* rom_tsens_read_init = 0x40001b00; *\/\n\/* rom_tsens_code_read = 0x40001b04; *\/\nrom_tsens_index_to_dac = 0x40001b08;\nrom_tsens_index_to_offset = 0x40001b0c;\n\/* rom_tsens_dac_cal = 0x40001b10; *\/\nrom_code_to_temp = 0x40001b14;\nrom_write_pll_cap_mem = 0x40001b18;\nrom_pll_correct_dcap = 0x40001b1c;\nrom_phy_en_hw_set_freq = 0x40001b20;\nrom_phy_dis_hw_set_freq = 0x40001b24;\nrom_pll_vol_cal = 0x40001b28;\n","old_contents":"\/* ROM function interface esp32c3.rom.ld for esp32c3\n *\n *\n * Generated from .\/interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208\n *\n * Compatible with ROM where ECO version equal or greater to 0.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\njtag_cpu_reset_happened = 0x40000020;\nrtc_get_wakeup_cause = 0x40000024;\nrtc_boot_control = 0x40000028;\nrtc_select_apb_bridge = 0x4000002c;\nrtc_unhold_all_pads = 0x40000030;\nset_rtc_memory_crc = 0x40000034;\ncacl_rtc_memory_crc = 0x40000038;\nets_is_print_boot = 0x4000003c;\nets_printf = 0x40000040;\nets_install_putc1 = 0x40000044;\nets_install_uart_printf = 0x40000048;\nets_install_putc2 = 0x4000004c;\nPROVIDE( ets_delay_us = 0x40000050 );\nets_get_stack_info = 0x40000054;\nets_install_lock = 0x40000058;\nets_backup_dma_copy = 0x4000005c;\nets_apb_backup_init_lock_func = 0x40000060;\nUartRxString = 0x40000064;\nuart_tx_one_char = 0x40000068;\nuart_tx_one_char2 = 0x4000006c;\nuart_rx_one_char = 0x40000070;\nuart_rx_one_char_block = 0x40000074;\nuart_rx_readbuff = 0x40000078;\nuartAttach = 0x4000007c;\nuart_tx_flush = 0x40000080;\nuart_tx_wait_idle = 0x40000084;\nuart_div_modify = 0x40000088;\nmultofup = 0x4000008c;\nsoftware_reset = 0x40000090;\nsoftware_reset_cpu = 0x40000094;\nassist_debug_clock_enable = 0x40000098;\nassist_debug_record_enable = 0x4000009c;\nclear_super_wdt_reset_flag = 0x400000a0;\ndisable_default_watchdog = 0x400000a4;\nsend_packet = 0x400000a8;\nrecv_packet = 0x400000ac;\nGetUartDevice = 0x400000b0;\nUartDwnLdProc = 0x400000b4;\nUart_Init = 0x400000b8;\nets_set_user_start = 0x400000bc;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff1fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000c0;\nmz_crc32 = 0x400000c4;\nmz_free = 0x400000c8;\ntdefl_compress = 0x400000cc;\ntdefl_compress_buffer = 0x400000d0;\ntdefl_compress_mem_to_heap = 0x400000d4;\ntdefl_compress_mem_to_mem = 0x400000d8;\ntdefl_compress_mem_to_output = 0x400000dc;\ntdefl_get_adler32 = 0x400000e0;\ntdefl_get_prev_return_status = 0x400000e4;\ntdefl_init = 0x400000e8;\ntdefl_write_image_to_png_file_in_memory = 0x400000ec;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000f0;\ntinfl_decompress = 0x400000f4;\ntinfl_decompress_mem_to_callback = 0x400000f8;\ntinfl_decompress_mem_to_heap = 0x400000fc;\ntinfl_decompress_mem_to_mem = 0x40000100;\n\n\n\/***************************************\n Group tjpgd\n ***************************************\/\n\n\/* Functions *\/\njd_prepare = 0x40000104;\njd_decomp = 0x40000108;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x4000010c );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x40000110 );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000114 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000118 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000011c );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x40000120 );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000124 );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x40000128 );\nPROVIDE( esp_rom_spiflash_write = 0x4000012c );\nPROVIDE( esp_rom_spiflash_read = 0x40000130 );\nPROVIDE( esp_rom_spiflash_config_param = 0x40000134 );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000138 );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x4000013c );\nPROVIDE( esp_rom_spiflash_unlock = 0x40000140 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000144 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x40000148 );\nPROVIDE( esp_rom_spi_flash_update_id = 0x4000014c );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000150 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000154 );\nPROVIDE( esp_rom_spiflash_read_status = 0x40000158 );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x4000015c );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000160 );\nPROVIDE( esp_rom_spiflash_attach = 0x40000164 );\nPROVIDE( spi_flash_get_chip_size = 0x40000168 );\nPROVIDE( spi_flash_guard_set = 0x4000016c );\nPROVIDE( spi_flash_guard_get = 0x40000170 );\nPROVIDE( spi_flash_write_config_set = 0x40000174 );\nPROVIDE( spi_flash_write_config_get = 0x40000178 );\nPROVIDE( spi_flash_safe_write_address_func_set = 0x4000017c );\nPROVIDE( spi_flash_unlock = 0x40000180 );\nPROVIDE( spi_flash_erase_range = 0x40000184 );\nPROVIDE( spi_flash_erase_sector = 0x40000188 );\nPROVIDE( spi_flash_write = 0x4000018c );\nPROVIDE( spi_flash_read = 0x40000190 );\nPROVIDE( spi_flash_write_encrypted = 0x40000194 );\nPROVIDE( spi_flash_read_encrypted = 0x40000198 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x4000019c );\nPROVIDE( spi_flash_mmap_page_num_init = 0x400001a0 );\nPROVIDE( spi_flash_mmap = 0x400001a4 );\nPROVIDE( spi_flash_mmap_pages = 0x400001a8 );\nPROVIDE( spi_flash_munmap = 0x400001ac );\nPROVIDE( spi_flash_mmap_dump = 0x400001b0 );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001b4 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001b8 );\nPROVIDE( spi_flash_cache2phys = 0x400001bc );\nPROVIDE( spi_flash_phys2cache = 0x400001c0 );\nPROVIDE( spi_flash_disable_cache = 0x400001c4 );\nPROVIDE( spi_flash_restore_cache = 0x400001c8 );\nPROVIDE( spi_flash_cache_enabled = 0x400001cc );\nPROVIDE( spi_flash_enable_cache = 0x400001d0 );\nPROVIDE( spi_cache_mode_switch = 0x400001d4 );\nPROVIDE( spi_common_set_dummy_output = 0x400001d8 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001dc );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001e0 );\nPROVIDE( SPIEraseArea = 0x400001e4 );\nPROVIDE( SPILock = 0x400001e8 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001ec );\nPROVIDE( SPI_Common_Command = 0x400001f0 );\nPROVIDE( SPI_WakeUp = 0x400001f4 );\nPROVIDE( SPI_block_erase = 0x400001f8 );\nPROVIDE( SPI_chip_erase = 0x400001fc );\nPROVIDE( SPI_init = 0x40000200 );\nPROVIDE( SPI_page_program = 0x40000204 );\nPROVIDE( SPI_read_data = 0x40000208 );\nPROVIDE( SPI_sector_erase = 0x4000020c );\nPROVIDE( SPI_write_enable = 0x40000210 );\nPROVIDE( SelectSpiFunction = 0x40000214 );\nPROVIDE( SetSpiDrvs = 0x40000218 );\nPROVIDE( Wait_SPI_Idle = 0x4000021c );\nPROVIDE( spi_dummy_len_fix = 0x40000220 );\nPROVIDE( Disable_QMode = 0x40000224 );\nPROVIDE( Enable_QMode = 0x40000228 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group spi_flash_hal\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x4000022c );\nPROVIDE( spi_flash_hal_device_config = 0x40000230 );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000234 );\nPROVIDE( spi_flash_hal_common_command = 0x40000238 );\nPROVIDE( spi_flash_hal_read = 0x4000023c );\nPROVIDE( spi_flash_hal_erase_chip = 0x40000240 );\nPROVIDE( spi_flash_hal_erase_sector = 0x40000244 );\nPROVIDE( spi_flash_hal_erase_block = 0x40000248 );\nPROVIDE( spi_flash_hal_program_page = 0x4000024c );\nPROVIDE( spi_flash_hal_set_write_protect = 0x40000250 );\nPROVIDE( spi_flash_hal_host_idle = 0x40000254 );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x40000258 );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x4000025c );\nPROVIDE( spi_flash_chip_generic_write = 0x40000260 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000264 );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000268 );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x4000026c );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000270 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x40000274 );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x40000278 );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x4000027c );\nPROVIDE( spi_flash_chip_generic_page_program = 0x40000280 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000284 );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000288 );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x4000028c );\nPROVIDE( spi_flash_chip_generic_yield = 0x40000290 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x40000294 );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x40000298 );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x4000029c );\nPROVIDE( spi_flash_chip_generic_read = 0x400002a0 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400002a4 );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400002a8 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400002ac );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400002b0 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400002b4 );\nPROVIDE( spi_flash_common_set_io_mode = 0x400002b8 );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400002bc );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400002c0 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400002c4 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400002c8 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffec );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x400002cc );\nPROVIDE( memspi_host_read_status_hs = 0x400002d0 );\nPROVIDE( memspi_host_flush_cache = 0x400002d4 );\nPROVIDE( memspi_host_erase_chip = 0x400002d8 );\nPROVIDE( memspi_host_erase_sector = 0x400002dc );\nPROVIDE( memspi_host_erase_block = 0x400002e0 );\nPROVIDE( memspi_host_program_page = 0x400002e4 );\nPROVIDE( memspi_host_read = 0x400002e8 );\nPROVIDE( memspi_host_set_write_protect = 0x400002ec );\nPROVIDE( memspi_host_set_max_read_len = 0x400002f0 );\nPROVIDE( memspi_host_read_data_slicer = 0x400002f4 );\nPROVIDE( memspi_host_write_data_slicer = 0x400002f8 );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x400002fc );\nPROVIDE( esp_flash_read_id = 0x40000300 );\nPROVIDE( esp_flash_get_size = 0x40000304 );\nPROVIDE( esp_flash_erase_chip = 0x40000308 );\nPROVIDE( esp_flash_erase_region = 0x4000030c );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000310 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000314 );\nPROVIDE( esp_flash_get_protectable_regions = 0x40000318 );\nPROVIDE( esp_flash_get_protected_region = 0x4000031c );\nPROVIDE( esp_flash_set_protected_region = 0x40000320 );\nPROVIDE( esp_flash_read = 0x40000324 );\nPROVIDE( esp_flash_write = 0x40000328 );\nPROVIDE( esp_flash_write_encrypted = 0x4000032c );\nPROVIDE( esp_flash_read_encrypted = 0x40000330 );\nPROVIDE( esp_flash_get_io_mode = 0x40000334 );\nPROVIDE( esp_flash_set_io_mode = 0x40000338 );\nPROVIDE( spi_flash_boot_attach = 0x4000033c );\nPROVIDE( spi_flash_dump_counters = 0x40000340 );\nPROVIDE( spi_flash_get_counters = 0x40000344 );\nPROVIDE( spi_flash_op_counters_config = 0x40000348 );\nPROVIDE( spi_flash_reset_counters = 0x4000034c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe8 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffe4 );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400004b0 );\nPROVIDE( Cache_Get_Mode = 0x400004b4 );\nPROVIDE( Cache_Address_Through_IBus = 0x400004b8 );\nPROVIDE( Cache_Address_Through_DBus = 0x400004bc );\nPROVIDE( Cache_Set_Default_Mode = 0x400004c0 );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400004c4 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400004c8 );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x400004cc );\nPROVIDE( Cache_Op_Addr = 0x400004d0 );\nPROVIDE( Cache_Invalidate_Addr = 0x400004d4 );\nPROVIDE( Cache_Invalidate_ICache_All = 0x400004d8 );\nPROVIDE( Cache_Mask_All = 0x400004dc );\nPROVIDE( Cache_UnMask_Dram0 = 0x400004e0 );\nPROVIDE( Cache_Suspend_ICache_Autoload = 0x400004e4 );\nPROVIDE( Cache_Resume_ICache_Autoload = 0x400004e8 );\nPROVIDE( Cache_Start_ICache_Preload = 0x400004ec );\nPROVIDE( Cache_ICache_Preload_Done = 0x400004f0 );\nPROVIDE( Cache_End_ICache_Preload = 0x400004f4 );\nPROVIDE( Cache_Config_ICache_Autoload = 0x400004f8 );\nPROVIDE( Cache_Enable_ICache_Autoload = 0x400004fc );\nPROVIDE( Cache_Disable_ICache_Autoload = 0x40000500 );\nPROVIDE( Cache_Enable_ICache_PreLock = 0x40000504 );\nPROVIDE( Cache_Disable_ICache_PreLock = 0x40000508 );\nPROVIDE( Cache_Lock_ICache_Items = 0x4000050c );\nPROVIDE( Cache_Unlock_ICache_Items = 0x40000510 );\nPROVIDE( Cache_Lock_Addr = 0x40000514 );\nPROVIDE( Cache_Unlock_Addr = 0x40000518 );\nPROVIDE( Cache_Disable_ICache = 0x4000051c );\nPROVIDE( Cache_Enable_ICache = 0x40000520 );\nPROVIDE( Cache_Suspend_ICache = 0x40000524 );\nPROVIDE( Cache_Resume_ICache = 0x40000528 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x4000052c );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x40000530 );\nPROVIDE( Cache_Pms_Lock = 0x40000534 );\nPROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000538 );\nPROVIDE( Cache_Ibus_Pms_Set_Attr = 0x4000053c );\nPROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000540 );\nPROVIDE( Cache_Dbus_Pms_Set_Attr = 0x40000544 );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000548 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x4000054c );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x40000550 );\nPROVIDE( Cache_Owner_Init = 0x40000554 );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000558 );\nPROVIDE( Cache_MMU_Init = 0x4000055c );\nPROVIDE( Cache_Ibus_MMU_Set = 0x40000560 );\nPROVIDE( Cache_Dbus_MMU_Set = 0x40000564 );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000568 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x4000056c );\nPROVIDE( Cache_Get_Virtual_Addr = 0x40000570 );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x40000574 );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000578 );\nPROVIDE( Cache_Get_Memory_value = 0x4000057c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd8 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd4 );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x40000580;\nets_get_cpu_frequency = 0x40000584;\nets_update_cpu_frequency = 0x40000588;\nets_get_printf_channel = 0x4000058c;\nets_get_xtal_div = 0x40000590;\nets_set_xtal_div = 0x40000594;\nets_get_xtal_freq = 0x40000598;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x4000059c;\ngpio_matrix_in = 0x400005a0;\ngpio_matrix_out = 0x400005a4;\ngpio_output_disable = 0x400005a8;\ngpio_output_enable = 0x400005ac;\ngpio_output_set = 0x400005b0;\ngpio_pad_hold = 0x400005b4;\ngpio_pad_input_disable = 0x400005b8;\ngpio_pad_input_enable = 0x400005bc;\ngpio_pad_pulldown = 0x400005c0;\ngpio_pad_pullup = 0x400005c4;\ngpio_pad_select_gpio = 0x400005c8;\ngpio_pad_set_drv = 0x400005cc;\ngpio_pad_unhold = 0x400005d0;\ngpio_pin_wakeup_disable = 0x400005d4;\ngpio_pin_wakeup_enable = 0x400005d8;\ngpio_bypass_matrix_in = 0x400005dc;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400005e0;\nesprv_intc_int_set_threshold = 0x400005e4;\nesprv_intc_int_enable = 0x400005e8;\nesprv_intc_int_disable = 0x400005ec;\nesprv_intc_int_set_type = 0x400005f0;\nintr_matrix_set = 0x400005f4;\nets_intr_lock = 0x400005f8;\nets_intr_unlock = 0x400005fc;\nPROVIDE( intr_handler_set = 0x40000600 );\nets_isr_attach = 0x40000604;\nets_isr_mask = 0x40000608;\nets_isr_unmask = 0x4000060c;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\nmd5_vector = 0x40000610;\nMD5Init = 0x40000614;\nMD5Update = 0x40000618;\nMD5Final = 0x4000061c;\nhmac_md5_vector = 0x40000620;\nhmac_md5 = 0x40000624;\ncrc32_le = 0x40000628;\ncrc32_be = 0x4000062c;\ncrc16_le = 0x40000630;\ncrc16_be = 0x40000634;\ncrc8_le = 0x40000638;\ncrc8_be = 0x4000063c;\nesp_crc8 = 0x40000640;\nets_sha_enable = 0x40000644;\nets_sha_disable = 0x40000648;\nets_sha_get_state = 0x4000064c;\nets_sha_init = 0x40000650;\nets_sha_process = 0x40000654;\nets_sha_starts = 0x40000658;\nets_sha_update = 0x4000065c;\nets_sha_finish = 0x40000660;\nets_sha_clone = 0x40000664;\nets_hmac_enable = 0x40000668;\nets_hmac_disable = 0x4000066c;\nets_hmac_calculate_message = 0x40000670;\nets_hmac_calculate_downstream = 0x40000674;\nets_hmac_invalidate_downstream = 0x40000678;\nets_jtag_enable_temporarily = 0x4000067c;\nets_aes_enable = 0x40000680;\nets_aes_disable = 0x40000684;\nets_aes_setkey = 0x40000688;\nets_aes_block = 0x4000068c;\nets_bigint_enable = 0x40000690;\nets_bigint_disable = 0x40000694;\nets_bigint_multiply = 0x40000698;\nets_bigint_modmult = 0x4000069c;\nets_bigint_modexp = 0x400006a0;\nets_bigint_wait_finish = 0x400006a4;\nets_bigint_getz = 0x400006a8;\nets_ds_enable = 0x400006ac;\nets_ds_disable = 0x400006b0;\nets_ds_start_sign = 0x400006b4;\nets_ds_is_busy = 0x400006b8;\nets_ds_finish_sign = 0x400006bc;\nets_ds_encrypt_params = 0x400006c0;\nets_aes_setkey_dec = 0x400006c4;\nets_aes_setkey_enc = 0x400006c8;\nets_mgf1_sha256 = 0x400006cc;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x400006d0;\nets_efuse_program = 0x400006d4;\nets_efuse_clear_program_registers = 0x400006d8;\nets_efuse_write_key = 0x400006dc;\nets_efuse_get_read_register_address = 0x400006e0;\nets_efuse_get_key_purpose = 0x400006e4;\nets_efuse_key_block_unused = 0x400006e8;\nets_efuse_find_unused_key_block = 0x400006ec;\nets_efuse_rs_calculate = 0x400006f0;\nets_efuse_count_unused_key_blocks = 0x400006f4;\nets_efuse_secure_boot_enabled = 0x400006f8;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x400006fc;\nets_efuse_cache_encryption_enabled = 0x40000700;\nets_efuse_download_modes_disabled = 0x40000704;\nets_efuse_find_purpose = 0x40000708;\nets_efuse_flash_opi_5pads_power_sel_vddspi = 0x4000070c;\nets_efuse_force_send_resume = 0x40000710;\nets_efuse_get_flash_delay_us = 0x40000714;\nets_efuse_get_mac = 0x40000718;\nets_efuse_get_spiconfig = 0x4000071c;\nets_efuse_usb_print_is_disabled = 0x40000720;\nets_efuse_get_uart_print_channel = 0x40000724;\nets_efuse_get_uart_print_control = 0x40000728;\nets_efuse_get_wp_pad = 0x4000072c;\nets_efuse_legacy_spi_boot_mode_disabled = 0x40000730;\nets_efuse_security_download_modes_enabled = 0x40000734;\nets_efuse_set_timing = 0x40000738;\nets_efuse_jtag_disabled = 0x4000073c;\nets_efuse_usb_download_mode_disabled = 0x40000740;\nets_efuse_usb_module_disabled = 0x40000744;\nets_efuse_usb_device_disabled = 0x40000748;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_emsa_pss_verify = 0x4000074c;\nets_rsa_pss_verify = 0x40000750;\nets_secure_boot_verify_bootloader_with_keys = 0x40000754;\nets_secure_boot_verify_signature = 0x40000758;\nets_secure_boot_read_key_digests = 0x4000075c;\nets_secure_boot_revoke_public_key_digest = 0x40000760;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( usb_uart_rx_one_char = 0x400008cc );\nPROVIDE( usb_uart_rx_one_char_block = 0x400008d0 );\nPROVIDE( usb_uart_tx_flush = 0x400008d4 );\nPROVIDE( usb_uart_tx_one_char = 0x400008d8 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( g_uart_print = 0x3fcdffd1 );\nPROVIDE( g_usb_print = 0x3fcdffd0 );\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nbt_rf_coex_get_dft_cfg = 0x400008dc;\nbt_rf_coex_hooks_p_set = 0x400008e0;\nbtdm_con_maxevtime_cal_impl = 0x400008e4;\nbtdm_controller_get_compile_version_impl = 0x400008e8;\nbtdm_controller_rom_data_init = 0x400008ec;\nbtdm_dis_privacy_err_report_impl = 0x400008f0;\nbtdm_disable_adv_delay_impl = 0x400008f4;\nbtdm_enable_scan_continue_impl = 0x400008f8;\nbtdm_enable_scan_forever_impl = 0x400008fc;\nbtdm_get_power_state_impl = 0x40000900;\nbtdm_get_prevent_sleep_flag_impl = 0x40000904;\nbtdm_power_state_active_impl = 0x40000908;\nbtdm_switch_phy_coded_impl = 0x4000090c;\nhci_acl_data_handler = 0x40000910;\nhci_disconnect_cmd_handler = 0x40000914;\nhci_le_con_upd_cmd_handler = 0x40000918;\nhci_le_ltk_req_neg_reply_cmd_handler = 0x4000091c;\nhci_le_ltk_req_reply_cmd_handler = 0x40000920;\nhci_le_rd_chnl_map_cmd_handler = 0x40000924;\nhci_le_rd_phy_cmd_handler = 0x40000928;\nhci_le_rd_rem_feats_cmd_handler = 0x4000092c;\nhci_le_rem_con_param_req_neg_reply_cmd_handler = 0x40000930;\nhci_le_rem_con_param_req_reply_cmd_handler = 0x40000934;\nhci_le_set_data_len_cmd_handler = 0x40000938;\nhci_le_set_phy_cmd_handler = 0x4000093c;\nhci_le_start_enc_cmd_handler = 0x40000940;\nhci_rd_auth_payl_to_cmd_handler = 0x40000944;\nhci_rd_rem_ver_info_cmd_handler = 0x40000948;\nhci_rd_rssi_cmd_handler = 0x4000094c;\nhci_rd_tx_pwr_lvl_cmd_handler = 0x40000950;\nhci_vs_set_pref_slave_evt_dur_cmd_handler = 0x40000954;\nhci_vs_set_pref_slave_latency_cmd_handler = 0x40000958;\nhci_wr_auth_payl_to_cmd_handler = 0x4000095c;\nll_channel_map_ind_handler = 0x40000960;\nll_connection_param_req_handler = 0x40000964;\nll_connection_param_rsp_handler = 0x40000968;\nll_connection_update_ind_handler = 0x4000096c;\nll_enc_req_handler = 0x40000970;\nll_enc_rsp_handler = 0x40000974;\nll_feature_req_handler = 0x40000978;\nll_feature_rsp_handler = 0x4000097c;\nll_length_req_handler = 0x40000980;\nll_length_rsp_handler = 0x40000984;\nll_min_used_channels_ind_handler = 0x40000988;\nll_pause_enc_req_handler = 0x4000098c;\nll_pause_enc_rsp_handler = 0x40000990;\nll_phy_req_handler = 0x40000994;\nll_phy_rsp_handler = 0x40000998;\nll_phy_update_ind_handler = 0x4000099c;\nll_ping_req_handler = 0x400009a0;\nll_ping_rsp_handler = 0x400009a4;\nll_slave_feature_req_handler = 0x400009a8;\nll_start_enc_req_handler = 0x400009ac;\nll_start_enc_rsp_handler = 0x400009b0;\nll_terminate_ind_handler = 0x400009b4;\nll_version_ind_handler = 0x400009b8;\nllc_auth_payl_nearly_to_handler = 0x400009bc;\nllc_auth_payl_real_to_handler = 0x400009c0;\nllc_encrypt_ind_handler = 0x400009c4;\nllc_hci_command_handler_wrapper = 0x400009c8;\nllc_ll_connection_param_req_pdu_send = 0x400009cc;\nllc_ll_connection_param_rsp_pdu_send = 0x400009d0;\nllc_ll_connection_update_ind_pdu_send = 0x400009d4;\nllc_ll_enc_req_pdu_send = 0x400009d8;\nllc_ll_enc_rsp_pdu_send = 0x400009dc;\nllc_ll_feature_req_pdu_send = 0x400009e0;\nllc_ll_feature_rsp_pdu_send = 0x400009e4;\nllc_ll_length_req_pdu_send = 0x400009e8;\nllc_ll_length_rsp_pdu_send = 0x400009ec;\nllc_ll_pause_enc_req_pdu_send = 0x400009f0;\nllc_ll_pause_enc_rsp_pdu_send = 0x400009f4;\nllc_ll_phy_req_pdu_send = 0x400009f8;\nllc_ll_phy_rsp_pdu_send = 0x400009fc;\nllc_ll_ping_req_pdu_send = 0x40000a00;\nllc_ll_ping_rsp_pdu_send = 0x40000a04;\nllc_ll_start_enc_req_pdu_send = 0x40000a08;\nllc_ll_start_enc_rsp_pdu_send = 0x40000a0c;\nllc_ll_terminate_ind_pdu_send = 0x40000a10;\nllc_ll_unknown_rsp_pdu_send = 0x40000a14;\nllc_llcp_ch_map_update_ind_pdu_send = 0x40000a18;\nllc_llcp_phy_upd_ind_pdu_send = 0x40000a1c;\nllc_llcp_version_ind_pdu_send = 0x40000a20;\nllc_op_ch_map_upd_ind_handler = 0x40000a24;\nllc_op_con_upd_ind_handler = 0x40000a28;\nllc_op_disconnect_ind_handler = 0x40000a2c;\nllc_op_dl_upd_ind_handler = 0x40000a30;\nllc_op_encrypt_ind_handler = 0x40000a34;\nllc_op_feats_exch_ind_handler = 0x40000a38;\nllc_op_le_ping_ind_handler = 0x40000a3c;\nllc_op_phy_upd_ind_handler = 0x40000a40;\nllc_op_ver_exch_ind_handler = 0x40000a44;\nllc_stopped_ind_handler = 0x40000a48;\nlld_acl_rx_ind_handler = 0x40000a4c;\nlld_acl_tx_cfm_handler = 0x40000a50;\nlld_adv_end_ind_handler = 0x40000a54;\nlld_adv_rep_ind_handler = 0x40000a58;\nlld_ch_map_upd_cfm_handler = 0x40000a5c;\nlld_con_estab_ind_handler = 0x40000a60;\nlld_con_evt_sd_evt_time_set = 0x40000a64;\nlld_con_offset_upd_ind_handler = 0x40000a68;\nlld_con_param_upd_cfm_handler = 0x40000a6c;\nlld_disc_ind_handler = 0x40000a70;\nlld_init_end_ind_handler = 0x40000a74;\nlld_llcp_rx_ind_handler_wrapper = 0x40000a78;\nlld_llcp_tx_cfm_handler = 0x40000a7c;\nlld_per_adv_end_ind_handler = 0x40000a80;\nlld_per_adv_rep_ind_handler = 0x40000a84;\nlld_per_adv_rx_end_ind_handler = 0x40000a88;\nlld_phy_coded_500k_get = 0x40000a8c;\nlld_phy_upd_cfm_handler = 0x40000a90;\nlld_scan_end_ind_handler = 0x40000a94;\nlld_scan_req_ind_handler = 0x40000a98;\nlld_sync_start_req_handler = 0x40000a9c;\nlld_test_end_ind_handler = 0x40000aa0;\nlld_update_rxbuf_handler = 0x40000aa4;\nllm_ch_map_update_ind_handler = 0x40000aa8;\nllm_hci_command_handler_wrapper = 0x40000aac;\nllm_scan_period_to_handler = 0x40000ab0;\nr_Add2SelfBigHex256 = 0x40000ab4;\nr_AddBigHex256 = 0x40000ab8;\nr_AddBigHexModP256 = 0x40000abc;\nr_AddP256 = 0x40000ac0;\nr_AddPdiv2_256 = 0x40000ac4;\nr_GF_Jacobian_Point_Addition256 = 0x40000ac8;\nr_GF_Jacobian_Point_Double256 = 0x40000acc;\nr_GF_Point_Jacobian_To_Affine256 = 0x40000ad0;\nr_MultiplyBigHexByUint32_256 = 0x40000ad4;\nr_MultiplyBigHexModP256 = 0x40000ad8;\nr_MultiplyByU16ModP256 = 0x40000adc;\nr_SubtractBigHex256 = 0x40000ae0;\nr_SubtractBigHexMod256 = 0x40000ae4;\nr_SubtractBigHexUint32_256 = 0x40000ae8;\nr_SubtractFromSelfBigHex256 = 0x40000aec;\nr_SubtractFromSelfBigHexSign256 = 0x40000af0;\nr_aes_alloc = 0x40000af4;\nr_aes_ccm_continue = 0x40000af8;\nr_aes_ccm_process_e = 0x40000afc;\nr_aes_ccm_xor_128_lsb = 0x40000b00;\nr_aes_ccm_xor_128_msb = 0x40000b04;\nr_aes_cmac_continue = 0x40000b08;\nr_aes_cmac_start = 0x40000b0c;\nr_aes_k1_continue = 0x40000b10;\nr_aes_k2_continue = 0x40000b14;\nr_aes_k3_continue = 0x40000b18;\nr_aes_k4_continue = 0x40000b1c;\nr_aes_shift_left_128 = 0x40000b20;\nr_aes_start = 0x40000b24;\nr_aes_xor_128 = 0x40000b28;\nr_assert_err = 0x40000b2c;\nr_assert_param = 0x40000b30;\nr_assert_warn = 0x40000b34;\nr_bigHexInversion256 = 0x40000b38;\nr_ble_sw_cca_check_isr = 0x40000b3c;\nr_ble_util_buf_acl_tx_alloc = 0x40000b40;\nr_ble_util_buf_acl_tx_elt_get = 0x40000b44;\nr_ble_util_buf_acl_tx_free = 0x40000b48;\nr_ble_util_buf_acl_tx_free_in_isr = 0x40000b4c;\nr_ble_util_buf_adv_tx_alloc = 0x40000b50;\nr_ble_util_buf_adv_tx_free = 0x40000b54;\nr_ble_util_buf_adv_tx_free_in_isr = 0x40000b58;\nr_ble_util_buf_env_deinit = 0x40000b5c;\nr_ble_util_buf_env_init = 0x40000b60;\nr_ble_util_buf_get_rx_buf_nb = 0x40000b64;\nr_ble_util_buf_get_rx_buf_size = 0x40000b68;\nr_ble_util_buf_llcp_tx_alloc = 0x40000b6c;\nr_ble_util_buf_llcp_tx_free = 0x40000b70;\nr_ble_util_buf_rx_alloc = 0x40000b74;\nr_ble_util_buf_rx_alloc_in_isr = 0x40000b78;\nr_ble_util_buf_rx_free = 0x40000b7c;\nr_ble_util_buf_rx_free_in_isr = 0x40000b80;\nr_ble_util_buf_set_rx_buf_nb = 0x40000b84;\nr_ble_util_buf_set_rx_buf_size = 0x40000b88;\nr_ble_util_data_rx_buf_reset = 0x40000b8c;\nr_bt_bb_get_intr_mask = 0x40000b90;\nr_bt_bb_intr_clear = 0x40000b94;\nr_bt_bb_intr_mask_set = 0x40000b98;\nr_bt_bb_isr = 0x40000b9c;\nr_bt_rf_coex_cfg_set = 0x40000ba0;\nr_bt_rf_coex_conn_dynamic_pti_en_get = 0x40000ba4;\nr_bt_rf_coex_conn_phy_coded_data_time_limit_en_get = 0x40000ba8;\nr_bt_rf_coex_ext_adv_dynamic_pti_en_get = 0x40000bac;\nr_bt_rf_coex_ext_scan_dynamic_pti_en_get = 0x40000bb0;\nr_bt_rf_coex_legacy_adv_dynamic_pti_en_get = 0x40000bb4;\nr_bt_rf_coex_per_adv_dynamic_pti_en_get = 0x40000bb8;\nr_bt_rf_coex_pti_table_get = 0x40000bbc;\nr_bt_rf_coex_st_param_get = 0x40000bc0;\nr_bt_rf_coex_st_param_set = 0x40000bc4;\nr_bt_rf_coex_sync_scan_dynamic_pti_en_get = 0x40000bc8;\nr_bt_rma_apply_rule_cs_fmt = 0x40000bcc;\nr_bt_rma_apply_rule_cs_idx = 0x40000bd0;\nr_bt_rma_configure = 0x40000bd4;\nr_bt_rma_deregister_rule_cs_fmt = 0x40000bd8;\nr_bt_rma_deregister_rule_cs_idx = 0x40000bdc;\nr_bt_rma_get_ant_by_act = 0x40000be0;\nr_bt_rma_init = 0x40000be4;\nr_bt_rma_register_rule_cs_fmt = 0x40000be8;\nr_bt_rma_register_rule_cs_idx = 0x40000bec;\nr_bt_rtp_apply_rule_cs_fmt = 0x40000bf0;\nr_bt_rtp_apply_rule_cs_idx = 0x40000bf4;\nr_bt_rtp_deregister_rule_cs_fmt = 0x40000bf8;\nr_bt_rtp_deregister_rule_cs_idx = 0x40000bfc;\nr_bt_rtp_get_txpwr_idx_by_act = 0x40000c00;\nr_bt_rtp_init = 0x40000c04;\nr_bt_rtp_register_rule_cs_fmt = 0x40000c08;\nr_bt_rtp_register_rule_cs_idx = 0x40000c0c;\nr_btdm_isr = 0x40000c10;\nr_btdm_task_post = 0x40000c14;\nr_btdm_task_post_from_isr = 0x40000c18;\nr_btdm_task_recycle = 0x40000c1c;\nr_cali_phase_match_p = 0x40000c20;\nr_cmp_abs_time = 0x40000c24;\nr_cmp_dest_id = 0x40000c28;\nr_cmp_timer_id = 0x40000c2c;\nr_co_bdaddr_compare = 0x40000c30;\nr_co_ble_pkt_dur_in_us = 0x40000c34;\nr_co_list_extract = 0x40000c38;\nr_co_list_extract_after = 0x40000c3c;\nr_co_list_extract_sublist = 0x40000c40;\nr_co_list_find = 0x40000c44;\nr_co_list_init = 0x40000c48;\nr_co_list_insert_after = 0x40000c4c;\nr_co_list_insert_before = 0x40000c50;\nr_co_list_merge = 0x40000c54;\nr_co_list_pool_init = 0x40000c58;\nr_co_list_pop_front = 0x40000c5c;\nr_co_list_push_back = 0x40000c60;\nr_co_list_push_back_sublist = 0x40000c64;\nr_co_list_push_front = 0x40000c68;\nr_co_list_size = 0x40000c6c;\nr_co_nb_good_le_channels = 0x40000c70;\nr_co_util_pack = 0x40000c74;\nr_co_util_read_array_size = 0x40000c78;\nr_co_util_unpack = 0x40000c7c;\nr_dbg_env_deinit = 0x40000c80;\nr_dbg_env_init = 0x40000c84;\nr_dbg_platform_reset_complete = 0x40000c88;\nr_dl_upd_proc_start = 0x40000c8c;\nr_dump_data = 0x40000c90;\nr_ecc_abort_key256_generation = 0x40000c94;\nr_ecc_gen_new_public_key = 0x40000c98;\nr_ecc_gen_new_secret_key = 0x40000c9c;\nr_ecc_generate_key256 = 0x40000ca0;\nr_ecc_get_debug_Keys = 0x40000ca4;\nr_ecc_init = 0x40000ca8;\nr_ecc_is_valid_point = 0x40000cac;\nr_ecc_multiplication_event_handler = 0x40000cb0;\nr_ecc_point_multiplication_win_256 = 0x40000cb4;\nr_emi_alloc_em_mapping_by_offset = 0x40000cb8;\nr_emi_base_reg_lut_show = 0x40000cbc;\nr_emi_em_base_reg_show = 0x40000cc0;\nr_emi_free_em_mapping_by_offset = 0x40000cc4;\nr_emi_get_em_mapping_idx_by_offset = 0x40000cc8;\nr_emi_get_mem_addr_by_offset = 0x40000ccc;\nr_emi_overwrite_em_mapping_by_offset = 0x40000cd0;\nr_esp_vendor_hci_command_handler = 0x40000cd4;\nr_get_stack_usage = 0x40000cd8;\nr_h4tl_acl_hdr_rx_evt_handler = 0x40000cdc;\nr_h4tl_cmd_hdr_rx_evt_handler = 0x40000ce0;\nr_h4tl_cmd_pld_rx_evt_handler = 0x40000ce4;\nr_h4tl_eif_io_event_post = 0x40000ce8;\nr_h4tl_eif_register = 0x40000cec;\nr_h4tl_init = 0x40000cf0;\nr_h4tl_out_of_sync = 0x40000cf4;\nr_h4tl_out_of_sync_check = 0x40000cf8;\nr_h4tl_read_hdr = 0x40000cfc;\nr_h4tl_read_next_out_of_sync = 0x40000d00;\nr_h4tl_read_payl = 0x40000d04;\nr_h4tl_read_start = 0x40000d08;\nr_h4tl_rx_acl_hdr_extract = 0x40000d0c;\nr_h4tl_rx_cmd_hdr_extract = 0x40000d10;\nr_h4tl_rx_done = 0x40000d14;\nr_h4tl_start = 0x40000d18;\nr_h4tl_stop = 0x40000d1c;\nr_h4tl_tx_done = 0x40000d20;\nr_h4tl_tx_evt_handler = 0x40000d24;\nr_h4tl_write = 0x40000d28;\nr_hci_acl_tx_data_alloc = 0x40000d2c;\nr_hci_acl_tx_data_received = 0x40000d30;\nr_hci_basic_cmd_send_2_controller = 0x40000d34;\nr_hci_ble_adv_report_filter_check = 0x40000d38;\nr_hci_ble_adv_report_tx_check = 0x40000d3c;\nr_hci_ble_conhdl_register = 0x40000d40;\nr_hci_ble_conhdl_unregister = 0x40000d44;\nr_hci_build_acl_data = 0x40000d48;\nr_hci_build_cc_evt = 0x40000d4c;\nr_hci_build_cs_evt = 0x40000d50;\nr_hci_build_evt = 0x40000d54;\nr_hci_build_le_evt = 0x40000d58;\nr_hci_cmd_get_max_param_size = 0x40000d5c;\nr_hci_cmd_received = 0x40000d60;\nr_hci_cmd_reject = 0x40000d64;\nr_hci_evt_mask_check = 0x40000d68;\nr_hci_evt_mask_set = 0x40000d6c;\nr_hci_fc_acl_buf_size_set = 0x40000d70;\nr_hci_fc_acl_en = 0x40000d74;\nr_hci_fc_acl_packet_sent = 0x40000d78;\nr_hci_fc_check_host_available_nb_acl_packets = 0x40000d7c;\nr_hci_fc_host_nb_acl_pkts_complete = 0x40000d80;\nr_hci_fc_init = 0x40000d84;\nr_hci_look_for_cmd_desc = 0x40000d88;\nr_hci_look_for_evt_desc = 0x40000d8c;\nr_hci_look_for_le_evt_desc = 0x40000d90;\nr_hci_look_for_le_evt_desc_esp = 0x40000d94;\nr_hci_pack_bytes = 0x40000d98;\nr_hci_register_vendor_desc_tab = 0x40000d9c;\nr_hci_send_2_controller = 0x40000da0;\nr_hci_send_2_host = 0x40000da4;\nr_hci_tl_c2h_data_flow_on = 0x40000da8;\nr_hci_tl_cmd_hdr_rx_evt_handler = 0x40000dac;\nr_hci_tl_cmd_pld_rx_evt_handler = 0x40000db0;\nr_hci_tl_get_pkt = 0x40000db4;\nr_hci_tl_hci_pkt_handler = 0x40000db8;\nr_hci_tl_hci_tx_done_evt_handler = 0x40000dbc;\nr_hci_tl_inc_nb_h2c_cmd_pkts = 0x40000dc0;\nr_hci_tl_save_pkt = 0x40000dc4;\nr_hci_tl_send = 0x40000dc8;\nr_hci_tx_done = 0x40000dcc;\nr_hci_tx_start = 0x40000dd0;\nr_hci_tx_trigger = 0x40000dd4;\nr_isValidSecretKey_256 = 0x40000dd8;\nr_ke_check_malloc = 0x40000ddc;\nr_ke_event_callback_set = 0x40000de0;\nr_ke_event_clear = 0x40000de4;\nr_ke_event_flush = 0x40000de8;\nr_ke_event_get = 0x40000dec;\nr_ke_event_get_all = 0x40000df0;\nr_ke_event_init = 0x40000df4;\nr_ke_event_schedule = 0x40000df8;\nr_ke_event_set = 0x40000dfc;\nr_ke_flush = 0x40000e00;\nr_ke_free = 0x40000e04;\nr_ke_handler_search = 0x40000e08;\nr_ke_init = 0x40000e0c;\nr_ke_is_free = 0x40000e10;\nr_ke_malloc = 0x40000e14;\nr_ke_mem_init = 0x40000e18;\nr_ke_mem_is_empty = 0x40000e1c;\nr_ke_mem_is_in_heap = 0x40000e20;\nr_ke_msg_alloc = 0x40000e24;\nr_ke_msg_dest_id_get = 0x40000e28;\nr_ke_msg_discard = 0x40000e2c;\nr_ke_msg_forward = 0x40000e30;\nr_ke_msg_forward_new_id = 0x40000e34;\nr_ke_msg_free = 0x40000e38;\nr_ke_msg_in_queue = 0x40000e3c;\nr_ke_msg_save = 0x40000e40;\nr_ke_msg_send = 0x40000e44;\nr_ke_msg_send_basic = 0x40000e48;\nr_ke_msg_src_id_get = 0x40000e4c;\nr_ke_queue_extract = 0x40000e50;\nr_ke_queue_insert = 0x40000e54;\nr_ke_sleep_check = 0x40000e58;\nr_ke_state_get = 0x40000e5c;\nr_ke_state_set = 0x40000e60;\nr_ke_task_check = 0x40000e64;\nr_ke_task_create = 0x40000e68;\nr_ke_task_delete = 0x40000e6c;\nr_ke_task_handler_get = 0x40000e70;\nr_ke_task_init = 0x40000e74;\nr_ke_task_msg_flush = 0x40000e78;\nr_ke_task_saved_update = 0x40000e7c;\nr_ke_task_schedule = 0x40000e80;\nr_ke_time = 0x40000e84;\nr_ke_time_cmp = 0x40000e88;\nr_ke_time_past = 0x40000e8c;\nr_ke_timer_active = 0x40000e90;\nr_ke_timer_adjust_all = 0x40000e94;\nr_ke_timer_clear = 0x40000e98;\nr_ke_timer_init = 0x40000e9c;\nr_ke_timer_schedule = 0x40000ea0;\nr_ke_timer_set = 0x40000ea4;\nr_led_init = 0x40000ea8;\nr_led_set_all = 0x40000eac;\nr_llc_aes_res_cb = 0x40000eb0;\nr_llc_ch_map_up_proc_err_cb = 0x40000eb4;\nr_llc_cleanup = 0x40000eb8;\nr_llc_cmd_cmp_send = 0x40000ebc;\nr_llc_cmd_stat_send = 0x40000ec0;\nr_llc_con_move_cbk = 0x40000ec4;\nr_llc_con_plan_set_update = 0x40000ec8;\nr_llc_con_upd_param_in_range = 0x40000ecc;\nr_llc_disconnect = 0x40000ed0;\nr_llc_disconnect_end = 0x40000ed4;\nr_llc_disconnect_proc_continue = 0x40000ed8;\nr_llc_disconnect_proc_err_cb = 0x40000edc;\nr_llc_dl_chg_check = 0x40000ee0;\nr_llc_dle_proc_err_cb = 0x40000ee4;\nr_llc_feats_exch_proc_err_cb = 0x40000ee8;\nr_llc_hci_cmd_handler_tab_p_get = 0x40000eec;\nr_llc_hci_command_handler = 0x40000ef0;\nr_llc_hci_con_param_req_evt_send = 0x40000ef4;\nr_llc_hci_con_upd_info_send = 0x40000ef8;\nr_llc_hci_disconnected_dis = 0x40000efc;\nr_llc_hci_dl_upd_info_send = 0x40000f00;\nr_llc_hci_enc_evt_send = 0x40000f04;\nr_llc_hci_feats_info_send = 0x40000f08;\nr_llc_hci_le_phy_upd_cmp_evt_send = 0x40000f0c;\nr_llc_hci_ltk_request_evt_send = 0x40000f10;\nr_llc_hci_nb_cmp_pkts_evt_send = 0x40000f14;\nr_llc_hci_version_info_send = 0x40000f18;\nr_llc_init_term_proc = 0x40000f1c;\nr_llc_iv_skd_rand_gen = 0x40000f20;\nr_llc_le_ping_proc_continue = 0x40000f24;\nr_llc_le_ping_proc_err_cb = 0x40000f28;\nr_llc_le_ping_restart = 0x40000f2c;\nr_llc_le_ping_set = 0x40000f30;\nr_llc_ll_pause_enc_rsp_ack_handler = 0x40000f34;\nr_llc_ll_reject_ind_ack_handler = 0x40000f38;\nr_llc_ll_reject_ind_pdu_send = 0x40000f3c;\nr_llc_ll_start_enc_rsp_ack_handler = 0x40000f40;\nr_llc_ll_terminate_ind_ack = 0x40000f44;\nr_llc_ll_unknown_ind_handler = 0x40000f48;\nr_llc_llcp_send = 0x40000f4c;\nr_llc_llcp_state_set = 0x40000f50;\nr_llc_llcp_trans_timer_set = 0x40000f54;\nr_llc_llcp_tx_check = 0x40000f58;\nr_llc_loc_ch_map_proc_continue = 0x40000f5c;\nr_llc_loc_con_upd_proc_continue = 0x40000f60;\nr_llc_loc_con_upd_proc_err_cb = 0x40000f64;\nr_llc_loc_dl_upd_proc_continue = 0x40000f68;\nr_llc_loc_encrypt_proc_continue = 0x40000f6c;\nr_llc_loc_encrypt_proc_err_cb = 0x40000f70;\nr_llc_loc_feats_exch_proc_continue = 0x40000f74;\nr_llc_loc_phy_upd_proc_continue = 0x40000f78;\nr_llc_loc_phy_upd_proc_err_cb = 0x40000f7c;\nr_llc_msg_handler_tab_p_get = 0x40000f80;\nr_llc_pref_param_compute = 0x40000f84;\nr_llc_proc_collision_check = 0x40000f88;\nr_llc_proc_err_ind = 0x40000f8c;\nr_llc_proc_get = 0x40000f90;\nr_llc_proc_id_get = 0x40000f94;\nr_llc_proc_reg = 0x40000f98;\nr_llc_proc_state_get = 0x40000f9c;\nr_llc_proc_state_set = 0x40000fa0;\nr_llc_proc_timer_pause_set = 0x40000fa4;\nr_llc_proc_timer_set = 0x40000fa8;\nr_llc_proc_unreg = 0x40000fac;\nr_llc_rem_ch_map_proc_continue = 0x40000fb0;\nr_llc_rem_con_upd_proc_continue = 0x40000fb4;\nr_llc_rem_con_upd_proc_err_cb = 0x40000fb8;\nr_llc_rem_dl_upd_proc = 0x40000fbc;\nr_llc_rem_encrypt_proc_continue = 0x40000fc0;\nr_llc_rem_encrypt_proc_err_cb = 0x40000fc4;\nr_llc_rem_phy_upd_proc_continue = 0x40000fc8;\nr_llc_rem_phy_upd_proc_err_cb = 0x40000fcc;\nr_llc_role_get = 0x40000fd0;\nr_llc_sk_gen = 0x40000fd4;\nr_llc_start = 0x40000fd8;\nr_llc_stop = 0x40000fdc;\nr_llc_ver_exch_loc_proc_continue = 0x40000fe0;\nr_llc_ver_proc_err_cb = 0x40000fe4;\nr_llcp_pdu_handler_tab_p_get = 0x40000fe8;\nr_lld_aa_gen = 0x40000fec;\nr_lld_adv_adv_data_set = 0x40000ff0;\nr_lld_adv_adv_data_update = 0x40000ff4;\nr_lld_adv_aux_ch_idx_set = 0x40000ff8;\nr_lld_adv_aux_evt_canceled_cbk = 0x40000ffc;\nr_lld_adv_aux_evt_start_cbk = 0x40001000;\nr_lld_adv_coex_check_ext_adv_synced = 0x40001004;\nr_lld_adv_coex_env_reset = 0x40001008;\nr_lld_adv_duration_update = 0x4000100c;\nr_lld_adv_dynamic_pti_process = 0x40001010;\nr_lld_adv_end = 0x40001014;\nr_lld_adv_evt_canceled_cbk = 0x40001018;\nr_lld_adv_evt_start_cbk = 0x4000101c;\nr_lld_adv_ext_chain_construct = 0x40001020;\nr_lld_adv_ext_pkt_prepare = 0x40001024;\nr_lld_adv_frm_cbk = 0x40001028;\nr_lld_adv_frm_isr = 0x4000102c;\nr_lld_adv_frm_skip_isr = 0x40001030;\nr_lld_adv_init = 0x40001034;\nr_lld_adv_pkt_rx = 0x40001038;\nr_lld_adv_pkt_rx_connect_ind = 0x4000103c;\nr_lld_adv_pkt_rx_send_scan_req_evt = 0x40001040;\nr_lld_adv_rand_addr_update = 0x40001044;\nr_lld_adv_restart = 0x40001048;\nr_lld_adv_scan_rsp_data_set = 0x4000104c;\nr_lld_adv_scan_rsp_data_update = 0x40001050;\nr_lld_adv_set_tx_power = 0x40001054;\nr_lld_adv_start = 0x40001058;\nr_lld_adv_stop = 0x4000105c;\nr_lld_adv_sync_info_set = 0x40001060;\nr_lld_adv_sync_info_update = 0x40001064;\nr_lld_calc_aux_rx = 0x40001068;\nr_lld_cca_alloc = 0x4000106c;\nr_lld_cca_data_reset = 0x40001070;\nr_lld_cca_free = 0x40001074;\nr_lld_ch_assess_data_get = 0x40001078;\nr_lld_ch_idx_get = 0x4000107c;\nr_lld_ch_map_set = 0x40001080;\nr_lld_channel_assess = 0x40001084;\nr_lld_con_activity_act_offset_compute = 0x40001088;\nr_lld_con_activity_offset_compute = 0x4000108c;\nr_lld_con_ch_map_update = 0x40001090;\nr_lld_con_cleanup = 0x40001094;\nr_lld_con_current_tx_power_get = 0x40001098;\nr_lld_con_data_flow_set = 0x4000109c;\nr_lld_con_data_len_update = 0x400010a0;\nr_lld_con_data_tx = 0x400010a4;\nr_lld_con_enc_key_load = 0x400010a8;\nr_lld_con_event_counter_get = 0x400010ac;\nr_lld_con_evt_canceled_cbk = 0x400010b0;\nr_lld_con_evt_duration_min_get = 0x400010b4;\nr_lld_con_evt_max_eff_time_cal = 0x400010b8;\nr_lld_con_evt_sd_evt_time_get = 0x400010bc;\nr_lld_con_evt_start_cbk = 0x400010c0;\nr_lld_con_evt_time_update = 0x400010c4;\nr_lld_con_free_all_tx_buf = 0x400010c8;\nr_lld_con_frm_cbk = 0x400010cc;\nr_lld_con_frm_isr = 0x400010d0;\nr_lld_con_frm_skip_isr = 0x400010d4;\nr_lld_con_init = 0x400010d8;\nr_lld_con_llcp_tx = 0x400010dc;\nr_lld_con_max_lat_calc = 0x400010e0;\nr_lld_con_offset_get = 0x400010e4;\nr_lld_con_param_update = 0x400010e8;\nr_lld_con_phys_update = 0x400010ec;\nr_lld_con_pref_slave_evt_dur_set = 0x400010f0;\nr_lld_con_pref_slave_latency_set = 0x400010f4;\nr_lld_con_rssi_get = 0x400010f8;\nr_lld_con_rx = 0x400010fc;\nr_lld_con_rx_channel_assess = 0x40001100;\nr_lld_con_rx_enc = 0x40001104;\nr_lld_con_rx_isr = 0x40001108;\nr_lld_con_rx_link_info_check = 0x4000110c;\nr_lld_con_rx_llcp_check = 0x40001110;\nr_lld_con_rx_sync_time_update = 0x40001114;\nr_lld_con_sched = 0x40001118;\nr_lld_con_set_tx_power = 0x4000111c;\nr_lld_con_start = 0x40001120;\nr_lld_con_stop = 0x40001124;\nr_lld_con_tx = 0x40001128;\nr_lld_con_tx_enc = 0x4000112c;\nr_lld_con_tx_isr = 0x40001130;\nr_lld_con_tx_len_update = 0x40001134;\nr_lld_con_tx_len_update_for_intv = 0x40001138;\nr_lld_con_tx_len_update_for_rate = 0x4000113c;\nr_lld_con_tx_prog = 0x40001140;\nr_lld_conn_dynamic_pti_process = 0x40001144;\nr_lld_continue_scan_rx_isr_end_process = 0x40001148;\nr_lld_ext_scan_dynamic_pti_process = 0x4000114c;\nr_lld_hw_cca_end_isr = 0x40001150;\nr_lld_hw_cca_evt_handler = 0x40001154;\nr_lld_hw_cca_isr = 0x40001158;\nr_lld_init_cal_anchor_point = 0x4000115c;\nr_lld_init_compute_winoffset = 0x40001160;\nr_lld_init_connect_req_pack = 0x40001164;\nr_lld_init_end = 0x40001168;\nr_lld_init_evt_canceled_cbk = 0x4000116c;\nr_lld_init_evt_start_cbk = 0x40001170;\nr_lld_init_frm_cbk = 0x40001174;\nr_lld_init_frm_eof_isr = 0x40001178;\nr_lld_init_frm_skip_isr = 0x4000117c;\nr_lld_init_init = 0x40001180;\nr_lld_init_process_pkt_rx = 0x40001184;\nr_lld_init_process_pkt_rx_adv_ext_ind = 0x40001188;\nr_lld_init_process_pkt_rx_adv_ind_or_direct_ind = 0x4000118c;\nr_lld_init_process_pkt_rx_aux_connect_rsp = 0x40001190;\nr_lld_init_process_pkt_tx = 0x40001194;\nr_lld_init_process_pkt_tx_cal_con_timestamp = 0x40001198;\nr_lld_init_sched = 0x4000119c;\nr_lld_init_set_tx_power = 0x400011a0;\nr_lld_init_start = 0x400011a4;\nr_lld_init_stop = 0x400011a8;\nr_lld_instant_proc_end = 0x400011ac;\nr_lld_llcp_rx_ind_handler = 0x400011b0;\nr_lld_per_adv_ch_map_update = 0x400011b4;\nr_lld_per_adv_chain_construct = 0x400011b8;\nr_lld_per_adv_cleanup = 0x400011bc;\nr_lld_per_adv_coex_env_reset = 0x400011c0;\nr_lld_per_adv_data_set = 0x400011c4;\nr_lld_per_adv_data_update = 0x400011c8;\nr_lld_per_adv_dynamic_pti_process = 0x400011cc;\nr_lld_per_adv_evt_canceled_cbk = 0x400011d0;\nr_lld_per_adv_evt_start_cbk = 0x400011d4;\nr_lld_per_adv_ext_pkt_prepare = 0x400011d8;\nr_lld_per_adv_frm_cbk = 0x400011dc;\nr_lld_per_adv_frm_isr = 0x400011e0;\nr_lld_per_adv_frm_skip_isr = 0x400011e4;\nr_lld_per_adv_init = 0x400011e8;\nr_lld_per_adv_init_info_get = 0x400011ec;\nr_lld_per_adv_list_add = 0x400011f0;\nr_lld_per_adv_list_rem = 0x400011f4;\nr_lld_per_adv_sched = 0x400011f8;\nr_lld_per_adv_set_tx_power = 0x400011fc;\nr_lld_per_adv_start = 0x40001200;\nr_lld_per_adv_stop = 0x40001204;\nr_lld_per_adv_sync_info_get = 0x40001208;\nr_lld_process_cca_data = 0x4000120c;\nr_lld_ral_search = 0x40001210;\nr_lld_read_clock = 0x40001214;\nr_lld_res_list_add = 0x40001218;\nr_lld_res_list_clear = 0x4000121c;\nr_lld_res_list_is_empty = 0x40001220;\nr_lld_res_list_local_rpa_get = 0x40001224;\nr_lld_res_list_peer_rpa_get = 0x40001228;\nr_lld_res_list_peer_update = 0x4000122c;\nr_lld_res_list_priv_mode_update = 0x40001230;\nr_lld_res_list_rem = 0x40001234;\nr_lld_reset_reg = 0x40001238;\nr_lld_rpa_renew = 0x4000123c;\nr_lld_rpa_renew_evt_canceled_cbk = 0x40001240;\nr_lld_rpa_renew_evt_start_cbk = 0x40001244;\nr_lld_rpa_renew_instant_cbk = 0x40001248;\nr_lld_rxdesc_check = 0x4000124c;\nr_lld_rxdesc_free = 0x40001250;\nr_lld_scan_create_sync = 0x40001254;\nr_lld_scan_create_sync_cancel = 0x40001258;\nr_lld_scan_end = 0x4000125c;\nr_lld_scan_evt_canceled_cbk = 0x40001260;\nr_lld_scan_evt_start_cbk = 0x40001264;\nr_lld_scan_frm_cbk = 0x40001268;\nr_lld_scan_frm_eof_isr = 0x4000126c;\nr_lld_scan_frm_rx_isr = 0x40001270;\nr_lld_scan_frm_skip_isr = 0x40001274;\nr_lld_scan_init = 0x40001278;\nr_lld_scan_params_update = 0x4000127c;\nr_lld_scan_process_pkt_rx = 0x40001280;\nr_lld_scan_process_pkt_rx_adv_rep = 0x40001284;\nr_lld_scan_process_pkt_rx_aux_adv_ind = 0x40001288;\nr_lld_scan_process_pkt_rx_aux_chain_ind = 0x4000128c;\nr_lld_scan_process_pkt_rx_aux_scan_rsp = 0x40001290;\nr_lld_scan_process_pkt_rx_ext_adv = 0x40001294;\nr_lld_scan_process_pkt_rx_ext_adv_ind = 0x40001298;\nr_lld_scan_process_pkt_rx_legacy_adv = 0x4000129c;\nr_lld_scan_restart = 0x400012a0;\nr_lld_scan_sched = 0x400012a4;\nr_lld_scan_set_tx_power = 0x400012a8;\nr_lld_scan_start = 0x400012ac;\nr_lld_scan_stop = 0x400012b0;\nr_lld_scan_sync_accept = 0x400012b4;\nr_lld_scan_sync_info_unpack = 0x400012b8;\nr_lld_scan_trunc_ind = 0x400012bc;\nr_lld_sw_cca_evt_handler = 0x400012c0;\nr_lld_sw_cca_isr = 0x400012c4;\nr_lld_sync_ch_map_update = 0x400012c8;\nr_lld_sync_cleanup = 0x400012cc;\nr_lld_sync_evt_canceled_cbk = 0x400012d0;\nr_lld_sync_evt_start_cbk = 0x400012d4;\nr_lld_sync_frm_cbk = 0x400012d8;\nr_lld_sync_frm_eof_isr = 0x400012dc;\nr_lld_sync_frm_rx_isr = 0x400012e0;\nr_lld_sync_frm_skip_isr = 0x400012e4;\nr_lld_sync_init = 0x400012e8;\nr_lld_sync_process_pkt_rx = 0x400012ec;\nr_lld_sync_process_pkt_rx_aux_sync_ind = 0x400012f0;\nr_lld_sync_process_pkt_rx_pkt_check = 0x400012f4;\nr_lld_sync_scan_dynamic_pti_process = 0x400012f8;\nr_lld_sync_sched = 0x400012fc;\nr_lld_sync_start = 0x40001300;\nr_lld_sync_stop = 0x40001304;\nr_lld_sync_trunc_ind = 0x40001308;\nr_lld_test_cleanup = 0x4000130c;\nr_lld_test_evt_canceled_cbk = 0x40001310;\nr_lld_test_evt_start_cbk = 0x40001314;\nr_lld_test_freq2chnl = 0x40001318;\nr_lld_test_frm_cbk = 0x4000131c;\nr_lld_test_frm_isr = 0x40001320;\nr_lld_test_init = 0x40001324;\nr_lld_test_rx_isr = 0x40001328;\nr_lld_test_set_tx_power = 0x4000132c;\nr_lld_test_start = 0x40001330;\nr_lld_test_stop = 0x40001334;\nr_lld_update_rxbuf = 0x40001338;\nr_lld_update_rxbuf_isr = 0x4000133c;\nr_lld_white_list_add = 0x40001340;\nr_lld_white_list_rem = 0x40001344;\nr_llm_activity_free_get = 0x40001348;\nr_llm_activity_free_set = 0x4000134c;\nr_llm_activity_syncing_get = 0x40001350;\nr_llm_adv_con_len_check = 0x40001354;\nr_llm_adv_hdl_to_id = 0x40001358;\nr_llm_adv_rep_flow_control_check = 0x4000135c;\nr_llm_adv_rep_flow_control_update = 0x40001360;\nr_llm_adv_reports_list_check = 0x40001364;\nr_llm_adv_set_all_release = 0x40001368;\nr_llm_adv_set_dft_params = 0x4000136c;\nr_llm_adv_set_release = 0x40001370;\nr_llm_aes_res_cb = 0x40001374;\nr_llm_ble_update_adv_flow_control = 0x40001378;\nr_llm_ch_map_update = 0x4000137c;\nr_llm_cmd_cmp_send = 0x40001380;\nr_llm_cmd_stat_send = 0x40001384;\nr_llm_dev_list_empty_entry = 0x40001388;\nr_llm_dev_list_search = 0x4000138c;\nr_llm_env_adv_dup_filt_deinit = 0x40001390;\nr_llm_env_adv_dup_filt_init = 0x40001394;\nr_llm_init_ble_adv_report_flow_contol = 0x40001398;\nr_llm_is_dev_connected = 0x4000139c;\nr_llm_is_dev_synced = 0x400013a0;\nr_llm_is_non_con_act_ongoing_check = 0x400013a4;\nr_llm_is_wl_accessible = 0x400013a8;\nr_llm_le_evt_mask_check = 0x400013ac;\nr_llm_le_features_get = 0x400013b0;\nr_llm_link_disc = 0x400013b4;\nr_llm_master_ch_map_get = 0x400013b8;\nr_llm_msg_handler_tab_p_get = 0x400013bc;\nr_llm_no_activity = 0x400013c0;\nr_llm_per_adv_slot_dur = 0x400013c4;\nr_llm_plan_elt_get = 0x400013c8;\nr_llm_rx_path_comp_get = 0x400013cc;\nr_llm_scan_start = 0x400013d0;\nr_llm_scan_sync_acad_attach = 0x400013d4;\nr_llm_scan_sync_acad_detach = 0x400013d8;\nr_llm_send_adv_lost_event_to_host = 0x400013dc;\nr_llm_tx_path_comp_get = 0x400013e0;\nr_misc_deinit = 0x400013e4;\nr_misc_free_em_buf_in_isr = 0x400013e8;\nr_misc_init = 0x400013ec;\nr_misc_msg_handler_tab_p_get = 0x400013f0;\nr_notEqual256 = 0x400013f4;\nr_phy_upd_proc_start = 0x400013f8;\nr_platform_reset = 0x400013fc;\nr_register_esp_vendor_cmd_handler = 0x40001400;\nr_rf_em_init = 0x40001404;\nr_rf_force_agc_enable = 0x40001408;\nr_rf_reg_rd = 0x4000140c;\nr_rf_reg_wr = 0x40001410;\nr_rf_reset = 0x40001414;\nr_rf_rssi_convert = 0x40001418;\nr_rf_rw_v9_le_disable = 0x4000141c;\nr_rf_rw_v9_le_enable = 0x40001420;\nr_rf_sleep = 0x40001424;\nr_rf_txpwr_cs_get = 0x40001428;\nr_rf_txpwr_dbm_get = 0x4000142c;\nr_rf_util_cs_fmt_convert = 0x40001430;\nr_rw_crypto_aes_ccm = 0x40001434;\nr_rw_crypto_aes_encrypt = 0x40001438;\nr_rw_crypto_aes_init = 0x4000143c;\nr_rw_crypto_aes_k1 = 0x40001440;\nr_rw_crypto_aes_k2 = 0x40001444;\nr_rw_crypto_aes_k3 = 0x40001448;\nr_rw_crypto_aes_k4 = 0x4000144c;\nr_rw_crypto_aes_rand = 0x40001450;\nr_rw_crypto_aes_result_handler = 0x40001454;\nr_rw_crypto_aes_s1 = 0x40001458;\nr_rw_cryto_aes_cmac = 0x4000145c;\nr_rw_v9_init_em_radio_table = 0x40001460;\nr_rwble_isr = 0x40001464;\nr_rwble_sleep_enter = 0x40001468;\nr_rwble_sleep_wakeup_end = 0x4000146c;\nr_rwbtdm_isr_wrapper = 0x40001470;\nr_rwip_active_check = 0x40001474;\nr_rwip_aes_encrypt = 0x40001478;\nr_rwip_assert = 0x4000147c;\nr_rwip_crypt_evt_handler = 0x40001480;\nr_rwip_crypt_isr_handler = 0x40001484;\nr_rwip_eif_get = 0x40001488;\nr_rwip_half_slot_2_lpcycles = 0x4000148c;\nr_rwip_hus_2_lpcycles = 0x40001490;\nr_rwip_isr = 0x40001494;\nr_rwip_lpcycles_2_hus = 0x40001498;\nr_rwip_prevent_sleep_clear = 0x4000149c;\nr_rwip_prevent_sleep_set = 0x400014a0;\nr_rwip_schedule = 0x400014a4;\nr_rwip_sleep = 0x400014a8;\nr_rwip_sw_int_handler = 0x400014ac;\nr_rwip_sw_int_req = 0x400014b0;\nr_rwip_time_get = 0x400014b4;\nr_rwip_timer_10ms_handler = 0x400014b8;\nr_rwip_timer_10ms_set = 0x400014bc;\nr_rwip_timer_hs_handler = 0x400014c0;\nr_rwip_timer_hs_set = 0x400014c4;\nr_rwip_timer_hus_handler = 0x400014c8;\nr_rwip_timer_hus_set = 0x400014cc;\nr_rwip_wakeup = 0x400014d0;\nr_rwip_wakeup_end = 0x400014d4;\nr_rwip_wlcoex_set = 0x400014d8;\nr_sch_alarm_clear = 0x400014dc;\nr_sch_alarm_init = 0x400014e0;\nr_sch_alarm_prog = 0x400014e4;\nr_sch_alarm_set = 0x400014e8;\nr_sch_alarm_timer_isr = 0x400014ec;\nr_sch_arb_conflict_check = 0x400014f0;\nr_sch_arb_elt_cancel = 0x400014f4;\nr_sch_arb_event_start_isr = 0x400014f8;\nr_sch_arb_init = 0x400014fc;\nr_sch_arb_insert = 0x40001500;\nr_sch_arb_prog_timer = 0x40001504;\nr_sch_arb_remove = 0x40001508;\nr_sch_arb_sw_isr = 0x4000150c;\nr_sch_plan_chk = 0x40001510;\nr_sch_plan_clock_wrap_offset_update = 0x40001514;\nr_sch_plan_init = 0x40001518;\nr_sch_plan_interval_req = 0x4000151c;\nr_sch_plan_offset_max_calc = 0x40001520;\nr_sch_plan_offset_req = 0x40001524;\nr_sch_plan_position_range_compute = 0x40001528;\nr_sch_plan_rem = 0x4000152c;\nr_sch_plan_req = 0x40001530;\nr_sch_plan_set = 0x40001534;\nr_sch_prog_end_isr = 0x40001538;\nr_sch_prog_init = 0x4000153c;\nr_sch_prog_push = 0x40001540;\nr_sch_prog_rx_isr = 0x40001544;\nr_sch_prog_skip_isr = 0x40001548;\nr_sch_prog_tx_isr = 0x4000154c;\nr_sch_slice_bg_add = 0x40001550;\nr_sch_slice_bg_remove = 0x40001554;\nr_sch_slice_compute = 0x40001558;\nr_sch_slice_fg_add = 0x4000155c;\nr_sch_slice_fg_remove = 0x40001560;\nr_sch_slice_init = 0x40001564;\nr_sch_slice_per_add = 0x40001568;\nr_sch_slice_per_remove = 0x4000156c;\nr_sdk_config_get_bt_sleep_enable = 0x40001570;\nr_sdk_config_get_hl_derived_opts = 0x40001574;\nr_sdk_config_get_opts = 0x40001578;\nr_sdk_config_get_priv_opts = 0x4000157c;\nr_sdk_config_set_bt_sleep_enable = 0x40001580;\nr_sdk_config_set_hl_derived_opts = 0x40001584;\nr_sdk_config_set_opts = 0x40001588;\nr_specialModP256 = 0x4000158c;\nr_unloaded_area_init = 0x40001590;\nr_vhci_flow_off = 0x40001594;\nr_vhci_flow_on = 0x40001598;\nr_vhci_notify_host_send_available = 0x4000159c;\nr_vhci_send_to_host = 0x400015a0;\nr_vnd_hci_command_handler = 0x400015a4;\nr_vshci_init = 0x400015a8;\nvnd_hci_command_handler_wrapper = 0x400015ac;\n\/* Data (.data, .bss, .rodata) *\/\nbt_rf_coex_cfg_p = 0x3fcdffcc;\nbt_rf_coex_hooks_p = 0x3fcdffc8;\nbtdm_env_p = 0x3fcdffc4;\ng_rw_controller_task_handle = 0x3fcdffc0;\ng_rw_init_sem = 0x3fcdffbc;\ng_rw_schd_queue = 0x3fcdffb8;\nlld_init_env = 0x3fcdffb4;\nlld_rpa_renew_env = 0x3fcdffb0;\nlld_scan_env = 0x3fcdffac;\nlld_scan_sync_env = 0x3fcdffa8;\nlld_test_env = 0x3fcdffa4;\np_ble_util_buf_env = 0x3fcdffa0;\np_lld_env = 0x3fcdff9c;\np_llm_env = 0x3fcdff98;\nr_h4tl_eif_p = 0x3fcdff94;\nr_hli_funcs_p = 0x3fcdff90;\nr_ip_funcs_p = 0x3fcdff8c;\nr_modules_funcs_p = 0x3fcdff88;\nr_osi_funcs_p = 0x3fcdff84;\nr_plf_funcs_p = 0x3fcdff80;\nvhci_env_p = 0x3fcdff7c;\naa_gen = 0x3fcdff78;\naes_env = 0x3fcdff6c;\nbt_rf_coex_cfg_cb = 0x3fcdff1c;\nbtdm_pwr_state = 0x3fcdff18;\nbtdm_slp_err = 0x3fcdff14;\necc_env = 0x3fcdff0c;\nesp_handler = 0x3fcdff04;\nesp_vendor_cmd = 0x3fcdfefc;\ng_adv_delay_dis = 0x3fcdfef8;\ng_conflict_elt = 0x3fcdfef4;\ng_eif_api = 0x3fcdfee4;\ng_event_empty = 0x3fcdfed8;\ng_llc_state = 0x3fcdfecc;\ng_llm_state = 0x3fcdfec8;\ng_max_evt_env = 0x3fcdfec4;\ng_misc_state = 0x3fcdfec0;\ng_rma_rule_db = 0x3fcdfea4;\ng_rtp_rule_db = 0x3fcdfe88;\ng_scan_forever = 0x3fcdfe85;\ng_time_msb = 0x3fcdfe84;\nh4tl_env = 0x3fcdfe5c;\nhci_env = 0x3fcdfe38;\nhci_ext_host = 0x3fcdfe34;\nhci_fc_env = 0x3fcdfe2c;\nhci_tl_env = 0x3fcdfe00;\nke_env = 0x3fcdfdd0;\nke_event_env = 0x3fcdfd90;\nke_task_env = 0x3fcdfd14;\nllc_env = 0x3fcdfcec;\nlld_adv_env = 0x3fcdfcc4;\nlld_con_env = 0x3fcdfc9c;\nlld_exp_sync_pos_tab = 0x3fcdfc94;\nlld_per_adv_env = 0x3fcdfc6c;\nlld_sync_env = 0x3fcdfc44;\nllm_le_adv_flow_env = 0x3fcdfc38;\nrw_sleep_enable = 0x3fcdfc34;\nrwble_env = 0x3fcdfc2c;\nrwip_env = 0x3fcdfc10;\nrwip_param = 0x3fcdfc04;\nrwip_prog_delay = 0x3fcdfc00;\nrwip_rf = 0x3fcdfbc8;\nsch_alarm_env = 0x3fcdfbc0;\nsch_arb_env = 0x3fcdfbac;\nsch_plan_env = 0x3fcdfba4;\nsch_prog_env = 0x3fcdfaa0;\nsch_slice_env = 0x3fcdfa40;\nsch_slice_params = 0x3fcdfa38;\ntimer_env = 0x3fcdfa30;\nunloaded_area = 0x3fcdfa2c;\nvshci_state = 0x3fcdfa28;\nTASK_DESC_LLC = 0x3fcdfa1c;\nTASK_DESC_LLM = 0x3fcdfa10;\nTASK_DESC_VSHCI = 0x3fcdfa04;\nco_default_bdaddr = 0x3fcdf9fc;\ndbg_assert_block = 0x3fcdf9f8;\ng_bt_plf_log_level = 0x3fcdf9f4;\nhci_cmd_desc_tab_vs_esp = 0x3fcdf9d0;\nhci_command_handler_tab_esp = 0x3fcdf9b8;\nprivacy_en = 0x3fcdf9b4;\nsdk_cfg_priv_opts = 0x3fcdf96c;\nBasePoint_x_256 = 0x3ff1ffdc;\nBasePoint_y_256 = 0x3ff1ffbc;\nDebugE256PublicKey_x = 0x3ff1ff9c;\nDebugE256PublicKey_y = 0x3ff1ff7c;\nDebugE256SecretKey = 0x3ff1ff5c;\nECC_4Win_Look_up_table = 0x3ff1f7a0;\nLLM_AA_CT1 = 0x3ff1f79c;\nLLM_AA_CT2 = 0x3ff1f798;\nRF_TX_PW_CONV_TBL = 0x3ff1f790;\nTASK_DESC_MISC = 0x3ff1f784;\nadv_evt_prop2type = 0x3ff1f768;\nadv_evt_type2prop = 0x3ff1f760;\naes_cmac_zero = 0x3ff1f750;\naes_k2_salt = 0x3ff1f740;\naes_k3_id64 = 0x3ff1f738;\naes_k3_salt = 0x3ff1f728;\naes_k4_id6 = 0x3ff1f724;\naes_k4_salt = 0x3ff1f714;\nbigHexP256 = 0x3ff1f6e8;\nbyte_tx_time = 0x3ff1f6e0;\nco_null_bdaddr = 0x3ff1f6d8;\nco_phy_mask_to_rate = 0x3ff1f6d0;\nco_phy_mask_to_value = 0x3ff1f6c8;\nco_phy_to_rate = 0x3ff1f6c4;\nco_phy_value_to_mask = 0x3ff1f6c0;\nco_rate_to_byte_dur_us = 0x3ff1f6b8;\nco_rate_to_phy = 0x3ff1f6b0;\nco_rate_to_phy_mask = 0x3ff1f6ac;\nco_sca2ppm = 0x3ff1f69c;\ncoef_B = 0x3ff1f670;\nconnect_req_dur_tab = 0x3ff1f668;\necc_Jacobian_InfinityPoint256 = 0x3ff1f5e4;\nem_base_reg_lut = 0x3ff1f518;\nfixed_tx_time = 0x3ff1f510;\nh4tl_msgtype2hdrlen = 0x3ff1f508;\nhci_cmd_desc_root_tab = 0x3ff1f4d8;\nhci_cmd_desc_tab_ctrl_bb = 0x3ff1f46c;\nhci_cmd_desc_tab_info_par = 0x3ff1f43c;\nhci_cmd_desc_tab_le = 0x3ff1f0a0;\nhci_cmd_desc_tab_lk_ctrl = 0x3ff1f088;\nhci_cmd_desc_tab_stat_par = 0x3ff1f07c;\nhci_cmd_desc_tab_vs = 0x3ff1f040;\nhci_evt_desc_tab = 0x3ff1eff8;\nhci_evt_le_desc_tab = 0x3ff1ef58;\nhci_evt_le_desc_tab_esp = 0x3ff1ef50;\nhci_rsvd_evt_msk = 0x3ff1ef48;\nlld_aux_phy_to_rate = 0x3ff1ef44;\nlld_init_max_aux_dur_tab = 0x3ff1ef3c;\nlld_scan_map_legacy_pdu_to_evt_type = 0x3ff1ef34;\nlld_scan_max_aux_dur_tab = 0x3ff1ef2c;\nlld_sync_max_aux_dur_tab = 0x3ff1ef24;\nllm_local_le_feats = 0x3ff1ef1c;\nllm_local_le_states = 0x3ff1ef14;\nllm_local_supp_cmds = 0x3ff1eeec;\nmaxSecretKey_256 = 0x3ff1eecc;\nmax_data_tx_time = 0x3ff1eec4;\none_bits = 0x3ff1eeb4;\nrwip_coex_cfg = 0x3ff1eeac;\nrwip_priority = 0x3ff1ee94;\nveryBigHexP256 = 0x3ff1ee48;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x400015b0;\nRC_GetBlockAckTime = 0x400015b4;\nebuf_list_remove = 0x400015b8;\nesf_buf_alloc = 0x400015bc;\nesf_buf_alloc_dynamic = 0x400015c0;\nesf_buf_recycle = 0x400015c4;\nGetAccess = 0x400015c8;\nhal_mac_is_low_rate_enabled = 0x400015cc;\nhal_mac_tx_get_blockack = 0x400015d0;\nhal_mac_tx_set_ppdu = 0x400015d4;\nic_get_trc = 0x400015d8;\nic_mac_deinit = 0x400015dc;\nic_mac_init = 0x400015e0;\nic_interface_enabled = 0x400015e4;\nis_lmac_idle = 0x400015e8;\nlmacAdjustTimestamp = 0x400015ec;\nlmacDiscardAgedMSDU = 0x400015f0;\nlmacDiscardMSDU = 0x400015f4;\nlmacEndFrameExchangeSequence = 0x400015f8;\nlmacIsIdle = 0x400015fc;\nlmacIsLongFrame = 0x40001600;\nlmacMSDUAged = 0x40001604;\nlmacPostTxComplete = 0x40001608;\nlmacProcessAllTxTimeout = 0x4000160c;\nlmacProcessCollisions = 0x40001610;\nlmacProcessRxSucData = 0x40001614;\nlmacReachLongLimit = 0x40001618;\nlmacReachShortLimit = 0x4000161c;\nlmacRecycleMPDU = 0x40001620;\nlmacRxDone = 0x40001624;\nlmacSetTxFrame = 0x40001628;\nlmacTxDone = 0x4000162c;\nlmacTxFrame = 0x40001630;\nmac_tx_set_duration = 0x40001634;\nmac_tx_set_htsig = 0x40001638;\nmac_tx_set_plcp0 = 0x4000163c;\nmac_tx_set_plcp1 = 0x40001640;\nmac_tx_set_plcp2 = 0x40001644;\npm_check_state = 0x40001648;\npm_disable_dream_timer = 0x4000164c;\npm_disable_sleep_delay_timer = 0x40001650;\npm_dream = 0x40001654;\npm_mac_wakeup = 0x40001658;\npm_mac_sleep = 0x4000165c;\npm_enable_active_timer = 0x40001660;\npm_enable_sleep_delay_timer = 0x40001664;\npm_local_tsf_process = 0x40001668;\npm_set_beacon_filter = 0x4000166c;\npm_is_in_wifi_slice_threshold = 0x40001670;\npm_is_waked = 0x40001674;\npm_keep_alive = 0x40001678;\npm_on_beacon_rx = 0x4000167c;\npm_on_data_rx = 0x40001680;\npm_on_tbtt = 0x40001684;\npm_parse_beacon = 0x40001688;\npm_process_tim = 0x4000168c;\npm_rx_beacon_process = 0x40001690;\npm_rx_data_process = 0x40001694;\npm_sleep = 0x40001698;\npm_sleep_for = 0x4000169c;\npm_tbtt_process = 0x400016a0;\nppAMPDU2Normal = 0x400016a4;\nppAssembleAMPDU = 0x400016a8;\nppCalFrameTimes = 0x400016ac;\nppCalSubFrameLength = 0x400016b0;\nppCalTxAMPDULength = 0x400016b4;\nppCheckTxAMPDUlength = 0x400016b8;\nppDequeueRxq_Locked = 0x400016bc;\nppDequeueTxQ = 0x400016c0;\nppEmptyDelimiterLength = 0x400016c4;\nppEnqueueRxq = 0x400016c8;\nppEnqueueTxDone = 0x400016cc;\nppGetTxQFirstAvail_Locked = 0x400016d0;\nppGetTxframe = 0x400016d4;\nppMapTxQueue = 0x400016d8;\nppProcTxSecFrame = 0x400016dc;\nppProcessRxPktHdr = 0x400016e0;\nppProcessTxQ = 0x400016e4;\nppRecordBarRRC = 0x400016e8;\nlmacRequestTxopQueue = 0x400016ec;\nlmacReleaseTxopQueue = 0x400016f0;\nppRecycleAmpdu = 0x400016f4;\nppRecycleRxPkt = 0x400016f8;\nppResortTxAMPDU = 0x400016fc;\nppResumeTxAMPDU = 0x40001700;\nppRxFragmentProc = 0x40001704;\nppRxPkt = 0x40001708;\nppRxProtoProc = 0x4000170c;\nppSearchTxQueue = 0x40001710;\nppSearchTxframe = 0x40001714;\nppSelectNextQueue = 0x40001718;\nppSubFromAMPDU = 0x4000171c;\nppTask = 0x40001720;\nppTxPkt = 0x40001724;\nppTxProtoProc = 0x40001728;\nppTxqUpdateBitmap = 0x4000172c;\npp_coex_tx_request = 0x40001730;\npp_hdrsize = 0x40001734;\npp_post = 0x40001738;\npp_process_hmac_waiting_txq = 0x4000173c;\nrcGetAmpduSched = 0x40001740;\nrcUpdateRxDone = 0x40001744;\nrc_get_trc = 0x40001748;\nrc_get_trc_by_index = 0x4000174c;\nrcAmpduLowerRate = 0x40001750;\nrcampduuprate = 0x40001754;\nrcClearCurAMPDUSched = 0x40001758;\nrcClearCurSched = 0x4000175c;\nrcClearCurStat = 0x40001760;\nrcGetSched = 0x40001764;\nrcLowerSched = 0x40001768;\nrcSetTxAmpduLimit = 0x4000176c;\nrcTxUpdatePer = 0x40001770;\nrcUpdateAckSnr = 0x40001774;\nrcUpdateRate = 0x40001778;\nrcUpdateTxDone = 0x4000177c;\nrcUpdateTxDoneAmpdu2 = 0x40001780;\nrcUpSched = 0x40001784;\nrssi_margin = 0x40001788;\nrx11NRate2AMPDULimit = 0x4000178c;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001790;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001794;\ntrc_calc_duration = 0x40001798;\ntrc_isTxAmpduOperational = 0x4000179c;\ntrc_onAmpduOp = 0x400017a0;\nTRC_PER_IS_GOOD = 0x400017a4;\ntrc_SetTxAmpduState = 0x400017a8;\ntrc_tid_isTxAmpduOperational = 0x400017ac;\ntrcAmpduSetState = 0x400017b0;\nwDevCheckBlockError = 0x400017b4;\nwDev_AppendRxBlocks = 0x400017b8;\nwDev_DiscardFrame = 0x400017bc;\nwDev_GetNoiseFloor = 0x400017c0;\nwDev_IndicateAmpdu = 0x400017c4;\nwDev_IndicateFrame = 0x400017c8;\nwdev_bank_store = 0x400017cc;\nwdev_bank_load = 0x400017d0;\nwdev_mac_reg_load = 0x400017d4;\nwdev_mac_reg_store = 0x400017d8;\nwdev_mac_special_reg_load = 0x400017dc;\nwdev_mac_special_reg_store = 0x400017e0;\nwdev_mac_wakeup = 0x400017e4;\nwdev_mac_sleep = 0x400017e8;\nhal_mac_is_dma_enable = 0x400017ec;\nwDev_ProcessFiq = 0x400017f0;\nwDev_ProcessRxSucData = 0x400017f4;\nwdevProcessRxSucDataAll = 0x400017f8;\nwdev_csi_len_align = 0x400017fc;\nppDequeueTxDone_Locked = 0x40001800;\nppProcTxDone = 0x40001804;\npm_tx_data_done_process = 0x40001808;\nconfig_is_cache_tx_buf_enabled = 0x4000180c;\nppMapWaitTxq = 0x40001810;\nppProcessWaitingQueue = 0x40001814;\nppDisableQueue = 0x40001818;\npm_allow_tx = 0x4000181c;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff1ee44;\npTxRx = 0x3fcdf968;\nlmacConfMib_ptr = 0x3fcdf964;\nour_wait_eb = 0x3fcdf960;\nour_tx_eb = 0x3fcdf95c;\npp_wdev_funcs = 0x3fcdf958;\ng_osi_funcs_p = 0x3fcdf954;\nwDevCtrl_ptr = 0x3fcdf950;\ng_wdev_last_desc_reset_ptr = 0x3ff1ee40;\nwDevMacSleep_ptr = 0x3fcdf94c;\ng_lmac_cnt_ptr = 0x3fcdf948;\nour_controls_ptr = 0x3ff1ee3c;\npp_sig_cnt_ptr = 0x3fcdf944;\ng_eb_list_desc_ptr = 0x3fcdf940;\ns_fragment_ptr = 0x3fcdf93c;\nif_ctrl_ptr = 0x3fcdf938;\ng_intr_lock_mux = 0x3fcdf934;\ng_wifi_global_lock = 0x3fcdf930;\ns_wifi_queue = 0x3fcdf92c;\npp_task_hdl = 0x3fcdf928;\ns_pp_task_create_sem = 0x3fcdf924;\ns_pp_task_del_sem = 0x3fcdf920;\ng_wifi_menuconfig_ptr = 0x3fcdf91c;\nxphyQueue = 0x3fcdf918;\nap_no_lr_ptr = 0x3fcdf914;\nrc11BSchedTbl_ptr = 0x3fcdf910;\nrc11NSchedTbl_ptr = 0x3fcdf90c;\nrcLoRaSchedTbl_ptr = 0x3fcdf908;\nBasicOFDMSched_ptr = 0x3fcdf904;\ntrc_ctl_ptr = 0x3fcdf900;\ng_pm_cnt_ptr = 0x3fcdf8fc;\ng_pm_ptr = 0x3fcdf8f8;\ng_pm_cfg_ptr = 0x3fcdf8f4;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdf8f0;\ng_txop_queue_status_ptr = 0x3fcdf8ec;\ng_mac_sleep_en_ptr = 0x3fcdf8e8;\ng_mesh_is_root_ptr = 0x3fcdf8e4;\ng_mesh_topology_ptr = 0x3fcdf8e0;\ng_mesh_init_ps_type_ptr = 0x3fcdf8dc;\ng_mesh_is_started_ptr = 0x3fcdf8d8;\ng_config_func = 0x3fcdf8d4;\ng_net80211_tx_func = 0x3fcdf8d0;\ng_timer_func = 0x3fcdf8cc;\ns_michael_mic_failure_cb = 0x3fcdf8c8;\nwifi_sta_rx_probe_req = 0x3fcdf8c4;\ng_tx_done_cb_func = 0x3fcdf8c0;\ng_per_conn_trc = 0x3fcdf874;\ns_encap_amsdu_func = 0x3fcdf870;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001820;\nampdu_dispatch = 0x40001824;\nampdu_dispatch_all = 0x40001828;\nampdu_dispatch_as_many_as_possible = 0x4000182c;\nampdu_dispatch_movement = 0x40001830;\nampdu_dispatch_upto = 0x40001834;\nchm_is_at_home_channel = 0x40001838;\ncnx_node_is_existing = 0x4000183c;\ncnx_node_search = 0x40001840;\nic_ebuf_recycle_rx = 0x40001844;\nic_ebuf_recycle_tx = 0x40001848;\nic_reset_rx_ba = 0x4000184c;\nieee80211_align_eb = 0x40001850;\nieee80211_ampdu_reorder = 0x40001854;\nieee80211_ampdu_start_age_timer = 0x40001858;\nieee80211_encap_esfbuf = 0x4000185c;\nieee80211_is_tx_allowed = 0x40001860;\nieee80211_output_pending_eb = 0x40001864;\nieee80211_output_process = 0x40001868;\nieee80211_set_tx_desc = 0x4000186c;\nrom_sta_input = 0x40001870;\nwifi_get_macaddr = 0x40001874;\nwifi_rf_phy_disable = 0x40001878;\nwifi_rf_phy_enable = 0x4000187c;\nic_ebuf_alloc = 0x40001880;\nieee80211_classify = 0x40001884;\nieee80211_copy_eb_header = 0x40001888;\nieee80211_recycle_cache_eb = 0x4000188c;\nieee80211_search_node = 0x40001890;\nroundup2 = 0x40001894;\nieee80211_crypto_encap = 0x40001898;\nieee80211_crypto_decap = 0x4000189c;\nieee80211_decap = 0x400018a0;\nieee80211_set_tx_pti = 0x400018a4;\nwifi_is_started = 0x400018a8;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdf86c;\ng_scan = 0x3fcdf868;\ng_chm = 0x3fcdf864;\ng_ic_ptr = 0x3fcdf860;\ng_hmac_cnt_ptr = 0x3fcdf85c;\ng_tx_cacheq_ptr = 0x3fcdf858;\ns_netstack_free = 0x3fcdf854;\nmesh_rxcb = 0x3fcdf850;\nsta_rxcb = 0x3fcdf84c;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x400018ac;\ncoex_bt_release = 0x400018b0;\ncoex_bt_request = 0x400018b4;\ncoex_core_ble_conn_dyn_prio_get = 0x400018b8;\ncoex_core_event_duration_get = 0x400018bc;\ncoex_core_pti_get = 0x400018c0;\ncoex_core_release = 0x400018c4;\ncoex_core_request = 0x400018c8;\ncoex_core_status_get = 0x400018cc;\ncoex_core_timer_idx_get = 0x400018d0;\ncoex_event_duration_get = 0x400018d4;\ncoex_hw_timer_disable = 0x400018d8;\ncoex_hw_timer_enable = 0x400018dc;\ncoex_hw_timer_set = 0x400018e0;\ncoex_schm_interval_set = 0x400018e4;\ncoex_schm_lock = 0x400018e8;\ncoex_schm_unlock = 0x400018ec;\ncoex_status_get = 0x400018f0;\ncoex_wifi_release = 0x400018f4;\nesp_coex_ble_conn_dynamic_prio_get = 0x400018f8;\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdf848;\ncoex_pti_tab_ptr = 0x3fcdf844;\ncoex_schm_env_ptr = 0x3fcdf840;\ncoexist_funcs = 0x3fcdf83c;\ng_coa_funcs_p = 0x3fcdf838;\ng_coex_param_ptr = 0x3fcdf834;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_get_romfuncs = 0x400018fc;\nrom_abs_temp = 0x40001900;\nrom_bb_bss_cbw40_dig = 0x40001904;\nrom_bb_wdg_test_en = 0x40001908;\nrom_bb_wdt_get_status = 0x4000190c;\nrom_bb_wdt_int_enable = 0x40001910;\nrom_bb_wdt_rst_enable = 0x40001914;\nrom_bb_wdt_timeout_clear = 0x40001918;\nrom_cbw2040_cfg = 0x4000191c;\nrom_check_noise_floor = 0x40001920;\nrom_chip_i2c_readReg = 0x40001924;\nrom_chip_i2c_writeReg = 0x40001928;\nrom_correct_rf_ana_gain = 0x4000192c;\nrom_dc_iq_est = 0x40001930;\nrom_disable_agc = 0x40001934;\nrom_en_pwdet = 0x40001938;\nrom_enable_agc = 0x4000193c;\nrom_get_bbgain_db = 0x40001940;\nrom_get_data_sat = 0x40001944;\nrom_get_i2c_read_mask = 0x40001948;\nrom_get_pwctrl_correct = 0x4000194c;\nrom_get_rf_gain_qdb = 0x40001950;\nrom_i2c_readReg = 0x40001954;\nrom_i2c_readReg_Mask = 0x40001958;\nrom_i2c_writeReg = 0x4000195c;\nrom_i2c_writeReg_Mask = 0x40001960;\nrom_index_to_txbbgain = 0x40001964;\nrom_iq_est_disable = 0x40001968;\nrom_iq_est_enable = 0x4000196c;\nrom_linear_to_db = 0x40001970;\nrom_loopback_mode_en = 0x40001974;\nrom_mhz2ieee = 0x40001978;\nrom_noise_floor_auto_set = 0x4000197c;\nrom_pbus_debugmode = 0x40001980;\nrom_pbus_force_mode = 0x40001984;\nrom_pbus_force_test = 0x40001988;\nrom_pbus_rd = 0x4000198c;\nrom_pbus_rd_addr = 0x40001990;\nrom_pbus_rd_shift = 0x40001994;\nrom_pbus_set_dco = 0x40001998;\nrom_pbus_set_rxgain = 0x4000199c;\nrom_pbus_workmode = 0x400019a0;\nrom_pbus_xpd_rx_off = 0x400019a4;\nrom_pbus_xpd_rx_on = 0x400019a8;\nrom_pbus_xpd_tx_off = 0x400019ac;\n\/* rom_pbus_xpd_tx_on = 0x400019b0; *\/\nrom_phy_byte_to_word = 0x400019b4;\nrom_phy_disable_cca = 0x400019b8;\nrom_phy_enable_cca = 0x400019bc;\nrom_phy_get_noisefloor = 0x400019c0;\nrom_phy_get_rx_freq = 0x400019c4;\nrom_phy_set_bbfreq_init = 0x400019c8;\nrom_pow_usr = 0x400019cc;\nrom_pwdet_sar2_init = 0x400019d0;\nrom_read_hw_noisefloor = 0x400019d4;\nrom_read_sar_dout = 0x400019d8;\nrom_set_cal_rxdc = 0x400019dc;\nrom_set_chan_cal_interp = 0x400019e0;\nrom_set_loopback_gain = 0x400019e4;\nrom_set_noise_floor = 0x400019e8;\nrom_set_rxclk_en = 0x400019ec;\nrom_set_tx_dig_gain = 0x400019f0;\n\/* rom_set_txcap_reg = 0x400019f4; *\/\nrom_set_txclk_en = 0x400019f8;\nrom_spur_cal = 0x400019fc;\nrom_spur_reg_write_one_tone = 0x40001a00;\nrom_target_power_add_backoff = 0x40001a04;\nrom_tx_pwctrl_bg_init = 0x40001a08;\nrom_txbbgain_to_index = 0x40001a0c;\nrom_wifi_11g_rate_chg = 0x40001a10;\nrom_write_gain_mem = 0x40001a14;\nchip726_phyrom_version = 0x40001a18;\nrom_disable_wifi_agc = 0x40001a1c;\nrom_enable_wifi_agc = 0x40001a20;\nrom_set_tx_gain_table = 0x40001a24;\nrom_bt_index_to_bb = 0x40001a28;\nrom_bt_bb_to_index = 0x40001a2c;\nrom_wr_bt_tx_atten = 0x40001a30;\nrom_wr_bt_tx_gain_mem = 0x40001a34;\nrom_spur_coef_cfg = 0x40001a38;\nrom_bb_bss_cbw40 = 0x40001a3c;\nrom_set_cca = 0x40001a40;\nrom_tx_paon_set = 0x40001a44;\nrom_i2cmst_reg_init = 0x40001a48;\nrom_iq_corr_enable = 0x40001a4c;\nrom_fe_reg_init = 0x40001a50;\n\/* rom_agc_reg_init = 0x40001a54; *\/\n\/* rom_bb_reg_init = 0x40001a58; *\/\nrom_mac_enable_bb = 0x40001a5c;\nrom_bb_wdg_cfg = 0x40001a60;\nrom_force_txon = 0x40001a64;\nrom_fe_txrx_reset = 0x40001a68;\nrom_set_rx_comp = 0x40001a6c;\n\/* rom_set_pbus_reg = 0x40001a70; *\/\nrom_write_chan_freq = 0x40001a74;\n\/* rom_phy_xpd_rf = 0x40001a78; *\/\nrom_set_xpd_sar = 0x40001a7c;\nrom_write_dac_gain2 = 0x40001a80;\nrom_rtc_sar2_init = 0x40001a84;\nrom_get_target_power_offset = 0x40001a88;\n\/* rom_write_txrate_power_offset = 0x40001a8c; *\/\nrom_get_rate_fcc_index = 0x40001a90;\nrom_get_rate_target_power = 0x40001a94;\nrom_write_wifi_dig_gain = 0x40001a98;\nrom_bt_correct_rf_ana_gain = 0x40001a9c;\nrom_pkdet_vol_start = 0x40001aa0;\nrom_read_sar2_code = 0x40001aa4;\nrom_get_sar2_vol = 0x40001aa8;\nrom_get_pll_vol = 0x40001aac;\nrom_get_phy_target_power = 0x40001ab0;\n\/* rom_temp_to_power = 0x40001ab4; *\/\nrom_phy_track_pll_cap = 0x40001ab8;\nrom_phy_pwdet_always_en = 0x40001abc;\nrom_phy_pwdet_onetime_en = 0x40001ac0;\nrom_get_i2c_mst0_mask = 0x40001ac4;\nrom_get_i2c_hostid = 0x40001ac8;\nrom_enter_critical_phy = 0x40001acc;\nrom_exit_critical_phy = 0x40001ad0;\nrom_chip_i2c_readReg_org = 0x40001ad4;\nrom_i2c_paral_set_mst0 = 0x40001ad8;\nrom_i2c_paral_set_read = 0x40001adc;\nrom_i2c_paral_read = 0x40001ae0;\nrom_i2c_paral_write = 0x40001ae4;\nrom_i2c_paral_write_num = 0x40001ae8;\nrom_i2c_paral_write_mask = 0x40001aec;\nrom_bb_bss_cbw40_ana = 0x40001af0;\nrom_chan_to_freq = 0x40001af4;\n\/* rom_open_i2c_xpd = 0x40001af8; *\/\nrom_dac_rate_set = 0x40001afc;\n\/* rom_tsens_read_init = 0x40001b00; *\/\n\/* rom_tsens_code_read = 0x40001b04; *\/\nrom_tsens_index_to_dac = 0x40001b08;\nrom_tsens_index_to_offset = 0x40001b0c;\n\/* rom_tsens_dac_cal = 0x40001b10; *\/\nrom_code_to_temp = 0x40001b14;\nrom_write_pll_cap_mem = 0x40001b18;\nrom_pll_correct_dcap = 0x40001b1c;\nrom_phy_en_hw_set_freq = 0x40001b20;\nrom_phy_dis_hw_set_freq = 0x40001b24;\nrom_pll_vol_cal = 0x40001b28;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"90ae0348d73f626f8880f3b3e971240ea97d0428","subject":"update ld script","message":"update ld script\n","repos":"stateos\/IntrOS,stateos\/IntrOS,stateos\/IntrOS","old_file":"startup\/STM32F4\/GCC\/script_gcc.ld","new_file":"startup\/STM32F4\/GCC\/script_gcc.ld","new_contents":"\/*******************************************************************************\n@file     stm32f4xx.ld\n@author   Rajmund Szymanski\n@date     08.03.2016\n@brief    Linker script for STM32F407VG device with 1024KB FLASH and 192KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 1024k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   64k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  128k\n\/*\tAUX (rwx) : ORIGIN = 0x2001C000, LENGTH =   16k\n*\/\tBKP (rwx) : ORIGIN = 0x40024000, LENGTH =    4k\n}\n\nREGION_ALIAS(\"TEXT\", ROM);\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(TEXT);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > TEXT\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > TEXT\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > TEXT\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > TEXT\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > TEXT\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__stack_start = .;\n\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\n\t\t__stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = __main_stack_end - __main_stack_start;\n\t__proc_stack_size = __proc_stack_end - __proc_stack_start;\n\n\t__stack_size = SIZEOF(.stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > TEXT\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t__heap_end = ABSOLUTE(__ram_end);\n\t} > RAM\n\n\tPROVIDE(__initial_msp = __main_stack_size ? __main_stack_end : __ram_end);\n\tPROVIDE(__initial_psp = __proc_stack_end);\n\tPROVIDE(__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp);\n\n\tPROVIDE(__bss_start__ = __bss_start);\n\tPROVIDE(__bss_end__   = __bss_end);\n\tPROVIDE(__heap_base__ = __heap_start);\n\tPROVIDE(__heap_end__  = __heap_end);\n\tPROVIDE(__heap_base   = __heap_start);\n\tPROVIDE(__heap_limit  = __heap_end);\n\tPROVIDE(__stack       = __initial_sp);\n\tPROVIDE(__end__       = __bss_end);\n\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","old_contents":"\/*******************************************************************************\n@file     stm32f4xx.ld\n@author   Rajmund Szymanski\n@date     22.02.2016\n@brief    Linker script for STM32F407VG device with 1024KB FLASH and 192KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 1024k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   64k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  128k\n\/*\tAUX (rwx) : ORIGIN = 0x2001C000, LENGTH =   16k\n*\/\tBKP (rwx) : ORIGIN = 0x40024000, LENGTH =    4k\n}\n\nREGION_ALIAS(\"TEXT\", ROM);\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(TEXT);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > TEXT\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > TEXT\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > TEXT\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > TEXT\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > TEXT\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__stack_start = .;\n\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\n\t\t__stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = __main_stack_end - __main_stack_start;\n\t__proc_stack_size = __proc_stack_end - __proc_stack_start;\n\n\t__stack_size = SIZEOF(.stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > TEXT\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t__heap_end = ABSOLUTE(__ram_end);\n\t} > RAM\n\n\tPROVIDE(__initial_msp = __main_stack_size ? __main_stack_end : __ram_end);\n\tPROVIDE(__initial_psp = __proc_stack_end);\n\tPROVIDE(__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp);\n\n\tPROVIDE(__bss_start__ = __bss_start);\n\tPROVIDE(__bss_end__   = __bss_end);\n\tPROVIDE(__heap_base__ = __heap_start);\n\tPROVIDE(__heap_end__  = __heap_end);\n\tPROVIDE(__heap_base   = __heap_start);\n\tPROVIDE(__heap_limit  = __heap_end);\n\tPROVIDE(__stack       = __initial_sp);\n\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0bc5c1dc20ec96deae3335e590ec40fe5085cbc7","subject":"kernel sections alignment bugfixes","message":"kernel sections alignment bugfixes\n","repos":"stoyan-shopov\/dt,stoyan-shopov\/dt","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"MEMORY\n{\n\trom (rx)\t:\tORIGIN = 0x50000, LENGTH = 0xa0000 - 0x50000\n\tram (rwx)\t:\tORIGIN = 0x100000, LENGTH = 0x100000\n}\n\nSECTIONS\n{\n\t.text\t\t: { *(.text) } > rom\n\t.init_startup ALIGN(8) : \n\t{\n\t\t_init_startup\t\t= .;\n\t\t*(.ctors)\n\t\t_init_startup_end\t= .;\n\t} > rom\n\t.x86_idt ALIGN(8)\t: { *(.x86_idt) } > rom\n\t.rodata ALIGN(8)\t: {\n\t\t*(.rodata)\n\t\t_idata_contents_start\t= .;\n\t} > rom\n\n\t.init_pgdir_tab :\n\t{\n\t\t*(.init_pgdir)\n\t} > ram\n\n\t.common-data ALIGN(4096)\t:\n\t{\n\t\t*(.common-data)\n\t} > ram\n\n\t.data ALIGN(4096)\t:\n\t{\n\t\t_data_start\t= .;\n\t\t*(.data)\n\t\t_data_end\t= .;\n\t} > ram AT> rom\n\n\t.bss ALIGN(1024) :\n\t{\n\t\t_bss_start = . ;\n\t\t*(.bss .bss*)\n\t\t_bss_end = . ;\n\t} > ram\n\n\t\/DISCARD\/ : \n\t{\n\t\t\t*(.eh_frame*)\n\t}\n}\n","old_contents":"MEMORY\n{\n\trom (rx)\t:\tORIGIN = 0x50000, LENGTH = 0xa0000 - 0x50000\n\tram (rwx)\t:\tORIGIN = 0x100000, LENGTH = 0x100000\n}\n\nSECTIONS\n{\n\t.text\t\t: { *(.text) } > rom\n\t.init_startup ALIGN(8) : \n\t{\n\t\t_init_startup\t\t= .;\n\t\t*(.ctors)\n\t\t_init_startup_end\t= .;\n\t} > rom\n\t.x86_idt ALIGN(8)\t: { *(.x86_idt) } > rom\n\t.rodata ALIGN(8)\t: {\n\t\t*(.rodata)\n\t\t_idata_contents_start\t= .;\n\t} > rom\n\n\t.init_pgdir_tab :\n\t{\n\t\t*(.init_pgdir)\n\t} > ram\n\n\t.common-data ALIGN(1024)\t:\n\t{\n\t\t*(.common-data)\n\t} > ram\n\n\t.data ALIGN(1024)\t:\n\t{\n\t\t_data_start\t= .;\n\t\t*(.data)\n\t\t_data_end\t= .;\n\t} > ram AT> rom\n\n\t.bss ALIGN(1024) :\n\t{\n\t\t_bss_start = . ;\n\t\t*(.bss .bss*)\n\t\t_bss_end = . ;\n\t} > ram\n\n\t\/DISCARD\/ : \n\t{\n\t\t\t*(.eh_frame*)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"6609dfb516f67ca72fd20b57c3679af006cea035","subject":"[stm32] fix linkscript issue in stm32f411-atk-nano","message":"[stm32] fix linkscript issue in stm32f411-atk-nano\n","repos":"weety\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,weety\/rt-thread,armink\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread","old_file":"bsp\/stm32\/stm32f411-atk-nano\/board\/linker_scripts\/link.lds","new_file":"bsp\/stm32\/stm32f411-atk-nano\/board\/linker_scripts\/link.lds","new_contents":"\/*\n * linker script for STM32F4xx with GNU ld\n * bernard.xiong 2009-10-14\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256k \/* 256KB flash *\/\n    RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k \/* 128K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n\n        _etext = .;\n    } > ROM = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > ROM\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >RAM\n\n    .stack : \n    {\n        . = ALIGN(4);\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >RAM\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > RAM\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * linker script for STM32F4xx with GNU ld\n * bernard.xiong 2009-10-14\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256 \/* 256KB flash *\/\n    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  128k \/* 128K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n\n        _etext = .;\n    } > ROM = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > ROM\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >RAM\n\n    .stack : \n    {\n        . = ALIGN(4);\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >RAM\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > RAM\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a8c999a1e323d83fe142a4987bae92b73efff8aa","subject":"Reorders link-time symbols to make all code come at lower addresses than data.","message":"Reorders link-time symbols to make all code come at lower addresses than data.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"test\/targets\/freertos.armv4t.lpc2368\/target.ld","new_file":"test\/targets\/freertos.armv4t.lpc2368\/target.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(entry)\n\n\/*INCLUDE \"testlibmbed_Debug_lib.ld\"*\/\nGROUP(\n libgcc.a\n libc.a\n libstdc++.a\n libm.a\n \/*libcr_newlib_nohost.a*\/\n crti.o\n crtn.o\n crtbegin.o\n crtend.o\n )\n\n\n\/* Memory Definitions: *\/\nMEMORY\n{\n    Flash  (rx)  : ORIGIN = 0x00005000, LENGTH = 480k\n    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 64k\n    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 16k\n    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k\n    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k\n    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k\n}\n\n\/* Stack sizes: *\/\nUND_Stack_Size = 32;\nABT_Stack_Size = 32;\nFIQ_Stack_Size = 32;\nIRQ_Stack_Size = 0x400;\nSVC_Stack_Size = 0x400;\nSYS_Stack_Size = 0x800; \/*main stack size*\/\n\nStack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;\n\n\/* Stack tops for each mode: *\/\n__stacks_top__ = __ETHRAM_segment_end__;\n__und_stack_top__ = __stacks_top__;\n__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;\n__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;\n__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;\n__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;\n__sys_stack_top__ = __svc_stack_top__ - SVC_Stack_Size ;\n__stacks_min__ = __sys_stack_top__ - SYS_Stack_Size;\n\n\/* C-accessible symbols for memory address ranges: *\/\n__FLASH_segment_start__ = ORIGIN( Flash );\n__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );\n__SRAM_segment_start__  = ORIGIN( Ram );\n__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );\n__ETHRAM_segment_start__  = ORIGIN( EthRam );\n__ETHRAM_segment_end__    = ORIGIN( EthRam ) + LENGTH( EthRam );\n\n\n\n\/* This symbol is used by malloc to ensure heap does not run oit of its\nallotted space (e.g. by colliding with stacks, or by reaching the end of the\nram segment. *\/\nPROVIDE(__cs3_heap_end = __SRAM_segment_end__);\n\nSECTIONS\n{\n    \/* first section is .text which is used for code *\/\n    __text_start__ = . ;\n    .text : {\n        __privileged_code_start__ = . ;\n        KEEP( *( .vectors ) )\n        *( .privileged_code )\n    \n        __privileged_code_end__ = .;\n\n        . = ALIGN( 4 ) ;\n        *( .text .text.* .gnu.linkonce.t.* )\n        *( .plt )\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *( .init ) )\n        . = ALIGN( 4 ) ;\n        KEEP( *( .fini ) )\n        . = ALIGN( 4 ) ;\n        __preinit_array_start = . ;\n        KEEP( *( .preinit_array ) )\n        __preinit_array_end = . ;\n        . = ALIGN( 4 ) ;\n        __init_array_start = . ;\n        KEEP( *( SORT( .init_array.* ) ) )\n        KEEP( *( .init_array ) )\n        __init_array_end = . ;\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *crtbegin.o( .ctors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )\n        KEEP( *( SORT( .ctors.* ) ) )\n        KEEP( *crtend.o( .ctors ) )\n        \n        . = ALIGN( 4 ) ;\n        __fini_array_start = . ;\n        KEEP( *( .fini_array ) )\n        KEEP( *( SORT( .fini_array.* ) ) )\n        __fini_array_end = . ;\n        \n        KEEP( *crtbegin.o( .dtors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )\n        KEEP( *( SORT( .dtors.* ) ) )\n        KEEP( *crtend.o( .dtors ) )\n\n        *( .gnu.warning )\n        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )\n\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n        \n        *( .rodata )\n        *(SORT(.rodata.*))\n\t*(SORT(.gnu.linkonce.r.*))\n    } >Flash\n    \n    __exidx_start = . ;\n    .ARM.exidx : {\n        *( .ARM.exidx* .gnu.linkonce.armexidx.* )\n    } >Flash\n    __exidx_end = . ;\n    \n    .text.align : { . = ALIGN( 8 ) ; } >Flash \/* Alignment schenanigans *\/\n    __text_end__ = . ;\n    \n    \/* .bss section -- used for uninitialized data *\/\n    \/* Located at the start of RAM *\/\n    .bss (NOLOAD) : {\n        __bss_start__ = . ;\n        *( .ram_vectors )\n        \n        __user_bss_start__ = . ;\n        *( .user_bss )\n        __user_bss_end__ = . ;\n        \n        *( .shbss )\n        *( .bss .bss.* .gnu.linkonce.b.* )\n        *( COMMON )\n        *( .ram.b )\n        . = ALIGN( 8 ) ;\n        \n        __bss_end__ = . ;\n    } >Ram AT>Flash\n\n    \/* .data section -- used for initialized data *\/\n    .data : {\n\tFILL(0xff)\n        __data_start__ = . ;\n        KEEP( *( .jcr ) )\n        *( .got.plt ) *( .got )\n        *( .shdata )\n        *( .data .data.* .gnu.linkonce.d.* )\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n        . = ALIGN (4);\n\n        *( .ram )\n        . = ALIGN( 8 ) ;\n        __data_end__ = . ;\n    } >Ram AT>Flash\n\n    __data_init_start__ = LOADADDR( .data ) ;\n\n    \/* Heap starts here and grows up in memory *\/\n    . = ALIGN( 8 ) ;\n    __heap_start__ = . ;\n    __cs3_heap_start = .;\n\n\tPROVIDE(_pvHeapStart = .);\n\t\n    .stab    0 (NOLOAD) : { *(.stab) }\n    .stabstr 0 (NOLOAD) : { *(.stabstr) }\n    \/* DWARF debug sections. *\/\n    \/* Symbols in the DWARF debugging sections are relative to the  *\/\n    \/* beginning of the section so we begin them at 0.              *\/\n    \/* DWARF 1 *\/\n    .debug           0 : { *(.debug) }\n    .line            0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo   0 : { *(.debug_srcinfo) }\n    .debug_sfnames   0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges   0 : { *(.debug_aranges) }\n    .debug_pubnames  0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev    0 : { *(.debug_abbrev) }\n    .debug_line      0 : { *(.debug_line) }\n    .debug_frame     0 : { *(.debug_frame) }\n    .debug_str       0 : { *(.debug_str) }\n    .debug_loc       0 : { *(.debug_loc) }\n    .debug_macinfo   0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n    \/* DWARF 3 *\/\n    .debug_pubtypes  0 : { *(.debug_pubtypes) }\n    .debug_ranges    0 : { *(.debug_ranges) }\n    \n    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }\n    .ARM.attributes     0 : {\n        KEEP( *( .ARM.attributes ) )\n        KEEP( *( .gnu.attributes ) )\n    }\n    \/DISCARD\/             : { *( .note.GNU-stack ) }\n    \n    \/* C data can be defined as being in special purpose RAMs using\n     * __attribute__ ((section (\"ethram\"))) for example. *\/\n    .usbram (NOLOAD):\n    {\n        *( .usbram )\n        *( .usbram.* )\n    } > UsbRam\n    .ethram (NOLOAD):\n    {\n        *( .ethram )\n        *( .ethram.* )\n    } > EthRam\n    .canram (NOLOAD):\n    {\n        *( .canram )\n        *( .canram.* )\n    } > CanRam\n    .batram (NOLOAD):\n    {\n        *( .batram )\n        *( .batram.* )\n    } > BatRam\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(entry)\n\n\/*INCLUDE \"testlibmbed_Debug_lib.ld\"*\/\nGROUP(\n libgcc.a\n libc.a\n libstdc++.a\n libm.a\n \/*libcr_newlib_nohost.a*\/\n crti.o\n crtn.o\n crtbegin.o\n crtend.o\n )\n\n\n\/* Memory Definitions: *\/\nMEMORY\n{\n    Flash  (rx)  : ORIGIN = 0x00005000, LENGTH = 480k\n    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 64k\n    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 16k\n    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k\n    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k\n    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k\n}\n\n\/* Stack sizes: *\/\nUND_Stack_Size = 32;\nABT_Stack_Size = 32;\nFIQ_Stack_Size = 32;\nIRQ_Stack_Size = 0x400;\nSVC_Stack_Size = 0x400;\nSYS_Stack_Size = 0x800; \/*main stack size*\/\n\nStack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;\n\n\/* Stack tops for each mode: *\/\n__stacks_top__ = __ETHRAM_segment_end__;\n__und_stack_top__ = __stacks_top__;\n__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;\n__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;\n__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;\n__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;\n__sys_stack_top__ = __svc_stack_top__ - SVC_Stack_Size ;\n__stacks_min__ = __sys_stack_top__ - SYS_Stack_Size;\n\n\/* C-accessible symbols for memory address ranges: *\/\n__FLASH_segment_start__ = ORIGIN( Flash );\n__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );\n__SRAM_segment_start__  = ORIGIN( Ram );\n__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );\n__ETHRAM_segment_start__  = ORIGIN( EthRam );\n__ETHRAM_segment_end__    = ORIGIN( EthRam ) + LENGTH( EthRam );\n\n\n\n\/* This symbol is used by malloc to ensure heap does not run oit of its\nallotted space (e.g. by colliding with stacks, or by reaching the end of the\nram segment. *\/\nPROVIDE(__cs3_heap_end = __SRAM_segment_end__);\n\nSECTIONS\n{\n    \/* first section is .text which is used for code *\/\n    __text_start__ = . ;\n    .text : {\n        __privileged_code_start__ = . ;\n        KEEP( *( .vectors ) )\n        *( .privileged_code )\n    \n        __privileged_code_end__ = .;\n\n        *( .text .text.* .gnu.linkonce.t.* )\n        *( .plt )\n        *( .gnu.warning )\n        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )\n        \n        *( .rodata .rodata.* .gnu.linkonce.r.* )\n        \n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.gcc_except_table)\n        *(.eh_frame_hdr)\n        *(.eh_frame)\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *( .init ) )\n        . = ALIGN( 4 ) ;\n        __preinit_array_start = . ;\n        KEEP( *( .preinit_array ) )\n        __preinit_array_end = . ;\n        . = ALIGN( 4 ) ;\n        __init_array_start = . ;\n        KEEP( *( SORT( .init_array.* ) ) )\n        KEEP( *( .init_array ) )\n        __init_array_end = . ;\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *crtbegin.o( .ctors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )\n        KEEP( *( SORT( .ctors.* ) ) )\n        KEEP( *crtend.o( .ctors ) )\n        \n        . = ALIGN( 4 ) ;\n        KEEP( *( .fini ) )\n        . = ALIGN( 4 ) ;\n        __fini_array_start = . ;\n        KEEP( *( .fini_array ) )\n        KEEP( *( SORT( .fini_array.* ) ) )\n        __fini_array_end = . ;\n        \n        KEEP( *crtbegin.o( .dtors ) )\n        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )\n        KEEP( *( SORT( .dtors.* ) ) )\n        KEEP( *crtend.o( .dtors ) )\n    \n    } >Flash\n    \n    __exidx_start = . ;\n    .ARM.exidx : {\n        *( .ARM.exidx* .gnu.linkonce.armexidx.* )\n    } >Flash\n    __exidx_end = . ;\n    \n    .text.align : { . = ALIGN( 8 ) ; } >Flash \/* Alignment schenanigans *\/\n    __text_end__ = . ;\n    \n    \/* .bss section -- used for uninitialized data *\/\n    \/* Located at the start of RAM *\/\n    .bss (NOLOAD) : {\n        __bss_start__ = . ;\n        *( .ram_vectors )\n        \n        __user_bss_start__ = . ;\n        *( .user_bss )\n        __user_bss_end__ = . ;\n        \n        *( .shbss )\n        *( .bss .bss.* .gnu.linkonce.b.* )\n        *( COMMON )\n        *( .ram.b )\n        . = ALIGN( 8 ) ;\n        \n        __bss_end__ = . ;\n    } >Ram AT>Flash\n\n    \/* .data section -- used for initialized data *\/\n    .data : {\n\tFILL(0xff)\n        __data_start__ = . ;\n        KEEP( *( .jcr ) )\n        *( .got.plt ) *( .got )\n        *( .shdata )\n        *( .data .data.* .gnu.linkonce.d.* )\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n        . = ALIGN (4);\n\n        *( .ram )\n        . = ALIGN( 8 ) ;\n        __data_end__ = . ;\n    } >Ram AT>Flash\n\n    __data_init_start__ = LOADADDR( .data ) ;\n\n    \/* Heap starts here and grows up in memory *\/\n    . = ALIGN( 8 ) ;\n    __heap_start__ = . ;\n    __cs3_heap_start = .;\n\n\tPROVIDE(_pvHeapStart = .);\n\t\n    .stab    0 (NOLOAD) : { *(.stab) }\n    .stabstr 0 (NOLOAD) : { *(.stabstr) }\n    \/* DWARF debug sections. *\/\n    \/* Symbols in the DWARF debugging sections are relative to the  *\/\n    \/* beginning of the section so we begin them at 0.              *\/\n    \/* DWARF 1 *\/\n    .debug           0 : { *(.debug) }\n    .line            0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo   0 : { *(.debug_srcinfo) }\n    .debug_sfnames   0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges   0 : { *(.debug_aranges) }\n    .debug_pubnames  0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev    0 : { *(.debug_abbrev) }\n    .debug_line      0 : { *(.debug_line) }\n    .debug_frame     0 : { *(.debug_frame) }\n    .debug_str       0 : { *(.debug_str) }\n    .debug_loc       0 : { *(.debug_loc) }\n    .debug_macinfo   0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n    \/* DWARF 3 *\/\n    .debug_pubtypes  0 : { *(.debug_pubtypes) }\n    .debug_ranges    0 : { *(.debug_ranges) }\n    \n    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }\n    .ARM.attributes     0 : {\n        KEEP( *( .ARM.attributes ) )\n        KEEP( *( .gnu.attributes ) )\n    }\n    \/DISCARD\/             : { *( .note.GNU-stack ) }\n    \n    \/* C data can be defined as being in special purpose RAMs using\n     * __attribute__ ((section (\"ethram\"))) for example. *\/\n    .usbram (NOLOAD):\n    {\n        *( .usbram )\n        *( .usbram.* )\n    } > UsbRam\n    .ethram (NOLOAD):\n    {\n        *( .ethram )\n        *( .ethram.* )\n    } > EthRam\n    .canram (NOLOAD):\n    {\n        *( .canram )\n        *( .canram.* )\n    } > CanRam\n    .batram (NOLOAD):\n    {\n        *( .batram )\n        *( .batram.* )\n    } > BatRam\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"ef6d583ec3b358c0ec925497395a97ef21dd54f7","subject":"nrf5\/boards: Updating nrf51822_aa_s110.ld to be more generic, leaving all RAM not used for stack, .bss and .data to the heap.","message":"nrf5\/boards: Updating nrf51822_aa_s110.ld to be more generic, leaving all RAM not used for stack, .bss and .data to the heap.\n","repos":"adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,tralamazza\/micropython","old_file":"nrf5\/boards\/nrf51822_aa_s110.ld","new_file":"nrf5\/boards\/nrf51822_aa_s110.ld","new_contents":"\/*\n    GNU linker script for NRF51822 AA w\/ S110 8.0.0 SoftDevice\n*\/\n\/* Specify the memory areas *\/\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00018000, LENGTH = 0x000400 \/* sector 0, 1 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 \/* 159 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20002000, LENGTH = 0x002000 \/* 8 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 1K;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20003c00; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF51822 AA w\/ S110 8.0.0 SoftDevice\n*\/\n\/* Specify the memory areas *\/\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00018000, LENGTH = 0x000400 \/* sector 0, 1 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 \/* 159 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20001000, LENGTH = 0x003000 \/* 12 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 8K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20003000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"6bfdca4e66822676cde0e090e91624bd6d27d334","subject":"Updates memory map of F091RC to reflect that this is a 256k flash part.","message":"Updates memory map of F091RC to reflect that this is a 256k flash part.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/st-stm32f091rc-nucleo\/memory_map.ld","new_file":"boards\/st-stm32f091rc-nucleo\/memory_map.ld","new_contents":"MEMORY\n{\n  FLASH      (rx)  : ORIGIN = 0x08000000, LENGTH = 240K\n  EEPROMEMU  (r)   : ORIGIN = 0x0803C000, LENGTH = 8K\n  BOOTLOADER (rx)  : ORIGIN = 0x0803E000, LENGTH = 8K\n  RAM        (rwx) : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\n__flash_start = ORIGIN(FLASH);\n__flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n__eeprom_start = ORIGIN(EEPROMEMU);\n__eeprom_end = ORIGIN(EEPROMEMU) + LENGTH(EEPROMEMU);\n__bootloader_start = ORIGIN(BOOTLOADER);\n__app_header_offset = 0x270;\n__bootloader_magic_ptr = ORIGIN(RAM);\n","old_contents":"MEMORY\n{\n  FLASH      (rx)  : ORIGIN = 0x08000000, LENGTH = 116K\n  EEPROMEMU  (r)   : ORIGIN = 0x0801D000, LENGTH = 4K\n  BOOTLOADER (rx)  : ORIGIN = 0x0801E000, LENGTH = 8K\n  RAM        (rwx) : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\n__flash_start = ORIGIN(FLASH);\n__flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n__eeprom_start = ORIGIN(EEPROMEMU);\n__eeprom_end = ORIGIN(EEPROMEMU) + LENGTH(EEPROMEMU);\n__bootloader_start = ORIGIN(BOOTLOADER);\n__app_header_offset = 0x270;\n__bootloader_magic_ptr = ORIGIN(RAM);\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"876deb420dfe1d18ce8f6a278c77d4b190b6f161","subject":"soc: intel_s1000: add lpsram in linker script","message":"soc: intel_s1000: add lpsram in linker script\n\nAdd LPSRAM definition in MEMORY\nPlace DMA buffer section in LPSRAM\n\nSigned-off-by: Sathish Kuttan <88b3ab91bbfd8c103d682ea5f9059cf275a3b834@intel.com>\n","repos":"zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr","old_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <generated_dts_board.h>\n#include \"memory.h\"\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#define LPRAM_REGION lpram\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LPRAM_BASE,\n\tlen = LPRAM_SIZE\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-through\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-through\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_s1000 = 0x1212fff2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    . = CONFIG_TEXT_SECTION_OFFSET;\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LPRAM_REGION\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <generated_dts_board.h>\n#include \"memory.h\"\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-through\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-through\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_s1000 = 0x1212fff2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    . = CONFIG_TEXT_SECTION_OFFSET;\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"0ee896117cb55c5d83ba069f30cf97c22e9d4ce3","subject":"linker: ifdef thread local storage script","message":"linker: ifdef thread local storage script\n\nXCC Clang doesn't emit load address when a section\nis empty, resulting in __tdata_start not being\ndefined. So put a #ifdef guard for the thread local\nstorage linker script to avoid this issue.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr","old_file":"include\/linker\/thread-local-storage.ld","new_file":"include\/linker\/thread-local-storage.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#ifdef CONFIG_THREAD_LOCAL_STORAGE\n\n\tSECTION_DATA_PROLOGUE(tdata,,)\n\t{\n\t\t*(.tdata .tdata.* .gnu.linkonce.td.*);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(tbss,,)\n\t{\n\t\t*(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t\/*\n\t * These needs to be outside of the tdata\/tbss\n\t * sections or else they would be considered\n\t * thread-local variables, and the code would use\n\t * the wrong values.\n\t *\/\n\tPROVIDE(__tdata_start = LOADADDR(tdata));\n\tPROVIDE(__tdata_size = SIZEOF(tdata));\n\tPROVIDE(__tdata_end = __tdata_start + __tdata_size);\n\n\tPROVIDE(__tbss_start = LOADADDR(tbss));\n\tPROVIDE(__tbss_size = SIZEOF(tbss));\n\tPROVIDE(__tbss_end = __tbss_start + __tbss_size);\n\n\tPROVIDE(__tls_start = __tdata_start);\n\tPROVIDE(__tls_end = __tbss_end);\n\tPROVIDE(__tls_size = __tbss_end - __tdata_start);\n\n#endif \/* CONFIG_THREAD_LOCAL_STORAGE *\/\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\tSECTION_DATA_PROLOGUE(tdata,,)\n\t{\n\t\t*(.tdata .tdata.* .gnu.linkonce.td.*);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(tbss,,)\n\t{\n\t\t*(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t\/*\n\t * These needs to be outside of the tdata\/tbss\n\t * sections or else they would be considered\n\t * thread-local variables, and the code would use\n\t * the wrong values.\n\t *\/\n\tPROVIDE(__tdata_start = LOADADDR(tdata));\n\tPROVIDE(__tdata_size = SIZEOF(tdata));\n\tPROVIDE(__tdata_end = __tdata_start + __tdata_size);\n\n\tPROVIDE(__tbss_start = LOADADDR(tbss));\n\tPROVIDE(__tbss_size = SIZEOF(tbss));\n\tPROVIDE(__tbss_end = __tbss_start + __tbss_size);\n\n\tPROVIDE(__tls_start = __tdata_start);\n\tPROVIDE(__tls_end = __tbss_end);\n\tPROVIDE(__tls_size = __tbss_end - __tdata_start);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5f853be2df5b98142aec6d8e0ae8a4a2d397a896","subject":"update link script","message":"update link script\n\ngit-svn-id: 839522a79b1d56a78fa446d2fd3a0c499f8e535e@2121 bbd45198-f89e-11dd-88c7-29a3b14d5316\n","repos":"ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,armink\/rt-thread,yongli3\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,zhaojuntao\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,armink\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,yongli3\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,weiyuliang\/rt-thread,hezlog\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,yongli3\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,zhaojuntao\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,yongli3\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,nongxiaoming\/rt-thread,igou\/rt-thread,igou\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,AubrCool\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread","old_file":"bsp\/stm32f20x\/stm32_rom.ld","new_file":"bsp\/stm32f20x\/stm32_rom.ld","new_contents":"\/*\r\n * linker script for STM32F10x with GNU ld\r\n * bernard.xiong 2009-10-14\r\n *\/\r\n\r\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\r\nMEMORY\r\n{\r\n    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k \/* 512KB flash *\/\r\n    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  128k \/* 64K sram *\/\r\n}\r\nENTRY(Reset_Handler)\r\n_system_stack_size = 0x100;\r\n\r\nSECTIONS\r\n{\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        KEEP(*(.isr_vector))            \/* Startup code *\/\r\n        . = ALIGN(4);\r\n        *(.text)                        \/* remaining code *\/\r\n        *(.text.*)                      \/* remaining code *\/\r\n        *(.rodata)                      \/* read-only data (constants) *\/\r\n        *(.rodata*)\r\n        *(.glue_7)\r\n        *(.glue_7t)\r\n        *(.gnu.linkonce.t*)\r\n\r\n        \/* section information for finsh shell *\/\r\n        . = ALIGN(4);\r\n        __fsymtab_start = .;\r\n        KEEP(*(FSymTab))\r\n        __fsymtab_end = .;\r\n        . = ALIGN(4);\r\n        __vsymtab_start = .;\r\n        KEEP(*(VSymTab))\r\n        __vsymtab_end = .;\r\n        . = ALIGN(4);\r\n\r\n        . = ALIGN(4);\r\n        _etext = .;\r\n    } > CODE = 0\r\n\r\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n    __exidx_start = .;\r\n    .ARM.exidx :\r\n    {\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sidata = .;\r\n    } > CODE\r\n    __exidx_end = .;\r\n\r\n    \/* .data section which is used for initialized data *\/\r\n\r\n    .data : AT (_sidata)\r\n    {\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sdata = . ;\r\n\r\n        *(.data)\r\n        *(.data.*)\r\n        *(.gnu.linkonce.d*)\r\n\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _edata = . ;\r\n    } >DATA\r\n\r\n\t.stack : \r\n\t{\r\n\t\t. = . + _system_stack_size;\r\n\t\t. = ALIGN(4);\r\n\t\t_estack = .;\r\n\t} >DATA\r\n\r\n    __bss_start = .;\r\n    .bss :\r\n    {\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _sbss = .;\r\n\r\n        *(.bss)\r\n        *(.bss.*)\r\n        *(COMMON)\r\n\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _ebss = . ;\r\n        \r\n        *(.bss.init)\r\n    } > DATA\r\n    __bss_end = .;\r\n\r\n    _end = .;\r\n\r\n    \/* Stabs debugging sections.  *\/\r\n    .stab          0 : { *(.stab) }\r\n    .stabstr       0 : { *(.stabstr) }\r\n    .stab.excl     0 : { *(.stab.excl) }\r\n    .stab.exclstr  0 : { *(.stab.exclstr) }\r\n    .stab.index    0 : { *(.stab.index) }\r\n    .stab.indexstr 0 : { *(.stab.indexstr) }\r\n    .comment       0 : { *(.comment) }\r\n    \/* DWARF debug sections.\r\n     * Symbols in the DWARF debugging sections are relative to the beginning\r\n     * of the section so we begin them at 0.  *\/\r\n    \/* DWARF 1 *\/\r\n    .debug          0 : { *(.debug) }\r\n    .line           0 : { *(.line) }\r\n    \/* GNU DWARF 1 extensions *\/\r\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n    .debug_sfnames  0 : { *(.debug_sfnames) }\r\n    \/* DWARF 1.1 and DWARF 2 *\/\r\n    .debug_aranges  0 : { *(.debug_aranges) }\r\n    .debug_pubnames 0 : { *(.debug_pubnames) }\r\n    \/* DWARF 2 *\/\r\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n    .debug_abbrev   0 : { *(.debug_abbrev) }\r\n    .debug_line     0 : { *(.debug_line) }\r\n    .debug_frame    0 : { *(.debug_frame) }\r\n    .debug_str      0 : { *(.debug_str) }\r\n    .debug_loc      0 : { *(.debug_loc) }\r\n    .debug_macinfo  0 : { *(.debug_macinfo) }\r\n    \/* SGI\/MIPS DWARF 2 extensions *\/\r\n    .debug_weaknames 0 : { *(.debug_weaknames) }\r\n    .debug_funcnames 0 : { *(.debug_funcnames) }\r\n    .debug_typenames 0 : { *(.debug_typenames) }\r\n    .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","old_contents":"\/*\r\n * linker script for STM32F10x with GNU ld\r\n * bernard.xiong 2009-10-14\r\n *\/\r\n\r\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\r\nMEMORY\r\n{\r\n    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k \/* 512KB flash *\/\r\n    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  64k \/* 64K sram *\/\r\n}\r\nENTRY(Reset_Handler)\r\n_system_stack_size = 0x100;\r\n\r\nSECTIONS\r\n{\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        KEEP(*(.isr_vector))            \/* Startup code *\/\r\n        . = ALIGN(4);\r\n        *(.text)                        \/* remaining code *\/\r\n        *(.text.*)                      \/* remaining code *\/\r\n        *(.rodata)                      \/* read-only data (constants) *\/\r\n        *(.rodata*)\r\n        *(.glue_7)\r\n        *(.glue_7t)\r\n        *(.gnu.linkonce.t*)\r\n\r\n        \/* section information for finsh shell *\/\r\n        . = ALIGN(4);\r\n        __fsymtab_start = .;\r\n        KEEP(*(FSymTab))\r\n        __fsymtab_end = .;\r\n        . = ALIGN(4);\r\n        __vsymtab_start = .;\r\n        KEEP(*(VSymTab))\r\n        __vsymtab_end = .;\r\n        . = ALIGN(4);\r\n\r\n        . = ALIGN(4);\r\n        _etext = .;\r\n    } > CODE = 0\r\n\r\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n    __exidx_start = .;\r\n    .ARM.exidx :\r\n    {\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sidata = .;\r\n    } > CODE\r\n    __exidx_end = .;\r\n\r\n    \/* .data section which is used for initialized data *\/\r\n\r\n    .data : AT (_sidata)\r\n    {\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _sdata = . ;\r\n\r\n        *(.data)\r\n        *(.data.*)\r\n        *(.gnu.linkonce.d*)\r\n\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .data secion *\/\r\n        _edata = . ;\r\n    } >DATA\r\n\r\n\t.stack : \r\n\t{\r\n\t\t. = . + _system_stack_size;\r\n\t\t. = ALIGN(4);\r\n\t\t_estack = .;\r\n\t} >DATA\r\n\r\n    __bss_start = .;\r\n    .bss :\r\n    {\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _sbss = .;\r\n\r\n        *(.bss)\r\n        *(.bss.*)\r\n        *(COMMON)\r\n\r\n        . = ALIGN(4);\r\n        \/* This is used by the startup in order to initialize the .bss secion *\/\r\n        _ebss = . ;\r\n        \r\n        *(.bss.init)\r\n    } > DATA\r\n    __bss_end = .;\r\n\r\n    _end = .;\r\n\r\n    \/* Stabs debugging sections.  *\/\r\n    .stab          0 : { *(.stab) }\r\n    .stabstr       0 : { *(.stabstr) }\r\n    .stab.excl     0 : { *(.stab.excl) }\r\n    .stab.exclstr  0 : { *(.stab.exclstr) }\r\n    .stab.index    0 : { *(.stab.index) }\r\n    .stab.indexstr 0 : { *(.stab.indexstr) }\r\n    .comment       0 : { *(.comment) }\r\n    \/* DWARF debug sections.\r\n     * Symbols in the DWARF debugging sections are relative to the beginning\r\n     * of the section so we begin them at 0.  *\/\r\n    \/* DWARF 1 *\/\r\n    .debug          0 : { *(.debug) }\r\n    .line           0 : { *(.line) }\r\n    \/* GNU DWARF 1 extensions *\/\r\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n    .debug_sfnames  0 : { *(.debug_sfnames) }\r\n    \/* DWARF 1.1 and DWARF 2 *\/\r\n    .debug_aranges  0 : { *(.debug_aranges) }\r\n    .debug_pubnames 0 : { *(.debug_pubnames) }\r\n    \/* DWARF 2 *\/\r\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n    .debug_abbrev   0 : { *(.debug_abbrev) }\r\n    .debug_line     0 : { *(.debug_line) }\r\n    .debug_frame    0 : { *(.debug_frame) }\r\n    .debug_str      0 : { *(.debug_str) }\r\n    .debug_loc      0 : { *(.debug_loc) }\r\n    .debug_macinfo  0 : { *(.debug_macinfo) }\r\n    \/* SGI\/MIPS DWARF 2 extensions *\/\r\n    .debug_weaknames 0 : { *(.debug_weaknames) }\r\n    .debug_funcnames 0 : { *(.debug_funcnames) }\r\n    .debug_typenames 0 : { *(.debug_typenames) }\r\n    .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"41b9c9920901df6d83677e3f142e892a2d318f94","subject":"ARM: removed multiboot from linker script for now","message":"ARM: removed multiboot from linker script for now\n","repos":"alfred-bratterud\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,hioa-cs\/IncludeOS,alfred-bratterud\/IncludeOS,AnnikaH\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,hioa-cs\/IncludeOS,AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,alfred-bratterud\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS","old_file":"src\/arch\/aarch64\/linker.ld","new_file":"src\/arch\/aarch64\/linker.ld","new_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0x200000 + 0x40000000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n  __stack_top = _ELF_START_ -16;\n\n  . = _ELF_START_ + SIZEOF_HEADERS;\n\n  .text ALIGN(0x1000):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n\/**\n  *   Global constructors\n  *   Constructors are split into groups allowing the OS to use global ctors\n  *   before the OS itself is initialized, while delaying the calls to service constructors\n  *   until as much of the OS \/ C++ runtime as possible is ready.\n  *\/\n\n  \/* OS \/ stdlib constructors *\/\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    *\/aarch64\/lib\/lib*.a:*(.init_array* .ctors*)\n    *\/aarch64\/platform\/lib*.a:*(.init_array* .ctors*)\n    *\/aarch64\/drivers\/lib*.a:*(.init_array* .ctors*)\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  \/* Stdout g constructors *\/\n  .stdout_ctors :\n  {\n    PROVIDE_HIDDEN (__stdout_ctors_start = .);\n    *\/aarch64\/drivers\/stdout\/lib*.a:*(.init_array* .ctors*)\n    PROVIDE_HIDDEN (__stdout_ctors_end = .);\n  }\n\n  \/* Driver g constructors *\/\n  .driver_ctors :\n  {\n    PROVIDE_HIDDEN (__driver_ctors_start = .);\n    *\/aarch64\/drivers\/lib*.a:*(.init_array* .ctors*)\n    PROVIDE_HIDDEN (__driver_ctors_end = .);\n  }\n\n  \/* Plugin constructors *\/\n  .plugin_ctors :\n  {\n    PROVIDE_HIDDEN (__plugin_ctors_start = .);\n    *\/aarch64\/plugins\/lib*.a:*(.init_array* .ctors*)\n    PROVIDE_HIDDEN (__plugin_ctors_end = .);\n  }\n\n  \/* All other constructors *\/\n  .service_ctors :\n  {\n    PROVIDE_HIDDEN (__service_ctors_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__service_ctors_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  _EXEC_END_ = .;\n  _READONLY_START_ = .;\n  .config ALIGN(0x1000) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n  _READONLY_END_ = .;\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","old_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0x200000 + 0x40000000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n  __stack_top = _ELF_START_ -16;\n\n  . = _ELF_START_ + SIZEOF_HEADERS;\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n  .text ALIGN(0x1000):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n\/**\n  *   Global constructors\n  *   Constructors are split into groups allowing the OS to use global ctors\n  *   before the OS itself is initialized, while delaying the calls to service constructors\n  *   until as much of the OS \/ C++ runtime as possible is ready.\n  *\/\n\n  \/* OS \/ stdlib constructors *\/\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    *\/aarch64\/lib\/lib*.a:*(.init_array* .ctors*)\n    *\/aarch64\/platform\/lib*.a:*(.init_array* .ctors*)\n    *\/aarch64\/drivers\/lib*.a:*(.init_array* .ctors*)\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  \/* Stdout g constructors *\/\n  .stdout_ctors :\n  {\n    PROVIDE_HIDDEN (__stdout_ctors_start = .);\n    *\/aarch64\/drivers\/stdout\/lib*.a:*(.init_array* .ctors*)\n    PROVIDE_HIDDEN (__stdout_ctors_end = .);\n  }\n\n  \/* Driver g constructors *\/\n  .driver_ctors :\n  {\n    PROVIDE_HIDDEN (__driver_ctors_start = .);\n    *\/aarch64\/drivers\/lib*.a:*(.init_array* .ctors*)\n    PROVIDE_HIDDEN (__driver_ctors_end = .);\n  }\n\n  \/* Plugin constructors *\/\n  .plugin_ctors :\n  {\n    PROVIDE_HIDDEN (__plugin_ctors_start = .);\n    *\/aarch64\/plugins\/lib*.a:*(.init_array* .ctors*)\n    PROVIDE_HIDDEN (__plugin_ctors_end = .);\n  }\n\n  \/* All other constructors *\/\n  .service_ctors :\n  {\n    PROVIDE_HIDDEN (__service_ctors_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__service_ctors_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  _EXEC_END_ = .;\n  _READONLY_START_ = .;\n  .config ALIGN(0x1000) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n  _READONLY_END_ = .;\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9a1c5ec78eac75fee8dacb17ebd31706942dc252","subject":"soc\/intel_adsp: cavs-link.ld: add *(.trace_ctx) sections","message":"soc\/intel_adsp: cavs-link.ld: add *(.trace_ctx) sections\n\nThe CAVS linker scripts in Zephyr and \"plain\" (XTOS) SOF seem to share\nthe same origin and they mostly duplicate each other so they naturally\nkeep diverging from each other. This commit catches up with the SOF\ncommit ef43899c580f (thesofproject\/sof\/pull\/2996) which added\nthe *(.trace_ctx) sections as part of the runtime log filtering\nimplementation (feature request thesofproject\/sof\/issues\/2172)\n\nParaphrasing that commit, the goal is to create at link time a C-like\narray by regrouping scattered trace contexts so they can be iterated on.\n\nTogether with some other changes in SOF, these 3 additional lines are\nenough change in Zephyr to fix SOF bug thesofproject\/sof\/issues\/5032\n\nSigned-off-by: Marc Herbert <77e7c7d746b52c6eb01119b65a031ae1f650246d@intel.com>\n","repos":"galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <cavs-vectors.h>\n#include <cavs-mem.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n * (Note clumsy syntax because XCC doesn't understand the \"~\" operator)\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & 0xdfffffff) \/* == ~0x20000000 *\/\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#define ucram_phdr ram_phdr\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr\n\n .MemoryExceptionVector.literal : {\n    _MemoryExceptionVector_literal_start = .;\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = .;\n  } >vector_memory_lit\n  .MemoryExceptionVector.text : {\n    _MemoryExceptionVector_text_start = .;\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = .;\n  } >vector_memory_text\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int6_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int6_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.module_init)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n    *(.cached .cached.*)\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  \/* Heap start and end markers.  Mostly unused, though newlib likes them *\/\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <cavs-vectors.h>\n#include <cavs-mem.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n * (Note clumsy syntax because XCC doesn't understand the \"~\" operator)\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & 0xdfffffff) \/* == ~0x20000000 *\/\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#define ucram_phdr ram_phdr\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr\n\n .MemoryExceptionVector.literal : {\n    _MemoryExceptionVector_literal_start = .;\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = .;\n  } >vector_memory_lit\n  .MemoryExceptionVector.text : {\n    _MemoryExceptionVector_text_start = .;\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = .;\n  } >vector_memory_text\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int6_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int6_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.module_init)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n    *(.cached .cached.*)\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  \/* Heap start and end markers.  Mostly unused, though newlib likes them *\/\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"52115e30aa2ee0ce482a52e976781a4fbc6083bd","subject":"firmware.ld: reduce stack size","message":"firmware.ld: reduce stack size\n","repos":"dbitbox\/mcu,dbitbox\/mcu,dbitbox\/mcu,dbitbox\/mcu","old_file":"firmware.ld","new_file":"firmware.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\n\n\/*ramf (rx) : ORIGIN = 0x20000000, LENGTH = 0x0000027c\n  ram (rw) : ORIGIN = 0x2000027c, LENGTH = 0x0000FD84*\/\nMEMORY\n{\n\trom (rx)  : ORIGIN = 0x00409000, LENGTH = 0x00037000\n\tramf (rx) : ORIGIN = 0x20000000, LENGTH = 0x000000fc\n\tram (rw) : ORIGIN = 0x200000fc, LENGTH = 0x0000FF04\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x2800;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .; \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n    } > ramf\n\n    .data : AT (_etext + SIZEOF(.relocate))\n    {\n        . = ALIGN(0x1000);\n        _sdata = .;\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\n\n\/*ramf (rx) : ORIGIN = 0x20000000, LENGTH = 0x0000027c\n  ram (rw) : ORIGIN = 0x2000027c, LENGTH = 0x0000FD84*\/\nMEMORY\n{\n\trom (rx)  : ORIGIN = 0x00409000, LENGTH = 0x00037000\n\tramf (rx) : ORIGIN = 0x20000000, LENGTH = 0x000000fc\n\tram (rw) : ORIGIN = 0x200000fc, LENGTH = 0x0000FF04\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x3000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .; \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n    } > ramf\n\n    .data : AT (_etext + SIZEOF(.relocate))\n    {\n        . = ALIGN(0x1000);\n        _sdata = .;\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"cd6194aefcab407f1fe580766008216ebab7e4a0","subject":"esp8266\/esp8266.ld: Put FatFs to FlashROM.","message":"esp8266\/esp8266.ld: Put FatFs to FlashROM.\n","repos":"hosaka\/micropython,blazewicz\/micropython,dinau\/micropython,kerneltask\/micropython,selste\/micropython,hosaka\/micropython,matthewelse\/micropython,deshipu\/micropython,cwyark\/micropython,emfcamp\/micropython,puuu\/micropython,toolmacher\/micropython,matthewelse\/micropython,drrk\/micropython,praemdonck\/micropython,pramasoul\/micropython,kerneltask\/micropython,alex-march\/micropython,puuu\/micropython,hiway\/micropython,Peetz0r\/micropython-esp32,mpalomer\/micropython,tobbad\/micropython,Timmenem\/micropython,drrk\/micropython,oopy\/micropython,MrSurly\/micropython-esp32,oopy\/micropython,dinau\/micropython,infinnovation\/micropython,dmazzella\/micropython,henriknelson\/micropython,dmazzella\/micropython,blazewicz\/micropython,HenrikSolver\/micropython,turbinenreiter\/micropython,swegener\/micropython,henriknelson\/micropython,hiway\/micropython,tralamazza\/micropython,adafruit\/circuitpython,chrisdearman\/micropython,mhoffma\/micropython,tralamazza\/micropython,pramasoul\/micropython,pozetroninc\/micropython,micropython\/micropython-esp32,dmazzella\/micropython,turbinenreiter\/micropython,bvernoux\/micropython,blazewicz\/micropython,selste\/micropython,alex-robbins\/micropython,pfalcon\/micropython,jmarcelino\/pycom-micropython,infinnovation\/micropython,TDAbboud\/micropython,pozetroninc\/micropython,toolmacher\/micropython,dxxb\/micropython,pfalcon\/micropython,Timmenem\/micropython,cwyark\/micropython,jmarcelino\/pycom-micropython,ganshun666\/micropython,swegener\/micropython,henriknelson\/micropython,adafruit\/circuitpython,MrSurly\/micropython,TDAbboud\/micropython,Peetz0r\/micropython-esp32,turbinenreiter\/micropython,chrisdearman\/micropython,ganshun666\/micropython,torwag\/micropython,infinnovation\/micropython,toolmacher\/micropython,matthewelse\/micropython,pfalcon\/micropython,oopy\/micropython,SHA2017-badge\/micropython-esp32,ryannathans\/micropython,torwag\/micropython,adafruit\/micropython,micropython\/micropython-esp32,AriZuu\/micropython,adafruit\/micropython,ryannathans\/micropython,adafruit\/circuitpython,TDAbboud\/micropython,mpalomer\/micropython,tralamazza\/micropython,alex-march\/micropython,adafruit\/micropython,tuc-osg\/micropython,Timmenem\/micropython,Timmenem\/micropython,turbinenreiter\/micropython,HenrikSolver\/micropython,bvernoux\/micropython,oopy\/micropython,misterdanb\/micropython,deshipu\/micropython,mhoffma\/micropython,cwyark\/micropython,bvernoux\/micropython,tralamazza\/micropython,kerneltask\/micropython,TDAbboud\/micropython,kerneltask\/micropython,MrSurly\/micropython,misterdanb\/micropython,MrSurly\/micropython,oopy\/micropython,mhoffma\/micropython,swegener\/micropython,pramasoul\/micropython,dxxb\/micropython,misterdanb\/micropython,jmarcelino\/pycom-micropython,turbinenreiter\/micropython,mpalomer\/micropython,AriZuu\/micropython,alex-robbins\/micropython,chrisdearman\/micropython,drrk\/micropython,puuu\/micropython,Peetz0r\/micropython-esp32,emfcamp\/micropython,deshipu\/micropython,alex-march\/micropython,chrisdearman\/micropython,AriZuu\/micropython,blazewicz\/micropython,alex-march\/micropython,hiway\/micropython,lowRISC\/micropython,torwag\/micropython,alex-robbins\/micropython,ganshun666\/micropython,selste\/micropython,ganshun666\/micropython,AriZuu\/micropython,micropython\/micropython-esp32,praemdonck\/micropython,lowRISC\/micropython,mpalomer\/micropython,SHA2017-badge\/micropython-esp32,kerneltask\/micropython,SHA2017-badge\/micropython-esp32,pozetroninc\/micropython,ryannathans\/micropython,MrSurly\/micropython,pfalcon\/micropython,selste\/micropython,dxxb\/micropython,cwyark\/micropython,dmazzella\/micropython,drrk\/micropython,bvernoux\/micropython,tobbad\/micropython,deshipu\/micropython,hosaka\/micropython,lowRISC\/micropython,chrisdearman\/micropython,matthewelse\/micropython,swegener\/micropython,pramasoul\/micropython,MrSurly\/micropython-esp32,redbear\/micropython,redbear\/micropython,infinnovation\/micropython,trezor\/micropython,matthewelse\/micropython,puuu\/micropython,tuc-osg\/micropython,swegener\/micropython,tobbad\/micropython,SHA2017-badge\/micropython-esp32,MrSurly\/micropython-esp32,emfcamp\/micropython,bvernoux\/micropython,praemdonck\/micropython,trezor\/micropython,MrSurly\/micropython,lowRISC\/micropython,emfcamp\/micropython,HenrikSolver\/micropython,dxxb\/micropython,MrSurly\/micropython-esp32,praemdonck\/micropython,cwyark\/micropython,ryannathans\/micropython,PappaPeppar\/micropython,infinnovation\/micropython,pramasoul\/micropython,emfcamp\/micropython,redbear\/micropython,HenrikSolver\/micropython,redbear\/micropython,adafruit\/micropython,AriZuu\/micropython,PappaPeppar\/micropython,pfalcon\/micropython,selste\/micropython,tuc-osg\/micropython,TDAbboud\/micropython,hosaka\/micropython,adafruit\/circuitpython,torwag\/micropython,micropython\/micropython-esp32,micropython\/micropython-esp32,alex-robbins\/micropython,PappaPeppar\/micropython,pozetroninc\/micropython,deshipu\/micropython,dinau\/micropython,PappaPeppar\/micropython,trezor\/micropython,dinau\/micropython,tuc-osg\/micropython,toolmacher\/micropython,jmarcelino\/pycom-micropython,trezor\/micropython,adafruit\/circuitpython,tuc-osg\/micropython,henriknelson\/micropython,dxxb\/micropython,alex-march\/micropython,lowRISC\/micropython,hiway\/micropython,puuu\/micropython,Peetz0r\/micropython-esp32,praemdonck\/micropython,trezor\/micropython,Peetz0r\/micropython-esp32,mhoffma\/micropython,HenrikSolver\/micropython,redbear\/micropython,tobbad\/micropython,misterdanb\/micropython,MrSurly\/micropython-esp32,adafruit\/circuitpython,mpalomer\/micropython,adafruit\/micropython,Timmenem\/micropython,alex-robbins\/micropython,ganshun666\/micropython,misterdanb\/micropython,pozetroninc\/micropython,SHA2017-badge\/micropython-esp32,henriknelson\/micropython,jmarcelino\/pycom-micropython,mhoffma\/micropython,blazewicz\/micropython,PappaPeppar\/micropython,torwag\/micropython,matthewelse\/micropython,hiway\/micropython,hosaka\/micropython,ryannathans\/micropython,dinau\/micropython,toolmacher\/micropython,tobbad\/micropython,drrk\/micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"93e2527a640f6d051eeb136b7b15993ea18080fd","subject":"cc26x0: Adjust ldscript memory segment attributes","message":"cc26x0: Adjust ldscript memory segment attributes\n","repos":"biboc\/RIOT,rfuentess\/RIOT,yogo1212\/RIOT,BytesGalore\/RIOT,gebart\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,x3ro\/RIOT,OTAkeys\/RIOT,toonst\/RIOT,josephnoir\/RIOT,josephnoir\/RIOT,mtausig\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,yogo1212\/RIOT,yogo1212\/RIOT,lazytech-org\/RIOT,authmillenon\/RIOT,smlng\/RIOT,aeneby\/RIOT,cladmi\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,miri64\/RIOT,aeneby\/RIOT,mtausig\/RIOT,authmillenon\/RIOT,biboc\/RIOT,neiljay\/RIOT,mtausig\/RIOT,mfrey\/RIOT,kYc0o\/RIOT,neiljay\/RIOT,rfuentess\/RIOT,kYc0o\/RIOT,kbumsik\/RIOT,smlng\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,cladmi\/RIOT,kbumsik\/RIOT,jasonatran\/RIOT,josephnoir\/RIOT,mtausig\/RIOT,biboc\/RIOT,x3ro\/RIOT,smlng\/RIOT,RIOT-OS\/RIOT,cladmi\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,cladmi\/RIOT,rfuentess\/RIOT,x3ro\/RIOT,gebart\/RIOT,mfrey\/RIOT,jasonatran\/RIOT,A-Paul\/RIOT,kYc0o\/RIOT,avmelnikoff\/RIOT,josephnoir\/RIOT,lazytech-org\/RIOT,avmelnikoff\/RIOT,ant9000\/RIOT,A-Paul\/RIOT,miri64\/RIOT,basilfx\/RIOT,BytesGalore\/RIOT,authmillenon\/RIOT,gebart\/RIOT,OTAkeys\/RIOT,kaspar030\/RIOT,x3ro\/RIOT,kaspar030\/RIOT,miri64\/RIOT,gebart\/RIOT,yogo1212\/RIOT,avmelnikoff\/RIOT,neiljay\/RIOT,smlng\/RIOT,ant9000\/RIOT,josephnoir\/RIOT,aeneby\/RIOT,basilfx\/RIOT,kbumsik\/RIOT,mtausig\/RIOT,mfrey\/RIOT,mfrey\/RIOT,OlegHahm\/RIOT,OTAkeys\/RIOT,mfrey\/RIOT,basilfx\/RIOT,BytesGalore\/RIOT,toonst\/RIOT,biboc\/RIOT,OTAkeys\/RIOT,toonst\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,authmillenon\/RIOT,lazytech-org\/RIOT,neiljay\/RIOT,biboc\/RIOT,A-Paul\/RIOT,aeneby\/RIOT,A-Paul\/RIOT,lazytech-org\/RIOT,basilfx\/RIOT,A-Paul\/RIOT,OTAkeys\/RIOT,lazytech-org\/RIOT,kYc0o\/RIOT,BytesGalore\/RIOT,cladmi\/RIOT,miri64\/RIOT,kaspar030\/RIOT,avmelnikoff\/RIOT,authmillenon\/RIOT,avmelnikoff\/RIOT,kbumsik\/RIOT,OlegHahm\/RIOT,BytesGalore\/RIOT,smlng\/RIOT,gebart\/RIOT,toonst\/RIOT,ant9000\/RIOT,rfuentess\/RIOT,kbumsik\/RIOT,ant9000\/RIOT,aeneby\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,x3ro\/RIOT,neiljay\/RIOT,toonst\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT","old_file":"cpu\/cc26x0\/ldscripts\/cc26x0f128.ld","new_file":"cpu\/cc26x0\/ldscripts\/cc26x0f128.ld","new_contents":"\/**\n * @addtogroup      cpu_cc26x0\n * @{\n *\n * @file\n * @brief           linker script for cc26x0f128 MCUs\n *\n * @}\n *\/\n\n\/* Memory Space Definitions: *\/\nMEMORY\n{\n    rom (rx)   : ORIGIN = 0x00000000, LENGTH = 0x00020000 - 88 \/* technically, it's 128K *\/\n    gpram      : ORIGIN = 0x11000000, LENGTH = 8K \/* configurable as cache. 20K here, 8K there, and 2K in the ld-script of cc26x0ware *\/\n    ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 20K \/* sram *\/\n}\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/**\n * @addtogroup      cpu_cc26x0\n * @{\n *\n * @file\n * @brief           linker script for cc26x0f128 MCUs\n *\n * @}\n *\/\n\n\/* Memory Space Definitions: *\/\nMEMORY\n{\n    rom  (rx ) : ORIGIN = 0x00000000, LENGTH = 0x00020000 - 88 \/* technically, it's 128K *\/\n    gpram  (rwx) : ORIGIN = 0x11000000, LENGTH = 8K \/* configurable as cache. 20K here, 8K there, and 2K in the ld-script of cc26x0ware *\/\n    ram    (rwx) : ORIGIN = 0x20000000, LENGTH = 20K \/* sram *\/\n}\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"55bbac8e523a8ea2a874d7d3d6f50cccea70ad04","subject":"Detab linker.ld","message":"Detab linker.ld\n","repos":"olsner\/verdigris,olsner\/verdigris,olsner\/verdigris","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(start32_mboot)\nOUTPUT_FORMAT(binary)\n\nhigh_org = 0xffffffffc0000000;\n\nMEMORY {\n    ram : org = 0x100000, l = 12K\n    high : org = 0xffffffffc0100000, l = 12K\n}\n\nSECTIONS {\n    . = 0x100000;\n\n    .text32 : {\n        start32.o(.text*);\n    } >ram AT>ram\n\n    .text64 (. + high_org) : {\n        *(.text*);\n    } >high AT>ram\n\n    .data32 (. - high_org) : {\n        start32.o(.data*);\n        start32.o(.rodata*);\n    } >ram AT>ram\n\n    .data64 (. + high_org) : {\n        *(.rodata*);\n        *(.data*);\n        PROVIDE(section.data.end = . - 0xffffffffc0000000);\n    } >high AT>ram\n\n    .bss32 (. - high_org) : {\n        start32.o(.bss*);\n    } >ram AT>ram\n\n    .bss64 (. + high_org) : {\n        *(.bss*);\n    } >high AT>ram\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.eh_frame)\n        *(.rel.eh_frame)\n    }\n}\n","old_contents":"ENTRY(start32_mboot)\nOUTPUT_FORMAT(binary)\n\nhigh_org = 0xffffffffc0000000;\n\nMEMORY {\n\tram : org = 0x100000, l = 12K\n\thigh : org = 0xffffffffc0100000, l = 12K\n}\n\nSECTIONS {\n    . = 0x100000;\n\n    .text32 : {\n\t\tstart32.o(.text*);\n\t} >ram AT>ram\n\n\t.text64 (. + high_org) : {\n        *(.text*);\n\t} >high AT>ram\n\n\t.data32 (. - high_org) : {\n\t\tstart32.o(.data*);\n\t\tstart32.o(.rodata*);\n\t} >ram AT>ram\n\n\t.data64 (. + high_org) : {\n\t\t*(.rodata*);\n\t\t*(.data*);\n\t\tPROVIDE(section.data.end = . - 0xffffffffc0000000);\n\t} >high AT>ram\n\n\t.bss32 (. - high_org) : {\n\t\tstart32.o(.bss*);\n\t} >ram AT>ram\n\n\t.bss64 (. + high_org) : {\n\t\t*(.bss*);\n\t} >high AT>ram\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.eh_frame)\n        *(.rel.eh_frame)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"56cea857f94bf8a841466a98172c6026b693135c","subject":"fix compile regression after folder position change","message":"fix compile regression after folder position change\n","repos":"luetgendorf\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,lancernet\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,lancernet\/Espruino,lancernet\/Espruino,wilberforce\/Espruino,wilberforce\/Espruino,lancernet\/Espruino","old_file":"targetlibs\/nrf5x\/nrf5x_linkers\/secure_dfu_gcc_nrf52.ld","new_file":"targetlibs\/nrf5x\/nrf5x_linkers\/secure_dfu_gcc_nrf52.ld","new_contents":"\/* Linker script to configure memory regions. *\/\r\n\r\nSEARCH_DIR(.)\r\nGROUP(-lgcc -lc -lnosys)\r\n\r\nMEMORY\r\n{\r\n  \/** Flash start address for the bootloader. This setting will also be stored in UICR to allow the\r\n   *  MBR to init the bootloader when starting the system. This value must correspond to\r\n   *  BOOTLOADER_REGION_START found in dfu_types.h. The system is prevented from starting up if\r\n   *  those values do not match. The check is performed in main.c, see\r\n   *  APP_ERROR_CHECK_BOOL(*((uint32_t *)NRF_UICR_BOOT_START_ADDRESS) == BOOTLOADER_REGION_START);\r\n   *\/\r\n  FLASH (rx) : ORIGIN = 0x78000, LENGTH = 0x6000\r\n\r\n  \/** RAM Region for bootloader. This setting is suitable when used with s132. *\/\r\n  RAM (rwx) :  ORIGIN = 0x20002C00, LENGTH = 0x5380\r\n\r\n  \/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n   *  from application to bootloader when using buttonluss DFU OTA.\r\n   *\/\r\n  NOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n  \/** Location of bootloader setting in flash. *\/\r\n  BOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n\r\n  \/** Location in UICR where bootloader start address is stored. *\/\r\n  UICR_BOOTLOADER (r) : ORIGIN = 0x10001014, LENGTH = 0x04\r\n\r\n  \/** Location of mbr params page in flash. *\/\r\n  MBR_PARAMS_PAGE (rw) : ORIGIN = 0x0007E000, LENGTH = 0x1000\r\n\r\n  \/** Location in UICR where mbr params page address is stored. *\/\r\n  UICR_MBR_PARAM_PAGE(r) : ORIGIN = 0x10001018, LENGTH = 0x04\r\n}\r\n\r\nSECTIONS\r\n{\r\n  \/* Place the bootloader settings page in flash. *\/\r\n  .bootloaderSettings(NOLOAD) :\r\n  {\r\n\r\n  } > BOOTLOADER_SETTINGS\r\n\r\n  \/* Write the bootloader address in UICR. *\/\r\n  .uicrBootStartAddress :\r\n  {\r\n    KEEP(*(.uicrBootStartAddress))\r\n  } > UICR_BOOTLOADER\r\n\r\n  \/* Place the mbr params page in flash. *\/\r\n    .mbrParamsPage(NOLOAD) :\r\n  {\r\n\r\n  } > MBR_PARAMS_PAGE\r\n\r\n  \/* Write the bootloader address in UICR. *\/\r\n  .uicrMbrParamsPageAddress :\r\n  {\r\n    KEEP(*(.uicrMbrParamsPageAddress))\r\n  } > UICR_MBR_PARAM_PAGE\r\n\r\n  \/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n  .noinit(NOLOAD) :\r\n  {\r\n\r\n  } > NOINIT\r\n  \/* other placements follow here... *\/\r\n}\r\n\r\nSECTIONS\r\n{\r\n  . = ALIGN(4);\r\n  .fs_data :\r\n  {\r\n    PROVIDE(__start_fs_data = .);\r\n    KEEP(*(.fs_data))\r\n    PROVIDE(__stop_fs_data = .);\r\n  } > RAM\r\n\r\n  . = ALIGN(4);\r\n  .svc_data :\r\n  {\r\n    PROVIDE(__start_svc_data = .);\r\n    KEEP(*(.svc_data))\r\n    PROVIDE(__stop_svc_data = .);\r\n  } > RAM\r\n\r\n  . = ALIGN(4);\r\n  .dfu_trans :\r\n  {\r\n    PROVIDE(__start_dfu_trans = .);\r\n    KEEP(*(.dfu_trans))\r\n    PROVIDE(__stop_dfu_trans = .);\r\n  } > RAM\r\n\r\n} INSERT AFTER .data\r\n\r\nINCLUDE \"..\/components\/toolchain\/gcc\/nrf52_common.ld\"\r\n","old_contents":"\/* Linker script to configure memory regions. *\/\r\n\r\nSEARCH_DIR(.)\r\nGROUP(-lgcc -lc -lnosys)\r\n\r\nMEMORY\r\n{\r\n  \/** Flash start address for the bootloader. This setting will also be stored in UICR to allow the\r\n   *  MBR to init the bootloader when starting the system. This value must correspond to\r\n   *  BOOTLOADER_REGION_START found in dfu_types.h. The system is prevented from starting up if\r\n   *  those values do not match. The check is performed in main.c, see\r\n   *  APP_ERROR_CHECK_BOOL(*((uint32_t *)NRF_UICR_BOOT_START_ADDRESS) == BOOTLOADER_REGION_START);\r\n   *\/\r\n  FLASH (rx) : ORIGIN = 0x78000, LENGTH = 0x6000\r\n\r\n  \/** RAM Region for bootloader. This setting is suitable when used with s132. *\/\r\n  RAM (rwx) :  ORIGIN = 0x20002C00, LENGTH = 0x5380\r\n\r\n  \/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n   *  from application to bootloader when using buttonluss DFU OTA.\r\n   *\/\r\n  NOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n  \/** Location of bootloader setting in flash. *\/\r\n  BOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n\r\n  \/** Location in UICR where bootloader start address is stored. *\/\r\n  UICR_BOOTLOADER (r) : ORIGIN = 0x10001014, LENGTH = 0x04\r\n\r\n  \/** Location of mbr params page in flash. *\/\r\n  MBR_PARAMS_PAGE (rw) : ORIGIN = 0x0007E000, LENGTH = 0x1000\r\n\r\n  \/** Location in UICR where mbr params page address is stored. *\/\r\n  UICR_MBR_PARAM_PAGE(r) : ORIGIN = 0x10001018, LENGTH = 0x04\r\n}\r\n\r\nSECTIONS\r\n{\r\n  \/* Place the bootloader settings page in flash. *\/\r\n  .bootloaderSettings(NOLOAD) :\r\n  {\r\n\r\n  } > BOOTLOADER_SETTINGS\r\n\r\n  \/* Write the bootloader address in UICR. *\/\r\n  .uicrBootStartAddress :\r\n  {\r\n    KEEP(*(.uicrBootStartAddress))\r\n  } > UICR_BOOTLOADER\r\n\r\n  \/* Place the mbr params page in flash. *\/\r\n    .mbrParamsPage(NOLOAD) :\r\n  {\r\n\r\n  } > MBR_PARAMS_PAGE\r\n\r\n  \/* Write the bootloader address in UICR. *\/\r\n  .uicrMbrParamsPageAddress :\r\n  {\r\n    KEEP(*(.uicrMbrParamsPageAddress))\r\n  } > UICR_MBR_PARAM_PAGE\r\n\r\n  \/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n  .noinit(NOLOAD) :\r\n  {\r\n\r\n  } > NOINIT\r\n  \/* other placements follow here... *\/\r\n}\r\n\r\nSECTIONS\r\n{\r\n  . = ALIGN(4);\r\n  .fs_data :\r\n  {\r\n    PROVIDE(__start_fs_data = .);\r\n    KEEP(*(.fs_data))\r\n    PROVIDE(__stop_fs_data = .);\r\n  } > RAM\r\n\r\n  . = ALIGN(4);\r\n  .svc_data :\r\n  {\r\n    PROVIDE(__start_svc_data = .);\r\n    KEEP(*(.svc_data))\r\n    PROVIDE(__stop_svc_data = .);\r\n  } > RAM\r\n\r\n  . = ALIGN(4);\r\n  .dfu_trans :\r\n  {\r\n    PROVIDE(__start_dfu_trans = .);\r\n    KEEP(*(.dfu_trans))\r\n    PROVIDE(__stop_dfu_trans = .);\r\n  } > RAM\r\n\r\n} INSERT AFTER .data\r\n\r\nINCLUDE \"..\/nrf5_sdk\/components\/toolchain\/gcc\/nrf52_common.ld\"\r\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"cb665ee7665c4d123a0242c2a2918ba790dd877b","subject":"Use linker script from latest tock version","message":"Use linker script from latest tock version\n","repos":"tock\/libtock-rs","old_file":"layout.ld","new_file":"layout.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\nSTACK_SIZE = 2048;\nAPP_HEAP_SIZE = 1024;\nKERNEL_HEAP_SIZE = 1024;\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _text);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _text);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tbf places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endsec) - _text);\n\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n\n\/* App state section. Used for persistent app data. *\/\n    .app_state :\n    {\n        KEEP (*(.app_state))\n    } > FLASH =0xFF\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n    } > SRAM\n\n\/*\n     * __NOTE__: The following symbols are used only to hint to elf2tbf how much\n     * total memory to request from the OS.\n *\/\n    .stack :\n    {\n        . += STACK_SIZE;\n    } > SRAM\n\n    .app_heap :\n    {\n        . += APP_HEAP_SIZE;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        . += KERNEL_HEAP_SIZE;\n    } > SRAM\n\n    _sram_end = .;\n    .endsec :\n    {\n    } > FLASH\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        KEEP (*(.text._start))\n        *(.text*)\n        *(.rodata*)\n\n        \/* C++ exception unwinding information *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH =0xFF\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += 1024;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += 1024;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += 1024;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ce57d0dd01386c633a02d2b11df0f7b326a81e8e","subject":"","message":"\n\ngit-svn-id: https:\/\/chibios.svn.sourceforge.net\/svnroot\/chibios\/trunk@5050 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"os\/ports\/GCC\/ARMCMx\/STM32F4xx\/ld\/STM32F407xG_CCM.ld","new_file":"os\/ports\/GCC\/ARMCMx\/STM32F4xx\/ld\/STM32F407xG_CCM.ld","new_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011,2012 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * ST32F407xG memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0400;\r\n__process_stack_size__  = 0x0400;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x08000000, len = 1M\r\n    ram : org = 0x20000000, len = 112k\r\n    ethram : org = 0x2001C000, len = 16k\r\n    ccmram : org = 0x10000000, len = 64k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n    . = 0;\r\n    _text = .;\r\n\r\n    startup : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        KEEP(*(vectors))\r\n    } > flash\r\n\r\n    constructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE(__init_array_end = .);\r\n    } > flash\r\n\r\n    destructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__fini_array_start = .);\r\n        KEEP(*(.fini_array))\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        PROVIDE(__fini_array_end = .);\r\n    } > flash\r\n\r\n    .text : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        *(.text.startup.*)\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n    } > flash\r\n\r\n    .ARM.extab :\r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > flash\r\n\r\n    .ARM.exidx : {\r\n        PROVIDE(__exidx_start = .);\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n        PROVIDE(__exidx_end = .);\r\n     } > flash\r\n\r\n    .eh_frame_hdr :\r\n    {\r\n        *(.eh_frame_hdr)\r\n    } > flash\r\n\r\n    .eh_frame : ONLY_IF_RO\r\n    {\r\n        *(.eh_frame)\r\n    } > flash\r\n    \r\n    .textalign : ONLY_IF_RO\r\n    {\r\n        . = ALIGN(8);\r\n    } > flash\r\n\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .stacks :\r\n    {\r\n        . = ALIGN(8);\r\n        __main_stack_base__ = .;\r\n        . += __main_stack_size__;\r\n        . = ALIGN(8);\r\n        __main_stack_end__ = .;\r\n        __process_stack_base__ = .;\r\n        __main_thread_stack_base__ = .;\r\n        . += __process_stack_size__;\r\n        . = ALIGN(8);\r\n        __process_stack_end__ = .;\r\n        __main_thread_stack_end__ = .;\r\n    } > ccmram\r\n\r\n    .ccm :\r\n    {\r\n        PROVIDE(_cmm_start = .);\r\n        . = ALIGN(4);\r\n        *(.bss.mainthread.*)\r\n        . = ALIGN(4);\r\n        *(.bss._idle_thread_wa)\r\n        . = ALIGN(4);\r\n        *(.bss.rlist)\r\n        . = ALIGN(4);\r\n        *(.bss.vtlist)\r\n        . = ALIGN(4);\r\n        *(.bss.endmem)\r\n        . = ALIGN(4);\r\n        *(.bss.nextmem)\r\n        . = ALIGN(4);\r\n        *(.bss.default_heap)\r\n        . = ALIGN(4);\r\n        PROVIDE(_cmm_end = .);\r\n    } > ccmram\r\n\r\n    .data :\r\n    {\r\n        . = ALIGN(4);\r\n        PROVIDE(_data = .);\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        PROVIDE(_edata = .);\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        . = ALIGN(4);\r\n        PROVIDE(_bss_start = .);\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        PROVIDE(_bss_end = .);\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__;\r\n","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011,2012 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * ST32F407xG memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0400;\r\n__process_stack_size__  = 0x0400;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x08000000, len = 1M\r\n    ram : org = 0x20000000, len = 112k\r\n    ethram : org = 0x2001C000, len = 16k\r\n    ccmram : org = 0x10000000, len = 64k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n    . = 0;\r\n    _text = .;\r\n\r\n    startup : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        KEEP(*(vectors))\r\n    } > flash\r\n\r\n    constructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE(__init_array_end = .);\r\n    } > flash\r\n\r\n    destructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__fini_array_start = .);\r\n        KEEP(*(.fini_array))\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        PROVIDE(__fini_array_end = .);\r\n    } > flash\r\n\r\n    .text : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        *(.text.startup.*)\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n    } > flash\r\n\r\n    .ARM.extab :\r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > flash\r\n\r\n    .ARM.exidx : {\r\n        PROVIDE(__exidx_start = .);\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n        PROVIDE(__exidx_end = .);\r\n     } > flash\r\n\r\n    .eh_frame_hdr :\r\n    {\r\n        *(.eh_frame_hdr)\r\n    } > flash\r\n\r\n    .eh_frame : ONLY_IF_RO\r\n    {\r\n        *(.eh_frame)\r\n    } > flash\r\n    \r\n    .textalign : ONLY_IF_RO\r\n    {\r\n        . = ALIGN(8);\r\n    } > flash\r\n\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .stacks :\r\n    {\r\n        . = ALIGN(8);\r\n        __main_stack_base__ = .;\r\n        . += __main_stack_size__;\r\n        . = ALIGN(8);\r\n        __main_stack_end__ = .;\r\n        __process_stack_base__ = .;\r\n        __main_thread_stack_base__ = .;\r\n        . += __process_stack_size__;\r\n        . = ALIGN(8);\r\n        __process_stack_end__ = .;\r\n        __main_thread_stack_end__ = .;\r\n    } > ccmram\r\n\r\n    .ccm :\r\n    {\r\n        PROVIDE(_cmm_start = .);\r\n        . = ALIGN(4);\r\n        *(.bss.mainthread.*)\r\n        . = ALIGN(4);\r\n        *(.bss._idle_thread_wa)\r\n        . = ALIGN(4);\r\n        *(.bss.rlist)\r\n        . = ALIGN(4);\r\n        *(.bss.vtlist)\r\n        . = ALIGN(4);\r\n        *(.bss.endmem)\r\n        . = ALIGN(4);\r\n        *(.bss.nextmem)\r\n        . = ALIGN(4);\r\n        *(.bss.default_heap)\r\n        . = ALIGN(4);\r\n        PROVIDE(_cmmend = .);\r\n    } > ccmram\r\n\r\n    .data :\r\n    {\r\n        . = ALIGN(4);\r\n        PROVIDE(_data = .);\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        PROVIDE(_edata = .);\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        . = ALIGN(4);\r\n        PROVIDE(_bss_start = .);\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        PROVIDE(_bss_end = .);\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__;\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9e75a1a8724358c53087710e9f31f528178f0832","subject":"linker: add .note.GNU-stack to arc linker","message":"linker: add .note.GNU-stack to arc linker\n\nWhen building for ARC this new section appears with gcc 8.2.\n\nSigned-off-by: Anas Nashif <0d9952ec84ac43c159f6b7e7ed99a9080c00dd6e@intel.com>\n","repos":"Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,explora26\/zephyr,ldts\/zephyr,explora26\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,ldts\/zephyr,finikorg\/zephyr,explora26\/zephyr,ldts\/zephyr,Vudentz\/zephyr,explora26\/zephyr,explora26\/zephyr,nashif\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/arc\/v2\/linker.ld","new_file":"include\/arch\/arc\/v2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <linker\/sections.h>\n\n#if defined(CONFIG_UART_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_HARVARD\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)\n\t\t#define ROMABLE_REGION FLASH\n\t\t#define RAMABLE_REGION SRAM\n\t#else\n\t\t#define ROMABLE_REGION SRAM\n\t\t#define RAMABLE_REGION SRAM\n\t#endif\n#endif\n\n#ifdef CONFIG_ARC_MPU_ENABLE\n\t#if CONFIG_ARC_MPU_VER == 2\n\t\t#define MPU_MIN_SIZE 2048\n\t#elif CONFIG_ARC_MPU_VER == 3\n\t\t#define MPU_MIN_SIZE 32\n\t#endif\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(CONFIG_KERNEL_ENTRY)\n\nMEMORY {\n#ifdef FLASH_START\n\tFLASH (rx)  : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n#endif\n#ifdef ICCM_START\n\tICCM  (rwx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n#endif\n#ifdef SRAM_START\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n#endif\n#ifdef DCCM_START\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n#endif\n\t\/* Used by and documented in include\/linker\/intlist.ld *\/\n\tIDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nSECTIONS {\n\n#include <linker\/rel-sections.ld>\n\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\t\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\tKEEP(*(.openocd_dbg))\n\t\tKEEP(*(\".openocd_dbg.*\"))\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMPU_MIN_SIZE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t_app_smem_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n#include <app_data_alignment.ld>\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t\tMPU_MIN_SIZE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\n#ifndef CONFIG_APPLICATION_MEMORY\n\t\t_image_ram_start = .;\n#endif\n\t\t__kernel_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.bss)\n\t\tKERNEL_INPUT_SECTION(\".bss.*\")\n\t\tKERNEL_INPUT_SECTION(COMMON)\n\t\t*(\".kernel_bss.*\")\n\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t KERNEL_INPUT_SECTION(.noinit)\n\t\t KERNEL_INPUT_SECTION(\".noinit.*\")\n\t\t *(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\t\t__data_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.data)\n\t\tKERNEL_INPUT_SECTION(\".data.*\")\n\t\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n\t__data_ram_end = .;\n\n\tMPU_MIN_SIZE_ALIGN\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n\n    SECTION_PROLOGUE(.ARC.attributes, 0,)\n\t{\n\tKEEP(*(.ARC.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\t}\n","old_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <linker\/sections.h>\n\n#if defined(CONFIG_UART_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_HARVARD\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)\n\t\t#define ROMABLE_REGION FLASH\n\t\t#define RAMABLE_REGION SRAM\n\t#else\n\t\t#define ROMABLE_REGION SRAM\n\t\t#define RAMABLE_REGION SRAM\n\t#endif\n#endif\n\n#ifdef CONFIG_ARC_MPU_ENABLE\n\t#if CONFIG_ARC_MPU_VER == 2\n\t\t#define MPU_MIN_SIZE 2048\n\t#elif CONFIG_ARC_MPU_VER == 3\n\t\t#define MPU_MIN_SIZE 32\n\t#endif\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(CONFIG_KERNEL_ENTRY)\n\nMEMORY {\n#ifdef FLASH_START\n\tFLASH (rx)  : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n#endif\n#ifdef ICCM_START\n\tICCM  (rwx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n#endif\n#ifdef SRAM_START\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n#endif\n#ifdef DCCM_START\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n#endif\n\t\/* Used by and documented in include\/linker\/intlist.ld *\/\n\tIDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nSECTIONS {\n\n#include <linker\/rel-sections.ld>\n\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\t\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\tKEEP(*(.openocd_dbg))\n\t\tKEEP(*(\".openocd_dbg.*\"))\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMPU_MIN_SIZE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t_app_smem_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n#include <app_data_alignment.ld>\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t\tMPU_MIN_SIZE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\n#ifndef CONFIG_APPLICATION_MEMORY\n\t\t_image_ram_start = .;\n#endif\n\t\t__kernel_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.bss)\n\t\tKERNEL_INPUT_SECTION(\".bss.*\")\n\t\tKERNEL_INPUT_SECTION(COMMON)\n\t\t*(\".kernel_bss.*\")\n\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t KERNEL_INPUT_SECTION(.noinit)\n\t\t KERNEL_INPUT_SECTION(\".noinit.*\")\n\t\t *(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\t\t__data_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.data)\n\t\tKERNEL_INPUT_SECTION(\".data.*\")\n\t\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n\t__data_ram_end = .;\n\n\tMPU_MIN_SIZE_ALIGN\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n\n    SECTION_PROLOGUE(.ARC.attributes, 0,)\n\t{\n\tKEEP(*(.ARC.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\t}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"321c8202d208fa89c78709bec61031856cd487c9","subject":"linker: Fixup warning associated with .ARC.attributes section","message":"linker: Fixup warning associated with .ARC.attributes section\n\nWith newer linker for ARC we can possibly get a warning like:\n\n   real-ld: warning: orphan section `.ARC.attributes' from `(foo.o)'\n   being placed in section `.ARC.attributes'.\n\nFixes #11060\n\nSigned-off-by: Kumar Gala <a5e5248af4cd4f0ed8c515f61d40a6e2db46a66e@linaro.org>\n","repos":"punitvara\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,ldts\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,punitvara\/zephyr,punitvara\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,ldts\/zephyr,galak\/zephyr,ldts\/zephyr,explora26\/zephyr,galak\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,galak\/zephyr,nashif\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,explora26\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr","old_file":"include\/arch\/arc\/v2\/linker.ld","new_file":"include\/arch\/arc\/v2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#if defined(CONFIG_UART_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_HARVARD\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)\n\t\t#define ROMABLE_REGION FLASH\n\t\t#define RAMABLE_REGION SRAM\n\t#else\n\t\t#define ROMABLE_REGION SRAM\n\t\t#define RAMABLE_REGION SRAM\n\t#endif\n#endif\n\n#ifdef CONFIG_ARC_MPU_ENABLE\n\t#if CONFIG_ARC_MPU_VER == 2\n\t\t#define MPU_MIN_SIZE 2048\n\t#elif CONFIG_ARC_MPU_VER == 3\n\t\t#define MPU_MIN_SIZE 32\n\t#endif\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(CONFIG_KERNEL_ENTRY)\n\nMEMORY {\n#ifdef FLASH_START\n\tFLASH (rx)  : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n#endif\n#ifdef ICCM_START\n\tICCM  (rwx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n#endif\n#ifdef SRAM_START\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n#endif\n#ifdef DCCM_START\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n#endif\n\t\/* Used by and documented in include\/linker\/intlist.ld *\/\n\tIDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nSECTIONS {\n\n#include <linker\/rel-sections.ld>\n\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\t\tKEEP(*(IRQ_VECTOR_TABLE))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\t\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\tKEEP(*(.openocd_dbg))\n\t\tKEEP(*(\".openocd_dbg.*\"))\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMPU_MIN_SIZE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t_app_smem_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n#include <app_data_alignment.ld>\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t\tMPU_MIN_SIZE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\n#ifndef CONFIG_APPLICATION_MEMORY\n\t\t_image_ram_start = .;\n#endif\n\t\t__kernel_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.bss)\n\t\tKERNEL_INPUT_SECTION(\".bss.*\")\n\t\tKERNEL_INPUT_SECTION(COMMON)\n\t\t*(\".kernel_bss.*\")\n\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t KERNEL_INPUT_SECTION(.noinit)\n\t\t KERNEL_INPUT_SECTION(\".noinit.*\")\n\t\t *(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\t\t__data_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.data)\n\t\tKERNEL_INPUT_SECTION(\".data.*\")\n\t\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n\t__data_ram_end = .;\n\n\tMPU_MIN_SIZE_ALIGN\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n\n    SECTION_PROLOGUE(.ARC.attributes, 0,)\n\t{\n\tKEEP(*(.ARC.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\t}\n","old_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#if defined(CONFIG_UART_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_HARVARD\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)\n\t\t#define ROMABLE_REGION FLASH\n\t\t#define RAMABLE_REGION SRAM\n\t#else\n\t\t#define ROMABLE_REGION SRAM\n\t\t#define RAMABLE_REGION SRAM\n\t#endif\n#endif\n\n#ifdef CONFIG_ARC_MPU_ENABLE\n\t#if CONFIG_ARC_MPU_VER == 2\n\t\t#define MPU_MIN_SIZE 2048\n\t#elif CONFIG_ARC_MPU_VER == 3\n\t\t#define MPU_MIN_SIZE 32\n\t#endif\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(CONFIG_KERNEL_ENTRY)\n\nMEMORY {\n#ifdef FLASH_START\n\tFLASH (rx)  : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n#endif\n#ifdef ICCM_START\n\tICCM  (rwx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n#endif\n#ifdef SRAM_START\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n#endif\n#ifdef DCCM_START\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n#endif\n\t\/* Used by and documented in include\/linker\/intlist.ld *\/\n\tIDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nSECTIONS {\n\n#include <linker\/rel-sections.ld>\n\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\t\tKEEP(*(IRQ_VECTOR_TABLE))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\t\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\tKEEP(*(.openocd_dbg))\n\t\tKEEP(*(\".openocd_dbg.*\"))\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMPU_MIN_SIZE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t_app_smem_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n#include <app_data_alignment.ld>\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t\tMPU_MIN_SIZE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\n#ifndef CONFIG_APPLICATION_MEMORY\n\t\t_image_ram_start = .;\n#endif\n\t\t__kernel_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.bss)\n\t\tKERNEL_INPUT_SECTION(\".bss.*\")\n\t\tKERNEL_INPUT_SECTION(COMMON)\n\t\t*(\".kernel_bss.*\")\n\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t KERNEL_INPUT_SECTION(.noinit)\n\t\t KERNEL_INPUT_SECTION(\".noinit.*\")\n\t\t *(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\t\t__data_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.data)\n\t\tKERNEL_INPUT_SECTION(\".data.*\")\n\t\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n\t__data_ram_end = .;\n\n\tMPU_MIN_SIZE_ALIGN\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n\t}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"023411f396a342178cce45f662a3a38d3a870475","subject":"keep the original common linker because it has defined symbols and no changes introduced here","message":"keep the original common linker because it has defined symbols and no changes introduced here\n","repos":"mjdietzx\/Espruino,luetgendorf\/Espruino,mjdietzx\/Espruino,nkolban\/Espruino,nkolban\/Espruino,nkolban\/Espruino,nkolban\/Espruino,wilberforce\/Espruino,lancernet\/Espruino,muet\/Espruino,tve\/Espruino,luetgendorf\/Espruino,redbear\/Espruino,tve\/Espruino,lancernet\/Espruino,muet\/Espruino,mjdietzx\/Espruino,redbear\/Espruino,tve\/Espruino,nkolban\/Espruino,lancernet\/Espruino,tve\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,wilberforce\/Espruino,nkolban\/Espruino,wilberforce\/Espruino,nkolban\/Espruino,muet\/Espruino,muet\/Espruino,tve\/Espruino,wilberforce\/Espruino,muet\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,mjdietzx\/Espruino,mjdietzx\/Espruino,luetgendorf\/Espruino,redbear\/Espruino,mjdietzx\/Espruino,redbear\/Espruino,mjdietzx\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,redbear\/Espruino,redbear\/Espruino,wilberforce\/Espruino,redbear\/Espruino,tve\/Espruino,tve\/Espruino,wilberforce\/Espruino,muet\/Espruino,wilberforce\/Espruino,lancernet\/Espruino,muet\/Espruino,luetgendorf\/Espruino","old_file":"targetlibs\/nrf5x\/nrf5x_linkers\/gcc_nrf5x_espruino_common.ld","new_file":"targetlibs\/nrf5x\/nrf5x_linkers\/gcc_nrf5x_espruino_common.ld","new_contents":"\/* Linker script for Nordic Semiconductor nRF5 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.Vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    \/* .ctors *\/\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    \/* .dtors *\/\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    *(.eh_frame*)\n    . = ALIGN(4);\n  } > FLASH\n    \n\n  .ARM.extab : \n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n    . = ALIGN(4);\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    . = ALIGN(4);\n  } > FLASH\n  __exidx_end = .;\n\n  __etext = .;\n  _etext = .;\n  _sidata = .;\n    \n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    _sdata = .;\n    *(vtable)\n    *(.data*)\n\n    . = ALIGN(4);\n    \/* preinit data *\/\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    *(.preinit_array)\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    \/* init data *\/\n    PROVIDE_HIDDEN (__init_array_start = .);\n    *(SORT(.init_array.*))\n    *(.init_array)\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n\n    . = ALIGN(4);\n    \/* finit data *\/\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    *(SORT(.fini_array.*))\n    *(.fini_array)\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    *(.jcr)\n    . = ALIGN(4);\n    \/* All data end *\/\n    __data_end__ = .;\n    _edata = .;\n\n  } > RAM\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    _sbss = .;\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    _ebss = .;\n  } > RAM\n  \n  .heap (COPY):\n  {\n    __end__ = .;\n    end = __end__;\n    *(.heap*)\n    __HeapLimit = .;\n  } > RAM\n\n  PROVIDE ( _end = end );\n\n  \/* .stack_dummy section doesn't contains any symbols. It is only\n   * used for linker to calculate size of stack sections, and assign\n   * values to stack symbols later *\/\n  .stack_dummy (COPY):\n  {\n    *(.stack*)\n  } > RAM\n\n  \/* Set stack top to end of RAM, and stack limit move down by\n   * size of stack_dummy section *\/\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n  _estack = __StackTop;\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n  PROVIDE(__stack = __StackTop);\n  \n  \/* Check if data + heap + stack exceeds RAM limit *\/\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for Nordic Semiconductor nRF5 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.Vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    \/* .ctors *\/\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    \/* .dtors *\/\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    *(.eh_frame*)\n    . = ALIGN(4);\n  } > FLASH\n    \n\n  .ARM.extab : \n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n    . = ALIGN(4);\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    . = ALIGN(4);\n  } > FLASH\n  __exidx_end = .;\n\n  __etext = .;\n    \n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data*)\n\n    . = ALIGN(4);\n    \/* preinit data *\/\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    *(.preinit_array)\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    \/* init data *\/\n    PROVIDE_HIDDEN (__init_array_start = .);\n    *(SORT(.init_array.*))\n    *(.init_array)\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n\n    . = ALIGN(4);\n    \/* finit data *\/\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    *(SORT(.fini_array.*))\n    *(.fini_array)\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    *(.jcr)\n    . = ALIGN(4);\n    \/* All data end *\/\n    __data_end__ = .;\n\n  } > RAM\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM\n  \n  .heap (COPY):\n  {\n    __end__ = .;\n    end = __end__;\n    *(.heap*)\n    __HeapLimit = .;\n  } > RAM\n\n  \/* .stack_dummy section doesn't contains any symbols. It is only\n   * used for linker to calculate size of stack sections, and assign\n   * values to stack symbols later *\/\n  .stack_dummy (COPY):\n  {\n    *(.stack*)\n  } > RAM\n\n  \/* Set stack top to end of RAM, and stack limit move down by\n   * size of stack_dummy section *\/\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n  PROVIDE(__stack = __StackTop);\n  \n  \/* Check if data + heap + stack exceeds RAM limit *\/\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"be254d4125c24805cba06e6e7cbe7dbb3acc0a69","subject":"cpu\/cc2538: adjust rom size to account for cca region","message":"cpu\/cc2538: adjust rom size to account for cca region\n","repos":"OlegHahm\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,kYc0o\/RIOT,kYc0o\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,miri64\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,ant9000\/RIOT,miri64\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT","old_file":"cpu\/cc2538\/ldscripts\/cc2538.ld","new_file":"cpu\/cc2538\/ldscripts\/cc2538.ld","new_contents":"\/*\n * Copyright (C) 2014 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_cc2538\n * @{\n *\n * @file\n * @brief           Linker script for the CC2538SF53\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n *\/\n\nINCLUDE cortexm_rom_offset.ld\n\n_cca_length = 44;\n\n\/* Memory Space Definitions: *\/\nMEMORY\n{\n    rom (rx)    : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _fw_rom_length - _cca_length\n    cca         : ORIGIN = 0x0027ffd4, LENGTH = _cca_length\n    sram0       : ORIGIN = 0x20000000, LENGTH = 16K \/* Lost in PM2 and PM3 *\/\n    sram1       : ORIGIN = 0x20004000, LENGTH = 16K\n    ram (w!rx)  : ORIGIN = _ram_start_addr, LENGTH = _ram_length\n}\n\n\/* MCU Specific Section Definitions *\/\nSECTIONS\n{\n    .flashcca :\n    {\n        KEEP(*(.flashcca))\n    } > cca\n}\n\nINCLUDE cortexm_base.ld\n\n\/* @} *\/\n","old_contents":"\/*\n * Copyright (C) 2014 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_cc2538\n * @{\n *\n * @file\n * @brief           Linker script for the CC2538SF53\n *\n * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>\n *\/\n\nINCLUDE cortexm_rom_offset.ld\n\n\/* Memory Space Definitions: *\/\nMEMORY\n{\n    rom (rx)    : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _fw_rom_length\n    cca         : ORIGIN = 0x0027ffd4, LENGTH = 44\n    sram0       : ORIGIN = 0x20000000, LENGTH = 16K \/* Lost in PM2 and PM3 *\/\n    sram1       : ORIGIN = 0x20004000, LENGTH = 16K\n    ram (w!rx)  : ORIGIN = _ram_start_addr, LENGTH = _ram_length\n}\n\n\/* MCU Specific Section Definitions *\/\nSECTIONS\n{\n    .flashcca :\n    {\n        KEEP(*(.flashcca))\n    } > cca\n}\n\nINCLUDE cortexm_base.ld\n\n\/* @} *\/\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"c064134caa0cbe7069ee388e5afa53649ed4e014","subject":"Linker now knows how not to make a giant mess","message":"Linker now knows how not to make a giant mess\n","repos":"rachlmac\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(start)\n\nSECTIONS {\n    . = 0xb8000;\n    vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .boot :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot))\n    }\n\n    .text :\n       {\n           *(.text .text.*)\n       }\n\n       .rodata : {\n           *(.rodata .rodata.*)\n       }\n\n       .data.rel.ro : {\n           *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n       }\n}\n","old_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(start)\n\nSECTIONS {\n    . = 0xb8000;\n    vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .boot :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot))\n    }\n\n    .text :\n    {\n        *(.text)\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"874d48e35de00369dddb64372eb971abb481c5ad","subject":"ld: higher stack alignment","message":"ld: higher stack alignment\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        _stack = .;\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        . = _stack + STACK_SIZE;\n        . = ALIGN(4);\n    } > SRAM\n\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n\t    \/* Include the \"small data\" in the data section. Otherwise it will be\n\t     * dropped when the TBF is created.\n\t     *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"21a9c413a0cffc987084e2af593dda216ad01f87","subject":"soc\/intel_adsp: Remove dead memory exception handler section","message":"soc\/intel_adsp: Remove dead memory exception handler section\n\nWe don't define a MemoryException handler, nor is one appropriate for\nthis hardware as it stands.  And the empty section keeps causing\nlinker warnings we have to work around.  Remove.\n\nSigned-off-by: Andy Ross <c70f9a6bf6ee0cd69c8af4ce5e6b131945769315@intel.com>\n","repos":"zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <cavs-vectors.h>\n#include <cavs-mem.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n * (Note clumsy syntax because XCC doesn't understand the \"~\" operator)\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & 0xdfffffff) \/* == ~0x20000000 *\/\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#define ucram_phdr ram_phdr\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int6_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int6_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.module_init)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n    *(.cached .cached.*)\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  \/* Heap start and end markers.  Mostly unused, though newlib likes them *\/\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <cavs-vectors.h>\n#include <cavs-mem.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n * (Note clumsy syntax because XCC doesn't understand the \"~\" operator)\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & 0xdfffffff) \/* == ~0x20000000 *\/\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#define ucram_phdr ram_phdr\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr\n\n .MemoryExceptionVector.literal : {\n    _MemoryExceptionVector_literal_start = .;\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = .;\n  } >vector_memory_lit\n  .MemoryExceptionVector.text : {\n    _MemoryExceptionVector_text_start = .;\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = .;\n  } >vector_memory_text\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int6_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int6_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.module_init)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n    *(.cached .cached.*)\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  \/* Heap start and end markers.  Mostly unused, though newlib likes them *\/\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5ebab0e8a2c7c5158b29c367557993465ada71f8","subject":"cleaned up init and fini data sections, removed pre-init section","message":"cleaned up init and fini data sections, removed pre-init section\n","repos":"joshfriend\/arm-project-template,joshfriend\/arm-project-template","old_file":"linker\/sections.ld","new_file":"linker\/sections.ld","new_contents":"\/*\n * Copyright (c) 2014 Josh Friend\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\/\n\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP(*(.nvic_table))\n        *(.text .text* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init.*)))\n        KEEP (*(.init))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        . = ALIGN(4);\n        _etext = .;\n    } > FLASH\n\n    .data : AT(ADDR(.text) + SIZEOF(.text))\n    {\n        . = ALIGN(4);\n        _data = .;\n        *(vtable)\n        *(.data .data* .gnu.linkonce.d.*)\n        _edata = .;\n    } > RAM\n\n    .bss (NOLOAD):\n    {\n        . = ALIGN(4);\n        _bss = .;\n        *(.bss .bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n        . = ALIGN(8);\n    } > RAM\n\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > RAM\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _end = . ;\n}\n\n\/* end of allocated ram is start of heap, heap grows up towards stack*\/\nPROVIDE(end = _end);\n\n\/* top of stack starts at end of ram, stack grows down towards heap *\/\nPROVIDE(_stack_top = ORIGIN(RAM) + LENGTH(RAM));\n","old_contents":"\/*\n * Copyright (c) 2014 Josh Friend\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\/\n\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP(*(.nvic_table))\n        *(.text .text* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(SORT(.preinit_array*)))\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        . = ALIGN(4);\n        _etext = .;\n    } > FLASH\n\n    .data : AT(ADDR(.text) + SIZEOF(.text))\n    {\n        . = ALIGN(4);\n        _data = .;\n        *(vtable)\n        *(.data .data* .gnu.linkonce.d.*)\n        _edata = .;\n    } > RAM\n\n    .bss (NOLOAD):\n    {\n        . = ALIGN(4);\n        _bss = .;\n        *(.bss .bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n        . = ALIGN(8);\n    } > RAM\n\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > RAM\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _end = . ;\n}\n\n\/* end of allocated ram is start of heap, heap grows up towards stack*\/\nPROVIDE(end = _end);\n\n\/* top of stack starts at end of ram, stack grows down towards heap *\/\nPROVIDE(_stack_top = ORIGIN(RAM) + LENGTH(RAM));\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4e9fbbe07604bc0e904bfd2563d9bfc3445bfea2","subject":"Added ARM exceptions to linker. Seems to be required to build with latest nightly.","message":"Added ARM exceptions to linker. Seems to be required to build with latest\nnightly.\n","repos":"thejpster\/kinetis-frdm,thejpster\/bare-metal-arm-rust,thejpster\/launchpad-rs,thejpster\/kinetis-frdm,thejpster\/bare-metal-arm-rust,thejpster\/launchpad-rs","old_file":"lm4f120.ld","new_file":"lm4f120.ld","new_contents":"\/*\n* Copyright (c) 2012, Mauro Scomparin\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*     * Redistributions of source code must retain the above copyright\n*       notice, this list of conditions and the following disclaimer.\n*     * Redistributions in binary form must reproduce the above copyright\n*       notice, this list of conditions and the following disclaimer in the\n*       documentation and\/or other materials provided with the distribution.\n*     * Neither the name of Mauro Scomparin nor the\n*       names of its contributors may be used to endorse or promote products\n*       derived from this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY Mauro Scomparin ``AS IS'' AND ANY\n* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL Mauro Scomparin BE LIABLE FOR ANY\n* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*\n* Author:   Mauro Scomparin <http:\/\/scompoprojects.wordpress.com>.\n* Author:   Jonathan Pallant <http:\/\/railwayelectronics.blogspot.com>.\n* Description:  Linker description file for LM4FXXX microcontrollers.\n*\/\n\n\/*\n* Memory definition:\n* FLASH:  start point 0x00,   lenght 0x40000.\n* SRAM:   start point 0x20000000  length 0x8000.\n*   VAR:    enough to hold .data and .bss\n*   HEAP:   All the remaining space, up to...\n*   STACK:  start point 0x20007000  length 0x1000.\n*\/\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\n_stack_size = 0x1000;\n\n\/*\n* Sections definitions:\n*\n* .text     - machine instructions.\n* .ARM*     - No idea\n* .eh_frame - No idea\n* .data     - initialized data defined in the program.\n* .bss      - un-initialized global and static variables (to be initialized to 0 before starting main).\n*\/\nSECTIONS\n{\n    \/* This section it's the code, containing the NVIC Vector table that must start at 0x0\n     *   Look at the LM4F120H5QR datasheet for details. (Table 2-8. Exception Types)\n     *\/\n\n     . = 0x00000000;\n\n    .text :\n    {\n        KEEP(*(.nvic_table))     \/* This must be first. It tells the ARM where the stack and IRQ vectors are. *\/\n                                 \/* KEEP stops it being removed as we don't refer to it anywhere. *\/\n        *(.text*)                \/* This contains most of the executable code. *\/\n        *(.rodata*)              \/* Read only data (const variables) *\/\n        . = ALIGN(4);\n    } > FLASH\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > FLASH\n\n    _start_data_flash = ALIGN(8);\n\n    \/*\n     * .data segment must be placed in RAM but it's originally stored in FLASH\n     * So I set the data segment in ram, but I specify the load address with the AT\n     * keyword to set that right after the .text section.\n     * (Look at the LD documentation. (Optional Section Attributes))\n     * Thanks https:\/\/github.com\/utzig for the hints!\n     *\/\n    .data : AT (_start_data_flash)\n    {\n        _start_data = .;  \/* An index to the beginning of .data segment. *\/\n        *(.data*)         \/* Initialised program data *\/\n        _end_data = .;    \/* And another index to the end of .data segment. *\/\n    } > SRAM\n\n    \/*\n    * .bss contains the unitialized variables and must be set as 0x0 during runtime.\n    * It should be loaded in RAM and particular care should be taken initializing them in the startup file.\n    *\/\n    .bss :\n    {\n        _bss_start = .;  \/* This is an index to the beginning of .bss segment. *\/\n        *(.bss*)         \/* The un-initialized data should go there.  *\/\n        _bss_end = .;    \/* End index for .bss segment *\/\n    } > SRAM\n\n    _heap_bottom = .;\n    _heap_top = ORIGIN(SRAM) + LENGTH(SRAM) - _stack_size;\n    _stack_bottom = _heap_top;\n    _stack_top = ORIGIN(SRAM) + LENGTH(SRAM);\n}\n","old_contents":"\/*\n* Copyright (c) 2012, Mauro Scomparin\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*     * Redistributions of source code must retain the above copyright\n*       notice, this list of conditions and the following disclaimer.\n*     * Redistributions in binary form must reproduce the above copyright\n*       notice, this list of conditions and the following disclaimer in the\n*       documentation and\/or other materials provided with the distribution.\n*     * Neither the name of Mauro Scomparin nor the\n*       names of its contributors may be used to endorse or promote products\n*       derived from this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY Mauro Scomparin ``AS IS'' AND ANY\n* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL Mauro Scomparin BE LIABLE FOR ANY\n* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*\n* Author:   Mauro Scomparin <http:\/\/scompoprojects.wordpress.com>.\n* Author:   Jonathan Pallant <http:\/\/railwayelectronics.blogspot.com>.\n* Description:  Linker description file for LM4FXXX microcontrollers.\n*\/\n\n\/*\n* Memory definition:\n* FLASH:  start point 0x00,   lenght 0x40000.\n* SRAM:   start point 0x20000000  length 0x8000.\n*   VAR:    enough to hold .data and .bss\n*   HEAP:   All the remaining space, up to...\n*   STACK:  start point 0x20007000  length 0x1000.\n*\/\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\n_stack_size = 0x1000;\n\n\/*\n* Sections definitions:\n*\n* .text     - machine instructions.\n* .ARM*     - No idea\n* .eh_frame - No idea\n* .data     - initialized data defined in the program.\n* .bss      - un-initialized global and static variables (to be initialized to 0 before starting main).\n*\/\nSECTIONS\n{\n    \/* This section it's the code, containing the NVIC Vector table that must start at 0x0\n     *   Look at the LM4F120H5QR datasheet for details. (Table 2-8. Exception Types)\n     *\/\n\n     . = 0x00000000;\n\n    .text :\n    {\n        KEEP(*(.nvic_table))     \/* This must be first. It tells the ARM where the stack and IRQ vectors are. *\/\n                                 \/* KEEP stops it being removed as we don't refer to it anywhere. *\/\n        *(.text*)                \/* This contains most of the executable code. *\/\n        *(.rodata*)              \/* Read only data (const variables) *\/\n        . = ALIGN(4);\n    } > FLASH\n\n    _start_data_flash = ALIGN(8);\n\n    \/*\n     * .data segment must be placed in RAM but it's originally stored in FLASH\n     * So I set the data segment in ram, but I specify the load address with the AT\n     * keyword to set that right after the .text section.\n     * (Look at the LD documentation. (Optional Section Attributes))\n     * Thanks https:\/\/github.com\/utzig for the hints!\n     *\/\n    .data : AT (_start_data_flash)\n    {\n        _start_data = .;  \/* An index to the beginning of .data segment. *\/\n        *(.data*)         \/* Initialised program data *\/\n        _end_data = .;    \/* And another index to the end of .data segment. *\/\n    } > SRAM\n\n    \/*\n    * .bss contains the unitialized variables and must be set as 0x0 during runtime.\n    * It should be loaded in RAM and particular care should be taken initializing them in the startup file.\n    *\/\n    .bss :\n    {\n        _bss_start = .;  \/* This is an index to the beginning of .bss segment. *\/\n        *(.bss*)         \/* The un-initialized data should go there.  *\/\n        _bss_end = .;    \/* End index for .bss segment *\/\n    } > SRAM\n\n    _heap_bottom = .;\n    _heap_top = ORIGIN(SRAM) + LENGTH(SRAM) - _stack_size;\n    _stack_bottom = _heap_top;\n    _stack_top = ORIGIN(SRAM) + LENGTH(SRAM);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5789588b5b58cb2be90a6dfd16c1a5b6cc670174","subject":"update linkerscript to use full available ram","message":"update linkerscript to use full available ram\n","repos":"nsol-nmsu\/RIOT,nsol-nmsu\/RIOT,nsol-nmsu\/RIOT,nsol-nmsu\/RIOT,nsol-nmsu\/RIOT","old_file":"cpu\/tm4c1294\/linkerscript.ld","new_file":"cpu\/tm4c1294\/linkerscript.ld","new_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n    rom  (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000\n    ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000\n}\n\n\/* The stack size used by the application. NOTE: you need to adjust  *\/\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0xa00 ;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x00000000, LENGTH = 0x40000\t\t\/* 256K flash *\/\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x8000\t\t\/* 32K ram *\/\n}\n\n\/* The stack size used by the application. NOTE: you need to adjust  *\/\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0xa00 ;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"601cd7ded2cd25d97dd44e954df140ae4dcd28ea","subject":"x86: Stack rewinding frame definition in linker script","message":"x86: Stack rewinding frame definition in linker script\n","repos":"zhicheng\/seL4,zhicheng\/seL4,cmr\/seL4,cmr\/seL4,zhicheng\/seL4,cmr\/seL4","old_file":"src\/plat\/pc99\/linker.lds","new_file":"src\/plat\/pc99\/linker.lds","new_contents":"\/*\n * Copyright 2014, General Dynamics C4 Systems\n *\n * This software may be distributed and modified according to the terms of\n * the GNU General Public License version 2. Note that NO WARRANTY is provided.\n * See \"LICENSE_GPLv2.txt\" for details.\n *\n * @TAG(GD_GPL)\n *\/\n\n#include <config.h>\n\nENTRY(_start)\n\n\/* WARNING: constants also defined in plat\/machine\/hardware.h *\/\nPADDR_BASE = 0x00000000;\nPADDR_LOAD = 0x00100000;\nKERNEL_BASE  = 0xe0000000;\nKERNEL_OFFSET = KERNEL_BASE - PADDR_BASE;\n\nSECTIONS\n{\n    \/* load kernel to 1M to avoid the famous IA-32 memory holes below *\/\n    . = PADDR_LOAD;\n\n    \/* code\/data only needed during bootstrapping, linked to physical addresses *\/\n\n    .phys . :\n    {\n        *(.mbh)\n        *(.phys.text)\n        _boot_stack_bottom = .;\n        . = . + 2K;\n        . = ALIGN(4K);\n        _boot_stack_top = .;\n        *(.phys)\n        *(.phys.*)\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .boot . : AT(ADDR(.boot) - KERNEL_OFFSET)\n    {\n        *(.boot.text)\n        *(.boot.data)\n        . = ALIGN(4K);\n    }\n\n    ki_boot_end = .;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        *(.text)\n    }\n\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    .ehframe : AT(ADDR(.ehframe) - KERNEL_OFFSET)\n    {\n        _ehframe = .;\n        *(.eh_frame)\n        . = ALIGN(4K);\n    }\n\n    . = ALIGN(4K);\n    ki_end = .;\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n    }\n}\n","old_contents":"\/*\n * Copyright 2014, General Dynamics C4 Systems\n *\n * This software may be distributed and modified according to the terms of\n * the GNU General Public License version 2. Note that NO WARRANTY is provided.\n * See \"LICENSE_GPLv2.txt\" for details.\n *\n * @TAG(GD_GPL)\n *\/\n\n#include <config.h>\n\nENTRY(_start)\n\n\/* WARNING: constants also defined in plat\/machine\/hardware.h *\/\nPADDR_BASE = 0x00000000;\nPADDR_LOAD = 0x00100000;\nKERNEL_BASE  = 0xe0000000;\nKERNEL_OFFSET = KERNEL_BASE - PADDR_BASE;\n\nSECTIONS\n{\n    \/* load kernel to 1M to avoid the famous IA-32 memory holes below *\/\n    . = PADDR_LOAD;\n\n    \/* code\/data only needed during bootstrapping, linked to physical addresses *\/\n\n    .phys . :\n    {\n        *(.mbh)\n        *(.phys.text)\n        _boot_stack_bottom = .;\n        . = . + 2K;\n        . = ALIGN(4K);\n        _boot_stack_top = .;\n        *(.phys)\n        *(.phys.*)\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .boot . : AT(ADDR(.boot) - KERNEL_OFFSET)\n    {\n        *(.boot.text)\n        *(.boot.data)\n        . = ALIGN(4K);\n    }\n\n    ki_boot_end = .;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        *(.text)\n    }\n\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    . = ALIGN(4K);\n    ki_end = .;\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n    }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"38020a6a8d305e1c11bbd7ad47ee715c2fd1a375","subject":"stm32f1: by default set ROM size to 64K (STM32F103C8T6)","message":"stm32f1: by default set ROM size to 64K (STM32F103C8T6)\n","repos":"ntwyman\/zinc,mcoffin\/zinc,ntwyman\/zinc,hackndev\/zinc,richo\/zinc,hackndev\/zinc,ntwyman\/zinc,hackndev\/zinc,richo\/zinc,ntwyman\/zinc,hackndev\/zinc,mcoffin\/zinc,mcoffin\/zinc,richo\/zinc,hackndev\/zinc,mcoffin\/zinc,mcoffin\/zinc,richo\/zinc,ntwyman\/zinc,richo\/zinc","old_file":"src\/hal\/stm32f1\/layout.ld","new_file":"src\/hal\/stm32f1\/layout.ld","new_contents":"__STACK_BASE = 0x20004FFF;  \/* end of ram *\/\n_data_load = LOADADDR(.data);\n\nINCLUDE iomem.ld\n\nENTRY(main)\n\nMEMORY\n{\n    rom(RX)     : ORIGIN = 0x08000000, LENGTH = 64K\n    ram(WAIL)   : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\nREGION_ALIAS(\"vectors\", rom);\n\nINCLUDE layout_common.ld\n","old_contents":"__STACK_BASE = 0x20004FFF;  \/* end of ram *\/\n_data_load = LOADADDR(.data);\n\nINCLUDE iomem.ld\n\nENTRY(main)\n\nMEMORY\n{\n    rom(RX)     : ORIGIN = 0x08000000, LENGTH = 128K\n    ram(WAIL)   : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\nREGION_ALIAS(\"vectors\", rom);\n\nINCLUDE layout_common.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f053f1b25dead6fb30f29492ae6ee20776fdcc72","subject":"arch: arm: cortex_r: linker.ld: Clean-up","message":"arch: arm: cortex_r: linker.ld: Clean-up\n\nThis commit cleans up the linker.ld file for the Cortex-R arch.\n\n* Convert all TAB characters to SPACE.\n* Fix insane placement of curly brackets.\n* Fix overall text alignments.\n* Remove the special handlings for the Cortex-M devices that were\n  copied from `include\/arm\/aarch32\/cortex_m\/scripts\/linker.ld`.\n\nSigned-off-by: Stephanos Ioannidis <dc76e9f0c0006e8f919e0c515c66dbba3982f785@stephanos.io>\n","repos":"galak\/zephyr,nashif\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_r\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_r\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM      (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    MPU_ALIGN(_image_rodata_end -_image_rom_start);\n    _image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        *(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n    } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_HAS_TI_CCFG\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_HAS_TI_CCFG\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_HAS_TI_CCFG\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8a2624c1066ee22af561582f1ab42fb04f4232fc","subject":"arch\/x86: linker.ld: do not pad _image_rom_end when XIP","message":"arch\/x86: linker.ld: do not pad _image_rom_end when XIP\n\nThis appears to be leftover from the days when we generated\nmore memory protection data at build time.\n\nSigned-off-by: Charles E. Youse <5bc2c6f24e92b68873229a004438f1d6a77a3862@intel.com>\n","repos":"Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/x86\/ia32\/linker.ld","new_file":"include\/arch\/x86\/ia32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <sys\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame_hdr)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_X86_MMU\n\t. = ALIGN(4);\n\tz_x86_mmulist_start = .;\n\tKEEP(*(.mmulist))\n\tz_x86_mmulist_end = .;\n#endif \/* CONFIG_X86_MMU *\/\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tMMU_PAGE_ALIGN\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\t_image_rodata_end = _image_rom_end;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t*(.noinit)\n\t*(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif \/* LINKER_PASS2 *\/\n\n\tz_interrupt_vectors_allocated = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_vectors_alloc))\n#else\n\t. += (CONFIG_IDT_NUM_VECTORS + 7) \/ 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_X86_KPTI\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_start = .;\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. IDT, GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\/\n#endif \/* CONFIG_X86_KPTI *\/\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_KPTI\n\tz_trampoline_stack_start = .;\n\tMMU_PAGE_ALIGN\n\tz_trampoline_stack_end = .;\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_trampoline_stack_end - z_trampoline_stack_start >= 40,\n\t\t\"trampoline stack too small\");\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(DT_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <sys\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame_hdr)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_X86_MMU\n\t. = ALIGN(4);\n\tz_x86_mmulist_start = .;\n\tKEEP(*(.mmulist))\n\tz_x86_mmulist_end = .;\n#endif \/* CONFIG_X86_MMU *\/\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tMMU_PAGE_ALIGN\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n#ifdef CONFIG_XIP\n\t\/* For XIP systems, the kernel object tables are kept at the end\n\t * of ROM and are unpredictable in size; the true size of the ROM\n\t * region isn't know when the MMU tables are generated.\n\t * Just set the rom region to extend to the end of flash.\n\t *\/\n\t_image_rom_end = _image_rom_start + KB(DT_ROM_SIZE);\n#else\n\t_image_rom_end = .;\n#endif\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\t_image_rodata_end = _image_rom_end;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t*(.noinit)\n\t*(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif \/* LINKER_PASS2 *\/\n\n\tz_interrupt_vectors_allocated = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_vectors_alloc))\n#else\n\t. += (CONFIG_IDT_NUM_VECTORS + 7) \/ 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_X86_KPTI\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_start = .;\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. IDT, GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\/\n#endif \/* CONFIG_X86_KPTI *\/\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_KPTI\n\tz_trampoline_stack_start = .;\n\tMMU_PAGE_ALIGN\n\tz_trampoline_stack_end = .;\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_trampoline_stack_end - z_trampoline_stack_start >= 40,\n\t\t\"trampoline stack too small\");\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(DT_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4ca53fad83fee3e4474311e3adc1738953314616","subject":"Firmware: Code format cleanup","message":"Firmware: Code format cleanup\n","repos":"Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano","old_file":"firmware\/mini\/avalon4_mini.ld","new_file":"firmware\/mini\/avalon4_mini.ld","new_contents":"MEMORY\n{\n\t\/* Define each memory region *\/\n\tMFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 \/* 32K bytes *\/\n\tRamLoc4 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x1000 \/* 4K bytes *\/\n\tRamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n}\n\n\/* Define a symbol for the top of each memory region *\/\n__top_MFlash32 = 0x0 + 0x8000;\n__top_RamLoc4 = 0x10000000 + 0x1000;\n__top_RamUsb2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\t\/* MAIN TEXT SECTION *\/\n\t.text : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t__vectors_start__ = ABSOLUTE(.);\n\t\tKEEP(*(.isr_vector))\n\n\t\t\/* Global Section Table *\/\n\t\t. = ALIGN(4);\n\t\t__section_table_start = .;\n\t\t__data_section_table = .;\n\t\tLONG(LOADADDR(.data));\n\t\tLONG(ADDR(.data));\n\t\tLONG(SIZEOF(.data));\n\t\tLONG(LOADADDR(.data_RAM2));\n\t\tLONG(ADDR(.data_RAM2));\n\t\tLONG(SIZEOF(.data_RAM2));\n\t\t__data_section_table_end = .;\n\t\t__bss_section_table = .;\n\t\tLONG(ADDR(.bss));\n\t\tLONG(SIZEOF(.bss));\n\t\tLONG(ADDR(.bss_RAM2));\n\t\tLONG(SIZEOF(.bss_RAM2));\n\t\t__bss_section_table_end = .;\n\t\t__section_table_end = . ;\n\t\t\/* End of Global Section Table *\/\n\n\t\t*(.after_vectors*)\n\n\t\t\/* Code Read Protect data *\/\n\t\t. = 0x000002FC;\n\t\tPROVIDE(__CRP_WORD_START__ = .);\n\t\tKEEP(*(.crp))\n\t\tPROVIDE(__CRP_WORD_END__ = .);\n\t\tASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), \"Linker CRP Enabled, but no CRP_WORD provided within application\");\n\t\t\/* End of Code Read Protect *\/\n\t} >MFlash32\n\n\t.text : ALIGN(4)\n\t{\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .constdata .constdata.*)\n\t\t. = ALIGN(4);\n\t} > MFlash32\n\n\t\/*\n\t * for exception handling\/unwind - some Newlib functions (in common\n\t * with C++ and STDC++) use this.\n\t *\/\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > MFlash32\n\t__exidx_start = .;\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > MFlash32\n\t__exidx_end = .;\n\n\t_etext = .;\n\n\t\/* DATA section for RamUsb2 *\/\n\t.data_RAM2 : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t*(.ramfunc.$RAM2)\n\t\t*(.ramfunc.$RamUsb2)\n\t\t*(.data.$RAM2*)\n\t\t*(.data.$RamUsb2*)\n\t\t. = ALIGN(4);\n\t} > RamUsb2 AT>MFlash32\n\n\t\/* MAIN DATA SECTION *\/\n\t.uninit_RESERVED : ALIGN(4)\n\t{\n\t\tKEEP(*(.bss.$RESERVED*))\n\t\t. = ALIGN(4);\n\t\t_end_uninit_RESERVED = .;\n\t} > RamLoc4\n\n\t\/* Main DATA section (RamLoc4) *\/\n\t.data : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t_data = .;\n\t\t*(vtable)\n\t\t*(.ramfunc*)\n\t\t*(.data*)\n\t\t. = ALIGN(4);\n\t\t_edata = .;\n\t} > RamLoc4 AT>MFlash32\n\n\t\/* BSS section for RamUsb2 *\/\n\t.bss_RAM2 : ALIGN(4)\n\t{\n\t\t*(.bss.$RAM2*)\n\t\t*(.bss.$RamUsb2*)\n\t\t. = ALIGN(4);\n\t} > RamUsb2\n\n\t\/* MAIN BSS SECTION *\/\n\t.bss : ALIGN(4)\n\t{\n\t\t_bss = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4) ;\n\t\t_ebss = .;\n\t\tPROVIDE(end = .);\n\t} > RamLoc4\n\n\t\/* NOINIT section for RamUsb2 *\/\n\t.noinit_RAM2 (NOLOAD) : ALIGN(4)\n\t{\n\t\t*(.noinit.$RAM2*)\n\t\t*(.noinit.$RamUsb2*)\n\t\t. = ALIGN(4);\n\t} > RamUsb2\n\n\t\/* DEFAULT NOINIT SECTION *\/\n\t.noinit (NOLOAD): ALIGN(4)\n\t{\n\t\t_noinit = .;\n\t\t*(.noinit*)\n\t\t. = ALIGN(4) ;\n\t\t_end_noinit = .;\n\t} > RamLoc4\n\n\tPROVIDE(_pvHeapStart = .);\n\tPROVIDE(_vStackTop = __top_RamLoc4 - 0);\n}\n","old_contents":"MEMORY\n{\n\t\/* Define each memory region *\/\n\tMFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 \/* 32K bytes *\/\n\tRamLoc4 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x1000 \/* 4K bytes *\/\n\tRamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n}\n\n\/* Define a symbol for the top of each memory region *\/\n__top_MFlash32 = 0x0 + 0x8000;\n__top_RamLoc4 = 0x10000000 + 0x1000;\n__top_RamUsb2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\t\/* MAIN TEXT SECTION *\/\n\t.text : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t__vectors_start__ = ABSOLUTE(.);\n\t\tKEEP(*(.isr_vector))\n\n\t\t\/* Global Section Table *\/\n\t\t. = ALIGN(4);\n\t\t__section_table_start = .;\n\t\t__data_section_table = .;\n\t\tLONG(LOADADDR(.data));\n\t\tLONG(ADDR(.data));\n\t\tLONG(SIZEOF(.data));\n\t\tLONG(LOADADDR(.data_RAM2));\n\t\tLONG(ADDR(.data_RAM2));\n\t\tLONG(SIZEOF(.data_RAM2));\n\t\t__data_section_table_end = .;\n\t\t__bss_section_table = .;\n\t\tLONG(ADDR(.bss));\n\t\tLONG(SIZEOF(.bss));\n\t\tLONG(ADDR(.bss_RAM2));\n\t\tLONG(SIZEOF(.bss_RAM2));\n\t\t__bss_section_table_end = .;\n\t\t__section_table_end = . ;\n\t\t\/* End of Global Section Table *\/\n\n\t\t*(.after_vectors*)\n\n\t\t\/* Code Read Protect data *\/\n\t\t. = 0x000002FC;\n\t\tPROVIDE(__CRP_WORD_START__ = .);\n\t\tKEEP(*(.crp))\n\t\tPROVIDE(__CRP_WORD_END__ = .);\n\t\tASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), \"Linker CRP Enabled, but no CRP_WORD provided within application\");\n\t\t\/* End of Code Read Protect *\/\n\t} >MFlash32\n\n\t.text : ALIGN(4)\n\t{\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .constdata .constdata.*)\n\t\t. = ALIGN(4);\n\t} > MFlash32\n\n\t\/*\n\t * for exception handling\/unwind - some Newlib functions (in common\n\t * with C++ and STDC++) use this.\n\t *\/\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > MFlash32\n\t__exidx_start = .;\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > MFlash32\n\t__exidx_end = .;\n\n\t_etext = .;\n\n\t\/* DATA section for RamUsb2 *\/\n\t.data_RAM2 : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t*(.ramfunc.$RAM2)\n\t\t*(.ramfunc.$RamUsb2)\n\t\t*(.data.$RAM2*)\n\t\t*(.data.$RamUsb2*)\n\t\t. = ALIGN(4);\n\t} > RamUsb2 AT>MFlash32\n\n\t\/* MAIN DATA SECTION *\/\n\t.uninit_RESERVED : ALIGN(4)\n\t{\n\t\tKEEP(*(.bss.$RESERVED*))\n\t\t. = ALIGN(4);\n\t\t_end_uninit_RESERVED = .;\n\t} > RamLoc4\n\n\t\/* Main DATA section (RamLoc4) *\/\n\t.data : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t_data = .;\n\t\t*(vtable)\n\t\t*(.ramfunc*)\n\t\t*(.data*)\n\t\t. = ALIGN(4);\n\t\t_edata = .;\n\t    } > RamLoc4 AT>MFlash32\n\n\t    \/* BSS section for RamUsb2 *\/\n\t    .bss_RAM2 : ALIGN(4)\n\t    {\n\t\t    *(.bss.$RAM2*)\n\t\t    *(.bss.$RamUsb2*)\n\t\t    . = ALIGN(4);\n\t} > RamUsb2\n\n\t\/* MAIN BSS SECTION *\/\n\t.bss : ALIGN(4)\n\t{\n\t\t_bss = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4) ;\n\t\t_ebss = .;\n\t\tPROVIDE(end = .);\n\t} > RamLoc4\n\n\t\/* NOINIT section for RamUsb2 *\/\n\t.noinit_RAM2 (NOLOAD) : ALIGN(4)\n\t{\n\t\t*(.noinit.$RAM2*)\n\t\t*(.noinit.$RamUsb2*)\n\t\t. = ALIGN(4);\n\t} > RamUsb2\n\n\t\/* DEFAULT NOINIT SECTION *\/\n\t.noinit (NOLOAD): ALIGN(4)\n\t{\n\t\t_noinit = .;\n\t\t*(.noinit*)\n\t\t. = ALIGN(4) ;\n\t\t_end_noinit = .;\n\t} > RamLoc4\n\n\tPROVIDE(_pvHeapStart = .);\n\tPROVIDE(_vStackTop = __top_RamLoc4 - 0);\n}\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"acf61c7597b33c56857eb68370df9e7c7108c083","subject":"lpc17xx: temporarily incrase flash size for testing","message":"lpc17xx: temporarily incrase flash size for testing\n\nThe debug binaries are big.  The lpc1768 has 512K, so there is plenty\nof room.  Will have to see why the flash amount was so low previously.\nThere may be some board that has that little space.\n","repos":"ntwyman\/zinc,hackndev\/zinc,richo\/zinc,hackndev\/zinc,troplin\/zinc,mcoffin\/zinc,hackndev\/zinc,richo\/zinc,mcoffin\/zinc,mcoffin\/zinc,phil-opp\/zinc,troplin\/zinc,troplin\/zinc,ntwyman\/zinc,richo\/zinc,farcaller\/zinc,farcaller\/zinc,phil-opp\/zinc,posborne\/zinc,mcoffin\/zinc,posborne\/zinc,posborne\/zinc,ntwyman\/zinc,hackndev\/zinc,phil-opp\/zinc,phil-opp\/zinc,farcaller\/zinc,ntwyman\/zinc,richo\/zinc,posborne\/zinc,mcoffin\/zinc,farcaller\/zinc,troplin\/zinc,phil-opp\/zinc,posborne\/zinc,ntwyman\/zinc,hackndev\/zinc,farcaller\/zinc,troplin\/zinc,richo\/zinc","old_file":"src\/hal\/lpc17xx\/layout.ld","new_file":"src\/hal\/lpc17xx\/layout.ld","new_contents":"__STACK_BASE  = 0x10002000;\n\nINCLUDE iomem.ld\n\nisr_reserved_1 = 0 - (__STACK_BASE + main + 1 + isr_nmi + 1 + isr_hardfault + 1);\n\n_data_load = LOADADDR(.data);\n\nENTRY(main)\n\nMEMORY\n{\n    rom(RX)   : ORIGIN = 0x00000000, LENGTH = 64K\n    ram(WAIL) : ORIGIN = 0x10000000, LENGTH = 0x2000\n}\n\nREGION_ALIAS(\"vectors\", rom);\n\nINCLUDE layout_common.ld\n","old_contents":"__STACK_BASE  = 0x10002000;\n\nINCLUDE iomem.ld\n\nisr_reserved_1 = 0 - (__STACK_BASE + main + 1 + isr_nmi + 1 + isr_hardfault + 1);\n\n_data_load = LOADADDR(.data);\n\nENTRY(main)\n\nMEMORY\n{\n    rom(RX)   : ORIGIN = 0x00000000, LENGTH = 0x8000\n    ram(WAIL) : ORIGIN = 0x10000000, LENGTH = 0x2000\n}\n\nREGION_ALIAS(\"vectors\", rom);\n\nINCLUDE layout_common.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a6b80c592fae246154f077ea30aa3199bbc3d7a7","subject":"Update location for the static libraries","message":"Update location for the static libraries\n","repos":"yanbe\/platform-espressif8266","old_file":"ldscripts\/esp8266.flash.common.ld","new_file":"ldscripts\/esp8266.flash.common.ld","new_contents":"\/* Base temaplte for ESP8266 *\/\n\n\/* PlatformIO modifications: please search for \"*.pioenvs\"  *\/\n\n\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.pioenvs\\\\*\\\\lib\\\\*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/lib\/*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\\\\*\\\\src\\\\*.o(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/src\/*.o(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.pioenvs\\\\*\\\\lib\\\\*.a:(.iram.text)\n    *.pioenvs\/*\/lib\/*.a:(.iram.text)\n    *.pioenvs\\\\*\\\\src\\\\*.o(.iram.text)\n    *.pioenvs\/*\/src\/*.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( ets_run = 0x40000e04 );\nPROVIDE ( ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n","old_contents":"\/* Base temaplte for ESP8266 *\/\n\n\/* PlatformIO modifications: please search for \"*.pioenvs\"  *\/\n\n\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.pioenvs\\\\*\\\\lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\\\\*\\\\src\\\\*.o(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/src\/*.o(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.pioenvs\\\\*\\\\lib*.a:(.iram.text)\n    *.pioenvs\/*\/lib*.a:(.iram.text)\n    *.pioenvs\\\\*\\\\src\\\\*.o(.iram.text)\n    *.pioenvs\/*\/src\/*.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\nPROVIDE ( Cache_Read_Enable = 0x40004678 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x400035a0 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000368c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40003538 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x40003658 );\nPROVIDE ( GetUartDevice = 0x40003f4c );\nPROVIDE ( MD5Final = 0x40009900 );\nPROVIDE ( MD5Init = 0x40009818 );\nPROVIDE ( MD5Update = 0x40009834 );\nPROVIDE ( MemDwnLdStartMsgProc = 0x400036c4 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x4000377c );\nPROVIDE ( MemPacketSendReqMsgProc = 0x400036f0 );\nPROVIDE ( RcvMsg = 0x40003eac );\nPROVIDE ( SHA1Final = 0x4000b648 );\nPROVIDE ( SHA1Init = 0x4000b584 );\nPROVIDE ( SHA1Transform = 0x4000a364 );\nPROVIDE ( SHA1Update = 0x4000b5a8 );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( SPIEraseArea = 0x40004b44 );\nPROVIDE ( SPIEraseBlock = 0x400049b4 );\nPROVIDE ( SPIEraseChip = 0x40004984 );\nPROVIDE ( SPIEraseSector = 0x40004a00 );\nPROVIDE ( SPILock = 0x400048a8 );\nPROVIDE ( SPIParamCfg = 0x40004c2c );\nPROVIDE ( SPIRead = 0x40004b1c );\nPROVIDE ( SPIReadModeCnfig = 0x400048ec );\nPROVIDE ( SPIUnlock = 0x40004878 );\nPROVIDE ( SPIWrite = 0x40004a4c );\nPROVIDE ( SelectSpiFunction = 0x40003f58 );\nPROVIDE ( SendMsg = 0x40003cf4 );\nPROVIDE ( UartConnCheck = 0x40003230 );\nPROVIDE ( UartConnectProc = 0x400037a0 );\nPROVIDE ( UartDwnLdProc = 0x40003368 );\nPROVIDE ( UartGetCmdLn = 0x40003ef4 );\nPROVIDE ( UartRegReadProc = 0x4000381c );\nPROVIDE ( UartRegWriteProc = 0x400037ac );\nPROVIDE ( UartRxString = 0x40003c30 );\nPROVIDE ( Uart_Init = 0x40003a14 );\nPROVIDE ( _DebugExceptionVector = 0x40000010 );\nPROVIDE ( _DoubleExceptionVector = 0x40000070 );\nPROVIDE ( _KernelExceptionVector = 0x40000030 );\nPROVIDE ( _NMIExceptionVector = 0x40000020 );\nPROVIDE ( _ResetHandler = 0x400000a4 );\nPROVIDE ( _ResetVector = 0x40000080 );\nPROVIDE ( _UserExceptionVector = 0x40000050 );\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\nPROVIDE ( _rom_store = 0x4000e388 );\nPROVIDE ( _rom_store_table = 0x4000e328 );\nPROVIDE ( _start = 0x4000042c );\nPROVIDE ( _xtos_alloca_handler = 0x4000dbe0 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000598 );\nPROVIDE ( _xtos_cause3_handler = 0x40000590 );\nPROVIDE ( _xtos_ints_off = 0x4000bda4 );\nPROVIDE ( _xtos_ints_on = 0x4000bd84 );\nPROVIDE ( _xtos_l1int_handler = 0x4000048c );\nPROVIDE ( _xtos_p_none = 0x4000dbf8 );\nPROVIDE ( _xtos_restore_intlevel = 0x4000056c );\nPROVIDE ( _xtos_return_from_exc = 0x4000dc54 );\nPROVIDE ( _xtos_set_exception_handler = 0x40000454 );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bd70 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bd28 );\nPROVIDE ( _xtos_set_intlevel = 0x4000dbfc );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000dc18 );\nPROVIDE ( _xtos_set_vpri = 0x40000574 );\nPROVIDE ( _xtos_syscall_handler = 0x4000dbe4 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000dc44 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000dc3c );\nPROVIDE ( aes_decrypt = 0x400092d4 );\nPROVIDE ( aes_decrypt_deinit = 0x400092e4 );\nPROVIDE ( aes_decrypt_init = 0x40008ea4 );\nPROVIDE ( aes_unwrap = 0x40009410 );\nPROVIDE ( base64_decode = 0x40009648 );\nPROVIDE ( base64_encode = 0x400094fc );\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( cmd_parse = 0x40000814 );\nPROVIDE ( conv_str_decimal = 0x40000b24 );\nPROVIDE ( conv_str_hex = 0x40000cb8 );\nPROVIDE ( convert_para_str = 0x40000a60 );\nPROVIDE ( dtm_get_intr_mask = 0x400026d0 );\nPROVIDE ( dtm_params_init = 0x4000269c );\nPROVIDE ( dtm_set_intr_mask = 0x400026c8 );\nPROVIDE ( dtm_set_params = 0x400026dc );\nPROVIDE ( eprintf = 0x40001d14 );\nPROVIDE ( eprintf_init_buf = 0x40001cb8 );\nPROVIDE ( eprintf_to_host = 0x40001d48 );\nPROVIDE ( est_get_printf_buf_remain_len = 0x40002494 );\nPROVIDE ( est_reset_printf_buf_len = 0x4000249c );\nPROVIDE ( ets_bzero = 0x40002ae8 );\nPROVIDE ( ets_char2xdigit = 0x40002b74 );\nPROVIDE ( ets_delay_us = 0x40002ecc );\nPROVIDE ( ets_enter_sleep = 0x400027b8 );\nPROVIDE ( ets_external_printf = 0x40002578 );\nPROVIDE ( ets_get_cpu_frequency = 0x40002f0c );\nPROVIDE ( ets_getc = 0x40002bcc );\nPROVIDE ( ets_install_external_printf = 0x40002450 );\nPROVIDE ( ets_install_putc1 = 0x4000242c );\nPROVIDE ( ets_install_putc2 = 0x4000248c );\nPROVIDE ( ets_install_uart_printf = 0x40002438 );\nPROVIDE ( ets_intr_lock = 0x40000f74 );\nPROVIDE ( ets_intr_unlock = 0x40000f80 );\nPROVIDE ( ets_isr_attach = 0x40000f88 );\nPROVIDE ( ets_isr_mask = 0x40000f98 );\nPROVIDE ( ets_isr_unmask = 0x40000fa8 );\nPROVIDE ( ets_memcmp = 0x400018d4 );\nPROVIDE ( ets_memcpy = 0x400018b4 );\nPROVIDE ( ets_memmove = 0x400018c4 );\nPROVIDE ( ets_memset = 0x400018a4 );\nPROVIDE ( ets_post = 0x40000e24 );\nPROVIDE ( ets_printf = 0x400024cc );\nPROVIDE ( ets_putc = 0x40002be8 );\nPROVIDE ( ets_rtc_int_register = 0x40002a40 );\nPROVIDE ( ets_run = 0x40000e04 );\nPROVIDE ( ets_set_idle_cb = 0x40000dc0 );\nPROVIDE ( ets_set_user_start = 0x40000fbc );\nPROVIDE ( ets_str2macaddr = 0x40002af8 );\nPROVIDE ( ets_strcmp = 0x40002aa8 );\nPROVIDE ( ets_strcpy = 0x40002a88 );\nPROVIDE ( ets_strlen = 0x40002ac8 );\nPROVIDE ( ets_strncmp = 0x40002ab8 );\nPROVIDE ( ets_strncpy = 0x40002a98 );\nPROVIDE ( ets_strstr = 0x40002ad8 );\nPROVIDE ( ets_task = 0x40000dd0 );\nPROVIDE ( ets_timer_arm = 0x40002cc4 );\nPROVIDE ( ets_timer_disarm = 0x40002d40 );\nPROVIDE ( ets_timer_done = 0x40002d80 );\nPROVIDE ( ets_timer_handler_isr = 0x40002da8 );\nPROVIDE ( ets_timer_init = 0x40002e68 );\nPROVIDE ( ets_timer_setfn = 0x40002c48 );\nPROVIDE ( ets_uart_printf = 0x40002544 );\nPROVIDE ( ets_update_cpu_frequency = 0x40002f04 );\nPROVIDE ( ets_vprintf = 0x40001f00 );\nPROVIDE ( ets_wdt_disable = 0x400030f0 );\nPROVIDE ( ets_wdt_enable = 0x40002fa0 );\nPROVIDE ( ets_wdt_get_mode = 0x40002f34 );\nPROVIDE ( ets_wdt_init = 0x40003170 );\nPROVIDE ( ets_wdt_restore = 0x40003158 );\nPROVIDE ( ets_write_char = 0x40001da0 );\nPROVIDE ( get_first_seg = 0x4000091c );\nPROVIDE ( gpio_init = 0x40004c50 );\nPROVIDE ( gpio_input_get = 0x40004cf0 );\nPROVIDE ( gpio_intr_ack = 0x40004dcc );\nPROVIDE ( gpio_intr_handler_register = 0x40004e28 );\nPROVIDE ( gpio_intr_pending = 0x40004d88 );\nPROVIDE ( gpio_intr_test = 0x40004efc );\nPROVIDE ( gpio_output_set = 0x40004cd0 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40004d90 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40004ed4 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40004e90 );\nPROVIDE ( gpio_register_get = 0x40004d5c );\nPROVIDE ( gpio_register_set = 0x40004d04 );\nPROVIDE ( hmac_md5 = 0x4000a2cc );\nPROVIDE ( hmac_md5_vector = 0x4000a160 );\nPROVIDE ( hmac_sha1 = 0x4000ba28 );\nPROVIDE ( hmac_sha1_vector = 0x4000b8b4 );\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\nPROVIDE ( main = 0x40000fec );\nPROVIDE ( md5_vector = 0x400097ac );\nPROVIDE ( mem_calloc = 0x40001c2c );\nPROVIDE ( mem_free = 0x400019e0 );\nPROVIDE ( mem_init = 0x40001998 );\nPROVIDE ( mem_malloc = 0x40001b40 );\nPROVIDE ( mem_realloc = 0x40001c6c );\nPROVIDE ( mem_trim = 0x40001a14 );\nPROVIDE ( mem_zalloc = 0x40001c58 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\nPROVIDE ( multofup = 0x400031c0 );\nPROVIDE ( pbkdf2_sha1 = 0x4000b840 );\nPROVIDE ( phy_get_romfuncs = 0x40006b08 );\nPROVIDE ( rand = 0x40000600 );\nPROVIDE ( rc4_skip = 0x4000dd68 );\nPROVIDE ( recv_packet = 0x40003d08 );\nPROVIDE ( remove_head_space = 0x40000a04 );\nPROVIDE ( rijndaelKeySetupDec = 0x40008dd0 );\nPROVIDE ( rijndaelKeySetupEnc = 0x40009300 );\nPROVIDE ( rom_abs_temp = 0x400060c0 );\nPROVIDE ( rom_ana_inf_gating_en = 0x40006b10 );\nPROVIDE ( rom_cal_tos_v50 = 0x40007a28 );\nPROVIDE ( rom_chip_50_set_channel = 0x40006f84 );\nPROVIDE ( rom_chip_v5_disable_cca = 0x400060d0 );\nPROVIDE ( rom_chip_v5_enable_cca = 0x400060ec );\nPROVIDE ( rom_chip_v5_rx_init = 0x4000711c );\nPROVIDE ( rom_chip_v5_sense_backoff = 0x4000610c );\nPROVIDE ( rom_chip_v5_tx_init = 0x4000718c );\nPROVIDE ( rom_dc_iq_est = 0x4000615c );\nPROVIDE ( rom_en_pwdet = 0x400061b8 );\nPROVIDE ( rom_get_bb_atten = 0x40006238 );\nPROVIDE ( rom_get_corr_power = 0x40006260 );\nPROVIDE ( rom_get_fm_sar_dout = 0x400062dc );\nPROVIDE ( rom_get_noisefloor = 0x40006394 );\nPROVIDE ( rom_get_power_db = 0x400063b0 );\nPROVIDE ( rom_i2c_readReg = 0x40007268 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x4000729c );\nPROVIDE ( rom_i2c_writeReg = 0x400072d8 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x4000730c );\nPROVIDE ( rom_iq_est_disable = 0x40006400 );\nPROVIDE ( rom_iq_est_enable = 0x40006430 );\nPROVIDE ( rom_linear_to_db = 0x40006484 );\nPROVIDE ( rom_mhz2ieee = 0x400065a4 );\nPROVIDE ( rom_pbus_dco___SA2 = 0x40007bf0 );\nPROVIDE ( rom_pbus_debugmode = 0x4000737c );\nPROVIDE ( rom_pbus_enter_debugmode = 0x40007410 );\nPROVIDE ( rom_pbus_exit_debugmode = 0x40007448 );\nPROVIDE ( rom_pbus_force_test = 0x4000747c );\nPROVIDE ( rom_pbus_rd = 0x400074d8 );\nPROVIDE ( rom_pbus_set_rxgain = 0x4000754c );\nPROVIDE ( rom_pbus_set_txgain = 0x40007610 );\nPROVIDE ( rom_pbus_workmode = 0x40007648 );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40007688 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x400076cc );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x400076fc );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x40007740 );\nPROVIDE ( rom_pbus_xpd_tx_on__low_gain = 0x400077a0 );\nPROVIDE ( rom_phy_reset_req = 0x40007804 );\nPROVIDE ( rom_restart_cal = 0x4000781c );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40007eb4 );\nPROVIDE ( rom_rfcal_rxiq = 0x4000804c );\nPROVIDE ( rom_rfcal_rxiq_set_reg = 0x40008264 );\nPROVIDE ( rom_rfcal_txcap = 0x40008388 );\nPROVIDE ( rom_rfcal_txiq = 0x40008610 );\nPROVIDE ( rom_rfcal_txiq_cover = 0x400088b8 );\nPROVIDE ( rom_rfcal_txiq_set_reg = 0x40008a70 );\nPROVIDE ( rom_rfpll_reset = 0x40007868 );\nPROVIDE ( rom_rfpll_set_freq = 0x40007968 );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40008b6c );\nPROVIDE ( rom_rxiq_get_mis = 0x40006628 );\nPROVIDE ( rom_sar_init = 0x40006738 );\nPROVIDE ( rom_set_ana_inf_tx_scale = 0x4000678c );\nPROVIDE ( rom_set_channel_freq = 0x40006c50 );\nPROVIDE ( rom_set_loopback_gain = 0x400067c8 );\nPROVIDE ( rom_set_noise_floor = 0x40006830 );\nPROVIDE ( rom_set_rxclk_en = 0x40006550 );\nPROVIDE ( rom_set_txbb_atten = 0x40008c6c );\nPROVIDE ( rom_set_txclk_en = 0x4000650c );\nPROVIDE ( rom_set_txiq_cal = 0x40008d34 );\nPROVIDE ( rom_start_noisefloor = 0x40006874 );\nPROVIDE ( rom_start_tx_tone = 0x400068b4 );\nPROVIDE ( rom_stop_tx_tone = 0x4000698c );\nPROVIDE ( rom_tx_mac_disable = 0x40006a98 );\nPROVIDE ( rom_tx_mac_enable = 0x40006ad4 );\nPROVIDE ( rom_txtone_linear_pwr = 0x40006a1c );\nPROVIDE ( rom_write_rfpll_sdm = 0x400078dc );\nPROVIDE ( roundup2 = 0x400031b4 );\nPROVIDE ( rtc_enter_sleep = 0x40002870 );\nPROVIDE ( rtc_get_reset_reason = 0x400025e0 );\nPROVIDE ( rtc_intr_handler = 0x400029ec );\nPROVIDE ( rtc_set_sleep_mode = 0x40002668 );\nPROVIDE ( save_rxbcn_mactime = 0x400027a4 );\nPROVIDE ( save_tsf_us = 0x400027ac );\nPROVIDE ( send_packet = 0x40003c80 );\nPROVIDE ( sha1_prf = 0x4000ba48 );\nPROVIDE ( sha1_vector = 0x4000a2ec );\nPROVIDE ( sip_alloc_to_host_evt = 0x40005180 );\nPROVIDE ( sip_get_ptr = 0x400058a8 );\nPROVIDE ( sip_get_state = 0x40005668 );\nPROVIDE ( sip_init_attach = 0x4000567c );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000544c );\nPROVIDE ( sip_install_rx_data_cb = 0x4000545c );\nPROVIDE ( sip_post = 0x400050fc );\nPROVIDE ( sip_post_init = 0x400056c4 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000534c );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x400052c0 );\nPROVIDE ( sip_send = 0x40005808 );\nPROVIDE ( sip_to_host_chain_append = 0x40005864 );\nPROVIDE ( sip_to_host_evt_send_done = 0x40005234 );\nPROVIDE ( slc_add_credits = 0x400060ac );\nPROVIDE ( slc_enable = 0x40005d90 );\nPROVIDE ( slc_from_host_chain_fetch = 0x40005f24 );\nPROVIDE ( slc_from_host_chain_recycle = 0x40005e94 );\nPROVIDE ( slc_init_attach = 0x40005c50 );\nPROVIDE ( slc_init_credit = 0x4000608c );\nPROVIDE ( slc_pause_from_host = 0x40006014 );\nPROVIDE ( slc_reattach = 0x40005c1c );\nPROVIDE ( slc_resume_from_host = 0x4000603c );\nPROVIDE ( slc_select_tohost_gpio = 0x40005dc0 );\nPROVIDE ( slc_select_tohost_gpio_mode = 0x40005db8 );\nPROVIDE ( slc_send_to_host_chain = 0x40005de4 );\nPROVIDE ( slc_set_host_io_max_window = 0x40006068 );\nPROVIDE ( slc_to_host_chain_recycle = 0x40005f10 );\nPROVIDE ( software_reset = 0x4000264c );\nPROVIDE ( spi_flash_attach = 0x40004644 );\nPROVIDE ( srand = 0x400005f0 );\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\nPROVIDE ( timer_insert = 0x40002c64 );\nPROVIDE ( uartAttach = 0x4000383c );\nPROVIDE ( uart_baudrate_detect = 0x40003924 );\nPROVIDE ( uart_buff_switch = 0x400038a4 );\nPROVIDE ( uart_div_modify = 0x400039d8 );\nPROVIDE ( uart_rx_intr_handler = 0x40003bbc );\nPROVIDE ( uart_rx_one_char = 0x40003b8c );\nPROVIDE ( uart_rx_one_char_block = 0x40003b64 );\nPROVIDE ( uart_rx_readbuff = 0x40003ec8 );\nPROVIDE ( uart_tx_one_char = 0x40003b30 );\nPROVIDE ( wepkey_128 = 0x4000bc40 );\nPROVIDE ( wepkey_64 = 0x4000bb3c );\nPROVIDE ( xthal_bcopy = 0x40000688 );\nPROVIDE ( xthal_copy123 = 0x4000074c );\nPROVIDE ( xthal_get_ccompare = 0x4000dd4c );\nPROVIDE ( xthal_get_ccount = 0x4000dd38 );\nPROVIDE ( xthal_get_interrupt = 0x4000dd58 );\nPROVIDE ( xthal_get_intread = 0x4000dd58 );\nPROVIDE ( xthal_memcpy = 0x400006c4 );\nPROVIDE ( xthal_set_ccompare = 0x4000dd40 );\nPROVIDE ( xthal_set_intclear = 0x4000dd60 );\nPROVIDE ( xthal_spill_registers_into_stack_nw = 0x4000e320 );\nPROVIDE ( xthal_window_spill = 0x4000e324 );\nPROVIDE ( xthal_window_spill_nw = 0x4000e320 );\n\nPROVIDE ( Te0 = 0x3fffccf0 );\nPROVIDE ( Td0 = 0x3fffd100 );\nPROVIDE ( Td4s = 0x3fffd500);\nPROVIDE ( rcons = 0x3fffd0f0);\nPROVIDE ( UartDev = 0x3fffde10 );\nPROVIDE ( flashchip = 0x3fffc714);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"28361592aeb2ac564d4a6dbe8c85319baa69055a","subject":"sam0_common: Adjust ldscript memory segment attributes","message":"sam0_common: Adjust ldscript memory segment attributes\n","repos":"avmelnikoff\/RIOT,toonst\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,miri64\/RIOT,kYc0o\/RIOT,A-Paul\/RIOT,kbumsik\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,OlegHahm\/RIOT,OTAkeys\/RIOT,josephnoir\/RIOT,x3ro\/RIOT,yogo1212\/RIOT,A-Paul\/RIOT,x3ro\/RIOT,kYc0o\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,smlng\/RIOT,mfrey\/RIOT,rfuentess\/RIOT,gebart\/RIOT,mfrey\/RIOT,cladmi\/RIOT,biboc\/RIOT,cladmi\/RIOT,toonst\/RIOT,yogo1212\/RIOT,OlegHahm\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,A-Paul\/RIOT,aeneby\/RIOT,kYc0o\/RIOT,aeneby\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,aeneby\/RIOT,josephnoir\/RIOT,mfrey\/RIOT,toonst\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,cladmi\/RIOT,avmelnikoff\/RIOT,neiljay\/RIOT,biboc\/RIOT,lazytech-org\/RIOT,jasonatran\/RIOT,smlng\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,mtausig\/RIOT,neiljay\/RIOT,authmillenon\/RIOT,kbumsik\/RIOT,kbumsik\/RIOT,basilfx\/RIOT,ant9000\/RIOT,neiljay\/RIOT,ant9000\/RIOT,OTAkeys\/RIOT,rfuentess\/RIOT,kbumsik\/RIOT,OTAkeys\/RIOT,mfrey\/RIOT,basilfx\/RIOT,rfuentess\/RIOT,biboc\/RIOT,cladmi\/RIOT,lazytech-org\/RIOT,gebart\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,miri64\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,lazytech-org\/RIOT,ant9000\/RIOT,avmelnikoff\/RIOT,biboc\/RIOT,lazytech-org\/RIOT,miri64\/RIOT,BytesGalore\/RIOT,aeneby\/RIOT,kaspar030\/RIOT,avmelnikoff\/RIOT,rfuentess\/RIOT,josephnoir\/RIOT,x3ro\/RIOT,x3ro\/RIOT,ant9000\/RIOT,josephnoir\/RIOT,yogo1212\/RIOT,mfrey\/RIOT,aeneby\/RIOT,smlng\/RIOT,gebart\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,mtausig\/RIOT,toonst\/RIOT,jasonatran\/RIOT,rfuentess\/RIOT,miri64\/RIOT,yogo1212\/RIOT,kbumsik\/RIOT,josephnoir\/RIOT,cladmi\/RIOT,yogo1212\/RIOT,lazytech-org\/RIOT,RIOT-OS\/RIOT,BytesGalore\/RIOT,basilfx\/RIOT,jasonatran\/RIOT,smlng\/RIOT,BytesGalore\/RIOT,A-Paul\/RIOT,RIOT-OS\/RIOT,neiljay\/RIOT,gebart\/RIOT,mtausig\/RIOT,mtausig\/RIOT,neiljay\/RIOT,biboc\/RIOT,A-Paul\/RIOT,yogo1212\/RIOT,toonst\/RIOT,mtausig\/RIOT,avmelnikoff\/RIOT,gebart\/RIOT,BytesGalore\/RIOT,smlng\/RIOT,BytesGalore\/RIOT","old_file":"cpu\/sam0_common\/ldscripts\/samd21j18a_arduino_bootloader.ld","new_file":"cpu\/sam0_common\/ldscripts\/samd21j18a_arduino_bootloader.ld","new_contents":"\/*\n * Copyright (C) 2017 Inria\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_samd21\n * @{\n *\n * @file\n * @brief           Memory definitions for the SAMD21J18A with Arduino bootloader\n *\n * @author          Alexandre Abadie <alexandre.abadie@inria.fr>\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x00002000, LENGTH = 256K-0x2000\n    ram (w!rx)  : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2017 Inria\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_samd21\n * @{\n *\n * @file\n * @brief           Memory definitions for the SAMD21J18A with Arduino bootloader\n *\n * @author          Alexandre Abadie <alexandre.abadie@inria.fr>\n *\n * @}\n *\/\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x00002000, LENGTH = 256K-0x2000\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"26f7601c18bf3dbc26c916db19661d608e2eb841","subject":"SDK13","message":"SDK13\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa.ld","new_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa.ld","new_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x20000, LENGTH = 0x60000\r\n\tRAM (rwx) :  ORIGIN = 0x20002200, LENGTH = 0xde00\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","old_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x1F000, LENGTH = 0x61000\r\n\tRAM (rwx) :  ORIGIN = 0x20002200, LENGTH = 0xde00\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"7f9b9b4d530433567913f6b895a713aded826472","subject":"append bss section, data section","message":"append bss section, data section\n","repos":"tjjh89017\/arm-slave,tjjh89017\/arm-slave","old_file":"src\/kernel.ld","new_file":"src\/kernel.ld","new_contents":"OUTPUT_ARCH(arm)\nENTRY(_start)\n\nENTRY_SVC_STACK_SIZE = 0x1000;\n\nSECTIONS\n{\n\t. = 0x10000;\n\t.start_section : {\n\t\tboot.o(.text .text.*)\n\t\tstart.o(.text .text.*)\n\n\t\tboot.o(.rodata .rodata.*)\n\t\tstart.o(.rodata .rodata.*)\n\n\t\tboot.o(.data .data.*)\n\t\tstart.o(.data .data.*)\n\n\t\tPROVIDE(boot_data_start = .);\n\t\tPROVIDE(boot_bss_start = .);\n\n\t\tboot.o(.bss .bss.* COMMON)\n\t\tstart.o(.bss .bss.* COMMON)\n\n\t\t. = ALIGN(0x1000);\n\t\tPROVIDE(boot_bss_end = .);\n\n\t\t\/* define a stack for boot *\/\n\t\t. += ENTRY_SVC_STACK_SIZE;\n\t\tPROVIDE(svc_stack = .);\n\n\t\t. = ALIGN(0x4000);\n\t\t\/* for kernel page table *\/\n\t\tPROVIDE(_kernel_pgd = .);\n\t\t. += 0x4000;\n\n\t\t\/* for user page table *\/\n\t\tPROVIDE(_user_pgd = .);\n\t\t. += 0x1000;\n\n\t\tPROVIDE(boot_data_end = .);\n\t}\n\n\t. = ALIGN(0x1000);\n\n\tPROVIDE(data_start = .);\n\n\tPROVIDE(data_end = .);\n\tPROVIDE(bss_start = .);\n\n\tPROVIDE(bss_end = .);\n\n\t. = ALIGN(0x1000);\n\tPROVIDE(end = .);\n}\n","old_contents":"OUTPUT_ARCH(arm)\nENTRY(_start)\n\nENTRY_SVC_STACK_SIZE = 0x1000;\n\nSECTIONS\n{\n\t. = 0x10000;\n\t.start_section : {\n\t\tboot.o(.text .text.*)\n\t\tstart.o(.text .text.*)\n\n\t\tboot.o(.rodata .rodata.*)\n\t\tstart.o(.rodata .rodata.*)\n\n\t\tboot.o(.data .data.*)\n\t\tstart.o(.data .data.*)\n\n\t\tPROVIDE(boot_data_start = .);\n\t\tPROVIDE(boot_bss_start = .);\n\n\t\tboot.o(.bss .bss.* COMMON)\n\t\tstart.o(.bss .bss.* COMMON)\n\n\t\t. = ALIGN(0x1000);\n\t\tPROVIDE(boot_bss_end = .);\n\n\t\t\/* define a stack for boot *\/\n\t\t. += ENTRY_SVC_STACK_SIZE;\n\t\tPROVIDE(svc_stack = .);\n\n\t\t. = ALIGN(0x4000);\n\t\t\/* for kernel page table *\/\n\t\tPROVIDE(_kernel_pgd = .);\n\t\t. += 0x4000;\n\n\t\t\/* for user page table *\/\n\t\tPROVIDE(_user_pgd = .);\n\t\t. += 0x1000;\n\n\t\tPROVIDE(boot_data_end = .);\n\t}\n\n\tPROVIDE(end = .);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4bdcd9dd82af875c0c8399985cf4d5f163313987","subject":"Moves the IRQ stack of the mbed to the ETHRAM segment (where the stacks are anyhow). This allows the last 4kb page of the core RAM to be allocated -- currently the last sbrk call could never complete because it requested 4kb but only a tiny bit less was actually available.","message":"Moves the IRQ stack of the mbed to the ETHRAM segment (where the stacks are anyhow). This allows the last 4kb page of the core RAM to be allocated -- currently the last sbrk call could never complete because it requested 4kb but only a tiny bit less was actually available.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/nxp-lpc1768-mbed-tch\/target.ld","new_file":"boards\/nxp-lpc1768-mbed-tch\/target.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\nGROUP(\n libgcc.a\n libc.a\n libstdc++.a\n libm.a\n \/*libcr_newlib_nohost.a*\/\n \/*crti.o\n crtn.o\n crtbegin.o\n crtend.o*\/\n )\n\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n__ETHRAM_segment_start__  = ORIGIN( ETH_RAM );\n\n\/* Set stack top to end of RAM, and stack limit move down by      \n * size of stack_dummy section *\/\n__cs3_heap_end = ORIGIN(RAM) + LENGTH(RAM);\n__StackTop = ORIGIN( ETH_RAM ) + LENGTH( ETH_RAM );\n__StackLimit = __StackTop - 0x200;\nPROVIDE(__stack = __StackTop);\n\/* This marks the highest allocatable stack space *\/\n__stacks_min__ = __StackLimit ;\n\n__USBRAM_segment_start__  = ORIGIN( USB_RAM );\n__USBRAM_segment_end__    = ORIGIN( USB_RAM ) + LENGTH( USB_RAM );\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(SORT(.rodata*))\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    __data_init_start__ = LOADADDR( .data ) ;\n    ASSERT(__data_init_start__ == __etext, \"Initialized data source inconsistent\")\n        \n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n        __cs3_heap_start = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\nGROUP(\n libgcc.a\n libc.a\n libstdc++.a\n libm.a\n \/*libcr_newlib_nohost.a*\/\n \/*crti.o\n crtn.o\n crtbegin.o\n crtend.o*\/\n )\n\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n__ETHRAM_segment_start__  = ORIGIN( ETH_RAM );\n\/* This marks the highest allocatable stack space *\/\n__stacks_min__ = ORIGIN( ETH_RAM ) + LENGTH( ETH_RAM );\n\n__USBRAM_segment_start__  = ORIGIN( USB_RAM );\n__USBRAM_segment_end__    = ORIGIN( USB_RAM ) + LENGTH( USB_RAM );\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(SORT(.rodata*))\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    __data_init_start__ = LOADADDR( .data ) ;\n    ASSERT(__data_init_start__ == __etext, \"Initialized data source inconsistent\")\n        \n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n        __cs3_heap_start = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - 0x200;\n    __cs3_heap_end = __StackLimit;\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"db6acbfb950c1ac526ab640974eeb3e21d242c4c","subject":"x86: set up shared kernel page","message":"x86: set up shared kernel page\n\nKPTI requires that there exist one kernel page marked\n'present', because switching between the kernel and the\nshadow page tables is not done automatically and certain\nother CPU data structures must always be in a present page.\n\nMove IDT, GDT, all TSS to this page, and set up a small\ntrampoline stack as a safe landing area when doing\nprivilege level transitions.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"GiulianoFranchetto\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,ldts\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,ldts\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,ldts\/zephyr,galak\/zephyr,Vudentz\/zephyr,explora26\/zephyr,galak\/zephyr,ldts\/zephyr,galak\/zephyr,explora26\/zephyr,explora26\/zephyr,nashif\/zephyr,ldts\/zephyr,finikorg\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/x86\/linker.ld","new_file":"include\/arch\/x86\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n\n\tGROUP_START(ROMABLE_REGION)\n#ifdef CONFIG_REALMODE\n\t\/* 16-bit sections *\/\n\t. = PHYS_RAM_ADDR;\n\n\tSECTION_PROLOGUE(boot, (OPTIONAL),)\n\t{\n\t*(.boot)\n\t. = ALIGN(16);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\t. = ALIGN(8);\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#ifndef CONFIG_REALMODE\n\t_image_text_start = PHYS_LOAD_ADDR;\n#else\n\t_image_text_start = .;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame_hdr)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif \/* CONFIG_X86_FIXED_IRQ_MAPPING *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMMU_PAGE_ALIGN\n#ifdef CONFIG_XIP\n\t\/* Kernel ROM extends to the end of flash. Need to do this to program\n\t * the MMU\n\t *\/\n\t_image_rom_end = _image_rom_start + KB(DT_ROM_SIZE);\n#else\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t_image_rom_end = .;\n#endif\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_COVERAGE_GCOV\n\tSECTION_PROLOGUE(_GCOV_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tMMU_PAGE_ALIGN\n\t\t__gcov_bss_start = .;\n\t\t*(\".bss.__gcov0.*\");\n\t\t. = ALIGN(4);\n\t\tMMU_PAGE_ALIGN\n\t\t__gcov_bss_end = .;\n\t}GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__gcov_bss_num_words = ((__gcov_bss_end - __gcov_bss_start) >> 2);\n\t__gcov_bss_size = __gcov_bss_end - __gcov_bss_start;\n#endif \/* CONFIG_COVERAGE_GCOV *\/\n\n#ifdef CONFIG_APP_SHARED_MEM\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_APP_SHARED_MEM *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\tMMU_PAGE_ALIGN\n#if !defined(CONFIG_APP_SHARED_MEM)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t*(.noinit)\n\t*(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_X86_FIXED_IRQ_MAPPING *\/\n\n\tz_interrupt_vectors_allocated = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_vectors_alloc_data))\n#else\n\t. += (CONFIG_IDT_NUM_VECTORS + 7) \/ 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_X86_KPTI\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_start = .;\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. IDT, GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\/\n#endif \/* CONFIG_X86_KPTI *\/\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_KPTI\n\tz_trampoline_stack_start = .;\n\tMMU_PAGE_ALIGN\n\tz_trampoline_stack_end = .;\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_trampoline_stack_end - z_trampoline_stack_start >= 40,\n\t\t\"trampoline stack too small\");\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n\n#ifdef CONFIG_X86_MMU\n\t\/* Can't really predict the size of this section. Anything after this\n\t * should not be affected if addresses change between builds (currently\n\t * just the gperf tables which is fine).\n\t *\n\t * However, __mmu_tables_start *must* remain stable between builds,\n\t * we can't have anything shifting the memory map beforehand.\n\t *\/\n\tSECTION_DATA_PROLOGUE(mmu_tables, (OPTIONAL),)\n\t{\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(DT_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu_x86.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n\n\tGROUP_START(ROMABLE_REGION)\n#ifdef CONFIG_REALMODE\n\t\/* 16-bit sections *\/\n\t. = PHYS_RAM_ADDR;\n\n\tSECTION_PROLOGUE(boot, (OPTIONAL),)\n\t{\n\t*(.boot)\n\t. = ALIGN(16);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\t. = ALIGN(8);\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#ifndef CONFIG_REALMODE\n\t_image_text_start = PHYS_LOAD_ADDR;\n#else\n\t_image_text_start = .;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame_hdr)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif \/* CONFIG_X86_FIXED_IRQ_MAPPING *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMMU_PAGE_ALIGN\n#ifdef CONFIG_XIP\n\t\/* Kernel ROM extends to the end of flash. Need to do this to program\n\t * the MMU\n\t *\/\n\t_image_rom_end = _image_rom_start + KB(DT_ROM_SIZE);\n#else\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n\t_image_rom_end = .;\n#endif\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_COVERAGE_GCOV\n\tSECTION_PROLOGUE(_GCOV_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tMMU_PAGE_ALIGN\n\t\t__gcov_bss_start = .;\n\t\t*(\".bss.__gcov0.*\");\n\t\t. = ALIGN(4);\n\t\tMMU_PAGE_ALIGN\n\t\t__gcov_bss_end = .;\n\t}GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__gcov_bss_num_words = ((__gcov_bss_end - __gcov_bss_start) >> 2);\n\t__gcov_bss_size = __gcov_bss_end - __gcov_bss_start;\n#endif \/* CONFIG_COVERAGE_GCOV *\/\n\n#ifdef CONFIG_APP_SHARED_MEM\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_APP_SHARED_MEM *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\tMMU_PAGE_ALIGN\n#if !defined(CONFIG_APP_SHARED_MEM)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t*(.noinit)\n\t*(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_X86_FIXED_IRQ_MAPPING *\/\n\n\tz_interrupt_vectors_allocated = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_vectors_alloc_data))\n#else\n\t. += (CONFIG_IDT_NUM_VECTORS + 7) \/ 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n\n#ifdef CONFIG_X86_MMU\n\t\/* Can't really predict the size of this section. Anything after this\n\t * should not be affected if addresses change between builds (currently\n\t * just the gperf tables which is fine).\n\t *\n\t * However, __mmu_tables_start *must* remain stable between builds,\n\t * we can't have anything shifting the memory map beforehand.\n\t *\/\n\tSECTION_DATA_PROLOGUE(mmu_tables, (OPTIONAL),)\n\t{\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(DT_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu_x86.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6b9ea45f3397e1a9e054f3fbba51262c41882f86","subject":"update","message":"update\n","repos":"vad7\/PowerMeter,vad7\/PowerMeter,vad7\/PowerMeter,vad7\/PowerMeter,vad7\/PowerMeter,vad7\/PowerMeter","old_file":"ld\/labels.ld","new_file":"ld\/labels.ld","new_contents":"<<<<<<< Upstream, based on 5ee9b049c02408d69696958a56fa91865e9d3ab1\nPROVIDE\t(_memmap_cacheattr_wb_base = 0x00000110);\r\nPROVIDE\t(_memmap_cacheattr_wt_base = 0x00000110);\r\nPROVIDE\t(_memmap_cacheattr_bp_base = 0x00000220);\r\nPROVIDE\t(_memmap_cacheattr_wb_allvalid = 0x22222112);\r\nPROVIDE\t(_memmap_cacheattr_wt_allvalid = 0x22222112);\r\nPROVIDE\t(_memmap_cacheattr_wb_trapnull = 0x2222211f);\r\nPROVIDE\t(_memmap_cacheattr_wba_trapnull = 0x2222211f);\r\nPROVIDE\t(_memmap_cacheattr_wbna_trapnull = 0x2222211f);\r\nPROVIDE\t(_memmap_cacheattr_wt_trapnull = 0x2222211f);\r\nPROVIDE\t(_memmap_cacheattr_bp_allvalid = 0x22222222);\r\nPROVIDE\t(_memmap_cacheattr_bp_trapnull = 0x2222222f);\r\nPROVIDE\t(_dport0_data_end = 0x3ff00000);\r\nPROVIDE\t(_dport0_data_start = 0x3ff00000);\r\nPROVIDE\t(_dport0_literal_end = 0x3ff00000);\r\nPROVIDE\t(_dport0_literal_start = 0x3ff00000);\r\nPROVIDE\t(_dport0_rodata_end = 0x3ff00000);\r\nPROVIDE\t(_dport0_rodata_start = 0x3ff00000);\r\nPROVIDE\t(dport_ = 0x3ff00000);\r\nPROVIDE\t(_data_start = 0x3ffe8000);\r\nPROVIDE\t(SDK_VERSION = 0x3ffe8000);\r\nPROVIDE\t(TmpSTAAPCloseAP = 0x3ffe8008);\r\nPROVIDE\t(memp_sizes_test = 0x3ffe800a);\r\nPROVIDE\t(tx_rf_ana_gain = 0x3ffe8012);\r\nPROVIDE\t(rx_gain_swp = 0x3ffe8040);\r\nPROVIDE\t(test_rffreq_txcap = 0x3ffe8060);\r\nPROVIDE\t(chip_version = 0x3ffe8064);\r\nPROVIDE\t(soft_wdt_interval = 0x3ffe8070);\r\nPROVIDE\t(NoiseTimerInterval = 0x3ffe8074);\r\nPROVIDE\t(sleep_start_wait_time = 0x3ffe807c);\r\nPROVIDE\t(CanDoFreqCal = 0x3ffe8084);\r\nPROVIDE\t(tcb = 0x3ffe8088);\r\nPROVIDE\t(timer2_ms_flag = 0x3ffe832d);\r\nPROVIDE\t(dhcps_flag = 0x3ffe832e);\r\nPROVIDE\t(dhcpc_flag = 0x3ffe832f);\r\nPROVIDE\t(reconnect_internal = 0x3ffe8331);\r\nPROVIDE\t(offer = 0x3ffe8344);\r\nPROVIDE\t(FRAM_Status = 0x3ffe8364);\r\nPROVIDE\t(i2c_delay_time = 0x3ffe8368);\r\nPROVIDE\t(HTTPCookie = 0x3ffe836c);\r\nPROVIDE\t(HTTPAuthorization = 0x3ffe8370);\r\nPROVIDE\t(HTTPboundary = 0x3ffe8374);\r\nPROVIDE\t(HTTPmultipartformdata = 0x3ffe8378);\r\nPROVIDE\t(HTTPContentType = 0x3ffe837c);\r\nPROVIDE\t(HTTPContentLength = 0x3ffe8380);\r\nPROVIDE\t(srvContenErr = 0x3ffe8384);\r\nPROVIDE\t(_data_end = 0x3ffe83c4);\r\nPROVIDE\t(_rodata_start = 0x3ffe83c4);\r\nPROVIDE\t(ethzero = 0x3ffe83c4);\r\nPROVIDE\t(ethbroadcast = 0x3ffe83ca);\r\nPROVIDE\t(year_lengths = 0x3ffe8480);\r\nPROVIDE\t(mon_lengths = 0x3ffe8488);\r\nPROVIDE\t(httpContentTypes = 0x3ffe84e8);\r\nPROVIDE\t(httpFileExtensions = 0x3ffe8534);\r\nPROVIDE\t(_bss_table_end = 0x3ffe8b64);\r\nPROVIDE\t(_bss_table_start = 0x3ffe8b64);\r\nPROVIDE\t(_rodata_end = 0x3ffe8b64);\r\nPROVIDE\t(_bss_start = 0x3ffe8b68);\r\nPROVIDE\t(etharp_cached_entry = 0x3ffe8b68);\r\nPROVIDE\t(arp_table = 0x3ffe8b6c);\r\nPROVIDE\t(g_ic = 0x3ffe8c5c);\r\nPROVIDE\t(BcnEb_update = 0x3ffe92e8);\r\nPROVIDE\t(BcnWithMcastSendStart = 0x3ffe92f5);\r\nPROVIDE\t(BcnWithMcastSendCnt = 0x3ffe92f6);\r\nPROVIDE\t(PendFreeBcnEb = 0x3ffe9310);\r\nPROVIDE\t(ApFreqCalTimer = 0x3ffe9314);\r\nPROVIDE\t(APRecvBcnStartTick = 0x3ffe9328);\r\nPROVIDE\t(gScanStruct = 0x3ffe9340);\r\nPROVIDE\t(connect_scan_flag = 0x3ffe93ec);\r\nPROVIDE\t(FreqCalCntForScan = 0x3ffe93ed);\r\nPROVIDE\t(TestStaFreqCalValInput = 0x3ffe93ee);\r\nPROVIDE\t(auth_type = 0x3ffe93f0);\r\nPROVIDE\t(scannum = 0x3ffe93f2);\r\nPROVIDE\t(interface_mask = 0x3ffe9420);\r\nPROVIDE\t(if_ctrl = 0x3ffe9440);\r\nPROVIDE\t(ip_id = 0x3ffe9460);\r\nPROVIDE\t(lmacConfMib = 0x3ffe9484);\r\nPROVIDE\t(our_tx_eb = 0x3ffe94a8);\r\nPROVIDE\t(xStart = 0x3ffe95d0);\r\nPROVIDE\t(g_phyFuns = 0x3ffe95e0);\r\nPROVIDE\t(rxiq_compute_num = 0x3ffe95e4);\r\nPROVIDE\t(rx_table_renew_en = 0x3ffe95e8);\r\nPROVIDE\t(check_result = 0x3ffe95ec);\r\nPROVIDE\t(chip6_sleep_params = 0x3ffe95f0);\r\nPROVIDE\t(chip6_phy_init_ctrl = 0x3ffe9684);\r\nPROVIDE\t(phy_freq_offset = 0x3ffe96f8);\r\nPROVIDE\t(do_pwctrl_flag = 0x3ffe96fa);\r\nPROVIDE\t(pwctrl_debug = 0x3ffe96fb);\r\nPROVIDE\t(txbk_dpdby_flag = 0x3ffe96fc);\r\nPROVIDE\t(sw_scan_mode = 0x3ffe96fe);\r\nPROVIDE\t(rxmax_ext_level = 0x3ffe96ff);\r\nPROVIDE\t(phy_rx_gain_dc_table = 0x3ffe9700);\r\nPROVIDE\t(periodic_cal_dc_num = 0x3ffe9714);\r\nPROVIDE\t(periodic_cal_flag = 0x3ffe9718);\r\nPROVIDE\t(bbpll_cal_flag = 0x3ffe9719);\r\nPROVIDE\t(phy_in_most_power = 0x3ffe971a);\r\nPROVIDE\t(init_rf_no_cal = 0x3ffe971b);\r\nPROVIDE\t(test_print_time = 0x3ffe971c);\r\nPROVIDE\t(phy_rx_gain_dc_flag = 0x3ffe9720);\r\nPROVIDE\t(phy_in_vdd33_offset = 0x3ffe9721);\r\nPROVIDE\t(phy_set_most_tpw_disbg = 0x3ffe9722);\r\nPROVIDE\t(phy_set_most_tpw_index = 0x3ffe9723);\r\nPROVIDE\t(adc_rand_noise = 0x3ffe9724);\r\nPROVIDE\t(dpd_bypass_original = 0x3ffe9728);\r\nPROVIDE\t(noise_array = 0x3ffe9730);\r\nPROVIDE\t(tout_dis_txpwr_track = 0x3ffe9740);\r\nPROVIDE\t(sleep_mode_flag = 0x3ffe9741);\r\nPROVIDE\t(phy_tx_power_out = 0x3ffe9744);\r\nPROVIDE\t(loop_pwctrl_pwdet_error_accum_high_power = 0x3ffe9746);\r\nPROVIDE\t(tx_pwctrl_pk_num = 0x3ffe9748);\r\nPROVIDE\t(tx_pwctrl_track_num = 0x3ffe9749);\r\nPROVIDE\t(loop_pwctrl_correct_atten_high_power = 0x3ffe974a);\r\nPROVIDE\t(rxiq_cover_fail_num = 0x3ffe974b);\r\nPROVIDE\t(periodic_cal_sat = 0x3ffe974c);\r\nPROVIDE\t(lslp_mem_opt_8266 = 0x3ffe974e);\r\nPROVIDE\t(software_slp_reject = 0x3ffe9750);\r\nPROVIDE\t(SDIO_slp_reject = 0x3ffe9751);\r\nPROVIDE\t(hardware_reject = 0x3ffe9752);\r\nPROVIDE\t(pmc = 0x3ffe9760);\r\nPROVIDE\t(flash_tmp = 0x3ffe9840);\r\nPROVIDE\t(pend_flag_noise_check = 0x3ffe98c8);\r\nPROVIDE\t(pend_flag_periodic_cal = 0x3ffe98d0);\r\nPROVIDE\t(idle_timer_reopen_flag = 0x3ffe98e8);\r\nPROVIDE\t(dbg_stop_sw_wdt = 0x3ffe98ea);\r\nPROVIDE\t(dbg_stop_hw_wdt = 0x3ffe98eb);\r\nPROVIDE\t(total_buffed_eb_num = 0x3ffe98ed);\r\nPROVIDE\t(HighestFreqOffsetInOneChk = 0x3ffe98f0);\r\nPROVIDE\t(LowestFreqOffsetInOneChk = 0x3ffe98f2);\r\nPROVIDE\t(DefFreqCalTimer = 0x3ffe98f4);\r\nPROVIDE\t(PktNumInOneChk = 0x3ffe9908);\r\nPROVIDE\t(buffed_eb_arr = 0x3ffe9a90);\r\nPROVIDE\t(tcp_timer = 0x3ffe9ce0);\r\nPROVIDE\t(recv_flags = 0x3ffe9ce4);\r\nPROVIDE\t(tcplen = 0x3ffe9ce6);\r\nPROVIDE\t(flags = 0x3ffe9ce8);\r\nPROVIDE\t(seqno = 0x3ffe9cec);\r\nPROVIDE\t(inseg = 0x3ffe9cf0);\r\nPROVIDE\t(deep_sleep_flag = 0x3ffea277);\r\nPROVIDE\t(cpu_overclock = 0x3ffea278);\r\nPROVIDE\t(event_cb = 0x3ffea27c);\r\nPROVIDE\t(status_led_output_level = 0x3ffea280);\r\nPROVIDE\t(done_cb = 0x3ffea284);\r\nPROVIDE\t(rst_if = 0x3ffea288);\r\nPROVIDE\t(default_interface = 0x3ffea2a4);\r\nPROVIDE\t(OpmodChgIsOnGoing = 0x3ffea2a5);\r\nPROVIDE\t(promiscuous_cb = 0x3ffea2a8);\r\nPROVIDE\t(event_TaskQueue = 0x3ffea2c0);\r\nPROVIDE\t(wDevCtrl = 0x3ffea3d0);\r\nPROVIDE\t(WdevTimOffSet = 0x3ffea578);\r\nPROVIDE\t(sta_con_timer = 0x3ffed6f8);\r\nPROVIDE\t(g_cnx_probe_rc_list_cb = 0x3ffed70c);\r\nPROVIDE\t(reconnect_flag = 0x3ffed710);\r\nPROVIDE\t(no_ap_found_index = 0x3ffed711);\r\nPROVIDE\t(client_address_plus = 0x3ffed98c);\r\nPROVIDE\t(client_address = 0x3ffed990);\r\nPROVIDE\t(server_address = 0x3ffed994);\r\nPROVIDE\t(broadcast_dhcps = 0x3ffed998);\r\nPROVIDE\t(dns_random = 0x3ffed99c);\r\nPROVIDE\t(dns_servers = 0x3ffed9a0);\r\nPROVIDE\t(dns_seqno = 0x3ffed9a8);\r\nPROVIDE\t(allrouters = 0x3ffee460);\r\nPROVIDE\t(allsystems = 0x3ffee464);\r\nPROVIDE\t(user_idle_func_working = 0x3ffee468);\r\nPROVIDE\t(FRAM_STORE_Readed = 0x3ffee469);\r\nPROVIDE\t(PowerCntTime = 0x3ffee46c);\r\nPROVIDE\t(PowerCnt = 0x3ffee470);\r\nPROVIDE\t(info = 0x3ffee474);\r\nPROVIDE\t(user_init_flag = 0x3ffee498);\r\nPROVIDE\t(lwip_timer_interval = 0x3ffee49a);\r\nPROVIDE\t(default_hostname = 0x3ffee49c);\r\nPROVIDE\t(current_iphdr_src = 0x3ffee4a0);\r\nPROVIDE\t(current_netif = 0x3ffee4a4);\r\nPROVIDE\t(current_iphdr_dest = 0x3ffee4a8);\r\nPROVIDE\t(current_header = 0x3ffee4ac);\r\nPROVIDE\t(tcp_listen_pcbs = 0x3ffee4b0);\r\nPROVIDE\t(dhcp_rx_options_given = 0x3ffee4b4);\r\nPROVIDE\t(dhcp_rx_options_val = 0x3ffee4c0);\r\nPROVIDE\t(dhcp_sntp_server_address = 0x3ffee4ec);\r\nPROVIDE\t(dhcps_lease = 0x3ffee4f0);\r\nPROVIDE\t(dns_table = 0x3ffee4f8);\r\nPROVIDE\t(fram_store = 0x3ffee958);\r\nPROVIDE\t(CntCurrent = 0x3ffee968);\r\nPROVIDE\t(cfg_meter = 0x3ffee96c);\r\nPROVIDE\t(Sensor_Edge = 0x3ffee974);\r\nPROVIDE\t(I2C_EEPROM_Error = 0x3ffee978);\r\nPROVIDE\t(wificonfig = 0x3ffee97c);\r\nPROVIDE\t(syscfg = 0x3ffeeaac);\r\nPROVIDE\t(fatCache = 0x3ffeeab8);\r\nPROVIDE\t(flash_firmware_size = 0x3ffeeac8);\r\nPROVIDE\t(_bss_end = 0x3ffeead0);\r\nPROVIDE\t(_heap_start = 0x3ffeead0);\r\nPROVIDE\t(flashchip = 0x3fffc714);\r\nPROVIDE\t(Te0 = 0x3fffccf0);\r\nPROVIDE\t(rcons = 0x3fffd0f0);\r\nPROVIDE\t(base64_table = 0x3fffd600);\r\nPROVIDE\t(ets_idle_cb = 0x3fffdab0);\r\nPROVIDE\t(timer_list = 0x3fffddb0);\r\nPROVIDE\t(UartDev = 0x3fffde10);\r\nPROVIDE\t(_sprintf_buf = 0x3fffe360);\r\nPROVIDE\t(print_mem_buf = 0x3fffe364);\r\nPROVIDE\t(_ResetVector = 0x40000080);\r\nPROVIDE\t(_xtos_set_exception_handler = 0x40000454);\r\nPROVIDE\t(__muldi3 = 0x40000650);\r\nPROVIDE\t(ets_set_idle_cb = 0x40000dc0);\r\nPROVIDE\t(ets_task = 0x40000dd0);\r\nPROVIDE\t(ets_run = 0x40000e04);\r\nPROVIDE\t(ets_post = 0x40000e24);\r\nPROVIDE\t(ets_intr_lock = 0x40000f74);\r\nPROVIDE\t(ets_intr_unlock = 0x40000f80);\r\nPROVIDE\t(ets_isr_attach = 0x40000f88);\r\nPROVIDE\t(ets_isr_mask = 0x40000f98);\r\nPROVIDE\t(ets_isr_unmask = 0x40000fa8);\r\nPROVIDE\t(ets_set_user_start = 0x40000fbc);\r\nPROVIDE\t(ets_memset = 0x400018a4);\r\nPROVIDE\t(ets_memcpy = 0x400018b4);\r\nPROVIDE\t(ets_memcmp = 0x400018d4);\r\nPROVIDE\t(ets_write_char = 0x40001da0);\r\nPROVIDE\t(ets_vprintf = 0x40001f00);\r\nPROVIDE\t(ets_install_putc1 = 0x4000242c);\r\nPROVIDE\t(ets_printf = 0x400024cc);\r\nPROVIDE\t(rtc_get_reset_reason = 0x400025e0);\r\nPROVIDE\t(ets_strcpy = 0x40002a88);\r\nPROVIDE\t(ets_strncpy = 0x40002a98);\r\nPROVIDE\t(ets_strcmp = 0x40002aa8);\r\nPROVIDE\t(ets_strncmp = 0x40002ab8);\r\nPROVIDE\t(ets_strlen = 0x40002ac8);\r\nPROVIDE\t(ets_bzero = 0x40002ae8);\r\nPROVIDE\t(ets_timer_setfn = 0x40002c48);\r\nPROVIDE\t(timer_insert = 0x40002c64);\r\nPROVIDE\t(ets_timer_disarm = 0x40002d40);\r\nPROVIDE\t(ets_timer_init = 0x40002e68);\r\nPROVIDE\t(ets_delay_us = 0x40002ecc);\r\nPROVIDE\t(ets_update_cpu_frequency = 0x40002f04);\r\nPROVIDE\t(ets_get_cpu_frequency = 0x40002f0c);\r\nPROVIDE\t(ets_wdt_get_mode = 0x40002f34);\r\nPROVIDE\t(roundup2 = 0x400031b4);\r\nPROVIDE\t(uart_buff_switch = 0x400038a4);\r\nPROVIDE\t(uart_div_modify = 0x400039d8);\r\nPROVIDE\t(Uart_Init = 0x40003a14);\r\nPROVIDE\t(SelectSpiFunction = 0x40003f58);\r\nPROVIDE\t(SPI_read_status = 0x400043c8);\r\nPROVIDE\t(SPI_write_status = 0x40004400);\r\nPROVIDE\t(Wait_SPI_Idle = 0x4000448c);\r\nPROVIDE\t(SPIFlashCnfig = 0x40004568);\r\nPROVIDE\t(Cache_Read_Enable = 0x40004678);\r\nPROVIDE\t(Cache_Read_Disable = 0x400047f0);\r\nPROVIDE\t(SPIReadModeCnfig = 0x400048ec);\r\nPROVIDE\t(SPIEraseBlock = 0x400049b4);\r\nPROVIDE\t(SPIEraseSector = 0x40004a00);\r\nPROVIDE\t(SPIWrite = 0x40004a4c);\r\nPROVIDE\t(gpio_output_set = 0x40004cd0);\r\nPROVIDE\t(gpio_input_get = 0x40004cf0);\r\nPROVIDE\t(gpio_pin_intr_state_set = 0x40004d90);\r\nPROVIDE\t(lldesc_build_chain = 0x40004f40);\r\nPROVIDE\t(lldesc_num2link = 0x40005050);\r\nPROVIDE\t(rom_chip_v5_disable_cca = 0x400060d0);\r\nPROVIDE\t(rom_chip_v5_enable_cca = 0x400060ec);\r\nPROVIDE\t(phy_get_romfuncs = 0x40006b08);\r\nPROVIDE\t(rom_i2c_readReg = 0x40007268);\r\nPROVIDE\t(rom_i2c_writeReg = 0x400072d8);\r\nPROVIDE\t(rom_i2c_writeReg_Mask = 0x4000730c);\r\nPROVIDE\t(aes_unwrap = 0x40009410);\r\nPROVIDE\t(hmac_md5 = 0x4000a2cc);\r\nPROVIDE\t(pbkdf2_sha1 = 0x4000b840);\r\nPROVIDE\t(hmac_sha1_vector = 0x4000b8b4);\r\nPROVIDE\t(hmac_sha1 = 0x4000ba28);\r\nPROVIDE\t(sha1_prf = 0x4000ba48);\r\nPROVIDE\t(__addsf3 = 0x4000c180);\r\nPROVIDE\t(__subsf3 = 0x4000c268);\r\nPROVIDE\t(__mulsf3 = 0x4000c3dc);\r\nPROVIDE\t(__fixunssfsi = 0x4000c4c4);\r\nPROVIDE\t(__muldf3 = 0x4000c8f0);\r\nPROVIDE\t(__divdf3 = 0x4000cb94);\r\nPROVIDE\t(__fixdfsi = 0x4000ccb8);\r\nPROVIDE\t(__truncdfsf2 = 0x4000cd5c);\r\nPROVIDE\t(__divdi3 = 0x4000ce60);\r\nPROVIDE\t(__umoddi3 = 0x4000d770);\r\nPROVIDE\t(__divsi3 = 0x4000dc88);\r\nPROVIDE\t(rc4_skip = 0x4000dd68);\r\nPROVIDE\t(memcpy = 0x4000df48);\r\nPROVIDE\t(__udivsi3 = 0x4000e21c);\r\nPROVIDE\t(__umodsi3 = 0x4000e268);\r\nPROVIDE\t(__floatunsisf = 0x4000e2a4);\r\nPROVIDE\t(__floatsisf = 0x4000e2ac);\r\nPROVIDE\t(__floatunsidf = 0x4000e2e8);\r\nPROVIDE\t(__floatsidf = 0x4000e2f0);\r\nPROVIDE\t(_stext = 0x40100000);\r\nPROVIDE\t(_text_start = 0x40100000);\r\nPROVIDE\t(jump_boot = 0x40100000);\r\nPROVIDE\t(set_qspi_flash_cache = 0x40100024);\r\nPROVIDE\t(uart0_write_char = 0x40100074);\r\nPROVIDE\t(call_jump_boot = 0x401000cc);\r\nPROVIDE\t(uart1_write_char = 0x4010013c);\r\nPROVIDE\t(user_uart_wait_tx_fifo_empty = 0x4010018c);\r\nPROVIDE\t(ets_timer_arm_new = 0x401001d0);\r\nPROVIDE\t(lmacIsActive = 0x401002a4);\r\nPROVIDE\t(lmacIsIdle = 0x401002b8);\r\nPROVIDE\t(lmacSetAcParam = 0x40100754);\r\nPROVIDE\t(lmacProcessTXStartData = 0x401007a8);\r\nPROVIDE\t(lmacProcessTxSuccess = 0x40100928);\r\nPROVIDE\t(GetAccess = 0x40100a6c);\r\nPROVIDE\t(lmacDiscardAgedMSDU = 0x40100a78);\r\nPROVIDE\t(lmacRecycleMPDU = 0x40100a8c);\r\nPROVIDE\t(lmacProcessTxTimeout = 0x40101064);\r\nPROVIDE\t(lmacProcessAllTxTimeout = 0x401010cc);\r\nPROVIDE\t(lmacProcessCollisions = 0x401010e0);\r\nPROVIDE\t(lmacProcessCollision = 0x40101140);\r\nPROVIDE\t(lmacMSDUAged = 0x401011c4);\r\nPROVIDE\t(lmacProcessCtsTimeout = 0x40101554);\r\nPROVIDE\t(lmacProcessAckTimeout = 0x4010158c);\r\nPROVIDE\t(lmacProcessRtsStart = 0x401015e4);\r\nPROVIDE\t(lmacProcessTxRtsError = 0x401015f0);\r\nPROVIDE\t(lmacProcessTxError = 0x40101690);\r\nPROVIDE\t(lmacTxFrame = 0x40101720);\r\nPROVIDE\t(lmacRxDone = 0x401018bc);\r\nPROVIDE\t(prvInsertBlockIntoFreeList = 0x401018dc);\r\nPROVIDE\t(pvPortMalloc = 0x40101924);\r\nPROVIDE\t(vPortFree = 0x401019d4);\r\nPROVIDE\t(pvPortCalloc = 0x40101a24);\r\nPROVIDE\t(pvPortZalloc = 0x40101a54);\r\nPROVIDE\t(pvPortRealloc = 0x40101a68);\r\nPROVIDE\t(xPortGetFreeHeapSize = 0x40101aa0);\r\nPROVIDE\t(vPortInitialiseBlocks = 0x40101aa8);\r\nPROVIDE\t(xPortWantedSizeAlign = 0x40101aac);\r\nPROVIDE\t(register_phy_ops = 0x40101ac4);\r\nPROVIDE\t(register_get_phy_addr = 0x40101ae4);\r\nPROVIDE\t(phy_change_channel = 0x40101aec);\r\nPROVIDE\t(phy_get_mactime = 0x40101b04);\r\nPROVIDE\t(unsign_to_sign = 0x40101b10);\r\nPROVIDE\t(phy_get_bb_freqoffset = 0x40101b48);\r\nPROVIDE\t(phy_get_bb_evm = 0x40101bac);\r\nPROVIDE\t(pm_rtc_clock_cali = 0x40101bcc);\r\nPROVIDE\t(clockgate_watchdog = 0x40101c88);\r\nPROVIDE\t(pp_soft_wdt_feed_local = 0x40101cec);\r\nPROVIDE\t(ppProcessTxQ = 0x40101d80);\r\nPROVIDE\t(ppFetchTxQFirstAvail = 0x40101df4);\r\nPROVIDE\t(ppDequeueTxQ = 0x40101e34);\r\nPROVIDE\t(ppRollBackTxQ = 0x40101e5c);\r\nPROVIDE\t(ppRecordBarRRC = 0x40101e80);\r\nPROVIDE\t(ppTxqUpdateBitmap = 0x40101e90);\r\nPROVIDE\t(ppEnqueueTxDone = 0x40101eb8);\r\nPROVIDE\t(ppEnqueueRxq = 0x40101eec);\r\nPROVIDE\t(ppDiscardMPDU = 0x401023d4);\r\nPROVIDE\t(pp_post = 0x401023f8);\r\nPROVIDE\t(pp_post2 = 0x40102484);\r\nPROVIDE\t(ppCalTxop = 0x401024ac);\r\nPROVIDE\t(ppCalFrameTimes = 0x4010252c);\r\nPROVIDE\t(RC_GetAckRate = 0x401025bc);\r\nPROVIDE\t(RC_GetRtsRate = 0x401025c8);\r\nPROVIDE\t(RC_GetAckTime = 0x401025d8);\r\nPROVIDE\t(RC_GetCtsTime = 0x401025ec);\r\nPROVIDE\t(RC_GetBlockAckTime = 0x40102624);\r\nPROVIDE\t(copy_s4d1 = 0x40102694);\r\nPROVIDE\t(copy_s1d4 = 0x40102728);\r\nPROVIDE\t(eRamRead = 0x401027c0);\r\nPROVIDE\t(eRamWrite = 0x401027e8);\r\nPROVIDE\t(rom_strlen = 0x4010280c);\r\nPROVIDE\t(rom_strcpy = 0x40102840);\r\nPROVIDE\t(rom_xstrcpy = 0x401028a4);\r\nPROVIDE\t(rom_xstrcmp = 0x401028f4);\r\nPROVIDE\t(rom_strchr = 0x4010293c);\r\nPROVIDE\t(get_align4_chr = 0x40102978);\r\nPROVIDE\t(write_align4_chr = 0x40102990);\r\nPROVIDE\t(Cache_Read_Enable_New = 0x401029b0);\r\nPROVIDE\t(spi_flash_read = 0x401029d8);\r\nPROVIDE\t(spi_flash_get_id = 0x40102b14);\r\nPROVIDE\t(spi_flash_read_status = 0x40102b64);\r\nPROVIDE\t(spi_flash_write_status = 0x40102ba0);\r\nPROVIDE\t(spi_flash_erase_sector = 0x40102bdc);\r\nPROVIDE\t(spi_flash_write = 0x40102c2c);\r\nPROVIDE\t(spi_flash_erase_block = 0x40102c94);\r\nPROVIDE\t(tcp_accept_null = 0x40102cdc);\r\nPROVIDE\t(tcp_new_port = 0x40102cf0);\r\nPROVIDE\t(tcp_close_shutdown = 0x40102d60);\r\nPROVIDE\t(dns_timer = 0x40102eb8);\r\nPROVIDE\t(igmp_timer = 0x40102ee4);\r\nPROVIDE\t(dhcp_timer_fine = 0x40102f10);\r\nPROVIDE\t(dhcp_timer_coarse = 0x40102f44);\r\nPROVIDE\t(rcUpdateTxDone = 0x40103140);\r\nPROVIDE\t(rcUpdateRxDone = 0x401031d4);\r\nPROVIDE\t(rcUpdateDataRxDone = 0x40103230);\r\nPROVIDE\t(rcGetSched = 0x4010324c);\r\nPROVIDE\t(rcGetRate = 0x40103330);\r\nPROVIDE\t(rcReachRetryLimit = 0x40103844);\r\nPROVIDE\t(trc_NeedRTS = 0x4010385c);\r\nPROVIDE\t(os_printf_plus = 0x4010392c);\r\nPROVIDE\t(system_restart_core = 0x40103a58);\r\nPROVIDE\t(system_deep_sleep_local_2 = 0x40103a94);\r\nPROVIDE\t(system_get_time = 0x40103b04);\r\nPROVIDE\t(system_os_post = 0x40103b1c);\r\nPROVIDE\t(system_rtc_mem_write = 0x40103b50);\r\nPROVIDE\t(system_rtc_mem_read = 0x40103ba8);\r\nPROVIDE\t(wDev_MacTim1SetFunc = 0x40103fa4);\r\nPROVIDE\t(wDev_MacTim1Arm = 0x40103fc4);\r\nPROVIDE\t(wDev_ProcessFiq = 0x4010405c);\r\nPROVIDE\t(wDev_EnableTransmit = 0x401043a0);\r\nPROVIDE\t(wDev_DisableTransmit = 0x401043d8);\r\nPROVIDE\t(Tx_Copy2Queue = 0x401043f8);\r\nPROVIDE\t(wDev_ProcessCollision = 0x40104440);\r\nPROVIDE\t(wDev_GetTxqCollisions = 0x40104464);\r\nPROVIDE\t(wDev_ClearTxqCollisions = 0x40104478);\r\nPROVIDE\t(wDev_SetWaitingQueue = 0x40104494);\r\nPROVIDE\t(wDev_ClearWaitingQueue = 0x401044dc);\r\nPROVIDE\t(wDev_SetFrameAckType = 0x40104500);\r\nPROVIDE\t(wDev_AppendRxBlocks = 0x40104564);\r\nPROVIDE\t(wDev_AppendRxAmpduLensBlocks = 0x401046a8);\r\nPROVIDE\t(wDev_GetBAInfo = 0x4010477c);\r\nPROVIDE\t(wDevDisableRx = 0x401047b0);\r\nPROVIDE\t(store_exception_error = 0x40104c70);\r\nPROVIDE\t(fatal_error = 0x40104ca8);\r\nPROVIDE\t(default_exception_handler = 0x40104cc4);\r\nPROVIDE\t(chm_get_current_channel = 0x40104cdc);\r\nPROVIDE\t(__divsf3_aux = 0x40104ce8);\r\nPROVIDE\t(__divsf3 = 0x40104d64);\r\nPROVIDE\t(__fixsfsi = 0x40104e20);\r\nPROVIDE\t(esf_rx_buf_alloc = 0x40104e64);\r\nPROVIDE\t(gpio_int_handler = 0x40104ec4);\r\nPROVIDE\t(i2c_delay = 0x40104f30);\r\nPROVIDE\t(i2c_Stop = 0x40104f44);\r\nPROVIDE\t(i2c_WriteBit = 0x40104f78);\r\nPROVIDE\t(i2c_ReadBit = 0x40104fac);\r\nPROVIDE\t(i2c_Write = 0x40104fd8);\r\nPROVIDE\t(i2c_Read = 0x40105014);\r\nPROVIDE\t(i2c_Start = 0x40105050);\r\nPROVIDE\t(GPIO_intr_handler = 0x401050ac);\r\nPROVIDE\t(__ashrdi3 = 0x4010510c);\r\nPROVIDE\t(__modsi3 = 0x40105124);\r\nPROVIDE\t(__lshrdi3 = 0x40105170);\r\nPROVIDE\t(eraminfo = 0x40105188);\r\nPROVIDE\t(_etext = 0x40105190);\r\nPROVIDE\t(_lit4_start = 0x40105190);\r\nPROVIDE\t(_text_end = 0x40105190);\r\nPROVIDE\t(check_timeouts_timer = 0x40105190);\r\nPROVIDE\t(lwip_if_queues = 0x401051a4);\r\nPROVIDE\t(hostname = 0x401051ac);\r\nPROVIDE\t(xBlockAllocatedBit = 0x401051b0);\r\nPROVIDE\t(xFreeBytesRemaining = 0x401051b4);\r\nPROVIDE\t(pxEnd = 0x401051b8);\r\nPROVIDE\t(netif_default = 0x401051bc);\r\nPROVIDE\t(netif_list = 0x401051c0);\r\nPROVIDE\t(raw_pcbs = 0x401051c4);\r\nPROVIDE\t(flash_size = 0x401051c8);\r\nPROVIDE\t(flash_read = 0x401051cc);\r\nPROVIDE\t(tcp_tmp_pcb = 0x401051d0);\r\nPROVIDE\t(tcp_tw_pcbs = 0x401051d4);\r\nPROVIDE\t(tcp_active_pcbs = 0x401051d8);\r\nPROVIDE\t(tcp_bound_pcbs = 0x401051dc);\r\nPROVIDE\t(tcp_ticks = 0x401051e0);\r\nPROVIDE\t(tcp_input_pcb = 0x401051e4);\r\nPROVIDE\t(recv_data = 0x401051e8);\r\nPROVIDE\t(ackno = 0x401051ec);\r\nPROVIDE\t(tcphdr = 0x401051f0);\r\nPROVIDE\t(tcpip_tcp_timer_active = 0x401051f4);\r\nPROVIDE\t(timeouts_last_time = 0x401051f8);\r\nPROVIDE\t(next_timeout = 0x401051fc);\r\nPROVIDE\t(udp_pcbs = 0x40105200);\r\nPROVIDE\t(dhcps_lease_time = 0x40105204);\r\nPROVIDE\t(renew = 0x40105208);\r\nPROVIDE\t(plist = 0x4010520c);\r\nPROVIDE\t(dhcps_lease_flag = 0x40105210);\r\nPROVIDE\t(pcb_dhcps = 0x40105214);\r\nPROVIDE\t(dns_payload = 0x40105218);\r\nPROVIDE\t(dns_pcb = 0x4010521c);\r\nPROVIDE\t(igmp_group_list = 0x40105220);\r\nPROVIDE\t(GPIO_TaskQueue = 0x40105224);\r\nPROVIDE\t(buf_scan_infos = 0x4010522c);\r\nPROVIDE\t(total_scan_infos = 0x401059ac);\r\nPROVIDE\t(flg_wifi_sleep_enable = 0x401059b0);\r\nPROVIDE\t(st_disconn_timer = 0x401059b4);\r\nPROVIDE\t(flg_sleep = 0x401059c8);\r\nPROVIDE\t(st_reconn_flg = 0x401059cc);\r\nPROVIDE\t(st_reconn_count = 0x401059d0);\r\nPROVIDE\t(flg_open_all_service = 0x401059d4);\r\nPROVIDE\t(probe_requests_count = 0x401059d8);\r\nPROVIDE\t(buf_probe_requests = 0x401059dc);\r\nPROVIDE\t(sntp = 0x40105bdc);\r\nPROVIDE\t(numFiles = 0x40105be0);\r\nPROVIDE\t(fatCacheID = 0x40105be4);\r\nPROVIDE\t(WEBFSStubs = 0x40105be8);\r\nPROVIDE\t(isWEBFSLocked = 0x40105d68);\r\nPROVIDE\t(disk_base_addr = 0x40105d6c);\r\nPROVIDE\t(phcfg = 0x40105d70);\r\nPROVIDE\t(wdrv_bufn = 0x40105d74);\r\nPROVIDE\t(_lit4_end = 0x40105d78);\r\nPROVIDE\t(_irom0_text_start = 0x40207000);\r\nPROVIDE\t(puts_buf = 0x40207004);\r\nPROVIDE\t(read_wifi_config = 0x40207048);\r\nPROVIDE\t(uart_wait_tx_fifo_empty = 0x402070e8);\r\nPROVIDE\t(loader = 0x40207100);\r\nPROVIDE\t(read_macaddr_from_otp = 0x4020713c);\r\nPROVIDE\t(tst_cfg_wifi = 0x402071a8);\r\nPROVIDE\t(startup_uart_init = 0x402072cc);\r\nPROVIDE\t(init_wifi = 0x40207338);\r\nPROVIDE\t(startup = 0x40207480);\r\nPROVIDE\t(init_fn = 0x40207740);\r\nPROVIDE\t(eagle_lwip_if_alloc = 0x4020778c);\r\nPROVIDE\t(eagle_lwip_getif = 0x40207904);\r\nPROVIDE\t(task_if0 = 0x40207924);\r\nPROVIDE\t(task_if1 = 0x4020795c);\r\nPROVIDE\t(eagle_lwip_if_free = 0x40207994);\r\nPROVIDE\t(free_entry = 0x402079ec);\r\nPROVIDE\t(find_entry = 0x40207a48);\r\nPROVIDE\t(etharp_send_ip = 0x40207b24);\r\nPROVIDE\t(update_arp_entry = 0x40207b78);\r\nPROVIDE\t(etharp_tmr = 0x40207c1c);\r\nPROVIDE\t(etharp_find_addr = 0x40207c74);\r\nPROVIDE\t(etharp_request = 0x40207cc8);\r\nPROVIDE\t(etharp_output_to_arp_index = 0x40207d98);\r\nPROVIDE\t(etharp_query = 0x40207e10);\r\nPROVIDE\t(etharp_output = 0x40207fc0);\r\nPROVIDE\t(ethernet_input = 0x402080b0);\r\nPROVIDE\t(etharp_cleanup_netif = 0x402082ac);\r\nPROVIDE\t(ieee80211_rate_ref_init = 0x40208374);\r\nPROVIDE\t(ieee80211_freedom_inside_cb = 0x4020838c);\r\nPROVIDE\t(ieee80211_freedom_init = 0x402083bc);\r\nPROVIDE\t(ieee80211_user_ie_init = 0x402083e0);\r\nPROVIDE\t(ieee80211_ifattach = 0x402083fc);\r\nPROVIDE\t(ieee80211_mhz2ieee = 0x40208464);\r\nPROVIDE\t(ieee80211_chan2ieee = 0x402084c4);\r\nPROVIDE\t(ieee80211_ieee2mhz = 0x402084e0);\r\nPROVIDE\t(ieee80211_find_channel = 0x40208520);\r\nPROVIDE\t(ieee80211_find_channel_byieee = 0x4020854c);\r\nPROVIDE\t(wifi_mode_set = 0x402085a0);\r\nPROVIDE\t(get_iav_key = 0x4020877c);\r\nPROVIDE\t(register_ieee80211_action_vendor_get_key_cb = 0x4020879c);\r\nPROVIDE\t(unregister_ieee80211_action_vendor_get_key_cb = 0x402087b0);\r\nPROVIDE\t(ieee80211_add_action_vendor_spec_esp = 0x402087c8);\r\nPROVIDE\t(ieee80211_alloc_action_vendor_spec = 0x40208810);\r\nPROVIDE\t(ieee80211_send_action_vendor_spec = 0x40208920);\r\nPROVIDE\t(ieee80211_recv_action_vendor_spec = 0x40208ab8);\r\nPROVIDE\t(ieee80211_action_vendor_spec_attach = 0x40208bc4);\r\nPROVIDE\t(register_ieee80211_action_vendor_spec_cb = 0x40208c04);\r\nPROVIDE\t(unregister_ieee80211_action_vendor_spec_cb = 0x40208c18);\r\nPROVIDE\t(ieee80211_crypto_attach = 0x40208c24);\r\nPROVIDE\t(ieee80211_crypto_available = 0x40208c28);\r\nPROVIDE\t(ieee80211_crypto_setkey = 0x40208c2c);\r\nPROVIDE\t(ieee80211_crypto_encap = 0x40208c30);\r\nPROVIDE\t(ieee80211_crypto_decap = 0x40208c88);\r\nPROVIDE\t(ieee80211_getmgtframe = 0x40208cf8);\r\nPROVIDE\t(ieee80211_hostap_attach = 0x4020939c);\r\nPROVIDE\t(hostap_handle_timer = 0x402094a0);\r\nPROVIDE\t(hostap_input = 0x40209538);\r\nPROVIDE\t(wifi_softap_start = 0x4020a4b8);\r\nPROVIDE\t(wifi_softap_stop = 0x4020a624);\r\nPROVIDE\t(ieee80211_ht_attach = 0x4020a7cc);\r\nPROVIDE\t(ieee80211_ht_node_init = 0x4020a820);\r\nPROVIDE\t(ieee80211_ht_node_cleanup = 0x4020a860);\r\nPROVIDE\t(ieee80211_parse_htcap = 0x4020a898);\r\nPROVIDE\t(ieee80211_ht_updateparams = 0x4020a998);\r\nPROVIDE\t(ieee80211_setup_htrates = 0x4020aab0);\r\nPROVIDE\t(ieee80211_setup_basic_htrates = 0x4020ab7c);\r\nPROVIDE\t(ieee80211_add_htcap = 0x4020aec8);\r\nPROVIDE\t(ieee80211_add_htcap_vendor = 0x4020aee4);\r\nPROVIDE\t(ieee80211_add_htinfo = 0x4020b008);\r\nPROVIDE\t(ieee80211_add_htinfo_vendor = 0x4020b024);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_head = 0x4020b264);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_mesh_assoc = 0x4020b29c);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_mesh_group = 0x4020b320);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_simple_pair = 0x4020b350);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_freq_annon = 0x4020b3a0);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_now = 0x4020b3d8);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_ssid = 0x4020b410);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_manufacturer = 0x4020b450);\r\nPROVIDE\t(ieee80211_deliver_data = 0x4020b4a0);\r\nPROVIDE\t(ieee80211_decap = 0x4020b4f4);\r\nPROVIDE\t(ieee80211_setup_rates = 0x4020b5f8);\r\nPROVIDE\t(ieee80211_alloc_challenge = 0x4020b668);\r\nPROVIDE\t(ieee80211_parse_beacon = 0x4020b6a4);\r\nPROVIDE\t(ieee80211_parse_wpa = 0x4020bc78);\r\nPROVIDE\t(ieee80211_parse_rsn = 0x4020bd8c);\r\nPROVIDE\t(ieee80211_parse_action = 0x4020be8c);\r\nPROVIDE\t(ieee80211_setup_rateset = 0x4020bf28);\r\nPROVIDE\t(ieee80211_mesh_quick_init = 0x4020bf38);\r\nPROVIDE\t(ieee80211_mesh_quick_deinit = 0x4020bfa8);\r\nPROVIDE\t(ieee80211_mesh_quick_set = 0x4020bfd8);\r\nPROVIDE\t(ieee80211_mesh_quick_get = 0x4020c0d4);\r\nPROVIDE\t(ieee80211_mesh_quick_ie_add = 0x4020c1a0);\r\nPROVIDE\t(ieee80211_output_pbuf = 0x4020c1d8);\r\nPROVIDE\t(ieee80211_send_setup = 0x4020c448);\r\nPROVIDE\t(ieee80211_mgmt_output = 0x4020c57c);\r\nPROVIDE\t(ieee80211_tx_mgt_cb = 0x4020c660);\r\nPROVIDE\t(ieee80211_send_nulldata = 0x4020c668);\r\nPROVIDE\t(ieee80211_add_rates = 0x4020cad4);\r\nPROVIDE\t(ieee80211_add_xrates = 0x4020cb24);\r\nPROVIDE\t(ieee80211_send_probereq = 0x4020cbf4);\r\nPROVIDE\t(ieee80211_getcapinfo = 0x4020ce08);\r\nPROVIDE\t(ieee80211_send_mgmt = 0x4020ce68);\r\nPROVIDE\t(ieee80211_alloc_proberesp = 0x4020d410);\r\nPROVIDE\t(ieee80211_send_proberesp = 0x4020d5ec);\r\nPROVIDE\t(ieee80211_alloc_deauth = 0x4020d734);\r\nPROVIDE\t(ieee80211_send_deauth = 0x4020d774);\r\nPROVIDE\t(ieee80211_freedom_output = 0x4020d8b0);\r\nPROVIDE\t(ieee80211_beacon_alloc = 0x4020dc98);\r\nPROVIDE\t(ieee80211_phy_init = 0x4020de30);\r\nPROVIDE\t(ieee80211_phy_type_get = 0x4020de64);\r\nPROVIDE\t(ieee80211_setup_ratetable = 0x4020de80);\r\nPROVIDE\t(ieee80211_psq_init = 0x4020df10);\r\nPROVIDE\t(ieee80211_psq_cleanup = 0x4020df30);\r\nPROVIDE\t(ieee80211_set_tim = 0x4020df38);\r\nPROVIDE\t(ieee80211_pwrsave = 0x4020df78);\r\nPROVIDE\t(pwrsave_flushq = 0x4020dfe0);\r\nPROVIDE\t(ieee80211_node_pwrsave = 0x4020e090);\r\nPROVIDE\t(ieee80211_proto_attach = 0x4020e0cc);\r\nPROVIDE\t(ieee80211_set_shortslottime = 0x4020e0f4);\r\nPROVIDE\t(ieee80211_iserp_rateset = 0x4020e110);\r\nPROVIDE\t(ieee80211_wme_initparams = 0x4020e144);\r\nPROVIDE\t(ieee80211_wme_updateparams = 0x4020e148);\r\nPROVIDE\t(ieee80211_mlme_connect_bss = 0x4020e150);\r\nPROVIDE\t(ieee80211_rfid_locp_recv_open = 0x4020e1d0);\r\nPROVIDE\t(ieee80211_rfid_locp_recv_close = 0x4020e20c);\r\nPROVIDE\t(ieee80211_rfid_locp_recv_reset = 0x4020e224);\r\nPROVIDE\t(ieee80211_rfid_locp_recv = 0x4020e244);\r\nPROVIDE\t(register_ieee80211_rfid_locp_recv_cb = 0x4020e260);\r\nPROVIDE\t(unregister_ieee80211_rfid_locp_recv_cb = 0x4020e274);\r\nPROVIDE\t(ieee80211_scan_attach = 0x4020e28c);\r\nPROVIDE\t(scan_start = 0x4020e320);\r\nPROVIDE\t(scan_pm_channel_op_cb = 0x4020e4e4);\r\nPROVIDE\t(scan_cancel = 0x4020e684);\r\nPROVIDE\t(scan_add_bssid = 0x4020e7e0);\r\nPROVIDE\t(scan_remove_bssid = 0x4020e804);\r\nPROVIDE\t(scan_hidden_ssid = 0x4020e810);\r\nPROVIDE\t(scan_add_probe_ssid = 0x4020e818);\r\nPROVIDE\t(scan_remove_probe_ssid = 0x4020e86c);\r\nPROVIDE\t(scan_clear_channles = 0x4020e9ac);\r\nPROVIDE\t(scan_set_desChan = 0x4020ea20);\r\nPROVIDE\t(scan_get_type = 0x4020ea2c);\r\nPROVIDE\t(cannel_scan_connect_state = 0x4020ea34);\r\nPROVIDE\t(scan_connect_state = 0x4020ea4c);\r\nPROVIDE\t(scan_check_hidden = 0x4020ea94);\r\nPROVIDE\t(scan_profile_check = 0x4020eac8);\r\nPROVIDE\t(scan_parse_beacon = 0x4020ee74);\r\nPROVIDE\t(sta_status_set = 0x4020f244);\r\nPROVIDE\t(ieee80211_sta_new_state = 0x4020f2b0);\r\nPROVIDE\t(sta_input = 0x4020f640);\r\nPROVIDE\t(ieee80211_parse_wmeparams = 0x4020fb8c);\r\nPROVIDE\t(wifi_station_start = 0x40210188);\r\nPROVIDE\t(wifi_station_stop = 0x402101f8);\r\nPROVIDE\t(ic_get_addr = 0x40210254);\r\nPROVIDE\t(ic_set_opmode = 0x40210260);\r\nPROVIDE\t(ic_enable_interface = 0x40210274);\r\nPROVIDE\t(ic_interface_enabled = 0x402102c4);\r\nPROVIDE\t(ic_disable_interface = 0x402102d8);\r\nPROVIDE\t(ic_is_pure_sta = 0x40210320);\r\nPROVIDE\t(ic_get_ptk_alg = 0x4021033c);\r\nPROVIDE\t(ic_get_gtk_alg = 0x4021034c);\r\nPROVIDE\t(ic_set_ptk_alg = 0x4021035c);\r\nPROVIDE\t(ic_set_gtk_alg = 0x4021036c);\r\nPROVIDE\t(ic_interface_is_p2p = 0x4021037c);\r\nPROVIDE\t(ic_set_vif = 0x40210414);\r\nPROVIDE\t(ic_set_sta = 0x402104d4);\r\nPROVIDE\t(ic_bss_info_update = 0x402105ac);\r\nPROVIDE\t(ic_set_key = 0x40210608);\r\nPROVIDE\t(ic_remove_key = 0x40210664);\r\nPROVIDE\t(ic_get_rssi = 0x40210678);\r\nPROVIDE\t(lwip_init = 0x402106b4);\r\nPROVIDE\t(ip_route = 0x402106f4);\r\nPROVIDE\t(ip_input = 0x4021077c);\r\nPROVIDE\t(ip_output_if_opt = 0x402109e0);\r\nPROVIDE\t(ip_output_if = 0x40210bf4);\r\nPROVIDE\t(ip_output = 0x40210c1c);\r\nPROVIDE\t(ip_router = 0x40210c6c);\r\nPROVIDE\t(ip4_addr_isbroadcast = 0x40210cc8);\r\nPROVIDE\t(ip4_addr_netmask_valid = 0x40210d08);\r\nPROVIDE\t(ipaddr_aton = 0x40210d54);\r\nPROVIDE\t(ipaddr_addr = 0x40210f40);\r\nPROVIDE\t(ipaddr_ntoa_r = 0x40210f5c);\r\nPROVIDE\t(ipaddr_ntoa = 0x40211030);\r\nPROVIDE\t(lmacInitAc = 0x40211048);\r\nPROVIDE\t(lmacInit = 0x4021107c);\r\nPROVIDE\t(lmacSetRetryLimit = 0x4021112c);\r\nPROVIDE\t(prvHeapInit = 0x40211164);\r\nPROVIDE\t(netif_init = 0x402111a4);\r\nPROVIDE\t(netif_find = 0x402111a8);\r\nPROVIDE\t(netif_set_default = 0x402111e0);\r\nPROVIDE\t(netif_set_ipaddr = 0x402111f0);\r\nPROVIDE\t(netif_set_addr = 0x4021125c);\r\nPROVIDE\t(netif_add = 0x40211294);\r\nPROVIDE\t(netif_set_netmask = 0x40211304);\r\nPROVIDE\t(netif_set_gw = 0x40211310);\r\nPROVIDE\t(netif_set_up = 0x4021131c);\r\nPROVIDE\t(netif_set_down = 0x4021135c);\r\nPROVIDE\t(netif_remove = 0x40211380);\r\nPROVIDE\t(netif_set_link_up = 0x402113e4);\r\nPROVIDE\t(netif_set_link_down = 0x40211434);\r\nPROVIDE\t(_sprintf_out = 0x4021144c);\r\nPROVIDE\t(__wrap_os_printf_plus = 0x4021148c);\r\nPROVIDE\t(ets_sprintf = 0x402114f0);\r\nPROVIDE\t(pbuf_header = 0x4021153c);\r\nPROVIDE\t(pbuf_ref = 0x402115cc);\r\nPROVIDE\t(pbuf_free = 0x402115d8);\r\nPROVIDE\t(pbuf_alloc = 0x40211640);\r\nPROVIDE\t(pbuf_realloc = 0x402117a4);\r\nPROVIDE\t(pbuf_clen = 0x402117f4);\r\nPROVIDE\t(pbuf_cat = 0x40211808);\r\nPROVIDE\t(pbuf_chain = 0x40211834);\r\nPROVIDE\t(pbuf_dechain = 0x40211850);\r\nPROVIDE\t(pbuf_copy = 0x40211884);\r\nPROVIDE\t(pbuf_copy_partial = 0x40211950);\r\nPROVIDE\t(pbuf_take = 0x40211a00);\r\nPROVIDE\t(pbuf_coalesce = 0x40211a7c);\r\nPROVIDE\t(pbuf_get_at = 0x40211abc);\r\nPROVIDE\t(pbuf_memcmp = 0x40211ae0);\r\nPROVIDE\t(pbuf_memfind = 0x40211b54);\r\nPROVIDE\t(pbuf_strstr = 0x40211bb8);\r\nPROVIDE\t(rf_init = 0x40211c04);\r\nPROVIDE\t(bb_init = 0x40211c20);\r\nPROVIDE\t(phy_init = 0x40211c38);\r\nPROVIDE\t(RFChannelSel = 0x40211c68);\r\nPROVIDE\t(phy_delete_channel = 0x40211c84);\r\nPROVIDE\t(phy_enable_agc = 0x40211c9c);\r\nPROVIDE\t(phy_disable_agc = 0x40211cb4);\r\nPROVIDE\t(phy_initialize_bb = 0x40211ccc);\r\nPROVIDE\t(phy_set_sense = 0x40211ce4);\r\nPROVIDE\t(ram_tx_mac_enable = 0x40211cfc);\r\nPROVIDE\t(ram_tx_mac_disable = 0x40211d00);\r\nPROVIDE\t(rtc_mem_backup = 0x40211d04);\r\nPROVIDE\t(rtc_mem_recovery = 0x40211d34);\r\nPROVIDE\t(set_cal_rxdc = 0x40211d68);\r\nPROVIDE\t(set_rx_gain_cal_iq = 0x40211e20);\r\nPROVIDE\t(gen_rx_gain_table = 0x40212178);\r\nPROVIDE\t(pbus_set_rxbbgain = 0x402122d0);\r\nPROVIDE\t(set_rx_gain_testchip_50 = 0x40212354);\r\nPROVIDE\t(ram_get_corr_power = 0x4021268c);\r\nPROVIDE\t(check_data_func = 0x4021277c);\r\nPROVIDE\t(do_noisefloor_lsleep_v50 = 0x4021279c);\r\nPROVIDE\t(do_noisefloor = 0x402127d0);\r\nPROVIDE\t(start_dig_rx = 0x40212844);\r\nPROVIDE\t(stop_dig_rx = 0x4021288c);\r\nPROVIDE\t(chip_v6_set_chanfreq = 0x402128b8);\r\nPROVIDE\t(tx_cap_init = 0x402128e8);\r\nPROVIDE\t(target_power_add_backoff = 0x40212a9c);\r\nPROVIDE\t(tx_pwctrl_init_cal = 0x40212aec);\r\nPROVIDE\t(tx_atten_set_interp = 0x40212c54);\r\nPROVIDE\t(tx_pwctrl_init = 0x40212ec4);\r\nPROVIDE\t(ram_get_noisefloor = 0x40212fb8);\r\nPROVIDE\t(get_noisefloor_sat = 0x40212fd4);\r\nPROVIDE\t(ram_set_noise_floor = 0x40213004);\r\nPROVIDE\t(ram_start_noisefloor = 0x40213060);\r\nPROVIDE\t(read_hw_noisefloor = 0x402130ac);\r\nPROVIDE\t(noise_check_loop = 0x402130d8);\r\nPROVIDE\t(noise_init = 0x40213230);\r\nPROVIDE\t(target_power_backoff = 0x40213430);\r\nPROVIDE\t(sdt_on_noise_start = 0x40213484);\r\nPROVIDE\t(chip_v6_set_chan_rx_cmp = 0x40213504);\r\nPROVIDE\t(chip_v6_set_chan_misc = 0x40213690);\r\nPROVIDE\t(phy_dig_spur_set = 0x40213734);\r\nPROVIDE\t(phy_dig_spur_prot = 0x40213a8c);\r\nPROVIDE\t(chip_v6_rxmax_ext_dig = 0x40213cc4);\r\nPROVIDE\t(chip_v6_rxmax_ext = 0x40213d10);\r\nPROVIDE\t(phy_bb_rx_cfg = 0x40213dc0);\r\nPROVIDE\t(uart_wait_idle = 0x402141c8);\r\nPROVIDE\t(phy_pbus_soc_cfg = 0x40214204);\r\nPROVIDE\t(phy_gpio_cfg = 0x402142c4);\r\nPROVIDE\t(tx_cont_en = 0x4021460c);\r\nPROVIDE\t(tx_cont_dis = 0x402146b4);\r\nPROVIDE\t(tx_cont_cfg = 0x40214708);\r\nPROVIDE\t(chip_v6_initialize_bb = 0x40214728);\r\nPROVIDE\t(periodic_cal = 0x4021488c);\r\nPROVIDE\t(bbpll_cal = 0x40214970);\r\nPROVIDE\t(periodic_cal_top = 0x40214a08);\r\nPROVIDE\t(register_chipv6_phy_init_param = 0x40214a68);\r\nPROVIDE\t(change_bbpll160_sleep = 0x40214d14);\r\nPROVIDE\t(change_bbpll160 = 0x40214e40);\r\nPROVIDE\t(set_crystal_uart = 0x40214e78);\r\nPROVIDE\t(ant_switch_init = 0x40214f0c);\r\nPROVIDE\t(reduce_current_init = 0x40214fb8);\r\nPROVIDE\t(rtc_mem_check = 0x40215020);\r\nPROVIDE\t(phy_afterwake_set_rfoption = 0x4021505c);\r\nPROVIDE\t(deep_sleep_set_option = 0x4021507c);\r\nPROVIDE\t(write_data_to_rtc = 0x402150a8);\r\nPROVIDE\t(get_data_from_rtc = 0x402150e0);\r\nPROVIDE\t(register_chipv6_phy = 0x40215170);\r\nPROVIDE\t(set_dpd_bypass = 0x40215580);\r\nPROVIDE\t(set_rf_gain_stage10 = 0x402155a8);\r\nPROVIDE\t(get_vdd33_offset = 0x402155d8);\r\nPROVIDE\t(get_phy_target_power = 0x4021564c);\r\nPROVIDE\t(set_most_pwr_reg = 0x40215700);\r\nPROVIDE\t(phy_set_most_tpw = 0x402157d4);\r\nPROVIDE\t(phy_vdd33_set_tpw = 0x402157f4);\r\nPROVIDE\t(get_adc_rand = 0x4021580c);\r\nPROVIDE\t(phy_get_rand = 0x4021583c);\r\nPROVIDE\t(phy_tx_pwctrl_cali = 0x40215854);\r\nPROVIDE\t(phy_check_data_table = 0x4021587c);\r\nPROVIDE\t(phy_after_init_enrx = 0x402158bc);\r\nPROVIDE\t(phy_set_rx11b_reg = 0x40215920);\r\nPROVIDE\t(phy_set_powerup_option = 0x40215954);\r\nPROVIDE\t(ram_pbus_set_rxgain = 0x40215960);\r\nPROVIDE\t(ram_pbus_debugmode = 0x40215a28);\r\nPROVIDE\t(ram_pbus_xpd_tx_on = 0x40215adc);\r\nPROVIDE\t(set_rf_freq_offset = 0x40215b48);\r\nPROVIDE\t(chip_v6_rxmax_ext_ana = 0x40215bb8);\r\nPROVIDE\t(ram_chip_v6_rx_init = 0x40215d0c);\r\nPROVIDE\t(tsen_meas = 0x40215d3c);\r\nPROVIDE\t(readvdd33 = 0x40215de8);\r\nPROVIDE\t(txpwr_offset = 0x40215fac);\r\nPROVIDE\t(set_txcap_reg = 0x40216068);\r\nPROVIDE\t(ram_ana_inf_gating_en = 0x402160e8);\r\nPROVIDE\t(ram_restart_cal = 0x40216248);\r\nPROVIDE\t(wait_rfpll_cal_end = 0x402162b4);\r\nPROVIDE\t(ram_rfpll_set_freq = 0x4021633c);\r\nPROVIDE\t(ram_set_channel_freq = 0x40216440);\r\nPROVIDE\t(chip_60_set_channel = 0x40216738);\r\nPROVIDE\t(chip_v6_set_chan_offset = 0x402168c8);\r\nPROVIDE\t(chip_v6_set_chan = 0x40216904);\r\nPROVIDE\t(chip_v6_set_chan_wakeup = 0x40216994);\r\nPROVIDE\t(chip_v6_rf_init = 0x40216a08);\r\nPROVIDE\t(low_power_set = 0x40216c2c);\r\nPROVIDE\t(test_tout = 0x40216c7c);\r\nPROVIDE\t(check_data_flag = 0x40216df4);\r\nPROVIDE\t(phy_get_check_flag = 0x40216e14);\r\nPROVIDE\t(phy_get_vdd33 = 0x40216f48);\r\nPROVIDE\t(txbbgain2dcoindex = 0x40216ffc);\r\nPROVIDE\t(dcoindex2txbbgain = 0x4021701c);\r\nPROVIDE\t(init_cal_dcoffset = 0x40217040);\r\nPROVIDE\t(set_rfanagain_dc_reg = 0x40217104);\r\nPROVIDE\t(set_txdc_pbus = 0x402171a0);\r\nPROVIDE\t(get_rf_gain_qdb = 0x4021720c);\r\nPROVIDE\t(correct_rf_ana_gain = 0x40217234);\r\nPROVIDE\t(get_sar_dout = 0x4021733c);\r\nPROVIDE\t(cal_rf_ana_gain = 0x402173d4);\r\nPROVIDE\t(meas_tone_pwr_db = 0x402174ac);\r\nPROVIDE\t(tx_pwr_backoff = 0x4021751c);\r\nPROVIDE\t(get_fcc_1m2m_pwr_offset = 0x40217668);\r\nPROVIDE\t(ram_set_txbb_atten = 0x402176a4);\r\nPROVIDE\t(txiq_get_mis_pwr = 0x40217738);\r\nPROVIDE\t(txiq_cover = 0x402177dc);\r\nPROVIDE\t(ram_rfcal_txiq = 0x402179f4);\r\nPROVIDE\t(rc_cal = 0x40217c60);\r\nPROVIDE\t(get_target_power_offset = 0x40217e20);\r\nPROVIDE\t(get_pwctrl_correct = 0x40217f28);\r\nPROVIDE\t(tx_pwctrl_cal = 0x40217f84);\r\nPROVIDE\t(tx_pwctrl_bg_init = 0x40218314);\r\nPROVIDE\t(tx_pwctrl_background = 0x4021838c);\r\nPROVIDE\t(read_sar_dout = 0x40218468);\r\nPROVIDE\t(ram_get_fm_sar_dout = 0x402184cc);\r\nPROVIDE\t(ram_cal_tos_v60 = 0x40218570);\r\nPROVIDE\t(ram_get_bb_atten = 0x40218750);\r\nPROVIDE\t(ram_rfcal_txcap = 0x40218780);\r\nPROVIDE\t(ram_rfcal_pwrctrl = 0x40218944);\r\nPROVIDE\t(ram_rxiq_get_mis = 0x40218b60);\r\nPROVIDE\t(ram_rxiq_cover_mg_mp = 0x40218d2c);\r\nPROVIDE\t(ram_rfcal_rxiq = 0x40218ed0);\r\nPROVIDE\t(dpd_scale_set = 0x402190dc);\r\nPROVIDE\t(dpd_mem_write = 0x40219124);\r\nPROVIDE\t(pm_usec2rtc = 0x402191a0);\r\nPROVIDE\t(pm_rtc2usec = 0x402191d4);\r\nPROVIDE\t(pm_set_sleep_cycles = 0x402191e0);\r\nPROVIDE\t(pm_sleep_opt = 0x40219208);\r\nPROVIDE\t(pm_wakeup_opt = 0x40219320);\r\nPROVIDE\t(get_chip_version = 0x40219358);\r\nPROVIDE\t(pm_sleep_opt_bb_off = 0x40219398);\r\nPROVIDE\t(pm_sleep_opt_bb_on = 0x402193d8);\r\nPROVIDE\t(pm_set_pll_xtal_wait_time = 0x40219424);\r\nPROVIDE\t(pm_prepare_to_sleep = 0x4021946c);\r\nPROVIDE\t(pm_sdio_nidle = 0x40219490);\r\nPROVIDE\t(chg_lslp_mem_opt_8266 = 0x40219504);\r\nPROVIDE\t(pm_goto_sleep = 0x40219534);\r\nPROVIDE\t(pm_wait4wakeup = 0x40219680);\r\nPROVIDE\t(pm_open_rf = 0x402196bc);\r\nPROVIDE\t(pm_sleep_set_mac = 0x40219700);\r\nPROVIDE\t(pm_set_wakeup_mac = 0x40219784);\r\nPROVIDE\t(pm_check_mac_idle = 0x40219820);\r\nPROVIDE\t(pm_set_sleep_btco = 0x40219878);\r\nPROVIDE\t(pm_set_wakeup_btco = 0x40219918);\r\nPROVIDE\t(pm_set_sleep_mode = 0x40219a30);\r\nPROVIDE\t(pm_unmask_bt = 0x40219b4c);\r\nPROVIDE\t(pm_wakeup_init = 0x40219bb4);\r\nPROVIDE\t(sleep_opt_8266 = 0x40219dc4);\r\nPROVIDE\t(sleep_opt_bb_on_8266 = 0x40219de4);\r\nPROVIDE\t(sleep_reset_analog_rtcreg_8266 = 0x40219e20);\r\nPROVIDE\t(pm_rtc_clock_cali_proc = 0x40219f2c);\r\nPROVIDE\t(pm_get_ck170_period = 0x40219f64);\r\nPROVIDE\t(pm_set_sleep_time = 0x40219f88);\r\nPROVIDE\t(pm_rf_is_closed = 0x4021a2ec);\r\nPROVIDE\t(pm_set_sleep_type_from_upper = 0x4021a318);\r\nPROVIDE\t(pm_get_sleep_type = 0x4021a408);\r\nPROVIDE\t(uart_tx_flush = 0x4021a58c);\r\nPROVIDE\t(pm_suspend = 0x4021a590);\r\nPROVIDE\t(pm_shutdown = 0x4021a7a8);\r\nPROVIDE\t(pm_reset_idle_sleep = 0x4021a870);\r\nPROVIDE\t(pm_idle_sleep = 0x4021a8b0);\r\nPROVIDE\t(pm_open = 0x4021a8bc);\r\nPROVIDE\t(pm_onBcnRx = 0x4021a984);\r\nPROVIDE\t(StopLightSleepSetFunc = 0x4021acec);\r\nPROVIDE\t(LightSleepWakedCbSetFunc = 0x4021acf4);\r\nPROVIDE\t(pm_enable_gpio_wakeup = 0x4021b1f4);\r\nPROVIDE\t(pm_attach = 0x4021b22c);\r\nPROVIDE\t(pm_send_nullfunc = 0x4021b310);\r\nPROVIDE\t(pm_is_waked = 0x4021b498);\r\nPROVIDE\t(pm_is_open = 0x4021b4b0);\r\nPROVIDE\t(pm_scan_lock = 0x4021b4c8);\r\nPROVIDE\t(pm_try_scan_unlock = 0x4021b4f0);\r\nPROVIDE\t(pm_force_scan_unlock = 0x4021b508);\r\nPROVIDE\t(pm_scan_unlocked = 0x4021b584);\r\nPROVIDE\t(pm_allow_tx = 0x4021b598);\r\nPROVIDE\t(pm_assoc_parse = 0x4021b5b4);\r\nPROVIDE\t(pm_set_addr = 0x4021b5cc);\r\nPROVIDE\t(pm_sleep_for = 0x4021b5ec);\r\nPROVIDE\t(pm_post = 0x4021b61c);\r\nPROVIDE\t(pm_get_idle_wait_time = 0x4021b720);\r\nPROVIDE\t(fpm_set_type_from_upper = 0x4021b778);\r\nPROVIDE\t(wifi_fpm_set_sleep_type = 0x4021b778);\r\nPROVIDE\t(fpm_get_slp_type = 0x4021b834);\r\nPROVIDE\t(wifi_fpm_get_sleep_type = 0x4021b834);\r\nPROVIDE\t(fpm_rf_is_closed = 0x4021b83c);\r\nPROVIDE\t(fpm_is_open = 0x4021b850);\r\nPROVIDE\t(fpm_allow_tx = 0x4021b85c);\r\nPROVIDE\t(fpm_close = 0x4021b880);\r\nPROVIDE\t(wifi_fpm_close = 0x4021b880);\r\nPROVIDE\t(fpm_open = 0x4021b8fc);\r\nPROVIDE\t(wifi_fpm_open = 0x4021b8fc);\r\nPROVIDE\t(fpm_attach = 0x4021b964);\r\nPROVIDE\t(fpm_set_wakeup_cb = 0x4021bb48);\r\nPROVIDE\t(wifi_fpm_set_wakeup_cb = 0x4021bb48);\r\nPROVIDE\t(fpm_do_wakeup = 0x4021bcbc);\r\nPROVIDE\t(wifi_fpm_do_wakeup = 0x4021bcbc);\r\nPROVIDE\t(fpm_do_sleep = 0x4021c17c);\r\nPROVIDE\t(wifi_fpm_do_sleep = 0x4021c17c);\r\nPROVIDE\t(PPWdtReset = 0x4021c204);\r\nPROVIDE\t(pp_soft_wdt_init = 0x4021c238);\r\nPROVIDE\t(pp_soft_wdt_feed = 0x4021c258);\r\nPROVIDE\t(system_soft_wdt_feed = 0x4021c258);\r\nPROVIDE\t(pp_soft_wdt_stop = 0x4021c274);\r\nPROVIDE\t(system_soft_wdt_stop = 0x4021c274);\r\nPROVIDE\t(pp_soft_wdt_restart = 0x4021c2a0);\r\nPROVIDE\t(system_soft_wdt_restart = 0x4021c2a0);\r\nPROVIDE\t(RxNodeNum = 0x4021c2d8);\r\nPROVIDE\t(TxNodeNum = 0x4021c2f0);\r\nPROVIDE\t(pp_disable_noise_timer = 0x4021c314);\r\nPROVIDE\t(pp_enable_noise_timer = 0x4021c334);\r\nPROVIDE\t(pp_noise_test = 0x4021c444);\r\nPROVIDE\t(reset_noise_timer = 0x4021c454);\r\nPROVIDE\t(pp_disable_idle_timer = 0x4021c48c);\r\nPROVIDE\t(pp_enable_idle_timer = 0x4021c4b0);\r\nPROVIDE\t(pp_try_enable_idle_timer = 0x4021c4d8);\r\nPROVIDE\t(ppPeocessRxPktHdr = 0x4021c514);\r\nPROVIDE\t(HdlAllBuffedEb = 0x4021c848);\r\nPROVIDE\t(ppTxPkt = 0x4021c8d0);\r\nPROVIDE\t(ppProcessWaitQ = 0x4021ca48);\r\nPROVIDE\t(ppRegisterTxCallback = 0x4021ca58);\r\nPROVIDE\t(ppUnregisterTxCallback = 0x4021ca80);\r\nPROVIDE\t(ppRecycleRxPkt = 0x4021cab4);\r\nPROVIDE\t(ppCheckTxIdle = 0x4021cb14);\r\nPROVIDE\t(pp_tx_idle_timeout = 0x4021cd8c);\r\nPROVIDE\t(DefFreqCalTimerCB = 0x4021cf40);\r\nPROVIDE\t(ppGetTxQFirstAvail_Locked = 0x4021d2b4);\r\nPROVIDE\t(pp_attach = 0x4021d390);\r\nPROVIDE\t(RC_SetBasicRate = 0x4021d9e4);\r\nPROVIDE\t(raw_new = 0x4021da34);\r\nPROVIDE\t(raw_remove = 0x4021da7c);\r\nPROVIDE\t(raw_bind = 0x4021dab0);\r\nPROVIDE\t(raw_connect = 0x4021dabc);\r\nPROVIDE\t(raw_recv = 0x4021dac8);\r\nPROVIDE\t(raw_sendto = 0x4021dad0);\r\nPROVIDE\t(raw_input = 0x4021db74);\r\nPROVIDE\t(raw_send = 0x4021dbf8);\r\nPROVIDE\t(iram_buf_init = 0x4021dc20);\r\nPROVIDE\t(spi_flash_real_size = 0x4021dc7c);\r\nPROVIDE\t(tcp_arg = 0x4021dce0);\r\nPROVIDE\t(tcp_accept = 0x4021dce4);\r\nPROVIDE\t(tcp_recv = 0x4021dce8);\r\nPROVIDE\t(tcp_sent = 0x4021dcf0);\r\nPROVIDE\t(tcp_poll = 0x4021dcf8);\r\nPROVIDE\t(tcp_err = 0x4021dd00);\r\nPROVIDE\t(tcp_bind = 0x4021dd14);\r\nPROVIDE\t(tcp_listen_with_backlog = 0x4021ddb8);\r\nPROVIDE\t(tcp_setprio = 0x4021de7c);\r\nPROVIDE\t(tcp_update_rcv_ann_wnd = 0x4021de84);\r\nPROVIDE\t(tcp_recved = 0x4021decc);\r\nPROVIDE\t(tcp_seg_free = 0x4021df1c);\r\nPROVIDE\t(tcp_segs_free = 0x4021df44);\r\nPROVIDE\t(tcp_pcb_purge = 0x4021df64);\r\nPROVIDE\t(tcp_slowtmr = 0x4021dfc0);\r\nPROVIDE\t(tcp_pcb_remove = 0x4021e23c);\r\nPROVIDE\t(tcp_close = 0x4021e2ac);\r\nPROVIDE\t(tcp_recv_null = 0x4021e2d4);\r\nPROVIDE\t(tcp_fasttmr = 0x4021e30c);\r\nPROVIDE\t(tcp_tmr = 0x4021e3a0);\r\nPROVIDE\t(tcp_shutdown = 0x4021e3c4);\r\nPROVIDE\t(tcp_abandon = 0x4021e424);\r\nPROVIDE\t(tcp_abort = 0x4021e4b4);\r\nPROVIDE\t(tcp_next_iss = 0x4021e4cc);\r\nPROVIDE\t(tcp_alloc = 0x4021e4ec);\r\nPROVIDE\t(tcp_new = 0x4021e60c);\r\nPROVIDE\t(tcp_eff_send_mss = 0x4021e620);\r\nPROVIDE\t(tcp_connect = 0x4021e654);\r\nPROVIDE\t(tcp_receive = 0x4021e784);\r\nPROVIDE\t(tcp_input = 0x4021ed10);\r\nPROVIDE\t(tcp_create_segment = 0x4021f68c);\r\nPROVIDE\t(tcp_write = 0x4021f87c);\r\nPROVIDE\t(tcp_send_empty_ack = 0x4021fb8c);\r\nPROVIDE\t(tcp_rexmit = 0x4021fc1c);\r\nPROVIDE\t(tcp_rexmit_fast = 0x4021fcd4);\r\nPROVIDE\t(tcp_enqueue_flags = 0x4021fd38);\r\nPROVIDE\t(tcp_send_fin = 0x4021fe04);\r\nPROVIDE\t(tcp_rst = 0x4021fe50);\r\nPROVIDE\t(tcp_keepalive = 0x4021ff84);\r\nPROVIDE\t(tcp_zero_window_probe = 0x40220004);\r\nPROVIDE\t(tcp_output = 0x40220114);\r\nPROVIDE\t(tcp_rexmit_rto = 0x4022053c);\r\nPROVIDE\t(sys_timeout = 0x402205c4);\r\nPROVIDE\t(sys_timeouts_init = 0x40220668);\r\nPROVIDE\t(tcpip_tcp_timer = 0x402206d8);\r\nPROVIDE\t(arp_timer = 0x4022070c);\r\nPROVIDE\t(sys_untimeout = 0x40220728);\r\nPROVIDE\t(sys_check_timeouts = 0x4022077c);\r\nPROVIDE\t(sys_restart_timeouts = 0x402207f8);\r\nPROVIDE\t(tcp_timer_needed = 0x40220804);\r\nPROVIDE\t(phytype2mode = 0x40220834);\r\nPROVIDE\t(rc_set_rate_limit_id = 0x40220850);\r\nPROVIDE\t(rcUpdatePhyMode = 0x4022096c);\r\nPROVIDE\t(rcAttach = 0x40220b38);\r\nPROVIDE\t(rcGetTrc = 0x40220b84);\r\nPROVIDE\t(trc_onDisconnect = 0x40220b8c);\r\nPROVIDE\t(trc_onScanStart = 0x40220b90);\r\nPROVIDE\t(trc_onScanDone = 0x40220ba4);\r\nPROVIDE\t(rc_enable_trc = 0x40220bc0);\r\nPROVIDE\t(rc_get_mask = 0x40220c98);\r\nPROVIDE\t(rc_disable_trc = 0x40220cac);\r\nPROVIDE\t(rc_disable_trc_by_interface = 0x40220d00);\r\nPROVIDE\t(rc_get_sta_trc = 0x40220d1c);\r\nPROVIDE\t(rc_get_trc = 0x40220d60);\r\nPROVIDE\t(rc_get_trc_by_index = 0x40220dd0);\r\nPROVIDE\t(rc_only_sta_trc = 0x40220df0);\r\nPROVIDE\t(udp_new = 0x40220e20);\r\nPROVIDE\t(udp_remove = 0x40220e54);\r\nPROVIDE\t(udp_bind = 0x40220e8c);\r\nPROVIDE\t(udp_connect = 0x40220f30);\r\nPROVIDE\t(udp_disconnect = 0x40220f98);\r\nPROVIDE\t(udp_recv = 0x40220fac);\r\nPROVIDE\t(udp_sendto_if = 0x40220fb4);\r\nPROVIDE\t(udp_sendto = 0x402210fc);\r\nPROVIDE\t(udp_send = 0x40221148);\r\nPROVIDE\t(udp_input = 0x40221160);\r\nPROVIDE\t(system_set_os_print = 0x40221344);\r\nPROVIDE\t(system_get_os_print = 0x40221354);\r\nPROVIDE\t(system_pp_recycle_rx_pkt = 0x4022151c);\r\nPROVIDE\t(system_adc_read = 0x40221530);\r\nPROVIDE\t(system_get_vdd33 = 0x40221548);\r\nPROVIDE\t(system_restart_hook = 0x40221560);\r\nPROVIDE\t(system_restart_local = 0x40221574);\r\nPROVIDE\t(system_restart = 0x4022165c);\r\nPROVIDE\t(system_restore = 0x402216b4);\r\nPROVIDE\t(system_get_flash_size_map = 0x4022171c);\r\nPROVIDE\t(system_get_boot_version = 0x4022173c);\r\nPROVIDE\t(system_get_test_result = 0x40221774);\r\nPROVIDE\t(system_get_userbin_addr = 0x40221798);\r\nPROVIDE\t(system_get_boot_mode = 0x40221830);\r\nPROVIDE\t(system_restart_enhance = 0x40221860);\r\nPROVIDE\t(system_upgrade_userbin_set = 0x40221990);\r\nPROVIDE\t(system_upgrade_userbin_check = 0x402219dc);\r\nPROVIDE\t(system_upgrade_flag_set = 0x40221a1c);\r\nPROVIDE\t(system_upgrade_flag_check = 0x40221a30);\r\nPROVIDE\t(system_upgrade_reboot = 0x40221a54);\r\nPROVIDE\t(system_deep_sleep_instant = 0x40221b70);\r\nPROVIDE\t(system_deep_sleep = 0x40221d10);\r\nPROVIDE\t(system_deep_sleep_set_option = 0x40221d70);\r\nPROVIDE\t(system_phy_temperature_alert = 0x40221d8c);\r\nPROVIDE\t(system_phy_set_max_tpw = 0x40221da0);\r\nPROVIDE\t(system_phy_set_tpw_via_vdd33 = 0x40221db4);\r\nPROVIDE\t(system_phy_set_rfoption = 0x40221dc8);\r\nPROVIDE\t(system_phy_set_powerup_option = 0x40221ddc);\r\nPROVIDE\t(system_update_cpu_freq = 0x40221df0);\r\nPROVIDE\t(system_get_cpu_freq = 0x40221e4c);\r\nPROVIDE\t(system_overclock = 0x40221e64);\r\nPROVIDE\t(system_restoreclock = 0x40221e90);\r\nPROVIDE\t(system_timer_reinit = 0x40221ec0);\r\nPROVIDE\t(system_relative_time = 0x40221ed8);\r\nPROVIDE\t(system_station_got_ip_set = 0x40221ef4);\r\nPROVIDE\t(system_print_meminfo = 0x40222020);\r\nPROVIDE\t(system_get_free_heap_size = 0x40222084);\r\nPROVIDE\t(system_get_chip_id = 0x40222098);\r\nPROVIDE\t(system_rtc_clock_cali_proc = 0x402220bc);\r\nPROVIDE\t(system_get_rtc_time = 0x402220d0);\r\nPROVIDE\t(system_mktime = 0x402220e0);\r\nPROVIDE\t(system_init_done_cb = 0x402221b0);\r\nPROVIDE\t(system_get_rst_info = 0x402221b8);\r\nPROVIDE\t(system_get_data_of_array_8 = 0x402221c0);\r\nPROVIDE\t(system_get_data_of_array_16 = 0x402221e4);\r\nPROVIDE\t(system_get_string_from_flash = 0x4022220c);\r\nPROVIDE\t(wifi_softap_dhcps_start = 0x40222278);\r\nPROVIDE\t(wifi_softap_dhcps_stop = 0x402222c0);\r\nPROVIDE\t(wifi_softap_dhcps_status = 0x40222300);\r\nPROVIDE\t(wifi_station_dhcpc_start = 0x40222308);\r\nPROVIDE\t(wifi_station_dhcpc_stop = 0x40222360);\r\nPROVIDE\t(wifi_station_dhcpc_event = 0x402223a0);\r\nPROVIDE\t(wifi_station_dhcpc_set_maxtry = 0x40222414);\r\nPROVIDE\t(wifi_station_dhcpc_status = 0x40222424);\r\nPROVIDE\t(wifi_get_opmode = 0x4022249c);\r\nPROVIDE\t(wifi_get_opmode_default = 0x402224b0);\r\nPROVIDE\t(wifi_get_broadcast_if = 0x40222528);\r\nPROVIDE\t(wifi_set_broadcast_if = 0x40222564);\r\nPROVIDE\t(wifi_set_opmode = 0x402226c0);\r\nPROVIDE\t(wifi_set_opmode_current = 0x402226d4);\r\nPROVIDE\t(system_get_checksum = 0x402226e8);\r\nPROVIDE\t(wifi_param_save_protect_with_check = 0x4022272c);\r\nPROVIDE\t(system_param_save_with_protect = 0x402227e4);\r\nPROVIDE\t(system_save_sys_param = 0x4022288c);\r\nPROVIDE\t(system_param_load = 0x402228b8);\r\nPROVIDE\t(wifi_station_get_config = 0x402229f0);\r\nPROVIDE\t(wifi_station_get_config_default = 0x40222a04);\r\nPROVIDE\t(wifi_station_get_ap_info = 0x40222a24);\r\nPROVIDE\t(wifi_station_ap_number_set = 0x40222adc);\r\nPROVIDE\t(wifi_station_set_config = 0x40222e3c);\r\nPROVIDE\t(wifi_station_set_config_current = 0x40222e54);\r\nPROVIDE\t(wifi_station_restore_config = 0x40222e6c);\r\nPROVIDE\t(wifi_station_get_current_ap_id = 0x40222e84);\r\nPROVIDE\t(wifi_station_ap_check = 0x40222e98);\r\nPROVIDE\t(wifi_station_ap_change = 0x40222ed8);\r\nPROVIDE\t(wifi_station_scan = 0x40223004);\r\nPROVIDE\t(wifi_station_get_auto_connect = 0x40223050);\r\nPROVIDE\t(wifi_station_set_auto_connect = 0x40223064);\r\nPROVIDE\t(wifi_station_save_pmk2cache = 0x402230b4);\r\nPROVIDE\t(wifi_station_connect = 0x40223164);\r\nPROVIDE\t(wifi_station_disconnect = 0x402231f8);\r\nPROVIDE\t(wifi_station_get_connect_status = 0x402232b8);\r\nPROVIDE\t(wifi_station_set_reconnect_policy = 0x402232e8);\r\nPROVIDE\t(wifi_station_get_reconnect_policy = 0x40223300);\r\nPROVIDE\t(wifi_station_get_rssi = 0x40223308);\r\nPROVIDE\t(wifi_station_set_default_hostname = 0x40223354);\r\nPROVIDE\t(wifi_station_get_hostname = 0x402233bc);\r\nPROVIDE\t(wifi_station_set_hostname = 0x402233e8);\r\nPROVIDE\t(wifi_softap_cacl_mac = 0x40223484);\r\nPROVIDE\t(wifi_softap_set_default_ssid = 0x402234e8);\r\nPROVIDE\t(wifi_softap_get_config = 0x402236c8);\r\nPROVIDE\t(wifi_softap_get_config_default = 0x402236dc);\r\nPROVIDE\t(wifi_softap_set_config = 0x40223a24);\r\nPROVIDE\t(wifi_softap_set_config_current = 0x40223a38);\r\nPROVIDE\t(wifi_softap_set_station_info = 0x40223a4c);\r\nPROVIDE\t(wifi_softap_get_station_info = 0x40223ab8);\r\nPROVIDE\t(wifi_softap_free_station_info = 0x40223b68);\r\nPROVIDE\t(wifi_softap_get_station_num = 0x40223bb0);\r\nPROVIDE\t(wifi_softap_deauth = 0x40223c00);\r\nPROVIDE\t(wifi_softap_get_beacon_only_mode = 0x40223cb0);\r\nPROVIDE\t(wifi_softap_set_beacon_only_mode = 0x40223cc4);\r\nPROVIDE\t(wifi_register_user_ie_manufacturer_recv_cb = 0x40223d28);\r\nPROVIDE\t(wifi_unregister_user_ie_manufacturer_recv_cb = 0x40223d3c);\r\nPROVIDE\t(wifi_set_user_ie = 0x40223d6c);\r\nPROVIDE\t(wifi_get_user_ie = 0x40223e7c);\r\nPROVIDE\t(wifi_get_phy_mode = 0x40223eb0);\r\nPROVIDE\t(wifi_set_phy_mode = 0x40223eb8);\r\nPROVIDE\t(wifi_set_sleep_type = 0x40223f80);\r\nPROVIDE\t(wifi_get_sleep_type = 0x40223f9c);\r\nPROVIDE\t(wifi_get_channel = 0x40223fb0);\r\nPROVIDE\t(wifi_set_channel = 0x40223fc8);\r\nPROVIDE\t(wifi_promiscuous_set_mac = 0x40224008);\r\nPROVIDE\t(wifi_promiscuous_enable = 0x40224064);\r\nPROVIDE\t(wifi_set_promiscuous_rx_cb = 0x40224148);\r\nPROVIDE\t(wifi_get_ip_info = 0x40224154);\r\nPROVIDE\t(wifi_set_ip_info = 0x402241d4);\r\nPROVIDE\t(wifi_get_macaddr = 0x40224248);\r\nPROVIDE\t(wifi_set_macaddr = 0x402242a8);\r\nPROVIDE\t(wifi_enable_6m_rate = 0x402243c4);\r\nPROVIDE\t(wifi_get_user_fixed_rate = 0x402243cc);\r\nPROVIDE\t(wifi_set_user_fixed_rate = 0x402243ec);\r\nPROVIDE\t(wifi_set_user_sup_rate = 0x4022440c);\r\nPROVIDE\t(wifi_set_user_rate_limit = 0x40224448);\r\nPROVIDE\t(wifi_get_user_limit_rate_mask = 0x4022446c);\r\nPROVIDE\t(wifi_set_user_limit_rate_mask = 0x40224474);\r\nPROVIDE\t(wifi_register_send_pkt_freedom_cb = 0x4022448c);\r\nPROVIDE\t(wifi_unregister_send_pkt_freedom_cb = 0x402244a0);\r\nPROVIDE\t(wifi_send_pkt_freedom = 0x402244ac);\r\nPROVIDE\t(wifi_rfid_locp_recv_open = 0x402244f8);\r\nPROVIDE\t(wifi_rfid_locp_recv_close = 0x4022450c);\r\nPROVIDE\t(wifi_register_rfid_locp_recv_cb = 0x40224520);\r\nPROVIDE\t(wifi_unregister_rfid_locp_recv_cb = 0x40224534);\r\nPROVIDE\t(wifi_status_led_install = 0x4022454c);\r\nPROVIDE\t(wifi_status_led_uninstall = 0x40224580);\r\nPROVIDE\t(wifi_set_status_led_output_level = 0x402245a4);\r\nPROVIDE\t(wifi_set_event_handler_cb = 0x402245f8);\r\nPROVIDE\t(system_os_task = 0x40224640);\r\nPROVIDE\t(system_uart_swap = 0x4022467c);\r\nPROVIDE\t(system_uart_de_swap = 0x402246e0);\r\nPROVIDE\t(system_get_sdk_version = 0x40224718);\r\nPROVIDE\t(wDev_Option_Init = 0x4022472c);\r\nPROVIDE\t(wDev_Enable_Beacon_Tsf = 0x40224820);\r\nPROVIDE\t(wDev_Disable_Beacon_Tsf = 0x4022483c);\r\nPROVIDE\t(wDev_Set_Beacon_Int = 0x40224858);\r\nPROVIDE\t(wDev_Reset_TBTT = 0x40224860);\r\nPROVIDE\t(wDev_Get_Next_TBTT = 0x40224890);\r\nPROVIDE\t(wDev_Initialize = 0x40224b0c);\r\nPROVIDE\t(wDevForceAck6M = 0x40224b7c);\r\nPROVIDE\t(wDev_SetMacAddress = 0x40224b98);\r\nPROVIDE\t(wDev_SetRxPolicy = 0x40224c34);\r\nPROVIDE\t(wDev_SetBssid = 0x40224c88);\r\nPROVIDE\t(wDev_ClearBssid = 0x40224d60);\r\nPROVIDE\t(wDev_Insert_KeyEntry = 0x40224d98);\r\nPROVIDE\t(wDev_remove_KeyEntry = 0x40224e8c);\r\nPROVIDE\t(wDev_remove_KeyEntry_all_cnx = 0x40224ec8);\r\nPROVIDE\t(wDev_Crypto_Conf = 0x40224f18);\r\nPROVIDE\t(wDev_Crypto_Disable = 0x40224fb4);\r\nPROVIDE\t(wDevEnableRx = 0x40224fec);\r\nPROVIDE\t(wdev_go_sniffer = 0x40225014);\r\nPROVIDE\t(wdev_set_sniffer_addr = 0x402250f0);\r\nPROVIDE\t(wdev_exit_sniffer = 0x40225148);\r\nPROVIDE\t(wdt_init = 0x40225218);\r\nPROVIDE\t(os_print_reset_error = 0x402252a0);\r\nPROVIDE\t(chm_init = 0x40225344);\r\nPROVIDE\t(chm_acquire_lock = 0x402253a8);\r\nPROVIDE\t(chm_release_lock = 0x402253ec);\r\nPROVIDE\t(chm_start_op = 0x40225400);\r\nPROVIDE\t(chm_end_op = 0x402254a4);\r\nPROVIDE\t(chm_cancel_op = 0x402254ec);\r\nPROVIDE\t(chm_return_home_channel = 0x40225520);\r\nPROVIDE\t(chm_set_current_channel = 0x40225550);\r\nPROVIDE\t(chm_freq2index = 0x40225580);\r\nPROVIDE\t(chm_check_same_channel = 0x402255a8);\r\nPROVIDE\t(cnx_attach = 0x402255e4);\r\nPROVIDE\t(cnx_sta_connect_led_timer_cb = 0x40225624);\r\nPROVIDE\t(cnx_sta_connect_cmd = 0x40225678);\r\nPROVIDE\t(cnx_sta_scan_cmd = 0x40225734);\r\nPROVIDE\t(cnx_connect_timeout = 0x40225990);\r\nPROVIDE\t(cnx_auth_timeout = 0x40225a0c);\r\nPROVIDE\t(cnx_assoc_timeout = 0x40225a30);\r\nPROVIDE\t(cnx_handshake_timeout = 0x40225a54);\r\nPROVIDE\t(cnx_start_handoff_cb = 0x40225a94);\r\nPROVIDE\t(cnx_bss_alloc = 0x40225ef4);\r\nPROVIDE\t(cnx_rc_search = 0x40225f94);\r\nPROVIDE\t(cnx_add_rc = 0x40226014);\r\nPROVIDE\t(cnx_remove_all_rc = 0x40226080);\r\nPROVIDE\t(cnx_remove_rc = 0x402260cc);\r\nPROVIDE\t(cnx_rc_update_rssi = 0x4022619c);\r\nPROVIDE\t(cnx_rc_update_state_metric = 0x40226224);\r\nPROVIDE\t(cnx_rc_update_age = 0x40226290);\r\nPROVIDE\t(cnx_update_bss = 0x402262b4);\r\nPROVIDE\t(cnx_update_bss_more = 0x402262e8);\r\nPROVIDE\t(cnx_sta_leave = 0x402264c4);\r\nPROVIDE\t(cnx_sta_associated = 0x40226758);\r\nPROVIDE\t(cnx_node_alloc = 0x40226860);\r\nPROVIDE\t(cnx_node_remove = 0x402268d4);\r\nPROVIDE\t(cnx_node_search = 0x40226960);\r\nPROVIDE\t(cnx_node_leave = 0x402269dc);\r\nPROVIDE\t(wifi_softap_staconnected_event_policy = 0x40226adc);\r\nPROVIDE\t(wifi_softap_toomany_deny = 0x40226b04);\r\nPROVIDE\t(cnx_node_join = 0x40226b40);\r\nPROVIDE\t(wpa_sm_rx_eapol = 0x40227d28);\r\nPROVIDE\t(wpa_register = 0x40227ea0);\r\nPROVIDE\t(wpa_set_profile = 0x40227ecc);\r\nPROVIDE\t(wpa_set_pmk = 0x40227ee4);\r\nPROVIDE\t(wpa_set_bss = 0x40227f10);\r\nPROVIDE\t(pp_michael_mic_failure = 0x40228114);\r\nPROVIDE\t(eapol_txcb = 0x402281b8);\r\nPROVIDE\t(wpa_sm_set_state = 0x40228244);\r\nPROVIDE\t(wpa_auth_for_each_sta = 0x402283b8);\r\nPROVIDE\t(wpa_init = 0x40228538);\r\nPROVIDE\t(wpa_auth_sta_init = 0x402285c8);\r\nPROVIDE\t(wpa_auth_sta_associated = 0x40228610);\r\nPROVIDE\t(wpa_auth_sta_no_wpa = 0x4022867c);\r\nPROVIDE\t(wpa_auth_sta_deinit = 0x402286d8);\r\nPROVIDE\t(wpa_receive = 0x402287a8);\r\nPROVIDE\t(__wpa_send_eapol = 0x40228c08);\r\nPROVIDE\t(wpa_remove_ptk = 0x4022912c);\r\nPROVIDE\t(wpa_auth_sm_event = 0x40229178);\r\nPROVIDE\t(wpa_write_rsn_ie = 0x40229fb0);\r\nPROVIDE\t(wpa_auth_gen_wpa_ie = 0x4022a0bc);\r\nPROVIDE\t(wpa_add_kde = 0x4022a14c);\r\nPROVIDE\t(wpa_validate_wpa_ie = 0x4022a1b8);\r\nPROVIDE\t(wpa_parse_kde_ies = 0x4022a3c4);\r\nPROVIDE\t(wpa_auth_uses_mfp = 0x4022a460);\r\nPROVIDE\t(wpa_parse_wpa_ie_rsn = 0x4022a5b8);\r\nPROVIDE\t(wpa_parse_wpa_ie_wpa = 0x4022a74c);\r\nPROVIDE\t(wpa_eapol_key_mic = 0x4022a8dc);\r\nPROVIDE\t(wpa_compare_rsn_ie = 0x4022a91c);\r\nPROVIDE\t(wpa_pmk_to_ptk = 0x4022a944);\r\nPROVIDE\t(rsn_pmkid = 0x4022aa34);\r\nPROVIDE\t(wpa_cipher_key_len = 0x4022aa90);\r\nPROVIDE\t(wpa_cipher_to_alg = 0x4022aab4);\r\nPROVIDE\t(wpa_cipher_to_suite = 0x4022aadc);\r\nPROVIDE\t(rsn_cipher_put_suites = 0x4022ab30);\r\nPROVIDE\t(wpa_cipher_put_suites = 0x4022ab90);\r\nPROVIDE\t(wpa_parse_wpa_ie = 0x4022abdc);\r\nPROVIDE\t(wpa_supplicant_parse_ies = 0x4022acd0);\r\nPROVIDE\t(wpa_gen_wpa_ie = 0x4022aed0);\r\nPROVIDE\t(ppInstallKey = 0x4022af08);\r\nPROVIDE\t(wpa_config_profile = 0x4022b098);\r\nPROVIDE\t(wpa_config_bss = 0x4022b0cc);\r\nPROVIDE\t(wpa_config_assoc_ie = 0x4022b0f8);\r\nPROVIDE\t(dhcp_bind_check = 0x4022b10c);\r\nPROVIDE\t(eagle_auth_done = 0x4022b140);\r\nPROVIDE\t(wpa_neg_complete = 0x4022b2bc);\r\nPROVIDE\t(wpa_attach = 0x4022b2e4);\r\nPROVIDE\t(wpa_sm_alloc_eapol = 0x4022b38c);\r\nPROVIDE\t(wpa_sm_deauthenticate = 0x4022b3cc);\r\nPROVIDE\t(wpa_sm_mlme_setprotection = 0x4022b3e8);\r\nPROVIDE\t(wpa_sm_get_beacon_ie = 0x4022b3ec);\r\nPROVIDE\t(wpa_sm_disassociate = 0x4022b3f0);\r\nPROVIDE\t(aes_wrap = 0x4022b3f4);\r\nPROVIDE\t(hostapd_config_defaults_bss = 0x4022b4d8);\r\nPROVIDE\t(hostapd_config_defaults = 0x4022b524);\r\nPROVIDE\t(hostapd_mac_comp = 0x4022b5a8);\r\nPROVIDE\t(hostapd_mac_comp_empty = 0x4022b5bc);\r\nPROVIDE\t(hostapd_setup_wpa_psk = 0x4022b628);\r\nPROVIDE\t(hostapd_wep_key_cmp = 0x4022b658);\r\nPROVIDE\t(hostapd_maclist_found = 0x4022b6a8);\r\nPROVIDE\t(hostapd_rate_found = 0x4022b710);\r\nPROVIDE\t(hostapd_get_psk = 0x4022b72c);\r\nPROVIDE\t(inc_byte_array = 0x4022b780);\r\nPROVIDE\t(hex2byte = 0x4022b7d4);\r\nPROVIDE\t(hexstr2bin = 0x4022b808);\r\nPROVIDE\t(wpa_get_ntp_timestamp = 0x4022b854);\r\nPROVIDE\t(wpa_config_parse_string = 0x4022b8ec);\r\nPROVIDE\t(dup_binstr = 0x4022b9f0);\r\nPROVIDE\t(dhcp_set_state = 0x4022ba38);\r\nPROVIDE\t(dhcp_check = 0x4022ba50);\r\nPROVIDE\t(dhcp_option = 0x4022ba8c);\r\nPROVIDE\t(dhcp_option_byte = 0x4022baac);\r\nPROVIDE\t(dhcp_option_short = 0x4022bac0);\r\nPROVIDE\t(dhcp_option_long = 0x4022bae8);\r\nPROVIDE\t(dhcp_create_msg = 0x4022bb40);\r\nPROVIDE\t(dhcp_delete_msg = 0x4022bcdc);\r\nPROVIDE\t(dhcp_bind = 0x4022bd04);\r\nPROVIDE\t(dhcp_option_trailer = 0x4022bdfc);\r\nPROVIDE\t(dhcp_reboot = 0x4022be34);\r\nPROVIDE\t(dhcp_rebind = 0x4022bf04);\r\nPROVIDE\t(dhcp_select = 0x4022bfe0);\r\nPROVIDE\t(dhcp_discover = 0x4022c180);\r\nPROVIDE\t(dhcp_recv = 0x4022c2cc);\r\nPROVIDE\t(dhcp_set_struct = 0x4022c8b4);\r\nPROVIDE\t(dhcp_cleanup = 0x4022c8dc);\r\nPROVIDE\t(dhcp_inform = 0x4022c900);\r\nPROVIDE\t(dhcp_network_changed = 0x4022c9b0);\r\nPROVIDE\t(dhcp_arp_reply = 0x4022c9f8);\r\nPROVIDE\t(dhcp_renew = 0x4022caac);\r\nPROVIDE\t(dhcp_coarse_tmr = 0x4022cb88);\r\nPROVIDE\t(dhcp_release = 0x4022cc1c);\r\nPROVIDE\t(dhcp_fine_tmr = 0x4022cce4);\r\nPROVIDE\t(dhcp_stop = 0x4022cdd8);\r\nPROVIDE\t(dhcp_start = 0x4022ce14);\r\nPROVIDE\t(create_msg = 0x4022cedc);\r\nPROVIDE\t(add_offer_options = 0x4022cf94);\r\nPROVIDE\t(node_insert_to_list = 0x4022d0d4);\r\nPROVIDE\t(node_remove_from_list = 0x4022d10c);\r\nPROVIDE\t(handle_dhcp = 0x4022d150);\r\nPROVIDE\t(dhcps_start = 0x4022d5bc);\r\nPROVIDE\t(dhcps_stop = 0x4022d69c);\r\nPROVIDE\t(wifi_softap_set_dhcps_lease = 0x4022d700);\r\nPROVIDE\t(wifi_softap_get_dhcps_lease = 0x4022d724);\r\nPROVIDE\t(dhcps_coarse_tmr = 0x4022d73c);\r\nPROVIDE\t(wifi_softap_set_dhcps_offer_option = 0x4022d7dc);\r\nPROVIDE\t(wifi_softap_set_dhcps_lease_time = 0x4022d81c);\r\nPROVIDE\t(wifi_softap_reset_dhcps_lease_time = 0x4022d82c);\r\nPROVIDE\t(wifi_softap_get_dhcps_lease_time = 0x4022d838);\r\nPROVIDE\t(dns_parse_name = 0x4022d840);\r\nPROVIDE\t(dns_recv = 0x4022d874);\r\nPROVIDE\t(dns_send = 0x4022dabc);\r\nPROVIDE\t(dns_check_entry = 0x4022dbcc);\r\nPROVIDE\t(dns_setserver = 0x4022dca8);\r\nPROVIDE\t(dns_init = 0x4022dcd0);\r\nPROVIDE\t(dns_getserver = 0x4022dd14);\r\nPROVIDE\t(dns_tmr = 0x4022dd2c);\r\nPROVIDE\t(dns_gethostbyname = 0x4022dd5c);\r\nPROVIDE\t(esf_buf_alloc = 0x4022de7c);\r\nPROVIDE\t(esf_buf_recycle = 0x4022e064);\r\nPROVIDE\t(esf_buf_setup = 0x4022e1a4);\r\nPROVIDE\t(icmp_input = 0x4022e264);\r\nPROVIDE\t(icmp_dest_unreach = 0x4022e3e8);\r\nPROVIDE\t(ieee80211_send_action_register = 0x4022e4a0);\r\nPROVIDE\t(ieee80211_send_action_unregister = 0x4022e4d4);\r\nPROVIDE\t(ieee80211_send_action = 0x4022e4e8);\r\nPROVIDE\t(ieee80211_recv_action_register = 0x4022e554);\r\nPROVIDE\t(ieee80211_recv_action_unregister = 0x4022e588);\r\nPROVIDE\t(ieee80211_recv_action = 0x4022e59c);\r\nPROVIDE\t(igmp_send = 0x4022e964);\r\nPROVIDE\t(igmp_delaying_member = 0x4022ea50);\r\nPROVIDE\t(igmp_init = 0x4022eaf4);\r\nPROVIDE\t(igmp_stop = 0x4022eb08);\r\nPROVIDE\t(igmp_report_groups = 0x4022eb6c);\r\nPROVIDE\t(igmp_lookfor_group = 0x4022eb9c);\r\nPROVIDE\t(igmp_start = 0x4022ebb8);\r\nPROVIDE\t(igmp_input = 0x4022ec0c);\r\nPROVIDE\t(igmp_joingroup = 0x4022ed28);\r\nPROVIDE\t(igmp_leavegroup = 0x4022edf0);\r\nPROVIDE\t(igmp_tmr = 0x4022eec4);\r\nPROVIDE\t(os_get_time = 0x4022ef00);\r\nPROVIDE\t(r_rand = 0x4022ef04);\r\nPROVIDE\t(os_random = 0x4022ef14);\r\nPROVIDE\t(os_get_random = 0x4022ef24);\r\nPROVIDE\t(ets_strrchr = 0x4022ef6c);\r\nPROVIDE\t(rijndaelEncrypt = 0x4022ef88);\r\nPROVIDE\t(aes_encrypt_init = 0x4022f3a4);\r\nPROVIDE\t(aes_encrypt = 0x4022f3f8);\r\nPROVIDE\t(aes_encrypt_deinit = 0x4022f410);\r\nPROVIDE\t(rijndaelKeySetupEnc = 0x4022f440);\r\nPROVIDE\t(init_done_cb = 0x4022f75c);\r\nPROVIDE\t(user_init = 0x4022f818);\r\nPROVIDE\t(write_power_meter_cfg = 0x4022f8d4);\r\nPROVIDE\t(power_meter_clear_all_data = 0x4022f8f8);\r\nPROVIDE\t(fram_init = 0x4022f9a4);\r\nPROVIDE\t(NextPtrCurrent = 0x4022f9c0);\r\nPROVIDE\t(FRAM_Store_Init = 0x4022fa80);\r\nPROVIDE\t(power_meter_init = 0x4022fdc0);\r\nPROVIDE\t(GPIO_Task_NewData = 0x4022ff68);\r\nPROVIDE\t(update_cnts = 0x40230068);\r\nPROVIDE\t(user_idle = 0x40230468);\r\nPROVIDE\t(FRAM_speed_test = 0x40230508);\r\nPROVIDE\t(i2c_Init = 0x402306b8);\r\nPROVIDE\t(i2c_eeprom_read_block = 0x40230740);\r\nPROVIDE\t(i2c_eeprom_write_block = 0x402307c8);\r\nPROVIDE\t(Set_default_wificfg = 0x40230860);\r\nPROVIDE\t(wifi_start_scan = 0x402309e8);\r\nPROVIDE\t(WiFi_go_to_sleep = 0x40230a3c);\r\nPROVIDE\t(WiFi_up_from_sleep = 0x40230a74);\r\nPROVIDE\t(Set_WiFi = 0x40230ab4);\r\nPROVIDE\t(Cmp_WiFi_chg = 0x40230db0);\r\nPROVIDE\t(print_wifi_config = 0x40231034);\r\nPROVIDE\t(New_WiFi_config = 0x402311a8);\r\nPROVIDE\t(wifi_scan_cb = 0x40231218);\r\nPROVIDE\t(wifi_read_fcfg = 0x40231318);\r\nPROVIDE\t(Setup_WiFi = 0x40231360);\r\nPROVIDE\t(Read_WiFi_config = 0x402313a8);\r\nPROVIDE\t(wifi_save_fcfg = 0x4023155c);\r\nPROVIDE\t(flash_read_cfg = 0x40231868);\r\nPROVIDE\t(flash_save_cfg = 0x402318e8);\r\nPROVIDE\t(sys_write_cfg = 0x40231910);\r\nPROVIDE\t(sys_read_cfg = 0x40231928);\r\nPROVIDE\t(current_cfg_length = 0x40231984);\r\nPROVIDE\t(read_user_const = 0x402319dc);\r\nPROVIDE\t(write_user_const = 0x40231a14);\r\nPROVIDE\t(station_connect_timer = 0x40231a4c);\r\nPROVIDE\t(station_reconnect_off = 0x40231aa4);\r\nPROVIDE\t(close_all_service = 0x40231ad0);\r\nPROVIDE\t(open_all_service = 0x40231b14);\r\nPROVIDE\t(print_event_reason = 0x40231ba8);\r\nPROVIDE\t(add_next_probe_requests = 0x40231bf0);\r\nPROVIDE\t(wifi_handle_event_cb = 0x40231cd8);\r\nPROVIDE\t(ntp_time_update = 0x40231f38);\r\nPROVIDE\t(sntp_retry = 0x40231f4c);\r\nPROVIDE\t(sntp_send_request = 0x40231f84);\r\nPROVIDE\t(sntp_request = 0x40231ff0);\r\nPROVIDE\t(sntp_dns_found = 0x4023204c);\r\nPROVIDE\t(sntp_inits = 0x40232078);\r\nPROVIDE\t(sntp_close = 0x40232108);\r\nPROVIDE\t(get_sntp_time = 0x40232150);\r\nPROVIDE\t(sntp_recv = 0x40232184);\r\nPROVIDE\t(web_fini = 0x402322d4);\r\nPROVIDE\t(_localtime = 0x40232504);\r\nPROVIDE\t(WEBFSClose = 0x40232644);\r\nPROVIDE\t(WEBFS_max_size = 0x4023266c);\r\nPROVIDE\t(WEBFS_curent_size = 0x402326a4);\r\nPROVIDE\t(WEBFS_base_addr = 0x402326d0);\r\nPROVIDE\t(WEBFSGetArray = 0x402326f8);\r\nPROVIDE\t(WEBFSInit = 0x40232798);\r\nPROVIDE\t(GetFATRecord = 0x40232824);\r\nPROVIDE\t(WEBFSOpen = 0x4023289c);\r\nPROVIDE\t(WEBFSGetFlags = 0x402329ac);\r\nPROVIDE\t(WEBFSGetSize = 0x402329e0);\r\nPROVIDE\t(WEBFSGetBytesRem = 0x40232a10);\r\nPROVIDE\t(WEBFSGetStartAddr = 0x40232a2c);\r\nPROVIDE\t(WEBFSGetEndAddr = 0x40232a5c);\r\nPROVIDE\t(WEBFSSeek = 0x40232a90);\r\nPROVIDE\t(WEBFSGetFilename = 0x40232b3c);\r\nPROVIDE\t(WEBFSGetPosition = 0x40232b94);\r\nPROVIDE\t(set_cpu_clk = 0x40232bb8);\r\nPROVIDE\t(get_addr_gpiox_mux = 0x40232c0c);\r\nPROVIDE\t(set_gpiox_mux_pull = 0x40232c38);\r\nPROVIDE\t(set_gpiox_mux_func = 0x40232c64);\r\nPROVIDE\t(set_gpiox_mux_func_ioport = 0x40232c9c);\r\nPROVIDE\t(set_gpiox_mux_func_default = 0x40232cc8);\r\nPROVIDE\t(get_gpiox_mux = 0x40232cf4);\r\nPROVIDE\t(get_gpiox_mux_func = 0x40232d0c);\r\nPROVIDE\t(test_pin_clr_wifi_config = 0x40232d3c);\r\nPROVIDE\t(get_mac_time = 0x40232e14);\r\nPROVIDE\t(web_int_disconnect = 0x40232e2c);\r\nPROVIDE\t(Close_web_conn = 0x40232e80);\r\nPROVIDE\t(webserver_disconnect = 0x40232ed8);\r\nPROVIDE\t(web_inc_fp = 0x40232f18);\r\nPROVIDE\t(find_boundary = 0x40232f84);\r\nPROVIDE\t(webserver_init = 0x4023302c);\r\nPROVIDE\t(webserver_close = 0x402330d8);\r\nPROVIDE\t(webserver_reinit = 0x40233104);\r\nPROVIDE\t(web_inc_fopen = 0x40233148);\r\nPROVIDE\t(webserver_open_file = 0x402331f4);\r\nPROVIDE\t(web_inc_fclose = 0x4023336c);\r\nPROVIDE\t(webserver_send_fdata = 0x40233410);\r\nPROVIDE\t(webserver_sent_callback = 0x4023379c);\r\nPROVIDE\t(web_trim_bufi = 0x40233830);\r\nPROVIDE\t(web_feee_bufi = 0x40233898);\r\nPROVIDE\t(head_find_ctr = 0x402338cc);\r\nPROVIDE\t(webserver_received_data = 0x40233acc);\r\nPROVIDE\t(tcpsrv_list_delete = 0x40234e04);\r\nPROVIDE\t(tcpsrv_client_reconnect = 0x40234eb0);\r\nPROVIDE\t(recv_trim_bufi = 0x40234f94);\r\nPROVIDE\t(tcpsrv_server_sent = 0x402350f8);\r\nPROVIDE\t(tcpsrv_print_remote_info = 0x40235150);\r\nPROVIDE\t(tcpsrv_server_close = 0x40235190);\r\nPROVIDE\t(tcpsrv_int_sent_data = 0x40235284);\r\nPROVIDE\t(tcpsrv_server_recv = 0x40235380);\r\nPROVIDE\t(tcpsrv_connected = 0x402354a8);\r\nPROVIDE\t(tcpsrv_server_poll = 0x4023556c);\r\nPROVIDE\t(tcpsrv_error = 0x40235614);\r\nPROVIDE\t(tcpsrv_disconnect_calback_default = 0x402356c0);\r\nPROVIDE\t(tcpsrv_listen_default = 0x402356e0);\r\nPROVIDE\t(tcpsrv_sent_callback_default = 0x40235700);\r\nPROVIDE\t(tcpsrv_received_data_default = 0x40235720);\r\nPROVIDE\t(tcpsrv_server_port2pcfg = 0x40235744);\r\nPROVIDE\t(tcpsrv_client_ip_port2conn = 0x40235764);\r\nPROVIDE\t(tcpsrv_unrecved_win = 0x40235790);\r\nPROVIDE\t(tcpsrv_init = 0x402357dc);\r\nPROVIDE\t(tcpsrv_start = 0x40235890);\r\nPROVIDE\t(tcpsrv_connected_default = 0x4023592c);\r\nPROVIDE\t(find_tcp_pcb = 0x40235948);\r\nPROVIDE\t(tcpsrv_close_cb = 0x4023599c);\r\nPROVIDE\t(tcpsrv_client_connect = 0x40235a84);\r\nPROVIDE\t(tcpsrv_client_start = 0x40235b48);\r\nPROVIDE\t(tcpsrv_disconnect = 0x40235be8);\r\nPROVIDE\t(tcpsrv_server_accept = 0x40235c1c);\r\nPROVIDE\t(tcpsrv_close = 0x40235d5c);\r\nPROVIDE\t(tcpsrv_close_port = 0x40235e1c);\r\nPROVIDE\t(tcpsrv_close_all = 0x40235e40);\r\nPROVIDE\t(web_hexdump = 0x40235e84);\r\nPROVIDE\t(web_get_i2c_eeprom = 0x40236008);\r\nPROVIDE\t(wifi_aps_xml = 0x402360a4);\r\nPROVIDE\t(web_wscan_xml = 0x40236208);\r\nPROVIDE\t(web_ProbeRequest_xml = 0x40236344);\r\nPROVIDE\t(web_get_history = 0x40236468);\r\nPROVIDE\t(web_get_flash = 0x402367cc);\r\nPROVIDE\t(web_get_ram = 0x40236860);\r\nPROVIDE\t(get_new_url = 0x402368ec);\r\nPROVIDE\t(web_int_callback = 0x40236c38);\r\nPROVIDE\t(rom_atoi = 0x40238970);\r\nPROVIDE\t(hextoul = 0x402389c0);\r\nPROVIDE\t(ahextoul = 0x40238a10);\r\nPROVIDE\t(cmpcpystr = 0x40238a44);\r\nPROVIDE\t(web_strnstr = 0x40238adc);\r\nPROVIDE\t(base64decode = 0x40238b4c);\r\nPROVIDE\t(base64encode = 0x40238c18);\r\nPROVIDE\t(strtomac = 0x40238ce4);\r\nPROVIDE\t(urldecode = 0x40238d50);\r\nPROVIDE\t(htmlcode = 0x40238e18);\r\nPROVIDE\t(print_hex_dump = 0x40238f60);\r\nPROVIDE\t(str_array = 0x40238fac);\r\nPROVIDE\t(str_array_w = 0x40239030);\r\nPROVIDE\t(str_array_b = 0x402390b8);\r\nPROVIDE\t(word_to_lower_case = 0x40239144);\r\nPROVIDE\t(copy_align4 = 0x4023917c);\r\nPROVIDE\t(go_deep_sleep = 0x4023924c);\r\nPROVIDE\t(reg_sct_bits = 0x40239264);\r\nPROVIDE\t(web_int_vars = 0x4023943c);\r\nPROVIDE\t(rd_buf_sec_blk = 0x4023a49c);\r\nPROVIDE\t(wr_buf_sec_blk = 0x4023a4d4);\r\nPROVIDE\t(read_sys_const = 0x4023a52c);\r\nPROVIDE\t(write_sys_const = 0x4023a54c);\r\nPROVIDE\t(uart_save_fcfg = 0x4023a5bc);\r\nPROVIDE\t(update_rts0 = 0x4023a658);\r\nPROVIDE\t(update_mux_uart0 = 0x4023a674);\r\nPROVIDE\t(uart0_set_flow = 0x4023a71c);\r\nPROVIDE\t(update_mux_txd1 = 0x4023a76c);\r\nPROVIDE\t(uart_read_fcfg = 0x4023a7a4);\r\nPROVIDE\t(uarts_init = 0x4023a864);\r\nPROVIDE\t(set_uartx_invx = 0x4023a888);\r\nPROVIDE\t(sar_init = 0x4023a900);\r\nPROVIDE\t(sar_off = 0x4023a9c8);\r\nPROVIDE\t(read_adcs = 0x4023aa2c);\r\nPROVIDE\t(sigma_delta_setup = 0x4023aad8);\r\nPROVIDE\t(sigma_delta_close = 0x4023ab30);\r\nPROVIDE\t(set_sigma_duty_312KHz = 0x4023ab80);\r\nPROVIDE\t(aFATAL_ERR_R6PHY = 0x4023abb4);\r\nPROVIDE\t(esp_init_data_default = 0x4023ac24);\r\nPROVIDE\t(ieee80211_opcap = 0x4023ad00);\r\nPROVIDE\t(ip_addr_broadcast = 0x4023b234);\r\nPROVIDE\t(ip_addr_any = 0x4023b238);\r\nPROVIDE\t(memp_sizes = 0x4023b270);\r\nPROVIDE\t(chip_v6_set_sense = 0x4023b5d4);\r\nPROVIDE\t(chip_v6_unset_chanfreq = 0x4023b5d8);\r\nPROVIDE\t(bit_popcount = 0x4023b89c);\r\nPROVIDE\t(tcp_pcb_lists = 0x4023b8c0);\r\nPROVIDE\t(tcp_persist_backoff = 0x4023b8d0);\r\nPROVIDE\t(tcp_backoff = 0x4023b8d8);\r\nPROVIDE\t(default_ssid = 0x4023b950);\r\nPROVIDE\t(eloop_cancel_timeout = 0x4023becc);\r\nPROVIDE\t(eloop_register_timeout = 0x4023bed0);\r\nPROVIDE\t(magic_cookie = 0x4023bfc4);\r\nPROVIDE\t(ccmp = 0x4023bfdc);\r\nPROVIDE\t(tkip = 0x4023bff4);\r\nPROVIDE\t(wep = 0x4023c00c);\r\nPROVIDE\t(lwip_standard_chksum = 0x4023c024);\r\nPROVIDE\t(inet_chksum = 0x4023c08c);\r\nPROVIDE\t(inet_chksum_pbuf = 0x4023c0a8);\r\nPROVIDE\t(inet_chksum_pseudo = 0x4023c114);\r\nPROVIDE\t(inet_chksum_pseudo_partial = 0x4023c1d4);\r\nPROVIDE\t(sysinifname = 0x4023c404);\r\nPROVIDE\t(wifi_st_password = 0x4023c964);\r\nPROVIDE\t(wifi_st_name = 0x4023c970);\r\nPROVIDE\t(wifi_ap_password = 0x4023c978);\r\nPROVIDE\t(wifi_ap_name = 0x4023c984);\r\nPROVIDE\t(tab_event_reason_1_24_200 = 0x4023cbe8);\r\nPROVIDE\t(txt_reason_handshake_timeout = 0x4023cc58);\r\nPROVIDE\t(txt_reason_assoc_fail = 0x4023cc6c);\r\nPROVIDE\t(txt_reason_auth_fail = 0x4023cc78);\r\nPROVIDE\t(txt_reason_no_ap_found = 0x4023cc84);\r\nPROVIDE\t(txt_reason_beacon_timeout = 0x4023cc90);\r\nPROVIDE\t(txt_reason_cipher_suite_rejected = 0x4023cca0);\r\nPROVIDE\t(txt_reason_802_1x_auth_failed = 0x4023ccb8);\r\nPROVIDE\t(txt_reason_invalid_rsn_ie_cap = 0x4023cccc);\r\nPROVIDE\t(txt_reason_unsupp_rsn_ie_version = 0x4023cce0);\r\nPROVIDE\t(txt_reason_akmp_invalid = 0x4023ccf8);\r\nPROVIDE\t(txt_reason_pairwise_cipher_invalid = 0x4023cd08);\r\nPROVIDE\t(txt_reason_group_cipher_invalid = 0x4023cd20);\r\nPROVIDE\t(txt_reason_ie_in_4way_differs = 0x4023cd38);\r\nPROVIDE\t(txt_reason_group_key_update_timeout = 0x4023cd4c);\r\nPROVIDE\t(txt_reason_4way_handshake_timeout = 0x4023cd68);\r\nPROVIDE\t(txt_reason_mic_failure = 0x4023cd80);\r\nPROVIDE\t(txt_reason_ie_invalid = 0x4023cd8c);\r\nPROVIDE\t(txt_reason_disassoc_supchan_bad = 0x4023cd98);\r\nPROVIDE\t(txt_reason_disassoc_pwrcap_bad = 0x4023cdb0);\r\nPROVIDE\t(txt_reason_assoc_not_authed = 0x4023cdc4);\r\nPROVIDE\t(txt_reason_assoc_leave = 0x4023cdd8);\r\nPROVIDE\t(txt_reason_not_assoced = 0x4023cde4);\r\nPROVIDE\t(txt_reason_not_authed = 0x4023cdf0);\r\nPROVIDE\t(txt_reason_assoc_toomany = 0x4023cdfc);\r\nPROVIDE\t(txt_reason_assoc_expire = 0x4023ce0c);\r\nPROVIDE\t(txt_reason_auth_leave = 0x4023ce1c);\r\nPROVIDE\t(txt_reason_auth_expire = 0x4023ce28);\r\nPROVIDE\t(txt_reason_unspecified = 0x4023ce34);\r\nPROVIDE\t(txt_reason_undef = 0x4023ce40);\r\nPROVIDE\t(sntp_server_addresses = 0x4023ce9c);\r\nPROVIDE\t(flash_filename = 0x4023d248);\r\nPROVIDE\t(file_label = 0x4023d254);\r\nPROVIDE\t(sector_filename = 0x4023d25c);\r\nPROVIDE\t(sysconst_filename = 0x4023d264);\r\nPROVIDE\t(disk_err4_filename = 0x4023d270);\r\nPROVIDE\t(disk_err3_filename = 0x4023d280);\r\nPROVIDE\t(disk_err2_filename = 0x4023d290);\r\nPROVIDE\t(disk_err1_filename = 0x4023d2a0);\r\nPROVIDE\t(disk_ok_filename = 0x4023d2b0);\r\nPROVIDE\t(crlf_end_boundary = 0x4023d2c0);\r\nPROVIDE\t(HTTPAccessControlAllowOrigin = 0x4023d5d4);\r\nPROVIDE\t(HTTPfserror = 0x4023d5f8);\r\nPROVIDE\t(HTTPdefault = 0x4023d644);\r\nPROVIDE\t(HTTPfsupload = 0x4023d690);\r\nPROVIDE\t(HTTPResponse = 0x4023d770);\r\nPROVIDE\t(HTTPresponse_501_content = 0x4023d840);\r\nPROVIDE\t(HTTPresponse_500_content = 0x4023d874);\r\nPROVIDE\t(HTTPresponse_418_content = 0x4023d890);\r\nPROVIDE\t(HTTPresponse_414_content = 0x4023d8a8);\r\nPROVIDE\t(HTTPresponse_413_content = 0x4023d8e0);\r\nPROVIDE\t(HTTPresponse_411_content = 0x4023d91c);\r\nPROVIDE\t(HTTPresponse_404_content = 0x4023d94c);\r\nPROVIDE\t(HTTPresponse_401_content = 0x4023d964);\r\nPROVIDE\t(HTTPresponse_501_head = 0x4023d98c);\r\nPROVIDE\t(HTTPresponse_500_head = 0x4023d9b0);\r\nPROVIDE\t(HTTPresponse_429_head = 0x4023d9c8);\r\nPROVIDE\t(HTTPresponse_418_head = 0x4023d9ec);\r\nPROVIDE\t(HTTPresponse_414_head = 0x4023d9fc);\r\nPROVIDE\t(HTTPresponse_413_head = 0x4023da14);\r\nPROVIDE\t(HTTPresponse_411_head = 0x4023da30);\r\nPROVIDE\t(HTTPresponse_404_head = 0x4023da40);\r\nPROVIDE\t(HTTPresponse_401_head = 0x4023da4c);\r\nPROVIDE\t(HTTPresponse_400_head = 0x4023da84);\r\nPROVIDE\t(HTTPresponse_304_head = 0x4023da90);\r\nPROVIDE\t(HTTPresponse_302_head = 0x4023daa0);\r\nPROVIDE\t(HTTPresponse_200_head = 0x4023daa8);\r\nPROVIDE\t(fsupload_fname = 0x4023daac);\r\nPROVIDE\t(web_cgi_fname = 0x4023dab8);\r\nPROVIDE\t(http_default_file = 0x4023dac0);\r\nPROVIDE\t(srvContenErr15 = 0x4023dc20);\r\nPROVIDE\t(srvContenErr14 = 0x4023dc34);\r\nPROVIDE\t(srvContenErr13 = 0x4023dc4c);\r\nPROVIDE\t(srvContenErr12 = 0x4023dc5c);\r\nPROVIDE\t(srvContenErr11 = 0x4023dc70);\r\nPROVIDE\t(srvContenErr10 = 0x4023dc80);\r\nPROVIDE\t(srvContenErr09 = 0x4023dc94);\r\nPROVIDE\t(srvContenErr08 = 0x4023dca8);\r\nPROVIDE\t(srvContenErr07 = 0x4023dcbc);\r\nPROVIDE\t(srvContenErr06 = 0x4023dcd4);\r\nPROVIDE\t(srvContenErr05 = 0x4023dce4);\r\nPROVIDE\t(srvContenErr04 = 0x4023dcfc);\r\nPROVIDE\t(srvContenErr03 = 0x4023dd0c);\r\nPROVIDE\t(srvContenErr02 = 0x4023dd14);\r\nPROVIDE\t(srvContenErr01 = 0x4023dd24);\r\nPROVIDE\t(srvContenErr00 = 0x4023dd38);\r\nPROVIDE\t(txt_tcpsrv_out_of_mem = 0x4023df20);\r\nPROVIDE\t(txt_tcpsrv_already_initialized = 0x4023df38);\r\nPROVIDE\t(txt_tcpsrv_NULL_pointer = 0x4023df58);\r\nPROVIDE\t(base64map = 0x4023e224);\r\nPROVIDE\t(_irom0_text_end = 0x4023e2cc);\r\nPROVIDE\t(uart0_ = 0x60000000);\r\nPROVIDE\t(spi0_ = 0x60000200);\r\nPROVIDE\t(gpio_ = 0x60000300);\r\nPROVIDE\t(timer_ = 0x60000600);\r\nPROVIDE\t(rtc_ = 0x60000700);\r\nPROVIDE\t(iomux_ = 0x60000800);\r\nPROVIDE\t(wdt_ = 0x60000900);\r\nPROVIDE\t(sar_ = 0x60000d00);\r\nPROVIDE\t(uart1_ = 0x60000f00);\r\nPROVIDE\t(rtc_ram_ = 0x60001000);\r\nPROVIDE\t(rtc_mem_ = 0x60001100);\r\nPROVIDE\t(_memmap_cacheattr_unused_mask = 0xfffff00f);\r\nPROVIDE\t(_memmap_cacheattr_wb_strict = 0xfffff11f);\r\nPROVIDE\t(_memmap_cacheattr_wt_strict = 0xfffff11f);\r\nPROVIDE\t(_memmap_cacheattr_bp_strict = 0xfffff22f);\r\n=======\nPROVIDE\t(_memmap_cacheattr_wb_base = 0x00000110);\nPROVIDE\t(_memmap_cacheattr_wt_base = 0x00000110);\nPROVIDE\t(_memmap_cacheattr_bp_base = 0x00000220);\nPROVIDE\t(_memmap_cacheattr_wb_allvalid = 0x22222112);\nPROVIDE\t(_memmap_cacheattr_wt_allvalid = 0x22222112);\nPROVIDE\t(_memmap_cacheattr_wb_trapnull = 0x2222211f);\nPROVIDE\t(_memmap_cacheattr_wba_trapnull = 0x2222211f);\nPROVIDE\t(_memmap_cacheattr_wbna_trapnull = 0x2222211f);\nPROVIDE\t(_memmap_cacheattr_wt_trapnull = 0x2222211f);\nPROVIDE\t(_memmap_cacheattr_bp_allvalid = 0x22222222);\nPROVIDE\t(_memmap_cacheattr_bp_trapnull = 0x2222222f);\nPROVIDE\t(_dport0_data_end = 0x3ff00000);\nPROVIDE\t(_dport0_data_start = 0x3ff00000);\nPROVIDE\t(_dport0_literal_end = 0x3ff00000);\nPROVIDE\t(_dport0_literal_start = 0x3ff00000);\nPROVIDE\t(_dport0_rodata_end = 0x3ff00000);\nPROVIDE\t(_dport0_rodata_start = 0x3ff00000);\nPROVIDE\t(dport_ = 0x3ff00000);\nPROVIDE\t(_data_start = 0x3ffe8000);\nPROVIDE\t(SDK_VERSION = 0x3ffe8000);\nPROVIDE\t(TmpSTAAPCloseAP = 0x3ffe8008);\nPROVIDE\t(memp_sizes_test = 0x3ffe800a);\nPROVIDE\t(tx_rf_ana_gain = 0x3ffe8012);\nPROVIDE\t(rx_gain_swp = 0x3ffe8040);\nPROVIDE\t(test_rffreq_txcap = 0x3ffe8060);\nPROVIDE\t(rfcal_bb_atten_init = 0x3ffe8064);\nPROVIDE\t(chip_version = 0x3ffe8068);\nPROVIDE\t(soft_wdt_interval = 0x3ffe8074);\nPROVIDE\t(NoiseTimerInterval = 0x3ffe8078);\nPROVIDE\t(sleep_start_wait_time = 0x3ffe8080);\nPROVIDE\t(CanDoFreqCal = 0x3ffe8088);\nPROVIDE\t(tcb = 0x3ffe808c);\nPROVIDE\t(timer2_ms_flag = 0x3ffe832d);\nPROVIDE\t(dhcps_flag = 0x3ffe832e);\nPROVIDE\t(dhcpc_flag = 0x3ffe832f);\nPROVIDE\t(reconnect_internal = 0x3ffe8331);\nPROVIDE\t(offer = 0x3ffe8344);\nPROVIDE\t(HTTPCookie = 0x3ffe8364);\nPROVIDE\t(HTTPAuthorization = 0x3ffe8368);\nPROVIDE\t(HTTPboundary = 0x3ffe836c);\nPROVIDE\t(HTTPmultipartformdata = 0x3ffe8370);\nPROVIDE\t(HTTPContentType = 0x3ffe8374);\nPROVIDE\t(HTTPContentLength = 0x3ffe8378);\nPROVIDE\t(HTTPHost = 0x3ffe837c);\nPROVIDE\t(HTTPSecWebSocketKey = 0x3ffe8380);\nPROVIDE\t(HTTPwebsocket = 0x3ffe8384);\nPROVIDE\t(HTTPUpgrade = 0x3ffe8388);\nPROVIDE\t(_data_end = 0x3ffe838c);\nPROVIDE\t(_rodata_start = 0x3ffe838c);\nPROVIDE\t(ethzero = 0x3ffe838c);\nPROVIDE\t(ethbroadcast = 0x3ffe8392);\nPROVIDE\t(HostNameLocal = 0x3ffe8448);\nPROVIDE\t(httpContentTypes = 0x3ffe846c);\nPROVIDE\t(httpFileExtensions = 0x3ffe84b4);\nPROVIDE\t(mdbtabaddr = 0x3ffe8538);\nPROVIDE\t(_bss_table_end = 0x3ffe8bbc);\nPROVIDE\t(_bss_table_start = 0x3ffe8bbc);\nPROVIDE\t(_rodata_end = 0x3ffe8bbc);\nPROVIDE\t(_bss_start = 0x3ffe8bc0);\nPROVIDE\t(etharp_cached_entry = 0x3ffe8bc0);\nPROVIDE\t(arp_table = 0x3ffe8bc4);\nPROVIDE\t(g_ic = 0x3ffe8cb4);\nPROVIDE\t(BcnEb_update = 0x3ffe9340);\nPROVIDE\t(BcnWithMcastSendStart = 0x3ffe934d);\nPROVIDE\t(BcnWithMcastSendCnt = 0x3ffe934e);\nPROVIDE\t(PendFreeBcnEb = 0x3ffe9368);\nPROVIDE\t(ApFreqCalTimer = 0x3ffe936c);\nPROVIDE\t(APRecvBcnStartTick = 0x3ffe9380);\nPROVIDE\t(gScanStruct = 0x3ffe9398);\nPROVIDE\t(connect_scan_flag = 0x3ffe9444);\nPROVIDE\t(FreqCalCntForScan = 0x3ffe9445);\nPROVIDE\t(TestStaFreqCalValInput = 0x3ffe9446);\nPROVIDE\t(auth_type = 0x3ffe9448);\nPROVIDE\t(scannum = 0x3ffe944a);\nPROVIDE\t(interface_mask = 0x3ffe9470);\nPROVIDE\t(if_ctrl = 0x3ffe9490);\nPROVIDE\t(ip_id = 0x3ffe94b0);\nPROVIDE\t(lmacConfMib = 0x3ffe94d4);\nPROVIDE\t(our_tx_eb = 0x3ffe94f8);\nPROVIDE\t(xStart = 0x3ffe9620);\nPROVIDE\t(g_phyFuns = 0x3ffe9630);\nPROVIDE\t(rxiq_compute_num = 0x3ffe9634);\nPROVIDE\t(rx_table_renew_en = 0x3ffe9638);\nPROVIDE\t(check_result = 0x3ffe963c);\nPROVIDE\t(chip6_sleep_params = 0x3ffe9640);\nPROVIDE\t(chip6_phy_init_ctrl = 0x3ffe96d4);\nPROVIDE\t(phy_freq_offset = 0x3ffe9748);\nPROVIDE\t(do_pwctrl_flag = 0x3ffe974a);\nPROVIDE\t(txbk_dpdby_flag = 0x3ffe974b);\nPROVIDE\t(sw_scan_mode = 0x3ffe974d);\nPROVIDE\t(rxmax_ext_level = 0x3ffe974e);\nPROVIDE\t(phy_rx_gain_dc_table = 0x3ffe9750);\nPROVIDE\t(periodic_cal_dc_num = 0x3ffe9764);\nPROVIDE\t(periodic_cal_flag = 0x3ffe9768);\nPROVIDE\t(bbpll_cal_flag = 0x3ffe9769);\nPROVIDE\t(phy_in_most_power = 0x3ffe976a);\nPROVIDE\t(init_rf_no_cal = 0x3ffe976b);\nPROVIDE\t(test_print_time = 0x3ffe976c);\nPROVIDE\t(phy_rx_gain_dc_flag = 0x3ffe9770);\nPROVIDE\t(phy_in_vdd33_offset = 0x3ffe9771);\nPROVIDE\t(phy_set_most_tpw_disbg = 0x3ffe9772);\nPROVIDE\t(phy_set_most_tpw_index = 0x3ffe9773);\nPROVIDE\t(adc_rand_noise = 0x3ffe9774);\nPROVIDE\t(dpd_bypass_original = 0x3ffe9778);\nPROVIDE\t(phy_txpwr_diff_flash = 0x3ffe977a);\nPROVIDE\t(noise_array = 0x3ffe9780);\nPROVIDE\t(tout_dis_txpwr_track = 0x3ffe978c);\nPROVIDE\t(sleep_mode_flag = 0x3ffe978d);\nPROVIDE\t(phy_tx_power_out = 0x3ffe9790);\nPROVIDE\t(phy_tx_pwr_error = 0x3ffe9792);\nPROVIDE\t(tx_pwctrl_track_num = 0x3ffe9794);\nPROVIDE\t(rxiq_cover_fail_num = 0x3ffe9795);\nPROVIDE\t(phy_meas_freq_offset = 0x3ffe9796);\nPROVIDE\t(tx_pwctrl_pk_num = 0x3ffe9798);\nPROVIDE\t(periodic_cal_sat = 0x3ffe979c);\nPROVIDE\t(lslp_mem_opt_8266 = 0x3ffe979e);\nPROVIDE\t(software_slp_reject = 0x3ffe97a0);\nPROVIDE\t(SDIO_slp_reject = 0x3ffe97a1);\nPROVIDE\t(hardware_reject = 0x3ffe97a2);\nPROVIDE\t(pmc = 0x3ffe97b0);\nPROVIDE\t(flash_tmp = 0x3ffe9890);\nPROVIDE\t(pend_flag_noise_check = 0x3ffe9918);\nPROVIDE\t(pend_flag_periodic_cal = 0x3ffe9920);\nPROVIDE\t(idle_timer_reopen_flag = 0x3ffe9938);\nPROVIDE\t(dbg_stop_sw_wdt = 0x3ffe993a);\nPROVIDE\t(dbg_stop_hw_wdt = 0x3ffe993b);\nPROVIDE\t(total_buffed_eb_num = 0x3ffe993d);\nPROVIDE\t(HighestFreqOffsetInOneChk = 0x3ffe9940);\nPROVIDE\t(LowestFreqOffsetInOneChk = 0x3ffe9942);\nPROVIDE\t(DefFreqCalTimer = 0x3ffe9944);\nPROVIDE\t(PktNumInOneChk = 0x3ffe9958);\nPROVIDE\t(buffed_eb_arr = 0x3ffe9ae0);\nPROVIDE\t(tcp_timer = 0x3ffe9d30);\nPROVIDE\t(recv_flags = 0x3ffe9d34);\nPROVIDE\t(tcplen = 0x3ffe9d36);\nPROVIDE\t(flags = 0x3ffe9d38);\nPROVIDE\t(seqno = 0x3ffe9d3c);\nPROVIDE\t(inseg = 0x3ffe9d40);\nPROVIDE\t(deep_sleep_flag = 0x3ffea2c7);\nPROVIDE\t(cpu_overclock = 0x3ffea2c8);\nPROVIDE\t(event_cb = 0x3ffea2cc);\nPROVIDE\t(status_led_output_level = 0x3ffea2d0);\nPROVIDE\t(done_cb = 0x3ffea2d4);\nPROVIDE\t(rst_if = 0x3ffea2d8);\nPROVIDE\t(default_interface = 0x3ffea2f4);\nPROVIDE\t(OpmodChgIsOnGoing = 0x3ffea2f5);\nPROVIDE\t(promiscuous_cb = 0x3ffea2f8);\nPROVIDE\t(event_TaskQueue = 0x3ffea310);\nPROVIDE\t(wDevCtrl = 0x3ffea420);\nPROVIDE\t(WdevTimOffSet = 0x3ffea5c8);\nPROVIDE\t(sta_con_timer = 0x3ffed748);\nPROVIDE\t(backup_ni_connect_status = 0x3ffed75c);\nPROVIDE\t(g_cnx_probe_rc_list_cb = 0x3ffed760);\nPROVIDE\t(reconnect_flag = 0x3ffed764);\nPROVIDE\t(no_ap_found_index = 0x3ffed765);\nPROVIDE\t(client_address_plus = 0x3ffed9dc);\nPROVIDE\t(client_address = 0x3ffed9e0);\nPROVIDE\t(server_address = 0x3ffed9e4);\nPROVIDE\t(broadcast_dhcps = 0x3ffed9e8);\nPROVIDE\t(dns_random = 0x3ffed9ec);\nPROVIDE\t(dns_servers = 0x3ffed9f0);\nPROVIDE\t(dns_seqno = 0x3ffed9f8);\nPROVIDE\t(allrouters = 0x3ffee4b0);\nPROVIDE\t(allsystems = 0x3ffee4b4);\nPROVIDE\t(info = 0x3ffee4b8);\nPROVIDE\t(user_init_flag = 0x3ffee4dc);\nPROVIDE\t(lwip_timer_interval = 0x3ffee4de);\nPROVIDE\t(default_hostname = 0x3ffee4e0);\nPROVIDE\t(current_iphdr_src = 0x3ffee4e4);\nPROVIDE\t(current_netif = 0x3ffee4e8);\nPROVIDE\t(current_iphdr_dest = 0x3ffee4ec);\nPROVIDE\t(current_header = 0x3ffee4f0);\nPROVIDE\t(tcp_listen_pcbs = 0x3ffee4f4);\nPROVIDE\t(dhcp_rx_options_given = 0x3ffee4f8);\nPROVIDE\t(dhcp_rx_options_val = 0x3ffee504);\nPROVIDE\t(dhcp_sntp_server_address = 0x3ffee530);\nPROVIDE\t(dhcps_lease = 0x3ffee534);\nPROVIDE\t(dns_table = 0x3ffee53c);\nPROVIDE\t(wificonfig = 0x3ffee99c);\nPROVIDE\t(syscfg = 0x3ffeeacc);\nPROVIDE\t(tcp_client_url = 0x3ffeeae4);\nPROVIDE\t(netbios_name = 0x3ffeeae8);\nPROVIDE\t(fatCache = 0x3ffeeafc);\nPROVIDE\t(mdb_buf = 0x3ffeeb0c);\nPROVIDE\t(_bss_end = 0x3ffeebd8);\nPROVIDE\t(_heap_start = 0x3ffeebd8);\nPROVIDE\t(flashchip = 0x3fffc714);\nPROVIDE\t(Te0 = 0x3fffccf0);\nPROVIDE\t(rcons = 0x3fffd0f0);\nPROVIDE\t(base64_table = 0x3fffd600);\nPROVIDE\t(timer_list = 0x3fffddb0);\nPROVIDE\t(UartDev = 0x3fffde10);\nPROVIDE\t(_sprintf_buf = 0x3fffe360);\nPROVIDE\t(print_mem_buf = 0x3fffe364);\nPROVIDE\t(_ResetVector = 0x40000080);\nPROVIDE\t(_xtos_set_exception_handler = 0x40000454);\nPROVIDE\t(__muldi3 = 0x40000650);\nPROVIDE\t(ets_set_idle_cb = 0x40000dc0);\nPROVIDE\t(ets_task = 0x40000dd0);\nPROVIDE\t(ets_run = 0x40000e04);\nPROVIDE\t(ets_post = 0x40000e24);\nPROVIDE\t(ets_intr_lock = 0x40000f74);\nPROVIDE\t(ets_intr_unlock = 0x40000f80);\nPROVIDE\t(ets_isr_attach = 0x40000f88);\nPROVIDE\t(ets_isr_mask = 0x40000f98);\nPROVIDE\t(ets_isr_unmask = 0x40000fa8);\nPROVIDE\t(ets_set_user_start = 0x40000fbc);\nPROVIDE\t(ets_memset = 0x400018a4);\nPROVIDE\t(ets_memcpy = 0x400018b4);\nPROVIDE\t(ets_memcmp = 0x400018d4);\nPROVIDE\t(ets_write_char = 0x40001da0);\nPROVIDE\t(ets_vprintf = 0x40001f00);\nPROVIDE\t(ets_install_putc1 = 0x4000242c);\nPROVIDE\t(ets_printf = 0x400024cc);\nPROVIDE\t(rtc_get_reset_reason = 0x400025e0);\nPROVIDE\t(ets_strcpy = 0x40002a88);\nPROVIDE\t(ets_strncpy = 0x40002a98);\nPROVIDE\t(ets_strcmp = 0x40002aa8);\nPROVIDE\t(ets_strncmp = 0x40002ab8);\nPROVIDE\t(ets_strlen = 0x40002ac8);\nPROVIDE\t(ets_bzero = 0x40002ae8);\nPROVIDE\t(ets_timer_setfn = 0x40002c48);\nPROVIDE\t(timer_insert = 0x40002c64);\nPROVIDE\t(ets_timer_disarm = 0x40002d40);\nPROVIDE\t(ets_timer_init = 0x40002e68);\nPROVIDE\t(ets_delay_us = 0x40002ecc);\nPROVIDE\t(ets_update_cpu_frequency = 0x40002f04);\nPROVIDE\t(ets_get_cpu_frequency = 0x40002f0c);\nPROVIDE\t(ets_wdt_get_mode = 0x40002f34);\nPROVIDE\t(roundup2 = 0x400031b4);\nPROVIDE\t(uart_buff_switch = 0x400038a4);\nPROVIDE\t(uart_div_modify = 0x400039d8);\nPROVIDE\t(Uart_Init = 0x40003a14);\nPROVIDE\t(SelectSpiFunction = 0x40003f58);\nPROVIDE\t(SPI_read_status = 0x400043c8);\nPROVIDE\t(SPI_write_status = 0x40004400);\nPROVIDE\t(Wait_SPI_Idle = 0x4000448c);\nPROVIDE\t(SPIFlashCnfig = 0x40004568);\nPROVIDE\t(Cache_Read_Enable = 0x40004678);\nPROVIDE\t(Cache_Read_Disable = 0x400047f0);\nPROVIDE\t(SPIReadModeCnfig = 0x400048ec);\nPROVIDE\t(SPIEraseBlock = 0x400049b4);\nPROVIDE\t(SPIEraseSector = 0x40004a00);\nPROVIDE\t(SPIWrite = 0x40004a4c);\nPROVIDE\t(gpio_output_set = 0x40004cd0);\nPROVIDE\t(gpio_pin_intr_state_set = 0x40004d90);\nPROVIDE\t(lldesc_build_chain = 0x40004f40);\nPROVIDE\t(lldesc_num2link = 0x40005050);\nPROVIDE\t(rom_chip_v5_disable_cca = 0x400060d0);\nPROVIDE\t(rom_chip_v5_enable_cca = 0x400060ec);\nPROVIDE\t(phy_get_romfuncs = 0x40006b08);\nPROVIDE\t(rom_i2c_readReg = 0x40007268);\nPROVIDE\t(rom_i2c_writeReg = 0x400072d8);\nPROVIDE\t(rom_i2c_writeReg_Mask = 0x4000730c);\nPROVIDE\t(aes_unwrap = 0x40009410);\nPROVIDE\t(hmac_md5 = 0x4000a2cc);\nPROVIDE\t(SHA1Init = 0x4000b584);\nPROVIDE\t(SHA1Update = 0x4000b5a8);\nPROVIDE\t(SHA1Final = 0x4000b648);\nPROVIDE\t(pbkdf2_sha1 = 0x4000b840);\nPROVIDE\t(hmac_sha1_vector = 0x4000b8b4);\nPROVIDE\t(hmac_sha1 = 0x4000ba28);\nPROVIDE\t(sha1_prf = 0x4000ba48);\nPROVIDE\t(__addsf3 = 0x4000c180);\nPROVIDE\t(__subsf3 = 0x4000c268);\nPROVIDE\t(__mulsf3 = 0x4000c3dc);\nPROVIDE\t(__fixunssfsi = 0x4000c4c4);\nPROVIDE\t(__muldf3 = 0x4000c8f0);\nPROVIDE\t(__divdf3 = 0x4000cb94);\nPROVIDE\t(__fixdfsi = 0x4000ccb8);\nPROVIDE\t(__truncdfsf2 = 0x4000cd5c);\nPROVIDE\t(__divdi3 = 0x4000ce60);\nPROVIDE\t(__umoddi3 = 0x4000d770);\nPROVIDE\t(__divsi3 = 0x4000dc88);\nPROVIDE\t(rc4_skip = 0x4000dd68);\nPROVIDE\t(memcpy = 0x4000df48);\nPROVIDE\t(memset = 0x4000e190);\nPROVIDE\t(__udivsi3 = 0x4000e21c);\nPROVIDE\t(__umodsi3 = 0x4000e268);\nPROVIDE\t(__floatunsisf = 0x4000e2a4);\nPROVIDE\t(__floatsisf = 0x4000e2ac);\nPROVIDE\t(__floatunsidf = 0x4000e2e8);\nPROVIDE\t(__floatsidf = 0x4000e2f0);\nPROVIDE\t(_stext = 0x40100000);\nPROVIDE\t(_text_start = 0x40100000);\nPROVIDE\t(jump_boot = 0x40100000);\nPROVIDE\t(set_qspi_flash_cache = 0x40100024);\nPROVIDE\t(uart1_write_char = 0x40100074);\nPROVIDE\t(call_jump_boot = 0x401000cc);\nPROVIDE\t(uart0_write_char = 0x4010013c);\nPROVIDE\t(user_uart_wait_tx_fifo_empty = 0x4010018c);\nPROVIDE\t(ets_timer_arm_new = 0x401001d0);\nPROVIDE\t(lmacIsActive = 0x401002a4);\nPROVIDE\t(lmacIsIdle = 0x401002b8);\nPROVIDE\t(lmacSetAcParam = 0x40100754);\nPROVIDE\t(lmacProcessTXStartData = 0x401007a8);\nPROVIDE\t(lmacProcessTxSuccess = 0x40100928);\nPROVIDE\t(GetAccess = 0x40100a6c);\nPROVIDE\t(lmacDiscardAgedMSDU = 0x40100a78);\nPROVIDE\t(lmacRecycleMPDU = 0x40100a8c);\nPROVIDE\t(lmacProcessTxTimeout = 0x40101064);\nPROVIDE\t(lmacProcessAllTxTimeout = 0x401010cc);\nPROVIDE\t(lmacProcessCollisions = 0x401010e0);\nPROVIDE\t(lmacProcessCollision = 0x40101140);\nPROVIDE\t(lmacMSDUAged = 0x401011c4);\nPROVIDE\t(lmacProcessCtsTimeout = 0x40101554);\nPROVIDE\t(lmacProcessAckTimeout = 0x4010158c);\nPROVIDE\t(lmacProcessRtsStart = 0x401015e4);\nPROVIDE\t(lmacProcessTxRtsError = 0x401015f0);\nPROVIDE\t(lmacProcessTxError = 0x40101690);\nPROVIDE\t(lmacTxFrame = 0x40101720);\nPROVIDE\t(lmacRxDone = 0x401018bc);\nPROVIDE\t(prvInsertBlockIntoFreeList = 0x401018dc);\nPROVIDE\t(pvPortMalloc = 0x40101924);\nPROVIDE\t(vPortFree = 0x401019d4);\nPROVIDE\t(pvPortCalloc = 0x40101a24);\nPROVIDE\t(pvPortZalloc = 0x40101a54);\nPROVIDE\t(pvPortRealloc = 0x40101a68);\nPROVIDE\t(xPortGetFreeHeapSize = 0x40101aa0);\nPROVIDE\t(vPortInitialiseBlocks = 0x40101aa8);\nPROVIDE\t(xPortWantedSizeAlign = 0x40101aac);\nPROVIDE\t(register_phy_ops = 0x40101ac4);\nPROVIDE\t(register_get_phy_addr = 0x40101ae4);\nPROVIDE\t(phy_change_channel = 0x40101aec);\nPROVIDE\t(phy_get_mactime = 0x40101b04);\nPROVIDE\t(phy_debug_print = 0x40101b24);\nPROVIDE\t(phy_adc_read_fast = 0x40101b84);\nPROVIDE\t(unsign_to_sign = 0x40101dc8);\nPROVIDE\t(phy_get_bb_freqoffset = 0x40101e04);\nPROVIDE\t(phy_get_bb_evm = 0x40101e6c);\nPROVIDE\t(pm_rtc_clock_cali = 0x40101e88);\nPROVIDE\t(clockgate_watchdog = 0x40101f44);\nPROVIDE\t(pp_soft_wdt_feed_local = 0x40101fa8);\nPROVIDE\t(ppProcessTxQ = 0x4010203c);\nPROVIDE\t(ppFetchTxQFirstAvail = 0x401020b0);\nPROVIDE\t(ppDequeueTxQ = 0x401020f0);\nPROVIDE\t(ppRollBackTxQ = 0x40102118);\nPROVIDE\t(ppRecordBarRRC = 0x4010213c);\nPROVIDE\t(ppTxqUpdateBitmap = 0x4010214c);\nPROVIDE\t(ppEnqueueTxDone = 0x40102174);\nPROVIDE\t(ppEnqueueRxq = 0x401021a8);\nPROVIDE\t(ppDiscardMPDU = 0x40102690);\nPROVIDE\t(pp_post = 0x401026b4);\nPROVIDE\t(pp_post2 = 0x40102740);\nPROVIDE\t(ppCalTxop = 0x40102768);\nPROVIDE\t(ppCalFrameTimes = 0x401027e8);\nPROVIDE\t(RC_GetAckRate = 0x40102878);\nPROVIDE\t(RC_GetRtsRate = 0x40102884);\nPROVIDE\t(RC_GetAckTime = 0x40102894);\nPROVIDE\t(RC_GetCtsTime = 0x401028a8);\nPROVIDE\t(RC_GetBlockAckTime = 0x401028e0);\nPROVIDE\t(copy_s4d1 = 0x40102950);\nPROVIDE\t(copy_s1d4 = 0x401029e4);\nPROVIDE\t(eRamRead = 0x40102a7c);\nPROVIDE\t(eRamWrite = 0x40102aa4);\nPROVIDE\t(rom_strlen = 0x40102ac8);\nPROVIDE\t(rom_strcpy = 0x40102afc);\nPROVIDE\t(rom_xstrcpy = 0x40102b60);\nPROVIDE\t(rom_xstrcmp = 0x40102bb0);\nPROVIDE\t(rom_strchr = 0x40102bf8);\nPROVIDE\t(get_align4_chr = 0x40102c34);\nPROVIDE\t(write_align4_chr = 0x40102c4c);\nPROVIDE\t(Cache_Read_Enable_New = 0x40102c6c);\nPROVIDE\t(spi_flash_read = 0x40102c90);\nPROVIDE\t(spi_flash_get_id = 0x40102d98);\nPROVIDE\t(spi_flash_read_status = 0x40102de8);\nPROVIDE\t(spi_flash_write_status = 0x40102e24);\nPROVIDE\t(spi_flash_erase_sector = 0x40102e60);\nPROVIDE\t(spi_flash_write = 0x40102eb0);\nPROVIDE\t(spi_flash_erase_block = 0x40102f18);\nPROVIDE\t(tcp_accept_null = 0x40102f60);\nPROVIDE\t(tcp_new_port = 0x40102f78);\nPROVIDE\t(tcp_close_shutdown = 0x4010300c);\nPROVIDE\t(dns_timer = 0x40103164);\nPROVIDE\t(igmp_timer = 0x40103190);\nPROVIDE\t(dhcp_timer_fine = 0x401031bc);\nPROVIDE\t(dhcp_timer_coarse = 0x401031f0);\nPROVIDE\t(rcUpdateTxDone = 0x401033ec);\nPROVIDE\t(rcUpdateRxDone = 0x40103480);\nPROVIDE\t(rcUpdateDataRxDone = 0x401034dc);\nPROVIDE\t(rcGetSched = 0x401034f8);\nPROVIDE\t(rcGetRate = 0x401035dc);\nPROVIDE\t(rcReachRetryLimit = 0x40103af0);\nPROVIDE\t(trc_NeedRTS = 0x40103b08);\nPROVIDE\t(os_printf_plus = 0x40103bd8);\nPROVIDE\t(system_restart_core = 0x40103d04);\nPROVIDE\t(system_deep_sleep_local_2 = 0x40103d40);\nPROVIDE\t(system_get_time = 0x40103db0);\nPROVIDE\t(system_os_post = 0x40103dc8);\nPROVIDE\t(system_rtc_mem_write = 0x40103dfc);\nPROVIDE\t(system_rtc_mem_read = 0x40103e54);\nPROVIDE\t(wDev_MacTim1SetFunc = 0x40104250);\nPROVIDE\t(wDev_MacTim1Arm = 0x40104270);\nPROVIDE\t(wDev_ProcessFiq = 0x40104308);\nPROVIDE\t(wDev_EnableTransmit = 0x4010464c);\nPROVIDE\t(wDev_DisableTransmit = 0x40104684);\nPROVIDE\t(Tx_Copy2Queue = 0x401046a4);\nPROVIDE\t(wDev_ProcessCollision = 0x401046ec);\nPROVIDE\t(wDev_GetTxqCollisions = 0x40104710);\nPROVIDE\t(wDev_ClearTxqCollisions = 0x40104724);\nPROVIDE\t(wDev_SetWaitingQueue = 0x40104740);\nPROVIDE\t(wDev_ClearWaitingQueue = 0x40104788);\nPROVIDE\t(wDev_SetFrameAckType = 0x401047ac);\nPROVIDE\t(wDev_AppendRxBlocks = 0x40104810);\nPROVIDE\t(wDev_AppendRxAmpduLensBlocks = 0x40104954);\nPROVIDE\t(wDev_GetBAInfo = 0x40104a28);\nPROVIDE\t(wDevDisableRx = 0x40104a5c);\nPROVIDE\t(store_exception_error = 0x40104f1c);\nPROVIDE\t(fatal_error = 0x40104f54);\nPROVIDE\t(default_exception_handler = 0x40104f70);\nPROVIDE\t(chm_get_current_channel = 0x40104f88);\nPROVIDE\t(__divsf3_aux = 0x40104f94);\nPROVIDE\t(__divsf3 = 0x40105010);\nPROVIDE\t(__fixsfsi = 0x401050cc);\nPROVIDE\t(esf_rx_buf_alloc = 0x40105110);\nPROVIDE\t(uart_intr_handler = 0x40105170);\nPROVIDE\t(uart0_set_tout = 0x40105294);\nPROVIDE\t(uart_tx_buf = 0x401052e0);\nPROVIDE\t(uart_task = 0x40105338);\nPROVIDE\t(uart_del_rx_chars = 0x4010537c);\nPROVIDE\t(tcp2uart_send_rxbuf = 0x401053ec);\nPROVIDE\t(tcp2uart_send_tx_buf = 0x40105454);\nPROVIDE\t(GPIO_intr_handler = 0x4010549c);\nPROVIDE\t(Swapws = 0x401054c0);\nPROVIDE\t(MdbWordR = 0x401054e0);\nPROVIDE\t(MdbWordRW = 0x4010550c);\nPROVIDE\t(__ashrdi3 = 0x40105588);\nPROVIDE\t(__modsi3 = 0x401055a0);\nPROVIDE\t(__lshrdi3 = 0x401055ec);\nPROVIDE\t(eraminfo = 0x40105604);\nPROVIDE\t(_etext = 0x4010560c);\nPROVIDE\t(_lit4_start = 0x4010560c);\nPROVIDE\t(_text_end = 0x4010560c);\nPROVIDE\t(check_timeouts_timer = 0x4010560c);\nPROVIDE\t(lwip_if_queues = 0x40105620);\nPROVIDE\t(hostname = 0x40105628);\nPROVIDE\t(xBlockAllocatedBit = 0x4010562c);\nPROVIDE\t(xFreeBytesRemaining = 0x40105630);\nPROVIDE\t(pxEnd = 0x40105634);\nPROVIDE\t(netif_default = 0x40105638);\nPROVIDE\t(netif_list = 0x4010563c);\nPROVIDE\t(raw_pcbs = 0x40105640);\nPROVIDE\t(flash_size = 0x40105644);\nPROVIDE\t(flash_read = 0x40105648);\nPROVIDE\t(tcp_tmp_pcb = 0x4010564c);\nPROVIDE\t(tcp_tw_pcbs = 0x40105650);\nPROVIDE\t(tcp_active_pcbs = 0x40105654);\nPROVIDE\t(tcp_bound_pcbs = 0x40105658);\nPROVIDE\t(tcp_ticks = 0x4010565c);\nPROVIDE\t(tcp_input_pcb = 0x40105660);\nPROVIDE\t(recv_data = 0x40105664);\nPROVIDE\t(ackno = 0x40105668);\nPROVIDE\t(tcphdr = 0x4010566c);\nPROVIDE\t(tcpip_tcp_timer_active = 0x40105670);\nPROVIDE\t(timeouts_last_time = 0x40105674);\nPROVIDE\t(next_timeout = 0x40105678);\nPROVIDE\t(udp_pcbs = 0x4010567c);\nPROVIDE\t(dhcps_lease_time = 0x40105680);\nPROVIDE\t(renew = 0x40105684);\nPROVIDE\t(plist = 0x40105688);\nPROVIDE\t(dhcps_lease_flag = 0x4010568c);\nPROVIDE\t(pcb_dhcps = 0x40105690);\nPROVIDE\t(dns_payload = 0x40105694);\nPROVIDE\t(dns_pcb = 0x40105698);\nPROVIDE\t(igmp_group_list = 0x4010569c);\nPROVIDE\t(buf_scan_infos = 0x401056a0);\nPROVIDE\t(total_scan_infos = 0x40105e20);\nPROVIDE\t(flg_wifi_sleep_enable = 0x40105e24);\nPROVIDE\t(st_disconn_timer = 0x40105e28);\nPROVIDE\t(flg_sleep = 0x40105e3c);\nPROVIDE\t(st_reconn_flg = 0x40105e40);\nPROVIDE\t(st_reconn_count = 0x40105e44);\nPROVIDE\t(flg_open_all_service = 0x40105e48);\nPROVIDE\t(probe_requests_count = 0x40105e4c);\nPROVIDE\t(buf_probe_requests = 0x40105e50);\nPROVIDE\t(sntp = 0x40106050);\nPROVIDE\t(pcb_cdns = 0x40106054);\nPROVIDE\t(uart_drv = 0x40106058);\nPROVIDE\t(tcp2uart_servcfg = 0x40106088);\nPROVIDE\t(tcp2uart_conn = 0x4010608c);\nPROVIDE\t(numFiles = 0x40106090);\nPROVIDE\t(fatCacheID = 0x40106094);\nPROVIDE\t(WEBFSStubs = 0x40106098);\nPROVIDE\t(isWEBFSLocked = 0x40106218);\nPROVIDE\t(disk_base_addr = 0x4010621c);\nPROVIDE\t(phcfg = 0x40106220);\nPROVIDE\t(ovl_call = 0x40106224);\nPROVIDE\t(lock_sntp_time = 0x40106228);\nPROVIDE\t(mdb_mactime = 0x4010622c);\nPROVIDE\t(ret_funcs = 0x40106234);\nPROVIDE\t(arg_funcs = 0x40106238);\nPROVIDE\t(gpio_fun_pin_num = 0x4010623c);\nPROVIDE\t(mdbiosize = 0x40106240);\nPROVIDE\t(mdb_tcp_conn = 0x40106244);\nPROVIDE\t(mdb_tcp_servcfg = 0x40106248);\nPROVIDE\t(wdrv_bufn = 0x4010624c);\nPROVIDE\t(_lit4_end = 0x40106250);\nPROVIDE\t(_irom0_text_start = 0x40207000);\nPROVIDE\t(puts_buf = 0x40207004);\nPROVIDE\t(read_wifi_config = 0x40207048);\nPROVIDE\t(uart_wait_tx_fifo_empty = 0x402070e8);\nPROVIDE\t(read_macaddr_from_otp = 0x40207104);\nPROVIDE\t(tst_cfg_wifi = 0x40207170);\nPROVIDE\t(startup_uart_init = 0x40207290);\nPROVIDE\t(init_wifi = 0x40207304);\nPROVIDE\t(startup = 0x40207450);\nPROVIDE\t(init_fn = 0x40207734);\nPROVIDE\t(eagle_lwip_if_alloc = 0x40207780);\nPROVIDE\t(eagle_lwip_getif = 0x402078f8);\nPROVIDE\t(task_if0 = 0x40207918);\nPROVIDE\t(task_if1 = 0x40207950);\nPROVIDE\t(eagle_lwip_if_free = 0x40207988);\nPROVIDE\t(free_entry = 0x402079e0);\nPROVIDE\t(find_entry = 0x40207a3c);\nPROVIDE\t(etharp_send_ip = 0x40207b18);\nPROVIDE\t(update_arp_entry = 0x40207b6c);\nPROVIDE\t(etharp_tmr = 0x40207c10);\nPROVIDE\t(etharp_find_addr = 0x40207c68);\nPROVIDE\t(etharp_request = 0x40207cbc);\nPROVIDE\t(etharp_output_to_arp_index = 0x40207d8c);\nPROVIDE\t(etharp_query = 0x40207e04);\nPROVIDE\t(etharp_output = 0x40207fb4);\nPROVIDE\t(ethernet_input = 0x402080a4);\nPROVIDE\t(etharp_cleanup_netif = 0x402082a0);\nPROVIDE\t(ieee80211_rate_ref_init = 0x40208368);\nPROVIDE\t(ieee80211_freedom_inside_cb = 0x40208380);\nPROVIDE\t(ieee80211_freedom_init = 0x402083b0);\nPROVIDE\t(ieee80211_user_ie_init = 0x402083d4);\nPROVIDE\t(ieee80211_ifattach = 0x402083f0);\nPROVIDE\t(ieee80211_mhz2ieee = 0x40208458);\nPROVIDE\t(ieee80211_chan2ieee = 0x402084b8);\nPROVIDE\t(ieee80211_ieee2mhz = 0x402084d4);\nPROVIDE\t(ieee80211_find_channel = 0x40208514);\nPROVIDE\t(ieee80211_find_channel_byieee = 0x40208540);\nPROVIDE\t(wifi_mode_set = 0x40208594);\nPROVIDE\t(get_iav_key = 0x40208770);\nPROVIDE\t(register_ieee80211_action_vendor_get_key_cb = 0x40208790);\nPROVIDE\t(unregister_ieee80211_action_vendor_get_key_cb = 0x402087a4);\nPROVIDE\t(ieee80211_add_action_vendor_spec_esp = 0x402087bc);\nPROVIDE\t(ieee80211_alloc_action_vendor_spec = 0x40208804);\nPROVIDE\t(ieee80211_send_action_vendor_spec = 0x40208914);\nPROVIDE\t(ieee80211_recv_action_vendor_spec = 0x40208aac);\nPROVIDE\t(ieee80211_action_vendor_spec_attach = 0x40208bb8);\nPROVIDE\t(register_ieee80211_action_vendor_spec_cb = 0x40208bf8);\nPROVIDE\t(unregister_ieee80211_action_vendor_spec_cb = 0x40208c0c);\nPROVIDE\t(ieee80211_crypto_attach = 0x40208c18);\nPROVIDE\t(ieee80211_crypto_available = 0x40208c1c);\nPROVIDE\t(ieee80211_crypto_setkey = 0x40208c20);\nPROVIDE\t(ieee80211_crypto_encap = 0x40208c24);\nPROVIDE\t(ieee80211_crypto_decap = 0x40208c7c);\nPROVIDE\t(ieee80211_getmgtframe = 0x40208cec);\nPROVIDE\t(ieee80211_hostap_attach = 0x40209390);\nPROVIDE\t(hostap_handle_timer = 0x40209494);\nPROVIDE\t(hostap_input = 0x4020952c);\nPROVIDE\t(wifi_softap_start = 0x4020a4ac);\nPROVIDE\t(wifi_softap_stop = 0x4020a618);\nPROVIDE\t(ieee80211_ht_attach = 0x4020a7c0);\nPROVIDE\t(ieee80211_ht_node_init = 0x4020a814);\nPROVIDE\t(ieee80211_ht_node_cleanup = 0x4020a854);\nPROVIDE\t(ieee80211_parse_htcap = 0x4020a88c);\nPROVIDE\t(ieee80211_ht_updateparams = 0x4020a98c);\nPROVIDE\t(ieee80211_setup_htrates = 0x4020aaa4);\nPROVIDE\t(ieee80211_setup_basic_htrates = 0x4020ab70);\nPROVIDE\t(ieee80211_add_htcap = 0x4020aebc);\nPROVIDE\t(ieee80211_add_htcap_vendor = 0x4020aed8);\nPROVIDE\t(ieee80211_add_htinfo = 0x4020affc);\nPROVIDE\t(ieee80211_add_htinfo_vendor = 0x4020b018);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_head = 0x4020b258);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_mesh_assoc = 0x4020b290);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_mesh_group = 0x4020b314);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_simple_pair = 0x4020b344);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_freq_annon = 0x4020b394);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_now = 0x4020b3cc);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_ssid = 0x4020b404);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_manufacturer = 0x4020b444);\nPROVIDE\t(ieee80211_deliver_data = 0x4020b494);\nPROVIDE\t(ieee80211_decap = 0x4020b4e8);\nPROVIDE\t(ieee80211_setup_rates = 0x4020b5ec);\nPROVIDE\t(ieee80211_alloc_challenge = 0x4020b65c);\nPROVIDE\t(ieee80211_parse_beacon = 0x4020b698);\nPROVIDE\t(ieee80211_parse_wpa = 0x4020bc6c);\nPROVIDE\t(ieee80211_parse_rsn = 0x4020bd80);\nPROVIDE\t(ieee80211_parse_action = 0x4020be80);\nPROVIDE\t(ieee80211_setup_rateset = 0x4020bf1c);\nPROVIDE\t(ieee80211_mesh_quick_init = 0x4020bf2c);\nPROVIDE\t(ieee80211_mesh_quick_deinit = 0x4020bf9c);\nPROVIDE\t(ieee80211_mesh_quick_set = 0x4020bfcc);\nPROVIDE\t(ieee80211_mesh_quick_get = 0x4020c0c8);\nPROVIDE\t(ieee80211_mesh_quick_ie_add = 0x4020c194);\nPROVIDE\t(ieee80211_output_pbuf = 0x4020c1cc);\nPROVIDE\t(ieee80211_send_setup = 0x4020c43c);\nPROVIDE\t(ieee80211_mgmt_output = 0x4020c570);\nPROVIDE\t(ieee80211_tx_mgt_cb = 0x4020c654);\nPROVIDE\t(ieee80211_send_nulldata = 0x4020c65c);\nPROVIDE\t(ieee80211_add_rates = 0x4020cac8);\nPROVIDE\t(ieee80211_add_xrates = 0x4020cb18);\nPROVIDE\t(ieee80211_send_probereq = 0x4020cbe8);\nPROVIDE\t(ieee80211_getcapinfo = 0x4020cdfc);\nPROVIDE\t(ieee80211_send_mgmt = 0x4020ce5c);\nPROVIDE\t(ieee80211_alloc_proberesp = 0x4020d40c);\nPROVIDE\t(ieee80211_send_proberesp = 0x4020d5e8);\nPROVIDE\t(ieee80211_alloc_deauth = 0x4020d730);\nPROVIDE\t(ieee80211_send_deauth = 0x4020d770);\nPROVIDE\t(ieee80211_freedom_output = 0x4020d8ac);\nPROVIDE\t(ieee80211_beacon_alloc = 0x4020dc9c);\nPROVIDE\t(ieee80211_phy_init = 0x4020de34);\nPROVIDE\t(ieee80211_phy_type_get = 0x4020de68);\nPROVIDE\t(ieee80211_setup_ratetable = 0x4020de84);\nPROVIDE\t(ieee80211_psq_init = 0x4020df14);\nPROVIDE\t(ieee80211_psq_cleanup = 0x4020df34);\nPROVIDE\t(ieee80211_set_tim = 0x4020df3c);\nPROVIDE\t(ieee80211_pwrsave = 0x4020df7c);\nPROVIDE\t(pwrsave_flushq = 0x4020dfe4);\nPROVIDE\t(ieee80211_node_pwrsave = 0x4020e094);\nPROVIDE\t(ieee80211_proto_attach = 0x4020e0d0);\nPROVIDE\t(ieee80211_set_shortslottime = 0x4020e0f8);\nPROVIDE\t(ieee80211_iserp_rateset = 0x4020e114);\nPROVIDE\t(ieee80211_wme_initparams = 0x4020e148);\nPROVIDE\t(ieee80211_wme_updateparams = 0x4020e14c);\nPROVIDE\t(ieee80211_mlme_connect_bss = 0x4020e154);\nPROVIDE\t(ieee80211_rfid_locp_recv_open = 0x4020e1d4);\nPROVIDE\t(ieee80211_rfid_locp_recv_close = 0x4020e210);\nPROVIDE\t(ieee80211_rfid_locp_recv_reset = 0x4020e228);\nPROVIDE\t(ieee80211_rfid_locp_recv = 0x4020e248);\nPROVIDE\t(register_ieee80211_rfid_locp_recv_cb = 0x4020e264);\nPROVIDE\t(unregister_ieee80211_rfid_locp_recv_cb = 0x4020e278);\nPROVIDE\t(ieee80211_scan_attach = 0x4020e290);\nPROVIDE\t(scan_start = 0x4020e324);\nPROVIDE\t(scan_pm_channel_op_cb = 0x4020e4e4);\nPROVIDE\t(scan_cancel = 0x4020e684);\nPROVIDE\t(scan_add_bssid = 0x4020e7e0);\nPROVIDE\t(scan_remove_bssid = 0x4020e804);\nPROVIDE\t(scan_hidden_ssid = 0x4020e810);\nPROVIDE\t(scan_add_probe_ssid = 0x4020e818);\nPROVIDE\t(scan_remove_probe_ssid = 0x4020e86c);\nPROVIDE\t(scan_clear_channles = 0x4020e9ac);\nPROVIDE\t(scan_set_desChan = 0x4020ea20);\nPROVIDE\t(scan_get_type = 0x4020ea2c);\nPROVIDE\t(cannel_scan_connect_state = 0x4020ea34);\nPROVIDE\t(scan_connect_state = 0x4020ea4c);\nPROVIDE\t(scan_check_hidden = 0x4020ea94);\nPROVIDE\t(scan_profile_check = 0x4020eac8);\nPROVIDE\t(scan_parse_beacon = 0x4020ee74);\nPROVIDE\t(sta_status_set = 0x4020f244);\nPROVIDE\t(ieee80211_sta_new_state = 0x4020f2b0);\nPROVIDE\t(sta_input = 0x4020f640);\nPROVIDE\t(ieee80211_parse_wmeparams = 0x4020fb8c);\nPROVIDE\t(wifi_station_start = 0x40210188);\nPROVIDE\t(wifi_station_stop = 0x402101f8);\nPROVIDE\t(ic_get_addr = 0x40210254);\nPROVIDE\t(ic_set_opmode = 0x40210260);\nPROVIDE\t(ic_enable_interface = 0x40210274);\nPROVIDE\t(ic_interface_enabled = 0x402102c4);\nPROVIDE\t(ic_disable_interface = 0x402102d8);\nPROVIDE\t(ic_is_pure_sta = 0x40210320);\nPROVIDE\t(ic_get_ptk_alg = 0x4021033c);\nPROVIDE\t(ic_get_gtk_alg = 0x4021034c);\nPROVIDE\t(ic_set_ptk_alg = 0x4021035c);\nPROVIDE\t(ic_set_gtk_alg = 0x4021036c);\nPROVIDE\t(ic_interface_is_p2p = 0x4021037c);\nPROVIDE\t(ic_set_vif = 0x40210414);\nPROVIDE\t(ic_set_sta = 0x402104d4);\nPROVIDE\t(ic_bss_info_update = 0x402105ac);\nPROVIDE\t(ic_set_key = 0x40210608);\nPROVIDE\t(ic_remove_key = 0x40210664);\nPROVIDE\t(ic_get_rssi = 0x40210678);\nPROVIDE\t(lwip_init = 0x402106b4);\nPROVIDE\t(ip_route = 0x402106f4);\nPROVIDE\t(ip_input = 0x4021077c);\nPROVIDE\t(ip_output_if_opt = 0x402109dc);\nPROVIDE\t(ip_output_if = 0x40210bf0);\nPROVIDE\t(ip_output = 0x40210c18);\nPROVIDE\t(ip_router = 0x40210c68);\nPROVIDE\t(ip4_addr_isbroadcast = 0x40210cc4);\nPROVIDE\t(ip4_addr_netmask_valid = 0x40210d04);\nPROVIDE\t(ipaddr_aton = 0x40210d50);\nPROVIDE\t(ipaddr_addr = 0x40210f3c);\nPROVIDE\t(ipaddr_ntoa_r = 0x40210f58);\nPROVIDE\t(ipaddr_ntoa = 0x4021102c);\nPROVIDE\t(lmacInitAc = 0x40211044);\nPROVIDE\t(lmacInit = 0x40211078);\nPROVIDE\t(lmacSetRetryLimit = 0x40211128);\nPROVIDE\t(prvHeapInit = 0x40211160);\nPROVIDE\t(netif_init = 0x402111a0);\nPROVIDE\t(netif_find = 0x402111a4);\nPROVIDE\t(netif_set_default = 0x402111dc);\nPROVIDE\t(netif_set_ipaddr = 0x402111ec);\nPROVIDE\t(netif_set_addr = 0x40211258);\nPROVIDE\t(netif_add = 0x40211290);\nPROVIDE\t(netif_set_netmask = 0x40211300);\nPROVIDE\t(netif_set_gw = 0x4021130c);\nPROVIDE\t(netif_set_up = 0x40211318);\nPROVIDE\t(netif_set_down = 0x40211354);\nPROVIDE\t(netif_remove = 0x40211374);\nPROVIDE\t(netif_set_link_up = 0x402113d8);\nPROVIDE\t(netif_set_link_down = 0x40211424);\nPROVIDE\t(_sprintf_out = 0x4021143c);\nPROVIDE\t(__wrap_os_printf_plus = 0x4021147c);\nPROVIDE\t(ets_sprintf = 0x402114e0);\nPROVIDE\t(pbuf_header = 0x4021152c);\nPROVIDE\t(pbuf_ref = 0x402115bc);\nPROVIDE\t(pbuf_free = 0x402115c8);\nPROVIDE\t(pbuf_alloc = 0x4021162c);\nPROVIDE\t(pbuf_realloc = 0x40211790);\nPROVIDE\t(pbuf_clen = 0x402117e0);\nPROVIDE\t(pbuf_cat = 0x402117f4);\nPROVIDE\t(pbuf_chain = 0x40211820);\nPROVIDE\t(pbuf_dechain = 0x4021183c);\nPROVIDE\t(pbuf_copy = 0x40211870);\nPROVIDE\t(pbuf_copy_partial = 0x4021193c);\nPROVIDE\t(pbuf_take = 0x402119ec);\nPROVIDE\t(pbuf_coalesce = 0x40211a68);\nPROVIDE\t(pbuf_get_at = 0x40211aa8);\nPROVIDE\t(pbuf_memcmp = 0x40211acc);\nPROVIDE\t(pbuf_memfind = 0x40211b40);\nPROVIDE\t(pbuf_strstr = 0x40211ba4);\nPROVIDE\t(rf_init = 0x40211bf0);\nPROVIDE\t(bb_init = 0x40211c0c);\nPROVIDE\t(phy_init = 0x40211c24);\nPROVIDE\t(RFChannelSel = 0x40211c54);\nPROVIDE\t(phy_delete_channel = 0x40211c70);\nPROVIDE\t(phy_enable_agc = 0x40211c88);\nPROVIDE\t(phy_disable_agc = 0x40211ca0);\nPROVIDE\t(phy_initialize_bb = 0x40211cb8);\nPROVIDE\t(phy_set_sense = 0x40211cd0);\nPROVIDE\t(ram_tx_mac_enable = 0x40211ce8);\nPROVIDE\t(ram_tx_mac_disable = 0x40211cec);\nPROVIDE\t(rtc_mem_backup = 0x40211cf0);\nPROVIDE\t(rtc_mem_recovery = 0x40211d20);\nPROVIDE\t(set_cal_rxdc = 0x40211d54);\nPROVIDE\t(set_rx_gain_cal_iq = 0x40211e0c);\nPROVIDE\t(gen_rx_gain_table = 0x40212164);\nPROVIDE\t(pbus_set_rxbbgain = 0x402122bc);\nPROVIDE\t(set_rx_gain_testchip_50 = 0x40212340);\nPROVIDE\t(ram_get_corr_power = 0x40212678);\nPROVIDE\t(check_data_func = 0x40212768);\nPROVIDE\t(do_noisefloor_lsleep_v50 = 0x40212788);\nPROVIDE\t(do_noisefloor = 0x402127bc);\nPROVIDE\t(start_dig_rx = 0x40212830);\nPROVIDE\t(stop_dig_rx = 0x40212878);\nPROVIDE\t(chip_v6_set_chanfreq = 0x402128a4);\nPROVIDE\t(tx_cap_init = 0x402128d8);\nPROVIDE\t(target_power_add_backoff = 0x40212ac4);\nPROVIDE\t(tx_pwctrl_init_cal = 0x40212af4);\nPROVIDE\t(tx_atten_set_interp = 0x40212c6c);\nPROVIDE\t(check_tx_pwr_cal = 0x40212ecc);\nPROVIDE\t(tx_pwctrl_init = 0x40213010);\nPROVIDE\t(ram_get_noisefloor = 0x40213134);\nPROVIDE\t(get_noisefloor_sat = 0x40213150);\nPROVIDE\t(ram_set_noise_floor = 0x40213180);\nPROVIDE\t(ram_start_noisefloor = 0x402131dc);\nPROVIDE\t(read_hw_noisefloor = 0x40213228);\nPROVIDE\t(noise_check_loop = 0x40213254);\nPROVIDE\t(noise_init = 0x402133ac);\nPROVIDE\t(target_power_backoff = 0x402135ac);\nPROVIDE\t(sdt_on_noise_start = 0x40213600);\nPROVIDE\t(chip_v6_set_chan_rx_cmp = 0x40213680);\nPROVIDE\t(chip_v6_set_chan_misc = 0x4021380c);\nPROVIDE\t(phy_dig_spur_set = 0x402138b0);\nPROVIDE\t(phy_dig_spur_prot = 0x40213c08);\nPROVIDE\t(chip_v6_rxmax_ext_dig = 0x40213e40);\nPROVIDE\t(chip_v6_rxmax_ext = 0x40213e8c);\nPROVIDE\t(phy_bb_rx_cfg = 0x40213f38);\nPROVIDE\t(uart_wait_idle = 0x40214350);\nPROVIDE\t(phy_pbus_soc_cfg = 0x4021438c);\nPROVIDE\t(phy_gpio_cfg = 0x40214444);\nPROVIDE\t(tx_cont_en = 0x4021465c);\nPROVIDE\t(tx_cont_dis = 0x40214704);\nPROVIDE\t(tx_cont_cfg = 0x40214758);\nPROVIDE\t(chip_v6_initialize_bb = 0x4021477c);\nPROVIDE\t(periodic_cal = 0x402148e4);\nPROVIDE\t(bbpll_cal = 0x402149c8);\nPROVIDE\t(periodic_cal_top = 0x40214a60);\nPROVIDE\t(register_chipv6_phy_init_param = 0x40214ac0);\nPROVIDE\t(change_bbpll160_sleep = 0x40214d6c);\nPROVIDE\t(change_bbpll160 = 0x40214f1c);\nPROVIDE\t(set_crystal_uart = 0x40214f54);\nPROVIDE\t(ant_switch_init = 0x40214fe4);\nPROVIDE\t(reduce_current_init = 0x40215094);\nPROVIDE\t(rtc_mem_check = 0x40215180);\nPROVIDE\t(phy_afterwake_set_rfoption = 0x402151bc);\nPROVIDE\t(deep_sleep_set_option = 0x402151dc);\nPROVIDE\t(write_data_to_rtc = 0x40215208);\nPROVIDE\t(get_data_from_rtc = 0x40215240);\nPROVIDE\t(register_chipv6_phy = 0x402152d4);\nPROVIDE\t(set_dpd_bypass = 0x40215770);\nPROVIDE\t(set_rf_gain_stage10 = 0x40215798);\nPROVIDE\t(get_vdd33_offset = 0x402157c8);\nPROVIDE\t(get_phy_target_power = 0x4021583c);\nPROVIDE\t(set_most_pwr_reg = 0x402158f0);\nPROVIDE\t(phy_set_most_tpw = 0x402159c4);\nPROVIDE\t(phy_vdd33_set_tpw = 0x402159e4);\nPROVIDE\t(get_adc_rand = 0x402159fc);\nPROVIDE\t(phy_get_rand = 0x40215a2c);\nPROVIDE\t(phy_tx_pwctrl_cali = 0x40215a44);\nPROVIDE\t(phy_check_data_table = 0x40215a6c);\nPROVIDE\t(phy_after_init_enrx = 0x40215aac);\nPROVIDE\t(phy_set_rx11b_reg = 0x40215b10);\nPROVIDE\t(phy_set_powerup_option = 0x40215b44);\nPROVIDE\t(phy_get_txpwr_param = 0x40215b54);\nPROVIDE\t(phy_get_rxnf_param = 0x40215ba0);\nPROVIDE\t(phy_get_freq_param = 0x40215bac);\nPROVIDE\t(ram_pbus_set_rxgain = 0x40215bc0);\nPROVIDE\t(ram_pbus_debugmode = 0x40215c88);\nPROVIDE\t(ram_pbus_xpd_tx_on = 0x40215d3c);\nPROVIDE\t(set_rf_freq_offset = 0x40215da8);\nPROVIDE\t(chip_v6_rxmax_ext_ana = 0x40215e18);\nPROVIDE\t(ram_chip_v6_rx_init = 0x40215f6c);\nPROVIDE\t(tsen_meas = 0x40215f9c);\nPROVIDE\t(readvdd33 = 0x40216048);\nPROVIDE\t(txpwr_offset = 0x40216210);\nPROVIDE\t(set_txcap_reg = 0x402162cc);\nPROVIDE\t(ram_ana_inf_gating_en = 0x4021634c);\nPROVIDE\t(ram_restart_cal = 0x402164ac);\nPROVIDE\t(wait_rfpll_cal_end = 0x40216518);\nPROVIDE\t(ram_rfpll_set_freq = 0x402165a0);\nPROVIDE\t(ram_set_channel_freq = 0x402166a4);\nPROVIDE\t(chip_60_set_channel = 0x4021699c);\nPROVIDE\t(chip_v6_set_chan_offset = 0x40216b3c);\nPROVIDE\t(chip_v6_set_chan = 0x40216b94);\nPROVIDE\t(chip_v6_set_chan_wakeup = 0x40216c38);\nPROVIDE\t(chip_v6_rf_init = 0x40216cac);\nPROVIDE\t(low_power_set = 0x40216f10);\nPROVIDE\t(test_tout = 0x40216f60);\nPROVIDE\t(check_data_flag = 0x402170d8);\nPROVIDE\t(phy_get_check_flag = 0x402170f8);\nPROVIDE\t(phy_get_vdd33 = 0x4021722c);\nPROVIDE\t(txbbgain2dcoindex = 0x402172e0);\nPROVIDE\t(dcoindex2txbbgain = 0x40217300);\nPROVIDE\t(init_cal_dcoffset = 0x40217324);\nPROVIDE\t(set_rfanagain_dc_reg = 0x402173e8);\nPROVIDE\t(set_txdc_pbus = 0x40217484);\nPROVIDE\t(get_rf_gain_qdb = 0x402174f0);\nPROVIDE\t(correct_rf_ana_gain = 0x40217518);\nPROVIDE\t(get_sar_dout = 0x40217620);\nPROVIDE\t(cal_rf_ana_gain = 0x402176ac);\nPROVIDE\t(meas_tone_pwr_db = 0x402177d8);\nPROVIDE\t(tx_pwr_backoff = 0x40217848);\nPROVIDE\t(get_fcc_1m2m_pwr_offset = 0x402179d0);\nPROVIDE\t(ram_set_txbb_atten = 0x40217a0c);\nPROVIDE\t(txiq_get_mis_pwr = 0x40217aa0);\nPROVIDE\t(txiq_cover = 0x40217b44);\nPROVIDE\t(ram_rfcal_txiq = 0x40217d5c);\nPROVIDE\t(rc_cal = 0x40217fc8);\nPROVIDE\t(get_target_power_offset = 0x40218188);\nPROVIDE\t(get_pwctrl_correct = 0x40218290);\nPROVIDE\t(tx_pwctrl_cal = 0x402182e8);\nPROVIDE\t(tx_pwctrl_bg_init = 0x402185e4);\nPROVIDE\t(tx_pwctrl_background = 0x4021865c);\nPROVIDE\t(read_sar_dout = 0x40218718);\nPROVIDE\t(ram_get_fm_sar_dout = 0x4021877c);\nPROVIDE\t(ram_cal_tos_v60 = 0x40218820);\nPROVIDE\t(ram_get_bb_atten = 0x402189f0);\nPROVIDE\t(ram_rfcal_txcap = 0x40218a20);\nPROVIDE\t(ram_rfcal_pwrctrl = 0x40218be4);\nPROVIDE\t(ram_rxiq_get_mis = 0x40218e0c);\nPROVIDE\t(ram_rxiq_cover_mg_mp = 0x40218fd8);\nPROVIDE\t(ram_rfcal_rxiq = 0x4021917c);\nPROVIDE\t(dpd_scale_set = 0x40219388);\nPROVIDE\t(dpd_mem_write = 0x402193d0);\nPROVIDE\t(pm_usec2rtc = 0x4021944c);\nPROVIDE\t(pm_rtc2usec = 0x40219480);\nPROVIDE\t(pm_set_sleep_cycles = 0x4021948c);\nPROVIDE\t(pm_sleep_opt = 0x402194b0);\nPROVIDE\t(pm_wakeup_opt = 0x402195f4);\nPROVIDE\t(get_chip_version = 0x4021962c);\nPROVIDE\t(pm_sleep_opt_bb_off = 0x4021966c);\nPROVIDE\t(pm_sleep_opt_bb_on = 0x402196ac);\nPROVIDE\t(pm_set_pll_xtal_wait_time = 0x402196f4);\nPROVIDE\t(pm_prepare_to_sleep = 0x40219720);\nPROVIDE\t(pm_sdio_nidle = 0x40219728);\nPROVIDE\t(chg_lslp_mem_opt_8266 = 0x4021979c);\nPROVIDE\t(pm_goto_sleep = 0x402197cc);\nPROVIDE\t(pm_wait4wakeup = 0x40219918);\nPROVIDE\t(pm_open_rf = 0x40219954);\nPROVIDE\t(pm_sleep_set_mac = 0x40219998);\nPROVIDE\t(pm_set_wakeup_mac = 0x40219a1c);\nPROVIDE\t(pm_check_mac_idle = 0x40219ab4);\nPROVIDE\t(pm_set_sleep_btco = 0x40219b0c);\nPROVIDE\t(pm_set_wakeup_btco = 0x40219bac);\nPROVIDE\t(pm_set_sleep_mode = 0x40219cc4);\nPROVIDE\t(pm_unmask_bt = 0x40219de0);\nPROVIDE\t(pm_wakeup_init = 0x40219e48);\nPROVIDE\t(sleep_opt_8266 = 0x4021a088);\nPROVIDE\t(sleep_opt_bb_on_8266 = 0x4021a0a8);\nPROVIDE\t(sleep_reset_analog_rtcreg_8266 = 0x4021a0e4);\nPROVIDE\t(pm_rtc_clock_cali_proc = 0x4021a1f0);\nPROVIDE\t(pm_get_ck170_period = 0x4021a228);\nPROVIDE\t(pm_set_sleep_time = 0x4021a24c);\nPROVIDE\t(pm_rf_is_closed = 0x4021a5d8);\nPROVIDE\t(pm_set_sleep_type_from_upper = 0x4021a604);\nPROVIDE\t(pm_get_sleep_type = 0x4021a6f4);\nPROVIDE\t(uart_tx_flush = 0x4021a8b0);\nPROVIDE\t(pm_suspend = 0x4021a8b4);\nPROVIDE\t(pm_shutdown = 0x4021aacc);\nPROVIDE\t(pm_reset_idle_sleep = 0x4021ab94);\nPROVIDE\t(pm_idle_sleep = 0x4021abd4);\nPROVIDE\t(pm_open = 0x4021abe0);\nPROVIDE\t(pm_onBcnRx = 0x4021acc0);\nPROVIDE\t(StopLightSleepSetFunc = 0x4021b058);\nPROVIDE\t(LightSleepWakedCbSetFunc = 0x4021b060);\nPROVIDE\t(pm_enable_gpio_wakeup = 0x4021b61c);\nPROVIDE\t(pm_attach = 0x4021b654);\nPROVIDE\t(pm_send_nullfunc = 0x4021b73c);\nPROVIDE\t(pm_is_waked = 0x4021b8e0);\nPROVIDE\t(pm_is_open = 0x4021b8f8);\nPROVIDE\t(pm_scan_lock = 0x4021b910);\nPROVIDE\t(pm_try_scan_unlock = 0x4021b938);\nPROVIDE\t(pm_force_scan_unlock = 0x4021b950);\nPROVIDE\t(pm_scan_unlocked = 0x4021b9f4);\nPROVIDE\t(pm_allow_tx = 0x4021ba08);\nPROVIDE\t(pm_assoc_parse = 0x4021ba24);\nPROVIDE\t(pm_set_addr = 0x4021ba3c);\nPROVIDE\t(pm_sleep_for = 0x4021ba5c);\nPROVIDE\t(pm_post = 0x4021ba8c);\nPROVIDE\t(pm_get_idle_wait_time = 0x4021bb90);\nPROVIDE\t(fpm_set_type_from_upper = 0x4021bbe8);\nPROVIDE\t(wifi_fpm_set_sleep_type = 0x4021bbe8);\nPROVIDE\t(fpm_get_slp_type = 0x4021bca4);\nPROVIDE\t(wifi_fpm_get_sleep_type = 0x4021bca4);\nPROVIDE\t(fpm_rf_is_closed = 0x4021bcac);\nPROVIDE\t(fpm_is_open = 0x4021bcc0);\nPROVIDE\t(fpm_allow_tx = 0x4021bccc);\nPROVIDE\t(fpm_close = 0x4021bcf0);\nPROVIDE\t(wifi_fpm_close = 0x4021bcf0);\nPROVIDE\t(fpm_open = 0x4021bd6c);\nPROVIDE\t(wifi_fpm_open = 0x4021bd6c);\nPROVIDE\t(fpm_attach = 0x4021bdd4);\nPROVIDE\t(fpm_set_wakeup_cb = 0x4021bfb8);\nPROVIDE\t(wifi_fpm_set_wakeup_cb = 0x4021bfb8);\nPROVIDE\t(fpm_do_wakeup = 0x4021c0fc);\nPROVIDE\t(wifi_fpm_do_wakeup = 0x4021c0fc);\nPROVIDE\t(fpm_do_sleep = 0x4021c630);\nPROVIDE\t(wifi_fpm_do_sleep = 0x4021c630);\nPROVIDE\t(fpm_auto_sleep_set_in_null_mode = 0x4021c6d0);\nPROVIDE\t(wifi_fpm_auto_sleep_set_in_null_mode = 0x4021c6d0);\nPROVIDE\t(get_fpm_auto_sleep_flag = 0x4021c710);\nPROVIDE\t(PPWdtReset = 0x4021c724);\nPROVIDE\t(pp_soft_wdt_init = 0x4021c758);\nPROVIDE\t(pp_soft_wdt_feed = 0x4021c778);\nPROVIDE\t(system_soft_wdt_feed = 0x4021c778);\nPROVIDE\t(pp_soft_wdt_stop = 0x4021c794);\nPROVIDE\t(system_soft_wdt_stop = 0x4021c794);\nPROVIDE\t(pp_soft_wdt_restart = 0x4021c7c0);\nPROVIDE\t(system_soft_wdt_restart = 0x4021c7c0);\nPROVIDE\t(RxNodeNum = 0x4021c7f8);\nPROVIDE\t(TxNodeNum = 0x4021c810);\nPROVIDE\t(pp_disable_noise_timer = 0x4021c834);\nPROVIDE\t(pp_enable_noise_timer = 0x4021c854);\nPROVIDE\t(pp_noise_test = 0x4021c964);\nPROVIDE\t(reset_noise_timer = 0x4021c974);\nPROVIDE\t(pp_disable_idle_timer = 0x4021c9ac);\nPROVIDE\t(pp_enable_idle_timer = 0x4021c9d0);\nPROVIDE\t(pp_try_enable_idle_timer = 0x4021c9f8);\nPROVIDE\t(ppPeocessRxPktHdr = 0x4021ca34);\nPROVIDE\t(HdlAllBuffedEb = 0x4021cd68);\nPROVIDE\t(ppTxPkt = 0x4021cdf0);\nPROVIDE\t(ppProcessWaitQ = 0x4021cf68);\nPROVIDE\t(ppRegisterTxCallback = 0x4021cf78);\nPROVIDE\t(ppUnregisterTxCallback = 0x4021cfa0);\nPROVIDE\t(ppRecycleRxPkt = 0x4021cfd4);\nPROVIDE\t(ppCheckTxIdle = 0x4021d034);\nPROVIDE\t(pp_tx_idle_timeout = 0x4021d2ac);\nPROVIDE\t(DefFreqCalTimerCB = 0x4021d46c);\nPROVIDE\t(ppGetTxQFirstAvail_Locked = 0x4021d7e0);\nPROVIDE\t(pp_attach = 0x4021d8bc);\nPROVIDE\t(RC_SetBasicRate = 0x4021df10);\nPROVIDE\t(raw_new = 0x4021df60);\nPROVIDE\t(raw_remove = 0x4021dfa8);\nPROVIDE\t(raw_bind = 0x4021dfdc);\nPROVIDE\t(raw_connect = 0x4021dfe8);\nPROVIDE\t(raw_recv = 0x4021dff4);\nPROVIDE\t(raw_sendto = 0x4021dffc);\nPROVIDE\t(raw_input = 0x4021e0a0);\nPROVIDE\t(raw_send = 0x4021e124);\nPROVIDE\t(iram_buf_init = 0x4021e14c);\nPROVIDE\t(spi_flash_real_size = 0x4021e1a8);\nPROVIDE\t(tcp_arg = 0x4021e20c);\nPROVIDE\t(tcp_accept = 0x4021e210);\nPROVIDE\t(tcp_recv = 0x4021e214);\nPROVIDE\t(tcp_sent = 0x4021e21c);\nPROVIDE\t(tcp_poll = 0x4021e224);\nPROVIDE\t(tcp_err = 0x4021e22c);\nPROVIDE\t(tcp_bind = 0x4021e240);\nPROVIDE\t(tcp_listen_with_backlog = 0x4021e2e4);\nPROVIDE\t(tcp_setprio = 0x4021e3a8);\nPROVIDE\t(tcp_update_rcv_ann_wnd = 0x4021e3b0);\nPROVIDE\t(tcp_recved = 0x4021e3f8);\nPROVIDE\t(tcp_seg_free = 0x4021e448);\nPROVIDE\t(tcp_segs_free = 0x4021e470);\nPROVIDE\t(tcp_pcb_purge = 0x4021e490);\nPROVIDE\t(tcp_slowtmr = 0x4021e4ec);\nPROVIDE\t(tcp_pcb_remove = 0x4021e768);\nPROVIDE\t(tcp_close = 0x4021e7e0);\nPROVIDE\t(tcp_recv_null = 0x4021e808);\nPROVIDE\t(tcp_fasttmr = 0x4021e840);\nPROVIDE\t(tcp_tmr = 0x4021e8d4);\nPROVIDE\t(tcp_shutdown = 0x4021e8f8);\nPROVIDE\t(tcp_abandon = 0x4021e958);\nPROVIDE\t(tcp_abort = 0x4021e9e8);\nPROVIDE\t(tcp_next_iss = 0x4021ea00);\nPROVIDE\t(tcp_alloc = 0x4021ea20);\nPROVIDE\t(tcp_new = 0x4021eb44);\nPROVIDE\t(tcp_eff_send_mss = 0x4021eb58);\nPROVIDE\t(tcp_connect = 0x4021eb8c);\nPROVIDE\t(tcp_receive = 0x4021ecbc);\nPROVIDE\t(tcp_input = 0x4021f248);\nPROVIDE\t(tcp_create_segment = 0x4021fbd4);\nPROVIDE\t(tcp_write = 0x4021fdc4);\nPROVIDE\t(tcp_send_empty_ack = 0x402200d4);\nPROVIDE\t(tcp_rexmit = 0x40220164);\nPROVIDE\t(tcp_rexmit_fast = 0x4022021c);\nPROVIDE\t(tcp_enqueue_flags = 0x40220280);\nPROVIDE\t(tcp_send_fin = 0x4022034c);\nPROVIDE\t(tcp_rst = 0x40220398);\nPROVIDE\t(tcp_keepalive = 0x402204cc);\nPROVIDE\t(tcp_zero_window_probe = 0x4022054c);\nPROVIDE\t(tcp_output = 0x4022065c);\nPROVIDE\t(tcp_rexmit_rto = 0x40220a84);\nPROVIDE\t(sys_timeout = 0x40220b0c);\nPROVIDE\t(sys_timeouts_init = 0x40220bb0);\nPROVIDE\t(tcpip_tcp_timer = 0x40220c20);\nPROVIDE\t(arp_timer = 0x40220c54);\nPROVIDE\t(sys_untimeout = 0x40220c70);\nPROVIDE\t(sys_check_timeouts = 0x40220cc4);\nPROVIDE\t(sys_restart_timeouts = 0x40220d40);\nPROVIDE\t(tcp_timer_needed = 0x40220d4c);\nPROVIDE\t(phytype2mode = 0x40220d7c);\nPROVIDE\t(rc_set_rate_limit_id = 0x40220d98);\nPROVIDE\t(rcUpdatePhyMode = 0x40220eb4);\nPROVIDE\t(rcAttach = 0x40221080);\nPROVIDE\t(rcGetTrc = 0x402210cc);\nPROVIDE\t(trc_onDisconnect = 0x402210d4);\nPROVIDE\t(trc_onScanStart = 0x402210d8);\nPROVIDE\t(trc_onScanDone = 0x402210ec);\nPROVIDE\t(rc_enable_trc = 0x40221108);\nPROVIDE\t(rc_get_mask = 0x402211e0);\nPROVIDE\t(rc_disable_trc = 0x402211f4);\nPROVIDE\t(rc_disable_trc_by_interface = 0x40221248);\nPROVIDE\t(rc_get_sta_trc = 0x40221264);\nPROVIDE\t(rc_get_trc = 0x402212a8);\nPROVIDE\t(rc_get_trc_by_index = 0x40221318);\nPROVIDE\t(rc_only_sta_trc = 0x40221338);\nPROVIDE\t(udp_new = 0x40221368);\nPROVIDE\t(udp_remove = 0x4022139c);\nPROVIDE\t(udp_bind = 0x402213d4);\nPROVIDE\t(udp_connect = 0x40221478);\nPROVIDE\t(udp_disconnect = 0x402214e0);\nPROVIDE\t(udp_recv = 0x402214f4);\nPROVIDE\t(udp_sendto_if = 0x402214fc);\nPROVIDE\t(udp_sendto = 0x40221648);\nPROVIDE\t(udp_send = 0x40221694);\nPROVIDE\t(udp_input = 0x402216ac);\nPROVIDE\t(system_set_os_print = 0x402218ac);\nPROVIDE\t(system_get_os_print = 0x402218bc);\nPROVIDE\t(system_pp_recycle_rx_pkt = 0x40221a84);\nPROVIDE\t(system_adc_read = 0x40221a98);\nPROVIDE\t(system_adc_read_fast = 0x40221ad8);\nPROVIDE\t(system_get_vdd33 = 0x40221b38);\nPROVIDE\t(system_restart_hook = 0x40221b64);\nPROVIDE\t(system_restart_local = 0x40221b78);\nPROVIDE\t(system_restart = 0x40221c60);\nPROVIDE\t(system_restore = 0x40221cb8);\nPROVIDE\t(system_get_flash_size_map = 0x40221d20);\nPROVIDE\t(system_get_boot_version = 0x40221d40);\nPROVIDE\t(system_get_test_result = 0x40221d78);\nPROVIDE\t(system_get_userbin_addr = 0x40221d9c);\nPROVIDE\t(system_get_boot_mode = 0x40221e34);\nPROVIDE\t(system_restart_enhance = 0x40221e64);\nPROVIDE\t(system_upgrade_userbin_set = 0x40221f94);\nPROVIDE\t(system_upgrade_userbin_check = 0x40221fe0);\nPROVIDE\t(system_upgrade_flag_set = 0x40222020);\nPROVIDE\t(system_upgrade_flag_check = 0x40222034);\nPROVIDE\t(system_upgrade_reboot = 0x40222058);\nPROVIDE\t(system_deep_sleep_instant = 0x40222174);\nPROVIDE\t(system_deep_sleep = 0x40222314);\nPROVIDE\t(system_deep_sleep_set_option = 0x40222374);\nPROVIDE\t(system_phy_temperature_alert = 0x40222390);\nPROVIDE\t(system_phy_set_max_tpw = 0x402223a4);\nPROVIDE\t(system_phy_set_tpw_via_vdd33 = 0x402223b8);\nPROVIDE\t(system_phy_set_rfoption = 0x402223cc);\nPROVIDE\t(system_phy_set_powerup_option = 0x402223e0);\nPROVIDE\t(system_update_cpu_freq = 0x402223f4);\nPROVIDE\t(system_get_cpu_freq = 0x40222450);\nPROVIDE\t(system_overclock = 0x40222468);\nPROVIDE\t(system_restoreclock = 0x40222494);\nPROVIDE\t(system_timer_reinit = 0x402224c4);\nPROVIDE\t(system_relative_time = 0x402224dc);\nPROVIDE\t(system_station_got_ip_set = 0x402224f8);\nPROVIDE\t(system_print_meminfo = 0x40222624);\nPROVIDE\t(system_get_free_heap_size = 0x40222688);\nPROVIDE\t(system_get_chip_id = 0x4022269c);\nPROVIDE\t(system_rtc_clock_cali_proc = 0x402226c0);\nPROVIDE\t(system_get_rtc_time = 0x402226d4);\nPROVIDE\t(system_mktime = 0x402226e4);\nPROVIDE\t(system_init_done_cb = 0x402227b4);\nPROVIDE\t(system_get_rst_info = 0x402227bc);\nPROVIDE\t(system_get_data_of_array_8 = 0x402227c4);\nPROVIDE\t(system_get_data_of_array_16 = 0x402227e8);\nPROVIDE\t(system_get_string_from_flash = 0x40222810);\nPROVIDE\t(wifi_softap_dhcps_start = 0x4022287c);\nPROVIDE\t(wifi_softap_dhcps_stop = 0x402228c4);\nPROVIDE\t(wifi_softap_dhcps_status = 0x40222904);\nPROVIDE\t(wifi_station_dhcpc_start = 0x4022290c);\nPROVIDE\t(wifi_station_dhcpc_stop = 0x40222964);\nPROVIDE\t(wifi_station_dhcpc_event = 0x402229a4);\nPROVIDE\t(wifi_station_dhcpc_set_maxtry = 0x40222a18);\nPROVIDE\t(wifi_station_dhcpc_status = 0x40222a28);\nPROVIDE\t(wifi_get_opmode = 0x40222aa0);\nPROVIDE\t(wifi_get_opmode_default = 0x40222ab4);\nPROVIDE\t(wifi_get_broadcast_if = 0x40222b2c);\nPROVIDE\t(wifi_set_broadcast_if = 0x40222b68);\nPROVIDE\t(wifi_set_opmode = 0x40222cdc);\nPROVIDE\t(wifi_set_opmode_current = 0x40222cf0);\nPROVIDE\t(system_get_checksum = 0x40222d04);\nPROVIDE\t(wifi_param_save_protect_with_check = 0x40222d48);\nPROVIDE\t(system_param_save_with_protect = 0x40222e00);\nPROVIDE\t(system_save_sys_param = 0x40222ea8);\nPROVIDE\t(system_param_load = 0x40222ed4);\nPROVIDE\t(wifi_station_get_config = 0x4022300c);\nPROVIDE\t(wifi_station_get_config_default = 0x40223020);\nPROVIDE\t(wifi_station_get_ap_info = 0x40223040);\nPROVIDE\t(wifi_station_ap_number_set = 0x402230f8);\nPROVIDE\t(wifi_station_set_config = 0x40223484);\nPROVIDE\t(wifi_station_set_config_current = 0x4022349c);\nPROVIDE\t(wifi_station_restore_config = 0x402234b4);\nPROVIDE\t(wifi_station_get_current_ap_id = 0x402234cc);\nPROVIDE\t(wifi_station_ap_check = 0x402234e0);\nPROVIDE\t(wifi_station_ap_change = 0x40223520);\nPROVIDE\t(wifi_station_scan = 0x4022364c);\nPROVIDE\t(wifi_station_get_auto_connect = 0x40223698);\nPROVIDE\t(wifi_station_set_auto_connect = 0x402236ac);\nPROVIDE\t(wifi_station_save_pmk2cache = 0x402236fc);\nPROVIDE\t(wifi_station_connect = 0x402237ac);\nPROVIDE\t(wifi_station_disconnect = 0x40223840);\nPROVIDE\t(wifi_station_get_connect_status = 0x40223900);\nPROVIDE\t(wifi_station_set_reconnect_policy = 0x40223930);\nPROVIDE\t(wifi_station_get_reconnect_policy = 0x40223948);\nPROVIDE\t(wifi_station_get_rssi = 0x40223950);\nPROVIDE\t(wifi_station_set_default_hostname = 0x4022399c);\nPROVIDE\t(wifi_station_get_hostname = 0x40223a04);\nPROVIDE\t(wifi_station_set_hostname = 0x40223a30);\nPROVIDE\t(wifi_softap_cacl_mac = 0x40223acc);\nPROVIDE\t(wifi_softap_set_default_ssid = 0x40223b30);\nPROVIDE\t(wifi_softap_get_config = 0x40223d0c);\nPROVIDE\t(wifi_softap_get_config_default = 0x40223d20);\nPROVIDE\t(wifi_softap_set_config = 0x4022406c);\nPROVIDE\t(wifi_softap_set_config_current = 0x40224080);\nPROVIDE\t(wifi_softap_set_station_info = 0x40224094);\nPROVIDE\t(wifi_softap_get_station_info = 0x40224100);\nPROVIDE\t(wifi_softap_free_station_info = 0x402241b0);\nPROVIDE\t(wifi_softap_get_station_num = 0x402241f8);\nPROVIDE\t(wifi_softap_deauth = 0x40224248);\nPROVIDE\t(wifi_softap_get_beacon_only_mode = 0x402242f8);\nPROVIDE\t(wifi_softap_set_beacon_only_mode = 0x4022430c);\nPROVIDE\t(wifi_register_user_ie_manufacturer_recv_cb = 0x40224370);\nPROVIDE\t(wifi_unregister_user_ie_manufacturer_recv_cb = 0x40224384);\nPROVIDE\t(wifi_set_user_ie = 0x402243b4);\nPROVIDE\t(wifi_get_user_ie = 0x402244c4);\nPROVIDE\t(wifi_get_phy_mode = 0x402244f8);\nPROVIDE\t(wifi_set_phy_mode = 0x40224500);\nPROVIDE\t(wifi_set_sleep_type = 0x402245c8);\nPROVIDE\t(wifi_get_sleep_type = 0x402245e4);\nPROVIDE\t(wifi_get_channel = 0x402245f8);\nPROVIDE\t(wifi_set_channel = 0x40224610);\nPROVIDE\t(wifi_promiscuous_set_mac = 0x40224650);\nPROVIDE\t(wifi_promiscuous_enable = 0x402246ac);\nPROVIDE\t(wifi_set_promiscuous_rx_cb = 0x40224790);\nPROVIDE\t(wifi_get_ip_info = 0x4022479c);\nPROVIDE\t(wifi_set_ip_info = 0x4022481c);\nPROVIDE\t(wifi_get_macaddr = 0x40224890);\nPROVIDE\t(wifi_set_macaddr = 0x402248f0);\nPROVIDE\t(wifi_enable_6m_rate = 0x40224a0c);\nPROVIDE\t(wifi_get_user_fixed_rate = 0x40224a14);\nPROVIDE\t(wifi_set_user_fixed_rate = 0x40224a34);\nPROVIDE\t(wifi_set_user_sup_rate = 0x40224a54);\nPROVIDE\t(wifi_set_user_rate_limit = 0x40224a90);\nPROVIDE\t(wifi_get_user_limit_rate_mask = 0x40224ab4);\nPROVIDE\t(wifi_set_user_limit_rate_mask = 0x40224abc);\nPROVIDE\t(wifi_register_send_pkt_freedom_cb = 0x40224ad4);\nPROVIDE\t(wifi_unregister_send_pkt_freedom_cb = 0x40224ae8);\nPROVIDE\t(wifi_send_pkt_freedom = 0x40224af4);\nPROVIDE\t(wifi_rfid_locp_recv_open = 0x40224b40);\nPROVIDE\t(wifi_rfid_locp_recv_close = 0x40224b54);\nPROVIDE\t(wifi_register_rfid_locp_recv_cb = 0x40224b68);\nPROVIDE\t(wifi_unregister_rfid_locp_recv_cb = 0x40224b7c);\nPROVIDE\t(wifi_status_led_install = 0x40224b94);\nPROVIDE\t(wifi_status_led_uninstall = 0x40224bc8);\nPROVIDE\t(wifi_set_status_led_output_level = 0x40224bec);\nPROVIDE\t(wifi_set_event_handler_cb = 0x40224c40);\nPROVIDE\t(system_os_task = 0x40224c88);\nPROVIDE\t(system_uart_swap = 0x40224cc4);\nPROVIDE\t(system_uart_de_swap = 0x40224d28);\nPROVIDE\t(system_get_sdk_version = 0x40224d60);\nPROVIDE\t(wDev_Option_Init = 0x40224d74);\nPROVIDE\t(wDev_Enable_Beacon_Tsf = 0x40224e68);\nPROVIDE\t(wDev_Disable_Beacon_Tsf = 0x40224e84);\nPROVIDE\t(wDev_Set_Beacon_Int = 0x40224ea0);\nPROVIDE\t(wDev_Reset_TBTT = 0x40224ea8);\nPROVIDE\t(wDev_Get_Next_TBTT = 0x40224ed8);\nPROVIDE\t(wDev_Initialize = 0x40225154);\nPROVIDE\t(wDevForceAck6M = 0x402251c4);\nPROVIDE\t(wDev_SetMacAddress = 0x402251e0);\nPROVIDE\t(wDev_SetRxPolicy = 0x4022527c);\nPROVIDE\t(wDev_SetBssid = 0x402252d0);\nPROVIDE\t(wDev_ClearBssid = 0x402253a8);\nPROVIDE\t(wDev_Insert_KeyEntry = 0x402253e0);\nPROVIDE\t(wDev_remove_KeyEntry = 0x402254d4);\nPROVIDE\t(wDev_remove_KeyEntry_all_cnx = 0x40225510);\nPROVIDE\t(wDev_Crypto_Conf = 0x40225560);\nPROVIDE\t(wDev_Crypto_Disable = 0x402255fc);\nPROVIDE\t(wDevEnableRx = 0x40225634);\nPROVIDE\t(wdev_go_sniffer = 0x4022565c);\nPROVIDE\t(wdev_set_sniffer_addr = 0x40225738);\nPROVIDE\t(wdev_exit_sniffer = 0x40225790);\nPROVIDE\t(wdt_init = 0x40225860);\nPROVIDE\t(os_print_reset_error = 0x402258e4);\nPROVIDE\t(chm_init = 0x40225988);\nPROVIDE\t(chm_acquire_lock = 0x402259ec);\nPROVIDE\t(chm_release_lock = 0x40225a30);\nPROVIDE\t(chm_start_op = 0x40225a44);\nPROVIDE\t(chm_end_op = 0x40225ae8);\nPROVIDE\t(chm_cancel_op = 0x40225b30);\nPROVIDE\t(chm_return_home_channel = 0x40225b64);\nPROVIDE\t(chm_set_current_channel = 0x40225b94);\nPROVIDE\t(chm_freq2index = 0x40225bc4);\nPROVIDE\t(chm_check_same_channel = 0x40225bec);\nPROVIDE\t(cnx_attach = 0x40225c28);\nPROVIDE\t(cnx_sta_connect_led_timer_cb = 0x40225c68);\nPROVIDE\t(cnx_sta_connect_cmd = 0x40225cbc);\nPROVIDE\t(cnx_sta_scan_cmd = 0x40225d78);\nPROVIDE\t(cnx_connect_timeout = 0x40225fe0);\nPROVIDE\t(cnx_auth_timeout = 0x4022605c);\nPROVIDE\t(cnx_assoc_timeout = 0x40226080);\nPROVIDE\t(cnx_handshake_timeout = 0x402260a4);\nPROVIDE\t(cnx_start_handoff_cb = 0x402260e4);\nPROVIDE\t(cnx_bss_alloc = 0x40226554);\nPROVIDE\t(cnx_rc_search = 0x402265f4);\nPROVIDE\t(cnx_add_rc = 0x40226674);\nPROVIDE\t(cnx_remove_all_rc = 0x402266e0);\nPROVIDE\t(cnx_remove_rc = 0x4022672c);\nPROVIDE\t(cnx_rc_update_rssi = 0x402267fc);\nPROVIDE\t(cnx_rc_update_state_metric = 0x40226884);\nPROVIDE\t(cnx_rc_update_age = 0x402268f0);\nPROVIDE\t(cnx_update_bss = 0x40226914);\nPROVIDE\t(cnx_update_bss_more = 0x40226948);\nPROVIDE\t(cnx_sta_leave = 0x40226b24);\nPROVIDE\t(cnx_sta_associated = 0x40226db8);\nPROVIDE\t(cnx_node_alloc = 0x40226ec0);\nPROVIDE\t(cnx_node_remove = 0x40226f34);\nPROVIDE\t(cnx_node_search = 0x40226fc0);\nPROVIDE\t(cnx_node_leave = 0x4022703c);\nPROVIDE\t(wifi_softap_staconnected_event_policy = 0x4022713c);\nPROVIDE\t(wifi_softap_toomany_deny = 0x40227164);\nPROVIDE\t(cnx_node_join = 0x402271a0);\nPROVIDE\t(wpa_sm_rx_eapol = 0x40228388);\nPROVIDE\t(wpa_register = 0x40228500);\nPROVIDE\t(wpa_set_profile = 0x4022852c);\nPROVIDE\t(wpa_set_pmk = 0x40228544);\nPROVIDE\t(wpa_set_bss = 0x40228570);\nPROVIDE\t(pp_michael_mic_failure = 0x40228774);\nPROVIDE\t(eapol_txcb = 0x40228818);\nPROVIDE\t(wpa_sm_set_state = 0x402288a4);\nPROVIDE\t(wpa_auth_for_each_sta = 0x40228a18);\nPROVIDE\t(wpa_init = 0x40228b98);\nPROVIDE\t(wpa_auth_sta_init = 0x40228c28);\nPROVIDE\t(wpa_auth_sta_associated = 0x40228c70);\nPROVIDE\t(wpa_auth_sta_no_wpa = 0x40228cdc);\nPROVIDE\t(wpa_auth_sta_deinit = 0x40228d38);\nPROVIDE\t(wpa_receive = 0x40228e08);\nPROVIDE\t(__wpa_send_eapol = 0x40229268);\nPROVIDE\t(wpa_remove_ptk = 0x4022978c);\nPROVIDE\t(wpa_auth_sm_event = 0x402297d8);\nPROVIDE\t(wpa_write_rsn_ie = 0x4022a614);\nPROVIDE\t(wpa_auth_gen_wpa_ie = 0x4022a720);\nPROVIDE\t(wpa_add_kde = 0x4022a7b0);\nPROVIDE\t(wpa_validate_wpa_ie = 0x4022a81c);\nPROVIDE\t(wpa_parse_kde_ies = 0x4022aa28);\nPROVIDE\t(wpa_auth_uses_mfp = 0x4022aac4);\nPROVIDE\t(wpa_parse_wpa_ie_rsn = 0x4022ac1c);\nPROVIDE\t(wpa_parse_wpa_ie_wpa = 0x4022adb0);\nPROVIDE\t(wpa_eapol_key_mic = 0x4022af40);\nPROVIDE\t(wpa_compare_rsn_ie = 0x4022af80);\nPROVIDE\t(wpa_pmk_to_ptk = 0x4022afa8);\nPROVIDE\t(rsn_pmkid = 0x4022b098);\nPROVIDE\t(wpa_cipher_key_len = 0x4022b0f4);\nPROVIDE\t(wpa_cipher_to_alg = 0x4022b118);\nPROVIDE\t(wpa_cipher_to_suite = 0x4022b140);\nPROVIDE\t(rsn_cipher_put_suites = 0x4022b194);\nPROVIDE\t(wpa_cipher_put_suites = 0x4022b1f4);\nPROVIDE\t(wpa_parse_wpa_ie = 0x4022b240);\nPROVIDE\t(wpa_supplicant_parse_ies = 0x4022b334);\nPROVIDE\t(wpa_gen_wpa_ie = 0x4022b534);\nPROVIDE\t(ppInstallKey = 0x4022b56c);\nPROVIDE\t(wpa_config_profile = 0x4022b6fc);\nPROVIDE\t(wpa_config_bss = 0x4022b730);\nPROVIDE\t(wpa_config_assoc_ie = 0x4022b75c);\nPROVIDE\t(dhcp_bind_check = 0x4022b770);\nPROVIDE\t(eagle_auth_done = 0x4022b7a4);\nPROVIDE\t(wpa_neg_complete = 0x4022b920);\nPROVIDE\t(wpa_attach = 0x4022b948);\nPROVIDE\t(wpa_sm_alloc_eapol = 0x4022b9f0);\nPROVIDE\t(wpa_sm_deauthenticate = 0x4022ba30);\nPROVIDE\t(wpa_sm_mlme_setprotection = 0x4022ba4c);\nPROVIDE\t(wpa_sm_get_beacon_ie = 0x4022ba50);\nPROVIDE\t(wpa_sm_disassociate = 0x4022ba54);\nPROVIDE\t(aes_wrap = 0x4022ba58);\nPROVIDE\t(hostapd_config_defaults_bss = 0x4022bb3c);\nPROVIDE\t(hostapd_config_defaults = 0x4022bb88);\nPROVIDE\t(hostapd_mac_comp = 0x4022bc0c);\nPROVIDE\t(hostapd_mac_comp_empty = 0x4022bc20);\nPROVIDE\t(hostapd_setup_wpa_psk = 0x4022bc8c);\nPROVIDE\t(hostapd_wep_key_cmp = 0x4022bcbc);\nPROVIDE\t(hostapd_maclist_found = 0x4022bd0c);\nPROVIDE\t(hostapd_rate_found = 0x4022bd74);\nPROVIDE\t(hostapd_get_psk = 0x4022bd90);\nPROVIDE\t(inc_byte_array = 0x4022bde4);\nPROVIDE\t(hex2byte = 0x4022be38);\nPROVIDE\t(hexstr2bin = 0x4022be6c);\nPROVIDE\t(wpa_get_ntp_timestamp = 0x4022beb8);\nPROVIDE\t(wpa_config_parse_string = 0x4022bf50);\nPROVIDE\t(dup_binstr = 0x4022c054);\nPROVIDE\t(dhcp_set_state = 0x4022c09c);\nPROVIDE\t(dhcp_check = 0x4022c0b4);\nPROVIDE\t(dhcp_option = 0x4022c0f0);\nPROVIDE\t(dhcp_option_byte = 0x4022c110);\nPROVIDE\t(dhcp_option_short = 0x4022c124);\nPROVIDE\t(dhcp_option_long = 0x4022c148);\nPROVIDE\t(dhcp_create_msg = 0x4022c1a0);\nPROVIDE\t(dhcp_delete_msg = 0x4022c33c);\nPROVIDE\t(dhcp_bind = 0x4022c364);\nPROVIDE\t(dhcp_option_trailer = 0x4022c45c);\nPROVIDE\t(dhcp_reboot = 0x4022c494);\nPROVIDE\t(dhcp_rebind = 0x4022c564);\nPROVIDE\t(dhcp_select = 0x4022c640);\nPROVIDE\t(dhcp_discover = 0x4022c7e0);\nPROVIDE\t(dhcp_recv = 0x4022c92c);\nPROVIDE\t(dhcp_set_struct = 0x4022cf18);\nPROVIDE\t(dhcp_cleanup = 0x4022cf40);\nPROVIDE\t(dhcp_inform = 0x4022cf64);\nPROVIDE\t(dhcp_network_changed = 0x4022d010);\nPROVIDE\t(dhcp_arp_reply = 0x4022d058);\nPROVIDE\t(dhcp_renew = 0x4022d10c);\nPROVIDE\t(dhcp_coarse_tmr = 0x4022d1e8);\nPROVIDE\t(dhcp_release = 0x4022d27c);\nPROVIDE\t(dhcp_fine_tmr = 0x4022d344);\nPROVIDE\t(dhcp_stop = 0x4022d434);\nPROVIDE\t(dhcp_start = 0x4022d470);\nPROVIDE\t(create_msg = 0x4022d538);\nPROVIDE\t(add_offer_options = 0x4022d5f0);\nPROVIDE\t(node_insert_to_list = 0x4022d730);\nPROVIDE\t(node_remove_from_list = 0x4022d768);\nPROVIDE\t(handle_dhcp = 0x4022d7ac);\nPROVIDE\t(dhcps_start = 0x4022dc1c);\nPROVIDE\t(dhcps_stop = 0x4022dd00);\nPROVIDE\t(wifi_softap_set_dhcps_lease = 0x4022dd64);\nPROVIDE\t(wifi_softap_get_dhcps_lease = 0x4022dd88);\nPROVIDE\t(dhcps_coarse_tmr = 0x4022dda0);\nPROVIDE\t(wifi_softap_set_dhcps_offer_option = 0x4022de40);\nPROVIDE\t(wifi_softap_set_dhcps_lease_time = 0x4022de80);\nPROVIDE\t(wifi_softap_reset_dhcps_lease_time = 0x4022de90);\nPROVIDE\t(wifi_softap_get_dhcps_lease_time = 0x4022de9c);\nPROVIDE\t(dns_parse_name = 0x4022dea4);\nPROVIDE\t(dns_recv = 0x4022ded8);\nPROVIDE\t(dns_send = 0x4022e120);\nPROVIDE\t(dns_check_entry = 0x4022e230);\nPROVIDE\t(dns_setserver = 0x4022e30c);\nPROVIDE\t(dns_init = 0x4022e334);\nPROVIDE\t(dns_getserver = 0x4022e378);\nPROVIDE\t(dns_tmr = 0x4022e390);\nPROVIDE\t(dns_gethostbyname = 0x4022e3c0);\nPROVIDE\t(esf_buf_alloc = 0x4022e4e0);\nPROVIDE\t(esf_buf_recycle = 0x4022e6c8);\nPROVIDE\t(esf_buf_setup = 0x4022e808);\nPROVIDE\t(icmp_input = 0x4022e8c8);\nPROVIDE\t(icmp_dest_unreach = 0x4022ea50);\nPROVIDE\t(ieee80211_send_action_register = 0x4022eb08);\nPROVIDE\t(ieee80211_send_action_unregister = 0x4022eb3c);\nPROVIDE\t(ieee80211_send_action = 0x4022eb50);\nPROVIDE\t(ieee80211_recv_action_register = 0x4022ebbc);\nPROVIDE\t(ieee80211_recv_action_unregister = 0x4022ebf0);\nPROVIDE\t(ieee80211_recv_action = 0x4022ec04);\nPROVIDE\t(igmp_send = 0x4022efcc);\nPROVIDE\t(igmp_delaying_member = 0x4022f0b8);\nPROVIDE\t(igmp_init = 0x4022f15c);\nPROVIDE\t(igmp_stop = 0x4022f170);\nPROVIDE\t(igmp_report_groups = 0x4022f1d4);\nPROVIDE\t(igmp_lookfor_group = 0x4022f204);\nPROVIDE\t(igmp_start = 0x4022f220);\nPROVIDE\t(igmp_input = 0x4022f274);\nPROVIDE\t(igmp_joingroup = 0x4022f390);\nPROVIDE\t(igmp_leavegroup = 0x4022f458);\nPROVIDE\t(igmp_tmr = 0x4022f52c);\nPROVIDE\t(os_get_time = 0x4022f568);\nPROVIDE\t(r_rand = 0x4022f56c);\nPROVIDE\t(os_random = 0x4022f57c);\nPROVIDE\t(os_get_random = 0x4022f58c);\nPROVIDE\t(ets_strrchr = 0x4022f5d4);\nPROVIDE\t(rijndaelEncrypt = 0x4022f5f0);\nPROVIDE\t(aes_encrypt_init = 0x4022fa0c);\nPROVIDE\t(aes_encrypt = 0x4022fa60);\nPROVIDE\t(aes_encrypt_deinit = 0x4022fa78);\nPROVIDE\t(rijndaelKeySetupEnc = 0x4022faa8);\nPROVIDE\t(init_done_cb = 0x4022fdb0);\nPROVIDE\t(user_init = 0x4022fe0c);\nPROVIDE\t(Set_default_wificfg = 0x4022fef8);\nPROVIDE\t(wifi_read_fcfg = 0x40230074);\nPROVIDE\t(wifi_start_scan = 0x402300c0);\nPROVIDE\t(WiFi_go_to_sleep = 0x40230114);\nPROVIDE\t(WiFi_up_from_sleep = 0x40230148);\nPROVIDE\t(Read_WiFi_config = 0x4023017c);\nPROVIDE\t(wifi_save_fcfg = 0x40230330);\nPROVIDE\t(Set_WiFi = 0x40230368);\nPROVIDE\t(Cmp_WiFi_chg = 0x40230664);\nPROVIDE\t(Setup_WiFi = 0x402308c8);\nPROVIDE\t(print_wifi_config = 0x40230940);\nPROVIDE\t(New_WiFi_config = 0x40230ab0);\nPROVIDE\t(wifi_scan_cb = 0x40230b20);\nPROVIDE\t(get_addr_fobj = 0x40230c2c);\nPROVIDE\t(get_addr_fobj_save = 0x40230cc0);\nPROVIDE\t(get_addr_bscfg = 0x40230d3c);\nPROVIDE\t(flash_read_cfg = 0x40231058);\nPROVIDE\t(flash_save_cfg = 0x402310d8);\nPROVIDE\t(sys_write_cfg = 0x40231100);\nPROVIDE\t(new_tcp_client_url = 0x40231120);\nPROVIDE\t(read_tcp_client_url = 0x402311a0);\nPROVIDE\t(sys_read_cfg = 0x40231224);\nPROVIDE\t(read_user_const = 0x402312b4);\nPROVIDE\t(write_user_const = 0x402312ec);\nPROVIDE\t(station_connect_timer = 0x40231324);\nPROVIDE\t(station_reconnect_off = 0x40231378);\nPROVIDE\t(close_all_service = 0x402313a0);\nPROVIDE\t(open_all_service = 0x402313e8);\nPROVIDE\t(add_next_probe_requests = 0x402314b0);\nPROVIDE\t(wifi_handle_event_cb = 0x40231594);\nPROVIDE\t(ntp_time_update = 0x402317fc);\nPROVIDE\t(sntp_retry = 0x40231810);\nPROVIDE\t(sntp_recv = 0x40231854);\nPROVIDE\t(sntp_send_request = 0x40231940);\nPROVIDE\t(sntp_request = 0x402319ac);\nPROVIDE\t(sntp_dns_found = 0x40231a08);\nPROVIDE\t(sntp_inits = 0x40231a34);\nPROVIDE\t(sntp_close = 0x40231ac4);\nPROVIDE\t(get_sntp_time = 0x40231b0c);\nPROVIDE\t(_cdns_recv = 0x40231b98);\nPROVIDE\t(cdns_recv = 0x40231e18);\nPROVIDE\t(captdns_close = 0x40231eb4);\nPROVIDE\t(captdns_init = 0x40231eec);\nPROVIDE\t(netbios_recv = 0x40231f4c);\nPROVIDE\t(netbios_pcb = 0x40232160);\nPROVIDE\t(netbios_set_name = 0x40232180);\nPROVIDE\t(netbios_init = 0x402321e8);\nPROVIDE\t(netbios_off = 0x40232234);\nPROVIDE\t(web_fini = 0x40232274);\nPROVIDE\t(uart_save_fcfg = 0x40232488);\nPROVIDE\t(update_rts0 = 0x40232528);\nPROVIDE\t(update_mux_uart0 = 0x40232554);\nPROVIDE\t(uart0_set_flow = 0x40232618);\nPROVIDE\t(update_mux_txd1 = 0x40232670);\nPROVIDE\t(set_uartx_invx = 0x40232698);\nPROVIDE\t(uart_read_fcfg = 0x40232714);\nPROVIDE\t(uart_drv_close = 0x402327e0);\nPROVIDE\t(uarts_init = 0x40232844);\nPROVIDE\t(uart_drv_start = 0x402328b8);\nPROVIDE\t(tcp2uart_sent_cb = 0x4023291c);\nPROVIDE\t(tcp2uart_recv = 0x40232984);\nPROVIDE\t(tcp2uart_listen = 0x402329c4);\nPROVIDE\t(tcp2uart_disconnect = 0x40232a0c);\nPROVIDE\t(tcp2uart_close = 0x40232a24);\nPROVIDE\t(tcp2uart_start = 0x40232a64);\nPROVIDE\t(WEBFSClose = 0x40232bdc);\nPROVIDE\t(WEBFS_max_size = 0x40232c00);\nPROVIDE\t(WEBFS_curent_size = 0x40232c38);\nPROVIDE\t(WEBFS_base_addr = 0x40232c64);\nPROVIDE\t(WEBFSGetArray = 0x40232c8c);\nPROVIDE\t(WEBFSInit = 0x40232d2c);\nPROVIDE\t(GetFATRecord = 0x40232db8);\nPROVIDE\t(WEBFSOpen = 0x40232e30);\nPROVIDE\t(WEBFSGetFlags = 0x40232f40);\nPROVIDE\t(WEBFSGetSize = 0x40232f74);\nPROVIDE\t(WEBFSGetBytesRem = 0x40232fa4);\nPROVIDE\t(WEBFSGetStartAddr = 0x40232fc0);\nPROVIDE\t(WEBFSGetEndAddr = 0x40232ff0);\nPROVIDE\t(WEBFSSeek = 0x40233024);\nPROVIDE\t(WEBFSGetFilename = 0x402330d0);\nPROVIDE\t(WEBFSGetPosition = 0x40233128);\nPROVIDE\t(set_cpu_clk = 0x4023314c);\nPROVIDE\t(get_addr_gpiox_mux = 0x402331a0);\nPROVIDE\t(set_gpiox_mux_pull = 0x402331cc);\nPROVIDE\t(set_gpiox_mux_func = 0x402331f8);\nPROVIDE\t(set_gpiox_mux_func_ioport = 0x40233230);\nPROVIDE\t(set_gpiox_mux_func_default = 0x4023325c);\nPROVIDE\t(get_gpiox_mux = 0x40233288);\nPROVIDE\t(get_gpiox_mux_func = 0x402332a0);\nPROVIDE\t(test_pin_clr_wifi_config = 0x402332d8);\nPROVIDE\t(get_mac_time = 0x402333b0);\nPROVIDE\t(web_int_disconnect = 0x402333c8);\nPROVIDE\t(Close_web_conn = 0x4023341c);\nPROVIDE\t(webserver_disconnect = 0x40233470);\nPROVIDE\t(find_boundary = 0x402334b0);\nPROVIDE\t(web_inc_fp = 0x40233548);\nPROVIDE\t(webserver_init = 0x402335bc);\nPROVIDE\t(webserver_close = 0x40233650);\nPROVIDE\t(webserver_reinit = 0x4023367c);\nPROVIDE\t(web_inc_fopen = 0x402336c0);\nPROVIDE\t(web_inc_fclose = 0x40233754);\nPROVIDE\t(webserver_send_fdata = 0x402337f4);\nPROVIDE\t(webserver_sent_callback = 0x40233b7c);\nPROVIDE\t(web_trim_bufi = 0x40233c1c);\nPROVIDE\t(web_feee_bufi = 0x40233c84);\nPROVIDE\t(head_find_ctr = 0x40233cb8);\nPROVIDE\t(web_cdns_no_redir = 0x40233d30);\nPROVIDE\t(webserver_open_file = 0x40233e08);\nPROVIDE\t(web_print_headers = 0x40233ff0);\nPROVIDE\t(webserver_received_data = 0x402343d8);\nPROVIDE\t(tcpsrv_list_delete = 0x402354dc);\nPROVIDE\t(tcpsrv_client_reconnect = 0x40235584);\nPROVIDE\t(recv_trim_bufi = 0x40235650);\nPROVIDE\t(tcpsrv_server_sent = 0x40235778);\nPROVIDE\t(tcpsrv_print_remote_info = 0x402357d0);\nPROVIDE\t(tcpsrv_server_close = 0x40235810);\nPROVIDE\t(tcpsrv_int_sent_data = 0x40235904);\nPROVIDE\t(tcpsrv_server_poll = 0x402359f8);\nPROVIDE\t(tcpsrv_server_recv = 0x40235a74);\nPROVIDE\t(tcpsrv_connected = 0x40235b80);\nPROVIDE\t(tcpsrv_error = 0x40235c08);\nPROVIDE\t(tcpsrv_disconnect_calback_default = 0x40235c6c);\nPROVIDE\t(tcpsrv_listen_default = 0x40235c8c);\nPROVIDE\t(tcpsrv_sent_callback_default = 0x40235cac);\nPROVIDE\t(tcpsrv_received_data_default = 0x40235ccc);\nPROVIDE\t(tcpsrv_server_port2pcfg = 0x40235cf0);\nPROVIDE\t(tcpsrv_client_ip_port2conn = 0x40235d10);\nPROVIDE\t(tcpsrv_unrecved_win = 0x40235d38);\nPROVIDE\t(tcpsrv_init = 0x40235d7c);\nPROVIDE\t(tcpsrv_start = 0x40235e30);\nPROVIDE\t(tcpsrv_connected_default = 0x40235ecc);\nPROVIDE\t(find_tcp_pcb = 0x40235ee8);\nPROVIDE\t(tcpsrv_close_cb = 0x40235f34);\nPROVIDE\t(tcpsrv_client_connect = 0x40235ffc);\nPROVIDE\t(tcpsrv_client_start = 0x402360a0);\nPROVIDE\t(tcpsrv_disconnect = 0x4023613c);\nPROVIDE\t(tcpsrv_server_accept = 0x40236170);\nPROVIDE\t(tcpsrv_close = 0x402362ac);\nPROVIDE\t(tcpsrv_close_port = 0x40236364);\nPROVIDE\t(tcpsrv_close_all = 0x40236388);\nPROVIDE\t(web_hexdump = 0x402363cc);\nPROVIDE\t(web_modbus_xml = 0x40236558);\nPROVIDE\t(wifi_aps_xml = 0x4023661c);\nPROVIDE\t(web_wscan_xml = 0x40236784);\nPROVIDE\t(web_ProbeRequest_xml = 0x402368c0);\nPROVIDE\t(web_get_flash = 0x402369c0);\nPROVIDE\t(web_get_ram = 0x40236a34);\nPROVIDE\t(get_new_url = 0x40236aac);\nPROVIDE\t(web_int_callback = 0x40236e20);\nPROVIDE\t(ovl_loader = 0x40239244);\nPROVIDE\t(WebSocketAcceptKey = 0x40239364);\nPROVIDE\t(WebsocketMask = 0x402393f0);\nPROVIDE\t(WebsocketHead = 0x40239420);\nPROVIDE\t(WebsocketTxFrame = 0x40239578);\nPROVIDE\t(rom_atoi = 0x4023967c);\nPROVIDE\t(hextoul = 0x402396cc);\nPROVIDE\t(ahextoul = 0x4023971c);\nPROVIDE\t(cmpcpystr = 0x40239750);\nPROVIDE\t(web_strnstr = 0x402397e8);\nPROVIDE\t(base64decode = 0x40239858);\nPROVIDE\t(base64encode = 0x40239924);\nPROVIDE\t(strtomac = 0x402399f0);\nPROVIDE\t(urldecode = 0x40239a5c);\nPROVIDE\t(htmlcode = 0x40239b24);\nPROVIDE\t(print_hex_dump = 0x40239c6c);\nPROVIDE\t(str_array = 0x40239cb8);\nPROVIDE\t(str_array_w = 0x40239d3c);\nPROVIDE\t(str_array_b = 0x40239dc4);\nPROVIDE\t(word_to_lower_case = 0x40239e50);\nPROVIDE\t(copy_align4 = 0x40239e88);\nPROVIDE\t(go_deep_sleep = 0x40239f58);\nPROVIDE\t(reg_sct_bits = 0x40239f70);\nPROVIDE\t(web_int_vars = 0x4023a144);\nPROVIDE\t(websock_tx_frame = 0x4023b544);\nPROVIDE\t(websock_tx_close_err = 0x4023b588);\nPROVIDE\t(websock_rx_data = 0x4023b5e8);\nPROVIDE\t(rd_buf_sec_blk = 0x4023b98c);\nPROVIDE\t(wr_buf_sec_blk = 0x4023b9c4);\nPROVIDE\t(read_sys_const = 0x4023ba1c);\nPROVIDE\t(write_sys_const = 0x4023ba3c);\nPROVIDE\t(MdbGpioMux = 0x4023baa4);\nPROVIDE\t(MdbGpioPullUp = 0x4023baf0);\nPROVIDE\t(MdbGpioOd = 0x4023bb48);\nPROVIDE\t(MdbGetSntpTimeLw = 0x4023bba8);\nPROVIDE\t(MdbMacTime = 0x4023bbd8);\nPROVIDE\t(MdbUserFunc = 0x4023bc10);\nPROVIDE\t(MdbVcc = 0x4023bc60);\nPROVIDE\t(MdbAdc = 0x4023bca4);\nPROVIDE\t(MdbGpioFunc = 0x4023bcf4);\nPROVIDE\t(MdbOut55AA = 0x4023bd5c);\nPROVIDE\t(mbd_fini = 0x4023bd94);\nPROVIDE\t(SetMdbErr = 0x4023be10);\nPROVIDE\t(RdMdbData = 0x4023be40);\nPROVIDE\t(ReadMdbData = 0x4023bef8);\nPROVIDE\t(WrMdbData = 0x4023bf4c);\nPROVIDE\t(MdbFunc = 0x4023bfd0);\nPROVIDE\t(mdb_tcp_disconnect = 0x4023c1cc);\nPROVIDE\t(mdb_tcp_listen = 0x4023c1e4);\nPROVIDE\t(mdb_tcp_recv = 0x4023c204);\nPROVIDE\t(mdb_tcp_close = 0x4023c364);\nPROVIDE\t(mdb_tcp_start = 0x4023c39c);\nPROVIDE\t(sar_init = 0x4023c498);\nPROVIDE\t(sar_off = 0x4023c55c);\nPROVIDE\t(read_adcs = 0x4023c5c0);\nPROVIDE\t(sigma_delta_setup = 0x4023c66c);\nPROVIDE\t(sigma_delta_close = 0x4023c6c4);\nPROVIDE\t(set_sigma_duty_312KHz = 0x4023c714);\nPROVIDE\t(aFATAL_ERR_R6PHY = 0x4023c748);\nPROVIDE\t(esp_init_data_default = 0x4023c7dc);\nPROVIDE\t(ieee80211_opcap = 0x4023c8b0);\nPROVIDE\t(ip_addr_broadcast = 0x4023cde4);\nPROVIDE\t(ip_addr_any = 0x4023cde8);\nPROVIDE\t(memp_sizes = 0x4023ce20);\nPROVIDE\t(chip_v6_set_sense = 0x4023d204);\nPROVIDE\t(chip_v6_unset_chanfreq = 0x4023d208);\nPROVIDE\t(bit_popcount = 0x4023d47c);\nPROVIDE\t(tcp_pcb_lists = 0x4023d4a0);\nPROVIDE\t(tcp_persist_backoff = 0x4023d4b0);\nPROVIDE\t(tcp_backoff = 0x4023d4b8);\nPROVIDE\t(default_ssid = 0x4023d530);\nPROVIDE\t(eloop_cancel_timeout = 0x4023daac);\nPROVIDE\t(eloop_register_timeout = 0x4023dab0);\nPROVIDE\t(magic_cookie = 0x4023dba4);\nPROVIDE\t(ccmp = 0x4023dbbc);\nPROVIDE\t(tkip = 0x4023dbd4);\nPROVIDE\t(wep = 0x4023dbec);\nPROVIDE\t(lwip_standard_chksum = 0x4023dc04);\nPROVIDE\t(inet_chksum = 0x4023dc6c);\nPROVIDE\t(inet_chksum_pbuf = 0x4023dc88);\nPROVIDE\t(inet_chksum_pseudo = 0x4023dcf4);\nPROVIDE\t(inet_chksum_pseudo_partial = 0x4023ddb4);\nPROVIDE\t(sysinifname = 0x4023dfa4);\nPROVIDE\t(wifi_st_password = 0x4023e214);\nPROVIDE\t(wifi_st_name = 0x4023e220);\nPROVIDE\t(wifi_ap_password = 0x4023e228);\nPROVIDE\t(wifi_ap_name = 0x4023e234);\nPROVIDE\t(sntp_server_addresses = 0x4023e46c);\nPROVIDE\t(httpHostNameLocal = 0x4023e4dc);\nPROVIDE\t(file_label = 0x4023e6d0);\nPROVIDE\t(sector_filename = 0x4023e6d8);\nPROVIDE\t(overlay_filename = 0x4023e6e0);\nPROVIDE\t(sysconst_filename = 0x4023e6e8);\nPROVIDE\t(disk_err3_filename = 0x4023e6f4);\nPROVIDE\t(disk_err2_filename = 0x4023e704);\nPROVIDE\t(disk_err1_filename = 0x4023e714);\nPROVIDE\t(disk_ok_filename = 0x4023e724);\nPROVIDE\t(crlf_end_boundary = 0x4023e734);\nPROVIDE\t(HTTPAccessControlAllowOrigin = 0x4023e9e8);\nPROVIDE\t(HTTPfserror = 0x4023ea0c);\nPROVIDE\t(HTTPdefault = 0x4023ea4c);\nPROVIDE\t(HTTPfsupload = 0x4023ea98);\nPROVIDE\t(HTTPResponse = 0x4023eb78);\nPROVIDE\t(HTTPresponse_501_content = 0x4023ec48);\nPROVIDE\t(HTTPresponse_500_content = 0x4023ec7c);\nPROVIDE\t(HTTPresponse_418_content = 0x4023ec98);\nPROVIDE\t(HTTPresponse_414_content = 0x4023ecb0);\nPROVIDE\t(HTTPresponse_413_content = 0x4023ece8);\nPROVIDE\t(HTTPresponse_411_content = 0x4023ed24);\nPROVIDE\t(HTTPresponse_404_content = 0x4023ed54);\nPROVIDE\t(HTTPresponse_401_content = 0x4023ed6c);\nPROVIDE\t(HTTPresponse_501_head = 0x4023ed94);\nPROVIDE\t(HTTPresponse_500_head = 0x4023edb8);\nPROVIDE\t(HTTPresponse_429_head = 0x4023edd0);\nPROVIDE\t(HTTPresponse_418_head = 0x4023edf4);\nPROVIDE\t(HTTPresponse_414_head = 0x4023ee04);\nPROVIDE\t(HTTPresponse_413_head = 0x4023ee1c);\nPROVIDE\t(HTTPresponse_411_head = 0x4023ee38);\nPROVIDE\t(HTTPresponse_404_head = 0x4023ee48);\nPROVIDE\t(HTTPresponse_401_head = 0x4023ee54);\nPROVIDE\t(HTTPresponse_400_head = 0x4023ee8c);\nPROVIDE\t(HTTPresponse_304_head = 0x4023ee98);\nPROVIDE\t(HTTPresponse_302_head = 0x4023eea8);\nPROVIDE\t(HTTPresponse_200_head = 0x4023eeb0);\nPROVIDE\t(ncsi_txt_fname = 0x4023eeb4);\nPROVIDE\t(fsupload_fname = 0x4023eec0);\nPROVIDE\t(web_cgi_fname = 0x4023eecc);\nPROVIDE\t(http_default_file = 0x4023eed4);\nPROVIDE\t(txt_tcpsrv_out_of_mem = 0x4023f0ac);\nPROVIDE\t(txt_tcpsrv_already_initialized = 0x4023f0c4);\nPROVIDE\t(txt_tcpsrv_NULL_pointer = 0x4023f0e4);\nPROVIDE\t(WebSocketAddKey = 0x4023f354);\nPROVIDE\t(WebSocketHTTPOkKey = 0x4023f37c);\nPROVIDE\t(base64map = 0x4023f404);\nPROVIDE\t(txt_wspong = 0x4023f524);\nPROVIDE\t(txt_wsping = 0x4023f52c);\nPROVIDE\t(_irom0_text_end = 0x4023f5a4);\nPROVIDE\t(uart0_ = 0x60000000);\nPROVIDE\t(spi0_ = 0x60000200);\nPROVIDE\t(gpio_ = 0x60000300);\nPROVIDE\t(timer_ = 0x60000600);\nPROVIDE\t(rtc_ = 0x60000700);\nPROVIDE\t(iomux_ = 0x60000800);\nPROVIDE\t(wdt_ = 0x60000900);\nPROVIDE\t(sar_ = 0x60000d00);\nPROVIDE\t(uart1_ = 0x60000f00);\nPROVIDE\t(rtc_ram_ = 0x60001000);\nPROVIDE\t(rtc_mem_ = 0x60001100);\nPROVIDE\t(_memmap_cacheattr_unused_mask = 0xfffff00f);\nPROVIDE\t(_memmap_cacheattr_wb_strict = 0xfffff11f);\nPROVIDE\t(_memmap_cacheattr_wt_strict = 0xfffff11f);\nPROVIDE\t(_memmap_cacheattr_bp_strict = 0xfffff22f);\n>>>>>>> a15a387 update\n","old_contents":"<<<<<<< Upstream, based on 5ee9b049c02408d69696958a56fa91865e9d3ab1\nPROVIDE\t(_memmap_cacheattr_wb_base = 0x00000110);\r\nPROVIDE\t(_memmap_cacheattr_wt_base = 0x00000110);\r\nPROVIDE\t(_memmap_cacheattr_bp_base = 0x00000220);\r\nPROVIDE\t(_memmap_cacheattr_wb_allvalid = 0x22222112);\r\nPROVIDE\t(_memmap_cacheattr_wt_allvalid = 0x22222112);\r\nPROVIDE\t(_memmap_cacheattr_wb_trapnull = 0x2222211f);\r\nPROVIDE\t(_memmap_cacheattr_wba_trapnull = 0x2222211f);\r\nPROVIDE\t(_memmap_cacheattr_wbna_trapnull = 0x2222211f);\r\nPROVIDE\t(_memmap_cacheattr_wt_trapnull = 0x2222211f);\r\nPROVIDE\t(_memmap_cacheattr_bp_allvalid = 0x22222222);\r\nPROVIDE\t(_memmap_cacheattr_bp_trapnull = 0x2222222f);\r\nPROVIDE\t(_dport0_data_end = 0x3ff00000);\r\nPROVIDE\t(_dport0_data_start = 0x3ff00000);\r\nPROVIDE\t(_dport0_literal_end = 0x3ff00000);\r\nPROVIDE\t(_dport0_literal_start = 0x3ff00000);\r\nPROVIDE\t(_dport0_rodata_end = 0x3ff00000);\r\nPROVIDE\t(_dport0_rodata_start = 0x3ff00000);\r\nPROVIDE\t(dport_ = 0x3ff00000);\r\nPROVIDE\t(_data_start = 0x3ffe8000);\r\nPROVIDE\t(SDK_VERSION = 0x3ffe8000);\r\nPROVIDE\t(TmpSTAAPCloseAP = 0x3ffe8008);\r\nPROVIDE\t(memp_sizes_test = 0x3ffe800a);\r\nPROVIDE\t(tx_rf_ana_gain = 0x3ffe8012);\r\nPROVIDE\t(rx_gain_swp = 0x3ffe8040);\r\nPROVIDE\t(test_rffreq_txcap = 0x3ffe8060);\r\nPROVIDE\t(chip_version = 0x3ffe8064);\r\nPROVIDE\t(soft_wdt_interval = 0x3ffe8070);\r\nPROVIDE\t(NoiseTimerInterval = 0x3ffe8074);\r\nPROVIDE\t(sleep_start_wait_time = 0x3ffe807c);\r\nPROVIDE\t(CanDoFreqCal = 0x3ffe8084);\r\nPROVIDE\t(tcb = 0x3ffe8088);\r\nPROVIDE\t(timer2_ms_flag = 0x3ffe832d);\r\nPROVIDE\t(dhcps_flag = 0x3ffe832e);\r\nPROVIDE\t(dhcpc_flag = 0x3ffe832f);\r\nPROVIDE\t(reconnect_internal = 0x3ffe8331);\r\nPROVIDE\t(offer = 0x3ffe8344);\r\nPROVIDE\t(FRAM_Status = 0x3ffe8364);\r\nPROVIDE\t(i2c_delay_time = 0x3ffe8368);\r\nPROVIDE\t(HTTPCookie = 0x3ffe836c);\r\nPROVIDE\t(HTTPAuthorization = 0x3ffe8370);\r\nPROVIDE\t(HTTPboundary = 0x3ffe8374);\r\nPROVIDE\t(HTTPmultipartformdata = 0x3ffe8378);\r\nPROVIDE\t(HTTPContentType = 0x3ffe837c);\r\nPROVIDE\t(HTTPContentLength = 0x3ffe8380);\r\nPROVIDE\t(srvContenErr = 0x3ffe8384);\r\nPROVIDE\t(_data_end = 0x3ffe83c4);\r\nPROVIDE\t(_rodata_start = 0x3ffe83c4);\r\nPROVIDE\t(ethzero = 0x3ffe83c4);\r\nPROVIDE\t(ethbroadcast = 0x3ffe83ca);\r\nPROVIDE\t(year_lengths = 0x3ffe8480);\r\nPROVIDE\t(mon_lengths = 0x3ffe8488);\r\nPROVIDE\t(httpContentTypes = 0x3ffe84e8);\r\nPROVIDE\t(httpFileExtensions = 0x3ffe8534);\r\nPROVIDE\t(_bss_table_end = 0x3ffe8b64);\r\nPROVIDE\t(_bss_table_start = 0x3ffe8b64);\r\nPROVIDE\t(_rodata_end = 0x3ffe8b64);\r\nPROVIDE\t(_bss_start = 0x3ffe8b68);\r\nPROVIDE\t(etharp_cached_entry = 0x3ffe8b68);\r\nPROVIDE\t(arp_table = 0x3ffe8b6c);\r\nPROVIDE\t(g_ic = 0x3ffe8c5c);\r\nPROVIDE\t(BcnEb_update = 0x3ffe92e8);\r\nPROVIDE\t(BcnWithMcastSendStart = 0x3ffe92f5);\r\nPROVIDE\t(BcnWithMcastSendCnt = 0x3ffe92f6);\r\nPROVIDE\t(PendFreeBcnEb = 0x3ffe9310);\r\nPROVIDE\t(ApFreqCalTimer = 0x3ffe9314);\r\nPROVIDE\t(APRecvBcnStartTick = 0x3ffe9328);\r\nPROVIDE\t(gScanStruct = 0x3ffe9340);\r\nPROVIDE\t(connect_scan_flag = 0x3ffe93ec);\r\nPROVIDE\t(FreqCalCntForScan = 0x3ffe93ed);\r\nPROVIDE\t(TestStaFreqCalValInput = 0x3ffe93ee);\r\nPROVIDE\t(auth_type = 0x3ffe93f0);\r\nPROVIDE\t(scannum = 0x3ffe93f2);\r\nPROVIDE\t(interface_mask = 0x3ffe9420);\r\nPROVIDE\t(if_ctrl = 0x3ffe9440);\r\nPROVIDE\t(ip_id = 0x3ffe9460);\r\nPROVIDE\t(lmacConfMib = 0x3ffe9484);\r\nPROVIDE\t(our_tx_eb = 0x3ffe94a8);\r\nPROVIDE\t(xStart = 0x3ffe95d0);\r\nPROVIDE\t(g_phyFuns = 0x3ffe95e0);\r\nPROVIDE\t(rxiq_compute_num = 0x3ffe95e4);\r\nPROVIDE\t(rx_table_renew_en = 0x3ffe95e8);\r\nPROVIDE\t(check_result = 0x3ffe95ec);\r\nPROVIDE\t(chip6_sleep_params = 0x3ffe95f0);\r\nPROVIDE\t(chip6_phy_init_ctrl = 0x3ffe9684);\r\nPROVIDE\t(phy_freq_offset = 0x3ffe96f8);\r\nPROVIDE\t(do_pwctrl_flag = 0x3ffe96fa);\r\nPROVIDE\t(pwctrl_debug = 0x3ffe96fb);\r\nPROVIDE\t(txbk_dpdby_flag = 0x3ffe96fc);\r\nPROVIDE\t(sw_scan_mode = 0x3ffe96fe);\r\nPROVIDE\t(rxmax_ext_level = 0x3ffe96ff);\r\nPROVIDE\t(phy_rx_gain_dc_table = 0x3ffe9700);\r\nPROVIDE\t(periodic_cal_dc_num = 0x3ffe9714);\r\nPROVIDE\t(periodic_cal_flag = 0x3ffe9718);\r\nPROVIDE\t(bbpll_cal_flag = 0x3ffe9719);\r\nPROVIDE\t(phy_in_most_power = 0x3ffe971a);\r\nPROVIDE\t(init_rf_no_cal = 0x3ffe971b);\r\nPROVIDE\t(test_print_time = 0x3ffe971c);\r\nPROVIDE\t(phy_rx_gain_dc_flag = 0x3ffe9720);\r\nPROVIDE\t(phy_in_vdd33_offset = 0x3ffe9721);\r\nPROVIDE\t(phy_set_most_tpw_disbg = 0x3ffe9722);\r\nPROVIDE\t(phy_set_most_tpw_index = 0x3ffe9723);\r\nPROVIDE\t(adc_rand_noise = 0x3ffe9724);\r\nPROVIDE\t(dpd_bypass_original = 0x3ffe9728);\r\nPROVIDE\t(noise_array = 0x3ffe9730);\r\nPROVIDE\t(tout_dis_txpwr_track = 0x3ffe9740);\r\nPROVIDE\t(sleep_mode_flag = 0x3ffe9741);\r\nPROVIDE\t(phy_tx_power_out = 0x3ffe9744);\r\nPROVIDE\t(loop_pwctrl_pwdet_error_accum_high_power = 0x3ffe9746);\r\nPROVIDE\t(tx_pwctrl_pk_num = 0x3ffe9748);\r\nPROVIDE\t(tx_pwctrl_track_num = 0x3ffe9749);\r\nPROVIDE\t(loop_pwctrl_correct_atten_high_power = 0x3ffe974a);\r\nPROVIDE\t(rxiq_cover_fail_num = 0x3ffe974b);\r\nPROVIDE\t(periodic_cal_sat = 0x3ffe974c);\r\nPROVIDE\t(lslp_mem_opt_8266 = 0x3ffe974e);\r\nPROVIDE\t(software_slp_reject = 0x3ffe9750);\r\nPROVIDE\t(SDIO_slp_reject = 0x3ffe9751);\r\nPROVIDE\t(hardware_reject = 0x3ffe9752);\r\nPROVIDE\t(pmc = 0x3ffe9760);\r\nPROVIDE\t(flash_tmp = 0x3ffe9840);\r\nPROVIDE\t(pend_flag_noise_check = 0x3ffe98c8);\r\nPROVIDE\t(pend_flag_periodic_cal = 0x3ffe98d0);\r\nPROVIDE\t(idle_timer_reopen_flag = 0x3ffe98e8);\r\nPROVIDE\t(dbg_stop_sw_wdt = 0x3ffe98ea);\r\nPROVIDE\t(dbg_stop_hw_wdt = 0x3ffe98eb);\r\nPROVIDE\t(total_buffed_eb_num = 0x3ffe98ed);\r\nPROVIDE\t(HighestFreqOffsetInOneChk = 0x3ffe98f0);\r\nPROVIDE\t(LowestFreqOffsetInOneChk = 0x3ffe98f2);\r\nPROVIDE\t(DefFreqCalTimer = 0x3ffe98f4);\r\nPROVIDE\t(PktNumInOneChk = 0x3ffe9908);\r\nPROVIDE\t(buffed_eb_arr = 0x3ffe9a90);\r\nPROVIDE\t(tcp_timer = 0x3ffe9ce0);\r\nPROVIDE\t(recv_flags = 0x3ffe9ce4);\r\nPROVIDE\t(tcplen = 0x3ffe9ce6);\r\nPROVIDE\t(flags = 0x3ffe9ce8);\r\nPROVIDE\t(seqno = 0x3ffe9cec);\r\nPROVIDE\t(inseg = 0x3ffe9cf0);\r\nPROVIDE\t(deep_sleep_flag = 0x3ffea277);\r\nPROVIDE\t(cpu_overclock = 0x3ffea278);\r\nPROVIDE\t(event_cb = 0x3ffea27c);\r\nPROVIDE\t(status_led_output_level = 0x3ffea280);\r\nPROVIDE\t(done_cb = 0x3ffea284);\r\nPROVIDE\t(rst_if = 0x3ffea288);\r\nPROVIDE\t(default_interface = 0x3ffea2a4);\r\nPROVIDE\t(OpmodChgIsOnGoing = 0x3ffea2a5);\r\nPROVIDE\t(promiscuous_cb = 0x3ffea2a8);\r\nPROVIDE\t(event_TaskQueue = 0x3ffea2c0);\r\nPROVIDE\t(wDevCtrl = 0x3ffea3d0);\r\nPROVIDE\t(WdevTimOffSet = 0x3ffea578);\r\nPROVIDE\t(sta_con_timer = 0x3ffed6f8);\r\nPROVIDE\t(g_cnx_probe_rc_list_cb = 0x3ffed70c);\r\nPROVIDE\t(reconnect_flag = 0x3ffed710);\r\nPROVIDE\t(no_ap_found_index = 0x3ffed711);\r\nPROVIDE\t(client_address_plus = 0x3ffed98c);\r\nPROVIDE\t(client_address = 0x3ffed990);\r\nPROVIDE\t(server_address = 0x3ffed994);\r\nPROVIDE\t(broadcast_dhcps = 0x3ffed998);\r\nPROVIDE\t(dns_random = 0x3ffed99c);\r\nPROVIDE\t(dns_servers = 0x3ffed9a0);\r\nPROVIDE\t(dns_seqno = 0x3ffed9a8);\r\nPROVIDE\t(allrouters = 0x3ffee460);\r\nPROVIDE\t(allsystems = 0x3ffee464);\r\nPROVIDE\t(user_idle_func_working = 0x3ffee468);\r\nPROVIDE\t(FRAM_STORE_Readed = 0x3ffee469);\r\nPROVIDE\t(PowerCntTime = 0x3ffee46c);\r\nPROVIDE\t(PowerCnt = 0x3ffee470);\r\nPROVIDE\t(info = 0x3ffee474);\r\nPROVIDE\t(user_init_flag = 0x3ffee498);\r\nPROVIDE\t(lwip_timer_interval = 0x3ffee49a);\r\nPROVIDE\t(default_hostname = 0x3ffee49c);\r\nPROVIDE\t(current_iphdr_src = 0x3ffee4a0);\r\nPROVIDE\t(current_netif = 0x3ffee4a4);\r\nPROVIDE\t(current_iphdr_dest = 0x3ffee4a8);\r\nPROVIDE\t(current_header = 0x3ffee4ac);\r\nPROVIDE\t(tcp_listen_pcbs = 0x3ffee4b0);\r\nPROVIDE\t(dhcp_rx_options_given = 0x3ffee4b4);\r\nPROVIDE\t(dhcp_rx_options_val = 0x3ffee4c0);\r\nPROVIDE\t(dhcp_sntp_server_address = 0x3ffee4ec);\r\nPROVIDE\t(dhcps_lease = 0x3ffee4f0);\r\nPROVIDE\t(dns_table = 0x3ffee4f8);\r\nPROVIDE\t(fram_store = 0x3ffee958);\r\nPROVIDE\t(CntCurrent = 0x3ffee968);\r\nPROVIDE\t(cfg_meter = 0x3ffee96c);\r\nPROVIDE\t(Sensor_Edge = 0x3ffee974);\r\nPROVIDE\t(I2C_EEPROM_Error = 0x3ffee978);\r\nPROVIDE\t(wificonfig = 0x3ffee97c);\r\nPROVIDE\t(syscfg = 0x3ffeeaac);\r\nPROVIDE\t(fatCache = 0x3ffeeab8);\r\nPROVIDE\t(flash_firmware_size = 0x3ffeeac8);\r\nPROVIDE\t(_bss_end = 0x3ffeead0);\r\nPROVIDE\t(_heap_start = 0x3ffeead0);\r\nPROVIDE\t(flashchip = 0x3fffc714);\r\nPROVIDE\t(Te0 = 0x3fffccf0);\r\nPROVIDE\t(rcons = 0x3fffd0f0);\r\nPROVIDE\t(base64_table = 0x3fffd600);\r\nPROVIDE\t(ets_idle_cb = 0x3fffdab0);\r\nPROVIDE\t(timer_list = 0x3fffddb0);\r\nPROVIDE\t(UartDev = 0x3fffde10);\r\nPROVIDE\t(_sprintf_buf = 0x3fffe360);\r\nPROVIDE\t(print_mem_buf = 0x3fffe364);\r\nPROVIDE\t(_ResetVector = 0x40000080);\r\nPROVIDE\t(_xtos_set_exception_handler = 0x40000454);\r\nPROVIDE\t(__muldi3 = 0x40000650);\r\nPROVIDE\t(ets_set_idle_cb = 0x40000dc0);\r\nPROVIDE\t(ets_task = 0x40000dd0);\r\nPROVIDE\t(ets_run = 0x40000e04);\r\nPROVIDE\t(ets_post = 0x40000e24);\r\nPROVIDE\t(ets_intr_lock = 0x40000f74);\r\nPROVIDE\t(ets_intr_unlock = 0x40000f80);\r\nPROVIDE\t(ets_isr_attach = 0x40000f88);\r\nPROVIDE\t(ets_isr_mask = 0x40000f98);\r\nPROVIDE\t(ets_isr_unmask = 0x40000fa8);\r\nPROVIDE\t(ets_set_user_start = 0x40000fbc);\r\nPROVIDE\t(ets_memset = 0x400018a4);\r\nPROVIDE\t(ets_memcpy = 0x400018b4);\r\nPROVIDE\t(ets_memcmp = 0x400018d4);\r\nPROVIDE\t(ets_write_char = 0x40001da0);\r\nPROVIDE\t(ets_vprintf = 0x40001f00);\r\nPROVIDE\t(ets_install_putc1 = 0x4000242c);\r\nPROVIDE\t(ets_printf = 0x400024cc);\r\nPROVIDE\t(rtc_get_reset_reason = 0x400025e0);\r\nPROVIDE\t(ets_strcpy = 0x40002a88);\r\nPROVIDE\t(ets_strncpy = 0x40002a98);\r\nPROVIDE\t(ets_strcmp = 0x40002aa8);\r\nPROVIDE\t(ets_strncmp = 0x40002ab8);\r\nPROVIDE\t(ets_strlen = 0x40002ac8);\r\nPROVIDE\t(ets_bzero = 0x40002ae8);\r\nPROVIDE\t(ets_timer_setfn = 0x40002c48);\r\nPROVIDE\t(timer_insert = 0x40002c64);\r\nPROVIDE\t(ets_timer_disarm = 0x40002d40);\r\nPROVIDE\t(ets_timer_init = 0x40002e68);\r\nPROVIDE\t(ets_delay_us = 0x40002ecc);\r\nPROVIDE\t(ets_update_cpu_frequency = 0x40002f04);\r\nPROVIDE\t(ets_get_cpu_frequency = 0x40002f0c);\r\nPROVIDE\t(ets_wdt_get_mode = 0x40002f34);\r\nPROVIDE\t(roundup2 = 0x400031b4);\r\nPROVIDE\t(uart_buff_switch = 0x400038a4);\r\nPROVIDE\t(uart_div_modify = 0x400039d8);\r\nPROVIDE\t(Uart_Init = 0x40003a14);\r\nPROVIDE\t(SelectSpiFunction = 0x40003f58);\r\nPROVIDE\t(SPI_read_status = 0x400043c8);\r\nPROVIDE\t(SPI_write_status = 0x40004400);\r\nPROVIDE\t(Wait_SPI_Idle = 0x4000448c);\r\nPROVIDE\t(SPIFlashCnfig = 0x40004568);\r\nPROVIDE\t(Cache_Read_Enable = 0x40004678);\r\nPROVIDE\t(Cache_Read_Disable = 0x400047f0);\r\nPROVIDE\t(SPIReadModeCnfig = 0x400048ec);\r\nPROVIDE\t(SPIEraseBlock = 0x400049b4);\r\nPROVIDE\t(SPIEraseSector = 0x40004a00);\r\nPROVIDE\t(SPIWrite = 0x40004a4c);\r\nPROVIDE\t(gpio_output_set = 0x40004cd0);\r\nPROVIDE\t(gpio_input_get = 0x40004cf0);\r\nPROVIDE\t(gpio_pin_intr_state_set = 0x40004d90);\r\nPROVIDE\t(lldesc_build_chain = 0x40004f40);\r\nPROVIDE\t(lldesc_num2link = 0x40005050);\r\nPROVIDE\t(rom_chip_v5_disable_cca = 0x400060d0);\r\nPROVIDE\t(rom_chip_v5_enable_cca = 0x400060ec);\r\nPROVIDE\t(phy_get_romfuncs = 0x40006b08);\r\nPROVIDE\t(rom_i2c_readReg = 0x40007268);\r\nPROVIDE\t(rom_i2c_writeReg = 0x400072d8);\r\nPROVIDE\t(rom_i2c_writeReg_Mask = 0x4000730c);\r\nPROVIDE\t(aes_unwrap = 0x40009410);\r\nPROVIDE\t(hmac_md5 = 0x4000a2cc);\r\nPROVIDE\t(pbkdf2_sha1 = 0x4000b840);\r\nPROVIDE\t(hmac_sha1_vector = 0x4000b8b4);\r\nPROVIDE\t(hmac_sha1 = 0x4000ba28);\r\nPROVIDE\t(sha1_prf = 0x4000ba48);\r\nPROVIDE\t(__addsf3 = 0x4000c180);\r\nPROVIDE\t(__subsf3 = 0x4000c268);\r\nPROVIDE\t(__mulsf3 = 0x4000c3dc);\r\nPROVIDE\t(__fixunssfsi = 0x4000c4c4);\r\nPROVIDE\t(__muldf3 = 0x4000c8f0);\r\nPROVIDE\t(__divdf3 = 0x4000cb94);\r\nPROVIDE\t(__fixdfsi = 0x4000ccb8);\r\nPROVIDE\t(__truncdfsf2 = 0x4000cd5c);\r\nPROVIDE\t(__divdi3 = 0x4000ce60);\r\nPROVIDE\t(__umoddi3 = 0x4000d770);\r\nPROVIDE\t(__divsi3 = 0x4000dc88);\r\nPROVIDE\t(rc4_skip = 0x4000dd68);\r\nPROVIDE\t(memcpy = 0x4000df48);\r\nPROVIDE\t(__udivsi3 = 0x4000e21c);\r\nPROVIDE\t(__umodsi3 = 0x4000e268);\r\nPROVIDE\t(__floatunsisf = 0x4000e2a4);\r\nPROVIDE\t(__floatsisf = 0x4000e2ac);\r\nPROVIDE\t(__floatunsidf = 0x4000e2e8);\r\nPROVIDE\t(__floatsidf = 0x4000e2f0);\r\nPROVIDE\t(_stext = 0x40100000);\r\nPROVIDE\t(_text_start = 0x40100000);\r\nPROVIDE\t(jump_boot = 0x40100000);\r\nPROVIDE\t(set_qspi_flash_cache = 0x40100024);\r\nPROVIDE\t(uart0_write_char = 0x40100074);\r\nPROVIDE\t(call_jump_boot = 0x401000cc);\r\nPROVIDE\t(uart1_write_char = 0x4010013c);\r\nPROVIDE\t(user_uart_wait_tx_fifo_empty = 0x4010018c);\r\nPROVIDE\t(ets_timer_arm_new = 0x401001d0);\r\nPROVIDE\t(lmacIsActive = 0x401002a4);\r\nPROVIDE\t(lmacIsIdle = 0x401002b8);\r\nPROVIDE\t(lmacSetAcParam = 0x40100754);\r\nPROVIDE\t(lmacProcessTXStartData = 0x401007a8);\r\nPROVIDE\t(lmacProcessTxSuccess = 0x40100928);\r\nPROVIDE\t(GetAccess = 0x40100a6c);\r\nPROVIDE\t(lmacDiscardAgedMSDU = 0x40100a78);\r\nPROVIDE\t(lmacRecycleMPDU = 0x40100a8c);\r\nPROVIDE\t(lmacProcessTxTimeout = 0x40101064);\r\nPROVIDE\t(lmacProcessAllTxTimeout = 0x401010cc);\r\nPROVIDE\t(lmacProcessCollisions = 0x401010e0);\r\nPROVIDE\t(lmacProcessCollision = 0x40101140);\r\nPROVIDE\t(lmacMSDUAged = 0x401011c4);\r\nPROVIDE\t(lmacProcessCtsTimeout = 0x40101554);\r\nPROVIDE\t(lmacProcessAckTimeout = 0x4010158c);\r\nPROVIDE\t(lmacProcessRtsStart = 0x401015e4);\r\nPROVIDE\t(lmacProcessTxRtsError = 0x401015f0);\r\nPROVIDE\t(lmacProcessTxError = 0x40101690);\r\nPROVIDE\t(lmacTxFrame = 0x40101720);\r\nPROVIDE\t(lmacRxDone = 0x401018bc);\r\nPROVIDE\t(prvInsertBlockIntoFreeList = 0x401018dc);\r\nPROVIDE\t(pvPortMalloc = 0x40101924);\r\nPROVIDE\t(vPortFree = 0x401019d4);\r\nPROVIDE\t(pvPortCalloc = 0x40101a24);\r\nPROVIDE\t(pvPortZalloc = 0x40101a54);\r\nPROVIDE\t(pvPortRealloc = 0x40101a68);\r\nPROVIDE\t(xPortGetFreeHeapSize = 0x40101aa0);\r\nPROVIDE\t(vPortInitialiseBlocks = 0x40101aa8);\r\nPROVIDE\t(xPortWantedSizeAlign = 0x40101aac);\r\nPROVIDE\t(register_phy_ops = 0x40101ac4);\r\nPROVIDE\t(register_get_phy_addr = 0x40101ae4);\r\nPROVIDE\t(phy_change_channel = 0x40101aec);\r\nPROVIDE\t(phy_get_mactime = 0x40101b04);\r\nPROVIDE\t(unsign_to_sign = 0x40101b10);\r\nPROVIDE\t(phy_get_bb_freqoffset = 0x40101b48);\r\nPROVIDE\t(phy_get_bb_evm = 0x40101bac);\r\nPROVIDE\t(pm_rtc_clock_cali = 0x40101bcc);\r\nPROVIDE\t(clockgate_watchdog = 0x40101c88);\r\nPROVIDE\t(pp_soft_wdt_feed_local = 0x40101cec);\r\nPROVIDE\t(ppProcessTxQ = 0x40101d80);\r\nPROVIDE\t(ppFetchTxQFirstAvail = 0x40101df4);\r\nPROVIDE\t(ppDequeueTxQ = 0x40101e34);\r\nPROVIDE\t(ppRollBackTxQ = 0x40101e5c);\r\nPROVIDE\t(ppRecordBarRRC = 0x40101e80);\r\nPROVIDE\t(ppTxqUpdateBitmap = 0x40101e90);\r\nPROVIDE\t(ppEnqueueTxDone = 0x40101eb8);\r\nPROVIDE\t(ppEnqueueRxq = 0x40101eec);\r\nPROVIDE\t(ppDiscardMPDU = 0x401023d4);\r\nPROVIDE\t(pp_post = 0x401023f8);\r\nPROVIDE\t(pp_post2 = 0x40102484);\r\nPROVIDE\t(ppCalTxop = 0x401024ac);\r\nPROVIDE\t(ppCalFrameTimes = 0x4010252c);\r\nPROVIDE\t(RC_GetAckRate = 0x401025bc);\r\nPROVIDE\t(RC_GetRtsRate = 0x401025c8);\r\nPROVIDE\t(RC_GetAckTime = 0x401025d8);\r\nPROVIDE\t(RC_GetCtsTime = 0x401025ec);\r\nPROVIDE\t(RC_GetBlockAckTime = 0x40102624);\r\nPROVIDE\t(copy_s4d1 = 0x40102694);\r\nPROVIDE\t(copy_s1d4 = 0x40102728);\r\nPROVIDE\t(eRamRead = 0x401027c0);\r\nPROVIDE\t(eRamWrite = 0x401027e8);\r\nPROVIDE\t(rom_strlen = 0x4010280c);\r\nPROVIDE\t(rom_strcpy = 0x40102840);\r\nPROVIDE\t(rom_xstrcpy = 0x401028a4);\r\nPROVIDE\t(rom_xstrcmp = 0x401028f4);\r\nPROVIDE\t(rom_strchr = 0x4010293c);\r\nPROVIDE\t(get_align4_chr = 0x40102978);\r\nPROVIDE\t(write_align4_chr = 0x40102990);\r\nPROVIDE\t(Cache_Read_Enable_New = 0x401029b0);\r\nPROVIDE\t(spi_flash_read = 0x401029d8);\r\nPROVIDE\t(spi_flash_get_id = 0x40102b14);\r\nPROVIDE\t(spi_flash_read_status = 0x40102b64);\r\nPROVIDE\t(spi_flash_write_status = 0x40102ba0);\r\nPROVIDE\t(spi_flash_erase_sector = 0x40102bdc);\r\nPROVIDE\t(spi_flash_write = 0x40102c2c);\r\nPROVIDE\t(spi_flash_erase_block = 0x40102c94);\r\nPROVIDE\t(tcp_accept_null = 0x40102cdc);\r\nPROVIDE\t(tcp_new_port = 0x40102cf0);\r\nPROVIDE\t(tcp_close_shutdown = 0x40102d60);\r\nPROVIDE\t(dns_timer = 0x40102eb8);\r\nPROVIDE\t(igmp_timer = 0x40102ee4);\r\nPROVIDE\t(dhcp_timer_fine = 0x40102f10);\r\nPROVIDE\t(dhcp_timer_coarse = 0x40102f44);\r\nPROVIDE\t(rcUpdateTxDone = 0x40103140);\r\nPROVIDE\t(rcUpdateRxDone = 0x401031d4);\r\nPROVIDE\t(rcUpdateDataRxDone = 0x40103230);\r\nPROVIDE\t(rcGetSched = 0x4010324c);\r\nPROVIDE\t(rcGetRate = 0x40103330);\r\nPROVIDE\t(rcReachRetryLimit = 0x40103844);\r\nPROVIDE\t(trc_NeedRTS = 0x4010385c);\r\nPROVIDE\t(os_printf_plus = 0x4010392c);\r\nPROVIDE\t(system_restart_core = 0x40103a58);\r\nPROVIDE\t(system_deep_sleep_local_2 = 0x40103a94);\r\nPROVIDE\t(system_get_time = 0x40103b04);\r\nPROVIDE\t(system_os_post = 0x40103b1c);\r\nPROVIDE\t(system_rtc_mem_write = 0x40103b50);\r\nPROVIDE\t(system_rtc_mem_read = 0x40103ba8);\r\nPROVIDE\t(wDev_MacTim1SetFunc = 0x40103fa4);\r\nPROVIDE\t(wDev_MacTim1Arm = 0x40103fc4);\r\nPROVIDE\t(wDev_ProcessFiq = 0x4010405c);\r\nPROVIDE\t(wDev_EnableTransmit = 0x401043a0);\r\nPROVIDE\t(wDev_DisableTransmit = 0x401043d8);\r\nPROVIDE\t(Tx_Copy2Queue = 0x401043f8);\r\nPROVIDE\t(wDev_ProcessCollision = 0x40104440);\r\nPROVIDE\t(wDev_GetTxqCollisions = 0x40104464);\r\nPROVIDE\t(wDev_ClearTxqCollisions = 0x40104478);\r\nPROVIDE\t(wDev_SetWaitingQueue = 0x40104494);\r\nPROVIDE\t(wDev_ClearWaitingQueue = 0x401044dc);\r\nPROVIDE\t(wDev_SetFrameAckType = 0x40104500);\r\nPROVIDE\t(wDev_AppendRxBlocks = 0x40104564);\r\nPROVIDE\t(wDev_AppendRxAmpduLensBlocks = 0x401046a8);\r\nPROVIDE\t(wDev_GetBAInfo = 0x4010477c);\r\nPROVIDE\t(wDevDisableRx = 0x401047b0);\r\nPROVIDE\t(store_exception_error = 0x40104c70);\r\nPROVIDE\t(fatal_error = 0x40104ca8);\r\nPROVIDE\t(default_exception_handler = 0x40104cc4);\r\nPROVIDE\t(chm_get_current_channel = 0x40104cdc);\r\nPROVIDE\t(__divsf3_aux = 0x40104ce8);\r\nPROVIDE\t(__divsf3 = 0x40104d64);\r\nPROVIDE\t(__fixsfsi = 0x40104e20);\r\nPROVIDE\t(esf_rx_buf_alloc = 0x40104e64);\r\nPROVIDE\t(gpio_int_handler = 0x40104ec4);\r\nPROVIDE\t(i2c_delay = 0x40104f30);\r\nPROVIDE\t(i2c_Stop = 0x40104f44);\r\nPROVIDE\t(i2c_WriteBit = 0x40104f78);\r\nPROVIDE\t(i2c_ReadBit = 0x40104fac);\r\nPROVIDE\t(i2c_Write = 0x40104fd8);\r\nPROVIDE\t(i2c_Read = 0x40105014);\r\nPROVIDE\t(i2c_Start = 0x40105050);\r\nPROVIDE\t(GPIO_intr_handler = 0x401050ac);\r\nPROVIDE\t(__ashrdi3 = 0x4010510c);\r\nPROVIDE\t(__modsi3 = 0x40105124);\r\nPROVIDE\t(__lshrdi3 = 0x40105170);\r\nPROVIDE\t(eraminfo = 0x40105188);\r\nPROVIDE\t(_etext = 0x40105190);\r\nPROVIDE\t(_lit4_start = 0x40105190);\r\nPROVIDE\t(_text_end = 0x40105190);\r\nPROVIDE\t(check_timeouts_timer = 0x40105190);\r\nPROVIDE\t(lwip_if_queues = 0x401051a4);\r\nPROVIDE\t(hostname = 0x401051ac);\r\nPROVIDE\t(xBlockAllocatedBit = 0x401051b0);\r\nPROVIDE\t(xFreeBytesRemaining = 0x401051b4);\r\nPROVIDE\t(pxEnd = 0x401051b8);\r\nPROVIDE\t(netif_default = 0x401051bc);\r\nPROVIDE\t(netif_list = 0x401051c0);\r\nPROVIDE\t(raw_pcbs = 0x401051c4);\r\nPROVIDE\t(flash_size = 0x401051c8);\r\nPROVIDE\t(flash_read = 0x401051cc);\r\nPROVIDE\t(tcp_tmp_pcb = 0x401051d0);\r\nPROVIDE\t(tcp_tw_pcbs = 0x401051d4);\r\nPROVIDE\t(tcp_active_pcbs = 0x401051d8);\r\nPROVIDE\t(tcp_bound_pcbs = 0x401051dc);\r\nPROVIDE\t(tcp_ticks = 0x401051e0);\r\nPROVIDE\t(tcp_input_pcb = 0x401051e4);\r\nPROVIDE\t(recv_data = 0x401051e8);\r\nPROVIDE\t(ackno = 0x401051ec);\r\nPROVIDE\t(tcphdr = 0x401051f0);\r\nPROVIDE\t(tcpip_tcp_timer_active = 0x401051f4);\r\nPROVIDE\t(timeouts_last_time = 0x401051f8);\r\nPROVIDE\t(next_timeout = 0x401051fc);\r\nPROVIDE\t(udp_pcbs = 0x40105200);\r\nPROVIDE\t(dhcps_lease_time = 0x40105204);\r\nPROVIDE\t(renew = 0x40105208);\r\nPROVIDE\t(plist = 0x4010520c);\r\nPROVIDE\t(dhcps_lease_flag = 0x40105210);\r\nPROVIDE\t(pcb_dhcps = 0x40105214);\r\nPROVIDE\t(dns_payload = 0x40105218);\r\nPROVIDE\t(dns_pcb = 0x4010521c);\r\nPROVIDE\t(igmp_group_list = 0x40105220);\r\nPROVIDE\t(GPIO_TaskQueue = 0x40105224);\r\nPROVIDE\t(buf_scan_infos = 0x4010522c);\r\nPROVIDE\t(total_scan_infos = 0x401059ac);\r\nPROVIDE\t(flg_wifi_sleep_enable = 0x401059b0);\r\nPROVIDE\t(st_disconn_timer = 0x401059b4);\r\nPROVIDE\t(flg_sleep = 0x401059c8);\r\nPROVIDE\t(st_reconn_flg = 0x401059cc);\r\nPROVIDE\t(st_reconn_count = 0x401059d0);\r\nPROVIDE\t(flg_open_all_service = 0x401059d4);\r\nPROVIDE\t(probe_requests_count = 0x401059d8);\r\nPROVIDE\t(buf_probe_requests = 0x401059dc);\r\nPROVIDE\t(sntp = 0x40105bdc);\r\nPROVIDE\t(numFiles = 0x40105be0);\r\nPROVIDE\t(fatCacheID = 0x40105be4);\r\nPROVIDE\t(WEBFSStubs = 0x40105be8);\r\nPROVIDE\t(isWEBFSLocked = 0x40105d68);\r\nPROVIDE\t(disk_base_addr = 0x40105d6c);\r\nPROVIDE\t(phcfg = 0x40105d70);\r\nPROVIDE\t(wdrv_bufn = 0x40105d74);\r\nPROVIDE\t(_lit4_end = 0x40105d78);\r\nPROVIDE\t(_irom0_text_start = 0x40207000);\r\nPROVIDE\t(puts_buf = 0x40207004);\r\nPROVIDE\t(read_wifi_config = 0x40207048);\r\nPROVIDE\t(uart_wait_tx_fifo_empty = 0x402070e8);\r\nPROVIDE\t(loader = 0x40207100);\r\nPROVIDE\t(read_macaddr_from_otp = 0x4020713c);\r\nPROVIDE\t(tst_cfg_wifi = 0x402071a8);\r\nPROVIDE\t(startup_uart_init = 0x402072cc);\r\nPROVIDE\t(init_wifi = 0x40207338);\r\nPROVIDE\t(startup = 0x40207480);\r\nPROVIDE\t(init_fn = 0x40207740);\r\nPROVIDE\t(eagle_lwip_if_alloc = 0x4020778c);\r\nPROVIDE\t(eagle_lwip_getif = 0x40207904);\r\nPROVIDE\t(task_if0 = 0x40207924);\r\nPROVIDE\t(task_if1 = 0x4020795c);\r\nPROVIDE\t(eagle_lwip_if_free = 0x40207994);\r\nPROVIDE\t(free_entry = 0x402079ec);\r\nPROVIDE\t(find_entry = 0x40207a48);\r\nPROVIDE\t(etharp_send_ip = 0x40207b24);\r\nPROVIDE\t(update_arp_entry = 0x40207b78);\r\nPROVIDE\t(etharp_tmr = 0x40207c1c);\r\nPROVIDE\t(etharp_find_addr = 0x40207c74);\r\nPROVIDE\t(etharp_request = 0x40207cc8);\r\nPROVIDE\t(etharp_output_to_arp_index = 0x40207d98);\r\nPROVIDE\t(etharp_query = 0x40207e10);\r\nPROVIDE\t(etharp_output = 0x40207fc0);\r\nPROVIDE\t(ethernet_input = 0x402080b0);\r\nPROVIDE\t(etharp_cleanup_netif = 0x402082ac);\r\nPROVIDE\t(ieee80211_rate_ref_init = 0x40208374);\r\nPROVIDE\t(ieee80211_freedom_inside_cb = 0x4020838c);\r\nPROVIDE\t(ieee80211_freedom_init = 0x402083bc);\r\nPROVIDE\t(ieee80211_user_ie_init = 0x402083e0);\r\nPROVIDE\t(ieee80211_ifattach = 0x402083fc);\r\nPROVIDE\t(ieee80211_mhz2ieee = 0x40208464);\r\nPROVIDE\t(ieee80211_chan2ieee = 0x402084c4);\r\nPROVIDE\t(ieee80211_ieee2mhz = 0x402084e0);\r\nPROVIDE\t(ieee80211_find_channel = 0x40208520);\r\nPROVIDE\t(ieee80211_find_channel_byieee = 0x4020854c);\r\nPROVIDE\t(wifi_mode_set = 0x402085a0);\r\nPROVIDE\t(get_iav_key = 0x4020877c);\r\nPROVIDE\t(register_ieee80211_action_vendor_get_key_cb = 0x4020879c);\r\nPROVIDE\t(unregister_ieee80211_action_vendor_get_key_cb = 0x402087b0);\r\nPROVIDE\t(ieee80211_add_action_vendor_spec_esp = 0x402087c8);\r\nPROVIDE\t(ieee80211_alloc_action_vendor_spec = 0x40208810);\r\nPROVIDE\t(ieee80211_send_action_vendor_spec = 0x40208920);\r\nPROVIDE\t(ieee80211_recv_action_vendor_spec = 0x40208ab8);\r\nPROVIDE\t(ieee80211_action_vendor_spec_attach = 0x40208bc4);\r\nPROVIDE\t(register_ieee80211_action_vendor_spec_cb = 0x40208c04);\r\nPROVIDE\t(unregister_ieee80211_action_vendor_spec_cb = 0x40208c18);\r\nPROVIDE\t(ieee80211_crypto_attach = 0x40208c24);\r\nPROVIDE\t(ieee80211_crypto_available = 0x40208c28);\r\nPROVIDE\t(ieee80211_crypto_setkey = 0x40208c2c);\r\nPROVIDE\t(ieee80211_crypto_encap = 0x40208c30);\r\nPROVIDE\t(ieee80211_crypto_decap = 0x40208c88);\r\nPROVIDE\t(ieee80211_getmgtframe = 0x40208cf8);\r\nPROVIDE\t(ieee80211_hostap_attach = 0x4020939c);\r\nPROVIDE\t(hostap_handle_timer = 0x402094a0);\r\nPROVIDE\t(hostap_input = 0x40209538);\r\nPROVIDE\t(wifi_softap_start = 0x4020a4b8);\r\nPROVIDE\t(wifi_softap_stop = 0x4020a624);\r\nPROVIDE\t(ieee80211_ht_attach = 0x4020a7cc);\r\nPROVIDE\t(ieee80211_ht_node_init = 0x4020a820);\r\nPROVIDE\t(ieee80211_ht_node_cleanup = 0x4020a860);\r\nPROVIDE\t(ieee80211_parse_htcap = 0x4020a898);\r\nPROVIDE\t(ieee80211_ht_updateparams = 0x4020a998);\r\nPROVIDE\t(ieee80211_setup_htrates = 0x4020aab0);\r\nPROVIDE\t(ieee80211_setup_basic_htrates = 0x4020ab7c);\r\nPROVIDE\t(ieee80211_add_htcap = 0x4020aec8);\r\nPROVIDE\t(ieee80211_add_htcap_vendor = 0x4020aee4);\r\nPROVIDE\t(ieee80211_add_htinfo = 0x4020b008);\r\nPROVIDE\t(ieee80211_add_htinfo_vendor = 0x4020b024);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_head = 0x4020b264);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_mesh_assoc = 0x4020b29c);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_mesh_group = 0x4020b320);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_simple_pair = 0x4020b350);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_freq_annon = 0x4020b3a0);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_now = 0x4020b3d8);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_ssid = 0x4020b410);\r\nPROVIDE\t(ieee80211_add_ie_vendor_esp_manufacturer = 0x4020b450);\r\nPROVIDE\t(ieee80211_deliver_data = 0x4020b4a0);\r\nPROVIDE\t(ieee80211_decap = 0x4020b4f4);\r\nPROVIDE\t(ieee80211_setup_rates = 0x4020b5f8);\r\nPROVIDE\t(ieee80211_alloc_challenge = 0x4020b668);\r\nPROVIDE\t(ieee80211_parse_beacon = 0x4020b6a4);\r\nPROVIDE\t(ieee80211_parse_wpa = 0x4020bc78);\r\nPROVIDE\t(ieee80211_parse_rsn = 0x4020bd8c);\r\nPROVIDE\t(ieee80211_parse_action = 0x4020be8c);\r\nPROVIDE\t(ieee80211_setup_rateset = 0x4020bf28);\r\nPROVIDE\t(ieee80211_mesh_quick_init = 0x4020bf38);\r\nPROVIDE\t(ieee80211_mesh_quick_deinit = 0x4020bfa8);\r\nPROVIDE\t(ieee80211_mesh_quick_set = 0x4020bfd8);\r\nPROVIDE\t(ieee80211_mesh_quick_get = 0x4020c0d4);\r\nPROVIDE\t(ieee80211_mesh_quick_ie_add = 0x4020c1a0);\r\nPROVIDE\t(ieee80211_output_pbuf = 0x4020c1d8);\r\nPROVIDE\t(ieee80211_send_setup = 0x4020c448);\r\nPROVIDE\t(ieee80211_mgmt_output = 0x4020c57c);\r\nPROVIDE\t(ieee80211_tx_mgt_cb = 0x4020c660);\r\nPROVIDE\t(ieee80211_send_nulldata = 0x4020c668);\r\nPROVIDE\t(ieee80211_add_rates = 0x4020cad4);\r\nPROVIDE\t(ieee80211_add_xrates = 0x4020cb24);\r\nPROVIDE\t(ieee80211_send_probereq = 0x4020cbf4);\r\nPROVIDE\t(ieee80211_getcapinfo = 0x4020ce08);\r\nPROVIDE\t(ieee80211_send_mgmt = 0x4020ce68);\r\nPROVIDE\t(ieee80211_alloc_proberesp = 0x4020d410);\r\nPROVIDE\t(ieee80211_send_proberesp = 0x4020d5ec);\r\nPROVIDE\t(ieee80211_alloc_deauth = 0x4020d734);\r\nPROVIDE\t(ieee80211_send_deauth = 0x4020d774);\r\nPROVIDE\t(ieee80211_freedom_output = 0x4020d8b0);\r\nPROVIDE\t(ieee80211_beacon_alloc = 0x4020dc98);\r\nPROVIDE\t(ieee80211_phy_init = 0x4020de30);\r\nPROVIDE\t(ieee80211_phy_type_get = 0x4020de64);\r\nPROVIDE\t(ieee80211_setup_ratetable = 0x4020de80);\r\nPROVIDE\t(ieee80211_psq_init = 0x4020df10);\r\nPROVIDE\t(ieee80211_psq_cleanup = 0x4020df30);\r\nPROVIDE\t(ieee80211_set_tim = 0x4020df38);\r\nPROVIDE\t(ieee80211_pwrsave = 0x4020df78);\r\nPROVIDE\t(pwrsave_flushq = 0x4020dfe0);\r\nPROVIDE\t(ieee80211_node_pwrsave = 0x4020e090);\r\nPROVIDE\t(ieee80211_proto_attach = 0x4020e0cc);\r\nPROVIDE\t(ieee80211_set_shortslottime = 0x4020e0f4);\r\nPROVIDE\t(ieee80211_iserp_rateset = 0x4020e110);\r\nPROVIDE\t(ieee80211_wme_initparams = 0x4020e144);\r\nPROVIDE\t(ieee80211_wme_updateparams = 0x4020e148);\r\nPROVIDE\t(ieee80211_mlme_connect_bss = 0x4020e150);\r\nPROVIDE\t(ieee80211_rfid_locp_recv_open = 0x4020e1d0);\r\nPROVIDE\t(ieee80211_rfid_locp_recv_close = 0x4020e20c);\r\nPROVIDE\t(ieee80211_rfid_locp_recv_reset = 0x4020e224);\r\nPROVIDE\t(ieee80211_rfid_locp_recv = 0x4020e244);\r\nPROVIDE\t(register_ieee80211_rfid_locp_recv_cb = 0x4020e260);\r\nPROVIDE\t(unregister_ieee80211_rfid_locp_recv_cb = 0x4020e274);\r\nPROVIDE\t(ieee80211_scan_attach = 0x4020e28c);\r\nPROVIDE\t(scan_start = 0x4020e320);\r\nPROVIDE\t(scan_pm_channel_op_cb = 0x4020e4e4);\r\nPROVIDE\t(scan_cancel = 0x4020e684);\r\nPROVIDE\t(scan_add_bssid = 0x4020e7e0);\r\nPROVIDE\t(scan_remove_bssid = 0x4020e804);\r\nPROVIDE\t(scan_hidden_ssid = 0x4020e810);\r\nPROVIDE\t(scan_add_probe_ssid = 0x4020e818);\r\nPROVIDE\t(scan_remove_probe_ssid = 0x4020e86c);\r\nPROVIDE\t(scan_clear_channles = 0x4020e9ac);\r\nPROVIDE\t(scan_set_desChan = 0x4020ea20);\r\nPROVIDE\t(scan_get_type = 0x4020ea2c);\r\nPROVIDE\t(cannel_scan_connect_state = 0x4020ea34);\r\nPROVIDE\t(scan_connect_state = 0x4020ea4c);\r\nPROVIDE\t(scan_check_hidden = 0x4020ea94);\r\nPROVIDE\t(scan_profile_check = 0x4020eac8);\r\nPROVIDE\t(scan_parse_beacon = 0x4020ee74);\r\nPROVIDE\t(sta_status_set = 0x4020f244);\r\nPROVIDE\t(ieee80211_sta_new_state = 0x4020f2b0);\r\nPROVIDE\t(sta_input = 0x4020f640);\r\nPROVIDE\t(ieee80211_parse_wmeparams = 0x4020fb8c);\r\nPROVIDE\t(wifi_station_start = 0x40210188);\r\nPROVIDE\t(wifi_station_stop = 0x402101f8);\r\nPROVIDE\t(ic_get_addr = 0x40210254);\r\nPROVIDE\t(ic_set_opmode = 0x40210260);\r\nPROVIDE\t(ic_enable_interface = 0x40210274);\r\nPROVIDE\t(ic_interface_enabled = 0x402102c4);\r\nPROVIDE\t(ic_disable_interface = 0x402102d8);\r\nPROVIDE\t(ic_is_pure_sta = 0x40210320);\r\nPROVIDE\t(ic_get_ptk_alg = 0x4021033c);\r\nPROVIDE\t(ic_get_gtk_alg = 0x4021034c);\r\nPROVIDE\t(ic_set_ptk_alg = 0x4021035c);\r\nPROVIDE\t(ic_set_gtk_alg = 0x4021036c);\r\nPROVIDE\t(ic_interface_is_p2p = 0x4021037c);\r\nPROVIDE\t(ic_set_vif = 0x40210414);\r\nPROVIDE\t(ic_set_sta = 0x402104d4);\r\nPROVIDE\t(ic_bss_info_update = 0x402105ac);\r\nPROVIDE\t(ic_set_key = 0x40210608);\r\nPROVIDE\t(ic_remove_key = 0x40210664);\r\nPROVIDE\t(ic_get_rssi = 0x40210678);\r\nPROVIDE\t(lwip_init = 0x402106b4);\r\nPROVIDE\t(ip_route = 0x402106f4);\r\nPROVIDE\t(ip_input = 0x4021077c);\r\nPROVIDE\t(ip_output_if_opt = 0x402109e0);\r\nPROVIDE\t(ip_output_if = 0x40210bf4);\r\nPROVIDE\t(ip_output = 0x40210c1c);\r\nPROVIDE\t(ip_router = 0x40210c6c);\r\nPROVIDE\t(ip4_addr_isbroadcast = 0x40210cc8);\r\nPROVIDE\t(ip4_addr_netmask_valid = 0x40210d08);\r\nPROVIDE\t(ipaddr_aton = 0x40210d54);\r\nPROVIDE\t(ipaddr_addr = 0x40210f40);\r\nPROVIDE\t(ipaddr_ntoa_r = 0x40210f5c);\r\nPROVIDE\t(ipaddr_ntoa = 0x40211030);\r\nPROVIDE\t(lmacInitAc = 0x40211048);\r\nPROVIDE\t(lmacInit = 0x4021107c);\r\nPROVIDE\t(lmacSetRetryLimit = 0x4021112c);\r\nPROVIDE\t(prvHeapInit = 0x40211164);\r\nPROVIDE\t(netif_init = 0x402111a4);\r\nPROVIDE\t(netif_find = 0x402111a8);\r\nPROVIDE\t(netif_set_default = 0x402111e0);\r\nPROVIDE\t(netif_set_ipaddr = 0x402111f0);\r\nPROVIDE\t(netif_set_addr = 0x4021125c);\r\nPROVIDE\t(netif_add = 0x40211294);\r\nPROVIDE\t(netif_set_netmask = 0x40211304);\r\nPROVIDE\t(netif_set_gw = 0x40211310);\r\nPROVIDE\t(netif_set_up = 0x4021131c);\r\nPROVIDE\t(netif_set_down = 0x4021135c);\r\nPROVIDE\t(netif_remove = 0x40211380);\r\nPROVIDE\t(netif_set_link_up = 0x402113e4);\r\nPROVIDE\t(netif_set_link_down = 0x40211434);\r\nPROVIDE\t(_sprintf_out = 0x4021144c);\r\nPROVIDE\t(__wrap_os_printf_plus = 0x4021148c);\r\nPROVIDE\t(ets_sprintf = 0x402114f0);\r\nPROVIDE\t(pbuf_header = 0x4021153c);\r\nPROVIDE\t(pbuf_ref = 0x402115cc);\r\nPROVIDE\t(pbuf_free = 0x402115d8);\r\nPROVIDE\t(pbuf_alloc = 0x40211640);\r\nPROVIDE\t(pbuf_realloc = 0x402117a4);\r\nPROVIDE\t(pbuf_clen = 0x402117f4);\r\nPROVIDE\t(pbuf_cat = 0x40211808);\r\nPROVIDE\t(pbuf_chain = 0x40211834);\r\nPROVIDE\t(pbuf_dechain = 0x40211850);\r\nPROVIDE\t(pbuf_copy = 0x40211884);\r\nPROVIDE\t(pbuf_copy_partial = 0x40211950);\r\nPROVIDE\t(pbuf_take = 0x40211a00);\r\nPROVIDE\t(pbuf_coalesce = 0x40211a7c);\r\nPROVIDE\t(pbuf_get_at = 0x40211abc);\r\nPROVIDE\t(pbuf_memcmp = 0x40211ae0);\r\nPROVIDE\t(pbuf_memfind = 0x40211b54);\r\nPROVIDE\t(pbuf_strstr = 0x40211bb8);\r\nPROVIDE\t(rf_init = 0x40211c04);\r\nPROVIDE\t(bb_init = 0x40211c20);\r\nPROVIDE\t(phy_init = 0x40211c38);\r\nPROVIDE\t(RFChannelSel = 0x40211c68);\r\nPROVIDE\t(phy_delete_channel = 0x40211c84);\r\nPROVIDE\t(phy_enable_agc = 0x40211c9c);\r\nPROVIDE\t(phy_disable_agc = 0x40211cb4);\r\nPROVIDE\t(phy_initialize_bb = 0x40211ccc);\r\nPROVIDE\t(phy_set_sense = 0x40211ce4);\r\nPROVIDE\t(ram_tx_mac_enable = 0x40211cfc);\r\nPROVIDE\t(ram_tx_mac_disable = 0x40211d00);\r\nPROVIDE\t(rtc_mem_backup = 0x40211d04);\r\nPROVIDE\t(rtc_mem_recovery = 0x40211d34);\r\nPROVIDE\t(set_cal_rxdc = 0x40211d68);\r\nPROVIDE\t(set_rx_gain_cal_iq = 0x40211e20);\r\nPROVIDE\t(gen_rx_gain_table = 0x40212178);\r\nPROVIDE\t(pbus_set_rxbbgain = 0x402122d0);\r\nPROVIDE\t(set_rx_gain_testchip_50 = 0x40212354);\r\nPROVIDE\t(ram_get_corr_power = 0x4021268c);\r\nPROVIDE\t(check_data_func = 0x4021277c);\r\nPROVIDE\t(do_noisefloor_lsleep_v50 = 0x4021279c);\r\nPROVIDE\t(do_noisefloor = 0x402127d0);\r\nPROVIDE\t(start_dig_rx = 0x40212844);\r\nPROVIDE\t(stop_dig_rx = 0x4021288c);\r\nPROVIDE\t(chip_v6_set_chanfreq = 0x402128b8);\r\nPROVIDE\t(tx_cap_init = 0x402128e8);\r\nPROVIDE\t(target_power_add_backoff = 0x40212a9c);\r\nPROVIDE\t(tx_pwctrl_init_cal = 0x40212aec);\r\nPROVIDE\t(tx_atten_set_interp = 0x40212c54);\r\nPROVIDE\t(tx_pwctrl_init = 0x40212ec4);\r\nPROVIDE\t(ram_get_noisefloor = 0x40212fb8);\r\nPROVIDE\t(get_noisefloor_sat = 0x40212fd4);\r\nPROVIDE\t(ram_set_noise_floor = 0x40213004);\r\nPROVIDE\t(ram_start_noisefloor = 0x40213060);\r\nPROVIDE\t(read_hw_noisefloor = 0x402130ac);\r\nPROVIDE\t(noise_check_loop = 0x402130d8);\r\nPROVIDE\t(noise_init = 0x40213230);\r\nPROVIDE\t(target_power_backoff = 0x40213430);\r\nPROVIDE\t(sdt_on_noise_start = 0x40213484);\r\nPROVIDE\t(chip_v6_set_chan_rx_cmp = 0x40213504);\r\nPROVIDE\t(chip_v6_set_chan_misc = 0x40213690);\r\nPROVIDE\t(phy_dig_spur_set = 0x40213734);\r\nPROVIDE\t(phy_dig_spur_prot = 0x40213a8c);\r\nPROVIDE\t(chip_v6_rxmax_ext_dig = 0x40213cc4);\r\nPROVIDE\t(chip_v6_rxmax_ext = 0x40213d10);\r\nPROVIDE\t(phy_bb_rx_cfg = 0x40213dc0);\r\nPROVIDE\t(uart_wait_idle = 0x402141c8);\r\nPROVIDE\t(phy_pbus_soc_cfg = 0x40214204);\r\nPROVIDE\t(phy_gpio_cfg = 0x402142c4);\r\nPROVIDE\t(tx_cont_en = 0x4021460c);\r\nPROVIDE\t(tx_cont_dis = 0x402146b4);\r\nPROVIDE\t(tx_cont_cfg = 0x40214708);\r\nPROVIDE\t(chip_v6_initialize_bb = 0x40214728);\r\nPROVIDE\t(periodic_cal = 0x4021488c);\r\nPROVIDE\t(bbpll_cal = 0x40214970);\r\nPROVIDE\t(periodic_cal_top = 0x40214a08);\r\nPROVIDE\t(register_chipv6_phy_init_param = 0x40214a68);\r\nPROVIDE\t(change_bbpll160_sleep = 0x40214d14);\r\nPROVIDE\t(change_bbpll160 = 0x40214e40);\r\nPROVIDE\t(set_crystal_uart = 0x40214e78);\r\nPROVIDE\t(ant_switch_init = 0x40214f0c);\r\nPROVIDE\t(reduce_current_init = 0x40214fb8);\r\nPROVIDE\t(rtc_mem_check = 0x40215020);\r\nPROVIDE\t(phy_afterwake_set_rfoption = 0x4021505c);\r\nPROVIDE\t(deep_sleep_set_option = 0x4021507c);\r\nPROVIDE\t(write_data_to_rtc = 0x402150a8);\r\nPROVIDE\t(get_data_from_rtc = 0x402150e0);\r\nPROVIDE\t(register_chipv6_phy = 0x40215170);\r\nPROVIDE\t(set_dpd_bypass = 0x40215580);\r\nPROVIDE\t(set_rf_gain_stage10 = 0x402155a8);\r\nPROVIDE\t(get_vdd33_offset = 0x402155d8);\r\nPROVIDE\t(get_phy_target_power = 0x4021564c);\r\nPROVIDE\t(set_most_pwr_reg = 0x40215700);\r\nPROVIDE\t(phy_set_most_tpw = 0x402157d4);\r\nPROVIDE\t(phy_vdd33_set_tpw = 0x402157f4);\r\nPROVIDE\t(get_adc_rand = 0x4021580c);\r\nPROVIDE\t(phy_get_rand = 0x4021583c);\r\nPROVIDE\t(phy_tx_pwctrl_cali = 0x40215854);\r\nPROVIDE\t(phy_check_data_table = 0x4021587c);\r\nPROVIDE\t(phy_after_init_enrx = 0x402158bc);\r\nPROVIDE\t(phy_set_rx11b_reg = 0x40215920);\r\nPROVIDE\t(phy_set_powerup_option = 0x40215954);\r\nPROVIDE\t(ram_pbus_set_rxgain = 0x40215960);\r\nPROVIDE\t(ram_pbus_debugmode = 0x40215a28);\r\nPROVIDE\t(ram_pbus_xpd_tx_on = 0x40215adc);\r\nPROVIDE\t(set_rf_freq_offset = 0x40215b48);\r\nPROVIDE\t(chip_v6_rxmax_ext_ana = 0x40215bb8);\r\nPROVIDE\t(ram_chip_v6_rx_init = 0x40215d0c);\r\nPROVIDE\t(tsen_meas = 0x40215d3c);\r\nPROVIDE\t(readvdd33 = 0x40215de8);\r\nPROVIDE\t(txpwr_offset = 0x40215fac);\r\nPROVIDE\t(set_txcap_reg = 0x40216068);\r\nPROVIDE\t(ram_ana_inf_gating_en = 0x402160e8);\r\nPROVIDE\t(ram_restart_cal = 0x40216248);\r\nPROVIDE\t(wait_rfpll_cal_end = 0x402162b4);\r\nPROVIDE\t(ram_rfpll_set_freq = 0x4021633c);\r\nPROVIDE\t(ram_set_channel_freq = 0x40216440);\r\nPROVIDE\t(chip_60_set_channel = 0x40216738);\r\nPROVIDE\t(chip_v6_set_chan_offset = 0x402168c8);\r\nPROVIDE\t(chip_v6_set_chan = 0x40216904);\r\nPROVIDE\t(chip_v6_set_chan_wakeup = 0x40216994);\r\nPROVIDE\t(chip_v6_rf_init = 0x40216a08);\r\nPROVIDE\t(low_power_set = 0x40216c2c);\r\nPROVIDE\t(test_tout = 0x40216c7c);\r\nPROVIDE\t(check_data_flag = 0x40216df4);\r\nPROVIDE\t(phy_get_check_flag = 0x40216e14);\r\nPROVIDE\t(phy_get_vdd33 = 0x40216f48);\r\nPROVIDE\t(txbbgain2dcoindex = 0x40216ffc);\r\nPROVIDE\t(dcoindex2txbbgain = 0x4021701c);\r\nPROVIDE\t(init_cal_dcoffset = 0x40217040);\r\nPROVIDE\t(set_rfanagain_dc_reg = 0x40217104);\r\nPROVIDE\t(set_txdc_pbus = 0x402171a0);\r\nPROVIDE\t(get_rf_gain_qdb = 0x4021720c);\r\nPROVIDE\t(correct_rf_ana_gain = 0x40217234);\r\nPROVIDE\t(get_sar_dout = 0x4021733c);\r\nPROVIDE\t(cal_rf_ana_gain = 0x402173d4);\r\nPROVIDE\t(meas_tone_pwr_db = 0x402174ac);\r\nPROVIDE\t(tx_pwr_backoff = 0x4021751c);\r\nPROVIDE\t(get_fcc_1m2m_pwr_offset = 0x40217668);\r\nPROVIDE\t(ram_set_txbb_atten = 0x402176a4);\r\nPROVIDE\t(txiq_get_mis_pwr = 0x40217738);\r\nPROVIDE\t(txiq_cover = 0x402177dc);\r\nPROVIDE\t(ram_rfcal_txiq = 0x402179f4);\r\nPROVIDE\t(rc_cal = 0x40217c60);\r\nPROVIDE\t(get_target_power_offset = 0x40217e20);\r\nPROVIDE\t(get_pwctrl_correct = 0x40217f28);\r\nPROVIDE\t(tx_pwctrl_cal = 0x40217f84);\r\nPROVIDE\t(tx_pwctrl_bg_init = 0x40218314);\r\nPROVIDE\t(tx_pwctrl_background = 0x4021838c);\r\nPROVIDE\t(read_sar_dout = 0x40218468);\r\nPROVIDE\t(ram_get_fm_sar_dout = 0x402184cc);\r\nPROVIDE\t(ram_cal_tos_v60 = 0x40218570);\r\nPROVIDE\t(ram_get_bb_atten = 0x40218750);\r\nPROVIDE\t(ram_rfcal_txcap = 0x40218780);\r\nPROVIDE\t(ram_rfcal_pwrctrl = 0x40218944);\r\nPROVIDE\t(ram_rxiq_get_mis = 0x40218b60);\r\nPROVIDE\t(ram_rxiq_cover_mg_mp = 0x40218d2c);\r\nPROVIDE\t(ram_rfcal_rxiq = 0x40218ed0);\r\nPROVIDE\t(dpd_scale_set = 0x402190dc);\r\nPROVIDE\t(dpd_mem_write = 0x40219124);\r\nPROVIDE\t(pm_usec2rtc = 0x402191a0);\r\nPROVIDE\t(pm_rtc2usec = 0x402191d4);\r\nPROVIDE\t(pm_set_sleep_cycles = 0x402191e0);\r\nPROVIDE\t(pm_sleep_opt = 0x40219208);\r\nPROVIDE\t(pm_wakeup_opt = 0x40219320);\r\nPROVIDE\t(get_chip_version = 0x40219358);\r\nPROVIDE\t(pm_sleep_opt_bb_off = 0x40219398);\r\nPROVIDE\t(pm_sleep_opt_bb_on = 0x402193d8);\r\nPROVIDE\t(pm_set_pll_xtal_wait_time = 0x40219424);\r\nPROVIDE\t(pm_prepare_to_sleep = 0x4021946c);\r\nPROVIDE\t(pm_sdio_nidle = 0x40219490);\r\nPROVIDE\t(chg_lslp_mem_opt_8266 = 0x40219504);\r\nPROVIDE\t(pm_goto_sleep = 0x40219534);\r\nPROVIDE\t(pm_wait4wakeup = 0x40219680);\r\nPROVIDE\t(pm_open_rf = 0x402196bc);\r\nPROVIDE\t(pm_sleep_set_mac = 0x40219700);\r\nPROVIDE\t(pm_set_wakeup_mac = 0x40219784);\r\nPROVIDE\t(pm_check_mac_idle = 0x40219820);\r\nPROVIDE\t(pm_set_sleep_btco = 0x40219878);\r\nPROVIDE\t(pm_set_wakeup_btco = 0x40219918);\r\nPROVIDE\t(pm_set_sleep_mode = 0x40219a30);\r\nPROVIDE\t(pm_unmask_bt = 0x40219b4c);\r\nPROVIDE\t(pm_wakeup_init = 0x40219bb4);\r\nPROVIDE\t(sleep_opt_8266 = 0x40219dc4);\r\nPROVIDE\t(sleep_opt_bb_on_8266 = 0x40219de4);\r\nPROVIDE\t(sleep_reset_analog_rtcreg_8266 = 0x40219e20);\r\nPROVIDE\t(pm_rtc_clock_cali_proc = 0x40219f2c);\r\nPROVIDE\t(pm_get_ck170_period = 0x40219f64);\r\nPROVIDE\t(pm_set_sleep_time = 0x40219f88);\r\nPROVIDE\t(pm_rf_is_closed = 0x4021a2ec);\r\nPROVIDE\t(pm_set_sleep_type_from_upper = 0x4021a318);\r\nPROVIDE\t(pm_get_sleep_type = 0x4021a408);\r\nPROVIDE\t(uart_tx_flush = 0x4021a58c);\r\nPROVIDE\t(pm_suspend = 0x4021a590);\r\nPROVIDE\t(pm_shutdown = 0x4021a7a8);\r\nPROVIDE\t(pm_reset_idle_sleep = 0x4021a870);\r\nPROVIDE\t(pm_idle_sleep = 0x4021a8b0);\r\nPROVIDE\t(pm_open = 0x4021a8bc);\r\nPROVIDE\t(pm_onBcnRx = 0x4021a984);\r\nPROVIDE\t(StopLightSleepSetFunc = 0x4021acec);\r\nPROVIDE\t(LightSleepWakedCbSetFunc = 0x4021acf4);\r\nPROVIDE\t(pm_enable_gpio_wakeup = 0x4021b1f4);\r\nPROVIDE\t(pm_attach = 0x4021b22c);\r\nPROVIDE\t(pm_send_nullfunc = 0x4021b310);\r\nPROVIDE\t(pm_is_waked = 0x4021b498);\r\nPROVIDE\t(pm_is_open = 0x4021b4b0);\r\nPROVIDE\t(pm_scan_lock = 0x4021b4c8);\r\nPROVIDE\t(pm_try_scan_unlock = 0x4021b4f0);\r\nPROVIDE\t(pm_force_scan_unlock = 0x4021b508);\r\nPROVIDE\t(pm_scan_unlocked = 0x4021b584);\r\nPROVIDE\t(pm_allow_tx = 0x4021b598);\r\nPROVIDE\t(pm_assoc_parse = 0x4021b5b4);\r\nPROVIDE\t(pm_set_addr = 0x4021b5cc);\r\nPROVIDE\t(pm_sleep_for = 0x4021b5ec);\r\nPROVIDE\t(pm_post = 0x4021b61c);\r\nPROVIDE\t(pm_get_idle_wait_time = 0x4021b720);\r\nPROVIDE\t(fpm_set_type_from_upper = 0x4021b778);\r\nPROVIDE\t(wifi_fpm_set_sleep_type = 0x4021b778);\r\nPROVIDE\t(fpm_get_slp_type = 0x4021b834);\r\nPROVIDE\t(wifi_fpm_get_sleep_type = 0x4021b834);\r\nPROVIDE\t(fpm_rf_is_closed = 0x4021b83c);\r\nPROVIDE\t(fpm_is_open = 0x4021b850);\r\nPROVIDE\t(fpm_allow_tx = 0x4021b85c);\r\nPROVIDE\t(fpm_close = 0x4021b880);\r\nPROVIDE\t(wifi_fpm_close = 0x4021b880);\r\nPROVIDE\t(fpm_open = 0x4021b8fc);\r\nPROVIDE\t(wifi_fpm_open = 0x4021b8fc);\r\nPROVIDE\t(fpm_attach = 0x4021b964);\r\nPROVIDE\t(fpm_set_wakeup_cb = 0x4021bb48);\r\nPROVIDE\t(wifi_fpm_set_wakeup_cb = 0x4021bb48);\r\nPROVIDE\t(fpm_do_wakeup = 0x4021bcbc);\r\nPROVIDE\t(wifi_fpm_do_wakeup = 0x4021bcbc);\r\nPROVIDE\t(fpm_do_sleep = 0x4021c17c);\r\nPROVIDE\t(wifi_fpm_do_sleep = 0x4021c17c);\r\nPROVIDE\t(PPWdtReset = 0x4021c204);\r\nPROVIDE\t(pp_soft_wdt_init = 0x4021c238);\r\nPROVIDE\t(pp_soft_wdt_feed = 0x4021c258);\r\nPROVIDE\t(system_soft_wdt_feed = 0x4021c258);\r\nPROVIDE\t(pp_soft_wdt_stop = 0x4021c274);\r\nPROVIDE\t(system_soft_wdt_stop = 0x4021c274);\r\nPROVIDE\t(pp_soft_wdt_restart = 0x4021c2a0);\r\nPROVIDE\t(system_soft_wdt_restart = 0x4021c2a0);\r\nPROVIDE\t(RxNodeNum = 0x4021c2d8);\r\nPROVIDE\t(TxNodeNum = 0x4021c2f0);\r\nPROVIDE\t(pp_disable_noise_timer = 0x4021c314);\r\nPROVIDE\t(pp_enable_noise_timer = 0x4021c334);\r\nPROVIDE\t(pp_noise_test = 0x4021c444);\r\nPROVIDE\t(reset_noise_timer = 0x4021c454);\r\nPROVIDE\t(pp_disable_idle_timer = 0x4021c48c);\r\nPROVIDE\t(pp_enable_idle_timer = 0x4021c4b0);\r\nPROVIDE\t(pp_try_enable_idle_timer = 0x4021c4d8);\r\nPROVIDE\t(ppPeocessRxPktHdr = 0x4021c514);\r\nPROVIDE\t(HdlAllBuffedEb = 0x4021c848);\r\nPROVIDE\t(ppTxPkt = 0x4021c8d0);\r\nPROVIDE\t(ppProcessWaitQ = 0x4021ca48);\r\nPROVIDE\t(ppRegisterTxCallback = 0x4021ca58);\r\nPROVIDE\t(ppUnregisterTxCallback = 0x4021ca80);\r\nPROVIDE\t(ppRecycleRxPkt = 0x4021cab4);\r\nPROVIDE\t(ppCheckTxIdle = 0x4021cb14);\r\nPROVIDE\t(pp_tx_idle_timeout = 0x4021cd8c);\r\nPROVIDE\t(DefFreqCalTimerCB = 0x4021cf40);\r\nPROVIDE\t(ppGetTxQFirstAvail_Locked = 0x4021d2b4);\r\nPROVIDE\t(pp_attach = 0x4021d390);\r\nPROVIDE\t(RC_SetBasicRate = 0x4021d9e4);\r\nPROVIDE\t(raw_new = 0x4021da34);\r\nPROVIDE\t(raw_remove = 0x4021da7c);\r\nPROVIDE\t(raw_bind = 0x4021dab0);\r\nPROVIDE\t(raw_connect = 0x4021dabc);\r\nPROVIDE\t(raw_recv = 0x4021dac8);\r\nPROVIDE\t(raw_sendto = 0x4021dad0);\r\nPROVIDE\t(raw_input = 0x4021db74);\r\nPROVIDE\t(raw_send = 0x4021dbf8);\r\nPROVIDE\t(iram_buf_init = 0x4021dc20);\r\nPROVIDE\t(spi_flash_real_size = 0x4021dc7c);\r\nPROVIDE\t(tcp_arg = 0x4021dce0);\r\nPROVIDE\t(tcp_accept = 0x4021dce4);\r\nPROVIDE\t(tcp_recv = 0x4021dce8);\r\nPROVIDE\t(tcp_sent = 0x4021dcf0);\r\nPROVIDE\t(tcp_poll = 0x4021dcf8);\r\nPROVIDE\t(tcp_err = 0x4021dd00);\r\nPROVIDE\t(tcp_bind = 0x4021dd14);\r\nPROVIDE\t(tcp_listen_with_backlog = 0x4021ddb8);\r\nPROVIDE\t(tcp_setprio = 0x4021de7c);\r\nPROVIDE\t(tcp_update_rcv_ann_wnd = 0x4021de84);\r\nPROVIDE\t(tcp_recved = 0x4021decc);\r\nPROVIDE\t(tcp_seg_free = 0x4021df1c);\r\nPROVIDE\t(tcp_segs_free = 0x4021df44);\r\nPROVIDE\t(tcp_pcb_purge = 0x4021df64);\r\nPROVIDE\t(tcp_slowtmr = 0x4021dfc0);\r\nPROVIDE\t(tcp_pcb_remove = 0x4021e23c);\r\nPROVIDE\t(tcp_close = 0x4021e2ac);\r\nPROVIDE\t(tcp_recv_null = 0x4021e2d4);\r\nPROVIDE\t(tcp_fasttmr = 0x4021e30c);\r\nPROVIDE\t(tcp_tmr = 0x4021e3a0);\r\nPROVIDE\t(tcp_shutdown = 0x4021e3c4);\r\nPROVIDE\t(tcp_abandon = 0x4021e424);\r\nPROVIDE\t(tcp_abort = 0x4021e4b4);\r\nPROVIDE\t(tcp_next_iss = 0x4021e4cc);\r\nPROVIDE\t(tcp_alloc = 0x4021e4ec);\r\nPROVIDE\t(tcp_new = 0x4021e60c);\r\nPROVIDE\t(tcp_eff_send_mss = 0x4021e620);\r\nPROVIDE\t(tcp_connect = 0x4021e654);\r\nPROVIDE\t(tcp_receive = 0x4021e784);\r\nPROVIDE\t(tcp_input = 0x4021ed10);\r\nPROVIDE\t(tcp_create_segment = 0x4021f68c);\r\nPROVIDE\t(tcp_write = 0x4021f87c);\r\nPROVIDE\t(tcp_send_empty_ack = 0x4021fb8c);\r\nPROVIDE\t(tcp_rexmit = 0x4021fc1c);\r\nPROVIDE\t(tcp_rexmit_fast = 0x4021fcd4);\r\nPROVIDE\t(tcp_enqueue_flags = 0x4021fd38);\r\nPROVIDE\t(tcp_send_fin = 0x4021fe04);\r\nPROVIDE\t(tcp_rst = 0x4021fe50);\r\nPROVIDE\t(tcp_keepalive = 0x4021ff84);\r\nPROVIDE\t(tcp_zero_window_probe = 0x40220004);\r\nPROVIDE\t(tcp_output = 0x40220114);\r\nPROVIDE\t(tcp_rexmit_rto = 0x4022053c);\r\nPROVIDE\t(sys_timeout = 0x402205c4);\r\nPROVIDE\t(sys_timeouts_init = 0x40220668);\r\nPROVIDE\t(tcpip_tcp_timer = 0x402206d8);\r\nPROVIDE\t(arp_timer = 0x4022070c);\r\nPROVIDE\t(sys_untimeout = 0x40220728);\r\nPROVIDE\t(sys_check_timeouts = 0x4022077c);\r\nPROVIDE\t(sys_restart_timeouts = 0x402207f8);\r\nPROVIDE\t(tcp_timer_needed = 0x40220804);\r\nPROVIDE\t(phytype2mode = 0x40220834);\r\nPROVIDE\t(rc_set_rate_limit_id = 0x40220850);\r\nPROVIDE\t(rcUpdatePhyMode = 0x4022096c);\r\nPROVIDE\t(rcAttach = 0x40220b38);\r\nPROVIDE\t(rcGetTrc = 0x40220b84);\r\nPROVIDE\t(trc_onDisconnect = 0x40220b8c);\r\nPROVIDE\t(trc_onScanStart = 0x40220b90);\r\nPROVIDE\t(trc_onScanDone = 0x40220ba4);\r\nPROVIDE\t(rc_enable_trc = 0x40220bc0);\r\nPROVIDE\t(rc_get_mask = 0x40220c98);\r\nPROVIDE\t(rc_disable_trc = 0x40220cac);\r\nPROVIDE\t(rc_disable_trc_by_interface = 0x40220d00);\r\nPROVIDE\t(rc_get_sta_trc = 0x40220d1c);\r\nPROVIDE\t(rc_get_trc = 0x40220d60);\r\nPROVIDE\t(rc_get_trc_by_index = 0x40220dd0);\r\nPROVIDE\t(rc_only_sta_trc = 0x40220df0);\r\nPROVIDE\t(udp_new = 0x40220e20);\r\nPROVIDE\t(udp_remove = 0x40220e54);\r\nPROVIDE\t(udp_bind = 0x40220e8c);\r\nPROVIDE\t(udp_connect = 0x40220f30);\r\nPROVIDE\t(udp_disconnect = 0x40220f98);\r\nPROVIDE\t(udp_recv = 0x40220fac);\r\nPROVIDE\t(udp_sendto_if = 0x40220fb4);\r\nPROVIDE\t(udp_sendto = 0x402210fc);\r\nPROVIDE\t(udp_send = 0x40221148);\r\nPROVIDE\t(udp_input = 0x40221160);\r\nPROVIDE\t(system_set_os_print = 0x40221344);\r\nPROVIDE\t(system_get_os_print = 0x40221354);\r\nPROVIDE\t(system_pp_recycle_rx_pkt = 0x4022151c);\r\nPROVIDE\t(system_adc_read = 0x40221530);\r\nPROVIDE\t(system_get_vdd33 = 0x40221548);\r\nPROVIDE\t(system_restart_hook = 0x40221560);\r\nPROVIDE\t(system_restart_local = 0x40221574);\r\nPROVIDE\t(system_restart = 0x4022165c);\r\nPROVIDE\t(system_restore = 0x402216b4);\r\nPROVIDE\t(system_get_flash_size_map = 0x4022171c);\r\nPROVIDE\t(system_get_boot_version = 0x4022173c);\r\nPROVIDE\t(system_get_test_result = 0x40221774);\r\nPROVIDE\t(system_get_userbin_addr = 0x40221798);\r\nPROVIDE\t(system_get_boot_mode = 0x40221830);\r\nPROVIDE\t(system_restart_enhance = 0x40221860);\r\nPROVIDE\t(system_upgrade_userbin_set = 0x40221990);\r\nPROVIDE\t(system_upgrade_userbin_check = 0x402219dc);\r\nPROVIDE\t(system_upgrade_flag_set = 0x40221a1c);\r\nPROVIDE\t(system_upgrade_flag_check = 0x40221a30);\r\nPROVIDE\t(system_upgrade_reboot = 0x40221a54);\r\nPROVIDE\t(system_deep_sleep_instant = 0x40221b70);\r\nPROVIDE\t(system_deep_sleep = 0x40221d10);\r\nPROVIDE\t(system_deep_sleep_set_option = 0x40221d70);\r\nPROVIDE\t(system_phy_temperature_alert = 0x40221d8c);\r\nPROVIDE\t(system_phy_set_max_tpw = 0x40221da0);\r\nPROVIDE\t(system_phy_set_tpw_via_vdd33 = 0x40221db4);\r\nPROVIDE\t(system_phy_set_rfoption = 0x40221dc8);\r\nPROVIDE\t(system_phy_set_powerup_option = 0x40221ddc);\r\nPROVIDE\t(system_update_cpu_freq = 0x40221df0);\r\nPROVIDE\t(system_get_cpu_freq = 0x40221e4c);\r\nPROVIDE\t(system_overclock = 0x40221e64);\r\nPROVIDE\t(system_restoreclock = 0x40221e90);\r\nPROVIDE\t(system_timer_reinit = 0x40221ec0);\r\nPROVIDE\t(system_relative_time = 0x40221ed8);\r\nPROVIDE\t(system_station_got_ip_set = 0x40221ef4);\r\nPROVIDE\t(system_print_meminfo = 0x40222020);\r\nPROVIDE\t(system_get_free_heap_size = 0x40222084);\r\nPROVIDE\t(system_get_chip_id = 0x40222098);\r\nPROVIDE\t(system_rtc_clock_cali_proc = 0x402220bc);\r\nPROVIDE\t(system_get_rtc_time = 0x402220d0);\r\nPROVIDE\t(system_mktime = 0x402220e0);\r\nPROVIDE\t(system_init_done_cb = 0x402221b0);\r\nPROVIDE\t(system_get_rst_info = 0x402221b8);\r\nPROVIDE\t(system_get_data_of_array_8 = 0x402221c0);\r\nPROVIDE\t(system_get_data_of_array_16 = 0x402221e4);\r\nPROVIDE\t(system_get_string_from_flash = 0x4022220c);\r\nPROVIDE\t(wifi_softap_dhcps_start = 0x40222278);\r\nPROVIDE\t(wifi_softap_dhcps_stop = 0x402222c0);\r\nPROVIDE\t(wifi_softap_dhcps_status = 0x40222300);\r\nPROVIDE\t(wifi_station_dhcpc_start = 0x40222308);\r\nPROVIDE\t(wifi_station_dhcpc_stop = 0x40222360);\r\nPROVIDE\t(wifi_station_dhcpc_event = 0x402223a0);\r\nPROVIDE\t(wifi_station_dhcpc_set_maxtry = 0x40222414);\r\nPROVIDE\t(wifi_station_dhcpc_status = 0x40222424);\r\nPROVIDE\t(wifi_get_opmode = 0x4022249c);\r\nPROVIDE\t(wifi_get_opmode_default = 0x402224b0);\r\nPROVIDE\t(wifi_get_broadcast_if = 0x40222528);\r\nPROVIDE\t(wifi_set_broadcast_if = 0x40222564);\r\nPROVIDE\t(wifi_set_opmode = 0x402226c0);\r\nPROVIDE\t(wifi_set_opmode_current = 0x402226d4);\r\nPROVIDE\t(system_get_checksum = 0x402226e8);\r\nPROVIDE\t(wifi_param_save_protect_with_check = 0x4022272c);\r\nPROVIDE\t(system_param_save_with_protect = 0x402227e4);\r\nPROVIDE\t(system_save_sys_param = 0x4022288c);\r\nPROVIDE\t(system_param_load = 0x402228b8);\r\nPROVIDE\t(wifi_station_get_config = 0x402229f0);\r\nPROVIDE\t(wifi_station_get_config_default = 0x40222a04);\r\nPROVIDE\t(wifi_station_get_ap_info = 0x40222a24);\r\nPROVIDE\t(wifi_station_ap_number_set = 0x40222adc);\r\nPROVIDE\t(wifi_station_set_config = 0x40222e3c);\r\nPROVIDE\t(wifi_station_set_config_current = 0x40222e54);\r\nPROVIDE\t(wifi_station_restore_config = 0x40222e6c);\r\nPROVIDE\t(wifi_station_get_current_ap_id = 0x40222e84);\r\nPROVIDE\t(wifi_station_ap_check = 0x40222e98);\r\nPROVIDE\t(wifi_station_ap_change = 0x40222ed8);\r\nPROVIDE\t(wifi_station_scan = 0x40223004);\r\nPROVIDE\t(wifi_station_get_auto_connect = 0x40223050);\r\nPROVIDE\t(wifi_station_set_auto_connect = 0x40223064);\r\nPROVIDE\t(wifi_station_save_pmk2cache = 0x402230b4);\r\nPROVIDE\t(wifi_station_connect = 0x40223164);\r\nPROVIDE\t(wifi_station_disconnect = 0x402231f8);\r\nPROVIDE\t(wifi_station_get_connect_status = 0x402232b8);\r\nPROVIDE\t(wifi_station_set_reconnect_policy = 0x402232e8);\r\nPROVIDE\t(wifi_station_get_reconnect_policy = 0x40223300);\r\nPROVIDE\t(wifi_station_get_rssi = 0x40223308);\r\nPROVIDE\t(wifi_station_set_default_hostname = 0x40223354);\r\nPROVIDE\t(wifi_station_get_hostname = 0x402233bc);\r\nPROVIDE\t(wifi_station_set_hostname = 0x402233e8);\r\nPROVIDE\t(wifi_softap_cacl_mac = 0x40223484);\r\nPROVIDE\t(wifi_softap_set_default_ssid = 0x402234e8);\r\nPROVIDE\t(wifi_softap_get_config = 0x402236c8);\r\nPROVIDE\t(wifi_softap_get_config_default = 0x402236dc);\r\nPROVIDE\t(wifi_softap_set_config = 0x40223a24);\r\nPROVIDE\t(wifi_softap_set_config_current = 0x40223a38);\r\nPROVIDE\t(wifi_softap_set_station_info = 0x40223a4c);\r\nPROVIDE\t(wifi_softap_get_station_info = 0x40223ab8);\r\nPROVIDE\t(wifi_softap_free_station_info = 0x40223b68);\r\nPROVIDE\t(wifi_softap_get_station_num = 0x40223bb0);\r\nPROVIDE\t(wifi_softap_deauth = 0x40223c00);\r\nPROVIDE\t(wifi_softap_get_beacon_only_mode = 0x40223cb0);\r\nPROVIDE\t(wifi_softap_set_beacon_only_mode = 0x40223cc4);\r\nPROVIDE\t(wifi_register_user_ie_manufacturer_recv_cb = 0x40223d28);\r\nPROVIDE\t(wifi_unregister_user_ie_manufacturer_recv_cb = 0x40223d3c);\r\nPROVIDE\t(wifi_set_user_ie = 0x40223d6c);\r\nPROVIDE\t(wifi_get_user_ie = 0x40223e7c);\r\nPROVIDE\t(wifi_get_phy_mode = 0x40223eb0);\r\nPROVIDE\t(wifi_set_phy_mode = 0x40223eb8);\r\nPROVIDE\t(wifi_set_sleep_type = 0x40223f80);\r\nPROVIDE\t(wifi_get_sleep_type = 0x40223f9c);\r\nPROVIDE\t(wifi_get_channel = 0x40223fb0);\r\nPROVIDE\t(wifi_set_channel = 0x40223fc8);\r\nPROVIDE\t(wifi_promiscuous_set_mac = 0x40224008);\r\nPROVIDE\t(wifi_promiscuous_enable = 0x40224064);\r\nPROVIDE\t(wifi_set_promiscuous_rx_cb = 0x40224148);\r\nPROVIDE\t(wifi_get_ip_info = 0x40224154);\r\nPROVIDE\t(wifi_set_ip_info = 0x402241d4);\r\nPROVIDE\t(wifi_get_macaddr = 0x40224248);\r\nPROVIDE\t(wifi_set_macaddr = 0x402242a8);\r\nPROVIDE\t(wifi_enable_6m_rate = 0x402243c4);\r\nPROVIDE\t(wifi_get_user_fixed_rate = 0x402243cc);\r\nPROVIDE\t(wifi_set_user_fixed_rate = 0x402243ec);\r\nPROVIDE\t(wifi_set_user_sup_rate = 0x4022440c);\r\nPROVIDE\t(wifi_set_user_rate_limit = 0x40224448);\r\nPROVIDE\t(wifi_get_user_limit_rate_mask = 0x4022446c);\r\nPROVIDE\t(wifi_set_user_limit_rate_mask = 0x40224474);\r\nPROVIDE\t(wifi_register_send_pkt_freedom_cb = 0x4022448c);\r\nPROVIDE\t(wifi_unregister_send_pkt_freedom_cb = 0x402244a0);\r\nPROVIDE\t(wifi_send_pkt_freedom = 0x402244ac);\r\nPROVIDE\t(wifi_rfid_locp_recv_open = 0x402244f8);\r\nPROVIDE\t(wifi_rfid_locp_recv_close = 0x4022450c);\r\nPROVIDE\t(wifi_register_rfid_locp_recv_cb = 0x40224520);\r\nPROVIDE\t(wifi_unregister_rfid_locp_recv_cb = 0x40224534);\r\nPROVIDE\t(wifi_status_led_install = 0x4022454c);\r\nPROVIDE\t(wifi_status_led_uninstall = 0x40224580);\r\nPROVIDE\t(wifi_set_status_led_output_level = 0x402245a4);\r\nPROVIDE\t(wifi_set_event_handler_cb = 0x402245f8);\r\nPROVIDE\t(system_os_task = 0x40224640);\r\nPROVIDE\t(system_uart_swap = 0x4022467c);\r\nPROVIDE\t(system_uart_de_swap = 0x402246e0);\r\nPROVIDE\t(system_get_sdk_version = 0x40224718);\r\nPROVIDE\t(wDev_Option_Init = 0x4022472c);\r\nPROVIDE\t(wDev_Enable_Beacon_Tsf = 0x40224820);\r\nPROVIDE\t(wDev_Disable_Beacon_Tsf = 0x4022483c);\r\nPROVIDE\t(wDev_Set_Beacon_Int = 0x40224858);\r\nPROVIDE\t(wDev_Reset_TBTT = 0x40224860);\r\nPROVIDE\t(wDev_Get_Next_TBTT = 0x40224890);\r\nPROVIDE\t(wDev_Initialize = 0x40224b0c);\r\nPROVIDE\t(wDevForceAck6M = 0x40224b7c);\r\nPROVIDE\t(wDev_SetMacAddress = 0x40224b98);\r\nPROVIDE\t(wDev_SetRxPolicy = 0x40224c34);\r\nPROVIDE\t(wDev_SetBssid = 0x40224c88);\r\nPROVIDE\t(wDev_ClearBssid = 0x40224d60);\r\nPROVIDE\t(wDev_Insert_KeyEntry = 0x40224d98);\r\nPROVIDE\t(wDev_remove_KeyEntry = 0x40224e8c);\r\nPROVIDE\t(wDev_remove_KeyEntry_all_cnx = 0x40224ec8);\r\nPROVIDE\t(wDev_Crypto_Conf = 0x40224f18);\r\nPROVIDE\t(wDev_Crypto_Disable = 0x40224fb4);\r\nPROVIDE\t(wDevEnableRx = 0x40224fec);\r\nPROVIDE\t(wdev_go_sniffer = 0x40225014);\r\nPROVIDE\t(wdev_set_sniffer_addr = 0x402250f0);\r\nPROVIDE\t(wdev_exit_sniffer = 0x40225148);\r\nPROVIDE\t(wdt_init = 0x40225218);\r\nPROVIDE\t(os_print_reset_error = 0x402252a0);\r\nPROVIDE\t(chm_init = 0x40225344);\r\nPROVIDE\t(chm_acquire_lock = 0x402253a8);\r\nPROVIDE\t(chm_release_lock = 0x402253ec);\r\nPROVIDE\t(chm_start_op = 0x40225400);\r\nPROVIDE\t(chm_end_op = 0x402254a4);\r\nPROVIDE\t(chm_cancel_op = 0x402254ec);\r\nPROVIDE\t(chm_return_home_channel = 0x40225520);\r\nPROVIDE\t(chm_set_current_channel = 0x40225550);\r\nPROVIDE\t(chm_freq2index = 0x40225580);\r\nPROVIDE\t(chm_check_same_channel = 0x402255a8);\r\nPROVIDE\t(cnx_attach = 0x402255e4);\r\nPROVIDE\t(cnx_sta_connect_led_timer_cb = 0x40225624);\r\nPROVIDE\t(cnx_sta_connect_cmd = 0x40225678);\r\nPROVIDE\t(cnx_sta_scan_cmd = 0x40225734);\r\nPROVIDE\t(cnx_connect_timeout = 0x40225990);\r\nPROVIDE\t(cnx_auth_timeout = 0x40225a0c);\r\nPROVIDE\t(cnx_assoc_timeout = 0x40225a30);\r\nPROVIDE\t(cnx_handshake_timeout = 0x40225a54);\r\nPROVIDE\t(cnx_start_handoff_cb = 0x40225a94);\r\nPROVIDE\t(cnx_bss_alloc = 0x40225ef4);\r\nPROVIDE\t(cnx_rc_search = 0x40225f94);\r\nPROVIDE\t(cnx_add_rc = 0x40226014);\r\nPROVIDE\t(cnx_remove_all_rc = 0x40226080);\r\nPROVIDE\t(cnx_remove_rc = 0x402260cc);\r\nPROVIDE\t(cnx_rc_update_rssi = 0x4022619c);\r\nPROVIDE\t(cnx_rc_update_state_metric = 0x40226224);\r\nPROVIDE\t(cnx_rc_update_age = 0x40226290);\r\nPROVIDE\t(cnx_update_bss = 0x402262b4);\r\nPROVIDE\t(cnx_update_bss_more = 0x402262e8);\r\nPROVIDE\t(cnx_sta_leave = 0x402264c4);\r\nPROVIDE\t(cnx_sta_associated = 0x40226758);\r\nPROVIDE\t(cnx_node_alloc = 0x40226860);\r\nPROVIDE\t(cnx_node_remove = 0x402268d4);\r\nPROVIDE\t(cnx_node_search = 0x40226960);\r\nPROVIDE\t(cnx_node_leave = 0x402269dc);\r\nPROVIDE\t(wifi_softap_staconnected_event_policy = 0x40226adc);\r\nPROVIDE\t(wifi_softap_toomany_deny = 0x40226b04);\r\nPROVIDE\t(cnx_node_join = 0x40226b40);\r\nPROVIDE\t(wpa_sm_rx_eapol = 0x40227d28);\r\nPROVIDE\t(wpa_register = 0x40227ea0);\r\nPROVIDE\t(wpa_set_profile = 0x40227ecc);\r\nPROVIDE\t(wpa_set_pmk = 0x40227ee4);\r\nPROVIDE\t(wpa_set_bss = 0x40227f10);\r\nPROVIDE\t(pp_michael_mic_failure = 0x40228114);\r\nPROVIDE\t(eapol_txcb = 0x402281b8);\r\nPROVIDE\t(wpa_sm_set_state = 0x40228244);\r\nPROVIDE\t(wpa_auth_for_each_sta = 0x402283b8);\r\nPROVIDE\t(wpa_init = 0x40228538);\r\nPROVIDE\t(wpa_auth_sta_init = 0x402285c8);\r\nPROVIDE\t(wpa_auth_sta_associated = 0x40228610);\r\nPROVIDE\t(wpa_auth_sta_no_wpa = 0x4022867c);\r\nPROVIDE\t(wpa_auth_sta_deinit = 0x402286d8);\r\nPROVIDE\t(wpa_receive = 0x402287a8);\r\nPROVIDE\t(__wpa_send_eapol = 0x40228c08);\r\nPROVIDE\t(wpa_remove_ptk = 0x4022912c);\r\nPROVIDE\t(wpa_auth_sm_event = 0x40229178);\r\nPROVIDE\t(wpa_write_rsn_ie = 0x40229fb0);\r\nPROVIDE\t(wpa_auth_gen_wpa_ie = 0x4022a0bc);\r\nPROVIDE\t(wpa_add_kde = 0x4022a14c);\r\nPROVIDE\t(wpa_validate_wpa_ie = 0x4022a1b8);\r\nPROVIDE\t(wpa_parse_kde_ies = 0x4022a3c4);\r\nPROVIDE\t(wpa_auth_uses_mfp = 0x4022a460);\r\nPROVIDE\t(wpa_parse_wpa_ie_rsn = 0x4022a5b8);\r\nPROVIDE\t(wpa_parse_wpa_ie_wpa = 0x4022a74c);\r\nPROVIDE\t(wpa_eapol_key_mic = 0x4022a8dc);\r\nPROVIDE\t(wpa_compare_rsn_ie = 0x4022a91c);\r\nPROVIDE\t(wpa_pmk_to_ptk = 0x4022a944);\r\nPROVIDE\t(rsn_pmkid = 0x4022aa34);\r\nPROVIDE\t(wpa_cipher_key_len = 0x4022aa90);\r\nPROVIDE\t(wpa_cipher_to_alg = 0x4022aab4);\r\nPROVIDE\t(wpa_cipher_to_suite = 0x4022aadc);\r\nPROVIDE\t(rsn_cipher_put_suites = 0x4022ab30);\r\nPROVIDE\t(wpa_cipher_put_suites = 0x4022ab90);\r\nPROVIDE\t(wpa_parse_wpa_ie = 0x4022abdc);\r\nPROVIDE\t(wpa_supplicant_parse_ies = 0x4022acd0);\r\nPROVIDE\t(wpa_gen_wpa_ie = 0x4022aed0);\r\nPROVIDE\t(ppInstallKey = 0x4022af08);\r\nPROVIDE\t(wpa_config_profile = 0x4022b098);\r\nPROVIDE\t(wpa_config_bss = 0x4022b0cc);\r\nPROVIDE\t(wpa_config_assoc_ie = 0x4022b0f8);\r\nPROVIDE\t(dhcp_bind_check = 0x4022b10c);\r\nPROVIDE\t(eagle_auth_done = 0x4022b140);\r\nPROVIDE\t(wpa_neg_complete = 0x4022b2bc);\r\nPROVIDE\t(wpa_attach = 0x4022b2e4);\r\nPROVIDE\t(wpa_sm_alloc_eapol = 0x4022b38c);\r\nPROVIDE\t(wpa_sm_deauthenticate = 0x4022b3cc);\r\nPROVIDE\t(wpa_sm_mlme_setprotection = 0x4022b3e8);\r\nPROVIDE\t(wpa_sm_get_beacon_ie = 0x4022b3ec);\r\nPROVIDE\t(wpa_sm_disassociate = 0x4022b3f0);\r\nPROVIDE\t(aes_wrap = 0x4022b3f4);\r\nPROVIDE\t(hostapd_config_defaults_bss = 0x4022b4d8);\r\nPROVIDE\t(hostapd_config_defaults = 0x4022b524);\r\nPROVIDE\t(hostapd_mac_comp = 0x4022b5a8);\r\nPROVIDE\t(hostapd_mac_comp_empty = 0x4022b5bc);\r\nPROVIDE\t(hostapd_setup_wpa_psk = 0x4022b628);\r\nPROVIDE\t(hostapd_wep_key_cmp = 0x4022b658);\r\nPROVIDE\t(hostapd_maclist_found = 0x4022b6a8);\r\nPROVIDE\t(hostapd_rate_found = 0x4022b710);\r\nPROVIDE\t(hostapd_get_psk = 0x4022b72c);\r\nPROVIDE\t(inc_byte_array = 0x4022b780);\r\nPROVIDE\t(hex2byte = 0x4022b7d4);\r\nPROVIDE\t(hexstr2bin = 0x4022b808);\r\nPROVIDE\t(wpa_get_ntp_timestamp = 0x4022b854);\r\nPROVIDE\t(wpa_config_parse_string = 0x4022b8ec);\r\nPROVIDE\t(dup_binstr = 0x4022b9f0);\r\nPROVIDE\t(dhcp_set_state = 0x4022ba38);\r\nPROVIDE\t(dhcp_check = 0x4022ba50);\r\nPROVIDE\t(dhcp_option = 0x4022ba8c);\r\nPROVIDE\t(dhcp_option_byte = 0x4022baac);\r\nPROVIDE\t(dhcp_option_short = 0x4022bac0);\r\nPROVIDE\t(dhcp_option_long = 0x4022bae8);\r\nPROVIDE\t(dhcp_create_msg = 0x4022bb40);\r\nPROVIDE\t(dhcp_delete_msg = 0x4022bcdc);\r\nPROVIDE\t(dhcp_bind = 0x4022bd04);\r\nPROVIDE\t(dhcp_option_trailer = 0x4022bdfc);\r\nPROVIDE\t(dhcp_reboot = 0x4022be34);\r\nPROVIDE\t(dhcp_rebind = 0x4022bf04);\r\nPROVIDE\t(dhcp_select = 0x4022bfe0);\r\nPROVIDE\t(dhcp_discover = 0x4022c180);\r\nPROVIDE\t(dhcp_recv = 0x4022c2cc);\r\nPROVIDE\t(dhcp_set_struct = 0x4022c8b4);\r\nPROVIDE\t(dhcp_cleanup = 0x4022c8dc);\r\nPROVIDE\t(dhcp_inform = 0x4022c900);\r\nPROVIDE\t(dhcp_network_changed = 0x4022c9b0);\r\nPROVIDE\t(dhcp_arp_reply = 0x4022c9f8);\r\nPROVIDE\t(dhcp_renew = 0x4022caac);\r\nPROVIDE\t(dhcp_coarse_tmr = 0x4022cb88);\r\nPROVIDE\t(dhcp_release = 0x4022cc1c);\r\nPROVIDE\t(dhcp_fine_tmr = 0x4022cce4);\r\nPROVIDE\t(dhcp_stop = 0x4022cdd8);\r\nPROVIDE\t(dhcp_start = 0x4022ce14);\r\nPROVIDE\t(create_msg = 0x4022cedc);\r\nPROVIDE\t(add_offer_options = 0x4022cf94);\r\nPROVIDE\t(node_insert_to_list = 0x4022d0d4);\r\nPROVIDE\t(node_remove_from_list = 0x4022d10c);\r\nPROVIDE\t(handle_dhcp = 0x4022d150);\r\nPROVIDE\t(dhcps_start = 0x4022d5bc);\r\nPROVIDE\t(dhcps_stop = 0x4022d69c);\r\nPROVIDE\t(wifi_softap_set_dhcps_lease = 0x4022d700);\r\nPROVIDE\t(wifi_softap_get_dhcps_lease = 0x4022d724);\r\nPROVIDE\t(dhcps_coarse_tmr = 0x4022d73c);\r\nPROVIDE\t(wifi_softap_set_dhcps_offer_option = 0x4022d7dc);\r\nPROVIDE\t(wifi_softap_set_dhcps_lease_time = 0x4022d81c);\r\nPROVIDE\t(wifi_softap_reset_dhcps_lease_time = 0x4022d82c);\r\nPROVIDE\t(wifi_softap_get_dhcps_lease_time = 0x4022d838);\r\nPROVIDE\t(dns_parse_name = 0x4022d840);\r\nPROVIDE\t(dns_recv = 0x4022d874);\r\nPROVIDE\t(dns_send = 0x4022dabc);\r\nPROVIDE\t(dns_check_entry = 0x4022dbcc);\r\nPROVIDE\t(dns_setserver = 0x4022dca8);\r\nPROVIDE\t(dns_init = 0x4022dcd0);\r\nPROVIDE\t(dns_getserver = 0x4022dd14);\r\nPROVIDE\t(dns_tmr = 0x4022dd2c);\r\nPROVIDE\t(dns_gethostbyname = 0x4022dd5c);\r\nPROVIDE\t(esf_buf_alloc = 0x4022de7c);\r\nPROVIDE\t(esf_buf_recycle = 0x4022e064);\r\nPROVIDE\t(esf_buf_setup = 0x4022e1a4);\r\nPROVIDE\t(icmp_input = 0x4022e264);\r\nPROVIDE\t(icmp_dest_unreach = 0x4022e3e8);\r\nPROVIDE\t(ieee80211_send_action_register = 0x4022e4a0);\r\nPROVIDE\t(ieee80211_send_action_unregister = 0x4022e4d4);\r\nPROVIDE\t(ieee80211_send_action = 0x4022e4e8);\r\nPROVIDE\t(ieee80211_recv_action_register = 0x4022e554);\r\nPROVIDE\t(ieee80211_recv_action_unregister = 0x4022e588);\r\nPROVIDE\t(ieee80211_recv_action = 0x4022e59c);\r\nPROVIDE\t(igmp_send = 0x4022e964);\r\nPROVIDE\t(igmp_delaying_member = 0x4022ea50);\r\nPROVIDE\t(igmp_init = 0x4022eaf4);\r\nPROVIDE\t(igmp_stop = 0x4022eb08);\r\nPROVIDE\t(igmp_report_groups = 0x4022eb6c);\r\nPROVIDE\t(igmp_lookfor_group = 0x4022eb9c);\r\nPROVIDE\t(igmp_start = 0x4022ebb8);\r\nPROVIDE\t(igmp_input = 0x4022ec0c);\r\nPROVIDE\t(igmp_joingroup = 0x4022ed28);\r\nPROVIDE\t(igmp_leavegroup = 0x4022edf0);\r\nPROVIDE\t(igmp_tmr = 0x4022eec4);\r\nPROVIDE\t(os_get_time = 0x4022ef00);\r\nPROVIDE\t(r_rand = 0x4022ef04);\r\nPROVIDE\t(os_random = 0x4022ef14);\r\nPROVIDE\t(os_get_random = 0x4022ef24);\r\nPROVIDE\t(ets_strrchr = 0x4022ef6c);\r\nPROVIDE\t(rijndaelEncrypt = 0x4022ef88);\r\nPROVIDE\t(aes_encrypt_init = 0x4022f3a4);\r\nPROVIDE\t(aes_encrypt = 0x4022f3f8);\r\nPROVIDE\t(aes_encrypt_deinit = 0x4022f410);\r\nPROVIDE\t(rijndaelKeySetupEnc = 0x4022f440);\r\nPROVIDE\t(init_done_cb = 0x4022f75c);\r\nPROVIDE\t(user_init = 0x4022f818);\r\nPROVIDE\t(write_power_meter_cfg = 0x4022f8d4);\r\nPROVIDE\t(power_meter_clear_all_data = 0x4022f8f8);\r\nPROVIDE\t(fram_init = 0x4022f9a4);\r\nPROVIDE\t(NextPtrCurrent = 0x4022f9c0);\r\nPROVIDE\t(FRAM_Store_Init = 0x4022fa80);\r\nPROVIDE\t(power_meter_init = 0x4022fdc0);\r\nPROVIDE\t(GPIO_Task_NewData = 0x4022ff68);\r\nPROVIDE\t(update_cnts = 0x40230068);\r\nPROVIDE\t(user_idle = 0x40230468);\r\nPROVIDE\t(FRAM_speed_test = 0x40230508);\r\nPROVIDE\t(i2c_Init = 0x402306b8);\r\nPROVIDE\t(i2c_eeprom_read_block = 0x40230740);\r\nPROVIDE\t(i2c_eeprom_write_block = 0x402307c8);\r\nPROVIDE\t(Set_default_wificfg = 0x40230860);\r\nPROVIDE\t(wifi_start_scan = 0x402309e8);\r\nPROVIDE\t(WiFi_go_to_sleep = 0x40230a3c);\r\nPROVIDE\t(WiFi_up_from_sleep = 0x40230a74);\r\nPROVIDE\t(Set_WiFi = 0x40230ab4);\r\nPROVIDE\t(Cmp_WiFi_chg = 0x40230db0);\r\nPROVIDE\t(print_wifi_config = 0x40231034);\r\nPROVIDE\t(New_WiFi_config = 0x402311a8);\r\nPROVIDE\t(wifi_scan_cb = 0x40231218);\r\nPROVIDE\t(wifi_read_fcfg = 0x40231318);\r\nPROVIDE\t(Setup_WiFi = 0x40231360);\r\nPROVIDE\t(Read_WiFi_config = 0x402313a8);\r\nPROVIDE\t(wifi_save_fcfg = 0x4023155c);\r\nPROVIDE\t(flash_read_cfg = 0x40231868);\r\nPROVIDE\t(flash_save_cfg = 0x402318e8);\r\nPROVIDE\t(sys_write_cfg = 0x40231910);\r\nPROVIDE\t(sys_read_cfg = 0x40231928);\r\nPROVIDE\t(current_cfg_length = 0x40231984);\r\nPROVIDE\t(read_user_const = 0x402319dc);\r\nPROVIDE\t(write_user_const = 0x40231a14);\r\nPROVIDE\t(station_connect_timer = 0x40231a4c);\r\nPROVIDE\t(station_reconnect_off = 0x40231aa4);\r\nPROVIDE\t(close_all_service = 0x40231ad0);\r\nPROVIDE\t(open_all_service = 0x40231b14);\r\nPROVIDE\t(print_event_reason = 0x40231ba8);\r\nPROVIDE\t(add_next_probe_requests = 0x40231bf0);\r\nPROVIDE\t(wifi_handle_event_cb = 0x40231cd8);\r\nPROVIDE\t(ntp_time_update = 0x40231f38);\r\nPROVIDE\t(sntp_retry = 0x40231f4c);\r\nPROVIDE\t(sntp_send_request = 0x40231f84);\r\nPROVIDE\t(sntp_request = 0x40231ff0);\r\nPROVIDE\t(sntp_dns_found = 0x4023204c);\r\nPROVIDE\t(sntp_inits = 0x40232078);\r\nPROVIDE\t(sntp_close = 0x40232108);\r\nPROVIDE\t(get_sntp_time = 0x40232150);\r\nPROVIDE\t(sntp_recv = 0x40232184);\r\nPROVIDE\t(web_fini = 0x402322d4);\r\nPROVIDE\t(_localtime = 0x40232504);\r\nPROVIDE\t(WEBFSClose = 0x40232644);\r\nPROVIDE\t(WEBFS_max_size = 0x4023266c);\r\nPROVIDE\t(WEBFS_curent_size = 0x402326a4);\r\nPROVIDE\t(WEBFS_base_addr = 0x402326d0);\r\nPROVIDE\t(WEBFSGetArray = 0x402326f8);\r\nPROVIDE\t(WEBFSInit = 0x40232798);\r\nPROVIDE\t(GetFATRecord = 0x40232824);\r\nPROVIDE\t(WEBFSOpen = 0x4023289c);\r\nPROVIDE\t(WEBFSGetFlags = 0x402329ac);\r\nPROVIDE\t(WEBFSGetSize = 0x402329e0);\r\nPROVIDE\t(WEBFSGetBytesRem = 0x40232a10);\r\nPROVIDE\t(WEBFSGetStartAddr = 0x40232a2c);\r\nPROVIDE\t(WEBFSGetEndAddr = 0x40232a5c);\r\nPROVIDE\t(WEBFSSeek = 0x40232a90);\r\nPROVIDE\t(WEBFSGetFilename = 0x40232b3c);\r\nPROVIDE\t(WEBFSGetPosition = 0x40232b94);\r\nPROVIDE\t(set_cpu_clk = 0x40232bb8);\r\nPROVIDE\t(get_addr_gpiox_mux = 0x40232c0c);\r\nPROVIDE\t(set_gpiox_mux_pull = 0x40232c38);\r\nPROVIDE\t(set_gpiox_mux_func = 0x40232c64);\r\nPROVIDE\t(set_gpiox_mux_func_ioport = 0x40232c9c);\r\nPROVIDE\t(set_gpiox_mux_func_default = 0x40232cc8);\r\nPROVIDE\t(get_gpiox_mux = 0x40232cf4);\r\nPROVIDE\t(get_gpiox_mux_func = 0x40232d0c);\r\nPROVIDE\t(test_pin_clr_wifi_config = 0x40232d3c);\r\nPROVIDE\t(get_mac_time = 0x40232e14);\r\nPROVIDE\t(web_int_disconnect = 0x40232e2c);\r\nPROVIDE\t(Close_web_conn = 0x40232e80);\r\nPROVIDE\t(webserver_disconnect = 0x40232ed8);\r\nPROVIDE\t(web_inc_fp = 0x40232f18);\r\nPROVIDE\t(find_boundary = 0x40232f84);\r\nPROVIDE\t(webserver_init = 0x4023302c);\r\nPROVIDE\t(webserver_close = 0x402330d8);\r\nPROVIDE\t(webserver_reinit = 0x40233104);\r\nPROVIDE\t(web_inc_fopen = 0x40233148);\r\nPROVIDE\t(webserver_open_file = 0x402331f4);\r\nPROVIDE\t(web_inc_fclose = 0x4023336c);\r\nPROVIDE\t(webserver_send_fdata = 0x40233410);\r\nPROVIDE\t(webserver_sent_callback = 0x4023379c);\r\nPROVIDE\t(web_trim_bufi = 0x40233830);\r\nPROVIDE\t(web_feee_bufi = 0x40233898);\r\nPROVIDE\t(head_find_ctr = 0x402338cc);\r\nPROVIDE\t(webserver_received_data = 0x40233acc);\r\nPROVIDE\t(tcpsrv_list_delete = 0x40234e04);\r\nPROVIDE\t(tcpsrv_client_reconnect = 0x40234eb0);\r\nPROVIDE\t(recv_trim_bufi = 0x40234f94);\r\nPROVIDE\t(tcpsrv_server_sent = 0x402350f8);\r\nPROVIDE\t(tcpsrv_print_remote_info = 0x40235150);\r\nPROVIDE\t(tcpsrv_server_close = 0x40235190);\r\nPROVIDE\t(tcpsrv_int_sent_data = 0x40235284);\r\nPROVIDE\t(tcpsrv_server_recv = 0x40235380);\r\nPROVIDE\t(tcpsrv_connected = 0x402354a8);\r\nPROVIDE\t(tcpsrv_server_poll = 0x4023556c);\r\nPROVIDE\t(tcpsrv_error = 0x40235614);\r\nPROVIDE\t(tcpsrv_disconnect_calback_default = 0x402356c0);\r\nPROVIDE\t(tcpsrv_listen_default = 0x402356e0);\r\nPROVIDE\t(tcpsrv_sent_callback_default = 0x40235700);\r\nPROVIDE\t(tcpsrv_received_data_default = 0x40235720);\r\nPROVIDE\t(tcpsrv_server_port2pcfg = 0x40235744);\r\nPROVIDE\t(tcpsrv_client_ip_port2conn = 0x40235764);\r\nPROVIDE\t(tcpsrv_unrecved_win = 0x40235790);\r\nPROVIDE\t(tcpsrv_init = 0x402357dc);\r\nPROVIDE\t(tcpsrv_start = 0x40235890);\r\nPROVIDE\t(tcpsrv_connected_default = 0x4023592c);\r\nPROVIDE\t(find_tcp_pcb = 0x40235948);\r\nPROVIDE\t(tcpsrv_close_cb = 0x4023599c);\r\nPROVIDE\t(tcpsrv_client_connect = 0x40235a84);\r\nPROVIDE\t(tcpsrv_client_start = 0x40235b48);\r\nPROVIDE\t(tcpsrv_disconnect = 0x40235be8);\r\nPROVIDE\t(tcpsrv_server_accept = 0x40235c1c);\r\nPROVIDE\t(tcpsrv_close = 0x40235d5c);\r\nPROVIDE\t(tcpsrv_close_port = 0x40235e1c);\r\nPROVIDE\t(tcpsrv_close_all = 0x40235e40);\r\nPROVIDE\t(web_hexdump = 0x40235e84);\r\nPROVIDE\t(web_get_i2c_eeprom = 0x40236008);\r\nPROVIDE\t(wifi_aps_xml = 0x402360a4);\r\nPROVIDE\t(web_wscan_xml = 0x40236208);\r\nPROVIDE\t(web_ProbeRequest_xml = 0x40236344);\r\nPROVIDE\t(web_get_history = 0x40236468);\r\nPROVIDE\t(web_get_flash = 0x402367cc);\r\nPROVIDE\t(web_get_ram = 0x40236860);\r\nPROVIDE\t(get_new_url = 0x402368ec);\r\nPROVIDE\t(web_int_callback = 0x40236c38);\r\nPROVIDE\t(rom_atoi = 0x40238970);\r\nPROVIDE\t(hextoul = 0x402389c0);\r\nPROVIDE\t(ahextoul = 0x40238a10);\r\nPROVIDE\t(cmpcpystr = 0x40238a44);\r\nPROVIDE\t(web_strnstr = 0x40238adc);\r\nPROVIDE\t(base64decode = 0x40238b4c);\r\nPROVIDE\t(base64encode = 0x40238c18);\r\nPROVIDE\t(strtomac = 0x40238ce4);\r\nPROVIDE\t(urldecode = 0x40238d50);\r\nPROVIDE\t(htmlcode = 0x40238e18);\r\nPROVIDE\t(print_hex_dump = 0x40238f60);\r\nPROVIDE\t(str_array = 0x40238fac);\r\nPROVIDE\t(str_array_w = 0x40239030);\r\nPROVIDE\t(str_array_b = 0x402390b8);\r\nPROVIDE\t(word_to_lower_case = 0x40239144);\r\nPROVIDE\t(copy_align4 = 0x4023917c);\r\nPROVIDE\t(go_deep_sleep = 0x4023924c);\r\nPROVIDE\t(reg_sct_bits = 0x40239264);\r\nPROVIDE\t(web_int_vars = 0x4023943c);\r\nPROVIDE\t(rd_buf_sec_blk = 0x4023a49c);\r\nPROVIDE\t(wr_buf_sec_blk = 0x4023a4d4);\r\nPROVIDE\t(read_sys_const = 0x4023a52c);\r\nPROVIDE\t(write_sys_const = 0x4023a54c);\r\nPROVIDE\t(uart_save_fcfg = 0x4023a5bc);\r\nPROVIDE\t(update_rts0 = 0x4023a658);\r\nPROVIDE\t(update_mux_uart0 = 0x4023a674);\r\nPROVIDE\t(uart0_set_flow = 0x4023a71c);\r\nPROVIDE\t(update_mux_txd1 = 0x4023a76c);\r\nPROVIDE\t(uart_read_fcfg = 0x4023a7a4);\r\nPROVIDE\t(uarts_init = 0x4023a864);\r\nPROVIDE\t(set_uartx_invx = 0x4023a888);\r\nPROVIDE\t(sar_init = 0x4023a900);\r\nPROVIDE\t(sar_off = 0x4023a9c8);\r\nPROVIDE\t(read_adcs = 0x4023aa2c);\r\nPROVIDE\t(sigma_delta_setup = 0x4023aad8);\r\nPROVIDE\t(sigma_delta_close = 0x4023ab30);\r\nPROVIDE\t(set_sigma_duty_312KHz = 0x4023ab80);\r\nPROVIDE\t(aFATAL_ERR_R6PHY = 0x4023abb4);\r\nPROVIDE\t(esp_init_data_default = 0x4023ac24);\r\nPROVIDE\t(ieee80211_opcap = 0x4023ad00);\r\nPROVIDE\t(ip_addr_broadcast = 0x4023b234);\r\nPROVIDE\t(ip_addr_any = 0x4023b238);\r\nPROVIDE\t(memp_sizes = 0x4023b270);\r\nPROVIDE\t(chip_v6_set_sense = 0x4023b5d4);\r\nPROVIDE\t(chip_v6_unset_chanfreq = 0x4023b5d8);\r\nPROVIDE\t(bit_popcount = 0x4023b89c);\r\nPROVIDE\t(tcp_pcb_lists = 0x4023b8c0);\r\nPROVIDE\t(tcp_persist_backoff = 0x4023b8d0);\r\nPROVIDE\t(tcp_backoff = 0x4023b8d8);\r\nPROVIDE\t(default_ssid = 0x4023b950);\r\nPROVIDE\t(eloop_cancel_timeout = 0x4023becc);\r\nPROVIDE\t(eloop_register_timeout = 0x4023bed0);\r\nPROVIDE\t(magic_cookie = 0x4023bfc4);\r\nPROVIDE\t(ccmp = 0x4023bfdc);\r\nPROVIDE\t(tkip = 0x4023bff4);\r\nPROVIDE\t(wep = 0x4023c00c);\r\nPROVIDE\t(lwip_standard_chksum = 0x4023c024);\r\nPROVIDE\t(inet_chksum = 0x4023c08c);\r\nPROVIDE\t(inet_chksum_pbuf = 0x4023c0a8);\r\nPROVIDE\t(inet_chksum_pseudo = 0x4023c114);\r\nPROVIDE\t(inet_chksum_pseudo_partial = 0x4023c1d4);\r\nPROVIDE\t(sysinifname = 0x4023c404);\r\nPROVIDE\t(wifi_st_password = 0x4023c964);\r\nPROVIDE\t(wifi_st_name = 0x4023c970);\r\nPROVIDE\t(wifi_ap_password = 0x4023c978);\r\nPROVIDE\t(wifi_ap_name = 0x4023c984);\r\nPROVIDE\t(tab_event_reason_1_24_200 = 0x4023cbe8);\r\nPROVIDE\t(txt_reason_handshake_timeout = 0x4023cc58);\r\nPROVIDE\t(txt_reason_assoc_fail = 0x4023cc6c);\r\nPROVIDE\t(txt_reason_auth_fail = 0x4023cc78);\r\nPROVIDE\t(txt_reason_no_ap_found = 0x4023cc84);\r\nPROVIDE\t(txt_reason_beacon_timeout = 0x4023cc90);\r\nPROVIDE\t(txt_reason_cipher_suite_rejected = 0x4023cca0);\r\nPROVIDE\t(txt_reason_802_1x_auth_failed = 0x4023ccb8);\r\nPROVIDE\t(txt_reason_invalid_rsn_ie_cap = 0x4023cccc);\r\nPROVIDE\t(txt_reason_unsupp_rsn_ie_version = 0x4023cce0);\r\nPROVIDE\t(txt_reason_akmp_invalid = 0x4023ccf8);\r\nPROVIDE\t(txt_reason_pairwise_cipher_invalid = 0x4023cd08);\r\nPROVIDE\t(txt_reason_group_cipher_invalid = 0x4023cd20);\r\nPROVIDE\t(txt_reason_ie_in_4way_differs = 0x4023cd38);\r\nPROVIDE\t(txt_reason_group_key_update_timeout = 0x4023cd4c);\r\nPROVIDE\t(txt_reason_4way_handshake_timeout = 0x4023cd68);\r\nPROVIDE\t(txt_reason_mic_failure = 0x4023cd80);\r\nPROVIDE\t(txt_reason_ie_invalid = 0x4023cd8c);\r\nPROVIDE\t(txt_reason_disassoc_supchan_bad = 0x4023cd98);\r\nPROVIDE\t(txt_reason_disassoc_pwrcap_bad = 0x4023cdb0);\r\nPROVIDE\t(txt_reason_assoc_not_authed = 0x4023cdc4);\r\nPROVIDE\t(txt_reason_assoc_leave = 0x4023cdd8);\r\nPROVIDE\t(txt_reason_not_assoced = 0x4023cde4);\r\nPROVIDE\t(txt_reason_not_authed = 0x4023cdf0);\r\nPROVIDE\t(txt_reason_assoc_toomany = 0x4023cdfc);\r\nPROVIDE\t(txt_reason_assoc_expire = 0x4023ce0c);\r\nPROVIDE\t(txt_reason_auth_leave = 0x4023ce1c);\r\nPROVIDE\t(txt_reason_auth_expire = 0x4023ce28);\r\nPROVIDE\t(txt_reason_unspecified = 0x4023ce34);\r\nPROVIDE\t(txt_reason_undef = 0x4023ce40);\r\nPROVIDE\t(sntp_server_addresses = 0x4023ce9c);\r\nPROVIDE\t(flash_filename = 0x4023d248);\r\nPROVIDE\t(file_label = 0x4023d254);\r\nPROVIDE\t(sector_filename = 0x4023d25c);\r\nPROVIDE\t(sysconst_filename = 0x4023d264);\r\nPROVIDE\t(disk_err4_filename = 0x4023d270);\r\nPROVIDE\t(disk_err3_filename = 0x4023d280);\r\nPROVIDE\t(disk_err2_filename = 0x4023d290);\r\nPROVIDE\t(disk_err1_filename = 0x4023d2a0);\r\nPROVIDE\t(disk_ok_filename = 0x4023d2b0);\r\nPROVIDE\t(crlf_end_boundary = 0x4023d2c0);\r\nPROVIDE\t(HTTPAccessControlAllowOrigin = 0x4023d5d4);\r\nPROVIDE\t(HTTPfserror = 0x4023d5f8);\r\nPROVIDE\t(HTTPdefault = 0x4023d644);\r\nPROVIDE\t(HTTPfsupload = 0x4023d690);\r\nPROVIDE\t(HTTPResponse = 0x4023d770);\r\nPROVIDE\t(HTTPresponse_501_content = 0x4023d840);\r\nPROVIDE\t(HTTPresponse_500_content = 0x4023d874);\r\nPROVIDE\t(HTTPresponse_418_content = 0x4023d890);\r\nPROVIDE\t(HTTPresponse_414_content = 0x4023d8a8);\r\nPROVIDE\t(HTTPresponse_413_content = 0x4023d8e0);\r\nPROVIDE\t(HTTPresponse_411_content = 0x4023d91c);\r\nPROVIDE\t(HTTPresponse_404_content = 0x4023d94c);\r\nPROVIDE\t(HTTPresponse_401_content = 0x4023d964);\r\nPROVIDE\t(HTTPresponse_501_head = 0x4023d98c);\r\nPROVIDE\t(HTTPresponse_500_head = 0x4023d9b0);\r\nPROVIDE\t(HTTPresponse_429_head = 0x4023d9c8);\r\nPROVIDE\t(HTTPresponse_418_head = 0x4023d9ec);\r\nPROVIDE\t(HTTPresponse_414_head = 0x4023d9fc);\r\nPROVIDE\t(HTTPresponse_413_head = 0x4023da14);\r\nPROVIDE\t(HTTPresponse_411_head = 0x4023da30);\r\nPROVIDE\t(HTTPresponse_404_head = 0x4023da40);\r\nPROVIDE\t(HTTPresponse_401_head = 0x4023da4c);\r\nPROVIDE\t(HTTPresponse_400_head = 0x4023da84);\r\nPROVIDE\t(HTTPresponse_304_head = 0x4023da90);\r\nPROVIDE\t(HTTPresponse_302_head = 0x4023daa0);\r\nPROVIDE\t(HTTPresponse_200_head = 0x4023daa8);\r\nPROVIDE\t(fsupload_fname = 0x4023daac);\r\nPROVIDE\t(web_cgi_fname = 0x4023dab8);\r\nPROVIDE\t(http_default_file = 0x4023dac0);\r\nPROVIDE\t(srvContenErr15 = 0x4023dc20);\r\nPROVIDE\t(srvContenErr14 = 0x4023dc34);\r\nPROVIDE\t(srvContenErr13 = 0x4023dc4c);\r\nPROVIDE\t(srvContenErr12 = 0x4023dc5c);\r\nPROVIDE\t(srvContenErr11 = 0x4023dc70);\r\nPROVIDE\t(srvContenErr10 = 0x4023dc80);\r\nPROVIDE\t(srvContenErr09 = 0x4023dc94);\r\nPROVIDE\t(srvContenErr08 = 0x4023dca8);\r\nPROVIDE\t(srvContenErr07 = 0x4023dcbc);\r\nPROVIDE\t(srvContenErr06 = 0x4023dcd4);\r\nPROVIDE\t(srvContenErr05 = 0x4023dce4);\r\nPROVIDE\t(srvContenErr04 = 0x4023dcfc);\r\nPROVIDE\t(srvContenErr03 = 0x4023dd0c);\r\nPROVIDE\t(srvContenErr02 = 0x4023dd14);\r\nPROVIDE\t(srvContenErr01 = 0x4023dd24);\r\nPROVIDE\t(srvContenErr00 = 0x4023dd38);\r\nPROVIDE\t(txt_tcpsrv_out_of_mem = 0x4023df20);\r\nPROVIDE\t(txt_tcpsrv_already_initialized = 0x4023df38);\r\nPROVIDE\t(txt_tcpsrv_NULL_pointer = 0x4023df58);\r\nPROVIDE\t(base64map = 0x4023e224);\r\nPROVIDE\t(_irom0_text_end = 0x4023e2cc);\r\nPROVIDE\t(uart0_ = 0x60000000);\r\nPROVIDE\t(spi0_ = 0x60000200);\r\nPROVIDE\t(gpio_ = 0x60000300);\r\nPROVIDE\t(timer_ = 0x60000600);\r\nPROVIDE\t(rtc_ = 0x60000700);\r\nPROVIDE\t(iomux_ = 0x60000800);\r\nPROVIDE\t(wdt_ = 0x60000900);\r\nPROVIDE\t(sar_ = 0x60000d00);\r\nPROVIDE\t(uart1_ = 0x60000f00);\r\nPROVIDE\t(rtc_ram_ = 0x60001000);\r\nPROVIDE\t(rtc_mem_ = 0x60001100);\r\nPROVIDE\t(_memmap_cacheattr_unused_mask = 0xfffff00f);\r\nPROVIDE\t(_memmap_cacheattr_wb_strict = 0xfffff11f);\r\nPROVIDE\t(_memmap_cacheattr_wt_strict = 0xfffff11f);\r\nPROVIDE\t(_memmap_cacheattr_bp_strict = 0xfffff22f);\r\n=======\nPROVIDE\t(_memmap_cacheattr_wb_base = 0x00000110);\nPROVIDE\t(_memmap_cacheattr_wt_base = 0x00000110);\nPROVIDE\t(_memmap_cacheattr_bp_base = 0x00000220);\nPROVIDE\t(_memmap_cacheattr_wb_allvalid = 0x22222112);\nPROVIDE\t(_memmap_cacheattr_wt_allvalid = 0x22222112);\nPROVIDE\t(_memmap_cacheattr_wb_trapnull = 0x2222211f);\nPROVIDE\t(_memmap_cacheattr_wba_trapnull = 0x2222211f);\nPROVIDE\t(_memmap_cacheattr_wbna_trapnull = 0x2222211f);\nPROVIDE\t(_memmap_cacheattr_wt_trapnull = 0x2222211f);\nPROVIDE\t(_memmap_cacheattr_bp_allvalid = 0x22222222);\nPROVIDE\t(_memmap_cacheattr_bp_trapnull = 0x2222222f);\nPROVIDE\t(_dport0_data_end = 0x3ff00000);\nPROVIDE\t(_dport0_data_start = 0x3ff00000);\nPROVIDE\t(_dport0_literal_end = 0x3ff00000);\nPROVIDE\t(_dport0_literal_start = 0x3ff00000);\nPROVIDE\t(_dport0_rodata_end = 0x3ff00000);\nPROVIDE\t(_dport0_rodata_start = 0x3ff00000);\nPROVIDE\t(dport_ = 0x3ff00000);\nPROVIDE\t(_data_start = 0x3ffe8000);\nPROVIDE\t(SDK_VERSION = 0x3ffe8000);\nPROVIDE\t(TmpSTAAPCloseAP = 0x3ffe8008);\nPROVIDE\t(memp_sizes_test = 0x3ffe800a);\nPROVIDE\t(tx_rf_ana_gain = 0x3ffe8012);\nPROVIDE\t(rx_gain_swp = 0x3ffe8040);\nPROVIDE\t(test_rffreq_txcap = 0x3ffe8060);\nPROVIDE\t(rfcal_bb_atten_init = 0x3ffe8064);\nPROVIDE\t(chip_version = 0x3ffe8068);\nPROVIDE\t(soft_wdt_interval = 0x3ffe8074);\nPROVIDE\t(NoiseTimerInterval = 0x3ffe8078);\nPROVIDE\t(sleep_start_wait_time = 0x3ffe8080);\nPROVIDE\t(CanDoFreqCal = 0x3ffe8088);\nPROVIDE\t(tcb = 0x3ffe808c);\nPROVIDE\t(timer2_ms_flag = 0x3ffe832d);\nPROVIDE\t(dhcps_flag = 0x3ffe832e);\nPROVIDE\t(dhcpc_flag = 0x3ffe832f);\nPROVIDE\t(reconnect_internal = 0x3ffe8331);\nPROVIDE\t(offer = 0x3ffe8344);\nPROVIDE\t(HTTPCookie = 0x3ffe8364);\nPROVIDE\t(HTTPAuthorization = 0x3ffe8368);\nPROVIDE\t(HTTPboundary = 0x3ffe836c);\nPROVIDE\t(HTTPmultipartformdata = 0x3ffe8370);\nPROVIDE\t(HTTPContentType = 0x3ffe8374);\nPROVIDE\t(HTTPContentLength = 0x3ffe8378);\nPROVIDE\t(HTTPHost = 0x3ffe837c);\nPROVIDE\t(HTTPSecWebSocketKey = 0x3ffe8380);\nPROVIDE\t(HTTPwebsocket = 0x3ffe8384);\nPROVIDE\t(HTTPUpgrade = 0x3ffe8388);\nPROVIDE\t(_data_end = 0x3ffe838c);\nPROVIDE\t(_rodata_start = 0x3ffe838c);\nPROVIDE\t(ethzero = 0x3ffe838c);\nPROVIDE\t(ethbroadcast = 0x3ffe8392);\nPROVIDE\t(HostNameLocal = 0x3ffe8448);\nPROVIDE\t(httpContentTypes = 0x3ffe846c);\nPROVIDE\t(httpFileExtensions = 0x3ffe84b4);\nPROVIDE\t(mdbtabaddr = 0x3ffe8538);\nPROVIDE\t(_bss_table_end = 0x3ffe8bbc);\nPROVIDE\t(_bss_table_start = 0x3ffe8bbc);\nPROVIDE\t(_rodata_end = 0x3ffe8bbc);\nPROVIDE\t(_bss_start = 0x3ffe8bc0);\nPROVIDE\t(etharp_cached_entry = 0x3ffe8bc0);\nPROVIDE\t(arp_table = 0x3ffe8bc4);\nPROVIDE\t(g_ic = 0x3ffe8cb4);\nPROVIDE\t(BcnEb_update = 0x3ffe9340);\nPROVIDE\t(BcnWithMcastSendStart = 0x3ffe934d);\nPROVIDE\t(BcnWithMcastSendCnt = 0x3ffe934e);\nPROVIDE\t(PendFreeBcnEb = 0x3ffe9368);\nPROVIDE\t(ApFreqCalTimer = 0x3ffe936c);\nPROVIDE\t(APRecvBcnStartTick = 0x3ffe9380);\nPROVIDE\t(gScanStruct = 0x3ffe9398);\nPROVIDE\t(connect_scan_flag = 0x3ffe9444);\nPROVIDE\t(FreqCalCntForScan = 0x3ffe9445);\nPROVIDE\t(TestStaFreqCalValInput = 0x3ffe9446);\nPROVIDE\t(auth_type = 0x3ffe9448);\nPROVIDE\t(scannum = 0x3ffe944a);\nPROVIDE\t(interface_mask = 0x3ffe9470);\nPROVIDE\t(if_ctrl = 0x3ffe9490);\nPROVIDE\t(ip_id = 0x3ffe94b0);\nPROVIDE\t(lmacConfMib = 0x3ffe94d4);\nPROVIDE\t(our_tx_eb = 0x3ffe94f8);\nPROVIDE\t(xStart = 0x3ffe9620);\nPROVIDE\t(g_phyFuns = 0x3ffe9630);\nPROVIDE\t(rxiq_compute_num = 0x3ffe9634);\nPROVIDE\t(rx_table_renew_en = 0x3ffe9638);\nPROVIDE\t(check_result = 0x3ffe963c);\nPROVIDE\t(chip6_sleep_params = 0x3ffe9640);\nPROVIDE\t(chip6_phy_init_ctrl = 0x3ffe96d4);\nPROVIDE\t(phy_freq_offset = 0x3ffe9748);\nPROVIDE\t(do_pwctrl_flag = 0x3ffe974a);\nPROVIDE\t(txbk_dpdby_flag = 0x3ffe974b);\nPROVIDE\t(sw_scan_mode = 0x3ffe974d);\nPROVIDE\t(rxmax_ext_level = 0x3ffe974e);\nPROVIDE\t(phy_rx_gain_dc_table = 0x3ffe9750);\nPROVIDE\t(periodic_cal_dc_num = 0x3ffe9764);\nPROVIDE\t(periodic_cal_flag = 0x3ffe9768);\nPROVIDE\t(bbpll_cal_flag = 0x3ffe9769);\nPROVIDE\t(phy_in_most_power = 0x3ffe976a);\nPROVIDE\t(init_rf_no_cal = 0x3ffe976b);\nPROVIDE\t(test_print_time = 0x3ffe976c);\nPROVIDE\t(phy_rx_gain_dc_flag = 0x3ffe9770);\nPROVIDE\t(phy_in_vdd33_offset = 0x3ffe9771);\nPROVIDE\t(phy_set_most_tpw_disbg = 0x3ffe9772);\nPROVIDE\t(phy_set_most_tpw_index = 0x3ffe9773);\nPROVIDE\t(adc_rand_noise = 0x3ffe9774);\nPROVIDE\t(dpd_bypass_original = 0x3ffe9778);\nPROVIDE\t(phy_txpwr_diff_flash = 0x3ffe977a);\nPROVIDE\t(noise_array = 0x3ffe9780);\nPROVIDE\t(tout_dis_txpwr_track = 0x3ffe978c);\nPROVIDE\t(sleep_mode_flag = 0x3ffe978d);\nPROVIDE\t(phy_tx_power_out = 0x3ffe9790);\nPROVIDE\t(phy_tx_pwr_error = 0x3ffe9792);\nPROVIDE\t(tx_pwctrl_track_num = 0x3ffe9794);\nPROVIDE\t(rxiq_cover_fail_num = 0x3ffe9795);\nPROVIDE\t(phy_meas_freq_offset = 0x3ffe9796);\nPROVIDE\t(tx_pwctrl_pk_num = 0x3ffe9798);\nPROVIDE\t(periodic_cal_sat = 0x3ffe979c);\nPROVIDE\t(lslp_mem_opt_8266 = 0x3ffe979e);\nPROVIDE\t(software_slp_reject = 0x3ffe97a0);\nPROVIDE\t(SDIO_slp_reject = 0x3ffe97a1);\nPROVIDE\t(hardware_reject = 0x3ffe97a2);\nPROVIDE\t(pmc = 0x3ffe97b0);\nPROVIDE\t(flash_tmp = 0x3ffe9890);\nPROVIDE\t(pend_flag_noise_check = 0x3ffe9918);\nPROVIDE\t(pend_flag_periodic_cal = 0x3ffe9920);\nPROVIDE\t(idle_timer_reopen_flag = 0x3ffe9938);\nPROVIDE\t(dbg_stop_sw_wdt = 0x3ffe993a);\nPROVIDE\t(dbg_stop_hw_wdt = 0x3ffe993b);\nPROVIDE\t(total_buffed_eb_num = 0x3ffe993d);\nPROVIDE\t(HighestFreqOffsetInOneChk = 0x3ffe9940);\nPROVIDE\t(LowestFreqOffsetInOneChk = 0x3ffe9942);\nPROVIDE\t(DefFreqCalTimer = 0x3ffe9944);\nPROVIDE\t(PktNumInOneChk = 0x3ffe9958);\nPROVIDE\t(buffed_eb_arr = 0x3ffe9ae0);\nPROVIDE\t(tcp_timer = 0x3ffe9d30);\nPROVIDE\t(recv_flags = 0x3ffe9d34);\nPROVIDE\t(tcplen = 0x3ffe9d36);\nPROVIDE\t(flags = 0x3ffe9d38);\nPROVIDE\t(seqno = 0x3ffe9d3c);\nPROVIDE\t(inseg = 0x3ffe9d40);\nPROVIDE\t(deep_sleep_flag = 0x3ffea2c7);\nPROVIDE\t(cpu_overclock = 0x3ffea2c8);\nPROVIDE\t(event_cb = 0x3ffea2cc);\nPROVIDE\t(status_led_output_level = 0x3ffea2d0);\nPROVIDE\t(done_cb = 0x3ffea2d4);\nPROVIDE\t(rst_if = 0x3ffea2d8);\nPROVIDE\t(default_interface = 0x3ffea2f4);\nPROVIDE\t(OpmodChgIsOnGoing = 0x3ffea2f5);\nPROVIDE\t(promiscuous_cb = 0x3ffea2f8);\nPROVIDE\t(event_TaskQueue = 0x3ffea310);\nPROVIDE\t(wDevCtrl = 0x3ffea420);\nPROVIDE\t(WdevTimOffSet = 0x3ffea5c8);\nPROVIDE\t(sta_con_timer = 0x3ffed748);\nPROVIDE\t(backup_ni_connect_status = 0x3ffed75c);\nPROVIDE\t(g_cnx_probe_rc_list_cb = 0x3ffed760);\nPROVIDE\t(reconnect_flag = 0x3ffed764);\nPROVIDE\t(no_ap_found_index = 0x3ffed765);\nPROVIDE\t(client_address_plus = 0x3ffed9dc);\nPROVIDE\t(client_address = 0x3ffed9e0);\nPROVIDE\t(server_address = 0x3ffed9e4);\nPROVIDE\t(broadcast_dhcps = 0x3ffed9e8);\nPROVIDE\t(dns_random = 0x3ffed9ec);\nPROVIDE\t(dns_servers = 0x3ffed9f0);\nPROVIDE\t(dns_seqno = 0x3ffed9f8);\nPROVIDE\t(allrouters = 0x3ffee4b0);\nPROVIDE\t(allsystems = 0x3ffee4b4);\nPROVIDE\t(info = 0x3ffee4b8);\nPROVIDE\t(user_init_flag = 0x3ffee4dc);\nPROVIDE\t(lwip_timer_interval = 0x3ffee4de);\nPROVIDE\t(default_hostname = 0x3ffee4e0);\nPROVIDE\t(current_iphdr_src = 0x3ffee4e4);\nPROVIDE\t(current_netif = 0x3ffee4e8);\nPROVIDE\t(current_iphdr_dest = 0x3ffee4ec);\nPROVIDE\t(current_header = 0x3ffee4f0);\nPROVIDE\t(tcp_listen_pcbs = 0x3ffee4f4);\nPROVIDE\t(dhcp_rx_options_given = 0x3ffee4f8);\nPROVIDE\t(dhcp_rx_options_val = 0x3ffee504);\nPROVIDE\t(dhcp_sntp_server_address = 0x3ffee530);\nPROVIDE\t(dhcps_lease = 0x3ffee534);\nPROVIDE\t(dns_table = 0x3ffee53c);\nPROVIDE\t(wificonfig = 0x3ffee99c);\nPROVIDE\t(syscfg = 0x3ffeeacc);\nPROVIDE\t(tcp_client_url = 0x3ffeeae4);\nPROVIDE\t(netbios_name = 0x3ffeeae8);\nPROVIDE\t(fatCache = 0x3ffeeafc);\nPROVIDE\t(mdb_buf = 0x3ffeeb0c);\nPROVIDE\t(_bss_end = 0x3ffeebd8);\nPROVIDE\t(_heap_start = 0x3ffeebd8);\nPROVIDE\t(flashchip = 0x3fffc714);\nPROVIDE\t(Te0 = 0x3fffccf0);\nPROVIDE\t(rcons = 0x3fffd0f0);\nPROVIDE\t(base64_table = 0x3fffd600);\nPROVIDE\t(timer_list = 0x3fffddb0);\nPROVIDE\t(UartDev = 0x3fffde10);\nPROVIDE\t(_sprintf_buf = 0x3fffe360);\nPROVIDE\t(print_mem_buf = 0x3fffe364);\nPROVIDE\t(_ResetVector = 0x40000080);\nPROVIDE\t(_xtos_set_exception_handler = 0x40000454);\nPROVIDE\t(__muldi3 = 0x40000650);\nPROVIDE\t(ets_set_idle_cb = 0x40000dc0);\nPROVIDE\t(ets_task = 0x40000dd0);\nPROVIDE\t(ets_run = 0x40000e04);\nPROVIDE\t(ets_post = 0x40000e24);\nPROVIDE\t(ets_intr_lock = 0x40000f74);\nPROVIDE\t(ets_intr_unlock = 0x40000f80);\nPROVIDE\t(ets_isr_attach = 0x40000f88);\nPROVIDE\t(ets_isr_mask = 0x40000f98);\nPROVIDE\t(ets_isr_unmask = 0x40000fa8);\nPROVIDE\t(ets_set_user_start = 0x40000fbc);\nPROVIDE\t(ets_memset = 0x400018a4);\nPROVIDE\t(ets_memcpy = 0x400018b4);\nPROVIDE\t(ets_memcmp = 0x400018d4);\nPROVIDE\t(ets_write_char = 0x40001da0);\nPROVIDE\t(ets_vprintf = 0x40001f00);\nPROVIDE\t(ets_install_putc1 = 0x4000242c);\nPROVIDE\t(ets_printf = 0x400024cc);\nPROVIDE\t(rtc_get_reset_reason = 0x400025e0);\nPROVIDE\t(ets_strcpy = 0x40002a88);\nPROVIDE\t(ets_strncpy = 0x40002a98);\nPROVIDE\t(ets_strcmp = 0x40002aa8);\nPROVIDE\t(ets_strncmp = 0x40002ab8);\nPROVIDE\t(ets_strlen = 0x40002ac8);\nPROVIDE\t(ets_bzero = 0x40002ae8);\nPROVIDE\t(ets_timer_setfn = 0x40002c48);\nPROVIDE\t(timer_insert = 0x40002c64);\nPROVIDE\t(ets_timer_disarm = 0x40002d40);\nPROVIDE\t(ets_timer_init = 0x40002e68);\nPROVIDE\t(ets_delay_us = 0x40002ecc);\nPROVIDE\t(ets_update_cpu_frequency = 0x40002f04);\nPROVIDE\t(ets_get_cpu_frequency = 0x40002f0c);\nPROVIDE\t(ets_wdt_get_mode = 0x40002f34);\nPROVIDE\t(roundup2 = 0x400031b4);\nPROVIDE\t(uart_buff_switch = 0x400038a4);\nPROVIDE\t(uart_div_modify = 0x400039d8);\nPROVIDE\t(Uart_Init = 0x40003a14);\nPROVIDE\t(SelectSpiFunction = 0x40003f58);\nPROVIDE\t(SPI_read_status = 0x400043c8);\nPROVIDE\t(SPI_write_status = 0x40004400);\nPROVIDE\t(Wait_SPI_Idle = 0x4000448c);\nPROVIDE\t(SPIFlashCnfig = 0x40004568);\nPROVIDE\t(Cache_Read_Enable = 0x40004678);\nPROVIDE\t(Cache_Read_Disable = 0x400047f0);\nPROVIDE\t(SPIReadModeCnfig = 0x400048ec);\nPROVIDE\t(SPIEraseBlock = 0x400049b4);\nPROVIDE\t(SPIEraseSector = 0x40004a00);\nPROVIDE\t(SPIWrite = 0x40004a4c);\nPROVIDE\t(gpio_output_set = 0x40004cd0);\nPROVIDE\t(gpio_pin_intr_state_set = 0x40004d90);\nPROVIDE\t(lldesc_build_chain = 0x40004f40);\nPROVIDE\t(lldesc_num2link = 0x40005050);\nPROVIDE\t(rom_chip_v5_disable_cca = 0x400060d0);\nPROVIDE\t(rom_chip_v5_enable_cca = 0x400060ec);\nPROVIDE\t(phy_get_romfuncs = 0x40006b08);\nPROVIDE\t(rom_i2c_readReg = 0x40007268);\nPROVIDE\t(rom_i2c_writeReg = 0x400072d8);\nPROVIDE\t(rom_i2c_writeReg_Mask = 0x4000730c);\nPROVIDE\t(aes_unwrap = 0x40009410);\nPROVIDE\t(hmac_md5 = 0x4000a2cc);\nPROVIDE\t(SHA1Init = 0x4000b584);\nPROVIDE\t(SHA1Update = 0x4000b5a8);\nPROVIDE\t(SHA1Final = 0x4000b648);\nPROVIDE\t(pbkdf2_sha1 = 0x4000b840);\nPROVIDE\t(hmac_sha1_vector = 0x4000b8b4);\nPROVIDE\t(hmac_sha1 = 0x4000ba28);\nPROVIDE\t(sha1_prf = 0x4000ba48);\nPROVIDE\t(__addsf3 = 0x4000c180);\nPROVIDE\t(__subsf3 = 0x4000c268);\nPROVIDE\t(__mulsf3 = 0x4000c3dc);\nPROVIDE\t(__fixunssfsi = 0x4000c4c4);\nPROVIDE\t(__muldf3 = 0x4000c8f0);\nPROVIDE\t(__divdf3 = 0x4000cb94);\nPROVIDE\t(__fixdfsi = 0x4000ccb8);\nPROVIDE\t(__truncdfsf2 = 0x4000cd5c);\nPROVIDE\t(__divdi3 = 0x4000ce60);\nPROVIDE\t(__umoddi3 = 0x4000d770);\nPROVIDE\t(__divsi3 = 0x4000dc88);\nPROVIDE\t(rc4_skip = 0x4000dd68);\nPROVIDE\t(memcpy = 0x4000df48);\nPROVIDE\t(memset = 0x4000e190);\nPROVIDE\t(__udivsi3 = 0x4000e21c);\nPROVIDE\t(__umodsi3 = 0x4000e268);\nPROVIDE\t(__floatunsisf = 0x4000e2a4);\nPROVIDE\t(__floatsisf = 0x4000e2ac);\nPROVIDE\t(__floatunsidf = 0x4000e2e8);\nPROVIDE\t(__floatsidf = 0x4000e2f0);\nPROVIDE\t(_stext = 0x40100000);\nPROVIDE\t(_text_start = 0x40100000);\nPROVIDE\t(jump_boot = 0x40100000);\nPROVIDE\t(set_qspi_flash_cache = 0x40100024);\nPROVIDE\t(uart1_write_char = 0x40100074);\nPROVIDE\t(call_jump_boot = 0x401000cc);\nPROVIDE\t(uart0_write_char = 0x4010013c);\nPROVIDE\t(user_uart_wait_tx_fifo_empty = 0x4010018c);\nPROVIDE\t(ets_timer_arm_new = 0x401001d0);\nPROVIDE\t(lmacIsActive = 0x401002a4);\nPROVIDE\t(lmacIsIdle = 0x401002b8);\nPROVIDE\t(lmacSetAcParam = 0x40100754);\nPROVIDE\t(lmacProcessTXStartData = 0x401007a8);\nPROVIDE\t(lmacProcessTxSuccess = 0x40100928);\nPROVIDE\t(GetAccess = 0x40100a6c);\nPROVIDE\t(lmacDiscardAgedMSDU = 0x40100a78);\nPROVIDE\t(lmacRecycleMPDU = 0x40100a8c);\nPROVIDE\t(lmacProcessTxTimeout = 0x40101064);\nPROVIDE\t(lmacProcessAllTxTimeout = 0x401010cc);\nPROVIDE\t(lmacProcessCollisions = 0x401010e0);\nPROVIDE\t(lmacProcessCollision = 0x40101140);\nPROVIDE\t(lmacMSDUAged = 0x401011c4);\nPROVIDE\t(lmacProcessCtsTimeout = 0x40101554);\nPROVIDE\t(lmacProcessAckTimeout = 0x4010158c);\nPROVIDE\t(lmacProcessRtsStart = 0x401015e4);\nPROVIDE\t(lmacProcessTxRtsError = 0x401015f0);\nPROVIDE\t(lmacProcessTxError = 0x40101690);\nPROVIDE\t(lmacTxFrame = 0x40101720);\nPROVIDE\t(lmacRxDone = 0x401018bc);\nPROVIDE\t(prvInsertBlockIntoFreeList = 0x401018dc);\nPROVIDE\t(pvPortMalloc = 0x40101924);\nPROVIDE\t(vPortFree = 0x401019d4);\nPROVIDE\t(pvPortCalloc = 0x40101a24);\nPROVIDE\t(pvPortZalloc = 0x40101a54);\nPROVIDE\t(pvPortRealloc = 0x40101a68);\nPROVIDE\t(xPortGetFreeHeapSize = 0x40101aa0);\nPROVIDE\t(vPortInitialiseBlocks = 0x40101aa8);\nPROVIDE\t(xPortWantedSizeAlign = 0x40101aac);\nPROVIDE\t(register_phy_ops = 0x40101ac4);\nPROVIDE\t(register_get_phy_addr = 0x40101ae4);\nPROVIDE\t(phy_change_channel = 0x40101aec);\nPROVIDE\t(phy_get_mactime = 0x40101b04);\nPROVIDE\t(phy_debug_print = 0x40101b24);\nPROVIDE\t(phy_adc_read_fast = 0x40101b84);\nPROVIDE\t(unsign_to_sign = 0x40101dc8);\nPROVIDE\t(phy_get_bb_freqoffset = 0x40101e04);\nPROVIDE\t(phy_get_bb_evm = 0x40101e6c);\nPROVIDE\t(pm_rtc_clock_cali = 0x40101e88);\nPROVIDE\t(clockgate_watchdog = 0x40101f44);\nPROVIDE\t(pp_soft_wdt_feed_local = 0x40101fa8);\nPROVIDE\t(ppProcessTxQ = 0x4010203c);\nPROVIDE\t(ppFetchTxQFirstAvail = 0x401020b0);\nPROVIDE\t(ppDequeueTxQ = 0x401020f0);\nPROVIDE\t(ppRollBackTxQ = 0x40102118);\nPROVIDE\t(ppRecordBarRRC = 0x4010213c);\nPROVIDE\t(ppTxqUpdateBitmap = 0x4010214c);\nPROVIDE\t(ppEnqueueTxDone = 0x40102174);\nPROVIDE\t(ppEnqueueRxq = 0x401021a8);\nPROVIDE\t(ppDiscardMPDU = 0x40102690);\nPROVIDE\t(pp_post = 0x401026b4);\nPROVIDE\t(pp_post2 = 0x40102740);\nPROVIDE\t(ppCalTxop = 0x40102768);\nPROVIDE\t(ppCalFrameTimes = 0x401027e8);\nPROVIDE\t(RC_GetAckRate = 0x40102878);\nPROVIDE\t(RC_GetRtsRate = 0x40102884);\nPROVIDE\t(RC_GetAckTime = 0x40102894);\nPROVIDE\t(RC_GetCtsTime = 0x401028a8);\nPROVIDE\t(RC_GetBlockAckTime = 0x401028e0);\nPROVIDE\t(copy_s4d1 = 0x40102950);\nPROVIDE\t(copy_s1d4 = 0x401029e4);\nPROVIDE\t(eRamRead = 0x40102a7c);\nPROVIDE\t(eRamWrite = 0x40102aa4);\nPROVIDE\t(rom_strlen = 0x40102ac8);\nPROVIDE\t(rom_strcpy = 0x40102afc);\nPROVIDE\t(rom_xstrcpy = 0x40102b60);\nPROVIDE\t(rom_xstrcmp = 0x40102bb0);\nPROVIDE\t(rom_strchr = 0x40102bf8);\nPROVIDE\t(get_align4_chr = 0x40102c34);\nPROVIDE\t(write_align4_chr = 0x40102c4c);\nPROVIDE\t(Cache_Read_Enable_New = 0x40102c6c);\nPROVIDE\t(spi_flash_read = 0x40102c90);\nPROVIDE\t(spi_flash_get_id = 0x40102d98);\nPROVIDE\t(spi_flash_read_status = 0x40102de8);\nPROVIDE\t(spi_flash_write_status = 0x40102e24);\nPROVIDE\t(spi_flash_erase_sector = 0x40102e60);\nPROVIDE\t(spi_flash_write = 0x40102eb0);\nPROVIDE\t(spi_flash_erase_block = 0x40102f18);\nPROVIDE\t(tcp_accept_null = 0x40102f60);\nPROVIDE\t(tcp_new_port = 0x40102f78);\nPROVIDE\t(tcp_close_shutdown = 0x4010300c);\nPROVIDE\t(dns_timer = 0x40103164);\nPROVIDE\t(igmp_timer = 0x40103190);\nPROVIDE\t(dhcp_timer_fine = 0x401031bc);\nPROVIDE\t(dhcp_timer_coarse = 0x401031f0);\nPROVIDE\t(rcUpdateTxDone = 0x401033ec);\nPROVIDE\t(rcUpdateRxDone = 0x40103480);\nPROVIDE\t(rcUpdateDataRxDone = 0x401034dc);\nPROVIDE\t(rcGetSched = 0x401034f8);\nPROVIDE\t(rcGetRate = 0x401035dc);\nPROVIDE\t(rcReachRetryLimit = 0x40103af0);\nPROVIDE\t(trc_NeedRTS = 0x40103b08);\nPROVIDE\t(os_printf_plus = 0x40103bd8);\nPROVIDE\t(system_restart_core = 0x40103d04);\nPROVIDE\t(system_deep_sleep_local_2 = 0x40103d40);\nPROVIDE\t(system_get_time = 0x40103db0);\nPROVIDE\t(system_os_post = 0x40103dc8);\nPROVIDE\t(system_rtc_mem_write = 0x40103dfc);\nPROVIDE\t(system_rtc_mem_read = 0x40103e54);\nPROVIDE\t(wDev_MacTim1SetFunc = 0x40104250);\nPROVIDE\t(wDev_MacTim1Arm = 0x40104270);\nPROVIDE\t(wDev_ProcessFiq = 0x40104308);\nPROVIDE\t(wDev_EnableTransmit = 0x4010464c);\nPROVIDE\t(wDev_DisableTransmit = 0x40104684);\nPROVIDE\t(Tx_Copy2Queue = 0x401046a4);\nPROVIDE\t(wDev_ProcessCollision = 0x401046ec);\nPROVIDE\t(wDev_GetTxqCollisions = 0x40104710);\nPROVIDE\t(wDev_ClearTxqCollisions = 0x40104724);\nPROVIDE\t(wDev_SetWaitingQueue = 0x40104740);\nPROVIDE\t(wDev_ClearWaitingQueue = 0x40104788);\nPROVIDE\t(wDev_SetFrameAckType = 0x401047ac);\nPROVIDE\t(wDev_AppendRxBlocks = 0x40104810);\nPROVIDE\t(wDev_AppendRxAmpduLensBlocks = 0x40104954);\nPROVIDE\t(wDev_GetBAInfo = 0x40104a28);\nPROVIDE\t(wDevDisableRx = 0x40104a5c);\nPROVIDE\t(store_exception_error = 0x40104f1c);\nPROVIDE\t(fatal_error = 0x40104f54);\nPROVIDE\t(default_exception_handler = 0x40104f70);\nPROVIDE\t(chm_get_current_channel = 0x40104f88);\nPROVIDE\t(__divsf3_aux = 0x40104f94);\nPROVIDE\t(__divsf3 = 0x40105010);\nPROVIDE\t(__fixsfsi = 0x401050cc);\nPROVIDE\t(esf_rx_buf_alloc = 0x40105110);\nPROVIDE\t(uart_intr_handler = 0x40105170);\nPROVIDE\t(uart0_set_tout = 0x40105294);\nPROVIDE\t(uart_tx_buf = 0x401052e0);\nPROVIDE\t(uart_task = 0x40105338);\nPROVIDE\t(uart_del_rx_chars = 0x4010537c);\nPROVIDE\t(tcp2uart_send_rxbuf = 0x401053ec);\nPROVIDE\t(tcp2uart_send_tx_buf = 0x40105454);\nPROVIDE\t(GPIO_intr_handler = 0x4010549c);\nPROVIDE\t(Swapws = 0x401054c0);\nPROVIDE\t(MdbWordR = 0x401054e0);\nPROVIDE\t(MdbWordRW = 0x4010550c);\nPROVIDE\t(__ashrdi3 = 0x40105588);\nPROVIDE\t(__modsi3 = 0x401055a0);\nPROVIDE\t(__lshrdi3 = 0x401055ec);\nPROVIDE\t(eraminfo = 0x40105604);\nPROVIDE\t(_etext = 0x4010560c);\nPROVIDE\t(_lit4_start = 0x4010560c);\nPROVIDE\t(_text_end = 0x4010560c);\nPROVIDE\t(check_timeouts_timer = 0x4010560c);\nPROVIDE\t(lwip_if_queues = 0x40105620);\nPROVIDE\t(hostname = 0x40105628);\nPROVIDE\t(xBlockAllocatedBit = 0x4010562c);\nPROVIDE\t(xFreeBytesRemaining = 0x40105630);\nPROVIDE\t(pxEnd = 0x40105634);\nPROVIDE\t(netif_default = 0x40105638);\nPROVIDE\t(netif_list = 0x4010563c);\nPROVIDE\t(raw_pcbs = 0x40105640);\nPROVIDE\t(flash_size = 0x40105644);\nPROVIDE\t(flash_read = 0x40105648);\nPROVIDE\t(tcp_tmp_pcb = 0x4010564c);\nPROVIDE\t(tcp_tw_pcbs = 0x40105650);\nPROVIDE\t(tcp_active_pcbs = 0x40105654);\nPROVIDE\t(tcp_bound_pcbs = 0x40105658);\nPROVIDE\t(tcp_ticks = 0x4010565c);\nPROVIDE\t(tcp_input_pcb = 0x40105660);\nPROVIDE\t(recv_data = 0x40105664);\nPROVIDE\t(ackno = 0x40105668);\nPROVIDE\t(tcphdr = 0x4010566c);\nPROVIDE\t(tcpip_tcp_timer_active = 0x40105670);\nPROVIDE\t(timeouts_last_time = 0x40105674);\nPROVIDE\t(next_timeout = 0x40105678);\nPROVIDE\t(udp_pcbs = 0x4010567c);\nPROVIDE\t(dhcps_lease_time = 0x40105680);\nPROVIDE\t(renew = 0x40105684);\nPROVIDE\t(plist = 0x40105688);\nPROVIDE\t(dhcps_lease_flag = 0x4010568c);\nPROVIDE\t(pcb_dhcps = 0x40105690);\nPROVIDE\t(dns_payload = 0x40105694);\nPROVIDE\t(dns_pcb = 0x40105698);\nPROVIDE\t(igmp_group_list = 0x4010569c);\nPROVIDE\t(buf_scan_infos = 0x401056a0);\nPROVIDE\t(total_scan_infos = 0x40105e20);\nPROVIDE\t(flg_wifi_sleep_enable = 0x40105e24);\nPROVIDE\t(st_disconn_timer = 0x40105e28);\nPROVIDE\t(flg_sleep = 0x40105e3c);\nPROVIDE\t(st_reconn_flg = 0x40105e40);\nPROVIDE\t(st_reconn_count = 0x40105e44);\nPROVIDE\t(flg_open_all_service = 0x40105e48);\nPROVIDE\t(probe_requests_count = 0x40105e4c);\nPROVIDE\t(buf_probe_requests = 0x40105e50);\nPROVIDE\t(sntp = 0x40106050);\nPROVIDE\t(pcb_cdns = 0x40106054);\nPROVIDE\t(uart_drv = 0x40106058);\nPROVIDE\t(tcp2uart_servcfg = 0x40106088);\nPROVIDE\t(tcp2uart_conn = 0x4010608c);\nPROVIDE\t(numFiles = 0x40106090);\nPROVIDE\t(fatCacheID = 0x40106094);\nPROVIDE\t(WEBFSStubs = 0x40106098);\nPROVIDE\t(isWEBFSLocked = 0x40106218);\nPROVIDE\t(disk_base_addr = 0x4010621c);\nPROVIDE\t(phcfg = 0x40106220);\nPROVIDE\t(ovl_call = 0x40106224);\nPROVIDE\t(lock_sntp_time = 0x40106228);\nPROVIDE\t(mdb_mactime = 0x4010622c);\nPROVIDE\t(ret_funcs = 0x40106234);\nPROVIDE\t(arg_funcs = 0x40106238);\nPROVIDE\t(gpio_fun_pin_num = 0x4010623c);\nPROVIDE\t(mdbiosize = 0x40106240);\nPROVIDE\t(mdb_tcp_conn = 0x40106244);\nPROVIDE\t(mdb_tcp_servcfg = 0x40106248);\nPROVIDE\t(wdrv_bufn = 0x4010624c);\nPROVIDE\t(_lit4_end = 0x40106250);\nPROVIDE\t(_irom0_text_start = 0x40207000);\nPROVIDE\t(puts_buf = 0x40207004);\nPROVIDE\t(read_wifi_config = 0x40207048);\nPROVIDE\t(uart_wait_tx_fifo_empty = 0x402070e8);\nPROVIDE\t(read_macaddr_from_otp = 0x40207104);\nPROVIDE\t(tst_cfg_wifi = 0x40207170);\nPROVIDE\t(startup_uart_init = 0x40207290);\nPROVIDE\t(init_wifi = 0x40207304);\nPROVIDE\t(startup = 0x40207450);\nPROVIDE\t(init_fn = 0x40207734);\nPROVIDE\t(eagle_lwip_if_alloc = 0x40207780);\nPROVIDE\t(eagle_lwip_getif = 0x402078f8);\nPROVIDE\t(task_if0 = 0x40207918);\nPROVIDE\t(task_if1 = 0x40207950);\nPROVIDE\t(eagle_lwip_if_free = 0x40207988);\nPROVIDE\t(free_entry = 0x402079e0);\nPROVIDE\t(find_entry = 0x40207a3c);\nPROVIDE\t(etharp_send_ip = 0x40207b18);\nPROVIDE\t(update_arp_entry = 0x40207b6c);\nPROVIDE\t(etharp_tmr = 0x40207c10);\nPROVIDE\t(etharp_find_addr = 0x40207c68);\nPROVIDE\t(etharp_request = 0x40207cbc);\nPROVIDE\t(etharp_output_to_arp_index = 0x40207d8c);\nPROVIDE\t(etharp_query = 0x40207e04);\nPROVIDE\t(etharp_output = 0x40207fb4);\nPROVIDE\t(ethernet_input = 0x402080a4);\nPROVIDE\t(etharp_cleanup_netif = 0x402082a0);\nPROVIDE\t(ieee80211_rate_ref_init = 0x40208368);\nPROVIDE\t(ieee80211_freedom_inside_cb = 0x40208380);\nPROVIDE\t(ieee80211_freedom_init = 0x402083b0);\nPROVIDE\t(ieee80211_user_ie_init = 0x402083d4);\nPROVIDE\t(ieee80211_ifattach = 0x402083f0);\nPROVIDE\t(ieee80211_mhz2ieee = 0x40208458);\nPROVIDE\t(ieee80211_chan2ieee = 0x402084b8);\nPROVIDE\t(ieee80211_ieee2mhz = 0x402084d4);\nPROVIDE\t(ieee80211_find_channel = 0x40208514);\nPROVIDE\t(ieee80211_find_channel_byieee = 0x40208540);\nPROVIDE\t(wifi_mode_set = 0x40208594);\nPROVIDE\t(get_iav_key = 0x40208770);\nPROVIDE\t(register_ieee80211_action_vendor_get_key_cb = 0x40208790);\nPROVIDE\t(unregister_ieee80211_action_vendor_get_key_cb = 0x402087a4);\nPROVIDE\t(ieee80211_add_action_vendor_spec_esp = 0x402087bc);\nPROVIDE\t(ieee80211_alloc_action_vendor_spec = 0x40208804);\nPROVIDE\t(ieee80211_send_action_vendor_spec = 0x40208914);\nPROVIDE\t(ieee80211_recv_action_vendor_spec = 0x40208aac);\nPROVIDE\t(ieee80211_action_vendor_spec_attach = 0x40208bb8);\nPROVIDE\t(register_ieee80211_action_vendor_spec_cb = 0x40208bf8);\nPROVIDE\t(unregister_ieee80211_action_vendor_spec_cb = 0x40208c0c);\nPROVIDE\t(ieee80211_crypto_attach = 0x40208c18);\nPROVIDE\t(ieee80211_crypto_available = 0x40208c1c);\nPROVIDE\t(ieee80211_crypto_setkey = 0x40208c20);\nPROVIDE\t(ieee80211_crypto_encap = 0x40208c24);\nPROVIDE\t(ieee80211_crypto_decap = 0x40208c7c);\nPROVIDE\t(ieee80211_getmgtframe = 0x40208cec);\nPROVIDE\t(ieee80211_hostap_attach = 0x40209390);\nPROVIDE\t(hostap_handle_timer = 0x40209494);\nPROVIDE\t(hostap_input = 0x4020952c);\nPROVIDE\t(wifi_softap_start = 0x4020a4ac);\nPROVIDE\t(wifi_softap_stop = 0x4020a618);\nPROVIDE\t(ieee80211_ht_attach = 0x4020a7c0);\nPROVIDE\t(ieee80211_ht_node_init = 0x4020a814);\nPROVIDE\t(ieee80211_ht_node_cleanup = 0x4020a854);\nPROVIDE\t(ieee80211_parse_htcap = 0x4020a88c);\nPROVIDE\t(ieee80211_ht_updateparams = 0x4020a98c);\nPROVIDE\t(ieee80211_setup_htrates = 0x4020aaa4);\nPROVIDE\t(ieee80211_setup_basic_htrates = 0x4020ab70);\nPROVIDE\t(ieee80211_add_htcap = 0x4020aebc);\nPROVIDE\t(ieee80211_add_htcap_vendor = 0x4020aed8);\nPROVIDE\t(ieee80211_add_htinfo = 0x4020affc);\nPROVIDE\t(ieee80211_add_htinfo_vendor = 0x4020b018);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_head = 0x4020b258);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_mesh_assoc = 0x4020b290);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_mesh_group = 0x4020b314);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_simple_pair = 0x4020b344);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_freq_annon = 0x4020b394);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_now = 0x4020b3cc);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_ssid = 0x4020b404);\nPROVIDE\t(ieee80211_add_ie_vendor_esp_manufacturer = 0x4020b444);\nPROVIDE\t(ieee80211_deliver_data = 0x4020b494);\nPROVIDE\t(ieee80211_decap = 0x4020b4e8);\nPROVIDE\t(ieee80211_setup_rates = 0x4020b5ec);\nPROVIDE\t(ieee80211_alloc_challenge = 0x4020b65c);\nPROVIDE\t(ieee80211_parse_beacon = 0x4020b698);\nPROVIDE\t(ieee80211_parse_wpa = 0x4020bc6c);\nPROVIDE\t(ieee80211_parse_rsn = 0x4020bd80);\nPROVIDE\t(ieee80211_parse_action = 0x4020be80);\nPROVIDE\t(ieee80211_setup_rateset = 0x4020bf1c);\nPROVIDE\t(ieee80211_mesh_quick_init = 0x4020bf2c);\nPROVIDE\t(ieee80211_mesh_quick_deinit = 0x4020bf9c);\nPROVIDE\t(ieee80211_mesh_quick_set = 0x4020bfcc);\nPROVIDE\t(ieee80211_mesh_quick_get = 0x4020c0c8);\nPROVIDE\t(ieee80211_mesh_quick_ie_add = 0x4020c194);\nPROVIDE\t(ieee80211_output_pbuf = 0x4020c1cc);\nPROVIDE\t(ieee80211_send_setup = 0x4020c43c);\nPROVIDE\t(ieee80211_mgmt_output = 0x4020c570);\nPROVIDE\t(ieee80211_tx_mgt_cb = 0x4020c654);\nPROVIDE\t(ieee80211_send_nulldata = 0x4020c65c);\nPROVIDE\t(ieee80211_add_rates = 0x4020cac8);\nPROVIDE\t(ieee80211_add_xrates = 0x4020cb18);\nPROVIDE\t(ieee80211_send_probereq = 0x4020cbe8);\nPROVIDE\t(ieee80211_getcapinfo = 0x4020cdfc);\nPROVIDE\t(ieee80211_send_mgmt = 0x4020ce5c);\nPROVIDE\t(ieee80211_alloc_proberesp = 0x4020d40c);\nPROVIDE\t(ieee80211_send_proberesp = 0x4020d5e8);\nPROVIDE\t(ieee80211_alloc_deauth = 0x4020d730);\nPROVIDE\t(ieee80211_send_deauth = 0x4020d770);\nPROVIDE\t(ieee80211_freedom_output = 0x4020d8ac);\nPROVIDE\t(ieee80211_beacon_alloc = 0x4020dc9c);\nPROVIDE\t(ieee80211_phy_init = 0x4020de34);\nPROVIDE\t(ieee80211_phy_type_get = 0x4020de68);\nPROVIDE\t(ieee80211_setup_ratetable = 0x4020de84);\nPROVIDE\t(ieee80211_psq_init = 0x4020df14);\nPROVIDE\t(ieee80211_psq_cleanup = 0x4020df34);\nPROVIDE\t(ieee80211_set_tim = 0x4020df3c);\nPROVIDE\t(ieee80211_pwrsave = 0x4020df7c);\nPROVIDE\t(pwrsave_flushq = 0x4020dfe4);\nPROVIDE\t(ieee80211_node_pwrsave = 0x4020e094);\nPROVIDE\t(ieee80211_proto_attach = 0x4020e0d0);\nPROVIDE\t(ieee80211_set_shortslottime = 0x4020e0f8);\nPROVIDE\t(ieee80211_iserp_rateset = 0x4020e114);\nPROVIDE\t(ieee80211_wme_initparams = 0x4020e148);\nPROVIDE\t(ieee80211_wme_updateparams = 0x4020e14c);\nPROVIDE\t(ieee80211_mlme_connect_bss = 0x4020e154);\nPROVIDE\t(ieee80211_rfid_locp_recv_open = 0x4020e1d4);\nPROVIDE\t(ieee80211_rfid_locp_recv_close = 0x4020e210);\nPROVIDE\t(ieee80211_rfid_locp_recv_reset = 0x4020e228);\nPROVIDE\t(ieee80211_rfid_locp_recv = 0x4020e248);\nPROVIDE\t(register_ieee80211_rfid_locp_recv_cb = 0x4020e264);\nPROVIDE\t(unregister_ieee80211_rfid_locp_recv_cb = 0x4020e278);\nPROVIDE\t(ieee80211_scan_attach = 0x4020e290);\nPROVIDE\t(scan_start = 0x4020e324);\nPROVIDE\t(scan_pm_channel_op_cb = 0x4020e4e4);\nPROVIDE\t(scan_cancel = 0x4020e684);\nPROVIDE\t(scan_add_bssid = 0x4020e7e0);\nPROVIDE\t(scan_remove_bssid = 0x4020e804);\nPROVIDE\t(scan_hidden_ssid = 0x4020e810);\nPROVIDE\t(scan_add_probe_ssid = 0x4020e818);\nPROVIDE\t(scan_remove_probe_ssid = 0x4020e86c);\nPROVIDE\t(scan_clear_channles = 0x4020e9ac);\nPROVIDE\t(scan_set_desChan = 0x4020ea20);\nPROVIDE\t(scan_get_type = 0x4020ea2c);\nPROVIDE\t(cannel_scan_connect_state = 0x4020ea34);\nPROVIDE\t(scan_connect_state = 0x4020ea4c);\nPROVIDE\t(scan_check_hidden = 0x4020ea94);\nPROVIDE\t(scan_profile_check = 0x4020eac8);\nPROVIDE\t(scan_parse_beacon = 0x4020ee74);\nPROVIDE\t(sta_status_set = 0x4020f244);\nPROVIDE\t(ieee80211_sta_new_state = 0x4020f2b0);\nPROVIDE\t(sta_input = 0x4020f640);\nPROVIDE\t(ieee80211_parse_wmeparams = 0x4020fb8c);\nPROVIDE\t(wifi_station_start = 0x40210188);\nPROVIDE\t(wifi_station_stop = 0x402101f8);\nPROVIDE\t(ic_get_addr = 0x40210254);\nPROVIDE\t(ic_set_opmode = 0x40210260);\nPROVIDE\t(ic_enable_interface = 0x40210274);\nPROVIDE\t(ic_interface_enabled = 0x402102c4);\nPROVIDE\t(ic_disable_interface = 0x402102d8);\nPROVIDE\t(ic_is_pure_sta = 0x40210320);\nPROVIDE\t(ic_get_ptk_alg = 0x4021033c);\nPROVIDE\t(ic_get_gtk_alg = 0x4021034c);\nPROVIDE\t(ic_set_ptk_alg = 0x4021035c);\nPROVIDE\t(ic_set_gtk_alg = 0x4021036c);\nPROVIDE\t(ic_interface_is_p2p = 0x4021037c);\nPROVIDE\t(ic_set_vif = 0x40210414);\nPROVIDE\t(ic_set_sta = 0x402104d4);\nPROVIDE\t(ic_bss_info_update = 0x402105ac);\nPROVIDE\t(ic_set_key = 0x40210608);\nPROVIDE\t(ic_remove_key = 0x40210664);\nPROVIDE\t(ic_get_rssi = 0x40210678);\nPROVIDE\t(lwip_init = 0x402106b4);\nPROVIDE\t(ip_route = 0x402106f4);\nPROVIDE\t(ip_input = 0x4021077c);\nPROVIDE\t(ip_output_if_opt = 0x402109dc);\nPROVIDE\t(ip_output_if = 0x40210bf0);\nPROVIDE\t(ip_output = 0x40210c18);\nPROVIDE\t(ip_router = 0x40210c68);\nPROVIDE\t(ip4_addr_isbroadcast = 0x40210cc4);\nPROVIDE\t(ip4_addr_netmask_valid = 0x40210d04);\nPROVIDE\t(ipaddr_aton = 0x40210d50);\nPROVIDE\t(ipaddr_addr = 0x40210f3c);\nPROVIDE\t(ipaddr_ntoa_r = 0x40210f58);\nPROVIDE\t(ipaddr_ntoa = 0x4021102c);\nPROVIDE\t(lmacInitAc = 0x40211044);\nPROVIDE\t(lmacInit = 0x40211078);\nPROVIDE\t(lmacSetRetryLimit = 0x40211128);\nPROVIDE\t(prvHeapInit = 0x40211160);\nPROVIDE\t(netif_init = 0x402111a0);\nPROVIDE\t(netif_find = 0x402111a4);\nPROVIDE\t(netif_set_default = 0x402111dc);\nPROVIDE\t(netif_set_ipaddr = 0x402111ec);\nPROVIDE\t(netif_set_addr = 0x40211258);\nPROVIDE\t(netif_add = 0x40211290);\nPROVIDE\t(netif_set_netmask = 0x40211300);\nPROVIDE\t(netif_set_gw = 0x4021130c);\nPROVIDE\t(netif_set_up = 0x40211318);\nPROVIDE\t(netif_set_down = 0x40211354);\nPROVIDE\t(netif_remove = 0x40211374);\nPROVIDE\t(netif_set_link_up = 0x402113d8);\nPROVIDE\t(netif_set_link_down = 0x40211424);\nPROVIDE\t(_sprintf_out = 0x4021143c);\nPROVIDE\t(__wrap_os_printf_plus = 0x4021147c);\nPROVIDE\t(ets_sprintf = 0x402114e0);\nPROVIDE\t(pbuf_header = 0x4021152c);\nPROVIDE\t(pbuf_ref = 0x402115bc);\nPROVIDE\t(pbuf_free = 0x402115c8);\nPROVIDE\t(pbuf_alloc = 0x4021162c);\nPROVIDE\t(pbuf_realloc = 0x40211790);\nPROVIDE\t(pbuf_clen = 0x402117e0);\nPROVIDE\t(pbuf_cat = 0x402117f4);\nPROVIDE\t(pbuf_chain = 0x40211820);\nPROVIDE\t(pbuf_dechain = 0x4021183c);\nPROVIDE\t(pbuf_copy = 0x40211870);\nPROVIDE\t(pbuf_copy_partial = 0x4021193c);\nPROVIDE\t(pbuf_take = 0x402119ec);\nPROVIDE\t(pbuf_coalesce = 0x40211a68);\nPROVIDE\t(pbuf_get_at = 0x40211aa8);\nPROVIDE\t(pbuf_memcmp = 0x40211acc);\nPROVIDE\t(pbuf_memfind = 0x40211b40);\nPROVIDE\t(pbuf_strstr = 0x40211ba4);\nPROVIDE\t(rf_init = 0x40211bf0);\nPROVIDE\t(bb_init = 0x40211c0c);\nPROVIDE\t(phy_init = 0x40211c24);\nPROVIDE\t(RFChannelSel = 0x40211c54);\nPROVIDE\t(phy_delete_channel = 0x40211c70);\nPROVIDE\t(phy_enable_agc = 0x40211c88);\nPROVIDE\t(phy_disable_agc = 0x40211ca0);\nPROVIDE\t(phy_initialize_bb = 0x40211cb8);\nPROVIDE\t(phy_set_sense = 0x40211cd0);\nPROVIDE\t(ram_tx_mac_enable = 0x40211ce8);\nPROVIDE\t(ram_tx_mac_disable = 0x40211cec);\nPROVIDE\t(rtc_mem_backup = 0x40211cf0);\nPROVIDE\t(rtc_mem_recovery = 0x40211d20);\nPROVIDE\t(set_cal_rxdc = 0x40211d54);\nPROVIDE\t(set_rx_gain_cal_iq = 0x40211e0c);\nPROVIDE\t(gen_rx_gain_table = 0x40212164);\nPROVIDE\t(pbus_set_rxbbgain = 0x402122bc);\nPROVIDE\t(set_rx_gain_testchip_50 = 0x40212340);\nPROVIDE\t(ram_get_corr_power = 0x40212678);\nPROVIDE\t(check_data_func = 0x40212768);\nPROVIDE\t(do_noisefloor_lsleep_v50 = 0x40212788);\nPROVIDE\t(do_noisefloor = 0x402127bc);\nPROVIDE\t(start_dig_rx = 0x40212830);\nPROVIDE\t(stop_dig_rx = 0x40212878);\nPROVIDE\t(chip_v6_set_chanfreq = 0x402128a4);\nPROVIDE\t(tx_cap_init = 0x402128d8);\nPROVIDE\t(target_power_add_backoff = 0x40212ac4);\nPROVIDE\t(tx_pwctrl_init_cal = 0x40212af4);\nPROVIDE\t(tx_atten_set_interp = 0x40212c6c);\nPROVIDE\t(check_tx_pwr_cal = 0x40212ecc);\nPROVIDE\t(tx_pwctrl_init = 0x40213010);\nPROVIDE\t(ram_get_noisefloor = 0x40213134);\nPROVIDE\t(get_noisefloor_sat = 0x40213150);\nPROVIDE\t(ram_set_noise_floor = 0x40213180);\nPROVIDE\t(ram_start_noisefloor = 0x402131dc);\nPROVIDE\t(read_hw_noisefloor = 0x40213228);\nPROVIDE\t(noise_check_loop = 0x40213254);\nPROVIDE\t(noise_init = 0x402133ac);\nPROVIDE\t(target_power_backoff = 0x402135ac);\nPROVIDE\t(sdt_on_noise_start = 0x40213600);\nPROVIDE\t(chip_v6_set_chan_rx_cmp = 0x40213680);\nPROVIDE\t(chip_v6_set_chan_misc = 0x4021380c);\nPROVIDE\t(phy_dig_spur_set = 0x402138b0);\nPROVIDE\t(phy_dig_spur_prot = 0x40213c08);\nPROVIDE\t(chip_v6_rxmax_ext_dig = 0x40213e40);\nPROVIDE\t(chip_v6_rxmax_ext = 0x40213e8c);\nPROVIDE\t(phy_bb_rx_cfg = 0x40213f38);\nPROVIDE\t(uart_wait_idle = 0x40214350);\nPROVIDE\t(phy_pbus_soc_cfg = 0x4021438c);\nPROVIDE\t(phy_gpio_cfg = 0x40214444);\nPROVIDE\t(tx_cont_en = 0x4021465c);\nPROVIDE\t(tx_cont_dis = 0x40214704);\nPROVIDE\t(tx_cont_cfg = 0x40214758);\nPROVIDE\t(chip_v6_initialize_bb = 0x4021477c);\nPROVIDE\t(periodic_cal = 0x402148e4);\nPROVIDE\t(bbpll_cal = 0x402149c8);\nPROVIDE\t(periodic_cal_top = 0x40214a60);\nPROVIDE\t(register_chipv6_phy_init_param = 0x40214ac0);\nPROVIDE\t(change_bbpll160_sleep = 0x40214d6c);\nPROVIDE\t(change_bbpll160 = 0x40214f1c);\nPROVIDE\t(set_crystal_uart = 0x40214f54);\nPROVIDE\t(ant_switch_init = 0x40214fe4);\nPROVIDE\t(reduce_current_init = 0x40215094);\nPROVIDE\t(rtc_mem_check = 0x40215180);\nPROVIDE\t(phy_afterwake_set_rfoption = 0x402151bc);\nPROVIDE\t(deep_sleep_set_option = 0x402151dc);\nPROVIDE\t(write_data_to_rtc = 0x40215208);\nPROVIDE\t(get_data_from_rtc = 0x40215240);\nPROVIDE\t(register_chipv6_phy = 0x402152d4);\nPROVIDE\t(set_dpd_bypass = 0x40215770);\nPROVIDE\t(set_rf_gain_stage10 = 0x40215798);\nPROVIDE\t(get_vdd33_offset = 0x402157c8);\nPROVIDE\t(get_phy_target_power = 0x4021583c);\nPROVIDE\t(set_most_pwr_reg = 0x402158f0);\nPROVIDE\t(phy_set_most_tpw = 0x402159c4);\nPROVIDE\t(phy_vdd33_set_tpw = 0x402159e4);\nPROVIDE\t(get_adc_rand = 0x402159fc);\nPROVIDE\t(phy_get_rand = 0x40215a2c);\nPROVIDE\t(phy_tx_pwctrl_cali = 0x40215a44);\nPROVIDE\t(phy_check_data_table = 0x40215a6c);\nPROVIDE\t(phy_after_init_enrx = 0x40215aac);\nPROVIDE\t(phy_set_rx11b_reg = 0x40215b10);\nPROVIDE\t(phy_set_powerup_option = 0x40215b44);\nPROVIDE\t(phy_get_txpwr_param = 0x40215b54);\nPROVIDE\t(phy_get_rxnf_param = 0x40215ba0);\nPROVIDE\t(phy_get_freq_param = 0x40215bac);\nPROVIDE\t(ram_pbus_set_rxgain = 0x40215bc0);\nPROVIDE\t(ram_pbus_debugmode = 0x40215c88);\nPROVIDE\t(ram_pbus_xpd_tx_on = 0x40215d3c);\nPROVIDE\t(set_rf_freq_offset = 0x40215da8);\nPROVIDE\t(chip_v6_rxmax_ext_ana = 0x40215e18);\nPROVIDE\t(ram_chip_v6_rx_init = 0x40215f6c);\nPROVIDE\t(tsen_meas = 0x40215f9c);\nPROVIDE\t(readvdd33 = 0x40216048);\nPROVIDE\t(txpwr_offset = 0x40216210);\nPROVIDE\t(set_txcap_reg = 0x402162cc);\nPROVIDE\t(ram_ana_inf_gating_en = 0x4021634c);\nPROVIDE\t(ram_restart_cal = 0x402164ac);\nPROVIDE\t(wait_rfpll_cal_end = 0x40216518);\nPROVIDE\t(ram_rfpll_set_freq = 0x402165a0);\nPROVIDE\t(ram_set_channel_freq = 0x402166a4);\nPROVIDE\t(chip_60_set_channel = 0x4021699c);\nPROVIDE\t(chip_v6_set_chan_offset = 0x40216b3c);\nPROVIDE\t(chip_v6_set_chan = 0x40216b94);\nPROVIDE\t(chip_v6_set_chan_wakeup = 0x40216c38);\nPROVIDE\t(chip_v6_rf_init = 0x40216cac);\nPROVIDE\t(low_power_set = 0x40216f10);\nPROVIDE\t(test_tout = 0x40216f60);\nPROVIDE\t(check_data_flag = 0x402170d8);\nPROVIDE\t(phy_get_check_flag = 0x402170f8);\nPROVIDE\t(phy_get_vdd33 = 0x4021722c);\nPROVIDE\t(txbbgain2dcoindex = 0x402172e0);\nPROVIDE\t(dcoindex2txbbgain = 0x40217300);\nPROVIDE\t(init_cal_dcoffset = 0x40217324);\nPROVIDE\t(set_rfanagain_dc_reg = 0x402173e8);\nPROVIDE\t(set_txdc_pbus = 0x40217484);\nPROVIDE\t(get_rf_gain_qdb = 0x402174f0);\nPROVIDE\t(correct_rf_ana_gain = 0x40217518);\nPROVIDE\t(get_sar_dout = 0x40217620);\nPROVIDE\t(cal_rf_ana_gain = 0x402176ac);\nPROVIDE\t(meas_tone_pwr_db = 0x402177d8);\nPROVIDE\t(tx_pwr_backoff = 0x40217848);\nPROVIDE\t(get_fcc_1m2m_pwr_offset = 0x402179d0);\nPROVIDE\t(ram_set_txbb_atten = 0x40217a0c);\nPROVIDE\t(txiq_get_mis_pwr = 0x40217aa0);\nPROVIDE\t(txiq_cover = 0x40217b44);\nPROVIDE\t(ram_rfcal_txiq = 0x40217d5c);\nPROVIDE\t(rc_cal = 0x40217fc8);\nPROVIDE\t(get_target_power_offset = 0x40218188);\nPROVIDE\t(get_pwctrl_correct = 0x40218290);\nPROVIDE\t(tx_pwctrl_cal = 0x402182e8);\nPROVIDE\t(tx_pwctrl_bg_init = 0x402185e4);\nPROVIDE\t(tx_pwctrl_background = 0x4021865c);\nPROVIDE\t(read_sar_dout = 0x40218718);\nPROVIDE\t(ram_get_fm_sar_dout = 0x4021877c);\nPROVIDE\t(ram_cal_tos_v60 = 0x40218820);\nPROVIDE\t(ram_get_bb_atten = 0x402189f0);\nPROVIDE\t(ram_rfcal_txcap = 0x40218a20);\nPROVIDE\t(ram_rfcal_pwrctrl = 0x40218be4);\nPROVIDE\t(ram_rxiq_get_mis = 0x40218e0c);\nPROVIDE\t(ram_rxiq_cover_mg_mp = 0x40218fd8);\nPROVIDE\t(ram_rfcal_rxiq = 0x4021917c);\nPROVIDE\t(dpd_scale_set = 0x40219388);\nPROVIDE\t(dpd_mem_write = 0x402193d0);\nPROVIDE\t(pm_usec2rtc = 0x4021944c);\nPROVIDE\t(pm_rtc2usec = 0x40219480);\nPROVIDE\t(pm_set_sleep_cycles = 0x4021948c);\nPROVIDE\t(pm_sleep_opt = 0x402194b0);\nPROVIDE\t(pm_wakeup_opt = 0x402195f4);\nPROVIDE\t(get_chip_version = 0x4021962c);\nPROVIDE\t(pm_sleep_opt_bb_off = 0x4021966c);\nPROVIDE\t(pm_sleep_opt_bb_on = 0x402196ac);\nPROVIDE\t(pm_set_pll_xtal_wait_time = 0x402196f4);\nPROVIDE\t(pm_prepare_to_sleep = 0x40219720);\nPROVIDE\t(pm_sdio_nidle = 0x40219728);\nPROVIDE\t(chg_lslp_mem_opt_8266 = 0x4021979c);\nPROVIDE\t(pm_goto_sleep = 0x402197cc);\nPROVIDE\t(pm_wait4wakeup = 0x40219918);\nPROVIDE\t(pm_open_rf = 0x40219954);\nPROVIDE\t(pm_sleep_set_mac = 0x40219998);\nPROVIDE\t(pm_set_wakeup_mac = 0x40219a1c);\nPROVIDE\t(pm_check_mac_idle = 0x40219ab4);\nPROVIDE\t(pm_set_sleep_btco = 0x40219b0c);\nPROVIDE\t(pm_set_wakeup_btco = 0x40219bac);\nPROVIDE\t(pm_set_sleep_mode = 0x40219cc4);\nPROVIDE\t(pm_unmask_bt = 0x40219de0);\nPROVIDE\t(pm_wakeup_init = 0x40219e48);\nPROVIDE\t(sleep_opt_8266 = 0x4021a088);\nPROVIDE\t(sleep_opt_bb_on_8266 = 0x4021a0a8);\nPROVIDE\t(sleep_reset_analog_rtcreg_8266 = 0x4021a0e4);\nPROVIDE\t(pm_rtc_clock_cali_proc = 0x4021a1f0);\nPROVIDE\t(pm_get_ck170_period = 0x4021a228);\nPROVIDE\t(pm_set_sleep_time = 0x4021a24c);\nPROVIDE\t(pm_rf_is_closed = 0x4021a5d8);\nPROVIDE\t(pm_set_sleep_type_from_upper = 0x4021a604);\nPROVIDE\t(pm_get_sleep_type = 0x4021a6f4);\nPROVIDE\t(uart_tx_flush = 0x4021a8b0);\nPROVIDE\t(pm_suspend = 0x4021a8b4);\nPROVIDE\t(pm_shutdown = 0x4021aacc);\nPROVIDE\t(pm_reset_idle_sleep = 0x4021ab94);\nPROVIDE\t(pm_idle_sleep = 0x4021abd4);\nPROVIDE\t(pm_open = 0x4021abe0);\nPROVIDE\t(pm_onBcnRx = 0x4021acc0);\nPROVIDE\t(StopLightSleepSetFunc = 0x4021b058);\nPROVIDE\t(LightSleepWakedCbSetFunc = 0x4021b060);\nPROVIDE\t(pm_enable_gpio_wakeup = 0x4021b61c);\nPROVIDE\t(pm_attach = 0x4021b654);\nPROVIDE\t(pm_send_nullfunc = 0x4021b73c);\nPROVIDE\t(pm_is_waked = 0x4021b8e0);\nPROVIDE\t(pm_is_open = 0x4021b8f8);\nPROVIDE\t(pm_scan_lock = 0x4021b910);\nPROVIDE\t(pm_try_scan_unlock = 0x4021b938);\nPROVIDE\t(pm_force_scan_unlock = 0x4021b950);\nPROVIDE\t(pm_scan_unlocked = 0x4021b9f4);\nPROVIDE\t(pm_allow_tx = 0x4021ba08);\nPROVIDE\t(pm_assoc_parse = 0x4021ba24);\nPROVIDE\t(pm_set_addr = 0x4021ba3c);\nPROVIDE\t(pm_sleep_for = 0x4021ba5c);\nPROVIDE\t(pm_post = 0x4021ba8c);\nPROVIDE\t(pm_get_idle_wait_time = 0x4021bb90);\nPROVIDE\t(fpm_set_type_from_upper = 0x4021bbe8);\nPROVIDE\t(wifi_fpm_set_sleep_type = 0x4021bbe8);\nPROVIDE\t(fpm_get_slp_type = 0x4021bca4);\nPROVIDE\t(wifi_fpm_get_sleep_type = 0x4021bca4);\nPROVIDE\t(fpm_rf_is_closed = 0x4021bcac);\nPROVIDE\t(fpm_is_open = 0x4021bcc0);\nPROVIDE\t(fpm_allow_tx = 0x4021bccc);\nPROVIDE\t(fpm_close = 0x4021bcf0);\nPROVIDE\t(wifi_fpm_close = 0x4021bcf0);\nPROVIDE\t(fpm_open = 0x4021bd6c);\nPROVIDE\t(wifi_fpm_open = 0x4021bd6c);\nPROVIDE\t(fpm_attach = 0x4021bdd4);\nPROVIDE\t(fpm_set_wakeup_cb = 0x4021bfb8);\nPROVIDE\t(wifi_fpm_set_wakeup_cb = 0x4021bfb8);\nPROVIDE\t(fpm_do_wakeup = 0x4021c0fc);\nPROVIDE\t(wifi_fpm_do_wakeup = 0x4021c0fc);\nPROVIDE\t(fpm_do_sleep = 0x4021c630);\nPROVIDE\t(wifi_fpm_do_sleep = 0x4021c630);\nPROVIDE\t(fpm_auto_sleep_set_in_null_mode = 0x4021c6d0);\nPROVIDE\t(wifi_fpm_auto_sleep_set_in_null_mode = 0x4021c6d0);\nPROVIDE\t(get_fpm_auto_sleep_flag = 0x4021c710);\nPROVIDE\t(PPWdtReset = 0x4021c724);\nPROVIDE\t(pp_soft_wdt_init = 0x4021c758);\nPROVIDE\t(pp_soft_wdt_feed = 0x4021c778);\nPROVIDE\t(system_soft_wdt_feed = 0x4021c778);\nPROVIDE\t(pp_soft_wdt_stop = 0x4021c794);\nPROVIDE\t(system_soft_wdt_stop = 0x4021c794);\nPROVIDE\t(pp_soft_wdt_restart = 0x4021c7c0);\nPROVIDE\t(system_soft_wdt_restart = 0x4021c7c0);\nPROVIDE\t(RxNodeNum = 0x4021c7f8);\nPROVIDE\t(TxNodeNum = 0x4021c810);\nPROVIDE\t(pp_disable_noise_timer = 0x4021c834);\nPROVIDE\t(pp_enable_noise_timer = 0x4021c854);\nPROVIDE\t(pp_noise_test = 0x4021c964);\nPROVIDE\t(reset_noise_timer = 0x4021c974);\nPROVIDE\t(pp_disable_idle_timer = 0x4021c9ac);\nPROVIDE\t(pp_enable_idle_timer = 0x4021c9d0);\nPROVIDE\t(pp_try_enable_idle_timer = 0x4021c9f8);\nPROVIDE\t(ppPeocessRxPktHdr = 0x4021ca34);\nPROVIDE\t(HdlAllBuffedEb = 0x4021cd68);\nPROVIDE\t(ppTxPkt = 0x4021cdf0);\nPROVIDE\t(ppProcessWaitQ = 0x4021cf68);\nPROVIDE\t(ppRegisterTxCallback = 0x4021cf78);\nPROVIDE\t(ppUnregisterTxCallback = 0x4021cfa0);\nPROVIDE\t(ppRecycleRxPkt = 0x4021cfd4);\nPROVIDE\t(ppCheckTxIdle = 0x4021d034);\nPROVIDE\t(pp_tx_idle_timeout = 0x4021d2ac);\nPROVIDE\t(DefFreqCalTimerCB = 0x4021d46c);\nPROVIDE\t(ppGetTxQFirstAvail_Locked = 0x4021d7e0);\nPROVIDE\t(pp_attach = 0x4021d8bc);\nPROVIDE\t(RC_SetBasicRate = 0x4021df10);\nPROVIDE\t(raw_new = 0x4021df60);\nPROVIDE\t(raw_remove = 0x4021dfa8);\nPROVIDE\t(raw_bind = 0x4021dfdc);\nPROVIDE\t(raw_connect = 0x4021dfe8);\nPROVIDE\t(raw_recv = 0x4021dff4);\nPROVIDE\t(raw_sendto = 0x4021dffc);\nPROVIDE\t(raw_input = 0x4021e0a0);\nPROVIDE\t(raw_send = 0x4021e124);\nPROVIDE\t(iram_buf_init = 0x4021e14c);\nPROVIDE\t(spi_flash_real_size = 0x4021e1a8);\nPROVIDE\t(tcp_arg = 0x4021e20c);\nPROVIDE\t(tcp_accept = 0x4021e210);\nPROVIDE\t(tcp_recv = 0x4021e214);\nPROVIDE\t(tcp_sent = 0x4021e21c);\nPROVIDE\t(tcp_poll = 0x4021e224);\nPROVIDE\t(tcp_err = 0x4021e22c);\nPROVIDE\t(tcp_bind = 0x4021e240);\nPROVIDE\t(tcp_listen_with_backlog = 0x4021e2e4);\nPROVIDE\t(tcp_setprio = 0x4021e3a8);\nPROVIDE\t(tcp_update_rcv_ann_wnd = 0x4021e3b0);\nPROVIDE\t(tcp_recved = 0x4021e3f8);\nPROVIDE\t(tcp_seg_free = 0x4021e448);\nPROVIDE\t(tcp_segs_free = 0x4021e470);\nPROVIDE\t(tcp_pcb_purge = 0x4021e490);\nPROVIDE\t(tcp_slowtmr = 0x4021e4ec);\nPROVIDE\t(tcp_pcb_remove = 0x4021e768);\nPROVIDE\t(tcp_close = 0x4021e7e0);\nPROVIDE\t(tcp_recv_null = 0x4021e808);\nPROVIDE\t(tcp_fasttmr = 0x4021e840);\nPROVIDE\t(tcp_tmr = 0x4021e8d4);\nPROVIDE\t(tcp_shutdown = 0x4021e8f8);\nPROVIDE\t(tcp_abandon = 0x4021e958);\nPROVIDE\t(tcp_abort = 0x4021e9e8);\nPROVIDE\t(tcp_next_iss = 0x4021ea00);\nPROVIDE\t(tcp_alloc = 0x4021ea20);\nPROVIDE\t(tcp_new = 0x4021eb44);\nPROVIDE\t(tcp_eff_send_mss = 0x4021eb58);\nPROVIDE\t(tcp_connect = 0x4021eb8c);\nPROVIDE\t(tcp_receive = 0x4021ecbc);\nPROVIDE\t(tcp_input = 0x4021f248);\nPROVIDE\t(tcp_create_segment = 0x4021fbd4);\nPROVIDE\t(tcp_write = 0x4021fdc4);\nPROVIDE\t(tcp_send_empty_ack = 0x402200d4);\nPROVIDE\t(tcp_rexmit = 0x40220164);\nPROVIDE\t(tcp_rexmit_fast = 0x4022021c);\nPROVIDE\t(tcp_enqueue_flags = 0x40220280);\nPROVIDE\t(tcp_send_fin = 0x4022034c);\nPROVIDE\t(tcp_rst = 0x40220398);\nPROVIDE\t(tcp_keepalive = 0x402204cc);\nPROVIDE\t(tcp_zero_window_probe = 0x4022054c);\nPROVIDE\t(tcp_output = 0x4022065c);\nPROVIDE\t(tcp_rexmit_rto = 0x40220a84);\nPROVIDE\t(sys_timeout = 0x40220b0c);\nPROVIDE\t(sys_timeouts_init = 0x40220bb0);\nPROVIDE\t(tcpip_tcp_timer = 0x40220c20);\nPROVIDE\t(arp_timer = 0x40220c54);\nPROVIDE\t(sys_untimeout = 0x40220c70);\nPROVIDE\t(sys_check_timeouts = 0x40220cc4);\nPROVIDE\t(sys_restart_timeouts = 0x40220d40);\nPROVIDE\t(tcp_timer_needed = 0x40220d4c);\nPROVIDE\t(phytype2mode = 0x40220d7c);\nPROVIDE\t(rc_set_rate_limit_id = 0x40220d98);\nPROVIDE\t(rcUpdatePhyMode = 0x40220eb4);\nPROVIDE\t(rcAttach = 0x40221080);\nPROVIDE\t(rcGetTrc = 0x402210cc);\nPROVIDE\t(trc_onDisconnect = 0x402210d4);\nPROVIDE\t(trc_onScanStart = 0x402210d8);\nPROVIDE\t(trc_onScanDone = 0x402210ec);\nPROVIDE\t(rc_enable_trc = 0x40221108);\nPROVIDE\t(rc_get_mask = 0x402211e0);\nPROVIDE\t(rc_disable_trc = 0x402211f4);\nPROVIDE\t(rc_disable_trc_by_interface = 0x40221248);\nPROVIDE\t(rc_get_sta_trc = 0x40221264);\nPROVIDE\t(rc_get_trc = 0x402212a8);\nPROVIDE\t(rc_get_trc_by_index = 0x40221318);\nPROVIDE\t(rc_only_sta_trc = 0x40221338);\nPROVIDE\t(udp_new = 0x40221368);\nPROVIDE\t(udp_remove = 0x4022139c);\nPROVIDE\t(udp_bind = 0x402213d4);\nPROVIDE\t(udp_connect = 0x40221478);\nPROVIDE\t(udp_disconnect = 0x402214e0);\nPROVIDE\t(udp_recv = 0x402214f4);\nPROVIDE\t(udp_sendto_if = 0x402214fc);\nPROVIDE\t(udp_sendto = 0x40221648);\nPROVIDE\t(udp_send = 0x40221694);\nPROVIDE\t(udp_input = 0x402216ac);\nPROVIDE\t(system_set_os_print = 0x402218ac);\nPROVIDE\t(system_get_os_print = 0x402218bc);\nPROVIDE\t(system_pp_recycle_rx_pkt = 0x40221a84);\nPROVIDE\t(system_adc_read = 0x40221a98);\nPROVIDE\t(system_adc_read_fast = 0x40221ad8);\nPROVIDE\t(system_get_vdd33 = 0x40221b38);\nPROVIDE\t(system_restart_hook = 0x40221b64);\nPROVIDE\t(system_restart_local = 0x40221b78);\nPROVIDE\t(system_restart = 0x40221c60);\nPROVIDE\t(system_restore = 0x40221cb8);\nPROVIDE\t(system_get_flash_size_map = 0x40221d20);\nPROVIDE\t(system_get_boot_version = 0x40221d40);\nPROVIDE\t(system_get_test_result = 0x40221d78);\nPROVIDE\t(system_get_userbin_addr = 0x40221d9c);\nPROVIDE\t(system_get_boot_mode = 0x40221e34);\nPROVIDE\t(system_restart_enhance = 0x40221e64);\nPROVIDE\t(system_upgrade_userbin_set = 0x40221f94);\nPROVIDE\t(system_upgrade_userbin_check = 0x40221fe0);\nPROVIDE\t(system_upgrade_flag_set = 0x40222020);\nPROVIDE\t(system_upgrade_flag_check = 0x40222034);\nPROVIDE\t(system_upgrade_reboot = 0x40222058);\nPROVIDE\t(system_deep_sleep_instant = 0x40222174);\nPROVIDE\t(system_deep_sleep = 0x40222314);\nPROVIDE\t(system_deep_sleep_set_option = 0x40222374);\nPROVIDE\t(system_phy_temperature_alert = 0x40222390);\nPROVIDE\t(system_phy_set_max_tpw = 0x402223a4);\nPROVIDE\t(system_phy_set_tpw_via_vdd33 = 0x402223b8);\nPROVIDE\t(system_phy_set_rfoption = 0x402223cc);\nPROVIDE\t(system_phy_set_powerup_option = 0x402223e0);\nPROVIDE\t(system_update_cpu_freq = 0x402223f4);\nPROVIDE\t(system_get_cpu_freq = 0x40222450);\nPROVIDE\t(system_overclock = 0x40222468);\nPROVIDE\t(system_restoreclock = 0x40222494);\nPROVIDE\t(system_timer_reinit = 0x402224c4);\nPROVIDE\t(system_relative_time = 0x402224dc);\nPROVIDE\t(system_station_got_ip_set = 0x402224f8);\nPROVIDE\t(system_print_meminfo = 0x40222624);\nPROVIDE\t(system_get_free_heap_size = 0x40222688);\nPROVIDE\t(system_get_chip_id = 0x4022269c);\nPROVIDE\t(system_rtc_clock_cali_proc = 0x402226c0);\nPROVIDE\t(system_get_rtc_time = 0x402226d4);\nPROVIDE\t(system_mktime = 0x402226e4);\nPROVIDE\t(system_init_done_cb = 0x402227b4);\nPROVIDE\t(system_get_rst_info = 0x402227bc);\nPROVIDE\t(system_get_data_of_array_8 = 0x402227c4);\nPROVIDE\t(system_get_data_of_array_16 = 0x402227e8);\nPROVIDE\t(system_get_string_from_flash = 0x40222810);\nPROVIDE\t(wifi_softap_dhcps_start = 0x4022287c);\nPROVIDE\t(wifi_softap_dhcps_stop = 0x402228c4);\nPROVIDE\t(wifi_softap_dhcps_status = 0x40222904);\nPROVIDE\t(wifi_station_dhcpc_start = 0x4022290c);\nPROVIDE\t(wifi_station_dhcpc_stop = 0x40222964);\nPROVIDE\t(wifi_station_dhcpc_event = 0x402229a4);\nPROVIDE\t(wifi_station_dhcpc_set_maxtry = 0x40222a18);\nPROVIDE\t(wifi_station_dhcpc_status = 0x40222a28);\nPROVIDE\t(wifi_get_opmode = 0x40222aa0);\nPROVIDE\t(wifi_get_opmode_default = 0x40222ab4);\nPROVIDE\t(wifi_get_broadcast_if = 0x40222b2c);\nPROVIDE\t(wifi_set_broadcast_if = 0x40222b68);\nPROVIDE\t(wifi_set_opmode = 0x40222cdc);\nPROVIDE\t(wifi_set_opmode_current = 0x40222cf0);\nPROVIDE\t(system_get_checksum = 0x40222d04);\nPROVIDE\t(wifi_param_save_protect_with_check = 0x40222d48);\nPROVIDE\t(system_param_save_with_protect = 0x40222e00);\nPROVIDE\t(system_save_sys_param = 0x40222ea8);\nPROVIDE\t(system_param_load = 0x40222ed4);\nPROVIDE\t(wifi_station_get_config = 0x4022300c);\nPROVIDE\t(wifi_station_get_config_default = 0x40223020);\nPROVIDE\t(wifi_station_get_ap_info = 0x40223040);\nPROVIDE\t(wifi_station_ap_number_set = 0x402230f8);\nPROVIDE\t(wifi_station_set_config = 0x40223484);\nPROVIDE\t(wifi_station_set_config_current = 0x4022349c);\nPROVIDE\t(wifi_station_restore_config = 0x402234b4);\nPROVIDE\t(wifi_station_get_current_ap_id = 0x402234cc);\nPROVIDE\t(wifi_station_ap_check = 0x402234e0);\nPROVIDE\t(wifi_station_ap_change = 0x40223520);\nPROVIDE\t(wifi_station_scan = 0x4022364c);\nPROVIDE\t(wifi_station_get_auto_connect = 0x40223698);\nPROVIDE\t(wifi_station_set_auto_connect = 0x402236ac);\nPROVIDE\t(wifi_station_save_pmk2cache = 0x402236fc);\nPROVIDE\t(wifi_station_connect = 0x402237ac);\nPROVIDE\t(wifi_station_disconnect = 0x40223840);\nPROVIDE\t(wifi_station_get_connect_status = 0x40223900);\nPROVIDE\t(wifi_station_set_reconnect_policy = 0x40223930);\nPROVIDE\t(wifi_station_get_reconnect_policy = 0x40223948);\nPROVIDE\t(wifi_station_get_rssi = 0x40223950);\nPROVIDE\t(wifi_station_set_default_hostname = 0x4022399c);\nPROVIDE\t(wifi_station_get_hostname = 0x40223a04);\nPROVIDE\t(wifi_station_set_hostname = 0x40223a30);\nPROVIDE\t(wifi_softap_cacl_mac = 0x40223acc);\nPROVIDE\t(wifi_softap_set_default_ssid = 0x40223b30);\nPROVIDE\t(wifi_softap_get_config = 0x40223d0c);\nPROVIDE\t(wifi_softap_get_config_default = 0x40223d20);\nPROVIDE\t(wifi_softap_set_config = 0x4022406c);\nPROVIDE\t(wifi_softap_set_config_current = 0x40224080);\nPROVIDE\t(wifi_softap_set_station_info = 0x40224094);\nPROVIDE\t(wifi_softap_get_station_info = 0x40224100);\nPROVIDE\t(wifi_softap_free_station_info = 0x402241b0);\nPROVIDE\t(wifi_softap_get_station_num = 0x402241f8);\nPROVIDE\t(wifi_softap_deauth = 0x40224248);\nPROVIDE\t(wifi_softap_get_beacon_only_mode = 0x402242f8);\nPROVIDE\t(wifi_softap_set_beacon_only_mode = 0x4022430c);\nPROVIDE\t(wifi_register_user_ie_manufacturer_recv_cb = 0x40224370);\nPROVIDE\t(wifi_unregister_user_ie_manufacturer_recv_cb = 0x40224384);\nPROVIDE\t(wifi_set_user_ie = 0x402243b4);\nPROVIDE\t(wifi_get_user_ie = 0x402244c4);\nPROVIDE\t(wifi_get_phy_mode = 0x402244f8);\nPROVIDE\t(wifi_set_phy_mode = 0x40224500);\nPROVIDE\t(wifi_set_sleep_type = 0x402245c8);\nPROVIDE\t(wifi_get_sleep_type = 0x402245e4);\nPROVIDE\t(wifi_get_channel = 0x402245f8);\nPROVIDE\t(wifi_set_channel = 0x40224610);\nPROVIDE\t(wifi_promiscuous_set_mac = 0x40224650);\nPROVIDE\t(wifi_promiscuous_enable = 0x402246ac);\nPROVIDE\t(wifi_set_promiscuous_rx_cb = 0x40224790);\nPROVIDE\t(wifi_get_ip_info = 0x4022479c);\nPROVIDE\t(wifi_set_ip_info = 0x4022481c);\nPROVIDE\t(wifi_get_macaddr = 0x40224890);\nPROVIDE\t(wifi_set_macaddr = 0x402248f0);\nPROVIDE\t(wifi_enable_6m_rate = 0x40224a0c);\nPROVIDE\t(wifi_get_user_fixed_rate = 0x40224a14);\nPROVIDE\t(wifi_set_user_fixed_rate = 0x40224a34);\nPROVIDE\t(wifi_set_user_sup_rate = 0x40224a54);\nPROVIDE\t(wifi_set_user_rate_limit = 0x40224a90);\nPROVIDE\t(wifi_get_user_limit_rate_mask = 0x40224ab4);\nPROVIDE\t(wifi_set_user_limit_rate_mask = 0x40224abc);\nPROVIDE\t(wifi_register_send_pkt_freedom_cb = 0x40224ad4);\nPROVIDE\t(wifi_unregister_send_pkt_freedom_cb = 0x40224ae8);\nPROVIDE\t(wifi_send_pkt_freedom = 0x40224af4);\nPROVIDE\t(wifi_rfid_locp_recv_open = 0x40224b40);\nPROVIDE\t(wifi_rfid_locp_recv_close = 0x40224b54);\nPROVIDE\t(wifi_register_rfid_locp_recv_cb = 0x40224b68);\nPROVIDE\t(wifi_unregister_rfid_locp_recv_cb = 0x40224b7c);\nPROVIDE\t(wifi_status_led_install = 0x40224b94);\nPROVIDE\t(wifi_status_led_uninstall = 0x40224bc8);\nPROVIDE\t(wifi_set_status_led_output_level = 0x40224bec);\nPROVIDE\t(wifi_set_event_handler_cb = 0x40224c40);\nPROVIDE\t(system_os_task = 0x40224c88);\nPROVIDE\t(system_uart_swap = 0x40224cc4);\nPROVIDE\t(system_uart_de_swap = 0x40224d28);\nPROVIDE\t(system_get_sdk_version = 0x40224d60);\nPROVIDE\t(wDev_Option_Init = 0x40224d74);\nPROVIDE\t(wDev_Enable_Beacon_Tsf = 0x40224e68);\nPROVIDE\t(wDev_Disable_Beacon_Tsf = 0x40224e84);\nPROVIDE\t(wDev_Set_Beacon_Int = 0x40224ea0);\nPROVIDE\t(wDev_Reset_TBTT = 0x40224ea8);\nPROVIDE\t(wDev_Get_Next_TBTT = 0x40224ed8);\nPROVIDE\t(wDev_Initialize = 0x40225154);\nPROVIDE\t(wDevForceAck6M = 0x402251c4);\nPROVIDE\t(wDev_SetMacAddress = 0x402251e0);\nPROVIDE\t(wDev_SetRxPolicy = 0x4022527c);\nPROVIDE\t(wDev_SetBssid = 0x402252d0);\nPROVIDE\t(wDev_ClearBssid = 0x402253a8);\nPROVIDE\t(wDev_Insert_KeyEntry = 0x402253e0);\nPROVIDE\t(wDev_remove_KeyEntry = 0x402254d4);\nPROVIDE\t(wDev_remove_KeyEntry_all_cnx = 0x40225510);\nPROVIDE\t(wDev_Crypto_Conf = 0x40225560);\nPROVIDE\t(wDev_Crypto_Disable = 0x402255fc);\nPROVIDE\t(wDevEnableRx = 0x40225634);\nPROVIDE\t(wdev_go_sniffer = 0x4022565c);\nPROVIDE\t(wdev_set_sniffer_addr = 0x40225738);\nPROVIDE\t(wdev_exit_sniffer = 0x40225790);\nPROVIDE\t(wdt_init = 0x40225860);\nPROVIDE\t(os_print_reset_error = 0x402258e4);\nPROVIDE\t(chm_init = 0x40225988);\nPROVIDE\t(chm_acquire_lock = 0x402259ec);\nPROVIDE\t(chm_release_lock = 0x40225a30);\nPROVIDE\t(chm_start_op = 0x40225a44);\nPROVIDE\t(chm_end_op = 0x40225ae8);\nPROVIDE\t(chm_cancel_op = 0x40225b30);\nPROVIDE\t(chm_return_home_channel = 0x40225b64);\nPROVIDE\t(chm_set_current_channel = 0x40225b94);\nPROVIDE\t(chm_freq2index = 0x40225bc4);\nPROVIDE\t(chm_check_same_channel = 0x40225bec);\nPROVIDE\t(cnx_attach = 0x40225c28);\nPROVIDE\t(cnx_sta_connect_led_timer_cb = 0x40225c68);\nPROVIDE\t(cnx_sta_connect_cmd = 0x40225cbc);\nPROVIDE\t(cnx_sta_scan_cmd = 0x40225d78);\nPROVIDE\t(cnx_connect_timeout = 0x40225fe0);\nPROVIDE\t(cnx_auth_timeout = 0x4022605c);\nPROVIDE\t(cnx_assoc_timeout = 0x40226080);\nPROVIDE\t(cnx_handshake_timeout = 0x402260a4);\nPROVIDE\t(cnx_start_handoff_cb = 0x402260e4);\nPROVIDE\t(cnx_bss_alloc = 0x40226554);\nPROVIDE\t(cnx_rc_search = 0x402265f4);\nPROVIDE\t(cnx_add_rc = 0x40226674);\nPROVIDE\t(cnx_remove_all_rc = 0x402266e0);\nPROVIDE\t(cnx_remove_rc = 0x4022672c);\nPROVIDE\t(cnx_rc_update_rssi = 0x402267fc);\nPROVIDE\t(cnx_rc_update_state_metric = 0x40226884);\nPROVIDE\t(cnx_rc_update_age = 0x402268f0);\nPROVIDE\t(cnx_update_bss = 0x40226914);\nPROVIDE\t(cnx_update_bss_more = 0x40226948);\nPROVIDE\t(cnx_sta_leave = 0x40226b24);\nPROVIDE\t(cnx_sta_associated = 0x40226db8);\nPROVIDE\t(cnx_node_alloc = 0x40226ec0);\nPROVIDE\t(cnx_node_remove = 0x40226f34);\nPROVIDE\t(cnx_node_search = 0x40226fc0);\nPROVIDE\t(cnx_node_leave = 0x4022703c);\nPROVIDE\t(wifi_softap_staconnected_event_policy = 0x4022713c);\nPROVIDE\t(wifi_softap_toomany_deny = 0x40227164);\nPROVIDE\t(cnx_node_join = 0x402271a0);\nPROVIDE\t(wpa_sm_rx_eapol = 0x40228388);\nPROVIDE\t(wpa_register = 0x40228500);\nPROVIDE\t(wpa_set_profile = 0x4022852c);\nPROVIDE\t(wpa_set_pmk = 0x40228544);\nPROVIDE\t(wpa_set_bss = 0x40228570);\nPROVIDE\t(pp_michael_mic_failure = 0x40228774);\nPROVIDE\t(eapol_txcb = 0x40228818);\nPROVIDE\t(wpa_sm_set_state = 0x402288a4);\nPROVIDE\t(wpa_auth_for_each_sta = 0x40228a18);\nPROVIDE\t(wpa_init = 0x40228b98);\nPROVIDE\t(wpa_auth_sta_init = 0x40228c28);\nPROVIDE\t(wpa_auth_sta_associated = 0x40228c70);\nPROVIDE\t(wpa_auth_sta_no_wpa = 0x40228cdc);\nPROVIDE\t(wpa_auth_sta_deinit = 0x40228d38);\nPROVIDE\t(wpa_receive = 0x40228e08);\nPROVIDE\t(__wpa_send_eapol = 0x40229268);\nPROVIDE\t(wpa_remove_ptk = 0x4022978c);\nPROVIDE\t(wpa_auth_sm_event = 0x402297d8);\nPROVIDE\t(wpa_write_rsn_ie = 0x4022a614);\nPROVIDE\t(wpa_auth_gen_wpa_ie = 0x4022a720);\nPROVIDE\t(wpa_add_kde = 0x4022a7b0);\nPROVIDE\t(wpa_validate_wpa_ie = 0x4022a81c);\nPROVIDE\t(wpa_parse_kde_ies = 0x4022aa28);\nPROVIDE\t(wpa_auth_uses_mfp = 0x4022aac4);\nPROVIDE\t(wpa_parse_wpa_ie_rsn = 0x4022ac1c);\nPROVIDE\t(wpa_parse_wpa_ie_wpa = 0x4022adb0);\nPROVIDE\t(wpa_eapol_key_mic = 0x4022af40);\nPROVIDE\t(wpa_compare_rsn_ie = 0x4022af80);\nPROVIDE\t(wpa_pmk_to_ptk = 0x4022afa8);\nPROVIDE\t(rsn_pmkid = 0x4022b098);\nPROVIDE\t(wpa_cipher_key_len = 0x4022b0f4);\nPROVIDE\t(wpa_cipher_to_alg = 0x4022b118);\nPROVIDE\t(wpa_cipher_to_suite = 0x4022b140);\nPROVIDE\t(rsn_cipher_put_suites = 0x4022b194);\nPROVIDE\t(wpa_cipher_put_suites = 0x4022b1f4);\nPROVIDE\t(wpa_parse_wpa_ie = 0x4022b240);\nPROVIDE\t(wpa_supplicant_parse_ies = 0x4022b334);\nPROVIDE\t(wpa_gen_wpa_ie = 0x4022b534);\nPROVIDE\t(ppInstallKey = 0x4022b56c);\nPROVIDE\t(wpa_config_profile = 0x4022b6fc);\nPROVIDE\t(wpa_config_bss = 0x4022b730);\nPROVIDE\t(wpa_config_assoc_ie = 0x4022b75c);\nPROVIDE\t(dhcp_bind_check = 0x4022b770);\nPROVIDE\t(eagle_auth_done = 0x4022b7a4);\nPROVIDE\t(wpa_neg_complete = 0x4022b920);\nPROVIDE\t(wpa_attach = 0x4022b948);\nPROVIDE\t(wpa_sm_alloc_eapol = 0x4022b9f0);\nPROVIDE\t(wpa_sm_deauthenticate = 0x4022ba30);\nPROVIDE\t(wpa_sm_mlme_setprotection = 0x4022ba4c);\nPROVIDE\t(wpa_sm_get_beacon_ie = 0x4022ba50);\nPROVIDE\t(wpa_sm_disassociate = 0x4022ba54);\nPROVIDE\t(aes_wrap = 0x4022ba58);\nPROVIDE\t(hostapd_config_defaults_bss = 0x4022bb3c);\nPROVIDE\t(hostapd_config_defaults = 0x4022bb88);\nPROVIDE\t(hostapd_mac_comp = 0x4022bc0c);\nPROVIDE\t(hostapd_mac_comp_empty = 0x4022bc20);\nPROVIDE\t(hostapd_setup_wpa_psk = 0x4022bc8c);\nPROVIDE\t(hostapd_wep_key_cmp = 0x4022bcbc);\nPROVIDE\t(hostapd_maclist_found = 0x4022bd0c);\nPROVIDE\t(hostapd_rate_found = 0x4022bd74);\nPROVIDE\t(hostapd_get_psk = 0x4022bd90);\nPROVIDE\t(inc_byte_array = 0x4022bde4);\nPROVIDE\t(hex2byte = 0x4022be38);\nPROVIDE\t(hexstr2bin = 0x4022be6c);\nPROVIDE\t(wpa_get_ntp_timestamp = 0x4022beb8);\nPROVIDE\t(wpa_config_parse_string = 0x4022bf50);\nPROVIDE\t(dup_binstr = 0x4022c054);\nPROVIDE\t(dhcp_set_state = 0x4022c09c);\nPROVIDE\t(dhcp_check = 0x4022c0b4);\nPROVIDE\t(dhcp_option = 0x4022c0f0);\nPROVIDE\t(dhcp_option_byte = 0x4022c110);\nPROVIDE\t(dhcp_option_short = 0x4022c124);\nPROVIDE\t(dhcp_option_long = 0x4022c148);\nPROVIDE\t(dhcp_create_msg = 0x4022c1a0);\nPROVIDE\t(dhcp_delete_msg = 0x4022c33c);\nPROVIDE\t(dhcp_bind = 0x4022c364);\nPROVIDE\t(dhcp_option_trailer = 0x4022c45c);\nPROVIDE\t(dhcp_reboot = 0x4022c494);\nPROVIDE\t(dhcp_rebind = 0x4022c564);\nPROVIDE\t(dhcp_select = 0x4022c640);\nPROVIDE\t(dhcp_discover = 0x4022c7e0);\nPROVIDE\t(dhcp_recv = 0x4022c92c);\nPROVIDE\t(dhcp_set_struct = 0x4022cf18);\nPROVIDE\t(dhcp_cleanup = 0x4022cf40);\nPROVIDE\t(dhcp_inform = 0x4022cf64);\nPROVIDE\t(dhcp_network_changed = 0x4022d010);\nPROVIDE\t(dhcp_arp_reply = 0x4022d058);\nPROVIDE\t(dhcp_renew = 0x4022d10c);\nPROVIDE\t(dhcp_coarse_tmr = 0x4022d1e8);\nPROVIDE\t(dhcp_release = 0x4022d27c);\nPROVIDE\t(dhcp_fine_tmr = 0x4022d344);\nPROVIDE\t(dhcp_stop = 0x4022d434);\nPROVIDE\t(dhcp_start = 0x4022d470);\nPROVIDE\t(create_msg = 0x4022d538);\nPROVIDE\t(add_offer_options = 0x4022d5f0);\nPROVIDE\t(node_insert_to_list = 0x4022d730);\nPROVIDE\t(node_remove_from_list = 0x4022d768);\nPROVIDE\t(handle_dhcp = 0x4022d7ac);\nPROVIDE\t(dhcps_start = 0x4022dc1c);\nPROVIDE\t(dhcps_stop = 0x4022dd00);\nPROVIDE\t(wifi_softap_set_dhcps_lease = 0x4022dd64);\nPROVIDE\t(wifi_softap_get_dhcps_lease = 0x4022dd88);\nPROVIDE\t(dhcps_coarse_tmr = 0x4022dda0);\nPROVIDE\t(wifi_softap_set_dhcps_offer_option = 0x4022de40);\nPROVIDE\t(wifi_softap_set_dhcps_lease_time = 0x4022de80);\nPROVIDE\t(wifi_softap_reset_dhcps_lease_time = 0x4022de90);\nPROVIDE\t(wifi_softap_get_dhcps_lease_time = 0x4022de9c);\nPROVIDE\t(dns_parse_name = 0x4022dea4);\nPROVIDE\t(dns_recv = 0x4022ded8);\nPROVIDE\t(dns_send = 0x4022e120);\nPROVIDE\t(dns_check_entry = 0x4022e230);\nPROVIDE\t(dns_setserver = 0x4022e30c);\nPROVIDE\t(dns_init = 0x4022e334);\nPROVIDE\t(dns_getserver = 0x4022e378);\nPROVIDE\t(dns_tmr = 0x4022e390);\nPROVIDE\t(dns_gethostbyname = 0x4022e3c0);\nPROVIDE\t(esf_buf_alloc = 0x4022e4e0);\nPROVIDE\t(esf_buf_recycle = 0x4022e6c8);\nPROVIDE\t(esf_buf_setup = 0x4022e808);\nPROVIDE\t(icmp_input = 0x4022e8c8);\nPROVIDE\t(icmp_dest_unreach = 0x4022ea50);\nPROVIDE\t(ieee80211_send_action_register = 0x4022eb08);\nPROVIDE\t(ieee80211_send_action_unregister = 0x4022eb3c);\nPROVIDE\t(ieee80211_send_action = 0x4022eb50);\nPROVIDE\t(ieee80211_recv_action_register = 0x4022ebbc);\nPROVIDE\t(ieee80211_recv_action_unregister = 0x4022ebf0);\nPROVIDE\t(ieee80211_recv_action = 0x4022ec04);\nPROVIDE\t(igmp_send = 0x4022efcc);\nPROVIDE\t(igmp_delaying_member = 0x4022f0b8);\nPROVIDE\t(igmp_init = 0x4022f15c);\nPROVIDE\t(igmp_stop = 0x4022f170);\nPROVIDE\t(igmp_report_groups = 0x4022f1d4);\nPROVIDE\t(igmp_lookfor_group = 0x4022f204);\nPROVIDE\t(igmp_start = 0x4022f220);\nPROVIDE\t(igmp_input = 0x4022f274);\nPROVIDE\t(igmp_joingroup = 0x4022f390);\nPROVIDE\t(igmp_leavegroup = 0x4022f458);\nPROVIDE\t(igmp_tmr = 0x4022f52c);\nPROVIDE\t(os_get_time = 0x4022f568);\nPROVIDE\t(r_rand = 0x4022f56c);\nPROVIDE\t(os_random = 0x4022f57c);\nPROVIDE\t(os_get_random = 0x4022f58c);\nPROVIDE\t(ets_strrchr = 0x4022f5d4);\nPROVIDE\t(rijndaelEncrypt = 0x4022f5f0);\nPROVIDE\t(aes_encrypt_init = 0x4022fa0c);\nPROVIDE\t(aes_encrypt = 0x4022fa60);\nPROVIDE\t(aes_encrypt_deinit = 0x4022fa78);\nPROVIDE\t(rijndaelKeySetupEnc = 0x4022faa8);\nPROVIDE\t(init_done_cb = 0x4022fdb0);\nPROVIDE\t(user_init = 0x4022fe0c);\nPROVIDE\t(Set_default_wificfg = 0x4022fef8);\nPROVIDE\t(wifi_read_fcfg = 0x40230074);\nPROVIDE\t(wifi_start_scan = 0x402300c0);\nPROVIDE\t(WiFi_go_to_sleep = 0x40230114);\nPROVIDE\t(WiFi_up_from_sleep = 0x40230148);\nPROVIDE\t(Read_WiFi_config = 0x4023017c);\nPROVIDE\t(wifi_save_fcfg = 0x40230330);\nPROVIDE\t(Set_WiFi = 0x40230368);\nPROVIDE\t(Cmp_WiFi_chg = 0x40230664);\nPROVIDE\t(Setup_WiFi = 0x402308c8);\nPROVIDE\t(print_wifi_config = 0x40230940);\nPROVIDE\t(New_WiFi_config = 0x40230ab0);\nPROVIDE\t(wifi_scan_cb = 0x40230b20);\nPROVIDE\t(get_addr_fobj = 0x40230c2c);\nPROVIDE\t(get_addr_fobj_save = 0x40230cc0);\nPROVIDE\t(get_addr_bscfg = 0x40230d3c);\nPROVIDE\t(flash_read_cfg = 0x40231058);\nPROVIDE\t(flash_save_cfg = 0x402310d8);\nPROVIDE\t(sys_write_cfg = 0x40231100);\nPROVIDE\t(new_tcp_client_url = 0x40231120);\nPROVIDE\t(read_tcp_client_url = 0x402311a0);\nPROVIDE\t(sys_read_cfg = 0x40231224);\nPROVIDE\t(read_user_const = 0x402312b4);\nPROVIDE\t(write_user_const = 0x402312ec);\nPROVIDE\t(station_connect_timer = 0x40231324);\nPROVIDE\t(station_reconnect_off = 0x40231378);\nPROVIDE\t(close_all_service = 0x402313a0);\nPROVIDE\t(open_all_service = 0x402313e8);\nPROVIDE\t(add_next_probe_requests = 0x402314b0);\nPROVIDE\t(wifi_handle_event_cb = 0x40231594);\nPROVIDE\t(ntp_time_update = 0x402317fc);\nPROVIDE\t(sntp_retry = 0x40231810);\nPROVIDE\t(sntp_recv = 0x40231854);\nPROVIDE\t(sntp_send_request = 0x40231940);\nPROVIDE\t(sntp_request = 0x402319ac);\nPROVIDE\t(sntp_dns_found = 0x40231a08);\nPROVIDE\t(sntp_inits = 0x40231a34);\nPROVIDE\t(sntp_close = 0x40231ac4);\nPROVIDE\t(get_sntp_time = 0x40231b0c);\nPROVIDE\t(_cdns_recv = 0x40231b98);\nPROVIDE\t(cdns_recv = 0x40231e18);\nPROVIDE\t(captdns_close = 0x40231eb4);\nPROVIDE\t(captdns_init = 0x40231eec);\nPROVIDE\t(netbios_recv = 0x40231f4c);\nPROVIDE\t(netbios_pcb = 0x40232160);\nPROVIDE\t(netbios_set_name = 0x40232180);\nPROVIDE\t(netbios_init = 0x402321e8);\nPROVIDE\t(netbios_off = 0x40232234);\nPROVIDE\t(web_fini = 0x40232274);\nPROVIDE\t(uart_save_fcfg = 0x40232488);\nPROVIDE\t(update_rts0 = 0x40232528);\nPROVIDE\t(update_mux_uart0 = 0x40232554);\nPROVIDE\t(uart0_set_flow = 0x40232618);\nPROVIDE\t(update_mux_txd1 = 0x40232670);\nPROVIDE\t(set_uartx_invx = 0x40232698);\nPROVIDE\t(uart_read_fcfg = 0x40232714);\nPROVIDE\t(uart_drv_close = 0x402327e0);\nPROVIDE\t(uarts_init = 0x40232844);\nPROVIDE\t(uart_drv_start = 0x402328b8);\nPROVIDE\t(tcp2uart_sent_cb = 0x4023291c);\nPROVIDE\t(tcp2uart_recv = 0x40232984);\nPROVIDE\t(tcp2uart_listen = 0x402329c4);\nPROVIDE\t(tcp2uart_disconnect = 0x40232a0c);\nPROVIDE\t(tcp2uart_close = 0x40232a24);\nPROVIDE\t(tcp2uart_start = 0x40232a64);\nPROVIDE\t(WEBFSClose = 0x40232bdc);\nPROVIDE\t(WEBFS_max_size = 0x40232c00);\nPROVIDE\t(WEBFS_curent_size = 0x40232c38);\nPROVIDE\t(WEBFS_base_addr = 0x40232c64);\nPROVIDE\t(WEBFSGetArray = 0x40232c8c);\nPROVIDE\t(WEBFSInit = 0x40232d2c);\nPROVIDE\t(GetFATRecord = 0x40232db8);\nPROVIDE\t(WEBFSOpen = 0x40232e30);\nPROVIDE\t(WEBFSGetFlags = 0x40232f40);\nPROVIDE\t(WEBFSGetSize = 0x40232f74);\nPROVIDE\t(WEBFSGetBytesRem = 0x40232fa4);\nPROVIDE\t(WEBFSGetStartAddr = 0x40232fc0);\nPROVIDE\t(WEBFSGetEndAddr = 0x40232ff0);\nPROVIDE\t(WEBFSSeek = 0x40233024);\nPROVIDE\t(WEBFSGetFilename = 0x402330d0);\nPROVIDE\t(WEBFSGetPosition = 0x40233128);\nPROVIDE\t(set_cpu_clk = 0x4023314c);\nPROVIDE\t(get_addr_gpiox_mux = 0x402331a0);\nPROVIDE\t(set_gpiox_mux_pull = 0x402331cc);\nPROVIDE\t(set_gpiox_mux_func = 0x402331f8);\nPROVIDE\t(set_gpiox_mux_func_ioport = 0x40233230);\nPROVIDE\t(set_gpiox_mux_func_default = 0x4023325c);\nPROVIDE\t(get_gpiox_mux = 0x40233288);\nPROVIDE\t(get_gpiox_mux_func = 0x402332a0);\nPROVIDE\t(test_pin_clr_wifi_config = 0x402332d8);\nPROVIDE\t(get_mac_time = 0x402333b0);\nPROVIDE\t(web_int_disconnect = 0x402333c8);\nPROVIDE\t(Close_web_conn = 0x4023341c);\nPROVIDE\t(webserver_disconnect = 0x40233470);\nPROVIDE\t(find_boundary = 0x402334b0);\nPROVIDE\t(web_inc_fp = 0x40233548);\nPROVIDE\t(webserver_init = 0x402335bc);\nPROVIDE\t(webserver_close = 0x40233650);\nPROVIDE\t(webserver_reinit = 0x4023367c);\nPROVIDE\t(web_inc_fopen = 0x402336c0);\nPROVIDE\t(web_inc_fclose = 0x40233754);\nPROVIDE\t(webserver_send_fdata = 0x402337f4);\nPROVIDE\t(webserver_sent_callback = 0x40233b7c);\nPROVIDE\t(web_trim_bufi = 0x40233c1c);\nPROVIDE\t(web_feee_bufi = 0x40233c84);\nPROVIDE\t(head_find_ctr = 0x40233cb8);\nPROVIDE\t(web_cdns_no_redir = 0x40233d30);\nPROVIDE\t(webserver_open_file = 0x40233e08);\nPROVIDE\t(web_print_headers = 0x40233ff0);\nPROVIDE\t(webserver_received_data = 0x402343d8);\nPROVIDE\t(tcpsrv_list_delete = 0x402354dc);\nPROVIDE\t(tcpsrv_client_reconnect = 0x40235584);\nPROVIDE\t(recv_trim_bufi = 0x40235650);\nPROVIDE\t(tcpsrv_server_sent = 0x40235778);\nPROVIDE\t(tcpsrv_print_remote_info = 0x402357d0);\nPROVIDE\t(tcpsrv_server_close = 0x40235810);\nPROVIDE\t(tcpsrv_int_sent_data = 0x40235904);\nPROVIDE\t(tcpsrv_server_poll = 0x402359f8);\nPROVIDE\t(tcpsrv_server_recv = 0x40235a74);\nPROVIDE\t(tcpsrv_connected = 0x40235b80);\nPROVIDE\t(tcpsrv_error = 0x40235c08);\nPROVIDE\t(tcpsrv_disconnect_calback_default = 0x40235c6c);\nPROVIDE\t(tcpsrv_listen_default = 0x40235c8c);\nPROVIDE\t(tcpsrv_sent_callback_default = 0x40235cac);\nPROVIDE\t(tcpsrv_received_data_default = 0x40235ccc);\nPROVIDE\t(tcpsrv_server_port2pcfg = 0x40235cf0);\nPROVIDE\t(tcpsrv_client_ip_port2conn = 0x40235d10);\nPROVIDE\t(tcpsrv_unrecved_win = 0x40235d38);\nPROVIDE\t(tcpsrv_init = 0x40235d7c);\nPROVIDE\t(tcpsrv_start = 0x40235e30);\nPROVIDE\t(tcpsrv_connected_default = 0x40235ecc);\nPROVIDE\t(find_tcp_pcb = 0x40235ee8);\nPROVIDE\t(tcpsrv_close_cb = 0x40235f34);\nPROVIDE\t(tcpsrv_client_connect = 0x40235ffc);\nPROVIDE\t(tcpsrv_client_start = 0x402360a0);\nPROVIDE\t(tcpsrv_disconnect = 0x4023613c);\nPROVIDE\t(tcpsrv_server_accept = 0x40236170);\nPROVIDE\t(tcpsrv_close = 0x402362ac);\nPROVIDE\t(tcpsrv_close_port = 0x40236364);\nPROVIDE\t(tcpsrv_close_all = 0x40236388);\nPROVIDE\t(web_hexdump = 0x402363cc);\nPROVIDE\t(web_modbus_xml = 0x40236558);\nPROVIDE\t(wifi_aps_xml = 0x4023661c);\nPROVIDE\t(web_wscan_xml = 0x40236784);\nPROVIDE\t(web_ProbeRequest_xml = 0x402368c0);\nPROVIDE\t(web_get_flash = 0x402369c0);\nPROVIDE\t(web_get_ram = 0x40236a34);\nPROVIDE\t(get_new_url = 0x40236aac);\nPROVIDE\t(web_int_callback = 0x40236e20);\nPROVIDE\t(ovl_loader = 0x40239244);\nPROVIDE\t(WebSocketAcceptKey = 0x40239364);\nPROVIDE\t(WebsocketMask = 0x402393f0);\nPROVIDE\t(WebsocketHead = 0x40239420);\nPROVIDE\t(WebsocketTxFrame = 0x40239578);\nPROVIDE\t(rom_atoi = 0x4023967c);\nPROVIDE\t(hextoul = 0x402396cc);\nPROVIDE\t(ahextoul = 0x4023971c);\nPROVIDE\t(cmpcpystr = 0x40239750);\nPROVIDE\t(web_strnstr = 0x402397e8);\nPROVIDE\t(base64decode = 0x40239858);\nPROVIDE\t(base64encode = 0x40239924);\nPROVIDE\t(strtomac = 0x402399f0);\nPROVIDE\t(urldecode = 0x40239a5c);\nPROVIDE\t(htmlcode = 0x40239b24);\nPROVIDE\t(print_hex_dump = 0x40239c6c);\nPROVIDE\t(str_array = 0x40239cb8);\nPROVIDE\t(str_array_w = 0x40239d3c);\nPROVIDE\t(str_array_b = 0x40239dc4);\nPROVIDE\t(word_to_lower_case = 0x40239e50);\nPROVIDE\t(copy_align4 = 0x40239e88);\nPROVIDE\t(go_deep_sleep = 0x40239f58);\nPROVIDE\t(reg_sct_bits = 0x40239f70);\nPROVIDE\t(web_int_vars = 0x4023a144);\nPROVIDE\t(websock_tx_frame = 0x4023b544);\nPROVIDE\t(websock_tx_close_err = 0x4023b588);\nPROVIDE\t(websock_rx_data = 0x4023b5e8);\nPROVIDE\t(rd_buf_sec_blk = 0x4023b98c);\nPROVIDE\t(wr_buf_sec_blk = 0x4023b9c4);\nPROVIDE\t(read_sys_const = 0x4023ba1c);\nPROVIDE\t(write_sys_const = 0x4023ba3c);\nPROVIDE\t(MdbGpioMux = 0x4023baa4);\nPROVIDE\t(MdbGpioPullUp = 0x4023baf0);\nPROVIDE\t(MdbGpioOd = 0x4023bb48);\nPROVIDE\t(MdbGetSntpTimeLw = 0x4023bba8);\nPROVIDE\t(MdbMacTime = 0x4023bbd8);\nPROVIDE\t(MdbUserFunc = 0x4023bc10);\nPROVIDE\t(MdbVcc = 0x4023bc60);\nPROVIDE\t(MdbAdc = 0x4023bca4);\nPROVIDE\t(MdbGpioFunc = 0x4023bcf4);\nPROVIDE\t(MdbOut55AA = 0x4023bd5c);\nPROVIDE\t(mbd_fini = 0x4023bd94);\nPROVIDE\t(SetMdbErr = 0x4023be10);\nPROVIDE\t(RdMdbData = 0x4023be40);\nPROVIDE\t(ReadMdbData = 0x4023bef8);\nPROVIDE\t(WrMdbData = 0x4023bf4c);\nPROVIDE\t(MdbFunc = 0x4023bfd0);\nPROVIDE\t(mdb_tcp_disconnect = 0x4023c1cc);\nPROVIDE\t(mdb_tcp_listen = 0x4023c1e4);\nPROVIDE\t(mdb_tcp_recv = 0x4023c204);\nPROVIDE\t(mdb_tcp_close = 0x4023c364);\nPROVIDE\t(mdb_tcp_start = 0x4023c39c);\nPROVIDE\t(sar_init = 0x4023c498);\nPROVIDE\t(sar_off = 0x4023c560);\nPROVIDE\t(read_adcs = 0x4023c5c4);\nPROVIDE\t(sigma_delta_setup = 0x4023c670);\nPROVIDE\t(sigma_delta_close = 0x4023c6c8);\nPROVIDE\t(set_sigma_duty_312KHz = 0x4023c718);\nPROVIDE\t(aFATAL_ERR_R6PHY = 0x4023c74c);\nPROVIDE\t(esp_init_data_default = 0x4023c7e0);\nPROVIDE\t(ieee80211_opcap = 0x4023c8c0);\nPROVIDE\t(ip_addr_broadcast = 0x4023cdf4);\nPROVIDE\t(ip_addr_any = 0x4023cdf8);\nPROVIDE\t(memp_sizes = 0x4023ce30);\nPROVIDE\t(chip_v6_set_sense = 0x4023d214);\nPROVIDE\t(chip_v6_unset_chanfreq = 0x4023d218);\nPROVIDE\t(bit_popcount = 0x4023d48c);\nPROVIDE\t(tcp_pcb_lists = 0x4023d4b0);\nPROVIDE\t(tcp_persist_backoff = 0x4023d4c0);\nPROVIDE\t(tcp_backoff = 0x4023d4c8);\nPROVIDE\t(default_ssid = 0x4023d540);\nPROVIDE\t(eloop_cancel_timeout = 0x4023dabc);\nPROVIDE\t(eloop_register_timeout = 0x4023dac0);\nPROVIDE\t(magic_cookie = 0x4023dbb4);\nPROVIDE\t(ccmp = 0x4023dbcc);\nPROVIDE\t(tkip = 0x4023dbe4);\nPROVIDE\t(wep = 0x4023dbfc);\nPROVIDE\t(lwip_standard_chksum = 0x4023dc14);\nPROVIDE\t(inet_chksum = 0x4023dc7c);\nPROVIDE\t(inet_chksum_pbuf = 0x4023dc98);\nPROVIDE\t(inet_chksum_pseudo = 0x4023dd04);\nPROVIDE\t(inet_chksum_pseudo_partial = 0x4023ddc4);\nPROVIDE\t(sysinifname = 0x4023dfb4);\nPROVIDE\t(wifi_st_password = 0x4023e224);\nPROVIDE\t(wifi_st_name = 0x4023e230);\nPROVIDE\t(wifi_ap_password = 0x4023e238);\nPROVIDE\t(wifi_ap_name = 0x4023e244);\nPROVIDE\t(sntp_server_addresses = 0x4023e47c);\nPROVIDE\t(httpHostNameLocal = 0x4023e4ec);\nPROVIDE\t(file_label = 0x4023e6e0);\nPROVIDE\t(sector_filename = 0x4023e6e8);\nPROVIDE\t(overlay_filename = 0x4023e6f0);\nPROVIDE\t(sysconst_filename = 0x4023e6f8);\nPROVIDE\t(disk_err3_filename = 0x4023e704);\nPROVIDE\t(disk_err2_filename = 0x4023e714);\nPROVIDE\t(disk_err1_filename = 0x4023e724);\nPROVIDE\t(disk_ok_filename = 0x4023e734);\nPROVIDE\t(crlf_end_boundary = 0x4023e744);\nPROVIDE\t(HTTPAccessControlAllowOrigin = 0x4023e9f8);\nPROVIDE\t(HTTPfserror = 0x4023ea1c);\nPROVIDE\t(HTTPdefault = 0x4023ea5c);\nPROVIDE\t(HTTPfsupload = 0x4023eaa8);\nPROVIDE\t(HTTPResponse = 0x4023eb88);\nPROVIDE\t(HTTPresponse_501_content = 0x4023ec58);\nPROVIDE\t(HTTPresponse_500_content = 0x4023ec8c);\nPROVIDE\t(HTTPresponse_418_content = 0x4023eca8);\nPROVIDE\t(HTTPresponse_414_content = 0x4023ecc0);\nPROVIDE\t(HTTPresponse_413_content = 0x4023ecf8);\nPROVIDE\t(HTTPresponse_411_content = 0x4023ed34);\nPROVIDE\t(HTTPresponse_404_content = 0x4023ed64);\nPROVIDE\t(HTTPresponse_401_content = 0x4023ed7c);\nPROVIDE\t(HTTPresponse_501_head = 0x4023eda4);\nPROVIDE\t(HTTPresponse_500_head = 0x4023edc8);\nPROVIDE\t(HTTPresponse_429_head = 0x4023ede0);\nPROVIDE\t(HTTPresponse_418_head = 0x4023ee04);\nPROVIDE\t(HTTPresponse_414_head = 0x4023ee14);\nPROVIDE\t(HTTPresponse_413_head = 0x4023ee2c);\nPROVIDE\t(HTTPresponse_411_head = 0x4023ee48);\nPROVIDE\t(HTTPresponse_404_head = 0x4023ee58);\nPROVIDE\t(HTTPresponse_401_head = 0x4023ee64);\nPROVIDE\t(HTTPresponse_400_head = 0x4023ee9c);\nPROVIDE\t(HTTPresponse_304_head = 0x4023eea8);\nPROVIDE\t(HTTPresponse_302_head = 0x4023eeb8);\nPROVIDE\t(HTTPresponse_200_head = 0x4023eec0);\nPROVIDE\t(ncsi_txt_fname = 0x4023eec4);\nPROVIDE\t(fsupload_fname = 0x4023eed0);\nPROVIDE\t(web_cgi_fname = 0x4023eedc);\nPROVIDE\t(http_default_file = 0x4023eee4);\nPROVIDE\t(txt_tcpsrv_out_of_mem = 0x4023f0bc);\nPROVIDE\t(txt_tcpsrv_already_initialized = 0x4023f0d4);\nPROVIDE\t(txt_tcpsrv_NULL_pointer = 0x4023f0f4);\nPROVIDE\t(WebSocketAddKey = 0x4023f364);\nPROVIDE\t(WebSocketHTTPOkKey = 0x4023f38c);\nPROVIDE\t(base64map = 0x4023f414);\nPROVIDE\t(txt_wspong = 0x4023f534);\nPROVIDE\t(txt_wsping = 0x4023f53c);\nPROVIDE\t(_irom0_text_end = 0x4023f5b4);\nPROVIDE\t(uart0_ = 0x60000000);\nPROVIDE\t(spi0_ = 0x60000200);\nPROVIDE\t(gpio_ = 0x60000300);\nPROVIDE\t(timer_ = 0x60000600);\nPROVIDE\t(rtc_ = 0x60000700);\nPROVIDE\t(iomux_ = 0x60000800);\nPROVIDE\t(wdt_ = 0x60000900);\nPROVIDE\t(sar_ = 0x60000d00);\nPROVIDE\t(uart1_ = 0x60000f00);\nPROVIDE\t(rtc_ram_ = 0x60001000);\nPROVIDE\t(rtc_mem_ = 0x60001100);\nPROVIDE\t(_memmap_cacheattr_unused_mask = 0xfffff00f);\nPROVIDE\t(_memmap_cacheattr_wb_strict = 0xfffff11f);\nPROVIDE\t(_memmap_cacheattr_wt_strict = 0xfffff11f);\nPROVIDE\t(_memmap_cacheattr_bp_strict = 0xfffff22f);\n>>>>>>> a15a387 update\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"7fd5d619806df5e5b9bdbd0cfe14580040ea3615","subject":"BaseTools GCC: drop GNU notes section from EFI image","message":"BaseTools GCC: drop GNU notes section from EFI image\n\nRecent versions of GNU ld automatically emit a .notes section into\nthe ELF binary containing a build id. Since this is an allocatable\nsection by default, it will be identified by GenFw as a section\nthat requires PE\/COFF conversion, which may cause sections to be\nmoved around unexpectedly.\n\nSo retain the section, but tag it as INFO, which tells the linker\nthat it should not be accounted for in the binary's memory layout.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org>\nAcked-by: Jordan Justen <a79006884ba9cf5f4f7fcbb92a15b208780d8c97@intel.com>\nReviewed-by: Liming Gao <6480311aeeb4b006862f6d13ebabddc03f51e507@intel.com>\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"BaseTools\/Scripts\/GccBase.lds","new_file":"BaseTools\/Scripts\/GccBase.lds","new_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are constant from the POV of the program,\r\n     * but most of its contents end up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     *\/\r\n    *:AutoGen.obj(.data .data.* .bss .bss.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/*\r\n   * Retain the GNU build id but in a non-allocatable section so GenFw\r\n   * does not copy it into the PE\/COFF image.\r\n   *\/\r\n  .build-id (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","old_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are constant from the POV of the program,\r\n     * but most of its contents end up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     *\/\r\n    *:AutoGen.obj(.data .data.* .bss .bss.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"7296a98d590514af1c39fa86ea209db245f8338d","subject":"forgot to add change to bluepill.lds","message":"forgot to add change to bluepill.lds\n","repos":"tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow,petewarden\/tensorflow,davidzchen\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,frreiss\/tensorflow-fred,frreiss\/tensorflow-fred,aam-at\/tensorflow,Intel-tensorflow\/tensorflow,sarvex\/tensorflow,freedomtan\/tensorflow,annarev\/tensorflow,cxxgtxy\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow,annarev\/tensorflow,annarev\/tensorflow,davidzchen\/tensorflow,Intel-tensorflow\/tensorflow,freedomtan\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,freedomtan\/tensorflow,petewarden\/tensorflow,Intel-tensorflow\/tensorflow,sarvex\/tensorflow,paolodedios\/tensorflow,davidzchen\/tensorflow,Intel-tensorflow\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-tensorflow\/tensorflow,gautam1858\/tensorflow,petewarden\/tensorflow,freedomtan\/tensorflow,Intel-Corporation\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,frreiss\/tensorflow-fred,petewarden\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,annarev\/tensorflow,frreiss\/tensorflow-fred,annarev\/tensorflow,paolodedios\/tensorflow,paolodedios\/tensorflow,gautam1858\/tensorflow,Intel-Corporation\/tensorflow,gautam1858\/tensorflow,freedomtan\/tensorflow,frreiss\/tensorflow-fred,yongtang\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,tensorflow\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow,paolodedios\/tensorflow,annarev\/tensorflow,frreiss\/tensorflow-fred,paolodedios\/tensorflow,annarev\/tensorflow,aam-at\/tensorflow,Intel-Corporation\/tensorflow,karllessard\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_tf_optimizer,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow,davidzchen\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,cxxgtxy\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,freedomtan\/tensorflow,cxxgtxy\/tensorflow,frreiss\/tensorflow-fred,sarvex\/tensorflow,frreiss\/tensorflow-fred,aam-at\/tensorflow,aam-at\/tensorflow,paolodedios\/tensorflow,annarev\/tensorflow,paolodedios\/tensorflow,yongtang\/tensorflow,Intel-tensorflow\/tensorflow,sarvex\/tensorflow,yongtang\/tensorflow,freedomtan\/tensorflow,petewarden\/tensorflow,annarev\/tensorflow,frreiss\/tensorflow-fred,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,frreiss\/tensorflow-fred,cxxgtxy\/tensorflow,aam-at\/tensorflow,freedomtan\/tensorflow,davidzchen\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,sarvex\/tensorflow,petewarden\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,paolodedios\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,aam-at\/tensorflow,karllessard\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,petewarden\/tensorflow,gautam1858\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,karllessard\/tensorflow,annarev\/tensorflow,Intel-Corporation\/tensorflow,frreiss\/tensorflow-fred,Intel-tensorflow\/tensorflow,davidzchen\/tensorflow,tensorflow\/tensorflow,yongtang\/tensorflow,yongtang\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-tensorflow\/tensorflow,karllessard\/tensorflow,freedomtan\/tensorflow,yongtang\/tensorflow,yongtang\/tensorflow,davidzchen\/tensorflow,cxxgtxy\/tensorflow,davidzchen\/tensorflow,paolodedios\/tensorflow,paolodedios\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,cxxgtxy\/tensorflow,gautam1858\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,davidzchen\/tensorflow,aam-at\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,gautam1858\/tensorflow,davidzchen\/tensorflow,karllessard\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,yongtang\/tensorflow,cxxgtxy\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,aam-at\/tensorflow,petewarden\/tensorflow,davidzchen\/tensorflow,karllessard\/tensorflow,davidzchen\/tensorflow,aam-at\/tensorflow,freedomtan\/tensorflow,Intel-Corporation\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow","old_file":"tensorflow\/lite\/micro\/tools\/make\/targets\/bluepill\/bluepill.lds","new_file":"tensorflow\/lite\/micro\/tools\/make\/targets\/bluepill\/bluepill.lds","new_contents":"\/* Copyright 2018 Google Inc. All Rights Reserved.\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n==============================================================================*\/\n\n\/* Copied and modified from:\n   https:\/\/github.com\/google\/stm32_bare_lib\/blob\/master\/stm32_linker_layout.lds\n\n   Modifications:\n    * increased the flash size to 512K and RAM to 256K. This far exceeds the\n      actual hardware but enables running the tests in the emulator.\n*\/\n\n\/*\n * 0x00000000 - 0x07ffffff - aliased to flash or sys memory depending on BOOT jumpers.\n * 0x08000000 - 0x080fffff - Flash.\n * 0x1ffff000 - 0x1ffff7ff - Boot firmware in system memory.\n * 0x1ffff800 - 0x1fffffff - Option bytes.\n * 0x20000000 - 0x2003ffff - SRAM.\n * 0x40000000 - 0x40023400 - Peripherals\n *\/\n\n\/* Define main entry point *\/\nENTRY(_main)\n\nMEMORY {\nRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K\nFLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K\n}\n\n\/* Compute where the stack ends rather than hard coding it *\/\n_ld_stack_end_addr = ORIGIN(RAM) + LENGTH(RAM);\n_ld_min_stack_size = 0x200;\n\nSECTIONS {\n\n\/* interrupt vector goes to top of flash *\/\n\n.interrupt_vector : {\n  . = ALIGN(4);\n  KEEP(*(.interrupt_vector))\n  . = ALIGN(4);\n} >FLASH\n\n\/* read only .text and .rodata go to flash *\/\n\n.text : {\n  . = ALIGN(4);\n  KEEP(*(.text.interrupt_handler))\n  *(.text*)\n} >FLASH\n\n.rodata : {\n  . = ALIGN(4);\n  *(.rodata*)\n  . = ALIGN(4);\n} >FLASH\n\n\/* read mwrite data needs to be stored in flash but copied to ram *\/\n.data : {\n  . = ALIGN(4);\n  _ld_data_load_dest_start = .; \/* export where to load from *\/\n  *(.data*)\n  . = ALIGN(4);\n  _ld_data_load_dest_stop = .; \/* export where to load from *\/\n} >RAM AT> FLASH\n_ld_data_load_source = LOADADDR(.data);\n\n\/* unitialized data section needs zero initialization *\/\n.bss :\n{\n  . = ALIGN(4);\n  _ld_bss_data_start = .;\n  *(.bss*)\n  . = ALIGN(4);\n  _ld_bss_data_stop = .;\n} >RAM\n\n._user_heap_stack :\n{\n  . = ALIGN(8);\n  . += _ld_min_stack_size;\n  PROVIDE(end = .);\n  . = ALIGN(8);\n} >RAM\n\n\/DISCARD\/ :\n{\n  libc.a (*)\n  libm.a (*)\n  libgcc.a (*)\n}\n\n}  \/* SECTIONS *\/\n","old_contents":"\/* Copyright 2018 Google Inc. All Rights Reserved.\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n    http:\/\/www.apache.org\/licenses\/LICENSE-2.0\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n==============================================================================*\/\n\n\/* Copied and modified from:\n   https:\/\/github.com\/google\/stm32_bare_lib\/blob\/master\/stm32_linker_layout.lds\n\n   Modifications:\n    * increased the flash size to 512K and RAM to 256K. This far exceeds the\n      actual hardware but enables running the tests in the emulator.\n*\/\n\n\/*\n * 0x00000000 - 0x07ffffff - aliased to flash or sys memory depending on BOOT jumpers.\n * 0x08000000 - 0x0807ffff - Flash.\n * 0x1ffff000 - 0x1ffff7ff - Boot firmware in system memory.\n * 0x1ffff800 - 0x1fffffff - Option bytes.\n * 0x20000000 - 0x2003ffff - SRAM.\n * 0x40000000 - 0x40023400 - Peripherals\n *\/\n\n\/* Define main entry point *\/\nENTRY(_main)\n\nMEMORY {\nRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K\nFLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K\n}\n\n\/* Compute where the stack ends rather than hard coding it *\/\n_ld_stack_end_addr = ORIGIN(RAM) + LENGTH(RAM);\n_ld_min_stack_size = 0x200;\n\nSECTIONS {\n\n\/* interrupt vector goes to top of flash *\/\n\n.interrupt_vector : {\n  . = ALIGN(4);\n  KEEP(*(.interrupt_vector))\n  . = ALIGN(4);\n} >FLASH\n\n\/* read only .text and .rodata go to flash *\/\n\n.text : {\n  . = ALIGN(4);\n  KEEP(*(.text.interrupt_handler))\n  *(.text*)\n} >FLASH\n\n.rodata : {\n  . = ALIGN(4);\n  *(.rodata*)\n  . = ALIGN(4);\n} >FLASH\n\n\/* read mwrite data needs to be stored in flash but copied to ram *\/\n.data : {\n  . = ALIGN(4);\n  _ld_data_load_dest_start = .; \/* export where to load from *\/\n  *(.data*)\n  . = ALIGN(4);\n  _ld_data_load_dest_stop = .; \/* export where to load from *\/\n} >RAM AT> FLASH\n_ld_data_load_source = LOADADDR(.data);\n\n\/* unitialized data section needs zero initialization *\/\n.bss :\n{\n  . = ALIGN(4);\n  _ld_bss_data_start = .;\n  *(.bss*)\n  . = ALIGN(4);\n  _ld_bss_data_stop = .;\n} >RAM\n\n._user_heap_stack :\n{\n  . = ALIGN(8);\n  . += _ld_min_stack_size;\n  PROVIDE(end = .);\n  . = ALIGN(8);\n} >RAM\n\n\/DISCARD\/ :\n{\n  libc.a (*)\n  libm.a (*)\n  libgcc.a (*)\n}\n\n}  \/* SECTIONS *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a292dea4963aebde53a551fa668b18172c13e59c","subject":"x86_64: Remove 16mb padding, page-align BSS","message":"x86_64: Remove 16mb padding, page-align BSS\n","repos":"ingve\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,hioa-cs\/IncludeOS,hioa-cs\/IncludeOS,ingve\/IncludeOS,AnnikaH\/IncludeOS,ingve\/IncludeOS,AnnikaH\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,alfred-bratterud\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,ingve\/IncludeOS,hioa-cs\/IncludeOS,ingve\/IncludeOS,hioa-cs\/IncludeOS,alfred-bratterud\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0xA00000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  .multiboot (_ELF_START_ + SIZEOF_HEADERS): {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n  PROVIDE( _TEXT_START_ = . );\n  .text (_TEXT_START_ ) :\n  {\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x10) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  .config ALIGN(0x8) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","old_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0xA00000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  .multiboot (_ELF_START_ + SIZEOF_HEADERS): {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n  PROVIDE( _TEXT_START_ = . );\n  .text (_TEXT_START_ ) :\n  {\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x10) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    *(.fini)\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  .config ALIGN(0x8) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/*\n   * XXX: We need this padding because in solo5 initialization some variables\n   * in the bss are set to non-zero values. So, without the padding the ELFs\n   * symbol table would get modified.\n   *\/\n  . += 0x1000000;\n\n  .bss :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cd96d007651c013c02db137008570c288b326702","subject":"Add readme","message":"Add readme\n","repos":"bakins\/stardust,bakins\/stardust,bakins\/stardust","old_file":"config.ld","new_file":"config.ld","new_contents":"file = 'lib'\nexamples = { 'examples' }\ndir = 'docs'\nreadme = \"README.md\"\n","old_contents":"file = 'lib'\nexamples = { 'examples' }\ndir = 'docs'\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"33b6d219de2216a9bcf7951dfad38aae9c65328e","subject":"[x86_64] Linker script exports VGA buffer location now This is for future improvement of arch-specific init process.","message":"[x86_64] Linker script exports VGA buffer location now\nThis is for future improvement of arch-specific init process.\n","repos":"hawkw\/sos-kernel,rachlmac\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .boot :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot))\n    }\n\n    .text :\n    {\n        *(.text .text.*)\n    }\n\n    .rodata : {\n       *(.rodata .rodata.*)\n    }\n\n    .data.rel.ro : {\n       *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n    }\n}\n","old_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(start)\n\nSECTIONS {\n    . = 0xb8000;\n    vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .boot :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot))\n    }\n\n    .text :\n    {\n        *(.text .text.*)\n    }\n\n    .rodata : {\n       *(.rodata .rodata.*)\n    }\n\n    .data.rel.ro : {\n       *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f762e31a3cfd635c5181de176ba3f294674c195f","subject":"bug length","message":"bug length\n","repos":"hirakuni45\/R8C,hirakuni45\/R8C,hirakuni45\/R8C","old_file":"M120AN\/m120an.ld","new_file":"M120AN\/m120an.ld","new_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x00300, LENGTH = 0x00400\n\tROM (r)  : ORIGIN = 0x08000, LENGTH = 0x07FD8\n\tEXT (r)  : ORIGIN = 0x10000, LENGTH = 0x08000\n\tVVEC (r) : ORIGIN = 0x0FED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0x0FFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0780;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  .exttext   :\n  {\n    *(.exttext .stub .exttext.* .gnu.linkonce.t.*)\n    KEEP (*(.exttext.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n  } > EXT =0\n\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x00300, LENGTH = 0x00400\n\tROM (r)  : ORIGIN = 0x08000, LENGTH = 0x07FD8\n\tEXT (r)  : ORIGIN = 0x10000, LENGTH = 0x17FFF\n\tVVEC (r) : ORIGIN = 0x0FED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0x0FFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0780;\n\t\t_isp_init = 0x0800;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  .exttext   :\n  {\n    *(.exttext .stub .exttext.* .gnu.linkonce.t.*)\n    KEEP (*(.exttext.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n  } > EXT =0\n\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"8190918f11f37521754189f40782549442ece89d","subject":"force reserved area in bootloader","message":"force reserved area in bootloader\n","repos":"dbitbox\/mcu,dbitbox\/mcu,dbitbox\/mcu,dbitbox\/mcu","old_file":"bootloader.ld","new_file":"bootloader.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n\trom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00007FE0\n\tram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x3000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .; \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n\trom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00008000\n\tram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x3000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .; \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0e3bc2863346819ebd3ba694d27e90a2e42fd2f4","subject":"arch: arm: cortex_r: linker.ld: Fix ROM section names","message":"arch: arm: cortex_r: linker.ld: Fix ROM section names\n\nThis commit fixes the improper naming of the ROM sections.\n\n1. Rename the first ROM section, which was previously named using the\n  `_TEXT_SECTION_NAME` definition, to `rom_start`, as this section does\n  not actually represent the text section.\n\n2. Rename the second ROM section, which was previously named\n  `_TEXT_SECTION_NAME_2` which supposedly refers to the definition of\n  the same name that does not exist, to `_TEXT_SECTION_NAME`. Note that\n  this is indeed the section that contains the text section from the\n  source image.\n\nSigned-off-by: Stephanos Ioannidis <dc76e9f0c0006e8f919e0c515c66dbba3982f785@stephanos.io>\n","repos":"finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_r\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_r\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM      (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    MPU_ALIGN(_image_rodata_end -_image_rom_start);\n    _image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        *(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n    } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM      (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    MPU_ALIGN(_image_rodata_end -_image_rom_start);\n    _image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        *(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n    } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"40bc0d2d333922ba236f3c256fc9a66fd86dead6","subject":"Revert \"hide symbols from statically linked stdlibc++\"","message":"Revert \"hide symbols from statically linked stdlibc++\"\n\nThis reverts commit 76f9a6e6ab51817272ce2b02f4de7e955485f4f9.\n","repos":"mapycz\/python-mapnik,mapycz\/python-mapnik","old_file":"debian\/mapnik.lds","new_file":"debian\/mapnik.lds","new_contents":"","old_contents":"{\n    global:\n        *mapnik*;\n        datasource_name;\n        on_plugin_load;\n        create;\n\n        \/* https:\/\/gcc.gnu.org\/bugzilla\/show_bug.cgi?id=82172 *\/\n        _ZNSs4_Rep20_S_empty_rep_storageE;\n\n    local: *;\n};\n\n\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"dd4fe70a6249b02b2f8a89b36be54aaaa1eed554","subject":"cpu\/riscv_common: add noinit section to ld script","message":"cpu\/riscv_common: add noinit section to ld script\n","repos":"miri64\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,miri64\/RIOT,miri64\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,ant9000\/RIOT","old_file":"cpu\/riscv_common\/ldscripts\/riscv_base.ld","new_file":"cpu\/riscv_common\/ldscripts\/riscv_base.ld","new_contents":"\/*\n * Copyright (C) 2017, 2019   Ken Rabold\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_riscv_common\n * @{\n *\n * @file\n * @brief           Common linker directives for the RISC-V CPU\n *\n * @author          Ken Rabold\n *\n * @}\n *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nPHDRS\n{\n  flash PT_LOAD;\n  ram_init PT_LOAD;\n  ram PT_NULL;\n  tls PT_TLS;\n}\n\nSECTIONS\n{\n  __stack_size     = DEFINED(__stack_size) ? __stack_size : 256;\n\n  \/* Populate information about rom size *\/\n  _srom = ORIGIN(flash);\n  _erom = ORIGIN(flash) + LENGTH(flash);\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash AT>flash :flash\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >flash AT>flash :flash\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >flash AT>flash :flash\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    KEEP (*(SORT(.roxfa.*)))\n  } >flash AT>flash :flash\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash AT>flash :flash\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash AT>flash :flash\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash AT>flash :flash\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash AT>flash :flash\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash AT>flash :flash\n\n  \/*\n   * TLS relocations are offsets relative to the address\n   * of the first TLS symbol. That means we just need to\n   * allocate them all together so that the TLS region\n   * is compact when allocated for each thread.\n   *\/\n\n  \/*\n   * TLS initialization data is loaded into ROM so that\n   * each thread can get its values initialized from there\n   * at startup\n   *\/\n  .tdata :\n  {\n       __tdata_start = .;\n      *(.tdata .tdata.* .gnu.linkonce.td.*)\n      __tdata_end = .;\n  } >flash AT>flash :tls\n  __tdata_source = LOADADDR(.tdata);\n  __tdata_size = SIZEOF(.tdata);\n\n  \/*\n   * TLS zeroed data is relocated as if it immediately followed\n   * the tdata values. However, the linker 'magically' erases the\n   * memory allocation so that no ROM is consumed by this\n   * section\n   *\/\n  .tbss :\n  {\n      *(.tbss .tbss.* .gnu.linkonce.tb.*)\n      *(.tcommon)\n      __tbss_end = .;\n  } >flash : tls\n  __tls_size = __tbss_end - __tdata_start;\n  __tbss_size = __tls_size - __tdata_size;\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash AT>flash :flash\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash :ram_init\n\n  .data          :\n  {\n    *(.ramfunc .ramfunc.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n    KEEP (*(SORT(.xfa.*)))\n  } >ram AT>flash :ram_init\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram AT>ram :ram\n\n  .noinit (NOLOAD) :\n  {\n      __noinit_begin__ = .;\n\n      *(.noinit .noinit.*)\n\n        . = ALIGN(4) ;\n      __noinit_end__ = .;\n  } >ram AT>ram :ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n  PROVIDE( _sheap = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _eheap = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram AT>ram :ram\n\n  .end_fw (NOLOAD) : ALIGN(4) {\n    _end_fw = . ;\n  } > flash\n}\n","old_contents":"\/*\n * Copyright (C) 2017, 2019   Ken Rabold\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_riscv_common\n * @{\n *\n * @file\n * @brief           Common linker directives for the RISC-V CPU\n *\n * @author          Ken Rabold\n *\n * @}\n *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nPHDRS\n{\n  flash PT_LOAD;\n  ram_init PT_LOAD;\n  ram PT_NULL;\n  tls PT_TLS;\n}\n\nSECTIONS\n{\n  __stack_size     = DEFINED(__stack_size) ? __stack_size : 256;\n\n  \/* Populate information about rom size *\/\n  _srom = ORIGIN(flash);\n  _erom = ORIGIN(flash) + LENGTH(flash);\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash AT>flash :flash\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >flash AT>flash :flash\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >flash AT>flash :flash\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    KEEP (*(SORT(.roxfa.*)))\n  } >flash AT>flash :flash\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash AT>flash :flash\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash AT>flash :flash\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash AT>flash :flash\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash AT>flash :flash\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash AT>flash :flash\n\n  \/*\n   * TLS relocations are offsets relative to the address\n   * of the first TLS symbol. That means we just need to\n   * allocate them all together so that the TLS region\n   * is compact when allocated for each thread.\n   *\/\n\n  \/*\n   * TLS initialization data is loaded into ROM so that\n   * each thread can get its values initialized from there\n   * at startup\n   *\/\n  .tdata :\n  {\n       __tdata_start = .;\n      *(.tdata .tdata.* .gnu.linkonce.td.*)\n      __tdata_end = .;\n  } >flash AT>flash :tls\n  __tdata_source = LOADADDR(.tdata);\n  __tdata_size = SIZEOF(.tdata);\n\n  \/*\n   * TLS zeroed data is relocated as if it immediately followed\n   * the tdata values. However, the linker 'magically' erases the\n   * memory allocation so that no ROM is consumed by this\n   * section\n   *\/\n  .tbss :\n  {\n      *(.tbss .tbss.* .gnu.linkonce.tb.*)\n      *(.tcommon)\n      __tbss_end = .;\n  } >flash : tls\n  __tls_size = __tbss_end - __tdata_start;\n  __tbss_size = __tls_size - __tdata_size;\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash AT>flash :flash\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash :ram_init\n\n  .data          :\n  {\n    *(.ramfunc .ramfunc.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n    KEEP (*(SORT(.xfa.*)))\n  } >ram AT>flash :ram_init\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram AT>ram :ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n  PROVIDE( _sheap = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _eheap = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram AT>ram :ram\n\n  .end_fw (NOLOAD) : ALIGN(4) {\n    _end_fw = . ;\n  } > flash\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"ee7d9c8dfdd9c1449dcd07d3b7973169a1426cd9","subject":"Changes the flash size of the lpc11c24 to be outside of the hardware spec, because our code does not fit in there anymore.","message":"Changes the flash size of the lpc11c24 to be outside of the hardware spec, because our code does not fit in there anymore.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/nxp-lpc11C24-lpcxpresso\/target.ld","new_file":"boards\/nxp-lpc11C24-lpcxpresso\/target.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(ResetISR)\nSEARCH_DIR(.)\n\nGROUP(\n libgcc.a\n libc_s.a\n libstdc++_s.a\n libm.a\n crti.o\n crtn.o\n crtbegin.o\n crtend.o\n)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  \/*MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x08000  \/*32k *\/\n  MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 \/* 64k TEMPORARY *\/\n  \/* Top 32 bytes is used by the flash writing firmware. 0x50..0xb8 by the ROM CAN drivers. 0 to 0x50 is used by the *\/\n\n  RamLoc8 (rwx) : ORIGIN = 0x10000100, LENGTH = 0x1ee0 \/* 7k *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash32 = ORIGIN(MFlash32) + LENGTH(MFlash32);\n  __top_RamLoc8 = ORIGIN(RamLoc8) + LENGTH(RamLoc8);\n\n  \/* The cortex-m0 FreeRTOS is not using the original stack once the scheduler\n  has started, so we have no reason to reserve the top of RAM. *\/\n  __cs3_heap_end = __top_RamLoc8;\n\n  __start_ram = ORIGIN(RamLoc8);\n  __end_ram = __top_RamLoc8;\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data)) ;\n        LONG(  SIZEOF(.data));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(SORT(.text*))\n\t*(.rodata)\n        *(SORT(.rodata.*))\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        \/* End C++ *\/\n\t\n\t__text_section_guard = .;\n\tLONG( 0 );\n    } > MFlash32\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash32\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash32\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \n    \/* MAIN DATA SECTION *\/\n    \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > RamLoc8\n\n    \/* It seems that in order for LPCXpresso to properly flash the data\n    section, an alignment of 256 bytes is necessary. Otherwise the separate\n    flashing of the data section will corrupt the end of the text section. *\/\n    .data : ALIGN(256)\n    {\n        FILL(0xff)\n        _data = .;\n        *(vtable)\n\t__impure_data_start = .;\n\t*(.data.impure_data)\n\t__impure_data_end = .;\n        *(.data*)\n\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n        . = ALIGN (4);\n\n        _edata = .;\n    } > RamLoc8 AT>MFlash32\n\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n    } > RamLoc8\n        \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > RamLoc8\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(__cs3_heap_start = .);\n    \/* This pointer will be written to the SP register at reset. *\/\n    PROVIDE(_vStackTop = __top_RamLoc8);\n\n    PROVIDE(__impure_data_size = __impure_data_end - __impure_data_start);\n\n}\n\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(ResetISR)\nSEARCH_DIR(.)\n\nGROUP(\n libgcc.a\n libc_s.a\n libstdc++_s.a\n libm.a\n crti.o\n crtn.o\n crtbegin.o\n crtend.o\n)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  \/*MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x08000  \/*32k *\/\n  MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 \/* 64k TEMPORARY *\/\n  \/* Top 32 bytes is used by the flash writing firmware. 0x50..0xb8 by the ROM CAN drivers. 0 to 0x50 is used by the *\/\n\n  RamLoc8 (rwx) : ORIGIN = 0x10000100, LENGTH = 0x1ee0 \/* 7k *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash32 = ORIGIN(MFlash32) + LENGTH(MFlash32);\n  __top_RamLoc8 = ORIGIN(RamLoc8) + LENGTH(RamLoc8);\n\n  \/* The cortex-m0 FreeRTOS is not using the original stack once the scheduler\n  has started, so we have no reason to reserve the top of RAM. *\/\n  __cs3_heap_end = __top_RamLoc8;\n\n  __start_ram = ORIGIN(RamLoc8);\n  __end_ram = __top_RamLoc8;\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data)) ;\n        LONG(  SIZEOF(.data));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(SORT(.text*))\n\t*(.rodata)\n        *(SORT(.rodata.*))\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        \/* End C++ *\/\n\t\n\t__text_section_guard = .;\n\tLONG( 0 );\n    } > MFlash32\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash32\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash32\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \n    \/* MAIN DATA SECTION *\/\n    \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > RamLoc8\n\n    \/* It seems that in order for LPCXpresso to properly flash the data\n    section, an alignment of 256 bytes is necessary. Otherwise the separate\n    flashing of the data section will corrupt the end of the text section. *\/\n    .data : ALIGN(256)\n    {\n        FILL(0xff)\n        _data = .;\n        *(vtable)\n\t__impure_data_start = .;\n\t*(.data.impure_data)\n\t__impure_data_end = .;\n        *(.data*)\n\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n        . = ALIGN (4);\n\n        _edata = .;\n    } > RamLoc8 AT>MFlash32\n\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n    } > RamLoc8\n        \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > RamLoc8\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(__cs3_heap_start = .);\n    \/* This pointer will be written to the SP register at reset. *\/\n    PROVIDE(_vStackTop = __top_RamLoc8);\n\n    PROVIDE(__impure_data_size = __impure_data_end - __impure_data_start);\n\n}\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"d150c82baa36e48b9026c286aadfa7e94b0ad64a","subject":"Update LPC1549.ld","message":"Update LPC1549.ld","repos":"NordicSemiconductor\/mbed,Archcady\/mbed-os,CalSol\/mbed,nRFMesh\/mbed-os,Tiryoh\/mbed,bremoran\/mbed-drivers,dbestm\/mbed,kpurusho\/mbed,andcor02\/mbed-os,fanghuaqi\/mbed,Marcomissyou\/mbed,jpbrucker\/mbed,netzimme\/mbed-os,ban4jp\/mbed,bentwire\/mbed,nvlsianpu\/mbed,RonEld\/mbed,rosterloh\/mbed,adamgreen\/mbed,dbestm\/mbed,pbrook\/mbed,Timmmm\/mbed,getopenmono\/mbed,larks\/mbed,karsev\/mbed-os,mazimkhan\/mbed-os,pbrook\/mbed,kpurusho\/mbed,svogl\/mbed-os,iriark01\/mbed-drivers,ryankurte\/mbed-os,andcor02\/mbed-os,mikaleppanen\/mbed-os,K4zuki\/mbed,DanKupiniak\/mbed,al177\/mbed,Willem23\/mbed,jrjang\/mbed,getopenmono\/mbed,Tiryoh\/mbed,fanghuaqi\/mbed,jamesadevine\/mbed,fanghuaqi\/mbed,maximmbed\/mbed,bikeNomad\/mbed,mnlipp\/mbed,YarivCol\/mbed-os,pbrook\/mbed,netzimme\/mbed-os,Timmmm\/mbed,fpiot\/mbed-ats,HeadsUpDisplayInc\/mbed,fvincenzo\/mbed-os,mazimkhan\/mbed-os,jpbrucker\/mbed,sg-\/mbed-drivers,adamgreen\/mbed,RonEld\/mbed,mmorenobarm\/mbed-os,wodji\/mbed,0xc0170\/mbed-drivers,NitinBhaskar\/mbed,EmuxEvans\/mbed,bentwire\/mbed,hwfwgrp\/mbed,rosterloh\/mbed,JasonHow44\/mbed,CalSol\/mbed,arostm\/mbed-os,bcostm\/mbed-os,pbrook\/mbed,c1728p9\/mbed-os,logost\/mbed,pedromes\/mbed,rgrover\/mbed,cvtsi2sd\/mbed-os,ban4jp\/mbed,larks\/mbed,infinnovation\/mbed-os,pedromes\/mbed,FranklyDev\/mbed,tung7970\/mbed-os,K4zuki\/mbed,FranklyDev\/mbed,tung7970\/mbed-os-1,YarivCol\/mbed-os,nRFMesh\/mbed-os,mbedmicro\/mbed,HeadsUpDisplayInc\/mbed,rosterloh\/mbed,betzw\/mbed-os,al177\/mbed,mazimkhan\/mbed-os,mnlipp\/mbed,fpiot\/mbed-ats,pradeep-gr\/mbed-os5-onsemi,fpiot\/mbed-ats,masaohamanaka\/mbed,nabilbendafi\/mbed,Timmmm\/mbed,arostm\/mbed-os,bcostm\/mbed-os,getopenmono\/mbed,tung7970\/mbed-os-1,rgrover\/mbed,pradeep-gr\/mbed-os5-onsemi,HeadsUpDisplayInc\/mbed,brstew\/MBED-BUILD,xcrespo\/mbed,YarivCol\/mbed-os,masaohamanaka\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,mmorenobarm\/mbed-os,NordicSemiconductor\/mbed,j-greffe\/mbed-os,jamesadevine\/mbed,jpbrucker\/mbed,monkiineko\/mbed-os,rgrover\/mbed,kl-cruz\/mbed-os,Timmmm\/mbed,fvincenzo\/mbed-os,NordicSemiconductor\/mbed,hwfwgrp\/mbed,GustavWi\/mbed,fahhem\/mbed-os,mmorenobarm\/mbed-os,brstew\/MBED-BUILD,tung7970\/mbed-os,ryankurte\/mbed-os,kl-cruz\/mbed-os,NXPmicro\/mbed,kpurusho\/mbed,RonEld\/mbed,nRFMesh\/mbed-os,jamesadevine\/mbed,GustavWi\/mbed,mnlipp\/mbed,tung7970\/mbed-os-1,nvlsianpu\/mbed,Shengliang\/mbed,maximmbed\/mbed,pedromes\/mbed,sam-geek\/mbed,DanKupiniak\/mbed,bulislaw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,arostm\/mbed-os,Marcomissyou\/mbed,jferreir\/mbed,Marcomissyou\/mbed,mazimkhan\/mbed-os,jrjang\/mbed,bulislaw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,pi19404\/mbed,al177\/mbed,jferreir\/mbed,maximmbed\/mbed,theotherjimmy\/mbed,NordicSemiconductor\/mbed,svastm\/mbed,Archcady\/mbed-os,Tiryoh\/mbed,K4zuki\/mbed,Tiryoh\/mbed,jeremybrodt\/mbed,tung7970\/mbed-os-1,logost\/mbed,GustavWi\/mbed,devanlai\/mbed,alertby\/mbed,jferreir\/mbed,struempelix\/mbed,maximmbed\/mbed,fvincenzo\/mbed-os,FranklyDev\/mbed,alertby\/mbed,catiedev\/mbed-os,nabilbendafi\/mbed,andcor02\/mbed-os,GustavWi\/mbed,nabilbendafi\/mbed,fpiot\/mbed-ats,pi19404\/mbed,fanghuaqi\/mbed,betzw\/mbed-os,fahhem\/mbed-os,monkiineko\/mbed-os,pi19404\/mbed,bulislaw\/mbed-os,xcrespo\/mbed,Sweet-Peas\/mbed,infinnovation\/mbed-os,j-greffe\/mbed-os,svogl\/mbed-os,jpbrucker\/mbed,jrjang\/mbed,adustm\/mbed,wodji\/mbed,K4zuki\/mbed,jrjang\/mbed,karsev\/mbed-os,jferreir\/mbed,rgrover\/mbed,kpurusho\/mbed,brstew\/MBED-BUILD,CalSol\/mbed,Tiryoh\/mbed,netzimme\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,pi19404\/mbed,HeadsUpDisplayInc\/mbed,masaohamanaka\/mbed,hwfwgrp\/mbed,bremoran\/mbed-drivers,logost\/mbed,bulislaw\/mbed-os,hwfwgrp\/mbed,infinnovation\/mbed-os,nRFMesh\/mbed-os,al177\/mbed,struempelix\/mbed,fvincenzo\/mbed-os,screamerbg\/mbed,kpurusho\/mbed,sam-geek\/mbed,bikeNomad\/mbed,mbedmicro\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,Shengliang\/mbed,mazimkhan\/mbed-os,cvtsi2sd\/mbed-os,alertby\/mbed,karsev\/mbed-os,HeadsUpDisplayInc\/mbed,mikaleppanen\/mbed-os,dbestm\/mbed,Archcady\/mbed-os,bulislaw\/mbed-os,arostm\/mbed-os,fpiot\/mbed-ats,cvtsi2sd\/mbed-os,svastm\/mbed,andcor02\/mbed-os,mikaleppanen\/mbed-os,dbestm\/mbed,xcrespo\/mbed,YarivCol\/mbed-os,mbedmicro\/mbed,mnlipp\/mbed,monkiineko\/mbed-os,svogl\/mbed-os,dbestm\/mbed,ban4jp\/mbed,RonEld\/mbed,mikaleppanen\/mbed-os,xcrespo\/mbed,infinnovation\/mbed-os,GustavWi\/mbed,sam-geek\/mbed,catiedev\/mbed-os,rosterloh\/mbed,Archcady\/mbed-os,Willem23\/mbed,theotherjimmy\/mbed,catiedev\/mbed-os,karsev\/mbed-os,sam-geek\/mbed,pi19404\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,monkiineko\/mbed-os,tung7970\/mbed-os,autopulated\/mbed,nvlsianpu\/mbed,mbedmicro\/mbed,Shengliang\/mbed,maximmbed\/mbed,nRFMesh\/mbed-os,larks\/mbed,larks\/mbed,struempelix\/mbed,wodji\/mbed,nabilbendafi\/mbed,svogl\/mbed-os,naves-thiago\/mbed-midi,autopulated\/mbed,devanlai\/mbed,nvlsianpu\/mbed,alertby\/mbed,NitinBhaskar\/mbed,andcor02\/mbed-os,JasonHow44\/mbed,j-greffe\/mbed-os,masaohamanaka\/mbed,ryankurte\/mbed-os,bcostm\/mbed-os,jpbrucker\/mbed,logost\/mbed,DanKupiniak\/mbed,Marcomissyou\/mbed,theotherjimmy\/mbed,pedromes\/mbed,getopenmono\/mbed,larks\/mbed,adamgreen\/mbed,ARM-software\/mbed-beetle,nvlsianpu\/mbed,netzimme\/mbed-os,CalSol\/mbed,mmorenobarm\/mbed-os,devanlai\/mbed,geky\/mbed,adustm\/mbed,adustm\/mbed,nabilbendafi\/mbed,NitinBhaskar\/mbed,devanlai\/mbed,bikeNomad\/mbed,autopulated\/mbed,NXPmicro\/mbed,Willem23\/mbed,ryankurte\/mbed-os,c1728p9\/mbed-os,0xc0170\/mbed-drivers,jamesadevine\/mbed,bentwire\/mbed,adamgreen\/mbed,NXPmicro\/mbed,Sweet-Peas\/mbed,Marcomissyou\/mbed,kl-cruz\/mbed-os,jrjang\/mbed,Shengliang\/mbed,ban4jp\/mbed,mnlipp\/mbed,al177\/mbed,karsev\/mbed-os,fahhem\/mbed-os,infinnovation\/mbed-os,fanghuaqi\/mbed,c1728p9\/mbed-os,larks\/mbed,j-greffe\/mbed-os,fahhem\/mbed-os,catiedev\/mbed-os,devanlai\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,EmuxEvans\/mbed,bcostm\/mbed-os,bikeNomad\/mbed,c1728p9\/mbed-os,kl-cruz\/mbed-os,Sweet-Peas\/mbed,sam-geek\/mbed,pedromes\/mbed,bikeNomad\/mbed,pradeep-gr\/mbed-os5-onsemi,andcor02\/mbed-os,naves-thiago\/mbed-midi,fahhem\/mbed-os,adustm\/mbed,arostm\/mbed-os,adamgreen\/mbed,wodji\/mbed,RonEld\/mbed,tung7970\/mbed-os,FranklyDev\/mbed,netzimme\/mbed-os,brstew\/MBED-BUILD,rosterloh\/mbed,alertby\/mbed,Marcomissyou\/mbed,fvincenzo\/mbed-os,EmuxEvans\/mbed,xcrespo\/mbed,bulislaw\/mbed-os,theotherjimmy\/mbed,Archcady\/mbed-os,betzw\/mbed-os,karsev\/mbed-os,Shengliang\/mbed,wodji\/mbed,screamerbg\/mbed,Timmmm\/mbed,NitinBhaskar\/mbed,screamerbg\/mbed,jpbrucker\/mbed,pradeep-gr\/mbed-os5-onsemi,ryankurte\/mbed-os,ryankurte\/mbed-os,naves-thiago\/mbed-midi,rosterloh\/mbed,andreaslarssonublox\/mbed,ARM-software\/mbed-beetle,betzw\/mbed-os,svastm\/mbed,HeadsUpDisplayInc\/mbed,NXPmicro\/mbed,fpiot\/mbed-ats,brstew\/MBED-BUILD,tung7970\/mbed-os,getopenmono\/mbed,catiedev\/mbed-os,theotherjimmy\/mbed,YarivCol\/mbed-os,jamesadevine\/mbed,mikaleppanen\/mbed-os,ban4jp\/mbed,nvlsianpu\/mbed,Sweet-Peas\/mbed,catiedev\/mbed-os,Sweet-Peas\/mbed,monkiineko\/mbed-os,JasonHow44\/mbed,EmuxEvans\/mbed,Sweet-Peas\/mbed,monkiineko\/mbed-os,kjbracey-arm\/mbed,CalSol\/mbed,maximmbed\/mbed,CalSol\/mbed,jeremybrodt\/mbed,c1728p9\/mbed-os,cvtsi2sd\/mbed-os,Willem23\/mbed,YarivCol\/mbed-os,j-greffe\/mbed-os,geky\/mbed,logost\/mbed,andreaslarssonublox\/mbed,alertby\/mbed,masaohamanaka\/mbed,mmorenobarm\/mbed-os,bcostm\/mbed-os,getopenmono\/mbed,theotherjimmy\/mbed,jferreir\/mbed,dbestm\/mbed,andreaslarssonublox\/mbed,andreaslarssonublox\/mbed,kl-cruz\/mbed-os,kjbracey-arm\/mbed,cvtsi2sd\/mbed-os,pi19404\/mbed,mazimkhan\/mbed-os,EmuxEvans\/mbed,naves-thiago\/mbed-midi,JasonHow44\/mbed,nabilbendafi\/mbed,struempelix\/mbed,naves-thiago\/mbed-midi,jamesadevine\/mbed,sg-\/mbed-drivers,cvtsi2sd\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,geky\/mbed,struempelix\/mbed,EmuxEvans\/mbed,mnlipp\/mbed,NitinBhaskar\/mbed,tung7970\/mbed-os-1,pedromes\/mbed,naves-thiago\/mbed-midi,al177\/mbed,betzw\/mbed-os,JasonHow44\/mbed,pbrook\/mbed,iriark01\/mbed-drivers,screamerbg\/mbed,K4zuki\/mbed,wodji\/mbed,mmorenobarm\/mbed-os,infinnovation\/mbed-os,brstew\/MBED-BUILD,arostm\/mbed-os,masaohamanaka\/mbed,jeremybrodt\/mbed,hwfwgrp\/mbed,netzimme\/mbed-os,andreaslarssonublox\/mbed,ARM-software\/mbed-beetle,pbrook\/mbed,hwfwgrp\/mbed,bentwire\/mbed,fahhem\/mbed-os,DanKupiniak\/mbed,svogl\/mbed-os,bentwire\/mbed,betzw\/mbed-os,xcrespo\/mbed,K4zuki\/mbed,Shengliang\/mbed,JasonHow44\/mbed,kjbracey-arm\/mbed,screamerbg\/mbed,j-greffe\/mbed-os,screamerbg\/mbed,svastm\/mbed,ban4jp\/mbed,kl-cruz\/mbed-os,c1728p9\/mbed-os,mikaleppanen\/mbed-os,bcostm\/mbed-os,Timmmm\/mbed,autopulated\/mbed,adustm\/mbed,NXPmicro\/mbed,nRFMesh\/mbed-os,ARM-software\/mbed-beetle,autopulated\/mbed,adamgreen\/mbed,jrjang\/mbed,RonEld\/mbed,svastm\/mbed,kjbracey-arm\/mbed,autopulated\/mbed,Willem23\/mbed,devanlai\/mbed,svogl\/mbed-os,jeremybrodt\/mbed,geky\/mbed,kpurusho\/mbed,rgrover\/mbed,struempelix\/mbed,mbedmicro\/mbed,jeremybrodt\/mbed,Tiryoh\/mbed,logost\/mbed,FranklyDev\/mbed,jferreir\/mbed,bentwire\/mbed,NXPmicro\/mbed,Archcady\/mbed-os,geky\/mbed,adustm\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC15XX\/TOOLCHAIN_GCC_CR\/LPC1549.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC15XX\/TOOLCHAIN_GCC_CR\/LPC1549.ld","new_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC1549\n * Created from generic_c.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Tue Jun 10 00:20:53 JST 2014\n *\/\n\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_16 (rwx) : ORIGIN = 0x2000000+0x100, LENGTH = 0x4000-0x100 \/* 16K bytes *\/\n  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 \/* 16K bytes *\/\n  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 \/* 4K bytes *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_16 = 0x2000000 + 0x4000;\n  __top_Ram1_16 = 0x2004000 + 0x4000;\n  __top_Ram2_4 = 0x2008000 + 0x1000;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n            \n    \/* DATA section for Ram1_16 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_16)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16 AT>MFlash256\n    \n    \/* DATA section for Ram2_4 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2_4)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/ \n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_16\n\t\n\t\/* Main DATA section (Ram0_16) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_16 AT>MFlash256\n\n    \/* BSS section for Ram1_16 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16\n    \/* BSS section for Ram2_4 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_16\n        \n    \/* NOINIT section for Ram1_16 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16 \n    \/* NOINIT section for Ram2_4 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_16\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_16 - 0);\n}\n","old_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC1549\n * Created from generic_c.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Tue Jun 10 00:20:53 JST 2014\n *\/\n\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 \/* 16K bytes *\/\n  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 \/* 16K bytes *\/\n  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 \/* 4K bytes *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_16 = 0x2000000 + 0x4000;\n  __top_Ram1_16 = 0x2004000 + 0x4000;\n  __top_Ram2_4 = 0x2008000 + 0x1000;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n            \n    \/* DATA section for Ram1_16 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_16)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16 AT>MFlash256\n    \n    \/* DATA section for Ram2_4 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2_4)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/ \n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_16\n\t\n\t\/* Main DATA section (Ram0_16) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_16 AT>MFlash256\n\n    \/* BSS section for Ram1_16 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16\n    \/* BSS section for Ram2_4 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_16\n        \n    \/* NOINIT section for Ram1_16 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16 \n    \/* NOINIT section for Ram2_4 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_16\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_16 - 0);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a5c04850550b2c48c13c7cea372493980a251b0f","subject":"Removed unused file","message":"Removed unused file\n","repos":"vipinbb\/nrf51x22base,vipinbb\/nrf51x22base","old_file":"gcc_nrf51_s310.ld","new_file":"gcc_nrf51_s310.ld","new_contents":"","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x20000, LENGTH = 0x20000 \/* 128 kB is taken by S310, 128 kB for app.  *\/\n  RAM (rwx) : ORIGIN = 0x20002800, LENGTH = 0x1800 \/* 10 kB is taken by S310, 6 kB for app. *\/\n}\nINCLUDE \"gcc_nrf51_common.ld\"\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b2a2da70a4ed6a5251d5b80436b6d2e35d69a33b","subject":"fix the ld","message":"fix the ld\n","repos":"hezlog\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread","old_file":"bsp\/nrf5x\/libraries\/templates\/nrfx\/board\/linker_scripts\/link.lds","new_file":"bsp\/nrf5x\/libraries\/templates\/nrfx\/board\/linker_scripts\/link.lds","new_contents":"\/* Linker script to configure memory regions. *\/\n\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000\n  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x40000\n}\n\nINCLUDE \"packages\/nrfx-v2.1.0\/mdk\/nrf_common.ld\"\n\n\n\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000\n  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x40000\n  CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x10000\n}\n\nINCLUDE \"packages\/nrfx-v2.1.0\/mdk\/nrf_common.ld\"\n\n\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"df5b22b2643b0bd27d6054130af12610bc325ed9","subject":"linker: esp32: moved windowspill to IRAM","message":"linker: esp32: moved windowspill to IRAM\n\nxthal_window_spill call has to be placed into IRAM\nin order to allow flash cache disabled operation, otherwise\nit will crash.\n\nSigned-off-by: Sylvio Alves <bd63183a3ab542e2b25ff1e90971d4881e1bdbe5@espressif.com>\n","repos":"Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\n\/* Global symbols required for espressif hal build *\/\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\nPROVIDE ( phy_get_romfuncs = 0x40004100 );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );\nPROVIDE ( g_rom_flashchip = 0x3ffae270 );\nPROVIDE ( SPI0 = 0x3ff43000 );\nPROVIDE ( SPI1 = 0x3ff42fff );\nPROVIDE ( SPI2 = 0x3ff64fff );\nPROVIDE ( SPI3 = 0x3ff65fff );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( esp32_rom_ets_printf = ets_printf );\nPROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );\nPROVIDE ( TIMERG0 = 0x3ff5F000 );\nPROVIDE ( TIMERG1 = 0x3ff60000 );\n\n\/* __udivdi3 is exported using assignment, which declares strong symbols *\/\n__udivdi3 = 0x4000cff8;\n__umoddi3 = 0x4000d280;\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *  - Reserve memory region for BT controller library from ROM\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x30000\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n#if defined(CONFIG_NET_SOCKETS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_socket_register);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(settings_handler_static);\n    . = ALIGN(4);\n#endif\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nPROVIDE ( __stack = 0x3ffe3f20 );\n\n\/* Global symbols required for espressif hal build *\/\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\nPROVIDE ( phy_get_romfuncs = 0x40004100 );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );\nPROVIDE ( g_rom_flashchip = 0x3ffae270 );\nPROVIDE ( SPI0 = 0x3ff43000 );\nPROVIDE ( SPI1 = 0x3ff42fff );\nPROVIDE ( SPI2 = 0x3ff64fff );\nPROVIDE ( SPI3 = 0x3ff65fff );\n\nPROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );\nPROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );\nPROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );\nPROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );\nPROVIDE ( esp32_rom_intr_matrix_set = intr_matrix_set );\nPROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );\nPROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );\nPROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );\nPROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );\nPROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );\nPROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( esp32_rom_ets_printf = ets_printf );\nPROVIDE ( esp32_rom_g_ticks_per_us_app = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_g_ticks_per_us_pro = g_ticks_per_us_app );\nPROVIDE ( esp32_rom_ets_delay_us = ets_delay_us );\nPROVIDE ( TIMERG0 = 0x3ff5F000 );\nPROVIDE ( TIMERG1 = 0x3ff60000 );\n\n\/* __udivdi3 is exported using assignment, which declares strong symbols *\/\n__udivdi3 = 0x4000cff8;\n__umoddi3 = 0x4000d280;\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *  - Reserve memory region for BT controller library from ROM\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000, len = 0x30000\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_if_dev);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_l2);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  Z_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef Z_ITERABLE_SECTION_RAM_GC_ALLOWED\n#define Z_ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef Z_ITERABLE_SECTION_RAM\n#define Z_ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n#if defined(CONFIG_NET_SOCKETS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(net_socket_register);\n    . = ALIGN(4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(settings_handler_static);\n    . = ALIGN(4);\n#endif\n\n    . = ALIGN(4);\n    Z_LINK_ITERABLE(shell);\n    . = ALIGN(4);\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"Z_ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef Z_ITERABLE_SECTION_ROM\n#define Z_ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"Z_ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.*)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.*)\n    _iram_text_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n    _heap_start = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a4ec37f87d2a86e0091bbb590b06f65757b01600","subject":"more explanations in mem.ld file","message":"more explanations in mem.ld file","repos":"gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins","old_file":"ilg.gnuarmeclipse.managedbuild.cross\/templates\/projecttemplates\/HelloWorld_CM3_C_Project\/ldscripts\/mem.ld","new_file":"ilg.gnuarmeclipse.managedbuild.cross\/templates\/projecttemplates\/HelloWorld_CM3_C_Project\/ldscripts\/mem.ld","new_contents":"\/* Linker script to configure memory regions. \n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 20K\n}\n","old_contents":"\/* Memory layout for STM32F103[CRTV]B *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 20K\n}\n","returncode":0,"stderr":"","license":"epl-1.0","lang":"Linker Script"}
{"commit":"d092dc76793766cbd835e7c38c078f27531fec9e","subject":"Internal change","message":"Internal change\n\nPiperOrigin-RevId: 326361710\n","repos":"GoogleCloudPlatform\/cloud-profiler-java,GoogleCloudPlatform\/cloud-profiler-java","old_file":"src\/cloud_profiler_java_agent.lds","new_file":"src\/cloud_profiler_java_agent.lds","new_contents":"VERS_1.0 {\n  global:\n    google_find_phdr;\n    Agent_OnLoad;\n    Agent_OnUnload;\n    Java_org_apache_beam_runners_dataflow_worker_profiler_Profiler_disable;\n    Java_org_apache_beam_runners_dataflow_worker_profiler_Profiler_enable;\n    Java_org_apache_beam_runners_dataflow_worker_profiler_Profiler_getAttribute;\n    Java_org_apache_beam_runners_dataflow_worker_profiler_Profiler_registerAttribute;\n    Java_org_apache_beam_runners_dataflow_worker_profiler_Profiler_setAttribute;\n  local:\n    *;\n};\n","old_contents":"VERS_1.0 {\n  global:\n    Agent_OnLoad;\n    Agent_OnUnload;\n    Java_org_apache_beam_runners_dataflow_worker_profiler_Profiler_disable;\n    Java_org_apache_beam_runners_dataflow_worker_profiler_Profiler_enable;\n    Java_org_apache_beam_runners_dataflow_worker_profiler_Profiler_getAttribute;\n    Java_org_apache_beam_runners_dataflow_worker_profiler_Profiler_registerAttribute;\n    Java_org_apache_beam_runners_dataflow_worker_profiler_Profiler_setAttribute;\n  local:\n    *;\n};\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"dc6fd00d63a999738e05b9205eab783672b92cb5","subject":"Modified memory sizes in linker script","message":"Modified memory sizes in linker script\n","repos":"bentwire\/mbed,geky\/mbed,mmorenobarm\/mbed-os,fvincenzo\/mbed-os,Archcady\/mbed-os,ryankurte\/mbed-os,fahhem\/mbed-os,catiedev\/mbed-os,nabilbendafi\/mbed,kpurusho\/mbed,jrjang\/mbed,rgrover\/mbed,YarivCol\/mbed-os,Tiryoh\/mbed,kjbracey-arm\/mbed,mazimkhan\/mbed-os,pedromes\/mbed,DanKupiniak\/mbed,bcostm\/mbed-os,nvlsianpu\/mbed,svastm\/mbed,fvincenzo\/mbed-os,theotherjimmy\/mbed,kjbracey-arm\/mbed,NXPmicro\/mbed,karsev\/mbed-os,karsev\/mbed-os,pedromes\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,arostm\/mbed-os,dbestm\/mbed,c1728p9\/mbed-os,ARM-software\/mbed-beetle,theotherjimmy\/mbed,kl-cruz\/mbed-os,tung7970\/mbed-os,mazimkhan\/mbed-os,nRFMesh\/mbed-os,rgrover\/mbed,catiedev\/mbed-os,screamerbg\/mbed,bentwire\/mbed,mikaleppanen\/mbed-os,andreaslarssonublox\/mbed,monkiineko\/mbed-os,mikaleppanen\/mbed-os,rosterloh\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,svastm\/mbed,RonEld\/mbed,infinnovation\/mbed-os,screamerbg\/mbed,adustm\/mbed,bikeNomad\/mbed,nvlsianpu\/mbed,bcostm\/mbed-os,cvtsi2sd\/mbed-os,rgrover\/mbed,cvtsi2sd\/mbed-os,jrjang\/mbed,netzimme\/mbed-os,maximmbed\/mbed,catiedev\/mbed-os,j-greffe\/mbed-os,Tiryoh\/mbed,adamgreen\/mbed,pradeep-gr\/mbed-os5-onsemi,infinnovation\/mbed-os,fanghuaqi\/mbed,YarivCol\/mbed-os,andcor02\/mbed-os,pradeep-gr\/mbed-os5-onsemi,geky\/mbed,mmorenobarm\/mbed-os,cvtsi2sd\/mbed-os,kl-cruz\/mbed-os,HeadsUpDisplayInc\/mbed,kl-cruz\/mbed-os,dbestm\/mbed,monkiineko\/mbed-os,monkiineko\/mbed-os,NXPmicro\/mbed,Tiryoh\/mbed,adamgreen\/mbed,arostm\/mbed-os,geky\/mbed,RonEld\/mbed,jeremybrodt\/mbed,netzimme\/mbed-os,netzimme\/mbed-os,cvtsi2sd\/mbed-os,karsev\/mbed-os,DanKupiniak\/mbed,j-greffe\/mbed-os,jeremybrodt\/mbed,jeremybrodt\/mbed,mazimkhan\/mbed-os,bentwire\/mbed,cvtsi2sd\/mbed-os,andreaslarssonublox\/mbed,andreaslarssonublox\/mbed,bikeNomad\/mbed,theotherjimmy\/mbed,CalSol\/mbed,andcor02\/mbed-os,Tiryoh\/mbed,screamerbg\/mbed,betzw\/mbed-os,tung7970\/mbed-os,svogl\/mbed-os,ryankurte\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,svogl\/mbed-os,mbedmicro\/mbed,andreaslarssonublox\/mbed,rosterloh\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,Shengliang\/mbed,adustm\/mbed,getopenmono\/mbed,netzimme\/mbed-os,pradeep-gr\/mbed-os5-onsemi,svogl\/mbed-os,dbestm\/mbed,kpurusho\/mbed,YarivCol\/mbed-os,bikeNomad\/mbed,fvincenzo\/mbed-os,Archcady\/mbed-os,rgrover\/mbed,kl-cruz\/mbed-os,jeremybrodt\/mbed,tung7970\/mbed-os,tung7970\/mbed-os-1,tung7970\/mbed-os-1,j-greffe\/mbed-os,arostm\/mbed-os,Shengliang\/mbed,RonEld\/mbed,bulislaw\/mbed-os,bcostm\/mbed-os,maximmbed\/mbed,karsev\/mbed-os,catiedev\/mbed-os,mazimkhan\/mbed-os,jrjang\/mbed,betzw\/mbed-os,monkiineko\/mbed-os,mikaleppanen\/mbed-os,NXPmicro\/mbed,tung7970\/mbed-os,NXPmicro\/mbed,getopenmono\/mbed,theotherjimmy\/mbed,Tiryoh\/mbed,nRFMesh\/mbed-os,svastm\/mbed,Shengliang\/mbed,screamerbg\/mbed,j-greffe\/mbed-os,mmorenobarm\/mbed-os,theotherjimmy\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,mazimkhan\/mbed-os,bulislaw\/mbed-os,geky\/mbed,jrjang\/mbed,bulislaw\/mbed-os,karsev\/mbed-os,rosterloh\/mbed,adustm\/mbed,ryankurte\/mbed-os,nvlsianpu\/mbed,jrjang\/mbed,adamgreen\/mbed,kjbracey-arm\/mbed,arostm\/mbed-os,kpurusho\/mbed,maximmbed\/mbed,dbestm\/mbed,Archcady\/mbed-os,mbedmicro\/mbed,mmorenobarm\/mbed-os,c1728p9\/mbed-os,YarivCol\/mbed-os,RonEld\/mbed,betzw\/mbed-os,ryankurte\/mbed-os,NXPmicro\/mbed,karsev\/mbed-os,dbestm\/mbed,tung7970\/mbed-os-1,pradeep-gr\/mbed-os5-onsemi,ARM-software\/mbed-beetle,rosterloh\/mbed,betzw\/mbed-os,fahhem\/mbed-os,infinnovation\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,pradeep-gr\/mbed-os5-onsemi,netzimme\/mbed-os,mbedmicro\/mbed,tung7970\/mbed-os,andcor02\/mbed-os,HeadsUpDisplayInc\/mbed,fvincenzo\/mbed-os,getopenmono\/mbed,ryankurte\/mbed-os,maximmbed\/mbed,mmorenobarm\/mbed-os,RonEld\/mbed,j-greffe\/mbed-os,fahhem\/mbed-os,nRFMesh\/mbed-os,geky\/mbed,mikaleppanen\/mbed-os,rosterloh\/mbed,jrjang\/mbed,adustm\/mbed,nabilbendafi\/mbed,j-greffe\/mbed-os,c1728p9\/mbed-os,bikeNomad\/mbed,andcor02\/mbed-os,HeadsUpDisplayInc\/mbed,arostm\/mbed-os,adamgreen\/mbed,fahhem\/mbed-os,nabilbendafi\/mbed,monkiineko\/mbed-os,kpurusho\/mbed,pedromes\/mbed,HeadsUpDisplayInc\/mbed,getopenmono\/mbed,svogl\/mbed-os,ryankurte\/mbed-os,Archcady\/mbed-os,pedromes\/mbed,infinnovation\/mbed-os,nRFMesh\/mbed-os,fanghuaqi\/mbed,infinnovation\/mbed-os,tung7970\/mbed-os-1,jeremybrodt\/mbed,nvlsianpu\/mbed,CalSol\/mbed,bcostm\/mbed-os,mazimkhan\/mbed-os,fanghuaqi\/mbed,kpurusho\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,fanghuaqi\/mbed,Tiryoh\/mbed,RonEld\/mbed,mikaleppanen\/mbed-os,CalSol\/mbed,nabilbendafi\/mbed,nabilbendafi\/mbed,HeadsUpDisplayInc\/mbed,mbedmicro\/mbed,kl-cruz\/mbed-os,kl-cruz\/mbed-os,DanKupiniak\/mbed,arostm\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,svastm\/mbed,Archcady\/mbed-os,betzw\/mbed-os,getopenmono\/mbed,adamgreen\/mbed,fahhem\/mbed-os,ARM-software\/mbed-beetle,Shengliang\/mbed,nRFMesh\/mbed-os,bulislaw\/mbed-os,adustm\/mbed,NXPmicro\/mbed,nvlsianpu\/mbed,screamerbg\/mbed,CalSol\/mbed,Shengliang\/mbed,DanKupiniak\/mbed,ARM-software\/mbed-beetle,pedromes\/mbed,pradeep-gr\/mbed-os5-onsemi,svogl\/mbed-os,maximmbed\/mbed,mikaleppanen\/mbed-os,YarivCol\/mbed-os,HeadsUpDisplayInc\/mbed,andcor02\/mbed-os,bentwire\/mbed,nabilbendafi\/mbed,bcostm\/mbed-os,netzimme\/mbed-os,fahhem\/mbed-os,YarivCol\/mbed-os,bikeNomad\/mbed,nRFMesh\/mbed-os,adamgreen\/mbed,bulislaw\/mbed-os,catiedev\/mbed-os,bcostm\/mbed-os,fanghuaqi\/mbed,getopenmono\/mbed,tung7970\/mbed-os-1,dbestm\/mbed,rosterloh\/mbed,infinnovation\/mbed-os,kjbracey-arm\/mbed,pedromes\/mbed,maximmbed\/mbed,Shengliang\/mbed,nvlsianpu\/mbed,catiedev\/mbed-os,andreaslarssonublox\/mbed,betzw\/mbed-os,screamerbg\/mbed,bentwire\/mbed,Archcady\/mbed-os,CalSol\/mbed,bulislaw\/mbed-os,bentwire\/mbed,svogl\/mbed-os,fvincenzo\/mbed-os,CalSol\/mbed,mmorenobarm\/mbed-os,monkiineko\/mbed-os,c1728p9\/mbed-os,kpurusho\/mbed,rgrover\/mbed,adustm\/mbed,svastm\/mbed,cvtsi2sd\/mbed-os,theotherjimmy\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_STM32F4\/TARGET_NUCLEO_F410RB\/TOOLCHAIN_GCC_ARM\/STM32F411XE.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_STM32F4\/TARGET_NUCLEO_F410RB\/TOOLCHAIN_GCC_ARM\/STM32F411XE.ld","new_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K\n  RAM (rwx)  : ORIGIN = 0x20000198, LENGTH = 32k - 0x198\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K\n  RAM (rwx)  : ORIGIN = 0x20000198, LENGTH = 128k - 0x198\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5587f5d88f63c972ae55cafc7a57e1bf73d4cb96","subject":"cpu\/cortexm_common: add flash_writable section to linker script","message":"cpu\/cortexm_common: add flash_writable section to linker script\n","repos":"OlegHahm\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,miri64\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,ant9000\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* This is only used by gdb to understand where to start *\/\nENTRY(reset_handler_default)\n\n_backup_ram_start_addr = DEFINED( _backup_ram_start_addr ) ? _backup_ram_start_addr : 0x0 ;\n_backup_ram_len = DEFINED( _backup_ram_len ) ? _backup_ram_len : 0x0 ;\n\n\/* not all Cortex-M platforms use cortexm.ld yet *\/\nMEMORY\n{\n    bkup_ram (w!rx) : ORIGIN = _backup_ram_start_addr, LENGTH = _backup_ram_len\n}\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _isr_vectors = DEFINED(_isr_vectors) ? _isr_vectors : . ;\n        KEEP(*(SORT(.vectors*)))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        KEEP (*(SORT(.roxfa.*)))\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/*\n     * TLS relocations are offsets relative to the address\n     * of the first TLS symbol. That means we just need to\n     * allocate them all together so that the TLS region\n     * is compact when allocated for each thread.\n     *\/\n\n    \/*\n     * TLS initialization data is loaded into ROM so that\n     * each thread can get its values initialized from there\n     * at startup\n     *\/\n    .tdata :\n    {\n         __tdata_start = .;\n        *(.tdata .tdata.* .gnu.linkonce.td.*)\n        __tdata_end = .;\n    } > rom\n    __tdata_source = LOADADDR(.tdata);\n    __tdata_size = SIZEOF(.tdata);\n\n    \/*\n     * TLS zeroed data is relocated as if it immediately followed\n     * the tdata values. However, the linker 'magically' erases the\n     * memory allocation so that no ROM is consumed by this\n     * section\n     *\/\n    .tbss :\n    {\n        *(.tbss .tbss.* .gnu.linkonce.tb.*)\n        *(.tcommon)\n        __tbss_end = .;\n    } > rom\n    __tls_size = __tbss_end - __tdata_start;\n    __tbss_size = __tls_size - __tdata_size;\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        KEEP (*(.puf))\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate :\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        KEEP (*(SORT(.xfa.*)))\n        KEEP (*(.openocd .openocd.*))\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram AT> rom\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        *(.noinit)\n        . = ALIGN(4);\n        __noinit_end = .;\n    }  > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about rom size *\/\n    _srom = ORIGIN(rom);\n    _erom = ORIGIN(rom) + LENGTH(rom);\n\n    _sbackup_data_load = LOADADDR(.backup.data);\n    .backup.data :  ALIGN(4) {\n        _sbackup_data = .;\n        *(.backup.data)\n        _ebackup_data = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > bkup_ram AT> rom\n\n    .backup.bss (NOLOAD) : ALIGN(4) {\n        _sbackup_bss = .;\n        *(.backup.bss)\n        _ebackup_bss = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > bkup_ram\n\n    .heap3 (NOLOAD) : ALIGN(4) {\n        _sheap1 = . ;\n        _eheap1 = ORIGIN(bkup_ram) + LENGTH(bkup_ram);\n    } > bkup_ram\n\n    .flash_writable (NOLOAD) : {\n        KEEP(*(SORT(.flash_writable.*)))\n    } > rom\n\n    .end_fw (NOLOAD) : ALIGN(4) {\n        _end_fw = . ;\n    } > rom\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* This is only used by gdb to understand where to start *\/\nENTRY(reset_handler_default)\n\n_backup_ram_start_addr = DEFINED( _backup_ram_start_addr ) ? _backup_ram_start_addr : 0x0 ;\n_backup_ram_len = DEFINED( _backup_ram_len ) ? _backup_ram_len : 0x0 ;\n\n\/* not all Cortex-M platforms use cortexm.ld yet *\/\nMEMORY\n{\n    bkup_ram (w!rx) : ORIGIN = _backup_ram_start_addr, LENGTH = _backup_ram_len\n}\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _isr_vectors = DEFINED(_isr_vectors) ? _isr_vectors : . ;\n        KEEP(*(SORT(.vectors*)))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        KEEP (*(SORT(.roxfa.*)))\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/*\n     * TLS relocations are offsets relative to the address\n     * of the first TLS symbol. That means we just need to\n     * allocate them all together so that the TLS region\n     * is compact when allocated for each thread.\n     *\/\n\n    \/*\n     * TLS initialization data is loaded into ROM so that\n     * each thread can get its values initialized from there\n     * at startup\n     *\/\n    .tdata :\n    {\n         __tdata_start = .;\n        *(.tdata .tdata.* .gnu.linkonce.td.*)\n        __tdata_end = .;\n    } > rom\n    __tdata_source = LOADADDR(.tdata);\n    __tdata_size = SIZEOF(.tdata);\n\n    \/*\n     * TLS zeroed data is relocated as if it immediately followed\n     * the tdata values. However, the linker 'magically' erases the\n     * memory allocation so that no ROM is consumed by this\n     * section\n     *\/\n    .tbss :\n    {\n        *(.tbss .tbss.* .gnu.linkonce.tb.*)\n        *(.tcommon)\n        __tbss_end = .;\n    } > rom\n    __tls_size = __tbss_end - __tdata_start;\n    __tbss_size = __tls_size - __tdata_size;\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        KEEP (*(.puf))\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate :\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        KEEP (*(SORT(.xfa.*)))\n        KEEP (*(.openocd .openocd.*))\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram AT> rom\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        *(.noinit)\n        . = ALIGN(4);\n        __noinit_end = .;\n    }  > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about rom size *\/\n    _srom = ORIGIN(rom);\n    _erom = ORIGIN(rom) + LENGTH(rom);\n\n    _sbackup_data_load = LOADADDR(.backup.data);\n    .backup.data :  ALIGN(4) {\n        _sbackup_data = .;\n        *(.backup.data)\n        _ebackup_data = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > bkup_ram AT> rom\n\n    .backup.bss (NOLOAD) : ALIGN(4) {\n        _sbackup_bss = .;\n        *(.backup.bss)\n        _ebackup_bss = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > bkup_ram\n\n    .heap3 (NOLOAD) : ALIGN(4) {\n        _sheap1 = . ;\n        _eheap1 = ORIGIN(bkup_ram) + LENGTH(bkup_ram);\n    } > bkup_ram\n\n    .end_fw (NOLOAD) : ALIGN(4) {\n        _end_fw = . ;\n    } > rom\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"8e592b9f919f2256a765829eb087a2201aed1008","subject":"[bsp][bluetrum] update link.lds","message":"[bsp][bluetrum] update link.lds\n","repos":"RT-Thread\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread","old_file":"bsp\/bluetrum\/ab32vg1-ab-prougen\/link.lds","new_file":"bsp\/bluetrum\/ab32vg1-ab-prougen\/link.lds","new_contents":"\/* Define the flash max size *\/\n__max_flash_size = 1024k;\n\n__data_ram_size = 8k;\n__stack_ram_size = 4k;\n__comm_ram_size = 83k;\n__heap_ram_size = 29k;\n\n__base = 0x10000000;\n\n__data_vma = 0x11000;\n__stack_vma = __data_vma + __data_ram_size;\n__comm_vma = __stack_vma + __stack_ram_size;\n__heap_vma = __comm_vma + __comm_ram_size;\n\n__ram1_vma = 0x50000;\n\nMEMORY\n{\n    init            : org = __base,             len = 512\n    flash(rx)       : org = __base + 512,       len = __max_flash_size\n    comm(rx)        : org = __comm_vma,         len = __comm_ram_size\n\n    data            : org = __data_vma,         len = __data_ram_size\n    stack           : org = __stack_vma,        len = __stack_ram_size\n    heap            : org = __heap_vma,         len = __heap_ram_size\n    ram1(rx)        : org = __ram1_vma,         len = 0x7a00\n}\n\nSECTIONS\n{\n    .init : {\n        *(.reset)\n    } > init\n\n    .ram1 __ram1_vma : {\n        . = ALIGN(4);\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n        *components*drivers**.o (.text*)\n        *device.o (.text*)\n        *components.o (.text*)\n        *idle.o (.text*)\n    } > ram1 AT > flash\n\n    .rti : {\n        . = ALIGN(4);\n        \/* section information for initial *\/\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(32);\n    } > ram1 AT > flash\n\n    .comm : {\n        . = ALIGN(4);\n        KEEP(*(.vector))\n        EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *dfs*filesystems**.o  \n        *romfs.o *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o\n        *letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o\n        *trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o) *(.text)\n        *finsh*shell.o (.text*)\n        *(.text.unlikely)\n        *(.text.startup)\n        EXCLUDE_FILE (*components*libc**.o *dfs*filesystems**.o *romfs.o *lib_a**.o \n        *cp-demangle.o *divdf3.o *muldf3.o *multf3.o *unwind*.o *_clz.o) *(.rodata)\n        *(.rodata.name)\n        EXCLUDE_FILE(*lib_a**.o *cp-demangle.o *cp-demangle.o) *(.rodata.str1.4)\n        EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata)\n        *(.rela*)\n        *(.data*)\n        *(.sdata*)\n    } > comm AT > flash\n\n    .bss (NOLOAD):\n    {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.sbss)\n        *(.buf*)\n        __bss_end = .;\n    } > data\n    __bss_size = __bss_end - __bss_start;\n\n    .stack (NOLOAD) : {\n        __irq_stack_start = .;\n        . = __stack_ram_size;\n        __irq_stack = .;\n    } > stack\n    __irq_stack_size = __irq_stack - __irq_stack_start;\n\n    .heap (NOLOAD) : {\n        __heap_start = .;\n        . = __heap_ram_size;\n        __heap_end = .;\n    } > heap\n\n    .flash : {\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*)\n        . = ALIGN(512);\n    } > flash\n}\n\n\/* Calc the lma *\/\n__bank_size = SIZEOF(.flash);\n__comm_lma = LOADADDR(.comm);\n__comm_size = SIZEOF(.comm);\n__ram1_lma = LOADADDR(.ram1);\n__ram1_size = SIZEOF(.ram1) + SIZEOF(.rti);\n","old_contents":"\/* Define the flash max size *\/\n__max_flash_size = 1024k;\n\n__data_ram_size = 8k;\n__stack_ram_size = 4k;\n__comm_ram_size = 83k;\n__heap_ram_size = 29k;\n\n__base = 0x10000000;\n\n__data_vma = 0x11000;\n__stack_vma = __data_vma + __data_ram_size;\n__comm_vma = __stack_vma + __stack_ram_size;\n__heap_vma = __comm_vma + __comm_ram_size;\n\n__ram1_vma = 0x50000;\n\nMEMORY\n{\n    init            : org = __base,             len = 512\n    flash(rx)       : org = __base + 512,       len = __max_flash_size\n    comm(rx)        : org = __comm_vma,         len = __comm_ram_size\n\n    data            : org = __data_vma,         len = __data_ram_size\n    stack           : org = __stack_vma,        len = __stack_ram_size\n    heap            : org = __heap_vma,         len = __heap_ram_size\n    ram1(rx)        : org = __ram1_vma,         len = 0x7a00\n}\n\nSECTIONS\n{\n    .init : {\n        *(.reset)\n    } > init\n\n    .ram1 __ram1_vma : {\n        . = ALIGN(4);\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n        *components*drivers**.o (.text*)\n        *device.o (.text*)\n        *components.o (.text*)\n        *idle.o (.text*)\n    } > ram1 AT > flash\n\n    .rti : {\n        . = ALIGN(4);\n        \/* section information for initial *\/\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(32);\n    } > ram1 AT > flash\n\n    .comm : {\n        . = ALIGN(4);\n        KEEP(*(.vector))\n        EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *romfs.o \n        *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o\n        *letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o\n        *trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o) *(.text)\n        *finsh*shell.o (.text*)\n        *(.text.unlikely)\n        *(.text.startup)\n        EXCLUDE_FILE (*components*libc**.o *romfs.o *lib_a**.o *cp-demangle.o\n        *divdf3.o *muldf3.o *multf3.o *unwind*.o *_clz.o) *(.rodata)\n        *(.rodata.name)\n        EXCLUDE_FILE(*lib_a**.o *cp-demangle.o) *(.rodata.str1.4)\n        EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata)\n        *(.rela*)\n        *(.data*)\n\t    *(.sdata*)\n    } > comm AT > flash\n\n    .bss (NOLOAD):\n    {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.sbss)\n        *(.buf*)\n        __bss_end = .;\n    } > data\n    __bss_size = __bss_end - __bss_start;\n\n    .stack (NOLOAD) : {\n        __irq_stack_start = .;\n        . = __stack_ram_size;\n        __irq_stack = .;\n    } > stack\n    __irq_stack_size = __irq_stack - __irq_stack_start;\n\n    .heap (NOLOAD) : {\n        __heap_start = .;\n        . = __heap_ram_size;\n        __heap_end = .;\n    } > heap\n\n    .flash : {\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*)\n        . = ALIGN(512);\n    } > flash\n}\n\n\/* Calc the lma *\/\n__bank_size = SIZEOF(.flash);\n__comm_lma = LOADADDR(.comm);\n__comm_size = SIZEOF(.comm);\n__ram1_lma = LOADADDR(.ram1);\n__ram1_size = SIZEOF(.ram1) + SIZEOF(.rti);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"49701ab5ef8dbe7e529f6568f0240be70fd61c19","subject":"Revert \"updated linker script\"","message":"Revert \"updated linker script\"\n\nThis reverts commit c60664889bf22416c0d7e5276ca9b1ebd3f56055.\n","repos":"stateos\/IntrOS,stateos\/IntrOS,stateos\/IntrOS","old_file":"startup\/STM32F4\/GNUCC\/script.ld","new_file":"startup\/STM32F4\/GNUCC\/script.ld","new_contents":"\/*******************************************************************************\n@file     stm32f4xx.ld\n@author   Rajmund Szymanski\n@date     02.01.2017\n@brief    Linker script for STM32F407VG device with 1024KB FLASH and 192KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 1024k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   64k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  128k\n\/*\tAUX (rwx) : ORIGIN = 0x2001C000, LENGTH =   16k\n*\/\tBKP (rwx) : ORIGIN = 0x40024000, LENGTH =    4k\n}\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t. = ABSOLUTE(__ram_end - __proc_stack_size);\n\t\t__heap_end = .;\n\t} > RAM\n\n\t__heap_size = SIZEOF(.heap);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","old_contents":"\/*******************************************************************************\n@file     stm32f4xx.ld\n@author   Rajmund Szymanski\n@date     28.02.2017\n@brief    Linker script for STM32F407VG device with 1024KB FLASH and 192KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x08000000, LENGTH = 1024k\n\tCCM (rwx) : ORIGIN = 0x10000000, LENGTH =   64k\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  128k\n\/*\tAUX (rwx) : ORIGIN = 0x2001C000, LENGTH =   16k\n*\/\tBKP (rwx) : ORIGIN = 0x40024000, LENGTH =    4k\n}\n\n__ccm_start = ORIGIN(CCM);\n__ccm_end   = ORIGIN(CCM) + LENGTH(CCM);\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(ROM);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > ROM\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > ROM\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > ROM\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > ROM\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > ROM\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.ccm (NOLOAD):\n\t{\n\t\t*(.ccm)\n\t} > CCM\n\n\t.bkp (NOLOAD):\n\t{\n\t\t*(.bkp)\n\t} > BKP\n\n\t.main_stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = SIZEOF(.main_stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > ROM\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM AT > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.proc_stack (NOLOAD): ALIGN(8)\n\t{\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t} > RAM\n\n\t__proc_stack_size = SIZEOF(.proc_stack);\n\n\t__heap_start = LOADADDR(.proc_stack);\n\t__heap_end   = __ram_end - __proc_stack_size;\n\n\t__proc_stack_start = __heap_end;\n\t__proc_stack_end   = __ram_end;\n\n\t__initial_msp = __main_stack_size ? __main_stack_end : __heap_end;\n\t__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp;\n\n\tPROVIDE(__data_start__ = __data_start);\n\tPROVIDE(__data_end__   = __data_end);\n\tPROVIDE(__bss_start__  = __bss_start);\n\tPROVIDE(__bss_end__    = __bss_end);\n\tPROVIDE(__end__        = __bss_end);\n\tPROVIDE(__heap_base__  = __heap_start);\n\tPROVIDE(__heap_end__   = __heap_end);\n\tPROVIDE(__heap_base    = __heap_start);\n\tPROVIDE(__heap_limit   = __heap_end);\n\tPROVIDE(__stack        = __initial_sp);\n\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n\tPROVIDE(__process_stack_end   = __proc_stack_end);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"98d4836105748906cfcdd67f4fb1818ff20b1508","subject":"linker quark_se: Fix operator precedence bug","message":"linker quark_se: Fix operator precedence bug\n\nWithout this patch, the final linker script had a memory region defined\nas:\n\n    RAM (wx) : ORIGIN = 0xA8006400, LENGTH = 55*1K - 0x20 +0x4\n\nresulting on the wrong RAM length. Fix BSP_SHARED_RAM_SIZE definition\nso the sum is always processed first.\n\nChange-Id: I16b93adbaf27bb84b6e5d1ac433ef80f854b218c\nSigned-off-by: Jesus Sanchez-Palencia <1d20c8e4bc5d088c92fbf17f94216ea9e3f7ce5e@intel.com>\n","repos":"pklazy\/zephyr,fractalclone\/zephyr-riscv,runchip\/zephyr-cc3200,bboozzoo\/zephyr,sharronliu\/zephyr,galak\/zephyr,runchip\/zephyr-cc3220,bboozzoo\/zephyr,ldts\/zephyr,Vudentz\/zephyr,aceofall\/zephyr-iotos,explora26\/zephyr,Vudentz\/zephyr,holtmann\/zephyr,kraj\/zephyr,punitvara\/zephyr,explora26\/zephyr,finikorg\/zephyr,punitvara\/zephyr,runchip\/zephyr-cc3220,ldts\/zephyr,ldts\/zephyr,tidyjiang8\/zephyr-doc,zephyriot\/zephyr,holtmann\/zephyr,mbolivar\/zephyr,holtmann\/zephyr,runchip\/zephyr-cc3220,GiulianoFranchetto\/zephyr,zephyriot\/zephyr,bboozzoo\/zephyr,bigdinotech\/zephyr,pklazy\/zephyr,sharronliu\/zephyr,ldts\/zephyr,bboozzoo\/zephyr,zephyriot\/zephyr,galak\/zephyr,Vudentz\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3200,punitvara\/zephyr,erwango\/zephyr,tidyjiang8\/zephyr-doc,rsalveti\/zephyr,pklazy\/zephyr,explora26\/zephyr,runchip\/zephyr-cc3220,finikorg\/zephyr,nashif\/zephyr,sharronliu\/zephyr,fbsder\/zephyr,erwango\/zephyr,rsalveti\/zephyr,zephyrproject-rtos\/zephyr,fractalclone\/zephyr-riscv,nashif\/zephyr,kraj\/zephyr,holtmann\/zephyr,nashif\/zephyr,explora26\/zephyr,bboozzoo\/zephyr,runchip\/zephyr-cc3200,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,zephyriot\/zephyr,galak\/zephyr,nashif\/zephyr,tidyjiang8\/zephyr-doc,fractalclone\/zephyr-riscv,punitvara\/zephyr,erwango\/zephyr,bigdinotech\/zephyr,rsalveti\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,aceofall\/zephyr-iotos,fractalclone\/zephyr-riscv,rsalveti\/zephyr,holtmann\/zephyr,aceofall\/zephyr-iotos,runchip\/zephyr-cc3220,bigdinotech\/zephyr,zephyriot\/zephyr,mbolivar\/zephyr,explora26\/zephyr,galak\/zephyr,fbsder\/zephyr,fbsder\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,pklazy\/zephyr,aceofall\/zephyr-iotos,GiulianoFranchetto\/zephyr,finikorg\/zephyr,tidyjiang8\/zephyr-doc,mbolivar\/zephyr,fractalclone\/zephyr-riscv,bigdinotech\/zephyr,runchip\/zephyr-cc3200,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,kraj\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,pklazy\/zephyr,bigdinotech\/zephyr,rsalveti\/zephyr,sharronliu\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,mbolivar\/zephyr,aceofall\/zephyr-iotos,sharronliu\/zephyr,kraj\/zephyr,tidyjiang8\/zephyr-doc,Vudentz\/zephyr,erwango\/zephyr,runchip\/zephyr-cc3200,zephyrproject-rtos\/zephyr,fbsder\/zephyr,erwango\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,kraj\/zephyr","old_file":"arch\/x86\/soc\/intel_quark\/quark_se\/linker.ld","new_file":"arch\/x86\/soc\/intel_quark\/quark_se\/linker.ld","new_contents":"\/*\n * Copyright (c) 2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * This is the linker script for both standard images and XIP images.\n *\/\n\n#include <autoconf.h>\n\n\/* physical address of RAM (needed for correct __ram_phys_end symbol) *\/\n#define PHYS_RAM_ADDR    CONFIG_PHYS_RAM_ADDR\n\n\/* physical address where the kernel is loaded *\/\n#ifdef CONFIG_XIP\n  #define PHYS_LOAD_ADDR   CONFIG_PHYS_LOAD_ADDR\n#else  \/* !CONFIG_XIP *\/\n  #define PHYS_LOAD_ADDR   CONFIG_PHYS_RAM_ADDR\n#endif \/* CONFIG_XIP *\/\n\n\/* total shared RAM size (restore info + gdt) *\/\n#define BSP_SHARED_RAM_SIZE \\\n\t(CONFIG_BSP_SHARED_GDT_RAM_SIZE+CONFIG_BSP_SHARED_RESTORE_INFO_SIZE)\n\/*\n * When DEEP_SLEEP is not enabled, the shared memory can be re-used after boot.\n * Since the memory regions area are at fixed address locations, only the\n * contiguous unused memory located at the end of RAM should be made available.\n *\/\n#ifdef CONFIG_SYS_POWER_DEEP_SLEEP\n#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K - BSP_SHARED_RAM_SIZE\n#else\n#ifdef CONFIG_SET_GDT\n#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K\n#else\n#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K - CONFIG_BSP_SHARED_GDT_RAM_SIZE\n#endif\n#endif\n\nMEMORY\n    {\n#ifdef CONFIG_XIP\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K\n    RAM (wx)        : ORIGIN = PHYS_RAM_ADDR, LENGTH =  PHYS_RAM_SIZE\n#else  \/* !CONFIG_XIP *\/\n    RAM (wx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_SIZE\n#endif \/* CONFIG_XIP *\/\n#ifdef CONFIG_SYS_POWER_DEEP_SLEEP\n    BSP_SHARED_RAM (rw) : ORIGIN = CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR,\n                          LENGTH = CONFIG_BSP_SHARED_RESTORE_INFO_SIZE\n#endif \/* CONFIG_SYS_POWER_DEEP_SLEEP *\/\n#ifndef CONFIG_SET_GDT\n    BSP_SHARED_GDT_RAM (rw) : ORIGIN = CONFIG_BSP_SHARED_GDT_RAM_ADDR,\n                              LENGTH = CONFIG_BSP_SHARED_GDT_RAM_SIZE\n#endif \/* !CONFIG_SET_GDT *\/\n\n    \/*\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 2K, LENGTH = 2K\n    }\n\n#include <arch\/x86\/linker.ld>\n\n","old_contents":"\/*\n * Copyright (c) 2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * This is the linker script for both standard images and XIP images.\n *\/\n\n#include <autoconf.h>\n\n\/* physical address of RAM (needed for correct __ram_phys_end symbol) *\/\n#define PHYS_RAM_ADDR    CONFIG_PHYS_RAM_ADDR\n\n\/* physical address where the kernel is loaded *\/\n#ifdef CONFIG_XIP\n  #define PHYS_LOAD_ADDR   CONFIG_PHYS_LOAD_ADDR\n#else  \/* !CONFIG_XIP *\/\n  #define PHYS_LOAD_ADDR   CONFIG_PHYS_RAM_ADDR\n#endif \/* CONFIG_XIP *\/\n\n\/* total shared RAM size (restore info + gdt) *\/\n#define BSP_SHARED_RAM_SIZE \\\n\tCONFIG_BSP_SHARED_GDT_RAM_SIZE+CONFIG_BSP_SHARED_RESTORE_INFO_SIZE\n\/*\n * When DEEP_SLEEP is not enabled, the shared memory can be re-used after boot.\n * Since the memory regions area are at fixed address locations, only the\n * contiguous unused memory located at the end of RAM should be made available.\n *\/\n#ifdef CONFIG_SYS_POWER_DEEP_SLEEP\n#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K - BSP_SHARED_RAM_SIZE\n#else\n#ifdef CONFIG_SET_GDT\n#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K\n#else\n#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K - CONFIG_BSP_SHARED_GDT_RAM_SIZE\n#endif\n#endif\n\nMEMORY\n    {\n#ifdef CONFIG_XIP\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K\n    RAM (wx)        : ORIGIN = PHYS_RAM_ADDR, LENGTH =  PHYS_RAM_SIZE\n#else  \/* !CONFIG_XIP *\/\n    RAM (wx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_SIZE\n#endif \/* CONFIG_XIP *\/\n#ifdef CONFIG_SYS_POWER_DEEP_SLEEP\n    BSP_SHARED_RAM (rw) : ORIGIN = CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR,\n                          LENGTH = CONFIG_BSP_SHARED_RESTORE_INFO_SIZE\n#endif \/* CONFIG_SYS_POWER_DEEP_SLEEP *\/\n#ifndef CONFIG_SET_GDT\n    BSP_SHARED_GDT_RAM (rw) : ORIGIN = CONFIG_BSP_SHARED_GDT_RAM_ADDR,\n                              LENGTH = CONFIG_BSP_SHARED_GDT_RAM_SIZE\n#endif \/* !CONFIG_SET_GDT *\/\n\n    \/*\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 2K, LENGTH = 2K\n    }\n\n#include <arch\/x86\/linker.ld>\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f1659ac582e90a753fd1e284501fb2c9e7bab244","subject":"Make less sections","message":"Make less sections\n","repos":"wichtounet\/thor-os,wichtounet\/thor-os","old_file":"kernel\/linker.ld","new_file":"kernel\/linker.ld","new_contents":"ENTRY(kernel_main)\n\nSECTIONS\n{\n    \/* This is where the micro kernel will load the code *\/\n\t. = 0x5000;\n\n    \/* 4K of code *\/\n\t.text BLOCK(1K) : ALIGN(1K)\n\t{\n\t\t*(main_section)\n\t\t*(.text)\n        *(.text.*)\n\t}\n\n\t\/* 4K of Read-only data *\/\n\t.rodata BLOCK(1K) : ALIGN(1K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* 4K of Read-write initialized data. *\/\n\t.data BLOCK(1K) : ALIGN(1K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* 4K of Read-write uninitialized data. *\/\n\t.bss BLOCK(1K) : ALIGN(1K)\n\t{\n\t\t*(.bss)\n\t}\n}","old_contents":"ENTRY(kernel_main)\n\nSECTIONS\n{\n    \/* This is where the micro kernel will load the code *\/\n\t. = 0x5000;\n\n    \/* 4K of code *\/\n\t.text BLOCK(1K) : ALIGN(1K)\n\t{\n\t\t*(main_section)\n\t\t*(.text)\n\t}\n\n\t\/* 4K of Read-only data *\/\n\t.rodata BLOCK(1K) : ALIGN(1K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* 4K of Read-write initialized data. *\/\n\t.data BLOCK(1K) : ALIGN(1K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* 4K of Read-write uninitialized data. *\/\n\t.bss BLOCK(1K) : ALIGN(1K)\n\t{\n\t\t*(.bss)\n\t}\n}","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f302be3e925aa300451a3caefb195de15bb0afe9","subject":"net: Introduce new NETWORK_RAM_SECTIONS() macro for common-ram.ld","message":"net: Introduce new NETWORK_RAM_SECTIONS() macro for common-ram.ld\n\nThis NETWORK_RAM_SECTIONS() macro can now be overridden (in board\nspecific linker.ld file) when one needs to force explicit placement\nof network interface' related elements.\n\nSigned-off-by: Lukasz Majewski <7acbb0643e3da1a0f6f894ebd720fb3807e67dff@denx.de>\n","repos":"nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/linker\/common-ram.ld","new_file":"include\/linker\/common-ram.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#if defined(CONFIG_NETWORKING)\n#ifndef NETWORK_RAM_SECTIONS\n#define NETWORK_RAM_SECTIONS \\\n\tZ_ITERABLE_SECTION_RAM(net_if, 4) \\\n\tZ_ITERABLE_SECTION_RAM(net_if_dev, 4) \\\n\tZ_ITERABLE_SECTION_RAM(net_l2, 4)\n#endif\n#endif \/* NETWORKING *\/\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_DATA_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_SYMS)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n\tSECTION_DATA_PROLOGUE(devices,,)\n\t{\n\t\t\/* link in devices objects, which are tied to the init ones;\n\t\t * the objects are thus sorted the same way as their init\n\t\t * object parent see include\/device.h\n\t\t *\/\n\t\t__device_start = .;\n\t\tCREATE_OBJ_LEVEL(device, PRE_KERNEL_1)\n\t\tCREATE_OBJ_LEVEL(device, PRE_KERNEL_2)\n\t\tCREATE_OBJ_LEVEL(device, POST_KERNEL)\n\t\tCREATE_OBJ_LEVEL(device, APPLICATION)\n\t\tCREATE_OBJ_LEVEL(device, SMP)\n\t\t__device_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(initshell,,)\n\t{\n\t\t\/* link in shell initialization objects for all modules that\n\t\t * use shell and their shell commands are automatically\n\t\t * initialized by the kernel.\n\t\t *\/\n\t\t__shell_module_start = .;\n\t\tKEEP(*(\".shell_module_*\"));\n\t\t__shell_module_end = .;\n\t\t__shell_cmd_start = .;\n\t\tKEEP(*(\".shell_cmd_*\"));\n\t\t__shell_cmd_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_dynamic_sections,,)\n\t{\n\t\t__log_dynamic_start = .;\n\t\tKEEP(*(SORT(.log_dynamic_*)));\n\t\t__log_dynamic_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_timer, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mem_slab, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mem_pool, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_heap, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mutex, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_stack, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_msgq, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mbox, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_pipe, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_sem, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_queue, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_condvar, 4)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area,,SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NETWORKING)\n\tNETWORK_RAM_SECTIONS\n#endif \/* NETWORKING *\/\n\n#if defined(CONFIG_UART_MUX)\n\tSECTION_DATA_PROLOGUE(uart_mux,,SUBALIGN(4))\n\t{\n\t\t__uart_mux_start = .;\n\t\t*(\".uart_mux.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".uart_mux.*\")))\n\t\t__uart_mux_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor,,SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(usb_data,,SUBALIGN(1))\n\t{\n\t\t__usb_data_start = .;\n\t\t*(\".usb.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.data*\")))\n\t\t__usb_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#if defined(CONFIG_USB_DEVICE_BOS)\n\tSECTION_DATA_PROLOGUE(usb_bos_desc,,SUBALIGN(1))\n\t{\n\t\t__usb_bos_desc_start = .;\n\t\t*(\".usb.bos_desc\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.bos_desc*\")))\n\t\t__usb_bos_desc_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_BOS *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_DATA_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_SYMS)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n\tSECTION_DATA_PROLOGUE(devices,,)\n\t{\n\t\t\/* link in devices objects, which are tied to the init ones;\n\t\t * the objects are thus sorted the same way as their init\n\t\t * object parent see include\/device.h\n\t\t *\/\n\t\t__device_start = .;\n\t\tCREATE_OBJ_LEVEL(device, PRE_KERNEL_1)\n\t\tCREATE_OBJ_LEVEL(device, PRE_KERNEL_2)\n\t\tCREATE_OBJ_LEVEL(device, POST_KERNEL)\n\t\tCREATE_OBJ_LEVEL(device, APPLICATION)\n\t\tCREATE_OBJ_LEVEL(device, SMP)\n\t\t__device_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(initshell,,)\n\t{\n\t\t\/* link in shell initialization objects for all modules that\n\t\t * use shell and their shell commands are automatically\n\t\t * initialized by the kernel.\n\t\t *\/\n\t\t__shell_module_start = .;\n\t\tKEEP(*(\".shell_module_*\"));\n\t\t__shell_module_end = .;\n\t\t__shell_cmd_start = .;\n\t\tKEEP(*(\".shell_cmd_*\"));\n\t\t__shell_cmd_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_dynamic_sections,,)\n\t{\n\t\t__log_dynamic_start = .;\n\t\tKEEP(*(SORT(.log_dynamic_*)));\n\t\t__log_dynamic_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tZ_ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_timer, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mem_slab, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mem_pool, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_heap, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mutex, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_stack, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_msgq, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_mbox, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_pipe, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_sem, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_queue, 4)\n\tZ_ITERABLE_SECTION_RAM_GC_ALLOWED(k_condvar, 4)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area,,SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NETWORKING)\n\tZ_ITERABLE_SECTION_RAM(net_if, 4)\n\tZ_ITERABLE_SECTION_RAM(net_if_dev, 4)\n\tZ_ITERABLE_SECTION_RAM(net_l2, 4)\n#endif \/* NETWORKING *\/\n\n#if defined(CONFIG_UART_MUX)\n\tSECTION_DATA_PROLOGUE(uart_mux,,SUBALIGN(4))\n\t{\n\t\t__uart_mux_start = .;\n\t\t*(\".uart_mux.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".uart_mux.*\")))\n\t\t__uart_mux_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor,,SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(usb_data,,SUBALIGN(1))\n\t{\n\t\t__usb_data_start = .;\n\t\t*(\".usb.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.data*\")))\n\t\t__usb_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#if defined(CONFIG_USB_DEVICE_BOS)\n\tSECTION_DATA_PROLOGUE(usb_bos_desc,,SUBALIGN(1))\n\t{\n\t\t__usb_bos_desc_start = .;\n\t\t*(\".usb.bos_desc\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.bos_desc*\")))\n\t\t__usb_bos_desc_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_BOS *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"49c09b6b1de357bba950288817125a87ebb08e8b","subject":"Remove heap allocation which is unused","message":"Remove heap allocation which is unused\n","repos":"bigclownlabs\/bc-core-module-sdk,bigclownlabs\/bc-core-module-sdk,bigclownlabs\/bc-core-module-sdk","old_file":"sys\/lkr\/stm32l083cz.ld","new_file":"sys\/lkr\/stm32l083cz.ld","new_contents":"\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20005000;    \/* end of RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x0;  \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 192K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data :\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20005000;    \/* end of RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x100;  \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 192K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data :\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"cd9fda84b3eac5554aa8bd7238bd881be6ce11bd","subject":"Change link base address from 0x0 to 0xC0000000","message":"Change link base address from 0x0 to 0xC0000000\n","repos":"waynecw\/cwos,waynecw\/cwos","old_file":"cwos.ld","new_file":"cwos.ld","new_contents":"ENTRY(_start)\nSECTIONS\n{\n\t. = 0xC0000000;  \/* QEMU versatilepb start address *\/\n\t.text : { \n\t\t_text = .;\n\t\tboot.o (interrupt_vector)\n\t\t*(.text)\n\t\t_etext = .;\n\t}\n\n\t.rodata : {\n\t\t_rodata = .;\n\t\t*(.rodata)\n\t\t_erodata = .;\n\t}\n\n\t.data : { \n\t\t_data = .;\n\t\t*(.data) \n\t\t_edata = .;\n\t}\n\t.bss : {\n\t\t_bss = .;\n\t\t*(.bss)\n\t\t*(COMMON)\n\t\t_ebss = .;\n\t} \n\n\t. = ALIGN(0x1000);\n\n\tkernel_stack_top = .;\n\t. += 0x1000;\n\tkernel_stack_start = .;\n\t. += 0x1000;\n\tirq_stack_start = .;\n}\n","old_contents":"ENTRY(_start)\nSECTIONS\n{\n\t. = 0x00000000;  \/* QEMU versatilepb start address *\/\n\t.text : { \n\t\t_text = .;\n\t\tboot.o (interrupt_vector)\n\t\t*(.text)\n\t\t_etext = .;\n\t}\n\n\t.rodata : {\n\t\t_rodata = .;\n\t\t*(.rodata)\n\t\t_erodata = .;\n\t}\n\n\t.data : { \n\t\t_data = .;\n\t\t*(.data) \n\t\t_edata = .;\n\t}\n\t.bss : {\n\t\t_bss = .;\n\t\t*(.bss)\n\t\t*(COMMON)\n\t\t_ebss = .;\n\t} \n\n\t. = ALIGN(0x1000);\n\n\tkernel_stack_top = .;\n\t. += 0x1000;\n\tkernel_stack_start = .;\n\t. += 0x1000;\n\tirq_stack_start = .;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"2a9f400f9008526215825dc75a3e2da5134aa99c","subject":"[arch][arm64] move the exception table after .text.boot","message":"[arch][arm64] move the exception table after .text.boot\n\nThis puts _start at the beginning of a flattened binary, which\nmakes it slightly easier to read, at the expense of adding a bit\nmore padding to get the exception table (.text.boot.vectab) aligned\non a 4K boundary.\n","repos":"sndnvaps\/lk,travisg\/lk,nvll\/lk,travisg\/lk,GCrean\/lk,travisg\/lk,littlekernel\/lk,sndnvaps\/lk,minglun-tsai\/lk,skabet\/lk,hollanderic\/lkstuff,hollanderic\/lkstuff,GCrean\/lk,skabet\/lk,srodrig1\/lk,srodrig1\/lk,nvll\/lk,M1cha\/lk,M1cha\/lk,grub4android\/lk,GCrean\/lk,srodrig1\/lk,GCrean\/lk,littlekernel\/lk,skabet\/lk,hollanderic\/lkstuff,grub4android\/lk,sndnvaps\/lk,M1cha\/lk,skabet\/lk,grub4android\/lk,sndnvaps\/lk,ErikCorryGoogle\/lk,littlekernel\/lk,GCrean\/lk,srodrig1\/lk,sndnvaps\/lk,littlekernel\/lk,minglun-tsai\/lk,skabet\/lk,M1cha\/lk,srodrig1\/lk,minglun-tsai\/lk,nvll\/lk,ErikCorryGoogle\/lk,minglun-tsai\/lk,ErikCorryGoogle\/lk,nvll\/lk,grub4android\/lk,grub4android\/lk,M1cha\/lk,travisg\/lk,hollanderic\/lkstuff,ErikCorryGoogle\/lk,nvll\/lk","old_file":"arch\/arm64\/system-onesegment.ld","new_file":"arch\/arm64\/system-onesegment.ld","new_contents":"OUTPUT_FORMAT(\"elf64-littleaarch64\", \"elf64-bigaarch64\", \"elf64-littleaarch64\")\nOUTPUT_ARCH(aarch64)\n\nENTRY(_start)\nSECTIONS\n{\n    . = %MEMBASE%;\n\n    \/* text\/read-only data *\/\n    .text : {\n        KEEP(*(.text.boot))\n        KEEP(*(.text.boot.vectab))\n        *(.text* .sram.text.glue_7* .gnu.linkonce.t.*)\n    }\n\n    .interp : { *(.interp) }\n    .hash : { *(.hash) }\n    .dynsym : { *(.dynsym) }\n    .dynstr : { *(.dynstr) }\n    .rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) }\n    .rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) }\n    .rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) }\n    .rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) }\n    .rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }\n    .rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }\n    .rel.got : { *(.rel.got) }\n    .rela.got : { *(.rela.got) }\n    .rel.ctors : { *(.rel.ctors) }\n    .rela.ctors : { *(.rela.ctors) }\n    .rel.dtors : { *(.rel.dtors) }\n    .rela.dtors : { *(.rela.dtors) }\n    .rel.init : { *(.rel.init) }\n    .rela.init : { *(.rela.init) }\n    .rel.fini : { *(.rel.fini) }\n    .rela.fini : { *(.rela.fini) }\n    .rel.bss : { *(.rel.bss) }\n    .rela.bss : { *(.rela.bss) }\n    .rel.plt : { *(.rel.plt) }\n    .rela.plt : { *(.rela.plt) }\n    .init : { *(.init) } =0x9090\n    .plt : { *(.plt) }\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n    __exidx_end = .;\n\n    .rodata : ALIGN(8) {\n        __rodata_start = .;\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\nINCLUDE \"arch\/shared_rodata_sections.ld\"\n        . = ALIGN(8);\n        __rodata_end = .;\n    }\n\n\n    .data : ALIGN(8) {\n        \/* writable data  *\/\n        __data_start_rom = .;\n        \/* in one segment binaries, the rom data address is on top of the ram data address *\/\n        __data_start = .;\n        *(.data .data.* .gnu.linkonce.d.*)\nINCLUDE \"arch\/shared_data_sections.ld\"\n    }\n\n    .ctors : ALIGN(8) {\n        __ctor_list = .;\n        KEEP(*(.ctors .init_array))\n        __ctor_end = .;\n    }\n    .dtors : ALIGN(8) {\n        __dtor_list = .;\n        KEEP(*(.dtors .fini_array))\n        __dtor_end = .;\n    }\n    .got : { *(.got.plt) *(.got) }\n    .dynamic : { *(.dynamic) }\n\n    __data_end = .;\n\n    \/* unintialized data (in same segment as writable data) *\/\n    .bss : ALIGN(8) {\n        KEEP(*(.bss.prebss.*))\n        . = ALIGN(8);\n        __bss_start = .;\n        *(.bss .bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end = .;\n    }\n\n    . = ALIGN(8);\n    _end = .;\n\n    . = %MEMBASE% + %MEMSIZE%;\n    _end_of_ram = .;\n\n    \/* Strip unnecessary stuff *\/\n    \/DISCARD\/ : { *(.comment .note .eh_frame) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf64-littleaarch64\", \"elf64-bigaarch64\", \"elf64-littleaarch64\")\nOUTPUT_ARCH(aarch64)\n\nENTRY(_start)\nSECTIONS\n{\n    . = %MEMBASE%;\n\n    \/* text\/read-only data *\/\n    .text : {\n        KEEP(*(.text.boot.vectab))\n        KEEP(*(.text.boot))\n        *(.text* .sram.text.glue_7* .gnu.linkonce.t.*)\n    }\n\n    .interp : { *(.interp) }\n    .hash : { *(.hash) }\n    .dynsym : { *(.dynsym) }\n    .dynstr : { *(.dynstr) }\n    .rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) }\n    .rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) }\n    .rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) }\n    .rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) }\n    .rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }\n    .rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }\n    .rel.got : { *(.rel.got) }\n    .rela.got : { *(.rela.got) }\n    .rel.ctors : { *(.rel.ctors) }\n    .rela.ctors : { *(.rela.ctors) }\n    .rel.dtors : { *(.rel.dtors) }\n    .rela.dtors : { *(.rela.dtors) }\n    .rel.init : { *(.rel.init) }\n    .rela.init : { *(.rela.init) }\n    .rel.fini : { *(.rel.fini) }\n    .rela.fini : { *(.rela.fini) }\n    .rel.bss : { *(.rel.bss) }\n    .rela.bss : { *(.rela.bss) }\n    .rel.plt : { *(.rel.plt) }\n    .rela.plt : { *(.rela.plt) }\n    .init : { *(.init) } =0x9090\n    .plt : { *(.plt) }\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n    __exidx_end = .;\n\n    .rodata : ALIGN(8) {\n        __rodata_start = .;\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\nINCLUDE \"arch\/shared_rodata_sections.ld\"\n        . = ALIGN(8);\n        __rodata_end = .;\n    }\n\n\n    .data : ALIGN(8) {\n        \/* writable data  *\/\n        __data_start_rom = .;\n        \/* in one segment binaries, the rom data address is on top of the ram data address *\/\n        __data_start = .;\n        *(.data .data.* .gnu.linkonce.d.*)\nINCLUDE \"arch\/shared_data_sections.ld\"\n    }\n\n    .ctors : ALIGN(8) {\n        __ctor_list = .;\n        KEEP(*(.ctors .init_array))\n        __ctor_end = .;\n    }\n    .dtors : ALIGN(8) {\n        __dtor_list = .;\n        KEEP(*(.dtors .fini_array))\n        __dtor_end = .;\n    }\n    .got : { *(.got.plt) *(.got) }\n    .dynamic : { *(.dynamic) }\n\n    __data_end = .;\n\n    \/* unintialized data (in same segment as writable data) *\/\n    .bss : ALIGN(8) {\n        KEEP(*(.bss.prebss.*))\n        . = ALIGN(8);\n        __bss_start = .;\n        *(.bss .bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end = .;\n    }\n\n    . = ALIGN(8);\n    _end = .;\n\n    . = %MEMBASE% + %MEMSIZE%;\n    _end_of_ram = .;\n\n    \/* Strip unnecessary stuff *\/\n    \/DISCARD\/ : { *(.comment .note .eh_frame) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"956a767cd645c8974c84b0450fcfd3b23b850f76","subject":"soc: arm: Fix SDRAM linker section size for i.mx rt","message":"soc: arm: Fix SDRAM linker section size for i.mx rt\n\nChange DT_REG_REG ==> DT_REG_SIZE for the SDRAM node\n\nSigned-off-by: Crist Xu <ffe113f03f779dde93f0683abcc2258a010b0e8a@nxp.com>\n","repos":"galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr","old_file":"soc\/arm\/nxp_imx\/rt\/linker.ld","new_file":"soc\/arm\/nxp_imx\/rt\/linker.ld","new_contents":"\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n #include <autoconf.h>\n #include <devicetree.h>\n\nMEMORY\n     {\n#if (DT_REG_SIZE(DT_NODELABEL(ocram)) > 0) && !defined(CONFIG_DATA_OCRAM)\n        OCRAM  (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ocram)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ocram))\n#endif\n#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !defined(CONFIG_DATA_SEMC)\n        SDRAM  (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0))\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm)) > 0) && !defined(CONFIG_DATA_DTCM)\n        DTCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_dtcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm))\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_itcm)) > 0) && !defined(CONFIG_CODE_ITCM)\n        ITCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_itcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_itcm))\n#endif\n     }\n\n#include <arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld>\n","old_contents":"\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n #include <autoconf.h>\n #include <devicetree.h>\n\nMEMORY\n     {\n#if (DT_REG_SIZE(DT_NODELABEL(ocram)) > 0) && !defined(CONFIG_DATA_OCRAM)\n        OCRAM  (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ocram)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ocram))\n#endif\n#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !defined(CONFIG_DATA_SEMC)\n        SDRAM  (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_ADDR(DT_NODELABEL(sdram0))\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm)) > 0) && !defined(CONFIG_DATA_DTCM)\n        DTCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_dtcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_dtcm))\n#endif\n#if (DT_REG_SIZE(DT_INST(0, nxp_imx_itcm)) > 0) && !defined(CONFIG_CODE_ITCM)\n        ITCM    (wx) : ORIGIN = DT_REG_ADDR(DT_INST(0, nxp_imx_itcm)), LENGTH = DT_REG_SIZE(DT_INST(0, nxp_imx_itcm))\n#endif\n     }\n\n#include <arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld>\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"08a962daa2fd2bc9fac3e4e80169047a7a0b328c","subject":"x86: place application data before kernel data","message":"x86: place application data before kernel data\n\nKernel data size shifts in between linker passes due to the addition\nof the page tables. We would like application memory bounds to\nremain fixed so that we can program the MMU permissions for it\nat build time.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"finikorg\/zephyr,punitvara\/zephyr,fbsder\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,mbolivar\/zephyr,aceofall\/zephyr-iotos,mbolivar\/zephyr,rsalveti\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,nashif\/zephyr,Vudentz\/zephyr,rsalveti\/zephyr,runchip\/zephyr-cc3220,ldts\/zephyr,Vudentz\/zephyr,explora26\/zephyr,galak\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3220,GiulianoFranchetto\/zephyr,runchip\/zephyr-cc3220,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,fbsder\/zephyr,zephyriot\/zephyr,fbsder\/zephyr,zephyriot\/zephyr,zephyriot\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,ldts\/zephyr,ldts\/zephyr,finikorg\/zephyr,nashif\/zephyr,aceofall\/zephyr-iotos,runchip\/zephyr-cc3220,zephyrproject-rtos\/zephyr,punitvara\/zephyr,fbsder\/zephyr,explora26\/zephyr,explora26\/zephyr,mbolivar\/zephyr,explora26\/zephyr,explora26\/zephyr,punitvara\/zephyr,punitvara\/zephyr,nashif\/zephyr,mbolivar\/zephyr,zephyriot\/zephyr,Vudentz\/zephyr,rsalveti\/zephyr,runchip\/zephyr-cc3220,finikorg\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,kraj\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,mbolivar\/zephyr,nashif\/zephyr,rsalveti\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,GiulianoFranchetto\/zephyr,aceofall\/zephyr-iotos,rsalveti\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,kraj\/zephyr,zephyriot\/zephyr,kraj\/zephyr","old_file":"include\/arch\/x86\/linker.ld","new_file":"include\/arch\/x86\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\n\t\/* This align directive needs to be after __data_rom_start or XIP\n\t * won't be copying the data from the right LMA\n\t *\/\n\tMMU_PAGE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t_image_ram_start = .;\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t\tMMU_PAGE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_X86_STACK_PROTECTION\n#define GDT_NUM_ENTRIES\t5\n#else \/* CONFIG_X86_STACK_PROTECTION *\/\n#define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_STACK_PROTECTION *\/\n\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_MMU\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n#endif\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\t\/* All stacks go in kernel's noinit, regardless of where they\n\t * were defined.\n\t *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\tMMU_PAGE_ALIGN\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t\/* Define linker symbols *\/\n\t__kernel_ram_end = .;\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#define _LINKER\n\n#define _ASMLANGUAGE\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <misc\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\tGROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = PHYS_LOAD_ADDR;\n\t_image_text_start = PHYS_LOAD_ADDR;\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)\n\t{\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif\n\n#ifndef CONFIG_X86_FIXED_IRQ_MAPPING\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t__data_rom_start = ALIGN(4);\t\t\/* XIP imaged DATA ROMABLE_REGION start addr *\/\n\n\t\/* This align directive needs to be after __data_rom_start or XIP\n\t * won't be copying the data from the right LMA\n\t *\/\n\tMMU_PAGE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t__data_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt_ram_data))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_X86_STACK_PROTECTION\n#define GDT_NUM_ENTRIES\t5\n#else \/* CONFIG_X86_STACK_PROTECTION *\/\n#define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_STACK_PROTECTION *\/\n\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_MMU\n\t\/* Page Tables are located here if MMU is enabled.*\/\n\tMMU_PAGE_ALIGN\n\t__mmu_tables_start = .;\n\tKEEP(*(.mmu_data));\n\t__mmu_tables_end = .;\n#endif\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\n\t. = ALIGN(4);\n\n\t__bss_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\tKERNEL_INPUT_SECTION(.noinit)\n\tKERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\t\/* All stacks go in kernel's noinit, regardless of where they\n\t * were defined.\n\t *\/\n\t*(.stacks)\n\t*(\".stacks.*\")\n\n\t__kernel_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tMMU_PAGE_ALIGN\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList, (OPTIONAL),)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\t__INT_LIST_START__ = .;\n\tLONG((__INT_LIST_END__ - __INT_LIST_START__) \/ __ISR_LIST_SIZEOF)\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t__INT_LIST_END__ = .;\n\t} > IDT_LIST\n\n#ifdef CONFIG_X86_MMU\n\t\/* Memory management unit*\/\n\tSECTION_PROLOGUE(mmulist, (OPTIONAL),)\n\t{\n\t\/* get size of the mmu lists needed for gen_mmu.py*\/\n\tLONG((__MMU_LIST_END__ - __MMU_LIST_START__) \/ __MMU_REGION_SIZEOF)\n\t\/* Get the start of mmu tables in data section so that the address\n\t * of the page tables can be calculated.\n\t *\/\n\tLONG(__mmu_tables_start)\n\t__MMU_LIST_START__ = .;\n\tKEEP(*(.mmulist))\n\t__MMU_LIST_END__ = .;\n\t} > MMU_LIST\n#endif \/* CONFIG_X86_MMU *\/\n\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\tKEEP(*(.mmulist))\n\t}\n#endif\n\n\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#ifdef CONFIG_APPLICATION_MEMORY\n__app_data_size = (__app_data_ram_end - __app_data_ram_start);\n__app_data_num_words = (__app_data_size + 3) >> 2;\n#endif\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8328d6df760a3f31f860bf69d7873bc1ecbf8817","subject":"linker: nios2: align rodata section","message":"linker: nios2: align rodata section\n\nDuring testing with sorting section by alignment with qemu_nios2,\nif rodata section is not aligned on 4-byte boundary and its size\nnot of multiple of 4, it would never boot correctly. So align\nthe rodata here. This is in preparation to enable the linker\noption to sort sections by alignment.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"finikorg\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,ldts\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,ldts\/zephyr,Vudentz\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,ldts\/zephyr,nashif\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,ldts\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr","old_file":"include\/arch\/nios2\/linker.ld","new_file":"include\/arch\/nios2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specfic linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to\n     * 'nios2-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n        {\n        *(.plt)\n        }\n\n    SECTION_PROLOGUE(.iplt,,)\n        {\n        *(.iplt)\n        }\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n#ifndef CONFIG_XIP\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined(CONFIG_GP_ALL_DATA)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        . = ALIGN(4);\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n        . = ALIGN(4);\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_DATA_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n\n#include <linker\/common-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n        *(.data)\n        *(\".data.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n        \/* the Nios2 architecture only has 16-bit signed immediate offsets in\n         * the instructions, so accessing a general address requires typically\n         * three instructions - basically, two for the two halves of the 32-bit\n         * address, and one to merge them - but if we can put the most commonly\n         * accessed globals in a special 64K span of memory addressed by the GP\n         * register, then we can access those values in a single instruction,\n         * saving both codespace and runtime.\n         *\n         * Since these immediate offsets are signed, place gp 0x8000 past the\n         * beginning of .sdata so that we can use both positive and negative\n         * offsets.\n         *\/\n#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n        *(.sdata .sdata.* .gnu.linkonce.s.*)\n        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_ram_end = .;\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.sbss)\n        *(\".sbss.*\")\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    }\n\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specfic linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to\n     * 'nios2-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n        {\n        *(.plt)\n        }\n\n    SECTION_PROLOGUE(.iplt,,)\n        {\n        *(.iplt)\n        }\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n#ifndef CONFIG_XIP\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined(CONFIG_GP_ALL_DATA)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_DATA_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n\n#include <linker\/common-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n        *(.data)\n        *(\".data.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n        \/* the Nios2 architecture only has 16-bit signed immediate offsets in\n         * the instructions, so accessing a general address requires typically\n         * three instructions - basically, two for the two halves of the 32-bit\n         * address, and one to merge them - but if we can put the most commonly\n         * accessed globals in a special 64K span of memory addressed by the GP\n         * register, then we can access those values in a single instruction,\n         * saving both codespace and runtime.\n         *\n         * Since these immediate offsets are signed, place gp 0x8000 past the\n         * beginning of .sdata so that we can use both positive and negative\n         * offsets.\n         *\/\n#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n        *(.sdata .sdata.* .gnu.linkonce.s.*)\n        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_ram_end = .;\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.sbss)\n        *(\".sbss.*\")\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    }\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"11106cc87dfece281c55300b64d44650f4868779","subject":"fix(docs) fix readme name (#6414)","message":"fix(docs) fix readme name (#6414)\n\nCommon mistake originating from case-insensitive Macs.\r\nAligns casing to also work on unix.","repos":"Kong\/kong,Kong\/kong,Kong\/kong","old_file":"spec\/config.ld","new_file":"spec\/config.ld","new_contents":"project='Kong test helpers'\ntitle='Kong test framework'\ndescription='Test helper functions for Kong (integration) testing'\nformat='markdown'\nfile='.\/'\ndir='docs'\nreadme='README.md'\nsort=true\nsort_modules=true\nstyle='.\/'\nno_space_before_args=true\n","old_contents":"project='Kong test helpers'\ntitle='Kong test framework'\ndescription='Test helper functions for Kong (integration) testing'\nformat='markdown'\nfile='.\/'\ndir='docs'\nreadme='readme.md'\nsort=true\nsort_modules=true\nstyle='.\/'\nno_space_before_args=true\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"eba974b6c1935f198a135d905d0919f3b2a6e7c7","subject":"Fixed memory size issue in MX460 linker script file. Added MX460 updated avrdude.conf files to Mac and Linux.","message":"Fixed memory size issue in MX460 linker script file. Added MX460 updated avrdude.conf files to Mac and Linux.\n\n\nFormer-commit-id: ce5d03105883543b353fb76264dd8930b2dccb51\n","repos":"chipKIT32\/chipkit-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,EmbeddedMan\/chipKIT-core,adamwolf\/chipKIT-core,adamwolf\/chipKIT-core,chipKIT32\/chipkit-core,pontech\/chipKIT-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core,chipKIT32\/chipkit-core,ricklon\/chipKIT-core,adamwolf\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,chipKIT32\/chipkit-core,pontech\/chipKIT-core,UECIDE\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,majenkotech\/chipKIT-core,UECIDE\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,EmbeddedMan\/chipKIT-core,UECIDE\/chipKIT-core,UECIDE\/chipKIT-core,pontech\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,adamwolf\/chipKIT-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,UECIDE\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,chipKIT32\/chipkit-core","old_file":"pic32\/cores\/pic32\/chipKIT-application-32MX460F512L.ld","new_file":"pic32\/cores\/pic32\/chipKIT-application-32MX460F512L.ld","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\n_ebase_address  = 0x9D000000;\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_RESET_ADDR              = 0x9D001000;\n_EEPROM_ADDR             = 0x9D07F000;\n_BEV_EXCPT_ADDR          = 0xBFC00380;\n_DBG_EXCPT_ADDR          = 0xBFC00480;\n_DBG_CODE_ADDR           = 0xBFC02000;\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7E000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 \n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x8000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\nSECTIONS\n{\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg0_program_mem\n  \n  .eeprom_pic32 _EEPROM_ADDR :\n  { \n    . += 0x1000;\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n  .vector_0 _ebase_address + 0x200 :\n  {\n    KEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n\n    _text_end = . ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }>kseg0_program_mem\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n  }>kseg0_program_mem\n\n\n  \/* Read-only sections *\/\n  .rodata   :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } >kseg1_data_mem\n  .data  ALIGN(4)  :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _data_image_begin = LOADADDR(.data) ;\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit8           :\n  {\n    *(.lit8)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    _sbss_end = . ;\n  } >kseg1_data_mem\n  .bss ALIGN(4)  :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  \/DISCARD\/         : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  \/DISCARD\/         : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\n_ebase_address  = 0x9D000000;\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_RESET_ADDR              = 0x9D001000;\n_EEPROM_ADDR             = 0x9D07C000;\n_BEV_EXCPT_ADDR          = 0xBFC00380;\n_DBG_EXCPT_ADDR          = 0xBFC00480;\n_DBG_CODE_ADDR           = 0xBFC02000;\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7B000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x4000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 \n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\nSECTIONS\n{\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg0_program_mem\n  \n  .eeprom_pic32 _EEPROM_ADDR :\n  { \n    . += 0x4000;\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n  .vector_0 _ebase_address + 0x200 :\n  {\n    KEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n\n    _text_end = . ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }>kseg0_program_mem\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n  }>kseg0_program_mem\n\n\n  \/* Read-only sections *\/\n  .rodata   :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } >kseg1_data_mem\n  .data  ALIGN(4)  :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _data_image_begin = LOADADDR(.data) ;\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit8           :\n  {\n    *(.lit8)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    _sbss_end = . ;\n  } >kseg1_data_mem\n  .bss ALIGN(4)  :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  \/DISCARD\/         : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  \/DISCARD\/         : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"eeba84b5b5de2ecbe8473f076e2fbcc50bc9c15f","subject":"arm: fix __kernel","message":"arm: fix __kernel\n\nThis wasn't working properly with CONFIG_APPLICATION_MEMORY enabled as\nthe sections weren't handled in the linker script.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"nashif\/zephyr,mbolivar\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,explora26\/zephyr,galak\/zephyr,fbsder\/zephyr,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,aceofall\/zephyr-iotos,Vudentz\/zephyr,explora26\/zephyr,nashif\/zephyr,nashif\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,explora26\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,finikorg\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,nashif\/zephyr,mbolivar\/zephyr,Vudentz\/zephyr,ldts\/zephyr,kraj\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,aceofall\/zephyr-iotos,punitvara\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,mbolivar\/zephyr,galak\/zephyr,fbsder\/zephyr,nashif\/zephyr,aceofall\/zephyr-iotos,galak\/zephyr,aceofall\/zephyr-iotos,Vudentz\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,punitvara\/zephyr,explora26\/zephyr,ldts\/zephyr,ldts\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,kraj\/zephyr,finikorg\/zephyr,ldts\/zephyr,kraj\/zephyr,fbsder\/zephyr,mbolivar\/zephyr,fbsder\/zephyr,GiulianoFranchetto\/zephyr,zephyriot\/zephyr,fbsder\/zephyr,GiulianoFranchetto\/zephyr,zephyriot\/zephyr,zephyriot\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t_vector_start = .;\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t_vector_start = .;\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b2c2ab9b280a8a45305961d5ba6abcc043992299","subject":"Added .ramprog section for easier moving code into RAM","message":"Added .ramprog section for easier moving code into RAM\n","repos":"Stephane-D\/SGDK,Stephane-D\/SGDK,Stephane-D\/SGDK","old_file":"md.ld","new_file":"md.ld","new_contents":"OUTPUT_ARCH(m68k)\r\nSEARCH_DIR(.)\r\n\/*GROUP(-lbcc -lc -lgcc)*\/\r\n__DYNAMIC  =  0;\r\n\r\n\/*\r\n * Setup the memory map of the SEGA Genesis.\r\n * stack grows down from high memory.\r\n *\r\n * The memory map look like this:\r\n * +--------------------+ <- low memory\r\n * | .text              |\r\n * |        _etext      |\r\n * |        ctor list   | the ctor and dtor lists are for\r\n * |        dtor list   | C++ support\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * +--------------------+ <- 0xE0FF0000\r\n * | .data              | initialized data goes here\r\n * |        _data       |\r\n * |        _edata      |\r\n * +--------------------+\r\n * | .bss               |\r\n * |        _bstart     | start of bss, cleared by crt0\r\n * |        _bend       | start of heap, used by sbrk()\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * |        __stack     | top of stack\r\n * +--------------------+ <- 0xE1000000\r\n *\/\r\nMEMORY\r\n{\r\n\trom (rx) : ORIGIN = 0x00000000, LENGTH = 0xE0000000\r\n\tram : ORIGIN = 0xE0FF0000, LENGTH = 0x00010000\r\n}\r\n\r\n\/*\r\n * allocate the stack to be at the top of memory, since the stack\r\n * grows down\r\n *\/\r\n\r\nPROVIDE (__stack = 0xE1000000);\r\n\r\n\r\nSECTIONS\r\n{\r\n  .text 0x00000000:\r\n  {\r\n    KEEP(*(.text.keepboot)) *(.text.*) *(.text)\r\n    . = ALIGN(0x4);\r\n     __CTOR_LIST__ = .;\r\n    LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\r\n    *(.ctors)\r\n    LONG(0)\r\n    __CTOR_END__ = .;\r\n    __DTOR_LIST__ = .;\r\n    LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\r\n    *(.dtors)\r\n     LONG(0)\r\n    __DTOR_END__ = .;\r\n\r\n    *(.rodata .rodata.*)\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n\r\n    . = ALIGN(0x4);\r\n    __INIT_SECTION__ = . ;\r\n    *(.init)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    __FINI_SECTION__ = . ;\r\n    *(.fini)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    _etext = .;\r\n    *(.lit)\r\n\r\n    *(.rodata_bin)\r\n    *(.rodata_binf)\r\n  } > rom\r\n  _stext = SIZEOF (.text);\r\n\r\n  .data 0xE0FF0000 :\r\n  AT ( ADDR (.text) + SIZEOF (.text) )\r\n  {\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.*)\r\n    *(.ramprog .ramprog.*)\r\n    _edata = .;\r\n  } > ram\r\n  _sdata = SIZEOF (.data);\r\n\r\n  .bss 0xE0FF0000 + SIZEOF (.data) :\r\n  {\r\n    _start = . ;\r\n    *(.shbss)\r\n    *(.bss .bss.*)\r\n    *(COMMON)\r\n    _bend = . ;\r\n  } > ram\r\n\r\n  .stab 0 (NOLOAD) :\r\n  {\r\n    *(.stab)\r\n  }\r\n\r\n  .stabstr 0 (NOLOAD) :\r\n  {\r\n    *(.stabstr)\r\n  }\r\n\r\n  .eh_frame 0 (NOLOAD) :\r\n  {\r\n    *(.eh_frame)\r\n  }\r\n}\r\n","old_contents":"OUTPUT_ARCH(m68k)\r\nSEARCH_DIR(.)\r\n\/*GROUP(-lbcc -lc -lgcc)*\/\r\n__DYNAMIC  =  0;\r\n\r\n\/*\r\n * Setup the memory map of the SEGA Genesis.\r\n * stack grows down from high memory.\r\n *\r\n * The memory map look like this:\r\n * +--------------------+ <- low memory\r\n * | .text              |\r\n * |        _etext      |\r\n * |        ctor list   | the ctor and dtor lists are for\r\n * |        dtor list   | C++ support\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * +--------------------+ <- 0xE0FF0000\r\n * | .data              | initialized data goes here\r\n * |        _data       |\r\n * |        _edata      |\r\n * +--------------------+\r\n * | .bss               |\r\n * |        _bstart     | start of bss, cleared by crt0\r\n * |        _bend       | start of heap, used by sbrk()\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * |        __stack     | top of stack\r\n * +--------------------+ <- 0xE1000000\r\n *\/\r\nMEMORY\r\n{\r\n\trom (rx) : ORIGIN = 0x00000000, LENGTH = 0xE0000000\r\n\tram : ORIGIN = 0xE0FF0000, LENGTH = 0x00010000\r\n}\r\n\r\n\/*\r\n * allocate the stack to be at the top of memory, since the stack\r\n * grows down\r\n *\/\r\n\r\nPROVIDE (__stack = 0xE1000000);\r\n\r\n\r\nSECTIONS\r\n{\r\n  .text 0x00000000:\r\n  {\r\n    KEEP(*(.text.keepboot)) *(.text.*) *(.text)\r\n    . = ALIGN(0x4);\r\n     __CTOR_LIST__ = .;\r\n    LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\r\n    *(.ctors)\r\n    LONG(0)\r\n    __CTOR_END__ = .;\r\n    __DTOR_LIST__ = .;\r\n    LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\r\n    *(.dtors)\r\n     LONG(0)\r\n    __DTOR_END__ = .;\r\n\r\n    *(.rodata .rodata.*)\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n\r\n    . = ALIGN(0x4);\r\n    __INIT_SECTION__ = . ;\r\n    *(.init)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    __FINI_SECTION__ = . ;\r\n    *(.fini)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    _etext = .;\r\n    *(.lit)\r\n\r\n    *(.rodata_bin)\r\n    *(.rodata_binf)\r\n  } > rom\r\n  _stext = SIZEOF (.text);\r\n\r\n  .data 0xE0FF0000 :\r\n  AT ( ADDR (.text) + SIZEOF (.text) )\r\n  {\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.*)\r\n    _edata = .;\r\n  } > ram\r\n  _sdata = SIZEOF (.data);\r\n\r\n  .bss 0xE0FF0000 + SIZEOF (.data) :\r\n  {\r\n    _start = . ;\r\n    *(.shbss)\r\n    *(.bss .bss.*)\r\n    *(COMMON)\r\n    _bend = . ;\r\n  } > ram\r\n\r\n  .stab 0 (NOLOAD) :\r\n  {\r\n    *(.stab)\r\n  }\r\n\r\n  .stabstr 0 (NOLOAD) :\r\n  {\r\n    *(.stabstr)\r\n  }\r\n\r\n  .eh_frame 0 (NOLOAD) :\r\n  {\r\n    *(.eh_frame)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"52f547f56a92756992f178392fa7f037f45be956","subject":"[bsp][bluetrum] add cpp support","message":"[bsp][bluetrum] add cpp support\n","repos":"ArdaFu\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,armink\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread","old_file":"bsp\/bluetrum\/ab32vg1-ab-prougen\/link.lds","new_file":"bsp\/bluetrum\/ab32vg1-ab-prougen\/link.lds","new_contents":"\/* Define the flash max size *\/\n__max_flash_size = 1024k;\n\n__data_ram_size = 8k;\n__stack_ram_size = 4k;\n__comm_ram_size = 83k;\n__heap_ram_size = 29k;\n\n__base = 0x10000000;\n\n__data_vma = 0x11000;\n__stack_vma = __data_vma + __data_ram_size;\n__comm_vma = __stack_vma + __stack_ram_size;\n__heap_vma = __comm_vma + __comm_ram_size;\n\n__ram1_vma = 0x50000;\n\nMEMORY\n{\n    init            : org = __base,             len = 512\n    flash(rx)       : org = __base + 512,       len = __max_flash_size\n    comm(rx)        : org = __comm_vma,         len = __comm_ram_size\n\n    data            : org = __data_vma,         len = __data_ram_size\n    stack           : org = __stack_vma,        len = __stack_ram_size\n    heap            : org = __heap_vma,         len = __heap_ram_size\n    ram1(rx)        : org = __ram1_vma,         len = 0x7a00\n}\n\nSECTIONS\n{\n    .init : {\n        *(.reset)\n    } > init\n\n    .ram1 __ram1_vma : {\n        . = ALIGN(4);\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n        *components*drivers**.o (.text*)\n        *device.o (.text*)\n        *components.o (.text*)\n        *idle.o (.text*)\n    } > ram1 AT > flash\n\n    .rti : {\n        . = ALIGN(4);\n        \/* section information for initial *\/\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(32);\n    } > ram1 AT > flash\n\n    .comm : {\n        . = ALIGN(4);\n        KEEP(*(.vector))\n        EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *romfs.o \n        *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o\n        *letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o\n        *trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o) *(.text)\n        *finsh*shell.o (.text*)\n        *(.text.unlikely)\n        *(.text.startup)\n        EXCLUDE_FILE (*components*libc**.o *romfs.o *lib_a**.o *cp-demangle.o\n        *divdf3.o *muldf3.o *multf3.o *unwind*.o *_clz.o) *(.rodata)\n        *(.rodata.name)\n        EXCLUDE_FILE(*lib_a**.o *cp-demangle.o) *(.rodata.str1.4)\n        EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata)\n        *(.rela*)\n        *(.data*)\n\t    *(.sdata*)\n    } > comm AT > flash\n\n    .bss (NOLOAD):\n    {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.sbss)\n        *(.buf*)\n        __bss_end = .;\n    } > data\n    __bss_size = __bss_end - __bss_start;\n\n    .stack (NOLOAD) : {\n        __irq_stack_start = .;\n        . = __stack_ram_size;\n        __irq_stack = .;\n    } > stack\n    __irq_stack_size = __irq_stack - __irq_stack_start;\n\n    .heap (NOLOAD) : {\n        __heap_start = .;\n        . = __heap_ram_size;\n        __heap_end = .;\n    } > heap\n\n    .flash : {\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*)\n        . = ALIGN(512);\n    } > flash\n}\n\n\/* Calc the lma *\/\n__bank_size = SIZEOF(.flash);\n__comm_lma = LOADADDR(.comm);\n__comm_size = SIZEOF(.comm);\n__ram1_lma = LOADADDR(.ram1);\n__ram1_size = SIZEOF(.ram1) + SIZEOF(.rti);\n","old_contents":"\/* Define the flash max size *\/\n__max_flash_size = 1024k;\n\n__data_ram_size = 8k;\n__stack_ram_size = 4k;\n__comm_ram_size = 83k;\n__heap_ram_size = 29k;\n\n__base = 0x10000000;\n\n__data_vma = 0x11000;\n__stack_vma = __data_vma + __data_ram_size;\n__comm_vma = __stack_vma + __stack_ram_size;\n__heap_vma = __comm_vma + __comm_ram_size;\n\n__ram1_vma = 0x50000;\n\nMEMORY\n{\n    init            : org = __base,             len = 512\n    flash(rx)       : org = __base + 512,       len = __max_flash_size\n    comm(rx)        : org = __comm_vma,         len = __comm_ram_size\n\n    data            : org = __data_vma,         len = __data_ram_size\n    stack           : org = __stack_vma,        len = __stack_ram_size\n    heap            : org = __heap_vma,         len = __heap_ram_size\n    ram1(rx)        : org = __ram1_vma,         len = 0x7a00\n}\n\nSECTIONS\n{\n    .init : {\n        *(.reset)\n    } > init\n\n    .ram1 __ram1_vma : {\n        *components*drivers**.o(.text* .rodata*)\n        *device.o(.text*)\n        . = ALIGN(32);\n    } > ram1 AT > flash\n\n    .rti : {\n        . = ALIGN(4);\n        \/* section information for initial *\/\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(32);\n    } > ram1 AT > flash\n\n    .comm : {\n        KEEP(*(.vector))\n        EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *romfs.o *lib_a**.o) *(.text*)\n        *finsh*shell.o (.text*)\n        EXCLUDE_FILE (*components*libc**.o *romfs.o *lib_a**.o) *(.rodata*)\n        *(.srodata*)\n        *(.rela*)\n        *(.data*)\n\t    *(.sdata*)\n        . = ALIGN(512);\n    } > comm AT > flash\n\n    .bss (NOLOAD):\n    {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.sbss)\n        *(.buf*)\n        __bss_end = .;\n    } > data\n    __bss_size = __bss_end - __bss_start;\n\n    .stack (NOLOAD) : {\n        __irq_stack_start = .;\n        . = __stack_ram_size;\n        __irq_stack = .;\n    } > stack\n    __irq_stack_size = __irq_stack - __irq_stack_start;\n\n    .heap (NOLOAD) : {\n        __heap_start = .;\n        . = __heap_ram_size;\n        __heap_end = .;\n    } > heap\n\n    .flash : {\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(512);\n    } > flash\n}\n\n\/* Calc the lma *\/\n__bank_size = SIZEOF(.flash);\n__comm_lma = LOADADDR(.comm);\n__comm_size = SIZEOF(.comm);\n__ram1_lma = LOADADDR(.ram1);\n__ram1_size = SIZEOF(.ram1) + SIZEOF(.rti);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a3c4469b1fad03cf7140d03045b0bfb301a72189","subject":"Add a linker script comment for all the patched newlib _lock_xxx symbols","message":"Add a linker script comment for all the patched newlib _lock_xxx symbols\n","repos":"alainmaes\/esp-open-rtos,UncleRus\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,SuperHouse\/esp-open-rtos,gpascualg\/esp-open-rtos,sheinz\/esp-open-rtos,urx\/esp-open-rtos,ourairquality\/esp-open-rtos,urx\/esp-open-rtos,ourairquality\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,kanflo\/esp-open-rtos,Angus71\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,hawkhsieh\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,UncleRus\/esp-open-rtos,UncleRus\/esp-open-rtos,foogod\/esp-open-rtos,sheinz\/esp-open-rtos,mr-nice\/esp-open-rtos,andree182\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,Zaltora\/esp-open-rtos,SuperHouse\/esp-open-rtos,andree182\/esp-open-rtos,kanflo\/esp-open-rtos,alainmaes\/esp-open-rtos,kamejoko80\/esp-open-rtos,mr-nice\/esp-open-rtos,mr-nice\/esp-open-rtos,someburner\/esp-rtos-tests,urx\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,DCoJA\/esp-open-rtos,kamejoko80\/esp-open-rtos,ourairquality\/esp-open-rtos,UncleRus\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,sheinz\/esp-open-rtos,kanflo\/esp-open-rtos,DCoJA\/esp-open-rtos,Angus71\/esp-open-rtos,Zaltora\/esp-open-rtos,alainmaes\/esp-open-rtos,Zaltora\/esp-open-rtos,DCoJA\/esp-open-rtos,ourairquality\/esp-open-rtos,Zaltora\/esp-open-rtos,Zaltora\/esp-open-rtos,hawkhsieh\/esp-open-rtos,UncleRus\/esp-open-rtos,someburner\/esp-rtos-tests,foogod\/esp-open-rtos,hawkhsieh\/esp-open-rtos,hawkhsieh\/esp-open-rtos,sheinz\/esp-open-rtos,ourairquality\/esp-open-rtos,gpascualg\/esp-open-rtos,urx\/esp-open-rtos,chaisme\/esp8266_FreeRTOS,SuperHouse\/esp-open-rtos,kanflo\/esp-open-rtos,SuperHouse\/esp-open-rtos,ourairquality\/esp-open-rtos,kanflo\/esp-open-rtos,SuperHouse\/esp-open-rtos,gpascualg\/esp-open-rtos,jaeh\/esp-open-rtos,urx\/esp-open-rtos,jaeh\/esp-open-rtos,SuperHouse\/esp-open-rtos,yesco\/esp-open-rtos,foogod\/esp-open-rtos,Zaltora\/esp-open-rtos,DCoJA\/esp-open-rtos,andree182\/esp-open-rtos,yesco\/esp-open-rtos,urx\/esp-open-rtos,mr-nice\/esp-open-rtos,kanflo\/esp-open-rtos,someburner\/esp-rtos-tests,someburner\/esp-rtos-tests,UncleRus\/esp-open-rtos,andree182\/esp-open-rtos,alainmaes\/esp-open-rtos","old_file":"ld\/eagle.app.v6.ld","new_file":"ld\/eagle.app.v6.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP .\n\n   Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one.\n*\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n\/* FreeRTOS lock functions.\n\n   Rely on a patch to libc that produces weak linked versions of the\n   below symbols. Currently treating locking primitives like universal\n   global critical section rather than individual locks, but this seems\n   OK from the use cases in newlib.\n*\/\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x8000\n  irom0_0_seg :                       \torg = 0x40240000, len = 0x7C000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(sdk__DebugExceptionVector)\nEXTERN(sdk__DoubleExceptionVector)\nEXTERN(sdk__KernelExceptionVector)\nEXTERN(sdk__NMIExceptionVector)\nEXTERN(sdk__UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg 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ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n  \t_UserExceptionVector_literal_start = ABSOLUTE(.);\n  \t*(.UserExceptionVector.literal)\n  \t_UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .iram1.text iram1.literal .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n}\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP .\n\n   Modified for esp open RTOS, this linker script is no longer the same as the esp_iot_rtos_sdk one.\n*\/\n\n\/* FreeRTOS memory management functions\n\n   We link these directly to newlib functions (have to do it at link\n   time as binary libraries use these symbols too.)\n*\/\npvPortMalloc = malloc;\nvPortFree = free;\n\n_lock_acquire = vPortEnterCritical;\n_lock_acquire_recursive = vPortEnterCritical;\n_lock_try_acquire = vPortEnterCritical;\n_lock_try_acquire_recursive = vPortEnterCritical;\n_lock_release = vPortExitCritical;\n_lock_release_recursive = vPortExitCritical;\n\n\/* SDK compatibility *\/\nets_printf = printf;\n\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x8000\n  irom0_0_seg :                       \torg = 0x40240000, len = 0x7C000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(sdk__DebugExceptionVector)\nEXTERN(sdk__DoubleExceptionVector)\nEXTERN(sdk__KernelExceptionVector)\nEXTERN(sdk__NMIExceptionVector)\nEXTERN(sdk__UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)\n  {\n  \t_UserExceptionVector_literal_start = ABSOLUTE(.);\n  \t*(.UserExceptionVector.literal)\n  \t_UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .iram1.text iram1.literal .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"04bdf1c507ba648a75b78d48271fed0dca3235b4","subject":"Adds bootloader section and the necessary symbols for the bootloader to compile.","message":"Adds bootloader section and the necessary symbols for the bootloader to compile.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/ti-ek-tm4c123gxl-launchpad\/memory_map.ld","new_file":"boards\/ti-ek-tm4c123gxl-launchpad\/memory_map.ld","new_contents":"MEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 248K\n  BOOTLOADER (rx) : ORIGIN = 0x0003E000, LENGTH = 8K\n  RAM  (rwx) : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\n__flash_start = ORIGIN(FLASH);\n__flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n__bootloader_start = ORIGIN(BOOTLOADER);\n__app_header_offset = 0x270;\n__bootloader_magic_ptr = ORIGIN(RAM);\n","old_contents":"MEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\n  RAM  (rwx) : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"14e2bae5f3dff05661c41f6a9f62ea5be9ea3624","subject":"Sections updated","message":"Sections updated\n","repos":"ckdur\/mriscv_vivado_arty,ckdur\/mriscv_vivado_arty,onchipuis\/mriscv_vivado,onchipuis\/mriscv_vivado,onchipuis\/mriscv_vivado,onchipuis\/mriscv_vivado,ckdur\/mriscv_vivado_arty,onchipuis\/mriscv_vivado,ckdur\/mriscv_vivado_arty","old_file":"tests\/mriscv_fpga.ld","new_file":"tests\/mriscv_fpga.ld","new_contents":"\/*\n  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.\n\n  This library is free software; you can redistribute it and\/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*\/\n\n\/* Linker script to configure memory regions.\n * Need modifying for a specific board.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00002000 \/*Put here if necesary bootloader start addressing*\/\n  RAM (rwx) : ORIGIN = 0x00010000, LENGTH = 0x00001000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t\/** TODO: maybe this is necesary if there is a section called by this.*\/\n\t\/*.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;*\/\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/*\n  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.\n\n  This library is free software; you can redistribute it and\/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*\/\n\n\/* Linker script to configure memory regions.\n * Need modifying for a specific board.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00002000 \/*Put here if necesary bootloader start addressing*\/\n  RAM (rwx) : ORIGIN = 0x00010000, LENGTH = 0x00001000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t\/** TODO: maybe this is necesary if there is a section called by this.*\/\n\t\/*.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;*\/\n\n\t\/* To copy multiple ROM to RAM sections,\n\t * uncomment .copy.table section and,\n\t * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.copy.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__copy_table_start__ = .;\n\t\tLONG (__etext)\n\t\tLONG (__data_start__)\n\t\tLONG (__data_end__ - __data_start__)\n\t\tLONG (__etext2)\n\t\tLONG (__data2_start__)\n\t\tLONG (__data2_end__ - __data2_start__)\n\t\t__copy_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t\/* To clear multiple BSS sections,\n\t * uncomment .zero.table section and,\n\t * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\n\t\/*\n\t.zero.table :\n\t{\n\t\t. = ALIGN(4);\n\t\t__zero_table_start__ = .;\n\t\tLONG (__bss_start__)\n\t\tLONG (__bss_end__ - __bss_start__)\n\t\tLONG (__bss2_start__)\n\t\tLONG (__bss2_end__ - __bss2_start__)\n\t\t__zero_table_end__ = .;\n\t} > FLASH\n\t*\/\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tPROVIDE(end = .);\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;\n\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8819742fe7d54e8018876e9a1bc392ce9ed38876","subject":"Fix f4-discovery\/blinky\/script.ld","message":"Fix f4-discovery\/blinky\/script.ld\n","repos":"ziutek\/emgo,ziutek\/emgo,ziutek\/emgo,ziutek\/emgo","old_file":"egpath\/src\/stm32\/examples\/f4-discovery\/blinky\/script.ld","new_file":"egpath\/src\/stm32\/examples\/f4-discovery\/blinky\/script.ld","new_contents":"\/* Stack size: 7\/8 KB *\/\nStackExp = 10;\nStackFrac = 7;\n\n\/* One stack, without gorutines *\/\nMaxTasks = 0;\nVTExp = 0;\n\nINCLUDE stm32\/f407_g\nINCLUDE stm32\/loadram\nINCLUDE noos-cortexm\n\n","old_contents":"INCLUDE stm32\/f407_g\nINCLUDE stm32\/loadram\nINCLUDE arch\/cortexm\nINCLUDE os\/noos\n\nstackExp = 10; \/* 1 KB *\/\nstackNum = 7;  \/* 7\/8 *\/\nStackSize = (stackExp - 1) << 8 | (stackNum - 1) << 5;\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"7d6116ec175d582c4a11d4de53d082c852c50cb3","subject":"Update LPC11U68.ld","message":"Update LPC11U68.ld","repos":"hwfwgrp\/mbed,tung7970\/mbed-os,Tiryoh\/mbed,arostm\/mbed-os,jpbrucker\/mbed,mbedmicro\/mbed,ban4jp\/mbed,maximmbed\/mbed,svogl\/mbed-os,Shengliang\/mbed,bulislaw\/mbed-os,YarivCol\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,mazimkhan\/mbed-os,svogl\/mbed-os,mmorenobarm\/mbed-os,devanlai\/mbed,nabilbendafi\/mbed,catiedev\/mbed-os,HeadsUpDisplayInc\/mbed,xcrespo\/mbed,dbestm\/mbed,pedromes\/mbed,andreaslarssonublox\/mbed,sg-\/mbed-drivers,NordicSemiconductor\/mbed,wodji\/mbed,svastm\/mbed,dbestm\/mbed,fpiot\/mbed-ats,FranklyDev\/mbed,nRFMesh\/mbed-os,adamgreen\/mbed,autopulated\/mbed,EmuxEvans\/mbed,adamgreen\/mbed,adustm\/mbed,HeadsUpDisplayInc\/mbed,DanKupiniak\/mbed,logost\/mbed,fvincenzo\/mbed-os,bikeNomad\/mbed,bikeNomad\/mbed,larks\/mbed,bentwire\/mbed,NXPmicro\/mbed,svastm\/mbed,bikeNomad\/mbed,devanlai\/mbed,jpbrucker\/mbed,pbrook\/mbed,fanghuaqi\/mbed,struempelix\/mbed,CalSol\/mbed,Tiryoh\/mbed,mikaleppanen\/mbed-os,Shengliang\/mbed,al177\/mbed,jamesadevine\/mbed,CalSol\/mbed,netzimme\/mbed-os,bentwire\/mbed,kpurusho\/mbed,DanKupiniak\/mbed,kpurusho\/mbed,jeremybrodt\/mbed,kl-cruz\/mbed-os,sg-\/mbed-drivers,al177\/mbed,kl-cruz\/mbed-os,jrjang\/mbed,geky\/mbed,arostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,svogl\/mbed-os,jpbrucker\/mbed,CalSol\/mbed,infinnovation\/mbed-os,maximmbed\/mbed,bremoran\/mbed-drivers,tung7970\/mbed-os,bcostm\/mbed-os,rosterloh\/mbed,xcrespo\/mbed,nRFMesh\/mbed-os,cvtsi2sd\/mbed-os,sam-geek\/mbed,mbedmicro\/mbed,andreaslarssonublox\/mbed,c1728p9\/mbed-os,EmuxEvans\/mbed,geky\/mbed,bcostm\/mbed-os,NitinBhaskar\/mbed,jeremybrodt\/mbed,devanlai\/mbed,adustm\/mbed,rgrover\/mbed,andreaslarssonublox\/mbed,K4zuki\/mbed,nvlsianpu\/mbed,nvlsianpu\/mbed,fanghuaqi\/mbed,bentwire\/mbed,kjbracey-arm\/mbed,EmuxEvans\/mbed,pbrook\/mbed,Timmmm\/mbed,larks\/mbed,mazimkhan\/mbed-os,al177\/mbed,nvlsianpu\/mbed,ban4jp\/mbed,andcor02\/mbed-os,K4zuki\/mbed,mmorenobarm\/mbed-os,rgrover\/mbed,andreaslarssonublox\/mbed,alertby\/mbed,0xc0170\/mbed-drivers,mikaleppanen\/mbed-os,fahhem\/mbed-os,YarivCol\/mbed-os,RonEld\/mbed,pbrook\/mbed,pradeep-gr\/mbed-os5-onsemi,bulislaw\/mbed-os,masaohamanaka\/mbed,theotherjimmy\/mbed,karsev\/mbed-os,mmorenobarm\/mbed-os,monkiineko\/mbed-os,infinnovation\/mbed-os,xcrespo\/mbed,NitinBhaskar\/mbed,kjbracey-arm\/mbed,adustm\/mbed,jferreir\/mbed,netzimme\/mbed-os,getopenmono\/mbed,andcor02\/mbed-os,HeadsUpDisplayInc\/mbed,hwfwgrp\/mbed,jferreir\/mbed,Willem23\/mbed,betzw\/mbed-os,alertby\/mbed,screamerbg\/mbed,ARM-software\/mbed-beetle,ARM-software\/mbed-beetle,mazimkhan\/mbed-os,mnlipp\/mbed,Tiryoh\/mbed,GustavWi\/mbed,nvlsianpu\/mbed,pbrook\/mbed,NordicSemiconductor\/mbed,autopulated\/mbed,dbestm\/mbed,tung7970\/mbed-os,JasonHow44\/mbed,Sweet-Peas\/mbed,bulislaw\/mbed-os,bulislaw\/mbed-os,monkiineko\/mbed-os,masaohamanaka\/mbed,nRFMesh\/mbed-os,xcrespo\/mbed,naves-thiago\/mbed-midi,logost\/mbed,theotherjimmy\/mbed,masaohamanaka\/mbed,svogl\/mbed-os,ban4jp\/mbed,autopulated\/mbed,adamgreen\/mbed,EmuxEvans\/mbed,adamgreen\/mbed,wodji\/mbed,brstew\/MBED-BUILD,FranklyDev\/mbed,naves-thiago\/mbed-midi,kpurusho\/mbed,kjbracey-arm\/mbed,Shengliang\/mbed,svastm\/mbed,jeremybrodt\/mbed,K4zuki\/mbed,karsev\/mbed-os,Tiryoh\/mbed,wodji\/mbed,larks\/mbed,pradeep-gr\/mbed-os5-onsemi,brstew\/MBED-BUILD,karsev\/mbed-os,pedromes\/mbed,Marcomissyou\/mbed,JasonHow44\/mbed,mnlipp\/mbed,hwfwgrp\/mbed,pedromes\/mbed,CalSol\/mbed,svastm\/mbed,bulislaw\/mbed-os,mmorenobarm\/mbed-os,tung7970\/mbed-os-1,fahhem\/mbed-os,andreaslarssonublox\/mbed,Archcady\/mbed-os,HeadsUpDisplayInc\/mbed,infinnovation\/mbed-os,jrjang\/mbed,catiedev\/mbed-os,andcor02\/mbed-os,fvincenzo\/mbed-os,cvtsi2sd\/mbed-os,getopenmono\/mbed,NitinBhaskar\/mbed,Archcady\/mbed-os,rosterloh\/mbed,larks\/mbed,jpbrucker\/mbed,screamerbg\/mbed,sam-geek\/mbed,c1728p9\/mbed-os,autopulated\/mbed,tung7970\/mbed-os-1,hwfwgrp\/mbed,monkiineko\/mbed-os,brstew\/MBED-BUILD,ban4jp\/mbed,NitinBhaskar\/mbed,tung7970\/mbed-os-1,RonEld\/mbed,svogl\/mbed-os,xcrespo\/mbed,geky\/mbed,mmorenobarm\/mbed-os,ryankurte\/mbed-os,jpbrucker\/mbed,adamgreen\/mbed,pi19404\/mbed,mazimkhan\/mbed-os,dbestm\/mbed,infinnovation\/mbed-os,fvincenzo\/mbed-os,YarivCol\/mbed-os,kpurusho\/mbed,kl-cruz\/mbed-os,andcor02\/mbed-os,adamgreen\/mbed,alertby\/mbed,andcor02\/mbed-os,bcostm\/mbed-os,bulislaw\/mbed-os,fvincenzo\/mbed-os,fpiot\/mbed-ats,fpiot\/mbed-ats,c1728p9\/mbed-os,tung7970\/mbed-os-1,YarivCol\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,ARM-software\/mbed-beetle,ryankurte\/mbed-os,jferreir\/mbed,betzw\/mbed-os,jpbrucker\/mbed,alertby\/mbed,pedromes\/mbed,nvlsianpu\/mbed,RonEld\/mbed,jeremybrodt\/mbed,betzw\/mbed-os,nRFMesh\/mbed-os,Timmmm\/mbed,FranklyDev\/mbed,jamesadevine\/mbed,GustavWi\/mbed,mnlipp\/mbed,mikaleppanen\/mbed-os,svogl\/mbed-os,j-greffe\/mbed-os,fpiot\/mbed-ats,arostm\/mbed-os,GustavWi\/mbed,pi19404\/mbed,arostm\/mbed-os,struempelix\/mbed,jrjang\/mbed,JasonHow44\/mbed,Sweet-Peas\/mbed,jferreir\/mbed,arostm\/mbed-os,jferreir\/mbed,bikeNomad\/mbed,nabilbendafi\/mbed,alertby\/mbed,Shengliang\/mbed,devanlai\/mbed,fpiot\/mbed-ats,Sweet-Peas\/mbed,K4zuki\/mbed,naves-thiago\/mbed-midi,pedromes\/mbed,rosterloh\/mbed,bentwire\/mbed,jeremybrodt\/mbed,brstew\/MBED-BUILD,EmuxEvans\/mbed,EmuxEvans\/mbed,Willem23\/mbed,Archcady\/mbed-os,fanghuaqi\/mbed,NordicSemiconductor\/mbed,fpiot\/mbed-ats,mbedmicro\/mbed,mikaleppanen\/mbed-os,JasonHow44\/mbed,Sweet-Peas\/mbed,jferreir\/mbed,autopulated\/mbed,RonEld\/mbed,ryankurte\/mbed-os,catiedev\/mbed-os,tung7970\/mbed-os,devanlai\/mbed,betzw\/mbed-os,maximmbed\/mbed,netzimme\/mbed-os,JasonHow44\/mbed,logost\/mbed,Tiryoh\/mbed,Marcomissyou\/mbed,Timmmm\/mbed,Marcomissyou\/mbed,dbestm\/mbed,jrjang\/mbed,mmorenobarm\/mbed-os,logost\/mbed,nabilbendafi\/mbed,Shengliang\/mbed,screamerbg\/mbed,betzw\/mbed-os,GustavWi\/mbed,NXPmicro\/mbed,getopenmono\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,HeadsUpDisplayInc\/mbed,ARM-software\/mbed-beetle,bikeNomad\/mbed,rosterloh\/mbed,pi19404\/mbed,kpurusho\/mbed,JasonHow44\/mbed,struempelix\/mbed,Archcady\/mbed-os,infinnovation\/mbed-os,tung7970\/mbed-os,dbestm\/mbed,fanghuaqi\/mbed,j-greffe\/mbed-os,nabilbendafi\/mbed,NXPmicro\/mbed,wodji\/mbed,struempelix\/mbed,theotherjimmy\/mbed,pradeep-gr\/mbed-os5-onsemi,Archcady\/mbed-os,pbrook\/mbed,geky\/mbed,fahhem\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,kl-cruz\/mbed-os,j-greffe\/mbed-os,pradeep-gr\/mbed-os5-onsemi,RonEld\/mbed,maximmbed\/mbed,netzimme\/mbed-os,autopulated\/mbed,jamesadevine\/mbed,masaohamanaka\/mbed,Willem23\/mbed,K4zuki\/mbed,al177\/mbed,NordicSemiconductor\/mbed,catiedev\/mbed-os,tung7970\/mbed-os-1,monkiineko\/mbed-os,pbrook\/mbed,HeadsUpDisplayInc\/mbed,Marcomissyou\/mbed,maximmbed\/mbed,al177\/mbed,karsev\/mbed-os,rgrover\/mbed,maximmbed\/mbed,xcrespo\/mbed,hwfwgrp\/mbed,bremoran\/mbed-drivers,karsev\/mbed-os,masaohamanaka\/mbed,CalSol\/mbed,c1728p9\/mbed-os,mnlipp\/mbed,mbedmicro\/mbed,theotherjimmy\/mbed,alertby\/mbed,getopenmono\/mbed,Timmmm\/mbed,nabilbendafi\/mbed,bentwire\/mbed,pi19404\/mbed,naves-thiago\/mbed-midi,sam-geek\/mbed,0xc0170\/mbed-drivers,netzimme\/mbed-os,Willem23\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,brstew\/MBED-BUILD,screamerbg\/mbed,kl-cruz\/mbed-os,ryankurte\/mbed-os,mikaleppanen\/mbed-os,cvtsi2sd\/mbed-os,svastm\/mbed,rosterloh\/mbed,DanKupiniak\/mbed,getopenmono\/mbed,jamesadevine\/mbed,nvlsianpu\/mbed,rgrover\/mbed,K4zuki\/mbed,ryankurte\/mbed-os,larks\/mbed,Timmmm\/mbed,cvtsi2sd\/mbed-os,Tiryoh\/mbed,monkiineko\/mbed-os,jrjang\/mbed,brstew\/MBED-BUILD,ban4jp\/mbed,devanlai\/mbed,pradeep-gr\/mbed-os5-onsemi,mikaleppanen\/mbed-os,mnlipp\/mbed,iriark01\/mbed-drivers,naves-thiago\/mbed-midi,cvtsi2sd\/mbed-os,NXPmicro\/mbed,pi19404\/mbed,screamerbg\/mbed,pi19404\/mbed,bentwire\/mbed,kjbracey-arm\/mbed,c1728p9\/mbed-os,bcostm\/mbed-os,struempelix\/mbed,hwfwgrp\/mbed,Marcomissyou\/mbed,NitinBhaskar\/mbed,fahhem\/mbed-os,CalSol\/mbed,adustm\/mbed,wodji\/mbed,larks\/mbed,nabilbendafi\/mbed,adustm\/mbed,Marcomissyou\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,kl-cruz\/mbed-os,fahhem\/mbed-os,fanghuaqi\/mbed,NXPmicro\/mbed,ban4jp\/mbed,j-greffe\/mbed-os,Shengliang\/mbed,logost\/mbed,masaohamanaka\/mbed,betzw\/mbed-os,fvincenzo\/mbed-os,Sweet-Peas\/mbed,infinnovation\/mbed-os,al177\/mbed,YarivCol\/mbed-os,YarivCol\/mbed-os,DanKupiniak\/mbed,NXPmicro\/mbed,mazimkhan\/mbed-os,sam-geek\/mbed,adustm\/mbed,screamerbg\/mbed,bcostm\/mbed-os,wodji\/mbed,Willem23\/mbed,mnlipp\/mbed,mazimkhan\/mbed-os,naves-thiago\/mbed-midi,theotherjimmy\/mbed,nRFMesh\/mbed-os,c1728p9\/mbed-os,RonEld\/mbed,kpurusho\/mbed,arostm\/mbed-os,getopenmono\/mbed,j-greffe\/mbed-os,mbedmicro\/mbed,FranklyDev\/mbed,ryankurte\/mbed-os,geky\/mbed,iriark01\/mbed-drivers,Archcady\/mbed-os,Timmmm\/mbed,nRFMesh\/mbed-os,FranklyDev\/mbed,karsev\/mbed-os,fahhem\/mbed-os,struempelix\/mbed,catiedev\/mbed-os,j-greffe\/mbed-os,bcostm\/mbed-os,logost\/mbed,jrjang\/mbed,GustavWi\/mbed,monkiineko\/mbed-os,pedromes\/mbed,sam-geek\/mbed,netzimme\/mbed-os,andcor02\/mbed-os,theotherjimmy\/mbed,catiedev\/mbed-os,cvtsi2sd\/mbed-os,rgrover\/mbed,Sweet-Peas\/mbed,jamesadevine\/mbed,rosterloh\/mbed,jamesadevine\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC11U6X\/TOOLCHAIN_GCC_CR\/TARGET_LPC11U68\/LPC11U68.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC11U6X\/TOOLCHAIN_GCC_CR\/TARGET_LPC11U68\/LPC11U68.ld","new_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC11U68\n * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Sat Jun 14 15:26:54 JST 2014\n *\/\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\/*GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)*\/\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 \/* 32K bytes *\/\n  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 \/* 2K bytes *\/\n  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_32 = 0x10000000+0x100 + 0x8000-0x100;\n  __top_Ram1_2 = 0x20000000 + 0x800;\n  __top_Ram2USB_2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n\t\t*(.text.ResetISR)\n        *(.text.SystemInit)\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \/* possible MTB section for Ram1_2 *\/\n    .mtb_buffer_RAM2 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM2*))\n        KEEP(*(.mtb.$RAM1_2*))\n    } > Ram1_2 \n    \n    \/* DATA section for Ram1_2 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_2)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 AT>MFlash256\n    \/* possible MTB section for Ram2USB_2 *\/\n    .mtb_buffer_RAM3 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM3*))\n        KEEP(*(.mtb.$RAM2USB_2*))\n    } > Ram2USB_2 \n    \n    \/* DATA section for Ram2USB_2 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2USB_2)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/\n    \n    \/* Default MTB section *\/\n    .mtb_buffer_default (NOLOAD) :\n    {\n       KEEP(*(.mtb*))\n    } > Ram0_32 \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_32\n\n\t\n\t\/* Main DATA section (Ram0_32) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_32 AT>MFlash256\n\n    \/* BSS section for Ram1_2 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2\n    \/* BSS section for Ram2USB_2 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_32\n        \n    \/* NOINIT section for Ram1_2 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 \n    \/* NOINIT section for Ram2USB_2 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_32 - 0);\n}\n","old_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC11U68\n * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Sat Jun 14 15:26:54 JST 2014\n *\/\n\nGROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 \/* 32K bytes *\/\n  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 \/* 2K bytes *\/\n  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_32 = 0x10000000 + 0x8000;\n  __top_Ram1_2 = 0x20000000 + 0x800;\n  __top_Ram2USB_2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        __vectors_start__ = ABSOLUTE(.) ;\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \/* possible MTB section for Ram1_2 *\/\n    .mtb_buffer_RAM2 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM2*))\n        KEEP(*(.mtb.$RAM1_2*))\n    } > Ram1_2 \n    \n    \/* DATA section for Ram1_2 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_2)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 AT>MFlash256\n    \/* possible MTB section for Ram2USB_2 *\/\n    .mtb_buffer_RAM3 (NOLOAD) :\n    {\n        KEEP(*(.mtb.$RAM3*))\n        KEEP(*(.mtb.$RAM2USB_2*))\n    } > Ram2USB_2 \n    \n    \/* DATA section for Ram2USB_2 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2USB_2)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/\n    \n    \/* Default MTB section *\/\n    .mtb_buffer_default (NOLOAD) :\n    {\n       KEEP(*(.mtb*))\n    } > Ram0_32 \n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_32\n\n\t\n\t\/* Main DATA section (Ram0_32) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_32 AT>MFlash256\n\n    \/* BSS section for Ram1_2 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2\n    \/* BSS section for Ram2USB_2 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_32\n        \n    \/* NOINIT section for Ram1_2 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_2*)\n       . = ALIGN(4) ;\n    } > Ram1_2 \n    \/* NOINIT section for Ram2USB_2 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2USB_2*)\n       . = ALIGN(4) ;\n    } > Ram2USB_2 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_32 - 0);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3b53d27f4ba53383abeb07ad4716e3075cef555e","subject":"Update: Change stack size","message":"Update: Change stack size\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX72T\/R5F572TK.ld","new_file":"RX72T\/R5F572TK.ld","new_contents":"\/*!\t@file\n\t@brief\tRX72T R5F572TK \u30ea\u30f3\u30ab\u30fc\u30fb\u30b9\u30af\u30ea\u30d7\u30c8 @n\n\t\t\tCode: 1M, RAM: 128K, DataFlash: 32K\n    @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\t@copyright\tCopyright (C) 2020 Kunihito Hiramatsu @n\n\t\t\t\tReleased under the MIT license @n\n\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX72TK chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x0001F800 \/* 128K - stack_size (2048) *\/\n\tUSTACK (w) : ORIGIN = 0x0001FE00, LENGTH = 4 \/* ustack 1536 bytes *\/\n\tISTACK (w) : ORIGIN = 0x00020000, LENGTH = 4 \/* istack 512 bytes  *\/\n\tROM (w)    : ORIGIN = 0xFFF00000, LENGTH = 0x000FFFD0 \/* 1024K - hw_vectors(48) *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .istack (ORIGIN (ISTACK)) :\n  {\n    PROVIDE (__istack = .);\n    *(.istack)\n  }\n\n  .ustack (ORIGIN (USTACK)) :\n  {\n    PROVIDE (__ustack = .);\n    *(.ustack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*!\t@file\n\t@brief\tRX72T R5F572TK \u30ea\u30f3\u30ab\u30fc\u30fb\u30b9\u30af\u30ea\u30d7\u30c8 @n\n\t\t\tCode: 1M, RAM: 128K, DataFlash: 32K\n    @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\t@copyright\tCopyright (C) 2019 Kunihito Hiramatsu @n\n\t\t\t\tReleased under the MIT license @n\n\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX66TK chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x0001FC00 \/* 128K - stack_size (1024) *\/\n\tUSTACK (w) : ORIGIN = 0x0001FF80, LENGTH = 4 \/* ustack 896 bytes *\/\n\tISTACK (w) : ORIGIN = 0x00020000, LENGTH = 4 \/* istack 128 bytes  *\/\n\tROM (w)    : ORIGIN = 0xFFF00000, LENGTH = 0x000FFFD0 \/* 1024K - hw_vectors(48) *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .istack (ORIGIN (ISTACK)) :\n  {\n    PROVIDE (__istack = .);\n    *(.istack)\n  }\n\n  .ustack (ORIGIN (USTACK)) :\n  {\n    PROVIDE (__ustack = .);\n    *(.ustack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"f612ea0b471f63f8c4e56f93773dce84596bc4ad","subject":"replace hard-coded vector size with macro in linker scripts","message":"replace hard-coded vector size with macro in linker scripts\n","repos":"mbedmicro\/mbed,betzw\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,betzw\/mbed-os,betzw\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,betzw\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,c1728p9\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,andcor02\/mbed-os,betzw\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,betzw\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,kjbracey-arm\/mbed","old_file":"targets\/TARGET_ARM_FM\/TARGET_FVP_MPS2\/TARGET_FVP_MPS2_M0\/device\/TOOLCHAIN_GCC_ARM\/MPS2.ld","new_file":"targets\/TARGET_ARM_FM\/TARGET_FVP_MPS2\/TARGET_FVP_MPS2_M0\/device\/TOOLCHAIN_GCC_ARM\/MPS2.ld","new_contents":"\/*\n * MPS2 CMSIS Library\n *\/\n\/*\n * Copyright (c) 2009-2018 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\/*\n * This file is derivative of CMSIS V5.00 gcc_arm.ld\n *\/\n\/* Linker script for mbed FVP Cortex-M0 on MPS2 *\/\n\n\/* Linker script to configure memory regions. *\/\n\/* The length of the VECTORS region is a bit larger than\n * is necessary based on the number of exception handlers.\n *\/\n\n#include \"..\/memory_zones.h\"\n#include \"..\/cmsis_nvic.h\"\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE\n  FLASH (rx)            : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE\n  RAM (rwx)             : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSTACK_SIZE = 0x400;\n\n\/* Size of the vector table in SRAM *\/\nM_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    .interrupts_ram :\n    {\n        . = ALIGN(4);\n        __VECTOR_RAM__ = .;\n        __interrupts_ram_start__ = .;   \/* Create a global symbol at data start *\/\n        . += M_VECTOR_RAM_SIZE;\n        . = ALIGN(4);\n        __interrupts_ram_end__ = .;     \/* Define a global symbol at data end *\/\n    } > RAM\n\n    .data :\n    {\n        PROVIDE(__etext = LOADADDR(.data));\n        . = ALIGN(4);\n        __data_start__ = .;\n        *(vtable)\n        *(.data)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM AT > FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __START_BSS = .;\n        __bss_start__ = .;\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        __END_BSS = .;\n\n    } > RAM\n\n    bss_size = __bss_end__ - __bss_start__;\n\n    .heap (COPY):\n    {\n        . = ALIGN(8);\n        __end__ = .;\n        PROVIDE(end = .);\n        __HeapBase = .;\n        *(.heap*)\n        __HeapLimit = .;\n        __heap_limit = .; \/* Add for _sbrk *\/\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}   \/* End of sections *\/\n","old_contents":"\/*\n * MPS2 CMSIS Library\n *\/\n\/*\n * Copyright (c) 2009-2018 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\/*\n * This file is derivative of CMSIS V5.00 gcc_arm.ld\n *\/\n\/* Linker script for mbed FVP Cortex-M0 on MPS2 *\/\n\n\/* Linker script to configure memory regions. *\/\n\/* The length of the VECTORS region is a bit larger than\n * is necessary based on the number of exception handlers.\n *\/\n\n#include \"..\/memory_zones.h\"\n#include \"..\/cmsis_nvic.h\"\n\nMEMORY\n{\n  VECTORS (rx)          : ORIGIN = MAPPABLE_START, LENGTH = MAPPABLE_SIZE\n  FLASH (rx)            : ORIGIN = ZBT_SRAM1_START, LENGTH = ZBT_SRAM1_SIZE\n  RAM (rwx)             : ORIGIN = ZBT_SRAM2_START, LENGTH = ZBT_SRAM2_SIZE\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSTACK_SIZE = 0x400;\n\n\/* Size of the vector table in SRAM *\/\nM_VECTOR_RAM_SIZE = 0x100;\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n         . = ALIGN(4);\n    } > VECTORS\n\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    .interrupts_ram :\n    {\n        . = ALIGN(4);\n        __VECTOR_RAM__ = .;\n        __interrupts_ram_start__ = .;   \/* Create a global symbol at data start *\/\n        . += M_VECTOR_RAM_SIZE;\n        . = ALIGN(4);\n        __interrupts_ram_end__ = .;     \/* Define a global symbol at data end *\/\n    } > RAM\n\n    .data :\n    {\n        PROVIDE(__etext = LOADADDR(.data));\n        . = ALIGN(4);\n        __data_start__ = .;\n        *(vtable)\n        *(.data)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM AT > FLASH\n\n    .uninitialized (NOLOAD):\n    {\n        . = ALIGN(32);\n        __uninitialized_start = .;\n        *(.uninitialized)\n        KEEP(*(.keep.uninitialized))\n        . = ALIGN(32);\n        __uninitialized_end = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __START_BSS = .;\n        __bss_start__ = .;\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        __END_BSS = .;\n\n    } > RAM\n\n    bss_size = __bss_end__ - __bss_start__;\n\n    .heap (COPY):\n    {\n        . = ALIGN(8);\n        __end__ = .;\n        PROVIDE(end = .);\n        __HeapBase = .;\n        *(.heap*)\n        __HeapLimit = .;\n        __heap_limit = .; \/* Add for _sbrk *\/\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}   \/* End of sections *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"03630a81488ca30c384c09034caa1a70afb80a0d","subject":"Preserve hii section in GCC binaries","message":"Preserve hii section in GCC binaries\n\nAccording to UEFI spec:\nOnce an image is loaded, LoadImage() installs\nEFI_HII_PACKAGE_LIST_PROTOCOL on the handle if the image contains a\ncustom PE\/COFF resource with the type 'HII'. The protocol's\ninterface pointer points to the HII package list which is contained\nin the resource's data.\n\nThis is controlled by the UEFI_HII_RESOURCE_SECTION define in the INF\nfile.  When present the HII resource is linked with the module\nbinary.\n\nUnfortunately GCC-built binaries have been stripping the .hii section\nentirely.  See  \"[edk2] HII gEfiHiiPackageListProtocolGuid problem\nwith  GCC48(VS2012x86 works)\"\nhttp:\/\/thread.gmane.org\/gmane.comp.bios.tianocore.devel\/13438\nhttp:\/\/thread.gmane.org\/gmane.comp.bios.tianocore.devel\/14899\n\nThis patch tells the linker to preserve the .hii sections\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Thomas Palmer <60f4d02ff984b42bd1e65cdc2278843916e619c4@hpe.com>\nAcked-by: Laszlo Ersek <7437296077edea1cb64451c122c4dac071f0cfbc@redhat.com>\nTested-by: Bruce Cran <ce547a98b2631aa2d77a4879bbd4113e9564a44b@gmail.com>\nReviewed-by: Bruce Cran <ce547a98b2631aa2d77a4879bbd4113e9564a44b@gmail.com>\nReviewed-by: Yonghong Zhu <78d981fe33a016071af5222c56d5cf77f30fb0b2@intel.com>\nReviewed-by: Liming Gao <6480311aeeb4b006862f6d13ebabddc03f51e507@intel.com>\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"BaseTools\/Scripts\/GccBase.lds","new_file":"BaseTools\/Scripts\/GccBase.lds","new_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are constant from the POV of the program,\r\n     * but most of its contents end up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     *\/\r\n    *:AutoGen.obj(.data .data.* .bss .bss.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","old_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are constant from the POV of the program,\r\n     * but most of its contents end up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     *\/\r\n    *:AutoGen.obj(.data .data.* .bss .bss.*)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash)\r\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"808b4569270083504bb5eae5a9e8f7eb9aaa34ca","subject":"mimxrt10xx: Use FLASH_FIRMWARE instead of FLASH_TEXT in linker scripts","message":"mimxrt10xx: Use FLASH_FIRMWARE instead of FLASH_TEXT in linker scripts\n\nfor compatibility with the build_memory_info script\n\nThis change was scripted:\n    git grep -l FLASH_TEXT | xargs sed -i s\/FLASH_TEXT\/FLASH_FIRMWARE\/\n","repos":"adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython","old_file":"ports\/mimxrt10xx\/linking\/common.ld","new_file":"ports\/mimxrt10xx\/linking\/common.ld","new_contents":"\/* Template for iMX RT 10xx linking. This is the last of four linker scripts passed in.\n\nThe first three provide variables for this one.\n\nBoards can setup reserved flash with _ld_reserved_flash_size in board.ld. *\/\n\nENTRY(Reset_Handler)\n\ncode_size = 1M;\n_ld_default_stack_size = 20K;\n\n\/* Default reserved flash to nothing. *\/\n_ld_reserved_flash_size = DEFINED(_ld_reserved_flash_size) ? _ld_reserved_flash_size : 0K ;\n\nMEMORY\n{\n    \/* These next two sections are included in place of a bootloader. If a UF2 is used to load, it\n      will ignore these two sections because it lives there. *\/\n    \/* This is the first block and is read so that the bootrom knows the optimal way to interface with the flash chip. *\/\n    FLASH_CONFIG (rx)     : ORIGIN = flash_config_location, LENGTH = 512\n    \/* This can't move because the bootrom looks at this address. *\/\n    FLASH_IVT (rx)        : ORIGIN = 0x60001000, LENGTH = 4K\n    \/* Place the ISRs 48k in to leave room for the bootloader when it is available. *\/\n    FLASH_FIRMWARE (rx)        : ORIGIN = 0x6000C000, LENGTH = code_size - 48K\n    FLASH_FATFS (r)       : ORIGIN = 0x60100000, LENGTH = _ld_flash_size - code_size - _ld_reserved_flash_size\n    \/* Teensy uses the last bit of flash for recovery. *\/\n    RESERVED_FLASH        : ORIGIN = 0x60100000 + _ld_flash_size - _ld_reserved_flash_size, LENGTH = _ld_reserved_flash_size\n    OCRAM (rwx)           : ORIGIN = 0x20200000, LENGTH = ram_size - 64K\n    DTCM (x)              : ORIGIN = 0x20000000, LENGTH = 32K\n    ITCM (x)              : ORIGIN = 0x00000000, LENGTH = 32K\n}\n\n__data_start__ = 0;\n__data_end__ = 0;\n_start = 0;\n\nSECTIONS\n{\n    .flash_config :\n    {\n        . = ALIGN(4);\n        KEEP(* (.boot_hdr.conf))\n        . = ALIGN(4);\n    } > FLASH_CONFIG\n\n    .ivt :\n    {\n        . = ALIGN(4);\n        KEEP(* (.boot_hdr.ivt))\n        KEEP(* (.boot_hdr.boot_data))\n        KEEP(* (.boot_hdr.dcd_data))\n        . = ALIGN(4);\n    } > FLASH_IVT\n    image_vector_table = LOADADDR(.ivt);\n\n    .text :\n    {\n        . = ALIGN(4);\n        __VECTOR_TABLE = .;\n        __VECTOR_RAM = .;\n        _ld_isr_table = .;\n\n        KEEP(*(.isr_vector))         \/* Startup code *\/\n    *(EXCLUDE_FILE(\n        *flexspi_nor_flash_ops.o\n        *fsl_flexspi.o\n    ) .text*)                \/* .text* sections (code) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        . = ALIGN(4);\n    } > FLASH_FIRMWARE\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        _etext = .;        \/* define a global symbol at end of code *\/\n        __etext = .;       \/* define a global symbol at end of code *\/\n    } > FLASH_FIRMWARE\n\n    _ld_filesystem_start = ORIGIN(FLASH_FATFS);\n    _ld_filesystem_end = _ld_filesystem_start + LENGTH(FLASH_FATFS);\n\n    .data :\n    {\n        . = ALIGN(4);\n        *(.data*)               \/* .data* sections *\/\n        *flexspi_nor_flash_ops.o(.text*)\n        *fsl_flexspi.o(.text*)\n        . = ALIGN(4);\n    } > OCRAM AT> FLASH_FIRMWARE\n    _ld_ocram_data_destination = ADDR(.data);\n    _ld_ocram_data_flash_copy = LOADADDR(.data);\n    _ld_ocram_data_size = SIZEOF(.data);\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n    } > OCRAM\n    _ld_ocram_bss_start = ADDR(.bss);\n    _ld_ocram_bss_size = SIZEOF(.bss);\n    _ld_heap_start = _ld_ocram_bss_start + _ld_ocram_bss_size;\n    _ld_heap_end = ORIGIN(OCRAM) + LENGTH(OCRAM);\n\n    .itcm :\n    {\n        . = ALIGN(4);\n\n        *(.itcm.*)\n\n        . = ALIGN(4);\n    } > ITCM AT> FLASH_FIRMWARE\n    _ld_itcm_destination = ADDR(.itcm);\n    _ld_itcm_flash_copy = LOADADDR(.itcm);\n    _ld_itcm_size = SIZEOF(.itcm);\n\n    .dtcm_data :\n    {\n        . = ALIGN(4);\n\n        *(.dtcm_data.*)\n\n        . = ALIGN(4);\n    } > DTCM AT> FLASH_FIRMWARE\n    _ld_dtcm_data_destination = ADDR(.dtcm_data);\n    _ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data);\n    _ld_dtcm_data_size = SIZEOF(.dtcm_data);\n\n    .dtcm_bss :\n    {\n        . = ALIGN(4);\n\n        *(.dtcm_bss.*)\n\n        . = ALIGN(4);\n    } > DTCM AT> DTCM\n    _ld_dtcm_bss_start = ADDR(.dtcm_bss);\n    _ld_dtcm_bss_size = SIZEOF(.dtcm_bss);\n\n    .stack :\n    {\n        . = ALIGN(8);\n        _ld_stack_bottom = .;\n        . += _ld_default_stack_size;\n    } > DTCM\n    _ld_stack_top = ORIGIN(DTCM) + LENGTH(DTCM);\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/* Template for iMX RT 10xx linking. This is the last of four linker scripts passed in.\n\nThe first three provide variables for this one.\n\nBoards can setup reserved flash with _ld_reserved_flash_size in board.ld. *\/\n\nENTRY(Reset_Handler)\n\ncode_size = 1M;\n_ld_default_stack_size = 20K;\n\n\/* Default reserved flash to nothing. *\/\n_ld_reserved_flash_size = DEFINED(_ld_reserved_flash_size) ? _ld_reserved_flash_size : 0K ;\n\nMEMORY\n{\n    \/* These next two sections are included in place of a bootloader. If a UF2 is used to load, it\n      will ignore these two sections because it lives there. *\/\n    \/* This is the first block and is read so that the bootrom knows the optimal way to interface with the flash chip. *\/\n    FLASH_CONFIG (rx)     : ORIGIN = flash_config_location, LENGTH = 512\n    \/* This can't move because the bootrom looks at this address. *\/\n    FLASH_IVT (rx)        : ORIGIN = 0x60001000, LENGTH = 4K\n    \/* Place the ISRs 48k in to leave room for the bootloader when it is available. *\/\n    FLASH_TEXT (rx)        : ORIGIN = 0x6000C000, LENGTH = code_size - 48K\n    FLASH_FATFS (r)       : ORIGIN = 0x60100000, LENGTH = _ld_flash_size - code_size - _ld_reserved_flash_size\n    \/* Teensy uses the last bit of flash for recovery. *\/\n    RESERVED_FLASH        : ORIGIN = 0x60100000 + _ld_flash_size - _ld_reserved_flash_size, LENGTH = _ld_reserved_flash_size\n    OCRAM (rwx)           : ORIGIN = 0x20200000, LENGTH = ram_size - 64K\n    DTCM (x)              : ORIGIN = 0x20000000, LENGTH = 32K\n    ITCM (x)              : ORIGIN = 0x00000000, LENGTH = 32K\n}\n\n__data_start__ = 0;\n__data_end__ = 0;\n_start = 0;\n\nSECTIONS\n{\n    .flash_config :\n    {\n        . = ALIGN(4);\n        KEEP(* (.boot_hdr.conf))\n        . = ALIGN(4);\n    } > FLASH_CONFIG\n\n    .ivt :\n    {\n        . = ALIGN(4);\n        KEEP(* (.boot_hdr.ivt))\n        KEEP(* (.boot_hdr.boot_data))\n        KEEP(* (.boot_hdr.dcd_data))\n        . = ALIGN(4);\n    } > FLASH_IVT\n    image_vector_table = LOADADDR(.ivt);\n\n    .text :\n    {\n        . = ALIGN(4);\n        __VECTOR_TABLE = .;\n        __VECTOR_RAM = .;\n        _ld_isr_table = .;\n\n        KEEP(*(.isr_vector))         \/* Startup code *\/\n    *(EXCLUDE_FILE(\n        *flexspi_nor_flash_ops.o\n        *fsl_flexspi.o\n    ) .text*)                \/* .text* sections (code) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        . = ALIGN(4);\n    } > FLASH_TEXT\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        _etext = .;        \/* define a global symbol at end of code *\/\n        __etext = .;       \/* define a global symbol at end of code *\/\n    } > FLASH_TEXT\n\n    _ld_filesystem_start = ORIGIN(FLASH_FATFS);\n    _ld_filesystem_end = _ld_filesystem_start + LENGTH(FLASH_FATFS);\n\n    .data :\n    {\n        . = ALIGN(4);\n        *(.data*)               \/* .data* sections *\/\n        *flexspi_nor_flash_ops.o(.text*)\n        *fsl_flexspi.o(.text*)\n        . = ALIGN(4);\n    } > OCRAM AT> FLASH_TEXT\n    _ld_ocram_data_destination = ADDR(.data);\n    _ld_ocram_data_flash_copy = LOADADDR(.data);\n    _ld_ocram_data_size = SIZEOF(.data);\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n    } > OCRAM\n    _ld_ocram_bss_start = ADDR(.bss);\n    _ld_ocram_bss_size = SIZEOF(.bss);\n    _ld_heap_start = _ld_ocram_bss_start + _ld_ocram_bss_size;\n    _ld_heap_end = ORIGIN(OCRAM) + LENGTH(OCRAM);\n\n    .itcm :\n    {\n        . = ALIGN(4);\n\n        *(.itcm.*)\n\n        . = ALIGN(4);\n    } > ITCM AT> FLASH_TEXT\n    _ld_itcm_destination = ADDR(.itcm);\n    _ld_itcm_flash_copy = LOADADDR(.itcm);\n    _ld_itcm_size = SIZEOF(.itcm);\n\n    .dtcm_data :\n    {\n        . = ALIGN(4);\n\n        *(.dtcm_data.*)\n\n        . = ALIGN(4);\n    } > DTCM AT> FLASH_TEXT\n    _ld_dtcm_data_destination = ADDR(.dtcm_data);\n    _ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data);\n    _ld_dtcm_data_size = SIZEOF(.dtcm_data);\n\n    .dtcm_bss :\n    {\n        . = ALIGN(4);\n\n        *(.dtcm_bss.*)\n\n        . = ALIGN(4);\n    } > DTCM AT> DTCM\n    _ld_dtcm_bss_start = ADDR(.dtcm_bss);\n    _ld_dtcm_bss_size = SIZEOF(.dtcm_bss);\n\n    .stack :\n    {\n        . = ALIGN(8);\n        _ld_stack_bottom = .;\n        . += _ld_default_stack_size;\n    } > DTCM\n    _ld_stack_top = ORIGIN(DTCM) + LENGTH(DTCM);\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"28a5a329ec510b76cea30667e9ab23caecb997e1","subject":"This file is no longer needed.","message":"This file is no longer needed.\n\nIt provided much inspiration in its life however.  May it live on in greener bit fields.\n","repos":"karlp\/kkstm32_base","old_file":"example\/32l_lcd\/linker_stm32l.lds","new_file":"example\/32l_lcd\/linker_stm32l.lds","new_contents":"","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nENTRY(_main)\n\nMEMORY\n{\n\tsram : ORIGIN = 0x20000000, LENGTH = 0x4000\n}\n\nSECTIONS\n{\n\t.text(ORIGIN(sram)):\n\t{\n\t\t_main = .;\n\t\t_ftext = .;\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t_etext = .;\n\t} > sram\n\n\t.rodata :\n\t{\n\t\t. = ALIGN(4);\n\t\t_frodata = .;\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.rodata1)\n\t\t_erodata = .;\n\t} > sram\n\n\t.data :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fdata = .;\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t\t_gp = ALIGN(16);\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t_edata = .;\n\t} > sram\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fbss = .;\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"bfdd5a7517ebba9acb1a27615898b847133acfdc","subject":"intel_adsp: ace: Remove un-existent vectors","message":"intel_adsp: ace: Remove un-existent vectors\n\nInterrupt vectors level 5 and 6 are not available in ACE. Just remove\nthem from the linker script.\n\nSigned-off-by: Flavio Ceolin <979b9165500b0741b9d0500e2efd74fc1547bff7@intel.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/ace\/ace-link.ld","new_file":"soc\/xtensa\/intel_adsp\/ace\/ace-link.ld","new_contents":"\/*\n * Copyright (c) 2022 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <zephyr\/devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <zephyr\/linker\/sections.h>\n#include <adsp-vectors.h>\n#include <adsp_memory.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n    _imr_end = .;\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int4_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int4_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_ram_start = .;\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.initcall)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <zephyr\/linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <zephyr\/linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n     _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n\n  \/* Heap start and end markers. Used to reserve system heap memory. *\/\n  .heap_mem SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _heap_start = .;\n    *(.heap_mem)\n    _heap_end = .;\n  } >ucram\n\n  .unused_ram_start_marker SEGSTART_CACHED (NOLOAD) :\n  {\n    . = ALIGN(4096);\n    _unused_ram_start_marker = .;\n    *(.unused_ram_start_marker)\n    *(.unused_ram_start_marker.*)\n  } >ram\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n    _image_ram_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2022 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <zephyr\/devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <zephyr\/linker\/sections.h>\n#include <adsp-vectors.h>\n#include <adsp_memory.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n    _imr_end = .;\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int4_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int4_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_ram_start = .;\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.initcall)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <zephyr\/linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <zephyr\/linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n     _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n\n  \/* Heap start and end markers. Used to reserve system heap memory. *\/\n  .heap_mem SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _heap_start = .;\n    *(.heap_mem)\n    _heap_end = .;\n  } >ucram\n\n  .unused_ram_start_marker SEGSTART_CACHED (NOLOAD) :\n  {\n    . = ALIGN(4096);\n    _unused_ram_start_marker = .;\n    *(.unused_ram_start_marker)\n    *(.unused_ram_start_marker.*)\n  } >ram\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n    _image_ram_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1083ac9baca0c8a5eb138fa6b62690ab5cb2a4d6","subject":"Remove unneeded gcc_except_table section","message":"Remove unneeded gcc_except_table section\n","repos":"phil-opp\/blog_os,phil-opp\/blog_os,phil-opp\/blogOS,phil-opp\/blog_os,phil-opp\/blogOS,phil-opp\/blog_os","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/*\nCopyright 2015 Philipp Oppermann. See the README.md\nfile at the top-level directory of this distribution.\n\nLicensed under the Apache License, Version 2.0 <LICENSE-APACHE or\nhttp:\/\/www.apache.org\/licenses\/LICENSE-2.0> or the MIT license\n<LICENSE-MIT or http:\/\/opensource.org\/licenses\/MIT>, at your\noption. This file may not be copied, modified, or distributed\nexcept according to those terms.\n*\/\n\nENTRY(start)\n\nSECTIONS {\n  . = 1M;\n\n  .rodata :\n  {\n    \/* ensure that the multiboot header is at the beginning *\/\n    KEEP(*(.multiboot_header))\n    *(.rodata .rodata.*)\n    . = ALIGN(4K);\n  }\n\n  .text :\n  {\n    *(.text .text.*)\n    . = ALIGN(4K);\n  }\n\n  .data :\n  {\n    *(.data .data.*)\n    . = ALIGN(4K);\n  }\n\n  .bss :\n  {\n    *(.bss .bss.*)\n    . = ALIGN(4K);\n  }\n\n  .data.rel.ro : ALIGN(4K) {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n    . = ALIGN(4K);\n  }\n}\n","old_contents":"\/*\nCopyright 2015 Philipp Oppermann. See the README.md\nfile at the top-level directory of this distribution.\n\nLicensed under the Apache License, Version 2.0 <LICENSE-APACHE or\nhttp:\/\/www.apache.org\/licenses\/LICENSE-2.0> or the MIT license\n<LICENSE-MIT or http:\/\/opensource.org\/licenses\/MIT>, at your\noption. This file may not be copied, modified, or distributed\nexcept according to those terms.\n*\/\n\nENTRY(start)\n\nSECTIONS {\n  . = 1M;\n\n  .rodata :\n  {\n    \/* ensure that the multiboot header is at the beginning *\/\n    KEEP(*(.multiboot_header))\n    *(.rodata .rodata.*)\n    . = ALIGN(4K);\n  }\n\n  .text :\n  {\n    *(.text .text.*)\n    . = ALIGN(4K);\n  }\n\n  .data :\n  {\n    *(.data .data.*)\n    . = ALIGN(4K);\n  }\n\n  .bss :\n  {\n    *(.bss .bss.*)\n    . = ALIGN(4K);\n  }\n\n  .data.rel.ro : ALIGN(4K) {\n    *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n    . = ALIGN(4K);\n  }\n\n  .gcc_except_table : ALIGN(4K) {\n    *(.gcc_except_table)\n    . = ALIGN(4K);\n  }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"68614c5fcaafa165413660bfc960d2f9f28e8757","subject":"[x86_64] add the rest of bss to the bss section","message":"[x86_64] add the rest of bss to the bss section\n","repos":"rachlmac\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel,hawkw\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .boot :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n        *(.rodata .rodata.*)\n        . = ALIGN(4096);\n    }\n\n    .text :\n    {\n     \/* NOTE we use KEEP here to prevent the linker from dropping\n        these symbols\n      *\/\n        KEEP(*(.text._start))\n        KEEP(*(.text.arch_init))\n        *(.text .text.*)\n        . = ALIGN(4096);\n    }\n\n    .gdt :\n    {\n        KEEP(*(.gdt64))\n        KEEP(*(gdt64_ptr))\n       *(.rodata .rodata.*)\n        . = ALIGN(4096);\n    }\n\n     .data :\n     {\n       *(.data .data.*)\n       . = ALIGN(4096);\n     }\n\n     .bss :\n     {\n        \/* Page-Map Level-4 Table (PML4) *\/\n        pml4_table = .;\n        . += 4096;\n        \/* Page-Directory Pointer Table (PDP) *\/\n        pdp_table = .;\n        . += 4096;\n        \/* Page-Directory Table (PD) *\/\n        pd_table = .;\n        . += 4096;\n\n\n        stack_base = .;\n        . += 4K * 2;\n        stack_top = .;\n\n        heap_base_addr = .;\n        . += 4 * 1k * 1k;\n        heap_top_addr = .;\n\n         *(.bss .bss.*)\n\n        . = ALIGN(4096);\n     }\n\n    .got :\n    {\n      *(.got)\n      . = ALIGN(4096);\n    }\n\n    .got.plt :\n    {\n      *(.got.plt)\n      . = ALIGN(4096);\n    }\n\n    .data.rel.ro : {\n       *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n        . = ALIGN(4096);\n    }\n\n    .gcc_except_table : ALIGN(4096) {\n      *(.gcc_except_table)\n      . = ALIGN(4096);\n    }\n}\n","old_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .boot :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n        *(.rodata .rodata.*)\n        . = ALIGN(4096);\n    }\n\n    .text :\n    {\n     \/* NOTE we use KEEP here to prevent the linker from dropping\n        these symbols\n      *\/\n        KEEP(*(.text._start))\n        KEEP(*(.text.arch_init))\n        *(.text .text.*)\n        . = ALIGN(4096);\n    }\n\n    .gdt :\n    {\n        KEEP(*(.gdt64))\n        KEEP(*(gdt64_ptr))\n       *(.rodata .rodata.*)\n        . = ALIGN(4096);\n    }\n\n     .data :\n     {\n       *(.data .data.*)\n       . = ALIGN(4096);\n     }\n\n     .bss :\n     {\n        \/* Page-Map Level-4 Table (PML4) *\/\n        pml4_table = .;\n        . += 4096;\n        \/* Page-Directory Pointer Table (PDP) *\/\n        pdp_table = .;\n        . += 4096;\n        \/* Page-Directory Table (PD) *\/\n        pd_table = .;\n        . += 4096;\n\n\n        stack_base = .;\n        . += 4K * 2;\n        stack_top = .;\n\n        heap_base_addr = .;\n        . += 4 * 1k * 1k;\n        heap_top_addr = .;\n\n        . = ALIGN(4096);\n     }\n\n    .got :\n    {\n      *(.got)\n      . = ALIGN(4096);\n    }\n\n    .got.plt :\n    {\n      *(.got.plt)\n      . = ALIGN(4096);\n    }\n\n    .data.rel.ro : {\n       *(.data.rel.ro.local*) *(.data.rel.ro .data.rel.ro.*)\n        . = ALIGN(4096);\n    }\n\n    .gcc_except_table : ALIGN(4096) {\n      *(.gcc_except_table)\n      . = ALIGN(4096);\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e4537f5feae727f50c375ff272efb36538cdf4c2","subject":"userland: ld: clearer variable name","message":"userland: ld: clearer variable name\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beginning = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beginning);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beginning);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beginning);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beg = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beg);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beg);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beg);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9d08e9fb1243aff1d23ff0da1fec4d5a13f765e6","subject":"[bsp][bluetrum] update link.lds","message":"[bsp][bluetrum] update link.lds\n","repos":"geniusgogo\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread","old_file":"bsp\/bluetrum\/ab32vg1-ab-prougen\/link.lds","new_file":"bsp\/bluetrum\/ab32vg1-ab-prougen\/link.lds","new_contents":"\/* Define the flash max size *\/\n__max_flash_size = 1024k;\n\n__data_ram_size = 8k;\n__stack_ram_size = 4k;\n__comm_ram_size = 42k;\n__heap_ram_size = 70k;\n\n__base = 0x10000000;\n\n__data_vma = 0x11000;\n__stack_vma = __data_vma + __data_ram_size;\n__comm_vma = __stack_vma + __stack_ram_size;\n__heap_vma = __comm_vma + __comm_ram_size;\n\n__ram1_vma = 0x50000;\n\nMEMORY\n{\n    init            : org = __base,             len = 512\n    flash(rx)       : org = __base + 512,       len = __max_flash_size\n    comm(rx)        : org = __comm_vma,         len = __comm_ram_size\n\n    data            : org = __data_vma,         len = __data_ram_size\n    stack           : org = __stack_vma,        len = __stack_ram_size\n    heap            : org = __heap_vma,         len = __heap_ram_size\n    ram1(rx)        : org = __ram1_vma,         len = 0x7a00\n}\n\nSECTIONS\n{\n    .init : {\n        *(.reset)\n    } > init\n\n    .ram1 __ram1_vma : {\n        . = ALIGN(4);\n        \/* section information for initial *\/\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array*))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n        *save-restore.o (.text* .rodata*)\n        *libcpu*cpu*context_gcc.o (.text* .rodata*)\n        *libcpu*cpu*interrupt.o (.text* .rodata*)\n        *libcpu**.o (.rodata*)\n\n        *components*drivers*misc*pin.o(.text*)\n        *components*drivers*misc*adc.o(.text*)\n\n        . = ALIGN(4);\n        *src*ipc.o (.text* .rodata*)\n        *src*irq.o (.text* .rodata*)\n        *src*object.o (.text* .rodata*)\n        *src*thread.o (.text* .rodata*)\n        *src*timer.o (.text* .rodata*)\n        *src*mempool.o (.text* .rodata*)\n        *src*scheduler.o (.text* .rodata*)\n        *src*clock.o (.text* .rodata*)\n        *src*kservice.o (.text* .rodata*)\n        *src*device.o (.text* .rodata*)\n        *src*idle.o (.text* .rodata*)\n        *src*components.o (.text* .rodata*)\n    } > ram1 AT > flash\n\n    .comm __comm_vma : {\n        . = ALIGN(4);\n        KEEP(*(.vector))\n        *(.irq.cache)\n        *(.irq*)\n        \/* *components*src**.o (.text* .rodata*) *\/\n        *ab32vg1_hal**.o (.text* .rodata*)\n        *drv_gpio.o (.text* .rodata*)\n        *drv_usart.o (.rodata*)\n        EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata*)\n        *(.rela*)\n        *(.data*)\n        *(.sdata*)\n        *(.com_text*)\n    } > comm AT > flash\n\n    .bss (NOLOAD):\n    {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.sbss)\n        *(.buf*)\n        __bss_end = .;\n    } > data\n    __bss_size = __bss_end - __bss_start;\n\n    .stack (NOLOAD) : {\n        __irq_stack_start = .;\n        . = __stack_ram_size;\n        __irq_stack = .;\n    } > stack\n    __irq_stack_size = __irq_stack - __irq_stack_start;\n\n    .heap (NOLOAD) : {\n        __heap_start = .;\n        . = __heap_ram_size;\n        __heap_end = .;\n    } > heap\n\n    .flash : {\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(4);\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*)\n        . = ALIGN(512);\n    } > flash\n}\n\n\/* Calc the lma *\/\n__bank_size = SIZEOF(.flash);\n__comm_lma = LOADADDR(.comm);\n__comm_size = SIZEOF(.comm);\n__ram1_lma = LOADADDR(.ram1);\n__ram1_size = SIZEOF(.ram1);\n","old_contents":"\/* Define the flash max size *\/\n__max_flash_size = 1024k;\n\n__data_ram_size = 8k;\n__stack_ram_size = 4k;\n__comm_ram_size = 42k;\n__heap_ram_size = 70k;\n\n__base = 0x10000000;\n\n__data_vma = 0x11000;\n__stack_vma = __data_vma + __data_ram_size;\n__comm_vma = __stack_vma + __stack_ram_size;\n__heap_vma = __comm_vma + __comm_ram_size;\n\n__ram1_vma = 0x50000;\n\nMEMORY\n{\n    init            : org = __base,             len = 512\n    flash(rx)       : org = __base + 512,       len = __max_flash_size\n    comm(rx)        : org = __comm_vma,         len = __comm_ram_size\n\n    data            : org = __data_vma,         len = __data_ram_size\n    stack           : org = __stack_vma,        len = __stack_ram_size\n    heap            : org = __heap_vma,         len = __heap_ram_size\n    ram1(rx)        : org = __ram1_vma,         len = 0x7a00\n}\n\nSECTIONS\n{\n    .init : {\n        *(.reset)\n    } > init\n\n    .ram1 __ram1_vma : {\n        . = ALIGN(4);\n        \/* section information for initial *\/\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array*))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n        *save-restore.o (.text* .rodata*)\n        *libcpu*cpu*context_gcc.o (.text* .rodata*)\n        *libcpu*cpu*interrupt.o (.text* .rodata*)\n        *libcpu**.o (.rodata*)\n\n        *components*drivers*misc*pin.o(.text*)\n        *components*drivers*misc*adc.o(.text*)\n\n        . = ALIGN(4);\n        *src*ipc.o (.text* .rodata*)\n        *src*irq.o (.text* .rodata*)\n        *src*object.o (.text* .rodata*)\n        *src*thread.o (.text* .rodata*)\n        *src*timer.o (.text* .rodata*)\n        *src*mempool.o (.text* .rodata*)\n        *src*scheduler.o (.text* .rodata*)\n        *src*clock.o (.text* .rodata*)\n        *src*kservice.o (.text* .rodata*)\n        *src*device.o (.text* .rodata*)\n        *src*idle.o (.text* .rodata*)\n        *src*components.o (.text* .rodata*)\n    } > ram1 AT > flash\n\n    .comm __comm_vma : {\n        . = ALIGN(4);\n        KEEP(*(.vector))\n        *(.irq.cache)\n        *(.irq*)\n        *components*src**.o (.text* .rodata*)\n        *ab32vg1_hal**.o (.text* .rodata*)\n        *drv_gpio.o (.text* .rodata*)\n        *drv_usart.o (.rodata*)\n        EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata*)\n        *(.rela*)\n        *(.data*)\n        *(.sdata*)\n        *(.com_text*)\n    } > comm AT > flash\n\n    .bss (NOLOAD):\n    {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.sbss)\n        *(.buf*)\n        __bss_end = .;\n    } > data\n    __bss_size = __bss_end - __bss_start;\n\n    .stack (NOLOAD) : {\n        __irq_stack_start = .;\n        . = __stack_ram_size;\n        __irq_stack = .;\n    } > stack\n    __irq_stack_size = __irq_stack - __irq_stack_start;\n\n    .heap (NOLOAD) : {\n        __heap_start = .;\n        . = __heap_ram_size;\n        __heap_end = .;\n    } > heap\n\n    .flash : {\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(4);\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*)\n        . = ALIGN(512);\n    } > flash\n}\n\n\/* Calc the lma *\/\n__bank_size = SIZEOF(.flash);\n__comm_lma = LOADADDR(.comm);\n__comm_size = SIZEOF(.comm);\n__ram1_lma = LOADADDR(.ram1);\n__ram1_size = SIZEOF(.ram1);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"caeacf1688021a8f05bbb3251e6025e2409573d9","subject":"menu.ld: workaround for buggy old linker","message":"menu.ld: workaround for buggy old linker\n","repos":"abrasive\/satisfier,abrasive\/satisfier,abrasive\/satisfier","old_file":"menu.ld","new_file":"menu.ld","new_contents":"\/*  Copyright (c) 2015 James Laird-Wah\n *\n * This Source Code Form is subject to the terms of the Mozilla Public\n * License, v. 2.0. If a copy of the MPL was not distributed with this\n * file, you can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/. *\/\n\nOUTPUT_FORMAT(\"elf32-sh\", \"elf32-sh\",\n          \"elf32-sh\")\nOUTPUT_ARCH(sh)\nENTRY(_start)\n\nMEMORY {\n    \/* all of low Work RAM is free for our use, woo *\/\n    work_low (rwx) : org = 0x200000, l = 0x100000\n}\n\nSECTIONS {\n    .ram : {\n        __load_start = .;\n        *(.start);\n\n        *(.text);\n        *(.text.*);\n        *(.rodata);\n        *(.rodata.*);\n        *(.data);\n        *(.data.*);\n        __load_end = .;\n        __load_sectors = (__load_end - __load_start - 1)\/0x800 + 1;\n    } >work_low\n\n    .noload : {\n        *(.bss);\n        *(.bss.*);\n        *(COMMON);\n        __bss_end = .;\n        . = ALIGN(4);\n        __free_ram_begin = .;\n        __free_ram_end = __load_start + 0x100000;\n    } >work_low\n}\n","old_contents":"\/*  Copyright (c) 2015 James Laird-Wah\n *\n * This Source Code Form is subject to the terms of the Mozilla Public\n * License, v. 2.0. If a copy of the MPL was not distributed with this\n * file, you can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/. *\/\n\nOUTPUT_FORMAT(\"elf32-sh\", \"elf32-sh\",\n          \"elf32-sh\")\nOUTPUT_ARCH(sh)\nENTRY(_start)\n\nMEMORY {\n    \/* all of low Work RAM is free for our use, woo *\/\n    work_low (rwx) : org = 0x200000, l = 0x100000\n}\n\nSECTIONS {\n    .ram : {\n        __load_start = .;\n        *(.start);\n\n        *(.text);\n        *(.text.*);\n        *(.rodata);\n        *(.rodata.*);\n        *(.data);\n        *(.data.*);\n        __load_end = .;\n    } >work_low\n\n    .noload : {\n        *(.bss);\n        *(.bss.*);\n        *(COMMON);\n        __bss_end = .;\n        . = ALIGN(4);\n        __free_ram_begin = .;\n        __free_ram_end = __load_start + 0x100000;\n    } >work_low\n\n    __load_sectors = (__load_end - __load_start - 1)\/0x800 + 1;\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"37cb8dcf95fc86794ce9fd117f2e35018ce4d4f9","subject":"lm4f120: Adjust ldscript memory segment attributes","message":"lm4f120: Adjust ldscript memory segment attributes\n","repos":"BytesGalore\/RIOT,mfrey\/RIOT,rfuentess\/RIOT,neiljay\/RIOT,rfuentess\/RIOT,gebart\/RIOT,biboc\/RIOT,josephnoir\/RIOT,x3ro\/RIOT,kYc0o\/RIOT,smlng\/RIOT,rfuentess\/RIOT,gebart\/RIOT,kaspar030\/RIOT,basilfx\/RIOT,gebart\/RIOT,toonst\/RIOT,toonst\/RIOT,neiljay\/RIOT,miri64\/RIOT,BytesGalore\/RIOT,neiljay\/RIOT,neiljay\/RIOT,BytesGalore\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,lazytech-org\/RIOT,yogo1212\/RIOT,smlng\/RIOT,mtausig\/RIOT,jasonatran\/RIOT,aeneby\/RIOT,A-Paul\/RIOT,cladmi\/RIOT,kYc0o\/RIOT,toonst\/RIOT,authmillenon\/RIOT,basilfx\/RIOT,toonst\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,yogo1212\/RIOT,biboc\/RIOT,aeneby\/RIOT,toonst\/RIOT,gebart\/RIOT,josephnoir\/RIOT,miri64\/RIOT,basilfx\/RIOT,basilfx\/RIOT,cladmi\/RIOT,OTAkeys\/RIOT,x3ro\/RIOT,aeneby\/RIOT,rfuentess\/RIOT,A-Paul\/RIOT,mtausig\/RIOT,kbumsik\/RIOT,josephnoir\/RIOT,yogo1212\/RIOT,kYc0o\/RIOT,basilfx\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,x3ro\/RIOT,yogo1212\/RIOT,cladmi\/RIOT,kbumsik\/RIOT,x3ro\/RIOT,mfrey\/RIOT,miri64\/RIOT,lazytech-org\/RIOT,OlegHahm\/RIOT,biboc\/RIOT,biboc\/RIOT,OTAkeys\/RIOT,mfrey\/RIOT,RIOT-OS\/RIOT,mfrey\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,rfuentess\/RIOT,lazytech-org\/RIOT,avmelnikoff\/RIOT,authmillenon\/RIOT,kbumsik\/RIOT,neiljay\/RIOT,josephnoir\/RIOT,miri64\/RIOT,lazytech-org\/RIOT,A-Paul\/RIOT,ant9000\/RIOT,lazytech-org\/RIOT,mfrey\/RIOT,kbumsik\/RIOT,gebart\/RIOT,BytesGalore\/RIOT,avmelnikoff\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,ant9000\/RIOT,kbumsik\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,yogo1212\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,josephnoir\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,smlng\/RIOT,mtausig\/RIOT,aeneby\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,mtausig\/RIOT,smlng\/RIOT,avmelnikoff\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,cladmi\/RIOT,aeneby\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,biboc\/RIOT,x3ro\/RIOT,BytesGalore\/RIOT,smlng\/RIOT,kYc0o\/RIOT,A-Paul\/RIOT,jasonatran\/RIOT,avmelnikoff\/RIOT,A-Paul\/RIOT,avmelnikoff\/RIOT,authmillenon\/RIOT,cladmi\/RIOT,mtausig\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT","old_file":"cpu\/lm4f120\/ldscripts\/LM4F120H5QR.ld","new_file":"cpu\/lm4f120\/ldscripts\/LM4F120H5QR.ld","new_contents":"\/*\n * Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com\n *\n * This file is subject to the terms and conditions of the GNU Lesser General\n * Public License v2.1. See the file LICENSE in the top level directory for more\n * details.\n *\/\n\n\/**\n * @ingroup     cpu_lm4f120\n * @{\n *\n * @file\t\tlm4f120_linkerscript.ld\n * @brief       Linker description file for LM4FXXX microcontrollers.\n *\n * @author      Rakendra Thapa <rakendrathapa@gmail.com>\n *\n * @}\n *\/\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x00000000, LENGTH = 256K\n    ram (w!rx)  : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com\n *\n * This file is subject to the terms and conditions of the GNU Lesser General\n * Public License v2.1. See the file LICENSE in the top level directory for more\n * details.\n *\/\n\n\/**\n * @ingroup     cpu_lm4f120\n * @{\n *\n * @file\t\tlm4f120_linkerscript.ld\n * @brief       Linker description file for LM4FXXX microcontrollers.\n *\n * @author      Rakendra Thapa <rakendrathapa@gmail.com>\n *\n * @}\n *\/\nMEMORY\n{\n    rom (rx)    : ORIGIN = 0x00000000, LENGTH = 256K\n    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"6b09a06b7288bd6e80777e81da6f3797467b2cbe","subject":"Fixed 795 -nobootloader script for correct debug interface for MAX32","message":"Fixed 795 -nobootloader script for correct debug interface for MAX32\n","repos":"adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX","old_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-32MX795F512-nobootloader.ld","new_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-32MX795F512-nobootloader.ld","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size -\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7E000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0x970\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0x490\n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0xFF0 \n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 4 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 4\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 4\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 4\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_ebase_address  \t    = ORIGIN(exception_mem);\n_IMAGE_PTR_TABLE       \t= _ebase_address + 0x0F8;\n_IMAGE_HEADER_ADDR      = _ebase_address + 0x0FC;\n_GEN_EXCPT_ADDR         = _ebase_address + 0x180;\n_RESET_ADDR             = ORIGIN(kseg1_boot_mem);\n_EEPROM_ADDR            = ORIGIN(kseg0_eeprom_mem);\n_BEV_EXCPT_ADDR         = 0xBFC00380;\n_DBG_EXCPT_ADDR         = 0xBFC00480;\n_DBG_CODE_ADDR          = ORIGIN(debug_exec_mem);\n\n\/*************************************************************************\n *  Bootloader program directives.\n *  \n * _IMAGE_TYPE\n *\n *  image type:\n *\/\n     \n_imageReserved                      = 0x00000000 ;\n_imageMPIDE                         = 0x00000001 ;  \/* This is a normal MPIDE sketch                                                                                                    *\/\n_imageBootFlashBootloader           = 0x00000002 ;  \/* This is a boot flash bootloader                                                                                                  *\/\n_imageProgramFlashBootloader        = 0x00000004 ;  \/* This is a program flash bootloader                                                                                               *\/\n_imageSplitFlashBootloader          = 0x00000008 ;  \/* This has bootloader code in both boot and program flash                                                                          *\/\n\n \/*\n *  Instructions for the bootloader\n *\/\n                                                                       \n_imageFullFlashEraseLess4KEEProm    = 0x00010000 ;  \/* The original bootloader method of erasing all of program flash except the last 4K reserved for eeprom                            *\/\n_imageJustInTimeFlashErase          = 0x00020000 ;  \/* Only flash pages written too needed by the sketch is erased                                                                      *\/\n_imageLinkerSpecifiedFlashErase     = 0x00040000 ;  \/* The linker defines the flash range to erase                                                                                      *\/\n_imageFullFlashErase                = 0x00080000 ;  \/* All of flash is erased                                                                                                           *\/\n_imageExecutionJumpAddress          = 0x01000000 ;  \/* the bootloader will jump to the execution jump address immediately after programming                                             *\/\n_imageExecutionJumpToFirstInFlash   = 0x02000000 ;  \/* the bootloader will jump to the first sketch loaded in flash ignoring the execution jump address immediately after programming   *\/\n \n\/*  \n * _IMAGE_FLASH_SIZE \n *\n *      Typically _imageJustInTimeFlashErase is selected to just erase the pages\n *      of flash that code is written too; thus leaving all other flash pages untouched.\n *  \n *      If _imageLinkerSpecifiedFlashErase set, then the range\n *      starting from _ebase_address for _IMAGE_FLASH_SIZE bytes are erased.\n *\n *      If _imageFullFlashErase is specified, than the whole flash\n *      as known by the bootloader will be erased. This will erase eeprom as well\n *\n *      if _imageFullFlashEraseLess4KEEProm is set, all of flash less the last 4K is\n *      erased, this is the old default. This bit could be set to make a program flash bootloader\n *      erasing everything but the old flash. If NOTHING is set, this will be the default as this is the old behavior.\n *  \n *  _JUMP_ADDR\n *  \n *      This is the address that the bootloader will jump to start execution\n *      of the sketch. This is almost always _RESET_ADDR.\n *\n *      However, you can specify an alternate entry execution point for example\n *      if you have alternate starup code that, say, shared\n *      the runtime with other sketches or needed some kind of specific handling\n *\n *      Immediately after programming (avrdude upload) the bootloader will typically\n *      jump to the just loaded sketch, no matter where it was loaded in flash.\n *      _imageExecutionJumpToFirstInFlash will tell the bootloader to jump to the first\n *      sketch in flash even if the just loaded one is not at the beginning of flash.\n *      This is useful when programming sketches in slots of flash and then always\n *      jumping to the program-flash loader (vector sketch) as if the board was just reset.\n *      This bit does not effect jumping to a sketch already in flash after reset.\n *      As of today, after reset, the first program in flash will always be jumped to.\n *\n *************************************************************************\/\n _IMAGE_TYPE            = _imageMPIDE | _imageJustInTimeFlashErase | _imageExecutionJumpAddress;\n _IMAGE_FLASH_SIZE      = LENGTH(exception_mem) + LENGTH(kseg0_program_mem);\n_JUMP_ADDR              = _RESET_ADDR;\n\nSECTIONS\n{\n  .config_BFC02FF0 : {\n    LONG(0x3AFFFFFF)\n  } > config3\n  .config_BFC02FF4 : {\n    LONG(0xFFF879D9)\n  } > config2\n  .config_BFC02FF8 : {\n    LONG(0xFF6ACD5B)\n  } > config1\n  .config_BFC02FFC : {\n    LONG(0x7FFFFFFE)\n  } > config0\n}\n\nSECTIONS\n{\n  .bev_excpt _BEV_EXCPT_ADDR :\n  {\n    KEEP(*(.bev_handler))\n  } > kseg1_boot_mem\n\n  .dbg_excpt _DBG_EXCPT_ADDR (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x8 : 0x0);\n  } > kseg1_boot_mem\n\n  .dbg_code _DBG_CODE_ADDR (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? LENGTH(debug_exec_mem) : 0x0);\n  } > debug_exec_mem\n\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg1_boot_mem\n}\n\n\/* From here out every linker script is the same, so just include it *\/\n\/*INCLUDE \"chipKIT-application-COMMON.ld\"*\/\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size -\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7E000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0x970\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0x490\n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0xFF0 \n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 4 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 4\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 4\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 4\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_ebase_address  \t    = ORIGIN(exception_mem);\n_IMAGE_PTR_TABLE       \t= _ebase_address + 0x0F8;\n_IMAGE_HEADER_ADDR      = _ebase_address + 0x0FC;\n_GEN_EXCPT_ADDR         = _ebase_address + 0x180;\n_RESET_ADDR             = ORIGIN(kseg1_boot_mem);\n_EEPROM_ADDR            = ORIGIN(kseg0_eeprom_mem);\n_BEV_EXCPT_ADDR         = 0xBFC00380;\n_DBG_EXCPT_ADDR         = 0xBFC00480;\n_DBG_CODE_ADDR          = ORIGIN(debug_exec_mem);\n\n\/*************************************************************************\n *  Bootloader program directives.\n *  \n * _IMAGE_TYPE\n *\n *  image type:\n *\/\n     \n_imageReserved                      = 0x00000000 ;\n_imageMPIDE                         = 0x00000001 ;  \/* This is a normal MPIDE sketch                                                                                                    *\/\n_imageBootFlashBootloader           = 0x00000002 ;  \/* This is a boot flash bootloader                                                                                                  *\/\n_imageProgramFlashBootloader        = 0x00000004 ;  \/* This is a program flash bootloader                                                                                               *\/\n_imageSplitFlashBootloader          = 0x00000008 ;  \/* This has bootloader code in both boot and program flash                                                                          *\/\n\n \/*\n *  Instructions for the bootloader\n *\/\n                                                                       \n_imageFullFlashEraseLess4KEEProm    = 0x00010000 ;  \/* The original bootloader method of erasing all of program flash except the last 4K reserved for eeprom                            *\/\n_imageJustInTimeFlashErase          = 0x00020000 ;  \/* Only flash pages written too needed by the sketch is erased                                                                      *\/\n_imageLinkerSpecifiedFlashErase     = 0x00040000 ;  \/* The linker defines the flash range to erase                                                                                      *\/\n_imageFullFlashErase                = 0x00080000 ;  \/* All of flash is erased                                                                                                           *\/\n_imageExecutionJumpAddress          = 0x01000000 ;  \/* the bootloader will jump to the execution jump address immediately after programming                                             *\/\n_imageExecutionJumpToFirstInFlash   = 0x02000000 ;  \/* the bootloader will jump to the first sketch loaded in flash ignoring the execution jump address immediately after programming   *\/\n \n\/*  \n * _IMAGE_FLASH_SIZE \n *\n *      Typically _imageJustInTimeFlashErase is selected to just erase the pages\n *      of flash that code is written too; thus leaving all other flash pages untouched.\n *  \n *      If _imageLinkerSpecifiedFlashErase set, then the range\n *      starting from _ebase_address for _IMAGE_FLASH_SIZE bytes are erased.\n *\n *      If _imageFullFlashErase is specified, than the whole flash\n *      as known by the bootloader will be erased. This will erase eeprom as well\n *\n *      if _imageFullFlashEraseLess4KEEProm is set, all of flash less the last 4K is\n *      erased, this is the old default. This bit could be set to make a program flash bootloader\n *      erasing everything but the old flash. If NOTHING is set, this will be the default as this is the old behavior.\n *  \n *  _JUMP_ADDR\n *  \n *      This is the address that the bootloader will jump to start execution\n *      of the sketch. This is almost always _RESET_ADDR.\n *\n *      However, you can specify an alternate entry execution point for example\n *      if you have alternate starup code that, say, shared\n *      the runtime with other sketches or needed some kind of specific handling\n *\n *      Immediately after programming (avrdude upload) the bootloader will typically\n *      jump to the just loaded sketch, no matter where it was loaded in flash.\n *      _imageExecutionJumpToFirstInFlash will tell the bootloader to jump to the first\n *      sketch in flash even if the just loaded one is not at the beginning of flash.\n *      This is useful when programming sketches in slots of flash and then always\n *      jumping to the program-flash loader (vector sketch) as if the board was just reset.\n *      This bit does not effect jumping to a sketch already in flash after reset.\n *      As of today, after reset, the first program in flash will always be jumped to.\n *\n *************************************************************************\/\n _IMAGE_TYPE            = _imageMPIDE | _imageJustInTimeFlashErase | _imageExecutionJumpAddress;\n _IMAGE_FLASH_SIZE      = LENGTH(exception_mem) + LENGTH(kseg0_program_mem);\n_JUMP_ADDR              = _RESET_ADDR;\n\nSECTIONS\n{\n  .config_BFC02FF0 : {\n    LONG(0x3AFFFFFF)\n  } > config3\n  .config_BFC02FF4 : {\n    LONG(0xFFF879D9)\n  } > config2\n  .config_BFC02FF8 : {\n    LONG(0xFF6ACD5B)\n  } > config1\n  .config_BFC02FFC : {\n    LONG(0x7FFFFFF7)\n  } > config0\n}\n\nSECTIONS\n{\n  .bev_excpt _BEV_EXCPT_ADDR :\n  {\n    KEEP(*(.bev_handler))\n  } > kseg1_boot_mem\n\n  .dbg_excpt _DBG_EXCPT_ADDR (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x8 : 0x0);\n  } > kseg1_boot_mem\n\n  .dbg_code _DBG_CODE_ADDR (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? LENGTH(debug_exec_mem) : 0x0);\n  } > debug_exec_mem\n\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg1_boot_mem\n}\n\n\/* From here out every linker script is the same, so just include it *\/\n\/*INCLUDE \"chipKIT-application-COMMON.ld\"*\/\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"6c7e9f424a05f4cc0ce078bb3f035ba83377af47","subject":"Fixed 795 -nobootloader script for correct debug interface for MAX32","message":"Fixed 795 -nobootloader script for correct debug interface for MAX32\n","repos":"majenkotech\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX","old_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-32MX795F512-nobootloader.ld","new_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-32MX795F512-nobootloader.ld","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size -\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7E000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0x970\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0x490\n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0xFF0 \n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 4 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 4\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 4\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 4\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_ebase_address  \t    = ORIGIN(exception_mem);\n_IMAGE_PTR_TABLE       \t= _ebase_address + 0x0F8;\n_IMAGE_HEADER_ADDR      = _ebase_address + 0x0FC;\n_GEN_EXCPT_ADDR         = _ebase_address + 0x180;\n_RESET_ADDR             = ORIGIN(kseg1_boot_mem);\n_EEPROM_ADDR            = ORIGIN(kseg0_eeprom_mem);\n_BEV_EXCPT_ADDR         = 0xBFC00380;\n_DBG_EXCPT_ADDR         = 0xBFC00480;\n_DBG_CODE_ADDR          = ORIGIN(debug_exec_mem);\n\n\/*************************************************************************\n *  Bootloader program directives.\n *  \n * _IMAGE_TYPE\n *\n *  image type:\n *\/\n     \n_imageReserved                      = 0x00000000 ;\n_imageMPIDE                         = 0x00000001 ;  \/* This is a normal MPIDE sketch                                                                                                    *\/\n_imageBootFlashBootloader           = 0x00000002 ;  \/* This is a boot flash bootloader                                                                                                  *\/\n_imageProgramFlashBootloader        = 0x00000004 ;  \/* This is a program flash bootloader                                                                                               *\/\n_imageSplitFlashBootloader          = 0x00000008 ;  \/* This has bootloader code in both boot and program flash                                                                          *\/\n\n \/*\n *  Instructions for the bootloader\n *\/\n                                                                       \n_imageFullFlashEraseLess4KEEProm    = 0x00010000 ;  \/* The original bootloader method of erasing all of program flash except the last 4K reserved for eeprom                            *\/\n_imageJustInTimeFlashErase          = 0x00020000 ;  \/* Only flash pages written too needed by the sketch is erased                                                                      *\/\n_imageLinkerSpecifiedFlashErase     = 0x00040000 ;  \/* The linker defines the flash range to erase                                                                                      *\/\n_imageFullFlashErase                = 0x00080000 ;  \/* All of flash is erased                                                                                                           *\/\n_imageExecutionJumpAddress          = 0x01000000 ;  \/* the bootloader will jump to the execution jump address immediately after programming                                             *\/\n_imageExecutionJumpToFirstInFlash   = 0x02000000 ;  \/* the bootloader will jump to the first sketch loaded in flash ignoring the execution jump address immediately after programming   *\/\n \n\/*  \n * _IMAGE_FLASH_SIZE \n *\n *      Typically _imageJustInTimeFlashErase is selected to just erase the pages\n *      of flash that code is written too; thus leaving all other flash pages untouched.\n *  \n *      If _imageLinkerSpecifiedFlashErase set, then the range\n *      starting from _ebase_address for _IMAGE_FLASH_SIZE bytes are erased.\n *\n *      If _imageFullFlashErase is specified, than the whole flash\n *      as known by the bootloader will be erased. This will erase eeprom as well\n *\n *      if _imageFullFlashEraseLess4KEEProm is set, all of flash less the last 4K is\n *      erased, this is the old default. This bit could be set to make a program flash bootloader\n *      erasing everything but the old flash. If NOTHING is set, this will be the default as this is the old behavior.\n *  \n *  _JUMP_ADDR\n *  \n *      This is the address that the bootloader will jump to start execution\n *      of the sketch. This is almost always _RESET_ADDR.\n *\n *      However, you can specify an alternate entry execution point for example\n *      if you have alternate starup code that, say, shared\n *      the runtime with other sketches or needed some kind of specific handling\n *\n *      Immediately after programming (avrdude upload) the bootloader will typically\n *      jump to the just loaded sketch, no matter where it was loaded in flash.\n *      _imageExecutionJumpToFirstInFlash will tell the bootloader to jump to the first\n *      sketch in flash even if the just loaded one is not at the beginning of flash.\n *      This is useful when programming sketches in slots of flash and then always\n *      jumping to the program-flash loader (vector sketch) as if the board was just reset.\n *      This bit does not effect jumping to a sketch already in flash after reset.\n *      As of today, after reset, the first program in flash will always be jumped to.\n *\n *************************************************************************\/\n _IMAGE_TYPE            = _imageMPIDE | _imageJustInTimeFlashErase | _imageExecutionJumpAddress;\n _IMAGE_FLASH_SIZE      = LENGTH(exception_mem) + LENGTH(kseg0_program_mem);\n_JUMP_ADDR              = _RESET_ADDR;\n\nSECTIONS\n{\n  .config_BFC02FF0 : {\n    LONG(0x3AFFFFFF)\n  } > config3\n  .config_BFC02FF4 : {\n    LONG(0xFFF879D9)\n  } > config2\n  .config_BFC02FF8 : {\n    LONG(0xFF6ACD5B)\n  } > config1\n  .config_BFC02FFC : {\n    LONG(0x7FFFFFFE)\n  } > config0\n}\n\nSECTIONS\n{\n  .bev_excpt _BEV_EXCPT_ADDR :\n  {\n    KEEP(*(.bev_handler))\n  } > kseg1_boot_mem\n\n  .dbg_excpt _DBG_EXCPT_ADDR (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x8 : 0x0);\n  } > kseg1_boot_mem\n\n  .dbg_code _DBG_CODE_ADDR (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? LENGTH(debug_exec_mem) : 0x0);\n  } > debug_exec_mem\n\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg1_boot_mem\n}\n\n\/* From here out every linker script is the same, so just include it *\/\n\/*INCLUDE \"chipKIT-application-COMMON.ld\"*\/\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size -\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7E000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x1000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0x970\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0x490\n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0xFF0 \n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 4 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 4\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 4\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 4\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_ebase_address  \t    = ORIGIN(exception_mem);\n_IMAGE_PTR_TABLE       \t= _ebase_address + 0x0F8;\n_IMAGE_HEADER_ADDR      = _ebase_address + 0x0FC;\n_GEN_EXCPT_ADDR         = _ebase_address + 0x180;\n_RESET_ADDR             = ORIGIN(kseg1_boot_mem);\n_EEPROM_ADDR            = ORIGIN(kseg0_eeprom_mem);\n_BEV_EXCPT_ADDR         = 0xBFC00380;\n_DBG_EXCPT_ADDR         = 0xBFC00480;\n_DBG_CODE_ADDR          = ORIGIN(debug_exec_mem);\n\n\/*************************************************************************\n *  Bootloader program directives.\n *  \n * _IMAGE_TYPE\n *\n *  image type:\n *\/\n     \n_imageReserved                      = 0x00000000 ;\n_imageMPIDE                         = 0x00000001 ;  \/* This is a normal MPIDE sketch                                                                                                    *\/\n_imageBootFlashBootloader           = 0x00000002 ;  \/* This is a boot flash bootloader                                                                                                  *\/\n_imageProgramFlashBootloader        = 0x00000004 ;  \/* This is a program flash bootloader                                                                                               *\/\n_imageSplitFlashBootloader          = 0x00000008 ;  \/* This has bootloader code in both boot and program flash                                                                          *\/\n\n \/*\n *  Instructions for the bootloader\n *\/\n                                                                       \n_imageFullFlashEraseLess4KEEProm    = 0x00010000 ;  \/* The original bootloader method of erasing all of program flash except the last 4K reserved for eeprom                            *\/\n_imageJustInTimeFlashErase          = 0x00020000 ;  \/* Only flash pages written too needed by the sketch is erased                                                                      *\/\n_imageLinkerSpecifiedFlashErase     = 0x00040000 ;  \/* The linker defines the flash range to erase                                                                                      *\/\n_imageFullFlashErase                = 0x00080000 ;  \/* All of flash is erased                                                                                                           *\/\n_imageExecutionJumpAddress          = 0x01000000 ;  \/* the bootloader will jump to the execution jump address immediately after programming                                             *\/\n_imageExecutionJumpToFirstInFlash   = 0x02000000 ;  \/* the bootloader will jump to the first sketch loaded in flash ignoring the execution jump address immediately after programming   *\/\n \n\/*  \n * _IMAGE_FLASH_SIZE \n *\n *      Typically _imageJustInTimeFlashErase is selected to just erase the pages\n *      of flash that code is written too; thus leaving all other flash pages untouched.\n *  \n *      If _imageLinkerSpecifiedFlashErase set, then the range\n *      starting from _ebase_address for _IMAGE_FLASH_SIZE bytes are erased.\n *\n *      If _imageFullFlashErase is specified, than the whole flash\n *      as known by the bootloader will be erased. This will erase eeprom as well\n *\n *      if _imageFullFlashEraseLess4KEEProm is set, all of flash less the last 4K is\n *      erased, this is the old default. This bit could be set to make a program flash bootloader\n *      erasing everything but the old flash. If NOTHING is set, this will be the default as this is the old behavior.\n *  \n *  _JUMP_ADDR\n *  \n *      This is the address that the bootloader will jump to start execution\n *      of the sketch. This is almost always _RESET_ADDR.\n *\n *      However, you can specify an alternate entry execution point for example\n *      if you have alternate starup code that, say, shared\n *      the runtime with other sketches or needed some kind of specific handling\n *\n *      Immediately after programming (avrdude upload) the bootloader will typically\n *      jump to the just loaded sketch, no matter where it was loaded in flash.\n *      _imageExecutionJumpToFirstInFlash will tell the bootloader to jump to the first\n *      sketch in flash even if the just loaded one is not at the beginning of flash.\n *      This is useful when programming sketches in slots of flash and then always\n *      jumping to the program-flash loader (vector sketch) as if the board was just reset.\n *      This bit does not effect jumping to a sketch already in flash after reset.\n *      As of today, after reset, the first program in flash will always be jumped to.\n *\n *************************************************************************\/\n _IMAGE_TYPE            = _imageMPIDE | _imageJustInTimeFlashErase | _imageExecutionJumpAddress;\n _IMAGE_FLASH_SIZE      = LENGTH(exception_mem) + LENGTH(kseg0_program_mem);\n_JUMP_ADDR              = _RESET_ADDR;\n\nSECTIONS\n{\n  .config_BFC02FF0 : {\n    LONG(0x3AFFFFFF)\n  } > config3\n  .config_BFC02FF4 : {\n    LONG(0xFFF879D9)\n  } > config2\n  .config_BFC02FF8 : {\n    LONG(0xFF6ACD5B)\n  } > config1\n  .config_BFC02FFC : {\n    LONG(0x7FFFFFF7)\n  } > config0\n}\n\nSECTIONS\n{\n  .bev_excpt _BEV_EXCPT_ADDR :\n  {\n    KEEP(*(.bev_handler))\n  } > kseg1_boot_mem\n\n  .dbg_excpt _DBG_EXCPT_ADDR (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x8 : 0x0);\n  } > kseg1_boot_mem\n\n  .dbg_code _DBG_CODE_ADDR (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? LENGTH(debug_exec_mem) : 0x0);\n  } > debug_exec_mem\n\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg1_boot_mem\n}\n\n\/* From here out every linker script is the same, so just include it *\/\n\/*INCLUDE \"chipKIT-application-COMMON.ld\"*\/\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"b64197fba653b76ad4d14afbfdce6d1bfcf724a4","subject":"linker: tweak section naming to feet all linkers","message":"linker: tweak section naming to feet all linkers\n\nMWDT toolchain adds additional suffix to sections name\nin case of ffunction-sections \/ fdata-sections are enabled.\nLet's pick a single set of rules and syntax that work.\n\nSigned-off-by: Watson Zeng <bb6a45ebfbb8932a11537002b062f5218879c562@synopsys.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,nashif\/zephyr","old_file":"include\/linker\/intlist.ld","new_file":"include\/linker\/intlist.ld","new_contents":"\/*\n * Copyright (c) 2017 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* This creates a special section which is not included by the final binary,\n * instead it is consumed by the gen_isr_tables.py script.\n *\n * What we create here is a data structure:\n *\n * struct {\n *\tuint32_t num_vectors;       <- typically CONFIG_NUM_IRQS\n *\tstruct _isr_list isrs[]; <- Usually of smaller size than num_vectors\n * }\n *\n * Which indicates the memory address of the number of isrs that were\n * defined, the total number of IRQ lines in the system, followed by\n * an appropriate number of instances of struct _isr_list. See\n * include\/sw_isr_table.h\n *\n * You will need to declare a bogus memory region for IDT_LIST. It doesn't\n * matter where this region goes as it is stripped from the final ELF image.\n * The address doesn't even have to be valid on the target. However, it\n * shouldn't overlap any other regions. On most arches the following should be\n * fine:\n *\n * MEMORY {\n *\t.. other regions ..\n *\tIDT_LIST        : ORIGIN = 0xfffff7ff, LENGTH = 2K\n * }\n *\/\n\n#ifndef LINKER_ZEPHYR_FINAL\nSECTION_PROLOGUE(.intList,,)\n{\n\tKEEP(*(.irq_info*))\n\tKEEP(*(.intList*))\n} GROUP_ROM_LINK_IN(IDT_LIST, IDT_LIST)\n#else\n\/DISCARD\/ :\n{\n\tKEEP(*(.irq_info*))\n\tKEEP(*(.intList*))\n}\n#endif\n","old_contents":"\/*\n * Copyright (c) 2017 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* This creates a special section which is not included by the final binary,\n * instead it is consumed by the gen_isr_tables.py script.\n *\n * What we create here is a data structure:\n *\n * struct {\n *\tuint32_t num_vectors;       <- typically CONFIG_NUM_IRQS\n *\tstruct _isr_list isrs[]; <- Usually of smaller size than num_vectors\n * }\n *\n * Which indicates the memory address of the number of isrs that were\n * defined, the total number of IRQ lines in the system, followed by\n * an appropriate number of instances of struct _isr_list. See\n * include\/sw_isr_table.h\n *\n * You will need to declare a bogus memory region for IDT_LIST. It doesn't\n * matter where this region goes as it is stripped from the final ELF image.\n * The address doesn't even have to be valid on the target. However, it\n * shouldn't overlap any other regions. On most arches the following should be\n * fine:\n *\n * MEMORY {\n *\t.. other regions ..\n *\tIDT_LIST        : ORIGIN = 0xfffff7ff, LENGTH = 2K\n * }\n *\/\n\n#ifndef LINKER_ZEPHYR_FINAL\nSECTION_PROLOGUE(.intList,,)\n{\n\tKEEP(*(.irq_info))\n\tKEEP(*(.intList))\n} GROUP_ROM_LINK_IN(IDT_LIST, IDT_LIST)\n#else\n\/DISCARD\/ :\n{\n\tKEEP(*(.irq_info*))\n\tKEEP(*(.intList*))\n}\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1f1c68ce1938116c034d09e26b6383833d0bf363","subject":" [LPC1768 GCC_CR exporter] Fixed linker description","message":" [LPC1768 GCC_CR exporter] Fixed linker description\n\n* Divide AHB SRAM for USB and Ethernet RAM regions\n* Add NOLOAD keyword for .bss sections to avoid redundant data in final\nimage\n","repos":"nabilbendafi\/mbed,mmorenobarm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,Timmmm\/mbed,andcor02\/mbed-os,mmorenobarm\/mbed-os,DanKupiniak\/mbed,jpbrucker\/mbed,netzimme\/mbed-os,K4zuki\/mbed,mazimkhan\/mbed-os,dbestm\/mbed,nabilbendafi\/mbed,rosterloh\/mbed,arostm\/mbed-os,netzimme\/mbed-os,bentwire\/mbed,mikaleppanen\/mbed-os,mazimkhan\/mbed-os,mazimkhan\/mbed-os,RonEld\/mbed,dbestm\/mbed,svastm\/mbed,catiedev\/mbed-os,maximmbed\/mbed,c1728p9\/mbed-os,betzw\/mbed-os,nvlsianpu\/mbed,bulislaw\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,tung7970\/mbed-os,infinnovation\/mbed-os,jferreir\/mbed,karsev\/mbed-os,monkiineko\/mbed-os,ryankurte\/mbed-os,tung7970\/mbed-os-1,rgrover\/mbed,devanlai\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,pbrook\/mbed,getopenmono\/mbed,fanghuaqi\/mbed,theotherjimmy\/mbed,pradeep-gr\/mbed-os5-onsemi,infinnovation\/mbed-os,rgrover\/mbed,monkiineko\/mbed-os,devanlai\/mbed,HeadsUpDisplayInc\/mbed,YarivCol\/mbed-os,j-greffe\/mbed-os,adamgreen\/mbed,pedromes\/mbed,mbedmicro\/mbed,bulislaw\/mbed-os,pbrook\/mbed,DanKupiniak\/mbed,tung7970\/mbed-os,NXPmicro\/mbed,svogl\/mbed-os,kpurusho\/mbed,cvtsi2sd\/mbed-os,YarivCol\/mbed-os,karsev\/mbed-os,monkiineko\/mbed-os,pbrook\/mbed,RonEld\/mbed,theotherjimmy\/mbed,devanlai\/mbed,monkiineko\/mbed-os,NXPmicro\/mbed,svogl\/mbed-os,screamerbg\/mbed,nRFMesh\/mbed-os,screamerbg\/mbed,pbrook\/mbed,pedromes\/mbed,fahhem\/mbed-os,cvtsi2sd\/mbed-os,screamerbg\/mbed,NXPmicro\/mbed,Timmmm\/mbed,netzimme\/mbed-os,CalSol\/mbed,nabilbendafi\/mbed,andreaslarssonublox\/mbed,rosterloh\/mbed,pbrook\/mbed,jrjang\/mbed,kjbracey-arm\/mbed,catiedev\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,infinnovation\/mbed-os,jferreir\/mbed,fanghuaqi\/mbed,Tiryoh\/mbed,kpurusho\/mbed,maximmbed\/mbed,c1728p9\/mbed-os,mbedmicro\/mbed,al177\/mbed,tung7970\/mbed-os-1,al177\/mbed,Archcady\/mbed-os,geky\/mbed,rgrover\/mbed,brstew\/MBED-BUILD,tung7970\/mbed-os-1,jrjang\/mbed,HeadsUpDisplayInc\/mbed,kl-cruz\/mbed-os,maximmbed\/mbed,j-greffe\/mbed-os,ARM-software\/mbed-beetle,kpurusho\/mbed,dbestm\/mbed,jferreir\/mbed,j-greffe\/mbed-os,netzimme\/mbed-os,svogl\/mbed-os,dbestm\/mbed,DanKupiniak\/mbed,getopenmono\/mbed,devanlai\/mbed,fanghuaqi\/mbed,netzimme\/mbed-os,j-greffe\/mbed-os,bentwire\/mbed,bikeNomad\/mbed,Shengliang\/mbed,theotherjimmy\/mbed,pradeep-gr\/mbed-os5-onsemi,HeadsUpDisplayInc\/mbed,Tiryoh\/mbed,geky\/mbed,Timmmm\/mbed,fahhem\/mbed-os,mazimkhan\/mbed-os,arostm\/mbed-os,adustm\/mbed,HeadsUpDisplayInc\/mbed,jpbrucker\/mbed,rgrover\/mbed,RonEld\/mbed,K4zuki\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,kjbracey-arm\/mbed,Archcady\/mbed-os,nabilbendafi\/mbed,bcostm\/mbed-os,fahhem\/mbed-os,dbestm\/mbed,RonEld\/mbed,fahhem\/mbed-os,betzw\/mbed-os,bikeNomad\/mbed,adustm\/mbed,pradeep-gr\/mbed-os5-onsemi,karsev\/mbed-os,jeremybrodt\/mbed,jferreir\/mbed,mmorenobarm\/mbed-os,ryankurte\/mbed-os,K4zuki\/mbed,tung7970\/mbed-os-1,tung7970\/mbed-os,geky\/mbed,jpbrucker\/mbed,Archcady\/mbed-os,bentwire\/mbed,brstew\/MBED-BUILD,geky\/mbed,cvtsi2sd\/mbed-os,pradeep-gr\/mbed-os5-onsemi,Shengliang\/mbed,devanlai\/mbed,adamgreen\/mbed,theotherjimmy\/mbed,kl-cruz\/mbed-os,theotherjimmy\/mbed,bentwire\/mbed,catiedev\/mbed-os,ryankurte\/mbed-os,brstew\/MBED-BUILD,Tiryoh\/mbed,bikeNomad\/mbed,YarivCol\/mbed-os,geky\/mbed,arostm\/mbed-os,jrjang\/mbed,YarivCol\/mbed-os,svastm\/mbed,bcostm\/mbed-os,CalSol\/mbed,mikaleppanen\/mbed-os,nRFMesh\/mbed-os,svastm\/mbed,andcor02\/mbed-os,infinnovation\/mbed-os,kl-cruz\/mbed-os,andcor02\/mbed-os,pbrook\/mbed,bulislaw\/mbed-os,rosterloh\/mbed,bulislaw\/mbed-os,betzw\/mbed-os,kjbracey-arm\/mbed,ryankurte\/mbed-os,karsev\/mbed-os,jeremybrodt\/mbed,andreaslarssonublox\/mbed,maximmbed\/mbed,adustm\/mbed,pedromes\/mbed,rosterloh\/mbed,kpurusho\/mbed,DanKupiniak\/mbed,mikaleppanen\/mbed-os,nvlsianpu\/mbed,bulislaw\/mbed-os,adustm\/mbed,getopenmono\/mbed,andreaslarssonublox\/mbed,arostm\/mbed-os,andreaslarssonublox\/mbed,cvtsi2sd\/mbed-os,fvincenzo\/mbed-os,fahhem\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,adamgreen\/mbed,mnlipp\/mbed,Shengliang\/mbed,fanghuaqi\/mbed,rosterloh\/mbed,fvincenzo\/mbed-os,Shengliang\/mbed,karsev\/mbed-os,infinnovation\/mbed-os,jferreir\/mbed,betzw\/mbed-os,Archcady\/mbed-os,Tiryoh\/mbed,kl-cruz\/mbed-os,mmorenobarm\/mbed-os,mazimkhan\/mbed-os,svogl\/mbed-os,CalSol\/mbed,c1728p9\/mbed-os,adamgreen\/mbed,K4zuki\/mbed,rgrover\/mbed,cvtsi2sd\/mbed-os,jeremybrodt\/mbed,bulislaw\/mbed-os,getopenmono\/mbed,nvlsianpu\/mbed,mbedmicro\/mbed,c1728p9\/mbed-os,cvtsi2sd\/mbed-os,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,nRFMesh\/mbed-os,rosterloh\/mbed,bentwire\/mbed,betzw\/mbed-os,Shengliang\/mbed,tung7970\/mbed-os,Timmmm\/mbed,andreaslarssonublox\/mbed,tung7970\/mbed-os-1,kl-cruz\/mbed-os,ARM-software\/mbed-beetle,jpbrucker\/mbed,bcostm\/mbed-os,jferreir\/mbed,mnlipp\/mbed,andcor02\/mbed-os,jeremybrodt\/mbed,K4zuki\/mbed,brstew\/MBED-BUILD,Timmmm\/mbed,getopenmono\/mbed,infinnovation\/mbed-os,HeadsUpDisplayInc\/mbed,ARM-software\/mbed-beetle,screamerbg\/mbed,andcor02\/mbed-os,Archcady\/mbed-os,tung7970\/mbed-os,c1728p9\/mbed-os,al177\/mbed,bcostm\/mbed-os,ryankurte\/mbed-os,j-greffe\/mbed-os,NXPmicro\/mbed,CalSol\/mbed,catiedev\/mbed-os,CalSol\/mbed,jpbrucker\/mbed,monkiineko\/mbed-os,bcostm\/mbed-os,j-greffe\/mbed-os,mazimkhan\/mbed-os,Tiryoh\/mbed,jeremybrodt\/mbed,mnlipp\/mbed,nvlsianpu\/mbed,RonEld\/mbed,arostm\/mbed-os,ryankurte\/mbed-os,screamerbg\/mbed,al177\/mbed,jpbrucker\/mbed,bcostm\/mbed-os,screamerbg\/mbed,Tiryoh\/mbed,al177\/mbed,dbestm\/mbed,theotherjimmy\/mbed,nabilbendafi\/mbed,svastm\/mbed,fvincenzo\/mbed-os,nRFMesh\/mbed-os,NXPmicro\/mbed,mnlipp\/mbed,adustm\/mbed,mikaleppanen\/mbed-os,Archcady\/mbed-os,RonEld\/mbed,mmorenobarm\/mbed-os,arostm\/mbed-os,adamgreen\/mbed,kpurusho\/mbed,netzimme\/mbed-os,fvincenzo\/mbed-os,YarivCol\/mbed-os,CalSol\/mbed,nRFMesh\/mbed-os,NXPmicro\/mbed,mikaleppanen\/mbed-os,kl-cruz\/mbed-os,ARM-software\/mbed-beetle,svastm\/mbed,jrjang\/mbed,svogl\/mbed-os,bikeNomad\/mbed,karsev\/mbed-os,fanghuaqi\/mbed,kpurusho\/mbed,pedromes\/mbed,fahhem\/mbed-os,adustm\/mbed,svogl\/mbed-os,catiedev\/mbed-os,bikeNomad\/mbed,mbedmicro\/mbed,K4zuki\/mbed,al177\/mbed,fvincenzo\/mbed-os,mmorenobarm\/mbed-os,brstew\/MBED-BUILD,radhika-raghavendran\/mbed-os5.1-onsemi,nvlsianpu\/mbed,maximmbed\/mbed,jrjang\/mbed,maximmbed\/mbed,mbedmicro\/mbed,pedromes\/mbed,monkiineko\/mbed-os,Shengliang\/mbed,pedromes\/mbed,bentwire\/mbed,nvlsianpu\/mbed,mikaleppanen\/mbed-os,kjbracey-arm\/mbed,c1728p9\/mbed-os,getopenmono\/mbed,Timmmm\/mbed,catiedev\/mbed-os,andcor02\/mbed-os,adamgreen\/mbed,devanlai\/mbed,mnlipp\/mbed,jrjang\/mbed,nRFMesh\/mbed-os,mnlipp\/mbed,brstew\/MBED-BUILD,HeadsUpDisplayInc\/mbed,YarivCol\/mbed-os,nabilbendafi\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_CR\/LPC1768.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_CR\/LPC1768.ld","new_contents":"\/* mbed - LPC1768 linker script\n * Based linker script generated by Code Red Technologies Red Suite 4.1\n *\/\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 \/* 512k *\/\n  RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 \/* 32k *\/\n  RamAHB_USB (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x4000 \/* 16k *\/\n  RamAHB_Eth (rwx) : ORIGIN = 0x20080000, LENGTH = 0x4000 \/* 16k *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash512 = 0x0 + 0x80000;\n  __top_RamLoc32 = 0x10000000 + 0x8000;\n  __top_RamAHB32 = 0x2007c000 + 0x8000;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/ \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data)) ;\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2)) ;\n        LONG(  SIZEOF(.data_RAM2));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        \/* End C++ *\/\n    } > MFlash512\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this.\n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash512\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash512\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n        *(.data.$RAM2*)\n        *(.data.$RamAHB32*)\n       . = ALIGN(4) ;\n    } > RamAHB_USB AT>MFlash512\n    \n    \/* MAIN DATA SECTION *\/\n\n    .uninit_RESERVED(NOLOAD) : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n    } > RamLoc32\n\n    .data : ALIGN(4)\n    {\n        FILL(0xff)\n        _data = .;\n        *(vtable)\n        *(.data*)\n        . = ALIGN(4) ;\n        _edata = .;\n    } > RamLoc32 AT>MFlash512\n\n    \n    .bss_RAM2(NOLOAD) : ALIGN(4)\n    {\n        *(.bss.$RAM2*)\n        *(.bss.$RamAHB32*)\n        *(AHBSRAM0)\n       . = ALIGN(4) ;\n    } > RamAHB_USB\n\n    .bss_RAM3(NOLOAD) : ALIGN(4)\n    {\n        *(AHBSRAM1)\n       . = ALIGN(4) ;\n    } > RamAHB_Eth\n    \/* MAIN BSS SECTION *\/\n    .bss(NOLOAD) : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > RamLoc32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_RamLoc32 - 0);\n}\n","old_contents":"\/* mbed - LPC1768 linker script\n * Based linker script generated by Code Red Technologies Red Suite 4.1\n *\/\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 \/* 512k *\/\n  RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 \/* 32k *\/\n  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 \/* 32k *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash512 = 0x0 + 0x80000;\n  __top_RamLoc32 = 0x10000000 + 0x8000;\n  __top_RamAHB32 = 0x2007c000 + 0x8000;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/ \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data)) ;\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2)) ;\n        LONG(  SIZEOF(.data_RAM2));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n        \/* End C++ *\/\n    } > MFlash512\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this.\n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash512\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash512\n    __exidx_end = .;\n    \n    _etext = .;\n        \n    \n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n        *(.data.$RAM2*)\n        *(.data.$RamAHB32*)\n       . = ALIGN(4) ;\n    } > RamAHB32 AT>MFlash512\n    \n    \/* MAIN DATA SECTION *\/\n\n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n    } > RamLoc32\n\n    .data : ALIGN(4)\n    {\n        FILL(0xff)\n        _data = .;\n        *(vtable)\n        *(.data*)\n        . = ALIGN(4) ;\n        _edata = .;\n    } > RamLoc32 AT>MFlash512\n\n    \n    .bss_RAM2 : ALIGN(4)\n    {\n        *(.bss.$RAM2*)\n        *(.bss.$RamAHB32*)\n       . = ALIGN(4) ;\n    } > RamAHB32\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > RamLoc32\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_RamLoc32 - 0);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c817bd35c5dec317efb3d051807faafb4be351c4","subject":"Delete kernel.ld","message":"Delete kernel.ld","repos":"jspaulse\/sugarcat,jspaulse\/sugarcat,jspaulse\/sugarcat","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(reset)\nkv_start \t= 0x80000000;\n\nSECTIONS {\n\t. = 0x8000;\n\t\n\t.start_sec : {\n\t\tss_start = .;\n\t\t\/* text *\/\n\t\tbuild\/armv6_boot.o(.text)\n\t\tbuild\/armv6_init.o(.text .text.*)\n\n\t\t\/* rodata *\/\n\t\tbuild\/armv6_boot.o(.rodata .rodata.*)\n\t\tbuild\/armv6_init.o(.rodata .rodata.*)\n\t\t\n\t\t\/* data *\/\n\t\tbuild\/armv6_boot.o(.data .data.*)\n\t\tbuild\/armv6_init.o(.data .data.*)\n\n\t\t\/* bss *\/\n\t\tss_bss_start = .;\n\t\tbuild\/armv6_boot.o(.bss .bss.* COMMON)\n\t\tbuild\/armv6_init.o(.bss .bss.* COMMON)\n\t\tss_bss_end\t= .;\n\t\t\n\t\t. = ALIGN(0x1000);\n\t\t. += 0x1000;\n\t\tsvc_stack = .;\n\t\tss_end = .;\n\t}\n\t. = kv_start + ss_end;\n\t\n\tk_start = .;\n\t.text : AT(ss_end) { \n\t\t*(.text .text* .gnu.linkonce.t.*) \n\t}\n\t\n\tPROVIDE(etext = .);\n    .rodata : { *(.rodata*) } \n    .data : { *(.data*) } \n    .bss : { \n\t\tbss_start = .;\n\t\t*(.bss*) \n\t\tbss_end\t= .;\n\t}\n\t\n\t. = ALIGN(0x1000);\n\tk_end = .;\n}\n\n\/*\nSECTIONS {\n\tk_start = .;\n    .text : { *(.text*) } > ram\n    .rodata : { *(.rodata*) } > ram\n    .data : { *(.data*) } > ram\n    .bss : { \n\t\tbss_start = .;\n\t\t*(.bss*) \n\t\tbss_end\t= .;\n\t} > ram\n    . = ALIGN(0x2000);\n    PROVIDE (mmu_kpgdir = .);\n    . += 0x2000;\n    PROVIDE(mmu_upgdir = .);\n    . += 0x2000;\n    k_end = .;\n}\n*\/\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"34d5a3cd4134b942b6db0cd8a47dd633faaf1ed4","subject":"linker: include constant strings","message":"linker: include constant strings\n\ngcc generates funkily named rodata sections that ended up not making it\ninto the image.\n","repos":"abrasive\/satisfier,abrasive\/satisfier,abrasive\/satisfier","old_file":"ldscript.ld","new_file":"ldscript.ld","new_contents":"\/*  Copyright (c) 2015 James Laird-Wah\n *\n * This Source Code Form is subject to the terms of the Mozilla Public\n * License, v. 2.0. If a copy of the MPL was not distributed with this\n * file, you can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/. *\/\n\nOUTPUT_FORMAT(\"elf32-sh\", \"elf32-sh\",\n          \"elf32-sh\")\nOUTPUT_ARCH(sh)\nENTRY(_start)\n\nMEMORY {\n    initial (rwx) : org = 0x200000, l = 0x8000\n}\n\nSECTIONS {\n    .initial : {\n        __load_start = .;\n        *(.start);\n        *ashiftrt.o(.text); \/* necessary for the BIOS load *\/\n\n        *(.text);\n        *(.rodata);\n        *(.rodata.*);\n        *(.data);\n        __load_end = .;\n        *(.bss);\n        __bss_end = .;\n    } >initial\n}\n","old_contents":"\/*  Copyright (c) 2015 James Laird-Wah\n *\n * This Source Code Form is subject to the terms of the Mozilla Public\n * License, v. 2.0. If a copy of the MPL was not distributed with this\n * file, you can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/. *\/\n\nOUTPUT_FORMAT(\"elf32-sh\", \"elf32-sh\",\n          \"elf32-sh\")\nOUTPUT_ARCH(sh)\nENTRY(_start)\n\nMEMORY {\n    initial (rwx) : org = 0x200000, l = 0x8000\n}\n\nSECTIONS {\n    .initial : {\n        __load_start = .;\n        *(.start);\n        *ashiftrt.o(.text); \/* necessary for the BIOS load *\/\n\n        *(.text);\n        *(.rodata);\n        *(.data);\n        __load_end = .;\n        *(.bss);\n        __bss_end = .;\n    } >initial\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"f63375b606118db653e8fbd5075ec55bd983c542","subject":"No Heap!","message":"No Heap!","repos":"rbsexton\/gecko,rbsexton\/gecko,rbsexton\/gecko","old_file":"tiny\/bringup\/launcher\/efm32tg.ld","new_file":"tiny\/bringup\/launcher\/efm32tg.ld","new_contents":"\/* Linker script for Silicon Labs EFM32TG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 4.1.0 *\/\r\n\/*                                                                  *\/\r\n\r\nMEMORY\r\n{\r\n  \/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144 *\/\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8192\r\n  \/* RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768 *\/\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 2048 + 512\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.vectors))\r\n    __Vectors_End = .;\r\n    __Vectors_Size = __Vectors_End - __Vectors;\r\n    __end__ = .;\r\n\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  \/* To copy multiple ROM to RAM sections,\r\n   * uncomment .copy.table section and,\r\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .copy.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __copy_table_start__ = .;\r\n    LONG (__etext)\r\n    LONG (__data_start__)\r\n    LONG (__data_end__ - __data_start__)\r\n    LONG (__etext2)\r\n    LONG (__data2_start__)\r\n    LONG (__data2_end__ - __data2_start__)\r\n    __copy_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  \/* To clear multiple BSS sections,\r\n   * uncomment .zero.table section and,\r\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .zero.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __zero_table_start__ = .;\r\n    LONG (__bss_start__)\r\n    LONG (__bss_end__ - __bss_start__)\r\n    LONG (__bss2_start__)\r\n    LONG (__bss2_end__ - __bss2_start__)\r\n    __zero_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy (COPY):\r\n  {\r\n    KEEP(*(.stack*))\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","old_contents":"\/* Linker script for Silicon Labs EFM32TG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 4.1.0 *\/\r\n\/*                                                                  *\/\r\n\r\nMEMORY\r\n{\r\n  \/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144 *\/\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8192\r\n  \/* RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768 *\/\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 2048 + 512\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.vectors))\r\n    __Vectors_End = .;\r\n    __Vectors_Size = __Vectors_End - __Vectors;\r\n    __end__ = .;\r\n\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  \/* To copy multiple ROM to RAM sections,\r\n   * uncomment .copy.table section and,\r\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .copy.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __copy_table_start__ = .;\r\n    LONG (__etext)\r\n    LONG (__data_start__)\r\n    LONG (__data_end__ - __data_start__)\r\n    LONG (__etext2)\r\n    LONG (__data2_start__)\r\n    LONG (__data2_end__ - __data2_start__)\r\n    __copy_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  \/* To clear multiple BSS sections,\r\n   * uncomment .zero.table section and,\r\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .zero.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __zero_table_start__ = .;\r\n    LONG (__bss_start__)\r\n    LONG (__bss_end__ - __bss_start__)\r\n    LONG (__bss2_start__)\r\n    LONG (__bss2_end__ - __bss2_start__)\r\n    __zero_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap (COPY):\r\n  {\r\n    __HeapBase = .;\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    KEEP(*(.heap*))\r\n    __HeapLimit = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy (COPY):\r\n  {\r\n    KEEP(*(.stack*))\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f0311ce1fa9d3ea9bbb9b61066f1bfab88668e80","subject":"kinetis\/ldscript: include _rom_offset","message":"kinetis\/ldscript: include _rom_offset\n\n- To be able to flash at an offset the vector table must be\n  relocated accordingly to the IMAGE_OFFSET, therefore linkage\n  needs to take the offset into account.\n","repos":"x3ro\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,OTAkeys\/RIOT,rfuentess\/RIOT,cladmi\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,cladmi\/RIOT,rfuentess\/RIOT,x3ro\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,mtausig\/RIOT,rfuentess\/RIOT,rfuentess\/RIOT,basilfx\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,smlng\/RIOT,authmillenon\/RIOT,toonst\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,toonst\/RIOT,mtausig\/RIOT,josephnoir\/RIOT,toonst\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,smlng\/RIOT,x3ro\/RIOT,RIOT-OS\/RIOT,josephnoir\/RIOT,basilfx\/RIOT,yogo1212\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,aeneby\/RIOT,miri64\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,toonst\/RIOT,smlng\/RIOT,OTAkeys\/RIOT,cladmi\/RIOT,mtausig\/RIOT,miri64\/RIOT,aeneby\/RIOT,yogo1212\/RIOT,aeneby\/RIOT,aeneby\/RIOT,mtausig\/RIOT,cladmi\/RIOT,miri64\/RIOT,mtausig\/RIOT,rfuentess\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,OlegHahm\/RIOT,cladmi\/RIOT,miri64\/RIOT,x3ro\/RIOT,kYc0o\/RIOT,josephnoir\/RIOT,yogo1212\/RIOT,kYc0o\/RIOT,basilfx\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,josephnoir\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,toonst\/RIOT,smlng\/RIOT,basilfx\/RIOT,kaspar030\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,josephnoir\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,smlng\/RIOT","old_file":"cpu\/kinetis\/ldscripts\/kinetis.ld","new_file":"cpu\/kinetis\/ldscripts\/kinetis.ld","new_contents":"\/*\n * Copyright (C) 2015 PHYTEC Messtechnik GmbH\n * Copyright (C) 2015-2017 Eistec AB\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_kinetis\n * @{\n *\n * @file\n * @brief           Sections definitions for the Freescale Kinetis MCUs\n *\n * @author          Johann Fischer <j.fischer@phytec.de>\n * @author          Joakim Nohlg\u00e5rd <joakim.nohlgard@eistec.se>\n *\n * @}\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\n_vectors_length = 0x400;\n_flashsec_length = 0x10;\n\nINCLUDE cortexm_rom_offset.ld\n\n_flash_sec_offset = _vectors_length + _rom_offset;\n\nMEMORY\n{\n    vectors    : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _vectors_length\n    flashsec   : ORIGIN = _rom_start_addr + _vectors_length + _rom_offset, LENGTH = _flashsec_length\n    rom (rx)   : ORIGIN = _rom_start_addr + _vectors_length + _flashsec_length + _rom_offset, LENGTH = _fw_rom_length - (_vectors_length + _flashsec_length)\n    ram (!rx)  : ORIGIN = _ram_start_addr, LENGTH = _ram_length\n}\n\nSECTIONS\n{\n    \/* Interrupt vectors 0x00-0x3ff. *\/\n    .vector :\n    {\n        _isr_vectors = .;\n        KEEP(*(SORT(.vector*)))\n    } > vectors\n    ASSERT (SIZEOF(.vector) == _vectors_length, \"Interrupt vector table of invalid size.\")\n    ASSERT (ADDR(.vector) == _rom_offset, \"Interrupt vector table at invalid location (linker-script error?)\")\n    ASSERT (LOADADDR(.vector) == _rom_offset, \"Interrupt vector table at invalid location (linker-script error?)\")\n\n    \/* Flash configuration field, very important in order to not accidentally lock the device *\/\n    \/* Flash configuration field 0x400-0x40f. *\/\n    .fcfield :\n    {\n        . = ALIGN(4);\n        KEEP(*(.fcfield))\n        . = ALIGN(4);\n    } > flashsec\n    ASSERT (SIZEOF(.fcfield) == _flashsec_length, \"Flash configuration field of invalid size (linker-script error?)\")\n    ASSERT (ADDR(.fcfield) == _flash_sec_offset, \"Flash configuration field at invalid position (linker-script error?)\")\n    ASSERT (LOADADDR(.fcfield) == _flash_sec_offset, \"Flash configuration field at invalid position (linker-script error?)\")\n}\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2015 PHYTEC Messtechnik GmbH\n * Copyright (C) 2015-2017 Eistec AB\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_kinetis\n * @{\n *\n * @file\n * @brief           Sections definitions for the Freescale Kinetis MCUs\n *\n * @author          Johann Fischer <j.fischer@phytec.de>\n * @author          Joakim Nohlg\u00e5rd <joakim.nohlgard@eistec.se>\n *\n * @}\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\n\n_vectors_length = 0x400;\n_flashsec_length = 0x10;\n\nMEMORY\n{\n    vectors    : ORIGIN = _rom_start_addr, LENGTH = _vectors_length\n    flashsec   : ORIGIN = _rom_start_addr + _vectors_length, LENGTH = _flashsec_length\n    rom (rx)   : ORIGIN = _rom_start_addr + _vectors_length + _flashsec_length, LENGTH = _rom_length - (_vectors_length + _flashsec_length)\n    ram (!rx)  : ORIGIN = _ram_start_addr, LENGTH = _ram_length\n}\n\nSECTIONS\n{\n    \/* Interrupt vectors 0x00-0x3ff. *\/\n    .vector :\n    {\n        _isr_vectors = .;\n        KEEP(*(SORT(.vector*)))\n    } > vectors\n    ASSERT (SIZEOF(.vector) == 0x400, \"Interrupt vector table of invalid size.\")\n    ASSERT (ADDR(.vector) == 0x00000000, \"Interrupt vector table at invalid location (linker-script error?)\")\n    ASSERT (LOADADDR(.vector) == 0x00000000, \"Interrupt vector table at invalid location (linker-script error?)\")\n\n    \/* Flash configuration field, very important in order to not accidentally lock the device *\/\n    \/* Flash configuration field 0x400-0x40f. *\/\n    .fcfield :\n    {\n        . = ALIGN(4);\n        KEEP(*(.fcfield))\n        . = ALIGN(4);\n    } > flashsec\n    ASSERT (SIZEOF(.fcfield) == 0x10, \"Flash configuration field of invalid size (linker-script error?)\")\n    ASSERT (ADDR(.fcfield) == 0x400, \"Flash configuration field at invalid position (linker-script error?)\")\n    ASSERT (LOADADDR(.fcfield) == 0x400, \"Flash configuration field at invalid position (linker-script error?)\")\n}\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"cf4cf6ac86739f373595b3553955285aefeec058","subject":"Move .multiboot section as first item in .text section","message":"Move .multiboot section as first item in .text section\n\nFor some reason having KEEP(*(.multiboot)) in the .boot section caused\nmultiboot header code from mb2.S to be physically at the end of the elf\nfile, but it would be relocated to the beginning so all was well. Until\nmy program grew larger than 32K and the grub wouldn't find the\nmultiboot header.\n\nBy having it explicitly at the beginning of the .text section all is\nnow well!\n","repos":"winksaville\/sadie,winksaville\/sadie","old_file":"platform\/pc_x86_64\/meson.link.ld","new_file":"platform\/pc_x86_64\/meson.link.ld","new_contents":"\/*\n * Copyright 2015 Wink Saville\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/*\n * A x86_64 linker script\n *\n * Model after [this](http:\/\/wiki.osdev.org\/Creating_a_64-bit_kernel#Linking)\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n  \/* Start at image 1 meg *\/\n  . = 1M;\n\n  \/* multiboot section must be first *\/\n  .text BLOCK(4K) : ALIGN(4K) {\n    *(.multiboot)\n    *(.text)\n  }\n\n  \/* Read-write data (initialized) *\/\n  .data BLOCK(4K) : ALIGN(4K) {\n    *(.data)\n  }\n\n  \/* Read-write data (uninitialized) *\/\n  .bss BLOCK(4K) : ALIGN(4K) {\n    *(COMMON)\n    *(.bss)\n  }\n\n  \/* Stack separate *\/\n  .stack BLOCK(4K) : ALIGN(4K) {\n    *(.bootstrap_stack)\n  }\n\n  \/* Other sections will be here *\/\n}\n","old_contents":"\/*\n * Copyright 2015 Wink Saville\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/*\n * A x86_64 linker script\n *\n * Model after [this](http:\/\/wiki.osdev.org\/Creating_a_64-bit_kernel#Linking)\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n  \/* Start at image 1 meg *\/\n  . = 1M;\n\n  \/* multiboot section must be first then text *\/\n  .boot BLOCK(4K) : ALIGN(4K) {\n    KEEP(*(.multiboot))\n  }\n\n  \/* multiboot section must be first then text *\/\n  .text BLOCK(4K) : ALIGN(4K) {\n    *(.text)\n  }\n\n  \/* Read-write data (initialized) *\/\n  .data BLOCK(4K) : ALIGN(4K) {\n    *(.data)\n  }\n\n  \/* Read-write data (uninitialized) *\/\n  .bss BLOCK(4K) : ALIGN(4K) {\n    *(COMMON)\n    *(.bss)\n  }\n\n  \/* Stack separate *\/\n  .stack BLOCK(4K) : ALIGN(4K) {\n    *(.bootstrap_stack)\n  }\n\n  \/* Other sections will be here *\/\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"dd36f09cae0fc11627bedca6e2861a7cf10b4b31","subject":"pw_boot_cortex_m: Add comment to linker file","message":"pw_boot_cortex_m: Add comment to linker file\n\nAdds a comment to basic_cortex_m.ld that was previously in a CL\ndescription.\n\nChange-Id: I8bc5c0f023d0ee811fa39d55865c1359090a5f6a\nReviewed-on: https:\/\/pigweed-review.googlesource.com\/c\/pigweed\/pigweed\/+\/107174\nReviewed-by: Keir Mierle <69344103cc60b36d6e1fbdc31ce6504b2286c646@google.com>\nCommit-Queue: Keir Mierle <69344103cc60b36d6e1fbdc31ce6504b2286c646@google.com>\n","repos":"google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed,google\/pigweed","old_file":"pw_boot_cortex_m\/basic_cortex_m.ld","new_file":"pw_boot_cortex_m\/basic_cortex_m.ld","new_contents":"\/*\n * Copyright 2020 The Pigweed Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\"); you may not\n * use this file except in compliance with the License. You may obtain a copy of\n * the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n * License for the specific language governing permissions and limitations under\n * the License.\n *\/\n\n\/* This relatively simplified linker script will work with many ARMv7-M and\n * ARMv8-M cores that have on-board memory-mapped RAM and FLASH. For more\n * complex projects and devices, it's possible this linker script will not be\n * sufficient as-is.\n *\n * This linker script is likely not suitable for a project with a bootloader.\n *\/\n\n\/* Provide useful error messages when required configurations are not set. *\/\n#ifndef PW_BOOT_VECTOR_TABLE_BEGIN\n#error \"PW_BOOT_VECTOR_TABLE_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_BEGIN\n\n#ifndef PW_BOOT_VECTOR_TABLE_SIZE\n#error \"PW_BOOT_VECTOR_TABLE_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_SIZE\n\n#ifndef PW_BOOT_FLASH_BEGIN\n#error \"PW_BOOT_FLASH_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_BEGIN\n\n#ifndef PW_BOOT_FLASH_SIZE\n#error \"PW_BOOT_FLASH_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_SIZE\n\n#ifndef PW_BOOT_RAM_BEGIN\n#error \"PW_BOOT_RAM_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_BEGIN\n\n#ifndef PW_BOOT_RAM_SIZE\n#error \"PW_BOOT_RAM_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_SIZE\n\n#ifndef PW_BOOT_HEAP_SIZE\n#error \"PW_BOOT_HEAP_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_HEAP_SIZE\n\n#ifndef PW_BOOT_MIN_STACK_SIZE\n#error \"PW_BOOT_MIN_STACK_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_MIN_STACK_SIZE\n\n\n\/* Note: This technically doesn't set the firmware's entry point. Setting the\n *       firmware entry point is done by setting vector_table[1]\n *       (Reset_Handler). However, this DOES tell the compiler how to optimize\n *       when --gc-sections is enabled.\n *\/\nENTRY(pw_boot_Entry)\n\nMEMORY\n{\n  \/* TODO(b\/234892223): Make it possible for projects to freely customize\n   * memory regions.\n   *\/\n\n  \/* Vector Table (typically in flash) *\/\n  VECTOR_TABLE(rx) : \\\n    ORIGIN = PW_BOOT_VECTOR_TABLE_BEGIN, \\\n    LENGTH = PW_BOOT_VECTOR_TABLE_SIZE\n  \/* Internal Flash *\/\n  FLASH(rx) : \\\n    ORIGIN = PW_BOOT_FLASH_BEGIN, \\\n    LENGTH = PW_BOOT_FLASH_SIZE\n  \/* Internal SRAM *\/\n  RAM(rwx) : \\\n    ORIGIN = PW_BOOT_RAM_BEGIN, \\\n    LENGTH = PW_BOOT_RAM_SIZE\n}\n\nSECTIONS\n{\n  \/* This is the link-time vector table. If used, the VTOR (Vector Table Offset\n   * Register) MUST point to this memory location in order to be used. This can\n   * be done by ensuring this section exists at the default location of the VTOR\n   * so it's used on reset, or by explicitly setting the VTOR in a bootloader\n   * manually to point to &pw_boot_vector_table_addr before interrupts are enabled.\n   *\/\n  .vector_table : ALIGN(512)\n  {\n    pw_boot_vector_table_addr = .;\n    KEEP(*(.vector_table))\n  } >VECTOR_TABLE\n\n  \/* Main executable code. *\/\n  .code : ALIGN(8)\n  {\n    . = ALIGN(8);\n    \/* Application code. *\/\n    *(.text)\n    *(.text*)\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    . = ALIGN(8);\n    \/* Constants.*\/\n    *(.rodata)\n    *(.rodata*)\n\n    \/* .preinit_array, .init_array, .fini_array are used by libc.\n     * Each section is a list of function pointers that are called pre-main and\n     * post-exit for object initialization and tear-down.\n     * Since the region isn't explicitly referenced, specify KEEP to prevent\n     * link-time garbage collection. SORT is used for sections that have strict\n     * init\/de-init ordering requirements. *\/\n    . = ALIGN(8);\n    PROVIDE_HIDDEN(__preinit_array_start = .);\n    KEEP(*(.preinit_array*))\n    PROVIDE_HIDDEN(__preinit_array_end = .);\n\n    PROVIDE_HIDDEN(__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array*))\n    PROVIDE_HIDDEN(__init_array_end = .);\n\n    PROVIDE_HIDDEN(__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array*))\n    PROVIDE_HIDDEN(__fini_array_end = .);\n  } >FLASH\n\n  \/* Used by unwind-arm\/ *\/\n  .ARM : ALIGN(8) {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  \/* Explicitly initialized global and static data. (.data)*\/\n  .static_init_ram : ALIGN(8)\n  {\n    *(.data)\n    *(.data*)\n    . = ALIGN(8);\n  } >RAM AT> FLASH\n\n  \/* The .zero_init_ram and .heap sections below require (NOLOAD) annotations\n   * for lld, but not ld, because lld intentionally interprets the linker file\n   * differently from ld:\n   * https:\/\/discourse.llvm.org\/t\/lld-vs-ld-section-type-progbits-vs-nobits\/5999\/3\n   *\/\n\n  \/* Zero initialized global\/static data. (.bss)\n   * This section is zero initialized in pw_boot_Entry(). *\/\n  .zero_init_ram (NOLOAD) : ALIGN(8)\n  {\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(8);\n  } >RAM\n\n  .heap (NOLOAD) : ALIGN(8)\n  {\n    pw_boot_heap_low_addr = .;\n    . = . + PW_BOOT_HEAP_SIZE;\n    . = ALIGN(8);\n    pw_boot_heap_high_addr = .;\n  } >RAM\n\n  \/* Link-time check for stack overlaps. *\/\n  .stack (NOLOAD) : ALIGN(8)\n  {\n    \/* Set the address that the main stack pointer should be initialized to. *\/\n    pw_boot_stack_low_addr = .;\n    HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);\n    \/* Align the stack to a lower address to ensure it isn't out of range. *\/\n    HIDDEN(_stack_high = (. + _stack_size) & ~0x7);\n    ASSERT(_stack_high - . >= PW_BOOT_MIN_STACK_SIZE,\n           \"Error: Not enough RAM for desired minimum stack size.\");\n    . = _stack_high;\n    pw_boot_stack_high_addr = .;\n  } >RAM\n\n  \/* Discard unwind info. *\/\n  .ARM.extab 0x0 (INFO) :\n  {\n    KEEP(*(.ARM.extab*))\n  }\n\n  \/* The unused_space symbols do not currently work in clang\/lld and result in\n   * binary bloat by several orders of magnitude. Allow disabling them until a\n   * proper workaround is in place.\n   *\/\n  #if !PW_BOOT_WORKAROUND_DISABLE_UNUSED_SPACE\n  \/*\n   * Do not declare any output sections after this comment. This area is\n   * reserved only for declaring unused sections of memory. These sections are\n   * used by pw_bloat.bloaty_config to create the utilization data source for\n   * bloaty.\n   *\/\n  .VECTOR_TABLE.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(VECTOR_TABLE) + LENGTH(VECTOR_TABLE));\n  } >VECTOR_TABLE\n\n  .FLASH.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(FLASH) + LENGTH(FLASH));\n  } >FLASH\n\n  .RAM.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(RAM) + LENGTH(RAM));\n  } >RAM\n  #endif \/*PW_BOOT_WORKAROUND_DISABLE_UNUSED_SPACE*\/\n}\n\n\/* Symbols used by core_init.c: *\/\n\/* Start of .static_init_ram in FLASH. *\/\n_pw_static_init_flash_start = LOADADDR(.static_init_ram);\n\n\/* Region of .static_init_ram in RAM. *\/\n_pw_static_init_ram_start = ADDR(.static_init_ram);\n_pw_static_init_ram_end = _pw_static_init_ram_start + SIZEOF(.static_init_ram);\n\n\/* Region of .zero_init_ram. *\/\n_pw_zero_init_ram_start = ADDR(.zero_init_ram);\n_pw_zero_init_ram_end = _pw_zero_init_ram_start + SIZEOF(.zero_init_ram);\n\n\/* arm-none-eabi expects `end` symbol to point to start of heap for sbrk. *\/\nPROVIDE(end = _pw_zero_init_ram_end);\n\n\/* These symbols are used by pw_bloat.bloaty_config to create the memoryregions\n * data source for bloaty in this format (where the optional _N defaults to 0):\n * pw_bloat_config_memory_region_NAME_{start,end}{_N,} *\/\npw_bloat_config_memory_region_VECTOR_TABLE_start = ORIGIN(VECTOR_TABLE);\npw_bloat_config_memory_region_VECTOR_TABLE_end =\n    ORIGIN(VECTOR_TABLE) + LENGTH(VECTOR_TABLE);\npw_bloat_config_memory_region_FLASH_start = ORIGIN(FLASH);\npw_bloat_config_memory_region_FLASH_end = ORIGIN(FLASH) + LENGTH(FLASH);\npw_bloat_config_memory_region_RAM_start = ORIGIN(RAM);\npw_bloat_config_memory_region_RAM_end = ORIGIN(RAM) + LENGTH(RAM);\n","old_contents":"\/*\n * Copyright 2020 The Pigweed Authors\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\"); you may not\n * use this file except in compliance with the License. You may obtain a copy of\n * the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n * License for the specific language governing permissions and limitations under\n * the License.\n *\/\n\n\/* This relatively simplified linker script will work with many ARMv7-M and\n * ARMv8-M cores that have on-board memory-mapped RAM and FLASH. For more\n * complex projects and devices, it's possible this linker script will not be\n * sufficient as-is.\n *\n * This linker script is likely not suitable for a project with a bootloader.\n *\/\n\n\/* Provide useful error messages when required configurations are not set. *\/\n#ifndef PW_BOOT_VECTOR_TABLE_BEGIN\n#error \"PW_BOOT_VECTOR_TABLE_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_BEGIN\n\n#ifndef PW_BOOT_VECTOR_TABLE_SIZE\n#error \"PW_BOOT_VECTOR_TABLE_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_VECTOR_TABLE_SIZE\n\n#ifndef PW_BOOT_FLASH_BEGIN\n#error \"PW_BOOT_FLASH_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_BEGIN\n\n#ifndef PW_BOOT_FLASH_SIZE\n#error \"PW_BOOT_FLASH_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_FLASH_SIZE\n\n#ifndef PW_BOOT_RAM_BEGIN\n#error \"PW_BOOT_RAM_BEGIN is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_BEGIN\n\n#ifndef PW_BOOT_RAM_SIZE\n#error \"PW_BOOT_RAM_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_RAM_SIZE\n\n#ifndef PW_BOOT_HEAP_SIZE\n#error \"PW_BOOT_HEAP_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_HEAP_SIZE\n\n#ifndef PW_BOOT_MIN_STACK_SIZE\n#error \"PW_BOOT_MIN_STACK_SIZE is not defined, and is required to use pw_boot_cortex_m\"\n#endif  \/\/ PW_BOOT_MIN_STACK_SIZE\n\n\n\/* Note: This technically doesn't set the firmware's entry point. Setting the\n *       firmware entry point is done by setting vector_table[1]\n *       (Reset_Handler). However, this DOES tell the compiler how to optimize\n *       when --gc-sections is enabled.\n *\/\nENTRY(pw_boot_Entry)\n\nMEMORY\n{\n  \/* TODO(b\/234892223): Make it possible for projects to freely customize\n   * memory regions.\n   *\/\n\n  \/* Vector Table (typically in flash) *\/\n  VECTOR_TABLE(rx) : \\\n    ORIGIN = PW_BOOT_VECTOR_TABLE_BEGIN, \\\n    LENGTH = PW_BOOT_VECTOR_TABLE_SIZE\n  \/* Internal Flash *\/\n  FLASH(rx) : \\\n    ORIGIN = PW_BOOT_FLASH_BEGIN, \\\n    LENGTH = PW_BOOT_FLASH_SIZE\n  \/* Internal SRAM *\/\n  RAM(rwx) : \\\n    ORIGIN = PW_BOOT_RAM_BEGIN, \\\n    LENGTH = PW_BOOT_RAM_SIZE\n}\n\nSECTIONS\n{\n  \/* This is the link-time vector table. If used, the VTOR (Vector Table Offset\n   * Register) MUST point to this memory location in order to be used. This can\n   * be done by ensuring this section exists at the default location of the VTOR\n   * so it's used on reset, or by explicitly setting the VTOR in a bootloader\n   * manually to point to &pw_boot_vector_table_addr before interrupts are enabled.\n   *\/\n  .vector_table : ALIGN(512)\n  {\n    pw_boot_vector_table_addr = .;\n    KEEP(*(.vector_table))\n  } >VECTOR_TABLE\n\n  \/* Main executable code. *\/\n  .code : ALIGN(8)\n  {\n    . = ALIGN(8);\n    \/* Application code. *\/\n    *(.text)\n    *(.text*)\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    . = ALIGN(8);\n    \/* Constants.*\/\n    *(.rodata)\n    *(.rodata*)\n\n    \/* .preinit_array, .init_array, .fini_array are used by libc.\n     * Each section is a list of function pointers that are called pre-main and\n     * post-exit for object initialization and tear-down.\n     * Since the region isn't explicitly referenced, specify KEEP to prevent\n     * link-time garbage collection. SORT is used for sections that have strict\n     * init\/de-init ordering requirements. *\/\n    . = ALIGN(8);\n    PROVIDE_HIDDEN(__preinit_array_start = .);\n    KEEP(*(.preinit_array*))\n    PROVIDE_HIDDEN(__preinit_array_end = .);\n\n    PROVIDE_HIDDEN(__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array*))\n    PROVIDE_HIDDEN(__init_array_end = .);\n\n    PROVIDE_HIDDEN(__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array*))\n    PROVIDE_HIDDEN(__fini_array_end = .);\n  } >FLASH\n\n  \/* Used by unwind-arm\/ *\/\n  .ARM : ALIGN(8) {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  \/* Explicitly initialized global and static data. (.data)*\/\n  .static_init_ram : ALIGN(8)\n  {\n    *(.data)\n    *(.data*)\n    . = ALIGN(8);\n  } >RAM AT> FLASH\n\n  \/* Zero initialized global\/static data. (.bss)\n   * This section is zero initialized in pw_boot_Entry(). *\/\n  .zero_init_ram (NOLOAD) : ALIGN(8)\n  {\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(8);\n  } >RAM\n\n  .heap (NOLOAD) : ALIGN(8)\n  {\n    pw_boot_heap_low_addr = .;\n    . = . + PW_BOOT_HEAP_SIZE;\n    . = ALIGN(8);\n    pw_boot_heap_high_addr = .;\n  } >RAM\n\n  \/* Link-time check for stack overlaps. *\/\n  .stack (NOLOAD) : ALIGN(8)\n  {\n    \/* Set the address that the main stack pointer should be initialized to. *\/\n    pw_boot_stack_low_addr = .;\n    HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);\n    \/* Align the stack to a lower address to ensure it isn't out of range. *\/\n    HIDDEN(_stack_high = (. + _stack_size) & ~0x7);\n    ASSERT(_stack_high - . >= PW_BOOT_MIN_STACK_SIZE,\n           \"Error: Not enough RAM for desired minimum stack size.\");\n    . = _stack_high;\n    pw_boot_stack_high_addr = .;\n  } >RAM\n\n  \/* Discard unwind info. *\/\n  .ARM.extab 0x0 (INFO) :\n  {\n    KEEP(*(.ARM.extab*))\n  }\n\n  \/* The unused_space symbols do not currently work in clang\/lld and result in\n   * binary bloat by several orders of magnitude. Allow disabling them until a\n   * proper workaround is in place.\n   *\/\n  #if !PW_BOOT_WORKAROUND_DISABLE_UNUSED_SPACE\n  \/*\n   * Do not declare any output sections after this comment. This area is\n   * reserved only for declaring unused sections of memory. These sections are\n   * used by pw_bloat.bloaty_config to create the utilization data source for\n   * bloaty.\n   *\/\n  .VECTOR_TABLE.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(VECTOR_TABLE) + LENGTH(VECTOR_TABLE));\n  } >VECTOR_TABLE\n\n  .FLASH.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(FLASH) + LENGTH(FLASH));\n  } >FLASH\n\n  .RAM.unused_space (NOLOAD) : ALIGN(8)\n  {\n    . = ABSOLUTE(ORIGIN(RAM) + LENGTH(RAM));\n  } >RAM\n  #endif \/*PW_BOOT_WORKAROUND_DISABLE_UNUSED_SPACE*\/\n}\n\n\/* Symbols used by core_init.c: *\/\n\/* Start of .static_init_ram in FLASH. *\/\n_pw_static_init_flash_start = LOADADDR(.static_init_ram);\n\n\/* Region of .static_init_ram in RAM. *\/\n_pw_static_init_ram_start = ADDR(.static_init_ram);\n_pw_static_init_ram_end = _pw_static_init_ram_start + SIZEOF(.static_init_ram);\n\n\/* Region of .zero_init_ram. *\/\n_pw_zero_init_ram_start = ADDR(.zero_init_ram);\n_pw_zero_init_ram_end = _pw_zero_init_ram_start + SIZEOF(.zero_init_ram);\n\n\/* arm-none-eabi expects `end` symbol to point to start of heap for sbrk. *\/\nPROVIDE(end = _pw_zero_init_ram_end);\n\n\/* These symbols are used by pw_bloat.bloaty_config to create the memoryregions\n * data source for bloaty in this format (where the optional _N defaults to 0):\n * pw_bloat_config_memory_region_NAME_{start,end}{_N,} *\/\npw_bloat_config_memory_region_VECTOR_TABLE_start = ORIGIN(VECTOR_TABLE);\npw_bloat_config_memory_region_VECTOR_TABLE_end =\n    ORIGIN(VECTOR_TABLE) + LENGTH(VECTOR_TABLE);\npw_bloat_config_memory_region_FLASH_start = ORIGIN(FLASH);\npw_bloat_config_memory_region_FLASH_end = ORIGIN(FLASH) + LENGTH(FLASH);\npw_bloat_config_memory_region_RAM_start = ORIGIN(RAM);\npw_bloat_config_memory_region_RAM_end = ORIGIN(RAM) + LENGTH(RAM);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1258ff73bf5c6a66bc5248b92bdb8a27f8f452f4","subject":"bochs fix","message":"bochs fix\n","repos":"jinet-vm\/vmm,jinet-vm\/vmm,ilya101010\/demos,ilya101010\/demos,jinet-vm\/vmm,ilya101010\/demos,jinet-vm\/vmm","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"MEMORY\n{\n\tbootloader : org = 0x7c00, len = 1k\n\tbasic_kernel : org = 0x8000, len = 16K-1\n\tfill : org = 0xBFFF, len = 1\n}\n\nOUTPUT_FORMAT(\"binary\")\nOUTPUT(\"final.img\")\nENTRY(start)\n\nSECTIONS\n{\n \t. = 0;\n\t.boot : {\n\t\tFILL(0);\n\t\t*(.text16);\n\t\t*(.data16);\n\t\t. = 510;\n\t\tSHORT(0xaa55);\n\t\t*(.text32);\n\t} > bootloader\n\n\t.text :\n\t{\n\t\t:*(.text)\n\t} > basic_kernel\n\n\t.data :\n\t{\n\t\t:*(.data);\n\t} > basic_kernel\n\n\t.bss :\n\t{\n\t\t:*(.bss);\n\t} > basic_kernel\n\n\t.fill :\n\t{\n\t\tBYTE(0x90);\n\t} > fill\n}","old_contents":"MEMORY\n{\n\tbootloader : org = 0x7c00, len = 1k\n\tbasic_kernel : org = 0x8000, len = 16K-1\n\tsysenter : org = 0xBC00, len = 1\n}\n\nOUTPUT_FORMAT(\"binary\")\nOUTPUT(\"final.img\")\nENTRY(start)\n\nSECTIONS\n{\n \t. = 0;\n\t.boot : {\n\t\tFILL(0);\n\t\t*(.text16);\n\t\t*(.data16);\n\t\t. = 510;\n\t\tSHORT(0xaa55);\n\t\t*(.text32);\n\t} > bootloader\n\n\t.text :\n\t{\n\t\t:*(.text)\n\t} > basic_kernel\n\n\t.data :\n\t{\n\t\t:*(.data);\n\t} > basic_kernel\n\n\t.bss :\n\t{\n\t\t:*(.bss);\n\t} > basic_kernel\n\n\t.fill :\n\t{\n\t\tBYTE(0x90);\n\t} > sysenter\n}","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5551b3f61628fc815293cb6e93d32bf2dfe6a141","subject":"bootloader: move iram_seg 1k up to have better looking idf_monitor output","message":"bootloader: move iram_seg 1k up to have better looking idf_monitor output\n\nWhen 2nd stage bootloader loads the ROM bootloader, it prints a\nmessage similar to \"entry 0x40080xxx\", which idf_monitor decodes\n(using application ELF file) as one of the reset vectors (xxx is <\n400h). This moves the iram_seg of bootloader 1k up to prevent overlap\nof bootloader .text and application vectors, making the output look\nnicer. There is still a chance that the entry point decodes as some\nsymbol in application ELF file, but at least it won't have\n\"Exception\" in its name.\n","repos":"mashaoze\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,espressif\/esp-idf,armada-ai\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf,www220\/esp-idf,espressif\/esp-idf,www220\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/esp32.bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/esp32.bootloader.ld","new_contents":"\/*\nLinker file used to link the bootloader.\n*\/\n\n\n\/* Simplified memory map for the bootloader\n\n   The main purpose is to make sure the bootloader can load into main memory\n   without overwriting itself.\n*\/\n\nMEMORY\n{\n  \/* I\/O *\/\n  dport0_seg (RW) :                 \torg = 0x3FF00000, len = 0x10\n  \/* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache *\/\n  iram_loader_seg (RWX) :           org = 0x40078000, len = 0x8000  \/* 32KB, APP CPU cache *\/\n  \/* 63kB, IRAM. We skip the first 1k to prevent the entry point being\n     placed into the same range as exception vectors in the app.\n     This leads to idf_monitor decoding ROM bootloader \"entry 0x40080xxx\"\n     message as one of the exception vectors, which looks scary to users.\n  *\/\n  iram_seg (RWX) :                  org = 0x40080400, len = 0xfc00\n  \/* 64k at the end of DRAM, after ROM bootloader stack *\/\n  dram_seg (RW) :                  \torg = 0x3FFF0000, len = 0x10000\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.o(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_loader_seg\n  \n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","old_contents":"\/*\nLinker file used to link the bootloader.\n*\/\n\n\n\/* Simplified memory map for the bootloader\n\n   The main purpose is to make sure the bootloader can load into main memory\n   without overwriting itself.\n*\/\n\nMEMORY\n{\n  \/* I\/O *\/\n  dport0_seg (RW) :                 \torg = 0x3FF00000, len = 0x10\n  \/* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache *\/\n  iram_loader_seg (RWX) :           org = 0x40078000, len = 0x8000  \/* 32KB, APP CPU cache *\/\n  iram_seg (RWX) :                  org = 0x40080000, len = 0x10000 \/* 64KB, IRAM *\/\n  \/* 64k at the end of DRAM, after ROM bootloader stack *\/\n  dram_seg (RW) :                  \torg = 0x3FFF0000, len = 0x10000\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.o(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.o(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_loader_seg\n  \n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"051be79e93e0808f52f7ceb7c277856141bc9c73","subject":"[sw,rom] Save 32 bytes at top of ROM for digest","message":"[sw,rom] Save 32 bytes at top of ROM for digest\n\nSigned-off-by: Rupert Swarbrick <290093e2ad2515ed2f14d749293c8cf8e02ca274@lowrisc.org>\n","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan","old_file":"sw\/device\/boot_rom\/rom_link.ld","new_file":"sw\/device\/boot_rom\/rom_link.ld","new_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * Linker script for an OpenTitan boot ROM.\n *\n * Portions of this file are Ibex-specific.\n *\/\n\nOUTPUT_ARCH(riscv)\nGROUP(-lgcc)\n\n\/**\n * Indicate that there are no dynamic libraries, whatsoever.\n *\/\n__DYNAMIC = 0;\n\nINCLUDE hw\/top_earlgrey\/sw\/autogen\/top_earlgrey_memory.ld\n\n\/**\n * The boot address, which indicates the location of the initial interrupt\n * vector.\n *\/\n_boot_address = ORIGIN(rom);\n\n_heap_size = 0xe000;\n_stack_size = LENGTH(ram_main) - _heap_size;\n_stack_end = ORIGIN(ram_main) + LENGTH(ram_main);\n_stack_start = _stack_end - _stack_size;\n_flash_start = ORIGIN(eflash);\n\n\/**\n * This symbol points at the header of the flash binary, which contains loading\n * and signing information.\n *\n * See sw\/device\/lib\/ext\/common\/flash_link.ld, under the .flash_header section,\n * which populates it.\n *\/\n_flash_header = _flash_start;\n\n_rom_digest_size = 32;\n_chip_info_size = 128;\n_chip_info_start = ORIGIN(rom) + LENGTH(rom) - _rom_digest_size - _chip_info_size;\n\n\/* DV Log offset (has to be different to other boot stages). *\/\n_dv_log_offset = 0x0;\n\n\/**\n * We define an entry point only for documentation purposes (and to stop LLD\n * erroring). In reality, we don't use this information within the ROM image, as\n * we start at a fixed offset.\n *\/\nENTRY(_reset_start);\n\n\/**\n * NOTE: We have to align each section to word boundaries as our current\n * s19->slm conversion scripts are not able to handle non-word aligned sections.\n *\/\nSECTIONS {\n  \/**\n   * Ibex interrupt vector. See irq_vector.S for more information.\n   *\n   * This has to be set up at the boot address, so that execution jumps to the\n   * reset handler correctly.\n   *\/\n  .vectors _boot_address : ALIGN(4) {\n    KEEP(*(.vectors))\n  } > rom\n\n  \/**\n   * C runtime (CRT) section, containing program initialization code.\n   *\/\n  .crt : ALIGN(4) {\n    KEEP(*(.crt))\n  } > rom\n\n  \/**\n   * Standard text section, containing program code.\n   *\/\n  .text : ALIGN(4) {\n    *(.text)\n    *(.text.*)\n  } > rom\n\n  \/**\n   * Read-only data section, containing all large compile-time constants, like\n   * strings.\n   *\/\n  .rodata : ALIGN(4) {\n    \/* Small read-only data comes before regular read-only data for the same\n     * reasons as in the data section *\/\n    *(.srodata)\n    *(.srodata.*)\n    *(.rodata)\n    *(.rodata.*)\n  } > rom\n\n  \/**\n   * \"Intitial data\" section, the initial values of the mutable data section\n   * initialized at runtime.\n   *\/\n  .idata : ALIGN(4) {\n    _data_init_start = .;\n  } > rom\n\n  \/**\n   * Standard mutable data section, at the bottom of RAM. This will be\n   * initialized from the .idata section at runtime by the CRT.\n   *\/\n  .data ORIGIN(ram_main): AT(_data_init_start) ALIGN(4) {\n    _data_start = .;\n    __global_pointer$ = . + 2048;\n\n    \/* Small data should come before larger data. This helps to ensure small\n     * globals are within 2048 bytes of the value of `gp`, making their accesses\n     * hopefully only take one instruction. *\/\n    *(.sdata)\n    *(.sdata.*)\n\n    \/* Other data will likely need multiple instructions to load, so we're less\n     * concerned about address materialisation taking more than one instruction.\n     *\/\n    *(.data)\n    *(.data.*)\n    . = ALIGN(4);\n    _data_end = .;\n  } > ram_main\n\n  \/**\n   * Immutable chip_info data, containing build-time-recorded information.\n   *\/\n  .chip_info _chip_info_start : ALIGN(4) {\n    *(.chip_info)\n  } > rom\n\n  \/**\n   * Standard BSS section. This will be zeroed at runtime by the CRT.\n   *\/\n  .bss : ALIGN(4) {\n    _bss_start = .;\n    \/* Small BSS comes before regular BSS for the same reasons as in the data\n     * section *\/\n    *(.sbss)\n    *(.sbss.*)\n    *(.bss)\n    *(.bss.*)\n    . = ALIGN(4);\n    _bss_end = .;\n  } > ram_main\n\n  INCLUDE sw\/device\/info_sections.ld\n}\n","old_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * Linker script for an OpenTitan boot ROM.\n *\n * Portions of this file are Ibex-specific.\n *\/\n\nOUTPUT_ARCH(riscv)\nGROUP(-lgcc)\n\n\/**\n * Indicate that there are no dynamic libraries, whatsoever.\n *\/\n__DYNAMIC = 0;\n\nINCLUDE hw\/top_earlgrey\/sw\/autogen\/top_earlgrey_memory.ld\n\n\/**\n * The boot address, which indicates the location of the initial interrupt\n * vector.\n *\/\n_boot_address = ORIGIN(rom);\n\n_heap_size = 0xe000;\n_stack_size = LENGTH(ram_main) - _heap_size;\n_stack_end = ORIGIN(ram_main) + LENGTH(ram_main);\n_stack_start = _stack_end - _stack_size;\n_flash_start = ORIGIN(eflash);\n\n\/**\n * This symbol points at the header of the flash binary, which contains loading\n * and signing information.\n *\n * See sw\/device\/lib\/ext\/common\/flash_link.ld, under the .flash_header section,\n * which populates it.\n *\/\n_flash_header = _flash_start;\n\n_chip_info_size = 128;\n_chip_info_start = ORIGIN(rom) + LENGTH(rom) - _chip_info_size;\n\n\/* DV Log offset (has to be different to other boot stages). *\/\n_dv_log_offset = 0x0;\n\n\/**\n * We define an entry point only for documentation purposes (and to stop LLD\n * erroring). In reality, we don't use this information within the ROM image, as\n * we start at a fixed offset.\n *\/\nENTRY(_reset_start);\n\n\/**\n * NOTE: We have to align each section to word boundaries as our current\n * s19->slm conversion scripts are not able to handle non-word aligned sections.\n *\/\nSECTIONS {\n  \/**\n   * Ibex interrupt vector. See irq_vector.S for more information.\n   *\n   * This has to be set up at the boot address, so that execution jumps to the\n   * reset handler correctly.\n   *\/\n  .vectors _boot_address : ALIGN(4) {\n    KEEP(*(.vectors))\n  } > rom\n\n  \/**\n   * C runtime (CRT) section, containing program initialization code.\n   *\/\n  .crt : ALIGN(4) {\n    KEEP(*(.crt))\n  } > rom\n\n  \/**\n   * Standard text section, containing program code.\n   *\/\n  .text : ALIGN(4) {\n    *(.text)\n    *(.text.*)\n  } > rom\n\n  \/**\n   * Read-only data section, containing all large compile-time constants, like\n   * strings.\n   *\/\n  .rodata : ALIGN(4) {\n    \/* Small read-only data comes before regular read-only data for the same\n     * reasons as in the data section *\/\n    *(.srodata)\n    *(.srodata.*)\n    *(.rodata)\n    *(.rodata.*)\n  } > rom\n\n  \/**\n   * \"Intitial data\" section, the initial values of the mutable data section\n   * initialized at runtime.\n   *\/\n  .idata : ALIGN(4) {\n    _data_init_start = .;\n  } > rom\n\n  \/**\n   * Standard mutable data section, at the bottom of RAM. This will be\n   * initialized from the .idata section at runtime by the CRT.\n   *\/\n  .data ORIGIN(ram_main): AT(_data_init_start) ALIGN(4) {\n    _data_start = .;\n    __global_pointer$ = . + 2048;\n\n    \/* Small data should come before larger data. This helps to ensure small\n     * globals are within 2048 bytes of the value of `gp`, making their accesses\n     * hopefully only take one instruction. *\/\n    *(.sdata)\n    *(.sdata.*)\n\n    \/* Other data will likely need multiple instructions to load, so we're less\n     * concerned about address materialisation taking more than one instruction.\n     *\/\n    *(.data)\n    *(.data.*)\n    . = ALIGN(4);\n    _data_end = .;\n  } > ram_main\n\n  \/**\n   * Immutable chip_info data, containing build-time-recorded information.\n   *\/\n  .chip_info _chip_info_start : ALIGN(4) {\n    *(.chip_info)\n  } > rom\n\n  \/**\n   * Standard BSS section. This will be zeroed at runtime by the CRT.\n   *\/\n  .bss : ALIGN(4) {\n    _bss_start = .;\n    \/* Small BSS comes before regular BSS for the same reasons as in the data\n     * section *\/\n    *(.sbss)\n    *(.sbss.*)\n    *(.bss)\n    *(.bss.*)\n    . = ALIGN(4);\n    _bss_end = .;\n  } > ram_main\n\n  INCLUDE sw\/device\/info_sections.ld\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"297221ba0550db511d45ff39da8078874601ef53","subject":"Define entry point to newlib's _mainCRTStartup","message":"Define entry point to newlib's _mainCRTStartup\n","repos":"simark\/qemu-arm-stuff,simark\/qemu-arm-stuff","old_file":"test.ld","new_file":"test.ld","new_contents":"MEMORY\n{\n  SDRAM (XRW) : ORIGIN = 0x00000000, LENGTH = 0x08000000\n  FLASH (xr)  : ORIGIN = 0x34000000, LENGTH = 0x04000000\n  SRAM (xrw)  : ORIGIN = 0x38000000, LENGTH = 0x04000000\n}\n\n\/* Define this so we can read flash in our program. *\/\nflash_start = ORIGIN(FLASH);\n\n\/* Define heap size, used lower in this file. *\/\nheap_size = 0x10000;\n\n\/* Define stack base, used in newlib's crt0.S. *\/\n__stack = ORIGIN(SDRAM) + LENGTH(SDRAM);\n\nENTRY(_mainCRTStartup);\n\nSECTIONS\n{\n  \/* QEMU has starts executing at 0x10000... *\/\n  . = 0x10000;\n\n  .text : {\n    *(.text)\n    *(.text.*)\n  } > SDRAM\n  \n  .data : {\n    *(.data)\n    *(.data.*)\n  } > SDRAM\n\n  .bss : {\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    __bss_end__ = .;\n  } > SDRAM\n\n  .heap : {\n    \/* Define \"end\" symbol (the end of interesting stuff) for the _sbrk\n       implementation from libgloss. *\/\n    end = .;\n\n    heap_start = .;\n    . = . + heap_size;\n    heap_end = .;\n  } > SDRAM\n}\n","old_contents":"MEMORY\n{\n  SDRAM (XRW) : ORIGIN = 0x00000000, LENGTH = 0x08000000\n  FLASH (xr)  : ORIGIN = 0x34000000, LENGTH = 0x04000000\n  SRAM (xrw)  : ORIGIN = 0x38000000, LENGTH = 0x04000000\n}\n\n\/* Define this so we can read flash in our program. *\/\nflash_start = ORIGIN(FLASH);\n\n\/* Define heap size, used lower in this file. *\/\nheap_size = 0x10000;\n\n\/* Define stack base, used in newlib's crt0.S. *\/\n__stack = ORIGIN(SDRAM) + LENGTH(SDRAM);\n\nSECTIONS\n{\n  \/* QEMU has starts executing at 0x10000... *\/\n  . = 0x10000;\n\n  .text : {\n    *(.text)\n    *(.text.*)\n  } > SDRAM\n  \n  .data : {\n    *(.data)\n    *(.data.*)\n  } > SDRAM\n\n  .bss : {\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    __bss_end__ = .;\n  } > SDRAM\n\n  .heap : {\n    \/* Define \"end\" symbol (the end of interesting stuff) for the _sbrk\n       implementation from libgloss. *\/\n    end = .;\n\n    heap_start = .;\n    . = . + heap_size;\n    heap_end = .;\n  } > SDRAM\n}\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"999e6d4e8f9035f8de54410a8e037ec7ada3e917","subject":"freertos: move panic handler data to DRAM","message":"freertos: move panic handler data to DRAM\n\nFixes https:\/\/ezredmine.espressif.com\/issues\/7817\n","repos":"empoweredhomes\/esp-idf,hwmaier\/esp-idf,espressif\/esp-idf,MIhanguangyi\/esp-idf,espressif\/esp-idf,empoweredhomes\/esp-idf,armada-ai\/esp-idf,www220\/esp-idf,icamgo\/esp-idf,jaracil\/esp-idf,Hermiedapwdrman\/esp-idf,armada-ai\/esp-idf,CliffsDover\/esp-idf,mashaoze\/esp-idf,ajs124\/esp-idf,hwmaier\/esp-idf,jaracil\/esp-idf,dschaefer\/esp-idf,Hermiedapwdrman\/esp-idf,MIhanguangyi\/esp-idf,jaracil\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,jaracil\/esp-idf,icamgo\/esp-idf,wmpluto\/esp-idf,shukyisme\/esp-idf-kwik,ajs124\/esp-idf,dschaefer\/esp-idf,tidyjiang8\/esp-idf-zh,tidyjiang8\/esp-idf-zh,dschaefer\/esp-idf,CliffsDover\/esp-idf,daiyinger\/esp-idf,MIhanguangyi\/esp-idf,tidyjiang8\/esp-idf-zh,mashaoze\/esp-idf,dschaefer\/esp-idf,dschaefer\/esp-idf,www220\/esp-idf,daiyinger\/esp-idf,CliffsDover\/esp-idf,espressif\/esp-idf,Hermiedapwdrman\/esp-idf,wmpluto\/esp-idf,shukyisme\/esp-idf-kwik,empoweredhomes\/esp-idf,MIhanguangyi\/esp-idf,hwmaier\/esp-idf,wmpluto\/esp-idf,icamgo\/esp-idf,daiyinger\/esp-idf,nineisk\/esp-idf,icamgo\/esp-idf,shukyisme\/esp-idf-kwik,daiyinger\/esp-idf,shukyisme\/esp-idf-kwik,hwmaier\/esp-idf,shukyisme\/esp-idf-kwik,dantonets\/Pingzee-ESP32,dantonets\/Pingzee-ESP32,dantonets\/Pingzee-ESP32,wmpluto\/esp-idf,tidyjiang8\/esp-idf-zh,ajs124\/esp-idf,empoweredhomes\/esp-idf,dantonets\/Pingzee-ESP32,espressif\/esp-idf,CliffsDover\/esp-idf,Hermiedapwdrman\/esp-idf,mashaoze\/esp-idf,nineisk\/esp-idf,MIhanguangyi\/esp-idf,nineisk\/esp-idf,nineisk\/esp-idf,ajs124\/esp-idf,empoweredhomes\/esp-idf,Hermiedapwdrman\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf,armada-ai\/esp-idf,tidyjiang8\/esp-idf-zh","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : \n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    KEEP(*(.bss))\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libfreertos.a:panic.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n  } >rtc_iram_seg\n\n  .rtc.data :\n  {\n    *(.rtc.data)\n    *(.rtc.rodata)\n  } > rtc_slow_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : \n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libpp.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    KEEP(*(.bss))\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram0_2_seg\n\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n  } >rtc_iram_seg\n\n  .rtc.data :\n  {\n    *(.rtc.data)\n    *(.rtc.rodata)\n  } > rtc_slow_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"787e04c6f8e6ccdeb8d1035efbcac9730be3e1b4","subject":".noinit section added to linker scripts","message":".noinit section added to linker scripts","repos":"gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins","old_file":"ilg.gnuarmeclipse.templates.stm\/templates\/ldscripts\/sections.ld","new_file":"ilg.gnuarmeclipse.templates.stm\/templates\/ldscripts\/sections.ld","new_contents":"\/*\n * Default linker script for STM32Fxxx.\n *\/\n\n\/*\n * The '__stack' definition is required by crt0, do not remove it.\n *\/\n__stack = ORIGIN(RAM) + LENGTH(RAM);\n\n_estack = __stack; \t\/* STM specific definition *\/\n\n\/*\n * Default stack sizes.\n * These are used by the startup in order to allocate stacks \n * for the different modes.\n *\/\n\n__Stack_Size = 1024 ;\n\nPROVIDE ( _Stack_Size = __Stack_Size ) ;\n\n__Stack_Init = __stack  - __Stack_Size ;\n\n\/*\"PROVIDE\" allows to easily override these values from an object file or the command line. *\/\nPROVIDE ( _Stack_Init = __Stack_Init ) ;\n\n\/*\n * There will be a link error if there is not this amount of \n * RAM free at the end. \n *\/\n_Minimum_Stack_Size = 0x100 ;\n\n\n\/* \n * The entry point is informative, for debuggers and simulators,\n * since the Cortex-M vector points to it anyway.\n *\/\nENTRY(Reset_Handler)\n\n\n\/* Sections Definitions *\/\n\nSECTIONS\n{\n    \/*\n     * For Cortex-M devices, the beginning of the startup code is stored in\n     * the .isr_vector section, which goes to FLASH \n     *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))     \t\/* Interrupt vectors *\/\n        \n        \/* \n         * This section is here for convenience, to store the\n         * startup code at the beginning of the flash area, hoping that\n         * this will increase the readbility of the listing.\n         *\/\n        *(.after_vectors .after_vectors.*)\t\/* Startup code and ISR *\/\n\n        . = ALIGN(4);\n    } >FLASH\n\n    ._inits :\n    {\n        . = ALIGN(4);\n        \n        \/*\n         * These are the old initialisation sections, intended to contain\n         * naked code, with the prologue\/epilogue added by crti.o\/crtn.o\n         * when linking with startup files. The standalone startup code\n         * currently does not run these, better use the init arrays below.\n         *\/\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The preinit code, i.e. an array of pointers to initialisation \n         * functions to be performed before constructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n        \n        \/*\n         * Used to run the SystemInit() before anything else.\n         *\/\n\t\tKEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))\n        \n        \/* \n         * Used for other platform inits.\n         *\/\n\t\tKEEP(*(.preinit_array_platform .preinit_array_platform.*))\n        \n        \/*\n         * The application inits. If you need to enforce some order in \n         * execution, create new sections, as before.\n         *\/\n\t\tKEEP(*(.preinit_array .preinit_array.*))\n\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The init code, i.e. an array of pointers to static constructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The fini code, i.e. an array of pointers to static destructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n        . = ALIGN(4);\n\n    } >FLASH\n\n    \/*\n     * For some STRx devices, the beginning of the startup code\n     * is stored in the .flashtext section, which goes to FLASH.\n     *\/\n    .flashtext :\n    {\n        . = ALIGN(4);\n        *(.flashtext .flashtext.*)\t\/* Startup code *\/\n        . = ALIGN(4);\n    } >FLASH\n \n    \n    \/*\n     * The program code is stored in the .text section, \n     * which goes to FLASH.\n     *\/\n    .text :\n    {\n        . = ALIGN(4);\n\t    \n        *(.text .text.*)\t\t\t\/* all remaining code *\/\n \n        *(.rodata .rodata.*) \t\t\/* read-only data (constants) *\/\n\n\t\tKEEP(*(.eh_frame*))\n\n        *(.glue_7)\n        *(.glue_7t)\n\n    } >FLASH\n\n\t\/* ARM magic sections *\/\n\t.ARM.extab :\n   \t{\n       *(.ARM.extab* .gnu.linkonce.armextab.*)\n   \t} > FLASH\n   \t\n   \t__exidx_start = .;   \t\n   \t.ARM.exidx :\n   \t{\n       *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n   \t} > FLASH\n   \t__exidx_end = .;\n   \t\n    . = ALIGN(4);\n    _etext = .;\n\n\t\/* \n     * This address is used by the startup code to \n     * initialise the .data section.\n     *\/\n    _sidata = _etext;\n    \n    \/* MEMORY_ARRAY *\/\n    .ROarraySection :\n    {\n     \t*(.ROarraySection .ROarraySection.*)                          \n    } >MEMORY_ARRAY\n     \n\n    \/*\n     * The initialised data section.\n     * The program executes knowing that the data is in the RAM\n     * but the loader puts the initial values in the FLASH (inidata).\n     * It is one task of the startup to copy the initial values from \n     * FLASH to RAM.\n     *\/\n    .data  : AT ( _sidata )\n    {\n\t    . = ALIGN(4);\n\n        \/* This is used by the startup code to initialise the .data section *\/\n        _sdata = . ;        \t\/* STM specific definition *\/\n        __data_start__ = . ;\n\n        *(vtable)\n\n        *(.data .data.*)\n\n\t    . = ALIGN(4);\n\n\t    \/* This is used by the startup code to initialise the .data section *\/\n        _edata = . ;        \t\/* STM specific definition *\/\n        __data_end__ = . ;\n\n    } >RAM\n    \n    \n\n    \/*\n     * The uninitialised data section.\n     *\/\n    .bss :\n    {\n\t    . = ALIGN(4);\n        __bss_start__ = .;     \t\/* standard newlib definition *\/\n        _sbss = .;              \/* STM specific definition *\/\n\n        *(.bss .bss.*)\n        *(COMMON)\n        \n\t    . = ALIGN(4);\n        __bss_end__ = .;        \/* standard newlib definition *\/\n        _ebss = . ;             \/* STM specific definition *\/\n    } >RAM\n    \n    .noinit (NOLOAD):\n    {\n\t    . = ALIGN(4);\n        _noinit = .;\n        \n        *(.noinit .noinit.*) \n        \n         . = ALIGN(4) ;\n        _end_noinit = .;   \n    } > RAM\n    \n    PROVIDE ( end = _end_noinit ); \/* was _ebss *\/\n    PROVIDE ( _end = end );\n    \n    \/*\n     * The user stack section.\n     * This is just to check that there is enough RAM left for the User\n     *  mode stack. It should generate an error if it's full.\n     *\/\n    ._usrstack :\n    {\n\t    . = ALIGN(4);\n        _susrstack = . ;\n        \n        . = . + _Minimum_Stack_Size ;\n        \n\t    . = ALIGN(4);\n        _eusrstack = . ;\n    } >RAM\n    \n\t.bss_CCMRAM : ALIGN(4)\n\t{\n\t\t*(.bss.CCMRAM .bss.CCMRAM.*)\n\t} > CCMRAM\n   \n    \/*\n     * The FLASH Bank1.\n     * The C or assembly source must explicitly place the code \n     * or data there using the \"section\" attribute.\n     *\/\n    .b1text :\n    {\n        *(.b1text)                   \/* remaining code *\/\n        *(.b1rodata)                 \/* read-only data (constants) *\/\n        *(.b1rodata.*)\n    } >FLASHB1\n    \n    \/*\n     * The EXTMEM.\n     * The C or assembly source must explicitly place the code or data there\n     * using the \"section\" attribute.\n     *\/\n\n    \/* EXTMEM Bank0 *\/\n    .eb0text :\n    {\n        *(.eb0text)                   \/* remaining code *\/\n        *(.eb0rodata)                 \/* read-only data (constants) *\/\n        *(.eb0rodata.*)\n    } >EXTMEMB0\n    \n    \/* EXTMEM Bank1 *\/\n    .eb1text :\n    {\n        *(.eb1text)                   \/* remaining code *\/\n        *(.eb1rodata)                 \/* read-only data (constants) *\/\n        *(.eb1rodata.*)\n    } >EXTMEMB1\n    \n    \/* EXTMEM Bank2 *\/\n    .eb2text :\n    {\n        *(.eb2text)                   \/* remaining code *\/\n        *(.eb2rodata)                 \/* read-only data (constants) *\/\n        *(.eb2rodata.*)\n    } >EXTMEMB2\n    \n    \/* EXTMEM Bank0 *\/\n    .eb3text :\n    {\n        *(.eb3text)                   \/* remaining code *\/\n        *(.eb3rodata)                 \/* read-only data (constants) *\/\n        *(.eb3rodata.*)\n    } >EXTMEMB3\n   \n\n    \n    \/* After that there are only debugging sections. *\/\n    \n    \/* This removes the debugging information from the standard libraries *\/\n    DISCARD :\n    {\n     libc.a ( * )\n     libm.a ( * )\n     libgcc.a ( * )\n     }\n  \n  \n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n       Symbols in the DWARF debugging sections are relative to the beginning\n       of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }    \n}\n","old_contents":"\/*\n * Default linker script for STM32Fxxx.\n *\/\n\n\/*\n * The '__stack' definition is required by crt0, do not remove it.\n *\/\n__stack = ORIGIN(RAM) + LENGTH(RAM);\n\n_estack = __stack; \t\/* STM specific definition *\/\n\n\/*\n * Default stack sizes.\n * These are used by the startup in order to allocate stacks \n * for the different modes.\n *\/\n\n__Stack_Size = 1024 ;\n\nPROVIDE ( _Stack_Size = __Stack_Size ) ;\n\n__Stack_Init = __stack  - __Stack_Size ;\n\n\/*\"PROVIDE\" allows to easily override these values from an object file or the command line. *\/\nPROVIDE ( _Stack_Init = __Stack_Init ) ;\n\n\/*\n * There will be a link error if there is not this amount of \n * RAM free at the end. \n *\/\n_Minimum_Stack_Size = 0x100 ;\n\n\n\/* \n * The entry point is informative, for debuggers and simulators,\n * since the Cortex-M vector points to it anyway.\n *\/\nENTRY(Reset_Handler)\n\n\n\/* Sections Definitions *\/\n\nSECTIONS\n{\n    \/*\n     * For Cortex-M devices, the beginning of the startup code is stored in\n     * the .isr_vector section, which goes to FLASH \n     *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))     \t\/* Interrupt vectors *\/\n        \n        \/* \n         * This section is here for convenience, to store the\n         * startup code at the beginning of the flash area, hoping that\n         * this will increase the readbility of the listing.\n         *\/\n        *(.after_vectors .after_vectors.*)\t\/* Startup code and ISR *\/\n\n        . = ALIGN(4);\n    } >FLASH\n\n    ._inits :\n    {\n        . = ALIGN(4);\n        \n        \/*\n         * These are the old initialisation sections, intended to contain\n         * naked code, with the prologue\/epilogue added by crti.o\/crtn.o\n         * when linking with startup files. The standalone startup code\n         * currently does not run these, better use the init arrays below.\n         *\/\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The preinit code, i.e. an array of pointers to initialisation \n         * functions to be performed before constructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n        \n        \/*\n         * Used to run the SystemInit() before anything else.\n         *\/\n\t\tKEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))\n        \n        \/* \n         * Used for other platform inits.\n         *\/\n\t\tKEEP(*(.preinit_array_platform .preinit_array_platform.*))\n        \n        \/*\n         * The application inits. If you need to enforce some order in \n         * execution, create new sections, as before.\n         *\/\n\t\tKEEP(*(.preinit_array .preinit_array.*))\n\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The init code, i.e. an array of pointers to static constructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\n\t\t\/*\n         * The fini code, i.e. an array of pointers to static destructors.\n         *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n        . = ALIGN(4);\n\n    } >FLASH\n\n    \/*\n     * For some STRx devices, the beginning of the startup code\n     * is stored in the .flashtext section, which goes to FLASH.\n     *\/\n    .flashtext :\n    {\n        . = ALIGN(4);\n        *(.flashtext .flashtext.*)\t\/* Startup code *\/\n        . = ALIGN(4);\n    } >FLASH\n \n    \n    \/*\n     * The program code is stored in the .text section, \n     * which goes to FLASH.\n     *\/\n    .text :\n    {\n        . = ALIGN(4);\n\t    \n        *(.text .text.*)\t\t\t\/* all remaining code *\/\n \n        *(.rodata .rodata.*) \t\t\/* read-only data (constants) *\/\n\n\t\tKEEP(*(.eh_frame*))\n\n        *(.glue_7)\n        *(.glue_7t)\n\n    } >FLASH\n\n\t\/* ARM magic sections *\/\n\t.ARM.extab :\n   \t{\n       *(.ARM.extab* .gnu.linkonce.armextab.*)\n   \t} > FLASH\n   \t\n   \t__exidx_start = .;   \t\n   \t.ARM.exidx :\n   \t{\n       *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n   \t} > FLASH\n   \t__exidx_end = .;\n   \t\n    . = ALIGN(4);\n    _etext = .;\n\n\t\/* \n     * This address is used by the startup code to \n     * initialise the .data section.\n     *\/\n    _sidata = _etext;\n    \n    \/* MEMORY_ARRAY *\/\n    .ROarraySection :\n    {\n     \t*(.ROarraySection .ROarraySection.*)                          \n    } >MEMORY_ARRAY\n     \n\n    \/*\n     * The initialised data section.\n     * The program executes knowing that the data is in the RAM\n     * but the loader puts the initial values in the FLASH (inidata).\n     * It is one task of the startup to copy the initial values from \n     * FLASH to RAM.\n     *\/\n    .data  : AT ( _sidata )\n    {\n\t    . = ALIGN(4);\n\n        \/* This is used by the startup code to initialise the .data section *\/\n        _sdata = . ;        \t\/* STM specific definition *\/\n        __data_start__ = . ;\n\n        *(vtable)\n\n        *(.data .data.*)\n\n\t    . = ALIGN(4);\n\n\t    \/* This is used by the startup code to initialise the .data section *\/\n        _edata = . ;        \t\/* STM specific definition *\/\n        __data_end__ = . ;\n\n    } >RAM\n    \n    \n\n    \/*\n     * The uninitialised data section.\n     *\/\n    .bss :\n    {\n\t    . = ALIGN(4);\n        __bss_start__ = .;     \t\/* standard newlib definition *\/\n        _sbss = .;              \/* STM specific definition *\/\n\n        *(.bss .bss.*)\n        *(COMMON)\n        \n\t    . = ALIGN(4);\n        __bss_end__ = .;        \/* standard newlib definition *\/\n        _ebss = . ;             \/* STM specific definition *\/\n    } >RAM\n    \n    PROVIDE ( end = _ebss );\n    PROVIDE ( _end = _ebss );\n    \n    \/*\n     * The user stack section.\n     * This is just to check that there is enough RAM left for the User\n     *  mode stack. It should generate an error if it's full.\n     *\/\n    ._usrstack :\n    {\n\t    . = ALIGN(4);\n        _susrstack = . ;\n        \n        . = . + _Minimum_Stack_Size ;\n        \n\t    . = ALIGN(4);\n        _eusrstack = . ;\n    } >RAM\n    \n\t.bss_CCMRAM : ALIGN(4)\n\t{\n\t\t*(.bss.CCMRAM .bss.CCMRAM.*)\n\t} > CCMRAM\n   \n    \/*\n     * The FLASH Bank1.\n     * The C or assembly source must explicitly place the code \n     * or data there using the \"section\" attribute.\n     *\/\n    .b1text :\n    {\n        *(.b1text)                   \/* remaining code *\/\n        *(.b1rodata)                 \/* read-only data (constants) *\/\n        *(.b1rodata.*)\n    } >FLASHB1\n    \n    \/*\n     * The EXTMEM.\n     * The C or assembly source must explicitly place the code or data there\n     * using the \"section\" attribute.\n     *\/\n\n    \/* EXTMEM Bank0 *\/\n    .eb0text :\n    {\n        *(.eb0text)                   \/* remaining code *\/\n        *(.eb0rodata)                 \/* read-only data (constants) *\/\n        *(.eb0rodata.*)\n    } >EXTMEMB0\n    \n    \/* EXTMEM Bank1 *\/\n    .eb1text :\n    {\n        *(.eb1text)                   \/* remaining code *\/\n        *(.eb1rodata)                 \/* read-only data (constants) *\/\n        *(.eb1rodata.*)\n    } >EXTMEMB1\n    \n    \/* EXTMEM Bank2 *\/\n    .eb2text :\n    {\n        *(.eb2text)                   \/* remaining code *\/\n        *(.eb2rodata)                 \/* read-only data (constants) *\/\n        *(.eb2rodata.*)\n    } >EXTMEMB2\n    \n    \/* EXTMEM Bank0 *\/\n    .eb3text :\n    {\n        *(.eb3text)                   \/* remaining code *\/\n        *(.eb3rodata)                 \/* read-only data (constants) *\/\n        *(.eb3rodata.*)\n    } >EXTMEMB3\n   \n\n    \n    \/* After that there are only debugging sections. *\/\n    \n    \/* This removes the debugging information from the standard libraries *\/\n    DISCARD :\n    {\n     libc.a ( * )\n     libm.a ( * )\n     libgcc.a ( * )\n     }\n  \n  \n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n       Symbols in the DWARF debugging sections are relative to the beginning\n       of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }    \n}\n","returncode":0,"stderr":"","license":"epl-1.0","lang":"Linker Script"}
{"commit":"b7a72220ea304c5274d7c0794229342fde5d4b43","subject":"trivial: fix comment style","message":"trivial: fix comment style\n\nChange-Id: Iaa1b27f2ac5a01598a044303ba45881ce45b2f4f\nSigned-off-by: Anas Nashif <0d9952ec84ac43c159f6b7e7ed99a9080c00dd6e@intel.com>\n","repos":"fbsder\/zephyr,holtmann\/zephyr,mirzak\/zephyr-os,zephyriot\/zephyr,finikorg\/zephyr,mbolivar\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,ldts\/zephyr,galak\/zephyr,tidyjiang8\/zephyr-doc,fbsder\/zephyr,tidyjiang8\/zephyr-doc,kraj\/zephyr,bboozzoo\/zephyr,runchip\/zephyr-cc3200,ldts\/zephyr,nashif\/zephyr,fbsder\/zephyr,mbolivar\/zephyr,mbolivar\/zephyr,punitvara\/zephyr,punitvara\/zephyr,kraj\/zephyr,finikorg\/zephyr,bigdinotech\/zephyr,tidyjiang8\/zephyr-doc,runchip\/zephyr-cc3200,rsalveti\/zephyr,aceofall\/zephyr-iotos,erwango\/zephyr,zephyriot\/zephyr,finikorg\/zephyr,mirzak\/zephyr-os,runchip\/zephyr-cc3220,fractalclone\/zephyr-riscv,zephyriot\/zephyr,GiulianoFranchetto\/zephyr,rsalveti\/zephyr,zephyriot\/zephyr,bboozzoo\/zephyr,ldts\/zephyr,mirzak\/zephyr-os,tidyjiang8\/zephyr-doc,GiulianoFranchetto\/zephyr,sharronliu\/zephyr,nashif\/zephyr,punitvara\/zephyr,erwango\/zephyr,pklazy\/zephyr,zephyrproject-rtos\/zephyr,runchip\/zephyr-cc3200,punitvara\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,holtmann\/zephyr,bboozzoo\/zephyr,runchip\/zephyr-cc3200,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,fbsder\/zephyr,sharronliu\/zephyr,runchip\/zephyr-cc3200,galak\/zephyr,mbolivar\/zephyr,zephyriot\/zephyr,fractalclone\/zephyr-riscv,galak\/zephyr,explora26\/zephyr,pklazy\/zephyr,runchip\/zephyr-cc3220,erwango\/zephyr,bboozzoo\/zephyr,holtmann\/zephyr,explora26\/zephyr,sharronliu\/zephyr,mbolivar\/zephyr,nashif\/zephyr,Vudentz\/zephyr,bboozzoo\/zephyr,galak\/zephyr,ldts\/zephyr,pklazy\/zephyr,GiulianoFranchetto\/zephyr,bigdinotech\/zephyr,kraj\/zephyr,Vudentz\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,pklazy\/zephyr,erwango\/zephyr,ldts\/zephyr,mirzak\/zephyr-os,Vudentz\/zephyr,finikorg\/zephyr,tidyjiang8\/zephyr-doc,erwango\/zephyr,fbsder\/zephyr,aceofall\/zephyr-iotos,holtmann\/zephyr,mirzak\/zephyr-os,runchip\/zephyr-cc3220,fractalclone\/zephyr-riscv,sharronliu\/zephyr,sharronliu\/zephyr,rsalveti\/zephyr,rsalveti\/zephyr,bigdinotech\/zephyr,punitvara\/zephyr,bigdinotech\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,bigdinotech\/zephyr,aceofall\/zephyr-iotos,fractalclone\/zephyr-riscv,pklazy\/zephyr,runchip\/zephyr-cc3220,runchip\/zephyr-cc3220,fractalclone\/zephyr-riscv,holtmann\/zephyr,kraj\/zephyr,aceofall\/zephyr-iotos,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,rsalveti\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/arc\/v2\/linker.ld","new_file":"include\/arch\/arc\/v2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#if defined(CONFIG_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nMEMORY {\n\tFLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n\tDCCM  (rw) : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n}\n\nSECTIONS {\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\n\n\t\tKEEP(*(.irq_vector_table))\n\t\tKEEP(*(\".irq_vector_table.*\"))\n\n#ifdef CONFIG_VERSION_HEADER\n\t\t*(.version_header)\n\t\tKEEP(*(\".version_header*\"))\n#endif\n#ifndef CONFIG_SW_ISR_TABLE_DYNAMIC\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*\n\t\t * The following sections maps the location of the different\n\t\t * rows for the _sw_isr_table. Each row maps to an IRQ entry\n\t\t * (handler, argument).\n\t\t *\n\t\t * In ARC architecture, IRQ 0-15 are reserved for the system\n\t\t * and are not * assignable by the user, for that reason the\n\t\t * linker sections start on IRQ 16\n\t\t *\/\n\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n#endif\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n\t\t_image_text_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE (devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(gpio_compat, (OPTIONAL),)\n\t{\n\t\t__gpio_compat_start = .;\n\t\t*(\".gpio_compat.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".gpio_compat*\")))\n\t\t__gpio_compat_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,) {\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below, hence\n\t\t * symbol __CTOR_LIST__ must be aligned on 4 byte boundary.\n\t\t * To align with the C++ standard, the first element of the array\n\t\t * contains the number of actual constructors. The last element is\n\t\t * NULL.\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\/* XIP imaged DATA ROM start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n\tSECTION_AT_PROLOGUE(_DATA_SECTION_NAME,,,_DATA_IN_ROM) {\n#else\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,) {\n#endif\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t\t_image_ram_start = .;\n\t\t__data_ram_start = .;\n\t\t*(.data)\n\t\t*(\".data.*\")\n\n#if CONFIG_SW_ISR_TABLE_DYNAMIC\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*The following sections maps the location of the different rows for\n\t\tthe _sw_isr_table. Each row maps to an IRQ entry (handler, argument).*\/\n\t\t\/*In ARC architecture, IRQ 0-15 are reserved for the system and are not\n\t\tassignable by the user, for that reason the linker sections start\n\t\ton IRQ 16*\/\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n#endif\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(\".bss.*\")\n\t\tCOMMON_SYMBOLS\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t*(.noinit)\n\t\t*(\".noinit.*\")\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\t__bss_num_words = (__bss_end - __bss_start) >> 2;\n\n\tGROUP_END(RAMABLE_REGION)\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\tGROUP_START(DCCM)\n\tGROUP_END(DCCM)\n\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n\n#endif\n","old_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#if defined(CONFIG_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nMEMORY {\n\tFLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n\tDCCM  (rw) : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n}\n\nSECTIONS {\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\n\n\t\tKEEP(*(.irq_vector_table))\n\t\tKEEP(*(\".irq_vector_table.*\"))\n\n#ifdef CONFIG_VERSION_HEADER\n\t\t*(.version_header)\n\t\tKEEP(*(\".version_header*\"))\n#endif\n#ifndef CONFIG_SW_ISR_TABLE_DYNAMIC\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*The following sections maps the location of the different rows for\n\t\tthe _sw_isr_table. Each row maps to an IRQ entry (handler, argument).*\/\n\t\t\/*In ARC architecture, IRQ 0-15 are reserved for the system and are not\n\t\tassignable by the user, for that reason the linker sections start\n\t\ton IRQ 16*\/\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n#endif\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n\t\t_image_text_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE (devconfig, (OPTIONAL),)\n\t{\n\t\t__devconfig_start = .;\n\t\t*(\".devconfig.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".devconfig*\")))\n\t\t__devconfig_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(gpio_compat, (OPTIONAL),)\n\t{\n\t\t__gpio_compat_start = .;\n\t\t*(\".gpio_compat.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".gpio_compat*\")))\n\t\t__gpio_compat_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CPLUSPLUS\n\tSECTION_PROLOGUE(_CTOR_SECTION_NAME,,) {\n\t\t\/*\n\t\t * The compiler fills the constructor pointers table below, hence\n\t\t * symbol __CTOR_LIST__ must be aligned on 4 byte boundary.\n\t\t * To align with the C++ standard, the first element of the array\n\t\t * contains the number of actual constructors. The last element is\n\t\t * NULL.\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__CTOR_LIST__ = .;\n\t\tLONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n\t\tKEEP(*(SORT_BY_NAME(\".ctors*\")))\n\t\tLONG(0)\n\t\t__CTOR_END__ = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(init_array, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\".init_array*\")))\n\t\t__init_array_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\/* XIP imaged DATA ROM start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n\tSECTION_AT_PROLOGUE(_DATA_SECTION_NAME,,,_DATA_IN_ROM) {\n#else\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,) {\n#endif\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t\t_image_ram_start = .;\n\t\t__data_ram_start = .;\n\t\t*(.data)\n\t\t*(\".data.*\")\n\n#if CONFIG_SW_ISR_TABLE_DYNAMIC\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*The following sections maps the location of the different rows for\n\t\tthe _sw_isr_table. Each row maps to an IRQ entry (handler, argument).*\/\n\t\t\/*In ARC architecture, IRQ 0-15 are reserved for the system and are not\n\t\tassignable by the user, for that reason the linker sections start\n\t\ton IRQ 16*\/\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n#endif\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(\".bss.*\")\n\t\tCOMMON_SYMBOLS\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t*(.noinit)\n\t\t*(\".noinit.*\")\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\t__bss_num_words = (__bss_end - __bss_start) >> 2;\n\n\tGROUP_END(RAMABLE_REGION)\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\tGROUP_START(DCCM)\n\tGROUP_END(DCCM)\n\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a06d38af5a16156bce33443bb0c166a8493da26c","subject":"arc: ICCM memory should have read-write-execute attributes","message":"arc: ICCM memory should have read-write-execute attributes\n\nThe ICCM memory, when present, can be both written and read,\nso changing the attributes to be read-write-execute.\n\nChange-Id: I432bd36f4a6ef632b7c4ce3bf8aa138895d52642\nSigned-off-by: Chuck Jordan <c464ed312fa6f818297227c7e5018fc9f4bd95ad@synopsys.com>\n","repos":"runchip\/zephyr-cc3220,holtmann\/zephyr,erwango\/zephyr,ldts\/zephyr,fractalclone\/zephyr-riscv,bboozzoo\/zephyr,tidyjiang8\/zephyr-doc,kraj\/zephyr,galak\/zephyr,mbolivar\/zephyr,aceofall\/zephyr-iotos,mbolivar\/zephyr,ldts\/zephyr,galak\/zephyr,punitvara\/zephyr,fbsder\/zephyr,bboozzoo\/zephyr,rsalveti\/zephyr,finikorg\/zephyr,runchip\/zephyr-cc3200,explora26\/zephyr,runchip\/zephyr-cc3200,bboozzoo\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,sharronliu\/zephyr,fbsder\/zephyr,punitvara\/zephyr,erwango\/zephyr,bigdinotech\/zephyr,tidyjiang8\/zephyr-doc,runchip\/zephyr-cc3220,runchip\/zephyr-cc3220,mbolivar\/zephyr,nashif\/zephyr,fractalclone\/zephyr-riscv,pklazy\/zephyr,aceofall\/zephyr-iotos,GiulianoFranchetto\/zephyr,fbsder\/zephyr,tidyjiang8\/zephyr-doc,rsalveti\/zephyr,pklazy\/zephyr,zephyriot\/zephyr,Vudentz\/zephyr,fractalclone\/zephyr-riscv,runchip\/zephyr-cc3220,finikorg\/zephyr,zephyriot\/zephyr,fractalclone\/zephyr-riscv,pklazy\/zephyr,nashif\/zephyr,pklazy\/zephyr,aceofall\/zephyr-iotos,zephyriot\/zephyr,GiulianoFranchetto\/zephyr,fbsder\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,sharronliu\/zephyr,runchip\/zephyr-cc3200,GiulianoFranchetto\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,kraj\/zephyr,finikorg\/zephyr,tidyjiang8\/zephyr-doc,Vudentz\/zephyr,bboozzoo\/zephyr,pklazy\/zephyr,bigdinotech\/zephyr,explora26\/zephyr,aceofall\/zephyr-iotos,zephyrproject-rtos\/zephyr,finikorg\/zephyr,kraj\/zephyr,finikorg\/zephyr,galak\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3220,rsalveti\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,holtmann\/zephyr,erwango\/zephyr,mbolivar\/zephyr,erwango\/zephyr,GiulianoFranchetto\/zephyr,bboozzoo\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,runchip\/zephyr-cc3200,bigdinotech\/zephyr,explora26\/zephyr,explora26\/zephyr,punitvara\/zephyr,erwango\/zephyr,ldts\/zephyr,sharronliu\/zephyr,zephyriot\/zephyr,fractalclone\/zephyr-riscv,nashif\/zephyr,kraj\/zephyr,Vudentz\/zephyr,holtmann\/zephyr,rsalveti\/zephyr,aceofall\/zephyr-iotos,bigdinotech\/zephyr,tidyjiang8\/zephyr-doc,bigdinotech\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,sharronliu\/zephyr,holtmann\/zephyr,kraj\/zephyr,holtmann\/zephyr,runchip\/zephyr-cc3200,mbolivar\/zephyr,ldts\/zephyr,rsalveti\/zephyr,ldts\/zephyr,punitvara\/zephyr,sharronliu\/zephyr,nashif\/zephyr","old_file":"include\/arch\/arc\/v2\/linker.ld","new_file":"include\/arch\/arc\/v2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#if defined(CONFIG_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_HARVARD\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)\n\t\t#define ROMABLE_REGION FLASH\n\t\t#define RAMABLE_REGION SRAM\n\t#else\n\t\t#define ROMABLE_REGION SRAM\n\t\t#define RAMABLE_REGION SRAM\n\t#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(__start)\n\nMEMORY {\n#ifdef FLASH_START\n\tFLASH (rx)  : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n#endif\n#ifdef ICCM_START\n\tICCM  (rwx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n#endif\n#ifdef SRAM_START\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n#endif\n#ifdef DCCM_START\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n#endif\n}\n\nSECTIONS {\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\n\n\t\tKEEP(*(.irq_vector_table))\n\t\tKEEP(*(\".irq_vector_table.*\"))\n\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*\n\t\t * The following sections maps the location of the different\n\t\t * rows for the _sw_isr_table. Each row maps to an IRQ entry\n\t\t * (handler, argument).\n\t\t *\n\t\t * In ARC architecture, IRQ 0-15 are reserved for the system\n\t\t * and are not * assignable by the user, for that reason the\n\t\t * linker sections start on IRQ 16\n\t\t *\/\n\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n\t\t_image_text_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\/* XIP imaged DATA ROM start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t\t_image_ram_start = .;\n\t\t__data_ram_start = .;\n\t\t*(.data)\n\t\t*(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(\".bss.*\")\n\t\tCOMMON_SYMBOLS\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t*(.noinit)\n\t\t*(\".noinit.*\")\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\tGROUP_START(DCCM)\n\tGROUP_END(DCCM)\n\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n","old_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#if defined(CONFIG_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_HARVARD\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)\n\t\t#define ROMABLE_REGION FLASH\n\t\t#define RAMABLE_REGION SRAM\n\t#else\n\t\t#define ROMABLE_REGION SRAM\n\t\t#define RAMABLE_REGION SRAM\n\t#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(__start)\n\nMEMORY {\n#ifdef FLASH_START\n\tFLASH (rx)  : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n#endif\n#ifdef ICCM_START\n\tICCM  (rx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n#endif\n#ifdef SRAM_START\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n#endif\n#ifdef DCCM_START\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n#endif\n}\n\nSECTIONS {\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\n\n\t\tKEEP(*(.irq_vector_table))\n\t\tKEEP(*(\".irq_vector_table.*\"))\n\n\t\tKEEP(*(.isr_irq*))\n\n\t\t\/*\n\t\t * The following sections maps the location of the different\n\t\t * rows for the _sw_isr_table. Each row maps to an IRQ entry\n\t\t * (handler, argument).\n\t\t *\n\t\t * In ARC architecture, IRQ 0-15 are reserved for the system\n\t\t * and are not * assignable by the user, for that reason the\n\t\t * linker sections start on IRQ 16\n\t\t *\/\n\n\t\t\/* sections for IRQ16-19 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))\n\t\t\/* sections for IRQ20-99 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))\n\t\t\/* sections for IRQ100-999 *\/\n\t\tKEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n\t\t_image_text_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rom_end = .;\n\t__data_rom_start = ALIGN(4);\t\/* XIP imaged DATA ROM start addr *\/\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t\t_image_ram_start = .;\n\t\t__data_ram_start = .;\n\t\t*(.data)\n\t\t*(\".data.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\t__data_ram_end = .;\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\t\t*(.bss)\n\t\t*(\".bss.*\")\n\t\tCOMMON_SYMBOLS\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t*(.noinit)\n\t\t*(\".noinit.*\")\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\tGROUP_START(DCCM)\n\tGROUP_END(DCCM)\n\n\tSECTION_PROLOGUE(initlevel_error, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\t}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"218e2c873df4ac8aada226cd72f04b807db41767","subject":"esp32h2beta2:rename __rom_printf_float\/__rom_scanf_float","message":"esp32h2beta2:rename __rom_printf_float\/__rom_scanf_float\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32h2\/ld\/rev2\/esp32h2.rom.newlib-nano.ld","new_file":"components\/esp_rom\/esp32h2\/ld\/rev2\/esp32h2.rom.newlib-nano.ld","new_contents":"\/*\n * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\/* ROM function interface esp32h2.rom.newlib-nano.ld for esp32h2\n *\n *\n * Generated from .\/target\/esp32h2\/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6\n *\n * Compatible with ROM where ECO version equal or greater to 0.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group newlib_nano_format\n ***************************************\/\n\n\/* Functions *\/\n__sprint_r = 0x40000684;\n_fiprintf_r = 0x40000688;\n_fprintf_r = 0x4000068c;\n_printf_common = 0x40000690;\n_printf_i = 0x40000694;\n_vfiprintf_r = 0x40000698;\n_vfprintf_r = 0x4000069c;\nfiprintf = 0x400006a0;\nfprintf = 0x400006a4;\nprintf = 0x400006a8;\nvfiprintf = 0x400006ac;\nvfprintf = 0x400006b0;\nasprintf = 0x400006b4;\nsprintf = 0x400006b8;\nsnprintf = 0x400006bc;\nsiprintf = 0x400006c0;\nsniprintf = 0x400006c4;\nvprintf = 0x400006c8;\nviprintf = 0x400006cc;\nvsnprintf = 0x400006d0;\nvsniprintf = 0x400006d4;\n_printf_float = 0x400006d8;\n_scanf_float = 0x400006dc;\n_scanf_i = 0x400006e0;\n_scanf_chars = 0x400006e4;\nsscanf = 0x400006e8;\nsiscanf = 0x400006ec;\n","old_contents":"\/*\n * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\/* ROM function interface esp32h2.rom.newlib-nano.ld for esp32h2\n *\n *\n * Generated from .\/target\/esp32h2\/interface-esp32h2.yml md5sum da4c474a48c097d4ac9acad67f70fda6\n *\n * Compatible with ROM where ECO version equal or greater to 0.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group newlib_nano_format\n ***************************************\/\n\n\/* Functions *\/\n__sprint_r = 0x40000684;\n_fiprintf_r = 0x40000688;\n_fprintf_r = 0x4000068c;\n_printf_common = 0x40000690;\n_printf_i = 0x40000694;\n_vfiprintf_r = 0x40000698;\n_vfprintf_r = 0x4000069c;\nfiprintf = 0x400006a0;\nfprintf = 0x400006a4;\nprintf = 0x400006a8;\nvfiprintf = 0x400006ac;\nvfprintf = 0x400006b0;\nasprintf = 0x400006b4;\nsprintf = 0x400006b8;\nsnprintf = 0x400006bc;\nsiprintf = 0x400006c0;\nsniprintf = 0x400006c4;\nvprintf = 0x400006c8;\nviprintf = 0x400006cc;\nvsnprintf = 0x400006d0;\nvsniprintf = 0x400006d4;\n__rom_printf_float = 0x400006d8;\n__rom_scanf_float = 0x400006dc;\n_scanf_i = 0x400006e0;\n_scanf_chars = 0x400006e4;\nsscanf = 0x400006e8;\nsiscanf = 0x400006ec;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f9636d6f7ec495e547737b749a111025b26a3739","subject":"riscv32: pulpino: add some missing linker symbols","message":"riscv32: pulpino: add some missing linker symbols\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"ldts\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,nashif\/zephyr,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,rsalveti\/zephyr,galak\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,finikorg\/zephyr,kraj\/zephyr,finikorg\/zephyr,runchip\/zephyr-cc3220,mbolivar\/zephyr,aceofall\/zephyr-iotos,runchip\/zephyr-cc3220,explora26\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,runchip\/zephyr-cc3220,zephyriot\/zephyr,fbsder\/zephyr,aceofall\/zephyr-iotos,mbolivar\/zephyr,mbolivar\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,kraj\/zephyr,galak\/zephyr,aceofall\/zephyr-iotos,punitvara\/zephyr,runchip\/zephyr-cc3220,Vudentz\/zephyr,fbsder\/zephyr,Vudentz\/zephyr,aceofall\/zephyr-iotos,rsalveti\/zephyr,ldts\/zephyr,finikorg\/zephyr,punitvara\/zephyr,fbsder\/zephyr,Vudentz\/zephyr,nashif\/zephyr,ldts\/zephyr,kraj\/zephyr,zephyriot\/zephyr,nashif\/zephyr,rsalveti\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,fbsder\/zephyr,zephyriot\/zephyr,GiulianoFranchetto\/zephyr,mbolivar\/zephyr,finikorg\/zephyr,kraj\/zephyr,GiulianoFranchetto\/zephyr,rsalveti\/zephyr,fbsder\/zephyr,ldts\/zephyr,galak\/zephyr,runchip\/zephyr-cc3220,Vudentz\/zephyr,mbolivar\/zephyr,explora26\/zephyr,galak\/zephyr,kraj\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,aceofall\/zephyr-iotos,rsalveti\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/riscv32\/pulpino\/linker.ld","new_file":"include\/arch\/riscv32\/pulpino\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the pulpino platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION              DATARAM\n#define RAMABLE_REGION              DATARAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nENTRY(__reset)\n\nMEMORY\n    {\n    INSTRRAM (wx) : ORIGIN = CONFIG_ITCM_BASE_ADDRESS, LENGTH = CONFIG_ITCM_SIZE\n    DATARAM  (rw) : ORIGIN = CONFIG_DTCM_BASE_ADDRESS, LENGTH = CONFIG_DTCM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nSECTIONS\n    {\n    GROUP_START(INSTRRAM)\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(INSTRRAM)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(INSTRRAM)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(INSTRRAM)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tKEEP(*(.openocd_dbg))\n\t\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\t_image_text_start = .;\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t} GROUP_LINK_IN(INSTRRAM)\n\n    _image_text_end = .;\n\n    GROUP_END(INSTRRAM)\n\n    GROUP_START(RAMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\t\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n    _image_ram_start = .;\n\n#include <linker\/common-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t\t . = ALIGN(4);\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\t}  GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(\".noinit.*\")\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n     GROUP_END(RAMABLE_REGION)\n}\n","old_contents":"\/*\n * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the pulpino platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION              DATARAM\n#define RAMABLE_REGION              DATARAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nENTRY(__reset)\n\nMEMORY\n    {\n    INSTRRAM (wx) : ORIGIN = CONFIG_ITCM_BASE_ADDRESS, LENGTH = CONFIG_ITCM_SIZE\n    DATARAM  (rw) : ORIGIN = CONFIG_DTCM_BASE_ADDRESS, LENGTH = CONFIG_DTCM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nSECTIONS\n    {\n    GROUP_START(INSTRRAM)\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(INSTRRAM)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(INSTRRAM)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(INSTRRAM)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\n\t\tKEEP(*(.openocd_dbg))\n\t\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\t_image_text_start = .;\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t} GROUP_LINK_IN(INSTRRAM)\n\n    _image_text_end = .;\n\n    GROUP_END(INSTRRAM)\n\n    GROUP_START(RAMABLE_REGION)\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\t\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t\t . = ALIGN(4);\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\t}  GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(\".noinit.*\")\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n     _end = .; \/* end of image *\/\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n     GROUP_END(RAMABLE_REGION)\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f4d3ba87bb8f5d82d3b80532ea4c83b7bbca41c0","subject":"BaseTools\/Scripts: fix GccBase.lds line endings","message":"BaseTools\/Scripts: fix GccBase.lds line endings\n\nReplace a <LF> line ending that was introduced inadvertently by a\nrecent commit with the correct <CR><LF>\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org>\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"BaseTools\/Scripts\/GccBase.lds","new_file":"BaseTools\/Scripts\/GccBase.lds","new_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are mostly constant from the POV of the\r\n     * program, but most of it ends up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     * Unfortunately, we cannot pull it into the .text section entirely, since\r\n     * patchable PCDs are also emitted here, but we can at least move all of the\r\n     * emitted GUIDs here.\r\n     *\/\r\n    *:AutoGen.obj(.data.g*Guid)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela (INFO) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/*\r\n   * Retain the GNU build id but in a non-allocatable section so GenFw\r\n   * does not copy it into the PE\/COFF image.\r\n   *\/\r\n  .build-id (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash .gnu.hash)\r\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","old_contents":"\/** @file\r\n\r\n  Unified linker script for GCC based builds\r\n\r\n  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r\n\r\n  This program and the accompanying materials are licensed and made available under\r\n  the terms and conditions of the BSD License that accompanies this distribution.\r\n  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php.\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS {\r\n\r\n  \/*\r\n   * The PE\/COFF binary consists of DOS and PE\/COFF headers, and a sequence of\r\n   * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs\r\n   * between 32-bit and 64-bit builds). The actual start of the .text section\r\n   * will be rounded up based on its actual alignment.\r\n   *\/\r\n  . = PECOFF_HEADER_SIZE;\r\n\r\n  .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.text .text.* .stub .gnu.linkonce.t.*)\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.got .got.*)\r\n\r\n    \/*\r\n     * The contents of AutoGen.c files are mostly constant from the POV of the\r\n     * program, but most of it ends up in .data or .bss by default since few of\r\n     * the variable definitions that get emitted are declared as CONST.\r\n     * Unfortunately, we cannot pull it into the .text section entirely, since\r\n     * patchable PCDs are also emitted here, but we can at least move all of the\r\n     * emitted GUIDs here.\r\n     *\/\r\n    *:AutoGen.obj(.data.g*Guid)\r\n  }\r\n\r\n  \/*\r\n   * The alignment of the .data section should be less than or equal to the\r\n   * alignment of the .text section. This ensures that the relative offset\r\n   * between these sections is the same in the ELF and the PE\/COFF versions of\r\n   * this binary.\r\n   *\/\r\n  .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    *(.bss .bss.*)\r\n  }\r\n\r\n  .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {\r\n    KEEP (*(.eh_frame))\r\n  }\r\n\r\n  .rela (INFO) : {\r\n    *(.rela .rela.*)\r\n  }\r\n\r\n  .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    KEEP (*(.hii))\r\n  }\r\n\r\n  \/*\r\n   * Retain the GNU build id but in a non-allocatable section so GenFw\r\n   * does not copy it into the PE\/COFF image.\r\n   *\/\r\n  .build-id (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.dynamic)\r\n    *(.hash .gnu.hash)\n    *(.comment)\r\n    *(COMMON)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"24bc7ac87039ad1c1e78fbe37550c48ae6d6a82a","subject":"[x3399]0M-2M for ARM Trusted Firmware, 132M-148M for OP-TEE OS","message":"[x3399]0M-2M for ARM Trusted Firmware, 132M-148M for OP-TEE OS\n","repos":"xboot\/xboot,xboot\/xboot","old_file":"src\/arch\/arm64\/mach-x3399\/xboot.ld","new_file":"src\/arch\/arm64\/mach-x3399\/xboot.ld","new_contents":"OUTPUT_FORMAT(\"elf64-littleaarch64\", \"elf64-littleaarch64\", \"elf64-littleaarch64\")\r\nOUTPUT_ARCH(\"aarch64\")\r\nENTRY(_start)\r\n\r\nSTACK_EL3_SIZE = 0x40000;\r\nSTACK_EL2_SIZE = 0x40000;\r\nSTACK_EL1_SIZE = 0x100000;\r\nSTACK_EL0_SIZE = 0x100000;\r\n\r\nMEMORY\r\n{\r\n\tram  : org = 0x09400000, len = 108M\r\n\tdma  : org = 0x10000000, len = 256M\r\n\theap : org = 0x20000000, len = 512M\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tPROVIDE(__image_start = .);\r\n\t\tPROVIDE(__text_start = .);\r\n\t\t.obj\/arch\/arm64\/mach-x3399\/start.o (.text)\r\n\t\t.obj\/arch\/arm64\/mach-x3399\/transition.o (.text)\r\n\t\t*(.text*)\r\n\t\t*(.init.text)\r\n\t\t*(.exit.text)\r\n\t\t*(.iplt)\r\n\t\t*(.note.gnu.build-id)\r\n\t\tPROVIDE(__text_end = .);\r\n\t} > ram\r\n\r\n\t.initcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE(__initcall_end = .);\r\n\t} > ram\r\n\r\n\t.exitcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE(__exitcall_end = .);\r\n\t} > ram\r\n\r\n\t.ksymtab ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE(__ksymtab_end = .);\r\n\t} > ram\r\n\r\n\t.romdisk ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE(__romdisk_end = .);\r\n\t} > ram\r\n\r\n\t.rodata ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__rodata_start = .);\r\n\t\t*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\r\n\t\tPROVIDE(__rodata_end = .);\r\n\t} > ram\r\n\r\n\t.data_shadow ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__data_shadow_start = .);\r\n\t\tPROVIDE(__data_shadow_end = (. + SIZEOF(.data)));\r\n\t\tPROVIDE(__image_end = __data_shadow_end);\r\n\t} > ram\r\n\r\n\t.data : AT(ADDR(.data_shadow))\r\n\t{\r\n\t\tPROVIDE(__data_start = .);\t\r\n\t\t*(.data*)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE(__data_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__bss_start = .);\r\n\t\t*(.bss*)\r\n\t\t*(.sbss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__bss_end = .);\r\n\t} > ram\r\n\r\n\t.stack ALIGN(16) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__stack_start = .);\r\n\t\tPROVIDE(__stack_el3_start = .);\r\n\t\t. += STACK_EL3_SIZE;\r\n\t\tPROVIDE(__stack_el3_end = .);\r\n\t\t. = ALIGN(16);\r\n\t\tPROVIDE(__stack_el2_start = .);\r\n\t\t. += STACK_EL2_SIZE;\r\n\t\tPROVIDE(__stack_el2_end = .);\r\n\t\t. = ALIGN(16);\r\n\t\tPROVIDE(__stack_el1_start = .);\r\n\t\t. += STACK_EL1_SIZE;\r\n\t\tPROVIDE(__stack_el1_end = .);\r\n\t\t. = ALIGN(16);\t\t\r\n\t\tPROVIDE(__stack_el0_start = .);\r\n\t\t. += STACK_EL0_SIZE;\r\n\t\tPROVIDE(__stack_el0_end = .);\r\n\t\t. = ALIGN(16);\r\n\t\tPROVIDE(__stack_end = .);\r\n\t} > ram\r\n\r\n\t.dma ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__dma_start = ORIGIN(dma));\r\n\t\tPROVIDE(__dma_end = ORIGIN(dma) + LENGTH(dma));\r\n\t} > dma\r\n\r\n\t.heap ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__heap_start = ORIGIN(heap));\r\n\t\tPROVIDE(__heap_end = ORIGIN(heap) + LENGTH(heap));\r\n\t} > heap\r\n\r\n\t\/DISCARD\/ : { *(.dynsym) }\r\n\t\/DISCARD\/ : { *(.dynstr*) }\r\n\t\/DISCARD\/ : { *(.dynamic*) }\r\n\t\/DISCARD\/ : { *(.plt*) }\r\n\t\/DISCARD\/ : { *(.interp*) }\r\n\t\/DISCARD\/ : { *(.gnu*) }\r\n}\r\n","old_contents":"OUTPUT_FORMAT(\"elf64-littleaarch64\", \"elf64-littleaarch64\", \"elf64-littleaarch64\")\r\nOUTPUT_ARCH(\"aarch64\")\r\nENTRY(_start)\r\n\r\nSTACK_EL3_SIZE = 0x40000;\r\nSTACK_EL2_SIZE = 0x40000;\r\nSTACK_EL1_SIZE = 0x100000;\r\nSTACK_EL0_SIZE = 0x100000;\r\n\r\nMEMORY\r\n{\r\n\tram  : org = 0x00200000, len = 128M - 2M\r\n\tdma  : org = 0x08000000, len = 128M\r\n\theap : org = 0x10000000, len = 256M\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.text :\r\n\t{\r\n\t\tPROVIDE(__image_start = .);\r\n\t\tPROVIDE(__text_start = .);\r\n\t\t.obj\/arch\/arm64\/mach-x3399\/start.o (.text)\r\n\t\t.obj\/arch\/arm64\/mach-x3399\/transition.o (.text)\r\n\t\t*(.text*)\r\n\t\t*(.init.text)\r\n\t\t*(.exit.text)\r\n\t\t*(.iplt)\r\n\t\t*(.note.gnu.build-id)\r\n\t\tPROVIDE(__text_end = .);\r\n\t} > ram\r\n\r\n\t.initcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__initcall_start = .);\r\n\t\tKEEP(*(.initcall_0.text))\r\n\t\tKEEP(*(.initcall_1.text))\r\n\t\tKEEP(*(.initcall_2.text))\r\n\t\tKEEP(*(.initcall_3.text))\r\n\t\tKEEP(*(.initcall_4.text))\r\n\t\tKEEP(*(.initcall_5.text))\r\n\t\tKEEP(*(.initcall_6.text))\r\n\t\tKEEP(*(.initcall_7.text))\r\n\t\tKEEP(*(.initcall_8.text))\r\n\t\tKEEP(*(.initcall_9.text))\r\n\t\tPROVIDE(__initcall_end = .);\r\n\t} > ram\r\n\r\n\t.exitcall ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__exitcall_start = .);\r\n\t\tKEEP(*(.exitcall_9.text))\r\n\t\tKEEP(*(.exitcall_8.text))\r\n\t\tKEEP(*(.exitcall_7.text))\r\n\t\tKEEP(*(.exitcall_6.text))\r\n\t\tKEEP(*(.exitcall_5.text))\r\n\t\tKEEP(*(.exitcall_4.text))\r\n\t\tKEEP(*(.exitcall_3.text))\r\n\t\tKEEP(*(.exitcall_2.text))\r\n\t\tKEEP(*(.exitcall_1.text))\r\n\t\tKEEP(*(.exitcall_0.text))\r\n\t\tPROVIDE(__exitcall_end = .);\r\n\t} > ram\r\n\r\n\t.ksymtab ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__ksymtab_start = .);\r\n\t\tKEEP(*(.ksymtab.text))\r\n\t\tPROVIDE(__ksymtab_end = .);\r\n\t} > ram\r\n\r\n\t.romdisk ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__romdisk_start = .);\r\n\t\tKEEP(*(.romdisk))\r\n\t\tPROVIDE(__romdisk_end = .);\r\n\t} > ram\r\n\r\n\t.rodata ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__rodata_start = .);\r\n\t\t*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\r\n\t\tPROVIDE(__rodata_end = .);\r\n\t} > ram\r\n\r\n\t.data_shadow ALIGN(8) :\r\n\t{\r\n\t\tPROVIDE(__data_shadow_start = .);\r\n\t\tPROVIDE(__data_shadow_end = (. + SIZEOF(.data)));\r\n\t\tPROVIDE(__image_end = __data_shadow_end);\r\n\t} > ram\r\n\r\n\t.data : AT(ADDR(.data_shadow))\r\n\t{\r\n\t\tPROVIDE(__data_start = .);\t\r\n\t\t*(.data*)\r\n\t\t. = ALIGN(8);\r\n  \t\tPROVIDE(__data_end = .);\r\n\t} > ram\r\n\r\n\t.bss ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__bss_start = .);\r\n\t\t*(.bss*)\r\n\t\t*(.sbss*)\r\n\t\t*(COMMON)\r\n\t\t. = ALIGN(8);\r\n\t\tPROVIDE(__bss_end = .);\r\n\t} > ram\r\n\r\n\t.stack ALIGN(16) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__stack_start = .);\r\n\t\tPROVIDE(__stack_el3_start = .);\r\n\t\t. += STACK_EL3_SIZE;\r\n\t\tPROVIDE(__stack_el3_end = .);\r\n\t\t. = ALIGN(16);\r\n\t\tPROVIDE(__stack_el2_start = .);\r\n\t\t. += STACK_EL2_SIZE;\r\n\t\tPROVIDE(__stack_el2_end = .);\r\n\t\t. = ALIGN(16);\r\n\t\tPROVIDE(__stack_el1_start = .);\r\n\t\t. += STACK_EL1_SIZE;\r\n\t\tPROVIDE(__stack_el1_end = .);\r\n\t\t. = ALIGN(16);\t\t\r\n\t\tPROVIDE(__stack_el0_start = .);\r\n\t\t. += STACK_EL0_SIZE;\r\n\t\tPROVIDE(__stack_el0_end = .);\r\n\t\t. = ALIGN(16);\r\n\t\tPROVIDE(__stack_end = .);\r\n\t} > ram\r\n\r\n\t.dma ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__dma_start = ORIGIN(dma));\r\n\t\tPROVIDE(__dma_end = ORIGIN(dma) + LENGTH(dma));\r\n\t} > dma\r\n\r\n\t.heap ALIGN(8) (NOLOAD) :\r\n\t{\r\n\t\tPROVIDE(__heap_start = ORIGIN(heap));\r\n\t\tPROVIDE(__heap_end = ORIGIN(heap) + LENGTH(heap));\r\n\t} > heap\r\n\r\n\t\/DISCARD\/ : { *(.dynsym) }\r\n\t\/DISCARD\/ : { *(.dynstr*) }\r\n\t\/DISCARD\/ : { *(.dynamic*) }\r\n\t\/DISCARD\/ : { *(.plt*) }\r\n\t\/DISCARD\/ : { *(.interp*) }\r\n\t\/DISCARD\/ : { *(.gnu*) }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"cda45fad8f5a45dfcf229f92a418ec8829f096f0","subject":"cpu\/esp8266: move most rodata sections to IROM","message":"cpu\/esp8266: move most rodata sections to IROM\n\nUsually, all .rodata sections are placed in RAM by the Espressif SDK since IROM (flash) access requires 32-bit word aligned reads. thanks to the LoadStoreError exception handler from esp-open-rtos which is used now in RIOT-OS, it is also possible to place .rodata sections in IROM (flash) to save RAM resources.\n","repos":"x3ro\/RIOT,josephnoir\/RIOT,cladmi\/RIOT,cladmi\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,toonst\/RIOT,mtausig\/RIOT,smlng\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,aeneby\/RIOT,kYc0o\/RIOT,mfrey\/RIOT,lazytech-org\/RIOT,yogo1212\/RIOT,smlng\/RIOT,jasonatran\/RIOT,OTAkeys\/RIOT,smlng\/RIOT,miri64\/RIOT,yogo1212\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,rfuentess\/RIOT,x3ro\/RIOT,authmillenon\/RIOT,basilfx\/RIOT,kaspar030\/RIOT,lazytech-org\/RIOT,ant9000\/RIOT,smlng\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,basilfx\/RIOT,mfrey\/RIOT,OTAkeys\/RIOT,cladmi\/RIOT,RIOT-OS\/RIOT,josephnoir\/RIOT,mfrey\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,x3ro\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,lazytech-org\/RIOT,toonst\/RIOT,mtausig\/RIOT,yogo1212\/RIOT,lazytech-org\/RIOT,x3ro\/RIOT,miri64\/RIOT,rfuentess\/RIOT,kYc0o\/RIOT,mtausig\/RIOT,ant9000\/RIOT,mfrey\/RIOT,RIOT-OS\/RIOT,josephnoir\/RIOT,x3ro\/RIOT,smlng\/RIOT,josephnoir\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,aeneby\/RIOT,OTAkeys\/RIOT,OTAkeys\/RIOT,aeneby\/RIOT,kaspar030\/RIOT,cladmi\/RIOT,toonst\/RIOT,toonst\/RIOT,basilfx\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,OTAkeys\/RIOT,mtausig\/RIOT,RIOT-OS\/RIOT,basilfx\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,josephnoir\/RIOT,mfrey\/RIOT,lazytech-org\/RIOT,toonst\/RIOT,miri64\/RIOT,miri64\/RIOT,rfuentess\/RIOT,kYc0o\/RIOT,rfuentess\/RIOT,OlegHahm\/RIOT,mtausig\/RIOT,authmillenon\/RIOT,miri64\/RIOT,kYc0o\/RIOT,aeneby\/RIOT,jasonatran\/RIOT,aeneby\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,cladmi\/RIOT,RIOT-OS\/RIOT","old_file":"cpu\/esp8266\/ld\/esp8266.riot-os.sdk.app.ld","new_file":"cpu\/esp8266\/ld\/esp8266.riot-os.sdk.app.ld","new_contents":"\/**\n  * This linker script is a modified version of eagle.app.v6.ld that\n  * was generated from xt-genldscripts.tpp for LSP and shipped with\n  * ESP8266_NONOS_SDK\n  *\/\n\n\/* Linker Script for ld -N *\/\n\nMEMORY\n{\n  dport0_0_seg : org = 0x3FF00000, len = 0x10\n  dram0_0_seg :  org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :  org = 0x40100000, len = 0x8000\n  irom0_0_seg :  org = 0x40210000, len = 0x5C000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\n\/* System task handling variables *\/\n\/* source: disassembly of boot rom at https:\/\/github.com\/trebisky\/esp8266 *\/\nPROVIDE( ets_task_min_prio = 0x3fffc6fc );\nPROVIDE( ets_idle_cb = 0x3fffdab0 );\nPROVIDE( ets_idle_arg = 0x3fffdab4 );\nPROVIDE( ets_task_exec_mask = 0x3fffdab8 );\nPROVIDE( ets_task_tab = 0x3fffdac0 );\nPROVIDE( flashchip = 0x3fffc714 );\nPROVIDE( sdk_flashchip = 0x3fffc718 );\nPROVIDE( _xt_interrupt_table = 0x3fffc200 );\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  \/*\n   * .rodata sections that are placed in RAM\n   *\n   * Usually, all .rodata sections are placed in RAM by the Espressif SDK\n   * since IROM (flash) access requires 32-bit word aligned reads.\n   *\n   * However, thanks to the LoadStoreError handler from esp-open-rtos which is\n   * also used in RIOT-OS, it is possible to place .rodata sections in IROM\n   * (flash) to save RAM resources.\n   *\n   * Only .rodata data sections of compilation units that may be executed\n   * while SPI flash is not mapped have to be stored in RAM. These are IRAM\n   * functions that are called from interrupt context or SPI flash management\n   * functions. Such compilation units have to be listed here.\n   *\n   * Furthermore, compilation units with constant data that are performance-\n   * critical should be listed here as well.\n   *\/\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n\n    *core.a:*(.rodata.* .rodata)\n    *cpu.a:*(.rodata .rodata.*)\n    *esp.a:*(.rodata .rodata.*)\n    *esp_now.a:*(.rodata .rodata.*)\n    *esp_wifi.a:*(.rodata .rodata.*)\n    *periph.a:*(.rodata.* .rodata)\n    *sdk.a:*(.rodata .rodata.*)\n    *xtensa.a:*(.rodata .rodata.*)\n\n    *libc.a:*.o(.rodata.* .rodata)\n    *libpp.a:wdev.o(.rodata.* .rodata)\n    *libmain.a:spi_flash.o(.rodata.* .rodata)\n\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  \/* ETS system memory starts at 0x3FFFC000 which is the top of the heap for the app *\/\n  . = 0x3FFFC000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.UserExceptionTrampoline.text)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* normal code should be in irom0 *\/\n    \/*\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *\/\n\n    \/* RIOT-OS compiled source files that use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *libcrypto.a:*(.literal .text)\n    *libmain.a:*(.literal .text .literal.* .text.*)\n    *libnet80211.a:*(.literal .text)\n    *libpp.a:*(.literal .text .literal.* .text.*)\n    *libphy.a:*(.literal .text .literal.* .text.*)\n    *libwpa.a:*(.literal .text)\n    *libwpa2.a:*(.literal .text)\n    *liblwip.a:*(.literal .text)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance) *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    *libgcc.a:*mulsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*divsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*fixsfsi.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memchr.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    enc28j60.a:*(.literal .text .literal.* .text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    *libmbedtls.a:(.literal .text .literal.* .text.*)\n\n    \/* RIOT-OS compiled code goes into IROM by default\n       (except for functions with section names defined in .text above.) *\/\n    *(.literal .text .literal.* .text.* .rodata .rodata.*)\n\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","old_contents":"\/**\n  * This linker script is a modified version of eagle.app.v6.ld that\n  * was generated from xt-genldscripts.tpp for LSP and shipped with\n  * ESP8266_NONOS_SDK\n  *\/\n\n\/* Linker Script for ld -N *\/\n\nMEMORY\n{\n  dport0_0_seg : org = 0x3FF00000, len = 0x10\n  dram0_0_seg :  org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :  org = 0x40100000, len = 0x8000\n  irom0_0_seg :  org = 0x40210000, len = 0x5C000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\n\/* System task handling variables *\/\n\/* source: disassembly of boot rom at https:\/\/github.com\/trebisky\/esp8266 *\/\nPROVIDE( ets_task_min_prio = 0x3fffc6fc );\nPROVIDE( ets_idle_cb = 0x3fffdab0 );\nPROVIDE( ets_idle_arg = 0x3fffdab4 );\nPROVIDE( ets_task_exec_mask = 0x3fffdab8 );\nPROVIDE( ets_task_tab = 0x3fffdac0 );\nPROVIDE( flashchip = 0x3fffc714 );\nPROVIDE( sdk_flashchip = 0x3fffc718 );\nPROVIDE( _xt_interrupt_table = 0x3fffc200 );\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    \/* TODO put only necessary .rodata to dram\n    *libc.a:*.o(.rodata.* .rodata)\n    *core.a:*(.rodata.* .rodata)\n    *cpu.a:*(.rodata .rodata.*)\n    *\/\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  \/* ETS system memory starts at 0x3FFFC000 which is the top of the heap for the app *\/\n  . = 0x3FFFC000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* normal code should be in irom0 *\/\n    \/*\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *\/\n\n    \/* RIOT-OS compiled source files that use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1.*)\n\n    \/* SDK libraries expect their .text sections to link to iram, not irom *\/\n    *libcrypto.a:*(.literal .text)\n    *libmain.a:*(.literal .text .literal.* .text.*)\n    *libnet80211.a:*(.literal .text)\n    *libpp.a:*(.literal .text .literal.* .text.*)\n    *libphy.a:*(.literal .text .literal.* .text.*)\n    *libwpa.a:*(.literal .text)\n    *libwpa2.a:*(.literal .text)\n    *liblwip.a:*(.literal .text)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n\n    \/* libgcc integer functions also need to be in .text, as some are called before\n       flash is mapped (also performance) *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    *libgcc.a:*mulsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*divsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*fixsfsi.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memchr.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n\n    enc28j60.a:*(.literal .text .literal.* .text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    *libmbedtls.a:(.literal .text .literal.* .text.*)\n\n    \/* RIOT-OS compiled code goes into IROM by default\n       (except for functions with section names defined in .text above.) *\/\n    *(.literal .text .literal.* .text.* .rodata .rodata.*)\n\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"6c58b1f6ea9856340dea89208135b1ea9122bd46","subject":"Mark `app` section as KEEP in linker script","message":"Mark `app` section as KEEP in linker script\n\nWe currently don't gc-sections on the final link, but if\/when we\ndo we'll need to mark the `app` sections to be kept.\n","repos":"google\/tock-on-titan,google\/tock-on-titan,google\/tock-on-titan","old_file":"src\/chips\/sam4l\/loader.ld","new_file":"src\/chips\/sam4l\/loader.ld","new_contents":"\/*\n * This file is part of StormLoader, the Storm Bootloader\n *\n * StormLoader is free software: you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation, either version 3 of the License, or\n * (at your option) any later version.\n *\n * StormLoader is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with Foobar.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n *  \n * Copyright 2014, Michael Andersen <m.andersen@eecs.berkeley.edu>\n *\n * This file is largely copied from the Atmel supplied linker scripts\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.) \n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nMEMORY\n{\n  rom (rx)  : ORIGIN = 0x00010000, LENGTH = 0x00070000\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _textstart = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        KEEP (*(.syscalls))\n\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _sapps = .;\n        KEEP (*(.app.*))\n        _eapps = .;\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n    _textend = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n\n        . = ALIGN(8);\n        *(.app_memory)\n\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","old_contents":"\/*\n * This file is part of StormLoader, the Storm Bootloader\n *\n * StormLoader is free software: you can redistribute it and\/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation, either version 3 of the License, or\n * (at your option) any later version.\n *\n * StormLoader is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with Foobar.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n *  \n * Copyright 2014, Michael Andersen <m.andersen@eecs.berkeley.edu>\n *\n * This file is largely copied from the Atmel supplied linker scripts\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.) \n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nMEMORY\n{\n  rom (rx)  : ORIGIN = 0x00010000, LENGTH = 0x00070000\n  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000\n}\n\n__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;\n__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _textstart = .;\n        KEEP(*(.vectors .vectors.*))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        KEEP (*(.syscalls))\n\n\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _sapps = .;\n        *(.app.*)\n        _eapps = .;\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n    _textend = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n\n        . = ALIGN(8);\n        *(.app_memory)\n\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n         _sstack = .;\n        . = . + __stack_size__;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"42a25255d23c10115cdd5e005afe8491ef7d62b1","subject":"nios2: rename default RAM region from 'SRAM' to 'RAM'","message":"nios2: rename default RAM region from 'SRAM' to 'RAM'\n\nIt's useful for the default RAM region to have a uniform name across\narchitectures so higher-level build processes do not need to have their\nown awareness of the names. Since NIOS2 uniformly uses 'SRAM', change it\nto 'RAM' to match most other architectures.\n\nSigned-off-by: Peter Marheine <ef0b2c492edde94778d7465bfbaeed52c5be6858@chromium.org>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr","old_file":"include\/zephyr\/arch\/nios2\/linker.ld","new_file":"include\/zephyr\/arch\/nios2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#include <zephyr\/linker\/sections.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specific linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n#else\n\t#define ROMABLE_REGION RAM\n#endif\n#define RAMABLE_REGION RAM\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    RAM   (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    RAM   (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to\n     * 'nios2-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n        {\n        *(.plt)\n        }\n\n    SECTION_PROLOGUE(.iplt,,)\n        {\n        *(.iplt)\n        }\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n#ifndef CONFIG_XIP\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        __text_region_start = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n#if defined(CONFIG_GP_ALL_DATA)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n    __rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        . = ALIGN(4);\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n        . = ALIGN(4);\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n    __rodata_region_end = .;\n    __rodata_region_size = __rodata_region_end - __rodata_region_start;\n\n    __rom_region_end = .;\n    __data_region_load_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_DATA_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            _image_ram_start = .;\n            __data_region_start = .;\n\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n\n#include <zephyr\/linker\/common-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n\t__data_start = .;\n        *(.data)\n        *(\".data.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        \/* the Nios2 architecture only has 16-bit signed immediate offsets in\n         * the instructions, so accessing a general address requires typically\n         * three instructions - basically, two for the two halves of the 32-bit\n         * address, and one to merge them - but if we can put the most commonly\n         * accessed globals in a special 64K span of memory addressed by the GP\n         * register, then we can access those values in a single instruction,\n         * saving both codespace and runtime.\n         *\n         * Since these immediate offsets are signed, place gp 0x8000 past the\n         * beginning of .sdata so that we can use both positive and negative\n         * offsets.\n         *\/\n#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n        *(.sdata .sdata.* .gnu.linkonce.s.*)\n        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\t__data_end = .;\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.sbss)\n        *(\".sbss.*\")\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#include <zephyr\/linker\/sections.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specific linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to\n     * 'nios2-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n        {\n        *(.plt)\n        }\n\n    SECTION_PROLOGUE(.iplt,,)\n        {\n        *(.iplt)\n        }\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n#ifndef CONFIG_XIP\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        __text_region_start = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n#if defined(CONFIG_GP_ALL_DATA)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n    __rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        . = ALIGN(4);\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n        . = ALIGN(4);\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n\n    __rodata_region_end = .;\n    __rodata_region_size = __rodata_region_end - __rodata_region_start;\n\n    __rom_region_end = .;\n    __data_region_load_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_DATA_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            _image_ram_start = .;\n            __data_region_start = .;\n\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n\n#include <zephyr\/linker\/common-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n\t__data_start = .;\n        *(.data)\n        *(\".data.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        \/* the Nios2 architecture only has 16-bit signed immediate offsets in\n         * the instructions, so accessing a general address requires typically\n         * three instructions - basically, two for the two halves of the 32-bit\n         * address, and one to merge them - but if we can put the most commonly\n         * accessed globals in a special 64K span of memory addressed by the GP\n         * register, then we can access those values in a single instruction,\n         * saving both codespace and runtime.\n         *\n         * Since these immediate offsets are signed, place gp 0x8000 past the\n         * beginning of .sdata so that we can use both positive and negative\n         * offsets.\n         *\/\n#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n        *(.sdata .sdata.* .gnu.linkonce.s.*)\n        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\t__data_end = .;\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.sbss)\n        *(\".sbss.*\")\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2ffc9c8de1d69ba20e8d1c576ad3e7944a354295","subject":"Use internal RAM only for data.","message":"Use internal RAM only for data.\n\ngit-svn-id: 43aea61533866f88f23079d48f4f5dc2d5288937@444 1d2547de-c912-0410-9cb9-b8ca96c0e9e2\n","repos":"Psykar\/kubos,kubostech\/KubOS,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos","old_file":"Demo\/ColdFire_MCF5282_Eclipse\/RTOSDemo\/m5282evb-ram-hosted.ld","new_file":"Demo\/ColdFire_MCF5282_Eclipse\/RTOSDemo\/m5282evb-ram-hosted.ld","new_contents":"\/* Linker script for m5282evb\n *\n * Version:Sourcery G++ Lite 4.2-125\n * BugURL:https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n *  Copyright 2007, 2008 CodeSourcery.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions. No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply. *\/\n\nOUTPUT_ARCH(m68k)\nENTRY(_start)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lcs3 -lcs3hosted -lcs3coldfire)\n\nMEMORY\n{\n  ram (rwx) : ORIGIN = 0x00000000, LENGTH = 16M\n  rom (rx) : ORIGIN = 0xFFE00000, LENGTH = 2M\n  rombar (rx) : ORIGIN = 0xf0000000, LENGTH = 512K\n  rambar (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\n  ipsbar (rw) : ORIGIN = 0x40000000, LENGTH = 0x20000000\n}\n\n\/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n *\/\nEXTERN(__cs3_reset_m5282evb)\nINCLUDE coldfire-names.inc\nEXTERN(__cs3_interrupt_vector_coldfire)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\nEXTERN(_start)\n\/* force exit to be picked up in a hosted or os environment *\/\nEXTERN(exit atexit)\n\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n\n  .text :\n  {\n    CREATE_OBJECT_SYMBOLS\n    __cs3_region_start_ram = .;\n    *(.cs3.region-head.ram)\n    ASSERT (. == __cs3_region_start_ram, \".cs3.region-head.ram not permitted\");\n    __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire;\n    *(.cs3.interrupt_vector)\n    \/* Make sure we pulled in an interrupt vector.  *\/\n    ASSERT (. != __cs3_interrupt_vector_coldfire, \"No interrupt vector\");\n\n    PROVIDE(__cs3_reset_m5282evb = _start);\n    __cs3_reset = __cs3_reset_m5282evb;\n    *(.cs3.reset)\n\n    *(.text .text.* .gnu.linkonce.t.*)\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.jcr))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\n    KEEP (*crtend.o(.jcr))\n\n    . = ALIGN(0x4);\n    *(.gcc_except_table .gcc_except_table.*)\n  } >ram\n  .eh_frame_hdr : ALIGN (4)\n  {\n    KEEP (*(.eh_frame_hdr))\n  } >ram\n  .eh_frame : ALIGN (4)\n  {\n    KEEP (*(.eh_frame))\n  } >ram\n  .rodata : ALIGN (4)\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n    . = ALIGN(4);\n    _init = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.init))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __preinit_array_start = .;\n    KEEP (*(.preinit_array))\n    __preinit_array_end = .;\n\n    . = ALIGN(4);\n    __init_array_start = .;\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    __init_array_end = .;\n\n    . = ALIGN(4);\n    _fini = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.fini))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __fini_array_start = .;\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    __fini_array_end = .;\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*crtend.o(.ctors))\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*crtend.o(.dtors))\n\n    *(.lit)\n\n    . = ALIGN(4);\n    __cs3_regions = .;\n    LONG (0)\n    LONG (__cs3_region_init_ram)\n    LONG (__cs3_region_start_ram)\n    LONG (__cs3_region_init_size_ram)\n    LONG (__cs3_region_zero_size_ram)\n    LONG (0)\n    LONG (__cs3_region_init_rombar)\n    LONG (__cs3_region_start_rombar)\n    LONG (__cs3_region_init_size_rombar)\n    LONG (__cs3_region_zero_size_rombar)\n    LONG (0)\n    LONG (__cs3_region_init_rambar)\n    LONG (__cs3_region_start_rambar)\n    LONG (__cs3_region_init_size_rambar)\n    LONG (__cs3_region_zero_size_rambar)\n    __cs3_regions_end = .;\n\n    . = ALIGN (8);\n    . = ALIGN (8);\n    _etext = .;\n  } >ram\n\n  .cs3.rom : ALIGN (8)\n  {\n    __cs3_region_start_rom = .;\n    *(.cs3.region-head.rom)\n    *(.rom)\n    . = ALIGN (8);\n  } >rom\n  .cs3.rom.bss :\n  {\n    *(.rom.b)\n    . = ALIGN (8);\n  } >rom\n  \/* __cs3_region_end_rom is deprecated *\/\n  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);\n  __cs3_region_size_rom = LENGTH(rom);\n  __cs3_region_init_rom = LOADADDR (.cs3.rom);\n  __cs3_region_init_size_rom = LOADADDR (.cs3.rom.bss) - LOADADDR (.cs3.rom);\n  __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);\n\n  .cs3.rombar : ALIGN (8)\n  {\n    __cs3_region_start_rombar = .;\n    *(.cs3.region-head.rombar)\n    *(.rombar)\n    . = ALIGN (8);\n  } >rombar\n  .cs3.rombar.bss :\n  {\n    *(.rombar.b)\n    . = ALIGN (8);\n  } >rombar\n  \/* __cs3_region_end_rombar is deprecated *\/\n  __cs3_region_end_rombar = __cs3_region_start_rombar + LENGTH(rombar);\n  __cs3_region_size_rombar = LENGTH(rombar);\n  __cs3_region_init_rombar = LOADADDR (.cs3.rombar);\n  __cs3_region_init_size_rombar = LOADADDR (.cs3.rombar.bss) - LOADADDR (.cs3.rombar);\n  __cs3_region_zero_size_rombar = SIZEOF(.cs3.rombar.bss);\n\n  .cs3.rambar : ALIGN (8)\n  {\n    __cs3_region_start_rambar = .;\n    *(.cs3.region-head.rambar)\n    *(.rambar)\n    . = ALIGN (8);\n  } >rambar\n  .cs3.rambar.bss :\n  {\n    *(.rambar.b)\n    . = ALIGN (8);\n  } >rambar\n  \/* __cs3_region_end_rambar is deprecated *\/\n  __cs3_region_end_rambar = __cs3_region_start_rambar + LENGTH(rambar);\n  __cs3_region_size_rambar = LENGTH(rambar);\n  __cs3_region_init_rambar = LOADADDR (.cs3.rambar);\n  __cs3_region_init_size_rambar = LOADADDR (.cs3.rambar.bss) - LOADADDR (.cs3.rambar);\n  __cs3_region_zero_size_rambar = SIZEOF(.cs3.rambar.bss);\n\n  .cs3.ipsbar :\n  {\n    __cs3_region_start_ipsbar = .;\n    *(.cs3.region-head.ipsbar)\n    . = ALIGN (8);\n  } >ipsbar\n  \/* __cs3_region_end_ipsbar is deprecated *\/\n  __cs3_region_end_ipsbar = __cs3_region_start_ipsbar + LENGTH(ipsbar);\n  __cs3_region_size_ipsbar = LENGTH(ipsbar);\n\n  .data : ALIGN (8)\n  {\n\n    *(.got.plt) *(.got)\n    *(.shdata)\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN (8);\n    *(.ram)\n    _edata = .;\n  } >rambar\n  .bss :\n  {\n    *(.shbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    *(.ram.b)\n    _end = .;\n    __end = .;\n  } >rambar\n  \/* __cs3_region_end_ram is deprecated *\/\n  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);\n  __cs3_region_size_ram = LENGTH(ram);\n  __cs3_region_init_ram = LOADADDR (.text);\n  __cs3_region_init_size_ram = _edata - ADDR (.text);\n  __cs3_region_zero_size_ram = _end - _edata;\n\n  .stab 0 (NOLOAD) : { *(.stab) }\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\n  \/* DWARF debug sections.\n   * Symbols in the DWARF debugging sections are relative to the beginning\n   * of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/* Linker script for m5282evb\n *\n * Version:Sourcery G++ Lite 4.2-125\n * BugURL:https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n *  Copyright 2007, 2008 CodeSourcery.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions. No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply. *\/\n\nOUTPUT_ARCH(m68k)\nENTRY(_start)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lcs3 -lcs3hosted -lcs3coldfire)\n\nMEMORY\n{\n  ram (rwx) : ORIGIN = 0x00000000, LENGTH = 16M\n  rom (rx) : ORIGIN = 0xFFE00000, LENGTH = 2M\n  rombar (rx) : ORIGIN = 0xf0000000, LENGTH = 512K\n  rambar (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\n  ipsbar (rw) : ORIGIN = 0x40000000, LENGTH = 0x20000000\n}\n\n\/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n *\/\nEXTERN(__cs3_reset_m5282evb)\nINCLUDE coldfire-names.inc\nEXTERN(__cs3_interrupt_vector_coldfire)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\nEXTERN(_start)\n\/* force exit to be picked up in a hosted or os environment *\/\nEXTERN(exit atexit)\n\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n\n  .text :\n  {\n    CREATE_OBJECT_SYMBOLS\n    __cs3_region_start_ram = .;\n    *(.cs3.region-head.ram)\n    ASSERT (. == __cs3_region_start_ram, \".cs3.region-head.ram not permitted\");\n    __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire;\n    *(.cs3.interrupt_vector)\n    \/* Make sure we pulled in an interrupt vector.  *\/\n    ASSERT (. != __cs3_interrupt_vector_coldfire, \"No interrupt vector\");\n\n    PROVIDE(__cs3_reset_m5282evb = _start);\n    __cs3_reset = __cs3_reset_m5282evb;\n    *(.cs3.reset)\n\n    *(.text .text.* .gnu.linkonce.t.*)\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.jcr))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\n    KEEP (*crtend.o(.jcr))\n\n    . = ALIGN(0x4);\n    *(.gcc_except_table .gcc_except_table.*)\n  } >ram\n  .eh_frame_hdr : ALIGN (4)\n  {\n    KEEP (*(.eh_frame_hdr))\n  } >ram\n  .eh_frame : ALIGN (4)\n  {\n    KEEP (*(.eh_frame))\n  } >ram\n  .rodata : ALIGN (4)\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n    . = ALIGN(4);\n    _init = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.init))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __preinit_array_start = .;\n    KEEP (*(.preinit_array))\n    __preinit_array_end = .;\n\n    . = ALIGN(4);\n    __init_array_start = .;\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    __init_array_end = .;\n\n    . = ALIGN(4);\n    _fini = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.fini))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __fini_array_start = .;\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    __fini_array_end = .;\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*crtend.o(.ctors))\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*crtend.o(.dtors))\n\n    *(.lit)\n\n    . = ALIGN(4);\n    __cs3_regions = .;\n    LONG (0)\n    LONG (__cs3_region_init_ram)\n    LONG (__cs3_region_start_ram)\n    LONG (__cs3_region_init_size_ram)\n    LONG (__cs3_region_zero_size_ram)\n    LONG (0)\n    LONG (__cs3_region_init_rombar)\n    LONG (__cs3_region_start_rombar)\n    LONG (__cs3_region_init_size_rombar)\n    LONG (__cs3_region_zero_size_rombar)\n    LONG (0)\n    LONG (__cs3_region_init_rambar)\n    LONG (__cs3_region_start_rambar)\n    LONG (__cs3_region_init_size_rambar)\n    LONG (__cs3_region_zero_size_rambar)\n    __cs3_regions_end = .;\n\n    . = ALIGN (8);\n    . = ALIGN (8);\n    _etext = .;\n  } >ram\n\n  .cs3.rom : ALIGN (8)\n  {\n    __cs3_region_start_rom = .;\n    *(.cs3.region-head.rom)\n    *(.rom)\n    . = ALIGN (8);\n  } >rom\n  .cs3.rom.bss :\n  {\n    *(.rom.b)\n    . = ALIGN (8);\n  } >rom\n  \/* __cs3_region_end_rom is deprecated *\/\n  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);\n  __cs3_region_size_rom = LENGTH(rom);\n  __cs3_region_init_rom = LOADADDR (.cs3.rom);\n  __cs3_region_init_size_rom = LOADADDR (.cs3.rom.bss) - LOADADDR (.cs3.rom);\n  __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);\n\n  .cs3.rombar : ALIGN (8)\n  {\n    __cs3_region_start_rombar = .;\n    *(.cs3.region-head.rombar)\n    *(.rombar)\n    . = ALIGN (8);\n  } >rombar\n  .cs3.rombar.bss :\n  {\n    *(.rombar.b)\n    . = ALIGN (8);\n  } >rombar\n  \/* __cs3_region_end_rombar is deprecated *\/\n  __cs3_region_end_rombar = __cs3_region_start_rombar + LENGTH(rombar);\n  __cs3_region_size_rombar = LENGTH(rombar);\n  __cs3_region_init_rombar = LOADADDR (.cs3.rombar);\n  __cs3_region_init_size_rombar = LOADADDR (.cs3.rombar.bss) - LOADADDR (.cs3.rombar);\n  __cs3_region_zero_size_rombar = SIZEOF(.cs3.rombar.bss);\n\n  .cs3.rambar : ALIGN (8)\n  {\n    __cs3_region_start_rambar = .;\n    *(.cs3.region-head.rambar)\n    *(.rambar)\n    . = ALIGN (8);\n  } >rambar\n  .cs3.rambar.bss :\n  {\n    *(.rambar.b)\n    . = ALIGN (8);\n  } >rambar\n  \/* __cs3_region_end_rambar is deprecated *\/\n  __cs3_region_end_rambar = __cs3_region_start_rambar + LENGTH(rambar);\n  __cs3_region_size_rambar = LENGTH(rambar);\n  __cs3_region_init_rambar = LOADADDR (.cs3.rambar);\n  __cs3_region_init_size_rambar = LOADADDR (.cs3.rambar.bss) - LOADADDR (.cs3.rambar);\n  __cs3_region_zero_size_rambar = SIZEOF(.cs3.rambar.bss);\n\n  .cs3.ipsbar :\n  {\n    __cs3_region_start_ipsbar = .;\n    *(.cs3.region-head.ipsbar)\n    . = ALIGN (8);\n  } >ipsbar\n  \/* __cs3_region_end_ipsbar is deprecated *\/\n  __cs3_region_end_ipsbar = __cs3_region_start_ipsbar + LENGTH(ipsbar);\n  __cs3_region_size_ipsbar = LENGTH(ipsbar);\n\n  .data : ALIGN (8)\n  {\n\n    *(.got.plt) *(.got)\n    *(.shdata)\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN (8);\n    *(.ram)\n    _edata = .;\n  } >ram\n  .bss :\n  {\n    *(.shbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    *(.ram.b)\n    _end = .;\n    __end = .;\n  } >ram\n  \/* __cs3_region_end_ram is deprecated *\/\n  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);\n  __cs3_region_size_ram = LENGTH(ram);\n  __cs3_region_init_ram = LOADADDR (.text);\n  __cs3_region_init_size_ram = _edata - ADDR (.text);\n  __cs3_region_zero_size_ram = _end - _edata;\n\n  .stab 0 (NOLOAD) : { *(.stab) }\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\n  \/* DWARF debug sections.\n   * Symbols in the DWARF debugging sections are relative to the beginning\n   * of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"52b774176416f438965546ff9f8171c539bd7cac","subject":"removed the superfluous and confusing '.'","message":"removed the superfluous and confusing '.'\n","repos":"matildah\/octocabbit","old_file":"scheduler\/startup.ld","new_file":"scheduler\/startup.ld","new_contents":"ENTRY(_Reset)\nSECTIONS\n{\n . = 0x10000;\n .startup : { startup.o(.text) }\n .text : { *(.text) }\n .data : { *(.data) }\n .bss : { *(.bss COMMON) }\n . = ALIGN(8);\n . = . + 0x1000; \/* 4kB of stack memory *\/\n stack_top = .;\n}\n","old_contents":"ENTRY(_Reset)\nSECTIONS\n{\n . = 0x10000;\n .startup . : { startup.o(.text) }\n .text : { *(.text) }\n .data : { *(.data) }\n .bss : { *(.bss COMMON) }\n . = ALIGN(8);\n . = . + 0x1000; \/* 4kB of stack memory *\/\n stack_top = .;\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"411f8d878f8fc10d110c25bba5e94b60fdd1a847","subject":"Add support for @PlatformIO Core 3.5.0","message":"Add support for @PlatformIO Core 3.5.0","repos":"lrmoreno007\/Arduino,sticilface\/Arduino,lrmoreno007\/Arduino,esp8266\/Arduino,wemos\/Arduino,esp8266\/Arduino,esp8266\/Arduino,Lan-Hekary\/Arduino,Adam5Wu\/Arduino,Adam5Wu\/Arduino,wemos\/Arduino,wemos\/Arduino,lrmoreno007\/Arduino,sticilface\/Arduino,esp8266\/Arduino,Lan-Hekary\/Arduino,Lan-Hekary\/Arduino,hallard\/Arduino,wemos\/Arduino,sticilface\/Arduino,Adam5Wu\/Arduino,lrmoreno007\/Arduino,wemos\/Arduino,hallard\/Arduino,Adam5Wu\/Arduino,Lan-Hekary\/Arduino,hallard\/Arduino,hallard\/Arduino,esp8266\/Arduino,sticilface\/Arduino,Lan-Hekary\/Arduino,lrmoreno007\/Arduino,Adam5Wu\/Arduino,sticilface\/Arduino,hallard\/Arduino","old_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nEXTERN(core_version)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    \/* PlatformIO *\/\n    \/* framework *\/\n    *.pioenvs\\\\*\\\\lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, EXCLUDE_FILE (umm_malloc.o) .text*)\n    \/* project dependencies *\/\n    *.pioenvs\\\\*\\\\lib*\\lib*.a:(.literal*, .text*)\n    *.pioenvs\/*\/lib*\/lib*.a:(.literal*, .text*)\n    \/* project source objects *\/\n    *.pioenvs\\\\*\\\\src\\\\*.o(.literal*, .text*)\n    *.pioenvs\/*\/src\/*.o(.literal*, .text*)\n    \/* End PlatformIO *\/\n    *libc.a:(.literal .text .literal.* .text.*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *libstdc++.a:(.literal .text .literal.* .text.*)\n    *liblwip_gcc.a:(.literal .text .literal.* .text.*)\n    *liblwip_src.a:(.literal .text .literal.* .text.*)\n    *liblwip2.a:(.literal .text .literal.* .text.*)\n    *liblwip2_1460.a:(.literal .text .literal.* .text.*)\n    *libaxtls.a:(.literal .text .literal.* .text.*)\n    *libat.a:(.literal.* .text.*)\n    *libcrypto.a:(.literal.* .text.*)\n    *libespnow.a:(.literal.* .text.*)\n    *libjson.a:(.literal.* .text.*)\n    *liblwip.a:(.literal.* .text.*)\n    *libmesh.a:(.literal.* .text.*)\n    *libnet80211.a:(.literal.* .text.*)\n    *libsmartconfig.a:(.literal.* .text.*)\n    *libssl.a:(.literal.* .text.*)\n    *libupgrade.a:(.literal.* .text.*)\n    *libwpa.a:(.literal.* .text.*)\n    *libwpa2.a:(.literal.* .text.*)\n    *libwps.a:(.literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    \/* PlatformIO *\/\n    \/* framework *\/\n    *.pioenvs\\\\*\\\\lib*.a:(.iram.text)\n    *.pioenvs\/*\/lib*.a:(.iram.text)\n    \/* project dependencies *\/\n    *.pioenvs\\\\*\\\\lib*\\\\lib*.a:(.iram.text)\n    *.pioenvs\/*\/lib*\/lib*.a:(.iram.text)\n    \/* project source objects *\/\n    *.pioenvs\\\\*\\\\src\\\\*.o(.iram.text)\n    *.pioenvs\/*\/src\/*.o(.iram.text)\n    \/* End PlatformIO *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nEXTERN(core_version)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    *.pioenvs\\\\*\\\\lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\\\\*\\\\lib\\*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/lib\/*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\\\\*\\\\src\\\\*.o(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/src\/*.o(EXCLUDE_FILE (umm_malloc.o) .literal*, \\\n    EXCLUDE_FILE (umm_malloc.o) .text*)\n    *libc.a:(.literal .text .literal.* .text.*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *libstdc++.a:(.literal .text .literal.* .text.*)\n    *liblwip_gcc.a:(.literal .text .literal.* .text.*)\n    *liblwip_src.a:(.literal .text .literal.* .text.*)\n    *liblwip2.a:(.literal .text .literal.* .text.*)\n    *liblwip2_1460.a:(.literal .text .literal.* .text.*)\n    *libaxtls.a:(.literal .text .literal.* .text.*)\n    *libat.a:(.literal.* .text.*)\n    *libcrypto.a:(.literal.* .text.*)\n    *libespnow.a:(.literal.* .text.*)\n    *libjson.a:(.literal.* .text.*)\n    *liblwip.a:(.literal.* .text.*)\n    *libmesh.a:(.literal.* .text.*)\n    *libnet80211.a:(.literal.* .text.*)\n    *libsmartconfig.a:(.literal.* .text.*)\n    *libssl.a:(.literal.* .text.*)\n    *libupgrade.a:(.literal.* .text.*)\n    *libwpa.a:(.literal.* .text.*)\n    *libwpa2.a:(.literal.* .text.*)\n    *libwps.a:(.literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    *.pioenvs\\\\*\\\\lib*.a:(.iram.text)\n    *.pioenvs\/*\/lib*.a:(.iram.text)\n    *.pioenvs\\\\*\\\\lib\\\\*.a:(.iram.text)\n    *.pioenvs\/*\/lib\/*.a:(.iram.text)\n    *.pioenvs\\\\*\\\\src\\\\*.o(.iram.text)\n    *.pioenvs\/*\/src\/*.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"d364601fc691fe11d64adaf4efb88ecf1fec30bc","subject":"Xen: Move .interp after .text","message":"Xen: Move .interp after .text\n\nMultiboot header needs to be in the first 8k of the file.\n","repos":"Solo5\/solo5,mato\/solo5,Solo5\/solo5,mato\/solo5,mato\/solo5","old_file":"bindings\/xen\/solo5_xen.lds","new_file":"bindings\/xen\/solo5_xen.lds","new_contents":"\/*\n * Copyright (c) 2015-2020 Contributors as noted in the AUTHORS file\n *\n * This file is part of Solo5, a sandboxed execution environment.\n *\n * Permission to use, copy, modify, and\/or distribute this software\n * for any purpose with or without fee is hereby granted, provided\n * that the above copyright notice and this permission notice appear\n * in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL\n * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE\n * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR\n * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS\n * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,\n * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN\n * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\/\n\n\/*\n * This is the custom linker script for the Solo5 'xen' target.\n *\n * The script is tested to work with a minimal set of input sections. If there\n * are unexpected input sections not named here, the result will probably not be\n * correct.\n *\/\nTEXT_START = 0x100000;\n\nENTRY(_start)\n\n\/*\n * Program headers: In order to force the linker to place each of our NOTEs\n * into a separate PT_NOTE header, we need to lay these out explicitly.\n *\/\nPHDRS {\n    interp PT_INTERP;\n    text PT_LOAD FLAGS(5); \/* No FILEHDR or PHDRS, force R\/E only.\n                              FLAGS values come from PF_x in elf.h *\/\n    data PT_LOAD;\n    note.not-openbsd PT_NOTE; \/* Must come first. *\/\n    note.xen PT_NOTE;\n    note.abi PT_NOTE;\n    note.manifest PT_NOTE;\n}\n\n\/*\n * Output sections.\n *\/\nSECTIONS {\n    . = TEXT_START; \/* No + SIZEOF_HEADERS *\/\n\n    \/*\n     * :text: The following input sections are placed in the R\/E :text segment.\n     *\/\n    _stext = .;\n\n    .text :\n    {\n        *(.data.multiboot)\n        *(.text)\n        *(.text.*)\n    } :text\n\n    .interp : {\n        *(.interp)\n    } :interp :text\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _etext = .;\n\n    \/* Read-only data *\/\n    .rodata :\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n    .eh_frame :\n    {\n        *(.eh_frame)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _erodata = .;\n\n    \/*\n     * :data: The following input sections are placed in the R\/W :data segment.\n     *\/\n\n    \/* For Xen, the ABI and MFT NOTEs must be in an R\/W segment, as they may\n     * be modified in-place by the bindings. *\/\n    .note.solo5.manifest :\n    {\n        *(.note.solo5.manifest*)\n    } :data :note.manifest\n    .note.solo5.abi :\n    {\n        *(.note.solo5.abi*)\n    } :data :note.abi\n    .note.solo5.not-openbsd :\n    {\n        *(.note.solo5.not-openbsd*)\n    } :data :note.not-openbsd\n    .note.solo5.xen :\n    {\n        *(.note.solo5.xen*)\n    } :data :note.xen\n\n    \/* Read-write data (initialized) *\/\n    .got :\n    {\n        *(.got.plt)\n        *(.got)\n    } :data\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n    }\n    .tdata :\n    {\n        *(.tdata)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _edata = .;\n\n    \/* Read-write data (uninitialized) *\/\n    .tbss :\n    {\n        *(.tbss)\n    }\n    .bss :\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _ebss = .;\n    _end = .;\n\n    \/* We are not building a GNU executable, so discard any default NOTEs the\n       toolchain might generate to prevent any surprises in the final layout. *\/\n    \/DISCARD\/ : {\n        *(.note.gnu.*)\n    }\n}\n","old_contents":"\/*\n * Copyright (c) 2015-2020 Contributors as noted in the AUTHORS file\n *\n * This file is part of Solo5, a sandboxed execution environment.\n *\n * Permission to use, copy, modify, and\/or distribute this software\n * for any purpose with or without fee is hereby granted, provided\n * that the above copyright notice and this permission notice appear\n * in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL\n * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE\n * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR\n * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS\n * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,\n * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN\n * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\/\n\n\/*\n * This is the custom linker script for the Solo5 'xen' target.\n *\n * The script is tested to work with a minimal set of input sections. If there\n * are unexpected input sections not named here, the result will probably not be\n * correct.\n *\/\nTEXT_START = 0x100000;\n\nENTRY(_start)\n\n\/*\n * Program headers: In order to force the linker to place each of our NOTEs\n * into a separate PT_NOTE header, we need to lay these out explicitly.\n *\/\nPHDRS {\n    interp PT_INTERP;\n    text PT_LOAD FLAGS(5); \/* No FILEHDR or PHDRS, force R\/E only.\n                              FLAGS values come from PF_x in elf.h *\/\n    data PT_LOAD;\n    note.not-openbsd PT_NOTE; \/* Must come first. *\/\n    note.xen PT_NOTE;\n    note.abi PT_NOTE;\n    note.manifest PT_NOTE;\n}\n\n\/*\n * Output sections.\n *\/\nSECTIONS {\n    . = TEXT_START; \/* No + SIZEOF_HEADERS *\/\n\n    \/*\n     * :text: The following input sections are placed in the R\/E :text segment.\n     *\/\n    _stext = .;\n\n    .interp : {\n        *(.interp)\n    } :interp :text\n\n    .text :\n    {\n        *(.data.multiboot)\n        *(.text)\n        *(.text.*)\n    } :text\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _etext = .;\n\n    \/* Read-only data *\/\n    .rodata :\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n    .eh_frame :\n    {\n        *(.eh_frame)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _erodata = .;\n\n    \/*\n     * :data: The following input sections are placed in the R\/W :data segment.\n     *\/\n\n    \/* For Xen, the ABI and MFT NOTEs must be in an R\/W segment, as they may\n     * be modified in-place by the bindings. *\/\n    .note.solo5.manifest :\n    {\n        *(.note.solo5.manifest*)\n    } :data :note.manifest\n    .note.solo5.abi :\n    {\n        *(.note.solo5.abi*)\n    } :data :note.abi\n    .note.solo5.not-openbsd :\n    {\n        *(.note.solo5.not-openbsd*)\n    } :data :note.not-openbsd\n    .note.solo5.xen :\n    {\n        *(.note.solo5.xen*)\n    } :data :note.xen\n\n    \/* Read-write data (initialized) *\/\n    .got :\n    {\n        *(.got.plt)\n        *(.got)\n    } :data\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n    }\n    .tdata :\n    {\n        *(.tdata)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _edata = .;\n\n    \/* Read-write data (uninitialized) *\/\n    .tbss :\n    {\n        *(.tbss)\n    }\n    .bss :\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    . = ALIGN(CONSTANT(MAXPAGESIZE));\n    _ebss = .;\n    _end = .;\n\n    \/* We are not building a GNU executable, so discard any default NOTEs the\n       toolchain might generate to prevent any surprises in the final layout. *\/\n    \/DISCARD\/ : {\n        *(.note.gnu.*)\n    }\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"a42cb2b0c4d45ded432c0e592f3fa06f69ab5f27","subject":"add comment 'symbole define'","message":"add comment 'symbole define'\n","repos":"hirakuni45\/RL78,hirakuni45\/RL78,hirakuni45\/RL78","old_file":"G13\/R5F100LGAFB.ld","new_file":"G13\/R5F100LGAFB.ld","new_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/G13, 128k flash, 12k ram *\/\n\/* R5F100LGAFB: 128K (0x00000 - 0x1FFFF) \/ 12K (0xFCF00 - 0xFFEFF) \/ 8K (0xF1000 - 0xF2FFF) *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007c\n\tOPT (r)   : ORIGIN = 0x000c0, LENGTH = 0x00004\n\tROM (r)   : ORIGIN = 0x000d8, LENGTH = 0x1ff28\n\tRAM (w)   : ORIGIN = 0xfcf00, LENGTH = 0x02fe0\n\tSTACK (w) : ORIGIN = 0xffee0, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n\/*\n\tSHORT(DEFINED(_INTWDTI) ? ABSOLUTE(_INTWDTI) : ABSOLUTE(_halt))\n*\/\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n\n  .opt :\n  {\n    KEEP(*(.opt))\n  } > OPT\n\n  \/* CubeSuite always starts at 0xd8.  *\/\n  .csstart : {\n    *(.csstart)\n  } > ROM\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  .rodata (MAX(__romdatastart + __romdatacopysize, 0x3000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > ROM\n\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/G13, 128k flash, 12k ram *\/\n\/* R5F100LGAFB: 128K (0x00000 - 0x1FFFF) \/ 12K (0xFCF00 - 0xFFEFF) \/ 8K (0xF1000 - 0xF2FFF) *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007c\n\tOPT (r)   : ORIGIN = 0x000c0, LENGTH = 0x00004\n\tROM (r)   : ORIGIN = 0x000d8, LENGTH = 0x1ff28\n\tRAM (w)   : ORIGIN = 0xfcf00, LENGTH = 0x02fe0\n\tSTACK (w) : ORIGIN = 0xffee0, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n  .opt :\n  {\n    KEEP(*(.opt))\n  } > OPT\n\n  \/* CubeSuite always starts at 0xd8.  *\/\n  .csstart : {\n    *(.csstart)\n  } > ROM\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  .rodata (MAX(__romdatastart + __romdatacopysize, 0x3000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > ROM\n\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c3953ccde66dc3b93850a09561919ca65d25f580","subject":"Fixes target_no_bootloader.ld: - makes the same changes as were done in target.ld - recomputes the size values for the 128K pic32mx device.","message":"Fixes target_no_bootloader.ld:\n- makes the same changes as were done in target.ld\n- recomputes the size values for the 128K pic32mx device.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/microchip-pic32mx-duinomitemega\/misc\/target_no_bootloader.ld","new_file":"boards\/microchip-pic32mx-duinomitemega\/misc\/target_no_bootloader.ld","new_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n**\r\n** This file was adjusted for memory regions of the PIC32MX530F128 device which\r\n** has 128+3K flash and 16K ram.  \r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 16K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0xBD000000, LENGTH = 128K \/* to BD020000-1, bootloader gets first 128k *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0xBFC00000, LENGTH = 0x180 \/* The beginning of the interrupt vector table is empty. *\/\r\n  PIC32MX_flash_boot_remaining (rx): ORIGIN = 0xBFC00A00, LENGTH = 3K-0x10-0xA00 \/* Skipped flash_cfg rgister and 0xa00 at the beginning for the interupt vector table. NOTE(bracz): also one debug page might need to be reserved here, which would directly prevent us from placing the interrupt vector table here. -- need 2K + 1k debug. Maybe the vector table could be trimmed. Calculations give that 48 vectors would fit. *\/\r\n  PIC32MX_flash_cfg  (r!x): ORIGIN = 0xBFC00BF0, LENGTH = 0x0010\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** Located at the beginning of bootflash for now.\r\n** 0xBFC00000 + 0x200 + (64 vectors * x20)) = 0xBFC00A00\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0xBFC00000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\n\/* NOT NEEDED -- we have our own entry routine, not using cs3's\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) *\/\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 9k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** PIC32MX configuration registers\r\n  *\/\r\n  .PIC32MX_cfg_init :\r\n  {\r\n    *(PIC32MX_cfg_init)\r\n  } >PIC32MX_flash_cfg \/*AT>PIC32MX_physical_flash_cfg*\/\r\n  \/* Assert exactly 4 words are placed in configuration area *\/\r\n  \/* Note: terminating semicolon causes syntax error for ASSERT in following line ! *\/\r\n  ASSERT (SIZEOF(.PIC32MX_cfg_init) == 0x10, \"PIC32MX configuration register set must be 4 words long\")\r\n\r\n  \/*\r\n  ** First thing in boot flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n    \/*\r\n    ** While the PIC32MX is in Bootstrap mode, all interrupts are disabled\r\n    ** and all general exceptions are redirected to address 0xBFC00380\r\n    *\/\r\n    . = __cs3_reset + 0x0380;\r\n    KEEP(*(.bev_handler)) \/* optional boot exception handler *\/\r\n\r\n  } >PIC32MX_flash_boot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n    *(.gnu_extab .gnu_extab.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame .eh_frame.*))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  \/*  __cs3_region_init_ram = _etext; DRN updated this; seems correct...  bracz: not really. *\/\r\n  __cs3_region_init_ram = LOADADDR(.data);\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","old_contents":"\/* PIC32MX linker script for CodeSourcery GCC toolchain\r\n**\r\n** Links a complete application to run from PIC32MX flash, including\r\n** initialization from power-on reset, interrupt vectors, etc.\r\n**\r\n** History:\r\n**   20090926 DRNadler: Per CodeSourcery, ENTRY is __cs3_reset_PIC32MX\r\n**   20090830 DRNadler: Minimal C++ demonstration version (KSEG1)\r\n**   20090713 DRNadler: Reset reason stored in RAM0\r\n**   20090511 DRNadler: Original coding\r\n**\r\n** For reference, see:\r\n** - CodeSourcery G++ 4.3-80 linker script for malta-24kc\r\n** - Microchip \"elf32pic32mx.x\" generic PIC32 link script\r\n** - Microchip 32MX440F256H processor-specific \"procdef.ld\" definitions\r\n*\/\r\n\r\n\r\n\/*\r\n * Copyright (c) 2009 Dave Nadler\r\n * Copyright (c) 2007, 2008 CodeSourcery, Inc.\r\n *\r\n * The authors hereby grant permission to use, copy, modify, distribute,\r\n * and license this software and its documentation for any purpose, provided\r\n * that existing copyright notices are retained in all copies and that this\r\n * notice is included verbatim in any distributions.  No written agreement,\r\n * license, or royalty fee is required for any of the authorized uses.\r\n * Modifications to this software may be copyrighted by their authors\r\n * and need not follow the licensing terms described here, provided that\r\n * the new terms are clearly indicated on the first page of each file where\r\n * they apply.\r\n *\/\r\nOUTPUT_ARCH(mips)\r\nENTRY(__cs3_reset_PIC32MX) \/* for debugger support, use actual HW-level entry and not _start *\/\r\nSEARCH_DIR(.)\r\n\/* Force repeated search of CS3 and GCC libraries *\/\r\nGROUP(-lcs3hal -lgcc -lc -lcs3 -lcs3unhosted)\r\n\/**\/\r\n\r\n\/*\r\n** NOTE: Device programmers require PIC32MX \"physical\" addresses.\r\n** PIC32MX \"physical\" addresses ::= \"virtual\" addresses & 0x1FFFffff\r\n** LD's >AT directive is incapable of performing this mapping,\r\n** as it does not respect alignment\/padding performed in the virtual space.\r\n** Therefore, this address mask operation must be performed by:\r\n** - address masking by the device programmer's software, or\r\n** - post-processing of ELF or HEX file prior device programming\r\n*\/\r\n\r\nMEMORY\r\n{\r\n  ram0 (!r!x) : ORIGIN = 0xA0000000, LENGTH = 16     \/* tiny part of RAM reserved for startup code *\/\r\n  ram  (!r!x) : ORIGIN = 0xA0000010, LENGTH = 32K-16 \/* not read-only, not executable *\/\r\n  \/*\r\n  ** Memory map here is based on executing in KSEG1 mode.\r\n  ** PIC32MX flash is broken into user flash and boot flash.\r\n  ** Boot flash contains the configuration words required for reset.\r\n  ** The following are KSEG1 logical addresses (??? should change to KSEG0 to enable caches).\r\n  *\/\r\n  PIC32MX_flash_user (rx) : ORIGIN = 0xBD000000, LENGTH = 128K \/* to BD020000-1, bootloader gets first 128k *\/\r\n  \/*\r\n  ** When PIC32MX comes out of reset, it branches to the start of the boot flash\r\n  ** The last (4kb) page in Boot Flash Memory contains the DEBUG Page, which is reserved for \r\n  ** use by (some) debugger tool while debugging (by convention, not by hardware).\r\n  *\/\r\n  PIC32MX_flash_boot (rx) : ORIGIN = 0xBFC00000, LENGTH = 0x2000 \/* 12k - 4k debug page *\/\r\n  PIC32MX_flash_cfg  (r!x): ORIGIN = 0xBFC02FF0, LENGTH = 0x0010\r\n}\r\n\r\n\/*\r\n** Interrupt vector spacing 1 (ie 0x20 or 32 bytes\/vector).\r\n** TEMPORARY: located at end of bootflash for now (this is \"debug page\")...\r\n** 0xBFC03000-(0x10 config registers + 0x200+ (64 vectors * x20))= 0xBFC025F0\r\n*\/\r\n_vector_spacing = 0x00000001;\r\n_ebase_address  = 0xBFC02000; \/* must be on a 4kb page boundary; rounded down *\/\r\n\r\n\/* These force the linker to search for particular symbols from\r\n * the start of the link process and thus ensure the user's\r\n * overrides are picked up\r\n *\/\r\nEXTERN(__cs3_reset_PIC32MX)\r\nEXTERN(_start)\r\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\r\n\r\n\/*\r\n * Provide for a minimum stack and heap size\r\n * - _min_stack_size - represents the minimum space that must be made\r\n *                     available for the stack.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n * - _min_heap_size  - represents the minimum space that must be made\r\n *                     available for the heap.  Can be overridden from\r\n *                     the command line using the linker's --defsym option.\r\n *\/\r\nEXTERN (_min_stack_size _min_heap_size)\r\nPROVIDE(_min_stack_size = 9k) ;\r\nPROVIDE(_min_heap_size  = 9k) ;\r\nPROVIDE(__cs3_heap_start = _end );\r\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram - _min_stack_size);\r\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); \/* stack grows down from end of RAM *\/\r\n\r\nHEAP_SPACE_AVAILABLE = (__cs3_heap_end - __cs3_heap_start);\r\nASSERT( HEAP_SPACE_AVAILABLE >= _min_heap_size , \"Not enough heap space\");\r\n\r\n\r\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\r\n\r\n\r\nSECTIONS\r\n{\r\n  \/*\r\n  ** PIC32MX configuration registers\r\n  *\/\r\n  .PIC32MX_cfg_init :\r\n  {\r\n    *(PIC32MX_cfg_init)\r\n  } >PIC32MX_flash_cfg \/*AT>PIC32MX_physical_flash_cfg*\/\r\n  \/* Assert exactly 4 words are placed in configuration area *\/\r\n  \/* Note: terminating semicolon causes syntax error for ASSERT in following line ! *\/\r\n  ASSERT (SIZEOF(.PIC32MX_cfg_init) == 0x10, \"PIC32MX configuration register set must be 4 words long\")\r\n\r\n  \/*\r\n  ** First thing in boot flash area must be 'reset' code, which must be\r\n  ** short enough it doesn't land in bootstrap exception address (unless\r\n  ** bootstrap exception is unused).\r\n  *\/\r\n  .boot_flash_text :\r\n  {\r\n    PROVIDE(__cs3_reset_PIC32MX = _start);\r\n    __cs3_reset = __cs3_reset_PIC32MX;\r\n    *(.cs3.reset)\r\n\r\n    \/*\r\n    ** While the PIC32MX is in Bootstrap mode, all interrupts are disabled\r\n    ** and all general exceptions are redirected to address 0xBFC00380\r\n    *\/\r\n    . = __cs3_reset + 0x0380;\r\n    KEEP(*(.bev_handler)) \/* optional boot exception handler *\/\r\n\r\n  } >PIC32MX_flash_boot\r\n\r\n  \/*\r\n  ** \"Normal\" code in user flash\r\n  *\/\r\n  .text :\r\n  {\r\n    CREATE_OBJECT_SYMBOLS \/* create symbols for each input file - why ??? *\/\r\n\r\n    __cs3_region_start_rom = .;\r\n    *(.cs3.region-head.rom)\r\n    ASSERT (. == __cs3_region_start_rom, \".cs3.region-head.rom not permitted\");\r\n\r\n    \/* \"normal\" code follows... *\/\r\n    *(.text .text.* .gnu.linkonce.t.*)\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.jcr))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\r\n    KEEP (*crtend.o(.jcr))\r\n\r\n    . = ALIGN(0x4);\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame_hdr : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame_hdr))\r\n    *(.eh_frame_entry .eh_frame_entry.*)\r\n  } >PIC32MX_flash_user\r\n  \r\n  .eh_frame : ALIGN (4)\r\n  {\r\n    KEEP (*(.eh_frame))\r\n  }  >PIC32MX_flash_user\r\n  \r\n  \/* MDI semihosting uses a pointer in this section.  *\/\r\n  .sdeosabi : ALIGN (4)\r\n  {\r\n    *(.sdeosabi)\r\n  } >ram\r\n  \r\n  .rodata : ALIGN (4)\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.init))\r\n\r\n    . = ALIGN(4);\r\n    __preinit_array_start = .;\r\n    KEEP (*(.preinit_array))\r\n    __preinit_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    __init_array_start = .;\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    __init_array_end = .;\r\n\r\n    . = ALIGN(4);\r\n    KEEP(*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    __fini_array_start = .;\r\n    KEEP (*(.fini_array))\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    __fini_array_end = .;\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*crtend.o(.ctors))\r\n\r\n    . = ALIGN(0x4);\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*crtend.o(.dtors))\r\n\r\n    *(.lit)\r\n\r\n    . = ALIGN(4);\r\n    __cs3_regions = .;\r\n    LONG (0)\r\n    LONG (__cs3_region_init_ram)\r\n    LONG (__cs3_region_start_ram)\r\n    LONG (__cs3_region_init_size_ram)\r\n    LONG (__cs3_region_zero_size_ram)\r\n    __cs3_regions_end = .;\r\n\r\n    . = ALIGN (8);\r\n    \/* Redundant, removed: . = ALIGN (8); *\/\r\n\r\n    _etext = .; \/* first double-word past end of text, and start address for RAM initialization data stored in ROM *\/\r\n  }  >PIC32MX_flash_user\r\n  \r\n  __cs3_region_size_rom = LENGTH(PIC32MX_flash_user); \/* just total size of flash *\/\r\n\r\n  \/*\r\n  ** Initialized data is linked for RAM, but placed in ROM using the AT> directive.\r\n  ** Startup code copies it to RAM during initialization.\r\n  ** WARNING: Must follow _etext !!\r\n  *\/\r\n  .data : ALIGN (8)\r\n  {\r\n    __cs3_region_start_ram = .;\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    . = ALIGN(8);\r\n    \/*\r\n    ** GP-relative addressing permits fast access via single instruction addressing,\r\n    ** using a signed 16-bit offset (i.e. -32768 to 32767) from the gp register.\r\n    ** Set GP to the middle of the \"small data\" area, then link in up to 64k\r\n    ** of \"small data\"....\r\n    *\/\r\n    _gp = . + 0x8000; \/* beginning of \"small data\" plus 32k *\/\r\n    *(.lit8)\r\n    *(.lit4)\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n\r\n    \/* this magic is needed for the device tables of openMRN *\/\r\n    . = ALIGN (8);\r\n    KEEP(*( SORT (.device.table.*))) ;\r\n\r\n    . = ALIGN (8);\r\n    *(.ram)\r\n    _edata = .;\r\n  } >ram  AT>PIC32MX_flash_user\r\n\r\n  \/* Wrong, length just gives 256k size of flash: USER_FLASH_USED = LENGTH(PIC32MX_flash_user)+SIZEOF(.data); *\/\r\n  \r\n  \/* DRN: The following is wrong; doesn't mark end of RAM copy...\r\n  \/* For diagnostic use only, mark end of initialized-data copy in ROM *\/\r\n  \/* .edata_copy_end :\r\n  \/* {\r\n  \/*   _edata_copy_end = .;\r\n  \/*   LONG(0) \/* force LD to output this section (empty sections are discarded) *\/\r\n  \/* } >PIC32MX_flash_user\r\n  *\/\r\n\r\n  \/* data written by startup code and NOT to be initialized by CS3 *\/\r\n  .startup_data :\r\n  {\r\n    *(.reset_data)\r\n  } >ram0\r\n\r\n  \/* Un-initialized data, zero'd by CS3 C-language initialization module *\/\r\n  .bss :\r\n  {\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    *(.shbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    . = ALIGN (8);\r\n    *(.ram.b)\r\n    _end = .;\r\n    __end = .;\r\n  } >ram\r\n\r\n  \/* __cs3_region_end_ram is deprecated *\/\r\n  \/*__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);*\/\r\n  __cs3_region_size_ram = LENGTH(ram);\r\n  \/* WRONG: load address is PHYSICAL, not logical address:  __cs3_region_init_ram = LOADADDR (.data);  WRONG *\/\r\n  __cs3_region_init_ram = _etext; \/* DRN updated this; seems correct... *\/\r\n  __cs3_region_init_size_ram = _edata - ADDR (.data);\r\n  __cs3_region_zero_size_ram = _end - _edata;\r\n\r\n  \/* Compute space available for stack+heap... *\/\r\n  AVAILABLE_RAM_FOR_STACK_PLUS_HEAP = LENGTH(ram)-(SIZEOF(.data)+SIZEOF(.bss));\r\n\r\n\r\n  \/* ============================  Interrupt Branch Vectors  =========================== *\/\r\n  .gen_exception _ebase_address + 0x180 :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  }\r\n\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  }\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  \/* ============================  End Interrupt Branch Vectors  =========================== *\/\r\n  \r\n\r\n\r\n  .stab 0 (NOLOAD) : { *(.stab) }\r\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\r\n  \/* DWARF debug sections.\r\n   * Symbols in the DWARF debugging sections are relative to the beginning\r\n   * of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0 : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"78be3771bdf2498d434d1cfd47d72542b63179a3","subject":"soc: andes_v5: linker: fix many linker symbols name","message":"soc: andes_v5: linker: fix many linker symbols name\n\nPR #37938 aligns many linker symbols name like rom\/rodata_regions ...,\nbut ae350 soc linker script doesn't update for that. Migrate all linker\nsymbols name to PR #37938 changes.\n\nSigned-off-by: Jim Shu <1635390bb889c4cdee38f53a57b0915ac07d9bd9@andestech.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/riscv\/riscv-privilege\/andes_v5\/ae350\/linker.ld","new_file":"soc\/riscv\/riscv-privilege\/andes_v5\/ae350\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n * Copyright (c) 2021 Andes Technology Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the ae350 platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n\/* Make linker section alignment comply with PMA granularity. *\/\n#if defined(CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE;\n#else\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_SOC_ANDES_V5_PMA)\n\/*\n * Andes-V5 PMA needs power-of-2 alignment.\n *\/\n#define MPU_MIN_SIZE_ALIGN . = ALIGN(_region_min_align);\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_MIN_SIZE_ALIGN\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t\/* In XIP mode, the .init section must be at the start of ROM *\/\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init.*))\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_region_start = .;\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n * Copyright (c) 2021 Andes Technology Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the ae350 platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n\/* Make linker section alignment comply with PMA granularity. *\/\n#if defined(CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE;\n#else\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_SOC_ANDES_V5_PMA)\n\/*\n * Andes-V5 PMA needs power-of-2 alignment.\n *\/\n#define MPU_MIN_SIZE_ALIGN . = ALIGN(_region_min_align);\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_MIN_SIZE_ALIGN\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    LINKER_DT_REGION_FROM_NODE(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t\/* In XIP mode, the .init section must be at the start of ROM *\/\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init.*))\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n\t_image_rodata_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end - _image_rom_start);\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_image_rom_end = LOADADDR(.last_section);\n_image_rom_size = _image_rom_end - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"243120da0c994baa14acb1e83703390a6b7a8d8e","subject":"linker: kobject-text: align multiline string definition syntax","message":"linker: kobject-text: align multiline string definition syntax\n\nAlign multiline string definition syntax in ASSERT in linker\nscript. This allows to use linker script with ASSERT provided\nby linker (i.e GNU toolchain) or dummy ASSERT defined as\npreprocessor macros (ARC MWDT toolchain).\n\nSigned-off-by: Eugeniy Paltsev <ec089b543c2604b626d7ce60c03e4d074ed102c7@synopsys.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr","old_file":"include\/linker\/kobject-text.ld","new_file":"include\/linker\/kobject-text.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#ifdef CONFIG_USERSPACE\n\t\/* We need to reserve room for the gperf generated hash functions.\n\t * Fortunately, unlike the data tables, the size of the code is\n\t * reasonably predictable.\n\t *\n\t * The linker will error out complaining that the location pointer\n\t * is moving backwards if the reserved room isn't large enough.\n\t *\/\n\t_kobject_text_area_start = .;\n\t*(\".kobject_data.text*\")\n\t_kobject_text_area_end = .;\n\t_kobject_text_area_used = _kobject_text_area_end - _kobject_text_area_start;\n#ifndef LINKER_PASS2\n#ifdef CONFIG_DYNAMIC_OBJECTS\n\tPROVIDE(z_object_gperf_find = .);\n\tPROVIDE(z_object_gperf_wordlist_foreach = .);\n#else\n\tPROVIDE(z_object_find = .);\n\tPROVIDE(z_object_wordlist_foreach = .);\n#endif\n#endif\n\n\t\/* In a valid build the MAX function will always evaluate to the\n\tsecond argument below, but to give the user a good error message\n\twhen the area overflows we need to temporarily corrupt the\n\tlocation counter, and then detect the overflow with an assertion\n\tlater on. *\/\n\n\t. = MAX(., _kobject_text_area_start + CONFIG_KOBJECT_TEXT_AREA);\n\n\tASSERT(\n\t\tCONFIG_KOBJECT_TEXT_AREA >= _kobject_text_area_used,\n\"The configuration system has incorrectly set \\\n'CONFIG_KOBJECT_TEXT_AREA' to \\\nCONFIG_KOBJECT_TEXT_AREA, which is not big enough. You must \\\nthrough Kconfig either disable 'CONFIG_USERSPACE', or set \\\n'CONFIG_KOBJECT_TEXT_AREA' to a value larger than \\\nCONFIG_KOBJECT_TEXT_AREA.\"\n\t\t);\n#endif \/* CONFIG_USERSPACE *\/\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#ifdef CONFIG_USERSPACE\n\t\/* We need to reserve room for the gperf generated hash functions.\n\t * Fortunately, unlike the data tables, the size of the code is\n\t * reasonably predictable.\n\t *\n\t * The linker will error out complaining that the location pointer\n\t * is moving backwards if the reserved room isn't large enough.\n\t *\/\n\t_kobject_text_area_start = .;\n\t*(\".kobject_data.text*\")\n\t_kobject_text_area_end = .;\n\t_kobject_text_area_used = _kobject_text_area_end - _kobject_text_area_start;\n#ifndef LINKER_PASS2\n#ifdef CONFIG_DYNAMIC_OBJECTS\n\tPROVIDE(z_object_gperf_find = .);\n\tPROVIDE(z_object_gperf_wordlist_foreach = .);\n#else\n\tPROVIDE(z_object_find = .);\n\tPROVIDE(z_object_wordlist_foreach = .);\n#endif\n#endif\n\n\t\/* In a valid build the MAX function will always evaluate to the\n\tsecond argument below, but to give the user a good error message\n\twhen the area overflows we need to temporarily corrupt the\n\tlocation counter, and then detect the overflow with an assertion\n\tlater on. *\/\n\n\t. = MAX(., _kobject_text_area_start + CONFIG_KOBJECT_TEXT_AREA);\n\n\tASSERT(\n\t\tCONFIG_KOBJECT_TEXT_AREA >= _kobject_text_area_used,\n\"The configuration system has incorrectly set\n'CONFIG_KOBJECT_TEXT_AREA' to\nCONFIG_KOBJECT_TEXT_AREA, which is not big enough. You must\nthrough Kconfig either disable 'CONFIG_USERSPACE', or set\n'CONFIG_KOBJECT_TEXT_AREA' to a value larger than\nCONFIG_KOBJECT_TEXT_AREA.\"\n\t\t);\n#endif \/* CONFIG_USERSPACE *\/\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c33adc86c776605d581bc84c850a3866fb100f57","subject":"Removed absolute path from linker script","message":"Removed absolute path from linker script\n","repos":"AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,hioa-cs\/IncludeOS,nlitsme\/IncludeOS,AndreasAakesson\/IncludeOS,hioa-cs\/IncludeOS,alfred-bratterud\/IncludeOS,ingve\/IncludeOS,ingve\/IncludeOS,mnordsletten\/IncludeOS,mnordsletten\/IncludeOS,alfred-bratterud\/IncludeOS,AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,nlitsme\/IncludeOS,nlitsme\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,ingve\/IncludeOS,AndreasAakesson\/IncludeOS,AnnikaH\/IncludeOS,mnordsletten\/IncludeOS,AnnikaH\/IncludeOS,hioa-cs\/IncludeOS,AndreasAakesson\/IncludeOS,AndreasAakesson\/IncludeOS,ingve\/IncludeOS,alfred-bratterud\/IncludeOS,ingve\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,nlitsme\/IncludeOS,mnordsletten\/IncludeOS,alfred-bratterud\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS","old_file":"src\/linker.ld","new_file":"src\/linker.ld","new_contents":"\nENTRY(_start)\n\nSECTIONS\n{\n    \/*\n  .text.start (0x200000+SIZEOF_HEADERS) : {\n    \/usr\/local\/IncludeOS\/lib\/os.a:kernel_start.o( .text )\n  }*\/\n\n  .text (0x200000+SIZEOF_HEADERS) : {\n   _TEXT_START_ = .;\n    *(.text)\n   _TEXT_END_ = .;\n  }\n\n  .init : {\t\n  \t_INIT_START_ = .;\n\t*(.init)\n\t_INIT_END_ = .;\t\n  }  \t\n  \n  .ctors : {\n  \t *(.ctors)\n  }\n  .dtors : {\n  \t *(.dtors)\n  }\n   .rodata :  {\n_RODATA_START_ = .;\n    *(.rodata)\n_RODATA_END_ = .;\n  }\n\n  \n  .data :  {\n_DATA_START_ = .;\n    *(.data)\n_DATA_END_ = .;\n  }\n\n  \n   .bss :  { _BSS_START_ = .;  *(.bss) _BSS_END_ = .;  }\n   _includeos = .;\n  _end = .;  \n}\n\n\n\n","old_contents":"\nENTRY(_start)\n\nSECTIONS\n{\n  .text.start (0x200000+SIZEOF_HEADERS) : {\n    \/usr\/local\/IncludeOS\/lib\/os.a:kernel_start.o( .text )\n  }\n\n  .text : {\n   _TEXT_START_ = .;\n    *(.text)\n   _TEXT_END_ = .;\n  }\n\n  .init : {\t\n  \t_INIT_START_ = .;\n\t*(.init)\n\t_INIT_END_ = .;\t\n  }  \t\n  \n  .ctors : {\n  \t *(.ctors)\n  }\n  .dtors : {\n  \t *(.dtors)\n  }\n   .rodata :  {\n_RODATA_START_ = .;\n    *(.rodata)\n_RODATA_END_ = .;\n  }\n\n  \n  .data :  {\n_DATA_START_ = .;\n    *(.data)\n_DATA_END_ = .;\n  }\n\n  \n   .bss :  { _BSS_START_ = .;  *(.bss) _BSS_END_ = .;  }\n   _includeos = .;\n  _end = .;  \n}\n\n\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c4dc72cf2d1704aeb9f8e0c27e4af357f3865286","subject":"[SAMR21] change stack allocation to use all free RAM (#2334)","message":"[SAMR21] change stack allocation to use all free RAM (#2334)\n\nInitially fixed size 8k was allocated for stack.\r\nAs result there was almost no free RAM. This\r\nchange creates stack on all free RAM.\r\n\r\nSigned-off-by: Oleksandr Grytsov <a4284420daa50c9a032f36f0da83444a864c07ab@gmail.com>","repos":"srickardti\/openthread,georgecpr\/openthread,erja-gp\/openthread,mszczodrak\/openthread,lanyuwen\/openthread,gandreello\/openthread,openthread\/openthread,xiaom-GitHub\/openthread,georgecpr\/openthread,gandreello\/openthread,turon\/openthread,turon\/openthread,LeZhang2016\/openthread,lanyuwen\/openthread,pvanhorn\/openthread,chshu\/openthread,pvanhorn\/openthread,jwhui\/openthread,LeZhang2016\/openthread,jwhui\/openthread,mszczodrak\/openthread,chshu\/openthread,openthread\/openthread,srickardti\/openthread,chshu\/openthread,gandreello\/openthread,srickardti\/openthread,LeZhang2016\/openthread,xiaom-GitHub\/openthread,mszczodrak\/openthread,LeZhang2016\/openthread,LeZhang2016\/openthread,abtink\/openthread,gandreello\/openthread,lanyuwen\/openthread,bukepo\/openthread,librasungirl\/openthread,erja-gp\/openthread,LeZhang2016\/openthread,pvanhorn\/openthread,georgecpr\/openthread,pvanhorn\/openthread,erja-gp\/openthread,xiaom-GitHub\/openthread,mszczodrak\/openthread,librasungirl\/openthread,chshu\/openthread,librasungirl\/openthread,mszczodrak\/openthread,openthread\/openthread,lanyuwen\/openthread,pvanhorn\/openthread,bukepo\/openthread,georgecpr\/openthread,abtink\/openthread,lanyuwen\/openthread,librasungirl\/openthread,pvanhorn\/openthread,xiaom-GitHub\/openthread,abtink\/openthread,mszczodrak\/openthread,xiaom-GitHub\/openthread,gandreello\/openthread,bukepo\/openthread,turon\/openthread,gandreello\/openthread,srickardti\/openthread,georgecpr\/openthread,chshu\/openthread,jwhui\/openthread,openthread\/openthread,chshu\/openthread,erja-gp\/openthread,erja-gp\/openthread,georgecpr\/openthread,jwhui\/openthread,abtink\/openthread,erja-gp\/openthread,turon\/openthread,bukepo\/openthread,lanyuwen\/openthread,xiaom-GitHub\/openthread","old_file":"third_party\/microchip\/include\/samr21x18a.ld","new_file":"third_party\/microchip\/include\/samr21x18a.ld","new_contents":"\/**\n * \\file\n *\n * \\brief Linker script for running in internal FLASH on the SAMR21x18A\n *\n * Copyright (c) 2015 Atmel Corporation. All rights reserved.\n *\n * \\asf_license_start\n *\n * \\page License\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n *    this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n *    this list of conditions and the following disclaimer in the documentation\n *    and\/or other materials provided with the distribution.\n *\n * 3. The name of Atmel may not be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * 4. This software may only be redistributed and used in connection with an\n *    Atmel microcontroller product.\n *\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n * \\asf_license_stop\n *\n *\/\n\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000\n  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n\n\t\tFILL(0xFF)\n        \/* PDS NV memory section *\/\n        . = ALIGN(0x100);\n        PROVIDE(__d_nv_mem_start = .);\n        . += ALIGN(0x1000); \/* Size of D_Nv memory section is 0x1000 i.e., 4KB *\/\n        PROVIDE(__d_nv_mem_end = .);\n\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack_dummy (NOLOAD):\n    {\n        KEEP(*(.stack*))\n    } > ram\n\n    _sstack = _ebss;\n    _estack = ORIGIN(ram) + LENGTH(ram);\n\n    ASSERT(_sstack < _estack, \"region RAM overflowed with stack\")\n\n    . = ALIGN(4);\n    _end = . ;\n    end = _end;\n}\n","old_contents":"\/**\n * \\file\n *\n * \\brief Linker script for running in internal FLASH on the SAMR21x18A\n *\n * Copyright (c) 2015 Atmel Corporation. All rights reserved.\n *\n * \\asf_license_start\n *\n * \\page License\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n *    this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n *    this list of conditions and the following disclaimer in the documentation\n *    and\/or other materials provided with the distribution.\n *\n * 3. The name of Atmel may not be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * 4. This software may only be redistributed and used in connection with an\n *    Atmel microcontroller product.\n *\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n * \\asf_license_stop\n *\n *\/\n\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* Memory Spaces Definitions *\/\nMEMORY\n{\n  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000\n  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000\n}\n\n\/* The stack size used by the application. NOTE: you need to adjust according to your application. *\/\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors .vectors.*))\n\n\t\tFILL(0xFF)\n        \/* PDS NV memory section *\/\n        . = ALIGN(0x100);\n        PROVIDE(__d_nv_mem_start = .);\n        . += ALIGN(0x1000); \/* Size of D_Nv memory section is 0x1000 i.e., 4KB *\/\n        PROVIDE(__d_nv_mem_end = .);\n\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    . = ALIGN(4);\n    _etext = .;\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        . = . + STACK_SIZE;\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    . = ALIGN(4);\n    _end = . ;\n    end = _end;\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"f5468d1192cbf6c097b8d507c43a2f13c07780a8","subject":"x86: add linker directives for 64-bit user mode","message":"x86: add linker directives for 64-bit user mode\n\nIncludes linker script fragments for the kernel object\ntables and automatic memory partitions. The data section\nis moved to the end per the requirements of\ninclude\/linker\/kobject.h.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/x86\/intel64\/linker.ld","new_file":"include\/arch\/x86\/intel64\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corp.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION RAM\n#define RAMABLE_REGION RAM\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\t\/*\n\t * The \"locore\" must be in the 64K of RAM, so that 16-bit code (with\n\t * segment registers == 0x0000) and 32\/64-bit code agree on addresses.\n\t * ... there is no 16-bit code yet, but there will be when we add SMP.\n\t *\/\n\n\t.locore 0x8000 : ALIGN(16)\n\t{\n\t_locore_start = .;\n\t*(.locore)\n\t*(.locore.*)\n\tMMU_PAGE_ALIGN\n\t_lorodata_start = .;\n\t*(.lorodata)\n\tMMU_PAGE_ALIGN\n\t_lodata_start = .;\n\t*(.tss)\n\t*(.lodata)\n\tMMU_PAGE_ALIGN\n\t_lodata_end = .;\n\t}\n\n\t_locore_size = _lorodata_start - _locore_start;\n\t_lorodata_size = _lodata_start - _lorodata_start;\n\t_lodata_size = _lodata_end - _lodata_start;\n\n\t\/*\n\t * The rest of the system is loaded in \"normal\" memory (typically\n\t * placed above 1MB to avoid the by memory hole at 0x90000-0xFFFFF).\n\t *\/\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_rom_start = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(.text.*)\n\n\t#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n\t#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t*(.rodata)\n\t*(.rodata.*)\n\n\t#include <snippets-rodata.ld>\n\n\t#ifdef CONFIG_CUSTOM_RODATA_LD\n\t#include <custom-rodata.ld>\n\t#endif \/* CONFIG_CUSTOM_RODATA_LD *\/\n\n#ifdef CONFIG_X86_MMU\n\t. = ALIGN(8);\n\t_mmu_region_list_start = .;\n\tKEEP(*(\"._mmu_region.static.*\"))\n\t_mmu_region_list_end = .;\n#endif \/* CONFIG_X86_MMU *\/\n\n\t#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\t_image_rom_end = .;\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\tMMU_PAGE_ALIGN\n#ifndef CONFIG_USERSPACE\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\t*(.bss)\n\t*(.bss.*)\n\t*(COMMON)\n\t. = ALIGN(4);\t\/* so __bss_num_dwords is exact *\/\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_dwords = (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t*(.noinit)\n\t*(.noinit.*)\n\t#include <snippets-noinit.ld>\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <snippets-sections.ld>\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n#include <custom-sections.ld>\n#endif \/* CONFIG_CUSTOM_SECTIONS_LD *\/\n\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t*(.data)\n\t*(.data.*)\n\t#include <snippets-rwdata.ld>\n\t#ifdef CONFIG_CUSTOM_RWDATA_LD\n\t#include <custom-rwdata.ld>\n\t#endif \/* CONFIG_CUSTOM_RWDATA_LD *\/\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <snippets-ram-sections.ld>\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n#include <linker\/kobject.ld>\n\n\t. = ALIGN(8);\n\tMMU_PAGE_ALIGN\n\t_image_ram_end = .;\n\t_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ :\n\t{\n\t*(.got)\n\t*(.got.plt)\n\t*(.igot)\n\t*(.igot.plt)\n\t*(.iplt)\n\t*(.plt)\n\t*(.note.GNU-stack)\n\t*(.rel.*)\n\t*(.rela.*)\n\t}\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corp.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define ROMABLE_REGION RAM\n#define RAMABLE_REGION RAM\n\n#ifdef CONFIG_X86_MMU\n\t#define MMU_PAGE_SIZE\tKB(4)\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\t\/*\n\t * The \"locore\" must be in the 64K of RAM, so that 16-bit code (with\n\t * segment registers == 0x0000) and 32\/64-bit code agree on addresses.\n\t * ... there is no 16-bit code yet, but there will be when we add SMP.\n\t *\/\n\n\t.locore 0x8000 : ALIGN(16)\n\t{\n\t_locore_start = .;\n\t*(.locore)\n\t*(.locore.*)\n\tMMU_PAGE_ALIGN\n\t_lorodata_start = .;\n\t*(.lorodata)\n\tMMU_PAGE_ALIGN\n\t_lodata_start = .;\n\t*(.tss)\n\t*(.lodata)\n\tMMU_PAGE_ALIGN\n\t_lodata_end = .;\n\t}\n\n\t_locore_size = _lorodata_start - _locore_start;\n\t_lorodata_size = _lodata_start - _lorodata_start;\n\t_lodata_size = _lodata_end - _lodata_start;\n\n\t\/*\n\t * The rest of the system is loaded in \"normal\" memory (typically\n\t * placed above 1MB to avoid the by memory hole at 0x90000-0xFFFFF).\n\t *\/\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(16))\n\t{\n\t_image_rom_start = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(.text.*)\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n\t#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(16))\n\t{\n\t*(.rodata)\n\t*(.rodata.*)\n\n\t#include <snippets-rodata.ld>\n\n\t#ifdef CONFIG_CUSTOM_RODATA_LD\n\t#include <custom-rodata.ld>\n\t#endif \/* CONFIG_CUSTOM_RODATA_LD *\/\n\n#ifdef CONFIG_X86_MMU\n\t. = ALIGN(8);\n\t_mmu_region_list_start = .;\n\tKEEP(*(\"._mmu_region.static.*\"))\n\t_mmu_region_list_end = .;\n#endif \/* CONFIG_X86_MMU *\/\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\t_image_rom_end = .;\n\n\tSECTION_PROLOGUE(_DATA_SECTION_NAME,,ALIGN(16))\n\t{\n\tMMU_PAGE_ALIGN\n\t_image_ram_start = .;\n\t__kernel_ram_start = .;\n\t*(.data)\n\t*(.data.*)\n\t#include <snippets-rwdata.ld>\n\t#ifdef CONFIG_CUSTOM_RWDATA_LD\n\t#include <custom-rwdata.ld>\n\t#endif \/* CONFIG_CUSTOM_RWDATA_LD *\/\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <snippets-ram-sections.ld>\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t__bss_start = .;\n\t*(.bss)\n\t*(.bss.*)\n\t*(COMMON)\n\t. = ALIGN(4);\t\/* so __bss_num_dwords is exact *\/\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_dwords = (__bss_end - __bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD), ALIGN(16))\n\t{\n\t*(.noinit)\n\t*(.noinit.*)\n\t#include <snippets-noinit.ld>\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <snippets-sections.ld>\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n#include <custom-sections.ld>\n#endif \/* CONFIG_CUSTOM_SECTIONS_LD *\/\n\n\t. = ALIGN(8);\n\t_image_ram_end = .;\n\t_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE);\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ :\n\t{\n\t*(.got)\n\t*(.got.plt)\n\t*(.igot)\n\t*(.igot.plt)\n\t*(.iplt)\n\t*(.plt)\n\t*(.note.GNU-stack)\n\t*(.rel.*)\n\t*(.rela.*)\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9036eee353ef169ee3f5a064d8e776507ff6084b","subject":"[rom_ext] Align .text section size to word boundary","message":"[rom_ext] Align .text section size to word boundary\n\nRequired because the .text section is used to define a PMP region\nand both the start and end of PMP regions must be word aligned.\n\nSigned-off-by: Michael Munday <19411bdeea90f848b8e02e9a1c63a7ce7cc699ea@lowrisc.org>\n","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan","old_file":"sw\/device\/silicon_creator\/rom_exts\/rom_ext_common.ld","new_file":"sw\/device\/silicon_creator\/rom_exts\/rom_ext_common.ld","new_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * NOTE:\n * This is an incomplete common portion of ROM_EXT linker file, and should not\n * be used directly. Instead it should be included by a top level ROM_EXT slot\n * linker file.\n *\/\n\nOUTPUT_ARCH(riscv)\nGROUP(-lgcc)\n\n\/**\n * Indicate that there are no dynamic libraries, whatsoever.\n *\/\n__DYNAMIC = 0;\n\n\/* DV Log offset (has to be different to other boot stages). *\/\n_dv_log_offset = 0x10000;\n\n\/**\n * Marking the entry point correctly for the ELF file. The signer tool will\n * transfer this value to the `entry_point` field of the manifest, which will\n * then be used by `mask_rom_boot` to handover execution to ROM_EXT.\n *\/\nENTRY(_rom_ext_start_boot)\n\n\/**\n * NOTE: We have to align each section to word boundaries as our current\n * s19->slm conversion scripts are not able to handle non-word aligned sections.\n *\/\nSECTIONS {\n  .manifest _slot_start_address : {\n    KEEP(*(.manifest))\n  } > eflash\n\n  \/**\n   * Ibex interrupt vector.\n   *\n   * This has to be set up at a 256-byte offset, so that we can use it with\n   * Ibex. This section includes the ROM_EXT entry address.\n   *\/\n  .vectors : ALIGN(256) {\n    KEEP(*(.vectors))\n  } > eflash\n\n  \/**\n   * C runtime (CRT) section, containing program initialization code.\n   *\n   * This is a separate section to `.text` so that the jumps inside `.vectors`\n   * will fit into the instruction encoding.\n   *\/\n  .crt : ALIGN(4) {\n    KEEP(*(.crt))\n  } > eflash\n\n  \/**\n   * Standard text section, containing program code.\n   *\/\n  .text : ALIGN(4) {\n    *(.text)\n    *(.text.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n  } > eflash\n\n  \/**\n   * Read-only data section, containing all large compile-time constants, like\n   * strings.\n   *\/\n  .rodata : ALIGN(4) {\n    \/* Small read-only data comes before regular read-only data for the same\n     * reasons as in the data section *\/\n    *(.srodata)\n    *(.srodata.*)\n    *(.rodata)\n    *(.rodata.*)\n  } > eflash\n\n  \/**\n   * Mutable data section, at the bottom of ram_main. This will be initialized\n   * from flash at runtime by the CRT.\n   *\n   * Load this by copying the bytes from [_data_init_start, _data_init_end] into\n   * the range [_data_start, _data_end].\n   *\/\n  .data ORIGIN(ram_main) : ALIGN(4) {\n    _data_start = .;\n    _data_init_start = LOADADDR(.data);\n\n    \/* This will get loaded into `gp`, and the linker will use that register for\n     * accessing data within [-2048,2047] of `__global_pointer$`.\n     *\n     * This is much cheaper (for small data) than materializing the\n     * address and loading from that (which will take one extra instruction).\n     *\/\n    __global_pointer$ = . + 2048;\n\n    \/* Small data should come before larger data. This helps to ensure small\n     * globals are within 2048 bytes of the value of `gp`, making their accesses\n     * hopefully only take one instruction. *\/\n    *(.sdata)\n    *(.sdata.*)\n\n    \/* Other data will likely need multiple instructions to load, so we're less\n     * concerned about address materialisation taking more than one instruction.\n     *\/\n    *(.data)\n    *(.data.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n    _data_end = .;\n    _data_init_end = LOADADDR(.data) + SIZEOF(.data);\n\n    \/* This puts it in ram_main at runtime (for the VMA), but puts the section\n     * into flash for load time (for the LMA). This is why `_data_init_*` uses\n     * `LOADADDR`.\n     *\n     * Using `AT>` means we don't have to keep track of the next free part of\n     * flash, as we do in our other linker scripts. *\/\n  } > ram_main AT> eflash\n\n  \/**\n   * Standard BSS section. This will be zeroed at runtime by the CRT.\n   *\/\n  .bss : ALIGN(4) {\n    _bss_start = .;\n\n    \/* Small BSS comes before regular BSS for the same reasons as in the data\n     * section *\/\n    *(.sbss)\n    *(.sbss.*)\n    *(.bss)\n    *(.bss.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n    _bss_end = .;\n  } > ram_main\n\n  INCLUDE sw\/device\/info_sections.ld\n}\n","old_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * NOTE:\n * This is an incomplete common portion of ROM_EXT linker file, and should not\n * be used directly. Instead it should be included by a top level ROM_EXT slot\n * linker file.\n *\/\n\nOUTPUT_ARCH(riscv)\nGROUP(-lgcc)\n\n\/**\n * Indicate that there are no dynamic libraries, whatsoever.\n *\/\n__DYNAMIC = 0;\n\n\/* DV Log offset (has to be different to other boot stages). *\/\n_dv_log_offset = 0x10000;\n\n\/**\n * Marking the entry point correctly for the ELF file. The signer tool will\n * transfer this value to the `entry_point` field of the manifest, which will\n * then be used by `mask_rom_boot` to handover execution to ROM_EXT.\n *\/\nENTRY(_rom_ext_start_boot)\n\n\/**\n * NOTE: We have to align each section to word boundaries as our current\n * s19->slm conversion scripts are not able to handle non-word aligned sections.\n *\/\nSECTIONS {\n  .manifest _slot_start_address : {\n    KEEP(*(.manifest))\n  } > eflash\n\n  \/**\n   * Ibex interrupt vector.\n   *\n   * This has to be set up at a 256-byte offset, so that we can use it with\n   * Ibex. This section includes the ROM_EXT entry address.\n   *\/\n  .vectors : ALIGN(256) {\n    KEEP(*(.vectors))\n  } > eflash\n\n  \/**\n   * C runtime (CRT) section, containing program initialization code.\n   *\n   * This is a separate section to `.text` so that the jumps inside `.vectors`\n   * will fit into the instruction encoding.\n   *\/\n  .crt : ALIGN(4) {\n    KEEP(*(.crt))\n  } > eflash\n\n  \/**\n   * Standard text section, containing program code.\n   *\/\n  .text : ALIGN(4) {\n    *(.text)\n    *(.text.*)\n  } > eflash\n\n  \/**\n   * Read-only data section, containing all large compile-time constants, like\n   * strings.\n   *\/\n  .rodata : ALIGN(4) {\n    \/* Small read-only data comes before regular read-only data for the same\n     * reasons as in the data section *\/\n    *(.srodata)\n    *(.srodata.*)\n    *(.rodata)\n    *(.rodata.*)\n  } > eflash\n\n  \/**\n   * Mutable data section, at the bottom of ram_main. This will be initialized\n   * from flash at runtime by the CRT.\n   *\n   * Load this by copying the bytes from [_data_init_start, _data_init_end] into\n   * the range [_data_start, _data_end].\n   *\/\n  .data ORIGIN(ram_main) : ALIGN(4) {\n    _data_start = .;\n    _data_init_start = LOADADDR(.data);\n\n    \/* This will get loaded into `gp`, and the linker will use that register for\n     * accessing data within [-2048,2047] of `__global_pointer$`.\n     *\n     * This is much cheaper (for small data) than materializing the\n     * address and loading from that (which will take one extra instruction).\n     *\/\n    __global_pointer$ = . + 2048;\n\n    \/* Small data should come before larger data. This helps to ensure small\n     * globals are within 2048 bytes of the value of `gp`, making their accesses\n     * hopefully only take one instruction. *\/\n    *(.sdata)\n    *(.sdata.*)\n\n    \/* Other data will likely need multiple instructions to load, so we're less\n     * concerned about address materialisation taking more than one instruction.\n     *\/\n    *(.data)\n    *(.data.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n    _data_end = .;\n    _data_init_end = LOADADDR(.data) + SIZEOF(.data);\n\n    \/* This puts it in ram_main at runtime (for the VMA), but puts the section\n     * into flash for load time (for the LMA). This is why `_data_init_*` uses\n     * `LOADADDR`.\n     *\n     * Using `AT>` means we don't have to keep track of the next free part of\n     * flash, as we do in our other linker scripts. *\/\n  } > ram_main AT> eflash\n\n  \/**\n   * Standard BSS section. This will be zeroed at runtime by the CRT.\n   *\/\n  .bss : ALIGN(4) {\n    _bss_start = .;\n\n    \/* Small BSS comes before regular BSS for the same reasons as in the data\n     * section *\/\n    *(.sbss)\n    *(.sbss.*)\n    *(.bss)\n    *(.bss.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n    _bss_end = .;\n  } > ram_main\n\n  INCLUDE sw\/device\/info_sections.ld\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"03f951c4f6f8f174c0487ce30a88cc7f12d39958","subject":"arch: arm: cortex_r: Move kobject text","message":"arch: arm: cortex_r: Move kobject text\n\nMove the kobject text area to be at the beginning of the text section to\nmatch Cortex-M.\n\nSigned-off-by: Bradley Bolen <a46f022a58b40f08f87b914d58da7dec46dba40c@lexmark.com>\n","repos":"galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_a_r\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_a_r\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A and Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n    _image_rom_start = ROM_ADDR;\n#else\n    _image_rom_start = RAM_ADDR;\n#endif\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n\n#include <linker\/kobject-text.ld>\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n#include <linker\/cplusplus-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n\n        \/*\n         * RODATA must be the last section so that the size of the entire read\n         * only area will be filled to a power of 2.\n         *\/\n        MPU_ALIGN(ABSOLUTE(.) - _image_rom_start);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_end = .;\n    _image_rom_end = .;\n    _image_rom_end_order = (LOG2CEIL(_image_rom_end) - 1) << 1;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A and Cortex-R platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN(1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n#if defined(CONFIG_XIP)\n    _image_rom_start = ROM_ADDR;\n#else\n    _image_rom_start = RAM_ADDR;\n#endif\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n#include <linker\/cplusplus-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n\n        \/*\n         * RODATA must be the last section so that the size of the entire read\n         * only area will be filled to a power of 2.\n         *\/\n        MPU_ALIGN(ABSOLUTE(.) - _image_rom_start);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rodata_end = .;\n    _image_rom_end = .;\n    _image_rom_end_order = (LOG2CEIL(_image_rom_end) - 1) << 1;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n         *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7acec6e317e3515528b41fabebaae409a6cbcb88","subject":"Make more room for the kernel. Useful for when there are lots of debugging messages.","message":"Make more room for the kernel. Useful for when there are lots\nof debugging messages.\n","repos":"google\/tock-on-titan,google\/tock-on-titan,google\/tock-on-titan","old_file":"golf2\/chip_layout.ld","new_file":"golf2\/chip_layout.ld","new_contents":"\/* Copyright 2018 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nMEMORY\n{\n  rom (rx)     : ORIGIN = 0x00044400, LENGTH = 0x00021c00\n  prog (rx)    : ORIGIN = 0x00076000, LENGTH = 0x00010000\n  ram (rwx)    : ORIGIN = 0x00010000, LENGTH = 0x00004000\n  appram (rwx) : ORIGIN = 0x00014000, LENGTH = 0x0000c000\n}\n\nMPU_MIN_ALIGN = 8K;\n","old_contents":"\/* Copyright 2018 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\nMEMORY\n{\n  rom (rx)     : ORIGIN = 0x00044400, LENGTH = 0x00021c00\n  prog (rx)    : ORIGIN = 0x00066000, LENGTH = 0x00020000\n  ram (rwx)    : ORIGIN = 0x00010000, LENGTH = 0x00004000\n  appram (rwx) : ORIGIN = 0x00014000, LENGTH = 0x0000c000\n}\n\nMPU_MIN_ALIGN = 8K;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"fc42c82cb9ab9cde82972c614e6b5294c9c6a8c3","subject":"soc: intel_s1000: define default MEMCTL reg value","message":"soc: intel_s1000: define default MEMCTL reg value\n\nWhen not using XCC, XCHAL_CACHE_MEMCTL_DEFAULT is not defined\nwhich results in some variables not being able to be defined.\nSo define them.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr","old_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <generated_dts_board.h>\n#include \"memory.h\"\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#define LPRAM_REGION lpram\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LPRAM_BASE,\n\tlen = LPRAM_SIZE\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nPROVIDE(__memctl_default = 0xFFFFFF00);\nPROVIDE(_MemErrorHandler = 0xFFFFFF00);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-through\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-through\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_s1000 = 0x1212fff2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    . = CONFIG_TEXT_SECTION_OFFSET;\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LPRAM_REGION\n  _heap_sentry = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <generated_dts_board.h>\n#include \"memory.h\"\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#define LPRAM_REGION lpram\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LPRAM_BASE,\n\tlen = LPRAM_SIZE\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-through\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-through\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_s1000 = 0x1212fff2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    . = CONFIG_TEXT_SECTION_OFFSET;\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LPRAM_REGION\n  _heap_sentry = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f7ce62aa7bd38281f4c628783cbea131106b38eb","subject":"added __ text label to stm32f0xx linker script for OS_CRASH_STACKTRACE and alike","message":"added __ text label to stm32f0xx linker script for OS_CRASH_STACKTRACE\nand alike\n","repos":"mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core","old_file":"hw\/mcu\/stm\/stm32f0xx\/stm32f0xx.ld","new_file":"hw\/mcu\/stm\/stm32f0xx\/stm32f0xx.ld","new_contents":"\/*\r\n * Licensed to the Apache Software Foundation (ASF) under one\r\n * or more contributor license agreements.  See the NOTICE file\r\n * distributed with this work for additional information\r\n * regarding copyright ownership.  The ASF licenses this file\r\n * to you under the Apache License, Version 2.0 (the\r\n * \"License\"); you may not use this file except in compliance\r\n * with the License.  You may obtain a copy of the License at\r\n *\r\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing,\r\n * software distributed under the License is distributed on an\r\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\r\n * KIND, either express or implied.  See the License for the\r\n * specific language governing permissions and limitations\r\n * under the License.\r\n *\/\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapBase\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __coredata_start__\r\n *   __coredata_end__\r\n *   __corebss_start__\r\n *   __corebss_end__\r\n *   __ecoredata\r\n *   __ecorebss\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\n_estack = ORIGIN(RAM) + LENGTH(RAM);\r\n\r\nSECTIONS\r\n{\r\n    \/* Reserve space at the start of the image for the header. *\/\r\n    .imghdr (NOLOAD):\r\n    {\r\n        . = . + _imghdr_size;\r\n    } > FLASH\r\n\r\n    __text = .;\r\n\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        __isr_vector_start = .;\r\n        KEEP(*(.isr_vector))\r\n        __isr_vector_end = .;\r\n        *(.text*)\r\n\r\n        KEEP(*(.init))\r\n        KEEP(*(.fini))\r\n\r\n        \/* .ctors *\/\r\n        *crtbegin.o(.ctors)\r\n        *crtbegin?.o(.ctors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n        *(SORT(.ctors.*))\r\n        *(.ctors)\r\n\r\n        \/* .dtors *\/\r\n        *crtbegin.o(.dtors)\r\n        *crtbegin?.o(.dtors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n        *(SORT(.dtors.*))\r\n        *(.dtors)\r\n\r\n        *(.rodata*)\r\n\r\n        KEEP(*(.eh_frame*))\r\n    } > FLASH\r\n\r\n    .ARM.extab :\r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > FLASH\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx :\r\n    {\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n\r\n    __exidx_end = .;\r\n\r\n    __etext = .;\r\n\r\n    .vector_relocation :\r\n    {\r\n        . = ALIGN(4);\r\n        __vector_tbl_reloc__ = .;\r\n        . = . + (__isr_vector_end - __isr_vector_start);\r\n        . = ALIGN(4);\r\n    } > RAM\r\n\r\n    .coredata :\r\n    {\r\n        . = ALIGN(4);\r\n        __coredata_start__ = .;\r\n        *(.data.core)\r\n        __coredata_end__ = .;\r\n    } > RAM AT > FLASH\r\n\r\n    __ecoredata = __etext + SIZEOF(.coredata);\r\n\r\n    _sidata = LOADADDR(.data);\r\n\r\n    .data :\r\n    {\r\n        . = ALIGN(4);\r\n        _sdata = .;\r\n        __data_start__ = _sdata;\r\n        *(vtable)\r\n        *(.data*)\r\n\r\n        \/* preinit data *\/\r\n        PROVIDE_HIDDEN (__preinit_array_start = .);\r\n        KEEP(*(.preinit_array))\r\n        PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* init data *\/\r\n        PROVIDE_HIDDEN (__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n        \/* finit data *\/\r\n        PROVIDE_HIDDEN (__fini_array_start = .);\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        KEEP(*(.fini_array))\r\n        PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* All data end *\/\r\n        _edata = .;\r\n        __data_end__ = _edata;\r\n\r\n    } > RAM AT > FLASH\r\n\r\n    .corebss (NOLOAD):\r\n    {\r\n        . = ALIGN(4);\r\n        __corebss_start__ = .;\r\n        *(.bss.core)\r\n        . = ALIGN(4);\r\n        __corebss_end__ = .;\r\n        *(.corebss*)\r\n        *(.bss.core.nz)\r\n        . = ALIGN(4);\r\n        __ecorebss = .;\r\n    } > RAM\r\n\r\n    .bss :\r\n    {\r\n        . = ALIGN(4);\r\n        _sbss = .;\r\n        __bss_start__ = _sbss;\r\n        *(.bss*)\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _ebss = .;\r\n        __bss_end__ = _ebss;\r\n    } > RAM\r\n\r\n    . = ALIGN(8);\r\n    __HeapBase = .;\r\n    __HeapLimit = ORIGIN(RAM) + LENGTH(RAM);\r\n\r\n    _ram_start = ORIGIN(RAM);\r\n\r\n    \/* .stack_dummy section doesn't contains any symbols. It is only\r\n     * used for linker to calculate size of stack sections, and assign\r\n     * values to stack symbols later *\/\r\n    .stack_dummy (COPY):\r\n    {\r\n        *(.stack*)\r\n    } > RAM\r\n\r\n    \/* Set stack top to end of RAM; stack limit is bottom of stack *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n    PROVIDE(__stack = __StackTop);\r\n}\r\n","old_contents":"\/*\r\n * Licensed to the Apache Software Foundation (ASF) under one\r\n * or more contributor license agreements.  See the NOTICE file\r\n * distributed with this work for additional information\r\n * regarding copyright ownership.  The ASF licenses this file\r\n * to you under the Apache License, Version 2.0 (the\r\n * \"License\"); you may not use this file except in compliance\r\n * with the License.  You may obtain a copy of the License at\r\n *\r\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing,\r\n * software distributed under the License is distributed on an\r\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\r\n * KIND, either express or implied.  See the License for the\r\n * specific language governing permissions and limitations\r\n * under the License.\r\n *\/\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapBase\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __coredata_start__\r\n *   __coredata_end__\r\n *   __corebss_start__\r\n *   __corebss_end__\r\n *   __ecoredata\r\n *   __ecorebss\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\n_estack = ORIGIN(RAM) + LENGTH(RAM);\r\n\r\nSECTIONS\r\n{\r\n    \/* Reserve space at the start of the image for the header. *\/\r\n    .imghdr (NOLOAD):\r\n    {\r\n        . = . + _imghdr_size;\r\n    } > FLASH\r\n\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        __isr_vector_start = .;\r\n        KEEP(*(.isr_vector))\r\n        __isr_vector_end = .;\r\n        *(.text*)\r\n\r\n        KEEP(*(.init))\r\n        KEEP(*(.fini))\r\n\r\n        \/* .ctors *\/\r\n        *crtbegin.o(.ctors)\r\n        *crtbegin?.o(.ctors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n        *(SORT(.ctors.*))\r\n        *(.ctors)\r\n\r\n        \/* .dtors *\/\r\n        *crtbegin.o(.dtors)\r\n        *crtbegin?.o(.dtors)\r\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n        *(SORT(.dtors.*))\r\n        *(.dtors)\r\n\r\n        *(.rodata*)\r\n\r\n        KEEP(*(.eh_frame*))\r\n    } > FLASH\r\n\r\n    .ARM.extab :\r\n    {\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n    } > FLASH\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx :\r\n    {\r\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n\r\n    __exidx_end = .;\r\n\r\n    __etext = .;\r\n\r\n    .vector_relocation :\r\n    {\r\n        . = ALIGN(4);\r\n        __vector_tbl_reloc__ = .;\r\n        . = . + (__isr_vector_end - __isr_vector_start);\r\n        . = ALIGN(4);\r\n    } > RAM\r\n\r\n    .coredata :\r\n    {\r\n        . = ALIGN(4);\r\n        __coredata_start__ = .;\r\n        *(.data.core)\r\n        __coredata_end__ = .;\r\n    } > RAM AT > FLASH\r\n\r\n    __ecoredata = __etext + SIZEOF(.coredata);\r\n\r\n    _sidata = LOADADDR(.data);\r\n\r\n    .data :\r\n    {\r\n        . = ALIGN(4);\r\n        _sdata = .;\r\n        __data_start__ = _sdata;\r\n        *(vtable)\r\n        *(.data*)\r\n\r\n        \/* preinit data *\/\r\n        PROVIDE_HIDDEN (__preinit_array_start = .);\r\n        KEEP(*(.preinit_array))\r\n        PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* init data *\/\r\n        PROVIDE_HIDDEN (__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n        \/* finit data *\/\r\n        PROVIDE_HIDDEN (__fini_array_start = .);\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        KEEP(*(.fini_array))\r\n        PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n        . = ALIGN(4);\r\n        \/* All data end *\/\r\n        _edata = .;\r\n        __data_end__ = _edata;\r\n\r\n    } > RAM AT > FLASH\r\n\r\n    .corebss (NOLOAD):\r\n    {\r\n        . = ALIGN(4);\r\n        __corebss_start__ = .;\r\n        *(.bss.core)\r\n        . = ALIGN(4);\r\n        __corebss_end__ = .;\r\n        *(.corebss*)\r\n        *(.bss.core.nz)\r\n        . = ALIGN(4);\r\n        __ecorebss = .;\r\n    } > RAM\r\n\r\n    .bss :\r\n    {\r\n        . = ALIGN(4);\r\n        _sbss = .;\r\n        __bss_start__ = _sbss;\r\n        *(.bss*)\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _ebss = .;\r\n        __bss_end__ = _ebss;\r\n    } > RAM\r\n\r\n    . = ALIGN(8);\r\n    __HeapBase = .;\r\n    __HeapLimit = ORIGIN(RAM) + LENGTH(RAM);\r\n\r\n    _ram_start = ORIGIN(RAM);\r\n\r\n    \/* .stack_dummy section doesn't contains any symbols. It is only\r\n     * used for linker to calculate size of stack sections, and assign\r\n     * values to stack symbols later *\/\r\n    .stack_dummy (COPY):\r\n    {\r\n        *(.stack*)\r\n    } > RAM\r\n\r\n    \/* Set stack top to end of RAM; stack limit is bottom of stack *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n    PROVIDE(__stack = __StackTop);\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5b3ca0d2f7b5f425ba1a14db8ce98b8d95a2f89f","subject":"Fix a broken file header on ia32","message":"Fix a broken file header on ia32\n\nCommit c6281c6a195edee61185 needs to have included a \". = ALIGN(4096)\"\ndirective before .reloc, but fails to do so.\n\nAs a result, binutils, which does not care about the actual binary\nformat's constraints in any way, does not enforce the section alignment,\nand it will not load.\n\nSigned-off-by: Peter Jones <2e0a021e603479ff81838c00c3b770daca4e0214@redhat.com>\n","repos":"rhinstaller\/shim,rhinstaller\/shim,rhinstaller\/shim","old_file":"elf_ia32_efi.lds","new_file":"elf_ia32_efi.lds","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSECTIONS\n{\n  . = 0;\n  ImageBase = .;\n  .hash : { *(.hash) }\t\/* this MUST come first! *\/\n  . = ALIGN(4096);\n  .text :\n  {\n   _text = .;\n   *(.text)\n   *(.text.*)\n   *(.gnu.linkonce.t.*)\n   _etext = .;\n  }\n  . = ALIGN(4096);\n  .reloc :\n  {\n   *(.reloc)\n  }\n  . = ALIGN(4096);\n  .note.gnu.build-id : {\n    *(.note.gnu.build-id)\n  }\n  . = ALIGN(4096);\n  .data.ident : {\n    *(.data.ident)\n  }\n\n  . = ALIGN(4096);\n  .data :\n  {\n   _data = .;\n   *(.rodata*)\n   *(.data)\n   *(.data1)\n   *(.data.*)\n   *(.sdata)\n   *(.got.plt)\n   *(.got)\n   \/* the EFI loader doesn't seem to like a .bss section, so we stick\n      it all into .data: *\/\n   *(.sbss)\n   *(.scommon)\n   *(.dynbss)\n   *(.bss)\n   *(COMMON)\n  }\n\n  . = ALIGN(4096);\n  .vendor_cert :\n  {\n   *(.vendor_cert)\n  }\n  . = ALIGN(4096);\n  .dynamic  : { *(.dynamic) }\n  . = ALIGN(4096);\n  .rel :\n  {\n    *(.rel.data)\n    *(.rel.data.*)\n    *(.rel.got)\n    *(.rel.stab)\n    *(.data.rel.ro.local)\n    *(.data.rel.local)\n    *(.data.rel.ro)\n    *(.data.rel*)\n  }\n  _edata = .;\n  _data_size = . - _data;\n  . = ALIGN(4096);\n  .sbat :\n  {\n    _sbat = .;\n    *(.sbat)\n    *(.sbat.*)\n  }\n  _esbat = .;\n  _sbat_size = . - _sbat;\n\n  . = ALIGN(4096);\n  .dynsym   : { *(.dynsym) }\n  . = ALIGN(4096);\n  .dynstr   : { *(.dynstr) }\n  . = ALIGN(4096);\n  \/DISCARD\/ :\n  {\n    *(.rel.reloc)\n    *(.eh_frame)\n    *(.note.GNU-stack)\n  }\n  .comment 0 : { *(.comment) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSECTIONS\n{\n  . = 0;\n  ImageBase = .;\n  .hash : { *(.hash) }\t\/* this MUST come first! *\/\n  . = ALIGN(4096);\n  .text :\n  {\n   _text = .;\n   *(.text)\n   *(.text.*)\n   *(.gnu.linkonce.t.*)\n   _etext = .;\n  }\n  .reloc :\n  {\n   *(.reloc)\n  }\n  . = ALIGN(4096);\n  .note.gnu.build-id : {\n    *(.note.gnu.build-id)\n  }\n  . = ALIGN(4096);\n  .data.ident : {\n    *(.data.ident)\n  }\n\n  . = ALIGN(4096);\n  .data :\n  {\n   _data = .;\n   *(.rodata*)\n   *(.data)\n   *(.data1)\n   *(.data.*)\n   *(.sdata)\n   *(.got.plt)\n   *(.got)\n   \/* the EFI loader doesn't seem to like a .bss section, so we stick\n      it all into .data: *\/\n   *(.sbss)\n   *(.scommon)\n   *(.dynbss)\n   *(.bss)\n   *(COMMON)\n  }\n\n  . = ALIGN(4096);\n  .vendor_cert :\n  {\n   *(.vendor_cert)\n  }\n  . = ALIGN(4096);\n  .dynamic  : { *(.dynamic) }\n  . = ALIGN(4096);\n  .rel :\n  {\n    *(.rel.data)\n    *(.rel.data.*)\n    *(.rel.got)\n    *(.rel.stab)\n    *(.data.rel.ro.local)\n    *(.data.rel.local)\n    *(.data.rel.ro)\n    *(.data.rel*)\n  }\n  _edata = .;\n  _data_size = . - _data;\n  . = ALIGN(4096);\n  .sbat :\n  {\n    _sbat = .;\n    *(.sbat)\n    *(.sbat.*)\n  }\n  _esbat = .;\n  _sbat_size = . - _sbat;\n\n  . = ALIGN(4096);\n  .dynsym   : { *(.dynsym) }\n  . = ALIGN(4096);\n  .dynstr   : { *(.dynstr) }\n  . = ALIGN(4096);\n  \/DISCARD\/ :\n  {\n    *(.rel.reloc)\n    *(.eh_frame)\n    *(.note.GNU-stack)\n  }\n  .comment 0 : { *(.comment) }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"001cb79471c87d923c81771e551c81130522bb42","subject":"AT91SAM7A3. Fixed RAM size in linker script.","message":"AT91SAM7A3. Fixed RAM size in linker script.\n\ngit-svn-id: 30f789d7039adee4ab6dc5f7dbec2df9251e516b@4880 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"os\/ports\/GCC\/ARM\/AT91SAM7\/ld\/AT91SAM7A3.ld","new_file":"os\/ports\/GCC\/ARM\/AT91SAM7\/ld\/AT91SAM7A3.ld","new_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011,2012 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * AT91SAM7X256 memory setup.\r\n *\/\r\n__und_stack_size__\t= 0x0004;\r\n__abt_stack_size__\t= 0x0004;\r\n__fiq_stack_size__\t= 0x0010;\r\n__irq_stack_size__\t= 0x0080;\r\n__svc_stack_size__\t= 0x0004;\r\n__sys_stack_size__\t= 0x0400;\r\n__stacks_total_size__\t= __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x100000, len = 256k\r\n    ram : org = 0x200020, len = 32k - 0x20\r\n}\r\n\r\n__ram_start__\t\t= ORIGIN(ram);\r\n__ram_size__\t\t= LENGTH(ram);\r\n__ram_end__\t\t= __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n\t. = 0;\r\n\r\n\t.text : ALIGN(16) SUBALIGN(16)\r\n\t{\r\n        _text = .;\r\n        KEEP(*(vectors))\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n        *(.ctors)\r\n        *(.dtors)\r\n    } > flash\r\n\r\n    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash\r\n    __exidx_end = .;\r\n\r\n    .eh_frame_hdr : {*(.eh_frame_hdr)}\r\n\r\n    .eh_frame : ONLY_IF_RO {*(.eh_frame)}\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .data :\r\n    {\r\n        _data = .;\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        _edata = .;\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        _bss_start = .;\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _bss_end = .;\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end = .;\r\n\r\n__heap_base__              = _end;\r\n__heap_end__               = __ram_end__ - __stacks_total_size__;\r\n__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__;\r\n","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011,2012 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * AT91SAM7X256 memory setup.\r\n *\/\r\n__und_stack_size__\t= 0x0004;\r\n__abt_stack_size__\t= 0x0004;\r\n__fiq_stack_size__\t= 0x0010;\r\n__irq_stack_size__\t= 0x0080;\r\n__svc_stack_size__\t= 0x0004;\r\n__sys_stack_size__\t= 0x0400;\r\n__stacks_total_size__\t= __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x100000, len = 256k\r\n    ram : org = 0x200020, len = 64k - 0x20\r\n}\r\n\r\n__ram_start__\t\t= ORIGIN(ram);\r\n__ram_size__\t\t= LENGTH(ram);\r\n__ram_end__\t\t= __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n\t. = 0;\r\n\r\n\t.text : ALIGN(16) SUBALIGN(16)\r\n\t{\r\n        _text = .;\r\n        KEEP(*(vectors))\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n        *(.ctors)\r\n        *(.dtors)\r\n    } > flash\r\n\r\n    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash\r\n    __exidx_end = .;\r\n\r\n    .eh_frame_hdr : {*(.eh_frame_hdr)}\r\n\r\n    .eh_frame : ONLY_IF_RO {*(.eh_frame)}\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .data :\r\n    {\r\n        _data = .;\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        _edata = .;\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        _bss_start = .;\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _bss_end = .;\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end = .;\r\n\r\n__heap_base__              = _end;\r\n__heap_end__               = __ram_end__ - __stacks_total_size__;\r\n__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__;\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d7a18ae0c161703a96cfbaf2174c511dd8578121","subject":"changed alignment in boot.ld","message":"changed alignment in boot.ld\n","repos":"ManyThreads\/mythos,ManyThreads\/mythos","old_file":"kernel\/boot\/kernel-amd64-ihk\/boot\/boot.ld","new_file":"kernel\/boot\/kernel-amd64-ihk\/boot\/boot.ld","new_contents":"\/* MIT License -- MyThOS: The Many-Threads Operating System\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without\n * restriction, including without limitation the rights to use, copy,\n * modify, merge, publish, distribute, sublicense, and\/or sell copies\n * of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\n * Copyright 2014 Randolf Rotta, Maik Kr\u00fcger, and contributors, BTU Cottbus-Senftenberg\n *\/\n#include \"boot\/memory-layout.h\"\n\nENTRY(_start_ihk_mythos_)\n\n\/** ELF programm header for the loader.\n *\n * See ftp:\/\/ftp.gnu.org\/old-gnu\/Manuals\/ld-2.9.1\/html_node\/ld_23.html\n * and the ELF ABI defines how this shall be interpreted.\n *\n * Two sections init and kern are defined with type PT_LOAD.\n * PT_LOAD indicates that this segment should be loaded from the file.\n * The sections below are assigned to segments by \":name\" at the\n * end of the section description.\n *\/\nPHDRS\n{\n    kern PT_LOAD;\n    data PT_LOAD;\n}\n\nSECTIONS\n{\n    \/* All following sections will be placed into the upper half\n    kernel address range. Thus, the Virtual Memory Address VMA will be\n    large. But the Load Memory Address LMA has to be in physical addresses still. *\/\n    . = VIRT_ADDR;\n    .text : {\n        *(.text.hot .text.hot.*)\n        *(\".text\" \".text$\" .text .text.* .gnu.linkonce.t.*)\n    } : kern\n\n    .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n    .eh_frame : { *(.eh_frame) }\n    .fixup : { FIXUP_START = .; *(.fixup); FIXUP_END = .; }\n\n    .init_array : {\n      CTORS_START = .;\n      KEEP(*(SORT(.init_array.*)))\n      KEEP(*(.init_array))\n      KEEP(*(SORT(.ctors.*)))\n      KEEP(*(.ctors))\n      CTORS_END = .;\n    }\n\n    . = ALIGN(4096); \/* page aligned *\/\n    \/*PROVIDE (KERN_ROEND = . - VIRT_ADDR);*\/\n\n    .data : {\n      *(.data .data.* .gnu.linkonce.d.*)\n      . = ALIGN(64); \/* cache line aligned *\/\n      CLM_ADDR = .;\n      *(SORT_BY_ALIGNMENT(.kernel_clm.hot))\n      *(SORT_BY_ALIGNMENT(.kernel_clm))\n      . = ALIGN(64); \/* cache line aligned *\/\n      CLM_BLOCKEND = .;\n    } : data\n\n    .bss : {\n      . += MYTHOS_MAX_THREADS*(CLM_BLOCKEND - CLM_ADDR);\n      CLM_END = .;\n      *(.bss .bss.* .gnu.linkonce.b.*)\n    }\n\n    . = ALIGN(4096); \/* page aligned *\/\n    PROVIDE (VIRT_END = .);\n    . += 4096 * 20; \n    . = ALIGN(2M); \/* page aligned *\/\n    PROVIDE (KERN_END = . - VIRT_ADDR); \/* to make kmem-common.h happy *\/\n    PROVIDE (KERN_SIZE = . - VIRT_ADDR); \/* the kernel SIZE (not physical end of the upper half stuff) *\/\n\n    \/DISCARD\/ :\n    {\n        *(.note.GNU-stack)\n        *(.comment*)\n    }\n}\n","old_contents":"\/* MIT License -- MyThOS: The Many-Threads Operating System\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without\n * restriction, including without limitation the rights to use, copy,\n * modify, merge, publish, distribute, sublicense, and\/or sell copies\n * of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\n * Copyright 2014 Randolf Rotta, Maik Kr\u00fcger, and contributors, BTU Cottbus-Senftenberg\n *\/\n#include \"boot\/memory-layout.h\"\n\nENTRY(_start_ihk_mythos_)\n\n\/** ELF programm header for the loader.\n *\n * See ftp:\/\/ftp.gnu.org\/old-gnu\/Manuals\/ld-2.9.1\/html_node\/ld_23.html\n * and the ELF ABI defines how this shall be interpreted.\n *\n * Two sections init and kern are defined with type PT_LOAD.\n * PT_LOAD indicates that this segment should be loaded from the file.\n * The sections below are assigned to segments by \":name\" at the\n * end of the section description.\n *\/\nPHDRS\n{\n    kern PT_LOAD;\n    data PT_LOAD;\n}\n\nSECTIONS\n{\n    \/* All following sections will be placed into the upper half\n    kernel address range. Thus, the Virtual Memory Address VMA will be\n    large. But the Load Memory Address LMA has to be in physical addresses still. *\/\n    . = VIRT_ADDR;\n    .text : {\n        *(.text.hot .text.hot.*)\n        *(\".text\" \".text$\" .text .text.* .gnu.linkonce.t.*)\n    } : kern\n\n    .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n    .eh_frame : { *(.eh_frame) }\n    .fixup : { FIXUP_START = .; *(.fixup); FIXUP_END = .; }\n\n    .init_array : {\n      CTORS_START = .;\n      KEEP(*(SORT(.init_array.*)))\n      KEEP(*(.init_array))\n      KEEP(*(SORT(.ctors.*)))\n      KEEP(*(.ctors))\n      CTORS_END = .;\n    }\n\n    . = ALIGN(2M); \/* page aligned *\/\n    \/*PROVIDE (KERN_ROEND = . - VIRT_ADDR);*\/\n\n    .data : {\n      *(.data .data.* .gnu.linkonce.d.*)\n      . = ALIGN(64); \/* cache line aligned *\/\n      CLM_ADDR = .;\n      *(SORT_BY_ALIGNMENT(.kernel_clm.hot))\n      *(SORT_BY_ALIGNMENT(.kernel_clm))\n      . = ALIGN(64); \/* cache line aligned *\/\n      CLM_BLOCKEND = .;\n    } : data\n\n    .bss : {\n      . += MYTHOS_MAX_THREADS*(CLM_BLOCKEND - CLM_ADDR);\n      CLM_END = .;\n      *(.bss .bss.* .gnu.linkonce.b.*)\n    }\n\n    . = ALIGN(4096); \/* page aligned *\/\n    PROVIDE (VIRT_END = .);\n    . = ALIGN(2M); \/* page aligned *\/\n    PROVIDE (KERN_END = . - VIRT_ADDR); \/* to make kmem-common.h happy *\/\n    PROVIDE (KERN_SIZE = . - VIRT_ADDR); \/* the kernel SIZE (not physical end of the upper half stuff) *\/\n\n    \/DISCARD\/ :\n    {\n        *(.note.GNU-stack)\n        *(.comment*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4d2c36907fae03abf7bd36756b6ab4d41915a377","subject":"more ram required for softdevice","message":"more ram required for softdevice\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa.ld","new_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_s132_xxaa.ld","new_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\t\/* nRF52832 has 512KB Flash (0x80000), 64KB RAM (0x10000) *\/\r\n\r\n\tFLASH (rx) : ORIGIN = 0x26000, LENGTH = 0x5a000\r\n\tRAM (rwx) :  ORIGIN = 0x20003300, LENGTH = 0xCD00\r\n\r\n\t\/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n\t*  from application to bootloader when using buttonless DFU OTA.\r\n\t*\/\r\n\tNOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n\t\/** Location of bootloader setting in flash. *\/\r\n\tBOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n}\r\n\r\n\r\nSECTIONS\r\n{\r\n\t\/* Place the bootloader settings page in flash. *\/\r\n\t.bootloaderSettings(NOLOAD) :\r\n\t{\r\n\r\n\t} > BOOTLOADER_SETTINGS\r\n\r\n\t\/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n\t.noinit(NOLOAD) :\r\n\t{\r\n\r\n\t} > NOINIT\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.pwr_mgmt_data :\r\n\t{\r\n\t\tPROVIDE(__start_pwr_mgmt_data = .);\r\n\t\tKEEP(*(SORT(.pwr_mgmt_data*)))\r\n\t\tPROVIDE(__stop_pwr_mgmt_data = .);\r\n\t} > FLASH\r\n\t\r\n\t.log_const_data :\r\n\t{\r\n\t  \tPROVIDE(__start_log_const_data = .);\r\n\t  \tKEEP(*(.log_const_data))\r\n\t  \tPROVIDE(__stop_log_const_data = .);\r\n\t} > FLASH\r\n\t\r\n    .crypto_data :\r\n    {\r\n        PROVIDE(__start_crypto_data = .);\r\n        KEEP(*(SORT(.crypto_data*)))\r\n        PROVIDE(__stop_crypto_data = .);\r\n    } > FLASH\r\n\t\r\n\t.cli_command :\r\n\t{\r\n\t\tPROVIDE(__start_cli_command = .);\r\n\t\tKEEP(*(.cli_command))\r\n\t\tPROVIDE(__stop_cli_command = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_stack_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_stack_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_stack_observers*)))\r\n\t\tPROVIDE(__stop_sdh_stack_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_req_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_req_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_req_observers*)))\r\n\t\tPROVIDE(__stop_sdh_req_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_state_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_state_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_state_observers*)))\r\n\t\tPROVIDE(__stop_sdh_state_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_ant_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_ant_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_ant_observers*)))\r\n\t\tPROVIDE(__stop_sdh_ant_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_ble_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_ble_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_ble_observers*)))\r\n\t\tPROVIDE(__stop_sdh_ble_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_soc_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_soc_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_soc_observers*)))\r\n\t\tPROVIDE(__stop_sdh_soc_observers = .);\r\n\t} > FLASH\r\n    .nrf_queue :\r\n  {\r\n    PROVIDE(__start_nrf_queue = .);\r\n    KEEP(*(.nrf_queue))\r\n    PROVIDE(__stop_nrf_queue = .);\r\n  } > FLASH\r\n} INSERT AFTER .text\r\n\r\nSECTIONS\r\n{\r\n\t. = ALIGN(4);\r\n\t.svc_data :\r\n\t{\r\n\t\tPROVIDE(__start_svc_data = .);\r\n\t\tKEEP(*(.svc_data))\r\n\t\tPROVIDE(__stop_svc_data = .);\r\n\t} > RAM AT > FLASH\r\n\t\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n\t\r\n\t.log_dynamic_data :\r\n\t{\r\n\t\tPROVIDE(__start_log_dynamic_data = .);\r\n\t\tKEEP(*(.log_dynamic_data))\r\n\t\tPROVIDE(__stop_log_dynamic_data = .);\r\n\t} > RAM AT > FLASH\r\n\t.cli_sorted_cmd_ptrs :\r\n\t{\r\n\t\tPROVIDE(__start_cli_sorted_cmd_ptrs = .);\r\n\t\tKEEP(*(.cli_sorted_cmd_ptrs))\r\n\t\tPROVIDE(__stop_cli_sorted_cmd_ptrs = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","old_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/..\/..\/EHAL\/ARM\/Nordic\/nRF52\/CMSIS\/Release\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\t\/* nRF52832 has 512KB Flash (0x80000), 64KB RAM (0x10000) *\/\r\n\r\n\tFLASH (rx) : ORIGIN = 0x26000, LENGTH = 0x5a000\r\n\tRAM (rwx) :  ORIGIN = 0x20002b00, LENGTH = 0xD500\r\n\r\n\t\/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n\t*  from application to bootloader when using buttonless DFU OTA.\r\n\t*\/\r\n\tNOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n\t\/** Location of bootloader setting in flash. *\/\r\n\tBOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n}\r\n\r\n\r\nSECTIONS\r\n{\r\n\t\/* Place the bootloader settings page in flash. *\/\r\n\t.bootloaderSettings(NOLOAD) :\r\n\t{\r\n\r\n\t} > BOOTLOADER_SETTINGS\r\n\r\n\t\/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n\t.noinit(NOLOAD) :\r\n\t{\r\n\r\n\t} > NOINIT\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.pwr_mgmt_data :\r\n\t{\r\n\t\tPROVIDE(__start_pwr_mgmt_data = .);\r\n\t\tKEEP(*(SORT(.pwr_mgmt_data*)))\r\n\t\tPROVIDE(__stop_pwr_mgmt_data = .);\r\n\t} > FLASH\r\n\t\r\n\t.log_const_data :\r\n\t{\r\n\t  \tPROVIDE(__start_log_const_data = .);\r\n\t  \tKEEP(*(.log_const_data))\r\n\t  \tPROVIDE(__stop_log_const_data = .);\r\n\t} > FLASH\r\n\t\r\n    .crypto_data :\r\n    {\r\n        PROVIDE(__start_crypto_data = .);\r\n        KEEP(*(SORT(.crypto_data*)))\r\n        PROVIDE(__stop_crypto_data = .);\r\n    } > FLASH\r\n\t\r\n\t.cli_command :\r\n\t{\r\n\t\tPROVIDE(__start_cli_command = .);\r\n\t\tKEEP(*(.cli_command))\r\n\t\tPROVIDE(__stop_cli_command = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_stack_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_stack_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_stack_observers*)))\r\n\t\tPROVIDE(__stop_sdh_stack_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_req_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_req_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_req_observers*)))\r\n\t\tPROVIDE(__stop_sdh_req_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_state_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_state_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_state_observers*)))\r\n\t\tPROVIDE(__stop_sdh_state_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_ant_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_ant_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_ant_observers*)))\r\n\t\tPROVIDE(__stop_sdh_ant_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_ble_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_ble_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_ble_observers*)))\r\n\t\tPROVIDE(__stop_sdh_ble_observers = .);\r\n\t} > FLASH\r\n\t\r\n\t.sdh_soc_observers :\r\n\t{\r\n\t\tPROVIDE(__start_sdh_soc_observers = .);\r\n\t\tKEEP(*(SORT(.sdh_soc_observers*)))\r\n\t\tPROVIDE(__stop_sdh_soc_observers = .);\r\n\t} > FLASH\r\n    .nrf_queue :\r\n  {\r\n    PROVIDE(__start_nrf_queue = .);\r\n    KEEP(*(.nrf_queue))\r\n    PROVIDE(__stop_nrf_queue = .);\r\n  } > FLASH\r\n} INSERT AFTER .text\r\n\r\nSECTIONS\r\n{\r\n\t. = ALIGN(4);\r\n\t.svc_data :\r\n\t{\r\n\t\tPROVIDE(__start_svc_data = .);\r\n\t\tKEEP(*(.svc_data))\r\n\t\tPROVIDE(__stop_svc_data = .);\r\n\t} > RAM AT > FLASH\r\n\t\r\n\t.fs_data :\r\n\t{\r\n\t\tPROVIDE(__start_fs_data = .);\r\n\t\tKEEP(*(.fs_data))\r\n\t\tPROVIDE(__stop_fs_data = .);\r\n\t} > RAM AT > FLASH\r\n\t\r\n\t.log_dynamic_data :\r\n\t{\r\n\t\tPROVIDE(__start_log_dynamic_data = .);\r\n\t\tKEEP(*(.log_dynamic_data))\r\n\t\tPROVIDE(__stop_log_dynamic_data = .);\r\n\t} > RAM AT > FLASH\r\n\t.cli_sorted_cmd_ptrs :\r\n\t{\r\n\t\tPROVIDE(__start_cli_sorted_cmd_ptrs = .);\r\n\t\tKEEP(*(.cli_sorted_cmd_ptrs))\r\n\t\tPROVIDE(__stop_cli_sorted_cmd_ptrs = .);\r\n\t} > RAM AT > FLASH\r\n} INSERT AFTER .data;\r\n\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c30a012340314510d24c51b10fb8ea31e4095701","subject":"board: Add required symbols for newlib in linker script.","message":"board: Add required symbols for newlib in linker script.\n","repos":"ksejdak\/cosmos,ksejdak\/cosmos,ksejdak\/cosmos","old_file":"board\/beaglebone-black\/beaglebone-black.ld","new_file":"board\/beaglebone-black\/beaglebone-black.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nENTRY(_start)\n\nMEMORY {\n\tddr (rwx)      :      ORIGIN = 0x00000000, LENGTH = 512M                        \/* External DDR3 RAM *\/\n    sram (rwx)     :      ORIGIN = 0x402f0400, LENGTH = (0x402fffff - 0x402f0400)   \/* Internal on-chip SRAM *\/\n}\n\n_textStart_va        = 0x80000000;   \/* Kernel .text starts at 2 GB. *\/\n_pagePoolInitialSize = 0x1000;       \/* Preallocated page for page pool.*\/\n_stackSize           = 0x1000;       \/* Stack size is 4KB.*\/\n\nSECTIONS {\n\t\/* Static page pool. *\/\n\t.pagePool : ALIGN(4) {\n\t\t_pagePoolStart_pa = .;\n\n        . += _pagePoolInitialSize;\n\t} AT > sram = 0\n\n    \/* Starup code. *\/\n    .boot : {\n        _bootStart_pa = .;\n\n        *(.boot)\n\n        _bootEnd_pa = .;\n    } AT > sram\n\n    \/* Kernel code. *\/\n    .text : {\n        *(.text)                \/* .text sections (code). *\/\n        *(.text*)               \/* .text* sections (code). *\/\n        *(.glue_7)              \/* Glue ARM to Thumb code. *\/\n        *(.glue_7t)             \/* Glue Thumb to ARM code. *\/\n        *(.eh_frame)\n        KEEP (*(.init))\n        KEEP (*(.fini))\n    } AT > sram\n\n    \/* Memory regions provided for kernel. *\/\n    .memory_regions : ALIGN(4) {\n\t\t_memoryRegions_pa = .;\n\n\t\/*  Physical address    Total size          Used size *\/\n        LONG(ORIGIN(sram))  LONG(LENGTH(sram))  LONG(_heapStart_pa - ORIGIN(sram))\n        LONG(0)             LONG(0)             LONG(0)\n    } AT > sram\n\n    \/* Constructors and destructors. *\/\n\t.ctors : {\n\t\tKEEP (*crtbegin*.o(.ctors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t} AT > sram\n\n\t.dtors : {\n\t\tKEEP (*crtbegin*.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t} AT > sram\n\n    \/* Data. *\/\n\t.data : {\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t} AT > sram = 0\n\t\n\t\/* Read only data *\/\n\t.rodata : ALIGN(8) {\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\n        *(.rodata1)\n    } AT > sram = 0\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } AT > sram\n\n\t\/* BSS. *\/\n\t.bss : ALIGN(4) {\n\t\t_bssStart_pa = .;\n\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\n\t\t. = ALIGN(4);\n\t\t_bssEnd_pa = .;\n\t} AT > sram\n\n\t\/* Stack. *\/\n\t.stack : ALIGN(4) {\n        . += _stackSize;\n\t} AT > sram\n\n\t\/* Calculate physical addresses of .bss and .stack for startup code. *\/\n\t_stackStart_pa = _bssEnd_pa + SIZEOF(.stack) - 4;\n\n\t\/* Heap. *\/\n\t_heapStart_pa = .;\n\tend = _heapStart_pa;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nENTRY(_start)\n\nMEMORY {\n\tddr (rwx)      :      ORIGIN = 0x00000000, LENGTH = 512M                        \/* External DDR3 RAM *\/\n    sram (rwx)     :      ORIGIN = 0x402f0400, LENGTH = (0x402fffff - 0x402f0400)   \/* Internal on-chip SRAM *\/\n}\n\n_textStart_va        = 0x80000000;   \/* Kernel .text starts at 2 GB. *\/\n_pagePoolInitialSize = 0x1000;       \/* Preallocated page for page pool.*\/\n_stackSize           = 0x1000;       \/* Stack size is 4KB.*\/\n\nSECTIONS {\n\t\/* Static page pool. *\/\n\t.pagePool : ALIGN(4) {\n\t\t_pagePoolStart_pa = .;\n\n        . += _pagePoolInitialSize;\n\t} AT > sram = 0\n\n    \/* Starup code. *\/\n    .boot : {\n        _bootStart_pa = .;\n\n        *(.boot)\n\n        _bootEnd_pa = .;\n    } AT > sram\n\n    \/* Kernel code. *\/\n    .text : {\n        *(.text)                \/* .text sections (code). *\/\n        *(.text*)               \/* .text* sections (code). *\/\n        *(.glue_7)              \/* Glue ARM to Thumb code. *\/\n        *(.glue_7t)             \/* Glue Thumb to ARM code. *\/\n        *(.eh_frame)\n        KEEP (*(.init))\n        KEEP (*(.fini))\n    } AT > sram\n\n    \/* Memory regions provided for kernel. *\/\n    .memory_regions : ALIGN(4) {\n\t\t_memoryRegions_pa = .;\n\n\t\/*  Physical address    Total size          Used size *\/\n        LONG(ORIGIN(sram))  LONG(LENGTH(sram))  LONG(_heapStart_pa - ORIGIN(sram))\n        LONG(0)             LONG(0)             LONG(0)\n    } AT > sram\n\n    \/* Constructors and destructors. *\/\n\t.ctors : {\n\t\tKEEP (*crtbegin*.o(.ctors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t} AT > sram\n\n\t.dtors : {\n\t\tKEEP (*crtbegin*.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t} AT > sram\n\n    \/* Data. *\/\n\t.data : {\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t} AT > sram = 0\n\t\n\t\/* Read only data *\/\n\t.rodata : ALIGN(8) {\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\n        *(.rodata1)\n    } AT > sram = 0\n\n\t\/* BSS. *\/\n\t.bss : ALIGN(4) {\n\t\t_bssStart_pa = .;\n\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\n\t\t. = ALIGN(4);\n\t\t_bssEnd_pa = .;\n\t} AT > sram\n\n\t\/* Stack. *\/\n\t.stack : ALIGN(4) {\n        . += _stackSize;\n\t} AT > sram\n\n\t\/* Calculate physical addresses of .bss and .stack for startup code. *\/\n\t_stackStart_pa = _bssEnd_pa + SIZEOF(.stack) - 4;\n\n\t\/* Heap. *\/\n\t_heapStart_pa = .;\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"2fd0a0bcf72d8458a72d6a71bfb6fc4dba6dbf44","subject":"Move kernel to higher virtual addresses.","message":"Move kernel to higher virtual addresses.\n\nThis patch fixes linker script so that kernel compiled to work\nin higher virtual address, actually at 0xc0000000 (last GB of\nvirtual address space). Userspace will work with lower 3GB of\nvirtual address space (linux kernel 3\/1 memory split).\n","repos":"krinkinmu\/auos,krinkinmu\/auos,krinkinmu\/auos,krinkinmu\/auos","old_file":"kernel\/arch\/x86\/boot\/kernel.ld","new_file":"kernel\/arch\/x86\/boot\/kernel.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nPAGE_OFFSET = 0xC0000000;\nPAGE_SIZE   = 0x00001000;\n\nSECTIONS\n{\n\t\/* GRUB will load kernel in memory starting from 1Mb *\/\n\t. = 1M;\n\t.header    : { *(.header) }\n\n\t. += PAGE_OFFSET;\n\t__kernel_begin = .;\n\t.bootstrap : AT(ADDR(.bootstrap) - PAGE_OFFSET) { *(.bootstrap) }\n\n\t.text   : { *(.text)   *(.text.*) }\n\t.rodata : { *(.rodata) *(.rodata.*) }\n\t.data   : { *(.data)   *(.data.*) }\n\n\t. = ALIGN(PAGE_SIZE);\n\t__bss_begin = .;\n\t.bss : { *(.bss) }\n\t__bss_end = .;\n\n\t. = ALIGN(PAGE_SIZE);\n\t__heap_begin = .;\n\t.heap : { . += 64 * 1024; }\n\t__heap_end = .;\n\n\t__kernel_end = .;\n\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\t.debug_info    0 : { *(.debug_info) }\n\t.debug_abbrev  0 : { *(.debug_abbrev) }\n\t.debug_line    0 : { *(.debug_line) }\n        .debug_str     0 : { *(.debug_str) }\n\n\t\/DISCARD\/ : { *(.eh_frame .note.* .comment) }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSECTIONS\n{\n\t\/* GRUB will load kernel in memory starting from 1Mb *\/\n\t. = 1M;\n\t__kernel_begin = .;\n\t.header    : { *(.header) }\n\t.bootstrap : { *(.bootstrap) }\n\n\t.text   : { *(.text)   *(.text.*) }\n\t.rodata : { *(.rodata) *(.rodata.*) }\n\t.data   : { *(.data)   *(.data.*) }\n\n\t__bss_begin = .;\n\t.bss : { *(.bss) }\n\t__bss_end = .;\n\t__kernel_end = .;\n\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\t.debug_info    0 : { *(.debug_info) }\n\t.debug_abbrev  0 : { *(.debug_abbrev) }\n\t.debug_line    0 : { *(.debug_line) }\n        .debug_str     0 : { *(.debug_str) }\n\n\t\/DISCARD\/ : { *(.eh_frame .note.* .comment) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f09a3a1bd6750b14ee401b5f01da5723d7175ba2","subject":"linker: intel_adsp: discard GNU-stack notes","message":"linker: intel_adsp: discard GNU-stack notes\n\ndiscard GNU-stack notes coming from linker when building with clang.\n\nSigned-off-by: Anas Nashif <0d9952ec84ac43c159f6b7e7ed99a9080c00dd6e@intel.com>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/ace\/ace-link.ld","new_file":"soc\/xtensa\/intel_adsp\/ace\/ace-link.ld","new_contents":"\/*\n * Copyright (c) 2022 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <zephyr\/devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <zephyr\/linker\/sections.h>\n#include <adsp-vectors.h>\n#include <adsp_memory.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n    _imr_end = .;\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int4_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int4_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_ram_start = .;\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.initcall)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <zephyr\/linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <zephyr\/linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n     _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n\n  \/* Heap start and end markers. Used to reserve system heap memory. *\/\n  .heap_mem SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _heap_start = .;\n    *(.heap_mem)\n    _heap_end = .;\n  } >ucram\n\n  .unused_ram_start_marker SEGSTART_CACHED (NOLOAD) :\n  {\n    . = ALIGN(4096);\n    _unused_ram_start_marker = .;\n    *(.unused_ram_start_marker)\n    *(.unused_ram_start_marker.*)\n  } >ram\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n    _image_ram_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n   \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2022 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <zephyr\/devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <zephyr\/linker\/sections.h>\n#include <adsp-vectors.h>\n#include <adsp_memory.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n    _imr_end = .;\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int4_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int4_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_ram_start = .;\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.initcall)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <zephyr\/linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <zephyr\/linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n     _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n\n  \/* Heap start and end markers. Used to reserve system heap memory. *\/\n  .heap_mem SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _heap_start = .;\n    *(.heap_mem)\n    _heap_end = .;\n  } >ucram\n\n  .unused_ram_start_marker SEGSTART_CACHED (NOLOAD) :\n  {\n    . = ALIGN(4096);\n    _unused_ram_start_marker = .;\n    *(.unused_ram_start_marker)\n    *(.unused_ram_start_marker.*)\n  } >ram\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n    _image_ram_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b8d6bcdb0774628ec7ee0ee58a76bf3b600d76cc","subject":"cortexm_common: specify load segment instead of load address for .data","message":"cortexm_common: specify load segment instead of load address for .data\n","repos":"A-Paul\/RIOT,ant9000\/RIOT,miri64\/RIOT,A-Paul\/RIOT,toonst\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,x3ro\/RIOT,jasonatran\/RIOT,BytesGalore\/RIOT,OlegHahm\/RIOT,mfrey\/RIOT,kYc0o\/RIOT,mtausig\/RIOT,gebart\/RIOT,kYc0o\/RIOT,cladmi\/RIOT,miri64\/RIOT,neiljay\/RIOT,basilfx\/RIOT,yogo1212\/RIOT,kaspar030\/RIOT,smlng\/RIOT,neiljay\/RIOT,ant9000\/RIOT,aeneby\/RIOT,kYc0o\/RIOT,avmelnikoff\/RIOT,jasonatran\/RIOT,gebart\/RIOT,gebart\/RIOT,avmelnikoff\/RIOT,cladmi\/RIOT,rfuentess\/RIOT,BytesGalore\/RIOT,avmelnikoff\/RIOT,OlegHahm\/RIOT,josephnoir\/RIOT,toonst\/RIOT,avmelnikoff\/RIOT,A-Paul\/RIOT,mtausig\/RIOT,OTAkeys\/RIOT,lazytech-org\/RIOT,RIOT-OS\/RIOT,mfrey\/RIOT,RIOT-OS\/RIOT,rfuentess\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,toonst\/RIOT,kbumsik\/RIOT,yogo1212\/RIOT,kaspar030\/RIOT,lazytech-org\/RIOT,A-Paul\/RIOT,OlegHahm\/RIOT,neiljay\/RIOT,cladmi\/RIOT,lazytech-org\/RIOT,rfuentess\/RIOT,OTAkeys\/RIOT,kbumsik\/RIOT,x3ro\/RIOT,BytesGalore\/RIOT,lazytech-org\/RIOT,avmelnikoff\/RIOT,biboc\/RIOT,neiljay\/RIOT,BytesGalore\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,mtausig\/RIOT,mfrey\/RIOT,basilfx\/RIOT,kaspar030\/RIOT,basilfx\/RIOT,authmillenon\/RIOT,ant9000\/RIOT,biboc\/RIOT,jasonatran\/RIOT,aeneby\/RIOT,biboc\/RIOT,biboc\/RIOT,rfuentess\/RIOT,BytesGalore\/RIOT,OTAkeys\/RIOT,yogo1212\/RIOT,yogo1212\/RIOT,miri64\/RIOT,miri64\/RIOT,authmillenon\/RIOT,kbumsik\/RIOT,yogo1212\/RIOT,toonst\/RIOT,OlegHahm\/RIOT,cladmi\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,smlng\/RIOT,josephnoir\/RIOT,smlng\/RIOT,aeneby\/RIOT,mtausig\/RIOT,gebart\/RIOT,neiljay\/RIOT,biboc\/RIOT,toonst\/RIOT,rfuentess\/RIOT,x3ro\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,gebart\/RIOT,RIOT-OS\/RIOT,josephnoir\/RIOT,cladmi\/RIOT,aeneby\/RIOT,miri64\/RIOT,mfrey\/RIOT,ant9000\/RIOT,lazytech-org\/RIOT,mtausig\/RIOT,smlng\/RIOT,kbumsik\/RIOT,x3ro\/RIOT,RIOT-OS\/RIOT,A-Paul\/RIOT,x3ro\/RIOT,josephnoir\/RIOT,smlng\/RIOT,josephnoir\/RIOT,basilfx\/RIOT,OTAkeys\/RIOT,kbumsik\/RIOT,OTAkeys\/RIOT,kaspar030\/RIOT,basilfx\/RIOT,kaspar030\/RIOT,mfrey\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* This is only used by gdb to understand where to start *\/\nENTRY(reset_handler_default)\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _isr_vectors = DEFINED(_isr_vectors) ? _isr_vectors : . ;\n        KEEP(*(SORT(.vectors*)))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate :\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        KEEP (*(.openocd .openocd.*))\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram AT> rom\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* This is only used by gdb to understand where to start *\/\nENTRY(reset_handler_default)\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _isr_vectors = DEFINED(_isr_vectors) ? _isr_vectors : . ;\n        KEEP(*(SORT(.vectors*)))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate : AT (_etext)\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        KEEP (*(.openocd .openocd.*))\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"3bbf5af668b26d7efdddf72ed295d860cabd2934","subject":"Linker: Add \".ARM.extab\" section in linker script for Cortex-M","message":"Linker: Add \".ARM.extab\" section in linker script for Cortex-M\n\nWhen using C++ exceptions in a Cortex-M, the linker return a warning:\nwarning: orphan section \".ARM.extab\"\n.ARM.extab section containing exception unwinding information.\nThis section is missing in the linker script for Cortex-M.\n\nSigned-off-by: Benoit Leforestier <643bdb7e1bff6fd5dea65e7d0b3d32ab0e78db80@gmail.com>\n","repos":"finikorg\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,explora26\/zephyr,nashif\/zephyr,Vudentz\/zephyr,explora26\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,ldts\/zephyr,Vudentz\/zephyr,ldts\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,ldts\/zephyr,galak\/zephyr,ldts\/zephyr,Vudentz\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,Vudentz\/zephyr,galak\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN . = ALIGN(4);\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t_app_smem_end = .;\n\t\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN . = ALIGN(4);\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t_app_smem_end = .;\n\t\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3475e82c44ae47a09777068867e18ca92b3da09b","subject":"Change alignment of Bootloader data section","message":"Change alignment of Bootloader data section\n\nUse 0x0400 rather than 0x1000 for aligning the Bootloader data section.\nMakes Bootloader .bin size smaller and helps with a seeprom 128k boundary\nproblem.\n\nChange-Id: I3e4f02213f704db22fdc875a2325352aae483cdf\nRTC: 152752\nReviewed-on: http:\/\/ralgit01.raleigh.ibm.com\/gerrit1\/23802\nTested-by: Jenkins Server\nTested-by: FSP CI Jenkins\nReviewed-by: Daniel M. Crowell <912029ca9254ac7b5854e56910561d682e1fa2d0@us.ibm.com>\nReviewed-by: Andrew J. Geissler <c46de238cd554860f0bd4010b1729f1323facd9c@us.ibm.com>\nReviewed-by: William G. Hoffa <7dd6aa5e78423995d9d7c7ecada5b77ee07f88cc@us.ibm.com>\n","repos":"Over-enthusiastic\/hostboot,Over-enthusiastic\/hostboot,Over-enthusiastic\/hostboot,Over-enthusiastic\/hostboot,Over-enthusiastic\/hostboot","old_file":"src\/bootloader.ld","new_file":"src\/bootloader.ld","new_contents":"\/* IBM_PROLOG_BEGIN_TAG                                                   *\/\n\/* This is an automatically generated prolog.                             *\/\n\/*                                                                        *\/\n\/* $Source: src\/bootloader.ld $                                           *\/\n\/*                                                                        *\/\n\/* OpenPOWER HostBoot Project                                             *\/\n\/*                                                                        *\/\n\/* Contributors Listed Below - COPYRIGHT 2015,2016                        *\/\n\/* [+] Google Inc.                                                        *\/\n\/* [+] International Business Machines Corp.                              *\/\n\/*                                                                        *\/\n\/*                                                                        *\/\n\/* Licensed under the Apache License, Version 2.0 (the \"License\");        *\/\n\/* you may not use this file except in compliance with the License.       *\/\n\/* You may obtain a copy of the License at                                *\/\n\/*                                                                        *\/\n\/*     http:\/\/www.apache.org\/licenses\/LICENSE-2.0                         *\/\n\/*                                                                        *\/\n\/* Unless required by applicable law or agreed to in writing, software    *\/\n\/* distributed under the License is distributed on an \"AS IS\" BASIS,      *\/\n\/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        *\/\n\/* implied. See the License for the specific language governing           *\/\n\/* permissions and limitations under the License.                         *\/\n\/*                                                                        *\/\n\/* IBM_PROLOG_END_TAG                                                     *\/\nbase_load_address = 0x00000000;\nsbe_hb_structures = 0x00000004;\n\/* @TODO-RTC:138273-Support multiple nodes using relative HRMOR *\/\n\/* Text section offset = 12KB (space reserved for exception vectors)      *\/\ntext_load_address = 0x00003000;\n\nSECTIONS\n{\n    . = base_load_address;\n\n    . = sbe_hb_structures;\n\n    . = text_load_address;\n    .text ALIGN(0x0020): {\n        *(.text.intvects)\n        *(.text.bootloaderasm)\n        *(.text)\n        *(.text._*)\n        *(.text.*)\n    }\n\n    .rodata ALIGN(0x8): {\n        __minimum_data_start_addr = ALIGN(0x400);\n        ctor_start_address = .;\n        *(.ctors)\n        *(.ctors.*)\n        ctor_end_address = .;\n        *(.rodata)\n        *(.rodata.*)\n        . = ALIGN(8);\n        toc_load_address = .;\n        *(.toc)\n        *(.opd)\n        *(.got)\n        *(.plt)\n        *(.data.rel.ro.*)\n        *(.data.*traceData_codeInfo*)\n\n        . = __minimum_data_start_addr > . ? __minimum_data_start_addr : .;\n    }\n\n    .data ALIGN(0x8): {\n        data_load_address = .;\n        *(.data)\n        *(.data.*)\n\n        *(.bss)\n        *(.bss.*)\n\n    }\n\n    end_load_address = .;\n\n    .rela : {\n        *(.rela.*)\n    }\n\n    .dynsym : { *(.dynsym) }\n    .dynstr : { *(.dynstr) }\n    .hash : { *(.hash) }\n    .gnu.hash : { *(.gnu.hash) }\n    .eh_frame : { *(.eh_frame) }\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.gnu.attributes)\n        *(.dtors)\n        *(.interp)\n    }\n}\n\n\n","old_contents":"\/* IBM_PROLOG_BEGIN_TAG                                                   *\/\n\/* This is an automatically generated prolog.                             *\/\n\/*                                                                        *\/\n\/* $Source: src\/bootloader.ld $                                           *\/\n\/*                                                                        *\/\n\/* OpenPOWER HostBoot Project                                             *\/\n\/*                                                                        *\/\n\/* Contributors Listed Below - COPYRIGHT 2015,2016                        *\/\n\/* [+] Google Inc.                                                        *\/\n\/* [+] International Business Machines Corp.                              *\/\n\/*                                                                        *\/\n\/*                                                                        *\/\n\/* Licensed under the Apache License, Version 2.0 (the \"License\");        *\/\n\/* you may not use this file except in compliance with the License.       *\/\n\/* You may obtain a copy of the License at                                *\/\n\/*                                                                        *\/\n\/*     http:\/\/www.apache.org\/licenses\/LICENSE-2.0                         *\/\n\/*                                                                        *\/\n\/* Unless required by applicable law or agreed to in writing, software    *\/\n\/* distributed under the License is distributed on an \"AS IS\" BASIS,      *\/\n\/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        *\/\n\/* implied. See the License for the specific language governing           *\/\n\/* permissions and limitations under the License.                         *\/\n\/*                                                                        *\/\n\/* IBM_PROLOG_END_TAG                                                     *\/\nbase_load_address = 0x00000000;\nsbe_hb_structures = 0x00000004;\n\/* @TODO-RTC:138273-Support multiple nodes using relative HRMOR *\/\n\/* Text section offset = 12KB (space reserved for exception vectors)      *\/\ntext_load_address = 0x00003000;\n\nSECTIONS\n{\n    . = base_load_address;\n\n    . = sbe_hb_structures;\n\n    . = text_load_address;\n    .text ALIGN(0x0020): {\n        *(.text.intvects)\n        *(.text.bootloaderasm)\n        *(.text)\n        *(.text._*)\n        *(.text.*)\n    }\n\n    .rodata ALIGN(0x8): {\n        __minimum_data_start_addr = ALIGN(0x1000);\n        ctor_start_address = .;\n        *(.ctors)\n        *(.ctors.*)\n        ctor_end_address = .;\n        *(.rodata)\n        *(.rodata.*)\n        . = ALIGN(8);\n        toc_load_address = .;\n        *(.toc)\n        *(.opd)\n        *(.got)\n        *(.plt)\n        *(.data.rel.ro.*)\n        *(.data.*traceData_codeInfo*)\n\n        . = __minimum_data_start_addr > . ? __minimum_data_start_addr : .;\n    }\n\n    .data ALIGN(0x8): {\n        data_load_address = .;\n        *(.data)\n        *(.data.*)\n\n        *(.bss)\n        *(.bss.*)\n\n    }\n\n    end_load_address = .;\n\n    .rela : {\n        *(.rela.*)\n    }\n\n    .dynsym : { *(.dynsym) }\n    .dynstr : { *(.dynstr) }\n    .hash : { *(.hash) }\n    .gnu.hash : { *(.gnu.hash) }\n    .eh_frame : { *(.eh_frame) }\n\n    \/DISCARD\/ : {\n        *(.comment)\n        *(.gnu.attributes)\n        *(.dtors)\n        *(.interp)\n    }\n}\n\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c4cb84140f619d16073ef24031c8534c7a491611","subject":"arch: arm: aarch64: linker.ld: Fix ROM section names","message":"arch: arm: aarch64: linker.ld: Fix ROM section names\n\nThis commit fixes the improper naming of the ROM sections.\n\n1. Rename the first ROM section, which was previously named using the\n  `_TEXT_SECTION_NAME` definition, to `rom_start`, as this section does\n  not actually represent the text section.\n\n2. Rename the second ROM section, which was previously named\n  `_TEXT_SECTION_NAME_2` which supposedly refers to the definition of\n  the same name that does not exist, to `_TEXT_SECTION_NAME`. Note that\n  this is indeed the section that contains the text section from the\n  source image.\n\nSigned-off-by: Stephanos Ioannidis <dc76e9f0c0006e8f919e0c515c66dbba3982f785@stephanos.io>\n","repos":"zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n  \/* If building without MPU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM       (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n        KEEP(*(.vector_relay_table))\n        KEEP(*(\".vector_relay_table.*\"))\n        KEEP(*(.vector_relay_handler))\n        KEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(IRQ_VECTOR_TABLE))\n\n        KEEP(*(.vectors))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        _vector_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    MPU_ALIGN(_image_rodata_end -_image_rom_start);\n    _image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        *(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n    } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n    #define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#else\n    #define NSC_ALIGN . = ALIGN(4)\n#endif\n\n    #define NSC_ALIGN_END . = ALIGN(4)\n\n    SECTION_PROLOGUE(.gnu.sgstubs,,)\n    {\n        NSC_ALIGN;\n        __sg_start = .;\n        \/* No input section necessary, since the Secure Entry Veneers are\n           automatically placed after the .gnu.sgstubs output section. *\/\n    } GROUP_LINK_IN(ROMABLE_REGION)\n    __sg_end = .;\n    __sg_size = __sg_end - __sg_start;\n    NSC_ALIGN_END;\n    __nsc_size = . - __sg_start;\n\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n  \/* If building without MPU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n  #define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM       (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n    {\n        *(.plt)\n    }\n\n    SECTION_PROLOGUE(.iplt,,)\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n        KEEP(*(.vector_relay_table))\n        KEEP(*(\".vector_relay_table.*\"))\n        KEEP(*(.vector_relay_handler))\n        KEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(IRQ_VECTOR_TABLE))\n\n        KEEP(*(.vectors))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        _vector_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n    {\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n        \/*\n         * For XIP images, in order to avoid the situation when __data_rom_start\n         * is 32-bit aligned, but the actual data is placed right after rodata\n         * section, which may not end exactly at 32-bit border, pad rodata\n         * section, so __data_rom_start points at data and it is 32-bit aligned.\n         *\n         * On non-XIP images this may enlarge image size up to 3 bytes. This\n         * generally is not an issue, since modern ROM and FLASH memory is\n         * usually 4k aligned.\n         *\/\n        . = ALIGN(4);\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    MPU_ALIGN(_image_rodata_end -_image_rom_start);\n    _image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MPU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        *(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n    } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n    #define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#else\n    #define NSC_ALIGN . = ALIGN(4)\n#endif\n\n    #define NSC_ALIGN_END . = ALIGN(4)\n\n    SECTION_PROLOGUE(.gnu.sgstubs,,)\n    {\n        NSC_ALIGN;\n        __sg_start = .;\n        \/* No input section necessary, since the Secure Entry Veneers are\n           automatically placed after the .gnu.sgstubs output section. *\/\n    } GROUP_LINK_IN(ROMABLE_REGION)\n    __sg_end = .;\n    __sg_size = __sg_end - __sg_start;\n    NSC_ALIGN_END;\n    __nsc_size = . - __sg_start;\n\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cd5acae4f429dbad649f0c10b72fd483c2294feb","subject":"Sort .text section to reduce fill","message":"Sort .text section to reduce fill\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/atmel-samd\/boards\/common.template.ld","new_file":"ports\/atmel-samd\/boards\/common.template.ld","new_contents":"\/* Template for SAMD21\/SAMD51 linking. dollar-sign-curly-bracket items are replaced with strings. *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_BOOTLOADER (rx): ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_FILESYSTEM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_CONFIG (r) : ORIGIN = ${CIRCUITPY_INTERNAL_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_CONFIG_SIZE}\n    FLASH_NVM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n\n    RAM (xrw)  : ORIGIN = 0x20000000, LENGTH = ${RAM_SIZE}\n}\n\n\/* top end of the stack *\/\n\/* stack must be double-word (8 byte) aligned *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - 8;\n_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors)) \/* isr vector table *\/\n\n        \/* Sort text sections so that they have fewer *fill* bytes needed. *\/\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.text))           \/* .text sections (code) *\/\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.text*))          \/* .text* sections (code) *\/\n\n        \/* Don't sort rodata because it impacts codegen size. *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n    } >FLASH_FIRMWARE\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = .;       \/* start of .data section *\/\n    } >FLASH_FIRMWARE\n\n    \/* Data accessed by the CAN peripheral must be in the first 64kB RAM *\/\n    \/* place it at the very start of RAM, before the .data section *\/\n    \/* it is zeroed by reset_port *\/\n    .canram (NOLOAD) :\n    {\n        . = ALIGN(4);\n        *(.canram)\n    } > RAM\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH_FIRMWARE to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _srelocate = .;        \/* create a global symbol at data start; used by startup code in order to initialize the .data section in RAM *\/\n        *(.ramfunc)\n        *(.ramfunc*)\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.data))           \/* .data sections *\/\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.data*))          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _erelocate = .;        \/* define a global symbol at data end; used by startup code in order to initialize the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        _szero = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ezero = .;         \/* define a global symbol at bss end; used by startup code *\/\n        _ebss = .;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the requested stack. *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/* Template for SAMD21\/SAMD51 linking. dollar-sign-curly-bracket items are replaced with strings. *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_BOOTLOADER (rx): ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_FILESYSTEM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_CONFIG (r) : ORIGIN = ${CIRCUITPY_INTERNAL_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_CONFIG_SIZE}\n    FLASH_NVM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n\n    RAM (xrw)  : ORIGIN = 0x20000000, LENGTH = ${RAM_SIZE}\n}\n\n\/* top end of the stack *\/\n\/* stack must be double-word (8 byte) aligned *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - 8;\n_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n    } >FLASH_FIRMWARE\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = .;       \/* start of .data section *\/\n    } >FLASH_FIRMWARE\n\n    \/* Data accessed by the CAN peripheral must be in the first 64kB RAM *\/\n    \/* place it at the very start of RAM, before the .data section *\/\n    \/* it is zeroed by reset_port *\/\n    .canram (NOLOAD) :\n    {\n        . = ALIGN(4);\n        *(.canram)\n    } > RAM\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH_FIRMWARE to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _srelocate = .;        \/* create a global symbol at data start; used by startup code in order to initialize the .data section in RAM *\/\n        *(.ramfunc)\n        *(.ramfunc*)\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _erelocate = .;        \/* define a global symbol at data end; used by startup code in order to initialize the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        _szero = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ezero = .;         \/* define a global symbol at bss end; used by startup code *\/\n        _ebss = .;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the requested stack. *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"259bbd4dbb284e48dd0044d6fdfa2677269e255f","subject":"build: Correct linker script alignment","message":"build: Correct linker script alignment\n\nFrom the docs:\n\n     SECTION [ADDRESS] [(TYPE)] :\n       [ALIGN(SECTION_ALIGN)]\n\nwhat Cibyl used:\n\n     SECTION ALIGN(...) [ADDRESS] [(TYPE)] :\n\t...\n\nCorrects GCC 4.4.5 builds.\n","repos":"SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl","old_file":"build\/linker.lds","new_file":"build\/linker.lds","new_contents":"","old_contents":"","returncode":0,"stderr":"unknown","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"5e887ce1c49a061eff3d5902160bc56a7873bdaa","subject":"Sync linker script with latest emt","message":"Sync linker script with latest emt\n","repos":"sanyaade-iot\/Energia,dvdvideo1234\/Energia,vigneshmanix\/Energia,dvdvideo1234\/Energia,qtonthat\/Energia,vigneshmanix\/Energia,DavidUser\/Energia,bobintornado\/Energia,qtonthat\/Energia,bobintornado\/Energia,DavidUser\/Energia,danielohh\/Energia,NoPinky\/Energia,martianmartin\/Energia,NoPinky\/Energia,battosai30\/Energia,danielohh\/Energia,sanyaade-iot\/Energia,martianmartin\/Energia,DavidUser\/Energia,radiolok\/Energia,radiolok\/Energia,croberts15\/Energia,vigneshmanix\/Energia,NoPinky\/Energia,martianmartin\/Energia,croberts15\/Energia,bobintornado\/Energia,qtonthat\/Energia,battosai30\/Energia,brianonn\/Energia,radiolok\/Energia,battosai30\/Energia,croberts15\/Energia,vigneshmanix\/Energia,cevatbostancioglu\/Energia,danielohh\/Energia,danielohh\/Energia,battosai30\/Energia,battosai30\/Energia,radiolok\/Energia,NoPinky\/Energia,dvdvideo1234\/Energia,brianonn\/Energia,dvdvideo1234\/Energia,battosai30\/Energia,cevatbostancioglu\/Energia,radiolok\/Energia,brianonn\/Energia,battosai30\/Energia,NoPinky\/Energia,croberts15\/Energia,bobintornado\/Energia,martianmartin\/Energia,sanyaade-iot\/Energia,DavidUser\/Energia,qtonthat\/Energia,sanyaade-iot\/Energia,sanyaade-iot\/Energia,qtonthat\/Energia,brianonn\/Energia,radiolok\/Energia,danielohh\/Energia,bobintornado\/Energia,cevatbostancioglu\/Energia,qtonthat\/Energia,croberts15\/Energia,martianmartin\/Energia,DavidUser\/Energia,martianmartin\/Energia,croberts15\/Energia,brianonn\/Energia,brianonn\/Energia,cevatbostancioglu\/Energia,cevatbostancioglu\/Energia,martianmartin\/Energia,croberts15\/Energia,vigneshmanix\/Energia,NoPinky\/Energia,vigneshmanix\/Energia,dvdvideo1234\/Energia,bobintornado\/Energia,cevatbostancioglu\/Energia,sanyaade-iot\/Energia,vigneshmanix\/Energia,sanyaade-iot\/Energia,bobintornado\/Energia,cevatbostancioglu\/Energia,danielohh\/Energia,qtonthat\/Energia,dvdvideo1234\/Energia,dvdvideo1234\/Energia,NoPinky\/Energia,DavidUser\/Energia,brianonn\/Energia,DavidUser\/Energia,radiolok\/Energia,danielohh\/Energia","old_file":"hardware\/msp432\/MSP432P401R.lds","new_file":"hardware\/msp432\/MSP432P401R.lds","new_contents":"\/******************************************************************************\n*\n* Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http:\/\/www.ti.com\/ \n*\n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions \n* are met:\n*\n*  Redistributions of source code must retain the above copyright \n*  notice, this list of conditions and the following disclaimer.\n*\n*  Redistributions in binary form must reproduce the above copyright\n*  notice, this list of conditions and the following disclaimer in the \n*  documentation and\/or other materials provided with the   \n*  distribution.\n*\n*  Neither the name of Texas Instruments Incorporated nor the names of\n*  its contributors may be used to endorse or promote products derived\n*  from this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \n* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \n* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \n* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*\n* GCC linker script for Texas Instruments MSP432P401R\n*\n* File creation date: 2014-04-25\n*\n******************************************************************************\/\n\nMEMORY\n{\n    FLASH     (RX) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n    FLASH_OTP (RX) : ORIGIN = 0x00200000, LENGTH = 0x00004000\n    SRAM      (RWX): ORIGIN = 0x20000000, LENGTH = 0x00010000\n}\n\nREGION_ALIAS(\"REGION_TEXT\", FLASH);\nREGION_ALIAS(\"REGION_BSS\", SRAM);\nREGION_ALIAS(\"REGION_DATA\", SRAM);\nREGION_ALIAS(\"REGION_STACK\", SRAM);\nREGION_ALIAS(\"REGION_HEAP\", SRAM);\nREGION_ALIAS(\"REGION_ARM_EXIDX\", FLASH);\nREGION_ALIAS(\"REGION_ARM_EXTAB\", FLASH);\n\nSECTIONS {\n\n    PROVIDE (_intvecs_base_address = 0x0);\n\n    .intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {\n        KEEP (*(.intvecs))\n    } > REGION_TEXT\n\n    PROVIDE (_vtable_base_address = 0x20000000);\n\n    .vtable (_vtable_base_address) : AT (_vtable_base_address) {\n        KEEP (*(.vtable))\n    } > REGION_DATA\n\n    .text : {\n        CREATE_OBJECT_SYMBOLS\n        KEEP (*(.text))\n        *(.text.*)\n        . = ALIGN(0x4);\n        KEEP (*(.ctors))\n        . = ALIGN(0x4);\n        KEEP (*(.dtors))\n        . = ALIGN(0x4);\n        __init_array_start = .;\n        KEEP (*(.init_array*))\n        __init_array_end = .;\n        *(.init)\n        *(.fini*)\n    } > REGION_TEXT\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata.*)\n    } > REGION_TEXT\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > REGION_ARM_EXIDX\n\n    .ARM.extab : {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > REGION_ARM_EXTAB\n\n    __etext = .;\n\n    .data : {\n        __data_load__ = LOADADDR (.data);\n        __data_start__ = .;\n        KEEP (*(.data))\n        KEEP (*(.data*))\n        . = ALIGN (4);\n        __data_end__ = .;\n    } > REGION_DATA AT> REGION_TEXT\n\n    .bss : {\n        __bss_start__ = .;\n        *(.shbss)\n        KEEP (*(.bss))\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN (4);\n        __bss_end__ = .;\n    } > REGION_BSS\n\n    .stack : ALIGN(0x8) {\n        _stack = .;\n        __stack = .;\n        KEEP(*(.stack))\n    } > REGION_STACK\n\n    .heap : {\n        __heap_start__ = .;\n        end = __heap_start__;\n        _end = end;\n        __end = end;\n        KEEP (*(.heap))\n        __heap_end__ = .;\n        __HeapLimit = __heap_end__;\n    } > REGION_HEAP\n}\n\n","old_contents":"\/******************************************************************************\n*\n* Copyright (C) 2012 - 2014 Texas Instruments Incorporated - http:\/\/www.ti.com\/ \n*\n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions \n* are met:\n*\n*  Redistributions of source code must retain the above copyright \n*  notice, this list of conditions and the following disclaimer.\n*\n*  Redistributions in binary form must reproduce the above copyright\n*  notice, this list of conditions and the following disclaimer in the \n*  documentation and\/or other materials provided with the   \n*  distribution.\n*\n*  Neither the name of Texas Instruments Incorporated nor the names of\n*  its contributors may be used to endorse or promote products derived\n*  from this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \n* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \n* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \n* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*\n* GCC linker script for Texas Instruments MSP432P401R\n*\n* File creation date: 2014-04-25\n*\n******************************************************************************\/\n\nMEMORY\n{\n    FLASH     (RX) : ORIGIN = 0x00000000, LENGTH = 0x00040000\n    FLASH_OTP (RX) : ORIGIN = 0x00200000, LENGTH = 0x00004000\n    SRAM      (RWX): ORIGIN = 0x20000000, LENGTH = 0x00010000\n}\n\nREGION_ALIAS(\"REGION_TEXT\", FLASH);\nREGION_ALIAS(\"REGION_BSS\", SRAM);\nREGION_ALIAS(\"REGION_DATA\", SRAM);\nREGION_ALIAS(\"REGION_STACK\", SRAM);\nREGION_ALIAS(\"REGION_HEAP\", SRAM);\nREGION_ALIAS(\"REGION_ARM_EXIDX\", FLASH);\nREGION_ALIAS(\"REGION_ARM_EXTAB\", FLASH);\n\nSECTIONS {\n\n    PROVIDE (_intvecs_base_address = 0x0);\n\n    .intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {\n        KEEP (*(.intvecs))\n    } > REGION_TEXT\n\n    PROVIDE (_vtable_base_address = 0x20000000);\n\n    .vtable (_vtable_base_address) : AT (_vtable_base_address) {\n        KEEP (*(.vtable))\n    } > REGION_DATA\n\n    .text : {\n        CREATE_OBJECT_SYMBOLS\n        KEEP (*(.text))\n        *(.text.*)\n        . = ALIGN(0x4);\n        KEEP (*(.ctors))\n        . = ALIGN(0x4);\n        KEEP (*(.dtors))\n        . = ALIGN(0x4);\n        __init_array_start = .;\n        KEEP (*(.init_array*))\n        __init_array_end = .;\n        *(.init)\n        *(.fini*)\n    } > REGION_TEXT\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata.*)\n    } > REGION_TEXT\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > REGION_ARM_EXIDX\n\n    .ARM.extab : {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > REGION_ARM_EXTAB\n\n    __etext = .;\n\n    .data : {\n        __data_load__ = LOADADDR (.data);\n        __data_start__ = .;\n        KEEP (*(.data))\n        KEEP (*(.data*))\n        . = ALIGN (4);\n        __data_end__ = .;\n    } > REGION_DATA AT> REGION_TEXT\n\n    .bss : {\n        __bss_start__ = .;\n        *(.shbss)\n        KEEP (*(.bss))\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN (4);\n        __bss_end__ = .;\n    } > REGION_BSS\n\n    .heap : {\n        __heap_start__ = .;\n        end = __heap_start__;\n        _end = end;\n        __end = end;\n        KEEP (*(.heap))\n        __heap_end__ = .;\n        __HeapLimit = __heap_end__;\n    } > REGION_HEAP\n\n    .stack : ALIGN(0x8) {\n        _stack = .;\n        __stack = .;\n        KEEP(*(.stack))\n    } > REGION_STACK\n}\n\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"8739bc261e225bae568f829ef1bba8d82c40d6b5","subject":"Data size calculation is required due to addition data sections created outside of .data section by Nordic SDK12. Without this, the firmware only runs within debugger.  Once power cycled, the data are undefined though causing a crash internal to Nordic SDK.","message":"Data size calculation is required due to addition data sections created outside of .data section by Nordic SDK12.\nWithout this, the firmware only runs within debugger.  Once power cycled, the data are undefined though causing a crash internal to Nordic SDK.\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/src\/gcc_arm_flash.ld","new_file":"ARM\/src\/gcc_arm_flash.ld","new_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t\n\t\t\/* At addr zero is the stack pointer *\/\n\t\t\/*LONG(__StackTop);*\/\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect*))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\t\/* in case security config is not defined, fill in default *\/\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xfffffffe);\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : \n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n\n   \t\/* calculate size to take full range from .data to .bss in case other data sections\n   \t   were inserted in between from outside of this file *\/\n   \t__data_size__ = __bss_start__ - __data_start__ ; \/* SIZEOF(.data);*\/\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","old_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t\n\t\t\/* At addr zero is the stack pointer *\/\n\t\t\/*LONG(__StackTop);*\/\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect*))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\t\/* in case security config is not defined, fill in default *\/\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xfffffffe);\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : \n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n\n   \t\/* calculate size to take full range from .data to .bss in case other data sections\n   \t   were inserted in between from outside of this file *\/\n   \t__data_size__ = SIZEOF(.data);\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"04ed57fd2bf608d787a7ed8ee0a6f0f8d108c7cb","subject":"Removed link script in source tree","message":"Removed link script in source tree\n","repos":"scrat101\/Alo2,scrat101\/Alo2","old_file":"src\/Kernel\/ALinkScript.ld","new_file":"src\/Kernel\/ALinkScript.ld","new_contents":"","old_contents":"ENTRY(_KernelEntry) \r\n\r\nSECTIONS { \r\n\t. = 1M; \r\n\t.text BLOCK(4k) : ALIGN(4k) { \r\n\t\t*(.multiboot) \r\n\t\t*(.text) \r\n\t} \r\n\t\r\n\t.rodata BLOCK(4K)  :  ALIGN(4K) { \r\n\t\t*(.rodata) \r\n\t} \r\n\t\r\n\t.data BLOCK(4K) : ALIGN(4K) \r\n\t{ \r\n\t\t*(.data) \r\n\t} \r\n\t\r\n\t.bss BLOCK(4K)    :          ALIGN(4K) { \r\n\t\t*(COMMON) \r\n\t\t*(.bss) \r\n\t\t*(.MainStack) \r\n\t} \r\n\r\n} \r\n\r\n","returncode":0,"stderr":"","license":"cc0-1.0","lang":"Linker Script"}
{"commit":"dbabbbe8ce66113baef87a6caaea5ce4db82a061","subject":"","message":"\n\ngit-svn-id: https:\/\/chibios.svn.sourceforge.net\/svnroot\/chibios\/trunk@4654 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"os\/ports\/GCC\/PPC\/SPC563Mxx\/ld\/SPC563M64.ld","new_file":"os\/ports\/GCC\/PPC\/SPC563Mxx\/ld\/SPC563M64.ld","new_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011,2012 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * SPC563M64 memory setup.\r\n *\/\r\n__irq_stack_size__      = 0x0400;\r\n__process_stack_size__  = 0x0800;\r\n__stacks_total_size__   = __irq_stack_size__ + __process_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x00000000, len = 1536k\r\n    ram   : org = 0x40000000, len = 94k\r\n}\r\n\r\n\/*\r\n * Derived constants.\r\n *\/\r\n__flash_size__          = LENGTH(flash);\r\n__flash_start__         = ORIGIN(flash);\r\n__flash_end__           = ORIGIN(flash) + LENGTH(flash);\r\n\r\n__ram_size__            = LENGTH(ram);\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_end__             = ORIGIN(ram) + LENGTH(ram);\r\n\r\nSECTIONS\r\n{\r\n    . = ORIGIN(flash);\r\n    .boot : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        __ivpr_base__ = .;\r\n        KEEP(*(.bam))\r\n        KEEP(*(.crt0))\r\n        KEEP(*(.handlers))\r\n        . = ALIGN(0x800);\r\n        KEEP(*(.vectors))\r\n    } > flash\r\n\r\n    constructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE(__init_array_end = .);\r\n    } > flash\r\n\r\n    destructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__fini_array_start = .);\r\n        KEEP(*(.fini_array))\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        PROVIDE(__fini_array_end = .);\r\n    } > flash\r\n\r\n    .text_vle : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        *(.text_vle)\r\n        *(.text_vle.*)\r\n        *(.gnu.linkonce.t_vle.*)\r\n    } > flash\r\n\r\n    .text : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.gnu.linkonce.t.*)\r\n    } > flash\r\n\r\n    .rodata : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.rodata1)\r\n    } > flash\r\n\r\n    .sdata2 : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        __sdata2_start__ = . + 0x8000;\r\n        *(.sdata2)\r\n        *(.sdata2.*)\r\n        *(.gnu.linkonce.s2.*)\r\n        *(.sbss2)\r\n        *(.sbss2.*)\r\n        *(.gnu.linkonce.sb2.*)\r\n    } > flash\r\n\r\n    .eh_frame_hdr :\r\n    {\r\n        *(.eh_frame_hdr)\r\n    } > flash\r\n\r\n    .eh_frame : ONLY_IF_RO\r\n    {\r\n        *(.eh_frame)\r\n    } > flash\r\n\r\n    .romdata : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        __romdata_start__ = .;\r\n    } > flash\r\n\r\n    .data : AT(__romdata_start__)\r\n    {\r\n        . = ALIGN(4);\r\n        __data_start__ = .;\r\n        *(.data)\r\n        *(.data.*)\r\n        *(.gnu.linkonce.d.*)\r\n        __sdata_start__ = . + 0x8000;\r\n        *(.sdata)\r\n        *(.sdata.*)\r\n        *(.gnu.linkonce.s.*)\r\n        __data_end__ = .;\r\n    } > ram\r\n\r\n    .sbss :\r\n    {\r\n        __bss_start__ = .;\r\n        *(.sbss)\r\n        *(.sbss.*)\r\n        *(.gnu.linkonce.sb.*)\r\n        *(.scommon)\r\n    } > ram\r\n\r\n    .bss :\r\n    {\r\n        *(.bss)\r\n        *(.bss.*)\r\n        *(.gnu.linkonce.b.*)\r\n        *(COMMON)\r\n        __bss_end__ = .;\r\n    } > ram\r\n\r\n    __heap_base__   = __bss_end__;\r\n    __heap_end__    = __ram_end__ - __stacks_total_size__;\r\n}\r\n","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010,\r\n                 2011,2012 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * SPC563M64 memory setup.\r\n *\/\r\n__irq_stack_size__      = 0x0400;\r\n__process_stack_size__  = 0x0800;\r\n__stacks_total_size__   = __irq_stack_size__ + __process_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x00000000, len = 1536k\r\n    ram   : org = 0x40000000, len = 94k\r\n}\r\n\r\n\/*\r\n * Derived constants.\r\n *\/\r\n__flash_size__          = LENGTH(flash);\r\n__flash_start__         = ORIGIN(flash);\r\n__flash_end__           = ORIGIN(flash) + LENGTH(flash);\r\n\r\n__ram_size__            = LENGTH(ram);\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_end__             = ORIGIN(ram) + LENGTH(ram);\r\n\r\nSECTIONS\r\n{\r\n    . = ORIGIN(flash);\r\n    .boot : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        __ivpr_base__ = .;\r\n        KEEP(*(.bam))\r\n        KEEP(*(.crt0))\r\n        KEEP(*(.handlers))\r\n        . = ALIGN(0x800);\r\n        KEEP(*(.vectors))\r\n    } > flash\r\n\r\n    constructors : ALIGN(4) SUBALIGN(4)\r\n    {\r\n        PROVIDE(__init_array_start = .);\r\n        KEEP(*(SORT(.init_array.*)))\r\n        KEEP(*(.init_array))\r\n        PROVIDE(__init_array_end = .);\r\n    } > flash\r\n\r\n    destructors : ALIGN(4) SUBALIGN(4) FLAGS(ax)\r\n    {\r\n        PROVIDE(__fini_array_start = .);\r\n        KEEP(*(.fini_array))\r\n        KEEP(*(SORT(.fini_array.*)))\r\n        PROVIDE(__fini_array_end = .);\r\n    } > flash\r\n\r\n    .text_vle : ALIGN(16) SUBALIGN(16) FLAGS(axv)\r\n    {\r\n        *(.text_vle)\r\n        *(.text_vle.*)\r\n        *(.gnu.linkonce.t_vle.*)\r\n    } > flash\r\n\r\n    .text : ALIGN(16) SUBALIGN(16) FLAGS(ax)\r\n    {\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.gnu.linkonce.t.*)\r\n    } > flash\r\n\r\n    .rodata : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.rodata1)\r\n    } > flash\r\n\r\n    .sdata2 : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        __sdata2_start__ = . + 0x8000;\r\n        *(.sdata2)\r\n        *(.sdata2.*)\r\n        *(.gnu.linkonce.s2.*)\r\n        *(.sbss2)\r\n        *(.sbss2.*)\r\n        *(.gnu.linkonce.sb2.*)\r\n    } > flash\r\n\r\n    .eh_frame_hdr :\r\n    {\r\n        *(.eh_frame_hdr)\r\n    } > flash\r\n\r\n    .eh_frame : ONLY_IF_RO\r\n    {\r\n        *(.eh_frame)\r\n    } > flash\r\n\r\n    .romdata : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        __romdata_start__ = .;\r\n    } > flash\r\n\r\n    .data : AT(__romdata_start__)\r\n    {\r\n        . = ALIGN(4);\r\n        __data_start__ = .;\r\n        *(.data)\r\n        *(.data.*)\r\n        *(.gnu.linkonce.d.*)\r\n        __sdata_start__ = . + 0x8000;\r\n        *(.sdata)\r\n        *(.sdata.*)\r\n        *(.gnu.linkonce.s.*)\r\n        __data_end__ = .;\r\n    } > ram\r\n\r\n    .sbss :\r\n    {\r\n        __bss_start__ = .;\r\n        *(.sbss)\r\n        *(.sbss.*)\r\n        *(.gnu.linkonce.sb.*)\r\n        *(.scommon)\r\n    } > ram\r\n\r\n    .bss :\r\n    {\r\n        *(.bss)\r\n        *(.bss.*)\r\n        *(.gnu.linkonce.b.*)\r\n        *(COMMON)\r\n        __bss_end__ = .;\r\n    } > ram\r\n\r\n    __heap_base__   = __bss_end__;\r\n    __heap_end__    = __ram_end__ - __stacks_total_size__;\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"34ca7347a2778b21f2d81d0019f306983f8fe23e","subject":"tests: remove incorrect comment from code_relocation for RISCV","message":"tests: remove incorrect comment from code_relocation for RISCV\n\nThis was copied from the ARM version of the test's linker script, which\nin turn seems to have been copied from another linker script at some\npoint. Remove the incorrect comment.\n\nSigned-off-by: Peter Marheine <ef0b2c492edde94778d7465bfbaeed52c5be6858@chromium.org>\n","repos":"finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"tests\/application_development\/code_relocation\/linker_riscv_qemu_sram2.ld","new_file":"tests\/application_development\/code_relocation\/linker_riscv_qemu_sram2.ld","new_contents":"\/*\n * Copyright 2022 The Chromium OS Authors\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/** enable CONFIG_SRAM2 or any other partition in soc Kconfig,\n * this is just an example to show relocation of code\/data\/bss script\n *\/\n#define _SRAM2_DATA_SECTION_NAME  .sram2_data\n#define _SRAM2_BSS_SECTION_NAME   .sram2_bss\n#define _SRAM2_TEXT_SECTION_NAME  .sram2_text\n#define SRAM2_ADDR  (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2)\n\n#define RAM_SIZE2 (CONFIG_SRAM_SIZE * 512)\nMEMORY\n    {\n    SRAM2                  (wx) : ORIGIN = (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2), LENGTH = RAM_SIZE2\n    }\n\n#include <zephyr\/arch\/riscv\/common\/linker.ld>\n","old_contents":"\/*\n * Copyright 2022 The Chromium OS Authors\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/** enable CONFIG_SRAM2 or any other partition in soc Kconfig,\n * this is just an example to show relocation of code\/data\/bss script\n *\/\n#define _SRAM2_DATA_SECTION_NAME  .sram2_data\n#define _SRAM2_BSS_SECTION_NAME   .sram2_bss\n#define _SRAM2_TEXT_SECTION_NAME  .sram2_text\n#define SRAM2_ADDR  (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2)\n\n#define RAM_SIZE2 (CONFIG_SRAM_SIZE * 512)\nMEMORY\n    {\n    SRAM2                  (wx) : ORIGIN = (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2), LENGTH = RAM_SIZE2\n    }\n\n#include <zephyr\/arch\/riscv\/common\/linker.ld>\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e1931b14b0575d557b59bc1f2bc186a47f26a138","subject":"Bump code size region for more TFLM growth.","message":"Bump code size region for more TFLM growth.\n\nSigned-off-by: Tim Callahan <ea16a3c075a6a229c9a452aa4faba7441b41c040@google.com>\n","repos":"google\/CFU-Playground,google\/CFU-Playground,google\/CFU-Playground,google\/CFU-Playground","old_file":"common\/_hps\/hps\/ld\/linker.ld","new_file":"common\/_hps\/hps\/ld\/linker.ld","new_contents":"INCLUDE output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE regions.ld\n\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(SORT(.text.start))\n\t\t*(SORT(.text))\n\t\t*(SORT(.stub))\n\t\t*(SORT(.text.*))\n\t\t*(SORT(.gnu.linkonce.t.*))\n\t\t_etext = .;\n\t} > rom\n\n\t.rodata :\n\t{\n\t\t\/*\n\t\t * Align models and large chunks of data into a constant position\n\t\t *\/\n\t\t. = _ftext + 0x98000;\n\t\t_frodata = .;\n\t\tsrc\/models\/*\/*(SORT(.rodata.*))\n\t\tsrc\/conv2d_??.o(SORT(.rodata.*))  \/* specific to hps_accel *\/\n\t\t. = ALIGN(4096);\n\t\t*(SORT(.rodata))\n\t\t*(SORT(.rodata.*))\n\t\t*(SORT(.gnu.linkonce.r.*))\n\t\t*(SORT(.rodata1))\n\t\t*(SORT(.srodata))\n\t\t*(SORT(.srodata.*))\n\t\t. = ALIGN(8);\n\t\t_erodata = .;\n\t} > rom\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(8);\n\t\t_fdata = .;\n\t\t*(SORT(.data))\n\t\t*(SORT(.data.*))\n\t\t*(SORT(.gnu.linkonce.d.*))\n\t\t*(SORT(.data1))\n\t\t*(SORT(.ramtext))\n\t\t*(SORT(.ramtext.*))\n\t\t_gp = ALIGN(16);\n\t\t*(SORT(.sdata))\n\t\t*(SORT(.sdata.*))\n\t\t*(SORT(.gnu.linkonce.s.*))\n\t\t*(SORT(.sdata2))\n\t\t*(SORT(.sdata2.*))\n\t\t_edata = ALIGN(16); \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss : AT (ADDR(.data) + SIZEOF (.data))\n\t{\n\t\t. = ALIGN(16);\n\t\t_fbss = .;\n\t\t*(SORT(.dynsbss))\n\t\t*(SORT(.sbss))\n\t\t*(SORT(.sbss.*))\n\t\t*(SORT(.gnu.linkonce.sb.*))\n\t\t*(SORT(.scommon))\n\t\t*(SORT(.dynbss))\n\t\t*(SORT(.bss))\n\t\t*(SORT(.bss.*))\n\t\t*(SORT(.gnu.linkonce.b.*))\n\t\t*(SORT(COMMON))\n\t\t. = ALIGN(8);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n\n        .arena (NOLOAD) :\n        {\n                _farena = .;\n                *(.arena)\n                _earena = .;\n        } > arena\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","old_contents":"INCLUDE output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE regions.ld\n\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(SORT(.text.start))\n\t\t*(SORT(.text))\n\t\t*(SORT(.stub))\n\t\t*(SORT(.text.*))\n\t\t*(SORT(.gnu.linkonce.t.*))\n\t\t_etext = .;\n\t} > rom\n\n\t.rodata :\n\t{\n\t\t\/*\n\t\t * Align models and large chunks of data into a constant position\n\t\t *\/\n\t\t. = _ftext + 0x86000;\n\t\t_frodata = .;\n\t\tsrc\/models\/*\/*(SORT(.rodata.*))\n\t\tsrc\/conv2d_??.o(SORT(.rodata.*))  \/* specific to hps_accel *\/\n\t\t. = ALIGN(4096);\n\t\t*(SORT(.rodata))\n\t\t*(SORT(.rodata.*))\n\t\t*(SORT(.gnu.linkonce.r.*))\n\t\t*(SORT(.rodata1))\n\t\t*(SORT(.srodata))\n\t\t*(SORT(.srodata.*))\n\t\t. = ALIGN(8);\n\t\t_erodata = .;\n\t} > rom\n\n\t.data : AT (ADDR(.rodata) + SIZEOF (.rodata))\n\t{\n\t\t. = ALIGN(8);\n\t\t_fdata = .;\n\t\t*(SORT(.data))\n\t\t*(SORT(.data.*))\n\t\t*(SORT(.gnu.linkonce.d.*))\n\t\t*(SORT(.data1))\n\t\t*(SORT(.ramtext))\n\t\t*(SORT(.ramtext.*))\n\t\t_gp = ALIGN(16);\n\t\t*(SORT(.sdata))\n\t\t*(SORT(.sdata.*))\n\t\t*(SORT(.gnu.linkonce.s.*))\n\t\t*(SORT(.sdata2))\n\t\t*(SORT(.sdata2.*))\n\t\t_edata = ALIGN(16); \/* Make sure _edata is >= _gp. *\/\n\t} > sram\n\n\t.bss : AT (ADDR(.data) + SIZEOF (.data))\n\t{\n\t\t. = ALIGN(16);\n\t\t_fbss = .;\n\t\t*(SORT(.dynsbss))\n\t\t*(SORT(.sbss))\n\t\t*(SORT(.sbss.*))\n\t\t*(SORT(.gnu.linkonce.sb.*))\n\t\t*(SORT(.scommon))\n\t\t*(SORT(.dynbss))\n\t\t*(SORT(.bss))\n\t\t*(SORT(.bss.*))\n\t\t*(SORT(.gnu.linkonce.b.*))\n\t\t*(SORT(COMMON))\n\t\t. = ALIGN(8);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n\n        .arena (NOLOAD) :\n        {\n                _farena = .;\n                *(.arena)\n                _earena = .;\n        } > arena\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"622e24ad6cde62470c0cea18addd8a760e3082cb","subject":"Disable backtick references for now. See stevedonovan\/LDoc#206","message":"Disable backtick references for now. See stevedonovan\/LDoc#206\n","repos":"deepakjois\/luaharfbuzz,deepakjois\/luaharfbuzz","old_file":"config.ld","new_file":"config.ld","new_contents":"project = 'luaharfbuzz'\ndescription = 'Lua bindings to Harfbuzz'\nfull_description = 'The documentation is available on the @{https:\/\/github.com\/deepakjois\/luaharfbuzz\/wiki|wiki}'\nuse_markdown_titles = true\nbacktick_references = false\ntitle = 'luaharfbuzz Documentation'\nfile = 'src\/harfbuzz.luadoc'\nexamples = 'examples'\nformat = 'markdown'\n","old_contents":"project = 'luaharfbuzz'\ndescription = 'Lua bindings to Harfbuzz'\nfull_description = 'The documentation is available on the @{https:\/\/github.com\/deepakjois\/luaharfbuzz\/wiki|wiki}'\nuse_markdown_titles = true\ntitle = 'luaharfbuzz Documentation'\nfile = 'src\/harfbuzz.luadoc'\nexamples = 'examples'\nformat = 'markdown'\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3f16fdefbf30d906f2999ad35104b757138c6c1b","subject":"riscv: linker: fix duplicate symbol when CONFIG_USERSPACE=y","message":"riscv: linker: fix duplicate symbol when CONFIG_USERSPACE=y\n\n_image_ram_start symbol is duplicate in CONFIG_USERSPACE. This symbol\nshould be at the start of app_smem in userspace, so remove another\nsymbol in CONFIG_USERSPACE.\n\nSigned-off-by: Jim Shu <1635390bb889c4cdee38f53a57b0915ac07d9bd9@andestech.com>\n","repos":"zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE);\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n#if !defined(CONFIG_USERSPACE)\n\t\t _image_ram_start = .;\n#endif \/* CONFIG_USERSPACE *\/\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ce1c5d7ccd324bbad3605cb1d6f0a8473d4001c4","subject":"Add new and delete operators to the stable delegate linker script.","message":"Add new and delete operators to the stable delegate linker script.\n\nThis adds new and delete operators to the list of symbols that we keep\nwhen building the sample stable delegate.  Those end up defined as weak\nsymbols in the stable delegate, and we need to ensure those get bound to\nthe same symbol for the stable delegate as for the main executable,\nsince data that is allocated by the stable delegate may be deallocated\nelsewhere.\n\nPiperOrigin-RevId: 490873417\n","repos":"tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow","old_file":"tensorflow\/lite\/delegates\/utils\/experimental\/sample_stable_delegate\/version_script.lds","new_file":"tensorflow\/lite\/delegates\/utils\/experimental\/sample_stable_delegate\/version_script.lds","new_contents":"VERS_1.0 {\n  # Export the stable delegate API.\n  global:\n    # Export stable delegate symbol.\n    extern \"C\" {\n      TFL_TheStableDelegate;\n    };\n\n    # Export operator new\/delete.  These are defined as weak symbols and we need to keep these\n    # symbols to ensure that if the main binary overrides these, we use the same version in the\n    # stable delegate, since data that is allocated by stable delegate may be deallocated elsewhere.\n    extern \"C++\" {\n      # The syntax here is a bit awkward.  Here we want to match against a demangled symbol name\n      # that contains spaces, but we also want to use glob-style pattern matching.\n      # The linker script syntax doesn't allow spaces in symbol names unless quoted;\n      # but if you do quote the symbol name, then it doesn't do glob-style pattern matching.\n      # So we can't use quotes.  Instead we just use the wildcard character \"?\" to match space,\n      # which is not ideal, since it would also match any other character.  But these patterns\n      # are nevertheless sufficiently unique that they are unlikely to match any symbols other\n      # than the overloaded global ::operator new and ::operator delete functions.\n      operator?new*;\n      operator?delete*;\n\n      # Currently the demangler doesn't output the leading \"::\" for global symbols.\n      # But just in case a future symbol demangler outputs the leading \"::\",\n      # we also export those names too...\n      ::operator?new*;\n      ::operator?delete*;\n    };\n\n  # Hide everything else.\n  local:\n    *;\n};\n","old_contents":"VERS_1.0 {\n  # Export vendor delegate symbol only.\n  global:\n    TFL_TheStableDelegate;\n\n  # Hide everything else.\n  local:\n    *;\n};\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"974946916b6aacb2c01bc726c9bf77bdc5e6a0a3","subject":"add licence information in the linker file","message":"add licence information in the linker file\n","repos":"PRIArobotics\/HedgehogLightFirmware,PRIArobotics\/STM32Template,PRIArobotics\/HedgehogLightFirmware","old_file":"system\/STM32F401XB_FLASH.ld","new_file":"system\/STM32F401XB_FLASH.ld","new_contents":"\/*\n*   Originally from\n*   https:\/\/developer.mbed.org\/users\/mbed_official\/code\/mbed-src\/file\/a11c0372f0ba\/targets\/cmsis\/TARGET_STM\/TARGET_STM32F4\/TARGET_NUCLEO_F401RE\/TOOLCHAIN_GCC_ARM\/STM32F401XE.ld\n*   Where it is available under the Apache Licence, V2\n*   https:\/\/developer.mbed.org\/handbook\/Apache-Licence\n*   Modified for STM32F401xB (128K Flash, 64K RAM)\n*\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 64K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/*\n*   Originally from https:\/\/developer.mbed.org\/users\/mbed_official\/code\/mbed-src\/file\/a11c0372f0ba\/targets\/cmsis\/TARGET_STM\/TARGET_STM32F4\/TARGET_NUCLEO_F401RE\/TOOLCHAIN_GCC_ARM\/STM32F401XE.ld\n*   Modified for STM32F401xB (128K Flash, 64K RAM)\n*\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 64K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"08a3db94f2a36c28278922732bc281c1722ceb18","subject":"m68k: Add NOTES to init data so its discarded at boot","message":"m68k: Add NOTES to init data so its discarded at boot\n\nAdd .note.gnu.build-id to init data so it's discarded at boot.\n\n[Andreas Schwab] Use NOTES macro\n\nSigned-off-by: Roman Zippel <f9f6ad990b4a8c1974dc6544787c1cc3570b6f00@linux-m68k.org>\nSigned-off-by: Geert Uytterhoeven <0da414d9d963da4039c2a0525b1844228075aa58@linux-m68k.org>\nSigned-off-by: Linus Torvalds <69652caca27c8b940640ad396ab71f93cacec34f@linux-foundation.org>\n","repos":"KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas","old_file":"arch\/m68k\/kernel\/vmlinux-std.lds","new_file":"arch\/m68k\/kernel\/vmlinux-std.lds","new_contents":"\/* ld script to make m68k Linux kernel *\/\n\n#include <asm-generic\/vmlinux.lds.h>\n#include <asm\/page.h>\n\nOUTPUT_FORMAT(\"elf32-m68k\", \"elf32-m68k\", \"elf32-m68k\")\nOUTPUT_ARCH(m68k)\nENTRY(_start)\njiffies = jiffies_64 + 4;\nSECTIONS\n{\n  . = 0x1000;\n  _text = .;\t\t\t\/* Text and read-only data *\/\n  .text : {\n\t*(.text.head)\n\tTEXT_TEXT\n\tSCHED_TEXT\n\tLOCK_TEXT\n\t*(.fixup)\n\t*(.gnu.warning)\n\t} :text = 0x4e75\n\n  _etext = .;\t\t\t\/* End of text section *\/\n\n  . = ALIGN(16);\t\t\/* Exception table *\/\n  __start___ex_table = .;\n  __ex_table : { *(__ex_table) }\n  __stop___ex_table = .;\n\n  RODATA\n\n  .data : {\t\t\t\/* Data *\/\n\tDATA_DATA\n\tCONSTRUCTORS\n\t}\n\n  . = ALIGN(16);\n  .data.cacheline_aligned : { *(.data.cacheline_aligned) }\n\n  .bss : { *(.bss) }\t\t\/* BSS *\/\n\n  _edata = .;\t\t\t\/* End of data section *\/\n\n  \/* will be freed after init *\/\n  . = ALIGN(PAGE_SIZE);\t\t\/* Init code and data *\/\n  __init_begin = .;\n  .init.text : {\n\t_sinittext = .;\n\tINIT_TEXT\n\t_einittext = .;\n  } :data\n  .init.data : { INIT_DATA }\n  . = ALIGN(16);\n  __setup_start = .;\n  .init.setup : { *(.init.setup) }\n  __setup_end = .;\n  __initcall_start = .;\n  .initcall.init : {\n\tINITCALLS\n  }\n  __initcall_end = .;\n  __con_initcall_start = .;\n  .con_initcall.init : { *(.con_initcall.init) }\n  __con_initcall_end = .;\n  .m68k_fixup : {\n\t__start_fixup = .;\n\t*(.m68k_fixup)\n\t__stop_fixup = .;\n  }\n  SECURITY_INIT\n#ifdef CONFIG_BLK_DEV_INITRD\n  . = ALIGN(8192);\n  __initramfs_start = .;\n  .init.ramfs : { *(.init.ramfs) }\n  __initramfs_end = .;\n#endif\n  NOTES\n  . = ALIGN(8192);\n  __init_end = .;\n\n  .data.init_task : { *(.data.init_task) }\t\/* The initial task and kernel stack *\/\n\n  _end = . ;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ : {\n\tEXIT_TEXT\n\tEXIT_DATA\n\t*(.exitcall.exit)\n\t}\n\n  \/* Stabs debugging sections.  *\/\n  .stab 0 : { *(.stab) }\n  .stabstr 0 : { *(.stabstr) }\n  .stab.excl 0 : { *(.stab.excl) }\n  .stab.exclstr 0 : { *(.stab.exclstr) }\n  .stab.index 0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment 0 : { *(.comment) }\n}\n","old_contents":"\/* ld script to make m68k Linux kernel *\/\n\n#include <asm-generic\/vmlinux.lds.h>\n#include <asm\/page.h>\n\nOUTPUT_FORMAT(\"elf32-m68k\", \"elf32-m68k\", \"elf32-m68k\")\nOUTPUT_ARCH(m68k)\nENTRY(_start)\njiffies = jiffies_64 + 4;\nSECTIONS\n{\n  . = 0x1000;\n  _text = .;\t\t\t\/* Text and read-only data *\/\n  .text : {\n\t*(.text.head)\n\tTEXT_TEXT\n\tSCHED_TEXT\n\tLOCK_TEXT\n\t*(.fixup)\n\t*(.gnu.warning)\n\t} :text = 0x4e75\n\n  _etext = .;\t\t\t\/* End of text section *\/\n\n  . = ALIGN(16);\t\t\/* Exception table *\/\n  __start___ex_table = .;\n  __ex_table : { *(__ex_table) }\n  __stop___ex_table = .;\n\n  RODATA\n\n  .data : {\t\t\t\/* Data *\/\n\tDATA_DATA\n\tCONSTRUCTORS\n\t}\n\n  . = ALIGN(16);\n  .data.cacheline_aligned : { *(.data.cacheline_aligned) }\n\n  .bss : { *(.bss) }\t\t\/* BSS *\/\n\n  _edata = .;\t\t\t\/* End of data section *\/\n\n  \/* will be freed after init *\/\n  . = ALIGN(PAGE_SIZE);\t\t\/* Init code and data *\/\n  __init_begin = .;\n  .init.text : {\n\t_sinittext = .;\n\tINIT_TEXT\n\t_einittext = .;\n  } :data\n  .init.data : { INIT_DATA }\n  . = ALIGN(16);\n  __setup_start = .;\n  .init.setup : { *(.init.setup) }\n  __setup_end = .;\n  __initcall_start = .;\n  .initcall.init : {\n\tINITCALLS\n  }\n  __initcall_end = .;\n  __con_initcall_start = .;\n  .con_initcall.init : { *(.con_initcall.init) }\n  __con_initcall_end = .;\n  .m68k_fixup : {\n\t__start_fixup = .;\n\t*(.m68k_fixup)\n\t__stop_fixup = .;\n  }\n  SECURITY_INIT\n#ifdef CONFIG_BLK_DEV_INITRD\n  . = ALIGN(8192);\n  __initramfs_start = .;\n  .init.ramfs : { *(.init.ramfs) }\n  __initramfs_end = .;\n#endif\n  . = ALIGN(8192);\n  __init_end = .;\n\n  .data.init_task : { *(.data.init_task) }\t\/* The initial task and kernel stack *\/\n\n  _end = . ;\n\n  \/* Sections to be discarded *\/\n  \/DISCARD\/ : {\n\tEXIT_TEXT\n\tEXIT_DATA\n\t*(.exitcall.exit)\n\t}\n\n  \/* Stabs debugging sections.  *\/\n  .stab 0 : { *(.stab) }\n  .stabstr 0 : { *(.stabstr) }\n  .stab.excl 0 : { *(.stab.excl) }\n  .stab.exclstr 0 : { *(.stab.exclstr) }\n  .stab.index 0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment 0 : { *(.comment) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"014b6d6dc4b7b6a73b956ed20bdf92c3892a3cba","subject":"cm3 flash start address changed to 08000000","message":"cm3 flash start address changed to 08000000\n","repos":"gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins","old_file":"ilg.gnuarmeclipse.managedbuild.cross\/templates\/projecttemplates\/HelloWorld_CM3_C_Project\/ldscripts\/mem.ld","new_file":"ilg.gnuarmeclipse.managedbuild.cross\/templates\/projecttemplates\/HelloWorld_CM3_C_Project\/ldscripts\/mem.ld","new_contents":"\/* Linker script to configure memory regions. \n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 20K\n}\n","old_contents":"\/* Linker script to configure memory regions. \n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 20K\n}\n","returncode":0,"stderr":"","license":"epl-1.0","lang":"Linker Script"}
{"commit":"96fa20491a1eeb1b3c9c41023a87f24f2f627770","subject":"add sanity checks to the linker scripts","message":"add sanity checks to the linker scripts\n\nthis ensures the binaries we produce obey the target device layout.\n","repos":"japaric\/cu,japaric\/cu","old_file":"common.ld","new_file":"common.ld","new_contents":"__DATA_LOAD = LOADADDR(.data);\n\nSECTIONS\n{\n    .text : ALIGN(4)\n    {\n        link_exceptions_start = .;\n        KEEP(*(.exceptions))\n        link_exceptions_end = .;\n        link_interrupts_start = .;\n        KEEP(*(.interrupts))\n        link_interrupts_end = .;\n        *(.text*)\n    } > rom\n\n    .data : ALIGN(4)\n    {\n      __DATA_START = .;\n      *(.data*)\n      . = ALIGN(4);\n      __DATA_END = .;\n    } > ram AT > rom\n\n    \/DISCARD\/ :\n    {\n      *(.ARM.exidx*)\n      *(.note.gnu.build-id*)\n    }\n\n    __STACK_START = ORIGIN(ram) + LENGTH(ram);\n}\n\n\/* Sanity checks *\/\nASSERT ( link_exceptions_start == ORIGIN(rom), \"exceptions not where expected\" );\nASSERT ( link_interrupts_start - ORIGIN(rom) == 0x40, \"interrupts not where expected\" );\nASSERT ( link_exceptions_start < link_exceptions_end, \"exceptions not linked in\" );\nASSERT ( link_interrupts_start < link_interrupts_end, \"interrupts not linked in\" );\n","old_contents":"__DATA_LOAD = LOADADDR(.data);\n\nSECTIONS\n{\n    .text : ALIGN(4)\n    {\n        KEEP(*(.exceptions))\n        KEEP(*(.interrupts))\n        *(.text*)\n    } > rom\n\n    .data : ALIGN(4)\n    {\n      __DATA_START = .;\n      *(.data*)\n      . = ALIGN(4);\n      __DATA_END = .;\n    } > ram AT > rom\n\n    \/DISCARD\/ :\n    {\n      *(.ARM.exidx*)\n      *(.note.gnu.build-id*)\n    }\n\n    __STACK_START = ORIGIN(ram) + LENGTH(ram);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e4ba75652de2495dc9efa5797a3a28d85aed185f","subject":"Fixed missing iram0.text segment.","message":"Fixed missing iram0.text segment.\n\nTrust me, without this things behave *very* strangely!\n","repos":"funshine\/nodemcu-firmware,remspoor\/nodemcu-firmware,eku\/nodemcu-firmware,remspoor\/nodemcu-firmware,eku\/nodemcu-firmware,FelixPe\/nodemcu-firmware,bhrt\/nodeMCU,vowstar\/nodemcu-firmware,petrkr\/nodemcu-firmware,devsaurus\/nodemcu-firmware,bogvak\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,vsky279\/nodemcu-firmware,djphoenix\/nodemcu-firmware,christakahashi\/nodemcu-firmware,Alkorin\/nodemcu-firmware,jmattsson\/nodemcu-firmware,jmattsson\/nodemcu-firmware,raburton\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,bhrt\/nodeMCU,remspoor\/nodemcu-firmware,vowstar\/nodemcu-firmware,karrots\/nodemcu-firmware,nwf\/nodemcu-firmware,dnc40085\/nodemcu-firmware,vowstar\/nodemcu-firmware,Alkorin\/nodemcu-firmware,FrankX0\/nodemcu-firmware,TerryE\/nodemcu-firmware,devsaurus\/nodemcu-firmware,dnc40085\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,shangwudong\/MyNodeMcu,fetchbot\/nodemcu-firmware,christakahashi\/nodemcu-firmware,Alkorin\/nodemcu-firmware,karrots\/nodemcu-firmware,FrankX0\/nodemcu-firmware,Alkorin\/nodemcu-firmware,nwf\/nodemcu-firmware,TerryE\/nodemcu-firmware,jmattsson\/nodemcu-firmware,oyooyo\/nodemcu-firmware,dnc40085\/nodemcu-firmware,dnc40085\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,romanchyla\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,shangwudong\/MyNodeMcu,luizfeliperj\/nodemcu-firmware,mikeller\/nodemcu-firmware,raburton\/nodemcu-firmware,zhujunsan\/nodemcu-firmware,karrots\/nodemcu-firmware,vsky279\/nodemcu-firmware,nwf\/nodemcu-firmware,nodemcu\/nodemcu-firmware,karrots\/nodemcu-firmware,fetchbot\/nodemcu-firmware,vsky279\/nodemcu-firmware,shangwudong\/MyNodeMcu,FelixPe\/nodemcu-firmware,nodemcu\/nodemcu-firmware,funshine\/nodemcu-firmware,nodemcu\/nodemcu-firmware,zhujunsan\/nodemcu-firmware,nwf\/nodemcu-firmware,FrankX0\/nodemcu-firmware,funshine\/nodemcu-firmware,nodemcu\/nodemcu-firmware,vsky279\/nodemcu-firmware,raburton\/nodemcu-firmware,shangwudong\/MyNodeMcu,oyooyo\/nodemcu-firmware,djphoenix\/nodemcu-firmware,eku\/nodemcu-firmware,jmattsson\/nodemcu-firmware,nodemcu\/nodemcu-firmware,TerryE\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,bhrt\/nodeMCU,shangwudong\/MyNodeMcu,TerryE\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,mikeller\/nodemcu-firmware,FelixPe\/nodemcu-firmware,bogvak\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,Alkorin\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,romanchyla\/nodemcu-firmware,vsky279\/nodemcu-firmware,devsaurus\/nodemcu-firmware,dnc40085\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,christakahashi\/nodemcu-firmware,devsaurus\/nodemcu-firmware,petrkr\/nodemcu-firmware,karrots\/nodemcu-firmware,jmattsson\/nodemcu-firmware,FrankX0\/nodemcu-firmware,TerryE\/nodemcu-firmware,mikeller\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,nwf\/nodemcu-firmware,petrkr\/nodemcu-firmware,funshine\/nodemcu-firmware,bogvak\/nodemcu-firmware,funshine\/nodemcu-firmware,oyooyo\/nodemcu-firmware,christakahashi\/nodemcu-firmware,zhujunsan\/nodemcu-firmware,bhrt\/nodeMCU,romanchyla\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,fetchbot\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,djphoenix\/nodemcu-firmware,remspoor\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,christakahashi\/nodemcu-firmware,petrkr\/nodemcu-firmware,oyooyo\/nodemcu-firmware,petrkr\/nodemcu-firmware,fetchbot\/nodemcu-firmware,eku\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,bhrt\/nodeMCU,FrankX0\/nodemcu-firmware,djphoenix\/nodemcu-firmware,devsaurus\/nodemcu-firmware,FelixPe\/nodemcu-firmware,FelixPe\/nodemcu-firmware,remspoor\/nodemcu-firmware","old_file":"ld\/eagle.app.v6.ld","new_file":"ld\/eagle.app.v6.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40210000, len = 0x80000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(user_start_trampoline)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n    *(.rodata*)\n    *(.sdk.version)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_used_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.gnu.linkonce.r.*)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram0.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                        org = 0x3FF00000, len = 0x10\n  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                         org = 0x40100000, len = 0x8000\n  irom0_0_seg :                         org = 0x40210000, len = 0x80000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(user_start_trampoline)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n    *(.rodata*)\n    *(.sdk.version)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_used_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.gnu.linkonce.r.*)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5a8b389a412d74f248579b7d5401e42a42b3ada2","subject":"- new 3.0.6 kernel load script","message":"- new 3.0.6 kernel load script\n","repos":"0x7678\/openss7,kerr-huang\/openss7,openss7\/openss7,kerr-huang\/openss7,openss7\/openss7,openss7\/openss7,0x7678\/openss7,0x7678\/openss7,0x7678\/openss7,kerr-huang\/openss7,openss7\/openss7,kerr-huang\/openss7,openss7\/openss7,0x7678\/openss7,kerr-huang\/openss7,kerr-huang\/openss7,openss7\/openss7,0x7678\/openss7,openss7\/openss7,0x7678\/openss7,kerr-huang\/openss7,openss7\/openss7,kerr-huang\/openss7,0x7678\/openss7","old_file":"scripts\/hot.lds","new_file":"scripts\/hot.lds","new_contents":"SECTIONS\n{\n\t\/DISCARD\/\t\t: { *(.discard) }\n\n\t.text\t\t\t: { *(.text.streams.hot.put)\n\t\t\t\t    *(.text.streams.hot.write)\n\t\t\t\t    *(.text.streams.hot.out)\n\t\t\t\t    *(.text.streams.hot)\n\t\t\t\t    *(.text.streams.hot.in)\n\t\t\t\t    *(.text.streams.hot.read)\n\t\t\t\t    *(.text.streams.hot.get)\n\t\t\t\t    *(.text)\n\t\t\t\t    *(.text.streams.unlikely) }\n\/*\n\t.text.unlikely\t\t: { *(.text.streams.unlikely)\t\t*(.text.unlikely)\t}\n *\/\n\t__ksymtab\t\t: { *(SORT(___ksymtab+*))\t\t*(__ksymtab)\t\t}\n\t__ksymtab_gpl\t\t: { *(SORT(___ksymtab_gpl+*))\t\t*(__ksymtab_gpl)\t}\n\t__ksymtab_unused\t: { *(SORT(___ksymtab_unused+*))\t*(__ksymtab_unused)\t}\n\t__ksymtab_unused_gpl\t: { *(SORT(___ksymtab_unused_gpl+*))\t*(__ksymtab_unused_gpl)\t}\n\t__ksymtab_gpl_future\t: { *(SORT(___ksymtab_gpl_future+*))\t*(__ksymtab_gpl_future)\t}\n\t__kcrctab\t\t: { *(SORT(___kcrctab+*))\t\t*(__kcrctab)\t\t}\n\t__kcrctab_gpl\t\t: { *(SORT(___kcrctab_gpl+*))\t\t*(__kcrctab_gpl)\t}\n\t__kcrctab_unused\t: { *(SORT(___kcrctab_unused+*))\t*(__kcrctab_unused)\t}\n\t__kcrctab_unused_gpl\t: { *(SORT(___kcrctab_unused_gpl+*))\t*(__kcrctab_unused_gpl)\t}\n\t__kcrctab_gpl_future\t: { *(SORT(___kcrctab_gpl_future+*))\t*(__kcrctab_gpl_future)\t}\n}\n","old_contents":"SECTIONS\n{\n\t.text :\n\t{\n\t\t*(.text.streams.hot.put)\n\t\t*(.text.streams.hot.write)\n\t\t*(.text.streams.hot.out)\n\t\t*(.text.streams.hot)\n\t\t*(.text.streams.hot.in)\n\t\t*(.text.streams.hot.read)\n\t\t*(.text.streams.hot.get)\n\t\t*(.text)\n\t\t*(.text.streams.unlikely)\n\t}\n}\n","returncode":0,"stderr":"","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"b7714d64560b229df8b4455f38abc831e66c4259","subject":"Provide explicit symbols for start and end of bss and data regions","message":"Provide explicit symbols for start and end of bss and data regions\n","repos":"smaccm\/camkes-tool,smaccm\/camkes-tool,smaccm\/camkes-tool,smaccm\/camkes-tool","old_file":"camkes\/templates\/linker.lds","new_file":"camkes\/templates\/linker.lds","new_contents":"\/*#\n *# Copyright 2014, NICTA\n *#\n *# This software may be distributed and modified according to the terms of\n *# the BSD 2-Clause license. Note that NO WARRANTY is provided.\n *# See \"LICENSE_BSD2.txt\" for details.\n *#\n *# @TAG(NICTA_BSD)\n #*\/\n\n\/* Linker script for CAmkES components. *\/\nENTRY(_start)\n\nSECTIONS {\n    \/* __executable_start is required by libsel4platsupport. *\/\n    PROVIDE (__executable_start = 0x100000);\n    . = 0x100000;\n\n    \/* Code. *\/\n    .text : ALIGN(4096) {\n        *(.text*)\n    }\n\n    \/* Read Only Data. *\/\n    .rodata : ALIGN(4096) {\n        *(.rodata*)\n    }\n\n    \/*- if arch == 'aarch32' or arch == 'arm_hyp' -*\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n    PROVIDE_HIDDEN (__exidx_end = .);\n    \/*- endif -*\/\n\n    \/* Data \/ BSS *\/\n    .data : ALIGN(4096) {\n        PROVIDE(__data_start = .);\n        *(.data)\n        PROVIDE(__data_end = .);\n    }\n\n    .bss : {\n        PROVIDE(__bss_start = .);\n        *(.bss)\n        *(COMMON)\n        PROVIDE(__bss_end = .);\n    }\n\n    guarded (NOLOAD) : ALIGN(4096) {\n        *(guarded)\n    }\n\n    \/*- for c in composition.connections -*\/\n    \/*- if c.type.name == 'seL4SharedData' -*\/\n      \/*- if c.from_instance == me -*\/\n    shared_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000) {\n        *(shared_\/*? c.from_interface.name ?*\/)\n    }\n      \/*- endif -*\/\n      \/*- if c.to_instance == me -*\/\n    shared_\/*? c.to_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000) {\n        *(shared_\/*? c.to_interface.name ?*\/)\n    }\n      \/*- endif -*\/\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    persistent (NOLOAD) : ALIGN(0x1000) {\n        *(persistent)\n    }\n\n    \/*- for c in composition.connections -*\/\n    \/*- if c.type.name == 'seL4HardwareMMIO' and c.from_instance == me -*\/\n    \/*- if arch == 'aarch32' or arch == 'arm_hyp' -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x100000) { \/*# ARM Section Size #*\/\n    \/*- else -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x400000) { \/*# IA32 4M Page Size #*\/\n    \/*- endif -*\/\n        *(ignore_\/*? c.from_interface.name ?*\/)\n    }\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    _end = .;\n}\n","old_contents":"\/*#\n *# Copyright 2014, NICTA\n *#\n *# This software may be distributed and modified according to the terms of\n *# the BSD 2-Clause license. Note that NO WARRANTY is provided.\n *# See \"LICENSE_BSD2.txt\" for details.\n *#\n *# @TAG(NICTA_BSD)\n #*\/\n\n\/* Linker script for CAmkES components. *\/\nENTRY(_start)\n\nSECTIONS {\n    \/* __executable_start is required by libsel4platsupport. *\/\n    PROVIDE (__executable_start = 0x100000);\n    . = 0x100000;\n\n    \/* Code. *\/\n    .text : ALIGN(4096) {\n        *(.text*)\n    }\n\n    \/* Read Only Data. *\/\n    .rodata : ALIGN(4096) {\n        *(.rodata*)\n    }\n\n    \/*- if arch == 'aarch32' or arch == 'arm_hyp' -*\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n    PROVIDE_HIDDEN (__exidx_end = .);\n    \/*- endif -*\/\n\n    \/* Data \/ BSS *\/\n    .data : ALIGN(4096) {\n        *(.data)\n    }\n\n    .bss : {\n        *(.bss)\n        *(COMMON)\n    }\n\n    guarded (NOLOAD) : ALIGN(4096) {\n        *(guarded)\n    }\n\n    \/*- for c in composition.connections -*\/\n    \/*- if c.type.name == 'seL4SharedData' -*\/\n      \/*- if c.from_instance == me -*\/\n    shared_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000) {\n        *(shared_\/*? c.from_interface.name ?*\/)\n    }\n      \/*- endif -*\/\n      \/*- if c.to_instance == me -*\/\n    shared_\/*? c.to_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000) {\n        *(shared_\/*? c.to_interface.name ?*\/)\n    }\n      \/*- endif -*\/\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    persistent (NOLOAD) : ALIGN(0x1000) {\n        *(persistent)\n    }\n\n    \/*- for c in composition.connections -*\/\n    \/*- if c.type.name == 'seL4HardwareMMIO' and c.from_instance == me -*\/\n    \/*- if arch == 'aarch32' or arch == 'arm_hyp' -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x100000) { \/*# ARM Section Size #*\/\n    \/*- else -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x400000) { \/*# IA32 4M Page Size #*\/\n    \/*- endif -*\/\n        *(ignore_\/*? c.from_interface.name ?*\/)\n    }\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    _end = .;\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"b6341d4f82ce1f125bbfadb120381f0f791628e1","subject":"templates.sifive\/sections.ld: local arch & device","message":"templates.sifive\/sections.ld: local arch & device\n","repos":"gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins","old_file":"bundles\/ilg.gnumcueclipse.templates.sifive\/templates\/sifive_exe_c_project\/ldscripts\/sections.ld","new_file":"bundles\/ilg.gnumcueclipse.templates.sifive\/templates\/sifive_exe_c_project\/ldscripts\/sections.ld","new_contents":"\/*\n * Default linker script.\n * \n * Static constructors\/destructors use the new .init_array\/.fini_array\n * definitions; the old .init\/.fini are no longer used.\n *\n * The heap starts immediately after the last statically allocated \n * .bss\/.noinit section (the _end symbol), and extends up to the stack.\n *\n * To make use of the multi-region initialisations, define\n * OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS for the _startup.cpp file.\n *\/\n\n\/*\n * Explicitly define the RISC-V architecture.\n *\/\nOUTPUT_ARCH( \"riscv\" )\n\n\/* \n * The entry point is informative, for debuggers and simulators, the\n * hardware has its own notion of the startup address.\n *\/\nENTRY(_start)\n\n\/*\n * The '__stack' definition is required by newlib crt0; do not remove it.\n * The stack is located at the very end of the RAM region.\n *\/\n__stack = ORIGIN(RAM) + LENGTH(RAM);\n__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n\n\/*\n * The ELF object file format uses program headers, also knows as segments.\n * The program headers describe how the program should be loaded into memory. \n * You can print them out by using the objdump program with the \u2018-p\u2019 option.\n *\/\nPHDRS\n{\n  phdr_flash PT_LOAD;\n  phdr_ram_init PT_LOAD;\n  phdr_ram PT_NULL;\n}\n\nSECTIONS\n{\n    \/*\n     * On RISC-V devices the startup address is a regular address, so this\n     * must be the very first section.\n     * Apart from the assembly code used to initialise the stack,\n     * do not place anything else into this section.\n     *\/ \n    .reset_entry : ALIGN(4)\n    {\n        KEEP(*(SORT_NONE(.reset_entry) SORT_NONE(.reset_entry.*)))\n    } >FLASH AT>FLASH :phdr_flash\n\n    \/* \n     * Dynamic Run Time Metadata.\n     * Normally the debugger reaches this section by resolving a symbol, \n     * but in case it should scan memory for the magic, better place this\n     * section as early as possible. \n     *\/\n    .drtm : ALIGN(4)\n    {\n        KEEP(*(.drtm .drtm.*))    \n    } >FLASH AT>FLASH :phdr_flash\n\n    \/*\n     * For convenience, place the trap code early.\n     *\/\n    .trap_entry : ALIGN(4)\n    {\n        *(.exceptions_array .exceptions_array.*)\n        *(.interrupts_local_arch_array .interrupts_local_arch_array.*)\n        *(.interrupts_local_device_array .interrupts_local_device_array.*)\n        *(.interrupts_global_array .interrupts_global_array.*)\n        *(.trap_entry .trap_entry.*)\n        *(.traps_handlers .traps_handlers.*)\n    } >FLASH AT>FLASH :phdr_flash\n\n    \/* \n     * Memory regions initialization arrays.\n     *\n     * There are two kinds of arrays for each RAM region, one for \n     * data and one for bss. Each is iterated at startup and the   \n     * region initialization is performed.\n     * \n     * The data array includes:\n     * - from (LOADADDR())\n     * - region_begin (ADDR())\n     * - region_end (ADDR()+SIZEOF())\n     *\n     * The bss array includes:\n     * - region_begin (ADDR())\n     * - region_end (ADDR()+SIZEOF())\n     *\n     * WARNING: It is mandatory that the regions are word aligned, \n     * since the initialization code works only on words.\n     *\/\n    .mem_inits : ALIGN(4)\n    {     \n        PROVIDE_HIDDEN(__data_regions_array_begin__ = .); \/* \u00b5OS++ specific. *\/\n        \n        LONG(LOADADDR(.data));\n        LONG(ADDR(.data));\n        LONG(ADDR(.data)+SIZEOF(.data));\n        \n        \/* If more DATA regions are needed, add more such records. *\/   \n             \n        PROVIDE_HIDDEN(__data_regions_array_end__ = .); \/* \u00b5OS++ specific. *\/\n        \n        PROVIDE_HIDDEN(__bss_regions_array_begin__ = .); \/* \u00b5OS++ specific. *\/\n        \n        LONG(ADDR(.bss));\n        LONG(ADDR(.bss)+SIZEOF(.bss));\n\n        \/* If more BSS regions are needed, add more such records. *\/   \n                \n        PROVIDE_HIDDEN(__bss_regions_array_end__ = .); \/* \u00b5OS++ specific. *\/\n    } >FLASH AT>FLASH :phdr_flash\n\n    \/*\n     * The preinit code, i.e. an array of pointers to initialization \n     * functions to be performed before constructors.\n     *\/\n    .preinit_array : ALIGN(4)\n    {\n        \/* \n         * PROVIDE not used intentionally, \n         * this symbol must not be used for other purposes. \n         *\/\n        __preinit_array_begin__ = .;    \/* \u00b5OS++ specific. *\/\n        \n        \/*\n         * Used to run the system inits before anything else.\n         *\/\n        KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))\n        \n        \/* \n         * Used for other platform inits.\n         *\/\n        KEEP(*(.preinit_array_platform .preinit_array_platform.*))\n        \n        \/*\n         * The application inits. If you need to enforce some order in \n         * execution, create new sections, as before.\n         *\/\n        KEEP(*(.preinit_array .preinit_array.*))\n\n        __preinit_array_end__ = .;     \/* \u00b5OS++ specific. *\/\n    } >FLASH AT>FLASH :phdr_flash\n\n    \/*\n     * The init code, i.e. an array of pointers to static constructors.\n     *\/\n    .init_array : ALIGN(4)\n    {\n        \/* PROVIDE not used intentionally, this symbol must not be used. *\/\n        __init_array_start = .;        \/* Standard newlib definition. *\/\n        __init_array_begin__ = .;    \/* \u00b5OS++ specific. *\/\n        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n        KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n        __init_array_end = .;        \/* Standard newlib definition. *\/\n        __init_array_end__ = .;        \/* \u00b5OS++ specific. *\/\n    } >FLASH AT>FLASH :phdr_flash\n\n    \/*\n     * The fini code, i.e. an array of pointers to static destructors.\n     *\/\n    .fini_array : ALIGN(4)\n    {\n        \/* PROVIDE not used intentionally, this symbol must not be used. *\/\n        __fini_array_start = .;        \/* Standard newlib definition. *\/\n        __fini_array_begin__ = .;    \/* \u00b5OS++ specific. *\/\n        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n        KEEP(*(.fini_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n        __fini_array_end = .;        \/* Standard newlib definition. *\/\n        __fini_array_end__ = .;        \/* \u00b5OS++ specific. *\/\n    } >FLASH AT>FLASH :phdr_flash\n    \n    \/*\n     * The program code.\n     *\/\n    .text : ALIGN(4)\n    {\n        *(.text.unlikely .text.unlikely.*)\n        *(.text.startup .text.startup.*)\n        *(.text .text.*)            \n           *(.gnu.linkonce.t.*)\n    } >FLASH AT>FLASH :phdr_flash\n\n    . = ALIGN(4);\n      PROVIDE(__etext = .);\n      PROVIDE(_etext = .);\n      PROVIDE(etext = .);\n \n    \/*\n     * C++ virtual tables.\n     *\/\n    .vtable : ALIGN(4)\n    {\n        KEEP(*(vtable))            \n    } >FLASH AT>FLASH :phdr_flash\n \n    \/*\n     * Exception frames.\n     *\/\n    .exceptions : ALIGN(4)\n    {\n        KEEP(*(.eh_frame*))\n        *(.gcc_except_table)\n    } >FLASH AT>FLASH :phdr_flash\n \n     \/*\n      * Read-only data (constants) \n      *\/\n    .rodata : ALIGN(4)\n    {\n        *(.rodata .rodata.*)         \n        *(.constdata .constdata.*)         \n        *(.gnu.linkonce.r.*)\n    } >FLASH AT>FLASH :phdr_flash\n\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n    \n    \/*\n     * The initialised data section.\n     *\n     * The program executes knowing that the data is in RAM\n     * but the loader puts the initial values in FLASH.\n     * The startup will copy the initial values from FLASH to RAM.\n     *\/\n    .data : ALIGN(4)\n    {\n        FILL(0xFF)\n        \n        __data_start__ = . ;            \/* Standard newlib definition. *\/\n        __data_begin__ = . ;            \/* \u00b5OS++ specific *\/\n        *(.data_begin .data_begin.*)    \/* \u00b5OS++ __data_begin_guard *\/\n\n        *(.data .data.*)\n        *(.gnu.linkonce.d.*)\n        \n        . = ALIGN(8);\n        \/* \n         * RISC-V specific; the compiler optimises memory accesses\n         * in the +\/- 2K range around __global_pointer$ to GP relative.\n         * For this to work, GP must be loaded during startup with the\n         * address of __global_pointer$.\n         * This optimisation favours a 4K range. Newlib places\n         * several impure and malloc pointers in the .sdata section.\n         *\/\n        PROVIDE( __global_pointer$ = . + (4K \/ 2) );\n        \n        *(.sdata .sdata.*)\n        *(.gnu.linkonce.s.*)\n\n        \/* RISC-V specific; not sure if needed. *\/\n        . = ALIGN(8);\n        *(.srodata.cst16)\n        *(.srodata.cst8)\n        *(.srodata.cst4)\n        *(.srodata.cst2)\n        *(.srodata .srodata.*)\n        \n        *(.data_end .data_end.*)        \/* \u00b5OS++ __data_end_guard; must be last *\/        \n        . = ALIGN(4);\n        __data_end__ = . ;                \/* Standard newlib definition. *\/\n    } >RAM AT>FLASH :phdr_ram_init\n\n    \/* \n     * This address is used by the \u00b5OS++ startup code to \n     * initialise the .data section.\n     *\/\n    __data_load_addr__ = LOADADDR(.data);\n\n      . = ALIGN(4);\n      PROVIDE( __edata = . );\n      PROVIDE( _edata = . );\n      PROVIDE( edata = . );\n    \n    \/*\n     * The uninitialised data sections. NOLOAD is used to avoid\n     * the \"section `.bss' type changed to PROGBITS\" warning\n     *\/\n\n    \/* The primary uninitialised data section. *\/\n    .bss (NOLOAD) : ALIGN(4)\n    {\n        __bss_start = .;                 \/* Standard newlib definition. *\/\n        __bss_start__ = .;                 \/* Standard newlib definition. *\/\n           __bss_begin__ = .;                 \/* \u00b5OS++ specific *\/\n         *(.bss_begin .bss_begin.*)     \/* \u00b5OS++ __bss_begin_guard *\/ \n\n        *(.sbss .sbss.*)\n        *(.gnu.linkonce.sb.*)\n        \n        *(.bss .bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        \n        *(.bss_end .bss_end.*)             \/* \u00b5OS++ __bss_end_guard; must be last *\/\n        . = ALIGN(4);\n        __bss_end__ = .;                \/* Standard newlib definition. *\/\n        __bss_end = .;                    \/* Standard newlib definition. *\/\n     } >RAM AT>RAM :phdr_ram\n\n    \/* \n     * Similar to .bss, but not initialised to zero. \u00b5OS++ extension.\n     *\/\n    .noinit (NOLOAD) : ALIGN(4)\n    {\n        __noinit_begin__ = .;            \/* \u00b5OS++ extension. *\/\n        \n        *(.noinit .noinit.*) \n        \n         . = ALIGN(4) ;\n        __noinit_end__ = .;               \/* \u00b5OS++ extension. *\/\n    } >RAM AT>RAM :phdr_ram\n    \n    \/* _sbrk() expects at least word alignment. *\/\n      . = ALIGN(8);\n    PROVIDE( __end = . );\n    PROVIDE( _end = . );\n    PROVIDE( end = . ); \n    \n    PROVIDE( __heap_begin__ = . );        \/* \u00b5OS++ extension. *\/\n    \n      .stack __stack - __stack_size :\n      {\n        PROVIDE( _heap_end = . );        \/* Standard newlib definition. *\/\n        PROVIDE( __heap_end__ = . );    \/* \u00b5OS++ extension. *\/\n        . += __stack_size;\n      } >RAM AT>RAM :phdr_ram\n    \n\n    \/* \n     * Stabs debugging sections.\n     *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \n    \/*\n     * DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  \n     *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }    \n}\n","old_contents":"\/*\n * Default linker script.\n * \n * Static constructors\/destructors use the new .init_array\/.fini_array\n * definitions; the old .init\/.fini are no longer used.\n *\n * The heap starts immediately after the last statically allocated \n * .bss\/.noinit section (the _end symbol), and extends up to the stack.\n *\n * To make use of the multi-region initialisations, define\n * OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS for the _startup.cpp file.\n *\/\n\n\/*\n * Explicitly define the RISC-V architecture.\n *\/\nOUTPUT_ARCH( \"riscv\" )\n\n\/* \n * The entry point is informative, for debuggers and simulators, the\n * hardware has its own notion of the startup address.\n *\/\nENTRY(_start)\n\n\/*\n * The '__stack' definition is required by newlib crt0; do not remove it.\n * The stack is located at the very end of the RAM region.\n *\/\n__stack = ORIGIN(RAM) + LENGTH(RAM);\n__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n\n\/*\n * The ELF object file format uses program headers, also knows as segments.\n * The program headers describe how the program should be loaded into memory. \n * You can print them out by using the objdump program with the \u2018-p\u2019 option.\n *\/\nPHDRS\n{\n  phdr_flash PT_LOAD;\n  phdr_ram_init PT_LOAD;\n  phdr_ram PT_NULL;\n}\n\nSECTIONS\n{\n    \/*\n     * On RISC-V devices the startup address is a regular address, so this\n     * must be the very first section.\n     * Apart from the assembly code used to initialise the stack,\n     * do not place anything else into this section.\n     *\/ \n    .reset_entry : ALIGN(4)\n    {\n        KEEP(*(SORT_NONE(.reset_entry) SORT_NONE(.reset_entry.*)))\n    } >FLASH AT>FLASH :phdr_flash\n\n    \/* \n     * Dynamic Run Time Metadata.\n     * Normally the debugger reaches this section by resolving a symbol, \n     * but in case it should scan memory for the magic, better place this\n     * section as early as possible. \n     *\/\n    .drtm : ALIGN(4)\n    {\n        KEEP(*(.drtm .drtm.*))    \n    } >FLASH AT>FLASH :phdr_flash\n\n    \/*\n     * For convenience, place the trap code early.\n     *\/\n    .trap_entry : ALIGN(4)\n    {\n        *(.exceptions_array .exceptions_array.*)\n        *(.local_interrupts_array .local_interrupts_array.*)\n        *(.device_local_interrupts_array .device_local_interrupts_array.*)\n        *(.global_interrupts_array .global_interrupts_array.*)\n        *(.trap_entry .trap_entry.*)\n        *(.traps_handlers .traps_handlers.*)\n    } >FLASH AT>FLASH :phdr_flash\n\n    \/* \n     * Memory regions initialisation arrays.\n     *\n     * There are two kinds of arrays for each RAM region, one for \n     * data and one for bss. Each is iterrated at startup and the   \n     * region initialisation is performed.\n     * \n     * The data array includes:\n     * - from (LOADADDR())\n     * - region_begin (ADDR())\n     * - region_end (ADDR()+SIZEOF())\n     *\n     * The bss array includes:\n     * - region_begin (ADDR())\n     * - region_end (ADDR()+SIZEOF())\n     *\n     * WARNING: It is mandatory that the regions are word aligned, \n     * since the initialisation code works only on words.\n     *\/\n    .mem_inits : ALIGN(4)\n    {     \n        PROVIDE_HIDDEN(__data_regions_array_begin__ = .); \/* \u00b5OS++ specific. *\/\n        \n        LONG(LOADADDR(.data));\n        LONG(ADDR(.data));\n        LONG(ADDR(.data)+SIZEOF(.data));\n        \n        \/* If more DATA regions are needed, add more such records. *\/   \n             \n        PROVIDE_HIDDEN(__data_regions_array_end__ = .); \/* \u00b5OS++ specific. *\/\n        \n        PROVIDE_HIDDEN(__bss_regions_array_begin__ = .); \/* \u00b5OS++ specific. *\/\n        \n        LONG(ADDR(.bss));\n        LONG(ADDR(.bss)+SIZEOF(.bss));\n\n        \/* If more BSS regions are needed, add more such records. *\/   \n                \n        PROVIDE_HIDDEN(__bss_regions_array_end__ = .); \/* \u00b5OS++ specific. *\/\n    } >FLASH AT>FLASH :phdr_flash\n\n    \/*\n     * The preinit code, i.e. an array of pointers to initialisation \n     * functions to be performed before constructors.\n     *\/\n    .preinit_array : ALIGN(4)\n    {\n        \/* \n         * PROVIDE not used intentionally, \n         * this symbol must not be used for other purposes. \n         *\/\n        __preinit_array_begin__ = .;    \/* \u00b5OS++ specific. *\/\n        \n        \/*\n         * Used to run the system inits before anything else.\n         *\/\n        KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))\n        \n        \/* \n         * Used for other platform inits.\n         *\/\n        KEEP(*(.preinit_array_platform .preinit_array_platform.*))\n        \n        \/*\n         * The application inits. If you need to enforce some order in \n         * execution, create new sections, as before.\n         *\/\n        KEEP(*(.preinit_array .preinit_array.*))\n\n        __preinit_array_end__ = .;     \/* \u00b5OS++ specific. *\/\n    } >FLASH AT>FLASH :phdr_flash\n\n    \/*\n     * The init code, i.e. an array of pointers to static constructors.\n     *\/\n    .init_array : ALIGN(4)\n    {\n        \/* PROVIDE not used intentionally, this symbol must not be used. *\/\n        __init_array_start = .;        \/* Standard newlib definition. *\/\n        __init_array_begin__ = .;    \/* \u00b5OS++ specific. *\/\n        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n        KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n        __init_array_end = .;        \/* Standard newlib definition. *\/\n        __init_array_end__ = .;        \/* \u00b5OS++ specific. *\/\n    } >FLASH AT>FLASH :phdr_flash\n\n    \/*\n     * The fini code, i.e. an array of pointers to static destructors.\n     *\/\n    .fini_array : ALIGN(4)\n    {\n        \/* PROVIDE not used intentionally, this symbol must not be used. *\/\n        __fini_array_start = .;        \/* Standard newlib definition. *\/\n        __fini_array_begin__ = .;    \/* \u00b5OS++ specific. *\/\n        KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n        KEEP(*(.fini_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n        __fini_array_end = .;        \/* Standard newlib definition. *\/\n        __fini_array_end__ = .;        \/* \u00b5OS++ specific. *\/\n    } >FLASH AT>FLASH :phdr_flash\n    \n    \/*\n     * The program code.\n     *\/\n    .text : ALIGN(4)\n    {\n        *(.text.unlikely .text.unlikely.*)\n        *(.text.startup .text.startup.*)\n        *(.text .text.*)            \n           *(.gnu.linkonce.t.*)\n    } >FLASH AT>FLASH :phdr_flash\n\n    . = ALIGN(4);\n      PROVIDE(__etext = .);\n      PROVIDE(_etext = .);\n      PROVIDE(etext = .);\n \n    \/*\n     * C++ virtual tables.\n     *\/\n    .vtable : ALIGN(4)\n    {\n        KEEP(*(vtable))            \n    } >FLASH AT>FLASH :phdr_flash\n \n    \/*\n     * Exception frames.\n     *\/\n    .exceptions : ALIGN(4)\n    {\n        KEEP(*(.eh_frame*))\n        *(.gcc_except_table)\n    } >FLASH AT>FLASH :phdr_flash\n \n     \/*\n      * Read-only data (constants) \n      *\/\n    .rodata : ALIGN(4)\n    {\n        *(.rodata .rodata.*)         \n        *(.constdata .constdata.*)         \n        *(.gnu.linkonce.r.*)\n    } >FLASH AT>FLASH :phdr_flash\n\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n    \n    \/*\n     * The initialised data section.\n     *\n     * The program executes knowing that the data is in RAM\n     * but the loader puts the initial values in FLASH.\n     * The startup will copy the initial values from FLASH to RAM.\n     *\/\n    .data : ALIGN(4)\n    {\n        FILL(0xFF)\n        \n        __data_start__ = . ;            \/* Standard newlib definition. *\/\n        __data_begin__ = . ;            \/* \u00b5OS++ specific *\/\n        *(.data_begin .data_begin.*)    \/* \u00b5OS++ __data_begin_guard *\/\n\n        *(.data .data.*)\n        *(.gnu.linkonce.d.*)\n        \n        . = ALIGN(8);\n        \/* \n         * RISC-V specific; the compiler optimises memory accesses\n         * in the +\/- 2K range around __global_pointer$ to GP relative.\n         * For this to work, GP must be loaded during startup with the\n         * address of __global_pointer$.\n         * This optimisation favours a 4K range. Newlib places\n         * several impure and malloc pointers in the .sdata section.\n         *\/\n        PROVIDE( __global_pointer$ = . + (4K \/ 2) );\n        \n        *(.sdata .sdata.*)\n        *(.gnu.linkonce.s.*)\n\n        \/* RISC-V specific; not sure if needed. *\/\n        . = ALIGN(8);\n        *(.srodata.cst16)\n        *(.srodata.cst8)\n        *(.srodata.cst4)\n        *(.srodata.cst2)\n        *(.srodata .srodata.*)\n        \n        *(.data_end .data_end.*)        \/* \u00b5OS++ __data_end_guard; must be last *\/        \n        . = ALIGN(4);\n        __data_end__ = . ;                \/* Standard newlib definition. *\/\n    } >RAM AT>FLASH :phdr_ram_init\n\n    \/* \n     * This address is used by the \u00b5OS++ startup code to \n     * initialise the .data section.\n     *\/\n    __data_load_addr__ = LOADADDR(.data);\n\n      . = ALIGN(4);\n      PROVIDE( __edata = . );\n      PROVIDE( _edata = . );\n      PROVIDE( edata = . );\n    \n    \/*\n     * The uninitialised data sections. NOLOAD is used to avoid\n     * the \"section `.bss' type changed to PROGBITS\" warning\n     *\/\n\n    \/* The primary uninitialised data section. *\/\n    .bss (NOLOAD) : ALIGN(4)\n    {\n        __bss_start = .;                 \/* Standard newlib definition. *\/\n        __bss_start__ = .;                 \/* Standard newlib definition. *\/\n           __bss_begin__ = .;                 \/* \u00b5OS++ specific *\/\n         *(.bss_begin .bss_begin.*)     \/* \u00b5OS++ __bss_begin_guard *\/ \n\n        *(.sbss .sbss.*)\n        *(.gnu.linkonce.sb.*)\n        \n        *(.bss .bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        \n        *(.bss_end .bss_end.*)             \/* \u00b5OS++ __bss_end_guard; must be last *\/\n        . = ALIGN(4);\n        __bss_end__ = .;                \/* Standard newlib definition. *\/\n        __bss_end = .;                    \/* Standard newlib definition. *\/\n     } >RAM AT>RAM :phdr_ram\n\n    \/* \n     * Similar to .bss, but not initialised to zero. \u00b5OS++ extension.\n     *\/\n    .noinit (NOLOAD) : ALIGN(4)\n    {\n        __noinit_begin__ = .;            \/* \u00b5OS++ extension. *\/\n        \n        *(.noinit .noinit.*) \n        \n         . = ALIGN(4) ;\n        __noinit_end__ = .;               \/* \u00b5OS++ extension. *\/\n    } >RAM AT>RAM :phdr_ram\n    \n    \/* _sbrk() expects at least word alignment. *\/\n      . = ALIGN(8);\n    PROVIDE( __end = . );\n    PROVIDE( _end = . );\n    PROVIDE( end = . ); \n    \n    PROVIDE( __heap_begin__ = . );        \/* \u00b5OS++ extension. *\/\n    \n      .stack __stack - __stack_size :\n      {\n        PROVIDE( _heap_end = . );        \/* Standard newlib definition. *\/\n        PROVIDE( __heap_end__ = . );    \/* \u00b5OS++ extension. *\/\n        . += __stack_size;\n      } >RAM AT>RAM :phdr_ram\n    \n\n    \/* \n     * Stabs debugging sections.\n     *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \n    \/*\n     * DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  \n     *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }    \n}\n","returncode":0,"stderr":"","license":"epl-1.0","lang":"Linker Script"}
{"commit":"06cf26beffc54bb43aebbefa60f84e0dffde3141","subject":"[PATCH] ppc64 boot: cleanup linker script","message":"[PATCH] ppc64 boot: cleanup linker script\n\nRemove userland related stuff from ld.script, they are not required for zImage\nuse wildcards for some sections.\n\nSigned-off-by: Olaf Hering <9d781ea8292a2154c6ca4a89a79e3c0c69f1ae9f@suse.de>\nCc: Benjamin Herrenschmidt <a7089bb6e7e92505d88aaff006cbdd60cc9120b6@kernel.crashing.org>\nCc: Anton Blanchard <14deb5e5e417133e888bf47bb6a3555c9bb7d81c@samba.org>\nSigned-off-by: Andrew Morton <5c1e68b099950c134891f0b6e179498a8ebe9cf9@osdl.org>\nSigned-off-by: Paul Mackerras <19a0ba370c443ba08d20b5061586430ab449ee8c@samba.org>\n","repos":"KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs","old_file":"arch\/ppc64\/boot\/zImage.lds","new_file":"arch\/ppc64\/boot\/zImage.lds","new_contents":"OUTPUT_ARCH(powerpc:common)\nSECTIONS\n{\n  .text      :\n  {\n    *(.text)\n    *(.fixup)\n  }\n  _etext = .;\n  . = ALIGN(4096);\n  .data    :\n  {\n    *(.rodata*)\n    *(.data*)\n    *(.sdata*)\n    *(.got*)\n  }\n\n  . = ALIGN(4096);\n  _vmlinux_start =  .;\n  .kernel:vmlinux.strip : { *(.kernel:vmlinux.strip) }\n  _vmlinux_end =  .;\n\n  . = ALIGN(4096);\n  _initrd_start =  .;\n  .kernel:initrd : { *(.kernel:initrd) }\n  _initrd_end =  .;\n\n  . = ALIGN(4096);\n  _edata  =  .;\n\n  . = ALIGN(4096);\n  __bss_start = .;\n  .bss       :\n  {\n   *(.sbss)\n   *(.bss)\n  }\n  . = ALIGN(4096);\n  _end = . ;\n}\n","old_contents":"OUTPUT_ARCH(powerpc:common)\nSEARCH_DIR(\/lib); SEARCH_DIR(\/usr\/lib); SEARCH_DIR(\/usr\/local\/lib); SEARCH_DIR(\/usr\/local\/powerpc-any-elf\/lib);\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  . = + SIZEOF_HEADERS;\n  .interp : { *(.interp) }\n  .hash          : { *(.hash)      }\n  .dynsym        : { *(.dynsym)        }\n  .dynstr        : { *(.dynstr)        }\n  .rel.text      : { *(.rel.text)      }\n  .rela.text     : { *(.rela.text)     }\n  .rel.data      : { *(.rel.data)      }\n  .rela.data     : { *(.rela.data)     }\n  .rel.rodata    : { *(.rel.rodata)    }\n  .rela.rodata   : { *(.rela.rodata)   }\n  .rel.got       : { *(.rel.got)       }\n  .rela.got      : { *(.rela.got)      }\n  .rel.ctors     : { *(.rel.ctors) }\n  .rela.ctors    : { *(.rela.ctors)    }\n  .rel.dtors     : { *(.rel.dtors) }\n  .rela.dtors    : { *(.rela.dtors)    }\n  .rel.bss       : { *(.rel.bss)       }\n  .rela.bss      : { *(.rela.bss)      }\n  .rel.plt       : { *(.rel.plt)       }\n  .rela.plt      : { *(.rela.plt)      }\n  .plt : { *(.plt) }\n  .text      :\n  {\n    *(.text)\n    *(.fixup)\n    *(.got1)\n  }\n  . = ALIGN(4096);\n  _etext = .;\n  PROVIDE (etext = .);\n  .rodata    :\n  {\n    *(.rodata)\n    *(.rodata1)\n  }\n  .kstrtab   : { *(.kstrtab) }\n  __vermagic : { *(__vermagic) }\n  .fini      : { *(.fini)    } =0\n  .ctors     : { *(.ctors)   }\n  .dtors     : { *(.dtors)   }\n  \/* Read-write section, merged into data segment: *\/\n  . = ALIGN(4096);\n  .data    :\n  {\n    *(.data)\n    *(.data1)\n    *(.sdata)\n    *(.sdata2)\n    *(.got.plt) *(.got)\n    *(.dynamic)\n    CONSTRUCTORS\n  }\n\n  . = ALIGN(4096);\n  _vmlinux_start =  .;\n  .kernel:vmlinux.strip : { *(.kernel:vmlinux.strip) }\n  _vmlinux_end =  .;\n\n  . = ALIGN(4096);\n  _initrd_start =  .;\n  .kernel:initrd : { *(.kernel:initrd) }\n  _initrd_end =  .;\n\n  . = ALIGN(4096);\n  _edata  =  .;\n  PROVIDE (edata = .);\n\n  .fixup   : { *(.fixup) }\n\n  . = ALIGN(4096);\n  __bss_start = .;\n  .bss       :\n  {\n   *(.sbss) *(.scommon)\n   *(.dynbss)\n   *(.bss)\n   *(COMMON)\n  }\n  . = ALIGN(4096);\n  _end = . ;\n  PROVIDE (end = .);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0a5473a35ba40cfc438ccfb589c13c8684f2409e","subject":"Updated LD file to add preliminary bank switch support","message":"Updated LD file to add preliminary bank switch support\n","repos":"andwn\/SGDK,Stephane-D\/SGDK,Stephane-D\/SGDK,andwn\/SGDK,andwn\/SGDK,Stephane-D\/SGDK","old_file":"md.ld","new_file":"md.ld","new_contents":"OUTPUT_ARCH(m68k)\r\nSEARCH_DIR(.)\r\n\/*GROUP(-lbcc -lc -lgcc)*\/\r\n__DYNAMIC  =  0;\r\n\r\n\/*\r\n * Setup the memory map of the SEGA Genesis.\r\n * stack grows down from high memory.\r\n *\r\n * The memory map look like this:\r\n * +--------------------+ <- low memory\r\n * | .text              |\r\n * |        _etext      |\r\n * |        ctor list   | the ctor and dtor lists are for\r\n * |        dtor list   | C++ support\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * +--------------------+ <- 0x00FF0000\r\n * | .data              | initialized data goes here\r\n * |        _data       |\r\n * |        _edata      |\r\n * +--------------------+\r\n * | .bss               |\r\n * |        _bstart     | start of bss, cleared by crt0\r\n * |        _bend       | start of heap, used by sbrk()\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * |        __stack     | top of stack\r\n * +--------------------+ <- 0x01000000\r\n *\/\r\nMEMORY\r\n{\r\n\trom : ORIGIN = 0x00000000, LENGTH = 0x00A00000\r\n\tram : ORIGIN = 0x00FF0000, LENGTH = 0x00010000\r\n}\r\n\r\n\/*\r\n * allocate the stack to be at the top of memory, since the stack\r\n * grows down\r\n *\/\r\n\r\nPROVIDE (__stack = 0x01000000);\r\n\r\n\r\nSECTIONS\r\n{\r\n  .text 0x00000000:\r\n  {\r\n    KEEP(*(.text.keepboot)) *(.text.*) *(.text)\r\n    . = ALIGN(0x4);\r\n     __CTOR_LIST__ = .;\r\n    LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\r\n    *(.ctors)\r\n    LONG(0)\r\n    __CTOR_END__ = .;\r\n    __DTOR_LIST__ = .;\r\n    LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\r\n    *(.dtors)\r\n     LONG(0)\r\n    __DTOR_END__ = .;\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n\r\n    . = ALIGN(0x4);\r\n    __INIT_SECTION__ = . ;\r\n    *(.init)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    __FINI_SECTION__ = . ;\r\n    *(.fini)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    _etext = .;\r\n    *(.lit)\r\n\r\n    *(.rodata .rodata.*)\r\n    *(.far_rodata .far_rodata.*)\r\n  } > rom\r\n  _stext = SIZEOF (.text);\r\n\r\n  .data 0xFF0000 :\r\n  AT ( ADDR (.text) + SIZEOF (.text) )\r\n  {\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.*)\r\n    _edata = .;\r\n  } > ram\r\n  _sdata = SIZEOF (.data);\r\n\r\n  .bss 0xFF0000 + SIZEOF (.data) :\r\n  {\r\n    _start = . ;\r\n    *(.shbss)\r\n    *(.bss .bss.*)\r\n    *(COMMON)\r\n    _bend = . ;\r\n  } > ram\r\n\r\n  .stab 0 (NOLOAD) :\r\n  {\r\n    *(.stab)\r\n  }\r\n\r\n  .stabstr 0 (NOLOAD) :\r\n  {\r\n    *(.stabstr)\r\n  }\r\n\r\n  .eh_frame 0 (NOLOAD) :\r\n  {\r\n    *(.eh_frame)\r\n  }\r\n}\r\n","old_contents":"OUTPUT_ARCH(m68k)\r\nSEARCH_DIR(.)\r\n\/*GROUP(-lbcc -lc -lgcc)*\/\r\n__DYNAMIC  =  0;\r\n\r\n\/*\r\n * Setup the memory map of the SEGA Genesis.\r\n * stack grows down from high memory.\r\n *\r\n * The memory map look like this:\r\n * +--------------------+ <- low memory\r\n * | .text              |\r\n * |        _etext      |\r\n * |        ctor list   | the ctor and dtor lists are for\r\n * |        dtor list   | C++ support\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * +--------------------+ <- 0x00FF0000\r\n * | .data              | initialized data goes here\r\n * |        _data       |\r\n * |        _edata      |\r\n * +--------------------+\r\n * | .bss               |\r\n * |        _bstart     | start of bss, cleared by crt0\r\n * |        _bend       | start of heap, used by sbrk()\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * |        __stack     | top of stack\r\n * +--------------------+ <- 0x01000000\r\n *\/\r\nMEMORY\r\n{\r\n\trom : ORIGIN = 0x00000000, LENGTH = 0x00A00000\r\n\tram : ORIGIN = 0x00FF0000, LENGTH = 0x00010000\r\n}\r\n\r\n\/*\r\n * allocate the stack to be at the top of memory, since the stack\r\n * grows down\r\n *\/\r\n\r\nPROVIDE (__stack = 0x01000000);\r\n\r\n\r\nSECTIONS\r\n{\r\n  .text 0x00000000:\r\n  {\r\n    KEEP(*(.text.keepboot)) *(.text.*) *(.text)\r\n    . = ALIGN(0x4);\r\n     __CTOR_LIST__ = .;\r\n    LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\r\n    *(.ctors)\r\n    LONG(0)\r\n    __CTOR_END__ = .;\r\n    __DTOR_LIST__ = .;\r\n    LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\r\n    *(.dtors)\r\n     LONG(0)\r\n    __DTOR_END__ = .;\r\n    *(.rodata .rodata.*)\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n\r\n    . = ALIGN(0x4);\r\n    __INIT_SECTION__ = . ;\r\n    *(.init)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    __FINI_SECTION__ = . ;\r\n    *(.fini)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    _etext = .;\r\n    *(.lit)\r\n  } > rom\r\n  _stext = SIZEOF (.text);\r\n\r\n  .data 0xFF0000 :\r\n  AT ( ADDR (.text) + SIZEOF (.text) )\r\n  {\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.*)\r\n    _edata = .;\r\n  } > ram\r\n  _sdata = SIZEOF (.data);\r\n\r\n  .bss 0xFF0000 + SIZEOF (.data) :\r\n  {\r\n    _start = . ;\r\n    *(.shbss)\r\n    *(.bss .bss.*)\r\n    *(COMMON)\r\n    _bend = . ;\r\n  } > ram\r\n\r\n  .stab 0 (NOLOAD) :\r\n  {\r\n    *(.stab)\r\n  }\r\n\r\n  .stabstr 0 (NOLOAD) :\r\n  {\r\n    *(.stabstr)\r\n  }\r\n\r\n  .eh_frame 0 (NOLOAD) :\r\n  {\r\n    *(.eh_frame)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ee781c95f510ee9cb76e8bdf41d8bb9b81746768","subject":"Updated stm32f373xc linker script","message":"Updated stm32f373xc linker script\n","repos":"dmitrystu\/libusb_stm32","old_file":"demo\/stm32f373xc.ld","new_file":"demo\/stm32f373xc.ld","new_contents":"ENTRY(Reset_Handler)\nMEMORY\n{\n    ROM   (rx): ORIGIN = 0x08000000, LENGTH = 256K\n    RAM  (rwx): ORIGIN = 0x20000000, LENGTH = 32K\n}\n\nINCLUDE sections.ld\n","old_contents":"ENTRY(Reset_Handler)\nMEMORY\n{\n    ROM   (rx): ORIGIN = 0x08000000, LENGTH = 256K\n    RAM  (rwx): ORIGIN = 0x20000000, LENGTH = 32K\n}\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))  KEEP(*(.fini))\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o).dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n        *(.rodata*)\n        KEEP(*(.eh_frame*))\n    } > ROM\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > ROM\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > ROM\n    __exidx_end = .;\n    __etext = .;\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n        . = ALIGN(4);\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n        . = ALIGN(4);\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n        . = ALIGN(4);\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n        . = ALIGN(4);\n        __data_end__ = .;\n    } > RAM\n    .bss (NOLOAD) :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    .heap (NOLOAD) :\n    {\n        __end__ = .;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n    .stack_dummy (NOLOAD) :\n    {\n        *(.stack)\n    } > RAM\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n    PROVIDE(_estack = __stack);\n    PROVIDE(_sidata = __etext);\n    PROVIDE(_sdata = __data_start__);\n    PROVIDE(_edata = __data_end__);\n    PROVIDE(_sbss = __bss_start__);\n    PROVIDE(_ebss = __bss_end__);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d4b3257ba0a5f39591961a1be753849330fc48a1","subject":"Linker for higher-half linking and lower setup sections","message":"Linker for higher-half linking and lower setup sections\n","repos":"akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix","old_file":"linker.ld","new_file":"linker.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\nhhalf = 0xc0000000;\npage_size = 4096;\n\nSECTIONS\n{\n    . = 0x00100000;\n    .setup :\n    {\n    __start_setup = .;\n        *(.setup)\n        *(.setup.data)\n        boot\/boot.o(.bss)\n        boot\/boot.o(COMMON)\n    __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    . += 0xc0000000;\n    .text : AT(ADDR(.text) - hhalf) \n    {\n        *(.text)\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n    }\n\n    .rodata ALIGN(page_size) : AT(ADDR(.rodata) - hhalf)\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN(page_size) : AT(ADDR(.data) - hhalf)\n    {\n        *(.data)\n    }\n\n    .bss ALIGN(page_size) : AT(ADDR(.bss) - hhalf)\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY (loader)\n\nSECTIONS\n{\n    . = 0x00100000;\n    .setup ALIGN (0x1000) :\n    {\n        __start_setup = .;\n        *(.setup)\n        *(.setup.data)\n        __end_setup = .;\n    }\n\n    \/* Higher half *\/\n    . += 0xc0000000;\n    .text ALIGN (0x1000) :\n    {\n        *(.text)\n    __start_cs_init = .;\n        *(.init.text)\n    __end_cs_init = .;\n    }\n\n    .rodata ALIGN (0x1000) :\n    {\n    __start_data_kernel = .;\n        *(.rodata*)\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        *(.data)\n    }\n\n    .bss :\n    {\n        sbss = .;\n        *(COMMON)\n        *(.bss)\n        ebss = .;\n    __end_data_kernel = .;\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"6d8da02c38178fd940e457ea78e8d844d1265969","subject":"popcorn: remove unused file","message":"popcorn: remove unused file\n","repos":"0ctobyte\/arm-kernel,0ctobyte\/arm-kernel","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"ENTRY(_start)\nSECTIONS\n{\n    __virtual_base = 0xFFFF000000000000;\n    . = __virtual_base;\n    __kernel_virtual_start = .;\n    __kernel_physical_start = . - __virtual_base;\n\n    \/* Align to page (4 kb) boundary *\/\n    .text ALIGN(0x1000) : AT(ADDR(.text) - __virtual_base) {\n        *(.text)\n    }\n    .rodata ALIGN(0x1000) : AT(ADDR(.rodata) - __virtual_base) {\n        *(.rodata)\n    }\n\n    .data ALIGN(0x1000) : AT(ADDR(.data) - __virtual_base) {\n        *(.data)\n    }\n\n    __kernel_physical_bss_start = . - __virtual_base;\n    .bss ALIGN(0x1000) : AT(ADDR(.bss) - __virtual_base) {\n        *(.bss)\n        *(.COMMON)\n    }\n    __kernel_physical_bss_end = . - __virtual_base;\n\n    __kernel_virtual_end = .;\n    __kernel_physical_end = . - __virtual_base;\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e43329cbc7c7c5cf28c9513ed9d9fbffd081b7b5","subject":"Skip calling wrappers from a number of the ROM functions.","message":"Skip calling wrappers from a number of the ROM functions.\n\nA number of the ROM functions were pointing to wrappers that saved and\nrestored the $a0 register, but the functions they called either did\nnot use $a0 or saved and restored $a0 as needed anyway.\n","repos":"UncleRus\/esp-open-rtos,urx\/esp-open-rtos,urx\/esp-open-rtos,ourairquality\/esp-open-rtos,SuperHouse\/esp-open-rtos,Zaltora\/esp-open-rtos,SuperHouse\/esp-open-rtos,SuperHouse\/esp-open-rtos,ourairquality\/esp-open-rtos,UncleRus\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,urx\/esp-open-rtos,SuperHouse\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,UncleRus\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,urx\/esp-open-rtos,Zaltora\/esp-open-rtos,ourairquality\/esp-open-rtos,Zaltora\/esp-open-rtos,UncleRus\/esp-open-rtos,Zaltora\/esp-open-rtos,SuperHouse\/esp-open-rtos,urx\/esp-open-rtos,UncleRus\/esp-open-rtos,UncleRus\/esp-open-rtos,Zaltora\/esp-open-rtos,bhuvanchandra\/esp-open-rtos,ourairquality\/esp-open-rtos,ourairquality\/esp-open-rtos,urx\/esp-open-rtos,ourairquality\/esp-open-rtos,SuperHouse\/esp-open-rtos,Zaltora\/esp-open-rtos","old_file":"ld\/rom.ld","new_file":"ld\/rom.ld","new_contents":"\/* Linker script containing Boot ROM functions for ESP8266\n\n   For more information, see:\n\n   http:\/\/esp8266-re.foogod.com\/wiki\/Boot_ROM\n   https:\/\/github.com\/jcmvbkbc\/esp-elf-rom\/\n*\/\n\nPROVIDE ( SPI_sector_erase = 0x400040c0 );\nPROVIDE ( SPI_page_program = 0x40004174 );\nPROVIDE ( SPI_read_data = 0x400042ac );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( Disable_QMode = 0x40004508 );\n\n\/* When using OTA, Cache_Read_Enable is defined in extras\/rboot-ota so\n   the ROM Cache_Read_Enable isn't picked up from here. However we\n   also provide access to the ROM function in all cases, via the name\n   rom_Cache_Read_Enable *\/\nPROVIDE ( rom_Cache_Read_Enable = 0x40004678 );\nPROVIDE ( Cache_Read_Enable = rom_Cache_Read_Enable );\n\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\n\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\n\n\/* TODO: Nearly everything below here is probably provided by the\n   libc, so never linked in, and can therefore be removed. *\/\n\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\n\nPROVIDE ( bzero = 0x4000de84 );\nPROVIDE ( memcmp = 0x4000dea8 );\nPROVIDE ( memcpy = 0x4000df48 );\nPROVIDE ( memmove = 0x4000e04c );\nPROVIDE ( memset = 0x4000e190 );\n\nPROVIDE ( strcmp = 0x4000bdc8 );\nPROVIDE ( strcpy = 0x4000bec8 );\nPROVIDE ( strlen = 0x4000bf4c );\nPROVIDE ( strncmp = 0x4000bfa8 );\nPROVIDE ( strncpy = 0x4000c0a0 );\nPROVIDE ( strstr = 0x4000e1e0 );\n\nPROVIDE ( ETS_INTR_LOCK = 0x40000f74 );\nPROVIDE ( ETS_INTR_UNLOCK = 0x40000f80 );\n","old_contents":"\/* Linker script containing Boot ROM functions for ESP8266\n\n   For more information, see:\n\n   http:\/\/esp8266-re.foogod.com\/wiki\/Boot_ROM\n   https:\/\/github.com\/jcmvbkbc\/esp-elf-rom\/\n*\/\n\nPROVIDE ( SPI_sector_erase = 0x400040c0 );\nPROVIDE ( SPI_page_program = 0x40004174 );\nPROVIDE ( SPI_read_data = 0x400042ac );\nPROVIDE ( SPI_read_status = 0x400043c8 );\nPROVIDE ( SPI_write_status = 0x40004400 );\nPROVIDE ( SPI_write_enable = 0x4000443c );\nPROVIDE ( Wait_SPI_Idle = 0x4000448c );\nPROVIDE ( Enable_QMode = 0x400044c0 );\nPROVIDE ( Disable_QMode = 0x40004508 );\n\n\/* When using OTA, Cache_Read_Enable is defined in extras\/rboot-ota so\n   the ROM Cache_Read_Enable isn't picked up from here. However we\n   also provide access to the ROM function in all cases, via the name\n   rom_Cache_Read_Enable *\/\nPROVIDE ( rom_Cache_Read_Enable = 0x40004678 );\nPROVIDE ( Cache_Read_Enable = rom_Cache_Read_Enable );\n\nPROVIDE ( Cache_Read_Disable = 0x400047f0 );\n\nPROVIDE ( lldesc_build_chain = 0x40004f40 );\nPROVIDE ( lldesc_num2link = 0x40005050 );\nPROVIDE ( lldesc_set_owner = 0x4000507c );\n\n\/* TODO: Nearly everything below here is probably provided by the\n   libc, so never linked in, and can therefore be removed. *\/\n\nPROVIDE ( __adddf3 = 0x4000c538 );\nPROVIDE ( __addsf3 = 0x4000c180 );\nPROVIDE ( __divdf3 = 0x4000cb94 );\nPROVIDE ( __divdi3 = 0x4000ce60 );\nPROVIDE ( __divsi3 = 0x4000dc88 );\nPROVIDE ( __extendsfdf2 = 0x4000cdfc );\nPROVIDE ( __fixdfsi = 0x4000ccb8 );\nPROVIDE ( __fixunsdfsi = 0x4000cd00 );\nPROVIDE ( __fixunssfsi = 0x4000c4c4 );\nPROVIDE ( __floatsidf = 0x4000e2f0 );\nPROVIDE ( __floatsisf = 0x4000e2ac );\nPROVIDE ( __floatunsidf = 0x4000e2e8 );\nPROVIDE ( __floatunsisf = 0x4000e2a4 );\nPROVIDE ( __muldf3 = 0x4000c8f0 );\nPROVIDE ( __muldi3 = 0x40000650 );\nPROVIDE ( __mulsf3 = 0x4000c3dc );\nPROVIDE ( __subdf3 = 0x4000c688 );\nPROVIDE ( __subsf3 = 0x4000c268 );\nPROVIDE ( __truncdfsf2 = 0x4000cd5c );\nPROVIDE ( __udivdi3 = 0x4000d310 );\nPROVIDE ( __udivsi3 = 0x4000e21c );\nPROVIDE ( __umoddi3 = 0x4000d770 );\nPROVIDE ( __umodsi3 = 0x4000e268 );\nPROVIDE ( __umulsidi3 = 0x4000dcf0 );\n\nPROVIDE ( bzero = 0x40002ae8 );\nPROVIDE ( memcmp = 0x400018d4 );\nPROVIDE ( memcpy = 0x400018b4 );\nPROVIDE ( memmove = 0x400018c4 );\nPROVIDE ( memset = 0x400018a4 );\n\nPROVIDE ( strcmp = 0x40002aa8 );\nPROVIDE ( strcpy = 0x40002a88 );\nPROVIDE ( strlen = 0x40002ac8 );\nPROVIDE ( strncmp = 0x40002ab8 );\nPROVIDE ( strncpy = 0x40002a98 );\nPROVIDE ( strstr = 0x40002ad8 );\n\nPROVIDE ( ETS_INTR_LOCK = 0x40000f74 );\nPROVIDE ( ETS_INTR_UNLOCK = 0x40000f80 );\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"2d8b22f01e479b0adb31ddf18c1878da00325ba9","subject":"Adapt flash location for NRF52","message":"Adapt flash location for NRF52\n\nThis reverts commit 112544055854f5c3763de2e8613b840e2db8fdaa.\n","repos":"tock\/libtock-rs","old_file":"layout.ld","new_file":"layout.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x00020038, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        KEEP (*(.text._start))\n        *(.text*)\n        *(.rodata*)\n\n        \/* C++ exception unwinding information *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH =0xFF\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += 1024;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += 1024;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += 1024;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x00040030, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        KEEP (*(.text._start))\n        *(.text*)\n        *(.rodata*)\n\n        \/* C++ exception unwinding information *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH =0xFF\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += 1024;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += 1024;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += 1024;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"73036daffab2afa07b00aa49d982ca21f82a82ff","subject":"[os.ld] Removed unneeded padding","message":"[os.ld] Removed unneeded padding\n\nSigned-off-by: Dan Printzell <69f25cbe4b2608181d39803083cb5ee0c30f2794@gmail.com>\n","repos":"Vild\/PowerNex","old_file":"kernel\/src\/os.ld","new_file":"kernel\/src\/os.ld","new_contents":"OUTPUT_FORMAT(elf64-x86-64)\nENTRY(lstart)\nKERNEL_LMA = 1M;\nKERNEL_VMA = 0xFFFFFFFF80000000;\nlstart = start - KERNEL_VMA;\nSECTIONS {\n\t. = KERNEL_LMA;\n\n\t.multiboot : AT(ADDR(.multiboot)) {\n\t\tLONG(0x0)\n\t\t*(.multiboot)\n\t}\n\n\t\/*. += 0x100000;*\/\n\t. += KERNEL_VMA;\n\n\t.text ALIGN(0x1000) : AT(ADDR(.text) - KERNEL_VMA) {\n\t\t*(.text .text.*)\n\t}\n\n\t.rodata ALIGN(0x1000) : AT(ADDR(.rodata) - KERNEL_VMA) {\n\t\t*(.initpd)\n\t\t*(.rodata .rodata.*)\n\t\t*(.rdata)\n\t}\n\n\t.minfo ALIGN(0x1000) : AT(ADDR(.minfo) - KERNEL_VMA) {\n\t\t*(.minfo)\n\t}\n\n\t.deh_eh ALIGN(0x1000) : AT(ADDR(.deh_eh) - KERNEL_VMA) {\n\t\t*(.deh_eh)\n\t}\n\n\t.dtors.d_dso_dtor ALIGN(0x1000) : AT(ADDR(.dtors.d_dso_dtor) - KERNEL_VMA) {\n\t\t*(.dtors .dtors.*)\n\t\t *(.dtors.d_dso_dtor)\n\t}\n\n\t.ctors.d_dso_ctor ALIGN(0x1000) : AT(ADDR(.ctors.d_dso_ctor) - KERNEL_VMA) {\n\t\t*(.ctors .ctors.*)\n\t\t*(.ctors.d_dso_ctor)\n\t}\n\n\t.eh_frame ALIGN(0x1000) : AT(ADDR(.eh_frame) - KERNEL_VMA) {\n\t\t*(.eh_frame)\n\t}\n\n\t.data ALIGN(0x1000) : AT(ADDR(.data) - KERNEL_VMA) {\n\t\t*(.padata)\n\t\t*(.data .data.*)\n\n\t\tKERNEL_MODULES_START = .;\n\t\t*(.KMODULES)\n\t\tKERNEL_MODULES_END = .;\n\t}\n\n\t.symbols ALIGN(0x1000) : AT(ADDR(.symbols) - KERNEL_VMA) {\n\t\tKERNEL_SYMBOLS_START = .;\n\t\t*(.symbols .symbols.*)\n\t\tKERNEL_SYMBOLS_END = .;\n\t}\n\n\t.tdata ALIGN(0x1000) : AT(ADDR(.tdata) - KERNEL_VMA) {\n\t\t*(.tdata .tdata.*)\n\t}\n\n\t.got ALIGN(0x1000) : AT(ADDR(.got) - KERNEL_VMA) {\n\t\t*(.got)\n\t\t*(.got.plt)\n\t}\n\n\t.bss ALIGN(0x1000) : AT(ADDR(.bss) - KERNEL_VMA) {\n\t\tKERNEL_BSS_START = .;\n\t\t*(.COMMON)\n\t\t*(.bss)\n\t}\n\n\t.tbss : AT(ADDR(.tbss) - KERNEL_VMA) {\n\t\t*(.tbss .tbss.*)\n\t}\n\n\tKERNEL_END = (. + 0xFFF) & 0xFFFFFFFFFFFFF000;\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t\t*(.note .note.*)\n\t\t*(.rela.*)\n\t}\n}\n","old_contents":"OUTPUT_FORMAT(elf64-x86-64)\nENTRY(lstart)\nKERNEL_LMA = 1M;\nKERNEL_VMA = 0xFFFFFFFF80000000;\nlstart = start - KERNEL_VMA;\nSECTIONS {\n\t. = KERNEL_LMA;\n\n\t.multiboot : AT(ADDR(.multiboot)) {\n\t\tLONG(0x0)\n\t\t*(.multiboot)\n\t}\n\n\t. += KERNEL_VMA;\n\n\t.text ALIGN(0x1000) : AT(ADDR(.text) - KERNEL_VMA) {\n\t\t*(.text .text.*)\n\t}\n\n\t.rodata ALIGN(0x1000) : AT(ADDR(.rodata) - KERNEL_VMA) {\n\t\t*(.initpd)\n\t\t*(.rodata .rodata.*)\n\t\t*(.rdata)\n\t}\n\n\t.minfo ALIGN(0x1000) : AT(ADDR(.minfo) - KERNEL_VMA) {\n\t\t*(.minfo)\n\t}\n\n\t.deh_eh ALIGN(0x1000) : AT(ADDR(.deh_eh) - KERNEL_VMA) {\n\t\t*(.deh_eh)\n\t}\n\n\t.dtors.d_dso_dtor ALIGN(0x1000) : AT(ADDR(.dtors.d_dso_dtor) - KERNEL_VMA) {\n\t\t*(.dtors .dtors.*)\n\t\t *(.dtors.d_dso_dtor)\n\t}\n\n\t.ctors.d_dso_ctor ALIGN(0x1000) : AT(ADDR(.ctors.d_dso_ctor) - KERNEL_VMA) {\n\t\t*(.ctors .ctors.*)\n\t\t*(.ctors.d_dso_ctor)\n\t}\n\n\t.eh_frame ALIGN(0x1000) : AT(ADDR(.eh_frame) - KERNEL_VMA) {\n\t\t*(.eh_frame)\n\t}\n\n\t.data ALIGN(0x1000) : AT(ADDR(.data) - KERNEL_VMA) {\n\t\t*(.padata)\n\t\t*(.data .data.*)\n\n\t\tKERNEL_MODULES_START = .;\n\t\t*(.KMODULES)\n\t\tKERNEL_MODULES_END = .;\n\t}\n\n\t.symbols ALIGN(0x1000) : AT(ADDR(.symbols) - KERNEL_VMA) {\n\t\tKERNEL_SYMBOLS_START = .;\n\t\t*(.symbols .symbols.*)\n\t\tKERNEL_SYMBOLS_END = .;\n\t}\n\n\t.tdata ALIGN(0x1000) : AT(ADDR(.tdata) - KERNEL_VMA) {\n\t\t*(.tdata .tdata.*)\n\t}\n\n\t.got ALIGN(0x1000) : AT(ADDR(.got) - KERNEL_VMA) {\n\t\t*(.got)\n\t\t*(.got.plt)\n\t}\n\n\t.bss ALIGN(0x1000) : AT(ADDR(.bss) - KERNEL_VMA) {\n\t\tKERNEL_BSS_START = .;\n\t\t*(.COMMON)\n\t\t*(.bss)\n\t}\n\n\t.tbss : AT(ADDR(.tbss) - KERNEL_VMA) {\n\t\t*(.tbss .tbss.*)\n\t}\n\n\tKERNEL_END = (. + 0xFFF) & 0xFFFFFFFFFFFFF000;\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t\t*(.note .note.*)\n\t\t*(.rela.*)\n\t}\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"aed251280ae453ba6072edd1b7f28f82c81bf2dd","subject":"Update stm32_rom.ld","message":"Update stm32_rom.ld","repos":"zhaojuntao\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,igou\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,FlyLu\/rt-thread,yongli3\/rt-thread,AubrCool\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,wolfgangz2013\/rt-thread,yongli3\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,igou\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,AubrCool\/rt-thread,yongli3\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,yongli3\/rt-thread,wolfgangz2013\/rt-thread,ArdaFu\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,geniusgogo\/rt-thread,igou\/rt-thread,yongli3\/rt-thread","old_file":"bsp\/stm32f40x\/stm32_rom.ld","new_file":"bsp\/stm32f40x\/stm32_rom.ld","new_contents":"\/*\n * linker script for STM32F10x with GNU ld\n * bernard.xiong 2009-10-14\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k \/* 1024KB flash *\/\n    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  128k \/* 128K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x100;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        _etext = .;\n    } > CODE = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > CODE\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >DATA\n\n    .stack : \n    {\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >DATA\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > DATA\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * linker script for STM32F10x with GNU ld\n * bernard.xiong 2009-10-14\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k \/* 512KB flash *\/\n    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  64k \/* 64K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x100;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        _etext = .;\n    } > CODE = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > CODE\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >DATA\n\n    .stack : \n    {\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >DATA\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > DATA\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"95c920505356d1444237565f38e1340221f9e258","subject":"fix bss start address in ld file","message":"fix bss start address in ld file\n","repos":"zhaojuntao\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,FlyLu\/rt-thread,wolfgangz2013\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,zhaojuntao\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,zhaojuntao\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread","old_file":"bsp\/zynq7000\/zynq7000.ld","new_file":"bsp\/zynq7000\/zynq7000.ld","new_contents":"\/*\n * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd\n *\n *  This file is part of RT-Thread (http:\/\/www.rt-thread.org)\n *\n *  All rights reserved.\n *\n *  This program is free software; you can redistribute it and\/or modify\n *  it under the terms of the GNU General Public License as published by\n *  the Free Software Foundation; either version 2 of the License, or\n *  (at your option) any later version.\n *\n *  This program is distributed in the hope that it will be useful,\n *  but WITHOUT ANY WARRANTY; without even the implied warranty of\n *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *  GNU General Public License for more details.\n *\n *  You should have received a copy of the GNU General Public License along\n *  with this program; if not, write to the Free Software Foundation, Inc.,\n *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSECTIONS\n{\n    . = 0x1ff00000;\n    __text_start = .;\n    .text :\n    {\n        *(.vectors)\n        \/* make the ISRs close to vectors may be more cache-friendly *\/\n        *(.text.isr)\n\n        *(.text)\n        *(.text.*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n\n        \/* section information for initialization *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n    } =0\n    __text_end = .;\n\n    __rodata_start = .;\n    .rodata   : { *(.rodata) *(.rodata.*) }\n    __rodata_end = .;\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    }\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    }\n\n    __data_start = .;\n    . = ALIGN(4);\n    .data :\n    {\n        KEEP(*(.resource_table))\n        *(.data)\n        *(.data.*)\n    }\n    __data_end = .;\n\n    . = ALIGN(4);\n    __bss_start = __data_end;\n    .bss       :\n    {\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    }\n    . = ALIGN(4);\n    __bss_end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab 0 : { *(.stab) }\n    .stabstr 0 : { *(.stabstr) }\n    .stab.excl 0 : { *(.stab.excl) }\n    .stab.exclstr 0 : { *(.stab.exclstr) }\n    .stab.index 0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment 0 : { *(.comment) }\n\n    _end = .;\n}\n","old_contents":"\/*\n * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd\n *\n *  This file is part of RT-Thread (http:\/\/www.rt-thread.org)\n *\n *  All rights reserved.\n *\n *  This program is free software; you can redistribute it and\/or modify\n *  it under the terms of the GNU General Public License as published by\n *  the Free Software Foundation; either version 2 of the License, or\n *  (at your option) any later version.\n *\n *  This program is distributed in the hope that it will be useful,\n *  but WITHOUT ANY WARRANTY; without even the implied warranty of\n *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *  GNU General Public License for more details.\n *\n *  You should have received a copy of the GNU General Public License along\n *  with this program; if not, write to the Free Software Foundation, Inc.,\n *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSECTIONS\n{\n    . = 0x1ff00000;\n    __text_start = .;\n    .text :\n    {\n        *(.vectors)\n        \/* make the ISRs close to vectors may be more cache-friendly *\/\n        *(.text.isr)\n\n        *(.text)\n        *(.text.*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n\n        \/* section information for initialization *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n    } =0\n    __text_end = .;\n\n    __rodata_start = .;\n    .rodata   : { *(.rodata) *(.rodata.*) }\n    __rodata_end = .;\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    }\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    }\n\n    __data_start = .;\n    . = ALIGN(4);\n    .data :\n    {\n        KEEP(*(.resource_table))\n        *(.data)\n        *(.data.*)\n    }\n    __data_end = .;\n\n    . = ALIGN(4);\n    __bss_start = 0;\n    .bss       :\n    {\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    }\n    . = ALIGN(4);\n    __bss_end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab 0 : { *(.stab) }\n    .stabstr 0 : { *(.stabstr) }\n    .stab.excl 0 : { *(.stab.excl) }\n    .stab.exclstr 0 : { *(.stab.exclstr) }\n    .stab.index 0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment 0 : { *(.comment) }\n\n    _end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bd00fa9f7d49900a85c1672f028e1db21648bbc2","subject":"userland: add comment to linker file","message":"userland: add comment to linker file\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beg = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beg);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beg);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beg);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        _beg = .; \/* Start of the app in flash. *\/\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash *\/\n        LONG(LOADADDR(.got) - _beg);\n        \/* Offset of GOT section in memory *\/\n        LONG(_got);\n        \/* Size of GOT section *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash *\/\n        LONG(LOADADDR(.data) - _beg);\n        \/* Offset of data section in memory *\/\n        LONG(_data);\n        \/* Size of data section *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of BSS section in memory *\/\n        LONG(_bss);\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - _beg);\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tbf. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2d5c724ed84729107812f1fa6961080c4ba2243d","subject":"Revert \"soc: intel_adsp: fix linker script for cavs_v20\"","message":"Revert \"soc: intel_adsp: fix linker script for cavs_v20\"\n\nThis reverts commit 3cc14b2c2b12abfd3c18c5245eaca0fbd5b21b49.\n\nRevert this due to the same reason as commit\na29b66bbf5fbe6a77b9055ce6a7cf260e2d0dd0a:\n\n  Unfortunately this mechanism doesn't seem to actually work on the SDK\n  linker.  The emitted sections, when passed a symbol name as the \"start\n  address\" just appear wherever the \".\" variable was pointing (in this\n  case, into the cached region).  That breaks the kernel coherence\n  layer, obviously.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v20\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v20\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs20_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs20_adsp);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .cached :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n\n  . = SEGSTART_UNCACHED;\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  .bss (NOLOAD) : ALIGN(4096)\n  {\n    . = ALIGN(4096);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n  . = SEGSTART_UNCACHED;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * The UNCACHED_RAM_OFFSET will be used before to move the address\n * pointer forward or backward so code and data land in correct\n * region. Remember to align the memory, and be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define UNCACHED_RAM_OFFSET\t0x20000000\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - UNCACHED_RAM_OFFSET,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs20_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs20_adsp);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  \/*\n   * Address pointer here is at cached ram.\n   * So need to go into uncached memory region, hence\n   * the subtraction.\n   *\/\n  segstart_uncached_noinit = ALIGN(64) - UNCACHED_RAM_OFFSET;\n\n  .noinit segstart_uncached_noinit : ALIGN(64)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  \/* Going back into cached memory region. *\/\n  segstart_cached_lit4 = ALIGN(64) + UNCACHED_RAM_OFFSET;\n\n  .lit4 segstart_cached_lit4 : ALIGN(64)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n#include <linker\/common-ram.ld>\n\n  \/* Going back into cached memory region. *\/\n  segstart_cached_cached = ALIGN(64) + UNCACHED_RAM_OFFSET;\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached segstart_cached_cached :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  \/* Going back into un-cached memory region. *\/\n  segstart_uncached_tm_clone_table = ALIGN(64) - UNCACHED_RAM_OFFSET;\n\n  .tm_clone_table segstart_uncached_tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss ALIGN(64) (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  _end = ALIGN(64);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  segstart_cached_stack = _end + UNCACHED_RAM_OFFSET;\n  . = segstart_cached_stack;\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n  segstart_uncached_lpbuf = ALIGN(4) - UNCACHED_RAM_OFFSET;\n  . = segstart_uncached_lpbuf;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  _heap_sentry = . - UNCACHED_RAM_OFFSET;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"23821d5b2b59a27deda637f9414dd4e619db181b","subject":"Fix WD in .bin opens","message":"Fix WD in .bin opens\n","repos":"redox-os\/libc,redox-os\/libc,redox-os\/libc","old_file":"program.ld","new_file":"program.ld","new_contents":"ENTRY(_start)\n\nMEMORY {\n\thighmem : org = 0x80000000, l = 4096K\n}\n\nSECTIONS {\n\t.text : {\n\t\t*(.text*)\n\t} >highmem\n\n\t.rodata : {\n\t\t*(.rodata*)\n\t} >highmem\n\n\t.data : {\n\t\t*(.data*)\n\t} >highmem\n\n        .eh_frame : {\n\t\t*(.eh_frame*)\n        } >highmem\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t\t*(.rel.eh_frame)\n\t}\n}\n","old_contents":"ENTRY(_start)\nOUTPUT_FORMAT(elf32-i386)\n\nMEMORY {\n\thighmem : org = 0x80000000, l = 4096K\n}\n\nSECTIONS {\n\t.text : {\n\t\t*(.text*)\n\t} >highmem\n\n\t.rodata : {\n\t\t*(.rodata*)\n\t} >highmem\n\n\t.data : {\n\t\t*(.data*)\n\t} >highmem\n\n\t.eh_frame : {\n\t\t*(.eh_frame)\n\t} >highmem\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t\t*(.rel.eh_frame)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"fcd6862597a769149e839b6aebf9f4b166a5dffb","subject":"esp8266: Bump iROM size to 512k.","message":"esp8266: Bump iROM size to 512k.\n\nNeeded for frozen scripts, and for future growth of binary.\n","repos":"pramasoul\/micropython,ganshun666\/micropython,toolmacher\/micropython,bvernoux\/micropython,PappaPeppar\/micropython,selste\/micropython,turbinenreiter\/micropython,PappaPeppar\/micropython,mpalomer\/micropython,TDAbboud\/micropython,adafruit\/circuitpython,bvernoux\/micropython,micropython\/micropython-esp32,ganshun666\/micropython,hosaka\/micropython,redbear\/micropython,tuc-osg\/micropython,emfcamp\/micropython,matthewelse\/micropython,henriknelson\/micropython,PappaPeppar\/micropython,cwyark\/micropython,alex-robbins\/micropython,tobbad\/micropython,tobbad\/micropython,dinau\/micropython,bvernoux\/micropython,chrisdearman\/micropython,puuu\/micropython,adafruit\/micropython,swegener\/micropython,turbinenreiter\/micropython,dinau\/micropython,adafruit\/micropython,mhoffma\/micropython,jmarcelino\/pycom-micropython,micropython\/micropython-esp32,drrk\/micropython,turbinenreiter\/micropython,oopy\/micropython,blazewicz\/micropython,emfcamp\/micropython,redbear\/micropython,selste\/micropython,pramasoul\/micropython,pramasoul\/micropython,deshipu\/micropython,mhoffma\/micropython,Timmenem\/micropython,matthewelse\/micropython,torwag\/micropython,hosaka\/micropython,kerneltask\/micropython,tuc-osg\/micropython,alex-robbins\/micropython,adafruit\/micropython,kerneltask\/micropython,pfalcon\/micropython,MrSurly\/micropython,mpalomer\/micropython,HenrikSolver\/micropython,selste\/micropython,oopy\/micropython,infinnovation\/micropython,HenrikSolver\/micropython,misterdanb\/micropython,tuc-osg\/micropython,pozetroninc\/micropython,henriknelson\/micropython,micropython\/micropython-esp32,micropython\/micropython-esp32,mpalomer\/micropython,TDAbboud\/micropython,praemdonck\/micropython,chrisdearman\/micropython,chrisdearman\/micropython,HenrikSolver\/micropython,mpalomer\/micropython,ryannathans\/micropython,lowRISC\/micropython,alex-march\/micropython,Peetz0r\/micropython-esp32,lowRISC\/micropython,pramasoul\/micropython,AriZuu\/micropython,adafruit\/micropython,MrSurly\/micropython-esp32,deshipu\/micropython,chrisdearman\/micropython,MrSurly\/micropython,MrSurly\/micropython-esp32,alex-march\/micropython,misterdanb\/micropython,pozetroninc\/micropython,pfalcon\/micropython,misterdanb\/micropython,micropython\/micropython-esp32,Timmenem\/micropython,Timmenem\/micropython,infinnovation\/micropython,pozetroninc\/micropython,tuc-osg\/micropython,pozetroninc\/micropython,hiway\/micropython,bvernoux\/micropython,adafruit\/micropython,hiway\/micropython,henriknelson\/micropython,kerneltask\/micropython,hiway\/micropython,chrisdearman\/micropython,hiway\/micropython,cwyark\/micropython,drrk\/micropython,emfcamp\/micropython,ganshun666\/micropython,emfcamp\/micropython,Peetz0r\/micropython-esp32,infinnovation\/micropython,PappaPeppar\/micropython,puuu\/micropython,tuc-osg\/micropython,torwag\/micropython,henriknelson\/micropython,adafruit\/circuitpython,ryannathans\/micropython,trezor\/micropython,TDAbboud\/micropython,tralamazza\/micropython,dmazzella\/micropython,trezor\/micropython,infinnovation\/micropython,alex-march\/micropython,dxxb\/micropython,MrSurly\/micropython-esp32,torwag\/micropython,mpalomer\/micropython,alex-robbins\/micropython,SHA2017-badge\/micropython-esp32,Peetz0r\/micropython-esp32,oopy\/micropython,torwag\/micropython,dmazzella\/micropython,henriknelson\/micropython,trezor\/micropython,AriZuu\/micropython,dmazzella\/micropython,swegener\/micropython,kerneltask\/micropython,praemdonck\/micropython,tobbad\/micropython,turbinenreiter\/micropython,hiway\/micropython,matthewelse\/micropython,matthewelse\/micropython,blazewicz\/micropython,tobbad\/micropython,emfcamp\/micropython,dinau\/micropython,dxxb\/micropython,HenrikSolver\/micropython,selste\/micropython,hosaka\/micropython,mhoffma\/micropython,redbear\/micropython,puuu\/micropython,dxxb\/micropython,pfalcon\/micropython,jmarcelino\/pycom-micropython,ryannathans\/micropython,TDAbboud\/micropython,oopy\/micropython,bvernoux\/micropython,blazewicz\/micropython,hosaka\/micropython,Timmenem\/micropython,puuu\/micropython,misterdanb\/micropython,redbear\/micropython,misterdanb\/micropython,dinau\/micropython,toolmacher\/micropython,adafruit\/circuitpython,SHA2017-badge\/micropython-esp32,tralamazza\/micropython,ganshun666\/micropython,swegener\/micropython,matthewelse\/micropython,TDAbboud\/micropython,redbear\/micropython,SHA2017-badge\/micropython-esp32,pozetroninc\/micropython,mhoffma\/micropython,dxxb\/micropython,cwyark\/micropython,swegener\/micropython,dinau\/micropython,PappaPeppar\/micropython,torwag\/micropython,deshipu\/micropython,dxxb\/micropython,dmazzella\/micropython,MrSurly\/micropython,ryannathans\/micropython,drrk\/micropython,pfalcon\/micropython,infinnovation\/micropython,jmarcelino\/pycom-micropython,adafruit\/circuitpython,blazewicz\/micropython,selste\/micropython,lowRISC\/micropython,deshipu\/micropython,SHA2017-badge\/micropython-esp32,blazewicz\/micropython,turbinenreiter\/micropython,alex-robbins\/micropython,praemdonck\/micropython,lowRISC\/micropython,deshipu\/micropython,tobbad\/micropython,tralamazza\/micropython,hosaka\/micropython,kerneltask\/micropython,oopy\/micropython,pramasoul\/micropython,praemdonck\/micropython,MrSurly\/micropython,matthewelse\/micropython,toolmacher\/micropython,toolmacher\/micropython,mhoffma\/micropython,MrSurly\/micropython-esp32,alex-march\/micropython,AriZuu\/micropython,alex-robbins\/micropython,swegener\/micropython,MrSurly\/micropython-esp32,drrk\/micropython,Peetz0r\/micropython-esp32,pfalcon\/micropython,praemdonck\/micropython,MrSurly\/micropython,tralamazza\/micropython,adafruit\/circuitpython,jmarcelino\/pycom-micropython,toolmacher\/micropython,cwyark\/micropython,ryannathans\/micropython,drrk\/micropython,adafruit\/circuitpython,AriZuu\/micropython,alex-march\/micropython,cwyark\/micropython,SHA2017-badge\/micropython-esp32,trezor\/micropython,ganshun666\/micropython,AriZuu\/micropython,lowRISC\/micropython,jmarcelino\/pycom-micropython,trezor\/micropython,HenrikSolver\/micropython,Peetz0r\/micropython-esp32,puuu\/micropython,Timmenem\/micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x80000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n  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*(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4eb5ce4c9b39ab131c0ead4f5147e07fec71e394","subject":"add a memory section for RAM so that the linker will warn when you've made your program too big.","message":"add a memory section for RAM so that the linker will warn when you've\nmade your program too big.\n","repos":"arurke\/contiki,malvira\/libmc1322x,bluerover\/6lbr,MohamedSeliem\/contiki,arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,bluerover\/6lbr,bluerover\/6lbr,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki,muffinator\/libmc1322x,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,malvira\/libmc1322x,MohamedSeliem\/contiki,muffinator\/libmc1322x,bluerover\/6lbr","old_file":"mc1322x.lds","new_file":"mc1322x.lds","new_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\n\nMEMORY\n  {\n    ram (rwx) : org = 0x00400000, l = 96K\n  }\n\nSECTIONS\n{\n\nSYS_STACK_SIZE = 1024;\nIRQ_STACK_SIZE = 256;\nFIQ_STACK_SIZE = 256;\nSVC_STACK_SIZE = 256;\nABT_STACK_SIZE = 16;\nUND_STACK_SIZE = 16;\nHEAP_SIZE = 1024;\n\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x00400000); . = 0x00400000;\n  .text           :\n  {\n    *(.start)\n    *(.irq)\t\t\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  } =0\n\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n      *(.rela.ctors)\n      *(.rela.dtors)\n      *(.rela.got)\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n    }\n  .rel.plt        : { *(.rel.plt) }\n  .rela.plt       : { *(.rela.plt) }\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0\n  .plt            : { *(.plt) }\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Adjust the address for the data segment.  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When there is no .bss section, we don't\n      pad the .data section.  *\/\n   . = ALIGN(. != 0 ? 32 \/ 8 : 1);\n  }\n  _bss_end__ = . ; __bss_end__ = . ;\n  . = ALIGN(32 \/ 8);\n\n   .heap : {\n                __heap_start__ = . ;\n                *(.heap);\n                . += HEAP_SIZE;\n                . = ALIGN (4);\n                __heap_end__ = . ;\n   }\n\n\n  . = ALIGN(32 \/ 8);\n  __end__ = . ;\n  _end = .; PROVIDE (end = .);\n  . = DATA_SEGMENT_END (.);\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"6b03f8e29d4e99bbc7a382b5561939184a7fdd70","subject":"Add nzbss memory section for nrf52.","message":"Add nzbss memory section for nrf52.\n","repos":"wes3\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,wes3\/incubator-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,wes3\/incubator-mynewt-core,mlaz\/mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core","old_file":"hw\/bsp\/nrf52pdk\/nrf52pdk.ld","new_file":"hw\/bsp\/nrf52pdk\/nrf52pdk.ld","new_contents":"\/**\n * Copyright (c) 2015 Runtime Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n *   http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script for Nordic Semiconductor nRF5 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000\n  CODE_RAM (rwx) : ORIGIN = 0x8000000, LENGTH = 0x8000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __nzbss_start__\n *   __nzbss_end__\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        __isr_vector_start = .;\n        KEEP(*(.isr_vector))\n        __isr_vector_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .vector_relocation :\n    {\n        . = ALIGN(4);\n        __vector_tbl_reloc__ = .;\n        . = . + (__isr_vector_end - __isr_vector_start);\n        . = ALIGN(4);\n    } > RAM\n            \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        *(.preinit_array)\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        *(SORT(.init_array.*))\n        *(.init_array)\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    \/* Heap starts after BSS *\/\n    __HeapBase = .;\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Top of head is the bottom of the stack *\/\n    __HeapLimit = __StackLimit;\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\n\n    \/* Non-zeroed BSS.  This section is similar to BSS, with the following two\n     * caveats:\n     *    1. It does not get zeroed at init-time.\n     *    2. You cannot use it as source memory for EasyDMA.\n     *\/\n    .nzbss :\n    {\n        . = ALIGN(4);\n        __nzbss_start__ = .;\n        *(.nzbss*)\n        . = ALIGN(4);\n        __nzbss_end__ = .;\n    } > CODE_RAM\n}\n\n","old_contents":"\/**\n * Copyright (c) 2015 Runtime Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n * \n *   http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/* Linker script for Nordic Semiconductor nRF5 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* \n * NOTE: This linker script is for version 1.0 of the nrf52. See\n * errata #33 and #34 on nordic infocenter website for details. This errata\n * causes us to allocate a memory regision we call \"CODE_RAM\" so that we can\n * access the full 64K RAM provided by the chip.\n *\/ \nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000\n  CODE_RAM (rwx) : ORIGIN = 0x8000000, LENGTH = 0x8000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapBase\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        __isr_vector_start = .;\n        KEEP(*(.isr_vector))\n        __isr_vector_end = .;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        *(.eh_frame*)\n        . = ALIGN(4);\n    } > FLASH\n\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        . = ALIGN(4);\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        . = ALIGN(4);\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .vector_relocation :\n    {\n        . = ALIGN(4);\n        __vector_tbl_reloc__ = .;\n        . = . + (__isr_vector_end - __isr_vector_start);\n        . = ALIGN(4);\n    } > RAM\n            \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        *(.preinit_array)\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        *(SORT(.init_array.*))\n        *(.init_array)\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        *(.jcr)\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > CODE_RAM\n\n    \/* \n     * Place heap and stack in CODE_RAM. Heap is at start, stack is at the\n     * top and stack limit is the bottom of the stack.\n     *\/\n    __HeapBase = ORIGIN(CODE_RAM);\n    __StackTop = ORIGIN(CODE_RAM) + LENGTH(CODE_RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Top of head is the bottom of the stack *\/\n    __HeapLimit = __StackLimit;\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"12e2656472bf53e467c066eda6f3e177a97210ca","subject":"stm: allow more flash for the binary.","message":"stm: allow more flash for the binary.\n","repos":"tdautc19841202\/micropython,aethaniel\/micropython,Peetz0r\/micropython-esp32,torwag\/micropython,xuxiaoxin\/micropython,orionrobots\/micropython,hosaka\/micropython,Timmenem\/micropython,utopiaprince\/micropython,adafruit\/circuitpython,stonegithubs\/micropython,adamkh\/micropython,SHA2017-badge\/micropython-esp32,suda\/micropython,Peetz0r\/micropython-esp32,stonegithubs\/micropython,dxxb\/micropython,trezor\/micropython,torwag\/micropython,noahchense\/micropython,AriZuu\/micropython,skybird6672\/micropython,dmazzella\/micropython,dmazzella\/micropython,MrSurly\/micropython,cwyark\/micropython,martinribelotta\/micropython,danicampora\/micropython,adamkh\/micropython,pfalcon\/micropython,cwyark\/micropython,oopy\/micropython,toolmacher\/micropython,ryannathans\/micropython,omtinez\/micropython,ericsnowcurrently\/micropython,mianos\/micropython,utopiaprince\/micropython,HenrikSolver\/micropython,ceramos\/micropython,KISSMonX\/micropython,xuxiaoxin\/micropython,selste\/micropython,deshipu\/micropython,aitjcize\/micropython,micropython\/micropython-esp32,deshipu\/micropython,aitjcize\/micropython,pramasoul\/micropython,tuc-osg\/micropython,tuc-osg\/micropython,trezor\/micropython,emfcamp\/micropython,neilh10\/micropython,drrk\/micropython,praemdonck\/micropython,toolmacher\/micropython,paul-xxx\/micropython,heisewangluo\/micropython,henriknelson\/micropython,redbear\/micropython,stonegithubs\/micropython,xuxiaoxin\/micropython,dhylands\/micropython,turbinenreiter\/micropython,galenhz\/micropython,utopiaprince\/micropython,jmarcelino\/pycom-micropython,danicampora\/micropython,vitiral\/micropython,adamkh\/micropython,supergis\/micropython,xuxiaoxin\/micropython,kostyll\/micropython,aethaniel\/micropython,slzatz\/micropython,feilongfl\/micropython,mhoffma\/micropython,drrk\/micropython,Peetz0r\/micropython-esp32,chrisdearman\/micropython,mpalomer\/micropython,SungEun-Steve-Kim\/test-mp,omtinez\/micropython,tralamazza\/micropython,xyb\/micropython,SungEun-Steve-Kim\/test-mp,mpalomer\/micropython,tuc-osg\/micropython,matthewelse\/micropython,hiway\/micropython,dxxb\/micropython,PappaPeppar\/micropython,TDAbboud\/micropython,selste\/micropython,micropython\/micropython-esp32,mgyenik\/micropython,dmazzella\/micropython,mianos\/micropython,blazewicz\/micropython,micropython\/micropython-esp32,trezor\/micropython,KISSMonX\/micropython,ernesto-g\/micropython,selste\/micropython,vitiral\/micropython,ernesto-g\/micropython,galenhz\/micropython,ahotam\/micropython,EcmaXp\/micropython,chrisdearman\/micropython,adamkh\/micropython,cnoviello\/micropython,feilongfl\/micropython,vriera\/micropython,adafruit\/circuitpython,warner83\/micropython,vitiral\/micropython,heisewangluo\/micropython,puuu\/micropython,henriknelson\/micropython,firstval\/micropython,TDAbboud\/micropython,toolmacher\/micropython,blmorris\/micropython,adafruit\/circuitpython,ceramos\/micropython,turbinenreiter\/micropython,KISSMonX\/micropython,kostyll\/micropython,pramasoul\/micropython,supergis\/micropython,omtinez\/micropython,tralamazza\/micropython,swegener\/micropython,selste\/micropython,skybird6672\/micropython,swegener\/micropython,alex-march\/micropython,jimkmc\/micropython,tdautc19841202\/micropython,emfcamp\/micropython,AriZuu\/micropython,jlillest\/micropython,mpalomer\/micropython,selste\/micropython,tralamazza\/micropython,bvernoux\/micropython,noahchense\/micropython,TDAbboud\/micropython,micropython\/micropython-esp32,firstval\/micropython,dinau\/micropython,suda\/micropython,kostyll\/micropython,praemdonck\/micropython,xyb\/micropython,PappaPeppar\/micropython,noahwilliamsson\/micropython,neilh10\/micropython,lowRISC\/micropython,skybird6672\/micropython,MrSurly\/micropython-esp32,omtinez\/micropython,SHA2017-badge\/micropython-esp32,xhat\/micropython,pozetroninc\/micropython,bvernoux\/micropython,alex-march\/micropython,heisewangluo\/micropython,vriera\/micropython,rubencabrera\/micropython,ahotam\/micropython,matthewelse\/micropython,skybird6672\/micropython,ganshun666\/micropython,ganshun666\/micropython,swegener\/micropython,feilongfl\/micropython,tralamazza\/micropython,jimkmc\/micropython,galenhz\/micropython,MrSurly\/micropython-esp32,cnoviello\/micropython,kerneltask\/micropython,trezor\/micropython,galenhz\/micropython,puuu\/micropython,ernesto-g\/micropython,puuu\/micropython,KISSMonX\/micropython,ernesto-g\/micropython,heisewangluo\/micropython,ericsnowcurrently\/micropython,alex-march\/micropython,HenrikSolver\/micropython,redbear\/micropython,jlillest\/micropython,blazewicz\/micropython,deshipu\/micropython,jmarcelino\/pycom-micropython,PappaPeppar\/micropython,ChuckM\/micropython,ryannathans\/micropython,mgyenik\/micropython,blazewicz\/micropython,hosaka\/micropython,vitiral\/micropython,feilongfl\/micropython,KISSMonX\/micropython,trezor\/micropython,mhoffma\/micropython,jimkmc\/micropython,orionrobots\/micropython,hiway\/micropython,dhylands\/micropython,ChuckM\/micropython,jimkmc\/micropython,adamkh\/micropython,ernesto-g\/micropython,ericsnowcurrently\/micropython,dinau\/micropython,ChuckM\/micropython,rubencabrera\/micropython,pramasoul\/micropython,chrisdearman\/micropython,puuu\/micropython,cloudformdesign\/micropython,oopy\/micropython,kostyll\/micropython,ahotam\/micropython,methoxid\/micropystat,ChuckM\/micropython,redbear\/micropython,Vogtinator\/micropython,drrk\/micropython,pozetroninc\/micropython,cloudformdesign\/micropython,MrSurly\/micropython,puuu\/micropython,noahwilliamsson\/micropython,tobbad\/micropython,Timmenem\/micropython,tuc-osg\/micropython,lowRISC\/micropython,micropython\/micropython-esp32,emfcamp\/micropython,ericsnowcurrently\/micropython,EcmaXp\/micropython,dhylands\/micropython,ruffy91\/micropython,noahwilliamsson\/micropython,cwyark\/micropython,infinnovation\/micropython,mgyenik\/micropython,SHA2017-badge\/micropython-esp32,paul-xxx\/micropython,pfalcon\/micropython,henriknelson\/micropython,torwag\/micropython,ahotam\/micropython,xhat\/micropython,infinnovation\/micropython,cnoviello\/micropython,misterdanb\/micropython,bvernoux\/micropython,xhat\/micropython,redbear\/micropython,dinau\/micropython,blazewicz\/micropython,matthewelse\/micropython,cloudformdesign\/micropython,warner83\/micropython,galenhz\/micropython,xyb\/micropython,deshipu\/micropython,adafruit\/micropython,rubencabrera\/micropython,HenrikSolver\/micropython,aethaniel\/micropython,SHA2017-badge\/micropython-esp32,orionrobots\/micropython,MrSurly\/micropython-esp32,TDAbboud\/micropython,lbattraw\/micropython,praemdonck\/micropython,Vogtinator\/micropython,mhoffma\/micropython,lbattraw\/micropython,deshipu\/micropython,kerneltask\/micropython,AriZuu\/micropython,slzatz\/micropython,Peetz0r\/micropython-esp32,ruffy91\/micropython,kerneltask\/micropython,infinnovation\/micropython,alex-robbins\/micropython,pfalcon\/micropython,noahwilliamsson\/micropython,pramasoul\/micropython,blmorris\/micropython,firstval\/micropython,alex-march\/micropython,PappaPeppar\/micropython,blmorris\/micropython,pozetroninc\/micropython,chrisdearman\/micropython,firstval\/micropython,turbinenreiter\/micropython,dxxb\/micropython,ceramos\/micropython,paul-xxx\/micropython,redbear\/micropython,utopiaprince\/micropython,blmorris\/micropython,martinribelotta\/micropython,danicampora\/micropython,emfcamp\/micropython,utopiaprince\/micropython,TDAbboud\/micropython,hiway\/micropython,kostyll\/micropython,orionrobots\/micropython,toolmacher\/micropython,vitiral\/micropython,Timmenem\/micropython,mianos\/micropython,xyb\/micropython,alex-march\/micropython,EcmaXp\/micropython,jlillest\/micropython,hiway\/micropython,adafruit\/micropython,ericsnowcurrently\/micropython,Vogtinator\/micropython,mhoffma\/micropython,misterdanb\/micropython,danicampora\/micropython,turbinenreiter\/micropython,infinnovation\/micropython,jlillest\/micropython,swegener\/micropython,slzatz\/micropython,heisewangluo\/micropython,stonegithubs\/micropython,Timmenem\/micropython,xuxiaoxin\/micropython,adafruit\/micropython,suda\/micropython,MrSurly\/micropython-esp32,vriera\/micropython,oopy\/micropython,martinribelotta\/micropython,ganshun666\/micropython,Timmenem\/micropython,tobbad\/micropython,tuc-osg\/micropython,jimkmc\/micropython,hosaka\/micropython,MrSurly\/micropython,firstval\/micropython,MrSurly\/micropython,stonegithubs\/micropython,noahchense\/micropython,methoxid\/micropystat,mgyenik\/micropython,lbattraw\/micropython,dinau\/micropython,martinribelotta\/micropython,methoxid\/micropystat,mianos\/micropython,omtinez\/micropython,rubencabrera\/micropython,adafruit\/circuitpython,aitjcize\/micropython,ryannathans\/micropython,cwyark\/micropython,torwag\/micropython,cloudformdesign\/micropython,matthewelse\/micropython,EcmaXp\/micropython,cloudformdesign\/micropython,praemdonck\/micropython,noahchense\/micropython,adafruit\/circuitpython,supergis\/micropython,pozetroninc\/micropython,neilh10\/micropython,hiway\/micropython,alex-robbins\/micropython,adafruit\/micropython,swegener\/micropython,pramasoul\/micropython,mhoffma\/micropython,ChuckM\/micropython,cnoviello\/micropython,supergis\/micropython,drrk\/micropython,aethaniel\/micropython,methoxid\/micropystat,aethaniel\/micropython,ruffy91\/micropython,Vogtinator\/micropython,ganshun666\/micropython,xyb\/micropython,skybird6672\/micropython,kerneltask\/micropython,Peetz0r\/micropython-esp32,ceramos\/micropython,jlillest\/micropython,bvernoux\/micropython,oopy\/micropython,dinau\/micropython,MrSurly\/micropython-esp32,tdautc19841202\/micropython,toolmacher\/micropython,dmazzella\/micropython,cwyark\/micropython,bvernoux\/micropython,HenrikSolver\/micropython,pfalcon\/micropython,tobbad\/micropython,lbattraw\/micropython,ruffy91\/micropython,feilongfl\/micropython,SungEun-Steve-Kim\/test-mp,kerneltask\/micropython,AriZuu\/micropython,dhylands\/micropython,lbattraw\/micropython,dxxb\/micropython,pozetroninc\/micropython,warner83\/micropython,AriZuu\/micropython,cnoviello\/micropython,slzatz\/micropython,mianos\/micropython,oopy\/micropython,jmarcelino\/pycom-micropython,tdautc19841202\/micropython,matthewelse\/micropython,ryannathans\/micropython,misterdanb\/micropython,aitjcize\/micropython,orionrobots\/micropython,ganshun666\/micropython,martinribelotta\/micropython,hosaka\/micropython,vriera\/micropython,lowRISC\/micropython,praemdonck\/micropython,mgyenik\/micropython,misterdanb\/micropython,pfalcon\/micropython,chrisdearman\/micropython,henriknelson\/micropython,rubencabrera\/micropython,vriera\/micropython,adafruit\/circuitpython,alex-robbins\/micropython,SungEun-Steve-Kim\/test-mp,warner83\/micropython,mpalomer\/micropython,suda\/micropython,MrSurly\/micropython,dxxb\/micropython,PappaPeppar\/micropython,tobbad\/micropython,ceramos\/micropython,infinnovation\/micropython,mpalomer\/micropython,lowRISC\/micropython,danicampora\/micropython,ruffy91\/micropython,paul-xxx\/micropython,SHA2017-badge\/micropython-esp32,alex-robbins\/micropython,turbinenreiter\/micropython,neilh10\/micropython,emfcamp\/micropython,xhat\/micropython,tdautc19841202\/micropython,suda\/micropython,matthewelse\/micropython,methoxid\/micropystat,Vogtinator\/micropython,paul-xxx\/micropython,blazewicz\/micropython,SungEun-Steve-Kim\/test-mp,xhat\/micropython,supergis\/micropython,ryannathans\/micropython,alex-robbins\/micropython,slzatz\/micropython,tobbad\/micropython,torwag\/micropython,hosaka\/micropython,jmarcelino\/pycom-micropython,jmarcelino\/pycom-micropython,neilh10\/micropython,HenrikSolver\/micropython,blmorris\/micropython,misterdanb\/micropython,noahchense\/micropython,henriknelson\/micropython,noahwilliamsson\/micropython,ahotam\/micropython,EcmaXp\/micropython,warner83\/micropython,lowRISC\/micropython,adafruit\/micropython,drrk\/micropython,dhylands\/micropython","old_file":"stm\/stm32f405.ld","new_file":"stm\/stm32f405.ld","new_contents":"\/*\n    GNU linker script for STM32F405\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 \/* sector 0, 16 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x080000 \/* sectors 5,6,7,8, 4*128KiB = 512 KiB (could increase it more) *\/\n    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 0x010000 \/* 64 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x020000 \/* 128 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n   \n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH_TEXT\n     \n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n        \n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n            \n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n    GNU linker script for STM32F405\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 \/* sector 0, 16 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x020000 \/* sector 5, 128 KiB *\/\n    CCMRAM (xrw)    : ORIGIN = 0x10000000, LENGTH = 0x010000 \/* 64 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x020000 \/* 128 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n   \n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH_TEXT\n     \n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n        \n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n            \n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e257791eb1bb779768b487e1c3091368230a50b6","subject":"boards\/layout_opentitan.ld: Update memory addresses","message":"boards\/layout_opentitan.ld: Update memory addresses\n\nSigned-off-by: Alistair Francis <52ecf00b70a50079ae8d5fa09b9af6904950b63c@wdc.com>\n","repos":"tock\/libtock-rs","old_file":"boards\/layout_opentitan.ld","new_file":"boards\/layout_opentitan.ld","new_contents":"\/* Layout for the RISC-V 32 boards, used by the examples in this repository. *\/\n\nMEMORY {\n  \/*\n   * The TBF header can change in size so use 0x40 combined with\n   * --protected-region-size with elf2tab to cover a header upto that\n   * size.\n   *\n   * Note that the SRAM address may need to be changed depending on\n   * the kernel binary, check for the actual address of APP_MEMORY!\n   *\/\n  FLASH (rx) : ORIGIN = 0x20030040, LENGTH = 32M\n  SRAM (rwx) : ORIGIN = 0x10004000, LENGTH = 512K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 1K;\n\nINCLUDE layout_generic.ld\n","old_contents":"\/* Layout for the RISC-V 32 boards, used by the examples in this repository. *\/\n\nMEMORY {\n  \/*\n   * The TBF header can change in size so use 0x40 combined with\n   * --protected-region-size with elf2tab to cover a header upto that\n   * size.\n   *\n   * Note that the SRAM address may need to be changed depending on\n   * the kernel binary, check for the actual address of APP_MEMORY!\n   *\/\n  FLASH (rx) : ORIGIN = 0x20030040, LENGTH = 32M\n  SRAM (rwx) : ORIGIN = 0x10003000, LENGTH = 512K\n}\n\n\/*\n * Any change to STACK_SIZE should be accompanied by a corresponding change to\n * `elf2tab`'s `--stack` option\n *\/\nSTACK_SIZE = 2048;\n\nMPU_MIN_ALIGN = 1K;\n\nINCLUDE layout_generic.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"0169ea5155d553094d33613e94a6c597ee2e0860","subject":"nrf: discard arm exception sections","message":"nrf: discard arm exception sections\n\nSince these exceptions are unused, don't include them in the output\nbinary.\n\nSigned-off-by: Sean Cross <d7e19930cc1f42c2d0781f4d9e6f1fe5891bf9cf@xobs.io>\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython","old_file":"ports\/nrf\/boards\/common.template.ld","new_file":"ports\/nrf\/boards\/common.template.ld","new_contents":"\/*\n    GNU linker script for NRF52840 w\/ s140 6.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = ${FLASH_SIZE} \/* entire flash *\/\n    \/* nRF SoftDevice *\/\n    FLASH_MBR (rx)  : ORIGIN = ${MBR_START_ADDR}, LENGTH = ${MBR_SIZE}\n    FLASH_SD (rx)   : ORIGIN = ${SD_FLASH_START_ADDR}, LENGTH = ${SD_FLASH_SIZE}\n    FLASH_ISR (rx)  : ORIGIN = ${ISR_START_ADDR}, LENGTH = ${ISR_SIZE}\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_BLE_CONFIG (r) : ORIGIN = ${CIRCUITPY_BLE_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_BLE_CONFIG_SIZE}\n    FLASH_NVM (r)   : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n    FLASH_FATFS (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_BOOTLOADER (rx) : ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n    FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}\n\n\n    \/* 0x2000000 - RAM:ORIGIN is reserved for Softdevice *\/\n    \/* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.\n    \/* To measure the minimum required amount of memory for given configuration, set this number\n       high enough to work and then check the mutation of the value done by sd_ble_enable. *\/\n    SPIM3_RAM (rw)  : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE}\n    RAM (xrw)       : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = ${RAM_SIZE} - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE}\n\n}\n\n\/* produce a link error if there is not this amount of RAM available *\/\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\n\/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. *\/\n_spim3_ram = ORIGIN(SPIM3_RAM);\n_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_FIRMWARE\n\n    \/* used by the startup to initialize data *\/\n    _sidata = .;\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* Zero-initialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Uninitialized data section\n    Data placed into this section will remain unchanged across reboots. *\/\n    .uninitialized (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _suninitialized = .; \/* define a global symbol at uninitialized start; currently unused *\/\n        *(.uninitialized)\n        *(.uninitialized*)\n\n        . = ALIGN(4);\n        _euninitialized = .; \/* define a global symbol at uninitialized end; currently unused *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\t      PROVIDE ( end = . );\n\t      PROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove exception unwinding information, since Circuit Python\n       does not support this GCC feature. *\/\n    \/DISCARD\/ :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n        *(.ARM.exidx*)\n    }\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n    GNU linker script for NRF52840 w\/ s140 6.0.0 SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = ${FLASH_SIZE} \/* entire flash *\/\n    \/* nRF SoftDevice *\/\n    FLASH_MBR (rx)  : ORIGIN = ${MBR_START_ADDR}, LENGTH = ${MBR_SIZE}\n    FLASH_SD (rx)   : ORIGIN = ${SD_FLASH_START_ADDR}, LENGTH = ${SD_FLASH_SIZE}\n    FLASH_ISR (rx)  : ORIGIN = ${ISR_START_ADDR}, LENGTH = ${ISR_SIZE}\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_BLE_CONFIG (r) : ORIGIN = ${CIRCUITPY_BLE_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_BLE_CONFIG_SIZE}\n    FLASH_NVM (r)   : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n    FLASH_FATFS (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_BOOTLOADER (rx) : ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n    FLASH_BOOTLOADER_SETTINGS (r) : ORIGIN = ${BOOTLOADER_SETTINGS_START_ADDR}, LENGTH = ${BOOTLOADER_SETTINGS_SIZE}\n\n\n    \/* 0x2000000 - RAM:ORIGIN is reserved for Softdevice *\/\n    \/* SoftDevice 6.1.0 with 5 connections and various increases takes just under 64kiB.\n    \/* To measure the minimum required amount of memory for given configuration, set this number\n       high enough to work and then check the mutation of the value done by sd_ble_enable. *\/\n    SPIM3_RAM (rw)  : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE}, LENGTH = ${SPIM3_BUFFER_SIZE}\n    RAM (xrw)       : ORIGIN = 0x20000000 + ${SOFTDEVICE_RAM_SIZE} + ${SPIM3_BUFFER_SIZE}, LENGTH = ${RAM_SIZE} - ${SOFTDEVICE_RAM_SIZE} -${SPIM3_BUFFER_SIZE}\n\n}\n\n\/* produce a link error if there is not this amount of RAM available *\/\n_minimum_heap_size = 0;\n\n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20020000; \/* tunable *\/\n\n\/* nrf52840 SPIM3 needs its own area to work around hardware problems. Nothing else may use this space. *\/\n_spim3_ram = ORIGIN(SPIM3_RAM);\n_spim3_ram_end = ORIGIN(SPIM3_RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_FIRMWARE\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH_FIRMWARE\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH_FIRMWARE\n\n    \/* used by the startup to initialize data *\/\n    _sidata = .;\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* Zero-initialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Uninitialized data section\n    Data placed into this section will remain unchanged across reboots. *\/\n    .uninitialized (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _suninitialized = .; \/* define a global symbol at uninitialized start; currently unused *\/\n        *(.uninitialized)\n        *(.uninitialized*)\n\n        . = ALIGN(4);\n        _euninitialized = .; \/* define a global symbol at uninitialized end; currently unused *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\t      PROVIDE ( end = . );\n\t      PROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7ac51be06d266d9c1666daadefa2a548adb706a1","subject":"arch\/x86: discard .note sections","message":"arch\/x86: discard .note sections\n","repos":"uni-rs\/uni.rs","old_file":"src\/arch\/i686\/linker.ld","new_file":"src\/arch\/i686\/linker.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSECTIONS\n{\n    . = 0x0;\n\n    .text : {\n        *(.text)\n        *(.text.*)\n    }\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    . = ALIGN(4096);\n\n    . += 8192;\n    _stack_start = .;\n\n    .data : {\n        *(.data)\n    }\n\n    \/DISCARD\/ : {\n        *(.note.*)\n    }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\n\nSECTIONS\n{\n    . = 0x0;\n\n    .text : {\n        *(.text)\n        *(.text.*)\n    }\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    . = ALIGN(4096);\n\n    . += 8192;\n    _stack_start = .;\n\n    .data : {\n        *(.data)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3b594f7b27881818645a52d7aa9469c97ef10ecf","subject":"nrf\/boards\/common.ld: Calculate unused flash region.","message":"nrf\/boards\/common.ld: Calculate unused flash region.\n\nCalculate the unused flash area on the target device.  The values will be\nexposed by _unused_flash_start and _unused_flash_length.  The start address\nand the length are not aligned to either word or pages.\n","repos":"adafruit\/circuitpython,bvernoux\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,bvernoux\/micropython,bvernoux\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,bvernoux\/micropython,bvernoux\/micropython,adafruit\/circuitpython","old_file":"ports\/nrf\/boards\/common.ld","new_file":"ports\/nrf\/boards\/common.ld","new_contents":"ENTRY(Reset_Handler)\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n        *(.text)             \/* .text sections (code) *\/\n        *(.text*)            \/* .text* sections (code) *\/\n        *(.rodata)           \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)          \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/      \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/      \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;          \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n\n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n\n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT>FLASH_TEXT\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\/* Define heap and stack areas *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n_unused_flash_start = (_sidata + (_edata - _sdata));\n_unused_flash_len = (ORIGIN(FLASH_TEXT) + LENGTH(FLASH_TEXT)) - _unused_flash_start;\n","old_contents":"ENTRY(Reset_Handler)\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n        *(.text)             \/* .text sections (code) *\/\n        *(.text*)            \/* .text* sections (code) *\/\n        *(.rodata)           \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)          \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/      \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/      \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;          \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n\n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n\n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT>FLASH_TEXT\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\/* Define heap and stack areas *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4fab12ec24b5e668b138943ecb3b1c766a4868be","subject":"tweak authors","message":"tweak authors","repos":"ggreif\/al4nin,ggreif\/al4nin","old_file":"purgatory\/db\/refs.ld","new_file":"purgatory\/db\/refs.ld","new_contents":"{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.category }\n   @Author { Wikipedia }\n   @Title { Category (mathematics) }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Category_(mathematics) }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.free-monoid }\n   @Author { Wikipedia }\n   @Title { Free monoid }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Free_monoid }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.groupoid }\n   @Author { Wikipedia }\n   @Title { Groupoid }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Groupoid }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.dominoes }\n   @Author { Wikipedia }\n   @Title { Dominoes }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Dominoes }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { roundy.darcs2 }\n   @Author { Wikipedia }\n   @Title { Darcs }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Darcs }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikibooks.patch }\n   @Author { Wikibooks }\n   @Title { Understanding darcs\"\/\"Patch theory }\n   @URL { http:\/\/en.wikibooks.org\/wiki\/Understanding_darcs\/Patch_theory }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { cil.intro }\n   @Author { Wikipedia }\n   @Title { Common Intermediate Language }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Common_Intermediate_Language }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { jvm.intro }\n   @Author { Wikipedia }\n   @Title { Java bytecode }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Java_bytecode }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { cat.intro }\n   @Author { Christopher Diggins }\n   @Title { The Cat Programming Language }\n   @URL { http:\/\/www.cat-language.com\/ }\n}\n\n{ @Reference\n   @Type { InProceedings }\n   @Tag { mcbride07.rstar }\n   @Author { Conor McBride }\n   @InTitle { Fun in the Afternoon }\n   @Title { R* is the new [{@Sym alpha}] }\n   @URL { http:\/\/sneezy.cs.nott.ac.uk\/fun\/nov-07\/R-star.pdf }\n   @Month { Nov }\n   @Year { 2007 }\n}\n","old_contents":"{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.category }\n   @Title { Wikipedia: Category (mathematics) }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Category_(mathematics) }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.free-monoid }\n   @Title { Wikipedia: Free monoid }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Free_monoid }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.groupoid }\n   @Title { Wikipedia: Groupoid }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Groupoid }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikipedia.dominoes }\n   @Title { Wikipedia: Dominoes }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Dominoes }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { roundy.darcs2 }\n   @Title { Wikipedia: Darcs }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Darcs }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { wikibooks.patch }\n   @Title { Wikibooks: Understanding darcs\"\/\"Patch theory }\n   @URL { http:\/\/en.wikibooks.org\/wiki\/Understanding_darcs\/Patch_theory }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { cil.intro }\n   @Title { Wikipedia: Common Intermediate Language }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Common_Intermediate_Language }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { jvm.intro }\n   @Title { Wikipedia: Java bytecode }\n   @URL { http:\/\/en.wikipedia.org\/wiki\/Java_bytecode }\n}\n\n{ @Reference\n   @Type { Misc }\n   @Tag { cat.intro }\n   @Title { The Cat Programming Language }\n   @URL { http:\/\/www.cat-language.com\/ }\n}\n\n{ @Reference\n   @Type { InProceedings }\n   @Tag { mcbride07.rstar }\n   @Author { Conor McBride }\n   @InTitle { Fun in the Afternoon }\n   @Title { R* is the new [{@Sym alpha}] }\n   @URL { http:\/\/sneezy.cs.nott.ac.uk\/fun\/nov-07\/R-star.pdf }\n   @Month { Nov }\n   @Year { 2007 }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"61f64c78a6c3ebfe42292b0ff9c93442883f5f0d","subject":"nrf\/boards\/common.ld: Add ENTRY(Reset_Handler) in linker script.","message":"nrf\/boards\/common.ld: Add ENTRY(Reset_Handler) in linker script.\n\nIt's not strictly needed but can be helpful when using a debugger.\n","repos":"selste\/micropython,adafruit\/circuitpython,bvernoux\/micropython,bvernoux\/micropython,tobbad\/micropython,henriknelson\/micropython,kerneltask\/micropython,adafruit\/circuitpython,pramasoul\/micropython,tobbad\/micropython,pramasoul\/micropython,henriknelson\/micropython,kerneltask\/micropython,henriknelson\/micropython,henriknelson\/micropython,pozetroninc\/micropython,MrSurly\/micropython,kerneltask\/micropython,bvernoux\/micropython,MrSurly\/micropython,tobbad\/micropython,pozetroninc\/micropython,adafruit\/circuitpython,bvernoux\/micropython,pramasoul\/micropython,pramasoul\/micropython,MrSurly\/micropython,pozetroninc\/micropython,tobbad\/micropython,bvernoux\/micropython,pramasoul\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,pozetroninc\/micropython,MrSurly\/micropython,henriknelson\/micropython,tobbad\/micropython,MrSurly\/micropython,selste\/micropython,selste\/micropython,adafruit\/circuitpython,kerneltask\/micropython,selste\/micropython,selste\/micropython,pozetroninc\/micropython,kerneltask\/micropython","old_file":"ports\/nrf\/boards\/common.ld","new_file":"ports\/nrf\/boards\/common.ld","new_contents":"ENTRY(Reset_Handler)\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n        *(.text)             \/* .text sections (code) *\/\n        *(.text*)            \/* .text* sections (code) *\/\n        *(.rodata)           \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)          \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/      \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/      \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;          \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n\n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n\n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT>FLASH_TEXT\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\/* Define heap and stack areas *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n","old_contents":"\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n        *(.text)             \/* .text sections (code) *\/\n        *(.text*)            \/* .text* sections (code) *\/\n        *(.rodata)           \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)          \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/      \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/      \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;          \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n\n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n\n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT>FLASH_TEXT\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\/* Define heap and stack areas *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"aaa09d54828e17a34d74933516712dc75498c126","subject":"Added missing subscription","message":"Added missing subscription\n","repos":"c1728p9\/mbed-os,betzw\/mbed-os,mazimkhan\/mbed-os,Archcady\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,karsev\/mbed-os,mbedmicro\/mbed,mazimkhan\/mbed-os,andcor02\/mbed-os,karsev\/mbed-os,mazimkhan\/mbed-os,mazimkhan\/mbed-os,betzw\/mbed-os,mbedmicro\/mbed,karsev\/mbed-os,kjbracey-arm\/mbed,betzw\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,mazimkhan\/mbed-os,betzw\/mbed-os,karsev\/mbed-os,karsev\/mbed-os,karsev\/mbed-os,betzw\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,betzw\/mbed-os,andcor02\/mbed-os,Archcady\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,c1728p9\/mbed-os,c1728p9\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,Archcady\/mbed-os,Archcady\/mbed-os,mazimkhan\/mbed-os,c1728p9\/mbed-os,kjbracey-arm\/mbed,Archcady\/mbed-os,Archcady\/mbed-os","old_file":"targets\/TARGET_Freescale\/TARGET_MCUXpresso_MCUS\/TARGET_MCU_K24F\/TARGET_MCU_K24F1M\/device\/TOOLCHAIN_GCC_ARM\/MK24FN1M0xxx12.ld","new_file":"targets\/TARGET_Freescale\/TARGET_MCUXpresso_MCUS\/TARGET_MCU_K24F\/TARGET_MCU_K24F1M\/device\/TOOLCHAIN_GCC_ARM\/MK24FN1M0xxx12.ld","new_contents":"\/*\n** ###################################################################\n**     Processors:          MK64FN1M0VDC12\n**                          MK64FN1M0VLL12\n**                          MK64FN1M0VLQ12\n**                          MK64FN1M0VMD12\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014\n**     Version:             rev. 2.8, 2015-02-19\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n__ram_vector_table__ = 1;\n\n\/* Heap 1\/4 of ram and stack 1\/8 *\/\n__stack_size__ = 0x8000;\n__heap_size__ = 0x10000;\n\n#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 0x100000\n#endif\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x8000;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x10000;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = MBED_APP_START, LENGTH = 0x400\n  m_flash_config        (RX)  : ORIGIN = MBED_APP_START + 0x400, LENGTH = 0x10\n  m_text                (RX)  : ORIGIN = MBED_APP_START + 0x410, LENGTH = MBED_APP_SIZE - 0x410\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: FLASH_OFFSET. *\/\n  __UVISOR_TEXT_OFFSET = 0x410;\n  __UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET;\n  .text __UVISOR_TEXT_START :\n  {\n    \/* uVisor code and data *\/\n    . = ALIGN(4);\n    __uvisor_main_start = .;\n    *(.uvisor.main)\n    __uvisor_main_end = .;\n\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  \/* Ensure that the uVisor BSS section is put first after the relocated\n   * interrupt table in SRAM. *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: SRAM_OFFSET. *\/\n  __UVISOR_SRAM_OFFSET = 0x400;\n  __UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;\n  ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,\n         \"The ISR relocation region overlaps with the uVisor BSS section.\")\n  .uvisor.bss __UVISOR_BSS_START (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uvisor_bss_start = .;\n\n    \/* protected uvisor main bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_main_start = .;\n    KEEP(*(.keep.uvisor.bss.main))\n    . = ALIGN(32);\n    __uvisor_bss_main_end = .;\n\n    \/* protected uvisor secure boxes bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_boxes_start = .;\n    KEEP(*(.keep.uvisor.bss.boxes))\n    . = ALIGN(32);\n    __uvisor_bss_boxes_end = .;\n\n    . = ALIGN(32);\n    __uvisor_bss_end = .;\n  } > m_data\n\n  \/* Heap space for the page allocator *\/\n  .page_heap (NOLOAD) :\n  {\n    . = ALIGN(32);\n    __uvisor_page_start = .;\n    KEEP(*(.keep.uvisor.page_heap))\n    . = ALIGN(32);\n    __uvisor_page_end = .;\n  } > m_data_2\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data :\n  {\n    PROVIDE(__etext = LOADADDR(.data));    \/* Define a global symbol at end of code, *\/\n    PROVIDE(__DATA_ROM = LOADADDR(.data)); \/* Symbol is used by startup for data initialization. *\/\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data_2 AT > m_text\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  \/* uVisor configuration section\n   * This section must be located after all other flash regions. *\/\n  .uvisor.secure :\n  {\n    . = ALIGN(32);\n    __uvisor_secure_start = .;\n\n    \/* uVisor secure boxes configuration tables *\/\n    . = ALIGN(32);\n    __uvisor_cfgtbl_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl))\n    . = ALIGN(32);\n    __uvisor_cfgtbl_end = .;\n\n    \/* Pointers to the uVisor secure boxes configuration tables *\/\n    \/* Note: Do not add any further alignment here, as uVisor will need to have\n     * access to the exact list of pointers. *\/\n    __uvisor_cfgtbl_ptr_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n    KEEP(*(.keep.uvisor.cfgtbl_ptr))\n    __uvisor_cfgtbl_ptr_end = .;\n\n    \/* Pointers to all boxes register gateways. These are grouped here to allow\n     * discoverability and firmware verification. *\/\n    __uvisor_register_gateway_ptr_start = .;\n    KEEP(*(.keep.uvisor.register_gateway_ptr))\n    __uvisor_register_gateway_ptr_end = .;\n\n    . = ALIGN(32);\n    __uvisor_secure_end = .;\n  } > m_text\n\n  \/* Uninitialized data section\n   * This region is not initialized by the C\/C++ library and can be used to\n   * store state across soft reboots. *\/\n  .uninitialized (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uninitialized_start = .;\n    *(.uninitialized)\n    KEEP(*(.keep.uninitialized))\n    . = ALIGN(32);\n    __uninitialized_end = .;\n  } > m_data_2\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data_2\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __uvisor_heap_start = .;\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n    __uvisor_heap_end = .;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n\n  \/* Provide the physical memory boundaries for uVisor. *\/\n  __uvisor_flash_start = ORIGIN(m_interrupts);\n  __uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);\n  __uvisor_sram_start = ORIGIN(m_data);\n  __uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);\n}\n","old_contents":"\/*\n** ###################################################################\n**     Processors:          MK64FN1M0VDC12\n**                          MK64FN1M0VLL12\n**                          MK64FN1M0VLQ12\n**                          MK64FN1M0VMD12\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014\n**     Version:             rev. 2.8, 2015-02-19\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n__ram_vector_table__ = 1;\n\n\/* Heap 1\/4 of ram and stack 1\/8 *\/\n__stack_size__ = 0x8000;\n__heap_size__ = 0x10000;\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: FLASH_OFFSET. *\/\n  __UVISOR_TEXT_OFFSET = 0x410;\n  __UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET;\n  .text __UVISOR_TEXT_START :\n  {\n    \/* uVisor code and data *\/\n    . = ALIGN(4);\n    __uvisor_main_start = .;\n    *(.uvisor.main)\n    __uvisor_main_end = .;\n\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  \/* Ensure that the uVisor BSS section is put first after the relocated\n   * interrupt table in SRAM. *\/\n  \/* Note: The uVisor expects this section at a fixed location, as specified by\n   * the porting process configuration parameter: SRAM_OFFSET. *\/\n  __UVISOR_SRAM_OFFSET = 0x400;\n  __UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;\n  ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,\n         \"The ISR relocation region overlaps with the uVisor BSS section.\")\n  .uvisor.bss __UVISOR_BSS_START (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uvisor_bss_start = .;\n\n    \/* protected uvisor main bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_main_start = .;\n    KEEP(*(.keep.uvisor.bss.main))\n    . = ALIGN(32);\n    __uvisor_bss_main_end = .;\n\n    \/* protected uvisor secure boxes bss *\/\n    . = ALIGN(32);\n    __uvisor_bss_boxes_start = .;\n    KEEP(*(.keep.uvisor.bss.boxes))\n    . = ALIGN(32);\n    __uvisor_bss_boxes_end = .;\n\n    . = ALIGN(32);\n    __uvisor_bss_end = .;\n  } > m_data\n\n  \/* Heap space for the page allocator *\/\n  .page_heap (NOLOAD) :\n  {\n    . = ALIGN(32);\n    __uvisor_page_start = .;\n    KEEP(*(.keep.uvisor.page_heap))\n    . = ALIGN(32);\n    __uvisor_page_end = .;\n  } > m_data_2\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data :\n  {\n    PROVIDE(__etext = LOADADDR(.data));    \/* Define a global symbol at end of code, *\/\n    PROVIDE(__DATA_ROM = LOADADDR(.data)); \/* Symbol is used by startup for data initialization. *\/\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data_2 AT > m_text\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  \/* uVisor configuration section\n   * This section must be located after all other flash regions. *\/\n  .uvisor.secure :\n  {\n    . = ALIGN(32);\n    __uvisor_secure_start = .;\n\n    \/* uVisor secure boxes configuration tables *\/\n    . = ALIGN(32);\n    __uvisor_cfgtbl_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl))\n    . = ALIGN(32);\n    __uvisor_cfgtbl_end = .;\n\n    \/* Pointers to the uVisor secure boxes configuration tables *\/\n    \/* Note: Do not add any further alignment here, as uVisor will need to have\n     * access to the exact list of pointers. *\/\n    __uvisor_cfgtbl_ptr_start = .;\n    KEEP(*(.keep.uvisor.cfgtbl_ptr_first))\n    KEEP(*(.keep.uvisor.cfgtbl_ptr))\n    __uvisor_cfgtbl_ptr_end = .;\n\n    \/* Pointers to all boxes register gateways. These are grouped here to allow\n     * discoverability and firmware verification. *\/\n    __uvisor_register_gateway_ptr_start = .;\n    KEEP(*(.keep.uvisor.register_gateway_ptr))\n    __uvisor_register_gateway_ptr_end = .;\n\n    . = ALIGN(32);\n    __uvisor_secure_end = .;\n  } > m_text\n\n  \/* Uninitialized data section\n   * This region is not initialized by the C\/C++ library and can be used to\n   * store state across soft reboots. *\/\n  .uninitialized (NOLOAD):\n  {\n    . = ALIGN(32);\n    __uninitialized_start = .;\n    *(.uninitialized)\n    KEEP(*(.keep.uninitialized))\n    . = ALIGN(32);\n    __uninitialized_end = .;\n  } > m_data_2\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data_2\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __uvisor_heap_start = .;\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n    __uvisor_heap_end = .;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n\n  \/* Provide the physical memory boundaries for uVisor. *\/\n  __uvisor_flash_start = ORIGIN(m_interrupts);\n  __uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);\n  __uvisor_sram_start = ORIGIN(m_data);\n  __uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"49266c161c2c2f2b5b282e9a53696c905b7199cb","subject":"Remove TOOLCHAIN_GCC_CW_NEWLIB files","message":"Remove TOOLCHAIN_GCC_CW_NEWLIB files\n","repos":"andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed,kjbracey-arm\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed","old_file":"targets\/TARGET_Freescale\/TARGET_KLXX\/TARGET_KL25Z\/device\/TOOLCHAIN_GCC_CW_NEWLIB\/MKL25Z4.ld","new_file":"targets\/TARGET_Freescale\/TARGET_KLXX\/TARGET_KL25Z\/device\/TOOLCHAIN_GCC_CW_NEWLIB\/MKL25Z4.ld","new_contents":"","old_contents":"\/* Linker script for mbed LPC1768 *\/\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K\n  RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 0x3F40\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text.Reset_Handler)\n        *(.text.SystemInit)\n        \n        \/* Only vectors and code running at reset are safe to be in first 512\n           bytes since RAM can be mapped into this area for RAM based interrupt\n           vectors. *\/\n        . = 0x00000200;\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e21f18505d7e594680e6b0c28ec9067772a33746","subject":"firmware\/lm32: use sram as ram (will allow reducing firmware_ram size)","message":"firmware\/lm32: use sram as ram (will allow reducing firmware_ram size)\n","repos":"cr1901\/HDMI2USB-litex-firmware,mithro\/HDMI2USB-litex-firmware,mithro\/HDMI2USB-litex-firmware,cr1901\/HDMI2USB-litex-firmware,cr1901\/HDMI2USB-litex-firmware,mithro\/HDMI2USB-litex-firmware,cr1901\/HDMI2USB-litex-firmware,mithro\/HDMI2USB-litex-firmware","old_file":"firmware\/lm32\/linker.ld","new_file":"firmware\/lm32\/linker.ld","new_contents":"INCLUDE generated\/output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE generated\/regions.ld\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t_etext = .;\n\t} > firmware_ram\n\n\t.rodata :\n\t{\n\t\t. = ALIGN(4);\n\t\t_frodata = .;\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.rodata1)\n\t\t_erodata = .;\n\t} > firmware_ram\n\n\t.data :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fdata = .;\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t\t_gp = ALIGN(16);\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t_edata = .;\n\t} > firmware_ram\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fbss = .;\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > sram\n}\n\nPROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);\n","old_contents":"INCLUDE generated\/output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE generated\/regions.ld\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t_etext = .;\n\t} > firmware_ram\n\n\t.rodata :\n\t{\n\t\t. = ALIGN(4);\n\t\t_frodata = .;\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.rodata1)\n\t\t_erodata = .;\n\t} > firmware_ram\n\n\t.data :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fdata = .;\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t\t_gp = ALIGN(16);\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t_edata = .;\n\t} > firmware_ram\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fbss = .;\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t\t. = ALIGN(8);\n\t\t_heapstart = .;\n\t} > firmware_ram\n}\n\nPROVIDE(_fstack = ORIGIN(firmware_ram) + LENGTH(firmware_ram) - 4);\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"82ef447e44c0d260f3dec85d5761fc33bfaf085e","subject":"[BSP] Update lpc176x GNU link script","message":"[BSP] Update lpc176x GNU link script\n","repos":"yongli3\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,igou\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,armink\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,zhaojuntao\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,yongli3\/rt-thread,AubrCool\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,igou\/rt-thread,wolfgangz2013\/rt-thread,nongxiaoming\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,ArdaFu\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,igou\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,igou\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,yongli3\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,weety\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread","old_file":"bsp\/lpc176x\/rtthread-lpc17xx.ld","new_file":"bsp\/lpc176x\/rtthread-lpc17xx.ld","new_contents":"\/*\n * linker script for LPC1768 (512kB Flash, 32kB + 32kB SRAM ) with GNU ld\n * bernard.xiong 2012-01-13\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000\n    DATA (rw) : ORIGIN = 0x10000000, LENGTH = 0x00008000\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.interrupt_vector))      \/* Startup code *\/\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        PROVIDE(__ctors_start__ = .);\n        \/* old GCC version uses .ctors *\/\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        \/* new GCC version uses .init_array *\/\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n\n        . = ALIGN(4);\n        _etext = .;\n    } > CODE = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > CODE\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >DATA\n\n\t.stack : \n\t{\n\t\t. = . + _system_stack_size;\n\t\t. = ALIGN(4);\n\t\t_estack = .;\n\t} >DATA\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;        \n        *(.bss.init)\n    } > DATA\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * linker script for LPC1768 (512kB Flash, 32kB + 32kB SRAM ) with GNU ld\n * bernard.xiong 2012-01-13\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000\n    DATA (rw) : ORIGIN = 0x10000000, LENGTH = 0x00008000\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.interrupt_vector))      \/* Startup code *\/\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        . = ALIGN(4);\n        _etext = .;\n    } > CODE = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > CODE\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >DATA\n\n\t.stack : \n\t{\n\t\t. = . + _system_stack_size;\n\t\t. = ALIGN(4);\n\t\t_estack = .;\n\t} >DATA\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;        \n        *(.bss.init)\n    } > DATA\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"06acd8b420c4015ab474f76d9f0542f3afc2f9cc","subject":"cpu\/esp8266: place freertos functions in IRAM","message":"cpu\/esp8266: place freertos functions in IRAM\n\nThe functions of the `esp*\/freetos` libraries must be placed in IRAM because they can be called when the IROM cache is disabled. While the functions implemented in `cpu\/esp8266\/freetos\/*.c` are already placed in IRAM, the functions implemented in `cpu\/esp_common\/freetos\/*.c` are not placed in IRAM. The reason for this is that the object files of these files are created in the `esp_freertos_common` directory, which is not included in the `esp.riot-os.ld` file because the library is named `esp_freertos_common`.","repos":"RIOT-OS\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,miri64\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,miri64\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,ant9000\/RIOT","old_file":"cpu\/esp8266\/ld\/esp8266.riot-os.ld","new_file":"cpu\/esp8266\/ld\/esp8266.riot-os.ld","new_contents":"\/**\n * This linker script is a combined and modified version of esp8266.ld and\n * esp8266.common.ld from ESP8266-RTOS-SDK.\n *\/\n\nMEMORY\n{\n  dport0_0_seg : org = 0x3FF00000, len = 0x10\n  dram0_0_seg  : org = 0x3FFE8000, len = 0x18000\n  iram1_0_seg  : org = 0x40100000, len = 0xC000\n  irom0_0_seg  : org = 0x40200010 + 0x10000, len = 0x80000 - 0x10 - 0x10000\n  rtc_seg      : org = 0x60001200, len = 0x200\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  \/* RTC memory holds user's data\/rodata *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .rtc.bss :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *(.rtc.bss)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    KEEP (*(SORT(.xfa.*)))\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    \/* TODO put only necessary .rodata to dram *\/\n    \/* *(.rodata .rodata.*) *\/\n    *libc.a:*.o(.rodata.* .rodata)\n    *core\/*(.rodata.* .rodata)\n    *cpu\/*(.rodata .rodata.*)\n    *libpp.a:(.rodata.* .rodata)\n    *liblog.a:(.rodata.* .rodata)\n\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    KEEP (*(SORT(.roxfa.*)))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  . = 0x3FFFFFF0;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    LONG(_text_start)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)   \/* 0x40100010 *\/\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)     \/* 0x40100020 *\/\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)  \/* 0x40100030 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)    \/* 0x40100050 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)  \/* 0x40100070 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.UserExceptionTrampoline.text)  \/* 0x40100090 *\/\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* normal code should be in irom0 *\/\n    \/*\n    *(.literal .text)\n    *core.a:*(.literal .text .literal.* .text.*)\n    *\/\n    *gdbstub\/*(.literal .text .literal.* .text.*)\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    \/* RIOT-OS compiled source files that use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1 .iram1.*)\n\n    \/* SDK libraries that expect their .text or .data sections to link to iram *\/\n    \/* TODO *libcore.a:(.bss .data .bss.* .data.* COMMON) *\/\n    *esp_idf_spi_flash\/spi_flash_raw.o(.literal .text .literal.* .text.*)\n    *esp_idf_esp8266\/ets_printf.o(.literal .text .literal.* .text.*)\n    \/*\n    *cpu.a:*.o(.literal .text .literal.* .text.*)\n    *\/\n    *core\/sched.o(.literal .text .literal.* .text.*)\n    *esp_wifi\/*(.literal .text .literal.* .text.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *freertos_common\/*(.literal .text .literal.* .text.*)\n    *periph\/*(.literal .text .literal.* .text.*)\n    *xtimer\/*(.literal .text .literal.* .text.*)\n\n    *libhal.a:clock.o(.literal .text .literal.* .text.*)\n    *libhal.a:int_asm--set_intclear.o(.literal .text .literal.* .text.*)\n    *libpp.a:esf_buf.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:rate_control.o(.literal .text .literal.* .text.*)\n    *libpp.a:trc.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_chip_v6_cal.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_sleep.o(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa\/*(.literal .text .literal.* .text.*)\n\n    \/* libgcc functions required for debugging have to be in IRAM *\/\n    *libgcc.a:unwind-dw2.o(.literal .text .literal.* .text.*)\n\n    \/* libgcc integer functions also need to be in .text *\/\n    \/* some are called before flash is mapped and also for performance) *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    *libgcc.a:*mulsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*divsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*fixsfsi.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    \/*\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memchr.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n    *\/\n\n    *enc28j60\/*(.literal .text .literal.* .text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    \/* RIOT-OS compiled code and RO data go into IROM by default *\/\n    *(.literal .text .literal.* .text.*)\n    *(.rodata .rodata.*)\n\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n    . = ALIGN(16);\n    __start_ksymatabesp_socket = .;\n    *(ksymatabesp_socket)\n    __stop_ksymatabesp_socket = .;\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","old_contents":"\/**\n * This linker script is a combined and modified version of esp8266.ld and\n * esp8266.common.ld from ESP8266-RTOS-SDK.\n *\/\n\nMEMORY\n{\n  dport0_0_seg : org = 0x3FF00000, len = 0x10\n  dram0_0_seg  : org = 0x3FFE8000, len = 0x18000\n  iram1_0_seg  : org = 0x40100000, len = 0xC000\n  irom0_0_seg  : org = 0x40200010 + 0x10000, len = 0x80000 - 0x10 - 0x10000\n  rtc_seg      : org = 0x60001200, len = 0x200\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  \/* RTC memory holds user's data\/rodata *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .rtc.bss :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *(.rtc.bss)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_seg\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    KEEP (*(SORT(.xfa.*)))\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    \/* TODO put only necessary .rodata to dram *\/\n    \/* *(.rodata .rodata.*) *\/\n    *libc.a:*.o(.rodata.* .rodata)\n    *core\/*(.rodata.* .rodata)\n    *cpu\/*(.rodata .rodata.*)\n    *libpp.a:(.rodata.* .rodata)\n    *liblog.a:(.rodata.* .rodata)\n\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    KEEP (*(SORT(.roxfa.*)))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\n  } >dram0_0_seg :dram0_0_bss_phdr\n\n  . = 0x3FFFFFF0;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .text : ALIGN(4) \/* IRAM *\/\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    LONG(_text_start)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)   \/* 0x40100010 *\/\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)     \/* 0x40100020 *\/\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)  \/* 0x40100030 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)    \/* 0x40100050 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)  \/* 0x40100070 *\/\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.UserExceptionTrampoline.text)  \/* 0x40100090 *\/\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n\n    \/* normal code should be in irom0 *\/\n    \/*\n    *(.literal .text)\n    *core.a:*(.literal .text .literal.* .text.*)\n    *\/\n    *gdbstub\/*(.literal .text .literal.* .text.*)\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    \/* RIOT-OS compiled source files that use the .iram1.* section names for IRAM\n       functions, etc. *\/\n    *(.iram1 .iram1.*)\n\n    \/* SDK libraries that expect their .text or .data sections to link to iram *\/\n    \/* TODO *libcore.a:(.bss .data .bss.* .data.* COMMON) *\/\n    *esp_idf_spi_flash\/spi_flash_raw.o(.literal .text .literal.* .text.*)\n    *esp_idf_esp8266\/ets_printf.o(.literal .text .literal.* .text.*)\n    \/*\n    *cpu.a:*.o(.literal .text .literal.* .text.*)\n    *\/\n    *core\/sched.o(.literal .text .literal.* .text.*)\n    *esp_wifi\/*(.literal .text .literal.* .text.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *periph\/*(.literal .text .literal.* .text.*)\n    *xtimer\/*(.literal .text .literal.* .text.*)\n\n    *libhal.a:clock.o(.literal .text .literal.* .text.*)\n    *libhal.a:int_asm--set_intclear.o(.literal .text .literal.* .text.*)\n    *libpp.a:esf_buf.o(.literal .text .literal.* .text.*)\n    *libpp.a:lmac.o(.literal .text .literal.* .text.*)\n    *libpp.a:pp.o(.literal .text .literal.* .text.*)\n    *libpp.a:rate_control.o(.literal .text .literal.* .text.*)\n    *libpp.a:trc.o(.literal .text .literal.* .text.*)\n    *libpp.a:wdev.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_chip_v6_cal.o(.literal .text .literal.* .text.*)\n    *libphy.a:phy_sleep.o(.literal .text .literal.* .text.*)\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa\/*(.literal .text .literal.* .text.*)\n\n    \/* libgcc functions required for debugging have to be in IRAM *\/\n    *libgcc.a:unwind-dw2.o(.literal .text .literal.* .text.*)\n\n    \/* libgcc integer functions also need to be in .text *\/\n    \/* some are called before flash is mapped and also for performance) *\/\n    *libgcc.a:*i3.o(.literal .text .literal.* .text.*)\n\n    *libgcc.a:*mulsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*divsf3.o(.literal .text .literal.* .text.*)\n    *libgcc.a:*fixsfsi.o(.literal .text .literal.* .text.*)\n\n    \/* libc also in IRAM *\/\n    \/*\n    *libc.a:*malloc.o(.literal .text .literal.* .text.*)\n    *libc.a:*mallocr.o(.literal .text .literal.* .text.*)\n    *libc.a:*freer.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcpy.o(.literal .text .literal.* .text.*)\n    *libc.a:*memchr.o(.literal .text .literal.* .text.*)\n    *libc.a:*memset.o(.literal .text .literal.* .text.*)\n    *libc.a:*memcmp.o(.literal .text .literal.* .text.*)\n    *libc.a:*memmove.o(.literal .text .literal.* .text.*)\n    *libc.a:*rand.o(.literal .text .literal.* .text.*)\n    *libc.a:*bzero.o(.literal .text .literal.* .text.*)\n    *libc.a:*lock.o(.literal .text .literal.* .text.*)\n\n    *libc.a:*printf.o(.literal .text .literal.* .text.*)\n    *libc.a:*findfp.o(.literal .text .literal.* .text.*)\n    *libc.a:*fputwc.o(.literal .text .literal.* .text.*)\n    *\/\n\n    *enc28j60\/*(.literal .text .literal.* .text.*)\n\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n\n    \/* RIOT-OS compiled code and RO data go into IROM by default *\/\n    *(.literal .text .literal.* .text.*)\n    *(.rodata .rodata.*)\n\n    \/* Anything explicitly marked as \"irom\" or \"irom0\" should go here *\/\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n    . = ALIGN(16);\n    __start_ksymatabesp_socket = .;\n    *(ksymatabesp_socket)\n    __stop_ksymatabesp_socket = .;\n\n    _irom0_text_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"18ce5f55bdecd1dfc3c2801e3f755f65f207170a","subject":"add more SRAM for app","message":"add more SRAM for app\n","repos":"maxml\/sample-apps,kaaproject\/sample-apps,kaaproject\/sample-apps,maxml\/sample-apps,kaaproject\/sample-apps,maxml\/sample-apps,kaaproject\/sample-apps,maxml\/sample-apps,kaaproject\/sample-apps,kaaproject\/sample-apps,maxml\/sample-apps,maxml\/sample-apps,kaaproject\/sample-apps,kaaproject\/sample-apps","old_file":"configurationdemo\/source\/cc32xx\/platform\/cc32xx\/app.ld","new_file":"configurationdemo\/source\/cc32xx\/platform\/cc32xx\/app.ld","new_contents":"\/*****************************************************************************\n* blinky.ld\n*\n* GCC Linker script for blinky application.\n*\n* Copyright (C) 2014 Texas Instruments Incorporated - http:\/\/www.ti.com\/ \n* \n* \n*  Redistribution and use in source and binary forms, with or without \n*  modification, are permitted provided that the following conditions \n*  are met:\n*\n*    Redistributions of source code must retain the above copyright \n*    notice, this list of conditions and the following disclaimer.\n*\n*    Redistributions in binary form must reproduce the above copyright\n*    notice, this list of conditions and the following disclaimer in the \n*    documentation and\/or other materials provided with the   \n*    distribution.\n*\n*    Neither the name of Texas Instruments Incorporated nor the names of\n*    its contributors may be used to endorse or promote products derived\n*    from this software without specific prior written permission.\n*\n*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \n*  \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \n*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \n*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \n*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \n*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \n*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*\n******************************************************************************\/\n\n\nHEAP_SIZE = 0x00010000;\n\nMEMORY\n{\n    SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 0x0003C000\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.intvecs))\n        *(.text*)\n        *(.rodata*)\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t. = ALIGN(8);\n        _etext = .;\n    } > SRAM\n\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } > SRAM\n\n    __init_data = .;\n\n    .data : AT(__init_data)\n    {\n        _data = .;\n        *(.data*)\n\t. = ALIGN (8);\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n    .heap :\n    {\n\t_heap = .;\n\t. = . + HEAP_SIZE;\n\t. = ALIGN(8);\n\t_eheap = .;\n\n    }\n}\n\n","old_contents":"\/*****************************************************************************\n* blinky.ld\n*\n* GCC Linker script for blinky application.\n*\n* Copyright (C) 2014 Texas Instruments Incorporated - http:\/\/www.ti.com\/ \n* \n* \n*  Redistribution and use in source and binary forms, with or without \n*  modification, are permitted provided that the following conditions \n*  are met:\n*\n*    Redistributions of source code must retain the above copyright \n*    notice, this list of conditions and the following disclaimer.\n*\n*    Redistributions in binary form must reproduce the above copyright\n*    notice, this list of conditions and the following disclaimer in the \n*    documentation and\/or other materials provided with the   \n*    distribution.\n*\n*    Neither the name of Texas Instruments Incorporated nor the names of\n*    its contributors may be used to endorse or promote products derived\n*    from this software without specific prior written permission.\n*\n*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \n*  \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \n*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \n*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \n*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \n*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \n*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*\n******************************************************************************\/\n\n\nHEAP_SIZE = 0x00010000;\n\nMEMORY\n{\n    SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 0x0002C000\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.intvecs))\n        *(.text*)\n        *(.rodata*)\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t. = ALIGN(8);\n        _etext = .;\n    } > SRAM\n\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } > SRAM\n\n    __init_data = .;\n\n    .data : AT(__init_data)\n    {\n        _data = .;\n        *(.data*)\n\t. = ALIGN (8);\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n    .heap :\n    {\n\t_heap = .;\n\t. = . + HEAP_SIZE;\n\t. = ALIGN(8);\n\t_eheap = .;\n\n    }\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a3c2812e37cd69e8b324b3bb9903bb22e9daa024","subject":"nios2: linker.ld: remove some assertions","message":"nios2: linker.ld: remove some assertions\n\nThese aren't valid in all circumstances; the reset vector in most cases\nneeds to be in ROM.\n\nChange-Id: I83df8762eecc53c99af92f3b0972dfbafac457fb\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"explora26\/zephyr,zephyriot\/zephyr,nashif\/zephyr,bigdinotech\/zephyr,galak\/zephyr,mirzak\/zephyr-os,pklazy\/zephyr,galak\/zephyr,fractalclone\/zephyr-riscv,mbolivar\/zephyr,GiulianoFranchetto\/zephyr,mirzak\/zephyr-os,nashif\/zephyr,zephyriot\/zephyr,rsalveti\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,sharronliu\/zephyr,bigdinotech\/zephyr,fractalclone\/zephyr-riscv,fbsder\/zephyr,finikorg\/zephyr,tidyjiang8\/zephyr-doc,ldts\/zephyr,erwango\/zephyr,galak\/zephyr,kraj\/zephyr,bigdinotech\/zephyr,GiulianoFranchetto\/zephyr,fbsder\/zephyr,sharronliu\/zephyr,finikorg\/zephyr,sharronliu\/zephyr,aceofall\/zephyr-iotos,runchip\/zephyr-cc3200,nashif\/zephyr,erwango\/zephyr,galak\/zephyr,tidyjiang8\/zephyr-doc,Vudentz\/zephyr,ldts\/zephyr,punitvara\/zephyr,rsalveti\/zephyr,bboozzoo\/zephyr,tidyjiang8\/zephyr-doc,bigdinotech\/zephyr,holtmann\/zephyr,rsalveti\/zephyr,holtmann\/zephyr,runchip\/zephyr-cc3220,holtmann\/zephyr,erwango\/zephyr,fbsder\/zephyr,aceofall\/zephyr-iotos,ldts\/zephyr,bboozzoo\/zephyr,runchip\/zephyr-cc3220,runchip\/zephyr-cc3220,nashif\/zephyr,runchip\/zephyr-cc3200,aceofall\/zephyr-iotos,finikorg\/zephyr,zephyrproject-rtos\/zephyr,kraj\/zephyr,explora26\/zephyr,fractalclone\/zephyr-riscv,runchip\/zephyr-cc3220,rsalveti\/zephyr,runchip\/zephyr-cc3220,explora26\/zephyr,mbolivar\/zephyr,zephyriot\/zephyr,Vudentz\/zephyr,tidyjiang8\/zephyr-doc,rsalveti\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,fractalclone\/zephyr-riscv,runchip\/zephyr-cc3200,punitvara\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,pklazy\/zephyr,erwango\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,holtmann\/zephyr,mbolivar\/zephyr,ldts\/zephyr,fractalclone\/zephyr-riscv,bboozzoo\/zephyr,bigdinotech\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,pklazy\/zephyr,sharronliu\/zephyr,punitvara\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,explora26\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,tidyjiang8\/zephyr-doc,bboozzoo\/zephyr,nashif\/zephyr,pklazy\/zephyr,mirzak\/zephyr-os,kraj\/zephyr,runchip\/zephyr-cc3200,holtmann\/zephyr,bboozzoo\/zephyr,mirzak\/zephyr-os,erwango\/zephyr,Vudentz\/zephyr,aceofall\/zephyr-iotos,finikorg\/zephyr,runchip\/zephyr-cc3200,sharronliu\/zephyr,mirzak\/zephyr-os,mbolivar\/zephyr,fbsder\/zephyr,aceofall\/zephyr-iotos,ldts\/zephyr,explora26\/zephyr,fbsder\/zephyr,zephyriot\/zephyr,pklazy\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/nios2\/linker.ld","new_file":"include\/arch\/nios2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specfic linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n}\n#endif\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        *(.reset.*)\n    } GROUP_LINK_IN(RESET)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#ifdef CONFIG_CPLUSPLUS\n    SECTION_PROLOGUE(_CTOR_SECTION_NAME, ,)\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __CTOR_LIST__ must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first elment of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT_BY_NAME(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(init_array, (OPTIONAL),)\n        {\n            . = ALIGN(4);\n            __init_array_start = .;\n            KEEP(*(SORT_BY_NAME(\".init_array*\")))\n            __init_array_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(devconfig, (OPTIONAL),)\n        {\n                __devconfig_start = .;\n                *(\".devconfig.*\")\n                KEEP(*(SORT_BY_NAME(\".devconfig*\")))\n                __devconfig_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * XXX any space between _RAM_ADDR and ALT_CPU_EXCEPTION_ADDR is lost,\n     * currently 0x20 bytes\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_AT_PROLOGUE(_EXCEPTION_SECTION_NAME,,, __data_rom_start)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            \/* FIXME these KEEP()s shouldn't be necessary *\/\n            KEEP(*(\".exception.entry.*\"))\n            KEEP(*(\".exception.other.*\"))\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n        *(.data)\n        *(\".data.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(initlevel, (OPTIONAL),)\n        {\n                DEVICE_INIT_SECTIONS()\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_list, (OPTIONAL),)\n        {\n                _k_task_list_start = .;\n                        *(._k_task_list.public.*)\n                        *(._k_task_list.private.*)\n                _k_task_list_idle_start = .;\n                        *(._k_task_list.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n                _k_task_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_ptr, (OPTIONAL),)\n        {\n                _k_task_ptr_start = .;\n                        *(._k_task_ptr.public.*)\n                        *(._k_task_ptr.private.*)\n                        *(._k_task_ptr.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n                _k_task_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_pipe_ptr, (OPTIONAL),)\n        {\n                _k_pipe_ptr_start = .;\n                        *(._k_pipe_ptr.public.*)\n                        *(._k_pipe_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n                _k_pipe_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_mem_map_ptr, (OPTIONAL),)\n        {\n                _k_mem_map_ptr_start = .;\n                        *(._k_mem_map_ptr.public.*)\n                        *(._k_mem_map_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n                _k_mem_map_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_event_list, (OPTIONAL),)\n        {\n                _k_event_list_start = .;\n                        *(._k_event_list.event.*)\n                KEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n                _k_event_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    __data_ram_end = .;\n\n    SECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    __bss_num_words = (__bss_end - __bss_start) >> 2;\n\n    GROUP_END(RAMABLE_REGION)\n\n    }\n\n#if CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <sections.h>\n\n#include <linker-defs.h>\n#include <linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specfic linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    }\n\n#else\n\nASSERT(_RESET_VECTOR == _RAM_ADDR, \"Reset vector not at beginning of RAM!\")\nASSERT(_EXC_VECTOR - _RESET_VECTOR == 0x20, \"Exception vector in wrong place?\")\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n}\n#endif\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        *(.reset.*)\n    } GROUP_LINK_IN(RESET)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#ifdef CONFIG_CPLUSPLUS\n    SECTION_PROLOGUE(_CTOR_SECTION_NAME, ,)\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __CTOR_LIST__ must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first elment of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT_BY_NAME(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(init_array, (OPTIONAL),)\n        {\n            . = ALIGN(4);\n            __init_array_start = .;\n            KEEP(*(SORT_BY_NAME(\".init_array*\")))\n            __init_array_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(devconfig, (OPTIONAL),)\n        {\n                __devconfig_start = .;\n                *(\".devconfig.*\")\n                KEEP(*(SORT_BY_NAME(\".devconfig*\")))\n                __devconfig_end = .;\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * XXX any space between _RAM_ADDR and ALT_CPU_EXCEPTION_ADDR is lost,\n     * currently 0x20 bytes\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_AT_PROLOGUE(_EXCEPTION_SECTION_NAME,,, __data_rom_start)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            \/* FIXME these KEEP()s shouldn't be necessary *\/\n            KEEP(*(\".exception.entry.*\"))\n            KEEP(*(\".exception.other.*\"))\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n        *(.data)\n        *(\".data.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(initlevel, (OPTIONAL),)\n        {\n                DEVICE_INIT_SECTIONS()\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_list, (OPTIONAL),)\n        {\n                _k_task_list_start = .;\n                        *(._k_task_list.public.*)\n                        *(._k_task_list.private.*)\n                _k_task_list_idle_start = .;\n                        *(._k_task_list.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n                _k_task_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_task_ptr, (OPTIONAL),)\n        {\n                _k_task_ptr_start = .;\n                        *(._k_task_ptr.public.*)\n                        *(._k_task_ptr.private.*)\n                        *(._k_task_ptr.idle.*)\n                KEEP(*(SORT_BY_NAME(\"._k_task_ptr*\")))\n                _k_task_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_pipe_ptr, (OPTIONAL),)\n        {\n                _k_pipe_ptr_start = .;\n                        *(._k_pipe_ptr.public.*)\n                        *(._k_pipe_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_pipe_ptr*\")))\n                _k_pipe_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_mem_map_ptr, (OPTIONAL),)\n        {\n                _k_mem_map_ptr_start = .;\n                        *(._k_mem_map_ptr.public.*)\n                        *(._k_mem_map_ptr.private.*)\n                KEEP(*(SORT_BY_NAME(\"._k_mem_map_ptr*\")))\n                _k_mem_map_ptr_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_k_event_list, (OPTIONAL),)\n        {\n                _k_event_list_start = .;\n                        *(._k_event_list.event.*)\n                KEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n                _k_event_list_end = .;\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    __data_ram_end = .;\n\n    SECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    __bss_num_words = (__bss_end - __bss_start) >> 2;\n\n    GROUP_END(RAMABLE_REGION)\n\n    }\n\n#if CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9c7e3353e5a7db5f7f5e511b0466949efd54b106","subject":"esp8266: Put lexerstr32.o into FlashROM.","message":"esp8266: Put lexerstr32.o into FlashROM.\n","repos":"mpalomer\/micropython,infinnovation\/micropython,ryannathans\/micropython,bvernoux\/micropython,jmarcelino\/pycom-micropython,toolmacher\/micropython,chrisdearman\/micropython,matthewelse\/micropython,matthewelse\/micropython,tobbad\/micropython,redbear\/micropython,swegener\/micropython,Peetz0r\/micropython-esp32,henriknelson\/micropython,puuu\/micropython,hosaka\/micropython,ryannathans\/micropython,adafruit\/circuitpython,toolmacher\/micropython,toolmacher\/micropython,praemdonck\/micropython,blazewicz\/micropython,MrSurly\/micropython,turbinenreiter\/micropython,hosaka\/micropython,deshipu\/micropython,pfalcon\/micropython,MrSurly\/micropython,MrSurly\/micropython,praemdonck\/micropython,bvernoux\/micropython,redbear\/micropython,mpalomer\/micropython,alex-robbins\/micropython,drrk\/micropython,trezor\/micropython,emfcamp\/micropython,puuu\/micropython,pramasoul\/micropython,tralamazza\/micropython,mpalomer\/micropython,pfalcon\/micropython,puuu\/micropython,dmazzella\/micropython,trezor\/micropython,tuc-osg\/micropython,selste\/micropython,dmazzella\/micropython,tobbad\/micropython,micropython\/micropython-esp32,ganshun666\/micropython,dinau\/micropython,tuc-osg\/micropython,toolmacher\/micropython,mhoffma\/micropython,pramasoul\/micropython,alex-march\/micropython,matthewelse\/micropython,micropython\/micropython-esp32,puuu\/micropython,dxxb\/micropython,redbear\/micropython,matthewelse\/micropython,chrisdearman\/micropython,misterdanb\/micropython,dmazzella\/micropython,HenrikSolver\/micropython,SHA2017-badge\/micropython-esp32,adafruit\/circuitpython,lowRISC\/micropython,dxxb\/micropython,kerneltask\/micropython,blazewicz\/micropython,adafruit\/circuitpython,alex-march\/micropython,infinnovation\/micropython,pramasoul\/micropython,puuu\/micropython,drrk\/micropython,tobbad\/micropython,torwag\/micropython,oopy\/micropython,henriknelson\/micropython,mhoffma\/micropython,oopy\/micropython,dinau\/micropython,pozetroninc\/micropython,MrSurly\/micropython,TDAbboud\/micropython,HenrikSolver\/micropython,hosaka\/micropython,selste\/micropython,cwyark\/micropython,pfalcon\/micropython,Timmenem\/micropython,micropython\/micropython-esp32,selste\/micropython,drrk\/micropython,tralamazza\/micropython,deshipu\/micropython,kerneltask\/micropython,emfcamp\/micropython,tuc-osg\/micropython,HenrikSolver\/micropython,alex-march\/micropython,MrSurly\/micropython-esp32,hosaka\/micropython,pramasoul\/micropython,TDAbboud\/micropython,dxxb\/micropython,alex-robbins\/micropython,swegener\/micropython,Peetz0r\/micropython-esp32,SHA2017-badge\/micropython-esp32,torwag\/micropython,praemdonck\/micropython,toolmacher\/micropython,deshipu\/micropython,alex-robbins\/micropython,adafruit\/micropython,TDAbboud\/micropython,cwyark\/micropython,mpalomer\/micropython,adafruit\/micropython,ryannathans\/micropython,MrSurly\/micropython-esp32,mhoffma\/micropython,alex-robbins\/micropython,torwag\/micropython,henriknelson\/micropython,drrk\/micropython,PappaPeppar\/micropython,AriZuu\/micropython,pozetroninc\/micropython,pozetroninc\/micropython,adafruit\/circuitpython,oopy\/micropython,turbinenreiter\/micropython,infinnovation\/micropython,PappaPeppar\/micropython,kerneltask\/micropython,praemdonck\/micropython,blazewicz\/micropython,deshipu\/micropython,hiway\/micropython,PappaPeppar\/micropython,Peetz0r\/micropython-esp32,ganshun666\/micropython,HenrikSolver\/micropython,TDAbboud\/micropython,turbinenreiter\/micropython,misterdanb\/micropython,jmarcelino\/pycom-micropython,turbinenreiter\/micropython,PappaPeppar\/micropython,tralamazza\/micropython,ganshun666\/micropython,pramasoul\/micropython,tralamazza\/micropython,AriZuu\/micropython,matthewelse\/micropython,Timmenem\/micropython,bvernoux\/micropython,henriknelson\/micropython,adafruit\/micropython,emfcamp\/micropython,dinau\/micropython,torwag\/micropython,misterdanb\/micropython,pozetroninc\/micropython,adafruit\/circuitpython,micropython\/micropython-esp32,chrisdearman\/micropython,lowRISC\/micropython,emfcamp\/micropython,lowRISC\/micropython,tobbad\/micropython,torwag\/micropython,selste\/micropython,jmarcelino\/pycom-micropython,cwyark\/micropython,SHA2017-badge\/micropython-esp32,AriZuu\/micropython,lowRISC\/micropython,infinnovation\/micropython,hiway\/micropython,Timmenem\/micropython,dinau\/micropython,trezor\/micropython,MrSurly\/micropython-esp32,hiway\/micropython,swegener\/micropython,ryannathans\/micropython,PappaPeppar\/micropython,redbear\/micropython,alex-robbins\/micropython,adafruit\/micropython,pfalcon\/micropython,hiway\/micropython,MrSurly\/micropython,tuc-osg\/micropython,blazewicz\/micropython,dinau\/micropython,bvernoux\/micropython,alex-march\/micropython,Peetz0r\/micropython-esp32,HenrikSolver\/micropython,deshipu\/micropython,turbinenreiter\/micropython,AriZuu\/micropython,hiway\/micropython,trezor\/micropython,oopy\/micropython,dmazzella\/micropython,pozetroninc\/micropython,ganshun666\/micropython,adafruit\/circuitpython,drrk\/micropython,bvernoux\/micropython,cwyark\/micropython,swegener\/micropython,tuc-osg\/micropython,mhoffma\/micropython,emfcamp\/micropython,SHA2017-badge\/micropython-esp32,jmarcelino\/pycom-micropython,Peetz0r\/micropython-esp32,MrSurly\/micropython-esp32,trezor\/micropython,selste\/micropython,redbear\/micropython,SHA2017-badge\/micropython-esp32,ganshun666\/micropython,tobbad\/micropython,oopy\/micropython,dxxb\/micropython,micropython\/micropython-esp32,adafruit\/micropython,lowRISC\/micropython,mhoffma\/micropython,praemdonck\/micropython,henriknelson\/micropython,pfalcon\/micropython,alex-march\/micropython,infinnovation\/micropython,kerneltask\/micropython,blazewicz\/micropython,Timmenem\/micropython,cwyark\/micropython,Timmenem\/micropython,misterdanb\/micropython,MrSurly\/micropython-esp32,jmarcelino\/pycom-micropython,kerneltask\/micropython,mpalomer\/micropython,AriZuu\/micropython,hosaka\/micropython,ryannathans\/micropython,dxxb\/micropython,misterdanb\/micropython,matthewelse\/micropython,chrisdearman\/micropython,swegener\/micropython,TDAbboud\/micropython,chrisdearman\/micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"1dd56ee29c3b56ea314a514c236f370b467c900e","subject":"Adjust the NRF52840-DK's RAM window to match that of latest Tock master.","message":"Adjust the NRF52840-DK's RAM window to match that of latest Tock master.\n","repos":"tock\/libtock-rs","old_file":"runtime\/layouts\/nrf52840.ld","new_file":"runtime\/layouts\/nrf52840.ld","new_contents":"\/* Layout for the nRF52840-DK, usable by the examples in this repository. *\/\n\nMEMORY {\n  FLASH (X) : ORIGIN = 0x00030000, LENGTH = 0x000D0000\n  RAM   (W) : ORIGIN = 0x20008000, LENGTH = 46K\n}\n\nTBF_HEADER_SIZE = 0x48;\nINCLUDE libtock_layout.ld\n","old_contents":"\/* Layout for the nRF52840-DK, usable by the examples in this repository. *\/\n\nMEMORY {\n  FLASH (X) : ORIGIN = 0x00030000, LENGTH = 0x000D0000\n  RAM   (W) : ORIGIN = 0x20004000, LENGTH = 62K\n}\n\nTBF_HEADER_SIZE = 0x48;\nINCLUDE libtock_layout.ld\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"c8211aa5c6a6135809790b77c0284ff58d4a6930","subject":"!27 [stm32] fix linkscript issue in stm32f411-atk-nano Merge pull request !27 from RT-Thread\/gitee_fix","message":"!27 [stm32] fix linkscript issue in stm32f411-atk-nano\nMerge pull request !27 from RT-Thread\/gitee_fix","repos":"geniusgogo\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,armink\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,armink\/rt-thread","old_file":"bsp\/stm32\/stm32f411-atk-nano\/board\/linker_scripts\/link.lds","new_file":"bsp\/stm32\/stm32f411-atk-nano\/board\/linker_scripts\/link.lds","new_contents":"\/*\n * linker script for STM32F4xx with GNU ld\n * bernard.xiong 2009-10-14\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256k \/* 256KB flash *\/\n    RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k \/* 128K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n\n        _etext = .;\n    } > ROM = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > ROM\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >RAM\n\n    .stack : \n    {\n        . = ALIGN(4);\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >RAM\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > RAM\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * linker script for STM32F4xx with GNU ld\n * bernard.xiong 2009-10-14\n *\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256 \/* 256KB flash *\/\n    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  128k \/* 128K sram *\/\n}\nENTRY(Reset_Handler)\n_system_stack_size = 0x200;\n\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _stext = .;\n        KEEP(*(.isr_vector))            \/* Startup code *\/\n\n        . = ALIGN(4);\n        *(.text)                        \/* remaining code *\/\n        *(.text.*)                      \/* remaining code *\/\n        *(.rodata)                      \/* read-only data (constants) *\/\n        *(.rodata*)\n        *(.glue_7)\n        *(.glue_7t)\n        *(.gnu.linkonce.t*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n\n        \/* section information for initial. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n\n        . = ALIGN(4);\n\n        PROVIDE(__ctors_start__ = .);\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        PROVIDE(__ctors_end__ = .);\n\n        . = ALIGN(4);\n\n        _etext = .;\n    } > ROM = 0\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > ROM\n    __exidx_end = .;\n\n    \/* .data section which is used for initialized data *\/\n\n    .data : AT (_sidata)\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sdata = . ;\n\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _edata = . ;\n    } >RAM\n\n    .stack : \n    {\n        . = ALIGN(4);\n        _sstack = .;\n        . = . + _system_stack_size;\n        . = ALIGN(4);\n        _estack = .;\n    } >RAM\n\n    __bss_start = .;\n    .bss :\n    {\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _sbss = .;\n\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        \/* This is used by the startup in order to initialize the .bss secion *\/\n        _ebss = . ;\n        \n        *(.bss.init)\n    } > RAM\n    __bss_end = .;\n\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"335a44afc925d21e621390e9a76ee21902d15f5a","subject":"ld: new riscv sections","message":"ld: new riscv sections\n\nThe RISC-V compiler likes to emit more sections, and if we don't include\nthem in .text and .bss then they get created as their own ELF sections\nand elf2tab doesn't handle that super well.\n","repos":"tock\/libtock-c,tock\/libtock-c,tock\/libtock-c","old_file":"userland_generic.ld","new_file":"userland_generic.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        *(.srodata*) \/* for RISC-V *\/\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to\n\t\t * mark the first address in the SRAM memory. Since ELF files do\n\t\t * not really need to specify this address as they only care about\n\t\t * loading into flash, we need to manually mark this address for\n\t\t * elf2tab. elf2tab will use it to add a fixed address header in the\n\t\t * TBF header if needed.\n\t\t *\/\n\t    _sram_origin = .;\n\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        KEEP(*(.sbss*)) \/* for RISC-V *\/\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: On platforms where apps are position-independent and relocatable, the\n * FLASH address here acts as a sentinel value for relocation fixup routines.\n * The application loader will select the actual location in flash where the app\n * is placed. On platforms where apps are compiled for fixed addresses, these\n * addresses will be changed automatically before the linking step.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n    \/* Section for just the app crt0 header.\n     * This must be first so that the app can find it.\n     *\/\n    .crt0_header :\n    {\n        \/**\n         * Populate the header expected by `crt0`:\n         *\n         *  struct hdr {\n         *    uint32_t got_sym_start;\n         *    uint32_t got_start;\n         *    uint32_t got_size;\n         *    uint32_t data_sym_start;\n         *    uint32_t data_start;\n         *    uint32_t data_size;\n         *    uint32_t bss_start;\n         *    uint32_t bss_size;\n         *    uint32_t reldata_start;\n         *    uint32_t stack_size;\n         *  };\n         *\/\n        \/* Offset of GOT symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.got) - ORIGIN(FLASH));\n        \/* Offset of where the GOT section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_got - ORIGIN(SRAM));\n        \/* Size of GOT section. *\/\n        LONG(SIZEOF(.got));\n        \/* Offset of data symbols in flash from the start of the application\n         * binary. *\/\n        LONG(LOADADDR(.data) - ORIGIN(FLASH));\n        \/* Offset of where the data section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_data - ORIGIN(SRAM));\n        \/* Size of data section. *\/\n        LONG(SIZEOF(.data));\n        \/* Offset of where the BSS section will be placed in memory from the\n         * beginning of the app's assigned memory. *\/\n        LONG(_bss - ORIGIN(SRAM));\n        \/* Size of BSS section *\/\n        LONG(SIZEOF(.bss));\n        \/* First address offset after program flash, where elf2tab places\n         * .rel.data section *\/\n        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));\n        \/* The size of the stack requested by this application *\/\n        LONG(STACK_SIZE);\n    } > FLASH =0xFF\n\n    \/* App state section. Used for persistent app data.\n     * We put this first so that if the app code changes but the persistent\n     * data doesn't, the app_state can be preserved.\n     *\/\n    .wfr.app_state :\n    {\n        KEEP (*(.app_state))\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Text section, Code! *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _text = .;\n        KEEP (*(.start))\n        *(.text*)\n        *(.rodata*)\n        KEEP (*(.syscalls))\n        _etext = .;\n        *(.ARM.extab*)\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n    } > FLASH =0xFF\n\n    \/* Need to reserve room for the stack in the linker file. This makes the\n     * _got addresses used by the compiler match what they will be when the\n     * app is loaded into memory. This is not necessary for full PIC supported\n     * platforms (like Cortex-M), but is needed when an app is compiled for a\n     * fixed address.\n     *\/\n    .stack :\n    {\n        \/* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to\n\t\t * mark the first address in the SRAM memory. Since ELF files do\n\t\t * not really need to specify this address as they only care about\n\t\t * loading into flash, we need to manually mark this address for\n\t\t * elf2tab. elf2tab will use it to add a fixed address header in the\n\t\t * TBF header if needed.\n\t\t *\/\n\t    _sram_origin = .;\n\n        \/* Be conservative about our alignment for the stack. Different\n         * architectures require different values (8 for ARM, 16 for RISC-V),\n         * so we choose the largest value. In practice, this likely will not\n         * matter since the start of SRAM is unlikely to be at a very peculiar\n         * address.\n         *\/\n        . = ALIGN(16);\n        _stack = .;\n        . = _stack + STACK_SIZE;\n        . = ALIGN(16);\n    } > SRAM\n\n\n    \/* Global Offset Table *\/\n    .got :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _got = .;\n        *(.got*)\n        *(.got.plt*)\n        . = ALIGN(4);\n    } > SRAM AT > FLASH\n\n    \/* Data section, static initialized variables\n     *  Note: This is placed in Flash after the text section, but needs to be\n     *  moved to SRAM at runtime\n     *\/\n    .data :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _data = .;\n        KEEP(*(.data*))\n        \/* Include the \"small data\" in the data section. Otherwise it will be\n         * dropped when the TBF is created.\n         *\/\n        KEEP(*(.sdata*))\n        . = ALIGN(4); \/* Make sure we're word-aligned at the end of flash *\/\n    } > SRAM AT > FLASH\n\n    \/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        . = ALIGN(4); \/* Make sure we're word-aligned here *\/\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        . = ALIGN(4);\n    } > SRAM\n\n    \/* End of flash. *\/\n    .endflash :\n    {\n    } > FLASH\n\n    \/* ARM Exception support\n     *\n     * This contains compiler-generated support for unwinding the stack,\n     * consisting of key-value pairs of function addresses and information on\n     * how to unwind stack frames.\n     * https:\/\/wiki-archive.linaro.org\/KenWerner\/Sandbox\/libunwind\n     * (See also https:\/\/github.com\/tock\/libtock-c\/issues\/48)\n     *\n     *\n     * .ARM.exidx is sorted, so has to go in its own output section.\n     *\n     * __NOTE__: It's at the end because we currently don't actually serialize\n     * it to the binary in elf2tab. If it was before the RAM sections, it would\n     * through off our calculations of the header.\n     *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n}\n\nASSERT(_got <= _bss, \"\nThe GOT section must be before the BSS section for crt0 setup to be correct.\");\nASSERT(_data <= _bss, \"\nThe data section must be before the BSS section for crt0 setup to be correct.\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1a9de2e1bd68ba76c3188c9413dd50ff9f37be76","subject":"[bsp][asm9260t] Fix link script ENTRY symbol.","message":"[bsp][asm9260t] Fix link script ENTRY symbol.\n","repos":"armink\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,wolfgangz2013\/rt-thread,yongli3\/rt-thread,ArdaFu\/rt-thread,yongli3\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,igou\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,igou\/rt-thread,RT-Thread\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,igou\/rt-thread,nongxiaoming\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,FlyLu\/rt-thread,wolfgangz2013\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,igou\/rt-thread,yongli3\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,zhaojuntao\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,igou\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,geniusgogo\/rt-thread,AubrCool\/rt-thread,nongxiaoming\/rt-thread,igou\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread,AubrCool\/rt-thread,yongli3\/rt-thread,weety\/rt-thread,armink\/rt-thread","old_file":"bsp\/asm9260t\/link_scripts\/sdram.ld","new_file":"bsp\/asm9260t\/link_scripts\/sdram.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(start)\nSECTIONS\n{\n    . = 0x20000000;\n\n    . = ALIGN(4);\n    .text : \n    {\n        *(.init)\n        *(.text)\n        *(.gnu.linkonce.t*)\n        \n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);   \n\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n    }\n\n    . = ALIGN(4);\n    .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    }\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    }\n\n    . = ALIGN(4);\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n    }\n\n    . = ALIGN(4);\n    .nobss : { *(.nobss) }\n    \n    . = ALIGN(4);\n    __bss_start__ = .;\n    .bss : { *(.bss)}\n    __bss_end__ = .;\n\n    \/* stabs debugging sections. *\/\n    .stab 0 : { *(.stab) }\n    .stabstr 0 : { *(.stabstr) }\n    .stab.excl 0 : { *(.stab.excl) }\n    .stab.exclstr 0 : { *(.stab.exclstr) }\n    .stab.index 0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment 0 : { *(.comment) }\n    .debug_abbrev 0 : { *(.debug_abbrev) }\n    .debug_info 0 : { *(.debug_info) }\n    .debug_line 0 : { *(.debug_line) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    .debug_aranges 0 : { *(.debug_aranges) }\n\n    _end = .;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(entry)\nSECTIONS\n{\n    . = 0x20000000;\n\n    . = ALIGN(4);\n    .text : \n    {\n        *(.init)\n        *(.text)\n        *(.gnu.linkonce.t*)\n        \n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);   \n\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n        \/* section information for modules *\/\n        . = ALIGN(4);\n        __rtmsymtab_start = .;\n        KEEP(*(RTMSymTab))\n        __rtmsymtab_end = .;\n    }\n\n    . = ALIGN(4);\n    .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }\n\n    . = ALIGN(4);\n    .ctors :\n    {\n        PROVIDE(__ctors_start__ = .);\n        KEEP(*(SORT(.ctors.*)))\n        KEEP(*(.ctors))\n        PROVIDE(__ctors_end__ = .);\n    }\n\n    .dtors :\n    {\n        PROVIDE(__dtors_start__ = .);\n        KEEP(*(SORT(.dtors.*)))\n        KEEP(*(.dtors))\n        PROVIDE(__dtors_end__ = .);\n    }\n\n    . = ALIGN(4);\n    .data :\n    {\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d*)\n    }\n\n    . = ALIGN(4);\n    .nobss : { *(.nobss) }\n    \n    . = ALIGN(4);\n    __bss_start__ = .;\n    .bss : { *(.bss)}\n    __bss_end__ = .;\n\n    \/* stabs debugging sections. *\/\n    .stab 0 : { *(.stab) }\n    .stabstr 0 : { *(.stabstr) }\n    .stab.excl 0 : { *(.stab.excl) }\n    .stab.exclstr 0 : { *(.stab.exclstr) }\n    .stab.index 0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment 0 : { *(.comment) }\n    .debug_abbrev 0 : { *(.debug_abbrev) }\n    .debug_info 0 : { *(.debug_info) }\n    .debug_line 0 : { *(.debug_line) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    .debug_aranges 0 : { *(.debug_aranges) }\n\n    _end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d1c8ca64be5d04d85f1ef5bf2291353caac47e40","subject":"Set stack limit to end of heap","message":"Set stack limit to end of heap\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/src\/gcc_arm_flash.ld","new_file":"ARM\/src\/gcc_arm_flash.ld","new_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t__isr_vector = .;\n\t\t\/* At addr zero is the stack pointer *\/\n\t\t\/*LONG(__StackTop);*\/\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect*))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\t\/* in case security config is not defined, fill in default *\/\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xfffffffe);\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : ALIGN(4)\n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\/*\t\t. = ALIGN(4);*\/\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\/*\t\t. = ALIGN(4);*\/\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n\n   \t\/* calculate size to take full range from .data to .bss in case other data sections\n   \t   were inserted in between from outside of this file *\/\n   \t__data_size__ = __bss_start__ - __data_start__ ; \/* SIZEOF(.data);*\/\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __HeapLimit + 4;\/*__StackTop - SIZEOF(.stack_dummy);*\/\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","old_contents":"\/*--------------------------------------------------------------------------\nFile   : gcc_arm.ld\n\nAuthor : Hoang Nguyen Hoan          Jan. 19, 2012\n\nDesc   : Generic common linker script sections.  General sections\n         definitions for of GCC compiler.  This file is to be inlcuded\n\t \tin the device specific linker script.\n\n\t \tRequire memory region name definition as follow\n\t\t \n\t        FLASH : Read only code memory region\n\t        RAM : Ram memory region for data  \n\nCopyright (c) 2012, I-SYST, all rights reserved\n\nPermission to use, copy, modify, and distribute this software for any purpose\nwith or without fee is hereby granted, provided that the above copyright\nnotice and this permission notice appear in all copies, and none of the\nnames : I-SYST or its contributors may be used to endorse or\npromote products derived from this software without specific prior written\npermission.\n\nFor info or contributing contact : hnhoan at i-syst dot com\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n----------------------------------------------------------------------------\nModified by        \tDate        \tDescription\nHoan\t\t\t\tJuly 3, 2015\tAdd Freescale Flash security config area\t\n----------------------------------------------------------------------------*\/\n\n\/* \nRequire custom section definitions\n   .intvect - ARM interrupt vector\n   .Version - Firmware version data \n*\/\n\nENTRY(ResetEntry)\n\n\n__CheckSum = 0;\n\nSECTIONS {\n\n    \/* Require ARM vectors located at begining of FLASH region at address 0*\/\n\t\/* Reseve 1K for the vector *\/\n\t.ivector : ALIGN(4)\n\t{\n\t\t__text_start__ = .;\n\t\t__isr_vector = .;\n\t\t\/* At addr zero is the stack pointer *\/\n\t\t\/*LONG(__StackTop);*\/\n\n\t\t\/* interrupt vector *\/\n\t\tKEEP(*(.intvect*))\n\t} > FLASH \n\t\n\t\/* This is where the firmware informaton is stored. Usefull for bootloader *\/\n\t.Version : ALIGN(4)\n\t{\n\t\tKEEP(*(.Version))\n\t\tLONG(__CheckSum);\n\t\tFILL(0xff)  \/* fill unsused area to have consistant checksum *\/\n\t\t. = 0x400 - SIZEOF(.ivector);\/* - SIZEOF(.Version);*\/\n\t} > FLASH\n\t\t\n\t\/* Require Frescale Flash security config *\/\n\t\/* Auto fill with 0xFF is section not present in code *\/\n\t.FSec : ALIGN(4)\n\t{\n\t\tKEEP(*(.fseccfg))\n\t\t\/* in case security config is not defined, fill in default *\/\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xffffffff);\n\t\tLONG(0xfffffffe);\n\t} > FLASH\n\t\n\t.AppStart : ALIGN(4)\n\t{\n\t\t\/* Application Entry point starts here.  Normaly is the ResetEntry function *\/ \n\t\tKEEP(*(.AppStart))\n\t} > FLASH\n\t\n\t\/* Code region starts here *\/\n\t.text : ALIGN(4)\n\t{\t\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\t\t\n\t\t\/* .ctors *\/\n\t\tKEEP(*crtbegin.o (.ctors))\n\t\tKEEP(*crtbegin?.o(.ctors))\n\t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n\t\tKEEP(*(SORT(.ctors.*)))\n\t\tKEEP(*crtend.o (.ctors))\n\n\t\t\/* .dtors *\/\n \t\tKEEP(*crtbegin.o(.dtors))\n \t\tKEEP(*crtbegin?.o(.dtors))\n \t\tKEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n \t\tKEEP(*(SORT(.dtors.*)))\n \t\tKEEP(*crtend.o (.dtors))\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .rodata1)\n\t\t*(.gnu.linkonce.r.*)\n\t} > FLASH\n    \n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\tPROVIDE (__exidx_start = .);\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\tPROVIDE (__exidx_end = .);\n\n\t.eh_frame_hdr : ALIGN(4)\n\t{ \n\t\t*(.eh_frame_hdr) \n\t} > FLASH\n\t\n\t.eh_frame : ONLY_IF_RO \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.eh_frame)\n\t} > FLASH\n\t\n\t.gcc_except_table : ONLY_IF_RO \n\t{ \n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > FLASH\n\t\n\t__text_end__ = .;\n\t\n\t.eh_frame : ONLY_IF_RW \n\t{ \n\/*\t\t. = ALIGN(4);*\/\n\t\t*(.eh_frame) \n\t} > RAM\n\t\n\t.gcc_except_table : ONLY_IF_RW \n\t{ \n\/*\t\t. = ALIGN(4);*\/\n\t\t*(.gcc_except_table .gcc_except_table.*) \n\t} > RAM\n\t\n\t\t\n\t.data : ALIGN(4)\n\t{\n\t\t\/* preinit data *\/\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE (__fini_array_end = .);\n\n\t\t. = ALIGN(4);        \n\n\t\t*(vtable)\n\t\t*(.data*)\n\t\t*(.fastrun*)\n\n\t\t*(.jcr)\n\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM AT > FLASH\n\t\n\t__data_start__ = ADDR(.data);\n   \t__data_loc__ = LOADADDR(.data);\n\n   \t\/* calculate size to take full range from .data to .bss in case other data sections\n   \t   were inserted in between from outside of this file *\/\n   \t__data_size__ = __bss_start__ - __data_start__ ; \/* SIZEOF(.data);*\/\n\t\n\t.bss : ALIGN(4)\n\t{\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n      \t*(.gnu.linkonce.b.*)\n\t\t__bss_end__ = .;\n\t\tPROVIDE(end = .);\t\t              \n\t} > RAM\n        __bss_size__ = SIZEOF(.bss);\n\t\n\t.heap : ALIGN(4)\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t_pvHeapStart = .;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy : ALIGN(4)\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"29ce72447c00965c13b323944b6334417abd50cc","subject":"Linker script for FC-Boot applications","message":"Linker script for FC-Boot applications\n","repos":"poe\/fadecandy,Jorgen-VikingGod\/fadecandy,adam-back\/fadecandy,piers7\/fadecandy,lincomatic\/fadecandy,adam-back\/fadecandy,fragmede\/fadecandy,poe\/fadecandy,scanlime\/fadecandy,adam-back\/fadecandy,nomis52\/fadecandy,nomis52\/fadecandy,poe\/fadecandy,PimentNoir\/fadecandy,Protoneer\/fadecandy,poe\/fadecandy,poe\/fadecandy,Jorgen-VikingGod\/fadecandy,fragmede\/fadecandy,hakan42\/fadecandy,scanlime\/fadecandy,pixelmatix\/fadecandy,adam-back\/fadecandy,Jorgen-VikingGod\/fadecandy,hakan42\/fadecandy,piers7\/fadecandy,hakan42\/fadecandy,jsestrich\/fadecandy,PimentNoir\/fadecandy,poe\/fadecandy,poe\/fadecandy,adam-back\/fadecandy,nomis52\/fadecandy,Protoneer\/fadecandy,jsestrich\/fadecandy,poe\/fadecandy,PimentNoir\/fadecandy,nomis52\/fadecandy,fragmede\/fadecandy,PimentNoir\/fadecandy,lincomatic\/fadecandy,Protoneer\/fadecandy,lincomatic\/fadecandy,pixelmatix\/fadecandy,scanlime\/fadecandy,nomis52\/fadecandy,scanlime\/fadecandy,nomis52\/fadecandy,pixelmatix\/fadecandy,lincomatic\/fadecandy,fragmede\/fadecandy,fragmede\/fadecandy,jsestrich\/fadecandy,nomis52\/fadecandy,piers7\/fadecandy,PimentNoir\/fadecandy,hakan42\/fadecandy,Protoneer\/fadecandy,lincomatic\/fadecandy,scanlime\/fadecandy,Protoneer\/fadecandy,pixelmatix\/fadecandy,fragmede\/fadecandy,hakan42\/fadecandy,lincomatic\/fadecandy,pixelmatix\/fadecandy,piers7\/fadecandy,scanlime\/fadecandy,jsestrich\/fadecandy,lincomatic\/fadecandy,jsestrich\/fadecandy,nomis52\/fadecandy,fragmede\/fadecandy,Jorgen-VikingGod\/fadecandy,lincomatic\/fadecandy,fragmede\/fadecandy,Jorgen-VikingGod\/fadecandy,piers7\/fadecandy,PimentNoir\/fadecandy","old_file":"firmware\/fcb-app.ld","new_file":"firmware\/fcb-app.ld","new_contents":"\/* Linker script for application firmware loaded by FC-Boot.\n * Originally based on:\n *\n * Teensyduino Core Library\n * http:\/\/www.pjrc.com\/teensy\/\n * Copyright (c) 2013 PJRC.COM, LLC.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * 1. The above copyright notice and this permission notice shall be \n * included in all copies or substantial portions of the Software.\n *\n * 2. If the Software is incorporated into a build system that allows \n * selection among a list of target devices, then similar target\n * devices manufactured by PJRC.COM must be included in the list of\n * target devices and selectable in the same manner.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\/\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x00001000, LENGTH = 124K\n    RAM  (rwx) : ORIGIN = 0x1FFFE000, LENGTH = 16K\n}\n\n\nSECTIONS\n{\n    .text : {\n        . = 0;\n        KEEP(*(.vectors))\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n    } > FLASH = 0xFF\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > FLASH\n    _etext = .;\n\n    .usbdescriptortable (NOLOAD) : {\n        \/* . = ORIGIN(RAM); *\/\n        . = ALIGN(512);\n        *(.usbdescriptortable*)\n    } > RAM\n\n    .dmabuffers (NOLOAD) : {\n        . = ALIGN(4);\n        *(.dmabuffers*)\n    } > RAM\n\n    .usbbuffers (NOLOAD) : {\n        . = ALIGN(4);\n        *(.usbbuffers*)\n    } > RAM\n\n    .data : AT (_etext) {\n        . = ALIGN(4);\n        _sdata = .; \n        *(.data*)\n        . = ALIGN(4);\n        _edata = .; \n    } > RAM\n\n    .noinit (NOLOAD) : {\n        *(.noinit*)\n    } > RAM\n\n    .bss : {\n        . = ALIGN(4);\n        _sbss = .; \n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n        __bss_end = .;\n    } > RAM\n\n    _estack = ORIGIN(RAM) + LENGTH(RAM) - 4;\n    boot_token = _estack;\n}\n\n\n","old_contents":"\/* Teensyduino Core Library\n * http:\/\/www.pjrc.com\/teensy\/\n * Copyright (c) 2013 PJRC.COM, LLC.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and\/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * 1. The above copyright notice and this permission notice shall be \n * included in all copies or substantial portions of the Software.\n *\n * 2. If the Software is incorporated into a build system that allows \n * selection among a list of target devices, then similar target\n * devices manufactured by PJRC.COM must be included in the list of\n * target devices and selectable in the same manner.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *\/\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K\n    RAM  (rwx) : ORIGIN = 0x1FFFE000, LENGTH = 16K\n}\n\n\nSECTIONS\n{\n    .text : {\n        . = 0;\n        KEEP(*(.vectors))\n        *(.startup*)\n        \/* TODO: does linker detect startup overflow onto flashconfig? *\/\n        . = 0x400;\n        KEEP(*(.flashconfig*))\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n    } > FLASH = 0xFF\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > FLASH\n    _etext = .;\n\n    .usbdescriptortable (NOLOAD) : {\n        \/* . = ORIGIN(RAM); *\/\n        . = ALIGN(512);\n        *(.usbdescriptortable*)\n    } > RAM\n\n    .dmabuffers (NOLOAD) : {\n        . = ALIGN(4);\n        *(.dmabuffers*)\n    } > RAM\n\n    .usbbuffers (NOLOAD) : {\n        . = ALIGN(4);\n        *(.usbbuffers*)\n    } > RAM\n\n    .data : AT (_etext) {\n        . = ALIGN(4);\n        _sdata = .; \n        *(.data*)\n        . = ALIGN(4);\n        _edata = .; \n    } > RAM\n\n    .noinit (NOLOAD) : {\n        *(.noinit*)\n    } > RAM\n\n    .bss : {\n        . = ALIGN(4);\n        _sbss = .; \n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n        __bss_end = .;\n    } > RAM\n\n    _estack = ORIGIN(RAM) + LENGTH(RAM);\n}\n\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"dcd29b5700f2e30b2060ab9dbd0d369714a44857","subject":"Debugging is for chumps","message":"Debugging is for chumps\n","repos":"richo\/zinc,richo\/zinc,richo\/zinc,richo\/zinc,richo\/zinc","old_file":"src\/hal\/layout_common.ld","new_file":"src\/hal\/layout_common.ld","new_contents":"\/* TODO(farcaller): layout_common isn't actually common. k20 keeps own copy *\/\n__aeabi_unwind_cpp_pr0 = abort;\n__aeabi_unwind_cpp_pr1 = abort;\n__aeabi_unwind_cpp_pr2 = abort;\n__exidx_start          = abort;\n__exidx_end            = abort;\n\n__aeabi_memclr4 = __aeabi_memclr;\n\nSECTIONS\n{\n    .vector : ALIGN(4)\n    {\n        FILL(0xff)\n\n        KEEP(*(.isr_vector))\n        KEEP(*(.isr_vector_nvic))\n    } > vectors\n\n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        *(.text*)\n        *(.rodata .rodata.*)\n    } > rom\n\n    .data : ALIGN(4)\n    {\n        _data = .;\n\n        *(SORT_BY_ALIGNMENT(.data*))\n        . = ALIGN(4);\n\n        _edata = .;\n    } > ram AT>rom = 0xff\n\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n\n        _ebss = .;\n\n        . += 4;\n\n        __STACK_LIMIT = .;\n\n        . += 4;\n\n        _eglobals = .;\n    } > ram\n\n    \/DISCARD\/ :\n    {\n        *(.glue_7*)  \/* arm-thumb interworking *\/\n        *(.v4_bx)  \/* ARMv4 interworking fixup for missing BX *\/\n        *(.vfp11_veneer)  \/* VFP11 bugfixes s.a. http:\/\/sourceware.org\/ml\/binutils\/2006-12\/msg00196.html *\/\n        *(.iplt .igot.plt)  \/* STT_GNU_IFUNC symbols *\/\n        *(.rel.*)  \/* dynamic relocations *\/\n        *(.ARM.exidx*) \/* index entries for section unwinding *\/\n        *(.ARM.extab*) \/* exception unwinding information *\/\n    }\n}\n","old_contents":"\/* TODO(farcaller): layout_common isn't actually common. k20 keeps own copy *\/\n__aeabi_unwind_cpp_pr0 = abort;\n__aeabi_unwind_cpp_pr1 = abort;\n__aeabi_unwind_cpp_pr2 = abort;\n__exidx_start          = abort;\n__exidx_end            = abort;\n\n__aeabi_memclr4 = __aeabi_memclr;\n\nSECTIONS\n{\n    .vector : ALIGN(4)\n    {\n        FILL(0xff)\n\n        KEEP(*(.isr_vector))\n        KEEP(*(.isr_vector_nvic))\n    } > vectors\n\n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        *(.text*)\n        *(.rodata .rodata.*)\n    } > rom\n\n    .data : ALIGN(4)\n    {\n        _data = .;\n\n        *(SORT_BY_ALIGNMENT(.data*))\n        . = ALIGN(4);\n\n        _edata = .;\n    } > ram AT>rom = 0xff\n\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n\n        _ebss = .;\n\n        . += 4;\n\n        __STACK_LIMIT = .;\n\n        . += 4;\n\n        _eglobals = .;\n    } > ram\n\n    \/DISCARD\/ :\n    {\n        *(.glue_7*)  \/* arm-thumb interworking *\/\n        *(.v4_bx)  \/* ARMv4 interworking fixup for missing BX *\/\n        *(.vfp11_veneer)  \/* VFP11 bugfixes s.a. http:\/\/sourceware.org\/ml\/binutils\/2006-12\/msg00196.html *\/\n        *(.iplt .igot.plt)  \/* STT_GNU_IFUNC symbols *\/\n        *(.rel.*)  \/* dynamic relocations *\/\n        *(.ARM.exidx*) \/* index entries for section unwinding *\/\n        *(.ARM.extab*) \/* exception unwinding information *\/\n        *(.debug_gdb_scripts)\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ca520700eeecd2aaf1e8a68d5c95e468d8679507","subject":"configurable flash & ram sizes","message":"configurable flash & ram sizes","repos":"gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins","old_file":"ilg.gnuarmeclipse.templates.st\/templates\/stm32f10x_exe_c_project\/ldscripts\/mem.ld","new_file":"ilg.gnuarmeclipse.templates.st\/templates\/stm32f10x_exe_c_project\/ldscripts\/mem.ld","new_contents":"\/* Linker script to configure memory regions. \n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = $(flashSize)K\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = $(ramSize)K\n}\n","old_contents":"\/* Linker script to configure memory regions. \n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 20K\n}\n","returncode":0,"stderr":"","license":"epl-1.0","lang":"Linker Script"}
{"commit":"f2d3810f3ac6195583526ded638548979474dddb","subject":"removed linker script, not XPD specific","message":"removed linker script, not XPD specific\n","repos":"IntergatedCircuits\/STM32_XPD,IntergatedCircuits\/STM32_XPD","old_file":"Projects\/STM32F4Discovery\/ld\/STM32F407VG_FLASH.ld","new_file":"Projects\/STM32F4Discovery\/ld\/STM32F407VG_FLASH.ld","new_contents":"","old_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F407VG Device with\n**                1024KByte FLASH, 128KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. This file may only be built (assembled or compiled and linked)\n**  using the Atollic TrueSTUDIO(R) product. The use of this file together\n**  with other tools than Atollic TrueSTUDIO(R) is not permitted.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x2001FFFF;    \/* end of RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\nCCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  _siccmram = LOADADDR(.ccmram);\n\n  \/* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section, \n  * the startup code needs to be modified to copy the init-values.  \n  *\/\n  .ccmram :\n  {\n    . = ALIGN(4);\n    _sccmram = .;       \/* create a global symbol at ccmram start *\/\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       \/* create a global symbol at ccmram end *\/\n  } >CCMRAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"567b2e1d68193451c1733a8835a44de0c1a32b48","subject":"provision for _examples_ (currently seriously borked)","message":"provision for _examples_ (currently seriously borked)\n","repos":"stevedonovan\/winapi,stevedonovan\/winapi","old_file":"config.ld","new_file":"config.ld","new_contents":"-- ldoc configuration file\r\nfile = \"winapi.l.c\"\r\noutput = \"api\"\r\ntitle = \"Winapi documentation\"\r\nproject = \"winapi\"\r\n-- no_summary = true\r\n-- examples = {'examples\/test-reg.lua'}\r\ndescription = [[\r\nA minimal but useful binding to the Windows API.\r\n]]\r\n\r\nformat = 'markdown'\r\n\r\n\r\n","old_contents":"-- ldoc configuration file\r\nfile = \"winapi.l.c\"\r\noutput = \"api\"\r\ntitle = \"Winapi documentation\"\r\nproject = \"winapi\"\r\n-- no_summary = true\r\ndescription = [[\r\nA minimal but useful binding to the Windows API.\r\n]]\r\n\r\nformat = 'markdown'\r\n\r\n\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3155268efb27fce7de141b25d05f53405ba08bca","subject":"Revert \"MYNEWT-512 Replace gen. sysinit with linker sect\"","message":"Revert \"MYNEWT-512 Replace gen. sysinit with linker sect\"\n\nThis reverts commit 5ba55a5201fd99c23688518d30f13356ce3a34c9.\n","repos":"runtimeinc\/mynewt_arduino_zero,runtimeinc\/mynewt_arduino_zero,runtimeinc\/mynewt_arduino_zero","old_file":"hw\/mcu\/atmel\/samd21xx\/samd21xx.ld","new_file":"hw\/mcu\/atmel\/samd21xx\/samd21xx.ld","new_contents":"\/**\r\n * \\file\r\n *\r\n * \\brief Linker script for running in internal FLASH on the SAMD21G18A\r\n *\r\n * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.\r\n *\r\n * \\asf_license_start\r\n *\r\n * \\page License\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * 1. Redistributions of source code must retain the above copyright notice,\r\n *    this list of conditions and the following disclaimer.\r\n *\r\n * 2. Redistributions in binary form must reproduce the above copyright notice,\r\n *    this list of conditions and the following disclaimer in the documentation\r\n *    and\/or other materials provided with the distribution.\r\n *\r\n * 3. The name of Atmel may not be used to endorse or promote products derived\r\n *    from this software without specific prior written permission.\r\n *\r\n * 4. This software may only be redistributed and used in connection with an\r\n *    Atmel microcontroller product.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\r\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n * POSSIBILITY OF SUCH DAMAGE.\r\n *\r\n * \\asf_license_stop\r\n *\r\n *\/\r\n\r\n\r\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nSEARCH_DIR(.)\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x200; \/* required amount of stack *\/\r\n\r\n\/* The stack size used by the application. NOTE: you need to adjust according to your application. *\/\r\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;\r\n\r\nENTRY(Reset_Handler)\r\n\r\n\/* Section Definitions *\/\r\nSECTIONS\r\n{\r\n\r\n    .imghdr (NOLOAD):\r\n    {\r\n        . = . + _imghdr_size;\r\n    } > FLASH\r\n\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        _sfixed = .;\r\n        __isr_vector_start = .;\r\n        KEEP(*(.vectors .vectors.*))\r\n        __isr_vector_end = .;\r\n\r\n        *(.text .text.* .gnu.linkonce.t.*)\r\n        *(.glue_7t) *(.glue_7)\r\n        *(.rodata .rodata* .gnu.linkonce.r.*)\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\r\n        \/* Support C constructors, and C destructors in both user code\r\n           and the C library. This also provides support for C++ code. *\/\r\n        . = ALIGN(4);\r\n        KEEP(*(.init))\r\n        . = ALIGN(4);\r\n        __preinit_array_start = .;\r\n        KEEP (*(.preinit_array))\r\n        __preinit_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        __init_array_start = .;\r\n        KEEP (*(SORT(.init_array.*)))\r\n        KEEP (*(.init_array))\r\n        __init_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        KEEP (*crtbegin.o(.ctors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n        KEEP (*(SORT(.ctors.*)))\r\n        KEEP (*crtend.o(.ctors))\r\n\r\n        . = ALIGN(4);\r\n        KEEP(*(.fini))\r\n\r\n        . = ALIGN(4);\r\n        __fini_array_start = .;\r\n        KEEP (*(.fini_array))\r\n        KEEP (*(SORT(.fini_array.*)))\r\n        __fini_array_end = .;\r\n\r\n        KEEP (*crtbegin.o(.dtors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n        KEEP (*(SORT(.dtors.*)))\r\n        KEEP (*crtend.o(.dtors))\r\n\r\n        . = ALIGN(4);\r\n        _efixed = .;            \/* End of text section *\/\r\n    } > FLASH\r\n\r\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n    PROVIDE_HIDDEN (__exidx_start = .);\r\n    .ARM.exidx :\r\n    {\r\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n    PROVIDE_HIDDEN (__exidx_end = .);\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n\r\n    .vector_relocation :\r\n    {\r\n        . = ALIGN(4);\r\n        __vector_tbl_reloc__ = .;\r\n        . = . + (__isr_vector_end - __isr_vector_start);\r\n        . = ALIGN(4);\r\n    } > RAM\r\n\r\n    .relocate :\r\n    {\r\n        . = ALIGN(4);\r\n        _srelocate = .;\r\n        *(.data .data.*);\r\n        . = ALIGN(4);\r\n        _erelocate = .;\r\n    } > RAM AT > FLASH\r\n\r\n    \/* .bss section which is used for uninitialized data *\/\r\n    .bss (NOLOAD) :\r\n    {\r\n        . = ALIGN(4);\r\n\t__bss_start__ = . ;\r\n        _sbss = . ;\r\n        _szero = .;\r\n        *(.bss .bss.*)\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n\t__bss_end__ = . ;\r\n        _ebss = . ;\r\n        _ezero = .;\r\n    } > RAM\r\n\r\n    \/* Heap starts after BSS *\/\r\n    __HeapBase = .;\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  .heap :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( _user_heap_start = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = ALIGN(4);\r\n  } > RAM\r\n\r\n\r\n    \/* .stack_dummy section doesn't contains any symbols. It is only\r\n     * used for linker to calculate size of stack sections, and assign\r\n     * values to stack symbols later *\/\r\n    .stack_dummy (COPY):\r\n    {\r\n        . = . + STACK_SIZE;\r\n        *(.stack*)\r\n    } > RAM\r\n\r\n    _ram_start = ORIGIN(RAM);\r\n\r\n    \/* Set stack top to end of RAM, and stack limit move down by\r\n     * size of stack_dummy section *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n    PROVIDE(__stack = __StackTop);\r\n\r\n    \/* Top of head is the bottom of the stack *\/\r\n  _user_heap_end = __StackLimit;\r\n  __HeapLimit = __StackLimit;\r\n\r\n\r\n    \/* Check if data + heap + stack exceeds RAM limit *\/\r\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","old_contents":"\/**\r\n * \\file\r\n *\r\n * \\brief Linker script for running in internal FLASH on the SAMD21G18A\r\n *\r\n * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.\r\n *\r\n * \\asf_license_start\r\n *\r\n * \\page License\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * 1. Redistributions of source code must retain the above copyright notice,\r\n *    this list of conditions and the following disclaimer.\r\n *\r\n * 2. Redistributions in binary form must reproduce the above copyright notice,\r\n *    this list of conditions and the following disclaimer in the documentation\r\n *    and\/or other materials provided with the distribution.\r\n *\r\n * 3. The name of Atmel may not be used to endorse or promote products derived\r\n *    from this software without specific prior written permission.\r\n *\r\n * 4. This software may only be redistributed and used in connection with an\r\n *    Atmel microcontroller product.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR IMPLIED\r\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r\n * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r\n * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n * POSSIBILITY OF SUCH DAMAGE.\r\n *\r\n * \\asf_license_stop\r\n *\r\n *\/\r\n\r\n\r\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\r\nOUTPUT_ARCH(arm)\r\nSEARCH_DIR(.)\r\n\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x200; \/* required amount of stack *\/\r\n\r\n\/* The stack size used by the application. NOTE: you need to adjust according to your application. *\/\r\nSTACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;\r\n\r\nENTRY(Reset_Handler)\r\n\r\n\/* Section Definitions *\/\r\nSECTIONS\r\n{\r\n\r\n    .imghdr (NOLOAD):\r\n    {\r\n        . = . + _imghdr_size;\r\n    } > FLASH\r\n\r\n    .text :\r\n    {\r\n        . = ALIGN(4);\r\n        _sfixed = .;\r\n        __isr_vector_start = .;\r\n        KEEP(*(.vectors .vectors.*))\r\n        __isr_vector_end = .;\r\n\r\n        *(.text .text.* .gnu.linkonce.t.*)\r\n        *(.glue_7t) *(.glue_7)\r\n        *(.rodata .rodata* .gnu.linkonce.r.*)\r\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n\r\n        \/* Support C constructors, and C destructors in both user code\r\n           and the C library. This also provides support for C++ code. *\/\r\n        . = ALIGN(4);\r\n        KEEP(*(.init))\r\n        . = ALIGN(4);\r\n        __preinit_array_start = .;\r\n        KEEP (*(.preinit_array))\r\n        __preinit_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        __init_array_start = .;\r\n        KEEP (*(SORT(.init_array.*)))\r\n        KEEP (*(.init_array))\r\n        __init_array_end = .;\r\n\r\n        . = ALIGN(4);\r\n        KEEP (*crtbegin.o(.ctors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r\n        KEEP (*(SORT(.ctors.*)))\r\n        KEEP (*crtend.o(.ctors))\r\n\r\n        . = ALIGN(4);\r\n        KEEP(*(.fini))\r\n\r\n        . = ALIGN(4);\r\n        __fini_array_start = .;\r\n        KEEP (*(.fini_array))\r\n        KEEP (*(SORT(.fini_array.*)))\r\n        __fini_array_end = .;\r\n\r\n        KEEP (*crtbegin.o(.dtors))\r\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r\n        KEEP (*(SORT(.dtors.*)))\r\n        KEEP (*crtend.o(.dtors))\r\n\r\n        . = ALIGN(4);\r\n        _efixed = .;            \/* End of text section *\/\r\n    } > FLASH\r\n\r\n    \/* The sysinit section contains package initialization information. *\/\r\n    .sysinit :\r\n    {\r\n        __sysinit_start__ = .;\r\n        KEEP(*(sysinit))\r\n        __sysinit_end__ = .;\r\n    } > FLASH\r\n\r\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\r\n    PROVIDE_HIDDEN (__exidx_start = .);\r\n    .ARM.exidx :\r\n    {\r\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    } > FLASH\r\n    PROVIDE_HIDDEN (__exidx_end = .);\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n\r\n    .vector_relocation :\r\n    {\r\n        . = ALIGN(4);\r\n        __vector_tbl_reloc__ = .;\r\n        . = . + (__isr_vector_end - __isr_vector_start);\r\n        . = ALIGN(4);\r\n    } > RAM\r\n\r\n    .relocate :\r\n    {\r\n        . = ALIGN(4);\r\n        _srelocate = .;\r\n        *(.data .data.*);\r\n        . = ALIGN(4);\r\n        _erelocate = .;\r\n    } > RAM AT > FLASH\r\n\r\n    \/* .bss section which is used for uninitialized data *\/\r\n    .bss (NOLOAD) :\r\n    {\r\n        . = ALIGN(4);\r\n\t__bss_start__ = . ;\r\n        _sbss = . ;\r\n        _szero = .;\r\n        *(.bss .bss.*)\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n\t__bss_end__ = . ;\r\n        _ebss = . ;\r\n        _ezero = .;\r\n    } > RAM\r\n\r\n    \/* Heap starts after BSS *\/\r\n    __HeapBase = .;\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  .heap :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( _user_heap_start = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = ALIGN(4);\r\n  } > RAM\r\n\r\n\r\n    \/* .stack_dummy section doesn't contains any symbols. It is only\r\n     * used for linker to calculate size of stack sections, and assign\r\n     * values to stack symbols later *\/\r\n    .stack_dummy (COPY):\r\n    {\r\n        . = . + STACK_SIZE;\r\n        *(.stack*)\r\n    } > RAM\r\n\r\n    _ram_start = ORIGIN(RAM);\r\n\r\n    \/* Set stack top to end of RAM, and stack limit move down by\r\n     * size of stack_dummy section *\/\r\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n    PROVIDE(__stack = __StackTop);\r\n\r\n    \/* Top of head is the bottom of the stack *\/\r\n  _user_heap_end = __StackLimit;\r\n  __HeapLimit = __StackLimit;\r\n\r\n\r\n    \/* Check if data + heap + stack exceeds RAM limit *\/\r\n    ASSERT(__HeapBase <= __HeapLimit, \"region RAM overflowed with stack\")\r\n}\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d17fdb415442ece3fc688fa1ff7277d045208fc9","subject":"Update build files.","message":"Update build files.\n","repos":"atraari\/playground,atraari\/playground","old_file":"src\/apps\/init\/linker.lds","new_file":"src\/apps\/init\/linker.lds","new_contents":"","old_contents":"\/*\n * Copyright 2014, NICTA\n *\n * This software may be distributed and modified according to the terms of\n * the BSD 2-Clause license. Note that NO WARRANTY is provided.\n * See \"LICENSE_BSD2.txt\" for details.\n *\n * @TAG(NICTA_BSD)\n *\/\n\nENTRY(_start)\n\nSECTIONS\n{\n    PROVIDE (__executable_start = 0x8000);\n    . = 0x8000;\n\n    \/* Code. *\/\n    .text : ALIGN(4096) {\n        _text = .;\n        *(.text*)\n    }\n\n    \/* Read Only Data. *\/\n    .rodata : ALIGN(4096) {\n        . = ALIGN(32);\n        *(.rodata*)\n    }\n\n    \/* Data \/ BSS *\/\n    .data : ALIGN(4096) {\n        *(.data)\n    }\n    .bss : ALIGN(4096) {\n        *(.bss)\n        *(COMMON)\n    }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"4c93672d74a8d7c68d093e364786ceb14909718e","subject":"","message":"\n\ngit-svn-id: https:\/\/chibios.svn.sourceforge.net\/svnroot\/chibios\/trunk@2796 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"testhal\/LPC11xx\/IRQ_STORM\/ch.ld","new_file":"testhal\/LPC11xx\/IRQ_STORM\/ch.ld","new_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * LPC1114 memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0100;\r\n__process_stack_size__  = 0x0100;\r\n__stacks_total_size__   = __main_stack_size__ + __process_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x00000000, len = 32k\r\n    ram : org = 0x10000000, len = 8k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n    . = 0;\r\n\r\n    .text : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        _text = .;\r\n        KEEP(*(vectors))\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n    } > flash\r\n\r\n    .ctors :\r\n    {\r\n        PROVIDE(_ctors_start_ = .);\r\n        KEEP(*(SORT(.ctors.*)))\r\n        KEEP(*(.ctors))\r\n        PROVIDE(_ctors_end_ = .);\r\n    } > flash\r\n\r\n    .dtors :\r\n    {\r\n        PROVIDE(_dtors_start_ = .);\r\n        KEEP(*(SORT(.dtors.*)))\r\n        KEEP(*(.dtors))\r\n        PROVIDE(_dtors_end_ = .);\r\n    } > flash\r\n\r\n    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash\r\n    __exidx_end = .;\r\n\r\n    .eh_frame_hdr : {*(.eh_frame_hdr)}\r\n\r\n    .eh_frame : ONLY_IF_RO {*(.eh_frame)}\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .data :\r\n    {\r\n        _data = .;\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        _edata = .;\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        _bss_start = .;\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _bss_end = .;\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__ - __stacks_total_size__;\r\n","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * ST32F103 memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0400;\r\n__process_stack_size__  = 0x0400;\r\n__stacks_total_size__   = __main_stack_size__ + __process_stack_size__;\r\n\r\nMEMORY\r\n{\r\n    flash : org = 0x08000000, len = 128k\r\n    ram : org = 0x20000000, len = 20k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n    . = 0;\r\n\r\n    .text : ALIGN(16) SUBALIGN(16)\r\n    {\r\n        _text = .;\r\n        KEEP(*(vectors))\r\n        *(.text)\r\n        *(.text.*)\r\n        *(.rodata)\r\n        *(.rodata.*)\r\n        *(.glue_7t)\r\n        *(.glue_7)\r\n        *(.gcc*)\r\n    } > flash\r\n\r\n    .ctors :\r\n    {\r\n        PROVIDE(_ctors_start_ = .);\r\n        KEEP(*(SORT(.ctors.*)))\r\n        KEEP(*(.ctors))\r\n        PROVIDE(_ctors_end_ = .);\r\n    } > flash\r\n\r\n    .dtors :\r\n    {\r\n        PROVIDE(_dtors_start_ = .);\r\n        KEEP(*(SORT(.dtors.*)))\r\n        KEEP(*(.dtors))\r\n        PROVIDE(_dtors_end_ = .);\r\n    } > flash\r\n\r\n    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}\r\n\r\n    __exidx_start = .;\r\n    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash\r\n    __exidx_end = .;\r\n\r\n    .eh_frame_hdr : {*(.eh_frame_hdr)}\r\n\r\n    .eh_frame : ONLY_IF_RO {*(.eh_frame)}\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;\r\n    _textdata = _etext;\r\n\r\n    .data :\r\n    {\r\n        _data = .;\r\n        *(.data)\r\n        . = ALIGN(4);\r\n        *(.data.*)\r\n        . = ALIGN(4);\r\n        *(.ramtext)\r\n        . = ALIGN(4);\r\n        _edata = .;\r\n    } > ram AT > flash\r\n\r\n    .bss :\r\n    {\r\n        _bss_start = .;\r\n        *(.bss)\r\n        . = ALIGN(4);\r\n        *(.bss.*)\r\n        . = ALIGN(4);\r\n        *(COMMON)\r\n        . = ALIGN(4);\r\n        _bss_end = .;\r\n    } > ram    \r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__ - __stacks_total_size__;\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bf1969e555197f501e78e5595d7dd95c2263b0e7","subject":"increase irom0","message":"increase irom0\n","repos":"FelixPe\/nodemcu-firmware,nodemcu\/nodemcu-firmware,filug\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,borromeotlhs\/nodemcu-firmware,romanchyla\/nodemcu-firmware,djphoenix\/nodemcu-firmware,petrkr\/nodemcu-firmware,FelixPe\/nodemcu-firmware,ktosiu\/nodemcu-firmware,vowstar\/nodemcu-firmware,funshine\/nodemcu-firmware,nodemcu\/nodemcu-firmware,Alkorin\/nodemcu-firmware,romanchyla\/nodemcu-firmware,dscoolx6\/MyESP8266,weera00\/nodemcu-firmware,robertfoss\/nodemcu-firmware,abgoyal\/nodemcu-firmware,vowstar\/nodemcu-firmware,mikeller\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,bhrt\/nodeMCU,cs8425\/nodemcu-firmware,FrankX0\/nodemcu-firmware,Audumla\/audiot-nodemcu-firmware,FrankX0\/nodemcu-firmware,remspoor\/nodemcu-firmware,chadouming\/nodemcu-firmware,creationix\/nodemcu-firmware,londry\/nodemcu-firmware,SmartArduino\/nodemcu-firmware,Kisaua\/nodemcu-firmware,TerryE\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,zerog2k\/nodemcu-firmware,Andrew-Collins\/nodemcu-firmware,vsky279\/nodemcu-firmware,funshine\/nodemcu-firmware,zerog2k\/nodemcu-firmware,ruisebastiao\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,abgoyal\/nodemcu-firmware,yurenyong123\/nodemcu-firmware,jmattsson\/nodemcu-firmware,iotcafe\/nodemcu-firmware,eku\/nodemcu-firmware,Kisaua\/nodemcu-firmware,vsky279\/nodemcu-firmware,vsky279\/nodemcu-firmware,oyooyo\/nodemcu-firmware,creationix\/nodemcu-firmware,ciufciuf57\/nodemcu-firmware,bhrt\/nodeMCU,danronco\/nodemcu-firmware,funshine\/nodemcu-firmware,bhrt\/nodeMCU,petrkr\/nodemcu-firmware,iotcafe\/nodemcu-firmware,londry\/nodemcu-firmware,marktsai0316\/nodemcu-firmware,eku\/nodemcu-firmware,natetrue\/nodemcu-firmware,ciufciuf57\/nodemcu-firmware,eku\/nodemcu-firmware,romanchyla\/nodemcu-firmware,noahchense\/nodemcu-firmware,TerryE\/nodemcu-firmware,eku\/nodemcu-firmware,borromeotlhs\/nodemcu-firmware,sowbug\/nodemcu-firmware,shangwudong\/MyNodeMcu,radiojam11\/nodemcu-firmware,nodemcu\/nodemcu-firmware,vowstar\/nodemcu-firmware,remspoor\/nodemcu-firmware,nwf\/nodemcu-firmware,jmattsson\/nodemcu-firmware,marktsai0316\/nodemcu-firmware,creationix\/nodemcu-firmware,anusornc\/nodemcu-firmware,AllAboutEE\/nodemcu-firmware,fetchbot\/nodemcu-firmware,vsky279\/nodemcu-firmware,Alkorin\/nodemcu-firmware,karrots\/nodemcu-firmware,noahchense\/nodemcu-firmware,TerryE\/nodemcu-firmware,daned33\/nodemcu-firmware,oyooyo\/nodemcu-firmware,digitalloggers\/nodemcu-firmware,Kisaua\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,oyooyo\/nodemcu-firmware,nwf\/nodemcu-firmware,radiojam11\/nodemcu-firmware,makefu\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,FelixPe\/nodemcu-firmware,klukonin\/nodemcu-firmware,sowbug\/nodemcu-firmware,fetchbot\/nodemcu-firmware,dnc40085\/nodemcu-firmware,jmattsson\/nodemcu-firmware,rickvanbodegraven\/nodemcu-firmware,radiojam11\/nodemcu-firmware,xatanais\/nodemcu-firmware,Audumla\/audiot-nodemcu-firmware,HEYAHONG\/nodemcu-firmware,dnc40085\/nodemcu-firmware,digitalloggers\/nodemcu-firmware,makefu\/nodemcu-firmware,FelixPe\/nodemcu-firmware,iotcafe\/nodemcu-firmware,remspoor\/nodemcu-firmware,christakahashi\/nodemcu-firmware,bogvak\/nodemcu-firmware,ojahan\/node-mcu-firmware,funshine\/nodemcu-firmware,cs8425\/nodemcu-firmware,FrankX0\/nodemcu-firmware,jmattsson\/nodemcu-firmware,bogvak\/nodemcu-firmware,TerryE\/nodemcu-firmware,karrots\/nodemcu-firmware,klukonin\/nodemcu-firmware,chadouming\/nodemcu-firmware,djphoenix\/nodemcu-firmware,vsky279\/nodemcu-firmware,rickvanbodegraven\/nodemcu-firmware,rowellx68\/nodemcu-firmware-custom,Alkorin\/nodemcu-firmware,FrankX0\/nodemcu-firmware,oyooyo\/nodemcu-firmware,nwf\/nodemcu-firmware,londry\/nodemcu-firmware,zhujunsan\/nodemcu-firmware,filug\/nodemcu-firmware,natetrue\/nodemcu-firmware,christakahashi\/nodemcu-firmware,karrots\/nodemcu-firmware,djphoenix\/nodemcu-firmware,robertfoss\/nodemcu-firmware,abgoyal\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,benwolfe\/nodemcu-firmware,dscoolx6\/MyESP8266,flexiti\/nodemcu-firmware,raburton\/nodemcu-firmware,ojahan\/node-mcu-firmware,mikeller\/nodemcu-firmware,danronco\/nodemcu-firmware,bhrt\/nodeMCU,devsaurus\/nodemcu-firmware,robertfoss\/nodemcu-firmware,dan-cleinmark\/nodemcu-firmware,cs8425\/nodemcu-firmware,sowbug\/nodemcu-firmware,dan-cleinmark\/nodemcu-firmware,shangwudong\/MyNodeMcu,borromeotlhs\/nodemcu-firmware,petrkr\/nodemcu-firmware,rickvanbodegraven\/nodemcu-firmware,petrkr\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,djphoenix\/nodemcu-firmware,Andrew-Collins\/nodemcu-firmware,ciufciuf57\/nodemcu-firmware,fetchbot\/nodemcu-firmware,Audumla\/audiot-nodemcu-firmware,luizfeliperj\/nodemcu-firmware,filug\/nodemcu-firmware,noahchense\/nodemcu-firmware,dan-cleinmark\/nodemcu-firmware,daned33\/nodemcu-firmware,makefu\/nodemcu-firmware,christakahashi\/nodemcu-firmware,Alkorin\/nodemcu-firmware,dnc40085\/nodemcu-firmware,SmartArduino\/nodemcu-firmware,zhujunsan\/nodemcu-firmware,anusornc\/nodemcu-firmware,fetchbot\/nodemcu-firmware,Andrew-Collins\/nodemcu-firmware,digitalloggers\/nodemcu-firmware,cal101\/nodemcu-firmware,weera00\/nodemcu-firmware,raburton\/nodemcu-firmware,daned33\/nodemcu-firmware,flexiti\/nodemcu-firmware,devsaurus\/nodemcu-firmware,devsaurus\/nodemcu-firmware,benwolfe\/nodemcu-firmware,rowellx68\/nodemcu-firmware-custom,HEYAHONG\/nodemcu-firmware,karrots\/nodemcu-firmware,mikeller\/nodemcu-firmware,zerog2k\/nodemcu-firmware,xatanais\/nodemcu-firmware,zhujunsan\/nodemcu-firmware,FelixPe\/nodemcu-firmware,Alkorin\/nodemcu-firmware,shangwudong\/MyNodeMcu,nodemcu\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,flexiti\/nodemcu-firmware,nwf\/nodemcu-firmware,yurenyong123\/nodemcu-firmware,chadouming\/nodemcu-firmware,FrankX0\/nodemcu-firmware,remspoor\/nodemcu-firmware,danronco\/nodemcu-firmware,ruisebastiao\/nodemcu-firmware,rowellx68\/nodemcu-firmware-custom,funshine\/nodemcu-firmware,TerryE\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,AllAboutEE\/nodemcu-firmware,benwolfe\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,anusornc\/nodemcu-firmware,xatanais\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,christakahashi\/nodemcu-firmware,ktosiu\/nodemcu-firmware,nodemcu\/nodemcu-firmware,ruisebastiao\/nodemcu-firmware,jmattsson\/nodemcu-firmware,SmartArduino\/nodemcu-firmware,orlando3d\/nodemcu-firmware,AllAboutEE\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,devsaurus\/nodemcu-firmware,dnc40085\/nodemcu-firmware,karrots\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,petrkr\/nodemcu-firmware,klukonin\/nodemcu-firmware,ojahan\/node-mcu-firmware,remspoor\/nodemcu-firmware,shangwudong\/MyNodeMcu,shangwudong\/MyNodeMcu,bogvak\/nodemcu-firmware,orlando3d\/nodemcu-firmware,dscoolx6\/MyESP8266,dnc40085\/nodemcu-firmware,yurenyong123\/nodemcu-firmware,bhrt\/nodeMCU,chadouming\/nodemcu-firmware,nwf\/nodemcu-firmware,marktsai0316\/nodemcu-firmware,raburton\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,christakahashi\/nodemcu-firmware,weera00\/nodemcu-firmware,devsaurus\/nodemcu-firmware,ktosiu\/nodemcu-firmware,orlando3d\/nodemcu-firmware,cal101\/nodemcu-firmware,natetrue\/nodemcu-firmware,cal101\/nodemcu-firmware","old_file":"ld\/eagle.app.v6.ld","new_file":"ld\/eagle.app.v6.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x8000\n  irom0_0_seg :                       \torg = 0x40210000, len = 0x55000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n    *(.rodata2.text)\n\n    \/* put font and progmem data into irom0 *\/\n    *(.u8g_progmem.*)\n\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_used_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n  \n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *\/\n    *(.literal .text .iram0.text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\nMEMORY\n{\n  dport0_0_seg :                      \torg = 0x3FF00000, len = 0x10\n  dram0_0_seg :                       \torg = 0x3FFE8000, len = 0x14000\n  iram1_0_seg :                       \torg = 0x40100000, len = 0x8000\n  irom0_0_seg :                       \torg = 0x40210000, len = 0x54000\n}\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n    *(.literal.* .text.*)\n    *(.rodata2.text)\n\n    \/* put font and progmem data into irom0 *\/\n    *(.u8g_progmem.*)\n\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_used_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n  \n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    \/* *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *\/\n    *(.literal .text .iram0.text .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b428d2895060486f298086d77c7e48c5cf3fda50","subject":"spiflash rom: Add symbols accidentally removed in refactor","message":"spiflash rom: Add symbols accidentally removed in refactor\n","repos":"MIhanguangyi\/esp-idf,mashaoze\/esp-idf,dschaefer\/esp-idf,ajs124\/esp-idf,www220\/esp-idf,www220\/esp-idf,www220\/esp-idf,empoweredhomes\/esp-idf,ajs124\/esp-idf,www220\/esp-idf,empoweredhomes\/esp-idf,armada-ai\/esp-idf,dschaefer\/esp-idf,empoweredhomes\/esp-idf,jaracil\/esp-idf,jaracil\/esp-idf,MIhanguangyi\/esp-idf,mashaoze\/esp-idf,nineisk\/esp-idf,nineisk\/esp-idf,espressif\/esp-idf,Hermiedapwdrman\/esp-idf,shukyisme\/esp-idf-kwik,Hermiedapwdrman\/esp-idf,espressif\/esp-idf,ajs124\/esp-idf,www220\/esp-idf,MIhanguangyi\/esp-idf,armada-ai\/esp-idf,empoweredhomes\/esp-idf,armada-ai\/esp-idf,ajs124\/esp-idf,Hermiedapwdrman\/esp-idf,dschaefer\/esp-idf,empoweredhomes\/esp-idf,Hermiedapwdrman\/esp-idf,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,MIhanguangyi\/esp-idf,nineisk\/esp-idf,mashaoze\/esp-idf,shukyisme\/esp-idf-kwik,dschaefer\/esp-idf,dschaefer\/esp-idf,armada-ai\/esp-idf,Hermiedapwdrman\/esp-idf,mashaoze\/esp-idf,shukyisme\/esp-idf-kwik,jaracil\/esp-idf,espressif\/esp-idf,jaracil\/esp-idf,MIhanguangyi\/esp-idf,shukyisme\/esp-idf-kwik,espressif\/esp-idf,nineisk\/esp-idf","old_file":"components\/esp32\/ld\/esp32.rom.ld","new_file":"components\/esp32\/ld\/esp32.rom.ld","new_contents":"\/*\nESP32 ROM address table\nGenerated for ROM with MD5sum:\nab8282ae908fe9e7a63fb2a4ac2df013  ..\/..\/rom_image\/prorom.elf\n*\/\nPROVIDE ( abort = 0x4000bba4 );\nPROVIDE ( abs = 0x40056340 );\nPROVIDE ( __absvdi2 = 0x4006387c );\nPROVIDE ( __absvsi2 = 0x40063868 );\nPROVIDE ( Add2SelfBigHex256 = 0x40015b7c );\nPROVIDE ( AddBigHex256 = 0x40015b28 );\nPROVIDE ( AddBigHexModP256 = 0x40015c98 );\nPROVIDE ( __adddf3 = 0x40002590 );\nPROVIDE ( AddP256 = 0x40015c74 );\nPROVIDE ( AddPdiv2_256 = 0x40015ce0 );\nPROVIDE ( __addsf3 = 0x400020e8 );\nPROVIDE ( __addvdi3 = 0x40002cbc );\nPROVIDE ( __addvsi3 = 0x40002c98 );\nPROVIDE ( aes_128_cbc_decrypt = 0x4005cc7c );\nPROVIDE ( aes_128_cbc_encrypt = 0x4005cc18 );\nPROVIDE ( aes_unwrap = 0x4005ccf0 );\nPROVIDE ( app_gpio_arg = 0x3ffe003c );\nPROVIDE ( app_gpio_handler = 0x3ffe0040 );\nPROVIDE ( __ascii_wctomb = 0x40058ef0 );\nPROVIDE ( asctime = 0x40059588 );\nPROVIDE ( asctime_r = 0x40000ec8 );\nPROVIDE ( __ashldi3 = 0x4000c818 );\nPROVIDE ( __ashrdi3 = 0x4000c830 );\nPROVIDE ( atoi = 0x400566c4 );\nPROVIDE ( _atoi_r = 0x400566d4 );\nPROVIDE ( atol = 0x400566ec );\nPROVIDE ( _atol_r = 0x400566fc );\nPROVIDE ( base64_decode = 0x4005ced8 );\nPROVIDE ( base64_encode = 0x4005cdbc );\nPROVIDE ( BasePoint_x_256 = 0x3ff97488 );\nPROVIDE ( BasePoint_y_256 = 0x3ff97468 );\nPROVIDE ( bigHexInversion256 = 0x400168f0 );\nPROVIDE ( bigHexP256 = 0x3ff973bc );\nPROVIDE ( __bswapdi2 = 0x400649c4 );\nPROVIDE ( __bswapsi2 = 0x4006499c );\nPROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c );\nPROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 );\nPROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 );\nPROVIDE ( btdm_r_data_init = 0x4001002c );\nPROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 );\nPROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 );\nPROVIDE ( btdm_r_ip_func_p_set = 0x40019afc );\nPROVIDE ( btdm_r_modules_func_p_get = 0x4005427c );\nPROVIDE ( btdm_r_modules_func_p_set = 0x40054270 );\nPROVIDE ( btdm_r_plf_func_p_set = 0x40054288 );\nPROVIDE ( bt_util_buf_env = 0x3ffb8bd4 );\nPROVIDE ( bzero = 0x4000c1f4 );\nPROVIDE ( cache_flash_mmu_set_rom = 0x400095e0 );\nPROVIDE ( Cache_Flush_rom = 0x40009a14 );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\nPROVIDE ( cache_sram_mmu_set_rom = 0x400097f4 );\n\/* This is static function, but can be used, not generated by script*\/\nPROVIDE ( calc_rtc_memory_crc = 0x40008170 );\nPROVIDE ( calloc = 0x4000bee4 );\nPROVIDE ( _calloc_r = 0x4000bbf8 );\nPROVIDE ( _cleanup = 0x40001df8 );\nPROVIDE ( _cleanup_r = 0x40001d48 );\nPROVIDE ( __clear_cache = 0x40063860 );\nPROVIDE ( close = 0x40001778 );\nPROVIDE ( _close_r = 0x4000bd3c );\nPROVIDE ( __clrsbdi2 = 0x40064a38 );\nPROVIDE ( __clrsbsi2 = 0x40064a20 );\nPROVIDE ( __clzdi2 = 0x4000ca50 );\nPROVIDE ( __clzsi2 = 0x4000c7e8 );\nPROVIDE ( __cmpdi2 = 0x40063820 );\nPROVIDE ( co_default_bdaddr = 0x3ffae704 );\nPROVIDE ( co_null_bdaddr = 0x3ffb80e0 );\nPROVIDE ( co_sca2ppm = 0x3ff971e8 );\nPROVIDE ( crc16_be = 0x4005d09c );\nPROVIDE ( crc16_le = 0x4005d05c );\nPROVIDE ( crc32_be = 0x4005d024 );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( crc8_be = 0x4005d114 );\nPROVIDE ( crc8_le = 0x4005d0e0 );\nPROVIDE ( creat = 0x40000e8c );\nPROVIDE ( ctime = 0x400595b0 );\nPROVIDE ( ctime_r = 0x400595c4 );\nPROVIDE ( _ctype_ = 0x3ff96354 );\nPROVIDE ( __ctype_ptr__ = 0x3ff96350 );\nPROVIDE ( __ctzdi2 = 0x4000ca64 );\nPROVIDE ( __ctzsi2 = 0x4000c7f0 );\nPROVIDE ( _data_end_rom = 0x4000d5c8 );\nPROVIDE ( _data_end_btdm_rom = 0x4000d4f8 );\nPROVIDE ( _data_start_rom = 0x4000d4f8 );\nPROVIDE ( _data_start_btdm_rom = 0x4000d4f4 );\nPROVIDE ( _data_start_btdm = 0x3ffae6e0);\nPROVIDE ( _data_end_btdm = 0x3ffaff10);\nPROVIDE ( _bss_start_btdm = 0x3ffb8000);\nPROVIDE ( _bss_end_btdm = 0x3ffbff70);\nPROVIDE ( _daylight = 0x3ffae0a4 );\nPROVIDE ( dbg_default_handler = 0x3ff97218 );\nPROVIDE ( dbg_state = 0x3ffb8d5d );\nPROVIDE ( DebugE256PublicKey_x = 0x3ff97428 );\nPROVIDE ( DebugE256PublicKey_y = 0x3ff97408 );\nPROVIDE ( DebugE256SecretKey = 0x3ff973e8 );\nPROVIDE ( debug_timer = 0x3ffe042c );\nPROVIDE ( debug_timerfn = 0x3ffe0430 );\nPROVIDE ( dh_group14_generator = 0x3ff9ac60 );\nPROVIDE ( dh_group14_prime = 0x3ff9ab60 );\nPROVIDE ( dh_group15_generator = 0x3ff9ab5f );\nPROVIDE ( dh_group15_prime = 0x3ff9a9df );\nPROVIDE ( dh_group16_generator = 0x3ff9a9de );\nPROVIDE ( dh_group16_prime = 0x3ff9a7de );\nPROVIDE ( dh_group17_generator = 0x3ff9a7dd );\nPROVIDE ( dh_group17_prime = 0x3ff9a4dd );\nPROVIDE ( dh_group18_generator = 0x3ff9a4dc );\nPROVIDE ( dh_group18_prime = 0x3ff9a0dc );\nPROVIDE ( dh_group1_generator = 0x3ff9ae03 );\nPROVIDE ( dh_group1_prime = 0x3ff9ada3 );\nPROVIDE ( dh_group2_generator = 0x3ff9ada2 );\nPROVIDE ( dh_group2_prime = 0x3ff9ad22 );\nPROVIDE ( dh_group5_generator = 0x3ff9ad21 );\nPROVIDE ( dh_group5_prime = 0x3ff9ac61 );\nPROVIDE ( div = 0x40056348 );\nPROVIDE ( __divdc3 = 0x40064460 );\nPROVIDE ( __divdf3 = 0x40002954 );\nPROVIDE ( __divdi3 = 0x4000ca84 );\nPROVIDE ( __divsc3 = 0x40064200 );\nPROVIDE ( __divsf3 = 0x4000234c );\nPROVIDE ( __divsi3 = 0x4000c7b8 );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );\nPROVIDE ( __dummy_lock = 0x4000c728 );\nPROVIDE ( __dummy_lock_try = 0x4000c730 );\nPROVIDE ( ecc_env = 0x3ffb8d60 );\nPROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 );\nPROVIDE ( em_buf_env = 0x3ffb8d74 );\nPROVIDE ( environ = 0x3ffae0b4 );\nPROVIDE ( __env_lock = 0x40001fd4 );\nPROVIDE ( __env_unlock = 0x40001fe0 );\nPROVIDE ( __eqdf2 = 0x400636a8 );\nPROVIDE ( __eqsf2 = 0x40063374 );\nPROVIDE ( esp_crc8 = 0x4005d144 );\nPROVIDE ( _etext = 0x4000d66c );\nPROVIDE ( ets_readySet_ = 0x3ffe01f0 );\nPROVIDE ( ets_startup_callback = 0x3ffe0404 );\nPROVIDE ( exc_cause_table = 0x3ff991d0 );\nPROVIDE ( _exit_r = 0x4000bd28 );\nPROVIDE ( __extendsfdf2 = 0x40002c34 );\nPROVIDE ( fclose = 0x400020ac );\nPROVIDE ( _fclose_r = 0x40001fec );\nPROVIDE ( fflush = 0x40059394 );\nPROVIDE ( _fflush_r = 0x40059320 );\nPROVIDE ( __ffsdi2 = 0x4000ca2c );\nPROVIDE ( __ffssi2 = 0x4000c804 );\nPROVIDE ( _findenv_r = 0x40001f44 );\nPROVIDE ( __fixdfdi = 0x40002ac4 );\nPROVIDE ( __fixdfsi = 0x40002a78 );\nPROVIDE ( __fixsfdi = 0x4000244c );\nPROVIDE ( __fixsfsi = 0x4000240c );\nPROVIDE ( __fixunsdfsi = 0x40002b30 );\nPROVIDE ( __fixunssfdi = 0x40002504 );\nPROVIDE ( __fixunssfsi = 0x400024ac );\nPROVIDE ( __floatdidf = 0x4000c988 );\nPROVIDE ( __floatdisf = 0x4000c8c0 );\nPROVIDE ( __floatsidf = 0x4000c944 );\nPROVIDE ( __floatsisf = 0x4000c870 );\nPROVIDE ( __floatundidf = 0x4000c978 );\nPROVIDE ( __floatundisf = 0x4000c8b0 );\nPROVIDE ( __floatunsidf = 0x4000c938 );\nPROVIDE ( __floatunsisf = 0x4000c864 );\nPROVIDE ( __fp_lock_all = 0x40001f1c );\nPROVIDE ( __fp_unlock_all = 0x40001f30 );\nPROVIDE ( fputwc = 0x40058ea8 );\nPROVIDE ( __fputwc = 0x40058da0 );\nPROVIDE ( _fputwc_r = 0x40058e4c );\nPROVIDE ( free = 0x4000beb8 );\nPROVIDE ( _free_r = 0x4000bbcc );\nPROVIDE ( _fstat_r = 0x4000bccc );\nPROVIDE ( _fwalk = 0x4000c738 );\nPROVIDE ( _fwalk_reent = 0x4000c770 );\nPROVIDE ( __gcc_bcmp = 0x40064a70 );\nPROVIDE ( __gedf2 = 0x40063768 );\nPROVIDE ( __gesf2 = 0x4006340c );\nPROVIDE ( __get_current_time_locale = 0x40001834 );\nPROVIDE ( _getenv_r = 0x40001fbc );\nPROVIDE ( _getpid_r = 0x4000bcfc );\nPROVIDE ( __getreent = 0x4000be8c );\nPROVIDE ( _gettimeofday_r = 0x4000bc58 );\nPROVIDE ( __gettzinfo = 0x40001fcc );\nPROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 );\nPROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 );\nPROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c );\nPROVIDE ( _global_impure_ptr = 0x3ffae0b0 );\nPROVIDE ( gmtime = 0x40059848 );\nPROVIDE ( gmtime_r = 0x40059868 );\nPROVIDE ( g_phyFuns_instance = 0x3ffae0c4 );\nPROVIDE ( g_rom_flashchip = 0x3ffae270 );\nPROVIDE ( __gtdf2 = 0x400636dc );\nPROVIDE ( __gtsf2 = 0x400633a0 );\nPROVIDE ( gTxMsg = 0x3ffe0050 );\nPROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 );\nPROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 );\nPROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c );\nPROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 );\nPROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 );\nPROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c );\nPROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 );\nPROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 );\nPROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 );\nPROVIDE ( hci_command_handler = 0x4004c928 );\nPROVIDE ( hci_env = 0x3ffb9350 );\nPROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c );\nPROVIDE ( hci_evt_desc_tab = 0x3ff9751c );\nPROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 );\nPROVIDE ( hci_fc_env = 0x3ffb9340 );\nPROVIDE ( hmac_md5 = 0x4005d264 );\nPROVIDE ( hmac_md5_vector = 0x4005d17c );\nPROVIDE ( hmac_sha1 = 0x40060acc );\nPROVIDE ( hmac_sha1_vector = 0x400609e4 );\nPROVIDE ( hmac_sha256 = 0x40060d58 );\nPROVIDE ( hmac_sha256_vector = 0x40060c84 );\nPROVIDE ( isalnum = 0x40000f04 );\nPROVIDE ( isalpha = 0x40000f18 );\nPROVIDE ( isascii = 0x4000c20c );\nPROVIDE ( _isatty_r = 0x40000ea0 );\nPROVIDE ( isblank = 0x40000f2c );\nPROVIDE ( iscntrl = 0x40000f50 );\nPROVIDE ( isdigit = 0x40000f64 );\nPROVIDE ( isgraph = 0x40000f94 );\nPROVIDE ( islower = 0x40000f78 );\nPROVIDE ( isprint = 0x40000fa8 );\nPROVIDE ( ispunct = 0x40000fc0 );\nPROVIDE ( isspace = 0x40000fd4 );\nPROVIDE ( isupper = 0x40000fe8 );\nPROVIDE ( itoa = 0x400566b4 );\nPROVIDE ( __itoa = 0x40056678 );\nPROVIDE ( jd_decomp = 0x400613e8 );\nPROVIDE ( jd_prepare = 0x40060fa8 );\nPROVIDE ( ke_env = 0x3ffb93cc );\nPROVIDE ( _kill_r = 0x4000bd10 );\nPROVIDE ( labs = 0x40056370 );\nPROVIDE ( lb_default_handler = 0x3ff982b8 );\nPROVIDE ( lb_default_state_tab_p_get = 0x4001c198 );\nPROVIDE ( lb_env = 0x3ffb9424 );\nPROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c );\nPROVIDE ( lb_state = 0x3ffb94e8 );\nPROVIDE ( lc_default_handler = 0x3ff98648 );\nPROVIDE ( lc_default_state_tab_p_get = 0x4002f494 );\nPROVIDE ( lc_env = 0x3ffb94ec );\nPROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 );\nPROVIDE ( lc_state = 0x3ffb9508 );\nPROVIDE ( ld_acl_br_sizes = 0x3ff98a2a );\nPROVIDE ( ld_acl_br_types = 0x3ff98a36 );\nPROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 );\nPROVIDE ( ld_acl_edr_types = 0x3ff98a22 );\nPROVIDE ( ld_env = 0x3ffb9510 );\nPROVIDE ( ldiv = 0x40056378 );\nPROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c );\nPROVIDE ( ld_sched_params = 0x3ffb96c0 );\nPROVIDE ( ld_sync_train_channels = 0x3ff98a3c );\nPROVIDE ( __ledf2 = 0x40063704 );\nPROVIDE ( __lesf2 = 0x400633c0 );\nPROVIDE ( _link_r = 0x4000bc9c );\nPROVIDE ( llc_default_handler = 0x3ff98b3c );\nPROVIDE ( llc_default_state_tab_p_get = 0x40046058 );\nPROVIDE ( llc_env = 0x3ffb96d0 );\nPROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 );\nPROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 );\nPROVIDE ( llc_hci_command_handler = 0x40042360 );\nPROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 );\nPROVIDE ( llc_state = 0x3ffb96f8 );\nPROVIDE ( lldesc_build_chain = 0x4000a850 );\nPROVIDE ( lldesc_num2link = 0x4000a948 );\nPROVIDE ( lldesc_set_owner = 0x4000a974 );\nPROVIDE ( lld_evt_env = 0x3ffb9704 );\nPROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 );\nPROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 );\nPROVIDE ( LLM_AA_CT1 = 0x3ff98d8a );\nPROVIDE ( LLM_AA_CT2 = 0x3ff98d88 );\nPROVIDE ( llm_default_handler = 0x3ff98d80 );\nPROVIDE ( llm_default_state_tab_p_get = 0x4004e718 );\nPROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 );\nPROVIDE ( llm_le_env = 0x3ffb976c );\nPROVIDE ( llm_local_cmds = 0x3ff98d38 );\nPROVIDE ( llm_local_data_len_values = 0x3ff98d1c );\nPROVIDE ( llm_local_le_feats = 0x3ff98d30 );\nPROVIDE ( llm_local_le_states = 0x3ff98d28 );\nPROVIDE ( llm_state = 0x3ffb985c );\nPROVIDE ( lm_default_handler = 0x3ff990e0 );\nPROVIDE ( lm_default_state_tab_p_get = 0x40054268 );\nPROVIDE ( lm_env = 0x3ffb9860 );\nPROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c );\nPROVIDE ( lm_local_supp_feats = 0x3ff990ee );\nPROVIDE ( lm_n_page_tab = 0x3ff990e8 );\nPROVIDE ( lmp_desc_tab = 0x3ff96e6c );\nPROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c );\nPROVIDE ( lm_state = 0x3ffb9a1c );\nPROVIDE ( __locale_charset = 0x40059540 );\nPROVIDE ( __locale_cjk_lang = 0x40059558 );\nPROVIDE ( localeconv = 0x4005957c );\nPROVIDE ( _localeconv_r = 0x40059560 );\nPROVIDE ( __locale_mb_cur_max = 0x40059548 );\nPROVIDE ( __locale_msgcharset = 0x40059550 );\nPROVIDE ( localtime = 0x400595dc );\nPROVIDE ( localtime_r = 0x400595fc );\nPROVIDE ( _lock_acquire = 0x4000be14 );\nPROVIDE ( _lock_acquire_recursive = 0x4000be28 );\nPROVIDE ( _lock_close = 0x4000bdec );\nPROVIDE ( _lock_close_recursive = 0x4000be00 );\nPROVIDE ( _lock_init = 0x4000bdc4 );\nPROVIDE ( _lock_init_recursive = 0x4000bdd8 );\nPROVIDE ( _lock_release = 0x4000be64 );\nPROVIDE ( _lock_release_recursive = 0x4000be78 );\nPROVIDE ( _lock_try_acquire = 0x4000be3c );\nPROVIDE ( _lock_try_acquire_recursive = 0x4000be50 );\nPROVIDE ( longjmp = 0x400562cc );\nPROVIDE ( _lseek_r = 0x4000bd8c );\nPROVIDE ( __lshrdi3 = 0x4000c84c );\nPROVIDE ( __ltdf2 = 0x40063790 );\nPROVIDE ( __ltsf2 = 0x4006342c );\nPROVIDE ( malloc = 0x4000bea0 );\nPROVIDE ( _malloc_r = 0x4000bbb4 );\nPROVIDE ( maxSecretKey_256 = 0x3ff97448 );\nPROVIDE ( __mb_cur_max = 0x3ff96530 );\nPROVIDE ( MD5Final = 0x4005db1c );\nPROVIDE ( MD5Init = 0x4005da7c );\nPROVIDE ( MD5Update = 0x4005da9c );\nPROVIDE ( md5_vector = 0x4005db80 );\nPROVIDE ( memccpy = 0x4000c220 );\nPROVIDE ( memchr = 0x4000c244 );\nPROVIDE ( memcmp = 0x4000c260 );\nPROVIDE ( memcpy = 0x4000c2c8 );\nPROVIDE ( memmove = 0x4000c3c0 );\nPROVIDE ( memrchr = 0x4000c400 );\nPROVIDE ( memset = 0x4000c44c );\nPROVIDE ( mktime = 0x4005a5e8 );\nPROVIDE ( mmu_init = 0x400095a4 );\nPROVIDE ( __moddi3 = 0x4000cd4c );\nPROVIDE ( __modsi3 = 0x4000c7c0 );\nPROVIDE ( __month_lengths = 0x3ff9609c );\nPROVIDE ( __muldc3 = 0x40063bf4 );\nPROVIDE ( __muldf3 = 0x4006358c );\nPROVIDE ( __muldi3 = 0x4000c9fc );\nPROVIDE ( __mulsc3 = 0x40063934 );\nPROVIDE ( __mulsf3 = 0x400632c8 );\nPROVIDE ( __mulsi3 = 0x4000c7b0 );\nPROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 );\nPROVIDE ( MultiplyBigHexModP256 = 0x400160b8 );\nPROVIDE ( MultiplyByU32ModP256 = 0x40015fdc );\nPROVIDE ( multofup = 0x4000ab8c );\nPROVIDE ( __mulvdi3 = 0x40002d78 );\nPROVIDE ( __mulvsi3 = 0x40002d60 );\nPROVIDE ( mz_adler32 = 0x4005edbc );\nPROVIDE ( mz_crc32 = 0x4005ee88 );\nPROVIDE ( mz_free = 0x4005eed4 );\nPROVIDE ( __nedf2 = 0x400636a8 );\nPROVIDE ( __negdf2 = 0x400634a0 );\nPROVIDE ( __negdi2 = 0x4000ca14 );\nPROVIDE ( __negsf2 = 0x400020c0 );\nPROVIDE ( __negvdi2 = 0x40002e98 );\nPROVIDE ( __negvsi2 = 0x40002e78 );\nPROVIDE ( __nesf2 = 0x40063374 );\nPROVIDE ( notEqual256 = 0x40015b04 );\nPROVIDE ( __nsau_data = 0x3ff96544 );\nPROVIDE ( one_bits = 0x3ff971f8 );\nPROVIDE ( open = 0x4000178c );\nPROVIDE ( _open_r = 0x4000bd54 );\nPROVIDE ( __paritysi2 = 0x40002f3c );\nPROVIDE ( pbkdf2_sha1 = 0x40060ba4 );\nPROVIDE ( phy_get_romfuncs = 0x40004100 );\nPROVIDE ( __popcountdi2 = 0x40002ef8 );\nPROVIDE ( __popcountsi2 = 0x40002ed0 );\nPROVIDE ( __popcount_tab = 0x3ff96544 );\nPROVIDE ( __powidf2 = 0x400638d4 );\nPROVIDE ( __powisf2 = 0x4006389c );\nPROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 );\nPROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c );\nPROVIDE ( qsort = 0x40056424 );\nPROVIDE ( _raise_r = 0x4000bc70 );\nPROVIDE ( rand = 0x40001058 );\nPROVIDE ( rand_r = 0x400010d4 );\nPROVIDE ( r_btdm_option_data = 0x3ffae6e0 );\nPROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 );\nPROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 );\nPROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 );\nPROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 );\nPROVIDE ( r_bt_util_buf_init = 0x400100e4 );\nPROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 );\nPROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec );\nPROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 );\nPROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 );\nPROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 );\nPROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c );\nPROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec );\nPROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 );\nPROVIDE ( rc4_skip = 0x40060928 );\nPROVIDE ( r_co_bdaddr_compare = 0x40014324 );\nPROVIDE ( r_co_bytes_to_string = 0x400142e4 );\nPROVIDE ( r_co_list_check_size_available = 0x400142c4 );\nPROVIDE ( r_co_list_extract = 0x4001404c );\nPROVIDE ( r_co_list_extract_after = 0x40014118 );\nPROVIDE ( r_co_list_find = 0x4001419c );\nPROVIDE ( r_co_list_init = 0x40013f14 );\nPROVIDE ( r_co_list_insert_after = 0x40014254 );\nPROVIDE ( r_co_list_insert_before = 0x40014200 );\nPROVIDE ( r_co_list_merge = 0x400141bc );\nPROVIDE ( r_co_list_pool_init = 0x40013f30 );\nPROVIDE ( r_co_list_pop_front = 0x40014028 );\nPROVIDE ( r_co_list_push_back = 0x40013fb8 );\nPROVIDE ( r_co_list_push_front = 0x40013ff4 );\nPROVIDE ( r_co_list_size = 0x400142ac );\nPROVIDE ( r_co_nb_good_channels = 0x40014360 );\nPROVIDE ( r_co_slot_to_duration = 0x40014348 );\nPROVIDE ( r_dbg_init = 0x40014394 );\nPROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 );\nPROVIDE ( r_dbg_swdiag_init = 0x40014470 );\nPROVIDE ( r_dbg_swdiag_read = 0x400144a4 );\nPROVIDE ( r_dbg_swdiag_write = 0x400144d0 );\nPROVIDE ( r_E1 = 0x400108e8 );\nPROVIDE ( r_E21 = 0x40010968 );\nPROVIDE ( r_E22 = 0x400109b4 );\nPROVIDE ( r_E3 = 0x40010a58 );\nPROVIDE ( r_ea_alarm_clear = 0x40015ab4 );\nPROVIDE ( r_ea_alarm_set = 0x40015a10 );\nPROVIDE ( read = 0x400017dc );\nPROVIDE ( _read_r = 0x4000bda8 );\nPROVIDE ( r_ea_elt_cancel = 0x400150d0 );\nPROVIDE ( r_ea_elt_create = 0x40015264 );\nPROVIDE ( r_ea_elt_insert = 0x400152a8 );\nPROVIDE ( r_ea_elt_remove = 0x400154f0 );\nPROVIDE ( r_ea_finetimer_isr = 0x400155d4 );\nPROVIDE ( r_ea_init = 0x40015228 );\nPROVIDE ( r_ea_interval_create = 0x4001555c );\nPROVIDE ( r_ea_interval_delete = 0x400155a8 );\nPROVIDE ( r_ea_interval_duration_req = 0x4001597c );\nPROVIDE ( r_ea_interval_insert = 0x4001557c );\nPROVIDE ( r_ea_interval_remove = 0x40015590 );\nPROVIDE ( realloc = 0x4000becc );\nPROVIDE ( _realloc_r = 0x4000bbe0 );\nPROVIDE ( r_ea_offset_req = 0x40015748 );\nPROVIDE ( r_ea_sleep_check = 0x40015928 );\nPROVIDE ( r_ea_sw_isr = 0x40015724 );\nPROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 );\nPROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 );\nPROVIDE ( r_ecc_abort_key256_generation = 0x40017070 );\nPROVIDE ( r_ecc_generate_key256 = 0x40016e00 );\nPROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 );\nPROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 );\nPROVIDE ( r_ecc_get_debug_Keys = 0x40017224 );\nPROVIDE ( r_ecc_init = 0x40016dbc );\nPROVIDE ( RecvBuff = 0x3ffe009c );\nPROVIDE ( r_em_buf_init = 0x4001729c );\nPROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 );\nPROVIDE ( r_em_buf_rx_free = 0x400173c4 );\nPROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 );\nPROVIDE ( r_em_buf_tx_free = 0x4001741c );\nPROVIDE ( _rename_r = 0x4000bc28 );\nPROVIDE ( r_F1_256 = 0x400133e4 );\nPROVIDE ( r_F2_256 = 0x40013568 );\nPROVIDE ( r_F3_256 = 0x40013664 );\nPROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c );\nPROVIDE ( r_G_256 = 0x40013470 );\nPROVIDE ( r_H3 = 0x40013760 );\nPROVIDE ( r_H4 = 0x40013830 );\nPROVIDE ( r_h4tl_init = 0x40017878 );\nPROVIDE ( r_h4tl_start = 0x40017924 );\nPROVIDE ( r_h4tl_stop = 0x40017934 );\nPROVIDE ( r_h4tl_write = 0x400178d0 );\nPROVIDE ( r_H5 = 0x400138dc );\nPROVIDE ( r_hashConcat = 0x40013a38 );\nPROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c );\nPROVIDE ( r_hci_acl_tx_data_received = 0x40019654 );\nPROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 );\nPROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac );\nPROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c );\nPROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 );\nPROVIDE ( r_hci_cmd_received = 0x400192f8 );\nPROVIDE ( r_hci_evt_filter_add = 0x40018a64 );\nPROVIDE ( r_hci_evt_mask_set = 0x400189e4 );\nPROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 );\nPROVIDE ( r_hci_fc_acl_en = 0x400179d8 );\nPROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c );\nPROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 );\nPROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 );\nPROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c );\nPROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 );\nPROVIDE ( r_hci_fc_init = 0x40017974 );\nPROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 );\nPROVIDE ( r_hci_fc_sync_en = 0x40017a30 );\nPROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 );\nPROVIDE ( r_hci_init = 0x40018538 );\nPROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 );\nPROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 );\nPROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 );\nPROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 );\nPROVIDE ( r_hci_reset = 0x4001856c );\nPROVIDE ( r_hci_send_2_host = 0x400185bc );\nPROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 );\nPROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 );\nPROVIDE ( r_hci_tl_init = 0x40019290 );\nPROVIDE ( r_hci_tl_send = 0x40019228 );\nPROVIDE ( r_hci_util_pack = 0x40019874 );\nPROVIDE ( r_hci_util_unpack = 0x40019998 );\nPROVIDE ( r_hci_voice_settings_get = 0x40018bdc );\nPROVIDE ( r_hci_voice_settings_set = 0x40018be8 );\nPROVIDE ( r_HMAC = 0x40013968 );\nPROVIDE ( r_import_rf_phy_func = 0x3ffb8354 );\nPROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 );\nPROVIDE ( r_ip_funcs = 0x3ffae710 );\nPROVIDE ( r_ip_funcs_p = 0x3ffae70c );\nPROVIDE ( r_ke_check_malloc = 0x40019de0 );\nPROVIDE ( r_ke_event_callback_set = 0x40019ba8 );\nPROVIDE ( r_ke_event_clear = 0x40019c2c );\nPROVIDE ( r_ke_event_flush = 0x40019ccc );\nPROVIDE ( r_ke_event_get = 0x40019c78 );\nPROVIDE ( r_ke_event_get_all = 0x40019cc0 );\nPROVIDE ( r_ke_event_init = 0x40019b90 );\nPROVIDE ( r_ke_event_schedule = 0x40019cdc );\nPROVIDE ( r_ke_event_set = 0x40019be0 );\nPROVIDE ( r_ke_flush = 0x4001a374 );\nPROVIDE ( r_ke_free = 0x4001a014 );\nPROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 );\nPROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 );\nPROVIDE ( r_ke_init = 0x4001a318 );\nPROVIDE ( r_ke_is_free = 0x4001a184 );\nPROVIDE ( r_ke_malloc = 0x40019eb4 );\nPROVIDE ( r_ke_mem_init = 0x40019d3c );\nPROVIDE ( r_ke_mem_is_empty = 0x40019d8c );\nPROVIDE ( r_ke_msg_alloc = 0x4001a1e0 );\nPROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 );\nPROVIDE ( r_ke_msg_discard = 0x4001a850 );\nPROVIDE ( r_ke_msg_forward = 0x4001a290 );\nPROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac );\nPROVIDE ( r_ke_msg_free = 0x4001a2cc );\nPROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 );\nPROVIDE ( r_ke_msg_save = 0x4001a858 );\nPROVIDE ( r_ke_msg_send = 0x4001a234 );\nPROVIDE ( r_ke_msg_send_basic = 0x4001a26c );\nPROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec );\nPROVIDE ( r_ke_queue_extract = 0x40055fd0 );\nPROVIDE ( r_ke_queue_insert = 0x40056020 );\nPROVIDE ( r_ke_sleep_check = 0x4001a3d8 );\nPROVIDE ( r_ke_state_get = 0x4001a7d8 );\nPROVIDE ( r_ke_state_set = 0x4001a6fc );\nPROVIDE ( r_ke_stats_get = 0x4001a3f0 );\nPROVIDE ( r_ke_task_check = 0x4001a8a4 );\nPROVIDE ( r_ke_task_create = 0x4001a674 );\nPROVIDE ( r_ke_task_delete = 0x4001a6c0 );\nPROVIDE ( r_ke_task_init = 0x4001a650 );\nPROVIDE ( r_ke_task_msg_flush = 0x4001a860 );\nPROVIDE ( r_ke_timer_active = 0x4001ac08 );\nPROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 );\nPROVIDE ( r_ke_timer_clear = 0x4001ab90 );\nPROVIDE ( r_ke_timer_init = 0x4001aa9c );\nPROVIDE ( r_ke_timer_set = 0x4001aac0 );\nPROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 );\nPROVIDE ( r_KPrimC = 0x40010ad4 );\nPROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 );\nPROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 );\nPROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 );\nPROVIDE ( r_lb_init = 0x4001acd4 );\nPROVIDE ( r_lb_mst_key = 0x4001afc0 );\nPROVIDE ( r_lb_mst_key_cmp = 0x4001af74 );\nPROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 );\nPROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 );\nPROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c );\nPROVIDE ( r_lb_reset = 0x4001ad38 );\nPROVIDE ( r_lb_send_lmp = 0x4001adbc );\nPROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c );\nPROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 );\nPROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 );\nPROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 );\nPROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c );\nPROVIDE ( r_lc_afh_set = 0x4001cc74 );\nPROVIDE ( r_lc_afh_start = 0x4001d240 );\nPROVIDE ( r_lc_auth_cmp = 0x4001cd54 );\nPROVIDE ( r_lc_calc_link_key = 0x4001ce7c );\nPROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 );\nPROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc );\nPROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac );\nPROVIDE ( r_lc_chk_to = 0x4001d2a8 );\nPROVIDE ( r_lc_cmd_stat_send = 0x4001c914 );\nPROVIDE ( r_lc_comb_key_svr = 0x4001d30c );\nPROVIDE ( r_lc_con_cmp = 0x4001d44c );\nPROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc );\nPROVIDE ( r_lc_conn_seq_done = 0x40021334 );\nPROVIDE ( r_lc_detach = 0x4002037c );\nPROVIDE ( r_lc_dhkey = 0x4001d564 );\nPROVIDE ( r_lc_enc_cmp = 0x4001d8bc );\nPROVIDE ( r_lc_enc_key_refresh = 0x4001d720 );\nPROVIDE ( r_lc_end_chk_colli = 0x4001d858 );\nPROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 );\nPROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 );\nPROVIDE ( r_lc_epr_change_lk = 0x4001db38 );\nPROVIDE ( r_lc_epr_cmp = 0x4001da88 );\nPROVIDE ( r_lc_epr_resp = 0x4001e0b4 );\nPROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 );\nPROVIDE ( r_lc_ext_feat = 0x40020d6c );\nPROVIDE ( r_lc_feat = 0x40020984 );\nPROVIDE ( r_lc_hl_connect = 0x400209e8 );\nPROVIDE ( r_lc_init = 0x4001c948 );\nPROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 );\nPROVIDE ( r_lc_initiator_epr = 0x4001e064 );\nPROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 );\nPROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 );\nPROVIDE ( r_lc_key_exch_end = 0x4001e140 );\nPROVIDE ( r_lc_legacy_pair = 0x4001e1c0 );\nPROVIDE ( r_lc_local_switch = 0x4001e22c );\nPROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 );\nPROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 );\nPROVIDE ( r_lc_loc_auth = 0x40020ecc );\nPROVIDE ( r_lc_locepr_lkref = 0x4001d648 );\nPROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 );\nPROVIDE ( r_lc_loc_sniff = 0x40020a6c );\nPROVIDE ( r_lc_max_slot_mgt = 0x4001e410 );\nPROVIDE ( r_lc_mst_key = 0x4001e7c0 );\nPROVIDE ( r_lc_mst_qos_done = 0x4001ea80 );\nPROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 );\nPROVIDE ( r_lc_mutual_auth_end = 0x4001e670 );\nPROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 );\nPROVIDE ( r_lc_packet_type = 0x40021038 );\nPROVIDE ( r_lc_pair = 0x40020ddc );\nPROVIDE ( r_lc_pairing_cont = 0x4001eafc );\nPROVIDE ( r_lc_passkey_comm = 0x4001ed20 );\nPROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 );\nPROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec );\nPROVIDE ( r_lc_ptt = 0x4001ee2c );\nPROVIDE ( r_lc_ptt_cmp = 0x4001eeec );\nPROVIDE ( r_lc_qos_setup = 0x4001ef50 );\nPROVIDE ( r_lc_rd_rem_name = 0x4001efd0 );\nPROVIDE ( r_lc_release = 0x4001f8a8 );\nPROVIDE ( r_lc_rem_enc = 0x4001f124 );\nPROVIDE ( r_lc_rem_name_cont = 0x4001f290 );\nPROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 );\nPROVIDE ( r_lc_rem_sniff = 0x40020ca4 );\nPROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 );\nPROVIDE ( r_lc_rem_switch = 0x4001f070 );\nPROVIDE ( r_lc_rem_trans_mode = 0x4001f314 );\nPROVIDE ( r_lc_rem_unsniff = 0x400207a0 );\nPROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c );\nPROVIDE ( r_lc_reset = 0x4001c99c );\nPROVIDE ( r_lc_resp_auth = 0x4001f518 );\nPROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 );\nPROVIDE ( r_lc_resp_num_comp = 0x40020074 );\nPROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 );\nPROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c );\nPROVIDE ( r_lc_resp_pair = 0x400208a4 );\nPROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 );\nPROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c );\nPROVIDE ( r_lc_restart_enc = 0x4001f8ec );\nPROVIDE ( r_lc_restart_enc_cont = 0x4001f940 );\nPROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 );\nPROVIDE ( r_lc_restore_to = 0x4001f9e0 );\nPROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 );\nPROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 );\nPROVIDE ( r_lc_rsw_done = 0x4001db94 );\nPROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 );\nPROVIDE ( r_lc_sco_detach = 0x40021e40 );\nPROVIDE ( r_lc_sco_host_accept = 0x40022118 );\nPROVIDE ( r_lc_sco_host_reject = 0x400222b8 );\nPROVIDE ( r_lc_sco_host_request = 0x40021f4c );\nPROVIDE ( r_lc_sco_host_request_disc = 0x4002235c );\nPROVIDE ( r_lc_sco_init = 0x40021dc8 );\nPROVIDE ( r_lc_sco_peer_accept = 0x40022780 );\nPROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 );\nPROVIDE ( r_lc_sco_peer_reject = 0x40022824 );\nPROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c );\nPROVIDE ( r_lc_sco_peer_request = 0x4002240c );\nPROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec );\nPROVIDE ( r_lc_sco_release = 0x40021eec );\nPROVIDE ( r_lc_sco_reset = 0x40021dfc );\nPROVIDE ( r_lc_sco_timeout = 0x40022bd4 );\nPROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec );\nPROVIDE ( r_lc_semi_key_cmp = 0x40020294 );\nPROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c );\nPROVIDE ( r_lc_send_enc_mode = 0x40020220 );\nPROVIDE ( r_lc_send_lmp = 0x4001c1a8 );\nPROVIDE ( r_lc_send_pdu_acc = 0x4001c21c );\nPROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 );\nPROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 );\nPROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 );\nPROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c );\nPROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 );\nPROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 );\nPROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 );\nPROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 );\nPROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 );\nPROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 );\nPROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 );\nPROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec );\nPROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 );\nPROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 );\nPROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c );\nPROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c );\nPROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 );\nPROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec );\nPROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c );\nPROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 );\nPROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 );\nPROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 );\nPROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 );\nPROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 );\nPROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c );\nPROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 );\nPROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 );\nPROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 );\nPROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 );\nPROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 );\nPROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 );\nPROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 );\nPROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 );\nPROVIDE ( r_lc_send_pdu_sres = 0x4001c548 );\nPROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc );\nPROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 );\nPROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 );\nPROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 );\nPROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc );\nPROVIDE ( r_lc_sniff_init = 0x40022cac );\nPROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 );\nPROVIDE ( r_lc_sniff_reset = 0x40022cc8 );\nPROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 );\nPROVIDE ( r_lc_sniff_sub_mode = 0x400204fc );\nPROVIDE ( r_lc_sp_end = 0x400213a8 );\nPROVIDE ( r_lc_sp_fail = 0x40020470 );\nPROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc );\nPROVIDE ( r_lc_ssr_nego = 0x4002125c );\nPROVIDE ( r_lc_start = 0x4001ca28 );\nPROVIDE ( r_lc_start_enc = 0x4001fb28 );\nPROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c );\nPROVIDE ( r_lc_start_key_exch = 0x4001fe10 );\nPROVIDE ( r_lc_start_lmp_to = 0x4001fae8 );\nPROVIDE ( r_lc_start_oob = 0x4001fffc );\nPROVIDE ( r_lc_start_passkey = 0x4001feac );\nPROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 );\nPROVIDE ( r_lc_stop_afh_report = 0x40020184 );\nPROVIDE ( r_lc_stop_enc = 0x40020110 );\nPROVIDE ( r_lc_switch_cmp = 0x40020448 );\nPROVIDE ( r_lc_unit_key_svr = 0x400206d8 );\nPROVIDE ( r_lc_unsniff = 0x40020c50 );\nPROVIDE ( r_lc_unsniff_cmp = 0x40020810 );\nPROVIDE ( r_lc_unsniff_cont = 0x40020750 );\nPROVIDE ( r_lc_upd_to = 0x4002065c );\nPROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 );\nPROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac );\nPROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 );\nPROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c );\nPROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 );\nPROVIDE ( r_lc_version = 0x40020a30 );\nPROVIDE ( lmp_accepted_ext_handler = 0x40027290 );\nPROVIDE ( lmp_not_accepted_ext_handler = 0x40029c54 );\nPROVIDE ( lmp_clk_adj_handler = 0x40027468 );\nPROVIDE ( lmp_clk_adj_ack_handler = 0x400274f4 );\nPROVIDE ( lmp_clk_adj_req_handler = 0x4002751c );\nPROVIDE ( lmp_feats_res_ext_handler = 0x4002cac4 );\nPROVIDE ( lmp_feats_req_ext_handler = 0x4002ccb0 );\nPROVIDE ( lmp_pkt_type_tbl_req_handler = 0x40027574 );\nPROVIDE ( lmp_esco_link_req_handler = 0x40027610 );\nPROVIDE ( lmp_rmv_esco_link_req_handler = 0x400276e8 );\nPROVIDE ( lmp_ch_class_req_handler = 0x40027730 );\nPROVIDE ( lmp_ch_class_handler = 0x4002ca18 );\nPROVIDE ( lmp_ssr_req_handler = 0x4002780c );\nPROVIDE ( lmp_ssr_res_handler = 0x40027900 );\nPROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );\nPROVIDE ( lmp_pause_enc_req_handler = 0x4002df90 );\nPROVIDE ( lmp_resume_enc_req_handler = 0x4002e084 );\nPROVIDE ( lmp_num_comparison_fail_handler = 0x40027a74 );\nPROVIDE ( lmp_passkey_fail_handler = 0x40027aec );\nPROVIDE ( lmp_keypress_notif_handler = 0x4002c5c8 );\nPROVIDE ( lmp_pwr_ctrl_req_handler = 0x400263bc );\nPROVIDE ( lmp_pwr_ctrl_res_handler = 0x40026480 );\nPROVIDE ( lmp_auto_rate_handler = 0x40026548 );\nPROVIDE ( lmp_pref_rate_handler = 0x4002657c );\nPROVIDE ( lmp_name_req_handler = 0x40025050 );\nPROVIDE ( lmp_name_res_handler = 0x400250bc );\nPROVIDE ( lmp_not_accepted_handler = 0x400251d0 );\nPROVIDE ( lmp_accepted_handler = 0x4002e894 );\nPROVIDE ( lmp_clk_off_req_handler = 0x40025a44 );\nPROVIDE ( lmp_clk_off_res_handler = 0x40025ab8 );\nPROVIDE ( lmp_detach_handler = 0x40025b74 );\nPROVIDE ( lmp_tempkey_handler = 0x4002b6b0 );\nPROVIDE ( lmp_temprand_handler = 0x4002b74c );\nPROVIDE ( lmp_sres_handler = 0x4002b840 );\nPROVIDE ( lmp_aurand_handler = 0x4002bda0 );\nPROVIDE ( lmp_unitkey_handler = 0x4002c13c );\nPROVIDE ( lmp_combkey_handler = 0x4002c234 );\nPROVIDE ( lmp_inrand_handler = 0x4002c414 );\nPROVIDE ( lmp_oob_fail_handler = 0x40027b84 );\nPROVIDE ( lmp_ping_req_handler = 0x40027c08 );\nPROVIDE ( lmp_ping_res_handler = 0x40027c5c );\nPROVIDE ( lmp_enc_mode_req_handler = 0x40025c60 );\nPROVIDE ( lmp_enc_key_size_req_handler = 0x40025e54 );\nPROVIDE ( lmp_switch_req_handler = 0x40025f84 );\nPROVIDE ( lmp_start_enc_req_handler = 0x4002e124 );\nPROVIDE ( lmp_stop_enc_req_handler = 0x4002de30 );\nPROVIDE ( lmp_sniff_req_handler = 0x400260c8 );\nPROVIDE ( lmp_unsniff_req_handler = 0x400261e0 );\nPROVIDE ( lmp_incr_pwr_req_handler = 0x4002629c );\nPROVIDE ( lmp_decr_pwr_req_handler = 0x400262f8 );\nPROVIDE ( lmp_max_pwr_handler = 0x40026354 );\nPROVIDE ( lmp_min_pwr_handler = 0x40026388 );\nPROVIDE ( lmp_ver_req_handler = 0x400265f0 );\nPROVIDE ( lmp_ver_res_handler = 0x40026670 );\nPROVIDE ( lmp_qos_handler = 0x40026790 );\nPROVIDE ( lmp_qos_req_handler = 0x40026844 );\nPROVIDE ( lmp_sco_link_req_handler = 0x40026930 );\nPROVIDE ( lmp_rmv_sco_link_req_handler = 0x40026a10 );\nPROVIDE ( lmp_max_slot_handler = 0x40026a54 );\nPROVIDE ( lmp_max_slot_req_handler = 0x40026aac );\nPROVIDE ( lmp_timing_accu_req_handler = 0x40026b54 );\nPROVIDE ( lmp_timing_accu_res_handler = 0x40026bcc );\nPROVIDE ( lmp_setup_cmp_handler = 0x40026c84 );\nPROVIDE ( lmp_feats_res_handler = 0x4002b548 );\nPROVIDE ( lmp_feats_req_handler = 0x4002b620 );\nPROVIDE ( lmp_host_con_req_handler = 0x4002b3d8 );\nPROVIDE ( lmp_use_semi_perm_key_handler = 0x4002b4c4 );\nPROVIDE ( lmp_slot_off_handler = 0x40026cc8 );\nPROVIDE ( lmp_page_mode_req_handler = 0x40026d0c );\nPROVIDE ( lmp_page_scan_mode_req_handler = 0x40026d4c );\nPROVIDE ( lmp_supv_to_handler = 0x40026d94 );\nPROVIDE ( lmp_test_activate_handler = 0x40026e7c );\nPROVIDE ( lmp_test_ctrl_handler = 0x40026ee4 );\nPROVIDE ( lmp_enc_key_size_mask_req_handler = 0x40027038 );\nPROVIDE ( lmp_enc_key_size_mask_res_handler = 0x400270a4 );\nPROVIDE ( lmp_set_afh_handler = 0x4002b2e4 );\nPROVIDE ( lmp_encaps_hdr_handler = 0x40027120 );\nPROVIDE ( lmp_encaps_payl_handler = 0x4002e590 );\nPROVIDE ( lmp_sp_nb_handler = 0x4002acf0 );\nPROVIDE ( lmp_sp_cfm_handler = 0x4002b170 );\nPROVIDE ( lmp_dhkey_chk_handler = 0x4002ab48 );\nPROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );\nPROVIDE ( lmp_io_cap_res_handler = 0x4002c670 );\nPROVIDE ( lmp_io_cap_req_handler = 0x4002c7a4 );\nPROVIDE ( ld_acl_tx_packet_type_select = 0x4002fb40 );\nPROVIDE ( ld_acl_sched = 0x40033268 );\nPROVIDE ( ld_acl_sniff_sched = 0x4003340c );\nPROVIDE ( lm_cmd_cmp_send = 0x40051838 );\nPROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 );\nPROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 );\nPROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 );\nPROVIDE ( r_ld_acl_afh_set = 0x40036b60 );\nPROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 );\nPROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 );\nPROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 );\nPROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 );\nPROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 );\nPROVIDE ( r_ld_acl_clk_set = 0x40036950 );\nPROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 );\nPROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 );\nPROVIDE ( r_ld_acl_data_flush = 0x400357bc );\nPROVIDE ( r_ld_acl_data_tx = 0x4003544c );\nPROVIDE ( r_ld_acl_edr_set = 0x4003678c );\nPROVIDE ( r_ld_acl_enc_key_load = 0x40036404 );\nPROVIDE ( r_ld_acl_flow_off = 0x40035400 );\nPROVIDE ( r_ld_acl_flow_on = 0x4003541c );\nPROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c );\nPROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 );\nPROVIDE ( r_ld_acl_init = 0x40034d08 );\nPROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 );\nPROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 );\nPROVIDE ( r_ld_acl_lsto_get = 0x400366b4 );\nPROVIDE ( r_ld_acl_lsto_set = 0x400366f8 );\nPROVIDE ( r_ld_acl_reset = 0x40034d24 );\nPROVIDE ( r_ld_acl_role_get = 0x40036b30 );\nPROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 );\nPROVIDE ( r_ld_acl_rsw_req = 0x40035e74 );\nPROVIDE ( r_ld_acl_rx_enc = 0x40036344 );\nPROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 );\nPROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 );\nPROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c );\nPROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 );\nPROVIDE ( r_ld_acl_sniff = 0x4003617c );\nPROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 );\nPROVIDE ( r_ld_acl_ssr_set = 0x40036274 );\nPROVIDE ( r_ld_acl_start = 0x40034ddc );\nPROVIDE ( r_ld_acl_stop = 0x4003532c );\nPROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 );\nPROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c );\nPROVIDE ( r_ld_acl_t_poll_get = 0x40036024 );\nPROVIDE ( r_ld_acl_t_poll_set = 0x40036068 );\nPROVIDE ( r_ld_acl_tx_enc = 0x400362f8 );\nPROVIDE ( r_ld_acl_unsniff = 0x400361e0 );\nPROVIDE ( r_ld_active_check = 0x4003cac4 );\nPROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec );\nPROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c );\nPROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 );\nPROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc );\nPROVIDE ( r_ld_bcst_acl_start = 0x4003882c );\nPROVIDE ( r_ld_bcst_afh_update = 0x40038f3c );\nPROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c );\nPROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 );\nPROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 );\nPROVIDE ( r_ld_bd_addr_get = 0x4003ca20 );\nPROVIDE ( r_ld_channel_assess = 0x4003c184 );\nPROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 );\nPROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 );\nPROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 );\nPROVIDE ( r_ld_csb_rx_init = 0x40039690 );\nPROVIDE ( r_ld_csb_rx_reset = 0x4003969c );\nPROVIDE ( r_ld_csb_rx_start = 0x4003972c );\nPROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 );\nPROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc );\nPROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c );\nPROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 );\nPROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 );\nPROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 );\nPROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 );\nPROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 );\nPROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 );\nPROVIDE ( r_ld_fm_frame_isr = 0x4003a82c );\nPROVIDE ( r_ld_fm_init = 0x4003a760 );\nPROVIDE ( r_ld_fm_prog_check = 0x4003ab28 );\nPROVIDE ( r_ld_fm_prog_disable = 0x4003a984 );\nPROVIDE ( r_ld_fm_prog_enable = 0x4003a944 );\nPROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 );\nPROVIDE ( r_ld_fm_reset = 0x4003a794 );\nPROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 );\nPROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 );\nPROVIDE ( r_ld_init = 0x4003c294 );\nPROVIDE ( r_ld_inq_init = 0x4003b15c );\nPROVIDE ( r_ld_inq_reset = 0x4003b168 );\nPROVIDE ( r_ld_inq_start = 0x4003b1f0 );\nPROVIDE ( r_ld_inq_stop = 0x4003b4f0 );\nPROVIDE ( r_ld_iscan_eir_get = 0x4003c118 );\nPROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 );\nPROVIDE ( r_ld_iscan_init = 0x4003b9f0 );\nPROVIDE ( r_ld_iscan_reset = 0x4003ba14 );\nPROVIDE ( r_ld_iscan_restart = 0x4003ba44 );\nPROVIDE ( r_ld_iscan_start = 0x4003bb28 );\nPROVIDE ( r_ld_iscan_stop = 0x4003bf1c );\nPROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 );\nPROVIDE ( r_ld_page_init = 0x4003d808 );\nPROVIDE ( r_ld_page_reset = 0x4003d814 );\nPROVIDE ( r_ld_page_start = 0x4003d848 );\nPROVIDE ( r_ld_page_stop = 0x4003da54 );\nPROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 );\nPROVIDE ( r_ld_pca_init = 0x4003deb4 );\nPROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac );\nPROVIDE ( r_ld_pca_local_config = 0x4003df6c );\nPROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 );\nPROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 );\nPROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 );\nPROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 );\nPROVIDE ( r_ld_pca_reset = 0x4003df0c );\nPROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 );\nPROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 );\nPROVIDE ( r_ld_pscan_init = 0x4003f474 );\nPROVIDE ( r_ld_pscan_reset = 0x4003f498 );\nPROVIDE ( r_ld_pscan_restart = 0x4003f4b8 );\nPROVIDE ( r_ld_pscan_start = 0x4003f514 );\nPROVIDE ( r_ld_pscan_stop = 0x4003f618 );\nPROVIDE ( r_ld_read_clock = 0x4003c9e4 );\nPROVIDE ( r_ld_reset = 0x4003c714 );\nPROVIDE ( r_ld_sched_acl_add = 0x4003f978 );\nPROVIDE ( r_ld_sched_acl_remove = 0x4003f99c );\nPROVIDE ( r_ld_sched_compute = 0x4003f6f8 );\nPROVIDE ( r_ld_sched_init = 0x4003f7ac );\nPROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 );\nPROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 );\nPROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 );\nPROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 );\nPROVIDE ( r_ld_sched_page_add = 0x4003f910 );\nPROVIDE ( r_ld_sched_page_remove = 0x4003f938 );\nPROVIDE ( r_ld_sched_pscan_add = 0x4003f828 );\nPROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 );\nPROVIDE ( r_ld_sched_reset = 0x4003f7d4 );\nPROVIDE ( r_ld_sched_sco_add = 0x4003fa4c );\nPROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c );\nPROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 );\nPROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c );\nPROVIDE ( r_ld_sched_sscan_add = 0x4003f868 );\nPROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 );\nPROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 );\nPROVIDE ( r_ld_sco_data_tx = 0x40037ee8 );\nPROVIDE ( r_ld_sco_start = 0x40037110 );\nPROVIDE ( r_ld_sco_stop = 0x40037c40 );\nPROVIDE ( r_ld_sco_update = 0x40037a74 );\nPROVIDE ( r_ld_sscan_activated = 0x4004031c );\nPROVIDE ( r_ld_sscan_init = 0x400402f0 );\nPROVIDE ( r_ld_sscan_reset = 0x400402fc );\nPROVIDE ( r_ld_sscan_start = 0x40040384 );\nPROVIDE ( r_ld_strain_init = 0x400409f4 );\nPROVIDE ( r_ld_strain_reset = 0x40040a00 );\nPROVIDE ( r_ld_strain_start = 0x40040a8c );\nPROVIDE ( r_ld_strain_stop = 0x40040df0 );\nPROVIDE ( r_ld_timing_accuracy_get = 0x4003caac );\nPROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c );\nPROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 );\nPROVIDE ( r_ld_util_bch_create = 0x40040fcc );\nPROVIDE ( r_ld_util_fhs_pk = 0x400411c8 );\nPROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 );\nPROVIDE ( r_ld_util_stp_pk = 0x400413f4 );\nPROVIDE ( r_ld_util_stp_unpk = 0x40041324 );\nPROVIDE ( r_ld_version_get = 0x4003ca6c );\nPROVIDE ( r_ld_wlcoex_set = 0x4003caf8 );\nPROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 );\nPROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c );\nPROVIDE ( r_llc_ch_assess_local = 0x40041494 );\nPROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 );\nPROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 );\nPROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac );\nPROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 );\nPROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c );\nPROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 );\nPROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c );\nPROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 );\nPROVIDE ( r_llc_con_update_complete_send = 0x40044d68 );\nPROVIDE ( r_llc_con_update_finished = 0x4004518c );\nPROVIDE ( r_llc_con_update_ind = 0x40045038 );\nPROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 );\nPROVIDE ( r_llc_end_evt_defer = 0x40046330 );\nPROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c );\nPROVIDE ( r_llc_init = 0x40044778 );\nPROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 );\nPROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 );\nPROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc );\nPROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 );\nPROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 );\nPROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 );\nPROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 );\nPROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 );\nPROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 );\nPROVIDE ( r_llc_llcp_get_autorize = 0x4004475c );\nPROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 );\nPROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac );\nPROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 );\nPROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 );\nPROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c );\nPROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 );\nPROVIDE ( r_llc_llcp_recv_handler = 0x40044678 );\nPROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c );\nPROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c );\nPROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 );\nPROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 );\nPROVIDE ( r_llc_llcp_tester_send = 0x400445e4 );\nPROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 );\nPROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c );\nPROVIDE ( r_llc_lsto_con_update = 0x40045098 );\nPROVIDE ( r_llc_ltk_req_send = 0x40044dc0 );\nPROVIDE ( r_llc_map_update_finished = 0x40045260 );\nPROVIDE ( r_llc_map_update_ind = 0x400450f0 );\nPROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc );\nPROVIDE ( r_llc_pdu_defer = 0x40046528 );\nPROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac );\nPROVIDE ( r_llc_reset = 0x400447b8 );\nPROVIDE ( r_llc_start = 0x400447f4 );\nPROVIDE ( r_llc_stop = 0x400449ac );\nPROVIDE ( r_llc_util_bw_mgt = 0x4004629c );\nPROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 );\nPROVIDE ( r_llc_util_dicon_procedure = 0x40046130 );\nPROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 );\nPROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 );\nPROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 );\nPROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 );\nPROVIDE ( r_llc_util_update_channel_map = 0x400461ac );\nPROVIDE ( r_llc_version_rd_event_send = 0x40044e60 );\nPROVIDE ( r_lld_adv_start = 0x40048b38 );\nPROVIDE ( r_lld_adv_stop = 0x40048ea0 );\nPROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 );\nPROVIDE ( r_lld_con_param_req = 0x40049f0c );\nPROVIDE ( r_lld_con_param_rsp = 0x40049e00 );\nPROVIDE ( r_lld_con_start = 0x400491f8 );\nPROVIDE ( r_lld_con_stop = 0x40049fdc );\nPROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc );\nPROVIDE ( r_lld_con_update_ind = 0x4004a30c );\nPROVIDE ( r_lld_con_update_req = 0x40049b60 );\nPROVIDE ( r_lld_core_reset = 0x40048a9c );\nPROVIDE ( r_lld_crypt_isr = 0x4004a324 );\nPROVIDE ( r_lld_evt_adv_create = 0x400481f4 );\nPROVIDE ( r_lld_evt_canceled = 0x400485c8 );\nPROVIDE ( r_lld_evt_channel_next = 0x40046aac );\nPROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc );\nPROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 );\nPROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c );\nPROVIDE ( r_lld_evt_drift_compute = 0x40047670 );\nPROVIDE ( r_lld_evt_elt_delete = 0x40047538 );\nPROVIDE ( r_lld_evt_elt_insert = 0x400474c8 );\nPROVIDE ( r_lld_evt_end = 0x400483e8 );\nPROVIDE ( r_lld_evt_end_isr = 0x4004862c );\nPROVIDE ( r_lld_evt_init = 0x40046b3c );\nPROVIDE ( r_lld_evt_init_evt = 0x40046cd0 );\nPROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 );\nPROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 );\nPROVIDE ( r_lld_evt_prevent_stop = 0x40047adc );\nPROVIDE ( r_lld_evt_restart = 0x40046d50 );\nPROVIDE ( r_lld_evt_rx = 0x40048578 );\nPROVIDE ( r_lld_evt_rx_isr = 0x40048678 );\nPROVIDE ( r_lld_evt_scan_create = 0x40047ae8 );\nPROVIDE ( r_lld_evt_schedule = 0x40047908 );\nPROVIDE ( r_lld_evt_schedule_next = 0x400477dc );\nPROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 );\nPROVIDE ( r_lld_evt_slave_update = 0x40048138 );\nPROVIDE ( r_lld_evt_update_create = 0x40047cd8 );\nPROVIDE ( r_lld_get_mode = 0x40049ff8 );\nPROVIDE ( r_lld_init = 0x4004873c );\nPROVIDE ( r_lld_move_to_master = 0x400499e0 );\nPROVIDE ( r_lld_move_to_slave = 0x4004a024 );\nPROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 );\nPROVIDE ( r_lld_pdu_check = 0x4004ac34 );\nPROVIDE ( r_lld_pdu_data_send = 0x4004b018 );\nPROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc );\nPROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 );\nPROVIDE ( r_lld_pdu_send_packet = 0x4004b774 );\nPROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 );\nPROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 );\nPROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 );\nPROVIDE ( r_lld_pdu_tx_push = 0x4004b080 );\nPROVIDE ( r_lld_ral_renew_req = 0x4004a73c );\nPROVIDE ( r_lld_scan_start = 0x40048ee0 );\nPROVIDE ( r_lld_scan_stop = 0x40049190 );\nPROVIDE ( r_lld_test_mode_rx = 0x4004a540 );\nPROVIDE ( r_lld_test_mode_tx = 0x4004a350 );\nPROVIDE ( r_lld_test_stop = 0x4004a710 );\nPROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc );\nPROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c );\nPROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 );\nPROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 );\nPROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 );\nPROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 );\nPROVIDE ( r_lld_util_flush_list = 0x4004bbd8 );\nPROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 );\nPROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac );\nPROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 );\nPROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 );\nPROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 );\nPROVIDE ( r_lld_util_instant_get = 0x4004b890 );\nPROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc );\nPROVIDE ( r_lld_util_priority_set = 0x4004bd10 );\nPROVIDE ( r_lld_util_priority_update = 0x4004bd78 );\nPROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 );\nPROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 );\nPROVIDE ( r_lld_wlcoex_set = 0x4004bd98 );\nPROVIDE ( r_llm_ble_ready = 0x4004cc34 );\nPROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 );\nPROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 );\nPROVIDE ( r_llm_con_req_ind = 0x4004cc54 );\nPROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 );\nPROVIDE ( r_llm_create_con = 0x4004de78 );\nPROVIDE ( r_llm_encryption_done = 0x4004dff8 );\nPROVIDE ( r_llm_encryption_start = 0x4004e128 );\nPROVIDE ( r_llm_end_evt_defer = 0x4004eb6c );\nPROVIDE ( r_llm_init = 0x4004c9f8 );\nPROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 );\nPROVIDE ( r_llm_pdu_defer = 0x4004ec48 );\nPROVIDE ( r_llm_ral_clear = 0x4004e1fc );\nPROVIDE ( r_llm_ral_dev_add = 0x4004e23c );\nPROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc );\nPROVIDE ( r_llm_ral_get_rpa = 0x4004e400 );\nPROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 );\nPROVIDE ( r_llm_ral_update = 0x4004e4f8 );\nPROVIDE ( r_llm_set_adv_data = 0x4004d960 );\nPROVIDE ( r_llm_set_adv_en = 0x4004d7ec );\nPROVIDE ( r_llm_set_adv_param = 0x4004d5f4 );\nPROVIDE ( r_llm_set_scan_en = 0x4004db64 );\nPROVIDE ( r_llm_set_scan_param = 0x4004dac8 );\nPROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 );\nPROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 );\nPROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc );\nPROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc );\nPROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 );\nPROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 );\nPROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 );\nPROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 );\nPROVIDE ( r_llm_util_bl_add = 0x4004e9ac );\nPROVIDE ( r_llm_util_bl_check = 0x4004e930 );\nPROVIDE ( r_llm_util_bl_rem = 0x4004ea70 );\nPROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 );\nPROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 );\nPROVIDE ( r_llm_util_check_map_validity = 0x4004e800 );\nPROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 );\nPROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 );\nPROVIDE ( r_llm_util_set_public_addr = 0x4004e89c );\nPROVIDE ( r_llm_wl_clr = 0x4004dc54 );\nPROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 );\nPROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 );\nPROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc );\nPROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 );\nPROVIDE ( r_lm_acl_disc = 0x4004f148 );\nPROVIDE ( r_LM_AddSniff = 0x40022d20 );\nPROVIDE ( r_lm_add_sync = 0x40051358 );\nPROVIDE ( r_lm_afh_activate_timer = 0x4004f444 );\nPROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 );\nPROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 );\nPROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c );\nPROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 );\nPROVIDE ( r_lm_check_active_sync = 0x40051334 );\nPROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c );\nPROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 );\nPROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c );\nPROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 );\nPROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 );\nPROVIDE ( r_LM_ComputePacketType = 0x4002f554 );\nPROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac );\nPROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 );\nPROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 );\nPROVIDE ( r_lm_dhkey_calc_init = 0x40013234 );\nPROVIDE ( r_lm_dhkey_compare = 0x400132d8 );\nPROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec );\nPROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 );\nPROVIDE ( r_lm_f1 = 0x40012bb8 );\nPROVIDE ( r_lm_f2 = 0x40012cfc );\nPROVIDE ( r_lm_f3 = 0x40013050 );\nPROVIDE ( r_lm_g = 0x40012f90 );\nPROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c );\nPROVIDE ( r_lm_get_auth_en = 0x4004f1ac );\nPROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c );\nPROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 );\nPROVIDE ( r_LM_GetFeature = 0x4002f924 );\nPROVIDE ( r_LM_GetLinkTimeout = 0x400233ec );\nPROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 );\nPROVIDE ( r_lm_get_loopback_mode = 0x4004f248 );\nPROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c );\nPROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 );\nPROVIDE ( r_LM_GetMasterKey = 0x4001b260 );\nPROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 );\nPROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 );\nPROVIDE ( r_lm_get_nb_acl = 0x4004ef9c );\nPROVIDE ( r_lm_get_nb_sync_link = 0x4005179c );\nPROVIDE ( r_lm_get_nonce = 0x400131c4 );\nPROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 );\nPROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 );\nPROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 );\nPROVIDE ( r_LM_GetPINType = 0x4004f1e8 );\nPROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 );\nPROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 );\nPROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 );\nPROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 );\nPROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 );\nPROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 );\nPROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c );\nPROVIDE ( r_lm_get_sp_en = 0x4004f1c0 );\nPROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 );\nPROVIDE ( r_lm_get_synchdl = 0x4005175c );\nPROVIDE ( r_lm_get_sync_param = 0x400503b4 );\nPROVIDE ( r_lm_init = 0x4004ed34 );\nPROVIDE ( r_lm_init_sync = 0x400512d8 );\nPROVIDE ( r_lm_is_acl_con = 0x4004f47c );\nPROVIDE ( r_lm_is_acl_con_role = 0x4004f49c );\nPROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 );\nPROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 );\nPROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 );\nPROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 );\nPROVIDE ( r_lm_look_for_sync = 0x40051774 );\nPROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c );\nPROVIDE ( r_lm_lt_addr_free = 0x4004ef74 );\nPROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 );\nPROVIDE ( r_LM_MakeCof = 0x4002f84c );\nPROVIDE ( r_LM_MakeRandVec = 0x400112d8 );\nPROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 );\nPROVIDE ( r_LM_MaxSlot = 0x4002f694 );\nPROVIDE ( r_lm_modif_sync = 0x40051578 );\nPROVIDE ( r_lm_n_is_zero = 0x40012170 );\nPROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 );\nPROVIDE ( r_lm_oob_f1 = 0x40012e54 );\nPROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 );\nPROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 );\nPROVIDE ( nvds_null_read = 0x400542a0 );\nPROVIDE ( nvds_null_write = 0x400542a8 );\nPROVIDE ( nvds_null_erase = 0x400542b0 );\nPROVIDE ( nvds_read = 0x400542c4 );\nPROVIDE ( nvds_write = 0x400542fc );\nPROVIDE ( nvds_erase = 0x40054334 );\nPROVIDE ( nvds_init_memory = 0x40054358 );\nPROVIDE ( r_lmp_pack = 0x4001135c );\nPROVIDE ( r_lmp_unpack = 0x4001149c );\nPROVIDE ( r_lm_read_features = 0x4004f0d8 );\nPROVIDE ( r_LM_RemoveSniff = 0x40023124 );\nPROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 );\nPROVIDE ( r_lm_remove_sync = 0x400517c8 );\nPROVIDE ( r_lm_reset_sync = 0x40051304 );\nPROVIDE ( r_lm_role_switch_finished = 0x4004f028 );\nPROVIDE ( r_lm_role_switch_start = 0x4004efe0 );\nPROVIDE ( r_lm_sco_nego_end = 0x40051828 );\nPROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 );\nPROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 );\nPROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc );\nPROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 );\nPROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 );\nPROVIDE ( r_lm_sp_n_one = 0x400123a4 );\nPROVIDE ( r_lm_sp_p192_add = 0x40012828 );\nPROVIDE ( r_lm_sp_p192_dbl = 0x4001268c );\nPROVIDE ( r_lm_sp_p192_invert = 0x40012b6c );\nPROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 );\nPROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 );\nPROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 );\nPROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 );\nPROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 );\nPROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 );\nPROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 );\nPROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 );\nPROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 );\nPROVIDE ( r_modules_funcs = 0x3ffafd6c );\nPROVIDE ( r_modules_funcs_p = 0x3ffafd68 );\nPROVIDE ( r_nvds_del = 0x400544c4 );\nPROVIDE ( r_nvds_get = 0x40054488 );\nPROVIDE ( r_nvds_init = 0x40054410 );\nPROVIDE ( r_nvds_lock = 0x400544fc );\nPROVIDE ( r_nvds_put = 0x40054534 );\nPROVIDE ( rom_abs_temp = 0x400054f0 );\nPROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c );\nPROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac );\nPROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 );\nPROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 );\nPROVIDE ( rom_bb_wdg_test_en = 0x40003b70 );\nPROVIDE ( rom_cbw2040_cfg = 0x400040b0 );\nPROVIDE ( rom_check_noise_floor = 0x40003c78 );\nPROVIDE ( rom_chip_i2c_readReg = 0x40004110 );\nPROVIDE ( rom_chip_i2c_writeReg = 0x40004168 );\nPROVIDE ( rom_chip_v7_bt_init = 0x40004d8c );\nPROVIDE ( rom_chip_v7_rx_init = 0x40004cec );\nPROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 );\nPROVIDE ( rom_chip_v7_tx_init = 0x40004d18 );\nPROVIDE ( rom_clk_force_on_vit = 0x40003710 );\nPROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 );\nPROVIDE ( rom_dc_iq_est = 0x400055c8 );\nPROVIDE ( rom_disable_agc = 0x40002fa4 );\nPROVIDE ( rom_enable_agc = 0x40002fcc );\nPROVIDE ( rom_en_pwdet = 0x4000506c );\nPROVIDE ( rom_gen_rx_gain_table = 0x40003e3c );\nPROVIDE ( rom_get_data_sat = 0x4000312c );\nPROVIDE ( rom_get_fm_sar_dout = 0x40005204 );\nPROVIDE ( rom_get_power_db = 0x40005fc8 );\nPROVIDE ( rom_get_pwctrl_correct = 0x400065d4 );\nPROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc );\nPROVIDE ( rom_get_rf_gain_qdb = 0x40006290 );\nPROVIDE ( rom_get_sar_dout = 0x40006564 );\nPROVIDE ( rom_i2c_readReg = 0x40004148 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x400041c0 );\nPROVIDE ( rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x400041fc );\nPROVIDE ( rom_index_to_txbbgain = 0x40004df8 );\nPROVIDE ( rom_iq_est_disable = 0x40005590 );\nPROVIDE ( rom_iq_est_enable = 0x40005514 );\nPROVIDE ( rom_linear_to_db = 0x40005f64 );\nPROVIDE ( rom_loopback_mode_en = 0x400030f8 );\nPROVIDE ( rom_meas_tone_pwr_db = 0x40006004 );\nPROVIDE ( rom_mhz2ieee = 0x4000404c );\nPROVIDE ( rom_noise_floor_auto_set = 0x40003bdc );\nPROVIDE ( rom_pbus_debugmode = 0x40004458 );\nPROVIDE ( rom_pbus_force_mode = 0x40004270 );\nPROVIDE ( rom_pbus_force_test = 0x400043c0 );\nPROVIDE ( rom_pbus_rd = 0x40004414 );\nPROVIDE ( rom_pbus_rd_addr = 0x40004334 );\nPROVIDE ( rom_pbus_rd_shift = 0x40004374 );\nPROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 );\nPROVIDE ( rom_pbus_set_dco = 0x40004638 );\nPROVIDE ( rom_pbus_set_rxgain = 0x40004480 );\nPROVIDE ( rom_pbus_workmode = 0x4000446c );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 );\nPROVIDE ( rom_phy_disable_agc = 0x40002f6c );\nPROVIDE ( rom_phy_disable_cca = 0x40003000 );\nPROVIDE ( rom_phy_enable_agc = 0x40002f88 );\nPROVIDE ( rom_phy_enable_cca = 0x4000302c );\nPROVIDE ( rom_phy_freq_correct = 0x40004b44 );\nPROVIDE ( rom_phyFuns = 0x3ffae0c0 );\nPROVIDE ( rom_phy_get_noisefloor = 0x40003c2c );\nPROVIDE ( rom_phy_get_vdd33 = 0x4000642c );\nPROVIDE ( rom_pow_usr = 0x40003044 );\nPROVIDE ( rom_read_sar_dout = 0x400051c0 );\nPROVIDE ( rom_restart_cal = 0x400046e0 );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40006058 );\nPROVIDE ( rom_rfcal_rxiq = 0x40005b4c );\nPROVIDE ( rom_rfcal_txcap = 0x40005dec );\nPROVIDE ( rom_rfpll_reset = 0x40004680 );\nPROVIDE ( rom_rfpll_set_freq = 0x400047f8 );\nPROVIDE ( rom_rtc_mem_backup = 0x40003db4 );\nPROVIDE ( rom_rtc_mem_recovery = 0x40003df4 );\nPROVIDE ( rom_rx_gain_force = 0x4000351c );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 );\nPROVIDE ( rom_rxiq_get_mis = 0x400058e4 );\nPROVIDE ( rom_rxiq_set_reg = 0x40005a00 );\nPROVIDE ( rom_set_cal_rxdc = 0x400030b8 );\nPROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 );\nPROVIDE ( rom_set_channel_freq = 0x40004880 );\nPROVIDE ( rom_set_loopback_gain = 0x40003060 );\nPROVIDE ( rom_set_noise_floor = 0x40003d48 );\nPROVIDE ( rom_set_pbus_mem = 0x400031a4 );\nPROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 );\nPROVIDE ( rom_set_rxclk_en = 0x40003594 );\nPROVIDE ( rom_set_txcap_reg = 0x40005d50 );\nPROVIDE ( rom_set_txclk_en = 0x40003564 );\nPROVIDE ( rom_spur_coef_cfg = 0x40003ac8 );\nPROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 );\nPROVIDE ( rom_start_tx_tone = 0x400036b4 );\nPROVIDE ( rom_start_tx_tone_step = 0x400035d0 );\nPROVIDE ( rom_stop_tx_tone = 0x40003f98 );\nPROVIDE ( _rom_store = 0x4000d66c );\nPROVIDE ( _rom_store_table = 0x4000d4f8 );\nPROVIDE ( rom_target_power_add_backoff = 0x40006268 );\nPROVIDE ( rom_tx_atten_set_interp = 0x400061cc );\nPROVIDE ( rom_txbbgain_to_index = 0x40004dc0 );\nPROVIDE ( rom_txcal_work_mode = 0x4000510c );\nPROVIDE ( rom_txdc_cal_init = 0x40004e10 );\nPROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 );\nPROVIDE ( rom_txiq_cover = 0x4000538c );\nPROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc );\nPROVIDE ( rom_txiq_set_reg = 0x40005154 );\nPROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c );\nPROVIDE ( rom_txtone_linear_pwr = 0x40005290 );\nPROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 );\nPROVIDE ( rom_write_gain_mem = 0x4000348c );\nPROVIDE ( rom_write_rfpll_sdm = 0x40004740 );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( r_plf_funcs_p = 0x3ffb8360 );\nPROVIDE ( r_rf_rw_bt_init = 0x40054868 );\nPROVIDE ( r_rf_rw_init = 0x40054b0c );\nPROVIDE ( r_rf_rw_le_init = 0x400549d0 );\nPROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c );\nPROVIDE ( r_rwble_init = 0x40054bf4 );\nPROVIDE ( r_rwble_isr = 0x40054e08 );\nPROVIDE ( r_rwble_reset = 0x40054ce8 );\nPROVIDE ( r_rwble_sleep_check = 0x40054d78 );\nPROVIDE ( r_rwble_version = 0x40054dac );\nPROVIDE ( r_rwbt_init = 0x40055160 );\nPROVIDE ( r_rwbt_isr = 0x40055248 );\nPROVIDE ( r_rwbt_reset = 0x400551bc );\nPROVIDE ( r_rwbt_sleep_check = 0x4005577c );\nPROVIDE ( r_rwbt_sleep_enter = 0x400557a4 );\nPROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc );\nPROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc );\nPROVIDE ( r_rwbt_version = 0x4005520c );\nPROVIDE ( r_rwip_assert_err = 0x40055f88 );\nPROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc );\nPROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c );\nPROVIDE ( r_rwip_init = 0x4005595c );\nPROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 );\nPROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 );\nPROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 );\nPROVIDE ( r_rwip_reset = 0x40055ab8 );\nPROVIDE ( r_rwip_schedule = 0x40055b38 );\nPROVIDE ( r_rwip_sleep = 0x40055b5c );\nPROVIDE ( r_rwip_sleep_enable = 0x40055f30 );\nPROVIDE ( r_rwip_version = 0x40055b20 );\nPROVIDE ( r_rwip_wakeup = 0x40055dc4 );\nPROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c );\nPROVIDE ( r_rwip_wakeup_end = 0x40055e18 );\nPROVIDE ( r_rwip_wlcoex_set = 0x40055f60 );\nPROVIDE ( r_SHA_256 = 0x40013a90 );\nPROVIDE ( rwip_coex_cfg = 0x3ff9914c );\nPROVIDE ( rwip_priority = 0x3ff99159 );\nPROVIDE ( rwip_rf = 0x3ffbdb28 );\nPROVIDE ( rwip_rf_p_get = 0x400558f4 );\nPROVIDE ( r_XorKey = 0x400112c0 );\nPROVIDE ( sbrk = 0x400017f4 );\nPROVIDE ( _sbrk_r = 0x4000bce4 );\nPROVIDE ( __sccl = 0x4000c498 );\nPROVIDE ( __sclose = 0x400011b8 );\nPROVIDE ( __seofread = 0x40001148 );\nPROVIDE ( setjmp = 0x40056268 );\nPROVIDE ( setlocale = 0x40059568 );\nPROVIDE ( _setlocale_r = 0x4005950c );\nPROVIDE ( __sf_fake_stderr = 0x3ff96458 );\nPROVIDE ( __sf_fake_stdin = 0x3ff96498 );\nPROVIDE ( __sf_fake_stdout = 0x3ff96478 );\nPROVIDE ( __sflush_r = 0x400591e0 );\nPROVIDE ( __sfmoreglue = 0x40001dc8 );\nPROVIDE ( __sfp = 0x40001e90 );\nPROVIDE ( __sfp_lock_acquire = 0x40001e08 );\nPROVIDE ( __sfp_lock_release = 0x40001e14 );\nPROVIDE ( __sfputs_r = 0x40057790 );\nPROVIDE ( __sfvwrite_r = 0x4005893c );\nPROVIDE ( sha1_prf = 0x40060ae8 );\nPROVIDE ( sha1_vector = 0x40060b64 );\nPROVIDE ( sha256_prf = 0x40060d70 );\nPROVIDE ( sha256_vector = 0x40060e08 );\nPROVIDE ( sha_blk_bits = 0x3ff99290 );\nPROVIDE ( sha_blk_bits_bytes = 0x3ff99288 );\nPROVIDE ( sha_blk_hash_bytes = 0x3ff9928c );\nPROVIDE ( sig_matrix = 0x3ffae293 );\nPROVIDE ( __sinit = 0x40001e38 );\nPROVIDE ( __sinit_lock_acquire = 0x40001e20 );\nPROVIDE ( __sinit_lock_release = 0x40001e2c );\nPROVIDE ( sip_after_tx_complete = 0x4000b358 );\nPROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c );\nPROVIDE ( sip_get_ptr = 0x4000b34c );\nPROVIDE ( sip_get_state = 0x4000ae2c );\nPROVIDE ( sip_init_attach = 0x4000ae58 );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 );\nPROVIDE ( sip_install_rx_data_cb = 0x4000ae20 );\nPROVIDE ( sip_is_active = 0x4000b3c0 );\nPROVIDE ( sip_post_init = 0x4000aed8 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c );\nPROVIDE ( sip_send = 0x4000af54 );\nPROVIDE ( sip_to_host_chain_append = 0x4000aef8 );\nPROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 );\nPROVIDE ( slc_add_credits = 0x4000baf4 );\nPROVIDE ( slc_enable = 0x4000b64c );\nPROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 );\nPROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 );\nPROVIDE ( slc_has_pkt_to_host = 0x4000b5fc );\nPROVIDE ( slc_init_attach = 0x4000b918 );\nPROVIDE ( slc_init_credit = 0x4000badc );\nPROVIDE ( slc_reattach = 0x4000b62c );\nPROVIDE ( slc_send_to_host_chain = 0x4000b6a0 );\nPROVIDE ( slc_set_host_io_max_window = 0x4000b89c );\nPROVIDE ( slc_to_host_chain_recycle = 0x4000b758 );\nPROVIDE ( __smakebuf_r = 0x40059108 );\nPROVIDE ( specialModP256 = 0x4001600c );\nPROVIDE ( srand = 0x40001004 );\nPROVIDE ( __sread = 0x40001118 );\nPROVIDE ( __srefill_r = 0x400593d4 );\nPROVIDE ( __sseek = 0x40001184 );\nPROVIDE ( __ssprint_r = 0x40056ff8 );\nPROVIDE ( __ssputs_r = 0x40056f2c );\nPROVIDE ( __ssrefill_r = 0x40057fec );\nPROVIDE ( __stack = 0x3ffe3f20 );\nPROVIDE ( __stack_app = 0x3ffe7e30 );\nPROVIDE ( _stack_sentry = 0x3ffe1320 );\nPROVIDE ( _stack_sentry_app = 0x3ffe5230 );\nPROVIDE ( _start = 0x40000704 );\nPROVIDE ( start_tb_console = 0x4005a980 );\nPROVIDE ( _stat_r = 0x4000bcb4 );\nPROVIDE ( _stext = 0x40000560 );\nPROVIDE ( strcasecmp = 0x400011cc );\nPROVIDE ( strcasestr = 0x40001210 );\nPROVIDE ( strcat = 0x4000c518 );\nPROVIDE ( strchr = 0x4000c53c );\nPROVIDE ( strcmp = 0x40001274 );\nPROVIDE ( strcoll = 0x40001398 );\nPROVIDE ( strcpy = 0x400013ac );\nPROVIDE ( strcspn = 0x4000c558 );\nPROVIDE ( strdup = 0x4000143c );\nPROVIDE ( _strdup_r = 0x40001450 );\nPROVIDE ( strftime = 0x40059ab4 );\nPROVIDE ( strlcat = 0x40001470 );\nPROVIDE ( strlcpy = 0x4000c584 );\nPROVIDE ( strlen = 0x400014c0 );\nPROVIDE ( strlwr = 0x40001524 );\nPROVIDE ( strncasecmp = 0x40001550 );\nPROVIDE ( strncat = 0x4000c5c4 );\nPROVIDE ( strncmp = 0x4000c5f4 );\nPROVIDE ( strncpy = 0x400015d4 );\nPROVIDE ( strndup = 0x400016b0 );\nPROVIDE ( _strndup_r = 0x400016c4 );\nPROVIDE ( strnlen = 0x4000c628 );\nPROVIDE ( strrchr = 0x40001708 );\nPROVIDE ( strsep = 0x40001734 );\nPROVIDE ( strspn = 0x4000c648 );\nPROVIDE ( strstr = 0x4000c674 );\nPROVIDE ( __strtok_r = 0x4000c6a8 );\nPROVIDE ( strtok_r = 0x4000c70c );\nPROVIDE ( strtol = 0x4005681c );\nPROVIDE ( _strtol_r = 0x40056714 );\nPROVIDE ( strtoul = 0x4005692c );\nPROVIDE ( _strtoul_r = 0x40056834 );\nPROVIDE ( strupr = 0x4000174c );\nPROVIDE ( __subdf3 = 0x400026e4 );\nPROVIDE ( __submore = 0x40058f3c );\nPROVIDE ( __subsf3 = 0x400021d0 );\nPROVIDE ( SubtractBigHex256 = 0x40015bcc );\nPROVIDE ( SubtractBigHexMod256 = 0x40015e8c );\nPROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c );\nPROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 );\nPROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 );\nPROVIDE ( __subvdi3 = 0x40002d20 );\nPROVIDE ( __subvsi3 = 0x40002cf8 );\nPROVIDE ( _sungetc_r = 0x40057f6c );\nPROVIDE ( __swbuf = 0x40058cb4 );\nPROVIDE ( __swbuf_r = 0x40058bec );\nPROVIDE ( __swrite = 0x40001150 );\nPROVIDE ( __swsetup_r = 0x40058cc8 );\nPROVIDE ( sw_to_hw = 0x3ffb8d40 );\nPROVIDE ( syscall_table_ptr_app = 0x3ffae020 );\nPROVIDE ( syscall_table_ptr_pro = 0x3ffae024 );\nPROVIDE ( _system_r = 0x4000bc10 );\nPROVIDE ( tdefl_compress = 0x400600bc );\nPROVIDE ( tdefl_compress_buffer = 0x400607f4 );\nPROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 );\nPROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 );\nPROVIDE ( tdefl_get_adler32 = 0x400608d8 );\nPROVIDE ( tdefl_get_prev_return_status = 0x400608d0 );\nPROVIDE ( tdefl_init = 0x40060810 );\nPROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c );\nPROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 );\nPROVIDE ( time = 0x40001844 );\nPROVIDE ( __time_load_locale = 0x4000183c );\nPROVIDE ( times = 0x40001808 );\nPROVIDE ( _times_r = 0x4000bc40 );\nPROVIDE ( _timezone = 0x3ffae0a0 );\nPROVIDE ( tinfl_decompress = 0x4005ef30 );\nPROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 );\nPROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 );\nPROVIDE ( toascii = 0x4000c720 );\nPROVIDE ( tolower = 0x40001868 );\nPROVIDE ( toupper = 0x40001884 );\nPROVIDE ( __truncdfsf2 = 0x40002b90 );\nPROVIDE ( __tzcalc_limits = 0x400018a0 );\nPROVIDE ( __tz_lock = 0x40001a04 );\nPROVIDE ( _tzname = 0x3ffae030 );\nPROVIDE ( tzset = 0x40001a1c );\nPROVIDE ( _tzset_r = 0x40001a28 );\nPROVIDE ( __tz_unlock = 0x40001a10 );\nPROVIDE ( UartDev = 0x3ffe019c );\nPROVIDE ( __ucmpdi2 = 0x40063840 );\nPROVIDE ( __udivdi3 = 0x4000cff8 );\nPROVIDE ( __udivmoddi4 = 0x40064ab0 );\nPROVIDE ( __udivsi3 = 0x4000c7c8 );\nPROVIDE ( __udiv_w_sdiv = 0x40064aa8 );\nPROVIDE ( __umoddi3 = 0x4000d280 );\nPROVIDE ( __umodsi3 = 0x4000c7d0 );\nPROVIDE ( __umulsidi3 = 0x4000c7d8 );\nPROVIDE ( ungetc = 0x400590f4 );\nPROVIDE ( _ungetc_r = 0x40058fa0 );\nPROVIDE ( _unlink_r = 0x4000bc84 );\nPROVIDE ( __unorddf2 = 0x400637f4 );\nPROVIDE ( __unordsf2 = 0x40063478 );\nPROVIDE ( user_code_start = 0x3ffe0400 );\nPROVIDE ( utoa = 0x40056258 );\nPROVIDE ( __utoa = 0x400561f0 );\nPROVIDE ( veryBigHexP256 = 0x3ff9736c );\nPROVIDE ( wcrtomb = 0x40058920 );\nPROVIDE ( _wcrtomb_r = 0x400588d8 );\nPROVIDE ( __wctomb = 0x3ff96540 );\nPROVIDE ( _wctomb_r = 0x40058f14 );\nPROVIDE ( write = 0x4000181c );\nPROVIDE ( _write_r = 0x4000bd70 );\nPROVIDE ( xthal_bcopy = 0x4000c098 );\nPROVIDE ( xthal_copy123 = 0x4000c124 );\nPROVIDE ( xthal_get_ccompare = 0x4000c078 );\nPROVIDE ( xthal_get_ccount = 0x4000c050 );\nPROVIDE ( xthal_get_interrupt = 0x4000c1e4 );\nPROVIDE ( xthal_get_intread = 0x4000c1e4 );\nPROVIDE ( Xthal_intlevel = 0x3ff9c2b4 );\nPROVIDE ( xthal_memcpy = 0x4000c0bc );\nPROVIDE ( xthal_set_ccompare = 0x4000c058 );\nPROVIDE ( xthal_set_intclear = 0x4000c1ec );\nPROVIDE ( _xtos_set_intlevel = 0x4000bfdc );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( esp_rom_spiflash_config_param = 0x40063238 );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );\nPROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 );\nPROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 );\nPROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c );\nPROVIDE ( esp_rom_spiflash_select_qio_pins = 0x40061ddc );\nPROVIDE ( esp_rom_spiflash_attach = 0x40062a6c );\nPROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 );\nPROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );\n\n\/* \nThese functions are xtos-related (or call xtos-related functions) and do not play well \nwith multicore FreeRTOS. Where needed, we provide alternatives that are multicore\ncompatible. These functions also use a chunk of static RAM, by not using them we can\nallocate that RAM for general use.\n*\/\n\/*\nPROVIDE ( _DebugExceptionVector = 0x40000280 );\nPROVIDE ( _DoubleExceptionVector = 0x400003c0 );\nPROVIDE ( _KernelExceptionVector = 0x40000300 );\nPROVIDE ( _GeneralException = 0x40000e14 );\nPROVIDE ( _ResetHandler = 0x40000450 );\nPROVIDE ( _ResetVector = 0x40000400 );\nPROVIDE ( _UserExceptionVector = 0x40000340 );\nPROVIDE ( _NMIExceptionVector = 0x400002c0 );\nPROVIDE ( _WindowOverflow12 = 0x40000100 );\nPROVIDE ( _WindowOverflow4 = 0x40000000 );\nPROVIDE ( _WindowOverflow8 = 0x40000080 );\nPROVIDE ( _WindowUnderflow12 = 0x40000140 );\nPROVIDE ( _WindowUnderflow4 = 0x40000040 );\nPROVIDE ( _WindowUnderflow8 = 0x400000c0 );\nPROVIDE ( _Level2FromVector = 0x40000954 );\nPROVIDE ( _Level3FromVector = 0x40000a28 );\nPROVIDE ( _Level4FromVector = 0x40000af8 );\nPROVIDE ( _Level5FromVector = 0x40000c68 );\nPROVIDE ( _Level2Vector = 0x40000180 );\nPROVIDE ( _Level3Vector = 0x400001c0 );\nPROVIDE ( _Level4Vector = 0x40000200 );\nPROVIDE ( _Level5Vector = 0x40000240 );\nPROVIDE ( _LevelOneInterrupt = 0x40000835 );\nPROVIDE ( _SyscallException = 0x400007cf );\nPROVIDE ( _xtos_alloca_handler = 0x40000010 );\nPROVIDE ( _xtos_cause3_handler = 0x40000dd8 );\nPROVIDE ( _xtos_c_handler_table = 0x3ffe0548 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 );\nPROVIDE ( _xtos_enabled = 0x3ffe0650 );\nPROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 );\nPROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 );\nPROVIDE ( _xtos_interrupt_table = 0x3ffe0658 );\nPROVIDE ( _xtos_ints_off = 0x4000bfac );\nPROVIDE ( _xtos_ints_on = 0x4000bf88 );\nPROVIDE ( _xtos_intstruct = 0x3ffe0650 );\nPROVIDE ( _xtos_l1int_handler = 0x40000814 );\nPROVIDE ( _xtos_p_none = 0x4000bfd4 );\nPROVIDE ( _xtos_restore_intlevel = 0x40000928 );\nPROVIDE ( _xtos_return_from_exc = 0x4000c034 );\nPROVIDE ( _xtos_set_exception_handler = 0x4000074c );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 );\nPROVIDE ( _xtos_set_vpri = 0x40000934 );\nPROVIDE ( _xtos_syscall_handler = 0x40000790 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000c024 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c );\nPROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 );\nPROVIDE ( ets_intr_count = 0x3ffe03fc );\n*\/\n\n\/* These functions are part of the UART downloader but also contain general UART functions. *\/\nPROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x40008860 );\nPROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 );\nPROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec );\nPROVIDE ( MemDwnLdStartMsgProc = 0x40008948 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc );\nPROVIDE ( MemPacketSendReqMsgProc = 0x40008978 );\nPROVIDE ( uart_baudrate_detect = 0x40009034 );\nPROVIDE ( uart_buff_switch = 0x400093c0 );\nPROVIDE ( UartConnCheck = 0x40008738 );\nPROVIDE ( UartConnectProc = 0x40008a04 );\nPROVIDE ( UartDwnLdProc = 0x40008ce8 );\nPROVIDE ( UartRegReadProc = 0x40008a58 );\nPROVIDE ( UartRegWriteProc = 0x40008a14 );\nPROVIDE ( UartSetBaudProc = 0x40008aac );\nPROVIDE ( UartSpiAttachProc = 0x40008a6c );\nPROVIDE ( UartSpiReadProc = 0x40008a80 );\nPROVIDE ( VerifyFlashMd5Proc = 0x40008c44 );\nPROVIDE ( GetUartDevice = 0x40009598 );\nPROVIDE ( RcvMsg = 0x4000954c );\nPROVIDE ( SendMsg = 0x40009384 );\nPROVIDE ( UartGetCmdLn = 0x40009564 );\nPROVIDE ( UartRxString = 0x400092fc );\nPROVIDE ( Uart_Init = 0x40009120 );\nPROVIDE ( recv_packet = 0x40009424 );\nPROVIDE ( send_packet = 0x40009340 );\nPROVIDE ( uartAttach = 0x40008fd0 );\nPROVIDE ( uart_div_modify = 0x400090cc );\nPROVIDE ( uart_rx_intr_handler = 0x40008f4c );\nPROVIDE ( uart_rx_one_char = 0x400092d0 );\nPROVIDE ( uart_rx_one_char_block = 0x400092a4 );\nPROVIDE ( uart_rx_readbuff = 0x40009394 );\nPROVIDE ( uart_tx_flush = 0x40009258 );\nPROVIDE ( uart_tx_one_char = 0x40009200 );\nPROVIDE ( uart_tx_one_char2 = 0x4000922c );\nPROVIDE ( uart_tx_switch = 0x40009028 );\nPROVIDE ( uart_tx_wait_idle = 0x40009278 );\n\n\n\/*\nThese functions are part of the ROM GPIO driver. We do not use them; the provided esp-idf functions\nreplace them and this way we can re-use the fixed RAM addresses these routines need.\n*\/\n\/* <-- So you don't read over it: This comment disables the next lines.\nPROVIDE ( gpio_init = 0x40009c20 );\nPROVIDE ( gpio_intr_ack = 0x40009dd4 );\nPROVIDE ( gpio_intr_ack_high = 0x40009e1c );\nPROVIDE ( gpio_intr_handler_register = 0x40009e6c );\nPROVIDE ( gpio_intr_pending = 0x40009cec );\nPROVIDE ( gpio_intr_pending_high = 0x40009cf8 );\nPROVIDE ( gpio_pending_mask = 0x3ffe0038 );\nPROVIDE ( gpio_pending_mask_high = 0x3ffe0044 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40009d04 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c );\nPROVIDE ( gpio_register_get = 0x40009cbc );\nPROVIDE ( gpio_register_set = 0x40009bbc );\n*\/\n\/* These are still part of that driver, but have been verified not to use static RAM, so they can be used. *\/\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( gpio_input_get = 0x40009b88 );\nPROVIDE ( gpio_input_get_high = 0x40009b9c );\nPROVIDE ( gpio_matrix_in = 0x40009edc );\nPROVIDE ( gpio_matrix_out = 0x40009f0c );\nPROVIDE ( gpio_pad_select_gpio = 0x40009fdc );\nPROVIDE ( gpio_pad_set_drv = 0x4000a11c );\nPROVIDE ( gpio_pad_pulldown = 0x4000a348 );\nPROVIDE ( gpio_pad_pullup = 0x4000a22c );\nPROVIDE ( gpio_pad_hold = 0x4000a734 );\nPROVIDE ( gpio_pad_unhold = 0x4000a484 );\n\n\/*\nThese functions are part of the non-os kernel (etsc).\n*\/\nPROVIDE ( ets_aes_crypt = 0x4005c9b8 );\nPROVIDE ( ets_aes_disable = 0x4005c8f8 );\nPROVIDE ( ets_aes_enable = 0x4005c8cc );\nPROVIDE ( ets_aes_set_endian = 0x4005c928 );\nPROVIDE ( ets_aes_setkey_dec = 0x4005c994 );\nPROVIDE ( ets_aes_setkey_enc = 0x4005c97c );\nPROVIDE ( ets_bigint_disable = 0x4005c4e0 );\nPROVIDE ( ets_bigint_enable = 0x4005c498 );\nPROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 );\nPROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 );\nPROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 );\nPROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c );\nPROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 );\nPROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc );\nPROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 );\nPROVIDE ( ets_bigint_mult_prepare = 0x4005c630 );\nPROVIDE ( ets_bigint_wait_finish = 0x4005c520 );\nPROVIDE ( ets_post = 0x4000673c );\nPROVIDE ( ets_run = 0x400066bc );\nPROVIDE ( ets_set_idle_cb = 0x40006674 );\nPROVIDE ( ets_task = 0x40006688 );\nPROVIDE ( ets_efuse_get_8M_clock = 0x40008710 );\nPROVIDE ( ets_efuse_get_spiconfig = 0x40008658 );\nPROVIDE ( ets_efuse_program_op = 0x40008628 );\nPROVIDE ( ets_efuse_read_op = 0x40008600 );\nPROVIDE ( ets_intr_lock = 0x400067b0 );\nPROVIDE ( ets_intr_unlock = 0x400067c4 );\nPROVIDE ( ets_isr_attach = 0x400067ec );\nPROVIDE ( ets_isr_mask = 0x400067fc );\nPROVIDE ( ets_isr_unmask = 0x40006808 );\nPROVIDE ( ets_waiti0 = 0x400067d8 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( check_pos = 0x400068b8 );\nPROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( ets_set_startup_callback = 0x4000688c );\nPROVIDE ( ets_set_user_start = 0x4000687c );\nPROVIDE ( ets_unpack_flash_code = 0x40007018 );\nPROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c );\nPROVIDE ( rom_main = 0x400076c4 );\nPROVIDE ( ets_write_char_uart = 0x40007cf8 );\nPROVIDE ( ets_install_putc1 = 0x40007d18 );\nPROVIDE ( ets_install_putc2 = 0x40007d38 );\nPROVIDE ( ets_install_uart_printf = 0x40007d28 );\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( rtc_boot_control = 0x4000821c );\nPROVIDE ( rtc_get_reset_reason = 0x400081d4 );\nPROVIDE ( rtc_get_wakeup_cause = 0x400081f4 );\nPROVIDE ( rtc_select_apb_bridge = 0x40008288 );\nPROVIDE ( set_rtc_memory_crc = 0x40008208 );\nPROVIDE ( software_reset = 0x4000824c );\nPROVIDE ( software_reset_cpu = 0x40008264 );\nPROVIDE ( ets_secure_boot_check = 0x4005cb40 );\nPROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 );\nPROVIDE ( ets_secure_boot_check_start = 0x4005cbcc );\nPROVIDE ( ets_secure_boot_finish = 0x4005ca84 );\nPROVIDE ( ets_secure_boot_hash = 0x4005cad4 );\nPROVIDE ( ets_secure_boot_obtain = 0x4005cb14 );\nPROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 );\nPROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 );\nPROVIDE ( ets_secure_boot_start = 0x4005ca34 );\nPROVIDE ( ets_sha_disable = 0x4005c0a8 );\nPROVIDE ( ets_sha_enable = 0x4005c07c );\nPROVIDE ( ets_sha_finish = 0x4005c104 );\nPROVIDE ( ets_sha_init = 0x4005c0d4 );\nPROVIDE ( ets_sha_update = 0x4005c2a0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( ets_get_cpu_frequency = 0x4000855c );\nPROVIDE ( ets_get_detected_xtal_freq = 0x40008588 );\nPROVIDE ( ets_get_xtal_scale = 0x4000856c );\nPROVIDE ( ets_timer_arm = 0x40008368 );\nPROVIDE ( ets_timer_arm_us = 0x400083ac );\nPROVIDE ( ets_timer_disarm = 0x400083ec );\nPROVIDE ( ets_timer_done = 0x40008428 );\nPROVIDE ( ets_timer_handler_isr = 0x40008454 );\nPROVIDE ( ets_timer_init = 0x400084e8 );\nPROVIDE ( ets_timer_setfn = 0x40008350 );\nPROVIDE ( ets_update_cpu_frequency_rom = 0x40008550 );  \/* Updates g_ticks_per_us on the current CPU only; not on the other core *\/\n\n\/* Following are static data, but can be used, not generated by script <<<<< btdm data *\/\nPROVIDE ( hci_tl_env = 0x3ffb8154 );\nPROVIDE ( ld_acl_env = 0x3ffb8258 );\nPROVIDE ( ld_active_ch_map = 0x3ffb8334 );\nPROVIDE ( ld_bcst_acl_env = 0x3ffb8274 );\nPROVIDE ( ld_csb_rx_env = 0x3ffb8278 );\nPROVIDE ( ld_csb_tx_env = 0x3ffb827c );\nPROVIDE ( ld_env = 0x3ffb9510 );\nPROVIDE ( ld_fm_env = 0x3ffb8284 );\nPROVIDE ( ld_inq_env = 0x3ffb82e4 );\nPROVIDE ( ld_iscan_env = 0x3ffb82e8 );\nPROVIDE ( ld_page_env = 0x3ffb82f0 );\nPROVIDE ( ld_pca_env = 0x3ffb82f4 );\nPROVIDE ( ld_pscan_env = 0x3ffb8308 );\nPROVIDE ( ld_sched_env = 0x3ffb830c );\nPROVIDE ( ld_sched_params = 0x3ffb96c0 );\nPROVIDE ( ld_sco_env = 0x3ffb824c );\nPROVIDE ( ld_sscan_env = 0x3ffb832c );\nPROVIDE ( ld_strain_env = 0x3ffb8330 );\nPROVIDE ( LM_Sniff = 0x3ffb8230 );\nPROVIDE ( LM_SniffSubRate = 0x3ffb8214 );\nPROVIDE ( prbs_64bytes = 0x3ff98992 );\nPROVIDE ( nvds_env = 0x3ffb8364 );\nPROVIDE ( nvds_magic_number = 0x3ff9912a );\n\/* Above are static data, but can be used, not generated by script >>>>> btdm data *\/\n\n","old_contents":"\/*\nESP32 ROM address table\nGenerated for ROM with MD5sum:\nab8282ae908fe9e7a63fb2a4ac2df013  ..\/..\/rom_image\/prorom.elf\n*\/\nPROVIDE ( abort = 0x4000bba4 );\nPROVIDE ( abs = 0x40056340 );\nPROVIDE ( __absvdi2 = 0x4006387c );\nPROVIDE ( __absvsi2 = 0x40063868 );\nPROVIDE ( Add2SelfBigHex256 = 0x40015b7c );\nPROVIDE ( AddBigHex256 = 0x40015b28 );\nPROVIDE ( AddBigHexModP256 = 0x40015c98 );\nPROVIDE ( __adddf3 = 0x40002590 );\nPROVIDE ( AddP256 = 0x40015c74 );\nPROVIDE ( AddPdiv2_256 = 0x40015ce0 );\nPROVIDE ( __addsf3 = 0x400020e8 );\nPROVIDE ( __addvdi3 = 0x40002cbc );\nPROVIDE ( __addvsi3 = 0x40002c98 );\nPROVIDE ( aes_128_cbc_decrypt = 0x4005cc7c );\nPROVIDE ( aes_128_cbc_encrypt = 0x4005cc18 );\nPROVIDE ( aes_unwrap = 0x4005ccf0 );\nPROVIDE ( app_gpio_arg = 0x3ffe003c );\nPROVIDE ( app_gpio_handler = 0x3ffe0040 );\nPROVIDE ( __ascii_wctomb = 0x40058ef0 );\nPROVIDE ( asctime = 0x40059588 );\nPROVIDE ( asctime_r = 0x40000ec8 );\nPROVIDE ( __ashldi3 = 0x4000c818 );\nPROVIDE ( __ashrdi3 = 0x4000c830 );\nPROVIDE ( atoi = 0x400566c4 );\nPROVIDE ( _atoi_r = 0x400566d4 );\nPROVIDE ( atol = 0x400566ec );\nPROVIDE ( _atol_r = 0x400566fc );\nPROVIDE ( base64_decode = 0x4005ced8 );\nPROVIDE ( base64_encode = 0x4005cdbc );\nPROVIDE ( BasePoint_x_256 = 0x3ff97488 );\nPROVIDE ( BasePoint_y_256 = 0x3ff97468 );\nPROVIDE ( bigHexInversion256 = 0x400168f0 );\nPROVIDE ( bigHexP256 = 0x3ff973bc );\nPROVIDE ( __bswapdi2 = 0x400649c4 );\nPROVIDE ( __bswapsi2 = 0x4006499c );\nPROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c );\nPROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 );\nPROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 );\nPROVIDE ( btdm_r_data_init = 0x4001002c );\nPROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 );\nPROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 );\nPROVIDE ( btdm_r_ip_func_p_set = 0x40019afc );\nPROVIDE ( btdm_r_modules_func_p_get = 0x4005427c );\nPROVIDE ( btdm_r_modules_func_p_set = 0x40054270 );\nPROVIDE ( btdm_r_plf_func_p_set = 0x40054288 );\nPROVIDE ( bt_util_buf_env = 0x3ffb8bd4 );\nPROVIDE ( bzero = 0x4000c1f4 );\nPROVIDE ( cache_flash_mmu_set_rom = 0x400095e0 );\nPROVIDE ( Cache_Flush_rom = 0x40009a14 );\nPROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );\nPROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );\nPROVIDE ( Cache_Read_Init_rom = 0x40009950 );\nPROVIDE ( cache_sram_mmu_set_rom = 0x400097f4 );\n\/* This is static function, but can be used, not generated by script*\/\nPROVIDE ( calc_rtc_memory_crc = 0x40008170 );\nPROVIDE ( calloc = 0x4000bee4 );\nPROVIDE ( _calloc_r = 0x4000bbf8 );\nPROVIDE ( _cleanup = 0x40001df8 );\nPROVIDE ( _cleanup_r = 0x40001d48 );\nPROVIDE ( __clear_cache = 0x40063860 );\nPROVIDE ( close = 0x40001778 );\nPROVIDE ( _close_r = 0x4000bd3c );\nPROVIDE ( __clrsbdi2 = 0x40064a38 );\nPROVIDE ( __clrsbsi2 = 0x40064a20 );\nPROVIDE ( __clzdi2 = 0x4000ca50 );\nPROVIDE ( __clzsi2 = 0x4000c7e8 );\nPROVIDE ( __cmpdi2 = 0x40063820 );\nPROVIDE ( co_default_bdaddr = 0x3ffae704 );\nPROVIDE ( co_null_bdaddr = 0x3ffb80e0 );\nPROVIDE ( co_sca2ppm = 0x3ff971e8 );\nPROVIDE ( crc16_be = 0x4005d09c );\nPROVIDE ( crc16_le = 0x4005d05c );\nPROVIDE ( crc32_be = 0x4005d024 );\nPROVIDE ( crc32_le = 0x4005cfec );\nPROVIDE ( crc8_be = 0x4005d114 );\nPROVIDE ( crc8_le = 0x4005d0e0 );\nPROVIDE ( creat = 0x40000e8c );\nPROVIDE ( ctime = 0x400595b0 );\nPROVIDE ( ctime_r = 0x400595c4 );\nPROVIDE ( _ctype_ = 0x3ff96354 );\nPROVIDE ( __ctype_ptr__ = 0x3ff96350 );\nPROVIDE ( __ctzdi2 = 0x4000ca64 );\nPROVIDE ( __ctzsi2 = 0x4000c7f0 );\nPROVIDE ( _data_end_rom = 0x4000d5c8 );\nPROVIDE ( _data_end_btdm_rom = 0x4000d4f8 );\nPROVIDE ( _data_start_rom = 0x4000d4f8 );\nPROVIDE ( _data_start_btdm_rom = 0x4000d4f4 );\nPROVIDE ( _data_start_btdm = 0x3ffae6e0);\nPROVIDE ( _data_end_btdm = 0x3ffaff10);\nPROVIDE ( _bss_start_btdm = 0x3ffb8000);\nPROVIDE ( _bss_end_btdm = 0x3ffbff70);\nPROVIDE ( _daylight = 0x3ffae0a4 );\nPROVIDE ( dbg_default_handler = 0x3ff97218 );\nPROVIDE ( dbg_state = 0x3ffb8d5d );\nPROVIDE ( DebugE256PublicKey_x = 0x3ff97428 );\nPROVIDE ( DebugE256PublicKey_y = 0x3ff97408 );\nPROVIDE ( DebugE256SecretKey = 0x3ff973e8 );\nPROVIDE ( debug_timer = 0x3ffe042c );\nPROVIDE ( debug_timerfn = 0x3ffe0430 );\nPROVIDE ( dh_group14_generator = 0x3ff9ac60 );\nPROVIDE ( dh_group14_prime = 0x3ff9ab60 );\nPROVIDE ( dh_group15_generator = 0x3ff9ab5f );\nPROVIDE ( dh_group15_prime = 0x3ff9a9df );\nPROVIDE ( dh_group16_generator = 0x3ff9a9de );\nPROVIDE ( dh_group16_prime = 0x3ff9a7de );\nPROVIDE ( dh_group17_generator = 0x3ff9a7dd );\nPROVIDE ( dh_group17_prime = 0x3ff9a4dd );\nPROVIDE ( dh_group18_generator = 0x3ff9a4dc );\nPROVIDE ( dh_group18_prime = 0x3ff9a0dc );\nPROVIDE ( dh_group1_generator = 0x3ff9ae03 );\nPROVIDE ( dh_group1_prime = 0x3ff9ada3 );\nPROVIDE ( dh_group2_generator = 0x3ff9ada2 );\nPROVIDE ( dh_group2_prime = 0x3ff9ad22 );\nPROVIDE ( dh_group5_generator = 0x3ff9ad21 );\nPROVIDE ( dh_group5_prime = 0x3ff9ac61 );\nPROVIDE ( div = 0x40056348 );\nPROVIDE ( __divdc3 = 0x40064460 );\nPROVIDE ( __divdf3 = 0x40002954 );\nPROVIDE ( __divdi3 = 0x4000ca84 );\nPROVIDE ( __divsc3 = 0x40064200 );\nPROVIDE ( __divsf3 = 0x4000234c );\nPROVIDE ( __divsi3 = 0x4000c7b8 );\nPROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );\nPROVIDE ( __dummy_lock = 0x4000c728 );\nPROVIDE ( __dummy_lock_try = 0x4000c730 );\nPROVIDE ( ecc_env = 0x3ffb8d60 );\nPROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 );\nPROVIDE ( em_buf_env = 0x3ffb8d74 );\nPROVIDE ( environ = 0x3ffae0b4 );\nPROVIDE ( __env_lock = 0x40001fd4 );\nPROVIDE ( __env_unlock = 0x40001fe0 );\nPROVIDE ( __eqdf2 = 0x400636a8 );\nPROVIDE ( __eqsf2 = 0x40063374 );\nPROVIDE ( esp_crc8 = 0x4005d144 );\nPROVIDE ( _etext = 0x4000d66c );\nPROVIDE ( ets_readySet_ = 0x3ffe01f0 );\nPROVIDE ( ets_startup_callback = 0x3ffe0404 );\nPROVIDE ( exc_cause_table = 0x3ff991d0 );\nPROVIDE ( _exit_r = 0x4000bd28 );\nPROVIDE ( __extendsfdf2 = 0x40002c34 );\nPROVIDE ( fclose = 0x400020ac );\nPROVIDE ( _fclose_r = 0x40001fec );\nPROVIDE ( fflush = 0x40059394 );\nPROVIDE ( _fflush_r = 0x40059320 );\nPROVIDE ( __ffsdi2 = 0x4000ca2c );\nPROVIDE ( __ffssi2 = 0x4000c804 );\nPROVIDE ( _findenv_r = 0x40001f44 );\nPROVIDE ( __fixdfdi = 0x40002ac4 );\nPROVIDE ( __fixdfsi = 0x40002a78 );\nPROVIDE ( __fixsfdi = 0x4000244c );\nPROVIDE ( __fixsfsi = 0x4000240c );\nPROVIDE ( __fixunsdfsi = 0x40002b30 );\nPROVIDE ( __fixunssfdi = 0x40002504 );\nPROVIDE ( __fixunssfsi = 0x400024ac );\nPROVIDE ( __floatdidf = 0x4000c988 );\nPROVIDE ( __floatdisf = 0x4000c8c0 );\nPROVIDE ( __floatsidf = 0x4000c944 );\nPROVIDE ( __floatsisf = 0x4000c870 );\nPROVIDE ( __floatundidf = 0x4000c978 );\nPROVIDE ( __floatundisf = 0x4000c8b0 );\nPROVIDE ( __floatunsidf = 0x4000c938 );\nPROVIDE ( __floatunsisf = 0x4000c864 );\nPROVIDE ( __fp_lock_all = 0x40001f1c );\nPROVIDE ( __fp_unlock_all = 0x40001f30 );\nPROVIDE ( fputwc = 0x40058ea8 );\nPROVIDE ( __fputwc = 0x40058da0 );\nPROVIDE ( _fputwc_r = 0x40058e4c );\nPROVIDE ( free = 0x4000beb8 );\nPROVIDE ( _free_r = 0x4000bbcc );\nPROVIDE ( _fstat_r = 0x4000bccc );\nPROVIDE ( _fwalk = 0x4000c738 );\nPROVIDE ( _fwalk_reent = 0x4000c770 );\nPROVIDE ( __gcc_bcmp = 0x40064a70 );\nPROVIDE ( __gedf2 = 0x40063768 );\nPROVIDE ( __gesf2 = 0x4006340c );\nPROVIDE ( __get_current_time_locale = 0x40001834 );\nPROVIDE ( _getenv_r = 0x40001fbc );\nPROVIDE ( _getpid_r = 0x4000bcfc );\nPROVIDE ( __getreent = 0x4000be8c );\nPROVIDE ( _gettimeofday_r = 0x4000bc58 );\nPROVIDE ( __gettzinfo = 0x40001fcc );\nPROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 );\nPROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 );\nPROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c );\nPROVIDE ( _global_impure_ptr = 0x3ffae0b0 );\nPROVIDE ( gmtime = 0x40059848 );\nPROVIDE ( gmtime_r = 0x40059868 );\nPROVIDE ( g_phyFuns_instance = 0x3ffae0c4 );\nPROVIDE ( g_rom_flashchip = 0x3ffae270 );\nPROVIDE ( __gtdf2 = 0x400636dc );\nPROVIDE ( __gtsf2 = 0x400633a0 );\nPROVIDE ( gTxMsg = 0x3ffe0050 );\nPROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 );\nPROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 );\nPROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c );\nPROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 );\nPROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 );\nPROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c );\nPROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 );\nPROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 );\nPROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 );\nPROVIDE ( hci_command_handler = 0x4004c928 );\nPROVIDE ( hci_env = 0x3ffb9350 );\nPROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c );\nPROVIDE ( hci_evt_desc_tab = 0x3ff9751c );\nPROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 );\nPROVIDE ( hci_fc_env = 0x3ffb9340 );\nPROVIDE ( hmac_md5 = 0x4005d264 );\nPROVIDE ( hmac_md5_vector = 0x4005d17c );\nPROVIDE ( hmac_sha1 = 0x40060acc );\nPROVIDE ( hmac_sha1_vector = 0x400609e4 );\nPROVIDE ( hmac_sha256 = 0x40060d58 );\nPROVIDE ( hmac_sha256_vector = 0x40060c84 );\nPROVIDE ( isalnum = 0x40000f04 );\nPROVIDE ( isalpha = 0x40000f18 );\nPROVIDE ( isascii = 0x4000c20c );\nPROVIDE ( _isatty_r = 0x40000ea0 );\nPROVIDE ( isblank = 0x40000f2c );\nPROVIDE ( iscntrl = 0x40000f50 );\nPROVIDE ( isdigit = 0x40000f64 );\nPROVIDE ( isgraph = 0x40000f94 );\nPROVIDE ( islower = 0x40000f78 );\nPROVIDE ( isprint = 0x40000fa8 );\nPROVIDE ( ispunct = 0x40000fc0 );\nPROVIDE ( isspace = 0x40000fd4 );\nPROVIDE ( isupper = 0x40000fe8 );\nPROVIDE ( itoa = 0x400566b4 );\nPROVIDE ( __itoa = 0x40056678 );\nPROVIDE ( jd_decomp = 0x400613e8 );\nPROVIDE ( jd_prepare = 0x40060fa8 );\nPROVIDE ( ke_env = 0x3ffb93cc );\nPROVIDE ( _kill_r = 0x4000bd10 );\nPROVIDE ( labs = 0x40056370 );\nPROVIDE ( lb_default_handler = 0x3ff982b8 );\nPROVIDE ( lb_default_state_tab_p_get = 0x4001c198 );\nPROVIDE ( lb_env = 0x3ffb9424 );\nPROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c );\nPROVIDE ( lb_state = 0x3ffb94e8 );\nPROVIDE ( lc_default_handler = 0x3ff98648 );\nPROVIDE ( lc_default_state_tab_p_get = 0x4002f494 );\nPROVIDE ( lc_env = 0x3ffb94ec );\nPROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 );\nPROVIDE ( lc_state = 0x3ffb9508 );\nPROVIDE ( ld_acl_br_sizes = 0x3ff98a2a );\nPROVIDE ( ld_acl_br_types = 0x3ff98a36 );\nPROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 );\nPROVIDE ( ld_acl_edr_types = 0x3ff98a22 );\nPROVIDE ( ld_env = 0x3ffb9510 );\nPROVIDE ( ldiv = 0x40056378 );\nPROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c );\nPROVIDE ( ld_sched_params = 0x3ffb96c0 );\nPROVIDE ( ld_sync_train_channels = 0x3ff98a3c );\nPROVIDE ( __ledf2 = 0x40063704 );\nPROVIDE ( __lesf2 = 0x400633c0 );\nPROVIDE ( _link_r = 0x4000bc9c );\nPROVIDE ( llc_default_handler = 0x3ff98b3c );\nPROVIDE ( llc_default_state_tab_p_get = 0x40046058 );\nPROVIDE ( llc_env = 0x3ffb96d0 );\nPROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 );\nPROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 );\nPROVIDE ( llc_hci_command_handler = 0x40042360 );\nPROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 );\nPROVIDE ( llc_state = 0x3ffb96f8 );\nPROVIDE ( lldesc_build_chain = 0x4000a850 );\nPROVIDE ( lldesc_num2link = 0x4000a948 );\nPROVIDE ( lldesc_set_owner = 0x4000a974 );\nPROVIDE ( lld_evt_env = 0x3ffb9704 );\nPROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 );\nPROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 );\nPROVIDE ( LLM_AA_CT1 = 0x3ff98d8a );\nPROVIDE ( LLM_AA_CT2 = 0x3ff98d88 );\nPROVIDE ( llm_default_handler = 0x3ff98d80 );\nPROVIDE ( llm_default_state_tab_p_get = 0x4004e718 );\nPROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 );\nPROVIDE ( llm_le_env = 0x3ffb976c );\nPROVIDE ( llm_local_cmds = 0x3ff98d38 );\nPROVIDE ( llm_local_data_len_values = 0x3ff98d1c );\nPROVIDE ( llm_local_le_feats = 0x3ff98d30 );\nPROVIDE ( llm_local_le_states = 0x3ff98d28 );\nPROVIDE ( llm_state = 0x3ffb985c );\nPROVIDE ( lm_default_handler = 0x3ff990e0 );\nPROVIDE ( lm_default_state_tab_p_get = 0x40054268 );\nPROVIDE ( lm_env = 0x3ffb9860 );\nPROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c );\nPROVIDE ( lm_local_supp_feats = 0x3ff990ee );\nPROVIDE ( lm_n_page_tab = 0x3ff990e8 );\nPROVIDE ( lmp_desc_tab = 0x3ff96e6c );\nPROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c );\nPROVIDE ( lm_state = 0x3ffb9a1c );\nPROVIDE ( __locale_charset = 0x40059540 );\nPROVIDE ( __locale_cjk_lang = 0x40059558 );\nPROVIDE ( localeconv = 0x4005957c );\nPROVIDE ( _localeconv_r = 0x40059560 );\nPROVIDE ( __locale_mb_cur_max = 0x40059548 );\nPROVIDE ( __locale_msgcharset = 0x40059550 );\nPROVIDE ( localtime = 0x400595dc );\nPROVIDE ( localtime_r = 0x400595fc );\nPROVIDE ( _lock_acquire = 0x4000be14 );\nPROVIDE ( _lock_acquire_recursive = 0x4000be28 );\nPROVIDE ( _lock_close = 0x4000bdec );\nPROVIDE ( _lock_close_recursive = 0x4000be00 );\nPROVIDE ( _lock_init = 0x4000bdc4 );\nPROVIDE ( _lock_init_recursive = 0x4000bdd8 );\nPROVIDE ( _lock_release = 0x4000be64 );\nPROVIDE ( _lock_release_recursive = 0x4000be78 );\nPROVIDE ( _lock_try_acquire = 0x4000be3c );\nPROVIDE ( _lock_try_acquire_recursive = 0x4000be50 );\nPROVIDE ( longjmp = 0x400562cc );\nPROVIDE ( _lseek_r = 0x4000bd8c );\nPROVIDE ( __lshrdi3 = 0x4000c84c );\nPROVIDE ( __ltdf2 = 0x40063790 );\nPROVIDE ( __ltsf2 = 0x4006342c );\nPROVIDE ( malloc = 0x4000bea0 );\nPROVIDE ( _malloc_r = 0x4000bbb4 );\nPROVIDE ( maxSecretKey_256 = 0x3ff97448 );\nPROVIDE ( __mb_cur_max = 0x3ff96530 );\nPROVIDE ( MD5Final = 0x4005db1c );\nPROVIDE ( MD5Init = 0x4005da7c );\nPROVIDE ( MD5Update = 0x4005da9c );\nPROVIDE ( md5_vector = 0x4005db80 );\nPROVIDE ( memccpy = 0x4000c220 );\nPROVIDE ( memchr = 0x4000c244 );\nPROVIDE ( memcmp = 0x4000c260 );\nPROVIDE ( memcpy = 0x4000c2c8 );\nPROVIDE ( memmove = 0x4000c3c0 );\nPROVIDE ( memrchr = 0x4000c400 );\nPROVIDE ( memset = 0x4000c44c );\nPROVIDE ( mktime = 0x4005a5e8 );\nPROVIDE ( mmu_init = 0x400095a4 );\nPROVIDE ( __moddi3 = 0x4000cd4c );\nPROVIDE ( __modsi3 = 0x4000c7c0 );\nPROVIDE ( __month_lengths = 0x3ff9609c );\nPROVIDE ( __muldc3 = 0x40063bf4 );\nPROVIDE ( __muldf3 = 0x4006358c );\nPROVIDE ( __muldi3 = 0x4000c9fc );\nPROVIDE ( __mulsc3 = 0x40063934 );\nPROVIDE ( __mulsf3 = 0x400632c8 );\nPROVIDE ( __mulsi3 = 0x4000c7b0 );\nPROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 );\nPROVIDE ( MultiplyBigHexModP256 = 0x400160b8 );\nPROVIDE ( MultiplyByU32ModP256 = 0x40015fdc );\nPROVIDE ( multofup = 0x4000ab8c );\nPROVIDE ( __mulvdi3 = 0x40002d78 );\nPROVIDE ( __mulvsi3 = 0x40002d60 );\nPROVIDE ( mz_adler32 = 0x4005edbc );\nPROVIDE ( mz_crc32 = 0x4005ee88 );\nPROVIDE ( mz_free = 0x4005eed4 );\nPROVIDE ( __nedf2 = 0x400636a8 );\nPROVIDE ( __negdf2 = 0x400634a0 );\nPROVIDE ( __negdi2 = 0x4000ca14 );\nPROVIDE ( __negsf2 = 0x400020c0 );\nPROVIDE ( __negvdi2 = 0x40002e98 );\nPROVIDE ( __negvsi2 = 0x40002e78 );\nPROVIDE ( __nesf2 = 0x40063374 );\nPROVIDE ( notEqual256 = 0x40015b04 );\nPROVIDE ( __nsau_data = 0x3ff96544 );\nPROVIDE ( one_bits = 0x3ff971f8 );\nPROVIDE ( open = 0x4000178c );\nPROVIDE ( _open_r = 0x4000bd54 );\nPROVIDE ( __paritysi2 = 0x40002f3c );\nPROVIDE ( pbkdf2_sha1 = 0x40060ba4 );\nPROVIDE ( phy_get_romfuncs = 0x40004100 );\nPROVIDE ( __popcountdi2 = 0x40002ef8 );\nPROVIDE ( __popcountsi2 = 0x40002ed0 );\nPROVIDE ( __popcount_tab = 0x3ff96544 );\nPROVIDE ( __powidf2 = 0x400638d4 );\nPROVIDE ( __powisf2 = 0x4006389c );\nPROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 );\nPROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c );\nPROVIDE ( qsort = 0x40056424 );\nPROVIDE ( _raise_r = 0x4000bc70 );\nPROVIDE ( rand = 0x40001058 );\nPROVIDE ( rand_r = 0x400010d4 );\nPROVIDE ( r_btdm_option_data = 0x3ffae6e0 );\nPROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 );\nPROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 );\nPROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 );\nPROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 );\nPROVIDE ( r_bt_util_buf_init = 0x400100e4 );\nPROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 );\nPROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec );\nPROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 );\nPROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 );\nPROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 );\nPROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c );\nPROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec );\nPROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 );\nPROVIDE ( rc4_skip = 0x40060928 );\nPROVIDE ( r_co_bdaddr_compare = 0x40014324 );\nPROVIDE ( r_co_bytes_to_string = 0x400142e4 );\nPROVIDE ( r_co_list_check_size_available = 0x400142c4 );\nPROVIDE ( r_co_list_extract = 0x4001404c );\nPROVIDE ( r_co_list_extract_after = 0x40014118 );\nPROVIDE ( r_co_list_find = 0x4001419c );\nPROVIDE ( r_co_list_init = 0x40013f14 );\nPROVIDE ( r_co_list_insert_after = 0x40014254 );\nPROVIDE ( r_co_list_insert_before = 0x40014200 );\nPROVIDE ( r_co_list_merge = 0x400141bc );\nPROVIDE ( r_co_list_pool_init = 0x40013f30 );\nPROVIDE ( r_co_list_pop_front = 0x40014028 );\nPROVIDE ( r_co_list_push_back = 0x40013fb8 );\nPROVIDE ( r_co_list_push_front = 0x40013ff4 );\nPROVIDE ( r_co_list_size = 0x400142ac );\nPROVIDE ( r_co_nb_good_channels = 0x40014360 );\nPROVIDE ( r_co_slot_to_duration = 0x40014348 );\nPROVIDE ( r_dbg_init = 0x40014394 );\nPROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 );\nPROVIDE ( r_dbg_swdiag_init = 0x40014470 );\nPROVIDE ( r_dbg_swdiag_read = 0x400144a4 );\nPROVIDE ( r_dbg_swdiag_write = 0x400144d0 );\nPROVIDE ( r_E1 = 0x400108e8 );\nPROVIDE ( r_E21 = 0x40010968 );\nPROVIDE ( r_E22 = 0x400109b4 );\nPROVIDE ( r_E3 = 0x40010a58 );\nPROVIDE ( r_ea_alarm_clear = 0x40015ab4 );\nPROVIDE ( r_ea_alarm_set = 0x40015a10 );\nPROVIDE ( read = 0x400017dc );\nPROVIDE ( _read_r = 0x4000bda8 );\nPROVIDE ( r_ea_elt_cancel = 0x400150d0 );\nPROVIDE ( r_ea_elt_create = 0x40015264 );\nPROVIDE ( r_ea_elt_insert = 0x400152a8 );\nPROVIDE ( r_ea_elt_remove = 0x400154f0 );\nPROVIDE ( r_ea_finetimer_isr = 0x400155d4 );\nPROVIDE ( r_ea_init = 0x40015228 );\nPROVIDE ( r_ea_interval_create = 0x4001555c );\nPROVIDE ( r_ea_interval_delete = 0x400155a8 );\nPROVIDE ( r_ea_interval_duration_req = 0x4001597c );\nPROVIDE ( r_ea_interval_insert = 0x4001557c );\nPROVIDE ( r_ea_interval_remove = 0x40015590 );\nPROVIDE ( realloc = 0x4000becc );\nPROVIDE ( _realloc_r = 0x4000bbe0 );\nPROVIDE ( r_ea_offset_req = 0x40015748 );\nPROVIDE ( r_ea_sleep_check = 0x40015928 );\nPROVIDE ( r_ea_sw_isr = 0x40015724 );\nPROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 );\nPROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 );\nPROVIDE ( r_ecc_abort_key256_generation = 0x40017070 );\nPROVIDE ( r_ecc_generate_key256 = 0x40016e00 );\nPROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 );\nPROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 );\nPROVIDE ( r_ecc_get_debug_Keys = 0x40017224 );\nPROVIDE ( r_ecc_init = 0x40016dbc );\nPROVIDE ( RecvBuff = 0x3ffe009c );\nPROVIDE ( r_em_buf_init = 0x4001729c );\nPROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 );\nPROVIDE ( r_em_buf_rx_free = 0x400173c4 );\nPROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 );\nPROVIDE ( r_em_buf_tx_free = 0x4001741c );\nPROVIDE ( _rename_r = 0x4000bc28 );\nPROVIDE ( r_F1_256 = 0x400133e4 );\nPROVIDE ( r_F2_256 = 0x40013568 );\nPROVIDE ( r_F3_256 = 0x40013664 );\nPROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c );\nPROVIDE ( r_G_256 = 0x40013470 );\nPROVIDE ( r_H3 = 0x40013760 );\nPROVIDE ( r_H4 = 0x40013830 );\nPROVIDE ( r_h4tl_init = 0x40017878 );\nPROVIDE ( r_h4tl_start = 0x40017924 );\nPROVIDE ( r_h4tl_stop = 0x40017934 );\nPROVIDE ( r_h4tl_write = 0x400178d0 );\nPROVIDE ( r_H5 = 0x400138dc );\nPROVIDE ( r_hashConcat = 0x40013a38 );\nPROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c );\nPROVIDE ( r_hci_acl_tx_data_received = 0x40019654 );\nPROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 );\nPROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac );\nPROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c );\nPROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 );\nPROVIDE ( r_hci_cmd_received = 0x400192f8 );\nPROVIDE ( r_hci_evt_filter_add = 0x40018a64 );\nPROVIDE ( r_hci_evt_mask_set = 0x400189e4 );\nPROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 );\nPROVIDE ( r_hci_fc_acl_en = 0x400179d8 );\nPROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c );\nPROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 );\nPROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 );\nPROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c );\nPROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 );\nPROVIDE ( r_hci_fc_init = 0x40017974 );\nPROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 );\nPROVIDE ( r_hci_fc_sync_en = 0x40017a30 );\nPROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 );\nPROVIDE ( r_hci_init = 0x40018538 );\nPROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 );\nPROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 );\nPROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 );\nPROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 );\nPROVIDE ( r_hci_reset = 0x4001856c );\nPROVIDE ( r_hci_send_2_host = 0x400185bc );\nPROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 );\nPROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 );\nPROVIDE ( r_hci_tl_init = 0x40019290 );\nPROVIDE ( r_hci_tl_send = 0x40019228 );\nPROVIDE ( r_hci_util_pack = 0x40019874 );\nPROVIDE ( r_hci_util_unpack = 0x40019998 );\nPROVIDE ( r_hci_voice_settings_get = 0x40018bdc );\nPROVIDE ( r_hci_voice_settings_set = 0x40018be8 );\nPROVIDE ( r_HMAC = 0x40013968 );\nPROVIDE ( r_import_rf_phy_func = 0x3ffb8354 );\nPROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 );\nPROVIDE ( r_ip_funcs = 0x3ffae710 );\nPROVIDE ( r_ip_funcs_p = 0x3ffae70c );\nPROVIDE ( r_ke_check_malloc = 0x40019de0 );\nPROVIDE ( r_ke_event_callback_set = 0x40019ba8 );\nPROVIDE ( r_ke_event_clear = 0x40019c2c );\nPROVIDE ( r_ke_event_flush = 0x40019ccc );\nPROVIDE ( r_ke_event_get = 0x40019c78 );\nPROVIDE ( r_ke_event_get_all = 0x40019cc0 );\nPROVIDE ( r_ke_event_init = 0x40019b90 );\nPROVIDE ( r_ke_event_schedule = 0x40019cdc );\nPROVIDE ( r_ke_event_set = 0x40019be0 );\nPROVIDE ( r_ke_flush = 0x4001a374 );\nPROVIDE ( r_ke_free = 0x4001a014 );\nPROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 );\nPROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 );\nPROVIDE ( r_ke_init = 0x4001a318 );\nPROVIDE ( r_ke_is_free = 0x4001a184 );\nPROVIDE ( r_ke_malloc = 0x40019eb4 );\nPROVIDE ( r_ke_mem_init = 0x40019d3c );\nPROVIDE ( r_ke_mem_is_empty = 0x40019d8c );\nPROVIDE ( r_ke_msg_alloc = 0x4001a1e0 );\nPROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 );\nPROVIDE ( r_ke_msg_discard = 0x4001a850 );\nPROVIDE ( r_ke_msg_forward = 0x4001a290 );\nPROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac );\nPROVIDE ( r_ke_msg_free = 0x4001a2cc );\nPROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 );\nPROVIDE ( r_ke_msg_save = 0x4001a858 );\nPROVIDE ( r_ke_msg_send = 0x4001a234 );\nPROVIDE ( r_ke_msg_send_basic = 0x4001a26c );\nPROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec );\nPROVIDE ( r_ke_queue_extract = 0x40055fd0 );\nPROVIDE ( r_ke_queue_insert = 0x40056020 );\nPROVIDE ( r_ke_sleep_check = 0x4001a3d8 );\nPROVIDE ( r_ke_state_get = 0x4001a7d8 );\nPROVIDE ( r_ke_state_set = 0x4001a6fc );\nPROVIDE ( r_ke_stats_get = 0x4001a3f0 );\nPROVIDE ( r_ke_task_check = 0x4001a8a4 );\nPROVIDE ( r_ke_task_create = 0x4001a674 );\nPROVIDE ( r_ke_task_delete = 0x4001a6c0 );\nPROVIDE ( r_ke_task_init = 0x4001a650 );\nPROVIDE ( r_ke_task_msg_flush = 0x4001a860 );\nPROVIDE ( r_ke_timer_active = 0x4001ac08 );\nPROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 );\nPROVIDE ( r_ke_timer_clear = 0x4001ab90 );\nPROVIDE ( r_ke_timer_init = 0x4001aa9c );\nPROVIDE ( r_ke_timer_set = 0x4001aac0 );\nPROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 );\nPROVIDE ( r_KPrimC = 0x40010ad4 );\nPROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 );\nPROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 );\nPROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 );\nPROVIDE ( r_lb_init = 0x4001acd4 );\nPROVIDE ( r_lb_mst_key = 0x4001afc0 );\nPROVIDE ( r_lb_mst_key_cmp = 0x4001af74 );\nPROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 );\nPROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 );\nPROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c );\nPROVIDE ( r_lb_reset = 0x4001ad38 );\nPROVIDE ( r_lb_send_lmp = 0x4001adbc );\nPROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c );\nPROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 );\nPROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 );\nPROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 );\nPROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c );\nPROVIDE ( r_lc_afh_set = 0x4001cc74 );\nPROVIDE ( r_lc_afh_start = 0x4001d240 );\nPROVIDE ( r_lc_auth_cmp = 0x4001cd54 );\nPROVIDE ( r_lc_calc_link_key = 0x4001ce7c );\nPROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 );\nPROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc );\nPROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac );\nPROVIDE ( r_lc_chk_to = 0x4001d2a8 );\nPROVIDE ( r_lc_cmd_stat_send = 0x4001c914 );\nPROVIDE ( r_lc_comb_key_svr = 0x4001d30c );\nPROVIDE ( r_lc_con_cmp = 0x4001d44c );\nPROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc );\nPROVIDE ( r_lc_conn_seq_done = 0x40021334 );\nPROVIDE ( r_lc_detach = 0x4002037c );\nPROVIDE ( r_lc_dhkey = 0x4001d564 );\nPROVIDE ( r_lc_enc_cmp = 0x4001d8bc );\nPROVIDE ( r_lc_enc_key_refresh = 0x4001d720 );\nPROVIDE ( r_lc_end_chk_colli = 0x4001d858 );\nPROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 );\nPROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 );\nPROVIDE ( r_lc_epr_change_lk = 0x4001db38 );\nPROVIDE ( r_lc_epr_cmp = 0x4001da88 );\nPROVIDE ( r_lc_epr_resp = 0x4001e0b4 );\nPROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 );\nPROVIDE ( r_lc_ext_feat = 0x40020d6c );\nPROVIDE ( r_lc_feat = 0x40020984 );\nPROVIDE ( r_lc_hl_connect = 0x400209e8 );\nPROVIDE ( r_lc_init = 0x4001c948 );\nPROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 );\nPROVIDE ( r_lc_initiator_epr = 0x4001e064 );\nPROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 );\nPROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 );\nPROVIDE ( r_lc_key_exch_end = 0x4001e140 );\nPROVIDE ( r_lc_legacy_pair = 0x4001e1c0 );\nPROVIDE ( r_lc_local_switch = 0x4001e22c );\nPROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 );\nPROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 );\nPROVIDE ( r_lc_loc_auth = 0x40020ecc );\nPROVIDE ( r_lc_locepr_lkref = 0x4001d648 );\nPROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 );\nPROVIDE ( r_lc_loc_sniff = 0x40020a6c );\nPROVIDE ( r_lc_max_slot_mgt = 0x4001e410 );\nPROVIDE ( r_lc_mst_key = 0x4001e7c0 );\nPROVIDE ( r_lc_mst_qos_done = 0x4001ea80 );\nPROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 );\nPROVIDE ( r_lc_mutual_auth_end = 0x4001e670 );\nPROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 );\nPROVIDE ( r_lc_packet_type = 0x40021038 );\nPROVIDE ( r_lc_pair = 0x40020ddc );\nPROVIDE ( r_lc_pairing_cont = 0x4001eafc );\nPROVIDE ( r_lc_passkey_comm = 0x4001ed20 );\nPROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 );\nPROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec );\nPROVIDE ( r_lc_ptt = 0x4001ee2c );\nPROVIDE ( r_lc_ptt_cmp = 0x4001eeec );\nPROVIDE ( r_lc_qos_setup = 0x4001ef50 );\nPROVIDE ( r_lc_rd_rem_name = 0x4001efd0 );\nPROVIDE ( r_lc_release = 0x4001f8a8 );\nPROVIDE ( r_lc_rem_enc = 0x4001f124 );\nPROVIDE ( r_lc_rem_name_cont = 0x4001f290 );\nPROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 );\nPROVIDE ( r_lc_rem_sniff = 0x40020ca4 );\nPROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 );\nPROVIDE ( r_lc_rem_switch = 0x4001f070 );\nPROVIDE ( r_lc_rem_trans_mode = 0x4001f314 );\nPROVIDE ( r_lc_rem_unsniff = 0x400207a0 );\nPROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c );\nPROVIDE ( r_lc_reset = 0x4001c99c );\nPROVIDE ( r_lc_resp_auth = 0x4001f518 );\nPROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 );\nPROVIDE ( r_lc_resp_num_comp = 0x40020074 );\nPROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 );\nPROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c );\nPROVIDE ( r_lc_resp_pair = 0x400208a4 );\nPROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 );\nPROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c );\nPROVIDE ( r_lc_restart_enc = 0x4001f8ec );\nPROVIDE ( r_lc_restart_enc_cont = 0x4001f940 );\nPROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 );\nPROVIDE ( r_lc_restore_to = 0x4001f9e0 );\nPROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 );\nPROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 );\nPROVIDE ( r_lc_rsw_done = 0x4001db94 );\nPROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 );\nPROVIDE ( r_lc_sco_detach = 0x40021e40 );\nPROVIDE ( r_lc_sco_host_accept = 0x40022118 );\nPROVIDE ( r_lc_sco_host_reject = 0x400222b8 );\nPROVIDE ( r_lc_sco_host_request = 0x40021f4c );\nPROVIDE ( r_lc_sco_host_request_disc = 0x4002235c );\nPROVIDE ( r_lc_sco_init = 0x40021dc8 );\nPROVIDE ( r_lc_sco_peer_accept = 0x40022780 );\nPROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 );\nPROVIDE ( r_lc_sco_peer_reject = 0x40022824 );\nPROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c );\nPROVIDE ( r_lc_sco_peer_request = 0x4002240c );\nPROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec );\nPROVIDE ( r_lc_sco_release = 0x40021eec );\nPROVIDE ( r_lc_sco_reset = 0x40021dfc );\nPROVIDE ( r_lc_sco_timeout = 0x40022bd4 );\nPROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec );\nPROVIDE ( r_lc_semi_key_cmp = 0x40020294 );\nPROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c );\nPROVIDE ( r_lc_send_enc_mode = 0x40020220 );\nPROVIDE ( r_lc_send_lmp = 0x4001c1a8 );\nPROVIDE ( r_lc_send_pdu_acc = 0x4001c21c );\nPROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 );\nPROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 );\nPROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 );\nPROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c );\nPROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 );\nPROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 );\nPROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 );\nPROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 );\nPROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 );\nPROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 );\nPROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 );\nPROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec );\nPROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 );\nPROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 );\nPROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c );\nPROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c );\nPROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 );\nPROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec );\nPROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c );\nPROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 );\nPROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 );\nPROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 );\nPROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 );\nPROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 );\nPROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c );\nPROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 );\nPROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 );\nPROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 );\nPROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 );\nPROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 );\nPROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 );\nPROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 );\nPROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 );\nPROVIDE ( r_lc_send_pdu_sres = 0x4001c548 );\nPROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc );\nPROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 );\nPROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 );\nPROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 );\nPROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc );\nPROVIDE ( r_lc_sniff_init = 0x40022cac );\nPROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 );\nPROVIDE ( r_lc_sniff_reset = 0x40022cc8 );\nPROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 );\nPROVIDE ( r_lc_sniff_sub_mode = 0x400204fc );\nPROVIDE ( r_lc_sp_end = 0x400213a8 );\nPROVIDE ( r_lc_sp_fail = 0x40020470 );\nPROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc );\nPROVIDE ( r_lc_ssr_nego = 0x4002125c );\nPROVIDE ( r_lc_start = 0x4001ca28 );\nPROVIDE ( r_lc_start_enc = 0x4001fb28 );\nPROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c );\nPROVIDE ( r_lc_start_key_exch = 0x4001fe10 );\nPROVIDE ( r_lc_start_lmp_to = 0x4001fae8 );\nPROVIDE ( r_lc_start_oob = 0x4001fffc );\nPROVIDE ( r_lc_start_passkey = 0x4001feac );\nPROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 );\nPROVIDE ( r_lc_stop_afh_report = 0x40020184 );\nPROVIDE ( r_lc_stop_enc = 0x40020110 );\nPROVIDE ( r_lc_switch_cmp = 0x40020448 );\nPROVIDE ( r_lc_unit_key_svr = 0x400206d8 );\nPROVIDE ( r_lc_unsniff = 0x40020c50 );\nPROVIDE ( r_lc_unsniff_cmp = 0x40020810 );\nPROVIDE ( r_lc_unsniff_cont = 0x40020750 );\nPROVIDE ( r_lc_upd_to = 0x4002065c );\nPROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 );\nPROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac );\nPROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 );\nPROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c );\nPROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 );\nPROVIDE ( r_lc_version = 0x40020a30 );\nPROVIDE ( lmp_accepted_ext_handler = 0x40027290 );\nPROVIDE ( lmp_not_accepted_ext_handler = 0x40029c54 );\nPROVIDE ( lmp_clk_adj_handler = 0x40027468 );\nPROVIDE ( lmp_clk_adj_ack_handler = 0x400274f4 );\nPROVIDE ( lmp_clk_adj_req_handler = 0x4002751c );\nPROVIDE ( lmp_feats_res_ext_handler = 0x4002cac4 );\nPROVIDE ( lmp_feats_req_ext_handler = 0x4002ccb0 );\nPROVIDE ( lmp_pkt_type_tbl_req_handler = 0x40027574 );\nPROVIDE ( lmp_esco_link_req_handler = 0x40027610 );\nPROVIDE ( lmp_rmv_esco_link_req_handler = 0x400276e8 );\nPROVIDE ( lmp_ch_class_req_handler = 0x40027730 );\nPROVIDE ( lmp_ch_class_handler = 0x4002ca18 );\nPROVIDE ( lmp_ssr_req_handler = 0x4002780c );\nPROVIDE ( lmp_ssr_res_handler = 0x40027900 );\nPROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );\nPROVIDE ( lmp_pause_enc_req_handler = 0x4002df90 );\nPROVIDE ( lmp_resume_enc_req_handler = 0x4002e084 );\nPROVIDE ( lmp_num_comparison_fail_handler = 0x40027a74 );\nPROVIDE ( lmp_passkey_fail_handler = 0x40027aec );\nPROVIDE ( lmp_keypress_notif_handler = 0x4002c5c8 );\nPROVIDE ( lmp_pwr_ctrl_req_handler = 0x400263bc );\nPROVIDE ( lmp_pwr_ctrl_res_handler = 0x40026480 );\nPROVIDE ( lmp_auto_rate_handler = 0x40026548 );\nPROVIDE ( lmp_pref_rate_handler = 0x4002657c );\nPROVIDE ( lmp_name_req_handler = 0x40025050 );\nPROVIDE ( lmp_name_res_handler = 0x400250bc );\nPROVIDE ( lmp_not_accepted_handler = 0x400251d0 );\nPROVIDE ( lmp_accepted_handler = 0x4002e894 );\nPROVIDE ( lmp_clk_off_req_handler = 0x40025a44 );\nPROVIDE ( lmp_clk_off_res_handler = 0x40025ab8 );\nPROVIDE ( lmp_detach_handler = 0x40025b74 );\nPROVIDE ( lmp_tempkey_handler = 0x4002b6b0 );\nPROVIDE ( lmp_temprand_handler = 0x4002b74c );\nPROVIDE ( lmp_sres_handler = 0x4002b840 );\nPROVIDE ( lmp_aurand_handler = 0x4002bda0 );\nPROVIDE ( lmp_unitkey_handler = 0x4002c13c );\nPROVIDE ( lmp_combkey_handler = 0x4002c234 );\nPROVIDE ( lmp_inrand_handler = 0x4002c414 );\nPROVIDE ( lmp_oob_fail_handler = 0x40027b84 );\nPROVIDE ( lmp_ping_req_handler = 0x40027c08 );\nPROVIDE ( lmp_ping_res_handler = 0x40027c5c );\nPROVIDE ( lmp_enc_mode_req_handler = 0x40025c60 );\nPROVIDE ( lmp_enc_key_size_req_handler = 0x40025e54 );\nPROVIDE ( lmp_switch_req_handler = 0x40025f84 );\nPROVIDE ( lmp_start_enc_req_handler = 0x4002e124 );\nPROVIDE ( lmp_stop_enc_req_handler = 0x4002de30 );\nPROVIDE ( lmp_sniff_req_handler = 0x400260c8 );\nPROVIDE ( lmp_unsniff_req_handler = 0x400261e0 );\nPROVIDE ( lmp_incr_pwr_req_handler = 0x4002629c );\nPROVIDE ( lmp_decr_pwr_req_handler = 0x400262f8 );\nPROVIDE ( lmp_max_pwr_handler = 0x40026354 );\nPROVIDE ( lmp_min_pwr_handler = 0x40026388 );\nPROVIDE ( lmp_ver_req_handler = 0x400265f0 );\nPROVIDE ( lmp_ver_res_handler = 0x40026670 );\nPROVIDE ( lmp_qos_handler = 0x40026790 );\nPROVIDE ( lmp_qos_req_handler = 0x40026844 );\nPROVIDE ( lmp_sco_link_req_handler = 0x40026930 );\nPROVIDE ( lmp_rmv_sco_link_req_handler = 0x40026a10 );\nPROVIDE ( lmp_max_slot_handler = 0x40026a54 );\nPROVIDE ( lmp_max_slot_req_handler = 0x40026aac );\nPROVIDE ( lmp_timing_accu_req_handler = 0x40026b54 );\nPROVIDE ( lmp_timing_accu_res_handler = 0x40026bcc );\nPROVIDE ( lmp_setup_cmp_handler = 0x40026c84 );\nPROVIDE ( lmp_feats_res_handler = 0x4002b548 );\nPROVIDE ( lmp_feats_req_handler = 0x4002b620 );\nPROVIDE ( lmp_host_con_req_handler = 0x4002b3d8 );\nPROVIDE ( lmp_use_semi_perm_key_handler = 0x4002b4c4 );\nPROVIDE ( lmp_slot_off_handler = 0x40026cc8 );\nPROVIDE ( lmp_page_mode_req_handler = 0x40026d0c );\nPROVIDE ( lmp_page_scan_mode_req_handler = 0x40026d4c );\nPROVIDE ( lmp_supv_to_handler = 0x40026d94 );\nPROVIDE ( lmp_test_activate_handler = 0x40026e7c );\nPROVIDE ( lmp_test_ctrl_handler = 0x40026ee4 );\nPROVIDE ( lmp_enc_key_size_mask_req_handler = 0x40027038 );\nPROVIDE ( lmp_enc_key_size_mask_res_handler = 0x400270a4 );\nPROVIDE ( lmp_set_afh_handler = 0x4002b2e4 );\nPROVIDE ( lmp_encaps_hdr_handler = 0x40027120 );\nPROVIDE ( lmp_encaps_payl_handler = 0x4002e590 );\nPROVIDE ( lmp_sp_nb_handler = 0x4002acf0 );\nPROVIDE ( lmp_sp_cfm_handler = 0x4002b170 );\nPROVIDE ( lmp_dhkey_chk_handler = 0x4002ab48 );\nPROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );\nPROVIDE ( lmp_io_cap_res_handler = 0x4002c670 );\nPROVIDE ( lmp_io_cap_req_handler = 0x4002c7a4 );\nPROVIDE ( ld_acl_tx_packet_type_select = 0x4002fb40 );\nPROVIDE ( ld_acl_sched = 0x40033268 );\nPROVIDE ( ld_acl_sniff_sched = 0x4003340c );\nPROVIDE ( lm_cmd_cmp_send = 0x40051838 );\nPROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 );\nPROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 );\nPROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 );\nPROVIDE ( r_ld_acl_afh_set = 0x40036b60 );\nPROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 );\nPROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 );\nPROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 );\nPROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 );\nPROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 );\nPROVIDE ( r_ld_acl_clk_set = 0x40036950 );\nPROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 );\nPROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 );\nPROVIDE ( r_ld_acl_data_flush = 0x400357bc );\nPROVIDE ( r_ld_acl_data_tx = 0x4003544c );\nPROVIDE ( r_ld_acl_edr_set = 0x4003678c );\nPROVIDE ( r_ld_acl_enc_key_load = 0x40036404 );\nPROVIDE ( r_ld_acl_flow_off = 0x40035400 );\nPROVIDE ( r_ld_acl_flow_on = 0x4003541c );\nPROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c );\nPROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 );\nPROVIDE ( r_ld_acl_init = 0x40034d08 );\nPROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 );\nPROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 );\nPROVIDE ( r_ld_acl_lsto_get = 0x400366b4 );\nPROVIDE ( r_ld_acl_lsto_set = 0x400366f8 );\nPROVIDE ( r_ld_acl_reset = 0x40034d24 );\nPROVIDE ( r_ld_acl_role_get = 0x40036b30 );\nPROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 );\nPROVIDE ( r_ld_acl_rsw_req = 0x40035e74 );\nPROVIDE ( r_ld_acl_rx_enc = 0x40036344 );\nPROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 );\nPROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 );\nPROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c );\nPROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 );\nPROVIDE ( r_ld_acl_sniff = 0x4003617c );\nPROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 );\nPROVIDE ( r_ld_acl_ssr_set = 0x40036274 );\nPROVIDE ( r_ld_acl_start = 0x40034ddc );\nPROVIDE ( r_ld_acl_stop = 0x4003532c );\nPROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 );\nPROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c );\nPROVIDE ( r_ld_acl_t_poll_get = 0x40036024 );\nPROVIDE ( r_ld_acl_t_poll_set = 0x40036068 );\nPROVIDE ( r_ld_acl_tx_enc = 0x400362f8 );\nPROVIDE ( r_ld_acl_unsniff = 0x400361e0 );\nPROVIDE ( r_ld_active_check = 0x4003cac4 );\nPROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec );\nPROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c );\nPROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 );\nPROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc );\nPROVIDE ( r_ld_bcst_acl_start = 0x4003882c );\nPROVIDE ( r_ld_bcst_afh_update = 0x40038f3c );\nPROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c );\nPROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 );\nPROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 );\nPROVIDE ( r_ld_bd_addr_get = 0x4003ca20 );\nPROVIDE ( r_ld_channel_assess = 0x4003c184 );\nPROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 );\nPROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 );\nPROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 );\nPROVIDE ( r_ld_csb_rx_init = 0x40039690 );\nPROVIDE ( r_ld_csb_rx_reset = 0x4003969c );\nPROVIDE ( r_ld_csb_rx_start = 0x4003972c );\nPROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 );\nPROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc );\nPROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c );\nPROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 );\nPROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 );\nPROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 );\nPROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 );\nPROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 );\nPROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 );\nPROVIDE ( r_ld_fm_frame_isr = 0x4003a82c );\nPROVIDE ( r_ld_fm_init = 0x4003a760 );\nPROVIDE ( r_ld_fm_prog_check = 0x4003ab28 );\nPROVIDE ( r_ld_fm_prog_disable = 0x4003a984 );\nPROVIDE ( r_ld_fm_prog_enable = 0x4003a944 );\nPROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 );\nPROVIDE ( r_ld_fm_reset = 0x4003a794 );\nPROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 );\nPROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 );\nPROVIDE ( r_ld_init = 0x4003c294 );\nPROVIDE ( r_ld_inq_init = 0x4003b15c );\nPROVIDE ( r_ld_inq_reset = 0x4003b168 );\nPROVIDE ( r_ld_inq_start = 0x4003b1f0 );\nPROVIDE ( r_ld_inq_stop = 0x4003b4f0 );\nPROVIDE ( r_ld_iscan_eir_get = 0x4003c118 );\nPROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 );\nPROVIDE ( r_ld_iscan_init = 0x4003b9f0 );\nPROVIDE ( r_ld_iscan_reset = 0x4003ba14 );\nPROVIDE ( r_ld_iscan_restart = 0x4003ba44 );\nPROVIDE ( r_ld_iscan_start = 0x4003bb28 );\nPROVIDE ( r_ld_iscan_stop = 0x4003bf1c );\nPROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 );\nPROVIDE ( r_ld_page_init = 0x4003d808 );\nPROVIDE ( r_ld_page_reset = 0x4003d814 );\nPROVIDE ( r_ld_page_start = 0x4003d848 );\nPROVIDE ( r_ld_page_stop = 0x4003da54 );\nPROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 );\nPROVIDE ( r_ld_pca_init = 0x4003deb4 );\nPROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac );\nPROVIDE ( r_ld_pca_local_config = 0x4003df6c );\nPROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 );\nPROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 );\nPROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 );\nPROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 );\nPROVIDE ( r_ld_pca_reset = 0x4003df0c );\nPROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 );\nPROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 );\nPROVIDE ( r_ld_pscan_init = 0x4003f474 );\nPROVIDE ( r_ld_pscan_reset = 0x4003f498 );\nPROVIDE ( r_ld_pscan_restart = 0x4003f4b8 );\nPROVIDE ( r_ld_pscan_start = 0x4003f514 );\nPROVIDE ( r_ld_pscan_stop = 0x4003f618 );\nPROVIDE ( r_ld_read_clock = 0x4003c9e4 );\nPROVIDE ( r_ld_reset = 0x4003c714 );\nPROVIDE ( r_ld_sched_acl_add = 0x4003f978 );\nPROVIDE ( r_ld_sched_acl_remove = 0x4003f99c );\nPROVIDE ( r_ld_sched_compute = 0x4003f6f8 );\nPROVIDE ( r_ld_sched_init = 0x4003f7ac );\nPROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 );\nPROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 );\nPROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 );\nPROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 );\nPROVIDE ( r_ld_sched_page_add = 0x4003f910 );\nPROVIDE ( r_ld_sched_page_remove = 0x4003f938 );\nPROVIDE ( r_ld_sched_pscan_add = 0x4003f828 );\nPROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 );\nPROVIDE ( r_ld_sched_reset = 0x4003f7d4 );\nPROVIDE ( r_ld_sched_sco_add = 0x4003fa4c );\nPROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c );\nPROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 );\nPROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c );\nPROVIDE ( r_ld_sched_sscan_add = 0x4003f868 );\nPROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 );\nPROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 );\nPROVIDE ( r_ld_sco_data_tx = 0x40037ee8 );\nPROVIDE ( r_ld_sco_start = 0x40037110 );\nPROVIDE ( r_ld_sco_stop = 0x40037c40 );\nPROVIDE ( r_ld_sco_update = 0x40037a74 );\nPROVIDE ( r_ld_sscan_activated = 0x4004031c );\nPROVIDE ( r_ld_sscan_init = 0x400402f0 );\nPROVIDE ( r_ld_sscan_reset = 0x400402fc );\nPROVIDE ( r_ld_sscan_start = 0x40040384 );\nPROVIDE ( r_ld_strain_init = 0x400409f4 );\nPROVIDE ( r_ld_strain_reset = 0x40040a00 );\nPROVIDE ( r_ld_strain_start = 0x40040a8c );\nPROVIDE ( r_ld_strain_stop = 0x40040df0 );\nPROVIDE ( r_ld_timing_accuracy_get = 0x4003caac );\nPROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c );\nPROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 );\nPROVIDE ( r_ld_util_bch_create = 0x40040fcc );\nPROVIDE ( r_ld_util_fhs_pk = 0x400411c8 );\nPROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 );\nPROVIDE ( r_ld_util_stp_pk = 0x400413f4 );\nPROVIDE ( r_ld_util_stp_unpk = 0x40041324 );\nPROVIDE ( r_ld_version_get = 0x4003ca6c );\nPROVIDE ( r_ld_wlcoex_set = 0x4003caf8 );\nPROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 );\nPROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c );\nPROVIDE ( r_llc_ch_assess_local = 0x40041494 );\nPROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 );\nPROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 );\nPROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac );\nPROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 );\nPROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c );\nPROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 );\nPROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c );\nPROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 );\nPROVIDE ( r_llc_con_update_complete_send = 0x40044d68 );\nPROVIDE ( r_llc_con_update_finished = 0x4004518c );\nPROVIDE ( r_llc_con_update_ind = 0x40045038 );\nPROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 );\nPROVIDE ( r_llc_end_evt_defer = 0x40046330 );\nPROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c );\nPROVIDE ( r_llc_init = 0x40044778 );\nPROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 );\nPROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 );\nPROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc );\nPROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 );\nPROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 );\nPROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 );\nPROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 );\nPROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 );\nPROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 );\nPROVIDE ( r_llc_llcp_get_autorize = 0x4004475c );\nPROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 );\nPROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac );\nPROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 );\nPROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 );\nPROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c );\nPROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 );\nPROVIDE ( r_llc_llcp_recv_handler = 0x40044678 );\nPROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c );\nPROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c );\nPROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 );\nPROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 );\nPROVIDE ( r_llc_llcp_tester_send = 0x400445e4 );\nPROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 );\nPROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c );\nPROVIDE ( r_llc_lsto_con_update = 0x40045098 );\nPROVIDE ( r_llc_ltk_req_send = 0x40044dc0 );\nPROVIDE ( r_llc_map_update_finished = 0x40045260 );\nPROVIDE ( r_llc_map_update_ind = 0x400450f0 );\nPROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc );\nPROVIDE ( r_llc_pdu_defer = 0x40046528 );\nPROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac );\nPROVIDE ( r_llc_reset = 0x400447b8 );\nPROVIDE ( r_llc_start = 0x400447f4 );\nPROVIDE ( r_llc_stop = 0x400449ac );\nPROVIDE ( r_llc_util_bw_mgt = 0x4004629c );\nPROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 );\nPROVIDE ( r_llc_util_dicon_procedure = 0x40046130 );\nPROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 );\nPROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 );\nPROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 );\nPROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 );\nPROVIDE ( r_llc_util_update_channel_map = 0x400461ac );\nPROVIDE ( r_llc_version_rd_event_send = 0x40044e60 );\nPROVIDE ( r_lld_adv_start = 0x40048b38 );\nPROVIDE ( r_lld_adv_stop = 0x40048ea0 );\nPROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 );\nPROVIDE ( r_lld_con_param_req = 0x40049f0c );\nPROVIDE ( r_lld_con_param_rsp = 0x40049e00 );\nPROVIDE ( r_lld_con_start = 0x400491f8 );\nPROVIDE ( r_lld_con_stop = 0x40049fdc );\nPROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc );\nPROVIDE ( r_lld_con_update_ind = 0x4004a30c );\nPROVIDE ( r_lld_con_update_req = 0x40049b60 );\nPROVIDE ( r_lld_core_reset = 0x40048a9c );\nPROVIDE ( r_lld_crypt_isr = 0x4004a324 );\nPROVIDE ( r_lld_evt_adv_create = 0x400481f4 );\nPROVIDE ( r_lld_evt_canceled = 0x400485c8 );\nPROVIDE ( r_lld_evt_channel_next = 0x40046aac );\nPROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc );\nPROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 );\nPROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c );\nPROVIDE ( r_lld_evt_drift_compute = 0x40047670 );\nPROVIDE ( r_lld_evt_elt_delete = 0x40047538 );\nPROVIDE ( r_lld_evt_elt_insert = 0x400474c8 );\nPROVIDE ( r_lld_evt_end = 0x400483e8 );\nPROVIDE ( r_lld_evt_end_isr = 0x4004862c );\nPROVIDE ( r_lld_evt_init = 0x40046b3c );\nPROVIDE ( r_lld_evt_init_evt = 0x40046cd0 );\nPROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 );\nPROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 );\nPROVIDE ( r_lld_evt_prevent_stop = 0x40047adc );\nPROVIDE ( r_lld_evt_restart = 0x40046d50 );\nPROVIDE ( r_lld_evt_rx = 0x40048578 );\nPROVIDE ( r_lld_evt_rx_isr = 0x40048678 );\nPROVIDE ( r_lld_evt_scan_create = 0x40047ae8 );\nPROVIDE ( r_lld_evt_schedule = 0x40047908 );\nPROVIDE ( r_lld_evt_schedule_next = 0x400477dc );\nPROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 );\nPROVIDE ( r_lld_evt_slave_update = 0x40048138 );\nPROVIDE ( r_lld_evt_update_create = 0x40047cd8 );\nPROVIDE ( r_lld_get_mode = 0x40049ff8 );\nPROVIDE ( r_lld_init = 0x4004873c );\nPROVIDE ( r_lld_move_to_master = 0x400499e0 );\nPROVIDE ( r_lld_move_to_slave = 0x4004a024 );\nPROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 );\nPROVIDE ( r_lld_pdu_check = 0x4004ac34 );\nPROVIDE ( r_lld_pdu_data_send = 0x4004b018 );\nPROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc );\nPROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 );\nPROVIDE ( r_lld_pdu_send_packet = 0x4004b774 );\nPROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 );\nPROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 );\nPROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 );\nPROVIDE ( r_lld_pdu_tx_push = 0x4004b080 );\nPROVIDE ( r_lld_ral_renew_req = 0x4004a73c );\nPROVIDE ( r_lld_scan_start = 0x40048ee0 );\nPROVIDE ( r_lld_scan_stop = 0x40049190 );\nPROVIDE ( r_lld_test_mode_rx = 0x4004a540 );\nPROVIDE ( r_lld_test_mode_tx = 0x4004a350 );\nPROVIDE ( r_lld_test_stop = 0x4004a710 );\nPROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc );\nPROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c );\nPROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 );\nPROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 );\nPROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 );\nPROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 );\nPROVIDE ( r_lld_util_flush_list = 0x4004bbd8 );\nPROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 );\nPROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac );\nPROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 );\nPROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 );\nPROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 );\nPROVIDE ( r_lld_util_instant_get = 0x4004b890 );\nPROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc );\nPROVIDE ( r_lld_util_priority_set = 0x4004bd10 );\nPROVIDE ( r_lld_util_priority_update = 0x4004bd78 );\nPROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 );\nPROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 );\nPROVIDE ( r_lld_wlcoex_set = 0x4004bd98 );\nPROVIDE ( r_llm_ble_ready = 0x4004cc34 );\nPROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 );\nPROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 );\nPROVIDE ( r_llm_con_req_ind = 0x4004cc54 );\nPROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 );\nPROVIDE ( r_llm_create_con = 0x4004de78 );\nPROVIDE ( r_llm_encryption_done = 0x4004dff8 );\nPROVIDE ( r_llm_encryption_start = 0x4004e128 );\nPROVIDE ( r_llm_end_evt_defer = 0x4004eb6c );\nPROVIDE ( r_llm_init = 0x4004c9f8 );\nPROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 );\nPROVIDE ( r_llm_pdu_defer = 0x4004ec48 );\nPROVIDE ( r_llm_ral_clear = 0x4004e1fc );\nPROVIDE ( r_llm_ral_dev_add = 0x4004e23c );\nPROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc );\nPROVIDE ( r_llm_ral_get_rpa = 0x4004e400 );\nPROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 );\nPROVIDE ( r_llm_ral_update = 0x4004e4f8 );\nPROVIDE ( r_llm_set_adv_data = 0x4004d960 );\nPROVIDE ( r_llm_set_adv_en = 0x4004d7ec );\nPROVIDE ( r_llm_set_adv_param = 0x4004d5f4 );\nPROVIDE ( r_llm_set_scan_en = 0x4004db64 );\nPROVIDE ( r_llm_set_scan_param = 0x4004dac8 );\nPROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 );\nPROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 );\nPROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc );\nPROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc );\nPROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 );\nPROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 );\nPROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 );\nPROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 );\nPROVIDE ( r_llm_util_bl_add = 0x4004e9ac );\nPROVIDE ( r_llm_util_bl_check = 0x4004e930 );\nPROVIDE ( r_llm_util_bl_rem = 0x4004ea70 );\nPROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 );\nPROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 );\nPROVIDE ( r_llm_util_check_map_validity = 0x4004e800 );\nPROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 );\nPROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 );\nPROVIDE ( r_llm_util_set_public_addr = 0x4004e89c );\nPROVIDE ( r_llm_wl_clr = 0x4004dc54 );\nPROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 );\nPROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 );\nPROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc );\nPROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 );\nPROVIDE ( r_lm_acl_disc = 0x4004f148 );\nPROVIDE ( r_LM_AddSniff = 0x40022d20 );\nPROVIDE ( r_lm_add_sync = 0x40051358 );\nPROVIDE ( r_lm_afh_activate_timer = 0x4004f444 );\nPROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 );\nPROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 );\nPROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c );\nPROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 );\nPROVIDE ( r_lm_check_active_sync = 0x40051334 );\nPROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c );\nPROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 );\nPROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c );\nPROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 );\nPROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 );\nPROVIDE ( r_LM_ComputePacketType = 0x4002f554 );\nPROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac );\nPROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 );\nPROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 );\nPROVIDE ( r_lm_dhkey_calc_init = 0x40013234 );\nPROVIDE ( r_lm_dhkey_compare = 0x400132d8 );\nPROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec );\nPROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 );\nPROVIDE ( r_lm_f1 = 0x40012bb8 );\nPROVIDE ( r_lm_f2 = 0x40012cfc );\nPROVIDE ( r_lm_f3 = 0x40013050 );\nPROVIDE ( r_lm_g = 0x40012f90 );\nPROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c );\nPROVIDE ( r_lm_get_auth_en = 0x4004f1ac );\nPROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c );\nPROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 );\nPROVIDE ( r_LM_GetFeature = 0x4002f924 );\nPROVIDE ( r_LM_GetLinkTimeout = 0x400233ec );\nPROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 );\nPROVIDE ( r_lm_get_loopback_mode = 0x4004f248 );\nPROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c );\nPROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 );\nPROVIDE ( r_LM_GetMasterKey = 0x4001b260 );\nPROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 );\nPROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 );\nPROVIDE ( r_lm_get_nb_acl = 0x4004ef9c );\nPROVIDE ( r_lm_get_nb_sync_link = 0x4005179c );\nPROVIDE ( r_lm_get_nonce = 0x400131c4 );\nPROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 );\nPROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 );\nPROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 );\nPROVIDE ( r_LM_GetPINType = 0x4004f1e8 );\nPROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 );\nPROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 );\nPROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 );\nPROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 );\nPROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 );\nPROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 );\nPROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c );\nPROVIDE ( r_lm_get_sp_en = 0x4004f1c0 );\nPROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 );\nPROVIDE ( r_lm_get_synchdl = 0x4005175c );\nPROVIDE ( r_lm_get_sync_param = 0x400503b4 );\nPROVIDE ( r_lm_init = 0x4004ed34 );\nPROVIDE ( r_lm_init_sync = 0x400512d8 );\nPROVIDE ( r_lm_is_acl_con = 0x4004f47c );\nPROVIDE ( r_lm_is_acl_con_role = 0x4004f49c );\nPROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 );\nPROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 );\nPROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 );\nPROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 );\nPROVIDE ( r_lm_look_for_sync = 0x40051774 );\nPROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c );\nPROVIDE ( r_lm_lt_addr_free = 0x4004ef74 );\nPROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 );\nPROVIDE ( r_LM_MakeCof = 0x4002f84c );\nPROVIDE ( r_LM_MakeRandVec = 0x400112d8 );\nPROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 );\nPROVIDE ( r_LM_MaxSlot = 0x4002f694 );\nPROVIDE ( r_lm_modif_sync = 0x40051578 );\nPROVIDE ( r_lm_n_is_zero = 0x40012170 );\nPROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 );\nPROVIDE ( r_lm_oob_f1 = 0x40012e54 );\nPROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 );\nPROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 );\nPROVIDE ( nvds_null_read = 0x400542a0 );\nPROVIDE ( nvds_null_write = 0x400542a8 );\nPROVIDE ( nvds_null_erase = 0x400542b0 );\nPROVIDE ( nvds_read = 0x400542c4 );\nPROVIDE ( nvds_write = 0x400542fc );\nPROVIDE ( nvds_erase = 0x40054334 );\nPROVIDE ( nvds_init_memory = 0x40054358 );\nPROVIDE ( r_lmp_pack = 0x4001135c );\nPROVIDE ( r_lmp_unpack = 0x4001149c );\nPROVIDE ( r_lm_read_features = 0x4004f0d8 );\nPROVIDE ( r_LM_RemoveSniff = 0x40023124 );\nPROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 );\nPROVIDE ( r_lm_remove_sync = 0x400517c8 );\nPROVIDE ( r_lm_reset_sync = 0x40051304 );\nPROVIDE ( r_lm_role_switch_finished = 0x4004f028 );\nPROVIDE ( r_lm_role_switch_start = 0x4004efe0 );\nPROVIDE ( r_lm_sco_nego_end = 0x40051828 );\nPROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 );\nPROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 );\nPROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc );\nPROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 );\nPROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 );\nPROVIDE ( r_lm_sp_n_one = 0x400123a4 );\nPROVIDE ( r_lm_sp_p192_add = 0x40012828 );\nPROVIDE ( r_lm_sp_p192_dbl = 0x4001268c );\nPROVIDE ( r_lm_sp_p192_invert = 0x40012b6c );\nPROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 );\nPROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 );\nPROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 );\nPROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 );\nPROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 );\nPROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 );\nPROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 );\nPROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 );\nPROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 );\nPROVIDE ( r_modules_funcs = 0x3ffafd6c );\nPROVIDE ( r_modules_funcs_p = 0x3ffafd68 );\nPROVIDE ( r_nvds_del = 0x400544c4 );\nPROVIDE ( r_nvds_get = 0x40054488 );\nPROVIDE ( r_nvds_init = 0x40054410 );\nPROVIDE ( r_nvds_lock = 0x400544fc );\nPROVIDE ( r_nvds_put = 0x40054534 );\nPROVIDE ( rom_abs_temp = 0x400054f0 );\nPROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c );\nPROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac );\nPROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 );\nPROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 );\nPROVIDE ( rom_bb_wdg_test_en = 0x40003b70 );\nPROVIDE ( rom_cbw2040_cfg = 0x400040b0 );\nPROVIDE ( rom_check_noise_floor = 0x40003c78 );\nPROVIDE ( rom_chip_i2c_readReg = 0x40004110 );\nPROVIDE ( rom_chip_i2c_writeReg = 0x40004168 );\nPROVIDE ( rom_chip_v7_bt_init = 0x40004d8c );\nPROVIDE ( rom_chip_v7_rx_init = 0x40004cec );\nPROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 );\nPROVIDE ( rom_chip_v7_tx_init = 0x40004d18 );\nPROVIDE ( rom_clk_force_on_vit = 0x40003710 );\nPROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 );\nPROVIDE ( rom_dc_iq_est = 0x400055c8 );\nPROVIDE ( rom_disable_agc = 0x40002fa4 );\nPROVIDE ( rom_enable_agc = 0x40002fcc );\nPROVIDE ( rom_en_pwdet = 0x4000506c );\nPROVIDE ( rom_gen_rx_gain_table = 0x40003e3c );\nPROVIDE ( rom_get_data_sat = 0x4000312c );\nPROVIDE ( rom_get_fm_sar_dout = 0x40005204 );\nPROVIDE ( rom_get_power_db = 0x40005fc8 );\nPROVIDE ( rom_get_pwctrl_correct = 0x400065d4 );\nPROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc );\nPROVIDE ( rom_get_rf_gain_qdb = 0x40006290 );\nPROVIDE ( rom_get_sar_dout = 0x40006564 );\nPROVIDE ( rom_i2c_readReg = 0x40004148 );\nPROVIDE ( rom_i2c_readReg_Mask = 0x400041c0 );\nPROVIDE ( rom_i2c_writeReg = 0x400041a4 );\nPROVIDE ( rom_i2c_writeReg_Mask = 0x400041fc );\nPROVIDE ( rom_index_to_txbbgain = 0x40004df8 );\nPROVIDE ( rom_iq_est_disable = 0x40005590 );\nPROVIDE ( rom_iq_est_enable = 0x40005514 );\nPROVIDE ( rom_linear_to_db = 0x40005f64 );\nPROVIDE ( rom_loopback_mode_en = 0x400030f8 );\nPROVIDE ( rom_meas_tone_pwr_db = 0x40006004 );\nPROVIDE ( rom_mhz2ieee = 0x4000404c );\nPROVIDE ( rom_noise_floor_auto_set = 0x40003bdc );\nPROVIDE ( rom_pbus_debugmode = 0x40004458 );\nPROVIDE ( rom_pbus_force_mode = 0x40004270 );\nPROVIDE ( rom_pbus_force_test = 0x400043c0 );\nPROVIDE ( rom_pbus_rd = 0x40004414 );\nPROVIDE ( rom_pbus_rd_addr = 0x40004334 );\nPROVIDE ( rom_pbus_rd_shift = 0x40004374 );\nPROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 );\nPROVIDE ( rom_pbus_set_dco = 0x40004638 );\nPROVIDE ( rom_pbus_set_rxgain = 0x40004480 );\nPROVIDE ( rom_pbus_workmode = 0x4000446c );\nPROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 );\nPROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c );\nPROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 );\nPROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 );\nPROVIDE ( rom_phy_disable_agc = 0x40002f6c );\nPROVIDE ( rom_phy_disable_cca = 0x40003000 );\nPROVIDE ( rom_phy_enable_agc = 0x40002f88 );\nPROVIDE ( rom_phy_enable_cca = 0x4000302c );\nPROVIDE ( rom_phy_freq_correct = 0x40004b44 );\nPROVIDE ( rom_phyFuns = 0x3ffae0c0 );\nPROVIDE ( rom_phy_get_noisefloor = 0x40003c2c );\nPROVIDE ( rom_phy_get_vdd33 = 0x4000642c );\nPROVIDE ( rom_pow_usr = 0x40003044 );\nPROVIDE ( rom_read_sar_dout = 0x400051c0 );\nPROVIDE ( rom_restart_cal = 0x400046e0 );\nPROVIDE ( rom_rfcal_pwrctrl = 0x40006058 );\nPROVIDE ( rom_rfcal_rxiq = 0x40005b4c );\nPROVIDE ( rom_rfcal_txcap = 0x40005dec );\nPROVIDE ( rom_rfpll_reset = 0x40004680 );\nPROVIDE ( rom_rfpll_set_freq = 0x400047f8 );\nPROVIDE ( rom_rtc_mem_backup = 0x40003db4 );\nPROVIDE ( rom_rtc_mem_recovery = 0x40003df4 );\nPROVIDE ( rom_rx_gain_force = 0x4000351c );\nPROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 );\nPROVIDE ( rom_rxiq_get_mis = 0x400058e4 );\nPROVIDE ( rom_rxiq_set_reg = 0x40005a00 );\nPROVIDE ( rom_set_cal_rxdc = 0x400030b8 );\nPROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 );\nPROVIDE ( rom_set_channel_freq = 0x40004880 );\nPROVIDE ( rom_set_loopback_gain = 0x40003060 );\nPROVIDE ( rom_set_noise_floor = 0x40003d48 );\nPROVIDE ( rom_set_pbus_mem = 0x400031a4 );\nPROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 );\nPROVIDE ( rom_set_rxclk_en = 0x40003594 );\nPROVIDE ( rom_set_txcap_reg = 0x40005d50 );\nPROVIDE ( rom_set_txclk_en = 0x40003564 );\nPROVIDE ( rom_spur_coef_cfg = 0x40003ac8 );\nPROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 );\nPROVIDE ( rom_start_tx_tone = 0x400036b4 );\nPROVIDE ( rom_start_tx_tone_step = 0x400035d0 );\nPROVIDE ( rom_stop_tx_tone = 0x40003f98 );\nPROVIDE ( _rom_store = 0x4000d66c );\nPROVIDE ( _rom_store_table = 0x4000d4f8 );\nPROVIDE ( rom_target_power_add_backoff = 0x40006268 );\nPROVIDE ( rom_tx_atten_set_interp = 0x400061cc );\nPROVIDE ( rom_txbbgain_to_index = 0x40004dc0 );\nPROVIDE ( rom_txcal_work_mode = 0x4000510c );\nPROVIDE ( rom_txdc_cal_init = 0x40004e10 );\nPROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 );\nPROVIDE ( rom_txiq_cover = 0x4000538c );\nPROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc );\nPROVIDE ( rom_txiq_set_reg = 0x40005154 );\nPROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c );\nPROVIDE ( rom_txtone_linear_pwr = 0x40005290 );\nPROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 );\nPROVIDE ( rom_write_gain_mem = 0x4000348c );\nPROVIDE ( rom_write_rfpll_sdm = 0x40004740 );\nPROVIDE ( roundup2 = 0x4000ab7c );\nPROVIDE ( r_plf_funcs_p = 0x3ffb8360 );\nPROVIDE ( r_rf_rw_bt_init = 0x40054868 );\nPROVIDE ( r_rf_rw_init = 0x40054b0c );\nPROVIDE ( r_rf_rw_le_init = 0x400549d0 );\nPROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c );\nPROVIDE ( r_rwble_init = 0x40054bf4 );\nPROVIDE ( r_rwble_isr = 0x40054e08 );\nPROVIDE ( r_rwble_reset = 0x40054ce8 );\nPROVIDE ( r_rwble_sleep_check = 0x40054d78 );\nPROVIDE ( r_rwble_version = 0x40054dac );\nPROVIDE ( r_rwbt_init = 0x40055160 );\nPROVIDE ( r_rwbt_isr = 0x40055248 );\nPROVIDE ( r_rwbt_reset = 0x400551bc );\nPROVIDE ( r_rwbt_sleep_check = 0x4005577c );\nPROVIDE ( r_rwbt_sleep_enter = 0x400557a4 );\nPROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc );\nPROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc );\nPROVIDE ( r_rwbt_version = 0x4005520c );\nPROVIDE ( r_rwip_assert_err = 0x40055f88 );\nPROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc );\nPROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c );\nPROVIDE ( r_rwip_init = 0x4005595c );\nPROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 );\nPROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 );\nPROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 );\nPROVIDE ( r_rwip_reset = 0x40055ab8 );\nPROVIDE ( r_rwip_schedule = 0x40055b38 );\nPROVIDE ( r_rwip_sleep = 0x40055b5c );\nPROVIDE ( r_rwip_sleep_enable = 0x40055f30 );\nPROVIDE ( r_rwip_version = 0x40055b20 );\nPROVIDE ( r_rwip_wakeup = 0x40055dc4 );\nPROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c );\nPROVIDE ( r_rwip_wakeup_end = 0x40055e18 );\nPROVIDE ( r_rwip_wlcoex_set = 0x40055f60 );\nPROVIDE ( r_SHA_256 = 0x40013a90 );\nPROVIDE ( rwip_coex_cfg = 0x3ff9914c );\nPROVIDE ( rwip_priority = 0x3ff99159 );\nPROVIDE ( rwip_rf = 0x3ffbdb28 );\nPROVIDE ( rwip_rf_p_get = 0x400558f4 );\nPROVIDE ( r_XorKey = 0x400112c0 );\nPROVIDE ( sbrk = 0x400017f4 );\nPROVIDE ( _sbrk_r = 0x4000bce4 );\nPROVIDE ( __sccl = 0x4000c498 );\nPROVIDE ( __sclose = 0x400011b8 );\nPROVIDE ( __seofread = 0x40001148 );\nPROVIDE ( setjmp = 0x40056268 );\nPROVIDE ( setlocale = 0x40059568 );\nPROVIDE ( _setlocale_r = 0x4005950c );\nPROVIDE ( __sf_fake_stderr = 0x3ff96458 );\nPROVIDE ( __sf_fake_stdin = 0x3ff96498 );\nPROVIDE ( __sf_fake_stdout = 0x3ff96478 );\nPROVIDE ( __sflush_r = 0x400591e0 );\nPROVIDE ( __sfmoreglue = 0x40001dc8 );\nPROVIDE ( __sfp = 0x40001e90 );\nPROVIDE ( __sfp_lock_acquire = 0x40001e08 );\nPROVIDE ( __sfp_lock_release = 0x40001e14 );\nPROVIDE ( __sfputs_r = 0x40057790 );\nPROVIDE ( __sfvwrite_r = 0x4005893c );\nPROVIDE ( sha1_prf = 0x40060ae8 );\nPROVIDE ( sha1_vector = 0x40060b64 );\nPROVIDE ( sha256_prf = 0x40060d70 );\nPROVIDE ( sha256_vector = 0x40060e08 );\nPROVIDE ( sha_blk_bits = 0x3ff99290 );\nPROVIDE ( sha_blk_bits_bytes = 0x3ff99288 );\nPROVIDE ( sha_blk_hash_bytes = 0x3ff9928c );\nPROVIDE ( sig_matrix = 0x3ffae293 );\nPROVIDE ( __sinit = 0x40001e38 );\nPROVIDE ( __sinit_lock_acquire = 0x40001e20 );\nPROVIDE ( __sinit_lock_release = 0x40001e2c );\nPROVIDE ( sip_after_tx_complete = 0x4000b358 );\nPROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c );\nPROVIDE ( sip_get_ptr = 0x4000b34c );\nPROVIDE ( sip_get_state = 0x4000ae2c );\nPROVIDE ( sip_init_attach = 0x4000ae58 );\nPROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 );\nPROVIDE ( sip_install_rx_data_cb = 0x4000ae20 );\nPROVIDE ( sip_is_active = 0x4000b3c0 );\nPROVIDE ( sip_post_init = 0x4000aed8 );\nPROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc );\nPROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c );\nPROVIDE ( sip_send = 0x4000af54 );\nPROVIDE ( sip_to_host_chain_append = 0x4000aef8 );\nPROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 );\nPROVIDE ( slc_add_credits = 0x4000baf4 );\nPROVIDE ( slc_enable = 0x4000b64c );\nPROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 );\nPROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 );\nPROVIDE ( slc_has_pkt_to_host = 0x4000b5fc );\nPROVIDE ( slc_init_attach = 0x4000b918 );\nPROVIDE ( slc_init_credit = 0x4000badc );\nPROVIDE ( slc_reattach = 0x4000b62c );\nPROVIDE ( slc_send_to_host_chain = 0x4000b6a0 );\nPROVIDE ( slc_set_host_io_max_window = 0x4000b89c );\nPROVIDE ( slc_to_host_chain_recycle = 0x4000b758 );\nPROVIDE ( __smakebuf_r = 0x40059108 );\nPROVIDE ( specialModP256 = 0x4001600c );\nPROVIDE ( srand = 0x40001004 );\nPROVIDE ( __sread = 0x40001118 );\nPROVIDE ( __srefill_r = 0x400593d4 );\nPROVIDE ( __sseek = 0x40001184 );\nPROVIDE ( __ssprint_r = 0x40056ff8 );\nPROVIDE ( __ssputs_r = 0x40056f2c );\nPROVIDE ( __ssrefill_r = 0x40057fec );\nPROVIDE ( __stack = 0x3ffe3f20 );\nPROVIDE ( __stack_app = 0x3ffe7e30 );\nPROVIDE ( _stack_sentry = 0x3ffe1320 );\nPROVIDE ( _stack_sentry_app = 0x3ffe5230 );\nPROVIDE ( _start = 0x40000704 );\nPROVIDE ( start_tb_console = 0x4005a980 );\nPROVIDE ( _stat_r = 0x4000bcb4 );\nPROVIDE ( _stext = 0x40000560 );\nPROVIDE ( strcasecmp = 0x400011cc );\nPROVIDE ( strcasestr = 0x40001210 );\nPROVIDE ( strcat = 0x4000c518 );\nPROVIDE ( strchr = 0x4000c53c );\nPROVIDE ( strcmp = 0x40001274 );\nPROVIDE ( strcoll = 0x40001398 );\nPROVIDE ( strcpy = 0x400013ac );\nPROVIDE ( strcspn = 0x4000c558 );\nPROVIDE ( strdup = 0x4000143c );\nPROVIDE ( _strdup_r = 0x40001450 );\nPROVIDE ( strftime = 0x40059ab4 );\nPROVIDE ( strlcat = 0x40001470 );\nPROVIDE ( strlcpy = 0x4000c584 );\nPROVIDE ( strlen = 0x400014c0 );\nPROVIDE ( strlwr = 0x40001524 );\nPROVIDE ( strncasecmp = 0x40001550 );\nPROVIDE ( strncat = 0x4000c5c4 );\nPROVIDE ( strncmp = 0x4000c5f4 );\nPROVIDE ( strncpy = 0x400015d4 );\nPROVIDE ( strndup = 0x400016b0 );\nPROVIDE ( _strndup_r = 0x400016c4 );\nPROVIDE ( strnlen = 0x4000c628 );\nPROVIDE ( strrchr = 0x40001708 );\nPROVIDE ( strsep = 0x40001734 );\nPROVIDE ( strspn = 0x4000c648 );\nPROVIDE ( strstr = 0x4000c674 );\nPROVIDE ( __strtok_r = 0x4000c6a8 );\nPROVIDE ( strtok_r = 0x4000c70c );\nPROVIDE ( strtol = 0x4005681c );\nPROVIDE ( _strtol_r = 0x40056714 );\nPROVIDE ( strtoul = 0x4005692c );\nPROVIDE ( _strtoul_r = 0x40056834 );\nPROVIDE ( strupr = 0x4000174c );\nPROVIDE ( __subdf3 = 0x400026e4 );\nPROVIDE ( __submore = 0x40058f3c );\nPROVIDE ( __subsf3 = 0x400021d0 );\nPROVIDE ( SubtractBigHex256 = 0x40015bcc );\nPROVIDE ( SubtractBigHexMod256 = 0x40015e8c );\nPROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c );\nPROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 );\nPROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 );\nPROVIDE ( __subvdi3 = 0x40002d20 );\nPROVIDE ( __subvsi3 = 0x40002cf8 );\nPROVIDE ( _sungetc_r = 0x40057f6c );\nPROVIDE ( __swbuf = 0x40058cb4 );\nPROVIDE ( __swbuf_r = 0x40058bec );\nPROVIDE ( __swrite = 0x40001150 );\nPROVIDE ( __swsetup_r = 0x40058cc8 );\nPROVIDE ( sw_to_hw = 0x3ffb8d40 );\nPROVIDE ( syscall_table_ptr_app = 0x3ffae020 );\nPROVIDE ( syscall_table_ptr_pro = 0x3ffae024 );\nPROVIDE ( _system_r = 0x4000bc10 );\nPROVIDE ( tdefl_compress = 0x400600bc );\nPROVIDE ( tdefl_compress_buffer = 0x400607f4 );\nPROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 );\nPROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 );\nPROVIDE ( tdefl_get_adler32 = 0x400608d8 );\nPROVIDE ( tdefl_get_prev_return_status = 0x400608d0 );\nPROVIDE ( tdefl_init = 0x40060810 );\nPROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c );\nPROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 );\nPROVIDE ( time = 0x40001844 );\nPROVIDE ( __time_load_locale = 0x4000183c );\nPROVIDE ( times = 0x40001808 );\nPROVIDE ( _times_r = 0x4000bc40 );\nPROVIDE ( _timezone = 0x3ffae0a0 );\nPROVIDE ( tinfl_decompress = 0x4005ef30 );\nPROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 );\nPROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 );\nPROVIDE ( toascii = 0x4000c720 );\nPROVIDE ( tolower = 0x40001868 );\nPROVIDE ( toupper = 0x40001884 );\nPROVIDE ( __truncdfsf2 = 0x40002b90 );\nPROVIDE ( __tzcalc_limits = 0x400018a0 );\nPROVIDE ( __tz_lock = 0x40001a04 );\nPROVIDE ( _tzname = 0x3ffae030 );\nPROVIDE ( tzset = 0x40001a1c );\nPROVIDE ( _tzset_r = 0x40001a28 );\nPROVIDE ( __tz_unlock = 0x40001a10 );\nPROVIDE ( UartDev = 0x3ffe019c );\nPROVIDE ( __ucmpdi2 = 0x40063840 );\nPROVIDE ( __udivdi3 = 0x4000cff8 );\nPROVIDE ( __udivmoddi4 = 0x40064ab0 );\nPROVIDE ( __udivsi3 = 0x4000c7c8 );\nPROVIDE ( __udiv_w_sdiv = 0x40064aa8 );\nPROVIDE ( __umoddi3 = 0x4000d280 );\nPROVIDE ( __umodsi3 = 0x4000c7d0 );\nPROVIDE ( __umulsidi3 = 0x4000c7d8 );\nPROVIDE ( ungetc = 0x400590f4 );\nPROVIDE ( _ungetc_r = 0x40058fa0 );\nPROVIDE ( _unlink_r = 0x4000bc84 );\nPROVIDE ( __unorddf2 = 0x400637f4 );\nPROVIDE ( __unordsf2 = 0x40063478 );\nPROVIDE ( user_code_start = 0x3ffe0400 );\nPROVIDE ( utoa = 0x40056258 );\nPROVIDE ( __utoa = 0x400561f0 );\nPROVIDE ( veryBigHexP256 = 0x3ff9736c );\nPROVIDE ( wcrtomb = 0x40058920 );\nPROVIDE ( _wcrtomb_r = 0x400588d8 );\nPROVIDE ( __wctomb = 0x3ff96540 );\nPROVIDE ( _wctomb_r = 0x40058f14 );\nPROVIDE ( write = 0x4000181c );\nPROVIDE ( _write_r = 0x4000bd70 );\nPROVIDE ( xthal_bcopy = 0x4000c098 );\nPROVIDE ( xthal_copy123 = 0x4000c124 );\nPROVIDE ( xthal_get_ccompare = 0x4000c078 );\nPROVIDE ( xthal_get_ccount = 0x4000c050 );\nPROVIDE ( xthal_get_interrupt = 0x4000c1e4 );\nPROVIDE ( xthal_get_intread = 0x4000c1e4 );\nPROVIDE ( Xthal_intlevel = 0x3ff9c2b4 );\nPROVIDE ( xthal_memcpy = 0x4000c0bc );\nPROVIDE ( xthal_set_ccompare = 0x4000c058 );\nPROVIDE ( xthal_set_intclear = 0x4000c1ec );\nPROVIDE ( _xtos_set_intlevel = 0x4000bfdc );\nPROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );\nPROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );\nPROVIDE ( esp_rom_spiflash_config_param = 0x40063238 );\nPROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );\nPROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 );\nPROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 );\nPROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c );\nPROVIDE ( esp_rom_spiflash_select_qio_pins = 0x40061ddc );\nPROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );\n\n\/* \nThese functions are xtos-related (or call xtos-related functions) and do not play well \nwith multicore FreeRTOS. Where needed, we provide alternatives that are multicore\ncompatible. These functions also use a chunk of static RAM, by not using them we can\nallocate that RAM for general use.\n*\/\n\/*\nPROVIDE ( _DebugExceptionVector = 0x40000280 );\nPROVIDE ( _DoubleExceptionVector = 0x400003c0 );\nPROVIDE ( _KernelExceptionVector = 0x40000300 );\nPROVIDE ( _GeneralException = 0x40000e14 );\nPROVIDE ( _ResetHandler = 0x40000450 );\nPROVIDE ( _ResetVector = 0x40000400 );\nPROVIDE ( _UserExceptionVector = 0x40000340 );\nPROVIDE ( _NMIExceptionVector = 0x400002c0 );\nPROVIDE ( _WindowOverflow12 = 0x40000100 );\nPROVIDE ( _WindowOverflow4 = 0x40000000 );\nPROVIDE ( _WindowOverflow8 = 0x40000080 );\nPROVIDE ( _WindowUnderflow12 = 0x40000140 );\nPROVIDE ( _WindowUnderflow4 = 0x40000040 );\nPROVIDE ( _WindowUnderflow8 = 0x400000c0 );\nPROVIDE ( _Level2FromVector = 0x40000954 );\nPROVIDE ( _Level3FromVector = 0x40000a28 );\nPROVIDE ( _Level4FromVector = 0x40000af8 );\nPROVIDE ( _Level5FromVector = 0x40000c68 );\nPROVIDE ( _Level2Vector = 0x40000180 );\nPROVIDE ( _Level3Vector = 0x400001c0 );\nPROVIDE ( _Level4Vector = 0x40000200 );\nPROVIDE ( _Level5Vector = 0x40000240 );\nPROVIDE ( _LevelOneInterrupt = 0x40000835 );\nPROVIDE ( _SyscallException = 0x400007cf );\nPROVIDE ( _xtos_alloca_handler = 0x40000010 );\nPROVIDE ( _xtos_cause3_handler = 0x40000dd8 );\nPROVIDE ( _xtos_c_handler_table = 0x3ffe0548 );\nPROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 );\nPROVIDE ( _xtos_enabled = 0x3ffe0650 );\nPROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 );\nPROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 );\nPROVIDE ( _xtos_interrupt_table = 0x3ffe0658 );\nPROVIDE ( _xtos_ints_off = 0x4000bfac );\nPROVIDE ( _xtos_ints_on = 0x4000bf88 );\nPROVIDE ( _xtos_intstruct = 0x3ffe0650 );\nPROVIDE ( _xtos_l1int_handler = 0x40000814 );\nPROVIDE ( _xtos_p_none = 0x4000bfd4 );\nPROVIDE ( _xtos_restore_intlevel = 0x40000928 );\nPROVIDE ( _xtos_return_from_exc = 0x4000c034 );\nPROVIDE ( _xtos_set_exception_handler = 0x4000074c );\nPROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 );\nPROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 );\nPROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 );\nPROVIDE ( _xtos_set_vpri = 0x40000934 );\nPROVIDE ( _xtos_syscall_handler = 0x40000790 );\nPROVIDE ( _xtos_unhandled_exception = 0x4000c024 );\nPROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c );\nPROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 );\nPROVIDE ( ets_intr_count = 0x3ffe03fc );\n*\/\n\n\/* These functions are part of the UART downloader but also contain general UART functions. *\/\nPROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 );\nPROVIDE ( FilePacketSendReqMsgProc = 0x40008860 );\nPROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 );\nPROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c );\nPROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 );\nPROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 );\nPROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec );\nPROVIDE ( MemDwnLdStartMsgProc = 0x40008948 );\nPROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc );\nPROVIDE ( MemPacketSendReqMsgProc = 0x40008978 );\nPROVIDE ( uart_baudrate_detect = 0x40009034 );\nPROVIDE ( uart_buff_switch = 0x400093c0 );\nPROVIDE ( UartConnCheck = 0x40008738 );\nPROVIDE ( UartConnectProc = 0x40008a04 );\nPROVIDE ( UartDwnLdProc = 0x40008ce8 );\nPROVIDE ( UartRegReadProc = 0x40008a58 );\nPROVIDE ( UartRegWriteProc = 0x40008a14 );\nPROVIDE ( UartSetBaudProc = 0x40008aac );\nPROVIDE ( UartSpiAttachProc = 0x40008a6c );\nPROVIDE ( UartSpiReadProc = 0x40008a80 );\nPROVIDE ( VerifyFlashMd5Proc = 0x40008c44 );\nPROVIDE ( GetUartDevice = 0x40009598 );\nPROVIDE ( RcvMsg = 0x4000954c );\nPROVIDE ( SendMsg = 0x40009384 );\nPROVIDE ( UartGetCmdLn = 0x40009564 );\nPROVIDE ( UartRxString = 0x400092fc );\nPROVIDE ( Uart_Init = 0x40009120 );\nPROVIDE ( recv_packet = 0x40009424 );\nPROVIDE ( send_packet = 0x40009340 );\nPROVIDE ( uartAttach = 0x40008fd0 );\nPROVIDE ( uart_div_modify = 0x400090cc );\nPROVIDE ( uart_rx_intr_handler = 0x40008f4c );\nPROVIDE ( uart_rx_one_char = 0x400092d0 );\nPROVIDE ( uart_rx_one_char_block = 0x400092a4 );\nPROVIDE ( uart_rx_readbuff = 0x40009394 );\nPROVIDE ( uart_tx_flush = 0x40009258 );\nPROVIDE ( uart_tx_one_char = 0x40009200 );\nPROVIDE ( uart_tx_one_char2 = 0x4000922c );\nPROVIDE ( uart_tx_switch = 0x40009028 );\nPROVIDE ( uart_tx_wait_idle = 0x40009278 );\n\n\n\/*\nThese functions are part of the ROM GPIO driver. We do not use them; the provided esp-idf functions\nreplace them and this way we can re-use the fixed RAM addresses these routines need.\n*\/\n\/* <-- So you don't read over it: This comment disables the next lines.\nPROVIDE ( gpio_init = 0x40009c20 );\nPROVIDE ( gpio_intr_ack = 0x40009dd4 );\nPROVIDE ( gpio_intr_ack_high = 0x40009e1c );\nPROVIDE ( gpio_intr_handler_register = 0x40009e6c );\nPROVIDE ( gpio_intr_pending = 0x40009cec );\nPROVIDE ( gpio_intr_pending_high = 0x40009cf8 );\nPROVIDE ( gpio_pending_mask = 0x3ffe0038 );\nPROVIDE ( gpio_pending_mask_high = 0x3ffe0044 );\nPROVIDE ( gpio_pin_intr_state_set = 0x40009d04 );\nPROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 );\nPROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c );\nPROVIDE ( gpio_register_get = 0x40009cbc );\nPROVIDE ( gpio_register_set = 0x40009bbc );\n*\/\n\/* These are still part of that driver, but have been verified not to use static RAM, so they can be used. *\/\nPROVIDE ( gpio_output_set = 0x40009b24 );\nPROVIDE ( gpio_output_set_high = 0x40009b5c );\nPROVIDE ( gpio_input_get = 0x40009b88 );\nPROVIDE ( gpio_input_get_high = 0x40009b9c );\nPROVIDE ( gpio_matrix_in = 0x40009edc );\nPROVIDE ( gpio_matrix_out = 0x40009f0c );\nPROVIDE ( gpio_pad_select_gpio = 0x40009fdc );\nPROVIDE ( gpio_pad_set_drv = 0x4000a11c );\nPROVIDE ( gpio_pad_pulldown = 0x4000a348 );\nPROVIDE ( gpio_pad_pullup = 0x4000a22c );\nPROVIDE ( gpio_pad_hold = 0x4000a734 );\nPROVIDE ( gpio_pad_unhold = 0x4000a484 );\n\n\/*\nThese functions are part of the non-os kernel (etsc).\n*\/\nPROVIDE ( ets_aes_crypt = 0x4005c9b8 );\nPROVIDE ( ets_aes_disable = 0x4005c8f8 );\nPROVIDE ( ets_aes_enable = 0x4005c8cc );\nPROVIDE ( ets_aes_set_endian = 0x4005c928 );\nPROVIDE ( ets_aes_setkey_dec = 0x4005c994 );\nPROVIDE ( ets_aes_setkey_enc = 0x4005c97c );\nPROVIDE ( ets_bigint_disable = 0x4005c4e0 );\nPROVIDE ( ets_bigint_enable = 0x4005c498 );\nPROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 );\nPROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 );\nPROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 );\nPROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c );\nPROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 );\nPROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc );\nPROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 );\nPROVIDE ( ets_bigint_mult_prepare = 0x4005c630 );\nPROVIDE ( ets_bigint_wait_finish = 0x4005c520 );\nPROVIDE ( ets_post = 0x4000673c );\nPROVIDE ( ets_run = 0x400066bc );\nPROVIDE ( ets_set_idle_cb = 0x40006674 );\nPROVIDE ( ets_task = 0x40006688 );\nPROVIDE ( ets_efuse_get_8M_clock = 0x40008710 );\nPROVIDE ( ets_efuse_get_spiconfig = 0x40008658 );\nPROVIDE ( ets_efuse_program_op = 0x40008628 );\nPROVIDE ( ets_efuse_read_op = 0x40008600 );\nPROVIDE ( ets_intr_lock = 0x400067b0 );\nPROVIDE ( ets_intr_unlock = 0x400067c4 );\nPROVIDE ( ets_isr_attach = 0x400067ec );\nPROVIDE ( ets_isr_mask = 0x400067fc );\nPROVIDE ( ets_isr_unmask = 0x40006808 );\nPROVIDE ( ets_waiti0 = 0x400067d8 );\nPROVIDE ( intr_matrix_set = 0x4000681c );\nPROVIDE ( check_pos = 0x400068b8 );\nPROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c );\nPROVIDE ( ets_set_startup_callback = 0x4000688c );\nPROVIDE ( ets_set_user_start = 0x4000687c );\nPROVIDE ( ets_unpack_flash_code = 0x40007018 );\nPROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c );\nPROVIDE ( rom_main = 0x400076c4 );\nPROVIDE ( ets_write_char_uart = 0x40007cf8 );\nPROVIDE ( ets_install_putc1 = 0x40007d18 );\nPROVIDE ( ets_install_putc2 = 0x40007d38 );\nPROVIDE ( ets_install_uart_printf = 0x40007d28 );\nPROVIDE ( ets_printf = 0x40007d54 );\nPROVIDE ( rtc_boot_control = 0x4000821c );\nPROVIDE ( rtc_get_reset_reason = 0x400081d4 );\nPROVIDE ( rtc_get_wakeup_cause = 0x400081f4 );\nPROVIDE ( rtc_select_apb_bridge = 0x40008288 );\nPROVIDE ( set_rtc_memory_crc = 0x40008208 );\nPROVIDE ( software_reset = 0x4000824c );\nPROVIDE ( software_reset_cpu = 0x40008264 );\nPROVIDE ( ets_secure_boot_check = 0x4005cb40 );\nPROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 );\nPROVIDE ( ets_secure_boot_check_start = 0x4005cbcc );\nPROVIDE ( ets_secure_boot_finish = 0x4005ca84 );\nPROVIDE ( ets_secure_boot_hash = 0x4005cad4 );\nPROVIDE ( ets_secure_boot_obtain = 0x4005cb14 );\nPROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 );\nPROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 );\nPROVIDE ( ets_secure_boot_start = 0x4005ca34 );\nPROVIDE ( ets_sha_disable = 0x4005c0a8 );\nPROVIDE ( ets_sha_enable = 0x4005c07c );\nPROVIDE ( ets_sha_finish = 0x4005c104 );\nPROVIDE ( ets_sha_init = 0x4005c0d4 );\nPROVIDE ( ets_sha_update = 0x4005c2a0 );\nPROVIDE ( ets_delay_us = 0x40008534 );\nPROVIDE ( ets_get_cpu_frequency = 0x4000855c );\nPROVIDE ( ets_get_detected_xtal_freq = 0x40008588 );\nPROVIDE ( ets_get_xtal_scale = 0x4000856c );\nPROVIDE ( ets_timer_arm = 0x40008368 );\nPROVIDE ( ets_timer_arm_us = 0x400083ac );\nPROVIDE ( ets_timer_disarm = 0x400083ec );\nPROVIDE ( ets_timer_done = 0x40008428 );\nPROVIDE ( ets_timer_handler_isr = 0x40008454 );\nPROVIDE ( ets_timer_init = 0x400084e8 );\nPROVIDE ( ets_timer_setfn = 0x40008350 );\nPROVIDE ( ets_update_cpu_frequency_rom = 0x40008550 );  \/* Updates g_ticks_per_us on the current CPU only; not on the other core *\/\n\n\/* Following are static data, but can be used, not generated by script <<<<< btdm data *\/\nPROVIDE ( hci_tl_env = 0x3ffb8154 );\nPROVIDE ( ld_acl_env = 0x3ffb8258 );\nPROVIDE ( ld_active_ch_map = 0x3ffb8334 );\nPROVIDE ( ld_bcst_acl_env = 0x3ffb8274 );\nPROVIDE ( ld_csb_rx_env = 0x3ffb8278 );\nPROVIDE ( ld_csb_tx_env = 0x3ffb827c );\nPROVIDE ( ld_env = 0x3ffb9510 );\nPROVIDE ( ld_fm_env = 0x3ffb8284 );\nPROVIDE ( ld_inq_env = 0x3ffb82e4 );\nPROVIDE ( ld_iscan_env = 0x3ffb82e8 );\nPROVIDE ( ld_page_env = 0x3ffb82f0 );\nPROVIDE ( ld_pca_env = 0x3ffb82f4 );\nPROVIDE ( ld_pscan_env = 0x3ffb8308 );\nPROVIDE ( ld_sched_env = 0x3ffb830c );\nPROVIDE ( ld_sched_params = 0x3ffb96c0 );\nPROVIDE ( ld_sco_env = 0x3ffb824c );\nPROVIDE ( ld_sscan_env = 0x3ffb832c );\nPROVIDE ( ld_strain_env = 0x3ffb8330 );\nPROVIDE ( LM_Sniff = 0x3ffb8230 );\nPROVIDE ( LM_SniffSubRate = 0x3ffb8214 );\nPROVIDE ( prbs_64bytes = 0x3ff98992 );\nPROVIDE ( nvds_env = 0x3ffb8364 );\nPROVIDE ( nvds_magic_number = 0x3ff9912a );\n\/* Above are static data, but can be used, not generated by script >>>>> btdm data *\/\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"45470e452c923edf30bd77c3df5bbdd8434af459","subject":"minor change to allow larger ROM (up to 12 MB)","message":"minor change to allow larger ROM (up to 12 MB)\n","repos":"Stephane-D\/SGDK,Stephane-D\/SGDK,andwn\/SGDK,andwn\/SGDK,Stephane-D\/SGDK,andwn\/SGDK","old_file":"md.ld","new_file":"md.ld","new_contents":"OUTPUT_ARCH(m68k)\r\nSEARCH_DIR(.)\r\n\/*GROUP(-lbcc -lc -lgcc)*\/\r\n__DYNAMIC  =  0;\r\n\r\n\/*\r\n * Setup the memory map of the SEGA Genesis.\r\n * stack grows down from high memory.\r\n *\r\n * The memory map look like this:\r\n * +--------------------+ <- low memory\r\n * | .text              |\r\n * |        _etext      |\r\n * |        ctor list   | the ctor and dtor lists are for\r\n * |        dtor list   | C++ support\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * +--------------------+ <- 0x00FF0000\r\n * | .data              | initialized data goes here\r\n * |        _data       |\r\n * |        _edata      |\r\n * +--------------------+\r\n * | .bss               |\r\n * |        _bstart     | start of bss, cleared by crt0\r\n * |        _bend       | start of heap, used by sbrk()\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * |        __stack     | top of stack\r\n * +--------------------+ <- 0x01000000\r\n *\/\r\nMEMORY\r\n{\r\n\trom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00C00000\r\n\tram : ORIGIN = 0x00FF0000, LENGTH = 0x00010000\r\n}\r\n\r\n\/*\r\n * allocate the stack to be at the top of memory, since the stack\r\n * grows down\r\n *\/\r\n\r\nPROVIDE (__stack = 0x01000000);\r\n\r\n\r\nSECTIONS\r\n{\r\n  .text 0x00000000:\r\n  {\r\n    KEEP(*(.text.keepboot)) *(.text.*) *(.text)\r\n    . = ALIGN(0x4);\r\n     __CTOR_LIST__ = .;\r\n    LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\r\n    *(.ctors)\r\n    LONG(0)\r\n    __CTOR_END__ = .;\r\n    __DTOR_LIST__ = .;\r\n    LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\r\n    *(.dtors)\r\n     LONG(0)\r\n    __DTOR_END__ = .;\r\n\r\n    *(.rodata .rodata.*)\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n\r\n    . = ALIGN(0x4);\r\n    __INIT_SECTION__ = . ;\r\n    *(.init)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    __FINI_SECTION__ = . ;\r\n    *(.fini)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    _etext = .;\r\n    *(.lit)\r\n\r\n    *(.rodata_bin)\r\n    *(.rodata_binf)\r\n  } > rom\r\n  _stext = SIZEOF (.text);\r\n\r\n  .data 0xFF0000 :\r\n  AT ( ADDR (.text) + SIZEOF (.text) )\r\n  {\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.*)\r\n    _edata = .;\r\n  } > ram\r\n  _sdata = SIZEOF (.data);\r\n\r\n  .bss 0xFF0000 + SIZEOF (.data) :\r\n  {\r\n    _start = . ;\r\n    *(.shbss)\r\n    *(.bss .bss.*)\r\n    *(COMMON)\r\n    _bend = . ;\r\n  } > ram\r\n\r\n  .stab 0 (NOLOAD) :\r\n  {\r\n    *(.stab)\r\n  }\r\n\r\n  .stabstr 0 (NOLOAD) :\r\n  {\r\n    *(.stabstr)\r\n  }\r\n\r\n  .eh_frame 0 (NOLOAD) :\r\n  {\r\n    *(.eh_frame)\r\n  }\r\n}\r\n","old_contents":"OUTPUT_ARCH(m68k)\r\nSEARCH_DIR(.)\r\n\/*GROUP(-lbcc -lc -lgcc)*\/\r\n__DYNAMIC  =  0;\r\n\r\n\/*\r\n * Setup the memory map of the SEGA Genesis.\r\n * stack grows down from high memory.\r\n *\r\n * The memory map look like this:\r\n * +--------------------+ <- low memory\r\n * | .text              |\r\n * |        _etext      |\r\n * |        ctor list   | the ctor and dtor lists are for\r\n * |        dtor list   | C++ support\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * +--------------------+ <- 0x00FF0000\r\n * | .data              | initialized data goes here\r\n * |        _data       |\r\n * |        _edata      |\r\n * +--------------------+\r\n * | .bss               |\r\n * |        _bstart     | start of bss, cleared by crt0\r\n * |        _bend       | start of heap, used by sbrk()\r\n * +--------------------+\r\n * .                    .\r\n * .                    .\r\n * .                    .\r\n * |        __stack     | top of stack\r\n * +--------------------+ <- 0x01000000\r\n *\/\r\nMEMORY\r\n{\r\n\trom : ORIGIN = 0x00000000, LENGTH = 0x00A00000\r\n\tram : ORIGIN = 0x00FF0000, LENGTH = 0x00010000\r\n}\r\n\r\n\/*\r\n * allocate the stack to be at the top of memory, since the stack\r\n * grows down\r\n *\/\r\n\r\nPROVIDE (__stack = 0x01000000);\r\n\r\n\r\nSECTIONS\r\n{\r\n  .text 0x00000000:\r\n  {\r\n    KEEP(*(.text.keepboot)) *(.text.*) *(.text)\r\n    . = ALIGN(0x4);\r\n     __CTOR_LIST__ = .;\r\n    LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\r\n    *(.ctors)\r\n    LONG(0)\r\n    __CTOR_END__ = .;\r\n    __DTOR_LIST__ = .;\r\n    LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\r\n    *(.dtors)\r\n     LONG(0)\r\n    __DTOR_END__ = .;\r\n\r\n    *(.rodata .rodata.*)\r\n    *(.gcc_except_table .gcc_except_table.*)\r\n\r\n    . = ALIGN(0x4);\r\n    __INIT_SECTION__ = . ;\r\n    *(.init)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    __FINI_SECTION__ = . ;\r\n    *(.fini)\r\n    SHORT (0x4E75)\t\/* rts *\/\r\n\r\n    _etext = .;\r\n    *(.lit)\r\n\r\n    *(.rodata_bin)\r\n    *(.rodata_binf)\r\n  } > rom\r\n  _stext = SIZEOF (.text);\r\n\r\n  .data 0xFF0000 :\r\n  AT ( ADDR (.text) + SIZEOF (.text) )\r\n  {\r\n    *(.got.plt) *(.got)\r\n    *(.shdata)\r\n    *(.data .data.*)\r\n    _edata = .;\r\n  } > ram\r\n  _sdata = SIZEOF (.data);\r\n\r\n  .bss 0xFF0000 + SIZEOF (.data) :\r\n  {\r\n    _start = . ;\r\n    *(.shbss)\r\n    *(.bss .bss.*)\r\n    *(COMMON)\r\n    _bend = . ;\r\n  } > ram\r\n\r\n  .stab 0 (NOLOAD) :\r\n  {\r\n    *(.stab)\r\n  }\r\n\r\n  .stabstr 0 (NOLOAD) :\r\n  {\r\n    *(.stabstr)\r\n  }\r\n\r\n  .eh_frame 0 (NOLOAD) :\r\n  {\r\n    *(.eh_frame)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"81ed9f9152d46d15a69adaaa0bdc005832146d8c","subject":"build: linker script: Link with crt0.o and -lc by default","message":"build: linker script: Link with crt0.o and -lc by default\n","repos":"SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl,SimonKagstrom\/cibyl","old_file":"build\/linker.lds","new_file":"build\/linker.lds","new_contents":"OUTPUT_ARCH(mips)\nSTARTUP(crt0.o)\nGROUP(-lcrt0 -lc -ljava)\nENTRY(__start)\n\nSECTIONS\n{\n       \t. = 0x1000000;\n       \t.text : ALIGN(4) { *(.init) *(.text) *(.text.*) *(.gnu.linkonce.t.*) }\n       \t. = 0x0;\n       \t.data : ALIGN(16) { *(.data0) *(.data) *(.rodata.str1.4)  *(.rodata.cst4) *(.rodata.cst8) *(.reginfo) }\n       \t.rodata : ALIGN(16) { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) *(.cibylsetjmp) }\n\n\t.ctors : ALIGN(4) {\n\t       PROVIDE(__ctors_begin = .);\n\t       *(.ctors)\n\t       PROVIDE(__ctors_end = .);\n\t}\n\t.dtors : ALIGN(4) {\n\t       PROVIDE(__dtors_begin = .);\n\t       *(.dtors)\n\t       PROVIDE(__dtors_end = .);\n\t}\n       \t.bss : ALIGN(16) {\n\t     *(.bss) *(.scommon) *(.sbss)\n\t     PROVIDE(__edata = .);\n\t}\n\n        \/* Exported symbols (to Java) *\/\n       \t.cibylexpsyms : { *(.cibylexpsyms) }\n\n\t\/* The string table with the exception names *\/\n\t. = 0xfd000000;\n       \t.cibylexceptionstrs : { *(.cibylexceptionstrs) }\n\n\t\/* The string table with the system call names *\/\n\t. = 0xff000000;\n       \t.cibylstrtab : { *(.cibylstrtab) }\n}\n","old_contents":"OUTPUT_ARCH(mips)\nENTRY(__start)\n\nSECTIONS\n{\n       \t. = 0x1000000;\n       \t.text : ALIGN(4) { *(.init) *(.text) *(.text.*) *(.gnu.linkonce.t.*) }\n       \t. = 0x0;\n       \t.data : ALIGN(16) { *(.data0) *(.data) *(.rodata.str1.4)  *(.rodata.cst4) *(.rodata.cst8) *(.reginfo) }\n       \t.rodata : ALIGN(16) { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) *(.cibylsetjmp) }\n\n\t.ctors : ALIGN(4) {\n\t       PROVIDE(__ctors_begin = .);\n\t       *(.ctors)\n\t       PROVIDE(__ctors_end = .);\n\t}\n\t.dtors : ALIGN(4) {\n\t       PROVIDE(__dtors_begin = .);\n\t       *(.dtors)\n\t       PROVIDE(__dtors_end = .);\n\t}\n       \t.bss : ALIGN(16) {\n\t     *(.bss) *(.scommon) *(.sbss)\n\t     PROVIDE(__edata = .);\n\t}\n\n        \/* Exported symbols (to Java) *\/\n       \t.cibylexpsyms : { *(.cibylexpsyms) }\n\n\t\/* The string table with the exception names *\/\n\t. = 0xfd000000;\n       \t.cibylexceptionstrs : { *(.cibylexceptionstrs) }\n\n\t\/* The string table with the system call names *\/\n\t. = 0xff000000;\n       \t.cibylstrtab : { *(.cibylstrtab) }\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"7adc06d38fe33296ff926c81c7632702049e19d1","subject":"hw\/mcu\/dialog: Provide generic names for CMAC sections","message":"hw\/mcu\/dialog: Provide generic names for CMAC sections\n\nWe do not want to rely on section names used in Dialog's libraries.\nInstead, we provide generic \"placeholders\" for firmware image and CMAC\nRAM and it's up to CMAC driver to load proper symbols into these\nsections.\n","repos":"mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core","old_file":"hw\/mcu\/dialog\/da1469x\/da1469x.ld","new_file":"hw\/mcu\/dialog\/da1469x\/da1469x.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"unknown","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e202ae972aba24372ab8fff769f39830c94d9845","subject":"Fixed a misplaced \"end\" symbol in the linker script.","message":"Fixed a misplaced \"end\" symbol in the linker script.\n","repos":"lightsfury\/GCC-ARM,lightsfury\/GCC-ARM","old_file":"config\/common\/sections.ld","new_file":"config\/common\/sections.ld","new_contents":"\/*\nCopyright (c) 2013 Robert Beam\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n*\/\n\nENTRY(Reset_Handler);\n\n_ramStart   = ORIGIN(RAM);\n_ramEnd     = _ramStart + LENGTH(RAM);\n_stackStart = _ramEnd;\n\nSECTIONS\n{\n\t.isr_vector   :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t} > FLASH\n\t\n\t.text         :\n\t{\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.vfp11_veneer)\n\t\t*(.v4_bx)\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\t\n\t.ARM.extab    :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\t\n\t.ARM.exidx    :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t\n\t. = ALIGN(4);\n\t_staticDataSource = .;\n\t\n\t\/* Static non-zero init data *\/\n\t.data         : AT(_staticDataSource)\n\t{\n\t\t*(.data)\n\t\t*(.data.*)\n\t} > RAM\n\t\n\t_staticDataStart  = ADDR(.data);\n\t_staticDataLength = SIZEOF(.data);\n\t\n\t\/* Static zero init data *\/\n\t.bss BLOCK(4) :\n\t{\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t\t*(COMMON)\n\t} > RAM\n\t\n\t_staticZeroStart = ADDR(.bss);\n\t_staticZeroLength = SIZEOF(.bss);\n\tPROVIDE(end = _staticZeroStart + _staticZeroLength);\n\t\n\t.gdb_index    :\n\t{\n\t\t*(.gdb_index)\n\t}\n\t\n\t\/** @section Debugging section-inception **\/\n\t.debug\t\t\t\t0\t: { *(.debug) }\n\t.line\t\t\t\t0\t: { *(.line) }\n\t.debug_srcinfo\t\t0\t: { *(.debug_srcinfo) }\n\t.debug_sfnames\t\t0\t: { *(.debug_sfnames) }\n\t.debug_aranges\t\t0\t: { *(.debug_aranges) }\n\t.debug_pubnames\t\t0\t: { *(.debug_pubnames) }\n\t.debug_info\t\t\t0\t: { *(.debug_info) }\n\t.debug_abbrev\t\t0\t: { *(.debug_abbrev) }\n\t.debug_line\t\t\t0\t: { *(.debug_line) }\n\t.debug_frame\t\t0\t: { *(.debug_frame) }\n\t.debug_str\t\t\t0\t: { *(.debug_str) }\n\t.debug_loc\t\t\t0\t: { *(.debug_loc) }\n\t.debug_macinfo\t\t0\t: { *(.debug_macinfo) }\n\t.debug_weaknames\t0\t: { *(.debug_weaknames) }\n\t.debug_funcnames\t0\t: { *(.debug_funcnames) }\n\t.debug_typenames\t0\t: { *(.debug_typenames) }\n\t.debug_varnames\t\t0\t: { *(.debug_varnames) }\n}\n","old_contents":"\/*\nCopyright (c) 2013 Robert Beam\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and\/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n*\/\n\nENTRY(Reset_Handler);\n\n_ramStart   = ORIGIN(RAM);\n_ramEnd     = _ramStart + LENGTH(RAM);\n_stackStart = _ramEnd;\nPROVIDE(end = _ramStart);\n\nSECTIONS\n{\n\t.isr_vector   :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t} > FLASH\n\t\n\t.text         :\n\t{\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.vfp11_veneer)\n\t\t*(.v4_bx)\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\t\n\t.ARM.extab    :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\t\n\t.ARM.exidx    :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t\n\t. = ALIGN(4);\n\t_staticDataSource = .;\n\t\n\t\/* Static non-zero init data *\/\n\t.data         : AT(_staticDataSource)\n\t{\n\t\t*(.data)\n\t\t*(.data.*)\n\t} > RAM\n\t\n\t_staticDataStart  = ADDR(.data);\n\t_staticDataLength = SIZEOF(.data);\n\t\n\t\/* Static zero init data *\/\n\t.bss BLOCK(4) :\n\t{\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t\t*(COMMON)\n\t} > RAM\n\t\n\t_staticZeroStart = ADDR(.bss);\n\t_staticZeroLength = SIZEOF(.bss);\n\t\n\t.gdb_index    :\n\t{\n\t\t*(.gdb_index)\n\t}\n\t\n\t\/** @section Debugging section-inception **\/\n\t.debug\t\t\t\t0\t: { *(.debug) }\n\t.line\t\t\t\t0\t: { *(.line) }\n\t.debug_srcinfo\t\t0\t: { *(.debug_srcinfo) }\n\t.debug_sfnames\t\t0\t: { *(.debug_sfnames) }\n\t.debug_aranges\t\t0\t: { *(.debug_aranges) }\n\t.debug_pubnames\t\t0\t: { *(.debug_pubnames) }\n\t.debug_info\t\t\t0\t: { *(.debug_info) }\n\t.debug_abbrev\t\t0\t: { *(.debug_abbrev) }\n\t.debug_line\t\t\t0\t: { *(.debug_line) }\n\t.debug_frame\t\t0\t: { *(.debug_frame) }\n\t.debug_str\t\t\t0\t: { *(.debug_str) }\n\t.debug_loc\t\t\t0\t: { *(.debug_loc) }\n\t.debug_macinfo\t\t0\t: { *(.debug_macinfo) }\n\t.debug_weaknames\t0\t: { *(.debug_weaknames) }\n\t.debug_funcnames\t0\t: { *(.debug_funcnames) }\n\t.debug_typenames\t0\t: { *(.debug_typenames) }\n\t.debug_varnames\t\t0\t: { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"3ad6af06386c39a22c293e1e5049439e029be265","subject":"linker.ld: add ELF header and keep alignment","message":"linker.ld: add ELF header and keep alignment\n","repos":"AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,AndreasAakesson\/IncludeOS,hioa-cs\/IncludeOS,AnnikaH\/IncludeOS,hioa-cs\/IncludeOS,AndreasAakesson\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,alfred-bratterud\/IncludeOS,AndreasAakesson\/IncludeOS,mnordsletten\/IncludeOS,alfred-bratterud\/IncludeOS,hioa-cs\/IncludeOS,mnordsletten\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,AnnikaH\/IncludeOS,alfred-bratterud\/IncludeOS,mnordsletten\/IncludeOS,AndreasAakesson\/IncludeOS,mnordsletten\/IncludeOS,hioa-cs\/IncludeOS,AnnikaH\/IncludeOS,AndreasAakesson\/IncludeOS,mnordsletten\/IncludeOS,alfred-bratterud\/IncludeOS","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\n\nENTRY(_start)\n\nSECTIONS\n{\n\n  PROVIDE (__executable_start = SEGMENT_START(\"text-segment\", 0xa00000));\n  . = SEGMENT_START(\"text-segment\", 0xa00000) + SIZEOF_HEADERS;\n\n  \/* For convenience w. multiboot *\/\n  PROVIDE ( _ELF_START_ = __executable_start);\n  PROVIDE ( _LOAD_START_ = _ELF_START_ );\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = . );\n      *(.multiboot)\n   }\n\n  .text ALIGN(0x1000):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n\n  PROVIDE( _TEXT_END_ = . );\n  .init ALIGN(0x10) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    _FINI_START_ = .;\n    *(.fini)\n    _FINI_END_ = .;\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  .rodata ALIGN(0x1000):\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  .config ALIGN(0x8) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .eh_frame :\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    PROVIDE (__eh_frame_end = .);\n  }\n\n  .eh_frame_hdr :\n  {\n    KEEP(*(.eh_frame_hdr))\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","old_contents":"\/**\n * This file is a part of the IncludeOS unikernel - www.includeos.org\n *\n * Copyright 2015 Oslo and Akershus University College of Applied Sciences\n * and Alfred Bratterud\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http: *www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n**\/\nENTRY(_start)\n\nSECTIONS\n{\n  PROVIDE ( _ELF_START_ = . + 0xA00000);\n  PROVIDE ( _LOAD_START_ = _ELF_START_); \/* For convenience w. multiboot *\/\n\n  . = _ELF_START_;\n\n  .multiboot : {\n      PROVIDE(_MULTIBOOT_START_ = .);\n      *(.multiboot)\n   }\n\n\n  .text ALIGN(0x10):\n  {\n  PROVIDE( _TEXT_START_ = . );\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _stext = .;\n    *(.text)\n    *(.text.*)\n    *(.gnu.linkonce.t*)\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _etext = .;\n  }\n  PROVIDE( _TEXT_END_ = . );\n\n  .init ALIGN(0x10) : {\n    _INIT_START_ = .;\n    *(.init)\n    _INIT_END_ = .;\n  }\n\n  .fini ALIGN(0x10) : {\n    _FINI_START_ = .;\n    *(.fini)\n    _FINI_END_ = .;\n  }\n\n  \/* Global offset-table. For dynamic linking *\/\n  .got ALIGN(0x10) : {\n      *(.got*)\n  }\n\n\/**\n *  .ctors, .dtors, .preinit_array, .init_array, .fini_array\n *  from GNU LD default linker script\n *\/\n\n.ctors          :\n  {\n    _GCONSTR_START_ = .;\n      \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n       KEEP (*crtbegin.o(.ctors))\n       KEEP (*crtbegin?.o(.ctors))\n       \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n       KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n       KEEP (*(SORT(.ctors.*)))\n       KEEP (*(.ctors))\n    _GCONSTR_END_ = .;\n  }\n\n  .dtors :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n\n  .fini_array :\n  {\n   PROVIDE_HIDDEN (__fini_array_start = .);\n   KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n   KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n   PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n\n  .config ALIGN(0x8) : {\n    _CONFIG_JSON_START_ = .;\n    KEEP(*(.config))\n    _CONFIG_JSON_END_ = .;\n    BYTE(0);\n  }\n\n  .rodata :\n  {\n    _RODATA_START_ = .;\n    *(.rodata*)\n    *(.gnu.linkonce.r*)\n    _RODATA_END_ = .;\n    \/* For solo5, although it's just used to print the mem layout. *\/\n    _erodata = .;\n  }\n\n  \/* For stack unwinding (exception handling)  *\/\n  .eh_frame_hdr ALIGN(0x8):\n  {\n    KEEP(*(.eh_frame_hdr*))\n  }\n  .eh_frame ALIGN(0x8):\n  {\n    PROVIDE (__eh_frame_start = .);\n    KEEP(*(.eh_frame))\n    LONG (0);\n  }\n\n  .gcc_except_table :\n  {\n    *(.gcc_except_table)\n  }\n\n  .data :\n  {\n    _DATA_START_ = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d*)\n    _DATA_END_ = .;\n  }\n\n  .tdata ALIGN(0x10) :\n  {\n    _TDATA_START_ = .;\n    *(.tdata .tdata.*)\n    _TDATA_END_ = .;\n    . = ALIGN(0x10);\n  }\n  .tbss :\n  {\n    _TBSS_START_ = .;\n    *(.tbss .tbss.*)\n    _TBSS_END_ = .;\n    . = ALIGN(0x10);\n  }\n\n  .memdisk :\n  {\n    _DISK_START_ = .;\n    *(.diskdata)\n    _DISK_END_ = .;\n  }\n\n  .elf_symbols : {\n    _ELF_SYM_START_ = .;\n    LONG (0);\n  }\n\n  \/** Optional memory hole between memdisk and bss **\/\n  . += PRE_BSS_AREA;\n\n  .bss ALIGN(0x1000) :\n  {\n    _BSS_START_ = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    _BSS_END_ = .;\n  }\n  . = ALIGN(0x8);\n\n  _end = .;\n\n  PROVIDE (end = .);\n  PROVIDE (_ELF_END_ = .);\n  PROVIDE (_LOAD_END_ = .);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"69151c09ee7e6c35122234aa32beb48b3ff995c8","subject":"Pin the reflection data sections on Linux","message":"Pin the reflection data sections on Linux\n\nThese had similar problems to the protocol conformance sections during\nLinux bringup. There are relative offsets from the main reflection\nsection to the two string sections, so their position relative to each\nother must remain fixed.\n","repos":"khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift","old_file":"stdlib\/public\/runtime\/swift.ld","new_file":"stdlib\/public\/runtime\/swift.ld","new_contents":"SECTIONS\n{\n  .swift3_typeref : { *(.swift3_typeref) },\n  .swift3_reflstr : { *(.swift3_reflstr) },\n  .swift3_reflect : { *(.swift3_reflect) },\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","old_contents":"SECTIONS\n{\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3c6a0b5009bc810ad81d39c9a5891f7201ead55d","subject":"Multiboot fix","message":"Multiboot fix\n","repos":"Hullu2000\/BFTK,Hullu2000\/BFTK","old_file":"C\/link.ld","new_file":"C\/link.ld","new_contents":"ENTRY(_start)\n\nSECTIONS\n{\n\t. = 1M;\n\n\t.text\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bootstrap_stack)\n\t\t*(.bss)\n\t}\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS\n{\n\t. = 1M;\n\n\t.text BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(.data)\n\t}\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss BLOCK(4K) : ALIGN(4K)\n\t{\n\t\t*(COMMON)\n\t\t*(.bootstrap_stack)\n\t\t*(.bss)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"1d6ce0529efe40e6b1add1e45b62c2aedd51ffb9","subject":"Remove stray cc3200.lds file","message":"Remove stray cc3200.lds file\n","repos":"qtonthat\/Energia,bobintornado\/Energia,vigneshmanix\/Energia,NoPinky\/Energia,brianonn\/Energia,battosai30\/Energia,brianonn\/Energia,brianonn\/Energia,radiolok\/Energia,cevatbostancioglu\/Energia,DavidUser\/Energia,vigneshmanix\/Energia,martianmartin\/Energia,DavidUser\/Energia,brianonn\/Energia,vigneshmanix\/Energia,radiolok\/Energia,NoPinky\/Energia,radiolok\/Energia,qtonthat\/Energia,sanyaade-iot\/Energia,battosai30\/Energia,martianmartin\/Energia,DavidUser\/Energia,danielohh\/Energia,cevatbostancioglu\/Energia,danielohh\/Energia,cevatbostancioglu\/Energia,battosai30\/Energia,bobintornado\/Energia,bobintornado\/Energia,radiolok\/Energia,sanyaade-iot\/Energia,qtonthat\/Energia,qtonthat\/Energia,radiolok\/Energia,sanyaade-iot\/Energia,vigneshmanix\/Energia,martianmartin\/Energia,danielohh\/Energia,vigneshmanix\/Energia,sanyaade-iot\/Energia,qtonthat\/Energia,brianonn\/Energia,dvdvideo1234\/Energia,brianonn\/Energia,sanyaade-iot\/Energia,martianmartin\/Energia,sanyaade-iot\/Energia,bobintornado\/Energia,DavidUser\/Energia,dvdvideo1234\/Energia,cevatbostancioglu\/Energia,martianmartin\/Energia,croberts15\/Energia,bobintornado\/Energia,radiolok\/Energia,brianonn\/Energia,qtonthat\/Energia,croberts15\/Energia,martianmartin\/Energia,danielohh\/Energia,dvdvideo1234\/Energia,battosai30\/Energia,DavidUser\/Energia,croberts15\/Energia,NoPinky\/Energia,bobintornado\/Energia,danielohh\/Energia,bobintornado\/Energia,croberts15\/Energia,qtonthat\/Energia,croberts15\/Energia,battosai30\/Energia,NoPinky\/Energia,sanyaade-iot\/Energia,dvdvideo1234\/Energia,croberts15\/Energia,martianmartin\/Energia,danielohh\/Energia,danielohh\/Energia,radiolok\/Energia,NoPinky\/Energia,dvdvideo1234\/Energia,NoPinky\/Energia,battosai30\/Energia,cevatbostancioglu\/Energia,vigneshmanix\/Energia,vigneshmanix\/Energia,DavidUser\/Energia,NoPinky\/Energia,DavidUser\/Energia,cevatbostancioglu\/Energia,cevatbostancioglu\/Energia,dvdvideo1234\/Energia,battosai30\/Energia,dvdvideo1234\/Energia,croberts15\/Energia","old_file":"hardware\/common\/cc3200.lds","new_file":"hardware\/common\/cc3200.lds","new_contents":"","old_contents":"\/******************************************************************************\n *\n * Default Linker script for the Texas Instruments CC3200\n *\n *****************************************************************************\/\n\nMEMORY\n{\n    SRAM (RWX)  : ORIGIN = 0x20004000, LENGTH = 0x00030000 - 0x4000\n}\n\nREGION_ALIAS(\"REGION_TEXT\", SRAM);\nREGION_ALIAS(\"REGION_BSS\", SRAM);\nREGION_ALIAS(\"REGION_DATA\", SRAM);\nREGION_ALIAS(\"REGION_STACK\", SRAM);\nREGION_ALIAS(\"REGION_HEAP\", SRAM);\nREGION_ALIAS(\"REGION_ARM_EXIDX\", SRAM);\nREGION_ALIAS(\"REGION_ARM_EXTAB\", SRAM);\n\nSECTIONS {\n\n    PROVIDE (_intvecs_base_address = 0x20004000);\n\n    .intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {\n        KEEP (*(.intvecs))\n    } > REGION_TEXT\n\n    PROVIDE (_vtable_base_address = 0x20004000);\n\n    .vtable (_vtable_base_address) : AT (_vtable_base_address) {\n        KEEP (*(.vtable))\n    } > REGION_DATA\n\n    .text : {\n        CREATE_OBJECT_SYMBOLS\n        *(.text)\n        *(.text.*)\n        . = ALIGN(0x4);\n        KEEP (*(.ctors))\n        . = ALIGN(0x4);\n        KEEP (*(.dtors))\n        . = ALIGN(0x4);\n        __init_array_start = .;\n        KEEP (*(.init_array*))\n        __init_array_end = .;\n        *(.init)\n        *(.fini*)\n    } > REGION_TEXT\n\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata*)\n    } > REGION_TEXT\n\n    .data : ALIGN (4) {\n        __data_load__ = LOADADDR (.data);\n        __data_start__ = .;\n        *(.data)\n        *(.data*)\n        . = ALIGN (4);\n        __data_end__ = .;\n    } > REGION_DATA AT> REGION_TEXT\n\n    .ARM.exidx : {\n        __exidx_start = .;\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n        __exidx_end = .;\n    } > REGION_ARM_EXIDX\n\n    .ARM.extab : {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > REGION_ARM_EXTAB\n\n    .bss : {\n        __bss_start__ = .;\n        *(.shbss)\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        . = ALIGN (4);\n        __bss_end__ = .;\n    } > REGION_BSS\n\n    .heap : {\n        __heap_start__ = .;\n        end = __heap_start__;\n        _end = end;\n        __end = end;\n        KEEP(*(.heap))\n        __heap_end__ = .;\n        __HeapLimit = __heap_end__;\n    } > REGION_HEAP\n\n    .stack : ALIGN(0x8) {\n        _stack = .;\n        __stack = .;\n        KEEP(*(.stack))\n    } > REGION_STACK\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"e11a491c150fcd4a2ad38ce8112681112c54f8e9","subject":"imx_usb.lds is auto-generated","message":"imx_usb.lds is auto-generated\n","repos":"vstehle\/imx_usb_loader,bwalle\/imx_usb_loader,pacificIT\/imx_usb_loader,Adellica\/imx_usb_loader,boundarydevices\/imx_usb_loader,lucaceresoli\/imx_usb_loader","old_file":"imx_usb.lds","new_file":"imx_usb.lds","new_contents":"","old_contents":"\/* Script for -z combreloc: combine and sort reloc sections *\/\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\",\n\t      \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\"\/usr\/i486-linux-gnu\/lib32\"); SEARCH_DIR(\"\/usr\/local\/lib32\"); SEARCH_DIR(\"\/lib32\"); SEARCH_DIR(\"\/usr\/lib32\"); SEARCH_DIR(\"\/usr\/i486-linux-gnu\/lib\"); SEARCH_DIR(\"\/usr\/local\/lib\"); SEARCH_DIR(\"\/lib\"); SEARCH_DIR(\"\/usr\/lib\");\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = SEGMENT_START(\"text-segment\", 0x08048000)); . = SEGMENT_START(\"text-segment\", 0x08048000) + SIZEOF_HEADERS;\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n      *(.rel.ifunc)\n    }\n  .rel.plt        :\n    {\n      *(.rel.plt)\n      PROVIDE_HIDDEN (__rel_iplt_start = .);\n      *(.rel.iplt)\n      PROVIDE_HIDDEN (__rel_iplt_end = .);\n    }\n  .init           :\n  {\n    KEEP (*(.init))\n  } =0x90909090\n  .plt            : { *(.plt) *(.iplt) }\n  .text           :\n  {\n    *(.text.unlikely .text.*_unlikely)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } =0x90909090\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } =0x90909090\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n  .init_array     :\n  {\n     PROVIDE_HIDDEN (__init_array_start = .);\n     KEEP (*(SORT(.init_array.*)))\n     KEEP (*(.init_array))\n     PROVIDE_HIDDEN (__init_array_end = .);\n  }\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .jcr            : { KEEP (*(.jcr)) }\n  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }\n  .dynamic        : { *(.dynamic) }\n  .got            : { *(.got) *(.igot) }\n  . = DATA_SEGMENT_RELRO_END (12, .);\n  .got.plt        : { *(.got.plt)  *(.igot.plt) }\n  .data           :\n  {\n     __processor_info_start = .;     *(.data.processor_info);     __processor_info_end = .;\n    *(.data .data.* .gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .data1          : { *(.data1) }\n  _edata = .; PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.\n      FIXME: Why do we need it? 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{"commit":"568ecaa26fd8551a7597b6e1f46898b511a5f5f6","subject":"Fixed linker script formatting; unbreaks master for real","message":"Fixed linker script formatting; unbreaks master for real\n","repos":"gapry\/zinc,dirvine\/zinc,ryankurte\/zinc,placrosse\/zinc,dirvine\/zinc,ryankurte\/zinc,hackndev\/zinc,ntwyman\/zinc,ntwyman\/zinc,farcaller\/zinc,phil-opp\/zinc,mcoffin\/zinc,ntwyman\/zinc,tempbottle\/zinc,hackndev\/zinc,troplin\/zinc,posborne\/zinc,aethaniel\/zinc,hackndev\/zinc,farcaller\/zinc,mcoffin\/zinc,dirvine\/zinc,gapry\/zinc,richo\/zinc,dirvine\/zinc,phil-opp\/zinc,posborne\/zinc,placrosse\/zinc,ntwyman\/zinc,mcoffin\/zinc,dirvine\/zinc,ryankurte\/zinc,hackndev\/zinc,mcoffin\/zinc,richo\/zinc,hugwijst\/zinc,phil-opp\/zinc,hugwijst\/zinc,hackndev\/zinc,richo\/zinc,placrosse\/zinc,ryankurte\/zinc,richo\/zinc,tempbottle\/zinc,troplin\/zinc,tempbottle\/zinc,tempbottle\/zinc,placrosse\/zinc,troplin\/zinc,aethaniel\/zinc,placrosse\/zinc,mcoffin\/zinc,ryankurte\/zinc,troplin\/zinc,0xc0170\/zinc,darayus\/zinc,farcaller\/zinc,posborne\/zinc,darayus\/zinc,phil-opp\/zinc,richo\/zinc,farcaller\/zinc,troplin\/zinc,phil-opp\/zinc,tempbottle\/zinc,posborne\/zinc,ntwyman\/zinc,0xc0170\/zinc,posborne\/zinc,farcaller\/zinc","old_file":"src\/zinc\/hal\/k20\/iomem.ld","new_file":"src\/zinc\/hal\/k20\/iomem.ld","new_contents":"INCLUDE .\/src\/zinc\/hal\/cortex_m3\/armmem.ld\n\nPROVIDE(isr_dma_0           = isr_default_fault);\nPROVIDE(isr_dma_1           = isr_default_fault);\nPROVIDE(isr_dma_2           = isr_default_fault);\nPROVIDE(isr_dma_3           = isr_default_fault);\nPROVIDE(isr_dma_4           = isr_default_fault);\nPROVIDE(isr_dma_5           = isr_default_fault);\nPROVIDE(isr_dma_6           = isr_default_fault);\nPROVIDE(isr_dma_7           = isr_default_fault);\nPROVIDE(isr_dma_8           = isr_default_fault);\nPROVIDE(isr_dma_9           = isr_default_fault);\nPROVIDE(isr_dma_10          = isr_default_fault);\nPROVIDE(isr_dma_11          = isr_default_fault);\nPROVIDE(isr_dma_12          = isr_default_fault);\nPROVIDE(isr_dma_13          = isr_default_fault);\nPROVIDE(isr_dma_14          = isr_default_fault);\nPROVIDE(isr_dma_15          = isr_default_fault);\nPROVIDE(isr_dma_err         = isr_default_fault);\nPROVIDE(isr_flash_complete  = isr_default_fault);\nPROVIDE(isr_flash_collision = isr_default_fault);\nPROVIDE(isr_low_volt        = isr_default_fault);\nPROVIDE(isr_llwu            = isr_default_fault);\nPROVIDE(isr_wdt             = isr_default_fault);\nPROVIDE(isr_i2c_0           = isr_default_fault);\nPROVIDE(isr_i2c_1           = isr_default_fault);\nPROVIDE(isr_spi_0           = isr_default_fault);\nPROVIDE(isr_spi_1           = isr_default_fault);\nPROVIDE(isr_can_0_msg       = isr_default_fault);\nPROVIDE(isr_can_0_bus       = isr_default_fault);\nPROVIDE(isr_can_0_err       = isr_default_fault);\nPROVIDE(isr_can_0_tx        = isr_default_fault);\nPROVIDE(isr_can_0_rx        = isr_default_fault);\nPROVIDE(isr_can_0_wake      = isr_default_fault);\nPROVIDE(isr_i2s_0_tx        = isr_default_fault);\nPROVIDE(isr_i2s_0_rx        = isr_default_fault);\nPROVIDE(isr_uart_0_lon      = isr_default_fault);\nPROVIDE(isr_uart_0_stat     = isr_default_fault);\nPROVIDE(isr_uart_0_err      = isr_default_fault);\nPROVIDE(isr_uart_1_stat     = isr_default_fault);\nPROVIDE(isr_uart_1_err      = isr_default_fault);\nPROVIDE(isr_uart_2_stat     = isr_default_fault);\nPROVIDE(isr_uart_2_err      = isr_default_fault);\nPROVIDE(isr_adc_0           = isr_default_fault);\nPROVIDE(isr_adc_1           = isr_default_fault);\nPROVIDE(isr_cmp_0           = isr_default_fault);\nPROVIDE(isr_cmp_1           = isr_default_fault);\nPROVIDE(isr_cmp_2           = isr_default_fault);\nPROVIDE(isr_ftm_0           = isr_default_fault);\nPROVIDE(isr_ftm_1           = isr_default_fault);\nPROVIDE(isr_ftm_2           = isr_default_fault);\nPROVIDE(ist_cmt             = isr_default_fault);\nPROVIDE(isr_rtc_alarm       = isr_default_fault);\nPROVIDE(isr_rtc_tick        = isr_default_fault);\nPROVIDE(isr_pit_0           = isr_default_fault);\nPROVIDE(isr_pit_1           = isr_default_fault);\nPROVIDE(isr_pit_2           = isr_default_fault);\nPROVIDE(isr_pit_3           = isr_default_fault);\nPROVIDE(isr_pdb             = isr_default_fault);\nPROVIDE(isr_usb             = isr_default_fault);\nPROVIDE(isr_usb_dcd         = isr_default_fault);\nPROVIDE(isr_dac_0           = isr_default_fault);\nPROVIDE(isr_tsi             = isr_default_fault);\nPROVIDE(isr_mcg             = isr_default_fault);\nPROVIDE(isr_lptimer         = isr_default_fault);\nPROVIDE(isr_port_a          = isr_default_fault);\nPROVIDE(isr_port_b          = isr_default_fault);\nPROVIDE(isr_port_c          = isr_default_fault);\nPROVIDE(isr_port_d          = isr_default_fault);\nPROVIDE(isr_port_e          = isr_default_fault);\nPROVIDE(isr_soft            = isr_default_fault);\n\n\/*\n  This originated from the Freescale K20 Sub-Family Reference Manual\n  Document number K20P48M50SF0RM, Rev. 2\n*\/\n\nk20_iomem_PERIPH0   = 0x40000000;\n\nk20_iomem_CROSSBAR  = 0x40004000;\n\nk20_iomem_DMACON    = 0x40008000;\nk20_iomem_DMATCD    = 0x40009000;\n\nk20_iomem_FLASHCON  = 0x4001F000;\nk20_iomem_FLASH     = 0x40020000;\nk20_iomem_DMAMUX0   = 0x40021000;\n\nk20_iomem_CAN0      = 0x40024000;\n\nk20_iomem_SPI0      = 0x4002C000;\nk20_iomem_SPI1      = 0x4002D000;\nk20_iomem_I2S0      = 0x4002F000;\n\nk20_iomem_CRC       = 0x40032000;\n\nk20_iomem_USBDCD    = 0x40035000;\nk20_iomem_PDB       = 0x40036000;\nk20_iomem_PIT       = 0x40037000;\nk20_iomem_FTM0      = 0x40038000;\nk20_iomem_FTM1      = 0x40039000;\n\nk20_iomem_ADC0      = 0x4003B000;\n\nk20_iomem_RTC       = 0x4003D000;\nk20_iomem_VBAT      = 0x4003E000;\n\nk20_iomem_LPTMR     = 0x40040000;\nk20_iomem_SYSREG    = 0x40041000;\n\nk20_iomem_TSI       = 0x40045000;\n\nk20_iomem_SIM       = 0x40047000;\nk20_iomem_PORTA     = 0x40049000;\nk20_iomem_PORTB     = 0x4004A000;\nk20_iomem_PORTC     = 0x4004B000;\nk20_iomem_PORTD     = 0x4004C000;\nk20_iomem_PORTE     = 0x4004D000;\n\nk20_iomem_WDINT     = 0x40052000;\n\nk20_iomem_WDEXT     = 0x40061000;\nk20_iomem_CMT       = 0x40062000;\n\nk20_iomem_MCG       = 0x40064000;\nk20_iomem_OSC       = 0x40065000;\nk20_iomem_I2C0      = 0x40066000;\nk20_iomem_I2C1      = 0x40067000;\n\nk20_iomem_UART0     = 0x4006A000;\nk20_iomem_UART1     = 0x4006B000;\nk20_iomem_UART2     = 0x4006C000;\n\nk20_iomem_USB       = 0x40072000;\nk20_iomem_CMP       = 0x40073000;\nk20_iomem_VREF      = 0x40074000;\n\nk20_iomem_LLWU      = 0x4007C000;\nk20_iomem_PMC       = 0x4007D000;\nk20_iomem_SMC       = 0x4007E000;\nk20_iomem_RCM       = 0x4007F000;\n\n\nk20_iomem_PERIPH1   = 0x40080000;\n\nk20_iomem_FTM2      = 0x400B8000;\n\nk20_iomem_ADC1      = 0x400BB000;\n\nk20_iomem_DAC0      = 0x400CC000;\n\nk20_iomem_GPIOA     = 0x400ff000;\nk20_iomem_GPIOB     = 0x400ff040;\nk20_iomem_GPIOC     = 0x400ff080;\nk20_iomem_GPIOD     = 0x400ff0C0;\nk20_iomem_GPIOE     = 0x400ff100;\n\nk20_iomem_WDOG      = 0x40052000;\n","old_contents":"INCLUDE .\/src\/zinc\/hal\/cortex_m3\/armmem.ld\n\nPROVIDE(isr_dma_0           = isr_default_fault);\nPROVIDE(isr_dma_1           = isr_default_fault);\nPROVIDE(isr_dma_2           = isr_default_fault);\nPROVIDE(isr_dma_3           = isr_default_fault);\nPROVIDE(isr_dma_4           = isr_default_fault);\nPROVIDE(isr_dma_5           = isr_default_fault);\nPROVIDE(isr_dma_6           = isr_default_fault);\nPROVIDE(isr_dma_7           = isr_default_fault);\nPROVIDE(isr_dma_8           = isr_default_fault);\nPROVIDE(isr_dma_9           = isr_default_fault);\nPROVIDE(isr_dma_10          = isr_default_fault);\nPROVIDE(isr_dma_11          = isr_default_fault);\nPROVIDE(isr_dma_12          = isr_default_fault);\nPROVIDE(isr_dma_13          = isr_default_fault);\nPROVIDE(isr_dma_14          = isr_default_fault);\nPROVIDE(isr_dma_15          = isr_default_fault);\nPROVIDE(isr_dma_err         = isr_default_fault);\nPROVIDE(isr_flash_complete  = isr_default_fault);\nPROVIDE(isr_flash_collision = isr_default_fault);\nPROVIDE(isr_low_volt        = isr_default_fault);\nPROVIDE(isr_llwu            = isr_default_fault);\nPROVIDE(isr_wdt             = isr_default_fault);\nPROVIDE(isr_i2c_0           = isr_default_fault);\nPROVIDE(isr_i2c_1           = isr_default_fault);\nPROVIDE(isr_spi_0           = isr_default_fault);\nPROVIDE(isr_spi_1           = isr_default_fault);\nPROVIDE(isr_can_0_msg       = isr_default_fault);\nPROVIDE(isr_can_0_bus       = isr_default_fault);\nPROVIDE(isr_can_0_err       = isr_default_fault);\nPROVIDE(isr_can_0_tx        = isr_default_fault);\nPROVIDE(isr_can_0_rx        = isr_default_fault);\nPROVIDE(isr_can_0_wake      = isr_default_fault);\nPROVIDE(isr_i2s_0_tx        = isr_default_fault);\nPROVIDE(isr_i2s_0_rx        = isr_default_fault);\nPROVIDE(isr_uart_0_lon      = isr_default_fault);\nPROVIDE(isr_uart_0_stat     = isr_default_fault);\nPROVIDE(isr_uart_0_err      = isr_default_fault);\nPROVIDE(isr_uart_1_stat     = isr_default_fault);\nPROVIDE(isr_uart_1_err      = isr_default_fault);\nPROVIDE(isr_uart_2_stat     = isr_default_fault);\nPROVIDE(isr_uart_2_err      = isr_default_fault);\nPROVIDE(isr_adc_0           = isr_default_fault);\nPROVIDE(isr_adc_1           = isr_default_fault);\nPROVIDE(isr_cmp_0           = isr_default_fault);\nPROVIDE(isr_cmp_1           = isr_default_fault);\nPROVIDE(isr_cmp_2           = isr_default_fault);\nPROVIDE(isr_ftm_0           = isr_default_fault);\nPROVIDE(isr_ftm_1           = isr_default_fault);\nPROVIDE(isr_ftm_2           = isr_default_fault);\nPROVIDE(ist_cmt             = isr_default_fault);\nPROVIDE(isr_rtc_alarm       = isr_default_fault);\nPROVIDE(isr_rtc_tick        = isr_default_fault);\nPROVIDE(isr_pit_0           = isr_default_fault);\nPROVIDE(isr_pit_1           = isr_default_fault);\nPROVIDE(isr_pit_2           = isr_default_fault);\nPROVIDE(isr_pit_3           = isr_default_fault);\nPROVIDE(isr_pdb             = isr_default_fault);\nPROVIDE(isr_usb             = isr_default_fault);\nPROVIDE(isr_usb_dcd         = isr_default_fault);\nPROVIDE(isr_dac_0           = isr_default_fault);\nPROVIDE(isr_tsi             = isr_default_fault);\nPROVIDE(isr_mcg             = isr_default_fault);\nPROVIDE(isr_lptimer         = isr_default_fault);\nPROVIDE(isr_port_a          = isr_default_fault);\nPROVIDE(isr_port_b          = isr_default_fault);\nPROVIDE(isr_port_c          = isr_default_fault);\nPROVIDE(isr_port_d          = isr_default_fault);\nPROVIDE(isr_port_e          = isr_default_fault);\nPROVIDE(isr_soft            = isr_default_fault);\n\n# This originated from the Freescale K20 Sub-Family Reference Manual\n# Document number K20P48M50SF0RM, Rev. 2\n\nk20_iomem_PERIPH0   = 0x40000000;\n\nk20_iomem_CROSSBAR  = 0x40004000;\n\nk20_iomem_DMACON    = 0x40008000;\nk20_iomem_DMATCD    = 0x40009000;\n\nk20_iomem_FLASHCON  = 0x4001F000;\nk20_iomem_FLASH     = 0x40020000;\nk20_iomem_DMAMUX0   = 0x40021000;\n\nk20_iomem_CAN0      = 0x40024000;\n\nk20_iomem_SPI0      = 0x4002C000;\nk20_iomem_SPI1      = 0x4002D000;\nk20_iomem_I2S0      = 0x4002F000;\n\nk20_iomem_CRC       = 0x40032000;\n\nk20_iomem_USBDCD    = 0x40035000;\nk20_iomem_PDB       = 0x40036000;\nk20_iomem_PIT       = 0x40037000;\nk20_iomem_FTM0      = 0x40038000;\nk20_iomem_FTM1      = 0x40039000;\n\nk20_iomem_ADC0      = 0x4003B000;\n\nk20_iomem_RTC       = 0x4003D000;\nk20_iomem_VBAT      = 0x4003E000;\n\nk20_iomem_LPTMR     = 0x40040000;\nk20_iomem_SYSREG    = 0x40041000;\n\nk20_iomem_TSI       = 0x40045000;\n\nk20_iomem_SIM       = 0x40047000;\nk20_iomem_PORTA     = 0x40049000;\nk20_iomem_PORTB     = 0x4004A000;\nk20_iomem_PORTC     = 0x4004B000;\nk20_iomem_PORTD     = 0x4004C000;\nk20_iomem_PORTE     = 0x4004D000;\n\nk20_iomem_WDINT     = 0x40052000;\n\nk20_iomem_WDEXT     = 0x40061000;\nk20_iomem_CMT       = 0x40062000;\n\nk20_iomem_MCG       = 0x40064000;\nk20_iomem_OSC       = 0x40065000;\nk20_iomem_I2C0      = 0x40066000;\nk20_iomem_I2C1      = 0x40067000;\n\nk20_iomem_UART0     = 0x4006A000;\nk20_iomem_UART1     = 0x4006B000;\nk20_iomem_UART2     = 0x4006C000;\n\nk20_iomem_USB       = 0x40072000;\nk20_iomem_CMP       = 0x40073000;\nk20_iomem_VREF      = 0x40074000;\n\nk20_iomem_LLWU      = 0x4007C000;\nk20_iomem_PMC       = 0x4007D000;\nk20_iomem_SMC       = 0x4007E000;\nk20_iomem_RCM       = 0x4007F000;\n\n\nk20_iomem_PERIPH1   = 0x40080000;\n\nk20_iomem_FTM2      = 0x400B8000;\n\nk20_iomem_ADC1      = 0x400BB000;\n\nk20_iomem_DAC0      = 0x400CC000;\n\nk20_iomem_GPIOA     = 0x400ff000;\nk20_iomem_GPIOB     = 0x400ff040;\nk20_iomem_GPIOC     = 0x400ff080;\nk20_iomem_GPIOD     = 0x400ff0C0;\nk20_iomem_GPIOE     = 0x400ff100;\n\nk20_iomem_WDOG      = 0x40052000;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d212e698d7dd83beb0aeb0366eaf11faf126af39","subject":"rtc: fix rtc slow memory layout on esp32s3","message":"rtc: fix rtc slow memory layout on esp32s3\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp32s3\/ld\/esp32s3.ld","new_file":"components\/esp32s3\/ld\/esp32s3.ld","new_contents":"\/**\n *                    ESP32-S3 Linker Script Memory Layout\n * This file describes the memory layout (memory blocks) by virtual memory addresses.\n * This linker script is passed through the C preprocessor to include configuration options.\n * Please use preprocessor features sparingly!\n * Restrict to simple macros with numeric values, and\/or #if\/#endif blocks.\n *\/\n\n#include \"sdkconfig.h\"\n\n#define SRAM_IRAM_START     0x40370000\n#define SRAM_DRAM_START     0x3FC80000\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403BA000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)\n\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\nASSERT((CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), \"Fixed static ram data does not fit.\")\n#define DRAM0_0_SEG_LEN CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE\n#else\n#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE\n#endif \/\/ CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\nMEMORY\n{\n  \/**\n   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n   *  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n   *  are connected to the data port of the CPU and eg allow byte-wise access.\n   *\/\n\n  \/* IRAM for PRO CPU. *\/\n  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped instruction data *\/\n  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x8000000-0x20\n\n  \/**\n   * (0x20 offset above is a convenience for the app binary image generation.\n   * Flash cache has 64KB pages. The .bin file which is flashed to the chip\n   * has a 0x18 byte file header, and each segment has a 0x08 byte segment\n   * header. Setting this offset makes it simple to meet the flash cache MMU's\n   * constraint that (paddr % 64KB == vaddr % 64KB).)\n   *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.\n   *\/\n  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x8000000-0x20\n\n  \/* (See iram0_2_seg for meaning of 0x20 offset in the above.) *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x600fe000, len = 0x2000\n\n  \/**\n   * RTC fast memory (same block as above), viewed from data bus\n   *\/\n  rtc_data_seg(RW) :                 org = 0x600fe000, len = 0x2000\n\n  \/**\n   * RTC slow memory (data accessible). Persists over deep sleep.\n   * Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n   *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM\n}\n\n#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\/* static data ends at defined address *\/\n_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;\n#else\n_static_data_end = _bss_end;\n#endif \/\/ CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000;\n\n_data_seg_org = ORIGIN(rtc_data_seg);\n\n#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM\nREGION_ALIAS(\"rtc_data_location\", rtc_slow_seg );\n#else\nREGION_ALIAS(\"rtc_data_location\", rtc_data_seg );\n#endif \/\/ CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\nREGION_ALIAS(\"default_code_seg\", iram0_2_seg);\n#else\nREGION_ALIAS(\"default_code_seg\", iram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\nREGION_ALIAS(\"default_rodata_seg\", drom0_0_seg);\n#else\nREGION_ALIAS(\"default_rodata_seg\", dram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n","old_contents":"\/**\n *                    ESP32-S3 Linker Script Memory Layout\n * This file describes the memory layout (memory blocks) by virtual memory addresses.\n * This linker script is passed through the C preprocessor to include configuration options.\n * Please use preprocessor features sparingly!\n * Restrict to simple macros with numeric values, and\/or #if\/#endif blocks.\n *\/\n\n#include \"sdkconfig.h\"\n\n#define SRAM_IRAM_START     0x40370000\n#define SRAM_DRAM_START     0x3FC80000\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403BA000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)\n\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\nASSERT((CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), \"Fixed static ram data does not fit.\")\n#define DRAM0_0_SEG_LEN CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE\n#else\n#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE\n#endif \/\/ CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\nMEMORY\n{\n  \/**\n   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n   *  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n   *  are connected to the data port of the CPU and eg allow byte-wise access.\n   *\/\n\n  \/* IRAM for PRO CPU. *\/\n  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped instruction data *\/\n  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x8000000-0x20\n\n  \/**\n   * (0x20 offset above is a convenience for the app binary image generation.\n   * Flash cache has 64KB pages. The .bin file which is flashed to the chip\n   * has a 0x18 byte file header, and each segment has a 0x08 byte segment\n   * header. Setting this offset makes it simple to meet the flash cache MMU's\n   * constraint that (paddr % 64KB == vaddr % 64KB).)\n   *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.\n   *\/\n  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x8000000-0x20\n\n  \/* (See iram0_2_seg for meaning of 0x20 offset in the above.) *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x600fe000, len = 0x2000\n\n  \/**\n   * RTC fast memory (same block as above), viewed from data bus\n   *\/\n  rtc_data_seg(RW) :                 org = 0x3ff80000, len = 0x2000\n\n  \/**\n   * RTC slow memory (data accessible). Persists over deep sleep.\n   * Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n   *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x1000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM\n}\n\n#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\/* static data ends at defined address *\/\n_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;\n#else\n_static_data_end = _bss_end;\n#endif \/\/ CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000;\n\n_data_seg_org = ORIGIN(rtc_data_seg);\n\n#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM\nREGION_ALIAS(\"rtc_data_location\", rtc_slow_seg );\n#else\nREGION_ALIAS(\"rtc_data_location\", rtc_data_seg );\n#endif \/\/ CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\nREGION_ALIAS(\"default_code_seg\", iram0_2_seg);\n#else\nREGION_ALIAS(\"default_code_seg\", iram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\nREGION_ALIAS(\"default_rodata_seg\", drom0_0_seg);\n#else\nREGION_ALIAS(\"default_rodata_seg\", dram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"0bf1dfcd326a0c542ac139885f2c7db1081745d9","subject":"Fix linker script","message":"Fix linker script\n","repos":"achanda\/redox,freakynit\/redox,achanda\/redox,skylerberg\/redox,nxnfufunezn\/redox,alwayrun\/redox,bradparks\/redox,LazyOxen\/redox,alwayrun\/redox,nxnfufunezn\/redox,fischmax\/redox,bradparks\/redox,esell\/redox,imp\/redox,achanda\/redox,nounoursheureux\/redox,tedsta\/redox,tedsta\/redox,bradparks\/redox,LazyOxen\/redox,tedsta\/redox,freakynit\/redox,NobbZ\/redox,Drooids\/redox,shaunstanislaus\/redox,dirvine\/redox,dirvine\/redox,Drooids\/redox,freakynit\/redox,stryan\/redox,shaunstanislaus\/redox,esell\/redox,bheesham\/redox,nounoursheureux\/redox,vvlevchenko\/redox,vvlevchenko\/redox,freakynit\/redox,alexzhang2015\/redox,Drooids\/redox,shaunstanislaus\/redox,bradparks\/redox,fischmax\/redox,LazyOxen\/redox,NobbZ\/redox,skylerberg\/redox,bheesham\/redox,fischmax\/redox,dirvine\/redox,alwayrun\/redox,stryan\/redox,alwayrun\/redox,esell\/redox,fischmax\/redox,bradparks\/redox,bheesham\/redox,LazyOxen\/redox,Drooids\/redox,skylerberg\/redox,alexzhang2015\/redox,NobbZ\/redox,alwayrun\/redox,alexzhang2015\/redox,Drooids\/redox,esell\/redox,alexzhang2015\/redox,esell\/redox,bheesham\/redox,nxnfufunezn\/redox,NobbZ\/redox,shaunstanislaus\/redox,skylerberg\/redox,alexzhang2015\/redox,dirvine\/redox,dirvine\/redox,shaunstanislaus\/redox,nounoursheureux\/redox,stryan\/redox,imp\/redox,imp\/redox,tedsta\/redox,stryan\/redox,vvlevchenko\/redox,freakynit\/redox","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(kernel)\nOUTPUT_FORMAT(elf32-i386)\n\nMEMORY {\n\tlowmem : org = 0xC000, l = 256K\n}\n\nSECTIONS {\n\t.text : {\n\t\t*(.text*)\n\t} >lowmem\n\n\t.data : {\n\t\t*(.data*)\n\t} >lowmem\n\n\t.rodata : {\n\t\t*(.rodata*)\n\t} >lowmem\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t\t*(.eh_frame)\n\t\t*(.rel.eh_frame)\n\t}\n}\n","old_contents":"ENTRY(kernel)\nOUTPUT_FORMAT(elf32-i386)\n\nMEMORY {\n\tlowmem : org = 0xC000, l = 256K\n}\n\nSECTIONS {\n\t.text : {\n\t\t*(.text*)\n\t} >lowmem\n\n\t.data: {\n\t\t*(.data*)\n\t} >lowmem\n\n\t.rodata: {\n\t\t*(.rodata*)\n\t} >lowmem\n\n\t\/DISCARD\/ : {\n\t\t*(.comment)\n\t\t*(.eh_frame)\n\t\t*(.rel.eh_frame)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5c48f2aa7f7fbf1b9af57986209c0338e1e31bac","subject":"update ld script","message":"update ld script\n","repos":"sinneb\/wakefield,thi-ng\/ws-ldn-12,thi-ng\/ws-ldn-12,sinneb\/wakefield,sinneb\/wakefield","old_file":"STM32F746NGHx_FLASH.ld","new_file":"STM32F746NGHx_FLASH.ld","new_contents":"\/*\n * Default linker script for Cortex-M (it includes specifics for STM32F[34]xx).\n * Based on GNU ARM Eclipse & STM32F7Cube templates\n *\/\n\n\/* Boot entry (defined in startup_stm32f746xx.s) *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY {\n  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 320K\n  \/*\n   * SRAM starts at 0xC0000000, but we reserve memory\n   * for two LCD screen buffers (800 * 480 * 4 * 2)\n   *\/\n  SRAM (xrw)  : ORIGIN = 0xC02EE000, LENGTH = 5192K\n}\n\n\/* Highest address of the user mode stack *\/\n__stack = ORIGIN(RAM) + LENGTH(RAM);\n_estack = __stack; \/* STM specific *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Define output sections *\/\nSECTIONS {\n  \/*\n   * For Cortex-M devices, the beginning of the startup code is stored in\n   * the .isr_vector section, which goes to FLASH.\n   *\/\n  .isr_vector : ALIGN(4) {\n    KEEP(*(.isr_vector)) \/* ISR jump table *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* Program code and other data goes into FLASH *\/\n  .text : ALIGN(4) {\n    *(.text .text.*)\n    \/*\n\t\t * Stub sections generated by the linker, to glue together\n\t\t * ARM and Thumb code. .glue_7 is used for ARM code calling\n\t\t * Thumb code, and .glue_7t is used for Thumb code calling\n\t\t * ARM code. Apparently always generated by the linker, for some\n\t\t * architectures, so better leave them here.\n\t\t *\/\n    *(.glue_7 .glue_7t)\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data (constants, strings, etc.) goes into FLASH *\/\n  .rodata : ALIGN(4) {\n    *(.rodata .rodata*)\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab : ALIGN(4) {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } >FLASH\n\n  .ARM : ALIGN(4) {\n    __exidx_start = .;\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array : {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n\n  .init_array : {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n\n  .fini_array : {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : ALIGN(4) {\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  .bss (NOLOAD) : ALIGN(4) {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss .bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack : ALIGN(8) {\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F746NGHx Device with\n**                1024KByte FLASH, 320KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Ac6.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Ac6 permit registered System Workbench for MCU users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the System Workbench for MCU toolchain.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20050000;    \/* end of RAM *\/\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\nFLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 320K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e521e2f8fb944db5a525087d34975ccf0d1733e1","subject":"apps: app_test: fix entry function in ld scripts","message":"apps: app_test: fix entry function in ld scripts\n","repos":"raphui\/rnk,raphui\/rnk,raphui\/rnk,raphui\/rnk","old_file":"apps\/app_test\/apps.ld","new_file":"apps\/app_test\/apps.ld","new_contents":"ENTRY(test)\n\nSECTIONS\n{\n\t.text 0x00000000 :\n\t{\n\t\t*(.text)\n\t\t*(.text.*)\n\t}\n\n\t.rodata :\n\t{\n\t\t*(.rodata)\n\t\t*(.rodata1)\n\t\t*(.rodata.*)\n\t}\n\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.data1)\n\t\t*(.data.*)\n\t}\n\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t\t*(.sbss)\n\t\t*(.sbss.*)\n\t\t*(COMMON)\n\t}\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS\n{\n\t.text 0x00000000 :\n\t{\n\t\t*(.text)\n\t\t*(.text.*)\n\t}\n\n\t.rodata :\n\t{\n\t\t*(.rodata)\n\t\t*(.rodata1)\n\t\t*(.rodata.*)\n\t}\n\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.data1)\n\t\t*(.data.*)\n\t}\n\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t\t*(.sbss)\n\t\t*(.sbss.*)\n\t\t*(COMMON)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a60d0b369a20868def0c23f270cfd3ef4b999d2f","subject":"change name in custom script to be clearer that the section resides in flash","message":"change name in custom script to be clearer that the section resides in flash\n","repos":"PDXostc\/can_firewall_software,PDXostc\/can_firewall_software","old_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-avr32\", \"elf32-avr32\",\n\t      \"elf32-avr32\")\nOUTPUT_ARCH(avr32:uc)\nENTRY(_start)\nSEARCH_DIR(\"\/home\/toolsbuild\/jenkins-knuth\/workspace\/avr32-gnu-toolchain\/avr32-gnu-toolchain-win32_x86\/avr32\/lib\");\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY\n{\n    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K-10K-8K\n\t\tFLASHRSVD (rxai!w) : ORIGIN = 0x80000000+512K-10K-8K, LENGTH = 10K\n    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC\n    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512\n    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512\n    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8\n    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8\n}\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;\n\t\/* Next line should not be necessary for use of flash for storing rules *\/\n\t\/* .flash-rsvd : { *(.flash-rsvd) } >FLASHRSVD AT>FLASHRSVD *\/\n  .interp         : { *(.interp) } >FLASH AT>FLASH\n  .reset : {  *(.reset) } >FLASH AT>FLASH\n  .hash           : { *(.hash) } >FLASH AT>FLASH\n  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH\n  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH\n  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH\n  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH\n  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH\n  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH\n  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH\n  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH\n  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH\n  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH\n  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH\n  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH\n  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH\n  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH\n  .init           :\n  {\n    KEEP (*(.init))\n  } >FLASH AT>FLASH =0xd703d703\n  .plt            : { *(.plt) } >FLASH AT>FLASH\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } >FLASH AT>FLASH =0xd703d703\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } >FLASH AT>FLASH =0xd703d703\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH\n  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH\n  .dalign\t: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH\n  PROVIDE (_data = ORIGIN(CPUSRAM));\n  . = ORIGIN(CPUSRAM);\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  PROVIDE (__preinit_array_start = ALIGN(32 \/ 8));\n  .preinit_array     : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >CPUSRAM AT>FLASH\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >CPUSRAM AT>FLASH\n  .jcr            : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH\n  .dynamic        : { *(.dynamic) } >CPUSRAM AT>FLASH\n  .got            : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH\n  .data           :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  } >CPUSRAM AT>FLASH\n  .data1          : { *(.data1) } >CPUSRAM AT>FLASH\n  .balign\t: { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(8);\n  } >CPUSRAM\n  . = ALIGN(8);\n  _end = .;\n  PROVIDE (end = .);\n  __heap_start__ = ALIGN(8);\n  . = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;\n  __heap_end__ = .;\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :\n  {\n    _stack = .;\n    *(.stack)\n    . = _stack_size;\n    _estack = .;\n  } >CPUSRAM\n  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE\n  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE\n\t.flash : { *(.flash .flash.*) } >FLASH AT>FLASH\n\t.flash-rsvd : { *(.flash-rsvd .flash-rsvd.*) } >FLASHRSVD AT>FLASHRSVD\n  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE\n  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-avr32\", \"elf32-avr32\",\n\t      \"elf32-avr32\")\nOUTPUT_ARCH(avr32:uc)\nENTRY(_start)\nSEARCH_DIR(\"\/home\/toolsbuild\/jenkins-knuth\/workspace\/avr32-gnu-toolchain\/avr32-gnu-toolchain-win32_x86\/avr32\/lib\");\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY\n{\n    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K-10K-8K\n\t\tRSVDFLASH (rxai!w) : ORIGIN = 0x80000000+512K-10K-8K, LENGTH = 10K\n    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC\n    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512\n    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512\n    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8\n    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8\n}\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;\n\t\/* Next line should not be necessary for use of flash for storing rules *\/\n\t\/* .rsvd_flash : { *(.rsvd_flash) } >RSVDFLASH AT>RSVDFLASH *\/\n  .interp         : { *(.interp) } >FLASH AT>FLASH\n  .reset : {  *(.reset) } >FLASH AT>FLASH\n  .hash           : { *(.hash) } >FLASH AT>FLASH\n  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH\n  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH\n  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH\n  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH\n  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH\n  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH\n  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH\n  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH\n  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH\n  .rel.tdata\t  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rela.tdata\t  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH\n  .rel.tbss\t  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rela.tbss\t  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH\n  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH\n  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH\n  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH\n  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH\n  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH\n  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH\n  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH\n  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH\n  .init           :\n  {\n    KEEP (*(.init))\n  } >FLASH AT>FLASH =0xd703d703\n  .plt            : { *(.plt) } >FLASH AT>FLASH\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n  } >FLASH AT>FLASH =0xd703d703\n  .fini           :\n  {\n    KEEP (*(.fini))\n  } >FLASH AT>FLASH =0xd703d703\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH\n  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH\n  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH\n  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH\n  .dalign\t: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH\n  PROVIDE (_data = ORIGIN(CPUSRAM));\n  . = ORIGIN(CPUSRAM);\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH\n  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM\n  \/* Ensure the __preinit_array_start label is properly aligned.  We\n     could instead move the label definition inside the section, but\n     the linker would then create the section even if it turns out to\n     be empty, which isn't pretty.  *\/\n  PROVIDE (__preinit_array_start = ALIGN(32 \/ 8));\n  .preinit_array     : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__preinit_array_end = .);\n  PROVIDE (__init_array_start = .);\n  .init_array     : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__init_array_end = .);\n  PROVIDE (__fini_array_start = .);\n  .fini_array     : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH\n  PROVIDE (__fini_array_end = .);\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >CPUSRAM AT>FLASH\n  .dtors          :\n  {\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >CPUSRAM AT>FLASH\n  .jcr            : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH\n  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH\n  .dynamic        : { *(.dynamic) } >CPUSRAM AT>FLASH\n  .got            : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH\n  .data           :\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n  } >CPUSRAM AT>FLASH\n  .data1          : { *(.data1) } >CPUSRAM AT>FLASH\n  .balign\t: { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH\n  _edata = .;\n  PROVIDE (edata = .);\n  __bss_start = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  *\/\n   . = ALIGN(8);\n  } >CPUSRAM\n  . = ALIGN(8);\n  _end = .;\n  PROVIDE (end = .);\n  __heap_start__ = ALIGN(8);\n  . = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;\n  __heap_end__ = .;\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .stack         ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :\n  {\n    _stack = .;\n    *(.stack)\n    . = _stack_size;\n    _estack = .;\n  } >CPUSRAM\n  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE\n  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE\n\t.flash : { *(.flash .flash.*) } >FLASH AT>FLASH\n\t.rsvd_flash : { *(.rsvd_flash .rsvd_flash.*) } >RSVDFLASH AT>RSVDFLASH\n  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE\n  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"4f78d86eb749d6458f9745ea9c5ea74a3362e4aa","subject":"arch: arm: linker.ld: Fixed incorrect placement of noinit section","message":"arch: arm: linker.ld: Fixed incorrect placement of noinit section\n\nThis was causing an incorrect hash for privileged stack.\n\nFixes: GH-10473\nFixes: GH-10474\nFixes: GH-10475\nFixes: GH-10476\n\nSigned-off-by: Adithya Baglody <06b44f6fa9a97a2b955c2d2cd070279967447860@intel.com>\n","repos":"nashif\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,ldts\/zephyr,explora26\/zephyr,ldts\/zephyr,explora26\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,ldts\/zephyr,explora26\/zephyr,ldts\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN . = ALIGN(4);\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t_app_smem_end = .;\n\t\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN . = ALIGN(4);\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t_app_smem_end = .;\n\t\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n#include <linker\/priv_stacks-noinit.ld>\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"781ce0bb3641298d5737895f6d9c38ab2a4dd52d","subject":"Fix issue in linker script generated by TrueStudio for STM32F0.","message":"Fix issue in linker script generated by TrueStudio for STM32F0.\n\ngit-svn-id: 43aea61533866f88f23079d48f4f5dc2d5288937@1693 1d2547de-c912-0410-9cb9-b8ca96c0e9e2\n","repos":"Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS","old_file":"Demo\/CORTEX_STM32F100_Atollic\/stm32_flash.ld","new_file":"Demo\/CORTEX_STM32F100_Atollic\/stm32_flash.ld","new_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F100RB Device with\n**                128KByte FLASH, 8KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  This file may be distributed and used with the FreeRTOS example project \n**  for Atollic TrueSTUDIO only. \n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20002000;    \/* end of 8K RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x80; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 8K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  PROVIDE ( end = _ebss );\n  PROVIDE ( _end = _ebss );\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\n  .memory_b1_text :\n  {\n    *(.mb1text)        \/* .mb1text sections (code) *\/\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\n    *(.mb1rodata)      \/* read-only data (constants) *\/\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32F100RB Device with\n**                128KByte FLASH, 8KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  This file may be distributed and used with the FreeRTOS example project \n**  for Atollic TrueSTUDIO only. \n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20002000;    \/* end of 8K RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x80; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 8K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n\t*(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n\n   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n    .ARM : {\n    __exidx_start = .;\n      *(.ARM.exidx*)\n      __exidx_end = .;\n    } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(.fini_array*))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  PROVIDE ( end = _ebss );\n  PROVIDE ( _end = _ebss );\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\n  .memory_b1_text :\n  {\n    *(.mb1text)        \/* .mb1text sections (code) *\/\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\n    *(.mb1rodata)      \/* read-only data (constants) *\/\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"100227cc851cc503448ae415ca97405125a7eeed","subject":"linker: arm: add SRAM3\/4 linker section","message":"linker: arm: add SRAM3\/4 linker section\n\nAdd a linker section for SRAM3\/4 if it is enabled in the device tree.\n\nSigned-off-by: Mario Jaun <d103db3e4f8d66d8732068e0cadccabd9c55aeb3@gmail.com>\n","repos":"galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr","old_file":"include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/devicetree_regions.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n#define _DATA_IN_ROM __data_rom_start\n#else\n#define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* TI CCFG Registers *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(FLASH_CCFG, rwx, DT_NODELABEL(ti_ccfg_partition))\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    DT_REGION_FROM_NODE_STATUS_OKAY(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n    \/* STM32 Core Coupled Memory *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(CCM, rw, DT_CHOSEN(zephyr_ccm))\n    \/* STM32WB IPC RAM *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(SRAM1, rw, DT_NODELABEL(sram1))\n    DT_REGION_FROM_NODE_STATUS_OKAY(SRAM2, rw, DT_NODELABEL(sram2))\n    \/* STM32 alternate RAM configurations *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(SRAM3, rw, DT_NODELABEL(sram3))\n    DT_REGION_FROM_NODE_STATUS_OKAY(SRAM4, rw, DT_NODELABEL(sram4))\n    DT_REGION_FROM_NODE_STATUS_OKAY(SDRAM1, rw, DT_NODELABEL(sdram1))\n    DT_REGION_FROM_NODE_STATUS_OKAY(SDRAM2, rw, DT_NODELABEL(sdram2))\n    DT_REGION_FROM_NODE_STATUS_OKAY(BACKUP_SRAM, rw, DT_NODELABEL(backup_sram))\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/devicetree_regions.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION FLASH\n#define RAMABLE_REGION SRAM\n#else\n#define ROMABLE_REGION SRAM\n#define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n#define _DATA_IN_ROM __data_rom_start\n#else\n#define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n#if defined(CONFIG_IS_BOOTLOADER)\n#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n#else\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_CUSTOM_SECTION_ALIGN)\n_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;\n#else\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n#endif\n\n#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* TI CCFG Registers *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(FLASH_CCFG, rwx, DT_NODELABEL(ti_ccfg_partition))\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(ITCM, rw, DT_CHOSEN(zephyr_itcm))\n    DT_REGION_FROM_NODE_STATUS_OKAY(DTCM, rw, DT_CHOSEN(zephyr_dtcm))\n    \/* STM32 Core Coupled Memory *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(CCM, rw, DT_CHOSEN(zephyr_ccm))\n    \/* STM32WB IPC RAM *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(SRAM1, rw, DT_NODELABEL(sram1))\n    DT_REGION_FROM_NODE_STATUS_OKAY(SRAM2, rw, DT_NODELABEL(sram2))\n    \/* STM32 alternate RAM configurations *\/\n    DT_REGION_FROM_NODE_STATUS_OKAY(SDRAM1, rw, DT_NODELABEL(sdram1))\n    DT_REGION_FROM_NODE_STATUS_OKAY(SDRAM2, rw, DT_NODELABEL(sdram2))\n    DT_REGION_FROM_NODE_STATUS_OKAY(BACKUP_SRAM, rw, DT_NODELABEL(backup_sram))\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(rom_start,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(\".TEXT.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n#ifndef CONFIG_USERSPACE\n   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n#endif \/* CONFIG_USERSPACE *\/\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8a955731fab6fbef0ebf2ddbea6d37007536a8c1","subject":"Separated rodata section in linker script.","message":"Separated rodata section in linker script.\n","repos":"shockkolate\/shockk-os,shockkolate\/shockk-os,shockkolate\/shockk-os","old_file":"link.ld","new_file":"link.ld","new_contents":"ENTRY(start)\nSECTIONS\n{\n\t.text :\n\t{\n\t\tcode = .; _code = .; __code = .;\n\t\t*(.text)\n\t\t. = ALIGN(512);\n\t}\n\n\t.data :\n\t{\n\t\tdata = .; _data = .; __data = .;\n\t\t*(.data)\n\t\t. = ALIGN(512);\n\t}\n\n\t.rodata :\n\t{\n\t\trodata = .; _rodata = .; __rodata = .;\n\t\t*(.rodata)\n\t\t. = ALIGN(512);\n\t}\n\n\t.bss :\n\t{\n\t\tbss = .; _bss = .; _bss = .;\n\t\t*(.bss)\n\t\t. = ALIGN(512);\n\t}\n\n\tend = .; _end = .; __end = .;\n}\n","old_contents":"ENTRY(start)\nSECTIONS\n{\n\t.text :\n\t{\n\t\tcode = .; _code = .; __code = .;\n\t\t*(.text)\n\t\t. = ALIGN(512);\n\t}\n\n\t.data :\n\t{\n\t\tdata = .; _data = .; __data = .;\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(512);\n\t}\n\n\t.bss :\n\t{\n\t\tbss = .; _bss = .; _bss = .;\n\t\t*(.bss)\n\t\t. = ALIGN(512);\n\t}\n\n\tend = .; _end = .; __end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4ebb77b89d0eb38af133ef02e15c60c54393877e","subject":"bsp\/hifive1: Reduce size of interrupt stack","message":"bsp\/hifive1: Reduce size of interrupt stack\n\nInterrupt stack was unreasonable large 2kB now it is\nreduced to 512 bytes leaving more ram for application.\n","repos":"mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core","old_file":"hw\/bsp\/hifive1\/hifive1.ld","new_file":"hw\/bsp\/hifive1\/hifive1.ld","new_contents":"\/*\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n *\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\nENTRY( _reset_handler )\n\nSECTIONS\n{\n  __stack_size = DEFINED(__stack_size) ? __stack_size : 512;\n  .imghdr (NOLOAD):\n  {\n      . = . + _imghdr_size;\n  } >flash\n\n  __text = .;\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >flash\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >flash\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n  } >flash\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash\n\n  .data          :\n  {\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n  } >ram AT>flash\n\n  .srodata        :\n  {\n    PROVIDE( _gp = . + 0x800 );\n    PROVIDE( __global_pointer$ = _gp);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n  } >ram AT>flash\n\n  .sdata          :\n  {\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n  } >ram AT>flash\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  .bssnz :\n  {\n      __bssnz_start__ = .;\n      *(.bss.core.nz*)\n      . = ALIGN(4);\n      __bssnz_end__ = .;\n      . = ALIGN(4);\n  } >ram\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _heap_end = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram\n\n  _ram_start = ORIGIN(ram);\n}\n","old_contents":"\/*\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n *\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\nENTRY( _reset_handler )\n\nSECTIONS\n{\n  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n  .imghdr (NOLOAD):\n  {\n      . = . + _imghdr_size;\n  } >flash\n\n  __text = .;\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >flash\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >flash\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n  } >flash\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash\n\n  .data          :\n  {\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n  } >ram AT>flash\n\n  .srodata        :\n  {\n    PROVIDE( _gp = . + 0x800 );\n    PROVIDE( __global_pointer$ = _gp);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n  } >ram AT>flash\n\n  .sdata          :\n  {\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n  } >ram AT>flash\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  .bssnz :\n  {\n      __bssnz_start__ = .;\n      *(.bss.core.nz*)\n      . = ALIGN(4);\n      __bssnz_end__ = .;\n      . = ALIGN(4);\n  } >ram\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _heap_end = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram\n\n  _ram_start = ORIGIN(ram);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bdcf58033a65581c190a8a826ff9aabd365b0733","subject":"x86: Group sections for QuarkX1000","message":"x86: Group sections for QuarkX1000\n\nChild sections can be created depending on the CFLAGS used when building Contiki.\nFor instance, if built with -ffunction-sections or -fdata-sections would create\none section per function\/variable and -Os sometimes split part of .text into one\nchild section.\n\nThis can also be an issue if we start linking with external libraries that are\nbuilt in such a way. Since we can't foresee how the port is going to be used,\nwe should make sure it is ready for the cases above.\n\nThis patch fixes this by correctly grouping child sections into their parent\nsections.\n\nPatch developed while investigating a bug with Jos\u00e9 Souza (jose.souza@intel.com).\n","repos":"MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,MohamedSeliem\/contiki,arurke\/contiki,arurke\/contiki","old_file":"cpu\/x86\/quarkX1000.ld","new_file":"cpu\/x86\/quarkX1000.ld","new_contents":"\/*\n * Copyright (C) 2015, Intel Corporation. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\nOUTPUT_FORMAT(\"elf32-i386\")\n\nENTRY(start)\n\nSECTIONS {\n    \/*\n       OS-Dev Wiki says it is common for kernels to start at 1M. Addresses before that\n       are used by BIOS\/EFI, the bootloader and memory-mapped I\/O.\n    *\/\n    . = 1M;\n\n    .text ALIGN (4K) :\n    {\n        *(.multiboot)\n        *(.text*)\n    }\n\n    .rodata ALIGN (4K) :\n    {\n        *(.rodata*)\n    }\n\n    .data ALIGN (4K) :\n    {\n        *(.data*)\n    }\n\n    .bss ALIGN (4K) :\n    {\n        *(COMMON)\n        *(.bss*)\n    }\n}\n","old_contents":"\/*\n * Copyright (C) 2015, Intel Corporation. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\nOUTPUT_FORMAT(\"elf32-i386\")\n\nENTRY(start)\n\nSECTIONS {\n    \/*\n       OS-Dev Wiki says it is common for kernels to start at 1M. Addresses before that\n       are used by BIOS\/EFI, the bootloader and memory-mapped I\/O.\n    *\/\n    . = 1M;\n\n    .text ALIGN (4K) :\n    {\n        *(.multiboot)\n        *(.text)\n    }\n\n    .rodata ALIGN (4K) :\n    {\n        *(.rodata*)\n    }\n\n    .data ALIGN (4K) :\n    {\n        *(.data)\n    }\n\n    .bss ALIGN (4K) :\n    {\n        *(COMMON)\n        *(.bss)\n    }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"1ee638199f2827b0a46d971e80b2c77fea3c4b76","subject":"emulator\/linker: update.","message":"emulator\/linker: update.\n","repos":"litex-hub\/linux-on-litex-vexriscv,litex-hub\/linux-on-litex-vexriscv","old_file":"emulator\/linker.ld","new_file":"emulator\/linker.ld","new_contents":"INCLUDE generated\/output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE generated\/regions.ld\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t_etext = .;\n\t} > emulator\n\n\t.rodata :\n\t{\n\t\t. = ALIGN(4);\n\t\t_frodata = .;\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.rodata1)\n\t\t_erodata = .;\n\t} > emulator\n\n\t.data :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fdata = .;\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t\t_gp = ALIGN(16);\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t_edata = .;\n\t} > emulator\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fbss = .;\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > emulator\n\n\t__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n\t.stack :\n\t{\n\t\tPROVIDE( _heap_end = . );\n\t\t. = __stack_size;\n\t\tPROVIDE( _sp = . );\n\t} > emulator\n}\n\nPROVIDE(_fstack = ORIGIN(emulator) + LENGTH(emulator) - 4);\n\nPROVIDE(_fdata_rom = LOADADDR(.data));\nPROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));\n","old_contents":"INCLUDE generated\/output_format.ld\nENTRY(_start)\n\n__DYNAMIC = 0;\n\nINCLUDE generated\/regions.ld\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t_ftext = .;\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t_etext = .;\n\t} > emulator\n\n\t.rodata :\n\t{\n\t\t. = ALIGN(4);\n\t\t_frodata = .;\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.rodata1)\n\t\t_erodata = .;\n\t} > emulator\n\n\t.data :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fdata = .;\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t\t_gp = ALIGN(16);\n\t\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t_edata = .;\n\t} > emulator\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t_fbss = .;\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t\t_end = .;\n\t} > emulator\n\n\t__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\n\t.stack :\n\t{\n\t\tPROVIDE( _heap_end = . );\n\t\t. = __stack_size;\n\t\tPROVIDE( _sp = . );\n\t} > emulator\n}\n\nPROVIDE(_fstack = ORIGIN(emulator) + LENGTH(emulator) - 4);\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"489bd3dec801b58fa6102c200f411a9e8f1a5bd2","subject":"stm32f413xh: add crash capture support for GCC_ARM","message":"stm32f413xh: add crash capture support for GCC_ARM\n","repos":"andcor02\/mbed-os,kjbracey-arm\/mbed,kjbracey-arm\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,kjbracey-arm\/mbed,mbedmicro\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,andcor02\/mbed-os","old_file":"targets\/TARGET_STM\/TARGET_STM32F4\/TARGET_STM32F413xH\/device\/TOOLCHAIN_GCC_ARM\/STM32F413xH.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32F4\/TARGET_STM32F413xH\/device\/TOOLCHAIN_GCC_ARM\/STM32F413xH.ld","new_contents":"#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 1536K\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\nM_CRASH_DATA_RAM_SIZE = 0x100;\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  RAM (rwx)  : ORIGIN = 0x200001D8, LENGTH = 320K - 0x1D8\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .crash_data_ram :\n    {\n        . = ALIGN(8);\n        __CRASH_DATA_RAM__ = .;\n        __CRASH_DATA_RAM_START__ = .; \/* Create a global symbol at data start *\/\n        KEEP(*(.keep.crash_data_ram))\n        *(.m_crash_data_ram)     \/* This is a user defined section *\/\n        . += M_CRASH_DATA_RAM_SIZE;\n        . = ALIGN(8);\n        __CRASH_DATA_RAM_END__ = .; \/* Define a global symbol at data end *\/\n    } > RAM\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 1536K\n#endif\n\n#if !defined(MBED_BOOT_STACK_SIZE)\n    #define MBED_BOOT_STACK_SIZE 0x400\n#endif\n\nSTACK_SIZE = MBED_BOOT_STACK_SIZE;\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  RAM (rwx)  : ORIGIN = 0x200001D8, LENGTH = 320K - 0x1D8\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(8);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(8);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(8);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(8);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(8);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(8);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4208bf192701640513a4c703ed9a8bb7542daa7e","subject":"xtensa: cavs_v18: use uncached addresses to support SMP","message":"xtensa: cavs_v18: use uncached addresses to support SMP\n\nSMP support on cAVS is implemented by using uncached addresses\nfor all writable data sections except for stack, i.e. for .data,\n.bss and some other specialised ones. So far that has been\nimplemented for cAVS 1.5. This patch does the same for cAVS 1.8.\n\nSigned-off-by: Guennadi Liakhovetski <974fc78730de35b120231422a86eeefcb293601e@linux.intel.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/cavs_v18\/linker.ld","new_file":"soc\/xtensa\/intel_adsp\/cavs_v18\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define LP_SRAM_REGION lpram\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP: once in\n * a 512MB region from 0x80000000-0x9fffffff and again from\n * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the\n * L1 cache, so it must be used when multiprocessor coherence is\n * desired, where the latter mapping is best used for processor-local\n * data (e.g. stacks) or shared data that is managed with explicit\n * cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram :ram_phdr\" or \">ucram :ucram_phdr\" as\n * appropriate. (Forgetting the correct PHDR will actually work, as\n * the output tooling ignores it, but it will cause the linker to emit\n * 512MB of unused data into the output file!)\n *\n *\/\n#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)\n#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n  ucram :\n\torg = RAM_BASE - 0x20000000,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n  ucram_phdr PT_LOAD;\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n_memmap_cacheattr_intel_cavs18_adsp = 0xFF42FFF2;\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit SEGSTART_UNCACHED : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram :ucram_phdr\n\n  .data SEGSTART_UNCACHED : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ucram :ucram_phdr\n\n  .lit4 SEGSTART_CACHED : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n\n  . = SEGSTART_UNCACHED;\n\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram :ucram_phdr\n#define ROMABLE_REGION ucram :ucram_phdr\n\n#include <linker\/common-ram.ld>\n\n  \/* This section is cached.  By default it contains only declared\n   * thread stacks, but applications can put symbols here too.\n   *\/\n  .cached SEGSTART_CACHED :\n  {\n    *(.cached .cached.*)\n  } >ram :ram_phdr\n\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ucram :ucram_phdr\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n\n  \/* Re-adjust to the upper mapping for the final symbols below *\/\n  . = SEGSTART_CACHED;\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n\n  . = SEGSTART_UNCACHED;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <soc\/memory.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nPROVIDE(__memctl_default = 0x00000000);\nPROVIDE(_MemErrorHandler = 0x00000000);\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#define LP_SRAM_REGION lpram\n\nMEMORY\n{\n  vector_memory_lit :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n\torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n\n  static_uuid_entries_seg (!ari) :\n        org = UUID_ENTRY_ELF_BASE,\n        len = UUID_ENTRY_ELF_SIZE\n  static_log_entries_seg (!ari) :\n        org = LOG_ENTRY_ELF_BASE,\n        len = LOG_ENTRY_ELF_SIZE\n  fw_metadata_seg (!ari) :\n        org = EXT_MANIFEST_ELF_BASE,\n        len = EXT_MANIFEST_ELF_SIZE\n}\n\nPHDRS\n{\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n\n  static_uuid_entries_phdr PT_NOTE;\n  static_log_entries_phdr PT_NOTE;\n  metadata_entries_phdr PT_NOTE;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n#ifndef CONFIG_SMP\n_memmap_cacheattr_intel_cavs18_adsp = 0xFF42FFF2;\n#else\n\/*\n * FIXME: Make 0xA0000000 - 0xBFFFFFFF to bypass cache under SMP\n * since there is no data cache manipulation for spinlock, kernel\n * object, scheduler, etc...\n *\/\n_memmap_cacheattr_intel_cavs18_adsp = 0xFF22FFF2;\n#endif\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp);\n\n_EXT_MAN_ALIGN_ = 16;\nEXTERN(ext_man_fw_ver)\nEXTERN(ext_man_cavs_config)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    KEEP(*(.MainEntry.text))\n    *(.MainEntry.literal)\n    KEEP (*(.ResetVector.text))\n    *(.ResetVector.literal)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .module_init : ALIGN(4)\n  {\n    _module_init_start = ABSOLUTE(.);\n    *(*.module_init)\n    _module_init_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n#include <linker\/common-rom.ld>\n\n  .fw_ready : ALIGN(4)\n  {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram :ram_phdr\n\n  .noinit : ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .bss (NOLOAD) : ALIGN(4096)\n  {\n    . = ALIGN(4096);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LP_SRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n .static_uuid_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_uuids)\n  } > static_uuid_entries_seg :static_uuid_entries_phdr\n\n  .static_log_entries (COPY) : ALIGN(1024)\n  {\n    *(*.static_log*)\n  } > static_log_entries_seg :static_log_entries_phdr\n\n  .fw_metadata (COPY) : ALIGN(1024)\n  {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(_EXT_MAN_ALIGN_);\n  } >fw_metadata_seg :metadata_entries_phdr\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"66aa3870a4be8382d28cc24cf3415114050bc494","subject":"some minor improvements","message":"some minor improvements\n","repos":"jezze\/fudge,jezze\/fudge,jezze\/fudge","old_file":"kernel\/arch\/x86\/linker.ld","new_file":"kernel\/arch\/x86\/linker.ld","new_contents":"ENTRY (init)\n\nSECTIONS\n{\n\n    . = 0x00100000;\n\n    .text ALIGN (0x1000) :\n    {\n        *(.mboot)\n        *(.text)\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        *(.rodata*)\n        *(.data)\n    }\n\n    .bss :\n    {\n        *(.bss)\n    }\n\n}\n","old_contents":"ENTRY (init)\n\nSECTIONS\n{\n\n    . = 0x00100000;\n\n    .text :\n    {\n        *(.mboot)\n        *(.text)\n    }\n\n    .data ALIGN (0x1000) :\n    {\n        *(.data)\n        *(.rodata)\n        *(.bss)\n    }\n\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"e6dd22113d15b7ba0a979a128b16cfc0ced6422e","subject":"linker: clarify CONFIG_KOBJECT_TEXT_AREA too small message","message":"linker: clarify CONFIG_KOBJECT_TEXT_AREA too small message\n\nThe assert error message when CONFIG_KOBJECT_TEXT_AREA is\ntoo small is confusing. Probably the original idea is for\nthe linker to substitue CONFIG_KOBJECT_TEXT_AREA with\nthe actual value. However, linker does not do that.\nSo change the message to say that the kconfig value needs\nto be increased.\n\nFixes #34387\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"galak\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/linker\/kobject-text.ld","new_file":"include\/linker\/kobject-text.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#ifdef CONFIG_USERSPACE\n\t\/* We need to reserve room for the gperf generated hash functions.\n\t * Fortunately, unlike the data tables, the size of the code is\n\t * reasonably predictable.\n\t *\n\t * The linker will error out complaining that the location pointer\n\t * is moving backwards if the reserved room isn't large enough.\n\t *\/\n\t_kobject_text_area_start = .;\n\t*(\".kobject_data.text*\")\n\t_kobject_text_area_end = .;\n\t_kobject_text_area_used = _kobject_text_area_end - _kobject_text_area_start;\n#ifndef LINKER_ZEPHYR_FINAL\n#ifdef CONFIG_DYNAMIC_OBJECTS\n\tPROVIDE(z_object_gperf_find = .);\n\tPROVIDE(z_object_gperf_wordlist_foreach = .);\n#else\n\tPROVIDE(z_object_find = .);\n\tPROVIDE(z_object_wordlist_foreach = .);\n#endif\n#endif\n\n\t\/* In a valid build the MAX function will always evaluate to the\n\tsecond argument below, but to give the user a good error message\n\twhen the area overflows we need to temporarily corrupt the\n\tlocation counter, and then detect the overflow with an assertion\n\tlater on. *\/\n\n\t. = MAX(., _kobject_text_area_start + CONFIG_KOBJECT_TEXT_AREA);\n\n\tASSERT(\n\t\tCONFIG_KOBJECT_TEXT_AREA >= _kobject_text_area_used,\n\"Reserved space for kobject text area is too small. \\\nPlease change CONFIG_KOBJECT_TEXT_AREA to a larger number.\"\n\t\t);\n#endif \/* CONFIG_USERSPACE *\/\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#ifdef CONFIG_USERSPACE\n\t\/* We need to reserve room for the gperf generated hash functions.\n\t * Fortunately, unlike the data tables, the size of the code is\n\t * reasonably predictable.\n\t *\n\t * The linker will error out complaining that the location pointer\n\t * is moving backwards if the reserved room isn't large enough.\n\t *\/\n\t_kobject_text_area_start = .;\n\t*(\".kobject_data.text*\")\n\t_kobject_text_area_end = .;\n\t_kobject_text_area_used = _kobject_text_area_end - _kobject_text_area_start;\n#ifndef LINKER_ZEPHYR_FINAL\n#ifdef CONFIG_DYNAMIC_OBJECTS\n\tPROVIDE(z_object_gperf_find = .);\n\tPROVIDE(z_object_gperf_wordlist_foreach = .);\n#else\n\tPROVIDE(z_object_find = .);\n\tPROVIDE(z_object_wordlist_foreach = .);\n#endif\n#endif\n\n\t\/* In a valid build the MAX function will always evaluate to the\n\tsecond argument below, but to give the user a good error message\n\twhen the area overflows we need to temporarily corrupt the\n\tlocation counter, and then detect the overflow with an assertion\n\tlater on. *\/\n\n\t. = MAX(., _kobject_text_area_start + CONFIG_KOBJECT_TEXT_AREA);\n\n\tASSERT(\n\t\tCONFIG_KOBJECT_TEXT_AREA >= _kobject_text_area_used,\n\"The configuration system has incorrectly set \\\n'CONFIG_KOBJECT_TEXT_AREA' to \\\nCONFIG_KOBJECT_TEXT_AREA, which is not big enough. You must \\\nthrough Kconfig either disable 'CONFIG_USERSPACE', or set \\\n'CONFIG_KOBJECT_TEXT_AREA' to a value larger than \\\nCONFIG_KOBJECT_TEXT_AREA.\"\n\t\t);\n#endif \/* CONFIG_USERSPACE *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5e050b077cb35aa6d5a787b618b10c9e856bb371","subject":"Updated linker.ld","message":"Updated linker.ld","repos":"beyondsociety\/ibox,beyondsociety\/ibox","old_file":"firmware\/pc-bios\/linker.ld","new_file":"firmware\/pc-bios\/linker.ld","new_contents":"OUTPUT_FORMAT(elf32-i386) \nOUTPUT_ARCH(i386) \nENTRY(start)\n\nPhysical_address = 1M;\n\nSECTIONS\n{\n\t\/* Load kernel at 1MB *\/\n\t. = Physical_address;\n\n\t\/* Multiboot Header *\/\n\t.multiboot :\n\t{\n\t\t*(.multiboot)\n\t}\n\t\t\n\t\/* Text section *\/\n\t.text :     \n\t{    \n\t\t*(.text)\n\t}\n         \n\t\/* Read-only data *\/\n\t.rodata :    \n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data :  \n\t{ \n\t\t*(.data)\n\t}\n\t\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss : \n\t{\t\t \n\t\t*(COMMON)\n\t\t*(.bss)\n\t}\n\t\n\t.note.gnu.build-id :\n\t{\n\t\t*(.note.gnu.build-id)\n\t}\n}\n\n","old_contents":"OUTPUT_FORMAT(elf32-i386) \nOUTPUT_ARCH(i386) \nENTRY(start)\n\nSECTIONS\n{\n\t\/* Load kernel at 1MB *\/\n\t. = 1M;\n\n\t\/* Multiboot Header *\/\n\t.multiboot :\n\t{\n\t\t*(.multiboot)\n\t}\n\t\t\n\t\/* Text section *\/\n\t.text :     \n\t{    \n\t\t*(.text)\n\t}\n         \n\t\/* Read-only data *\/\n\t.rodata :    \n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data :  \n\t{ \n\t\t*(.data)\n\t}\n\t\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss : \n\t{\t\t \n\t\t*(COMMON)\n\t\t*(.bss)\n\t}\n\t\n\t.note.gnu.build-id :\n\t{\n\t\t*(.note.gnu.build-id)\n\t}\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"cc159a7a4936a7f4664ca94c8f23dba8b215f07e","subject":"Try to fix broken build on some templates","message":"Try to fix broken build on some templates","repos":"mike2390\/embox,gzoom13\/embox,Kefir0192\/embox,Kefir0192\/embox,vrxfile\/embox-trik,abusalimov\/embox,gzoom13\/embox,abusalimov\/embox,gzoom13\/embox,embox\/embox,Kakadu\/embox,vrxfile\/embox-trik,abusalimov\/embox,Kefir0192\/embox,vrxfile\/embox-trik,gzoom13\/embox,vrxfile\/embox-trik,vrxfile\/embox-trik,mike2390\/embox,embox\/embox,Kakadu\/embox,vrxfile\/embox-trik,gzoom13\/embox,Kefir0192\/embox,mike2390\/embox,Kefir0192\/embox,gzoom13\/embox,gzoom13\/embox,Kakadu\/embox,Kakadu\/embox,Kefir0192\/embox,embox\/embox,mike2390\/embox,embox\/embox,embox\/embox,mike2390\/embox,vrxfile\/embox-trik,Kakadu\/embox,abusalimov\/embox,Kakadu\/embox,Kakadu\/embox,mike2390\/embox,embox\/embox,abusalimov\/embox,Kefir0192\/embox,mike2390\/embox,abusalimov\/embox","old_file":"src\/kernel\/nosys.lds","new_file":"src\/kernel\/nosys.lds","new_contents":"\nPROVIDE(diag_init = nosys);\nPROVIDE(diag_getc = nosys);\nPROVIDE(diag_putc = nosys);\n\nPROVIDE(irq_init     = nosys);\nPROVIDE(irq_attach   = nosys);\nPROVIDE(irq_detach   = nosys);\nPROVIDE(irq_dispatch = nosys);\n\nPROVIDE(softirq_init     = nosys);\nPROVIDE(softirq_install  = nosys);\nPROVIDE(softirq_raise    = nosys);\nPROVIDE(softirq_dispatch = nosys);\n\nPROVIDE(sched_lock = nosys);\nPROVIDE(sched_unlock = nosys);\n\nPROVIDE(printk = nosys);\n\nPROVIDE(timer_init = nosys);\nPROVIDE(set_timer = nosys);\nPROVIDE(close_timer = nosys);\nPROVIDE(timers_off = nosys);\nPROVIDE(irq_func_tmr_1mS = nosys);\nPROVIDE(usleep = nosys);\n\n\/* XXX remove from here. -- Eldar *\/\nPROVIDE(uart_init = nosys);\n","old_contents":"\nPROVIDE(diag_init = nosys);\nPROVIDE(diag_getc = nosys);\nPROVIDE(diag_putc = nosys);\n\nPROVIDE(irq_init     = nosys);\nPROVIDE(irq_attach   = nosys);\nPROVIDE(irq_detach   = nosys);\nPROVIDE(irq_dispatch = nosys);\n\nPROVIDE(softirq_init     = nosys);\nPROVIDE(softirq_install  = nosys);\nPROVIDE(softirq_raise    = nosys);\nPROVIDE(softirq_dispatch = nosys);\n\nPROVIDE(scheduler_lock = nosys);\nPROVIDE(scheduler_unlock = nosys);\n\nPROVIDE(printk = nosys);\n\nPROVIDE(timer_init = nosys);\nPROVIDE(set_timer = nosys);\nPROVIDE(close_timer = nosys);\nPROVIDE(timers_off = nosys);\nPROVIDE(irq_func_tmr_1mS = nosys);\nPROVIDE(usleep = nosys);\n\n\/* XXX remove from here. -- Eldar *\/\nPROVIDE(uart_init = nosys);\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"6566e3f6a87ea0080d93a59f750b6616276841a0","subject":"esp8266\/esp8266.ld: Move help.o to iROM.","message":"esp8266\/esp8266.ld: Move help.o to iROM.\n","repos":"MrSurly\/micropython-esp32,MrSurly\/micropython-esp32,pramasoul\/micropython,pfalcon\/micropython,alex-robbins\/micropython,micropython\/micropython-esp32,bvernoux\/micropython,Peetz0r\/micropython-esp32,MrSurly\/micropython,adafruit\/circuitpython,Peetz0r\/micropython-esp32,SHA2017-badge\/micropython-esp32,adafruit\/circuitpython,toolmacher\/micropython,tuc-osg\/micropython,adafruit\/circuitpython,PappaPeppar\/micropython,tobbad\/micropython,Timmenem\/micropython,TDAbboud\/micropython,torwag\/micropython,pramasoul\/micropython,bvernoux\/micropython,cwyark\/micropython,pfalcon\/micropython,lowRISC\/micropython,MrSurly\/micropython-esp32,HenrikSolver\/micropython,pozetroninc\/micropython,MrSurly\/micropython,tralamazza\/micropython,HenrikSolver\/micropython,HenrikSolver\/micropython,Peetz0r\/micropython-esp32,selste\/micropython,kerneltask\/micropython,matthewelse\/micropython,infinnovation\/micropython,tobbad\/micropython,dmazzella\/micropython,trezor\/micropython,MrSurly\/micropython,selste\/micropython,MrSurly\/micropython,infinnovation\/micropython,trezor\/micropython,TDAbboud\/micropython,hosaka\/micropython,toolmacher\/micropython,micropython\/micropython-esp32,mhoffma\/micropython,lowRISC\/micropython,jmarcelino\/pycom-micropython,oopy\/micropython,alex-robbins\/micropython,pozetroninc\/micropython,micropython\/micropython-esp32,matthewelse\/micropython,AriZuu\/micropython,tralamazza\/micropython,adafruit\/micropython,jmarcelino\/pycom-micropython,hiway\/micropython,torwag\/micropython,blazewicz\/micropython,cwyark\/micropython,dxxb\/micropython,Timmenem\/micropython,toolmacher\/micropython,lowRISC\/micropython,swegener\/micropython,hosaka\/micropython,micropython\/micropython-esp32,alex-robbins\/micropython,SHA2017-badge\/micropython-esp32,chrisdearman\/micropython,tobbad\/micropython,chrisdearman\/micropython,MrSurly\/micropython-esp32,ryannathans\/micropython,chrisdearman\/micropython,bvernoux\/micropython,cwyark\/micropython,TDAbboud\/micropython,SHA2017-badge\/micropython-esp32,hiway\/micropython,blazewicz\/micropython,oopy\/micropython,kerneltask\/micropython,HenrikSolver\/micropython,Timmenem\/micropython,matthewelse\/micropython,pozetroninc\/micropython,cwyark\/micropython,henriknelson\/micropython,pramasoul\/micropython,TDAbboud\/micropython,pramasoul\/micropython,puuu\/micropython,ryannathans\/micropython,matthewelse\/micropython,swegener\/micropython,pfalcon\/micropython,tralamazza\/micropython,trezor\/micropython,trezor\/micropython,PappaPeppar\/micropython,henriknelson\/micropython,alex-robbins\/micropython,oopy\/micropython,pozetroninc\/micropython,tobbad\/micropython,oopy\/micropython,mhoffma\/micropython,AriZuu\/micropython,trezor\/micropython,tobbad\/micropython,hosaka\/micropython,alex-march\/micropython,hosaka\/micropython,torwag\/micropython,toolmacher\/micropython,kerneltask\/micropython,dmazzella\/micropython,blazewicz\/micropython,adafruit\/micropython,jmarcelino\/pycom-micropython,infinnovation\/micropython,deshipu\/micropython,AriZuu\/micropython,Peetz0r\/micropython-esp32,toolmacher\/micropython,kerneltask\/micropython,pfalcon\/micropython,deshipu\/micropython,alex-robbins\/micropython,PappaPeppar\/micropython,selste\/micropython,TDAbboud\/micropython,micropython\/micropython-esp32,oopy\/micropython,pozetroninc\/micropython,lowRISC\/micropython,matthewelse\/micropython,infinnovation\/micropython,adafruit\/micropython,mhoffma\/micropython,dmazzella\/micropython,alex-march\/micropython,bvernoux\/micropython,henriknelson\/micropython,dxxb\/micropython,hosaka\/micropython,tuc-osg\/micropython,swegener\/micropython,tralamazza\/micropython,blazewicz\/micropython,ryannathans\/micropython,tuc-osg\/micropython,matthewelse\/micropython,henriknelson\/micropython,puuu\/micropython,alex-march\/micropython,SHA2017-badge\/micropython-esp32,tuc-osg\/micropython,hiway\/micropython,deshipu\/micropython,puuu\/micropython,deshipu\/micropython,mhoffma\/micropython,adafruit\/micropython,Timmenem\/micropython,bvernoux\/micropython,puuu\/micropython,blazewicz\/micropython,hiway\/micropython,mhoffma\/micropython,kerneltask\/micropython,adafruit\/circuitpython,SHA2017-badge\/micropython-esp32,dxxb\/micropython,adafruit\/micropython,pfalcon\/micropython,adafruit\/circuitpython,pramasoul\/micropython,alex-march\/micropython,chrisdearman\/micropython,dxxb\/micropython,AriZuu\/micropython,ryannathans\/micropython,PappaPeppar\/micropython,torwag\/micropython,MrSurly\/micropython-esp32,hiway\/micropython,alex-march\/micropython,puuu\/micropython,PappaPeppar\/micropython,lowRISC\/micropython,swegener\/micropython,Timmenem\/micropython,chrisdearman\/micropython,torwag\/micropython,AriZuu\/micropython,HenrikSolver\/micropython,cwyark\/micropython,MrSurly\/micropython,selste\/micropython,jmarcelino\/pycom-micropython,ryannathans\/micropython,Peetz0r\/micropython-esp32,deshipu\/micropython,dxxb\/micropython,selste\/micropython,swegener\/micropython,adafruit\/circuitpython,infinnovation\/micropython,dmazzella\/micropython,tuc-osg\/micropython,henriknelson\/micropython,jmarcelino\/pycom-micropython","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40209000, len = 0x87000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *help.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybuart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachinewdt.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modpybhspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40209000, len = 0x87000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(firmware_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n\n        *py\/argcheck.o*(.literal* .text*)\n        *py\/asm*.o*(.literal* .text*)\n        *py\/bc.o*(.literal* .text*)\n        *py\/binary.o*(.literal* .text*)\n        *py\/builtin*.o*(.literal* .text*)\n        *py\/compile.o*(.literal* .text*)\n        *py\/emit*.o*(.literal* .text*)\n        *py\/formatfloat.o*(.literal* .text*)\n        *py\/frozenmod.o*(.literal* .text*)\n        *py\/gc.o*(.literal* .text*)\n        *py\/lexer*.o*(.literal* .text*)\n        *py\/malloc*.o*(.literal* .text*)\n        *py\/map*.o*(.literal* .text*)\n        *py\/mod*.o*(.literal* .text*)\n        *py\/mpprint.o*(.literal* .text*)\n        *py\/mpstate.o*(.literal* .text*)\n        *py\/mpz.o*(.literal* .text*)\n        *py\/native*.o*(.literal* .text*)\n        *py\/nlr*.o*(.literal* .text*)\n        *py\/obj*.o*(.literal* .text*)\n        *py\/opmethods.o*(.literal* .text*)\n        *py\/parse*.o*(.literal* .text*)\n        *py\/qstr.o*(.literal* .text*)\n        *py\/repl.o*(.literal* .text*)\n        *py\/runtime.o*(.literal* .text*)\n        *py\/scope.o*(.literal* .text*)\n        *py\/sequence.o*(.literal* .text*)\n        *py\/showbc.o*(.literal* .text*)\n        *py\/smallint.o*(.literal* .text*)\n        *py\/stackctrl.o*(.literal* .text*)\n        *py\/stream.o*(.literal* .text*)\n        *py\/unicode.o*(.literal* .text*)\n        *py\/vm.o*(.literal* .text*)\n        *py\/vstr.o*(.literal* .text*)\n        *py\/warning.o*(.literal* .text*)\n\n        *extmod\/*.o*(.literal* .text*)\n\n        *lib\/fatfs\/*.o*(.literal*, .text*)\n        *\/libaxtls.a:(.literal*, .text*)\n        *lib\/berkeley-db-1.xx\/*.o(.literal*, .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *lib\/mp-readline\/*.o(.literal*, .text*)\n        *lib\/netutils\/*.o*(.literal*, .text*)\n        *lib\/timeutils\/*.o*(.literal*, .text*)\n        *lib\/utils\/*.o*(.literal*, .text*)\n\n        *stmhal\/pybstdio.o(.literal*, .text*)\n\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *lexerstr32.o(.literal* .text*)\n        *utils.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybpwm.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modpybadc.o(.literal*, .text*)\n        *modpybuart.o(.literal*, .text*)\n        *modpybi2c.o(.literal*, .text*)\n        *modmachinewdt.o(.literal*, .text*)\n        *modpybspi.o(.literal*, .text*)\n        *modpybhspi.o(.literal*, .text*)\n        *hspi.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n        *modlwip.o(.literal* .text*)\n        *modsocket.o(.literal* .text*)\n        *modonewire.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n        *\/frozen.o(.rodata.mp_frozen_sizes) \/* frozen modules *\/\n        *\/frozen.o(.rodata.mp_frozen_content) \/* frozen modules *\/\n\n        \/* for -mforce-l32 *\/\n        build\/*.o(.rodata*)\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"79be658988e497e560486a990ff8a773e8e0d779","subject":"[kernel] Fix a rather embarassing typo in link.ld causing .rodata to load in the same place as .data","message":"[kernel] Fix a rather embarassing typo in link.ld causing .rodata to load in the same place as .data\n","repos":"devyn\/kit,devyn\/kit,devyn\/kit,devyn\/kit","old_file":"kernel\/scripts\/link.ld","new_file":"kernel\/scripts\/link.ld","new_contents":"\/* Based on OSDev Bare Bones tutorial\n   http:\/\/wiki.osdev.org\/Bare_Bones *\/\n\n\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_bootstrap)\n\nKERNEL_LMA = 0x100000;           \/* Physical address *\/\nKERNEL_VMA = 0xffff800000000000; \/* Virtual (higher half) address *\/\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n  \/* 32-bit and 64-bit bootstrap routines at 1 MB *\/\n  .                = KERNEL_LMA;\n  _bootstrap_begin = .;\n\n  .bootstrap :\n  {\n    build\/kernel\/boot32.o (.multiboot)\n    build\/kernel\/boot32.o (.text)\n    . = ALIGN(4K);\n  }\n\n  .bootstrap64 :\n  {\n    build\/kernel\/boot64.o (.text)\n    . = ALIGN(4K);\n  }\n\n  .bootstrap_data :\n  {\n    build\/kernel\/boot32.o (.bootstrap_gdt64)\n    build\/kernel\/boot32.o (.bootstrap_stack)\n    build\/kernel\/boot32.o (.rodata)\n    build\/kernel\/boot32.o (.data)\n    . = ALIGN(4K);\n  }\n\n  \/* 64-bit kernel in the higher half of the 48-bit addressing scheme *\/\n  .             += KERNEL_VMA;\n  _kernel_begin  = .;\n\n  \/* Kernel executable code. *\/\n  .text : AT(ADDR(.text) - KERNEL_VMA)\n  {\n    *(EXCLUDE_FILE(build\/kernel\/boot*.o) .text)\n    . = ALIGN(4K);\n  }\n\n  \/* Read-only data. *\/\n  .rodata : AT(ADDR(.rodata) - KERNEL_VMA)\n  {\n    *(EXCLUDE_FILE(build\/kernel\/boot*.o) .rodata*)\n    . = ALIGN(4K);\n  }\n\n  \/* Read-write data (initialized) *\/\n  .data : AT(ADDR(.data) - KERNEL_VMA)\n  {\n    *(EXCLUDE_FILE(build\/kernel\/boot*.o) .data)\n    . = ALIGN(4K);\n  }\n\n  \/* Read-write data (uninitialized) *\/\n  .bss : AT(ADDR(.bss) - KERNEL_VMA)\n  {\n    *(EXCLUDE_FILE(build\/kernel\/boot*.o) COMMON)\n    *(EXCLUDE_FILE(build\/kernel\/boot*.o) .bss)\n    . = ALIGN(4K);\n  }\n\n  \/* The compiler may produce other sections, by default it will put them in\n     a segment with the same name. Simply add stuff here as needed. *\/\n\n  _kernel_end = .;\n\n  \/DISCARD\/ :\n  {\n    *(.comment)\n    *(.eh_frame)\n  }\n}\n","old_contents":"\/* Based on OSDev Bare Bones tutorial\n   http:\/\/wiki.osdev.org\/Bare_Bones *\/\n\n\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_bootstrap)\n\nKERNEL_LMA = 0x100000;           \/* Physical address *\/\nKERNEL_VMA = 0xffff800000000000; \/* Virtual (higher half) address *\/\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n  \/* 32-bit and 64-bit bootstrap routines at 1 MB *\/\n  .                = KERNEL_LMA;\n  _bootstrap_begin = .;\n\n  .bootstrap :\n  {\n    build\/kernel\/boot32.o (.multiboot)\n    build\/kernel\/boot32.o (.text)\n    . = ALIGN(4K);\n  }\n\n  .bootstrap64 :\n  {\n    build\/kernel\/boot64.o (.text)\n    . = ALIGN(4K);\n  }\n\n  .bootstrap_data :\n  {\n    build\/kernel\/boot32.o (.bootstrap_gdt64)\n    build\/kernel\/boot32.o (.bootstrap_stack)\n    build\/kernel\/boot32.o (.rodata)\n    build\/kernel\/boot32.o (.data)\n    . = ALIGN(4K);\n  }\n\n  \/* 64-bit kernel in the higher half of the 48-bit addressing scheme *\/\n  .             += KERNEL_VMA;\n  _kernel_begin  = .;\n\n  \/* Kernel executable code. *\/\n  .text : AT(ADDR(.text) - KERNEL_VMA)\n  {\n    *(EXCLUDE_FILE(build\/kernel\/boot*.o) .text)\n    . = ALIGN(4K);\n  }\n\n  \/* Read-only data. *\/\n  .rodata : AT(ADDR(.rodata) - KERNEL_VMA)\n  {\n    *(EXCLUDE_FILE(build\/kernel\/boot*.o) .rodata*)\n    . = ALIGN(4K);\n  }\n\n  \/* Read-write data (initialized) *\/\n  .data : AT(ADDR(.rodata) - KERNEL_VMA)\n  {\n    *(EXCLUDE_FILE(build\/kernel\/boot*.o) .data)\n    . = ALIGN(4K);\n  }\n\n  \/* Read-write data (uninitialized) *\/\n  .bss : AT(ADDR(.bss) - KERNEL_VMA)\n  {\n    *(EXCLUDE_FILE(build\/kernel\/boot*.o) COMMON)\n    *(EXCLUDE_FILE(build\/kernel\/boot*.o) .bss)\n    . = ALIGN(4K);\n  }\n\n  \/* The compiler may produce other sections, by default it will put them in\n     a segment with the same name. Simply add stuff here as needed. *\/\n\n  _kernel_end = .;\n\n  \/DISCARD\/ :\n  {\n    *(.comment)\n    *(.eh_frame)\n  }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"32c924b5cde5d9de490735d46f0659db89691199","subject":"esp32s3: Reserve RTC memory in bootloader in the app linker script","message":"esp32s3: Reserve RTC memory in bootloader in the app linker script\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp32s3\/ld\/esp32s3.ld","new_file":"components\/esp32s3\/ld\/esp32s3.ld","new_contents":"\/**\n *                    ESP32-S3 Linker Script Memory Layout\n * This file describes the memory layout (memory blocks) by virtual memory addresses.\n * This linker script is passed through the C preprocessor to include configuration options.\n * Please use preprocessor features sparingly!\n * Restrict to simple macros with numeric values, and\/or #if\/#endif blocks.\n *\/\n\n#include \"sdkconfig.h\"\n\n#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC\n#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)\n#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)\n#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)\n#else\n#define ESP_BOOTLOADER_RESERVE_RTC 0\n#endif\n\n#define SRAM_IRAM_START     0x40370000\n#define SRAM_DRAM_START     0x3FC80000\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403BA000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)\n\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\nASSERT((CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), \"Fixed static ram data does not fit.\")\n#define DRAM0_0_SEG_LEN CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE\n#else\n#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE\n#endif \/\/ CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\nMEMORY\n{\n  \/**\n   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n   *  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n   *  are connected to the data port of the CPU and eg allow byte-wise access.\n   *\/\n\n  \/* IRAM for PRO CPU. *\/\n  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped instruction data *\/\n  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x8000000-0x20\n\n  \/**\n   * (0x20 offset above is a convenience for the app binary image generation.\n   * Flash cache has 64KB pages. The .bin file which is flashed to the chip\n   * has a 0x18 byte file header, and each segment has a 0x08 byte segment\n   * header. Setting this offset makes it simple to meet the flash cache MMU's\n   * constraint that (paddr % 64KB == vaddr % 64KB).)\n   *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.\n   *\/\n  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x8000000-0x20\n\n  \/* (See iram0_2_seg for meaning of 0x20 offset in the above.) *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x600fe000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC\n\n  \/**\n   * RTC fast memory (same block as above), viewed from data bus\n   *\/\n  rtc_data_seg(RW) :                 org = 0x600fe000, len = 0x2000\n\n  \/**\n   * RTC slow memory (data accessible). Persists over deep sleep.\n   * Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n   *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM\n}\n\n#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\/* static data ends at defined address *\/\n_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;\n#else\n_static_data_end = _bss_end;\n#endif \/\/ CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000;\n\n_data_seg_org = ORIGIN(rtc_data_seg);\n\n#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM\nREGION_ALIAS(\"rtc_data_location\", rtc_slow_seg );\n#else\nREGION_ALIAS(\"rtc_data_location\", rtc_data_seg );\n#endif \/\/ CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\nREGION_ALIAS(\"default_code_seg\", iram0_2_seg);\n#else\nREGION_ALIAS(\"default_code_seg\", iram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\nREGION_ALIAS(\"default_rodata_seg\", drom0_0_seg);\n#else\nREGION_ALIAS(\"default_rodata_seg\", dram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n","old_contents":"\/**\n *                    ESP32-S3 Linker Script Memory Layout\n * This file describes the memory layout (memory blocks) by virtual memory addresses.\n * This linker script is passed through the C preprocessor to include configuration options.\n * Please use preprocessor features sparingly!\n * Restrict to simple macros with numeric values, and\/or #if\/#endif blocks.\n *\/\n\n#include \"sdkconfig.h\"\n\n#define SRAM_IRAM_START     0x40370000\n#define SRAM_DRAM_START     0x3FC80000\n#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)\n#define SRAM_DRAM_END       0x403BA000 - I_D_SRAM_OFFSET  \/* 2nd stage bootloader iram_loader_seg start address *\/\n\n#define SRAM_IRAM_ORG       (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)\n#define SRAM_DRAM_ORG       (SRAM_DRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)\n\n#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG\n\n#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\nASSERT((CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), \"Fixed static ram data does not fit.\")\n#define DRAM0_0_SEG_LEN CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE\n#else\n#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE\n#endif \/\/ CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\nMEMORY\n{\n  \/**\n   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n   *  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n   *  are connected to the data port of the CPU and eg allow byte-wise access.\n   *\/\n\n  \/* IRAM for PRO CPU. *\/\n  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped instruction data *\/\n  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x8000000-0x20\n\n  \/**\n   * (0x20 offset above is a convenience for the app binary image generation.\n   * Flash cache has 64KB pages. The .bin file which is flashed to the chip\n   * has a 0x18 byte file header, and each segment has a 0x08 byte segment\n   * header. Setting this offset makes it simple to meet the flash cache MMU's\n   * constraint that (paddr % 64KB == vaddr % 64KB).)\n   *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.\n   *\/\n  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x8000000-0x20\n\n  \/* (See iram0_2_seg for meaning of 0x20 offset in the above.) *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/**\n   * RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x600fe000, len = 0x2000\n\n  \/**\n   * RTC fast memory (same block as above), viewed from data bus\n   *\/\n  rtc_data_seg(RW) :                 org = 0x600fe000, len = 0x2000\n\n  \/**\n   * RTC slow memory (data accessible). Persists over deep sleep.\n   * Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n   *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM\n}\n\n#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\/* static data ends at defined address *\/\n_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;\n#else\n_static_data_end = _bss_end;\n#endif \/\/ CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000;\n\n_data_seg_org = ORIGIN(rtc_data_seg);\n\n#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM\nREGION_ALIAS(\"rtc_data_location\", rtc_slow_seg );\n#else\nREGION_ALIAS(\"rtc_data_location\", rtc_data_seg );\n#endif \/\/ CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\nREGION_ALIAS(\"default_code_seg\", iram0_2_seg);\n#else\nREGION_ALIAS(\"default_code_seg\", iram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS\nREGION_ALIAS(\"default_rodata_seg\", drom0_0_seg);\n#else\nREGION_ALIAS(\"default_rodata_seg\", dram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d39aafb5610d22c760449f94b202c8d65c4dddd9","subject":"[build] Add PHDRS to kernel linker script","message":"[build] Add PHDRS to kernel linker script\n","repos":"vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs,vvaltchev\/experimentOs","old_file":"kernel\/arch\/i386\/linker_script.ld","new_file":"kernel\/arch\/i386\/linker_script.ld","new_contents":"\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib32\");\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib\");\n\nkernel_base_va     = 0xC0000000;\nkernel_paddr       = 0x00100000;\nkernel_text_paddr  = kernel_paddr + 0x1000;\n\nPHDRS\n{\n  ro_segment PT_LOAD FILEHDR PHDRS;\n  rw_segment PT_LOAD;\n}\n\nSECTIONS\n{\n  . = SEGMENT_START(\"text-segment\", kernel_base_va + kernel_text_paddr);\n\n  .text : AT(kernel_text_paddr)\n  {\n    text = .;\n    *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    *(.text.exit .text.exit.*)\n    *(.text.startup .text.startup.*)\n    *(.text.hot .text.hot.*)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    . = ALIGN(4);\n  } : ro_segment\n\n   .rodata : AT(kernel_text_paddr + (rodata - text))\n   {\n      rodata = .;\n      *(.rodata .rodata.* .gnu.linkonce.r.*)\n      . = ALIGN(4096);\n   } : ro_segment\n\n  .data : AT(kernel_text_paddr + (data - text))\n  {\n    data = .;\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN(4);\n  } : rw_segment\n\n  .bss : AT(kernel_text_paddr + (bss - text))\n  {\n    bss = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n  } : rw_segment\n\n  . = ALIGN(4);\n  _end = .;\n\n  \/DISCARD\/ : { *(.eh_frame*) }\n  \/DISCARD\/ : { *(.comment) }\n}\n\n\n","old_contents":"\nOUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(_start)\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib32\");\nSEARCH_DIR(\"=\/tmp\/x86-i686--glibc--stable\/usr\/i686-buildroot-linux-gnu\/lib\");\n\nkernel_base_va = 0xC0000000;\nkernel_paddr   = 0x00100000;\n\nSECTIONS\n{\n  . = SEGMENT_START(\"text-segment\", kernel_base_va + kernel_paddr);\n\n  .text : AT(kernel_paddr)\n  {\n    text = .;\n    *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    *(.text.exit .text.exit.*)\n    *(.text.startup .text.startup.*)\n    *(.text.hot .text.hot.*)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    . = ALIGN(4);\n  }\n\n   .rodata : AT(kernel_paddr + (rodata - text))\n   {\n      rodata = .;\n      *(.rodata .rodata.* .gnu.linkonce.r.*)\n      . = ALIGN(4096);\n   }\n\n  .data : AT(kernel_paddr + (data - text))\n  {\n    data = .;\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN(4096);\n  }\n\n  .bss : AT(kernel_paddr + (bss - text))\n  {\n    bss = .;\n    *(.bss .bss.* .gnu.linkonce.b.*)\n  }\n\n  . = ALIGN(4);\n  _end = .;\n\n  \/DISCARD\/ : { *(.eh_frame*) }\n  \/DISCARD\/ : { *(.comment) }\n}\n\n\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"2c3bfae3e7ab3491aacffafc7e2dd2cdc6af4e0f","subject":"[test, sw\/silicon_creator] Emit .rodata even if it's empty","message":"[test, sw\/silicon_creator] Emit .rodata even if it's empty\n\nextract_sw_logs_db requires .rodata to exist. Since we build for sim_dv\nunconditionally and pass .rodata as an argument to that script, build\nfails if a flash binary does not have the .rodata section. This commit\nadds a workaround for this issue so that .rodata is emitted even if it's\nempty. See #14636.\n\nSigned-off-by: Alphan Ulusoy <23b245cc5a07aacf75a9db847b24c67dee1707bf@google.com>\n","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan","old_file":"sw\/device\/silicon_creator\/rom_ext\/rom_ext_common.ld","new_file":"sw\/device\/silicon_creator\/rom_ext\/rom_ext_common.ld","new_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * NOTE:\n * This is an incomplete common portion of ROM_EXT linker file, and should not\n * be used directly. Instead it should be included by a top level ROM_EXT slot\n * linker file.\n *\/\n\nOUTPUT_ARCH(riscv)\n\n\/**\n * Indicate that there are no dynamic libraries, whatsoever.\n *\/\n__DYNAMIC = 0;\n\n\/* Reserving space at the top of the RAM for the stack. *\/\n_stack_size = 0x2000;\n_stack_end = ORIGIN(ram_main) + LENGTH(ram_main);\n_stack_start = _stack_end - _stack_size;\n\n\/**\n * Symbols to be used in the setup of the address translation for ROM_EXT.\n *\/\n_owner_virtual_start_address = ORIGIN(owner_virtual);\n_owner_virtual_size = LENGTH(owner_virtual);\n\n\/**\n * Marking the entry point correctly for the ELF file. The signer tool will\n * transfer this value to the `entry_point` field of the manifest, which will\n * then be used by `rom_boot` to handover execution to ROM_EXT.\n *\/\nENTRY(_rom_ext_start_boot)\n\n\/* DV Log offset (has to be different to other boot stages). *\/\n_dv_log_offset = 0x10000;\n\n\/*\n * The start of the .text section relative to the beginning of the associated\n * slot for use in the manifest.\n *\/\n_manifest_code_start = _text_start - _rom_ext_start_address;\n\/*\n * The end of the .text section relative to the beginning of the associated slot\n * for use in the manifest.\n *\/\n_manifest_code_end = _text_end - _rom_ext_start_address;\n\/*\n * The location of the entry point relative to the beginning of the associated\n * slot for use in the manifest.\n *\/\n_manifest_entry_point = _rom_ext_start_boot - _rom_ext_start_address;\n\n\n\/**\n * NOTE: We have to align each section to word boundaries as our current\n * s19->slm conversion scripts are not able to handle non-word aligned sections.\n *\/\nSECTIONS {\n  .manifest _rom_ext_start_address : {\n    KEEP(*(.manifest))\n    . = ALIGN(256);\n  } > rom_ext_flash\n\n  \/**\n   * Ibex interrupt vector.\n   *\n   * This has to be set up at a 256-byte offset, so that we can use it with\n   * Ibex.\n   *\/\n  .vectors : ALIGN(256) {\n    _text_start = .;\n    KEEP(*(.vectors))\n  } > rom_ext_flash\n\n  \/**\n   * C runtime (CRT) section, containing program initialization code.\n   *\/\n  .crt : ALIGN(4) {\n    KEEP(*(.crt))\n  } > rom_ext_flash\n\n  \/**\n   * Standard text section, containing program code.\n   *\/\n  .text : ALIGN(4) {\n    *(.text)\n    *(.text.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n  } > rom_ext_flash\n\n  \/**\n   * Shutdown text section, containing shutdown function(s).\n   *\n   * This must be the last executable section in the ROM_EXT flash image.\n   *\/\n  .shutdown : ALIGN(4) {\n    *(.shutdown)\n    *(.shutdown.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n    _text_end = .;\n  } > rom_ext_flash\n\n  \/**\n   * Read-only data section, containing all large compile-time constants, like\n   * strings.\n   *\/\n  .rodata : ALIGN(4) {\n    \/* Small read-only data comes before regular read-only data for the same\n     * reasons as in the data section *\/\n    *(.srodata)\n    *(.srodata.*)\n    *(.rodata)\n    *(.rodata.*)\n    \/* TODO(#14636): extract_sw_logs_db requires .rodata section. *\/\n    . = ALIGN(4);\n    _rodata_end = .;\n  } > rom_ext_flash\n\n  \/**\n   * Critical static data that is accessible by both the ROM and the ROM\n   * extension.\n   *\/\n  INCLUDE sw\/device\/silicon_creator\/lib\/base\/static_critical.ld\n\n  \/**\n   * Mutable data section, at the bottom of ram_main. This will be initialized\n   * from flash at runtime by the CRT.\n   *\n   * Load this by copying the bytes from [_data_init_start, _data_init_end] into\n   * the range [_data_start, _data_end].\n   *\/\n  .data : ALIGN(4) {\n    _data_start = .;\n    _data_init_start = LOADADDR(.data);\n\n    \/* This will get loaded into `gp`, and the linker will use that register for\n     * accessing data within [-2048,2047] of `__global_pointer$`.\n     *\n     * This is much cheaper (for small data) than materializing the\n     * address and loading from that (which will take one extra instruction).\n     *\/\n    __global_pointer$ = . + 2048;\n\n    \/* Small data should come before larger data. This helps to ensure small\n     * globals are within 2048 bytes of the value of `gp`, making their accesses\n     * hopefully only take one instruction. *\/\n    *(.sdata)\n    *(.sdata.*)\n\n    \/* Other data will likely need multiple instructions to load, so we're less\n     * concerned about address materialisation taking more than one instruction.\n     *\/\n    *(.data)\n    *(.data.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n    _data_end = .;\n    _data_init_end = LOADADDR(.data) + SIZEOF(.data);\n\n    \/* This puts it in ram_main at runtime (for the VMA), but puts the section\n     * into flash for load time (for the LMA). This is why `_data_init_*` uses\n     * `LOADADDR`.\n     *\n     * Using `AT>` means we don't have to keep track of the next free part of\n     * flash, as we do in our other linker scripts. *\/\n  } > ram_main AT> rom_ext_flash\n\n  \/**\n   * Standard BSS section. This will be zeroed at runtime by the CRT.\n   *\/\n  .bss : ALIGN(4) {\n    _bss_start = .;\n\n    \/* Small BSS comes before regular BSS for the same reasons as in the data\n     * section *\/\n    *(.sbss)\n    *(.sbss.*)\n    *(.bss)\n    *(.bss.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n    _bss_end = .;\n  } > ram_main\n\n  INCLUDE sw\/device\/info_sections.ld\n}\n","old_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * NOTE:\n * This is an incomplete common portion of ROM_EXT linker file, and should not\n * be used directly. Instead it should be included by a top level ROM_EXT slot\n * linker file.\n *\/\n\nOUTPUT_ARCH(riscv)\n\n\/**\n * Indicate that there are no dynamic libraries, whatsoever.\n *\/\n__DYNAMIC = 0;\n\n\/* Reserving space at the top of the RAM for the stack. *\/\n_stack_size = 0x2000;\n_stack_end = ORIGIN(ram_main) + LENGTH(ram_main);\n_stack_start = _stack_end - _stack_size;\n\n\/**\n * Symbols to be used in the setup of the address translation for ROM_EXT.\n *\/\n_owner_virtual_start_address = ORIGIN(owner_virtual);\n_owner_virtual_size = LENGTH(owner_virtual);\n\n\/**\n * Marking the entry point correctly for the ELF file. The signer tool will\n * transfer this value to the `entry_point` field of the manifest, which will\n * then be used by `rom_boot` to handover execution to ROM_EXT.\n *\/\nENTRY(_rom_ext_start_boot)\n\n\/* DV Log offset (has to be different to other boot stages). *\/\n_dv_log_offset = 0x10000;\n\n\/*\n * The start of the .text section relative to the beginning of the associated\n * slot for use in the manifest.\n *\/\n_manifest_code_start = _text_start - _rom_ext_start_address;\n\/*\n * The end of the .text section relative to the beginning of the associated slot\n * for use in the manifest.\n *\/\n_manifest_code_end = _text_end - _rom_ext_start_address;\n\/*\n * The location of the entry point relative to the beginning of the associated\n * slot for use in the manifest.\n *\/\n_manifest_entry_point = _rom_ext_start_boot - _rom_ext_start_address;\n\n\n\/**\n * NOTE: We have to align each section to word boundaries as our current\n * s19->slm conversion scripts are not able to handle non-word aligned sections.\n *\/\nSECTIONS {\n  .manifest _rom_ext_start_address : {\n    KEEP(*(.manifest))\n    . = ALIGN(256);\n  } > rom_ext_flash\n\n  \/**\n   * Ibex interrupt vector.\n   *\n   * This has to be set up at a 256-byte offset, so that we can use it with\n   * Ibex.\n   *\/\n  .vectors : ALIGN(256) {\n    _text_start = .;\n    KEEP(*(.vectors))\n  } > rom_ext_flash\n\n  \/**\n   * C runtime (CRT) section, containing program initialization code.\n   *\/\n  .crt : ALIGN(4) {\n    KEEP(*(.crt))\n  } > rom_ext_flash\n\n  \/**\n   * Standard text section, containing program code.\n   *\/\n  .text : ALIGN(4) {\n    *(.text)\n    *(.text.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n  } > rom_ext_flash\n\n  \/**\n   * Shutdown text section, containing shutdown function(s).\n   *\n   * This must be the last executable section in the ROM_EXT flash image.\n   *\/\n  .shutdown : ALIGN(4) {\n    *(.shutdown)\n    *(.shutdown.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n    _text_end = .;\n  } > rom_ext_flash\n\n  \/**\n   * Read-only data section, containing all large compile-time constants, like\n   * strings.\n   *\/\n  .rodata : ALIGN(4) {\n    \/* Small read-only data comes before regular read-only data for the same\n     * reasons as in the data section *\/\n    *(.srodata)\n    *(.srodata.*)\n    *(.rodata)\n    *(.rodata.*)\n  } > rom_ext_flash\n\n  \/**\n   * Critical static data that is accessible by both the ROM and the ROM\n   * extension.\n   *\/\n  INCLUDE sw\/device\/silicon_creator\/lib\/base\/static_critical.ld\n\n  \/**\n   * Mutable data section, at the bottom of ram_main. This will be initialized\n   * from flash at runtime by the CRT.\n   *\n   * Load this by copying the bytes from [_data_init_start, _data_init_end] into\n   * the range [_data_start, _data_end].\n   *\/\n  .data : ALIGN(4) {\n    _data_start = .;\n    _data_init_start = LOADADDR(.data);\n\n    \/* This will get loaded into `gp`, and the linker will use that register for\n     * accessing data within [-2048,2047] of `__global_pointer$`.\n     *\n     * This is much cheaper (for small data) than materializing the\n     * address and loading from that (which will take one extra instruction).\n     *\/\n    __global_pointer$ = . + 2048;\n\n    \/* Small data should come before larger data. This helps to ensure small\n     * globals are within 2048 bytes of the value of `gp`, making their accesses\n     * hopefully only take one instruction. *\/\n    *(.sdata)\n    *(.sdata.*)\n\n    \/* Other data will likely need multiple instructions to load, so we're less\n     * concerned about address materialisation taking more than one instruction.\n     *\/\n    *(.data)\n    *(.data.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n    _data_end = .;\n    _data_init_end = LOADADDR(.data) + SIZEOF(.data);\n\n    \/* This puts it in ram_main at runtime (for the VMA), but puts the section\n     * into flash for load time (for the LMA). This is why `_data_init_*` uses\n     * `LOADADDR`.\n     *\n     * Using `AT>` means we don't have to keep track of the next free part of\n     * flash, as we do in our other linker scripts. *\/\n  } > ram_main AT> rom_ext_flash\n\n  \/**\n   * Standard BSS section. This will be zeroed at runtime by the CRT.\n   *\/\n  .bss : ALIGN(4) {\n    _bss_start = .;\n\n    \/* Small BSS comes before regular BSS for the same reasons as in the data\n     * section *\/\n    *(.sbss)\n    *(.sbss.*)\n    *(.bss)\n    *(.bss.*)\n\n    \/* Ensure section end is word-aligned. *\/\n    . = ALIGN(4);\n    _bss_end = .;\n  } > ram_main\n\n  INCLUDE sw\/device\/info_sections.ld\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"32b1eb40f070afa8f5a39c4a66afa2eb769d42c7","subject":"Use full flash in S110 linker script","message":"Use full flash in S110 linker script","repos":"jf87\/nrf51-pure-gcc-setup","old_file":"template\/gcc_nrf51_s110.ld","new_file":"template\/gcc_nrf51_s110.ld","new_contents":"\/* Linker script to configure memory regions. *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x14000, LENGTH = 0x2C000 \/* 80 kB is taken by S110, 176 kB for app. *\/\r\n  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 \/* 8 kB is taken by S110,8 kB for app. *\/\r\n}\r\nINCLUDE \"gcc_nrf51_common.ld\"\r\n","old_contents":"\/* Linker script to configure memory regions. *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x14000, LENGTH = 0x26000 \/* 80 kB is taken by S110, 176 kB for app. *\/\r\n  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 \/* 8 kB is taken by S110,8 kB for app. *\/\r\n}\r\nINCLUDE \"gcc_nrf51_common.ld\"\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"cde1d1a367960fd0f0973b4e3ecae13f25e3c5f5","subject":"Added comments back to linker script and changedgp location","message":"Added comments back to linker script and changedgp location\n","repos":"DragonMinded\/libdragon,sp1187\/libdragon,sp1187\/libdragon,DragonMinded\/libdragon,DragonMinded\/libdragon,sp1187\/libdragon","old_file":"n64.ld","new_file":"n64.ld","new_contents":"\/* ========================================================================\n *\n * n64ld.x\n *\n * GNU Linker script for building an image that is set up for the N64\n * but still has the data factored into sections.  It is not directly\n * runnable, and it contains the debug info if available.  It will need\n * a 'loader' to perform the final stage of transformation to produce\n * a raw image.\n *\n * Copyright (c) 1999 Ground Zero Development, All rights reserved.\n * Developed by Frank Somers <frank@g0dev.com>\n * Modifications by hcs (halleyscometsoftware@hotmail.com)\n *\n * $Header: \/afs\/icequake.net\/users\/nemesis\/n64\/sf\/asdf\/n64dev\/lib\/alt-libn64\/n64ld.x,v 1.2 2006-08-11 15:54:11 halleyscometsw Exp $\n *\n * ========================================================================\n *\/\n\nOUTPUT_FORMAT (\"elf32-bigmips\", \"elf32-bigmips\", \"elf32-littlemips\")\nOUTPUT_ARCH (mips)\nEXTERN (_start)\nENTRY (_start)\n\nMEMORY\n{\n    mem : ORIGIN = 0x80000400, LENGTH = 4M-0x0400\n}\n\nSECTIONS {\n   \/* Start address of code is 1K up in uncached, unmapped RAM.  We have\n    * to be at least this far up in order to not interfere with the cart\n    * boot code which is copying it down from the cart\n    *\/\n    . = 0x80000400;\n\n    \/* The text section carries the app code and its relocation addr is\n    * the first byte of the cart domain in cached, unmapped memory\n    *\/\n    .text : {\n        *(.boot)\n        . = ALIGN(16);\n        __text_start = .;\n        *(.text)\n        *(.text.*)\n        *(.init)\n        *(.fini)\n        *(.gnu.linkonce.t.*)\n        __text_end  = .;\n    } > mem\n\n   .eh_frame_hdr : { *(.eh_frame_hdr) } > mem\n   .eh_frame : { KEEP (*(.eh_frame)) } > mem\n   .gcc_except_table : { *(.gcc_except_table*) } > mem\n   .jcr : { KEEP (*(.jcr)) } > mem\n\n    .rodata : {\n        *(.rdata)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n    } > mem\n\n    . = ALIGN(8);\n\n    .ctors : {\n        __CTOR_LIST_SIZE__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 1)\n        __CTOR_LIST__ = .;\n        *(.ctors)\n        LONG(0)\n        __CTOR_END__ = .;\n    } > mem\n\n    . = ALIGN(8);\n\n    .dtors : {\n        __DTOR_LIST__ = .;\n        LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\n        *(.dtors)\n        LONG(0)\n        __DTOR_END__ = .;\n    } > mem\n\n    . = ALIGN(8);\n\n    \/* Data section has relocation address at start of RAM in cached,\n    * unmapped memory, but is loaded just at the end of the text segment,\n    * and must be copied to the correct location at startup\n    * Gather all initialised data together.  The memory layout\n    * will place the global initialised data at the lowest addrs.\n    * The lit8, lit4, sdata and sbss sections have to be placed\n    * together in that order from low to high addrs with the _gp symbol\n    * positioned (aligned) at the start of the sdata section.\n    * We then finish off with the standard bss section\n    *\/\n    .data : {\n        __data_start = .;\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n    } > mem\n\n    .lit8 : {\n        *(.lit8)\n    } > mem\n    .lit4 : {\n        *(.lit4)\n    } > mem\n\n    . = ALIGN(8);\n    .sdata : {\n        _gp = .;\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n    } > mem\n\n    __data_end = .;\n\n    . = ALIGN(8);\n    .sbss (NOLOAD) : {\n         __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.scommon.*)\n    } > mem\n\n    . = ALIGN(8);\n    .bss (NOLOAD) : {\n        *(.bss)\n        *(.bss*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        __bss_end = .;\n    } > mem\n\n    . = ALIGN(8);\n    end = .;\n}\n","old_contents":"\/* ========================================================================\n *\n * n64ld.x\n *\n * GNU Linker script for building an image that is set up for the N64\n * but still has the data factored into sections.  It is not directly\n * runnable, and it contains the debug info if available.  It will need\n * a 'loader' to perform the final stage of transformation to produce\n * a raw image.\n *\n * Copyright (c) 1999 Ground Zero Development, All rights reserved.\n * Developed by Frank Somers <frank@g0dev.com>\n * Modifications by hcs (halleyscometsoftware@hotmail.com)\n *\n * $Header: \/afs\/icequake.net\/users\/nemesis\/n64\/sf\/asdf\/n64dev\/lib\/alt-libn64\/n64ld.x,v 1.2 2006-08-11 15:54:11 halleyscometsw Exp $\n *\n * ========================================================================\n *\/\n\nOUTPUT_FORMAT (\"elf32-bigmips\", \"elf32-bigmips\", \"elf32-littlemips\")\nOUTPUT_ARCH (mips)\nEXTERN (_start)\nENTRY (_start)\n\nMEMORY\n{\n    mem : ORIGIN = 0x80000400, LENGTH = 4M-0x0400\n}\n\nSECTIONS {\n    . = 0x80000400;\n\n    .text : {\n        *(.boot)\n        . = ALIGN(16);\n        __text_start = .;\n        *(.text)\n        *(.text.*)\n        *(.init)\n        *(.fini)\n        *(.gnu.linkonce.t.*)\n        __text_end  = .;\n    } > mem\n\n   .eh_frame_hdr : { *(.eh_frame_hdr) } > mem\n   .eh_frame : { KEEP (*(.eh_frame)) } > mem\n   .gcc_except_table : { *(.gcc_except_table*) } > mem\n   .jcr : { KEEP (*(.jcr)) } > mem\n\n    .rodata : {\n        *(.rdata)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n    } > mem\n\n    . = ALIGN(8);\n\n    .ctors : {\n        __CTOR_LIST_SIZE__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 1)\n        __CTOR_LIST__ = .;\n        *(.ctors)\n        LONG(0)\n        __CTOR_END__ = .;\n    } > mem\n\n    . = ALIGN(8);\n\n    .dtors : {\n        __DTOR_LIST__ = .;\n        LONG((__DTOR_END__ - __DTOR_LIST__) \/ 4 - 2)\n        *(.dtors)\n        LONG(0)\n        __DTOR_END__ = .;\n    } > mem\n\n    . = ALIGN(8);\n\n    .data : {\n        __data_start = .;\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n    } > mem\n\n    .lit8 : {\n        *(.lit8)\n    } > mem\n    .lit4 : {\n        *(.lit4)\n    } > mem\n\n    . = ALIGN(8);\n    .sdata : {\n        \/* Ideally, this should be _gp = . + 0x8000 - GCC is complaining about small data not being smaller than 64k - Any ideas? *\/\n        _gp = . + 0x7000;\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n    } > mem\n\n    __data_end = .;\n\n    . = ALIGN(8);\n    .sbss (NOLOAD) : {\n         __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.scommon.*)\n    } > mem\n\n\n    . = ALIGN(8);\n    .bss (NOLOAD) : {\n        *(.bss)\n        *(.bss*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        __bss_end = .;\n    } > mem\n\n    . = ALIGN(8);\n    end = .;\n}\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"8001d608f4e63cb29766324663924326a1826e23","subject":"[sound driver linker script] fix NMI routine length","message":"[sound driver linker script] fix NMI routine length\n","repos":"freem\/freemlib-neogeo,freem\/freemlib-neogeo","old_file":"src_z80\/sounddrv.ld","new_file":"src_z80\/sounddrv.ld","new_contents":"\/* vlink linker script for freemlib sound driver *\/\r\n\r\nMEMORY\r\n{\r\n\tstart:   ORIGIN = 0x0000, LENGTH = 0x0004 \/* 0x0000: entry point *\/\r\n\tdelay1:  ORIGIN = 0x0008, LENGTH = 0x0003 \/* 0x0008: port write delay (addr) *\/\r\n\tdelay2:  ORIGIN = 0x0010, LENGTH = 0x0003 \/* 0x0010: port write delay (data) *\/\r\n\twrite45: ORIGIN = 0x0018, LENGTH = 0x0003 \/* 0x0018: shortcut to write_45 *\/\r\n\twrite67: ORIGIN = 0x0020, LENGTH = 0x0003 \/* 0x0020: shortcut to write_67 *\/\r\n\tymwait:  ORIGIN = 0x0028, LENGTH = 0x0006 \/* 0x0028: YM2610 busy wait *\/\r\n\tIRQ:     ORIGIN = 0x0038, LENGTH = 0x0004 \/* 0x0038: IRQ trampoline *\/\r\n\tidstr:   ORIGIN = 0x0040, LENGTH = 0x0020 \/* 0x0040: driver identification *\/\r\n\tNMI:     ORIGIN = 0x0066, LENGTH = 0x003A \/* 0x0066: NMI routine *\/\r\n\trom:     ORIGIN = 0x00A0, LENGTH = 0xF760 \/* 0x00A0: start of the rest of ROM *\/\r\n\tram:     ORIGIN = 0xF800, LENGTH = 0x0800 \/* RAM at 0xF800-0xFFFF *\/\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.start : { *(start) } > start\r\n\t.delay1 : { *(delay1) } > delay1\r\n\t.delay2 : { *(delay2) } > delay2\r\n\t.write45 : { *(write45) } > write45\r\n\t.write67 : { *(write67) } > write67\r\n\t.ymwait : { *(ymwait) } > ymwait\r\n\t.IRQ : { *(IRQ) } > IRQ\r\n\t.idstr : { *(idstr) } > idstr\r\n\t.NMI : { *(NMI) } > NMI\r\n\t.code : { *(code) } > rom\r\n\t.bss (NOLOAD) : { *(bss) } > ram\r\n}\r\n","old_contents":"\/* vlink linker script for freemlib sound driver *\/\r\n\r\nMEMORY\r\n{\r\n\tstart:   ORIGIN = 0x0000, LENGTH = 0x0004 \/* 0x0000: entry point *\/\r\n\tdelay1:  ORIGIN = 0x0008, LENGTH = 0x0003 \/* 0x0008: port write delay (addr) *\/\r\n\tdelay2:  ORIGIN = 0x0010, LENGTH = 0x0003 \/* 0x0010: port write delay (data) *\/\r\n\twrite45: ORIGIN = 0x0018, LENGTH = 0x0003 \/* 0x0018: shortcut to write_45 *\/\r\n\twrite67: ORIGIN = 0x0020, LENGTH = 0x0003 \/* 0x0020: shortcut to write_67 *\/\r\n\tymwait:  ORIGIN = 0x0028, LENGTH = 0x0006 \/* 0x0028: YM2610 busy wait *\/\r\n\tIRQ:     ORIGIN = 0x0038, LENGTH = 0x0004 \/* 0x0038: IRQ trampoline *\/\r\n\tidstr:   ORIGIN = 0x0040, LENGTH = 0x0020 \/* 0x0040: driver identification *\/\r\n\tNMI:     ORIGIN = 0x0066, LENGTH = 0x004A \/* 0x0066: NMI routine *\/\r\n\trom:     ORIGIN = 0x00A0, LENGTH = 0xF760 \/* 0x00A0: start of the rest of ROM *\/\r\n\tram:     ORIGIN = 0xF800, LENGTH = 0x0800 \/* RAM at 0xF800-0xFFFF *\/\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t.start : { *(start) } > start\r\n\t.delay1 : { *(delay1) } > delay1\r\n\t.delay2 : { *(delay2) } > delay2\r\n\t.write45 : { *(write45) } > write45\r\n\t.write67 : { *(write67) } > write67\r\n\t.ymwait : { *(ymwait) } > ymwait\r\n\t.IRQ : { *(IRQ) } > IRQ\r\n\t.idstr : { *(idstr) } > idstr\r\n\t.NMI : { *(NMI) } > NMI\r\n\t.code : { *(code) } > rom\r\n\t.bss (NOLOAD) : { *(bss) } > ram\r\n}\r\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"d650c37b2f8dbc5ac5055957617816eeb40ec79c","subject":"[IA64] check-segrel.lds vs --build-id","message":"[IA64] check-segrel.lds vs --build-id\n\nSome versions of ld with --build-id support will crash when using the flag\nwith a linker script that discards notes.  This bites ia64's check-segrel.lds.\nThe bug is easy to avoid.\n\nSigned-off-by: Roland McGrath <0d270388f2f92757a5de0f4bd891d3b392c44c4f@redhat.com>\nSigned-off-by: Tony Luck <e7984595ec0368ff920a7b3521dc7093683f6f26@intel.com>\n","repos":"KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas","old_file":"arch\/ia64\/scripts\/check-segrel.lds","new_file":"arch\/ia64\/scripts\/check-segrel.lds","new_contents":"SECTIONS {\n\t. = SIZEOF_HEADERS;\n\t.rodata : { *(.rodata) } :ro\n\t.note : { *(.note*) }\n\t. = 0xa0000;\n\t.data : { *(.data) } :dat\n\t\/DISCARD\/ : { *(*) }\n}\nPHDRS {\n  ro PT_LOAD FILEHDR PHDRS;\n  dat PT_LOAD;\n}\n","old_contents":"SECTIONS {\n\t. = SIZEOF_HEADERS;\n\t.rodata : { *(.rodata) } :ro\n\t. = 0xa0000;\n\t.data : { *(.data) } :dat\n\t\/DISCARD\/ : { *(*) }\n}\nPHDRS {\n  ro PT_LOAD FILEHDR PHDRS;\n  dat PT_LOAD;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b35a41f9815cf84afd2e87f5128dbf55db094a7d","subject":"include: linker: add sections for USB device stack","message":"include: linker: add sections for USB device stack\n\nThis patch adds a RAM section for the USB descriptors and\nUSB interfaces data.\n\nThe parts of USB descriptor can be declared independently in\ndifferent USB class drivers or functions. These must then be\nplaced in a predefined order one after the other without gaps\nin a RAM section. There may also be several device descriptors\nin the section such as for USB DFU.\n\nSince at runtime the number of interfaces and endpoints in the\ncomposite device descriptor is unknown, they must be corrected.\nThe class drivers or functions use the usb_cfg_data struct to\nstore the callbacks, interface and endpoints data. This struct\nmust also be corrected and needs to be placed in the data section.\nThe descriptor section and data section must be processed by\nthe USB Device Stack before the enumeration.\n\nSigned-off-by: Johann Fischer <b39b26e1812eb092eb217277792f3735321fa456@phytec.de>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,ldts\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,punitvara\/zephyr,finikorg\/zephyr,ldts\/zephyr,explora26\/zephyr,punitvara\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,punitvara\/zephyr,punitvara\/zephyr,ldts\/zephyr,Vudentz\/zephyr,explora26\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,kraj\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,kraj\/zephyr,nashif\/zephyr,Vudentz\/zephyr,ldts\/zephyr,Vudentz\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,kraj\/zephyr,kraj\/zephyr,explora26\/zephyr,galak\/zephyr,finikorg\/zephyr","old_file":"include\/linker\/common-ram.ld","new_file":"include\/linker\/common-ram.ld","new_contents":"\tSECTION_DATA_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_DATA_PROLOGUE(initlevel_error, (OPTIONAL), )\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\tSECTION_DATA_PROLOGUE(initshell, (OPTIONAL),)\n\t{\n\t\tSHELL_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_static_thread_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_static_thread_data_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._static_thread_data.static.*\")))\n\t\t_static_thread_data_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_DATA_PROLOGUE(_k_timer_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_timer_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_timer.static.*\")))\n\t\t_k_timer_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_slab_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mem_slab_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_slab.static.*\")))\n\t\t_k_mem_slab_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\t\t_k_mem_pool_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_pool.static.*\")))\n\t\t_k_mem_pool_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_sem_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_sem_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_sem.static.*\")))\n\t\t_k_sem_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mutex_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mutex_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mutex.static.*\")))\n\t\t_k_mutex_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_alert_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_alert_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_alert.static.*\")))\n\t\t_k_alert_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_queue_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_queue_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_queue.static.*\")))\n\t\t_k_queue_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_stack_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_stack_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_stack.static.*\")))\n\t\t_k_stack_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_msgq_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_msgq_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_msgq.static.*\")))\n\t\t_k_msgq_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mbox_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mbox_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mbox.static.*\")))\n\t\t_k_mbox_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_pipe_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_pipe_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe.static.*\")))\n\t\t_k_pipe_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_work_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_work_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_work.static.*\")))\n\t\t_k_work_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_task_list, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_task_list_start = .;\n\t\t*(._k_task_list.public.*)\n\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_event_list, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_event_list_start = .;\n\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_memory_pool, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t*(._k_memory_pool.struct*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\n\t\t_k_mem_pool_start = .;\n\t\t*(._k_memory_pool.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool*\")))\n\t\t_k_mem_pool_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_start = .;\n\t\t*(\".net_if.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if.*\")))\n\t\t__net_if_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if_dev, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_dev_start = .;\n\t\t*(\".net_if_dev.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if_dev.*\")))\n\t\t__net_if_dev_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SHELL)\n\tSECTION_DATA_PROLOGUE(net_stack, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_stack_start = .;\n\t\t*(\".net_stack.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_stack*\")))\n\t\t__net_stack_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_NET_SHELL *\/\n\n\tSECTION_DATA_PROLOGUE(net_l2_data, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_l2_data_start = .;\n\t\t*(\".net_l2.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.data*\")))\n\t\t__net_l2_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(usb_data, (OPTIONAL), SUBALIGN(1))\n\t{\n\t\t__usb_data_start = .;\n\t\t*(\".usb.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.data*\")))\n\t\t__usb_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n","old_contents":"\tSECTION_DATA_PROLOGUE(initlevel, (OPTIONAL),)\n\t{\n\t\tDEVICE_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t\/* verify we don't have rogue .init_<something> initlevel sections *\/\n\tSECTION_DATA_PROLOGUE(initlevel_error, (OPTIONAL), )\n\t{\n\t\tDEVICE_INIT_UNDEFINED_SECTION()\n\t}\n\tASSERT(SIZEOF(initlevel_error) == 0, \"Undefined initialization levels used.\")\n\n\tSECTION_DATA_PROLOGUE(initshell, (OPTIONAL),)\n\t{\n\t\tSHELL_INIT_SECTIONS()\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_static_thread_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_static_thread_data_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._static_thread_data.static.*\")))\n\t\t_static_thread_data_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_DATA_PROLOGUE(_k_timer_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_timer_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_timer.static.*\")))\n\t\t_k_timer_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_slab_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mem_slab_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_slab.static.*\")))\n\t\t_k_mem_slab_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mem_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\t\t_k_mem_pool_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mem_pool.static.*\")))\n\t\t_k_mem_pool_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_sem_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_sem_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_sem.static.*\")))\n\t\t_k_sem_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mutex_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mutex_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mutex.static.*\")))\n\t\t_k_mutex_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_alert_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_alert_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_alert.static.*\")))\n\t\t_k_alert_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_queue_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_queue_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_queue.static.*\")))\n\t\t_k_queue_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_stack_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_stack_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_stack.static.*\")))\n\t\t_k_stack_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_msgq_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_msgq_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_msgq.static.*\")))\n\t\t_k_msgq_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_mbox_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_mbox_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_mbox.static.*\")))\n\t\t_k_mbox_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_pipe_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_pipe_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_pipe.static.*\")))\n\t\t_k_pipe_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_work_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_work_list_start = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._k_work.static.*\")))\n\t\t_k_work_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_task_list, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_task_list_start = .;\n\t\t*(._k_task_list.public.*)\n\t\t*(._k_task_list.private.*)\n\t\t_k_task_list_idle_start = .;\n\t\t*(._k_task_list.idle.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_task_list*\")))\n\t\t_k_task_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_event_list, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_k_event_list_start = .;\n\t\t*(._k_event_list.event.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_event_list*\")))\n\t\t_k_event_list_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_k_memory_pool, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t*(._k_memory_pool.struct*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool.struct*\")))\n\n\t\t_k_mem_pool_start = .;\n\t\t*(._k_memory_pool.*)\n\t\tKEEP(*(SORT_BY_NAME(\"._k_memory_pool*\")))\n\t\t_k_mem_pool_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_start = .;\n\t\t*(\".net_if.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if.*\")))\n\t\t__net_if_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(net_if_dev, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_if_dev_start = .;\n\t\t*(\".net_if_dev.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_if_dev.*\")))\n\t\t__net_if_dev_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NET_SHELL)\n\tSECTION_DATA_PROLOGUE(net_stack, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_stack_start = .;\n\t\t*(\".net_stack.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_stack*\")))\n\t\t__net_stack_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_NET_SHELL *\/\n\n\tSECTION_DATA_PROLOGUE(net_l2_data, (OPTIONAL), SUBALIGN(4))\n\t{\n\t\t__net_l2_data_start = .;\n\t\t*(\".net_l2.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".net_l2.data*\")))\n\t\t__net_l2_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9845a064ad22dd6cc6c720a8b765978a16e71ff7","subject":"ports: fomu: move more functions into ram for stability","message":"ports: fomu: move more functions into ram for stability\n\nThe SPI flash on current Fomu firmware is slow.  Circuitpython runs\nXIP from SPI flash, and so execution time can also be slow.  Ordinarily\nthis isn't a problem, however certain operations are time-sensitive.\n\nIn particular, USB function needs to be handled quickly in order to\nprevent the host from re-enumerating the device.\n\nPlace several critical TinyUSB structures into RAM, as well as several\nhot functions that are frequently called.  This reduces execution time\nat the expense of system memory, and greatly improves system stability.\n\nSigned-off-by: Sean Cross <d7e19930cc1f42c2d0781f4d9e6f1fe5891bf9cf@xobs.io>\n","repos":"adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython","old_file":"ports\/litex\/boards\/fomu\/fomu-spi.ld","new_file":"ports\/litex\/boards\/fomu\/fomu-spi.ld","new_contents":"\/*\n    GNU linker script for Fomu\n*\/\n\nENTRY(_start)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x20040000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    RAM (xrw)       : ORIGIN = 0x10000000, LENGTH = 0x00020000 \/* 128 KiB *\/\n}\n\n\/* top end of the stack *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :  AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n\n        *(.itcm.*)         \/* Instruction Tightly Coupled Memory *\/\n        *(.dtcm_data.*)    \/* Data Tightly Coupled Memory *\/\n\n        *(.text.cmp_lfn)\n        *(.text.qstr_find_strn)\n        *(.text.dcd_edpt_xfer)\n        *(.text.pop_rule)\n        *(.text.ff_wtoupper)\n        *(.text.dir_find)\n        *(.text.push_rule)\n        *(.text.csr_writel)\n        *(.text.csr_readl)\n        *(.text.timer0_ev_pending_write)\n        *(.text.autoreload_tick)\n        *(.text.filesystem_tick)\n        *(.text.usb_background)\n\n        *(.text.dcd_*)\n        *(.text.tud_control_*)\n        *(.text.tud_cdc_n_write_flush)\n        *(.text.tud_task)\n        *(.text.tu_edpt_dir)\n        *(.text.tu_fifo_empty)\n        *(.text.usbd_edpt_busy)\n        *(.text.irq_getmask)\n        *(.text.irq_setmask)\n        *(.text.irq_pending)\n        *(.text._osal_q_lock)\n        *(.text.osal_queue_receive)\n\n        *(.text.mp_obj_get_type)\n        *(.text.mp_parse)\n        *(.text.parse_compile_execute)\n        *(.text.mp_map_lookup)\n        *(.text.mp_execute_bytecode) \/* Note: this function is 7kb *\/\n\n        *(.ramtext)        \/* .text* sections (code) *\/\n        *(.ramtext*)       \/* .text* sections (code) *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n        *(.sdata)          \/* .data sections *\/\n        *(.sdata*)         \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.text.start)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        *(.srodata)        \/* .rodata sections (constants, strings, etc.) *\/\n        *(.srodata*)       \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(.dtcm_bss.*)     \/* Data Tightly Coupled Memory *\/\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n    } >RAM\n}\n","old_contents":"\/*\n    GNU linker script for Fomu\n*\/\n\nENTRY(_start)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x20040000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    RAM (xrw)       : ORIGIN = 0x10000000, LENGTH = 0x00020000 \/* 128 KiB *\/\n}\n\n\/* top end of the stack *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :  AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n\n\t*(.itcm.*)         \/* Instruction Tightly Coupled Memory *\/\n\t*(.dtcm_data.*)    \/* Data Tightly Coupled Memory *\/\n        *(.ramtext)        \/* .text* sections (code) *\/\n        *(.ramtext*)       \/* .text* sections (code) *\/\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n        *(.sdata)          \/* .data sections *\/\n        *(.sdata*)         \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM\n\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        KEEP(*(.text.start)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n        *(.srodata)        \/* .rodata sections (constants, strings, etc.) *\/\n        *(.srodata*)       \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = _etext;  \/* This is used by the startup in order to initialize the .data secion *\/\n    } >FLASH\n\n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n\t*(.dtcm_bss.*)     \/* Data Tightly Coupled Memory *\/\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code *\/\n    } >RAM\n\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n    } >RAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"df9b7e8f24384df446c98c10b28f4fb143d66d61","subject":"esp32\/esp32.custom_common.ld: Put soc code in iram0.","message":"esp32\/esp32.custom_common.ld: Put soc code in iram0.\n\nThis is what the IDF does, it must be done.\n","repos":"adafruit\/micropython,MrSurly\/micropython,trezor\/micropython,henriknelson\/micropython,MrSurly\/micropython,pozetroninc\/micropython,kerneltask\/micropython,dmazzella\/micropython,selste\/micropython,pfalcon\/micropython,pfalcon\/micropython,adafruit\/micropython,selste\/micropython,tobbad\/micropython,adafruit\/micropython,kerneltask\/micropython,pfalcon\/micropython,tobbad\/micropython,adafruit\/circuitpython,MrSurly\/micropython,adafruit\/circuitpython,tralamazza\/micropython,trezor\/micropython,trezor\/micropython,selste\/micropython,adafruit\/micropython,tralamazza\/micropython,henriknelson\/micropython,swegener\/micropython,dmazzella\/micropython,MrSurly\/micropython,selste\/micropython,kerneltask\/micropython,pozetroninc\/micropython,adafruit\/circuitpython,swegener\/micropython,swegener\/micropython,tobbad\/micropython,pozetroninc\/micropython,dmazzella\/micropython,pramasoul\/micropython,tobbad\/micropython,tralamazza\/micropython,henriknelson\/micropython,pramasoul\/micropython,kerneltask\/micropython,adafruit\/circuitpython,adafruit\/micropython,kerneltask\/micropython,adafruit\/circuitpython,pfalcon\/micropython,pramasoul\/micropython,bvernoux\/micropython,trezor\/micropython,trezor\/micropython,pramasoul\/micropython,bvernoux\/micropython,dmazzella\/micropython,henriknelson\/micropython,MrSurly\/micropython,pfalcon\/micropython,tralamazza\/micropython,swegener\/micropython,bvernoux\/micropython,pozetroninc\/micropython,pozetroninc\/micropython,bvernoux\/micropython,swegener\/micropython,selste\/micropython,pramasoul\/micropython,henriknelson\/micropython,tobbad\/micropython,bvernoux\/micropython,adafruit\/circuitpython","old_file":"ports\/esp32\/esp32.custom_common.ld","new_file":"ports\/esp32\/esp32.custom_common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *heap\/multi_heap.o(.literal .text .literal.* .text.*)\n    *heap\/multi_heap_poisoning.o(.literal .text .literal.* .text.*)\n    *esp32\/panic.o(.literal .text .literal.* .text.*)\n    *esp32\/core_dump.o(.literal .text .literal.* .text.*)\n    *app_trace\/*(.literal .text .literal.* .text.*)\n    *xtensa-debug-module\/eri.o(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *soc\/esp32\/*(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *spi_flash\/spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    *py\/scheduler.o*(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *esp32\/panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *soc\/esp32\/rtc_clk.o(.rodata .rodata.*)\n    *app_trace\/app_trace.o(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *heap\/multi_heap.o(.rodata .rodata.*)\n    *heap\/multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *freertos\/*(.literal .text .literal.* .text.*)\n    *heap\/multi_heap.o(.literal .text .literal.* .text.*)\n    *heap\/multi_heap_poisoning.o(.literal .text .literal.* .text.*)\n    *esp32\/panic.o(.literal .text .literal.* .text.*)\n    *esp32\/core_dump.o(.literal .text .literal.* .text.*)\n    *app_trace\/*(.literal .text .literal.* .text.*)\n    *xtensa-debug-module\/eri.o(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *spi_flash\/spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    *py\/scheduler.o*(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *esp32\/panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *soc\/esp32\/rtc_clk.o(.rodata .rodata.*)\n    *app_trace\/app_trace.o(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *heap\/multi_heap.o(.rodata .rodata.*)\n    *heap\/multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"998c1cfd9d05ef597b0a89f0b7f969789830041e","subject":"put NOLOAD on persistent data section","message":"put NOLOAD on persistent data section\n\n\nFormer-commit-id: 0726be634dd7106eda57a21c34d6ce43ec5ed373","repos":"adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX","old_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_contents":"\/************************************************************************\r\n *\tchipKIT-applicaiton-COMMON.ld\r\n *\t\r\n *\tThis is the common part of the linker script shared\r\n *\tacross all chipKIT PIC32 processors \/ boards.\r\n *\t\r\n ************************************************************************\r\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\r\n * \tThis library is free software; you can redistribute it and\/or\r\n *  modify it under the terms of the GNU Lesser General Public\r\n *\tLicense as published by the Free Software Foundation; either\r\n *\tversion 2.1 of the License, or (at your option) any later version.\r\n *\t\r\n *\tThis library is distributed in the hope that it will be useful,\r\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\r\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\r\n *\tLesser General Public License for more details.\r\n *\t\r\n *\tYou should have received a copy of the GNU Lesser General\r\n *\tPublic License along with this library; if not, write to the\r\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\r\n *\tBoston, MA\t02111-1307\tUSA\r\n *\t\r\n *\t\r\n ************************************************************************\r\n *\tEdit History\r\n ************************************************************************\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\r\n ************************************************************************\r\n *\/\r\n\r\n\/*************************************************************************\r\n * For interrupt vector handling\r\n *************************************************************************\/\r\nPROVIDE(_vector_spacing = 0x00000001);\r\n\r\n\/*************************************************************************\r\n * Start the layout of memory, the sections...\r\n *************************************************************************\/\r\nSECTIONS\r\n{\r\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\r\n  {\r\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\r\n  } > kseg0_eeprom_mem\r\n\r\n  \/DISCARD\/ : { *(.bev_handler) }\r\n\r\n .image_ptr_table _IMAGE_PTR_TABLE :\r\n  {\r\n    LONG(_ebase_address)\t\r\n    LONG(_image_header_info)\r\n  } > exception_mem\r\n\r\n  .app_excpt _GEN_EXCPT_ADDR :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  } > exception_mem\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  .startup :\r\n  {\r\n    KEEP(*(.startup))\r\n  } > kseg0_program_mem\r\n  \/* Code Sections *\/\r\n\r\n  .text  :\r\n  {\r\n    _text_begin = . ;\r\n\r\n    *(.text .stub .text.* .gnu.linkonce.t.*)\r\n    KEEP (*(.text.*personality*))\r\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\r\n    *(.gnu.warning)\r\n    *(.mips16.fn.*)\r\n    *(.mips16.call.*)\r\n    . = ALIGN(4) ;\r\n    _text_end = . ;\r\n  } >kseg0_program_mem =0\r\n\r\n   .init      :\r\n  {\r\n\tKEEP (*crti.o(.init))\r\n\tKEEP (*crtbegin.o(.init))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\r\n\tKEEP (*crtend.o(.init))\r\n    KEEP (*crtn.o(.init))\r\n    . = ALIGN(4) ;\r\n  }  >kseg0_program_mem\r\n\r\n  .fini       :\r\n  {\r\n    KEEP (*(.fini))\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .init_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .fini_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .ctors        :\r\n  {\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  .dtors          :\r\n  {\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  .preinit_array    :\r\n  {\r\n    KEEP (*(.preinit_array))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  \/* Read-only sections *\/\r\n  .header_info ALIGN(4) :\r\n  {\r\n    _image_header_info = . ;\r\n    LONG(SIZEOF(.header_info))          \/* size of this structure       *\/\r\n    LONG(0xFFFFFFFF)                    \/* bootloader version           *\/\r\n    KEEP(*(.mpide_version))             \/* MPIDE build version          *\/\r\n    LONG(0xFFFFFFFF)                    \/* booloader capabilities       *\/\r\n    LONG(0xFFFFFFFF)                    \/* VID and PID                  *\/\r\n    LONG(_IMAGE_TYPE)                   \/* image type and options       *\/\r\n    LONG(_JUMP_ADDR)                    \/* image execution address      *\/\r\n    LONG(_ebase_address)                \/* image base address           *\/\r\n    LONG(_IMAGE_FLASH_SIZE)             \/* size of image flash used     *\/\r\n    LONG(ORIGIN(kseg0_eeprom_mem))      \/* eeprom location              *\/\r\n    LONG(LENGTH(kseg0_eeprom_mem))      \/* eeprom size                  *\/   \r\n    LONG(ORIGIN(configsfrs))            \/* config bits location         *\/\r\n    LONG(LENGTH(configsfrs))            \/* config bits size             *\/\r\n    LONG(_ram_header_addr)              \/* ram header pointer           *\/\r\n    LONG(SIZEOF(.ram_exchange_data))    \/* ram Header size              *\/\r\n    LONG(0xFFFFFFFF)                    \/* what the bootloader skips    *\/\r\n    _image_header_info_end = . ;\r\n  } > kseg0_program_mem\r\n  ASSERT (SIZEOF(.header_info) == 64, \"MPIDE Version not specfied correctly\")\r\n\r\n  .rodata  ALIGN(4) :\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.rodata1)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  \/*\r\n   * Small initialized constant global and static data can be placed in the\r\n   * .sdata2 section.  This is different from .sdata, which contains small\r\n   * initialized non-constant global and static data.\r\n   *\/\r\n  .sdata2 ALIGN(4)   :\r\n  {\r\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  \/*\r\n   * Uninitialized constant global and static data (i.e., variables which will\r\n   * always be zero).  Again, this is different from .sbss, which contains\r\n   * small non-initialized, non-constant global and static data.\r\n   *\/\r\n  .sbss2 ALIGN(4)   :\r\n  {\r\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\r\n  {\r\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\r\n  } >kseg1_data_mem\r\n  \r\n  .ram_exchange_data (NOLOAD) :\r\n  {\r\n    _ram_header_addr = . ;\r\n    . += 8 ;\r\n  } >kseg1_data_mem\r\n\r\n  \/* Persistent data *\/\r\n  .persist ALIGN(4) (NOLOAD) :\r\n  {\r\n    _persist_begin = .;\r\n    *(.persist .persist.*)\r\n    . = ALIGN(4) ;\r\n    _persist_end = .;\r\n  } >kseg1_data_mem\r\n\r\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\r\n\r\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\r\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\r\n\r\n  .data  _protected_end :\r\n  { \r\n    _data_begin = . ;\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    KEEP (*(.gnu.linkonce.d.*personality*))\r\n\r\n    *(.data1)\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  _data_image_begin = LOADADDR(.data) ;\r\n  . = .;\r\n  _gp = ALIGN(16) + 0x7ff0;\r\n\r\n  .got ALIGN(4)   :\r\n  {\r\n     *(.got.plt) *(.got)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n  \/*\r\n   * We want the small data sections together, so single-instruction offsets\r\n   * can access them all, and initialized data all before uninitialized, so\r\n   * we can shorten the on-disk segment size.\r\n   *\/\r\n  .sdata ALIGN(4)   :\r\n  {\r\n    _sdata_begin = . ;\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n    . = ALIGN(4) ;\r\n    _sdata_end = . ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  .lit8           :\r\n  {\r\n    *(.lit8)\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  .lit4           :\r\n  {\r\n    *(.lit4)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  . = ALIGN (4) ;\r\n  _data_end = . ;\r\n  _bss_begin = . ;\r\n\r\n  .sbss ALIGN(4)   :\r\n  {\r\n    _sbss_begin = . ;\r\n    *(.dynsbss)\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    . = ALIGN(4) ;\r\n    _sbss_end = . ;\r\n  } >kseg1_data_mem\r\n\r\n  .bss   :\r\n  {\r\n    *(.dynbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    \/*\r\n     * Align here to ensure that the .bss section occupies space up to\r\n     * _end.  Align after .bss to ensure correct alignment even if the\r\n     * .bss section disappears because there are no input sections.\r\n     *\/\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem\r\n\r\n  . = ALIGN(4) ;\r\n  _end = . ;\r\n  _bss_end = . ;\r\n\r\n  \/* Heap allocating takes a chunk of memory following BSS *\/\r\n  .heap ALIGN(8) :\r\n  {\r\n    _heap = . ;\r\n    . += _min_heap_size ;\r\n    . = ALIGN(8);\r\n  } >kseg1_data_mem\r\n\r\n  \/* Stack allocation follows the heap *\/\r\n  .stack ALIGN(8) :\r\n  {\r\n    _splim = . ;\r\n    _SPLIM = . ;\r\n    . += _min_stack_size ;\r\n    . = ALIGN(8);\r\n  } >kseg1_data_mem\r\n\r\n  \/*\r\n   * RAM functions go at the end of our stack and heap allocation.\r\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\r\n   *\/\r\n  .ramfunc ALIGN(2K) :\r\n  {\r\n    _ramfunc_begin = . ;\r\n    *(.ramfunc  .ramfunc.*)\r\n    . = ALIGN(4) ;\r\n    _ramfunc_end = . ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\r\n  _ramfunc_length = SIZEOF(.ramfunc) ;\r\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\r\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\r\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\r\n  \/*\r\n   * The actual top of stack should include the gap between the stack\r\n   * section and the beginning of the .ramfunc section caused by the\r\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\r\n   * do not exist, then the top of the stack should point to the end of\r\n   * the data memory.\r\n   *\/\r\n  _stack = (_ramfunc_length > 0)\r\n         ? _ramfunc_begin - 4\r\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\r\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\r\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\r\n    \/* The .pdr section belongs in the absolute section *\/\r\n    \/DISCARD\/ : { *(.pdr) }\r\n    \/* We don't load .reginfo onto the target, so don't locate it\r\n     * in real memory\r\n     *\/\r\n    \/DISCARD\/ : { *(.reginfo) }\r\n  \/* Stabs debugging sections.  *\/\r\n  .stab          0 : { *(.stab) }\r\n  .stabstr       0 : { *(.stabstr) }\r\n  .stab.excl     0 : { *(.stab.excl) }\r\n  .stab.exclstr  0 : { *(.stab.exclstr) }\r\n  .stab.index    0 : { *(.stab.index) }\r\n  .stab.indexstr 0 : { *(.stab.indexstr) }\r\n  .comment       0 : { *(.comment) }\r\n  \/* DWARF debug sections.\r\n     Symbols in the DWARF debugging sections are relative to the beginning\r\n     of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0  : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n  \/* DWARF 3 *\/\r\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\r\n  .debug_ranges   0 : { *(.debug_ranges) }\r\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\r\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\r\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\r\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\r\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\r\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\r\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\r\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\r\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\r\n  \/DISCARD\/ : { *(.rel.dyn) }\r\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\r\n}\r\n","old_contents":"\/************************************************************************\r\n *\tchipKIT-applicaiton-COMMON.ld\r\n *\t\r\n *\tThis is the common part of the linker script shared\r\n *\tacross all chipKIT PIC32 processors \/ boards.\r\n *\t\r\n ************************************************************************\r\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\r\n * \tThis library is free software; you can redistribute it and\/or\r\n *  modify it under the terms of the GNU Lesser General Public\r\n *\tLicense as published by the Free Software Foundation; either\r\n *\tversion 2.1 of the License, or (at your option) any later version.\r\n *\t\r\n *\tThis library is distributed in the hope that it will be useful,\r\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\r\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\r\n *\tLesser General Public License for more details.\r\n *\t\r\n *\tYou should have received a copy of the GNU Lesser General\r\n *\tPublic License along with this library; if not, write to the\r\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\r\n *\tBoston, MA\t02111-1307\tUSA\r\n *\t\r\n *\t\r\n ************************************************************************\r\n *\tEdit History\r\n ************************************************************************\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\r\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\r\n ************************************************************************\r\n *\/\r\n\r\n\/*************************************************************************\r\n * For interrupt vector handling\r\n *************************************************************************\/\r\nPROVIDE(_vector_spacing = 0x00000001);\r\n\r\n\/*************************************************************************\r\n * Start the layout of memory, the sections...\r\n *************************************************************************\/\r\nSECTIONS\r\n{\r\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\r\n  {\r\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\r\n  } > kseg0_eeprom_mem\r\n\r\n  \/DISCARD\/ : { *(.bev_handler) }\r\n\r\n .image_ptr_table _IMAGE_PTR_TABLE :\r\n  {\r\n    LONG(_ebase_address)\t\r\n    LONG(_image_header_info)\r\n  } > exception_mem\r\n\r\n  .app_excpt _GEN_EXCPT_ADDR :\r\n  {\r\n    KEEP(*(.gen_handler))\r\n  } > exception_mem\r\n\r\n  .vector_0 _ebase_address + 0x200 :\r\n  {\r\n    KEEP(*(.vector_0))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\r\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\r\n  {\r\n    KEEP(*(.vector_1))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\r\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\r\n  {\r\n    KEEP(*(.vector_2))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\r\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\r\n  {\r\n    KEEP(*(.vector_3))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\r\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\r\n  {\r\n    KEEP(*(.vector_4))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\r\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\r\n  {\r\n    KEEP(*(.vector_5))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\r\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\r\n  {\r\n    KEEP(*(.vector_6))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\r\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\r\n  {\r\n    KEEP(*(.vector_7))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\r\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\r\n  {\r\n    KEEP(*(.vector_8))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\r\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\r\n  {\r\n    KEEP(*(.vector_9))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\r\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\r\n  {\r\n    KEEP(*(.vector_10))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\r\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\r\n  {\r\n    KEEP(*(.vector_11))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\r\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\r\n  {\r\n    KEEP(*(.vector_12))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\r\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\r\n  {\r\n    KEEP(*(.vector_13))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\r\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\r\n  {\r\n    KEEP(*(.vector_14))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\r\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\r\n  {\r\n    KEEP(*(.vector_15))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\r\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\r\n  {\r\n    KEEP(*(.vector_16))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\r\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\r\n  {\r\n    KEEP(*(.vector_17))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\r\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\r\n  {\r\n    KEEP(*(.vector_18))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\r\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\r\n  {\r\n    KEEP(*(.vector_19))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\r\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\r\n  {\r\n    KEEP(*(.vector_20))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\r\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\r\n  {\r\n    KEEP(*(.vector_21))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\r\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\r\n  {\r\n    KEEP(*(.vector_22))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\r\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\r\n  {\r\n    KEEP(*(.vector_23))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\r\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\r\n  {\r\n    KEEP(*(.vector_24))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\r\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\r\n  {\r\n    KEEP(*(.vector_25))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\r\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\r\n  {\r\n    KEEP(*(.vector_26))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\r\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\r\n  {\r\n    KEEP(*(.vector_27))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\r\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\r\n  {\r\n    KEEP(*(.vector_28))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\r\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\r\n  {\r\n    KEEP(*(.vector_29))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\r\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\r\n  {\r\n    KEEP(*(.vector_30))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\r\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\r\n  {\r\n    KEEP(*(.vector_31))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\r\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\r\n  {\r\n    KEEP(*(.vector_32))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\r\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\r\n  {\r\n    KEEP(*(.vector_33))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\r\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\r\n  {\r\n    KEEP(*(.vector_34))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\r\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\r\n  {\r\n    KEEP(*(.vector_35))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\r\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\r\n  {\r\n    KEEP(*(.vector_36))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\r\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\r\n  {\r\n    KEEP(*(.vector_37))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\r\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\r\n  {\r\n    KEEP(*(.vector_38))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\r\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\r\n  {\r\n    KEEP(*(.vector_39))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\r\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\r\n  {\r\n    KEEP(*(.vector_40))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\r\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\r\n  {\r\n    KEEP(*(.vector_41))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\r\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\r\n  {\r\n    KEEP(*(.vector_42))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\r\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\r\n  {\r\n    KEEP(*(.vector_43))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\r\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\r\n  {\r\n    KEEP(*(.vector_44))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\r\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\r\n  {\r\n    KEEP(*(.vector_45))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\r\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\r\n  {\r\n    KEEP(*(.vector_46))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\r\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\r\n  {\r\n    KEEP(*(.vector_47))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\r\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\r\n  {\r\n    KEEP(*(.vector_48))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\r\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\r\n  {\r\n    KEEP(*(.vector_49))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\r\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\r\n  {\r\n    KEEP(*(.vector_50))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\r\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\r\n  {\r\n    KEEP(*(.vector_51))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\r\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\r\n  {\r\n    KEEP(*(.vector_52))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\r\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\r\n  {\r\n    KEEP(*(.vector_53))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\r\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\r\n  {\r\n    KEEP(*(.vector_54))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\r\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\r\n  {\r\n    KEEP(*(.vector_55))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\r\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\r\n  {\r\n    KEEP(*(.vector_56))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\r\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\r\n  {\r\n    KEEP(*(.vector_57))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\r\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\r\n  {\r\n    KEEP(*(.vector_58))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\r\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\r\n  {\r\n    KEEP(*(.vector_59))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\r\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\r\n  {\r\n    KEEP(*(.vector_60))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\r\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\r\n  {\r\n    KEEP(*(.vector_61))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\r\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\r\n  {\r\n    KEEP(*(.vector_62))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\r\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\r\n  {\r\n    KEEP(*(.vector_63))\r\n  } > exception_mem\r\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\r\n  .startup :\r\n  {\r\n    KEEP(*(.startup))\r\n  } > kseg0_program_mem\r\n  \/* Code Sections *\/\r\n\r\n  .text  :\r\n  {\r\n    _text_begin = . ;\r\n\r\n    *(.text .stub .text.* .gnu.linkonce.t.*)\r\n    KEEP (*(.text.*personality*))\r\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\r\n    *(.gnu.warning)\r\n    *(.mips16.fn.*)\r\n    *(.mips16.call.*)\r\n    . = ALIGN(4) ;\r\n    _text_end = . ;\r\n  } >kseg0_program_mem =0\r\n\r\n   .init      :\r\n  {\r\n\tKEEP (*crti.o(.init))\r\n\tKEEP (*crtbegin.o(.init))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\r\n\tKEEP (*crtend.o(.init))\r\n    KEEP (*crtn.o(.init))\r\n    . = ALIGN(4) ;\r\n  }  >kseg0_program_mem\r\n\r\n  .fini       :\r\n  {\r\n    KEEP (*(.fini))\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .init_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .fini_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array))\r\n    . = ALIGN(4) ;\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  }>kseg0_program_mem\r\n\r\n  .ctors        :\r\n  {\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  The wildcard also means that it\r\n       doesn't matter which directory crtbegin.o\r\n       is in.  *\/\r\n    KEEP (*crtbegin.o(.ctors))\r\n    KEEP (*crtbegin?.o(.ctors))\r\n    \/* We don't want to include the .ctor section from\r\n       the crtend.o file until after the sorted ctors.\r\n       The .ctor section from the crtend file contains the\r\n       end of ctors marker and it must be last *\/\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\r\n    KEEP (*(SORT(.ctors.*)))\r\n    KEEP (*(.ctors))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  .dtors          :\r\n  {\r\n    KEEP (*crtbegin.o(.dtors))\r\n    KEEP (*crtbegin?.o(.dtors))\r\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\r\n    KEEP (*(SORT(.dtors.*)))\r\n    KEEP (*(.dtors))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  .preinit_array    :\r\n  {\r\n    KEEP (*(.preinit_array))\r\n    . = ALIGN(4) ;\r\n  }>kseg0_program_mem\r\n\r\n  \/* Read-only sections *\/\r\n  .header_info ALIGN(4) :\r\n  {\r\n    _image_header_info = . ;\r\n    LONG(SIZEOF(.header_info))          \/* size of this structure       *\/\r\n    LONG(0xFFFFFFFF)                    \/* bootloader version           *\/\r\n    KEEP(*(.mpide_version))             \/* MPIDE build version          *\/\r\n    LONG(0xFFFFFFFF)                    \/* booloader capabilities       *\/\r\n    LONG(0xFFFFFFFF)                    \/* VID and PID                  *\/\r\n    LONG(_IMAGE_TYPE)                   \/* image type and options       *\/\r\n    LONG(_JUMP_ADDR)                    \/* image execution address      *\/\r\n    LONG(_ebase_address)                \/* image base address           *\/\r\n    LONG(_IMAGE_FLASH_SIZE)             \/* size of image flash used     *\/\r\n    LONG(ORIGIN(kseg0_eeprom_mem))      \/* eeprom location              *\/\r\n    LONG(LENGTH(kseg0_eeprom_mem))      \/* eeprom size                  *\/   \r\n    LONG(ORIGIN(configsfrs))            \/* config bits location         *\/\r\n    LONG(LENGTH(configsfrs))            \/* config bits size             *\/\r\n    LONG(_ram_header_addr)              \/* ram header pointer           *\/\r\n    LONG(SIZEOF(.ram_exchange_data))    \/* ram Header size              *\/\r\n    LONG(0xFFFFFFFF)                    \/* what the bootloader skips    *\/\r\n    _image_header_info_end = . ;\r\n  } > kseg0_program_mem\r\n  ASSERT (SIZEOF(.header_info) == 64, \"MPIDE Version not specfied correctly\")\r\n\r\n  .rodata  ALIGN(4) :\r\n  {\r\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\r\n    *(.rodata1)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  \/*\r\n   * Small initialized constant global and static data can be placed in the\r\n   * .sdata2 section.  This is different from .sdata, which contains small\r\n   * initialized non-constant global and static data.\r\n   *\/\r\n  .sdata2 ALIGN(4)   :\r\n  {\r\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  \/*\r\n   * Uninitialized constant global and static data (i.e., variables which will\r\n   * always be zero).  Again, this is different from .sbss, which contains\r\n   * small non-initialized, non-constant global and static data.\r\n   *\/\r\n  .sbss2 ALIGN(4)   :\r\n  {\r\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\r\n    . = ALIGN(4) ;\r\n  } >kseg0_program_mem\r\n\r\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\r\n  {\r\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\r\n  } >kseg1_data_mem\r\n  \r\n  .ram_exchange_data :\r\n  {\r\n    _ram_header_addr = . ;\r\n    . += 8 ;\r\n  } >kseg1_data_mem\r\n\r\n  \/* Persistent data *\/\r\n  .persist ALIGN(4) :\r\n  {\r\n    _persist_begin = .;\r\n    *(.persist .persist.*)\r\n    . = ALIGN(4) ;\r\n    _persist_end = .;\r\n  } >kseg1_data_mem\r\n\r\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\r\n\r\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\r\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\r\n\r\n  .data  _protected_end :\r\n  { \r\n    _data_begin = . ;\r\n    *(.data .data.* .gnu.linkonce.d.*)\r\n    KEEP (*(.gnu.linkonce.d.*personality*))\r\n\r\n    *(.data1)\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  _data_image_begin = LOADADDR(.data) ;\r\n  . = .;\r\n  _gp = ALIGN(16) + 0x7ff0;\r\n\r\n  .got ALIGN(4)   :\r\n  {\r\n     *(.got.plt) *(.got)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n  \/*\r\n   * We want the small data sections together, so single-instruction offsets\r\n   * can access them all, and initialized data all before uninitialized, so\r\n   * we can shorten the on-disk segment size.\r\n   *\/\r\n  .sdata ALIGN(4)   :\r\n  {\r\n    _sdata_begin = . ;\r\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\r\n    . = ALIGN(4) ;\r\n    _sdata_end = . ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  .lit8           :\r\n  {\r\n    *(.lit8)\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  .lit4           :\r\n  {\r\n    *(.lit4)\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  . = ALIGN (4) ;\r\n  _data_end = . ;\r\n  _bss_begin = . ;\r\n\r\n  .sbss ALIGN(4)   :\r\n  {\r\n    _sbss_begin = . ;\r\n    *(.dynsbss)\r\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\r\n    *(.scommon)\r\n    . = ALIGN(4) ;\r\n    _sbss_end = . ;\r\n  } >kseg1_data_mem\r\n\r\n  .bss   :\r\n  {\r\n    *(.dynbss)\r\n    *(.bss .bss.* .gnu.linkonce.b.*)\r\n    *(COMMON)\r\n    \/*\r\n     * Align here to ensure that the .bss section occupies space up to\r\n     * _end.  Align after .bss to ensure correct alignment even if the\r\n     * .bss section disappears because there are no input sections.\r\n     *\/\r\n    . = ALIGN(4) ;\r\n  } >kseg1_data_mem\r\n\r\n  . = ALIGN(4) ;\r\n  _end = . ;\r\n  _bss_end = . ;\r\n\r\n  \/* Heap allocating takes a chunk of memory following BSS *\/\r\n  .heap ALIGN(8) :\r\n  {\r\n    _heap = . ;\r\n    . += _min_heap_size ;\r\n    . = ALIGN(8);\r\n  } >kseg1_data_mem\r\n\r\n  \/* Stack allocation follows the heap *\/\r\n  .stack ALIGN(8) :\r\n  {\r\n    _splim = . ;\r\n    _SPLIM = . ;\r\n    . += _min_stack_size ;\r\n    . = ALIGN(8);\r\n  } >kseg1_data_mem\r\n\r\n  \/*\r\n   * RAM functions go at the end of our stack and heap allocation.\r\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\r\n   *\/\r\n  .ramfunc ALIGN(2K) :\r\n  {\r\n    _ramfunc_begin = . ;\r\n    *(.ramfunc  .ramfunc.*)\r\n    . = ALIGN(4) ;\r\n    _ramfunc_end = . ;\r\n  } >kseg1_data_mem AT>kseg0_program_mem\r\n\r\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\r\n  _ramfunc_length = SIZEOF(.ramfunc) ;\r\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\r\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\r\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\r\n  \/*\r\n   * The actual top of stack should include the gap between the stack\r\n   * section and the beginning of the .ramfunc section caused by the\r\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\r\n   * do not exist, then the top of the stack should point to the end of\r\n   * the data memory.\r\n   *\/\r\n  _stack = (_ramfunc_length > 0)\r\n         ? _ramfunc_begin - 4\r\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\r\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\r\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\r\n    \/* The .pdr section belongs in the absolute section *\/\r\n    \/DISCARD\/ : { *(.pdr) }\r\n    \/* We don't load .reginfo onto the target, so don't locate it\r\n     * in real memory\r\n     *\/\r\n    \/DISCARD\/ : { *(.reginfo) }\r\n  \/* Stabs debugging sections.  *\/\r\n  .stab          0 : { *(.stab) }\r\n  .stabstr       0 : { *(.stabstr) }\r\n  .stab.excl     0 : { *(.stab.excl) }\r\n  .stab.exclstr  0 : { *(.stab.exclstr) }\r\n  .stab.index    0 : { *(.stab.index) }\r\n  .stab.indexstr 0 : { *(.stab.indexstr) }\r\n  .comment       0 : { *(.comment) }\r\n  \/* DWARF debug sections.\r\n     Symbols in the DWARF debugging sections are relative to the beginning\r\n     of the section so we begin them at 0.  *\/\r\n  \/* DWARF 1 *\/\r\n  .debug          0 : { *(.debug) }\r\n  .line           0 : { *(.line) }\r\n  \/* GNU DWARF 1 extensions *\/\r\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\r\n  .debug_sfnames  0 : { *(.debug_sfnames) }\r\n  \/* DWARF 1.1 and DWARF 2 *\/\r\n  .debug_aranges  0 : { *(.debug_aranges) }\r\n  .debug_pubnames 0 : { *(.debug_pubnames) }\r\n  \/* DWARF 2 *\/\r\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\r\n  .debug_abbrev   0 : { *(.debug_abbrev) }\r\n  .debug_line     0 : { *(.debug_line) }\r\n  .debug_frame    0 : { *(.debug_frame) }\r\n  .debug_str      0 : { *(.debug_str) }\r\n  .debug_loc      0  : { *(.debug_loc) }\r\n  .debug_macinfo  0 : { *(.debug_macinfo) }\r\n  \/* SGI\/MIPS DWARF 2 extensions *\/\r\n  .debug_weaknames 0 : { *(.debug_weaknames) }\r\n  .debug_funcnames 0 : { *(.debug_funcnames) }\r\n  .debug_typenames 0 : { *(.debug_typenames) }\r\n  .debug_varnames  0 : { *(.debug_varnames) }\r\n  \/* DWARF 3 *\/\r\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\r\n  .debug_ranges   0 : { *(.debug_ranges) }\r\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\r\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\r\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\r\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\r\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\r\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\r\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\r\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\r\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\r\n  \/DISCARD\/ : { *(.rel.dyn) }\r\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\r\n}\r\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"301bc5a35850017f6ecafa0aa32e6c8c5d685935","subject":"factory-elf.lds: use ALIGN instead of NEXT","message":"factory-elf.lds: use ALIGN instead of NEXT\n","repos":"gdelugre\/shell-factory,gdelugre\/shell-factory,gdelugre\/shell-factory","old_file":"factory-elf.lds","new_file":"factory-elf.lds","new_contents":"\/* \n * Linker script for generating shell-factory targets with -N.\n *\/\nSECTIONS\n{\n    PROVIDE (__executable_start = SEGMENT_START(\"text-segment\", 0x400000));\n    . = SEGMENT_START(\"text-segment\", 0x400000) + SIZEOF_HEADERS;\n\n    \/*\n     * The executable code.\n     *\/\n    .text               : { *(.text .text.* .gnu.linkonce.t.*) }\n    PROVIDE(__etext = .);\n    PROVIDE(_etext = .);\n    PROVIDE(etext = .);\n\n    \/* \n     * Constant data.\n     * Merge into the text section.\n     *\/\n    .rodata             : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n\n    \/*\n     * Non-constant data.\n     * Pushed inside the data segment which should be adjacent to text.\n     *\/\n\n    .data               : { *(.data .data.* .gnu.linkonce.d.*) }\n    PROVIDE(edata = .);\n\n    \/*\n     * Uninitialized data. Bound to the data segment, should not take any space.\n     *\/\n    __bss_start = .;\n    .bss                : { *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) }\n\n    PROVIDE (ebss = .);\n\n    _end = ALIGN(4096);\n    PROVIDE (eend = _end);\n\n    \/DISCARD\/           : { *(.note.*) }\n}\n","old_contents":"\/* \n * Linker script for generating shell-factory targets with -N.\n *\/\nSECTIONS\n{\n    PROVIDE (__executable_start = SEGMENT_START(\"text-segment\", 0x400000));\n    . = SEGMENT_START(\"text-segment\", 0x400000) + SIZEOF_HEADERS;\n\n    \/*\n     * The executable code.\n     *\/\n    .text               : { *(.text .text.* .gnu.linkonce.t.*) }\n    PROVIDE(__etext = .);\n    PROVIDE(_etext = .);\n    PROVIDE(etext = .);\n\n    \/* \n     * Constant data.\n     * Merge into the text section.\n     *\/\n    .rodata             : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n\n    \/*\n     * Non-constant data.\n     * Pushed inside the data segment which should be adjacent to text.\n     *\/\n\n    .data               : { *(.data .data.* .gnu.linkonce.d.*) }\n    PROVIDE(edata = .);\n\n    \/*\n     * Uninitialized data. Bound to the data segment, should not take any space.\n     *\/\n    __bss_start = .;\n    .bss                : { *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) }\n\n    PROVIDE (ebss = .);\n\n    _end = NEXT(4096);\n    PROVIDE (eend = _end);\n\n    \/DISCARD\/           : { *(.note.*) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4d66c384a404d0a537416eeb587a9949a61b33a0","subject":"esp32s2: Fix missed features CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP and CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC","message":"esp32s2: Fix missed features CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP and CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC\n\nDefines the correct size for RTC fast memory (the same as for ESP32).\n\nCloses: IDF-1800\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp32s2\/ld\/esp32s2.ld","new_file":"components\/esp32s2\/ld\/esp32s2.ld","new_contents":"\/* ESP32S2 Linker Script Memory Layout\n\n   This file describes the memory layout (memory blocks) by virtual memory addresses.\n\n   This linker script is passed through the C preprocessor to include configuration options.\n\n   Please use preprocessor features sparingly!\n   Restrict to simple macros with numeric values, and\/or #if\/#endif blocks.\n*\/\n#include \"sdkconfig.h\"\n\n#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC\n#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)\n#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)\n#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)\n#else\n#define ESP_BOOTLOADER_RESERVE_RTC 0\n#endif\n\n#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB\n#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000\n#else\n#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x4000\n#endif\n\n#ifdef CONFIG_ESP32S2_DATA_CACHE_0KB\n#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0\n#elif defined CONFIG_ESP32S2_DATA_CACHE_8KB\n#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000\n#else\n#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x4000\n#endif\n\n#define RAM_IRAM_START    0x40020000\n#define RAM_DRAM_START    0x3FFB0000\n\n#define DATA_RAM_END      0x3FFE4000  \/* 2nd stage bootloader iram_loader_seg starts at block 15 *\/\n\n#define IRAM_ORG    (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define DRAM_ORG    (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define I_D_RAM_SIZE   DATA_RAM_END - DRAM_ORG\n\nMEMORY\n{\n  \/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n  are connected to the data port of the CPU and eg allow bytewise access. *\/\n\n  \/* IRAM for CPU.*\/\n  iram0_0_seg (RX) :                 org = IRAM_ORG, len = I_D_RAM_SIZE\n\n#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Even though the segment name is iram, it is actually mapped to flash\n  *\/\n  iram0_2_seg (RX) :                 org = 0x40080020, len = 0x780000-0x20\n\n  \/*\n    (0x20 offset above is a convenience for the app binary image generation.\n    Flash cache has 64KB pages. The .bin file which is flashed to the chip\n    has a 0x18 byte file header, and each segment has a 0x08 byte segment\n    header. Setting this offset makes it simple to meet the flash cache MMU's\n    constraint that (paddr % 64KB == vaddr % 64KB).)\n  *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n\n  \/* Shared data RAM, excluding memory reserved for bootloader and ROM bss\/data\/stack. *\/\n  dram0_0_seg (RW) :                 org = DRAM_ORG, len = I_D_RAM_SIZE\n\n#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3F000020, len = 0x3f0000-0x20\n\n  \/* (See iram0_2_seg for meaning of 0x20 offset in the above.) *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/* RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x40070000, len = 0x2000\n\n  \/* RTC slow memory (data accessible). Persists over deep sleep.\n\n     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n  *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM\n\n  \/* RTC fast memory (same block as above), viewed from data bus *\/\n  rtc_data_seg(RW) :                 org = 0x3ff9e000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC\n}\n\n_static_data_end = _bss_end;\n\n_heap_end = 0x40000000;\n\n_data_seg_org = ORIGIN(rtc_data_seg);\n\n\/* The lines below define location alias for .rtc.data section based on Kconfig option.\n   When the option is not defined then use slow memory segment\n   else the data will be placed in fast memory segment\n   TODO: check whether the rtc_data_location is correct for esp32s2 - IDF-761 *\/\n#ifndef CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM\nREGION_ALIAS(\"rtc_data_location\", rtc_slow_seg );\n#else\nREGION_ALIAS(\"rtc_data_location\", rtc_data_seg );\n#endif\n\n#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  REGION_ALIAS(\"default_code_seg\", iram0_2_seg);\n#else\n  REGION_ALIAS(\"default_code_seg\", iram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  REGION_ALIAS(\"default_rodata_seg\", drom0_0_seg);\n#else\n  REGION_ALIAS(\"default_rodata_seg\", dram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n","old_contents":"\/* ESP32S2 Linker Script Memory Layout\n\n   This file describes the memory layout (memory blocks) by virtual memory addresses.\n\n   This linker script is passed through the C preprocessor to include configuration options.\n\n   Please use preprocessor features sparingly!\n   Restrict to simple macros with numeric values, and\/or #if\/#endif blocks.\n*\/\n#include \"sdkconfig.h\"\n\n\n#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB\n#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000\n#else\n#define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x4000\n#endif\n\n#ifdef CONFIG_ESP32S2_DATA_CACHE_0KB\n#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0\n#elif defined CONFIG_ESP32S2_DATA_CACHE_8KB\n#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000\n#else\n#define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x4000\n#endif\n\n#define RAM_IRAM_START    0x40020000\n#define RAM_DRAM_START    0x3FFB0000\n\n#define DATA_RAM_END      0x3FFE4000  \/* 2nd stage bootloader iram_loader_seg starts at block 15 *\/\n\n#define IRAM_ORG    (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define DRAM_ORG    (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \\\n                                    + CONFIG_ESP32S2_DATA_CACHE_SIZE)\n\n#define I_D_RAM_SIZE   DATA_RAM_END - DRAM_ORG\n\nMEMORY\n{\n  \/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n  are connected to the data port of the CPU and eg allow bytewise access. *\/\n\n  \/* IRAM for CPU.*\/\n  iram0_0_seg (RX) :                 org = IRAM_ORG, len = I_D_RAM_SIZE\n\n#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Even though the segment name is iram, it is actually mapped to flash\n  *\/\n  iram0_2_seg (RX) :                 org = 0x40080020, len = 0x780000-0x20\n\n  \/*\n    (0x20 offset above is a convenience for the app binary image generation.\n    Flash cache has 64KB pages. The .bin file which is flashed to the chip\n    has a 0x18 byte file header, and each segment has a 0x08 byte segment\n    header. Setting this offset makes it simple to meet the flash cache MMU's\n    constraint that (paddr % 64KB == vaddr % 64KB).)\n  *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n\n  \/* Shared data RAM, excluding memory reserved for bootloader and ROM bss\/data\/stack. *\/\n  dram0_0_seg (RW) :                 org = DRAM_ORG, len = I_D_RAM_SIZE\n\n#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3F000020, len = 0x3f0000-0x20\n\n  \/* (See iram0_2_seg for meaning of 0x20 offset in the above.) *\/\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n  \/* RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x40070000, len = 0x2000\n\n  \/* RTC slow memory (data accessible). Persists over deep sleep.\n\n     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n  *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM\n\n  \/* RTC fast memory (same block as above), viewed from data bus *\/\n  rtc_data_seg(RW) :                 org = 0x3ff9e000, len = 0x2000\n}\n\n_static_data_end = _bss_end;\n\n_heap_end = 0x40000000;\n\n_data_seg_org = ORIGIN(rtc_data_seg);\n\n\/* The lines below define location alias for .rtc.data section based on Kconfig option.\n   When the option is not defined then use slow memory segment\n   else the data will be placed in fast memory segment\n   TODO: check whether the rtc_data_location is correct for esp32s2 - IDF-761 *\/\n#ifndef CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM\nREGION_ALIAS(\"rtc_data_location\", rtc_slow_seg );\n#else\nREGION_ALIAS(\"rtc_data_location\", rtc_data_seg );\n#endif\n\n#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  REGION_ALIAS(\"default_code_seg\", iram0_2_seg);\n#else\n  REGION_ALIAS(\"default_code_seg\", iram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n\n#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n  REGION_ALIAS(\"default_rodata_seg\", drom0_0_seg);\n#else\n  REGION_ALIAS(\"default_rodata_seg\", dram0_0_seg);\n#endif \/\/ CONFIG_APP_BUILD_USE_FLASH_SECTIONS\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4004665fa77d223838d48b0758c90da86170b7eb","subject":"arch: riscv: linker: fix _image_rom_start symbol","message":"arch: riscv: linker: fix _image_rom_start symbol\n\nChange _image_rom_start symbol from 0 to the beginning of\nROMABLE_REGION.\n\nSigned-off-by: Jim Shu <1635390bb889c4cdee38f53a57b0915ac07d9bd9@andestech.com>\n","repos":"finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n#include <linker\/kobject-text.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n\t_image_rodata_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end - _image_rom_start);\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n    __data_ram_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n#include <linker\/kobject-text.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n\t_image_rodata_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end - _image_rom_start);\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n    __data_ram_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"dd82f91ebdb4d207598b4f01f76453d7a86fd2ae","subject":"soc: xtensa: fix missing rodata section in intel_s1000","message":"soc: xtensa: fix missing rodata section in intel_s1000\n\nThe linker script for the intel_s1000 was missing an include for the\nsnippets-rodata.ld file which is needed for any applications using the\n`zephyr_linker_sources(RODATA <linker_script>)` cmake function.\n\nSigned-off-by: Yuval Peress <50dc11c009bd4d7e9d9d15a383c1743ce5ee82ef@google.com>\n","repos":"finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_file":"soc\/xtensa\/intel_s1000\/linker.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include \"memory.h\"\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#include <xtensa\/config\/core-isa.h>\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#define LPRAM_REGION lpram\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LPRAM_BASE,\n\tlen = LPRAM_SIZE\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nPROVIDE(__memctl_default = 0xFFFFFF00);\nPROVIDE(_MemErrorHandler = 0xFFFFFF00);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-through\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-through\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n#ifndef CONFIG_SMP\n_memmap_cacheattr_intel_s1000 = 0x1212fff2;\n#else\n\/*\n * Since there is no cache coherence between cores,\n * set the data section (0xA0000000 - 0xBFFFFFFF) to be\n * non-cacheable, for now. Until we have proper support\n * to manipulate cache lines.\n *\/\n_memmap_cacheattr_intel_s1000 = 0x1222fff2;\n#endif\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    . = CONFIG_ROM_START_OFFSET;\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LPRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_s1000_crb platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include \"memory.h\"\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#include <xtensa\/config\/core-isa.h>\n\n#define RAMABLE_REGION ram :ram_phdr\n#define ROMABLE_REGION ram :ram_phdr\n#define LPRAM_REGION lpram\n\nMEMORY\n{\n  vector_reset_text :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM,\n        len = MEM_RESET_TEXT_SIZE\n  vector_reset_lit :\n        org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,\n        len = MEM_RESET_LIT_SIZE\n  vector_memory_lit :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,\n        len = MEM_ERROR_LIT_SIZE\n  vector_memory_text :\n       \torg = XCHAL_MEMERROR_VECTOR_PADDR,\n        len = MEM_ERROR_TEXT_SIZE\n  vector_base_text :\n       \torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n       \torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n       \torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n       \torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n       \torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n       \torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n       \torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n       \torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n       \torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n       \torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LPRAM_BASE,\n\tlen = LPRAM_SIZE\n}\n\nPHDRS\n{\n  vector_reset_text_phdr PT_LOAD;\n  vector_reset_lit_phdr PT_LOAD;\n  vector_memory_lit_phdr PT_LOAD;\n  vector_memory_text_phdr PT_LOAD;\n  vector_base_text_phdr PT_LOAD;\n  vector_int2_lit_phdr PT_LOAD;\n  vector_int2_text_phdr PT_LOAD;\n  vector_int3_lit_phdr PT_LOAD;\n  vector_int3_text_phdr PT_LOAD;\n  vector_int4_lit_phdr PT_LOAD;\n  vector_int4_text_phdr PT_LOAD;\n  vector_int5_lit_phdr PT_LOAD;\n  vector_int5_text_phdr PT_LOAD;\n  vector_int6_lit_phdr PT_LOAD;\n  vector_int6_text_phdr PT_LOAD;\n  vector_int7_lit_phdr PT_LOAD;\n  vector_int7_text_phdr PT_LOAD;\n  vector_kernel_lit_phdr PT_LOAD;\n  vector_kernel_text_phdr PT_LOAD;\n  vector_user_lit_phdr PT_LOAD;\n  vector_user_text_phdr PT_LOAD;\n  vector_double_lit_phdr PT_LOAD;\n  vector_double_text_phdr PT_LOAD;\n  ram_phdr PT_LOAD;\n}\n_rom_store_table = 0;\nPROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);\n\nPROVIDE(__memctl_default = 0xFFFFFF00);\nPROVIDE(_MemErrorHandler = 0xFFFFFF00);\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x44024000;\n_memmap_cacheattr_wt_base = 0x11021000;\n_memmap_cacheattr_bp_base = 0x22022000;\n_memmap_cacheattr_unused_mask = 0x00F00FFF;\n_memmap_cacheattr_wb_trapnull = 0x4422422F;\n_memmap_cacheattr_wba_trapnull = 0x4422422F;\n_memmap_cacheattr_wbna_trapnull = 0x25222222;\n_memmap_cacheattr_wt_trapnull = 0x1122122F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0x44F24FFF;\n_memmap_cacheattr_wt_strict = 0x11F21FFF;\n_memmap_cacheattr_bp_strict = 0x22F22FFF;\n_memmap_cacheattr_wb_allvalid = 0x44224222;\n_memmap_cacheattr_wt_allvalid = 0x11221222;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\n\n\/*\n * Cache attributes for memory addresses:\n * (Each 4 bits correspond to 512MB of memory)\n *\n * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache\n *                                         (region for hardware registers)\n * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access\n * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access\n * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access\n * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache\n * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-through\n * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache\n * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-through\n *\n * Note that this is both for instruction and data caches,\n * as cacheattr_set macro sets them both to the same set of\n * attributes.\n *\/\n#ifndef CONFIG_SMP\n_memmap_cacheattr_intel_s1000 = 0x1212fff2;\n#else\n\/*\n * Since there is no cache coherence between cores,\n * set the data section (0xA0000000 - 0xBFFFFFFF) to be\n * non-cacheable, for now. Until we have proper support\n * to manipulate cache lines.\n *\/\n_memmap_cacheattr_intel_s1000 = 0x1222fff2;\n#endif\n\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  .ResetVector.text : ALIGN(4)\n  {\n    . = CONFIG_ROM_START_OFFSET;\n    _ResetVector_text_start = ABSOLUTE(.);\n    KEEP (*(.ResetVector.text))\n    _ResetVector_text_end = ABSOLUTE(.);\n  } >vector_reset_text :vector_reset_text_phdr\n  .ResetVector.literal : ALIGN(4)\n  {\n    _ResetVector_literal_start = ABSOLUTE(.);\n    *(.ResetVector.literal)\n    _ResetVector_literal_end = ABSOLUTE(.);\n  } >vector_reset_lit :vector_reset_lit_phdr\n .MemoryExceptionVector.literal : ALIGN(4)\n  {\n    _MemoryExceptionVector_literal_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.literal))\n    _MemoryExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_memory_lit :vector_memory_lit_phdr\n  .MemoryExceptionVector.text : ALIGN(4)\n  {\n    _MemoryExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.MemoryExceptionVector.text))\n    _MemoryExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_memory_text :vector_memory_text_phdr\n   .WindowVectors.text : ALIGN(4)\n  {\n    _WindowVectors_text_start = ABSOLUTE(.);\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = ABSOLUTE(.);\n  } >vector_base_text :vector_base_text_phdr\n  .Level2InterruptVector.literal : ALIGN(4)\n  {\n    _Level2InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int2_lit :vector_int2_lit_phdr\n  .Level2InterruptVector.text : ALIGN(4)\n  {\n    _Level2InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int2_text :vector_int2_text_phdr\n  .Level3InterruptVector.literal : ALIGN(4)\n  {\n    _Level3InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int3_lit :vector_int3_lit_phdr\n  .Level3InterruptVector.text : ALIGN(4)\n  {\n    _Level3InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int3_text :vector_int3_text_phdr\n  .Level4InterruptVector.literal : ALIGN(4)\n  {\n    _Level4InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int4_lit :vector_int4_lit_phdr\n  .Level4InterruptVector.text : ALIGN(4)\n  {\n    _Level4InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int4_text :vector_int4_text_phdr\n  .Level5InterruptVector.literal : ALIGN(4)\n  {\n    _Level5InterruptVector_literal_start = ABSOLUTE(.);\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = ABSOLUTE(.);\n  } >vector_int5_lit :vector_int5_lit_phdr\n  .Level5InterruptVector.text : ALIGN(4)\n  {\n    _Level5InterruptVector_text_start = ABSOLUTE(.);\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = ABSOLUTE(.);\n  } >vector_int5_text :vector_int5_text_phdr\n  .DebugExceptionVector.literal : ALIGN(4)\n  {\n    _DebugExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int6_lit :vector_int6_lit_phdr\n  .DebugExceptionVector.text : ALIGN(4)\n  {\n    _DebugExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int6_text :vector_int6_text_phdr\n  .NMIExceptionVector.literal : ALIGN(4)\n  {\n    _NMIExceptionVector_literal_start = ABSOLUTE(.);\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_int7_lit :vector_int7_lit_phdr\n  .NMIExceptionVector.text : ALIGN(4)\n  {\n    _NMIExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_int7_text :vector_int7_text_phdr\n  .KernelExceptionVector.literal : ALIGN(4)\n  {\n    _KernelExceptionVector_literal_start = ABSOLUTE(.);\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_kernel_lit :vector_kernel_lit_phdr\n  .KernelExceptionVector.text : ALIGN(4)\n  {\n    _KernelExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_kernel_text :vector_kernel_text_phdr\n  .UserExceptionVector.literal : ALIGN(4)\n  {\n    _UserExceptionVector_literal_start = ABSOLUTE(.);\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_user_lit :vector_user_lit_phdr\n  .UserExceptionVector.text : ALIGN(4)\n  {\n    _UserExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_user_text :vector_user_text_phdr\n  .DoubleExceptionVector.literal : ALIGN(4)\n  {\n    _DoubleExceptionVector_literal_start = ABSOLUTE(.);\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = ABSOLUTE(.);\n  } >vector_double_lit :vector_double_lit_phdr\n  .DoubleExceptionVector.text : ALIGN(4)\n  {\n    _DoubleExceptionVector_text_start = ABSOLUTE(.);\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = ABSOLUTE(.);\n  } >vector_double_text :vector_double_text_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >ram :ram_phdr\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n  .noinit :  ALIGN(4)\n  {\n    *(.noinit)\n    *(.noinit.*)\n  } >ram :ram_phdr\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    . = ALIGN(4096);\n    *(.gna_model)\n    _data_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table :\n  {\n    *(.tm_clone_table)\n  } >ram :ram_phdr\n\n  .bss (NOLOAD) : ALIGN(8)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >ram :ram_phdr\n\n  \/* stack *\/\n  _end = ALIGN(8);\n  PROVIDE(end = ALIGN(8));\n  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): ALIGN(4)\n  {\n    _dma_buf_start = ABSOLUTE(.);\n    *(.dma_buffers)\n    _dma_buf_end = ABSOLUTE(.);\n  } >LPRAM_REGION\n  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;\n  .comment  0 :  { *(.comment) }\n  .debug 0 : { *(.debug) }\n  .line 0 : { *(.line) }\n  .debug_srcinfo 0 : { *(.debug_srcinfo) }\n  .debug_sfnames 0 : { *(.debug_sfnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_frame 0 : { *(.debug_frame) }\n  .debug_str 0 : { *(.debug_str) }\n  .debug_loc 0 : { *(.debug_loc) }\n  .debug_macinfo 0 : { *(.debug_macinfo) }\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames 0 : { *(.debug_varnames) }\n  .debug_ranges  0 :  { *(.debug_ranges) }\n  .xtensa.info  0 :  { *(.xtensa.info) }\n  .xt.insn 0 :\n  {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 :\n  {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 :\n  {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 :\n  {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 :\n  {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 :\n  {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"154b59337b0b883702967d9c168fccb448467c43","subject":"templates.stm: f7 mem320.ld","message":"templates.stm: f7 mem320.ld\n","repos":"gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins,gnuarmeclipse\/plug-ins","old_file":"ilg.gnuarmeclipse.templates.stm\/templates\/stm32f7xx_exe_c_project\/ldscripts\/mem320.ld","new_file":"ilg.gnuarmeclipse.templates.stm\/templates\/stm32f7xx_exe_c_project\/ldscripts\/mem320.ld","new_contents":"\/*\n * Memory Spaces Definitions.\n *\n * Need modifying for a specific board.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\n * The values below can be addressed in further linker scripts\n * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\n *\/\n\nMEMORY\n{\n  \/*\n   * DTCM 64K, SRAM1 240K, SRAM2 16K\n   *\/\n  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K\n  CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 0\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = $(STM32F7flashSize)K\n  FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n}\n\n\/*\n * For external ram use something like:\n\n   RAM (xrw) : ORIGIN = 0x64000000, LENGTH = 2048K\n\n *\/\n","old_contents":"\/*\n * Memory Spaces Definitions.\n *\n * Need modifying for a specific board.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\n * The values below can be addressed in further linker scripts\n * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\n *\/\n\nMEMORY\n{\n  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K\n  CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = $(STM32F7flashSize)K\n  FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0\n  MEMORY_ARRAY (xrw)  : ORIGIN = 0x20002000, LENGTH = 32\n}\n\n\/*\n * For external ram use something like:\n\n   RAM (xrw) : ORIGIN = 0x64000000, LENGTH = 2048K\n\n *\/\n","returncode":0,"stderr":"","license":"epl-1.0","lang":"Linker Script"}
{"commit":"77f3a8f7f59b9037961886f6d871603c2d5abce7","subject":"fix linking mbed binaries.","message":"fix linking mbed binaries.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/nxp-lpc1768-mbed-tch\/target.ld","new_file":"boards\/nxp-lpc1768-mbed-tch\/target.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\nGROUP(\n libgcc.a\n libc.a\n libstdc++.a\n libm.a\n \/*libcr_newlib_nohost.a*\/\n \/*crti.o\n crtn.o\n crtbegin.o\n crtend.o*\/\n )\n\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  \/*ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K*\/\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 32K\n}\n\n\/* Set stack top to end of RAM, and stack limit move down by      \n * size of stack_dummy section *\/\n__cs3_heap_end = ORIGIN(RAM) + LENGTH(RAM);\n__StackTop = ORIGIN( USB_RAM ) + LENGTH( USB_RAM );\n__StackLimit = __StackTop - 0x200;\nPROVIDE(__stack = __StackTop);\n\/* This marks the highest allocatable stack space *\/\n__stacks_min__ = __StackLimit ;\n\n\/*__USBRAM_segment_start__  = ORIGIN( USB_RAM );*\/\n__USBRAM_segment_start__  = __bss_end__;\n__USBRAM_segment_end__    = __StackLimit; \/*ORIGIN( USB_RAM ) + LENGTH( USB_RAM );*\/\n_sym_use_separate_stack_segment = 2; \/* false *\/\n\/* This should not be used on the mbed -- will crash immediately. *\/\n__ETHRAM_segment_start__  = 0xFFFF0000;\n\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(SORT(.rodata*))\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > USB_RAM\n\n    __data_init_start__ = LOADADDR( .data ) ;\n    ASSERT(__data_init_start__ == __etext, \"Initialized data source inconsistent\")\n        \n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > USB_RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n        __cs3_heap_start = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\nGROUP(\n libgcc.a\n libc.a\n libstdc++.a\n libm.a\n \/*libcr_newlib_nohost.a*\/\n \/*crti.o\n crtn.o\n crtbegin.o\n crtend.o*\/\n )\n\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  \/*ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K*\/\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 32K\n}\n\n\/*  XX__ETHRAM_segment_start__  = ORIGIN( ETH_RAM );*\/\n\n\/* Set stack top to end of RAM, and stack limit move down by      \n * size of stack_dummy section *\/\n__cs3_heap_end = ORIGIN(RAM) + LENGTH(RAM);\n__StackTop = ORIGIN( USB_RAM ) + LENGTH( USB_RAM );\n__StackLimit = __StackTop - 0x200;\nPROVIDE(__stack = __StackTop);\n\/* This marks the highest allocatable stack space *\/\n__stacks_min__ = __StackLimit ;\n\n\/*__USBRAM_segment_start__  = ORIGIN( USB_RAM );*\/\n__USBRAM_segment_start__  = __bss_end__;\n__USBRAM_segment_end__    = __StackLimit; \/*ORIGIN( USB_RAM ) + LENGTH( USB_RAM );*\/\n_sym_use_separate_stack_segment = 2; \/* false *\/\n\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(SORT(.rodata*))\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n\t\/* this magic is needed for the device tables of openMRN *\/\n        . = ALIGN (8);\n        KEEP(*( SORT (.device.table.*))) ;\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > USB_RAM\n\n    __data_init_start__ = LOADADDR( .data ) ;\n    ASSERT(__data_init_start__ == __etext, \"Initialized data source inconsistent\")\n        \n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > USB_RAM\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n        __cs3_heap_start = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"f1ad829890495659ca69f30913e9372e2767cff2","subject":"Pin the reflection data sections on Linux","message":"Pin the reflection data sections on Linux\n\nThese had similar problems to the protocol conformance sections during\nLinux bringup. There are relative offsets from the main reflection\nsection to the two string sections, so their position relative to each\nother must remain fixed.\n","repos":"JGiola\/swift,huonw\/swift,tkremenek\/swift,harlanhaskins\/swift,austinzheng\/swift,hughbe\/swift,apple\/swift,tardieu\/swift,kperryua\/swift,gmilos\/swift,roambotics\/swift,sschiau\/swift,devincoughlin\/swift,austinzheng\/swift,frootloops\/swift,atrick\/swift,natecook1000\/swift,shajrawi\/swift,dduan\/swift,manavgabhawala\/swift,SwiftAndroid\/swift,modocache\/swift,glessard\/swift,gregomni\/swift,KrishMunot\/swift,uasys\/swift,atrick\/swift,jckarter\/swift,gmilos\/swift,benlangmuir\/swift,gribozavr\/swift,gottesmm\/swift,swiftix\/swift,brentdax\/swift,natecook1000\/swift,gmilos\/swift,codestergit\/swift,lorentey\/swift,arvedviehweger\/swift,hooman\/swift,jtbandes\/swift,ken0nek\/swift,devincoughlin\/swift,russbishop\/swift,hughbe\/swift,dduan\/swift,alblue\/swift,uasys\/swift,bitjammer\/swift,aschwaighofer\/swift,calebd\/swift,jckarter\/swift,ahoppen\/swift,swiftix\/swift,tjw\/swift,nathawes\/swift,therealbnut\/swift,airspeedswift\/swift,nathawes\/swift,aschwaighofer\/swift,CodaFi\/swift,deyton\/swift,rudkx\/swift,jtbandes\/swift,xedin\/swift,apple\/swift,johnno1962d\/swift,airspeedswift\/swift,ken0nek\/swift,lorentey\/swift,brentdax\/swift,airspeedswift\/swift,amraboelela\/swift,arvedviehweger\/swift,alblue\/swift,airspeedswift\/swift,shahmishal\/swift,glessard\/swift,codestergit\/swift,tardieu\/swift,felix91gr\/swift,sschiau\/swift,allevato\/swift,ben-ng\/swift,return\/swift,austinzheng\/swift,jmgc\/swift,return\/swift,nathawes\/swift,felix91gr\/swift,swiftix\/swift,felix91gr\/swift,sschiau\/swift,amraboelela\/swift,johnno1962d\/swift,therealbnut\/swift,alblue\/swift,Jnosh\/swift,austinzheng\/swift,zisko\/swift,practicalswift\/swift,arvedviehweger\/swift,CodaFi\/swift,OscarSwanros\/swift,milseman\/swift,IngmarStein\/swift,manavgabhawala\/swift,swiftix\/swift,rudkx\/swift,xedin\/swift,shahmishal\/swift,bitjammer\/swift,jmgc\/swift,modocache\/swift,xedin\/swift,JGiola\/swift,milseman\/swift,OscarSwanros\/swift,ben-ng\/swift,shajrawi\/swift,ben-ng\/swift,glessard\/swift,benlangmuir\/swift,lorentey\/swift,hughbe\/swift,frootloops\/swift,dduan\/swift,modocache\/swift,stephentyrone\/swift,brentdax\/swift,karwa\/swift,gribozavr\/swift,gribozavr\/swift,milseman\/swift,deyton\/swift,brentdax\/swift,jmgc\/swift,johnno1962d\/swift,parkera\/swift,allevato\/swift,hughbe\/swift,ken0nek\/swift,hooman\/swift,kperryua\/swift,jopamer\/swift,frootloops\/swift,tkremenek\/swift,return\/swift,hooman\/swift,uasys\/swift,practicalswift\/swift,atrick\/swift,hughbe\/swift,xwu\/swift,xedin\/swift,djwbrown\/swift,gmilos\/swift,roambotics\/swift,IngmarStein\/swift,hooman\/swift,rudkx\/swift,nathawes\/swift,rudkx\/swift,calebd\/swift,ahoppen\/swift,tinysun212\/swift-windows,aschwaighofer\/swift,jopamer\/swift,OscarSwanros\/swift,gribozavr\/swift,apple\/swift,jckarter\/swift,milseman\/swift,JaSpa\/swift,shahmishal\/swift,karwa\/swift,gottesmm\/swift,felix91gr\/swift,jtbandes\/swift,bitjammer\/swift,huonw\/swift,alblue\/swift,swiftix\/swift,modocache\/swift,OscarSwanros\/swift,IngmarStein\/swift,xwu\/swift,tjw\/swift,CodaFi\/swift,JGiola\/swift,ken0nek\/swift,JGiola\/swift,djwbrown\/swift,ben-ng\/swift,harlanhaskins\/swift,harlanhaskins\/swift,return\/swift,KrishMunot\/swift,amraboelela\/swift,roambotics\/swift,benlangmuir\/swift,aschwaighofer\/swift,huonw\/swift,hughbe\/swift,therealbnut\/swift,alblue\/swift,alblue\/swift,felix91gr\/swift,russbishop\/swift,tjw\/swift,lorentey\/swift,kstaring\/swift,devincoughlin\/swift,natecook1000\/swift,SwiftAndroid\/swift,atrick\/swift,brentdax\/swift,codestergit\/swift,manavgabhawala\/swift,gottesmm\/swift,jckarter\/swift,benlangmuir\/swift,manavgabhawala\/swift,karwa\/swift,glessard\/swift,modocache\/swift,russbishop\/swift,alblue\/swift,SwiftAndroid\/swift,tjw\/swift,natecook1000\/swift,bitjammer\/swift,SwiftAndroid\/swift,codestergit\/swift,deyton\/swift,xedin\/swift,shahmishal\/swift,parkera\/swift,gregomni\/swift,devincoughlin\/swift,JaSpa\/swift,slavapestov\/swift,deyton\/swift,felix91gr\/swift,dreamsxin\/swift,tardieu\/swift,zisko\/swift,jopamer\/swift,kstaring\/swift,tinysun212\/swift-windows,therealbnut\/swift,kstaring\/swift,uasys\/swift,huonw\/swift,manavgabhawala\/swift,austinzheng\/swift,frootloops\/swift,stephentyrone\/swift,uasys\/swift,tinysun212\/swift-windows,huonw\/swift,jmgc\/swift,practicalswift\/swift,arvedviehweger\/swift,KrishMunot\/swift,ken0nek\/swift,ken0nek\/swift,dduan\/swift,gottesmm\/swift,CodaFi\/swift,tjw\/swift,stephentyrone\/swift,lorentey\/swift,danielmartin\/swift,deyton\/swift,KrishMunot\/swift,roambotics\/swift,zisko\/swift,return\/swift,CodaFi\/swift,tardieu\/swift,parkera\/swift,gribozavr\/swift,slavapestov\/swift,amraboelela\/swift,shahmishal\/swift,KrishMunot\/swift,zisko\/swift,tkremenek\/swift,karwa\/swift,xwu\/swift,hooman\/swift,jtbandes\/swift,gribozavr\/swift,gottesmm\/swift,harlanhaskins\/swift,Jnosh\/swift,tinysun212\/swift-windows,deyton\/swift,russbishop\/swift,danielmartin\/swift,modocache\/swift,swiftix\/swift,roambotics\/swift,karwa\/swift,OscarSwanros\/swift,KrishMunot\/swift,kstaring\/swift,milseman\/swift,ben-ng\/swift,gregomni\/swift,shajrawi\/swift,deyton\/swift,tinysun212\/swift-windows,IngmarStein\/swift,tinysun212\/swift-windows,hooman\/swift,aschwaighofer\/swift,parkera\/swift,xedin\/swift,harlanhaskins\/swift,hughbe\/swift,amraboelela\/swift,ahoppen\/swift,jtbandes\/swift,jckarter\/swift,therealbnut\/swift,codestergit\/swift,danielmartin\/swift,SwiftAndroid\/swift,airspeedswift\/swift,parkera\/swift,xwu\/swift,johnno1962d\/swift,jckarter\/swift,tardieu\/swift,IngmarStein\/swift,KrishMunot\/swift,slavapestov\/swift,parkera\/swift,return\/swift,jopamer\/swift,uasys\/swift,therealbnut\/swift,parkera\/swift,rudkx\/swift,jopamer\/swift,devincoughlin\/swift,kperryua\/swift,practicalswift\/swift,amraboelela\/swift,atrick\/swift,lorentey\/swift,bitjammer\/swift,CodaFi\/swift,practicalswift\/swift,stephentyrone\/swift,gribozavr\/swift,dduan\/swift,devincoughlin\/swift,airspeedswift\/swift,ahoppen\/swift,karwa\/swift,jmgc\/swift,kperryua\/swift,tjw\/swift,natecook1000\/swift,austinzheng\/swift,frootloops\/swift,airspeedswift\/swift,harlanhaskins\/swift,danielmartin\/swift,milseman\/swift,sschiau\/swift,huonw\/swift,bitjammer\/swift,djwbrown\/swift,tinysun212\/swift-windows,calebd\/swift,tkremenek\/swift,Jnosh\/swift,arvedviehweger\/swift,milseman\/swift,kperryua\/swift,gmilos\/swift,djwbrown\/swift,slavapestov\/swift,tjw\/swift,lorentey\/swift,roambotics\/swift,tkremenek\/swift,uasys\/swift,russbishop\/swift,devincoughlin\/swift,JaSpa\/swift,djwbrown\/swift,amraboelela\/swift,shajrawi\/swift,tkremenek\/swift,zisko\/swift,glessard\/swift,Jnosh\/swift,gregomni\/swift,glessard\/swift,danielmartin\/swift,ben-ng\/swift,kstaring\/swift,gregomni\/swift,danielmartin\/swift,codestergit\/swift,xwu\/swift,nathawes\/swift,manavgabhawala\/swift,slavapestov\/swift,ahoppen\/swift,jmgc\/swift,arvedviehweger\/swift,JaSpa\/swift,danielmartin\/swift,manavgabhawala\/swift,ben-ng\/swift,IngmarStein\/swift,calebd\/swift,sschiau\/swift,natecook1000\/swift,shahmishal\/swift,zisko\/swift,benlangmuir\/swift,russbishop\/swift,sschiau\/swift,devincoughlin\/swift,apple\/swift,stephentyrone\/swift,allevato\/swift,SwiftAndroid\/swift,SwiftAndroid\/swift,djwbrown\/swift,nathawes\/swift,xwu\/swift,jmgc\/swift,sschiau\/swift,johnno1962d\/swift,apple\/swift,ahoppen\/swift,Jnosh\/swift,calebd\/swift,gmilos\/swift,shajrawi\/swift,stephentyrone\/swift,brentdax\/swift,jckarter\/swift,dduan\/swift,shahmishal\/swift,bitjammer\/swift,aschwaighofer\/swift,allevato\/swift,nathawes\/swift,kstaring\/swift,JGiola\/swift,arvedviehweger\/swift,jtbandes\/swift,dreamsxin\/swift,JaSpa\/swift,lorentey\/swift,jopamer\/swift,dduan\/swift,felix91gr\/swift,xedin\/swift,practicalswift\/swift,aschwaighofer\/swift,brentdax\/swift,gmilos\/swift,sschiau\/swift,codestergit\/swift,frootloops\/swift,parkera\/swift,tardieu\/swift,johnno1962d\/swift,gregomni\/swift,return\/swift,tkremenek\/swift,gottesmm\/swift,djwbrown\/swift,JaSpa\/swift,benlangmuir\/swift,shajrawi\/swift,Jnosh\/swift,huonw\/swift,jopamer\/swift,therealbnut\/swift,atrick\/swift,allevato\/swift,Jnosh\/swift,IngmarStein\/swift,kperryua\/swift,xedin\/swift,ken0nek\/swift,shahmishal\/swift,allevato\/swift,shajrawi\/swift,kstaring\/swift,gottesmm\/swift,apple\/swift,stephentyrone\/swift,CodaFi\/swift,calebd\/swift,johnno1962d\/swift,austinzheng\/swift,JGiola\/swift,practicalswift\/swift,OscarSwanros\/swift,frootloops\/swift,shajrawi\/swift,calebd\/swift,swiftix\/swift,slavapestov\/swift,allevato\/swift,JaSpa\/swift,hooman\/swift,OscarSwanros\/swift,gribozavr\/swift,zisko\/swift,natecook1000\/swift,jtbandes\/swift,russbishop\/swift,xwu\/swift,kperryua\/swift,slavapestov\/swift,modocache\/swift,tardieu\/swift,rudkx\/swift,karwa\/swift,karwa\/swift,practicalswift\/swift,harlanhaskins\/swift","old_file":"stdlib\/public\/runtime\/swift.ld","new_file":"stdlib\/public\/runtime\/swift.ld","new_contents":"SECTIONS\n{\n  .swift3_typeref : { *(.swift3_typeref) },\n  .swift3_reflstr : { *(.swift3_reflstr) },\n  .swift3_reflect : { *(.swift3_reflect) },\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","old_contents":"SECTIONS\n{\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"85b166adaef17836ffe18a475833662e26e655c6","subject":"Some changes in linker.ld","message":"Some changes in linker.ld\n","repos":"Mrokkk\/objective-kernel,Mrokkk\/objective-kernel","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(_start)\n\n__kernel_phys = 0x00100000;\n__kernel_virt = 0xC0100000;\n\n__kernel_offset = __kernel_virt - __kernel_phys;\n\nSECTIONS {\n\n    . = __kernel_phys;\n\n    .unpagged BLOCK(4K) : ALIGN(4K) {\n        __unpagged_start = .;\n        KEEP(*(.multiboot))\n        KEEP(*(.text.boot))\n        __unpagged_end = .;\n    }\n\n    .text BLOCK(4K) : ALIGN(4K) {\n        __text_start = .;\n        *(.text)\n        __text_end = .;\n    }\n\n    .rodata BLOCK(4K) : ALIGN(4K) {\n        *(.rodata)\n    }\n\n    .preinit_array : {\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP (*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n    }\n\n    .init_array : {\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n        KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n        PROVIDE_HIDDEN (__init_array_end = .);\n    }\n\n    .fini_array : {\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n        KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n    }\n\n    .data BLOCK(4K) : ALIGN(4K) {\n        __data_start = .;\n        *(.data)\n        __data_end = .;\n    }\n\n    .bss BLOCK(4K) : ALIGN(4K) {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.stack)\n        __bss_end = .;\n    }\n\n    . = ALIGN(4K);\n\n    __heap_start = .;\n\n}\n\n","old_contents":"ENTRY(_start)\n\nSECTIONS {\n\n    . = 1M;\n\n    .unpagged BLOCK(4K) : ALIGN(4K) {\n        __unpagged_start = .;\n        KEEP(*(.multiboot))\n        KEEP(*(.text.boot))\n        __unpagged_end = .;\n    }\n\n    .text BLOCK(4K) : ALIGN(4K) {\n        __text_start = .;\n        *(.text)\n        __text_end = .;\n    }\n\n    .rodata BLOCK(4K) : ALIGN(4K) {\n        *(.rodata)\n    }\n\n    .preinit_array : {\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP (*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n    }\n\n    .init_array : {\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n        KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n        PROVIDE_HIDDEN (__init_array_end = .);\n    }\n\n    .fini_array : {\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n        KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n    }\n\n    .data BLOCK(4K) : ALIGN(4K) {\n        __data_start = .;\n        *(.data)\n        __data_end = .;\n    }\n\n    .bss BLOCK(4K) : ALIGN(4K) {\n        __bss_start = .;\n        *(COMMON)\n        *(.bss)\n        *(.stack)\n        __bss_end = .;\n    }\n\n    . = ALIGN(4K);\n\n    __heap_start = .;\n\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8b61c40fc8a14289d5f2e03322d42963c0fcbc23","subject":"cpu\/esp32: add .noinit section to linker script","message":"cpu\/esp32: add .noinit section to linker script\n\n","repos":"kaspar030\/RIOT,kYc0o\/RIOT,OTAkeys\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,smlng\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,smlng\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,smlng\/RIOT,basilfx\/RIOT,ant9000\/RIOT,basilfx\/RIOT,smlng\/RIOT,miri64\/RIOT,authmillenon\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,basilfx\/RIOT,yogo1212\/RIOT,yogo1212\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,kYc0o\/RIOT,smlng\/RIOT,jasonatran\/RIOT,yogo1212\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,kYc0o\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,basilfx\/RIOT,OlegHahm\/RIOT,ant9000\/RIOT","old_file":"cpu\/esp32\/ld\/esp32.common.ld","new_file":"cpu\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* This section holds data that should not be initialized at power up\n     and will be retained during deep sleep. The section located in\n     RTC SLOW Memory area. User data marked with RTC_NOINIT_ATTR will be placed\n     into this section. See the file \"esp_attr.h\" for more information.\n  *\/\n  .rtc.noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _rtc_noinit_start = ABSOLUTE(.);\n    *(.rtc_noinit .rtc_noinit.*)\n    . = ALIGN(4) ;\n    _rtc_noinit_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *littlefs.a:*(.literal .text .literal.* .text.*)\n    *littlefs2.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* This section holds data that should not be initialized at power up.\n     The section located in Internal SRAM memory region. The macro _NOINIT\n     can be used as attribute to place data into this section.\n     See the esp_attr.h file for more information.\n  *\/\n  .noinit (NOLOAD):\n  {\n    . = ALIGN(4);\n    _noinit_start = ABSOLUTE(.);\n    __noinit_start = ABSOLUTE(.);\n    *(.noinit .noinit.*)\n    . = ALIGN(4) ;\n    _noinit_end = ABSOLUTE(.);\n    __noinit_end = ABSOLUTE(.);\n  } > dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    \/* part that is initialized if not waking up from deep sleep *\/\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n    \/* part that saves some data for rtc periph module, this part is\n       only initialized at power on reset *\/\n    _rtc_bss_rtc_start = ABSOLUTE(.);\n    *(.rtc.bss .rtc.bss.*)\n    _rtc_bss_rtc_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(**(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n    \/* *libc.a:(.literal .text .literal.* .text.*) *\/\n\n    \/* Xtensa basic functionality written in assembler should be placed in iram *\/\n    *xtensa.a:*(.literal .text .literal.* .text.*)\n    \/* ESP-IDF parts that have to run in IRAM *\/\n    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)\n    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)\n    \/* parts of RIOT that should to run in IRAM *\/\n    *core.a:*(.literal .text .literal.* .text.*)\n    *littlefs.a:*(.literal .text .literal.* .text.*)\n    *littlefs2.a:*(.literal .text .literal.* .text.*)\n    *spiffs_fs.a:*(.literal .text .literal.* .text.*)\n    *spiffs.a:*(.literal .text .literal.* .text.*)\n    *vfs.a:*(.literal .text .literal.* .text.*)\n\n    \/* part of the RIOT port that should run in IRAM *\/\n    *cpu.a:*(.literal .text .literal.* .text.*)\n    *periph.a:*(.literal .text .literal.* .text.*)\n    *mtd.a:**(.literal .text .literal.* .text.*)\n\n    INCLUDE esp32.spiram.rom-functions-iram.ld\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    *libsoc.a:rtc_clk.o(.rodata .rodata.*)\n    *libapp_trace.a:(.rodata .rodata.*)\n    *libgcov.a:(.rodata .rodata.*)\n    *libheap.a:multi_heap.o(.rodata .rodata.*)\n    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)\n    INCLUDE esp32.spiram.rom-functions-dram.ld\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n    _sheap = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  \/* TODO HEAP handling when BT is used\n     ETS system memory seems to start at 0x3FFE0000 if BT is not used.\n     This is the top of the heap for the app *\/\n    . = 0x3FFE0000;\n  _heap_top = ABSOLUTE(.);\n  _eheap = ABSOLUTE(.);\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table .gcc_except_table.*)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    . = (. + 3) & ~ 3;\n    __eh_frame = ABSOLUTE(.);\n    KEEP(*(.eh_frame))\n    . = (. + 7) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _thread_local_start = ABSOLUTE(.);\n    *(.tdata)\n    *(.tdata.*)\n    *(.tbss)\n    *(.tbss.*)\n    _thread_local_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    \/* place everything else in iram0_2_seg (cached ROM) *\/\n    *(.literal .text .literal.* .text.* .stub)\n    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"3581deec816ff88a7dc2c0274b7c60b11e4ade34","subject":"stm32\/boards\/PYBD_SF2: Put mbedtls library code in external QSPI flash.","message":"stm32\/boards\/PYBD_SF2: Put mbedtls library code in external QSPI flash.\n\nmbedtls is large and self contained so is a good candidate to be in\nexternal XIP flash, to keep enough spare ROM in internal flash.\n","repos":"pfalcon\/micropython,pozetroninc\/micropython,MrSurly\/micropython,pramasoul\/micropython,adafruit\/circuitpython,henriknelson\/micropython,bvernoux\/micropython,pramasoul\/micropython,tobbad\/micropython,pramasoul\/micropython,bvernoux\/micropython,MrSurly\/micropython,pfalcon\/micropython,henriknelson\/micropython,tobbad\/micropython,selste\/micropython,trezor\/micropython,trezor\/micropython,adafruit\/circuitpython,MrSurly\/micropython,trezor\/micropython,trezor\/micropython,pfalcon\/micropython,bvernoux\/micropython,adafruit\/circuitpython,kerneltask\/micropython,pramasoul\/micropython,tobbad\/micropython,henriknelson\/micropython,adafruit\/circuitpython,selste\/micropython,selste\/micropython,pramasoul\/micropython,pozetroninc\/micropython,kerneltask\/micropython,bvernoux\/micropython,kerneltask\/micropython,tobbad\/micropython,MrSurly\/micropython,trezor\/micropython,adafruit\/circuitpython,tobbad\/micropython,kerneltask\/micropython,selste\/micropython,henriknelson\/micropython,pfalcon\/micropython,pozetroninc\/micropython,bvernoux\/micropython,kerneltask\/micropython,adafruit\/circuitpython,MrSurly\/micropython,pfalcon\/micropython,pozetroninc\/micropython,selste\/micropython,henriknelson\/micropython,pozetroninc\/micropython","old_file":"ports\/stm32\/boards\/PYBD_SF2\/f722_qspi.ld","new_file":"ports\/stm32\/boards\/PYBD_SF2\/f722_qspi.ld","new_contents":"\/*\n    Linker script for PYBD with STM32F722\/STM32F723\/STM32F732\/STM32F733\n\n    Memory layout for mboot configuration (this here describes the app part):\n\n    FLASH_APP   .isr_vector\n    FLASH_APP   .text\n    FLASH_APP   .data\n\n    FLASH_EXT   .big_const\n\n    RAM         .data\n    RAM         .bss\n    RAM         .heap\n    RAM         .stack\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 32K     \/* sectors 0,1 *\/\n    FLASH_APP (rx)  : ORIGIN = 0x08008000, LENGTH = 480K    \/* sectors 2-7 *\/\n    FLASH_EXT (rx)  : ORIGIN = 0x90000000, LENGTH = 2048K   \/* external QSPI *\/\n    RAM (rwx)       : ORIGIN = 0x20000000, LENGTH = 256K    \/* DTCM+SRAM1+SRAM2 *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K;\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n\nENTRY(Reset_Handler)\n\n\/* Define output sections *\/\nSECTIONS\n{\n    .text_ext :\n    {\n        . = ALIGN(4);\n        *lib\/mbedtls\/*(.text* .rodata*)\n        . = ALIGN(512);\n        *(.big_const*)\n        . = ALIGN(4);\n    } >FLASH_EXT\n\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n    } >FLASH_APP\n\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        _etext = .;\n    } >FLASH_APP\n\n    _sidata = LOADADDR(.data);\n\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.data*)\n\n        . = ALIGN(4);\n        _edata = .;\n    } >RAM AT> FLASH_APP\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n    } >RAM\n\n    .heap :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_heap_size;\n        . = ALIGN(4);\n    } >RAM\n\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n}\n","old_contents":"\/*\n    Linker script for PYBD with STM32F722\/STM32F723\/STM32F732\/STM32F733\n\n    Memory layout for mboot configuration (this here describes the app part):\n\n    FLASH_APP   .isr_vector\n    FLASH_APP   .text\n    FLASH_APP   .data\n\n    FLASH_EXT   .big_const\n\n    RAM         .data\n    RAM         .bss\n    RAM         .heap\n    RAM         .stack\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 32K     \/* sectors 0,1 *\/\n    FLASH_APP (rx)  : ORIGIN = 0x08008000, LENGTH = 480K    \/* sectors 2-7 *\/\n    FLASH_EXT (rx)  : ORIGIN = 0x90000000, LENGTH = 2048K   \/* external QSPI *\/\n    RAM (rwx)       : ORIGIN = 0x20000000, LENGTH = 256K    \/* DTCM+SRAM1+SRAM2 *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define the stack.  The stack is full descending so begins just above last byte\n   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;\n_sstack = _estack - 16K;\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = _sstack;\n\nENTRY(Reset_Handler)\n\n\/* Define output sections *\/\nSECTIONS\n{\n    .text_ext :\n    {\n        . = ALIGN(512);\n        *(.big_const*)\n        . = ALIGN(4);\n    } >FLASH_EXT\n\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n    } >FLASH_APP\n\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        _etext = .;\n    } >FLASH_APP\n\n    _sidata = LOADADDR(.data);\n\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.data*)\n\n        . = ALIGN(4);\n        _edata = .;\n    } >RAM AT> FLASH_APP\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n    } >RAM\n\n    .heap :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_heap_size;\n        . = ALIGN(4);\n    } >RAM\n\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"ff54bcdf2e4e07d91e6568953d3af359fd6b5586","subject":"ArmVirtPkg\/ArmVirtPrePiUniCoreRelocatable: ignore .hash and .note sections","message":"ArmVirtPkg\/ArmVirtPrePiUniCoreRelocatable: ignore .hash and .note sections\n\nNewer versions of ld automatically emit .gnu.hash and .note.gnu.build-id\nsections, which are not listed in the linker script, and will end up\nbreaking the build with an allocation conflict, e.g.,\n\n  \/usr\/bin\/aarch64-linux-gnu-ld: section .note.gnu.build-id loaded at\n    [0000000000000000,0000000000000023] overlaps section .text loaded at\n    [0000000000000000,0000000000017dbf]\n\nSince we don't require or care about these sections, update the linker\nscript so that they are discarded. Note that this involves emitting the\n.note.gnu.build-id section into a non-allocatable segment to prevent the\nlinker from noticing that it is being discarded (and subsequently\ncomplaining about it)\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <66d3c5fdaeea7ff1f996ad04f2c45e08ab38e2f5@linaro.org>\nAcked-by: Laszlo Ersek <7437296077edea1cb64451c122c4dac071f0cfbc@redhat.com>\nAcked-by: Jordan Justen <a79006884ba9cf5f4f7fcbb92a15b208780d8c97@intel.com>\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"ArmVirtPkg\/PrePi\/Scripts\/PrePi-PIE.lds","new_file":"ArmVirtPkg\/PrePi\/Scripts\/PrePi-PIE.lds","new_contents":"\/** @file\r\n\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n\r\n  This program and the accompanying materials\r\n  are licensed and made available under the terms and conditions of the BSD License\r\n  which accompanies this distribution.  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS\r\n{\r\n  .text 0x0 : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    PROVIDE(__reloc_base = .);\r\n\r\n    *(.text .text*)\r\n    *(.got .got*)\r\n    *(.rodata .rodata*)\r\n    *(.data .data*)\r\n    *(.bss .bss*)\r\n\r\n    . = ALIGN(0x20);\r\n    PROVIDE(__reloc_start = .);\r\n    *(.rel .rel.*)\r\n    *(.rela .rela.*)\r\n    PROVIDE(__reloc_end = .);\r\n  }\r\n\r\n  .note (INFO) : { *(.note.gnu.build-id) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu.hash)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynamic)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.hash)\r\n    *(.comment)\r\n  }\r\n}\r\n","old_contents":"\/** @file\r\n\r\n  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n\r\n  This program and the accompanying materials\r\n  are licensed and made available under the terms and conditions of the BSD License\r\n  which accompanies this distribution.  The full text of the license may be found at\r\n  http:\/\/opensource.org\/licenses\/bsd-license.php\r\n\r\n  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n\r\n**\/\r\n\r\nSECTIONS\r\n{\r\n  .text 0x0 : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    PROVIDE(__reloc_base = .);\r\n\r\n    *(.text .text*)\r\n    *(.got .got*)\r\n    *(.rodata .rodata*)\r\n    *(.data .data*)\r\n    *(.bss .bss*)\r\n\r\n    . = ALIGN(0x20);\r\n    PROVIDE(__reloc_start = .);\r\n    *(.rel .rel.*)\r\n    *(.rela .rela.*)\r\n    PROVIDE(__reloc_end = .);\r\n  }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynamic)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.hash)\r\n    *(.comment)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"dc5ac89ab9a7c26919bbdfa97daab4ecadca3f89","subject":"posix: add zephyr_linker_sources() support","message":"posix: add zephyr_linker_sources() support\n\nAdd snippets sections in linker script, so we add support for\nzephyr_linker_sources() in native_posix arch.\n\nSigned-off-by: Marcin Niestroj <63506c06cfbc47ace147db1702f6e751f5ac2132@grinn-global.com>\n","repos":"galak\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/posix\/linker.ld","new_file":"include\/arch\/posix\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n * Copyright (c) 2017 Oticon A\/S\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the POSIX (native) platform\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\nSECTIONS\n {\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rom-start.ld>\n\n#include <linker\/common-rom.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#include <linker\/common-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#include <arch\/posix\/native_tasks.ld>\n\n __data_ram_end = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n } INSERT AFTER .data;\n\n\/*\n * Note that the INSERT command actually changes the meaning of the -T command\n * line switch: The script will now augment the default SECTIONS instead of\n * replacing it.\n *\/\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n * Copyright (c) 2017 Oticon A\/S\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the POSIX (native) platform\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\nSECTIONS\n {\n\n#include <linker\/common-rom.ld>\n\n#include <linker\/common-ram.ld>\n\n#include <arch\/posix\/native_tasks.ld>\n\n __data_ram_end = .;\n\n } INSERT AFTER .data;\n\n\/*\n * Note that the INSERT command actually changes the meaning of the -T command\n * line switch: The script will now augment the default SECTIONS instead of\n * replacing it.\n *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"801877e57c7c8976920d41dee682d58365a97ca4","subject":"exclude retained RAM","message":"exclude retained RAM\n","repos":"denisbohm\/firefly-ice-firmware,denisbohm\/firefly-ice-firmware,denisbohm\/firefly-ice-firmware","old_file":"ldscripts\/mem_EFM32LG330F256.ld","new_file":"ldscripts\/mem_EFM32LG330F256.ld","new_contents":"\/* Linker script to configure memory regions for EFM32LG330F256.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\n * Denis Bohm \/ Firefly Design\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K *\/\n  RAM (rwx) : ORIGIN = 0x20000100, LENGTH = 0x7f00 \/* 32K - 256 retained RAM *\/\n}\n","old_contents":"\/* Linker script to configure memory regions for EFM32LG330F256.\n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\n * Denis Bohm \/ Firefly Design\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K *\/\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 \/* 32K *\/\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"0649bb18907f56da90a0e557d3c15c225762bb4c","subject":"Divide up the memory.","message":"Divide up the memory.","repos":"rbsexton\/mpelite-stm32f0,rbsexton\/mpelite-stm32f0","old_file":"supervisor\/STM32F072VBTx_FLASH.ld","new_file":"supervisor\/STM32F072VBTx_FLASH.ld","new_contents":"\/*\r\n*****************************************************************************\r\n**\r\n\r\n**  File        : LinkerScript.ld\r\n**\r\n**  Abstract    : Linker script for STM32F072VBTx Device with\r\n**                128KByte FLASH, 16KByte RAM\r\n**\r\n**                Set heap size, stack size and stack location according\r\n**                to application requirements.\r\n**\r\n**                Set memory bank area and size if external memory is used.\r\n**\r\n**  Target      : STMicroelectronics STM32\r\n**\r\n**\r\n**  Distribution: The file is distributed as is, without any warranty\r\n**                of any kind.\r\n**\r\n**  (c)Copyright Ac6.\r\n**  You may use this file as-is or modify it according to the needs of your\r\n**  project. Distribution of this file (unmodified or modified) is not\r\n**  permitted. Ac6 permit registered System Workbench for MCU users the\r\n**  rights to distribute the assembled, compiled & linked contents of this\r\n**  file as part of an application binary file, provided that it is built\r\n**  using the System Workbench for MCU toolchain.\r\n**\r\n*****************************************************************************\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\n\/* Highest address of the user mode stack *\/\r\n_estack = 0x20002000;    \/* end of RAM *\/\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size  = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 32K\r\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 8K\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector)) \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  \/* The program code and other data goes into FLASH *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)           \/* .text sections (code) *\/\r\n    *(.text*)          \/* .text* sections (code) *\/\r\n    *(.glue_7)         \/* glue arm to thumb code *\/\r\n    *(.glue_7t)        \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;        \/* define a global symbols at end of code *\/\r\n  } >FLASH\r\n\r\n  \/* Constant data goes into FLASH *\/\r\n  .rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n  .ARM : {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } >FLASH\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } >FLASH\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } >FLASH\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } >FLASH\r\n\r\n  \/* used by the startup to initialize data *\/\r\n  _sidata = LOADADDR(.data);\r\n\r\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\r\n  .data : \r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .;        \/* create a global symbol at data start *\/\r\n    *(.data)           \/* .data sections *\/\r\n    *(.data*)          \/* .data* sections *\/\r\n\r\n    . = ALIGN(4);\r\n    _edata = .;        \/* define a global symbol at data end *\/\r\n  } >RAM AT> FLASH\r\n\r\n  \r\n  \/* Uninitialized data section *\/\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n    _sbss = .;         \/* define a global symbol at bss start *\/\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .;         \/* define a global symbol at bss end *\/\r\n    __bss_end__ = _ebss;\r\n  } >RAM\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(8);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(8);\r\n  } >RAM\r\n\r\n  \r\n\r\n  \/* Remove information from the standard libraries *\/\r\n  \/DISCARD\/ :\r\n  {\r\n    libc.a ( * )\r\n    libm.a ( * )\r\n    libgcc.a ( * )\r\n  }\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n\r\n\r\n","old_contents":"\/*\r\n*****************************************************************************\r\n**\r\n\r\n**  File        : LinkerScript.ld\r\n**\r\n**  Abstract    : Linker script for STM32F072VBTx Device with\r\n**                128KByte FLASH, 16KByte RAM\r\n**\r\n**                Set heap size, stack size and stack location according\r\n**                to application requirements.\r\n**\r\n**                Set memory bank area and size if external memory is used.\r\n**\r\n**  Target      : STMicroelectronics STM32\r\n**\r\n**\r\n**  Distribution: The file is distributed as is, without any warranty\r\n**                of any kind.\r\n**\r\n**  (c)Copyright Ac6.\r\n**  You may use this file as-is or modify it according to the needs of your\r\n**  project. Distribution of this file (unmodified or modified) is not\r\n**  permitted. Ac6 permit registered System Workbench for MCU users the\r\n**  rights to distribute the assembled, compiled & linked contents of this\r\n**  file as part of an application binary file, provided that it is built\r\n**  using the System Workbench for MCU toolchain.\r\n**\r\n*****************************************************************************\r\n*\/\r\n\r\n\/* Entry Point *\/\r\nENTRY(Reset_Handler)\r\n\r\n\/* Highest address of the user mode stack *\/\r\n_estack = 0x20004000;    \/* end of RAM *\/\r\n\/* Generate a link error if heap and stack don't fit into RAM *\/\r\n_Min_Heap_Size = 0x200;      \/* required amount of heap  *\/\r\n_Min_Stack_Size = 0x400; \/* required amount of stack *\/\r\n\r\n\/* Specify the memory areas *\/\r\nMEMORY\r\n{\r\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 128K\r\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 16K\r\n}\r\n\r\n\/* Define output sections *\/\r\nSECTIONS\r\n{\r\n  \/* The startup code goes first into FLASH *\/\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector)) \/* Startup code *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  \/* The program code and other data goes into FLASH *\/\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)           \/* .text sections (code) *\/\r\n    *(.text*)          \/* .text* sections (code) *\/\r\n    *(.glue_7)         \/* glue arm to thumb code *\/\r\n    *(.glue_7t)        \/* glue thumb to arm code *\/\r\n    *(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;        \/* define a global symbols at end of code *\/\r\n  } >FLASH\r\n\r\n  \/* Constant data goes into FLASH *\/\r\n  .rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\r\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n  .ARM : {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } >FLASH\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } >FLASH\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } >FLASH\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } >FLASH\r\n\r\n  \/* used by the startup to initialize data *\/\r\n  _sidata = LOADADDR(.data);\r\n\r\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\r\n  .data : \r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .;        \/* create a global symbol at data start *\/\r\n    *(.data)           \/* .data sections *\/\r\n    *(.data*)          \/* .data* sections *\/\r\n\r\n    . = ALIGN(4);\r\n    _edata = .;        \/* define a global symbol at data end *\/\r\n  } >RAM AT> FLASH\r\n\r\n  \r\n  \/* Uninitialized data section *\/\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    \/* This is used by the startup in order to initialize the .bss secion *\/\r\n    _sbss = .;         \/* define a global symbol at bss start *\/\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .;         \/* define a global symbol at bss end *\/\r\n    __bss_end__ = _ebss;\r\n  } >RAM\r\n\r\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(8);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(8);\r\n  } >RAM\r\n\r\n  \r\n\r\n  \/* Remove information from the standard libraries *\/\r\n  \/DISCARD\/ :\r\n  {\r\n    libc.a ( * )\r\n    libm.a ( * )\r\n    libgcc.a ( * )\r\n  }\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n}\r\n\r\n\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f98c5a7fa205bff1a67154405e1f22ffcf000436","subject":"Don't overwrite app vectors when updating bootloader","message":"Don't overwrite app vectors when updating bootloader\n","repos":"lincomatic\/fadecandy,fragmede\/fadecandy,adam-back\/fadecandy,nomis52\/fadecandy,jsestrich\/fadecandy,jsestrich\/fadecandy,PimentNoir\/fadecandy,adam-back\/fadecandy,PimentNoir\/fadecandy,hakan42\/fadecandy,lincomatic\/fadecandy,Jorgen-VikingGod\/fadecandy,piers7\/fadecandy,poe\/fadecandy,poe\/fadecandy,poe\/fadecandy,Protoneer\/fadecandy,scanlime\/fadecandy,fragmede\/fadecandy,hakan42\/fadecandy,piers7\/fadecandy,poe\/fadecandy,adam-back\/fadecandy,scanlime\/fadecandy,PimentNoir\/fadecandy,scanlime\/fadecandy,hakan42\/fadecandy,pixelmatix\/fadecandy,pixelmatix\/fadecandy,nomis52\/fadecandy,Protoneer\/fadecandy,nomis52\/fadecandy,piers7\/fadecandy,nomis52\/fadecandy,nomis52\/fadecandy,PimentNoir\/fadecandy,PimentNoir\/fadecandy,fragmede\/fadecandy,piers7\/fadecandy,pixelmatix\/fadecandy,lincomatic\/fadecandy,pixelmatix\/fadecandy,lincomatic\/fadecandy,fragmede\/fadecandy,jsestrich\/fadecandy,lincomatic\/fadecandy,scanlime\/fadecandy,adam-back\/fadecandy,nomis52\/fadecandy,fragmede\/fadecandy,Jorgen-VikingGod\/fadecandy,poe\/fadecandy,scanlime\/fadecandy,Jorgen-VikingGod\/fadecandy,pixelmatix\/fadecandy,lincomatic\/fadecandy,hakan42\/fadecandy,poe\/fadecandy,jsestrich\/fadecandy,nomis52\/fadecandy,lincomatic\/fadecandy,hakan42\/fadecandy,fragmede\/fadecandy,poe\/fadecandy,Protoneer\/fadecandy,lincomatic\/fadecandy,Jorgen-VikingGod\/fadecandy,scanlime\/fadecandy,fragmede\/fadecandy,Protoneer\/fadecandy,jsestrich\/fadecandy,Protoneer\/fadecandy,fragmede\/fadecandy,nomis52\/fadecandy,Jorgen-VikingGod\/fadecandy,piers7\/fadecandy,PimentNoir\/fadecandy,poe\/fadecandy,adam-back\/fadecandy","old_file":"bootloader\/mk20dx128.ld","new_file":"bootloader\/mk20dx128.ld","new_contents":"\/*\n * FC-Boot linker script.\n *\n *   - Early startup code runs out of flash\n *   - Everything else runs out of RAM\n *   - All flash after the first 4K page is reserved for application use\n *   - The last 4 bytes of RAM are used as our boot token\n *\/\n\nMEMORY\n{\n    BOOT_FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 4K\n    APP_FLASH (rx) : ORIGIN = 0x00001000, LENGTH = 124K\n    RAM (rwx) : ORIGIN = 0x1FFFE000, LENGTH = 16K\n    FLEXRAM (rwx) : ORIGIN = 0x14000000, LENGTH = 2K\n}\n\nSECTIONS\n{\n    .flash : {\n        . = 0;\n        KEEP(*(.vectors))\n        *(.startup*)\n        . = 0x400;\n        KEEP(*(.flashconfig*))\n    } > BOOT_FLASH = 0xFF\n    _eflash = .;\n\n    .apptext (NOLOAD) : {\n        . = ORIGIN(APP_FLASH);\n        *(.appvectors)\n    } > APP_FLASH = 0xFF\n\n    .usbdescriptortable (NOLOAD) : {\n        . = ALIGN(512);\n        *(.usbdescriptortable*)\n    } > RAM\n\n    .dmabuffers (NOLOAD) : {\n        . = ALIGN(4);\n        *(.dmabuffers*)\n    } > RAM\n\n    .usbbuffers (NOLOAD) : {\n        . = ALIGN(4);\n        *(.usbbuffers*)\n    } > RAM\n\n    .flexram (NOLOAD) : {\n        . = ALIGN(4);\n        *(.flexram*)\n    } > FLEXRAM\n\n    \/* Combined data and text, after relocation *\/\n    .dtext : AT (_eflash) {\n        . = ALIGN(4);\n        _sdtext = .; \n        *(.text*)\n        *(.rodata*)\n        *(.data*)\n        . = ALIGN(4);\n        _edtext = .; \n    } > RAM\n\n    .noinit (NOLOAD) : {\n        *(.noinit*)\n    } > RAM\n\n    .bss : {\n        . = ALIGN(4);\n        _sbss = .; \n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n        __bss_end = .;\n    } > RAM\n\n    _estack = ORIGIN(RAM) + LENGTH(RAM) - 4;\n    boot_token = _estack;\n}\n\n\n","old_contents":"\/*\n * FC-Boot linker script.\n *\n *   - Early startup code runs out of flash\n *   - Everything else runs out of RAM\n *   - All flash after the first 4K page is reserved for application use\n *   - The last 4 bytes of RAM are used as our boot token\n *\/\n\nMEMORY\n{\n    BOOT_FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 4K\n    APP_FLASH (rx) : ORIGIN = 0x00001000, LENGTH = 124K\n    RAM (rwx) : ORIGIN = 0x1FFFE000, LENGTH = 16K\n    FLEXRAM (rwx) : ORIGIN = 0x14000000, LENGTH = 2K\n}\n\nSECTIONS\n{\n    .flash : {\n        . = 0;\n        KEEP(*(.vectors))\n        *(.startup*)\n        . = 0x400;\n        KEEP(*(.flashconfig*))\n    } > BOOT_FLASH = 0xFF\n    _eflash = .;\n\n    .apptext : {\n        . = ORIGIN(APP_FLASH);\n        *(.appvectors)\n    } > APP_FLASH = 0xFF\n\n    .usbdescriptortable (NOLOAD) : {\n        . = ALIGN(512);\n        *(.usbdescriptortable*)\n    } > RAM\n\n    .dmabuffers (NOLOAD) : {\n        . = ALIGN(4);\n        *(.dmabuffers*)\n    } > RAM\n\n    .usbbuffers (NOLOAD) : {\n        . = ALIGN(4);\n        *(.usbbuffers*)\n    } > RAM\n\n    .flexram (NOLOAD) : {\n        . = ALIGN(4);\n        *(.flexram*)\n    } > FLEXRAM\n\n    \/* Combined data and text, after relocation *\/\n    .dtext : AT (_eflash) {\n        . = ALIGN(4);\n        _sdtext = .; \n        *(.text*)\n        *(.rodata*)\n        *(.data*)\n        . = ALIGN(4);\n        _edtext = .; \n    } > RAM\n\n    .noinit (NOLOAD) : {\n        *(.noinit*)\n    } > RAM\n\n    .bss : {\n        . = ALIGN(4);\n        _sbss = .; \n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n        __bss_end = .;\n    } > RAM\n\n    _estack = ORIGIN(RAM) + LENGTH(RAM) - 4;\n    boot_token = _estack;\n}\n\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"5cdf55ff2084d8aa719fe74fbe1622b61ff64294","subject":"Remove vkGetInstanceProcAddr from exported symbols on Fuchsia","message":"Remove vkGetInstanceProcAddr from exported symbols on Fuchsia\n\nFuchsia only allows access to the ICD's functions, through the Vulkan\nLoader interface functions.\n\nExporting this function was copied from the android_vk_swiftshader.lds\nfile, but it has been removed from the latter due to causing direct\naccess to methods that should have an overridden implementation. Similar\nissues are likely to occur on Fuchsia if we keep this function exported.\n\nBug: b\/148822450\nChange-Id: I12f2dad933abcd9dbf89518ac5714b9f936419e4\nReviewed-on: https:\/\/swiftshader-review.googlesource.com\/c\/SwiftShader\/+\/53609\nKokoro-Result: kokoro <2ac7b1f3fa578934c95181d4272be0d3bca00121@google.com>\nReviewed-by: David Turner <dcb93bd72059500c1226ad16fdd58ffe25c9e0ea@google.com>\nReviewed-by: Nicolas Capens <51edc787c30f24c4904e8ffbb5523c3a9f7a451d@google.com>\nTested-by: Nicolas Capens <51edc787c30f24c4904e8ffbb5523c3a9f7a451d@google.com>\n","repos":"google\/swiftshader,bkaradzic\/SwiftShader,bkaradzic\/SwiftShader,bkaradzic\/SwiftShader,google\/swiftshader,bkaradzic\/SwiftShader,google\/swiftshader,bkaradzic\/SwiftShader","old_file":"src\/Vulkan\/fuchsia_vk_swiftshader.lds","new_file":"src\/Vulkan\/fuchsia_vk_swiftshader.lds","new_contents":"# For Fuchsia, we must not export anything other than loader-related API\n# There is also the vk_icdInitializeConnectToServiceCallback entry point\n# that is specific to the Fuchsia Vulkan loader implementation.\n{\nglobal:\n\t# Loader-ICD interface functions\n\tvk_icdGetInstanceProcAddr;\n\tvk_icdNegotiateLoaderICDInterfaceVersion;\n\tvk_icdInitializeConnectToServiceCallback;\n\nlocal:\n\t*;\n};\n\n","old_contents":"# For Fuchsia, we must not export anything other than loader-related API\n# There is also the vk_icdInitializeConnectToServiceCallback entry point\n# that is specific to the Fuchsia Vulkan loader implementation.\n{\nglobal:\n\tvkGetInstanceProcAddr;\n\n\t# Loader-ICD interface functions\n\tvk_icdGetInstanceProcAddr;\n\tvk_icdNegotiateLoaderICDInterfaceVersion;\n\tvk_icdInitializeConnectToServiceCallback;\n\nlocal:\n\t*;\n};\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"79e573472ea719597228ed024bd493cb78f477be","subject":"Added __argdata__ to switch.ld.","message":"Added __argdata__ to switch.ld.\n","repos":"switchbrew\/libnx","old_file":"buildscripts\/lib\/switch.ld","new_file":"buildscripts\/lib\/switch.ld","new_contents":"OUTPUT_ARCH(aarch64)\nENTRY(_start)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(5) \/* Read | Execute *\/;\n\trodata PT_LOAD FLAGS(4) \/* Read *\/;\n\tdata   PT_LOAD FLAGS(6) \/* Read | Write *\/;\n\tdyn    PT_DYNAMIC;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\tPROVIDE(__start__ = 0x0);\n\t. = __start__;\n\n\t.crt0 :\n\t{\n\t\tKEEP (*(.crt0))\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.init :\n\t{\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.plt :\n\t{\n\t\t*(.plt)\n\t\t*(.iplt)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.text :\n\t{\n\t\t*(.text.unlikely .text.*_unlikely .text.unlikely.*)\n\t\t*(.text.exit .text.exit.*)\n\t\t*(.text.startup .text.startup.*)\n\t\t*(.text.hot .text.hot.*)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.fini :\n\t{\n\t\tKEEP( *(.fini) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t\/* =========== RODATA section =========== *\/\n\t. = ALIGN(0x1000);\n\n\t.rodata :\n\t{\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(8);\n\t} :rodata\n\n\t.eh_frame_hdr     : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } :rodata\n\t.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata\n\t.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata\n\t.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata\n\n\t.dynamic           : { *(.dynamic) } :rodata :dyn\n\t.interp            : { *(.interp) } :rodata\n\t.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata\n\t.hash              : { *(.hash) } :rodata\n\t.gnu.hash          : { *(.gnu.hash) } :rodata\n\t.gnu.version       : { *(.gnu.version) } :rodata\n\t.gnu.version_d     : { *(.gnu.version_d) } :rodata\n\t.gnu.version_r     : { *(.gnu.version_r) } :rodata\n\t.dynsym            : { *(.dynsym) } :rodata\n\t.dynstr            : { *(.dynstr) } :rodata\n\t.rela.dyn          : { *(.rela.*) } :rodata\n\n\t\/* =========== DATA section =========== *\/\n\t. = ALIGN(0x1000);\n\n\t.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data\n\t.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data\n\t.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data\n\t.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data\n\n\t.tdata ALIGN(8) :\n\t{\n\t\t__tdata_lma = .;\n\t\t*(.tdata .tdata.* .gnu.linkonce.td.*)\n\t\t. = ALIGN(8);\n\t\t__tdata_lma_end = .;\n\t} :data\n\n\t.tbss ALIGN(8) :\n\t{\n\t\t*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)\n\t\t. = ALIGN(8);\n\t} :data\n\n\t.preinit_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\t} :data\n\n\t.init_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\t} :data\n\n\t.fini_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__fini_array_start = .);\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tPROVIDE (__fini_array_end = .);\n\t} :data\n\n\t.ctors ALIGN(8) :\n\t{\n\t\tKEEP (*crtbegin.o(.ctors)) \/* MUST be first -- GCC requires it *\/\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t} :data\n\n\t.dtors ALIGN(8) :\n\t{\n\t\tKEEP (*crtbegin.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t} :data\n\n\t__got_start__ = .;\n\n\t.got            : { *(.got) *(.igot) } :data\n\t.got.plt        : { *(.got.plt)  *(.igot.plt) } :data\n\n\t__got_end__ = .;\n\n\t.data ALIGN(8) :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tSORT(CONSTRUCTORS)\n\t} :data\n\n\t__bss_start__ = .;\n\t.bss ALIGN(8) :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\n\t\t\/* Reserve space for the TLS segment of the main thread *\/\n\t\t__tls_start = .;\n\t\t. += + SIZEOF(.tdata) + SIZEOF(.tbss);\n\t\t__tls_end = .;\n\t} : data\n\t__bss_end__ = .;\n\n\t__end__ = ABSOLUTE(.) ;\n\n\t. = ALIGN(0x1000);\n\t__argdata__ = ABSOLUTE(.) ;\n\n\t\/* ==================\n\t   ==== Metadata ====\n\t   ================== *\/\n\n\t\/* Discard sections that difficult post-processing *\/\n\t\/DISCARD\/ : { *(.group .comment .note) }\n\n\t\/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n}\n","old_contents":"OUTPUT_ARCH(aarch64)\nENTRY(_start)\n\nPHDRS\n{\n\tcode   PT_LOAD FLAGS(5) \/* Read | Execute *\/;\n\trodata PT_LOAD FLAGS(4) \/* Read *\/;\n\tdata   PT_LOAD FLAGS(6) \/* Read | Write *\/;\n\tdyn    PT_DYNAMIC;\n}\n\nSECTIONS\n{\n\t\/* =========== CODE section =========== *\/\n\tPROVIDE(__start__ = 0x0);\n\t. = __start__;\n\n\t.crt0 :\n\t{\n\t\tKEEP (*(.crt0))\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.init :\n\t{\n\t\tKEEP( *(.init) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.plt :\n\t{\n\t\t*(.plt)\n\t\t*(.iplt)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.text :\n\t{\n\t\t*(.text.unlikely .text.*_unlikely .text.unlikely.*)\n\t\t*(.text.exit .text.exit.*)\n\t\t*(.text.startup .text.startup.*)\n\t\t*(.text.hot .text.hot.*)\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t\t. = ALIGN(8);\n\t} :code\n\n\t.fini :\n\t{\n\t\tKEEP( *(.fini) )\n\t\t. = ALIGN(8);\n\t} :code\n\n\t\/* =========== RODATA section =========== *\/\n\t. = ALIGN(0x1000);\n\n\t.rodata :\n\t{\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t. = ALIGN(8);\n\t} :rodata\n\n\t.eh_frame_hdr     : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } :rodata\n\t.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata\n\t.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata\n\t.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata\n\n\t.dynamic           : { *(.dynamic) } :rodata :dyn\n\t.interp            : { *(.interp) } :rodata\n\t.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata\n\t.hash              : { *(.hash) } :rodata\n\t.gnu.hash          : { *(.gnu.hash) } :rodata\n\t.gnu.version       : { *(.gnu.version) } :rodata\n\t.gnu.version_d     : { *(.gnu.version_d) } :rodata\n\t.gnu.version_r     : { *(.gnu.version_r) } :rodata\n\t.dynsym            : { *(.dynsym) } :rodata\n\t.dynstr            : { *(.dynstr) } :rodata\n\t.rela.dyn          : { *(.rela.*) } :rodata\n\n\t\/* =========== DATA section =========== *\/\n\t. = ALIGN(0x1000);\n\n\t.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data\n\t.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data\n\t.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data\n\t.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data\n\n\t.tdata ALIGN(8) :\n\t{\n\t\t__tdata_lma = .;\n\t\t*(.tdata .tdata.* .gnu.linkonce.td.*)\n\t\t. = ALIGN(8);\n\t\t__tdata_lma_end = .;\n\t} :data\n\n\t.tbss ALIGN(8) :\n\t{\n\t\t*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)\n\t\t. = ALIGN(8);\n\t} :data\n\n\t.preinit_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE (__preinit_array_end = .);\n\t} :data\n\n\t.init_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\tPROVIDE (__init_array_end = .);\n\t} :data\n\n\t.fini_array ALIGN(8) :\n\t{\n\t\tPROVIDE (__fini_array_start = .);\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tPROVIDE (__fini_array_end = .);\n\t} :data\n\n\t.ctors ALIGN(8) :\n\t{\n\t\tKEEP (*crtbegin.o(.ctors)) \/* MUST be first -- GCC requires it *\/\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t} :data\n\n\t.dtors ALIGN(8) :\n\t{\n\t\tKEEP (*crtbegin.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t} :data\n\n\t__got_start__ = .;\n\n\t.got            : { *(.got) *(.igot) } :data\n\t.got.plt        : { *(.got.plt)  *(.igot.plt) } :data\n\n\t__got_end__ = .;\n\n\t.data ALIGN(8) :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\tSORT(CONSTRUCTORS)\n\t} :data\n\n\t__bss_start__ = .;\n\t.bss ALIGN(8) :\n\t{\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\n\t\t\/* Reserve space for the TLS segment of the main thread *\/\n\t\t__tls_start = .;\n\t\t. += + SIZEOF(.tdata) + SIZEOF(.tbss);\n\t\t__tls_end = .;\n\t} : data\n\t__bss_end__ = .;\n\n\t__end__ = ABSOLUTE(.) ;\n\n\t\/* ==================\n\t   ==== Metadata ====\n\t   ================== *\/\n\n\t\/* Discard sections that difficult post-processing *\/\n\t\/DISCARD\/ : { *(.group .comment .note) }\n\n\t\/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\n\t\/* DWARF debug sections.\n\t   Symbols in the DWARF debugging sections are relative to the beginning\n\t   of the section so we begin them at 0. *\/\n\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n}\n","returncode":0,"stderr":"","license":"isc","lang":"Linker Script"}
{"commit":"84cb7615e42a39cc73b4183c9602573fee61cc29","subject":"x86: Explicitly declare adress of .phys.bss","message":"x86: Explicitly declare adress of .phys.bss\n\nSometimes when linking the linker relocates the .phys.bss section to\nthe 0 physical address (seemingly ignoring the `.` directive). To work\naround this we calculate an explicit address based on the size of the\n.phys section and set that as the segment address. This *should* be\ncompletely equivalent to just using `.`, but ld seems to disagree\n","repos":"cmr\/seL4,cmr\/seL4,cmr\/seL4","old_file":"src\/plat\/pc99\/linker.lds","new_file":"src\/plat\/pc99\/linker.lds","new_contents":"\/*\n * Copyright 2014, General Dynamics C4 Systems\n *\n * This software may be distributed and modified according to the terms of\n * the GNU General Public License version 2. Note that NO WARRANTY is provided.\n * See \"LICENSE_GPLv2.txt\" for details.\n *\n * @TAG(GD_GPL)\n *\/\n\n#include <config.h>\n\nENTRY(_start)\n\n\/* WARNING: constants also defined in plat\/machine\/hardware.h *\/\n#if defined(CONFIG_ARCH_IA32)\nPADDR_BASE = 0x00000000;\nPADDR_LOAD = 0x00100000;\nKERNEL_BASE  = 0xe0000000;\nOUTPUT_ARCH(i386)\nOUTPUT_FORMAT(elf32-i386)\n#elif defined(CONFIG_ARCH_X86_64)\nPADDR_BASE = 0x00000000;\nPADDR_LOAD = 0x00100000;\nKERNEL_BASE = 0xffffffff80000000;\nOUTPUT_FORMAT(elf64-x86-64)\n#endif\n\nKERNEL_OFFSET = KERNEL_BASE - PADDR_BASE;\n\nSECTIONS\n{\n    \/* load kernel to 1M to avoid the famous IA-32 memory holes below *\/\n    . = PADDR_LOAD;\n\n    \/* code\/data only needed during bootstrapping, linked to physical addresses *\/\n\n    .phys . :\n    {\n        *(.mbh)\n        *(.phys.text)\n        *(.phys.data)\n        . = ALIGN(4K);\n    }\n\n    .phys.bss ADDR(.phys) + SIZEOF(.phys) (NOLOAD) :\n    {\n        boot_stack_bottom = .;\n        . = . + 2K;\n        . = ALIGN(4K);\n        boot_stack_top = .;\n        *(.phys.bss)\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .boot . : AT(ADDR(.boot) - KERNEL_OFFSET)\n    {\n        *(.boot.text)\n        *(.boot.data)\n    }\n\n    .boot.bss . (NOLOAD) : AT(ADDR(.boot.bss) - KERNEL_OFFSET)\n    {\n        *(.boot.bss)\n        . = ALIGN(4K);\n    }\n\n    ki_boot_end = .;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        *(.text)\n    }\n\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    .ehframe : AT(ADDR(.ehframe) - KERNEL_OFFSET)\n    {\n        _ehframe = .;\n        *(.eh_frame)\n        . = ALIGN(4K);\n    }\n\n    . = ALIGN(4K);\n    ki_end = .;\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n    }\n}\n","old_contents":"\/*\n * Copyright 2014, General Dynamics C4 Systems\n *\n * This software may be distributed and modified according to the terms of\n * the GNU General Public License version 2. Note that NO WARRANTY is provided.\n * See \"LICENSE_GPLv2.txt\" for details.\n *\n * @TAG(GD_GPL)\n *\/\n\n#include <config.h>\n\nENTRY(_start)\n\n\/* WARNING: constants also defined in plat\/machine\/hardware.h *\/\n#if defined(CONFIG_ARCH_IA32)\nPADDR_BASE = 0x00000000;\nPADDR_LOAD = 0x00100000;\nKERNEL_BASE  = 0xe0000000;\nOUTPUT_ARCH(i386)\nOUTPUT_FORMAT(elf32-i386)\n#elif defined(CONFIG_ARCH_X86_64)\nPADDR_BASE = 0x00000000;\nPADDR_LOAD = 0x00100000;\nKERNEL_BASE = 0xffffffff80000000;\nOUTPUT_FORMAT(elf64-x86-64)\n#endif\n\nKERNEL_OFFSET = KERNEL_BASE - PADDR_BASE;\n\nSECTIONS\n{\n    \/* load kernel to 1M to avoid the famous IA-32 memory holes below *\/\n    . = PADDR_LOAD;\n\n    \/* code\/data only needed during bootstrapping, linked to physical addresses *\/\n\n    .phys . :\n    {\n        *(.mbh)\n        *(.phys.text)\n        *(.phys.data)\n        . = ALIGN(4K);\n    }\n\n    .phys.bss . (NOLOAD) :\n    {\n        boot_stack_bottom = .;\n        . = . + 2K;\n        . = ALIGN(4K);\n        boot_stack_top = .;\n        *(.phys.bss)\n    }\n\n    . = . + KERNEL_OFFSET;\n\n    .boot . : AT(ADDR(.boot) - KERNEL_OFFSET)\n    {\n        *(.boot.text)\n        *(.boot.data)\n    }\n\n    .boot.bss . (NOLOAD) : AT(ADDR(.boot.bss) - KERNEL_OFFSET)\n    {\n        *(.boot.bss)\n        . = ALIGN(4K);\n    }\n\n    ki_boot_end = .;\n\n    .text . : AT(ADDR(.text) - KERNEL_OFFSET)\n    {\n        *(.text)\n    }\n\n    .rodata . : AT(ADDR(.rodata) - KERNEL_OFFSET)\n    {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data . : AT(ADDR(.data) - KERNEL_OFFSET)\n    {\n        *(.data)\n    }\n\n    .bss . : AT(ADDR(.bss) - KERNEL_OFFSET)\n    {\n        *(.bss)\n        *(COMMON)\n    }\n\n    .ehframe : AT(ADDR(.ehframe) - KERNEL_OFFSET)\n    {\n        _ehframe = .;\n        *(.eh_frame)\n        . = ALIGN(4K);\n    }\n\n    . = ALIGN(4K);\n    ki_end = .;\n\n    \/DISCARD\/ :\n    {\n        *(.note.gnu.build-id)\n        *(.comment)\n    }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"4d409b8e3276c2e40191ada9726780a0dcc776ba","subject":"stm32\/boards\/stm32f767.ld: Add definition of FLASH_APP.","message":"stm32\/boards\/stm32f767.ld: Add definition of FLASH_APP.\n\nThis allows F767 MCUs to support a bootloader in the first sector.\n","repos":"pfalcon\/micropython,pfalcon\/micropython,dmazzella\/micropython,swegener\/micropython,pramasoul\/micropython,adafruit\/micropython,ryannathans\/micropython,swegener\/micropython,tralamazza\/micropython,swegener\/micropython,pozetroninc\/micropython,MrSurly\/micropython,swegener\/micropython,henriknelson\/micropython,adafruit\/micropython,pfalcon\/micropython,tobbad\/micropython,kerneltask\/micropython,selste\/micropython,trezor\/micropython,henriknelson\/micropython,pramasoul\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,ryannathans\/micropython,bvernoux\/micropython,adafruit\/micropython,adafruit\/circuitpython,pfalcon\/micropython,bvernoux\/micropython,trezor\/micropython,selste\/micropython,adafruit\/circuitpython,selste\/micropython,tobbad\/micropython,pfalcon\/micropython,dmazzella\/micropython,pozetroninc\/micropython,pramasoul\/micropython,trezor\/micropython,kerneltask\/micropython,pramasoul\/micropython,MrSurly\/micropython,ryannathans\/micropython,tralamazza\/micropython,henriknelson\/micropython,kerneltask\/micropython,MrSurly\/micropython,pozetroninc\/micropython,adafruit\/micropython,ryannathans\/micropython,tobbad\/micropython,trezor\/micropython,bvernoux\/micropython,selste\/micropython,swegener\/micropython,pozetroninc\/micropython,MrSurly\/micropython,henriknelson\/micropython,tobbad\/micropython,pozetroninc\/micropython,pramasoul\/micropython,bvernoux\/micropython,tralamazza\/micropython,henriknelson\/micropython,adafruit\/micropython,bvernoux\/micropython,kerneltask\/micropython,adafruit\/circuitpython,selste\/micropython,dmazzella\/micropython,trezor\/micropython,kerneltask\/micropython,tralamazza\/micropython,MrSurly\/micropython,tobbad\/micropython,adafruit\/circuitpython,dmazzella\/micropython,ryannathans\/micropython","old_file":"ports\/stm32\/boards\/stm32f767.ld","new_file":"ports\/stm32\/boards\/stm32f767.ld","new_contents":"\/*\n    GNU linker script for STM32F767\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 32K     \/* sector 0, 32K *\/\n    FLASH_APP (rx)  : ORIGIN = 0x08008000, LENGTH = 2016K   \/* sectors 1-11 3x32K 1*128K 7*256K *\/\n    FLASH_FS (r)    : ORIGIN = 0x08008000, LENGTH = 96K     \/* sectors 1, 2, 3 (32K each) *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 896K    \/* sectors 4-7 1*128Kib 3*256KiB = 896K *\/\n    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    \/* Used for storage cache *\/\n    RAM (xrw)       : ORIGIN = 0x20020000, LENGTH = 384K    \/* SRAM1 = 368K, SRAM2 = 16K *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = 0x20078000; \/* tunable *\/\n","old_contents":"\/*\n    GNU linker script for STM32F767\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 32K     \/* sector 0, 32K *\/\n    FLASH_FS (r)    : ORIGIN = 0x08008000, LENGTH = 96K     \/* sectors 1, 2, 3 (32K each) *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 896K    \/* sectors 4-7 1*128Kib 3*256KiB = 896K *\/\n    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    \/* Used for storage cache *\/\n    RAM (xrw)       : ORIGIN = 0x20020000, LENGTH = 384K    \/* SRAM1 = 368K, SRAM2 = 16K *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n\n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_start = ORIGIN(RAM);\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_start = _ebss; \/* heap starts just after statically allocated memory *\/\n_heap_end = 0x20078000; \/* tunable *\/\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"9f09c985daaffb67586978a3d85508d8e4d617b7","subject":"Fixed nRF52 linker script RAM length","message":"Fixed nRF52 linker script RAM length\n\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_xxaa.ld","new_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_xxaa.ld","new_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000\r\n\tRAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x10000\r\n}\r\n\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"\r\n","old_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\nMEMORY\n{\n\tFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000\n\tRAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x8000\n}\r\n\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"e5dcea5b7cf926ab675bc6cf98d1cb70dc9d8b56","subject":"Fix linker script to deal with data section alignment.","message":"Fix linker script to deal with data section alignment.\n\n- The location of \"_sidata\" wasn't matching the LMA of \".data\" due\n  to alignment of the data section, leading to segfaults depending\n  on how much code was in the \".text\" section.\n","repos":"GaloisInc\/ivory-tower-stm32,GaloisInc\/ivory-tower-stm32,GaloisInc\/ivory-tower-stm32","old_file":"stm32_flash.ld","new_file":"stm32_flash.ld","new_contents":"\/****************************************************************************\n * configs\/px4fmu\/common\/ld.script\n *\n *   Copyright (C) 2011 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The STM32F405 has 1024Kb of FLASH beginning at address 0x0800:0000 and\n * 192Kb of SRAM. SRAM is split up into three blocks:\n *\n * 1) 112Kb of SRAM beginning at address 0x2000:0000\n * 2)  16Kb of SRAM beginning at address 0x2001:c000\n * 3)  64Kb of TCM SRAM beginning at address 0x1000:0000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0800:0000 address range.\n *\n * HWF4: In the original linker script, the first 0x4000 of flash was\n * reserved for the bootloader.  For now, we'll place the application\n * at the start of flash until we start using a boot loader again.\n *\/\n\nMEMORY\n{\n\/*  flash (rx)   : ORIGIN = 0x08004000, LENGTH = 1008K *\/\n  flash (rx)   : ORIGIN = 0x08000000, LENGTH = 1024K\n  sram (rwx)   : ORIGIN = 0x20000000, LENGTH = 128K\n  ccsram (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Top of the user mode stack. *\/\n_estack = 0x20020000;           \/* top of 128KiB of SRAM *\/\n\n\/* Error in the linker if heap and stack don't fit. *\/\n_min_heap_size = 0;\n_min_stack_size = 0x400;\n\nOUTPUT_ARCH(arm)\n\nENTRY(Reset_Handler)\n\n\/*\n * Ensure that abort() is present in the final object.  The exception handling\n * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).\n *\/\n\/* EXTERN(abort) *\/\n\nSECTIONS\n{\n  \/* Place startup code at start of flash. *\/\n  .isr_vector : {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))\n    . = ALIGN(4);\n  } > flash\n\n  \/* Program code and constant data. *\/\n  .text : {\n    *(.text .text.*)\n    *(.fixup)\n    *(.gnu.warning)\n    *(.rodata .rodata.*)\n    *(.glue_7)\n    *(.glue_7t)\n    *(.eh_frame)\n    *(.gnu.linkonce.t.*)\n    *(.got)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.r.*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    . = ALIGN(4);\n    _etext = ABSOLUTE(.);\n  } > flash\n\n  .ARM.extab : {\n    *(.ARM.extab*)\n  } > flash\n\n  __exidx_start = ABSOLUTE(.);\n  .ARM.exidx : {\n    *(.ARM.exidx*)\n  } > flash\n  __exidx_end = ABSOLUTE(.);\n\n  .preinit_array : {\n    PROVIDE_HIDDEN(__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN(__preinit_array_end = .);\n  } > flash\n\n  .init_array : {\n    PROVIDE_HIDDEN(__init_array_start = .);\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN(__init_array_end = .);\n  } > flash\n\n  .ctors : {\n    KEEP(*crtbegin.o(.ctors))\n    KEEP(*crtbegin?.o(.ctors))\n    KEEP(*(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors))\n    KEEP(*(SORT(.ctors.*)))\n    KEEP(*(.ctors))\n  } > flash\n\n  .data : {\n    _sidata = LOADADDR(.data);\n    _sdata = ABSOLUTE(.);\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    CONSTRUCTORS\n    _edata = ABSOLUTE(.);\n  } > sram AT > flash\n\n  . = ALIGN(4);\n  .bss : {\n    _sbss = ABSOLUTE(.);\n    __bss_start__ = ABSOLUTE(_sbss);\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n    _ebss = ABSOLUTE(.);\n    __bss_end__ = ABSOLUTE(_ebss);\n  } > sram\n\n  ._user_heap_stack : {\n    . = ALIGN(4);\n    PROVIDE(end = .);\n    PROVIDE(_end = .);\n    . = . + _min_heap_size;\n    . = . + _min_stack_size;\n    . = ALIGN(4);\n  } > sram\n\n  \/* Stabs debugging sections. *\/\n  .stab 0 : { *(.stab) }\n  .stabstr 0 : { *(.stabstr) }\n  .stab.excl 0 : { *(.stab.excl) }\n  .stab.exclstr 0 : { *(.stab.exclstr) }\n  .stab.index 0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment 0 : { *(.comment) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n\n  \/DISCARD\/ : {\n    libc.a (*)\n    libm.a (*)\n    libgcc.a (*)\n  }\n}\n","old_contents":"\/****************************************************************************\n * configs\/px4fmu\/common\/ld.script\n *\n *   Copyright (C) 2011 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The STM32F405 has 1024Kb of FLASH beginning at address 0x0800:0000 and\n * 192Kb of SRAM. SRAM is split up into three blocks:\n *\n * 1) 112Kb of SRAM beginning at address 0x2000:0000\n * 2)  16Kb of SRAM beginning at address 0x2001:c000\n * 3)  64Kb of TCM SRAM beginning at address 0x1000:0000\n *\n * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000\n * where the code expects to begin execution by jumping to the entry point in\n * the 0x0800:0000 address range.\n *\n * HWF4: In the original linker script, the first 0x4000 of flash was\n * reserved for the bootloader.  For now, we'll place the application\n * at the start of flash until we start using a boot loader again.\n *\/\n\nMEMORY\n{\n\/*  flash (rx)   : ORIGIN = 0x08004000, LENGTH = 1008K *\/\n  flash (rx)   : ORIGIN = 0x08000000, LENGTH = 1024K\n  sram (rwx)   : ORIGIN = 0x20000000, LENGTH = 128K\n  ccsram (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Top of the user mode stack. *\/\n_estack = 0x20020000;           \/* top of 128KiB of SRAM *\/\n\n\/* Error in the linker if heap and stack don't fit. *\/\n_min_heap_size = 0;\n_min_stack_size = 0x400;\n\nOUTPUT_ARCH(arm)\n\nENTRY(Reset_Handler)\n\n\/*\n * Ensure that abort() is present in the final object.  The exception handling\n * code pulled in by libgcc.a requires it (and that code cannot be easily avoided).\n *\/\n\/* EXTERN(abort) *\/\n\nSECTIONS\n{\n  \/* Place startup code at start of flash. *\/\n  .isr_vector : {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))\n    . = ALIGN(4);\n  } > flash\n\n  \/* Program code and constant data. *\/\n  .text : {\n    *(.text .text.*)\n    *(.fixup)\n    *(.gnu.warning)\n    *(.rodata .rodata.*)\n    *(.glue_7)\n    *(.glue_7t)\n    *(.eh_frame)\n    *(.gnu.linkonce.t.*)\n    *(.got)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.r.*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    . = ALIGN(4);\n    _etext = ABSOLUTE(.);\n  } > flash\n\n  .ARM.extab : {\n    *(.ARM.extab*)\n  } > flash\n\n  __exidx_start = ABSOLUTE(.);\n  .ARM.exidx : {\n    *(.ARM.exidx*)\n  } > flash\n  __exidx_end = ABSOLUTE(.);\n\n  .preinit_array : {\n    PROVIDE_HIDDEN(__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN(__preinit_array_end = .);\n  } > flash\n\n  .init_array : {\n    PROVIDE_HIDDEN(__init_array_start = .);\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN(__init_array_end = .);\n  } > flash\n\n  .ctors : {\n    KEEP(*crtbegin.o(.ctors))\n    KEEP(*crtbegin?.o(.ctors))\n    KEEP(*(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors))\n    KEEP(*(SORT(.ctors.*)))\n    KEEP(*(.ctors))\n  } > flash\n\n  _sidata = ABSOLUTE(.);\n\n  .data : {\n    _sdata = ABSOLUTE(.);\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    CONSTRUCTORS\n    _edata = ABSOLUTE(.);\n  } > sram AT > flash\n\n  . = ALIGN(4);\n  .bss : {\n    _sbss = ABSOLUTE(.);\n    __bss_start__ = ABSOLUTE(_sbss);\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n    _ebss = ABSOLUTE(.);\n    __bss_end__ = ABSOLUTE(_ebss);\n  } > sram\n\n  ._user_heap_stack : {\n    . = ALIGN(4);\n    PROVIDE(end = .);\n    PROVIDE(_end = .);\n    . = . + _min_heap_size;\n    . = . + _min_stack_size;\n    . = ALIGN(4);\n  } > sram\n\n  \/* Stabs debugging sections. *\/\n  .stab 0 : { *(.stab) }\n  .stabstr 0 : { *(.stabstr) }\n  .stab.excl 0 : { *(.stab.excl) }\n  .stab.exclstr 0 : { *(.stab.exclstr) }\n  .stab.index 0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment 0 : { *(.comment) }\n  .debug_abbrev 0 : { *(.debug_abbrev) }\n  .debug_info 0 : { *(.debug_info) }\n  .debug_line 0 : { *(.debug_line) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  .debug_aranges 0 : { *(.debug_aranges) }\n\n  \/DISCARD\/ : {\n    libc.a (*)\n    libm.a (*)\n    libgcc.a (*)\n  }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"ea96984fe567c0729b88f2b6f50ae2cea3e4184f","subject":"update: append data flash size","message":"update: append data flash size\n","repos":"hirakuni45\/RL78,hirakuni45\/RL78,hirakuni45\/RL78","old_file":"G13\/R5F100LE.ld","new_file":"G13\/R5F100LE.ld","new_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/G13, 64K Flash, 4K RAM, 4K DataFlash *\/\n\/* R5F100LEAFB:  64K (0x00000 - 0x0FFFF) \/  4K (0xFEF00 - 0xFFEFF) \/ 4K (0xF1000 - 0xF1FFF) *\/\n\/* DataFlash Library(FDL T04) used self-ram: 0xFEF00 to 0xFEF87 (136 bytes) *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007C\n\tOPT (r)   : ORIGIN = 0x000C0, LENGTH = 0x00004\n\tSEC_ID (r): ORIGIN = 0x000C4, LENGTH = 0x0000A\n\tROM (r)   : ORIGIN = 0x000D8, LENGTH = 0x0FF28\n\tRAM (w)   : ORIGIN = 0xFEF88, LENGTH = 0x00E98\n\tDATAF (W) : ORIGIN = 0xF1000, LENGTH = 0x01000\n\tSTACK (w) : ORIGIN = 0xFFE20, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n\n  .opt :\n  {\n    KEEP(*(.opt))\n  } > OPT\n\n  .sec_id :\n  {\n    KEEP(*(.sec_id))\n  } > SEC_ID\n\n  \/* CubeSuite always starts at 0xd8.  *\/\n  .csstart : {\n    *(.csstart)\n  } > ROM\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n\t.rodata (MAX(__romdatastart + __romdatacopysize, 0x2000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n\tPROVIDE (__dataflashsize = .);\n\tSHORT(LENGTH(DATAF));\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    PROVIDE (__ctor_start = .);\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    PROVIDE (__ctor_end = .);\n\n    PROVIDE (__dtor_start = .);\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    PROVIDE (__dtor_end = .);\n  } > ROM\n\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    *(PFDL_COD)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .hightext : {\n    *(.hightext)\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009,2011 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rl78)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This is for an RL78\/G13, 64K Flash, 4K RAM, 4K DataFlash *\/\n\/* R5F100LEAFB:  64K (0x00000 - 0x0FFFF) \/  4K (0xFEF00 - 0xFFEFF) \/ 4K (0xF1000 - 0xF1FFF) *\/\n\/* DataFlash Library(FDL T04) used self-ram: 0xFEF00 to 0xFEF87 (136 bytes) *\/\nMEMORY {\n\tVEC (r)   : ORIGIN = 0x00000, LENGTH = 0x00002\n\tIVEC (r)  : ORIGIN = 0x00004, LENGTH = 0x0007C\n\tOPT (r)   : ORIGIN = 0x000C0, LENGTH = 0x00004\n\tSEC_ID (r): ORIGIN = 0x000C4, LENGTH = 0x0000A\n\tROM (r)   : ORIGIN = 0x000D8, LENGTH = 0x0FF28\n\tRAM (w)   : ORIGIN = 0xFEF88, LENGTH = 0x00E98\n\tSTACK (w) : ORIGIN = 0xFFE20, LENGTH = 0x00002\n}\n\nSECTIONS\n{\n  .vec :\n  {\n    KEEP(*(.vec))\n  } > VEC\n\n  .ivec :\n  {\n    KEEP(*(.ivec))\n  } > IVEC\n\n  .opt :\n  {\n    KEEP(*(.opt))\n  } > OPT\n\n  .sec_id :\n  {\n    KEEP(*(.sec_id))\n  } > SEC_ID\n\n  \/* CubeSuite always starts at 0xd8.  *\/\n  .csstart : {\n    *(.csstart)\n  } > ROM\n\n  \/* For code that must be in the first 64k, or could fill unused\n     space below .rodata.  *\/\n  .lowtext : {\n    *(.plt)\n    *(.lowtext)\n  } > ROM\n\n  .data : {\n    . = ALIGN(2);\n    PROVIDE (__datastart = .);\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(2);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that crt0 assumes this is a multiple of two; all the\n     start\/stop symbols are also assumed word-aligned.  *\/\n  PROVIDE(__romdatastart = LOADADDR(.data));\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(2);\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n\t.rodata (MAX(__romdatastart + __romdatacopysize, 0x2000)) : {\n    . = ALIGN(2);\n    *(.plt)\n    *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    PROVIDE (__ctor_start = .);\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    PROVIDE (__ctor_end = .);\n\n    PROVIDE (__dtor_start = .);\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    PROVIDE (__dtor_end = .);\n  } > ROM\n\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    *(PFDL_COD)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .hightext : {\n    *(.hightext)\n  } > ROM\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c7b703a7431ef511466edc32f37995c803ad2225","subject":"fix typo for wrong file path in artik053\/flash.ld","message":"fix typo for wrong file path in artik053\/flash.ld\n","repos":"jeongchanKim\/TizenRT,davidfather\/TizenRT,chanijjani\/TizenRT,shivgarg\/TizenRT,shivgarg\/TizenRT,an4967\/TizenRT,pillip8282\/TizenRT,Parkjihooni6186\/TizenRT,btheosam\/TizenRT,pillip8282\/TizenRT,chanijjani\/TizenRT,jeongchanKim\/TizenRT,davidfather\/TizenRT,sunghan-chang\/TizenRT,junmin-kim\/TizenRT,sunghan-chang\/TizenRT,Samsung\/TizenRT,an4967\/TizenRT,HONGCHAEHEE\/TizenRT,jsdosa\/TizenRT,junmin-kim\/TizenRT,yashwanth686007\/TizenRTOS,shivgarg\/TizenRT,sangwon03\/TizenRT,sunghan-chang\/TizenRT,JeongJunSik\/TizenRT,junmin-kim\/TizenRT,shivgarg\/TizenRT,jeongarmy\/TizenRT,heejin-kim\/TizenRT,pillip8282\/TizenRT,pillip8282\/TizenRT,yashwanth686007\/TizenRTOS,Parkjihooni6186\/TizenRT,jeongarmy\/TizenRT,sangwon03\/TizenRT,Samsung\/TizenRT,yashwanth686007\/TizenRTOS,JeonginKim\/TizenRT,pillip8282\/TizenRT,sunghan-chang\/TizenRT,chanijjani\/TizenRT,yashwanth686007\/TizenRTOS,btheosam\/TizenRT,pillip8282\/TizenRT,junmin-kim\/TizenRT,junmin-kim\/TizenRT,JeonginKim\/TizenRT,davidfather\/TizenRT,sangwon03\/TizenRT,lokeshbv\/TizenRT,sangwon03\/TizenRT,Samsung\/TizenRT,JeonginKim\/TizenRT,Parkjihooni6186\/TizenRT,heejin-kim\/TizenRT,JeongJunSik\/TizenRT,jsdosa\/TizenRT,JeongJunSik\/TizenRT,JeonginKim\/TizenRT,chanijjani\/TizenRT,jeongarmy\/TizenRT,JeongJunSik\/TizenRT,jsdosa\/TizenRT,an4967\/TizenRT,junmin-kim\/TizenRT,Parkjihooni6186\/TizenRT,heejin-kim\/TizenRT,btheosam\/TizenRT,Samsung\/TizenRT,jsdosa\/TizenRT,shivgarg\/TizenRT,HONGCHAEHEE\/TizenRT,chanijjani\/TizenRT,HONGCHAEHEE\/TizenRT,an4967\/TizenRT,lokeshbv\/TizenRT,HONGCHAEHEE\/TizenRT,Samsung\/TizenRT,chanijjani\/TizenRT,btheosam\/TizenRT,HONGCHAEHEE\/TizenRT,jsdosa\/TizenRT,sunghan-chang\/TizenRT,JeongJunSik\/TizenRT,jeongarmy\/TizenRT,sangwon03\/TizenRT,junmin-kim\/TizenRT,Samsung\/TizenRT,jeongarmy\/TizenRT,sunghan-chang\/TizenRT,jeongchanKim\/TizenRT,davidfather\/TizenRT,chanijjani\/TizenRT,davidfather\/TizenRT,Parkjihooni6186\/TizenRT,shivgarg\/TizenRT,heejin-kim\/TizenRT,davidfather\/TizenRT,JeonginKim\/TizenRT,jeongarmy\/TizenRT,btheosam\/TizenRT,jeongchanKim\/TizenRT,yashwanth686007\/TizenRTOS,jeongchanKim\/TizenRT,heejin-kim\/TizenRT,sunghan-chang\/TizenRT,JeonginKim\/TizenRT,btheosam\/TizenRT,pillip8282\/TizenRT,Parkjihooni6186\/TizenRT,yashwanth686007\/TizenRTOS,an4967\/TizenRT,jeongarmy\/TizenRT,lokeshbv\/TizenRT,sangwon03\/TizenRT,lokeshbv\/TizenRT,jeongchanKim\/TizenRT,HONGCHAEHEE\/TizenRT,an4967\/TizenRT,heejin-kim\/TizenRT,JeongJunSik\/TizenRT,jsdosa\/TizenRT,jsdosa\/TizenRT,an4967\/TizenRT,lokeshbv\/TizenRT,lokeshbv\/TizenRT,jeongchanKim\/TizenRT,Samsung\/TizenRT,davidfather\/TizenRT","old_file":"build\/configs\/artik053\/scripts\/flash.ld","new_file":"build\/configs\/artik053\/scripts\/flash.ld","new_contents":"\/****************************************************************************\n *\n * Copyright 2017 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * configs\/artik053\/scripts\/flash.ld\n *\n *   Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *           Laurent Latil <laurent@latil.nom.fr>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nMEMORY\n{\n\tFLASH\t(rx)\t: ORIGIN = 0x040C8000, LENGTH = 2400K\n\tSRAM\t(rwx)\t: ORIGIN = 0x02023800, LENGTH = 946K\n}\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_stext)\nSECTIONS\n{\n\t.header : {\n\t\t_start = .;\n\t\tLONG((_end - _start) \/ 512);\n\t\tLONG(0);\n\t\tLONG(0x656d6264);\n\t\t. = ALIGN(0x20);\n\t} > FLASH =0x0\n\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > FLASH\n\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\t*(.init_array .init_array.*)\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > SRAM AT > FLASH\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > SRAM\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.padding : {\n\t\t. = ALIGN(512);\n\t\t. = . + 1020;\n\t\tLONG(0);\n\t\t_end = .;\n\t} > FLASH =0x0\n}\n","old_contents":"\/****************************************************************************\n *\n * Copyright 2017 Samsung Electronics All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * configs\/sidk_s5jt200\/scripts\/ld_s5jt200_flash.script\n *\n *   Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *           Laurent Latil <laurent@latil.nom.fr>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name NuttX nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\nMEMORY\n{\n\tFLASH\t(rx)\t: ORIGIN = 0x040C8000, LENGTH = 2400K\n\tSRAM\t(rwx)\t: ORIGIN = 0x02023800, LENGTH = 946K\n}\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_stext)\nSECTIONS\n{\n\t.header : {\n\t\t_start = .;\n\t\tLONG((_end - _start) \/ 512);\n\t\tLONG(0);\n\t\tLONG(0x656d6264);\n\t\t. = ALIGN(0x20);\n\t} > FLASH =0x0\n\n\t.text : {\n\t\t_stext = ABSOLUTE(.);\n\t\t*(.vectors)\n\t\t*(.text .text.*)\n\t\t*(.fixup)\n\t\t*(.gnu.warning)\n\t\t*(.rodata .rodata.*)\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.glue_7)\n\t\t*(.glue_7t)\n\t\t*(.got)\n\t\t*(.gcc_except_table)\n\t\t*(.gnu.linkonce.r.*)\n\t\t_etext = ABSOLUTE(.);\n\t} > FLASH\n\n\t.init_section : {\n\t\t_sinit = ABSOLUTE(.);\n\t\t*(.init_array .init_array.*)\n\t\t_einit = ABSOLUTE(.);\n\t} > FLASH\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} > FLASH\n\n\t__exidx_start = ABSOLUTE(.);\n\t.ARM.exidx : {\n\t\t*(.ARM.exidx*)\n\t} > FLASH\n\t__exidx_end = ABSOLUTE(.);\n\n\t_eronly = ABSOLUTE(.);\n\n\t.data : {\n\t\t_sdata = ABSOLUTE(.);\n\t\t*(.data .data.*)\n\t\t*(.gnu.linkonce.d.*)\n\t\tCONSTRUCTORS\n\t\t_edata = ABSOLUTE(.);\n\t} > SRAM AT > FLASH\n\n\t.bss : {\n\t\t_sbss = ABSOLUTE(.);\n\t\t*(.bss .bss.*)\n\t\t*(.gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = ABSOLUTE(.);\n\t} > SRAM\n\n\t\/* Stabs debugging sections. *\/\n\t.stab 0 : { *(.stab) }\n\t.stabstr 0 : { *(.stabstr) }\n\t.stab.excl 0 : { *(.stab.excl) }\n\t.stab.exclstr 0 : { *(.stab.exclstr) }\n\t.stab.index 0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment 0 : { *(.comment) }\n\t.debug_abbrev 0 : { *(.debug_abbrev) }\n\t.debug_info 0 : { *(.debug_info) }\n\t.debug_line 0 : { *(.debug_line) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\n\t.padding : {\n\t\t. = ALIGN(512);\n\t\t. = . + 1020;\n\t\tLONG(0);\n\t\t_end = .;\n\t} > FLASH =0x0\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"300a56b8cfa7906aa98a348d82678c0f5df71993","subject":"Fix-up linker definition file","message":"Fix-up linker definition file\n","repos":"zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder,zorxx\/micro-builder","old_file":"include\/esp8266\/ld\/eagle.app.v6.common.ld","new_file":"include\/esp8266\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);\t\t\/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *.c.o(.literal*, .text*)\n    *.cpp.o(.literal*, .text*)\n    *.a:(.literal .text .literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"367c084c4beb62e16c5fb4dccd8e55e950bc2f1d","subject":"stmhal: Fix typo in stm32f401.ld file, regarding flash size.","message":"stmhal: Fix typo in stm32f401.ld file, regarding flash size.\n","repos":"swegener\/micropython,ganshun666\/micropython,Peetz0r\/micropython-esp32,hiway\/micropython,adafruit\/circuitpython,drrk\/micropython,torwag\/micropython,henriknelson\/micropython,PappaPeppar\/micropython,tobbad\/micropython,bvernoux\/micropython,matthewelse\/micropython,infinnovation\/micropython,blazewicz\/micropython,tuc-osg\/micropython,lowRISC\/micropython,SHA2017-badge\/micropython-esp32,TDAbboud\/micropython,infinnovation\/micropython,dxxb\/micropython,MrSurly\/micropython,adafruit\/micropython,Timmenem\/micropython,HenrikSolver\/micropython,ryannathans\/micropython,SHA2017-badge\/micropython-esp32,tralamazza\/micropython,MrSurly\/micropython-esp32,micropython\/micropython-esp32,infinnovation\/micropython,lowRISC\/micropython,jmarcelino\/pycom-micropython,dinau\/micropython,micropython\/micropython-esp32,micropython\/micropython-esp32,puuu\/micropython,mpalomer\/micropython,swegener\/micropython,alex-robbins\/micropython,torwag\/micropython,kerneltask\/micropython,swegener\/micropython,AriZuu\/micropython,tralamazza\/micropython,Timmenem\/micropython,selste\/micropython,dxxb\/micropython,praemdonck\/micropython,hiway\/micropython,pfalcon\/micropython,drrk\/micropython,dinau\/micropython,pozetroninc\/micropython,praemdonck\/micropython,chrisdearman\/micropython,ryannathans\/micropython,jmarcelino\/pycom-micropython,emfcamp\/micropython,pozetroninc\/micropython,HenrikSolver\/micropython,blazewicz\/micropython,SHA2017-badge\/micropython-esp32,pozetroninc\/micropython,Peetz0r\/micropython-esp32,mpalomer\/micropython,jmarcelino\/pycom-micropython,bvernoux\/micropython,infinnovation\/micropython,turbinenreiter\/micropython,matthewelse\/micropython,mhoffma\/micropython,trezor\/micropython,hiway\/micropython,blazewicz\/micropython,dxxb\/micropython,Peetz0r\/micropython-esp32,kerneltask\/micropython,oopy\/micropython,tuc-osg\/micropython,cwyark\/micropython,pramasoul\/micropython,tuc-osg\/micropython,ganshun666\/micropython,chrisdearman\/micropython,TDAbboud\/micropython,swegener\/micropython,puuu\/micropython,alex-march\/micropython,lowRISC\/micropython,mhoffma\/micropython,AriZuu\/micropython,selste\/micropython,redbear\/micropython,alex-robbins\/micropython,adafruit\/circuitpython,pramasoul\/micropython,selste\/micropython,adafruit\/micropython,micropython\/micropython-esp32,adafruit\/circuitpython,matthewelse\/micropython,PappaPeppar\/micropython,swegener\/micropython,pfalcon\/micropython,MrSurly\/micropython-esp32,toolmacher\/micropython,lowRISC\/micropython,selste\/micropython,PappaPeppar\/micropython,cwyark\/micropython,MrSurly\/micropython-esp32,dmazzella\/micropython,toolmacher\/micropython,drrk\/micropython,tuc-osg\/micropython,HenrikSolver\/micropython,dinau\/micropython,HenrikSolver\/micropython,ganshun666\/micropython,cwyark\/micropython,AriZuu\/micropython,pfalcon\/micropython,emfcamp\/micropython,tralamazza\/micropython,emfcamp\/micropython,torwag\/micropython,AriZuu\/micropython,redbear\/micropython,mpalomer\/micropython,kerneltask\/micropython,PappaPeppar\/micropython,adafruit\/circuitpython,tobbad\/micropython,cwyark\/micropython,Timmenem\/micropython,kerneltask\/micropython,dmazzella\/micropython,Timmenem\/micropython,redbear\/micropython,alex-march\/micropython,oopy\/micropython,jmarcelino\/pycom-micropython,Peetz0r\/micropython-esp32,pramasoul\/micropython,MrSurly\/micropython,adafruit\/micropython,matthewelse\/micropython,pozetroninc\/micropython,pozetroninc\/micropython,misterdanb\/micropython,dinau\/micropython,MrSurly\/micropython,hosaka\/micropython,redbear\/micropython,turbinenreiter\/micropython,misterdanb\/micropython,MrSurly\/micropython-esp32,oopy\/micropython,alex-robbins\/micropython,hosaka\/micropython,hiway\/micropython,SHA2017-badge\/micropython-esp32,turbinenreiter\/micropython,bvernoux\/micropython,deshipu\/micropython,PappaPeppar\/micropython,bvernoux\/micropython,alex-march\/micropython,matthewelse\/micropython,ryannathans\/micropython,alex-robbins\/micropython,toolmacher\/micropython,Timmenem\/micropython,henriknelson\/micropython,torwag\/micropython,toolmacher\/micropython,mhoffma\/micropython,MrSurly\/micropython,tobbad\/micropython,pramasoul\/micropython,mhoffma\/micropython,oopy\/micropython,cwyark\/micropython,jmarcelino\/pycom-micropython,dmazzella\/micropython,misterdanb\/micropython,adafruit\/circuitpython,SHA2017-badge\/micropython-esp32,tobbad\/micropython,tobbad\/micropython,MrSurly\/micropython,pfalcon\/micropython,bvernoux\/micropython,kerneltask\/micropython,hosaka\/micropython,dxxb\/micropython,deshipu\/micropython,turbinenreiter\/micropython,praemdonck\/micropython,toolmacher\/micropython,hosaka\/micropython,henriknelson\/micropython,dinau\/micropython,ryannathans\/micropython,MrSurly\/micropython-esp32,TDAbboud\/micropython,drrk\/micropython,puuu\/micropython,henriknelson\/micropython,dmazzella\/micropython,chrisdearman\/micropython,chrisdearman\/micropython,adafruit\/micropython,Peetz0r\/micropython-esp32,emfcamp\/micropython,misterdanb\/micropython,pfalcon\/micropython,mpalomer\/micropython,drrk\/micropython,emfcamp\/micropython,AriZuu\/micropython,henriknelson\/micropython,chrisdearman\/micropython,puuu\/micropython,deshipu\/micropython,infinnovation\/micropython,puuu\/micropython,TDAbboud\/micropython,turbinenreiter\/micropython,pramasoul\/micropython,selste\/micropython,ganshun666\/micropython,trezor\/micropython,praemdonck\/micropython,deshipu\/micropython,ryannathans\/micropython,matthewelse\/micropython,tuc-osg\/micropython,alex-march\/micropython,adafruit\/circuitpython,hosaka\/micropython,alex-robbins\/micropython,HenrikSolver\/micropython,hiway\/micropython,dxxb\/micropython,praemdonck\/micropython,mhoffma\/micropython,TDAbboud\/micropython,ganshun666\/micropython,misterdanb\/micropython,adafruit\/micropython,tralamazza\/micropython,deshipu\/micropython,lowRISC\/micropython,blazewicz\/micropython,oopy\/micropython,mpalomer\/micropython,alex-march\/micropython,micropython\/micropython-esp32,blazewicz\/micropython,redbear\/micropython,trezor\/micropython,trezor\/micropython,trezor\/micropython,torwag\/micropython","old_file":"stmhal\/boards\/stm32f401.ld","new_file":"stmhal\/boards\/stm32f401.ld","new_contents":"\/*\n    GNU linker script for STM32F401\n*\/\n\n\/* Specify the memory areas *\/\n\/* TODO verify these regions *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 \/* sector 0, 16 KiB *\/\n                                                             \/* sectors 1,2,3 are 16K, 4 is 64K (for filesystem) *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x080000 \/* sectors 5,6,7 3*128KiB = 384 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x018000 \/* 96 KiB *\/\n}\n\nENTRY(Reset_Handler)\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20014000; \/* tunable *\/\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        \/* This first flash block is 16K annd the isr vectors only take up\n           about 400 bytes. So we pull in a couple of object files to pad it\n           out. *\/\n\n        . = ALIGN(4);\n        *\/ff.o(.text*)\n        *\/stm32f4xx_hal_sd.o(.text*)\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n   \n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n     \n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n        \n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n        \n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT> FLASH_TEXT\n            \n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\tPROVIDE ( end = . );\n\tPROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/*\n    GNU linker script for STM32F401\n*\/\n\n\/* Specify the memory areas *\/\n\/* TODO verify these regions *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 0x080000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 0x004000 \/* sector 0, 16 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x080000 \/* sectors 5,6,7,8, 4*128KiB = 512 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x018000 \/* 96 KiB *\/\n}\n\nENTRY(Reset_Handler)\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* Define tho top end of the stack.  The stack is full descending so begins just\n   above last byte of RAM.  Note that EABI requires the stack to be 8-byte\n   aligned for a call. *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20014000; \/* tunable *\/\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The startup code goes first into FLASH *\/\n    .isr_vector :\n    {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector)) \/* Startup code *\/\n\n        \/* This first flash block is 16K annd the isr vectors only take up\n           about 400 bytes. So we pull in a couple of object files to pad it\n           out. *\/\n\n        . = ALIGN(4);\n        *\/ff.o(.text*)\n        *\/stm32f4xx_hal_sd.o(.text*)\n\n        . = ALIGN(4);\n    } >FLASH_ISR\n   \n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    \/*  *(.glue_7)   *\/    \/* glue arm to thumb code *\/\n    \/*  *(.glue_7t)  *\/    \/* glue thumb to arm code *\/\n\n        . = ALIGN(4);\n        _etext = .;        \/* define a global symbol at end of code *\/\n    } >FLASH_TEXT\n     \n    \/*\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } >FLASH\n\n    .ARM :\n    {\n        __exidx_start = .;\n        *(.ARM.exidx*)\n        __exidx_end = .;\n    } >FLASH\n    *\/\n        \n    \/* used by the startup to initialize data *\/\n    _sidata = LOADADDR(.data);\n        \n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. *\/\n    .data :\n    {\n        . = ALIGN(4);\n        _sdata = .;        \/* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM *\/\n        _ram_start = .;    \/* create a global symbol at ram start for garbage collector *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _edata = .;        \/* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM *\/\n    } >RAM AT> FLASH_TEXT\n            \n    \/* Uninitialized data section *\/\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         \/* define a global symbol at bss end; used by startup code and GC *\/\n    } >RAM\n\n    \/* this is to define the start of the heap, and make sure we have a minimum size *\/\n    .heap :\n    {\n        . = ALIGN(4);\n\tPROVIDE ( end = . );\n\tPROVIDE ( _end = . );\n        _heap_start = .;    \/* define a global symbol at heap start *\/\n        . = . + _minimum_heap_size;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the stack *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + _minimum_stack_size;\n        . = ALIGN(4);\n    } >RAM\n\n    \/* Remove information from the standard libraries *\/\n    \/*\n    \/DISCARD\/ :\n    {\n        libc.a ( * )\n        libm.a ( * )\n        libgcc.a ( * )\n    }\n    *\/\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0e018872e72f2237147a0086075bfc788384ed9c","subject":"cleanup linker","message":"cleanup linker\n","repos":"jezze\/fudge,jezze\/fudge,jezze\/fudge","old_file":"linker-arm.ld","new_file":"linker-arm.ld","new_contents":"ENTRY (loader)\n\nSECTIONS\n{\n\n    . = 0x0;\n\n    .text :\n    {\n        *(.text)\n        *(.rodata)\n    }\n\n    .data :\n    {\n        *(.data)\n    }\n\n    .bss :\n    {\n        *(.bss)\n    }\n\n}\n","old_contents":"ENTRY (loader)\n\nSECTIONS\n{\n\n\t. = 0x0;\n\n\t.text :\n\t{\n\t\t*(.text)\n\t\t*(.rodata)\n\t}\n\n\t.data :\n\t{\n\t\t*(.data)\n\t}\n\n\t.bss :\n\t{\n        *(.bss)\n\t}\n\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"abdb8785cb177577d3f7f9d308cf47fcf2c58352","subject":"linker: riscv: Disable creating ROM domain by config option.","message":"linker: riscv: Disable creating ROM domain by config option.\n\nPatch is useful for RISCV platforms which can not provide ROM memory.\nSwitching CONFIG_XIP to \"n\" disables allocating ROM region.\n\nSigned-off-by: Vitaly Gaiduk <2385ca62c0788ff08a50dc4be712cde808e4823e@cloudbear.ru>\n","repos":"galak\/zephyr,explora26\/zephyr,punitvara\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,ldts\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,ldts\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,nashif\/zephyr,galak\/zephyr,Vudentz\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,explora26\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,punitvara\/zephyr,punitvara\/zephyr,punitvara\/zephyr,ldts\/zephyr,explora26\/zephyr,nashif\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,nashif\/zephyr,Vudentz\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/riscv32\/common\/linker.ld","new_file":"include\/arch\/riscv32\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv32 platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <soc.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\t\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(\".noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv32 platform\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <soc.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nMEMORY\n{\n    ROM (rx)  : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE\n    RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROM)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROM)\n\n    GROUP_END(ROM)\n\n    GROUP_START(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\t\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_rom_end = .;\n    __data_rom_start = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t *(.noinit)\n\t\t *(\".noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"62683863e8621cef35e94c9dcfe5abcaf996d7a2","subject":"remove a duplicate alias definition.","message":"remove a duplicate alias definition.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/ti-cc3220sf-generic\/memory_map.ld","new_file":"boards\/ti-cc3220sf-generic\/memory_map.ld","new_contents":"___total_ram = 256K;\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x01000800, LENGTH = 1022K\n  RAM  (rwx) : ORIGIN = 0x20000000, LENGTH = 256K\n  \/* used in the presence of a bootloader *\/\n  FLASH_APP (rx) : ORIGIN = 0x0100c000, LENGTH = 464K\n  \/* used for the debug signature when flashing an app binary directly *\/\n  FLASH_HDR (rx) : ORIGIN = 0x01000000, LENGTH = 2K\n}\n\nREGION_ALIAS(\"REGION_RAM\", RAM);\n\n\/* TODO: the bootloader specific defines need to be revised once we know how the bootloader will work at all. *\/\n__application_code_start = ORIGIN(RAM);\n__application_code_end = ORIGIN(RAM) + LENGTH(RAM);\n__app_header_address = ORIGIN(RAM) + 0x270;\n__bootloader_magic_ptr = 0x4402FC24;\n\/* This pointer will be written to the SP register at reset. *\/\nPROVIDE(__stack = ORIGIN(RAM) + LENGTH(RAM) - 4);\n__cs3_heap_end = ORIGIN(RAM) + LENGTH(RAM);\n","old_contents":"___total_ram = 256K;\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x01000800, LENGTH = 1022K\n  RAM  (rwx) : ORIGIN = 0x20000000, LENGTH = 256K\n  \/* used in the presence of a bootloader *\/\n  FLASH_APP (rx) : ORIGIN = 0x0100c000, LENGTH = 464K\n  \/* used for the debug signature when flashing an app binary directly *\/\n  FLASH_HDR (rx) : ORIGIN = 0x01000000, LENGTH = 2K\n}\n\nREGION_ALIAS(\"REGION_PGM\", RAM);\nREGION_ALIAS(\"REGION_RAM\", RAM);\n\n\/* TODO: the bootloader specific defines need to be revised once we know how the bootloader will work at all. *\/\n__application_code_start = ORIGIN(RAM);\n__application_code_end = ORIGIN(RAM) + LENGTH(RAM);\n__app_header_address = ORIGIN(RAM) + 0x270;\n__bootloader_magic_ptr = 0x4402FC24;\n\/* This pointer will be written to the SP register at reset. *\/\nPROVIDE(__stack = ORIGIN(RAM) + LENGTH(RAM) - 4);\n__cs3_heap_end = ORIGIN(RAM) + LENGTH(RAM);\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"adf8c286b6291c6945664c50005771f6faa00a4a","subject":"Require change for GCC version 6","message":"Require change for GCC version 6\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/src\/gcc_arm_flash.ld","new_file":"ARM\/src\/gcc_arm_flash.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"unknown","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"fe4eb545c0b213537eef754c6adc836a5e5bdaea","subject":"cc2538: Remove the unused vtable section","message":"cc2538: Remove the unused vtable section\n\nSigned-off-by: Beno\u00eet Th\u00e9baudeau <835bc8b01b82c0117127b72626b289641d7633e2@advansee.com>\n","repos":"arurke\/contiki,arurke\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,arurke\/contiki,arurke\/contiki,arurke\/contiki,arurke\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,MohamedSeliem\/contiki,bluerover\/6lbr,bluerover\/6lbr,bluerover\/6lbr,MohamedSeliem\/contiki,bluerover\/6lbr,MohamedSeliem\/contiki","old_file":"cpu\/cc2538\/cc2538.lds","new_file":"cpu\/cc2538\/cc2538.lds","new_contents":"\/*\n * Copyright (c) 2013, Texas Instruments Incorporated - http:\/\/www.ti.com\/\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\/*\n * cc2538 linker configuration file. This is not the actual file used at link\n * stage. Rather, it is used as input for the auto-generation of the actual\n * ld script, which is called cc2538.ld and will be in the project directory\n *\/\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n#define NRSRAM_START    0x20000000\n#define NRSRAM_LEN      0x00004000\n#define SRAM_START      0x20004000\n#define SRAM_LEN        0x00004000\n#else\n#define SRAM_START      0x20000000\n#define SRAM_LEN        0x00008000\n#endif\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x200000, LENGTH = 0x0007FFD4\n    FLASH_CCA (RX) : ORIGIN = 0x0027FFD4, LENGTH = 44\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    NRSRAM (RWX) : ORIGIN = NRSRAM_START, LENGTH = NRSRAM_LEN\n#endif\n    SRAM (RWX) : ORIGIN = SRAM_START, LENGTH = SRAM_LEN\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH= 0\n\n    .socdata (NOLOAD) :\n    {\n        *(.udma_channel_control_table)\n    } > SRAM\n\n    .data :\n    {\n        _data = .;\n        *(.data*)\n        _edata = .;\n    } > SRAM AT > FLASH\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n    } > FLASH\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    .nrdata (NOLOAD) :\n    {\n        _nrdata = .;\n        *(.nrdata*)\n        _enrdata = .;\n    } > NRSRAM\n#endif\n\n    .flashcca :\n    {\n        KEEP(*(.flashcca))\n    } > FLASH_CCA\n}\n","old_contents":"\/*\n * Copyright (c) 2013, Texas Instruments Incorporated - http:\/\/www.ti.com\/\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and\/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n *\/\n\/*\n * cc2538 linker configuration file. This is not the actual file used at link\n * stage. Rather, it is used as input for the auto-generation of the actual\n * ld script, which is called cc2538.ld and will be in the project directory\n *\/\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n#define NRSRAM_START    0x20000000\n#define NRSRAM_LEN      0x00004000\n#define SRAM_START      0x20004000\n#define SRAM_LEN        0x00004000\n#else\n#define SRAM_START      0x20000000\n#define SRAM_LEN        0x00008000\n#endif\n\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x200000, LENGTH = 0x0007FFD4\n    FLASH_CCA (RX) : ORIGIN = 0x0027FFD4, LENGTH = 44\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    NRSRAM (RWX) : ORIGIN = NRSRAM_START, LENGTH = NRSRAM_LEN\n#endif\n    SRAM (RWX) : ORIGIN = SRAM_START, LENGTH = SRAM_LEN\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.vectors))\n        *(.text*)\n        *(.rodata*)\n        _etext = .;\n    } > FLASH= 0\n\n    .socdata (NOLOAD) :\n    {\n        *(.udma_channel_control_table)\n    } > SRAM\n\n    .data :\n    {\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > SRAM AT > FLASH\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n    } > FLASH\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)\n    .nrdata (NOLOAD) :\n    {\n        _nrdata = .;\n        *(.nrdata*)\n        _enrdata = .;\n    } > NRSRAM\n#endif\n\n    .flashcca :\n    {\n        KEEP(*(.flashcca))\n    } > FLASH_CCA\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"f813a0b05b517624853ab87c7f27b77c6d1193d3","subject":"tweak the linker script to allow overrides of init, panic_fmt and ...","message":"tweak the linker script to allow overrides of init, panic_fmt and ...\n\ndefault_exception_handler by *dependencies*\n","repos":"japaric\/f3,japaric\/f3,japaric\/f3,etrombly\/bluepill,etrombly\/bluepill","old_file":"stm32f3discovery.ld","new_file":"stm32f3discovery.ld","new_contents":"MEMORY\n{\n  CCRAM : ORIGIN = 0x10000000, LENGTH = 8K\n  FLASH : ORIGIN = 0x08000000, LENGTH = 256K\n  RAM : ORIGIN = 0x20000000, LENGTH = 40K\n}\n\nENTRY(_reset)\n\nSECTIONS\n{\n  .text ORIGIN(FLASH) :\n  {\n    \/* Vector table *\/\n    LONG(ORIGIN(RAM) + LENGTH(RAM));\n    LONG(_reset + 1);\n    KEEP(*(.text.exceptions));\n    _eexceptions = .;\n    KEEP(*(.text.interrupts));\n    _einterrupts = .;\n\n    \/* Entry point: reset handler *\/\n    _reset = .;\n    KEEP(*(.text._reset));\n\n    *(.text.*);\n    *(.rodata.*);\n  } > FLASH\n\n  .bss : ALIGN(4)\n  {\n    _sbss = .;\n    *(.bss.*);\n    _ebss = ALIGN(4);\n  } > RAM\n\n  .data : ALIGN(4)\n  {\n    _sdata = .;\n    *(.data.*);\n    _edata = ALIGN(4);\n  } > RAM AT > FLASH\n\n  _sidata = LOADADDR(.data);\n\n  \/DISCARD\/ :\n  {\n    *(.ARM.exidx.*)\n  }\n}\n\n\/* HACK to make these symbols overrideable by _dependencies_ (they were already\n   overridable by the top crate), we declare them as undefined (EXTERN) here. *\/\nEXTERN(_default_exception_handler);\nEXTERN(_init);\n\n\/* Exceptions *\/\nPROVIDE(_nmi = _default_exception_handler);\nPROVIDE(_hard_fault = _default_exception_handler);\nPROVIDE(_memmanage_fault = _default_exception_handler);\nPROVIDE(_bus_fault = _default_exception_handler);\nPROVIDE(_usage_fault = _default_exception_handler);\nPROVIDE(_svcall = _default_exception_handler);\nPROVIDE(_pendsv = _default_exception_handler);\nPROVIDE(_systick = _default_exception_handler);\n\n\/* Interrupts *\/\nPROVIDE(_wwdg = _default_exception_handler);\nPROVIDE(_pvd = _default_exception_handler);\nPROVIDE(_tamper_stamp = _default_exception_handler);\nPROVIDE(_rtc_wkup = _default_exception_handler);\nPROVIDE(_flash = _default_exception_handler);\nPROVIDE(_rcc = _default_exception_handler);\nPROVIDE(_exti0 = _default_exception_handler);\nPROVIDE(_exti1 = _default_exception_handler);\nPROVIDE(_exti2_ts = _default_exception_handler);\nPROVIDE(_exti3 = _default_exception_handler);\nPROVIDE(_exti4 = _default_exception_handler);\nPROVIDE(_dma1_channel1 = _default_exception_handler);\nPROVIDE(_dma1_channel2 = _default_exception_handler);\nPROVIDE(_dma1_channel3 = _default_exception_handler);\nPROVIDE(_dma1_channel4 = _default_exception_handler);\nPROVIDE(_dma1_channel5 = _default_exception_handler);\nPROVIDE(_dma1_channel6 = _default_exception_handler);\nPROVIDE(_dma1_channel7 = _default_exception_handler);\nPROVIDE(_adc1_2 = _default_exception_handler);\nPROVIDE(_usb_hp_can_tx = _default_exception_handler);\nPROVIDE(_usb_lp_can_rx0 = _default_exception_handler);\nPROVIDE(_can_rx1 = _default_exception_handler);\nPROVIDE(_can_sce = _default_exception_handler);\nPROVIDE(_exti9_5 = _default_exception_handler);\nPROVIDE(_tim1_brk_tim15 = _default_exception_handler);\nPROVIDE(_tim1_up_tim16 = _default_exception_handler);\nPROVIDE(_tim1_trg_com_tim17 = _default_exception_handler);\nPROVIDE(_tim1_cc = _default_exception_handler);\nPROVIDE(_tim2 = _default_exception_handler);\nPROVIDE(_tim3 = _default_exception_handler);\nPROVIDE(_tim4 = _default_exception_handler);\nPROVIDE(_i2c1_ev = _default_exception_handler);\nPROVIDE(_i2c1_er = _default_exception_handler);\nPROVIDE(_i2c2_ev = _default_exception_handler);\nPROVIDE(_i2c2_er = _default_exception_handler);\nPROVIDE(_spi1 = _default_exception_handler);\nPROVIDE(_spi2 = _default_exception_handler);\nPROVIDE(_usart1 = _default_exception_handler);\nPROVIDE(_usart2 = _default_exception_handler);\nPROVIDE(_usart3 = _default_exception_handler);\nPROVIDE(_exti15_10 = _default_exception_handler);\nPROVIDE(_rtc_alarm = _default_exception_handler);\nPROVIDE(_usb_wake_up = _default_exception_handler);\nPROVIDE(_tim8_brk = _default_exception_handler);\nPROVIDE(_tim8_up = _default_exception_handler);\nPROVIDE(_tim8_trg_com = _default_exception_handler);\nPROVIDE(_tim8_cc = _default_exception_handler);\nPROVIDE(_adc3 = _default_exception_handler);\nPROVIDE(_fmc = _default_exception_handler);\nPROVIDE(_spi3 = _default_exception_handler);\nPROVIDE(_uart4 = _default_exception_handler);\nPROVIDE(_uart5 = _default_exception_handler);\nPROVIDE(_tim6_dac = _default_exception_handler);\nPROVIDE(_tim7 = _default_exception_handler);\nPROVIDE(_dma2_channel1 = _default_exception_handler);\nPROVIDE(_dma2_channel2 = _default_exception_handler);\nPROVIDE(_dma2_channel3 = _default_exception_handler);\nPROVIDE(_dma2_channel4 = _default_exception_handler);\nPROVIDE(_dma2_channel5 = _default_exception_handler);\nPROVIDE(_adc4 = _default_exception_handler);\nPROVIDE(_comp1_2_3 = _default_exception_handler);\nPROVIDE(_comp4_5_6 = _default_exception_handler);\nPROVIDE(_comp7 = _default_exception_handler);\nPROVIDE(_i2c3_ev = _default_exception_handler);\nPROVIDE(_i2c3_er = _default_exception_handler);\nPROVIDE(_usb_hp = _default_exception_handler);\nPROVIDE(_usb_lp = _default_exception_handler);\nPROVIDE(_usb_wake_up_rmp = _default_exception_handler);\nPROVIDE(_tim20_brk = _default_exception_handler);\nPROVIDE(_tim20_up = _default_exception_handler);\nPROVIDE(_tim20_trg_com = _default_exception_handler);\nPROVIDE(_tim20_cc = _default_exception_handler);\nPROVIDE(_fpu = _default_exception_handler);\nPROVIDE(_spi4 = _default_exception_handler);\n\nASSERT(_eexceptions - ORIGIN(FLASH) == 0x40, \"exceptions not linked where expected\");\nASSERT(_einterrupts - ORIGIN(FLASH) == 0x194, \"interrupts not linked where expected\");\n","old_contents":"MEMORY\n{\n  CCRAM : ORIGIN = 0x10000000, LENGTH = 8K\n  FLASH : ORIGIN = 0x08000000, LENGTH = 256K\n  RAM : ORIGIN = 0x20000000, LENGTH = 40K\n}\n\nENTRY(_reset)\n\nSECTIONS\n{\n  .text ORIGIN(FLASH) :\n  {\n    \/* Vector table *\/\n    LONG(ORIGIN(RAM) + LENGTH(RAM));\n    LONG(_reset + 1);\n    KEEP(*(.text.exceptions));\n    _eexceptions = .;\n    KEEP(*(.text.interrupts));\n    _einterrupts = .;\n\n    \/* Entry point: reset handler *\/\n    _reset = .;\n    KEEP(*(.text._reset));\n\n    *(.text.*);\n    *(.rodata.*);\n  } > FLASH\n\n  .bss : ALIGN(4)\n  {\n    _sbss = .;\n    *(.bss.*);\n    _ebss = ALIGN(4);\n  } > RAM\n\n  .data : ALIGN(4)\n  {\n    _sdata = .;\n    *(.data.*);\n    _edata = ALIGN(4);\n  } > RAM AT > FLASH\n\n  _sidata = LOADADDR(.data);\n\n  \/DISCARD\/ :\n  {\n    *(.ARM.exidx.*)\n  }\n}\n\n\/* Exceptions *\/\nPROVIDE(_nmi = _default_exception_handler);\nPROVIDE(_hard_fault = _default_exception_handler);\nPROVIDE(_memmanage_fault = _default_exception_handler);\nPROVIDE(_bus_fault = _default_exception_handler);\nPROVIDE(_usage_fault = _default_exception_handler);\nPROVIDE(_svcall = _default_exception_handler);\nPROVIDE(_pendsv = _default_exception_handler);\nPROVIDE(_systick = _default_exception_handler);\n\n\/* Interrupts *\/\nPROVIDE(_wwdg = _default_exception_handler);\nPROVIDE(_pvd = _default_exception_handler);\nPROVIDE(_tamper_stamp = _default_exception_handler);\nPROVIDE(_rtc_wkup = _default_exception_handler);\nPROVIDE(_flash = _default_exception_handler);\nPROVIDE(_rcc = _default_exception_handler);\nPROVIDE(_exti0 = _default_exception_handler);\nPROVIDE(_exti1 = _default_exception_handler);\nPROVIDE(_exti2_ts = _default_exception_handler);\nPROVIDE(_exti3 = _default_exception_handler);\nPROVIDE(_exti4 = _default_exception_handler);\nPROVIDE(_dma1_channel1 = _default_exception_handler);\nPROVIDE(_dma1_channel2 = _default_exception_handler);\nPROVIDE(_dma1_channel3 = _default_exception_handler);\nPROVIDE(_dma1_channel4 = _default_exception_handler);\nPROVIDE(_dma1_channel5 = _default_exception_handler);\nPROVIDE(_dma1_channel6 = _default_exception_handler);\nPROVIDE(_dma1_channel7 = _default_exception_handler);\nPROVIDE(_adc1_2 = _default_exception_handler);\nPROVIDE(_usb_hp_can_tx = _default_exception_handler);\nPROVIDE(_usb_lp_can_rx0 = _default_exception_handler);\nPROVIDE(_can_rx1 = _default_exception_handler);\nPROVIDE(_can_sce = _default_exception_handler);\nPROVIDE(_exti9_5 = _default_exception_handler);\nPROVIDE(_tim1_brk_tim15 = _default_exception_handler);\nPROVIDE(_tim1_up_tim16 = _default_exception_handler);\nPROVIDE(_tim1_trg_com_tim17 = _default_exception_handler);\nPROVIDE(_tim1_cc = _default_exception_handler);\nPROVIDE(_tim2 = _default_exception_handler);\nPROVIDE(_tim3 = _default_exception_handler);\nPROVIDE(_tim4 = _default_exception_handler);\nPROVIDE(_i2c1_ev = _default_exception_handler);\nPROVIDE(_i2c1_er = _default_exception_handler);\nPROVIDE(_i2c2_ev = _default_exception_handler);\nPROVIDE(_i2c2_er = _default_exception_handler);\nPROVIDE(_spi1 = _default_exception_handler);\nPROVIDE(_spi2 = _default_exception_handler);\nPROVIDE(_usart1 = _default_exception_handler);\nPROVIDE(_usart2 = _default_exception_handler);\nPROVIDE(_usart3 = _default_exception_handler);\nPROVIDE(_exti15_10 = _default_exception_handler);\nPROVIDE(_rtc_alarm = _default_exception_handler);\nPROVIDE(_usb_wake_up = _default_exception_handler);\nPROVIDE(_tim8_brk = _default_exception_handler);\nPROVIDE(_tim8_up = _default_exception_handler);\nPROVIDE(_tim8_trg_com = _default_exception_handler);\nPROVIDE(_tim8_cc = _default_exception_handler);\nPROVIDE(_adc3 = _default_exception_handler);\nPROVIDE(_fmc = _default_exception_handler);\nPROVIDE(_spi3 = _default_exception_handler);\nPROVIDE(_uart4 = _default_exception_handler);\nPROVIDE(_uart5 = _default_exception_handler);\nPROVIDE(_tim6_dac = _default_exception_handler);\nPROVIDE(_tim7 = _default_exception_handler);\nPROVIDE(_dma2_channel1 = _default_exception_handler);\nPROVIDE(_dma2_channel2 = _default_exception_handler);\nPROVIDE(_dma2_channel3 = _default_exception_handler);\nPROVIDE(_dma2_channel4 = _default_exception_handler);\nPROVIDE(_dma2_channel5 = _default_exception_handler);\nPROVIDE(_adc4 = _default_exception_handler);\nPROVIDE(_comp1_2_3 = _default_exception_handler);\nPROVIDE(_comp4_5_6 = _default_exception_handler);\nPROVIDE(_comp7 = _default_exception_handler);\nPROVIDE(_i2c3_ev = _default_exception_handler);\nPROVIDE(_i2c3_er = _default_exception_handler);\nPROVIDE(_usb_hp = _default_exception_handler);\nPROVIDE(_usb_lp = _default_exception_handler);\nPROVIDE(_usb_wake_up_rmp = _default_exception_handler);\nPROVIDE(_tim20_brk = _default_exception_handler);\nPROVIDE(_tim20_up = _default_exception_handler);\nPROVIDE(_tim20_trg_com = _default_exception_handler);\nPROVIDE(_tim20_cc = _default_exception_handler);\nPROVIDE(_fpu = _default_exception_handler);\nPROVIDE(_spi4 = _default_exception_handler);\n\nASSERT(_eexceptions - ORIGIN(FLASH) == 0x40, \"exceptions not linked where expected\");\nASSERT(_einterrupts - ORIGIN(FLASH) == 0x194, \"interrupts not linked where expected\");\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4fd946682d614168c25697f08bd51a78298bf236","subject":"another file to remove","message":"another file to remove\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/qemu-arm\/imx6.ld","new_file":"ports\/qemu-arm\/imx6.ld","new_contents":"","old_contents":"\/* Vector table is at 0x00000000, entry point is 0x10000000. *\/\n\nMEMORY\n{\n    ROM : ORIGIN = 0x00000000, LENGTH = 96K\n    RAM : ORIGIN = 0x10000000, LENGTH = 128M\n}\n\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\nSECTIONS\n{\n    .rom : {\n        . = ALIGN(4);\n        KEEP(*(.isr_vector))\n        . = ALIGN(4);\n    } > ROM\n\n    .text : {\n        . = ALIGN(4);\n        *(.text.Reset_Handler)\n        *(.text*)\n        *(.rodata*)\n        . = ALIGN(4);\n        _etext = .;\n        _sidata = _etext;\n    } > RAM\n\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;\n        *(.data*)\n        . = ALIGN(4);\n        _edata = .;\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = .;\n    } > RAM\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"7987653034f7b779bfd18bcad5c7f3b48e910ad3","subject":"adjust alignment of section .comp_text","message":"adjust alignment of section .comp_text\n","repos":"kaiyuanl\/gem5,kaiyuanl\/gem5,kaiyuanl\/gem5,kaiyuanl\/gem5,kaiyuanl\/gem5,kaiyuanl\/gem5,kaiyuanl\/gem5","old_file":"testprogram\/isoxld.ld","new_file":"testprogram\/isoxld.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSEARCH_DIR(\"\/tools\/lib\"); SEARCH_DIR(\"=\/tools\/arm-unknown-linux-gnueabi\/lib\");\nSECTIONS\n{\n  \/* Read-only sections, merged into text segment: *\/\n  PROVIDE (__executable_start = SEGMENT_START(\"text-segment\", 0x00010000)); . = SEGMENT_START(\"text-segment\", 0x00010000) + SIZEOF_HEADERS;\n\n  .comp_text ALIGN(0x1000)          :\n  {\n    __COMP__ = .;\n    comp.o(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    comp.o(.text.exit .text.exit.*)\n    comp.o(.text.startup .text.startup.*)\n    comp.o(.text.hot .text.hot.*)\n    comp.o(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    comp.o(.gnu.warning)\n    comp.o(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n    . = __COMP__ + 0x1000;\n  }\n   .comp_data           :\n  {\n    PROVIDE (__data_start = .);\n    comp.o(.data .data.* .gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro .rel.data.rel.ro.* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n      PROVIDE_HIDDEN (__rel_iplt_start = .);\n      *(.rel.iplt)\n      PROVIDE_HIDDEN (__rel_iplt_end = .);\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n      *(.rela.ctors)\n      *(.rela.dtors)\n      *(.rela.got)\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n      PROVIDE_HIDDEN (__rela_iplt_start = .);\n      *(.rela.iplt)\n      PROVIDE_HIDDEN (__rela_iplt_end = .);\n    }\n  .rel.plt        :\n    {\n      *(.rel.plt)\n    }\n  .rela.plt       :\n    {\n      *(.rela.plt)\n    }\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  }\n  .plt            : { *(.plt) }\n  .iplt           : { *(.iplt) }\n  .text           :\n  {\n    main.o(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    main.o(.text.exit .text.exit.*)\n    main.o(.text.startup .text.startup.*)\n    main.o(.text.hot .text.hot.*)\n    main.o(.text .stub .text.* .gnu.linkonce.t.*)\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    main.o(.gnu.warning)\n    main.o(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  }\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  }\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) }\n   PROVIDE_HIDDEN (__exidx_start = .);\n  .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n   PROVIDE_HIDDEN (__exidx_end = .);\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table\n  .gcc_except_table.*) }\n  \/* These sections are generated by the Sun\/Oracle C++ compiler.  *\/\n  .exception_ranges   : ONLY_IF_RO { *(.exception_ranges\n  .exception_ranges*) }\n  \/* Adjust the address for the data segment.  We want to adjust up to\n     the same address within the page on the next page up.  *\/\n  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));\n  \/* Exception handling  *\/\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\n  .exception_ranges   : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) }\n  \/* Thread Local Storage sections  *\/\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array ))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array ))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .jcr            : { KEEP (*(.jcr)) }\n  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }\n  .dynamic        : { *(.dynamic) }\n  . = DATA_SEGMENT_RELRO_END (0, .);\n  .got            : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }\n  .data           :\n  {\n    PROVIDE (__data_start = .);\n    main.o(.data .data.* .gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .data1          : { *(.data1) }\n  _edata = .; PROVIDE (edata = .);\n  . = .;\n  __bss_start = .;\n  __bss_start__ = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  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The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }\n  .jcr            : { KEEP (*(.jcr)) }\n  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }\n  .dynamic        : { *(.dynamic) }\n  . = DATA_SEGMENT_RELRO_END (0, .);\n  .got            : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }\n  .data           :\n  {\n    PROVIDE (__data_start = .);\n    main.o(.data .data.* .gnu.linkonce.d.*)\n    SORT(CONSTRUCTORS)\n  }\n  .data1          : { *(.data1) }\n  _edata = .; PROVIDE (edata = .);\n  . = .;\n  __bss_start = .;\n  __bss_start__ = .;\n  .bss            :\n  {\n   *(.dynbss)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   \/* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.\n      FIXME: Why do we need it? When there is no .bss section, we don't\n      pad the .data section.  *\/\n   . = ALIGN(. != 0 ? 32 \/ 8 : 1);\n  }\n  _bss_end__ = . ; __bss_end__ = . ;\n  . = ALIGN(32 \/ 8);\n  . = SEGMENT_START(\"ldata-segment\", .);\n  . = ALIGN(32 \/ 8);\n  __end__ = . ;\n  _end = .; PROVIDE (end = .);\n  . = DATA_SEGMENT_END (.);\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end ) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  \/* DWARF Extension.  *\/\n  .debug_macro    0 : { *(.debug_macro) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"65e7c5c372c5078df671a461b6a8b3174f23cb82","subject":"Update linker script to put every section VMA before __pok_end symbol","message":"Update linker script to put every section VMA before __pok_end symbol\n","repos":"pok-kernel\/pok,pok-kernel\/pok,pok-kernel\/pok,pok-kernel\/pok","old_file":"misc\/ldscripts\/x86\/x86-qemu\/kernel.lds","new_file":"misc\/ldscripts\/x86\/x86-qemu\/kernel.lds","new_contents":"OUTPUT_FORMAT(\"elf32-i386\");\nOUTPUT_ARCH(\"i386\")\nENTRY(_core_entry)\n\nSECTIONS\n{\n\t. = 0x100000;\n\n\t__pok_begin = . ;\n\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t\t*(*got*)\n\t}\n\n\t.rodata :\n\t{\n\t\t*(.rodata)\n\t}\n\n\t.data :\n\t{\n\t\t*(.data*) *(.bss) *(COMMON)\n\n\t\t__archive_begin = .;\n\t\t*(.archive)\n\t\t__archive_end = .;\n\t\t__archive2_begin = .;\n\t\t*(.archive2)\n\t\t__archive2_end = .;\n\t}\n\n\t\/* Nothing must have a VMA greater than __pok_end symbol address *\/\n\t__pok_end = . ;\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-i386\");\nOUTPUT_ARCH(\"i386\")\nENTRY(_core_entry)\n\nSECTIONS\n{\n\t. = 0x100000;\n\n\t__pok_begin = . ;\n\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t}\n\n\t.rodata :\n\t{\n\t\t*(.rodata)\n\t}\n\n\t.data :\n\t{\n\t\t*(.data) *(.bss) *(COMMON)\n\n\t\t__archive_begin = .;\n\t\t*(.archive)\n\t\t__archive_end = .;\n\t\t__archive2_begin = .;\n\t\t*(.archive2)\n\t\t__archive2_end = .;\n\t}\n\n\t__pok_end = . ;\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"171f287acf58e469fa914723f6eda9721ec9fbc2","subject":"\tCorrected INCLUDE directive.","message":"\tCorrected INCLUDE directive.\n","repos":"masilvabustos\/CabbageOS,masilvabustos\/CabbageOS","old_file":"hw\/stm32vldiscovery.ld","new_file":"hw\/stm32vldiscovery.ld","new_contents":"\nINCLUDE stm32f100xb.ld\n\n","old_contents":"\nINCLUDE stm32f100rb.ld\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"a87ae1abee5e7e512fa240f83a6a9b40cd140217","subject":"ls1b: add rt_init section","message":"ls1b: add rt_init section\n","repos":"weety\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,wolfgangz2013\/rt-thread,yongli3\/rt-thread,zhaojuntao\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,igou\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,weety\/rt-thread,AubrCool\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,AubrCool\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,RT-Thread\/rt-thread,yongli3\/rt-thread,weety\/rt-thread,igou\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,FlyLu\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,yongli3\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,wolfgangz2013\/rt-thread,nongxiaoming\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,yongli3\/rt-thread,RT-Thread\/rt-thread,igou\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,zhaojuntao\/rt-thread,wolfgangz2013\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,AubrCool\/rt-thread,FlyLu\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,yongli3\/rt-thread,hezlog\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,weety\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,AubrCool\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread","old_file":"bsp\/ls1bdev\/ls1b_ram.lds","new_file":"bsp\/ls1bdev\/ls1b_ram.lds","new_contents":"\/*\n * File      : ls1b_ram.lds\n * This file is part of RT-Thread RTOS\n * COPYRIGHT (C) 2011, RT-Thread Development Team\n *\n * The license and distribution terms for this file may be\n * found in the file LICENSE in this distribution or at\n * http:\/\/www.rt-thread.org\/license\/LICENSE\n *\n * Change Logs:\n * Date           Author       Notes\n * 2010-05-17     swkyer       first version\n * 2010-09-04     bernard      move the beginning entry to 0x80200000\n *\/\n\nOUTPUT_ARCH(mips)\nGROUP(-lgcc -lc)\n\nENTRY(_start)\nSECTIONS\n{\n    . = 0x80200000 ;\n\n    .start :\n    {\n        *(.start);\n    }\n\n    . = ALIGN(4);\n    .text : \n    {\n         *(.text)\n         *(.text.*)\n         *(.rodata)\n         *(.rodata.*)\n         *(.rodata1)\n         *(.rodata1.*)\n         \n         \/* section information for finsh shell *\/\n         . = ALIGN(4);\n         __fsymtab_start = .;\n         KEEP(*(FSymTab))\n         __fsymtab_end = .;\n         . = ALIGN(4);\n         __vsymtab_start = .;\n         KEEP(*(VSymTab))\n         __vsymtab_end = .;\n         . = ALIGN(4);\n\n         . = ALIGN(4);\n         __rt_init_start = .;\n         KEEP(*(SORT(.rti_fn*)))\n             __rt_init_end = .;\n         . = ALIGN(4);\n    }\n\n    . = ALIGN(4);\n    .data : \n    {\n         *(.data)\n         *(.data.*)\n        \n         *(.data1)\n         *(.data1.*)\n         \n         . = ALIGN(8);\n         _gp = ABSOLUTE(.);     \/* Base of small data *\/\n         \n         *(.sdata)\n         *(.sdata.*)\n    }\n\n    .sbss : \n    {\n        __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.dynsbss)\n        *(.scommon)\n    }\n\n    .bss :\n    {\n        *(.bss)\n        *(.bss.*)\n        *(.dynbss)\n        *(COMMON)\n        __bss_end = .;\n    }\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/*\n * File      : ls1b_ram.lds\n * This file is part of RT-Thread RTOS\n * COPYRIGHT (C) 2011, RT-Thread Development Team\n *\n * The license and distribution terms for this file may be\n * found in the file LICENSE in this distribution or at\n * http:\/\/www.rt-thread.org\/license\/LICENSE\n *\n * Change Logs:\n * Date           Author       Notes\n * 2010-05-17     swkyer       first version\n * 2010-09-04     bernard      move the beginning entry to 0x80200000\n *\/\n\nOUTPUT_ARCH(mips)\nGROUP(-lgcc -lc)\n\nENTRY(_start)\nSECTIONS\n{\n    . = 0x80200000 ;\n\n    .start :\n    {\n        *(.start);\n    }\n\n    . = ALIGN(4);\n    .text : \n    {\n         *(.text)\n         *(.text.*)\n         *(.rodata)\n         *(.rodata.*)\n         *(.rodata1)\n         *(.rodata1.*)\n         \n         \/* section information for finsh shell *\/\n         . = ALIGN(4);\n         __fsymtab_start = .;\n         KEEP(*(FSymTab))\n         __fsymtab_end = .;\n         . = ALIGN(4);\n         __vsymtab_start = .;\n         KEEP(*(VSymTab))\n         __vsymtab_end = .;\n         . = ALIGN(4);\n    }\n\n    . = ALIGN(4);\n    .data : \n    {\n         *(.data)\n         *(.data.*)\n        \n         *(.data1)\n         *(.data1.*)\n         \n         . = ALIGN(8);\n         _gp = ABSOLUTE(.);     \/* Base of small data *\/\n         \n         *(.sdata)\n         *(.sdata.*)\n    }\n\n    .sbss : \n    {\n        __bss_start = .;\n        *(.sbss)\n        *(.sbss.*)\n        *(.dynsbss)\n        *(.scommon)\n    }\n\n    .bss :\n    {\n        *(.bss)\n        *(.bss.*)\n        *(.dynbss)\n        *(COMMON)\n        __bss_end = .;\n    }\n    _end = .;\n\n    \/* Stabs debugging sections.  *\/\n    .stab          0 : { *(.stab) }\n    .stabstr       0 : { *(.stabstr) }\n    .stab.excl     0 : { *(.stab.excl) }\n    .stab.exclstr  0 : { *(.stab.exclstr) }\n    .stab.index    0 : { *(.stab.index) }\n    .stab.indexstr 0 : { *(.stab.indexstr) }\n    .comment       0 : { *(.comment) }\n    \/* DWARF debug sections.\n     * Symbols in the DWARF debugging sections are relative to the beginning\n     * of the section so we begin them at 0.  *\/\n    \/* DWARF 1 *\/\n    .debug          0 : { *(.debug) }\n    .line           0 : { *(.line) }\n    \/* GNU DWARF 1 extensions *\/\n    .debug_srcinfo  0 : { *(.debug_srcinfo) }\n    .debug_sfnames  0 : { *(.debug_sfnames) }\n    \/* DWARF 1.1 and DWARF 2 *\/\n    .debug_aranges  0 : { *(.debug_aranges) }\n    .debug_pubnames 0 : { *(.debug_pubnames) }\n    \/* DWARF 2 *\/\n    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n    .debug_abbrev   0 : { *(.debug_abbrev) }\n    .debug_line     0 : { *(.debug_line) }\n    .debug_frame    0 : { *(.debug_frame) }\n    .debug_str      0 : { *(.debug_str) }\n    .debug_loc      0 : { *(.debug_loc) }\n    .debug_macinfo  0 : { *(.debug_macinfo) }\n    \/* SGI\/MIPS DWARF 2 extensions *\/\n    .debug_weaknames 0 : { *(.debug_weaknames) }\n    .debug_funcnames 0 : { *(.debug_funcnames) }\n    .debug_typenames 0 : { *(.debug_typenames) }\n    .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"357b64fd2c4d1fb8e02da9fc551b2c70d87b5e33","subject":"bugfix: add .rodata section for riscv ulp for esp32s2","message":"bugfix: add .rodata section for riscv ulp for esp32s2\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/ulp\/ld\/esp32s2.ulp.riscv.ld","new_file":"components\/ulp\/ld\/esp32s2.ulp.riscv.ld","new_contents":"#include \"sdkconfig.h\"\n\nENTRY(reset_vector)\n\nMEMORY\n{\n    ram(RW) : ORIGIN = 0, LENGTH = CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM\n}\n\nSECTIONS\n{\n    . = ORIGIN(ram);\n    .text :\n    {\n        *(.text)\n        *(.text*)\n    } >ram\n\n    .rodata ALIGN(4):\n    {\n        *(.rodata)\n        *(.rodata*)\n    } > ram\n\n    .data ALIGN(4):\n    {\n        *(.data)\n        *(.data*)\n        *(.sdata)\n        *(.sdata*)\n    } > ram\n\n    .bss ALIGN(4) :\n    {\n        *(.bss)\n        *(.bss*)\n        *(.sbss)\n        *(.sbss*)\n    } >ram\n\n    __stack_top = ORIGIN(ram) + LENGTH(ram);\n}\n","old_contents":"#include \"sdkconfig.h\"\n\nENTRY(reset_vector)\n\nMEMORY\n{\n    ram(RW) : ORIGIN = 0, LENGTH = CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM\n}\n\nSECTIONS\n{\n    . = ORIGIN(ram);\n    .text :\n    {\n        *(.text)\n        *(.text*)\n    } >ram\n\n    .data ALIGN(4):\n    {\n        *(.data)\n        *(.data*)\n        *(.sdata)\n        *(.sdata*)\n    } > ram\n\n    .bss ALIGN(4) :\n    {\n        *(.bss)\n        *(.bss*)\n        *(.sbss)\n        *(.sbss*)\n    } >ram\n\n    __stack_top = ORIGIN(ram) + LENGTH(ram);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"fd5f09d3a2e75625f6075575c835edce8ce81908","subject":"Add comment to affect that changing values in this file means that parameters in the CBUS parameters block also needs changing.","message":"Add comment to affect that changing values in this file means that parameters in the CBUS parameters block also needs changing.\n","repos":"the-nw1-group\/acb-modules","old_file":"acb-common\/ldscripts\/m0\/f32r6-acb-module-mem.ld","new_file":"acb-common\/ldscripts\/m0\/f32r6-acb-module-mem.ld","new_contents":"\/*\n * Memory Spaces Definitions.\n *\n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\n * The values below can be addressed in further linker scripts\n * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\n *\/\n\n\/*\n * Location of CBUS module parameter block. This needs to be within the main application code, and after the\n * vector table. non-M0 devices vector tables contain upto 128 entries (512 bytes), plus an additional 16 entries (64\n * bytes) for the exception and core peripherial devices,  and usually have 4K pages (unlike the low density M0 devices\n * that have 1K pages). So the location of the CBUS parameter block needs to be at least 4628 bytes from the nominal\n * application origin (0x08000000). The parameter block is therefore placed at location 0x1214 (4628) after the\n * application origin, so that it's in a common location across all cortex devices. \n *\n * If CBUS_MOD_VARS changes then modify MODULE_NAME in cbusModuleParameters.S file. If the FLASH_VTOR changes, then \n * modify LOAD_ADDRESS in cbusModuleParameters.S file.\n *\n * This does mean that this creates a gap in the application image on m0 devices (as they only have a 32 entry vector \n * table, or 128 bytes, with the same set of exception handlers as the other cortex devices, making 192 bytes), in\n * addition to the flash image starting at 3K, rather than 4K. This leaves a gap of 1364 bytes. Therefore we allocate\n * a \"vtor\" flash area, where some routines can be placed. These need to be defined in code, to be placed in the\n * after_vectors section, as the linker won't flow sections around the fixed CBUS module parameters block.\n *\n * Note the offset here, is from the _flash_origin as defined above.\n *\/\n\n\nMEMORY\n{\n  RAM (xrw)         : ORIGIN = 0x200000C0, LENGTH = 5952\n  FLASH_VTOR(rx)    : ORIGIN = 0x08000C00, LENGTH = 4628\n  CBUS_MOD_VARS(rx) : ORIGIN = 0x08001214, LENGTH = 40\n  FLASH (rx)        : ORIGIN = 0x0800123C, LENGTH = 28240\n}\n\n_ram_origin   = ORIGIN(RAM);\n_ram_length   = LENGTH(RAM);\n_ram_lastLocation = _ram_origin + _ram_length;\n\n_flash_origin = ORIGIN(FLASH_VTOR);\n_flash_length = LENGTH(FLASH) + LENGTH(CBUS_MOD_VARS) + LENGTH(FLASH);\n","old_contents":"\/*\n * Memory Spaces Definitions.\n *\n * Need modifying for a specific board. \n *   FLASH.ORIGIN: starting address of flash\n *   FLASH.LENGTH: length of flash\n *   RAM.ORIGIN: starting address of RAM bank 0\n *   RAM.LENGTH: length of RAM bank 0\n *\n * The values below can be addressed in further linker scripts\n * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\n *\/\n\n\/*\n * Location of CBUS module parameter block. This needs to be within the main application code, and after the\n * vector table. non-M0 devices vector tables contain upto 128 entries (512 bytes), plus an additional 16 entries (64\n * bytes) for the exception and core peripherial devices,  and usually have 4K pages (unlike the low density M0 devices\n * that have 1K pages). So the location of the CBUS parameter block needs to be at least 4628 bytes from the nominal\n * application origin (0x08000000). The parameter block is therefore placed at location 0x1214 (4628) after the\n * application origin, so that it's in a common location across all cortex devices.\n *\n * This does mean that this creates a gap in the application image on m0 devices (as they only have a 32 entry vector \n * table, or 128 bytes, with the same set of exception handlers as the other cortex devices, making 192 bytes), in\n * addition to the flash image starting at 3K, rather than 4K. This leaves a gap of 1364 bytes. Therefore we allocate\n * a \"vtor\" flash area, where some routines can be placed. These need to be defined in code, to be placed in the\n * after_vectors section, as the linker won't flow sections around the fixed CBUS module parameters block.\n *\n * Note the offset here, is from the _flash_origin as defined above.\n *\/\n\n\nMEMORY\n{\n  RAM (xrw)         : ORIGIN = 0x200000C0, LENGTH = 5952\n  FLASH_VTOR(rx)    : ORIGIN = 0x08000C00, LENGTH = 4628\n  CBUS_MOD_VARS(rx) : ORIGIN = 0x08001214, LENGTH = 40\n  FLASH (rx)        : ORIGIN = 0x0800123C, LENGTH = 28240\n}\n\n_ram_origin   = ORIGIN(RAM);\n_ram_length   = LENGTH(RAM);\n_ram_lastLocation = _ram_origin + _ram_length;\n\n_flash_origin = ORIGIN(FLASH_VTOR);\n_flash_length = LENGTH(FLASH) + LENGTH(CBUS_MOD_VARS) + LENGTH(FLASH);\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"4c31c228026cc76aa81792d8d2f2e982846ca812","subject":"[CME_M7] update gcc linker script.","message":"[CME_M7] update gcc linker script.\n","repos":"weety\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,yongli3\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,yongli3\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,zhaojuntao\/rt-thread,zhaojuntao\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,wolfgangz2013\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,AubrCool\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,weiyuliang\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,yongli3\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,igou\/rt-thread,igou\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,yongli3\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,zhaojuntao\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,yongli3\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread","old_file":"bsp\/CME_M7\/CME_M7.ld","new_file":"bsp\/CME_M7\/CME_M7.ld","new_contents":"\/******************************************************************************\n *\n * CME_M7.ld - Linker configuration file for project.\n *\n * Change Logs:\n * Date           Author       Notes\n * 2014-11-02     aozima       first implementation\n *\n *****************************************************************************\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K \/* !!! real 128K, up to 256K for linker. *\/\n    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.isr_vector))\n        *(.text*)\n        *(.rodata*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for components init. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n    } > FLASH\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > FLASH\n    __exidx_end = .;\n\n\t\/* end of all text. *\/\n    _etext = .;\n\t\n    .data : AT(_etext)\n    {\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n    __bss_end = .;\n\n}\n","old_contents":"\/******************************************************************************\n *\n * nuc472_flash.ld - Linker configuration file for project.\n *\n * Change Logs:\n * Date           Author       Notes\n * 2014-08-24     aozima       first implementation\n *\n *****************************************************************************\/\n\n\/* Program Entry, set to mark it as \"used\" and avoid gc *\/\nMEMORY\n{\n    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\n}\n\nSECTIONS\n{\n    .text :\n    {\n        _text = .;\n        KEEP(*(.isr_vector))\n        *(.text*)\n        *(.rodata*)\n\n        \/* section information for finsh shell *\/\n        . = ALIGN(4);\n        __fsymtab_start = .;\n        KEEP(*(FSymTab))\n        __fsymtab_end = .;\n        . = ALIGN(4);\n        __vsymtab_start = .;\n        KEEP(*(VSymTab))\n        __vsymtab_end = .;\n        . = ALIGN(4);\n\n        \/* section information for components init. *\/\n        . = ALIGN(4);\n        __rt_init_start = .;\n        KEEP(*(SORT(.rti_fn*)))\n        __rt_init_end = .;\n        . = ALIGN(4);\n\n    } > FLASH\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\n        \/* This is used by the startup in order to initialize the .data secion *\/\n        _sidata = .;\n    } > FLASH\n    __exidx_end = .;\n\n\t\/* end of all text. *\/\n    _etext = .;\n\t\n    .data : AT(_etext)\n    {\n        _data = .;\n        *(vtable)\n        *(.data*)\n        _edata = .;\n    } > SRAM\n\n    .bss :\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n    __bss_end = .;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a9b47fc32c0ec67dcdc85abc860406f666f66d74","subject":"arm: cortex_m: linker.ld: fix relocate by moving _vector_start","message":"arm: cortex_m: linker.ld: fix relocate by moving _vector_start\n\nThe _vector_start was placed before the CONFIG_TEXT_SECTION_OFFSET, thus\nadding the offset in the relocated vector table, making the table\ninvalid when relocated with a non null CONFIG_TEXT_SECTION_OFFSET.\n\nThis was tested using MCUboot with a 0x200 offset for the image header.\n\nFixes: eb48a0a73c11 (\"arm: armv6-m: Support relocating vector table\")\nSigned-off-by: Neil Armstrong <619b324efbf5f7848de055bdc8bef4c0dd7c8ef5@baylibre.com>\n","repos":"zephyrproject-rtos\/zephyr,mbolivar\/zephyr,nashif\/zephyr,punitvara\/zephyr,nashif\/zephyr,mbolivar\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,mbolivar\/zephyr,ldts\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,galak\/zephyr,mbolivar\/zephyr,kraj\/zephyr,galak\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyriot\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,galak\/zephyr,Vudentz\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,zephyriot\/zephyr,ldts\/zephyr,nashif\/zephyr,kraj\/zephyr,zephyriot\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,ldts\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,explora26\/zephyr,ldts\/zephyr,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyriot\/zephyr,explora26\/zephyr,punitvara\/zephyr,finikorg\/zephyr,nashif\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,kraj\/zephyr,punitvara\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M3 platform.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nSECTIONS\n    {\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t_vector_start = .;\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n#ifndef CONFIG_APPLICATION_MEMORY\n\t_image_ram_start = .;\n#endif\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ae34d9d4c23ad75ad49c984c94bdca1001250dc4","subject":"Revert \"arch: arm: linker.ld: Fixed incorrect placement of noinit section\"","message":"Revert \"arch: arm: linker.ld: Fixed incorrect placement of noinit section\"\n\nThis reverts commit 4f78d86eb749d6458f9745ea9c5ea74a3362e4aa.\n\nSigned-off-by: Anas Nashif <0d9952ec84ac43c159f6b7e7ed99a9080c00dd6e@intel.com>\n","repos":"punitvara\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,ldts\/zephyr,nashif\/zephyr,Vudentz\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,ldts\/zephyr,punitvara\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,explora26\/zephyr,ldts\/zephyr,punitvara\/zephyr,galak\/zephyr,explora26\/zephyr,Vudentz\/zephyr,galak\/zephyr,explora26\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,galak\/zephyr,explora26\/zephyr,finikorg\/zephyr,punitvara\/zephyr,galak\/zephyr,punitvara\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN . = ALIGN(4);\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t_app_smem_end = .;\n\t\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n#include <linker\/priv_stacks-noinit.ld>\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef CONFIG_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = CONFIG_CCM_BASE_ADDRESS, LENGTH = CONFIG_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t_vector_end = .;\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    SECTION_PROLOGUE(.got,,)\n\t{\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#include <app_data_alignment.ld>\n\n#if defined(CONFIG_APP_SHARED_MEM)\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define APP_SHARED_ALIGN . = ALIGN(4);\n\t\t#include <app_smem.ld>\n#else\n\tSECTION_PROLOGUE(_APP_SMEM_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\t. = ALIGN(4);\n\t\t_image_ram_start = .;\n\t\t_app_smem_start = .;\n\t\tAPP_SMEM_SECTION()\n\t\t_app_smem_end = .;\n\t\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_APP_SHARED_MEM *\/\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\tKERNEL_INPUT_SECTION(.bss)\n\tKERNEL_INPUT_SECTION(\".bss.*\")\n\tKERNEL_INPUT_SECTION(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        KERNEL_INPUT_SECTION(.noinit)\n        KERNEL_INPUT_SECTION(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#include <linker\/priv_stacks-noinit.ld>\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\tKERNEL_INPUT_SECTION(.data)\n\tKERNEL_INPUT_SECTION(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* CONFIG_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ed88d38a702b946c0a6932aae7400dbe9f6313a0","subject":"Replaced inaccurate comment and removed cruft","message":"Replaced inaccurate comment and removed cruft\n","repos":"SimonGustavsson\/nox,SimonGustavsson\/nox","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"ENTRY(_start)\n\nSECTIONS\n{\n    \/* This is where kloader will put us at boot *\/\n\t. = 0x10000;\n\n    LD_KERNEL_START = .;\n\n    \/* Kernel code *\/\n\t.text :\n\t{\n        *(.text.boot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata ALIGN(4):\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data ALIGN(4):\n\t{\n\t\t*(.data)\n\t}\n\n    LD_KERNEL_DATA_END = .;\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss ALIGN(4):\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t}\n\n    LD_KERNEL_END = .;\n}\n","old_contents":"\/* The bootloader will look at this image and start execution at the symbol\n   designated as the entry point. *\/\nENTRY(_start)\n\n\/* Tell where the various sections of the object files will be put in the final\n   kernel image. *\/\nSECTIONS\n{\n\t\/* Begin putting sections at 1 MiB, a conventional place for kernels to be\n\t   loaded at by the bootloader. *\/\n\t. = 0x10000;\n\n    LD_KERNEL_START = .;\n\n    \/* Kernel code *\/\n\t.text :\n\t{\n        *(.text.boot)\n\t\t*(.text)\n\t}\n\n\t\/* Read-only data. *\/\n\t.rodata ALIGN(4):\n\t{\n\t\t*(.rodata)\n\t}\n\n\t\/* Read-write data (initialized) *\/\n\t.data ALIGN(4):\n\t{\n\t\t*(.data)\n\t}\n\n    LD_KERNEL_DATA_END = .;\n\n\t\/* Read-write data (uninitialized) and stack *\/\n\t.bss ALIGN(4):\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t\t*(.bootstrap_stack)\n\t}\n\n    LD_KERNEL_END = .;\n\n\n\t\/* The compiler may produce other sections, by default it will put them in\n\t   a segment with the same name. Simply add stuff here as needed. *\/\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8c5b43ff28b161deabbc47c8c99d20f50f0c3a75","subject":"Fix issue due to LD 20815","message":"Fix issue due to LD 20815\n\nhttps:\/\/sourceware.org\/bugzilla\/show_bug.cgi?id=20815\n","repos":"Sebazzz\/sdos","old_file":"os\/os.lds","new_file":"os\/os.lds","new_contents":"ENTRY(kinit);\nOUTPUT_FORMAT(elf32-i386);\n\nPHDRS { \n\theaders PT_PHDR PHDRS; \n\tcode PT_LOAD FILEHDR PHDRS;\n}\n\nSECTIONS {\n\t.text 0x600: ALIGN(0x100) { *(.text) } :code\n\t.rdata : { *(rdata) }\n\t.data : { *(data) }\n\t.bss : { *(bss) }\n\t\/DISCARD\/ : { *(.eh_frame) }\n}","old_contents":"ENTRY(kinit);\nOUTPUT_FORMAT(elf32-i386);\n\nPHDRS { \n\theaders PT_PHDR FILEHDR PHDRS; \n\tcode PT_LOAD;\n}\n\nSECTIONS {\n\t.text 0x600: ALIGN(0x100) { *(.text) } :code\n\t.rdata : { *(rdata) }\n\t.data : { *(data) }\n\t.bss : { *(bss) }\n\t\/DISCARD\/ : { *(.eh_frame) }\n}","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"4a1e0f0f41701d10839587565fe03de0e4bde2c5","subject":"\u30b9\u30bf\u30c3\u30af\u306e\u8a2d\u5b9a\u30a2\u30c9\u30ec\u30b9\u306e\u4e0d\u5177\u5408\u4fee\u6b63 \u53ef\u5909\u30d9\u30af\u30bf\u30fc\u306e\u5c02\u7528\u30bb\u30af\u30b7\u30e7\u30f3\u8a2d\u5b9a","message":"\u30b9\u30bf\u30c3\u30af\u306e\u8a2d\u5b9a\u30a2\u30c9\u30ec\u30b9\u306e\u4e0d\u5177\u5408\u4fee\u6b63\n\u53ef\u5909\u30d9\u30af\u30bf\u30fc\u306e\u5c02\u7528\u30bb\u30af\u30b7\u30e7\u30f3\u8a2d\u5b9a\n","repos":"hirakuni45\/R8C,hirakuni45\/R8C,hirakuni45\/R8C","old_file":"M120AN\/m120an.ld","new_file":"M120AN\/m120an.ld","new_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x0300, LENGTH = 0x0480\n\tROM (r)  : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVVEC (r) : ORIGIN = 0xFED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0760-1;\n\t\t_isp_init = 0x0780-1;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w) : ORIGIN = 0x0300, LENGTH = 0x0480\n\tROM (r) : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x07E0-1;\n\t\t_isp_init = 0x0800-1;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vec : {\n    *(.vec)\n  } > VEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"e9901d15a1c3f20608246ae0ab3794e0c898fdb1","subject":"rtc: fix memory map","message":"rtc: fix memory map\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp32s2beta\/ld\/esp32s2beta.ld","new_file":"components\/esp32s2beta\/ld\/esp32s2beta.ld","new_contents":"\/* ESP32 Linker Script Memory Layout\n\n   This file describes the memory layout (memory blocks) as virtual\n   memory addresses.\n\n   esp32.common.ld contains output sections to link compiler output\n   into these memory blocks.\n\n   ***\n\n   This linker script is passed through the C preprocessor to include\n   configuration options.\n\n   Please use preprocessor features sparingly! Restrict\n   to simple macros with numeric values, and\/or #if\/#endif blocks.\n*\/\n#include \"sdkconfig.h\"\n\n\/* If BT is not built at all *\/\n#ifndef CONFIG_BT_RESERVE_DRAM\n#define CONFIG_BT_RESERVE_DRAM 0\n#endif\n\nMEMORY\n{\n  \/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n  are connected to the data port of the CPU and eg allow bytewise access. *\/\n\n  \/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... *\/\n  iram0_0_seg (RX) :                 org = 0x40028000, len = 0x18000\n\n  \/* Even though the segment name is iram, it is actually mapped to flash\n  *\/\n  iram0_2_seg (RX) :                 org = 0x40080018, len = 0xb80000-0x18\n\n  \/*\n    (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file\n    which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash\n    cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)\n  *\/\n\n\n  \/* Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n\n     Enabling Bluetooth & Trace Memory features in menuconfig will decrease\n     the amount of RAM available.\n\n     Note: Length of this section *should* be 0x50000, and this extra DRAM is available\n     in heap at runtime. However due to static ROM memory usage at this 176KB mark, the\n     additional static memory temporarily cannot be used.\n  *\/\n  dram0_0_seg (RW) :                 org = 0x3FFD0000 + CONFIG_BT_RESERVE_DRAM,\n                                     len = 0x28000 - CONFIG_BT_RESERVE_DRAM\n\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3F000018, len = 0x3f0000-0x18\n\n  \/* (See iram0_2_seg for meaning of 0x18 offset in the above.) *\/\n\n  \/* RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x40070000, len = 0x2000\n\n  \/* RTC slow memory (data accessible). Persists over deep sleep.\n\n     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n  *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM\n\n  \/* RTC fast memory (same block as above), viewed from data bus *\/\n  rtc_data_seg(RW) :                 org = 0x3ff9e000, len = 0x2000\n}\n\n_static_data_end = _bss_end;\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000 - CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM;\n\n_data_seg_org = ORIGIN(rtc_data_seg);\n\n\/* The lines below define location alias for .rtc.data section based on Kconfig option.\n   When the option is not defined then use slow memory segment\n   else the data will be placed in fast memory segment\n   TODO: check whether the rtc_data_location is correct for esp32s2beta - IDF-761 *\/\n#ifndef CONFIG_ESP32_RTCDATA_IN_FAST_MEM\nREGION_ALIAS(\"rtc_data_location\", rtc_slow_seg );\n#else\nREGION_ALIAS(\"rtc_data_location\", rtc_data_seg );\n#endif\n","old_contents":"\/* ESP32 Linker Script Memory Layout\n\n   This file describes the memory layout (memory blocks) as virtual\n   memory addresses.\n\n   esp32.common.ld contains output sections to link compiler output\n   into these memory blocks.\n\n   ***\n\n   This linker script is passed through the C preprocessor to include\n   configuration options.\n\n   Please use preprocessor features sparingly! Restrict\n   to simple macros with numeric values, and\/or #if\/#endif blocks.\n*\/\n#include \"sdkconfig.h\"\n\n\/* If BT is not built at all *\/\n#ifndef CONFIG_BT_RESERVE_DRAM\n#define CONFIG_BT_RESERVE_DRAM 0\n#endif\n\nMEMORY\n{\n  \/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length\n  of the various regions. The 'data access port' dram\/drom regions map to the same iram\/irom regions but\n  are connected to the data port of the CPU and eg allow bytewise access. *\/\n\n  \/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... *\/\n  iram0_0_seg (RX) :                 org = 0x40028000, len = 0x18000\n\n  \/* Even though the segment name is iram, it is actually mapped to flash\n  *\/\n  iram0_2_seg (RX) :                 org = 0x40080018, len = 0xb80000-0x18\n\n  \/*\n    (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file\n    which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash\n    cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)\n  *\/\n\n\n  \/* Shared data RAM, excluding memory reserved for ROM bss\/data\/stack.\n\n     Enabling Bluetooth & Trace Memory features in menuconfig will decrease\n     the amount of RAM available.\n\n     Note: Length of this section *should* be 0x50000, and this extra DRAM is available\n     in heap at runtime. However due to static ROM memory usage at this 176KB mark, the\n     additional static memory temporarily cannot be used.\n  *\/\n  dram0_0_seg (RW) :                 org = 0x3FFD0000 + CONFIG_BT_RESERVE_DRAM,\n                                     len = 0x28000 - CONFIG_BT_RESERVE_DRAM\n\n  \/* Flash mapped constant data *\/\n  drom0_0_seg (R) :                  org = 0x3F000018, len = 0x3f0000-0x18\n\n  \/* (See iram0_2_seg for meaning of 0x18 offset in the above.) *\/\n\n  \/* RTC fast memory (executable). Persists over deep sleep.\n   *\/\n  rtc_iram_seg(RWX) :                org = 0x40070000, len = 0x2000\n\n  \/* RTC slow memory (data accessible). Persists over deep sleep.\n\n     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.\n  *\/\n  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,\n                                     len = 0x1000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM\n\n  \/* RTC fast memory (same block as above), viewed from data bus\n   * TODO: check whether rtc_data_seg address is correct - IDF-760 *\/\n  rtc_data_seg(RW) :                 org = 0x3ff9e000, len = 0\n}\n\n_static_data_end = _bss_end;\n\n\/* Heap ends at top of dram0_0_seg *\/\n_heap_end = 0x40000000 - CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM;\n\n_data_seg_org = ORIGIN(rtc_data_seg);\n\n\/* The lines below define location alias for .rtc.data section based on Kconfig option.\n   When the option is not defined then use slow memory segment\n   else the data will be placed in fast memory segment\n   TODO: check whether the rtc_data_location is correct for esp32s2beta - IDF-761 *\/\n#ifndef CONFIG_ESP32_RTCDATA_IN_FAST_MEM\nREGION_ALIAS(\"rtc_data_location\", rtc_slow_seg );\n#else\nREGION_ALIAS(\"rtc_data_location\", rtc_data_seg );\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9782f86f82aa8b4af898a887619bb70a82a35f38","subject":"update rom file for c2 controller lib","message":"update rom file for c2 controller lib\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.ld","new_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.ld","new_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\nrtc_get_wakeup_cause = 0x40000020;\nrtc_select_apb_bridge = 0x40000024;\nrtc_unhold_all_pads = 0x40000028;\nets_is_print_boot = 0x4000002c;\nets_vprintf = 0x40000030;\nets_printf = 0x40000034;\nets_install_putc1 = 0x40000038;\nets_install_uart_printf = 0x4000003c;\nets_install_putc2 = 0x40000040;\nets_delay_us = 0x40000044;\nets_get_stack_info = 0x40000048;\nets_install_lock = 0x4000004c;\nUartRxString = 0x40000050;\nUartGetCmdLn = 0x40000054;\nuart_tx_one_char = 0x40000058;\nuart_tx_one_char2 = 0x4000005c;\nuart_rx_one_char = 0x40000060;\nuart_rx_one_char_block = 0x40000064;\nuart_rx_readbuff = 0x40000068;\nuartAttach = 0x4000006c;\nuart_tx_flush = 0x40000070;\nuart_tx_wait_idle = 0x40000074;\nuart_div_modify = 0x40000078;\nets_write_char_uart = 0x4000007c;\nuart_tx_switch = 0x40000080;\nmultofup = 0x40000084;\nsoftware_reset = 0x40000088;\nsoftware_reset_cpu = 0x4000008c;\nassist_debug_clock_enable = 0x40000090;\nassist_debug_record_enable = 0x40000094;\nclear_super_wdt_reset_flag = 0x40000098;\ndisable_default_watchdog = 0x4000009c;\nsend_packet = 0x400000a0;\nrecv_packet = 0x400000a4;\nGetUartDevice = 0x400000a8;\nUartDwnLdProc = 0x400000ac;\nGetSecurityInfoProc = 0x400000b0;\nUart_Init = 0x400000b4;\nets_set_user_start = 0x400000b8;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff4fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000bc;\nmz_free = 0x400000c0;\ntdefl_compress = 0x400000c4;\ntdefl_compress_buffer = 0x400000c8;\ntdefl_compress_mem_to_heap = 0x400000cc;\ntdefl_compress_mem_to_mem = 0x400000d0;\ntdefl_compress_mem_to_output = 0x400000d4;\ntdefl_get_adler32 = 0x400000d8;\ntdefl_get_prev_return_status = 0x400000dc;\ntdefl_init = 0x400000e0;\ntdefl_write_image_to_png_file_in_memory = 0x400000e4;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000e8;\ntinfl_decompress = 0x400000ec;\ntinfl_decompress_mem_to_callback = 0x400000f0;\ntinfl_decompress_mem_to_heap = 0x400000f4;\ntinfl_decompress_mem_to_mem = 0x400000f8;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 );\nPROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 );\nPROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 );\nPROVIDE( _esp_rom_spiflash_write = 0x4000011c );\nPROVIDE( _esp_rom_spiflash_read = 0x40000120 );\nPROVIDE( _esp_rom_spiflash_unlock = 0x40000124 );\nPROVIDE( _SPIEraseArea = 0x40000128 );\nPROVIDE( _SPI_write_enable = 0x4000012c );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000134 );\nPROVIDE( esp_rom_spiflash_write = 0x40000138 );\nPROVIDE( esp_rom_spiflash_read = 0x4000013c );\nPROVIDE( esp_rom_spiflash_unlock = 0x40000140 );\nPROVIDE( SPIEraseArea = 0x40000144 );\nPROVIDE( SPI_write_enable = 0x40000148 );\nPROVIDE( esp_rom_spiflash_config_param = 0x4000014c );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c );\nPROVIDE( esp_rom_spi_flash_update_id = 0x40000160 );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000164 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 );\nPROVIDE( esp_rom_spiflash_read_status = 0x4000016c );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000174 );\nPROVIDE( spi_flash_attach = 0x40000178 );\nPROVIDE( spi_flash_get_chip_size = 0x4000017c );\nPROVIDE( spi_flash_guard_set = 0x40000180 );\nPROVIDE( spi_flash_guard_get = 0x40000184 );\nPROVIDE( spi_flash_read_encrypted = 0x40000188 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x4000018c );\nPROVIDE( spi_flash_mmap_page_num_init = 0x40000190 );\nPROVIDE( spi_flash_mmap = 0x40000194 );\nPROVIDE( spi_flash_mmap_pages = 0x40000198 );\nPROVIDE( spi_flash_munmap = 0x4000019c );\nPROVIDE( spi_flash_mmap_dump = 0x400001a0 );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );\nPROVIDE( spi_flash_cache2phys = 0x400001ac );\nPROVIDE( spi_flash_phys2cache = 0x400001b0 );\nPROVIDE( spi_flash_disable_cache = 0x400001b4 );\nPROVIDE( spi_flash_restore_cache = 0x400001b8 );\nPROVIDE( spi_flash_cache_enabled = 0x400001bc );\nPROVIDE( spi_flash_enable_cache = 0x400001c0 );\nPROVIDE( spi_cache_mode_switch = 0x400001c4 );\nPROVIDE( spi_common_set_dummy_output = 0x400001c8 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001cc );\nPROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 );\nPROVIDE( SPILock = 0x400001d8 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001dc );\nPROVIDE( SPI_Common_Command = 0x400001e0 );\nPROVIDE( SPI_WakeUp = 0x400001e4 );\nPROVIDE( SPI_block_erase = 0x400001e8 );\nPROVIDE( SPI_chip_erase = 0x400001ec );\nPROVIDE( SPI_init = 0x400001f0 );\nPROVIDE( SPI_page_program = 0x400001f4 );\nPROVIDE( SPI_read_data = 0x400001f8 );\nPROVIDE( SPI_sector_erase = 0x400001fc );\nPROVIDE( SelectSpiFunction = 0x40000200 );\nPROVIDE( SetSpiDrvs = 0x40000204 );\nPROVIDE( Wait_SPI_Idle = 0x40000208 );\nPROVIDE( spi_dummy_len_fix = 0x4000020c );\nPROVIDE( Disable_QMode = 0x40000210 );\nPROVIDE( Enable_QMode = 0x40000214 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group hal_soc\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 );\nPROVIDE( spi_flash_hal_device_config = 0x4000021c );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 );\nPROVIDE( spi_flash_hal_common_command = 0x40000224 );\nPROVIDE( spi_flash_hal_read = 0x40000228 );\nPROVIDE( spi_flash_hal_erase_chip = 0x4000022c );\nPROVIDE( spi_flash_hal_erase_sector = 0x40000230 );\nPROVIDE( spi_flash_hal_erase_block = 0x40000234 );\nPROVIDE( spi_flash_hal_program_page = 0x40000238 );\nPROVIDE( spi_flash_hal_set_write_protect = 0x4000023c );\nPROVIDE( spi_flash_hal_host_idle = 0x40000240 );\nPROVIDE( spi_flash_hal_check_status = 0x40000244 );\nPROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 );\nPROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c );\nPROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 );\nPROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 );\nPROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 );\nPROVIDE( spi_flash_hal_resume = 0x4000025c );\nPROVIDE( spi_flash_hal_suspend = 0x40000260 );\nPROVIDE( spi_flash_encryption_hal_enable = 0x40000264 );\nPROVIDE( spi_flash_encryption_hal_disable = 0x40000268 );\nPROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c );\nPROVIDE( spi_flash_encryption_hal_done = 0x40000270 );\nPROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 );\nPROVIDE( spi_flash_encryption_hal_check = 0x40000278 );\nPROVIDE( wdt_hal_init = 0x4000027c );\nPROVIDE( wdt_hal_deinit = 0x40000280 );\nPROVIDE( wdt_hal_config_stage = 0x40000284 );\nPROVIDE( wdt_hal_write_protect_disable = 0x40000288 );\nPROVIDE( wdt_hal_write_protect_enable = 0x4000028c );\nPROVIDE( wdt_hal_enable = 0x40000290 );\nPROVIDE( wdt_hal_disable = 0x40000294 );\nPROVIDE( wdt_hal_handle_intr = 0x40000298 );\nPROVIDE( wdt_hal_feed = 0x4000029c );\nPROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 );\nPROVIDE( wdt_hal_is_enabled = 0x400002a4 );\nPROVIDE( systimer_hal_init = 0x400002a8 );\nPROVIDE( systimer_hal_get_counter_value = 0x400002ac );\nPROVIDE( systimer_hal_get_time = 0x400002b0 );\nPROVIDE( systimer_hal_set_alarm_target = 0x400002b4 );\nPROVIDE( systimer_hal_set_alarm_period = 0x400002b8 );\nPROVIDE( systimer_hal_get_alarm_value = 0x400002bc );\nPROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 );\nPROVIDE( systimer_hal_on_apb_freq_update = 0x400002c4 );\nPROVIDE( systimer_hal_counter_value_advance = 0x400002c8 );\nPROVIDE( systimer_hal_enable_counter = 0x400002cc );\nPROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 );\nPROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 );\nPROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 );\n\n\n\/***************************************\n Group heap\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( tlsf_create = 0x400002dc );\nPROVIDE( tlsf_create_with_pool = 0x400002e0 );\nPROVIDE( tlsf_get_pool = 0x400002e4 );\nPROVIDE( tlsf_add_pool = 0x400002e8 );\nPROVIDE( tlsf_remove_pool = 0x400002ec );\nPROVIDE( tlsf_malloc = 0x400002f0 );\nPROVIDE( tlsf_memalign = 0x400002f4 );\nPROVIDE( tlsf_memalign_offs = 0x400002f8 );\nPROVIDE( tlsf_realloc = 0x400002fc );\nPROVIDE( tlsf_free = 0x40000300 );\nPROVIDE( tlsf_block_size = 0x40000304 );\nPROVIDE( tlsf_size = 0x40000308 );\nPROVIDE( tlsf_align_size = 0x4000030c );\nPROVIDE( tlsf_block_size_min = 0x40000310 );\nPROVIDE( tlsf_block_size_max = 0x40000314 );\nPROVIDE( tlsf_pool_overhead = 0x40000318 );\nPROVIDE( tlsf_alloc_overhead = 0x4000031c );\nPROVIDE( tlsf_walk_pool = 0x40000320 );\nPROVIDE( tlsf_check = 0x40000324 );\nPROVIDE( tlsf_check_pool = 0x40000328 );\nPROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c );\nPROVIDE( multi_heap_get_block_address_impl = 0x40000330 );\nPROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 );\nPROVIDE( multi_heap_register_impl = 0x40000338 );\nPROVIDE( multi_heap_set_lock = 0x4000033c );\nPROVIDE( multi_heap_os_funcs_init = 0x40000340 );\nPROVIDE( multi_heap_internal_lock = 0x40000344 );\nPROVIDE( multi_heap_internal_unlock = 0x40000348 );\nPROVIDE( multi_heap_get_first_block = 0x4000034c );\nPROVIDE( multi_heap_get_next_block = 0x40000350 );\nPROVIDE( multi_heap_is_free = 0x40000354 );\nPROVIDE( multi_heap_malloc_impl = 0x40000358 );\nPROVIDE( multi_heap_free_impl = 0x4000035c );\nPROVIDE( multi_heap_realloc_impl = 0x40000360 );\nPROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 );\nPROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 );\nPROVIDE( multi_heap_check = 0x4000036c );\nPROVIDE( multi_heap_dump = 0x40000370 );\nPROVIDE( multi_heap_free_size_impl = 0x40000374 );\nPROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 );\nPROVIDE( multi_heap_get_info_impl = 0x4000037c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x40000380 );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 );\nPROVIDE( spi_flash_chip_generic_write = 0x40000388 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000398 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 );\nPROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 );\nPROVIDE( spi_flash_chip_generic_yield = 0x400003b8 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 );\nPROVIDE( spi_flash_chip_generic_read = 0x400003c8 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc );\nPROVIDE( spi_flash_common_set_io_mode = 0x400003e0 );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 );\nPROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 );\nPROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec );\nPROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400003f8 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );\nPROVIDE( spi_flash_encryption = 0x3fcdffe4 );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x40000400 );\nPROVIDE( memspi_host_read_status_hs = 0x40000404 );\nPROVIDE( memspi_host_flush_cache = 0x40000408 );\nPROVIDE( memspi_host_erase_chip = 0x4000040c );\nPROVIDE( memspi_host_erase_sector = 0x40000410 );\nPROVIDE( memspi_host_erase_block = 0x40000414 );\nPROVIDE( memspi_host_program_page = 0x40000418 );\nPROVIDE( memspi_host_read = 0x4000041c );\nPROVIDE( memspi_host_set_write_protect = 0x40000420 );\nPROVIDE( memspi_host_set_max_read_len = 0x40000424 );\nPROVIDE( memspi_host_read_data_slicer = 0x40000428 );\nPROVIDE( memspi_host_write_data_slicer = 0x4000042c );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x40000430 );\nPROVIDE( esp_flash_read_id = 0x40000434 );\nPROVIDE( esp_flash_get_size = 0x40000438 );\nPROVIDE( esp_flash_erase_chip = 0x4000043c );\nPROVIDE( esp_flash_erase_region = 0x40000440 );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000444 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000448 );\nPROVIDE( esp_flash_get_protectable_regions = 0x4000044c );\nPROVIDE( esp_flash_get_protected_region = 0x40000450 );\nPROVIDE( esp_flash_set_protected_region = 0x40000454 );\nPROVIDE( esp_flash_read = 0x40000458 );\nPROVIDE( esp_flash_write = 0x4000045c );\nPROVIDE( esp_flash_write_encrypted = 0x40000460 );\nPROVIDE( esp_flash_read_encrypted = 0x40000464 );\nPROVIDE( esp_flash_get_io_mode = 0x40000468 );\nPROVIDE( esp_flash_set_io_mode = 0x4000046c );\nPROVIDE( spi_flash_boot_attach = 0x40000470 );\nPROVIDE( esp_flash_read_chip_id = 0x40000474 );\nPROVIDE( detect_spi_flash_chip = 0x40000478 );\nPROVIDE( esp_rom_spiflash_write_disable = 0x4000047c );\nPROVIDE( esp_flash_suspend_cmd_init = 0x40000480 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe0 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffdc );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 );\nPROVIDE( Cache_Get_Mode = 0x400006e4 );\nPROVIDE( Cache_Address_Through_IBus = 0x400006e8 );\nPROVIDE( Cache_Address_Through_DBus = 0x400006ec );\nPROVIDE( Cache_Set_Default_Mode = 0x400006f0 );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400006f8 );\nPROVIDE( MMU_Set_Page_Mode = 0x400006fc );\nPROVIDE( MMU_Get_Page_Mode = 0x40000700 );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x40000704 );\nPROVIDE( Cache_Op_Addr = 0x40000708 );\nPROVIDE( Cache_Invalidate_Addr = 0x4000070c );\nPROVIDE( Cache_Invalidate_ICache_All = 0x40000710 );\nPROVIDE( Cache_Mask_All = 0x40000714 );\nPROVIDE( Cache_UnMask_Dram0 = 0x40000718 );\nPROVIDE( Cache_Disable_ICache = 0x4000071c );\nPROVIDE( Cache_Enable_ICache = 0x40000720 );\nPROVIDE( Cache_Suspend_ICache = 0x40000724 );\nPROVIDE( Cache_Resume_ICache = 0x40000728 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x4000072c );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x40000730 );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000734 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x40000738 );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x4000073c );\nPROVIDE( Cache_Owner_Init = 0x40000740 );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000744 );\nPROVIDE( Cache_MMU_Init = 0x40000748 );\nPROVIDE( Cache_Ibus_MMU_Set = 0x4000074c );\nPROVIDE( Cache_Dbus_MMU_Set = 0x40000750 );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000754 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x40000758 );\nPROVIDE( Cache_Get_Virtual_Addr = 0x4000075c );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x40000760 );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000764 );\nPROVIDE( Cache_Get_Memory_value = 0x40000768 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd0 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x4000076c;\nets_get_cpu_frequency = 0x40000770;\nets_update_cpu_frequency = 0x40000774;\nets_get_printf_channel = 0x40000778;\nets_get_xtal_div = 0x4000077c;\nets_set_xtal_div = 0x40000780;\nets_get_xtal_freq = 0x40000784;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x40000788;\ngpio_matrix_in = 0x4000078c;\ngpio_matrix_out = 0x40000790;\ngpio_output_disable = 0x40000794;\ngpio_output_enable = 0x40000798;\ngpio_output_set = 0x4000079c;\ngpio_pad_hold = 0x400007a0;\ngpio_pad_input_disable = 0x400007a4;\ngpio_pad_input_enable = 0x400007a8;\ngpio_pad_pulldown = 0x400007ac;\ngpio_pad_pullup = 0x400007b0;\ngpio_pad_select_gpio = 0x400007b4;\ngpio_pad_set_drv = 0x400007b8;\ngpio_pad_unhold = 0x400007bc;\ngpio_pin_wakeup_disable = 0x400007c0;\ngpio_pin_wakeup_enable = 0x400007c4;\ngpio_bypass_matrix_in = 0x400007c8;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400007cc;\nesprv_intc_int_set_threshold = 0x400007d0;\nesprv_intc_int_enable = 0x400007d4;\nesprv_intc_int_disable = 0x400007d8;\nesprv_intc_int_set_type = 0x400007dc;\nPROVIDE( intr_handler_set = 0x400007e0 );\nintr_matrix_set = 0x400007e4;\nets_intr_lock = 0x400007e8;\nets_intr_unlock = 0x400007ec;\nets_isr_attach = 0x400007f0;\nets_isr_mask = 0x400007f4;\nets_isr_unmask = 0x400007f8;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\ncrc32_le = 0x400007fc;\ncrc16_le = 0x40000800;\ncrc8_le = 0x40000804;\ncrc32_be = 0x40000808;\ncrc16_be = 0x4000080c;\ncrc8_be = 0x40000810;\nesp_crc8 = 0x40000814;\nets_sha_enable = 0x40000818;\nets_sha_disable = 0x4000081c;\nets_sha_get_state = 0x40000820;\nets_sha_init = 0x40000824;\nets_sha_process = 0x40000828;\nets_sha_starts = 0x4000082c;\nets_sha_update = 0x40000830;\nets_sha_finish = 0x40000834;\nets_sha_clone = 0x40000838;\n\/* Data (.data, .bss, .rodata) *\/\ncrc32_le_table_ptr = 0x3ff4fff8;\ncrc16_le_table_ptr = 0x3ff4fff4;\ncrc8_le_table_ptr = 0x3ff4fff0;\ncrc32_be_table_ptr = 0x3ff4ffec;\ncrc16_be_table_ptr = 0x3ff4ffe8;\ncrc8_be_table_ptr = 0x3ff4ffe4;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x4000083c;\nets_efuse_program = 0x40000840;\nets_efuse_clear_program_registers = 0x40000844;\nets_efuse_write_key = 0x40000848;\nets_efuse_get_read_register_address = 0x4000084c;\nets_efuse_get_key_purpose = 0x40000850;\nets_efuse_key_block_unused = 0x40000854;\nets_efuse_find_unused_key_block = 0x40000858;\nets_efuse_rs_calculate = 0x4000085c;\nets_efuse_count_unused_key_blocks = 0x40000860;\nets_efuse_secure_boot_enabled = 0x40000864;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000868;\nets_efuse_cache_encryption_enabled = 0x4000086c;\nets_efuse_download_modes_disabled = 0x40000870;\nets_efuse_find_purpose = 0x40000874;\nets_efuse_force_send_resume = 0x40000878;\nets_efuse_get_flash_delay_us = 0x4000087c;\nets_efuse_get_mac = 0x40000880;\nets_efuse_get_uart_print_control = 0x40000884;\nets_efuse_direct_boot_mode_disabled = 0x40000888;\nets_efuse_security_download_modes_enabled = 0x4000088c;\nets_efuse_set_timing = 0x40000890;\nets_efuse_jtag_disabled = 0x40000894;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_ecdsa_verify = 0x40000898;\nets_secure_boot_verify_bootloader_with_keys = 0x4000089c;\nets_secure_boot_verify_signature = 0x400008a0;\nets_secure_boot_read_key_digests = 0x400008a4;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Data (.data, .bss, .rodata) *\/\ng_uart_print = 0x3fcdffc9;\ng_usb_print = 0x3fcdffc8;\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nble_controller_rom_data_init = 0x40000aa8;\nble_osi_coex_funcs_register = 0x40000aac;\nbt_rf_coex_cfg_get_default = 0x40000ab0;\nbt_rf_coex_dft_pti_get_default = 0x40000ab4;\nbt_rf_coex_hooks_p_set = 0x40000ab8;\nr__os_mbuf_copypkthdr = 0x40000abc;\nr__os_msys_find_pool = 0x40000ac0;\nr_ble_controller_get_rom_compile_version = 0x40000ac4;\nr_ble_hci_ram_hs_acl_tx = 0x40000ac8;\nr_ble_hci_ram_hs_cmd_tx = 0x40000acc;\nr_ble_hci_ram_ll_acl_tx = 0x40000ad0;\nr_ble_hci_ram_ll_evt_tx = 0x40000ad4;\nr_ble_hci_ram_reset = 0x40000ad8;\nr_ble_hci_ram_set_acl_free_cb = 0x40000adc;\nr_ble_hci_trans_acl_buf_alloc = 0x40000ae0;\nr_ble_hci_trans_buf_alloc = 0x40000ae4;\nr_ble_hci_trans_buf_free = 0x40000ae8;\nr_ble_hci_trans_cfg_hs = 0x40000aec;\nr_ble_hci_trans_cfg_ll = 0x40000af0;\nr_ble_hci_trans_deinit = 0x40000af4;\nr_ble_hci_trans_env_init = 0x40000af8;\nr_ble_hci_trans_init = 0x40000afc;\nr_ble_hci_uart_acl_tx = 0x40000b00;\nr_ble_hci_uart_cmdevt_tx = 0x40000b04;\nr_ble_hci_uart_config = 0x40000b08;\nr_ble_hci_uart_free_pkt = 0x40000b0c;\nr_ble_hci_uart_hs_acl_tx = 0x40000b10;\nr_ble_hci_uart_hs_cmd_tx = 0x40000b14;\nr_ble_hci_uart_ll_acl_tx = 0x40000b18;\nr_ble_hci_uart_ll_evt_tx = 0x40000b1c;\nr_ble_hci_uart_rx_acl = 0x40000b20;\nr_ble_hci_uart_rx_char = 0x40000b24;\nr_ble_hci_uart_rx_cmd = 0x40000b28;\nr_ble_hci_uart_rx_evt = 0x40000b2c;\nr_ble_hci_uart_rx_evt_cb = 0x40000b30;\nr_ble_hci_uart_rx_le_evt = 0x40000b34;\nr_ble_hci_uart_rx_pkt_type = 0x40000b38;\nr_ble_hci_uart_rx_skip_acl = 0x40000b3c;\nr_ble_hci_uart_rx_skip_cmd = 0x40000b40;\nr_ble_hci_uart_rx_skip_evt = 0x40000b44;\nr_ble_hci_uart_rx_sync_loss = 0x40000b48;\nr_ble_hci_uart_set_acl_free_cb = 0x40000b4c;\nr_ble_hci_uart_sync_lost = 0x40000b50;\nr_ble_hci_uart_trans_reset = 0x40000b54;\nr_ble_hci_uart_tx_char = 0x40000b58;\nr_ble_hci_uart_tx_pkt_type = 0x40000b5c;\nr_ble_hw_driver_deinit = 0x40000b60;\nr_ble_hw_driver_env_init = 0x40000b64;\nr_ble_hw_encrypt_block = 0x40000b68;\nr_ble_hw_get_public_addr = 0x40000b6c;\nr_ble_hw_get_static_addr = 0x40000b70;\nr_ble_hw_periodiclist_add = 0x40000b74;\nr_ble_hw_periodiclist_clear = 0x40000b78;\nr_ble_hw_periodiclist_rmv = 0x40000b7c;\nr_ble_hw_resolv_list_cur_entry = 0x40000b80;\nr_ble_hw_resolv_list_get_cur_entry = 0x40000b84;\nr_ble_hw_resolv_list_set = 0x40000b88;\nr_ble_hw_rng_init = 0x40000b8c;\nr_ble_hw_rng_start = 0x40000b90;\nr_ble_hw_rng_stop = 0x40000b94;\nr_ble_hw_rx_local_is_resolved = 0x40000b98;\nr_ble_hw_rx_local_is_rpa = 0x40000b9c;\nr_ble_hw_whitelist_add = 0x40000ba0;\nr_ble_hw_whitelist_clear = 0x40000ba4;\nr_ble_hw_whitelist_dev_num = 0x40000ba8;\nr_ble_hw_whitelist_get_base = 0x40000bac;\nr_ble_hw_whitelist_rmv = 0x40000bb0;\nr_ble_hw_whitelist_search = 0x40000bb4;\nr_ble_hw_whitelist_sort = 0x40000bb8;\nr_ble_ll_acl_data_in = 0x40000bbc;\nr_ble_ll_addr_is_id = 0x40000bc0;\nr_ble_ll_addr_subtype = 0x40000bc4;\nr_ble_ll_adv_active_chanset_clear = 0x40000bc8;\nr_ble_ll_adv_active_chanset_is_pri = 0x40000bcc;\nr_ble_ll_adv_active_chanset_is_sec = 0x40000bd0;\nr_ble_ll_adv_active_chanset_set_pri = 0x40000bd4;\nr_ble_ll_adv_active_chanset_set_sec = 0x40000bd8;\nr_ble_ll_adv_aux_calculate = 0x40000bdc;\nr_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000be0;\nr_ble_ll_adv_aux_pdu_make = 0x40000be4;\nr_ble_ll_adv_aux_scannable_pdu_make = 0x40000be8;\nr_ble_ll_adv_aux_txed = 0x40000bec;\nr_ble_ll_adv_can_chg_whitelist = 0x40000bf0;\nr_ble_ll_adv_chk_rpa_timeout = 0x40000bf4;\nr_ble_ll_adv_clear_all = 0x40000bf8;\nr_ble_ll_adv_conn_req_rxd = 0x40000bfc;\nr_ble_ll_adv_deinit = 0x40000c00;\nr_ble_ll_adv_enabled = 0x40000c04;\nr_ble_ll_adv_env_init = 0x40000c08;\nr_ble_ll_adv_ext_set_adv_data = 0x40000c0c;\nr_ble_ll_adv_ext_set_enable = 0x40000c10;\nr_ble_ll_adv_ext_set_param = 0x40000c14;\nr_ble_ll_adv_ext_set_scan_rsp = 0x40000c18;\nr_ble_ll_adv_final_chan = 0x40000c1c;\nr_ble_ll_adv_first_chan = 0x40000c20;\nr_ble_ll_adv_flags_clear = 0x40000c24;\nr_ble_ll_adv_flags_set = 0x40000c28;\nr_ble_ll_adv_get_chan_num = 0x40000c2c;\nr_ble_ll_adv_get_local_rpa = 0x40000c30;\nr_ble_ll_adv_get_peer_rpa = 0x40000c34;\nr_ble_ll_adv_hci_set_random_addr = 0x40000c38;\nr_ble_ll_adv_init = 0x40000c3c;\nr_ble_ll_adv_legacy_pdu_make = 0x40000c40;\nr_ble_ll_adv_next_chan = 0x40000c44;\nr_ble_ll_adv_pdu_make = 0x40000c48;\nr_ble_ll_adv_periodic_check_data_itvl = 0x40000c4c;\nr_ble_ll_adv_periodic_enable = 0x40000c50;\nr_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c54;\nr_ble_ll_adv_periodic_send_sync_ind = 0x40000c58;\nr_ble_ll_adv_periodic_set_data = 0x40000c5c;\nr_ble_ll_adv_periodic_set_info_transfer = 0x40000c60;\nr_ble_ll_adv_periodic_set_param = 0x40000c64;\nr_ble_ll_adv_pre_process = 0x40000c68;\nr_ble_ll_adv_put_acad_chM_update_ind = 0x40000c6c;\nr_ble_ll_adv_put_aux_ptr = 0x40000c70;\nr_ble_ll_adv_put_syncinfo = 0x40000c74;\nr_ble_ll_adv_rd_max_adv_data_len = 0x40000c78;\nr_ble_ll_adv_rd_sup_adv_sets = 0x40000c7c;\nr_ble_ll_adv_read_txpwr = 0x40000c80;\nr_ble_ll_adv_remove = 0x40000c84;\nr_ble_ll_adv_reset = 0x40000c88;\nr_ble_ll_adv_rpa_timeout = 0x40000c8c;\nr_ble_ll_adv_rpa_update = 0x40000c90;\nr_ble_ll_adv_rx_pkt_in = 0x40000c94;\nr_ble_ll_adv_scan_req_rxd = 0x40000c98;\nr_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c;\nr_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0;\nr_ble_ll_adv_scheduled = 0x40000ca4;\nr_ble_ll_adv_send_conn_comp_ev = 0x40000ca8;\nr_ble_ll_adv_set_adv_data = 0x40000cac;\nr_ble_ll_adv_set_adv_params = 0x40000cb0;\nr_ble_ll_adv_set_enable = 0x40000cb4;\nr_ble_ll_adv_set_random_addr = 0x40000cb8;\nr_ble_ll_adv_set_scan_rsp_data = 0x40000cbc;\nr_ble_ll_adv_set_sched = 0x40000cc0;\nr_ble_ll_adv_sm_deinit = 0x40000cc4;\nr_ble_ll_adv_sm_event_init = 0x40000cc8;\nr_ble_ll_adv_sm_find_configured = 0x40000ccc;\nr_ble_ll_adv_sm_get = 0x40000cd0;\nr_ble_ll_adv_sm_init = 0x40000cd4;\nr_ble_ll_adv_sm_reset = 0x40000cd8;\nr_ble_ll_adv_sm_start = 0x40000cdc;\nr_ble_ll_adv_sm_start_periodic = 0x40000ce0;\nr_ble_ll_adv_sm_stop = 0x40000ce4;\nr_ble_ll_adv_sm_stop_limit_reached = 0x40000ce8;\nr_ble_ll_adv_sm_stop_periodic = 0x40000cec;\nr_ble_ll_adv_sm_stop_timeout = 0x40000cf0;\nr_ble_ll_adv_sync_calculate = 0x40000cf4;\nr_ble_ll_adv_sync_get_pdu_len = 0x40000cf8;\nr_ble_ll_adv_sync_pdu_make = 0x40000cfc;\nr_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d00;\nr_ble_ll_adv_update_data_mbuf = 0x40000d04;\nr_ble_ll_adv_update_did = 0x40000d08;\nr_ble_ll_adv_update_periodic_data = 0x40000d0c;\nr_ble_ll_arr_pool_init = 0x40000d10;\nr_ble_ll_auth_pyld_tmo_event_send = 0x40000d14;\nr_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d18;\nr_ble_ll_calc_session_key = 0x40000d1c;\nr_ble_ll_calc_ticks_per_slot = 0x40000d20;\nr_ble_ll_check_scan_params = 0x40000d24;\nr_ble_ll_chk_txrx_octets = 0x40000d28;\nr_ble_ll_chk_txrx_time = 0x40000d2c;\nr_ble_ll_conn_adjust_pyld_len = 0x40000d30;\nr_ble_ll_conn_auth_pyld_timer_cb = 0x40000d34;\nr_ble_ll_conn_auth_pyld_timer_start = 0x40000d38;\nr_ble_ll_conn_calc_dci = 0x40000d3c;\nr_ble_ll_conn_calc_dci_csa1 = 0x40000d40;\nr_ble_ll_conn_calc_itvl_ticks = 0x40000d44;\nr_ble_ll_conn_chk_csm_flags = 0x40000d48;\nr_ble_ll_conn_chk_phy_upd_start = 0x40000d4c;\nr_ble_ll_conn_comp_event_send = 0x40000d50;\nr_ble_ll_conn_connect_ind_pdu_make = 0x40000d54;\nr_ble_ll_conn_create = 0x40000d58;\nr_ble_ll_conn_create_cancel = 0x40000d5c;\nr_ble_ll_conn_created = 0x40000d60;\nr_ble_ll_conn_cth_flow_enable = 0x40000d64;\nr_ble_ll_conn_cth_flow_error_fn = 0x40000d68;\nr_ble_ll_conn_cth_flow_have_credit = 0x40000d6c;\nr_ble_ll_conn_cth_flow_is_enabled = 0x40000d70;\nr_ble_ll_conn_cth_flow_process_cmd = 0x40000d74;\nr_ble_ll_conn_cth_flow_set_buffers = 0x40000d78;\nr_ble_ll_conn_enqueue_pkt = 0x40000d7c;\nr_ble_ll_conn_env_init = 0x40000d80;\nr_ble_ll_conn_ext_master_init = 0x40000d84;\nr_ble_ll_conn_find_active_conn = 0x40000d88;\nr_ble_ll_conn_get_active_conn = 0x40000d8c;\nr_ble_ll_conn_get_anchor = 0x40000d90;\nr_ble_ll_conn_hcc_params_set_fallback = 0x40000d94;\nr_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000d98;\nr_ble_ll_conn_hci_chk_conn_params = 0x40000d9c;\nr_ble_ll_conn_hci_chk_scan_params = 0x40000da0;\nr_ble_ll_conn_hci_disconnect_cmd = 0x40000da4;\nr_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000da8;\nr_ble_ll_conn_hci_le_ltk_reply = 0x40000dac;\nr_ble_ll_conn_hci_le_rd_phy = 0x40000db0;\nr_ble_ll_conn_hci_le_set_phy = 0x40000db4;\nr_ble_ll_conn_hci_le_start_encrypt = 0x40000db8;\nr_ble_ll_conn_hci_param_nrr = 0x40000dbc;\nr_ble_ll_conn_hci_param_rr = 0x40000dc0;\nr_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000dc4;\nr_ble_ll_conn_hci_rd_chan_map = 0x40000dc8;\nr_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000dcc;\nr_ble_ll_conn_hci_rd_rssi = 0x40000dd0;\nr_ble_ll_conn_hci_read_rem_features = 0x40000dd4;\nr_ble_ll_conn_hci_set_chan_class = 0x40000dd8;\nr_ble_ll_conn_hci_set_data_len = 0x40000ddc;\nr_ble_ll_conn_hci_update = 0x40000de0;\nr_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000de4;\nr_ble_ll_conn_init_phy = 0x40000de8;\nr_ble_ll_conn_is_empty_pdu = 0x40000df0;\nr_ble_ll_conn_is_lru = 0x40000df4;\nr_ble_ll_conn_master_init = 0x40000df8;\nr_ble_ll_conn_module_deinit = 0x40000dfc;\nr_ble_ll_conn_module_init = 0x40000e00;\nr_ble_ll_conn_module_reset = 0x40000e04;\nr_ble_ll_conn_next_event = 0x40000e08;\nr_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c;\nr_ble_ll_conn_prepare_tx_pdu = 0x40000e10;\nr_ble_ll_conn_process_conn_params = 0x40000e14;\nr_ble_ll_conn_req_peer_sca = 0x40000e18;\nr_ble_ll_conn_rx_data_pdu = 0x40000e1c;\nr_ble_ll_conn_set_csa = 0x40000e20;\nr_ble_ll_conn_set_ext_con_params = 0x40000e24;\nr_ble_ll_conn_set_global_chanmap = 0x40000e28;\nr_ble_ll_conn_set_phy = 0x40000e2c;\nr_ble_ll_conn_set_txpwr_by_handle = 0x40000e30;\nr_ble_ll_conn_set_unknown_rx_octets = 0x40000e34;\nr_ble_ll_conn_slave_start = 0x40000e38;\nr_ble_ll_conn_sm_get = 0x40000e3c;\nr_ble_ll_conn_sm_new = 0x40000e40;\nr_ble_ll_conn_sm_npl_deinit = 0x40000e44;\nr_ble_ll_conn_sm_npl_init = 0x40000e48;\nr_ble_ll_conn_tx_pkt_in = 0x40000e4c;\nr_ble_ll_conn_update_eff_data_len = 0x40000e50;\nr_ble_ll_ctrl_chanmap_req_make = 0x40000e54;\nr_ble_ll_ctrl_chk_proc_start = 0x40000e58;\nr_ble_ll_ctrl_conn_param_pdu_make = 0x40000e5c;\nr_ble_ll_ctrl_conn_param_pdu_proc = 0x40000e60;\nr_ble_ll_ctrl_conn_param_reply = 0x40000e64;\nr_ble_ll_ctrl_conn_upd_make = 0x40000e68;\nr_ble_ll_ctrl_datalen_upd_make = 0x40000e6c;\nr_ble_ll_ctrl_enc_allowed_pdu = 0x40000e70;\nr_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000e74;\nr_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40000e78;\nr_ble_ll_ctrl_enc_req_make = 0x40000e7c;\nr_ble_ll_ctrl_find_new_phy = 0x40000e80;\nr_ble_ll_ctrl_initiate_dle = 0x40000e84;\nr_ble_ll_ctrl_len_proc = 0x40000e88;\nr_ble_ll_ctrl_min_used_chan_rsp = 0x40000e8c;\nr_ble_ll_ctrl_phy_from_phy_mask = 0x40000e90;\nr_ble_ll_ctrl_phy_req_rsp_make = 0x40000e94;\nr_ble_ll_ctrl_phy_tx_transition_get = 0x40000e98;\nr_ble_ll_ctrl_phy_update_cancel = 0x40000e9c;\nr_ble_ll_ctrl_phy_update_ind_make = 0x40000ea0;\nr_ble_ll_ctrl_phy_update_proc_complete = 0x40000ea4;\nr_ble_ll_ctrl_proc_init = 0x40000ea8;\nr_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000eac;\nr_ble_ll_ctrl_proc_start = 0x40000eb0;\nr_ble_ll_ctrl_proc_stop = 0x40000eb4;\nr_ble_ll_ctrl_proc_unk_rsp = 0x40000eb8;\nr_ble_ll_ctrl_proc_with_instant_initiated = 0x40000ebc;\nr_ble_ll_ctrl_rej_ext_ind_make = 0x40000ec0;\nr_ble_ll_ctrl_reject_ind_send = 0x40000ec4;\nr_ble_ll_ctrl_rx_chanmap_req = 0x40000ec8;\nr_ble_ll_ctrl_rx_conn_param_req = 0x40000ecc;\nr_ble_ll_ctrl_rx_conn_param_rsp = 0x40000ed0;\nr_ble_ll_ctrl_rx_conn_update = 0x40000ed4;\nr_ble_ll_ctrl_rx_enc_req = 0x40000ed8;\nr_ble_ll_ctrl_rx_enc_rsp = 0x40000edc;\nr_ble_ll_ctrl_rx_feature_req = 0x40000ee0;\nr_ble_ll_ctrl_rx_feature_rsp = 0x40000ee4;\nr_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8;\nr_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec;\nr_ble_ll_ctrl_rx_pdu = 0x40000ef0;\nr_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4;\nr_ble_ll_ctrl_rx_phy_req = 0x40000ef8;\nr_ble_ll_ctrl_rx_phy_rsp = 0x40000efc;\nr_ble_ll_ctrl_rx_phy_update_ind = 0x40000f00;\nr_ble_ll_ctrl_rx_ping_rsp = 0x40000f04;\nr_ble_ll_ctrl_rx_reject_ind = 0x40000f08;\nr_ble_ll_ctrl_rx_sca_req = 0x40000f0c;\nr_ble_ll_ctrl_rx_sca_rsp = 0x40000f10;\nr_ble_ll_ctrl_rx_start_enc_req = 0x40000f14;\nr_ble_ll_ctrl_rx_start_enc_rsp = 0x40000f18;\nr_ble_ll_ctrl_rx_version_ind = 0x40000f1c;\nr_ble_ll_ctrl_sca_req_rsp_make = 0x40000f20;\nr_ble_ll_ctrl_start_enc_send = 0x40000f24;\nr_ble_ll_ctrl_start_rsp_timer = 0x40000f28;\nr_ble_ll_ctrl_terminate_start = 0x40000f2c;\nr_ble_ll_ctrl_tx_done = 0x40000f30;\nr_ble_ll_ctrl_update_features = 0x40000f34;\nr_ble_ll_ctrl_version_ind_make = 0x40000f38;\nr_ble_ll_data_buffer_overflow = 0x40000f3c;\nr_ble_ll_deinit = 0x40000f40;\nr_ble_ll_disconn_comp_event_send = 0x40000f44;\nr_ble_ll_env_init = 0x40000f48;\nr_ble_ll_event_comp_pkts = 0x40000f4c;\nr_ble_ll_event_dbuf_overflow = 0x40000f50;\nr_ble_ll_event_send = 0x40000f54;\nr_ble_ll_event_tx_pkt = 0x40000f58;\nr_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40000f5c;\nr_ble_ll_ext_conn_create = 0x40000f60;\nr_ble_ll_ext_scan_parse_adv_info = 0x40000f64;\nr_ble_ll_ext_scan_parse_aux_ptr = 0x40000f68;\nr_ble_ll_flush_pkt_queue = 0x40000f6c;\nr_ble_ll_generate_dh_key_v1 = 0x40000f70;\nr_ble_ll_generate_dh_key_v2 = 0x40000f74;\nr_ble_ll_generic_data_init = 0x40000f78;\nr_ble_ll_get_addr_type = 0x40000f7c;\nr_ble_ll_get_chan_to_scan = 0x40000f80;\nr_ble_ll_get_our_devaddr = 0x40000f84;\nr_ble_ll_get_tx_pwr_compensation = 0x40000f88;\nr_ble_ll_hci_acl_rx = 0x40000f8c;\nr_ble_ll_hci_adv_mode_ext = 0x40000f90;\nr_ble_ll_hci_adv_set_enable = 0x40000f94;\nr_ble_ll_hci_cb_host_buf_size = 0x40000f98;\nr_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x40000f9c;\nr_ble_ll_hci_cb_set_event_mask = 0x40000fa0;\nr_ble_ll_hci_cb_set_event_mask2 = 0x40000fa4;\nr_ble_ll_hci_chk_phy_masks = 0x40000fa8;\nr_ble_ll_hci_cmd_proc = 0x40000fac;\nr_ble_ll_hci_cmd_rx = 0x40000fb0;\nr_ble_ll_hci_ctlr_bb_cmd_proc = 0x40000fb4;\nr_ble_ll_hci_deinit = 0x40000fb8;\nr_ble_ll_hci_disconnect = 0x40000fbc;\nr_ble_ll_hci_env_init = 0x40000fc0;\nr_ble_ll_hci_ev_conn_update = 0x40000fc4;\nr_ble_ll_hci_ev_databuf_overflow = 0x40000fc8;\nr_ble_ll_hci_ev_datalen_chg = 0x40000fcc;\nr_ble_ll_hci_ev_encrypt_chg = 0x40000fd0;\nr_ble_ll_hci_ev_hw_err = 0x40000fd4;\nr_ble_ll_hci_ev_le_csa = 0x40000fd8;\nr_ble_ll_hci_ev_ltk_req = 0x40000fdc;\nr_ble_ll_hci_ev_phy_update = 0x40000fe0;\nr_ble_ll_hci_ev_rd_rem_used_feat = 0x40000fe4;\nr_ble_ll_hci_ev_rd_rem_ver = 0x40000fe8;\nr_ble_ll_hci_ev_rem_conn_parm_req = 0x40000fec;\nr_ble_ll_hci_ev_sca_update = 0x40000ff0;\nr_ble_ll_hci_ev_send_adv_set_terminated = 0x40000ff4;\nr_ble_ll_hci_ev_send_scan_req_recv = 0x40000ff8;\nr_ble_ll_hci_ev_send_scan_timeout = 0x40000ffc;\nr_ble_ll_hci_ev_send_vendor_err = 0x40001000;\nr_ble_ll_hci_event_send = 0x40001004;\nr_ble_ll_hci_ext_scan_set_enable = 0x40001008;\nr_ble_ll_hci_get_num_cmd_pkts = 0x4000100c;\nr_ble_ll_hci_info_params_cmd_proc = 0x40001010;\nr_ble_ll_hci_init = 0x40001014;\nr_ble_ll_hci_init_support_cmd_base_on_lmp_ver = 0x40001018;\nr_ble_ll_hci_is_event_enabled = 0x4000101c;\nr_ble_ll_hci_is_le_event_enabled = 0x40001020;\nr_ble_ll_hci_le_cmd_proc = 0x40001024;\nr_ble_ll_hci_le_cmd_send_cmd_status = 0x40001028;\nr_ble_ll_hci_le_encrypt = 0x4000102c;\nr_ble_ll_hci_le_rand = 0x40001030;\nr_ble_ll_hci_le_rd_max_data_len = 0x40001034;\nr_ble_ll_hci_le_rd_sugg_data_len = 0x40001038;\nr_ble_ll_hci_le_read_bufsize = 0x4000103c;\nr_ble_ll_hci_le_read_local_features = 0x40001040;\nr_ble_ll_hci_le_read_supp_states = 0x40001044;\nr_ble_ll_hci_le_set_def_phy = 0x40001048;\nr_ble_ll_hci_le_wr_sugg_data_len = 0x4000104c;\nr_ble_ll_hci_link_ctrl_cmd_proc = 0x40001050;\nr_ble_ll_hci_npl_init = 0x40001054;\nr_ble_ll_hci_post_gen_dhkey_cmp_evt = 0x40001058;\nr_ble_ll_hci_post_rd_p256_pubkey_cmp_evt = 0x4000105c;\nr_ble_ll_hci_rd_bd_addr = 0x40001060;\nr_ble_ll_hci_rd_local_supp_cmd = 0x40001064;\nr_ble_ll_hci_rd_local_supp_feat = 0x40001068;\nr_ble_ll_hci_rd_local_version = 0x4000106c;\nr_ble_ll_hci_scan_set_enable = 0x40001070;\nr_ble_ll_hci_send_adv_report = 0x40001074;\nr_ble_ll_hci_send_dir_adv_report = 0x40001078;\nr_ble_ll_hci_send_ext_adv_report = 0x4000107c;\nr_ble_ll_hci_send_legacy_ext_adv_report = 0x40001080;\nr_ble_ll_hci_send_noop = 0x40001084;\nr_ble_ll_hci_set_adv_data = 0x40001088;\nr_ble_ll_hci_set_le_event_mask = 0x4000108c;\nr_ble_ll_hci_set_scan_rsp_data = 0x40001090;\nr_ble_ll_hci_status_params_cmd_proc = 0x40001094;\nr_ble_ll_hci_vs_cmd_proc = 0x40001098;\nr_ble_ll_hci_vs_rd_static_addr = 0x4000109c;\nr_ble_ll_hw_err_timer_cb = 0x400010a0;\nr_ble_ll_hw_error = 0x400010a4;\nr_ble_ll_init = 0x400010a8;\nr_ble_ll_init_alloc_conn_comp_ev = 0x400010ac;\nr_ble_ll_init_get_conn_comp_ev = 0x400010b0;\nr_ble_ll_init_rx_pkt_in = 0x400010b4;\nr_ble_ll_is_addr_empty = 0x400010b8;\nr_ble_ll_is_controller_busy = 0x400010bc;\nr_ble_ll_is_on_resolv_list = 0x400010c0;\nr_ble_ll_is_our_devaddr = 0x400010c4;\nr_ble_ll_is_rpa = 0x400010c8;\nr_ble_ll_is_valid_adv_mode = 0x400010cc;\nr_ble_ll_is_valid_own_addr_type = 0x400010d0;\nr_ble_ll_is_valid_public_addr = 0x400010d4;\nr_ble_ll_is_valid_random_addr = 0x400010d8;\nr_ble_ll_mbuf_init = 0x400010dc;\nr_ble_ll_misc_options_set = 0x400010e0;\nr_ble_ll_modify_sca = 0x400010e4;\nr_ble_ll_modify_sca_action = 0x400010e8;\nr_ble_ll_pdu_max_tx_octets_get = 0x400010ec;\nr_ble_ll_pdu_tx_time_get = 0x400010f0;\nr_ble_ll_phy_to_phy_mode = 0x400010f4;\nr_ble_ll_qa_enable = 0x400010f8;\nr_ble_ll_rand = 0x400010fc;\nr_ble_ll_rand_data_get = 0x40001100;\nr_ble_ll_rand_deinit = 0x40001104;\nr_ble_ll_rand_env_init = 0x40001108;\nr_ble_ll_rand_init = 0x4000110c;\nr_ble_ll_rand_prand_get = 0x40001110;\nr_ble_ll_rand_sample = 0x40001114;\nr_ble_ll_rand_start = 0x40001118;\nr_ble_ll_read_local_p256_pub_key = 0x4000111c;\nr_ble_ll_read_rf_path_compensation = 0x40001120;\nr_ble_ll_read_supp_features = 0x40001124;\nr_ble_ll_read_supp_states = 0x40001128;\nr_ble_ll_read_tx_power = 0x4000112c;\nr_ble_ll_reset = 0x40001130;\nr_ble_ll_resolv_clear_all_pl_bit = 0x40001134;\nr_ble_ll_resolv_clear_all_wl_bit = 0x40001138;\nr_ble_ll_resolv_deinit = 0x4000113c;\nr_ble_ll_resolv_enable_cmd = 0x40001140;\nr_ble_ll_resolv_enabled = 0x40001144;\nr_ble_ll_resolv_env_init = 0x40001148;\nr_ble_ll_resolv_gen_priv_addr = 0x4000114c;\nr_ble_ll_resolv_gen_rpa = 0x40001150;\nr_ble_ll_resolv_get_addr_pointer = 0x40001154;\nr_ble_ll_resolv_get_index = 0x40001158;\nr_ble_ll_resolv_get_irk_pointer = 0x4000115c;\nr_ble_ll_resolv_get_list = 0x40001160;\nr_ble_ll_resolv_get_priv_addr = 0x40001164;\nr_ble_ll_resolv_get_rpa_tmo = 0x40001168;\nr_ble_ll_resolv_init = 0x4000116c;\nr_ble_ll_resolv_irk_nonzero = 0x40001170;\nr_ble_ll_resolv_list_add = 0x40001174;\nr_ble_ll_resolv_list_chg_allowed = 0x40001178;\nr_ble_ll_resolv_list_clr = 0x4000117c;\nr_ble_ll_resolv_list_find = 0x40001180;\nr_ble_ll_resolv_list_read_size = 0x40001184;\nr_ble_ll_resolv_list_reset = 0x40001188;\nr_ble_ll_resolv_list_rmv = 0x4000118c;\nr_ble_ll_resolv_local_addr_rd = 0x40001190;\nr_ble_ll_resolv_peer_addr_rd = 0x40001194;\nr_ble_ll_resolv_peer_rpa_any = 0x40001198;\nr_ble_ll_resolv_reset = 0x4000119c;\nr_ble_ll_resolv_rpa = 0x400011a0;\nr_ble_ll_resolv_rpa_timer_cb = 0x400011a4;\nr_ble_ll_resolv_set_local_rpa = 0x400011a8;\nr_ble_ll_resolv_set_peer_rpa = 0x400011ac;\nr_ble_ll_resolv_set_rpa_tmo = 0x400011b0;\nr_ble_ll_resolve_set_priv_mode = 0x400011b4;\nr_ble_ll_rxpdu_alloc = 0x400011b8;\nr_ble_ll_scan_add_scan_rsp_adv = 0x400011bc;\nr_ble_ll_scan_adv_decode_addr = 0x400011c0;\nr_ble_ll_scan_aux_data_ref = 0x400011c4;\nr_ble_ll_scan_aux_data_unref = 0x400011c8;\nr_ble_ll_scan_can_chg_whitelist = 0x400011cc;\nr_ble_ll_scan_check_periodic_sync = 0x400011d0;\nr_ble_ll_scan_classify_filter_aux_init = 0x400011d4;\nr_ble_ll_scan_classify_filter_init = 0x400011d8;\nr_ble_ll_scan_common_init = 0x400011dc;\nr_ble_ll_scan_continue_en = 0x400011e0;\nr_ble_ll_scan_deinit = 0x400011e4;\nr_ble_ll_scan_dup_check_ext = 0x400011e8;\nr_ble_ll_scan_dup_check_legacy = 0x400011ec;\nr_ble_ll_scan_dup_move_to_head = 0x400011f0;\nr_ble_ll_scan_dup_new = 0x400011f4;\nr_ble_ll_scan_dup_update_ext = 0x400011f8;\nr_ble_ll_scan_dup_update_legacy = 0x400011fc;\nr_ble_ll_scan_enabled = 0x40001200;\nr_ble_ll_scan_end_adv_evt = 0x40001204;\nr_ble_ll_scan_env_init = 0x40001208;\nr_ble_ll_scan_ext_initiator_start = 0x4000120c;\nr_ble_ll_scan_get_addr_data_from_legacy = 0x40001210;\nr_ble_ll_scan_get_addr_from_ext_adv = 0x40001214;\nr_ble_ll_scan_get_cur_sm = 0x40001218;\nr_ble_ll_scan_get_ext_adv_report = 0x4000121c;\nr_ble_ll_scan_get_local_rpa = 0x40001220;\nr_ble_ll_scan_get_next_adv_prim_chan = 0x40001224;\nr_ble_ll_scan_get_peer_rpa = 0x40001228;\nr_ble_ll_scan_have_rxd_scan_rsp = 0x4000122c;\nr_ble_ll_scan_init = 0x40001230;\nr_ble_ll_scan_initiator_start = 0x40001234;\nr_ble_ll_scan_is_inside_window = 0x40001238;\nr_ble_ll_scan_move_window_to = 0x4000123c;\nr_ble_ll_scan_npl_reset = 0x40001240;\nr_ble_ll_scan_parse_auxptr = 0x40001244;\nr_ble_ll_scan_parse_ext_hdr = 0x40001248;\nr_ble_ll_scan_pre_process = 0x4000124c;\nr_ble_ll_scan_record_new_adv = 0x40001250;\nr_ble_ll_scan_refresh_nrpa = 0x40001254;\nr_ble_ll_scan_reset = 0x40001258;\nr_ble_ll_scan_rx_pkt_in = 0x4000125c;\nr_ble_ll_scan_rx_pkt_in_on_aux = 0x40001260;\nr_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001264;\nr_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268;\nr_ble_ll_scan_rxed = 0x4000126c;\nr_ble_ll_scan_send_adv_report = 0x40001270;\nr_ble_ll_scan_send_truncated = 0x40001274;\nr_ble_ll_scan_set_enable = 0x40001278;\nr_ble_ll_scan_set_peer_rpa = 0x4000127c;\nr_ble_ll_scan_set_perfer_addr = 0x40001280;\nr_ble_ll_scan_set_scan_params = 0x40001284;\nr_ble_ll_scan_sm_start = 0x40001288;\nr_ble_ll_scan_sm_stop = 0x4000128c;\nr_ble_ll_scan_time_hci_to_ticks = 0x40001290;\nr_ble_ll_scan_update_aux_data = 0x40001294;\nr_ble_ll_scan_whitelist_enabled = 0x40001298;\nr_ble_ll_set_default_privacy_mode = 0x4000129c;\nr_ble_ll_set_default_sync_transfer_params = 0x400012a0;\nr_ble_ll_set_ext_scan_params = 0x400012a4;\nr_ble_ll_set_host_feat = 0x400012a8;\nr_ble_ll_set_public_addr = 0x400012ac;\nr_ble_ll_set_random_addr = 0x400012b0;\nr_ble_ll_set_sync_transfer_params = 0x400012b4;\nr_ble_ll_state_get = 0x400012b8;\nr_ble_ll_state_set = 0x400012bc;\nr_ble_ll_sync_adjust_ext_hdr = 0x400012c0;\nr_ble_ll_sync_cancel = 0x400012c4;\nr_ble_ll_sync_cancel_complete_event = 0x400012c8;\nr_ble_ll_sync_check_acad = 0x400012cc;\nr_ble_ll_sync_check_failed = 0x400012d0;\nr_ble_ll_sync_create = 0x400012d4;\nr_ble_ll_sync_deinit = 0x400012d8;\nr_ble_ll_sync_enabled = 0x400012dc;\nr_ble_ll_sync_env_init = 0x400012e0;\nr_ble_ll_sync_est_event_failed = 0x400012e4;\nr_ble_ll_sync_est_event_success = 0x400012e8;\nr_ble_ll_sync_established = 0x400012ec;\nr_ble_ll_sync_filter_enabled = 0x400012f0;\nr_ble_ll_sync_find = 0x400012f4;\nr_ble_ll_sync_get_cur_sm = 0x400012f8;\nr_ble_ll_sync_get_handle = 0x400012fc;\nr_ble_ll_sync_get_sm = 0x40001300;\nr_ble_ll_sync_info_event = 0x40001304;\nr_ble_ll_sync_init = 0x40001308;\nr_ble_ll_sync_list_add = 0x4000130c;\nr_ble_ll_sync_list_clear = 0x40001310;\nr_ble_ll_sync_list_empty = 0x40001314;\nr_ble_ll_sync_list_get_free = 0x40001318;\nr_ble_ll_sync_list_remove = 0x4000131c;\nr_ble_ll_sync_list_search = 0x40001320;\nr_ble_ll_sync_list_size = 0x40001324;\nr_ble_ll_sync_lost_event = 0x40001328;\nr_ble_ll_sync_next_event = 0x4000132c;\nr_ble_ll_sync_on_list = 0x40001330;\nr_ble_ll_sync_parse_ext_hdr = 0x40001334;\nr_ble_ll_sync_periodic_ind = 0x40001338;\nr_ble_ll_sync_phy_mode_to_aux_phy = 0x4000133c;\nr_ble_ll_sync_phy_mode_to_hci = 0x40001340;\nr_ble_ll_sync_put_syncinfo = 0x40001344;\nr_ble_ll_sync_receive_enable = 0x40001348;\nr_ble_ll_sync_reserve = 0x4000134c;\nr_ble_ll_sync_reset = 0x40001350;\nr_ble_ll_sync_reset_sm = 0x40001354;\nr_ble_ll_sync_rx_pkt_in = 0x40001358;\nr_ble_ll_sync_send_per_adv_rpt = 0x4000135c;\nr_ble_ll_sync_send_sync_ind = 0x40001360;\nr_ble_ll_sync_send_truncated_per_adv_rpt = 0x40001364;\nr_ble_ll_sync_sm_clear = 0x40001368;\nr_ble_ll_sync_terminate = 0x4000136c;\nr_ble_ll_sync_transfer = 0x40001370;\nr_ble_ll_sync_transfer_get = 0x40001374;\nr_ble_ll_sync_transfer_received = 0x40001378;\nr_ble_ll_task = 0x4000137c;\nr_ble_ll_trace_set_func = 0x40001380;\nr_ble_ll_trace_u32 = 0x40001384;\nr_ble_ll_trace_u32x2 = 0x40001388;\nr_ble_ll_trace_u32x3 = 0x4000138c;\nr_ble_ll_tx_flat_mbuf_pducb = 0x40001390;\nr_ble_ll_tx_mbuf_pducb = 0x40001394;\nr_ble_ll_tx_pkt_in = 0x40001398;\nr_ble_ll_update_max_tx_octets_phy_mode = 0x4000139c;\nr_ble_ll_usecs_to_ticks_round_up = 0x400013a0;\nr_ble_ll_utils_calc_access_addr = 0x400013a4;\nr_ble_ll_utils_calc_dci_csa2 = 0x400013a8;\nr_ble_ll_utils_calc_num_used_chans = 0x400013ac;\nr_ble_ll_utils_calc_window_widening = 0x400013b0;\nr_ble_ll_utils_csa2_perm = 0x400013b4;\nr_ble_ll_utils_csa2_prng = 0x400013b8;\nr_ble_ll_utils_remapped_channel = 0x400013bc;\nr_ble_ll_whitelist_add = 0x400013c0;\nr_ble_ll_whitelist_chg_allowed = 0x400013c4;\nr_ble_ll_whitelist_clear = 0x400013c8;\nr_ble_ll_whitelist_read_size = 0x400013cc;\nr_ble_ll_whitelist_rmv = 0x400013d0;\nr_ble_ll_whitelist_search = 0x400013d4;\nr_ble_ll_write_rf_path_compensation = 0x400013d8;\nr_ble_lll_adv_aux_scannable_pdu_payload_len = 0x400013dc;\nr_ble_lll_adv_aux_schedule = 0x400013e0;\nr_ble_lll_adv_aux_schedule_first = 0x400013e4;\nr_ble_lll_adv_aux_schedule_next = 0x400013e8;\nr_ble_lll_adv_aux_scheduled = 0x400013ec;\nr_ble_lll_adv_aux_set_start_time = 0x400013f0;\nr_ble_lll_adv_coex_dpc_calc_pti_update_itvl = 0x400013f4;\nr_ble_lll_adv_coex_dpc_process_pri = 0x400013f8;\nr_ble_lll_adv_coex_dpc_process_sec = 0x400013fc;\nr_ble_lll_adv_coex_dpc_pti_get = 0x40001400;\nr_ble_lll_adv_coex_dpc_update = 0x40001404;\nr_ble_lll_adv_coex_dpc_update_on_adv_start = 0x40001408;\nr_ble_lll_adv_coex_dpc_update_on_aux_scheduled = 0x4000140c;\nr_ble_lll_adv_coex_dpc_update_on_data_updated = 0x40001410;\nr_ble_lll_adv_coex_dpc_update_on_event_end = 0x40001414;\nr_ble_lll_adv_coex_dpc_update_on_event_scheduled = 0x40001418;\nr_ble_lll_adv_done = 0x4000141c;\nr_ble_lll_adv_drop_event = 0x40001420;\nr_ble_lll_adv_event_done = 0x40001424;\nr_ble_lll_adv_event_rmvd_from_sched = 0x40001428;\nr_ble_lll_adv_ext_estimate_data_itvl = 0x4000142c;\nr_ble_lll_adv_get_sec_pdu_len = 0x40001430;\nr_ble_lll_adv_halt = 0x40001434;\nr_ble_lll_adv_make_done = 0x40001438;\nr_ble_lll_adv_periodic_done = 0x4000143c;\nr_ble_lll_adv_periodic_event_done = 0x40001440;\nr_ble_lll_adv_periodic_rmvd_from_sched = 0x40001444;\nr_ble_lll_adv_periodic_schedule_first = 0x40001448;\nr_ble_lll_adv_periodic_schedule_next = 0x4000144c;\nr_ble_lll_adv_periodic_start = 0x40001450;\nr_ble_lll_adv_periodic_stop = 0x40001454;\nr_ble_lll_adv_pri_schedule_tx_pdu = 0x40001458;\nr_ble_lll_adv_reschedule_event = 0x4000145c;\nr_ble_lll_adv_reschedule_periodic_event = 0x40001460;\nr_ble_lll_adv_rx_pkt_isr = 0x40001464;\nr_ble_lll_adv_sec_done = 0x40001468;\nr_ble_lll_adv_sec_event_done = 0x4000146c;\nr_ble_lll_adv_sec_schedule_next_aux = 0x40001470;\nr_ble_lll_adv_secondary_tx_start_cb = 0x40001474;\nr_ble_lll_adv_sm_deinit = 0x40001478;\nr_ble_lll_adv_sm_event_init = 0x4000147c;\nr_ble_lll_adv_sm_event_restore = 0x40001480;\nr_ble_lll_adv_sm_event_store = 0x40001484;\nr_ble_lll_adv_sm_init = 0x40001488;\nr_ble_lll_adv_sm_reset = 0x4000148c;\nr_ble_lll_adv_start = 0x40001490;\nr_ble_lll_adv_stop = 0x40001494;\nr_ble_lll_adv_sync_next_scheduled = 0x40001498;\nr_ble_lll_adv_sync_schedule = 0x4000149c;\nr_ble_lll_adv_sync_tx_done = 0x400014a0;\nr_ble_lll_adv_sync_tx_end = 0x400014a4;\nr_ble_lll_adv_sync_tx_start_cb = 0x400014a8;\nr_ble_lll_adv_tx_done = 0x400014ac;\nr_ble_lll_adv_tx_start_cb = 0x400014b0;\nr_ble_lll_adv_update_rsp_offset = 0x400014b4;\nr_ble_lll_aux_scan_cb = 0x400014b8;\nr_ble_lll_aux_scan_drop = 0x400014bc;\nr_ble_lll_aux_scan_drop_event_cb = 0x400014c0;\nr_ble_lll_calc_us_convert_tick_unit = 0x400014c4;\nr_ble_lll_conn_append_tx_buffer = 0x400014c8;\nr_ble_lll_conn_can_send_next_pdu = 0x400014cc;\nr_ble_lll_conn_check_opcode_matched = 0x400014d0;\nr_ble_lll_conn_coex_dpc_process = 0x400014d4;\nr_ble_lll_conn_coex_dpc_pti_get = 0x400014d8;\nr_ble_lll_conn_coex_dpc_update = 0x400014dc;\nr_ble_lll_conn_coex_dpc_update_on_event_end = 0x400014e0;\nr_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4;\nr_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8;\nr_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec;\nr_ble_lll_conn_cth_flow_free_credit = 0x400014f0;\nr_ble_lll_conn_current_sm_over = 0x400014f4;\nr_ble_lll_conn_env_deinit = 0x400014fc;\nr_ble_lll_conn_env_init = 0x40001500;\nr_ble_lll_conn_event_end = 0x40001504;\nr_ble_lll_conn_event_end_timer_cb = 0x40001508;\nr_ble_lll_conn_event_halt = 0x4000150c;\nr_ble_lll_conn_event_is_over = 0x40001510;\nr_ble_lll_conn_event_start_cb = 0x40001514;\nr_ble_lll_conn_free_rx_mbuf = 0x40001518;\nr_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c;\nr_ble_lll_conn_get_ce_end_time = 0x40001520;\nr_ble_lll_conn_get_next_sched_time = 0x40001524;\nr_ble_lll_conn_get_rx_mbuf = 0x40001528;\nr_ble_lll_conn_halt = 0x4000152c;\nr_ble_lll_conn_master_common_init = 0x40001530;\nr_ble_lll_conn_master_new = 0x40001534;\nr_ble_lll_conn_module_deinit = 0x40001538;\nr_ble_lll_conn_module_init = 0x4000153c;\nr_ble_lll_conn_module_reset = 0x40001540;\nr_ble_lll_conn_no_mem_evt_pre_cb = 0x40001544;\nr_ble_lll_conn_pre_process = 0x40001548;\nr_ble_lll_conn_process_acked_pdu = 0x4000154c;\nr_ble_lll_conn_process_in_isr = 0x40001550;\nr_ble_lll_conn_recv_ack = 0x40001554;\nr_ble_lll_conn_recv_valid_packet = 0x40001558;\nr_ble_lll_conn_reset_pending_sched = 0x4000155c;\nr_ble_lll_conn_rx_pkt_isr = 0x40001560;\nr_ble_lll_conn_sched_next_anchor = 0x40001564;\nr_ble_lll_conn_sched_next_event = 0x40001568;\nr_ble_lll_conn_set_slave_flow_control = 0x4000156c;\nr_ble_lll_conn_slave_new = 0x40001570;\nr_ble_lll_conn_sm_new = 0x40001574;\nr_ble_lll_conn_sm_npl_deinit = 0x40001578;\nr_ble_lll_conn_sm_npl_init = 0x4000157c;\nr_ble_lll_conn_superversion_timer_cb = 0x40001580;\nr_ble_lll_conn_timeout = 0x40001584;\nr_ble_lll_conn_update_anchor = 0x40001588;\nr_ble_lll_conn_update_conn_ind_params = 0x4000158c;\nr_ble_lll_conn_update_encryption = 0x40001590;\nr_ble_lll_conn_update_tx_buffer = 0x40001594;\nr_ble_lll_deinit = 0x40001598;\nr_ble_lll_dtm_calculate_itvl = 0x4000159c;\nr_ble_lll_dtm_ctx_free = 0x400015a0;\nr_ble_lll_dtm_deinit = 0x400015a4;\nr_ble_lll_dtm_end_test = 0x400015a8;\nr_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;\nr_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;\nr_ble_lll_dtm_init = 0x400015b4;\nr_ble_lll_dtm_reset = 0x400015b8;\nr_ble_lll_dtm_rx_create_ctx = 0x400015bc;\nr_ble_lll_dtm_rx_isr_end = 0x400015c0;\nr_ble_lll_dtm_rx_isr_start = 0x400015c4;\nr_ble_lll_dtm_rx_pkt_in = 0x400015c8;\nr_ble_lll_dtm_rx_sched_cb = 0x400015cc;\nr_ble_lll_dtm_rx_start = 0x400015d0;\nr_ble_lll_dtm_rx_test = 0x400015d4;\nr_ble_lll_dtm_set_next = 0x400015d8;\nr_ble_lll_dtm_tx_create_ctx = 0x400015dc;\nr_ble_lll_dtm_tx_done = 0x400015e0;\nr_ble_lll_dtm_tx_sched_cb = 0x400015e4;\nr_ble_lll_dtm_tx_test = 0x400015e8;\nr_ble_lll_dtm_wfr_timer_exp = 0x400015ec;\nr_ble_lll_event_rx_pkt = 0x400015f0;\nr_ble_lll_ext_scan_coex_dpc_process = 0x400015f4;\nr_ble_lll_ext_scan_coex_dpc_pti_get = 0x400015f8;\nr_ble_lll_ext_scan_coex_dpc_update = 0x400015fc;\nr_ble_lll_ext_scan_coex_dpc_update_on_start = 0x40001600;\nr_ble_lll_hci_dtm_rx_test = 0x40001604;\nr_ble_lll_hci_dtm_rx_test_v2 = 0x40001608;\nr_ble_lll_hci_dtm_tx_test = 0x4000160c;\nr_ble_lll_hci_dtm_tx_test_ext = 0x40001610;\nr_ble_lll_hci_dtm_tx_test_v2 = 0x40001614;\nr_ble_lll_hci_dtm_tx_test_v2_ext = 0x40001618;\nr_ble_lll_init = 0x4000161c;\nr_ble_lll_init_pre_process = 0x40001620;\nr_ble_lll_init_rx_pkt_isr = 0x40001624;\nr_ble_lll_per_adv_coex_dpc_calc_pti_update_itvl = 0x40001628;\nr_ble_lll_per_adv_coex_dpc_process = 0x4000162c;\nr_ble_lll_per_adv_coex_dpc_pti_get = 0x40001630;\nr_ble_lll_per_adv_coex_dpc_update = 0x40001634;\nr_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638;\nr_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c;\nr_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640;\nr_ble_lll_reset = 0x40001644;\nr_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;\nr_ble_lll_rfmgmt_deinit = 0x4000164c;\nr_ble_lll_rfmgmt_disable = 0x40001650;\nr_ble_lll_rfmgmt_enable = 0x40001654;\nr_ble_lll_rfmgmt_enable_now = 0x40001658;\nr_ble_lll_rfmgmt_init = 0x4000165c;\nr_ble_lll_rfmgmt_is_enabled = 0x40001660;\nr_ble_lll_rfmgmt_release = 0x40001664;\nr_ble_lll_rfmgmt_release_ev = 0x40001668;\nr_ble_lll_rfmgmt_reset = 0x4000166c;\nr_ble_lll_rfmgmt_scan_changed = 0x40001670;\nr_ble_lll_rfmgmt_sched_changed = 0x40001674;\nr_ble_lll_rfmgmt_set_sleep_cb = 0x40001678;\nr_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c;\nr_ble_lll_rfmgmt_timer_exp = 0x40001680;\nr_ble_lll_rfmgmt_timer_reschedule = 0x40001684;\nr_ble_lll_rx_pdu_in = 0x40001688;\nr_ble_lll_rx_pkt_in = 0x4000168c;\nr_ble_lll_rx_pkt_isr = 0x40001690;\nr_ble_lll_scan_abort_aux_sched = 0x40001694;\nr_ble_lll_scan_aux_data_free = 0x40001698;\nr_ble_lll_scan_chk_resume = 0x4000169c;\nr_ble_lll_scan_clean_cur_aux_data = 0x400016a0;\nr_ble_lll_scan_coex_event_cb = 0x400016a4;\nr_ble_lll_scan_common_init = 0x400016a8;\nr_ble_lll_scan_deinit = 0x400016ac;\nr_ble_lll_scan_duration_period_timers_restart = 0x400016b0;\nr_ble_lll_scan_duration_period_timers_stop = 0x400016b4;\nr_ble_lll_scan_duration_timer_cb = 0x400016b8;\nr_ble_lll_scan_event_proc = 0x400016bc;\nr_ble_lll_scan_ext_adv_init = 0x400016c0;\nr_ble_lll_scan_halt = 0x400016c4;\nr_ble_lll_scan_has_sent_scan_req = 0x400016c8;\nr_ble_lll_scan_init = 0x400016cc;\nr_ble_lll_scan_npl_init = 0x400016d0;\nr_ble_lll_scan_npl_reset = 0x400016d4;\nr_ble_lll_scan_npl_restore = 0x400016d8;\nr_ble_lll_scan_npl_store = 0x400016dc;\nr_ble_lll_scan_period_timer_cb = 0x400016e0;\nr_ble_lll_scan_process_adv_in_isr = 0x400016e4;\nr_ble_lll_scan_process_rsp_in_isr = 0x400016e8;\nr_ble_lll_scan_req_backoff = 0x400016ec;\nr_ble_lll_scan_restart = 0x400016f0;\nr_ble_lll_scan_rx_isr_on_aux = 0x400016f4;\nr_ble_lll_scan_rx_isr_on_legacy = 0x400016f8;\nr_ble_lll_scan_rx_pkt_isr = 0x400016fc;\nr_ble_lll_scan_sched_next_aux = 0x40001700;\nr_ble_lll_scan_sched_remove = 0x40001704;\nr_ble_lll_scan_start = 0x40001708;\nr_ble_lll_scan_start_rx = 0x4000170c;\nr_ble_lll_scan_stop = 0x40001710;\nr_ble_lll_scan_targeta_is_matched = 0x40001714;\nr_ble_lll_scan_timer_cb = 0x40001718;\nr_ble_lll_sched_adv_new = 0x4000171c;\nr_ble_lll_sched_adv_resched_pdu = 0x40001720;\nr_ble_lll_sched_adv_reschedule = 0x40001724;\nr_ble_lll_sched_aux_scan = 0x40001728;\nr_ble_lll_sched_conn_overlap = 0x4000172c;\nr_ble_lll_sched_conn_reschedule = 0x40001730;\nr_ble_lll_sched_deinit = 0x40001734;\nr_ble_lll_sched_dtm = 0x40001738;\nr_ble_lll_sched_env_init = 0x4000173c;\nr_ble_lll_sched_execute_item = 0x40001744;\nr_ble_lll_sched_init = 0x40001748;\nr_ble_lll_sched_insert_if_empty = 0x4000174c;\nr_ble_lll_sched_is_overlap = 0x40001750;\nr_ble_lll_sched_master_new = 0x40001754;\nr_ble_lll_sched_next_time = 0x40001758;\nr_ble_lll_sched_overlaps_current = 0x4000175c;\nr_ble_lll_sched_periodic_adv = 0x40001760;\nr_ble_lll_sched_rmv_elem = 0x40001764;\nr_ble_lll_sched_rmv_elem_type = 0x40001768;\nr_ble_lll_sched_run = 0x4000176c;\nr_ble_lll_sched_scan_req_over_aux_ptr = 0x40001770;\nr_ble_lll_sched_slave_new = 0x40001774;\nr_ble_lll_sched_stop = 0x40001778;\nr_ble_lll_sched_sync = 0x4000177c;\nr_ble_lll_sched_sync_overlaps_current = 0x40001780;\nr_ble_lll_sched_sync_reschedule = 0x40001784;\nr_ble_lll_sync_chain_start_cb = 0x40001788;\nr_ble_lll_sync_coex_dpc_process = 0x4000178c;\nr_ble_lll_sync_coex_dpc_pti_get = 0x40001790;\nr_ble_lll_sync_coex_dpc_update = 0x40001794;\nr_ble_lll_sync_current_sm_over = 0x40001798;\nr_ble_lll_sync_deinit = 0x4000179c;\nr_ble_lll_sync_event_end = 0x400017a0;\nr_ble_lll_sync_event_end_cb = 0x400017a4;\nr_ble_lll_sync_event_start_cb = 0x400017a8;\nr_ble_lll_sync_get_event_end_time = 0x400017ac;\nr_ble_lll_sync_halt = 0x400017b0;\nr_ble_lll_sync_init = 0x400017b4;\nr_ble_lll_sync_new = 0x400017b8;\nr_ble_lll_sync_reset = 0x400017bc;\nr_ble_lll_sync_reset_sm = 0x400017c0;\nr_ble_lll_sync_rmvd_from_sched = 0x400017c4;\nr_ble_lll_sync_rx_pkt_isr = 0x400017c8;\nr_ble_lll_sync_schedule_chain = 0x400017cc;\nr_ble_lll_sync_stop = 0x400017d0;\nr_ble_lll_sync_trnasfer_sched = 0x400017d4;\nr_ble_phy_access_addr_get = 0x400017d8;\nr_ble_phy_calculate_rxtx_ifs = 0x400017dc;\nr_ble_phy_calculate_rxwindow = 0x400017e0;\nr_ble_phy_calculate_txrx_ifs = 0x400017e4;\nr_ble_phy_check_bb_status = 0x400017e8;\nr_ble_phy_complete_rx_info = 0x400017ec;\nr_ble_phy_config_access_addr = 0x400017f0;\nr_ble_phy_data_make = 0x400017f4;\nr_ble_phy_disable = 0x400017f8;\nr_ble_phy_disable_irq = 0x400017fc;\nr_ble_phy_disable_whitening = 0x40001800;\nr_ble_phy_enable_whitening = 0x40001804;\nr_ble_phy_encrypt_disable = 0x40001808;\nr_ble_phy_env_init = 0x4000180c;\nr_ble_phy_get_current_phy = 0x40001810;\nr_ble_phy_get_packet_counter = 0x40001814;\nr_ble_phy_get_packet_status = 0x40001818;\nr_ble_phy_get_pyld_time_offset = 0x4000181c;\nr_ble_phy_get_rx_phy_mode = 0x40001820;\nr_ble_phy_get_seq_end_st = 0x40001824;\nr_ble_phy_init = 0x40001828;\nr_ble_phy_isr = 0x4000182c;\nr_ble_phy_max_data_pdu_pyld = 0x40001830;\nr_ble_phy_mode_config = 0x40001834;\nr_ble_phy_mode_convert = 0x40001838;\nr_ble_phy_mode_write = 0x4000183c;\nr_ble_phy_module_deinit = 0x40001840;\nr_ble_phy_module_init = 0x40001844;\nr_ble_phy_monitor_bb_sync = 0x40001848;\nr_ble_phy_reset_bb_monitor = 0x4000184c;\nr_ble_phy_resolv_list_disable = 0x40001850;\nr_ble_phy_resolv_list_enable = 0x40001854;\nr_ble_phy_restart_sequence = 0x40001858;\nr_ble_phy_rx_set_start_time_forcibly = 0x4000185c;\nr_ble_phy_rxpdu_copy = 0x40001860;\nr_ble_phy_seq_encrypt_enable = 0x40001864;\nr_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001868;\nr_ble_phy_sequence_end_isr = 0x4000186c;\nr_ble_phy_sequence_get_mode = 0x40001870;\nr_ble_phy_sequence_is_running = 0x40001874;\nr_ble_phy_sequence_is_waiting_rsp = 0x40001878;\nr_ble_phy_sequence_single_end = 0x4000187c;\nr_ble_phy_sequence_tx_end_invoke = 0x40001880;\nr_ble_phy_sequence_update_conn_ind_params = 0x40001884;\nr_ble_phy_set_adv_mode = 0x40001888;\nr_ble_phy_set_coex_pti = 0x4000188c;\nr_ble_phy_set_conn_ind_pdu = 0x40001890;\nr_ble_phy_set_conn_mode = 0x40001894;\nr_ble_phy_set_dev_address = 0x40001898;\nr_ble_phy_set_rx_pwr_compensation = 0x4000189c;\nr_ble_phy_set_rxhdr = 0x400018a0;\nr_ble_phy_set_scan_mode = 0x400018a4;\nr_ble_phy_set_sequence_mode = 0x400018a8;\nr_ble_phy_set_single_packet_rx_sequence = 0x400018ac;\nr_ble_phy_set_single_packet_tx_sequence = 0x400018b0;\nr_ble_phy_set_tx_rx_transition = 0x400018b4;\nr_ble_phy_set_txend_cb = 0x400018b8;\nr_ble_phy_setchan = 0x400018bc;\nr_ble_phy_start_rx_immediately = 0x400018c0;\nr_ble_phy_state_get = 0x400018c4;\nr_ble_phy_timer_config_start_time = 0x400018c8;\nr_ble_phy_timer_start_now = 0x400018cc;\nr_ble_phy_timer_stop = 0x400018d0;\nr_ble_phy_tx_set_start_time = 0x400018d4;\nr_ble_phy_txpower_round = 0x400018d8;\nr_ble_phy_txpwr_set = 0x400018dc;\nr_ble_phy_update_conn_sequence = 0x400018e0;\nr_ble_phy_update_encryption = 0x400018e4;\nr_ble_phy_update_ifs = 0x400018e8;\nr_ble_phy_xcvr_state_get = 0x400018ec;\nr_ble_plf_set_log_level = 0x400018f0;\nr_ble_rtc_wake_up_cpu_init = 0x400018f4;\nr_ble_rtc_wake_up_state_clr = 0x400018f8;\nr_ble_vendor_hci_register = 0x400018fc;\nr_bt_rf_coex_cfg_set = 0x40001900;\nr_bt_rf_coex_coded_txrx_time_upper_lim = 0x40001904;\nr_bt_rf_coex_dft_pti_set = 0x40001908;\nr_bt_rf_coex_hook_deinit = 0x4000190c;\nr_bt_rf_coex_hook_init = 0x40001910;\nr_bt_rf_coex_hook_st_set = 0x40001914;\nr_bt_rf_coex_hooks_p_set_default = 0x40001918;\nr_btdm_disable_adv_delay = 0x4000191c;\nr_btdm_switch_phy_coded = 0x40001920;\nr_esp_wait_disabled = 0x40001924;\nr_get_be16 = 0x40001928;\nr_get_be24 = 0x4000192c;\nr_get_be32 = 0x40001930;\nr_get_be64 = 0x40001934;\nr_get_le16 = 0x40001938;\nr_get_le24 = 0x4000193c;\nr_get_le32 = 0x40001940;\nr_get_le64 = 0x40001944;\nr_get_local_irk_offset = 0x40001948;\nr_get_local_rpa_offset = 0x4000194c;\nr_get_max_skip = 0x40001950;\nr_get_peer_id_offset = 0x40001954;\nr_get_peer_irk_offset = 0x40001958;\nr_get_peer_rpa_offset = 0x4000195c;\nr_hal_rtc_intr_init = 0x40001960;\nr_hal_rtc_irq_handler = 0x40001964;\nr_hal_timer_deinit = 0x40001968;\nr_hal_timer_disable_irq = 0x4000196c;\nr_hal_timer_env_init = 0x40001970;\nr_hal_timer_init = 0x40001974;\nr_hal_timer_process = 0x40001978;\nr_hal_timer_read = 0x4000197c;\nr_hal_timer_read_tick = 0x40001980;\nr_hal_timer_set_cb = 0x40001984;\nr_hal_timer_set_exp_tick = 0x40001988;\nr_hal_timer_start = 0x4000198c;\nr_hal_timer_start_at = 0x40001990;\nr_hal_timer_stop = 0x40001994;\nr_hal_timer_task_start = 0x40001998;\nr_ll_assert = 0x4000199c;\nr_mem_init_mbuf_pool = 0x400019a0;\nr_mem_malloc_mbuf_pool = 0x400019a4;\nr_mem_malloc_mbufpkt_pool = 0x400019a8;\nr_mem_malloc_mempool = 0x400019ac;\nr_mem_malloc_mempool_ext = 0x400019b0;\nr_mem_malloc_mempool_gen = 0x400019b4;\nr_mem_pullup_obj = 0x400019b8;\nr_mem_split_frag = 0x400019bc;\nr_os_cputime_get32 = 0x400019c0;\nr_os_cputime_ticks_to_usecs = 0x400019c4;\nr_os_cputime_timer_init = 0x400019c8;\nr_os_cputime_timer_relative = 0x400019cc;\nr_os_cputime_timer_start = 0x400019d0;\nr_os_cputime_timer_stop = 0x400019d4;\nr_os_cputime_usecs_to_ticks = 0x400019d8;\nr_os_mbuf_adj = 0x400019dc;\nr_os_mbuf_append = 0x400019e0;\nr_os_mbuf_appendfrom = 0x400019e4;\nr_os_mbuf_cmpf = 0x400019e8;\nr_os_mbuf_cmpm = 0x400019ec;\nr_os_mbuf_concat = 0x400019f0;\nr_os_mbuf_copydata = 0x400019f4;\nr_os_mbuf_copyinto = 0x400019f8;\nr_os_mbuf_dup = 0x400019fc;\nr_os_mbuf_extend = 0x40001a00;\nr_os_mbuf_free = 0x40001a04;\nr_os_mbuf_free_chain = 0x40001a08;\nr_os_mbuf_get = 0x40001a0c;\nr_os_mbuf_get_pkthdr = 0x40001a10;\nr_os_mbuf_leadingspace = 0x40001a14;\nr_os_mbuf_len = 0x40001a18;\nr_os_mbuf_off = 0x40001a1c;\nr_os_mbuf_pack_chains = 0x40001a20;\nr_os_mbuf_pool_init = 0x40001a24;\nr_os_mbuf_prepend = 0x40001a28;\nr_os_mbuf_prepend_pullup = 0x40001a2c;\nr_os_mbuf_pullup = 0x40001a30;\nr_os_mbuf_trailingspace = 0x40001a34;\nr_os_mbuf_trim_front = 0x40001a38;\nr_os_mbuf_widen = 0x40001a3c;\nr_os_memblock_from = 0x40001a40;\nr_os_memblock_get = 0x40001a44;\nr_os_memblock_put = 0x40001a48;\nr_os_memblock_put_from_cb = 0x40001a4c;\nr_os_mempool_clear = 0x40001a50;\nr_os_mempool_ext_clear = 0x40001a54;\nr_os_mempool_ext_init = 0x40001a58;\nr_os_mempool_info_get_next = 0x40001a5c;\nr_os_mempool_init = 0x40001a60;\nr_os_mempool_init_internal = 0x40001a64;\nr_os_mempool_is_sane = 0x40001a68;\nr_os_mempool_module_init = 0x40001a6c;\nr_os_mempool_unregister = 0x40001a70;\nr_os_mqueue_get = 0x40001a74;\nr_os_mqueue_init = 0x40001a78;\nr_os_mqueue_put = 0x40001a7c;\nr_os_msys_count = 0x40001a80;\nr_os_msys_get = 0x40001a84;\nr_os_msys_get_pkthdr = 0x40001a88;\nr_os_msys_num_free = 0x40001a8c;\nr_os_msys_register = 0x40001a90;\nr_os_msys_reset = 0x40001a94;\nr_pri_phy_valid = 0x40001a98;\nr_put_be16 = 0x40001a9c;\nr_put_be24 = 0x40001aa0;\nr_put_be32 = 0x40001aa4;\nr_put_be64 = 0x40001aa8;\nr_put_le16 = 0x40001aac;\nr_put_le24 = 0x40001ab0;\nr_put_le32 = 0x40001ab4;\nr_put_le64 = 0x40001ab8;\nr_rtc0_timer_handler = 0x40001abc;\nr_sdkconfig_get_opts = 0x40001ac0;\nr_sdkconfig_set_opts = 0x40001ac4;\nr_sec_phy_valid = 0x40001ac8;\nr_swap_buf = 0x40001acc;\nr_swap_in_place = 0x40001ad0;\n\/* Data (.data, .bss, .rodata) *\/\nble_lll_dtm_module_env_p = 0x3fcdffc4;\ng_ble_lll_dtm_prbs15_data = 0x3ff4fee4;\ng_ble_lll_dtm_prbs9_data = 0x3ff4fde4;\ng_channel_rf_to_index = 0x3ff4fdbc;\ng_ble_lll_rfmgmt_data = 0x3fcdff7c;\ng_ble_sleep_enter_cb = 0x3fcdff78;\ng_ble_sleep_exit_cb = 0x3fcdff74;\nble_lll_sched_env_p = 0x3fcdff70;\nble_ll_env_p = 0x3fcdff6c;\ng_ble_ll_pdu_header_tx_time_ro = 0x3ff4fdb4;\nble_ll_adv_env_p = 0x3fcdff68;\nble_ll_conn_env_p = 0x3fcdff64;\nble_ll_conn_required_phy_mask = 0x3ff4fdb0;\nble_ll_valid_conn_phy_mask = 0x3ff4fdaf;\ng_ble_ll_ctrl_pkt_lengths_ro = 0x3ff4fd8c;\nble_ll_hci_env_p = 0x3fcdff60;\ng_debug_le_private_key = 0x3ff4fd6c;\ng_ecc_key = 0x3fcdfefc;\nble_ll_rand_env_p = 0x3fcdfef8;\nble_ll_resolv_env_p = 0x3fcdfef4;\ng_ble_ll_resolve_hdr = 0x3fcdfeec;\ng_device_mode_default = 0x3fcdfe68;\nble_ll_scan_classify_filter_aux_check_cb = 0x3fcdfee8;\nble_ll_scan_classify_filter_check_cb = 0x3fcdfee4;\nble_ll_scan_env_p = 0x3fcdfee0;\ng_ble_ll_supp_cmds_ro = 0x3ff4fd3c;\nble_ll_sync_env_p = 0x3fcdfedc;\ng_ble_sca_ppm_tbl_ro = 0x3ff4fd2c;\npriv_config_opts = 0x3fcdfe48;\nble_hci_uart_reset_cmd = 0x3ff4fd28;\nble_hci_trans_env_p = 0x3fcdfed8;\nble_hci_trans_mode = 0x3fcdfe44;\nble_hci_trans_funcs_ptr = 0x3fcdfed4;\nr_ble_lll_stub_funcs_ptr = 0x3fcdfed0;\nr_ble_stub_funcs_ptr = 0x3fcdfecc;\nr_ext_funcs_p = 0x3fcdfec8;\nr_npl_funcs = 0x3fcdfec4;\nble_hw_env_p = 0x3fcdfec0;\nble_phy_module_env_p = 0x3fcdfebc;\ng_ble_phy_chan_freq_ro = 0x3ff4fd00;\ng_ble_phy_mode_pkt_start_off_ro = 0x3ff4fcf8;\ng_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fce8;\ng_ble_phy_t_rxaddrdelay_ro = 0x3ff4fce4;\ng_ble_phy_t_rxenddelay_ro = 0x3ff4fce0;\ng_ble_phy_t_txdelay_ro = 0x3ff4fcdc;\ng_ble_phy_t_txenddelay_ro = 0x3ff4fcd8;\ng_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcc8;\nhal_timer_env_p = 0x3fcdfeb8;\nr_osi_coex_funcs_p = 0x3fcdfeb4;\nbt_rf_coex_hooks = 0x3fcdfeac;\nbt_rf_coex_hooks_p = 0x3fcdfea8;\ncoex_hook_st_group_tab = 0x3ff4fcbc;\ncoex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcb8;\ns_ble_act_count_by_group = 0x3fcdfea4;\ns_ble_coex_st_map = 0x3fcdfe90;\nbt_rf_coex_cfg_cb = 0x3fcdfe74;\nbt_rf_coex_cfg_p = 0x3fcdfe70;\nbt_rf_coex_cfg_rom = 0x3ff4fc9c;\nbt_rf_coex_pti_dft_p = 0x3fcdfe6c;\nbt_rf_coex_pti_dft_rom = 0x3fcdfe04;\nconn_dynamic_pti_param_rom = 0x3ff4fc84;\nconn_phy_coded_max_data_time_param_rom = 0x3ff4fc80;\next_adv_dynamic_pti_param_rom = 0x3ff4fc4c;\next_scan_dynamic_param_rom = 0x3ff4fc14;\nlegacy_adv_dynamic_pti_param_rom = 0x3ff4fbf4;\nper_adv_dynamic_pti_param_rom = 0x3ff4fbd8;\nsync_dynamic_param_rom = 0x3ff4fbc0;\ng_ble_plf_log_level = 0x3fcdfe00;\ng_msys_pool_list = 0x3fcdfdf8;\ng_os_mempool_list = 0x3fcdfdf0;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x40001ad4;\nRC_GetBlockAckTime = 0x40001ad8;\nebuf_list_remove = 0x40001adc;\nesf_buf_alloc = 0x40001ae0;\nesf_buf_alloc_dynamic = 0x40001ae4;\nesf_buf_recycle = 0x40001ae8;\nGetAccess = 0x40001aec;\nhal_mac_is_low_rate_enabled = 0x40001af0;\nhal_mac_tx_get_blockack = 0x40001af4;\nhal_mac_tx_set_ppdu = 0x40001af8;\nic_get_trc = 0x40001afc;\nic_mac_deinit = 0x40001b00;\nic_mac_init = 0x40001b04;\nic_interface_enabled = 0x40001b08;\nis_lmac_idle = 0x40001b0c;\nlmacAdjustTimestamp = 0x40001b10;\nlmacDiscardAgedMSDU = 0x40001b14;\nlmacDiscardMSDU = 0x40001b18;\nlmacEndFrameExchangeSequence = 0x40001b1c;\nlmacIsIdle = 0x40001b20;\nlmacIsLongFrame = 0x40001b24;\nlmacMSDUAged = 0x40001b28;\nlmacPostTxComplete = 0x40001b2c;\nlmacProcessAllTxTimeout = 0x40001b30;\nlmacProcessCollisions = 0x40001b34;\nlmacProcessRxSucData = 0x40001b38;\nlmacReachLongLimit = 0x40001b3c;\nlmacReachShortLimit = 0x40001b40;\nlmacRecycleMPDU = 0x40001b44;\nlmacRxDone = 0x40001b48;\nlmacSetTxFrame = 0x40001b4c;\nlmacTxDone = 0x40001b50;\nlmacTxFrame = 0x40001b54;\nmac_tx_set_duration = 0x40001b58;\nmac_tx_set_htsig = 0x40001b5c;\nmac_tx_set_plcp0 = 0x40001b60;\nmac_tx_set_plcp1 = 0x40001b64;\nmac_tx_set_plcp2 = 0x40001b68;\npm_check_state = 0x40001b6c;\npm_disable_dream_timer = 0x40001b70;\npm_disable_sleep_delay_timer = 0x40001b74;\npm_dream = 0x40001b78;\npm_mac_wakeup = 0x40001b7c;\npm_mac_sleep = 0x40001b80;\npm_enable_active_timer = 0x40001b84;\npm_enable_sleep_delay_timer = 0x40001b88;\npm_local_tsf_process = 0x40001b8c;\npm_set_beacon_filter = 0x40001b90;\npm_is_in_wifi_slice_threshold = 0x40001b94;\npm_is_waked = 0x40001b98;\npm_keep_alive = 0x40001b9c;\npm_on_beacon_rx = 0x40001ba0;\npm_on_data_rx = 0x40001ba4;\npm_on_tbtt = 0x40001ba8;\npm_parse_beacon = 0x40001bac;\npm_process_tim = 0x40001bb0;\npm_rx_beacon_process = 0x40001bb4;\npm_rx_data_process = 0x40001bb8;\npm_sleep = 0x40001bbc;\npm_sleep_for = 0x40001bc0;\npm_tbtt_process = 0x40001bc4;\nppAMPDU2Normal = 0x40001bc8;\nppAssembleAMPDU = 0x40001bcc;\nppCalFrameTimes = 0x40001bd0;\nppCalSubFrameLength = 0x40001bd4;\nppCalTxAMPDULength = 0x40001bd8;\nppCheckTxAMPDUlength = 0x40001bdc;\nppDequeueRxq_Locked = 0x40001be0;\nppDequeueTxQ = 0x40001be4;\nppEmptyDelimiterLength = 0x40001be8;\nppEnqueueRxq = 0x40001bec;\nppEnqueueTxDone = 0x40001bf0;\nppGetTxQFirstAvail_Locked = 0x40001bf4;\nppGetTxframe = 0x40001bf8;\nppMapTxQueue = 0x40001bfc;\nppProcTxSecFrame = 0x40001c00;\nppProcessRxPktHdr = 0x40001c04;\nppProcessTxQ = 0x40001c08;\nppRecordBarRRC = 0x40001c0c;\nlmacRequestTxopQueue = 0x40001c10;\nlmacReleaseTxopQueue = 0x40001c14;\nppRecycleAmpdu = 0x40001c18;\nppRecycleRxPkt = 0x40001c1c;\nppResortTxAMPDU = 0x40001c20;\nppResumeTxAMPDU = 0x40001c24;\nppRxFragmentProc = 0x40001c28;\nppRxPkt = 0x40001c2c;\nppRxProtoProc = 0x40001c30;\nppSearchTxQueue = 0x40001c34;\nppSearchTxframe = 0x40001c38;\nppSelectNextQueue = 0x40001c3c;\nppSubFromAMPDU = 0x40001c40;\nppTask = 0x40001c44;\nppTxPkt = 0x40001c48;\nppTxProtoProc = 0x40001c4c;\nppTxqUpdateBitmap = 0x40001c50;\npp_coex_tx_request = 0x40001c54;\npp_hdrsize = 0x40001c58;\npp_post = 0x40001c5c;\npp_process_hmac_waiting_txq = 0x40001c60;\nrcGetAmpduSched = 0x40001c64;\nrcUpdateRxDone = 0x40001c68;\nrc_get_trc = 0x40001c6c;\nrc_get_trc_by_index = 0x40001c70;\nrcAmpduLowerRate = 0x40001c74;\nrcampduuprate = 0x40001c78;\nrcClearCurAMPDUSched = 0x40001c7c;\nrcClearCurSched = 0x40001c80;\nrcClearCurStat = 0x40001c84;\nrcGetSched = 0x40001c88;\nrcLowerSched = 0x40001c8c;\nrcSetTxAmpduLimit = 0x40001c90;\nrcTxUpdatePer = 0x40001c94;\nrcUpdateAckSnr = 0x40001c98;\nrcUpdateRate = 0x40001c9c;\nrcUpdateTxDone = 0x40001ca0;\nrcUpdateTxDoneAmpdu2 = 0x40001ca4;\nrcUpSched = 0x40001ca8;\nrssi_margin = 0x40001cac;\nrx11NRate2AMPDULimit = 0x40001cb0;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001cb4;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001cb8;\ntrc_calc_duration = 0x40001cbc;\ntrc_isTxAmpduOperational = 0x40001cc0;\ntrc_onAmpduOp = 0x40001cc4;\nTRC_PER_IS_GOOD = 0x40001cc8;\ntrc_SetTxAmpduState = 0x40001ccc;\ntrc_tid_isTxAmpduOperational = 0x40001cd0;\ntrcAmpduSetState = 0x40001cd4;\nwDevCheckBlockError = 0x40001cd8;\nwDev_AppendRxBlocks = 0x40001cdc;\nwDev_DiscardFrame = 0x40001ce0;\nwDev_GetNoiseFloor = 0x40001ce4;\nwDev_IndicateAmpdu = 0x40001ce8;\nwDev_IndicateFrame = 0x40001cec;\nwdev_mac_reg_load = 0x40001cf0;\nwdev_mac_reg_store = 0x40001cf4;\nwdev_mac_special_reg_load = 0x40001cf8;\nwdev_mac_special_reg_store = 0x40001cfc;\nwdev_mac_wakeup = 0x40001d00;\nwdev_mac_sleep = 0x40001d04;\nwDev_ProcessFiq = 0x40001d08;\nwDev_ProcessRxSucData = 0x40001d0c;\nwdevProcessRxSucDataAll = 0x40001d10;\nwdev_csi_len_align = 0x40001d14;\nppDequeueTxDone_Locked = 0x40001d18;\nppProcTxDone = 0x40001d1c;\npm_tx_data_done_process = 0x40001d20;\nconfig_is_cache_tx_buf_enabled = 0x40001d24;\nppMapWaitTxq = 0x40001d28;\nppProcessWaitingQueue = 0x40001d2c;\nppDisableQueue = 0x40001d30;\npm_allow_tx = 0x40001d34;\nwdev_is_data_in_rxlist = 0x40001d38;\nppProcTxCallback = 0x40001d3c;\npm_is_open = 0x40001d40;\npm_wake_up = 0x40001d44;\npm_wake_done = 0x40001d48;\npm_disable_disconnected_sleep_delay_timer = 0x40001d4c;\npm_enable_disconnected_sleep_delay_timer = 0x40001d50;\nhal_mac_get_txq_state = 0x40001d54;\nhal_mac_clr_txq_state = 0x40001d58;\nhal_mac_tx_set_cca = 0x40001d5c;\nhal_mac_set_txq_invalid = 0x40001d60;\nhal_mac_txq_disable = 0x40001d64;\nhal_mac_is_txq_enabled = 0x40001d68;\nhal_mac_get_txq_pmd = 0x40001d6c;\nlmacDiscardFrameExchangeSequence = 0x40001d70;\nlmacDisableTransmit = 0x40001d74;\nlmacProcessTxTimeout = 0x40001d78;\nlmacProcessTxSuccess = 0x40001d7c;\nlmacProcessCollision = 0x40001d80;\nlmacProcessTxRtsError = 0x40001d84;\nlmacProcessCtsTimeout = 0x40001d88;\nlmacProcessTxComplete = 0x40001d8c;\nlmacProcessAckTimeout = 0x40001d90;\nlmacProcessTxError = 0x40001d94;\nlmacProcessTxseckiderr = 0x40001d98;\nrcReachRetryLimit = 0x40001d9c;\nlmacProcessShortRetryFail = 0x40001da0;\nlmacEndRetryAMPDUFail = 0x40001da4;\nppFillAMPDUBar = 0x40001da8;\nrcGetRate = 0x40001dac;\nppReSendBar = 0x40001db0;\nlmacProcessLongRetryFail = 0x40001db4;\nlmacRetryTxFrame = 0x40001db8;\nlmacProcessCollisions_task = 0x40001dbc;\nlmacProcessTxopQComplete = 0x40001dc0;\nlmacInitAc = 0x40001dc4;\nlmacInit = 0x40001dc8;\nmac_tx_set_txop_q = 0x40001dcc;\nhal_init = 0x40001dd0;\nhal_mac_rx_set_policy = 0x40001dd4;\nhal_mac_set_bssid = 0x40001dd8;\nmac_rx_policy_init = 0x40001ddc;\nmac_txrx_init = 0x40001de0;\nmac_rxbuf_init = 0x40001de4;\nmac_last_rxbuf_init = 0x40001de8;\nhal_attenna_init = 0x40001dec;\nhal_timer_update_by_rtc = 0x40001df0;\nhal_coex_pti_init = 0x40001df4;\nlmac_stop_hw_txq = 0x40001df8;\nppDirectRecycleAmpdu = 0x40001dfc;\nesp_wifi_internal_set_rts = 0x40001e00;\nesp_wifi_internal_get_rts = 0x40001e04;\nppTxFragmentProc = 0x40001e08;\nesf_buf_setup = 0x40001e0c;\nhal_agreement_add_rx_ba = 0x40001e10;\nhal_agreement_del_rx_ba = 0x40001e14;\nhal_crypto_set_key_entry = 0x40001e18;\nhal_crypto_get_key_entry = 0x40001e1c;\nhal_crypto_clr_key_entry = 0x40001e20;\nconfig_get_wifi_task_stack_size = 0x40001e24;\npp_create_task = 0x40001e28;\nhal_set_sta_tsf_wakeup = 0x40001e2c;\nhal_set_rx_beacon_pti = 0x40001e30;\npm_start = 0x40001e34;\npm_stop = 0x40001e38;\nhal_disable_sta_tbtt = 0x40001e3c;\nppCalTxopDur = 0x40001e40;\nwDev_IndicateCtrlFrame = 0x40001e44;\nhal_enable_sta_tbtt = 0x40001e48;\nhal_set_sta_tbtt = 0x40001e4c;\npm_update_next_tbtt = 0x40001e50;\npm_set_sleep_type = 0x40001e54;\nwDev_Rxbuf_Init = 0x40001e58;\nwDev_Rxbuf_Deinit = 0x40001e5c;\nppCalTkipMic = 0x40001e60;\nwDev_SnifferRxData = 0x40001e64;\nhal_crypto_enable = 0x40001e68;\nhal_crypto_disable = 0x40001e6c;\nwDev_Insert_KeyEntry = 0x40001e70;\nwDev_remove_KeyEntry = 0x40001e74;\nrc_enable_trc = 0x40001e78;\nrc_set_per_conn_fix_rate = 0x40001e7c;\nwdev_csi_rx_process = 0x40001e80;\nwDev_SnifferRxAmpdu = 0x40001e84;\nhal_mac_tsf_reset = 0x40001e88;\ndbg_lmac_statis_dump = 0x40001e8c;\ndbg_lmac_rxtx_statis_dump = 0x40001e90;\ndbg_lmac_hw_statis_dump = 0x40001e94;\ndbg_lmac_diag_statis_dump = 0x40001e98;\ndbg_lmac_ps_statis_dump = 0x40001e9c;\npp_timer_do_process = 0x40001ea0;\nrcUpdateAMPDUParam = 0x40001ea4;\nrcUpdatePhyMode = 0x40001ea8;\nrcGetHighestRateIdx = 0x40001eac;\npm_tx_null_data_done_process = 0x40001eb0;\npm_tx_data_process = 0x40001eb4;\npm_attach = 0x40001eb8;\npm_coex_schm_process = 0x40001ebc;\nppInitTxq = 0x40001ec0;\npp_attach = 0x40001ec4;\npp_deattach = 0x40001ec8;\npm_on_probe_resp_rx = 0x40001ecc;\nhal_set_sta_tsf = 0x40001ed0;\nic_update_sta_tsf = 0x40001ed4;\nic_tx_pkt = 0x40001ed8;\npm_send_probe_stop = 0x40001edc;\npm_send_probe_start = 0x40001ee0;\npm_on_coex_schm_process_restart = 0x40001ee4;\nhal_mac_set_rxq_policy = 0x40001ee8;\nhal_sniffer_enable = 0x40001eec;\nhal_sniffer_disable = 0x40001ef0;\nhal_sniffer_rx_set_promis = 0x40001ef4;\nhal_sniffer_rx_clr_statistics = 0x40001ef8;\nhal_sniffer_set_promis_misc_pkt = 0x40001efc;\ntsf_hal_set_tsf_enable = 0x40001f00;\ntsf_hal_set_tsf_disable = 0x40001f04;\ntsf_hal_is_tsf_enabled = 0x40001f08;\ntsf_hal_set_modem_wakeup_early_time = 0x40001f0c;\ntsf_hal_get_counter_value = 0x40001f10;\ntsf_hal_set_counter_value = 0x40001f14;\ntsf_hal_get_time = 0x40001f18;\ntsf_hal_set_time = 0x40001f1c;\ntsf_hal_set_tbtt_enable = 0x40001f20;\ntsf_hal_set_tbtt_disable = 0x40001f24;\ntsf_hal_set_tbtt_intr_enable = 0x40001f28;\ntsf_hal_set_tbtt_intr_disable = 0x40001f2c;\ntsf_hal_set_tbtt_soc_wakeup_enable = 0x40001f30;\ntsf_hal_set_tbtt_soc_wakeup_disable = 0x40001f34;\ntsf_hal_set_tbtt_start_time = 0x40001f38;\ntsf_hal_set_tbtt_early_time = 0x40001f3c;\ntsf_hal_set_tbtt_interval = 0x40001f40;\ntsf_hal_get_tbtt_interval = 0x40001f44;\ntsf_hal_set_timer_enable = 0x40001f48;\ntsf_hal_set_timer_disable = 0x40001f4c;\ntsf_hal_set_timer_target = 0x40001f50;\ntsf_hal_get_timer_target = 0x40001f54;\ntsf_hal_set_timer_intr_enable = 0x40001f58;\ntsf_hal_set_timer_intr_disable = 0x40001f5c;\ntsf_hal_set_timer_soc_wakeup_enable = 0x40001f60;\ntsf_hal_set_timer_soc_wakeup_disable = 0x40001f64;\npm_disconnected_wake = 0x40001f68;\npm_get_connectionless_status = 0x40001f6c;\npm_update_by_connectionless_status = 0x40001f70;\npm_connectionless_wake_interval_timeout_process = 0x40001f74;\npm_connectionless_wake_window_timeout_process = 0x40001f78;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff4fbbc;\npTxRx = 0x3fcdfdec;\nlmacConfMib_ptr = 0x3fcdfde8;\nour_wait_eb = 0x3fcdfde4;\nour_tx_eb = 0x3fcdfde0;\npp_wdev_funcs = 0x3fcdfddc;\ng_osi_funcs_p = 0x3fcdfdd8;\nwDevCtrl_ptr = 0x3fcdfdd4;\ng_wdev_last_desc_reset_ptr = 0x3ff4fbb8;\nwDevMacSleep_ptr = 0x3fcdfdd0;\ng_lmac_cnt_ptr = 0x3fcdfdcc;\nour_controls_ptr = 0x3ff4fbb4;\npp_sig_cnt_ptr = 0x3fcdfdc8;\ng_eb_list_desc_ptr = 0x3fcdfdc4;\ns_fragment_ptr = 0x3fcdfdc0;\nif_ctrl_ptr = 0x3fcdfdbc;\ng_intr_lock_mux = 0x3fcdfdb8;\ng_wifi_global_lock = 0x3fcdfdb4;\ns_wifi_queue = 0x3fcdfdb0;\npp_task_hdl = 0x3fcdfdac;\ns_pp_task_create_sem = 0x3fcdfda8;\ns_pp_task_del_sem = 0x3fcdfda4;\ng_wifi_menuconfig_ptr = 0x3fcdfda0;\nxphyQueue = 0x3fcdfd9c;\nap_no_lr_ptr = 0x3fcdfd98;\nrc11BSchedTbl_ptr = 0x3fcdfd94;\nrc11NSchedTbl_ptr = 0x3fcdfd90;\nrcLoRaSchedTbl_ptr = 0x3fcdfd8c;\nBasicOFDMSched_ptr = 0x3fcdfd88;\ntrc_ctl_ptr = 0x3fcdfd84;\ng_pm_cnt_ptr = 0x3fcdfd80;\ng_pm_ptr = 0x3fcdfd7c;\ng_pm_cfg_ptr = 0x3fcdfd78;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdfd74;\ng_txop_queue_status_ptr = 0x3fcdfd70;\ng_mac_sleep_en_ptr = 0x3fcdfd6c;\ng_mesh_is_root_ptr = 0x3fcdfd68;\ng_mesh_topology_ptr = 0x3fcdfd64;\ng_mesh_init_ps_type_ptr = 0x3fcdfd60;\ng_mesh_is_started_ptr = 0x3fcdfd5c;\ng_config_func = 0x3fcdfd58;\ng_net80211_tx_func = 0x3fcdfd54;\ng_timer_func = 0x3fcdfd50;\ns_michael_mic_failure_cb = 0x3fcdfd4c;\nwifi_sta_rx_probe_req = 0x3fcdfd48;\ng_tx_done_cb_func = 0x3fcdfd44;\ng_per_conn_trc = 0x3fcdfd28;\ns_encap_amsdu_func = 0x3fcdfd24;\nbars = 0x3fcdfc84;\neb_txdesc_space = 0x3fcdfbf4;\neb_space = 0x3fcdfb54;\ng_pd_mac_in_light_sleep = 0x3fcdfb50;\ns_fix_rate_mask = 0x3fcdfb4c;\ns_fix_rate = 0x3fcdfb44;\ng_wdev_csi_rx = 0x3fcdfb40;\ng_wdev_csi_rx_ctx = 0x3fcdfb3c;\nBcnSendTick = 0x3fcdfb38;\ng_pp_timer_info_ptr = 0x3fcdfb34;\nrcP2P11NSchedTbl_ptr = 0x3fcdfb30;\nrcP2P11GSchedTbl_ptr = 0x3fcdfb2c;\nrc11GSchedTbl_ptr = 0x3fcdfb28;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001f7c;\nampdu_dispatch = 0x40001f80;\nampdu_dispatch_all = 0x40001f84;\nampdu_dispatch_as_many_as_possible = 0x40001f88;\nampdu_dispatch_movement = 0x40001f8c;\nampdu_dispatch_upto = 0x40001f90;\nchm_is_at_home_channel = 0x40001f94;\ncnx_node_is_existing = 0x40001f98;\ncnx_node_search = 0x40001f9c;\nic_ebuf_recycle_rx = 0x40001fa0;\nic_ebuf_recycle_tx = 0x40001fa4;\nic_reset_rx_ba = 0x40001fa8;\nieee80211_align_eb = 0x40001fac;\nieee80211_ampdu_reorder = 0x40001fb0;\nieee80211_ampdu_start_age_timer = 0x40001fb4;\nieee80211_encap_esfbuf = 0x40001fb8;\nieee80211_is_tx_allowed = 0x40001fbc;\nieee80211_output_pending_eb = 0x40001fc0;\nieee80211_output_process = 0x40001fc4;\nieee80211_set_tx_desc = 0x40001fc8;\nsta_input = 0x40001fcc;\nwifi_get_macaddr = 0x40001fd0;\nwifi_rf_phy_disable = 0x40001fd4;\nwifi_rf_phy_enable = 0x40001fd8;\nic_ebuf_alloc = 0x40001fdc;\nieee80211_classify = 0x40001fe0;\nieee80211_copy_eb_header = 0x40001fe4;\nieee80211_recycle_cache_eb = 0x40001fe8;\nieee80211_search_node = 0x40001fec;\nroundup2 = 0x40001ff0;\nieee80211_crypto_encap = 0x40001ff4;\nieee80211_crypto_decap = 0x40001ff8;\nieee80211_decap = 0x40001ffc;\nieee80211_set_tx_pti = 0x40002000;\nwifi_is_started = 0x40002004;\nieee80211_gettid = 0x40002008;\nieee80211_ccmp_decrypt = 0x4000200c;\nieee80211_ccmp_encrypt = 0x40002010;\nccmp_encap = 0x40002014;\nccmp_decap = 0x40002018;\ntkip_encap = 0x4000201c;\ntkip_decap = 0x40002020;\nwep_encap = 0x40002024;\nwep_decap = 0x40002028;\ndbg_hmac_rxtx_statis_dump = 0x4000202c;\ndbg_hmac_statis_dump = 0x40002030;\nieee80211_send_action_vendor_spec = 0x40002034;\nieee80211_deauth_construct = 0x40002040;\nieee80211_disassoc_construct = 0x40002044;\nieee80211_vnd_lora_ie_size = 0x40002048;\nieee80211_vnd_ie_size = 0x4000204c;\nieee80211_add_ssid = 0x40002050;\nieee80211_add_rates = 0x40002054;\nieee80211_add_xrates = 0x40002058;\nieee80211_is_ht_cipher = 0x4000205c;\nieee80211_assoc_resp_construct = 0x40002064;\nieee80211_setup_lr_rates = 0x40002068;\nieee80211_ht_node_init = 0x4000206c;\nieee80211_is_support_rate = 0x40002070;\nieee80211_setup_rates = 0x40002074;\nieee80211_is_lr_only = 0x40002078;\nieee80211_setup_phy_mode = 0x4000207c;\nieee80211_sta_is_connected = 0x40002080;\ncurrent_task_is_wifi_task = 0x40002084;\nwifi_get_init_state = 0x40002088;\nieee80211_timer_process = 0x4000208c;\ncnx_coexist_timeout = 0x40002090;\nsta_recv_mgmt = 0x40002094;\nieee80211_send_setup = 0x40002098;\nieee80211_send_probereq = 0x4000209c;\nsta_auth_shared = 0x400020a4;\nsta_auth_sae = 0x400020a8;\ncnx_coexist_timeout_process = 0x400020ac;\nieee80211_alloc_challenge = 0x400020b0;\ncnx_assoc_timeout = 0x400020b4;\nieee80211_vnd_ie_set = 0x400020b8;\nieee80211_vnd_lora_ie_set = 0x400020bc;\nieee80211_add_wme_param = 0x400020c0;\nieee80211_add_dsparams = 0x400020c4;\nieee80211_add_csa = 0x400020c8;\nieee80211_add_extcap = 0x400020cc;\nieee80211_regdomain_get_country = 0x400020d0;\nieee80211_add_countryie = 0x400020d4;\nieee80211_amsdu_adjust_head = 0x400020dc;\nieee80211_amsdu_adjust_last_length = 0x400020e0;\nieee80211_amsdu_send_check = 0x400020e4;\nieee80211_amsdu_encap_check = 0x400020e8;\nieee80211_amsdu_length_check = 0x400020ec;\nieee80211_encap_amsdu = 0x400020f0;\nieee80211_output_raw_process = 0x400020f4;\nesp_wifi_80211_tx = 0x400020f8;\nieee80211_raw_frame_sanity_check = 0x400020fc;\nieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;\nieee80211_crypto_aes_128_cmac_decrypt = 0x40002104;\nieee80211_alloc_tx_buf = 0x40002108;\nieee80211_output_do = 0x4000210c;\nieee80211_send_nulldata = 0x40002110;\nieee80211_setup_robust_mgmtframe = 0x40002114;\nieee80211_mgmt_output = 0x40002118;\nieee80211_encap_null_data = 0x4000211c;\nieee80211_send_deauth = 0x40002120;\nieee80211_alloc_deauth = 0x40002124;\nieee80211_send_proberesp = 0x40002128;\nieee80211_tx_mgt_cb = 0x4000212c;\nieee80211_getcapinfo = 0x40002130;\nsta_rx_csa = 0x40002134;\nsta_recv_sa_query_resp = 0x40002144;\nieee80211_set_max_rate = 0x4000214c;\nic_set_sta = 0x40002150;\nieee80211_parse_wpa = 0x40002158;\nieee80211_add_assoc_req_ies = 0x40002160;\nieee80211_add_probe_req_ies = 0x40002164;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdfb24;\ng_scan = 0x3fcdfb20;\ng_chm = 0x3fcdfb1c;\ng_ic_ptr = 0x3fcdfb18;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_tx_cacheq_ptr = 0x3fcdfb14;\ns_netstack_free = 0x3fcdfb10;\nmesh_rxcb = 0x3fcdfb0c;\nsta_rxcb = 0x3fcdfb08;\nccmp_ptr = 0x3fcdfb04;\ns_wifi_nvs_ptr = 0x3fcdfb00;\ntkip_ptr = 0x3fcdfafc;\nwep_ptr = 0x3fcdfaf8;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_misc_nvs = 0x3fcdfaf0;\ns_wifi_init_state = 0x3fcdfac0;\ns_wifi_task_hdl = 0x3fcdfaec;\nin_rssi_adjust = 0x3fcdfae8;\nrssi_saved = 0x3fcdfae0;\nrssi_index = 0x3fcdfadc;\ns_sa_query_retries = 0x3fcdfad8;\ns_sa_query_success = 0x3fcdfad5;\ng_sta_connected_flag = 0x3fcdfad4;\nwpa_crypto_funcs_ptr = 0x3fcdfad0;\ns_netstack_ref = 0x3fcdfacc;\nsta_csa_timer_ptr = 0x3fcdfac8;\ns_trans_id = 0x3fcdfac4;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x40002168;\ncoex_bt_release = 0x4000216c;\ncoex_bt_request = 0x40002170;\ncoex_core_ble_conn_dyn_prio_get = 0x40002174;\ncoex_core_event_duration_get = 0x40002178;\ncoex_core_pti_get = 0x4000217c;\ncoex_core_release = 0x40002180;\ncoex_core_request = 0x40002184;\ncoex_core_status_get = 0x40002188;\ncoex_core_timer_idx_get = 0x4000218c;\ncoex_event_duration_get = 0x40002190;\ncoex_hw_timer_disable = 0x40002194;\ncoex_hw_timer_enable = 0x40002198;\ncoex_hw_timer_set = 0x4000219c;\ncoex_schm_interval_set = 0x400021a0;\ncoex_schm_lock = 0x400021a4;\ncoex_schm_unlock = 0x400021a8;\ncoex_status_get = 0x400021ac;\ncoex_wifi_release = 0x400021b0;\nesp_coex_ble_conn_dynamic_prio_get = 0x400021b4;\ncoex_hw_timer_tick_get = 0x400021b8;\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdfabc;\ncoex_pti_tab_ptr = 0x3fcdfab8;\ncoex_schm_env_ptr = 0x3fcdfab4;\ncoexist_funcs = 0x3fcdfab0;\ng_coa_funcs_p = 0x3fcdfaac;\ng_coex_param_ptr = 0x3fcdfaa8;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_param_addr = 0x400021bc;\nphy_get_romfuncs = 0x400021c0;\nchip729_phyrom_version = 0x400021c4;\nchip729_phyrom_version_num = 0x400021c8;\nrom_get_rc_dout = 0x400021cc;\nrc_cal = 0x400021d0;\nphy_analog_delay_cal = 0x400021d4;\nphy_rx_rifs_en = 0x400021d8;\nphy_current_level_set = 0x400021dc;\nphy_bbpll_en_usb = 0x400021e0;\nphy_bt_power_track = 0x400021e4;\nphy_xpd_tsens = 0x400021e8;\nbb_wdt_rst_enable = 0x400021ec;\nbb_wdt_int_enable = 0x400021f0;\nbb_wdt_timeout_clear = 0x400021f4;\nbb_wdt_get_status = 0x400021f8;\nrom_enter_critical_phy = 0x400021fc;\nrom_exit_critical_phy = 0x40002200;\nrom_bb_bss_cbw40 = 0x40002204;\nrom_set_chan_reg = 0x40002208;\nabs_temp = 0x4000220c;\nset_chan_cal_interp = 0x40002210;\nloopback_mode_en = 0x40002214;\nget_data_sat = 0x40002218;\nphy_byte_to_word = 0x4000221c;\nphy_get_rx_freq = 0x40002220;\ni2c_master_reset = 0x40002224;\nchan14_mic_enable = 0x40002228;\nchan14_mic_cfg = 0x4000222c;\nset_adc_rand = 0x40002230;\nphy_set_most_tpw = 0x40002234;\nphy_get_most_tpw = 0x40002238;\nesp_tx_state_out = 0x4000223c;\nphy_get_adc_rand = 0x40002240;\nphy_internal_delay = 0x40002244;\nphy_ftm_comp = 0x40002248;\nphy_11p_set = 0x4000224c;\nphy_freq_mem_backup = 0x40002250;\nant_dft_cfg = 0x40002254;\nant_wifitx_cfg = 0x40002258;\nant_wifirx_cfg = 0x4000225c;\nant_bttx_cfg = 0x40002260;\nant_btrx_cfg = 0x40002264;\nphy_chan_dump_cfg = 0x40002268;\nphy_enable_low_rate = 0x4000226c;\nphy_disable_low_rate = 0x40002270;\nphy_dig_reg_backup = 0x40002274;\nphy_chan_filt_set = 0x40002278;\nphy_rx11blr_cfg = 0x4000227c;\nset_cca = 0x40002280;\nset_rx_sense = 0x40002284;\nrx_gain_force = 0x40002288;\nrom_phy_en_hw_set_freq = 0x4000228c;\nrom_phy_dis_hw_set_freq = 0x40002290;\nwr_rf_freq_mem = 0x40002294;\nfreq_i2c_write_set = 0x40002298;\nwrite_pll_cap_mem = 0x4000229c;\npll_dac_mem_update = 0x400022a0;\npll_cap_mem_update = 0x400022a4;\nget_rf_freq_cap = 0x400022a8;\nget_rf_freq_init = 0x400022ac;\nfreq_get_i2c_data = 0x400022b0;\nfreq_i2c_data_write = 0x400022b4;\nset_chan_freq_hw_init = 0x400022b8;\nset_chan_freq_sw_start = 0x400022bc;\nrom_get_i2c_read_mask = 0x400022c0;\nrom_get_i2c_mst0_mask = 0x400022c4;\nrom_get_i2c_hostid = 0x400022c8;\nrom_chip_i2c_readReg_org = 0x400022cc;\nrom_chip_i2c_readReg = 0x400022d0;\nrom_i2c_paral_set_mst0 = 0x400022d4;\nrom_i2c_paral_set_read = 0x400022d8;\nrom_i2c_paral_read = 0x400022dc;\nrom_i2c_paral_write = 0x400022e0;\nrom_i2c_paral_write_num = 0x400022e4;\nrom_i2c_paral_write_mask = 0x400022e8;\nrom_i2c_readReg = 0x400022ec;\nrom_chip_i2c_writeReg = 0x400022f0;\nrom_i2c_writeReg = 0x400022f4;\nrom_i2c_readReg_Mask = 0x400022f8;\nrom_i2c_writeReg_Mask = 0x400022fc;\nrom_set_txcap_reg = 0x40002300;\ni2c_sar2_init_code = 0x40002304;\nphy_i2c_init1 = 0x40002308;\nphy_i2c_init2 = 0x4000230c;\nphy_get_i2c_data = 0x40002310;\nbias_reg_set = 0x40002314;\ni2c_rc_cal_set = 0x40002318;\ni2c_bbpll_set = 0x4000231c;\nrom_phy_xpd_rf = 0x40002320;\nphy_wakeup_init_rom = 0x40002324;\nregister_chipv7_phy_init_param = 0x40002328;\nphy_reg_init = 0x4000232c;\nphy_close_rf_rom = 0x40002330;\nrom_pbus_force_mode = 0x40002334;\nrom_pbus_rd_addr = 0x40002338;\nrom_pbus_rd_shift = 0x4000233c;\nrom_pbus_force_test = 0x40002340;\nrom_pbus_rd = 0x40002344;\nrom_pbus_debugmode = 0x40002348;\nrom_pbus_workmode = 0x4000234c;\nrom_pbus_set_rxgain = 0x40002350;\nrom_pbus_xpd_rx_off = 0x40002354;\nrom_pbus_xpd_rx_on = 0x40002358;\nrom_pbus_xpd_tx_off = 0x4000235c;\nrom_pbus_xpd_tx_on = 0x40002360;\nrom_pbus_set_dco = 0x40002364;\nrom_set_loopback_gain = 0x40002368;\nrom_txcal_debuge_mode = 0x4000236c;\nrom_txcal_work_mode = 0x40002370;\nset_pbus_mem = 0x40002374;\nrom_pwdet_sar2_init = 0x40002378;\nrom_en_pwdet = 0x4000237c;\nrom_get_sar_sig_ref = 0x40002380;\nrom_pwdet_tone_start = 0x40002384;\nrom_get_tone_sar_dout = 0x40002388;\nrom_get_fm_sar_dout = 0x4000238c;\nrom_txtone_linear_pwr = 0x40002390;\nrom_get_power_db = 0x40002394;\nrom_meas_tone_pwr_db = 0x40002398;\nrom_pkdet_vol_start = 0x4000239c;\nrom_read_sar_dout = 0x400023a0;\nrom_read_sar2_code = 0x400023a4;\nrom_get_sar2_vol = 0x400023a8;\nrom_get_pll_vol = 0x400023ac;\nrom_tx_pwctrl_bg_init = 0x400023b0;\nrom_phy_pwdet_always_en = 0x400023b4;\nrom_phy_pwdet_onetime_en = 0x400023b8;\nlinear_to_db = 0x400023bc;\nrom_disable_agc = 0x400023c0;\nrom_enable_agc = 0x400023c4;\nrom_disable_wifi_agc = 0x400023c8;\nrom_enable_wifi_agc = 0x400023cc;\nrom_write_gain_mem = 0x400023d0;\nrom_bb_bss_cbw40_dig = 0x400023d4;\nrom_cbw2040_cfg = 0x400023d8;\nrom_mac_tx_chan_offset = 0x400023dc;\nrom_tx_paon_set = 0x400023e0;\nrom_i2cmst_reg_init = 0x400023e4;\nrom_bt_gain_offset = 0x400023e8;\nrom_fe_reg_init = 0x400023ec;\nrom_mac_enable_bb = 0x400023f0;\nrom_bb_wdg_cfg = 0x400023f4;\nrom_fe_txrx_reset = 0x400023f8;\nrom_set_rx_comp = 0x400023fc;\nrom_write_chan_freq = 0x40002400;\nrom_agc_reg_init = 0x40002404;\nrom_bb_reg_init = 0x40002408;\nrom_write_txrate_power_offset = 0x4000240c;\nrom_open_i2c_xpd = 0x40002410;\nrom_txiq_set_reg = 0x40002414;\nrom_rxiq_set_reg = 0x40002418;\nrom_phy_bbpll_cal = 0x4000241c;\nphy_disable_cca = 0x40002420;\nphy_enable_cca = 0x40002424;\nforce_txon = 0x40002428;\nset_txclk_en = 0x4000242c;\nset_rxclk_en = 0x40002430;\nstart_tx_tone_step = 0x40002434;\nstop_tx_tone = 0x40002438;\nbb_wdg_test_en = 0x4000243c;\nnoise_floor_auto_set = 0x40002440;\nread_hw_noisefloor = 0x40002444;\niq_corr_enable = 0x40002448;\nbt_tx_dig_gain = 0x4000244c;\nwifi_tx_dig_reg = 0x40002450;\nwifi_agc_sat_gain = 0x40002454;\nphy_ant_init = 0x40002458;\nphy_set_bbfreq_init = 0x4000245c;\nwifi_fbw_sel = 0x40002460;\nphy_rx_sense_set = 0x40002464;\ntx_state_set = 0x40002468;\nphy_close_pa = 0x4000246c;\nbt_filter_reg = 0x40002470;\nphy_freq_correct = 0x40002474;\nset_pbus_reg = 0x40002478;\nwifi_rifs_mode_en = 0x4000247c;\nrfagc_disable = 0x40002480;\nrom_restart_cal = 0x40002484;\nrom_write_rfpll_sdm = 0x40002488;\nrom_wait_rfpll_cal_end = 0x4000248c;\nrom_rfpll_set_freq = 0x40002490;\nrom_rfpll_cap_init_cal = 0x40002494;\nrom_set_rfpll_freq = 0x40002498;\nrom_write_pll_cap = 0x4000249c;\nrom_read_pll_cap = 0x400024a0;\nmhz2ieee = 0x400024a4;\nchan_to_freq = 0x400024a8;\nset_rf_freq_offset = 0x400024ac;\nset_channel_rfpll_freq = 0x400024b0;\nrfpll_cap_correct = 0x400024b4;\nphy_set_freq = 0x400024b8;\ncorrect_rfpll_offset = 0x400024bc;\npll_vol_cal = 0x400024c0;\nchip_v7_set_chan_misc = 0x400024c4;\nchip_v7_set_chan = 0x400024c8;\nchip_v7_set_chan_offset = 0x400024cc;\nchip_v7_set_chan_ana = 0x400024d0;\nset_chanfreq = 0x400024d4;\nrom_rxiq_cover_mg_mp = 0x400024d8;\nrom_rfcal_rxiq = 0x400024dc;\nrom_get_rfcal_rxiq_data = 0x400024e0;\nrom_pbus_rx_dco_cal = 0x400024e4;\nrom_rxdc_est_min = 0x400024e8;\nrom_pbus_rx_dco_cal_1step = 0x400024ec;\nrom_set_lb_txiq = 0x400024f0;\nrom_set_rx_gain_cal_iq = 0x400024f4;\nrom_set_rx_gain_cal_dc = 0x400024f8;\niq_est_enable = 0x400024fc;\niq_est_disable = 0x40002500;\ndc_iq_est = 0x40002504;\nset_cal_rxdc = 0x40002508;\nrxiq_get_mis = 0x4000250c;\nspur_reg_write_one_tone = 0x40002510;\nspur_cal = 0x40002514;\nspur_coef_cfg = 0x40002518;\ngen_rx_gain_table = 0x4000251c;\nwr_rx_gain_mem = 0x40002520;\nset_rx_gain_param = 0x40002524;\nset_rx_gain_table = 0x40002528;\nrom_tester_wifi_cali = 0x4000252c;\nesp_recover_efuse_data = 0x40002530;\nbt_track_pll_cap = 0x40002534;\nrfpll_cap_track = 0x40002538;\nphy_param_track = 0x4000253c;\ntxpwr_correct = 0x40002540;\ntxpwr_cal_track = 0x40002544;\n\/* tx_pwctrl_background = 0x40002548;*\/\nbt_track_tx_power = 0x4000254c;\nwifi_track_tx_power = 0x40002550;\nrom_code_to_temp = 0x40002554;\nrom_tsens_index_to_dac = 0x40002558;\nrom_tsens_index_to_offset = 0x4000255c;\nrom_tsens_dac_cal = 0x40002560;\nrom_tsens_code_read = 0x40002564;\nrom_tsens_temp_read = 0x40002568;\nrom_temp_to_power = 0x4000256c;\ntsens_read_init = 0x40002570;\nget_temp_init = 0x40002574;\nrom_txiq_cover = 0x40002578;\nrom_rfcal_txiq = 0x4000257c;\nrom_get_power_atten = 0x40002580;\nrom_tx_pwctrl_init_cal = 0x40002584;\nbt_txdc_cal = 0x40002588;\nbt_txiq_cal = 0x4000258c;\ntxiq_cal_init = 0x40002590;\ntxdc_cal_init = 0x40002594;\ntxdc_cal_v70 = 0x40002598;\ntxiq_get_mis_pwr = 0x4000259c;\npwdet_ref_code = 0x400025a0;\npwdet_code_cal = 0x400025a4;\nrfcal_txcap = 0x400025a8;\ntx_cap_init = 0x400025ac;\nrfcal_pwrctrl = 0x400025b0;\ntx_pwctrl_init = 0x400025b4;\nbt_tx_pwctrl_init = 0x400025b8;\nbt_txpwr_freq = 0x400025bc;\nrom_txbbgain_to_index = 0x400025c0;\nrom_index_to_txbbgain = 0x400025c4;\nrom_bt_index_to_bb = 0x400025c8;\nrom_bt_bb_to_index = 0x400025cc;\nrom_bt_get_tx_gain = 0x400025d0;\nrom_get_tx_gain_value = 0x400025d4;\nrom_wifi_get_tx_gain = 0x400025d8;\nrom_set_tx_gain_mem = 0x400025dc;\nrom_get_rate_fcc_index = 0x400025e0;\nrom_get_chan_target_power = 0x400025e4;\nrom_wifi_tx_dig_gain = 0x400025e8;\nrom_wifi_set_tx_gain = 0x400025ec;\nrom_bt_set_tx_gain = 0x400025f0;\nwifi_11g_rate_chg = 0x400025f4;\nbt_chan_pwr_interp = 0x400025f8;\nbt_tx_gain_init = 0x400025fc;\n\/* Data (.data, .bss, .rodata) *\/\nphy_param_rom = 0x3fcdfaa4;\n\n\n\/***************************************\n Group rom_btbb\n ***************************************\/\n\n\/* Functions *\/\nbt_agc_gain_offset = 0x40002600;\nbt_agc_gain_max = 0x40002604;\nbt_set_rx_comp = 0x40002608;\nbt_agc_gain_set = 0x4000260c;\nbt_agc_rssi_thresh = 0x40002610;\nbt_agc_target_set = 0x40002614;\nbt_agc_restart_set = 0x40002618;\nbt_agc_recorrect_set = 0x4000261c;\nbt_agc_detect_set = 0x40002620;\nbt_bb_rx_correlator_set = 0x40002624;\nbt_bb_rx_dpo_set = 0x40002628;\nbt_bb_rx_filter_sel = 0x4000262c;\nbt_bb_rx_set1 = 0x40002630;\nbt_bb_v2_rx_set = 0x40002634;\nbt_bb_v2_tx_set = 0x40002638;\nbt_bb_tx_cca_set = 0x4000263c;\nbt_bb_tx_cca_period = 0x40002640;\nbt_bb_tx_cca_fifo_reset = 0x40002644;\nbt_bb_tx_cca_fifo_empty = 0x40002648;\nbt_bb_tx_cca_fifo_full = 0x4000264c;\nbt_bb_tx_cca_fifo_count = 0x40002650;\nbt_bb_tx_cca_fifo_read = 0x40002654;\ncoex_pti_v2 = 0x40002658;\nbt_bb_set_le_tx_on_delay = 0x4000265c;\nbt_bb_set_corr_thresh_le = 0x40002660;\n","old_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\nrtc_get_wakeup_cause = 0x40000020;\nrtc_select_apb_bridge = 0x40000024;\nrtc_unhold_all_pads = 0x40000028;\nets_is_print_boot = 0x4000002c;\nets_vprintf = 0x40000030;\nets_printf = 0x40000034;\nets_install_putc1 = 0x40000038;\nets_install_uart_printf = 0x4000003c;\nets_install_putc2 = 0x40000040;\nets_delay_us = 0x40000044;\nets_get_stack_info = 0x40000048;\nets_install_lock = 0x4000004c;\nUartRxString = 0x40000050;\nUartGetCmdLn = 0x40000054;\nuart_tx_one_char = 0x40000058;\nuart_tx_one_char2 = 0x4000005c;\nuart_rx_one_char = 0x40000060;\nuart_rx_one_char_block = 0x40000064;\nuart_rx_readbuff = 0x40000068;\nuartAttach = 0x4000006c;\nuart_tx_flush = 0x40000070;\nuart_tx_wait_idle = 0x40000074;\nuart_div_modify = 0x40000078;\nets_write_char_uart = 0x4000007c;\nuart_tx_switch = 0x40000080;\nmultofup = 0x40000084;\nsoftware_reset = 0x40000088;\nsoftware_reset_cpu = 0x4000008c;\nassist_debug_clock_enable = 0x40000090;\nassist_debug_record_enable = 0x40000094;\nclear_super_wdt_reset_flag = 0x40000098;\ndisable_default_watchdog = 0x4000009c;\nsend_packet = 0x400000a0;\nrecv_packet = 0x400000a4;\nGetUartDevice = 0x400000a8;\nUartDwnLdProc = 0x400000ac;\nGetSecurityInfoProc = 0x400000b0;\nUart_Init = 0x400000b4;\nets_set_user_start = 0x400000b8;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff4fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000bc;\nmz_free = 0x400000c0;\ntdefl_compress = 0x400000c4;\ntdefl_compress_buffer = 0x400000c8;\ntdefl_compress_mem_to_heap = 0x400000cc;\ntdefl_compress_mem_to_mem = 0x400000d0;\ntdefl_compress_mem_to_output = 0x400000d4;\ntdefl_get_adler32 = 0x400000d8;\ntdefl_get_prev_return_status = 0x400000dc;\ntdefl_init = 0x400000e0;\ntdefl_write_image_to_png_file_in_memory = 0x400000e4;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000e8;\ntinfl_decompress = 0x400000ec;\ntinfl_decompress_mem_to_callback = 0x400000f0;\ntinfl_decompress_mem_to_heap = 0x400000f4;\ntinfl_decompress_mem_to_mem = 0x400000f8;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 );\nPROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 );\nPROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 );\nPROVIDE( _esp_rom_spiflash_write = 0x4000011c );\nPROVIDE( _esp_rom_spiflash_read = 0x40000120 );\nPROVIDE( _esp_rom_spiflash_unlock = 0x40000124 );\nPROVIDE( _SPIEraseArea = 0x40000128 );\nPROVIDE( _SPI_write_enable = 0x4000012c );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000134 );\nPROVIDE( esp_rom_spiflash_write = 0x40000138 );\nPROVIDE( esp_rom_spiflash_read = 0x4000013c );\nPROVIDE( esp_rom_spiflash_unlock = 0x40000140 );\nPROVIDE( SPIEraseArea = 0x40000144 );\nPROVIDE( SPI_write_enable = 0x40000148 );\nPROVIDE( esp_rom_spiflash_config_param = 0x4000014c );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c );\nPROVIDE( esp_rom_spi_flash_update_id = 0x40000160 );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000164 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 );\nPROVIDE( esp_rom_spiflash_read_status = 0x4000016c );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000174 );\nPROVIDE( spi_flash_attach = 0x40000178 );\nPROVIDE( spi_flash_get_chip_size = 0x4000017c );\nPROVIDE( spi_flash_guard_set = 0x40000180 );\nPROVIDE( spi_flash_guard_get = 0x40000184 );\nPROVIDE( spi_flash_read_encrypted = 0x40000188 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x4000018c );\nPROVIDE( spi_flash_mmap_page_num_init = 0x40000190 );\nPROVIDE( spi_flash_mmap = 0x40000194 );\nPROVIDE( spi_flash_mmap_pages = 0x40000198 );\nPROVIDE( spi_flash_munmap = 0x4000019c );\nPROVIDE( spi_flash_mmap_dump = 0x400001a0 );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );\nPROVIDE( spi_flash_cache2phys = 0x400001ac );\nPROVIDE( spi_flash_phys2cache = 0x400001b0 );\nPROVIDE( spi_flash_disable_cache = 0x400001b4 );\nPROVIDE( spi_flash_restore_cache = 0x400001b8 );\nPROVIDE( spi_flash_cache_enabled = 0x400001bc );\nPROVIDE( spi_flash_enable_cache = 0x400001c0 );\nPROVIDE( spi_cache_mode_switch = 0x400001c4 );\nPROVIDE( spi_common_set_dummy_output = 0x400001c8 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001cc );\nPROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 );\nPROVIDE( SPILock = 0x400001d8 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001dc );\nPROVIDE( SPI_Common_Command = 0x400001e0 );\nPROVIDE( SPI_WakeUp = 0x400001e4 );\nPROVIDE( SPI_block_erase = 0x400001e8 );\nPROVIDE( SPI_chip_erase = 0x400001ec );\nPROVIDE( SPI_init = 0x400001f0 );\nPROVIDE( SPI_page_program = 0x400001f4 );\nPROVIDE( SPI_read_data = 0x400001f8 );\nPROVIDE( SPI_sector_erase = 0x400001fc );\nPROVIDE( SelectSpiFunction = 0x40000200 );\nPROVIDE( SetSpiDrvs = 0x40000204 );\nPROVIDE( Wait_SPI_Idle = 0x40000208 );\nPROVIDE( spi_dummy_len_fix = 0x4000020c );\nPROVIDE( Disable_QMode = 0x40000210 );\nPROVIDE( Enable_QMode = 0x40000214 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group hal_soc\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 );\nPROVIDE( spi_flash_hal_device_config = 0x4000021c );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 );\nPROVIDE( spi_flash_hal_common_command = 0x40000224 );\nPROVIDE( spi_flash_hal_read = 0x40000228 );\nPROVIDE( spi_flash_hal_erase_chip = 0x4000022c );\nPROVIDE( spi_flash_hal_erase_sector = 0x40000230 );\nPROVIDE( spi_flash_hal_erase_block = 0x40000234 );\nPROVIDE( spi_flash_hal_program_page = 0x40000238 );\nPROVIDE( spi_flash_hal_set_write_protect = 0x4000023c );\nPROVIDE( spi_flash_hal_host_idle = 0x40000240 );\nPROVIDE( spi_flash_hal_check_status = 0x40000244 );\nPROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 );\nPROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c );\nPROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 );\nPROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 );\nPROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 );\nPROVIDE( spi_flash_hal_resume = 0x4000025c );\nPROVIDE( spi_flash_hal_suspend = 0x40000260 );\nPROVIDE( spi_flash_encryption_hal_enable = 0x40000264 );\nPROVIDE( spi_flash_encryption_hal_disable = 0x40000268 );\nPROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c );\nPROVIDE( spi_flash_encryption_hal_done = 0x40000270 );\nPROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 );\nPROVIDE( spi_flash_encryption_hal_check = 0x40000278 );\nPROVIDE( wdt_hal_init = 0x4000027c );\nPROVIDE( wdt_hal_deinit = 0x40000280 );\nPROVIDE( wdt_hal_config_stage = 0x40000284 );\nPROVIDE( wdt_hal_write_protect_disable = 0x40000288 );\nPROVIDE( wdt_hal_write_protect_enable = 0x4000028c );\nPROVIDE( wdt_hal_enable = 0x40000290 );\nPROVIDE( wdt_hal_disable = 0x40000294 );\nPROVIDE( wdt_hal_handle_intr = 0x40000298 );\nPROVIDE( wdt_hal_feed = 0x4000029c );\nPROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 );\nPROVIDE( wdt_hal_is_enabled = 0x400002a4 );\nPROVIDE( systimer_hal_init = 0x400002a8 );\nPROVIDE( systimer_hal_get_counter_value = 0x400002ac );\nPROVIDE( systimer_hal_get_time = 0x400002b0 );\nPROVIDE( systimer_hal_set_alarm_target = 0x400002b4 );\nPROVIDE( systimer_hal_set_alarm_period = 0x400002b8 );\nPROVIDE( systimer_hal_get_alarm_value = 0x400002bc );\nPROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 );\nPROVIDE( systimer_hal_on_apb_freq_update = 0x400002c4 );\nPROVIDE( systimer_hal_counter_value_advance = 0x400002c8 );\nPROVIDE( systimer_hal_enable_counter = 0x400002cc );\nPROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 );\nPROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 );\nPROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 );\n\n\n\/***************************************\n Group heap\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( tlsf_create = 0x400002dc );\nPROVIDE( tlsf_create_with_pool = 0x400002e0 );\nPROVIDE( tlsf_get_pool = 0x400002e4 );\nPROVIDE( tlsf_add_pool = 0x400002e8 );\nPROVIDE( tlsf_remove_pool = 0x400002ec );\nPROVIDE( tlsf_malloc = 0x400002f0 );\nPROVIDE( tlsf_memalign = 0x400002f4 );\nPROVIDE( tlsf_memalign_offs = 0x400002f8 );\nPROVIDE( tlsf_realloc = 0x400002fc );\nPROVIDE( tlsf_free = 0x40000300 );\nPROVIDE( tlsf_block_size = 0x40000304 );\nPROVIDE( tlsf_size = 0x40000308 );\nPROVIDE( tlsf_align_size = 0x4000030c );\nPROVIDE( tlsf_block_size_min = 0x40000310 );\nPROVIDE( tlsf_block_size_max = 0x40000314 );\nPROVIDE( tlsf_pool_overhead = 0x40000318 );\nPROVIDE( tlsf_alloc_overhead = 0x4000031c );\nPROVIDE( tlsf_walk_pool = 0x40000320 );\nPROVIDE( tlsf_check = 0x40000324 );\nPROVIDE( tlsf_check_pool = 0x40000328 );\nPROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c );\nPROVIDE( multi_heap_get_block_address_impl = 0x40000330 );\nPROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 );\nPROVIDE( multi_heap_register_impl = 0x40000338 );\nPROVIDE( multi_heap_set_lock = 0x4000033c );\nPROVIDE( multi_heap_os_funcs_init = 0x40000340 );\nPROVIDE( multi_heap_internal_lock = 0x40000344 );\nPROVIDE( multi_heap_internal_unlock = 0x40000348 );\nPROVIDE( multi_heap_get_first_block = 0x4000034c );\nPROVIDE( multi_heap_get_next_block = 0x40000350 );\nPROVIDE( multi_heap_is_free = 0x40000354 );\nPROVIDE( multi_heap_malloc_impl = 0x40000358 );\nPROVIDE( multi_heap_free_impl = 0x4000035c );\nPROVIDE( multi_heap_realloc_impl = 0x40000360 );\nPROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 );\nPROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 );\nPROVIDE( multi_heap_check = 0x4000036c );\nPROVIDE( multi_heap_dump = 0x40000370 );\nPROVIDE( multi_heap_free_size_impl = 0x40000374 );\nPROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 );\nPROVIDE( multi_heap_get_info_impl = 0x4000037c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x40000380 );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 );\nPROVIDE( spi_flash_chip_generic_write = 0x40000388 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000398 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 );\nPROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 );\nPROVIDE( spi_flash_chip_generic_yield = 0x400003b8 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 );\nPROVIDE( spi_flash_chip_generic_read = 0x400003c8 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc );\nPROVIDE( spi_flash_common_set_io_mode = 0x400003e0 );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 );\nPROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 );\nPROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec );\nPROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400003f8 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );\nPROVIDE( spi_flash_encryption = 0x3fcdffe4 );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x40000400 );\nPROVIDE( memspi_host_read_status_hs = 0x40000404 );\nPROVIDE( memspi_host_flush_cache = 0x40000408 );\nPROVIDE( memspi_host_erase_chip = 0x4000040c );\nPROVIDE( memspi_host_erase_sector = 0x40000410 );\nPROVIDE( memspi_host_erase_block = 0x40000414 );\nPROVIDE( memspi_host_program_page = 0x40000418 );\nPROVIDE( memspi_host_read = 0x4000041c );\nPROVIDE( memspi_host_set_write_protect = 0x40000420 );\nPROVIDE( memspi_host_set_max_read_len = 0x40000424 );\nPROVIDE( memspi_host_read_data_slicer = 0x40000428 );\nPROVIDE( memspi_host_write_data_slicer = 0x4000042c );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x40000430 );\nPROVIDE( esp_flash_read_id = 0x40000434 );\nPROVIDE( esp_flash_get_size = 0x40000438 );\nPROVIDE( esp_flash_erase_chip = 0x4000043c );\nPROVIDE( esp_flash_erase_region = 0x40000440 );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000444 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000448 );\nPROVIDE( esp_flash_get_protectable_regions = 0x4000044c );\nPROVIDE( esp_flash_get_protected_region = 0x40000450 );\nPROVIDE( esp_flash_set_protected_region = 0x40000454 );\nPROVIDE( esp_flash_read = 0x40000458 );\nPROVIDE( esp_flash_write = 0x4000045c );\nPROVIDE( esp_flash_write_encrypted = 0x40000460 );\nPROVIDE( esp_flash_read_encrypted = 0x40000464 );\nPROVIDE( esp_flash_get_io_mode = 0x40000468 );\nPROVIDE( esp_flash_set_io_mode = 0x4000046c );\nPROVIDE( spi_flash_boot_attach = 0x40000470 );\nPROVIDE( esp_flash_read_chip_id = 0x40000474 );\nPROVIDE( detect_spi_flash_chip = 0x40000478 );\nPROVIDE( esp_rom_spiflash_write_disable = 0x4000047c );\nPROVIDE( esp_flash_suspend_cmd_init = 0x40000480 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe0 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffdc );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 );\nPROVIDE( Cache_Get_Mode = 0x400006e4 );\nPROVIDE( Cache_Address_Through_IBus = 0x400006e8 );\nPROVIDE( Cache_Address_Through_DBus = 0x400006ec );\nPROVIDE( Cache_Set_Default_Mode = 0x400006f0 );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400006f8 );\nPROVIDE( MMU_Set_Page_Mode = 0x400006fc );\nPROVIDE( MMU_Get_Page_Mode = 0x40000700 );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x40000704 );\nPROVIDE( Cache_Op_Addr = 0x40000708 );\nPROVIDE( Cache_Invalidate_Addr = 0x4000070c );\nPROVIDE( Cache_Invalidate_ICache_All = 0x40000710 );\nPROVIDE( Cache_Mask_All = 0x40000714 );\nPROVIDE( Cache_UnMask_Dram0 = 0x40000718 );\nPROVIDE( Cache_Disable_ICache = 0x4000071c );\nPROVIDE( Cache_Enable_ICache = 0x40000720 );\nPROVIDE( Cache_Suspend_ICache = 0x40000724 );\nPROVIDE( Cache_Resume_ICache = 0x40000728 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x4000072c );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x40000730 );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000734 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x40000738 );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x4000073c );\nPROVIDE( Cache_Owner_Init = 0x40000740 );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000744 );\nPROVIDE( Cache_MMU_Init = 0x40000748 );\nPROVIDE( Cache_Ibus_MMU_Set = 0x4000074c );\nPROVIDE( Cache_Dbus_MMU_Set = 0x40000750 );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000754 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x40000758 );\nPROVIDE( Cache_Get_Virtual_Addr = 0x4000075c );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x40000760 );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000764 );\nPROVIDE( Cache_Get_Memory_value = 0x40000768 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd0 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x4000076c;\nets_get_cpu_frequency = 0x40000770;\nets_update_cpu_frequency = 0x40000774;\nets_get_printf_channel = 0x40000778;\nets_get_xtal_div = 0x4000077c;\nets_set_xtal_div = 0x40000780;\nets_get_xtal_freq = 0x40000784;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x40000788;\ngpio_matrix_in = 0x4000078c;\ngpio_matrix_out = 0x40000790;\ngpio_output_disable = 0x40000794;\ngpio_output_enable = 0x40000798;\ngpio_output_set = 0x4000079c;\ngpio_pad_hold = 0x400007a0;\ngpio_pad_input_disable = 0x400007a4;\ngpio_pad_input_enable = 0x400007a8;\ngpio_pad_pulldown = 0x400007ac;\ngpio_pad_pullup = 0x400007b0;\ngpio_pad_select_gpio = 0x400007b4;\ngpio_pad_set_drv = 0x400007b8;\ngpio_pad_unhold = 0x400007bc;\ngpio_pin_wakeup_disable = 0x400007c0;\ngpio_pin_wakeup_enable = 0x400007c4;\ngpio_bypass_matrix_in = 0x400007c8;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400007cc;\nesprv_intc_int_set_threshold = 0x400007d0;\nesprv_intc_int_enable = 0x400007d4;\nesprv_intc_int_disable = 0x400007d8;\nesprv_intc_int_set_type = 0x400007dc;\nPROVIDE( intr_handler_set = 0x400007e0 );\nintr_matrix_set = 0x400007e4;\nets_intr_lock = 0x400007e8;\nets_intr_unlock = 0x400007ec;\nets_isr_attach = 0x400007f0;\nets_isr_mask = 0x400007f4;\nets_isr_unmask = 0x400007f8;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\ncrc32_le = 0x400007fc;\ncrc16_le = 0x40000800;\ncrc8_le = 0x40000804;\ncrc32_be = 0x40000808;\ncrc16_be = 0x4000080c;\ncrc8_be = 0x40000810;\nesp_crc8 = 0x40000814;\nets_sha_enable = 0x40000818;\nets_sha_disable = 0x4000081c;\nets_sha_get_state = 0x40000820;\nets_sha_init = 0x40000824;\nets_sha_process = 0x40000828;\nets_sha_starts = 0x4000082c;\nets_sha_update = 0x40000830;\nets_sha_finish = 0x40000834;\nets_sha_clone = 0x40000838;\n\/* Data (.data, .bss, .rodata) *\/\ncrc32_le_table_ptr = 0x3ff4fff8;\ncrc16_le_table_ptr = 0x3ff4fff4;\ncrc8_le_table_ptr = 0x3ff4fff0;\ncrc32_be_table_ptr = 0x3ff4ffec;\ncrc16_be_table_ptr = 0x3ff4ffe8;\ncrc8_be_table_ptr = 0x3ff4ffe4;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x4000083c;\nets_efuse_program = 0x40000840;\nets_efuse_clear_program_registers = 0x40000844;\nets_efuse_write_key = 0x40000848;\nets_efuse_get_read_register_address = 0x4000084c;\nets_efuse_get_key_purpose = 0x40000850;\nets_efuse_key_block_unused = 0x40000854;\nets_efuse_find_unused_key_block = 0x40000858;\nets_efuse_rs_calculate = 0x4000085c;\nets_efuse_count_unused_key_blocks = 0x40000860;\nets_efuse_secure_boot_enabled = 0x40000864;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000868;\nets_efuse_cache_encryption_enabled = 0x4000086c;\nets_efuse_download_modes_disabled = 0x40000870;\nets_efuse_find_purpose = 0x40000874;\nets_efuse_force_send_resume = 0x40000878;\nets_efuse_get_flash_delay_us = 0x4000087c;\nets_efuse_get_mac = 0x40000880;\nets_efuse_get_uart_print_control = 0x40000884;\nets_efuse_direct_boot_mode_disabled = 0x40000888;\nets_efuse_security_download_modes_enabled = 0x4000088c;\nets_efuse_set_timing = 0x40000890;\nets_efuse_jtag_disabled = 0x40000894;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_ecdsa_verify = 0x40000898;\nets_secure_boot_verify_bootloader_with_keys = 0x4000089c;\nets_secure_boot_verify_signature = 0x400008a0;\nets_secure_boot_read_key_digests = 0x400008a4;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Data (.data, .bss, .rodata) *\/\ng_uart_print = 0x3fcdffc9;\ng_usb_print = 0x3fcdffc8;\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nble_controller_rom_data_init = 0x40000aa8;\nble_osi_coex_funcs_register = 0x40000aac;\nbt_rf_coex_cfg_get_default = 0x40000ab0;\nbt_rf_coex_dft_pti_get_default = 0x40000ab4;\nbt_rf_coex_hooks_p_set = 0x40000ab8;\nr__os_mbuf_copypkthdr = 0x40000abc;\nr__os_msys_find_pool = 0x40000ac0;\nr_ble_controller_get_rom_compile_version = 0x40000ac4;\nr_ble_hci_ram_hs_acl_tx = 0x40000ac8;\nr_ble_hci_ram_hs_cmd_tx = 0x40000acc;\nr_ble_hci_ram_ll_acl_tx = 0x40000ad0;\nr_ble_hci_ram_ll_evt_tx = 0x40000ad4;\nr_ble_hci_ram_reset = 0x40000ad8;\nr_ble_hci_ram_set_acl_free_cb = 0x40000adc;\nr_ble_hci_trans_acl_buf_alloc = 0x40000ae0;\nr_ble_hci_trans_buf_alloc = 0x40000ae4;\nr_ble_hci_trans_buf_free = 0x40000ae8;\nr_ble_hci_trans_cfg_hs = 0x40000aec;\nr_ble_hci_trans_cfg_ll = 0x40000af0;\nr_ble_hci_trans_deinit = 0x40000af4;\nr_ble_hci_trans_env_init = 0x40000af8;\nr_ble_hci_trans_init = 0x40000afc;\nr_ble_hci_uart_acl_tx = 0x40000b00;\nr_ble_hci_uart_cmdevt_tx = 0x40000b04;\nr_ble_hci_uart_config = 0x40000b08;\nr_ble_hci_uart_free_pkt = 0x40000b0c;\nr_ble_hci_uart_hs_acl_tx = 0x40000b10;\nr_ble_hci_uart_hs_cmd_tx = 0x40000b14;\nr_ble_hci_uart_ll_acl_tx = 0x40000b18;\nr_ble_hci_uart_ll_evt_tx = 0x40000b1c;\nr_ble_hci_uart_rx_acl = 0x40000b20;\nr_ble_hci_uart_rx_char = 0x40000b24;\nr_ble_hci_uart_rx_cmd = 0x40000b28;\nr_ble_hci_uart_rx_evt = 0x40000b2c;\nr_ble_hci_uart_rx_evt_cb = 0x40000b30;\nr_ble_hci_uart_rx_le_evt = 0x40000b34;\nr_ble_hci_uart_rx_pkt_type = 0x40000b38;\nr_ble_hci_uart_rx_skip_acl = 0x40000b3c;\nr_ble_hci_uart_rx_skip_cmd = 0x40000b40;\nr_ble_hci_uart_rx_skip_evt = 0x40000b44;\nr_ble_hci_uart_rx_sync_loss = 0x40000b48;\nr_ble_hci_uart_set_acl_free_cb = 0x40000b4c;\nr_ble_hci_uart_sync_lost = 0x40000b50;\nr_ble_hci_uart_trans_reset = 0x40000b54;\nr_ble_hci_uart_tx_char = 0x40000b58;\nr_ble_hci_uart_tx_pkt_type = 0x40000b5c;\nr_ble_hw_driver_deinit = 0x40000b60;\nr_ble_hw_driver_env_init = 0x40000b64;\nr_ble_hw_encrypt_block = 0x40000b68;\nr_ble_hw_get_public_addr = 0x40000b6c;\nr_ble_hw_get_static_addr = 0x40000b70;\nr_ble_hw_periodiclist_add = 0x40000b74;\nr_ble_hw_periodiclist_clear = 0x40000b78;\nr_ble_hw_periodiclist_rmv = 0x40000b7c;\nr_ble_hw_resolv_list_cur_entry = 0x40000b80;\nr_ble_hw_resolv_list_get_cur_entry = 0x40000b84;\nr_ble_hw_resolv_list_set = 0x40000b88;\nr_ble_hw_rng_init = 0x40000b8c;\nr_ble_hw_rng_start = 0x40000b90;\nr_ble_hw_rng_stop = 0x40000b94;\nr_ble_hw_rx_local_is_resolved = 0x40000b98;\nr_ble_hw_rx_local_is_rpa = 0x40000b9c;\nr_ble_hw_whitelist_add = 0x40000ba0;\nr_ble_hw_whitelist_clear = 0x40000ba4;\nr_ble_hw_whitelist_dev_num = 0x40000ba8;\nr_ble_hw_whitelist_get_base = 0x40000bac;\nr_ble_hw_whitelist_rmv = 0x40000bb0;\nr_ble_hw_whitelist_search = 0x40000bb4;\nr_ble_hw_whitelist_sort = 0x40000bb8;\nr_ble_ll_acl_data_in = 0x40000bbc;\nr_ble_ll_addr_is_id = 0x40000bc0;\nr_ble_ll_addr_subtype = 0x40000bc4;\nr_ble_ll_adv_active_chanset_clear = 0x40000bc8;\nr_ble_ll_adv_active_chanset_is_pri = 0x40000bcc;\nr_ble_ll_adv_active_chanset_is_sec = 0x40000bd0;\nr_ble_ll_adv_active_chanset_set_pri = 0x40000bd4;\nr_ble_ll_adv_active_chanset_set_sec = 0x40000bd8;\nr_ble_ll_adv_aux_calculate = 0x40000bdc;\nr_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000be0;\nr_ble_ll_adv_aux_pdu_make = 0x40000be4;\nr_ble_ll_adv_aux_scannable_pdu_make = 0x40000be8;\nr_ble_ll_adv_aux_txed = 0x40000bec;\nr_ble_ll_adv_can_chg_whitelist = 0x40000bf0;\nr_ble_ll_adv_chk_rpa_timeout = 0x40000bf4;\nr_ble_ll_adv_clear_all = 0x40000bf8;\nr_ble_ll_adv_conn_req_rxd = 0x40000bfc;\nr_ble_ll_adv_deinit = 0x40000c00;\nr_ble_ll_adv_enabled = 0x40000c04;\nr_ble_ll_adv_env_init = 0x40000c08;\nr_ble_ll_adv_ext_set_adv_data = 0x40000c0c;\nr_ble_ll_adv_ext_set_enable = 0x40000c10;\nr_ble_ll_adv_ext_set_param = 0x40000c14;\nr_ble_ll_adv_ext_set_scan_rsp = 0x40000c18;\nr_ble_ll_adv_final_chan = 0x40000c1c;\nr_ble_ll_adv_first_chan = 0x40000c20;\nr_ble_ll_adv_flags_clear = 0x40000c24;\nr_ble_ll_adv_flags_set = 0x40000c28;\nr_ble_ll_adv_get_chan_num = 0x40000c2c;\nr_ble_ll_adv_get_local_rpa = 0x40000c30;\nr_ble_ll_adv_get_peer_rpa = 0x40000c34;\nr_ble_ll_adv_hci_set_random_addr = 0x40000c38;\nr_ble_ll_adv_init = 0x40000c3c;\nr_ble_ll_adv_legacy_pdu_make = 0x40000c40;\nr_ble_ll_adv_next_chan = 0x40000c44;\nr_ble_ll_adv_pdu_make = 0x40000c48;\nr_ble_ll_adv_periodic_check_data_itvl = 0x40000c4c;\nr_ble_ll_adv_periodic_enable = 0x40000c50;\nr_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c54;\nr_ble_ll_adv_periodic_send_sync_ind = 0x40000c58;\nr_ble_ll_adv_periodic_set_data = 0x40000c5c;\nr_ble_ll_adv_periodic_set_info_transfer = 0x40000c60;\nr_ble_ll_adv_periodic_set_param = 0x40000c64;\nr_ble_ll_adv_pre_process = 0x40000c68;\nr_ble_ll_adv_put_acad_chM_update_ind = 0x40000c6c;\nr_ble_ll_adv_put_aux_ptr = 0x40000c70;\nr_ble_ll_adv_put_syncinfo = 0x40000c74;\nr_ble_ll_adv_rd_max_adv_data_len = 0x40000c78;\nr_ble_ll_adv_rd_sup_adv_sets = 0x40000c7c;\nr_ble_ll_adv_read_txpwr = 0x40000c80;\nr_ble_ll_adv_remove = 0x40000c84;\nr_ble_ll_adv_reset = 0x40000c88;\nr_ble_ll_adv_rpa_timeout = 0x40000c8c;\nr_ble_ll_adv_rpa_update = 0x40000c90;\nr_ble_ll_adv_rx_pkt_in = 0x40000c94;\nr_ble_ll_adv_scan_req_rxd = 0x40000c98;\nr_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c;\nr_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0;\nr_ble_ll_adv_scheduled = 0x40000ca4;\nr_ble_ll_adv_send_conn_comp_ev = 0x40000ca8;\nr_ble_ll_adv_set_adv_data = 0x40000cac;\nr_ble_ll_adv_set_adv_params = 0x40000cb0;\nr_ble_ll_adv_set_enable = 0x40000cb4;\nr_ble_ll_adv_set_random_addr = 0x40000cb8;\nr_ble_ll_adv_set_scan_rsp_data = 0x40000cbc;\nr_ble_ll_adv_set_sched = 0x40000cc0;\nr_ble_ll_adv_sm_deinit = 0x40000cc4;\nr_ble_ll_adv_sm_event_init = 0x40000cc8;\nr_ble_ll_adv_sm_find_configured = 0x40000ccc;\nr_ble_ll_adv_sm_get = 0x40000cd0;\nr_ble_ll_adv_sm_init = 0x40000cd4;\nr_ble_ll_adv_sm_reset = 0x40000cd8;\nr_ble_ll_adv_sm_start = 0x40000cdc;\nr_ble_ll_adv_sm_start_periodic = 0x40000ce0;\nr_ble_ll_adv_sm_stop = 0x40000ce4;\nr_ble_ll_adv_sm_stop_limit_reached = 0x40000ce8;\nr_ble_ll_adv_sm_stop_periodic = 0x40000cec;\nr_ble_ll_adv_sm_stop_timeout = 0x40000cf0;\nr_ble_ll_adv_sync_calculate = 0x40000cf4;\nr_ble_ll_adv_sync_get_pdu_len = 0x40000cf8;\nr_ble_ll_adv_sync_pdu_make = 0x40000cfc;\nr_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d00;\nr_ble_ll_adv_update_data_mbuf = 0x40000d04;\nr_ble_ll_adv_update_did = 0x40000d08;\nr_ble_ll_adv_update_periodic_data = 0x40000d0c;\nr_ble_ll_arr_pool_init = 0x40000d10;\nr_ble_ll_auth_pyld_tmo_event_send = 0x40000d14;\nr_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d18;\nr_ble_ll_calc_session_key = 0x40000d1c;\nr_ble_ll_calc_ticks_per_slot = 0x40000d20;\nr_ble_ll_check_scan_params = 0x40000d24;\nr_ble_ll_chk_txrx_octets = 0x40000d28;\nr_ble_ll_chk_txrx_time = 0x40000d2c;\nr_ble_ll_conn_adjust_pyld_len = 0x40000d30;\nr_ble_ll_conn_auth_pyld_timer_cb = 0x40000d34;\nr_ble_ll_conn_auth_pyld_timer_start = 0x40000d38;\nr_ble_ll_conn_calc_dci = 0x40000d3c;\nr_ble_ll_conn_calc_dci_csa1 = 0x40000d40;\nr_ble_ll_conn_calc_itvl_ticks = 0x40000d44;\nr_ble_ll_conn_chk_csm_flags = 0x40000d48;\nr_ble_ll_conn_chk_phy_upd_start = 0x40000d4c;\nr_ble_ll_conn_comp_event_send = 0x40000d50;\nr_ble_ll_conn_connect_ind_pdu_make = 0x40000d54;\nr_ble_ll_conn_create = 0x40000d58;\nr_ble_ll_conn_create_cancel = 0x40000d5c;\nr_ble_ll_conn_created = 0x40000d60;\nr_ble_ll_conn_cth_flow_enable = 0x40000d64;\nr_ble_ll_conn_cth_flow_error_fn = 0x40000d68;\nr_ble_ll_conn_cth_flow_have_credit = 0x40000d6c;\nr_ble_ll_conn_cth_flow_is_enabled = 0x40000d70;\nr_ble_ll_conn_cth_flow_process_cmd = 0x40000d74;\nr_ble_ll_conn_cth_flow_set_buffers = 0x40000d78;\nr_ble_ll_conn_enqueue_pkt = 0x40000d7c;\nr_ble_ll_conn_env_init = 0x40000d80;\nr_ble_ll_conn_ext_master_init = 0x40000d84;\nr_ble_ll_conn_find_active_conn = 0x40000d88;\nr_ble_ll_conn_get_active_conn = 0x40000d8c;\nr_ble_ll_conn_get_anchor = 0x40000d90;\nr_ble_ll_conn_hcc_params_set_fallback = 0x40000d94;\nr_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000d98;\nr_ble_ll_conn_hci_chk_conn_params = 0x40000d9c;\nr_ble_ll_conn_hci_chk_scan_params = 0x40000da0;\nr_ble_ll_conn_hci_disconnect_cmd = 0x40000da4;\nr_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000da8;\nr_ble_ll_conn_hci_le_ltk_reply = 0x40000dac;\nr_ble_ll_conn_hci_le_rd_phy = 0x40000db0;\nr_ble_ll_conn_hci_le_set_phy = 0x40000db4;\nr_ble_ll_conn_hci_le_start_encrypt = 0x40000db8;\nr_ble_ll_conn_hci_param_nrr = 0x40000dbc;\nr_ble_ll_conn_hci_param_rr = 0x40000dc0;\nr_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000dc4;\nr_ble_ll_conn_hci_rd_chan_map = 0x40000dc8;\nr_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000dcc;\nr_ble_ll_conn_hci_rd_rssi = 0x40000dd0;\nr_ble_ll_conn_hci_read_rem_features = 0x40000dd4;\nr_ble_ll_conn_hci_set_chan_class = 0x40000dd8;\nr_ble_ll_conn_hci_set_data_len = 0x40000ddc;\nr_ble_ll_conn_hci_update = 0x40000de0;\nr_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000de4;\nr_ble_ll_conn_init_phy = 0x40000de8;\nr_ble_ll_conn_is_dev_connected = 0x40000dec;\nr_ble_ll_conn_is_empty_pdu = 0x40000df0;\nr_ble_ll_conn_is_lru = 0x40000df4;\nr_ble_ll_conn_master_init = 0x40000df8;\nr_ble_ll_conn_module_deinit = 0x40000dfc;\nr_ble_ll_conn_module_init = 0x40000e00;\nr_ble_ll_conn_module_reset = 0x40000e04;\nr_ble_ll_conn_next_event = 0x40000e08;\nr_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c;\nr_ble_ll_conn_prepare_tx_pdu = 0x40000e10;\nr_ble_ll_conn_process_conn_params = 0x40000e14;\nr_ble_ll_conn_req_peer_sca = 0x40000e18;\nr_ble_ll_conn_rx_data_pdu = 0x40000e1c;\nr_ble_ll_conn_set_csa = 0x40000e20;\nr_ble_ll_conn_set_ext_con_params = 0x40000e24;\nr_ble_ll_conn_set_global_chanmap = 0x40000e28;\nr_ble_ll_conn_set_phy = 0x40000e2c;\nr_ble_ll_conn_set_txpwr_by_handle = 0x40000e30;\nr_ble_ll_conn_set_unknown_rx_octets = 0x40000e34;\nr_ble_ll_conn_slave_start = 0x40000e38;\nr_ble_ll_conn_sm_get = 0x40000e3c;\nr_ble_ll_conn_sm_new = 0x40000e40;\nr_ble_ll_conn_sm_npl_deinit = 0x40000e44;\nr_ble_ll_conn_sm_npl_init = 0x40000e48;\nr_ble_ll_conn_tx_pkt_in = 0x40000e4c;\nr_ble_ll_conn_update_eff_data_len = 0x40000e50;\nr_ble_ll_ctrl_chanmap_req_make = 0x40000e54;\nr_ble_ll_ctrl_chk_proc_start = 0x40000e58;\nr_ble_ll_ctrl_conn_param_pdu_make = 0x40000e5c;\nr_ble_ll_ctrl_conn_param_pdu_proc = 0x40000e60;\nr_ble_ll_ctrl_conn_param_reply = 0x40000e64;\nr_ble_ll_ctrl_conn_upd_make = 0x40000e68;\nr_ble_ll_ctrl_datalen_upd_make = 0x40000e6c;\nr_ble_ll_ctrl_enc_allowed_pdu = 0x40000e70;\nr_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000e74;\nr_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40000e78;\nr_ble_ll_ctrl_enc_req_make = 0x40000e7c;\nr_ble_ll_ctrl_find_new_phy = 0x40000e80;\nr_ble_ll_ctrl_initiate_dle = 0x40000e84;\nr_ble_ll_ctrl_len_proc = 0x40000e88;\nr_ble_ll_ctrl_min_used_chan_rsp = 0x40000e8c;\nr_ble_ll_ctrl_phy_from_phy_mask = 0x40000e90;\nr_ble_ll_ctrl_phy_req_rsp_make = 0x40000e94;\nr_ble_ll_ctrl_phy_tx_transition_get = 0x40000e98;\nr_ble_ll_ctrl_phy_update_cancel = 0x40000e9c;\nr_ble_ll_ctrl_phy_update_ind_make = 0x40000ea0;\nr_ble_ll_ctrl_phy_update_proc_complete = 0x40000ea4;\nr_ble_ll_ctrl_proc_init = 0x40000ea8;\nr_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000eac;\nr_ble_ll_ctrl_proc_start = 0x40000eb0;\nr_ble_ll_ctrl_proc_stop = 0x40000eb4;\nr_ble_ll_ctrl_proc_unk_rsp = 0x40000eb8;\nr_ble_ll_ctrl_proc_with_instant_initiated = 0x40000ebc;\nr_ble_ll_ctrl_rej_ext_ind_make = 0x40000ec0;\nr_ble_ll_ctrl_reject_ind_send = 0x40000ec4;\nr_ble_ll_ctrl_rx_chanmap_req = 0x40000ec8;\nr_ble_ll_ctrl_rx_conn_param_req = 0x40000ecc;\nr_ble_ll_ctrl_rx_conn_param_rsp = 0x40000ed0;\nr_ble_ll_ctrl_rx_conn_update = 0x40000ed4;\nr_ble_ll_ctrl_rx_enc_req = 0x40000ed8;\nr_ble_ll_ctrl_rx_enc_rsp = 0x40000edc;\nr_ble_ll_ctrl_rx_feature_req = 0x40000ee0;\nr_ble_ll_ctrl_rx_feature_rsp = 0x40000ee4;\nr_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8;\nr_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec;\nr_ble_ll_ctrl_rx_pdu = 0x40000ef0;\nr_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4;\nr_ble_ll_ctrl_rx_phy_req = 0x40000ef8;\nr_ble_ll_ctrl_rx_phy_rsp = 0x40000efc;\nr_ble_ll_ctrl_rx_phy_update_ind = 0x40000f00;\nr_ble_ll_ctrl_rx_ping_rsp = 0x40000f04;\nr_ble_ll_ctrl_rx_reject_ind = 0x40000f08;\nr_ble_ll_ctrl_rx_sca_req = 0x40000f0c;\nr_ble_ll_ctrl_rx_sca_rsp = 0x40000f10;\nr_ble_ll_ctrl_rx_start_enc_req = 0x40000f14;\nr_ble_ll_ctrl_rx_start_enc_rsp = 0x40000f18;\nr_ble_ll_ctrl_rx_version_ind = 0x40000f1c;\nr_ble_ll_ctrl_sca_req_rsp_make = 0x40000f20;\nr_ble_ll_ctrl_start_enc_send = 0x40000f24;\nr_ble_ll_ctrl_start_rsp_timer = 0x40000f28;\nr_ble_ll_ctrl_terminate_start = 0x40000f2c;\nr_ble_ll_ctrl_tx_done = 0x40000f30;\nr_ble_ll_ctrl_update_features = 0x40000f34;\nr_ble_ll_ctrl_version_ind_make = 0x40000f38;\nr_ble_ll_data_buffer_overflow = 0x40000f3c;\nr_ble_ll_deinit = 0x40000f40;\nr_ble_ll_disconn_comp_event_send = 0x40000f44;\nr_ble_ll_env_init = 0x40000f48;\nr_ble_ll_event_comp_pkts = 0x40000f4c;\nr_ble_ll_event_dbuf_overflow = 0x40000f50;\nr_ble_ll_event_send = 0x40000f54;\nr_ble_ll_event_tx_pkt = 0x40000f58;\nr_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40000f5c;\nr_ble_ll_ext_conn_create = 0x40000f60;\nr_ble_ll_ext_scan_parse_adv_info = 0x40000f64;\nr_ble_ll_ext_scan_parse_aux_ptr = 0x40000f68;\nr_ble_ll_flush_pkt_queue = 0x40000f6c;\nr_ble_ll_generate_dh_key_v1 = 0x40000f70;\nr_ble_ll_generate_dh_key_v2 = 0x40000f74;\nr_ble_ll_generic_data_init = 0x40000f78;\nr_ble_ll_get_addr_type = 0x40000f7c;\nr_ble_ll_get_chan_to_scan = 0x40000f80;\nr_ble_ll_get_our_devaddr = 0x40000f84;\nr_ble_ll_get_tx_pwr_compensation = 0x40000f88;\nr_ble_ll_hci_acl_rx = 0x40000f8c;\nr_ble_ll_hci_adv_mode_ext = 0x40000f90;\nr_ble_ll_hci_adv_set_enable = 0x40000f94;\nr_ble_ll_hci_cb_host_buf_size = 0x40000f98;\nr_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x40000f9c;\nr_ble_ll_hci_cb_set_event_mask = 0x40000fa0;\nr_ble_ll_hci_cb_set_event_mask2 = 0x40000fa4;\nr_ble_ll_hci_chk_phy_masks = 0x40000fa8;\nr_ble_ll_hci_cmd_proc = 0x40000fac;\nr_ble_ll_hci_cmd_rx = 0x40000fb0;\nr_ble_ll_hci_ctlr_bb_cmd_proc = 0x40000fb4;\nr_ble_ll_hci_deinit = 0x40000fb8;\nr_ble_ll_hci_disconnect = 0x40000fbc;\nr_ble_ll_hci_env_init = 0x40000fc0;\nr_ble_ll_hci_ev_conn_update = 0x40000fc4;\nr_ble_ll_hci_ev_databuf_overflow = 0x40000fc8;\nr_ble_ll_hci_ev_datalen_chg = 0x40000fcc;\nr_ble_ll_hci_ev_encrypt_chg = 0x40000fd0;\nr_ble_ll_hci_ev_hw_err = 0x40000fd4;\nr_ble_ll_hci_ev_le_csa = 0x40000fd8;\nr_ble_ll_hci_ev_ltk_req = 0x40000fdc;\nr_ble_ll_hci_ev_phy_update = 0x40000fe0;\nr_ble_ll_hci_ev_rd_rem_used_feat = 0x40000fe4;\nr_ble_ll_hci_ev_rd_rem_ver = 0x40000fe8;\nr_ble_ll_hci_ev_rem_conn_parm_req = 0x40000fec;\nr_ble_ll_hci_ev_sca_update = 0x40000ff0;\nr_ble_ll_hci_ev_send_adv_set_terminated = 0x40000ff4;\nr_ble_ll_hci_ev_send_scan_req_recv = 0x40000ff8;\nr_ble_ll_hci_ev_send_scan_timeout = 0x40000ffc;\nr_ble_ll_hci_ev_send_vendor_err = 0x40001000;\nr_ble_ll_hci_event_send = 0x40001004;\nr_ble_ll_hci_ext_scan_set_enable = 0x40001008;\nr_ble_ll_hci_get_num_cmd_pkts = 0x4000100c;\nr_ble_ll_hci_info_params_cmd_proc = 0x40001010;\nr_ble_ll_hci_init = 0x40001014;\nr_ble_ll_hci_init_support_cmd_base_on_lmp_ver = 0x40001018;\nr_ble_ll_hci_is_event_enabled = 0x4000101c;\nr_ble_ll_hci_is_le_event_enabled = 0x40001020;\nr_ble_ll_hci_le_cmd_proc = 0x40001024;\nr_ble_ll_hci_le_cmd_send_cmd_status = 0x40001028;\nr_ble_ll_hci_le_encrypt = 0x4000102c;\nr_ble_ll_hci_le_rand = 0x40001030;\nr_ble_ll_hci_le_rd_max_data_len = 0x40001034;\nr_ble_ll_hci_le_rd_sugg_data_len = 0x40001038;\nr_ble_ll_hci_le_read_bufsize = 0x4000103c;\nr_ble_ll_hci_le_read_local_features = 0x40001040;\nr_ble_ll_hci_le_read_supp_states = 0x40001044;\nr_ble_ll_hci_le_set_def_phy = 0x40001048;\nr_ble_ll_hci_le_wr_sugg_data_len = 0x4000104c;\nr_ble_ll_hci_link_ctrl_cmd_proc = 0x40001050;\nr_ble_ll_hci_npl_init = 0x40001054;\nr_ble_ll_hci_post_gen_dhkey_cmp_evt = 0x40001058;\nr_ble_ll_hci_post_rd_p256_pubkey_cmp_evt = 0x4000105c;\nr_ble_ll_hci_rd_bd_addr = 0x40001060;\nr_ble_ll_hci_rd_local_supp_cmd = 0x40001064;\nr_ble_ll_hci_rd_local_supp_feat = 0x40001068;\nr_ble_ll_hci_rd_local_version = 0x4000106c;\nr_ble_ll_hci_scan_set_enable = 0x40001070;\nr_ble_ll_hci_send_adv_report = 0x40001074;\nr_ble_ll_hci_send_dir_adv_report = 0x40001078;\nr_ble_ll_hci_send_ext_adv_report = 0x4000107c;\nr_ble_ll_hci_send_legacy_ext_adv_report = 0x40001080;\nr_ble_ll_hci_send_noop = 0x40001084;\nr_ble_ll_hci_set_adv_data = 0x40001088;\nr_ble_ll_hci_set_le_event_mask = 0x4000108c;\nr_ble_ll_hci_set_scan_rsp_data = 0x40001090;\nr_ble_ll_hci_status_params_cmd_proc = 0x40001094;\nr_ble_ll_hci_vs_cmd_proc = 0x40001098;\nr_ble_ll_hci_vs_rd_static_addr = 0x4000109c;\nr_ble_ll_hw_err_timer_cb = 0x400010a0;\nr_ble_ll_hw_error = 0x400010a4;\nr_ble_ll_init = 0x400010a8;\nr_ble_ll_init_alloc_conn_comp_ev = 0x400010ac;\nr_ble_ll_init_get_conn_comp_ev = 0x400010b0;\nr_ble_ll_init_rx_pkt_in = 0x400010b4;\nr_ble_ll_is_addr_empty = 0x400010b8;\nr_ble_ll_is_controller_busy = 0x400010bc;\nr_ble_ll_is_on_resolv_list = 0x400010c0;\nr_ble_ll_is_our_devaddr = 0x400010c4;\nr_ble_ll_is_rpa = 0x400010c8;\nr_ble_ll_is_valid_adv_mode = 0x400010cc;\nr_ble_ll_is_valid_own_addr_type = 0x400010d0;\nr_ble_ll_is_valid_public_addr = 0x400010d4;\nr_ble_ll_is_valid_random_addr = 0x400010d8;\nr_ble_ll_mbuf_init = 0x400010dc;\nr_ble_ll_misc_options_set = 0x400010e0;\nr_ble_ll_modify_sca = 0x400010e4;\nr_ble_ll_modify_sca_action = 0x400010e8;\nr_ble_ll_pdu_max_tx_octets_get = 0x400010ec;\nr_ble_ll_pdu_tx_time_get = 0x400010f0;\nr_ble_ll_phy_to_phy_mode = 0x400010f4;\nr_ble_ll_qa_enable = 0x400010f8;\nr_ble_ll_rand = 0x400010fc;\nr_ble_ll_rand_data_get = 0x40001100;\nr_ble_ll_rand_deinit = 0x40001104;\nr_ble_ll_rand_env_init = 0x40001108;\nr_ble_ll_rand_init = 0x4000110c;\nr_ble_ll_rand_prand_get = 0x40001110;\nr_ble_ll_rand_sample = 0x40001114;\nr_ble_ll_rand_start = 0x40001118;\nr_ble_ll_read_local_p256_pub_key = 0x4000111c;\nr_ble_ll_read_rf_path_compensation = 0x40001120;\nr_ble_ll_read_supp_features = 0x40001124;\nr_ble_ll_read_supp_states = 0x40001128;\nr_ble_ll_read_tx_power = 0x4000112c;\nr_ble_ll_reset = 0x40001130;\nr_ble_ll_resolv_clear_all_pl_bit = 0x40001134;\nr_ble_ll_resolv_clear_all_wl_bit = 0x40001138;\nr_ble_ll_resolv_deinit = 0x4000113c;\nr_ble_ll_resolv_enable_cmd = 0x40001140;\nr_ble_ll_resolv_enabled = 0x40001144;\nr_ble_ll_resolv_env_init = 0x40001148;\nr_ble_ll_resolv_gen_priv_addr = 0x4000114c;\nr_ble_ll_resolv_gen_rpa = 0x40001150;\nr_ble_ll_resolv_get_addr_pointer = 0x40001154;\nr_ble_ll_resolv_get_index = 0x40001158;\nr_ble_ll_resolv_get_irk_pointer = 0x4000115c;\nr_ble_ll_resolv_get_list = 0x40001160;\nr_ble_ll_resolv_get_priv_addr = 0x40001164;\nr_ble_ll_resolv_get_rpa_tmo = 0x40001168;\nr_ble_ll_resolv_init = 0x4000116c;\nr_ble_ll_resolv_irk_nonzero = 0x40001170;\nr_ble_ll_resolv_list_add = 0x40001174;\nr_ble_ll_resolv_list_chg_allowed = 0x40001178;\nr_ble_ll_resolv_list_clr = 0x4000117c;\nr_ble_ll_resolv_list_find = 0x40001180;\nr_ble_ll_resolv_list_read_size = 0x40001184;\nr_ble_ll_resolv_list_reset = 0x40001188;\nr_ble_ll_resolv_list_rmv = 0x4000118c;\nr_ble_ll_resolv_local_addr_rd = 0x40001190;\nr_ble_ll_resolv_peer_addr_rd = 0x40001194;\nr_ble_ll_resolv_peer_rpa_any = 0x40001198;\nr_ble_ll_resolv_reset = 0x4000119c;\nr_ble_ll_resolv_rpa = 0x400011a0;\nr_ble_ll_resolv_rpa_timer_cb = 0x400011a4;\nr_ble_ll_resolv_set_local_rpa = 0x400011a8;\nr_ble_ll_resolv_set_peer_rpa = 0x400011ac;\nr_ble_ll_resolv_set_rpa_tmo = 0x400011b0;\nr_ble_ll_resolve_set_priv_mode = 0x400011b4;\nr_ble_ll_rxpdu_alloc = 0x400011b8;\nr_ble_ll_scan_add_scan_rsp_adv = 0x400011bc;\nr_ble_ll_scan_adv_decode_addr = 0x400011c0;\nr_ble_ll_scan_aux_data_ref = 0x400011c4;\nr_ble_ll_scan_aux_data_unref = 0x400011c8;\nr_ble_ll_scan_can_chg_whitelist = 0x400011cc;\nr_ble_ll_scan_check_periodic_sync = 0x400011d0;\nr_ble_ll_scan_classify_filter_aux_init = 0x400011d4;\nr_ble_ll_scan_classify_filter_init = 0x400011d8;\nr_ble_ll_scan_common_init = 0x400011dc;\nr_ble_ll_scan_continue_en = 0x400011e0;\nr_ble_ll_scan_deinit = 0x400011e4;\nr_ble_ll_scan_dup_check_ext = 0x400011e8;\nr_ble_ll_scan_dup_check_legacy = 0x400011ec;\nr_ble_ll_scan_dup_move_to_head = 0x400011f0;\nr_ble_ll_scan_dup_new = 0x400011f4;\nr_ble_ll_scan_dup_update_ext = 0x400011f8;\nr_ble_ll_scan_dup_update_legacy = 0x400011fc;\nr_ble_ll_scan_enabled = 0x40001200;\nr_ble_ll_scan_end_adv_evt = 0x40001204;\nr_ble_ll_scan_env_init = 0x40001208;\nr_ble_ll_scan_ext_initiator_start = 0x4000120c;\nr_ble_ll_scan_get_addr_data_from_legacy = 0x40001210;\nr_ble_ll_scan_get_addr_from_ext_adv = 0x40001214;\nr_ble_ll_scan_get_cur_sm = 0x40001218;\nr_ble_ll_scan_get_ext_adv_report = 0x4000121c;\nr_ble_ll_scan_get_local_rpa = 0x40001220;\nr_ble_ll_scan_get_next_adv_prim_chan = 0x40001224;\nr_ble_ll_scan_get_peer_rpa = 0x40001228;\nr_ble_ll_scan_have_rxd_scan_rsp = 0x4000122c;\nr_ble_ll_scan_init = 0x40001230;\nr_ble_ll_scan_initiator_start = 0x40001234;\nr_ble_ll_scan_is_inside_window = 0x40001238;\nr_ble_ll_scan_move_window_to = 0x4000123c;\nr_ble_ll_scan_npl_reset = 0x40001240;\nr_ble_ll_scan_parse_auxptr = 0x40001244;\nr_ble_ll_scan_parse_ext_hdr = 0x40001248;\nr_ble_ll_scan_pre_process = 0x4000124c;\nr_ble_ll_scan_record_new_adv = 0x40001250;\nr_ble_ll_scan_refresh_nrpa = 0x40001254;\nr_ble_ll_scan_reset = 0x40001258;\nr_ble_ll_scan_rx_pkt_in = 0x4000125c;\nr_ble_ll_scan_rx_pkt_in_on_aux = 0x40001260;\nr_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001264;\nr_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268;\nr_ble_ll_scan_rxed = 0x4000126c;\nr_ble_ll_scan_send_adv_report = 0x40001270;\nr_ble_ll_scan_send_truncated = 0x40001274;\nr_ble_ll_scan_set_enable = 0x40001278;\nr_ble_ll_scan_set_peer_rpa = 0x4000127c;\nr_ble_ll_scan_set_perfer_addr = 0x40001280;\nr_ble_ll_scan_set_scan_params = 0x40001284;\nr_ble_ll_scan_sm_start = 0x40001288;\nr_ble_ll_scan_sm_stop = 0x4000128c;\nr_ble_ll_scan_time_hci_to_ticks = 0x40001290;\nr_ble_ll_scan_update_aux_data = 0x40001294;\nr_ble_ll_scan_whitelist_enabled = 0x40001298;\nr_ble_ll_set_default_privacy_mode = 0x4000129c;\nr_ble_ll_set_default_sync_transfer_params = 0x400012a0;\nr_ble_ll_set_ext_scan_params = 0x400012a4;\nr_ble_ll_set_host_feat = 0x400012a8;\nr_ble_ll_set_public_addr = 0x400012ac;\nr_ble_ll_set_random_addr = 0x400012b0;\nr_ble_ll_set_sync_transfer_params = 0x400012b4;\nr_ble_ll_state_get = 0x400012b8;\nr_ble_ll_state_set = 0x400012bc;\nr_ble_ll_sync_adjust_ext_hdr = 0x400012c0;\nr_ble_ll_sync_cancel = 0x400012c4;\nr_ble_ll_sync_cancel_complete_event = 0x400012c8;\nr_ble_ll_sync_check_acad = 0x400012cc;\nr_ble_ll_sync_check_failed = 0x400012d0;\nr_ble_ll_sync_create = 0x400012d4;\nr_ble_ll_sync_deinit = 0x400012d8;\nr_ble_ll_sync_enabled = 0x400012dc;\nr_ble_ll_sync_env_init = 0x400012e0;\nr_ble_ll_sync_est_event_failed = 0x400012e4;\nr_ble_ll_sync_est_event_success = 0x400012e8;\nr_ble_ll_sync_established = 0x400012ec;\nr_ble_ll_sync_filter_enabled = 0x400012f0;\nr_ble_ll_sync_find = 0x400012f4;\nr_ble_ll_sync_get_cur_sm = 0x400012f8;\nr_ble_ll_sync_get_handle = 0x400012fc;\nr_ble_ll_sync_get_sm = 0x40001300;\nr_ble_ll_sync_info_event = 0x40001304;\nr_ble_ll_sync_init = 0x40001308;\nr_ble_ll_sync_list_add = 0x4000130c;\nr_ble_ll_sync_list_clear = 0x40001310;\nr_ble_ll_sync_list_empty = 0x40001314;\nr_ble_ll_sync_list_get_free = 0x40001318;\nr_ble_ll_sync_list_remove = 0x4000131c;\nr_ble_ll_sync_list_search = 0x40001320;\nr_ble_ll_sync_list_size = 0x40001324;\nr_ble_ll_sync_lost_event = 0x40001328;\nr_ble_ll_sync_next_event = 0x4000132c;\nr_ble_ll_sync_on_list = 0x40001330;\nr_ble_ll_sync_parse_ext_hdr = 0x40001334;\nr_ble_ll_sync_periodic_ind = 0x40001338;\nr_ble_ll_sync_phy_mode_to_aux_phy = 0x4000133c;\nr_ble_ll_sync_phy_mode_to_hci = 0x40001340;\nr_ble_ll_sync_put_syncinfo = 0x40001344;\nr_ble_ll_sync_receive_enable = 0x40001348;\nr_ble_ll_sync_reserve = 0x4000134c;\nr_ble_ll_sync_reset = 0x40001350;\nr_ble_ll_sync_reset_sm = 0x40001354;\nr_ble_ll_sync_rx_pkt_in = 0x40001358;\nr_ble_ll_sync_send_per_adv_rpt = 0x4000135c;\nr_ble_ll_sync_send_sync_ind = 0x40001360;\nr_ble_ll_sync_send_truncated_per_adv_rpt = 0x40001364;\nr_ble_ll_sync_sm_clear = 0x40001368;\nr_ble_ll_sync_terminate = 0x4000136c;\nr_ble_ll_sync_transfer = 0x40001370;\nr_ble_ll_sync_transfer_get = 0x40001374;\nr_ble_ll_sync_transfer_received = 0x40001378;\nr_ble_ll_task = 0x4000137c;\nr_ble_ll_trace_set_func = 0x40001380;\nr_ble_ll_trace_u32 = 0x40001384;\nr_ble_ll_trace_u32x2 = 0x40001388;\nr_ble_ll_trace_u32x3 = 0x4000138c;\nr_ble_ll_tx_flat_mbuf_pducb = 0x40001390;\nr_ble_ll_tx_mbuf_pducb = 0x40001394;\nr_ble_ll_tx_pkt_in = 0x40001398;\nr_ble_ll_update_max_tx_octets_phy_mode = 0x4000139c;\nr_ble_ll_usecs_to_ticks_round_up = 0x400013a0;\nr_ble_ll_utils_calc_access_addr = 0x400013a4;\nr_ble_ll_utils_calc_dci_csa2 = 0x400013a8;\nr_ble_ll_utils_calc_num_used_chans = 0x400013ac;\nr_ble_ll_utils_calc_window_widening = 0x400013b0;\nr_ble_ll_utils_csa2_perm = 0x400013b4;\nr_ble_ll_utils_csa2_prng = 0x400013b8;\nr_ble_ll_utils_remapped_channel = 0x400013bc;\nr_ble_ll_whitelist_add = 0x400013c0;\nr_ble_ll_whitelist_chg_allowed = 0x400013c4;\nr_ble_ll_whitelist_clear = 0x400013c8;\nr_ble_ll_whitelist_read_size = 0x400013cc;\nr_ble_ll_whitelist_rmv = 0x400013d0;\nr_ble_ll_whitelist_search = 0x400013d4;\nr_ble_ll_write_rf_path_compensation = 0x400013d8;\nr_ble_lll_adv_aux_scannable_pdu_payload_len = 0x400013dc;\nr_ble_lll_adv_aux_schedule = 0x400013e0;\nr_ble_lll_adv_aux_schedule_first = 0x400013e4;\nr_ble_lll_adv_aux_schedule_next = 0x400013e8;\nr_ble_lll_adv_aux_scheduled = 0x400013ec;\nr_ble_lll_adv_aux_set_start_time = 0x400013f0;\nr_ble_lll_adv_coex_dpc_calc_pti_update_itvl = 0x400013f4;\nr_ble_lll_adv_coex_dpc_process_pri = 0x400013f8;\nr_ble_lll_adv_coex_dpc_process_sec = 0x400013fc;\nr_ble_lll_adv_coex_dpc_pti_get = 0x40001400;\nr_ble_lll_adv_coex_dpc_update = 0x40001404;\nr_ble_lll_adv_coex_dpc_update_on_adv_start = 0x40001408;\nr_ble_lll_adv_coex_dpc_update_on_aux_scheduled = 0x4000140c;\nr_ble_lll_adv_coex_dpc_update_on_data_updated = 0x40001410;\nr_ble_lll_adv_coex_dpc_update_on_event_end = 0x40001414;\nr_ble_lll_adv_coex_dpc_update_on_event_scheduled = 0x40001418;\nr_ble_lll_adv_done = 0x4000141c;\nr_ble_lll_adv_drop_event = 0x40001420;\nr_ble_lll_adv_event_done = 0x40001424;\nr_ble_lll_adv_event_rmvd_from_sched = 0x40001428;\nr_ble_lll_adv_ext_estimate_data_itvl = 0x4000142c;\nr_ble_lll_adv_get_sec_pdu_len = 0x40001430;\nr_ble_lll_adv_halt = 0x40001434;\nr_ble_lll_adv_make_done = 0x40001438;\nr_ble_lll_adv_periodic_done = 0x4000143c;\nr_ble_lll_adv_periodic_event_done = 0x40001440;\nr_ble_lll_adv_periodic_rmvd_from_sched = 0x40001444;\nr_ble_lll_adv_periodic_schedule_first = 0x40001448;\nr_ble_lll_adv_periodic_schedule_next = 0x4000144c;\nr_ble_lll_adv_periodic_start = 0x40001450;\nr_ble_lll_adv_periodic_stop = 0x40001454;\nr_ble_lll_adv_pri_schedule_tx_pdu = 0x40001458;\nr_ble_lll_adv_reschedule_event = 0x4000145c;\nr_ble_lll_adv_reschedule_periodic_event = 0x40001460;\nr_ble_lll_adv_rx_pkt_isr = 0x40001464;\nr_ble_lll_adv_sec_done = 0x40001468;\nr_ble_lll_adv_sec_event_done = 0x4000146c;\nr_ble_lll_adv_sec_schedule_next_aux = 0x40001470;\nr_ble_lll_adv_secondary_tx_start_cb = 0x40001474;\nr_ble_lll_adv_sm_deinit = 0x40001478;\nr_ble_lll_adv_sm_event_init = 0x4000147c;\nr_ble_lll_adv_sm_event_restore = 0x40001480;\nr_ble_lll_adv_sm_event_store = 0x40001484;\nr_ble_lll_adv_sm_init = 0x40001488;\nr_ble_lll_adv_sm_reset = 0x4000148c;\nr_ble_lll_adv_start = 0x40001490;\nr_ble_lll_adv_stop = 0x40001494;\nr_ble_lll_adv_sync_next_scheduled = 0x40001498;\nr_ble_lll_adv_sync_schedule = 0x4000149c;\nr_ble_lll_adv_sync_tx_done = 0x400014a0;\nr_ble_lll_adv_sync_tx_end = 0x400014a4;\nr_ble_lll_adv_sync_tx_start_cb = 0x400014a8;\nr_ble_lll_adv_tx_done = 0x400014ac;\nr_ble_lll_adv_tx_start_cb = 0x400014b0;\nr_ble_lll_adv_update_rsp_offset = 0x400014b4;\nr_ble_lll_aux_scan_cb = 0x400014b8;\nr_ble_lll_aux_scan_drop = 0x400014bc;\nr_ble_lll_aux_scan_drop_event_cb = 0x400014c0;\nr_ble_lll_calc_us_convert_tick_unit = 0x400014c4;\nr_ble_lll_conn_append_tx_buffer = 0x400014c8;\nr_ble_lll_conn_can_send_next_pdu = 0x400014cc;\nr_ble_lll_conn_check_opcode_matched = 0x400014d0;\nr_ble_lll_conn_coex_dpc_process = 0x400014d4;\nr_ble_lll_conn_coex_dpc_pti_get = 0x400014d8;\nr_ble_lll_conn_coex_dpc_update = 0x400014dc;\nr_ble_lll_conn_coex_dpc_update_on_event_end = 0x400014e0;\nr_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4;\nr_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8;\nr_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec;\nr_ble_lll_conn_cth_flow_free_credit = 0x400014f0;\nr_ble_lll_conn_current_sm_over = 0x400014f4;\nr_ble_lll_conn_end = 0x400014f8;\nr_ble_lll_conn_env_deinit = 0x400014fc;\nr_ble_lll_conn_env_init = 0x40001500;\nr_ble_lll_conn_event_end = 0x40001504;\nr_ble_lll_conn_event_end_timer_cb = 0x40001508;\nr_ble_lll_conn_event_halt = 0x4000150c;\nr_ble_lll_conn_event_is_over = 0x40001510;\nr_ble_lll_conn_event_start_cb = 0x40001514;\nr_ble_lll_conn_free_rx_mbuf = 0x40001518;\nr_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c;\nr_ble_lll_conn_get_ce_end_time = 0x40001520;\nr_ble_lll_conn_get_next_sched_time = 0x40001524;\nr_ble_lll_conn_get_rx_mbuf = 0x40001528;\nr_ble_lll_conn_halt = 0x4000152c;\nr_ble_lll_conn_master_common_init = 0x40001530;\nr_ble_lll_conn_master_new = 0x40001534;\nr_ble_lll_conn_module_deinit = 0x40001538;\nr_ble_lll_conn_module_init = 0x4000153c;\nr_ble_lll_conn_module_reset = 0x40001540;\nr_ble_lll_conn_no_mem_evt_pre_cb = 0x40001544;\nr_ble_lll_conn_pre_process = 0x40001548;\nr_ble_lll_conn_process_acked_pdu = 0x4000154c;\nr_ble_lll_conn_process_in_isr = 0x40001550;\nr_ble_lll_conn_recv_ack = 0x40001554;\nr_ble_lll_conn_recv_valid_packet = 0x40001558;\nr_ble_lll_conn_reset_pending_sched = 0x4000155c;\nr_ble_lll_conn_rx_pkt_isr = 0x40001560;\nr_ble_lll_conn_sched_next_anchor = 0x40001564;\nr_ble_lll_conn_sched_next_event = 0x40001568;\nr_ble_lll_conn_set_slave_flow_control = 0x4000156c;\nr_ble_lll_conn_slave_new = 0x40001570;\nr_ble_lll_conn_sm_new = 0x40001574;\nr_ble_lll_conn_sm_npl_deinit = 0x40001578;\nr_ble_lll_conn_sm_npl_init = 0x4000157c;\nr_ble_lll_conn_superversion_timer_cb = 0x40001580;\nr_ble_lll_conn_timeout = 0x40001584;\nr_ble_lll_conn_update_anchor = 0x40001588;\nr_ble_lll_conn_update_conn_ind_params = 0x4000158c;\nr_ble_lll_conn_update_encryption = 0x40001590;\nr_ble_lll_conn_update_tx_buffer = 0x40001594;\nr_ble_lll_deinit = 0x40001598;\nr_ble_lll_dtm_calculate_itvl = 0x4000159c;\nr_ble_lll_dtm_ctx_free = 0x400015a0;\nr_ble_lll_dtm_deinit = 0x400015a4;\nr_ble_lll_dtm_end_test = 0x400015a8;\nr_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;\nr_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;\nr_ble_lll_dtm_init = 0x400015b4;\nr_ble_lll_dtm_reset = 0x400015b8;\nr_ble_lll_dtm_rx_create_ctx = 0x400015bc;\nr_ble_lll_dtm_rx_isr_end = 0x400015c0;\nr_ble_lll_dtm_rx_isr_start = 0x400015c4;\nr_ble_lll_dtm_rx_pkt_in = 0x400015c8;\nr_ble_lll_dtm_rx_sched_cb = 0x400015cc;\nr_ble_lll_dtm_rx_start = 0x400015d0;\nr_ble_lll_dtm_rx_test = 0x400015d4;\nr_ble_lll_dtm_set_next = 0x400015d8;\nr_ble_lll_dtm_tx_create_ctx = 0x400015dc;\nr_ble_lll_dtm_tx_done = 0x400015e0;\nr_ble_lll_dtm_tx_sched_cb = 0x400015e4;\nr_ble_lll_dtm_tx_test = 0x400015e8;\nr_ble_lll_dtm_wfr_timer_exp = 0x400015ec;\nr_ble_lll_event_rx_pkt = 0x400015f0;\nr_ble_lll_ext_scan_coex_dpc_process = 0x400015f4;\nr_ble_lll_ext_scan_coex_dpc_pti_get = 0x400015f8;\nr_ble_lll_ext_scan_coex_dpc_update = 0x400015fc;\nr_ble_lll_ext_scan_coex_dpc_update_on_start = 0x40001600;\nr_ble_lll_hci_dtm_rx_test = 0x40001604;\nr_ble_lll_hci_dtm_rx_test_v2 = 0x40001608;\nr_ble_lll_hci_dtm_tx_test = 0x4000160c;\nr_ble_lll_hci_dtm_tx_test_ext = 0x40001610;\nr_ble_lll_hci_dtm_tx_test_v2 = 0x40001614;\nr_ble_lll_hci_dtm_tx_test_v2_ext = 0x40001618;\nr_ble_lll_init = 0x4000161c;\nr_ble_lll_init_pre_process = 0x40001620;\nr_ble_lll_init_rx_pkt_isr = 0x40001624;\nr_ble_lll_per_adv_coex_dpc_calc_pti_update_itvl = 0x40001628;\nr_ble_lll_per_adv_coex_dpc_process = 0x4000162c;\nr_ble_lll_per_adv_coex_dpc_pti_get = 0x40001630;\nr_ble_lll_per_adv_coex_dpc_update = 0x40001634;\nr_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638;\nr_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c;\nr_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640;\nr_ble_lll_reset = 0x40001644;\nr_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;\nr_ble_lll_rfmgmt_deinit = 0x4000164c;\nr_ble_lll_rfmgmt_disable = 0x40001650;\nr_ble_lll_rfmgmt_enable = 0x40001654;\nr_ble_lll_rfmgmt_enable_now = 0x40001658;\nr_ble_lll_rfmgmt_init = 0x4000165c;\nr_ble_lll_rfmgmt_is_enabled = 0x40001660;\nr_ble_lll_rfmgmt_release = 0x40001664;\nr_ble_lll_rfmgmt_release_ev = 0x40001668;\nr_ble_lll_rfmgmt_reset = 0x4000166c;\nr_ble_lll_rfmgmt_scan_changed = 0x40001670;\nr_ble_lll_rfmgmt_sched_changed = 0x40001674;\nr_ble_lll_rfmgmt_set_sleep_cb = 0x40001678;\nr_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c;\nr_ble_lll_rfmgmt_timer_exp = 0x40001680;\nr_ble_lll_rfmgmt_timer_reschedule = 0x40001684;\nr_ble_lll_rx_pdu_in = 0x40001688;\nr_ble_lll_rx_pkt_in = 0x4000168c;\nr_ble_lll_rx_pkt_isr = 0x40001690;\nr_ble_lll_scan_abort_aux_sched = 0x40001694;\nr_ble_lll_scan_aux_data_free = 0x40001698;\nr_ble_lll_scan_chk_resume = 0x4000169c;\nr_ble_lll_scan_clean_cur_aux_data = 0x400016a0;\nr_ble_lll_scan_coex_event_cb = 0x400016a4;\nr_ble_lll_scan_common_init = 0x400016a8;\nr_ble_lll_scan_deinit = 0x400016ac;\nr_ble_lll_scan_duration_period_timers_restart = 0x400016b0;\nr_ble_lll_scan_duration_period_timers_stop = 0x400016b4;\nr_ble_lll_scan_duration_timer_cb = 0x400016b8;\nr_ble_lll_scan_event_proc = 0x400016bc;\nr_ble_lll_scan_ext_adv_init = 0x400016c0;\nr_ble_lll_scan_halt = 0x400016c4;\nr_ble_lll_scan_has_sent_scan_req = 0x400016c8;\nr_ble_lll_scan_init = 0x400016cc;\nr_ble_lll_scan_npl_init = 0x400016d0;\nr_ble_lll_scan_npl_reset = 0x400016d4;\nr_ble_lll_scan_npl_restore = 0x400016d8;\nr_ble_lll_scan_npl_store = 0x400016dc;\nr_ble_lll_scan_period_timer_cb = 0x400016e0;\nr_ble_lll_scan_process_adv_in_isr = 0x400016e4;\nr_ble_lll_scan_process_rsp_in_isr = 0x400016e8;\nr_ble_lll_scan_req_backoff = 0x400016ec;\nr_ble_lll_scan_restart = 0x400016f0;\nr_ble_lll_scan_rx_isr_on_aux = 0x400016f4;\nr_ble_lll_scan_rx_isr_on_legacy = 0x400016f8;\nr_ble_lll_scan_rx_pkt_isr = 0x400016fc;\nr_ble_lll_scan_sched_next_aux = 0x40001700;\nr_ble_lll_scan_sched_remove = 0x40001704;\nr_ble_lll_scan_start = 0x40001708;\nr_ble_lll_scan_start_rx = 0x4000170c;\nr_ble_lll_scan_stop = 0x40001710;\nr_ble_lll_scan_targeta_is_matched = 0x40001714;\nr_ble_lll_scan_timer_cb = 0x40001718;\nr_ble_lll_sched_adv_new = 0x4000171c;\nr_ble_lll_sched_adv_resched_pdu = 0x40001720;\nr_ble_lll_sched_adv_reschedule = 0x40001724;\nr_ble_lll_sched_aux_scan = 0x40001728;\nr_ble_lll_sched_conn_overlap = 0x4000172c;\nr_ble_lll_sched_conn_reschedule = 0x40001730;\nr_ble_lll_sched_deinit = 0x40001734;\nr_ble_lll_sched_dtm = 0x40001738;\nr_ble_lll_sched_env_init = 0x4000173c;\nr_ble_lll_sched_execute_check = 0x40001740;\nr_ble_lll_sched_execute_item = 0x40001744;\nr_ble_lll_sched_init = 0x40001748;\nr_ble_lll_sched_insert_if_empty = 0x4000174c;\nr_ble_lll_sched_is_overlap = 0x40001750;\nr_ble_lll_sched_master_new = 0x40001754;\nr_ble_lll_sched_next_time = 0x40001758;\nr_ble_lll_sched_overlaps_current = 0x4000175c;\nr_ble_lll_sched_periodic_adv = 0x40001760;\nr_ble_lll_sched_rmv_elem = 0x40001764;\nr_ble_lll_sched_rmv_elem_type = 0x40001768;\nr_ble_lll_sched_run = 0x4000176c;\nr_ble_lll_sched_scan_req_over_aux_ptr = 0x40001770;\nr_ble_lll_sched_slave_new = 0x40001774;\nr_ble_lll_sched_stop = 0x40001778;\nr_ble_lll_sched_sync = 0x4000177c;\nr_ble_lll_sched_sync_overlaps_current = 0x40001780;\nr_ble_lll_sched_sync_reschedule = 0x40001784;\nr_ble_lll_sync_chain_start_cb = 0x40001788;\nr_ble_lll_sync_coex_dpc_process = 0x4000178c;\nr_ble_lll_sync_coex_dpc_pti_get = 0x40001790;\nr_ble_lll_sync_coex_dpc_update = 0x40001794;\nr_ble_lll_sync_current_sm_over = 0x40001798;\nr_ble_lll_sync_deinit = 0x4000179c;\nr_ble_lll_sync_event_end = 0x400017a0;\nr_ble_lll_sync_event_end_cb = 0x400017a4;\nr_ble_lll_sync_event_start_cb = 0x400017a8;\nr_ble_lll_sync_get_event_end_time = 0x400017ac;\nr_ble_lll_sync_halt = 0x400017b0;\nr_ble_lll_sync_init = 0x400017b4;\nr_ble_lll_sync_new = 0x400017b8;\nr_ble_lll_sync_reset = 0x400017bc;\nr_ble_lll_sync_reset_sm = 0x400017c0;\nr_ble_lll_sync_rmvd_from_sched = 0x400017c4;\nr_ble_lll_sync_rx_pkt_isr = 0x400017c8;\nr_ble_lll_sync_schedule_chain = 0x400017cc;\nr_ble_lll_sync_stop = 0x400017d0;\nr_ble_lll_sync_trnasfer_sched = 0x400017d4;\nr_ble_phy_access_addr_get = 0x400017d8;\nr_ble_phy_calculate_rxtx_ifs = 0x400017dc;\nr_ble_phy_calculate_rxwindow = 0x400017e0;\nr_ble_phy_calculate_txrx_ifs = 0x400017e4;\nr_ble_phy_check_bb_status = 0x400017e8;\nr_ble_phy_complete_rx_info = 0x400017ec;\nr_ble_phy_config_access_addr = 0x400017f0;\nr_ble_phy_data_make = 0x400017f4;\nr_ble_phy_disable = 0x400017f8;\nr_ble_phy_disable_irq = 0x400017fc;\nr_ble_phy_disable_whitening = 0x40001800;\nr_ble_phy_enable_whitening = 0x40001804;\nr_ble_phy_encrypt_disable = 0x40001808;\nr_ble_phy_env_init = 0x4000180c;\nr_ble_phy_get_current_phy = 0x40001810;\nr_ble_phy_get_packet_counter = 0x40001814;\nr_ble_phy_get_packet_status = 0x40001818;\nr_ble_phy_get_pyld_time_offset = 0x4000181c;\nr_ble_phy_get_rx_phy_mode = 0x40001820;\nr_ble_phy_get_seq_end_st = 0x40001824;\nr_ble_phy_init = 0x40001828;\nr_ble_phy_isr = 0x4000182c;\nr_ble_phy_max_data_pdu_pyld = 0x40001830;\nr_ble_phy_mode_config = 0x40001834;\nr_ble_phy_mode_convert = 0x40001838;\nr_ble_phy_mode_write = 0x4000183c;\nr_ble_phy_module_deinit = 0x40001840;\nr_ble_phy_module_init = 0x40001844;\nr_ble_phy_monitor_bb_sync = 0x40001848;\nr_ble_phy_reset_bb_monitor = 0x4000184c;\nr_ble_phy_resolv_list_disable = 0x40001850;\nr_ble_phy_resolv_list_enable = 0x40001854;\nr_ble_phy_restart_sequence = 0x40001858;\nr_ble_phy_rx_set_start_time_forcibly = 0x4000185c;\nr_ble_phy_rxpdu_copy = 0x40001860;\nr_ble_phy_seq_encrypt_enable = 0x40001864;\nr_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001868;\nr_ble_phy_sequence_end_isr = 0x4000186c;\nr_ble_phy_sequence_get_mode = 0x40001870;\nr_ble_phy_sequence_is_running = 0x40001874;\nr_ble_phy_sequence_is_waiting_rsp = 0x40001878;\nr_ble_phy_sequence_single_end = 0x4000187c;\nr_ble_phy_sequence_tx_end_invoke = 0x40001880;\nr_ble_phy_sequence_update_conn_ind_params = 0x40001884;\nr_ble_phy_set_adv_mode = 0x40001888;\nr_ble_phy_set_coex_pti = 0x4000188c;\nr_ble_phy_set_conn_ind_pdu = 0x40001890;\nr_ble_phy_set_conn_mode = 0x40001894;\nr_ble_phy_set_dev_address = 0x40001898;\nr_ble_phy_set_rx_pwr_compensation = 0x4000189c;\nr_ble_phy_set_rxhdr = 0x400018a0;\nr_ble_phy_set_scan_mode = 0x400018a4;\nr_ble_phy_set_sequence_mode = 0x400018a8;\nr_ble_phy_set_single_packet_rx_sequence = 0x400018ac;\nr_ble_phy_set_single_packet_tx_sequence = 0x400018b0;\nr_ble_phy_set_tx_rx_transition = 0x400018b4;\nr_ble_phy_set_txend_cb = 0x400018b8;\nr_ble_phy_setchan = 0x400018bc;\nr_ble_phy_start_rx_immediately = 0x400018c0;\nr_ble_phy_state_get = 0x400018c4;\nr_ble_phy_timer_config_start_time = 0x400018c8;\nr_ble_phy_timer_start_now = 0x400018cc;\nr_ble_phy_timer_stop = 0x400018d0;\nr_ble_phy_tx_set_start_time = 0x400018d4;\nr_ble_phy_txpower_round = 0x400018d8;\nr_ble_phy_txpwr_set = 0x400018dc;\nr_ble_phy_update_conn_sequence = 0x400018e0;\nr_ble_phy_update_encryption = 0x400018e4;\nr_ble_phy_update_ifs = 0x400018e8;\nr_ble_phy_xcvr_state_get = 0x400018ec;\nr_ble_plf_set_log_level = 0x400018f0;\nr_ble_rtc_wake_up_cpu_init = 0x400018f4;\nr_ble_rtc_wake_up_state_clr = 0x400018f8;\nr_ble_vendor_hci_register = 0x400018fc;\nr_bt_rf_coex_cfg_set = 0x40001900;\nr_bt_rf_coex_coded_txrx_time_upper_lim = 0x40001904;\nr_bt_rf_coex_dft_pti_set = 0x40001908;\nr_bt_rf_coex_hook_deinit = 0x4000190c;\nr_bt_rf_coex_hook_init = 0x40001910;\nr_bt_rf_coex_hook_st_set = 0x40001914;\nr_bt_rf_coex_hooks_p_set_default = 0x40001918;\nr_btdm_disable_adv_delay = 0x4000191c;\nr_btdm_switch_phy_coded = 0x40001920;\nr_esp_wait_disabled = 0x40001924;\nr_get_be16 = 0x40001928;\nr_get_be24 = 0x4000192c;\nr_get_be32 = 0x40001930;\nr_get_be64 = 0x40001934;\nr_get_le16 = 0x40001938;\nr_get_le24 = 0x4000193c;\nr_get_le32 = 0x40001940;\nr_get_le64 = 0x40001944;\nr_get_local_irk_offset = 0x40001948;\nr_get_local_rpa_offset = 0x4000194c;\nr_get_max_skip = 0x40001950;\nr_get_peer_id_offset = 0x40001954;\nr_get_peer_irk_offset = 0x40001958;\nr_get_peer_rpa_offset = 0x4000195c;\nr_hal_rtc_intr_init = 0x40001960;\nr_hal_rtc_irq_handler = 0x40001964;\nr_hal_timer_deinit = 0x40001968;\nr_hal_timer_disable_irq = 0x4000196c;\nr_hal_timer_env_init = 0x40001970;\nr_hal_timer_init = 0x40001974;\nr_hal_timer_process = 0x40001978;\nr_hal_timer_read = 0x4000197c;\nr_hal_timer_read_tick = 0x40001980;\nr_hal_timer_set_cb = 0x40001984;\nr_hal_timer_set_exp_tick = 0x40001988;\nr_hal_timer_start = 0x4000198c;\nr_hal_timer_start_at = 0x40001990;\nr_hal_timer_stop = 0x40001994;\nr_hal_timer_task_start = 0x40001998;\nr_ll_assert = 0x4000199c;\nr_mem_init_mbuf_pool = 0x400019a0;\nr_mem_malloc_mbuf_pool = 0x400019a4;\nr_mem_malloc_mbufpkt_pool = 0x400019a8;\nr_mem_malloc_mempool = 0x400019ac;\nr_mem_malloc_mempool_ext = 0x400019b0;\nr_mem_malloc_mempool_gen = 0x400019b4;\nr_mem_pullup_obj = 0x400019b8;\nr_mem_split_frag = 0x400019bc;\nr_os_cputime_get32 = 0x400019c0;\nr_os_cputime_ticks_to_usecs = 0x400019c4;\nr_os_cputime_timer_init = 0x400019c8;\nr_os_cputime_timer_relative = 0x400019cc;\nr_os_cputime_timer_start = 0x400019d0;\nr_os_cputime_timer_stop = 0x400019d4;\nr_os_cputime_usecs_to_ticks = 0x400019d8;\nr_os_mbuf_adj = 0x400019dc;\nr_os_mbuf_append = 0x400019e0;\nr_os_mbuf_appendfrom = 0x400019e4;\nr_os_mbuf_cmpf = 0x400019e8;\nr_os_mbuf_cmpm = 0x400019ec;\nr_os_mbuf_concat = 0x400019f0;\nr_os_mbuf_copydata = 0x400019f4;\nr_os_mbuf_copyinto = 0x400019f8;\nr_os_mbuf_dup = 0x400019fc;\nr_os_mbuf_extend = 0x40001a00;\nr_os_mbuf_free = 0x40001a04;\nr_os_mbuf_free_chain = 0x40001a08;\nr_os_mbuf_get = 0x40001a0c;\nr_os_mbuf_get_pkthdr = 0x40001a10;\nr_os_mbuf_leadingspace = 0x40001a14;\nr_os_mbuf_len = 0x40001a18;\nr_os_mbuf_off = 0x40001a1c;\nr_os_mbuf_pack_chains = 0x40001a20;\nr_os_mbuf_pool_init = 0x40001a24;\nr_os_mbuf_prepend = 0x40001a28;\nr_os_mbuf_prepend_pullup = 0x40001a2c;\nr_os_mbuf_pullup = 0x40001a30;\nr_os_mbuf_trailingspace = 0x40001a34;\nr_os_mbuf_trim_front = 0x40001a38;\nr_os_mbuf_widen = 0x40001a3c;\nr_os_memblock_from = 0x40001a40;\nr_os_memblock_get = 0x40001a44;\nr_os_memblock_put = 0x40001a48;\nr_os_memblock_put_from_cb = 0x40001a4c;\nr_os_mempool_clear = 0x40001a50;\nr_os_mempool_ext_clear = 0x40001a54;\nr_os_mempool_ext_init = 0x40001a58;\nr_os_mempool_info_get_next = 0x40001a5c;\nr_os_mempool_init = 0x40001a60;\nr_os_mempool_init_internal = 0x40001a64;\nr_os_mempool_is_sane = 0x40001a68;\nr_os_mempool_module_init = 0x40001a6c;\nr_os_mempool_unregister = 0x40001a70;\nr_os_mqueue_get = 0x40001a74;\nr_os_mqueue_init = 0x40001a78;\nr_os_mqueue_put = 0x40001a7c;\nr_os_msys_count = 0x40001a80;\nr_os_msys_get = 0x40001a84;\nr_os_msys_get_pkthdr = 0x40001a88;\nr_os_msys_num_free = 0x40001a8c;\nr_os_msys_register = 0x40001a90;\nr_os_msys_reset = 0x40001a94;\nr_pri_phy_valid = 0x40001a98;\nr_put_be16 = 0x40001a9c;\nr_put_be24 = 0x40001aa0;\nr_put_be32 = 0x40001aa4;\nr_put_be64 = 0x40001aa8;\nr_put_le16 = 0x40001aac;\nr_put_le24 = 0x40001ab0;\nr_put_le32 = 0x40001ab4;\nr_put_le64 = 0x40001ab8;\nr_rtc0_timer_handler = 0x40001abc;\nr_sdkconfig_get_opts = 0x40001ac0;\nr_sdkconfig_set_opts = 0x40001ac4;\nr_sec_phy_valid = 0x40001ac8;\nr_swap_buf = 0x40001acc;\nr_swap_in_place = 0x40001ad0;\n\/* Data (.data, .bss, .rodata) *\/\nble_lll_dtm_module_env_p = 0x3fcdffc4;\ng_ble_lll_dtm_prbs15_data = 0x3ff4fee4;\ng_ble_lll_dtm_prbs9_data = 0x3ff4fde4;\ng_channel_rf_to_index = 0x3ff4fdbc;\ng_ble_lll_rfmgmt_data = 0x3fcdff7c;\ng_ble_sleep_enter_cb = 0x3fcdff78;\ng_ble_sleep_exit_cb = 0x3fcdff74;\nble_lll_sched_env_p = 0x3fcdff70;\nble_ll_env_p = 0x3fcdff6c;\ng_ble_ll_pdu_header_tx_time_ro = 0x3ff4fdb4;\nble_ll_adv_env_p = 0x3fcdff68;\nble_ll_conn_env_p = 0x3fcdff64;\nble_ll_conn_required_phy_mask = 0x3ff4fdb0;\nble_ll_valid_conn_phy_mask = 0x3ff4fdaf;\ng_ble_ll_ctrl_pkt_lengths_ro = 0x3ff4fd8c;\nble_ll_hci_env_p = 0x3fcdff60;\ng_debug_le_private_key = 0x3ff4fd6c;\ng_ecc_key = 0x3fcdfefc;\nble_ll_rand_env_p = 0x3fcdfef8;\nble_ll_resolv_env_p = 0x3fcdfef4;\ng_ble_ll_resolve_hdr = 0x3fcdfeec;\ng_device_mode_default = 0x3fcdfe68;\nble_ll_scan_classify_filter_aux_check_cb = 0x3fcdfee8;\nble_ll_scan_classify_filter_check_cb = 0x3fcdfee4;\nble_ll_scan_env_p = 0x3fcdfee0;\ng_ble_ll_supp_cmds_ro = 0x3ff4fd3c;\nble_ll_sync_env_p = 0x3fcdfedc;\ng_ble_sca_ppm_tbl_ro = 0x3ff4fd2c;\npriv_config_opts = 0x3fcdfe48;\nble_hci_uart_reset_cmd = 0x3ff4fd28;\nble_hci_trans_env_p = 0x3fcdfed8;\nble_hci_trans_mode = 0x3fcdfe44;\nble_hci_trans_funcs_ptr = 0x3fcdfed4;\nr_ble_lll_stub_funcs_ptr = 0x3fcdfed0;\nr_ble_stub_funcs_ptr = 0x3fcdfecc;\nr_ext_funcs_p = 0x3fcdfec8;\nr_npl_funcs = 0x3fcdfec4;\nble_hw_env_p = 0x3fcdfec0;\nble_phy_module_env_p = 0x3fcdfebc;\ng_ble_phy_chan_freq_ro = 0x3ff4fd00;\ng_ble_phy_mode_pkt_start_off_ro = 0x3ff4fcf8;\ng_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fce8;\ng_ble_phy_t_rxaddrdelay_ro = 0x3ff4fce4;\ng_ble_phy_t_rxenddelay_ro = 0x3ff4fce0;\ng_ble_phy_t_txdelay_ro = 0x3ff4fcdc;\ng_ble_phy_t_txenddelay_ro = 0x3ff4fcd8;\ng_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcc8;\nhal_timer_env_p = 0x3fcdfeb8;\nr_osi_coex_funcs_p = 0x3fcdfeb4;\nbt_rf_coex_hooks = 0x3fcdfeac;\nbt_rf_coex_hooks_p = 0x3fcdfea8;\ncoex_hook_st_group_tab = 0x3ff4fcbc;\ncoex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcb8;\ns_ble_act_count_by_group = 0x3fcdfea4;\ns_ble_coex_st_map = 0x3fcdfe90;\nbt_rf_coex_cfg_cb = 0x3fcdfe74;\nbt_rf_coex_cfg_p = 0x3fcdfe70;\nbt_rf_coex_cfg_rom = 0x3ff4fc9c;\nbt_rf_coex_pti_dft_p = 0x3fcdfe6c;\nbt_rf_coex_pti_dft_rom = 0x3fcdfe04;\nconn_dynamic_pti_param_rom = 0x3ff4fc84;\nconn_phy_coded_max_data_time_param_rom = 0x3ff4fc80;\next_adv_dynamic_pti_param_rom = 0x3ff4fc4c;\next_scan_dynamic_param_rom = 0x3ff4fc14;\nlegacy_adv_dynamic_pti_param_rom = 0x3ff4fbf4;\nper_adv_dynamic_pti_param_rom = 0x3ff4fbd8;\nsync_dynamic_param_rom = 0x3ff4fbc0;\ng_ble_plf_log_level = 0x3fcdfe00;\ng_msys_pool_list = 0x3fcdfdf8;\ng_os_mempool_list = 0x3fcdfdf0;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x40001ad4;\nRC_GetBlockAckTime = 0x40001ad8;\nebuf_list_remove = 0x40001adc;\nesf_buf_alloc = 0x40001ae0;\nesf_buf_alloc_dynamic = 0x40001ae4;\nesf_buf_recycle = 0x40001ae8;\nGetAccess = 0x40001aec;\nhal_mac_is_low_rate_enabled = 0x40001af0;\nhal_mac_tx_get_blockack = 0x40001af4;\nhal_mac_tx_set_ppdu = 0x40001af8;\nic_get_trc = 0x40001afc;\nic_mac_deinit = 0x40001b00;\nic_mac_init = 0x40001b04;\nic_interface_enabled = 0x40001b08;\nis_lmac_idle = 0x40001b0c;\nlmacAdjustTimestamp = 0x40001b10;\nlmacDiscardAgedMSDU = 0x40001b14;\nlmacDiscardMSDU = 0x40001b18;\nlmacEndFrameExchangeSequence = 0x40001b1c;\nlmacIsIdle = 0x40001b20;\nlmacIsLongFrame = 0x40001b24;\nlmacMSDUAged = 0x40001b28;\nlmacPostTxComplete = 0x40001b2c;\nlmacProcessAllTxTimeout = 0x40001b30;\nlmacProcessCollisions = 0x40001b34;\nlmacProcessRxSucData = 0x40001b38;\nlmacReachLongLimit = 0x40001b3c;\nlmacReachShortLimit = 0x40001b40;\nlmacRecycleMPDU = 0x40001b44;\nlmacRxDone = 0x40001b48;\nlmacSetTxFrame = 0x40001b4c;\nlmacTxDone = 0x40001b50;\nlmacTxFrame = 0x40001b54;\nmac_tx_set_duration = 0x40001b58;\nmac_tx_set_htsig = 0x40001b5c;\nmac_tx_set_plcp0 = 0x40001b60;\nmac_tx_set_plcp1 = 0x40001b64;\nmac_tx_set_plcp2 = 0x40001b68;\npm_check_state = 0x40001b6c;\npm_disable_dream_timer = 0x40001b70;\npm_disable_sleep_delay_timer = 0x40001b74;\npm_dream = 0x40001b78;\npm_mac_wakeup = 0x40001b7c;\npm_mac_sleep = 0x40001b80;\npm_enable_active_timer = 0x40001b84;\npm_enable_sleep_delay_timer = 0x40001b88;\npm_local_tsf_process = 0x40001b8c;\npm_set_beacon_filter = 0x40001b90;\npm_is_in_wifi_slice_threshold = 0x40001b94;\npm_is_waked = 0x40001b98;\npm_keep_alive = 0x40001b9c;\npm_on_beacon_rx = 0x40001ba0;\npm_on_data_rx = 0x40001ba4;\npm_on_tbtt = 0x40001ba8;\npm_parse_beacon = 0x40001bac;\npm_process_tim = 0x40001bb0;\npm_rx_beacon_process = 0x40001bb4;\npm_rx_data_process = 0x40001bb8;\npm_sleep = 0x40001bbc;\npm_sleep_for = 0x40001bc0;\npm_tbtt_process = 0x40001bc4;\nppAMPDU2Normal = 0x40001bc8;\nppAssembleAMPDU = 0x40001bcc;\nppCalFrameTimes = 0x40001bd0;\nppCalSubFrameLength = 0x40001bd4;\nppCalTxAMPDULength = 0x40001bd8;\nppCheckTxAMPDUlength = 0x40001bdc;\nppDequeueRxq_Locked = 0x40001be0;\nppDequeueTxQ = 0x40001be4;\nppEmptyDelimiterLength = 0x40001be8;\nppEnqueueRxq = 0x40001bec;\nppEnqueueTxDone = 0x40001bf0;\nppGetTxQFirstAvail_Locked = 0x40001bf4;\nppGetTxframe = 0x40001bf8;\nppMapTxQueue = 0x40001bfc;\nppProcTxSecFrame = 0x40001c00;\nppProcessRxPktHdr = 0x40001c04;\nppProcessTxQ = 0x40001c08;\nppRecordBarRRC = 0x40001c0c;\nlmacRequestTxopQueue = 0x40001c10;\nlmacReleaseTxopQueue = 0x40001c14;\nppRecycleAmpdu = 0x40001c18;\nppRecycleRxPkt = 0x40001c1c;\nppResortTxAMPDU = 0x40001c20;\nppResumeTxAMPDU = 0x40001c24;\nppRxFragmentProc = 0x40001c28;\nppRxPkt = 0x40001c2c;\nppRxProtoProc = 0x40001c30;\nppSearchTxQueue = 0x40001c34;\nppSearchTxframe = 0x40001c38;\nppSelectNextQueue = 0x40001c3c;\nppSubFromAMPDU = 0x40001c40;\nppTask = 0x40001c44;\nppTxPkt = 0x40001c48;\nppTxProtoProc = 0x40001c4c;\nppTxqUpdateBitmap = 0x40001c50;\npp_coex_tx_request = 0x40001c54;\npp_hdrsize = 0x40001c58;\npp_post = 0x40001c5c;\npp_process_hmac_waiting_txq = 0x40001c60;\nrcGetAmpduSched = 0x40001c64;\nrcUpdateRxDone = 0x40001c68;\nrc_get_trc = 0x40001c6c;\nrc_get_trc_by_index = 0x40001c70;\nrcAmpduLowerRate = 0x40001c74;\nrcampduuprate = 0x40001c78;\nrcClearCurAMPDUSched = 0x40001c7c;\nrcClearCurSched = 0x40001c80;\nrcClearCurStat = 0x40001c84;\nrcGetSched = 0x40001c88;\nrcLowerSched = 0x40001c8c;\nrcSetTxAmpduLimit = 0x40001c90;\nrcTxUpdatePer = 0x40001c94;\nrcUpdateAckSnr = 0x40001c98;\nrcUpdateRate = 0x40001c9c;\nrcUpdateTxDone = 0x40001ca0;\nrcUpdateTxDoneAmpdu2 = 0x40001ca4;\nrcUpSched = 0x40001ca8;\nrssi_margin = 0x40001cac;\nrx11NRate2AMPDULimit = 0x40001cb0;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001cb4;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001cb8;\ntrc_calc_duration = 0x40001cbc;\ntrc_isTxAmpduOperational = 0x40001cc0;\ntrc_onAmpduOp = 0x40001cc4;\nTRC_PER_IS_GOOD = 0x40001cc8;\ntrc_SetTxAmpduState = 0x40001ccc;\ntrc_tid_isTxAmpduOperational = 0x40001cd0;\ntrcAmpduSetState = 0x40001cd4;\nwDevCheckBlockError = 0x40001cd8;\nwDev_AppendRxBlocks = 0x40001cdc;\nwDev_DiscardFrame = 0x40001ce0;\nwDev_GetNoiseFloor = 0x40001ce4;\nwDev_IndicateAmpdu = 0x40001ce8;\nwDev_IndicateFrame = 0x40001cec;\nwdev_mac_reg_load = 0x40001cf0;\nwdev_mac_reg_store = 0x40001cf4;\nwdev_mac_special_reg_load = 0x40001cf8;\nwdev_mac_special_reg_store = 0x40001cfc;\nwdev_mac_wakeup = 0x40001d00;\nwdev_mac_sleep = 0x40001d04;\nwDev_ProcessFiq = 0x40001d08;\nwDev_ProcessRxSucData = 0x40001d0c;\nwdevProcessRxSucDataAll = 0x40001d10;\nwdev_csi_len_align = 0x40001d14;\nppDequeueTxDone_Locked = 0x40001d18;\nppProcTxDone = 0x40001d1c;\npm_tx_data_done_process = 0x40001d20;\nconfig_is_cache_tx_buf_enabled = 0x40001d24;\nppMapWaitTxq = 0x40001d28;\nppProcessWaitingQueue = 0x40001d2c;\nppDisableQueue = 0x40001d30;\npm_allow_tx = 0x40001d34;\nwdev_is_data_in_rxlist = 0x40001d38;\nppProcTxCallback = 0x40001d3c;\npm_is_open = 0x40001d40;\npm_wake_up = 0x40001d44;\npm_wake_done = 0x40001d48;\npm_disable_disconnected_sleep_delay_timer = 0x40001d4c;\npm_enable_disconnected_sleep_delay_timer = 0x40001d50;\nhal_mac_get_txq_state = 0x40001d54;\nhal_mac_clr_txq_state = 0x40001d58;\nhal_mac_tx_set_cca = 0x40001d5c;\nhal_mac_set_txq_invalid = 0x40001d60;\nhal_mac_txq_disable = 0x40001d64;\nhal_mac_is_txq_enabled = 0x40001d68;\nhal_mac_get_txq_pmd = 0x40001d6c;\nlmacDiscardFrameExchangeSequence = 0x40001d70;\nlmacDisableTransmit = 0x40001d74;\nlmacProcessTxTimeout = 0x40001d78;\nlmacProcessTxSuccess = 0x40001d7c;\nlmacProcessCollision = 0x40001d80;\nlmacProcessTxRtsError = 0x40001d84;\nlmacProcessCtsTimeout = 0x40001d88;\nlmacProcessTxComplete = 0x40001d8c;\nlmacProcessAckTimeout = 0x40001d90;\nlmacProcessTxError = 0x40001d94;\nlmacProcessTxseckiderr = 0x40001d98;\nrcReachRetryLimit = 0x40001d9c;\nlmacProcessShortRetryFail = 0x40001da0;\nlmacEndRetryAMPDUFail = 0x40001da4;\nppFillAMPDUBar = 0x40001da8;\nrcGetRate = 0x40001dac;\nppReSendBar = 0x40001db0;\nlmacProcessLongRetryFail = 0x40001db4;\nlmacRetryTxFrame = 0x40001db8;\nlmacProcessCollisions_task = 0x40001dbc;\nlmacProcessTxopQComplete = 0x40001dc0;\nlmacInitAc = 0x40001dc4;\nlmacInit = 0x40001dc8;\nmac_tx_set_txop_q = 0x40001dcc;\nhal_init = 0x40001dd0;\nhal_mac_rx_set_policy = 0x40001dd4;\nhal_mac_set_bssid = 0x40001dd8;\nmac_rx_policy_init = 0x40001ddc;\nmac_txrx_init = 0x40001de0;\nmac_rxbuf_init = 0x40001de4;\nmac_last_rxbuf_init = 0x40001de8;\nhal_attenna_init = 0x40001dec;\nhal_timer_update_by_rtc = 0x40001df0;\nhal_coex_pti_init = 0x40001df4;\nlmac_stop_hw_txq = 0x40001df8;\nppDirectRecycleAmpdu = 0x40001dfc;\nesp_wifi_internal_set_rts = 0x40001e00;\nesp_wifi_internal_get_rts = 0x40001e04;\nppTxFragmentProc = 0x40001e08;\nesf_buf_setup = 0x40001e0c;\nhal_agreement_add_rx_ba = 0x40001e10;\nhal_agreement_del_rx_ba = 0x40001e14;\nhal_crypto_set_key_entry = 0x40001e18;\nhal_crypto_get_key_entry = 0x40001e1c;\nhal_crypto_clr_key_entry = 0x40001e20;\nconfig_get_wifi_task_stack_size = 0x40001e24;\npp_create_task = 0x40001e28;\nhal_set_sta_tsf_wakeup = 0x40001e2c;\nhal_set_rx_beacon_pti = 0x40001e30;\npm_start = 0x40001e34;\npm_stop = 0x40001e38;\nhal_disable_sta_tbtt = 0x40001e3c;\nppCalTxopDur = 0x40001e40;\nwDev_IndicateCtrlFrame = 0x40001e44;\nhal_enable_sta_tbtt = 0x40001e48;\nhal_set_sta_tbtt = 0x40001e4c;\npm_update_next_tbtt = 0x40001e50;\npm_set_sleep_type = 0x40001e54;\nwDev_Rxbuf_Init = 0x40001e58;\nwDev_Rxbuf_Deinit = 0x40001e5c;\nppCalTkipMic = 0x40001e60;\nwDev_SnifferRxData = 0x40001e64;\nhal_crypto_enable = 0x40001e68;\nhal_crypto_disable = 0x40001e6c;\nwDev_Insert_KeyEntry = 0x40001e70;\nwDev_remove_KeyEntry = 0x40001e74;\nrc_enable_trc = 0x40001e78;\nrc_set_per_conn_fix_rate = 0x40001e7c;\nwdev_csi_rx_process = 0x40001e80;\nwDev_SnifferRxAmpdu = 0x40001e84;\nhal_mac_tsf_reset = 0x40001e88;\ndbg_lmac_statis_dump = 0x40001e8c;\ndbg_lmac_rxtx_statis_dump = 0x40001e90;\ndbg_lmac_hw_statis_dump = 0x40001e94;\ndbg_lmac_diag_statis_dump = 0x40001e98;\ndbg_lmac_ps_statis_dump = 0x40001e9c;\npp_timer_do_process = 0x40001ea0;\nrcUpdateAMPDUParam = 0x40001ea4;\nrcUpdatePhyMode = 0x40001ea8;\nrcGetHighestRateIdx = 0x40001eac;\npm_tx_null_data_done_process = 0x40001eb0;\npm_tx_data_process = 0x40001eb4;\npm_attach = 0x40001eb8;\npm_coex_schm_process = 0x40001ebc;\nppInitTxq = 0x40001ec0;\npp_attach = 0x40001ec4;\npp_deattach = 0x40001ec8;\npm_on_probe_resp_rx = 0x40001ecc;\nhal_set_sta_tsf = 0x40001ed0;\nic_update_sta_tsf = 0x40001ed4;\nic_tx_pkt = 0x40001ed8;\npm_send_probe_stop = 0x40001edc;\npm_send_probe_start = 0x40001ee0;\npm_on_coex_schm_process_restart = 0x40001ee4;\nhal_mac_set_rxq_policy = 0x40001ee8;\nhal_sniffer_enable = 0x40001eec;\nhal_sniffer_disable = 0x40001ef0;\nhal_sniffer_rx_set_promis = 0x40001ef4;\nhal_sniffer_rx_clr_statistics = 0x40001ef8;\nhal_sniffer_set_promis_misc_pkt = 0x40001efc;\ntsf_hal_set_tsf_enable = 0x40001f00;\ntsf_hal_set_tsf_disable = 0x40001f04;\ntsf_hal_is_tsf_enabled = 0x40001f08;\ntsf_hal_set_modem_wakeup_early_time = 0x40001f0c;\ntsf_hal_get_counter_value = 0x40001f10;\ntsf_hal_set_counter_value = 0x40001f14;\ntsf_hal_get_time = 0x40001f18;\ntsf_hal_set_time = 0x40001f1c;\ntsf_hal_set_tbtt_enable = 0x40001f20;\ntsf_hal_set_tbtt_disable = 0x40001f24;\ntsf_hal_set_tbtt_intr_enable = 0x40001f28;\ntsf_hal_set_tbtt_intr_disable = 0x40001f2c;\ntsf_hal_set_tbtt_soc_wakeup_enable = 0x40001f30;\ntsf_hal_set_tbtt_soc_wakeup_disable = 0x40001f34;\ntsf_hal_set_tbtt_start_time = 0x40001f38;\ntsf_hal_set_tbtt_early_time = 0x40001f3c;\ntsf_hal_set_tbtt_interval = 0x40001f40;\ntsf_hal_get_tbtt_interval = 0x40001f44;\ntsf_hal_set_timer_enable = 0x40001f48;\ntsf_hal_set_timer_disable = 0x40001f4c;\ntsf_hal_set_timer_target = 0x40001f50;\ntsf_hal_get_timer_target = 0x40001f54;\ntsf_hal_set_timer_intr_enable = 0x40001f58;\ntsf_hal_set_timer_intr_disable = 0x40001f5c;\ntsf_hal_set_timer_soc_wakeup_enable = 0x40001f60;\ntsf_hal_set_timer_soc_wakeup_disable = 0x40001f64;\npm_disconnected_wake = 0x40001f68;\npm_get_connectionless_status = 0x40001f6c;\npm_update_by_connectionless_status = 0x40001f70;\npm_connectionless_wake_interval_timeout_process = 0x40001f74;\npm_connectionless_wake_window_timeout_process = 0x40001f78;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff4fbbc;\npTxRx = 0x3fcdfdec;\nlmacConfMib_ptr = 0x3fcdfde8;\nour_wait_eb = 0x3fcdfde4;\nour_tx_eb = 0x3fcdfde0;\npp_wdev_funcs = 0x3fcdfddc;\ng_osi_funcs_p = 0x3fcdfdd8;\nwDevCtrl_ptr = 0x3fcdfdd4;\ng_wdev_last_desc_reset_ptr = 0x3ff4fbb8;\nwDevMacSleep_ptr = 0x3fcdfdd0;\ng_lmac_cnt_ptr = 0x3fcdfdcc;\nour_controls_ptr = 0x3ff4fbb4;\npp_sig_cnt_ptr = 0x3fcdfdc8;\ng_eb_list_desc_ptr = 0x3fcdfdc4;\ns_fragment_ptr = 0x3fcdfdc0;\nif_ctrl_ptr = 0x3fcdfdbc;\ng_intr_lock_mux = 0x3fcdfdb8;\ng_wifi_global_lock = 0x3fcdfdb4;\ns_wifi_queue = 0x3fcdfdb0;\npp_task_hdl = 0x3fcdfdac;\ns_pp_task_create_sem = 0x3fcdfda8;\ns_pp_task_del_sem = 0x3fcdfda4;\ng_wifi_menuconfig_ptr = 0x3fcdfda0;\nxphyQueue = 0x3fcdfd9c;\nap_no_lr_ptr = 0x3fcdfd98;\nrc11BSchedTbl_ptr = 0x3fcdfd94;\nrc11NSchedTbl_ptr = 0x3fcdfd90;\nrcLoRaSchedTbl_ptr = 0x3fcdfd8c;\nBasicOFDMSched_ptr = 0x3fcdfd88;\ntrc_ctl_ptr = 0x3fcdfd84;\ng_pm_cnt_ptr = 0x3fcdfd80;\ng_pm_ptr = 0x3fcdfd7c;\ng_pm_cfg_ptr = 0x3fcdfd78;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdfd74;\ng_txop_queue_status_ptr = 0x3fcdfd70;\ng_mac_sleep_en_ptr = 0x3fcdfd6c;\ng_mesh_is_root_ptr = 0x3fcdfd68;\ng_mesh_topology_ptr = 0x3fcdfd64;\ng_mesh_init_ps_type_ptr = 0x3fcdfd60;\ng_mesh_is_started_ptr = 0x3fcdfd5c;\ng_config_func = 0x3fcdfd58;\ng_net80211_tx_func = 0x3fcdfd54;\ng_timer_func = 0x3fcdfd50;\ns_michael_mic_failure_cb = 0x3fcdfd4c;\nwifi_sta_rx_probe_req = 0x3fcdfd48;\ng_tx_done_cb_func = 0x3fcdfd44;\ng_per_conn_trc = 0x3fcdfd28;\ns_encap_amsdu_func = 0x3fcdfd24;\nbars = 0x3fcdfc84;\neb_txdesc_space = 0x3fcdfbf4;\neb_space = 0x3fcdfb54;\ng_pd_mac_in_light_sleep = 0x3fcdfb50;\ns_fix_rate_mask = 0x3fcdfb4c;\ns_fix_rate = 0x3fcdfb44;\ng_wdev_csi_rx = 0x3fcdfb40;\ng_wdev_csi_rx_ctx = 0x3fcdfb3c;\nBcnSendTick = 0x3fcdfb38;\ng_pp_timer_info_ptr = 0x3fcdfb34;\nrcP2P11NSchedTbl_ptr = 0x3fcdfb30;\nrcP2P11GSchedTbl_ptr = 0x3fcdfb2c;\nrc11GSchedTbl_ptr = 0x3fcdfb28;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001f7c;\nampdu_dispatch = 0x40001f80;\nampdu_dispatch_all = 0x40001f84;\nampdu_dispatch_as_many_as_possible = 0x40001f88;\nampdu_dispatch_movement = 0x40001f8c;\nampdu_dispatch_upto = 0x40001f90;\nchm_is_at_home_channel = 0x40001f94;\ncnx_node_is_existing = 0x40001f98;\ncnx_node_search = 0x40001f9c;\nic_ebuf_recycle_rx = 0x40001fa0;\nic_ebuf_recycle_tx = 0x40001fa4;\nic_reset_rx_ba = 0x40001fa8;\nieee80211_align_eb = 0x40001fac;\nieee80211_ampdu_reorder = 0x40001fb0;\nieee80211_ampdu_start_age_timer = 0x40001fb4;\nieee80211_encap_esfbuf = 0x40001fb8;\nieee80211_is_tx_allowed = 0x40001fbc;\nieee80211_output_pending_eb = 0x40001fc0;\nieee80211_output_process = 0x40001fc4;\nieee80211_set_tx_desc = 0x40001fc8;\nsta_input = 0x40001fcc;\nwifi_get_macaddr = 0x40001fd0;\nwifi_rf_phy_disable = 0x40001fd4;\nwifi_rf_phy_enable = 0x40001fd8;\nic_ebuf_alloc = 0x40001fdc;\nieee80211_classify = 0x40001fe0;\nieee80211_copy_eb_header = 0x40001fe4;\nieee80211_recycle_cache_eb = 0x40001fe8;\nieee80211_search_node = 0x40001fec;\nroundup2 = 0x40001ff0;\nieee80211_crypto_encap = 0x40001ff4;\nieee80211_crypto_decap = 0x40001ff8;\nieee80211_decap = 0x40001ffc;\nieee80211_set_tx_pti = 0x40002000;\nwifi_is_started = 0x40002004;\nieee80211_gettid = 0x40002008;\nieee80211_ccmp_decrypt = 0x4000200c;\nieee80211_ccmp_encrypt = 0x40002010;\nccmp_encap = 0x40002014;\nccmp_decap = 0x40002018;\ntkip_encap = 0x4000201c;\ntkip_decap = 0x40002020;\nwep_encap = 0x40002024;\nwep_decap = 0x40002028;\ndbg_hmac_rxtx_statis_dump = 0x4000202c;\ndbg_hmac_statis_dump = 0x40002030;\nieee80211_send_action_vendor_spec = 0x40002034;\nieee80211_deauth_construct = 0x40002040;\nieee80211_disassoc_construct = 0x40002044;\nieee80211_vnd_lora_ie_size = 0x40002048;\nieee80211_vnd_ie_size = 0x4000204c;\nieee80211_add_ssid = 0x40002050;\nieee80211_add_rates = 0x40002054;\nieee80211_add_xrates = 0x40002058;\nieee80211_is_ht_cipher = 0x4000205c;\nieee80211_assoc_resp_construct = 0x40002064;\nieee80211_setup_lr_rates = 0x40002068;\nieee80211_ht_node_init = 0x4000206c;\nieee80211_is_support_rate = 0x40002070;\nieee80211_setup_rates = 0x40002074;\nieee80211_is_lr_only = 0x40002078;\nieee80211_setup_phy_mode = 0x4000207c;\nieee80211_sta_is_connected = 0x40002080;\ncurrent_task_is_wifi_task = 0x40002084;\nwifi_get_init_state = 0x40002088;\nieee80211_timer_process = 0x4000208c;\ncnx_coexist_timeout = 0x40002090;\nsta_recv_mgmt = 0x40002094;\nieee80211_send_setup = 0x40002098;\nieee80211_send_probereq = 0x4000209c;\nsta_auth_shared = 0x400020a4;\nsta_auth_sae = 0x400020a8;\ncnx_coexist_timeout_process = 0x400020ac;\nieee80211_alloc_challenge = 0x400020b0;\ncnx_assoc_timeout = 0x400020b4;\nieee80211_vnd_ie_set = 0x400020b8;\nieee80211_vnd_lora_ie_set = 0x400020bc;\nieee80211_add_wme_param = 0x400020c0;\nieee80211_add_dsparams = 0x400020c4;\nieee80211_add_csa = 0x400020c8;\nieee80211_add_extcap = 0x400020cc;\nieee80211_regdomain_get_country = 0x400020d0;\nieee80211_add_countryie = 0x400020d4;\nieee80211_amsdu_adjust_head = 0x400020dc;\nieee80211_amsdu_adjust_last_length = 0x400020e0;\nieee80211_amsdu_send_check = 0x400020e4;\nieee80211_amsdu_encap_check = 0x400020e8;\nieee80211_amsdu_length_check = 0x400020ec;\nieee80211_encap_amsdu = 0x400020f0;\nieee80211_output_raw_process = 0x400020f4;\nesp_wifi_80211_tx = 0x400020f8;\nieee80211_raw_frame_sanity_check = 0x400020fc;\nieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;\nieee80211_crypto_aes_128_cmac_decrypt = 0x40002104;\nieee80211_alloc_tx_buf = 0x40002108;\nieee80211_output_do = 0x4000210c;\nieee80211_send_nulldata = 0x40002110;\nieee80211_setup_robust_mgmtframe = 0x40002114;\nieee80211_mgmt_output = 0x40002118;\nieee80211_encap_null_data = 0x4000211c;\nieee80211_send_deauth = 0x40002120;\nieee80211_alloc_deauth = 0x40002124;\nieee80211_send_proberesp = 0x40002128;\nieee80211_tx_mgt_cb = 0x4000212c;\nieee80211_getcapinfo = 0x40002130;\nsta_rx_csa = 0x40002134;\nsta_recv_sa_query_resp = 0x40002144;\nieee80211_set_max_rate = 0x4000214c;\nic_set_sta = 0x40002150;\nieee80211_parse_wpa = 0x40002158;\nieee80211_add_assoc_req_ies = 0x40002160;\nieee80211_add_probe_req_ies = 0x40002164;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdfb24;\ng_scan = 0x3fcdfb20;\ng_chm = 0x3fcdfb1c;\ng_ic_ptr = 0x3fcdfb18;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_tx_cacheq_ptr = 0x3fcdfb14;\ns_netstack_free = 0x3fcdfb10;\nmesh_rxcb = 0x3fcdfb0c;\nsta_rxcb = 0x3fcdfb08;\nccmp_ptr = 0x3fcdfb04;\ns_wifi_nvs_ptr = 0x3fcdfb00;\ntkip_ptr = 0x3fcdfafc;\nwep_ptr = 0x3fcdfaf8;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_misc_nvs = 0x3fcdfaf0;\ns_wifi_init_state = 0x3fcdfac0;\ns_wifi_task_hdl = 0x3fcdfaec;\nin_rssi_adjust = 0x3fcdfae8;\nrssi_saved = 0x3fcdfae0;\nrssi_index = 0x3fcdfadc;\ns_sa_query_retries = 0x3fcdfad8;\ns_sa_query_success = 0x3fcdfad5;\ng_sta_connected_flag = 0x3fcdfad4;\nwpa_crypto_funcs_ptr = 0x3fcdfad0;\ns_netstack_ref = 0x3fcdfacc;\nsta_csa_timer_ptr = 0x3fcdfac8;\ns_trans_id = 0x3fcdfac4;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x40002168;\ncoex_bt_release = 0x4000216c;\ncoex_bt_request = 0x40002170;\ncoex_core_ble_conn_dyn_prio_get = 0x40002174;\ncoex_core_event_duration_get = 0x40002178;\ncoex_core_pti_get = 0x4000217c;\ncoex_core_release = 0x40002180;\ncoex_core_request = 0x40002184;\ncoex_core_status_get = 0x40002188;\ncoex_core_timer_idx_get = 0x4000218c;\ncoex_event_duration_get = 0x40002190;\ncoex_hw_timer_disable = 0x40002194;\ncoex_hw_timer_enable = 0x40002198;\ncoex_hw_timer_set = 0x4000219c;\ncoex_schm_interval_set = 0x400021a0;\ncoex_schm_lock = 0x400021a4;\ncoex_schm_unlock = 0x400021a8;\ncoex_status_get = 0x400021ac;\ncoex_wifi_release = 0x400021b0;\nesp_coex_ble_conn_dynamic_prio_get = 0x400021b4;\ncoex_hw_timer_tick_get = 0x400021b8;\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdfabc;\ncoex_pti_tab_ptr = 0x3fcdfab8;\ncoex_schm_env_ptr = 0x3fcdfab4;\ncoexist_funcs = 0x3fcdfab0;\ng_coa_funcs_p = 0x3fcdfaac;\ng_coex_param_ptr = 0x3fcdfaa8;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_param_addr = 0x400021bc;\nphy_get_romfuncs = 0x400021c0;\nchip729_phyrom_version = 0x400021c4;\nchip729_phyrom_version_num = 0x400021c8;\nrom_get_rc_dout = 0x400021cc;\nrc_cal = 0x400021d0;\nphy_analog_delay_cal = 0x400021d4;\nphy_rx_rifs_en = 0x400021d8;\nphy_current_level_set = 0x400021dc;\nphy_bbpll_en_usb = 0x400021e0;\nphy_bt_power_track = 0x400021e4;\nphy_xpd_tsens = 0x400021e8;\nbb_wdt_rst_enable = 0x400021ec;\nbb_wdt_int_enable = 0x400021f0;\nbb_wdt_timeout_clear = 0x400021f4;\nbb_wdt_get_status = 0x400021f8;\nrom_enter_critical_phy = 0x400021fc;\nrom_exit_critical_phy = 0x40002200;\nrom_bb_bss_cbw40 = 0x40002204;\nrom_set_chan_reg = 0x40002208;\nabs_temp = 0x4000220c;\nset_chan_cal_interp = 0x40002210;\nloopback_mode_en = 0x40002214;\nget_data_sat = 0x40002218;\nphy_byte_to_word = 0x4000221c;\nphy_get_rx_freq = 0x40002220;\ni2c_master_reset = 0x40002224;\nchan14_mic_enable = 0x40002228;\nchan14_mic_cfg = 0x4000222c;\nset_adc_rand = 0x40002230;\nphy_set_most_tpw = 0x40002234;\nphy_get_most_tpw = 0x40002238;\nesp_tx_state_out = 0x4000223c;\nphy_get_adc_rand = 0x40002240;\nphy_internal_delay = 0x40002244;\nphy_ftm_comp = 0x40002248;\nphy_11p_set = 0x4000224c;\nphy_freq_mem_backup = 0x40002250;\nant_dft_cfg = 0x40002254;\nant_wifitx_cfg = 0x40002258;\nant_wifirx_cfg = 0x4000225c;\nant_bttx_cfg = 0x40002260;\nant_btrx_cfg = 0x40002264;\nphy_chan_dump_cfg = 0x40002268;\nphy_enable_low_rate = 0x4000226c;\nphy_disable_low_rate = 0x40002270;\nphy_dig_reg_backup = 0x40002274;\nphy_chan_filt_set = 0x40002278;\nphy_rx11blr_cfg = 0x4000227c;\nset_cca = 0x40002280;\nset_rx_sense = 0x40002284;\nrx_gain_force = 0x40002288;\nrom_phy_en_hw_set_freq = 0x4000228c;\nrom_phy_dis_hw_set_freq = 0x40002290;\nwr_rf_freq_mem = 0x40002294;\nfreq_i2c_write_set = 0x40002298;\nwrite_pll_cap_mem = 0x4000229c;\npll_dac_mem_update = 0x400022a0;\npll_cap_mem_update = 0x400022a4;\nget_rf_freq_cap = 0x400022a8;\nget_rf_freq_init = 0x400022ac;\nfreq_get_i2c_data = 0x400022b0;\nfreq_i2c_data_write = 0x400022b4;\nset_chan_freq_hw_init = 0x400022b8;\nset_chan_freq_sw_start = 0x400022bc;\nrom_get_i2c_read_mask = 0x400022c0;\nrom_get_i2c_mst0_mask = 0x400022c4;\nrom_get_i2c_hostid = 0x400022c8;\nrom_chip_i2c_readReg_org = 0x400022cc;\nrom_chip_i2c_readReg = 0x400022d0;\nrom_i2c_paral_set_mst0 = 0x400022d4;\nrom_i2c_paral_set_read = 0x400022d8;\nrom_i2c_paral_read = 0x400022dc;\nrom_i2c_paral_write = 0x400022e0;\nrom_i2c_paral_write_num = 0x400022e4;\nrom_i2c_paral_write_mask = 0x400022e8;\nrom_i2c_readReg = 0x400022ec;\nrom_chip_i2c_writeReg = 0x400022f0;\nrom_i2c_writeReg = 0x400022f4;\nrom_i2c_readReg_Mask = 0x400022f8;\nrom_i2c_writeReg_Mask = 0x400022fc;\nrom_set_txcap_reg = 0x40002300;\ni2c_sar2_init_code = 0x40002304;\nphy_i2c_init1 = 0x40002308;\nphy_i2c_init2 = 0x4000230c;\nphy_get_i2c_data = 0x40002310;\nbias_reg_set = 0x40002314;\ni2c_rc_cal_set = 0x40002318;\ni2c_bbpll_set = 0x4000231c;\nrom_phy_xpd_rf = 0x40002320;\nphy_wakeup_init_rom = 0x40002324;\nregister_chipv7_phy_init_param = 0x40002328;\nphy_reg_init = 0x4000232c;\nphy_close_rf_rom = 0x40002330;\nrom_pbus_force_mode = 0x40002334;\nrom_pbus_rd_addr = 0x40002338;\nrom_pbus_rd_shift = 0x4000233c;\nrom_pbus_force_test = 0x40002340;\nrom_pbus_rd = 0x40002344;\nrom_pbus_debugmode = 0x40002348;\nrom_pbus_workmode = 0x4000234c;\nrom_pbus_set_rxgain = 0x40002350;\nrom_pbus_xpd_rx_off = 0x40002354;\nrom_pbus_xpd_rx_on = 0x40002358;\nrom_pbus_xpd_tx_off = 0x4000235c;\nrom_pbus_xpd_tx_on = 0x40002360;\nrom_pbus_set_dco = 0x40002364;\nrom_set_loopback_gain = 0x40002368;\nrom_txcal_debuge_mode = 0x4000236c;\nrom_txcal_work_mode = 0x40002370;\nset_pbus_mem = 0x40002374;\nrom_pwdet_sar2_init = 0x40002378;\nrom_en_pwdet = 0x4000237c;\nrom_get_sar_sig_ref = 0x40002380;\nrom_pwdet_tone_start = 0x40002384;\nrom_get_tone_sar_dout = 0x40002388;\nrom_get_fm_sar_dout = 0x4000238c;\nrom_txtone_linear_pwr = 0x40002390;\nrom_get_power_db = 0x40002394;\nrom_meas_tone_pwr_db = 0x40002398;\nrom_pkdet_vol_start = 0x4000239c;\nrom_read_sar_dout = 0x400023a0;\nrom_read_sar2_code = 0x400023a4;\nrom_get_sar2_vol = 0x400023a8;\nrom_get_pll_vol = 0x400023ac;\nrom_tx_pwctrl_bg_init = 0x400023b0;\nrom_phy_pwdet_always_en = 0x400023b4;\nrom_phy_pwdet_onetime_en = 0x400023b8;\nlinear_to_db = 0x400023bc;\nrom_disable_agc = 0x400023c0;\nrom_enable_agc = 0x400023c4;\nrom_disable_wifi_agc = 0x400023c8;\nrom_enable_wifi_agc = 0x400023cc;\nrom_write_gain_mem = 0x400023d0;\nrom_bb_bss_cbw40_dig = 0x400023d4;\nrom_cbw2040_cfg = 0x400023d8;\nrom_mac_tx_chan_offset = 0x400023dc;\nrom_tx_paon_set = 0x400023e0;\nrom_i2cmst_reg_init = 0x400023e4;\nrom_bt_gain_offset = 0x400023e8;\nrom_fe_reg_init = 0x400023ec;\nrom_mac_enable_bb = 0x400023f0;\nrom_bb_wdg_cfg = 0x400023f4;\nrom_fe_txrx_reset = 0x400023f8;\nrom_set_rx_comp = 0x400023fc;\nrom_write_chan_freq = 0x40002400;\nrom_agc_reg_init = 0x40002404;\nrom_bb_reg_init = 0x40002408;\nrom_write_txrate_power_offset = 0x4000240c;\nrom_open_i2c_xpd = 0x40002410;\nrom_txiq_set_reg = 0x40002414;\nrom_rxiq_set_reg = 0x40002418;\nrom_phy_bbpll_cal = 0x4000241c;\nphy_disable_cca = 0x40002420;\nphy_enable_cca = 0x40002424;\nforce_txon = 0x40002428;\nset_txclk_en = 0x4000242c;\nset_rxclk_en = 0x40002430;\nstart_tx_tone_step = 0x40002434;\nstop_tx_tone = 0x40002438;\nbb_wdg_test_en = 0x4000243c;\nnoise_floor_auto_set = 0x40002440;\nread_hw_noisefloor = 0x40002444;\niq_corr_enable = 0x40002448;\nbt_tx_dig_gain = 0x4000244c;\nwifi_tx_dig_reg = 0x40002450;\nwifi_agc_sat_gain = 0x40002454;\nphy_ant_init = 0x40002458;\nphy_set_bbfreq_init = 0x4000245c;\nwifi_fbw_sel = 0x40002460;\nphy_rx_sense_set = 0x40002464;\ntx_state_set = 0x40002468;\nphy_close_pa = 0x4000246c;\nbt_filter_reg = 0x40002470;\nphy_freq_correct = 0x40002474;\nset_pbus_reg = 0x40002478;\nwifi_rifs_mode_en = 0x4000247c;\nrfagc_disable = 0x40002480;\nrom_restart_cal = 0x40002484;\nrom_write_rfpll_sdm = 0x40002488;\nrom_wait_rfpll_cal_end = 0x4000248c;\nrom_rfpll_set_freq = 0x40002490;\nrom_rfpll_cap_init_cal = 0x40002494;\nrom_set_rfpll_freq = 0x40002498;\nrom_write_pll_cap = 0x4000249c;\nrom_read_pll_cap = 0x400024a0;\nmhz2ieee = 0x400024a4;\nchan_to_freq = 0x400024a8;\nset_rf_freq_offset = 0x400024ac;\nset_channel_rfpll_freq = 0x400024b0;\nrfpll_cap_correct = 0x400024b4;\nphy_set_freq = 0x400024b8;\ncorrect_rfpll_offset = 0x400024bc;\npll_vol_cal = 0x400024c0;\nchip_v7_set_chan_misc = 0x400024c4;\nchip_v7_set_chan = 0x400024c8;\nchip_v7_set_chan_offset = 0x400024cc;\nchip_v7_set_chan_ana = 0x400024d0;\nset_chanfreq = 0x400024d4;\nrom_rxiq_cover_mg_mp = 0x400024d8;\nrom_rfcal_rxiq = 0x400024dc;\nrom_get_rfcal_rxiq_data = 0x400024e0;\nrom_pbus_rx_dco_cal = 0x400024e4;\nrom_rxdc_est_min = 0x400024e8;\nrom_pbus_rx_dco_cal_1step = 0x400024ec;\nrom_set_lb_txiq = 0x400024f0;\nrom_set_rx_gain_cal_iq = 0x400024f4;\nrom_set_rx_gain_cal_dc = 0x400024f8;\niq_est_enable = 0x400024fc;\niq_est_disable = 0x40002500;\ndc_iq_est = 0x40002504;\nset_cal_rxdc = 0x40002508;\nrxiq_get_mis = 0x4000250c;\nspur_reg_write_one_tone = 0x40002510;\nspur_cal = 0x40002514;\nspur_coef_cfg = 0x40002518;\ngen_rx_gain_table = 0x4000251c;\nwr_rx_gain_mem = 0x40002520;\nset_rx_gain_param = 0x40002524;\nset_rx_gain_table = 0x40002528;\nrom_tester_wifi_cali = 0x4000252c;\nesp_recover_efuse_data = 0x40002530;\nbt_track_pll_cap = 0x40002534;\nrfpll_cap_track = 0x40002538;\nphy_param_track = 0x4000253c;\ntxpwr_correct = 0x40002540;\ntxpwr_cal_track = 0x40002544;\n\/* tx_pwctrl_background = 0x40002548;*\/\nbt_track_tx_power = 0x4000254c;\nwifi_track_tx_power = 0x40002550;\nrom_code_to_temp = 0x40002554;\nrom_tsens_index_to_dac = 0x40002558;\nrom_tsens_index_to_offset = 0x4000255c;\nrom_tsens_dac_cal = 0x40002560;\nrom_tsens_code_read = 0x40002564;\nrom_tsens_temp_read = 0x40002568;\nrom_temp_to_power = 0x4000256c;\ntsens_read_init = 0x40002570;\nget_temp_init = 0x40002574;\nrom_txiq_cover = 0x40002578;\nrom_rfcal_txiq = 0x4000257c;\nrom_get_power_atten = 0x40002580;\nrom_tx_pwctrl_init_cal = 0x40002584;\nbt_txdc_cal = 0x40002588;\nbt_txiq_cal = 0x4000258c;\ntxiq_cal_init = 0x40002590;\ntxdc_cal_init = 0x40002594;\ntxdc_cal_v70 = 0x40002598;\ntxiq_get_mis_pwr = 0x4000259c;\npwdet_ref_code = 0x400025a0;\npwdet_code_cal = 0x400025a4;\nrfcal_txcap = 0x400025a8;\ntx_cap_init = 0x400025ac;\nrfcal_pwrctrl = 0x400025b0;\ntx_pwctrl_init = 0x400025b4;\nbt_tx_pwctrl_init = 0x400025b8;\nbt_txpwr_freq = 0x400025bc;\nrom_txbbgain_to_index = 0x400025c0;\nrom_index_to_txbbgain = 0x400025c4;\nrom_bt_index_to_bb = 0x400025c8;\nrom_bt_bb_to_index = 0x400025cc;\nrom_bt_get_tx_gain = 0x400025d0;\nrom_get_tx_gain_value = 0x400025d4;\nrom_wifi_get_tx_gain = 0x400025d8;\nrom_set_tx_gain_mem = 0x400025dc;\nrom_get_rate_fcc_index = 0x400025e0;\nrom_get_chan_target_power = 0x400025e4;\nrom_wifi_tx_dig_gain = 0x400025e8;\nrom_wifi_set_tx_gain = 0x400025ec;\nrom_bt_set_tx_gain = 0x400025f0;\nwifi_11g_rate_chg = 0x400025f4;\nbt_chan_pwr_interp = 0x400025f8;\nbt_tx_gain_init = 0x400025fc;\n\/* Data (.data, .bss, .rodata) *\/\nphy_param_rom = 0x3fcdfaa4;\n\n\n\/***************************************\n Group rom_btbb\n ***************************************\/\n\n\/* Functions *\/\nbt_agc_gain_offset = 0x40002600;\nbt_agc_gain_max = 0x40002604;\nbt_set_rx_comp = 0x40002608;\nbt_agc_gain_set = 0x4000260c;\nbt_agc_rssi_thresh = 0x40002610;\nbt_agc_target_set = 0x40002614;\nbt_agc_restart_set = 0x40002618;\nbt_agc_recorrect_set = 0x4000261c;\nbt_agc_detect_set = 0x40002620;\nbt_bb_rx_correlator_set = 0x40002624;\nbt_bb_rx_dpo_set = 0x40002628;\nbt_bb_rx_filter_sel = 0x4000262c;\nbt_bb_rx_set1 = 0x40002630;\nbt_bb_v2_rx_set = 0x40002634;\nbt_bb_v2_tx_set = 0x40002638;\nbt_bb_tx_cca_set = 0x4000263c;\nbt_bb_tx_cca_period = 0x40002640;\nbt_bb_tx_cca_fifo_reset = 0x40002644;\nbt_bb_tx_cca_fifo_empty = 0x40002648;\nbt_bb_tx_cca_fifo_full = 0x4000264c;\nbt_bb_tx_cca_fifo_count = 0x40002650;\nbt_bb_tx_cca_fifo_read = 0x40002654;\ncoex_pti_v2 = 0x40002658;\nbt_bb_set_le_tx_on_delay = 0x4000265c;\nbt_bb_set_corr_thresh_le = 0x40002660;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9d8425bd72aa2fd530370ad77998ac29a865de83","subject":"put RODATA of libphy.a into DRAM","message":"put RODATA of libphy.a into DRAM\n\n    There are some RODATAs of libphy.a that are called in ISR. So need\n    to put them into DRAM to avoid access them when R\/W SPI flash. Due\n    to the RODATAs which are called in ISR haven't been picked out to\n    put into DRAM, put all of the RODATA of libphy.a into DRAM. This\n    will be optimized in the future.\n","repos":"tidyjiang8\/esp-idf-zh,ajs124\/esp-idf,ajs124\/esp-idf,armada-ai\/esp-idf,www220\/esp-idf,MIhanguangyi\/esp-idf,www220\/esp-idf,hwmaier\/esp-idf,hwmaier\/esp-idf,armada-ai\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,Hermiedapwdrman\/esp-idf,Hermiedapwdrman\/esp-idf,Hermiedapwdrman\/esp-idf,www220\/esp-idf,dschaefer\/esp-idf,dschaefer\/esp-idf,jaracil\/esp-idf,espressif\/esp-idf,jaracil\/esp-idf,shukyisme\/esp-idf-kwik,www220\/esp-idf,dschaefer\/esp-idf,tidyjiang8\/esp-idf-zh,tidyjiang8\/esp-idf-zh,empoweredhomes\/esp-idf,www220\/esp-idf,hwmaier\/esp-idf,nineisk\/esp-idf,empoweredhomes\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf,ajs124\/esp-idf,hwmaier\/esp-idf,shukyisme\/esp-idf-kwik,ajs124\/esp-idf,Hermiedapwdrman\/esp-idf,jaracil\/esp-idf,empoweredhomes\/esp-idf,nineisk\/esp-idf,shukyisme\/esp-idf-kwik,tidyjiang8\/esp-idf-zh,nineisk\/esp-idf,MIhanguangyi\/esp-idf,mashaoze\/esp-idf,dschaefer\/esp-idf,empoweredhomes\/esp-idf,MIhanguangyi\/esp-idf,shukyisme\/esp-idf-kwik,MIhanguangyi\/esp-idf,Hermiedapwdrman\/esp-idf,jaracil\/esp-idf,tidyjiang8\/esp-idf-zh,espressif\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,empoweredhomes\/esp-idf,dschaefer\/esp-idf,nineisk\/esp-idf,MIhanguangyi\/esp-idf,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,armada-ai\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libesp32.a:heap_alloc_caps.o(.literal .text .literal.* .text.*)\n    *libesp32.a:app_trace.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libesp32.a:app_trace.o(.rodata .rodata.*)\n    *libphy.a:(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","old_contents":"\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\nSECTIONS\n{\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors :\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } > iram0_0_seg\n\n  .iram0.text :\n  {\n    \/* Code marked as runnning out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *libfreertos.a:(.literal .text .literal.* .text.*)\n    *libesp32.a:panic.o(.literal .text .literal.* .text.*)\n    *libesp32.a:core_dump.o(.literal .text .literal.* .text.*)\n    *libesp32.a:heap_alloc_caps.o(.literal .text .literal.* .text.*)\n    *libesp32.a:app_trace.o(.literal .text .literal.* .text.*)\n    *libphy.a:(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:(.literal .text .literal.* .text.*)\n    *libhal.a:(.literal .text .literal.* .text.*)\n    *libspi_flash.a:spi_flash_rom_patch.o(.literal .text .literal.* .text.*)\n    _iram_text_end = ABSOLUTE(.);\n  } > iram0_0_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    *libesp32.a:panic.o(.rodata .rodata.*)\n    *libesp32.a:app_trace.o(.rodata .rodata.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >dram0_0_seg\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n  } >dram0_0_seg\n\n  .flash.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.irom1.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n    \/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } >drom0_0_seg\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.irom0.text) \/* catch stray ICACHE_RODATA_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } >iram0_2_seg\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4ca61a9d0e3f0f789e3da7931805bf2e96cef224","subject":"nrf5\/boards: Giving a bit more heap for nrf52840 linker script.","message":"nrf5\/boards: Giving a bit more heap for nrf52840 linker script.\n","repos":"adafruit\/circuitpython,tralamazza\/micropython,adafruit\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/micropython,tralamazza\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython","old_file":"nrf5\/boards\/nrf52840_aa.ld","new_file":"nrf5\/boards\/nrf52840_aa.ld","new_contents":"\/*\n    GNU linker script for NRF52840 blank w\/ no SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x0FF000 \/* 1020 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x040000 \/* 256 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 32K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20008000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52840 blank w\/ no SoftDevice\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x100000 \/* entire flash, 1 MiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x001000 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x0FF000 \/* 1020 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x040000 \/* 256 KiB *\/\n}\n\n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 16K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20005000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"87764298db0fb9766a15c7e1e75a88be7ca9ef59","subject":"init main() link script","message":"init main() link script\n","repos":"kbu1564\/NetOS","old_file":"src\/netos\/boot\/main.ld","new_file":"src\/netos\/boot\/main.ld","new_contents":"OUTPUT_FORMAT(\"elf32-i386\", \"elf32-i386\", \"elf32-i386\")\nOUTPUT_ARCH(i386)\nENTRY(main)\nSECTIONS\n{\n}\n\n","old_contents":"","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"26fb9786505af4e431e209fb162060a6ea31210d","subject":"edited linker script a little","message":"edited linker script a little\n","repos":"benaryorg\/benarydingOS,benaryorg\/benarydingOS,benaryorg\/benarydingOS,benaryorg\/benarydingOS","old_file":"src\/linker\/kernel.ld","new_file":"src\/linker\/kernel.ld","new_contents":"ENTRY(_start)\n\nSECTIONS\n{\n\t. = 0x100000;\n\t\n\t. = ALIGN(4096);\n\t_KERNEL_START = .;\n\n\t.text : {\n\t\t*(multiboot)\n\t\t*(.text)\n\t}\n\n\t.data ALIGN(4096) : {\n\t\t*(.data)\n\t}\n\n\t.rodata ALIGN(4096) : {\n\t\t*(.rodata)\n\t}\n\n\t.bss ALIGN(4096) : {\n\t\t*(.bss)\n\t}\n\n\t. = ALIGN(4096);\n\t_KERNEL_END = .;\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS\n{\n\t. = 0x100000;\n\t\n\t. = ALIGN(4096);\n\tkrnlstart=.;\n\n\t.text:\n\t{\n\t\t*(multiboot)\n\t\t*(.text)\n\t}\n\n\t.data ALIGN(4096):\n\t{\n\t\t*(.data)\n\t}\n\n\t.rodata ALIGN(4096):\n\t{\n\t\t*(.rodata)\n\t}\n\n\t.bss ALIGN(4096):\n\t{\n\t\t*(.bss)\n\t}\n\n\t. = ALIGN(4096);\n\tkrnlend=.;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8f9d79e0fd4717f96f6f67f4983b57f69ec8bd87","subject":"resize stack","message":"resize stack\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX64M\/R5F564ML.ld","new_file":"RX64M\/R5F564ML.ld","new_contents":"\/*!\t@file\n\t@brief\tRX64M R5F564ML \u30ea\u30f3\u30ab\u30fc\u30fb\u30b9\u30af\u30ea\u30d7\u30c8\n    @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\t@copyright\tCopyright (C) 2016, 2017 Kunihito Hiramatsu @n\n\t\t\t\tReleased under the MIT license @n\n\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x0007D000 \/* 512k - (USTACK+ISTACK)(0x2000) *\/\n\tUSTACK (w) : ORIGIN = 0x0007E000, LENGTH = 4 \/* ustack 8192 *\/\n\tISTACK (w) : ORIGIN = 0x00080000, LENGTH = 4 \/* istack 8192 *\/\n\tROM (w)    : ORIGIN = 0xFFC00000, LENGTH = 0x003FFFD0 \/* 4M *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .istack (ORIGIN (ISTACK)) :\n  {\n    PROVIDE (__istack = .);\n    *(.istack)\n  }\n\n  .ustack (ORIGIN (USTACK)) :\n  {\n    PROVIDE (__ustack = .);\n    *(.ustack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*!\t@file\n\t@brief\tRX64M R5F564ML \u30ea\u30f3\u30ab\u30fc\u30fb\u30b9\u30af\u30ea\u30d7\u30c8\n    @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\t@copyright\tCopyright (C) 2016, 2017 Kunihito Hiramatsu @n\n\t\t\t\tReleased under the MIT license @n\n\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x0007E000 \/* 512k - (USTACK+ISTACK)(0x2000) *\/\n\tUSTACK (w) : ORIGIN = 0x0007F800, LENGTH = 4 \/* ustack 6144 *\/\n\tISTACK (w) : ORIGIN = 0x00080000, LENGTH = 4 \/* istack 2048 *\/\n\tROM (w)    : ORIGIN = 0xFFC00000, LENGTH = 0x003FFFD0 \/* 4M *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .istack (ORIGIN (ISTACK)) :\n  {\n    PROVIDE (__istack = .);\n    *(.istack)\n  }\n\n  .ustack (ORIGIN (USTACK)) :\n  {\n    PROVIDE (__ustack = .);\n    *(.ustack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"a5f7a0f7913900c371f44de4de5bb42e4e2dac32","subject":"[sw] Update linker scripts for DWARF version 5","message":"[sw] Update linker scripts for DWARF version 5\n\nRecent versions of Clang started defaulting to the DWARF debug format\nversion 5. When emitting DWARF 5 clang emits two new debug sections.\nThis patch includes those new sections in the linked ELF files, for\nproper debug support and to fix build failures caused by warnings of\norphan sections.\n\nSigned-off-by: Lu\u00eds Marques <3b3ecfbddc4b81704f7616abd2273612f2861878@lowrisc.org>\n","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan","old_file":"sw\/device\/info_sections.ld","new_file":"sw\/device\/info_sections.ld","new_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * Partial Linker Script for OpenTitan Device Executables\n *\n * This Linker Script controls all the sections that we need in the ELF file for\n * a device executable, but which are not mapped into memory or otherwise\n * allocated on the device itself.\n *\n * These contain amongst other things:\n * - debugging information needed by DV logging,\n * - DWARF Sections\n * - RISC-V Attributes sections\n *\n * This is also where we specify the sections to discard, because it is a common\n * file between all our other linker scripts.\n *\n * This partial linker script requires the main linker script to define the\n * following symbols:\n * - _dv_log_offset\n *\/\n\n\/*\n * Start DV Sections.\n *\n * The following sections are used by DV to implement logging in an\n * alternate way, which enables simulation speed up by completely avoiding\n * any string format processing or even the actual transmission of log data\n * to a real peripheral.\n *\n * These sections are marked as dummy so that they can still be extracted\n * using readelf or similar utilities. As such, the content in these sections\n * is not relevant for the actual SW code and can be safely discarded.\n *\/\n\n\/**\n * The following section contains log fields constructed from the logs using\n * the log_fields_t struct defined in sw\/device\/lib\/runtime\/log.h. The size of\n * each log field is fixed - 20 bytes.\n *\/\n.logs.fields _dv_log_offset (INFO): {\n  \/* Force this section to always be emitted. The logs extraction script expects\n   * this section to be present in the ELF file, but the linker will not emit it\n   * if there are no outputs (i.e, the *(.logs.fields) statement) with contents.\n   *\n   * However, almost any assignment will implicitly create even an empty section,\n   * including the very silly . = . (set the program counter to itself).\n   * \n   * See https:\/\/sourceware.org\/binutils\/docs-2.29\/ld\/Output-Section-Discarding.html. *\/\n  . = .;\n  *(.logs.fields)\n}\n\n\/*\n * End DV Sections\n *\/\n\n\/* ELF-internal Sections. *\/\n.symtab 0x0 : { *(.symtab) }\n.strtab 0x0 : { *(.strtab) }\n.shstrtab 0x0 : { *(.shstrtab) }\n\n\/* Preserve RISC-V Attributes *\/\n.riscv.attributes 0x0 : { *(.riscv.attributes) }\n\n\/* Preserve Debug Info in ELF Files *\/\n.debug_info 0x0 : { *(.debug_info) }\n.debug_abbrev 0x0 : { *(.debug_abbrev) }\n.debug_aranges 0x0 : { *(.debug_aranges) }\n.debug_line 0x0 : { *(.debug_line) }\n.debug_loc 0x0 : { *(.debug_loc) }\n.debug_ranges 0x0 : { *(.debug_ranges) }\n.debug_str 0x0 : { *(.debug_str) }\n.debug_frame 0x0 : { *(.debug_frame) }\n.debug_line_str 0x0 : { *(.debug_line_str) }\n.debug_loclists 0x0 : { *(.debug_loclists) }\n.debug_rnglists 0x0 : { *(.debug_rnglists) }\n.debug_addr 0x0 : { *(.debug_addr) }\n.debug_str_offsets 0x0 : { *(.debug_str_offsets) }\n\n\/* Discarded Sections (Not needed in device images). *\/\n\/DISCARD\/ : {\n  \/* We don't keep unwind information *\/\n  *(.eh_frame)\n  *(.eh_frame_hdr)\n\n  \/* Compiler Information *\/\n  *(.comment)\n  *(.comment.*)\n\n  \/* Other Notes *\/\n  *(.note)\n  *(.note.*)\n\n  \/* Relocations *\/\n  *(.rela.*)\n  *(.rela.dyn)\n\n  \/* STAB Debugging Info - We Use DWARF *\/\n  *(.stab)\n  *(.stab.*)\n  *(.stabstr)\n\n  \/* COMMON Sections *\/\n  *(COMMON)\n}\n","old_contents":"\/* Copyright lowRISC contributors. *\/\n\/* Licensed under the Apache License, Version 2.0, see LICENSE for details. *\/\n\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n\/**\n * Partial Linker Script for OpenTitan Device Executables\n *\n * This Linker Script controls all the sections that we need in the ELF file for\n * a device executable, but which are not mapped into memory or otherwise\n * allocated on the device itself.\n *\n * These contain amongst other things:\n * - debugging information needed by DV logging,\n * - DWARF Sections\n * - RISC-V Attributes sections\n *\n * This is also where we specify the sections to discard, because it is a common\n * file between all our other linker scripts.\n *\n * This partial linker script requires the main linker script to define the\n * following symbols:\n * - _dv_log_offset\n *\/\n\n\/*\n * Start DV Sections.\n *\n * The following sections are used by DV to implement logging in an\n * alternate way, which enables simulation speed up by completely avoiding\n * any string format processing or even the actual transmission of log data\n * to a real peripheral.\n *\n * These sections are marked as dummy so that they can still be extracted\n * using readelf or similar utilities. As such, the content in these sections\n * is not relevant for the actual SW code and can be safely discarded.\n *\/\n\n\/**\n * The following section contains log fields constructed from the logs using\n * the log_fields_t struct defined in sw\/device\/lib\/runtime\/log.h. The size of\n * each log field is fixed - 20 bytes.\n *\/\n.logs.fields _dv_log_offset (INFO): {\n  \/* Force this section to always be emitted. The logs extraction script expects\n   * this section to be present in the ELF file, but the linker will not emit it\n   * if there are no outputs (i.e, the *(.logs.fields) statement) with contents.\n   *\n   * However, almost any assignment will implicitly create even an empty section,\n   * including the very silly . = . (set the program counter to itself).\n   * \n   * See https:\/\/sourceware.org\/binutils\/docs-2.29\/ld\/Output-Section-Discarding.html. *\/\n  . = .;\n  *(.logs.fields)\n}\n\n\/*\n * End DV Sections\n *\/\n\n\/* ELF-internal Sections. *\/\n.symtab 0x0 : { *(.symtab) }\n.strtab 0x0 : { *(.strtab) }\n.shstrtab 0x0 : { *(.shstrtab) }\n\n\/* Preserve RISC-V Attributes *\/\n.riscv.attributes 0x0 : { *(.riscv.attributes) }\n\n\/* Preserve Debug Info in ELF Files *\/\n.debug_info 0x0 : { *(.debug_info) }\n.debug_abbrev 0x0 : { *(.debug_abbrev) }\n.debug_aranges 0x0 : { *(.debug_aranges) }\n.debug_line 0x0 : { *(.debug_line) }\n.debug_loc 0x0 : { *(.debug_loc) }\n.debug_ranges 0x0 : { *(.debug_ranges) }\n.debug_str 0x0 : { *(.debug_str) }\n.debug_frame 0x0 : { *(.debug_frame) }\n.debug_line_str 0x0 : { *(.debug_line_str) }\n.debug_loclists 0x0 : { *(.debug_loclists) }\n.debug_rnglists 0x0 : { *(.debug_rnglists) }\n\n\/* Discarded Sections (Not needed in device images). *\/\n\/DISCARD\/ : {\n  \/* We don't keep unwind information *\/\n  *(.eh_frame)\n  *(.eh_frame_hdr)\n\n  \/* Compiler Information *\/\n  *(.comment)\n  *(.comment.*)\n\n  \/* Other Notes *\/\n  *(.note)\n  *(.note.*)\n\n  \/* Relocations *\/\n  *(.rela.*)\n  *(.rela.dyn)\n\n  \/* STAB Debugging Info - We Use DWARF *\/\n  *(.stab)\n  *(.stab.*)\n  *(.stabstr)\n\n  \/* COMMON Sections *\/\n  *(COMMON)\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b23784bf7e463fc51e5ef7309825032ef7dc2d39","subject":"nios2: add _image_rodata_start\/end to linker script","message":"nios2: add _image_rodata_start\/end to linker script\n\nThis adds the _image_rodata_start and _image_rodata_end\nsymbols to NIOS2's linker script.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr","old_file":"include\/arch\/nios2\/linker.ld","new_file":"include\/arch\/nios2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specific linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to\n     * 'nios2-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n        {\n        *(.plt)\n        }\n\n    SECTION_PROLOGUE(.iplt,,)\n        {\n        *(.iplt)\n        }\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n#ifndef CONFIG_XIP\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined(CONFIG_GP_ALL_DATA)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        . = ALIGN(4);\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n        . = ALIGN(4);\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_DATA_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n\n#include <linker\/common-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n        *(.data)\n        *(\".data.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        \/* the Nios2 architecture only has 16-bit signed immediate offsets in\n         * the instructions, so accessing a general address requires typically\n         * three instructions - basically, two for the two halves of the 32-bit\n         * address, and one to merge them - but if we can put the most commonly\n         * accessed globals in a special 64K span of memory addressed by the GP\n         * register, then we can access those values in a single instruction,\n         * saving both codespace and runtime.\n         *\n         * Since these immediate offsets are signed, place gp 0x8000 past the\n         * beginning of .sdata so that we can use both positive and negative\n         * offsets.\n         *\/\n#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n        *(.sdata .sdata.* .gnu.linkonce.s.*)\n        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_ram_end = .;\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.sbss)\n        *(\".sbss.*\")\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2016 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Nios II platform\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* These sections are specific to this CPU *\/\n#define _EXCEPTION_SECTION_NAME exceptions\n#define _RESET_SECTION_NAME reset\n\n\/* This linker script requires the following macros to be defined in the\n * SOC-specific linker script. All of these values can be found defined\n * in system.h for CPU configurations that can generate a HAL.\n *\n * _RESET_VECTOR     CPU entry point at boot\n * _EXC_VECTOR       General exception vector\n * _ROM_ADDR         Beginning of flash memory\n * _ROM_SIZE         Size in bytes of flash memory\n * _RAM_ADDR         Beginning of RAM\n * _RAM_SIZE         Size of RAM in bytes\n *\n * For now we support two scenarios:\n *\n * 1. Non-XIP systems where the reset vector is at the beginning of RAM\n * with the exception vector 0x20 bytes after it.\n * 2. XIP systems where the reset vector is at the beginning of ROM and\n * the exception vector is in RAM\n *\/\n\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION FLASH\n\t#define RAMABLE_REGION SRAM\n#else\n\t#define ROMABLE_REGION SRAM\n\t#define RAMABLE_REGION SRAM\n#endif\n\n#ifdef CONFIG_XIP\n\nASSERT(_RESET_VECTOR == _ROM_ADDR, \"Reset vector not at beginning of ROM!\")\n\nMEMORY\n    {\n    RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n\n    }\n\n#else\n\nMEMORY\n    {\n    RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20\n    SRAM  (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to\n     * 'nios2-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n        {\n        *(.plt)\n        }\n\n    SECTION_PROLOGUE(.iplt,,)\n        {\n        *(.iplt)\n        }\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = _ROM_ADDR;\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n        KEEP(*(.reset.*))\n    } GROUP_LINK_IN(RESET)\n\n#ifndef CONFIG_XIP\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n        {\n        \/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR\n         * we are going to waste flash space? *\/\n        . = ALT_CPU_RESET_ADDR;\n\n        _image_text_start = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#if defined(CONFIG_GP_ALL_DATA)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n        {\n        . = ALIGN(4);\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n        . = ALIGN(4);\n        } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rom_end = .;\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_XIP\n    \/* Altera strongly recommends keeping exception entry code in RAM\n     * even on XIP systems\n     *\n     * This is code not data, but we need this copied just like XIP data\n     *\/\n\n    SECTION_DATA_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n        {\n            _image_ram_start = .;\n            __data_ram_start = .;\n\n            KEEP(*(\".exception.entry.*\"))\n            *(\".exception.other.*\")\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#ifndef CONFIG_XIP\n        _image_ram_start = .;\n#endif\n\n#include <linker\/common-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n        {\n        *(.data)\n        *(\".data.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        \/* the Nios2 architecture only has 16-bit signed immediate offsets in\n         * the instructions, so accessing a general address requires typically\n         * three instructions - basically, two for the two halves of the 32-bit\n         * address, and one to merge them - but if we can put the most commonly\n         * accessed globals in a special 64K span of memory addressed by the GP\n         * register, then we can access those values in a single instruction,\n         * saving both codespace and runtime.\n         *\n         * Since these immediate offsets are signed, place gp 0x8000 past the\n         * beginning of .sdata so that we can use both positive and negative\n         * offsets.\n         *\/\n#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL)\n        _gp = ABSOLUTE(. + 0x8000);\n        PROVIDE(gp = _gp);\n#endif\n\n        *(.sdata .sdata.* .gnu.linkonce.s.*)\n        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_ram_end = .;\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        *(.sbss)\n        *(\".sbss.*\")\n        *(.bss)\n        *(\".bss.*\")\n        COMMON_SYMBOLS\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n    \/* Define linker symbols *\/\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5bf49babd0caf61f1702c7d175e2eed327b521d0","subject":"rad1o-badge: fix the linker scripts to work with nosys","message":"rad1o-badge: fix the linker scripts to work with nosys\n","repos":"dominicgs\/GreatFET-experimental,dominicgs\/GreatFET-experimental,greatscottgadgets\/greatfet,dominicgs\/GreatFET-experimental,greatscottgadgets\/greatfet,greatscottgadgets\/greatfet,greatscottgadgets\/greatfet","old_file":"firmware\/common\/LPC43xx_l0adable.ld","new_file":"firmware\/common\/LPC43xx_l0adable.ld","new_contents":"\/*\n * This file is part of the libopencm3 project.\n *\n * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>\n * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>\n * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>\n * Copyright (C) 2012 Jared Boone <jared@sharebrained.com>\n *\n * This library is free software: you can redistribute it and\/or modify\n * it under the terms of the GNU Lesser General Public License as published by\n * the Free Software Foundation, either version 3 of the License, or\n * (at your option) any later version.\n *\n * This library is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU Lesser General Public License for more details.\n *\n * You should have received a copy of the GNU Lesser General Public License\n * along with this library.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n *\/\n\n\/* Generic linker script for LPC43XX targets using libopencm3. *\/\n\n\/* Memory regions must be defined in the ld script which includes this one. *\/\n\n\/* Enforce emmission of the vector table. *\/\nEXTERN (vector_table)\nEXTERN (JumpTable)\n\n\/* Define the entry point of the output file. *\/\nENTRY(reset_handler)\n\n\/* Define sections. *\/\nSECTIONS\n{\n\t.vect : {\n\t\t_text_ram = 0; \/* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled *\/\n\t\t. = ALIGN(0x400);\n\t\t*(.vectors)\t\/* Vector table *\/\n\t} > ram_local1\n\n\t.jump : {\n\t\tKEEP(*(.jump))\t\/* Jump table *\/\n\t} > ram_local1\n\n\t.text : {\n\t\t*(.text*)\t\/* Program code *\/\n\t\t. = ALIGN(4);\n\t\t*(.rodata*)\t\/* Read-only data *\/\n\t\t. = ALIGN(4);\n\t} >ram_local1\n\n\t\/* C++ Static constructors\/destructors, also used for __attribute__\n\t * ((constructor)) and the likes *\/\n\t.preinit_array : {\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t} >ram_local1\n\t.init_array : {\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\t} >ram_local1\n\t.fini_array : {\n\t\t. = ALIGN(4);\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\t} >ram_local1\n\n\t\/*\n\t * Another section used by C++ stuff, appears when using newlib with\n\t * 64bit (long long) printf support\n\t *\/\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} >ram_local1\n    \n\t\/* exception index - required due to libgcc.a issuing \/0 exceptions *\/\n\t.ARM.exidx : {\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx*)\n\t\t__exidx_end = .;\n\t} >ram_local1\n\n\t. = ALIGN(4);\n\t_etext = .;\n\t_etext_ram = 0; \/* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled *\/\n\t_etext_rom = 0; \/* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled *\/\n\n\t. = ORIGIN(ram_local2);\n\n\t.data : {\n\t\t_data = .;\n\t\t*(.data*)\t\/* Read-write initialized data *\/\n\t\t. = ALIGN(4);\n\t\t_edata = .;\n\t} >ram_local2 AT >ram_local1\n\t_data_loadaddr = LOADADDR(.data);\n\n\/*\t_data_rom = LOADADDR (.data) + ORIGIN(rom);\n\t_edata_rom = _data_rom + SIZEOF (.data); *\/\n\n\t.bss : {\n\t\t_bss = .;\n\t\t*(.bss*)\t\/* Read-write zero initialized data *\/\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t} >ram_local2\n\n\t\/* exception unwind data - required due to libgcc.a issuing \/0 exceptions *\/\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} >ram_local2\n\n\t\/*\n\t * The .eh_frame section appears to be used for C++ exception handling.\n\t * You may need to fix this if you're using C++.\n\t *\/\n\t\/DISCARD\/ : { *(.eh_frame) }\n\n\t. = ALIGN(4);\n\tend = .;\n\n\t\/* Leave room above stack for IAP to run. *\/\n\t__StackTop = ORIGIN(ram_local2) + LENGTH(ram_local2) - 32;\n\tPROVIDE(_stack = __StackTop);\n\t_l0dable_start = ORIGIN(ram_l0dable);\n\t_l0dable_len = LENGTH(ram_l0dable);\n\t_jumptable_len = SIZEOF(.jump);\n}\n","old_contents":"\/*\n * This file is part of the libopencm3 project.\n *\n * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>\n * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>\n * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>\n * Copyright (C) 2012 Jared Boone <jared@sharebrained.com>\n *\n * This library is free software: you can redistribute it and\/or modify\n * it under the terms of the GNU Lesser General Public License as published by\n * the Free Software Foundation, either version 3 of the License, or\n * (at your option) any later version.\n *\n * This library is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU Lesser General Public License for more details.\n *\n * You should have received a copy of the GNU Lesser General Public License\n * along with this library.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\n *\/\n\n\/* Generic linker script for LPC43XX targets using libopencm3. *\/\n\n\/* Memory regions must be defined in the ld script which includes this one. *\/\n\n\/* Enforce emmission of the vector table. *\/\nEXTERN (vector_table)\nEXTERN (JumpTable)\n\n\/* Define the entry point of the output file. *\/\nENTRY(reset_handler)\n\n\/* Define sections. *\/\nSECTIONS\n{\n\t.vect : {\n\t\t_text_ram = 0; \/* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled *\/\n\t\t. = ALIGN(0x400);\n\t\t*(.vectors)\t\/* Vector table *\/\n\t} > ram_local1\n\n\t.jump : {\n\t\tKEEP(*(.jump))\t\/* Jump table *\/\n\t} > ram_local1\n\n\t.text : {\n\t\t*(.text*)\t\/* Program code *\/\n\t\t. = ALIGN(4);\n\t\t*(.rodata*)\t\/* Read-only data *\/\n\t\t. = ALIGN(4);\n\t} >ram_local1\n\n\t\/* C++ Static constructors\/destructors, also used for __attribute__\n\t * ((constructor)) and the likes *\/\n\t.preinit_array : {\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\t} >ram_local1\n\t.init_array : {\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\t} >ram_local1\n\t.fini_array : {\n\t\t. = ALIGN(4);\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\t} >ram_local1\n\n\t\/*\n\t * Another section used by C++ stuff, appears when using newlib with\n\t * 64bit (long long) printf support\n\t *\/\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} >ram_local1\n    \n\t\/* exception index - required due to libgcc.a issuing \/0 exceptions *\/\n\t.ARM.exidx : {\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx*)\n\t\t__exidx_end = .;\n\t} >ram_local1\n\n\t. = ALIGN(4);\n\t_etext = .;\n\t_etext_ram = 0; \/* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled *\/\n\t_etext_rom = 0; \/* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled *\/\n\n\t. = ORIGIN(ram_local2);\n\n\t.data : {\n\t\t_data = .;\n\t\t*(.data*)\t\/* Read-write initialized data *\/\n\t\t. = ALIGN(4);\n\t\t_edata = .;\n\t} >ram_local2 AT >ram_local1\n\t_data_loadaddr = LOADADDR(.data);\n\n\/*\t_data_rom = LOADADDR (.data) + ORIGIN(rom);\n\t_edata_rom = _data_rom + SIZEOF (.data); *\/\n\n\t.bss : {\n\t\t_bss = .;\n\t\t*(.bss*)\t\/* Read-write zero initialized data *\/\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t_ebss = .;\n\t} >ram_local2\n\n\t\/* exception unwind data - required due to libgcc.a issuing \/0 exceptions *\/\n\t.ARM.extab : {\n\t\t*(.ARM.extab*)\n\t} >ram_local2\n\n\t\/*\n\t * The .eh_frame section appears to be used for C++ exception handling.\n\t * You may need to fix this if you're using C++.\n\t *\/\n\t\/DISCARD\/ : { *(.eh_frame) }\n\n\t. = ALIGN(4);\n\t_end = .;\n\n\t\/* Leave room above stack for IAP to run. *\/\n\t__StackTop = ORIGIN(ram_local2) + LENGTH(ram_local2) - 32;\n\tPROVIDE(_stack = __StackTop);\n\t_l0dable_start = ORIGIN(ram_l0dable);\n\t_l0dable_len = LENGTH(ram_l0dable);\n\t_jumptable_len = SIZEOF(.jump);\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c56346e5507a5612f061e1372f9c7c43bf0e8338","subject":"Provide explicit symbols for start and end of bss and data regions","message":"Provide explicit symbols for start and end of bss and data regions\n","repos":"smaccm\/camkes-tool,smaccm\/camkes-tool,smaccm\/camkes-tool,smaccm\/camkes-tool","old_file":"camkes\/templates\/linker.lds","new_file":"camkes\/templates\/linker.lds","new_contents":"\/*#\n *# Copyright 2014, NICTA\n *#\n *# This software may be distributed and modified according to the terms of\n *# the BSD 2-Clause license. Note that NO WARRANTY is provided.\n *# See \"LICENSE_BSD2.txt\" for details.\n *#\n *# @TAG(NICTA_BSD)\n #*\/\n\n\/* Linker script for CAmkES components. *\/\nENTRY(_start)\n\nSECTIONS {\n    \/* __executable_start is required by libsel4platsupport. *\/\n    PROVIDE (__executable_start = 0x100000);\n    . = 0x100000;\n\n    \/* Code. *\/\n    .text : ALIGN(4096) {\n        *(.text*)\n    }\n\n    \/* Read Only Data. *\/\n    .rodata : ALIGN(4096) {\n        *(.rodata*)\n    }\n\n    \/*- if arch == 'arm' -*\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n    PROVIDE_HIDDEN (__exidx_end = .);\n    \/*- endif -*\/\n\n    \/* Data \/ BSS *\/\n    .data : ALIGN(4096) {\n        PROVIDE(__data_start = .);\n        *(.data)\n        PROVIDE(__data_end = .);\n    }\n\n    .bss : {\n        PROVIDE(__bss_start = .);\n        *(.bss)\n        *(COMMON)\n        PROVIDE(__bss_end = .);\n    }\n\n    guarded (NOLOAD) : ALIGN(4096) {\n        *(guarded)\n    }\n\n    \/*- for c in composition.connections -*\/\n    \/*- if c.type.name == 'seL4SharedData' -*\/\n      \/*- if c.from_instance == me -*\/\n    shared_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000) {\n        *(shared_\/*? c.from_interface.name ?*\/)\n    }\n      \/*- endif -*\/\n      \/*- if c.to_instance == me -*\/\n    shared_\/*? c.to_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000) {\n        *(shared_\/*? c.to_interface.name ?*\/)\n    }\n      \/*- endif -*\/\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    persistent (NOLOAD) : ALIGN(0x1000) {\n        *(persistent)\n    }\n\n    \/*- for c in composition.connections -*\/\n    \/*- if c.type.name == 'seL4HardwareMMIO' and c.from_instance == me -*\/\n    \/*- if arch == 'arm' -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x100000) { \/*# ARM Section Size #*\/\n    \/*- else -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x400000) { \/*# IA32 4M Page Size #*\/\n    \/*- endif -*\/\n        *(ignore_\/*? c.from_interface.name ?*\/)\n    }\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    _end = .;\n}\n","old_contents":"\/*#\n *# Copyright 2014, NICTA\n *#\n *# This software may be distributed and modified according to the terms of\n *# the BSD 2-Clause license. Note that NO WARRANTY is provided.\n *# See \"LICENSE_BSD2.txt\" for details.\n *#\n *# @TAG(NICTA_BSD)\n #*\/\n\n\/* Linker script for CAmkES components. *\/\nENTRY(_start)\n\nSECTIONS {\n    \/* __executable_start is required by libsel4platsupport. *\/\n    PROVIDE (__executable_start = 0x100000);\n    . = 0x100000;\n\n    \/* Code. *\/\n    .text : ALIGN(4096) {\n        *(.text*)\n    }\n\n    \/* Read Only Data. *\/\n    .rodata : ALIGN(4096) {\n        *(.rodata*)\n    }\n\n    \/*- if arch == 'arm' -*\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n    PROVIDE_HIDDEN (__exidx_end = .);\n    \/*- endif -*\/\n\n    \/* Data \/ BSS *\/\n    .data : ALIGN(4096) {\n        *(.data)\n    }\n\n    .bss : {\n        *(.bss)\n        *(COMMON)\n    }\n\n    guarded (NOLOAD) : ALIGN(4096) {\n        *(guarded)\n    }\n\n    \/*- for c in composition.connections -*\/\n    \/*- if c.type.name == 'seL4SharedData' -*\/\n      \/*- if c.from_instance == me -*\/\n    shared_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000) {\n        *(shared_\/*? c.from_interface.name ?*\/)\n    }\n      \/*- endif -*\/\n      \/*- if c.to_instance == me -*\/\n    shared_\/*? c.to_interface.name ?*\/ (NOLOAD) : ALIGN(0x1000) {\n        *(shared_\/*? c.to_interface.name ?*\/)\n    }\n      \/*- endif -*\/\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    persistent (NOLOAD) : ALIGN(0x1000) {\n        *(persistent)\n    }\n\n    \/*- for c in composition.connections -*\/\n    \/*- if c.type.name == 'seL4HardwareMMIO' and c.from_instance == me -*\/\n    \/*- if arch == 'arm' -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x100000) { \/*# ARM Section Size #*\/\n    \/*- else -*\/\n    ignore_\/*? c.from_interface.name ?*\/ (NOLOAD) : ALIGN(0x400000) { \/*# IA32 4M Page Size #*\/\n    \/*- endif -*\/\n        *(ignore_\/*? c.from_interface.name ?*\/)\n    }\n    \/*- endif -*\/\n    \/*- endfor -*\/\n\n    _end = .;\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"59b3f7f476751bf660e00406f9afba6ca7bddd70","subject":"Set the ELF entry point in simple system linker script","message":"Set the ELF entry point in simple system linker script\n\nThis is part of work to run binaries created for the simple system\nunder Spike. Spike's default behaviour (after a weird 'rom' trampoline\nat 0x1000) is to obey the entry point given in the ELF file. So let's\nset it correctly.\n","repos":"AmbiML\/ibex,lowRISC\/ibex,lowRISC\/ibex,lowRISC\/ibex,AmbiML\/ibex,lowRISC\/ibex,AmbiML\/ibex,AmbiML\/ibex","old_file":"examples\/sw\/simple_system\/common\/link.ld","new_file":"examples\/sw\/simple_system\/common\/link.ld","new_contents":"\/* Copyright lowRISC contributors.\n   Licensed under the Apache License, Version 2.0, see LICENSE for details.\n   SPDX-License-Identifier: Apache-2.0 *\/\n\nOUTPUT_ARCH(riscv)\n\nMEMORY\n{\n    \/* 992 kB should be enough for anybody... *\/\n    ram         : ORIGIN = 0x00100000, LENGTH = 0xF8000 \/* 992 kB *\/\n    stack       : ORIGIN = 0x001F8000, LENGTH = 0x8000  \/* 32 kB *\/\n}\n\n\/* Stack information variables *\/\n_min_stack      = 0x2000;   \/* 8K - minimum stack space to reserve *\/\n_stack_len     = LENGTH(stack);\n_stack_start   = ORIGIN(stack) + LENGTH(stack);\n\n_entry_point = _vectors_start + 0x80;\nENTRY(_entry_point)\n\nSECTIONS\n{\n    .vectors :\n    {\n        . = ALIGN(4);\n\t\t_vectors_start = .;\n        KEEP(*(.vectors))\n\t\t_vectors_end = .;\n    } > ram\n\n    .text : {\n        . = ALIGN(4);\n        *(.text)\n        *(.text.*)\n    }  > ram\n\n    .rodata : {\n        . = ALIGN(4);\n        *(.rodata);\n        *(.rodata.*)\n    } > ram\n\n    .data : {\n        . = ALIGN(4);\n        *(.data);\n        *(.data.*)\n    } > ram\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        _bss_end = .;\n    } > ram\n\n    \/* ensure there is enough room for stack *\/\n    .stack (NOLOAD): {\n        . = ALIGN(4);\n        . = . + _min_stack ;\n        . = ALIGN(4);\n        stack = . ;\n        _stack = . ;\n    } > stack\n}\n","old_contents":"\/* Copyright lowRISC contributors.\n   Licensed under the Apache License, Version 2.0, see LICENSE for details.\n   SPDX-License-Identifier: Apache-2.0 *\/\n\nOUTPUT_ARCH(riscv)\n\nMEMORY\n{\n    \/* 992 kB should be enough for anybody... *\/\n    ram         : ORIGIN = 0x00100000, LENGTH = 0xF8000 \/* 992 kB *\/\n    stack       : ORIGIN = 0x001F8000, LENGTH = 0x8000  \/* 32 kB *\/\n}\n\n\/* Stack information variables *\/\n_min_stack      = 0x2000;   \/* 8K - minimum stack space to reserve *\/\n_stack_len     = LENGTH(stack);\n_stack_start   = ORIGIN(stack) + LENGTH(stack);\n\nSECTIONS\n{\n    .vectors :\n    {\n        . = ALIGN(4);\n        KEEP(*(.vectors))\n    } > ram\n\n    .text : {\n        . = ALIGN(4);\n        *(.text)\n        *(.text.*)\n    }  > ram\n\n    .rodata : {\n        . = ALIGN(4);\n        *(.rodata);\n        *(.rodata.*)\n    } > ram\n\n    .data : {\n        . = ALIGN(4);\n        *(.data);\n        *(.data.*)\n    } > ram\n\n    .bss :\n    {\n        . = ALIGN(4);\n        _bss_start = .;\n        *(.bss)\n        *(.bss.*)\n        *(COMMON)\n        _bss_end = .;\n    } > ram\n\n    \/* ensure there is enough room for stack *\/\n    .stack (NOLOAD): {\n        . = ALIGN(4);\n        . = . + _min_stack ;\n        . = ALIGN(4);\n        stack = . ;\n        _stack = . ;\n    } > stack\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8aeb54b49c59a41bba99b563fbdb60a4116dd882","subject":"Delete flash file","message":"Delete flash file\n","repos":"wht4\/c_stm32l053_blinky,wht4\/c_stm32l053_blinky,wht4\/c_stm32l053_blinky","old_file":"stm32_flash.ld","new_file":"stm32_flash.ld","new_contents":"","old_contents":"\/*\n*****************************************************************************\n**\n**  File        : stm32_flash.ld\n**\n**  Abstract    : Linker script for STM32L053C8 Device with\n**                64KByte FLASH, 8KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Environment : Atollic TrueSTUDIO(R)\n**\n**  Distribution: The file is distributed \"as is\", without any warranty\n**                of any kind.\n**\n**  (c)Copyright Atollic AB.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. This file may only be built (assembled or compiled and linked)\n**  using the Atollic TrueSTUDIO(R) product. The use of this file together\n**  with other tools than Atollic TrueSTUDIO(R) is not permitted.\n**\n*****************************************************************************\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Highest address of the user mode stack *\/\n_estack = 0x20002000;    \/* end of 8K RAM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_Min_Heap_Size = 0;      \/* required amount of heap  *\/\n_Min_Stack_Size = 0x80; \/* required amount of stack *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 64K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 8K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n  } >FLASH\n\n  \/* Constant data goes into FLASH *\/\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  \/* used by the startup to initialize data *\/\n  _sidata = LOADADDR(.data);\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >RAM AT> FLASH\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n  } >RAM\n\n  \/* User_heap_stack section, used to check that there is enough RAM left *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  \/* MEMORY_bank1 section, code must be located here explicitly            *\/\n  \/* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); *\/\n  .memory_b1_text :\n  {\n    *(.mb1text)        \/* .mb1text sections (code) *\/\n    *(.mb1text*)       \/* .mb1text* sections (code)  *\/\n    *(.mb1rodata)      \/* read-only data (constants) *\/\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  \/* Remove information from the standard libraries *\/\n  \/DISCARD\/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"50589cb7c507d98f1ddaa817d042cd7bd30435cf","subject":"Update the linker script - Vector table went missing due to the dev tools upgrade.","message":"Update the linker script - Vector table went missing due to the dev tools upgrade.","repos":"rbsexton\/gecko,rbsexton\/gecko,rbsexton\/gecko","old_file":"zero\/pwmclock\/launcher\/efm32zg.ld","new_file":"zero\/pwmclock\/launcher\/efm32zg.ld","new_contents":"\/* Linker script for Silicon Labs EFM32ZG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 4.1.0 *\/\r\n\/*                                                                  *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 12288\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 4096\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n *\r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __copy_table_start__\r\n *   __copy_table_end__\r\n *   __zero_table_start__\r\n *   __zero_table_end__\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *   __Vectors_End\r\n *   __Vectors_Size\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.vectors))\r\n    __Vectors_End = .;\r\n    __Vectors_Size = __Vectors_End - __Vectors;\r\n    __end__ = .;\r\n\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  \/* To copy multiple ROM to RAM sections,\r\n   * uncomment .copy.table section and,\r\n   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .copy.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __copy_table_start__ = .;\r\n    LONG (__etext)\r\n    LONG (__data_start__)\r\n    LONG (__data_end__ - __data_start__)\r\n    LONG (__etext2)\r\n    LONG (__data2_start__)\r\n    LONG (__data2_end__ - __data2_start__)\r\n    __copy_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  \/* To clear multiple BSS sections,\r\n   * uncomment .zero.table section and,\r\n   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S *\/\r\n  \/*\r\n  .zero.table :\r\n  {\r\n    . = ALIGN(4);\r\n    __zero_table_start__ = .;\r\n    LONG (__bss_start__)\r\n    LONG (__bss_end__ - __bss_start__)\r\n    LONG (__bss2_start__)\r\n    LONG (__bss2_end__ - __bss2_start__)\r\n    __zero_table_end__ = .;\r\n  } > FLASH\r\n  *\/\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    KEEP(*(.jcr*))\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap (COPY):\r\n  {\r\n    __HeapBase = .;\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    KEEP(*(.heap*))\r\n    __HeapLimit = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy (COPY):\r\n  {\r\n    KEEP(*(.stack*))\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","old_contents":"\/* Linker script for Silicon Labs EFM32ZG devices *\/\r\n\/*                                                                  *\/\r\n\/* This file is subject to the license terms as defined in ARM's    *\/\r\n\/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       *\/\r\n\/* Example Code.                                                    *\/\r\n\/*                                                                  *\/\r\n\/* Silicon Laboratories, Inc. 2015                                  *\/\r\n\/*                                                                  *\/\r\n\/* Version 3.20.12 *\/\r\n\/*                                                                  *\/\r\nMEMORY\r\n{\r\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 12288\r\n  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 4096\r\n}\r\n\r\n\/* Linker script to place sections and symbol values. Should be used together\r\n * with other linker script that defines memory regions FLASH and RAM.\r\n * It references following symbols, which must be defined in code:\r\n *   Reset_Handler : Entry of reset handler\r\n * \r\n * It defines following symbols, which code can use without definition:\r\n *   __exidx_start\r\n *   __exidx_end\r\n *   __etext\r\n *   __data_start__\r\n *   __preinit_array_start\r\n *   __preinit_array_end\r\n *   __init_array_start\r\n *   __init_array_end\r\n *   __fini_array_start\r\n *   __fini_array_end\r\n *   __data_end__\r\n *   __bss_start__\r\n *   __bss_end__\r\n *   __end__\r\n *   end\r\n *   __HeapLimit\r\n *   __StackLimit\r\n *   __StackTop\r\n *   __stack\r\n *\/\r\nENTRY(Reset_Handler)\r\n\r\nSECTIONS\r\n{\r\n  .text :\r\n  {\r\n    KEEP(*(.isr_vector))\r\n    KEEP(*(.jumptable))\r\n    *(.text*)\r\n\r\n    KEEP(*(.init))\r\n    KEEP(*(.fini))\r\n\r\n    \/* .ctors *\/\r\n    *crtbegin.o(.ctors)\r\n    *crtbegin?.o(.ctors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r\n    *(SORT(.ctors.*))\r\n    *(.ctors)\r\n\r\n    \/* .dtors *\/\r\n    *crtbegin.o(.dtors)\r\n    *crtbegin?.o(.dtors)\r\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r\n    *(SORT(.dtors.*))\r\n    *(.dtors)\r\n\r\n    *(.rodata*)\r\n\r\n    KEEP(*(.eh_frame*))\r\n  } > FLASH\r\n\r\n  .ARM.extab : \r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > FLASH\r\n\r\n  __exidx_start = .;\r\n  .ARM.exidx :\r\n  {\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n  } > FLASH\r\n  __exidx_end = .;\r\n\r\n  __etext = .;\r\n\r\n  .data : AT (__etext)\r\n  {\r\n    __data_start__ = .;\r\n    *(.shareddata)\r\n    *(vtable)\r\n    *(.data*)\r\n    . = ALIGN (4);\r\n    *(.ram)\r\n\r\n    . = ALIGN(4);\r\n    \/* preinit data *\/\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP(*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* init data *\/\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* finit data *\/\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    KEEP(*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n\r\n    . = ALIGN(4);\r\n    \/* All data end *\/\r\n    __data_end__ = .;\r\n\r\n  } > RAM\r\n\r\n  .bss :\r\n  {\r\n    __bss_start__ = .;\r\n    *(.bss*)\r\n    *(COMMON)\r\n    __bss_end__ = .;\r\n  } > RAM\r\n\r\n  .heap :\r\n  {\r\n    __end__ = .;\r\n    end = __end__;\r\n    _end = __end__;\r\n    *(.heap*)\r\n    __HeapLimit = .;\r\n  } > RAM\r\n\r\n  \/* .stack_dummy section doesn't contains any symbols. It is only\r\n   * used for linker to calculate size of stack sections, and assign\r\n   * values to stack symbols later *\/\r\n  .stack_dummy :\r\n  {\r\n    *(.stack)\r\n  } > RAM\r\n\r\n  \/* Set stack top to end of RAM, and stack limit move down by\r\n   * size of stack_dummy section *\/\r\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r\n  PROVIDE(__stack = __StackTop);\r\n\r\n  \/* Check if data + heap + stack exceeds RAM limit *\/\r\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\r\n\r\n  \/* Check if FLASH usage exceeds FLASH size *\/\r\n  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), \"FLASH memory overflowed !\")\r\n}\r\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"977c326963ccbe2d7ca215ef6dc78c5b12921d4e","subject":"Adjust linker script.","message":"Adjust linker script.\n","repos":"ksejdak\/cosmos,ksejdak\/cosmos,ksejdak\/cosmos","old_file":"board\/beaglebone-black\/beaglebone-black.ld","new_file":"board\/beaglebone-black\/beaglebone-black.ld","new_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nENTRY(_start)\n\nMEMORY {\n\tddr (rwx)      :      ORIGIN = 0x00000000, LENGTH = 512M       \/* External DDR3 RAM *\/\n    sram (rwx)     :      ORIGIN = 0x402f0400, LENGTH = 32K        \/* Internal on-chip SRAM *\/\n}\n\n_bootStart_vma = ORIGIN(sram); \/* Kernel .boot VMA should be the same as LMA, as MMU is not configured. *\/\n_textStart_vma = 0x80000000;   \/* Kernel .text starts at 2 GB. *\/\n_stackSize     = 0x1000;       \/* Stak size is 4KB.*\/\n\nSECTIONS {\n    \/* Starup code. *\/\n    .boot _bootStart_vma : {\n        _bootStart_lma = .;\n\n        *(.boot)\n\n        _bootEnd_lma = .;\n    } AT > sram\n\n    \/* Kernel code. *\/\n    \/* .text _textStart_vma : *\/\n    .text : { \/* TODO: change to above in future. *\/\n        _textStart_lma = .;\n\n        *(.text)                \/* .text sections (code). *\/\n        *(.text*)               \/* .text* sections (code) - this will merge all symbols in .text into one section. *\/\n        *(.glue_7)              \/* Glue arm to thumb code. *\/\n        *(.glue_7t)             \/* Glue thumb to arm code. *\/\n        *(.eh_frame)\n        KEEP (*(.init))\n        KEEP (*(.fini))\n\n        _textEnd_lma = .;\n    } AT > sram \/* TODO: change to ddr in future. *\/\n\n    \/* Constructors and destructors. *\/\n\t.ctors : {\n\t\tKEEP (*crtbegin*.o(.ctors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t} AT > sram \/* TODO: change to ddr in future. *\/\n\n\t.dtors : {\n\t\tKEEP (*crtbegin*.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t} AT > sram \/* TODO: change to ddr in future. *\/\n\n    \/* Data. *\/\n\t.data : {\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t} AT > sram = 0\n\t\n\t\/* Read only data *\/\n\t.rodata : ALIGN(8) {\n        *(.rodata .rodata.* .gnu.linkonce.r.*)\n        *(.rodata1)\n    } AT > sram = 0\n\n\t\/* BSS. *\/\n\t.bss : {\n\t\t_bssStart_lma = .;\n\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\n\t\t. = ALIGN(4);\n\t\t_bssEnd_lma = .;\n\t} AT > sram\n\n\t\/* Stack. *\/\n\t.stack : ALIGN(4) {\n        . += _stackSize;\n\t} AT > sram\n}\n","old_contents":"OUTPUT_FORMAT(\"elf32-littlearm\")\nENTRY(_start)\n\nMEMORY\n{\n\tddr (rwx)      :      ORIGIN = 0x00000000, LENGTH = 512M       \/* External DDR3 RAM *\/\n    sram (rwx)     :      ORIGIN = 0x402f0400, LENGTH = 32K        \/* Internal on-chip SRAM *\/\n}\n\n_bootStart_vma = ORIGIN(sram); \/* Kernel .boot VMA should be the same as LMA, as MMU is not configured. *\/\n_textStart_vma = 0x80000000;   \/* Kernel .text starts at 2 GB. *\/\n_stackSize     = 0x1000;       \/* Stak size is 4KB.*\/\n\nSECTIONS\n{\n    \/* Starup code. *\/\n    .boot _bootStart_vma :\n    {\n        _bootStart_lma = .;\n\n        *(.boot)\n\n        _bootEnd_lma = .;\n    } AT > sram\n\n    \/* Data. *\/\n\t.data :\n\t{\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t\t*(.data1)\n\t} AT > sram\n\t\n\t\/* BSS. *\/\n\t.bss :\n\t{\n\t\t_bssStart_lma = .;\n\n\t\t*(.dynsbss)\n\t\t*(.sbss .sbss.* .gnu.linkonce.sb.*)\n\t\t*(.scommon)\n\t\t*(.dynbss)\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\n\t\t. = ALIGN(2);\n\t\t_bssEnd_lma = .;\n\t} AT > sram\n\n\t\/* Stack. *\/\n\t.stack : ALIGN(4)\n\t{\n        . += _stackSize;\n\t} AT > sram\n\n    \/* Kernel code. *\/\n    .text _textStart_vma :\n    {\n        _textStart_lma = .;\n\n        *(.text)                \/* .text sections (code). *\/\n        *(.text*)               \/* .text* sections (code) - this will merge all symbols in .text into one section. *\/\n        *(.rodata)              \/* .rodata sections (constants, strings, etc.). *\/\n        *(.rodata*)             \/* .rodata* sections (constants, strings, etc.). *\/\n        *(.glue_7)              \/* Glue arm to thumb code. *\/\n        *(.glue_7t)             \/* Glue thumb to arm code. *\/\n        *(.eh_frame)\n        KEEP (*(.init))\n        KEEP (*(.fini))\n\n        _textEnd_lma = .;\n    } AT > ddr\n    \n    \/* Constructors and destructors. *\/\n\t.ctors :\n\t{\n\t\tKEEP (*crtbegin*.o(.ctors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n\t\tKEEP (*(SORT(.ctors.*)))\n\t\tKEEP (*(.ctors))\n\t} AT > ddr\n\n\t.dtors :\n\t{\n\t\tKEEP (*crtbegin*.o(.dtors))\n\t\tKEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n\t\tKEEP (*(SORT(.dtors.*)))\n\t\tKEEP (*(.dtors))\n\t} AT > ddr\n\t\n    \/* Stabs debugging sections. *\/\n\t.stab          0 : { *(.stab) }\n\t.stabstr       0 : { *(.stabstr) }\n\t.stab.excl     0 : { *(.stab.excl) }\n\t.stab.exclstr  0 : { *(.stab.exclstr) }\n\t.stab.index    0 : { *(.stab.index) }\n\t.stab.indexstr 0 : { *(.stab.indexstr) }\n\t.comment       0 : { *(.comment) }\n\n\t\/* DWARF debug sections. Symbols in the DWARF debugging sections are relative to the beginning of the section so we begin them at 0. *\/\n\t\/* DWARF 1 *\/\n\t.debug          0 : { *(.debug) }\n\t.line           0 : { *(.line) }\n\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo  0 : { *(.debug_srcinfo) }\n\t.debug_sfnames  0 : { *(.debug_sfnames) }\n\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges  0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\n\t\/* DWARF 2 *\/\n\t.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n\t.debug_abbrev   0 : { *(.debug_abbrev) }\n\t.debug_line     0 : { *(.debug_line) }\n\t.debug_frame    0 : { *(.debug_frame) }\n\t.debug_str      0 : { *(.debug_str) }\n\t.debug_loc      0 : { *(.debug_loc) }\n\t.debug_macinfo  0 : { *(.debug_macinfo) }\n\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\n\t.debug_typenames 0 : { *(.debug_typenames) }\n\t.debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"7ca246834c99b8460120043a640cf5d8992ac020","subject":"arm64: mmu: Fix SMEM_PARTITION_ALIGN define","message":"arm64: mmu: Fix SMEM_PARTITION_ALIGN define\n\nIn the linker script SMEM_PARTITION_ALIGN is being redefined to be the\nsame as MMU_ALIGN. The problem is that SMEM_PARTITION_ALIGN __must__\ntake a parameter in input because this is being used by the\nscripts\/gen_app_partitions.py script passing a parameter as input.\n\nSigned-off-by: Carlo Caione <ca4506c8c654a4ccf75802e86b5d162c1e96f065@baylibre.com>\n","repos":"nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n\/*\n * MMU currently supports 4 kB translation granule size,\n * so all regions are required to be 4 kB aligned\n *\/\n#define PAGE_SIZE\t0x1000\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_NAME))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n\/*\n * MMU currently supports 4 kB translation granule size,\n * so all regions are required to be 4 kB aligned\n *\/\n#define PAGE_SIZE\t0x1000\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if defined(CONFIG_XIP)\n  #if defined(CONFIG_IS_BOOTLOADER)\n    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n  #else\n    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n  #endif\n#else\n  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_NAME))\n\n        KEEP(*(.openocd_dbg))\n        KEEP(*(\".openocd_dbg.*\"))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"823d86097fd566b28500d1c5a89311583efb73df","subject":"arch: arm: MPU-align GCOV section, only if CONFIG_USERSPACE=y","message":"arch: arm: MPU-align GCOV section, only if CONFIG_USERSPACE=y\n\nThe GCOV section is programmed as a static MPU region, only\nin builds with support for User Mode, otherwise it is not\nprogrammed into an MPU region at all. To reflect this in the\nlinker, the MPU-alignment for GCOV section is enforced only\nunder CONFIG_USERSPACE=y. Otherwise, single-word alignment\nis enforced.\n\nSigned-off-by: Ioannis Glaropoulos <5921cc8bab7e1d4329f52fd8f6268f9692e3de80@nordicsemi.no>\n","repos":"Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,ldts\/zephyr,ldts\/zephyr,finikorg\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,ldts\/zephyr,galak\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,ldts\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,nashif\/zephyr,ldts\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\n#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER\n\tKEEP(*(.boot_hdr.conf))\n\t. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;\n\tKEEP(*(.boot_hdr.ivt))\n\tKEEP(*(.boot_hdr.data))\n#ifdef CONFIG_DEVICE_CONFIGURATION_DATA\n\tKEEP(*(.boot_hdr.dcd_data))\n#endif\n#endif\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#ifdef CONFIG_COVERAGE_GCOV\n    SECTION_DATA_PROLOGUE(_GCOV_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\n#ifdef CONFIG_USERSPACE\n       MPU_ALIGN(__gcov_bss_end - __gcov_bss_start );\n#else  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT && CONFIG_USERSPACE *\/\n       . = ALIGN(_region_min_align);\n#endif \/* CONFIG_USERSPACE *\/\n\n       __gcov_bss_start = .;\n       KEEP(*(\".bss.__gcov0.*\"));\n\n#ifdef CONFIG_USERSPACE\n       MPU_ALIGN(__gcov_bss_end - __gcov_bss_start );\n#else  \/* CONFIG_USERSPACE *\/\n       . = ALIGN(_region_min_align);\n#endif \/* CONFIG_USERSPACE *\/\n\n       __gcov_bss_end = .;\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n       __gcov_bss_num_words = ((__gcov_bss_end - __gcov_bss_start) >> 2);\n       __gcov_bss_size = __gcov_bss_end - __gcov_bss_start;\n\n#endif \/* CONFIG_COVERAGE_GCOV *\/\n\n#if defined(CONFIG_NOCACHE_MEMORY)\n\t\/* Non-cached region of RAM *\/\n\tSECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_start = .;\n\t\t*(.nocache)\n\t\t*(\".nocache.*\")\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\t_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;\n#endif \/* CONFIG_NOCACHE_MEMORY *\/\n\n#if defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT)\n\tSECTION_DATA_PROLOGUE(.ramfunc,,)\n\t{\n\t\tMPU_ALIGN(_ramfunc_ram_size);\n\t\t_ramfunc_ram_start = .;\n\t\t*(.ramfunc)\n\t\t*(\".ramfunc.*\")\n\t\tMPU_ALIGN(_ramfunc_ram_size);\n\t\t_ramfunc_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t_ramfunc_ram_size = _ramfunc_ram_end - _ramfunc_ram_start;\n\t_ramfunc_rom_start = LOADADDR(.ramfunc);\n#endif \/* CONFIG_ARCH_HAS_RAMFUNC_SUPPORT *\/\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef DT_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* DT_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\n#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER\n\tKEEP(*(.boot_hdr.conf))\n\t. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;\n\tKEEP(*(.boot_hdr.ivt))\n\tKEEP(*(.boot_hdr.data))\n#ifdef CONFIG_DEVICE_CONFIGURATION_DATA\n\tKEEP(*(.boot_hdr.dcd_data))\n#endif\n#endif\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#if defined CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n       SECTION_PROLOGUE(.gnu.sgstubs,CONFIG_ARM_NSC_REGION_BASE_ADDRESS,)\n#else\n       SECTION_PROLOGUE(.gnu.sgstubs,,)\n#endif \/* CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0 *\/\n       {\n       . = ALIGN(4);\n       __sg_start = .;\n       *(.gnu*)\n       . = ALIGN(4);\n       __sg_end = .;\n       __sg_size = __sg_end - __sg_start;\n       } GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\t_image_rodata_end = .;\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\t\/* Reserved 4 bytes to save vector table base address *\/\n\tSECTION_PROLOGUE(.vt_pointer,(NOLOAD),)\n\t{\n\t\t*(.vt_pointer_section)\n\t\t*(\".vt_pointer_section.*\")\n\t}\n#endif\n\n#ifdef CONFIG_COVERAGE_GCOV\n    SECTION_DATA_PROLOGUE(_GCOV_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\n#ifdef CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT\n       . = ALIGN( 1 << LOG2CEIL(__gcov_bss_end - __gcov_bss_start ));\n#endif \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n       __gcov_bss_start = .;\n       KEEP(*(\".bss.__gcov0.*\"));\n\n#ifdef CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT\n       . = ALIGN( 1 << LOG2CEIL(__gcov_bss_end - __gcov_bss_start ));\n#else  \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n       . = ALIGN(4);\n#endif \/* CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT *\/\n\n       __gcov_bss_end = .;\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n       __gcov_bss_num_words = ((__gcov_bss_end - __gcov_bss_start) >> 2);\n       __gcov_bss_size = __gcov_bss_end - __gcov_bss_start;\n\n#endif \/* CONFIG_COVERAGE_GCOV *\/\n\n#if defined(CONFIG_NOCACHE_MEMORY)\n\t\/* Non-cached region of RAM *\/\n\tSECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_start = .;\n\t\t*(.nocache)\n\t\t*(\".nocache.*\")\n\t\tMPU_ALIGN(_nocache_ram_size);\n\t\t_nocache_ram_end = .;\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\t_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;\n#endif \/* CONFIG_NOCACHE_MEMORY *\/\n\n#if defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT)\n\tSECTION_DATA_PROLOGUE(.ramfunc,,)\n\t{\n\t\tMPU_ALIGN(_ramfunc_ram_size);\n\t\t_ramfunc_ram_start = .;\n\t\t*(.ramfunc)\n\t\t*(\".ramfunc.*\")\n\t\tMPU_ALIGN(_ramfunc_ram_size);\n\t\t_ramfunc_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t_ramfunc_ram_size = _ramfunc_ram_end - _ramfunc_ram_start;\n\t_ramfunc_rom_start = LOADADDR(.ramfunc);\n#endif \/* CONFIG_ARCH_HAS_RAMFUNC_SUPPORT *\/\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef DT_CCM_BASE_ADDRESS\n\n    GROUP_START(CCM)\n\n\tSECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_start = .;\n\t\t__ccm_bss_start = .;\n\t\t*(.ccm_bss)\n\t\t*(\".ccm_bss.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_bss_end = .;\n\n\tSECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_noinit_start = .;\n\t\t*(.ccm_noinit)\n\t\t*(\".ccm_noinit.*\")\n\t} GROUP_LINK_IN(CCM)\n\n\t__ccm_noinit_end = .;\n\n\tSECTION_PROLOGUE(_CCM_DATA_SECTION_NAME, (OPTIONAL),SUBALIGN(4))\n\t{\n\t\t__ccm_data_start = .;\n\t\t*(.ccm_data)\n\t\t*(\".ccm_data.*\")\n\t} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)\n\n\t__ccm_data_end = .;\n\t__ccm_end = .;\n\n\t__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);\n\n    GROUP_END(CCM)\n\n#endif \/* DT_CCM_BASE_ADDRESS *\/\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4ddcc56354fc02a98a12c1f9aa918c0d4ac888e4","subject":"Add some fake addresses to the test linker script","message":"Add some fake addresses to the test linker script\n","repos":"hoelzro\/rose-kernel,hoelzro\/rose-kernel","old_file":"tests\/verify-idt.ld","new_file":"tests\/verify-idt.ld","new_contents":"isr0 = 0x00000000;\nisr1 = 0x00001111;\nisr2 = 0x00002222;\nisr3 = 0x00003333;\nisr4 = 0x00004444;\nisr5 = 0x00005555;\nisr6 = 0x00006666;\nisr7 = 0x00007777;\nisr8 = 0x00008888;\nisr9 = 0x00009999;\nisr10 = 0x0000AAAA;\nisr11 = 0x0000BBBB;\nisr12 = 0x0000CCCC;\nisr13 = 0x0000DDDD;\nisr14 = 0x0000EEEE;\nisr15 = 0x0000FFFF;\nisr16 = 0x11110000;\nisr17 = 0x11111111;\nisr18 = 0x11112222;\nisr19 = 0x11113333;\nisr20 = 0x11114444;\nisr21 = 0x11115555;\nisr22 = 0x11116666;\nisr23 = 0x11117777;\nisr24 = 0x11118888;\nisr25 = 0x11119999;\nisr26 = 0x1111AAAA;\nisr27 = 0x1111BBBB;\nisr28 = 0x1111CCCC;\nisr29 = 0x1111DDDD;\nisr30 = 0x1111EEEE;\nisr31 = 0x1111FFFF;\n\nstart = 0x200000;\nend   = start + 0x8800;\n\nscreen_write_string_at  = 0x0;\nscreen_write_integer_at = 0x0;\n\nio_inb  = 0x0;\nio_outb = 0x0;\n","old_contents":"isr0 = 0x00000000;\nisr1 = 0x00001111;\nisr2 = 0x00002222;\nisr3 = 0x00003333;\nisr4 = 0x00004444;\nisr5 = 0x00005555;\nisr6 = 0x00006666;\nisr7 = 0x00007777;\nisr8 = 0x00008888;\nisr9 = 0x00009999;\nisr10 = 0x0000AAAA;\nisr11 = 0x0000BBBB;\nisr12 = 0x0000CCCC;\nisr13 = 0x0000DDDD;\nisr14 = 0x0000EEEE;\nisr15 = 0x0000FFFF;\nisr16 = 0x11110000;\nisr17 = 0x11111111;\nisr18 = 0x11112222;\nisr19 = 0x11113333;\nisr20 = 0x11114444;\nisr21 = 0x11115555;\nisr22 = 0x11116666;\nisr23 = 0x11117777;\nisr24 = 0x11118888;\nisr25 = 0x11119999;\nisr26 = 0x1111AAAA;\nisr27 = 0x1111BBBB;\nisr28 = 0x1111CCCC;\nisr29 = 0x1111DDDD;\nisr30 = 0x1111EEEE;\nisr31 = 0x1111FFFF;\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"8d284116b0f3f3d2f0544f38fec101cad4d0cc12","subject":"arch: arc: modify the linker template for APPLICAITON Memory","message":"arch: arc: modify the linker template for APPLICAITON Memory\n\nThe application memory area has a requirement of address alignment,\nespecially when MPU requires power of 2.\n\nModify the linker tmemplate to apply application memory address\nalignment generation\n\nSigned-off-by: Wayne Ren <d5c6d7c4aa45e53f819f17870783d153a32ba7d0@synopsys.com>\n","repos":"nashif\/zephyr,punitvara\/zephyr,nashif\/zephyr,galak\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,mbolivar\/zephyr,finikorg\/zephyr,zephyriot\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,kraj\/zephyr,finikorg\/zephyr,zephyriot\/zephyr,Vudentz\/zephyr,galak\/zephyr,ldts\/zephyr,kraj\/zephyr,mbolivar\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,ldts\/zephyr,ldts\/zephyr,mbolivar\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,zephyriot\/zephyr,galak\/zephyr,ldts\/zephyr,nashif\/zephyr,ldts\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,finikorg\/zephyr,punitvara\/zephyr,nashif\/zephyr,GiulianoFranchetto\/zephyr,Vudentz\/zephyr,explora26\/zephyr,GiulianoFranchetto\/zephyr,punitvara\/zephyr,kraj\/zephyr,finikorg\/zephyr,zephyriot\/zephyr,punitvara\/zephyr,kraj\/zephyr,explora26\/zephyr,mbolivar\/zephyr,zephyrproject-rtos\/zephyr,explora26\/zephyr,explora26\/zephyr,Vudentz\/zephyr,kraj\/zephyr","old_file":"include\/arch\/arc\/v2\/linker.ld","new_file":"include\/arch\/arc\/v2\/linker.ld","new_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#if defined(CONFIG_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define KOBJECT_TEXT_AREA 256\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_HARVARD\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)\n\t\t#define ROMABLE_REGION FLASH\n\t\t#define RAMABLE_REGION SRAM\n\t#else\n\t\t#define ROMABLE_REGION SRAM\n\t\t#define RAMABLE_REGION SRAM\n\t#endif\n#endif\n\n#ifdef CONFIG_ARC_MPU_ENABLE\n\t#if CONFIG_ARC_MPU_VER == 2\n\t\t#define MPU_MIN_SIZE 2048\n\t#elif CONFIG_ARC_MPU_VER == 3\n\t\t#define MPU_MIN_SIZE 32\n\t#endif\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(__start)\n\nMEMORY {\n#ifdef FLASH_START\n\tFLASH (rx)  : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n#endif\n#ifdef ICCM_START\n\tICCM  (rwx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n#endif\n#ifdef SRAM_START\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n#endif\n#ifdef DCCM_START\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n#endif\n\t\/* Used by and documented in include\/linker\/intlist.ld *\/\n\tIDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nSECTIONS {\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\t\tKEEP(*(IRQ_VECTOR_TABLE))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\t\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\tKEEP(*(.openocd_dbg))\n\t\tKEEP(*(\".openocd_dbg.*\"))\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMPU_MIN_SIZE_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n#include <app_data_alignment.ld>\n\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_last_address_used = .;\n\n\t\/* Pad out application ram area to make MPU friendly *\/\n\tSECTION_PROLOGUE(app_pad, (NOLOAD OPTIONAL),)\n\t{\n\t\t. = ALIGN(_app_data_align);\n\t\tMPU_MIN_SIZE_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\n#ifndef CONFIG_APPLICATION_MEMORY\n\t\t_image_ram_start = .;\n#endif\n\t\t__kernel_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.bss)\n\t\tKERNEL_INPUT_SECTION(\".bss.*\")\n\t\tKERNEL_INPUT_SECTION(COMMON)\n\t\t*(\".kernel_bss.*\")\n\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t KERNEL_INPUT_SECTION(.noinit)\n\t\t KERNEL_INPUT_SECTION(\".noinit.*\")\n\t\t *(\".kernel_noinit.*\")\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\t\t__data_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.data)\n\t\tKERNEL_INPUT_SECTION(\".data.*\")\n\t\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n\t__data_ram_end = .;\n\n\tMPU_MIN_SIZE_ALIGN\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\t}\n","old_contents":"\/*\n * Copyright (c) 2014-2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @brief Common parts of the linker scripts for the ARCv2\/EM targets.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#if defined(CONFIG_NSIM)\n\tEXTERN(_VectorTable)\n#endif\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define KOBJECT_TEXT_AREA 256\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_HARVARD\n\t#define ROMABLE_REGION ICCM\n\t#define RAMABLE_REGION DCCM\n#else\n\t#if defined(CONFIG_XIP) && (FLASH_SIZE != 0)\n\t\t#define ROMABLE_REGION FLASH\n\t\t#define RAMABLE_REGION SRAM\n\t#else\n\t\t#define ROMABLE_REGION SRAM\n\t\t#define RAMABLE_REGION SRAM\n\t#endif\n#endif\n\n#ifdef CONFIG_ARC_MPU_ENABLE\n\t#if CONFIG_ARC_MPU_VER == 2\n\t\t#define MPU_ADDR_ALIGN . = ALIGN(2048);\n\t#elif CONFIG_ARC_MPU_VER == 3\n\t\t#define MPU_ADDR_ALIGN . = ALIGN(32);\n\t#endif\n#else\n\t#define MPU_ADDR_ALIGN\n#endif\n\n#if defined(CONFIG_XIP)\n\t#define _DATA_IN_ROM __data_rom_start\n#else\n\t#define _DATA_IN_ROM\n#endif\n\nOUTPUT_ARCH(arc)\nENTRY(__start)\n\nMEMORY {\n#ifdef FLASH_START\n\tFLASH (rx)  : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE*1k\n#endif\n#ifdef ICCM_START\n\tICCM  (rwx)  : ORIGIN = ICCM_START,  LENGTH = ICCM_SIZE*1k\n#endif\n#ifdef SRAM_START\n\tSRAM  (rwx) : ORIGIN = SRAM_START,  LENGTH = SRAM_SIZE*1k\n#endif\n#ifdef DCCM_START\n\tDCCM  (rw)  : ORIGIN = DCCM_START,  LENGTH = DCCM_SIZE*1k\n#endif\n\t\/* Used by and documented in include\/linker\/intlist.ld *\/\n\tIDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nSECTIONS {\n\tGROUP_START(ROMABLE_REGION)\n\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,ALIGN(1024)) {\n\t\t_image_rom_start = .;\n\t\t_image_text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\n\t\tKEEP(*(.exc_vector_table))\n\t\tKEEP(*(\".exc_vector_table.*\"))\n\t\tKEEP(*(IRQ_VECTOR_TABLE))\n\n#ifdef CONFIG_GEN_SW_ISR_TABLE\n\t\tKEEP(*(SW_ISR_TABLE))\n#endif\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\n#include <linker\/kobject-text.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {\n\t\tKEEP(*(.openocd_dbg))\n\t\tKEEP(*(\".openocd_dbg.*\"))\n\t\t*(.rodata)\n\t\t*(\".rodata.*\")\n\t\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/kobject-rom.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMPU_ADDR_ALIGN\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n\n\tGROUP_END(ROMABLE_REGION)\n\n\tGROUP_START(RAMABLE_REGION)\n\n#ifdef CONFIG_APPLICATION_MEMORY\n\tSECTION_DATA_PROLOGUE(_APP_DATA_SECTION_NAME, (OPTIONAL),)\n\t{\n\t\tMPU_ADDR_ALIGN\n\t\t__app_ram_start = .;\n\t\t__app_data_ram_start = .;\n\t\t_image_ram_start = .;\n\t\tAPP_INPUT_SECTION(.data)\n\t\tAPP_INPUT_SECTION(\".data.*\")\n\t\t__app_data_ram_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__app_data_rom_start = LOADADDR(_APP_DATA_SECTION_NAME);\n\n\tSECTION_PROLOGUE(_APP_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\t__app_bss_start = .;\n\t\tAPP_INPUT_SECTION(.bss)\n\t\tAPP_INPUT_SECTION(\".bss.*\")\n\t\tAPP_INPUT_SECTION(COMMON)\n\t\t__app_bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_bss_num_words = (__app_bss_end - __app_bss_start) >> 2;\n\n\tSECTION_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)\n\t{\n\t\tAPP_INPUT_SECTION(.noinit)\n\t\tAPP_INPUT_SECTION(\".noinit.*\")\n\/*\n * for MPU v2,the application memory section must be aligned to the size of\n * section\n *\/\n\t\tMPU_ADDR_ALIGN\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__app_ram_end = .;\n\t__app_ram_size = __app_ram_end - __app_ram_start;\n#endif \/* CONFIG_APPLICATION_MEMORY *\/\n\n\tSECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) {\n\t\tMPU_ADDR_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\n#ifndef CONFIG_APPLICATION_MEMORY\n\t\t_image_ram_start = .;\n#endif\n\t\t__kernel_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.bss)\n\t\tKERNEL_INPUT_SECTION(\".bss.*\")\n\t\tKERNEL_INPUT_SECTION(COMMON)\n\t\t*(\".kernel_bss.*\")\n\n\t\t\/*\n\t\t * BSP clears this memory in words only and doesn't clear any\n\t\t * potential left over bytes.\n\t\t *\/\n\t\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\tSECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) {\n\t\t\/*\n\t\t * This section is used for non-initialized objects that\n\t\t * will not be cleared during the boot process.\n\t\t *\/\n\t\t KERNEL_INPUT_SECTION(.noinit)\n\t\t KERNEL_INPUT_SECTION(\".noinit.*\")\n\t\t *(\".kernel_noinit.*\")\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) {\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\t\t__data_ram_start = .;\n\t\tKERNEL_INPUT_SECTION(.data)\n\t\tKERNEL_INPUT_SECTION(\".data.*\")\n\t\t*(\".kernel.*\")\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n\t__data_ram_end = .;\n\n\tMPU_ADDR_ALIGN\n\n\t\/* Define linker symbols *\/\n\t_image_ram_end = .;\n\t_end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\t}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"49db292cf1cce2e75d067aa571bc79b76d7dff9b","subject":"more accurate linker script","message":"more accurate linker script\n","repos":"aclements\/sv6,aclements\/sv6,bowlofstew\/sv6,bowlofstew\/sv6,aclements\/sv6,bowlofstew\/sv6,aclements\/sv6,bowlofstew\/sv6,aclements\/sv6,bowlofstew\/sv6","old_file":"kernel\/kernel.ld","new_file":"kernel\/kernel.ld","new_contents":"OUTPUT_FORMAT(\"elf64-x86-64\", \"elf64-x86-64\", \"elf64-x86-64\")\nOUTPUT_ARCH(i386:x86-64)\nENTRY(xxx)\n\nSECTIONS\n{\n\t. = 0xFFFFFFFFC0100000;\n\tPROVIDE(text = .);\n\t.text : AT(0x100000) {\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t}\n\t.rodata : {\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t}\n\t. = ALIGN(0x1000);\n\tPROVIDE(sprof = .);\n\t.prof : {\n\t\t*(.prof)\n\t}\n\tPROVIDE(eprof = .);\n\t. = ALIGN(0x1000);\n\t.data : {\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\t}\n\tPROVIDE(edata = .);\n\t.bss : {\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t}\n        \/* 2MByte align, because we set NX on 2MByte super pages. *\/\n\t. = ALIGN(0x200000);\n\tPROVIDE(end = .);\n}\n","old_contents":"OUTPUT_FORMAT(\"elf64-x86-64\", \"elf64-x86-64\", \"elf64-x86-64\")\nOUTPUT_ARCH(i386:x86-64)\nENTRY(xxx)\n\nSECTIONS\n{\n\t. = 0xFFFFFFFFC0100000;\n\tPROVIDE(text = .);\n\t.text : AT(0x100000) {\n\t\t*(.text .stub .text.* .gnu.linkonce.t.*)\n\t}\n\t.rodata : {\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t}\n\t. = ALIGN(0x1000);\n\tPROVIDE(sprof = .);\n\t.prof : {\n\t\t*(.prof)\n\t}\n\tPROVIDE(eprof = .);\n\t. = ALIGN(0x1000);\n\t.data : {\n\t\t*(.data)\n\t}\n\tPROVIDE(edata = .);\n\t.bss : {\n\t\t*(.bss)\n\t}\n        \/* 2MByte align, because we set NX on 2MByte super pages. *\/\n\t. = ALIGN(0x200000);\n\tPROVIDE(end = .);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"6f094e1833050b8a6c0be3b44d46055f1474e6f6","subject":"\tAdjusted vector size.","message":"\tAdjusted vector size.\n","repos":"masilvabustos\/CabbageOS,masilvabustos\/CabbageOS","old_file":"hw\/stm32f100xx.ld","new_file":"hw\/stm32f100xx.ld","new_contents":"\nSECTIONS {\n\t\n\t__end_of_ram__ = ALIGN(ORIGIN(SRAM) + LENGTH(SRAM), 4) ;\n\n\t.cm3.isr_vector ORIGIN(FLASH) : {\n\t\tLONG(__end_of_ram__)\n\t\t\/* ARM Thumb interwork requires the LSB to be set.\t*\n\t\t * (Can ld do this automatically?) \t\t\t*\/ \t\t\t\n\t\tLONG(Reset \t\t| 1)\n\t\tLONG(NMI_Handler \t| 1)\n\t\tLONG(HardFault_Handler \t| 1)\n\t\tLONG(MemManage_Handler \t| 1)\n\t\tLONG(BusFault_Handler \t| 1)\n\t\tLONG(UsageFault_Handler | 1)\n\t\t. = 0x2c ; \/* Reserved *\/\n\t\tLONG(SVC_Handler \t| 1)\n\t\tLONG(DebugMon_Handler\t| 1)\n\t\t. = 0x38 ; \/* Reserved *\/\n\t\tLONG(PendSV_Handler\t| 1)\n\t\tLONG(SysTick_Handler\t| 1)\n\t\t\n\t\t. = 0x40 ;\n\t\t* (.isr_vector)\n\t\t\n\t\t. = 0x134 ;\n\n\t} > FLASH\n\n\n\t.text : { \n\t\t. = ALIGN(4) ;\n\t\t* (.text) \n\t} > FLASH\n\t\n\t__data_lma__ = . ;\n\t.data : AT(__data_lma__) { \n\t\t__data_vma__ = . ;\n\t\t* (.data) \n\t} > SRAM\n\t__init_data_end = . ;\n\n\t.bss : {\n\t\t* (.bss)\n\t} > SRAM\n\n\t__brk = . ;\n\n\t.stm32f100xx.peripherals_registers : {\n\n\t\t\/* TODO: Add remaing registers *\/\n\t\t. = 0x10800 ;\n\t\tGPIOA_CRL \t= . + 0x00 ;\n\t\tGPIOA_CRH \t= . + 0x04 ;\n\t\tGPIOA_IDR \t= . + 0x08 ;\n\t\tGPIOA_ODR \t= . + 0x0C ;\n\t\tGPIOA_BSRR \t= . + 0x10 ;\n\t\tGPIOA_BRR\t= . + 0x14 ;\n\t\tGPIOA_LCKR\t= . + 0x18 ;\n\t\t\n\t\t. = 0x11000 ;\n\t\tGPIOC_CRL \t= . + 0x00 ;\n\t\tGPIOC_CRH \t= . + 0x04 ;\n\t\tGPIOC_IDR \t= . + 0x08 ;\n\t\tGPIOC_ODR \t= . + 0x0C ;\n\t\tGPIOC_BSRR \t= . + 0x10 ;\n\t\tGPIOC_BRR\t= . + 0x14 ;\n\t\tGPIOC_LCKR\t= . + 0x18 ;\n\n\t\t. = 0x21000 ;\n\t\tRCC_CR\t\t= . + 0x00 ;\n\t\tRCC_CFGR\t= . + 0x04 ;\n\t\tRCC_CIR\t\t= . + 0x08 ;\n\t\tRCC_APB2RSTR\t= . + 0x0C ;\n\t\tRCC_APB1RSTR \t= . + 0x10 ;\n\t\tRCC_AHBENR\t= . + 0x14 ;\n\t\tRCC_APB2ENR\t= . + 0x18 ;\n\t\tRCC_APB1ENR\t= . + 0x1C ;\n\t\tRCC_BDCR\t= . + 0x20 ;\n\t\tRCC_CSR\t\t= . + 0x24 ;\n\t\tRCC_CFGR2\t= . + 0x2C ;\n\n\n\t} > PERIPH\n\n\t.stm32f100xx.peripherals_bitband_alias 0x42000000 : {\n\n\t\t. \t\t= (RCC_APB2ENR \t- ORIGIN(PERIPH)) * 32 ;\n\t\tIOPCEN\t\t=  . +  4 * 4 ;\n\n\t} > PERIPH\t\n}\n\n","old_contents":"\nSECTIONS {\n\t\n\t__end_of_ram__ = ALIGN(ORIGIN(SRAM) + LENGTH(SRAM), 4) ;\n\n\t.cm3.isr_vector ORIGIN(FLASH) : {\n\t\tLONG(__end_of_ram__)\n\t\t\/* ARM Thumb interwork requires the LSB to be set.\t*\n\t\t * (Can ld do this automatically?) \t\t\t*\/ \t\t\t\n\t\tLONG(Reset \t\t| 1)\n\t\tLONG(NMI_Handler \t| 1)\n\t\tLONG(HardFault_Handler \t| 1)\n\t\tLONG(MemManage_Handler \t| 1)\n\t\tLONG(BusFault_Handler \t| 1)\n\t\tLONG(UsageFault_Handler | 1)\n\t\t. = 0x2c ; \/* Reserved *\/\n\t\tLONG(SVC_Handler \t| 1)\n\t\tLONG(DebugMon_Handler\t| 1)\n\t\t. = 0x38 ; \/* Reserved *\/\n\t\tLONG(PendSV_Handler\t| 1)\n\t\tLONG(SysTick_Handler\t| 1)\n\n\t\t* (.isr_vector) \/* IRQs *\/\n\t\t\n\t\t. = 0x150 ; \/* Max. vector size? *\/\n\n\t} > FLASH\n\n\n\t.text : { \n\t\t. = ALIGN(4) ;\n\t\t* (.text) \n\t} > FLASH\n\t\n\t__data_lma__ = . ;\n\t.data : AT(__data_lma__) { \n\t\t__data_vma__ = . ;\n\t\t* (.data) \n\t} > SRAM\n\t__init_data_end = . ;\n\n\t.bss : {\n\t\t* (.bss)\n\t} > SRAM\n\n\t__brk = . ;\n\n\t.stm32f100xx.peripherals_registers : {\n\n\t\t\/* TODO: Add remaing registers *\/\n\t\t. = 0x10800 ;\n\t\tGPIOA_CRL \t= . + 0x00 ;\n\t\tGPIOA_CRH \t= . + 0x04 ;\n\t\tGPIOA_IDR \t= . + 0x08 ;\n\t\tGPIOA_ODR \t= . + 0x0C ;\n\t\tGPIOA_BSRR \t= . + 0x10 ;\n\t\tGPIOA_BRR\t= . + 0x14 ;\n\t\tGPIOA_LCKR\t= . + 0x18 ;\n\t\t\n\t\t. = 0x11000 ;\n\t\tGPIOC_CRL \t= . + 0x00 ;\n\t\tGPIOC_CRH \t= . + 0x04 ;\n\t\tGPIOC_IDR \t= . + 0x08 ;\n\t\tGPIOC_ODR \t= . + 0x0C ;\n\t\tGPIOC_BSRR \t= . + 0x10 ;\n\t\tGPIOC_BRR\t= . + 0x14 ;\n\t\tGPIOC_LCKR\t= . + 0x18 ;\n\n\t\t. = 0x21000 ;\n\t\tRCC_CR\t\t= . + 0x00 ;\n\t\tRCC_CFGR\t= . + 0x04 ;\n\t\tRCC_CIR\t\t= . + 0x08 ;\n\t\tRCC_APB2RSTR\t= . + 0x0C ;\n\t\tRCC_APB1RSTR \t= . + 0x10 ;\n\t\tRCC_AHBENR\t= . + 0x14 ;\n\t\tRCC_APB2ENR\t= . + 0x18 ;\n\t\tRCC_APB1ENR\t= . + 0x1C ;\n\t\tRCC_BDCR\t= . + 0x20 ;\n\t\tRCC_CSR\t\t= . + 0x24 ;\n\t\tRCC_CFGR2\t= . + 0x2C ;\n\n\n\t} > PERIPH\n\n\t.stm32f100xx.peripherals_bitband_alias 0x42000000 : {\n\n\t\t. \t\t= (RCC_APB2ENR \t- ORIGIN(PERIPH)) * 32 ;\n\t\tIOPCEN\t\t=  . +  4 * 4 ;\n\n\t} > PERIPH\t\n}\n\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"e435f55801514f6216910bd730bb7d8a4ab8e823","subject":"\u30b9\u30bf\u30c3\u30af\u521d\u671f\u5024\u5909\u66f4","message":"\u30b9\u30bf\u30c3\u30af\u521d\u671f\u5024\u5909\u66f4\n","repos":"hirakuni45\/R8C,hirakuni45\/R8C,hirakuni45\/R8C","old_file":"M120AN\/m120an.ld","new_file":"M120AN\/m120an.ld","new_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x0300, LENGTH = 0x0480\n\tROM (r)  : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVVEC (r) : ORIGIN = 0xFED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0760;\n\t\t_isp_init = 0x0780;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*==============================================================\/\n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/\n\/   R8C(Tiny)\/M110AN, R8C(Tiny)\/M120AN Link Loader Script       \/\n\/\tFlash-ROM and RAM extends version                           \/\n\/   Flash-ROM: 2048(0xF800) ---> 32768(start: 0x8000) bytes     \/\n\/   RAM:        256(0x0400) --->  1280(start: 0x0300) bytes     \/ \n\/\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\/ \n\/==============================================================*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-m32c\", \"elf32-m32c\",\n\t      \"elf32-m32c\")\nOUTPUT_ARCH(m32c)\nENTRY(_start)\nINPUT(-lm32cgloss)\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\nMEMORY {\n\tRAM (w)  : ORIGIN = 0x0300, LENGTH = 0x0480\n\tROM (r)  : ORIGIN = 0x8000, LENGTH = 0x7FD8\n\tVVEC (r) : ORIGIN = 0xFED8, LENGTH = 256\n\tFVEC (r) : ORIGIN = 0xFFD8, LENGTH = 40\n}\nSECTIONS\n{\n\t\t_usp_init = 0x0760-1;\n\t\t_isp_init = 0x0780-1;\n\n  \/* There are three cases we care about: First, RW data that must be\n     in the low 64k.  This will always be copied from ROM.  Second, RO\n     data that must be in the low 64k.  This may be copied from ROM if\n     the ROM is above 64k.  Third, anything that does not need to be\n     in the first 64k.  Chips normally only have two memory regions;\n     low ram and either high or low rom.  We map the low rom needs\n     into one of the actual regions.  *\/\n\n  \/* .text goes first so the rom image of ram data will follow it.  *\/\n  .text           :\n  {\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(2);\n  } > ROM =0\n\n  \/* rodata will either be part of data, or will be in low rom.  So we\n     might be spanning it, or we might not.  This lets us include it\n     in our calculations when appropriate.  *\/\n\n  .rodata : {\n    . = ALIGN(2);\n    *(.plt)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(2);\n    PROVIDE(__romdatastart = .); \/* IF_ROROM *\/\n  } > ROM\n\n  PROVIDE( __datainternal = ABSOLUTE(LOADADDR(.data)));\n\n  .data : {\n    . = ALIGN(32 \/ 8);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    PROVIDE (__fini_array_end = .);\n\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n    PROVIDE (__var_vect_start = .);\n    *(.var_vects)\n\n    . = ALIGN(2);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT>ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is even; all the start\/stop symbols\n     are also assumed word-aligned.  *\/\n  PROVIDE (__romdatacopysize =SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(2);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(2);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss));\n\n  .vvec : {\n    *(.vvec)\n  } > VVEC\n\n  .fvec : {\n    *(.fvec)\n  } > FVEC\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"080da7b24abe600f4c5624f67b8ce833d03c0cd8","subject":"bsp\/nucleo-f411re: Fix linker script","message":"bsp\/nucleo-f411re: Fix linker script\n\nFlash area size for bootloader was different in bsp.yml and\nin bootloader linker script.\nWhen FLASH_AREA_REBOOT_LOG flash area was used bootloader area was\ncorrupted.\n","repos":"mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core","old_file":"hw\/bsp\/nucleo-f411re\/boot-nucleo-f411re.ld","new_file":"hw\/bsp\/nucleo-f411re\/boot-nucleo-f411re.ld","new_contents":"\/*\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n *\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 16K\n  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 128K\n}\n\n\/* The bootloader does not contain an image header *\/\n_imghdr_size = 0x0;\n","old_contents":"\/*\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n *\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K\n  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 128K\n}\n\n\/* The bootloader does not contain an image header *\/\n_imghdr_size = 0x0;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"16a377affd51f3fff274480df543bdcbf4721f0b","subject":"Update linker script","message":"Update linker script\n","repos":"kwagyeman\/openmv,iabdalkader\/openmv,SmartArduino\/openmv,openmv\/openmv,tianzhihen\/openmv,iabdalkader\/openmv,tianzhihen\/openmv,iabdalkader\/openmv,SmartArduino\/openmv,tianzhihen\/openmv,iabdalkader\/openmv,openmv\/openmv,kwagyeman\/openmv,kwagyeman\/openmv,kwagyeman\/openmv,SmartArduino\/openmv,openmv\/openmv,openmv\/openmv,SmartArduino\/openmv,tianzhihen\/openmv","old_file":"src\/stm32f4xx.ld","new_file":"src\/stm32f4xx.ld","new_contents":"\/**\n *  Linker script for STM32F4xx Devices with 1MB FLASH, 192KB RAM (64KB CCM)\n *\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K\n  FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 512K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n  CCM (w!rx)      : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Highest address of the user mode stack *\/\n_estack     = 0x10010000; \/* Stack is allocated on CCM block *\/\n\n_ram_end   = 0x10010000; \/* 64KB CCM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_stack_size = 0x1300; \/* required amount of stack *\/\n_heap_size  = 0x8000; \/* 0xC800 required amount of heap *\/\n_cache_size = 0x4000; \/* 0x4000 required amount of cache *\/\n\n_main_ram_start = 0x20000000;\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH_ISR\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n    _exit = .;\n  } >FLASH_TEXT\n\n   \/* used by the startup to initialize data *\/\n   _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    _ram_start = .;\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >CCM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n    _bss_end = _ebss; \/* for gccollect *\/\n  } >CCM\n\n  ._heap :\n  {\n    . = ALIGN(4);\n    _heap_start = .;\n    . = . + _heap_size;\n    . = ALIGN(4);\n    _heap_end  = .;\n  } >CCM\n\n  \/* Make sure there is enough RAM left for the stack *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _cache_size;\n    . = . + _stack_size;\n    . = ALIGN(4);\n  } >CCM\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/**\n *  Linker script for STM32F4xx Devices with 1MB FLASH, 192KB RAM (64KB CCM)\n *\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K\n  FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 896K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K\n  CCM (w!rx)      : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n\/* Highest address of the user mode stack *\/\n_estack     = 0x10010000; \/* Stack is allocated on CCM block *\/\n\n_ram_end   = 0x10010000; \/* 64KB CCM *\/\n\n\/* Generate a link error if heap and stack don't fit into RAM *\/\n_stack_size = 0x1000; \/* required amount of stack *\/\n_heap_size  = 0x8000; \/* 0xC800 required amount of heap *\/\n_cache_size = 0x4000; \/* required amount of cache *\/\n\n_main_ram_start = 0x20000000;\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into FLASH *\/\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) \/* Startup code *\/\n    . = ALIGN(4);\n  } >FLASH_ISR\n\n  \/* The program code and other data goes into FLASH *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           \/* .text sections (code) *\/\n    *(.text*)          \/* .text* sections (code) *\/\n    *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)         \/* glue arm to thumb code *\/\n    *(.glue_7t)        \/* glue thumb to arm code *\/\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        \/* define a global symbols at end of code *\/\n    _exit = .;\n  } >FLASH_TEXT\n\n  \/* used by the startup to initialize data *\/\n  _sidata = .;\n\n  \/* Initialized data sections goes into RAM, load LMA copy after code *\/\n  .data : AT ( _sidata )\n  {\n    . = ALIGN(4);\n    _sdata = .;        \/* create a global symbol at data start *\/\n    _ram_start = .;\n    *(.data)           \/* .data sections *\/\n    *(.data*)          \/* .data* sections *\/\n\n    . = ALIGN(4);\n    _edata = .;        \/* define a global symbol at data end *\/\n  } >CCM\n\n  \/* Uninitialized data section *\/\n  . = ALIGN(4);\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss secion *\/\n    _sbss = .;         \/* define a global symbol at bss start *\/\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         \/* define a global symbol at bss end *\/\n    __bss_end__ = _ebss;\n    _bss_end = _ebss; \/* for gccollect *\/\n  } >CCM\n\n  ._heap :\n  {\n    . = ALIGN(4);\n    _heap_start = .;\n    . = . + _heap_size;\n    . = ALIGN(4);\n    _heap_end  = .;\n  } >CCM\n\n  \/* Make sure there is enough RAM left for the stack *\/\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    . = . + _cache_size;\n    . = . + _stack_size;\n    . = ALIGN(4);\n  } >CCM\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"025ae4526cd430e1377cbb203dbad26fd4b16068","subject":"update ld script","message":"update ld script\n","repos":"stateos\/IntrOS-LM4F120XL,stateos\/IntrOS-LM4F120XL","old_file":"startup\/LM4F\/GCC\/script_gcc.ld","new_file":"startup\/LM4F\/GCC\/script_gcc.ld","new_contents":"\/*******************************************************************************\n@file     lm4f120h5qr.ld\n@author   Rajmund Szymanski\n@date     08.03.2016\n@brief    Linker script for LM4F120H5QR device with 256KB FLASH and 32KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x00000000, LENGTH = 256K\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  32K\n}\n\nREGION_ALIAS(\"TEXT\", ROM);\n\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(TEXT);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > TEXT\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > TEXT\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > TEXT\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > TEXT\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > TEXT\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__stack_start = .;\n\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\n\t\t__stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = __main_stack_end - __main_stack_start;\n\t__proc_stack_size = __proc_stack_end - __proc_stack_start;\n\n\t__stack_size = SIZEOF(.stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > TEXT\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t__heap_end = ABSOLUTE(__ram_end);\n\t} > RAM\n\n\tPROVIDE(__initial_msp = __main_stack_size ? __main_stack_end : __ram_end);\n\tPROVIDE(__initial_psp = __proc_stack_end);\n\tPROVIDE(__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp);\n\n\tPROVIDE(__bss_start__ = __bss_start);\n\tPROVIDE(__bss_end__   = __bss_end);\n\tPROVIDE(__heap_base__ = __heap_start);\n\tPROVIDE(__heap_end__  = __heap_end);\n\tPROVIDE(__heap_base   = __heap_start);\n\tPROVIDE(__heap_limit  = __heap_end);\n\tPROVIDE(__stack       = __initial_sp);\n\tPROVIDE(__end__       = __bss_end);\n\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","old_contents":"\/*******************************************************************************\n@file     lm4f120h5qr.ld\n@author   Rajmund Szymanski\n@date     22.02.2016\n@brief    Linker script for LM4F120H5QR device with 256KB FLASH and 32KB RAM\n*******************************************************************************\/\n\nMEMORY\n{\n\tROM (rx)  : ORIGIN = 0x00000000, LENGTH = 256K\n\tRAM (rwx) : ORIGIN = 0x20000000, LENGTH =  32K\n}\n\nREGION_ALIAS(\"TEXT\", ROM);\n\n__ram_start = ORIGIN(RAM);\n__ram_end   = ORIGIN(RAM) + LENGTH(RAM);\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t__text_start = ORIGIN(TEXT);\n\n\t.text :\n\t{\n\t\tKEEP (*(.vectors))\n\n\t\t*(.text   .text.*   .gnu.linkonce.t.*)\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*)\n\t\t*(.glue_7 .glue_7t)\n\t} > TEXT\n\n\t.init : ALIGN(4)\n\t{\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\tKEEP (*(.init))\n\t} > TEXT\n\n\t.fini : ALIGN(4)\n\t{\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\tKEEP (*(.fini))\n\t} > TEXT\n\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t\t*(.gcc_except_table)\n\t\t*(.eh_frame_hdr)\n\t\t*(.eh_frame)\n\t} > TEXT\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > TEXT\n\n\t__text_end  = .;\n\t__text_size = . - __text_start;\n\n\t.stack (NOLOAD): ALIGN(8)\n\t{\n\t\t__stack_start = .;\n\n\t\t__main_stack_start = .;\n\t\tKEEP (*(.main_stack))\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\n\t\t__proc_stack_start = .;\n\t\tKEEP (*(.proc_stack))\n\t\t. = ALIGN(8);\n\t\t__proc_stack_end = .;\n\n\t\t__stack_end = .;\n\t} > RAM\n\n\t__main_stack_size = __main_stack_end - __main_stack_start;\n\t__proc_stack_size = __proc_stack_end - __proc_stack_start;\n\n\t__stack_size = SIZEOF(.stack);\n\n\t.data : ALIGN(4)\n\t{\n\t\t__data_init_start = LOADADDR(.data);\n\n\t\t__data_start = .;\n\t\t*(.data* .gnu.linkonce.d.*)\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t} > RAM AT > TEXT\n\n\t__data_size = SIZEOF(.data);\n\n\t.bss (NOLOAD): ALIGN(4)\n\t{\n\t\t__bss_start = .;\n\t\t*(.bss* .gnu.linkonce.b.*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t} > RAM\n\n\t__bss_size = SIZEOF(.bss);\n\n\t.heap (NOLOAD): ALIGN(8)\n\t{\n\t\t__heap_start = .;\n\t\t__heap_end = ABSOLUTE(__ram_end);\n\t} > RAM\n\n\tPROVIDE(__initial_msp = __main_stack_size ? __main_stack_end : __ram_end);\n\tPROVIDE(__initial_psp = __proc_stack_end);\n\tPROVIDE(__initial_sp  = __proc_stack_size ? __proc_stack_end : __initial_msp);\n\n\tPROVIDE(__bss_start__ = __bss_start);\n\tPROVIDE(__bss_end__   = __bss_end);\n\tPROVIDE(__heap_base__ = __heap_start);\n\tPROVIDE(__heap_end__  = __heap_end);\n\tPROVIDE(__heap_base   = __heap_start);\n\tPROVIDE(__heap_limit  = __heap_end);\n\tPROVIDE(__stack       = __initial_sp);\n\n\tPROVIDE(__process_stack_start = __proc_stack_start);\n\tPROVIDE(__process_stack_size  = __proc_stack_size);\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"d9db2584115055cf1b6f0797dcdb8c22c58838b5","subject":"cortexm_common\/ldscript: re-use _rom_offset variable name","message":"cortexm_common\/ldscript: re-use _rom_offset variable name\n\nInspired by kaspar030 version to removing the new _boot_offset variable.\n\nhttps:\/\/github.com\/kaspar030\/RIOT\/blob\/cbf324a66d0c925dd02eca290e17c350945e97b2\/cpu\/cortexm_common\/ldscripts\/cortexm.ld\n","repos":"ant9000\/RIOT,miri64\/RIOT,aeneby\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,toonst\/RIOT,kYc0o\/RIOT,kYc0o\/RIOT,biboc\/RIOT,josephnoir\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,ant9000\/RIOT,x3ro\/RIOT,RIOT-OS\/RIOT,rfuentess\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,A-Paul\/RIOT,mtausig\/RIOT,basilfx\/RIOT,mfrey\/RIOT,smlng\/RIOT,smlng\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,toonst\/RIOT,A-Paul\/RIOT,RIOT-OS\/RIOT,toonst\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,miri64\/RIOT,OTAkeys\/RIOT,mtausig\/RIOT,miri64\/RIOT,lazytech-org\/RIOT,mtausig\/RIOT,mfrey\/RIOT,lazytech-org\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,jasonatran\/RIOT,smlng\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,cladmi\/RIOT,yogo1212\/RIOT,rfuentess\/RIOT,basilfx\/RIOT,A-Paul\/RIOT,lazytech-org\/RIOT,mtausig\/RIOT,biboc\/RIOT,x3ro\/RIOT,ant9000\/RIOT,authmillenon\/RIOT,mfrey\/RIOT,authmillenon\/RIOT,lazytech-org\/RIOT,basilfx\/RIOT,yogo1212\/RIOT,miri64\/RIOT,avmelnikoff\/RIOT,biboc\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,avmelnikoff\/RIOT,cladmi\/RIOT,yogo1212\/RIOT,kYc0o\/RIOT,basilfx\/RIOT,avmelnikoff\/RIOT,kbumsik\/RIOT,josephnoir\/RIOT,OlegHahm\/RIOT,aeneby\/RIOT,gebart\/RIOT,A-Paul\/RIOT,x3ro\/RIOT,avmelnikoff\/RIOT,jasonatran\/RIOT,gebart\/RIOT,kaspar030\/RIOT,avmelnikoff\/RIOT,josephnoir\/RIOT,gebart\/RIOT,jasonatran\/RIOT,josephnoir\/RIOT,BytesGalore\/RIOT,OTAkeys\/RIOT,gebart\/RIOT,kaspar030\/RIOT,x3ro\/RIOT,kbumsik\/RIOT,rfuentess\/RIOT,cladmi\/RIOT,biboc\/RIOT,mfrey\/RIOT,toonst\/RIOT,toonst\/RIOT,A-Paul\/RIOT,kYc0o\/RIOT,cladmi\/RIOT,yogo1212\/RIOT,mfrey\/RIOT,BytesGalore\/RIOT,kbumsik\/RIOT,jasonatran\/RIOT,BytesGalore\/RIOT,cladmi\/RIOT,kaspar030\/RIOT,x3ro\/RIOT,rfuentess\/RIOT,lazytech-org\/RIOT,aeneby\/RIOT,gebart\/RIOT,kbumsik\/RIOT,OTAkeys\/RIOT,BytesGalore\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,miri64\/RIOT,kbumsik\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,smlng\/RIOT,yogo1212\/RIOT,biboc\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,BytesGalore\/RIOT,josephnoir\/RIOT,mtausig\/RIOT,yogo1212\/RIOT,smlng\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm.ld","new_contents":"\/*\n * Copyright (C) 2017 Inria\n *               2018 Freie Universit\u00e4t Berlin\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_cortexm_common\n * @{\n *\n * @file\n * @brief           Memory definitions for the Cortex-M family\n *\n * @author          Francisco Acosta <francisco.acosta@inria.fr>\n *                  Ga\u00ebtan Harter <gaetan.harter@inria.fr>\n *\n * @}\n *\/\n\n_rom_offset = DEFINED( _rom_offset ) ? _rom_offset : 0x0;\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _rom_length - _rom_offset\n    ram (w!rx)  : ORIGIN = _ram_start_addr,               LENGTH = _ram_length\n}\n\nINCLUDE cortexm_base.ld\n","old_contents":"\/*\n * Copyright (C) 2017 Inria\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_cortexm_common\n * @{\n *\n * @file\n * @brief           Memory definitions for the Cortex-M family\n *\n * @author          Francisco Acosta <francisco.acosta@inria.fr>\n *\n * @}\n *\/\n\n_boot_offset = DEFINED( _rom_offset ) ? _rom_offset : 0x0 ;\n\nMEMORY\n{\n    rom (rx)    : ORIGIN = _rom_start_addr + _boot_offset, LENGTH = _rom_length - _boot_offset\n    ram (w!rx)  : ORIGIN = _ram_start_addr,                LENGTH = _ram_length\n}\n\nINCLUDE cortexm_base.ld\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"cba2dae148a82413e14cf681b507aee7cb60d7b2","subject":"Change SRAM mapping and increase SRAM allocated to ARC core -increase SRAM to 40K -change SRAM start address -increase heap size to 16K -this change is needed for BLE scan for SensorTag","message":"Change SRAM mapping and increase SRAM allocated to ARC core\n-increase SRAM to 40K\n-change SRAM start address\n-increase heap size to 16K\n-this change is needed for BLE scan for SensorTag\n","repos":"yashaswini-hanji\/corelibs-arduino101,yashaswini-hanji\/corelibs-arduino101,yashaswini-hanji\/corelibs-arduino101","old_file":"variants\/arduino_101\/linker_scripts\/flash.ld","new_file":"variants\/arduino_101\/linker_scripts\/flash.ld","new_contents":"\/* linker.cmd - Linker command\/script file *\/\n\n\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1) Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2) Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and\/or other materials provided with the distribution.\n *\n * 3) Neither the name of Wind River Systems nor the names of its contributors\n * may be used to endorse or promote products derived from this software without\n * specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\/\n\n\/*\nDESCRIPTION\nLinker script for the Arduino 101 ARC BSPs.\n*\/\n\nOUTPUT_FORMAT(\"elf32-littlearc\", \"elf32-bigarc\", \"elf32-littlearc\")\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = 0x40034000, LENGTH = 152K\n    SRAM                  (wx) : ORIGIN = 0xa800a000, LENGTH = 40K\n    DCCM                  (wx) : ORIGIN = 0x80000000, LENGTH = 8K\n    }\n\n\/* Define default stack size and FIRQ stack size.\n * See below stack section for __stack_start and __firq_stack_start\n *\/\n__stack_size = 2048;\n__firq_stack_size = 1024;\n\n\/* Minimum heap size to allocate\n * Actual heap size might be bigger due to page size alignment *\/\n__HEAP_SIZE_MIN = 16384;\n\/* This should be set to the page size used by the malloc implementation *\/\n__PAGE_SIZE = 4096;\n\nSECTIONS\n    {\n\/* FLASH Start *\/\n\n    text : ALIGN(1024)\n\t{\n\t__text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\tKEEP(*(.int_vector_table))\n\tKEEP(*(\".int_vector_table.*\"))\n\n\t*(.version_header)\n\tKEEP(*(\".version_header*\"))\n\n\t*(.text)\n\t*(\".text.*\")\n\t__text_end = .;\n\t} > FLASH\n\n    ctors :\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __ctor_table_start must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first element of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } > FLASH\n\n    rodata :\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t} > FLASH\n\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n\/* FLASH End *\/\n\n\/* SRAM Start *\/\n\n    datas : AT(__data_rom_start)\n\t{\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t. = ALIGN(4);\n\t} > SRAM\n\n    __data_ram_end = .;\n\n    bss (NOLOAD) :\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n        \/*\n         * BSP clears this memory in words only and doesn't clear any\n         * potential left over bytes.\n\t *\/\n\t__bss_end = ALIGN(4);\n\t} > SRAM\n\n    noinit (NOLOAD) :\n        {\n        \/*\n         * This section is used for non-intialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t\/*\n\t * The seg_rxtx section is used by the Host IO module for\n\t * allocating RX\/TX buffers. If a specific memory location is\n\t * required for these buffers, then a MEMORY definition should be\n\t * made.\n\t *\/\n\t*(.seg_rxtx)\n\t*(\".seg_rxtx.*\")\n        } > SRAM\n\n    heap (NOLOAD) :\n    {\n        . = ALIGN(4);\n        __start_heap = .;\n        . = . + __HEAP_SIZE_MIN;\n        __end_heap = ALIGN(__PAGE_SIZE);\n    } > SRAM\n\n    stack :\n    {\n        . += __firq_stack_size;\n        . = ALIGN(4);\n        __firq_stack_start = .;\n\n        . += __stack_size;\n        . = ALIGN(4);\n        __stack_start = .;\n    } > SRAM\n\n    \/* Define linker symbols *\/\n\n    _end = .; \/* end of image *\/\n\n\/* SRAM End *\/\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\/* DCCM Start *\/\n\/* DCCM End *\/\n\n    }\n","old_contents":"\/* linker.cmd - Linker command\/script file *\/\n\n\/*\n * Copyright (c) 2014 Wind River Systems, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1) Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2) Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and\/or other materials provided with the distribution.\n *\n * 3) Neither the name of Wind River Systems nor the names of its contributors\n * may be used to endorse or promote products derived from this software without\n * specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\/\n\n\/*\nDESCRIPTION\nLinker script for the Arduino 101 ARC BSPs.\n*\/\n\nOUTPUT_FORMAT(\"elf32-littlearc\", \"elf32-bigarc\", \"elf32-littlearc\")\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = 0x40034000, LENGTH = 152K\n    SRAM                  (wx) : ORIGIN = 0xa800e000, LENGTH = 24K\n    DCCM                  (wx) : ORIGIN = 0x80000000, LENGTH = 8K\n    }\n\n\/* Define default stack size and FIRQ stack size.\n * See below stack section for __stack_start and __firq_stack_start\n *\/\n__stack_size = 2048;\n__firq_stack_size = 1024;\n\n\/* Minimum heap size to allocate\n * Actual heap size might be bigger due to page size alignment *\/\n__HEAP_SIZE_MIN = 8192;\n\/* This should be set to the page size used by the malloc implementation *\/\n__PAGE_SIZE = 4096;\n\nSECTIONS\n    {\n\/* FLASH Start *\/\n\n    text : ALIGN(1024)\n\t{\n\t__text_start = .;\n\n\/* when !XIP, .text is in RAM, and vector table must be at its very start *\/\n\tKEEP(*(.int_vector_table))\n\tKEEP(*(\".int_vector_table.*\"))\n\n\t*(.version_header)\n\tKEEP(*(\".version_header*\"))\n\n\t*(.text)\n\t*(\".text.*\")\n\t__text_end = .;\n\t} > FLASH\n\n    ctors :\n        {\n        \/*\n         * The compiler fills the constructor pointers table below, hence symbol\n         * __ctor_table_start must be aligned on 4 byte boundary.\n         * To align with the C++ standard, the first element of the array\n         * contains the number of actual constructors. The last element is\n         * NULL.\n         *\/\n        . = ALIGN(4);\n        __CTOR_LIST__ = .;\n        LONG((__CTOR_END__ - __CTOR_LIST__) \/ 4 - 2)\n        KEEP(*(SORT(\".ctors*\")))\n        LONG(0)\n        __CTOR_END__ = .;\n        } > FLASH\n\n    rodata :\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t} > FLASH\n\n    __data_rom_start = ALIGN(4);    \/* XIP imaged DATA ROM start addr *\/\n\n\/* FLASH End *\/\n\n\/* SRAM Start *\/\n\n    datas : AT(__data_rom_start)\n\t{\n\n\/* when XIP, .text is in ROM, but vector table must be at start of .data *\/\n\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t. = ALIGN(4);\n\t} > SRAM\n\n    __data_ram_end = .;\n\n    bss (NOLOAD) :\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n        \/*\n         * BSP clears this memory in words only and doesn't clear any\n         * potential left over bytes.\n\t *\/\n\t__bss_end = ALIGN(4);\n\t} > SRAM\n\n    noinit (NOLOAD) :\n        {\n        \/*\n         * This section is used for non-intialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t\/*\n\t * The seg_rxtx section is used by the Host IO module for\n\t * allocating RX\/TX buffers. If a specific memory location is\n\t * required for these buffers, then a MEMORY definition should be\n\t * made.\n\t *\/\n\t*(.seg_rxtx)\n\t*(\".seg_rxtx.*\")\n        } > SRAM\n\n    heap (NOLOAD) :\n    {\n        . = ALIGN(4);\n        __start_heap = .;\n        . = . + __HEAP_SIZE_MIN;\n        __end_heap = ALIGN(__PAGE_SIZE);\n    } > SRAM\n\n    stack :\n    {\n        . += __firq_stack_size;\n        . = ALIGN(4);\n        __firq_stack_start = .;\n\n        . += __stack_size;\n        . = ALIGN(4);\n        __stack_start = .;\n    } > SRAM\n\n    \/* Define linker symbols *\/\n\n    _end = .; \/* end of image *\/\n\n\/* SRAM End *\/\n\n\t\/* Data Closely Coupled Memory (DCCM) *\/\n\/* DCCM Start *\/\n\/* DCCM End *\/\n\n    }\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"c60cd716445dcf7f0557c2745514e1ad7b5eeeca","subject":"Pin the reflection data sections on Linux","message":"Pin the reflection data sections on Linux\n\nThese had similar problems to the protocol conformance sections during\nLinux bringup. There are relative offsets from the main reflection\nsection to the two string sections, so their position relative to each\nother must remain fixed.\n","repos":"khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift,khizkhiz\/swift","old_file":"stdlib\/public\/runtime\/swift.ld","new_file":"stdlib\/public\/runtime\/swift.ld","new_contents":"SECTIONS\n{\n  .swift3_typeref : { *(.swift3_typeref) },\n  .swift3_reflstr : { *(.swift3_reflstr) },\n  .swift3_reflect : { *(.swift3_reflect) },\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","old_contents":"SECTIONS\n{\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"02c7a3aa4c5f87a29ed1b5023024b7c090d2b9b9","subject":"update copyright","message":"update copyright\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX71M\/R5F571MF.ld","new_file":"RX71M\/R5F571MF.ld","new_contents":"\/*!\t@file\n\t@brief\tRX71M R5F571MF \u30ea\u30f3\u30ab\u30fc\u30fb\u30b9\u30af\u30ea\u30d7\u30c8\n    @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\t@copyright\tCopyright (C) 2017 Kunihito Hiramatsu @n\n\t\t\t\tReleased under the MIT license @n\n\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)   : ORIGIN = 0x00000000, LENGTH = 0x00080000 \/* 512K bytes (+32K) *\/\n\tSTACK (w) : ORIGIN = 0x00080000, LENGTH = 16 \/* top of RAM *\/\n\n\tROM (w)   : ORIGIN = 0xFFE00000, LENGTH = 0x001FFFD0 \/* 2M bytes *\/\n\/* This is the largest RX6000: *\/\n\/*\tROM (w)   : ORIGIN = 0xFFE00000, LENGTH = 0x001FFFD0 *\/ \/* 2Mb *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)   : ORIGIN = 0x00000000, LENGTH = 0x00080000 \/* 512K bytes (+32K) *\/\n\tSTACK (w) : ORIGIN = 0x00080000, LENGTH = 16 \/* top of RAM *\/\n\n\tROM (w)   : ORIGIN = 0xFFE00000, LENGTH = 0x001FFFD0 \/* 2M bytes *\/\n\/* This is the largest RX6000: *\/\n\/*\tROM (w)   : ORIGIN = 0xFFE00000, LENGTH = 0x001FFFD0 *\/ \/* 2Mb *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .stack (ORIGIN (STACK)) :\n  {\n    PROVIDE (__stack = .);\n    *(.stack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"2849c044fbfa154090f069da8b3a9e47ef26af7e","subject":"PMU741: Cleanup pmu741.ld","message":"PMU741: Cleanup pmu741.ld\n","repos":"Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano,Canaan-Creative\/Avalon-nano","old_file":"firmware\/pmu741\/pmu741.ld","new_file":"firmware\/pmu741\/pmu741.ld","new_contents":"MEMORY\n{\n\t\/* Define each memory region *\/\n\tMFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 \/* 32K bytes *\/\n\tRamLoc4 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x1000 \/* 4K bytes *\/\n}\n\n\/* Define a symbol for the top of each memory region *\/\n__top_MFlash32 = 0x0 + 0x8000;\n__top_RamLoc4 = 0x10000000 + 0x1000;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\t\/* MAIN TEXT SECTION *\/\n\t.text : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t__vectors_start__ = ABSOLUTE(.);\n\t\tKEEP(*(.isr_vector))\n\n\t\t\/* Global Section Table *\/\n\t\t. = ALIGN(4);\n\t\t__section_table_start = .;\n\t\t__data_section_table = .;\n\t\tLONG(LOADADDR(.data));\n\t\tLONG(ADDR(.data));\n\t\tLONG(SIZEOF(.data));\n\t\t__data_section_table_end = .;\n\t\t__bss_section_table = .;\n\t\tLONG(ADDR(.bss));\n\t\tLONG(SIZEOF(.bss));\n\t\t__bss_section_table_end = .;\n\t\t__section_table_end = . ;\n\t\t\/* End of Global Section Table *\/\n\n\t\t*(.after_vectors*)\n\n\t\t\/* Code Read Protect data *\/\n\t\t. = 0x000002FC;\n\t\tPROVIDE(__CRP_WORD_START__ = .);\n\t\tKEEP(*(.crp))\n\t\tPROVIDE(__CRP_WORD_END__ = .);\n\t\tASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), \"Linker CRP Enabled, but no CRP_WORD provided within application\");\n\t\t\/* End of Code Read Protect *\/\n\t} >MFlash32\n\n\t.text : ALIGN(4)\n\t{\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .constdata .constdata.*)\n\t\t. = ALIGN(4);\n\t} > MFlash32\n\n\t\/*\n\t * for exception handling\/unwind - some Newlib functions (in common\n\t * with C++ and STDC++) use this.\n\t *\/\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > MFlash32\n\t__exidx_start = .;\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > MFlash32\n\t__exidx_end = .;\n\n\t_etext = .;\n\n\t\/* MAIN DATA SECTION *\/\n\t.uninit_RESERVED : ALIGN(4)\n\t{\n\t\tKEEP(*(.bss.$RESERVED*))\n\t\t. = ALIGN(4);\n\t\t_end_uninit_RESERVED = .;\n\t} > RamLoc4\n\n\t\/* Main DATA section (RamLoc4) *\/\n\t.data : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t_data = .;\n\t\t*(vtable)\n\t\t*(.ramfunc*)\n\t\t*(.data*)\n\t\t. = ALIGN(4);\n\t\t_edata = .;\n\t} > RamLoc4 AT>MFlash32\n\n\t\/* MAIN BSS SECTION *\/\n\t.bss : ALIGN(4)\n\t{\n\t\t_bss = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4) ;\n\t\t_ebss = .;\n\t\tPROVIDE(end = .);\n\t} > RamLoc4\n\n\t\/* DEFAULT NOINIT SECTION *\/\n\t.noinit (NOLOAD): ALIGN(4)\n\t{\n\t\t_noinit = .;\n\t\t*(.noinit*)\n\t\t. = ALIGN(4) ;\n\t\t_end_noinit = .;\n\t} > RamLoc4\n\n\tPROVIDE(_pvHeapStart = .);\n\tPROVIDE(_vStackTop = __top_RamLoc4 - 0);\n}\n","old_contents":"MEMORY\n{\n\t\/* Define each memory region *\/\n\tMFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 \/* 32K bytes *\/\n\tRamLoc4 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x1000 \/* 4K bytes *\/\n\tRamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 \/* 2K bytes *\/\n}\n\n\/* Define a symbol for the top of each memory region *\/\n__top_MFlash32 = 0x0 + 0x8000;\n__top_RamLoc4 = 0x10000000 + 0x1000;\n__top_RamUsb2 = 0x20004000 + 0x800;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\t\/* MAIN TEXT SECTION *\/\n\t.text : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t__vectors_start__ = ABSOLUTE(.);\n\t\tKEEP(*(.isr_vector))\n\n\t\t\/* Global Section Table *\/\n\t\t. = ALIGN(4);\n\t\t__section_table_start = .;\n\t\t__data_section_table = .;\n\t\tLONG(LOADADDR(.data));\n\t\tLONG(ADDR(.data));\n\t\tLONG(SIZEOF(.data));\n\t\tLONG(LOADADDR(.data_RAM2));\n\t\tLONG(ADDR(.data_RAM2));\n\t\tLONG(SIZEOF(.data_RAM2));\n\t\t__data_section_table_end = .;\n\t\t__bss_section_table = .;\n\t\tLONG(ADDR(.bss));\n\t\tLONG(SIZEOF(.bss));\n\t\tLONG(ADDR(.bss_RAM2));\n\t\tLONG(SIZEOF(.bss_RAM2));\n\t\t__bss_section_table_end = .;\n\t\t__section_table_end = . ;\n\t\t\/* End of Global Section Table *\/\n\n\t\t*(.after_vectors*)\n\n\t\t\/* Code Read Protect data *\/\n\t\t. = 0x000002FC;\n\t\tPROVIDE(__CRP_WORD_START__ = .);\n\t\tKEEP(*(.crp))\n\t\tPROVIDE(__CRP_WORD_END__ = .);\n\t\tASSERT(!(__CRP_WORD_START__ == __CRP_WORD_END__), \"Linker CRP Enabled, but no CRP_WORD provided within application\");\n\t\t\/* End of Code Read Protect *\/\n\t} >MFlash32\n\n\t.text : ALIGN(4)\n\t{\n\t\t*(.text*)\n\t\t*(.rodata .rodata.* .constdata .constdata.*)\n\t\t. = ALIGN(4);\n\t} > MFlash32\n\n\t\/*\n\t * for exception handling\/unwind - some Newlib functions (in common\n\t * with C++ and STDC++) use this.\n\t *\/\n\t.ARM.extab : ALIGN(4)\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > MFlash32\n\t__exidx_start = .;\n\n\t.ARM.exidx : ALIGN(4)\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > MFlash32\n\t__exidx_end = .;\n\n\t_etext = .;\n\n\t\/* DATA section for RamUsb2 *\/\n\t.data_RAM2 : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t*(.ramfunc.$RAM2)\n\t\t*(.ramfunc.$RamUsb2)\n\t\t*(.data.$RAM2*)\n\t\t*(.data.$RamUsb2*)\n\t\t. = ALIGN(4);\n\t} > RamUsb2 AT>MFlash32\n\n\t\/* MAIN DATA SECTION *\/\n\t.uninit_RESERVED : ALIGN(4)\n\t{\n\t\tKEEP(*(.bss.$RESERVED*))\n\t\t. = ALIGN(4);\n\t\t_end_uninit_RESERVED = .;\n\t} > RamLoc4\n\n\t\/* Main DATA section (RamLoc4) *\/\n\t.data : ALIGN(4)\n\t{\n\t\tFILL(0xff)\n\t\t_data = .;\n\t\t*(vtable)\n\t\t*(.ramfunc*)\n\t\t*(.data*)\n\t\t. = ALIGN(4);\n\t\t_edata = .;\n\t} > RamLoc4 AT>MFlash32\n\n\t\/* BSS section for RamUsb2 *\/\n\t.bss_RAM2 : ALIGN(4)\n\t{\n\t\t*(.bss.$RAM2*)\n\t\t*(.bss.$RamUsb2*)\n\t\t. = ALIGN(4);\n\t} > RamUsb2\n\n\t\/* MAIN BSS SECTION *\/\n\t.bss : ALIGN(4)\n\t{\n\t\t_bss = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4) ;\n\t\t_ebss = .;\n\t\tPROVIDE(end = .);\n\t} > RamLoc4\n\n\t\/* NOINIT section for RamUsb2 *\/\n\t.noinit_RAM2 (NOLOAD) : ALIGN(4)\n\t{\n\t\t*(.noinit.$RAM2*)\n\t\t*(.noinit.$RamUsb2*)\n\t\t. = ALIGN(4);\n\t} > RamUsb2\n\n\t\/* DEFAULT NOINIT SECTION *\/\n\t.noinit (NOLOAD): ALIGN(4)\n\t{\n\t\t_noinit = .;\n\t\t*(.noinit*)\n\t\t. = ALIGN(4) ;\n\t\t_end_noinit = .;\n\t} > RamLoc4\n\n\tPROVIDE(_pvHeapStart = .);\n\tPROVIDE(_vStackTop = __top_RamLoc4 - 0);\n}\n","returncode":0,"stderr":"","license":"unlicense","lang":"Linker Script"}
{"commit":"7f4901b8a68596f47f487121f890ee8b2bac5c0c","subject":"x86: 32-bit: remove mmu region list","message":"x86: 32-bit: remove mmu region list\n\nThis related to old infrastructure which has been removed\nfrom Zephyr.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,Vudentz\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/x86\/ia32\/linker.ld","new_file":"include\/arch\/x86\/ia32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <sys\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n#ifdef CONFIG_XIP\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame_hdr)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n#ifdef CONFIG_XIP\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n#endif\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n#include <linker\/common-noinit.ld>\n\n\tMMU_PAGE_ALIGN\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif \/* LINKER_PASS2 *\/\n\n\tz_interrupt_vectors_allocated = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_vectors_alloc))\n#else\n\t. += (CONFIG_IDT_NUM_VECTORS + 7) \/ 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_X86_KPTI\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_start = .;\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. IDT, GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\/\n#endif \/* CONFIG_X86_KPTI *\/\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_KPTI\n\tz_trampoline_stack_start = .;\n\tMMU_PAGE_ALIGN\n\tz_trampoline_stack_end = .;\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_trampoline_stack_end - z_trampoline_stack_start >= 40,\n\t\t\"trampoline stack too small\");\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Common linker sections\n *\n * This script defines the memory location of the various sections that make up\n * a Zephyr Kernel image. This file is used by the linker.\n *\n * This script places the various sections of the image according to what\n * features are enabled by the kernel's configuration options.\n *\n * For a build that does not use the execute in place (XIP) feature, the script\n * generates an image suitable for loading into and executing from RAMABLE_REGION by\n * placing all the sections adjacent to each other.  There is also no separate\n * load address for the DATA section which means it doesn't have to be copied\n * into RAMABLE_REGION.\n *\n * For builds using XIP, there is a different load memory address (LMA) and\n * virtual memory address (VMA) for the DATA section.  In this case the DATA\n * section is copied into RAMABLE_REGION at runtime.\n *\n * When building an XIP image the data section is placed into ROMABLE_REGION.  In this\n * case, the LMA is set to __data_rom_start so the data section is concatenated\n * at the end of the RODATA section.  At runtime, the DATA section is copied\n * into the RAMABLE_REGION region so it can be accessed with read and write permission.\n *\n * Most symbols defined in the sections below are subject to be referenced in\n * the Zephyr Kernel image. If a symbol is used but not defined the linker will\n * emit an undefined symbol error.\n *\n * Please do not change the order of the section as the kernel expects this\n * order when programming the MMU.\n *\/\n\n#include <linker\/linker-defs.h>\n#include <offsets.h>\n#include <sys\/util.h>\n\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n\t#define ROMABLE_REGION ROM\n\t#define RAMABLE_REGION RAM\n#else\n\t#define ROMABLE_REGION RAM\n\t#define RAMABLE_REGION RAM\n#endif\n\n\/* Used to align areas with separate memory permission characteristics\n * so that the page permissions can be set in the MMU. Without this,\n * the kernel is just one blob with the same RWX permissions on all RAM\n *\/\n#ifdef CONFIG_SRAM_REGION_PERMISSIONS\n\t#define MMU_PAGE_ALIGN\t. = ALIGN(CONFIG_MMU_PAGE_SIZE);\n#else\n\t#define MMU_PAGE_ALIGN\n#endif\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\n\/* SECTIONS definitions *\/\nSECTIONS\n\t{\n\n#include <linker\/rel-sections.ld>\n\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n\n\tGROUP_START(ROMABLE_REGION)\n\n\t. = ALIGN(8);\n\n#ifdef CONFIG_XIP\n\t_image_rom_start = PHYS_LOAD_ADDR;\n#endif\n\tSECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t_image_text_start = .;\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t*(.text_start)\n\t*(\".text_start.*\")\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame_hdr)\n\t*(.eh_frame)\n\t*(.init)\n\t*(.fini)\n\t*(.eini)\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n#include <linker\/kobject-text.ld>\n\n\tMMU_PAGE_ALIGN\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\t_image_text_size = _image_text_end - _image_text_start;\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n\tSECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n#ifdef CONFIG_X86_MMU\n\t. = ALIGN(4);\n\t_mmu_region_list_start = .;\n\tKEEP(*(\"._mmu_region.static.*\"))\n\t_mmu_region_list_end = .;\n#endif \/* CONFIG_X86_MMU *\/\n\n#ifndef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n\tMMU_PAGE_ALIGN\n\t\/* ROM ends here, position counter will now be in RAM areas *\/\n#ifdef CONFIG_XIP\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n#endif\n\t_image_rodata_end = .;\n\t_image_rodata_size = _image_rodata_end - _image_rodata_start;\n\tGROUP_END(ROMABLE_REGION)\n\t\/*\n\t * Needed for dynamic linking which we do not have, do discard\n\t *\/\n\t\/DISCARD\/ : {\n\t\t*(.got.plt)\n\t\t*(.igot.plt)\n\t\t*(.got)\n\t\t*(.igot)\n\t}\n\t\/* RAMABLE_REGION *\/\n\tGROUP_START(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#ifdef CONFIG_USERSPACE\n\t\/* APP SHARED MEMORY REGION *\/\n#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN\n#define APP_SHARED_ALIGN  MMU_PAGE_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_num_words = _app_smem_size >> 2;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n\t_app_smem_num_words = _app_smem_size >> 2;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tSECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD),)\n\t{\n\tMMU_PAGE_ALIGN\n#if !defined(CONFIG_USERSPACE)\n\t_image_ram_start = .;\n#endif\n\t\/*\n\t * For performance, BSS section is forced to be both 4 byte aligned and\n\t * a multiple of 4 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__kernel_ram_start = .;\n\t__bss_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n\t\/*\n\t * As memory is cleared in words only, it is simpler to ensure the BSS\n\t * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t *\/\n\t. = ALIGN(4);\n\t__bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n\t__bss_num_words\t= (__bss_end - __bss_start) >> 2;\n\n#include <linker\/common-noinit.ld>\n\n\tMMU_PAGE_ALIGN\n\n\tSECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(4);\n\t_irq_to_interrupt_vector = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_int_vector_map))\n#else\n\t. += CONFIG_MAX_IRQ_LINES;\n#endif \/* LINKER_PASS2 *\/\n\n\tz_interrupt_vectors_allocated = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(irq_vectors_alloc))\n#else\n\t. += (CONFIG_IDT_NUM_VECTORS + 7) \/ 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n#ifdef CONFIG_X86_KPTI\n\tMMU_PAGE_ALIGN\n\tz_shared_kernel_page_start = .;\n\t\/* Special page containing supervisor data that is still mapped in\n\t * user mode page tables. IDT, GDT, TSSes, trampoline stack, and\n\t * any LDT must go here as they always must live in a page that is\n\t * marked 'present'. Still not directly user accessible, but\n\t * no sensitive data should be here as Meltdown exploits may read it.\n\t *\/\n#endif \/* CONFIG_X86_KPTI *\/\n\n#ifdef CONFIG_DYNAMIC_INTERRUPTS\n\t. = ALIGN(8);\n\t_idt_base_address = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(staticIdt))\n#else\n\t. += CONFIG_IDT_NUM_VECTORS * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_DYNAMIC_INTERRUPTS *\/\n\n#ifdef CONFIG_GDT_DYNAMIC\n\tKEEP(*(.tss))\n\t. = ALIGN(8);\n\t_gdt = .;\n#ifdef LINKER_PASS2\n\tKEEP(*(gdt))\n#else \/* LINKER_PASS2 *\/\n\n#ifdef CONFIG_USERSPACE\n    #define GDT_NUM_ENTRIES 7\n#elif defined(CONFIG_HW_STACK_PROTECTION)\n    #define GDT_NUM_ENTRIES 5\n#else\n    #define GDT_NUM_ENTRIES 3\n#endif \/* CONFIG_X86_USERSPACE *\/\n\t. += GDT_NUM_ENTRIES * 8;\n#endif \/* LINKER_PASS2 *\/\n#endif \/* CONFIG_GDT_DYNAMIC *\/\n\n#ifdef CONFIG_X86_KPTI\n\tz_trampoline_stack_start = .;\n\tMMU_PAGE_ALIGN\n\tz_trampoline_stack_end = .;\n\tz_shared_kernel_page_end = .;\n\n\tASSERT(z_trampoline_stack_end - z_trampoline_stack_start >= 40,\n\t\t\"trampoline stack too small\");\n\tASSERT(z_shared_kernel_page_end - z_shared_kernel_page_start == 4096,\n\t       \"shared kernel area is not one memory page\");\n#endif \/* CONFIG_X86_KPTI *\/\n\n\t. = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n#include <arch\/x86\/pagetables.ld>\n\n\/* Must be last in RAM *\/\n#include <linker\/kobject.ld>\n\n\tMMU_PAGE_ALIGN\n\t__data_ram_end = .;\n\n\t\/* All unused memory also owned by the kernel for heaps *\/\n\t__kernel_ram_end = KERNEL_BASE_ADDR + KERNEL_RAM_SIZE;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\t_image_ram_end = .;\n\t_image_ram_all = (KERNEL_BASE_ADDR + KERNEL_RAM_SIZE) - _image_ram_start;\n\n\t_end = .; \/* end of image *\/\n\n\tGROUP_END(RAMABLE_REGION)\n\n#ifndef LINKER_PASS2\n\t\/* static interrupts *\/\n\tSECTION_PROLOGUE(intList,,)\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t} > IDT_LIST\n#else\n\t\/DISCARD\/ :\n\t{\n\tKEEP(*(.spurIsr))\n\tKEEP(*(.spurNoErrIsr))\n\tKEEP(*(.intList))\n\tKEEP(*(.gnu.linkonce.intList.*))\n\t}\n#endif\n\n\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n\t\/DISCARD\/ : { *(.note.GNU-stack) }\n\n\t}\n\n#ifdef CONFIG_XIP\n\/*\n * Round up number of words for DATA section to ensure that XIP copies the\n * entire data section. XIP copy is done in words only, so there may be up\n * to 3 extra bytes copied in next section (BSS). At run time, the XIP copy\n * is done first followed by clearing the BSS section.\n *\/\n__data_size = (__data_ram_end - __data_ram_start);\n__data_num_words = (__data_size + 3) >> 2;\n#endif\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1af54fa124fcf659405282b15f91f0959f45c037","subject":"[x86_64] reserve a non-tiny amount of heap space for now","message":"[x86_64] reserve a non-tiny amount of heap space for now\n\nTODO: this is Bad, heap should grow dynamically from frame alloc?\n","repos":"rachlmac\/sos-kernel,hawkw\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel,hawkw\/sos-kernel,rachlmac\/sos-kernel","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .rodata :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n        *(.rodata .rodata.*)\n    }\n\n    .text ALIGN(4K) :\n    {\n     \/* NOTE we use KEEP here to prevent the linker from dropping\n        these symbols\n      *\/\n        KEEP(*(.text._start))\n        KEEP(*(.text.arch_init))\n        *(.text .text.*)\n    }\n\n     .data ALIGN(4K) :\n     {\n       *(.data .data.*)\n     }\n\n     .bss ALIGN(4K) :\n     {\n\n        *(.bss .bss.*)\n        . = ALIGN(4K);\n\n        \/* Page-Map Level-4 Table (PML4) *\/\n        pml4_table = .;\n        . += 4096;\n        \/* Page-Directory Pointer Table (PDP) *\/\n        pdp_table = .;\n        . += 4096;\n        \/* Page-Directory Table (PD) *\/\n        pd_table = .;\n        . += 4096;\n\n        stack_base = .;\n        . += 4K * 2;\n        stack_top = .;\n\n        heap_base_addr = .;\n        . += 4K * 2K;\n        heap_top_addr = .;\n     }\n\n    .data.rel.ro : ALIGN(4K) {\n       *(.data.rel.ro.local*)\n       *(.data.rel.ro .data.rel.ro.*)\n    }\n\n    .gcc_except_table : ALIGN(4K) {\n      *(.gcc_except_table)\n      . = ALIGN(4096);\n    }\n}\n","old_contents":"\/* Based on http:\/\/blog.phil-opp.com\/rust-os\/multiboot-kernel.html\n *\n * Used to specify a custom linking layout that puts our multiboot header\n * before everything else.\n *\/\n\nENTRY(_start)\n\nSECTIONS {\n    . = 0xb8000;\n    __vga_buffer = .;\n    . += 80 * 24 * 2;\n\n    \/* Load the kernel reasonably high in memory to avoid special addresses. *\/\n    . = 1M;\n\n    .rodata :\n    {\n        \/* This goes first. *\/\n        KEEP(*(.multiboot_header))\n        *(.rodata .rodata.*)\n    }\n\n    .text ALIGN(4K) :\n    {\n     \/* NOTE we use KEEP here to prevent the linker from dropping\n        these symbols\n      *\/\n        KEEP(*(.text._start))\n        KEEP(*(.text.arch_init))\n        *(.text .text.*)\n    }\n\n     .data ALIGN(4K) :\n     {\n       *(.data .data.*)\n     }\n\n     .bss ALIGN(4K) :\n     {\n        \/* Page-Map Level-4 Table (PML4) *\/\n        pml4_table = .;\n        . += 4096;\n        \/* Page-Directory Pointer Table (PDP) *\/\n        pdp_table = .;\n        . += 4096;\n        \/* Page-Directory Table (PD) *\/\n        pd_table = .;\n        . += 4096;\n\n        stack_base = .;\n        . += 4K * 2;\n        stack_top = .;\n\n        heap_base_addr = .;\n        . += 4K * 2;\n        heap_top_addr = .;\n        *(.bss .bss.*)\n     }\n\n    .data.rel.ro : ALIGN(4K) {\n       *(.data.rel.ro.local*)\n       *(.data.rel.ro .data.rel.ro.*)\n    }\n\n    .gcc_except_table : ALIGN(4K) {\n      *(.gcc_except_table)\n      . = ALIGN(4096);\n    }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f84f52a5c15db7d14a534815f27253b001735183","subject":"m68knommu: clean up linker script","message":"m68knommu: clean up linker script\n\nThere is a lot of years of collected cruft in the m68knommu linker script.\nClean it all up and use the well defined linker script support macros.\n\nSupport is maintained for building both ROM\/FLASH based and RAM based setups.\nNo major changes to section layouts, though the rodata section is now lumped\nin with the read\/write data section.\n\nSigned-off-by: Greg Ungerer <ed22c22dbde360207569092e60b4298397efb8da@uclinux.org>\n","repos":"TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs","old_file":"arch\/m68k\/kernel\/vmlinux-nommu.lds","new_file":"arch\/m68k\/kernel\/vmlinux-nommu.lds","new_contents":"\/*\n *\tvmlinux.lds.S -- master linker script for m68knommu arch\n *\n *\t(C) Copyright 2002-2012, Greg Ungerer <gerg@snapgear.com>\n *\n *\tThis linker script is equipped to build either ROM loaded or RAM\n *\trun kernels.\n *\/\n\n#if defined(CONFIG_RAMKERNEL)\n#define\tKTEXT_ADDR\tCONFIG_KERNELBASE\n#endif\n#if defined(CONFIG_ROMKERNEL)\n#define\tKTEXT_ADDR\tCONFIG_ROMSTART\n#define\tKDATA_ADDR\tCONFIG_KERNELBASE\n#define\tLOAD_OFFSET\tKDATA_ADDR + (ADDR(.text) + SIZEOF(.text))\n#endif\n\n#include <asm\/page.h>\n#include <asm\/thread_info.h>\n#include <asm-generic\/vmlinux.lds.h>\n\nOUTPUT_ARCH(m68k)\nENTRY(_start)\n\njiffies = jiffies_64 + 4;\n\nSECTIONS {\n\n#ifdef CONFIG_ROMVEC\n\t. = CONFIG_ROMVEC;\n\t.romvec : {\n\t\t__rom_start = .;\n\t\t_romvec = .;\n\t\t*(.romvec)\n\t\t*(.data..initvect)\n\t}\n#endif\n\n\t. = KTEXT_ADDR;\n\n\t_text = .;\n\t_stext = .;\n\t.text : {\n\t\tHEAD_TEXT\n\t\tTEXT_TEXT\n\t\tSCHED_TEXT\n\t\tLOCK_TEXT\n\t\t*(.fixup)\n\t\t. = ALIGN(16);\n\t}\n\t_etext = .;\n\n#ifdef KDATA_ADDR\n\t. = KDATA_ADDR;\n#endif\n\n\t_sdata = .;\n\tRO_DATA_SECTION(PAGE_SIZE)\n\tRW_DATA_SECTION(16, PAGE_SIZE, THREAD_SIZE)\n\t_edata = .;\n\n\tEXCEPTION_TABLE(16)\n\tNOTES\n\n\t. = ALIGN(PAGE_SIZE);\n\t__init_begin = .;\n\tINIT_TEXT_SECTION(PAGE_SIZE)\n\tINIT_DATA_SECTION(16)\n\tPERCPU_SECTION(16)\n\t.m68k_fixup : {\n\t\t__start_fixup = .;\n\t\t*(.m68k_fixup)\n\t\t__stop_fixup = .;\n\t}\n\t.init.data : {\n\t\t. = ALIGN(PAGE_SIZE);\n\t\t__init_end = .;\n\t}\n\n\t_sbss = .;\n\tBSS_SECTION(0, 0, 0)\n\t_ebss = .;\n\n\t_end = .;\n\n\tSTABS_DEBUG\n\t.comment 0 : { *(.comment) }\n\n\t\/* Sections to be discarded *\/\n\tDISCARDS\n}\n\n","old_contents":"\/*\n *\tvmlinux.lds.S -- master linker script for m68knommu arch\n *\n *\t(C) Copyright 2002-2006, Greg Ungerer <gerg@snapgear.com>\n *\n *\tThis linker script is equipped to build either ROM loaded or RAM\n *\trun kernels.\n *\/\n\n#include <asm-generic\/vmlinux.lds.h>\n#include <asm\/page.h>\n#include <asm\/thread_info.h>\n\n#if defined(CONFIG_RAMKERNEL)\n#define\tRAM_START\tCONFIG_KERNELBASE\n#define\tRAM_LENGTH\t(CONFIG_RAMBASE + CONFIG_RAMSIZE - CONFIG_KERNELBASE)\n#define\tTEXT\t\tram\n#define\tDATA\t\tram\n#define\tINIT\t\tram\n#define\tBSSS\t\tram\n#endif\n#if defined(CONFIG_ROMKERNEL) || defined(CONFIG_HIMEMKERNEL)\n#define\tRAM_START\tCONFIG_RAMBASE\n#define\tRAM_LENGTH\tCONFIG_RAMSIZE\n#define\tROMVEC_START\tCONFIG_ROMVEC\n#define\tROMVEC_LENGTH\tCONFIG_ROMVECSIZE\n#define\tROM_START\tCONFIG_ROMSTART\n#define\tROM_LENGTH\tCONFIG_ROMSIZE\n#define\tTEXT\t\trom\n#define\tDATA\t\tram\n#define\tINIT\t\tram\n#define\tBSSS\t\tram\n#endif\n\n#ifndef DATA_ADDR\n#define\tDATA_ADDR\n#endif\n\n\nOUTPUT_ARCH(m68k)\nENTRY(_start)\n\nMEMORY {\n\tram\t: ORIGIN = RAM_START, LENGTH = RAM_LENGTH\n#ifdef ROM_START\n\tromvec\t: ORIGIN = ROMVEC_START, LENGTH = ROMVEC_LENGTH\n\trom\t: ORIGIN = ROM_START, LENGTH = ROM_LENGTH\n#endif\n}\n\njiffies = jiffies_64 + 4;\n\nSECTIONS {\n\n#ifdef ROMVEC_START\n\t. = ROMVEC_START ;\n\t.romvec : {\n\t\t__rom_start = . ;\n\t\t_romvec = .;\n\t\t*(.data..initvect)\n\t} > romvec\n#endif\n\n\t.text : {\n\t\t_text = .;\n\t\t_stext = . ;\n\t\tHEAD_TEXT\n\t\tTEXT_TEXT\n\t\tSCHED_TEXT\n\t\tLOCK_TEXT\n\t\t*(.text..lock)\n\t\t*(.fixup)\n\n\t\t. = ALIGN(16);          \/* Exception table              *\/\n\t\t__start___ex_table = .;\n\t\t*(__ex_table)\n\t\t__stop___ex_table = .;\n\n\t\t*(.rodata) *(.rodata.*)\n\t\t*(__vermagic)\t\t\/* Kernel version magic *\/\n\t\t*(.rodata1)\n\t\t*(.rodata.str1.1)\n\n\t\t\/* Kernel symbol table: Normal symbols *\/\n\t\t. = ALIGN(4);\n\t\t__start___ksymtab = .;\n\t\t*(SORT(___ksymtab+*))\n\t\t__stop___ksymtab = .;\n\n\t\t\/* Kernel symbol table: GPL-only symbols *\/\n\t\t__start___ksymtab_gpl = .;\n\t\t*(SORT(___ksymtab_gpl+*))\n\t\t__stop___ksymtab_gpl = .;\n\n\t\t\/* Kernel symbol table: Normal unused symbols *\/\n\t\t__start___ksymtab_unused = .;\n\t\t*(SORT(___ksymtab_unused+*))\n\t\t__stop___ksymtab_unused = .;\n\n\t\t\/* Kernel symbol table: GPL-only unused symbols *\/\n\t\t__start___ksymtab_unused_gpl = .;\n\t\t*(SORT(___ksymtab_unused_gpl+*))\n\t\t__stop___ksymtab_unused_gpl = .;\n\n\t\t\/* Kernel symbol table: GPL-future symbols *\/\n\t\t__start___ksymtab_gpl_future = .;\n\t\t*(SORT(___ksymtab_gpl_future+*))\n\t\t__stop___ksymtab_gpl_future = .;\n\n\t\t\/* Kernel symbol table: Normal symbols *\/\n\t\t__start___kcrctab = .;\n\t\t*(SORT(___kcrctab+*))\n\t\t__stop___kcrctab = .;\n\n\t\t\/* Kernel symbol table: GPL-only symbols *\/\n\t\t__start___kcrctab_gpl = .;\n\t\t*(SORT(___kcrctab_gpl+*))\n\t\t__stop___kcrctab_gpl = .;\n\n\t\t\/* Kernel symbol table: Normal unused symbols *\/\n\t\t__start___kcrctab_unused = .;\n\t\t*(SORT(___kcrctab_unused+*))\n\t\t__stop___kcrctab_unused = .;\n\n\t\t\/* Kernel symbol table: GPL-only unused symbols *\/\n\t\t__start___kcrctab_unused_gpl = .;\n\t\t*(SORT(___kcrctab_unused_gpl+*))\n\t\t__stop___kcrctab_unused_gpl = .;\n\n\t\t\/* Kernel symbol table: GPL-future symbols *\/\n\t\t__start___kcrctab_gpl_future = .;\n\t\t*(SORT(___kcrctab_gpl_future+*))\n\t\t__stop___kcrctab_gpl_future = .;\n\n\t\t\/* Kernel symbol table: strings *\/\n\t\t*(__ksymtab_strings)\n\n\t\t\/* Built-in module parameters *\/\n\t\t. = ALIGN(4) ;\n\t\t__start___param = .;\n\t\t*(__param)\n\t\t__stop___param = .;\n\n\t\t\/* Built-in module versions *\/\n\t\t. = ALIGN(4) ;\n\t\t__start___modver = .;\n\t\t*(__modver)\n\t\t__stop___modver = .;\n\n\t\t. = ALIGN(4) ;\n\t\t_etext = . ;\n\t} > TEXT\n\n\t.data DATA_ADDR : {\n\t\t. = ALIGN(4);\n\t\t_sdata = . ;\n\t\tDATA_DATA\n\t\tCACHELINE_ALIGNED_DATA(32)\n\t\tPAGE_ALIGNED_DATA(PAGE_SIZE)\n\t\t*(.data..shared_aligned)\n\t\tINIT_TASK_DATA(THREAD_SIZE)\n\t\t_edata = . ;\n\t} > DATA\n\n\t.m68k_fixup : {\n\t\t__start_fixup = .;\n\t\t*(.m68k_fixup)\n\t\t__stop_fixup = .;\n\t} > DATA\n\tNOTES > DATA\n\n\t.init.text : {\n\t\t. = ALIGN(PAGE_SIZE);\n\t\t__init_begin = .;\n\t} > INIT\n\tINIT_TEXT_SECTION(PAGE_SIZE) > INIT\n\tINIT_DATA_SECTION(16) > INIT\n\t.init.data : {\n\t\t. = ALIGN(PAGE_SIZE);\n\t\t__init_end = .;\n\t} > INIT\n\n\t.bss : {\n\t\t. = ALIGN(4);\n\t\t_sbss = . ;\n\t\t*(.bss)\n\t\t*(COMMON)\n\t\t. = ALIGN(4) ;\n\t\t_ebss = . ;\n\t \t_end = . ;\n\t} > BSSS\n\n\tDISCARDS\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1efa3a64ed2dfdccf86e38c5a8c7431319812137","subject":"configs\/imxrt1050-evk: fix description of ld script, Kb -> KB","message":"configs\/imxrt1050-evk: fix description of ld script, Kb -> KB\n\nThe linker script has the length of each part in kilbytes, not in kilobits.\nTo avoid giving wrong information, let's modify Kb to KB.\n\nSigned-off-by: sunghan-chang <c954e25285721d8faa8b1a5c1ae2ef5a35338d32@samsung.com>\n","repos":"chanijjani\/TizenRT,pillip8282\/TizenRT,chanijjani\/TizenRT,jsdosa\/TizenRT,jsdosa\/TizenRT,jsdosa\/TizenRT,davidfather\/TizenRT,chanijjani\/TizenRT,sunghan-chang\/TizenRT,sunghan-chang\/TizenRT,pillip8282\/TizenRT,chanijjani\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,jeongchanKim\/TizenRT,jeongarmy\/TizenRT,jeongchanKim\/TizenRT,chanijjani\/TizenRT,chanijjani\/TizenRT,davidfather\/TizenRT,jeongchanKim\/TizenRT,pillip8282\/TizenRT,jsdosa\/TizenRT,jeongchanKim\/TizenRT,junmin-kim\/TizenRT,an4967\/TizenRT,davidfather\/TizenRT,Samsung\/TizenRT,jsdosa\/TizenRT,Samsung\/TizenRT,jsdosa\/TizenRT,junmin-kim\/TizenRT,Samsung\/TizenRT,junmin-kim\/TizenRT,davidfather\/TizenRT,jeongchanKim\/TizenRT,sunghan-chang\/TizenRT,pillip8282\/TizenRT,davidfather\/TizenRT,jeongarmy\/TizenRT,jeongchanKim\/TizenRT,jsdosa\/TizenRT,chanijjani\/TizenRT,davidfather\/TizenRT,an4967\/TizenRT,Samsung\/TizenRT,sunghan-chang\/TizenRT,junmin-kim\/TizenRT,jeongchanKim\/TizenRT,an4967\/TizenRT,Samsung\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT,an4967\/TizenRT,an4967\/TizenRT,Samsung\/TizenRT,junmin-kim\/TizenRT,sunghan-chang\/TizenRT,an4967\/TizenRT,junmin-kim\/TizenRT,an4967\/TizenRT,jeongarmy\/TizenRT,jeongarmy\/TizenRT,junmin-kim\/TizenRT,pillip8282\/TizenRT,jeongarmy\/TizenRT,pillip8282\/TizenRT,jeongarmy\/TizenRT,davidfather\/TizenRT,sunghan-chang\/TizenRT","old_file":"build\/configs\/imxrt1050-evk\/scripts\/memory.ld","new_file":"build\/configs\/imxrt1050-evk\/scripts\/memory.ld","new_contents":"\/****************************************************************************\n *\n * Copyright 2019 NXP Semiconductors All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * build\/configs\/simxrt1050-evk\/scripts\/memory.ld\n *\n *   Copyright (C) 2018 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name TinyARA nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The i.MXRT1050-EVK has 64MB of Hyper FLASH beginning at address,\n * 0x0060:0000, 512KB of DTCM RAM beginning at 0x2000:0000, and 512KB OCRAM\n * beginning at 0x2020:0000.  Neither DTCM or SDRAM are used in this\n * configuratin.\n *\n * The user and kernel space partitions will be spanned with a single\n * region of size 2**n bytes.  As a consequence, as the partitions increase\n * in size, the alignment requirement also increases.  The sizes below give\n * the largest possible user address spaces (but leave far too much for the\n * OS).\n *\n * The solution to this wasted memory is to (1) use more than one region to\n * span the user spaces, or (2) poke holes in a larger region (via sub-\n * regions) to trim it to fit better.\n *\n * A detailed memory map for the 512KB SRAM region is as follows:\n *\n *   0x2020 0000:  Kernel .data region.  Typical size: 0.1KB\n *   ------ ----   Kernel .bss  region.  Typical size: 1.8KB\n *   0x2020 0800:  Kernel IDLE thread stack (approximate).  Size is\n *                 determined by CONFIG_IDLETHREAD_STACKSIZE and\n *                 adjustments for alignment.  Typical is 1KB.\n *   ------ ----   Padded to 4KB\n *   0x2040 0000:  User .data region.  Size is variable.\n *   ------- ----  User .bss region  Size is variable.\n *   0x2042 0000:  Beginning of kernel heap.  Size determined by\n *                 CONFIG_MM_KERNEL_HEAPSIZE.\n *   ------ ----   Beginning of user heap.  Can vary with other settings.\n *   0x2080 0000:  End+1 of mappable OCRAM\n *\/\n\n\/* Specify the memory areas *\/\n\nMEMORY\n{\n  \/* 64MB of HyperFLASH *\/\n\n  kflash (rx)  : ORIGIN = 0x60000000, LENGTH = 1M\n  uflash (rx)  : ORIGIN = 0x60200000, LENGTH = 1M\n  flash  (rx)  : ORIGIN = 0x60400000, LENGTH = 62M\n\n  \/* 512KB of OCRAM *\/\n\n  dtcm   (rwx) : ORIGIN = 0x20000000, LENGTH = 512K\n  kocram (rwx) : ORIGIN = 0x20200000, LENGTH = 256K\n  uocram (rwx) : ORIGIN = 0x20240000, LENGTH = 256K\n  \n  itcm\t (rwx) : ORIGIN = 0x00000000, LENGTH = 512K\n}\n","old_contents":"\/****************************************************************************\n *\n * Copyright 2019 NXP Semiconductors All Rights Reserved.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,\n * either express or implied. See the License for the specific\n * language governing permissions and limitations under the License.\n *\n ****************************************************************************\/\n\/****************************************************************************\n * build\/configs\/simxrt1050-evk\/scripts\/memory.ld\n *\n *   Copyright (C) 2018 Gregory Nutt. All rights reserved.\n *   Author: Gregory Nutt <gnutt@nuttx.org>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and\/or other materials provided with the\n *    distribution.\n * 3. Neither the name TinyARA nor the names of its contributors may be\n *    used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS\n * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ****************************************************************************\/\n\n\/* The i.MXRT1050-EVK has 64Mb of Hyper FLASH beginning at address,\n * 0x0060:0000, 512Kb of DTCM RAM beginning at 0x2000:0000, and 512Kb OCRAM\n * beginning at 0x2020:0000.  Neither DTCM or SDRAM are used in this\n * configuratin.\n *\n * The user and kernel space partitions will be spanned with a single\n * region of size 2**n bytes.  As a consequence, as the partitions increase\n * in size, the alignment requirement also increases.  The sizes below give\n * the largest possible user address spaces (but leave far too much for the\n * OS).\n *\n * The solution to this wasted memory is to (1) use more than one region to\n * span the user spaces, or (2) poke holes in a larger region (via sub-\n * regions) to trim it to fit better.\n *\n * A detailed memory map for the 512KB SRAM region is as follows:\n *\n *   0x2020 0000:  Kernel .data region.  Typical size: 0.1KB\n *   ------ ----   Kernel .bss  region.  Typical size: 1.8KB\n *   0x2020 0800:  Kernel IDLE thread stack (approximate).  Size is\n *                 determined by CONFIG_IDLETHREAD_STACKSIZE and\n *                 adjustments for alignment.  Typical is 1KB.\n *   ------ ----   Padded to 4KB\n *   0x2040 0000:  User .data region.  Size is variable.\n *   ------- ----  User .bss region  Size is variable.\n *   0x2042 0000:  Beginning of kernel heap.  Size determined by\n *                 CONFIG_MM_KERNEL_HEAPSIZE.\n *   ------ ----   Beginning of user heap.  Can vary with other settings.\n *   0x2080 0000:  End+1 of mappable OCRAM\n *\/\n\n\/* Specify the memory areas *\/\n\nMEMORY\n{\n  \/* 64Mb of HyperFLASH *\/\n\n  kflash (rx)  : ORIGIN = 0x60000000, LENGTH = 1M\n  uflash (rx)  : ORIGIN = 0x60200000, LENGTH = 1M\n  flash  (rx)  : ORIGIN = 0x60400000, LENGTH = 62M\n\n  \/* 512Kb of OCRAM *\/\n\n  dtcm   (rwx) : ORIGIN = 0x20000000, LENGTH = 512K\n  kocram (rwx) : ORIGIN = 0x20200000, LENGTH = 256K\n  uocram (rwx) : ORIGIN = 0x20240000, LENGTH = 256K\n  \n  itcm\t (rwx) : ORIGIN = 0x00000000, LENGTH = 512K\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6ef9ecc1e1d702016c12d8ed1ee01bfedd1f6dd0","subject":"Update linker script for armgcc","message":"Update linker script for armgcc\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/ti-lm4f120xl-launchpad-ek\/target.ld","new_file":"boards\/ti-lm4f120xl-launchpad-ek\/target.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"unknown","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"259f1344ca38b202462d2d1b89e4820c110982ef","subject":"esp8266\/esp8266.ld: Link in SDK version section.","message":"esp8266\/esp8266.ld: Link in SDK version section.\n\nOtherwise, os.uname() returns empty string for SDK version.\n","repos":"henriknelson\/micropython,alex-robbins\/micropython,dinau\/micropython,toolmacher\/micropython,ganshun666\/micropython,PappaPeppar\/micropython,toolmacher\/micropython,pramasoul\/micropython,emfcamp\/micropython,cwyark\/micropython,matthewelse\/micropython,trezor\/micropython,MrSurly\/micropython-esp32,pfalcon\/micropython,drrk\/micropython,drrk\/micropython,dmazzella\/micropython,pramasoul\/micropython,pozetroninc\/micropython,Peetz0r\/micropython-esp32,TDAbboud\/micropython,toolmacher\/micropython,adafruit\/micropython,mhoffma\/micropython,HenrikSolver\/micropython,emfcamp\/micropython,alex-march\/micropython,Timmenem\/micropython,trezor\/micropython,blazewicz\/micropython,TDAbboud\/micropython,ryannathans\/micropython,bvernoux\/micropython,trezor\/micropython,oopy\/micropython,alex-march\/micropython,tuc-osg\/micropython,adafruit\/micropython,micropython\/micropython-esp32,AriZuu\/micropython,hosaka\/micropython,tobbad\/micropython,selste\/micropython,selste\/micropython,misterdanb\/micropython,adafruit\/circuitpython,torwag\/micropython,ryannathans\/micropython,adafruit\/circuitpython,PappaPeppar\/micropython,dxxb\/micropython,turbinenreiter\/micropython,hiway\/micropython,dinau\/micropython,henriknelson\/micropython,torwag\/micropython,mhoffma\/micropython,Timmenem\/micropython,micropython\/micropython-esp32,adafruit\/circuitpython,SHA2017-badge\/micropython-esp32,torwag\/micropython,bvernoux\/micropython,swegener\/micropython,hosaka\/micropython,PappaPeppar\/micropython,cwyark\/micropython,emfcamp\/micropython,puuu\/micropython,alex-robbins\/micropython,pfalcon\/micropython,oopy\/micropython,dmazzella\/micropython,adafruit\/micropython,alex-robbins\/micropython,mhoffma\/micropython,toolmacher\/micropython,turbinenreiter\/micropython,praemdonck\/micropython,turbinenreiter\/micropython,drrk\/micropython,hosaka\/micropython,adafruit\/circuitpython,jmarcelino\/pycom-micropython,alex-robbins\/micropython,tuc-osg\/micropython,trezor\/micropython,pozetroninc\/micropython,emfcamp\/micropython,hiway\/micropython,blazewicz\/micropython,dxxb\/micropython,hiway\/micropython,emfcamp\/micropython,kerneltask\/micropython,deshipu\/micropython,redbear\/micropython,micropython\/micropython-esp32,matthewelse\/micropython,SHA2017-badge\/micropython-esp32,pfalcon\/micropython,deshipu\/micropython,micropython\/micropython-esp32,MrSurly\/micropython,ganshun666\/micropython,HenrikSolver\/micropython,dxxb\/micropython,lowRISC\/micropython,alex-march\/micropython,MrSurly\/micropython-esp32,ganshun666\/micropython,turbinenreiter\/micropython,TDAbboud\/micropython,swegener\/micropython,blazewicz\/micropython,trezor\/micropython,alex-march\/micropython,oopy\/micropython,bvernoux\/micropython,MrSurly\/micropython,infinnovation\/micropython,adafruit\/micropython,henriknelson\/micropython,deshipu\/micropython,chrisdearman\/micropython,ryannathans\/micropython,pramasoul\/micropython,oopy\/micropython,misterdanb\/micropython,blazewicz\/micropython,lowRISC\/micropython,selste\/micropython,matthewelse\/micropython,chrisdearman\/micropython,tralamazza\/micropython,dxxb\/micropython,hiway\/micropython,swegener\/micropython,matthewelse\/micropython,praemdonck\/micropython,mhoffma\/micropython,hosaka\/micropython,pozetroninc\/micropython,infinnovation\/micropython,kerneltask\/micropython,torwag\/micropython,alex-robbins\/micropython,drrk\/micropython,toolmacher\/micropython,tuc-osg\/micropython,redbear\/micropython,SHA2017-badge\/micropython-esp32,bvernoux\/micropython,henriknelson\/micropython,HenrikSolver\/micropython,tralamazza\/micropython,misterdanb\/micropython,alex-march\/micropython,selste\/micropython,redbear\/micropython,turbinenreiter\/micropython,mpalomer\/micropython,torwag\/micropython,ryannathans\/micropython,pramasoul\/micropython,PappaPeppar\/micropython,misterdanb\/micropython,tralamazza\/micropython,ganshun666\/micropython,deshipu\/micropython,misterdanb\/micropython,mpalomer\/micropython,tobbad\/micropython,pozetroninc\/micropython,henriknelson\/micropython,kerneltask\/micropython,puuu\/micropython,SHA2017-badge\/micropython-esp32,SHA2017-badge\/micropython-esp32,MrSurly\/micropython,Peetz0r\/micropython-esp32,jmarcelino\/pycom-micropython,dinau\/micropython,Timmenem\/micropython,cwyark\/micropython,adafruit\/micropython,dmazzella\/micropython,puuu\/micropython,pozetroninc\/micropython,kerneltask\/micropython,Timmenem\/micropython,MrSurly\/micropython,pfalcon\/micropython,lowRISC\/micropython,adafruit\/circuitpython,redbear\/micropython,hosaka\/micropython,MrSurly\/micropython,AriZuu\/micropython,lowRISC\/micropython,infinnovation\/micropython,cwyark\/micropython,infinnovation\/micropython,mpalomer\/micropython,mpalomer\/micropython,puuu\/micropython,matthewelse\/micropython,praemdonck\/micropython,chrisdearman\/micropython,Peetz0r\/micropython-esp32,jmarcelino\/pycom-micropython,dinau\/micropython,tobbad\/micropython,TDAbboud\/micropython,MrSurly\/micropython-esp32,praemdonck\/micropython,oopy\/micropython,jmarcelino\/pycom-micropython,praemdonck\/micropython,selste\/micropython,Peetz0r\/micropython-esp32,hiway\/micropython,cwyark\/micropython,Timmenem\/micropython,redbear\/micropython,HenrikSolver\/micropython,drrk\/micropython,kerneltask\/micropython,tuc-osg\/micropython,PappaPeppar\/micropython,bvernoux\/micropython,tobbad\/micropython,adafruit\/circuitpython,AriZuu\/micropython,tobbad\/micropython,HenrikSolver\/micropython,swegener\/micropython,jmarcelino\/pycom-micropython,blazewicz\/micropython,TDAbboud\/micropython,ryannathans\/micropython,lowRISC\/micropython,micropython\/micropython-esp32,pramasoul\/micropython,infinnovation\/micropython,matthewelse\/micropython,ganshun666\/micropython,mhoffma\/micropython,dxxb\/micropython,chrisdearman\/micropython,chrisdearman\/micropython,puuu\/micropython,MrSurly\/micropython-esp32,AriZuu\/micropython,Peetz0r\/micropython-esp32,AriZuu\/micropython,dmazzella\/micropython,tralamazza\/micropython,pfalcon\/micropython,tuc-osg\/micropython,swegener\/micropython,mpalomer\/micropython,dinau\/micropython,deshipu\/micropython,MrSurly\/micropython-esp32","old_file":"esp8266\/esp8266.ld","new_file":"esp8266\/esp8266.ld","new_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n        *py\/*.o*(.literal* .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *pyexec.o(.literal*, .text*)\n        *readline.o(.literal*, .text*)\n        *pybstdio.o(.literal*, .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *py\/*.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *py\/*.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *py\/*.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.sdk.version)\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","old_contents":"\/* GNU linker script for ESP8266 *\/\n\nMEMORY\n{\n    dport0_0_seg : org = 0x3ff00000, len = 0x10\n    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000\n    iram1_0_seg :  org = 0x40100000, len = 0x8000\n    irom0_0_seg :  org = 0x40210000, len = 0x5A000\n}\n\n\/* define the top of RAM *\/\n_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);\n\nPHDRS\n{\n    dport0_0_phdr PT_LOAD;\n    dram0_0_phdr PT_LOAD;\n    dram0_0_bss_phdr PT_LOAD;\n    iram1_0_phdr PT_LOAD;\n    irom0_0_phdr PT_LOAD;\n}\n\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\n\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n    .dport0.rodata : ALIGN(4)\n    {\n        _dport0_rodata_start = ABSOLUTE(.);\n        *(.dport0.rodata)\n        *(.dport.rodata)\n        _dport0_rodata_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.literal : ALIGN(4)\n    {\n        _dport0_literal_start = ABSOLUTE(.);\n        *(.dport0.literal)\n        *(.dport.literal)\n        _dport0_literal_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .dport0.data : ALIGN(4)\n    {\n        _dport0_data_start = ABSOLUTE(.);\n        *(.dport0.data)\n        *(.dport.data)\n        _dport0_data_end = ABSOLUTE(.);\n    } >dport0_0_seg :dport0_0_phdr\n\n    .irom0.text : ALIGN(4)\n    {\n        _irom0_text_start = ABSOLUTE(.);\n        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)\n\n        \/* we put some specific text in this section *\/\n        *py\/*.o*(.literal* .text*)\n        *lib\/libm\/*.o*(.literal*, .text*)\n        *pyexec.o(.literal*, .text*)\n        *readline.o(.literal*, .text*)\n        *pybstdio.o(.literal*, .text*)\n        *gccollect.o(.literal* .text*)\n        *gchelper.o(.literal* .text*)\n        *modpyb.o(.literal*, .text*)\n        *modpybpin.o(.literal*, .text*)\n        *modpybrtc.o(.literal*, .text*)\n        *modesp.o(.literal* .text*)\n        *modnetwork.o(.literal* .text*)\n        *moduos.o(.literal* .text*)\n        *modutime.o(.literal* .text*)\n\n        \/* we put as much rodata as possible in this section *\/\n        \/* note that only rodata accessed as a machine word is allowed here *\/\n        *py\/qstr.o(.rodata.const_pool)\n        *py\/*.o(.rodata.mp_type_*) \/* catches type: mp_obj_type_t *\/\n        *py\/*.o(.rodata.*_locals_dict*) \/* catches types: mp_obj_dict_t, mp_map_elem_t *\/\n        *py\/*.o(.rodata.mp_module_*) \/* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t *\/\n\n        _irom0_text_end = ABSOLUTE(.);\n    } >irom0_0_seg :irom0_0_phdr\n\n    .text : ALIGN(4)\n    {\n        _stext = .;\n        _text_start = ABSOLUTE(.);\n        *(.UserEnter.text)\n        . = ALIGN(16);\n        *(.DebugExceptionVector.text)\n        . = ALIGN(16);\n        *(.NMIExceptionVector.text)\n        . = ALIGN(16);\n        *(.KernelExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.UserExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN(16);\n        *(.DoubleExceptionVector.text)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        LONG(0)\n        . = ALIGN (16);\n        *(.entry.text)\n        *(.init.literal)\n        *(.init)\n        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n        *(.fini.literal)\n        *(.fini)\n        *(.gnu.version)\n        _text_end = ABSOLUTE(.);\n        _etext = .;\n    } >iram1_0_seg :iram1_0_phdr\n\n    .lit4 : ALIGN(4)\n    {\n        _lit4_start = ABSOLUTE(.);\n        *(*.lit4)\n        *(.lit4.*)\n        *(.gnu.linkonce.lit4.*)\n        _lit4_end = ABSOLUTE(.);\n    } >iram1_0_seg :iram1_0_phdr\n\n    .data : ALIGN(4)\n    {\n        _data_start = ABSOLUTE(.);\n        *(.data)\n        *(.data.*)\n        *(.gnu.linkonce.d.*)\n        *(.data1)\n        *(.sdata)\n        *(.sdata.*)\n        *(.gnu.linkonce.s.*)\n        *(.sdata2)\n        *(.sdata2.*)\n        *(.gnu.linkonce.s2.*)\n        *(.jcr)\n        _data_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .rodata : ALIGN(4)\n    {\n        _rodata_start = ABSOLUTE(.);\n        *(.rodata)\n        *(.rodata.*)\n        *(.gnu.linkonce.r.*)\n        *(.rodata1)\n        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n        *(.xt_except_table)\n        *(.gcc_except_table)\n        *(.gnu.linkonce.e.*)\n        *(.gnu.version_r)\n        *(.eh_frame)\n        \/*  C++ constructor and destructor tables, properly ordered:  *\/\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*(.ctors))\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*(.dtors))\n        \/*  C++ exception handlers table:  *\/\n        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n        *(.xt_except_desc)\n        *(.gnu.linkonce.h.*)\n        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n        *(.xt_except_desc_end)\n        *(.dynamic)\n        *(.gnu.version_d)\n        . = ALIGN(4);        \/* this table MUST be 4-byte aligned *\/\n        _bss_table_start = ABSOLUTE(.);\n        LONG(_bss_start)\n        LONG(_bss_end)\n        _bss_table_end = ABSOLUTE(.);\n        _rodata_end = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_phdr\n\n    .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n    {\n        . = ALIGN (8);\n        _bss_start = ABSOLUTE(.);\n        *(.dynsbss)\n        *(.sbss)\n        *(.sbss.*)\n        *(.gnu.linkonce.sb.*)\n        *(.scommon)\n        *(.sbss2)\n        *(.sbss2.*)\n        *(.gnu.linkonce.sb2.*)\n        *(.dynbss)\n        *(.bss)\n        *(.bss.*)\n        *(.gnu.linkonce.b.*)\n        *(COMMON)\n        . = ALIGN (8);\n        _bss_end = ABSOLUTE(.);\n        _heap_start = ABSOLUTE(.);\n    } >dram0_0_seg :dram0_0_bss_phdr\n}\n\n\/* get ROM code address *\/\nINCLUDE \"eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"393e340f9a65e70514134fbd7b8c7aadfc0f3a87","subject":"Completely rewrite linker script","message":"Completely rewrite linker script\n","repos":"nicholatian\/saturn,nicholatian\/saturn,nicholatian\/saturn","old_file":"util\/gba.ld","new_file":"util\/gba.ld","new_contents":"\nOUTPUT_ARCH(arm)\n\nENTRY(_sat__start)\n\nMEMORY\n{\n    ewram   : ORIGIN = 0x2000000, LENGTH = 256k\n    iwram   : ORIGIN = 0x3000000, LENGTH = 32k\n    rom     : ORIGIN = 0x8000000, LENGTH = 32M\n    sram    : ORIGIN = 0xE000000, LENGTH = 64k\n}\n\n_sat___text_start  = ORIGIN(rom);\n_sat___ewram_start = ORIGIN(ewram);\n_sat___iwram_start = ORIGIN(iwram);\n_sat___sram_start  = ORIGIN(sram);\n\nSECTIONS\n{\n    . = _sat___text_start;\n    _sat___init_start = .;\n    \n    .init :\n    {\n        *(.init);\n        *(.fini);\n        . = ALIGN(4);\n    } >rom\n    \n    _sat___init_end  = .;\n    _sat___init_size = SIZEOF(.init);\n    \n    .text :\n    {\n        *(.text);\n        *(.ctors);\n        *(.dtors);\n        *(.rodata);\n        . = ALIGN(4);\n    } >rom\n    \n    _sat___text_end  = .;\n    _sat___text_size = SIZEOF(.text);\n    \n    . = _sat___iwram_start;\n    \n    \/* Load code from ROM into IWRAM *\/\n    .iwram :\n    {\n        _sat___iwram_load = LOADADDR(.iwram);\n        \n        *(.iwram);\n        . = ALIGN(4);\n    } >iwram AT >rom\n    \n    _sat___iwram_end  = .;\n    \/* This is NOT the size of the IWRAM memory region! *\/\n    _sat___iwram_size = SIZEOF(.iwram);\n    _sat___bss_start  = .;\n    \n    \/* Earmark memory for uninitialised variables *\/\n    .bss :\n    {\n        *(.bss);\n        . = ALIGN(4);\n        \n        _sat___end = .;\n    } >iwram\n    \n    _sat___bss_end         = .;\n    _sat___bss_size        = SIZEOF(.bss);\n    _sat___iwram_total     = _sat___iwram_size + _sat___bss_size;\n    _sat___iwram_total_end = ORIGIN(iwram) + _sat___iwram_total;\n    \n    . = _sat___sram_start;\n    \n    .sram :\n    {\n        *(.sram);\n        \n        . = ALIGN(4);\n        _sat___sram_end = .;\n    } >sram\n    \n    _sat___sram_size = SIZEOF(.sram);\n}\n","old_contents":"\nOUTPUT_ARCH(arm)\n\nENTRY(__start)\n\nMEMORY\n{\n    ewram   : ORIGIN = 0x2000000, LENGTH = 256k\n    iwram   : ORIGIN = 0x3000000, LENGTH = 32k\n    io      : ORIGIN = 0x4000000, LENGTH = 1k - 1\n    pal     : ORIGIN = 0x5000000, LENGTH = 1k\n    vram    : ORIGIN = 0x6000000, LENGTH = 96k\n    oam     : ORIGIN = 0x7000000, LENGTH = 1k\n    rom     : ORIGIN = 0x8000000, LENGTH = 32M\n}\n\nSECTIONS\n{\n    .text :\n    {\n        FILL (0xABCD)\n        \n        __text_start = . ;\n        *(.init)\n        *(.text)\n        *(.ctors)\n        *(.dtors)\n        *(.rodata)\n        *(.fini)\n        *(.data)\n        *(COMMON)\n        __text_end  = . ;\n        \n        __bss_start__ = . ;\n        *(.bss)\n        __bss_end__ = . ;\n        _end = __bss_end__ ;\n        __end__ = __bss_end__ ;\n    } >rom = 0xFF\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b0099e0e652f59c8c07d07cada704f8d966fab33","subject":"Cleaned up, removed higher half mapping","message":"Cleaned up, removed higher half mapping\n","repos":"stelfer\/nubbin,stelfer\/nubbin","old_file":"kernel\/asm\/kernel.elf_x86_64.ld","new_file":"kernel\/asm\/kernel.elf_x86_64.ld","new_contents":"\/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt *\/\nENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.setup :\n\t{\n\t\t*(.setup)\n\t}\n\n\t.text ALIGN (4K):\n\t{\n\t\t*(.text)\n\t}\n\n\t.data ALIGN (4K) :\n\t{\n\t\t*(.data)\n\t\t*(.rodata*)\n\t}\n\n\t.bss ALIGN (4K) :\n\t{\n\t\t*(COMMON*)\n\t\t*(.bss*)\n\t}\n}\n","old_contents":"\n\/* OUTPUT_FORMAT(\"elf32-i386\") *\/\nENTRY(_start)\n\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.multiboot :\n\t{\n\t\t*(.multiboot)\n\t}\n\n\t.setup :\n\t{\n\t\t*(.setup)\n\t}\n\n\t. += 0xC0000000;\n\n\t.text : AT(ADDR(.text) - 0xC0000000)\n\t{\n\t\t*(.text)\n\t}\n\n\t.data ALIGN (4K) : AT(ADDR(.data) - 0xC0000000)\n\t{\n\t\t*(.data)\n\t\t*(.rodata*)\n\t}\n\n\t.bss ALIGN (4K) : AT(ADDR(.bss) - 0xC0000000)\n\t{\n\t\t*(COMMON*)\n\t\t*(.bss*)\n\t}\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"0c9831edd73dcad803fd6c04d950b37c67b4bc5e","subject":"update copyright","message":"update copyright\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX63T\/R5F563T6.ld","new_file":"RX63T\/R5F563T6.ld","new_contents":"\/*!\t@file\n\t@brief\tRX63T R5F563T6 \u30ea\u30f3\u30ab\u30fc\u30fb\u30b9\u30af\u30ea\u30d7\u30c8\n    @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\t@copyright\tCopyright (C) 2016, 2017 Kunihito Hiramatsu @n\n\t\t\t\tReleased under the MIT license @n\n\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x00001F00 \/* 8k - 256(USP + SP) *\/\n\tUSTACK (w) : ORIGIN = 0x00001FC0, LENGTH = 4 \/* ustack 192 bytes *\/\n\tISTACK (w) : ORIGIN = 0x00002000, LENGTH = 4 \/* istack 64 bytes  *\/\n\tROM (w)    : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FFD0 \/* 64k - 0x30(.fvectors) *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .istack (ORIGIN (ISTACK)) :\n  {\n    PROVIDE (__istack = .);\n    *(.istack)\n  }\n\n  .ustack (ORIGIN (USTACK)) :\n  {\n    PROVIDE (__ustack = .);\n    *(.ustack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*\n\nCopyright (c) 2005,2008,2009 Red Hat Incorporated.\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without \nmodification, are permitted provided that the following conditions are met: \n\n    Redistributions of source code must retain the above copyright \n    notice, this list of conditions and the following disclaimer.\n\n    Redistributions in binary form must reproduce the above copyright\n    notice, this list of conditions and the following disclaimer in the\n    documentation and\/or other materials provided with the distribution.\n\n    The name of Red Hat Incorporated may not be used to endorse \n    or promote products derived from this software without specific \n    prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \n\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX600 chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x00001F00 \/* 8k - 256(USP + SP) *\/\n\tUSTACK (w) : ORIGIN = 0x00001FC0, LENGTH = 4 \/* ustack 192 bytes *\/\n\tISTACK (w) : ORIGIN = 0x00002000, LENGTH = 4 \/* istack 64 bytes  *\/\n\tROM (w)    : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FFD0 \/* 64k - 0x30(.fvectors) *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .istack (ORIGIN (ISTACK)) :\n  {\n    PROVIDE (__istack = .);\n    *(.istack)\n  }\n\n  .ustack (ORIGIN (USTACK)) :\n  {\n    PROVIDE (__ustack = .);\n    *(.ustack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c6fc0a134ca5ba76c16f95b2ef65151e14a472dd","subject":"nrf51\/boards: Increasing heap and stack size in the pca10028 board.","message":"nrf51\/boards: Increasing heap and stack size in the pca10028 board.\n","repos":"tralamazza\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,tralamazza\/micropython,tralamazza\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython","old_file":"nrf5\/boards\/nrf51822_ac.ld","new_file":"nrf5\/boards\/nrf51822_ac.ld","new_contents":"\/*\n    GNU linker script for NRF52 blank w\/ no SoftDevice\n*\/\n\/* Specify the memory areas *\/\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x000400 \/* sector 0, 1 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00000400, LENGTH = 0x03F000 \/* 255 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x008000 \/* 32 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 4K;\n_minimum_heap_size = 24K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20006000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52 blank w\/ no SoftDevice\n*\/\n\/* Specify the memory areas *\/\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lnosys)\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 0x040000 \/* entire flash, 256 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x00000000, LENGTH = 0x000400 \/* sector 0, 1 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x00000400, LENGTH = 0x03F000 \/* 255 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 0x008000 \/* 32 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 2K;\n_minimum_heap_size = 20K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20005000; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b44cfc4ac3fb73036dbd623ae1a5e95c31a06c00","subject":"Be more explicit on how to treat sections","message":"Be more explicit on how to treat sections\n","repos":"smaeul\/quarto","old_file":"scripts\/kernel.ld","new_file":"scripts\/kernel.ld","new_contents":"\/*\n * scripts\/kernel.ld - Main quarto linker script\n *\n * Copyright 2012-2013 Samuel Holland <samuel@sholland.net>\n *\/\n\nOUTPUT_FORMAT(elf32-x86-64)\nOUTPUT_ARCH(i386:x86-64)\n\nENTRY (__entry)\n\nHM_OFFSET = 0xFFFFFF8000000000;\n\nSECTIONS\n{\n    . = 0x00000000001000A0;\t\/* Reserve enough space for ELF header *\/\n\n    __start = .;\n\n    .loader : ALIGN(0x10)\n    {\n\t__loader_start = .;\n\t*(.loader)\t\t\/* BIOS and multiboot loader code *\/\n\t*(.loaderdata)\t\t\/* GDT, its pointer struct, and friends *\/\n\t__loader_end = .;\n    }\n\n    . += HM_OFFSET;\t\t\/* Move to the top of virtual memory *\/\n\n    .text : AT(ADDR(.text) - HM_OFFSET)\n    {\n\t__text_start = .;\n\t*(.init)\t\t\/* The springboard we jump to in high RAM *\/\n\t*(.text*)\t\t\/* Normal 64-Bit Code *\/\n\t__text_end = .;\n\t__multiboot_text_end = . - HM_OFFSET;\n    }\n\n    .data : AT(ADDR(.data) - HM_OFFSET)\n    {\n\t__data_start = .;\n\t*(.data*)\t\t\/* Global Variables *\/\n\t*(.rodata*)\t\t\/* String Constants *\/\n\t__data_end = .;\n\t__multiboot_data_end = . - HM_OFFSET;\n    }\n\n    .bss : AT(ADDR(.bss) - HM_OFFSET)\n    {\n\t__bss_start = .;\n\t__multiboot_bss_start = . - HM_OFFSET; \/* For 32-bit relocations *\/\n\t*(.loaderbss)\t\t\/* Temporary init data (multiboot struct) *\/\n\t*(.bss*)\t\t\/* Normal Reserved Memory *\/\n\t*(COMMON)\t\t\/* Other Uninitialized Data *\/\n\t__bss_end = .;\n\t__multiboot_bss_end = . - HM_OFFSET;\n    }\n\n    __end = .;\n\n    \/DISCARD\/ :\n    {\n\t*(.comment)\n\t*(.eh_frame)\n\t*(.note*)\n    }\n}\n","old_contents":"\/*\n * scripts\/kernel.ld - Main quarto linker script\n *\n * Copyright 2012-2013 Samuel Holland <samuel@sholland.net>\n *\/\n\nOUTPUT_FORMAT(elf32-x86-64)\nOUTPUT_ARCH(i386:x86-64)\n\nENTRY (__entry)\n\nHM_OFFSET = 0xFFFFFF8000000000;\n\nSECTIONS\n{\n    . = 0x00000000001000A0;\t\/* Reserve enough space for ELF header *\/\n\n    __start = .;\n\n    .loader : ALIGN(0x10)\n    {\n\t__loader_start = .;\n\t*(.loader)\t\t\/* BIOS and multiboot loader code *\/\n\t*(.loaderdata)\t\t\/* GDT, its pointer struct, and friends *\/\n\t__loader_end = .;\n    }\n\n    . += HM_OFFSET;\t\t\/* Move to the top of virtual memory *\/\n\n    .text : AT(ADDR(.text) - HM_OFFSET)\n    {\n\t__text_start = .;\n\t*(.init)\t\t\/* The springboard we jump to in high RAM *\/\n\t*(.text)\t\t\/* Normal 64-Bit Code *\/\n\t__text_end = .;\n\t__multiboot_text_end = . - HM_OFFSET;\n    }\n\n    .data : AT(ADDR(.data) - HM_OFFSET)\n    {\n\t__data_start = .;\n\t*(.data)\t\t\/* Global Variables *\/\n\t*(.rodata*)\t\t\/* String Constants *\/\n\t__data_end = .;\n\t__multiboot_data_end = . - HM_OFFSET;\n    }\n\n    .bss : AT(ADDR(.bss) - HM_OFFSET)\n    {\n\t__bss_start = .;\n\t__multiboot_bss_start = . - HM_OFFSET; \/* For 32-bit relocations *\/\n\t*(.loaderbss)\t\t\/* Temporary init data (multiboot struct) *\/\n\t*(.bss)\t\t\t\/* Normal Reserved Memory *\/\n\t*(COMMON)\t\t\/* Other Uninitialized Data *\/\n\t__bss_end = .;\n\t__multiboot_bss_end = . - HM_OFFSET;\n    }\n\n    __end = .;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"f5ac11ae32e37bc69f2e33fc3e3adcbe3665fa07","subject":"arch: riscv: linker: add support for userspace","message":"arch: riscv: linker: add support for userspace\n\n- Move kobject list after .bss\n  The previous order shift kernel object address defined in prebuild\n  file (which is use as reference in running time). So it was impossible\n  for zephyr to check if a kernel object address was granted because\n  address changed during build.\n\n- Add support for memory shared.\n\n- Move sdata2 section in ROM because it contains constants.\n\nSigned-off-by: Nicolas Royer <cdb96cf79f201960f391fbb8a3ea2297421a62dd@baylibre.com>\n","repos":"nashif\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n#include <linker\/kobject-text.ld>\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n\t_image_rodata_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end - _image_rom_start);\n\t_image_rom_end = .;\n\t_image_rom_size = _image_rom_end - _image_rom_start;\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\t__data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n    __data_ram_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    _image_rom_start = .;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t_image_text_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n\t\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rom_end = .;\n    __data_rom_start = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t _image_ram_start = .;\n\t\t __data_ram_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n    __data_ram_end = .;\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n#include <linker\/cplusplus-ram.ld>\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"23824c9846f21f5a37bbf89b0adc85782ce7dc10","subject":"added kernelStart variable to linker script","message":"added kernelStart variable to linker script\n","repos":"fasterthanlime\/oos,fasterthanlime\/oos,tsion\/oos,tsion\/oos","old_file":"Src\/Kernel\/Linker.ld","new_file":"Src\/Kernel\/Linker.ld","new_contents":"ENTRY(bootEntry)\n\nSECTIONS {\n    \/* 0x100000 = 1 MB. The kernel must be above 1 MB in order for GRUB to be able to load it. *\/\n    . = 0x100000;\n    kernelStart = .;\n\n    .text ALIGN (0x1000) : {\n        *(.text)\n    }\n\n    .rodata ALIGN (0x1000) : {\n        *(.rodata)\n    }\n\n    .data ALIGN (0x1000) : {\n        *(.data)\n    }\n\n    .bss ALIGN (0x1000) : {\n        *(COMMON)\n        *(.bss)\n    }\n\n    kernelEnd = .;\n}\n\n","old_contents":"ENTRY(bootEntry)\n\nSECTIONS {\n    \/* 0x100000 = 1 MB. The kernel must be above 1 MB in order for GRUB to be able to load it. *\/\n    . = 0x100000;\n\n    .text ALIGN (0x1000) : {\n        *(.text)\n    }\n\n    .rodata ALIGN (0x1000) : {\n        *(.rodata)\n    }\n\n    .data ALIGN (0x1000) : {\n        *(.data)\n    }\n\n    .bss ALIGN (0x1000) : {\n        *(COMMON)\n        *(.bss)\n    }\n\n    kernelEnd = .;\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b1e3967b16087c4e376e44f346b07f6887daa07f","subject":"ArmVirtPkg: use global section alignment in custom linker script","message":"ArmVirtPkg: use global section alignment in custom linker script\n\nThe ArmVirtPrePiUniCoreRelocatable module comes with its own GNU\nlinker script to create a PIE executable that can relocate itself\nat runtime. In order to be able to build this module using CLANG,\nwe need to adhere to the section alignment passed via to the linker\nusing -z commmon-page-size, so add this to the linker script.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nAcked-by: Laszlo Ersek <lersek@redhat.com>\n\ngit-svn-id: 3158a46dfd52e07d1fda3e32e1ab2e353a00b20f@18203 6f19259b-4bc3-4df7-8a09-765794883524\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"ArmVirtPkg\/PrePi\/Scripts\/PrePi-PIE.lds","new_file":"ArmVirtPkg\/PrePi\/Scripts\/PrePi-PIE.lds","new_contents":"#\/** @file\r\n#\r\n#  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n#\r\n#  This program and the accompanying materials\r\n#  are licensed and made available under the terms and conditions of the BSD License\r\n#  which accompanies this distribution.  The full text of the license may be found at\r\n#  http:\/\/opensource.org\/licenses\/bsd-license.php\r\n#\r\n#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n#\r\n#**\/\r\n\r\nSECTIONS\r\n{\r\n  .text 0x0 : ALIGN(CONSTANT(COMMONPAGESIZE)) {\r\n    PROVIDE(__reloc_base = .);\r\n\r\n    *(.text .text*)\r\n    *(.got .got*)\r\n    *(.rodata .rodata*)\r\n    *(.data .data*)\r\n    *(.bss .bss*)\r\n\r\n    . = ALIGN(0x20);\r\n    PROVIDE(__reloc_start = .);\r\n    *(.rela .rela*)\r\n    PROVIDE(__reloc_end = .);\r\n  }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynamic)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.hash)\r\n    *(.comment)\r\n  }\r\n}\r\n","old_contents":"#\/** @file\r\n#\r\n#  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>\r\n#\r\n#  This program and the accompanying materials\r\n#  are licensed and made available under the terms and conditions of the BSD License\r\n#  which accompanies this distribution.  The full text of the license may be found at\r\n#  http:\/\/opensource.org\/licenses\/bsd-license.php\r\n#\r\n#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN \"AS IS\" BASIS,\r\n#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r\n#\r\n#**\/\r\n\r\nSECTIONS\r\n{\r\n  .text 0x0 : {\r\n    PROVIDE(__reloc_base = .);\r\n\r\n    *(.text .text*)\r\n    *(.got .got*)\r\n    *(.rodata .rodata*)\r\n    *(.data .data*)\r\n\r\n    . = ALIGN(0x20);\r\n    PROVIDE(__reloc_start = .);\r\n    *(.rela .rela*)\r\n    PROVIDE(__reloc_end = .);\r\n  }\r\n  .bss ALIGN(0x20) : { *(.bss .bss*) }\r\n\r\n  \/DISCARD\/ : {\r\n    *(.note.GNU-stack)\r\n    *(.gnu_debuglink)\r\n    *(.interp)\r\n    *(.dynamic)\r\n    *(.dynsym)\r\n    *(.dynstr)\r\n    *(.hash)\r\n    *(.comment)\r\n  }\r\n}\r\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"c63c4ccc625a596606e144a2f8bec33a67b08fae","subject":"Replaces the forked memory map with a symlink.","message":"Replaces the forked memory map with a symlink.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/ti-ek-tm4c123gxl-z-dev-board\/memory_map.ld","new_file":"boards\/ti-ek-tm4c123gxl-z-dev-board\/memory_map.ld","new_contents":"","old_contents":"MEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 240K\n  EEPROMEMU (r): ORIGIN = 0x3C000, LENGTH = 8K\n  BOOTLOADER (rx) : ORIGIN = 0x0003E000, LENGTH = 8K\n  RAM  (rwx) : ORIGIN = 0x20000000, LENGTH = 32K\n}\n\n__flash_start = ORIGIN(FLASH);\n__flash_end = ORIGIN(FLASH) + LENGTH(FLASH);\n__eeprom_start = ORIGIN(EEPROMEMU);\n__eeprom_end = ORIGIN(EEPROMEMU) + LENGTH(EEPROMEMU);\n__bootloader_start = ORIGIN(BOOTLOADER);\n__bootloader_end = ORIGIN(BOOTLOADER) + LENGTH(BOOTLOADER);\n__app_header_offset = 0x270;\n__bootloader_magic_ptr = ORIGIN(RAM);\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"8f10f22b1fe51e6aee041fbd9722886055cac532","subject":"cpu\/cortexm: ldscripts: bkup-ram -> bkup_ram","message":"cpu\/cortexm: ldscripts: bkup-ram -> bkup_ram\n\nFixes this error with binutils 2.37:\n\n```\n\/usr\/lib\/gcc\/arm-none-eabi\/11.2.0\/..\/..\/..\/..\/arm-none-eabi\/bin\/ld:cortexm_base.ld:217: warning: memory region `bkup' not declared\n\/usr\/lib\/gcc\/arm-none-eabi\/11.2.0\/..\/..\/..\/..\/arm-none-eabi\/bin\/ld:cortexm_base.ld:217: syntax error\n```\n","repos":"ant9000\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,ant9000\/RIOT,miri64\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,authmillenon\/RIOT,ant9000\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,miri64\/RIOT,kYc0o\/RIOT,miri64\/RIOT,kaspar030\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* This is only used by gdb to understand where to start *\/\nENTRY(reset_handler_default)\n\n_backup_ram_start_addr = DEFINED( _backup_ram_start_addr ) ? _backup_ram_start_addr : 0x0 ;\n_backup_ram_len = DEFINED( _backup_ram_len ) ? _backup_ram_len : 0x0 ;\n\n\/* not all Cortex-M platforms use cortexm.ld yet *\/\nMEMORY\n{\n    bkup_ram (w!rx) : ORIGIN = _backup_ram_start_addr, LENGTH = _backup_ram_len\n}\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _isr_vectors = DEFINED(_isr_vectors) ? _isr_vectors : . ;\n        KEEP(*(SORT(.vectors*)))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        KEEP (*(SORT(.roxfa.*)))\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/*\n     * TLS relocations are offsets relative to the address\n     * of the first TLS symbol. That means we just need to\n     * allocate them all together so that the TLS region\n     * is compact when allocated for each thread.\n     *\/\n\n    \/*\n     * TLS initialization data is loaded into ROM so that\n     * each thread can get its values initialized from there\n     * at startup\n     *\/\n    .tdata :\n    {\n         __tdata_start = .;\n        *(.tdata .tdata.* .gnu.linkonce.td.*)\n        __tdata_end = .;\n    } > rom\n    __tdata_source = LOADADDR(.tdata);\n    __tdata_size = SIZEOF(.tdata);\n\n    \/*\n     * TLS zeroed data is relocated as if it immediately followed\n     * the tdata values. However, the linker 'magically' erases the\n     * memory allocation so that no ROM is consumed by this\n     * section\n     *\/\n    .tbss :\n    {\n        *(.tbss .tbss.* .gnu.linkonce.tb.*)\n        *(.tcommon)\n        __tbss_end = .;\n    } > rom\n    __tls_size = __tbss_end - __tdata_start;\n    __tbss_size = __tls_size - __tdata_size;\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        KEEP (*(.puf))\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate :\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        KEEP (*(SORT(.xfa.*)))\n        KEEP (*(.openocd .openocd.*))\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram AT> rom\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        *(.noinit)\n        . = ALIGN(4);\n        __noinit_end = .;\n    }  > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n\n    _sbackup_data_load = LOADADDR(.backup.data);\n    .backup.data :  ALIGN(4) {\n        _sbackup_data = .;\n        *(.backup.data)\n        _ebackup_data = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > bkup_ram AT> rom\n\n    .backup.bss (NOLOAD) : ALIGN(4) {\n        _sbackup_bss = .;\n        *(.backup.bss)\n        _ebackup_bss = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > bkup_ram\n\n    .heap3 (NOLOAD) : ALIGN(4) {\n        _sheap1 = . ;\n        _eheap1 = ORIGIN(bkup_ram) + LENGTH(bkup_ram);\n    } > bkup_ram\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* This is only used by gdb to understand where to start *\/\nENTRY(reset_handler_default)\n\n_backup_ram_start_addr = DEFINED( _backup_ram_start_addr ) ? _backup_ram_start_addr : 0x0 ;\n_backup_ram_len = DEFINED( _backup_ram_len ) ? _backup_ram_len : 0x0 ;\n\n\/* not all Cortex-M platforms use cortexm.ld yet *\/\nMEMORY\n{\n    bkup-ram (w!rx) : ORIGIN = _backup_ram_start_addr, LENGTH = _backup_ram_len\n}\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _isr_vectors = DEFINED(_isr_vectors) ? _isr_vectors : . ;\n        KEEP(*(SORT(.vectors*)))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        KEEP (*(SORT(.roxfa.*)))\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/*\n     * TLS relocations are offsets relative to the address\n     * of the first TLS symbol. That means we just need to\n     * allocate them all together so that the TLS region\n     * is compact when allocated for each thread.\n     *\/\n\n    \/*\n     * TLS initialization data is loaded into ROM so that\n     * each thread can get its values initialized from there\n     * at startup\n     *\/\n    .tdata :\n    {\n         __tdata_start = .;\n        *(.tdata .tdata.* .gnu.linkonce.td.*)\n        __tdata_end = .;\n    } > rom\n    __tdata_source = LOADADDR(.tdata);\n    __tdata_size = SIZEOF(.tdata);\n\n    \/*\n     * TLS zeroed data is relocated as if it immediately followed\n     * the tdata values. However, the linker 'magically' erases the\n     * memory allocation so that no ROM is consumed by this\n     * section\n     *\/\n    .tbss :\n    {\n        *(.tbss .tbss.* .gnu.linkonce.tb.*)\n        *(.tcommon)\n        __tbss_end = .;\n    } > rom\n    __tls_size = __tbss_end - __tdata_start;\n    __tbss_size = __tls_size - __tdata_size;\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        KEEP (*(.puf))\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate :\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        KEEP (*(SORT(.xfa.*)))\n        KEEP (*(.openocd .openocd.*))\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram AT> rom\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        *(.noinit)\n        . = ALIGN(4);\n        __noinit_end = .;\n    }  > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n\n    _sbackup_data_load = LOADADDR(.backup.data);\n    .backup.data :  ALIGN(4) {\n        _sbackup_data = .;\n        *(.backup.data)\n        _ebackup_data = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > bkup-ram AT> rom\n\n    .backup.bss (NOLOAD) : ALIGN(4) {\n        _sbackup_bss = .;\n        *(.backup.bss)\n        _ebackup_bss = .;\n        \/* Round size so that we can use 4 byte copy in init *\/\n        . = ALIGN(4);\n    } > bkup-ram\n\n    .heap3 (NOLOAD) : ALIGN(4) {\n        _sheap1 = . ;\n        _eheap1 = ORIGIN(bkup-ram) + LENGTH(bkup-ram);\n    } > bkup-ram\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"02d1fd9ad78bbbe1d12eb59f747d8d16d4f354d7","subject":"linker: remove unused usb_data data section in RAM","message":"linker: remove unused usb_data data section in RAM\n\nRemove unused usb_data data section in RAM which is\nreplaced by iterable section usb_cfg_data.\n\nSigned-off-by: Johann Fischer <64a5f06fca6b2d93d742efe564789153170f6198@nordicsemi.no>\n","repos":"zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr","old_file":"include\/linker\/common-ram.ld","new_file":"include\/linker\/common-ram.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#if defined(CONFIG_NETWORKING)\n#ifndef NETWORK_RAM_SECTIONS\n#define NETWORK_RAM_SECTIONS \\\n\tITERABLE_SECTION_RAM(net_if, 4) \\\n\tITERABLE_SECTION_RAM(net_if_dev, 4) \\\n\tITERABLE_SECTION_RAM(net_l2, 4) \\\n\tITERABLE_SECTION_RAM(eth_bridge, 4)\n#endif\n#endif \/* NETWORKING *\/\n\n#if defined(CONFIG_BT_MESH)\n\tITERABLE_SECTION_RAM(bt_mesh_ext_adv, 4)\n#endif\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_DATA_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_SYMS)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n        SECTION_DATA_PROLOGUE(device_states,,)\n        {\n\t\t\/* Device states used by the device objects. *\/\n                __device_states_start = .;\n\t\tKEEP(*(\".z_devstate\"));\n\t\tKEEP(*(\".z_devstate.*\"));\n                __device_states_end = .;\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if CONFIG_PM_DEVICE\n\tSECTION_DATA_PROLOGUE(pm_device_slots, (NOLOAD),)\n\t{\n\t\t__pm_device_slots_start = .;\n\t\tKEEP(*(\".z_pm_device_slots\"));\n\t\t__pm_device_slots_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n\tSECTION_DATA_PROLOGUE(initshell,,)\n\t{\n\t\t\/* link in shell initialization objects for all modules that\n\t\t * use shell and their shell commands are automatically\n\t\t * initialized by the kernel.\n\t\t *\/\n\t\t__shell_module_start = .;\n\t\tKEEP(*(\".shell_module_*\"));\n\t\t__shell_module_end = .;\n\t\t__shell_cmd_start = .;\n\t\tKEEP(*(\".shell_cmd_*\"));\n\t\t__shell_cmd_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_dynamic_sections,,)\n\t{\n\t\t__log_dynamic_start = .;\n\t\tKEEP(*(SORT(.log_dynamic_*)));\n\t\t__log_dynamic_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_timer, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_mem_slab, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_mem_pool, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_heap, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_mutex, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_stack, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_msgq, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_mbox, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_pipe, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_sem, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_event, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_queue, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_condvar, 4)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area,,SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NETWORKING)\n\tNETWORK_RAM_SECTIONS\n#endif \/* NETWORKING *\/\n\n#if defined(CONFIG_UART_MUX)\n\tSECTION_DATA_PROLOGUE(uart_mux,,SUBALIGN(4))\n\t{\n\t\t__uart_mux_start = .;\n\t\t*(\".uart_mux.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".uart_mux.*\")))\n\t\t__uart_mux_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor,,SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tITERABLE_SECTION_RAM(usb_cfg_data, 4)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#if defined(CONFIG_USB_DEVICE_BOS)\n\tSECTION_DATA_PROLOGUE(usb_bos_desc,,SUBALIGN(1))\n\t{\n\t\t__usb_bos_desc_start = .;\n\t\t*(\".usb.bos_desc\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.bos_desc*\")))\n\t\t__usb_bos_desc_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_BOS *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n\n#if defined(CONFIG_ZTEST)\n\tITERABLE_SECTION_RAM(ztest_suite_node, 4)\n#endif \/* CONFIG_ZTEST *\/\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\n#if defined(CONFIG_NETWORKING)\n#ifndef NETWORK_RAM_SECTIONS\n#define NETWORK_RAM_SECTIONS \\\n\tITERABLE_SECTION_RAM(net_if, 4) \\\n\tITERABLE_SECTION_RAM(net_if_dev, 4) \\\n\tITERABLE_SECTION_RAM(net_l2, 4) \\\n\tITERABLE_SECTION_RAM(eth_bridge, 4)\n#endif\n#endif \/* NETWORKING *\/\n\n#if defined(CONFIG_BT_MESH)\n\tITERABLE_SECTION_RAM(bt_mesh_ext_adv, 4)\n#endif\n\n#if defined(CONFIG_GEN_SW_ISR_TABLE) && defined(CONFIG_DYNAMIC_INTERRUPTS)\n\tSECTION_DATA_PROLOGUE(sw_isr_table,,)\n\t{\n\t\t\/*\n\t\t * Some arch requires an entry to be aligned to arch\n\t\t * specific boundary for using double word load\n\t\t * instruction.  See include\/sw_isr_table.h.\n\t\t *\/\n\t\t. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);\n\t\t*(_SW_ISR_TABLE_SECTION_SYMS)\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n        SECTION_DATA_PROLOGUE(device_states,,)\n        {\n\t\t\/* Device states used by the device objects. *\/\n                __device_states_start = .;\n\t\tKEEP(*(\".z_devstate\"));\n\t\tKEEP(*(\".z_devstate.*\"));\n                __device_states_end = .;\n        } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if CONFIG_PM_DEVICE\n\tSECTION_DATA_PROLOGUE(pm_device_slots, (NOLOAD),)\n\t{\n\t\t__pm_device_slots_start = .;\n\t\tKEEP(*(\".z_pm_device_slots\"));\n\t\t__pm_device_slots_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n\tSECTION_DATA_PROLOGUE(initshell,,)\n\t{\n\t\t\/* link in shell initialization objects for all modules that\n\t\t * use shell and their shell commands are automatically\n\t\t * initialized by the kernel.\n\t\t *\/\n\t\t__shell_module_start = .;\n\t\tKEEP(*(\".shell_module_*\"));\n\t\t__shell_module_end = .;\n\t\t__shell_cmd_start = .;\n\t\tKEEP(*(\".shell_cmd_*\"));\n\t\t__shell_cmd_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(log_dynamic_sections,,)\n\t{\n\t\t__log_dynamic_start = .;\n\t\tKEEP(*(SORT(.log_dynamic_*)));\n\t\t__log_dynamic_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#ifdef CONFIG_USERSPACE\n\t\/* All kernel objects within are assumed to be either completely\n\t * initialized at build time, or initialized automatically at runtime\n\t * via iteration before the POST_KERNEL phase.\n\t *\n\t * These two symbols only used by gen_kobject_list.py\n\t *\/\n\n\t_static_kernel_objects_begin = .;\n#endif \/* CONFIG_USERSPACE *\/\n\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_timer, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_mem_slab, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_mem_pool, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_heap, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_mutex, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_stack, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_msgq, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_mbox, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_pipe, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_sem, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_event, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_queue, 4)\n\tITERABLE_SECTION_RAM_GC_ALLOWED(k_condvar, 4)\n\n\tSECTION_DATA_PROLOGUE(_net_buf_pool_area,,SUBALIGN(4))\n\t{\n\t\t_net_buf_pool_list = .;\n\t\tKEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#if defined(CONFIG_NETWORKING)\n\tNETWORK_RAM_SECTIONS\n#endif \/* NETWORKING *\/\n\n#if defined(CONFIG_UART_MUX)\n\tSECTION_DATA_PROLOGUE(uart_mux,,SUBALIGN(4))\n\t{\n\t\t__uart_mux_start = .;\n\t\t*(\".uart_mux.*\")\n\t\tKEEP(*(SORT_BY_NAME(\".uart_mux.*\")))\n\t\t__uart_mux_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n#if defined(CONFIG_USB_DEVICE_STACK)\n\tSECTION_DATA_PROLOGUE(usb_descriptor,,SUBALIGN(1))\n\t{\n\t\t__usb_descriptor_start = .;\n\t\t*(\".usb.descriptor\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.descriptor*\")))\n\t\t__usb_descriptor_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n\tSECTION_DATA_PROLOGUE(usb_data,,SUBALIGN(1))\n\t{\n\t\t__usb_data_start = .;\n\t\t*(\".usb.data\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.data*\")))\n\t\t__usb_data_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\tITERABLE_SECTION_RAM(usb_cfg_data, 4)\n#endif \/* CONFIG_USB_DEVICE_STACK *\/\n\n#if defined(CONFIG_USB_DEVICE_BOS)\n\tSECTION_DATA_PROLOGUE(usb_bos_desc,,SUBALIGN(1))\n\t{\n\t\t__usb_bos_desc_start = .;\n\t\t*(\".usb.bos_desc\")\n\t\tKEEP(*(SORT_BY_NAME(\".usb.bos_desc*\")))\n\t\t__usb_bos_desc_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif \/* CONFIG_USB_DEVICE_BOS *\/\n\n#ifdef CONFIG_USERSPACE\n\t_static_kernel_objects_end = .;\n#endif\n\n#if defined(CONFIG_ZTEST)\n\tITERABLE_SECTION_RAM(ztest_suite_node, 4)\n#endif \/* CONFIG_ZTEST *\/\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"986285d3435783f11441e064799dbdcf49bf07da","subject":"[DOCS]: Add a comment","message":"[DOCS]: Add a comment\n","repos":"but0n\/Avem,but0n\/Avem,but0n\/Avem","old_file":"linker.ld","new_file":"linker.ld","new_contents":"ENTRY(Reset_Handler)\n\nMEMORY {\n\t\/*Adust LENGTH to RAMsize of target MCU:*\/\n\t\/*STM32F103RBT --> 20K*\/\n\t\/*RAM (RWX) : ORIGIN = 0x20000000 , LENGTH = 20K*\/\n\t\/*STM32F103RET --> 64K*\/\n\t\/*STM32F103ZET --> 64K*\/\n\tRAM (RWX) : ORIGIN = 0x20000000 , LENGTH = 64K\n\tEXTSRAM (RWX) : ORIGIN = 0x68000000 , LENGTH = 0\n\t\/*Adust LENGTH to (FLASHsize - FeePROMsize) of target MCU:*\/\n\t\/*STM32F103RBT --> 126K*\/\n\tFLASH (RX) : ORIGIN = 0x08000000 , LENGTH = 508K\n\t\/*STM32F103RET --> 508K*\/\n\t\/*FLASH (RX) : ORIGIN = 0x08000000 , LENGTH = 508K*\/\n\t\/*STM32F103ZET --> 508K*\/\n\t\/*FLASH (RX) : ORIGIN = 0x08000000 , LENGTH = 508K*\/\n\t\/*Adust ORIGIN to (0x08000000 + (FLASHsize-FeePROMsize)) of target MCU*\/\n\t\/*and adust LENGTH to FeePROMsize allocated:*\/\n\t\/*STM32F103RBT --> 0x08000000+126K, 2K*\/\n\tEEMUL (RWX) : ORIGIN = 0x08000000+508K, LENGTH = 4K\n\t\/*STM32F103RET --> 0x08000000+508K, 4K*\/\n\t\/*EEMUL (RWX) : ORIGIN = 0x08000000+508K, LENGTH = 4K*\/\n}\n_estack\t= ORIGIN(RAM)+LENGTH(RAM);\t\/* end of the stack *\/\n_seemul = ORIGIN(EEMUL);\t\/* start of the eeprom emulation area; stm32\u7684 eeprom \u662f\u7528 flash \u6a21\u62df\u7684 *\/\n_min_stack\t= 0x100;\t\/* minimum stack space to reserve for the user app *\/\n\/* check valid alignment for the vector table *\/\nASSERT(ORIGIN(FLASH) == ALIGN(ORIGIN(FLASH), 0x80), \"Start of memory region flash not aligned for startup vector table\");\nSECTIONS {\n\t\/* vector table and program code goes into FLASH *\/\n\t.text : {\n\t\t. = ALIGN(0x80);\n\t\t_isr_vectors_offs = . - 0x08000000;\n\t\tKEEP(*(.isr_vectors))\n\t\t. = ALIGN(4);\n\t\tCREATE_OBJECT_SYMBOLS\n\t\t*(.text .text.*)\n\t} >FLASH\n\t.rodata : ALIGN (4) {\n\t\t*(.rodata .rodata.*)\n\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init))\n\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.fini))\n\n\t\t. = ALIGN(4);\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\t*(.init .init.*)\n\t\t*(.fini .fini.*)\n\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\t. = ALIGN (8);\n\t\t*(.rom)\n\t\t*(.rom.b)\n\t\t_etext = .;\n\t\t_sidata = _etext; \/* exported for the startup function *\/\n\t} >FLASH\n\t\/*\n\t\tthis data is expected by the program to be in ram\n\t\tbut we have to store it in the FLASH otherwise it\n\t\twill get lost between resets, so the startup code\n\t\thas to copy it into RAM before the program starts\n\t*\/\n\t.data : ALIGN (8) {\n\t\t_sdata = . ; \/* exported for the startup function *\/\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.jcr))\n\t\t*(.got.plt) *(.got)\n\t\t*(.shdata)\n\t\t*(.data .data.*)\n\t\t. = ALIGN (8);\n\t\t*(.ram)\n\t\t*(.ramfunc*)\n\t\t. = ALIGN(4);\n\t\t_edata = . ; \/* exported for the startup function *\/\n\t} >RAM AT>FLASH\n\t\/* This is the uninitialized data section *\/\n\t.bss (NOLOAD): {\n\t\t. = ALIGN(4);\n\t\t_sbss = . ; \/* exported for the startup function *\/\n\t\t*(.shbss)\n\t\t*(.bss .bss.*)\n\t\t*(COMMON)\n\t\t. = ALIGN (8);\n\t\t*(.ram.b)\n\t\t. = ALIGN(4);\n\t\t_ebss = . ; \/* exported for the startup function *\/\n\t\t_end = .;\n\t\t__end = .;\n\t} >RAM AT>FLASH\n\t\/* ensure there is enough room for the user stack *\/\n\t._usrstack (NOLOAD): {\n\t\t. = ALIGN(4);\n\t\t_susrstack = . ;\n\t\t. = . + _min_stack ;\n\t\t. = ALIGN(4);\n\t\t_eusrstack = . ;\n\t} >RAM\n\t\/* Stabs debugging sections. *\/\n\t.stab\t\t0 : { *(.stab) }\n\t.stabstr\t0 : { *(.stabstr) }\n\t.stab.excl \t0 : { *(.stab.excl) }\n\t.stab.exclstr \t0 : { *(.stab.exclstr) }\n\t.stab.index \t0 : { *(.stab.index) }\n\t.stab.indexstr \t0 : { *(.stab.indexstr) }\n\t.comment\t0 : { *(.comment) }\n\t\/* DWARF debug sections.\n\t\tSymbols in the DWARF debugging sections are relative to the beginning\n\t\tof the section so we begin them at 0. *\/\n\t\/* DWARF 1 *\/\n\t.debug\t\t0 : { *(.debug) }\n\t.line\t\t0 : { *(.line) }\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo 0 : { *(.debug_srcinfo) }\n\t.debug_sfnames 0 : { *(.debug_sfnames) }\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t\/* DWARF 2 *\/\n\t.debug_info \t0 : { *(.debug_info .gnu.linkonce.wi.*) }\n\t.debug_abbrev \t0 : { *(.debug_abbrev) }\n\t.debug_line \t0 : { *(.debug_line) }\n\t.debug_frame \t0 : { *(.debug_frame) }\n\t.debug_str\t0 : { *(.debug_str) }\n\t.debug_loc\t0 : { *(.debug_loc) }\n\t.debug_macinfo \t0 : { *(.debug_macinfo) }\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\n\t.debug_typenames 0 : { *(.debug_typenames) }\n\t.debug_varnames 0 : { *(.debug_varnames) }\n\t\/* DWARF 3 *\/\n\t.debug_pubtypes 0 : { *(.debug_pubtypes) }\n\t.debug_ranges 0 : { *(.debug_ranges) }\n\n\t.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }\n\t.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n\t\/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","old_contents":"ENTRY(Reset_Handler)\n\nMEMORY {\n\t\/*Adust LENGTH to RAMsize of target MCU:*\/\n\t\/*STM32F103RBT --> 20K*\/\n\t\/*RAM (RWX) : ORIGIN = 0x20000000 , LENGTH = 20K*\/\n\t\/*STM32F103RET --> 64K*\/\n\t\/*STM32F103ZET --> 64K*\/\n\tRAM (RWX) : ORIGIN = 0x20000000 , LENGTH = 64K\n\tEXTSRAM (RWX) : ORIGIN = 0x68000000 , LENGTH = 0\n\t\/*Adust LENGTH to (FLASHsize - FeePROMsize) of target MCU:*\/\n\t\/*STM32F103RBT --> 126K*\/\n\tFLASH (RX) : ORIGIN = 0x08000000 , LENGTH = 508K\n\t\/*STM32F103RET --> 508K*\/\n\t\/*FLASH (RX) : ORIGIN = 0x08000000 , LENGTH = 508K*\/\n\t\/*STM32F103ZET --> 508K*\/\n\t\/*FLASH (RX) : ORIGIN = 0x08000000 , LENGTH = 508K*\/\n\t\/*Adust ORIGIN to (0x08000000 + (FLASHsize-FeePROMsize)) of target MCU*\/\n\t\/*and adust LENGTH to FeePROMsize allocated:*\/\n\t\/*STM32F103RBT --> 0x08000000+126K, 2K*\/\n\tEEMUL (RWX) : ORIGIN = 0x08000000+508K, LENGTH = 4K\n\t\/*STM32F103RET --> 0x08000000+508K, 4K*\/\n\t\/*EEMUL (RWX) : ORIGIN = 0x08000000+508K, LENGTH = 4K*\/\n}\n_estack\t= ORIGIN(RAM)+LENGTH(RAM);\t\/* end of the stack *\/\n_seemul = ORIGIN(EEMUL);\t\/* start of the eeprom emulation area *\/\n_min_stack\t= 0x100;\t\/* minimum stack space to reserve for the user app *\/\n\/* check valid alignment for the vector table *\/\nASSERT(ORIGIN(FLASH) == ALIGN(ORIGIN(FLASH), 0x80), \"Start of memory region flash not aligned for startup vector table\");\nSECTIONS {\n\t\/* vector table and program code goes into FLASH *\/\n\t.text : {\n\t\t. = ALIGN(0x80);\n\t\t_isr_vectors_offs = . - 0x08000000;\n\t\tKEEP(*(.isr_vectors))\n\t\t. = ALIGN(4);\n\t\tCREATE_OBJECT_SYMBOLS\n\t\t*(.text .text.*)\n\t} >FLASH\n\t.rodata : ALIGN (4) {\n\t\t*(.rodata .rodata.*)\n\t\t\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init))\n\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP (*(.preinit_array))\n\t\t__preinit_array_end = .;\n\n\t\t. = ALIGN(4);\n\t\t__init_array_start = .;\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\t__init_array_end = .;\n\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.fini))\n\n\t\t. = ALIGN(4);\n\t\t__fini_array_start = .;\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\t__fini_array_end = .;\n\n\t\t*(.init .init.*)\n\t\t*(.fini .fini.*)\n\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP (*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP (*(SORT(.init_array.*)))\n\t\tKEEP (*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP (*(.fini_array))\n\t\tKEEP (*(SORT(.fini_array.*)))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\t. = ALIGN (8);\n\t\t*(.rom)\n\t\t*(.rom.b)\n\t\t_etext = .;\n\t\t_sidata = _etext; \/* exported for the startup function *\/\n\t} >FLASH\n\t\/*\n\t\tthis data is expected by the program to be in ram\n\t\tbut we have to store it in the FLASH otherwise it\n\t\twill get lost between resets, so the startup code\n\t\thas to copy it into RAM before the program starts\n\t*\/\n\t.data : ALIGN (8) {\n\t\t_sdata = . ; \/* exported for the startup function *\/\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.jcr))\n\t\t*(.got.plt) *(.got)\n\t\t*(.shdata)\n\t\t*(.data .data.*)\n\t\t. = ALIGN (8);\n\t\t*(.ram)\n\t\t*(.ramfunc*)\n\t\t. = ALIGN(4);\n\t\t_edata = . ; \/* exported for the startup function *\/\n\t} >RAM AT>FLASH\n\t\/* This is the uninitialized data section *\/\n\t.bss (NOLOAD): {\n\t\t. = ALIGN(4);\n\t\t_sbss = . ; \/* exported for the startup function *\/\n\t\t*(.shbss)\n\t\t*(.bss .bss.*)\n\t\t*(COMMON)\n\t\t. = ALIGN (8);\n\t\t*(.ram.b)\n\t\t. = ALIGN(4);\n\t\t_ebss = . ; \/* exported for the startup function *\/\n\t\t_end = .;\n\t\t__end = .;\n\t} >RAM AT>FLASH\n\t\/* ensure there is enough room for the user stack *\/\n\t._usrstack (NOLOAD): {\n\t\t. = ALIGN(4);\n\t\t_susrstack = . ;\n\t\t. = . + _min_stack ;\n\t\t. = ALIGN(4);\n\t\t_eusrstack = . ;\n\t} >RAM\n\t\/* Stabs debugging sections. *\/\n\t.stab\t\t0 : { *(.stab) }\n\t.stabstr\t0 : { *(.stabstr) }\n\t.stab.excl \t0 : { *(.stab.excl) }\n\t.stab.exclstr \t0 : { *(.stab.exclstr) }\n\t.stab.index \t0 : { *(.stab.index) }\n\t.stab.indexstr \t0 : { *(.stab.indexstr) }\n\t.comment\t0 : { *(.comment) }\n\t\/* DWARF debug sections.\n\t\tSymbols in the DWARF debugging sections are relative to the beginning\n\t\tof the section so we begin them at 0. *\/\n\t\/* DWARF 1 *\/\n\t.debug\t\t0 : { *(.debug) }\n\t.line\t\t0 : { *(.line) }\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo 0 : { *(.debug_srcinfo) }\n\t.debug_sfnames 0 : { *(.debug_sfnames) }\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges 0 : { *(.debug_aranges) }\n\t.debug_pubnames 0 : { *(.debug_pubnames) }\n\t\/* DWARF 2 *\/\n\t.debug_info \t0 : { *(.debug_info .gnu.linkonce.wi.*) }\n\t.debug_abbrev \t0 : { *(.debug_abbrev) }\n\t.debug_line \t0 : { *(.debug_line) }\n\t.debug_frame \t0 : { *(.debug_frame) }\n\t.debug_str\t0 : { *(.debug_str) }\n\t.debug_loc\t0 : { *(.debug_loc) }\n\t.debug_macinfo \t0 : { *(.debug_macinfo) }\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\t.debug_weaknames 0 : { *(.debug_weaknames) }\t\n\t.debug_funcnames 0 : { *(.debug_funcnames) }\n\t.debug_typenames 0 : { *(.debug_typenames) }\n\t.debug_varnames 0 : { *(.debug_varnames) }\n\t\/* DWARF 3 *\/\n\t.debug_pubtypes 0 : { *(.debug_pubtypes) }\n\t.debug_ranges 0 : { *(.debug_ranges) }\n\n\t.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }\n\t.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n\t\/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"1212ea0c399ab6c029d91195333dd7815a53d0c1","subject":"riscv: linker.ld: Fix undefined reference linker error","message":"riscv: linker.ld: Fix undefined reference linker error\n\nThe commit a28830b aligned the data and rename some symbols.  However\nthere are two symbols at riscv linker script that were missing, which\ncauses below linker error:\n\nkernel\/xip.c:28: undefined reference to `__itcm_load_start'\nkernel\/xip.c:43: undefined reference to `__dtcm_data_load_start'\n\nRename below symbols to fix the issues.\n\n__itcm_rom_start -> __itcm_load_start\n__dtcm_data_rom_start -> __dtcm_data_load_start\n\nSigned-off-by: Gerson Fernando Budke <0ad1c92223f8f375c46e39c6141096f3d30896b4@gmail.com>\n","repos":"zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr","old_file":"include\/arch\/riscv\/common\/linker.ld","new_file":"include\/arch\/riscv\/common\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","old_contents":"\/*\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Generic Linker script for the riscv platform\n *\/\n\n#include <soc.h>\n#include <devicetree.h>\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/devicetree_regions.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#ifdef CONFIG_XIP\n#define ROMABLE_REGION              ROM\n#else\n#define ROMABLE_REGION              RAM\n#endif\n#define RAMABLE_REGION              RAM\n\n#define _VECTOR_SECTION_NAME        vector\n#define _EXCEPTION_SECTION_NAME     exceptions\n#define _RESET_SECTION_NAME         reset\n\n#ifdef CONFIG_XIP\n#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)\n#ifdef CONFIG_FLASH_LOAD_OFFSET\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \\\n\t\t\t\tCONFIG_FLASH_LOAD_OFFSET)\n#else \/* !CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#endif \/* CONFIG_FLASH_LOAD_OFFSET *\/\n#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))\n#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)\n\/* For jedec,spi-nor we expect the spi controller to memory map the flash\n * and for that mapping to be the second register property of the spi\n * controller.\n *\/\n#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))\n#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)\n#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)\n#endif\n#else \/* CONFIG_XIP *\/\n#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define ROM_SIZE KB(CONFIG_SRAM_SIZE)\n#endif \/* CONFIG_XIP *\/\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\n#ifdef CONFIG_RISCV_PMP\n\t#define MPU_MIN_SIZE 4\n\t#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );\n\t#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE); \\\n\t\t\t. = ALIGN( 1 << LOG2CEIL(region_size))\n\t#else\n\t\t#define MPU_ALIGN(region_size) \\\n\t\t\t. = ALIGN(MPU_MIN_SIZE)\n\t#endif\n#else\n\t#define MPU_MIN_SIZE_ALIGN\n\t#define MPU_ALIGN(region_size) . = ALIGN(4)\n#endif\n\nMEMORY\n{\n#ifdef CONFIG_XIP\n    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE\n#endif\n    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE\n\n    \/* Data & Instruction Tightly Coupled Memory *\/\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_itcm), rw)\n    LINKER_DT_REGION_FROM_NODE(DT_CHOSEN(zephyr_dtcm), rw)\n\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * The .plt and .iplt are here according to\n     * 'riscv32-zephyr-elf-ld --verbose', before text section.\n     *\/\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n    __rom_region_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)\n    {\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.vectors.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(rom_start,,)\n    {\n\t\t. = ALIGN(16);\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...).\n *\/\n#include <snippets-rom-start.ld>\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)\n    {\n\t\tKEEP(*(.reset.*))\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)\n    {\n\t\t KEEP(*(\".exception.entry.*\"))\n\t\t *(\".exception.other.*\")\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.openocd_debug))\n\t\tKEEP(*(\".openocd_debug.*\"))\n\n\t\t__text_region_start = .;\n\n\t\t*(.text)\n\t\t*(\".text.*\")\n\t\t*(.gnu.linkonce.t.*)\n#include <linker\/kobject-text.ld>\n#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION\n\t\t. = ALIGN(0x1000);\n\t\t_ram_code_start = .;\n\t\tKEEP(*(.__ram_code))\n\t\t__ram_code_size = . - _ram_code_start;\n\t\tASSERT((__ram_code_size <= 0x1000),\n\t\t\t\"__ram_code_size <= 4k bytes\");\n#endif\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n    __text_region_end = .;\n\n\t__rodata_region_start = .;\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t *(.srodata)\n\t\t *(\".srodata.*\")\n\t\t *(.rodata)\n\t\t *(\".rodata.*\")\n\t\t *(.gnu.linkonce.r.*)\n\t\t *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#include <linker\/kobject-rom.ld>\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\t__rodata_region_end = .;\n\n\t\/* For non-XIP system, __rom_region_end symbol should be set to\n\t * the end of common ROMABLE_REGIONs (text and rodata) instead of\n\t * the linker script end, so it wouldn't mistakely contain\n\t * RAMABLE_REGION in it.\n\t *\/\n#ifndef CONFIG_XIP\n#ifdef CONFIG_RISCV_PMP\n\tSECTION_PROLOGUE(rom_mpu_padding,,)\n\t{\n\t\tMPU_ALIGN(__rodata_region_end - __rom_region_start);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif \/* CONFIG_RISCV_PMP *\/\n\n\t__rom_region_end = .;\n\t__rom_region_size = __rom_region_end - __rom_region_start;\n#endif \/* CONFIG_XIP *\/\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_image_ram_start = _app_smem_start;\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\tMPU_MIN_SIZE_ALIGN\n\t\t\/*\n\t\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t\t * a multiple of 4 bytes\n\t\t *\/\n\t\t . = ALIGN(4);\n\t\t __bss_start = .;\n\t\t _image_ram_start = .;\n\t\t__kernel_ram_start = .;\n\t\t *(.sbss)\n\t\t *(\".sbss.*\")\n\t\t *(.bss)\n\t\t *(\".bss.*\")\n\t\t COMMON_SYMBOLS\n\t\t \/*\n\t\t  * As memory is cleared in words only, it is simpler to ensure the BSS\n\t\t  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t  *\/\n\t\t  __bss_end = ALIGN(4);\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t\t . = ALIGN(4);\n\t\t\/* _image_ram_start = .; *\/\n\t\t __data_region_start = .;\n\t\t __data_start = .;\n\n\t\t *(.data)\n\t\t *(\".data.*\")\n\n#ifdef CONFIG_RISCV_GP\n\t\t\/*\n\t\t * RISC-V architecture has 12-bit signed immediate offsets in the\n\t\t * instructions. If we can put the most commonly accessed globals\n\t\t * in a special 4K span of memory addressed by the GP register, then\n\t\t * we can access those values in a single instruction, saving both\n\t\t * codespace and runtime.\n\t\t *\n\t\t * Since these immediate offsets are signed, place gp 0x800 past the\n\t\t * beginning of .sdata so that we can use both positive and negative\n\t\t * offsets.\n\t\t *\/\n\t\t . = ALIGN(8);\n\t\t PROVIDE (__global_pointer$ = . + 0x800);\n#endif\n\n\t\t *(.sdata .sdata.* .gnu.linkonce.s.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\t\t __data_end = .;\n\n\t}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\t__data_size = __data_end - __data_start;\n\t__data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n\t__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject-data.ld>\n#include <linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n    MPU_MIN_SIZE_ALIGN\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n\t__kernel_ram_end = .;\n\t__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)\nGROUP_START(ITCM)\n\n\tSECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__itcm_start = .;\n\t\t*(.itcm)\n\t\t*(\".itcm.*\")\n\t\t__itcm_end = .;\n\t} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)\n\n\t__itcm_size = __itcm_end - __itcm_start;\n\t__itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME);\n\nGROUP_END(ITCM)\n#endif\n\n#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)\nGROUP_START(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_start = .;\n\t\t__dtcm_bss_start = .;\n\t\t*(.dtcm_bss)\n\t\t*(\".dtcm_bss.*\")\n\t\t__dtcm_bss_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))\n\t{\n\t\t__dtcm_noinit_start = .;\n\t\t*(.dtcm_noinit)\n\t\t*(\".dtcm_noinit.*\")\n\t\t__dtcm_noinit_end = .;\n\t} GROUP_LINK_IN(DTCM)\n\n\tSECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))\n\t{\n\t\t__dtcm_data_start = .;\n\t\t*(.dtcm_data)\n\t\t*(\".dtcm_data.*\")\n\t\t__dtcm_data_end = .;\n\t} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)\n\n\t__dtcm_end = .;\n\n\t__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);\n\nGROUP_END(DTCM)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n     GROUP_END(RAMABLE_REGION)\n\n#include <linker\/debug-sections.ld>\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n\/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid\n * to set __rom_region_end symbol at the end of linker script and\n * doesn't mistakely contain the RAMABLE_REGION in it.\n *\/\n#ifdef CONFIG_XIP\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n__rom_region_end = LOADADDR(.last_section);\n__rom_region_size = __rom_region_end - __rom_region_start;\n#endif\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a6403bee004b576e71e7d428bf5cc37a05235549","subject":"Move stack define out of boot.asm","message":"Move stack define out of boot.asm\n","repos":"IcebergOS\/frogimine,IcebergOS\/frogimine,IcebergOS\/Cryst","old_file":"scripts\/linker.ld","new_file":"scripts\/linker.ld","new_contents":"ENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t\t. = ALIGN(4096);\n\t}\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(4096);\n\t}\n\t.stab :\n\t{\n\t\t*(.stab)\n\t\t. = ALIGN(4096);\n\t}\n\t.stabstr :\n\t{\n\t\t*(.stabstr)\n\t\t. = ALIGN(4096);\n\t}\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t. = ALIGN(4096);\n\t}\n\n\tSTACK_TOP = .;\n\t. = ALIGN(32768);\n\tKERNEL_CODE_END = .;\n\n\t\/DISCARD\/ : { *(.comment) *(.eh_frame) }\n}\n","old_contents":"ENTRY(_start)\nSECTIONS\n{\n\t. = 0x100000;\n\n\t.text :\n\t{\n\t\t*(.multiboot)\n\t\t*(.text)\n\t\t. = ALIGN(4096);\n\t}\n\t.data :\n\t{\n\t\t*(.data)\n\t\t*(.rodata)\n\t\t. = ALIGN(4096);\n\t}\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t. = ALIGN(4096);\n\t}\n\t.stab :\n\t{\n\t\t*(.stab)\n\t\t. = ALIGN(4096);\n\t}\n\t.stabstr :\n\t{\n\t\t*(.stabstr)\n\t\t. = ALIGN(4096);\n\t}\n\n\t. = ALIGN(4096);\n\tKERNEL_CODE_END = .;\n\n\t\/DISCARD\/ : { *(.comment) *(.eh_frame) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"09f8a83a756c784e846d2acd9a929e4a45ea34b4","subject":"samd: template.ld: put canram in its own output section","message":"samd: template.ld: put canram in its own output section\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/atmel-samd\/boards\/common.template.ld","new_file":"ports\/atmel-samd\/boards\/common.template.ld","new_contents":"\/* Template for SAMD21\/SAMD51 linking. dollar-sign-curly-bracket items are replaced with strings. *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_BOOTLOADER (rx): ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_FILESYSTEM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_CONFIG (r) : ORIGIN = ${CIRCUITPY_INTERNAL_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_CONFIG_SIZE}\n    FLASH_NVM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n\n    RAM (xrw)  : ORIGIN = 0x20000000, LENGTH = ${RAM_SIZE}\n}\n\n\/* top end of the stack *\/\n\/* stack must be double-word (8 byte) aligned *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - 8;\n_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n    } >FLASH_FIRMWARE\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = .;       \/* start of .data section *\/\n    } >FLASH_FIRMWARE\n\n    \/* Data accessed by the CAN peripheral must be in the first 64kB RAM *\/\n    \/* place it at the very start of RAM, before the .data section *\/\n    \/* it is zeroed by reset_port *\/\n    .canram (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _scanram = .;\n        *(.canram)\n        _ecanram = .;\n    } > RAM\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH_FIRMWARE to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _srelocate = .;        \/* create a global symbol at data start; used by startup code in order to initialize the .data section in RAM *\/\n        . = ALIGN(4);\n        *(.ramfunc)\n        *(.ramfunc*)\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _erelocate = .;        \/* define a global symbol at data end; used by startup code in order to initialize the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        _szero = .;         \/* define a global symbol at bss start; used by startup code *\/\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ezero = .;         \/* define a global symbol at bss end; used by startup code *\/\n        _ebss = .;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the requested stack. *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","old_contents":"\/* Template for SAMD21\/SAMD51 linking. dollar-sign-curly-bracket items are replaced with strings. *\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH_BOOTLOADER (rx): ORIGIN = ${BOOTLOADER_START_ADDR}, LENGTH = ${BOOTLOADER_SIZE}\n\n    FLASH_FIRMWARE (rx) : ORIGIN = ${CIRCUITPY_FIRMWARE_START_ADDR}, LENGTH = ${CIRCUITPY_FIRMWARE_SIZE}\n    FLASH_FILESYSTEM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE}\n    FLASH_CONFIG (r) : ORIGIN = ${CIRCUITPY_INTERNAL_CONFIG_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_CONFIG_SIZE}\n    FLASH_NVM (r) : ORIGIN = ${CIRCUITPY_INTERNAL_NVM_START_ADDR}, LENGTH = ${CIRCUITPY_INTERNAL_NVM_SIZE}\n\n    RAM (xrw)  : ORIGIN = 0x20000000, LENGTH = ${RAM_SIZE}\n}\n\n\/* top end of the stack *\/\n\/* stack must be double-word (8 byte) aligned *\/\n_estack = ORIGIN(RAM) + LENGTH(RAM) - 8;\n_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;\n\n\/* define output sections *\/\nSECTIONS\n{\n    \/* The program code and other data goes into FLASH *\/\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        KEEP(*(.vectors)) \/* isr vector table *\/\n        *(.text)           \/* .text sections (code) *\/\n        *(.text*)          \/* .text* sections (code) *\/\n        *(.rodata)         \/* .rodata sections (constants, strings, etc.) *\/\n        *(.rodata*)        \/* .rodata* sections (constants, strings, etc.) *\/\n\n        . = ALIGN(4);\n    } >FLASH_FIRMWARE\n\n    .ARM.exidx :\n    {\n        *(.ARM.exidx*)\n        *(.gnu.linkonce.armexidx.*)\n        _etext = .;        \/* define a global symbol at end of code *\/\n        _sidata = .;       \/* start of .data section *\/\n    } >FLASH_FIRMWARE\n\n    \/* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH_FIRMWARE (inidata).\n    It is one task of the startup to copy the initial values from FLASH_FIRMWARE to RAM. *\/\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _srelocate = .;        \/* create a global symbol at data start; used by startup code in order to initialize the .data section in RAM *\/\n        . = ALIGN(4);\n        *(.ramfunc)\n        *(.ramfunc*)\n        *(.data)           \/* .data sections *\/\n        *(.data*)          \/* .data* sections *\/\n\n        . = ALIGN(4);\n        _erelocate = .;        \/* define a global symbol at data end; used by startup code in order to initialize the .data section in RAM *\/\n    } >RAM\n\n    \/* Uninitialized data section *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = .;\n        _szero = .;         \/* define a global symbol at bss start; used by startup code *\/\n        \/* Data accessed by the CAN peripheral must be in the first 64kB RAM *\/\n        _scanram = .;\n        *(.canram)\n        _ecanram = .;\n        *(.bss)\n        *(.bss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ezero = .;         \/* define a global symbol at bss end; used by startup code *\/\n        _ebss = .;\n    } >RAM\n\n    \/* this just checks there is enough RAM for the requested stack. *\/\n    .stack :\n    {\n        . = ALIGN(4);\n        . = . + ${CIRCUITPY_DEFAULT_STACK_SIZE};\n        . = ALIGN(4);\n    } >RAM\n\n    .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"b726259bfd7013b706ab689b8961d575cfca4d93","subject":"Update LPC1549.ld","message":"Update LPC1549.ld\n","repos":"Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS","old_file":"TARGET_NXP\/TARGET_LPC15XX\/TOOLCHAIN_GCC_CR\/LPC1549.ld","new_file":"TARGET_NXP\/TARGET_LPC15XX\/TOOLCHAIN_GCC_CR\/LPC1549.ld","new_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC1549\n * Created from generic_c.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Tue Jun 10 00:20:53 JST 2014\n *\/\n\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_16 (rwx) : ORIGIN = 0x2000000+0x100, LENGTH = 0x4000-0x100 \/* 16K bytes *\/\n  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 \/* 16K bytes *\/\n  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 \/* 4K bytes *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_16 = 0x2000000 + 0x4000;\n  __top_Ram1_16 = 0x2004000 + 0x4000;\n  __top_Ram2_4 = 0x2008000 + 0x1000;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n            \n    \/* DATA section for Ram1_16 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_16)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16 AT>MFlash256\n    \n    \/* DATA section for Ram2_4 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2_4)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/ \n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_16\n\t\n\t\/* Main DATA section (Ram0_16) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_16 AT>MFlash256\n\n    \/* BSS section for Ram1_16 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16\n    \/* BSS section for Ram2_4 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_16\n        \n    \/* NOINIT section for Ram1_16 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16 \n    \/* NOINIT section for Ram2_4 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_16\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_16 - 0);\n}\n","old_contents":"\/*Based on following file*\/\n\/*\n * GENERATED FILE - DO NOT EDIT\n * (c) Code Red Technologies Ltd, 2008-13\n * (c) NXP Semiconductors 2013-2014\n * Generated linker script file for LPC1549\n * Created from generic_c.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))\n * By LPCXpresso v7.2.0 [Build 153] [2014-05-19]  on Tue Jun 10 00:20:53 JST 2014\n *\/\n\nGROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)\n\nMEMORY\n{\n  \/* Define each memory region *\/\n  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 \/* 256K bytes *\/\n  Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 \/* 16K bytes *\/\n  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 \/* 16K bytes *\/\n  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 \/* 4K bytes *\/\n\n}\n  \/* Define a symbol for the top of each memory region *\/\n  __top_MFlash256 = 0x0 + 0x40000;\n  __top_Ram0_16 = 0x2000000 + 0x4000;\n  __top_Ram1_16 = 0x2004000 + 0x4000;\n  __top_Ram2_4 = 0x2008000 + 0x1000;\n\nENTRY(ResetISR)\n\nSECTIONS\n{\n\n    \/* MAIN TEXT SECTION *\/    \n    .text : ALIGN(4)\n    {\n        FILL(0xff)\n        KEEP(*(.isr_vector))\n        \n        \/* Global Section Table *\/\n        . = ALIGN(4) ;\n        __section_table_start = .;\n        __data_section_table = .;\n        LONG(LOADADDR(.data));\n        LONG(    ADDR(.data));\n        LONG(  SIZEOF(.data));\n        LONG(LOADADDR(.data_RAM2));\n        LONG(    ADDR(.data_RAM2));\n        LONG(  SIZEOF(.data_RAM2));\n        LONG(LOADADDR(.data_RAM3));\n        LONG(    ADDR(.data_RAM3));\n        LONG(  SIZEOF(.data_RAM3));\n        __data_section_table_end = .;\n        __bss_section_table = .;\n        LONG(    ADDR(.bss));\n        LONG(  SIZEOF(.bss));\n        LONG(    ADDR(.bss_RAM2));\n        LONG(  SIZEOF(.bss_RAM2));\n        LONG(    ADDR(.bss_RAM3));\n        LONG(  SIZEOF(.bss_RAM3));\n        __bss_section_table_end = .;\n        __section_table_end = . ;\n        \/* End of Global Section Table *\/\n        \n\n        *(.after_vectors*)\n        \n        *(.text*)\n        *(.rodata .rodata.*)\n        . = ALIGN(4);\n        \n        \/* C++ constructors etc *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        \n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n        \n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n        \n        KEEP(*(.fini));\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n        \n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n    } > MFlash256\n\n    \/*\n     * for exception handling\/unwind - some Newlib functions (in common\n     * with C++ and STDC++) use this. \n     *\/\n    .ARM.extab : ALIGN(4)\n    {\n    \t*(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > MFlash256\n    __exidx_start = .;\n    \n    .ARM.exidx : ALIGN(4)\n    {\n    \t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > MFlash256\n    __exidx_end = .;\n    \n    _etext = .;\n            \n    \/* DATA section for Ram1_16 *\/\n    .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM2)\n       *(.ramfunc.$Ram1_16)\n    \t*(.data.$RAM2*)\n    \t*(.data.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16 AT>MFlash256\n    \n    \/* DATA section for Ram2_4 *\/\n    .data_RAM3 : ALIGN(4)\n    {\n       FILL(0xff)\n       *(.ramfunc.$RAM3)\n       *(.ramfunc.$Ram2_4)\n    \t*(.data.$RAM3*)\n    \t*(.data.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4 AT>MFlash256\n    \n    \/* MAIN DATA SECTION *\/ \n    .uninit_RESERVED : ALIGN(4)\n    {\n        KEEP(*(.bss.$RESERVED*))\n        . = ALIGN(4) ;\n        _end_uninit_RESERVED = .;\n    } > Ram0_16\n\t\n\t\/* Main DATA section (Ram0_16) *\/\n\t.data : ALIGN(4)\n\t{\n\t   FILL(0xff)\n\t   _data = . ;\n\t   *(vtable)\n\t   *(.ramfunc*)\n\t   *(.data*)\n\t   . = ALIGN(4) ;\n\t   _edata = . ;\n\t} > Ram0_16 AT>MFlash256\n\n    \/* BSS section for Ram1_16 *\/\n    .bss_RAM2 : ALIGN(4)\n    {\n    \t*(.bss.$RAM2*)\n    \t*(.bss.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16\n    \/* BSS section for Ram2_4 *\/\n    .bss_RAM3 : ALIGN(4)\n    {\n    \t*(.bss.$RAM3*)\n    \t*(.bss.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4\n\n    \/* MAIN BSS SECTION *\/\n    .bss : ALIGN(4)\n    {\n        _bss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4) ;\n        _ebss = .;\n        PROVIDE(end = .);\n        __end__ = .;\n    } > Ram0_16\n        \n    \/* NOINIT section for Ram1_16 *\/\n    .noinit_RAM2 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM2*)\n    \t*(.noinit.$Ram1_16*)\n       . = ALIGN(4) ;\n    } > Ram1_16 \n    \/* NOINIT section for Ram2_4 *\/\n    .noinit_RAM3 (NOLOAD) : ALIGN(4)\n    {\n    \t*(.noinit.$RAM3*)\n    \t*(.noinit.$Ram2_4*)\n       . = ALIGN(4) ;\n    } > Ram2_4 \n    \n    \/* DEFAULT NOINIT SECTION *\/\n    .noinit (NOLOAD): ALIGN(4)\n    {\n        _noinit = .;\n        *(.noinit*) \n         . = ALIGN(4) ;\n        _end_noinit = .;\n    } > Ram0_16\n    \n    PROVIDE(_pvHeapStart = .);\n    PROVIDE(_vStackTop = __top_Ram0_16 - 0);\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"988f9b3a59c7d7ef5073cd4aba145e8d607517df","subject":"esp_wifi: fix esp32c2 tx crash issue","message":"esp_wifi: fix esp32c2 tx crash issue\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.ld","new_file":"components\/esp_rom\/esp32c2\/ld\/esp32c2.rom.ld","new_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\nrtc_get_wakeup_cause = 0x40000020;\nrtc_select_apb_bridge = 0x40000024;\nrtc_unhold_all_pads = 0x40000028;\nets_is_print_boot = 0x4000002c;\nets_vprintf = 0x40000030;\nets_printf = 0x40000034;\nets_install_putc1 = 0x40000038;\nets_install_uart_printf = 0x4000003c;\nets_install_putc2 = 0x40000040;\nets_delay_us = 0x40000044;\nets_get_stack_info = 0x40000048;\nets_install_lock = 0x4000004c;\nUartRxString = 0x40000050;\nUartGetCmdLn = 0x40000054;\nuart_tx_one_char = 0x40000058;\nuart_tx_one_char2 = 0x4000005c;\nuart_rx_one_char = 0x40000060;\nuart_rx_one_char_block = 0x40000064;\nuart_rx_readbuff = 0x40000068;\nuartAttach = 0x4000006c;\nuart_tx_flush = 0x40000070;\nuart_tx_wait_idle = 0x40000074;\nuart_div_modify = 0x40000078;\nets_write_char_uart = 0x4000007c;\nuart_tx_switch = 0x40000080;\nmultofup = 0x40000084;\nsoftware_reset = 0x40000088;\nsoftware_reset_cpu = 0x4000008c;\nassist_debug_clock_enable = 0x40000090;\nassist_debug_record_enable = 0x40000094;\nclear_super_wdt_reset_flag = 0x40000098;\ndisable_default_watchdog = 0x4000009c;\nsend_packet = 0x400000a0;\nrecv_packet = 0x400000a4;\nGetUartDevice = 0x400000a8;\nUartDwnLdProc = 0x400000ac;\nGetSecurityInfoProc = 0x400000b0;\nUart_Init = 0x400000b4;\nets_set_user_start = 0x400000b8;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff4fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000bc;\nmz_free = 0x400000c0;\ntdefl_compress = 0x400000c4;\ntdefl_compress_buffer = 0x400000c8;\ntdefl_compress_mem_to_heap = 0x400000cc;\ntdefl_compress_mem_to_mem = 0x400000d0;\ntdefl_compress_mem_to_output = 0x400000d4;\ntdefl_get_adler32 = 0x400000d8;\ntdefl_get_prev_return_status = 0x400000dc;\ntdefl_init = 0x400000e0;\ntdefl_write_image_to_png_file_in_memory = 0x400000e4;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000e8;\ntinfl_decompress = 0x400000ec;\ntinfl_decompress_mem_to_callback = 0x400000f0;\ntinfl_decompress_mem_to_heap = 0x400000f4;\ntinfl_decompress_mem_to_mem = 0x400000f8;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 );\nPROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 );\nPROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 );\nPROVIDE( _esp_rom_spiflash_write = 0x4000011c );\nPROVIDE( _esp_rom_spiflash_read = 0x40000120 );\nPROVIDE( _esp_rom_spiflash_unlock = 0x40000124 );\nPROVIDE( _SPIEraseArea = 0x40000128 );\nPROVIDE( _SPI_write_enable = 0x4000012c );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000134 );\nPROVIDE( esp_rom_spiflash_write = 0x40000138 );\nPROVIDE( esp_rom_spiflash_read = 0x4000013c );\nPROVIDE( esp_rom_spiflash_unlock = 0x40000140 );\nPROVIDE( SPIEraseArea = 0x40000144 );\nPROVIDE( SPI_write_enable = 0x40000148 );\nPROVIDE( esp_rom_spiflash_config_param = 0x4000014c );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c );\nPROVIDE( esp_rom_spi_flash_update_id = 0x40000160 );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000164 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 );\nPROVIDE( esp_rom_spiflash_read_status = 0x4000016c );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000174 );\nPROVIDE( spi_flash_attach = 0x40000178 );\nPROVIDE( spi_flash_get_chip_size = 0x4000017c );\nPROVIDE( spi_flash_guard_set = 0x40000180 );\nPROVIDE( spi_flash_guard_get = 0x40000184 );\nPROVIDE( spi_flash_read_encrypted = 0x40000188 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x4000018c );\nPROVIDE( spi_flash_mmap_page_num_init = 0x40000190 );\nPROVIDE( spi_flash_mmap = 0x40000194 );\nPROVIDE( spi_flash_mmap_pages = 0x40000198 );\nPROVIDE( spi_flash_munmap = 0x4000019c );\nPROVIDE( spi_flash_mmap_dump = 0x400001a0 );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );\nPROVIDE( spi_flash_cache2phys = 0x400001ac );\nPROVIDE( spi_flash_phys2cache = 0x400001b0 );\nPROVIDE( spi_flash_disable_cache = 0x400001b4 );\nPROVIDE( spi_flash_restore_cache = 0x400001b8 );\nPROVIDE( spi_flash_cache_enabled = 0x400001bc );\nPROVIDE( spi_flash_enable_cache = 0x400001c0 );\nPROVIDE( spi_cache_mode_switch = 0x400001c4 );\nPROVIDE( spi_common_set_dummy_output = 0x400001c8 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001cc );\nPROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 );\nPROVIDE( SPILock = 0x400001d8 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001dc );\nPROVIDE( SPI_Common_Command = 0x400001e0 );\nPROVIDE( SPI_WakeUp = 0x400001e4 );\nPROVIDE( SPI_block_erase = 0x400001e8 );\nPROVIDE( SPI_chip_erase = 0x400001ec );\nPROVIDE( SPI_init = 0x400001f0 );\nPROVIDE( SPI_page_program = 0x400001f4 );\nPROVIDE( SPI_read_data = 0x400001f8 );\nPROVIDE( SPI_sector_erase = 0x400001fc );\nPROVIDE( SelectSpiFunction = 0x40000200 );\nPROVIDE( SetSpiDrvs = 0x40000204 );\nPROVIDE( Wait_SPI_Idle = 0x40000208 );\nPROVIDE( spi_dummy_len_fix = 0x4000020c );\nPROVIDE( Disable_QMode = 0x40000210 );\nPROVIDE( Enable_QMode = 0x40000214 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group hal_soc\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 );\nPROVIDE( spi_flash_hal_device_config = 0x4000021c );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 );\nPROVIDE( spi_flash_hal_common_command = 0x40000224 );\nPROVIDE( spi_flash_hal_read = 0x40000228 );\nPROVIDE( spi_flash_hal_erase_chip = 0x4000022c );\nPROVIDE( spi_flash_hal_erase_sector = 0x40000230 );\nPROVIDE( spi_flash_hal_erase_block = 0x40000234 );\nPROVIDE( spi_flash_hal_program_page = 0x40000238 );\nPROVIDE( spi_flash_hal_set_write_protect = 0x4000023c );\nPROVIDE( spi_flash_hal_host_idle = 0x40000240 );\nPROVIDE( spi_flash_hal_check_status = 0x40000244 );\nPROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 );\nPROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c );\nPROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 );\nPROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 );\nPROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 );\nPROVIDE( spi_flash_hal_resume = 0x4000025c );\nPROVIDE( spi_flash_hal_suspend = 0x40000260 );\nPROVIDE( spi_flash_encryption_hal_enable = 0x40000264 );\nPROVIDE( spi_flash_encryption_hal_disable = 0x40000268 );\nPROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c );\nPROVIDE( spi_flash_encryption_hal_done = 0x40000270 );\nPROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 );\nPROVIDE( spi_flash_encryption_hal_check = 0x40000278 );\nPROVIDE( wdt_hal_init = 0x4000027c );\nPROVIDE( wdt_hal_deinit = 0x40000280 );\nPROVIDE( wdt_hal_config_stage = 0x40000284 );\nPROVIDE( wdt_hal_write_protect_disable = 0x40000288 );\nPROVIDE( wdt_hal_write_protect_enable = 0x4000028c );\nPROVIDE( wdt_hal_enable = 0x40000290 );\nPROVIDE( wdt_hal_disable = 0x40000294 );\nPROVIDE( wdt_hal_handle_intr = 0x40000298 );\nPROVIDE( wdt_hal_feed = 0x4000029c );\nPROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 );\nPROVIDE( wdt_hal_is_enabled = 0x400002a4 );\nPROVIDE( systimer_hal_init = 0x400002a8 );\nPROVIDE( systimer_hal_get_counter_value = 0x400002ac );\nPROVIDE( systimer_hal_get_time = 0x400002b0 );\nPROVIDE( systimer_hal_set_alarm_target = 0x400002b4 );\nPROVIDE( systimer_hal_set_alarm_period = 0x400002b8 );\nPROVIDE( systimer_hal_get_alarm_value = 0x400002bc );\nPROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 );\nPROVIDE( systimer_hal_on_apb_freq_update = 0x400002c4 );\nPROVIDE( systimer_hal_counter_value_advance = 0x400002c8 );\nPROVIDE( systimer_hal_enable_counter = 0x400002cc );\nPROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 );\nPROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 );\nPROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 );\n\n\n\/***************************************\n Group heap\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( tlsf_create = 0x400002dc );\nPROVIDE( tlsf_create_with_pool = 0x400002e0 );\nPROVIDE( tlsf_get_pool = 0x400002e4 );\nPROVIDE( tlsf_add_pool = 0x400002e8 );\nPROVIDE( tlsf_remove_pool = 0x400002ec );\nPROVIDE( tlsf_malloc = 0x400002f0 );\nPROVIDE( tlsf_memalign = 0x400002f4 );\nPROVIDE( tlsf_memalign_offs = 0x400002f8 );\nPROVIDE( tlsf_realloc = 0x400002fc );\nPROVIDE( tlsf_free = 0x40000300 );\nPROVIDE( tlsf_block_size = 0x40000304 );\nPROVIDE( tlsf_size = 0x40000308 );\nPROVIDE( tlsf_align_size = 0x4000030c );\nPROVIDE( tlsf_block_size_min = 0x40000310 );\nPROVIDE( tlsf_block_size_max = 0x40000314 );\nPROVIDE( tlsf_pool_overhead = 0x40000318 );\nPROVIDE( tlsf_alloc_overhead = 0x4000031c );\nPROVIDE( tlsf_walk_pool = 0x40000320 );\nPROVIDE( tlsf_check = 0x40000324 );\nPROVIDE( tlsf_check_pool = 0x40000328 );\nPROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c );\nPROVIDE( multi_heap_get_block_address_impl = 0x40000330 );\nPROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 );\nPROVIDE( multi_heap_register_impl = 0x40000338 );\nPROVIDE( multi_heap_set_lock = 0x4000033c );\nPROVIDE( multi_heap_os_funcs_init = 0x40000340 );\nPROVIDE( multi_heap_internal_lock = 0x40000344 );\nPROVIDE( multi_heap_internal_unlock = 0x40000348 );\nPROVIDE( multi_heap_get_first_block = 0x4000034c );\nPROVIDE( multi_heap_get_next_block = 0x40000350 );\nPROVIDE( multi_heap_is_free = 0x40000354 );\nPROVIDE( multi_heap_malloc_impl = 0x40000358 );\nPROVIDE( multi_heap_free_impl = 0x4000035c );\nPROVIDE( multi_heap_realloc_impl = 0x40000360 );\nPROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 );\nPROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 );\nPROVIDE( multi_heap_check = 0x4000036c );\nPROVIDE( multi_heap_dump = 0x40000370 );\nPROVIDE( multi_heap_free_size_impl = 0x40000374 );\nPROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 );\nPROVIDE( multi_heap_get_info_impl = 0x4000037c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x40000380 );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 );\nPROVIDE( spi_flash_chip_generic_write = 0x40000388 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000398 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 );\nPROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 );\nPROVIDE( spi_flash_chip_generic_yield = 0x400003b8 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 );\nPROVIDE( spi_flash_chip_generic_read = 0x400003c8 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc );\nPROVIDE( spi_flash_common_set_io_mode = 0x400003e0 );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 );\nPROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 );\nPROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec );\nPROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400003f8 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );\nPROVIDE( spi_flash_encryption = 0x3fcdffe4 );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x40000400 );\nPROVIDE( memspi_host_read_status_hs = 0x40000404 );\nPROVIDE( memspi_host_flush_cache = 0x40000408 );\nPROVIDE( memspi_host_erase_chip = 0x4000040c );\nPROVIDE( memspi_host_erase_sector = 0x40000410 );\nPROVIDE( memspi_host_erase_block = 0x40000414 );\nPROVIDE( memspi_host_program_page = 0x40000418 );\nPROVIDE( memspi_host_read = 0x4000041c );\nPROVIDE( memspi_host_set_write_protect = 0x40000420 );\nPROVIDE( memspi_host_set_max_read_len = 0x40000424 );\nPROVIDE( memspi_host_read_data_slicer = 0x40000428 );\nPROVIDE( memspi_host_write_data_slicer = 0x4000042c );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x40000430 );\nPROVIDE( esp_flash_read_id = 0x40000434 );\nPROVIDE( esp_flash_get_size = 0x40000438 );\nPROVIDE( esp_flash_erase_chip = 0x4000043c );\nPROVIDE( esp_flash_erase_region = 0x40000440 );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000444 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000448 );\nPROVIDE( esp_flash_get_protectable_regions = 0x4000044c );\nPROVIDE( esp_flash_get_protected_region = 0x40000450 );\nPROVIDE( esp_flash_set_protected_region = 0x40000454 );\nPROVIDE( esp_flash_read = 0x40000458 );\nPROVIDE( esp_flash_write = 0x4000045c );\nPROVIDE( esp_flash_write_encrypted = 0x40000460 );\nPROVIDE( esp_flash_read_encrypted = 0x40000464 );\nPROVIDE( esp_flash_get_io_mode = 0x40000468 );\nPROVIDE( esp_flash_set_io_mode = 0x4000046c );\nPROVIDE( spi_flash_boot_attach = 0x40000470 );\nPROVIDE( esp_flash_read_chip_id = 0x40000474 );\nPROVIDE( detect_spi_flash_chip = 0x40000478 );\nPROVIDE( esp_rom_spiflash_write_disable = 0x4000047c );\nPROVIDE( esp_flash_suspend_cmd_init = 0x40000480 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe0 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffdc );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 );\nPROVIDE( Cache_Get_Mode = 0x400006e4 );\nPROVIDE( Cache_Address_Through_IBus = 0x400006e8 );\nPROVIDE( Cache_Address_Through_DBus = 0x400006ec );\nPROVIDE( Cache_Set_Default_Mode = 0x400006f0 );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400006f8 );\nPROVIDE( MMU_Set_Page_Mode = 0x400006fc );\nPROVIDE( MMU_Get_Page_Mode = 0x40000700 );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x40000704 );\nPROVIDE( Cache_Op_Addr = 0x40000708 );\nPROVIDE( Cache_Invalidate_Addr = 0x4000070c );\nPROVIDE( Cache_Invalidate_ICache_All = 0x40000710 );\nPROVIDE( Cache_Mask_All = 0x40000714 );\nPROVIDE( Cache_UnMask_Dram0 = 0x40000718 );\nPROVIDE( Cache_Disable_ICache = 0x4000071c );\nPROVIDE( Cache_Enable_ICache = 0x40000720 );\nPROVIDE( Cache_Suspend_ICache = 0x40000724 );\nPROVIDE( Cache_Resume_ICache = 0x40000728 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x4000072c );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x40000730 );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000734 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x40000738 );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x4000073c );\nPROVIDE( Cache_Owner_Init = 0x40000740 );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000744 );\nPROVIDE( Cache_MMU_Init = 0x40000748 );\nPROVIDE( Cache_Ibus_MMU_Set = 0x4000074c );\nPROVIDE( Cache_Dbus_MMU_Set = 0x40000750 );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000754 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x40000758 );\nPROVIDE( Cache_Get_Virtual_Addr = 0x4000075c );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x40000760 );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000764 );\nPROVIDE( Cache_Get_Memory_value = 0x40000768 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd0 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x4000076c;\nets_get_cpu_frequency = 0x40000770;\nets_update_cpu_frequency = 0x40000774;\nets_get_printf_channel = 0x40000778;\nets_get_xtal_div = 0x4000077c;\nets_set_xtal_div = 0x40000780;\nets_get_xtal_freq = 0x40000784;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x40000788;\ngpio_matrix_in = 0x4000078c;\ngpio_matrix_out = 0x40000790;\ngpio_output_disable = 0x40000794;\ngpio_output_enable = 0x40000798;\ngpio_output_set = 0x4000079c;\ngpio_pad_hold = 0x400007a0;\ngpio_pad_input_disable = 0x400007a4;\ngpio_pad_input_enable = 0x400007a8;\ngpio_pad_pulldown = 0x400007ac;\ngpio_pad_pullup = 0x400007b0;\ngpio_pad_select_gpio = 0x400007b4;\ngpio_pad_set_drv = 0x400007b8;\ngpio_pad_unhold = 0x400007bc;\ngpio_pin_wakeup_disable = 0x400007c0;\ngpio_pin_wakeup_enable = 0x400007c4;\ngpio_bypass_matrix_in = 0x400007c8;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400007cc;\nesprv_intc_int_set_threshold = 0x400007d0;\nesprv_intc_int_enable = 0x400007d4;\nesprv_intc_int_disable = 0x400007d8;\nesprv_intc_int_set_type = 0x400007dc;\nPROVIDE( intr_handler_set = 0x400007e0 );\nintr_matrix_set = 0x400007e4;\nets_intr_lock = 0x400007e8;\nets_intr_unlock = 0x400007ec;\nets_isr_attach = 0x400007f0;\nets_isr_mask = 0x400007f4;\nets_isr_unmask = 0x400007f8;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\ncrc32_le = 0x400007fc;\ncrc16_le = 0x40000800;\ncrc8_le = 0x40000804;\ncrc32_be = 0x40000808;\ncrc16_be = 0x4000080c;\ncrc8_be = 0x40000810;\nesp_crc8 = 0x40000814;\nets_sha_enable = 0x40000818;\nets_sha_disable = 0x4000081c;\nets_sha_get_state = 0x40000820;\nets_sha_init = 0x40000824;\nets_sha_process = 0x40000828;\nets_sha_starts = 0x4000082c;\nets_sha_update = 0x40000830;\nets_sha_finish = 0x40000834;\nets_sha_clone = 0x40000838;\n\/* Data (.data, .bss, .rodata) *\/\ncrc32_le_table_ptr = 0x3ff4fff8;\ncrc16_le_table_ptr = 0x3ff4fff4;\ncrc8_le_table_ptr = 0x3ff4fff0;\ncrc32_be_table_ptr = 0x3ff4ffec;\ncrc16_be_table_ptr = 0x3ff4ffe8;\ncrc8_be_table_ptr = 0x3ff4ffe4;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x4000083c;\nets_efuse_program = 0x40000840;\nets_efuse_clear_program_registers = 0x40000844;\nets_efuse_write_key = 0x40000848;\nets_efuse_get_read_register_address = 0x4000084c;\nets_efuse_get_key_purpose = 0x40000850;\nets_efuse_key_block_unused = 0x40000854;\nets_efuse_find_unused_key_block = 0x40000858;\nets_efuse_rs_calculate = 0x4000085c;\nets_efuse_count_unused_key_blocks = 0x40000860;\nets_efuse_secure_boot_enabled = 0x40000864;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000868;\nets_efuse_cache_encryption_enabled = 0x4000086c;\nets_efuse_download_modes_disabled = 0x40000870;\nets_efuse_find_purpose = 0x40000874;\nets_efuse_force_send_resume = 0x40000878;\nets_efuse_get_flash_delay_us = 0x4000087c;\nets_efuse_get_mac = 0x40000880;\nets_efuse_get_uart_print_control = 0x40000884;\nets_efuse_direct_boot_mode_disabled = 0x40000888;\nets_efuse_security_download_modes_enabled = 0x4000088c;\nets_efuse_set_timing = 0x40000890;\nets_efuse_jtag_disabled = 0x40000894;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_ecdsa_verify = 0x40000898;\nets_secure_boot_verify_bootloader_with_keys = 0x4000089c;\nets_secure_boot_verify_signature = 0x400008a0;\nets_secure_boot_read_key_digests = 0x400008a4;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Data (.data, .bss, .rodata) *\/\ng_uart_print = 0x3fcdffc9;\ng_usb_print = 0x3fcdffc8;\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nble_controller_rom_data_init = 0x40000aa8;\nble_osi_coex_funcs_register = 0x40000aac;\nbt_rf_coex_cfg_get_default = 0x40000ab0;\nbt_rf_coex_dft_pti_get_default = 0x40000ab4;\nbt_rf_coex_hooks_p_set = 0x40000ab8;\nr__os_mbuf_copypkthdr = 0x40000abc;\nr__os_msys_find_pool = 0x40000ac0;\nr_ble_controller_get_rom_compile_version = 0x40000ac4;\nr_ble_hci_ram_hs_acl_tx = 0x40000ac8;\nr_ble_hci_ram_hs_cmd_tx = 0x40000acc;\nr_ble_hci_ram_ll_acl_tx = 0x40000ad0;\nr_ble_hci_ram_ll_evt_tx = 0x40000ad4;\nr_ble_hci_ram_reset = 0x40000ad8;\nr_ble_hci_ram_set_acl_free_cb = 0x40000adc;\nr_ble_hci_trans_acl_buf_alloc = 0x40000ae0;\nr_ble_hci_trans_buf_alloc = 0x40000ae4;\nr_ble_hci_trans_buf_free = 0x40000ae8;\nr_ble_hci_trans_cfg_hs = 0x40000aec;\nr_ble_hci_trans_cfg_ll = 0x40000af0;\nr_ble_hci_trans_deinit = 0x40000af4;\nr_ble_hci_trans_env_init = 0x40000af8;\nr_ble_hci_trans_init = 0x40000afc;\nr_ble_hci_uart_acl_tx = 0x40000b00;\nr_ble_hci_uart_cmdevt_tx = 0x40000b04;\nr_ble_hci_uart_config = 0x40000b08;\nr_ble_hci_uart_free_pkt = 0x40000b0c;\nr_ble_hci_uart_hs_acl_tx = 0x40000b10;\nr_ble_hci_uart_hs_cmd_tx = 0x40000b14;\nr_ble_hci_uart_ll_acl_tx = 0x40000b18;\nr_ble_hci_uart_ll_evt_tx = 0x40000b1c;\nr_ble_hci_uart_rx_acl = 0x40000b20;\nr_ble_hci_uart_rx_char = 0x40000b24;\nr_ble_hci_uart_rx_cmd = 0x40000b28;\nr_ble_hci_uart_rx_evt = 0x40000b2c;\nr_ble_hci_uart_rx_evt_cb = 0x40000b30;\nr_ble_hci_uart_rx_le_evt = 0x40000b34;\nr_ble_hci_uart_rx_pkt_type = 0x40000b38;\nr_ble_hci_uart_rx_skip_acl = 0x40000b3c;\nr_ble_hci_uart_rx_skip_cmd = 0x40000b40;\nr_ble_hci_uart_rx_skip_evt = 0x40000b44;\nr_ble_hci_uart_rx_sync_loss = 0x40000b48;\nr_ble_hci_uart_set_acl_free_cb = 0x40000b4c;\nr_ble_hci_uart_sync_lost = 0x40000b50;\nr_ble_hci_uart_trans_reset = 0x40000b54;\nr_ble_hci_uart_tx_char = 0x40000b58;\nr_ble_hci_uart_tx_pkt_type = 0x40000b5c;\nr_ble_hw_driver_deinit = 0x40000b60;\nr_ble_hw_driver_env_init = 0x40000b64;\nr_ble_hw_encrypt_block = 0x40000b68;\nr_ble_hw_get_public_addr = 0x40000b6c;\nr_ble_hw_get_static_addr = 0x40000b70;\nr_ble_hw_periodiclist_add = 0x40000b74;\nr_ble_hw_periodiclist_clear = 0x40000b78;\nr_ble_hw_periodiclist_rmv = 0x40000b7c;\nr_ble_hw_resolv_list_cur_entry = 0x40000b80;\nr_ble_hw_resolv_list_set = 0x40000b88;\nr_ble_hw_rng_init = 0x40000b8c;\nr_ble_hw_rng_start = 0x40000b90;\nr_ble_hw_rng_stop = 0x40000b94;\nr_ble_hw_rx_local_is_resolved = 0x40000b98;\nr_ble_hw_rx_local_is_rpa = 0x40000b9c;\nr_ble_hw_whitelist_add = 0x40000ba0;\nr_ble_hw_whitelist_clear = 0x40000ba4;\nr_ble_hw_whitelist_dev_num = 0x40000ba8;\nr_ble_hw_whitelist_get_base = 0x40000bac;\nr_ble_hw_whitelist_rmv = 0x40000bb0;\nr_ble_hw_whitelist_search = 0x40000bb4;\nr_ble_hw_whitelist_sort = 0x40000bb8;\nr_ble_ll_acl_data_in = 0x40000bbc;\nr_ble_ll_addr_is_id = 0x40000bc0;\nr_ble_ll_addr_subtype = 0x40000bc4;\nr_ble_ll_adv_active_chanset_clear = 0x40000bc8;\nr_ble_ll_adv_active_chanset_is_pri = 0x40000bcc;\nr_ble_ll_adv_active_chanset_is_sec = 0x40000bd0;\nr_ble_ll_adv_active_chanset_set_pri = 0x40000bd4;\nr_ble_ll_adv_active_chanset_set_sec = 0x40000bd8;\nr_ble_ll_adv_aux_calculate = 0x40000bdc;\nr_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000be0;\nr_ble_ll_adv_aux_pdu_make = 0x40000be4;\nr_ble_ll_adv_aux_scannable_pdu_make = 0x40000be8;\nr_ble_ll_adv_aux_txed = 0x40000bec;\nr_ble_ll_adv_can_chg_whitelist = 0x40000bf0;\nr_ble_ll_adv_chk_rpa_timeout = 0x40000bf4;\nr_ble_ll_adv_clear_all = 0x40000bf8;\nr_ble_ll_adv_conn_req_rxd = 0x40000bfc;\nr_ble_ll_adv_deinit = 0x40000c00;\nr_ble_ll_adv_enabled = 0x40000c04;\nr_ble_ll_adv_env_init = 0x40000c08;\nr_ble_ll_adv_ext_set_adv_data = 0x40000c0c;\nr_ble_ll_adv_ext_set_enable = 0x40000c10;\nr_ble_ll_adv_ext_set_param = 0x40000c14;\nr_ble_ll_adv_ext_set_scan_rsp = 0x40000c18;\nr_ble_ll_adv_final_chan = 0x40000c1c;\nr_ble_ll_adv_first_chan = 0x40000c20;\nr_ble_ll_adv_flags_clear = 0x40000c24;\nr_ble_ll_adv_flags_set = 0x40000c28;\nr_ble_ll_adv_get_chan_num = 0x40000c2c;\nr_ble_ll_adv_get_local_rpa = 0x40000c30;\nr_ble_ll_adv_get_peer_rpa = 0x40000c34;\nr_ble_ll_adv_hci_set_random_addr = 0x40000c38;\nr_ble_ll_adv_init = 0x40000c3c;\nr_ble_ll_adv_legacy_pdu_make = 0x40000c40;\nr_ble_ll_adv_next_chan = 0x40000c44;\nr_ble_ll_adv_pdu_make = 0x40000c48;\nr_ble_ll_adv_periodic_check_data_itvl = 0x40000c4c;\nr_ble_ll_adv_periodic_enable = 0x40000c50;\nr_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c54;\nr_ble_ll_adv_periodic_send_sync_ind = 0x40000c58;\nr_ble_ll_adv_periodic_set_data = 0x40000c5c;\nr_ble_ll_adv_periodic_set_info_transfer = 0x40000c60;\nr_ble_ll_adv_periodic_set_param = 0x40000c64;\nr_ble_ll_adv_pre_process = 0x40000c68;\nr_ble_ll_adv_put_acad_chM_update_ind = 0x40000c6c;\nr_ble_ll_adv_put_aux_ptr = 0x40000c70;\nr_ble_ll_adv_put_syncinfo = 0x40000c74;\nr_ble_ll_adv_rd_max_adv_data_len = 0x40000c78;\nr_ble_ll_adv_rd_sup_adv_sets = 0x40000c7c;\nr_ble_ll_adv_read_txpwr = 0x40000c80;\nr_ble_ll_adv_remove = 0x40000c84;\nr_ble_ll_adv_reset = 0x40000c88;\nr_ble_ll_adv_rpa_timeout = 0x40000c8c;\nr_ble_ll_adv_rpa_update = 0x40000c90;\nr_ble_ll_adv_rx_pkt_in = 0x40000c94;\nr_ble_ll_adv_scan_req_rxd = 0x40000c98;\nr_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c;\nr_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0;\nr_ble_ll_adv_scheduled = 0x40000ca4;\nr_ble_ll_adv_send_conn_comp_ev = 0x40000ca8;\nr_ble_ll_adv_set_adv_data = 0x40000cac;\nr_ble_ll_adv_set_adv_params = 0x40000cb0;\nr_ble_ll_adv_set_enable = 0x40000cb4;\nr_ble_ll_adv_set_random_addr = 0x40000cb8;\nr_ble_ll_adv_set_scan_rsp_data = 0x40000cbc;\nr_ble_ll_adv_set_sched = 0x40000cc0;\nr_ble_ll_adv_sm_deinit = 0x40000cc4;\nr_ble_ll_adv_sm_event_init = 0x40000cc8;\nr_ble_ll_adv_sm_find_configured = 0x40000ccc;\nr_ble_ll_adv_sm_get = 0x40000cd0;\nr_ble_ll_adv_sm_init = 0x40000cd4;\nr_ble_ll_adv_sm_reset = 0x40000cd8;\nr_ble_ll_adv_sm_start = 0x40000cdc;\nr_ble_ll_adv_sm_start_periodic = 0x40000ce0;\nr_ble_ll_adv_sm_stop = 0x40000ce4;\nr_ble_ll_adv_sm_stop_limit_reached = 0x40000ce8;\nr_ble_ll_adv_sm_stop_periodic = 0x40000cec;\nr_ble_ll_adv_sm_stop_timeout = 0x40000cf0;\nr_ble_ll_adv_sync_calculate = 0x40000cf4;\nr_ble_ll_adv_sync_get_pdu_len = 0x40000cf8;\nr_ble_ll_adv_sync_pdu_make = 0x40000cfc;\nr_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d00;\nr_ble_ll_adv_update_data_mbuf = 0x40000d04;\nr_ble_ll_adv_update_did = 0x40000d08;\nr_ble_ll_adv_update_periodic_data = 0x40000d0c;\nr_ble_ll_arr_pool_init = 0x40000d10;\nr_ble_ll_auth_pyld_tmo_event_send = 0x40000d14;\nr_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d18;\nr_ble_ll_calc_session_key = 0x40000d1c;\nr_ble_ll_calc_ticks_per_slot = 0x40000d20;\nr_ble_ll_check_scan_params = 0x40000d24;\nr_ble_ll_chk_txrx_octets = 0x40000d28;\nr_ble_ll_chk_txrx_time = 0x40000d2c;\nr_ble_ll_conn_adjust_pyld_len = 0x40000d30;\nr_ble_ll_conn_auth_pyld_timer_cb = 0x40000d34;\nr_ble_ll_conn_auth_pyld_timer_start = 0x40000d38;\nr_ble_ll_conn_calc_dci = 0x40000d3c;\nr_ble_ll_conn_calc_dci_csa1 = 0x40000d40;\nr_ble_ll_conn_calc_itvl_ticks = 0x40000d44;\nr_ble_ll_conn_chk_csm_flags = 0x40000d48;\nr_ble_ll_conn_chk_phy_upd_start = 0x40000d4c;\nr_ble_ll_conn_comp_event_send = 0x40000d50;\nr_ble_ll_conn_connect_ind_pdu_make = 0x40000d54;\nr_ble_ll_conn_create = 0x40000d58;\nr_ble_ll_conn_create_cancel = 0x40000d5c;\nr_ble_ll_conn_created = 0x40000d60;\nr_ble_ll_conn_cth_flow_enable = 0x40000d64;\nr_ble_ll_conn_cth_flow_error_fn = 0x40000d68;\nr_ble_ll_conn_cth_flow_have_credit = 0x40000d6c;\nr_ble_ll_conn_cth_flow_is_enabled = 0x40000d70;\nr_ble_ll_conn_cth_flow_process_cmd = 0x40000d74;\nr_ble_ll_conn_cth_flow_set_buffers = 0x40000d78;\nr_ble_ll_conn_enqueue_pkt = 0x40000d7c;\nr_ble_ll_conn_env_init = 0x40000d80;\nr_ble_ll_conn_ext_master_init = 0x40000d84;\nr_ble_ll_conn_find_active_conn = 0x40000d88;\nr_ble_ll_conn_get_active_conn = 0x40000d8c;\nr_ble_ll_conn_get_anchor = 0x40000d90;\nr_ble_ll_conn_hcc_params_set_fallback = 0x40000d94;\nr_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000d98;\nr_ble_ll_conn_hci_chk_conn_params = 0x40000d9c;\nr_ble_ll_conn_hci_chk_scan_params = 0x40000da0;\nr_ble_ll_conn_hci_disconnect_cmd = 0x40000da4;\nr_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000da8;\nr_ble_ll_conn_hci_le_ltk_reply = 0x40000dac;\nr_ble_ll_conn_hci_le_rd_phy = 0x40000db0;\nr_ble_ll_conn_hci_le_set_phy = 0x40000db4;\nr_ble_ll_conn_hci_le_start_encrypt = 0x40000db8;\nr_ble_ll_conn_hci_param_nrr = 0x40000dbc;\nr_ble_ll_conn_hci_param_rr = 0x40000dc0;\nr_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000dc4;\nr_ble_ll_conn_hci_rd_chan_map = 0x40000dc8;\nr_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000dcc;\nr_ble_ll_conn_hci_rd_rssi = 0x40000dd0;\nr_ble_ll_conn_hci_read_rem_features = 0x40000dd4;\nr_ble_ll_conn_hci_set_chan_class = 0x40000dd8;\nr_ble_ll_conn_hci_set_data_len = 0x40000ddc;\nr_ble_ll_conn_hci_update = 0x40000de0;\nr_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000de4;\nr_ble_ll_conn_init_phy = 0x40000de8;\nr_ble_ll_conn_is_empty_pdu = 0x40000df0;\nr_ble_ll_conn_is_lru = 0x40000df4;\nr_ble_ll_conn_master_init = 0x40000df8;\nr_ble_ll_conn_module_deinit = 0x40000dfc;\nr_ble_ll_conn_module_init = 0x40000e00;\nr_ble_ll_conn_module_reset = 0x40000e04;\nr_ble_ll_conn_next_event = 0x40000e08;\nr_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c;\nr_ble_ll_conn_prepare_tx_pdu = 0x40000e10;\nr_ble_ll_conn_process_conn_params = 0x40000e14;\nr_ble_ll_conn_req_peer_sca = 0x40000e18;\nr_ble_ll_conn_rx_data_pdu = 0x40000e1c;\nr_ble_ll_conn_set_csa = 0x40000e20;\nr_ble_ll_conn_set_ext_con_params = 0x40000e24;\nr_ble_ll_conn_set_global_chanmap = 0x40000e28;\nr_ble_ll_conn_set_phy = 0x40000e2c;\nr_ble_ll_conn_set_txpwr_by_handle = 0x40000e30;\nr_ble_ll_conn_set_unknown_rx_octets = 0x40000e34;\nr_ble_ll_conn_slave_start = 0x40000e38;\nr_ble_ll_conn_sm_get = 0x40000e3c;\nr_ble_ll_conn_sm_new = 0x40000e40;\nr_ble_ll_conn_sm_npl_deinit = 0x40000e44;\nr_ble_ll_conn_sm_npl_init = 0x40000e48;\nr_ble_ll_conn_tx_pkt_in = 0x40000e4c;\nr_ble_ll_conn_update_eff_data_len = 0x40000e50;\nr_ble_ll_ctrl_chanmap_req_make = 0x40000e54;\nr_ble_ll_ctrl_chk_proc_start = 0x40000e58;\nr_ble_ll_ctrl_conn_param_pdu_make = 0x40000e5c;\nr_ble_ll_ctrl_conn_param_pdu_proc = 0x40000e60;\nr_ble_ll_ctrl_conn_param_reply = 0x40000e64;\nr_ble_ll_ctrl_conn_upd_make = 0x40000e68;\nr_ble_ll_ctrl_datalen_upd_make = 0x40000e6c;\nr_ble_ll_ctrl_enc_allowed_pdu = 0x40000e70;\nr_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000e74;\nr_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40000e78;\nr_ble_ll_ctrl_enc_req_make = 0x40000e7c;\nr_ble_ll_ctrl_find_new_phy = 0x40000e80;\nr_ble_ll_ctrl_initiate_dle = 0x40000e84;\nr_ble_ll_ctrl_len_proc = 0x40000e88;\nr_ble_ll_ctrl_min_used_chan_rsp = 0x40000e8c;\nr_ble_ll_ctrl_phy_from_phy_mask = 0x40000e90;\nr_ble_ll_ctrl_phy_req_rsp_make = 0x40000e94;\nr_ble_ll_ctrl_phy_tx_transition_get = 0x40000e98;\nr_ble_ll_ctrl_phy_update_cancel = 0x40000e9c;\nr_ble_ll_ctrl_phy_update_ind_make = 0x40000ea0;\nr_ble_ll_ctrl_phy_update_proc_complete = 0x40000ea4;\nr_ble_ll_ctrl_proc_init = 0x40000ea8;\nr_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000eac;\nr_ble_ll_ctrl_proc_start = 0x40000eb0;\nr_ble_ll_ctrl_proc_stop = 0x40000eb4;\nr_ble_ll_ctrl_proc_unk_rsp = 0x40000eb8;\nr_ble_ll_ctrl_proc_with_instant_initiated = 0x40000ebc;\nr_ble_ll_ctrl_rej_ext_ind_make = 0x40000ec0;\nr_ble_ll_ctrl_reject_ind_send = 0x40000ec4;\nr_ble_ll_ctrl_rx_chanmap_req = 0x40000ec8;\nr_ble_ll_ctrl_rx_conn_param_req = 0x40000ecc;\nr_ble_ll_ctrl_rx_conn_param_rsp = 0x40000ed0;\nr_ble_ll_ctrl_rx_conn_update = 0x40000ed4;\nr_ble_ll_ctrl_rx_enc_req = 0x40000ed8;\nr_ble_ll_ctrl_rx_enc_rsp = 0x40000edc;\nr_ble_ll_ctrl_rx_feature_req = 0x40000ee0;\nr_ble_ll_ctrl_rx_feature_rsp = 0x40000ee4;\nr_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8;\nr_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec;\nr_ble_ll_ctrl_rx_pdu = 0x40000ef0;\nr_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4;\nr_ble_ll_ctrl_rx_phy_req = 0x40000ef8;\nr_ble_ll_ctrl_rx_phy_rsp = 0x40000efc;\nr_ble_ll_ctrl_rx_phy_update_ind = 0x40000f00;\nr_ble_ll_ctrl_rx_ping_rsp = 0x40000f04;\nr_ble_ll_ctrl_rx_reject_ind = 0x40000f08;\nr_ble_ll_ctrl_rx_sca_req = 0x40000f0c;\nr_ble_ll_ctrl_rx_sca_rsp = 0x40000f10;\nr_ble_ll_ctrl_rx_start_enc_req = 0x40000f14;\nr_ble_ll_ctrl_rx_start_enc_rsp = 0x40000f18;\nr_ble_ll_ctrl_rx_version_ind = 0x40000f1c;\nr_ble_ll_ctrl_sca_req_rsp_make = 0x40000f20;\nr_ble_ll_ctrl_start_enc_send = 0x40000f24;\nr_ble_ll_ctrl_start_rsp_timer = 0x40000f28;\nr_ble_ll_ctrl_terminate_start = 0x40000f2c;\nr_ble_ll_ctrl_tx_done = 0x40000f30;\nr_ble_ll_ctrl_update_features = 0x40000f34;\nr_ble_ll_ctrl_version_ind_make = 0x40000f38;\nr_ble_ll_data_buffer_overflow = 0x40000f3c;\nr_ble_ll_deinit = 0x40000f40;\nr_ble_ll_disconn_comp_event_send = 0x40000f44;\nr_ble_ll_env_init = 0x40000f48;\nr_ble_ll_event_comp_pkts = 0x40000f4c;\nr_ble_ll_event_dbuf_overflow = 0x40000f50;\nr_ble_ll_event_send = 0x40000f54;\nr_ble_ll_event_tx_pkt = 0x40000f58;\nr_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40000f5c;\nr_ble_ll_ext_conn_create = 0x40000f60;\nr_ble_ll_ext_scan_parse_adv_info = 0x40000f64;\nr_ble_ll_ext_scan_parse_aux_ptr = 0x40000f68;\nr_ble_ll_flush_pkt_queue = 0x40000f6c;\nr_ble_ll_generate_dh_key_v1 = 0x40000f70;\nr_ble_ll_generate_dh_key_v2 = 0x40000f74;\nr_ble_ll_generic_data_init = 0x40000f78;\nr_ble_ll_get_addr_type = 0x40000f7c;\nr_ble_ll_get_chan_to_scan = 0x40000f80;\nr_ble_ll_get_our_devaddr = 0x40000f84;\nr_ble_ll_get_tx_pwr_compensation = 0x40000f88;\nr_ble_ll_hci_acl_rx = 0x40000f8c;\nr_ble_ll_hci_adv_mode_ext = 0x40000f90;\nr_ble_ll_hci_adv_set_enable = 0x40000f94;\nr_ble_ll_hci_cb_host_buf_size = 0x40000f98;\nr_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x40000f9c;\nr_ble_ll_hci_cb_set_event_mask = 0x40000fa0;\nr_ble_ll_hci_cb_set_event_mask2 = 0x40000fa4;\nr_ble_ll_hci_chk_phy_masks = 0x40000fa8;\nr_ble_ll_hci_cmd_proc = 0x40000fac;\nr_ble_ll_hci_cmd_rx = 0x40000fb0;\nr_ble_ll_hci_ctlr_bb_cmd_proc = 0x40000fb4;\nr_ble_ll_hci_deinit = 0x40000fb8;\nr_ble_ll_hci_disconnect = 0x40000fbc;\nr_ble_ll_hci_env_init = 0x40000fc0;\nr_ble_ll_hci_ev_conn_update = 0x40000fc4;\nr_ble_ll_hci_ev_databuf_overflow = 0x40000fc8;\nr_ble_ll_hci_ev_datalen_chg = 0x40000fcc;\nr_ble_ll_hci_ev_encrypt_chg = 0x40000fd0;\nr_ble_ll_hci_ev_hw_err = 0x40000fd4;\nr_ble_ll_hci_ev_le_csa = 0x40000fd8;\nr_ble_ll_hci_ev_ltk_req = 0x40000fdc;\nr_ble_ll_hci_ev_phy_update = 0x40000fe0;\nr_ble_ll_hci_ev_rd_rem_used_feat = 0x40000fe4;\nr_ble_ll_hci_ev_rd_rem_ver = 0x40000fe8;\nr_ble_ll_hci_ev_rem_conn_parm_req = 0x40000fec;\nr_ble_ll_hci_ev_sca_update = 0x40000ff0;\nr_ble_ll_hci_ev_send_adv_set_terminated = 0x40000ff4;\nr_ble_ll_hci_ev_send_scan_req_recv = 0x40000ff8;\nr_ble_ll_hci_ev_send_scan_timeout = 0x40000ffc;\nr_ble_ll_hci_ev_send_vendor_err = 0x40001000;\nr_ble_ll_hci_event_send = 0x40001004;\nr_ble_ll_hci_ext_scan_set_enable = 0x40001008;\nr_ble_ll_hci_get_num_cmd_pkts = 0x4000100c;\nr_ble_ll_hci_info_params_cmd_proc = 0x40001010;\nr_ble_ll_hci_init = 0x40001014;\nr_ble_ll_hci_init_support_cmd_base_on_lmp_ver = 0x40001018;\nr_ble_ll_hci_is_event_enabled = 0x4000101c;\nr_ble_ll_hci_is_le_event_enabled = 0x40001020;\nr_ble_ll_hci_le_cmd_proc = 0x40001024;\nr_ble_ll_hci_le_cmd_send_cmd_status = 0x40001028;\nr_ble_ll_hci_le_encrypt = 0x4000102c;\nr_ble_ll_hci_le_rand = 0x40001030;\nr_ble_ll_hci_le_rd_max_data_len = 0x40001034;\nr_ble_ll_hci_le_rd_sugg_data_len = 0x40001038;\nr_ble_ll_hci_le_read_bufsize = 0x4000103c;\nr_ble_ll_hci_le_read_local_features = 0x40001040;\nr_ble_ll_hci_le_read_supp_states = 0x40001044;\nr_ble_ll_hci_le_set_def_phy = 0x40001048;\nr_ble_ll_hci_le_wr_sugg_data_len = 0x4000104c;\nr_ble_ll_hci_link_ctrl_cmd_proc = 0x40001050;\nr_ble_ll_hci_npl_init = 0x40001054;\nr_ble_ll_hci_post_gen_dhkey_cmp_evt = 0x40001058;\nr_ble_ll_hci_post_rd_p256_pubkey_cmp_evt = 0x4000105c;\nr_ble_ll_hci_rd_bd_addr = 0x40001060;\nr_ble_ll_hci_rd_local_supp_cmd = 0x40001064;\nr_ble_ll_hci_rd_local_supp_feat = 0x40001068;\nr_ble_ll_hci_rd_local_version = 0x4000106c;\nr_ble_ll_hci_scan_set_enable = 0x40001070;\nr_ble_ll_hci_send_adv_report = 0x40001074;\nr_ble_ll_hci_send_dir_adv_report = 0x40001078;\nr_ble_ll_hci_send_ext_adv_report = 0x4000107c;\nr_ble_ll_hci_send_legacy_ext_adv_report = 0x40001080;\nr_ble_ll_hci_send_noop = 0x40001084;\nr_ble_ll_hci_set_adv_data = 0x40001088;\nr_ble_ll_hci_set_le_event_mask = 0x4000108c;\nr_ble_ll_hci_set_scan_rsp_data = 0x40001090;\nr_ble_ll_hci_status_params_cmd_proc = 0x40001094;\nr_ble_ll_hci_vs_cmd_proc = 0x40001098;\nr_ble_ll_hci_vs_rd_static_addr = 0x4000109c;\nr_ble_ll_hw_err_timer_cb = 0x400010a0;\nr_ble_ll_hw_error = 0x400010a4;\nr_ble_ll_init = 0x400010a8;\nr_ble_ll_init_alloc_conn_comp_ev = 0x400010ac;\nr_ble_ll_init_get_conn_comp_ev = 0x400010b0;\nr_ble_ll_init_rx_pkt_in = 0x400010b4;\nr_ble_ll_is_addr_empty = 0x400010b8;\nr_ble_ll_is_controller_busy = 0x400010bc;\nr_ble_ll_is_on_resolv_list = 0x400010c0;\nr_ble_ll_is_our_devaddr = 0x400010c4;\nr_ble_ll_is_rpa = 0x400010c8;\nr_ble_ll_is_valid_adv_mode = 0x400010cc;\nr_ble_ll_is_valid_own_addr_type = 0x400010d0;\nr_ble_ll_is_valid_public_addr = 0x400010d4;\nr_ble_ll_is_valid_random_addr = 0x400010d8;\nr_ble_ll_mbuf_init = 0x400010dc;\nr_ble_ll_misc_options_set = 0x400010e0;\nr_ble_ll_modify_sca = 0x400010e4;\nr_ble_ll_modify_sca_action = 0x400010e8;\nr_ble_ll_pdu_max_tx_octets_get = 0x400010ec;\nr_ble_ll_pdu_tx_time_get = 0x400010f0;\nr_ble_ll_phy_to_phy_mode = 0x400010f4;\nr_ble_ll_qa_enable = 0x400010f8;\nr_ble_ll_rand = 0x400010fc;\nr_ble_ll_rand_data_get = 0x40001100;\nr_ble_ll_rand_deinit = 0x40001104;\nr_ble_ll_rand_env_init = 0x40001108;\nr_ble_ll_rand_init = 0x4000110c;\nr_ble_ll_rand_prand_get = 0x40001110;\nr_ble_ll_rand_sample = 0x40001114;\nr_ble_ll_rand_start = 0x40001118;\nr_ble_ll_read_local_p256_pub_key = 0x4000111c;\nr_ble_ll_read_rf_path_compensation = 0x40001120;\nr_ble_ll_read_supp_features = 0x40001124;\nr_ble_ll_read_supp_states = 0x40001128;\nr_ble_ll_read_tx_power = 0x4000112c;\nr_ble_ll_reset = 0x40001130;\nr_ble_ll_resolv_clear_all_pl_bit = 0x40001134;\nr_ble_ll_resolv_clear_all_wl_bit = 0x40001138;\nr_ble_ll_resolv_deinit = 0x4000113c;\nr_ble_ll_resolv_enable_cmd = 0x40001140;\nr_ble_ll_resolv_enabled = 0x40001144;\nr_ble_ll_resolv_env_init = 0x40001148;\nr_ble_ll_resolv_gen_priv_addr = 0x4000114c;\nr_ble_ll_resolv_gen_rpa = 0x40001150;\nr_ble_ll_resolv_get_addr_pointer = 0x40001154;\nr_ble_ll_resolv_get_index = 0x40001158;\nr_ble_ll_resolv_get_irk_pointer = 0x4000115c;\nr_ble_ll_resolv_get_list = 0x40001160;\nr_ble_ll_resolv_get_priv_addr = 0x40001164;\nr_ble_ll_resolv_get_rpa_tmo = 0x40001168;\nr_ble_ll_resolv_init = 0x4000116c;\nr_ble_ll_resolv_irk_nonzero = 0x40001170;\nr_ble_ll_resolv_list_add = 0x40001174;\nr_ble_ll_resolv_list_chg_allowed = 0x40001178;\nr_ble_ll_resolv_list_clr = 0x4000117c;\nr_ble_ll_resolv_list_find = 0x40001180;\nr_ble_ll_resolv_list_read_size = 0x40001184;\nr_ble_ll_resolv_list_reset = 0x40001188;\nr_ble_ll_resolv_list_rmv = 0x4000118c;\nr_ble_ll_resolv_local_addr_rd = 0x40001190;\nr_ble_ll_resolv_peer_addr_rd = 0x40001194;\nr_ble_ll_resolv_peer_rpa_any = 0x40001198;\nr_ble_ll_resolv_reset = 0x4000119c;\nr_ble_ll_resolv_rpa = 0x400011a0;\nr_ble_ll_resolv_rpa_timer_cb = 0x400011a4;\nr_ble_ll_resolv_set_local_rpa = 0x400011a8;\nr_ble_ll_resolv_set_peer_rpa = 0x400011ac;\nr_ble_ll_resolv_set_rpa_tmo = 0x400011b0;\nr_ble_ll_resolve_set_priv_mode = 0x400011b4;\nr_ble_ll_rxpdu_alloc = 0x400011b8;\nr_ble_ll_scan_add_scan_rsp_adv = 0x400011bc;\nr_ble_ll_scan_adv_decode_addr = 0x400011c0;\nr_ble_ll_scan_aux_data_ref = 0x400011c4;\nr_ble_ll_scan_aux_data_unref = 0x400011c8;\nr_ble_ll_scan_can_chg_whitelist = 0x400011cc;\nr_ble_ll_scan_check_periodic_sync = 0x400011d0;\nr_ble_ll_scan_classify_filter_aux_init = 0x400011d4;\nr_ble_ll_scan_classify_filter_init = 0x400011d8;\nr_ble_ll_scan_common_init = 0x400011dc;\nr_ble_ll_scan_continue_en = 0x400011e0;\nr_ble_ll_scan_deinit = 0x400011e4;\nr_ble_ll_scan_dup_check_ext = 0x400011e8;\nr_ble_ll_scan_dup_check_legacy = 0x400011ec;\nr_ble_ll_scan_dup_move_to_head = 0x400011f0;\nr_ble_ll_scan_dup_new = 0x400011f4;\nr_ble_ll_scan_dup_update_ext = 0x400011f8;\nr_ble_ll_scan_dup_update_legacy = 0x400011fc;\nr_ble_ll_scan_enabled = 0x40001200;\nr_ble_ll_scan_end_adv_evt = 0x40001204;\nr_ble_ll_scan_env_init = 0x40001208;\nr_ble_ll_scan_ext_initiator_start = 0x4000120c;\nr_ble_ll_scan_get_addr_data_from_legacy = 0x40001210;\nr_ble_ll_scan_get_addr_from_ext_adv = 0x40001214;\nr_ble_ll_scan_get_cur_sm = 0x40001218;\nr_ble_ll_scan_get_ext_adv_report = 0x4000121c;\nr_ble_ll_scan_get_local_rpa = 0x40001220;\nr_ble_ll_scan_get_next_adv_prim_chan = 0x40001224;\nr_ble_ll_scan_get_peer_rpa = 0x40001228;\nr_ble_ll_scan_have_rxd_scan_rsp = 0x4000122c;\nr_ble_ll_scan_init = 0x40001230;\nr_ble_ll_scan_initiator_start = 0x40001234;\nr_ble_ll_scan_is_inside_window = 0x40001238;\nr_ble_ll_scan_move_window_to = 0x4000123c;\nr_ble_ll_scan_npl_reset = 0x40001240;\nr_ble_ll_scan_parse_auxptr = 0x40001244;\nr_ble_ll_scan_parse_ext_hdr = 0x40001248;\nr_ble_ll_scan_pre_process = 0x4000124c;\nr_ble_ll_scan_record_new_adv = 0x40001250;\nr_ble_ll_scan_refresh_nrpa = 0x40001254;\nr_ble_ll_scan_reset = 0x40001258;\nr_ble_ll_scan_rx_pkt_in = 0x4000125c;\nr_ble_ll_scan_rx_pkt_in_on_aux = 0x40001260;\nr_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001264;\nr_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268;\nr_ble_ll_scan_rxed = 0x4000126c;\nr_ble_ll_scan_send_adv_report = 0x40001270;\nr_ble_ll_scan_send_truncated = 0x40001274;\nr_ble_ll_scan_set_enable = 0x40001278;\nr_ble_ll_scan_set_peer_rpa = 0x4000127c;\nr_ble_ll_scan_set_perfer_addr = 0x40001280;\nr_ble_ll_scan_set_scan_params = 0x40001284;\nr_ble_ll_scan_sm_start = 0x40001288;\nr_ble_ll_scan_sm_stop = 0x4000128c;\nr_ble_ll_scan_time_hci_to_ticks = 0x40001290;\nr_ble_ll_scan_update_aux_data = 0x40001294;\nr_ble_ll_scan_whitelist_enabled = 0x40001298;\nr_ble_ll_set_default_privacy_mode = 0x4000129c;\nr_ble_ll_set_default_sync_transfer_params = 0x400012a0;\nr_ble_ll_set_ext_scan_params = 0x400012a4;\nr_ble_ll_set_host_feat = 0x400012a8;\nr_ble_ll_set_public_addr = 0x400012ac;\nr_ble_ll_set_random_addr = 0x400012b0;\nr_ble_ll_set_sync_transfer_params = 0x400012b4;\nr_ble_ll_state_get = 0x400012b8;\nr_ble_ll_state_set = 0x400012bc;\nr_ble_ll_sync_adjust_ext_hdr = 0x400012c0;\nr_ble_ll_sync_cancel = 0x400012c4;\nr_ble_ll_sync_cancel_complete_event = 0x400012c8;\nr_ble_ll_sync_check_acad = 0x400012cc;\nr_ble_ll_sync_check_failed = 0x400012d0;\nr_ble_ll_sync_create = 0x400012d4;\nr_ble_ll_sync_deinit = 0x400012d8;\nr_ble_ll_sync_enabled = 0x400012dc;\nr_ble_ll_sync_env_init = 0x400012e0;\nr_ble_ll_sync_est_event_failed = 0x400012e4;\nr_ble_ll_sync_est_event_success = 0x400012e8;\nr_ble_ll_sync_established = 0x400012ec;\nr_ble_ll_sync_filter_enabled = 0x400012f0;\nr_ble_ll_sync_find = 0x400012f4;\nr_ble_ll_sync_get_cur_sm = 0x400012f8;\nr_ble_ll_sync_get_handle = 0x400012fc;\nr_ble_ll_sync_get_sm = 0x40001300;\nr_ble_ll_sync_info_event = 0x40001304;\nr_ble_ll_sync_init = 0x40001308;\nr_ble_ll_sync_list_add = 0x4000130c;\nr_ble_ll_sync_list_clear = 0x40001310;\nr_ble_ll_sync_list_empty = 0x40001314;\nr_ble_ll_sync_list_get_free = 0x40001318;\nr_ble_ll_sync_list_remove = 0x4000131c;\nr_ble_ll_sync_list_search = 0x40001320;\nr_ble_ll_sync_list_size = 0x40001324;\nr_ble_ll_sync_lost_event = 0x40001328;\nr_ble_ll_sync_next_event = 0x4000132c;\nr_ble_ll_sync_on_list = 0x40001330;\nr_ble_ll_sync_parse_ext_hdr = 0x40001334;\nr_ble_ll_sync_periodic_ind = 0x40001338;\nr_ble_ll_sync_phy_mode_to_aux_phy = 0x4000133c;\nr_ble_ll_sync_phy_mode_to_hci = 0x40001340;\nr_ble_ll_sync_put_syncinfo = 0x40001344;\nr_ble_ll_sync_receive_enable = 0x40001348;\nr_ble_ll_sync_reserve = 0x4000134c;\nr_ble_ll_sync_reset = 0x40001350;\nr_ble_ll_sync_reset_sm = 0x40001354;\nr_ble_ll_sync_rx_pkt_in = 0x40001358;\nr_ble_ll_sync_send_per_adv_rpt = 0x4000135c;\nr_ble_ll_sync_send_sync_ind = 0x40001360;\nr_ble_ll_sync_send_truncated_per_adv_rpt = 0x40001364;\nr_ble_ll_sync_sm_clear = 0x40001368;\nr_ble_ll_sync_terminate = 0x4000136c;\nr_ble_ll_sync_transfer = 0x40001370;\nr_ble_ll_sync_transfer_get = 0x40001374;\nr_ble_ll_sync_transfer_received = 0x40001378;\nr_ble_ll_task = 0x4000137c;\nr_ble_ll_trace_set_func = 0x40001380;\nr_ble_ll_trace_u32 = 0x40001384;\nr_ble_ll_trace_u32x2 = 0x40001388;\nr_ble_ll_trace_u32x3 = 0x4000138c;\nr_ble_ll_tx_flat_mbuf_pducb = 0x40001390;\nr_ble_ll_tx_mbuf_pducb = 0x40001394;\nr_ble_ll_tx_pkt_in = 0x40001398;\nr_ble_ll_update_max_tx_octets_phy_mode = 0x4000139c;\nr_ble_ll_usecs_to_ticks_round_up = 0x400013a0;\nr_ble_ll_utils_calc_access_addr = 0x400013a4;\nr_ble_ll_utils_calc_dci_csa2 = 0x400013a8;\nr_ble_ll_utils_calc_num_used_chans = 0x400013ac;\nr_ble_ll_utils_calc_window_widening = 0x400013b0;\nr_ble_ll_utils_csa2_perm = 0x400013b4;\nr_ble_ll_utils_csa2_prng = 0x400013b8;\nr_ble_ll_utils_remapped_channel = 0x400013bc;\nr_ble_ll_whitelist_add = 0x400013c0;\nr_ble_ll_whitelist_chg_allowed = 0x400013c4;\nr_ble_ll_whitelist_clear = 0x400013c8;\nr_ble_ll_whitelist_read_size = 0x400013cc;\nr_ble_ll_whitelist_rmv = 0x400013d0;\nr_ble_ll_whitelist_search = 0x400013d4;\nr_ble_ll_write_rf_path_compensation = 0x400013d8;\nr_ble_lll_adv_aux_scannable_pdu_payload_len = 0x400013dc;\nr_ble_lll_adv_aux_schedule = 0x400013e0;\nr_ble_lll_adv_aux_schedule_first = 0x400013e4;\nr_ble_lll_adv_aux_schedule_next = 0x400013e8;\nr_ble_lll_adv_aux_scheduled = 0x400013ec;\nr_ble_lll_adv_aux_set_start_time = 0x400013f0;\nr_ble_lll_adv_coex_dpc_calc_pti_update_itvl = 0x400013f4;\nr_ble_lll_adv_coex_dpc_process_pri = 0x400013f8;\nr_ble_lll_adv_coex_dpc_process_sec = 0x400013fc;\nr_ble_lll_adv_coex_dpc_pti_get = 0x40001400;\nr_ble_lll_adv_coex_dpc_update = 0x40001404;\nr_ble_lll_adv_coex_dpc_update_on_adv_start = 0x40001408;\nr_ble_lll_adv_coex_dpc_update_on_aux_scheduled = 0x4000140c;\nr_ble_lll_adv_coex_dpc_update_on_data_updated = 0x40001410;\nr_ble_lll_adv_coex_dpc_update_on_event_end = 0x40001414;\nr_ble_lll_adv_coex_dpc_update_on_event_scheduled = 0x40001418;\nr_ble_lll_adv_done = 0x4000141c;\nr_ble_lll_adv_drop_event = 0x40001420;\nr_ble_lll_adv_event_done = 0x40001424;\nr_ble_lll_adv_event_rmvd_from_sched = 0x40001428;\nr_ble_lll_adv_ext_estimate_data_itvl = 0x4000142c;\nr_ble_lll_adv_get_sec_pdu_len = 0x40001430;\nr_ble_lll_adv_halt = 0x40001434;\nr_ble_lll_adv_make_done = 0x40001438;\nr_ble_lll_adv_periodic_done = 0x4000143c;\nr_ble_lll_adv_periodic_event_done = 0x40001440;\nr_ble_lll_adv_periodic_rmvd_from_sched = 0x40001444;\nr_ble_lll_adv_periodic_schedule_first = 0x40001448;\nr_ble_lll_adv_periodic_schedule_next = 0x4000144c;\nr_ble_lll_adv_periodic_start = 0x40001450;\nr_ble_lll_adv_periodic_stop = 0x40001454;\nr_ble_lll_adv_pri_schedule_tx_pdu = 0x40001458;\nr_ble_lll_adv_reschedule_event = 0x4000145c;\nr_ble_lll_adv_reschedule_periodic_event = 0x40001460;\nr_ble_lll_adv_rx_pkt_isr = 0x40001464;\nr_ble_lll_adv_sec_done = 0x40001468;\nr_ble_lll_adv_sec_event_done = 0x4000146c;\nr_ble_lll_adv_sec_schedule_next_aux = 0x40001470;\nr_ble_lll_adv_secondary_tx_start_cb = 0x40001474;\nr_ble_lll_adv_sm_deinit = 0x40001478;\nr_ble_lll_adv_sm_event_init = 0x4000147c;\nr_ble_lll_adv_sm_event_restore = 0x40001480;\nr_ble_lll_adv_sm_event_store = 0x40001484;\nr_ble_lll_adv_sm_init = 0x40001488;\nr_ble_lll_adv_sm_reset = 0x4000148c;\nr_ble_lll_adv_start = 0x40001490;\nr_ble_lll_adv_stop = 0x40001494;\nr_ble_lll_adv_sync_next_scheduled = 0x40001498;\nr_ble_lll_adv_sync_schedule = 0x4000149c;\nr_ble_lll_adv_sync_tx_done = 0x400014a0;\nr_ble_lll_adv_sync_tx_end = 0x400014a4;\nr_ble_lll_adv_sync_tx_start_cb = 0x400014a8;\nr_ble_lll_adv_tx_done = 0x400014ac;\nr_ble_lll_adv_tx_start_cb = 0x400014b0;\nr_ble_lll_adv_update_rsp_offset = 0x400014b4;\nr_ble_lll_aux_scan_cb = 0x400014b8;\nr_ble_lll_aux_scan_drop = 0x400014bc;\nr_ble_lll_aux_scan_drop_event_cb = 0x400014c0;\nr_ble_lll_calc_us_convert_tick_unit = 0x400014c4;\nr_ble_lll_conn_append_tx_buffer = 0x400014c8;\nr_ble_lll_conn_can_send_next_pdu = 0x400014cc;\nr_ble_lll_conn_check_opcode_matched = 0x400014d0;\nr_ble_lll_conn_coex_dpc_process = 0x400014d4;\nr_ble_lll_conn_coex_dpc_pti_get = 0x400014d8;\nr_ble_lll_conn_coex_dpc_update = 0x400014dc;\nr_ble_lll_conn_coex_dpc_update_on_event_end = 0x400014e0;\nr_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4;\nr_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8;\nr_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec;\nr_ble_lll_conn_cth_flow_free_credit = 0x400014f0;\nr_ble_lll_conn_current_sm_over = 0x400014f4;\nr_ble_lll_conn_env_deinit = 0x400014fc;\nr_ble_lll_conn_env_init = 0x40001500;\nr_ble_lll_conn_event_end = 0x40001504;\nr_ble_lll_conn_event_end_timer_cb = 0x40001508;\nr_ble_lll_conn_event_halt = 0x4000150c;\nr_ble_lll_conn_event_is_over = 0x40001510;\nr_ble_lll_conn_event_start_cb = 0x40001514;\nr_ble_lll_conn_free_rx_mbuf = 0x40001518;\nr_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c;\nr_ble_lll_conn_get_ce_end_time = 0x40001520;\nr_ble_lll_conn_get_next_sched_time = 0x40001524;\nr_ble_lll_conn_get_rx_mbuf = 0x40001528;\nr_ble_lll_conn_halt = 0x4000152c;\nr_ble_lll_conn_master_common_init = 0x40001530;\nr_ble_lll_conn_master_new = 0x40001534;\nr_ble_lll_conn_module_deinit = 0x40001538;\nr_ble_lll_conn_module_init = 0x4000153c;\nr_ble_lll_conn_module_reset = 0x40001540;\nr_ble_lll_conn_no_mem_evt_pre_cb = 0x40001544;\nr_ble_lll_conn_pre_process = 0x40001548;\nr_ble_lll_conn_process_acked_pdu = 0x4000154c;\nr_ble_lll_conn_process_in_isr = 0x40001550;\nr_ble_lll_conn_recv_ack = 0x40001554;\nr_ble_lll_conn_recv_valid_packet = 0x40001558;\nr_ble_lll_conn_reset_pending_sched = 0x4000155c;\nr_ble_lll_conn_rx_pkt_isr = 0x40001560;\nr_ble_lll_conn_sched_next_anchor = 0x40001564;\nr_ble_lll_conn_sched_next_event = 0x40001568;\nr_ble_lll_conn_set_slave_flow_control = 0x4000156c;\nr_ble_lll_conn_slave_new = 0x40001570;\nr_ble_lll_conn_sm_new = 0x40001574;\nr_ble_lll_conn_sm_npl_deinit = 0x40001578;\nr_ble_lll_conn_sm_npl_init = 0x4000157c;\nr_ble_lll_conn_superversion_timer_cb = 0x40001580;\nr_ble_lll_conn_timeout = 0x40001584;\nr_ble_lll_conn_update_anchor = 0x40001588;\nr_ble_lll_conn_update_conn_ind_params = 0x4000158c;\nr_ble_lll_conn_update_encryption = 0x40001590;\nr_ble_lll_conn_update_tx_buffer = 0x40001594;\nr_ble_lll_deinit = 0x40001598;\nr_ble_lll_dtm_calculate_itvl = 0x4000159c;\nr_ble_lll_dtm_ctx_free = 0x400015a0;\nr_ble_lll_dtm_deinit = 0x400015a4;\nr_ble_lll_dtm_end_test = 0x400015a8;\nr_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;\nr_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;\nr_ble_lll_dtm_init = 0x400015b4;\nr_ble_lll_dtm_reset = 0x400015b8;\nr_ble_lll_dtm_rx_create_ctx = 0x400015bc;\nr_ble_lll_dtm_rx_isr_end = 0x400015c0;\nr_ble_lll_dtm_rx_isr_start = 0x400015c4;\nr_ble_lll_dtm_rx_pkt_in = 0x400015c8;\nr_ble_lll_dtm_rx_sched_cb = 0x400015cc;\nr_ble_lll_dtm_rx_start = 0x400015d0;\nr_ble_lll_dtm_rx_test = 0x400015d4;\nr_ble_lll_dtm_set_next = 0x400015d8;\nr_ble_lll_dtm_tx_create_ctx = 0x400015dc;\nr_ble_lll_dtm_tx_done = 0x400015e0;\nr_ble_lll_dtm_tx_sched_cb = 0x400015e4;\nr_ble_lll_dtm_tx_test = 0x400015e8;\nr_ble_lll_dtm_wfr_timer_exp = 0x400015ec;\nr_ble_lll_event_rx_pkt = 0x400015f0;\nr_ble_lll_ext_scan_coex_dpc_process = 0x400015f4;\nr_ble_lll_ext_scan_coex_dpc_pti_get = 0x400015f8;\nr_ble_lll_ext_scan_coex_dpc_update = 0x400015fc;\nr_ble_lll_ext_scan_coex_dpc_update_on_start = 0x40001600;\nr_ble_lll_hci_dtm_rx_test = 0x40001604;\nr_ble_lll_hci_dtm_rx_test_v2 = 0x40001608;\nr_ble_lll_hci_dtm_tx_test = 0x4000160c;\nr_ble_lll_hci_dtm_tx_test_ext = 0x40001610;\nr_ble_lll_hci_dtm_tx_test_v2 = 0x40001614;\nr_ble_lll_hci_dtm_tx_test_v2_ext = 0x40001618;\nr_ble_lll_init = 0x4000161c;\nr_ble_lll_init_pre_process = 0x40001620;\nr_ble_lll_per_adv_coex_dpc_calc_pti_update_itvl = 0x40001628;\nr_ble_lll_per_adv_coex_dpc_process = 0x4000162c;\nr_ble_lll_per_adv_coex_dpc_pti_get = 0x40001630;\nr_ble_lll_per_adv_coex_dpc_update = 0x40001634;\nr_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638;\nr_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c;\nr_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640;\nr_ble_lll_reset = 0x40001644;\nr_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;\nr_ble_lll_rfmgmt_deinit = 0x4000164c;\nr_ble_lll_rfmgmt_disable = 0x40001650;\nr_ble_lll_rfmgmt_enable = 0x40001654;\nr_ble_lll_rfmgmt_enable_now = 0x40001658;\nr_ble_lll_rfmgmt_init = 0x4000165c;\nr_ble_lll_rfmgmt_is_enabled = 0x40001660;\nr_ble_lll_rfmgmt_release = 0x40001664;\nr_ble_lll_rfmgmt_release_ev = 0x40001668;\nr_ble_lll_rfmgmt_reset = 0x4000166c;\nr_ble_lll_rfmgmt_scan_changed = 0x40001670;\nr_ble_lll_rfmgmt_sched_changed = 0x40001674;\nr_ble_lll_rfmgmt_set_sleep_cb = 0x40001678;\nr_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c;\nr_ble_lll_rfmgmt_timer_exp = 0x40001680;\nr_ble_lll_rfmgmt_timer_reschedule = 0x40001684;\nr_ble_lll_rx_pdu_in = 0x40001688;\nr_ble_lll_rx_pkt_in = 0x4000168c;\nr_ble_lll_rx_pkt_isr = 0x40001690;\nr_ble_lll_scan_abort_aux_sched = 0x40001694;\nr_ble_lll_scan_aux_data_free = 0x40001698;\nr_ble_lll_scan_chk_resume = 0x4000169c;\nr_ble_lll_scan_clean_cur_aux_data = 0x400016a0;\nr_ble_lll_scan_coex_event_cb = 0x400016a4;\nr_ble_lll_scan_common_init = 0x400016a8;\nr_ble_lll_scan_deinit = 0x400016ac;\nr_ble_lll_scan_duration_period_timers_restart = 0x400016b0;\nr_ble_lll_scan_duration_period_timers_stop = 0x400016b4;\nr_ble_lll_scan_duration_timer_cb = 0x400016b8;\nr_ble_lll_scan_event_proc = 0x400016bc;\nr_ble_lll_scan_ext_adv_init = 0x400016c0;\nr_ble_lll_scan_halt = 0x400016c4;\nr_ble_lll_scan_has_sent_scan_req = 0x400016c8;\nr_ble_lll_scan_init = 0x400016cc;\nr_ble_lll_scan_npl_init = 0x400016d0;\nr_ble_lll_scan_npl_reset = 0x400016d4;\nr_ble_lll_scan_npl_restore = 0x400016d8;\nr_ble_lll_scan_npl_store = 0x400016dc;\nr_ble_lll_scan_period_timer_cb = 0x400016e0;\nr_ble_lll_scan_process_adv_in_isr = 0x400016e4;\nr_ble_lll_scan_process_rsp_in_isr = 0x400016e8;\nr_ble_lll_scan_req_backoff = 0x400016ec;\nr_ble_lll_scan_restart = 0x400016f0;\nr_ble_lll_scan_rx_isr_on_aux = 0x400016f4;\nr_ble_lll_scan_rx_isr_on_legacy = 0x400016f8;\nr_ble_lll_scan_rx_pkt_isr = 0x400016fc;\nr_ble_lll_scan_sched_next_aux = 0x40001700;\nr_ble_lll_scan_sched_remove = 0x40001704;\nr_ble_lll_scan_start = 0x40001708;\nr_ble_lll_scan_start_rx = 0x4000170c;\nr_ble_lll_scan_stop = 0x40001710;\nr_ble_lll_scan_targeta_is_matched = 0x40001714;\nr_ble_lll_scan_timer_cb = 0x40001718;\nr_ble_lll_sched_adv_new = 0x4000171c;\nr_ble_lll_sched_adv_resched_pdu = 0x40001720;\nr_ble_lll_sched_adv_reschedule = 0x40001724;\nr_ble_lll_sched_aux_scan = 0x40001728;\nr_ble_lll_sched_conn_overlap = 0x4000172c;\nr_ble_lll_sched_conn_reschedule = 0x40001730;\nr_ble_lll_sched_deinit = 0x40001734;\nr_ble_lll_sched_dtm = 0x40001738;\nr_ble_lll_sched_env_init = 0x4000173c;\nr_ble_lll_sched_execute_item = 0x40001744;\nr_ble_lll_sched_init = 0x40001748;\nr_ble_lll_sched_insert_if_empty = 0x4000174c;\nr_ble_lll_sched_is_overlap = 0x40001750;\nr_ble_lll_sched_master_new = 0x40001754;\nr_ble_lll_sched_next_time = 0x40001758;\nr_ble_lll_sched_overlaps_current = 0x4000175c;\nr_ble_lll_sched_periodic_adv = 0x40001760;\nr_ble_lll_sched_rmv_elem = 0x40001764;\nr_ble_lll_sched_rmv_elem_type = 0x40001768;\nr_ble_lll_sched_run = 0x4000176c;\nr_ble_lll_sched_scan_req_over_aux_ptr = 0x40001770;\nr_ble_lll_sched_slave_new = 0x40001774;\nr_ble_lll_sched_stop = 0x40001778;\nr_ble_lll_sched_sync = 0x4000177c;\nr_ble_lll_sched_sync_overlaps_current = 0x40001780;\nr_ble_lll_sched_sync_reschedule = 0x40001784;\nr_ble_lll_sync_chain_start_cb = 0x40001788;\nr_ble_lll_sync_coex_dpc_process = 0x4000178c;\nr_ble_lll_sync_coex_dpc_pti_get = 0x40001790;\nr_ble_lll_sync_coex_dpc_update = 0x40001794;\nr_ble_lll_sync_current_sm_over = 0x40001798;\nr_ble_lll_sync_deinit = 0x4000179c;\nr_ble_lll_sync_event_end = 0x400017a0;\nr_ble_lll_sync_event_end_cb = 0x400017a4;\nr_ble_lll_sync_event_start_cb = 0x400017a8;\nr_ble_lll_sync_get_event_end_time = 0x400017ac;\nr_ble_lll_sync_halt = 0x400017b0;\nr_ble_lll_sync_init = 0x400017b4;\nr_ble_lll_sync_new = 0x400017b8;\nr_ble_lll_sync_reset = 0x400017bc;\nr_ble_lll_sync_reset_sm = 0x400017c0;\nr_ble_lll_sync_rmvd_from_sched = 0x400017c4;\nr_ble_lll_sync_rx_pkt_isr = 0x400017c8;\nr_ble_lll_sync_schedule_chain = 0x400017cc;\nr_ble_lll_sync_stop = 0x400017d0;\nr_ble_lll_sync_trnasfer_sched = 0x400017d4;\nr_ble_phy_access_addr_get = 0x400017d8;\nr_ble_phy_calculate_rxtx_ifs = 0x400017dc;\nr_ble_phy_calculate_rxwindow = 0x400017e0;\nr_ble_phy_calculate_txrx_ifs = 0x400017e4;\nr_ble_phy_check_bb_status = 0x400017e8;\nr_ble_phy_complete_rx_info = 0x400017ec;\nr_ble_phy_config_access_addr = 0x400017f0;\nr_ble_phy_data_make = 0x400017f4;\nr_ble_phy_disable = 0x400017f8;\nr_ble_phy_disable_irq = 0x400017fc;\nr_ble_phy_disable_whitening = 0x40001800;\nr_ble_phy_enable_whitening = 0x40001804;\nr_ble_phy_encrypt_disable = 0x40001808;\nr_ble_phy_env_init = 0x4000180c;\nr_ble_phy_get_current_phy = 0x40001810;\nr_ble_phy_get_packet_counter = 0x40001814;\nr_ble_phy_get_packet_status = 0x40001818;\nr_ble_phy_get_pyld_time_offset = 0x4000181c;\nr_ble_phy_get_rx_phy_mode = 0x40001820;\nr_ble_phy_get_seq_end_st = 0x40001824;\nr_ble_phy_init = 0x40001828;\nr_ble_phy_isr = 0x4000182c;\nr_ble_phy_max_data_pdu_pyld = 0x40001830;\nr_ble_phy_mode_config = 0x40001834;\nr_ble_phy_mode_convert = 0x40001838;\nr_ble_phy_mode_write = 0x4000183c;\nr_ble_phy_module_deinit = 0x40001840;\nr_ble_phy_module_init = 0x40001844;\nr_ble_phy_monitor_bb_sync = 0x40001848;\nr_ble_phy_reset_bb_monitor = 0x4000184c;\nr_ble_phy_resolv_list_disable = 0x40001850;\nr_ble_phy_resolv_list_enable = 0x40001854;\nr_ble_phy_restart_sequence = 0x40001858;\nr_ble_phy_rx_set_start_time_forcibly = 0x4000185c;\nr_ble_phy_rxpdu_copy = 0x40001860;\nr_ble_phy_seq_encrypt_enable = 0x40001864;\nr_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001868;\nr_ble_phy_sequence_end_isr = 0x4000186c;\nr_ble_phy_sequence_get_mode = 0x40001870;\nr_ble_phy_sequence_is_running = 0x40001874;\nr_ble_phy_sequence_is_waiting_rsp = 0x40001878;\nr_ble_phy_sequence_single_end = 0x4000187c;\nr_ble_phy_sequence_tx_end_invoke = 0x40001880;\nr_ble_phy_sequence_update_conn_ind_params = 0x40001884;\nr_ble_phy_set_adv_mode = 0x40001888;\nr_ble_phy_set_coex_pti = 0x4000188c;\nr_ble_phy_set_conn_ind_pdu = 0x40001890;\nr_ble_phy_set_conn_mode = 0x40001894;\nr_ble_phy_set_dev_address = 0x40001898;\nr_ble_phy_set_rx_pwr_compensation = 0x4000189c;\nr_ble_phy_set_rxhdr = 0x400018a0;\nr_ble_phy_set_scan_mode = 0x400018a4;\nr_ble_phy_set_sequence_mode = 0x400018a8;\nr_ble_phy_set_single_packet_rx_sequence = 0x400018ac;\nr_ble_phy_set_single_packet_tx_sequence = 0x400018b0;\nr_ble_phy_set_tx_rx_transition = 0x400018b4;\nr_ble_phy_set_txend_cb = 0x400018b8;\nr_ble_phy_setchan = 0x400018bc;\nr_ble_phy_start_rx_immediately = 0x400018c0;\nr_ble_phy_state_get = 0x400018c4;\nr_ble_phy_timer_config_start_time = 0x400018c8;\nr_ble_phy_timer_start_now = 0x400018cc;\nr_ble_phy_timer_stop = 0x400018d0;\nr_ble_phy_tx_set_start_time = 0x400018d4;\nr_ble_phy_txpower_round = 0x400018d8;\nr_ble_phy_txpwr_set = 0x400018dc;\nr_ble_phy_update_conn_sequence = 0x400018e0;\nr_ble_phy_update_encryption = 0x400018e4;\nr_ble_phy_update_ifs = 0x400018e8;\nr_ble_phy_xcvr_state_get = 0x400018ec;\nr_ble_plf_set_log_level = 0x400018f0;\nr_ble_rtc_wake_up_cpu_init = 0x400018f4;\nr_ble_rtc_wake_up_state_clr = 0x400018f8;\nr_ble_vendor_hci_register = 0x400018fc;\nr_bt_rf_coex_cfg_set = 0x40001900;\nr_bt_rf_coex_coded_txrx_time_upper_lim = 0x40001904;\nr_bt_rf_coex_dft_pti_set = 0x40001908;\nr_bt_rf_coex_hook_deinit = 0x4000190c;\nr_bt_rf_coex_hook_init = 0x40001910;\nr_bt_rf_coex_hook_st_set = 0x40001914;\nr_bt_rf_coex_hooks_p_set_default = 0x40001918;\nr_btdm_disable_adv_delay = 0x4000191c;\nr_btdm_switch_phy_coded = 0x40001920;\nr_esp_wait_disabled = 0x40001924;\nr_get_be16 = 0x40001928;\nr_get_be24 = 0x4000192c;\nr_get_be32 = 0x40001930;\nr_get_be64 = 0x40001934;\nr_get_le16 = 0x40001938;\nr_get_le24 = 0x4000193c;\nr_get_le32 = 0x40001940;\nr_get_le64 = 0x40001944;\nr_get_local_irk_offset = 0x40001948;\nr_get_local_rpa_offset = 0x4000194c;\nr_get_max_skip = 0x40001950;\nr_get_peer_id_offset = 0x40001954;\nr_get_peer_irk_offset = 0x40001958;\nr_get_peer_rpa_offset = 0x4000195c;\nr_hal_rtc_intr_init = 0x40001960;\nr_hal_rtc_irq_handler = 0x40001964;\nr_hal_timer_deinit = 0x40001968;\nr_hal_timer_disable_irq = 0x4000196c;\nr_hal_timer_env_init = 0x40001970;\nr_hal_timer_init = 0x40001974;\nr_hal_timer_process = 0x40001978;\nr_hal_timer_read = 0x4000197c;\nr_hal_timer_read_tick = 0x40001980;\nr_hal_timer_set_cb = 0x40001984;\nr_hal_timer_set_exp_tick = 0x40001988;\nr_hal_timer_start = 0x4000198c;\nr_hal_timer_start_at = 0x40001990;\nr_hal_timer_stop = 0x40001994;\nr_hal_timer_task_start = 0x40001998;\nr_ll_assert = 0x4000199c;\nr_mem_init_mbuf_pool = 0x400019a0;\nr_mem_malloc_mbuf_pool = 0x400019a4;\nr_mem_malloc_mbufpkt_pool = 0x400019a8;\nr_mem_malloc_mempool = 0x400019ac;\nr_mem_malloc_mempool_ext = 0x400019b0;\nr_mem_malloc_mempool_gen = 0x400019b4;\nr_mem_pullup_obj = 0x400019b8;\nr_mem_split_frag = 0x400019bc;\nr_os_cputime_get32 = 0x400019c0;\nr_os_cputime_ticks_to_usecs = 0x400019c4;\nr_os_cputime_timer_init = 0x400019c8;\nr_os_cputime_timer_relative = 0x400019cc;\nr_os_cputime_timer_start = 0x400019d0;\nr_os_cputime_timer_stop = 0x400019d4;\nr_os_cputime_usecs_to_ticks = 0x400019d8;\nr_os_mbuf_adj = 0x400019dc;\nr_os_mbuf_append = 0x400019e0;\nr_os_mbuf_appendfrom = 0x400019e4;\nr_os_mbuf_cmpf = 0x400019e8;\nr_os_mbuf_cmpm = 0x400019ec;\nr_os_mbuf_concat = 0x400019f0;\nr_os_mbuf_copydata = 0x400019f4;\nr_os_mbuf_copyinto = 0x400019f8;\nr_os_mbuf_dup = 0x400019fc;\nr_os_mbuf_extend = 0x40001a00;\nr_os_mbuf_free = 0x40001a04;\nr_os_mbuf_free_chain = 0x40001a08;\nr_os_mbuf_get = 0x40001a0c;\nr_os_mbuf_get_pkthdr = 0x40001a10;\nr_os_mbuf_leadingspace = 0x40001a14;\nr_os_mbuf_len = 0x40001a18;\nr_os_mbuf_off = 0x40001a1c;\nr_os_mbuf_pack_chains = 0x40001a20;\nr_os_mbuf_pool_init = 0x40001a24;\nr_os_mbuf_prepend = 0x40001a28;\nr_os_mbuf_prepend_pullup = 0x40001a2c;\nr_os_mbuf_pullup = 0x40001a30;\nr_os_mbuf_trailingspace = 0x40001a34;\nr_os_mbuf_trim_front = 0x40001a38;\nr_os_mbuf_widen = 0x40001a3c;\nr_os_memblock_from = 0x40001a40;\nr_os_memblock_get = 0x40001a44;\nr_os_memblock_put = 0x40001a48;\nr_os_memblock_put_from_cb = 0x40001a4c;\nr_os_mempool_clear = 0x40001a50;\nr_os_mempool_ext_clear = 0x40001a54;\nr_os_mempool_ext_init = 0x40001a58;\nr_os_mempool_info_get_next = 0x40001a5c;\nr_os_mempool_init = 0x40001a60;\nr_os_mempool_init_internal = 0x40001a64;\nr_os_mempool_is_sane = 0x40001a68;\nr_os_mempool_module_init = 0x40001a6c;\nr_os_mempool_unregister = 0x40001a70;\nr_os_mqueue_get = 0x40001a74;\nr_os_mqueue_init = 0x40001a78;\nr_os_mqueue_put = 0x40001a7c;\nr_os_msys_count = 0x40001a80;\nr_os_msys_get = 0x40001a84;\nr_os_msys_get_pkthdr = 0x40001a88;\nr_os_msys_num_free = 0x40001a8c;\nr_os_msys_register = 0x40001a90;\nr_os_msys_reset = 0x40001a94;\nr_pri_phy_valid = 0x40001a98;\nr_put_be16 = 0x40001a9c;\nr_put_be24 = 0x40001aa0;\nr_put_be32 = 0x40001aa4;\nr_put_be64 = 0x40001aa8;\nr_put_le16 = 0x40001aac;\nr_put_le24 = 0x40001ab0;\nr_put_le32 = 0x40001ab4;\nr_put_le64 = 0x40001ab8;\nr_rtc0_timer_handler = 0x40001abc;\nr_sdkconfig_get_opts = 0x40001ac0;\nr_sdkconfig_set_opts = 0x40001ac4;\nr_sec_phy_valid = 0x40001ac8;\nr_swap_buf = 0x40001acc;\nr_swap_in_place = 0x40001ad0;\n\/* Data (.data, .bss, .rodata) *\/\nble_lll_dtm_module_env_p = 0x3fcdffc4;\ng_ble_lll_dtm_prbs15_data = 0x3ff4fee4;\ng_ble_lll_dtm_prbs9_data = 0x3ff4fde4;\ng_channel_rf_to_index = 0x3ff4fdbc;\ng_ble_lll_rfmgmt_data = 0x3fcdff7c;\ng_ble_sleep_enter_cb = 0x3fcdff78;\ng_ble_sleep_exit_cb = 0x3fcdff74;\nble_lll_sched_env_p = 0x3fcdff70;\nble_ll_env_p = 0x3fcdff6c;\ng_ble_ll_pdu_header_tx_time_ro = 0x3ff4fdb4;\nble_ll_adv_env_p = 0x3fcdff68;\nble_ll_conn_env_p = 0x3fcdff64;\nble_ll_conn_required_phy_mask = 0x3ff4fdb0;\nble_ll_valid_conn_phy_mask = 0x3ff4fdaf;\ng_ble_ll_ctrl_pkt_lengths_ro = 0x3ff4fd8c;\nble_ll_hci_env_p = 0x3fcdff60;\ng_debug_le_private_key = 0x3ff4fd6c;\ng_ecc_key = 0x3fcdfefc;\nble_ll_rand_env_p = 0x3fcdfef8;\nble_ll_resolv_env_p = 0x3fcdfef4;\ng_ble_ll_resolve_hdr = 0x3fcdfeec;\ng_device_mode_default = 0x3fcdfe68;\nble_ll_scan_classify_filter_aux_check_cb = 0x3fcdfee8;\nble_ll_scan_classify_filter_check_cb = 0x3fcdfee4;\nble_ll_scan_env_p = 0x3fcdfee0;\ng_ble_ll_supp_cmds_ro = 0x3ff4fd3c;\nble_ll_sync_env_p = 0x3fcdfedc;\ng_ble_sca_ppm_tbl_ro = 0x3ff4fd2c;\npriv_config_opts = 0x3fcdfe48;\nble_hci_uart_reset_cmd = 0x3ff4fd28;\nble_hci_trans_env_p = 0x3fcdfed8;\nble_hci_trans_mode = 0x3fcdfe44;\nble_hci_trans_funcs_ptr = 0x3fcdfed4;\nr_ble_lll_stub_funcs_ptr = 0x3fcdfed0;\nr_ble_stub_funcs_ptr = 0x3fcdfecc;\nr_ext_funcs_p = 0x3fcdfec8;\nr_npl_funcs = 0x3fcdfec4;\nble_hw_env_p = 0x3fcdfec0;\nble_phy_module_env_p = 0x3fcdfebc;\ng_ble_phy_chan_freq_ro = 0x3ff4fd00;\ng_ble_phy_mode_pkt_start_off_ro = 0x3ff4fcf8;\ng_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fce8;\ng_ble_phy_t_rxaddrdelay_ro = 0x3ff4fce4;\ng_ble_phy_t_rxenddelay_ro = 0x3ff4fce0;\ng_ble_phy_t_txdelay_ro = 0x3ff4fcdc;\ng_ble_phy_t_txenddelay_ro = 0x3ff4fcd8;\ng_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcc8;\nhal_timer_env_p = 0x3fcdfeb8;\nr_osi_coex_funcs_p = 0x3fcdfeb4;\nbt_rf_coex_hooks = 0x3fcdfeac;\nbt_rf_coex_hooks_p = 0x3fcdfea8;\ncoex_hook_st_group_tab = 0x3ff4fcbc;\ncoex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcb8;\ns_ble_act_count_by_group = 0x3fcdfea4;\ns_ble_coex_st_map = 0x3fcdfe90;\nbt_rf_coex_cfg_cb = 0x3fcdfe74;\nbt_rf_coex_cfg_p = 0x3fcdfe70;\nbt_rf_coex_cfg_rom = 0x3ff4fc9c;\nbt_rf_coex_pti_dft_p = 0x3fcdfe6c;\nbt_rf_coex_pti_dft_rom = 0x3fcdfe04;\nconn_dynamic_pti_param_rom = 0x3ff4fc84;\nconn_phy_coded_max_data_time_param_rom = 0x3ff4fc80;\next_adv_dynamic_pti_param_rom = 0x3ff4fc4c;\next_scan_dynamic_param_rom = 0x3ff4fc14;\nlegacy_adv_dynamic_pti_param_rom = 0x3ff4fbf4;\nper_adv_dynamic_pti_param_rom = 0x3ff4fbd8;\nsync_dynamic_param_rom = 0x3ff4fbc0;\ng_ble_plf_log_level = 0x3fcdfe00;\ng_msys_pool_list = 0x3fcdfdf8;\ng_os_mempool_list = 0x3fcdfdf0;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x40001ad4;\nRC_GetBlockAckTime = 0x40001ad8;\nebuf_list_remove = 0x40001adc;\nesf_buf_alloc = 0x40001ae0;\nesf_buf_alloc_dynamic = 0x40001ae4;\nesf_buf_recycle = 0x40001ae8;\nGetAccess = 0x40001aec;\nhal_mac_is_low_rate_enabled = 0x40001af0;\nhal_mac_tx_get_blockack = 0x40001af4;\nhal_mac_tx_set_ppdu = 0x40001af8;\nic_get_trc = 0x40001afc;\nic_mac_deinit = 0x40001b00;\nic_mac_init = 0x40001b04;\nic_interface_enabled = 0x40001b08;\nis_lmac_idle = 0x40001b0c;\nlmacAdjustTimestamp = 0x40001b10;\nlmacDiscardAgedMSDU = 0x40001b14;\nlmacDiscardMSDU = 0x40001b18;\nlmacEndFrameExchangeSequence = 0x40001b1c;\nlmacIsIdle = 0x40001b20;\nlmacIsLongFrame = 0x40001b24;\nlmacMSDUAged = 0x40001b28;\nlmacPostTxComplete = 0x40001b2c;\nlmacProcessAllTxTimeout = 0x40001b30;\nlmacProcessCollisions = 0x40001b34;\nlmacProcessRxSucData = 0x40001b38;\nlmacReachLongLimit = 0x40001b3c;\nlmacReachShortLimit = 0x40001b40;\nlmacRecycleMPDU = 0x40001b44;\nlmacRxDone = 0x40001b48;\nlmacSetTxFrame = 0x40001b4c;\nlmacTxDone = 0x40001b50;\nlmacTxFrame = 0x40001b54;\nmac_tx_set_duration = 0x40001b58;\nmac_tx_set_htsig = 0x40001b5c;\nmac_tx_set_plcp0 = 0x40001b60;\nmac_tx_set_plcp1 = 0x40001b64;\nmac_tx_set_plcp2 = 0x40001b68;\npm_check_state = 0x40001b6c;\npm_disable_dream_timer = 0x40001b70;\npm_disable_sleep_delay_timer = 0x40001b74;\npm_dream = 0x40001b78;\npm_mac_wakeup = 0x40001b7c;\npm_mac_sleep = 0x40001b80;\npm_enable_active_timer = 0x40001b84;\npm_enable_sleep_delay_timer = 0x40001b88;\npm_local_tsf_process = 0x40001b8c;\npm_set_beacon_filter = 0x40001b90;\npm_is_in_wifi_slice_threshold = 0x40001b94;\npm_is_waked = 0x40001b98;\npm_keep_alive = 0x40001b9c;\npm_on_beacon_rx = 0x40001ba0;\npm_on_data_rx = 0x40001ba4;\npm_on_tbtt = 0x40001ba8;\npm_parse_beacon = 0x40001bac;\npm_process_tim = 0x40001bb0;\npm_rx_beacon_process = 0x40001bb4;\npm_rx_data_process = 0x40001bb8;\npm_sleep = 0x40001bbc;\npm_sleep_for = 0x40001bc0;\npm_tbtt_process = 0x40001bc4;\nppAMPDU2Normal = 0x40001bc8;\nppAssembleAMPDU = 0x40001bcc;\nppCalFrameTimes = 0x40001bd0;\nppCalSubFrameLength = 0x40001bd4;\nppCalTxAMPDULength = 0x40001bd8;\nppCheckTxAMPDUlength = 0x40001bdc;\nppDequeueRxq_Locked = 0x40001be0;\nppDequeueTxQ = 0x40001be4;\nppEmptyDelimiterLength = 0x40001be8;\nppEnqueueRxq = 0x40001bec;\nppEnqueueTxDone = 0x40001bf0;\nppGetTxQFirstAvail_Locked = 0x40001bf4;\nppGetTxframe = 0x40001bf8;\nppMapTxQueue = 0x40001bfc;\nppProcTxSecFrame = 0x40001c00;\nppProcessRxPktHdr = 0x40001c04;\nppProcessTxQ = 0x40001c08;\nppRecordBarRRC = 0x40001c0c;\nlmacRequestTxopQueue = 0x40001c10;\nlmacReleaseTxopQueue = 0x40001c14;\nppRecycleAmpdu = 0x40001c18;\nppRecycleRxPkt = 0x40001c1c;\nppResortTxAMPDU = 0x40001c20;\nppResumeTxAMPDU = 0x40001c24;\nppRxFragmentProc = 0x40001c28;\nppRxPkt = 0x40001c2c;\nppRxProtoProc = 0x40001c30;\nppSearchTxQueue = 0x40001c34;\nppSearchTxframe = 0x40001c38;\nppSelectNextQueue = 0x40001c3c;\nppSubFromAMPDU = 0x40001c40;\nppTask = 0x40001c44;\nppTxPkt = 0x40001c48;\nppTxProtoProc = 0x40001c4c;\nppTxqUpdateBitmap = 0x40001c50;\npp_coex_tx_request = 0x40001c54;\npp_hdrsize = 0x40001c58;\npp_post = 0x40001c5c;\npp_process_hmac_waiting_txq = 0x40001c60;\nrcGetAmpduSched = 0x40001c64;\nrcUpdateRxDone = 0x40001c68;\nrc_get_trc = 0x40001c6c;\nrc_get_trc_by_index = 0x40001c70;\nrcAmpduLowerRate = 0x40001c74;\nrcampduuprate = 0x40001c78;\nrcClearCurAMPDUSched = 0x40001c7c;\nrcClearCurSched = 0x40001c80;\nrcClearCurStat = 0x40001c84;\nrcGetSched = 0x40001c88;\nrcLowerSched = 0x40001c8c;\nrcSetTxAmpduLimit = 0x40001c90;\nrcTxUpdatePer = 0x40001c94;\nrcUpdateAckSnr = 0x40001c98;\nrcUpdateRate = 0x40001c9c;\nrcUpdateTxDone = 0x40001ca0;\nrcUpdateTxDoneAmpdu2 = 0x40001ca4;\nrcUpSched = 0x40001ca8;\nrssi_margin = 0x40001cac;\nrx11NRate2AMPDULimit = 0x40001cb0;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001cb4;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001cb8;\ntrc_calc_duration = 0x40001cbc;\ntrc_isTxAmpduOperational = 0x40001cc0;\ntrc_onAmpduOp = 0x40001cc4;\nTRC_PER_IS_GOOD = 0x40001cc8;\ntrc_SetTxAmpduState = 0x40001ccc;\ntrc_tid_isTxAmpduOperational = 0x40001cd0;\ntrcAmpduSetState = 0x40001cd4;\nwDevCheckBlockError = 0x40001cd8;\nwDev_AppendRxBlocks = 0x40001cdc;\nwDev_DiscardFrame = 0x40001ce0;\nwDev_GetNoiseFloor = 0x40001ce4;\nwDev_IndicateAmpdu = 0x40001ce8;\nwDev_IndicateFrame = 0x40001cec;\nwdev_mac_reg_load = 0x40001cf0;\nwdev_mac_reg_store = 0x40001cf4;\nwdev_mac_special_reg_load = 0x40001cf8;\nwdev_mac_special_reg_store = 0x40001cfc;\nwdev_mac_wakeup = 0x40001d00;\nwdev_mac_sleep = 0x40001d04;\nwDev_ProcessFiq = 0x40001d08;\nwDev_ProcessRxSucData = 0x40001d0c;\nwdevProcessRxSucDataAll = 0x40001d10;\nwdev_csi_len_align = 0x40001d14;\nppDequeueTxDone_Locked = 0x40001d18;\nppProcTxDone = 0x40001d1c;\npm_tx_data_done_process = 0x40001d20;\nconfig_is_cache_tx_buf_enabled = 0x40001d24;\nppMapWaitTxq = 0x40001d28;\nppProcessWaitingQueue = 0x40001d2c;\nppDisableQueue = 0x40001d30;\npm_allow_tx = 0x40001d34;\nwdev_is_data_in_rxlist = 0x40001d38;\nppProcTxCallback = 0x40001d3c;\npm_is_open = 0x40001d40;\npm_wake_up = 0x40001d44;\npm_wake_done = 0x40001d48;\npm_disable_disconnected_sleep_delay_timer = 0x40001d4c;\npm_enable_disconnected_sleep_delay_timer = 0x40001d50;\nhal_mac_get_txq_state = 0x40001d54;\nhal_mac_clr_txq_state = 0x40001d58;\nhal_mac_tx_set_cca = 0x40001d5c;\nhal_mac_set_txq_invalid = 0x40001d60;\nhal_mac_txq_disable = 0x40001d64;\nhal_mac_is_txq_enabled = 0x40001d68;\nhal_mac_get_txq_pmd = 0x40001d6c;\nlmacDiscardFrameExchangeSequence = 0x40001d70;\nlmacDisableTransmit = 0x40001d74;\nlmacProcessTxTimeout = 0x40001d78;\nlmacProcessTxSuccess = 0x40001d7c;\nlmacProcessCollision = 0x40001d80;\nlmacProcessTxRtsError = 0x40001d84;\nlmacProcessCtsTimeout = 0x40001d88;\nlmacProcessTxComplete = 0x40001d8c;\nlmacProcessAckTimeout = 0x40001d90;\nlmacProcessTxError = 0x40001d94;\nlmacProcessTxseckiderr = 0x40001d98;\nrcReachRetryLimit = 0x40001d9c;\nlmacProcessShortRetryFail = 0x40001da0;\nlmacEndRetryAMPDUFail = 0x40001da4;\nppFillAMPDUBar = 0x40001da8;\nrcGetRate = 0x40001dac;\nppReSendBar = 0x40001db0;\nlmacProcessLongRetryFail = 0x40001db4;\nlmacRetryTxFrame = 0x40001db8;\nlmacProcessCollisions_task = 0x40001dbc;\nlmacProcessTxopQComplete = 0x40001dc0;\nlmacInitAc = 0x40001dc4;\nlmacInit = 0x40001dc8;\nmac_tx_set_txop_q = 0x40001dcc;\nhal_init = 0x40001dd0;\nhal_mac_rx_set_policy = 0x40001dd4;\nhal_mac_set_bssid = 0x40001dd8;\nmac_rx_policy_init = 0x40001ddc;\nmac_txrx_init = 0x40001de0;\nmac_rxbuf_init = 0x40001de4;\nmac_last_rxbuf_init = 0x40001de8;\nhal_attenna_init = 0x40001dec;\nhal_timer_update_by_rtc = 0x40001df0;\nhal_coex_pti_init = 0x40001df4;\nlmac_stop_hw_txq = 0x40001df8;\nppDirectRecycleAmpdu = 0x40001dfc;\nesp_wifi_internal_set_rts = 0x40001e00;\nesp_wifi_internal_get_rts = 0x40001e04;\nppTxFragmentProc = 0x40001e08;\n\/*esf_buf_setup = 0x40001e0c;*\/\nhal_agreement_add_rx_ba = 0x40001e10;\nhal_agreement_del_rx_ba = 0x40001e14;\nhal_crypto_set_key_entry = 0x40001e18;\nhal_crypto_get_key_entry = 0x40001e1c;\nhal_crypto_clr_key_entry = 0x40001e20;\nconfig_get_wifi_task_stack_size = 0x40001e24;\npp_create_task = 0x40001e28;\nhal_set_sta_tsf_wakeup = 0x40001e2c;\nhal_set_rx_beacon_pti = 0x40001e30;\npm_start = 0x40001e34;\npm_stop = 0x40001e38;\nhal_disable_sta_tbtt = 0x40001e3c;\nppCalTxopDur = 0x40001e40;\nwDev_IndicateCtrlFrame = 0x40001e44;\nhal_enable_sta_tbtt = 0x40001e48;\nhal_set_sta_tbtt = 0x40001e4c;\npm_update_next_tbtt = 0x40001e50;\npm_set_sleep_type = 0x40001e54;\nwDev_Rxbuf_Init = 0x40001e58;\nwDev_Rxbuf_Deinit = 0x40001e5c;\nppCalTkipMic = 0x40001e60;\nwDev_SnifferRxData = 0x40001e64;\nhal_crypto_enable = 0x40001e68;\nhal_crypto_disable = 0x40001e6c;\nwDev_Insert_KeyEntry = 0x40001e70;\nwDev_remove_KeyEntry = 0x40001e74;\nrc_enable_trc = 0x40001e78;\nrc_set_per_conn_fix_rate = 0x40001e7c;\nwdev_csi_rx_process = 0x40001e80;\nwDev_SnifferRxAmpdu = 0x40001e84;\nhal_mac_tsf_reset = 0x40001e88;\ndbg_lmac_statis_dump = 0x40001e8c;\ndbg_lmac_rxtx_statis_dump = 0x40001e90;\ndbg_lmac_hw_statis_dump = 0x40001e94;\ndbg_lmac_diag_statis_dump = 0x40001e98;\ndbg_lmac_ps_statis_dump = 0x40001e9c;\npp_timer_do_process = 0x40001ea0;\nrcUpdateAMPDUParam = 0x40001ea4;\nrcUpdatePhyMode = 0x40001ea8;\nrcGetHighestRateIdx = 0x40001eac;\npm_tx_null_data_done_process = 0x40001eb0;\npm_tx_data_process = 0x40001eb4;\npm_attach = 0x40001eb8;\npm_coex_schm_process = 0x40001ebc;\nppInitTxq = 0x40001ec0;\npp_attach = 0x40001ec4;\npp_deattach = 0x40001ec8;\npm_on_probe_resp_rx = 0x40001ecc;\nhal_set_sta_tsf = 0x40001ed0;\nic_update_sta_tsf = 0x40001ed4;\nic_tx_pkt = 0x40001ed8;\npm_send_probe_stop = 0x40001edc;\npm_send_probe_start = 0x40001ee0;\npm_on_coex_schm_process_restart = 0x40001ee4;\nhal_mac_set_rxq_policy = 0x40001ee8;\nhal_sniffer_enable = 0x40001eec;\nhal_sniffer_disable = 0x40001ef0;\nhal_sniffer_rx_set_promis = 0x40001ef4;\nhal_sniffer_rx_clr_statistics = 0x40001ef8;\nhal_sniffer_set_promis_misc_pkt = 0x40001efc;\ntsf_hal_set_tsf_enable = 0x40001f00;\ntsf_hal_set_tsf_disable = 0x40001f04;\ntsf_hal_is_tsf_enabled = 0x40001f08;\ntsf_hal_set_modem_wakeup_early_time = 0x40001f0c;\ntsf_hal_get_counter_value = 0x40001f10;\ntsf_hal_set_counter_value = 0x40001f14;\ntsf_hal_get_time = 0x40001f18;\ntsf_hal_set_time = 0x40001f1c;\ntsf_hal_set_tbtt_enable = 0x40001f20;\ntsf_hal_set_tbtt_disable = 0x40001f24;\ntsf_hal_set_tbtt_intr_enable = 0x40001f28;\ntsf_hal_set_tbtt_intr_disable = 0x40001f2c;\ntsf_hal_set_tbtt_soc_wakeup_enable = 0x40001f30;\ntsf_hal_set_tbtt_soc_wakeup_disable = 0x40001f34;\ntsf_hal_set_tbtt_start_time = 0x40001f38;\ntsf_hal_set_tbtt_early_time = 0x40001f3c;\ntsf_hal_set_tbtt_interval = 0x40001f40;\ntsf_hal_get_tbtt_interval = 0x40001f44;\ntsf_hal_set_timer_enable = 0x40001f48;\ntsf_hal_set_timer_disable = 0x40001f4c;\ntsf_hal_set_timer_target = 0x40001f50;\ntsf_hal_get_timer_target = 0x40001f54;\ntsf_hal_set_timer_intr_enable = 0x40001f58;\ntsf_hal_set_timer_intr_disable = 0x40001f5c;\ntsf_hal_set_timer_soc_wakeup_enable = 0x40001f60;\ntsf_hal_set_timer_soc_wakeup_disable = 0x40001f64;\npm_disconnected_wake = 0x40001f68;\npm_get_connectionless_status = 0x40001f6c;\npm_update_by_connectionless_status = 0x40001f70;\npm_connectionless_wake_interval_timeout_process = 0x40001f74;\npm_connectionless_wake_window_timeout_process = 0x40001f78;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff4fbbc;\npTxRx = 0x3fcdfdec;\nlmacConfMib_ptr = 0x3fcdfde8;\nour_wait_eb = 0x3fcdfde4;\nour_tx_eb = 0x3fcdfde0;\npp_wdev_funcs = 0x3fcdfddc;\ng_osi_funcs_p = 0x3fcdfdd8;\nwDevCtrl_ptr = 0x3fcdfdd4;\ng_wdev_last_desc_reset_ptr = 0x3ff4fbb8;\nwDevMacSleep_ptr = 0x3fcdfdd0;\ng_lmac_cnt_ptr = 0x3fcdfdcc;\nour_controls_ptr = 0x3ff4fbb4;\npp_sig_cnt_ptr = 0x3fcdfdc8;\ng_eb_list_desc_ptr = 0x3fcdfdc4;\ns_fragment_ptr = 0x3fcdfdc0;\nif_ctrl_ptr = 0x3fcdfdbc;\ng_intr_lock_mux = 0x3fcdfdb8;\ng_wifi_global_lock = 0x3fcdfdb4;\ns_wifi_queue = 0x3fcdfdb0;\npp_task_hdl = 0x3fcdfdac;\ns_pp_task_create_sem = 0x3fcdfda8;\ns_pp_task_del_sem = 0x3fcdfda4;\ng_wifi_menuconfig_ptr = 0x3fcdfda0;\nxphyQueue = 0x3fcdfd9c;\nap_no_lr_ptr = 0x3fcdfd98;\nrc11BSchedTbl_ptr = 0x3fcdfd94;\nrc11NSchedTbl_ptr = 0x3fcdfd90;\nrcLoRaSchedTbl_ptr = 0x3fcdfd8c;\nBasicOFDMSched_ptr = 0x3fcdfd88;\ntrc_ctl_ptr = 0x3fcdfd84;\ng_pm_cnt_ptr = 0x3fcdfd80;\ng_pm_ptr = 0x3fcdfd7c;\ng_pm_cfg_ptr = 0x3fcdfd78;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdfd74;\ng_txop_queue_status_ptr = 0x3fcdfd70;\ng_mac_sleep_en_ptr = 0x3fcdfd6c;\ng_mesh_is_root_ptr = 0x3fcdfd68;\ng_mesh_topology_ptr = 0x3fcdfd64;\ng_mesh_init_ps_type_ptr = 0x3fcdfd60;\ng_mesh_is_started_ptr = 0x3fcdfd5c;\ng_config_func = 0x3fcdfd58;\ng_net80211_tx_func = 0x3fcdfd54;\ng_timer_func = 0x3fcdfd50;\ns_michael_mic_failure_cb = 0x3fcdfd4c;\nwifi_sta_rx_probe_req = 0x3fcdfd48;\ng_tx_done_cb_func = 0x3fcdfd44;\ng_per_conn_trc = 0x3fcdfd28;\ns_encap_amsdu_func = 0x3fcdfd24;\nbars = 0x3fcdfc84;\neb_txdesc_space = 0x3fcdfbf4;\neb_space = 0x3fcdfb54;\ng_pd_mac_in_light_sleep = 0x3fcdfb50;\ns_fix_rate_mask = 0x3fcdfb4c;\ns_fix_rate = 0x3fcdfb44;\ng_wdev_csi_rx = 0x3fcdfb40;\ng_wdev_csi_rx_ctx = 0x3fcdfb3c;\nBcnSendTick = 0x3fcdfb38;\ng_pp_timer_info_ptr = 0x3fcdfb34;\nrcP2P11NSchedTbl_ptr = 0x3fcdfb30;\nrcP2P11GSchedTbl_ptr = 0x3fcdfb2c;\nrc11GSchedTbl_ptr = 0x3fcdfb28;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001f7c;\nampdu_dispatch = 0x40001f80;\nampdu_dispatch_all = 0x40001f84;\nampdu_dispatch_as_many_as_possible = 0x40001f88;\nampdu_dispatch_movement = 0x40001f8c;\nampdu_dispatch_upto = 0x40001f90;\nchm_is_at_home_channel = 0x40001f94;\ncnx_node_is_existing = 0x40001f98;\ncnx_node_search = 0x40001f9c;\nic_ebuf_recycle_rx = 0x40001fa0;\nic_ebuf_recycle_tx = 0x40001fa4;\nic_reset_rx_ba = 0x40001fa8;\nieee80211_align_eb = 0x40001fac;\nieee80211_ampdu_reorder = 0x40001fb0;\nieee80211_ampdu_start_age_timer = 0x40001fb4;\nieee80211_encap_esfbuf = 0x40001fb8;\nieee80211_is_tx_allowed = 0x40001fbc;\nieee80211_output_pending_eb = 0x40001fc0;\nieee80211_output_process = 0x40001fc4;\nieee80211_set_tx_desc = 0x40001fc8;\nsta_input = 0x40001fcc;\nwifi_get_macaddr = 0x40001fd0;\nwifi_rf_phy_disable = 0x40001fd4;\nwifi_rf_phy_enable = 0x40001fd8;\nic_ebuf_alloc = 0x40001fdc;\nieee80211_classify = 0x40001fe0;\nieee80211_copy_eb_header = 0x40001fe4;\nieee80211_recycle_cache_eb = 0x40001fe8;\nieee80211_search_node = 0x40001fec;\nroundup2 = 0x40001ff0;\nieee80211_crypto_encap = 0x40001ff4;\nieee80211_crypto_decap = 0x40001ff8;\nieee80211_decap = 0x40001ffc;\nieee80211_set_tx_pti = 0x40002000;\nwifi_is_started = 0x40002004;\nieee80211_gettid = 0x40002008;\nieee80211_ccmp_decrypt = 0x4000200c;\nieee80211_ccmp_encrypt = 0x40002010;\nccmp_encap = 0x40002014;\nccmp_decap = 0x40002018;\ntkip_encap = 0x4000201c;\ntkip_decap = 0x40002020;\nwep_encap = 0x40002024;\nwep_decap = 0x40002028;\ndbg_hmac_rxtx_statis_dump = 0x4000202c;\ndbg_hmac_statis_dump = 0x40002030;\nieee80211_send_action_vendor_spec = 0x40002034;\nieee80211_deauth_construct = 0x40002040;\nieee80211_disassoc_construct = 0x40002044;\nieee80211_vnd_lora_ie_size = 0x40002048;\nieee80211_vnd_ie_size = 0x4000204c;\nieee80211_add_ssid = 0x40002050;\nieee80211_add_rates = 0x40002054;\nieee80211_add_xrates = 0x40002058;\nieee80211_is_ht_cipher = 0x4000205c;\nieee80211_assoc_resp_construct = 0x40002064;\nieee80211_setup_lr_rates = 0x40002068;\nieee80211_ht_node_init = 0x4000206c;\nieee80211_is_support_rate = 0x40002070;\nieee80211_setup_rates = 0x40002074;\nieee80211_is_lr_only = 0x40002078;\nieee80211_setup_phy_mode = 0x4000207c;\nieee80211_sta_is_connected = 0x40002080;\ncurrent_task_is_wifi_task = 0x40002084;\nwifi_get_init_state = 0x40002088;\nieee80211_timer_process = 0x4000208c;\ncnx_coexist_timeout = 0x40002090;\n\/* sta_recv_mgmt = 0x40002094;*\/\nieee80211_send_setup = 0x40002098;\nieee80211_send_probereq = 0x4000209c;\nsta_auth_shared = 0x400020a4;\ncnx_coexist_timeout_process = 0x400020ac;\nieee80211_alloc_challenge = 0x400020b0;\ncnx_assoc_timeout = 0x400020b4;\nieee80211_vnd_ie_set = 0x400020b8;\nieee80211_vnd_lora_ie_set = 0x400020bc;\nieee80211_add_wme_param = 0x400020c0;\nieee80211_add_dsparams = 0x400020c4;\nieee80211_add_csa = 0x400020c8;\nieee80211_add_extcap = 0x400020cc;\nieee80211_regdomain_get_country = 0x400020d0;\nieee80211_add_countryie = 0x400020d4;\nieee80211_amsdu_adjust_head = 0x400020dc;\nieee80211_amsdu_adjust_last_length = 0x400020e0;\nieee80211_amsdu_send_check = 0x400020e4;\nieee80211_amsdu_encap_check = 0x400020e8;\nieee80211_amsdu_length_check = 0x400020ec;\nieee80211_encap_amsdu = 0x400020f0;\nieee80211_output_raw_process = 0x400020f4;\nieee80211_raw_frame_sanity_check = 0x400020fc;\nieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;\nieee80211_crypto_aes_128_cmac_decrypt = 0x40002104;\nieee80211_alloc_tx_buf = 0x40002108;\nieee80211_output_do = 0x4000210c;\nieee80211_send_nulldata = 0x40002110;\nieee80211_setup_robust_mgmtframe = 0x40002114;\nieee80211_mgmt_output = 0x40002118;\nieee80211_encap_null_data = 0x4000211c;\nieee80211_send_deauth = 0x40002120;\nieee80211_alloc_deauth = 0x40002124;\nieee80211_send_proberesp = 0x40002128;\nieee80211_tx_mgt_cb = 0x4000212c;\nieee80211_getcapinfo = 0x40002130;\nsta_rx_csa = 0x40002134;\nsta_recv_sa_query_resp = 0x40002144;\nieee80211_set_max_rate = 0x4000214c;\nic_set_sta = 0x40002150;\nieee80211_parse_wpa = 0x40002158;\nieee80211_add_assoc_req_ies = 0x40002160;\nieee80211_add_probe_req_ies = 0x40002164;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdfb24;\ng_scan = 0x3fcdfb20;\ng_chm = 0x3fcdfb1c;\ng_ic_ptr = 0x3fcdfb18;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_tx_cacheq_ptr = 0x3fcdfb14;\ns_netstack_free = 0x3fcdfb10;\nmesh_rxcb = 0x3fcdfb0c;\nsta_rxcb = 0x3fcdfb08;\nccmp_ptr = 0x3fcdfb04;\ns_wifi_nvs_ptr = 0x3fcdfb00;\ntkip_ptr = 0x3fcdfafc;\nwep_ptr = 0x3fcdfaf8;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_misc_nvs = 0x3fcdfaf0;\ns_wifi_init_state = 0x3fcdfac0;\ns_wifi_task_hdl = 0x3fcdfaec;\nin_rssi_adjust = 0x3fcdfae8;\nrssi_saved = 0x3fcdfae0;\nrssi_index = 0x3fcdfadc;\ns_sa_query_retries = 0x3fcdfad8;\ns_sa_query_success = 0x3fcdfad5;\ng_sta_connected_flag = 0x3fcdfad4;\nwpa_crypto_funcs_ptr = 0x3fcdfad0;\ns_netstack_ref = 0x3fcdfacc;\nsta_csa_timer_ptr = 0x3fcdfac8;\ns_trans_id = 0x3fcdfac4;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x40002168;\ncoex_bt_release = 0x4000216c;\ncoex_bt_request = 0x40002170;\ncoex_core_ble_conn_dyn_prio_get = 0x40002174;\ncoex_core_event_duration_get = 0x40002178;\ncoex_core_pti_get = 0x4000217c;\ncoex_core_release = 0x40002180;\ncoex_core_request = 0x40002184;\ncoex_core_status_get = 0x40002188;\ncoex_core_timer_idx_get = 0x4000218c;\ncoex_event_duration_get = 0x40002190;\ncoex_hw_timer_disable = 0x40002194;\ncoex_hw_timer_enable = 0x40002198;\ncoex_hw_timer_set = 0x4000219c;\ncoex_schm_interval_set = 0x400021a0;\ncoex_schm_lock = 0x400021a4;\ncoex_schm_unlock = 0x400021a8;\ncoex_status_get = 0x400021ac;\ncoex_wifi_release = 0x400021b0;\nesp_coex_ble_conn_dynamic_prio_get = 0x400021b4;\ncoex_hw_timer_tick_get = 0x400021b8;\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdfabc;\ncoex_pti_tab_ptr = 0x3fcdfab8;\ncoex_schm_env_ptr = 0x3fcdfab4;\ncoexist_funcs = 0x3fcdfab0;\ng_coa_funcs_p = 0x3fcdfaac;\ng_coex_param_ptr = 0x3fcdfaa8;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_param_addr = 0x400021bc;\nphy_get_romfuncs = 0x400021c0;\nchip729_phyrom_version = 0x400021c4;\nchip729_phyrom_version_num = 0x400021c8;\nrom_get_rc_dout = 0x400021cc;\nrc_cal = 0x400021d0;\nphy_analog_delay_cal = 0x400021d4;\nphy_rx_rifs_en = 0x400021d8;\nphy_current_level_set = 0x400021dc;\nphy_bbpll_en_usb = 0x400021e0;\nphy_bt_power_track = 0x400021e4;\nphy_xpd_tsens = 0x400021e8;\nbb_wdt_rst_enable = 0x400021ec;\nbb_wdt_int_enable = 0x400021f0;\nbb_wdt_timeout_clear = 0x400021f4;\nbb_wdt_get_status = 0x400021f8;\nrom_enter_critical_phy = 0x400021fc;\nrom_exit_critical_phy = 0x40002200;\nrom_bb_bss_cbw40 = 0x40002204;\nrom_set_chan_reg = 0x40002208;\nabs_temp = 0x4000220c;\nset_chan_cal_interp = 0x40002210;\nloopback_mode_en = 0x40002214;\nget_data_sat = 0x40002218;\nphy_byte_to_word = 0x4000221c;\nphy_get_rx_freq = 0x40002220;\ni2c_master_reset = 0x40002224;\nchan14_mic_enable = 0x40002228;\nchan14_mic_cfg = 0x4000222c;\nset_adc_rand = 0x40002230;\nphy_set_most_tpw = 0x40002234;\nphy_get_most_tpw = 0x40002238;\nesp_tx_state_out = 0x4000223c;\nphy_get_adc_rand = 0x40002240;\nphy_internal_delay = 0x40002244;\nphy_ftm_comp = 0x40002248;\nphy_11p_set = 0x4000224c;\nphy_freq_mem_backup = 0x40002250;\nant_dft_cfg = 0x40002254;\nant_wifitx_cfg = 0x40002258;\nant_wifirx_cfg = 0x4000225c;\nant_bttx_cfg = 0x40002260;\nant_btrx_cfg = 0x40002264;\nphy_chan_dump_cfg = 0x40002268;\nphy_enable_low_rate = 0x4000226c;\nphy_disable_low_rate = 0x40002270;\nphy_dig_reg_backup = 0x40002274;\nphy_chan_filt_set = 0x40002278;\nphy_rx11blr_cfg = 0x4000227c;\nset_cca = 0x40002280;\nset_rx_sense = 0x40002284;\nrx_gain_force = 0x40002288;\nrom_phy_en_hw_set_freq = 0x4000228c;\nrom_phy_dis_hw_set_freq = 0x40002290;\nwr_rf_freq_mem = 0x40002294;\nfreq_i2c_write_set = 0x40002298;\nwrite_pll_cap_mem = 0x4000229c;\npll_dac_mem_update = 0x400022a0;\npll_cap_mem_update = 0x400022a4;\nget_rf_freq_cap = 0x400022a8;\nget_rf_freq_init = 0x400022ac;\nfreq_get_i2c_data = 0x400022b0;\nfreq_i2c_data_write = 0x400022b4;\nset_chan_freq_hw_init = 0x400022b8;\nset_chan_freq_sw_start = 0x400022bc;\nrom_get_i2c_read_mask = 0x400022c0;\nrom_get_i2c_mst0_mask = 0x400022c4;\nrom_get_i2c_hostid = 0x400022c8;\nrom_chip_i2c_readReg_org = 0x400022cc;\nrom_chip_i2c_readReg = 0x400022d0;\nrom_i2c_paral_set_mst0 = 0x400022d4;\nrom_i2c_paral_set_read = 0x400022d8;\nrom_i2c_paral_read = 0x400022dc;\nrom_i2c_paral_write = 0x400022e0;\nrom_i2c_paral_write_num = 0x400022e4;\nrom_i2c_paral_write_mask = 0x400022e8;\nrom_i2c_readReg = 0x400022ec;\nrom_chip_i2c_writeReg = 0x400022f0;\nrom_i2c_writeReg = 0x400022f4;\nrom_i2c_readReg_Mask = 0x400022f8;\nrom_i2c_writeReg_Mask = 0x400022fc;\nrom_set_txcap_reg = 0x40002300;\ni2c_sar2_init_code = 0x40002304;\nphy_i2c_init1 = 0x40002308;\nphy_i2c_init2 = 0x4000230c;\nphy_get_i2c_data = 0x40002310;\nbias_reg_set = 0x40002314;\ni2c_rc_cal_set = 0x40002318;\ni2c_bbpll_set = 0x4000231c;\nrom_phy_xpd_rf = 0x40002320;\nphy_wakeup_init_rom = 0x40002324;\nregister_chipv7_phy_init_param = 0x40002328;\nphy_reg_init = 0x4000232c;\nphy_close_rf_rom = 0x40002330;\nrom_pbus_force_mode = 0x40002334;\nrom_pbus_rd_addr = 0x40002338;\nrom_pbus_rd_shift = 0x4000233c;\nrom_pbus_force_test = 0x40002340;\nrom_pbus_rd = 0x40002344;\nrom_pbus_debugmode = 0x40002348;\nrom_pbus_workmode = 0x4000234c;\nrom_pbus_set_rxgain = 0x40002350;\nrom_pbus_xpd_rx_off = 0x40002354;\nrom_pbus_xpd_rx_on = 0x40002358;\nrom_pbus_xpd_tx_off = 0x4000235c;\nrom_pbus_xpd_tx_on = 0x40002360;\nrom_pbus_set_dco = 0x40002364;\nrom_set_loopback_gain = 0x40002368;\nrom_txcal_debuge_mode = 0x4000236c;\nrom_txcal_work_mode = 0x40002370;\nset_pbus_mem = 0x40002374;\nrom_pwdet_sar2_init = 0x40002378;\nrom_en_pwdet = 0x4000237c;\nrom_get_sar_sig_ref = 0x40002380;\nrom_pwdet_tone_start = 0x40002384;\nrom_get_tone_sar_dout = 0x40002388;\nrom_get_fm_sar_dout = 0x4000238c;\nrom_txtone_linear_pwr = 0x40002390;\nrom_get_power_db = 0x40002394;\nrom_meas_tone_pwr_db = 0x40002398;\nrom_pkdet_vol_start = 0x4000239c;\nrom_read_sar_dout = 0x400023a0;\nrom_read_sar2_code = 0x400023a4;\nrom_get_sar2_vol = 0x400023a8;\nrom_get_pll_vol = 0x400023ac;\nrom_tx_pwctrl_bg_init = 0x400023b0;\nrom_phy_pwdet_always_en = 0x400023b4;\nrom_phy_pwdet_onetime_en = 0x400023b8;\nlinear_to_db = 0x400023bc;\nrom_disable_agc = 0x400023c0;\nrom_enable_agc = 0x400023c4;\nrom_disable_wifi_agc = 0x400023c8;\nrom_enable_wifi_agc = 0x400023cc;\nrom_write_gain_mem = 0x400023d0;\nrom_bb_bss_cbw40_dig = 0x400023d4;\nrom_cbw2040_cfg = 0x400023d8;\nrom_mac_tx_chan_offset = 0x400023dc;\nrom_tx_paon_set = 0x400023e0;\nrom_i2cmst_reg_init = 0x400023e4;\nrom_bt_gain_offset = 0x400023e8;\nrom_fe_reg_init = 0x400023ec;\nrom_mac_enable_bb = 0x400023f0;\nrom_bb_wdg_cfg = 0x400023f4;\nrom_fe_txrx_reset = 0x400023f8;\nrom_set_rx_comp = 0x400023fc;\nrom_write_chan_freq = 0x40002400;\nrom_agc_reg_init = 0x40002404;\nrom_bb_reg_init = 0x40002408;\nrom_write_txrate_power_offset = 0x4000240c;\nrom_open_i2c_xpd = 0x40002410;\nrom_txiq_set_reg = 0x40002414;\nrom_rxiq_set_reg = 0x40002418;\nrom_phy_bbpll_cal = 0x4000241c;\nphy_disable_cca = 0x40002420;\nphy_enable_cca = 0x40002424;\nforce_txon = 0x40002428;\nset_txclk_en = 0x4000242c;\nset_rxclk_en = 0x40002430;\nstart_tx_tone_step = 0x40002434;\nstop_tx_tone = 0x40002438;\nbb_wdg_test_en = 0x4000243c;\nnoise_floor_auto_set = 0x40002440;\nread_hw_noisefloor = 0x40002444;\niq_corr_enable = 0x40002448;\nbt_tx_dig_gain = 0x4000244c;\nwifi_tx_dig_reg = 0x40002450;\nwifi_agc_sat_gain = 0x40002454;\nphy_ant_init = 0x40002458;\nphy_set_bbfreq_init = 0x4000245c;\nwifi_fbw_sel = 0x40002460;\nphy_rx_sense_set = 0x40002464;\ntx_state_set = 0x40002468;\nphy_close_pa = 0x4000246c;\nbt_filter_reg = 0x40002470;\nphy_freq_correct = 0x40002474;\nset_pbus_reg = 0x40002478;\nwifi_rifs_mode_en = 0x4000247c;\nrfagc_disable = 0x40002480;\nrom_restart_cal = 0x40002484;\nrom_write_rfpll_sdm = 0x40002488;\nrom_wait_rfpll_cal_end = 0x4000248c;\nrom_rfpll_set_freq = 0x40002490;\nrom_rfpll_cap_init_cal = 0x40002494;\nrom_set_rfpll_freq = 0x40002498;\nrom_write_pll_cap = 0x4000249c;\nrom_read_pll_cap = 0x400024a0;\nmhz2ieee = 0x400024a4;\nchan_to_freq = 0x400024a8;\nset_rf_freq_offset = 0x400024ac;\nset_channel_rfpll_freq = 0x400024b0;\nrfpll_cap_correct = 0x400024b4;\nphy_set_freq = 0x400024b8;\ncorrect_rfpll_offset = 0x400024bc;\npll_vol_cal = 0x400024c0;\nchip_v7_set_chan_misc = 0x400024c4;\nchip_v7_set_chan = 0x400024c8;\nchip_v7_set_chan_offset = 0x400024cc;\nchip_v7_set_chan_ana = 0x400024d0;\nset_chanfreq = 0x400024d4;\nrom_rxiq_cover_mg_mp = 0x400024d8;\nrom_rfcal_rxiq = 0x400024dc;\nrom_get_rfcal_rxiq_data = 0x400024e0;\nrom_pbus_rx_dco_cal = 0x400024e4;\nrom_rxdc_est_min = 0x400024e8;\nrom_pbus_rx_dco_cal_1step = 0x400024ec;\nrom_set_lb_txiq = 0x400024f0;\nrom_set_rx_gain_cal_iq = 0x400024f4;\nrom_set_rx_gain_cal_dc = 0x400024f8;\niq_est_enable = 0x400024fc;\niq_est_disable = 0x40002500;\ndc_iq_est = 0x40002504;\nset_cal_rxdc = 0x40002508;\nrxiq_get_mis = 0x4000250c;\nspur_reg_write_one_tone = 0x40002510;\nspur_cal = 0x40002514;\nspur_coef_cfg = 0x40002518;\ngen_rx_gain_table = 0x4000251c;\nwr_rx_gain_mem = 0x40002520;\nset_rx_gain_param = 0x40002524;\nset_rx_gain_table = 0x40002528;\nrom_tester_wifi_cali = 0x4000252c;\nesp_recover_efuse_data = 0x40002530;\nbt_track_pll_cap = 0x40002534;\nrfpll_cap_track = 0x40002538;\nphy_param_track = 0x4000253c;\ntxpwr_correct = 0x40002540;\ntxpwr_cal_track = 0x40002544;\n\/* tx_pwctrl_background = 0x40002548;*\/\nbt_track_tx_power = 0x4000254c;\nwifi_track_tx_power = 0x40002550;\nrom_code_to_temp = 0x40002554;\nrom_tsens_index_to_dac = 0x40002558;\nrom_tsens_index_to_offset = 0x4000255c;\nrom_tsens_dac_cal = 0x40002560;\nrom_tsens_code_read = 0x40002564;\nrom_tsens_temp_read = 0x40002568;\nrom_temp_to_power = 0x4000256c;\ntsens_read_init = 0x40002570;\nget_temp_init = 0x40002574;\nrom_txiq_cover = 0x40002578;\nrom_rfcal_txiq = 0x4000257c;\nrom_get_power_atten = 0x40002580;\nrom_tx_pwctrl_init_cal = 0x40002584;\nbt_txdc_cal = 0x40002588;\nbt_txiq_cal = 0x4000258c;\ntxiq_cal_init = 0x40002590;\ntxdc_cal_init = 0x40002594;\ntxdc_cal_v70 = 0x40002598;\ntxiq_get_mis_pwr = 0x4000259c;\npwdet_ref_code = 0x400025a0;\npwdet_code_cal = 0x400025a4;\nrfcal_txcap = 0x400025a8;\ntx_cap_init = 0x400025ac;\nrfcal_pwrctrl = 0x400025b0;\ntx_pwctrl_init = 0x400025b4;\nbt_tx_pwctrl_init = 0x400025b8;\nbt_txpwr_freq = 0x400025bc;\nrom_txbbgain_to_index = 0x400025c0;\nrom_index_to_txbbgain = 0x400025c4;\nrom_bt_index_to_bb = 0x400025c8;\nrom_bt_bb_to_index = 0x400025cc;\nrom_bt_get_tx_gain = 0x400025d0;\nrom_get_tx_gain_value = 0x400025d4;\nrom_wifi_get_tx_gain = 0x400025d8;\nrom_set_tx_gain_mem = 0x400025dc;\nrom_get_rate_fcc_index = 0x400025e0;\nrom_get_chan_target_power = 0x400025e4;\nrom_wifi_tx_dig_gain = 0x400025e8;\nrom_wifi_set_tx_gain = 0x400025ec;\nrom_bt_set_tx_gain = 0x400025f0;\nwifi_11g_rate_chg = 0x400025f4;\nbt_chan_pwr_interp = 0x400025f8;\nbt_tx_gain_init = 0x400025fc;\n\/* Data (.data, .bss, .rodata) *\/\nphy_param_rom = 0x3fcdfaa4;\n\n\n\/***************************************\n Group rom_btbb\n ***************************************\/\n\n\/* Functions *\/\nbt_agc_gain_offset = 0x40002600;\nbt_agc_gain_max = 0x40002604;\nbt_set_rx_comp = 0x40002608;\nbt_agc_gain_set = 0x4000260c;\nbt_agc_rssi_thresh = 0x40002610;\nbt_agc_target_set = 0x40002614;\nbt_agc_restart_set = 0x40002618;\nbt_agc_recorrect_set = 0x4000261c;\nbt_agc_detect_set = 0x40002620;\nbt_bb_rx_correlator_set = 0x40002624;\nbt_bb_rx_dpo_set = 0x40002628;\nbt_bb_rx_filter_sel = 0x4000262c;\nbt_bb_rx_set1 = 0x40002630;\nbt_bb_v2_rx_set = 0x40002634;\nbt_bb_v2_tx_set = 0x40002638;\nbt_bb_tx_cca_set = 0x4000263c;\nbt_bb_tx_cca_period = 0x40002640;\nbt_bb_tx_cca_fifo_reset = 0x40002644;\nbt_bb_tx_cca_fifo_empty = 0x40002648;\nbt_bb_tx_cca_fifo_full = 0x4000264c;\nbt_bb_tx_cca_fifo_count = 0x40002650;\nbt_bb_tx_cca_fifo_read = 0x40002654;\ncoex_pti_v2 = 0x40002658;\nbt_bb_set_le_tx_on_delay = 0x4000265c;\nbt_bb_set_corr_thresh_le = 0x40002660;\n","old_contents":"\/*\n * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/* ROM function interface esp32c2.rom.ld for esp32c2\n *\n *\n * Generated from .\/interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3\n *\n * Compatible with ROM where ECO version equal or greater to 1.\n *\n * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.\n *\/\n\n\/***************************************\n Group common\n ***************************************\/\n\n\/* Functions *\/\nrtc_get_reset_reason = 0x40000018;\nanalog_super_wdt_reset_happened = 0x4000001c;\nrtc_get_wakeup_cause = 0x40000020;\nrtc_select_apb_bridge = 0x40000024;\nrtc_unhold_all_pads = 0x40000028;\nets_is_print_boot = 0x4000002c;\nets_vprintf = 0x40000030;\nets_printf = 0x40000034;\nets_install_putc1 = 0x40000038;\nets_install_uart_printf = 0x4000003c;\nets_install_putc2 = 0x40000040;\nets_delay_us = 0x40000044;\nets_get_stack_info = 0x40000048;\nets_install_lock = 0x4000004c;\nUartRxString = 0x40000050;\nUartGetCmdLn = 0x40000054;\nuart_tx_one_char = 0x40000058;\nuart_tx_one_char2 = 0x4000005c;\nuart_rx_one_char = 0x40000060;\nuart_rx_one_char_block = 0x40000064;\nuart_rx_readbuff = 0x40000068;\nuartAttach = 0x4000006c;\nuart_tx_flush = 0x40000070;\nuart_tx_wait_idle = 0x40000074;\nuart_div_modify = 0x40000078;\nets_write_char_uart = 0x4000007c;\nuart_tx_switch = 0x40000080;\nmultofup = 0x40000084;\nsoftware_reset = 0x40000088;\nsoftware_reset_cpu = 0x4000008c;\nassist_debug_clock_enable = 0x40000090;\nassist_debug_record_enable = 0x40000094;\nclear_super_wdt_reset_flag = 0x40000098;\ndisable_default_watchdog = 0x4000009c;\nsend_packet = 0x400000a0;\nrecv_packet = 0x400000a4;\nGetUartDevice = 0x400000a8;\nUartDwnLdProc = 0x400000ac;\nGetSecurityInfoProc = 0x400000b0;\nUart_Init = 0x400000b4;\nets_set_user_start = 0x400000b8;\n\/* Data (.data, .bss, .rodata) *\/\nets_rom_layout_p = 0x3ff4fffc;\nets_ops_table_ptr = 0x3fcdfffc;\n\n\n\/***************************************\n Group miniz\n ***************************************\/\n\n\/* Functions *\/\nmz_adler32 = 0x400000bc;\nmz_free = 0x400000c0;\ntdefl_compress = 0x400000c4;\ntdefl_compress_buffer = 0x400000c8;\ntdefl_compress_mem_to_heap = 0x400000cc;\ntdefl_compress_mem_to_mem = 0x400000d0;\ntdefl_compress_mem_to_output = 0x400000d4;\ntdefl_get_adler32 = 0x400000d8;\ntdefl_get_prev_return_status = 0x400000dc;\ntdefl_init = 0x400000e0;\ntdefl_write_image_to_png_file_in_memory = 0x400000e4;\ntdefl_write_image_to_png_file_in_memory_ex = 0x400000e8;\ntinfl_decompress = 0x400000ec;\ntinfl_decompress_mem_to_callback = 0x400000f0;\ntinfl_decompress_mem_to_heap = 0x400000f4;\ntinfl_decompress_mem_to_mem = 0x400000f8;\n\n\n\/***************************************\n Group spiflash_legacy\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc );\nPROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 );\nPROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 );\nPROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 );\nPROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c );\nPROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 );\nPROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 );\nPROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 );\nPROVIDE( _esp_rom_spiflash_write = 0x4000011c );\nPROVIDE( _esp_rom_spiflash_read = 0x40000120 );\nPROVIDE( _esp_rom_spiflash_unlock = 0x40000124 );\nPROVIDE( _SPIEraseArea = 0x40000128 );\nPROVIDE( _SPI_write_enable = 0x4000012c );\nPROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 );\nPROVIDE( esp_rom_spiflash_erase_block = 0x40000134 );\nPROVIDE( esp_rom_spiflash_write = 0x40000138 );\nPROVIDE( esp_rom_spiflash_read = 0x4000013c );\nPROVIDE( esp_rom_spiflash_unlock = 0x40000140 );\nPROVIDE( SPIEraseArea = 0x40000144 );\nPROVIDE( SPI_write_enable = 0x40000148 );\nPROVIDE( esp_rom_spiflash_config_param = 0x4000014c );\nPROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 );\nPROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 );\nPROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 );\nPROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c );\nPROVIDE( esp_rom_spi_flash_update_id = 0x40000160 );\nPROVIDE( esp_rom_spiflash_config_clk = 0x40000164 );\nPROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 );\nPROVIDE( esp_rom_spiflash_read_status = 0x4000016c );\nPROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 );\nPROVIDE( esp_rom_spiflash_write_status = 0x40000174 );\nPROVIDE( spi_flash_attach = 0x40000178 );\nPROVIDE( spi_flash_get_chip_size = 0x4000017c );\nPROVIDE( spi_flash_guard_set = 0x40000180 );\nPROVIDE( spi_flash_guard_get = 0x40000184 );\nPROVIDE( spi_flash_read_encrypted = 0x40000188 );\nPROVIDE( spi_flash_mmap_os_func_set = 0x4000018c );\nPROVIDE( spi_flash_mmap_page_num_init = 0x40000190 );\nPROVIDE( spi_flash_mmap = 0x40000194 );\nPROVIDE( spi_flash_mmap_pages = 0x40000198 );\nPROVIDE( spi_flash_munmap = 0x4000019c );\nPROVIDE( spi_flash_mmap_dump = 0x400001a0 );\nPROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );\nPROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );\nPROVIDE( spi_flash_cache2phys = 0x400001ac );\nPROVIDE( spi_flash_phys2cache = 0x400001b0 );\nPROVIDE( spi_flash_disable_cache = 0x400001b4 );\nPROVIDE( spi_flash_restore_cache = 0x400001b8 );\nPROVIDE( spi_flash_cache_enabled = 0x400001bc );\nPROVIDE( spi_flash_enable_cache = 0x400001c0 );\nPROVIDE( spi_cache_mode_switch = 0x400001c4 );\nPROVIDE( spi_common_set_dummy_output = 0x400001c8 );\nPROVIDE( spi_common_set_flash_cs_timing = 0x400001cc );\nPROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 );\nPROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 );\nPROVIDE( SPILock = 0x400001d8 );\nPROVIDE( SPIMasterReadModeCnfig = 0x400001dc );\nPROVIDE( SPI_Common_Command = 0x400001e0 );\nPROVIDE( SPI_WakeUp = 0x400001e4 );\nPROVIDE( SPI_block_erase = 0x400001e8 );\nPROVIDE( SPI_chip_erase = 0x400001ec );\nPROVIDE( SPI_init = 0x400001f0 );\nPROVIDE( SPI_page_program = 0x400001f4 );\nPROVIDE( SPI_read_data = 0x400001f8 );\nPROVIDE( SPI_sector_erase = 0x400001fc );\nPROVIDE( SelectSpiFunction = 0x40000200 );\nPROVIDE( SetSpiDrvs = 0x40000204 );\nPROVIDE( Wait_SPI_Idle = 0x40000208 );\nPROVIDE( spi_dummy_len_fix = 0x4000020c );\nPROVIDE( Disable_QMode = 0x40000210 );\nPROVIDE( Enable_QMode = 0x40000214 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );\nPROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );\nPROVIDE( g_flash_guard_ops = 0x3fcdfff8 );\n\n\n\/***************************************\n Group hal_soc\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 );\nPROVIDE( spi_flash_hal_device_config = 0x4000021c );\nPROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 );\nPROVIDE( spi_flash_hal_common_command = 0x40000224 );\nPROVIDE( spi_flash_hal_read = 0x40000228 );\nPROVIDE( spi_flash_hal_erase_chip = 0x4000022c );\nPROVIDE( spi_flash_hal_erase_sector = 0x40000230 );\nPROVIDE( spi_flash_hal_erase_block = 0x40000234 );\nPROVIDE( spi_flash_hal_program_page = 0x40000238 );\nPROVIDE( spi_flash_hal_set_write_protect = 0x4000023c );\nPROVIDE( spi_flash_hal_host_idle = 0x40000240 );\nPROVIDE( spi_flash_hal_check_status = 0x40000244 );\nPROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 );\nPROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c );\nPROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 );\nPROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 );\nPROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 );\nPROVIDE( spi_flash_hal_resume = 0x4000025c );\nPROVIDE( spi_flash_hal_suspend = 0x40000260 );\nPROVIDE( spi_flash_encryption_hal_enable = 0x40000264 );\nPROVIDE( spi_flash_encryption_hal_disable = 0x40000268 );\nPROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c );\nPROVIDE( spi_flash_encryption_hal_done = 0x40000270 );\nPROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 );\nPROVIDE( spi_flash_encryption_hal_check = 0x40000278 );\nPROVIDE( wdt_hal_init = 0x4000027c );\nPROVIDE( wdt_hal_deinit = 0x40000280 );\nPROVIDE( wdt_hal_config_stage = 0x40000284 );\nPROVIDE( wdt_hal_write_protect_disable = 0x40000288 );\nPROVIDE( wdt_hal_write_protect_enable = 0x4000028c );\nPROVIDE( wdt_hal_enable = 0x40000290 );\nPROVIDE( wdt_hal_disable = 0x40000294 );\nPROVIDE( wdt_hal_handle_intr = 0x40000298 );\nPROVIDE( wdt_hal_feed = 0x4000029c );\nPROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 );\nPROVIDE( wdt_hal_is_enabled = 0x400002a4 );\nPROVIDE( systimer_hal_init = 0x400002a8 );\nPROVIDE( systimer_hal_get_counter_value = 0x400002ac );\nPROVIDE( systimer_hal_get_time = 0x400002b0 );\nPROVIDE( systimer_hal_set_alarm_target = 0x400002b4 );\nPROVIDE( systimer_hal_set_alarm_period = 0x400002b8 );\nPROVIDE( systimer_hal_get_alarm_value = 0x400002bc );\nPROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 );\nPROVIDE( systimer_hal_on_apb_freq_update = 0x400002c4 );\nPROVIDE( systimer_hal_counter_value_advance = 0x400002c8 );\nPROVIDE( systimer_hal_enable_counter = 0x400002cc );\nPROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 );\nPROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 );\nPROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 );\n\n\n\/***************************************\n Group heap\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( tlsf_create = 0x400002dc );\nPROVIDE( tlsf_create_with_pool = 0x400002e0 );\nPROVIDE( tlsf_get_pool = 0x400002e4 );\nPROVIDE( tlsf_add_pool = 0x400002e8 );\nPROVIDE( tlsf_remove_pool = 0x400002ec );\nPROVIDE( tlsf_malloc = 0x400002f0 );\nPROVIDE( tlsf_memalign = 0x400002f4 );\nPROVIDE( tlsf_memalign_offs = 0x400002f8 );\nPROVIDE( tlsf_realloc = 0x400002fc );\nPROVIDE( tlsf_free = 0x40000300 );\nPROVIDE( tlsf_block_size = 0x40000304 );\nPROVIDE( tlsf_size = 0x40000308 );\nPROVIDE( tlsf_align_size = 0x4000030c );\nPROVIDE( tlsf_block_size_min = 0x40000310 );\nPROVIDE( tlsf_block_size_max = 0x40000314 );\nPROVIDE( tlsf_pool_overhead = 0x40000318 );\nPROVIDE( tlsf_alloc_overhead = 0x4000031c );\nPROVIDE( tlsf_walk_pool = 0x40000320 );\nPROVIDE( tlsf_check = 0x40000324 );\nPROVIDE( tlsf_check_pool = 0x40000328 );\nPROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c );\nPROVIDE( multi_heap_get_block_address_impl = 0x40000330 );\nPROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 );\nPROVIDE( multi_heap_register_impl = 0x40000338 );\nPROVIDE( multi_heap_set_lock = 0x4000033c );\nPROVIDE( multi_heap_os_funcs_init = 0x40000340 );\nPROVIDE( multi_heap_internal_lock = 0x40000344 );\nPROVIDE( multi_heap_internal_unlock = 0x40000348 );\nPROVIDE( multi_heap_get_first_block = 0x4000034c );\nPROVIDE( multi_heap_get_next_block = 0x40000350 );\nPROVIDE( multi_heap_is_free = 0x40000354 );\nPROVIDE( multi_heap_malloc_impl = 0x40000358 );\nPROVIDE( multi_heap_free_impl = 0x4000035c );\nPROVIDE( multi_heap_realloc_impl = 0x40000360 );\nPROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 );\nPROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 );\nPROVIDE( multi_heap_check = 0x4000036c );\nPROVIDE( multi_heap_dump = 0x40000370 );\nPROVIDE( multi_heap_free_size_impl = 0x40000374 );\nPROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 );\nPROVIDE( multi_heap_get_info_impl = 0x4000037c );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );\n\n\n\/***************************************\n Group spi_flash_chips\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( spi_flash_chip_generic_probe = 0x40000380 );\nPROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 );\nPROVIDE( spi_flash_chip_generic_write = 0x40000388 );\nPROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c );\nPROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 );\nPROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 );\nPROVIDE( spi_flash_chip_generic_reset = 0x40000398 );\nPROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c );\nPROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 );\nPROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 );\nPROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 );\nPROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac );\nPROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 );\nPROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 );\nPROVIDE( spi_flash_chip_generic_yield = 0x400003b8 );\nPROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc );\nPROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 );\nPROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 );\nPROVIDE( spi_flash_chip_generic_read = 0x400003c8 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc );\nPROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 );\nPROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 );\nPROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc );\nPROVIDE( spi_flash_common_set_io_mode = 0x400003e0 );\nPROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 );\nPROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 );\nPROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec );\nPROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 );\nPROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 );\nPROVIDE( spi_flash_chip_gd_probe = 0x400003f8 );\nPROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );\nPROVIDE( spi_flash_encryption = 0x3fcdffe4 );\n\n\n\/***************************************\n Group memspi_host\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( memspi_host_read_id_hs = 0x40000400 );\nPROVIDE( memspi_host_read_status_hs = 0x40000404 );\nPROVIDE( memspi_host_flush_cache = 0x40000408 );\nPROVIDE( memspi_host_erase_chip = 0x4000040c );\nPROVIDE( memspi_host_erase_sector = 0x40000410 );\nPROVIDE( memspi_host_erase_block = 0x40000414 );\nPROVIDE( memspi_host_program_page = 0x40000418 );\nPROVIDE( memspi_host_read = 0x4000041c );\nPROVIDE( memspi_host_set_write_protect = 0x40000420 );\nPROVIDE( memspi_host_set_max_read_len = 0x40000424 );\nPROVIDE( memspi_host_read_data_slicer = 0x40000428 );\nPROVIDE( memspi_host_write_data_slicer = 0x4000042c );\n\n\n\/***************************************\n Group esp_flash\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( esp_flash_chip_driver_initialized = 0x40000430 );\nPROVIDE( esp_flash_read_id = 0x40000434 );\nPROVIDE( esp_flash_get_size = 0x40000438 );\nPROVIDE( esp_flash_erase_chip = 0x4000043c );\nPROVIDE( esp_flash_erase_region = 0x40000440 );\nPROVIDE( esp_flash_get_chip_write_protect = 0x40000444 );\nPROVIDE( esp_flash_set_chip_write_protect = 0x40000448 );\nPROVIDE( esp_flash_get_protectable_regions = 0x4000044c );\nPROVIDE( esp_flash_get_protected_region = 0x40000450 );\nPROVIDE( esp_flash_set_protected_region = 0x40000454 );\nPROVIDE( esp_flash_read = 0x40000458 );\nPROVIDE( esp_flash_write = 0x4000045c );\nPROVIDE( esp_flash_write_encrypted = 0x40000460 );\nPROVIDE( esp_flash_read_encrypted = 0x40000464 );\nPROVIDE( esp_flash_get_io_mode = 0x40000468 );\nPROVIDE( esp_flash_set_io_mode = 0x4000046c );\nPROVIDE( spi_flash_boot_attach = 0x40000470 );\nPROVIDE( esp_flash_read_chip_id = 0x40000474 );\nPROVIDE( detect_spi_flash_chip = 0x40000478 );\nPROVIDE( esp_rom_spiflash_write_disable = 0x4000047c );\nPROVIDE( esp_flash_suspend_cmd_init = 0x40000480 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( esp_flash_default_chip = 0x3fcdffe0 );\nPROVIDE( esp_flash_api_funcs = 0x3fcdffdc );\n\n\n\/***************************************\n Group cache\n ***************************************\/\n\n\/* Functions *\/\nPROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 );\nPROVIDE( Cache_Get_Mode = 0x400006e4 );\nPROVIDE( Cache_Address_Through_IBus = 0x400006e8 );\nPROVIDE( Cache_Address_Through_DBus = 0x400006ec );\nPROVIDE( Cache_Set_Default_Mode = 0x400006f0 );\nPROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 );\nPROVIDE( ROM_Boot_Cache_Init = 0x400006f8 );\nPROVIDE( MMU_Set_Page_Mode = 0x400006fc );\nPROVIDE( MMU_Get_Page_Mode = 0x40000700 );\nPROVIDE( Cache_Invalidate_ICache_Items = 0x40000704 );\nPROVIDE( Cache_Op_Addr = 0x40000708 );\nPROVIDE( Cache_Invalidate_Addr = 0x4000070c );\nPROVIDE( Cache_Invalidate_ICache_All = 0x40000710 );\nPROVIDE( Cache_Mask_All = 0x40000714 );\nPROVIDE( Cache_UnMask_Dram0 = 0x40000718 );\nPROVIDE( Cache_Disable_ICache = 0x4000071c );\nPROVIDE( Cache_Enable_ICache = 0x40000720 );\nPROVIDE( Cache_Suspend_ICache = 0x40000724 );\nPROVIDE( Cache_Resume_ICache = 0x40000728 );\nPROVIDE( Cache_Freeze_ICache_Enable = 0x4000072c );\nPROVIDE( Cache_Freeze_ICache_Disable = 0x40000730 );\nPROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000734 );\nPROVIDE( Cache_Get_IROM_MMU_End = 0x40000738 );\nPROVIDE( Cache_Get_DROM_MMU_End = 0x4000073c );\nPROVIDE( Cache_Owner_Init = 0x40000740 );\nPROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000744 );\nPROVIDE( Cache_MMU_Init = 0x40000748 );\nPROVIDE( Cache_Ibus_MMU_Set = 0x4000074c );\nPROVIDE( Cache_Dbus_MMU_Set = 0x40000750 );\nPROVIDE( Cache_Count_Flash_Pages = 0x40000754 );\nPROVIDE( Cache_Travel_Tag_Memory = 0x40000758 );\nPROVIDE( Cache_Get_Virtual_Addr = 0x4000075c );\nPROVIDE( Cache_Get_Memory_BaseAddr = 0x40000760 );\nPROVIDE( Cache_Get_Memory_Addr = 0x40000764 );\nPROVIDE( Cache_Get_Memory_value = 0x40000768 );\n\/* Data (.data, .bss, .rodata) *\/\nPROVIDE( rom_cache_op_cb = 0x3fcdffd0 );\nPROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );\n\n\n\/***************************************\n Group clock\n ***************************************\/\n\n\/* Functions *\/\nets_get_apb_freq = 0x4000076c;\nets_get_cpu_frequency = 0x40000770;\nets_update_cpu_frequency = 0x40000774;\nets_get_printf_channel = 0x40000778;\nets_get_xtal_div = 0x4000077c;\nets_set_xtal_div = 0x40000780;\nets_get_xtal_freq = 0x40000784;\n\n\n\/***************************************\n Group gpio\n ***************************************\/\n\n\/* Functions *\/\ngpio_input_get = 0x40000788;\ngpio_matrix_in = 0x4000078c;\ngpio_matrix_out = 0x40000790;\ngpio_output_disable = 0x40000794;\ngpio_output_enable = 0x40000798;\ngpio_output_set = 0x4000079c;\ngpio_pad_hold = 0x400007a0;\ngpio_pad_input_disable = 0x400007a4;\ngpio_pad_input_enable = 0x400007a8;\ngpio_pad_pulldown = 0x400007ac;\ngpio_pad_pullup = 0x400007b0;\ngpio_pad_select_gpio = 0x400007b4;\ngpio_pad_set_drv = 0x400007b8;\ngpio_pad_unhold = 0x400007bc;\ngpio_pin_wakeup_disable = 0x400007c0;\ngpio_pin_wakeup_enable = 0x400007c4;\ngpio_bypass_matrix_in = 0x400007c8;\n\n\n\/***************************************\n Group interrupts\n ***************************************\/\n\n\/* Functions *\/\nesprv_intc_int_set_priority = 0x400007cc;\nesprv_intc_int_set_threshold = 0x400007d0;\nesprv_intc_int_enable = 0x400007d4;\nesprv_intc_int_disable = 0x400007d8;\nesprv_intc_int_set_type = 0x400007dc;\nPROVIDE( intr_handler_set = 0x400007e0 );\nintr_matrix_set = 0x400007e4;\nets_intr_lock = 0x400007e8;\nets_intr_unlock = 0x400007ec;\nets_isr_attach = 0x400007f0;\nets_isr_mask = 0x400007f4;\nets_isr_unmask = 0x400007f8;\n\n\n\/***************************************\n Group crypto\n ***************************************\/\n\n\/* Functions *\/\ncrc32_le = 0x400007fc;\ncrc16_le = 0x40000800;\ncrc8_le = 0x40000804;\ncrc32_be = 0x40000808;\ncrc16_be = 0x4000080c;\ncrc8_be = 0x40000810;\nesp_crc8 = 0x40000814;\nets_sha_enable = 0x40000818;\nets_sha_disable = 0x4000081c;\nets_sha_get_state = 0x40000820;\nets_sha_init = 0x40000824;\nets_sha_process = 0x40000828;\nets_sha_starts = 0x4000082c;\nets_sha_update = 0x40000830;\nets_sha_finish = 0x40000834;\nets_sha_clone = 0x40000838;\n\/* Data (.data, .bss, .rodata) *\/\ncrc32_le_table_ptr = 0x3ff4fff8;\ncrc16_le_table_ptr = 0x3ff4fff4;\ncrc8_le_table_ptr = 0x3ff4fff0;\ncrc32_be_table_ptr = 0x3ff4ffec;\ncrc16_be_table_ptr = 0x3ff4ffe8;\ncrc8_be_table_ptr = 0x3ff4ffe4;\n\n\n\/***************************************\n Group efuse\n ***************************************\/\n\n\/* Functions *\/\nets_efuse_read = 0x4000083c;\nets_efuse_program = 0x40000840;\nets_efuse_clear_program_registers = 0x40000844;\nets_efuse_write_key = 0x40000848;\nets_efuse_get_read_register_address = 0x4000084c;\nets_efuse_get_key_purpose = 0x40000850;\nets_efuse_key_block_unused = 0x40000854;\nets_efuse_find_unused_key_block = 0x40000858;\nets_efuse_rs_calculate = 0x4000085c;\nets_efuse_count_unused_key_blocks = 0x40000860;\nets_efuse_secure_boot_enabled = 0x40000864;\nets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000868;\nets_efuse_cache_encryption_enabled = 0x4000086c;\nets_efuse_download_modes_disabled = 0x40000870;\nets_efuse_find_purpose = 0x40000874;\nets_efuse_force_send_resume = 0x40000878;\nets_efuse_get_flash_delay_us = 0x4000087c;\nets_efuse_get_mac = 0x40000880;\nets_efuse_get_uart_print_control = 0x40000884;\nets_efuse_direct_boot_mode_disabled = 0x40000888;\nets_efuse_security_download_modes_enabled = 0x4000088c;\nets_efuse_set_timing = 0x40000890;\nets_efuse_jtag_disabled = 0x40000894;\n\n\n\/***************************************\n Group secureboot\n ***************************************\/\n\n\/* Functions *\/\nets_ecdsa_verify = 0x40000898;\nets_secure_boot_verify_bootloader_with_keys = 0x4000089c;\nets_secure_boot_verify_signature = 0x400008a0;\nets_secure_boot_read_key_digests = 0x400008a4;\n\n\n\/***************************************\n Group usb_uart\n ***************************************\/\n\n\/* Data (.data, .bss, .rodata) *\/\ng_uart_print = 0x3fcdffc9;\ng_usb_print = 0x3fcdffc8;\n\n\n\/***************************************\n Group bluetooth\n ***************************************\/\n\n\/* Functions *\/\nble_controller_rom_data_init = 0x40000aa8;\nble_osi_coex_funcs_register = 0x40000aac;\nbt_rf_coex_cfg_get_default = 0x40000ab0;\nbt_rf_coex_dft_pti_get_default = 0x40000ab4;\nbt_rf_coex_hooks_p_set = 0x40000ab8;\nr__os_mbuf_copypkthdr = 0x40000abc;\nr__os_msys_find_pool = 0x40000ac0;\nr_ble_controller_get_rom_compile_version = 0x40000ac4;\nr_ble_hci_ram_hs_acl_tx = 0x40000ac8;\nr_ble_hci_ram_hs_cmd_tx = 0x40000acc;\nr_ble_hci_ram_ll_acl_tx = 0x40000ad0;\nr_ble_hci_ram_ll_evt_tx = 0x40000ad4;\nr_ble_hci_ram_reset = 0x40000ad8;\nr_ble_hci_ram_set_acl_free_cb = 0x40000adc;\nr_ble_hci_trans_acl_buf_alloc = 0x40000ae0;\nr_ble_hci_trans_buf_alloc = 0x40000ae4;\nr_ble_hci_trans_buf_free = 0x40000ae8;\nr_ble_hci_trans_cfg_hs = 0x40000aec;\nr_ble_hci_trans_cfg_ll = 0x40000af0;\nr_ble_hci_trans_deinit = 0x40000af4;\nr_ble_hci_trans_env_init = 0x40000af8;\nr_ble_hci_trans_init = 0x40000afc;\nr_ble_hci_uart_acl_tx = 0x40000b00;\nr_ble_hci_uart_cmdevt_tx = 0x40000b04;\nr_ble_hci_uart_config = 0x40000b08;\nr_ble_hci_uart_free_pkt = 0x40000b0c;\nr_ble_hci_uart_hs_acl_tx = 0x40000b10;\nr_ble_hci_uart_hs_cmd_tx = 0x40000b14;\nr_ble_hci_uart_ll_acl_tx = 0x40000b18;\nr_ble_hci_uart_ll_evt_tx = 0x40000b1c;\nr_ble_hci_uart_rx_acl = 0x40000b20;\nr_ble_hci_uart_rx_char = 0x40000b24;\nr_ble_hci_uart_rx_cmd = 0x40000b28;\nr_ble_hci_uart_rx_evt = 0x40000b2c;\nr_ble_hci_uart_rx_evt_cb = 0x40000b30;\nr_ble_hci_uart_rx_le_evt = 0x40000b34;\nr_ble_hci_uart_rx_pkt_type = 0x40000b38;\nr_ble_hci_uart_rx_skip_acl = 0x40000b3c;\nr_ble_hci_uart_rx_skip_cmd = 0x40000b40;\nr_ble_hci_uart_rx_skip_evt = 0x40000b44;\nr_ble_hci_uart_rx_sync_loss = 0x40000b48;\nr_ble_hci_uart_set_acl_free_cb = 0x40000b4c;\nr_ble_hci_uart_sync_lost = 0x40000b50;\nr_ble_hci_uart_trans_reset = 0x40000b54;\nr_ble_hci_uart_tx_char = 0x40000b58;\nr_ble_hci_uart_tx_pkt_type = 0x40000b5c;\nr_ble_hw_driver_deinit = 0x40000b60;\nr_ble_hw_driver_env_init = 0x40000b64;\nr_ble_hw_encrypt_block = 0x40000b68;\nr_ble_hw_get_public_addr = 0x40000b6c;\nr_ble_hw_get_static_addr = 0x40000b70;\nr_ble_hw_periodiclist_add = 0x40000b74;\nr_ble_hw_periodiclist_clear = 0x40000b78;\nr_ble_hw_periodiclist_rmv = 0x40000b7c;\nr_ble_hw_resolv_list_cur_entry = 0x40000b80;\nr_ble_hw_resolv_list_set = 0x40000b88;\nr_ble_hw_rng_init = 0x40000b8c;\nr_ble_hw_rng_start = 0x40000b90;\nr_ble_hw_rng_stop = 0x40000b94;\nr_ble_hw_rx_local_is_resolved = 0x40000b98;\nr_ble_hw_rx_local_is_rpa = 0x40000b9c;\nr_ble_hw_whitelist_add = 0x40000ba0;\nr_ble_hw_whitelist_clear = 0x40000ba4;\nr_ble_hw_whitelist_dev_num = 0x40000ba8;\nr_ble_hw_whitelist_get_base = 0x40000bac;\nr_ble_hw_whitelist_rmv = 0x40000bb0;\nr_ble_hw_whitelist_search = 0x40000bb4;\nr_ble_hw_whitelist_sort = 0x40000bb8;\nr_ble_ll_acl_data_in = 0x40000bbc;\nr_ble_ll_addr_is_id = 0x40000bc0;\nr_ble_ll_addr_subtype = 0x40000bc4;\nr_ble_ll_adv_active_chanset_clear = 0x40000bc8;\nr_ble_ll_adv_active_chanset_is_pri = 0x40000bcc;\nr_ble_ll_adv_active_chanset_is_sec = 0x40000bd0;\nr_ble_ll_adv_active_chanset_set_pri = 0x40000bd4;\nr_ble_ll_adv_active_chanset_set_sec = 0x40000bd8;\nr_ble_ll_adv_aux_calculate = 0x40000bdc;\nr_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000be0;\nr_ble_ll_adv_aux_pdu_make = 0x40000be4;\nr_ble_ll_adv_aux_scannable_pdu_make = 0x40000be8;\nr_ble_ll_adv_aux_txed = 0x40000bec;\nr_ble_ll_adv_can_chg_whitelist = 0x40000bf0;\nr_ble_ll_adv_chk_rpa_timeout = 0x40000bf4;\nr_ble_ll_adv_clear_all = 0x40000bf8;\nr_ble_ll_adv_conn_req_rxd = 0x40000bfc;\nr_ble_ll_adv_deinit = 0x40000c00;\nr_ble_ll_adv_enabled = 0x40000c04;\nr_ble_ll_adv_env_init = 0x40000c08;\nr_ble_ll_adv_ext_set_adv_data = 0x40000c0c;\nr_ble_ll_adv_ext_set_enable = 0x40000c10;\nr_ble_ll_adv_ext_set_param = 0x40000c14;\nr_ble_ll_adv_ext_set_scan_rsp = 0x40000c18;\nr_ble_ll_adv_final_chan = 0x40000c1c;\nr_ble_ll_adv_first_chan = 0x40000c20;\nr_ble_ll_adv_flags_clear = 0x40000c24;\nr_ble_ll_adv_flags_set = 0x40000c28;\nr_ble_ll_adv_get_chan_num = 0x40000c2c;\nr_ble_ll_adv_get_local_rpa = 0x40000c30;\nr_ble_ll_adv_get_peer_rpa = 0x40000c34;\nr_ble_ll_adv_hci_set_random_addr = 0x40000c38;\nr_ble_ll_adv_init = 0x40000c3c;\nr_ble_ll_adv_legacy_pdu_make = 0x40000c40;\nr_ble_ll_adv_next_chan = 0x40000c44;\nr_ble_ll_adv_pdu_make = 0x40000c48;\nr_ble_ll_adv_periodic_check_data_itvl = 0x40000c4c;\nr_ble_ll_adv_periodic_enable = 0x40000c50;\nr_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c54;\nr_ble_ll_adv_periodic_send_sync_ind = 0x40000c58;\nr_ble_ll_adv_periodic_set_data = 0x40000c5c;\nr_ble_ll_adv_periodic_set_info_transfer = 0x40000c60;\nr_ble_ll_adv_periodic_set_param = 0x40000c64;\nr_ble_ll_adv_pre_process = 0x40000c68;\nr_ble_ll_adv_put_acad_chM_update_ind = 0x40000c6c;\nr_ble_ll_adv_put_aux_ptr = 0x40000c70;\nr_ble_ll_adv_put_syncinfo = 0x40000c74;\nr_ble_ll_adv_rd_max_adv_data_len = 0x40000c78;\nr_ble_ll_adv_rd_sup_adv_sets = 0x40000c7c;\nr_ble_ll_adv_read_txpwr = 0x40000c80;\nr_ble_ll_adv_remove = 0x40000c84;\nr_ble_ll_adv_reset = 0x40000c88;\nr_ble_ll_adv_rpa_timeout = 0x40000c8c;\nr_ble_ll_adv_rpa_update = 0x40000c90;\nr_ble_ll_adv_rx_pkt_in = 0x40000c94;\nr_ble_ll_adv_scan_req_rxd = 0x40000c98;\nr_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c;\nr_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0;\nr_ble_ll_adv_scheduled = 0x40000ca4;\nr_ble_ll_adv_send_conn_comp_ev = 0x40000ca8;\nr_ble_ll_adv_set_adv_data = 0x40000cac;\nr_ble_ll_adv_set_adv_params = 0x40000cb0;\nr_ble_ll_adv_set_enable = 0x40000cb4;\nr_ble_ll_adv_set_random_addr = 0x40000cb8;\nr_ble_ll_adv_set_scan_rsp_data = 0x40000cbc;\nr_ble_ll_adv_set_sched = 0x40000cc0;\nr_ble_ll_adv_sm_deinit = 0x40000cc4;\nr_ble_ll_adv_sm_event_init = 0x40000cc8;\nr_ble_ll_adv_sm_find_configured = 0x40000ccc;\nr_ble_ll_adv_sm_get = 0x40000cd0;\nr_ble_ll_adv_sm_init = 0x40000cd4;\nr_ble_ll_adv_sm_reset = 0x40000cd8;\nr_ble_ll_adv_sm_start = 0x40000cdc;\nr_ble_ll_adv_sm_start_periodic = 0x40000ce0;\nr_ble_ll_adv_sm_stop = 0x40000ce4;\nr_ble_ll_adv_sm_stop_limit_reached = 0x40000ce8;\nr_ble_ll_adv_sm_stop_periodic = 0x40000cec;\nr_ble_ll_adv_sm_stop_timeout = 0x40000cf0;\nr_ble_ll_adv_sync_calculate = 0x40000cf4;\nr_ble_ll_adv_sync_get_pdu_len = 0x40000cf8;\nr_ble_ll_adv_sync_pdu_make = 0x40000cfc;\nr_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d00;\nr_ble_ll_adv_update_data_mbuf = 0x40000d04;\nr_ble_ll_adv_update_did = 0x40000d08;\nr_ble_ll_adv_update_periodic_data = 0x40000d0c;\nr_ble_ll_arr_pool_init = 0x40000d10;\nr_ble_ll_auth_pyld_tmo_event_send = 0x40000d14;\nr_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d18;\nr_ble_ll_calc_session_key = 0x40000d1c;\nr_ble_ll_calc_ticks_per_slot = 0x40000d20;\nr_ble_ll_check_scan_params = 0x40000d24;\nr_ble_ll_chk_txrx_octets = 0x40000d28;\nr_ble_ll_chk_txrx_time = 0x40000d2c;\nr_ble_ll_conn_adjust_pyld_len = 0x40000d30;\nr_ble_ll_conn_auth_pyld_timer_cb = 0x40000d34;\nr_ble_ll_conn_auth_pyld_timer_start = 0x40000d38;\nr_ble_ll_conn_calc_dci = 0x40000d3c;\nr_ble_ll_conn_calc_dci_csa1 = 0x40000d40;\nr_ble_ll_conn_calc_itvl_ticks = 0x40000d44;\nr_ble_ll_conn_chk_csm_flags = 0x40000d48;\nr_ble_ll_conn_chk_phy_upd_start = 0x40000d4c;\nr_ble_ll_conn_comp_event_send = 0x40000d50;\nr_ble_ll_conn_connect_ind_pdu_make = 0x40000d54;\nr_ble_ll_conn_create = 0x40000d58;\nr_ble_ll_conn_create_cancel = 0x40000d5c;\nr_ble_ll_conn_created = 0x40000d60;\nr_ble_ll_conn_cth_flow_enable = 0x40000d64;\nr_ble_ll_conn_cth_flow_error_fn = 0x40000d68;\nr_ble_ll_conn_cth_flow_have_credit = 0x40000d6c;\nr_ble_ll_conn_cth_flow_is_enabled = 0x40000d70;\nr_ble_ll_conn_cth_flow_process_cmd = 0x40000d74;\nr_ble_ll_conn_cth_flow_set_buffers = 0x40000d78;\nr_ble_ll_conn_enqueue_pkt = 0x40000d7c;\nr_ble_ll_conn_env_init = 0x40000d80;\nr_ble_ll_conn_ext_master_init = 0x40000d84;\nr_ble_ll_conn_find_active_conn = 0x40000d88;\nr_ble_ll_conn_get_active_conn = 0x40000d8c;\nr_ble_ll_conn_get_anchor = 0x40000d90;\nr_ble_ll_conn_hcc_params_set_fallback = 0x40000d94;\nr_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000d98;\nr_ble_ll_conn_hci_chk_conn_params = 0x40000d9c;\nr_ble_ll_conn_hci_chk_scan_params = 0x40000da0;\nr_ble_ll_conn_hci_disconnect_cmd = 0x40000da4;\nr_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000da8;\nr_ble_ll_conn_hci_le_ltk_reply = 0x40000dac;\nr_ble_ll_conn_hci_le_rd_phy = 0x40000db0;\nr_ble_ll_conn_hci_le_set_phy = 0x40000db4;\nr_ble_ll_conn_hci_le_start_encrypt = 0x40000db8;\nr_ble_ll_conn_hci_param_nrr = 0x40000dbc;\nr_ble_ll_conn_hci_param_rr = 0x40000dc0;\nr_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000dc4;\nr_ble_ll_conn_hci_rd_chan_map = 0x40000dc8;\nr_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000dcc;\nr_ble_ll_conn_hci_rd_rssi = 0x40000dd0;\nr_ble_ll_conn_hci_read_rem_features = 0x40000dd4;\nr_ble_ll_conn_hci_set_chan_class = 0x40000dd8;\nr_ble_ll_conn_hci_set_data_len = 0x40000ddc;\nr_ble_ll_conn_hci_update = 0x40000de0;\nr_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000de4;\nr_ble_ll_conn_init_phy = 0x40000de8;\nr_ble_ll_conn_is_empty_pdu = 0x40000df0;\nr_ble_ll_conn_is_lru = 0x40000df4;\nr_ble_ll_conn_master_init = 0x40000df8;\nr_ble_ll_conn_module_deinit = 0x40000dfc;\nr_ble_ll_conn_module_init = 0x40000e00;\nr_ble_ll_conn_module_reset = 0x40000e04;\nr_ble_ll_conn_next_event = 0x40000e08;\nr_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c;\nr_ble_ll_conn_prepare_tx_pdu = 0x40000e10;\nr_ble_ll_conn_process_conn_params = 0x40000e14;\nr_ble_ll_conn_req_peer_sca = 0x40000e18;\nr_ble_ll_conn_rx_data_pdu = 0x40000e1c;\nr_ble_ll_conn_set_csa = 0x40000e20;\nr_ble_ll_conn_set_ext_con_params = 0x40000e24;\nr_ble_ll_conn_set_global_chanmap = 0x40000e28;\nr_ble_ll_conn_set_phy = 0x40000e2c;\nr_ble_ll_conn_set_txpwr_by_handle = 0x40000e30;\nr_ble_ll_conn_set_unknown_rx_octets = 0x40000e34;\nr_ble_ll_conn_slave_start = 0x40000e38;\nr_ble_ll_conn_sm_get = 0x40000e3c;\nr_ble_ll_conn_sm_new = 0x40000e40;\nr_ble_ll_conn_sm_npl_deinit = 0x40000e44;\nr_ble_ll_conn_sm_npl_init = 0x40000e48;\nr_ble_ll_conn_tx_pkt_in = 0x40000e4c;\nr_ble_ll_conn_update_eff_data_len = 0x40000e50;\nr_ble_ll_ctrl_chanmap_req_make = 0x40000e54;\nr_ble_ll_ctrl_chk_proc_start = 0x40000e58;\nr_ble_ll_ctrl_conn_param_pdu_make = 0x40000e5c;\nr_ble_ll_ctrl_conn_param_pdu_proc = 0x40000e60;\nr_ble_ll_ctrl_conn_param_reply = 0x40000e64;\nr_ble_ll_ctrl_conn_upd_make = 0x40000e68;\nr_ble_ll_ctrl_datalen_upd_make = 0x40000e6c;\nr_ble_ll_ctrl_enc_allowed_pdu = 0x40000e70;\nr_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000e74;\nr_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40000e78;\nr_ble_ll_ctrl_enc_req_make = 0x40000e7c;\nr_ble_ll_ctrl_find_new_phy = 0x40000e80;\nr_ble_ll_ctrl_initiate_dle = 0x40000e84;\nr_ble_ll_ctrl_len_proc = 0x40000e88;\nr_ble_ll_ctrl_min_used_chan_rsp = 0x40000e8c;\nr_ble_ll_ctrl_phy_from_phy_mask = 0x40000e90;\nr_ble_ll_ctrl_phy_req_rsp_make = 0x40000e94;\nr_ble_ll_ctrl_phy_tx_transition_get = 0x40000e98;\nr_ble_ll_ctrl_phy_update_cancel = 0x40000e9c;\nr_ble_ll_ctrl_phy_update_ind_make = 0x40000ea0;\nr_ble_ll_ctrl_phy_update_proc_complete = 0x40000ea4;\nr_ble_ll_ctrl_proc_init = 0x40000ea8;\nr_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000eac;\nr_ble_ll_ctrl_proc_start = 0x40000eb0;\nr_ble_ll_ctrl_proc_stop = 0x40000eb4;\nr_ble_ll_ctrl_proc_unk_rsp = 0x40000eb8;\nr_ble_ll_ctrl_proc_with_instant_initiated = 0x40000ebc;\nr_ble_ll_ctrl_rej_ext_ind_make = 0x40000ec0;\nr_ble_ll_ctrl_reject_ind_send = 0x40000ec4;\nr_ble_ll_ctrl_rx_chanmap_req = 0x40000ec8;\nr_ble_ll_ctrl_rx_conn_param_req = 0x40000ecc;\nr_ble_ll_ctrl_rx_conn_param_rsp = 0x40000ed0;\nr_ble_ll_ctrl_rx_conn_update = 0x40000ed4;\nr_ble_ll_ctrl_rx_enc_req = 0x40000ed8;\nr_ble_ll_ctrl_rx_enc_rsp = 0x40000edc;\nr_ble_ll_ctrl_rx_feature_req = 0x40000ee0;\nr_ble_ll_ctrl_rx_feature_rsp = 0x40000ee4;\nr_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8;\nr_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec;\nr_ble_ll_ctrl_rx_pdu = 0x40000ef0;\nr_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4;\nr_ble_ll_ctrl_rx_phy_req = 0x40000ef8;\nr_ble_ll_ctrl_rx_phy_rsp = 0x40000efc;\nr_ble_ll_ctrl_rx_phy_update_ind = 0x40000f00;\nr_ble_ll_ctrl_rx_ping_rsp = 0x40000f04;\nr_ble_ll_ctrl_rx_reject_ind = 0x40000f08;\nr_ble_ll_ctrl_rx_sca_req = 0x40000f0c;\nr_ble_ll_ctrl_rx_sca_rsp = 0x40000f10;\nr_ble_ll_ctrl_rx_start_enc_req = 0x40000f14;\nr_ble_ll_ctrl_rx_start_enc_rsp = 0x40000f18;\nr_ble_ll_ctrl_rx_version_ind = 0x40000f1c;\nr_ble_ll_ctrl_sca_req_rsp_make = 0x40000f20;\nr_ble_ll_ctrl_start_enc_send = 0x40000f24;\nr_ble_ll_ctrl_start_rsp_timer = 0x40000f28;\nr_ble_ll_ctrl_terminate_start = 0x40000f2c;\nr_ble_ll_ctrl_tx_done = 0x40000f30;\nr_ble_ll_ctrl_update_features = 0x40000f34;\nr_ble_ll_ctrl_version_ind_make = 0x40000f38;\nr_ble_ll_data_buffer_overflow = 0x40000f3c;\nr_ble_ll_deinit = 0x40000f40;\nr_ble_ll_disconn_comp_event_send = 0x40000f44;\nr_ble_ll_env_init = 0x40000f48;\nr_ble_ll_event_comp_pkts = 0x40000f4c;\nr_ble_ll_event_dbuf_overflow = 0x40000f50;\nr_ble_ll_event_send = 0x40000f54;\nr_ble_ll_event_tx_pkt = 0x40000f58;\nr_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40000f5c;\nr_ble_ll_ext_conn_create = 0x40000f60;\nr_ble_ll_ext_scan_parse_adv_info = 0x40000f64;\nr_ble_ll_ext_scan_parse_aux_ptr = 0x40000f68;\nr_ble_ll_flush_pkt_queue = 0x40000f6c;\nr_ble_ll_generate_dh_key_v1 = 0x40000f70;\nr_ble_ll_generate_dh_key_v2 = 0x40000f74;\nr_ble_ll_generic_data_init = 0x40000f78;\nr_ble_ll_get_addr_type = 0x40000f7c;\nr_ble_ll_get_chan_to_scan = 0x40000f80;\nr_ble_ll_get_our_devaddr = 0x40000f84;\nr_ble_ll_get_tx_pwr_compensation = 0x40000f88;\nr_ble_ll_hci_acl_rx = 0x40000f8c;\nr_ble_ll_hci_adv_mode_ext = 0x40000f90;\nr_ble_ll_hci_adv_set_enable = 0x40000f94;\nr_ble_ll_hci_cb_host_buf_size = 0x40000f98;\nr_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x40000f9c;\nr_ble_ll_hci_cb_set_event_mask = 0x40000fa0;\nr_ble_ll_hci_cb_set_event_mask2 = 0x40000fa4;\nr_ble_ll_hci_chk_phy_masks = 0x40000fa8;\nr_ble_ll_hci_cmd_proc = 0x40000fac;\nr_ble_ll_hci_cmd_rx = 0x40000fb0;\nr_ble_ll_hci_ctlr_bb_cmd_proc = 0x40000fb4;\nr_ble_ll_hci_deinit = 0x40000fb8;\nr_ble_ll_hci_disconnect = 0x40000fbc;\nr_ble_ll_hci_env_init = 0x40000fc0;\nr_ble_ll_hci_ev_conn_update = 0x40000fc4;\nr_ble_ll_hci_ev_databuf_overflow = 0x40000fc8;\nr_ble_ll_hci_ev_datalen_chg = 0x40000fcc;\nr_ble_ll_hci_ev_encrypt_chg = 0x40000fd0;\nr_ble_ll_hci_ev_hw_err = 0x40000fd4;\nr_ble_ll_hci_ev_le_csa = 0x40000fd8;\nr_ble_ll_hci_ev_ltk_req = 0x40000fdc;\nr_ble_ll_hci_ev_phy_update = 0x40000fe0;\nr_ble_ll_hci_ev_rd_rem_used_feat = 0x40000fe4;\nr_ble_ll_hci_ev_rd_rem_ver = 0x40000fe8;\nr_ble_ll_hci_ev_rem_conn_parm_req = 0x40000fec;\nr_ble_ll_hci_ev_sca_update = 0x40000ff0;\nr_ble_ll_hci_ev_send_adv_set_terminated = 0x40000ff4;\nr_ble_ll_hci_ev_send_scan_req_recv = 0x40000ff8;\nr_ble_ll_hci_ev_send_scan_timeout = 0x40000ffc;\nr_ble_ll_hci_ev_send_vendor_err = 0x40001000;\nr_ble_ll_hci_event_send = 0x40001004;\nr_ble_ll_hci_ext_scan_set_enable = 0x40001008;\nr_ble_ll_hci_get_num_cmd_pkts = 0x4000100c;\nr_ble_ll_hci_info_params_cmd_proc = 0x40001010;\nr_ble_ll_hci_init = 0x40001014;\nr_ble_ll_hci_init_support_cmd_base_on_lmp_ver = 0x40001018;\nr_ble_ll_hci_is_event_enabled = 0x4000101c;\nr_ble_ll_hci_is_le_event_enabled = 0x40001020;\nr_ble_ll_hci_le_cmd_proc = 0x40001024;\nr_ble_ll_hci_le_cmd_send_cmd_status = 0x40001028;\nr_ble_ll_hci_le_encrypt = 0x4000102c;\nr_ble_ll_hci_le_rand = 0x40001030;\nr_ble_ll_hci_le_rd_max_data_len = 0x40001034;\nr_ble_ll_hci_le_rd_sugg_data_len = 0x40001038;\nr_ble_ll_hci_le_read_bufsize = 0x4000103c;\nr_ble_ll_hci_le_read_local_features = 0x40001040;\nr_ble_ll_hci_le_read_supp_states = 0x40001044;\nr_ble_ll_hci_le_set_def_phy = 0x40001048;\nr_ble_ll_hci_le_wr_sugg_data_len = 0x4000104c;\nr_ble_ll_hci_link_ctrl_cmd_proc = 0x40001050;\nr_ble_ll_hci_npl_init = 0x40001054;\nr_ble_ll_hci_post_gen_dhkey_cmp_evt = 0x40001058;\nr_ble_ll_hci_post_rd_p256_pubkey_cmp_evt = 0x4000105c;\nr_ble_ll_hci_rd_bd_addr = 0x40001060;\nr_ble_ll_hci_rd_local_supp_cmd = 0x40001064;\nr_ble_ll_hci_rd_local_supp_feat = 0x40001068;\nr_ble_ll_hci_rd_local_version = 0x4000106c;\nr_ble_ll_hci_scan_set_enable = 0x40001070;\nr_ble_ll_hci_send_adv_report = 0x40001074;\nr_ble_ll_hci_send_dir_adv_report = 0x40001078;\nr_ble_ll_hci_send_ext_adv_report = 0x4000107c;\nr_ble_ll_hci_send_legacy_ext_adv_report = 0x40001080;\nr_ble_ll_hci_send_noop = 0x40001084;\nr_ble_ll_hci_set_adv_data = 0x40001088;\nr_ble_ll_hci_set_le_event_mask = 0x4000108c;\nr_ble_ll_hci_set_scan_rsp_data = 0x40001090;\nr_ble_ll_hci_status_params_cmd_proc = 0x40001094;\nr_ble_ll_hci_vs_cmd_proc = 0x40001098;\nr_ble_ll_hci_vs_rd_static_addr = 0x4000109c;\nr_ble_ll_hw_err_timer_cb = 0x400010a0;\nr_ble_ll_hw_error = 0x400010a4;\nr_ble_ll_init = 0x400010a8;\nr_ble_ll_init_alloc_conn_comp_ev = 0x400010ac;\nr_ble_ll_init_get_conn_comp_ev = 0x400010b0;\nr_ble_ll_init_rx_pkt_in = 0x400010b4;\nr_ble_ll_is_addr_empty = 0x400010b8;\nr_ble_ll_is_controller_busy = 0x400010bc;\nr_ble_ll_is_on_resolv_list = 0x400010c0;\nr_ble_ll_is_our_devaddr = 0x400010c4;\nr_ble_ll_is_rpa = 0x400010c8;\nr_ble_ll_is_valid_adv_mode = 0x400010cc;\nr_ble_ll_is_valid_own_addr_type = 0x400010d0;\nr_ble_ll_is_valid_public_addr = 0x400010d4;\nr_ble_ll_is_valid_random_addr = 0x400010d8;\nr_ble_ll_mbuf_init = 0x400010dc;\nr_ble_ll_misc_options_set = 0x400010e0;\nr_ble_ll_modify_sca = 0x400010e4;\nr_ble_ll_modify_sca_action = 0x400010e8;\nr_ble_ll_pdu_max_tx_octets_get = 0x400010ec;\nr_ble_ll_pdu_tx_time_get = 0x400010f0;\nr_ble_ll_phy_to_phy_mode = 0x400010f4;\nr_ble_ll_qa_enable = 0x400010f8;\nr_ble_ll_rand = 0x400010fc;\nr_ble_ll_rand_data_get = 0x40001100;\nr_ble_ll_rand_deinit = 0x40001104;\nr_ble_ll_rand_env_init = 0x40001108;\nr_ble_ll_rand_init = 0x4000110c;\nr_ble_ll_rand_prand_get = 0x40001110;\nr_ble_ll_rand_sample = 0x40001114;\nr_ble_ll_rand_start = 0x40001118;\nr_ble_ll_read_local_p256_pub_key = 0x4000111c;\nr_ble_ll_read_rf_path_compensation = 0x40001120;\nr_ble_ll_read_supp_features = 0x40001124;\nr_ble_ll_read_supp_states = 0x40001128;\nr_ble_ll_read_tx_power = 0x4000112c;\nr_ble_ll_reset = 0x40001130;\nr_ble_ll_resolv_clear_all_pl_bit = 0x40001134;\nr_ble_ll_resolv_clear_all_wl_bit = 0x40001138;\nr_ble_ll_resolv_deinit = 0x4000113c;\nr_ble_ll_resolv_enable_cmd = 0x40001140;\nr_ble_ll_resolv_enabled = 0x40001144;\nr_ble_ll_resolv_env_init = 0x40001148;\nr_ble_ll_resolv_gen_priv_addr = 0x4000114c;\nr_ble_ll_resolv_gen_rpa = 0x40001150;\nr_ble_ll_resolv_get_addr_pointer = 0x40001154;\nr_ble_ll_resolv_get_index = 0x40001158;\nr_ble_ll_resolv_get_irk_pointer = 0x4000115c;\nr_ble_ll_resolv_get_list = 0x40001160;\nr_ble_ll_resolv_get_priv_addr = 0x40001164;\nr_ble_ll_resolv_get_rpa_tmo = 0x40001168;\nr_ble_ll_resolv_init = 0x4000116c;\nr_ble_ll_resolv_irk_nonzero = 0x40001170;\nr_ble_ll_resolv_list_add = 0x40001174;\nr_ble_ll_resolv_list_chg_allowed = 0x40001178;\nr_ble_ll_resolv_list_clr = 0x4000117c;\nr_ble_ll_resolv_list_find = 0x40001180;\nr_ble_ll_resolv_list_read_size = 0x40001184;\nr_ble_ll_resolv_list_reset = 0x40001188;\nr_ble_ll_resolv_list_rmv = 0x4000118c;\nr_ble_ll_resolv_local_addr_rd = 0x40001190;\nr_ble_ll_resolv_peer_addr_rd = 0x40001194;\nr_ble_ll_resolv_peer_rpa_any = 0x40001198;\nr_ble_ll_resolv_reset = 0x4000119c;\nr_ble_ll_resolv_rpa = 0x400011a0;\nr_ble_ll_resolv_rpa_timer_cb = 0x400011a4;\nr_ble_ll_resolv_set_local_rpa = 0x400011a8;\nr_ble_ll_resolv_set_peer_rpa = 0x400011ac;\nr_ble_ll_resolv_set_rpa_tmo = 0x400011b0;\nr_ble_ll_resolve_set_priv_mode = 0x400011b4;\nr_ble_ll_rxpdu_alloc = 0x400011b8;\nr_ble_ll_scan_add_scan_rsp_adv = 0x400011bc;\nr_ble_ll_scan_adv_decode_addr = 0x400011c0;\nr_ble_ll_scan_aux_data_ref = 0x400011c4;\nr_ble_ll_scan_aux_data_unref = 0x400011c8;\nr_ble_ll_scan_can_chg_whitelist = 0x400011cc;\nr_ble_ll_scan_check_periodic_sync = 0x400011d0;\nr_ble_ll_scan_classify_filter_aux_init = 0x400011d4;\nr_ble_ll_scan_classify_filter_init = 0x400011d8;\nr_ble_ll_scan_common_init = 0x400011dc;\nr_ble_ll_scan_continue_en = 0x400011e0;\nr_ble_ll_scan_deinit = 0x400011e4;\nr_ble_ll_scan_dup_check_ext = 0x400011e8;\nr_ble_ll_scan_dup_check_legacy = 0x400011ec;\nr_ble_ll_scan_dup_move_to_head = 0x400011f0;\nr_ble_ll_scan_dup_new = 0x400011f4;\nr_ble_ll_scan_dup_update_ext = 0x400011f8;\nr_ble_ll_scan_dup_update_legacy = 0x400011fc;\nr_ble_ll_scan_enabled = 0x40001200;\nr_ble_ll_scan_end_adv_evt = 0x40001204;\nr_ble_ll_scan_env_init = 0x40001208;\nr_ble_ll_scan_ext_initiator_start = 0x4000120c;\nr_ble_ll_scan_get_addr_data_from_legacy = 0x40001210;\nr_ble_ll_scan_get_addr_from_ext_adv = 0x40001214;\nr_ble_ll_scan_get_cur_sm = 0x40001218;\nr_ble_ll_scan_get_ext_adv_report = 0x4000121c;\nr_ble_ll_scan_get_local_rpa = 0x40001220;\nr_ble_ll_scan_get_next_adv_prim_chan = 0x40001224;\nr_ble_ll_scan_get_peer_rpa = 0x40001228;\nr_ble_ll_scan_have_rxd_scan_rsp = 0x4000122c;\nr_ble_ll_scan_init = 0x40001230;\nr_ble_ll_scan_initiator_start = 0x40001234;\nr_ble_ll_scan_is_inside_window = 0x40001238;\nr_ble_ll_scan_move_window_to = 0x4000123c;\nr_ble_ll_scan_npl_reset = 0x40001240;\nr_ble_ll_scan_parse_auxptr = 0x40001244;\nr_ble_ll_scan_parse_ext_hdr = 0x40001248;\nr_ble_ll_scan_pre_process = 0x4000124c;\nr_ble_ll_scan_record_new_adv = 0x40001250;\nr_ble_ll_scan_refresh_nrpa = 0x40001254;\nr_ble_ll_scan_reset = 0x40001258;\nr_ble_ll_scan_rx_pkt_in = 0x4000125c;\nr_ble_ll_scan_rx_pkt_in_on_aux = 0x40001260;\nr_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001264;\nr_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268;\nr_ble_ll_scan_rxed = 0x4000126c;\nr_ble_ll_scan_send_adv_report = 0x40001270;\nr_ble_ll_scan_send_truncated = 0x40001274;\nr_ble_ll_scan_set_enable = 0x40001278;\nr_ble_ll_scan_set_peer_rpa = 0x4000127c;\nr_ble_ll_scan_set_perfer_addr = 0x40001280;\nr_ble_ll_scan_set_scan_params = 0x40001284;\nr_ble_ll_scan_sm_start = 0x40001288;\nr_ble_ll_scan_sm_stop = 0x4000128c;\nr_ble_ll_scan_time_hci_to_ticks = 0x40001290;\nr_ble_ll_scan_update_aux_data = 0x40001294;\nr_ble_ll_scan_whitelist_enabled = 0x40001298;\nr_ble_ll_set_default_privacy_mode = 0x4000129c;\nr_ble_ll_set_default_sync_transfer_params = 0x400012a0;\nr_ble_ll_set_ext_scan_params = 0x400012a4;\nr_ble_ll_set_host_feat = 0x400012a8;\nr_ble_ll_set_public_addr = 0x400012ac;\nr_ble_ll_set_random_addr = 0x400012b0;\nr_ble_ll_set_sync_transfer_params = 0x400012b4;\nr_ble_ll_state_get = 0x400012b8;\nr_ble_ll_state_set = 0x400012bc;\nr_ble_ll_sync_adjust_ext_hdr = 0x400012c0;\nr_ble_ll_sync_cancel = 0x400012c4;\nr_ble_ll_sync_cancel_complete_event = 0x400012c8;\nr_ble_ll_sync_check_acad = 0x400012cc;\nr_ble_ll_sync_check_failed = 0x400012d0;\nr_ble_ll_sync_create = 0x400012d4;\nr_ble_ll_sync_deinit = 0x400012d8;\nr_ble_ll_sync_enabled = 0x400012dc;\nr_ble_ll_sync_env_init = 0x400012e0;\nr_ble_ll_sync_est_event_failed = 0x400012e4;\nr_ble_ll_sync_est_event_success = 0x400012e8;\nr_ble_ll_sync_established = 0x400012ec;\nr_ble_ll_sync_filter_enabled = 0x400012f0;\nr_ble_ll_sync_find = 0x400012f4;\nr_ble_ll_sync_get_cur_sm = 0x400012f8;\nr_ble_ll_sync_get_handle = 0x400012fc;\nr_ble_ll_sync_get_sm = 0x40001300;\nr_ble_ll_sync_info_event = 0x40001304;\nr_ble_ll_sync_init = 0x40001308;\nr_ble_ll_sync_list_add = 0x4000130c;\nr_ble_ll_sync_list_clear = 0x40001310;\nr_ble_ll_sync_list_empty = 0x40001314;\nr_ble_ll_sync_list_get_free = 0x40001318;\nr_ble_ll_sync_list_remove = 0x4000131c;\nr_ble_ll_sync_list_search = 0x40001320;\nr_ble_ll_sync_list_size = 0x40001324;\nr_ble_ll_sync_lost_event = 0x40001328;\nr_ble_ll_sync_next_event = 0x4000132c;\nr_ble_ll_sync_on_list = 0x40001330;\nr_ble_ll_sync_parse_ext_hdr = 0x40001334;\nr_ble_ll_sync_periodic_ind = 0x40001338;\nr_ble_ll_sync_phy_mode_to_aux_phy = 0x4000133c;\nr_ble_ll_sync_phy_mode_to_hci = 0x40001340;\nr_ble_ll_sync_put_syncinfo = 0x40001344;\nr_ble_ll_sync_receive_enable = 0x40001348;\nr_ble_ll_sync_reserve = 0x4000134c;\nr_ble_ll_sync_reset = 0x40001350;\nr_ble_ll_sync_reset_sm = 0x40001354;\nr_ble_ll_sync_rx_pkt_in = 0x40001358;\nr_ble_ll_sync_send_per_adv_rpt = 0x4000135c;\nr_ble_ll_sync_send_sync_ind = 0x40001360;\nr_ble_ll_sync_send_truncated_per_adv_rpt = 0x40001364;\nr_ble_ll_sync_sm_clear = 0x40001368;\nr_ble_ll_sync_terminate = 0x4000136c;\nr_ble_ll_sync_transfer = 0x40001370;\nr_ble_ll_sync_transfer_get = 0x40001374;\nr_ble_ll_sync_transfer_received = 0x40001378;\nr_ble_ll_task = 0x4000137c;\nr_ble_ll_trace_set_func = 0x40001380;\nr_ble_ll_trace_u32 = 0x40001384;\nr_ble_ll_trace_u32x2 = 0x40001388;\nr_ble_ll_trace_u32x3 = 0x4000138c;\nr_ble_ll_tx_flat_mbuf_pducb = 0x40001390;\nr_ble_ll_tx_mbuf_pducb = 0x40001394;\nr_ble_ll_tx_pkt_in = 0x40001398;\nr_ble_ll_update_max_tx_octets_phy_mode = 0x4000139c;\nr_ble_ll_usecs_to_ticks_round_up = 0x400013a0;\nr_ble_ll_utils_calc_access_addr = 0x400013a4;\nr_ble_ll_utils_calc_dci_csa2 = 0x400013a8;\nr_ble_ll_utils_calc_num_used_chans = 0x400013ac;\nr_ble_ll_utils_calc_window_widening = 0x400013b0;\nr_ble_ll_utils_csa2_perm = 0x400013b4;\nr_ble_ll_utils_csa2_prng = 0x400013b8;\nr_ble_ll_utils_remapped_channel = 0x400013bc;\nr_ble_ll_whitelist_add = 0x400013c0;\nr_ble_ll_whitelist_chg_allowed = 0x400013c4;\nr_ble_ll_whitelist_clear = 0x400013c8;\nr_ble_ll_whitelist_read_size = 0x400013cc;\nr_ble_ll_whitelist_rmv = 0x400013d0;\nr_ble_ll_whitelist_search = 0x400013d4;\nr_ble_ll_write_rf_path_compensation = 0x400013d8;\nr_ble_lll_adv_aux_scannable_pdu_payload_len = 0x400013dc;\nr_ble_lll_adv_aux_schedule = 0x400013e0;\nr_ble_lll_adv_aux_schedule_first = 0x400013e4;\nr_ble_lll_adv_aux_schedule_next = 0x400013e8;\nr_ble_lll_adv_aux_scheduled = 0x400013ec;\nr_ble_lll_adv_aux_set_start_time = 0x400013f0;\nr_ble_lll_adv_coex_dpc_calc_pti_update_itvl = 0x400013f4;\nr_ble_lll_adv_coex_dpc_process_pri = 0x400013f8;\nr_ble_lll_adv_coex_dpc_process_sec = 0x400013fc;\nr_ble_lll_adv_coex_dpc_pti_get = 0x40001400;\nr_ble_lll_adv_coex_dpc_update = 0x40001404;\nr_ble_lll_adv_coex_dpc_update_on_adv_start = 0x40001408;\nr_ble_lll_adv_coex_dpc_update_on_aux_scheduled = 0x4000140c;\nr_ble_lll_adv_coex_dpc_update_on_data_updated = 0x40001410;\nr_ble_lll_adv_coex_dpc_update_on_event_end = 0x40001414;\nr_ble_lll_adv_coex_dpc_update_on_event_scheduled = 0x40001418;\nr_ble_lll_adv_done = 0x4000141c;\nr_ble_lll_adv_drop_event = 0x40001420;\nr_ble_lll_adv_event_done = 0x40001424;\nr_ble_lll_adv_event_rmvd_from_sched = 0x40001428;\nr_ble_lll_adv_ext_estimate_data_itvl = 0x4000142c;\nr_ble_lll_adv_get_sec_pdu_len = 0x40001430;\nr_ble_lll_adv_halt = 0x40001434;\nr_ble_lll_adv_make_done = 0x40001438;\nr_ble_lll_adv_periodic_done = 0x4000143c;\nr_ble_lll_adv_periodic_event_done = 0x40001440;\nr_ble_lll_adv_periodic_rmvd_from_sched = 0x40001444;\nr_ble_lll_adv_periodic_schedule_first = 0x40001448;\nr_ble_lll_adv_periodic_schedule_next = 0x4000144c;\nr_ble_lll_adv_periodic_start = 0x40001450;\nr_ble_lll_adv_periodic_stop = 0x40001454;\nr_ble_lll_adv_pri_schedule_tx_pdu = 0x40001458;\nr_ble_lll_adv_reschedule_event = 0x4000145c;\nr_ble_lll_adv_reschedule_periodic_event = 0x40001460;\nr_ble_lll_adv_rx_pkt_isr = 0x40001464;\nr_ble_lll_adv_sec_done = 0x40001468;\nr_ble_lll_adv_sec_event_done = 0x4000146c;\nr_ble_lll_adv_sec_schedule_next_aux = 0x40001470;\nr_ble_lll_adv_secondary_tx_start_cb = 0x40001474;\nr_ble_lll_adv_sm_deinit = 0x40001478;\nr_ble_lll_adv_sm_event_init = 0x4000147c;\nr_ble_lll_adv_sm_event_restore = 0x40001480;\nr_ble_lll_adv_sm_event_store = 0x40001484;\nr_ble_lll_adv_sm_init = 0x40001488;\nr_ble_lll_adv_sm_reset = 0x4000148c;\nr_ble_lll_adv_start = 0x40001490;\nr_ble_lll_adv_stop = 0x40001494;\nr_ble_lll_adv_sync_next_scheduled = 0x40001498;\nr_ble_lll_adv_sync_schedule = 0x4000149c;\nr_ble_lll_adv_sync_tx_done = 0x400014a0;\nr_ble_lll_adv_sync_tx_end = 0x400014a4;\nr_ble_lll_adv_sync_tx_start_cb = 0x400014a8;\nr_ble_lll_adv_tx_done = 0x400014ac;\nr_ble_lll_adv_tx_start_cb = 0x400014b0;\nr_ble_lll_adv_update_rsp_offset = 0x400014b4;\nr_ble_lll_aux_scan_cb = 0x400014b8;\nr_ble_lll_aux_scan_drop = 0x400014bc;\nr_ble_lll_aux_scan_drop_event_cb = 0x400014c0;\nr_ble_lll_calc_us_convert_tick_unit = 0x400014c4;\nr_ble_lll_conn_append_tx_buffer = 0x400014c8;\nr_ble_lll_conn_can_send_next_pdu = 0x400014cc;\nr_ble_lll_conn_check_opcode_matched = 0x400014d0;\nr_ble_lll_conn_coex_dpc_process = 0x400014d4;\nr_ble_lll_conn_coex_dpc_pti_get = 0x400014d8;\nr_ble_lll_conn_coex_dpc_update = 0x400014dc;\nr_ble_lll_conn_coex_dpc_update_on_event_end = 0x400014e0;\nr_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4;\nr_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8;\nr_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec;\nr_ble_lll_conn_cth_flow_free_credit = 0x400014f0;\nr_ble_lll_conn_current_sm_over = 0x400014f4;\nr_ble_lll_conn_env_deinit = 0x400014fc;\nr_ble_lll_conn_env_init = 0x40001500;\nr_ble_lll_conn_event_end = 0x40001504;\nr_ble_lll_conn_event_end_timer_cb = 0x40001508;\nr_ble_lll_conn_event_halt = 0x4000150c;\nr_ble_lll_conn_event_is_over = 0x40001510;\nr_ble_lll_conn_event_start_cb = 0x40001514;\nr_ble_lll_conn_free_rx_mbuf = 0x40001518;\nr_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c;\nr_ble_lll_conn_get_ce_end_time = 0x40001520;\nr_ble_lll_conn_get_next_sched_time = 0x40001524;\nr_ble_lll_conn_get_rx_mbuf = 0x40001528;\nr_ble_lll_conn_halt = 0x4000152c;\nr_ble_lll_conn_master_common_init = 0x40001530;\nr_ble_lll_conn_master_new = 0x40001534;\nr_ble_lll_conn_module_deinit = 0x40001538;\nr_ble_lll_conn_module_init = 0x4000153c;\nr_ble_lll_conn_module_reset = 0x40001540;\nr_ble_lll_conn_no_mem_evt_pre_cb = 0x40001544;\nr_ble_lll_conn_pre_process = 0x40001548;\nr_ble_lll_conn_process_acked_pdu = 0x4000154c;\nr_ble_lll_conn_process_in_isr = 0x40001550;\nr_ble_lll_conn_recv_ack = 0x40001554;\nr_ble_lll_conn_recv_valid_packet = 0x40001558;\nr_ble_lll_conn_reset_pending_sched = 0x4000155c;\nr_ble_lll_conn_rx_pkt_isr = 0x40001560;\nr_ble_lll_conn_sched_next_anchor = 0x40001564;\nr_ble_lll_conn_sched_next_event = 0x40001568;\nr_ble_lll_conn_set_slave_flow_control = 0x4000156c;\nr_ble_lll_conn_slave_new = 0x40001570;\nr_ble_lll_conn_sm_new = 0x40001574;\nr_ble_lll_conn_sm_npl_deinit = 0x40001578;\nr_ble_lll_conn_sm_npl_init = 0x4000157c;\nr_ble_lll_conn_superversion_timer_cb = 0x40001580;\nr_ble_lll_conn_timeout = 0x40001584;\nr_ble_lll_conn_update_anchor = 0x40001588;\nr_ble_lll_conn_update_conn_ind_params = 0x4000158c;\nr_ble_lll_conn_update_encryption = 0x40001590;\nr_ble_lll_conn_update_tx_buffer = 0x40001594;\nr_ble_lll_deinit = 0x40001598;\nr_ble_lll_dtm_calculate_itvl = 0x4000159c;\nr_ble_lll_dtm_ctx_free = 0x400015a0;\nr_ble_lll_dtm_deinit = 0x400015a4;\nr_ble_lll_dtm_end_test = 0x400015a8;\nr_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;\nr_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;\nr_ble_lll_dtm_init = 0x400015b4;\nr_ble_lll_dtm_reset = 0x400015b8;\nr_ble_lll_dtm_rx_create_ctx = 0x400015bc;\nr_ble_lll_dtm_rx_isr_end = 0x400015c0;\nr_ble_lll_dtm_rx_isr_start = 0x400015c4;\nr_ble_lll_dtm_rx_pkt_in = 0x400015c8;\nr_ble_lll_dtm_rx_sched_cb = 0x400015cc;\nr_ble_lll_dtm_rx_start = 0x400015d0;\nr_ble_lll_dtm_rx_test = 0x400015d4;\nr_ble_lll_dtm_set_next = 0x400015d8;\nr_ble_lll_dtm_tx_create_ctx = 0x400015dc;\nr_ble_lll_dtm_tx_done = 0x400015e0;\nr_ble_lll_dtm_tx_sched_cb = 0x400015e4;\nr_ble_lll_dtm_tx_test = 0x400015e8;\nr_ble_lll_dtm_wfr_timer_exp = 0x400015ec;\nr_ble_lll_event_rx_pkt = 0x400015f0;\nr_ble_lll_ext_scan_coex_dpc_process = 0x400015f4;\nr_ble_lll_ext_scan_coex_dpc_pti_get = 0x400015f8;\nr_ble_lll_ext_scan_coex_dpc_update = 0x400015fc;\nr_ble_lll_ext_scan_coex_dpc_update_on_start = 0x40001600;\nr_ble_lll_hci_dtm_rx_test = 0x40001604;\nr_ble_lll_hci_dtm_rx_test_v2 = 0x40001608;\nr_ble_lll_hci_dtm_tx_test = 0x4000160c;\nr_ble_lll_hci_dtm_tx_test_ext = 0x40001610;\nr_ble_lll_hci_dtm_tx_test_v2 = 0x40001614;\nr_ble_lll_hci_dtm_tx_test_v2_ext = 0x40001618;\nr_ble_lll_init = 0x4000161c;\nr_ble_lll_init_pre_process = 0x40001620;\nr_ble_lll_per_adv_coex_dpc_calc_pti_update_itvl = 0x40001628;\nr_ble_lll_per_adv_coex_dpc_process = 0x4000162c;\nr_ble_lll_per_adv_coex_dpc_pti_get = 0x40001630;\nr_ble_lll_per_adv_coex_dpc_update = 0x40001634;\nr_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638;\nr_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c;\nr_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640;\nr_ble_lll_reset = 0x40001644;\nr_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;\nr_ble_lll_rfmgmt_deinit = 0x4000164c;\nr_ble_lll_rfmgmt_disable = 0x40001650;\nr_ble_lll_rfmgmt_enable = 0x40001654;\nr_ble_lll_rfmgmt_enable_now = 0x40001658;\nr_ble_lll_rfmgmt_init = 0x4000165c;\nr_ble_lll_rfmgmt_is_enabled = 0x40001660;\nr_ble_lll_rfmgmt_release = 0x40001664;\nr_ble_lll_rfmgmt_release_ev = 0x40001668;\nr_ble_lll_rfmgmt_reset = 0x4000166c;\nr_ble_lll_rfmgmt_scan_changed = 0x40001670;\nr_ble_lll_rfmgmt_sched_changed = 0x40001674;\nr_ble_lll_rfmgmt_set_sleep_cb = 0x40001678;\nr_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c;\nr_ble_lll_rfmgmt_timer_exp = 0x40001680;\nr_ble_lll_rfmgmt_timer_reschedule = 0x40001684;\nr_ble_lll_rx_pdu_in = 0x40001688;\nr_ble_lll_rx_pkt_in = 0x4000168c;\nr_ble_lll_rx_pkt_isr = 0x40001690;\nr_ble_lll_scan_abort_aux_sched = 0x40001694;\nr_ble_lll_scan_aux_data_free = 0x40001698;\nr_ble_lll_scan_chk_resume = 0x4000169c;\nr_ble_lll_scan_clean_cur_aux_data = 0x400016a0;\nr_ble_lll_scan_coex_event_cb = 0x400016a4;\nr_ble_lll_scan_common_init = 0x400016a8;\nr_ble_lll_scan_deinit = 0x400016ac;\nr_ble_lll_scan_duration_period_timers_restart = 0x400016b0;\nr_ble_lll_scan_duration_period_timers_stop = 0x400016b4;\nr_ble_lll_scan_duration_timer_cb = 0x400016b8;\nr_ble_lll_scan_event_proc = 0x400016bc;\nr_ble_lll_scan_ext_adv_init = 0x400016c0;\nr_ble_lll_scan_halt = 0x400016c4;\nr_ble_lll_scan_has_sent_scan_req = 0x400016c8;\nr_ble_lll_scan_init = 0x400016cc;\nr_ble_lll_scan_npl_init = 0x400016d0;\nr_ble_lll_scan_npl_reset = 0x400016d4;\nr_ble_lll_scan_npl_restore = 0x400016d8;\nr_ble_lll_scan_npl_store = 0x400016dc;\nr_ble_lll_scan_period_timer_cb = 0x400016e0;\nr_ble_lll_scan_process_adv_in_isr = 0x400016e4;\nr_ble_lll_scan_process_rsp_in_isr = 0x400016e8;\nr_ble_lll_scan_req_backoff = 0x400016ec;\nr_ble_lll_scan_restart = 0x400016f0;\nr_ble_lll_scan_rx_isr_on_aux = 0x400016f4;\nr_ble_lll_scan_rx_isr_on_legacy = 0x400016f8;\nr_ble_lll_scan_rx_pkt_isr = 0x400016fc;\nr_ble_lll_scan_sched_next_aux = 0x40001700;\nr_ble_lll_scan_sched_remove = 0x40001704;\nr_ble_lll_scan_start = 0x40001708;\nr_ble_lll_scan_start_rx = 0x4000170c;\nr_ble_lll_scan_stop = 0x40001710;\nr_ble_lll_scan_targeta_is_matched = 0x40001714;\nr_ble_lll_scan_timer_cb = 0x40001718;\nr_ble_lll_sched_adv_new = 0x4000171c;\nr_ble_lll_sched_adv_resched_pdu = 0x40001720;\nr_ble_lll_sched_adv_reschedule = 0x40001724;\nr_ble_lll_sched_aux_scan = 0x40001728;\nr_ble_lll_sched_conn_overlap = 0x4000172c;\nr_ble_lll_sched_conn_reschedule = 0x40001730;\nr_ble_lll_sched_deinit = 0x40001734;\nr_ble_lll_sched_dtm = 0x40001738;\nr_ble_lll_sched_env_init = 0x4000173c;\nr_ble_lll_sched_execute_item = 0x40001744;\nr_ble_lll_sched_init = 0x40001748;\nr_ble_lll_sched_insert_if_empty = 0x4000174c;\nr_ble_lll_sched_is_overlap = 0x40001750;\nr_ble_lll_sched_master_new = 0x40001754;\nr_ble_lll_sched_next_time = 0x40001758;\nr_ble_lll_sched_overlaps_current = 0x4000175c;\nr_ble_lll_sched_periodic_adv = 0x40001760;\nr_ble_lll_sched_rmv_elem = 0x40001764;\nr_ble_lll_sched_rmv_elem_type = 0x40001768;\nr_ble_lll_sched_run = 0x4000176c;\nr_ble_lll_sched_scan_req_over_aux_ptr = 0x40001770;\nr_ble_lll_sched_slave_new = 0x40001774;\nr_ble_lll_sched_stop = 0x40001778;\nr_ble_lll_sched_sync = 0x4000177c;\nr_ble_lll_sched_sync_overlaps_current = 0x40001780;\nr_ble_lll_sched_sync_reschedule = 0x40001784;\nr_ble_lll_sync_chain_start_cb = 0x40001788;\nr_ble_lll_sync_coex_dpc_process = 0x4000178c;\nr_ble_lll_sync_coex_dpc_pti_get = 0x40001790;\nr_ble_lll_sync_coex_dpc_update = 0x40001794;\nr_ble_lll_sync_current_sm_over = 0x40001798;\nr_ble_lll_sync_deinit = 0x4000179c;\nr_ble_lll_sync_event_end = 0x400017a0;\nr_ble_lll_sync_event_end_cb = 0x400017a4;\nr_ble_lll_sync_event_start_cb = 0x400017a8;\nr_ble_lll_sync_get_event_end_time = 0x400017ac;\nr_ble_lll_sync_halt = 0x400017b0;\nr_ble_lll_sync_init = 0x400017b4;\nr_ble_lll_sync_new = 0x400017b8;\nr_ble_lll_sync_reset = 0x400017bc;\nr_ble_lll_sync_reset_sm = 0x400017c0;\nr_ble_lll_sync_rmvd_from_sched = 0x400017c4;\nr_ble_lll_sync_rx_pkt_isr = 0x400017c8;\nr_ble_lll_sync_schedule_chain = 0x400017cc;\nr_ble_lll_sync_stop = 0x400017d0;\nr_ble_lll_sync_trnasfer_sched = 0x400017d4;\nr_ble_phy_access_addr_get = 0x400017d8;\nr_ble_phy_calculate_rxtx_ifs = 0x400017dc;\nr_ble_phy_calculate_rxwindow = 0x400017e0;\nr_ble_phy_calculate_txrx_ifs = 0x400017e4;\nr_ble_phy_check_bb_status = 0x400017e8;\nr_ble_phy_complete_rx_info = 0x400017ec;\nr_ble_phy_config_access_addr = 0x400017f0;\nr_ble_phy_data_make = 0x400017f4;\nr_ble_phy_disable = 0x400017f8;\nr_ble_phy_disable_irq = 0x400017fc;\nr_ble_phy_disable_whitening = 0x40001800;\nr_ble_phy_enable_whitening = 0x40001804;\nr_ble_phy_encrypt_disable = 0x40001808;\nr_ble_phy_env_init = 0x4000180c;\nr_ble_phy_get_current_phy = 0x40001810;\nr_ble_phy_get_packet_counter = 0x40001814;\nr_ble_phy_get_packet_status = 0x40001818;\nr_ble_phy_get_pyld_time_offset = 0x4000181c;\nr_ble_phy_get_rx_phy_mode = 0x40001820;\nr_ble_phy_get_seq_end_st = 0x40001824;\nr_ble_phy_init = 0x40001828;\nr_ble_phy_isr = 0x4000182c;\nr_ble_phy_max_data_pdu_pyld = 0x40001830;\nr_ble_phy_mode_config = 0x40001834;\nr_ble_phy_mode_convert = 0x40001838;\nr_ble_phy_mode_write = 0x4000183c;\nr_ble_phy_module_deinit = 0x40001840;\nr_ble_phy_module_init = 0x40001844;\nr_ble_phy_monitor_bb_sync = 0x40001848;\nr_ble_phy_reset_bb_monitor = 0x4000184c;\nr_ble_phy_resolv_list_disable = 0x40001850;\nr_ble_phy_resolv_list_enable = 0x40001854;\nr_ble_phy_restart_sequence = 0x40001858;\nr_ble_phy_rx_set_start_time_forcibly = 0x4000185c;\nr_ble_phy_rxpdu_copy = 0x40001860;\nr_ble_phy_seq_encrypt_enable = 0x40001864;\nr_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001868;\nr_ble_phy_sequence_end_isr = 0x4000186c;\nr_ble_phy_sequence_get_mode = 0x40001870;\nr_ble_phy_sequence_is_running = 0x40001874;\nr_ble_phy_sequence_is_waiting_rsp = 0x40001878;\nr_ble_phy_sequence_single_end = 0x4000187c;\nr_ble_phy_sequence_tx_end_invoke = 0x40001880;\nr_ble_phy_sequence_update_conn_ind_params = 0x40001884;\nr_ble_phy_set_adv_mode = 0x40001888;\nr_ble_phy_set_coex_pti = 0x4000188c;\nr_ble_phy_set_conn_ind_pdu = 0x40001890;\nr_ble_phy_set_conn_mode = 0x40001894;\nr_ble_phy_set_dev_address = 0x40001898;\nr_ble_phy_set_rx_pwr_compensation = 0x4000189c;\nr_ble_phy_set_rxhdr = 0x400018a0;\nr_ble_phy_set_scan_mode = 0x400018a4;\nr_ble_phy_set_sequence_mode = 0x400018a8;\nr_ble_phy_set_single_packet_rx_sequence = 0x400018ac;\nr_ble_phy_set_single_packet_tx_sequence = 0x400018b0;\nr_ble_phy_set_tx_rx_transition = 0x400018b4;\nr_ble_phy_set_txend_cb = 0x400018b8;\nr_ble_phy_setchan = 0x400018bc;\nr_ble_phy_start_rx_immediately = 0x400018c0;\nr_ble_phy_state_get = 0x400018c4;\nr_ble_phy_timer_config_start_time = 0x400018c8;\nr_ble_phy_timer_start_now = 0x400018cc;\nr_ble_phy_timer_stop = 0x400018d0;\nr_ble_phy_tx_set_start_time = 0x400018d4;\nr_ble_phy_txpower_round = 0x400018d8;\nr_ble_phy_txpwr_set = 0x400018dc;\nr_ble_phy_update_conn_sequence = 0x400018e0;\nr_ble_phy_update_encryption = 0x400018e4;\nr_ble_phy_update_ifs = 0x400018e8;\nr_ble_phy_xcvr_state_get = 0x400018ec;\nr_ble_plf_set_log_level = 0x400018f0;\nr_ble_rtc_wake_up_cpu_init = 0x400018f4;\nr_ble_rtc_wake_up_state_clr = 0x400018f8;\nr_ble_vendor_hci_register = 0x400018fc;\nr_bt_rf_coex_cfg_set = 0x40001900;\nr_bt_rf_coex_coded_txrx_time_upper_lim = 0x40001904;\nr_bt_rf_coex_dft_pti_set = 0x40001908;\nr_bt_rf_coex_hook_deinit = 0x4000190c;\nr_bt_rf_coex_hook_init = 0x40001910;\nr_bt_rf_coex_hook_st_set = 0x40001914;\nr_bt_rf_coex_hooks_p_set_default = 0x40001918;\nr_btdm_disable_adv_delay = 0x4000191c;\nr_btdm_switch_phy_coded = 0x40001920;\nr_esp_wait_disabled = 0x40001924;\nr_get_be16 = 0x40001928;\nr_get_be24 = 0x4000192c;\nr_get_be32 = 0x40001930;\nr_get_be64 = 0x40001934;\nr_get_le16 = 0x40001938;\nr_get_le24 = 0x4000193c;\nr_get_le32 = 0x40001940;\nr_get_le64 = 0x40001944;\nr_get_local_irk_offset = 0x40001948;\nr_get_local_rpa_offset = 0x4000194c;\nr_get_max_skip = 0x40001950;\nr_get_peer_id_offset = 0x40001954;\nr_get_peer_irk_offset = 0x40001958;\nr_get_peer_rpa_offset = 0x4000195c;\nr_hal_rtc_intr_init = 0x40001960;\nr_hal_rtc_irq_handler = 0x40001964;\nr_hal_timer_deinit = 0x40001968;\nr_hal_timer_disable_irq = 0x4000196c;\nr_hal_timer_env_init = 0x40001970;\nr_hal_timer_init = 0x40001974;\nr_hal_timer_process = 0x40001978;\nr_hal_timer_read = 0x4000197c;\nr_hal_timer_read_tick = 0x40001980;\nr_hal_timer_set_cb = 0x40001984;\nr_hal_timer_set_exp_tick = 0x40001988;\nr_hal_timer_start = 0x4000198c;\nr_hal_timer_start_at = 0x40001990;\nr_hal_timer_stop = 0x40001994;\nr_hal_timer_task_start = 0x40001998;\nr_ll_assert = 0x4000199c;\nr_mem_init_mbuf_pool = 0x400019a0;\nr_mem_malloc_mbuf_pool = 0x400019a4;\nr_mem_malloc_mbufpkt_pool = 0x400019a8;\nr_mem_malloc_mempool = 0x400019ac;\nr_mem_malloc_mempool_ext = 0x400019b0;\nr_mem_malloc_mempool_gen = 0x400019b4;\nr_mem_pullup_obj = 0x400019b8;\nr_mem_split_frag = 0x400019bc;\nr_os_cputime_get32 = 0x400019c0;\nr_os_cputime_ticks_to_usecs = 0x400019c4;\nr_os_cputime_timer_init = 0x400019c8;\nr_os_cputime_timer_relative = 0x400019cc;\nr_os_cputime_timer_start = 0x400019d0;\nr_os_cputime_timer_stop = 0x400019d4;\nr_os_cputime_usecs_to_ticks = 0x400019d8;\nr_os_mbuf_adj = 0x400019dc;\nr_os_mbuf_append = 0x400019e0;\nr_os_mbuf_appendfrom = 0x400019e4;\nr_os_mbuf_cmpf = 0x400019e8;\nr_os_mbuf_cmpm = 0x400019ec;\nr_os_mbuf_concat = 0x400019f0;\nr_os_mbuf_copydata = 0x400019f4;\nr_os_mbuf_copyinto = 0x400019f8;\nr_os_mbuf_dup = 0x400019fc;\nr_os_mbuf_extend = 0x40001a00;\nr_os_mbuf_free = 0x40001a04;\nr_os_mbuf_free_chain = 0x40001a08;\nr_os_mbuf_get = 0x40001a0c;\nr_os_mbuf_get_pkthdr = 0x40001a10;\nr_os_mbuf_leadingspace = 0x40001a14;\nr_os_mbuf_len = 0x40001a18;\nr_os_mbuf_off = 0x40001a1c;\nr_os_mbuf_pack_chains = 0x40001a20;\nr_os_mbuf_pool_init = 0x40001a24;\nr_os_mbuf_prepend = 0x40001a28;\nr_os_mbuf_prepend_pullup = 0x40001a2c;\nr_os_mbuf_pullup = 0x40001a30;\nr_os_mbuf_trailingspace = 0x40001a34;\nr_os_mbuf_trim_front = 0x40001a38;\nr_os_mbuf_widen = 0x40001a3c;\nr_os_memblock_from = 0x40001a40;\nr_os_memblock_get = 0x40001a44;\nr_os_memblock_put = 0x40001a48;\nr_os_memblock_put_from_cb = 0x40001a4c;\nr_os_mempool_clear = 0x40001a50;\nr_os_mempool_ext_clear = 0x40001a54;\nr_os_mempool_ext_init = 0x40001a58;\nr_os_mempool_info_get_next = 0x40001a5c;\nr_os_mempool_init = 0x40001a60;\nr_os_mempool_init_internal = 0x40001a64;\nr_os_mempool_is_sane = 0x40001a68;\nr_os_mempool_module_init = 0x40001a6c;\nr_os_mempool_unregister = 0x40001a70;\nr_os_mqueue_get = 0x40001a74;\nr_os_mqueue_init = 0x40001a78;\nr_os_mqueue_put = 0x40001a7c;\nr_os_msys_count = 0x40001a80;\nr_os_msys_get = 0x40001a84;\nr_os_msys_get_pkthdr = 0x40001a88;\nr_os_msys_num_free = 0x40001a8c;\nr_os_msys_register = 0x40001a90;\nr_os_msys_reset = 0x40001a94;\nr_pri_phy_valid = 0x40001a98;\nr_put_be16 = 0x40001a9c;\nr_put_be24 = 0x40001aa0;\nr_put_be32 = 0x40001aa4;\nr_put_be64 = 0x40001aa8;\nr_put_le16 = 0x40001aac;\nr_put_le24 = 0x40001ab0;\nr_put_le32 = 0x40001ab4;\nr_put_le64 = 0x40001ab8;\nr_rtc0_timer_handler = 0x40001abc;\nr_sdkconfig_get_opts = 0x40001ac0;\nr_sdkconfig_set_opts = 0x40001ac4;\nr_sec_phy_valid = 0x40001ac8;\nr_swap_buf = 0x40001acc;\nr_swap_in_place = 0x40001ad0;\n\/* Data (.data, .bss, .rodata) *\/\nble_lll_dtm_module_env_p = 0x3fcdffc4;\ng_ble_lll_dtm_prbs15_data = 0x3ff4fee4;\ng_ble_lll_dtm_prbs9_data = 0x3ff4fde4;\ng_channel_rf_to_index = 0x3ff4fdbc;\ng_ble_lll_rfmgmt_data = 0x3fcdff7c;\ng_ble_sleep_enter_cb = 0x3fcdff78;\ng_ble_sleep_exit_cb = 0x3fcdff74;\nble_lll_sched_env_p = 0x3fcdff70;\nble_ll_env_p = 0x3fcdff6c;\ng_ble_ll_pdu_header_tx_time_ro = 0x3ff4fdb4;\nble_ll_adv_env_p = 0x3fcdff68;\nble_ll_conn_env_p = 0x3fcdff64;\nble_ll_conn_required_phy_mask = 0x3ff4fdb0;\nble_ll_valid_conn_phy_mask = 0x3ff4fdaf;\ng_ble_ll_ctrl_pkt_lengths_ro = 0x3ff4fd8c;\nble_ll_hci_env_p = 0x3fcdff60;\ng_debug_le_private_key = 0x3ff4fd6c;\ng_ecc_key = 0x3fcdfefc;\nble_ll_rand_env_p = 0x3fcdfef8;\nble_ll_resolv_env_p = 0x3fcdfef4;\ng_ble_ll_resolve_hdr = 0x3fcdfeec;\ng_device_mode_default = 0x3fcdfe68;\nble_ll_scan_classify_filter_aux_check_cb = 0x3fcdfee8;\nble_ll_scan_classify_filter_check_cb = 0x3fcdfee4;\nble_ll_scan_env_p = 0x3fcdfee0;\ng_ble_ll_supp_cmds_ro = 0x3ff4fd3c;\nble_ll_sync_env_p = 0x3fcdfedc;\ng_ble_sca_ppm_tbl_ro = 0x3ff4fd2c;\npriv_config_opts = 0x3fcdfe48;\nble_hci_uart_reset_cmd = 0x3ff4fd28;\nble_hci_trans_env_p = 0x3fcdfed8;\nble_hci_trans_mode = 0x3fcdfe44;\nble_hci_trans_funcs_ptr = 0x3fcdfed4;\nr_ble_lll_stub_funcs_ptr = 0x3fcdfed0;\nr_ble_stub_funcs_ptr = 0x3fcdfecc;\nr_ext_funcs_p = 0x3fcdfec8;\nr_npl_funcs = 0x3fcdfec4;\nble_hw_env_p = 0x3fcdfec0;\nble_phy_module_env_p = 0x3fcdfebc;\ng_ble_phy_chan_freq_ro = 0x3ff4fd00;\ng_ble_phy_mode_pkt_start_off_ro = 0x3ff4fcf8;\ng_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fce8;\ng_ble_phy_t_rxaddrdelay_ro = 0x3ff4fce4;\ng_ble_phy_t_rxenddelay_ro = 0x3ff4fce0;\ng_ble_phy_t_txdelay_ro = 0x3ff4fcdc;\ng_ble_phy_t_txenddelay_ro = 0x3ff4fcd8;\ng_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcc8;\nhal_timer_env_p = 0x3fcdfeb8;\nr_osi_coex_funcs_p = 0x3fcdfeb4;\nbt_rf_coex_hooks = 0x3fcdfeac;\nbt_rf_coex_hooks_p = 0x3fcdfea8;\ncoex_hook_st_group_tab = 0x3ff4fcbc;\ncoex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcb8;\ns_ble_act_count_by_group = 0x3fcdfea4;\ns_ble_coex_st_map = 0x3fcdfe90;\nbt_rf_coex_cfg_cb = 0x3fcdfe74;\nbt_rf_coex_cfg_p = 0x3fcdfe70;\nbt_rf_coex_cfg_rom = 0x3ff4fc9c;\nbt_rf_coex_pti_dft_p = 0x3fcdfe6c;\nbt_rf_coex_pti_dft_rom = 0x3fcdfe04;\nconn_dynamic_pti_param_rom = 0x3ff4fc84;\nconn_phy_coded_max_data_time_param_rom = 0x3ff4fc80;\next_adv_dynamic_pti_param_rom = 0x3ff4fc4c;\next_scan_dynamic_param_rom = 0x3ff4fc14;\nlegacy_adv_dynamic_pti_param_rom = 0x3ff4fbf4;\nper_adv_dynamic_pti_param_rom = 0x3ff4fbd8;\nsync_dynamic_param_rom = 0x3ff4fbc0;\ng_ble_plf_log_level = 0x3fcdfe00;\ng_msys_pool_list = 0x3fcdfdf8;\ng_os_mempool_list = 0x3fcdfdf0;\n\n\n\/***************************************\n Group rom_pp\n ***************************************\/\n\n\/* Functions *\/\nesp_pp_rom_version_get = 0x40001ad4;\nRC_GetBlockAckTime = 0x40001ad8;\nebuf_list_remove = 0x40001adc;\nesf_buf_alloc = 0x40001ae0;\nesf_buf_alloc_dynamic = 0x40001ae4;\nesf_buf_recycle = 0x40001ae8;\nGetAccess = 0x40001aec;\nhal_mac_is_low_rate_enabled = 0x40001af0;\nhal_mac_tx_get_blockack = 0x40001af4;\nhal_mac_tx_set_ppdu = 0x40001af8;\nic_get_trc = 0x40001afc;\nic_mac_deinit = 0x40001b00;\nic_mac_init = 0x40001b04;\nic_interface_enabled = 0x40001b08;\nis_lmac_idle = 0x40001b0c;\nlmacAdjustTimestamp = 0x40001b10;\nlmacDiscardAgedMSDU = 0x40001b14;\nlmacDiscardMSDU = 0x40001b18;\nlmacEndFrameExchangeSequence = 0x40001b1c;\nlmacIsIdle = 0x40001b20;\nlmacIsLongFrame = 0x40001b24;\nlmacMSDUAged = 0x40001b28;\nlmacPostTxComplete = 0x40001b2c;\nlmacProcessAllTxTimeout = 0x40001b30;\nlmacProcessCollisions = 0x40001b34;\nlmacProcessRxSucData = 0x40001b38;\nlmacReachLongLimit = 0x40001b3c;\nlmacReachShortLimit = 0x40001b40;\nlmacRecycleMPDU = 0x40001b44;\nlmacRxDone = 0x40001b48;\nlmacSetTxFrame = 0x40001b4c;\nlmacTxDone = 0x40001b50;\nlmacTxFrame = 0x40001b54;\nmac_tx_set_duration = 0x40001b58;\nmac_tx_set_htsig = 0x40001b5c;\nmac_tx_set_plcp0 = 0x40001b60;\nmac_tx_set_plcp1 = 0x40001b64;\nmac_tx_set_plcp2 = 0x40001b68;\npm_check_state = 0x40001b6c;\npm_disable_dream_timer = 0x40001b70;\npm_disable_sleep_delay_timer = 0x40001b74;\npm_dream = 0x40001b78;\npm_mac_wakeup = 0x40001b7c;\npm_mac_sleep = 0x40001b80;\npm_enable_active_timer = 0x40001b84;\npm_enable_sleep_delay_timer = 0x40001b88;\npm_local_tsf_process = 0x40001b8c;\npm_set_beacon_filter = 0x40001b90;\npm_is_in_wifi_slice_threshold = 0x40001b94;\npm_is_waked = 0x40001b98;\npm_keep_alive = 0x40001b9c;\npm_on_beacon_rx = 0x40001ba0;\npm_on_data_rx = 0x40001ba4;\npm_on_tbtt = 0x40001ba8;\npm_parse_beacon = 0x40001bac;\npm_process_tim = 0x40001bb0;\npm_rx_beacon_process = 0x40001bb4;\npm_rx_data_process = 0x40001bb8;\npm_sleep = 0x40001bbc;\npm_sleep_for = 0x40001bc0;\npm_tbtt_process = 0x40001bc4;\nppAMPDU2Normal = 0x40001bc8;\nppAssembleAMPDU = 0x40001bcc;\nppCalFrameTimes = 0x40001bd0;\nppCalSubFrameLength = 0x40001bd4;\nppCalTxAMPDULength = 0x40001bd8;\nppCheckTxAMPDUlength = 0x40001bdc;\nppDequeueRxq_Locked = 0x40001be0;\nppDequeueTxQ = 0x40001be4;\nppEmptyDelimiterLength = 0x40001be8;\nppEnqueueRxq = 0x40001bec;\nppEnqueueTxDone = 0x40001bf0;\nppGetTxQFirstAvail_Locked = 0x40001bf4;\nppGetTxframe = 0x40001bf8;\nppMapTxQueue = 0x40001bfc;\nppProcTxSecFrame = 0x40001c00;\nppProcessRxPktHdr = 0x40001c04;\nppProcessTxQ = 0x40001c08;\nppRecordBarRRC = 0x40001c0c;\nlmacRequestTxopQueue = 0x40001c10;\nlmacReleaseTxopQueue = 0x40001c14;\nppRecycleAmpdu = 0x40001c18;\nppRecycleRxPkt = 0x40001c1c;\nppResortTxAMPDU = 0x40001c20;\nppResumeTxAMPDU = 0x40001c24;\nppRxFragmentProc = 0x40001c28;\nppRxPkt = 0x40001c2c;\nppRxProtoProc = 0x40001c30;\nppSearchTxQueue = 0x40001c34;\nppSearchTxframe = 0x40001c38;\nppSelectNextQueue = 0x40001c3c;\nppSubFromAMPDU = 0x40001c40;\nppTask = 0x40001c44;\nppTxPkt = 0x40001c48;\nppTxProtoProc = 0x40001c4c;\nppTxqUpdateBitmap = 0x40001c50;\npp_coex_tx_request = 0x40001c54;\npp_hdrsize = 0x40001c58;\npp_post = 0x40001c5c;\npp_process_hmac_waiting_txq = 0x40001c60;\nrcGetAmpduSched = 0x40001c64;\nrcUpdateRxDone = 0x40001c68;\nrc_get_trc = 0x40001c6c;\nrc_get_trc_by_index = 0x40001c70;\nrcAmpduLowerRate = 0x40001c74;\nrcampduuprate = 0x40001c78;\nrcClearCurAMPDUSched = 0x40001c7c;\nrcClearCurSched = 0x40001c80;\nrcClearCurStat = 0x40001c84;\nrcGetSched = 0x40001c88;\nrcLowerSched = 0x40001c8c;\nrcSetTxAmpduLimit = 0x40001c90;\nrcTxUpdatePer = 0x40001c94;\nrcUpdateAckSnr = 0x40001c98;\nrcUpdateRate = 0x40001c9c;\nrcUpdateTxDone = 0x40001ca0;\nrcUpdateTxDoneAmpdu2 = 0x40001ca4;\nrcUpSched = 0x40001ca8;\nrssi_margin = 0x40001cac;\nrx11NRate2AMPDULimit = 0x40001cb0;\nTRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001cb4;\nTRC_AMPDU_PER_UP_THRESHOLD = 0x40001cb8;\ntrc_calc_duration = 0x40001cbc;\ntrc_isTxAmpduOperational = 0x40001cc0;\ntrc_onAmpduOp = 0x40001cc4;\nTRC_PER_IS_GOOD = 0x40001cc8;\ntrc_SetTxAmpduState = 0x40001ccc;\ntrc_tid_isTxAmpduOperational = 0x40001cd0;\ntrcAmpduSetState = 0x40001cd4;\nwDevCheckBlockError = 0x40001cd8;\nwDev_AppendRxBlocks = 0x40001cdc;\nwDev_DiscardFrame = 0x40001ce0;\nwDev_GetNoiseFloor = 0x40001ce4;\nwDev_IndicateAmpdu = 0x40001ce8;\nwDev_IndicateFrame = 0x40001cec;\nwdev_mac_reg_load = 0x40001cf0;\nwdev_mac_reg_store = 0x40001cf4;\nwdev_mac_special_reg_load = 0x40001cf8;\nwdev_mac_special_reg_store = 0x40001cfc;\nwdev_mac_wakeup = 0x40001d00;\nwdev_mac_sleep = 0x40001d04;\nwDev_ProcessFiq = 0x40001d08;\nwDev_ProcessRxSucData = 0x40001d0c;\nwdevProcessRxSucDataAll = 0x40001d10;\nwdev_csi_len_align = 0x40001d14;\nppDequeueTxDone_Locked = 0x40001d18;\nppProcTxDone = 0x40001d1c;\npm_tx_data_done_process = 0x40001d20;\nconfig_is_cache_tx_buf_enabled = 0x40001d24;\nppMapWaitTxq = 0x40001d28;\nppProcessWaitingQueue = 0x40001d2c;\nppDisableQueue = 0x40001d30;\npm_allow_tx = 0x40001d34;\nwdev_is_data_in_rxlist = 0x40001d38;\nppProcTxCallback = 0x40001d3c;\npm_is_open = 0x40001d40;\npm_wake_up = 0x40001d44;\npm_wake_done = 0x40001d48;\npm_disable_disconnected_sleep_delay_timer = 0x40001d4c;\npm_enable_disconnected_sleep_delay_timer = 0x40001d50;\nhal_mac_get_txq_state = 0x40001d54;\nhal_mac_clr_txq_state = 0x40001d58;\nhal_mac_tx_set_cca = 0x40001d5c;\nhal_mac_set_txq_invalid = 0x40001d60;\nhal_mac_txq_disable = 0x40001d64;\nhal_mac_is_txq_enabled = 0x40001d68;\nhal_mac_get_txq_pmd = 0x40001d6c;\nlmacDiscardFrameExchangeSequence = 0x40001d70;\nlmacDisableTransmit = 0x40001d74;\nlmacProcessTxTimeout = 0x40001d78;\nlmacProcessTxSuccess = 0x40001d7c;\nlmacProcessCollision = 0x40001d80;\nlmacProcessTxRtsError = 0x40001d84;\nlmacProcessCtsTimeout = 0x40001d88;\nlmacProcessTxComplete = 0x40001d8c;\nlmacProcessAckTimeout = 0x40001d90;\nlmacProcessTxError = 0x40001d94;\nlmacProcessTxseckiderr = 0x40001d98;\nrcReachRetryLimit = 0x40001d9c;\nlmacProcessShortRetryFail = 0x40001da0;\nlmacEndRetryAMPDUFail = 0x40001da4;\nppFillAMPDUBar = 0x40001da8;\nrcGetRate = 0x40001dac;\nppReSendBar = 0x40001db0;\nlmacProcessLongRetryFail = 0x40001db4;\nlmacRetryTxFrame = 0x40001db8;\nlmacProcessCollisions_task = 0x40001dbc;\nlmacProcessTxopQComplete = 0x40001dc0;\nlmacInitAc = 0x40001dc4;\nlmacInit = 0x40001dc8;\nmac_tx_set_txop_q = 0x40001dcc;\nhal_init = 0x40001dd0;\nhal_mac_rx_set_policy = 0x40001dd4;\nhal_mac_set_bssid = 0x40001dd8;\nmac_rx_policy_init = 0x40001ddc;\nmac_txrx_init = 0x40001de0;\nmac_rxbuf_init = 0x40001de4;\nmac_last_rxbuf_init = 0x40001de8;\nhal_attenna_init = 0x40001dec;\nhal_timer_update_by_rtc = 0x40001df0;\nhal_coex_pti_init = 0x40001df4;\nlmac_stop_hw_txq = 0x40001df8;\nppDirectRecycleAmpdu = 0x40001dfc;\nesp_wifi_internal_set_rts = 0x40001e00;\nesp_wifi_internal_get_rts = 0x40001e04;\nppTxFragmentProc = 0x40001e08;\n\/*esf_buf_setup = 0x40001e0c;*\/\nhal_agreement_add_rx_ba = 0x40001e10;\nhal_agreement_del_rx_ba = 0x40001e14;\nhal_crypto_set_key_entry = 0x40001e18;\nhal_crypto_get_key_entry = 0x40001e1c;\nhal_crypto_clr_key_entry = 0x40001e20;\nconfig_get_wifi_task_stack_size = 0x40001e24;\npp_create_task = 0x40001e28;\nhal_set_sta_tsf_wakeup = 0x40001e2c;\nhal_set_rx_beacon_pti = 0x40001e30;\npm_start = 0x40001e34;\npm_stop = 0x40001e38;\nhal_disable_sta_tbtt = 0x40001e3c;\nppCalTxopDur = 0x40001e40;\nwDev_IndicateCtrlFrame = 0x40001e44;\nhal_enable_sta_tbtt = 0x40001e48;\nhal_set_sta_tbtt = 0x40001e4c;\npm_update_next_tbtt = 0x40001e50;\npm_set_sleep_type = 0x40001e54;\nwDev_Rxbuf_Init = 0x40001e58;\nwDev_Rxbuf_Deinit = 0x40001e5c;\nppCalTkipMic = 0x40001e60;\nwDev_SnifferRxData = 0x40001e64;\nhal_crypto_enable = 0x40001e68;\nhal_crypto_disable = 0x40001e6c;\nwDev_Insert_KeyEntry = 0x40001e70;\nwDev_remove_KeyEntry = 0x40001e74;\nrc_enable_trc = 0x40001e78;\nrc_set_per_conn_fix_rate = 0x40001e7c;\nwdev_csi_rx_process = 0x40001e80;\nwDev_SnifferRxAmpdu = 0x40001e84;\nhal_mac_tsf_reset = 0x40001e88;\ndbg_lmac_statis_dump = 0x40001e8c;\ndbg_lmac_rxtx_statis_dump = 0x40001e90;\ndbg_lmac_hw_statis_dump = 0x40001e94;\ndbg_lmac_diag_statis_dump = 0x40001e98;\ndbg_lmac_ps_statis_dump = 0x40001e9c;\npp_timer_do_process = 0x40001ea0;\nrcUpdateAMPDUParam = 0x40001ea4;\nrcUpdatePhyMode = 0x40001ea8;\nrcGetHighestRateIdx = 0x40001eac;\npm_tx_null_data_done_process = 0x40001eb0;\npm_tx_data_process = 0x40001eb4;\npm_attach = 0x40001eb8;\npm_coex_schm_process = 0x40001ebc;\nppInitTxq = 0x40001ec0;\npp_attach = 0x40001ec4;\npp_deattach = 0x40001ec8;\npm_on_probe_resp_rx = 0x40001ecc;\nhal_set_sta_tsf = 0x40001ed0;\nic_update_sta_tsf = 0x40001ed4;\nic_tx_pkt = 0x40001ed8;\npm_send_probe_stop = 0x40001edc;\npm_send_probe_start = 0x40001ee0;\npm_on_coex_schm_process_restart = 0x40001ee4;\nhal_mac_set_rxq_policy = 0x40001ee8;\nhal_sniffer_enable = 0x40001eec;\nhal_sniffer_disable = 0x40001ef0;\nhal_sniffer_rx_set_promis = 0x40001ef4;\nhal_sniffer_rx_clr_statistics = 0x40001ef8;\nhal_sniffer_set_promis_misc_pkt = 0x40001efc;\ntsf_hal_set_tsf_enable = 0x40001f00;\ntsf_hal_set_tsf_disable = 0x40001f04;\ntsf_hal_is_tsf_enabled = 0x40001f08;\ntsf_hal_set_modem_wakeup_early_time = 0x40001f0c;\ntsf_hal_get_counter_value = 0x40001f10;\ntsf_hal_set_counter_value = 0x40001f14;\ntsf_hal_get_time = 0x40001f18;\ntsf_hal_set_time = 0x40001f1c;\ntsf_hal_set_tbtt_enable = 0x40001f20;\ntsf_hal_set_tbtt_disable = 0x40001f24;\ntsf_hal_set_tbtt_intr_enable = 0x40001f28;\ntsf_hal_set_tbtt_intr_disable = 0x40001f2c;\ntsf_hal_set_tbtt_soc_wakeup_enable = 0x40001f30;\ntsf_hal_set_tbtt_soc_wakeup_disable = 0x40001f34;\ntsf_hal_set_tbtt_start_time = 0x40001f38;\ntsf_hal_set_tbtt_early_time = 0x40001f3c;\ntsf_hal_set_tbtt_interval = 0x40001f40;\ntsf_hal_get_tbtt_interval = 0x40001f44;\ntsf_hal_set_timer_enable = 0x40001f48;\ntsf_hal_set_timer_disable = 0x40001f4c;\ntsf_hal_set_timer_target = 0x40001f50;\ntsf_hal_get_timer_target = 0x40001f54;\ntsf_hal_set_timer_intr_enable = 0x40001f58;\ntsf_hal_set_timer_intr_disable = 0x40001f5c;\ntsf_hal_set_timer_soc_wakeup_enable = 0x40001f60;\ntsf_hal_set_timer_soc_wakeup_disable = 0x40001f64;\npm_disconnected_wake = 0x40001f68;\npm_get_connectionless_status = 0x40001f6c;\npm_update_by_connectionless_status = 0x40001f70;\npm_connectionless_wake_interval_timeout_process = 0x40001f74;\npm_connectionless_wake_window_timeout_process = 0x40001f78;\n\/* Data (.data, .bss, .rodata) *\/\nour_instances_ptr = 0x3ff4fbbc;\npTxRx = 0x3fcdfdec;\nlmacConfMib_ptr = 0x3fcdfde8;\nour_wait_eb = 0x3fcdfde4;\nour_tx_eb = 0x3fcdfde0;\npp_wdev_funcs = 0x3fcdfddc;\ng_osi_funcs_p = 0x3fcdfdd8;\nwDevCtrl_ptr = 0x3fcdfdd4;\ng_wdev_last_desc_reset_ptr = 0x3ff4fbb8;\nwDevMacSleep_ptr = 0x3fcdfdd0;\ng_lmac_cnt_ptr = 0x3fcdfdcc;\nour_controls_ptr = 0x3ff4fbb4;\npp_sig_cnt_ptr = 0x3fcdfdc8;\ng_eb_list_desc_ptr = 0x3fcdfdc4;\ns_fragment_ptr = 0x3fcdfdc0;\nif_ctrl_ptr = 0x3fcdfdbc;\ng_intr_lock_mux = 0x3fcdfdb8;\ng_wifi_global_lock = 0x3fcdfdb4;\ns_wifi_queue = 0x3fcdfdb0;\npp_task_hdl = 0x3fcdfdac;\ns_pp_task_create_sem = 0x3fcdfda8;\ns_pp_task_del_sem = 0x3fcdfda4;\ng_wifi_menuconfig_ptr = 0x3fcdfda0;\nxphyQueue = 0x3fcdfd9c;\nap_no_lr_ptr = 0x3fcdfd98;\nrc11BSchedTbl_ptr = 0x3fcdfd94;\nrc11NSchedTbl_ptr = 0x3fcdfd90;\nrcLoRaSchedTbl_ptr = 0x3fcdfd8c;\nBasicOFDMSched_ptr = 0x3fcdfd88;\ntrc_ctl_ptr = 0x3fcdfd84;\ng_pm_cnt_ptr = 0x3fcdfd80;\ng_pm_ptr = 0x3fcdfd7c;\ng_pm_cfg_ptr = 0x3fcdfd78;\ng_esp_mesh_quick_funcs_ptr = 0x3fcdfd74;\ng_txop_queue_status_ptr = 0x3fcdfd70;\ng_mac_sleep_en_ptr = 0x3fcdfd6c;\ng_mesh_is_root_ptr = 0x3fcdfd68;\ng_mesh_topology_ptr = 0x3fcdfd64;\ng_mesh_init_ps_type_ptr = 0x3fcdfd60;\ng_mesh_is_started_ptr = 0x3fcdfd5c;\ng_config_func = 0x3fcdfd58;\ng_net80211_tx_func = 0x3fcdfd54;\ng_timer_func = 0x3fcdfd50;\ns_michael_mic_failure_cb = 0x3fcdfd4c;\nwifi_sta_rx_probe_req = 0x3fcdfd48;\ng_tx_done_cb_func = 0x3fcdfd44;\ng_per_conn_trc = 0x3fcdfd28;\ns_encap_amsdu_func = 0x3fcdfd24;\nbars = 0x3fcdfc84;\neb_txdesc_space = 0x3fcdfbf4;\neb_space = 0x3fcdfb54;\ng_pd_mac_in_light_sleep = 0x3fcdfb50;\ns_fix_rate_mask = 0x3fcdfb4c;\ns_fix_rate = 0x3fcdfb44;\ng_wdev_csi_rx = 0x3fcdfb40;\ng_wdev_csi_rx_ctx = 0x3fcdfb3c;\nBcnSendTick = 0x3fcdfb38;\ng_pp_timer_info_ptr = 0x3fcdfb34;\nrcP2P11NSchedTbl_ptr = 0x3fcdfb30;\nrcP2P11GSchedTbl_ptr = 0x3fcdfb2c;\nrc11GSchedTbl_ptr = 0x3fcdfb28;\n\n\n\/***************************************\n Group rom_net80211\n ***************************************\/\n\n\/* Functions *\/\nesp_net80211_rom_version_get = 0x40001f7c;\nampdu_dispatch = 0x40001f80;\nampdu_dispatch_all = 0x40001f84;\nampdu_dispatch_as_many_as_possible = 0x40001f88;\nampdu_dispatch_movement = 0x40001f8c;\nampdu_dispatch_upto = 0x40001f90;\nchm_is_at_home_channel = 0x40001f94;\ncnx_node_is_existing = 0x40001f98;\ncnx_node_search = 0x40001f9c;\nic_ebuf_recycle_rx = 0x40001fa0;\nic_ebuf_recycle_tx = 0x40001fa4;\nic_reset_rx_ba = 0x40001fa8;\nieee80211_align_eb = 0x40001fac;\nieee80211_ampdu_reorder = 0x40001fb0;\nieee80211_ampdu_start_age_timer = 0x40001fb4;\nieee80211_encap_esfbuf = 0x40001fb8;\nieee80211_is_tx_allowed = 0x40001fbc;\nieee80211_output_pending_eb = 0x40001fc0;\nieee80211_output_process = 0x40001fc4;\nieee80211_set_tx_desc = 0x40001fc8;\nsta_input = 0x40001fcc;\nwifi_get_macaddr = 0x40001fd0;\nwifi_rf_phy_disable = 0x40001fd4;\nwifi_rf_phy_enable = 0x40001fd8;\nic_ebuf_alloc = 0x40001fdc;\nieee80211_classify = 0x40001fe0;\nieee80211_copy_eb_header = 0x40001fe4;\nieee80211_recycle_cache_eb = 0x40001fe8;\nieee80211_search_node = 0x40001fec;\nroundup2 = 0x40001ff0;\nieee80211_crypto_encap = 0x40001ff4;\nieee80211_crypto_decap = 0x40001ff8;\nieee80211_decap = 0x40001ffc;\nieee80211_set_tx_pti = 0x40002000;\nwifi_is_started = 0x40002004;\nieee80211_gettid = 0x40002008;\nieee80211_ccmp_decrypt = 0x4000200c;\nieee80211_ccmp_encrypt = 0x40002010;\nccmp_encap = 0x40002014;\nccmp_decap = 0x40002018;\ntkip_encap = 0x4000201c;\ntkip_decap = 0x40002020;\nwep_encap = 0x40002024;\nwep_decap = 0x40002028;\ndbg_hmac_rxtx_statis_dump = 0x4000202c;\ndbg_hmac_statis_dump = 0x40002030;\nieee80211_send_action_vendor_spec = 0x40002034;\nieee80211_deauth_construct = 0x40002040;\nieee80211_disassoc_construct = 0x40002044;\nieee80211_vnd_lora_ie_size = 0x40002048;\nieee80211_vnd_ie_size = 0x4000204c;\nieee80211_add_ssid = 0x40002050;\nieee80211_add_rates = 0x40002054;\nieee80211_add_xrates = 0x40002058;\nieee80211_is_ht_cipher = 0x4000205c;\nieee80211_assoc_resp_construct = 0x40002064;\nieee80211_setup_lr_rates = 0x40002068;\nieee80211_ht_node_init = 0x4000206c;\nieee80211_is_support_rate = 0x40002070;\nieee80211_setup_rates = 0x40002074;\nieee80211_is_lr_only = 0x40002078;\nieee80211_setup_phy_mode = 0x4000207c;\nieee80211_sta_is_connected = 0x40002080;\ncurrent_task_is_wifi_task = 0x40002084;\nwifi_get_init_state = 0x40002088;\nieee80211_timer_process = 0x4000208c;\ncnx_coexist_timeout = 0x40002090;\n\/* sta_recv_mgmt = 0x40002094;*\/\nieee80211_send_setup = 0x40002098;\nieee80211_send_probereq = 0x4000209c;\nsta_auth_shared = 0x400020a4;\ncnx_coexist_timeout_process = 0x400020ac;\nieee80211_alloc_challenge = 0x400020b0;\ncnx_assoc_timeout = 0x400020b4;\nieee80211_vnd_ie_set = 0x400020b8;\nieee80211_vnd_lora_ie_set = 0x400020bc;\nieee80211_add_wme_param = 0x400020c0;\nieee80211_add_dsparams = 0x400020c4;\nieee80211_add_csa = 0x400020c8;\nieee80211_add_extcap = 0x400020cc;\nieee80211_regdomain_get_country = 0x400020d0;\nieee80211_add_countryie = 0x400020d4;\nieee80211_amsdu_adjust_head = 0x400020dc;\nieee80211_amsdu_adjust_last_length = 0x400020e0;\nieee80211_amsdu_send_check = 0x400020e4;\nieee80211_amsdu_encap_check = 0x400020e8;\nieee80211_amsdu_length_check = 0x400020ec;\nieee80211_encap_amsdu = 0x400020f0;\nieee80211_output_raw_process = 0x400020f4;\nesp_wifi_80211_tx = 0x400020f8;\nieee80211_raw_frame_sanity_check = 0x400020fc;\nieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;\nieee80211_crypto_aes_128_cmac_decrypt = 0x40002104;\nieee80211_alloc_tx_buf = 0x40002108;\nieee80211_output_do = 0x4000210c;\nieee80211_send_nulldata = 0x40002110;\nieee80211_setup_robust_mgmtframe = 0x40002114;\nieee80211_mgmt_output = 0x40002118;\nieee80211_encap_null_data = 0x4000211c;\nieee80211_send_deauth = 0x40002120;\nieee80211_alloc_deauth = 0x40002124;\nieee80211_send_proberesp = 0x40002128;\nieee80211_tx_mgt_cb = 0x4000212c;\nieee80211_getcapinfo = 0x40002130;\nsta_rx_csa = 0x40002134;\nsta_recv_sa_query_resp = 0x40002144;\nieee80211_set_max_rate = 0x4000214c;\nic_set_sta = 0x40002150;\nieee80211_parse_wpa = 0x40002158;\nieee80211_add_assoc_req_ies = 0x40002160;\nieee80211_add_probe_req_ies = 0x40002164;\n\/* Data (.data, .bss, .rodata) *\/\nnet80211_funcs = 0x3fcdfb24;\ng_scan = 0x3fcdfb20;\ng_chm = 0x3fcdfb1c;\ng_ic_ptr = 0x3fcdfb18;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_tx_cacheq_ptr = 0x3fcdfb14;\ns_netstack_free = 0x3fcdfb10;\nmesh_rxcb = 0x3fcdfb0c;\nsta_rxcb = 0x3fcdfb08;\nccmp_ptr = 0x3fcdfb04;\ns_wifi_nvs_ptr = 0x3fcdfb00;\ntkip_ptr = 0x3fcdfafc;\nwep_ptr = 0x3fcdfaf8;\ng_hmac_cnt_ptr = 0x3fcdfaf4;\ng_misc_nvs = 0x3fcdfaf0;\ns_wifi_init_state = 0x3fcdfac0;\ns_wifi_task_hdl = 0x3fcdfaec;\nin_rssi_adjust = 0x3fcdfae8;\nrssi_saved = 0x3fcdfae0;\nrssi_index = 0x3fcdfadc;\ns_sa_query_retries = 0x3fcdfad8;\ns_sa_query_success = 0x3fcdfad5;\ng_sta_connected_flag = 0x3fcdfad4;\nwpa_crypto_funcs_ptr = 0x3fcdfad0;\ns_netstack_ref = 0x3fcdfacc;\nsta_csa_timer_ptr = 0x3fcdfac8;\ns_trans_id = 0x3fcdfac4;\n\n\n\/***************************************\n Group rom_coexist\n ***************************************\/\n\n\/* Functions *\/\nesp_coex_rom_version_get = 0x40002168;\ncoex_bt_release = 0x4000216c;\ncoex_bt_request = 0x40002170;\ncoex_core_ble_conn_dyn_prio_get = 0x40002174;\ncoex_core_event_duration_get = 0x40002178;\ncoex_core_pti_get = 0x4000217c;\ncoex_core_release = 0x40002180;\ncoex_core_request = 0x40002184;\ncoex_core_status_get = 0x40002188;\ncoex_core_timer_idx_get = 0x4000218c;\ncoex_event_duration_get = 0x40002190;\ncoex_hw_timer_disable = 0x40002194;\ncoex_hw_timer_enable = 0x40002198;\ncoex_hw_timer_set = 0x4000219c;\ncoex_schm_interval_set = 0x400021a0;\ncoex_schm_lock = 0x400021a4;\ncoex_schm_unlock = 0x400021a8;\ncoex_status_get = 0x400021ac;\ncoex_wifi_release = 0x400021b0;\nesp_coex_ble_conn_dynamic_prio_get = 0x400021b4;\ncoex_hw_timer_tick_get = 0x400021b8;\n\/* Data (.data, .bss, .rodata) *\/\ncoex_env_ptr = 0x3fcdfabc;\ncoex_pti_tab_ptr = 0x3fcdfab8;\ncoex_schm_env_ptr = 0x3fcdfab4;\ncoexist_funcs = 0x3fcdfab0;\ng_coa_funcs_p = 0x3fcdfaac;\ng_coex_param_ptr = 0x3fcdfaa8;\n\n\n\/***************************************\n Group rom_phy\n ***************************************\/\n\n\/* Functions *\/\nphy_param_addr = 0x400021bc;\nphy_get_romfuncs = 0x400021c0;\nchip729_phyrom_version = 0x400021c4;\nchip729_phyrom_version_num = 0x400021c8;\nrom_get_rc_dout = 0x400021cc;\nrc_cal = 0x400021d0;\nphy_analog_delay_cal = 0x400021d4;\nphy_rx_rifs_en = 0x400021d8;\nphy_current_level_set = 0x400021dc;\nphy_bbpll_en_usb = 0x400021e0;\nphy_bt_power_track = 0x400021e4;\nphy_xpd_tsens = 0x400021e8;\nbb_wdt_rst_enable = 0x400021ec;\nbb_wdt_int_enable = 0x400021f0;\nbb_wdt_timeout_clear = 0x400021f4;\nbb_wdt_get_status = 0x400021f8;\nrom_enter_critical_phy = 0x400021fc;\nrom_exit_critical_phy = 0x40002200;\nrom_bb_bss_cbw40 = 0x40002204;\nrom_set_chan_reg = 0x40002208;\nabs_temp = 0x4000220c;\nset_chan_cal_interp = 0x40002210;\nloopback_mode_en = 0x40002214;\nget_data_sat = 0x40002218;\nphy_byte_to_word = 0x4000221c;\nphy_get_rx_freq = 0x40002220;\ni2c_master_reset = 0x40002224;\nchan14_mic_enable = 0x40002228;\nchan14_mic_cfg = 0x4000222c;\nset_adc_rand = 0x40002230;\nphy_set_most_tpw = 0x40002234;\nphy_get_most_tpw = 0x40002238;\nesp_tx_state_out = 0x4000223c;\nphy_get_adc_rand = 0x40002240;\nphy_internal_delay = 0x40002244;\nphy_ftm_comp = 0x40002248;\nphy_11p_set = 0x4000224c;\nphy_freq_mem_backup = 0x40002250;\nant_dft_cfg = 0x40002254;\nant_wifitx_cfg = 0x40002258;\nant_wifirx_cfg = 0x4000225c;\nant_bttx_cfg = 0x40002260;\nant_btrx_cfg = 0x40002264;\nphy_chan_dump_cfg = 0x40002268;\nphy_enable_low_rate = 0x4000226c;\nphy_disable_low_rate = 0x40002270;\nphy_dig_reg_backup = 0x40002274;\nphy_chan_filt_set = 0x40002278;\nphy_rx11blr_cfg = 0x4000227c;\nset_cca = 0x40002280;\nset_rx_sense = 0x40002284;\nrx_gain_force = 0x40002288;\nrom_phy_en_hw_set_freq = 0x4000228c;\nrom_phy_dis_hw_set_freq = 0x40002290;\nwr_rf_freq_mem = 0x40002294;\nfreq_i2c_write_set = 0x40002298;\nwrite_pll_cap_mem = 0x4000229c;\npll_dac_mem_update = 0x400022a0;\npll_cap_mem_update = 0x400022a4;\nget_rf_freq_cap = 0x400022a8;\nget_rf_freq_init = 0x400022ac;\nfreq_get_i2c_data = 0x400022b0;\nfreq_i2c_data_write = 0x400022b4;\nset_chan_freq_hw_init = 0x400022b8;\nset_chan_freq_sw_start = 0x400022bc;\nrom_get_i2c_read_mask = 0x400022c0;\nrom_get_i2c_mst0_mask = 0x400022c4;\nrom_get_i2c_hostid = 0x400022c8;\nrom_chip_i2c_readReg_org = 0x400022cc;\nrom_chip_i2c_readReg = 0x400022d0;\nrom_i2c_paral_set_mst0 = 0x400022d4;\nrom_i2c_paral_set_read = 0x400022d8;\nrom_i2c_paral_read = 0x400022dc;\nrom_i2c_paral_write = 0x400022e0;\nrom_i2c_paral_write_num = 0x400022e4;\nrom_i2c_paral_write_mask = 0x400022e8;\nrom_i2c_readReg = 0x400022ec;\nrom_chip_i2c_writeReg = 0x400022f0;\nrom_i2c_writeReg = 0x400022f4;\nrom_i2c_readReg_Mask = 0x400022f8;\nrom_i2c_writeReg_Mask = 0x400022fc;\nrom_set_txcap_reg = 0x40002300;\ni2c_sar2_init_code = 0x40002304;\nphy_i2c_init1 = 0x40002308;\nphy_i2c_init2 = 0x4000230c;\nphy_get_i2c_data = 0x40002310;\nbias_reg_set = 0x40002314;\ni2c_rc_cal_set = 0x40002318;\ni2c_bbpll_set = 0x4000231c;\nrom_phy_xpd_rf = 0x40002320;\nphy_wakeup_init_rom = 0x40002324;\nregister_chipv7_phy_init_param = 0x40002328;\nphy_reg_init = 0x4000232c;\nphy_close_rf_rom = 0x40002330;\nrom_pbus_force_mode = 0x40002334;\nrom_pbus_rd_addr = 0x40002338;\nrom_pbus_rd_shift = 0x4000233c;\nrom_pbus_force_test = 0x40002340;\nrom_pbus_rd = 0x40002344;\nrom_pbus_debugmode = 0x40002348;\nrom_pbus_workmode = 0x4000234c;\nrom_pbus_set_rxgain = 0x40002350;\nrom_pbus_xpd_rx_off = 0x40002354;\nrom_pbus_xpd_rx_on = 0x40002358;\nrom_pbus_xpd_tx_off = 0x4000235c;\nrom_pbus_xpd_tx_on = 0x40002360;\nrom_pbus_set_dco = 0x40002364;\nrom_set_loopback_gain = 0x40002368;\nrom_txcal_debuge_mode = 0x4000236c;\nrom_txcal_work_mode = 0x40002370;\nset_pbus_mem = 0x40002374;\nrom_pwdet_sar2_init = 0x40002378;\nrom_en_pwdet = 0x4000237c;\nrom_get_sar_sig_ref = 0x40002380;\nrom_pwdet_tone_start = 0x40002384;\nrom_get_tone_sar_dout = 0x40002388;\nrom_get_fm_sar_dout = 0x4000238c;\nrom_txtone_linear_pwr = 0x40002390;\nrom_get_power_db = 0x40002394;\nrom_meas_tone_pwr_db = 0x40002398;\nrom_pkdet_vol_start = 0x4000239c;\nrom_read_sar_dout = 0x400023a0;\nrom_read_sar2_code = 0x400023a4;\nrom_get_sar2_vol = 0x400023a8;\nrom_get_pll_vol = 0x400023ac;\nrom_tx_pwctrl_bg_init = 0x400023b0;\nrom_phy_pwdet_always_en = 0x400023b4;\nrom_phy_pwdet_onetime_en = 0x400023b8;\nlinear_to_db = 0x400023bc;\nrom_disable_agc = 0x400023c0;\nrom_enable_agc = 0x400023c4;\nrom_disable_wifi_agc = 0x400023c8;\nrom_enable_wifi_agc = 0x400023cc;\nrom_write_gain_mem = 0x400023d0;\nrom_bb_bss_cbw40_dig = 0x400023d4;\nrom_cbw2040_cfg = 0x400023d8;\nrom_mac_tx_chan_offset = 0x400023dc;\nrom_tx_paon_set = 0x400023e0;\nrom_i2cmst_reg_init = 0x400023e4;\nrom_bt_gain_offset = 0x400023e8;\nrom_fe_reg_init = 0x400023ec;\nrom_mac_enable_bb = 0x400023f0;\nrom_bb_wdg_cfg = 0x400023f4;\nrom_fe_txrx_reset = 0x400023f8;\nrom_set_rx_comp = 0x400023fc;\nrom_write_chan_freq = 0x40002400;\nrom_agc_reg_init = 0x40002404;\nrom_bb_reg_init = 0x40002408;\nrom_write_txrate_power_offset = 0x4000240c;\nrom_open_i2c_xpd = 0x40002410;\nrom_txiq_set_reg = 0x40002414;\nrom_rxiq_set_reg = 0x40002418;\nrom_phy_bbpll_cal = 0x4000241c;\nphy_disable_cca = 0x40002420;\nphy_enable_cca = 0x40002424;\nforce_txon = 0x40002428;\nset_txclk_en = 0x4000242c;\nset_rxclk_en = 0x40002430;\nstart_tx_tone_step = 0x40002434;\nstop_tx_tone = 0x40002438;\nbb_wdg_test_en = 0x4000243c;\nnoise_floor_auto_set = 0x40002440;\nread_hw_noisefloor = 0x40002444;\niq_corr_enable = 0x40002448;\nbt_tx_dig_gain = 0x4000244c;\nwifi_tx_dig_reg = 0x40002450;\nwifi_agc_sat_gain = 0x40002454;\nphy_ant_init = 0x40002458;\nphy_set_bbfreq_init = 0x4000245c;\nwifi_fbw_sel = 0x40002460;\nphy_rx_sense_set = 0x40002464;\ntx_state_set = 0x40002468;\nphy_close_pa = 0x4000246c;\nbt_filter_reg = 0x40002470;\nphy_freq_correct = 0x40002474;\nset_pbus_reg = 0x40002478;\nwifi_rifs_mode_en = 0x4000247c;\nrfagc_disable = 0x40002480;\nrom_restart_cal = 0x40002484;\nrom_write_rfpll_sdm = 0x40002488;\nrom_wait_rfpll_cal_end = 0x4000248c;\nrom_rfpll_set_freq = 0x40002490;\nrom_rfpll_cap_init_cal = 0x40002494;\nrom_set_rfpll_freq = 0x40002498;\nrom_write_pll_cap = 0x4000249c;\nrom_read_pll_cap = 0x400024a0;\nmhz2ieee = 0x400024a4;\nchan_to_freq = 0x400024a8;\nset_rf_freq_offset = 0x400024ac;\nset_channel_rfpll_freq = 0x400024b0;\nrfpll_cap_correct = 0x400024b4;\nphy_set_freq = 0x400024b8;\ncorrect_rfpll_offset = 0x400024bc;\npll_vol_cal = 0x400024c0;\nchip_v7_set_chan_misc = 0x400024c4;\nchip_v7_set_chan = 0x400024c8;\nchip_v7_set_chan_offset = 0x400024cc;\nchip_v7_set_chan_ana = 0x400024d0;\nset_chanfreq = 0x400024d4;\nrom_rxiq_cover_mg_mp = 0x400024d8;\nrom_rfcal_rxiq = 0x400024dc;\nrom_get_rfcal_rxiq_data = 0x400024e0;\nrom_pbus_rx_dco_cal = 0x400024e4;\nrom_rxdc_est_min = 0x400024e8;\nrom_pbus_rx_dco_cal_1step = 0x400024ec;\nrom_set_lb_txiq = 0x400024f0;\nrom_set_rx_gain_cal_iq = 0x400024f4;\nrom_set_rx_gain_cal_dc = 0x400024f8;\niq_est_enable = 0x400024fc;\niq_est_disable = 0x40002500;\ndc_iq_est = 0x40002504;\nset_cal_rxdc = 0x40002508;\nrxiq_get_mis = 0x4000250c;\nspur_reg_write_one_tone = 0x40002510;\nspur_cal = 0x40002514;\nspur_coef_cfg = 0x40002518;\ngen_rx_gain_table = 0x4000251c;\nwr_rx_gain_mem = 0x40002520;\nset_rx_gain_param = 0x40002524;\nset_rx_gain_table = 0x40002528;\nrom_tester_wifi_cali = 0x4000252c;\nesp_recover_efuse_data = 0x40002530;\nbt_track_pll_cap = 0x40002534;\nrfpll_cap_track = 0x40002538;\nphy_param_track = 0x4000253c;\ntxpwr_correct = 0x40002540;\ntxpwr_cal_track = 0x40002544;\n\/* tx_pwctrl_background = 0x40002548;*\/\nbt_track_tx_power = 0x4000254c;\nwifi_track_tx_power = 0x40002550;\nrom_code_to_temp = 0x40002554;\nrom_tsens_index_to_dac = 0x40002558;\nrom_tsens_index_to_offset = 0x4000255c;\nrom_tsens_dac_cal = 0x40002560;\nrom_tsens_code_read = 0x40002564;\nrom_tsens_temp_read = 0x40002568;\nrom_temp_to_power = 0x4000256c;\ntsens_read_init = 0x40002570;\nget_temp_init = 0x40002574;\nrom_txiq_cover = 0x40002578;\nrom_rfcal_txiq = 0x4000257c;\nrom_get_power_atten = 0x40002580;\nrom_tx_pwctrl_init_cal = 0x40002584;\nbt_txdc_cal = 0x40002588;\nbt_txiq_cal = 0x4000258c;\ntxiq_cal_init = 0x40002590;\ntxdc_cal_init = 0x40002594;\ntxdc_cal_v70 = 0x40002598;\ntxiq_get_mis_pwr = 0x4000259c;\npwdet_ref_code = 0x400025a0;\npwdet_code_cal = 0x400025a4;\nrfcal_txcap = 0x400025a8;\ntx_cap_init = 0x400025ac;\nrfcal_pwrctrl = 0x400025b0;\ntx_pwctrl_init = 0x400025b4;\nbt_tx_pwctrl_init = 0x400025b8;\nbt_txpwr_freq = 0x400025bc;\nrom_txbbgain_to_index = 0x400025c0;\nrom_index_to_txbbgain = 0x400025c4;\nrom_bt_index_to_bb = 0x400025c8;\nrom_bt_bb_to_index = 0x400025cc;\nrom_bt_get_tx_gain = 0x400025d0;\nrom_get_tx_gain_value = 0x400025d4;\nrom_wifi_get_tx_gain = 0x400025d8;\nrom_set_tx_gain_mem = 0x400025dc;\nrom_get_rate_fcc_index = 0x400025e0;\nrom_get_chan_target_power = 0x400025e4;\nrom_wifi_tx_dig_gain = 0x400025e8;\nrom_wifi_set_tx_gain = 0x400025ec;\nrom_bt_set_tx_gain = 0x400025f0;\nwifi_11g_rate_chg = 0x400025f4;\nbt_chan_pwr_interp = 0x400025f8;\nbt_tx_gain_init = 0x400025fc;\n\/* Data (.data, .bss, .rodata) *\/\nphy_param_rom = 0x3fcdfaa4;\n\n\n\/***************************************\n Group rom_btbb\n ***************************************\/\n\n\/* Functions *\/\nbt_agc_gain_offset = 0x40002600;\nbt_agc_gain_max = 0x40002604;\nbt_set_rx_comp = 0x40002608;\nbt_agc_gain_set = 0x4000260c;\nbt_agc_rssi_thresh = 0x40002610;\nbt_agc_target_set = 0x40002614;\nbt_agc_restart_set = 0x40002618;\nbt_agc_recorrect_set = 0x4000261c;\nbt_agc_detect_set = 0x40002620;\nbt_bb_rx_correlator_set = 0x40002624;\nbt_bb_rx_dpo_set = 0x40002628;\nbt_bb_rx_filter_sel = 0x4000262c;\nbt_bb_rx_set1 = 0x40002630;\nbt_bb_v2_rx_set = 0x40002634;\nbt_bb_v2_tx_set = 0x40002638;\nbt_bb_tx_cca_set = 0x4000263c;\nbt_bb_tx_cca_period = 0x40002640;\nbt_bb_tx_cca_fifo_reset = 0x40002644;\nbt_bb_tx_cca_fifo_empty = 0x40002648;\nbt_bb_tx_cca_fifo_full = 0x4000264c;\nbt_bb_tx_cca_fifo_count = 0x40002650;\nbt_bb_tx_cca_fifo_read = 0x40002654;\ncoex_pti_v2 = 0x40002658;\nbt_bb_set_le_tx_on_delay = 0x4000265c;\nbt_bb_set_corr_thresh_le = 0x40002660;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d4066dae834396ad9b98ca9e0f631297201ba7c4","subject":"aarch64: Rework linker script for better MMU support","message":"aarch64: Rework linker script for better MMU support\n\nIn acda9bf9cec8 new macros were introduced to support a virtual memory\nmap. Adjust these macros also for AArch64. This also fixes a problem\nwhen building Zephyr when CONFIG_KERNEL_VM_BASE is not the same as\nCONFIG_SRAM_BASE_ADDRESS\n\nSigned-off-by: Carlo Caione <ca4506c8c654a4ccf75802e86b5d162c1e96f065@baylibre.com>\n","repos":"Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,Vudentz\/zephyr,nashif\/zephyr,galak\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,galak\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr","old_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_file":"include\/arch\/arm\/aarch64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <devicetree.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    _image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        _image_text_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    _image_text_end = .;\n    _image_text_size = _image_text_end - _image_text_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n        _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n#include <linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        KEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <linker\/kobject-rom.ld>\n\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    _image_rodata_end = .;\n    _image_rodata_size = _image_rodata_end - _image_rodata_start;\n    _image_rom_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.got.plt)\n        *(.igot.plt)\n        *(.got)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n        __data_ram_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/kobject.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_LINK_IN(ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e51c2095cdfcc521929da76d21ed54e2d84b143a","subject":"linker: move scripts generated code at the beginning of .text","message":"linker: move scripts generated code at the beginning of .text\n\nWhen code relocation enabled, there will be serval regions holding\ntext. And then there will be function call between these .text\nregions, when distance between caller and callee is too far, linker\nwill automatically generate and insert veneer functions. And these\nveneer functions will be located right after the last instruction\nin the .text region by the linker. So these code will be put in the\nmemory reserved for priv_stacks text and kobject text if they don't\nconsume all the reserved memory. Or the veneer functions will be put\nbefore the reserved memory if there isn't code in the reserved\nmemory. And then in the user mode building process, there will be\ndifferent memory layout and it will cause usr mode not working.\nAnd moving the memory reserved for priv_stacks text and kobject text\nat the beginning of .text will avoid above problem. The detailed\nanalysis for this issue can be found on Github issue #17038.\n\nFixes: #17038.\n\nSigned-off-by: Wentong Wu <a92ffab6ab5ff780cf36418e13a69a97399df0f5@intel.com>\n","repos":"Vudentz\/zephyr,nashif\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr","old_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_file":"include\/arch\/arm\/cortex_m\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\n#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER\n\tKEEP(*(.boot_hdr.conf))\n\t. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;\n\tKEEP(*(.boot_hdr.ivt))\n\tKEEP(*(.boot_hdr.data))\n#ifdef CONFIG_DEVICE_CONFIGURATION_DATA\n\tKEEP(*(.boot_hdr.dcd_data))\n#endif\n#endif\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#elif defined(CONFIG_CPU_HAS_NRF_IDAU)\n\t\/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. *\/\n\t#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NSC_ALIGN_END . = ALIGN(0x8000)\n#else\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\tASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))\n\t\t\t == (0x8000 - (__sg_start % 0x8000))\n\t\t&& (0x8000 - (__sg_start % 0x8000)) >= 32\n\t\t&& (0x8000 - (__sg_start % 0x8000)) <= 4096,\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-M platforms.\n *\/\n\n#define _LINKER\n#define _ASMLANGUAGE\n\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <generated_dts_board.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if defined(CONFIG_XIP)\n  #define _DATA_IN_ROM __data_rom_start\n#else\n  #define _DATA_IN_ROM\n#endif\n\n#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)\n  #define SKIP_TO_KINETIS_FLASH_CONFIG\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n#define ROM_ADDR RAM_ADDR\n#else\n#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#ifdef CONFIG_TI_CCFG_PRESENT\n  #define CCFG_SIZE 88\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \\\n\t\t    CCFG_SIZE)\n  #define CCFG_ADDR (ROM_ADDR + ROM_SIZE)\n#else\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n#endif\n\n#if defined(CONFIG_XIP)\n\t#if defined(CONFIG_IS_BOOTLOADER)\n\t\t#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \\\n\t\t\t(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))\n\t#else\n\t\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n\t\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\t#endif\n#else\n\t#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)\n\t#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n#endif\n\n\/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE\n * to make linker section alignment comply with MPU granularity.\n *\/\n#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)\n_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n#else\n\/* If building without MPU support, use default 4-byte alignment. *\/\n_region_min_align = 4;\n#endif\n\n#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align); \\\n    . = ALIGN( 1 << LOG2CEIL(region_size))\n#else\n#define MPU_ALIGN(region_size) \\\n    . = ALIGN(_region_min_align)\n#endif\n\nMEMORY\n    {\n    FLASH                 (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n#ifdef CONFIG_TI_CCFG_PRESENT\n    FLASH_CCFG            (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE\n#endif\n#ifdef DT_CCM_BASE_ADDRESS\n    CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K\n#endif\n    SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n#ifdef CONFIG_BT_STM32_IPM\n    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE\n    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE\n#endif\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n\t{\n\t*(.plt)\n\t}\n\n    \/DISCARD\/ :\n\t{\n\t*(.iplt)\n\t}\n\n    GROUP_START(ROMABLE_REGION)\n\n\t_image_rom_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n#ifdef CONFIG_CC3220SF_DEBUG\n\t\/* Add CC3220SF flash header to disable flash verification *\/\n\t. = 0x0;\n\tKEEP(*(.dbghdr))\n\tKEEP(*(\".dbghdr.*\"))\n#endif\n\n#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER\n\tKEEP(*(.boot_hdr.conf))\n\t. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;\n\tKEEP(*(.boot_hdr.ivt))\n\tKEEP(*(.boot_hdr.data))\n#ifdef CONFIG_DEVICE_CONFIGURATION_DATA\n\tKEEP(*(.boot_hdr.dcd_data))\n#endif\n#endif\n\n\t. = CONFIG_TEXT_SECTION_OFFSET;\n\n#if defined(CONFIG_SW_VECTOR_RELAY)\n\tKEEP(*(.vector_relay_table))\n\tKEEP(*(\".vector_relay_table.*\"))\n\tKEEP(*(.vector_relay_handler))\n\tKEEP(*(\".vector_relay_handler.*\"))\n#endif\n\n\t_vector_start = .;\n\tKEEP(*(.exc_vector_table))\n\tKEEP(*(\".exc_vector_table.*\"))\n\n\tKEEP(*(IRQ_VECTOR_TABLE))\n\n\tKEEP(*(.vectors))\n\n\tKEEP(*(.openocd_dbg))\n\tKEEP(*(\".openocd_dbg.*\"))\n\n\t\/* Kinetis has to write 16 bytes at 0x400 *\/\n\tSKIP_TO_KINETIS_FLASH_CONFIG\n\tKEEP(*(.kinetis_flash_config))\n\tKEEP(*(\".kinetis_flash_config.*\"))\n\n\t_vector_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n\n#include <linker_relocate.ld>\n\n#endif \/* CONFIG_CODE_DATA_RELOCATION *\/\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)\n\t{\n\t_image_text_start = .;\n\t*(.text)\n\t*(\".text.*\")\n\t*(.gnu.linkonce.t.*)\n\n\t\/*\n\t * These are here according to 'arm-zephyr-elf-ld --verbose',\n\t * after .gnu.linkonce.t.*\n\t *\/\n\t*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <linker\/priv_stacks-text.ld>\n#include <linker\/kobject-text.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_text_end = .;\n\n#if defined (CONFIG_CPLUSPLUS)\n\tSECTION_PROLOGUE(.ARM.extab,,)\n\t{\n\t\/*\n\t * .ARM.extab section containing exception unwinding information.\n\t *\/\n\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n#endif\n\n\tSECTION_PROLOGUE(.ARM.exidx,,)\n\t{\n\t\/*\n\t * This section, related to stack and exception unwinding, is placed\n\t * explicitly to prevent it from being shared between multiple regions.\n\t * It  must be defined for gcc to support 64-bit math and avoid\n\t * section overlap.\n\t *\/\n\t__exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n\t*(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n\t__exidx_end = .;\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t*(.rodata)\n\t*(\".rodata.*\")\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n#ifdef CONFIG_SOC_RODATA_LD\n#include <soc-rodata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RODATA_LD\n\/* Located in project source directory *\/\n#include <custom-rodata.ld>\n#endif\n\n#include <linker\/priv_stacks-rom.ld>\n#include <linker\/kobject-rom.ld>\n\n\t\/*\n\t * For XIP images, in order to avoid the situation when __data_rom_start\n\t * is 32-bit aligned, but the actual data is placed right after rodata\n\t * section, which may not end exactly at 32-bit border, pad rodata\n\t * section, so __data_rom_start points at data and it is 32-bit aligned.\n\t *\n\t * On non-XIP images this may enlarge image size up to 3 bytes. This\n\t * generally is not an issue, since modern ROM and FLASH memory is\n\t * usually 4k aligned.\n\t *\/\n\t. = ALIGN(4);\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n\t_image_rodata_end = .;\n\tMPU_ALIGN(_image_rodata_end -_image_rom_start);\n\t_image_rom_end = .;\n\n    GROUP_END(ROMABLE_REGION)\n\n\/* Some TI SoCs have a special configuration footer, at the end of flash. *\/\n#ifdef CONFIG_TI_CCFG_PRESENT\n    SECTION_PROLOGUE(.ti_ccfg,,)\n    {\n    KEEP(*(TI_CCFG))\n    } > FLASH_CCFG\n#endif\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ : {\n\t*(.got.plt)\n\t*(.igot.plt)\n\t*(.got)\n\t*(.igot)\n\t}\n\n    GROUP_START(RAMABLE_REGION)\n\n\t. = RAM_ADDR;\n\t\/* Align the start of image SRAM with the\n\t * minimum granularity required by MPU.\n\t *\/\n\t. = ALIGN(_region_min_align);\n\t_image_ram_start = .;\n\n#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)\n    \/* Must be first in ramable region *\/\n\tSECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)\n\t{\n        _ram_vector_start = .;\n        . += _vector_end - _vector_start;\n        _ram_vector_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN MPU_ALIGN\n\n#include <app_smem.ld>\n\n\t_app_smem_size = _app_smem_end - _app_smem_start;\n\t_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n\t__bss_start = .;\n\t__kernel_ram_start = .;\n\n\t*(.bss)\n\t*(\".bss.*\")\n\t*(COMMON)\n\t*(\".kernel_bss.*\")\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_bss_relocate.ld>\n#endif\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n\t\t *\/\n\t__bss_end = ALIGN(4);\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n        {\n        \/*\n         * This section is used for non-initialized objects that\n         * will not be cleared during the boot process.\n         *\/\n        *(.noinit)\n        *(\".noinit.*\")\n\t*(\".kernel_noinit.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n#ifdef CONFIG_SOC_NOINIT_LD\n#include <soc-noinit.ld>\n#endif\n\n        } GROUP_LINK_IN(RAMABLE_REGION)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t__data_ram_start = .;\n\t*(.data)\n\t*(\".data.*\")\n\t*(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n#ifdef CONFIG_SOC_RWDATA_LD\n#include <soc-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CUSTOM_RWDATA_LD\n\/* Located in project source directory *\/\n#include <custom-rwdata.ld>\n#endif\n\n#ifdef CONFIG_CODE_DATA_RELOCATION\n#include <linker_sram_data_relocate.ld>\n#endif\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <linker\/common-ram.ld>\n#include <linker\/priv_stacks.ld>\n#include <linker\/kobject.ld>\n\n#include <linker\/priv_stacks-noinit.ld>\n\n    __data_ram_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n\t{\n\tKEEP(*(.ARM.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n\n#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)\n#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0\n\t#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)\n#elif defined(CONFIG_CPU_HAS_NRF_IDAU)\n\t\/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. *\/\n\t#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))\n#else\n\t#define NSC_ALIGN . = ALIGN(4)\n#endif\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\t#define NSC_ALIGN_END . = ALIGN(0x8000)\n#else\n\t#define NSC_ALIGN_END . = ALIGN(4)\n#endif\n\nSECTION_PROLOGUE(.gnu.sgstubs,,)\n{\n\tNSC_ALIGN;\n\t__sg_start = .;\n\t\/* No input section necessary, since the Secure Entry Veneers are\n\t   automatically placed after the .gnu.sgstubs output section. *\/\n} GROUP_LINK_IN(ROMABLE_REGION)\n__sg_end = .;\n__sg_size = __sg_end - __sg_start;\nNSC_ALIGN_END;\n__nsc_size = . - __sg_start;\n\n#ifdef CONFIG_CPU_HAS_NRF_IDAU\n\tASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))\n\t\t\t == (0x8000 - (__sg_start % 0x8000))\n\t\t&& (0x8000 - (__sg_start % 0x8000)) >= 32\n\t\t&& (0x8000 - (__sg_start % 0x8000)) <= 4096,\n\t\t\"The Non-Secure Callable region size must be a power of 2 \\\nbetween 32 and 4096 bytes.\")\n#endif\n#endif \/* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS *\/\n\n\/* Must be last in romable region *\/\nSECTION_PROLOGUE(.last_section,(NOLOAD),)\n{\n} GROUP_LINK_IN(ROMABLE_REGION)\n\n\/* To provide the image size as a const expression,\n * calculate this value here. *\/\n_flash_used = LOADADDR(.last_section) - _image_rom_start;\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"561e22588315c30f8aec9ad7b0d735dd567aad2d","subject":"Start RAM at 0x20000000 (was: 0x20000188).","message":"Start RAM at 0x20000000 (was: 0x20000188).\n","repos":"mlaz\/mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,IMGJulian\/incubator-mynewt-core,mlaz\/mynewt-core,wes3\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,IMGJulian\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core","old_file":"hw\/bsp\/olimex_stm32-e407_devboard-boot\/olimex_stm32-e407_devboard-boot.ld","new_file":"hw\/bsp\/olimex_stm32-e407_devboard-boot\/olimex_stm32-e407_devboard-boot.ld","new_contents":"\/* Linker script for STM32F407 *\/\n\n\/* XXX: Currently only runs from RAM *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K\n  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > RAM\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > RAM\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > RAM\n\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data)\n\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","old_contents":"\/* Linker script for STM32F407 *\/\n\n\/* XXX: Currently only runs from RAM *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K\n  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K\n  RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 0x1FE78\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > RAM\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > RAM\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > RAM\n\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data)\n\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n    } > RAM\n    \n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6b29062987510f97bf56dcf60b7260eaaaae53f7","subject":"Correct start address of region kseg0_eeprom_mem","message":"Correct start address of region kseg0_eeprom_mem\n\n\nFormer-commit-id: cd9c2afa8d2702df676ab31a0ac711d7bfb933ce\n","repos":"EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,majenkotech\/chipKIT-core,chipKIT32\/chipkit-core,ricklon\/chipKIT-core,adamwolf\/chipKIT-core,pontech\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,chipKIT32\/chipkit-core,majenkotech\/chipKIT-core,pontech\/chipKIT-core,pontech\/chipKIT-core,UECIDE\/chipKIT-core,UECIDE\/chipKIT-core,chipKIT32\/chipkit-core,adamwolf\/chipKIT-core,pontech\/chipKIT-core,pontech\/chipKIT-core,UECIDE\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,pontech\/chipKIT-core,chipKIT32\/chipkit-core,ricklon\/chipKIT-core,ricklon\/chipKIT-core,UECIDE\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,EmbeddedMan\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,ricklon\/chipKIT-core,adamwolf\/chipKIT-core,adamwolf\/chipKIT-core,UECIDE\/chipKIT-core,chipKIT32\/chipkit-core","old_file":"pic32\/cores\/pic32\/chipKIT-MAX32-application-32MX795F512L.ld","new_file":"pic32\/cores\/pic32\/chipKIT-MAX32-application-32MX795F512L.ld","new_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\n_ebase_address  = 0x9D000000;\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_RESET_ADDR              = 0x9D001000;\n_EEPROM_ADDR             = 0x9D07C000;\n_BEV_EXCPT_ADDR          = 0xBFC00380;\n_DBG_EXCPT_ADDR          = 0xBFC00480;\n_DBG_CODE_ADDR           = 0xBFC02000;\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7B000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07C000, LENGTH = 0x4000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 \n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\nSECTIONS\n{\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg0_program_mem\n  \n  .eeprom_pic32 _EEPROM_ADDR :\n  { \n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\n    \/* . += 0x4000; *\/\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n  .vector_0 _ebase_address + 0x200 :\n  {\n    KEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n\n    _text_end = . ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }>kseg0_program_mem\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n  }>kseg0_program_mem\n\n\n  \/* Read-only sections *\/\n  .rodata   :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } >kseg1_data_mem\n  .data  ALIGN(4)  :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _data_image_begin = LOADADDR(.data) ;\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit8           :\n  {\n    *(.lit8)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    _sbss_end = . ;\n  } >kseg1_data_mem\n  .bss ALIGN(4)  :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0  : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","old_contents":"\/* Default linker script, for normal executables *\/\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\nENTRY(_reset)\n\/*\n * Provide for a minimum stack and heap size\n * - _min_stack_size - represents the minimum space that must be made\n *                     available for the stack.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n * - _min_heap_size  - represents the minimum space that must be made\n *                     available for the heap.  Can be overridden from\n *                     the command line using the linker's --defsym option.\n *\/\nEXTERN (_min_stack_size _min_heap_size)\nPROVIDE(_min_stack_size = 0x800) ;\nPROVIDE(_min_heap_size = 0x800) ;\n\n\/*************************************************************************\n * Processor-specific object file.  Contains SFR definitions.\n *************************************************************************\/\nINPUT(\"processor.o\")\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\n_ebase_address  = 0x9D000000;\n\n\/*************************************************************************\n * Memory Address Equates\n *************************************************************************\/\n_RESET_ADDR              = 0x9D001000;\n_EEPROM_ADDR             = 0x9D07C000;\n_BEV_EXCPT_ADDR          = 0xBFC00380;\n_DBG_EXCPT_ADDR          = 0xBFC00480;\n_DBG_CODE_ADDR           = 0xBFC02000;\n_GEN_EXCPT_ADDR          = _ebase_address + 0x180;\n\n\/*************************************************************************\n * Memory Regions\n *\n * Memory regions without attributes cannot be used for orphaned sections.\n * Only sections specifically assigned to these regions can be allocated\n * into these regions.\n *************************************************************************\/\nMEMORY\n{\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D001000, LENGTH = 0x7B000\n  kseg0_eeprom_mem           : ORIGIN = 0x9D07F000, LENGTH = 0x4000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00490, LENGTH = 0\n  exception_mem              : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0 \n  debug_exec_mem             : ORIGIN = 0xBFC02000, LENGTH = 0\n  config3                    : ORIGIN = 0xBFC02FF0, LENGTH = 0 \n  config2                    : ORIGIN = 0xBFC02FF4, LENGTH = 0\n  config1                    : ORIGIN = 0xBFC02FF8, LENGTH = 0\n  config0                    : ORIGIN = 0xBFC02FFC, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n  sfrs                       : ORIGIN = 0xBF800000, LENGTH = 0x100000\n  configsfrs                 : ORIGIN = 0xBFC02FF0, LENGTH = 0x10\n}\n\nSECTIONS\n{\n  \/* Boot Sections *\/\n  .reset _RESET_ADDR :\n  {\n    KEEP(*(.reset))\n  } > kseg0_program_mem\n  \n  .eeprom_pic32 _EEPROM_ADDR :\n  { \n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\n    \/* . += 0x4000; *\/\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n  .vector_0 _ebase_address + 0x200 :\n  {\n    KEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n\n    _text_end = . ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  }>kseg0_program_mem\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n  }>kseg0_program_mem\n\n\n  \/* Read-only sections *\/\n  .rodata   :\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  \/* Persistent data *\/\n  .persist :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } >kseg1_data_mem\n  .data  ALIGN(4)  :\n  {\n    _data_begin = . ;\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _data_image_begin = LOADADDR(.data) ;\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit8           :\n  {\n    *(.lit8)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem AT>kseg0_program_mem\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    _sbss_end = . ;\n  } >kseg1_data_mem\n  .bss ALIGN(4)  :\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n  \/* Heap allocating takes a chunk of memory following BSS *\/\n  .heap ALIGN(8) :\n  {\n    _heap = . ;\n    . += _min_heap_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/* Stack allocation follows the heap *\/\n  .stack ALIGN(8) :\n  {\n    _splim = . ;\n    _SPLIM = . ;\n    . += _min_stack_size ;\n    . = ALIGN(8);\n  } >kseg1_data_mem\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\/\n  .ramfunc ALIGN(2K) :\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >kseg1_data_mem AT>kseg0_program_mem\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n  _bmxdkpba_address = _ramfunc_begin - ORIGIN(kseg1_data_mem) ;\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n  \/*\n   * The actual top of stack should include the gap between the stack\n   * section and the beginning of the .ramfunc section caused by the\n   * alignment of the .ramfunc section minus 1 word.  If RAM functions\n   * do not exist, then the top of the stack should point to the end of\n   * the data memory.\n   *\/\n  _stack = (_ramfunc_length > 0)\n         ? _ramfunc_begin - 4\n         : ORIGIN(kseg1_data_mem) + LENGTH(kseg1_data_mem) ;\n  ASSERT((_min_stack_size + _min_heap_size) <= (_stack - _heap),\n    \"Not enough space to allocate both stack and heap.  Reduce heap and\/or stack size.\")\n    \/* The .pdr section belongs in the absolute section *\/\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0  : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9d121df705cbb21d0ff82ed237f761b9442e48e3","subject":"fix compile regression after folder position change","message":"fix compile regression after folder position change\n","repos":"lancernet\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,lancernet\/Espruino,lancernet\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,lancernet\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino","old_file":"targetlibs\/nrf5x\/nrf5x_linkers\/secure_dfu_gcc_nrf52.ld","new_file":"targetlibs\/nrf5x\/nrf5x_linkers\/secure_dfu_gcc_nrf52.ld","new_contents":"\/* Linker script to configure memory regions. *\/\r\n\r\nSEARCH_DIR(.)\r\nGROUP(-lgcc -lc -lnosys)\r\n\r\nMEMORY\r\n{\r\n  \/** Flash start address for the bootloader. This setting will also be stored in UICR to allow the\r\n   *  MBR to init the bootloader when starting the system. This value must correspond to\r\n   *  BOOTLOADER_REGION_START found in dfu_types.h. The system is prevented from starting up if\r\n   *  those values do not match. The check is performed in main.c, see\r\n   *  APP_ERROR_CHECK_BOOL(*((uint32_t *)NRF_UICR_BOOT_START_ADDRESS) == BOOTLOADER_REGION_START);\r\n   *\/\r\n  FLASH (rx) : ORIGIN = 0x78000, LENGTH = 0x6000\r\n\r\n  \/** RAM Region for bootloader. This setting is suitable when used with s132. *\/\r\n  RAM (rwx) :  ORIGIN = 0x20002C00, LENGTH = 0x5380\r\n\r\n  \/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n   *  from application to bootloader when using buttonluss DFU OTA.\r\n   *\/\r\n  NOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n  \/** Location of bootloader setting in flash. *\/\r\n  BOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n\r\n  \/** Location in UICR where bootloader start address is stored. *\/\r\n  UICR_BOOTLOADER (r) : ORIGIN = 0x10001014, LENGTH = 0x04\r\n\r\n  \/** Location of mbr params page in flash. *\/\r\n  MBR_PARAMS_PAGE (rw) : ORIGIN = 0x0007E000, LENGTH = 0x1000\r\n\r\n  \/** Location in UICR where mbr params page address is stored. *\/\r\n  UICR_MBR_PARAM_PAGE(r) : ORIGIN = 0x10001018, LENGTH = 0x04\r\n}\r\n\r\nSECTIONS\r\n{\r\n  \/* Place the bootloader settings page in flash. *\/\r\n  .bootloaderSettings(NOLOAD) :\r\n  {\r\n\r\n  } > BOOTLOADER_SETTINGS\r\n\r\n  \/* Write the bootloader address in UICR. *\/\r\n  .uicrBootStartAddress :\r\n  {\r\n    KEEP(*(.uicrBootStartAddress))\r\n  } > UICR_BOOTLOADER\r\n\r\n  \/* Place the mbr params page in flash. *\/\r\n    .mbrParamsPage(NOLOAD) :\r\n  {\r\n\r\n  } > MBR_PARAMS_PAGE\r\n\r\n  \/* Write the bootloader address in UICR. *\/\r\n  .uicrMbrParamsPageAddress :\r\n  {\r\n    KEEP(*(.uicrMbrParamsPageAddress))\r\n  } > UICR_MBR_PARAM_PAGE\r\n\r\n  \/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n  .noinit(NOLOAD) :\r\n  {\r\n\r\n  } > NOINIT\r\n  \/* other placements follow here... *\/\r\n}\r\n\r\nSECTIONS\r\n{\r\n  . = ALIGN(4);\r\n  .fs_data :\r\n  {\r\n    PROVIDE(__start_fs_data = .);\r\n    KEEP(*(.fs_data))\r\n    PROVIDE(__stop_fs_data = .);\r\n  } > RAM\r\n\r\n  . = ALIGN(4);\r\n  .svc_data :\r\n  {\r\n    PROVIDE(__start_svc_data = .);\r\n    KEEP(*(.svc_data))\r\n    PROVIDE(__stop_svc_data = .);\r\n  } > RAM\r\n\r\n  . = ALIGN(4);\r\n  .dfu_trans :\r\n  {\r\n    PROVIDE(__start_dfu_trans = .);\r\n    KEEP(*(.dfu_trans))\r\n    PROVIDE(__stop_dfu_trans = .);\r\n  } > RAM\r\n\r\n} INSERT AFTER .data\r\n\r\nINCLUDE \"..\/components\/toolchain\/gcc\/nrf52_common.ld\"\r\n","old_contents":"\/* Linker script to configure memory regions. *\/\r\n\r\nSEARCH_DIR(.)\r\nGROUP(-lgcc -lc -lnosys)\r\n\r\nMEMORY\r\n{\r\n  \/** Flash start address for the bootloader. This setting will also be stored in UICR to allow the\r\n   *  MBR to init the bootloader when starting the system. This value must correspond to\r\n   *  BOOTLOADER_REGION_START found in dfu_types.h. The system is prevented from starting up if\r\n   *  those values do not match. The check is performed in main.c, see\r\n   *  APP_ERROR_CHECK_BOOL(*((uint32_t *)NRF_UICR_BOOT_START_ADDRESS) == BOOTLOADER_REGION_START);\r\n   *\/\r\n  FLASH (rx) : ORIGIN = 0x78000, LENGTH = 0x6000\r\n\r\n  \/** RAM Region for bootloader. This setting is suitable when used with s132. *\/\r\n  RAM (rwx) :  ORIGIN = 0x20002C00, LENGTH = 0x5380\r\n\r\n  \/** Location of non initialized RAM. Non initialized RAM is used for exchanging bond information\r\n   *  from application to bootloader when using buttonluss DFU OTA.\r\n   *\/\r\n  NOINIT (rwx) :  ORIGIN = 0x20007F80, LENGTH = 0x80\r\n\r\n  \/** Location of bootloader setting in flash. *\/\r\n  BOOTLOADER_SETTINGS (rw) : ORIGIN = 0x0007F000, LENGTH = 0x1000\r\n\r\n  \/** Location in UICR where bootloader start address is stored. *\/\r\n  UICR_BOOTLOADER (r) : ORIGIN = 0x10001014, LENGTH = 0x04\r\n\r\n  \/** Location of mbr params page in flash. *\/\r\n  MBR_PARAMS_PAGE (rw) : ORIGIN = 0x0007E000, LENGTH = 0x1000\r\n\r\n  \/** Location in UICR where mbr params page address is stored. *\/\r\n  UICR_MBR_PARAM_PAGE(r) : ORIGIN = 0x10001018, LENGTH = 0x04\r\n}\r\n\r\nSECTIONS\r\n{\r\n  \/* Place the bootloader settings page in flash. *\/\r\n  .bootloaderSettings(NOLOAD) :\r\n  {\r\n\r\n  } > BOOTLOADER_SETTINGS\r\n\r\n  \/* Write the bootloader address in UICR. *\/\r\n  .uicrBootStartAddress :\r\n  {\r\n    KEEP(*(.uicrBootStartAddress))\r\n  } > UICR_BOOTLOADER\r\n\r\n  \/* Place the mbr params page in flash. *\/\r\n    .mbrParamsPage(NOLOAD) :\r\n  {\r\n\r\n  } > MBR_PARAMS_PAGE\r\n\r\n  \/* Write the bootloader address in UICR. *\/\r\n  .uicrMbrParamsPageAddress :\r\n  {\r\n    KEEP(*(.uicrMbrParamsPageAddress))\r\n  } > UICR_MBR_PARAM_PAGE\r\n\r\n  \/* No init RAM section in bootloader. Used for bond information exchange. *\/\r\n  .noinit(NOLOAD) :\r\n  {\r\n\r\n  } > NOINIT\r\n  \/* other placements follow here... *\/\r\n}\r\n\r\nSECTIONS\r\n{\r\n  . = ALIGN(4);\r\n  .fs_data :\r\n  {\r\n    PROVIDE(__start_fs_data = .);\r\n    KEEP(*(.fs_data))\r\n    PROVIDE(__stop_fs_data = .);\r\n  } > RAM\r\n\r\n  . = ALIGN(4);\r\n  .svc_data :\r\n  {\r\n    PROVIDE(__start_svc_data = .);\r\n    KEEP(*(.svc_data))\r\n    PROVIDE(__stop_svc_data = .);\r\n  } > RAM\r\n\r\n  . = ALIGN(4);\r\n  .dfu_trans :\r\n  {\r\n    PROVIDE(__start_dfu_trans = .);\r\n    KEEP(*(.dfu_trans))\r\n    PROVIDE(__stop_dfu_trans = .);\r\n  } > RAM\r\n\r\n} INSERT AFTER .data\r\n\r\nINCLUDE \"..\/nrf5_sdk\/components\/toolchain\/gcc\/nrf52_common.ld\"\r\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"dfbff57cfa19a2028d295ecad4618c40c1e0284c","subject":"Formatting","message":"Formatting\n","repos":"benaryorg\/benarydingOS,benaryorg\/benarydingOS,benaryorg\/benarydingOS,benaryorg\/benarydingOS","old_file":"src\/linker\/kernel.ld","new_file":"src\/linker\/kernel.ld","new_contents":"ENTRY(_start)\n\nSECTIONS\n{\n\t. = 0x100000;\n\t\n\tkrnl_start=.;\n\n\t.text:\n\t{\n\t\t*(multiboot)\n\t\t*(.text)\n\t}\n\n\t.data ALIGN(4096):\n\t{\n\t\t*(.data)\n\t}\n\n\t.rodata ALIGN(4096):\n\t{\n\t\t*(.rodata)\n\t}\n\n\t.bss ALIGN(4096):\n\t{\n\t\t*(.bss)\n\t}\n\n\t. = ALIGN(4096);\n\tkrnl_end=.;\n}\n","old_contents":"ENTRY(_start)\n\nSECTIONS\n{\n\t. = 0x100000;\n\t\n\tkernel_start=.;\n\n\t.text:\n\t{\n\t\t*(multiboot)\n\t\t*(.text)\n\t}\n\n\t.data ALIGN(4096):\n\t{\n\t\t*(.data)\n\t}\n\n\t.rodata ALIGN(4096):\n\t{\n\t\t*(.rodata)\n\t}\n\n\t.bss ALIGN(4096):\n\t{\n\t\t*(.bss)\n\t}\n\n\t. = ALIGN(4096);\n\tkernel_end=.;\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"051f355720346d8f2a0fe97d50ab7d4c97b9e7b9","subject":"demo\/kernel-stm32f4xx.ld: fix tyop","message":"demo\/kernel-stm32f4xx.ld: fix tyop\n","repos":"cbiffle\/brittle-kernel,cbiffle\/brittle-kernel,cbiffle\/brittle-kernel,cbiffle\/brittle-kernel","old_file":"demo\/kernel-stm32f4xx.ld","new_file":"demo\/kernel-stm32f4xx.ld","new_contents":"MEMORY {\n  \/* Alias of the SRAM112 region when it's remapped. *\/\n  sram112_at_zero (rwx) : ORIGIN = 0x00000000, LENGTH =  112K\n\n  rom (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  ccm (rwx)     : ORIGIN = 0x10000000, LENGTH =   64K\n  sram112 (rwx) : ORIGIN = 0x20000000, LENGTH =  112K\n  sram16  (rwx) : ORIGIN = 0x2001c000, LENGTH =   16K\n}\n\nEXTERN(_ZN3etl6armv7m15exception_tableE)\nEXTERN(_ZN4demo4mainEv)\n\nENTRY(etl_armv7m_reset_handler)\n\nSECTIONS {\n  .vector_tables : {\n    PROVIDE(_kernel_rom_start = .);\n    KEEP(*(.etl_armv7m_exception_table*))\n    KEEP(*(.etl_stm32f4xx_interrupt_table))\n    \/* Include initialized data here, so we initialize it during the copy. *\/\n    \/* We use a word copy, so ensure alignment. *\/\n    . = ALIGN(4);\n  } >rom\n\n  .text : {\n    *(.text*)\n    . = ALIGN(4);\n    *(.rodata*)\n  } >rom\n\n  .init : ALIGN(2) {\n    KEEP(*(.init_prologue))\n    KEEP(*(.init))\n    KEEP(*(.init_epilogue))\n  } >rom\n\n  .preinit_array : ALIGN(4) {\n    _preinit_array_start = .;\n    KEEP(*(.preinit_array))\n    _preinit_array_end = .;\n  } >rom\n\n  .init_array : ALIGN(4) {\n    _init_array_start = .;\n    KEEP(*(.init_array))\n    _init_array_end = .;\n  } >rom\n\n  .data : {\n    PROVIDE(_kernel_ram_start = .);\n    *(.data*)\n  } >ccm AT>rom\n\n  PROVIDE(_data_init_image_start = LOADADDR(.data));\n  PROVIDE(_data_start = ADDR(.data));\n  PROVIDE(_data_end = ADDR(.data) + SIZEOF(.data));\n\n  .app : {\n    . = ORIGIN(rom) + 16384;\n    PROVIDE(_app_rom_start = .);\n    . = ORIGIN(rom) + LENGTH(rom);\n    PROVIDE(_app_rom_end = .);\n  } >rom\n\n  .bss (NOLOAD) : {\n    . += 512;  \/* Leave room for a stack. *\/\n    PROVIDE(etl_armv7m_initial_stack_top = .);\n    . += 512;  \/* HACK padding *\/\n    . = ALIGN(4);\n    PROVIDE(_bss_start = .);\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE(_bss_end = .);\n    PROVIDE(_kernel_ram_end = .);\n  } >ccm\n\n  .app_ram (NOLOAD) : {\n    PROVIDE(_app_ram_start = .);\n    . = ORIGIN(sram112) + LENGTH(sram112);\n    PROVIDE(_app_ram_end = .);\n  } >sram112\n}\n","old_contents":"MEMORY {\n  \/* Alias of the SRAM112 region when it's remapped. *\/\n  sram112_at_zero (rwx) : ORIGIN = 0x00000000, LENGTH =  112K\n\n  rom (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  ccm (rwx)     : ORIGIN = 0x10000000, LENGTH =   64K\n  sram112 (rwx) : ORIGIN = 0x20000000, LENGTH =  112K\n  sram16  (rwx) : ORIGIN = 0x2001c000, LENGTH =   16K\n}\n\nEXTERN(_ZN3etl6armv7mL15exception_tableE)\nEXTERN(_ZN4demo4mainEv)\n\nENTRY(etl_armv7m_reset_handler)\n\nSECTIONS {\n  .vector_tables : {\n    PROVIDE(_kernel_rom_start = .);\n    KEEP(*(.etl_armv7m_exception_table*))\n    KEEP(*(.etl_stm32f4xx_interrupt_table))\n    \/* Include initialized data here, so we initialize it during the copy. *\/\n    \/* We use a word copy, so ensure alignment. *\/\n    . = ALIGN(4);\n  } >rom\n\n  .text : {\n    *(.text*)\n    . = ALIGN(4);\n    *(.rodata*)\n  } >rom\n\n  .init : ALIGN(2) {\n    KEEP(*(.init_prologue))\n    KEEP(*(.init))\n    KEEP(*(.init_epilogue))\n  } >rom\n\n  .preinit_array : ALIGN(4) {\n    _preinit_array_start = .;\n    KEEP(*(.preinit_array))\n    _preinit_array_end = .;\n  } >rom\n\n  .init_array : ALIGN(4) {\n    _init_array_start = .;\n    KEEP(*(.init_array))\n    _init_array_end = .;\n  } >rom\n\n  .data : {\n    PROVIDE(_kernel_ram_start = .);\n    *(.data*)\n  } >ccm AT>rom\n\n  PROVIDE(_data_init_image_start = LOADADDR(.data));\n  PROVIDE(_data_start = ADDR(.data));\n  PROVIDE(_data_end = ADDR(.data) + SIZEOF(.data));\n\n  .app : {\n    . = ORIGIN(rom) + 16384;\n    PROVIDE(_app_rom_start = .);\n    . = ORIGIN(rom) + LENGTH(rom);\n    PROVIDE(_app_rom_end = .);\n  } >rom\n\n  .bss (NOLOAD) : {\n    . += 512;  \/* Leave room for a stack. *\/\n    PROVIDE(etl_armv7m_initial_stack_top = .);\n    . += 512;  \/* HACK padding *\/\n    . = ALIGN(4);\n    PROVIDE(_bss_start = .);\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE(_bss_end = .);\n    PROVIDE(_kernel_ram_end = .);\n  } >ccm\n\n  .app_ram (NOLOAD) : {\n    PROVIDE(_app_ram_start = .);\n    . = ORIGIN(sram112) + LENGTH(sram112);\n    PROVIDE(_app_ram_end = .);\n  } >sram112\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b3b04faadb6783b6238a05eded75bb0bc8a0f9eb","subject":"cpu\/fe310: add XFA support","message":"cpu\/fe310: add XFA support\n","repos":"kYc0o\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,ant9000\/RIOT,authmillenon\/RIOT,OlegHahm\/RIOT,OTAkeys\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,miri64\/RIOT,authmillenon\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,authmillenon\/RIOT,OlegHahm\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,kYc0o\/RIOT","old_file":"cpu\/riscv_common\/ldscripts\/riscv_base.ld","new_file":"cpu\/riscv_common\/ldscripts\/riscv_base.ld","new_contents":"\/*\n * Copyright (C) 2017, 2019   Ken Rabold\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_riscv_common\n * @{\n *\n * @file\n * @brief           Common linker directives for the RISC-V CPU\n *\n * @author          Ken Rabold\n *\n * @}\n *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nPHDRS\n{\n  flash PT_LOAD;\n  ram_init PT_LOAD;\n  ram PT_NULL;\n  tls PT_TLS;\n}\n\nSECTIONS\n{\n  __stack_size     = DEFINED(__stack_size) ? __stack_size : 256;\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash AT>flash :flash\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >flash AT>flash :flash\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >flash AT>flash :flash\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n    KEEP (*(SORT(.roxfa.*)))\n  } >flash AT>flash :flash\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash AT>flash :flash\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash AT>flash :flash\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash AT>flash :flash\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash AT>flash :flash\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash AT>flash :flash\n\n  \/*\n   * TLS relocations are offsets relative to the address\n   * of the first TLS symbol. That means we just need to\n   * allocate them all together so that the TLS region\n   * is compact when allocated for each thread.\n   *\/\n\n  \/*\n   * TLS initialization data is loaded into ROM so that\n   * each thread can get its values initialized from there\n   * at startup\n   *\/\n  .tdata :\n  {\n       __tdata_start = .;\n      *(.tdata .tdata.* .gnu.linkonce.td.*)\n      __tdata_end = .;\n  } >flash AT>flash :tls\n  __tdata_source = LOADADDR(.tdata);\n  __tdata_size = SIZEOF(.tdata);\n\n  \/*\n   * TLS zeroed data is relocated as if it immediately followed\n   * the tdata values. However, the linker 'magically' erases the\n   * memory allocation so that no ROM is consumed by this\n   * section\n   *\/\n  .tbss :\n  {\n      *(.tbss .tbss.* .gnu.linkonce.tb.*)\n      *(.tcommon)\n      __tbss_end = .;\n  } >flash : tls\n  __tls_size = __tbss_end - __tdata_start;\n  __tbss_size = __tls_size - __tdata_size;\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash AT>flash :flash\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash :ram_init\n\n  .data          :\n  {\n    *(.ramfunc .ramfunc.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n    KEEP (*(SORT(.xfa.*)))\n  } >ram AT>flash :ram_init\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram AT>ram :ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n  PROVIDE( _sheap = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _eheap = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram AT>ram :ram\n}\n","old_contents":"\/*\n * Copyright (C) 2017, 2019   Ken Rabold\n *\n * This file is subject to the terms and conditions of the GNU Lesser\n * General Public License v2.1. See the file LICENSE in the top level\n * directory for more details.\n *\/\n\n\/**\n * @addtogroup      cpu_riscv_common\n * @{\n *\n * @file\n * @brief           Common linker directives for the RISC-V CPU\n *\n * @author          Ken Rabold\n *\n * @}\n *\/\n\nOUTPUT_ARCH( \"riscv\" )\n\nENTRY( _start )\n\nPHDRS\n{\n  flash PT_LOAD;\n  ram_init PT_LOAD;\n  ram PT_NULL;\n  tls PT_TLS;\n}\n\nSECTIONS\n{\n  __stack_size     = DEFINED(__stack_size) ? __stack_size : 256;\n\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  } >flash AT>flash :flash\n\n  .text           :\n  {\n    *(.text.unlikely .text.unlikely.*)\n    *(.text.startup .text.startup.*)\n    *(.text .text.*)\n    *(.gnu.linkonce.t.*)\n  } >flash AT>flash :flash\n\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  } >flash AT>flash :flash\n\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n\n  .rodata         :\n  {\n    *(.rdata)\n    *(.rodata .rodata.*)\n    *(.gnu.linkonce.r.*)\n  } >flash AT>flash :flash\n\n  . = ALIGN(4);\n\n  .preinit_array  :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >flash AT>flash :flash\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\n    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >flash AT>flash :flash\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >flash AT>flash :flash\n\n  .ctors          :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } >flash AT>flash :flash\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } >flash AT>flash :flash\n\n  \/*\n   * TLS relocations are offsets relative to the address\n   * of the first TLS symbol. That means we just need to\n   * allocate them all together so that the TLS region\n   * is compact when allocated for each thread.\n   *\/\n\n  \/*\n   * TLS initialization data is loaded into ROM so that\n   * each thread can get its values initialized from there\n   * at startup\n   *\/\n  .tdata :\n  {\n       __tdata_start = .;\n      *(.tdata .tdata.* .gnu.linkonce.td.*)\n      __tdata_end = .;\n  } >flash AT>flash :tls\n  __tdata_source = LOADADDR(.tdata);\n  __tdata_size = SIZEOF(.tdata);\n\n  \/*\n   * TLS zeroed data is relocated as if it immediately followed\n   * the tdata values. However, the linker 'magically' erases the\n   * memory allocation so that no ROM is consumed by this\n   * section\n   *\/\n  .tbss :\n  {\n      *(.tbss .tbss.* .gnu.linkonce.tb.*)\n      *(.tcommon)\n      __tbss_end = .;\n  } >flash : tls\n  __tls_size = __tbss_end - __tdata_start;\n  __tbss_size = __tls_size - __tdata_size;\n\n  .lalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data_lma = . );\n  } >flash AT>flash :flash\n\n  .dalign         :\n  {\n    . = ALIGN(4);\n    PROVIDE( _data = . );\n  } >ram AT>flash :ram_init\n\n  .data          :\n  {\n    *(.ramfunc .ramfunc.*)\n    *(.data .data.*)\n    *(.gnu.linkonce.d.*)\n    . = ALIGN(8);\n    PROVIDE( __global_pointer$ = . + 0x800 );\n    *(.sdata .sdata.*)\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(8);\n    *(.srodata.cst16)\n    *(.srodata.cst8)\n    *(.srodata.cst4)\n    *(.srodata.cst2)\n    *(.srodata .srodata.*)\n  } >ram AT>flash :ram_init\n\n  . = ALIGN(4);\n  PROVIDE( _edata = . );\n  PROVIDE( edata = . );\n\n  PROVIDE( _fbss = . );\n  PROVIDE( __bss_start = . );\n  .bss            :\n  {\n    *(.sbss*)\n    *(.gnu.linkonce.sb.*)\n    *(.bss .bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(4);\n  } >ram AT>ram :ram\n\n  . = ALIGN(8);\n  PROVIDE( _end = . );\n  PROVIDE( end = . );\n  PROVIDE( _sheap = . );\n\n  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\n  {\n    PROVIDE( _eheap = . );\n    . = __stack_size;\n    PROVIDE( _sp = . );\n  } >ram AT>ram :ram\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"09df2d8fdfc199069440cd1cc80a6c46ca7eba99","subject":"[KINETIS] Fix base flash size","message":"[KINETIS] Fix base flash size\n\ngit-svn-id: de15d415ffb1bc5d91a165b5b7d2093897d104a2@7219 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"os\/common\/ports\/ARMCMx\/compilers\/GCC\/ld\/MK20DX128.ld","new_file":"os\/common\/ports\/ARMCMx\/compilers\/GCC\/ld\/MK20DX128.ld","new_contents":"","old_contents":"","returncode":0,"stderr":"unknown","license":"apache-2.0","lang":"Linker Script"}
{"commit":"006d12eccafb5dc72f25cca19ff07d78b336a989","subject":"modify 00 hello.ld","message":"modify 00 hello.ld\n","repos":"tony0620emma\/mini-arm-os,tony0620emma\/mini-arm-os","old_file":"00-HelloWorld\/hello.ld","new_file":"00-HelloWorld\/hello.ld","new_contents":"\nMEMORY\n{\n\tFLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K\n}\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text)\n\t} >FLASH\n}\n","old_contents":"ENTRY(reset_handler)\n\nMEMORY\n{\n\tFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K\n}\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text)\n\t} >FLASH\n}\n","returncode":0,"stderr":"","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"9011a5453ada72ac2e2390f1366974561fe4d0e4","subject":"Compile network and RTOS with GCC_ARM","message":"Compile network and RTOS with GCC_ARM\n","repos":"pi19404\/mbed,pradeep-gr\/mbed-os5-onsemi,DanKupiniak\/mbed,larks\/mbed,Marcomissyou\/mbed,Sweet-Peas\/mbed,mnlipp\/mbed,RonEld\/mbed,fvincenzo\/mbed-os,infinnovation\/mbed-os,nRFMesh\/mbed-os,brstew\/MBED-BUILD,pbrook\/mbed,larks\/mbed,jpbrucker\/mbed,cvtsi2sd\/mbed-os,NXPmicro\/mbed,devanlai\/mbed,naves-thiago\/mbed-midi,kjbracey-arm\/mbed,cvtsi2sd\/mbed-os,YarivCol\/mbed-os,bcostm\/mbed-os,Archcady\/mbed-os,geky\/mbed,logost\/mbed,nRFMesh\/mbed-os,alertby\/mbed,betzw\/mbed-os,jferreir\/mbed,c1728p9\/mbed-os,mazimkhan\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,fpiot\/mbed-ats,rosterloh\/mbed,nvlsianpu\/mbed,geky\/mbed,rosterloh\/mbed,cvtsi2sd\/mbed-os,bentwire\/mbed,pradeep-gr\/mbed-os5-onsemi,larks\/mbed,bremoran\/mbed-drivers,theotherjimmy\/mbed,arostm\/mbed-os,andreaslarssonublox\/mbed,logost\/mbed,andcor02\/mbed-os,svastm\/mbed,Sweet-Peas\/mbed,mnlipp\/mbed,mmorenobarm\/mbed-os,bikeNomad\/mbed,catiedev\/mbed-os,arostm\/mbed-os,infinnovation\/mbed-os,c1728p9\/mbed-os,YarivCol\/mbed-os,ban4jp\/mbed,Tiryoh\/mbed,RonEld\/mbed,nabilbendafi\/mbed,c1728p9\/mbed-os,Timmmm\/mbed,tung7970\/mbed-os,arostm\/mbed-os,Sweet-Peas\/mbed,JasonHow44\/mbed,adamgreen\/mbed,jferreir\/mbed,jpbrucker\/mbed,YarivCol\/mbed-os,CalSol\/mbed,bulislaw\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,fpiot\/mbed-ats,jamesadevine\/mbed,pi19404\/mbed,screamerbg\/mbed,NitinBhaskar\/mbed,sam-geek\/mbed,bcostm\/mbed-os,fanghuaqi\/mbed,screamerbg\/mbed,GustavWi\/mbed,cvtsi2sd\/mbed-os,fpiot\/mbed-ats,svogl\/mbed-os,kpurusho\/mbed,naves-thiago\/mbed-midi,pedromes\/mbed,logost\/mbed,jferreir\/mbed,sg-\/mbed-drivers,netzimme\/mbed-os,K4zuki\/mbed,c1728p9\/mbed-os,NitinBhaskar\/mbed,larks\/mbed,sam-geek\/mbed,bentwire\/mbed,jpbrucker\/mbed,catiedev\/mbed-os,sg-\/mbed-drivers,geky\/mbed,devanlai\/mbed,bikeNomad\/mbed,Shengliang\/mbed,pradeep-gr\/mbed-os5-onsemi,tung7970\/mbed-os-1,xcrespo\/mbed,jamesadevine\/mbed,ryankurte\/mbed-os,ARM-software\/mbed-beetle,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,EmuxEvans\/mbed,Archcady\/mbed-os,hwfwgrp\/mbed,K4zuki\/mbed,nRFMesh\/mbed-os,andreaslarssonublox\/mbed,kl-cruz\/mbed-os,EmuxEvans\/mbed,hwfwgrp\/mbed,Marcomissyou\/mbed,theotherjimmy\/mbed,JasonHow44\/mbed,j-greffe\/mbed-os,alertby\/mbed,RonEld\/mbed,kjbracey-arm\/mbed,ban4jp\/mbed,fanghuaqi\/mbed,pi19404\/mbed,FranklyDev\/mbed,Shengliang\/mbed,brstew\/MBED-BUILD,mmorenobarm\/mbed-os,K4zuki\/mbed,svogl\/mbed-os,rgrover\/mbed,EmuxEvans\/mbed,wodji\/mbed,nvlsianpu\/mbed,betzw\/mbed-os,DanKupiniak\/mbed,bentwire\/mbed,infinnovation\/mbed-os,infinnovation\/mbed-os,fahhem\/mbed-os,karsev\/mbed-os,CalSol\/mbed,jeremybrodt\/mbed,adustm\/mbed,bikeNomad\/mbed,jeremybrodt\/mbed,autopulated\/mbed,betzw\/mbed-os,adustm\/mbed,adamgreen\/mbed,NordicSemiconductor\/mbed,pbrook\/mbed,Willem23\/mbed,jamesadevine\/mbed,pedromes\/mbed,theotherjimmy\/mbed,theotherjimmy\/mbed,theotherjimmy\/mbed,Sweet-Peas\/mbed,xcrespo\/mbed,logost\/mbed,Sweet-Peas\/mbed,al177\/mbed,ryankurte\/mbed-os,brstew\/MBED-BUILD,bulislaw\/mbed-os,fanghuaqi\/mbed,DanKupiniak\/mbed,DanKupiniak\/mbed,mikaleppanen\/mbed-os,mmorenobarm\/mbed-os,andcor02\/mbed-os,andcor02\/mbed-os,alertby\/mbed,cvtsi2sd\/mbed-os,NordicSemiconductor\/mbed,kl-cruz\/mbed-os,monkiineko\/mbed-os,iriark01\/mbed-drivers,NordicSemiconductor\/mbed,mbedmicro\/mbed,betzw\/mbed-os,struempelix\/mbed,infinnovation\/mbed-os,fanghuaqi\/mbed,ryankurte\/mbed-os,fahhem\/mbed-os,adamgreen\/mbed,svastm\/mbed,jrjang\/mbed,EmuxEvans\/mbed,bcostm\/mbed-os,nvlsianpu\/mbed,screamerbg\/mbed,rosterloh\/mbed,bikeNomad\/mbed,karsev\/mbed-os,karsev\/mbed-os,screamerbg\/mbed,mazimkhan\/mbed-os,jferreir\/mbed,Willem23\/mbed,YarivCol\/mbed-os,struempelix\/mbed,RonEld\/mbed,dbestm\/mbed,adustm\/mbed,jeremybrodt\/mbed,bulislaw\/mbed-os,HeadsUpDisplayInc\/mbed,devanlai\/mbed,netzimme\/mbed-os,K4zuki\/mbed,Timmmm\/mbed,pradeep-gr\/mbed-os5-onsemi,autopulated\/mbed,Marcomissyou\/mbed,Archcady\/mbed-os,al177\/mbed,Timmmm\/mbed,logost\/mbed,Tiryoh\/mbed,adamgreen\/mbed,Tiryoh\/mbed,fahhem\/mbed-os,dbestm\/mbed,pbrook\/mbed,larks\/mbed,svastm\/mbed,bikeNomad\/mbed,catiedev\/mbed-os,andreaslarssonublox\/mbed,mbedmicro\/mbed,NitinBhaskar\/mbed,fahhem\/mbed-os,mikaleppanen\/mbed-os,naves-thiago\/mbed-midi,ban4jp\/mbed,devanlai\/mbed,JasonHow44\/mbed,fpiot\/mbed-ats,rgrover\/mbed,betzw\/mbed-os,Timmmm\/mbed,andreaslarssonublox\/mbed,struempelix\/mbed,andcor02\/mbed-os,mnlipp\/mbed,al177\/mbed,pedromes\/mbed,FranklyDev\/mbed,Tiryoh\/mbed,tung7970\/mbed-os,xcrespo\/mbed,maximmbed\/mbed,kpurusho\/mbed,logost\/mbed,Willem23\/mbed,FranklyDev\/mbed,maximmbed\/mbed,andcor02\/mbed-os,al177\/mbed,pradeep-gr\/mbed-os5-onsemi,nRFMesh\/mbed-os,dbestm\/mbed,nabilbendafi\/mbed,adamgreen\/mbed,getopenmono\/mbed,catiedev\/mbed-os,nabilbendafi\/mbed,mbedmicro\/mbed,hwfwgrp\/mbed,YarivCol\/mbed-os,masaohamanaka\/mbed,bcostm\/mbed-os,nRFMesh\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,radhika-raghavendran\/mbed-os5.1-onsemi,tung7970\/mbed-os,GustavWi\/mbed,K4zuki\/mbed,bentwire\/mbed,mnlipp\/mbed,getopenmono\/mbed,fpiot\/mbed-ats,screamerbg\/mbed,karsev\/mbed-os,kpurusho\/mbed,GustavWi\/mbed,mikaleppanen\/mbed-os,jrjang\/mbed,alertby\/mbed,Tiryoh\/mbed,al177\/mbed,netzimme\/mbed-os,bulislaw\/mbed-os,JasonHow44\/mbed,c1728p9\/mbed-os,getopenmono\/mbed,mazimkhan\/mbed-os,autopulated\/mbed,struempelix\/mbed,fvincenzo\/mbed-os,karsev\/mbed-os,rosterloh\/mbed,maximmbed\/mbed,kl-cruz\/mbed-os,ban4jp\/mbed,ARM-software\/mbed-beetle,svastm\/mbed,masaohamanaka\/mbed,kpurusho\/mbed,NitinBhaskar\/mbed,struempelix\/mbed,autopulated\/mbed,mikaleppanen\/mbed-os,fvincenzo\/mbed-os,mmorenobarm\/mbed-os,karsev\/mbed-os,pi19404\/mbed,hwfwgrp\/mbed,JasonHow44\/mbed,wodji\/mbed,tung7970\/mbed-os,dbestm\/mbed,jrjang\/mbed,autopulated\/mbed,wodji\/mbed,nvlsianpu\/mbed,xcrespo\/mbed,svogl\/mbed-os,Sweet-Peas\/mbed,bcostm\/mbed-os,bulislaw\/mbed-os,jrjang\/mbed,ryankurte\/mbed-os,YarivCol\/mbed-os,Willem23\/mbed,kl-cruz\/mbed-os,mbedmicro\/mbed,NitinBhaskar\/mbed,svastm\/mbed,xcrespo\/mbed,masaohamanaka\/mbed,CalSol\/mbed,kpurusho\/mbed,K4zuki\/mbed,ban4jp\/mbed,netzimme\/mbed-os,jferreir\/mbed,larks\/mbed,pedromes\/mbed,tung7970\/mbed-os,masaohamanaka\/mbed,adamgreen\/mbed,Shengliang\/mbed,rgrover\/mbed,getopenmono\/mbed,JasonHow44\/mbed,al177\/mbed,NXPmicro\/mbed,mmorenobarm\/mbed-os,tung7970\/mbed-os-1,RonEld\/mbed,j-greffe\/mbed-os,bentwire\/mbed,jpbrucker\/mbed,j-greffe\/mbed-os,bcostm\/mbed-os,pi19404\/mbed,jferreir\/mbed,HeadsUpDisplayInc\/mbed,pedromes\/mbed,naves-thiago\/mbed-midi,brstew\/MBED-BUILD,jrjang\/mbed,arostm\/mbed-os,masaohamanaka\/mbed,monkiineko\/mbed-os,naves-thiago\/mbed-midi,catiedev\/mbed-os,0xc0170\/mbed-drivers,nvlsianpu\/mbed,NXPmicro\/mbed,svogl\/mbed-os,Timmmm\/mbed,andreaslarssonublox\/mbed,nabilbendafi\/mbed,catiedev\/mbed-os,pedromes\/mbed,kl-cruz\/mbed-os,kjbracey-arm\/mbed,hwfwgrp\/mbed,NXPmicro\/mbed,dbestm\/mbed,netzimme\/mbed-os,iriark01\/mbed-drivers,ryankurte\/mbed-os,maximmbed\/mbed,rosterloh\/mbed,fvincenzo\/mbed-os,EmuxEvans\/mbed,struempelix\/mbed,jamesadevine\/mbed,Timmmm\/mbed,ban4jp\/mbed,autopulated\/mbed,getopenmono\/mbed,jpbrucker\/mbed,bulislaw\/mbed-os,bremoran\/mbed-drivers,j-greffe\/mbed-os,arostm\/mbed-os,HeadsUpDisplayInc\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,maximmbed\/mbed,mazimkhan\/mbed-os,maximmbed\/mbed,kjbracey-arm\/mbed,ARM-software\/mbed-beetle,brstew\/MBED-BUILD,j-greffe\/mbed-os,monkiineko\/mbed-os,jrjang\/mbed,HeadsUpDisplayInc\/mbed,andcor02\/mbed-os,netzimme\/mbed-os,tung7970\/mbed-os-1,sam-geek\/mbed,ARM-software\/mbed-beetle,bentwire\/mbed,HeadsUpDisplayInc\/mbed,rgrover\/mbed,NXPmicro\/mbed,monkiineko\/mbed-os,mnlipp\/mbed,GustavWi\/mbed,devanlai\/mbed,brstew\/MBED-BUILD,ryankurte\/mbed-os,mikaleppanen\/mbed-os,wodji\/mbed,nabilbendafi\/mbed,adustm\/mbed,Willem23\/mbed,devanlai\/mbed,mikaleppanen\/mbed-os,wodji\/mbed,pbrook\/mbed,FranklyDev\/mbed,fpiot\/mbed-ats,masaohamanaka\/mbed,sam-geek\/mbed,mazimkhan\/mbed-os,mmorenobarm\/mbed-os,Marcomissyou\/mbed,pbrook\/mbed,pradeep-gr\/mbed-os5-onsemi,alertby\/mbed,infinnovation\/mbed-os,cvtsi2sd\/mbed-os,dbestm\/mbed,NXPmicro\/mbed,tung7970\/mbed-os-1,mazimkhan\/mbed-os,naves-thiago\/mbed-midi,RonEld\/mbed,adustm\/mbed,jeremybrodt\/mbed,mnlipp\/mbed,jpbrucker\/mbed,jeremybrodt\/mbed,jamesadevine\/mbed,arostm\/mbed-os,hwfwgrp\/mbed,rgrover\/mbed,NordicSemiconductor\/mbed,Shengliang\/mbed,geky\/mbed,xcrespo\/mbed,screamerbg\/mbed,CalSol\/mbed,Marcomissyou\/mbed,mbedmicro\/mbed,nabilbendafi\/mbed,getopenmono\/mbed,0xc0170\/mbed-drivers,Archcady\/mbed-os,geky\/mbed,alertby\/mbed,jamesadevine\/mbed,svogl\/mbed-os,EmuxEvans\/mbed,CalSol\/mbed,nRFMesh\/mbed-os,tung7970\/mbed-os-1,Archcady\/mbed-os,monkiineko\/mbed-os,fvincenzo\/mbed-os,j-greffe\/mbed-os,betzw\/mbed-os,adustm\/mbed,svogl\/mbed-os,FranklyDev\/mbed,pbrook\/mbed,Marcomissyou\/mbed,wodji\/mbed,sam-geek\/mbed,Tiryoh\/mbed,kl-cruz\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,Shengliang\/mbed,rosterloh\/mbed,CalSol\/mbed,fahhem\/mbed-os,Archcady\/mbed-os,pi19404\/mbed,fahhem\/mbed-os,kpurusho\/mbed,theotherjimmy\/mbed,fanghuaqi\/mbed,GustavWi\/mbed,monkiineko\/mbed-os,Shengliang\/mbed,nvlsianpu\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    \/* Code can explicitly ask for data to be\n       placed in these higher RAM banks where\n       they will be left uninitialized.\n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n    \n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    \/* Code can explicitly ask for data to be\n       placed in these higher RAM banks where\n       they will be left uninitialized.\n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n    \n    \/* .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n        *(.data.$RAM2*)\n        *(.data.$ETH_RAM*)\n       . = ALIGN(4) ;\n    } > ETH_RAM AT>FLASH\n        \n    .bss_RAM2 : ALIGN(4)\n    {\n        *(.bss.$RAM2*)\n        *(.bss.$ETH_RAM*)\n       . = ALIGN(4) ;\n    } > ETH_RAM\n    *\/\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e41c4a692454bd5086ce00af45fe08ae2b75f7e4","subject":"bsp\/nordic_pca10095_net: Set empty IPC region for bootloader build","message":"bsp\/nordic_pca10095_net: Set empty IPC region for bootloader build\n\nIPC is not used in bootloader but linker were complaining about IPC\nregion being not present.\n","repos":"mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core","old_file":"hw\/bsp\/nordic_pca10095_net\/boot-nrf5340_net.ld","new_file":"hw\/bsp\/nordic_pca10095_net\/boot-nrf5340_net.ld","new_contents":"\/*\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n *\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x01000000, LENGTH = 0x4000\n  RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000\n  IPC (rw)  : ORIGIN = 0x20000400, LENGTH = 0\n}\n\n\/* The bootloader does not contain an image header *\/\n_imghdr_size = 0x0;\n","old_contents":"\/*\n * Licensed to the Apache Software Foundation (ASF) under one\n * or more contributor license agreements.  See the NOTICE file\n * distributed with this work for additional information\n * regarding copyright ownership.  The ASF licenses this file\n * to you under the Apache License, Version 2.0 (the\n * \"License\"); you may not use this file except in compliance\n * with the License.  You may obtain a copy of the License at\n *\n *  http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing,\n * software distributed under the License is distributed on an\n * \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n * KIND, either express or implied.  See the License for the\n * specific language governing permissions and limitations\n * under the License.\n *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x01000000, LENGTH = 0x4000\n  RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000\n}\n\n\/* The bootloader does not contain an image header *\/\n_imghdr_size = 0x0;\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b8bf605ad79044c7cf63a3039bd8e02f586c07e9","subject":"x86_64: Improve linker script","message":"x86_64: Improve linker script\n","repos":"uni-rs\/uni.rs","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"OUTPUT_FORMAT(\"elf64-x86-64\", \"elf64-x86-64\", \"elf64-x86-64\")\nOUTPUT_ARCH(i386:x86-64)\nENTRY(_start)\n\nSECTIONS\n{\n    . = 0x0;\n\n    .text : {\n        *(.text .text.*)\n    }\n\n    .rodata : {\n        *(.rodata .rodata.*)\n    }\n\n    .data : {\n        *(.data .data.*)\n    }\n\n    \/DISCARD\/ : {\n        *(.note .note.*)\n        *(.debug .debug.*)\n    }\n}\n","old_contents":"OUTPUT_FORMAT(\"elf64-x86-64\", \"elf64-x86-64\", \"elf64-x86-64\")\nOUTPUT_ARCH(i386:x86-64)\nENTRY(_start)\n\nSECTIONS\n{\n    . = 0x0;\n\n    .text : {\n        *(.text)\n        *(.text.*)\n    }\n\n    .rodata : {\n        *(.rodata)\n        *(.rodata.*)\n    }\n\n    .data : {\n        *(.data)\n    }\n\n    \/DISCARD\/ : {\n        *(.note.*)\n    }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"68c69572c1dec1bc411ee220322ac0e9c78bc9aa","subject":"Added libnosys.a","message":"Added libnosys.a\n","repos":"vipinbb\/nrf51x22base,vipinbb\/nrf51x22base","old_file":"gcc_nrf51_common.ld","new_file":"gcc_nrf51_common.ld","new_contents":"\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        *(.preinit_array)\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        *(SORT(.init_array.*))\n        *(.init_array)\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Library configurations *\/\nGROUP(libgcc.a libc.a libm.a)\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        *(.preinit_array)\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        *(SORT(.init_array.*))\n        *(.init_array)\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        *(SORT(.fini_array.*))\n        *(.fini_array)\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d5e5772cd434e47bd6a0618766f4e070adb82b44","subject":"Add back _end in linker. Didn't mean to remove this.","message":"Add back _end in linker. Didn't mean to remove this.\n","repos":"lancernet\/Espruino,muet\/Espruino,luetgendorf\/Espruino,nkolban\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,muet\/Espruino,luetgendorf\/Espruino,redbear\/Espruino,nkolban\/Espruino,luetgendorf\/Espruino,nkolban\/Espruino,lancernet\/Espruino,lancernet\/Espruino,redbear\/Espruino,redbear\/Espruino,redbear\/Espruino,tve\/Espruino,lancernet\/Espruino,tve\/Espruino,muet\/Espruino,muet\/Espruino,nkolban\/Espruino,tve\/Espruino,tve\/Espruino,wilberforce\/Espruino,tve\/Espruino,lancernet\/Espruino,nkolban\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,redbear\/Espruino,redbear\/Espruino,muet\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,tve\/Espruino,wilberforce\/Espruino,redbear\/Espruino,nkolban\/Espruino,lancernet\/Espruino,muet\/Espruino,nkolban\/Espruino,wilberforce\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,muet\/Espruino,tve\/Espruino","old_file":"targetlibs\/nrf5x\/nrf5x_linkers\/gcc_nrf5x_espruino_common.ld","new_file":"targetlibs\/nrf5x\/nrf5x_linkers\/gcc_nrf5x_espruino_common.ld","new_contents":"\/* Linker script for Nordic Semiconductor nRF51 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.isr_vector))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    \/* .ctors *\/\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    \/* .dtors *\/\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n    \n\n  .ARM.extab : \n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  __etext = .;\n  _etext = .;\n  _sidata = .;\n    \n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    _sdata = .;\n    *(vtable)\n    *(.data*)\n\n    . = ALIGN(4);\n    \/* preinit data *\/\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    \/* init data *\/\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n\n    . = ALIGN(4);\n    \/* finit data *\/\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    \/* All data end *\/\n    __data_end__ = .;\n    _edata = .;\n\n  } > RAM\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    _sbss = .;\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    _ebss = .;\n  } > RAM\n  \n  .heap (COPY):\n  {\n    __end__ = .;\n    PROVIDE(end = .);\n    *(.heap*)\n    __HeapLimit = .;\n  } > RAM\n\n  PROVIDE ( _end = end );\n\n  \/* .stack_dummy section doesn't contains any symbols. It is only\n   * used for linker to calculate size of stack sections, and assign\n   * values to stack symbols later *\/\n  .stack_dummy (COPY):\n  {\n    *(.stack*)\n  } > RAM\n\n  \/* Set stack top to end of RAM, and stack limit move down by\n   * size of stack_dummy section *\/\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n  _estack = __StackTop;\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n  PROVIDE(__stack = __StackTop);\n  \n  \/* Check if data + heap + stack exceeds RAM limit *\/\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for Nordic Semiconductor nRF51 devices\n *\n * Version: Sourcery G++ 4.5-1\n * Support: https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions.  No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n *\/\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.isr_vector))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    \/* .ctors *\/\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    \/* .dtors *\/\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n    \n\n  .ARM.extab : \n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  __etext = .;\n  _etext = .;\n  _sidata = .;\n    \n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    _sdata = .;\n    *(vtable)\n    *(.data*)\n\n    . = ALIGN(4);\n    \/* preinit data *\/\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    \/* init data *\/\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n\n    . = ALIGN(4);\n    \/* finit data *\/\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    \/* All data end *\/\n    __data_end__ = .;\n    _edata = .;\n\n  } > RAM\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    _sbss = .;\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    _ebss = .;\n  } > RAM\n  \n  .heap (COPY):\n  {\n    __end__ = .;\n    PROVIDE(end = .);\n    *(.heap*)\n    __HeapLimit = .;\n  } > RAM\n\n  \/* .stack_dummy section doesn't contains any symbols. It is only\n   * used for linker to calculate size of stack sections, and assign\n   * values to stack symbols later *\/\n  .stack_dummy (COPY):\n  {\n    *(.stack*)\n  } > RAM\n\n  \/* Set stack top to end of RAM, and stack limit move down by\n   * size of stack_dummy section *\/\n  __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n  _estack = __StackTop;\n  __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n  PROVIDE(__stack = __StackTop);\n  \n  \/* Check if data + heap + stack exceeds RAM limit *\/\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"25d97da7d303f348cec2943cda714822a373ca7d","subject":"soc: esp32: Fix placement for system heap","message":"soc: esp32: Fix placement for system heap\n\nSystem heap buffer was moved from dram0_0_seg to dram0_1_seg.\nThis commit fixes system heap buffer placement.\n\nSigned-off-by: Shubham Kulkarni <1478dde7897089bf180c3c690a61b19b869e8abd@espressif.com>\n","repos":"finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr","old_file":"soc\/xtensa\/esp32\/linker.ld","new_file":"soc\/xtensa\/esp32\/linker.ld","new_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef ITERABLE_SECTION_RAM_GC_ALLOWED\n#define ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef ITERABLE_SECTION_RAM\n#define ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef ITERABLE_SECTION_ROM\n#define ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    \/* Buffer for system heap should be placed in dram0_0_seg *\/\n    *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap)\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","old_contents":"\/*\n * Copyright (c) 2016 Cadence Design Systems, Inc.\n * Copyright (c) 2017 Intel Corporation\n * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Xtensa platform.\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr\n#define RAMABLE_REGION_1 dram0_1_seg :dram0_1_phdr\n#define ROMABLE_REGION drom0_0_seg :drom0_0_phdr\n#define IRAM_REGION iram0_0_seg :iram0_0_phdr\n#define FLASH_CODE_REGION irom0_0_seg :irom0_0_phdr\n\nMEMORY\n{\n  iram0_0_seg(RX): org = 0x40080000, len = 0x20000\n  irom0_0_seg(RX): org = 0x400D0020, len = 0x330000-0x20\n  \/*\n   * Following is DRAM memory split with reserved address ranges in ESP32:\n   *\n   * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)\n   * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)\n   * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)\n   * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)\n   * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)\n   *\n   * FIXME:\n   *  - Utilize available memory regions to full capacity\n   *\/\n  dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM\n  dram0_1_seg(RW): org = 0x3FFE4350, len = 0x1BCB0\n  drom0_0_seg(R): org = 0x3F400020, len = 0x400000-0x20\n  rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000\n  rtc_slow_seg(RW): org = 0x50000000, len = 0x1000\n#if defined(CONFIG_ESP_SPIRAM)\n  ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000\n#endif\n}\n\nPHDRS\n{\n  drom0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_1_phdr PT_LOAD;\n  iram0_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\/*  Default entry point:  *\/\nPROVIDE ( _ResetVector = 0x40000400 );\nENTRY(CONFIG_KERNEL_ENTRY)\n\n_rom_store_table = 0;\n\nPROVIDE(_memmap_vecbase_reset = 0x40000450);\nPROVIDE(_memmap_reset_vector = 0x40000400);\n\nSECTIONS\n{\n\n#include <linker\/rel-sections.ld>\n\n  \/* RTC fast memory holds RTC wake stub code,\n     including from any source file named rtc_wake_stub*.c\n  *\/\n  .rtc.text :\n  {\n    . = ALIGN(4);\n    *(.rtc.literal .rtc.text)\n    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)\n  } >rtc_iram_seg\n\n  \/* RTC slow memory holds RTC wake stub\n     data\/rodata, including from any source file\n     named rtc_wake_stub*.c\n  *\/\n  .rtc.data :\n  {\n    _rtc_data_start = ABSOLUTE(.);\n    *(.rtc.data)\n    *(.rtc.rodata)\n    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)\n    _rtc_data_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* RTC bss, from any source file named rtc_wake_stub*.c *\/\n  .rtc.bss (NOLOAD) :\n  {\n    _rtc_bss_start = ABSOLUTE(.);\n    *rtc_wake_stub*.o(.bss .bss.*)\n    *rtc_wake_stub*.o(COMMON)\n    _rtc_bss_end = ABSOLUTE(.);\n  } > rtc_slow_seg\n\n  \/* Send .iram0 code to iram *\/\n  .iram0.vectors : ALIGN(4)\n  {\n    \/* Vectors go to IRAM *\/\n    _init_start = ABSOLUTE(.);\n    \/* Vectors according to builds\/RF-2015.2-win32\/esp108_v1_2_s5_512int_2\/config.html *\/\n    . = 0x0;\n    KEEP(*(.WindowVectors.text));\n    . = 0x180;\n    KEEP(*(.Level2InterruptVector.text));\n    . = 0x1c0;\n    KEEP(*(.Level3InterruptVector.text));\n    . = 0x200;\n    KEEP(*(.Level4InterruptVector.text));\n    . = 0x240;\n    KEEP(*(.Level5InterruptVector.text));\n    . = 0x280;\n    KEEP(*(.DebugExceptionVector.text));\n    . = 0x2c0;\n    KEEP(*(.NMIExceptionVector.text));\n    . = 0x300;\n    KEEP(*(.KernelExceptionVector.text));\n    . = 0x340;\n    KEEP(*(.UserExceptionVector.text));\n    . = 0x3C0;\n    KEEP(*(.DoubleExceptionVector.text));\n    . = 0x400;\n    *(.*Vector.literal)\n\n    *(.UserEnter.literal);\n    *(.UserEnter.text);\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    _init_end = ABSOLUTE(.);\n\n    \/* This goes here, not at top of linker script, so addr2line finds it last,\n       and uses it in preference to the first symbol in IRAM *\/\n    _iram_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  SECTION_DATA_PROLOGUE(k_objects,, ALIGN(4))\n  {\n    Z_LINK_ITERABLE_GC_ALLOWED(k_timer);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_slab);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mem_pool);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_heap);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mutex);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_stack);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_msgq);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_mbox);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_pipe);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_sem);\n    . = ALIGN(4);\n    Z_LINK_ITERABLE_GC_ALLOWED(k_queue);\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  SECTION_DATA_PROLOGUE(net,, ALIGN(4))\n  {\n    _esp_net_buf_pool_list = .;\n    KEEP(*(SORT_BY_NAME(\"._net_buf_pool.static.*\")))\n\n#if defined(CONFIG_NETWORKING)\n    Z_LINK_ITERABLE_ALIGNED(net_if, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_if_dev, 4);\n    Z_LINK_ITERABLE_ALIGNED(net_l2, 4);\n#endif\n\n  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n  ITERABLE_SECTION_RAM(_static_thread_data, 4)\n\n#pragma push_macro(\"ITERABLE_SECTION_RAM\")\n#pragma push_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#undef ITERABLE_SECTION_RAM_GC_ALLOWED\n#define ITERABLE_SECTION_RAM_GC_ALLOWED(x, y)\n#undef ITERABLE_SECTION_RAM\n#define ITERABLE_SECTION_RAM(x, y)\n#include <linker\/common-ram.ld>\n\/* Restore original value for symbols referenced by `common-ram.ld` *\/\n_net_buf_pool_list = _esp_net_buf_pool_list;\n#pragma pop_macro(\"ITERABLE_SECTION_RAM_GC_ALLOWED\")\n#pragma pop_macro(\"ITERABLE_SECTION_RAM\")\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n\n    _btdm_data_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.data .data.*)\n    . = ALIGN (4);\n    _btdm_data_end = ABSOLUTE(.);\n\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    \/* rodata for panic handler(libarch__xtensa__core.a) and all\n     * dependent functions should be placed in DRAM to avoid issue\n     * when flash cache is disabled *\/\n    *libarch__xtensa__core.a:(.rodata .rodata.*)\n    *libkernel.a:fatal.*(.rodata .rodata.*)\n    *libkernel.a:init.*(.rodata .rodata.*)\n    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)\n    *libzephyr.a:log_core.*(.rodata .rodata.*)\n    *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)\n    *libzephyr.a:log_output.*(.rodata .rodata.*)\n    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)\n    *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)\n\n   . = ALIGN(4);\n    __esp_log_const_start = .;\n    KEEP(*(SORT(.log_const_*)));\n    __esp_log_const_end = .;\n\n    . = ALIGN(4);\n    __esp_log_backends_start = .;\n    KEEP(*(\"._log_backend.*\"));\n    __esp_log_backends_end = .;\n\n    KEEP(*(.jcr))\n    *(.dram1 .dram1.*)\n    _data_end = ABSOLUTE(.);\n    . = ALIGN(4);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n#if defined(CONFIG_ESP_SPIRAM)\n  .ext_ram.bss (NOLOAD):\n  {\n    _ext_ram_data_start = ABSOLUTE(.);\n    *(.ext_ram.bss*)\n    _ext_ram_data_end = ABSOLUTE(.) + CONFIG_ESP_SPIRAM_SIZE;\n  } > ext_ram_seg\n#endif\n\n SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(20))\n  {\n    _rodata_start = ABSOLUTE(.);\n\n#ifdef CONFIG_USERSPACE\n    Z_LINK_ITERABLE_ALIGNED(z_object_assignment, 4);\n#endif\n\n#if defined(CONFIG_NET_SOCKETS)\n    Z_LINK_ITERABLE_ALIGNED(net_socket_register, 4);\n#endif\n\n#if defined(CONFIG_NET_L2_PPP)\n    Z_LINK_ITERABLE_ALIGNED(ppp_protocol_handler, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_fixed_chan, 4);\n\n#if defined(CONFIG_BT_BREDR)\n    Z_LINK_ITERABLE_ALIGNED(bt_l2cap_br_fixed_chan, 4);\n#endif\n\n#if defined(CONFIG_BT_CONN)\n    Z_LINK_ITERABLE_ALIGNED(bt_conn_cb, 4)\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(bt_gatt_service_static, 4);\n\n#if defined(CONFIG_BT_MESH)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_subnet_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_app_key_cb, 4);\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_hb_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_FRIEND)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_friend_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_LOW_POWER)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_lpn_cb, 4);\n#endif\n\n#if defined(CONFIG_BT_MESH_PROXY)\n    Z_LINK_ITERABLE_ALIGNED(bt_mesh_proxy_cb, 4);\n#endif\n\n#if defined(CONFIG_EC_HOST_CMD)\n    Z_LINK_ITERABLE_ALIGNED(ec_host_cmd_handler, 4);\n#endif\n\n#if defined(CONFIG_SETTINGS)\n    Z_LINK_ITERABLE_ALIGNED(settings_handler_static, 4);\n#endif\n\n    Z_LINK_ITERABLE_ALIGNED(k_p4wq_initparam, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(shell, 4);\n\n    Z_LINK_ITERABLE_ALIGNED(tracing_backend, 4)\n\n    __esp_shell_root_cmds_start = .;\n    KEEP(*(SORT(.shell_root_cmd_*)));\n    __esp_shell_root_cmds_end = .;\n\n    . = ALIGN(4);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);               \/* this table MUST be 4-byte aligned *\/\n    _rodata_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(ROMABLE_REGION)\n\n#pragma push_macro(\"ITERABLE_SECTION_ROM\")\n#pragma push_macro(\"ROMABLE_REGION\")\n#undef ITERABLE_SECTION_ROM\n#define ITERABLE_SECTION_ROM(x,y)\n#undef ROMABLE_REGION\n\/* This is to workaround limitation of `esptool` which needs single `FLASH` data segment\n * which is already defined above. In case, `common-rom.ld` creates additional segments\n * they will be placed in DRAM instead. *\/\n#define ROMABLE_REGION RAMABLE_REGION\n#include <linker\/common-rom.ld>\n\/* Restore original value for symbols referenced by `common-rom.ld` *\/\n__log_const_start = __esp_log_const_start;\n__log_const_end = __esp_log_const_end;\n__log_backends_start = __esp_log_backends_start;\n__log_backends_end = __esp_log_backends_end;\n__shell_root_cmds_start = __esp_shell_root_cmds_start;\n__shell_root_cmds_end = __esp_shell_root_cmds_end;\n#pragma pop_macro(\"ROMABLE_REGION\")\n#pragma pop_macro(\"ITERABLE_SECTION_ROM\")\n\n  SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))\n  {\n    \/* Code marked as running out of IRAM *\/\n    _iram_text_start = ABSOLUTE(.);\n    *(.iram1 .iram1.*)\n    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)\n    *libesp32.a:panic.*(.literal .text .literal.* .text.*)\n    *librtc.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net__ip.a:(.literal .text .literal.* .text.*)\n    *libsubsys__net.a:(.literal .text .literal.* .text.*)\n    *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)\n    *libkernel.a:(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)\n    *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)\n    *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)\n    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)\n    *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_list.*(.literal .text .literal.* .text.*)\n    *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)\n    *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)\n    *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)\n    *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)\n    *libphy.a:( .phyiram .phyiram.*)\n    *libgcov.a:(.literal .text .literal.* .text.*)\n\n#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    _iram_text_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _iram_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(IRAM_REGION)\n\n  .flash.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n\n#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)\n    *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n    *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.*)\n#endif\n\n#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)\n    *libnet80211.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n    *libpp.a:( .wifirxiram  .wifirxiram.* .wifislprxiram .wifislprxiram.*)\n#endif\n\n    *(.literal .text .literal.* .text.*)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n\n    \/* Similar to _iram_start, this symbol goes here so it is\n       resolved by addr2line in preference to the first symbol in\n       the flash.text segment.\n    *\/\n    _flash_cache_start = ABSOLUTE(0);\n  } GROUP_LINK_IN(FLASH_CODE_REGION)\n\n  \/* Shared RAM *\/\n  SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n\n    _btdm_bss_start = ABSOLUTE(.);\n    *libbtdm_app.a:(.bss .bss.* COMMON)\n    . = ALIGN (4);\n    _btdm_bss_end = ABSOLUTE(.);\n\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.share.mem)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } GROUP_LINK_IN(RAMABLE_REGION)\n\n  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),\n          \"DRAM segment data does not fit.\")\n\n  SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)\n  {\n    . = ALIGN (8);\n    *(.noinit)\n    *(\".noinit.*\")\n    . = ALIGN (8);\n  } GROUP_LINK_IN(RAMABLE_REGION_1)\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n  SECTION_PROLOGUE(.xtensa.info, 0,)\n  {\n    *(.xtensa.info)\n  }\n\n}\n\nASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),\n          \"IRAM0 segment data does not fit.\")\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b1d1f442ccd529c6d282a91d64fa26b1186e0f35","subject":"xtensa: linker: add missing snippets-sections to ace-link.ld","message":"xtensa: linker: add missing snippets-sections to ace-link.ld\n\nThe linker script for intel_adsp ace was missing the\nsnippets-sections.ld include, causing it to ignore any custom section\ndefined in with cmake zephyr_linker_sources().\n\nAdding it in the same location as it's done in xtensa-cavs-linker.ld.\n\nSigned-off-by: Fabio Baltieri <1c55e39c05d9ab42261288cf330256b2af6ba179@google.com>\n","repos":"zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/ace\/ace-link.ld","new_file":"soc\/xtensa\/intel_adsp\/ace\/ace-link.ld","new_contents":"\/*\n * Copyright (c) 2022 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <zephyr\/devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <zephyr\/linker\/sections.h>\n#include <adsp-vectors.h>\n#include <adsp_memory.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n    _imr_end = .;\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int4_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int4_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    __rodata_region_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_ram_start = .;\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    __rodata_region_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.initcall)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <zephyr\/linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    __data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    __data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <zephyr\/linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n     _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n\n  \/* Heap start and end markers. Used to reserve system heap memory. *\/\n  .heap_mem SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _heap_start = .;\n    *(.heap_mem)\n    _heap_end = .;\n  } >ucram\n\n  .unused_ram_start_marker SEGSTART_CACHED (NOLOAD) :\n  {\n    . = ALIGN(4096);\n    _unused_ram_start_marker = .;\n    *(.unused_ram_start_marker)\n    *(.unused_ram_start_marker.*)\n  } >ram\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n    _image_ram_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n   \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2022 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <zephyr\/devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <zephyr\/linker\/sections.h>\n#include <adsp-vectors.h>\n#include <adsp_memory.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n    _imr_end = .;\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int4_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int4_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    __rodata_region_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _image_ram_start = .;\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    __rodata_region_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.initcall)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <zephyr\/linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    __data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    __data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <zephyr\/linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n     _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n\n  \/* Heap start and end markers. Used to reserve system heap memory. *\/\n  .heap_mem SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _heap_start = .;\n    *(.heap_mem)\n    _heap_end = .;\n  } >ucram\n\n  .unused_ram_start_marker SEGSTART_CACHED (NOLOAD) :\n  {\n    . = ALIGN(4096);\n    _unused_ram_start_marker = .;\n    *(.unused_ram_start_marker)\n    *(.unused_ram_start_marker.*)\n  } >ram\n\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n    _image_ram_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n   \/DISCARD\/ : { *(.note.GNU-stack) }\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <zephyr\/linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f63dfce4bbaef4e197c432439f221f143ff08044","subject":"modification to .ld to improve memory","message":"modification to .ld to improve memory\n","repos":"kjbracey-arm\/mbed,ryankurte\/mbed-os,mazimkhan\/mbed-os,karsev\/mbed-os,andcor02\/mbed-os,Archcady\/mbed-os,mbedmicro\/mbed,betzw\/mbed-os,c1728p9\/mbed-os,Archcady\/mbed-os,mbedmicro\/mbed,andcor02\/mbed-os,infinnovation\/mbed-os,ryankurte\/mbed-os,kjbracey-arm\/mbed,ryankurte\/mbed-os,HeadsUpDisplayInc\/mbed,betzw\/mbed-os,HeadsUpDisplayInc\/mbed,karsev\/mbed-os,betzw\/mbed-os,infinnovation\/mbed-os,c1728p9\/mbed-os,infinnovation\/mbed-os,mazimkhan\/mbed-os,CalSol\/mbed,kjbracey-arm\/mbed,c1728p9\/mbed-os,ryankurte\/mbed-os,betzw\/mbed-os,kjbracey-arm\/mbed,karsev\/mbed-os,ryankurte\/mbed-os,c1728p9\/mbed-os,mazimkhan\/mbed-os,CalSol\/mbed,mazimkhan\/mbed-os,andcor02\/mbed-os,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,mbedmicro\/mbed,andcor02\/mbed-os,betzw\/mbed-os,mbedmicro\/mbed,ryankurte\/mbed-os,CalSol\/mbed,karsev\/mbed-os,CalSol\/mbed,CalSol\/mbed,karsev\/mbed-os,HeadsUpDisplayInc\/mbed,infinnovation\/mbed-os,Archcady\/mbed-os,Archcady\/mbed-os,CalSol\/mbed,andcor02\/mbed-os,Archcady\/mbed-os,mazimkhan\/mbed-os,mbedmicro\/mbed,mazimkhan\/mbed-os,HeadsUpDisplayInc\/mbed,karsev\/mbed-os,c1728p9\/mbed-os,infinnovation\/mbed-os,Archcady\/mbed-os,HeadsUpDisplayInc\/mbed,andcor02\/mbed-os,betzw\/mbed-os,infinnovation\/mbed-os","old_file":"targets\/TARGET_STM\/TARGET_STM32L4\/TARGET_STM32L476xG\/TARGET_SILICA_SENSOR_NODE\/device\/TOOLCHAIN_GCC_ARM\/STM32L476XX.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32L4\/TARGET_STM32L476xG\/TARGET_SILICA_SENSOR_NODE\/device\/TOOLCHAIN_GCC_ARM\/STM32L476XX.ld","new_contents":"#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 1024k\n#endif\n\nSTACK_SIZE = 0x400;\nHEAP_SIZE = 0x7800;\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188\n  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .mesh_heap (COPY):\n    {\n        *(mesh_heap*)\n    } > SRAM2\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > SRAM1\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > SRAM1\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        . += HEAP_SIZE;\n        __HeapLimit = .;\n    } > SRAM1\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SRAM1\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - STACK_SIZE;\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"#if !defined(MBED_APP_START)\n  #define MBED_APP_START 0x08000000\n#endif\n\n#if !defined(MBED_APP_SIZE)\n  #define MBED_APP_SIZE 1024k\n#endif\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE\n  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 32k - 0x188\n  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 96k\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > SRAM1\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > SRAM1\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > SRAM1\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > SRAM1\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"67a51f9a9efa8e29b1bc12aaab444b9f60638bdc","subject":"quark_d2000: fix IDT_LIST definition","message":"quark_d2000: fix IDT_LIST definition\n\nThis should be the same size as other x86 boards.\n\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"nashif\/zephyr,zephyriot\/zephyr,mbolivar\/zephyr,ldts\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,zephyriot\/zephyr,galak\/zephyr,mbolivar\/zephyr,zephyrproject-rtos\/zephyr,GiulianoFranchetto\/zephyr,runchip\/zephyr-cc3220,kraj\/zephyr,kraj\/zephyr,Vudentz\/zephyr,runchip\/zephyr-cc3220,nashif\/zephyr,GiulianoFranchetto\/zephyr,explora26\/zephyr,punitvara\/zephyr,ldts\/zephyr,zephyriot\/zephyr,finikorg\/zephyr,aceofall\/zephyr-iotos,fbsder\/zephyr,galak\/zephyr,fbsder\/zephyr,zephyrproject-rtos\/zephyr,mbolivar\/zephyr,fbsder\/zephyr,runchip\/zephyr-cc3220,punitvara\/zephyr,nashif\/zephyr,rsalveti\/zephyr,galak\/zephyr,finikorg\/zephyr,punitvara\/zephyr,fbsder\/zephyr,nashif\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,finikorg\/zephyr,explora26\/zephyr,ldts\/zephyr,aceofall\/zephyr-iotos,zephyriot\/zephyr,rsalveti\/zephyr,aceofall\/zephyr-iotos,explora26\/zephyr,ldts\/zephyr,nashif\/zephyr,fbsder\/zephyr,punitvara\/zephyr,explora26\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,kraj\/zephyr,mbolivar\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,rsalveti\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,GiulianoFranchetto\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,kraj\/zephyr,ldts\/zephyr,galak\/zephyr,rsalveti\/zephyr,punitvara\/zephyr,finikorg\/zephyr,galak\/zephyr,Vudentz\/zephyr,aceofall\/zephyr-iotos,explora26\/zephyr,aceofall\/zephyr-iotos,mbolivar\/zephyr,runchip\/zephyr-cc3220,runchip\/zephyr-cc3220,rsalveti\/zephyr","old_file":"arch\/x86\/soc\/intel_quark\/quark_d2000\/linker.ld","new_file":"arch\/x86\/soc\/intel_quark\/quark_d2000\/linker.ld","new_contents":"\/*\n * Copyright (c) 2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * This is the linker script for both standard images and XIP images.\n *\/\n\n#include <autoconf.h>\n\n#include <generated_dts_board.h>\n\/* physical address of RAM (needed for correct __ram_phys_end symbol) *\/\n#define PHYS_RAM_ADDR    CONFIG_PHYS_RAM_ADDR\n\n\/* physical address where the kernel is loaded *\/\n#ifdef CONFIG_XIP\n  #define PHYS_LOAD_ADDR   CONFIG_PHYS_LOAD_ADDR\n#else  \/* !CONFIG_XIP *\/\n  #define PHYS_LOAD_ADDR   CONFIG_PHYS_RAM_ADDR\n#endif \/* CONFIG_XIP *\/\n\n#ifdef CONFIG_SET_GDT\n#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K\n#else \/* !CONFIG_SET_GDT *\/\n#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K - CONFIG_BSP_SHARED_GDT_RAM_SIZE\n#endif\n\nMEMORY\n    {\n#ifdef CONFIG_XIP\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K\n    RAM (wx)        : ORIGIN = PHYS_RAM_ADDR, LENGTH =  PHYS_RAM_SIZE\n#else  \/* !CONFIG_XIP *\/\n    RAM (wx)\t    : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_SIZE\n#endif \/* CONFIG_XIP *\/\n#ifndef CONFIG_SET_GDT\n    BSP_SHARED_GDT_RAM (rw) : ORIGIN = CONFIG_BSP_SHARED_GDT_RAM_ADDR,\n                              LENGTH = CONFIG_BSP_SHARED_GDT_RAM_SIZE\n#endif \/* !CONFIG_SET_GDT *\/\n\n    \/*\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 0, LENGTH = 2K\n    }\n\n#include <arch\/x86\/linker.ld>\n\n","old_contents":"\/*\n * Copyright (c) 2015 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * This is the linker script for both standard images and XIP images.\n *\/\n\n#include <autoconf.h>\n\n#include <generated_dts_board.h>\n\/* physical address of RAM (needed for correct __ram_phys_end symbol) *\/\n#define PHYS_RAM_ADDR    CONFIG_PHYS_RAM_ADDR\n\n\/* physical address where the kernel is loaded *\/\n#ifdef CONFIG_XIP\n  #define PHYS_LOAD_ADDR   CONFIG_PHYS_LOAD_ADDR\n#else  \/* !CONFIG_XIP *\/\n  #define PHYS_LOAD_ADDR   CONFIG_PHYS_RAM_ADDR\n#endif \/* CONFIG_XIP *\/\n\n#ifdef CONFIG_SET_GDT\n#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K\n#else \/* !CONFIG_SET_GDT *\/\n#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K - CONFIG_BSP_SHARED_GDT_RAM_SIZE\n#endif\n\nMEMORY\n    {\n#ifdef CONFIG_XIP\n    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K\n    RAM (wx)        : ORIGIN = PHYS_RAM_ADDR, LENGTH =  PHYS_RAM_SIZE\n#else  \/* !CONFIG_XIP *\/\n    RAM (wx)\t    : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_SIZE\n#endif \/* CONFIG_XIP *\/\n#ifndef CONFIG_SET_GDT\n    BSP_SHARED_GDT_RAM (rw) : ORIGIN = CONFIG_BSP_SHARED_GDT_RAM_ADDR,\n                              LENGTH = CONFIG_BSP_SHARED_GDT_RAM_SIZE\n#endif \/* !CONFIG_SET_GDT *\/\n\n    \/*\n     * It doesn't matter where this region goes as it is stripped from the\n     * final ELF image. The address doesn't even have to be valid on the\n     * target. However, it shouldn't overlap any other regions.\n     *\/\n\n    IDT_LIST        : ORIGIN = 512, LENGTH = 512\n    }\n\n#include <arch\/x86\/linker.ld>\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e222c1e6ac586ddb4d0163cd70d96ac0f760f487","subject":"Group .sdata input sections into the .sdata output section","message":"Group .sdata input sections into the .sdata output section\n","repos":"majenkotech\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,adamwolf\/chipKIT-core,pontech\/chipKIT-core,chipKIT32\/chipkit-core,chipKIT32\/chipkit-core,majenkotech\/chipKIT-core,EmbeddedMan\/chipKIT-core,chipKIT32\/chipkit-core,ricklon\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,pontech\/chipKIT-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core,majenkotech\/chipKIT-core,ricklon\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,majenkotech\/chipKIT-core,chipKIT32\/chipkit-core,ricklon\/chipKIT-core,adamwolf\/chipKIT-core,adamwolf\/chipKIT-core,adamwolf\/chipKIT-core,pontech\/chipKIT-core,ricklon\/chipKIT-core,chipKIT32\/chipkit-core,EmbeddedMan\/chipKIT-core,adamwolf\/chipKIT-core","old_file":"pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_file":"pic32\/cores\/pic32\/chipKIT-application-COMMON.ld","new_contents":"\/************************************************************************\n *\tchipKIT-applicaiton-COMMON.ld\n *\n *\tThis is the common part of the linker script shared\n *\tacross all chipKIT PIC32 processors \/ boards.\n *\n ************************************************************************\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\n * \tThis library is free software; you can redistribute it and\/or\n *  modify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tThis library is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General\n *\tPublic License along with this library; if not, write to the\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\n *\tBoston, MA\t02111-1307\tUSA\n *\n *\n ************************************************************************\n *\tEdit History\n ************************************************************************\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\n ************************************************************************\n *\/\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\nINPUT(\"crtbegin.o\")\nINPUT(\"crtend.o\")\nINPUT(\"crtn.o\")\nOPTIONAL(\"libmchp_peripheral.a\")\n\n\/*************************************************************************\n * Start the layout of memory, the sections...\n *************************************************************************\/\n\nSECTIONS\n{\n  \/* Don't allow config-fuse sections in an application sketch *\/\n  \/DISCARD\/ : { *(.config_*) }\n}\n\nSECTIONS\n{\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\n  {\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n .image_ptr_table _IMAGE_PTR_TABLE :\n  {\n    LONG(_ebase_address)\n    LONG(_image_header_info)\n  } > exception_mem\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n\n  .vector_0 _ebase_address + 0x200 :\n  {\n    _new_vector_0 = . ;\n\tKEEP(*(.vector_new_0))\n    _original_vector_0 = . ;\n\tKEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_new_1))\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_new_2))\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_new_3))\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_new_4))\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_new_5))\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_new_6))\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_new_7))\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_new_8))\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_new_9))\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_new_10))\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_new_11))\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_new_12))\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_new_13))\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_new_14))\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_new_15))\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_new_16))\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_new_17))\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_new_18))\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_new_19))\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_new_20))\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_new_21))\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_new_22))\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_new_23))\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_new_24))\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_new_25))\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_new_26))\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_new_27))\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_new_28))\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_new_29))\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_new_30))\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_new_31))\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_new_32))\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_new_33))\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_new_34))\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_new_35))\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_new_36))\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_new_37))\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_new_38))\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_new_39))\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_new_40))\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_new_41))\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_new_42))\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_new_43))\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_new_44))\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_new_45))\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_new_46))\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_new_47))\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_new_48))\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_new_49))\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_new_50))\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_new_51))\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_new_52))\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_new_53))\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_new_54))\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_new_55))\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_new_56))\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_new_57))\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_new_58))\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_new_59))\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_new_60))\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_new_61))\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_new_62))\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_new_63))\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.stub .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n    *(.gnu.warning)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n    . = ALIGN(4) ;\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  \/* Read-only sections *\/\n  .header_info ALIGN(4) :\n  {\n    _image_header_info = . ;\n    LONG(SIZEOF(.header_info))                 \/* size of this structure       *\/\n    LONG(0xFFFFFFFF)                           \/* bootloader version           *\/\n    KEEP(*(.mpide_version *.mpide_version.*))  \/* MPIDE build version          *\/\n    LONG(0xFFFFFFFF)                           \/* booloader capabilities       *\/\n    LONG(0xFFFFFFFF)                           \/* VID and PID                  *\/\n    LONG(_IMAGE_TYPE)                          \/* image type and options       *\/\n    LONG(_JUMP_ADDR)                           \/* image execution address      *\/\n    LONG(_ebase_address)                       \/* image base address           *\/\n    LONG(_IMAGE_FLASH_SIZE)                    \/* size of image flash used     *\/\n    LONG(ORIGIN(kseg0_eeprom_mem))             \/* eeprom location              *\/\n    LONG(LENGTH(kseg0_eeprom_mem))             \/* eeprom size                  *\/\n    LONG(ORIGIN(configsfrs))                   \/* config bits location         *\/\n    LONG(LENGTH(configsfrs))                   \/* config bits size             *\/\n    LONG(_ram_header_addr)                     \/* ram header pointer           *\/\n    LONG(SIZEOF(.ram_exchange_data))           \/* ram Header size              *\/\n    LONG(0xFFFFFFFF)                           \/* what the bootloader skips    *\/\n    LONG(_original_vector_0)                   \/* the original vector 0        *\/\n    LONG(_new_vector_0)                        \/* new\/indirect vector 0        *\/\n    LONG(_vector_spacing << 5)                 \/* spacing of both org\/new vec  *\/\n    _image_header_info_end = . ;\n  } > kseg0_program_mem\n  ASSERT (SIZEOF(.header_info) == 76, \"MPIDE Version not specfied correctly\")\n\n  .rodata  ALIGN(4) :\n  {\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n\n  .ram_exchange_data (NOLOAD) :\n  {\n    _ram_header_addr = . ;\n    . += 8 ;\n  } >kseg1_data_mem\n\n  \/* Persistent data - Use the new C 'persistent' attribute instead. *\/\n  .persist ALIGN(4) (NOLOAD) :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4) ;\n    _persist_end = .;\n  } >kseg1_data_mem\n\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\n\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\n\n  .protected_bootloader ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : 0x0);\n  }\n\n  \/*\n   *  Note that input sections named .data* are not mapped here.\n   *  The best-fit allocator locates them, so that they may flow\n   *  around absolute sections as needed.\n   *\/\n  .data :\n  {\n    _data_begin = . ;\n    *( .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  _data_image_begin = LOADADDR(.data) ;\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4) :\n  {\n    _sdata_begin = . ;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    . = ALIGN(4) ;\n    _sdata_end = . ;\n  } >kseg1_data_mem\n  .lit8           :\n  {\n    *(.lit8)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem\n\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n\n  .sbss ALIGN(4) :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    . = ALIGN(4) ;\n    _sbss_end = . ;\n  } >kseg1_data_mem\n\n  .bss   :\n  {\n    *(.dynbss)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n\n  \/*\n   *  The heap and stack are best-fit allocated by the linker after other\n   *  data and bss sections have been allocated.\n   *\/\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\n   * RAM functions are now allocated by the linker. The linker generates\n   * _ramfunc_begin and _bmxdkpba_address symbols depending on the\n   * location of RAM functions.\n   *\/\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n\n    \/* The .pdr section belongs in the absolute section *\/\n\n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n\n  .gcc_compiled_long32 : { KEEP(*(.gcc_compiled_long32)) }\n  .gcc_compiled_long64 : { KEEP(*(.gcc_compiled_long64)) }\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0  : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) *(.discard) }\n}\n","old_contents":"\/************************************************************************\n *\tchipKIT-applicaiton-COMMON.ld\n *\t\n *\tThis is the common part of the linker script shared\n *\tacross all chipKIT PIC32 processors \/ boards.\n *\t\n ************************************************************************\n *\tthis code is based on code Copyright (c) 2005-2006 David A. Mellis\n * \tThis library is free software; you can redistribute it and\/or\n *  modify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\t\n *\tThis library is distributed in the hope that it will be useful,\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\/\/*\tSee the GNU\n *\tLesser General Public License for more details.\n *\t\n *\tYou should have received a copy of the GNU Lesser General\n *\tPublic License along with this library; if not, write to the\n *\tFree Software Foundation, Inc., 59 Temple Place, Suite 330,\n *\tBoston, MA\t02111-1307\tUSA\n *\t\n *\t\n ************************************************************************\n *\tEdit History\n ************************************************************************\n *\tJun 30 2012 <Keith Vogel, Digilent> Extracted the common section of the linker script\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a flash header section\n *\tJun 30 2012 <Keith Vogel, Digilent> Created a RAM header section\n ************************************************************************\n *\/\n\n\/*************************************************************************\n * For interrupt vector handling\n *************************************************************************\/\nPROVIDE(_vector_spacing = 0x00000001);\nINPUT(\"crtbegin.o\")\nINPUT(\"crtend.o\")\nINPUT(\"crtn.o\")\nOPTIONAL(\"libmchp_peripheral.a\") \n\n\/*************************************************************************\n * Start the layout of memory, the sections...\n *************************************************************************\/\n\nSECTIONS\n{\n  \/* Don't allow config-fuse sections in an application sketch *\/\n  \/DISCARD\/ : { *(.config_*) }\n}\n\nSECTIONS\n{\n  .eeprom_pic32 _EEPROM_ADDR (NOLOAD):\n  {\n    KEEP(*(.eeprom_pic32 .eeprom_pic32.*))\n  } > kseg0_eeprom_mem\n\n  \/DISCARD\/ : { *(.bev_handler) }\n\n .image_ptr_table _IMAGE_PTR_TABLE :\n  {\n    LONG(_ebase_address)\t\n    LONG(_image_header_info)\n  } > exception_mem\n\n  .app_excpt _GEN_EXCPT_ADDR :\n  {\n    KEEP(*(.gen_handler))\n  } > exception_mem\n\n  .vector_0 _ebase_address + 0x200 :\n  {\n    _new_vector_0 = . ;\n\tKEEP(*(.vector_new_0))\n    _original_vector_0 = . ;\n\tKEEP(*(.vector_0))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_0) <= (_vector_spacing << 5), \"function at exception vector 0 too large\")\n  .vector_1 _ebase_address + 0x200 + (_vector_spacing << 5) * 1 :\n  {\n    KEEP(*(.vector_new_1))\n    KEEP(*(.vector_1))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_1) <= (_vector_spacing << 5), \"function at exception vector 1 too large\")\n  .vector_2 _ebase_address + 0x200 + (_vector_spacing << 5) * 2 :\n  {\n    KEEP(*(.vector_new_2))\n    KEEP(*(.vector_2))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_2) <= (_vector_spacing << 5), \"function at exception vector 2 too large\")\n  .vector_3 _ebase_address + 0x200 + (_vector_spacing << 5) * 3 :\n  {\n    KEEP(*(.vector_new_3))\n    KEEP(*(.vector_3))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_3) <= (_vector_spacing << 5), \"function at exception vector 3 too large\")\n  .vector_4 _ebase_address + 0x200 + (_vector_spacing << 5) * 4 :\n  {\n    KEEP(*(.vector_new_4))\n    KEEP(*(.vector_4))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_4) <= (_vector_spacing << 5), \"function at exception vector 4 too large\")\n  .vector_5 _ebase_address + 0x200 + (_vector_spacing << 5) * 5 :\n  {\n    KEEP(*(.vector_new_5))\n    KEEP(*(.vector_5))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_5) <= (_vector_spacing << 5), \"function at exception vector 5 too large\")\n  .vector_6 _ebase_address + 0x200 + (_vector_spacing << 5) * 6 :\n  {\n    KEEP(*(.vector_new_6))\n    KEEP(*(.vector_6))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_6) <= (_vector_spacing << 5), \"function at exception vector 6 too large\")\n  .vector_7 _ebase_address + 0x200 + (_vector_spacing << 5) * 7 :\n  {\n    KEEP(*(.vector_new_7))\n    KEEP(*(.vector_7))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_7) <= (_vector_spacing << 5), \"function at exception vector 7 too large\")\n  .vector_8 _ebase_address + 0x200 + (_vector_spacing << 5) * 8 :\n  {\n    KEEP(*(.vector_new_8))\n    KEEP(*(.vector_8))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_8) <= (_vector_spacing << 5), \"function at exception vector 8 too large\")\n  .vector_9 _ebase_address + 0x200 + (_vector_spacing << 5) * 9 :\n  {\n    KEEP(*(.vector_new_9))\n    KEEP(*(.vector_9))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_9) <= (_vector_spacing << 5), \"function at exception vector 9 too large\")\n  .vector_10 _ebase_address + 0x200 + (_vector_spacing << 5) * 10 :\n  {\n    KEEP(*(.vector_new_10))\n    KEEP(*(.vector_10))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_10) <= (_vector_spacing << 5), \"function at exception vector 10 too large\")\n  .vector_11 _ebase_address + 0x200 + (_vector_spacing << 5) * 11 :\n  {\n    KEEP(*(.vector_new_11))\n    KEEP(*(.vector_11))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_11) <= (_vector_spacing << 5), \"function at exception vector 11 too large\")\n  .vector_12 _ebase_address + 0x200 + (_vector_spacing << 5) * 12 :\n  {\n    KEEP(*(.vector_new_12))\n    KEEP(*(.vector_12))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_12) <= (_vector_spacing << 5), \"function at exception vector 12 too large\")\n  .vector_13 _ebase_address + 0x200 + (_vector_spacing << 5) * 13 :\n  {\n    KEEP(*(.vector_new_13))\n    KEEP(*(.vector_13))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_13) <= (_vector_spacing << 5), \"function at exception vector 13 too large\")\n  .vector_14 _ebase_address + 0x200 + (_vector_spacing << 5) * 14 :\n  {\n    KEEP(*(.vector_new_14))\n    KEEP(*(.vector_14))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_14) <= (_vector_spacing << 5), \"function at exception vector 14 too large\")\n  .vector_15 _ebase_address + 0x200 + (_vector_spacing << 5) * 15 :\n  {\n    KEEP(*(.vector_new_15))\n    KEEP(*(.vector_15))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_15) <= (_vector_spacing << 5), \"function at exception vector 15 too large\")\n  .vector_16 _ebase_address + 0x200 + (_vector_spacing << 5) * 16 :\n  {\n    KEEP(*(.vector_new_16))\n    KEEP(*(.vector_16))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_16) <= (_vector_spacing << 5), \"function at exception vector 16 too large\")\n  .vector_17 _ebase_address + 0x200 + (_vector_spacing << 5) * 17 :\n  {\n    KEEP(*(.vector_new_17))\n    KEEP(*(.vector_17))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_17) <= (_vector_spacing << 5), \"function at exception vector 17 too large\")\n  .vector_18 _ebase_address + 0x200 + (_vector_spacing << 5) * 18 :\n  {\n    KEEP(*(.vector_new_18))\n    KEEP(*(.vector_18))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_18) <= (_vector_spacing << 5), \"function at exception vector 18 too large\")\n  .vector_19 _ebase_address + 0x200 + (_vector_spacing << 5) * 19 :\n  {\n    KEEP(*(.vector_new_19))\n    KEEP(*(.vector_19))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_19) <= (_vector_spacing << 5), \"function at exception vector 19 too large\")\n  .vector_20 _ebase_address + 0x200 + (_vector_spacing << 5) * 20 :\n  {\n    KEEP(*(.vector_new_20))\n    KEEP(*(.vector_20))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_20) <= (_vector_spacing << 5), \"function at exception vector 20 too large\")\n  .vector_21 _ebase_address + 0x200 + (_vector_spacing << 5) * 21 :\n  {\n    KEEP(*(.vector_new_21))\n    KEEP(*(.vector_21))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_21) <= (_vector_spacing << 5), \"function at exception vector 21 too large\")\n  .vector_22 _ebase_address + 0x200 + (_vector_spacing << 5) * 22 :\n  {\n    KEEP(*(.vector_new_22))\n    KEEP(*(.vector_22))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_22) <= (_vector_spacing << 5), \"function at exception vector 22 too large\")\n  .vector_23 _ebase_address + 0x200 + (_vector_spacing << 5) * 23 :\n  {\n    KEEP(*(.vector_new_23))\n    KEEP(*(.vector_23))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_23) <= (_vector_spacing << 5), \"function at exception vector 23 too large\")\n  .vector_24 _ebase_address + 0x200 + (_vector_spacing << 5) * 24 :\n  {\n    KEEP(*(.vector_new_24))\n    KEEP(*(.vector_24))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_24) <= (_vector_spacing << 5), \"function at exception vector 24 too large\")\n  .vector_25 _ebase_address + 0x200 + (_vector_spacing << 5) * 25 :\n  {\n    KEEP(*(.vector_new_25))\n    KEEP(*(.vector_25))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_25) <= (_vector_spacing << 5), \"function at exception vector 25 too large\")\n  .vector_26 _ebase_address + 0x200 + (_vector_spacing << 5) * 26 :\n  {\n    KEEP(*(.vector_new_26))\n    KEEP(*(.vector_26))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_26) <= (_vector_spacing << 5), \"function at exception vector 26 too large\")\n  .vector_27 _ebase_address + 0x200 + (_vector_spacing << 5) * 27 :\n  {\n    KEEP(*(.vector_new_27))\n    KEEP(*(.vector_27))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_27) <= (_vector_spacing << 5), \"function at exception vector 27 too large\")\n  .vector_28 _ebase_address + 0x200 + (_vector_spacing << 5) * 28 :\n  {\n    KEEP(*(.vector_new_28))\n    KEEP(*(.vector_28))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_28) <= (_vector_spacing << 5), \"function at exception vector 28 too large\")\n  .vector_29 _ebase_address + 0x200 + (_vector_spacing << 5) * 29 :\n  {\n    KEEP(*(.vector_new_29))\n    KEEP(*(.vector_29))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_29) <= (_vector_spacing << 5), \"function at exception vector 29 too large\")\n  .vector_30 _ebase_address + 0x200 + (_vector_spacing << 5) * 30 :\n  {\n    KEEP(*(.vector_new_30))\n    KEEP(*(.vector_30))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_30) <= (_vector_spacing << 5), \"function at exception vector 30 too large\")\n  .vector_31 _ebase_address + 0x200 + (_vector_spacing << 5) * 31 :\n  {\n    KEEP(*(.vector_new_31))\n    KEEP(*(.vector_31))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_31) <= (_vector_spacing << 5), \"function at exception vector 31 too large\")\n  .vector_32 _ebase_address + 0x200 + (_vector_spacing << 5) * 32 :\n  {\n    KEEP(*(.vector_new_32))\n    KEEP(*(.vector_32))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_32) <= (_vector_spacing << 5), \"function at exception vector 32 too large\")\n  .vector_33 _ebase_address + 0x200 + (_vector_spacing << 5) * 33 :\n  {\n    KEEP(*(.vector_new_33))\n    KEEP(*(.vector_33))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_33) <= (_vector_spacing << 5), \"function at exception vector 33 too large\")\n  .vector_34 _ebase_address + 0x200 + (_vector_spacing << 5) * 34 :\n  {\n    KEEP(*(.vector_new_34))\n    KEEP(*(.vector_34))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_34) <= (_vector_spacing << 5), \"function at exception vector 34 too large\")\n  .vector_35 _ebase_address + 0x200 + (_vector_spacing << 5) * 35 :\n  {\n    KEEP(*(.vector_new_35))\n    KEEP(*(.vector_35))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_35) <= (_vector_spacing << 5), \"function at exception vector 35 too large\")\n  .vector_36 _ebase_address + 0x200 + (_vector_spacing << 5) * 36 :\n  {\n    KEEP(*(.vector_new_36))\n    KEEP(*(.vector_36))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_36) <= (_vector_spacing << 5), \"function at exception vector 36 too large\")\n  .vector_37 _ebase_address + 0x200 + (_vector_spacing << 5) * 37 :\n  {\n    KEEP(*(.vector_new_37))\n    KEEP(*(.vector_37))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_37) <= (_vector_spacing << 5), \"function at exception vector 37 too large\")\n  .vector_38 _ebase_address + 0x200 + (_vector_spacing << 5) * 38 :\n  {\n    KEEP(*(.vector_new_38))\n    KEEP(*(.vector_38))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_38) <= (_vector_spacing << 5), \"function at exception vector 38 too large\")\n  .vector_39 _ebase_address + 0x200 + (_vector_spacing << 5) * 39 :\n  {\n    KEEP(*(.vector_new_39))\n    KEEP(*(.vector_39))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_39) <= (_vector_spacing << 5), \"function at exception vector 39 too large\")\n  .vector_40 _ebase_address + 0x200 + (_vector_spacing << 5) * 40 :\n  {\n    KEEP(*(.vector_new_40))\n    KEEP(*(.vector_40))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_40) <= (_vector_spacing << 5), \"function at exception vector 40 too large\")\n  .vector_41 _ebase_address + 0x200 + (_vector_spacing << 5) * 41 :\n  {\n    KEEP(*(.vector_new_41))\n    KEEP(*(.vector_41))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_41) <= (_vector_spacing << 5), \"function at exception vector 41 too large\")\n  .vector_42 _ebase_address + 0x200 + (_vector_spacing << 5) * 42 :\n  {\n    KEEP(*(.vector_new_42))\n    KEEP(*(.vector_42))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_42) <= (_vector_spacing << 5), \"function at exception vector 42 too large\")\n  .vector_43 _ebase_address + 0x200 + (_vector_spacing << 5) * 43 :\n  {\n    KEEP(*(.vector_new_43))\n    KEEP(*(.vector_43))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_43) <= (_vector_spacing << 5), \"function at exception vector 43 too large\")\n  .vector_44 _ebase_address + 0x200 + (_vector_spacing << 5) * 44 :\n  {\n    KEEP(*(.vector_new_44))\n    KEEP(*(.vector_44))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_44) <= (_vector_spacing << 5), \"function at exception vector 44 too large\")\n  .vector_45 _ebase_address + 0x200 + (_vector_spacing << 5) * 45 :\n  {\n    KEEP(*(.vector_new_45))\n    KEEP(*(.vector_45))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_45) <= (_vector_spacing << 5), \"function at exception vector 45 too large\")\n  .vector_46 _ebase_address + 0x200 + (_vector_spacing << 5) * 46 :\n  {\n    KEEP(*(.vector_new_46))\n    KEEP(*(.vector_46))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_46) <= (_vector_spacing << 5), \"function at exception vector 46 too large\")\n  .vector_47 _ebase_address + 0x200 + (_vector_spacing << 5) * 47 :\n  {\n    KEEP(*(.vector_new_47))\n    KEEP(*(.vector_47))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_47) <= (_vector_spacing << 5), \"function at exception vector 47 too large\")\n  .vector_48 _ebase_address + 0x200 + (_vector_spacing << 5) * 48 :\n  {\n    KEEP(*(.vector_new_48))\n    KEEP(*(.vector_48))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_48) <= (_vector_spacing << 5), \"function at exception vector 48 too large\")\n  .vector_49 _ebase_address + 0x200 + (_vector_spacing << 5) * 49 :\n  {\n    KEEP(*(.vector_new_49))\n    KEEP(*(.vector_49))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_49) <= (_vector_spacing << 5), \"function at exception vector 49 too large\")\n  .vector_50 _ebase_address + 0x200 + (_vector_spacing << 5) * 50 :\n  {\n    KEEP(*(.vector_new_50))\n    KEEP(*(.vector_50))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_50) <= (_vector_spacing << 5), \"function at exception vector 50 too large\")\n  .vector_51 _ebase_address + 0x200 + (_vector_spacing << 5) * 51 :\n  {\n    KEEP(*(.vector_new_51))\n    KEEP(*(.vector_51))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_51) <= (_vector_spacing << 5), \"function at exception vector 51 too large\")\n  .vector_52 _ebase_address + 0x200 + (_vector_spacing << 5) * 52 :\n  {\n    KEEP(*(.vector_new_52))\n    KEEP(*(.vector_52))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_52) <= (_vector_spacing << 5), \"function at exception vector 52 too large\")\n  .vector_53 _ebase_address + 0x200 + (_vector_spacing << 5) * 53 :\n  {\n    KEEP(*(.vector_new_53))\n    KEEP(*(.vector_53))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_53) <= (_vector_spacing << 5), \"function at exception vector 53 too large\")\n  .vector_54 _ebase_address + 0x200 + (_vector_spacing << 5) * 54 :\n  {\n    KEEP(*(.vector_new_54))\n    KEEP(*(.vector_54))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_54) <= (_vector_spacing << 5), \"function at exception vector 54 too large\")\n  .vector_55 _ebase_address + 0x200 + (_vector_spacing << 5) * 55 :\n  {\n    KEEP(*(.vector_new_55))\n    KEEP(*(.vector_55))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_55) <= (_vector_spacing << 5), \"function at exception vector 55 too large\")\n  .vector_56 _ebase_address + 0x200 + (_vector_spacing << 5) * 56 :\n  {\n    KEEP(*(.vector_new_56))\n    KEEP(*(.vector_56))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_56) <= (_vector_spacing << 5), \"function at exception vector 56 too large\")\n  .vector_57 _ebase_address + 0x200 + (_vector_spacing << 5) * 57 :\n  {\n    KEEP(*(.vector_new_57))\n    KEEP(*(.vector_57))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_57) <= (_vector_spacing << 5), \"function at exception vector 57 too large\")\n  .vector_58 _ebase_address + 0x200 + (_vector_spacing << 5) * 58 :\n  {\n    KEEP(*(.vector_new_58))\n    KEEP(*(.vector_58))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_58) <= (_vector_spacing << 5), \"function at exception vector 58 too large\")\n  .vector_59 _ebase_address + 0x200 + (_vector_spacing << 5) * 59 :\n  {\n    KEEP(*(.vector_new_59))\n    KEEP(*(.vector_59))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_59) <= (_vector_spacing << 5), \"function at exception vector 59 too large\")\n  .vector_60 _ebase_address + 0x200 + (_vector_spacing << 5) * 60 :\n  {\n    KEEP(*(.vector_new_60))\n    KEEP(*(.vector_60))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_60) <= (_vector_spacing << 5), \"function at exception vector 60 too large\")\n  .vector_61 _ebase_address + 0x200 + (_vector_spacing << 5) * 61 :\n  {\n    KEEP(*(.vector_new_61))\n    KEEP(*(.vector_61))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_61) <= (_vector_spacing << 5), \"function at exception vector 61 too large\")\n  .vector_62 _ebase_address + 0x200 + (_vector_spacing << 5) * 62 :\n  {\n    KEEP(*(.vector_new_62))\n    KEEP(*(.vector_62))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_62) <= (_vector_spacing << 5), \"function at exception vector 62 too large\")\n  .vector_63 _ebase_address + 0x200 + (_vector_spacing << 5) * 63 :\n  {\n    KEEP(*(.vector_new_63))\n    KEEP(*(.vector_63))\n  } > exception_mem\n  ASSERT (_vector_spacing == 0 || SIZEOF(.vector_63) <= (_vector_spacing << 5), \"function at exception vector 63 too large\")\n  .startup :\n  {\n    KEEP(*(.startup))\n  } > kseg0_program_mem\n  \/* Code Sections *\/\n\n  .text  :\n  {\n    _text_begin = . ;\n\n    *(.stub .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n    *(.gnu.warning)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem =0\n\n   .init      :\n  {\n\tKEEP (*crti.o(.init))\n\tKEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n\tKEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n    . = ALIGN(4) ;\n  }  >kseg0_program_mem\n\n  .fini       :\n  {\n    KEEP (*(.fini))\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  }>kseg0_program_mem\n\n  .init_array     :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__init_array_end = .);\n  }>kseg0_program_mem\n\n  .fini_array     :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    . = ALIGN(4) ;\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  }>kseg0_program_mem\n\n  .ctors        :\n  {\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .dtors          :\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  .preinit_array    :\n  {\n    KEEP (*(.preinit_array))\n    . = ALIGN(4) ;\n  }>kseg0_program_mem\n\n  \/* Read-only sections *\/\n  .header_info ALIGN(4) :\n  {\n    _image_header_info = . ;\n    LONG(SIZEOF(.header_info))                 \/* size of this structure       *\/\n    LONG(0xFFFFFFFF)                           \/* bootloader version           *\/\n    KEEP(*(.mpide_version *.mpide_version.*))  \/* MPIDE build version          *\/\n    LONG(0xFFFFFFFF)                           \/* booloader capabilities       *\/\n    LONG(0xFFFFFFFF)                           \/* VID and PID                  *\/\n    LONG(_IMAGE_TYPE)                          \/* image type and options       *\/\n    LONG(_JUMP_ADDR)                           \/* image execution address      *\/\n    LONG(_ebase_address)                       \/* image base address           *\/\n    LONG(_IMAGE_FLASH_SIZE)                    \/* size of image flash used     *\/\n    LONG(ORIGIN(kseg0_eeprom_mem))             \/* eeprom location              *\/\n    LONG(LENGTH(kseg0_eeprom_mem))             \/* eeprom size                  *\/   \n    LONG(ORIGIN(configsfrs))                   \/* config bits location         *\/\n    LONG(LENGTH(configsfrs))                   \/* config bits size             *\/\n    LONG(_ram_header_addr)                     \/* ram header pointer           *\/\n    LONG(SIZEOF(.ram_exchange_data))           \/* ram Header size              *\/\n    LONG(0xFFFFFFFF)                           \/* what the bootloader skips    *\/\n    LONG(_original_vector_0)                   \/* the original vector 0        *\/\n    LONG(_new_vector_0)                        \/* new\/indirect vector 0        *\/\n    LONG(_vector_spacing << 5)                 \/* spacing of both org\/new vec  *\/\n    _image_header_info_end = . ;\n  } > kseg0_program_mem\n  ASSERT (SIZEOF(.header_info) == 76, \"MPIDE Version not specfied correctly\")\n\n  .rodata  ALIGN(4) :\n  {\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   *\/\n  .sdata2 ALIGN(4)   :\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  \/*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   *\/\n  .sbss2 ALIGN(4)   :\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4) ;\n  } >kseg0_program_mem\n\n  .dbg_data ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } >kseg1_data_mem\n  \n  .ram_exchange_data (NOLOAD) :\n  {\n    _ram_header_addr = . ;\n    . += 8 ;\n  } >kseg1_data_mem\n\n  \/* Persistent data - Use the new C 'persistent' attribute instead. *\/\n  .persist ALIGN(4) (NOLOAD) :\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4) ;\n    _persist_end = .;\n  } >kseg1_data_mem\n\n  ASSERT( _persist_end <= ORIGIN(kseg1_data_mem) + 0x600, \"Bootloader does not preserve debug, RAM Header, or persistent data beyond the first 1.5K\")\n\n  \/* If this is a bootloader, than skip around the protected memory and don't place anything there *\/\n  _protected_end = ((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : . ;\n\n  .protected_bootloader ORIGIN(kseg1_data_mem) (NOLOAD) :\n  {\n    . += (((_IMAGE_TYPE & (_imageSplitFlashBootloader | _imageProgramFlashBootloader | _imageBootFlashBootloader)) != 0) ? (ORIGIN(kseg1_data_mem) + 0x600) : 0x0);\n  }\n\n  \/*\n   *  Note that input sections named .data* are not mapped here.\n   *  The best-fit allocator locates them, so that they may flow\n   *  around absolute sections as needed.\n   *\/\n  .data :\n  {\n    _data_begin = . ;\n    *( .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n\n    *(.data1)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  _data_image_begin = LOADADDR(.data) ;\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n\n  .got ALIGN(4)   :\n  {\n     *(.got.plt) *(.got)\n  } >kseg1_data_mem\n  \/*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   *\/\n  .sdata ALIGN(4)   :\n  {\n    _sdata_begin = . ;\n    *(.gnu.linkonce.s.*)\n    . = ALIGN(4) ;\n    _sdata_end = . ;\n  } >kseg1_data_mem\n\n  .lit8           :\n  {\n    *(.lit8)\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  .lit4           :\n  {\n    *(.lit4)\n  } >kseg1_data_mem \n\n  . = ALIGN (4) ;\n  _data_end = . ;\n  _bss_begin = . ;\n\n  .sbss ALIGN(4)   :\n  {\n    _sbss_begin = . ;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    . = ALIGN(4) ;\n    _sbss_end = . ;\n  } >kseg1_data_mem\n\n  .bss   :\n  {\n    *(.dynbss)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    \/*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     *\/\n    . = ALIGN(4) ;\n  } >kseg1_data_mem\n\n  . = ALIGN(4) ;\n  _end = . ;\n  _bss_end = . ;\n\n  \/*\n   *  The heap and stack are best-fit allocated by the linker after other\n   *  data and bss sections have been allocated.\n   *\/\n  \/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   *\n   * RAM functions are now allocated by the linker. The linker generates\n   * _ramfunc_begin and _bmxdkpba_address symbols depending on the\n   * location of RAM functions.\n   *\/\n  _bmxdudba_address = LENGTH(kseg1_data_mem) ;\n  _bmxdupba_address = LENGTH(kseg1_data_mem) ;\n\n    \/* The .pdr section belongs in the absolute section *\/\n    \n    \/DISCARD\/ : { *(.pdr) }\n    \/* We don't load .reginfo onto the target, so don't locate it\n     * in real memory\n     *\/\n    \/DISCARD\/ : { *(.reginfo) }\n\n  .gcc_compiled_long32 : { KEEP(*(.gcc_compiled_long32)) }\n  .gcc_compiled_long64 : { KEEP(*(.gcc_compiled_long64)) }\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0  : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/* DWARF 3 *\/\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  \/DISCARD\/ : { *(.rel.dyn) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n  \/DISCARD\/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) *(.discard) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e59ac0810ec79d7a67c8d65cb574853aec408672","subject":"Update: cleanup","message":"Update: cleanup\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX24T\/R5F524T8.ld","new_file":"RX24T\/R5F524T8.ld","new_contents":"\/* -*- tab-width : 4 -*- *\/\n\/*!\t@file\n\t@brief\tRX24T R5F524T8 \u30ea\u30f3\u30ab\u30fc\u30fb\u30b9\u30af\u30ea\u30d7\u30c8\n    @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\t@copyright\tCopyright (C) 2016, 2020 Kunihito Hiramatsu @n\n\t\t\t\tReleased under the MIT license @n\n\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX24T8 chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x00003A00 \/* 16K - stack_size (0x600) *\/\n\tUSTACK (w) : ORIGIN = 0x00003E00, LENGTH = 4 \/* ustack 1024 bytes *\/\n\tISTACK (w) : ORIGIN = 0x00004000, LENGTH = 4 \/* istack 512 bytes  *\/\n\tROM (w)    : ORIGIN = 0xFFFE0000, LENGTH = 0x0001FFD0 \/* 128K *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); \/* IF_ROROM *\/\n    PROVIDE (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE (__preinit_array_end = .);\n    PROVIDE (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE (__init_array_end = .);\n    PROVIDE (__fini_array_start = .);\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    PROVIDE (__fini_array_end = .);\n    LONG(0); \/* Sentinel.  *\/\n\n    \/* gcc uses crtbegin.o to find the start of the constructors, so\n       we make sure it is first.  Because this is a wildcard, it\n       doesn't matter if the user does not actually link against\n       crtbegin.o; the linker won't look for a file to match a\n       wildcard.  The wildcard also means that it doesn't matter which\n       directory crtbegin.o is in.  *\/\n    KEEP (*crtbegin*.o(.ctors))\n\n    \/* We don't want to include the .ctor section from from the\n       crtend.o file until after the sorted ctors.  The .ctor section\n       from the crtend file contains the end of ctors marker and it\n       must be last *\/\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n\n    KEEP (*crtbegin*.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n\n    KEEP (*(.jcr))\n    *(.data.rel.ro.local) *(.data.rel.ro*)\n    *(.dynamic)\n\n    *(.data D .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    SORT(CONSTRUCTORS)\n    *(.data1)\n    *(.got.plt) *(.got)\n\n    \/* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  *\/\n    . = ALIGN(4);\n    *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1)\n\n    . = ALIGN(4);\n    _edata = .;\n    PROVIDE (edata = .);\n    PROVIDE (__dataend = .);\n  } > RAM AT> ROM\n\n  \/* Note that __romdatacopysize may be ZERO for the simulator, which\n     knows how to intialize RAM directly.  It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .istack (ORIGIN (ISTACK)) :\n  {\n    PROVIDE (__istack = .);\n    *(.istack)\n  }\n\n  .ustack (ORIGIN (USTACK)) :\n  {\n    PROVIDE (__ustack = .);\n    *(.ustack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","old_contents":"\/*!\t@file\n\t@brief\tRX24T R5F524T8 \u30ea\u30f3\u30ab\u30fc\u30fb\u30b9\u30af\u30ea\u30d7\u30c8\n    @author \u5e73\u677e\u90a6\u4ec1 (hira@rvf-rc45.net)\n\t@copyright\tCopyright (C) 2016, 2017 Kunihito Hiramatsu @n\n\t\t\t\tReleased under the MIT license @n\n\t\t\t\thttps:\/\/github.com\/hirakuni45\/RX\/blob\/master\/LICENSE\n*\/\n\n\/* Default linker script, for normal executables *\/\nOUTPUT_ARCH(rx)\nENTRY(_start)\n\n\/* Do we need any of these for elf?\n   __DYNAMIC = 0;    *\/\n\n\/* This memory layout corresponds to the smallest predicted RX24T8 chip.  *\/\nMEMORY {\n\tRAM (w)    : ORIGIN = 0x00000000, LENGTH = 0x00003A00 \/* 16K - stack_size (0x600) *\/\n\tUSTACK (w) : ORIGIN = 0x00003E00, LENGTH = 4 \/* ustack 1024 bytes *\/\n\tISTACK (w) : ORIGIN = 0x00004000, LENGTH = 4 \/* istack 512 bytes  *\/\n\tROM (w)    : ORIGIN = 0xFFFE0000, LENGTH = 0x0001FFD0 \/* 128K *\/\n}\n\nSECTIONS\n{\n  .text           :\n  {\n    PROVIDE (_start = .);\n    *(.text P .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\n    *(.gnu.warning)\n    *(.interp .hash .dynsym .dynstr .gnu.version*)\n    PROVIDE (__etext = .);\n    PROVIDE (_etext = .);\n    PROVIDE (etext = .);\n    . = ALIGN(4);\n    KEEP (*(.init))\n    KEEP (*(.fini))\n  } > ROM\n\n  .rodata : {\n    . = ALIGN(4);\n    *(.plt)\n    *(.rodata C C_2 C_1 W W_2 W_1 .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    *(.eh_frame_hdr)\n    KEEP (*(.eh_frame))\n    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)\n    . = ALIGN(4);\n    PROVIDE(__romdatastart = .);\n  } > ROM\n\n  .data : {\n    . = ALIGN(4);\n    PROVIDE (__datastart = .); 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It should ONLY be used for\n     copying data from ROM to RAM; if you need to know the size of the\n     data section, subtract the end symbol from the start symbol.  *\/\n  \/* Note that crt0 assumes this is a multiple of four; all the\n     start\/stop symbols are also assumed long-aligned.  *\/\n  PROVIDE (__romdatacopysize = SIZEOF(.data));\n\n  .bss : {\n    . = ALIGN(4);\n    PROVIDE (__bssstart = .);\n    *(.dynbss)\n    *(.sbss .sbss.*)\n    *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*)\n    . = ALIGN(4);\n    *(COMMON)\n    . = ALIGN(4);\n    PROVIDE (__bssend = .);\n    _end = .;\n    PROVIDE (end = .);\n  } > RAM\n  PROVIDE (__bsssize = SIZEOF(.bss) \/ 4);\n\n  .istack (ORIGIN (ISTACK)) :\n  {\n    PROVIDE (__istack = .);\n    *(.istack)\n  }\n\n  .ustack (ORIGIN (USTACK)) :\n  {\n    PROVIDE (__ustack = .);\n    *(.ustack)\n  }\n\n  \/* Providing one of these symbols in your code is sufficient to have\n     it linked in to the fixed vector table.  *\/\n\n  PROVIDE (__rx_priviledged_exception_handler = 0x00000000);\n  PROVIDE (__rx_access_exception_handler = 0x00000000);\n  PROVIDE (__rx_undefined_exception_handler = 0x00000000);\n  PROVIDE (__rx_floating_exception_handler = 0x00000000);\n  PROVIDE (__rx_nonmaskable_exception_handler = 0x00000000);\n\n  .vectors (0xFFFFFFD0) :\n  {\n    PROVIDE (__vectors = .);\n    LONG (__rx_priviledged_exception_handler);\n    LONG (__rx_access_exception_handler);\n    LONG (0);\n    LONG (__rx_undefined_exception_handler);\n    LONG (0);\n    LONG (__rx_floating_exception_handler);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (0);\n    LONG (__rx_nonmaskable_exception_handler);\n    LONG (_start);\n  }\n\n  \/* The rest are all not normally part of the runtime image.  *\/\n\n  \/* Stabs debugging sections.  *\/\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  \/* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  \/DISCARD\/ : { *(.note.GNU-stack) }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"ae5945d7bedf739ba0beb9d11cd8394f0e78fd1c","subject":"soc: xtensa: fix missing rodata section in intel_adsp","message":"soc: xtensa: fix missing rodata section in intel_adsp\n\nThe common linker script for cavs_v?? was missing an include for the\nsnippets-rodata.ld file which is needed for any applications using the\n`zephyr_linker_source(RODATA <linker_script>)` cmake function.\n\nSigned-off-by: Yuval Peress <50dc11c009bd4d7e9d9d15a383c1743ce5ee82ef@google.com>\n","repos":"zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr","old_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_file":"soc\/xtensa\/intel_adsp\/common\/include\/cavs-link.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <linker\/sections.h>\n#include <cavs-vectors.h>\n#include <cavs-mem.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n    _imr_end = .;\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int6_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int6_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n\n    . = ALIGN(4);\n    #include <snippets-rodata.ld>\n\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.module_init)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n    _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  \/* Heap start and end markers.  Mostly unused, though newlib likes them *\/\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the intel_apl_adsp platform\n *\/\n\nOUTPUT_ARCH(xtensa)\n\n#include <devicetree.h>\n#include <xtensa\/config\/core-isa.h>\n#include <linker\/sections.h>\n#include <cavs-vectors.h>\n#include <cavs-mem.h>\n\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\nENTRY(rom_entry);\n\n\/* DSP RAM regions (all of them) are mapped twice on the DSP.  One\n * mapping is set up to bypass the L1 cache, so it must be used when\n * multiprocessor coherence is desired, where the latter mapping is\n * best used for processor-local data (e.g. stacks) or shared data\n * that is managed with explicit cache flush\/invalidate operations.\n *\n * These macros will set up a segment start address correctly,\n * including alignment to a cache line.  Be sure to also emit the\n * section to \">ram\" or \">ucram\" as appropriate, to prevent the linker\n * from filling in 512MB of sparse zeros.\n *\/\n#ifdef CONFIG_KERNEL_COHERENCE\n#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))\n#define SEGSTART_CACHED   RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)\n#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)\n#else\n#define SEGSTART_CACHED   .\n#define SEGSTART_UNCACHED .\n#define ucram ram\n#endif\n\n\/* intlist.ld needs an IDT_LIST memory region *\/\n#define IDT_BASE 0xe0000000\n#define IDT_SIZE 0x2000\n\n\/* rimage module sections are C struct data, and thus flagged ALLOC.\n * The xcc linker demands they be in a declared memory region even if\n * the enclosing output section is (NOLOAD).  Put them here.\n *\/\n#define NOLOAD_BASE 0x20000\n#define NOLOAD_SIZE 0x100000\n\nMEMORY {\n  vector_base_text :\n\torg = XCHAL_VECBASE_RESET_PADDR_SRAM,\n        len = MEM_VECBASE_LIT_SIZE\n  vector_int2_lit :\n\torg = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int2_text :\n        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int3_lit :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int3_text :\n\torg = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int4_lit :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int4_text :\n\torg = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int5_lit :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int5_text :\n\torg = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int6_lit :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int6_text :\n\torg = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_int7_lit :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_int7_text :\n\torg = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_kernel_lit :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_kernel_text :\n\torg = XCHAL_KERNEL_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_user_lit :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_user_text :\n\torg = XCHAL_USER_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  vector_double_lit :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,\n        len = MEM_VECT_LIT_SIZE\n  vector_double_text :\n\torg = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,\n        len = MEM_VECT_TEXT_SIZE\n  imr :\n        org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,\n        len = 0x100000\n  ram :\n\torg = RAM_BASE,\n\tlen = RAM_SIZE\n#ifdef CONFIG_KERNEL_COHERENCE\n  ucram :\n\torg = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),\n\tlen = RAM_SIZE\n#endif\n#ifdef CONFIG_GEN_ISR_TABLES\n  IDT_LIST :\n\torg = IDT_BASE,\n\tlen = IDT_SIZE\n#endif\n  lpram :\n\torg = LP_SRAM_BASE,\n\tlen = LP_SRAM_SIZE\n  noload :\n        org = NOLOAD_BASE,\n        len = NOLOAD_SIZE\n}\n\nSECTIONS {\n\n  \/* Boot loader code in IMR memory *\/\n  .imr : {\n    _imr_start = .;\n    \/* Entry point MUST be here per external configuration *\/\n    KEEP (*(.boot_entry.text))\n    *(.imr .imr.*)\n    _imr_end = .;\n  } >imr\n\n  \/* Boot loader data.  Note that rimage seems to want this\n   * page-aligned or it will throw an error, not sure why since all\n   * the ROM cares about is a contiguous region.  And it's\n   * particularly infuriating as it precludes linker .rodata next to\n   * .text.\n   *\/\n  .imrdata : ALIGN(4096) {\n    *(.imrdata .imrdata.*)\n  } >imr\n\n   .WindowVectors.text : {\n    _WindowVectors_text_start = .;\n    KEEP (*(.WindowVectors.text))\n    _WindowVectors_text_end = .;\n  } >vector_base_text\n  .Level2InterruptVector.literal : {\n    _Level2InterruptVector_literal_start = .;\n    *(.Level2InterruptVector.literal)\n    _Level2InterruptVector_literal_end = .;\n  } >vector_int2_lit\n  .Level2InterruptVector.text : {\n    _Level2InterruptVector_text_start = .;\n    KEEP (*(.Level2InterruptVector.text))\n    _Level2InterruptVector_text_end = .;\n  } >vector_int2_text\n  .Level3InterruptVector.literal : {\n    _Level3InterruptVector_literal_start = .;\n    *(.Level3InterruptVector.literal)\n    _Level3InterruptVector_literal_end = .;\n  } >vector_int3_lit\n  .Level3InterruptVector.text : {\n    _Level3InterruptVector_text_start = .;\n    KEEP (*(.Level3InterruptVector.text))\n    _Level3InterruptVector_text_end = .;\n  } >vector_int3_text\n  .Level4InterruptVector.literal : {\n    _Level4InterruptVector_literal_start = .;\n    *(.Level4InterruptVector.literal)\n    _Level4InterruptVector_literal_end = .;\n  } >vector_int4_lit\n  .Level4InterruptVector.text : {\n    _Level4InterruptVector_text_start = .;\n    KEEP (*(.Level4InterruptVector.text))\n    _Level4InterruptVector_text_end = .;\n  } >vector_int4_text\n  .Level5InterruptVector.literal : {\n    _Level5InterruptVector_literal_start = .;\n    *(.Level5InterruptVector.literal)\n    _Level5InterruptVector_literal_end = .;\n  } >vector_int5_lit\n  .Level5InterruptVector.text : {\n    _Level5InterruptVector_text_start = .;\n    KEEP (*(.Level5InterruptVector.text))\n    _Level5InterruptVector_text_end = .;\n  } >vector_int5_text\n  .DebugExceptionVector.literal : {\n    _DebugExceptionVector_literal_start = .;\n    *(.DebugExceptionVector.literal)\n    _DebugExceptionVector_literal_end = .;\n  } >vector_int6_lit\n  .DebugExceptionVector.text : {\n    _DebugExceptionVector_text_start = .;\n    KEEP (*(.DebugExceptionVector.text))\n    _DebugExceptionVector_text_end = .;\n  } >vector_int6_text\n  .NMIExceptionVector.literal : {\n    _NMIExceptionVector_literal_start = .;\n    *(.NMIExceptionVector.literal)\n    _NMIExceptionVector_literal_end = .;\n  } >vector_int7_lit\n  .NMIExceptionVector.text : {\n    _NMIExceptionVector_text_start = .;\n    KEEP (*(.NMIExceptionVector.text))\n    _NMIExceptionVector_text_end = .;\n  } >vector_int7_text\n  .KernelExceptionVector.literal : {\n    _KernelExceptionVector_literal_start = .;\n    *(.KernelExceptionVector.literal)\n    _KernelExceptionVector_literal_end = .;\n  } >vector_kernel_lit\n  .KernelExceptionVector.text : {\n    _KernelExceptionVector_text_start = .;\n    KEEP (*(.KernelExceptionVector.text))\n    _KernelExceptionVector_text_end = .;\n  } >vector_kernel_text\n  .UserExceptionVector.literal : {\n    _UserExceptionVector_literal_start = .;\n    *(.UserExceptionVector.literal)\n    _UserExceptionVector_literal_end = .;\n  } >vector_user_lit\n  .UserExceptionVector.text : {\n    _UserExceptionVector_text_start = .;\n    KEEP (*(.UserExceptionVector.text))\n    _UserExceptionVector_text_end = .;\n  } >vector_user_text\n  .DoubleExceptionVector.literal : {\n    _DoubleExceptionVector_literal_start = .;\n    *(.DoubleExceptionVector.literal)\n    _DoubleExceptionVector_literal_end = .;\n  } >vector_double_lit\n  .DoubleExceptionVector.text : {\n    _DoubleExceptionVector_text_start = .;\n    KEEP (*(.DoubleExceptionVector.text))\n    _DoubleExceptionVector_text_end = .;\n  } >vector_double_text\n\n  .text : {\n    _text_start = .;\n    *(.iram1 .iram1.*)\n    *(.entry.text)\n    *(.init.literal)\n    *(.iram0.text)\n    KEEP(*(.init))\n    KEEP(*(.lps_vector))\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.fini.literal)\n    KEEP(*(.fini))\n    *(.gnu.version)\n    _text_end = .;\n  } >ram\n\n  .rodata : ALIGN(4096)\n  {\n    _rodata_start = .;\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = .;\n    KEEP (*(.xt_except_table))\n    KEEP (*(.gcc_except_table .gcc_except_table.*))\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    KEEP (*(.eh_frame))\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __XT_EXCEPTION_DESCS__ = .;\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = .;\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _bss_table_start = .;\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = .;\n    _rodata_end = .;\n  } >ram\n\n  .module_init : {\n    _module_init_start = .;\n    *(*.module_init)\n    _module_init_end = .;\n  } >ram\n\n#define RAMABLE_REGION ram\n#define ROMABLE_REGION ram\n#include <linker\/common-rom.ld>\n\n  .fw_ready : {\n    KEEP(*(\".fw_ready\"));\n    KEEP (*(.fw_ready_metadata))\n  } >ram\n\n  .noinit SEGSTART_UNCACHED : {\n    *(.noinit)\n    *(.noinit.*)\n  } >ucram\n\n  .data SEGSTART_UNCACHED : {\n    _data_start = .;\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    KEEP(*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    KEEP(*(.jcr))\n    _trace_ctx_start = ABSOLUTE(.);\n    *(.trace_ctx)\n    _trace_ctx_end = ABSOLUTE(.);\n    *(.gna_model)\n    _data_end = .;\n  } >ucram\n\n  .lit4 SEGSTART_CACHED : {\n    _lit4_start = .;\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = .;\n  } >ram\n\n\/* These values need to change in our scheme, where the common-ram\n * sections need to be linked in safe\/uncached memory but common-rom\n * wants to use the cache\n *\/\n. = SEGSTART_UNCACHED;\n#undef RAMABLE_REGION\n#undef ROMABLE_REGION\n#define RAMABLE_REGION ucram\n#define ROMABLE_REGION ucram\n\n#include <linker\/common-ram.ld>\n\n  .tm_clone_table : {\n    *(.tm_clone_table)\n  } >ram\n\n  \/* This section is cached.  By default it contains only declared\n  * thread stacks, but applications can put symbols here too.\n  *\/\n  .cached SEGSTART_CACHED : {\n    _cached_start = .;\n    *(.cached .cached.*)\n    _cached_end = .;\n  } >ram\n\n  \/* Rimage requires 4k alignment between \"DATA\" and \"BSS\", can't do\n   * this in the section declaration below because we're also changing\n   * cacheability and that leaves a gap in the image large enough for\n   * binutils to decide to warn about (no way to turn that off, it\n   * seems, --warn-section-align is on by default)\n   *\/\n  . = ALIGN(4096);\n\n  .bss SEGSTART_UNCACHED (NOLOAD) :\n  {\n    _bss_start = .;\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN(8);\n    _bss_end = .;\n  } >ucram\n\n  \/* Heap start and end markers.  Mostly unused, though newlib likes them *\/\n  . = SEGSTART_UNCACHED;\n  _end = ALIGN(8);\n  . = L2_SRAM_BASE + L2_SRAM_SIZE;\n  . = SEGSTART_UNCACHED;\n  _heap_sentry = .;\n\n  \/* dma buffers *\/\n  .lpbuf (NOLOAD): {\n    _dma_buf_start = .;\n    *(.dma_buffers)\n    _dma_buf_end = .;\n  } >lpram\n\n  \/* Non-loadable sections below.  Back to cached memory so\n   * the cache remap script doesn't try to move them around needlessly.\n   *\/\n  . = SEGSTART_CACHED;\n\n  \/* rimage module manifest headers *\/\n  .module.boot : { KEEP(*(.module.boot)) } >noload\n  .module.main : { KEEP(*(.module.main)) } >noload\n\n .static_uuid_entries : {\n    *(*.static_uuids)\n  } >noload\n\n  .static_log_entries : {\n    *(*.static_log*)\n  } >noload\n\n  \/* This is the \"extended manifest\" data (mostly versioning stuff)\n   * emitted by SOF and inspected by the kernel driver.  It doesn't\n   * appear directly in the image, but rimage will parse and repack\n   * this into the output file header, so requires this be present\n   * even if empty.  Alignment and padding to 16 bytes is required,\n   * otherwise rimage will complain about the size being wrong (which\n   * sounds like a struct should be declared packed somewhere...)\n   *\/\n  .fw_metadata : ALIGN(16) {\n    KEEP (*(.fw_metadata))\n    . = ALIGN(16);\n  } >noload\n\n#include <linker\/debug-sections.ld>\n\n  .xtensa.info 0 : { *(.xtensa.info) }\n  .xt.insn 0 : {\n    KEEP (*(.xt.insn))\n    KEEP (*(.gnu.linkonce.x.*))\n  }\n  .xt.prop 0 : {\n    KEEP (*(.xt.prop))\n    KEEP (*(.xt.prop.*))\n    KEEP (*(.gnu.linkonce.prop.*))\n  }\n  .xt.lit 0 : {\n    KEEP (*(.xt.lit))\n    KEEP (*(.xt.lit.*))\n    KEEP (*(.gnu.linkonce.p.*))\n  }\n  .xt.profile_range 0 : {\n    KEEP (*(.xt.profile_range))\n    KEEP (*(.gnu.linkonce.profile_range.*))\n  }\n  .xt.profile_ranges 0 : {\n    KEEP (*(.xt.profile_ranges))\n    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))\n  }\n  .xt.profile_files 0 : {\n    KEEP (*(.xt.profile_files))\n    KEEP (*(.gnu.linkonce.xt.profile_files.*))\n  }\n\n#ifdef CONFIG_GEN_ISR_TABLES\n#include <linker\/intlist.ld>\n#endif\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ec5b9ad34852916ebefabbbe644ecb4d6bcbd58b","subject":"arm64: rename default RAM region from 'SRAM' to 'RAM'","message":"arm64: rename default RAM region from 'SRAM' to 'RAM'\n\nAs with 32-bit ARM, it is useful to make the RAMABLE_REGION name uniform\nacross architectures so the build system does not need to be aware of\nthe differences when CODE_DATA_RELOCATION is supported. Generalize the\nname to just 'RAM' for uniformity.\n\nSigned-off-by: Peter Marheine <ef0b2c492edde94778d7465bfbaeed52c5be6858@chromium.org>\n","repos":"finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr","old_file":"include\/zephyr\/arch\/arm64\/scripts\/linker.ld","new_file":"include\/zephyr\/arch\/arm64\/scripts\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n#else\n  #define ROMABLE_REGION RAM\n#endif\n#define RAMABLE_REGION RAM\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#elif defined(CONFIG_ARM_MPU)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n  #define BSS_ALIGN ALIGN(_region_min_align)\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#ifndef BSS_ALIGN\n#define BSS_ALIGN\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    RAM       (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    __rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        __text_region_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __text_region_end = .;\n    __text_region_size = __text_region_end - __text_region_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n        __rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n        \/*\n         * The following is a workaround to allow compiling with GCC 12 and\n         * above, which may emit \"GOT indirections\" for the weak symbol\n         * references (see the GitHub issue zephyrproject-rtos\/sdk-ng#547).\n         *\/\n        *(.got)\n        *(.got.plt)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    __rodata_region_end = .;\n    __rodata_region_size = __rodata_region_end - __rodata_region_start;\n    __rom_region_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.igot.plt)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image RAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#if defined(CONFIG_ARM_MPU)\n\/*\n * When _app_smem region is empty, alignment is also needed. If there\n * is no alignment, the _app_smem_start used by arm mpu can be lower\n * than __rodata_region_end, and this two regions can overlap.\n * The Armv8-R aarch64 MPU does not allow overlapped regions.\n *\/\n#define EMPTY_APP_SHARED_ALIGN APP_SHARED_ALIGN\n#endif\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n\t__data_region_start = .;\n\t__data_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        __data_end = .;\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n}\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n\/**\n * @file\n * @brief Linker command\/script file\n *\n * Linker script for the Cortex-A platforms.\n *\/\n\n#include <zephyr\/linker\/sections.h>\n#include <zephyr\/devicetree.h>\n\n#include <zephyr\/linker\/linker-defs.h>\n#include <zephyr\/linker\/linker-tool.h>\n\n\/* physical address of RAM *\/\n#ifdef CONFIG_XIP\n  #define ROMABLE_REGION FLASH\n  #define RAMABLE_REGION SRAM\n#else\n  #define ROMABLE_REGION SRAM\n  #define RAMABLE_REGION SRAM\n#endif\n\n#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)\n  #define ROM_ADDR RAM_ADDR\n#else\n  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#if CONFIG_FLASH_LOAD_SIZE > 0\n  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE\n#else\n  #define ROM_SIZE (CONFIG_FLASH_SIZE * 1K - CONFIG_FLASH_LOAD_OFFSET)\n#endif\n\n#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)\n#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS\n\n#if defined(CONFIG_ARM_MMU)\n  _region_min_align = CONFIG_MMU_PAGE_SIZE;\n#elif defined(CONFIG_ARM_MPU)\n  _region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;\n  #define BSS_ALIGN ALIGN(_region_min_align)\n#else\n  \/* If building without MMU support, use default 4-byte alignment. *\/\n  _region_min_align = 4;\n#endif\n\n#ifndef BSS_ALIGN\n#define BSS_ALIGN\n#endif\n\n#define MMU_ALIGN    . = ALIGN(_region_min_align)\n\nMEMORY\n{\n    FLASH     (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE\n    SRAM      (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE\n    \/* Used by and documented in include\/linker\/intlist.ld *\/\n    IDT_LIST  (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n}\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n{\n\n#include <zephyr\/linker\/rel-sections.ld>\n\n    \/*\n     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',\n     * before text section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.plt)\n    }\n\n    \/DISCARD\/ :\n    {\n        *(.iplt)\n    }\n\n    GROUP_START(ROMABLE_REGION)\n\n    __rom_region_start = ROM_ADDR;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n    {\n        __text_region_start = .;\n#ifndef CONFIG_XIP\n        z_mapped_start = .;\n#endif\n\n#ifdef CONFIG_AARCH64_IMAGE_HEADER\n        KEEP(*(.image_header))\n        KEEP(*(\".image_header.*\"))\n#endif\n\n        _vector_start = .;\n        KEEP(*(.exc_vector_table))\n        KEEP(*(\".exc_vector_table.*\"))\n\n        KEEP(*(.vectors))\n\n        _vector_end = .;\n\n        *(.text)\n        *(\".text.*\")\n        *(.gnu.linkonce.t.*)\n\n        \/*\n         * These are here according to 'arm-zephyr-elf-ld --verbose',\n         * after .gnu.linkonce.t.*\n         *\/\n        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n\n#include <zephyr\/linker\/kobject-text.ld>\n\n        MMU_ALIGN;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    __text_region_end = .;\n    __text_region_size = __text_region_end - __text_region_start;\n\n#if defined (CONFIG_CPLUSPLUS)\n    SECTION_PROLOGUE(.ARM.extab,,)\n    {\n        \/*\n         * .ARM.extab section containing exception unwinding information.\n         *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n#endif\n\n    SECTION_PROLOGUE(.ARM.exidx,,)\n    {\n        \/*\n         * This section, related to stack and exception unwinding, is placed\n         * explicitly to prevent it from being shared between multiple regions.\n         * It  must be defined for gcc to support 64-bit math and avoid\n         * section overlap.\n         *\/\n        __exidx_start = .;\n#if defined (__GCC_LINKER_CMD__)\n        *(.ARM.exidx* gnu.linkonce.armexidx.*)\n#endif\n        __exidx_end = .;\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n        __rodata_region_start = .;\n\n#include <zephyr\/linker\/common-rom.ld>\n#include <zephyr\/linker\/thread-local-storage.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n    {\n        *(.rodata)\n        *(\".rodata.*\")\n        *(.gnu.linkonce.r.*)\n\n        \/*\n         * The following is a workaround to allow compiling with GCC 12 and\n         * above, which may emit \"GOT indirections\" for the weak symbol\n         * references (see the GitHub issue zephyrproject-rtos\/sdk-ng#547).\n         *\/\n        *(.got)\n        *(.got.plt)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n#include <zephyr\/linker\/kobject-rom.ld>\n\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <zephyr\/linker\/cplusplus-rom.ld>\n    MMU_ALIGN;\n\n    __rodata_region_end = .;\n    __rodata_region_size = __rodata_region_end - __rodata_region_start;\n    __rom_region_end = .;\n\n    \/*\n     * These are here according to 'arm-zephyr-elf-ld --verbose',\n     * before data section.\n     *\/\n    \/DISCARD\/ :\n    {\n        *(.igot.plt)\n        *(.igot)\n    }\n\n    GROUP_END(ROMABLE_REGION)\n\n    GROUP_START(RAMABLE_REGION)\n\n    . = RAM_ADDR;\n    \/* Align the start of image SRAM with the\n     * minimum granularity required by MMU.\n     *\/\n    . = ALIGN(_region_min_align);\n    _image_ram_start = .;\n#ifdef CONFIG_XIP\n    z_mapped_start = .;\n#endif\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n#if defined(CONFIG_USERSPACE)\n#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);\n#define SMEM_PARTITION_ALIGN(size) MMU_ALIGN\n\n#if defined(CONFIG_ARM_MPU)\n\/*\n * When _app_smem region is empty, alignment is also needed. If there\n * is no alignment, the _app_smem_start used by arm mpu can be lower\n * than __rodata_region_end, and this two regions can overlap.\n * The Armv8-R aarch64 MPU does not allow overlapped regions.\n *\/\n#define EMPTY_APP_SHARED_ALIGN APP_SHARED_ALIGN\n#endif\n\n#include <app_smem.ld>\n\n    _app_smem_size = _app_smem_end - _app_smem_start;\n    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);\n#endif  \/* CONFIG_USERSPACE *\/\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)\n    {\n        \/*\n         * For performance, BSS section is assumed to be 4 byte aligned and\n         * a multiple of 4 bytes\n         *\/\n        . = ALIGN(4);\n        __bss_start = .;\n        __kernel_ram_start = .;\n\n        *(.bss)\n        *(\".bss.*\")\n        *(COMMON)\n        *(\".kernel_bss.*\")\n\n        \/*\n         * As memory is cleared in words only, it is simpler to ensure the BSS\n         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.\n                 *\/\n        __bss_end = ALIGN(4);\n    } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n#include <zephyr\/linker\/common-noinit.ld>\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n    {\n\t__data_region_start = .;\n\t__data_start = .;\n        *(.data)\n        *(\".data.*\")\n        *(\".kernel.*\")\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n        __data_end = .;\n\n    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n    __data_size = __data_end - __data_start;\n    __data_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n    __data_region_load_start = LOADADDR(_DATA_SECTION_NAME);\n\n#include <zephyr\/linker\/common-ram.ld>\n#include <zephyr\/linker\/kobject-data.ld>\n#include <zephyr\/linker\/cplusplus-ram.ld>\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-data-sections.ld>\n\n    __data_region_end = .;\n\n\n    \/* Define linker symbols *\/\n\n    MMU_ALIGN;\n    _image_ram_end = .;\n    _end = .; \/* end of image *\/\n    z_mapped_end = .;\n\n    __kernel_ram_end = RAM_ADDR + RAM_SIZE;\n    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;\n\n    GROUP_END(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#include <zephyr\/linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.ARM.attributes, 0,)\n    {\n        KEEP(*(.ARM.attributes))\n        KEEP(*(.gnu.attributes))\n    }\n\n    \/DISCARD\/ : { *(.note.GNU-stack) }\n\n\n    \/* Must be last in romable region *\/\n    SECTION_PROLOGUE(.last_section,(NOLOAD),)\n    {\n    } GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n    \/* To provide the image size as a const expression,\n     * calculate this value here. *\/\n    _flash_used = LOADADDR(.last_section) - __rom_region_start;\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bb794f9e02f1fcfe4cbafafe2f4f79a8c826313f","subject":"Move C++ vtables into IRAM, out of HEAP (#4179)","message":"Move C++ vtables into IRAM, out of HEAP (#4179)\n\nGCC places vtables in .rodata, with a mangled name of \"_ZTV*.\"  Because\r\nthese are simply address jump tables, there is no need to place them in\r\nRAM.  Instead, have the linker place them in the .text (aka IRAM) section.\r\nThis will free up a variable amount of heap space, depending on the number\r\nof classes with virtual functions used in any particular project.","repos":"wemos\/Arduino,Adam5Wu\/Arduino,Lan-Hekary\/Arduino,Lan-Hekary\/Arduino,Adam5Wu\/Arduino,esp8266\/Arduino,hallard\/Arduino,hallard\/Arduino,wemos\/Arduino,Lan-Hekary\/Arduino,Lan-Hekary\/Arduino,wemos\/Arduino,lrmoreno007\/Arduino,sticilface\/Arduino,esp8266\/Arduino,hallard\/Arduino,sticilface\/Arduino,hallard\/Arduino,Adam5Wu\/Arduino,esp8266\/Arduino,lrmoreno007\/Arduino,sticilface\/Arduino,Adam5Wu\/Arduino,lrmoreno007\/Arduino,wemos\/Arduino,Lan-Hekary\/Arduino,esp8266\/Arduino,hallard\/Arduino,Adam5Wu\/Arduino,lrmoreno007\/Arduino,sticilface\/Arduino,lrmoreno007\/Arduino,esp8266\/Arduino,sticilface\/Arduino,wemos\/Arduino","old_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nEXTERN(core_version)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    \/* PlatformIO *\/\n    \/* framework *\/\n    *.pioenvs\\\\*\\\\lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, EXCLUDE_FILE (umm_malloc.o) .text*)\n    \/* project dependencies *\/\n    *.pioenvs\\\\*\\\\lib*\\lib*.a:(.literal*, .text*)\n    *.pioenvs\/*\/lib*\/lib*.a:(.literal*, .text*)\n    \/* project source objects *\/\n    *.pioenvs\\\\*\\\\src\\\\*.o(.literal*, .text*)\n    *.pioenvs\/*\/src\/*.o(.literal*, .text*)\n    \/* End PlatformIO *\/\n    *libc.a:(.literal .text .literal.* .text.*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *libstdc++.a:(.literal .text .literal.* .text.*)\n    *liblwip_gcc.a:(.literal .text .literal.* .text.*)\n    *liblwip_src.a:(.literal .text .literal.* .text.*)\n    *liblwip2.a:(.literal .text .literal.* .text.*)\n    *liblwip2_1460.a:(.literal .text .literal.* .text.*)\n    *libaxtls.a:(.literal .text .literal.* .text.*)\n    *libat.a:(.literal.* .text.*)\n    *libcrypto.a:(.literal.* .text.*)\n    *libespnow.a:(.literal.* .text.*)\n    *libjson.a:(.literal.* .text.*)\n    *liblwip.a:(.literal.* .text.*)\n    *libmesh.a:(.literal.* .text.*)\n    *libnet80211.a:(.literal.* .text.*)\n    *libsmartconfig.a:(.literal.* .text.*)\n    *libssl.a:(.literal.* .text.*)\n    *libupgrade.a:(.literal.* .text.*)\n    *libwpa.a:(.literal.* .text.*)\n    *libwpa2.a:(.literal.* .text.*)\n    *libwps.a:(.literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    *(.rodata._ZTV*) \/* C++ vtables *\/\n    \/* PlatformIO *\/\n    \/* framework *\/\n    *.pioenvs\\\\*\\\\lib*.a:(.iram.text)\n    *.pioenvs\/*\/lib*.a:(.iram.text)\n    \/* project dependencies *\/\n    *.pioenvs\\\\*\\\\lib*\\\\lib*.a:(.iram.text)\n    *.pioenvs\/*\/lib*\/lib*.a:(.iram.text)\n    \/* project source objects *\/\n    *.pioenvs\\\\*\\\\src\\\\*.o(.iram.text)\n    *.pioenvs\/*\/src\/*.o(.iram.text)\n    \/* End PlatformIO *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","old_contents":"\/* This linker script generated from xt-genldscripts.tpp for LSP . *\/\n\/* Linker Script for ld -N *\/\n\nPHDRS\n{\n  dport0_0_phdr PT_LOAD;\n  dram0_0_phdr PT_LOAD;\n  dram0_0_bss_phdr PT_LOAD;\n  iram1_0_phdr PT_LOAD;\n  irom0_0_phdr PT_LOAD;\n}\n\n\n\/*  Default entry point:  *\/\nENTRY(call_user_start)\nEXTERN(_DebugExceptionVector)\nEXTERN(_DoubleExceptionVector)\nEXTERN(_KernelExceptionVector)\nEXTERN(_NMIExceptionVector)\nEXTERN(_UserExceptionVector)\nEXTERN(core_version)\nPROVIDE(_memmap_vecbase_reset = 0x40000000);\n\/* Various memory-map dependent cache attribute settings: *\/\n_memmap_cacheattr_wb_base = 0x00000110;\n_memmap_cacheattr_wt_base = 0x00000110;\n_memmap_cacheattr_bp_base = 0x00000220;\n_memmap_cacheattr_unused_mask = 0xFFFFF00F;\n_memmap_cacheattr_wb_trapnull = 0x2222211F;\n_memmap_cacheattr_wba_trapnull = 0x2222211F;\n_memmap_cacheattr_wbna_trapnull = 0x2222211F;\n_memmap_cacheattr_wt_trapnull = 0x2222211F;\n_memmap_cacheattr_bp_trapnull = 0x2222222F;\n_memmap_cacheattr_wb_strict = 0xFFFFF11F;\n_memmap_cacheattr_wt_strict = 0xFFFFF11F;\n_memmap_cacheattr_bp_strict = 0xFFFFF22F;\n_memmap_cacheattr_wb_allvalid = 0x22222112;\n_memmap_cacheattr_wt_allvalid = 0x22222112;\n_memmap_cacheattr_bp_allvalid = 0x22222222;\nPROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);\n\nSECTIONS\n{\n\n  .dport0.rodata : ALIGN(4)\n  {\n    _dport0_rodata_start = ABSOLUTE(.);\n    *(.dport0.rodata)\n    *(.dport.rodata)\n    _dport0_rodata_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.literal : ALIGN(4)\n  {\n    _dport0_literal_start = ABSOLUTE(.);\n    *(.dport0.literal)\n    *(.dport.literal)\n    _dport0_literal_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .dport0.data : ALIGN(4)\n  {\n    _dport0_data_start = ABSOLUTE(.);\n    *(.dport0.data)\n    *(.dport.data)\n    _dport0_data_end = ABSOLUTE(.);\n  } >dport0_0_seg :dport0_0_phdr\n\n  .data : ALIGN(4)\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    . = ALIGN(4);\n    _Pri_3_HandlerAddress = ABSOLUTE(.);\n    _data_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .rodata : ALIGN(4)\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.sdk.version)\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    . = ALIGN(4);       \/* this table MUST be 4-byte aligned *\/\n    _bss_table_start = ABSOLUTE(.);\n    LONG(_bss_start)\n    LONG(_bss_end)\n    _bss_table_end = ABSOLUTE(.);\n    _rodata_end = ABSOLUTE(.);\n  } >dram0_0_seg :dram0_0_phdr\n\n  .bss ALIGN(8) (NOLOAD) : ALIGN(4)\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n    _heap_start = ABSOLUTE(.);\n\/*    _stack_sentry = ALIGN(0x8); *\/\n  } >dram0_0_seg :dram0_0_bss_phdr\n\/* __stack = 0x3ffc8000; *\/\n\n  .irom0.text : ALIGN(4)\n  {\n    _irom0_text_start = ABSOLUTE(.);\n    *(.ver_number)\n    *.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, \\\n           EXCLUDE_FILE (umm_malloc.c.o) .text*)\n    *.cpp.o(.literal*, .text*)\n    \/* PlatformIO *\/\n    \/* framework *\/\n    *.pioenvs\\\\*\\\\lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, EXCLUDE_FILE (umm_malloc.o) .text*)\n    *.pioenvs\/*\/lib*.a:(EXCLUDE_FILE (umm_malloc.o) .literal*, EXCLUDE_FILE (umm_malloc.o) .text*)\n    \/* project dependencies *\/\n    *.pioenvs\\\\*\\\\lib*\\lib*.a:(.literal*, .text*)\n    *.pioenvs\/*\/lib*\/lib*.a:(.literal*, .text*)\n    \/* project source objects *\/\n    *.pioenvs\\\\*\\\\src\\\\*.o(.literal*, .text*)\n    *.pioenvs\/*\/src\/*.o(.literal*, .text*)\n    \/* End PlatformIO *\/\n    *libc.a:(.literal .text .literal.* .text.*)\n    *libm.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:_umoddi3.o(.literal .text)\n    *libgcc.a:_udivdi3.o(.literal .text)\n    *libsmartconfig.a:(.literal .text .literal.* .text.*)\n    *libstdc++.a:(.literal .text .literal.* .text.*)\n    *liblwip_gcc.a:(.literal .text .literal.* .text.*)\n    *liblwip_src.a:(.literal .text .literal.* .text.*)\n    *liblwip2.a:(.literal .text .literal.* .text.*)\n    *liblwip2_1460.a:(.literal .text .literal.* .text.*)\n    *libaxtls.a:(.literal .text .literal.* .text.*)\n    *libat.a:(.literal.* .text.*)\n    *libcrypto.a:(.literal.* .text.*)\n    *libespnow.a:(.literal.* .text.*)\n    *libjson.a:(.literal.* .text.*)\n    *liblwip.a:(.literal.* .text.*)\n    *libmesh.a:(.literal.* .text.*)\n    *libnet80211.a:(.literal.* .text.*)\n    *libsmartconfig.a:(.literal.* .text.*)\n    *libssl.a:(.literal.* .text.*)\n    *libupgrade.a:(.literal.* .text.*)\n    *libwpa.a:(.literal.* .text.*)\n    *libwpa2.a:(.literal.* .text.*)\n    *libwps.a:(.literal.* .text.*)\n    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)\n    _irom0_text_end = ABSOLUTE(.);\n    _flash_code_end = ABSOLUTE(.);\n  } >irom0_0_seg :irom0_0_phdr\n\n  .text : ALIGN(4)\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n     *(.UserEnter.text)\n    . = ALIGN(16);\n    *(.DebugExceptionVector.text)\n    . = ALIGN(16);\n    *(.NMIExceptionVector.text)\n    . = ALIGN(16);\n    *(.KernelExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.UserExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN(16);\n    *(.DoubleExceptionVector.text)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    LONG(0)\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *.cpp.o(.iram.text)\n    *.c.o(.iram.text)\n    \/* PlatformIO *\/\n    \/* framework *\/\n    *.pioenvs\\\\*\\\\lib*.a:(.iram.text)\n    *.pioenvs\/*\/lib*.a:(.iram.text)\n    \/* project dependencies *\/\n    *.pioenvs\\\\*\\\\lib*\\\\lib*.a:(.iram.text)\n    *.pioenvs\/*\/lib*\/lib*.a:(.iram.text)\n    \/* project source objects *\/\n    *.pioenvs\\\\*\\\\src\\\\*.o(.iram.text)\n    *.pioenvs\/*\/src\/*.o(.iram.text)\n    \/* End PlatformIO *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } >iram1_0_seg :iram1_0_phdr\n\n  .lit4 : ALIGN(4)\n  {\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n  } >iram1_0_seg :iram1_0_phdr\n\n\n}\n\n\/* get ROM code address *\/\nINCLUDE \"..\/ld\/eagle.rom.addr.v6.ld\"\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"2d3c2efebddff0ca9ce36b7083c33a78ad462ea8","subject":"tests: arch: arm: arm-irq-vector-table: define _vector_end","message":"tests: arch: arm: arm-irq-vector-table: define _vector_end\n\nFollowing implementation of commit 219d5b5,\nand to complement commit 8c4f98d\nit is also necessary define _vector_end in\ntest specific arm-irq-vector-table.ld\n\nFixes #47273\n\nSigned-off-by: Alexandre Bourdiol <c23cc711c078d3e6bb50b3dc45a1b8842691e59a@st.com>\n","repos":"zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"tests\/arch\/arm\/arm_irq_vector_table\/irq-vector-table.ld","new_file":"tests\/arch\/arm\/arm_irq_vector_table\/irq-vector-table.ld","new_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\nKEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n\n\/*\n * Some ARM platforms require this symbol to be placed after the IRQ vector\n * table (like STM32F0). The symbol defined here is overriding the one in\n * arch\/arm\/core\/aarch32\/vector_table.ld when the IRQ vector table is enabled.\n *\/\n_vector_end = .;\n","old_contents":"\/* SPDX-License-Identifier: Apache-2.0 *\/\n\nKEEP(*(_IRQ_VECTOR_TABLE_SECTION_SYMS))\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4049f4ba07120c818cf5fa9e60dcd1b3c683e0e3","subject":"[KINETIS] Add missing entry to linker script","message":"[KINETIS] Add missing entry to linker script\n\ngit-svn-id: de15d415ffb1bc5d91a165b5b7d2093897d104a2@7155 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"os\/common\/ports\/ARMCMx\/compilers\/GCC\/ld\/KL25Z128.ld","new_file":"os\/common\/ports\/ARMCMx\/compilers\/GCC\/ld\/KL25Z128.ld","new_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * KL25Z128 memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0400;\r\n__process_stack_size__  = 0x0400;\r\n\r\nENTRY(Reset_Handler)\r\n\r\nMEMORY\r\n{\r\n  flash0   :  org = 0x00000000,  len = 0xc0\r\n  flashcfg :  org = 0x00000400,  len = 0x10\r\n  flash    :  org = 0x00000410,  len = 128k - 0x410\r\n  ram      :  org = 0x1FFFF000,  len = 16k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n  . = 0;\r\n\r\n  .isr : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    KEEP(*(vectors))\r\n  } > flash0\r\n\r\n  .cfmprotect : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    KEEP(*(.cfmconfig))\r\n  } > flashcfg\r\n\r\n  _text = .;\r\n\r\n  constructors : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    PROVIDE(__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE(__init_array_end = .);\r\n  } > flash\r\n\r\n  destructors : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    PROVIDE(__fini_array_start = .);\r\n    KEEP(*(.fini_array))\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    PROVIDE(__fini_array_end = .);\r\n  } > flash\r\n\r\n  .text : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    *(.text)\r\n    *(.text.*)\r\n    *(.rodata)\r\n    *(.rodata.*)\r\n    *(.glue_7t)\r\n    *(.glue_7)\r\n    *(.gcc*)\r\n  } > flash\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > flash\r\n\r\n  .ARM.exidx : {\r\n    PROVIDE(__exidx_start = .);\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    PROVIDE(__exidx_end = .);\r\n  } > flash\r\n\r\n  .eh_frame_hdr :\r\n  {\r\n    *(.eh_frame_hdr)\r\n  } > flash\r\n\r\n  .eh_frame : ONLY_IF_RO\r\n  {\r\n    *(.eh_frame)\r\n  } > flash\r\n\r\n  .textalign : ONLY_IF_RO\r\n  {\r\n    . = ALIGN(8);\r\n  } > flash\r\n\r\n  _etext = .;\r\n  _textdata = _etext;\r\n\r\n  .stacks :\r\n  {\r\n    . = ALIGN(8);\r\n    __main_stack_base__ = .;\r\n    . += __main_stack_size__;\r\n    . = ALIGN(8);\r\n    __main_stack_end__ = .;\r\n    __process_stack_base__ = .;\r\n    __main_thread_stack_base__ = .;\r\n    . += __process_stack_size__;\r\n    . = ALIGN(8);\r\n    __process_stack_end__ = .;\r\n    __main_thread_stack_end__ = .;\r\n  } > ram\r\n\r\n  .data :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE(_data = .);\r\n    *(.data)\r\n    . = ALIGN(4);\r\n    *(.data.*)\r\n    . = ALIGN(4);\r\n    *(.ramtext)\r\n    . = ALIGN(4);\r\n    PROVIDE(_edata = .);\r\n  } > ram AT > flash\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE(_bss_start = .);\r\n    *(.bss)\r\n    . = ALIGN(4);\r\n    *(.bss.*)\r\n    . = ALIGN(4);\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    PROVIDE(_bss_end = .);\r\n  } > ram\r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__;\r\n","old_contents":"\/*\r\n    ChibiOS\/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.\r\n\r\n    This file is part of ChibiOS\/RT.\r\n\r\n    ChibiOS\/RT is free software; you can redistribute it and\/or modify\r\n    it under the terms of the GNU General Public License as published by\r\n    the Free Software Foundation; either version 3 of the License, or\r\n    (at your option) any later version.\r\n\r\n    ChibiOS\/RT is distributed in the hope that it will be useful,\r\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r\n    GNU General Public License for more details.\r\n\r\n    You should have received a copy of the GNU General Public License\r\n    along with this program.  If not, see <http:\/\/www.gnu.org\/licenses\/>.\r\n*\/\r\n\r\n\/*\r\n * KL25Z128 memory setup.\r\n *\/\r\n__main_stack_size__     = 0x0400;\r\n__process_stack_size__  = 0x0400;\r\n\r\nMEMORY\r\n{\r\n  flash0   :  org = 0x00000000,  len = 0xc0\r\n  flashcfg :  org = 0x00000400,  len = 0x10\r\n  flash    :  org = 0x00000410,  len = 128k - 0x410\r\n  ram      :  org = 0x1FFFF000,  len = 16k\r\n}\r\n\r\n__ram_start__           = ORIGIN(ram);\r\n__ram_size__            = LENGTH(ram);\r\n__ram_end__             = __ram_start__ + __ram_size__;\r\n\r\nSECTIONS\r\n{\r\n  . = 0;\r\n\r\n  .isr : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    KEEP(*(vectors))\r\n  } > flash0\r\n\r\n  .cfmprotect : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    KEEP(*(.cfmconfig))\r\n  } > flashcfg\r\n\r\n  _text = .;\r\n\r\n  constructors : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    PROVIDE(__init_array_start = .);\r\n    KEEP(*(SORT(.init_array.*)))\r\n    KEEP(*(.init_array))\r\n    PROVIDE(__init_array_end = .);\r\n  } > flash\r\n\r\n  destructors : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    PROVIDE(__fini_array_start = .);\r\n    KEEP(*(.fini_array))\r\n    KEEP(*(SORT(.fini_array.*)))\r\n    PROVIDE(__fini_array_end = .);\r\n  } > flash\r\n\r\n  .text : ALIGN(4) SUBALIGN(4)\r\n  {\r\n    *(.text)\r\n    *(.text.*)\r\n    *(.rodata)\r\n    *(.rodata.*)\r\n    *(.glue_7t)\r\n    *(.glue_7)\r\n    *(.gcc*)\r\n  } > flash\r\n\r\n  .ARM.extab :\r\n  {\r\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\r\n  } > flash\r\n\r\n  .ARM.exidx : {\r\n    PROVIDE(__exidx_start = .);\r\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r\n    PROVIDE(__exidx_end = .);\r\n  } > flash\r\n\r\n  .eh_frame_hdr :\r\n  {\r\n    *(.eh_frame_hdr)\r\n  } > flash\r\n\r\n  .eh_frame : ONLY_IF_RO\r\n  {\r\n    *(.eh_frame)\r\n  } > flash\r\n\r\n  .textalign : ONLY_IF_RO\r\n  {\r\n    . = ALIGN(8);\r\n  } > flash\r\n\r\n  _etext = .;\r\n  _textdata = _etext;\r\n\r\n  .stacks :\r\n  {\r\n    . = ALIGN(8);\r\n    __main_stack_base__ = .;\r\n    . += __main_stack_size__;\r\n    . = ALIGN(8);\r\n    __main_stack_end__ = .;\r\n    __process_stack_base__ = .;\r\n    __main_thread_stack_base__ = .;\r\n    . += __process_stack_size__;\r\n    . = ALIGN(8);\r\n    __process_stack_end__ = .;\r\n    __main_thread_stack_end__ = .;\r\n  } > ram\r\n\r\n  .data :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE(_data = .);\r\n    *(.data)\r\n    . = ALIGN(4);\r\n    *(.data.*)\r\n    . = ALIGN(4);\r\n    *(.ramtext)\r\n    . = ALIGN(4);\r\n    PROVIDE(_edata = .);\r\n  } > ram AT > flash\r\n\r\n  .bss :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE(_bss_start = .);\r\n    *(.bss)\r\n    . = ALIGN(4);\r\n    *(.bss.*)\r\n    . = ALIGN(4);\r\n    *(COMMON)\r\n    . = ALIGN(4);\r\n    PROVIDE(_bss_end = .);\r\n  } > ram\r\n}\r\n\r\nPROVIDE(end = .);\r\n_end            = .;\r\n\r\n__heap_base__   = _end;\r\n__heap_end__    = __ram_end__;\r\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ca66da94b8e7fa9f4f5855d392d65cab18c0c591","subject":"bootloader_test: Allocating 32KB for the bootloader.","message":"bootloader_test: Allocating 32KB for the bootloader.\n","repos":"andrewparlane\/kinetis_test_projects,andrewparlane\/kinetis_test_projects","old_file":"frdm_k66f_board\/bootloader_test\/kds\/settings\/MK66FN2M0xxx18_flash_bootloader.ld","new_file":"frdm_k66f_board\/bootloader_test\/kds\/settings\/MK66FN2M0xxx18_flash_bootloader.ld","new_contents":"\/*\n** ###################################################################\n**     Processors:          MK66FN2M0VLQ18\n**                          MK66FN2M0VMD18\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015\n**     Version:             rev. 3.0, 2015-03-25\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/*\n   NOTE: This has been modified to limit the size of the bootloader.\n         Make sure that the value used in the length field for the\n         text section, is the same as is used as offsets in the app\n         linker script\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x00008000 - 0x410\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n}\n\n","old_contents":"\/*\n** ###################################################################\n**     Processors:          MK66FN2M0VLQ18\n**                          MK66FN2M0VMD18\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015\n**     Version:             rev. 3.0, 2015-03-25\n**     Build:               b151217\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright (c) 2015 Freescale Semiconductor, Inc.\n**     All rights reserved.\n**\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     o Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     o Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.freescale.com\n**     mail:                 support@freescale.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\nM_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x001FFBF0\n  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000\n  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  \/* The startup code goes first into internal flash *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  .flash_config :\n  {\n    . = ALIGN(4);\n    KEEP(*(.FlashConfig))    \/* Flash Configuration Field (FCF) *\/\n    . = ALIGN(4);\n  } > m_flash_config\n\n  \/* The program code and other data goes into internal flash *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .interrupts_ram :\n  {\n    . = ALIGN(4);\n    __VECTOR_RAM__ = .;\n    __interrupts_ram_start__ = .; \/* Create a global symbol at data start *\/\n    *(.m_interrupts_ram)     \/* This is a user defined section *\/\n    . += M_VECTOR_RAM_SIZE;\n    . = ALIGN(4);\n    __interrupts_ram_end__ = .; \/* Define a global symbol at data end *\/\n  } > m_data\n\n  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);\n  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_data\n\n  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss*)\n    . = ALIGN(512);\n    USB_RAM_START = .;\n    . += USB_RAM_GAP;\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_data\n\n  .heap :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    __HeapBase = .;\n    . += HEAP_SIZE;\n    __HeapLimit = .;\n    __heap_limit = .; \/* Add for _sbrk *\/\n  } > m_data_2\n\n  .stack :\n  {\n    . = ALIGN(8);\n    . += STACK_SIZE;\n  } > m_data_2\n\n  m_usb_bdt USB_RAM_START (NOLOAD) :\n  {\n    *(m_usb_bdt)\n    USB_RAM_BDT_END = .;\n  }\n\n  m_usb_global USB_RAM_BDT_END (NOLOAD) :\n  {\n    *(m_usb_global)\n  }\n\n  \/* Initializes stack on the end of block *\/\n  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);\n  __StackLimit = __StackTop - STACK_SIZE;\n  PROVIDE(__stack = __StackTop);\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n  ASSERT(__StackLimit >= __HeapLimit, \"region m_data_2 overflowed with stack and heap\")\n}\n\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"08beebcd83b1473f252d7a6ba7ea3bc4b8066f71","subject":"RAM region shifted by 0xC0 for vectors","message":"RAM region shifted by 0xC0 for vectors\n","repos":"EmuxEvans\/mbed,autopulated\/mbed,al177\/mbed,RonEld\/mbed,Marcomissyou\/mbed,tung7970\/mbed-os,sam-geek\/mbed,mazimkhan\/mbed-os,jeremybrodt\/mbed,adustm\/mbed,betzw\/mbed-os,struempelix\/mbed,betzw\/mbed-os,al177\/mbed,nabilbendafi\/mbed,jferreir\/mbed,devanlai\/mbed,struempelix\/mbed,andcor02\/mbed-os,rosterloh\/mbed,karsev\/mbed-os,tung7970\/mbed-os-1,hwfwgrp\/mbed,bentwire\/mbed,bcostm\/mbed-os,kpurusho\/mbed,bikeNomad\/mbed,FranklyDev\/mbed,betzw\/mbed-os,adamgreen\/mbed,mazimkhan\/mbed-os,ban4jp\/mbed,HeadsUpDisplayInc\/mbed,naves-thiago\/mbed-midi,Timmmm\/mbed,theotherjimmy\/mbed,FranklyDev\/mbed,autopulated\/mbed,jamesadevine\/mbed,al177\/mbed,FranklyDev\/mbed,Willem23\/mbed,pradeep-gr\/mbed-os5-onsemi,infinnovation\/mbed-os,nabilbendafi\/mbed,catiedev\/mbed-os,NXPmicro\/mbed,GustavWi\/mbed,nvlsianpu\/mbed,YarivCol\/mbed-os,pbrook\/mbed,jferreir\/mbed,j-greffe\/mbed-os,j-greffe\/mbed-os,mmorenobarm\/mbed-os,infinnovation\/mbed-os,andcor02\/mbed-os,FranklyDev\/mbed,DanKupiniak\/mbed,arostm\/mbed-os,DanKupiniak\/mbed,dbestm\/mbed,al177\/mbed,bcostm\/mbed-os,adamgreen\/mbed,jrjang\/mbed,K4zuki\/mbed,adamgreen\/mbed,maximmbed\/mbed,catiedev\/mbed-os,jpbrucker\/mbed,getopenmono\/mbed,Sweet-Peas\/mbed,svogl\/mbed-os,fvincenzo\/mbed-os,mmorenobarm\/mbed-os,fpiot\/mbed-ats,netzimme\/mbed-os,fpiot\/mbed-ats,arostm\/mbed-os,bulislaw\/mbed-os,iriark01\/mbed-drivers,cvtsi2sd\/mbed-os,getopenmono\/mbed,adamgreen\/mbed,xcrespo\/mbed,CalSol\/mbed,nvlsianpu\/mbed,bremoran\/mbed-drivers,pi19404\/mbed,Archcady\/mbed-os,cvtsi2sd\/mbed-os,infinnovation\/mbed-os,jamesadevine\/mbed,nvlsianpu\/mbed,JasonHow44\/mbed,ryankurte\/mbed-os,adustm\/mbed,HeadsUpDisplayInc\/mbed,fahhem\/mbed-os,RonEld\/mbed,catiedev\/mbed-os,wodji\/mbed,nRFMesh\/mbed-os,mazimkhan\/mbed-os,mikaleppanen\/mbed-os,masaohamanaka\/mbed,pbrook\/mbed,cvtsi2sd\/mbed-os,bentwire\/mbed,tung7970\/mbed-os,ban4jp\/mbed,jpbrucker\/mbed,arostm\/mbed-os,adamgreen\/mbed,infinnovation\/mbed-os,bentwire\/mbed,kl-cruz\/mbed-os,theotherjimmy\/mbed,tung7970\/mbed-os-1,pbrook\/mbed,getopenmono\/mbed,larks\/mbed,brstew\/MBED-BUILD,jpbrucker\/mbed,Marcomissyou\/mbed,NXPmicro\/mbed,HeadsUpDisplayInc\/mbed,c1728p9\/mbed-os,RonEld\/mbed,screamerbg\/mbed,c1728p9\/mbed-os,rosterloh\/mbed,fpiot\/mbed-ats,j-greffe\/mbed-os,xcrespo\/mbed,kpurusho\/mbed,HeadsUpDisplayInc\/mbed,struempelix\/mbed,DanKupiniak\/mbed,autopulated\/mbed,j-greffe\/mbed-os,adamgreen\/mbed,jferreir\/mbed,fanghuaqi\/mbed,NXPmicro\/mbed,jpbrucker\/mbed,mbedmicro\/mbed,autopulated\/mbed,brstew\/MBED-BUILD,kpurusho\/mbed,fahhem\/mbed-os,ryankurte\/mbed-os,Willem23\/mbed,pradeep-gr\/mbed-os5-onsemi,fvincenzo\/mbed-os,Marcomissyou\/mbed,devanlai\/mbed,nRFMesh\/mbed-os,xcrespo\/mbed,fvincenzo\/mbed-os,mikaleppanen\/mbed-os,Archcady\/mbed-os,tung7970\/mbed-os,adustm\/mbed,andcor02\/mbed-os,c1728p9\/mbed-os,bulislaw\/mbed-os,svogl\/mbed-os,devanlai\/mbed,sg-\/mbed-drivers,mikaleppanen\/mbed-os,maximmbed\/mbed,jeremybrodt\/mbed,rosterloh\/mbed,mmorenobarm\/mbed-os,Tiryoh\/mbed,sam-geek\/mbed,theotherjimmy\/mbed,jamesadevine\/mbed,andreaslarssonublox\/mbed,bentwire\/mbed,ryankurte\/mbed-os,screamerbg\/mbed,screamerbg\/mbed,rgrover\/mbed,alertby\/mbed,mazimkhan\/mbed-os,jferreir\/mbed,mmorenobarm\/mbed-os,fvincenzo\/mbed-os,CalSol\/mbed,xcrespo\/mbed,fvincenzo\/mbed-os,mnlipp\/mbed,larks\/mbed,monkiineko\/mbed-os,jeremybrodt\/mbed,jpbrucker\/mbed,netzimme\/mbed-os,geky\/mbed,RonEld\/mbed,Marcomissyou\/mbed,ARM-software\/mbed-beetle,ryankurte\/mbed-os,Tiryoh\/mbed,YarivCol\/mbed-os,alertby\/mbed,bcostm\/mbed-os,infinnovation\/mbed-os,hwfwgrp\/mbed,jrjang\/mbed,alertby\/mbed,pedromes\/mbed,naves-thiago\/mbed-midi,kl-cruz\/mbed-os,NordicSemiconductor\/mbed,fahhem\/mbed-os,xcrespo\/mbed,brstew\/MBED-BUILD,pedromes\/mbed,nRFMesh\/mbed-os,cvtsi2sd\/mbed-os,al177\/mbed,jamesadevine\/mbed,NXPmicro\/mbed,CalSol\/mbed,svogl\/mbed-os,pi19404\/mbed,mmorenobarm\/mbed-os,kl-cruz\/mbed-os,hwfwgrp\/mbed,alertby\/mbed,Archcady\/mbed-os,K4zuki\/mbed,pedromes\/mbed,fanghuaqi\/mbed,kl-cruz\/mbed-os,bikeNomad\/mbed,theotherjimmy\/mbed,Tiryoh\/mbed,bulislaw\/mbed-os,ryankurte\/mbed-os,hwfwgrp\/mbed,YarivCol\/mbed-os,autopulated\/mbed,mnlipp\/mbed,alertby\/mbed,dbestm\/mbed,pradeep-gr\/mbed-os5-onsemi,tung7970\/mbed-os-1,Shengliang\/mbed,bremoran\/mbed-drivers,naves-thiago\/mbed-midi,CalSol\/mbed,svastm\/mbed,rosterloh\/mbed,NitinBhaskar\/mbed,mbedmicro\/mbed,jrjang\/mbed,pedromes\/mbed,wodji\/mbed,masaohamanaka\/mbed,adustm\/mbed,CalSol\/mbed,alertby\/mbed,catiedev\/mbed-os,GustavWi\/mbed,ban4jp\/mbed,kpurusho\/mbed,getopenmono\/mbed,EmuxEvans\/mbed,j-greffe\/mbed-os,fanghuaqi\/mbed,iriark01\/mbed-drivers,Timmmm\/mbed,getopenmono\/mbed,screamerbg\/mbed,dbestm\/mbed,nRFMesh\/mbed-os,EmuxEvans\/mbed,nvlsianpu\/mbed,andcor02\/mbed-os,karsev\/mbed-os,rgrover\/mbed,GustavWi\/mbed,nabilbendafi\/mbed,andreaslarssonublox\/mbed,mazimkhan\/mbed-os,autopulated\/mbed,andcor02\/mbed-os,fahhem\/mbed-os,nvlsianpu\/mbed,kjbracey-arm\/mbed,logost\/mbed,wodji\/mbed,ryankurte\/mbed-os,brstew\/MBED-BUILD,geky\/mbed,Archcady\/mbed-os,tung7970\/mbed-os-1,jpbrucker\/mbed,JasonHow44\/mbed,andreaslarssonublox\/mbed,brstew\/MBED-BUILD,ARM-software\/mbed-beetle,Archcady\/mbed-os,NXPmicro\/mbed,devanlai\/mbed,dbestm\/mbed,theotherjimmy\/mbed,jeremybrodt\/mbed,0xc0170\/mbed-drivers,mnlipp\/mbed,fanghuaqi\/mbed,GustavWi\/mbed,netzimme\/mbed-os,ban4jp\/mbed,logost\/mbed,rgrover\/mbed,mikaleppanen\/mbed-os,betzw\/mbed-os,mbedmicro\/mbed,Timmmm\/mbed,fahhem\/mbed-os,monkiineko\/mbed-os,netzimme\/mbed-os,bikeNomad\/mbed,sam-geek\/mbed,c1728p9\/mbed-os,Sweet-Peas\/mbed,getopenmono\/mbed,bulislaw\/mbed-os,wodji\/mbed,rosterloh\/mbed,larks\/mbed,wodji\/mbed,nvlsianpu\/mbed,Shengliang\/mbed,bentwire\/mbed,Timmmm\/mbed,dbestm\/mbed,pradeep-gr\/mbed-os5-onsemi,nabilbendafi\/mbed,pradeep-gr\/mbed-os5-onsemi,struempelix\/mbed,fpiot\/mbed-ats,arostm\/mbed-os,andreaslarssonublox\/mbed,Timmmm\/mbed,mazimkhan\/mbed-os,K4zuki\/mbed,maximmbed\/mbed,pi19404\/mbed,tung7970\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,pedromes\/mbed,monkiineko\/mbed-os,brstew\/MBED-BUILD,bcostm\/mbed-os,pedromes\/mbed,Shengliang\/mbed,svogl\/mbed-os,NordicSemiconductor\/mbed,Shengliang\/mbed,mnlipp\/mbed,pi19404\/mbed,devanlai\/mbed,JasonHow44\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,karsev\/mbed-os,K4zuki\/mbed,CalSol\/mbed,jrjang\/mbed,pradeep-gr\/mbed-os5-onsemi,cvtsi2sd\/mbed-os,ban4jp\/mbed,Timmmm\/mbed,geky\/mbed,nRFMesh\/mbed-os,monkiineko\/mbed-os,jeremybrodt\/mbed,svastm\/mbed,kjbracey-arm\/mbed,ban4jp\/mbed,NXPmicro\/mbed,catiedev\/mbed-os,kl-cruz\/mbed-os,adustm\/mbed,rgrover\/mbed,mikaleppanen\/mbed-os,EmuxEvans\/mbed,mbedmicro\/mbed,jamesadevine\/mbed,karsev\/mbed-os,c1728p9\/mbed-os,GustavWi\/mbed,geky\/mbed,nRFMesh\/mbed-os,larks\/mbed,ARM-software\/mbed-beetle,K4zuki\/mbed,kl-cruz\/mbed-os,RonEld\/mbed,mnlipp\/mbed,logost\/mbed,larks\/mbed,svastm\/mbed,netzimme\/mbed-os,bikeNomad\/mbed,mnlipp\/mbed,mmorenobarm\/mbed-os,jrjang\/mbed,Willem23\/mbed,EmuxEvans\/mbed,kjbracey-arm\/mbed,bulislaw\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,hwfwgrp\/mbed,Shengliang\/mbed,fpiot\/mbed-ats,Willem23\/mbed,svastm\/mbed,RonEld\/mbed,jferreir\/mbed,DanKupiniak\/mbed,JasonHow44\/mbed,adustm\/mbed,jferreir\/mbed,Willem23\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,rgrover\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,andcor02\/mbed-os,monkiineko\/mbed-os,betzw\/mbed-os,bcostm\/mbed-os,FranklyDev\/mbed,catiedev\/mbed-os,svogl\/mbed-os,Tiryoh\/mbed,logost\/mbed,wodji\/mbed,pbrook\/mbed,geky\/mbed,Shengliang\/mbed,kjbracey-arm\/mbed,naves-thiago\/mbed-midi,Sweet-Peas\/mbed,maximmbed\/mbed,screamerbg\/mbed,bikeNomad\/mbed,svogl\/mbed-os,arostm\/mbed-os,YarivCol\/mbed-os,masaohamanaka\/mbed,betzw\/mbed-os,sg-\/mbed-drivers,HeadsUpDisplayInc\/mbed,al177\/mbed,mikaleppanen\/mbed-os,maximmbed\/mbed,monkiineko\/mbed-os,Marcomissyou\/mbed,infinnovation\/mbed-os,masaohamanaka\/mbed,sam-geek\/mbed,Archcady\/mbed-os,jrjang\/mbed,theotherjimmy\/mbed,NordicSemiconductor\/mbed,struempelix\/mbed,Marcomissyou\/mbed,tung7970\/mbed-os-1,maximmbed\/mbed,cvtsi2sd\/mbed-os,NordicSemiconductor\/mbed,devanlai\/mbed,K4zuki\/mbed,bentwire\/mbed,pbrook\/mbed,HeadsUpDisplayInc\/mbed,ARM-software\/mbed-beetle,kpurusho\/mbed,Sweet-Peas\/mbed,screamerbg\/mbed,hwfwgrp\/mbed,karsev\/mbed-os,fpiot\/mbed-ats,NitinBhaskar\/mbed,fahhem\/mbed-os,andreaslarssonublox\/mbed,kpurusho\/mbed,pi19404\/mbed,nabilbendafi\/mbed,JasonHow44\/mbed,svastm\/mbed,JasonHow44\/mbed,0xc0170\/mbed-drivers,j-greffe\/mbed-os,naves-thiago\/mbed-midi,pi19404\/mbed,larks\/mbed,nabilbendafi\/mbed,logost\/mbed,bulislaw\/mbed-os,Sweet-Peas\/mbed,NitinBhaskar\/mbed,NitinBhaskar\/mbed,rosterloh\/mbed,masaohamanaka\/mbed,NitinBhaskar\/mbed,fanghuaqi\/mbed,YarivCol\/mbed-os,YarivCol\/mbed-os,karsev\/mbed-os,jamesadevine\/mbed,naves-thiago\/mbed-midi,netzimme\/mbed-os,Sweet-Peas\/mbed,pbrook\/mbed,mbedmicro\/mbed,struempelix\/mbed,sam-geek\/mbed,Tiryoh\/mbed,tung7970\/mbed-os,logost\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,xcrespo\/mbed,dbestm\/mbed,arostm\/mbed-os,masaohamanaka\/mbed,bcostm\/mbed-os,EmuxEvans\/mbed,Tiryoh\/mbed,c1728p9\/mbed-os","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_Freescale\/TARGET_KL25Z\/TOOLCHAIN_GCC_ARM\/MKL25Z4.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_Freescale\/TARGET_KL25Z\/TOOLCHAIN_GCC_ARM\/MKL25Z4.ld","new_contents":"\/*\n * KL25Z ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH_PROTECTION\t(rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410\n  RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 16K - 0xC0\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        *(.text.Reset_Handler)\n        *(.text.System_Init)\n         . = ALIGN(4);\n    } > VECTORS\n\n    .flash_protect :\n    {\n        KEEP(*(.kinetis_flash_config_field))\n         . = ALIGN(4);\n    } > FLASH_PROTECTION\n\n    .text :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/*\n * KL25Z ARM GCC linker script file\n *\/\n\nMEMORY\n{\n  VECTORS\t(rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400\n  FLASH_PROTECTION\t(rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010\n  FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410\n  RAM (rwx) : ORIGIN = 0x1FFFF000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * _reset_init : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .isr_vector :\n    {\n        __vector_table = .;\n        KEEP(*(.vector_table))\n        *(.text.Reset_Handler)\n        *(.text.System_Init)\n         . = ALIGN(4);\n    } > VECTORS\n\n    .flash_protect :\n    {\n        KEEP(*(.kinetis_flash_config_field))\n         . = ALIGN(4);\n    } > FLASH_PROTECTION\n\n    .text :\n    {\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        \/* vectors come here, shift 0xc0 *\/\n        . = . + 0xC0;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"92d66626268a79b6cae9b2750d8a82ed7fd2f2fb","subject":"Enables hex hook","message":"Enables hex hook\n","repos":"Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos","old_file":"TARGET_NORDIC\/TARGET_NRF51822\/TOOLCHAIN_GCC_ARM\/NRF51822.ld","new_file":"TARGET_NORDIC\/TARGET_NRF51822\/TOOLCHAIN_GCC_ARM\/NRF51822.ld","new_contents":"\/* Linker script to configure memory regions. *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00014000, LENGTH = 0x2C000 \n  RAM (rwx) :  ORIGIN = 0x20002000, LENGTH = 0x2000 \n}\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.Vectors))\n\t\t*(.text*)\n\n\t\t*(.init)\n\t\t*(.fini)\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\t*(.eh_frame*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t__etext = .;\n\t\t\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\t*(.preinit_array)\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\t*(.init_array)\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\t*(.fini_array)\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\t*(.jcr)\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\t\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","old_contents":"\/* Linker script to configure memory regions. *\/\n\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000\n  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x4000\n}\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.Vectors))\n\t\t*(.text*)\n\n\t\t*(.init)\n\t\t*(.fini)\n\n\t\t\/* .ctors *\/\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t\/* .dtors *\/\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\t*(.eh_frame*)\n\t} > FLASH\n    \n\n\t.ARM.extab : \n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t__etext = .;\n\t\t\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t\/* preinit data *\/\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\t*(.preinit_array)\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t\/* init data *\/\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\t*(SORT(.init_array.*))\n\t\t*(.init_array)\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t\/* finit data *\/\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\t*(SORT(.fini_array.*))\n\t\t*(.fini_array)\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\t*(.jcr)\n\t\t. = ALIGN(4);\n\t\t\/* All data end *\/\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\t\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t\/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later *\/\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t\/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section *\/\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\t\n\t\/* Check if data + heap + stack exceeds RAM limit *\/\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"97bdc38813bc3cba30022183626937703680e46e","subject":"Tidy up.","message":"Tidy up.\n\ngit-svn-id: 43aea61533866f88f23079d48f4f5dc2d5288937@449 1d2547de-c912-0410-9cb9-b8ca96c0e9e2\n","repos":"Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,kubostech\/KubOS,Psykar\/kubos","old_file":"Demo\/ColdFire_MCF5282_Eclipse\/RTOSDemo\/m5282evb-ram-hosted.ld","new_file":"Demo\/ColdFire_MCF5282_Eclipse\/RTOSDemo\/m5282evb-ram-hosted.ld","new_contents":"\/* Linker script for m5282evb\n *\n * Version:Sourcery G++ Lite 4.2-125\n * BugURL:https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n *  Copyright 2007, 2008 CodeSourcery.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions. No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply. *\/\n\nOUTPUT_ARCH(m68k)\nENTRY(_start)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lcs3 -lcs3hosted -lcs3coldfire)\n\nMEMORY\n{\n  ram (rwx) : ORIGIN = 0x00000000, LENGTH = 16M\n  rom (rx) : ORIGIN = 0xFFE00000, LENGTH = 2M\n  rombar (rx) : ORIGIN = 0xf0000000, LENGTH = 512K\n  rambar (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\n  ipsbar (rw) : ORIGIN = 0x40000000, LENGTH = 0x20000000\n}\n\n\/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n *\/\nEXTERN(__cs3_reset_m5282evb)\nINCLUDE coldfire-names.inc\nEXTERN(__cs3_interrupt_vector_coldfire)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\nEXTERN(_start)\n\/* force exit to be picked up in a hosted or os environment *\/\nEXTERN(exit atexit)\n\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n\n  .text :\n  {\n    CREATE_OBJECT_SYMBOLS\n    __cs3_region_start_ram = .;\n    *(.cs3.region-head.ram)\n    ASSERT (. == __cs3_region_start_ram, \".cs3.region-head.ram not permitted\");\n    __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire;\n    *(.cs3.interrupt_vector)\n    \/* Make sure we pulled in an interrupt vector.  *\/\n    ASSERT (. != __cs3_interrupt_vector_coldfire, \"No interrupt vector\");\n\n    PROVIDE(__cs3_reset_m5282evb = _start);\n    __cs3_reset = __cs3_reset_m5282evb;\n    *(.cs3.reset)\n\n    *(.text .text.* .gnu.linkonce.t.*)\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.jcr))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\n    KEEP (*crtend.o(.jcr))\n\n    . = ALIGN(0x4);\n    *(.gcc_except_table .gcc_except_table.*)\n  } >ram\n  .eh_frame_hdr : ALIGN (4)\n  {\n    KEEP (*(.eh_frame_hdr))\n  } >ram\n  .eh_frame : ALIGN (4)\n  {\n    KEEP (*(.eh_frame))\n  } >ram\n  .rodata : ALIGN (4)\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n    . = ALIGN(4);\n    _init = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.init))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __preinit_array_start = .;\n    KEEP (*(.preinit_array))\n    __preinit_array_end = .;\n\n    . = ALIGN(4);\n    __init_array_start = .;\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    __init_array_end = .;\n\n    . = ALIGN(4);\n    _fini = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.fini))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __fini_array_start = .;\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    __fini_array_end = .;\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*crtend.o(.ctors))\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*crtend.o(.dtors))\n\n    *(.lit)\n\n    . = ALIGN(4);\n    __cs3_regions = .;\n    LONG (0)\n    LONG (__cs3_region_init_ram)\n    LONG (__cs3_region_start_ram)\n    LONG (__cs3_region_init_size_ram)\n    LONG (__cs3_region_zero_size_ram)\n    LONG (0)\n    LONG (__cs3_region_init_rombar)\n    LONG (__cs3_region_start_rombar)\n    LONG (__cs3_region_init_size_rombar)\n    LONG (__cs3_region_zero_size_rombar)\n    LONG (0)\n    LONG (__cs3_region_init_rambar)\n    LONG (__cs3_region_start_rambar)\n    LONG (__cs3_region_init_size_rambar)\n    LONG (__cs3_region_zero_size_rambar)\n    __cs3_regions_end = .;\n\n    . = ALIGN (8);\n    . = ALIGN (8);\n    _etext = .;\n  } >ram\n\n  .cs3.rom : ALIGN (8)\n  {\n    __cs3_region_start_rom = .;\n    *(.cs3.region-head.rom)\n    *(.rom)\n    . = ALIGN (8);\n  } >rom\n  .cs3.rom.bss :\n  {\n    *(.rom.b)\n    . = ALIGN (8);\n  } >rom\n  \/* __cs3_region_end_rom is deprecated *\/\n  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);\n  __cs3_region_size_rom = LENGTH(rom);\n  __cs3_region_init_rom = LOADADDR (.cs3.rom);\n  __cs3_region_init_size_rom = LOADADDR (.cs3.rom.bss) - LOADADDR (.cs3.rom);\n  __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);\n\n  .cs3.rombar : ALIGN (8)\n  {\n    __cs3_region_start_rombar = .;\n    *(.cs3.region-head.rombar)\n    *(.rombar)\n    . = ALIGN (8);\n  } >rombar\n  .cs3.rombar.bss :\n  {\n    *(.rombar.b)\n    . = ALIGN (8);\n  } >rombar\n  \/* __cs3_region_end_rombar is deprecated *\/\n  __cs3_region_end_rombar = __cs3_region_start_rombar + LENGTH(rombar);\n  __cs3_region_size_rombar = LENGTH(rombar);\n  __cs3_region_init_rombar = LOADADDR (.cs3.rombar);\n  __cs3_region_init_size_rombar = LOADADDR (.cs3.rombar.bss) - LOADADDR (.cs3.rombar);\n  __cs3_region_zero_size_rombar = SIZEOF(.cs3.rombar.bss);\n\n  .cs3.rambar : ALIGN (8)\n  {\n    __cs3_region_start_rambar = .;\n    *(.cs3.region-head.rambar)\n    *(.rambar)\n    . = ALIGN (8);\n  } >rambar\n  .cs3.rambar.bss :\n  {\n    *(.rambar.b)\n    . = ALIGN (8);\n  } >rambar\n  \/* __cs3_region_end_rambar is deprecated *\/\n  __cs3_region_end_rambar = __cs3_region_start_rambar + LENGTH(rambar);\n  __cs3_region_size_rambar = LENGTH(rambar);\n  __cs3_region_init_rambar = LOADADDR (.cs3.rambar);\n  __cs3_region_init_size_rambar = LOADADDR (.cs3.rambar.bss) - LOADADDR (.cs3.rambar);\n  __cs3_region_zero_size_rambar = SIZEOF(.cs3.rambar.bss);\n\n  .cs3.ipsbar :\n  {\n    __cs3_region_start_ipsbar = .;\n    *(.cs3.region-head.ipsbar)\n    . = ALIGN (8);\n  } >ipsbar\n  \/* __cs3_region_end_ipsbar is deprecated *\/\n  __cs3_region_end_ipsbar = __cs3_region_start_ipsbar + LENGTH(ipsbar);\n  __cs3_region_size_ipsbar = LENGTH(ipsbar);\n\n  .data : ALIGN (8)\n  {\n\n    *(.got.plt) *(.got)\n    *(.shdata)\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN (8);\n    *(.ram)\n    _edata = .;\n  } >ram\n  .bss :\n  {\n    *(.shbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    *(.ram.b)\n    _end = .;\n    __end = .;\n  } >ram\n  \/* __cs3_region_end_ram is deprecated *\/\n  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);\n  __cs3_region_size_ram = LENGTH(ram);\n  __cs3_region_init_ram = LOADADDR (.text);\n  __cs3_region_init_size_ram = _edata - ADDR (.text);\n  __cs3_region_zero_size_ram = _end - _edata;\n\n  .stab 0 (NOLOAD) : { *(.stab) }\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\n  \/* DWARF debug sections.\n   * Symbols in the DWARF debugging sections are relative to the beginning\n   * of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/* Linker script for m5282evb\n *\n * Version:Sourcery G++ Lite 4.2-125\n * BugURL:https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n *  Copyright 2007, 2008 CodeSourcery.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions. No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply. *\/\n\nOUTPUT_ARCH(m68k)\nENTRY(_start)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lcs3 -lcs3hosted -lcs3coldfire)\n\nMEMORY\n{\n  ram (rwx) : ORIGIN = 0x00000000, LENGTH = 16M\n  rom (rx) : ORIGIN = 0xFFE00000, LENGTH = 2M\n  rombar (rx) : ORIGIN = 0xf0000000, LENGTH = 512K\n  rambar (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\n  ipsbar (rw) : ORIGIN = 0x40000000, LENGTH = 0x20000000\n}\n\n\/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n *\/\nEXTERN(__cs3_reset_m5282evb)\nINCLUDE coldfire-names.inc\nEXTERN(__cs3_interrupt_vector_coldfire)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\nEXTERN(_start)\n\/* force exit to be picked up in a hosted or os environment *\/\nEXTERN(exit atexit)\n\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n\n  .text :\n  {\n    CREATE_OBJECT_SYMBOLS\n    __cs3_region_start_ram = .;\n    *(.cs3.region-head.ram)\n    ASSERT (. == __cs3_region_start_ram, \".cs3.region-head.ram not permitted\");\n    __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire;\n    *(.cs3.interrupt_vector)\n    \/* Make sure we pulled in an interrupt vector.  *\/\n    ASSERT (. != __cs3_interrupt_vector_coldfire, \"No interrupt vector\");\n\n    PROVIDE(__cs3_reset_m5282evb = _start);\n    __cs3_reset = __cs3_reset_m5282evb;\n    *(.cs3.reset)\n\n    *(.text .text.* .gnu.linkonce.t.*)\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.jcr))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\n    KEEP (*crtend.o(.jcr))\n\n    . = ALIGN(0x4);\n    *(.gcc_except_table .gcc_except_table.*)\n  } >ram\n  .eh_frame_hdr : ALIGN (4)\n  {\n    KEEP (*(.eh_frame_hdr))\n  } >ram\n  .eh_frame : ALIGN (4)\n  {\n    KEEP (*(.eh_frame))\n  } >ram\n  .rodata : ALIGN (4)\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n    . = ALIGN(4);\n    _init = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.init))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __preinit_array_start = .;\n    KEEP (*(.preinit_array))\n    __preinit_array_end = .;\n\n    . = ALIGN(4);\n    __init_array_start = .;\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    __init_array_end = .;\n\n    . = ALIGN(4);\n    _fini = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.fini))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __fini_array_start = .;\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    __fini_array_end = .;\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*crtend.o(.ctors))\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*crtend.o(.dtors))\n\n    *(.lit)\n\n    . = ALIGN(4);\n    __cs3_regions = .;\n    LONG (0)\n    LONG (__cs3_region_init_ram)\n    LONG (__cs3_region_start_ram)\n    LONG (__cs3_region_init_size_ram)\n    LONG (__cs3_region_zero_size_ram)\n    LONG (0)\n    LONG (__cs3_region_init_rombar)\n    LONG (__cs3_region_start_rombar)\n    LONG (__cs3_region_init_size_rombar)\n    LONG (__cs3_region_zero_size_rombar)\n    LONG (0)\n    LONG (__cs3_region_init_rambar)\n    LONG (__cs3_region_start_rambar)\n    LONG (__cs3_region_init_size_rambar)\n    LONG (__cs3_region_zero_size_rambar)\n    __cs3_regions_end = .;\n\n    . = ALIGN (8);\n    . = ALIGN (8);\n    _etext = .;\n  } >ram\n\n  .cs3.rom : ALIGN (8)\n  {\n    __cs3_region_start_rom = .;\n    *(.cs3.region-head.rom)\n    *(.rom)\n    . = ALIGN (8);\n  } >rom\n  .cs3.rom.bss :\n  {\n    *(.rom.b)\n    . = ALIGN (8);\n  } >rom\n  \/* __cs3_region_end_rom is deprecated *\/\n  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);\n  __cs3_region_size_rom = LENGTH(rom);\n  __cs3_region_init_rom = LOADADDR (.cs3.rom);\n  __cs3_region_init_size_rom = LOADADDR (.cs3.rom.bss) - LOADADDR (.cs3.rom);\n  __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);\n\n  .cs3.rombar : ALIGN (8)\n  {\n    __cs3_region_start_rombar = .;\n    *(.cs3.region-head.rombar)\n    *(.rombar)\n    . = ALIGN (8);\n  } >rombar\n  .cs3.rombar.bss :\n  {\n    *(.rombar.b)\n    . = ALIGN (8);\n  } >rombar\n  \/* __cs3_region_end_rombar is deprecated *\/\n  __cs3_region_end_rombar = __cs3_region_start_rombar + LENGTH(rombar);\n  __cs3_region_size_rombar = LENGTH(rombar);\n  __cs3_region_init_rombar = LOADADDR (.cs3.rombar);\n  __cs3_region_init_size_rombar = LOADADDR (.cs3.rombar.bss) - LOADADDR (.cs3.rombar);\n  __cs3_region_zero_size_rombar = SIZEOF(.cs3.rombar.bss);\n\n  .cs3.rambar : ALIGN (8)\n  {\n    __cs3_region_start_rambar = .;\n    *(.cs3.region-head.rambar)\n    *(.rambar)\n    . = ALIGN (8);\n  } >rambar\n  .cs3.rambar.bss :\n  {\n    *(.rambar.b)\n    . = ALIGN (8);\n  } >rambar\n  \/* __cs3_region_end_rambar is deprecated *\/\n  __cs3_region_end_rambar = __cs3_region_start_rambar + LENGTH(rambar);\n  __cs3_region_size_rambar = LENGTH(rambar);\n  __cs3_region_init_rambar = LOADADDR (.cs3.rambar);\n  __cs3_region_init_size_rambar = LOADADDR (.cs3.rambar.bss) - LOADADDR (.cs3.rambar);\n  __cs3_region_zero_size_rambar = SIZEOF(.cs3.rambar.bss);\n\n  .cs3.ipsbar :\n  {\n    __cs3_region_start_ipsbar = .;\n    *(.cs3.region-head.ipsbar)\n    . = ALIGN (8);\n  } >ipsbar\n  \/* __cs3_region_end_ipsbar is deprecated *\/\n  __cs3_region_end_ipsbar = __cs3_region_start_ipsbar + LENGTH(ipsbar);\n  __cs3_region_size_ipsbar = LENGTH(ipsbar);\n\n  .data : ALIGN (8)\n  {\n\n    *(.got.plt) *(.got)\n    *(.shdata)\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN (8);\n    *(.ram)\n    _edata = .;\n  } >rambar\n  .bss :\n  {\n    *(.shbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    *(.ram.b)\n    _end = .;\n    __end = .;\n  } >rambar\n  \/* __cs3_region_end_ram is deprecated *\/\n  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);\n  __cs3_region_size_ram = LENGTH(ram);\n  __cs3_region_init_ram = LOADADDR (.text);\n  __cs3_region_init_size_ram = _edata - ADDR (.text);\n  __cs3_region_zero_size_ram = _end - _edata;\n\n  .stab 0 (NOLOAD) : { *(.stab) }\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\n  \/* DWARF debug sections.\n   * Symbols in the DWARF debugging sections are relative to the beginning\n   * of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3fbfed928ffc3a71643fdaa7eda20b54f3032a28","subject":"refactor the bootloader!","message":"refactor the bootloader!\n","repos":"Fleurer\/fleurix,Fleurer\/fleurix,Fleurer\/fleurix","old_file":"img.ld","new_file":"img.ld","new_contents":"","old_contents":"OUTPUT_FORMAT(\"binary\")\nENTRY(\"boot\")\nSECTIONS {\n    .text 0x7c00 : {\n        *(.text)\n        *(.rodata)\n    }\n    .data : {\n        *(.data)\n    }\n}\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"0feae6ba085d7c4b92bd7c5e4ff9829a06c07384","subject":"Reduced Size of Image file","message":"Reduced Size of Image file\n","repos":"JimmyKenMerchant\/RaspberryPi,JimmyKenMerchant\/RaspberryPi","old_file":"framebuffer_test\/linker_script.ld","new_file":"framebuffer_test\/linker_script.ld","new_contents":"\/**\n * linker_script.ld\n * Author: Kenta Ishii\n * License: MIT\n * License URL: https:\/\/opensource.org\/licenses\/MIT\n *\n * Linker Script for ARM Baremetal for Raspberry Pi\n *\/\n\n\/* Wildcards before parenthesis in curly brackets mean any file to link *\/\n\nSECTIONS {\n\n\t\/* Assign Address *\/\n\t. = 0x0000;\n\t.el01_vector32 : {\n\t\taloha_vector32.o(.el01_vector)\n\t\t. = 0x1000;\n\t}\n\t. = 0x1000;\n\t.el2_vector32 : {\n\t\taloha_vector32.o(.el2_vector)\n\t\t. = 0x1000;\n\t}\n\t. = 0x2000;\n\t.el3_vector32 : {\n\t\taloha_vector32.o(.el3_vector)\n\t\t. = 0x1000;\n\t}\n\t. = 0x8000;\n\t.aloha_vector32 : {\n\t\taloha_vector32.o(.aloha_vector)\n\t\t. = 0x2000;\n\t}\n\t. = 0xA000;\n\t.system32 : {\n\t\tsystem32.o(.system)\n\t\t. += 0x00100000;\n\t}\n\t.text : {\n\t\t*(.text)\n\t}\n\n\t.data : {\n\t\t*(.data)\n\t}\n\n\t.rodata : {\n\t\t*(.rodata)\n\t}\n\t. = 0x04000000;\n\t.bss : {\n\t\t*(.bss)\n\t}\n\n}","old_contents":"\/**\n * linker_script.ld\n * Author: Kenta Ishii\n * License: MIT\n * License URL: https:\/\/opensource.org\/licenses\/MIT\n *\n * Linker Script for ARM Baremetal for Raspberry Pi\n *\/\n\n\/* Wildcards before parenthesis in curly brackets mean any file to link *\/\n\nSECTIONS {\n\n\t\/* Assign Address *\/\n\t. = 0x0000;\n\t.el01_vector32 : {\n\t\taloha_vector32.o(.el01_vector)\n\t\t. = 0x1000;\n\t}\n\t. = 0x1000;\n\t.el2_vector32 : {\n\t\taloha_vector32.o(.el2_vector)\n\t\t. = 0x1000;\n\t}\n\t. = 0x2000;\n\t.el3_vector32 : {\n\t\taloha_vector32.o(.el3_vector)\n\t\t. = 0x1000;\n\t}\n\t. = 0x8000;\n\t.aloha_vector32 : {\n\t\taloha_vector32.o(.aloha_vector)\n\t\t. = 0x2000;\n\t}\n\t. = 0xA000;\n\t.system32 : {\n\t\tsystem32.o(.system)\n\t\t\/* Add size, 16,777,216 bytes to the end of .vector *\/\n\t\t. += 0x1000000;\n\t}\n\t.text : {\n\t\t*(.text)\n\t}\n\n\t.data : {\n\t\t*(.data)\n\t}\n\n\t.rodata : {\n\t\t*(.rodata)\n\t}\n\t. = 0x04000000;\n\t.bss : {\n\t\t*(.bss)\n\t}\n\n}","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a943ccd85afed895fda20214d3c687aed3fa4437","subject":"Use internal RAM only for data.","message":"Use internal RAM only for data.\n","repos":"FreeRTOS\/FreeRTOS-Kernel,FreeRTOS\/FreeRTOS-Kernel","old_file":"Demo\/ColdFire_MCF5282_Eclipse\/RTOSDemo\/m5282evb-ram-hosted.ld","new_file":"Demo\/ColdFire_MCF5282_Eclipse\/RTOSDemo\/m5282evb-ram-hosted.ld","new_contents":"\/* Linker script for m5282evb\n *\n * Version:Sourcery G++ Lite 4.2-125\n * BugURL:https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n *  Copyright 2007, 2008 CodeSourcery.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions. No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply. *\/\n\nOUTPUT_ARCH(m68k)\nENTRY(_start)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lcs3 -lcs3hosted -lcs3coldfire)\n\nMEMORY\n{\n  ram (rwx) : ORIGIN = 0x00000000, LENGTH = 16M\n  rom (rx) : ORIGIN = 0xFFE00000, LENGTH = 2M\n  rombar (rx) : ORIGIN = 0xf0000000, LENGTH = 512K\n  rambar (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\n  ipsbar (rw) : ORIGIN = 0x40000000, LENGTH = 0x20000000\n}\n\n\/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n *\/\nEXTERN(__cs3_reset_m5282evb)\nINCLUDE coldfire-names.inc\nEXTERN(__cs3_interrupt_vector_coldfire)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\nEXTERN(_start)\n\/* force exit to be picked up in a hosted or os environment *\/\nEXTERN(exit atexit)\n\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n\n  .text :\n  {\n    CREATE_OBJECT_SYMBOLS\n    __cs3_region_start_ram = .;\n    *(.cs3.region-head.ram)\n    ASSERT (. == __cs3_region_start_ram, \".cs3.region-head.ram not permitted\");\n    __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire;\n    *(.cs3.interrupt_vector)\n    \/* Make sure we pulled in an interrupt vector.  *\/\n    ASSERT (. != __cs3_interrupt_vector_coldfire, \"No interrupt vector\");\n\n    PROVIDE(__cs3_reset_m5282evb = _start);\n    __cs3_reset = __cs3_reset_m5282evb;\n    *(.cs3.reset)\n\n    *(.text .text.* .gnu.linkonce.t.*)\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.jcr))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\n    KEEP (*crtend.o(.jcr))\n\n    . = ALIGN(0x4);\n    *(.gcc_except_table .gcc_except_table.*)\n  } >ram\n  .eh_frame_hdr : ALIGN (4)\n  {\n    KEEP (*(.eh_frame_hdr))\n  } >ram\n  .eh_frame : ALIGN (4)\n  {\n    KEEP (*(.eh_frame))\n  } >ram\n  .rodata : ALIGN (4)\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n    . = ALIGN(4);\n    _init = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.init))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __preinit_array_start = .;\n    KEEP (*(.preinit_array))\n    __preinit_array_end = .;\n\n    . = ALIGN(4);\n    __init_array_start = .;\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    __init_array_end = .;\n\n    . = ALIGN(4);\n    _fini = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.fini))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __fini_array_start = .;\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    __fini_array_end = .;\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*crtend.o(.ctors))\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*crtend.o(.dtors))\n\n    *(.lit)\n\n    . = ALIGN(4);\n    __cs3_regions = .;\n    LONG (0)\n    LONG (__cs3_region_init_ram)\n    LONG (__cs3_region_start_ram)\n    LONG (__cs3_region_init_size_ram)\n    LONG (__cs3_region_zero_size_ram)\n    LONG (0)\n    LONG (__cs3_region_init_rombar)\n    LONG (__cs3_region_start_rombar)\n    LONG (__cs3_region_init_size_rombar)\n    LONG (__cs3_region_zero_size_rombar)\n    LONG (0)\n    LONG (__cs3_region_init_rambar)\n    LONG (__cs3_region_start_rambar)\n    LONG (__cs3_region_init_size_rambar)\n    LONG (__cs3_region_zero_size_rambar)\n    __cs3_regions_end = .;\n\n    . = ALIGN (8);\n    . = ALIGN (8);\n    _etext = .;\n  } >ram\n\n  .cs3.rom : ALIGN (8)\n  {\n    __cs3_region_start_rom = .;\n    *(.cs3.region-head.rom)\n    *(.rom)\n    . = ALIGN (8);\n  } >rom\n  .cs3.rom.bss :\n  {\n    *(.rom.b)\n    . = ALIGN (8);\n  } >rom\n  \/* __cs3_region_end_rom is deprecated *\/\n  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);\n  __cs3_region_size_rom = LENGTH(rom);\n  __cs3_region_init_rom = LOADADDR (.cs3.rom);\n  __cs3_region_init_size_rom = LOADADDR (.cs3.rom.bss) - LOADADDR (.cs3.rom);\n  __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);\n\n  .cs3.rombar : ALIGN (8)\n  {\n    __cs3_region_start_rombar = .;\n    *(.cs3.region-head.rombar)\n    *(.rombar)\n    . = ALIGN (8);\n  } >rombar\n  .cs3.rombar.bss :\n  {\n    *(.rombar.b)\n    . = ALIGN (8);\n  } >rombar\n  \/* __cs3_region_end_rombar is deprecated *\/\n  __cs3_region_end_rombar = __cs3_region_start_rombar + LENGTH(rombar);\n  __cs3_region_size_rombar = LENGTH(rombar);\n  __cs3_region_init_rombar = LOADADDR (.cs3.rombar);\n  __cs3_region_init_size_rombar = LOADADDR (.cs3.rombar.bss) - LOADADDR (.cs3.rombar);\n  __cs3_region_zero_size_rombar = SIZEOF(.cs3.rombar.bss);\n\n  .cs3.rambar : ALIGN (8)\n  {\n    __cs3_region_start_rambar = .;\n    *(.cs3.region-head.rambar)\n    *(.rambar)\n    . = ALIGN (8);\n  } >rambar\n  .cs3.rambar.bss :\n  {\n    *(.rambar.b)\n    . = ALIGN (8);\n  } >rambar\n  \/* __cs3_region_end_rambar is deprecated *\/\n  __cs3_region_end_rambar = __cs3_region_start_rambar + LENGTH(rambar);\n  __cs3_region_size_rambar = LENGTH(rambar);\n  __cs3_region_init_rambar = LOADADDR (.cs3.rambar);\n  __cs3_region_init_size_rambar = LOADADDR (.cs3.rambar.bss) - LOADADDR (.cs3.rambar);\n  __cs3_region_zero_size_rambar = SIZEOF(.cs3.rambar.bss);\n\n  .cs3.ipsbar :\n  {\n    __cs3_region_start_ipsbar = .;\n    *(.cs3.region-head.ipsbar)\n    . = ALIGN (8);\n  } >ipsbar\n  \/* __cs3_region_end_ipsbar is deprecated *\/\n  __cs3_region_end_ipsbar = __cs3_region_start_ipsbar + LENGTH(ipsbar);\n  __cs3_region_size_ipsbar = LENGTH(ipsbar);\n\n  .data : ALIGN (8)\n  {\n\n    *(.got.plt) *(.got)\n    *(.shdata)\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN (8);\n    *(.ram)\n    _edata = .;\n  } >rambar\n  .bss :\n  {\n    *(.shbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    *(.ram.b)\n    _end = .;\n    __end = .;\n  } >rambar\n  \/* __cs3_region_end_ram is deprecated *\/\n  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);\n  __cs3_region_size_ram = LENGTH(ram);\n  __cs3_region_init_ram = LOADADDR (.text);\n  __cs3_region_init_size_ram = _edata - ADDR (.text);\n  __cs3_region_zero_size_ram = _end - _edata;\n\n  .stab 0 (NOLOAD) : { *(.stab) }\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\n  \/* DWARF debug sections.\n   * Symbols in the DWARF debugging sections are relative to the beginning\n   * of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n}\n","old_contents":"\/* Linker script for m5282evb\n *\n * Version:Sourcery G++ Lite 4.2-125\n * BugURL:https:\/\/support.codesourcery.com\/GNUToolchain\/\n *\n *  Copyright 2007, 2008 CodeSourcery.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions. No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply. *\/\n\nOUTPUT_ARCH(m68k)\nENTRY(_start)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lcs3 -lcs3hosted -lcs3coldfire)\n\nMEMORY\n{\n  ram (rwx) : ORIGIN = 0x00000000, LENGTH = 16M\n  rom (rx) : ORIGIN = 0xFFE00000, LENGTH = 2M\n  rombar (rx) : ORIGIN = 0xf0000000, LENGTH = 512K\n  rambar (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\n  ipsbar (rw) : ORIGIN = 0x40000000, LENGTH = 0x20000000\n}\n\n\/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n *\/\nEXTERN(__cs3_reset_m5282evb)\nINCLUDE coldfire-names.inc\nEXTERN(__cs3_interrupt_vector_coldfire)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\nEXTERN(_start)\n\/* force exit to be picked up in a hosted or os environment *\/\nEXTERN(exit atexit)\n\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) \/ 20);\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n\n  .text :\n  {\n    CREATE_OBJECT_SYMBOLS\n    __cs3_region_start_ram = .;\n    *(.cs3.region-head.ram)\n    ASSERT (. == __cs3_region_start_ram, \".cs3.region-head.ram not permitted\");\n    __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire;\n    *(.cs3.interrupt_vector)\n    \/* Make sure we pulled in an interrupt vector.  *\/\n    ASSERT (. != __cs3_interrupt_vector_coldfire, \"No interrupt vector\");\n\n    PROVIDE(__cs3_reset_m5282evb = _start);\n    __cs3_reset = __cs3_reset_m5282evb;\n    *(.cs3.reset)\n\n    *(.text .text.* .gnu.linkonce.t.*)\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.jcr))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))\n    KEEP (*crtend.o(.jcr))\n\n    . = ALIGN(0x4);\n    *(.gcc_except_table .gcc_except_table.*)\n  } >ram\n  .eh_frame_hdr : ALIGN (4)\n  {\n    KEEP (*(.eh_frame_hdr))\n  } >ram\n  .eh_frame : ALIGN (4)\n  {\n    KEEP (*(.eh_frame))\n  } >ram\n  .rodata : ALIGN (4)\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n    . = ALIGN(4);\n    _init = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.init))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __preinit_array_start = .;\n    KEEP (*(.preinit_array))\n    __preinit_array_end = .;\n\n    . = ALIGN(4);\n    __init_array_start = .;\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    __init_array_end = .;\n\n    . = ALIGN(4);\n    _fini = .;\n    LONG (0x4e560000)\t\/* linkw %fp,#0 *\/\n    KEEP(*(.fini))\n    SHORT (0x4e5e)\t\/* unlk %fp *\/\n    SHORT (0x4e75)\t\/* rts *\/\n\n    . = ALIGN(4);\n    __fini_array_start = .;\n    KEEP (*(.fini_array))\n    KEEP (*(SORT(.fini_array.*)))\n    __fini_array_end = .;\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*crtend.o(.ctors))\n\n    . = ALIGN(0x4);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*crtend.o(.dtors))\n\n    *(.lit)\n\n    . = ALIGN(4);\n    __cs3_regions = .;\n    LONG (0)\n    LONG (__cs3_region_init_ram)\n    LONG (__cs3_region_start_ram)\n    LONG (__cs3_region_init_size_ram)\n    LONG (__cs3_region_zero_size_ram)\n    LONG (0)\n    LONG (__cs3_region_init_rombar)\n    LONG (__cs3_region_start_rombar)\n    LONG (__cs3_region_init_size_rombar)\n    LONG (__cs3_region_zero_size_rombar)\n    LONG (0)\n    LONG (__cs3_region_init_rambar)\n    LONG (__cs3_region_start_rambar)\n    LONG (__cs3_region_init_size_rambar)\n    LONG (__cs3_region_zero_size_rambar)\n    __cs3_regions_end = .;\n\n    . = ALIGN (8);\n    . = ALIGN (8);\n    _etext = .;\n  } >ram\n\n  .cs3.rom : ALIGN (8)\n  {\n    __cs3_region_start_rom = .;\n    *(.cs3.region-head.rom)\n    *(.rom)\n    . = ALIGN (8);\n  } >rom\n  .cs3.rom.bss :\n  {\n    *(.rom.b)\n    . = ALIGN (8);\n  } >rom\n  \/* __cs3_region_end_rom is deprecated *\/\n  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);\n  __cs3_region_size_rom = LENGTH(rom);\n  __cs3_region_init_rom = LOADADDR (.cs3.rom);\n  __cs3_region_init_size_rom = LOADADDR (.cs3.rom.bss) - LOADADDR (.cs3.rom);\n  __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);\n\n  .cs3.rombar : ALIGN (8)\n  {\n    __cs3_region_start_rombar = .;\n    *(.cs3.region-head.rombar)\n    *(.rombar)\n    . = ALIGN (8);\n  } >rombar\n  .cs3.rombar.bss :\n  {\n    *(.rombar.b)\n    . = ALIGN (8);\n  } >rombar\n  \/* __cs3_region_end_rombar is deprecated *\/\n  __cs3_region_end_rombar = __cs3_region_start_rombar + LENGTH(rombar);\n  __cs3_region_size_rombar = LENGTH(rombar);\n  __cs3_region_init_rombar = LOADADDR (.cs3.rombar);\n  __cs3_region_init_size_rombar = LOADADDR (.cs3.rombar.bss) - LOADADDR (.cs3.rombar);\n  __cs3_region_zero_size_rombar = SIZEOF(.cs3.rombar.bss);\n\n  .cs3.rambar : ALIGN (8)\n  {\n    __cs3_region_start_rambar = .;\n    *(.cs3.region-head.rambar)\n    *(.rambar)\n    . = ALIGN (8);\n  } >rambar\n  .cs3.rambar.bss :\n  {\n    *(.rambar.b)\n    . = ALIGN (8);\n  } >rambar\n  \/* __cs3_region_end_rambar is deprecated *\/\n  __cs3_region_end_rambar = __cs3_region_start_rambar + LENGTH(rambar);\n  __cs3_region_size_rambar = LENGTH(rambar);\n  __cs3_region_init_rambar = LOADADDR (.cs3.rambar);\n  __cs3_region_init_size_rambar = LOADADDR (.cs3.rambar.bss) - LOADADDR (.cs3.rambar);\n  __cs3_region_zero_size_rambar = SIZEOF(.cs3.rambar.bss);\n\n  .cs3.ipsbar :\n  {\n    __cs3_region_start_ipsbar = .;\n    *(.cs3.region-head.ipsbar)\n    . = ALIGN (8);\n  } >ipsbar\n  \/* __cs3_region_end_ipsbar is deprecated *\/\n  __cs3_region_end_ipsbar = __cs3_region_start_ipsbar + LENGTH(ipsbar);\n  __cs3_region_size_ipsbar = LENGTH(ipsbar);\n\n  .data : ALIGN (8)\n  {\n\n    *(.got.plt) *(.got)\n    *(.shdata)\n    *(.data .data.* .gnu.linkonce.d.*)\n    . = ALIGN (8);\n    *(.ram)\n    _edata = .;\n  } >ram\n  .bss :\n  {\n    *(.shbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    *(.ram.b)\n    _end = .;\n    __end = .;\n  } >ram\n  \/* __cs3_region_end_ram is deprecated *\/\n  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);\n  __cs3_region_size_ram = LENGTH(ram);\n  __cs3_region_init_ram = LOADADDR (.text);\n  __cs3_region_init_size_ram = _edata - ADDR (.text);\n  __cs3_region_zero_size_ram = _end - _edata;\n\n  .stab 0 (NOLOAD) : { *(.stab) }\n  .stabstr 0 (NOLOAD) : { *(.stabstr) }\n  \/* DWARF debug sections.\n   * Symbols in the DWARF debugging sections are relative to the beginning\n   * of the section so we begin them at 0.  *\/\n  \/* DWARF 1 *\/\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  \/* GNU DWARF 1 extensions *\/\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  \/* DWARF 1.1 and DWARF 2 *\/\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  \/* DWARF 2 *\/\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  \/* SGI\/MIPS DWARF 2 extensions *\/\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n}\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"871ba41a0972ccd9e619192ab1dc5c720cb3d772","subject":"bootloader: Remove unnecessary KEEP on data\/bss sections, save static RAM","message":"bootloader: Remove unnecessary KEEP on data\/bss sections, save static RAM\n","repos":"Hermiedapwdrman\/esp-idf,armada-ai\/esp-idf,ajs124\/esp-idf,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,Hermiedapwdrman\/esp-idf,dschaefer\/esp-idf,jaracil\/esp-idf,empoweredhomes\/esp-idf,armada-ai\/esp-idf,nineisk\/esp-idf,www220\/esp-idf,ajs124\/esp-idf,dschaefer\/esp-idf,shukyisme\/esp-idf-kwik,dschaefer\/esp-idf,espressif\/esp-idf,MIhanguangyi\/esp-idf,shukyisme\/esp-idf-kwik,MIhanguangyi\/esp-idf,armada-ai\/esp-idf,ajs124\/esp-idf,MIhanguangyi\/esp-idf,espressif\/esp-idf,Hermiedapwdrman\/esp-idf,mashaoze\/esp-idf,dschaefer\/esp-idf,empoweredhomes\/esp-idf,nineisk\/esp-idf,empoweredhomes\/esp-idf,empoweredhomes\/esp-idf,jaracil\/esp-idf,empoweredhomes\/esp-idf,dschaefer\/esp-idf,shukyisme\/esp-idf-kwik,mashaoze\/esp-idf,Hermiedapwdrman\/esp-idf,jaracil\/esp-idf,MIhanguangyi\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,nineisk\/esp-idf,armada-ai\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf,MIhanguangyi\/esp-idf,nineisk\/esp-idf,www220\/esp-idf,www220\/esp-idf,jaracil\/esp-idf,ajs124\/esp-idf,shukyisme\/esp-idf-kwik,www220\/esp-idf,Hermiedapwdrman\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/esp32.bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/esp32.bootloader.ld","new_contents":"\/*\nLinker file used to link the bootloader.\n*\/\n\n\n\/* Simplified memory map for the bootloader\n\n   The main purpose is to make sure the bootloader can load into main memory\n   without overwriting itself.\n*\/\nMEMORY\n{\n  \/* I\/O *\/\n  dport0_seg (RW) :                 \torg = 0x3FF00000, len = 0x10\n  \/* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, the main app enables APP CPU cache *\/\n  iram_seg (RWX) :           org = 0x40078000, len = 0x8000\n  \/* 64k at the end of DRAM, after ROM bootloader stack *\/\n  dram_seg (RW) :                  \torg = 0x3FFF0000, len = 0x10000\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n  .iram1.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","old_contents":"\/*\nLinker file used to link the bootloader.\n*\/\n\n\n\/* Simplified memory map for the bootloader\n\n   The main purpose is to make sure the bootloader can load into main memory\n   without overwriting itself.\n*\/\nMEMORY\n{\n  \/* I\/O *\/\n  dport0_seg (RW) :                 \torg = 0x3FF00000, len = 0x10\n  \/* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, the main app enables APP CPU cache *\/\n  iram_seg (RWX) :           org = 0x40078000, len = 0x8000\n  \/* 64k at the end of DRAM, after ROM bootloader stack *\/\n  dram_seg (RW) :                  \torg = 0x3FFF0000, len = 0x10000\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n  .iram1.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    KEEP(*(.bss))\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    KEEP(*(.data))\n    KEEP(*(.data.*))\n    KEEP(*(.gnu.linkonce.d.*))\n    KEEP(*(.data1))\n    KEEP(*(.sdata))\n    KEEP(*(.sdata.*))\n    KEEP(*(.gnu.linkonce.s.*))\n    KEEP(*(.sdata2))\n    KEEP(*(.sdata2.*))\n    KEEP(*(.gnu.linkonce.s2.*))\n    KEEP(*(.jcr))\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e8ceb3bfa144f536f5eb5f0cbd80888a36438ac7","subject":"DISCO_F413ZH: correct ram length in GCC ld file","message":"DISCO_F413ZH: correct ram length in GCC ld file\n","repos":"mbedmicro\/mbed,Archcady\/mbed-os,NXPmicro\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,ryankurte\/mbed-os,andcor02\/mbed-os,infinnovation\/mbed-os,NXPmicro\/mbed,adamgreen\/mbed,bcostm\/mbed-os,fahhem\/mbed-os,mazimkhan\/mbed-os,infinnovation\/mbed-os,c1728p9\/mbed-os,Archcady\/mbed-os,NXPmicro\/mbed,kjbracey-arm\/mbed,bcostm\/mbed-os,catiedev\/mbed-os,karsev\/mbed-os,mazimkhan\/mbed-os,CalSol\/mbed,betzw\/mbed-os,YarivCol\/mbed-os,infinnovation\/mbed-os,catiedev\/mbed-os,andcor02\/mbed-os,HeadsUpDisplayInc\/mbed,nRFMesh\/mbed-os,CalSol\/mbed,ryankurte\/mbed-os,CalSol\/mbed,nRFMesh\/mbed-os,adamgreen\/mbed,c1728p9\/mbed-os,mbedmicro\/mbed,YarivCol\/mbed-os,YarivCol\/mbed-os,HeadsUpDisplayInc\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,CalSol\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,monkiineko\/mbed-os,nRFMesh\/mbed-os,adamgreen\/mbed,NXPmicro\/mbed,kjbracey-arm\/mbed,pradeep-gr\/mbed-os5-onsemi,mazimkhan\/mbed-os,HeadsUpDisplayInc\/mbed,Archcady\/mbed-os,andcor02\/mbed-os,adamgreen\/mbed,pradeep-gr\/mbed-os5-onsemi,infinnovation\/mbed-os,monkiineko\/mbed-os,ryankurte\/mbed-os,bcostm\/mbed-os,fahhem\/mbed-os,HeadsUpDisplayInc\/mbed,monkiineko\/mbed-os,mazimkhan\/mbed-os,betzw\/mbed-os,infinnovation\/mbed-os,mazimkhan\/mbed-os,karsev\/mbed-os,Archcady\/mbed-os,fahhem\/mbed-os,c1728p9\/mbed-os,YarivCol\/mbed-os,pradeep-gr\/mbed-os5-onsemi,andcor02\/mbed-os,svogl\/mbed-os,mbedmicro\/mbed,infinnovation\/mbed-os,nRFMesh\/mbed-os,betzw\/mbed-os,adamgreen\/mbed,NXPmicro\/mbed,betzw\/mbed-os,c1728p9\/mbed-os,svogl\/mbed-os,c1728p9\/mbed-os,YarivCol\/mbed-os,fahhem\/mbed-os,pradeep-gr\/mbed-os5-onsemi,svogl\/mbed-os,svogl\/mbed-os,mbedmicro\/mbed,mbedmicro\/mbed,CalSol\/mbed,fahhem\/mbed-os,karsev\/mbed-os,nRFMesh\/mbed-os,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,bcostm\/mbed-os,monkiineko\/mbed-os,YarivCol\/mbed-os,ryankurte\/mbed-os,catiedev\/mbed-os,catiedev\/mbed-os,andcor02\/mbed-os,nRFMesh\/mbed-os,ryankurte\/mbed-os,karsev\/mbed-os,Archcady\/mbed-os,bcostm\/mbed-os,Archcady\/mbed-os,karsev\/mbed-os,catiedev\/mbed-os,svogl\/mbed-os,karsev\/mbed-os,CalSol\/mbed,catiedev\/mbed-os,kjbracey-arm\/mbed,ryankurte\/mbed-os,fahhem\/mbed-os,monkiineko\/mbed-os,NXPmicro\/mbed,adamgreen\/mbed,bcostm\/mbed-os,svogl\/mbed-os,HeadsUpDisplayInc\/mbed,monkiineko\/mbed-os,mazimkhan\/mbed-os","old_file":"targets\/TARGET_STM\/TARGET_STM32F4\/TARGET_STM32F413xH\/device\/TOOLCHAIN_GCC_ARM\/STM32F413xH.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32F4\/TARGET_STM32F413xH\/device\/TOOLCHAIN_GCC_ARM\/STM32F413xH.ld","new_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1536K\n  RAM (rwx)  : ORIGIN = 0x200001D8, LENGTH = 320K - 0x1D8\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script to configure memory regions. *\/\nMEMORY\n{ \n  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1536K\n  RAM (rwx)  : ORIGIN = 0x200001D8, LENGTH = 320K - 0x1C4\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   _estack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab :\n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n    _sidata = .;\n\n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        _sdata = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE_HIDDEN (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE_HIDDEN (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE_HIDDEN (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE_HIDDEN (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE_HIDDEN (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE_HIDDEN (__fini_array_end = .);\n\n        KEEP(*(.jcr*))\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n        _edata = .;\n\n    } > RAM\n\n    .bss :\n    {\n        . = ALIGN(4);\n        __bss_start__ = .;\n        _sbss = .;\n        *(.bss*)\n        *(COMMON)\n        . = ALIGN(4);\n        __bss_end__ = .;\n        _ebss = .;\n    } > RAM\n\n    .heap (COPY):\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy (COPY):\n    {\n        *(.stack*)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    _estack = __StackTop;\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n\n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"005b9da3d5233f1f76013543d4817eaf36956a75","subject":"[bsp] update gcc nocache section","message":"[bsp] update gcc nocache section\n","repos":"ArdaFu\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,wolfgangz2013\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,igou\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,igou\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,geniusgogo\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,zhaojuntao\/rt-thread,yongli3\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,yongli3\/rt-thread,yongli3\/rt-thread,ArdaFu\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,armink\/rt-thread,weety\/rt-thread,igou\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,weiyuliang\/rt-thread,ArdaFu\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,AubrCool\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,yongli3\/rt-thread,weety\/rt-thread,wolfgangz2013\/rt-thread","old_file":"bsp\/imxrt1052-evk\/Libraries\/gcc\/MIMXRT1052xxxxx_flexspi_nor.ld","new_file":"bsp\/imxrt1052-evk\/Libraries\/gcc\/MIMXRT1052xxxxx_flexspi_nor.ld","new_contents":"\/*\n** ###################################################################\n**     Processors:          MIMXRT1052CVL5A\n**                          MIMXRT1052DVL6A\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    IMXRT1050RM Rev.C, 08\/2017\n**     Version:             rev. 0.1, 2017-01-10\n**     Build:               b170927\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright 2016 Freescale Semiconductor, Inc.\n**     Copyright 2016-2017 NXP\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     1. Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     2. Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     3. Neither the name of the copyright holder nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.nxp.com\n**     mail:                 support@nxp.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_boot_data           (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00000400\n  m_image_vertor_table  (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00000400\n\n  m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400\n  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00\n\n  m_itcm                (RW)  : ORIGIN = 0x00000000, LENGTH = 0x00020000\n  m_dtcm                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000\n  m_ocram               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00040000\n\n  m_sdram               (RW)  : ORIGIN = 0x80000000, LENGTH = 0x01E00000\n  m_nocache             (RW)  : ORIGIN = 0x81E00000, LENGTH = 0x00200000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  .boot_data :\n  {\n    KEEP(*(.bootdata))\n  } > m_boot_data\n\n  .image_vertor_table :\n  {\n    KEEP(*(.ivt))\n  } > m_image_vertor_table\n\n  \/* The startup code goes first into internal RAM *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  __VECTOR_RAM = __VECTOR_TABLE;\n  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;\n\n  \/* The program code and other data goes into internal RAM *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n\n    \/* section information for finsh shell *\/\n    . = ALIGN(4);\n    __fsymtab_start = .;\n    KEEP(*(FSymTab))\n    __fsymtab_end = .;\n    . = ALIGN(4);\n    __vsymtab_start = .;\n    KEEP(*(VSymTab))\n    __vsymtab_end = .;\n    . = ALIGN(4);\n\n    \/* section information for initial. *\/\n    . = ALIGN(4);\n    __rt_init_start = .;\n    KEEP(*(SORT(.rti_fn*)))\n    __rt_init_end = .;\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(m_usb_dma_init_data)\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_dtcm\n\n  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);\n  .ncache.init : AT(__NDATA_ROM)\n  {\n    __noncachedata_start__ = .;   \/* create a global symbol at ncache data start *\/\n    *(NonCacheable.init)\n    . = ALIGN(4);\n    __noncachedata_init_end__ = .;   \/* create a global symbol at initialized ncache data end *\/\n  } > m_nocache\n  . = __noncachedata_init_end__;\n  .ncache :\n  {\n    *(NonCacheable)\n    . = ALIGN(4);\n    __noncachedata_end__ = .;     \/* define a global symbol at ncache data end *\/\n  } > m_nocache\n\n  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(m_usb_dma_noninit_data)\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_dtcm\n\n  .stack :\n  {\n    . = ALIGN(8);\n    stack_start = .;\n    . += STACK_SIZE;\n    stack_end = .;\n    __StackTop = .;\n  } > m_dtcm\n  \n  .RTT_HEAP :\n  {\n    heap_start = .;\n    . = ALIGN(8);\n  } > m_dtcm\n\n  PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm));\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n}\n\n","old_contents":"\/*\n** ###################################################################\n**     Processors:          MIMXRT1052CVL5A\n**                          MIMXRT1052DVL6A\n**\n**     Compiler:            GNU C Compiler\n**     Reference manual:    IMXRT1050RM Rev.C, 08\/2017\n**     Version:             rev. 0.1, 2017-01-10\n**     Build:               b170927\n**\n**     Abstract:\n**         Linker file for the GNU C Compiler\n**\n**     Copyright 2016 Freescale Semiconductor, Inc.\n**     Copyright 2016-2017 NXP\n**     Redistribution and use in source and binary forms, with or without modification,\n**     are permitted provided that the following conditions are met:\n**\n**     1. Redistributions of source code must retain the above copyright notice, this list\n**       of conditions and the following disclaimer.\n**\n**     2. Redistributions in binary form must reproduce the above copyright notice, this\n**       list of conditions and the following disclaimer in the documentation and\/or\n**       other materials provided with the distribution.\n**\n**     3. Neither the name of the copyright holder nor the names of its\n**       contributors may be used to endorse or promote products derived from this\n**       software without specific prior written permission.\n**\n**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n**     http:                 www.nxp.com\n**     mail:                 support@nxp.com\n**\n** ###################################################################\n*\/\n\n\/* Entry Point *\/\nENTRY(Reset_Handler)\n\nHEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;\nSTACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n  m_boot_data           (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00000400\n  m_image_vertor_table  (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00000400\n\n  m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400\n  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00\n\n  m_itcm                (RW)  : ORIGIN = 0x00000000, LENGTH = 0x00020000\n  m_dtcm                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000\n  m_ocram               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00040000\n\n  m_sdram               (RW)  : ORIGIN = 0x80000000, LENGTH = 0x01E00000\n  m_nocache             (RW)  : ORIGIN = 0x81E00000, LENGTH = 0x00200000\n}\n\n\/* Define output sections *\/\nSECTIONS\n{\n  .boot_data :\n  {\n    KEEP(*(.bootdata))\n  } > m_boot_data\n\n  .image_vertor_table :\n  {\n    KEEP(*(.ivt))\n  } > m_image_vertor_table\n\n  \/* The startup code goes first into internal RAM *\/\n  .interrupts :\n  {\n    __VECTOR_TABLE = .;\n    . = ALIGN(4);\n    KEEP(*(.isr_vector))     \/* Startup code *\/\n    . = ALIGN(4);\n  } > m_interrupts\n\n  __VECTOR_RAM = __VECTOR_TABLE;\n  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;\n\n  \/* The program code and other data goes into internal RAM *\/\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)                 \/* .text sections (code) *\/\n    *(.text*)                \/* .text* sections (code) *\/\n    *(.rodata)               \/* .rodata sections (constants, strings, etc.) *\/\n    *(.rodata*)              \/* .rodata* sections (constants, strings, etc.) *\/\n    *(.glue_7)               \/* glue arm to thumb code *\/\n    *(.glue_7t)              \/* glue thumb to arm code *\/\n    *(.eh_frame)\n    KEEP (*(.init))\n    KEEP (*(.fini))\n    . = ALIGN(4);\n\n    \/* section information for finsh shell *\/\n    . = ALIGN(4);\n    __fsymtab_start = .;\n    KEEP(*(FSymTab))\n    __fsymtab_end = .;\n    . = ALIGN(4);\n    __vsymtab_start = .;\n    KEEP(*(VSymTab))\n    __vsymtab_end = .;\n    . = ALIGN(4);\n\n    \/* section information for initial. *\/\n    . = ALIGN(4);\n    __rt_init_start = .;\n    KEEP(*(SORT(.rti_fn*)))\n    __rt_init_end = .;\n  } > m_text\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > m_text\n\n  .ARM :\n  {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } > m_text\n\n .ctors :\n  {\n    __CTOR_LIST__ = .;\n    \/* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in.  *\/\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    \/* We don't want to include the .ctor section from\n       from the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last *\/\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __CTOR_END__ = .;\n  } > m_text\n\n  .dtors :\n  {\n    __DTOR_LIST__ = .;\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    __DTOR_END__ = .;\n  } > m_text\n\n  .preinit_array :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > m_text\n\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > m_text\n\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > m_text\n\n  __etext = .;    \/* define a global symbol at end of code *\/\n  __DATA_ROM = .; \/* Symbol is used by startup for data initialization *\/\n\n  .data : AT(__DATA_ROM)\n  {\n    . = ALIGN(4);\n    __DATA_RAM = .;\n    __data_start__ = .;      \/* create a global symbol at data start *\/\n    *(m_usb_dma_init_data)\n    *(.data)                 \/* .data sections *\/\n    *(.data*)                \/* .data* sections *\/\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    __data_end__ = .;        \/* define a global symbol at data end *\/\n  } > m_dtcm\n\n  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);\n  .ncache.init : AT(__NDATA_ROM)\n  {\n    __noncachedata_start__ = .;   \/* create a global symbol at ncache data start *\/\n    *(NonCacheable.init)\n    . = ALIGN(4);\n    __noncachedata_init_end__ = .;   \/* create a global symbol at initialized ncache data end *\/\n  } > m_dtcm\n  . = __noncachedata_init_end__;\n  .ncache :\n  {\n    *(NonCacheable)\n    . = ALIGN(4);\n    __noncachedata_end__ = .;     \/* define a global symbol at ncache data end *\/\n  } > m_dtcm\n\n  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);\n  text_end = ORIGIN(m_text) + LENGTH(m_text);\n  ASSERT(__DATA_END <= text_end, \"region m_text overflowed with text and data\")\n\n  \/* Uninitialized data section *\/\n  .bss :\n  {\n    \/* This is used by the startup in order to initialize the .bss section *\/\n    . = ALIGN(4);\n    __START_BSS = .;\n    __bss_start__ = .;\n    *(m_usb_dma_noninit_data)\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n    __END_BSS = .;\n  } > m_dtcm\n\n  .stack :\n  {\n    . = ALIGN(8);\n    stack_start = .;\n    . += STACK_SIZE;\n    stack_end = .;\n    __StackTop = .;\n  } > m_dtcm\n  \n  .RTT_HEAP :\n  {\n    heap_start = .;\n    . = ALIGN(8);\n  } > m_dtcm\n\n  PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm));\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n\n}\n\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"fd15acb50f2df20ba308050989be4b7be573d74f","subject":"esp32s2: bootloader: move iram_loader segment higher","message":"esp32s2: bootloader: move iram_loader segment higher\n\nThis gives extra 16kB for the application's static .data\/.bss\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/ld\/esp32s2\/bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/ld\/esp32s2\/bootloader.ld","new_contents":"\/* Simplified memory map for the bootloader.\n * Make sure the bootloader can load into main memory without overwriting itself.\n *\/\n\n\nMEMORY\n{\n  iram_seg (RWX) :                  org = 0x40050000, len = 0x4000  \/* 16KB, SRAM Block_14 *\/\n  iram_loader_seg (RWX) :           org = 0x40054000, len = 0x4000  \/* 16KB, SRAM Block_15 *\/\n  dram_seg (RW) :                   org = 0x3FFE8000, len = 0x2800  \/* 10KB, Top of SRAM Block_16, and before ROM data and stack *\/\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_wdt.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","old_contents":"\/* Simplified memory map for the bootloader.\n * Make sure the bootloader can load into main memory without overwriting itself.\n *\/\n\n\nMEMORY\n{\n  iram_loader_seg (RWX) :           org = 0x40050000, len = 0x4000  \/* 16KB, SRAM Block_14 *\/\n  iram_seg (RWX) :                  org = 0x40054000, len = 0x4000  \/* 16KB, SRAM Block_15 *\/\n  dram_seg (RW) :                   org = 0x3FFE8000, len = 0x2800  \/* 10KB, Top of SRAM Block_16, and before ROM data and stack *\/\n}\n\n\/*  Default entry point:  *\/\nENTRY(call_start_cpu0);\n\n\nSECTIONS\n{\n\n  .iram_loader.text :\n  {\n    . = ALIGN (16);\n    _loader_text_start = ABSOLUTE(.);\n    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n     *(.iram1 .iram1.*) \/* catch stray IRAM_ATTR *\/\n    *liblog.a:(.literal .text .literal.* .text.*)\n    *libgcc.a:(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_common.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)\n    *libbootloader_support.a:secure_boot_signatures.*(.literal .text .literal.* .text.*)\n    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)\n    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)\n    *libsoc.a:rtc_wdt.*(.literal .text .literal.* .text.*)\n    *libefuse.a:*.*(.literal .text .literal.* .text.*)\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _loader_text_end = ABSOLUTE(.);\n  } > iram_loader_seg\n\n  .iram.text :\n  {\n    . = ALIGN (16);\n    *(.entry.text)\n    *(.init.literal)\n    *(.init)\n  } > iram_seg\n\n\n  \/* Shared RAM *\/\n  .dram0.bss (NOLOAD) :\n  {\n    . = ALIGN (8);\n    _bss_start = ABSOLUTE(.);\n    *(.dynsbss)\n    *(.sbss)\n    *(.sbss.*)\n    *(.gnu.linkonce.sb.*)\n    *(.scommon)\n    *(.sbss2)\n    *(.sbss2.*)\n    *(.gnu.linkonce.sb2.*)\n    *(.dynbss)\n    *(.bss)\n    *(.bss.*)\n    *(.gnu.linkonce.b.*)\n    *(COMMON)\n    . = ALIGN (8);\n    _bss_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.data :\n  {\n    _data_start = ABSOLUTE(.);\n    *(.data)\n    *(.data.*)\n    *(.gnu.linkonce.d.*)\n    *(.data1)\n    *(.sdata)\n    *(.sdata.*)\n    *(.gnu.linkonce.s.*)\n    *(.sdata2)\n    *(.sdata2.*)\n    *(.gnu.linkonce.s2.*)\n    *(.jcr)\n    _data_end = ABSOLUTE(.);\n  } >dram_seg\n\n  .dram0.rodata :\n  {\n    _rodata_start = ABSOLUTE(.);\n    *(.rodata)\n    *(.rodata.*)\n    *(.gnu.linkonce.r.*)\n    *(.rodata1)\n    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);\n    *(.xt_except_table)\n    *(.gcc_except_table)\n    *(.gnu.linkonce.e.*)\n    *(.gnu.version_r)\n    *(.eh_frame)\n    . = (. + 3) & ~ 3;\n    \/*  C++ constructor and destructor tables, properly ordered:  *\/\n    __init_array_start = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.ctors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n    __init_array_end = ABSOLUTE(.);\n    KEEP (*crtbegin.*(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n    \/*  C++ exception handlers table:  *\/\n    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);\n    *(.xt_except_desc)\n    *(.gnu.linkonce.h.*)\n    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);\n    *(.xt_except_desc_end)\n    *(.dynamic)\n    *(.gnu.version_d)\n    _rodata_end = ABSOLUTE(.);\n\t\/* Literals are also RO data. *\/\n    _lit4_start = ABSOLUTE(.);\n    *(*.lit4)\n    *(.lit4.*)\n    *(.gnu.linkonce.lit4.*)\n    _lit4_end = ABSOLUTE(.);\n    . = ALIGN(4);\n    _heap_start = ABSOLUTE(.);\n  } >dram_seg\n\n  .iram.text :\n  {\n    _stext = .;\n    _text_start = ABSOLUTE(.);\n    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\n    *(.iram .iram.*) \/* catch stray IRAM_ATTR *\/\n    *(.fini.literal)\n    *(.fini)\n    *(.gnu.version)\n    _text_end = ABSOLUTE(.);\n    _etext = .;\n  } > iram_seg\n\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"42fb2ee819946144445a1c9b8eb2e426ca2c6f7e","subject":"Rewrote linker script","message":"Rewrote linker script\n","repos":"shockkolate\/shockk-os,shockkolate\/shockk-os,shockkolate\/shockk-os","old_file":"link.ld","new_file":"link.ld","new_contents":"ENTRY(entry)\nSECTIONS\n{\n\t.text BLOCK(512) : ALIGN(512)\n\t{\n\t\t*(.text)\n\t}\n\n\t.rodata BLOCK(512) : ALIGN(512)\n\t{\n\t\t*(.rodata)\n\t}\n\n\t.data BLOCK(512) : ALIGN(512)\n\t{\n\t\t*(.data)\n\t}\n\n\t.bss BLOCK(512) : ALIGN(512)\n\t{\n\t\t*(COMMON)\n\t\t*(.bss)\n\t}\n}\n","old_contents":"ENTRY(entry)\nSECTIONS\n{\n\t.text :\n\t{\n\t\t*(.text)\n\t\t. = ALIGN(512);\n\t}\n\n\t.data :\n\t{\n\t\t*(.data)\n\t\t. = ALIGN(512);\n\t}\n\n\t.rodata :\n\t{\n\t\t*(.rodata)\n\t\t. = ALIGN(512);\n\t}\n\n\t.bss :\n\t{\n\t\t*(.bss)\n\t\t. = ALIGN(512);\n\t}\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"520105aaa7ecf7453e1ddceb1f97724ae15513dc","subject":"nrf52\/boards: Tuning linker script for nrf52832 when using iot softdevice. Need more heap for LCD framebuffer.","message":"nrf52\/boards: Tuning linker script for nrf52832 when using iot softdevice. Need more heap for LCD framebuffer.\n","repos":"adafruit\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,tralamazza\/micropython,tralamazza\/micropython","old_file":"nrf5\/boards\/nrf52832_aa_s1xx.ld","new_file":"nrf5\/boards\/nrf52832_aa_s1xx.ld","new_contents":"\/*\n    GNU linker script for NRF52 w\/ s1xx prototype3 softdevice (IPv6)\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x0001F000, LENGTH = 0x061000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x0001F000, LENGTH = 0x000400 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x0001F400, LENGTH = 0x060c00 \/* 396 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20002800, LENGTH = 0x00D800 \/* 54 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 8K;\n_minimum_heap_size = 28K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x2000a800; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","old_contents":"\/*\n    GNU linker script for NRF52 w\/ s1xx prototype3 softdevice (IPv6)\n*\/\n\n\/* Specify the memory areas *\/\nMEMORY\n{\n    FLASH (rx)      : ORIGIN = 0x0001F000, LENGTH = 0x061000 \/* entire flash, 512 KiB *\/\n    FLASH_ISR (rx)  : ORIGIN = 0x0001F000, LENGTH = 0x000400 \/* sector 0, 4 KiB *\/\n    FLASH_TEXT (rx) : ORIGIN = 0x0001F400, LENGTH = 0x060c00 \/* 396 KiB *\/\n    RAM (xrw)       : ORIGIN = 0x20002800, LENGTH = 0x00D800 \/* 54 KiB *\/\n}\n \n\/* produce a link error if there is not this amount of RAM for these sections *\/\n_minimum_stack_size = 16K;\n_minimum_heap_size = 20K;\n \n\/* top end of the stack *\/\n\n\/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*\/\n_estack = ORIGIN(RAM) + LENGTH(RAM);\n\n\/* RAM extents for the garbage collector *\/\n_ram_end = ORIGIN(RAM) + LENGTH(RAM);\n_heap_end = 0x20008800; \/* tunable *\/\n\nINCLUDE \"boards\/common.ld\"\n","returncode":0,"stderr":"","license":"mit","lang":"Linker Script"}
{"commit":"a060155877bd13142570785b516d1c012e6ba9a4","subject":"Add search path","message":"Add search path\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_xxaa.ld","new_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_xxaa.ld","new_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\nMEMORY\n{\n\tFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000\n\tRAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x8000\n}\r\n\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"\r\n","old_contents":"OUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\r\nSEARCH_DIR(.)\r\nSEARCH_DIR(\"..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/src\")\r\nSEARCH_DIR(\"..\/..\/..\/..\/..\/..\/EHAL\/ARM\/src\")\r\nGROUP(-lgcc -lc -lnosys -lCMSIS)\r\n\nMEMORY\n{\n\tFLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000\n\tRAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x8000\n}\r\n\r\n\r\nINCLUDE \"gcc_arm_flash.ld\"\r\n","returncode":0,"stderr":"","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"8c795148b5b292fdaf27145b8c6e66182649be49","subject":"move base flash","message":"move base flash\n","repos":"tock\/libtock-rs","old_file":"layout.ld","new_file":"layout.ld","new_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x00040030, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        KEEP (*(.text._start))\n        *(.text*)\n        *(.rodata*)\n\n        \/* C++ exception unwinding information *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH =0xFF\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += 1024;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += 1024;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += 1024;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n}\n","old_contents":"\/* Userland Generic Layout\n *\n * This linker script is designed for Tock apps where the end microcontroller\n * is not known. Therefore, this script over provisions space on some platforms.\n *\/\n\n\/* Memory Spaces Definitions, 448K flash, 64K ram *\/\nPROG_LENGTH = 0x00040000;\nRAM_LENGTH  = 0x00010000;\n\nENTRY(_start)\n\n\/* Note: Because apps are relocated, the FLASH address here acts as a sentinel\n * value for relocation fixup routines. The application loader will select the\n * actual location in flash where the app is placed.\n *\/\nMEMORY {\n    FLASH (rx) : ORIGIN = 0x00030030, LENGTH = PROG_LENGTH\n    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH\n}\n\nSECTIONS {\n\/* Text section, Code! *\/\n    .text :\n    {\n        _text = .;\n        KEEP (*(.text._start))\n        *(.text*)\n        *(.rodata*)\n\n        \/* C++ exception unwinding information *\/\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH =0xFF\n\n\/* ARM Exception support\n *\n * This contains compiler-generated support for unwinding the stack,\n * consisting of key-value pairs of function addresses and information on\n * how to unwind stack frames.\n * https:\/\/wiki.linaro.org\/KenWerner\/Sandbox\/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf\n *\n * .ARM.exidx is sorted, so has to go in its own output section.\n *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      \/* (C++) Index entries for section unwinding *\/\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n\/* Beginning of SRAM *\/\n    _sram_start = .;\n\n\/* Global Offset Table *\/\n    .got :\n    {\n        _got = .;\n        *(.got*)\n        _egot = .;\n        _plt = .;\n        *(.got.plt*)\n        _eplt = .;\n    } > SRAM AT > FLASH\n\n\/* Data section, static initialized variables\n *  Note: This is placed in Flash after the text section, but needs to be\n *  moved to SRAM at runtime\n *\/\n    .data :\n    {\n        _data = .;\n        KEEP(*(.data*))\n        _edata = .;\n    } > SRAM AT > FLASH\n\n\/* BSS section, static uninitialized variables *\/\n    .bss :\n    {\n        _bss = .;\n        KEEP(*(.bss*))\n        *(COMMON)\n        _ebss = .;\n    } > SRAM\n\n\/*\n * __NOTE__: The following symbols are used only to pass information\n * through the elf -> tbf -> Tock kernel.\n *\n * The kernel will place the stack at the beginning of the SRAM section so\n * that stack overflows run off the end of the memory segment and trigger an\n * MPU violation instead of overwriting data\/got\/bss information. This means\n * the actual location of symbols in those sections in memory will be offset\n * by STACK_SIZE.\n *\/\n    .stack :\n    {\n        _stack = .;\n        . += 1024;\n        _estack = .;\n    } > SRAM\n\n    .app_heap :\n    {\n        _app_heap = .;\n        . += 1024;\n        _eapp_heap = .;\n    } > SRAM\n\n    .kernel_heap :\n    {\n        _kernel_heap = .;\n        . += 1024;\n        _ekernel_heap = .;\n    } > SRAM\n\n    _sram_end = .;\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"29bf6c712b73147b61c419c33301e685aca78bbd","subject":"cortexm_common: add .noinit section","message":"cortexm_common: add .noinit section\n\nMake it possible to specify a section of RAM that is not touched by\nthe init routing so data can be kept across resets.\n\nThis should behave the same as on atmega & lpc2387.\n","repos":"authmillenon\/RIOT,aeneby\/RIOT,ant9000\/RIOT,aeneby\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,yogo1212\/RIOT,x3ro\/RIOT,RIOT-OS\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,smlng\/RIOT,mfrey\/RIOT,smlng\/RIOT,OTAkeys\/RIOT,OTAkeys\/RIOT,yogo1212\/RIOT,rfuentess\/RIOT,kaspar030\/RIOT,basilfx\/RIOT,cladmi\/RIOT,aeneby\/RIOT,toonst\/RIOT,kYc0o\/RIOT,josephnoir\/RIOT,smlng\/RIOT,basilfx\/RIOT,kYc0o\/RIOT,rfuentess\/RIOT,OlegHahm\/RIOT,smlng\/RIOT,mfrey\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,mtausig\/RIOT,kYc0o\/RIOT,miri64\/RIOT,mfrey\/RIOT,OlegHahm\/RIOT,mfrey\/RIOT,basilfx\/RIOT,x3ro\/RIOT,toonst\/RIOT,ant9000\/RIOT,toonst\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,mtausig\/RIOT,x3ro\/RIOT,authmillenon\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,rfuentess\/RIOT,jasonatran\/RIOT,cladmi\/RIOT,OTAkeys\/RIOT,x3ro\/RIOT,josephnoir\/RIOT,kaspar030\/RIOT,mtausig\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,mfrey\/RIOT,josephnoir\/RIOT,rfuentess\/RIOT,cladmi\/RIOT,jasonatran\/RIOT,toonst\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,yogo1212\/RIOT,miri64\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,aeneby\/RIOT,RIOT-OS\/RIOT,toonst\/RIOT,jasonatran\/RIOT,cladmi\/RIOT,jasonatran\/RIOT,kaspar030\/RIOT,mtausig\/RIOT,josephnoir\/RIOT,smlng\/RIOT,yogo1212\/RIOT,ant9000\/RIOT,OTAkeys\/RIOT,mtausig\/RIOT,kYc0o\/RIOT,RIOT-OS\/RIOT,aeneby\/RIOT,OTAkeys\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,josephnoir\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,miri64\/RIOT,basilfx\/RIOT,cladmi\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* This is only used by gdb to understand where to start *\/\nENTRY(reset_handler_default)\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _isr_vectors = DEFINED(_isr_vectors) ? _isr_vectors : . ;\n        KEEP(*(SORT(.vectors*)))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        KEEP (*(.puf))\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate :\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        KEEP (*(.openocd .openocd.*))\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram AT> rom\n\n    \/*\n     * collect all uninitialized sections that go into RAM\n     *\/\n    .noinit (NOLOAD) :\n    {\n        __noinit_start = .;\n        *(.noinit)\n        . = ALIGN(4);\n        __noinit_end = .;\n    }  > ram\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n}\n","old_contents":"\/* ----------------------------------------------------------------------------\n *         SAM Software Package License\n * ----------------------------------------------------------------------------\n * Copyright (c) 2012, Atmel Corporation\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following condition is met:\n *\n * - Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the disclaimer below.\n *\n * Atmel's name may not be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL \"AS IS\" AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * ----------------------------------------------------------------------------\n *\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nSEARCH_DIR(.)\n\n\/* This is only used by gdb to understand where to start *\/\nENTRY(reset_handler_default)\n\n\/* Section Definitions *\/\nSECTIONS\n{\n    .text :\n    {\n        . = ALIGN(4);\n        _sfixed = .;\n        _isr_vectors = DEFINED(_isr_vectors) ? _isr_vectors : . ;\n        KEEP(*(SORT(.vectors*)))\n        *(.text .text.* .gnu.linkonce.t.*)\n        *(.glue_7t) *(.glue_7)\n        *(.rodata .rodata* .gnu.linkonce.r.*)\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n\n        \/* Support C constructors, and C destructors in both user code\n           and the C library. This also provides support for C++ code. *\/\n        . = ALIGN(4);\n        KEEP(*(.init))\n        . = ALIGN(4);\n        __preinit_array_start = .;\n        KEEP (*(.preinit_array))\n        __preinit_array_end = .;\n\n        . = ALIGN(4);\n        __init_array_start = .;\n        KEEP (*(SORT(.init_array.*)))\n        KEEP (*(.init_array))\n        __init_array_end = .;\n\n        . = ALIGN(0x4);\n        KEEP (*crtbegin.o(.ctors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n        KEEP (*(SORT(.ctors.*)))\n        KEEP (*crtend.o(.ctors))\n\n        . = ALIGN(4);\n        KEEP(*(.fini))\n\n        . = ALIGN(4);\n        __fini_array_start = .;\n        KEEP (*(.fini_array))\n        KEEP (*(SORT(.fini_array.*)))\n        __fini_array_end = .;\n\n        KEEP (*crtbegin.o(.dtors))\n        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n        KEEP (*(SORT(.dtors.*)))\n        KEEP (*crtend.o(.dtors))\n\n        . = ALIGN(4);\n        _efixed = .;            \/* End of text section *\/\n    } > rom\n\n    \/* .ARM.exidx is sorted, so has to go in its own output section.  *\/\n    PROVIDE_HIDDEN (__exidx_start = .);\n    .ARM.exidx :\n    {\n      *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > rom\n    PROVIDE_HIDDEN (__exidx_end = .);\n\n    \/* exception handling *\/\n    . = ALIGN(4);\n    .eh_frame :\n    {\n        KEEP (*(.eh_frame))\n    } > rom\n\n    . = ALIGN(4);\n    _etext = .;\n\n    \/* stack section *\/\n    .stack (NOLOAD):\n    {\n        KEEP (*(.puf))\n        . = ALIGN(8);\n        _sstack = .;\n        KEEP (*(.isr_stack))\n        . = ALIGN(8);\n        _estack = .;\n    } > ram\n\n    .relocate :\n    {\n        . = ALIGN(4);\n        _srelocate = .;\n        *(.ramfunc .ramfunc.*);\n        *(.data .data.*);\n        KEEP (*(.openocd .openocd.*))\n        . = ALIGN(4);\n        _erelocate = .;\n    } > ram AT> rom\n\n    \/* .bss section which is used for uninitialized data *\/\n    .bss (NOLOAD) :\n    {\n        . = ALIGN(4);\n        _sbss = . ;\n        _szero = .;\n        *(.bss .bss.*)\n        *(COMMON)\n        . = ALIGN(4);\n        _ebss = . ;\n        _ezero = .;\n    } > ram\n\n    \/* heap section *\/\n    . = ALIGN(4);\n    _sheap = . ;\n    _eheap = ORIGIN(ram) + LENGTH(ram);\n\n    \/* Populate information about ram size *\/\n    _sram = ORIGIN(ram);\n    _eram = ORIGIN(ram) + LENGTH(ram);\n}\n","returncode":0,"stderr":"","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"95b4abc9fb9e7d0bd6b4dbd5702d694b513abad4","subject":"Pin the reflection data sections on Linux","message":"Pin the reflection data sections on Linux\n\nThese had similar problems to the protocol conformance sections during\nLinux bringup. There are relative offsets from the main reflection\nsection to the two string sections, so their position relative to each\nother must remain fixed.\n","repos":"swiftix\/swift,swiftix\/swift,nathawes\/swift,tjw\/swift,tinysun212\/swift-windows,gregomni\/swift,hooman\/swift,benlangmuir\/swift,austinzheng\/swift,JaSpa\/swift,devincoughlin\/swift,nathawes\/swift,milseman\/swift,gmilos\/swift,zisko\/swift,dduan\/swift,parkera\/swift,brentdax\/swift,allevato\/swift,parkera\/swift,shajrawi\/swift,roambotics\/swift,ben-ng\/swift,modocache\/swift,karwa\/swift,felix91gr\/swift,danielmartin\/swift,devincoughlin\/swift,JGiola\/swift,jmgc\/swift,bitjammer\/swift,ken0nek\/swift,danielmartin\/swift,russbishop\/swift,uasys\/swift,alblue\/swift,KrishMunot\/swift,djwbrown\/swift,dduan\/swift,Jnosh\/swift,jmgc\/swift,benlangmuir\/swift,amraboelela\/swift,tkremenek\/swift,milseman\/swift,alblue\/swift,deyton\/swift,tardieu\/swift,frootloops\/swift,jckarter\/swift,ahoppen\/swift,IngmarStein\/swift,manavgabhawala\/swift,austinzheng\/swift,xedin\/swift,gregomni\/swift,tardieu\/swift,JaSpa\/swift,practicalswift\/swift,xwu\/swift,parkera\/swift,IngmarStein\/swift,codestergit\/swift,zisko\/swift,nathawes\/swift,therealbnut\/swift,tinysun212\/swift-windows,tinysun212\/swift-windows,felix91gr\/swift,CodaFi\/swift,parkera\/swift,apple\/swift,rudkx\/swift,ben-ng\/swift,modocache\/swift,tkremenek\/swift,huonw\/swift,frootloops\/swift,devincoughlin\/swift,gmilos\/swift,jtbandes\/swift,djwbrown\/swift,glessard\/swift,bitjammer\/swift,harlanhaskins\/swift,modocache\/swift,dduan\/swift,airspeedswift\/swift,amraboelela\/swift,practicalswift\/swift,huonw\/swift,jckarter\/swift,sschiau\/swift,hooman\/swift,roambotics\/swift,calebd\/swift,jtbandes\/swift,sschiau\/swift,jopamer\/swift,jtbandes\/swift,sschiau\/swift,harlanhaskins\/swift,gribozavr\/swift,atrick\/swift,gottesmm\/swift,rudkx\/swift,gribozavr\/swift,lorentey\/swift,airspeedswift\/swift,shahmishal\/swift,hooman\/swift,manavgabhawala\/swift,zisko\/swift,djwbrown\/swift,CodaFi\/swift,stephentyrone\/swift,JaSpa\/swift,gregomni\/swift,Jnosh\/swift,brentdax\/swift,deyton\/swift,lorentey\/swift,jckarter\/swift,gottesmm\/swift,codestergit\/swift,gribozavr\/swift,xwu\/swift,ken0nek\/swift,jtbandes\/swift,brentdax\/swift,KrishMunot\/swift,jmgc\/swift,jopamer\/swift,tkremenek\/swift,hughbe\/swift,austinzheng\/swift,austinzheng\/swift,nathawes\/swift,deyton\/swift,tardieu\/swift,manavgabhawala\/swift,shajrawi\/swift,xedin\/swift,frootloops\/swift,CodaFi\/swift,bitjammer\/swift,jopamer\/swift,jopamer\/swift,glessard\/swift,apple\/swift,therealbnut\/swift,jtbandes\/swift,SwiftAndroid\/swift,bitjammer\/swift,hughbe\/swift,SwiftAndroid\/swift,devincoughlin\/swift,lorentey\/swift,xedin\/swift,KrishMunot\/swift,practicalswift\/swift,karwa\/swift,dreamsxin\/swift,ahoppen\/swift,kperryua\/swift,return\/swift,gregomni\/swift,return\/swift,arvedviehweger\/swift,JGiola\/swift,benlangmuir\/swift,swiftix\/swift,therealbnut\/swift,xedin\/swift,lorentey\/swift,tkremenek\/swift,danielmartin\/swift,alblue\/swift,modocache\/swift,harlanhaskins\/swift,amraboelela\/swift,practicalswift\/swift,arvedviehweger\/swift,codestergit\/swift,alblue\/swift,aschwaighofer\/swift,parkera\/swift,hughbe\/swift,xwu\/swift,hooman\/swift,kstaring\/swift,danielmartin\/swift,kperryua\/swift,calebd\/swift,russbishop\/swift,huonw\/swift,shahmishal\/swift,hooman\/swift,gregomni\/swift,dduan\/swift,SwiftAndroid\/swift,rudkx\/swift,bitjammer\/swift,devincoughlin\/swift,JaSpa\/swift,shahmishal\/swift,atrick\/swift,calebd\/swift,gmilos\/swift,allevato\/swift,apple\/swift,kstaring\/swift,swiftix\/swift,zisko\/swift,jmgc\/swift,calebd\/swift,kperryua\/swift,zisko\/swift,shahmishal\/swift,rudkx\/swift,sschiau\/swift,milseman\/swift,karwa\/swift,glessard\/swift,kperryua\/swift,natecook1000\/swift,johnno1962d\/swift,codestergit\/swift,huonw\/swift,tjw\/swift,felix91gr\/swift,djwbrown\/swift,OscarSwanros\/swift,johnno1962d\/swift,dduan\/swift,alblue\/swift,hughbe\/swift,ken0nek\/swift,IngmarStein\/swift,brentdax\/swift,ahoppen\/swift,therealbnut\/swift,uasys\/swift,apple\/swift,roambotics\/swift,glessard\/swift,manavgabhawala\/swift,gmilos\/swift,apple\/swift,nathawes\/swift,Jnosh\/swift,ken0nek\/swift,hughbe\/swift,JGiola\/swift,apple\/swift,johnno1962d\/swift,KrishMunot\/swift,ben-ng\/swift,ken0nek\/swift,return\/swift,harlanhaskins\/swift,xedin\/swift,stephentyrone\/swift,gribozavr\/swift,nathawes\/swift,parkera\/swift,ben-ng\/swift,OscarSwanros\/swift,gregomni\/swift,hooman\/swift,gribozavr\/swift,russbishop\/swift,airspeedswift\/swift,tkremenek\/swift,return\/swift,jmgc\/swift,tjw\/swift,tjw\/swift,jckarter\/swift,gmilos\/swift,aschwaighofer\/swift,sschiau\/swift,russbishop\/swift,tkremenek\/swift,IngmarStein\/swift,shahmishal\/swift,johnno1962d\/swift,hughbe\/swift,kstaring\/swift,xwu\/swift,aschwaighofer\/swift,rudkx\/swift,airspeedswift\/swift,JGiola\/swift,hughbe\/swift,natecook1000\/swift,jtbandes\/swift,jckarter\/swift,rudkx\/swift,jmgc\/swift,devincoughlin\/swift,karwa\/swift,kstaring\/swift,airspeedswift\/swift,therealbnut\/swift,devincoughlin\/swift,kstaring\/swift,return\/swift,karwa\/swift,frootloops\/swift,lorentey\/swift,ahoppen\/swift,danielmartin\/swift,natecook1000\/swift,CodaFi\/swift,stephentyrone\/swift,shajrawi\/swift,tardieu\/swift,ben-ng\/swift,milseman\/swift,jopamer\/swift,zisko\/swift,swiftix\/swift,felix91gr\/swift,OscarSwanros\/swift,OscarSwanros\/swift,JaSpa\/swift,arvedviehweger\/swift,gottesmm\/swift,allevato\/swift,airspeedswift\/swift,atrick\/swift,IngmarStein\/swift,SwiftAndroid\/swift,devincoughlin\/swift,roambotics\/swift,stephentyrone\/swift,felix91gr\/swift,natecook1000\/swift,arvedviehweger\/swift,uasys\/swift,milseman\/swift,russbishop\/swift,russbishop\/swift,brentdax\/swift,uasys\/swift,ken0nek\/swift,harlanhaskins\/swift,tjw\/swift,amraboelela\/swift,jmgc\/swift,aschwaighofer\/swift,JaSpa\/swift,allevato\/swift,alblue\/swift,huonw\/swift,russbishop\/swift,milseman\/swift,jopamer\/swift,shahmishal\/swift,shajrawi\/swift,tardieu\/swift,tkremenek\/swift,calebd\/swift,karwa\/swift,tardieu\/swift,xedin\/swift,manavgabhawala\/swift,johnno1962d\/swift,danielmartin\/swift,deyton\/swift,calebd\/swift,harlanhaskins\/swift,felix91gr\/swift,JaSpa\/swift,OscarSwanros\/swift,tinysun212\/swift-windows,arvedviehweger\/swift,austinzheng\/swift,KrishMunot\/swift,tinysun212\/swift-windows,karwa\/swift,atrick\/swift,djwbrown\/swift,gottesmm\/swift,glessard\/swift,practicalswift\/swift,johnno1962d\/swift,xedin\/swift,deyton\/swift,gribozavr\/swift,uasys\/swift,modocache\/swift,gmilos\/swift,benlangmuir\/swift,practicalswift\/swift,therealbnut\/swift,deyton\/swift,Jnosh\/swift,brentdax\/swift,milseman\/swift,kperryua\/swift,jopamer\/swift,nathawes\/swift,johnno1962d\/swift,roambotics\/swift,modocache\/swift,allevato\/swift,gottesmm\/swift,JGiola\/swift,benlangmuir\/swift,airspeedswift\/swift,dduan\/swift,djwbrown\/swift,benlangmuir\/swift,sschiau\/swift,harlanhaskins\/swift,return\/swift,parkera\/swift,bitjammer\/swift,stephentyrone\/swift,KrishMunot\/swift,ahoppen\/swift,allevato\/swift,alblue\/swift,tinysun212\/swift-windows,swiftix\/swift,manavgabhawala\/swift,KrishMunot\/swift,huonw\/swift,atrick\/swift,aschwaighofer\/swift,shajrawi\/swift,dduan\/swift,natecook1000\/swift,arvedviehweger\/swift,lorentey\/swift,CodaFi\/swift,gribozavr\/swift,huonw\/swift,kstaring\/swift,sschiau\/swift,aschwaighofer\/swift,gmilos\/swift,tardieu\/swift,shahmishal\/swift,stephentyrone\/swift,jtbandes\/swift,frootloops\/swift,amraboelela\/swift,codestergit\/swift,natecook1000\/swift,manavgabhawala\/swift,gottesmm\/swift,swiftix\/swift,arvedviehweger\/swift,shajrawi\/swift,hooman\/swift,danielmartin\/swift,kstaring\/swift,uasys\/swift,Jnosh\/swift,frootloops\/swift,lorentey\/swift,ben-ng\/swift,tjw\/swift,aschwaighofer\/swift,bitjammer\/swift,uasys\/swift,jckarter\/swift,practicalswift\/swift,return\/swift,frootloops\/swift,SwiftAndroid\/swift,djwbrown\/swift,lorentey\/swift,gottesmm\/swift,ahoppen\/swift,xwu\/swift,atrick\/swift,codestergit\/swift,therealbnut\/swift,OscarSwanros\/swift,xwu\/swift,CodaFi\/swift,karwa\/swift,amraboelela\/swift,xwu\/swift,austinzheng\/swift,Jnosh\/swift,tjw\/swift,ben-ng\/swift,parkera\/swift,felix91gr\/swift,dreamsxin\/swift,glessard\/swift,SwiftAndroid\/swift,shajrawi\/swift,kperryua\/swift,austinzheng\/swift,allevato\/swift,jckarter\/swift,CodaFi\/swift,stephentyrone\/swift,Jnosh\/swift,natecook1000\/swift,xedin\/swift,gribozavr\/swift,deyton\/swift,OscarSwanros\/swift,ken0nek\/swift,zisko\/swift,practicalswift\/swift,modocache\/swift,brentdax\/swift,tinysun212\/swift-windows,IngmarStein\/swift,SwiftAndroid\/swift,roambotics\/swift,calebd\/swift,shahmishal\/swift,IngmarStein\/swift,sschiau\/swift,codestergit\/swift,shajrawi\/swift,kperryua\/swift,amraboelela\/swift,JGiola\/swift","old_file":"stdlib\/public\/runtime\/swift.ld","new_file":"stdlib\/public\/runtime\/swift.ld","new_contents":"SECTIONS\n{\n  .swift3_typeref : { *(.swift3_typeref) },\n  .swift3_reflstr : { *(.swift3_reflstr) },\n  .swift3_reflect : { *(.swift3_reflect) },\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","old_contents":"SECTIONS\n{\n  .swift2_protocol_conformances :\n  {\n    .swift2_protocol_conformances_start = . ;\n    QUAD(SIZEOF(.swift2_protocol_conformances) - 8) ;\n    *(.swift2_protocol_conformances) ;\n  },\n  .swift2_type_metadata :\n  {\n    .swift2_type_metadata_start = . ;\n    QUAD(SIZEOF(.swift2_type_metadata) - 8) ;\n    *(.swift2_type_metadata) ;\n  }\n}\nINSERT AFTER .dtors\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f47b43a31a9ae9f84a5b1406e04cd2511744b2ff","subject":"delete ARMv7-M.ld linker script","message":"delete ARMv7-M.ld linker script","repos":"jasmin-j\/distortos,DISTORTEC\/distortos,DISTORTEC\/distortos,DISTORTEC\/distortos,CezaryGapinski\/distortos,jasmin-j\/distortos,DISTORTEC\/distortos,CezaryGapinski\/distortos,CezaryGapinski\/distortos,jasmin-j\/distortos,jasmin-j\/distortos,CezaryGapinski\/distortos,jasmin-j\/distortos,CezaryGapinski\/distortos","old_file":"source\/architecture\/ARM\/ARMv7-M\/ARMv7-M.ld","new_file":"source\/architecture\/ARM\/ARMv7-M\/ARMv7-M.ld","new_contents":"","old_contents":"\/**\n * \\file ARMv7-M.ld\n * \\brief Generic linker script for ARMv7-M. Should not be used directly!\n *\n * \\author Copyright (C) 2014 Kamil Szczygiel http:\/\/www.distortec.com http:\/\/www.freddiechopin.info\n *\n * \\par License\n * This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0. If a copy of the MPL was not\n * distributed with this file, You can obtain one at http:\/\/mozilla.org\/MPL\/2.0\/.\n *\n * \\date 2014-11-23\n *\/\n\nSEARCH_DIR(.);\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| format configurations\n+---------------------------------------------------------------------------------------------------------------------*\/\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\");\nOUTPUT_ARCH(arm);\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| stacks sizes\n+---------------------------------------------------------------------------------------------------------------------*\/\n\n\/* sizes of stacks should come from parent file *\/\n\nPROVIDE(__main_stack_size = __main_stack_size);\nPROVIDE(__process_stack_size = __process_stack_size);\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| available memories definitions\n+---------------------------------------------------------------------------------------------------------------------*\/\n\n\/* sizes of MEMORY regions should come from parent file *\/\n\n__rom_start = ORIGIN(rom);\n__rom_size = LENGTH(rom);\n__rom_end = __rom_start + __rom_size;\n\nPROVIDE(__rom_start = __rom_start);\nPROVIDE(__rom_size = __rom_size);\nPROVIDE(__rom_end = __rom_end);\n\n__ram_start = ORIGIN(ram);\n__ram_size = LENGTH(ram);\n__ram_end = __ram_start + __ram_size;\n\nPROVIDE(__ram_start = __ram_start);\nPROVIDE(__ram_size = __ram_size);\nPROVIDE(__ram_end = __ram_end);\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| entry point\n+---------------------------------------------------------------------------------------------------------------------*\/\n\nENTRY(Reset_Handler);\n\n\/*---------------------------------------------------------------------------------------------------------------------+\n| put data in sections\n+---------------------------------------------------------------------------------------------------------------------*\/\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\t. = ALIGN(4);\n\t\t__text_start = .;\n\t\tPROVIDE(__text_start = __text_start);\n\n\t\t\/* sub-section: .vectors *\/\n\n\t\t. = ALIGN(4);\n\t\t__vectors_start = .;\n\t\tPROVIDE(__vectors_start = __vectors_start);\n\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.coreVectors));\n\t\tKEEP(*(.chipVectors));\n\n\t\t. = ALIGN(4);\n\t\t__vectors_end = .;\n\t\tPROVIDE(__vectors_end = __vectors_end);\n\n\t\t\/* end of sub-section: .vectors *\/\n\n\t\t. = ALIGN(4);\n\t\t*(.text);\n\t\t. = ALIGN(4);\n\t\t*(.text.*);\n\t\t. = ALIGN(4);\n\t\t*(.gnu.linkonce.t.*);\n\t\t. = ALIGN(4);\n\t\t*(.glue_7t .glue_7);\n\t\t. = ALIGN(4);\n\t\t*(.rodata .rodata.* .gnu.linkonce.r.*);\n\n\t\t. = ALIGN(4);\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*);\t\/* exception unwinding information *\/\n\t\t. = ALIGN(4);\n\t\t*(.gcc_except_table);\t\t\t\t\t\t\/* information used for stack unwinding during exception *\/\n\t\t. = ALIGN(4);\n\t\t*(.eh_frame_hdr);\t\t\t\t\t\t\t\/* additional information about .ex_frame section *\/\n\t\t. = ALIGN(4);\n\t\t*(.eh_frame);\t\t\t\t\t\t\t\t\/* information used for stack unwinding during exception *\/\n\n\t\t\/* sub-section: data_array *\/\n\n\t\t. = ALIGN(4);\n\t\t__data_array_start = .;\n\t\tPROVIDE(__data_array_start = __data_array_start);\n\n\t\tLONG(LOADADDR(.data)); LONG(ADDR(.data)); LONG(ADDR(.data) + SIZEOF(.data));\n\n\t\t. = ALIGN(4);\n\t\t__data_array_end = .;\n\t\tPROVIDE(__data_array_end = __data_array_end);\n\n\t\t\/* end of sub-section: data_array *\/\n\n\t\t\/* sub-section: bss_array *\/\n\n\t\t. = ALIGN(4);\n\t\t__bss_array_start = .;\n\t\tPROVIDE(__bss_array_start = __bss_array_start);\n\n\t\tLONG(ADDR(.bss)); LONG(ADDR(.bss) + SIZEOF(.bss));\n\t\tLONG(ADDR(.stack)); LONG(ADDR(.stack) + SIZEOF(.stack));\n\n\t\t. = ALIGN(4);\n\t\t__bss_array_end = .;\n\t\tPROVIDE(__bss_array_end = __bss_array_end);\n\n\t\t\/* end of sub-section: bss_array *\/\n\n\t\t\/* sub-sections: init, preinit_array, init_array and fini_array *\/\n\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init));\n\t\t. = ALIGN(4);\n\t\t__preinit_array_start = .;\n\t\tKEEP(*(.preinit_array));\n\t\t. = ALIGN(4);\n\t\t__preinit_array_end = .;\n\t\t__init_array_start = .;\n\t\tKEEP(*(SORT(.init_array.*)));\n\t\t. = ALIGN(4);\n\t\tKEEP(*(.init_array));\n\t\t. = ALIGN(4);\n\t\t__init_array_end = .;\n\t\tKEEP(*(.fini));\n\t\t. = ALIGN(4);\n\t\t__fini_array_start = .;\n\t\tKEEP(*(.fini_array));\n\t\t. = ALIGN(4);\n\t\tKEEP(*(SORT(.fini_array.*)));\n\t\t. = ALIGN(4);\n\t\t__fini_array_end = .;\n\n\t\t\/* end of sub-sections: init, preinit_array, init_array and fini_array *\/\n\n\t\t. = ALIGN(4);\n\t\t__text_end = .;\n\t\tPROVIDE(__text_end = __text_end);\n\t} > rom AT > rom\n\n\t. = ALIGN(4);\n\t__exidx_start = .;\n\tPROVIDE(__exidx_start = __exidx_start);\n\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*);\n\t} > rom AT > rom\t\t\t\t\t\t\t\t\/* index entries for section unwinding *\/\n\n\t. = ALIGN(4);\n\t__exidx_end = .;\n\tPROVIDE(__exidx_end = __exidx_end);\n\n\t.data :\n\t{\n\t\t. = ALIGN(4);\n\t\t__data_init_start = LOADADDR(.data);\n\t\tPROVIDE(__data_init_start = __data_init_start);\n\t\t__data_start = .;\n\t\tPROVIDE(__data_start = __data_start);\n\n\t\t. = ALIGN(4);\n\t\t*(.data .data.* .gnu.linkonce.d.*)\n\n\t\t. = ALIGN(4);\n\t\t__data_end = .;\n\t\tPROVIDE(__data_end = __data_end);\n\t} > ram AT > rom\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start = .;\n\t\tPROVIDE(__bss_start = __bss_start);\n\n\t\t. = ALIGN(4);\n\t\t*(.bss .bss.* .gnu.linkonce.b.*)\n\t\t. = ALIGN(4);\n\t\t*(COMMON);\n\n\t\t. = ALIGN(4);\n\t\t__bss_end = .;\n\t\tPROVIDE(__bss_end = __bss_end);\n\t} > ram AT > ram\n\n\t.stack :\n\t{\n\t\t. = ALIGN(8);\n\t\t__stack_start = .;\n\t\tPROVIDE(__stack_start = __stack_start);\n\n\t\t. = ALIGN(8);\n\t\t__main_stack_start = .;\n\t\tPROVIDE(__main_stack_start = __main_stack_start);\n\n\t\t. += __main_stack_size;\n\n\t\t. = ALIGN(8);\n\t\t__main_stack_end = .;\n\t\tPROVIDE(__main_stack_end = __main_stack_end);\n\n\t\t. = ALIGN(8);\n\t\t__process_stack_start = .;\n\t\tPROVIDE(__process_stack_start = __process_stack_start);\n\n\t\t. += __process_stack_size;\n\n\t\t. = ALIGN(8);\n\t\t__process_stack_end = .;\n\t\tPROVIDE(__process_stack_end = __process_stack_end);\n\n\t\t. = ALIGN(8);\n\t\t__stack_end = .;\n\t\tPROVIDE(__stack_end = __stack_end);\n\t} > ram AT > ram\n\n\t. = ALIGN(4);\n\t__heap_start = .;\n\tPROVIDE(__heap_start = __heap_start);\n\n\t. = ALIGN(4);\n\t__heap_end = __ram_end;\n\tPROVIDE(__heap_end = __heap_end);\n\n\t.stab \t\t\t\t0 (NOLOAD) : { *(.stab) }\n\t.stabstr \t\t\t0 (NOLOAD) : { *(.stabstr) }\n\t\/* DWARF debug sections.\n\t* Symbols in the DWARF debugging sections are relative to the beginning\n\t* of the section so we begin them at 0. *\/\n\t\/* DWARF 1 *\/\n\t.debug\t\t\t\t0 : { *(.debug) }\n\t.line\t\t\t\t0 : { *(.line) }\n\t\/* GNU DWARF 1 extensions *\/\n\t.debug_srcinfo\t\t0 : { *(.debug_srcinfo) }\n\t.debug_sfnames\t\t0 : { *(.debug_sfnames) }\n\t\/* DWARF 1.1 and DWARF 2 *\/\n\t.debug_aranges\t\t0 : { *(.debug_aranges) }\n\t.debug_pubnames\t\t0 : { *(.debug_pubnames) }\n\t\/* DWARF 2 *\/\n\t.debug_info\t\t\t0 : { *(.debug_info .gnu.linkonce.wi.*) }\n\t.debug_abbrev\t\t0 : { *(.debug_abbrev) }\n\t.debug_line\t\t\t0 : { *(.debug_line) }\n\t.debug_frame\t\t0 : { *(.debug_frame) }\n\t.debug_str\t\t\t0 : { *(.debug_str) }\n\t.debug_loc\t\t\t0 : { *(.debug_loc) }\n\t.debug_macinfo\t\t0 : { *(.debug_macinfo) }\n\t\/* SGI\/MIPS DWARF 2 extensions *\/\n\t.debug_weaknames\t0 : { *(.debug_weaknames) }\n\t.debug_funcnames\t0 : { *(.debug_funcnames) }\n\t.debug_typenames\t0 : { *(.debug_typenames) }\n\t.debug_varnames\t\t0 : { *(.debug_varnames) }\n\n\t.note.gnu.arm.ident\t0 : { KEEP(*(.note.gnu.arm.ident)) }\n\t.ARM.attributes\t\t0 : { KEEP(*(.ARM.attributes)) }\n\t\/DISCARD\/\t\t\t\t: { *(.note.GNU-stack) }\n}\n\nPROVIDE(__text_size = __text_end - __text_start);\n\tPROVIDE(__vectors_size = __vectors_end - __vectors_start);\nPROVIDE(__exidx_size = __exidx_end - __exidx_start);\nPROVIDE(__data_size = __data_end - __data_start);\nPROVIDE(__bss_size = __bss_end - __bss_start);\nPROVIDE(__stack_size = __stack_end - __stack_start);\nPROVIDE(__heap_size = __heap_end - __heap_start);\n\nPROVIDE(__bss_start__ = __bss_start);\nPROVIDE(__bss_end__ = __bss_end);\n","returncode":0,"stderr":"","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"52a950bbe6b8e3e1d6c4de57b41519da8a2ab63b","subject":"soc: riscv: openisa_rv32m1: Conver to new devicetree macros","message":"soc: riscv: openisa_rv32m1: Conver to new devicetree macros\n\nConvert DT_CODE_PARTITION_{OFFSET,SIZE} to use new\nDT_REG_ADDR\/DT_REG_SIZE macros instead based on\nDT_CHOSEN(zephyr_code_partition).\n\nSigned-off-by: Kumar Gala <a5e5248af4cd4f0ed8c515f61d40a6e2db46a66e@linaro.org>\n","repos":"Vudentz\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,nashif\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,nashif\/zephyr,finikorg\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,galak\/zephyr,nashif\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,finikorg\/zephyr,galak\/zephyr,nashif\/zephyr","old_file":"soc\/riscv\/openisa_rv32m1\/linker.ld","new_file":"soc\/riscv\/openisa_rv32m1\/linker.ld","new_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n * Copyright (c) 2018 Foundries.io Ltd\n *\n * This file is based on:\n *\n * - include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld\n * - include\/arch\/riscv\/common\/linker.ld\n * - include\/arch\/riscv\/pulpino\/linker.ld\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/*\n * Extra efforts would need to be taken to ensure the IRQ handlers are within\n * jumping distance of the vector table in non-XIP builds, so avoid them.\n *\/\n#define ROMABLE_REGION              ROM\n#define RAMABLE_REGION              RAM\n\n#define VECTOR_SIZE 0x100\n\n#ifdef CONFIG_USE_DT_CODE_PARTITION\n\n#ifdef CONFIG_BOOTLOADER_MCUBOOT\n\n\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition)))\n#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_code_partition)))\n\n#define VECTOR_BASE (ROM_BASE + CONFIG_TEXT_SECTION_OFFSET)\n\n#else\n\n#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition)))\n#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_code_partition)) - VECTOR_BASE)\n\n#define VECTOR_BASE (ROM_BASE + ROM_SIZE)\n\n#endif\n\n#else\n\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) - VECTOR_SIZE)\n\n#define VECTOR_BASE (ROM_BASE + ROM_SIZE)\n\n#endif\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\nMEMORY\n    {\n    ROM (rx)      : ORIGIN = ROM_BASE,    LENGTH = ROM_SIZE\n    \/*\n     * Each RISC-V core on this chip (RI5CY and ZERO-RISCY) has\n     * a vector table at the end of its flash bank. They are relocatable\n     * at runtime, but we need to put the reset vectors in hardcoded places.\n     *\n     * (The Arm core vector tables are at the beginning of each\n     * flash bank.)\n     *\/\n#ifndef CONFIG_BOOTLOADER_MCUBOOT\n    VECTORS (rx)  : ORIGIN = VECTOR_BASE, LENGTH = VECTOR_SIZE\n#endif\n    RAM (rwx)     : ORIGIN = RAM_BASE,    LENGTH = RAM_SIZE\n    \/*\n     * Special section, not included in the final binary, used\n     * to generate interrupt tables. See include\/linker\/intlist.ld.\n     *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROM)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t_image_text_start = .;\n\n\t*(.text .text.*)\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROM)\n\n    _image_text_end = .;\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t. = ALIGN(4);\n\t*(.srodata)\n\t*(\".srodata.*\")\n\t*(.rodata)\n\t*(.rodata.*)\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    _image_rom_end = .;\n\n#ifndef CONFIG_BOOTLOADER_MCUBOOT\n    \/* The vector table goes into core-dependent flash locations. *\/\n    SECTION_PROLOGUE(vectors,,)\n\t{\n\t_vector_start = .;\n\tKEEP(*(.vectors.*))\n\t} GROUP_LINK_IN(VECTORS)\n    _vector_end = .;\n#endif\n\n    GROUP_END(ROM)\n\n    GROUP_START(RAM)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t. = ALIGN(4);\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(.data.*)\n\t*(.gnu.linkonce.s.*)\n\n\t\/* https:\/\/groups.google.com\/a\/groups.riscv.org\/d\/msg\/sw-dev\/60IdaZj27dY\/TKT3hbNlAgAJ *\/\n\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\/*\n\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t * a multiple of 4 bytes, so it can be cleared in words.\n\t *\/\n\t . = ALIGN(4);\n\t __bss_start = .;\n\n\t *(.bss .bss.*)\n\t *(.sbss .sbss.*)\n\t COMMON_SYMBOLS\n\n\t \/* Ensure 4 byte alignment for the entire section. *\/\n\t . = ALIGN(4);\n\t  __bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t *(.noinit .noinit.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n     GROUP_END(RAM)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#ifdef CONFIG_GEN_ISR_TABLES\n\/* Bogus section, post-processed during the build to initialize interrupts. *\/\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n    \/*\n     * Pulpino toolchains emit these sections; we don't care about them,\n     * but need to avoid build system warnings about orphaned sections.\n     *\/\n    SECTION_PROLOGUE(.Pulp_Chip.Info,,)\n\t{\n\t\t*(.Pulp_Chip.*)\n\t}\n\n    }\n","old_contents":"\/*\n * Copyright (c) 2013-2014 Wind River Systems, Inc.\n * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>\n * Copyright (c) 2018 Foundries.io Ltd\n *\n * This file is based on:\n *\n * - include\/arch\/arm\/aarch32\/cortex_m\/scripts\/linker.ld\n * - include\/arch\/riscv\/common\/linker.ld\n * - include\/arch\/riscv\/pulpino\/linker.ld\n *\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n#include <devicetree.h>\n#include <autoconf.h>\n\n#include <linker\/sections.h>\n#include <linker\/linker-defs.h>\n#include <linker\/linker-tool.h>\n\n\/*\n * Extra efforts would need to be taken to ensure the IRQ handlers are within\n * jumping distance of the vector table in non-XIP builds, so avoid them.\n *\/\n#define ROMABLE_REGION              ROM\n#define RAMABLE_REGION              RAM\n\n#define VECTOR_SIZE 0x100\n\n#ifdef CONFIG_USE_DT_CODE_PARTITION\n\n#ifdef CONFIG_BOOTLOADER_MCUBOOT\n\n\n#define ROM_BASE (DT_CODE_PARTITION_OFFSET)\n#define ROM_SIZE (DT_CODE_PARTITION_SIZE)\n\n#define VECTOR_BASE (ROM_BASE + CONFIG_TEXT_SECTION_OFFSET)\n\n#else\n\n#define ROM_BASE DT_CODE_PARTITION_OFFSET\n#define ROM_SIZE (DT_CODE_PARTITION_SIZE - VECTOR_SIZE)\n\n#define VECTOR_BASE (ROM_BASE + ROM_SIZE)\n\n#endif\n\n#else\n\n#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))\n#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) - VECTOR_SIZE)\n\n#define VECTOR_BASE (ROM_BASE + ROM_SIZE)\n\n#endif\n\n#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS\n#define RAM_SIZE KB(CONFIG_SRAM_SIZE)\n\nMEMORY\n    {\n    ROM (rx)      : ORIGIN = ROM_BASE,    LENGTH = ROM_SIZE\n    \/*\n     * Each RISC-V core on this chip (RI5CY and ZERO-RISCY) has\n     * a vector table at the end of its flash bank. They are relocatable\n     * at runtime, but we need to put the reset vectors in hardcoded places.\n     *\n     * (The Arm core vector tables are at the beginning of each\n     * flash bank.)\n     *\/\n#ifndef CONFIG_BOOTLOADER_MCUBOOT\n    VECTORS (rx)  : ORIGIN = VECTOR_BASE, LENGTH = VECTOR_SIZE\n#endif\n    RAM (rwx)     : ORIGIN = RAM_BASE,    LENGTH = RAM_SIZE\n    \/*\n     * Special section, not included in the final binary, used\n     * to generate interrupt tables. See include\/linker\/intlist.ld.\n     *\/\n    IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K\n    }\n\nENTRY(CONFIG_KERNEL_ENTRY)\n\nSECTIONS\n    {\n\n#include <linker\/rel-sections.ld>\n\n    SECTION_PROLOGUE(.plt,,)\n\t{\n\t\t*(.plt)\n\t}\n\n    SECTION_PROLOGUE(.iplt,,)\n\t{\n\t\t*(.iplt)\n\t}\n\n    GROUP_START(ROM)\n    _image_rom_start = ROM_BASE;\n\n    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)\n\t{\n\n\/* Located in generated directory. This file is populated by calling\n * zephyr_linker_sources(ROM_START ...). This typically contains the vector\n * table and debug information.\n *\/\n#include <snippets-rom-start.ld>\n\n\t_image_text_start = .;\n\n\t*(.text .text.*)\n\t*(.gnu.linkonce.t.*)\n\t*(.eh_frame)\n\t} GROUP_LINK_IN(ROM)\n\n    _image_text_end = .;\n\n    _image_rodata_start = .;\n\n#include <linker\/common-rom.ld>\n\n    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)\n\t{\n\t. = ALIGN(4);\n\t*(.srodata)\n\t*(\".srodata.*\")\n\t*(.rodata)\n\t*(.rodata.*)\n\t*(.gnu.linkonce.r.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rodata.ld>\n\n\t} GROUP_LINK_IN(ROMABLE_REGION)\n\n#include <linker\/cplusplus-rom.ld>\n\n    _image_rodata_end = .;\n    _image_rom_end = .;\n\n#ifndef CONFIG_BOOTLOADER_MCUBOOT\n    \/* The vector table goes into core-dependent flash locations. *\/\n    SECTION_PROLOGUE(vectors,,)\n\t{\n\t_vector_start = .;\n\tKEEP(*(.vectors.*))\n\t} GROUP_LINK_IN(VECTORS)\n    _vector_end = .;\n#endif\n\n    GROUP_END(ROM)\n\n    GROUP_START(RAM)\n\n    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)\n\t{\n\t. = ALIGN(4);\n\t_image_ram_start = .;\n\t__data_ram_start = .;\n\n\t*(.data)\n\t*(.data.*)\n\t*(.gnu.linkonce.s.*)\n\n\t\/* https:\/\/groups.google.com\/a\/groups.riscv.org\/d\/msg\/sw-dev\/60IdaZj27dY\/TKT3hbNlAgAJ *\/\n\t*(.sdata .sdata.* .gnu.linkonce.s.*)\n\t*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-rwdata.ld>\n\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)\n\n#include <linker\/common-ram.ld>\n#include <linker\/cplusplus-ram.ld>\n\n    __data_ram_end = .;\n    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);\n\n    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)\n\t{\n\t\/*\n\t * For performance, BSS section is assumed to be 4 byte aligned and\n\t * a multiple of 4 bytes, so it can be cleared in words.\n\t *\/\n\t . = ALIGN(4);\n\t __bss_start = .;\n\n\t *(.bss .bss.*)\n\t *(.sbss .sbss.*)\n\t COMMON_SYMBOLS\n\n\t \/* Ensure 4 byte alignment for the entire section. *\/\n\t . = ALIGN(4);\n\t  __bss_end = .;\n\t} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)\n\n    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)\n\t{\n\t\/*\n\t * This section is used for non-initialized objects that\n\t * will not be cleared during the boot process.\n\t *\/\n\t *(.noinit .noinit.*)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-noinit.ld>\n\n\t} GROUP_LINK_IN(RAMABLE_REGION)\n\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-ram-sections.ld>\n\n     _image_ram_end = .;\n     _end = .; \/* end of image *\/\n\n     GROUP_END(RAM)\n\n#ifdef CONFIG_CUSTOM_SECTIONS_LD\n\/* Located in project source directory *\/\n#include <custom-sections.ld>\n#endif\n\/* Located in generated directory. This file is populated by the\n * zephyr_linker_sources() Cmake function.\n *\/\n#include <snippets-sections.ld>\n\n#ifdef CONFIG_GEN_ISR_TABLES\n\/* Bogus section, post-processed during the build to initialize interrupts. *\/\n#include <linker\/intlist.ld>\n#endif\n\n#include <linker\/debug-sections.ld>\n\n    SECTION_PROLOGUE(.riscv.attributes, 0,)\n\t{\n\tKEEP(*(.riscv.attributes))\n\tKEEP(*(.gnu.attributes))\n\t}\n    \/*\n     * Pulpino toolchains emit these sections; we don't care about them,\n     * but need to avoid build system warnings about orphaned sections.\n     *\/\n    SECTION_PROLOGUE(.Pulp_Chip.Info,,)\n\t{\n\t\t*(.Pulp_Chip.*)\n\t}\n\n    }\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"80135ff6e4087bc9c834baa8ac0ccdbf55c04d61","subject":"Compile network and RTOS with GCC_ARM","message":"Compile network and RTOS with GCC_ARM\n","repos":"Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos","old_file":"TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_file":"TARGET_NXP\/TARGET_LPC176X\/TOOLCHAIN_GCC_ARM\/LPC1768.ld","new_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    \/* Code can explicitly ask for data to be\n       placed in these higher RAM banks where\n       they will be left uninitialized.\n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n    \n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","old_contents":"\/* Linker script for mbed LPC1768 *\/\n\n\/* Linker script to configure memory regions. *\/\nMEMORY\n{\n  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K\n  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38\n\n  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\n  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\n}\n\n\/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n * \n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *\/\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n        KEEP(*(.isr_vector))\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        \/* .ctors *\/\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        \/* .dtors *\/\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        *(.rodata*)\n\n        KEEP(*(.eh_frame*))\n    } > FLASH\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > FLASH\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > FLASH\n    __exidx_end = .;\n\n    __etext = .;\n        \n    .data : AT (__etext)\n    {\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n\n        . = ALIGN(4);\n        \/* preinit data *\/\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        \/* init data *\/\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        \/* finit data *\/\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        \/* All data end *\/\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    \/* Code can explicitly ask for data to be\n       placed in these higher RAM banks where\n       they will be left uninitialized.\n    *\/\n    .AHBSRAM0 (NOLOAD):\n    {\n        Image$$RW_IRAM2$$Base = . ;\n        *(AHBSRAM0)\n        Image$$RW_IRAM2$$ZI$$Limit = .;\n    } > USB_RAM\n\n    .AHBSRAM1 (NOLOAD):\n    {\n        Image$$RW_IRAM3$$Base = . ;\n        *(AHBSRAM1)\n        Image$$RW_IRAM3$$ZI$$Limit = .;\n    } > ETH_RAM\n    \n    \/* .data_RAM2 : ALIGN(4)\n    {\n       FILL(0xff)\n        *(.data.$RAM2*)\n        *(.data.$ETH_RAM*)\n       . = ALIGN(4) ;\n    } > ETH_RAM AT>FLASH\n        \n    .bss_RAM2 : ALIGN(4)\n    {\n        *(.bss.$RAM2*)\n        *(.bss.$ETH_RAM*)\n       . = ALIGN(4) ;\n    } > ETH_RAM\n    *\/\n    \n    .bss :\n    {\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n    } > RAM\n\n    \n    .heap :\n    {\n        __end__ = .;\n        end = __end__;\n        *(.heap*)\n        __HeapLimit = .;\n    } > RAM\n\n    \/* .stack_dummy section doesn't contains any symbols. It is only\n     * used for linker to calculate size of stack sections, and assign\n     * values to stack symbols later *\/\n    .stack_dummy :\n    {\n        *(.stack)\n    } > RAM\n\n    \/* Set stack top to end of RAM, and stack limit move down by\n     * size of stack_dummy section *\/\n    __StackTop = ORIGIN(RAM) + LENGTH(RAM);\n    __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n    PROVIDE(__stack = __StackTop);\n    \n    \/* Check if data + heap + stack exceeds RAM limit *\/\n    ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ade3394f119e539b0b5877d5dc6f0cdaf99e52d8","subject":"testsuite: coverage: align rodata section","message":"testsuite: coverage: align rodata section\n\nThis adds an ALIGN statement to the rodata linker snippet\nfor coverage. Without this, sometimes the section is not\naligned, but __init_array_start indicates an aligned\naddress, resulting in incorrect function pointers.\nSo align it.\n\nSigned-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>\n","repos":"zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,galak\/zephyr,galak\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr","old_file":"subsys\/testsuite\/coverage\/coverage_rodata.ld","new_file":"subsys\/testsuite\/coverage\/coverage_rodata.ld","new_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\n. = ALIGN(4);\n\nPROVIDE_HIDDEN (__init_array_start = .);\nKEEP (*(SORT(.init_array.*)))\nKEEP (*(.init_array*))\nPROVIDE_HIDDEN (__init_array_end = .);\n","old_contents":"\/*\n * Copyright (c) 2019 Intel Corporation\n * SPDX-License-Identifier: Apache-2.0\n *\/\n\nPROVIDE_HIDDEN (__init_array_start = .);\nKEEP (*(SORT(.init_array.*)))\nKEEP (*(.init_array*))\nPROVIDE_HIDDEN (__init_array_end = .);\n","returncode":0,"stderr":"","license":"apache-2.0","lang":"Linker Script"}
{"commit":"86f605e067e38ff43997d09be50f3d76ba06df38","subject":"Added mbed layout file","message":"Added mbed layout file","repos":"farcaller\/arm-demos,farcaller\/arm-demos,farcaller\/arm-demos,farcaller\/arm-demos","old_file":"02-blink-with-systick\/platform\/mbed\/layout.ld","new_file":"02-blink-with-systick\/platform\/mbed\/layout.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/farcaller\/arm-demos.git\/': The requested URL returned error: 403\n","license":"unlicense","lang":"Linker Script"}
{"commit":"fe8f2bf1c4f3e1fcac1e619485352691b6d7c4ab","subject":"PCIe: fix section name for eth control structure","message":"PCIe: fix section name for eth control structure\n","repos":"kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa","old_file":"firmware\/iopcie\/linker.ld","new_file":"firmware\/iopcie\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kalray\/odp-mppa.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"41d874ba52f8b2be15ee3b87a1da44c94971fd0e","subject":"trivial: add linker script for armhf","message":"trivial: add linker script for armhf\n\nfixes FTBFS in Debian:\nhttps:\/\/buildd.debian.org\/status\/fetch.php?pkg=fwupd&arch=armhf&ver=1.5.7-1&stamp=1614100547&raw=0\n","repos":"hughsie\/fwupd,hughsie\/fwupd,fwupd\/fwupd,fwupd\/fwupd,hughsie\/fwupd,hughsie\/fwupd,fwupd\/fwupd,fwupd\/fwupd","old_file":"plugins\/uefi-capsule\/efi\/lds\/elf_arm_efi.lds","new_file":"plugins\/uefi-capsule\/efi\/lds\/elf_arm_efi.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/hughsie\/fwupd.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"bdf0366452599aafe2f8a1ddefe982d669fb51d9","subject":"Import CM7 ram link script","message":"Import CM7 ram link script\n\nGitOrigin-RevId: 22b0ac13db442a4989d6b3ca7997af83a2a986d2\n","repos":"google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro,google-coral\/coralmicro","old_file":"libs\/nxp\/rt1176-sdk\/MIMXRT1176xxxxx_cm7_ram.ld","new_file":"libs\/nxp\/rt1176-sdk\/MIMXRT1176xxxxx_cm7_ram.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/google-coral\/coralmicro.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6a42aae2cce6d077fe327756763cec7181dc097b","subject":"Architecture: Linker: Remove stm32_itcm.ld. Useless.","message":"Architecture: Linker: Remove stm32_itcm.ld. Useless.","repos":"dergraaf\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc","old_file":"src\/xpcc\/architecture\/platform\/linker\/stm32\/stm32_itcm.ld","new_file":"src\/xpcc\/architecture\/platform\/linker\/stm32\/stm32_itcm.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/dergraaf\/xpcc.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"56744cf728e9f9d7ee9fda2cdd27dfdd008f9c16","subject":"chip\/STMicroelectronics\/STM32F4: add STM32F4xxxG.ld","message":"chip\/STMicroelectronics\/STM32F4: add STM32F4xxxG.ld\n","repos":"jasmin-j\/distortos,jasmin-j\/distortos,CezaryGapinski\/distortos,DISTORTEC\/distortos,DISTORTEC\/distortos,jasmin-j\/distortos,CezaryGapinski\/distortos,CezaryGapinski\/distortos,CezaryGapinski\/distortos,CezaryGapinski\/distortos,jasmin-j\/distortos,jasmin-j\/distortos,DISTORTEC\/distortos,DISTORTEC\/distortos","old_file":"source\/chip\/STMicroelectronics\/STM32F4\/STM32F4xxxG.ld","new_file":"source\/chip\/STMicroelectronics\/STM32F4\/STM32F4xxxG.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/jasmin-j\/distortos.git\/': The requested URL returned error: 403\n","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"f510efc2c12cc32cc4a1c3d10dd2ad32c65c9649","subject":"build\/configs\/rtl8721csm\/scripts: Update memory region","message":"build\/configs\/rtl8721csm\/scripts: Update memory region\n\nSigned-off-by: Nitish Ambastha <fe3fdc39e03194843ec106698f0d3de8d8813ae6@samsung.com>\n","repos":"an4967\/TizenRT,sunghan-chang\/TizenRT,pillip8282\/TizenRT,an4967\/TizenRT,Samsung\/TizenRT,jeongchanKim\/TizenRT,jsdosa\/TizenRT,jeongarmy\/TizenRT,jsdosa\/TizenRT,jeongchanKim\/TizenRT,jsdosa\/TizenRT,jeongchanKim\/TizenRT,jeongarmy\/TizenRT,jeongchanKim\/TizenRT,an4967\/TizenRT,pillip8282\/TizenRT,jeongarmy\/TizenRT,jeongchanKim\/TizenRT,jeongchanKim\/TizenRT,an4967\/TizenRT,sunghan-chang\/TizenRT,jeongarmy\/TizenRT,Samsung\/TizenRT,jeongarmy\/TizenRT,an4967\/TizenRT,jsdosa\/TizenRT,sunghan-chang\/TizenRT,pillip8282\/TizenRT,junmin-kim\/TizenRT,jsdosa\/TizenRT,sunghan-chang\/TizenRT,Samsung\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,Samsung\/TizenRT,pillip8282\/TizenRT,junmin-kim\/TizenRT,junmin-kim\/TizenRT,sunghan-chang\/TizenRT,jsdosa\/TizenRT,pillip8282\/TizenRT,Samsung\/TizenRT,sunghan-chang\/TizenRT,Samsung\/TizenRT,an4967\/TizenRT,junmin-kim\/TizenRT,an4967\/TizenRT,jeongarmy\/TizenRT,junmin-kim\/TizenRT,junmin-kim\/TizenRT,jsdosa\/TizenRT,jeongarmy\/TizenRT,pillip8282\/TizenRT,jeongchanKim\/TizenRT,sunghan-chang\/TizenRT,junmin-kim\/TizenRT","old_file":"build\/configs\/rtl8721csm\/scripts\/rlx8721d_img2_ns.ld","new_file":"build\/configs\/rtl8721csm\/scripts\/rlx8721d_img2_ns.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Samsung\/TizenRT.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5174ded74c5b6dd8d1df46dc7946a4879c06927a","subject":"Reference startup file from linker script to put reset handerl at top of mem.","message":"Reference startup file from linker script to put reset handerl at top of mem.\n","repos":"openxc\/vi-firmware,openxc\/vi-firmware,ene-ilies\/vi-firmware,mgiannikouris\/vi-firmware,mgiannikouris\/vi-firmware,mgiannikouris\/vi-firmware,ene-ilies\/vi-firmware,ene-ilies\/vi-firmware,ene-ilies\/vi-firmware,mgiannikouris\/vi-firmware,openxc\/vi-firmware,openxc\/vi-firmware","old_file":"src\/lpc17xx\/LPC17xx-base.ld","new_file":"src\/lpc17xx\/LPC17xx-base.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mgiannikouris\/vi-firmware.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"06b71c085e8766dc904ec7caced6954bae8a45a5","subject":"added the linker script","message":"added the linker script\n","repos":"Ciusss89\/STM32nucleo,Ciusss89\/STM32nucleo,Ciusss89\/STM32nucleo","old_file":"system\/STM32F401CE_FLASH.ld","new_file":"system\/STM32F401CE_FLASH.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Ciusss89\/STM32nucleo.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"0a22d668c806f30185c74b30bb7a75a7794f763b","subject":"Add LDoc configuration file","message":"Add LDoc configuration file\n","repos":"xpol\/luainstaller,tst2005\/luarocks,rrthomas\/luarocks,aryajur\/luarocks,ignacio\/luarocks,xpol\/luavm,xiaq\/luarocks,xiaq\/luarocks,rrthomas\/luarocks,keplerproject\/luarocks,usstwxy\/luarocks,coderstudy\/luarocks,starius\/luarocks,tarantool\/luarocks,luarocks\/luarocks,leafo\/luarocks,xpol\/luavm,keplerproject\/luarocks,leafo\/luarocks,rrthomas\/luarocks,robooo\/luarocks,starius\/luarocks,usstwxy\/luarocks,robooo\/luarocks,tarantool\/luarocks,lxbgit\/luarocks,tst2005\/luarocks,xpol\/luavm,keplerproject\/luarocks,xpol\/luarocks,leafo\/luarocks,lxbgit\/luarocks,robooo\/luarocks,tst2005\/luarocks,ignacio\/luarocks,rrthomas\/luarocks,starius\/luarocks,aryajur\/luarocks,lxbgit\/luarocks,xpol\/luainstaller,xpol\/luainstaller,xpol\/luarocks,lxbgit\/luarocks,xiaq\/luarocks,tst2005\/luarocks,usstwxy\/luarocks,tarantool\/luarocks,ignacio\/luarocks,robooo\/luarocks,xpol\/luavm,luarocks\/luarocks,coderstudy\/luarocks,xpol\/luarocks,luarocks\/luarocks,usstwxy\/luarocks,starius\/luarocks,xpol\/luarocks,coderstudy\/luarocks,xiaq\/luarocks,xpol\/luainstaller,xpol\/luavm,ignacio\/luarocks,coderstudy\/luarocks,aryajur\/luarocks,aryajur\/luarocks,keplerproject\/luarocks","old_file":"config.ld","new_file":"config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/robooo\/luarocks.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"a7233c1f17c4305dc7886ded6d48170a581d58f1","subject":"LPC11C24 linking alignment fix","message":"LPC11C24 linking alignment fix\n","repos":"diydrones\/uavcan,Yurisu\/uavcan,xukunfeng\/uavcan,tridge\/uavcan,PX4\/uavcan,cvra\/uavcan,kobrabyte\/uavcan,cvra\/uavcan,pireerliu\/uavcan,trigrass2\/libuavcan,ilia-sheremet\/uavcan,soulsheng\/libuavcan,381426068\/uavcan,PX4\/uavcan,tridge\/uavcan,381426068\/uavcan,Yurisu\/uavcan,soulsheng\/libuavcan,pireerliu\/uavcan,tridge\/uavcan,xukunfeng\/uavcan,xukunfeng\/uavcan,3drobotics\/libuavcan,kobrabyte\/uavcan,cvra\/uavcan,PX4\/uavcan,pireerliu\/uavcan,trigrass2\/libuavcan,diydrones\/uavcan,pireerliu\/uavcan,kobrabyte\/uavcan,trigrass2\/libuavcan,ilia-sheremet\/uavcan,3drobotics\/libuavcan,ilia-sheremet\/uavcan,ilia-sheremet\/uavcan,MaxQu\/uavcan,soulsheng\/libuavcan,kobrabyte\/uavcan,diydrones\/uavcan,MaxQu\/uavcan,tridge\/uavcan,381426068\/uavcan,nuft\/uavcan,3drobotics\/libuavcan,trigrass2\/libuavcan,soulsheng\/libuavcan,PX4\/uavcan,diydrones\/uavcan,381426068\/uavcan,Yurisu\/uavcan,MaxQu\/uavcan,nuft\/uavcan,nuft\/uavcan,3drobotics\/libuavcan,Yurisu\/uavcan,MaxQu\/uavcan,nuft\/uavcan,cvra\/uavcan,xukunfeng\/uavcan","old_file":"libuavcan_drivers\/lpc11c24\/test_olimex_lpc_p11c24\/lpc11c24.ld","new_file":"libuavcan_drivers\/lpc11c24\/test_olimex_lpc_p11c24\/lpc11c24.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/nuft\/uavcan.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"a598fb8ded068eb69f5bce8352cc74f07c97fd16","subject":"Try to avoid erasing section","message":"Try to avoid erasing section\n","repos":"Tutul-\/tumuxOS,Tutul-\/tumuxOS,Tutul-\/tumuxOS","old_file":"src\/kernel\/arch\/x86\/linker.ld","new_file":"src\/kernel\/arch\/x86\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Tutul-\/tumuxOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"ff85c3398b35f6d15e0bc2dd584a38756746fb05","subject":"Added linker64.ld files to fimrware\/pc-bios folder","message":"Added linker64.ld files to fimrware\/pc-bios folder\n","repos":"beyondsociety\/ibox,beyondsociety\/ibox","old_file":"firmware\/pc-bios\/linker64.ld","new_file":"firmware\/pc-bios\/linker64.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/beyondsociety\/ibox.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"8556e2d28db1d47b7cf0906207d2448ade442c71","subject":"Combined extra sections","message":"Combined extra sections\n","repos":"daveshep666\/davos,daveshep666\/davos","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/daveshep666\/davos.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"8db93cf0d915431f240bd3a26c8135b491bfee5c","subject":"K64F: Explicitly set the start of .uvisor.bss","message":"K64F: Explicitly set the start of .uvisor.bss\n","repos":"cvtsi2sd\/mbed-os,geky\/mbed,HeadsUpDisplayInc\/mbed,svogl\/mbed-os,YarivCol\/mbed-os,RonEld\/mbed,karsev\/mbed-os,bulislaw\/mbed-os,cvtsi2sd\/mbed-os,bulislaw\/mbed-os,tung7970\/mbed-os-1,karsev\/mbed-os,betzw\/mbed-os,tung7970\/mbed-os,theotherjimmy\/mbed,screamerbg\/mbed,nRFMesh\/mbed-os,catiedev\/mbed-os,andreaslarssonublox\/mbed,maximmbed\/mbed,catiedev\/mbed-os,pradeep-gr\/mbed-os5-onsemi,nRFMesh\/mbed-os,infinnovation\/mbed-os,mmorenobarm\/mbed-os,RonEld\/mbed,maximmbed\/mbed,adustm\/mbed,betzw\/mbed-os,arostm\/mbed-os,infinnovation\/mbed-os,HeadsUpDisplayInc\/mbed,nvlsianpu\/mbed,kjbracey-arm\/mbed,kl-cruz\/mbed-os,bcostm\/mbed-os,fahhem\/mbed-os,tung7970\/mbed-os,kjbracey-arm\/mbed,theotherjimmy\/mbed,mbedmicro\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,fanghuaqi\/mbed,maximmbed\/mbed,adustm\/mbed,mikaleppanen\/mbed-os,mbedmicro\/mbed,tung7970\/mbed-os-1,bulislaw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,NXPmicro\/mbed,CalSol\/mbed,bulislaw\/mbed-os,bcostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,HeadsUpDisplayInc\/mbed,mbedmicro\/mbed,mikaleppanen\/mbed-os,svastm\/mbed,andcor02\/mbed-os,geky\/mbed,catiedev\/mbed-os,mazimkhan\/mbed-os,RonEld\/mbed,andcor02\/mbed-os,rgrover\/mbed,jeremybrodt\/mbed,screamerbg\/mbed,CalSol\/mbed,netzimme\/mbed-os,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,DanKupiniak\/mbed,adamgreen\/mbed,rgrover\/mbed,Archcady\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,HeadsUpDisplayInc\/mbed,CalSol\/mbed,geky\/mbed,mikaleppanen\/mbed-os,mbedmicro\/mbed,j-greffe\/mbed-os,maximmbed\/mbed,c1728p9\/mbed-os,andcor02\/mbed-os,ryankurte\/mbed-os,theotherjimmy\/mbed,adamgreen\/mbed,kjbracey-arm\/mbed,YarivCol\/mbed-os,j-greffe\/mbed-os,fahhem\/mbed-os,mmorenobarm\/mbed-os,nRFMesh\/mbed-os,karsev\/mbed-os,svastm\/mbed,j-greffe\/mbed-os,andcor02\/mbed-os,mmorenobarm\/mbed-os,kl-cruz\/mbed-os,Archcady\/mbed-os,Archcady\/mbed-os,svogl\/mbed-os,CalSol\/mbed,rgrover\/mbed,svogl\/mbed-os,ryankurte\/mbed-os,bcostm\/mbed-os,geky\/mbed,pradeep-gr\/mbed-os5-onsemi,nRFMesh\/mbed-os,nvlsianpu\/mbed,cvtsi2sd\/mbed-os,netzimme\/mbed-os,kjbracey-arm\/mbed,betzw\/mbed-os,karsev\/mbed-os,RonEld\/mbed,j-greffe\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,YarivCol\/mbed-os,monkiineko\/mbed-os,catiedev\/mbed-os,bcostm\/mbed-os,mazimkhan\/mbed-os,infinnovation\/mbed-os,cvtsi2sd\/mbed-os,Archcady\/mbed-os,maximmbed\/mbed,fahhem\/mbed-os,mbedmicro\/mbed,jeremybrodt\/mbed,mazimkhan\/mbed-os,NXPmicro\/mbed,fanghuaqi\/mbed,YarivCol\/mbed-os,mazimkhan\/mbed-os,mikaleppanen\/mbed-os,RonEld\/mbed,DanKupiniak\/mbed,bcostm\/mbed-os,ryankurte\/mbed-os,fvincenzo\/mbed-os,infinnovation\/mbed-os,monkiineko\/mbed-os,mikaleppanen\/mbed-os,adustm\/mbed,jeremybrodt\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,svastm\/mbed,cvtsi2sd\/mbed-os,arostm\/mbed-os,nvlsianpu\/mbed,arostm\/mbed-os,catiedev\/mbed-os,NXPmicro\/mbed,mazimkhan\/mbed-os,arostm\/mbed-os,adustm\/mbed,svogl\/mbed-os,fvincenzo\/mbed-os,infinnovation\/mbed-os,arostm\/mbed-os,nvlsianpu\/mbed,theotherjimmy\/mbed,CalSol\/mbed,CalSol\/mbed,rgrover\/mbed,ryankurte\/mbed-os,monkiineko\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,andreaslarssonublox\/mbed,adamgreen\/mbed,andreaslarssonublox\/mbed,karsev\/mbed-os,pradeep-gr\/mbed-os5-onsemi,tung7970\/mbed-os-1,screamerbg\/mbed,svastm\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,netzimme\/mbed-os,monkiineko\/mbed-os,screamerbg\/mbed,adamgreen\/mbed,RonEld\/mbed,c1728p9\/mbed-os,rgrover\/mbed,nRFMesh\/mbed-os,kl-cruz\/mbed-os,fahhem\/mbed-os,Archcady\/mbed-os,betzw\/mbed-os,karsev\/mbed-os,fvincenzo\/mbed-os,c1728p9\/mbed-os,nRFMesh\/mbed-os,arostm\/mbed-os,j-greffe\/mbed-os,betzw\/mbed-os,bcostm\/mbed-os,nvlsianpu\/mbed,HeadsUpDisplayInc\/mbed,fanghuaqi\/mbed,tung7970\/mbed-os-1,mikaleppanen\/mbed-os,screamerbg\/mbed,YarivCol\/mbed-os,infinnovation\/mbed-os,kl-cruz\/mbed-os,fanghuaqi\/mbed,tung7970\/mbed-os,fvincenzo\/mbed-os,svastm\/mbed,NXPmicro\/mbed,mmorenobarm\/mbed-os,NXPmicro\/mbed,bulislaw\/mbed-os,geky\/mbed,jeremybrodt\/mbed,fahhem\/mbed-os,kl-cruz\/mbed-os,fanghuaqi\/mbed,YarivCol\/mbed-os,c1728p9\/mbed-os,mazimkhan\/mbed-os,kl-cruz\/mbed-os,svogl\/mbed-os,netzimme\/mbed-os,netzimme\/mbed-os,andcor02\/mbed-os,adamgreen\/mbed,adustm\/mbed,j-greffe\/mbed-os,mmorenobarm\/mbed-os,svogl\/mbed-os,monkiineko\/mbed-os,adustm\/mbed,ryankurte\/mbed-os,bulislaw\/mbed-os,nvlsianpu\/mbed,monkiineko\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,DanKupiniak\/mbed,c1728p9\/mbed-os,DanKupiniak\/mbed,tung7970\/mbed-os,cvtsi2sd\/mbed-os,fvincenzo\/mbed-os,theotherjimmy\/mbed,mmorenobarm\/mbed-os,theotherjimmy\/mbed,tung7970\/mbed-os,adamgreen\/mbed,ryankurte\/mbed-os,andcor02\/mbed-os,NXPmicro\/mbed,netzimme\/mbed-os,tung7970\/mbed-os-1,jeremybrodt\/mbed,maximmbed\/mbed,screamerbg\/mbed,Archcady\/mbed-os,catiedev\/mbed-os,andreaslarssonublox\/mbed,andreaslarssonublox\/mbed,fahhem\/mbed-os","old_file":"hal\/targets\/cmsis\/TARGET_Freescale\/TARGET_K64F\/TOOLCHAIN_GCC_ARM\/MK64FN1M0xxx12.ld","new_file":"hal\/targets\/cmsis\/TARGET_Freescale\/TARGET_K64F\/TOOLCHAIN_GCC_ARM\/MK64FN1M0xxx12.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/RonEld\/mbed.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2da01b3d10de9f571c0bcd26d2cbc0016e4e25b8","subject":"Linker script added","message":"Linker script added\n","repos":"rksdna\/swamp-m0,rksdna\/swamp,rksdna\/swamp","old_file":"kernel\/target\/stm32f030x8.ld","new_file":"kernel\/target\/stm32f030x8.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/rksdna\/swamp-m0.git\/': GnuTLS recv error (-54): Error in the pull function.\n","license":"mit","lang":"Linker Script"}
{"commit":"54c984b7f0f83cc7bf34985faf7b3ac169706ed1","subject":"add linker script template for F407","message":"add linker script template for F407\n","repos":"IntergatedCircuits\/STM32_XPD,IntergatedCircuits\/STM32_XPD","old_file":"CMSIS\/Device\/ST\/STM32F4xx\/Source\/Templates\/gcc\/linker\/STM32F407VG_FLASH.ld","new_file":"CMSIS\/Device\/ST\/STM32F4xx\/Source\/Templates\/gcc\/linker\/STM32F407VG_FLASH.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/IntergatedCircuits\/STM32_XPD.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f0d6e0e17366987a8c5c5bb0883e52f6801663f3","subject":"add gcc.ld","message":"add gcc.ld\n","repos":"igou\/rt-thread,nongxiaoming\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,RT-Thread\/rt-thread,yongli3\/rt-thread,wolfgangz2013\/rt-thread,gbcwbz\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,yongli3\/rt-thread,geniusgogo\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,wolfgangz2013\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,zhaojuntao\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,armink\/rt-thread,yongli3\/rt-thread,gbcwbz\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,RT-Thread\/rt-thread,igou\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,AubrCool\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,ArdaFu\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,hezlog\/rt-thread,AubrCool\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,wolfgangz2013\/rt-thread,armink\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread","old_file":"bsp\/simlinux\/gcc.ld","new_file":"bsp\/simlinux\/gcc.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/igou\/rt-thread.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f7d318fe72efc1f93558335f63dac8e9f5a51d79","subject":"qemu won't load the vectors, only stuff starting at 0x10000 so we dont put the vectors in a separate section","message":"qemu won't load the vectors, only stuff starting at 0x10000 so we dont put the vectors in a separate section\n","repos":"matildah\/octocabbit","old_file":"scheduler\/startup.ld","new_file":"scheduler\/startup.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/matildah\/octocabbit.git\/': The requested URL returned error: 403\n","license":"isc","lang":"Linker Script"}
{"commit":"0f0563dbc5f8db18fc4fd73e49db5c2442d5673a","subject":"Linker script","message":"Linker script\n","repos":"smaeul\/quarto","old_file":"scripts\/kernel.ld","new_file":"scripts\/kernel.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/smaeul\/quarto.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"2b6f541c1875e92b7122de90fc9285156ee944b7","subject":"store default linker script for reference","message":"store default linker script for reference\n","repos":"wilseypa\/llamaOS,wilseypa\/llamaOS,wilseypa\/llamaOS","old_file":"build\/default-2.22.lds","new_file":"build\/default-2.22.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/wilseypa\/llamaOS.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"787b599c8108f514645d9ee6256ee53dccc9db84","subject":"libfdt: Add version.lds file","message":"libfdt: Add version.lds file\n\nAdd the initial symbol versioning file as groundwork for creating\na libfdt shared library\n\nSigned-off-by: Josh Boyer <94755a79aca753e683bb6d0e796d473b797056eb@linux.vnet.ibm.com>\n","repos":"jbott\/lk_gee,RonGokhale\/android_lk_bootloader,t2m-foxfone\/kernel_lk,chirayudesai\/android_bootable_bootloader_lk,zhuotong\/mi2_lk_NoEmmc,M1cha\/lktris,Foxda-Tech\/argo8-bootable-bootloader-lk,t2m-foxfone\/kernel_lk,mozilla-b2g\/fairphone2_kernel_lk,RonGokhale\/android_lk_bootloader,t2m-foxfone\/android_kernel_lk,mozilla-b2g\/kernel_lk,oubeichen\/lk-v500,detule\/lk-g2-spr,RonGokhale\/android_lk_bootloader,M1cha\/android_bootable_bootloader_lk,pichina\/lk,M1cha\/lktris,DooMLoRD\/android_bootable_bootloader_lk,DooMLoRD\/android_bootable_bootloader_lk,t2m-foxfone\/kernel_lk,Foxda-Tech\/argo8-bootable-bootloader-lk,jsr-d10\/android_bootable_bootloader_lk,chirayudesai\/android_bootable_bootloader_lk,lg-devs\/g2-bootloader,hanjae\/lumiab0,Foxda-Tech\/polaris-bootable-bootloader-lk,MiCode\/mi2_lk,lg-devs\/g2-bootloader,thornbirdblue\/codeaurora_lk,M1cha\/mi2_lk,M1cha\/android_bootable_bootloader_lk,Blefish\/android_bootable_bootloader_lk,CanarySolutions\/little-kernel,CanarySolutions\/little-kernel,efidroid\/lk,DooMLoRD\/android_bootable_bootloader_lk,utilite2\/lk,chirayudesai\/android_bootable_bootloader_lk,M1cha\/mi2_lk,hanjae\/lumiab0,oubeichen\/lk-v500,M1cha\/android_bootable_bootloader_lk,utilite2\/lk,M1cha\/lktris,jsr-d9\/android_kernel_lk,mozilla-b2g\/fairphone2_kernel_lk,thornbirdblue\/codeaurora_lk,idor\/dk50-bootable_bootloader_lk,Blefish\/android_bootable_bootloader_lk,MiCode\/mi2_lk,M1cha\/android_bootable_bootloader_lk,Foxda-Tech\/polaris-bootable-bootloader-lk,mozilla-b2g\/kernel_lk,MiCode\/mi2_lk,RonGokhale\/android_lk_bootloader,utilite2\/lk,M1cha\/lktris,mozilla-b2g\/kernel_lk,MiCode\/mi2_lk,lg-devs\/g2-bootloader,jsr-d9\/android_kernel_lk,thornbirdblue\/codeaurora_lk,M1cha\/mi2_lk,CanarySolutions\/little-kernel,mozilla-b2g\/kernel_lk,chirayudesai\/android_bootable_bootloader_lk,efidroid\/lk,efidroid\/lk,oubeichen\/lk-v500,t2m-foxfone\/android_kernel_lk,zhuotong\/mi2_lk_NoEmmc,jbott\/lk_gee,chirayudesai\/android_bootable_bootloader_lk,Blefish\/android_bootable_bootloader_lk,mozilla-b2g\/fairphone2_kernel_lk,t2m-foxfone\/android_kernel_lk,pichina\/lk,Foxda-Tech\/polaris-bootable-bootloader-lk,jsr-d10\/android_bootable_bootloader_lk,hanjae\/lumiab0,M1cha\/android_bootable_bootloader_lk,Redmi-dev\/android_bootable_lk,M1cha\/mi2_lk,utilite2\/lk,zhuotong\/mi2_lk_NoEmmc,Redmi-dev\/android_bootable_lk,detule\/lk-g2-spr,mozilla-b2g\/fairphone2_kernel_lk,jsr-d10\/android_bootable_bootloader_lk,Redmi-dev\/android_bootable_lk,Foxda-Tech\/argo8-bootable-bootloader-lk,M1cha\/android_bootable_bootloader_lk,Blefish\/android_bootable_bootloader_lk,efidroid\/lk,lg-devs\/g2-bootloader,t2m-foxfone\/android_kernel_lk,zhuotong\/mi2_lk_NoEmmc,detule\/lk-g2-spr,zhuotong\/mi2_lk_NoEmmc,hanjae\/lumiab0,oubeichen\/lk-v500,idor\/dk50-bootable_bootloader_lk,Blefish\/android_bootable_bootloader_lk,DooMLoRD\/android_bootable_bootloader_lk,mozilla-b2g\/kernel_lk,jsr-d9\/android_kernel_lk,pichina\/lk,CanarySolutions\/little-kernel,jsr-d10\/android_bootable_bootloader_lk,RonGokhale\/android_lk_bootloader,idor\/dk50-bootable_bootloader_lk,jsr-d9\/android_kernel_lk,Foxda-Tech\/argo8-bootable-bootloader-lk,pichina\/lk,hanjae\/lumiab0,M1cha\/mi2_lk,idor\/dk50-bootable_bootloader_lk,Redmi-dev\/android_bootable_lk,detule\/lk-g2-spr,utilite2\/lk,jbott\/lk_gee,thornbirdblue\/codeaurora_lk,t2m-foxfone\/android_kernel_lk,CanarySolutions\/little-kernel,jsr-d9\/android_kernel_lk,Redmi-dev\/android_bootable_lk,Foxda-Tech\/polaris-bootable-bootloader-lk,mozilla-b2g\/fairphone2_kernel_lk,Foxda-Tech\/argo8-bootable-bootloader-lk,t2m-foxfone\/kernel_lk,t2m-foxfone\/kernel_lk,pichina\/lk,idor\/dk50-bootable_bootloader_lk,thornbirdblue\/codeaurora_lk,jbott\/lk_gee,jsr-d10\/android_bootable_bootloader_lk,efidroid\/lk,jbott\/lk_gee,detule\/lk-g2-spr,Foxda-Tech\/polaris-bootable-bootloader-lk,MiCode\/mi2_lk,oubeichen\/lk-v500,lg-devs\/g2-bootloader,M1cha\/lktris,DooMLoRD\/android_bootable_bootloader_lk","old_file":"libfdt\/version.lds","new_file":"libfdt\/version.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/detule\/lk-g2-spr.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"05e5d411b53dcba9529b6ac1e9388bab65f8c11b","subject":"mimxrt\/boards: Set __heap_size__ to 0 in MIMXRT1011.ld.","message":"mimxrt\/boards: Set __heap_size__ to 0 in MIMXRT1011.ld.\n\nDo not use the traditional C heap in order to save memory, because the\ntraditional C heap is unused in MicroPython.\n","repos":"selste\/micropython,kerneltask\/micropython,henriknelson\/micropython,adafruit\/circuitpython,bvernoux\/micropython,MrSurly\/micropython,adafruit\/circuitpython,pramasoul\/micropython,henriknelson\/micropython,kerneltask\/micropython,adafruit\/circuitpython,bvernoux\/micropython,pramasoul\/micropython,henriknelson\/micropython,kerneltask\/micropython,selste\/micropython,henriknelson\/micropython,MrSurly\/micropython,MrSurly\/micropython,selste\/micropython,MrSurly\/micropython,adafruit\/circuitpython,kerneltask\/micropython,bvernoux\/micropython,henriknelson\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,MrSurly\/micropython,pramasoul\/micropython,pramasoul\/micropython,selste\/micropython,bvernoux\/micropython,pramasoul\/micropython,kerneltask\/micropython,selste\/micropython,bvernoux\/micropython","old_file":"ports\/mimxrt\/boards\/MIMXRT1011.ld","new_file":"ports\/mimxrt\/boards\/MIMXRT1011.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kerneltask\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"8752894cc96c8793c304bbd988457d2fcddff29f","subject":"cpu\/cortexm: added base linkerscript","message":"cpu\/cortexm: added base linkerscript\n","repos":"zhuoshuguo\/RIOT,plushvoxel\/RIOT,jasonatran\/RIOT,cladmi\/RIOT,ThanhVic\/RIOT,Lexandro92\/RIOT-CoAP,Osblouf\/RIOT,neiljay\/RIOT,latsku\/RIOT,kbumsik\/RIOT,brettswann\/RIOT,daniel-k\/RIOT,MohmadAyman\/RIOT,toonst\/RIOT,patkan\/RIOT,ximus\/RIOT,rousselk\/RIOT,alignan\/RIOT,d00616\/RIOT,l3nko\/RIOT,openkosmosorg\/RIOT,TobiasFredersdorf\/RIOT,LudwigOrtmann\/RIOT,kbumsik\/RIOT,Yonezawa-T2\/RIOT,BytesGalore\/RIOT,toonst\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,thiagohd\/RIOT,yogo1212\/RIOT,ximus\/RIOT,LudwigOrtmann\/RIOT,shady33\/RIOT,herrfz\/RIOT,plushvoxel\/RIOT,jferreir\/RIOT,altairpearl\/RIOT,ant9000\/RIOT,stevenj\/RIOT,khhhh\/RIOT,hamilton-mote\/RIOT-OS,chris-wood\/RIOT,l3nko\/RIOT,kerneltask\/RIOT,gbarnett\/RIOT,kaspar030\/RIOT,mziegert\/RIOT,yogo1212\/RIOT,dhruvvyas90\/RIOT,katezilla\/RIOT,kb2ma\/RIOT,FrancescoErmini\/RIOT,kerneltask\/RIOT,dkm\/RIOT,MonsterCode8000\/RIOT,DipSwitch\/RIOT,EmuxEvans\/RIOT,PSHIVANI\/Riot-Code,rajma996\/RIOT,dailab\/RIOT,zhuoshuguo\/RIOT,jferreir\/RIOT,openkosmosorg\/RIOT,neumodisch\/RIOT,altairpearl\/RIOT,herrfz\/RIOT,sgso\/RIOT,automote\/RIOT,FrancescoErmini\/RIOT,kbumsik\/RIOT,rfuentess\/RIOT,ThanhVic\/RIOT,yogo1212\/RIOT,smlng\/RIOT,RBartz\/RIOT,JensErdmann\/RIOT,marcosalm\/RIOT,rajma996\/RIOT,daniel-k\/RIOT,haoyangyu\/RIOT,cladmi\/RIOT,DipSwitch\/RIOT,ant9000\/RIOT,lazytech-org\/RIOT,adrianghc\/RIOT,abkam07\/RIOT,thomaseichinger\/RIOT,mfrey\/RIOT,backenklee\/RIOT,asanka-code\/RIOT,lebrush\/RIOT,plushvoxel\/RIOT,benoit-canet\/RIOT,herrfz\/RIOT,beurdouche\/RIOT,patkan\/RIOT,phiros\/RIOT,wentaoshang\/RIOT,jremmert-phytec-iot\/RIOT,wentaoshang\/RIOT,toonst\/RIOT,dhruvvyas90\/RIOT,dkm\/RIOT,latsku\/RIOT,altairpearl\/RIOT,bartfaizoltan\/RIOT,JensErdmann\/RIOT,rajma996\/RIOT,MarkXYang\/RIOT,alex1818\/RIOT,kushalsingh007\/RIOT,automote\/RIOT,MarkXYang\/RIOT,chris-wood\/RIOT,rfuentess\/RIOT,attdona\/RIOT,LudwigOrtmann\/RIOT,RIOT-OS\/RIOT,jbeyerstedt\/RIOT-OTA-update,rakendrathapa\/RIOT,l3nko\/RIOT,gebart\/RIOT,l3nko\/RIOT,tdautc19841202\/RIOT,ks156\/RIOT,avmelnikoff\/RIOT,stevenj\/RIOT,marcosalm\/RIOT,immesys\/RiSyn,binarylemon\/RIOT,syin2\/RIOT,abkam07\/RIOT,x3ro\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,arvindpdmn\/RIOT,beurdouche\/RIOT,gbarnett\/RIOT,rousselk\/RIOT,abp719\/RIOT,sumanpanchal\/RIOT,automote\/RIOT,josephnoir\/RIOT,mtausig\/RIOT,wentaoshang\/RIOT,malosek\/RIOT,gautric\/RIOT,RubikonAlpha\/RIOT,abp719\/RIOT,shady33\/RIOT,centurysys\/RIOT,plushvoxel\/RIOT,openkosmosorg\/RIOT,A-Paul\/RIOT,centurysys\/RIOT,PSHIVANI\/Riot-Code,PSHIVANI\/Riot-Code,OlegHahm\/RIOT,thomaseichinger\/RIOT,abkam07\/RIOT,ntrtrung\/RIOT,katezilla\/RIOT,d00616\/RIOT,arvindpdmn\/RIOT,beurdouche\/RIOT,sgso\/RIOT,lebrush\/RIOT,mziegert\/RIOT,zhuoshuguo\/RIOT,immesys\/RiSyn,msolters\/RIOT,d00616\/RIOT,jremmert-phytec-iot\/RIOT,ntrtrung\/RIOT,EmuxEvans\/RIOT,syin2\/RIOT,kaleb-himes\/RIOT,ks156\/RIOT,adrianghc\/RIOT,rakendrathapa\/RIOT,jferreir\/RIOT,gebart\/RIOT,kbumsik\/RIOT,luciotorre\/RIOT,RBartz\/RIOT,dkm\/RIOT,koenning\/RIOT,MarkXYang\/RIOT,latsku\/RIOT,daniel-k\/RIOT,LudwigKnuepfer\/RIOT,adjih\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,bartfaizoltan\/RIOT,ntrtrung\/RIOT,ks156\/RIOT,yogo1212\/RIOT,changbiao\/RIOT,DipSwitch\/RIOT,miri64\/RIOT,authmillenon\/RIOT,cladmi\/RIOT,lazytech-org\/RIOT,l3nko\/RIOT,neumodisch\/RIOT,RBartz\/RIOT,khhhh\/RIOT,smlng\/RIOT,LudwigOrtmann\/RIOT,ximus\/RIOT,sgso\/RIOT,latsku\/RIOT,Josar\/RIOT,DipSwitch\/RIOT,jremmert-phytec-iot\/RIOT,MonsterCode8000\/RIOT,aeneby\/RIOT,MarkXYang\/RIOT,Darredevil\/RIOT,neumodisch\/RIOT,Darredevil\/RIOT,lebrush\/RIOT,neumodisch\/RIOT,mfrey\/RIOT,thomaseichinger\/RIOT,attdona\/RIOT,openkosmosorg\/RIOT,katezilla\/RIOT,A-Paul\/RIOT,wentaoshang\/RIOT,Hyungsin\/RIOT-OS,roberthartung\/RIOT,brettswann\/RIOT,wentaoshang\/RIOT,gebart\/RIOT,immesys\/RiSyn,khhhh\/RIOT,immesys\/RiSyn,tfar\/RIOT,lebrush\/RIOT,Lexandro92\/RIOT-CoAP,immesys\/RiSyn,sumanpanchal\/RIOT,phiros\/RIOT,jremmert-phytec-iot\/RIOT,yogo1212\/RIOT,mziegert\/RIOT,koenning\/RIOT,sgso\/RIOT,Osblouf\/RIOT,JensErdmann\/RIOT,ntrtrung\/RIOT,arvindpdmn\/RIOT,OlegHahm\/RIOT,brettswann\/RIOT,MohmadAyman\/RIOT,TobiasFredersdorf\/RIOT,Lexandro92\/RIOT-CoAP,basilfx\/RIOT,neumodisch\/RIOT,dkm\/RIOT,adrianghc\/RIOT,hamilton-mote\/RIOT-OS,centurysys\/RIOT,luciotorre\/RIOT,jasonatran\/RIOT,daniel-k\/RIOT,chris-wood\/RIOT,jfischer-phytec-iot\/RIOT,binarylemon\/RIOT,shady33\/RIOT,RubikonAlpha\/RIOT,RBartz\/RIOT,MarkXYang\/RIOT,OTAkeys\/RIOT,toonst\/RIOT,MohmadAyman\/RIOT,LudwigKnuepfer\/RIOT,syin2\/RIOT,miri64\/RIOT,benoit-canet\/RIOT,abp719\/RIOT,arvindpdmn\/RIOT,MonsterCode8000\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,automote\/RIOT,rfuentess\/RIOT,BytesGalore\/RIOT,patkan\/RIOT,BytesGalore\/RIOT,changbiao\/RIOT,asanka-code\/RIOT,abp719\/RIOT,tfar\/RIOT,mtausig\/RIOT,Darredevil\/RIOT,authmillenon\/RIOT,mziegert\/RIOT,ntrtrung\/RIOT,msolters\/RIOT,OTAkeys\/RIOT,thomaseichinger\/RIOT,altairpearl\/RIOT,herrfz\/RIOT,ant9000\/RIOT,RubikonAlpha\/RIOT,avmelnikoff\/RIOT,MarkXYang\/RIOT,daniel-k\/RIOT,herrfz\/RIOT,jbeyerstedt\/RIOT-OTA-update,luciotorre\/RIOT,marcosalm\/RIOT,koenning\/RIOT,wentaoshang\/RIOT,luciotorre\/RIOT,rousselk\/RIOT,adjih\/RIOT,kerneltask\/RIOT,hamilton-mote\/RIOT-OS,tfar\/RIOT,MonsterCode8000\/RIOT,tdautc19841202\/RIOT,alignan\/RIOT,dkm\/RIOT,Osblouf\/RIOT,malosek\/RIOT,attdona\/RIOT,alignan\/RIOT,rajma996\/RIOT,robixnai\/RIOT,mtausig\/RIOT,smlng\/RIOT,yogo1212\/RIOT,abp719\/RIOT,Yonezawa-T2\/RIOT,Yonezawa-T2\/RIOT,Lexandro92\/RIOT-CoAP,kushalsingh007\/RIOT,marcosalm\/RIOT,bartfaizoltan\/RIOT,zhuoshuguo\/RIOT,shady33\/RIOT,adrianghc\/RIOT,alignan\/RIOT,rakendrathapa\/RIOT,aeneby\/RIOT,binarylemon\/RIOT,automote\/RIOT,lazytech-org\/RIOT,bartfaizoltan\/RIOT,mfrey\/RIOT,haoyangyu\/RIOT,RubikonAlpha\/RIOT,JensErdmann\/RIOT,aeneby\/RIOT,FrancescoErmini\/RIOT,centurysys\/RIOT,adrianghc\/RIOT,jbeyerstedt\/RIOT-OTA-update,EmuxEvans\/RIOT,A-Paul\/RIOT,rajma996\/RIOT,OTAkeys\/RIOT,patkan\/RIOT,rousselk\/RIOT,biboc\/RIOT,jferreir\/RIOT,TobiasFredersdorf\/RIOT,watr-li\/RIOT,katezilla\/RIOT,kushalsingh007\/RIOT,OlegHahm\/RIOT,asanka-code\/RIOT,luciotorre\/RIOT,cladmi\/RIOT,changbiao\/RIOT,rajma996\/RIOT,rfswarm\/RIOT,d00616\/RIOT,Darredevil\/RIOT,biboc\/RIOT,malosek\/RIOT,alex1818\/RIOT,koenning\/RIOT,Ell-i\/RIOT,stevenj\/RIOT,LudwigKnuepfer\/RIOT,OlegHahm\/RIOT,brettswann\/RIOT,msolters\/RIOT,ximus\/RIOT,gautric\/RIOT,watr-li\/RIOT,rfswarm\/RIOT,beurdouche\/RIOT,PSHIVANI\/Riot-Code,RubikonAlpha\/RIOT,kaspar030\/RIOT,A-Paul\/RIOT,khhhh\/RIOT,dailab\/RIOT,tdautc19841202\/RIOT,watr-li\/RIOT,watr-li\/RIOT,josephnoir\/RIOT,roberthartung\/RIOT,Hyungsin\/RIOT-OS,Ell-i\/RIOT,Yonezawa-T2\/RIOT,binarylemon\/RIOT,kaleb-himes\/RIOT,RIOT-OS\/RIOT,kerneltask\/RIOT,kYc0o\/RIOT,kb2ma\/RIOT,Lexandro92\/RIOT-CoAP,ant9000\/RIOT,EmuxEvans\/RIOT,robixnai\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,adjih\/RIOT,jremmert-phytec-iot\/RIOT,neiljay\/RIOT,altairpearl\/RIOT,arvindpdmn\/RIOT,stevenj\/RIOT,biboc\/RIOT,DipSwitch\/RIOT,miri64\/RIOT,zhuoshuguo\/RIOT,basilfx\/RIOT,kYc0o\/RIOT,attdona\/RIOT,robixnai\/RIOT,LudwigOrtmann\/RIOT,robixnai\/RIOT,gautric\/RIOT,EmuxEvans\/RIOT,changbiao\/RIOT,Yonezawa-T2\/RIOT,roberthartung\/RIOT,khhhh\/RIOT,jfischer-phytec-iot\/RIOT,hamilton-mote\/RIOT-OS,gbarnett\/RIOT,Hyungsin\/RIOT-OS,JensErdmann\/RIOT,sumanpanchal\/RIOT,sumanpanchal\/RIOT,ThanhVic\/RIOT,mziegert\/RIOT,jfischer-phytec-iot\/RIOT,TobiasFredersdorf\/RIOT,Osblouf\/RIOT,gebart\/RIOT,toonst\/RIOT,jferreir\/RIOT,biboc\/RIOT,miri64\/RIOT,basilfx\/RIOT,Hyungsin\/RIOT-OS,DipSwitch\/RIOT,luciotorre\/RIOT,ThanhVic\/RIOT,rfswarm\/RIOT,benoit-canet\/RIOT,abp719\/RIOT,tdautc19841202\/RIOT,authmillenon\/RIOT,ximus\/RIOT,msolters\/RIOT,phiros\/RIOT,jfischer-phytec-iot\/RIOT,dhruvvyas90\/RIOT,mziegert\/RIOT,patkan\/RIOT,smlng\/RIOT,adjih\/RIOT,kb2ma\/RIOT,sumanpanchal\/RIOT,jbeyerstedt\/RIOT-OTA-update,asanka-code\/RIOT,RBartz\/RIOT,neiljay\/RIOT,alex1818\/RIOT,gbarnett\/RIOT,thiagohd\/RIOT,rousselk\/RIOT,Ell-i\/RIOT,abkam07\/RIOT,x3ro\/RIOT,backenklee\/RIOT,katezilla\/RIOT,haoyangyu\/RIOT,mtausig\/RIOT,patkan\/RIOT,rfuentess\/RIOT,msolters\/RIOT,TobiasFredersdorf\/RIOT,benoit-canet\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,MohmadAyman\/RIOT,kYc0o\/RIOT,tdautc19841202\/RIOT,daniel-k\/RIOT,brettswann\/RIOT,centurysys\/RIOT,jasonatran\/RIOT,l3nko\/RIOT,neiljay\/RIOT,Ell-i\/RIOT,FrancescoErmini\/RIOT,syin2\/RIOT,altairpearl\/RIOT,haoyangyu\/RIOT,kaspar030\/RIOT,cladmi\/RIOT,Yonezawa-T2\/RIOT,MonsterCode8000\/RIOT,kYc0o\/RIOT,Ell-i\/RIOT,abkam07\/RIOT,koenning\/RIOT,dhruvvyas90\/RIOT,alex1818\/RIOT,ximus\/RIOT,chris-wood\/RIOT,sumanpanchal\/RIOT,JensErdmann\/RIOT,mfrey\/RIOT,roberthartung\/RIOT,marcosalm\/RIOT,thiagohd\/RIOT,basilfx\/RIOT,Lexandro92\/RIOT-CoAP,biboc\/RIOT,PSHIVANI\/Riot-Code,Darredevil\/RIOT,kerneltask\/RIOT,rousselk\/RIOT,openkosmosorg\/RIOT,josephnoir\/RIOT,robixnai\/RIOT,josephnoir\/RIOT,herrfz\/RIOT,kYc0o\/RIOT,avmelnikoff\/RIOT,kbumsik\/RIOT,koenning\/RIOT,chris-wood\/RIOT,asanka-code\/RIOT,kushalsingh007\/RIOT,Hyungsin\/RIOT-OS,FrancescoErmini\/RIOT,ThanhVic\/RIOT,adjih\/RIOT,jferreir\/RIOT,changbiao\/RIOT,alex1818\/RIOT,lebrush\/RIOT,Josar\/RIOT,jremmert-phytec-iot\/RIOT,EmuxEvans\/RIOT,immesys\/RiSyn,LudwigOrtmann\/RIOT,ant9000\/RIOT,beurdouche\/RIOT,thiagohd\/RIOT,BytesGalore\/RIOT,changbiao\/RIOT,ThanhVic\/RIOT,gautric\/RIOT,dhruvvyas90\/RIOT,kaleb-himes\/RIOT,avmelnikoff\/RIOT,haoyangyu\/RIOT,aeneby\/RIOT,sgso\/RIOT,jasonatran\/RIOT,alex1818\/RIOT,brettswann\/RIOT,phiros\/RIOT,shady33\/RIOT,bartfaizoltan\/RIOT,thiagohd\/RIOT,gebart\/RIOT,OTAkeys\/RIOT,mfrey\/RIOT,mtausig\/RIOT,jasonatran\/RIOT,ks156\/RIOT,Osblouf\/RIOT,dailab\/RIOT,chris-wood\/RIOT,smlng\/RIOT,Josar\/RIOT,haoyangyu\/RIOT,x3ro\/RIOT,centurysys\/RIOT,stevenj\/RIOT,miri64\/RIOT,benoit-canet\/RIOT,neumodisch\/RIOT,backenklee\/RIOT,RBartz\/RIOT,gbarnett\/RIOT,alignan\/RIOT,kb2ma\/RIOT,rfswarm\/RIOT,josephnoir\/RIOT,thomaseichinger\/RIOT,backenklee\/RIOT,Josar\/RIOT,kaleb-himes\/RIOT,kaleb-himes\/RIOT,attdona\/RIOT,syin2\/RIOT,latsku\/RIOT,rfswarm\/RIOT,LudwigKnuepfer\/RIOT,x3ro\/RIOT,MohmadAyman\/RIOT,backenklee\/RIOT,neiljay\/RIOT,stevenj\/RIOT,rakendrathapa\/RIOT,gautric\/RIOT,dailab\/RIOT,aeneby\/RIOT,lebrush\/RIOT,PSHIVANI\/Riot-Code,plushvoxel\/RIOT,MonsterCode8000\/RIOT,marcosalm\/RIOT,ntrtrung\/RIOT,roberthartung\/RIOT,kushalsingh007\/RIOT,RubikonAlpha\/RIOT,lazytech-org\/RIOT,arvindpdmn\/RIOT,hamilton-mote\/RIOT-OS,automote\/RIOT,Darredevil\/RIOT,kushalsingh007\/RIOT,authmillenon\/RIOT,watr-li\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,A-Paul\/RIOT,benoit-canet\/RIOT,bartfaizoltan\/RIOT,rakendrathapa\/RIOT,phiros\/RIOT,LudwigKnuepfer\/RIOT,kb2ma\/RIOT,kaspar030\/RIOT,malosek\/RIOT,rfswarm\/RIOT,avmelnikoff\/RIOT,shady33\/RIOT,BytesGalore\/RIOT,thiagohd\/RIOT,abkam07\/RIOT,latsku\/RIOT,d00616\/RIOT,Osblouf\/RIOT,dailab\/RIOT,watr-li\/RIOT,phiros\/RIOT,zhuoshuguo\/RIOT,ks156\/RIOT,malosek\/RIOT,MohmadAyman\/RIOT,lazytech-org\/RIOT,malosek\/RIOT,rfuentess\/RIOT,openkosmosorg\/RIOT,sgso\/RIOT,asanka-code\/RIOT,jbeyerstedt\/RIOT-OTA-update,foss-for-synopsys-dwc-arc-processors\/RIOT,x3ro\/RIOT,dhruvvyas90\/RIOT,gbarnett\/RIOT,tfar\/RIOT,msolters\/RIOT,binarylemon\/RIOT,khhhh\/RIOT,FrancescoErmini\/RIOT,jfischer-phytec-iot\/RIOT,binarylemon\/RIOT,tfar\/RIOT,tdautc19841202\/RIOT,attdona\/RIOT,d00616\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,basilfx\/RIOT,Josar\/RIOT,robixnai\/RIOT,rakendrathapa\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm_base.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"667afd37c207d36e9f6b02a8e9ee21e40660281a","subject":"config.ld: add basic configuration for LDoc","message":"config.ld: add basic configuration for LDoc\n","repos":"RyanSquared\/FusionScript","old_file":"config.ld","new_file":"config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/RyanSquared\/FusionScript.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"b29b69fa6b0a7a79b8be5c7c414de425fd7fc433","subject":"Moved constructor pointers to read only data","message":"Moved constructor pointers to read only data\n","repos":"daveshep666\/davos,daveshep666\/davos","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/daveshep666\/davos.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"f2fad4a7ae858e9fea3f06109459afa39d36e61a","subject":"Added linker script","message":"Added linker script\n","repos":"Mendelt\/lpc810-blink","old_file":"src\/lpc8xx.ld","new_file":"src\/lpc8xx.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Mendelt\/lpc810-blink.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2c529d0060c9518eb72469f3266fb533ab5745f5","subject":"Add a basic linker script","message":"Add a basic linker script\n\nEnsures that the multiboot header is early in the executable.\n","repos":"rafalmiel\/blog_os,phil-opp\/blog_os,phil-opp\/blog_os,phil-opp\/blog_os,phil-opp\/blogOS,phil-opp\/blogOS,rafalmiel\/blog_os,phil-opp\/blog_os","old_file":"src\/arch\/x86_64\/linker.ld","new_file":"src\/arch\/x86_64\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/phil-opp\/blogOS.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a049c8a021837e930608b72dedfc8b9180d4dca1","subject":"add custom linker script for calling out locations in memory","message":"add custom linker script for calling out locations in memory\n","repos":"PDXostc\/can_firewall_software,PDXostc\/can_firewall_software","old_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_file":"avr32elf_uc3c2512c-custom-linker-script.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/PDXostc\/can_firewall_software.git\/': The requested URL returned error: 403\n","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"b77520202d1e9029d07f04ba013d3b01f1c27894","subject":"Add linker script for S120","message":"Add linker script for S120\n","repos":"jf87\/nrf51-pure-gcc-setup","old_file":"template\/gcc_nrf51_s120.ld","new_file":"template\/gcc_nrf51_s120.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/jf87\/nrf51-pure-gcc-setup.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"8522874167ea1b38f4041d209d1cab41bc3bc7e3","subject":"stm32\/boards: Add stm32h743.ld linker script.","message":"stm32\/boards: Add stm32h743.ld linker script.\n","repos":"tobbad\/micropython,swegener\/micropython,adafruit\/micropython,pfalcon\/micropython,tobbad\/micropython,selste\/micropython,trezor\/micropython,pozetroninc\/micropython,henriknelson\/micropython,kerneltask\/micropython,adafruit\/micropython,adafruit\/micropython,selste\/micropython,MrSurly\/micropython,dmazzella\/micropython,adafruit\/circuitpython,tralamazza\/micropython,tralamazza\/micropython,pozetroninc\/micropython,kerneltask\/micropython,tralamazza\/micropython,trezor\/micropython,bvernoux\/micropython,kerneltask\/micropython,dmazzella\/micropython,selste\/micropython,pozetroninc\/micropython,henriknelson\/micropython,ryannathans\/micropython,trezor\/micropython,adafruit\/circuitpython,henriknelson\/micropython,trezor\/micropython,pozetroninc\/micropython,tobbad\/micropython,pfalcon\/micropython,tobbad\/micropython,pramasoul\/micropython,tralamazza\/micropython,henriknelson\/micropython,adafruit\/circuitpython,kerneltask\/micropython,pramasoul\/micropython,ryannathans\/micropython,pfalcon\/micropython,kerneltask\/micropython,selste\/micropython,MrSurly\/micropython,adafruit\/circuitpython,dmazzella\/micropython,ryannathans\/micropython,MrSurly\/micropython,pramasoul\/micropython,pramasoul\/micropython,pfalcon\/micropython,adafruit\/micropython,swegener\/micropython,tobbad\/micropython,selste\/micropython,MrSurly\/micropython,trezor\/micropython,swegener\/micropython,adafruit\/micropython,adafruit\/circuitpython,MrSurly\/micropython,dmazzella\/micropython,bvernoux\/micropython,pozetroninc\/micropython,swegener\/micropython,swegener\/micropython,henriknelson\/micropython,ryannathans\/micropython,bvernoux\/micropython,ryannathans\/micropython,bvernoux\/micropython,pramasoul\/micropython,adafruit\/circuitpython,pfalcon\/micropython,bvernoux\/micropython","old_file":"ports\/stm32\/boards\/stm32h743.ld","new_file":"ports\/stm32\/boards\/stm32h743.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/pfalcon\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"d8a4dc470af21d06cd3dd4d70689fc7142724feb","subject":"stm32_alt.ld: add an alternate linker script","message":"stm32_alt.ld: add an alternate linker script\n","repos":"raphui\/rnk,raphui\/rnk,raphui\/rnk,raphui\/rnk","old_file":"stm32_alt.ld","new_file":"stm32_alt.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/raphui\/rnk.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"ad301d57456bfce245dfa640d7d2a15c802b686d","subject":"added simple kernel linker script","message":"added simple kernel linker script\n","repos":"ReturnInfinity\/BareMetal-kernel,ReturnInfinity\/BareMetal-kernel","old_file":"src\/x86-64\/kernel.ld","new_file":"src\/x86-64\/kernel.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ReturnInfinity\/BareMetal-kernel.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"d25fd647e7f36bbf502428e75b83c947fc85ddd7","subject":"cpu\/cortexm_common\/ldscripts: add common linker script for cortexm family","message":"cpu\/cortexm_common\/ldscripts: add common linker script for cortexm family\n","repos":"jasonatran\/RIOT,OTAkeys\/RIOT,immesys\/RiSyn,RIOT-OS\/RIOT,x3ro\/RIOT,biboc\/RIOT,Josar\/RIOT,x3ro\/RIOT,kaspar030\/RIOT,cladmi\/RIOT,yogo1212\/RIOT,neiljay\/RIOT,jasonatran\/RIOT,miri64\/RIOT,jasonatran\/RIOT,ks156\/RIOT,avmelnikoff\/RIOT,cladmi\/RIOT,OTAkeys\/RIOT,immesys\/RiSyn,smlng\/RIOT,immesys\/RiSyn,kYc0o\/RIOT,OTAkeys\/RIOT,immesys\/RiSyn,aeneby\/RIOT,josephnoir\/RIOT,biboc\/RIOT,BytesGalore\/RIOT,A-Paul\/RIOT,mtausig\/RIOT,cladmi\/RIOT,toonst\/RIOT,mtausig\/RIOT,kaspar030\/RIOT,x3ro\/RIOT,neiljay\/RIOT,kYc0o\/RIOT,smlng\/RIOT,gebart\/RIOT,RIOT-OS\/RIOT,ks156\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,josephnoir\/RIOT,biboc\/RIOT,biboc\/RIOT,LudwigOrtmann\/RIOT,adrianghc\/RIOT,BytesGalore\/RIOT,basilfx\/RIOT,kbumsik\/RIOT,rfuentess\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,immesys\/RiSyn,rfuentess\/RIOT,ks156\/RIOT,ks156\/RIOT,rfuentess\/RIOT,A-Paul\/RIOT,authmillenon\/RIOT,gebart\/RIOT,A-Paul\/RIOT,miri64\/RIOT,josephnoir\/RIOT,x3ro\/RIOT,aeneby\/RIOT,avmelnikoff\/RIOT,mfrey\/RIOT,kYc0o\/RIOT,avmelnikoff\/RIOT,toonst\/RIOT,rfuentess\/RIOT,ks156\/RIOT,avmelnikoff\/RIOT,roberthartung\/RIOT,kYc0o\/RIOT,aeneby\/RIOT,kbumsik\/RIOT,LudwigOrtmann\/RIOT,lazytech-org\/RIOT,basilfx\/RIOT,mfrey\/RIOT,roberthartung\/RIOT,authmillenon\/RIOT,roberthartung\/RIOT,basilfx\/RIOT,smlng\/RIOT,adrianghc\/RIOT,cladmi\/RIOT,josephnoir\/RIOT,toonst\/RIOT,miri64\/RIOT,neiljay\/RIOT,BytesGalore\/RIOT,immesys\/RiSyn,adrianghc\/RIOT,yogo1212\/RIOT,A-Paul\/RIOT,lazytech-org\/RIOT,LudwigKnuepfer\/RIOT,authmillenon\/RIOT,LudwigOrtmann\/RIOT,mtausig\/RIOT,mtausig\/RIOT,jasonatran\/RIOT,ant9000\/RIOT,mfrey\/RIOT,BytesGalore\/RIOT,josephnoir\/RIOT,adrianghc\/RIOT,smlng\/RIOT,LudwigKnuepfer\/RIOT,OTAkeys\/RIOT,lazytech-org\/RIOT,neiljay\/RIOT,jasonatran\/RIOT,A-Paul\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,Josar\/RIOT,LudwigOrtmann\/RIOT,authmillenon\/RIOT,mfrey\/RIOT,ant9000\/RIOT,lazytech-org\/RIOT,ant9000\/RIOT,LudwigOrtmann\/RIOT,x3ro\/RIOT,authmillenon\/RIOT,BytesGalore\/RIOT,kbumsik\/RIOT,aeneby\/RIOT,adrianghc\/RIOT,toonst\/RIOT,LudwigKnuepfer\/RIOT,basilfx\/RIOT,aeneby\/RIOT,roberthartung\/RIOT,Josar\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,LudwigOrtmann\/RIOT,LudwigKnuepfer\/RIOT,yogo1212\/RIOT,RIOT-OS\/RIOT,gebart\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,toonst\/RIOT,gebart\/RIOT,smlng\/RIOT,basilfx\/RIOT,ant9000\/RIOT,gebart\/RIOT,yogo1212\/RIOT,roberthartung\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,LudwigKnuepfer\/RIOT,kbumsik\/RIOT,rfuentess\/RIOT,avmelnikoff\/RIOT,neiljay\/RIOT,Josar\/RIOT,mfrey\/RIOT,lazytech-org\/RIOT,yogo1212\/RIOT,Josar\/RIOT,OlegHahm\/RIOT,kbumsik\/RIOT,biboc\/RIOT,OlegHahm\/RIOT,cladmi\/RIOT,kaspar030\/RIOT,miri64\/RIOT,mtausig\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"4849dff16ccaef7885f761741e99b26fa76d5052","subject":"Added ldscripts","message":"Added ldscripts\n","repos":"MITEVT\/lpc11cx4-library,MITEVT\/lpc11cx4-library","old_file":"ldscripts\/gcc.ld","new_file":"ldscripts\/gcc.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/MITEVT\/lpc11cx4-library.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"9712bc0567368ee40eb413883057824aa0249c08","subject":"Cancel 16-bit emergency code","message":"Cancel 16-bit emergency code\n","repos":"Tutul-\/tumuxOS,Tutul-\/tumuxOS,Tutul-\/tumuxOS","old_file":"src\/tumux\/arch\/x86\/linker.ld","new_file":"src\/tumux\/arch\/x86\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Tutul-\/tumuxOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"480e966737bdcc1dda02512fa0c54639fbc9f57e","subject":"cpu\/stm32f1: add opencm9-04 specific linker script","message":"cpu\/stm32f1: add opencm9-04 specific linker script\n","repos":"dailab\/RIOT,miri64\/RIOT,LudwigOrtmann\/RIOT,jfischer-phytec-iot\/RIOT,adrianghc\/RIOT,ant9000\/RIOT,adjih\/RIOT,beurdouche\/RIOT,hamilton-mote\/RIOT-OS,beurdouche\/RIOT,Ell-i\/RIOT,ks156\/RIOT,Hyungsin\/RIOT-OS,cladmi\/RIOT,dailab\/RIOT,LudwigOrtmann\/RIOT,LudwigOrtmann\/RIOT,kaleb-himes\/RIOT,dkm\/RIOT,TobiasFredersdorf\/RIOT,authmillenon\/RIOT,basilfx\/RIOT,Hyungsin\/RIOT-OS,immesys\/RiSyn,Ell-i\/RIOT,cladmi\/RIOT,kerneltask\/RIOT,LudwigKnuepfer\/RIOT,aeneby\/RIOT,gautric\/RIOT,beurdouche\/RIOT,LudwigKnuepfer\/RIOT,BytesGalore\/RIOT,yogo1212\/RIOT,thomaseichinger\/RIOT,smlng\/RIOT,mtausig\/RIOT,adjih\/RIOT,x3ro\/RIOT,josephnoir\/RIOT,neumodisch\/RIOT,A-Paul\/RIOT,hamilton-mote\/RIOT-OS,immesys\/RiSyn,RIOT-OS\/RIOT,gebart\/RIOT,kaleb-himes\/RIOT,Josar\/RIOT,aeneby\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,OTAkeys\/RIOT,gautric\/RIOT,kaleb-himes\/RIOT,toonst\/RIOT,A-Paul\/RIOT,Hyungsin\/RIOT-OS,kYc0o\/RIOT,ks156\/RIOT,mfrey\/RIOT,A-Paul\/RIOT,mfrey\/RIOT,jasonatran\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,gebart\/RIOT,ks156\/RIOT,josephnoir\/RIOT,syin2\/RIOT,roberthartung\/RIOT,basilfx\/RIOT,RIOT-OS\/RIOT,smlng\/RIOT,lazytech-org\/RIOT,aeneby\/RIOT,adrianghc\/RIOT,kYc0o\/RIOT,toonst\/RIOT,hamilton-mote\/RIOT-OS,jbeyerstedt\/RIOT-OTA-update,plushvoxel\/RIOT,OTAkeys\/RIOT,biboc\/RIOT,OlegHahm\/RIOT,gebart\/RIOT,kYc0o\/RIOT,OTAkeys\/RIOT,OTAkeys\/RIOT,roberthartung\/RIOT,plushvoxel\/RIOT,josephnoir\/RIOT,josephnoir\/RIOT,roberthartung\/RIOT,thomaseichinger\/RIOT,cladmi\/RIOT,kerneltask\/RIOT,smlng\/RIOT,aeneby\/RIOT,adjih\/RIOT,ks156\/RIOT,rfuentess\/RIOT,gautric\/RIOT,mtausig\/RIOT,A-Paul\/RIOT,mtausig\/RIOT,ks156\/RIOT,dkm\/RIOT,dkm\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,Josar\/RIOT,jfischer-phytec-iot\/RIOT,kaspar030\/RIOT,basilfx\/RIOT,TobiasFredersdorf\/RIOT,mtausig\/RIOT,dailab\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,syin2\/RIOT,Ell-i\/RIOT,kerneltask\/RIOT,mfrey\/RIOT,neiljay\/RIOT,TobiasFredersdorf\/RIOT,beurdouche\/RIOT,authmillenon\/RIOT,neumodisch\/RIOT,x3ro\/RIOT,biboc\/RIOT,miri64\/RIOT,roberthartung\/RIOT,LudwigKnuepfer\/RIOT,kerneltask\/RIOT,adrianghc\/RIOT,mfrey\/RIOT,ant9000\/RIOT,jfischer-phytec-iot\/RIOT,biboc\/RIOT,TobiasFredersdorf\/RIOT,kaspar030\/RIOT,neiljay\/RIOT,authmillenon\/RIOT,toonst\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,gebart\/RIOT,BytesGalore\/RIOT,avmelnikoff\/RIOT,Ell-i\/RIOT,x3ro\/RIOT,beurdouche\/RIOT,syin2\/RIOT,adrianghc\/RIOT,Josar\/RIOT,adrianghc\/RIOT,adjih\/RIOT,gebart\/RIOT,BytesGalore\/RIOT,jasonatran\/RIOT,dkm\/RIOT,OlegHahm\/RIOT,roberthartung\/RIOT,lazytech-org\/RIOT,rfuentess\/RIOT,thomaseichinger\/RIOT,kbumsik\/RIOT,plushvoxel\/RIOT,yogo1212\/RIOT,Josar\/RIOT,thomaseichinger\/RIOT,BytesGalore\/RIOT,kbumsik\/RIOT,TobiasFredersdorf\/RIOT,kaspar030\/RIOT,basilfx\/RIOT,avmelnikoff\/RIOT,mtausig\/RIOT,basilfx\/RIOT,plushvoxel\/RIOT,kaspar030\/RIOT,dailab\/RIOT,kaleb-himes\/RIOT,yogo1212\/RIOT,biboc\/RIOT,avmelnikoff\/RIOT,Ell-i\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,Hyungsin\/RIOT-OS,adjih\/RIOT,OlegHahm\/RIOT,kbumsik\/RIOT,LudwigOrtmann\/RIOT,neiljay\/RIOT,lazytech-org\/RIOT,kYc0o\/RIOT,miri64\/RIOT,jfischer-phytec-iot\/RIOT,x3ro\/RIOT,biboc\/RIOT,OTAkeys\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,BytesGalore\/RIOT,jfischer-phytec-iot\/RIOT,yogo1212\/RIOT,dailab\/RIOT,jasonatran\/RIOT,neumodisch\/RIOT,lazytech-org\/RIOT,gautric\/RIOT,mfrey\/RIOT,cladmi\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,jbeyerstedt\/RIOT-OTA-update,neiljay\/RIOT,kerneltask\/RIOT,LudwigOrtmann\/RIOT,jbeyerstedt\/RIOT-OTA-update,foss-for-synopsys-dwc-arc-processors\/RIOT,lazytech-org\/RIOT,aeneby\/RIOT,ant9000\/RIOT,Josar\/RIOT,avmelnikoff\/RIOT,hamilton-mote\/RIOT-OS,jbeyerstedt\/RIOT-OTA-update,neiljay\/RIOT,syin2\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,toonst\/RIOT,LudwigKnuepfer\/RIOT,smlng\/RIOT,kbumsik\/RIOT,plushvoxel\/RIOT,jbeyerstedt\/RIOT-OTA-update,toonst\/RIOT,immesys\/RiSyn,hamilton-mote\/RIOT-OS,kbumsik\/RIOT,rfuentess\/RIOT,josephnoir\/RIOT,miri64\/RIOT,gautric\/RIOT,Hyungsin\/RIOT-OS,LudwigOrtmann\/RIOT,neumodisch\/RIOT,smlng\/RIOT,kaleb-himes\/RIOT,immesys\/RiSyn,kaspar030\/RIOT,rfuentess\/RIOT,jasonatran\/RIOT,syin2\/RIOT,A-Paul\/RIOT,neumodisch\/RIOT,immesys\/RiSyn,neumodisch\/RIOT,cladmi\/RIOT,LudwigKnuepfer\/RIOT,thomaseichinger\/RIOT,immesys\/RiSyn,dkm\/RIOT,x3ro\/RIOT,rfuentess\/RIOT,avmelnikoff\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,ant9000\/RIOT,kYc0o\/RIOT","old_file":"cpu\/stm32f1\/ldscripts\/stm32f103cb_opencm9-04.ld","new_file":"cpu\/stm32f1\/ldscripts\/stm32f103cb_opencm9-04.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"d768f5b35757e87cae597ad1faa31f2f05146ee9","subject":"cpu\/sam0_common: add support for MCU used in Arduino MKR1000 board","message":"cpu\/sam0_common: add support for MCU used in Arduino MKR1000 board\n","repos":"jfischer-phytec-iot\/RIOT,plushvoxel\/RIOT,LudwigKnuepfer\/RIOT,yogo1212\/RIOT,neiljay\/RIOT,mtausig\/RIOT,kaleb-himes\/RIOT,adjih\/RIOT,miri64\/RIOT,dkm\/RIOT,biboc\/RIOT,aeneby\/RIOT,roberthartung\/RIOT,LudwigOrtmann\/RIOT,rfuentess\/RIOT,x3ro\/RIOT,dailab\/RIOT,plushvoxel\/RIOT,mfrey\/RIOT,gebart\/RIOT,toonst\/RIOT,Josar\/RIOT,OTAkeys\/RIOT,kaleb-himes\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,BytesGalore\/RIOT,miri64\/RIOT,A-Paul\/RIOT,RIOT-OS\/RIOT,plushvoxel\/RIOT,Hyungsin\/RIOT-OS,authmillenon\/RIOT,Hyungsin\/RIOT-OS,smlng\/RIOT,x3ro\/RIOT,mfrey\/RIOT,roberthartung\/RIOT,Ell-i\/RIOT,kYc0o\/RIOT,biboc\/RIOT,BytesGalore\/RIOT,authmillenon\/RIOT,A-Paul\/RIOT,jasonatran\/RIOT,gebart\/RIOT,neiljay\/RIOT,authmillenon\/RIOT,cladmi\/RIOT,avmelnikoff\/RIOT,hamilton-mote\/RIOT-OS,ks156\/RIOT,yogo1212\/RIOT,immesys\/RiSyn,OlegHahm\/RIOT,plushvoxel\/RIOT,Ell-i\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,mfrey\/RIOT,thomaseichinger\/RIOT,adrianghc\/RIOT,kaleb-himes\/RIOT,beurdouche\/RIOT,Josar\/RIOT,toonst\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,RIOT-OS\/RIOT,BytesGalore\/RIOT,OlegHahm\/RIOT,kbumsik\/RIOT,LudwigKnuepfer\/RIOT,neumodisch\/RIOT,neiljay\/RIOT,ant9000\/RIOT,ks156\/RIOT,LudwigKnuepfer\/RIOT,immesys\/RiSyn,avmelnikoff\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,mtausig\/RIOT,rfuentess\/RIOT,avmelnikoff\/RIOT,dailab\/RIOT,mfrey\/RIOT,adjih\/RIOT,Ell-i\/RIOT,LudwigOrtmann\/RIOT,josephnoir\/RIOT,OTAkeys\/RIOT,lazytech-org\/RIOT,beurdouche\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,josephnoir\/RIOT,cladmi\/RIOT,dkm\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,lazytech-org\/RIOT,toonst\/RIOT,kaleb-himes\/RIOT,RIOT-OS\/RIOT,rfuentess\/RIOT,aeneby\/RIOT,Josar\/RIOT,kbumsik\/RIOT,aeneby\/RIOT,kerneltask\/RIOT,hamilton-mote\/RIOT-OS,jfischer-phytec-iot\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,neumodisch\/RIOT,miri64\/RIOT,x3ro\/RIOT,avmelnikoff\/RIOT,basilfx\/RIOT,Hyungsin\/RIOT-OS,gebart\/RIOT,dkm\/RIOT,adjih\/RIOT,Josar\/RIOT,dailab\/RIOT,authmillenon\/RIOT,josephnoir\/RIOT,adrianghc\/RIOT,thomaseichinger\/RIOT,kaspar030\/RIOT,avmelnikoff\/RIOT,adrianghc\/RIOT,basilfx\/RIOT,x3ro\/RIOT,neiljay\/RIOT,rfuentess\/RIOT,basilfx\/RIOT,ant9000\/RIOT,Ell-i\/RIOT,miri64\/RIOT,jfischer-phytec-iot\/RIOT,OTAkeys\/RIOT,ks156\/RIOT,A-Paul\/RIOT,jasonatran\/RIOT,biboc\/RIOT,kerneltask\/RIOT,kaspar030\/RIOT,neumodisch\/RIOT,BytesGalore\/RIOT,smlng\/RIOT,thomaseichinger\/RIOT,lazytech-org\/RIOT,mfrey\/RIOT,immesys\/RiSyn,kbumsik\/RIOT,gebart\/RIOT,ant9000\/RIOT,hamilton-mote\/RIOT-OS,beurdouche\/RIOT,x3ro\/RIOT,authmillenon\/RIOT,adjih\/RIOT,kaspar030\/RIOT,yogo1212\/RIOT,thomaseichinger\/RIOT,LudwigKnuepfer\/RIOT,rfuentess\/RIOT,jfischer-phytec-iot\/RIOT,LudwigOrtmann\/RIOT,gebart\/RIOT,immesys\/RiSyn,kaspar030\/RIOT,basilfx\/RIOT,A-Paul\/RIOT,mtausig\/RIOT,miri64\/RIOT,neumodisch\/RIOT,lazytech-org\/RIOT,kYc0o\/RIOT,neumodisch\/RIOT,LudwigOrtmann\/RIOT,Ell-i\/RIOT,smlng\/RIOT,kYc0o\/RIOT,cladmi\/RIOT,aeneby\/RIOT,beurdouche\/RIOT,jasonatran\/RIOT,josephnoir\/RIOT,neiljay\/RIOT,biboc\/RIOT,LudwigOrtmann\/RIOT,yogo1212\/RIOT,biboc\/RIOT,roberthartung\/RIOT,cladmi\/RIOT,A-Paul\/RIOT,dkm\/RIOT,ks156\/RIOT,neumodisch\/RIOT,dailab\/RIOT,josephnoir\/RIOT,aeneby\/RIOT,plushvoxel\/RIOT,smlng\/RIOT,beurdouche\/RIOT,hamilton-mote\/RIOT-OS,OlegHahm\/RIOT,LudwigOrtmann\/RIOT,kaleb-himes\/RIOT,roberthartung\/RIOT,kerneltask\/RIOT,jasonatran\/RIOT,hamilton-mote\/RIOT-OS,toonst\/RIOT,OlegHahm\/RIOT,kerneltask\/RIOT,cladmi\/RIOT,dailab\/RIOT,jfischer-phytec-iot\/RIOT,ks156\/RIOT,Hyungsin\/RIOT-OS,lazytech-org\/RIOT,smlng\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,immesys\/RiSyn,BytesGalore\/RIOT,thomaseichinger\/RIOT,basilfx\/RIOT,mtausig\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,LudwigKnuepfer\/RIOT,dkm\/RIOT,immesys\/RiSyn,Hyungsin\/RIOT-OS,ant9000\/RIOT,kerneltask\/RIOT,toonst\/RIOT,yogo1212\/RIOT,roberthartung\/RIOT,RIOT-OS\/RIOT,adjih\/RIOT,mtausig\/RIOT,adrianghc\/RIOT,kbumsik\/RIOT,Josar\/RIOT,kYc0o\/RIOT,kbumsik\/RIOT,RIOT-OS\/RIOT,adrianghc\/RIOT","old_file":"cpu\/sam0_common\/ldscripts\/samd21g18a_mkr1000.ld","new_file":"cpu\/sam0_common\/ldscripts\/samd21g18a_mkr1000.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"0d6bec9d8c74d3005e6899eb923f821946963ee9","subject":"LD - space reserved for vectors in RAM","message":"LD - space reserved for vectors in RAM\n","repos":"jpbrucker\/mbed,arostm\/mbed-os,jpbrucker\/mbed,bcostm\/mbed-os,CalSol\/mbed,bcostm\/mbed-os,NitinBhaskar\/mbed,logost\/mbed,ryankurte\/mbed-os,Marcomissyou\/mbed,pi19404\/mbed,mbedmicro\/mbed,sam-geek\/mbed,nabilbendafi\/mbed,infinnovation\/mbed-os,hwfwgrp\/mbed,arostm\/mbed-os,EmuxEvans\/mbed,dbestm\/mbed,bikeNomad\/mbed,sg-\/mbed-drivers,bentwire\/mbed,K4zuki\/mbed,bcostm\/mbed-os,autopulated\/mbed,netzimme\/mbed-os,bentwire\/mbed,fpiot\/mbed-ats,iriark01\/mbed-drivers,betzw\/mbed-os,Shengliang\/mbed,netzimme\/mbed-os,Sweet-Peas\/mbed,nabilbendafi\/mbed,catiedev\/mbed-os,JasonHow44\/mbed,Willem23\/mbed,bikeNomad\/mbed,kpurusho\/mbed,Timmmm\/mbed,ryankurte\/mbed-os,alertby\/mbed,c1728p9\/mbed-os,alertby\/mbed,bulislaw\/mbed-os,nRFMesh\/mbed-os,logost\/mbed,svastm\/mbed,mikaleppanen\/mbed-os,Marcomissyou\/mbed,mazimkhan\/mbed-os,pradeep-gr\/mbed-os5-onsemi,nabilbendafi\/mbed,geky\/mbed,RonEld\/mbed,rgrover\/mbed,struempelix\/mbed,catiedev\/mbed-os,arostm\/mbed-os,getopenmono\/mbed,c1728p9\/mbed-os,screamerbg\/mbed,HeadsUpDisplayInc\/mbed,jamesadevine\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,nvlsianpu\/mbed,monkiineko\/mbed-os,Tiryoh\/mbed,pedromes\/mbed,svogl\/mbed-os,pi19404\/mbed,adustm\/mbed,jeremybrodt\/mbed,FranklyDev\/mbed,ARM-software\/mbed-beetle,rosterloh\/mbed,infinnovation\/mbed-os,autopulated\/mbed,wodji\/mbed,RonEld\/mbed,c1728p9\/mbed-os,monkiineko\/mbed-os,Sweet-Peas\/mbed,larks\/mbed,autopulated\/mbed,svastm\/mbed,wodji\/mbed,bulislaw\/mbed-os,NXPmicro\/mbed,mbedmicro\/mbed,mnlipp\/mbed,autopulated\/mbed,andcor02\/mbed-os,Sweet-Peas\/mbed,tung7970\/mbed-os,pedromes\/mbed,fahhem\/mbed-os,cvtsi2sd\/mbed-os,DanKupiniak\/mbed,getopenmono\/mbed,pbrook\/mbed,kjbracey-arm\/mbed,ARM-software\/mbed-beetle,Marcomissyou\/mbed,adustm\/mbed,infinnovation\/mbed-os,Marcomissyou\/mbed,sam-geek\/mbed,CalSol\/mbed,fahhem\/mbed-os,jamesadevine\/mbed,ban4jp\/mbed,maximmbed\/mbed,jrjang\/mbed,masaohamanaka\/mbed,jferreir\/mbed,pradeep-gr\/mbed-os5-onsemi,larks\/mbed,mazimkhan\/mbed-os,FranklyDev\/mbed,c1728p9\/mbed-os,mikaleppanen\/mbed-os,larks\/mbed,pbrook\/mbed,fpiot\/mbed-ats,tung7970\/mbed-os-1,radhika-raghavendran\/mbed-os5.1-onsemi,jeremybrodt\/mbed,GustavWi\/mbed,NXPmicro\/mbed,K4zuki\/mbed,mbedmicro\/mbed,fpiot\/mbed-ats,kl-cruz\/mbed-os,GustavWi\/mbed,HeadsUpDisplayInc\/mbed,jamesadevine\/mbed,Timmmm\/mbed,rgrover\/mbed,xcrespo\/mbed,Timmmm\/mbed,al177\/mbed,sam-geek\/mbed,hwfwgrp\/mbed,tung7970\/mbed-os,NXPmicro\/mbed,adamgreen\/mbed,devanlai\/mbed,K4zuki\/mbed,tung7970\/mbed-os,betzw\/mbed-os,fanghuaqi\/mbed,mikaleppanen\/mbed-os,Shengliang\/mbed,Marcomissyou\/mbed,brstew\/MBED-BUILD,screamerbg\/mbed,geky\/mbed,NitinBhaskar\/mbed,ban4jp\/mbed,mnlipp\/mbed,geky\/mbed,mmorenobarm\/mbed-os,naves-thiago\/mbed-midi,FranklyDev\/mbed,nRFMesh\/mbed-os,cvtsi2sd\/mbed-os,kl-cruz\/mbed-os,kpurusho\/mbed,0xc0170\/mbed-drivers,adustm\/mbed,mikaleppanen\/mbed-os,pradeep-gr\/mbed-os5-onsemi,ryankurte\/mbed-os,nRFMesh\/mbed-os,mazimkhan\/mbed-os,nvlsianpu\/mbed,Timmmm\/mbed,andcor02\/mbed-os,K4zuki\/mbed,jrjang\/mbed,Archcady\/mbed-os,devanlai\/mbed,YarivCol\/mbed-os,JasonHow44\/mbed,pradeep-gr\/mbed-os5-onsemi,fvincenzo\/mbed-os,pedromes\/mbed,JasonHow44\/mbed,tung7970\/mbed-os-1,NXPmicro\/mbed,naves-thiago\/mbed-midi,mmorenobarm\/mbed-os,jrjang\/mbed,jamesadevine\/mbed,theotherjimmy\/mbed,adustm\/mbed,monkiineko\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,dbestm\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,Archcady\/mbed-os,fanghuaqi\/mbed,mnlipp\/mbed,alertby\/mbed,xcrespo\/mbed,YarivCol\/mbed-os,fvincenzo\/mbed-os,Tiryoh\/mbed,GustavWi\/mbed,xcrespo\/mbed,struempelix\/mbed,brstew\/MBED-BUILD,svogl\/mbed-os,bikeNomad\/mbed,karsev\/mbed-os,jrjang\/mbed,nvlsianpu\/mbed,andreaslarssonublox\/mbed,bikeNomad\/mbed,maximmbed\/mbed,NitinBhaskar\/mbed,bulislaw\/mbed-os,al177\/mbed,Shengliang\/mbed,geky\/mbed,pbrook\/mbed,kpurusho\/mbed,Willem23\/mbed,andcor02\/mbed-os,0xc0170\/mbed-drivers,al177\/mbed,RonEld\/mbed,HeadsUpDisplayInc\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,hwfwgrp\/mbed,tung7970\/mbed-os-1,fanghuaqi\/mbed,rosterloh\/mbed,YarivCol\/mbed-os,bikeNomad\/mbed,nabilbendafi\/mbed,rosterloh\/mbed,jamesadevine\/mbed,monkiineko\/mbed-os,maximmbed\/mbed,autopulated\/mbed,pbrook\/mbed,fahhem\/mbed-os,devanlai\/mbed,larks\/mbed,Archcady\/mbed-os,HeadsUpDisplayInc\/mbed,alertby\/mbed,struempelix\/mbed,rgrover\/mbed,pedromes\/mbed,mikaleppanen\/mbed-os,adamgreen\/mbed,masaohamanaka\/mbed,Willem23\/mbed,Archcady\/mbed-os,wodji\/mbed,FranklyDev\/mbed,NitinBhaskar\/mbed,catiedev\/mbed-os,andreaslarssonublox\/mbed,Archcady\/mbed-os,theotherjimmy\/mbed,j-greffe\/mbed-os,bremoran\/mbed-drivers,getopenmono\/mbed,sam-geek\/mbed,fvincenzo\/mbed-os,HeadsUpDisplayInc\/mbed,rosterloh\/mbed,Tiryoh\/mbed,GustavWi\/mbed,andcor02\/mbed-os,jpbrucker\/mbed,bentwire\/mbed,kl-cruz\/mbed-os,al177\/mbed,fpiot\/mbed-ats,jrjang\/mbed,iriark01\/mbed-drivers,screamerbg\/mbed,dbestm\/mbed,catiedev\/mbed-os,Tiryoh\/mbed,Sweet-Peas\/mbed,jamesadevine\/mbed,theotherjimmy\/mbed,dbestm\/mbed,hwfwgrp\/mbed,j-greffe\/mbed-os,autopulated\/mbed,svastm\/mbed,Sweet-Peas\/mbed,catiedev\/mbed-os,bcostm\/mbed-os,karsev\/mbed-os,naves-thiago\/mbed-midi,al177\/mbed,YarivCol\/mbed-os,rgrover\/mbed,xcrespo\/mbed,EmuxEvans\/mbed,mikaleppanen\/mbed-os,masaohamanaka\/mbed,sam-geek\/mbed,struempelix\/mbed,bcostm\/mbed-os,adamgreen\/mbed,NitinBhaskar\/mbed,svastm\/mbed,CalSol\/mbed,wodji\/mbed,larks\/mbed,pedromes\/mbed,pbrook\/mbed,cvtsi2sd\/mbed-os,NordicSemiconductor\/mbed,naves-thiago\/mbed-midi,RonEld\/mbed,fahhem\/mbed-os,arostm\/mbed-os,svogl\/mbed-os,bremoran\/mbed-drivers,ban4jp\/mbed,pi19404\/mbed,karsev\/mbed-os,catiedev\/mbed-os,nabilbendafi\/mbed,jferreir\/mbed,Tiryoh\/mbed,mazimkhan\/mbed-os,j-greffe\/mbed-os,c1728p9\/mbed-os,theotherjimmy\/mbed,theotherjimmy\/mbed,geky\/mbed,mmorenobarm\/mbed-os,DanKupiniak\/mbed,maximmbed\/mbed,kjbracey-arm\/mbed,EmuxEvans\/mbed,andreaslarssonublox\/mbed,monkiineko\/mbed-os,bentwire\/mbed,adustm\/mbed,pbrook\/mbed,brstew\/MBED-BUILD,K4zuki\/mbed,netzimme\/mbed-os,ban4jp\/mbed,xcrespo\/mbed,karsev\/mbed-os,fanghuaqi\/mbed,Timmmm\/mbed,mnlipp\/mbed,NordicSemiconductor\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,Willem23\/mbed,svogl\/mbed-os,HeadsUpDisplayInc\/mbed,kl-cruz\/mbed-os,ban4jp\/mbed,sg-\/mbed-drivers,mazimkhan\/mbed-os,fvincenzo\/mbed-os,svastm\/mbed,jrjang\/mbed,mnlipp\/mbed,CalSol\/mbed,DanKupiniak\/mbed,pi19404\/mbed,ryankurte\/mbed-os,kpurusho\/mbed,JasonHow44\/mbed,monkiineko\/mbed-os,andcor02\/mbed-os,j-greffe\/mbed-os,bentwire\/mbed,wodji\/mbed,jpbrucker\/mbed,larks\/mbed,bcostm\/mbed-os,logost\/mbed,fanghuaqi\/mbed,infinnovation\/mbed-os,logost\/mbed,nRFMesh\/mbed-os,pedromes\/mbed,K4zuki\/mbed,adamgreen\/mbed,naves-thiago\/mbed-midi,struempelix\/mbed,nabilbendafi\/mbed,rosterloh\/mbed,svogl\/mbed-os,fahhem\/mbed-os,nvlsianpu\/mbed,betzw\/mbed-os,logost\/mbed,mazimkhan\/mbed-os,jferreir\/mbed,kpurusho\/mbed,DanKupiniak\/mbed,NXPmicro\/mbed,karsev\/mbed-os,screamerbg\/mbed,logost\/mbed,rosterloh\/mbed,YarivCol\/mbed-os,NordicSemiconductor\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,getopenmono\/mbed,cvtsi2sd\/mbed-os,FranklyDev\/mbed,c1728p9\/mbed-os,Archcady\/mbed-os,kjbracey-arm\/mbed,brstew\/MBED-BUILD,bentwire\/mbed,pi19404\/mbed,bulislaw\/mbed-os,netzimme\/mbed-os,jeremybrodt\/mbed,tung7970\/mbed-os,kjbracey-arm\/mbed,EmuxEvans\/mbed,adustm\/mbed,hwfwgrp\/mbed,mnlipp\/mbed,bulislaw\/mbed-os,netzimme\/mbed-os,YarivCol\/mbed-os,rgrover\/mbed,ryankurte\/mbed-os,getopenmono\/mbed,andcor02\/mbed-os,masaohamanaka\/mbed,dbestm\/mbed,CalSol\/mbed,EmuxEvans\/mbed,ARM-software\/mbed-beetle,Willem23\/mbed,nRFMesh\/mbed-os,adamgreen\/mbed,getopenmono\/mbed,alertby\/mbed,JasonHow44\/mbed,kl-cruz\/mbed-os,fpiot\/mbed-ats,cvtsi2sd\/mbed-os,cvtsi2sd\/mbed-os,devanlai\/mbed,kpurusho\/mbed,fvincenzo\/mbed-os,svogl\/mbed-os,andreaslarssonublox\/mbed,netzimme\/mbed-os,nvlsianpu\/mbed,mmorenobarm\/mbed-os,NXPmicro\/mbed,theotherjimmy\/mbed,infinnovation\/mbed-os,jpbrucker\/mbed,ryankurte\/mbed-os,GustavWi\/mbed,maximmbed\/mbed,wodji\/mbed,Shengliang\/mbed,ARM-software\/mbed-beetle,j-greffe\/mbed-os,tung7970\/mbed-os-1,maximmbed\/mbed,screamerbg\/mbed,NordicSemiconductor\/mbed,al177\/mbed,betzw\/mbed-os,Marcomissyou\/mbed,adamgreen\/mbed,tung7970\/mbed-os,brstew\/MBED-BUILD,screamerbg\/mbed,jeremybrodt\/mbed,EmuxEvans\/mbed,struempelix\/mbed,andreaslarssonublox\/mbed,Timmmm\/mbed,betzw\/mbed-os,jferreir\/mbed,fahhem\/mbed-os,masaohamanaka\/mbed,karsev\/mbed-os,tung7970\/mbed-os-1,jferreir\/mbed,xcrespo\/mbed,pradeep-gr\/mbed-os5-onsemi,j-greffe\/mbed-os,JasonHow44\/mbed,brstew\/MBED-BUILD,Shengliang\/mbed,pi19404\/mbed,mbedmicro\/mbed,jeremybrodt\/mbed,arostm\/mbed-os,hwfwgrp\/mbed,dbestm\/mbed,CalSol\/mbed,jpbrucker\/mbed,ban4jp\/mbed,naves-thiago\/mbed-midi,Shengliang\/mbed,infinnovation\/mbed-os,alertby\/mbed,mbedmicro\/mbed,nvlsianpu\/mbed,jferreir\/mbed,bulislaw\/mbed-os,mmorenobarm\/mbed-os,Tiryoh\/mbed,Sweet-Peas\/mbed,RonEld\/mbed,RonEld\/mbed,kl-cruz\/mbed-os,nRFMesh\/mbed-os,devanlai\/mbed,mmorenobarm\/mbed-os,devanlai\/mbed,fpiot\/mbed-ats,arostm\/mbed-os,masaohamanaka\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_Freescale\/TARGET_KL25Z\/TOOLCHAIN_GCC_ARM\/MKL25Z4.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_Freescale\/TARGET_KL25Z\/TOOLCHAIN_GCC_ARM\/MKL25Z4.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/nvlsianpu\/mbed.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"09686ea26d507a1d9a51abf3bfd70b5df201f3e5","subject":"produce an elf file, instead of a flat binary","message":"produce an elf file, instead of a flat binary\n","repos":"ReturnInfinity\/Alloy,ReturnInfinity\/Alloy","old_file":"alloy.ld","new_file":"alloy.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ReturnInfinity\/Alloy.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"77bd5da8e73bf917d931036dfce77a7e0c64e7b5","subject":"Lpc: Linker: lpc11c24 only has 8kbit of RAM","message":"Lpc: Linker: lpc11c24 only has 8kbit of RAM\n","repos":"chrism333\/xpcc,dergraaf\/xpcc,chrism333\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc,chrism333\/xpcc,chrism333\/xpcc","old_file":"src\/xpcc\/architecture\/platform\/linker\/lpc\/lpc11c24.ld","new_file":"src\/xpcc\/architecture\/platform\/linker\/lpc\/lpc11c24.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/dergraaf\/xpcc.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"a9cefb2fb482f79fe6741a46152636a010e99a05","subject":"Adds missing memory map.","message":"Adds missing memory map.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/ti-bracz-acc\/memory_map.ld","new_file":"boards\/ti-bracz-acc\/memory_map.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/bakerstu\/openmrn.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"4e0299259fb7a526b3e0020bd7af624fcd60c2e7","subject":"Fix linker error","message":"Fix linker error\n","repos":"Tutul-\/tumuxOS,Tutul-\/tumuxOS,Tutul-\/tumuxOS","old_file":"src\/kernel\/arch\/x86\/linker.ld","new_file":"src\/kernel\/arch\/x86\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Tutul-\/tumuxOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"e81dbfc42a963ec68aa67caf0f6f36d15bee8ef8","subject":"Issue #102 chose replacement file as official file. Resolved the conflict.","message":"Issue #102 chose replacement file as official file. Resolved the conflict.\n\n\nFormer-commit-id: a95174d04b09b89e937dd68c0c966b7332571c9e","repos":"majenkotech\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX","old_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-32MX460F512L.ld","new_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-32MX460F512L.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ricklon\/chipKIT32-MAX.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"c5e65e85da7d1472fe5ee0d901f76da35753bcee","subject":"the bootloader linker script","message":"the bootloader linker script\n","repos":"TorstenRobitzki\/bluetoe,TorstenRobitzki\/bluetoe","old_file":"examples\/nrf51\/bootloader.ld","new_file":"examples\/nrf51\/bootloader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/TorstenRobitzki\/bluetoe.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"e466685666b25b1d5828420e405c21945797604f","subject":"copy of L476RG ld file","message":"copy of L476RG ld file\n","repos":"ryankurte\/mbed-os,andcor02\/mbed-os,kjbracey-arm\/mbed,mbedmicro\/mbed,HeadsUpDisplayInc\/mbed,mazimkhan\/mbed-os,andcor02\/mbed-os,karsev\/mbed-os,CalSol\/mbed,betzw\/mbed-os,ryankurte\/mbed-os,karsev\/mbed-os,karsev\/mbed-os,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,mazimkhan\/mbed-os,kjbracey-arm\/mbed,Archcady\/mbed-os,c1728p9\/mbed-os,CalSol\/mbed,ryankurte\/mbed-os,c1728p9\/mbed-os,andcor02\/mbed-os,CalSol\/mbed,betzw\/mbed-os,mazimkhan\/mbed-os,betzw\/mbed-os,infinnovation\/mbed-os,Archcady\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,HeadsUpDisplayInc\/mbed,karsev\/mbed-os,CalSol\/mbed,kjbracey-arm\/mbed,betzw\/mbed-os,mazimkhan\/mbed-os,mazimkhan\/mbed-os,infinnovation\/mbed-os,betzw\/mbed-os,ryankurte\/mbed-os,HeadsUpDisplayInc\/mbed,Archcady\/mbed-os,ryankurte\/mbed-os,Archcady\/mbed-os,andcor02\/mbed-os,HeadsUpDisplayInc\/mbed,ryankurte\/mbed-os,HeadsUpDisplayInc\/mbed,CalSol\/mbed,infinnovation\/mbed-os,betzw\/mbed-os,Archcady\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,karsev\/mbed-os,infinnovation\/mbed-os,andcor02\/mbed-os,mbedmicro\/mbed,c1728p9\/mbed-os,infinnovation\/mbed-os,mbedmicro\/mbed,kjbracey-arm\/mbed,CalSol\/mbed,mbedmicro\/mbed,karsev\/mbed-os,Archcady\/mbed-os,infinnovation\/mbed-os,mazimkhan\/mbed-os","old_file":"targets\/TARGET_STM\/TARGET_STM32L4\/TARGET_STM32L476xG\/TARGET_SILICA_SENSOR_NODE\/device\/TOOLCHAIN_GCC_ARM\/STM32L476XX.ld","new_file":"targets\/TARGET_STM\/TARGET_STM32L4\/TARGET_STM32L476xG\/TARGET_SILICA_SENSOR_NODE\/device\/TOOLCHAIN_GCC_ARM\/STM32L476XX.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kjbracey-arm\/mbed.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"986c6cb288e7318c78a573d53be104337f22ac99","subject":"tiva_c: Add dummy iomem.ld to appease build system","message":"tiva_c: Add dummy iomem.ld to appease build system\n","repos":"dirvine\/zinc,mcoffin\/zinc,posborne\/zinc,tempbottle\/zinc,posborne\/zinc,phil-opp\/zinc,richo\/zinc,troplin\/zinc,tempbottle\/zinc,placrosse\/zinc,ryankurte\/zinc,farcaller\/zinc,placrosse\/zinc,richo\/zinc,ntwyman\/zinc,ntwyman\/zinc,richo\/zinc,mcoffin\/zinc,posborne\/zinc,farcaller\/zinc,ntwyman\/zinc,dirvine\/zinc,mcoffin\/zinc,hackndev\/zinc,dirvine\/zinc,troplin\/zinc,placrosse\/zinc,hackndev\/zinc,ntwyman\/zinc,troplin\/zinc,troplin\/zinc,posborne\/zinc,posborne\/zinc,ryankurte\/zinc,ntwyman\/zinc,farcaller\/zinc,phil-opp\/zinc,hackndev\/zinc,richo\/zinc,hackndev\/zinc,ryankurte\/zinc,farcaller\/zinc,placrosse\/zinc,phil-opp\/zinc,placrosse\/zinc,phil-opp\/zinc,mcoffin\/zinc,ryankurte\/zinc,ryankurte\/zinc,richo\/zinc,tempbottle\/zinc,farcaller\/zinc,troplin\/zinc,dirvine\/zinc,tempbottle\/zinc,phil-opp\/zinc,tempbottle\/zinc,hackndev\/zinc,mcoffin\/zinc,dirvine\/zinc","old_file":"src\/hal\/tiva_c\/iomem.ld","new_file":"src\/hal\/tiva_c\/iomem.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/troplin\/zinc.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f27113b2ccfdc183a9631253cc602af9ece88a6c","subject":"cpu\/stm32f1: add linkerscript for stm32f103rb","message":"cpu\/stm32f1: add linkerscript for stm32f103rb\n","repos":"attdona\/RIOT,dkm\/RIOT,stevenj\/RIOT,beurdouche\/RIOT,jremmert-phytec-iot\/RIOT,Yonezawa-T2\/RIOT,l3nko\/RIOT,malosek\/RIOT,plushvoxel\/RIOT,jfischer-phytec-iot\/RIOT,neumodisch\/RIOT,syin2\/RIOT,altairpearl\/RIOT,alignan\/RIOT,jasonatran\/RIOT,l3nko\/RIOT,l3nko\/RIOT,neumodisch\/RIOT,syin2\/RIOT,alignan\/RIOT,jremmert-phytec-iot\/RIOT,rakendrathapa\/RIOT,adrianghc\/RIOT,TobiasFredersdorf\/RIOT,malosek\/RIOT,binarylemon\/RIOT,LudwigOrtmann\/RIOT,TobiasFredersdorf\/RIOT,authmillenon\/RIOT,shady33\/RIOT,immesys\/RiSyn,katezilla\/RIOT,jremmert-phytec-iot\/RIOT,TobiasFredersdorf\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,dailab\/RIOT,kbumsik\/RIOT,aeneby\/RIOT,Ell-i\/RIOT,ant9000\/RIOT,cladmi\/RIOT,RBartz\/RIOT,lazytech-org\/RIOT,binarylemon\/RIOT,FrancescoErmini\/RIOT,adjih\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,OTAkeys\/RIOT,Yonezawa-T2\/RIOT,OlegHahm\/RIOT,FrancescoErmini\/RIOT,x3ro\/RIOT,aeneby\/RIOT,Ell-i\/RIOT,dailab\/RIOT,miri64\/RIOT,attdona\/RIOT,aeneby\/RIOT,immesys\/RiSyn,wentaoshang\/RIOT,biboc\/RIOT,attdona\/RIOT,MohmadAyman\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,biboc\/RIOT,jbeyerstedt\/RIOT-OTA-update,rakendrathapa\/RIOT,attdona\/RIOT,kaleb-himes\/RIOT,jbeyerstedt\/RIOT-OTA-update,LudwigOrtmann\/RIOT,A-Paul\/RIOT,stevenj\/RIOT,ant9000\/RIOT,kbumsik\/RIOT,rajma996\/RIOT,brettswann\/RIOT,kYc0o\/RIOT,toonst\/RIOT,Yonezawa-T2\/RIOT,d00616\/RIOT,shady33\/RIOT,tfar\/RIOT,lazytech-org\/RIOT,gebart\/RIOT,x3ro\/RIOT,kaspar030\/RIOT,LudwigOrtmann\/RIOT,syin2\/RIOT,kaspar030\/RIOT,wentaoshang\/RIOT,ks156\/RIOT,BytesGalore\/RIOT,biboc\/RIOT,dailab\/RIOT,jbeyerstedt\/RIOT-OTA-update,rfuentess\/RIOT,ks156\/RIOT,rakendrathapa\/RIOT,plushvoxel\/RIOT,syin2\/RIOT,neumodisch\/RIOT,backenklee\/RIOT,neiljay\/RIOT,zhuoshuguo\/RIOT,jremmert-phytec-iot\/RIOT,mtausig\/RIOT,A-Paul\/RIOT,aeneby\/RIOT,altairpearl\/RIOT,katezilla\/RIOT,zhuoshuguo\/RIOT,malosek\/RIOT,syin2\/RIOT,lazytech-org\/RIOT,asanka-code\/RIOT,zhuoshuguo\/RIOT,Ell-i\/RIOT,TobiasFredersdorf\/RIOT,yogo1212\/RIOT,OlegHahm\/RIOT,adrianghc\/RIOT,smlng\/RIOT,gautric\/RIOT,Josar\/RIOT,dkm\/RIOT,mtausig\/RIOT,alignan\/RIOT,cladmi\/RIOT,LudwigKnuepfer\/RIOT,dailab\/RIOT,rousselk\/RIOT,jfischer-phytec-iot\/RIOT,binarylemon\/RIOT,hamilton-mote\/RIOT-OS,shady33\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,x3ro\/RIOT,kerneltask\/RIOT,kerneltask\/RIOT,basilfx\/RIOT,immesys\/RiSyn,RBartz\/RIOT,l3nko\/RIOT,mfrey\/RIOT,rajma996\/RIOT,zhuoshuguo\/RIOT,beurdouche\/RIOT,Josar\/RIOT,backenklee\/RIOT,adjih\/RIOT,altairpearl\/RIOT,rfuentess\/RIOT,asanka-code\/RIOT,miri64\/RIOT,tfar\/RIOT,Josar\/RIOT,gebart\/RIOT,A-Paul\/RIOT,thomaseichinger\/RIOT,mfrey\/RIOT,stevenj\/RIOT,thomaseichinger\/RIOT,Josar\/RIOT,mfrey\/RIOT,josephnoir\/RIOT,adrianghc\/RIOT,neiljay\/RIOT,Hyungsin\/RIOT-OS,mfrey\/RIOT,LudwigKnuepfer\/RIOT,josephnoir\/RIOT,kbumsik\/RIOT,josephnoir\/RIOT,plushvoxel\/RIOT,thomaseichinger\/RIOT,smlng\/RIOT,zhuoshuguo\/RIOT,MohmadAyman\/RIOT,MohmadAyman\/RIOT,hamilton-mote\/RIOT-OS,asanka-code\/RIOT,FrancescoErmini\/RIOT,BytesGalore\/RIOT,neiljay\/RIOT,backenklee\/RIOT,josephnoir\/RIOT,basilfx\/RIOT,smlng\/RIOT,kYc0o\/RIOT,altairpearl\/RIOT,brettswann\/RIOT,jasonatran\/RIOT,stevenj\/RIOT,katezilla\/RIOT,hamilton-mote\/RIOT-OS,binarylemon\/RIOT,RBartz\/RIOT,avmelnikoff\/RIOT,Yonezawa-T2\/RIOT,BytesGalore\/RIOT,kYc0o\/RIOT,avmelnikoff\/RIOT,d00616\/RIOT,binarylemon\/RIOT,d00616\/RIOT,MohmadAyman\/RIOT,d00616\/RIOT,biboc\/RIOT,jasonatran\/RIOT,LudwigOrtmann\/RIOT,RubikonAlpha\/RIOT,Ell-i\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,LudwigKnuepfer\/RIOT,brettswann\/RIOT,ant9000\/RIOT,kaspar030\/RIOT,tfar\/RIOT,smlng\/RIOT,authmillenon\/RIOT,cladmi\/RIOT,asanka-code\/RIOT,asanka-code\/RIOT,jfischer-phytec-iot\/RIOT,authmillenon\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,yogo1212\/RIOT,rfuentess\/RIOT,d00616\/RIOT,katezilla\/RIOT,miri64\/RIOT,gautric\/RIOT,kb2ma\/RIOT,katezilla\/RIOT,shady33\/RIOT,rousselk\/RIOT,OTAkeys\/RIOT,kb2ma\/RIOT,immesys\/RiSyn,kaleb-himes\/RIOT,rousselk\/RIOT,kYc0o\/RIOT,LudwigKnuepfer\/RIOT,immesys\/RiSyn,kbumsik\/RIOT,lazytech-org\/RIOT,miri64\/RIOT,neiljay\/RIOT,gebart\/RIOT,ks156\/RIOT,OlegHahm\/RIOT,adjih\/RIOT,Hyungsin\/RIOT-OS,wentaoshang\/RIOT,malosek\/RIOT,gautric\/RIOT,alignan\/RIOT,LudwigOrtmann\/RIOT,toonst\/RIOT,kaspar030\/RIOT,Josar\/RIOT,backenklee\/RIOT,OlegHahm\/RIOT,ks156\/RIOT,rakendrathapa\/RIOT,brettswann\/RIOT,lazytech-org\/RIOT,FrancescoErmini\/RIOT,biboc\/RIOT,dkm\/RIOT,plushvoxel\/RIOT,FrancescoErmini\/RIOT,RubikonAlpha\/RIOT,attdona\/RIOT,RubikonAlpha\/RIOT,aeneby\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,LudwigOrtmann\/RIOT,RIOT-OS\/RIOT,kbumsik\/RIOT,tfar\/RIOT,kaspar030\/RIOT,gautric\/RIOT,kb2ma\/RIOT,kaleb-himes\/RIOT,rakendrathapa\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,RIOT-OS\/RIOT,ks156\/RIOT,avmelnikoff\/RIOT,OTAkeys\/RIOT,altairpearl\/RIOT,adrianghc\/RIOT,kaleb-himes\/RIOT,gautric\/RIOT,l3nko\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,x3ro\/RIOT,basilfx\/RIOT,Yonezawa-T2\/RIOT,authmillenon\/RIOT,TobiasFredersdorf\/RIOT,RIOT-OS\/RIOT,jremmert-phytec-iot\/RIOT,beurdouche\/RIOT,beurdouche\/RIOT,OTAkeys\/RIOT,RBartz\/RIOT,roberthartung\/RIOT,RIOT-OS\/RIOT,RBartz\/RIOT,roberthartung\/RIOT,smlng\/RIOT,FrancescoErmini\/RIOT,rakendrathapa\/RIOT,dkm\/RIOT,basilfx\/RIOT,brettswann\/RIOT,BytesGalore\/RIOT,cladmi\/RIOT,x3ro\/RIOT,avmelnikoff\/RIOT,mtausig\/RIOT,ant9000\/RIOT,jfischer-phytec-iot\/RIOT,l3nko\/RIOT,A-Paul\/RIOT,yogo1212\/RIOT,mtausig\/RIOT,toonst\/RIOT,toonst\/RIOT,shady33\/RIOT,adjih\/RIOT,hamilton-mote\/RIOT-OS,mtausig\/RIOT,neumodisch\/RIOT,d00616\/RIOT,kYc0o\/RIOT,roberthartung\/RIOT,jfischer-phytec-iot\/RIOT,avmelnikoff\/RIOT,rousselk\/RIOT,rajma996\/RIOT,thomaseichinger\/RIOT,hamilton-mote\/RIOT-OS,beurdouche\/RIOT,gebart\/RIOT,neumodisch\/RIOT,BytesGalore\/RIOT,kaleb-himes\/RIOT,Hyungsin\/RIOT-OS,kerneltask\/RIOT,stevenj\/RIOT,brettswann\/RIOT,rajma996\/RIOT,tfar\/RIOT,yogo1212\/RIOT,rajma996\/RIOT,gebart\/RIOT,thomaseichinger\/RIOT,attdona\/RIOT,asanka-code\/RIOT,shady33\/RIOT,stevenj\/RIOT,Hyungsin\/RIOT-OS,LudwigKnuepfer\/RIOT,altairpearl\/RIOT,RubikonAlpha\/RIOT,plushvoxel\/RIOT,MohmadAyman\/RIOT,miri64\/RIOT,dkm\/RIOT,neiljay\/RIOT,toonst\/RIOT,backenklee\/RIOT,jbeyerstedt\/RIOT-OTA-update,authmillenon\/RIOT,cladmi\/RIOT,wentaoshang\/RIOT,dailab\/RIOT,josephnoir\/RIOT,rousselk\/RIOT,zhuoshuguo\/RIOT,RBartz\/RIOT,A-Paul\/RIOT,alignan\/RIOT,immesys\/RiSyn,Yonezawa-T2\/RIOT,roberthartung\/RIOT,rfuentess\/RIOT,Ell-i\/RIOT,adrianghc\/RIOT,MohmadAyman\/RIOT,RubikonAlpha\/RIOT,kerneltask\/RIOT,kb2ma\/RIOT,rousselk\/RIOT,binarylemon\/RIOT,ant9000\/RIOT,roberthartung\/RIOT,wentaoshang\/RIOT,rajma996\/RIOT,malosek\/RIOT,mfrey\/RIOT,jremmert-phytec-iot\/RIOT,malosek\/RIOT,wentaoshang\/RIOT,neumodisch\/RIOT,yogo1212\/RIOT,adjih\/RIOT,jbeyerstedt\/RIOT-OTA-update,basilfx\/RIOT,Hyungsin\/RIOT-OS,RubikonAlpha\/RIOT,kb2ma\/RIOT,kerneltask\/RIOT","old_file":"cpu\/stm32f1\/ldscripts\/stm32f103rb.ld","new_file":"cpu\/stm32f1\/ldscripts\/stm32f103rb.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"1e5a4855397489d19959860d9912559664658a97","subject":"cortexm_common\/ldscript: add common script for rom_offset calculation","message":"cortexm_common\/ldscript: add common script for rom_offset calculation\n","repos":"yogo1212\/RIOT,kYc0o\/RIOT,josephnoir\/RIOT,aeneby\/RIOT,smlng\/RIOT,josephnoir\/RIOT,ant9000\/RIOT,smlng\/RIOT,kaspar030\/RIOT,cladmi\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,miri64\/RIOT,yogo1212\/RIOT,toonst\/RIOT,smlng\/RIOT,kYc0o\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,jasonatran\/RIOT,toonst\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,aeneby\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,toonst\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,basilfx\/RIOT,aeneby\/RIOT,cladmi\/RIOT,rfuentess\/RIOT,cladmi\/RIOT,miri64\/RIOT,x3ro\/RIOT,cladmi\/RIOT,mtausig\/RIOT,toonst\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,x3ro\/RIOT,basilfx\/RIOT,rfuentess\/RIOT,authmillenon\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,mtausig\/RIOT,x3ro\/RIOT,smlng\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,kYc0o\/RIOT,yogo1212\/RIOT,mtausig\/RIOT,josephnoir\/RIOT,aeneby\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,mtausig\/RIOT,OTAkeys\/RIOT,josephnoir\/RIOT,josephnoir\/RIOT,rfuentess\/RIOT,mtausig\/RIOT,RIOT-OS\/RIOT,basilfx\/RIOT,ant9000\/RIOT,basilfx\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,miri64\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,rfuentess\/RIOT,ant9000\/RIOT,toonst\/RIOT,OTAkeys\/RIOT,x3ro\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,OTAkeys\/RIOT,smlng\/RIOT,jasonatran\/RIOT,cladmi\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/cortexm_rom_offset.ld","new_file":"cpu\/cortexm_common\/ldscripts\/cortexm_rom_offset.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/toonst\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"1a52c80bf4c0492c2eab3c2a9187b5a7dc8a8c18","subject":"cpu\/cortexm_common\/ldscripts: add multislot variables","message":"cpu\/cortexm_common\/ldscripts: add multislot variables\n","repos":"neumodisch\/RIOT,kYc0o\/RIOT,hamilton-mote\/RIOT-OS,neiljay\/RIOT,gebart\/RIOT,mtausig\/RIOT,neumodisch\/RIOT,x3ro\/RIOT,toonst\/RIOT,mtausig\/RIOT,ks156\/RIOT,OTAkeys\/RIOT,avmelnikoff\/RIOT,rfuentess\/RIOT,beurdouche\/RIOT,adrianghc\/RIOT,immesys\/RiSyn,ant9000\/RIOT,OlegHahm\/RIOT,cladmi\/RIOT,basilfx\/RIOT,jfischer-phytec-iot\/RIOT,Josar\/RIOT,jfischer-phytec-iot\/RIOT,biboc\/RIOT,aeneby\/RIOT,neiljay\/RIOT,basilfx\/RIOT,A-Paul\/RIOT,lazytech-org\/RIOT,basilfx\/RIOT,neumodisch\/RIOT,BytesGalore\/RIOT,mtausig\/RIOT,OlegHahm\/RIOT,thomaseichinger\/RIOT,josephnoir\/RIOT,neiljay\/RIOT,A-Paul\/RIOT,mtausig\/RIOT,thomaseichinger\/RIOT,neumodisch\/RIOT,RIOT-OS\/RIOT,LudwigKnuepfer\/RIOT,plushvoxel\/RIOT,Josar\/RIOT,adrianghc\/RIOT,yogo1212\/RIOT,Josar\/RIOT,neumodisch\/RIOT,OTAkeys\/RIOT,A-Paul\/RIOT,Josar\/RIOT,OlegHahm\/RIOT,kerneltask\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,kYc0o\/RIOT,hamilton-mote\/RIOT-OS,josephnoir\/RIOT,smlng\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,toonst\/RIOT,gebart\/RIOT,kerneltask\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,josephnoir\/RIOT,kbumsik\/RIOT,x3ro\/RIOT,mfrey\/RIOT,roberthartung\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,cladmi\/RIOT,thomaseichinger\/RIOT,cladmi\/RIOT,adjih\/RIOT,immesys\/RiSyn,LudwigOrtmann\/RIOT,plushvoxel\/RIOT,toonst\/RIOT,adjih\/RIOT,kaspar030\/RIOT,A-Paul\/RIOT,biboc\/RIOT,lazytech-org\/RIOT,mfrey\/RIOT,ks156\/RIOT,kbumsik\/RIOT,lazytech-org\/RIOT,toonst\/RIOT,smlng\/RIOT,immesys\/RiSyn,neiljay\/RIOT,BytesGalore\/RIOT,LudwigOrtmann\/RIOT,OTAkeys\/RIOT,immesys\/RiSyn,ks156\/RIOT,smlng\/RIOT,aeneby\/RIOT,BytesGalore\/RIOT,aeneby\/RIOT,immesys\/RiSyn,basilfx\/RIOT,rfuentess\/RIOT,ks156\/RIOT,LudwigKnuepfer\/RIOT,LudwigOrtmann\/RIOT,cladmi\/RIOT,kerneltask\/RIOT,jasonatran\/RIOT,thomaseichinger\/RIOT,roberthartung\/RIOT,biboc\/RIOT,roberthartung\/RIOT,OlegHahm\/RIOT,beurdouche\/RIOT,authmillenon\/RIOT,biboc\/RIOT,yogo1212\/RIOT,jasonatran\/RIOT,hamilton-mote\/RIOT-OS,aeneby\/RIOT,ks156\/RIOT,A-Paul\/RIOT,rfuentess\/RIOT,RIOT-OS\/RIOT,biboc\/RIOT,ant9000\/RIOT,plushvoxel\/RIOT,gebart\/RIOT,beurdouche\/RIOT,gebart\/RIOT,jasonatran\/RIOT,yogo1212\/RIOT,avmelnikoff\/RIOT,hamilton-mote\/RIOT-OS,miri64\/RIOT,miri64\/RIOT,LudwigKnuepfer\/RIOT,kbumsik\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,jfischer-phytec-iot\/RIOT,kaspar030\/RIOT,adjih\/RIOT,miri64\/RIOT,avmelnikoff\/RIOT,rfuentess\/RIOT,LudwigKnuepfer\/RIOT,yogo1212\/RIOT,smlng\/RIOT,miri64\/RIOT,jfischer-phytec-iot\/RIOT,LudwigKnuepfer\/RIOT,plushvoxel\/RIOT,kerneltask\/RIOT,OTAkeys\/RIOT,LudwigOrtmann\/RIOT,LudwigOrtmann\/RIOT,x3ro\/RIOT,roberthartung\/RIOT,immesys\/RiSyn,josephnoir\/RIOT,roberthartung\/RIOT,adrianghc\/RIOT,Josar\/RIOT,avmelnikoff\/RIOT,mfrey\/RIOT,neiljay\/RIOT,beurdouche\/RIOT,toonst\/RIOT,cladmi\/RIOT,lazytech-org\/RIOT,adjih\/RIOT,BytesGalore\/RIOT,kYc0o\/RIOT,jfischer-phytec-iot\/RIOT,hamilton-mote\/RIOT-OS,thomaseichinger\/RIOT,kaspar030\/RIOT,BytesGalore\/RIOT,beurdouche\/RIOT,adrianghc\/RIOT,rfuentess\/RIOT,kbumsik\/RIOT,josephnoir\/RIOT,kbumsik\/RIOT,miri64\/RIOT,adjih\/RIOT,kYc0o\/RIOT,yogo1212\/RIOT,jasonatran\/RIOT,mtausig\/RIOT,aeneby\/RIOT,jasonatran\/RIOT,kerneltask\/RIOT,ant9000\/RIOT,basilfx\/RIOT,adrianghc\/RIOT,kaspar030\/RIOT,lazytech-org\/RIOT,kaspar030\/RIOT,LudwigOrtmann\/RIOT,mfrey\/RIOT,gebart\/RIOT,smlng\/RIOT,plushvoxel\/RIOT,RIOT-OS\/RIOT,ant9000\/RIOT,mfrey\/RIOT,x3ro\/RIOT,RIOT-OS\/RIOT,neumodisch\/RIOT,avmelnikoff\/RIOT,authmillenon\/RIOT","old_file":"cpu\/cortexm_common\/ldscripts\/multislot.ld","new_file":"cpu\/cortexm_common\/ldscripts\/multislot.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"271465cda6d9b1d85b7e1d9c5c5f231d558dbb7b","subject":"new file","message":"new file\n","repos":"hirakuni45\/RL78,hirakuni45\/RL78,hirakuni45\/RL78","old_file":"L1C\/R5F110ME.ld","new_file":"L1C\/R5F110ME.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/hirakuni45\/RL78.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"6e3136b4d49326449263b44d20db1b3a847360b4","subject":"Linker file for the kernel","message":"Linker file for the kernel\n","repos":"mikehabibi\/osdev,mikehabibi\/osdev","old_file":"src\/kernel.ld","new_file":"src\/kernel.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mikehabibi\/osdev.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"b95af21ca48b51da028cc7f18bb27dc5228acc6f","subject":"asm: link user.ld -> gpio.ld","message":"asm: link user.ld -> gpio.ld\n","repos":"bwitherspoon\/core,bwitherspoon\/core","old_file":"src\/gpio.ld","new_file":"src\/gpio.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/bwitherspoon\/core.git\/': The requested URL returned error: 403\n","license":"isc","lang":"Linker Script"}
{"commit":"d9e0eab8fef1a008941d1e8a5ea5d4b7857e8cb7","subject":"Force a bit more stuff into CCM ram","message":"Force a bit more stuff into CCM ram\n","repos":"jessicakam\/tenshi,tobinsarah\/tenshi,hozhu123\/tenshi,pioneers\/tenshi,cduck\/tenshi,JaronArmiger\/tenshi,JaronArmiger\/tenshi,abhishyantkhare\/tenshi,chuen0630\/tenshi,jessicakam\/tenshi,tobinsarah\/tenshi,hozhu123\/tenshi,SamboyKirk\/tenshi,abhishyantkhare\/tenshi,abhishyantkhare\/tenshi,jessicakam\/tenshi,hozhu123\/tenshi,tobinsarah\/tenshi,jarzofjam\/tenshi,cduck\/tenshi,abhishyantkhare\/tenshi,hozhu123\/tenshi,jarzofjam\/tenshi,cduck\/tenshi,jessicakam\/tenshi,hozhu123\/tenshi,JaronArmiger\/tenshi,chuen0630\/tenshi,jessicakam\/tenshi,JaronArmiger\/tenshi,SamboyKirk\/tenshi,hozhu123\/tenshi,abhishyantkhare\/tenshi,abhishyantkhare\/tenshi,pioneers\/tenshi,SamboyKirk\/tenshi,tobinsarah\/tenshi,jessicakam\/tenshi,cduck\/tenshi,hozhu123\/tenshi,JaronArmiger\/tenshi,pioneers\/tenshi,JaronArmiger\/tenshi,jarzofjam\/tenshi,tobinsarah\/tenshi,SamboyKirk\/tenshi,SamboyKirk\/tenshi,chuen0630\/tenshi,jarzofjam\/tenshi,tobinsarah\/tenshi,jarzofjam\/tenshi,pioneers\/tenshi,abhishyantkhare\/tenshi,pioneers\/tenshi,pioneers\/tenshi,tobinsarah\/tenshi,cduck\/tenshi,jarzofjam\/tenshi,chuen0630\/tenshi,SamboyKirk\/tenshi,chuen0630\/tenshi,JaronArmiger\/tenshi,jessicakam\/tenshi,chuen0630\/tenshi,cduck\/tenshi,chuen0630\/tenshi,SamboyKirk\/tenshi,pioneers\/tenshi,cduck\/tenshi,jarzofjam\/tenshi","old_file":"controller\/ldscript.ld","new_file":"controller\/ldscript.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/abhishyantkhare\/tenshi.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"faa460ae883d685f238a08de888a49360707cd3d","subject":"nrf5: Adding new linker script for nrf52840.","message":"nrf5: Adding new linker script for nrf52840.\n","repos":"tralamazza\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,tralamazza\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,tralamazza\/micropython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/circuitpython,adafruit\/micropython","old_file":"nrf5\/boards\/nrf52840_aa.ld","new_file":"nrf5\/boards\/nrf52840_aa.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/tralamazza\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"9a4d1815838acf099ed8f113920305cfedbaed91","subject":"added linker script","message":"added linker script\n","repos":"openmv\/openmv,openmv\/openmv,SmartArduino\/openmv,iabdalkader\/openmv,iabdalkader\/openmv,kwagyeman\/openmv,iabdalkader\/openmv,tianzhihen\/openmv,tianzhihen\/openmv,tianzhihen\/openmv,tianzhihen\/openmv,openmv\/openmv,kwagyeman\/openmv,SmartArduino\/openmv,kwagyeman\/openmv,kwagyeman\/openmv,SmartArduino\/openmv,iabdalkader\/openmv,openmv\/openmv,SmartArduino\/openmv","old_file":"stm32_flash.ld","new_file":"stm32_flash.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kwagyeman\/openmv.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"65aebef596418fca6d15a091ab2bf9924d4f6130","subject":"esp32c3: added 2nd bootloader project linker file","message":"esp32c3: added 2nd bootloader project linker file\n","repos":"espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/ld\/esp32c3\/bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/ld\/esp32c3\/bootloader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/espressif\/esp-idf.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"585f7d54f76579afadd4e5eaf2d0360c8e244e1d","subject":"cpu: stm32f2: ldscripts: change flash map.","message":"cpu: stm32f2: ldscripts: change flash map.\n","repos":"centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT","old_file":"cpu\/stm32f2\/ldscripts\/stm32f205re_MMA200.ld","new_file":"cpu\/stm32f2\/ldscripts\/stm32f205re_MMA200.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/centurysys\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"b94fb5be45275ad3e799eb0c0e2ffcabe96b3952","subject":"Add linker","message":"Add linker\n","repos":"ReturnInfinity\/Alloy,ReturnInfinity\/Alloy","old_file":"loader.ld","new_file":"loader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ReturnInfinity\/Alloy.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"10d0708c8942c44f50c40d075ebe72a4ddaf8ba2","subject":"Create linker.ld","message":"Create linker.ld\n\nCopied sample code from OSDev","repos":"NETponents\/HiveOS,NETponents\/HiveOS","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/NETponents\/HiveOS.git\/': The requested URL returned error: 403\n","license":"agpl-3.0","lang":"Linker Script"}
{"commit":"bc9fe3f110e87cc7084f635da548abbd361ee320","subject":"Add linker script for running from boot loader.","message":"Add linker script for running from boot loader.\n","repos":"IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,wes3\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,IMGJulian\/incubator-mynewt-core,wes3\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,IMGJulian\/incubator-mynewt-core,mlaz\/mynewt-core","old_file":"hw\/bsp\/olimex_stm32-e407_devboard\/run_from_loader.ld","new_file":"hw\/bsp\/olimex_stm32-e407_devboard\/run_from_loader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mlaz\/mynewt-core.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e3ee010ef3a48f2bd538a0518ae0647f306d8a45","subject":"cleaned up linker script","message":"cleaned up linker script\n","repos":"DavidDiPaola\/DirtOS,DavidDiPaola\/DirtOS,DavidDiPaola\/dirt,DavidDiPaola\/dirt,DavidDiPaola\/dirt","old_file":"layout.lds","new_file":"layout.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/DavidDiPaola\/DirtOS.git\/': The requested URL returned error: 403\n","license":"cc0-1.0","lang":"Linker Script"}
{"commit":"d6ca374515905650f9ba4f7efab38b9951921d8a","subject":"[linker] add file for stm32f0 with 128k flash and 16k ram","message":"[linker] add file for stm32f0 with 128k flash and 16k ram\n","repos":"dergraaf\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc","old_file":"src\/xpcc\/architecture\/platform\/linker\/stm32\/stm32f0xx_b.ld","new_file":"src\/xpcc\/architecture\/platform\/linker\/stm32\/stm32f0xx_b.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/dergraaf\/xpcc.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"814934d78df7d3ab33875ca44e0e7905400d60c9","subject":"Add missing linker script.","message":"Add missing linker script.\n","repos":"anchovieshat\/cathode-old,anchovieshat\/cathode-old,anchovieshat\/cathode-old","old_file":"kernel\/kernel.ld","new_file":"kernel\/kernel.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/anchovieshat\/cathode-old.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"994dea3de3eeb5f16519d0199aa43cbb2f43a234","subject":"forgot the flash.4m1m linker script?","message":"forgot the flash.4m1m linker script?\n","repos":"martinayotte\/ESP8266-Arduino,chrisfraser\/Arduino,quertenmont\/Arduino,sticilface\/Arduino,Cloudino\/Arduino,CanTireInnovations\/Arduino,lrmoreno007\/Arduino,Juppit\/Arduino,jes\/Arduino,me-no-dev\/Arduino,Lan-Hekary\/Arduino,me-no-dev\/Arduino,lrmoreno007\/Arduino,chrisfraser\/Arduino,Adam5Wu\/Arduino,hallard\/Arduino,gguuss\/Arduino,sticilface\/Arduino,me-no-dev\/Arduino,CanTireInnovations\/Arduino,edog1973\/Arduino,NullMedia\/Arduino,CanTireInnovations\/Arduino,hallard\/Arduino,CanTireInnovations\/Arduino,esp8266\/Arduino,Cloudino\/Arduino,wemos\/Arduino,Cloudino\/Arduino,Lan-Hekary\/Arduino,toastedcode\/esp8266-Arduino,Juppit\/Arduino,wemos\/Arduino,wemos\/Arduino,Links2004\/Arduino,Juppit\/Arduino,lrmoreno007\/Arduino,KaloNK\/Arduino,sticilface\/Arduino,Cloudino\/Cloudino-Arduino-IDE,NullMedia\/Arduino,chrisfraser\/Arduino,esp8266\/Arduino,Links2004\/Arduino,gguuss\/Arduino,martinayotte\/ESP8266-Arduino,Cloudino\/Cloudino-Arduino-IDE,lrmoreno007\/Arduino,lrmoreno007\/Arduino,gguuss\/Arduino,esp8266\/Arduino,Juppit\/Arduino,Cloudino\/Cloudino-Arduino-IDE,CanTireInnovations\/Arduino,Cloudino\/Arduino,NextDevBoard\/Arduino,NextDevBoard\/Arduino,jes\/Arduino,martinayotte\/ESP8266-Arduino,toastedcode\/esp8266-Arduino,Adam5Wu\/Arduino,NextDevBoard\/Arduino,Links2004\/Arduino,quertenmont\/Arduino,jes\/Arduino,chrisfraser\/Arduino,NullMedia\/Arduino,KaloNK\/Arduino,esp8266\/Arduino,toastedcode\/esp8266-Arduino,hallard\/Arduino,Links2004\/Arduino,Adam5Wu\/Arduino,Juppit\/Arduino,NextDevBoard\/Arduino,jes\/Arduino,martinayotte\/ESP8266-Arduino,Cloudino\/Cloudino-Arduino-IDE,sticilface\/Arduino,hallard\/Arduino,Cloudino\/Arduino,wemos\/Arduino,Cloudino\/Cloudino-Arduino-IDE,CanTireInnovations\/Arduino,Cloudino\/Arduino,chrisfraser\/Arduino,Links2004\/Arduino,Adam5Wu\/Arduino,me-no-dev\/Arduino,hallard\/Arduino,KaloNK\/Arduino,Cloudino\/Cloudino-Arduino-IDE,edog1973\/Arduino,esp8266\/Arduino,Lan-Hekary\/Arduino,KaloNK\/Arduino,sticilface\/Arduino,Cloudino\/Cloudino-Arduino-IDE,Adam5Wu\/Arduino,Lan-Hekary\/Arduino,gguuss\/Arduino,quertenmont\/Arduino,Cloudino\/Arduino,me-no-dev\/Arduino,wemos\/Arduino,quertenmont\/Arduino,martinayotte\/ESP8266-Arduino,NullMedia\/Arduino,CanTireInnovations\/Arduino,toastedcode\/esp8266-Arduino,jes\/Arduino,NullMedia\/Arduino,quertenmont\/Arduino,edog1973\/Arduino,NextDevBoard\/Arduino,toastedcode\/esp8266-Arduino,KaloNK\/Arduino,edog1973\/Arduino,gguuss\/Arduino,Lan-Hekary\/Arduino,edog1973\/Arduino","old_file":"tools\/sdk\/ld\/eagle.flash.4m1m.ld","new_file":"tools\/sdk\/ld\/eagle.flash.4m1m.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Adam5Wu\/Arduino.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"6721a71feb162541895451ac00155c8c23605361","subject":"Should put things in a right-er place now.","message":"Should put things in a right-er place now.\n","repos":"Gen-OS\/bbb-proof-of-concept,Gen-OS\/bbb-proof-of-concept,Gen-OS\/bbb-proof-of-concept","old_file":"src\/cpu\/am335x\/linker.ld","new_file":"src\/cpu\/am335x\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Gen-OS\/bbb-proof-of-concept.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"085682c76b74a9b7eb57075557b3a9575962c2c7","subject":"\tnew file:   bsp\/ls1cdev\/ls1b_ram.lds","message":"\tnew file:   bsp\/ls1cdev\/ls1b_ram.lds\n","repos":"FlyLu\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,geniusgogo\/rt-thread,zhaojuntao\/rt-thread,AubrCool\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,yongli3\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,igou\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,armink\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,zhaojuntao\/rt-thread,igou\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,FlyLu\/rt-thread,weety\/rt-thread,yongli3\/rt-thread,igou\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,wolfgangz2013\/rt-thread,wolfgangz2013\/rt-thread,ArdaFu\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,igou\/rt-thread,weiyuliang\/rt-thread,weiyuliang\/rt-thread,hezlog\/rt-thread,FlyLu\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,igou\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,geniusgogo\/rt-thread,RT-Thread\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,yongli3\/rt-thread,gbcwbz\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,igou\/rt-thread,yongli3\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,wolfgangz2013\/rt-thread,wolfgangz2013\/rt-thread,nongxiaoming\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread","old_file":"bsp\/ls1cdev\/ls1b_ram.lds","new_file":"bsp\/ls1cdev\/ls1b_ram.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/igou\/rt-thread.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4b168dfe179f640499680e6cfdccf57f2fa82732","subject":"Add config.ld for documentation, only documenting some libraries right now","message":"Add config.ld for documentation, only documenting some libraries right now\n","repos":"Quenty\/NevermoreEngine,Quenty\/NevermoreEngine,Quenty\/NevermoreEngine","old_file":"Doc\/config.ld","new_file":"Doc\/config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Quenty\/NevermoreEngine.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"00721f87b55e2ec820394e5558af26f9a42ddade","subject":"Adds memory map for MX530.","message":"Adds memory map for MX530.\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/microchip-pic32mx-generic\/memory_map.mx530.ld","new_file":"boards\/microchip-pic32mx-generic\/memory_map.mx530.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/bakerstu\/openmrn.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"4f259925c2c92bc1db936075bc7cefdad64010e2","subject":"stm32: add missing ld script","message":"stm32: add missing ld script\n\nSigned-off-by: Fabien Parent <2a93cde040adee823a667eed2882d05f12a84573@gmail.com>\n","repos":"mtitinger\/phabos,mtitinger\/phabos","old_file":"arch\/arm\/mach-stm32\/stm32f417xx.ld","new_file":"arch\/arm\/mach-stm32\/stm32f417xx.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mtitinger\/phabos.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"7f405236a3355467a37cb16762939d6362352089","subject":"nrf\/boards: Add linker script for nrf52840 Open Bootloader 1.2.0.","message":"nrf\/boards: Add linker script for nrf52840 Open Bootloader 1.2.0.\n","repos":"adafruit\/circuitpython,henriknelson\/micropython,henriknelson\/micropython,bvernoux\/micropython,bvernoux\/micropython,bvernoux\/micropython,henriknelson\/micropython,adafruit\/circuitpython,henriknelson\/micropython,bvernoux\/micropython,adafruit\/circuitpython,henriknelson\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,bvernoux\/micropython,adafruit\/circuitpython","old_file":"ports\/nrf\/boards\/nrf52840_open_bootloader_1.2.x.ld","new_file":"ports\/nrf\/boards\/nrf52840_open_bootloader_1.2.x.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/henriknelson\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"ac067609488004d1513c14f7a3a81ade0b34b9dd","subject":"forgot the flash.4m1m linker script?","message":"forgot the flash.4m1m linker script?\n","repos":"leftbrainstrain\/Arduino-ESP8266,ssvs111\/Arduino,sanyaade-iot\/Arduino-1,sanyaade-iot\/Arduino-1,leftbrainstrain\/Arduino-ESP8266,ssvs111\/Arduino,paulmand3l\/Arduino,smily77\/Arduino,myrtleTree33\/Arduino,smily77\/Arduino,eeijcea\/Arduino-1,gonium\/Arduino,mangelajo\/Arduino,spapadim\/Arduino,mateuszdw\/Arduino,mangelajo\/Arduino,leftbrainstrain\/Arduino-ESP8266,drpjk\/Arduino,mangelajo\/Arduino,myrtleTree33\/Arduino,EmuxEvans\/Arduino,spapadim\/Arduino,weera00\/Arduino,sanyaade-iot\/Arduino-1,paulmand3l\/Arduino,ogahara\/Arduino,zenmanenergy\/Arduino,drpjk\/Arduino,mateuszdw\/Arduino,spapadim\/Arduino,ssvs111\/Arduino,EmuxEvans\/Arduino,ssvs111\/Arduino,paulmand3l\/Arduino,ssvs111\/Arduino,gonium\/Arduino,leftbrainstrain\/Arduino-ESP8266,myrtleTree33\/Arduino,eeijcea\/Arduino-1,eeijcea\/Arduino-1,spapadim\/Arduino,leftbrainstrain\/Arduino-ESP8266,drpjk\/Arduino,mangelajo\/Arduino,paulmand3l\/Arduino,EmuxEvans\/Arduino,eeijcea\/Arduino-1,EmuxEvans\/Arduino,ogahara\/Arduino,drpjk\/Arduino,weera00\/Arduino,mateuszdw\/Arduino,paulmand3l\/Arduino,myrtleTree33\/Arduino,smily77\/Arduino,ogahara\/Arduino,mateuszdw\/Arduino,sanyaade-iot\/Arduino-1,zenmanenergy\/Arduino,mateuszdw\/Arduino,zenmanenergy\/Arduino,myrtleTree33\/Arduino,zenmanenergy\/Arduino,weera00\/Arduino,leftbrainstrain\/Arduino-ESP8266,weera00\/Arduino,spapadim\/Arduino,sanyaade-iot\/Arduino-1,gonium\/Arduino,drpjk\/Arduino,zenmanenergy\/Arduino,spapadim\/Arduino,weera00\/Arduino,EmuxEvans\/Arduino,weera00\/Arduino,leftbrainstrain\/Arduino-ESP8266,myrtleTree33\/Arduino,ssvs111\/Arduino,drpjk\/Arduino,myrtleTree33\/Arduino,sanyaade-iot\/Arduino-1,mangelajo\/Arduino,gonium\/Arduino,mateuszdw\/Arduino,ogahara\/Arduino,mateuszdw\/Arduino,zenmanenergy\/Arduino,spapadim\/Arduino,EmuxEvans\/Arduino,ssvs111\/Arduino,eeijcea\/Arduino-1,gonium\/Arduino,drpjk\/Arduino,smily77\/Arduino,paulmand3l\/Arduino,weera00\/Arduino,smily77\/Arduino,smily77\/Arduino,gonium\/Arduino,mangelajo\/Arduino,gonium\/Arduino,sanyaade-iot\/Arduino-1,eeijcea\/Arduino-1,ogahara\/Arduino,ogahara\/Arduino,paulmand3l\/Arduino,ogahara\/Arduino,zenmanenergy\/Arduino,EmuxEvans\/Arduino,smily77\/Arduino,eeijcea\/Arduino-1,mangelajo\/Arduino","old_file":"hardware\/esp8266com\/esp8266\/tools\/sdk\/ld\/eagle.flash.4m1m.ld","new_file":"hardware\/esp8266com\/esp8266\/tools\/sdk\/ld\/eagle.flash.4m1m.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mateuszdw\/Arduino.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"c44632238238517afcd27712f7bf37e202cdf656","subject":"hw\/mcu\/stm: Add missing ld file for nucleo-l073rz BSP","message":"hw\/mcu\/stm: Add missing ld file for nucleo-l073rz BSP\n\nFile stm32l073.ld should have been added when BSP for\nnucleo-l073rz was committed by 'Add nucleo-l073rz BSP'\n","repos":"mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core","old_file":"hw\/mcu\/stm\/stm32l0xx\/stm32l073.ld","new_file":"hw\/mcu\/stm\/stm32l0xx\/stm32l073.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mlaz\/mynewt-core.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b230e4de89a6abca18b3c45814e1343da0a98bcd","subject":".library_info put to address (instead of load address)","message":".library_info put to address (instead of load address)\n\n    The relevant FIXME comment included (this is a problem in the nRF5 SDK\n  and this \"fix\" is just a workaround).\n","repos":"PulseOn\/Embedded_Build_System","old_file":"library_info.ld","new_file":"library_info.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/PulseOn\/Embedded_Build_System.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"128410bc1ea59835f713e3e735b921ca096ccb29","subject":"fix memory for central role","message":"fix memory for central role\n","repos":"muet\/Espruino,mjdietzx\/Espruino,mjdietzx\/Espruino,mjdietzx\/Espruino,muet\/Espruino,wilberforce\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino,nkolban\/Espruino,mjdietzx\/Espruino,luetgendorf\/Espruino,redbear\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,muet\/Espruino,nkolban\/Espruino,lancernet\/Espruino,muet\/Espruino,mjdietzx\/Espruino,nkolban\/Espruino,nkolban\/Espruino,tve\/Espruino,mjdietzx\/Espruino,muet\/Espruino,wilberforce\/Espruino,tve\/Espruino,luetgendorf\/Espruino,tve\/Espruino,lancernet\/Espruino,lancernet\/Espruino,redbear\/Espruino,wilberforce\/Espruino,tve\/Espruino,nkolban\/Espruino,lancernet\/Espruino,redbear\/Espruino,nkolban\/Espruino,muet\/Espruino,redbear\/Espruino,muet\/Espruino,redbear\/Espruino,nkolban\/Espruino,wilberforce\/Espruino,redbear\/Espruino,redbear\/Espruino,mjdietzx\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,tve\/Espruino,tve\/Espruino,lancernet\/Espruino,tve\/Espruino,luetgendorf\/Espruino,lancernet\/Espruino,wilberforce\/Espruino,luetgendorf\/Espruino","old_file":"targetlibs\/nrf5x\/nrf5x_linkers\/linker_nrf52_ble_espruino.ld","new_file":"targetlibs\/nrf5x\/nrf5x_linkers\/linker_nrf52_ble_espruino.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/muet\/Espruino.git\/': The requested URL returned error: 403\n","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"a5516ef706abe5ad6d118e734f23ae81e1aa8554","subject":"nRF52 xxAB variant 256KB FLASH, 32KB RAM","message":"nRF52 xxAB variant 256KB FLASH, 32KB RAM\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_xxab.ld","new_file":"ARM\/Nordic\/nRF52\/src\/gcc_nrf52_xxab.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/I-SYST\/EHAL.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"d0aedf0f959238a8b9b68c12a231b69c847a2522","subject":"cpu\/cc26xx_cc13xx: add custom ld script","message":"cpu\/cc26xx_cc13xx: add custom ld script\n\nThis add a custom ldscript for cc26xx_cc13xx CPUs,\nwhich allows linking CCFG configuration, usage of GPRAM,\netc.\n\nSigned-off-by: Jean Pierre Dudey <b1c1d8736f20db3fb6c1c66bb1455ed43909f0d8@jeandudey.tech>\n","repos":"RIOT-OS\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,miri64\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,OTAkeys\/RIOT,miri64\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,OlegHahm\/RIOT,kYc0o\/RIOT,ant9000\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,kaspar030\/RIOT,ant9000\/RIOT,miri64\/RIOT,authmillenon\/RIOT,authmillenon\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,OlegHahm\/RIOT,jasonatran\/RIOT,authmillenon\/RIOT,miri64\/RIOT,OTAkeys\/RIOT,jasonatran\/RIOT,OlegHahm\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,kYc0o\/RIOT,kaspar030\/RIOT,RIOT-OS\/RIOT,kaspar030\/RIOT,miri64\/RIOT","old_file":"cpu\/cc26xx_cc13xx\/ldscripts\/cc26xx_cc13xx.ld","new_file":"cpu\/cc26xx_cc13xx\/ldscripts\/cc26xx_cc13xx.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kaspar030\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"4d36fd94d00c805401eeaacd1cadea664e5a44e9","subject":"Add: linker script (RX62N7)","message":"Add: linker script (RX62N7)\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX62x\/R5F562N7.ld","new_file":"RX62x\/R5F562N7.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/hirakuni45\/RX.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"55d10d1663f1dfa642f9555e5526e116f0654593","subject":"Linking the kernel","message":"Linking the kernel\n","repos":"GalacticOne\/StarOS","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/GalacticOne\/StarOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"1445fe579b83c88c7579264a28cd11f03a27ffc1","subject":"Omitted linker script added","message":"Omitted linker script added\n","repos":"akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix,akoskovacs\/Akosix","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/akoskovacs\/Akosix.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"18555e2b30b398550aa874d512692b0a202e4ae9","subject":"Added cart.ld file","message":"Added cart.ld file\n","repos":"jesusatc\/libgba,jesusatc\/libgba","old_file":"cart.ld","new_file":"cart.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/jesusatc\/libgba.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"6e5a22080e155dae7d6c85701d53b93a4f338be4","subject":"Add .ARM.exidx section (#521)","message":"Add .ARM.exidx section (#521)\n\n","repos":"vaas-krish\/openthread,openthread\/openthread,fbsder\/openthread,fbsder\/openthread,lanyuwen\/openthread,srickardti\/openthread,vaas-krish\/openthread,georgecpr\/openthread,openthread\/openthread,nibanks\/openthread,vaas-krish\/openthread,pvanhorn\/openthread,jwhui\/openthread,xiaom-GitHub\/openthread,xiaom-GitHub\/openthread,LeZhang2016\/openthread,vaas-krish\/openthread,srickardti\/openthread,aeliot\/openthread,jjlee3\/openthread,LeZhang2016\/openthread,jjlee9\/openthread,srickardti\/openthread,aeliot\/openthread,pvanhorn\/openthread,georgecpr\/openthread,jjlee3\/openthread,erja-gp\/openthread,pvanhorn\/openthread,lanyuwen\/openthread,chshu\/openthread,nibanks\/openthread,nibanks\/openthread,gandreello\/openthread,bukepo\/openthread,georgecpr\/openthread,JakubBrachTieto\/openthread,jwhui\/openthread,pvanhorn\/openthread,xiaom-GitHub\/openthread,Zolertia\/openthread,Zolertia\/openthread,jjlee9\/openthread,pvanhorn\/openthread,turon\/openthread,chshu\/openthread,gandreello\/openthread,JakubBrachTieto\/openthread,LeZhang2016\/openthread,mszczodrak\/openthread,jjlee9\/openthread,abtink\/openthread,xiaom-GitHub\/openthread,jwhui\/openthread,Zolertia\/openthread,fbsder\/openthread,georgecpr\/openthread,xiaom-GitHub\/openthread,lanyuwen\/openthread,lanyuwen\/openthread,bukepo\/openthread,bukepo\/openthread,JakubBrachTieto\/openthread,jwhui\/openthread,mszczodrak\/openthread,jjlee3\/openthread,GiedriusM\/openthread,GiedriusM\/openthread,lanyuwen\/openthread,erja-gp\/openthread,LeZhang2016\/openthread,chshu\/openthread,gandreello\/openthread,nibanks\/openthread,librasungirl\/openthread,abtink\/openthread,GiedriusM\/openthread,erja-gp\/openthread,nibanks\/openthread,jjlee9\/openthread,jjlee3\/openthread,chshu\/openthread,aeliot\/openthread,librasungirl\/openthread,aeliot\/openthread,abtink\/openthread,jjlee9\/openthread,mszczodrak\/openthread,mszczodrak\/openthread,JakubBrachTieto\/openthread,JakubBrachTieto\/openthread,jjlee3\/openthread,vaas-krish\/openthread,GiedriusM\/openthread,turon\/openthread,turon\/openthread,vaas-krish\/openthread,mszczodrak\/openthread,erja-gp\/openthread,GiedriusM\/openthread,erja-gp\/openthread,Zolertia\/openthread,jjlee9\/openthread,georgecpr\/openthread,librasungirl\/openthread,LeZhang2016\/openthread,abtink\/openthread,turon\/openthread,mszczodrak\/openthread,JakubBrachTieto\/openthread,srickardti\/openthread,aeliot\/openthread,chshu\/openthread,openthread\/openthread,Zolertia\/openthread,bukepo\/openthread,nibanks\/openthread,lanyuwen\/openthread,fbsder\/openthread,pvanhorn\/openthread,georgecpr\/openthread,erja-gp\/openthread,xiaom-GitHub\/openthread,gandreello\/openthread,chshu\/openthread,gandreello\/openthread,fbsder\/openthread,openthread\/openthread,LeZhang2016\/openthread,fbsder\/openthread,librasungirl\/openthread,aeliot\/openthread,gandreello\/openthread","old_file":"examples\/platforms\/cc2538\/cc2538.ld","new_file":"examples\/platforms\/cc2538\/cc2538.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/jwhui\/openthread.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"d5f71eb0c633a039cdd6b70dc93c44641b5b11ca","subject":"Simplified linker script handling of libc.","message":"Simplified linker script handling of libc.\n\nHaving ascertained that the SDK itself has no (zero, zilch, nada) dependencies\non the standard C library, the NodeMCU linker script now puts any and all\nlibc functions into irom, rather than carefully picking the ones that\nwere used by NodeMCU some months ago. This should help keep iram free for\nthe things which really need to be in iram (such as ISRs).\n","repos":"mikeller\/nodemcu-firmware,TerryE\/nodemcu-firmware,eku\/nodemcu-firmware,nodemcu\/nodemcu-firmware,mikeller\/nodemcu-firmware,dnc40085\/nodemcu-firmware,nodemcu\/nodemcu-firmware,vsky279\/nodemcu-firmware,bogvak\/nodemcu-firmware,FrankX0\/nodemcu-firmware,TerryE\/nodemcu-firmware,jmattsson\/nodemcu-firmware,jmattsson\/nodemcu-firmware,karrots\/nodemcu-firmware,devsaurus\/nodemcu-firmware,mikeller\/nodemcu-firmware,FelixPe\/nodemcu-firmware,karrots\/nodemcu-firmware,zhujunsan\/nodemcu-firmware,zhujunsan\/nodemcu-firmware,TerryE\/nodemcu-firmware,dnc40085\/nodemcu-firmware,devsaurus\/nodemcu-firmware,TerryE\/nodemcu-firmware,fetchbot\/nodemcu-firmware,devsaurus\/nodemcu-firmware,djphoenix\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,vsky279\/nodemcu-firmware,vsky279\/nodemcu-firmware,vowstar\/nodemcu-firmware,petrkr\/nodemcu-firmware,devsaurus\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,nwf\/nodemcu-firmware,vsky279\/nodemcu-firmware,bogvak\/nodemcu-firmware,jmattsson\/nodemcu-firmware,fetchbot\/nodemcu-firmware,petrkr\/nodemcu-firmware,oyooyo\/nodemcu-firmware,jmattsson\/nodemcu-firmware,devsaurus\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,raburton\/nodemcu-firmware,nwf\/nodemcu-firmware,eku\/nodemcu-firmware,vsky279\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,karrots\/nodemcu-firmware,eku\/nodemcu-firmware,oyooyo\/nodemcu-firmware,nwf\/nodemcu-firmware,dnc40085\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,nodemcu\/nodemcu-firmware,FelixPe\/nodemcu-firmware,FrankX0\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,zhujunsan\/nodemcu-firmware,petrkr\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,dnc40085\/nodemcu-firmware,eku\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,oyooyo\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,petrkr\/nodemcu-firmware,djphoenix\/nodemcu-firmware,nwf\/nodemcu-firmware,dnc40085\/nodemcu-firmware,marcelstoer\/nodemcu-firmware,petrkr\/nodemcu-firmware,TerryE\/nodemcu-firmware,raburton\/nodemcu-firmware,FrankX0\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,FelixPe\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,djphoenix\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,vowstar\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,romanchyla\/nodemcu-firmware,djphoenix\/nodemcu-firmware,karrots\/nodemcu-firmware,FelixPe\/nodemcu-firmware,nwf\/nodemcu-firmware,FrankX0\/nodemcu-firmware,jmattsson\/nodemcu-firmware,luizfeliperj\/nodemcu-firmware,bogvak\/nodemcu-firmware,romanchyla\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,vowstar\/nodemcu-firmware,HEYAHONG\/nodemcu-firmware,fetchbot\/nodemcu-firmware,nodemcu\/nodemcu-firmware,FrankX0\/nodemcu-firmware,oyooyo\/nodemcu-firmware,fetchbot\/nodemcu-firmware,nodemcu\/nodemcu-firmware,FelixPe\/nodemcu-firmware,kbeckmann\/nodemcu-firmware,karrots\/nodemcu-firmware,romanchyla\/nodemcu-firmware,raburton\/nodemcu-firmware","old_file":"ld\/nodemcu.ld","new_file":"ld\/nodemcu.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/FrankX0\/nodemcu-firmware.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"431ac7b3c559fb76dbfd13bbd3b572ca5299c670","subject":"cpu\/nrf51: added linkerscript for 128kb variant","message":"cpu\/nrf51: added linkerscript for 128kb variant\n","repos":"biboc\/RIOT,haoyangyu\/RIOT,gautric\/RIOT,biboc\/RIOT,MohmadAyman\/RIOT,watr-li\/RIOT,lebrush\/RIOT,Lexandro92\/RIOT-CoAP,adjih\/RIOT,cladmi\/RIOT,alex1818\/RIOT,rajma996\/RIOT,altairpearl\/RIOT,RBartz\/RIOT,haoyangyu\/RIOT,basilfx\/RIOT,wentaoshang\/RIOT,automote\/RIOT,brettswann\/RIOT,DipSwitch\/RIOT,asanka-code\/RIOT,TobiasFredersdorf\/RIOT,gautric\/RIOT,OTAkeys\/RIOT,rousselk\/RIOT,rakendrathapa\/RIOT,LudwigKnuepfer\/RIOT,zhuoshuguo\/RIOT,RubikonAlpha\/RIOT,neumodisch\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,josephnoir\/RIOT,hamilton-mote\/RIOT-OS,rfuentess\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,watr-li\/RIOT,Ell-i\/RIOT,beurdouche\/RIOT,mfrey\/RIOT,stevenj\/RIOT,attdona\/RIOT,wentaoshang\/RIOT,rousselk\/RIOT,abkam07\/RIOT,alex1818\/RIOT,patkan\/RIOT,cladmi\/RIOT,syin2\/RIOT,latsku\/RIOT,attdona\/RIOT,lebrush\/RIOT,JensErdmann\/RIOT,backenklee\/RIOT,plushvoxel\/RIOT,zhuoshuguo\/RIOT,openkosmosorg\/RIOT,robixnai\/RIOT,gbarnett\/RIOT,adrianghc\/RIOT,kYc0o\/RIOT,rakendrathapa\/RIOT,chris-wood\/RIOT,roberthartung\/RIOT,Lexandro92\/RIOT-CoAP,bartfaizoltan\/RIOT,tdautc19841202\/RIOT,abp719\/RIOT,luciotorre\/RIOT,ximus\/RIOT,ntrtrung\/RIOT,robixnai\/RIOT,watr-li\/RIOT,MonsterCode8000\/RIOT,changbiao\/RIOT,MonsterCode8000\/RIOT,kerneltask\/RIOT,arvindpdmn\/RIOT,mfrey\/RIOT,TobiasFredersdorf\/RIOT,stevenj\/RIOT,RubikonAlpha\/RIOT,EmuxEvans\/RIOT,tdautc19841202\/RIOT,immesys\/RiSyn,koenning\/RIOT,altairpearl\/RIOT,smlng\/RIOT,LudwigOrtmann\/RIOT,latsku\/RIOT,tfar\/RIOT,tfar\/RIOT,yogo1212\/RIOT,jremmert-phytec-iot\/RIOT,dhruvvyas90\/RIOT,arvindpdmn\/RIOT,Lexandro92\/RIOT-CoAP,cladmi\/RIOT,roberthartung\/RIOT,lebrush\/RIOT,dhruvvyas90\/RIOT,FrancescoErmini\/RIOT,brettswann\/RIOT,LudwigKnuepfer\/RIOT,tdautc19841202\/RIOT,FrancescoErmini\/RIOT,daniel-k\/RIOT,luciotorre\/RIOT,A-Paul\/RIOT,haoyangyu\/RIOT,adrianghc\/RIOT,koenning\/RIOT,JensErdmann\/RIOT,lazytech-org\/RIOT,kushalsingh007\/RIOT,FrancescoErmini\/RIOT,shady33\/RIOT,marcosalm\/RIOT,changbiao\/RIOT,LudwigKnuepfer\/RIOT,jbeyerstedt\/RIOT-OTA-update,thiagohd\/RIOT,rajma996\/RIOT,RBartz\/RIOT,kushalsingh007\/RIOT,kYc0o\/RIOT,bartfaizoltan\/RIOT,OTAkeys\/RIOT,neumodisch\/RIOT,BytesGalore\/RIOT,kYc0o\/RIOT,rousselk\/RIOT,toonst\/RIOT,abkam07\/RIOT,Lexandro92\/RIOT-CoAP,adrianghc\/RIOT,ks156\/RIOT,robixnai\/RIOT,patkan\/RIOT,Yonezawa-T2\/RIOT,RBartz\/RIOT,backenklee\/RIOT,robixnai\/RIOT,gebart\/RIOT,lebrush\/RIOT,ant9000\/RIOT,ntrtrung\/RIOT,miri64\/RIOT,beurdouche\/RIOT,aeneby\/RIOT,Darredevil\/RIOT,LudwigKnuepfer\/RIOT,marcosalm\/RIOT,adjih\/RIOT,centurysys\/RIOT,jfischer-phytec-iot\/RIOT,Ell-i\/RIOT,ThanhVic\/RIOT,marcosalm\/RIOT,attdona\/RIOT,syin2\/RIOT,cladmi\/RIOT,adjih\/RIOT,miri64\/RIOT,mfrey\/RIOT,watr-li\/RIOT,ThanhVic\/RIOT,katezilla\/RIOT,x3ro\/RIOT,kaspar030\/RIOT,asanka-code\/RIOT,marcosalm\/RIOT,Yonezawa-T2\/RIOT,wentaoshang\/RIOT,BytesGalore\/RIOT,RIOT-OS\/RIOT,Ell-i\/RIOT,patkan\/RIOT,bartfaizoltan\/RIOT,ThanhVic\/RIOT,OlegHahm\/RIOT,ntrtrung\/RIOT,katezilla\/RIOT,mfrey\/RIOT,altairpearl\/RIOT,ntrtrung\/RIOT,ntrtrung\/RIOT,altairpearl\/RIOT,gbarnett\/RIOT,daniel-k\/RIOT,malosek\/RIOT,yogo1212\/RIOT,Hyungsin\/RIOT-OS,kb2ma\/RIOT,chris-wood\/RIOT,asanka-code\/RIOT,binarylemon\/RIOT,thomaseichinger\/RIOT,shady33\/RIOT,OTAkeys\/RIOT,centurysys\/RIOT,l3nko\/RIOT,daniel-k\/RIOT,alignan\/RIOT,patkan\/RIOT,mziegert\/RIOT,LudwigOrtmann\/RIOT,lazytech-org\/RIOT,alignan\/RIOT,stevenj\/RIOT,RBartz\/RIOT,dailab\/RIOT,wentaoshang\/RIOT,ximus\/RIOT,Yonezawa-T2\/RIOT,toonst\/RIOT,dhruvvyas90\/RIOT,Josar\/RIOT,RIOT-OS\/RIOT,rousselk\/RIOT,abkam07\/RIOT,immesys\/RiSyn,kaleb-himes\/RIOT,alex1818\/RIOT,EmuxEvans\/RIOT,kbumsik\/RIOT,attdona\/RIOT,authmillenon\/RIOT,A-Paul\/RIOT,altairpearl\/RIOT,adjih\/RIOT,Hyungsin\/RIOT-OS,RBartz\/RIOT,syin2\/RIOT,rousselk\/RIOT,centurysys\/RIOT,automote\/RIOT,kb2ma\/RIOT,kaspar030\/RIOT,immesys\/RiSyn,lazytech-org\/RIOT,smlng\/RIOT,BytesGalore\/RIOT,kushalsingh007\/RIOT,arvindpdmn\/RIOT,basilfx\/RIOT,herrfz\/RIOT,daniel-k\/RIOT,JensErdmann\/RIOT,aeneby\/RIOT,changbiao\/RIOT,x3ro\/RIOT,smlng\/RIOT,tdautc19841202\/RIOT,gbarnett\/RIOT,Lexandro92\/RIOT-CoAP,roberthartung\/RIOT,adjih\/RIOT,Josar\/RIOT,OlegHahm\/RIOT,LudwigKnuepfer\/RIOT,alex1818\/RIOT,koenning\/RIOT,jfischer-phytec-iot\/RIOT,tdautc19841202\/RIOT,haoyangyu\/RIOT,avmelnikoff\/RIOT,PSHIVANI\/Riot-Code,tfar\/RIOT,alignan\/RIOT,dkm\/RIOT,BytesGalore\/RIOT,thomaseichinger\/RIOT,kaleb-himes\/RIOT,neiljay\/RIOT,backenklee\/RIOT,Osblouf\/RIOT,MarkXYang\/RIOT,Josar\/RIOT,aeneby\/RIOT,jbeyerstedt\/RIOT-OTA-update,Hyungsin\/RIOT-OS,brettswann\/RIOT,khhhh\/RIOT,koenning\/RIOT,msolters\/RIOT,PSHIVANI\/Riot-Code,FrancescoErmini\/RIOT,rajma996\/RIOT,MarkXYang\/RIOT,bartfaizoltan\/RIOT,gautric\/RIOT,automote\/RIOT,binarylemon\/RIOT,kushalsingh007\/RIOT,jremmert-phytec-iot\/RIOT,A-Paul\/RIOT,avmelnikoff\/RIOT,ks156\/RIOT,dailab\/RIOT,l3nko\/RIOT,l3nko\/RIOT,Osblouf\/RIOT,gautric\/RIOT,haoyangyu\/RIOT,malosek\/RIOT,kb2ma\/RIOT,adrianghc\/RIOT,openkosmosorg\/RIOT,DipSwitch\/RIOT,patkan\/RIOT,immesys\/RiSyn,authmillenon\/RIOT,Lexandro92\/RIOT-CoAP,mtausig\/RIOT,marcosalm\/RIOT,asanka-code\/RIOT,marcosalm\/RIOT,OTAkeys\/RIOT,jasonatran\/RIOT,mziegert\/RIOT,plushvoxel\/RIOT,smlng\/RIOT,kbumsik\/RIOT,zhuoshuguo\/RIOT,miri64\/RIOT,abkam07\/RIOT,kaspar030\/RIOT,Darredevil\/RIOT,Josar\/RIOT,watr-li\/RIOT,abp719\/RIOT,herrfz\/RIOT,centurysys\/RIOT,ximus\/RIOT,msolters\/RIOT,RIOT-OS\/RIOT,mtausig\/RIOT,d00616\/RIOT,mtausig\/RIOT,adrianghc\/RIOT,rakendrathapa\/RIOT,x3ro\/RIOT,RubikonAlpha\/RIOT,Yonezawa-T2\/RIOT,ant9000\/RIOT,ntrtrung\/RIOT,plushvoxel\/RIOT,dhruvvyas90\/RIOT,shady33\/RIOT,LudwigOrtmann\/RIOT,arvindpdmn\/RIOT,ant9000\/RIOT,Osblouf\/RIOT,koenning\/RIOT,basilfx\/RIOT,patkan\/RIOT,openkosmosorg\/RIOT,authmillenon\/RIOT,changbiao\/RIOT,Ell-i\/RIOT,stevenj\/RIOT,immesys\/RiSyn,kerneltask\/RIOT,RubikonAlpha\/RIOT,asanka-code\/RIOT,beurdouche\/RIOT,biboc\/RIOT,yogo1212\/RIOT,ThanhVic\/RIOT,gebart\/RIOT,rfuentess\/RIOT,kaspar030\/RIOT,MarkXYang\/RIOT,changbiao\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,x3ro\/RIOT,l3nko\/RIOT,tfar\/RIOT,MohmadAyman\/RIOT,rousselk\/RIOT,tfar\/RIOT,luciotorre\/RIOT,malosek\/RIOT,robixnai\/RIOT,biboc\/RIOT,alignan\/RIOT,neiljay\/RIOT,Hyungsin\/RIOT-OS,kbumsik\/RIOT,smlng\/RIOT,mziegert\/RIOT,Osblouf\/RIOT,avmelnikoff\/RIOT,khhhh\/RIOT,PSHIVANI\/Riot-Code,kerneltask\/RIOT,immesys\/RiSyn,x3ro\/RIOT,ThanhVic\/RIOT,DipSwitch\/RIOT,MonsterCode8000\/RIOT,mziegert\/RIOT,khhhh\/RIOT,hamilton-mote\/RIOT-OS,biboc\/RIOT,zhuoshuguo\/RIOT,latsku\/RIOT,OlegHahm\/RIOT,plushvoxel\/RIOT,d00616\/RIOT,abkam07\/RIOT,RBartz\/RIOT,malosek\/RIOT,binarylemon\/RIOT,thiagohd\/RIOT,jbeyerstedt\/RIOT-OTA-update,TobiasFredersdorf\/RIOT,syin2\/RIOT,bartfaizoltan\/RIOT,MarkXYang\/RIOT,openkosmosorg\/RIOT,jbeyerstedt\/RIOT-OTA-update,MonsterCode8000\/RIOT,gbarnett\/RIOT,malosek\/RIOT,ks156\/RIOT,luciotorre\/RIOT,khhhh\/RIOT,jasonatran\/RIOT,openkosmosorg\/RIOT,alignan\/RIOT,stevenj\/RIOT,rakendrathapa\/RIOT,mtausig\/RIOT,abp719\/RIOT,rfuentess\/RIOT,altairpearl\/RIOT,rfuentess\/RIOT,kbumsik\/RIOT,jfischer-phytec-iot\/RIOT,TobiasFredersdorf\/RIOT,kaleb-himes\/RIOT,josephnoir\/RIOT,toonst\/RIOT,automote\/RIOT,neiljay\/RIOT,daniel-k\/RIOT,TobiasFredersdorf\/RIOT,alex1818\/RIOT,roberthartung\/RIOT,centurysys\/RIOT,kb2ma\/RIOT,authmillenon\/RIOT,mtausig\/RIOT,gbarnett\/RIOT,mziegert\/RIOT,ks156\/RIOT,l3nko\/RIOT,gbarnett\/RIOT,roberthartung\/RIOT,thiagohd\/RIOT,neumodisch\/RIOT,msolters\/RIOT,syin2\/RIOT,shady33\/RIOT,ximus\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,JensErdmann\/RIOT,MohmadAyman\/RIOT,dailab\/RIOT,zhuoshuguo\/RIOT,bartfaizoltan\/RIOT,chris-wood\/RIOT,backenklee\/RIOT,dailab\/RIOT,MarkXYang\/RIOT,dkm\/RIOT,MohmadAyman\/RIOT,EmuxEvans\/RIOT,daniel-k\/RIOT,katezilla\/RIOT,Ell-i\/RIOT,thiagohd\/RIOT,lazytech-org\/RIOT,neiljay\/RIOT,rajma996\/RIOT,FrancescoErmini\/RIOT,neiljay\/RIOT,thiagohd\/RIOT,binarylemon\/RIOT,ks156\/RIOT,arvindpdmn\/RIOT,attdona\/RIOT,ant9000\/RIOT,RIOT-OS\/RIOT,LudwigOrtmann\/RIOT,lebrush\/RIOT,msolters\/RIOT,OlegHahm\/RIOT,l3nko\/RIOT,Yonezawa-T2\/RIOT,plushvoxel\/RIOT,d00616\/RIOT,RubikonAlpha\/RIOT,khhhh\/RIOT,lazytech-org\/RIOT,kaleb-himes\/RIOT,PSHIVANI\/Riot-Code,kbumsik\/RIOT,JensErdmann\/RIOT,jasonatran\/RIOT,miri64\/RIOT,kushalsingh007\/RIOT,abp719\/RIOT,Darredevil\/RIOT,d00616\/RIOT,Yonezawa-T2\/RIOT,malosek\/RIOT,backenklee\/RIOT,automote\/RIOT,ximus\/RIOT,jremmert-phytec-iot\/RIOT,gautric\/RIOT,MonsterCode8000\/RIOT,attdona\/RIOT,Josar\/RIOT,gebart\/RIOT,LudwigOrtmann\/RIOT,josephnoir\/RIOT,MarkXYang\/RIOT,MohmadAyman\/RIOT,dkm\/RIOT,rfuentess\/RIOT,yogo1212\/RIOT,abp719\/RIOT,kYc0o\/RIOT,abp719\/RIOT,kb2ma\/RIOT,beurdouche\/RIOT,jbeyerstedt\/RIOT-OTA-update,katezilla\/RIOT,neumodisch\/RIOT,haoyangyu\/RIOT,d00616\/RIOT,jfischer-phytec-iot\/RIOT,wentaoshang\/RIOT,miri64\/RIOT,PSHIVANI\/Riot-Code,dailab\/RIOT,dkm\/RIOT,hamilton-mote\/RIOT-OS,thomaseichinger\/RIOT,Hyungsin\/RIOT-OS,gebart\/RIOT,shady33\/RIOT,gebart\/RIOT,kerneltask\/RIOT,kYc0o\/RIOT,MohmadAyman\/RIOT,authmillenon\/RIOT,mziegert\/RIOT,openkosmosorg\/RIOT,binarylemon\/RIOT,LudwigOrtmann\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,kaspar030\/RIOT,herrfz\/RIOT,zhuoshuguo\/RIOT,chris-wood\/RIOT,toonst\/RIOT,wentaoshang\/RIOT,thomaseichinger\/RIOT,aeneby\/RIOT,luciotorre\/RIOT,hamilton-mote\/RIOT-OS,avmelnikoff\/RIOT,Darredevil\/RIOT,thomaseichinger\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,herrfz\/RIOT,watr-li\/RIOT,jasonatran\/RIOT,Osblouf\/RIOT,robixnai\/RIOT,koenning\/RIOT,kushalsingh007\/RIOT,cladmi\/RIOT,RubikonAlpha\/RIOT,Darredevil\/RIOT,binarylemon\/RIOT,chris-wood\/RIOT,jremmert-phytec-iot\/RIOT,jremmert-phytec-iot\/RIOT,DipSwitch\/RIOT,jfischer-phytec-iot\/RIOT,dkm\/RIOT,stevenj\/RIOT,rakendrathapa\/RIOT,kerneltask\/RIOT,tdautc19841202\/RIOT,asanka-code\/RIOT,MonsterCode8000\/RIOT,msolters\/RIOT,aeneby\/RIOT,khhhh\/RIOT,arvindpdmn\/RIOT,JensErdmann\/RIOT,A-Paul\/RIOT,herrfz\/RIOT,chris-wood\/RIOT,brettswann\/RIOT,mfrey\/RIOT,FrancescoErmini\/RIOT,A-Paul\/RIOT,dhruvvyas90\/RIOT,josephnoir\/RIOT,BytesGalore\/RIOT,thiagohd\/RIOT,EmuxEvans\/RIOT,automote\/RIOT,katezilla\/RIOT,josephnoir\/RIOT,herrfz\/RIOT,avmelnikoff\/RIOT,basilfx\/RIOT,dhruvvyas90\/RIOT,yogo1212\/RIOT,DipSwitch\/RIOT,luciotorre\/RIOT,shady33\/RIOT,rakendrathapa\/RIOT,changbiao\/RIOT,Osblouf\/RIOT,PSHIVANI\/Riot-Code,hamilton-mote\/RIOT-OS,abkam07\/RIOT,centurysys\/RIOT,EmuxEvans\/RIOT,msolters\/RIOT,beurdouche\/RIOT,neumodisch\/RIOT,lebrush\/RIOT,rajma996\/RIOT,ximus\/RIOT,brettswann\/RIOT,d00616\/RIOT,latsku\/RIOT,brettswann\/RIOT,latsku\/RIOT,authmillenon\/RIOT,alex1818\/RIOT,kaleb-himes\/RIOT,OlegHahm\/RIOT,basilfx\/RIOT,neumodisch\/RIOT,toonst\/RIOT,Darredevil\/RIOT,yogo1212\/RIOT,EmuxEvans\/RIOT,jasonatran\/RIOT,ThanhVic\/RIOT,latsku\/RIOT,DipSwitch\/RIOT,jremmert-phytec-iot\/RIOT,ant9000\/RIOT,rajma996\/RIOT","old_file":"cpu\/nrf51\/ldscripts\/nrf51x22xxab.ld","new_file":"cpu\/nrf51\/ldscripts\/nrf51x22xxab.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"cec49d2394174e4daac5bc6feb4e53219ae71a4b","subject":"Added a basic linker script.","message":"Added a basic linker script.","repos":"JackScottAU\/Synergy-OS","old_file":"Resources\/Linker-Script.ld","new_file":"Resources\/Linker-Script.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/JackScottAU\/Synergy-OS.git\/': The requested URL returned error: 403\n","license":"isc","lang":"Linker Script"}
{"commit":"9aeb273ce235369b06af0ebdbed11010daaf6fa6","subject":"add ldoc config","message":"add ldoc config\n","repos":"bakins\/stardust,bakins\/stardust,bakins\/stardust","old_file":"config.ld","new_file":"config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/bakins\/stardust.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5a515dc0ee1bcb7dbda92507fe6addcf599fbd36","subject":"Create linker.ld","message":"Create linker.ld","repos":"Star-Corporation\/StarOS,Star-Corporation\/StarOS,Star-Corporation\/StarOS","old_file":"staros\/kernel\/linker.ld","new_file":"staros\/kernel\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Star-Corporation\/StarOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"f77fd606a0834398c20b80ad15ce07ad290e4e10","subject":"nRF linker script cleanup.","message":"nRF linker script cleanup.\n","repos":"tve\/Espruino,redbear\/Espruino,wilberforce\/Espruino,lancernet\/Espruino,redbear\/Espruino,lancernet\/Espruino,luetgendorf\/Espruino,nkolban\/Espruino,nkolban\/Espruino,redbear\/Espruino,muet\/Espruino,wilberforce\/Espruino,tve\/Espruino,muet\/Espruino,muet\/Espruino,lancernet\/Espruino,muet\/Espruino,luetgendorf\/Espruino,redbear\/Espruino,luetgendorf\/Espruino,luetgendorf\/Espruino,tve\/Espruino,wilberforce\/Espruino,lancernet\/Espruino,luetgendorf\/Espruino,nkolban\/Espruino,tve\/Espruino,tve\/Espruino,tve\/Espruino,nkolban\/Espruino,lancernet\/Espruino,tve\/Espruino,lancernet\/Espruino,wilberforce\/Espruino,muet\/Espruino,wilberforce\/Espruino,nkolban\/Espruino,muet\/Espruino,redbear\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,nkolban\/Espruino,nkolban\/Espruino,muet\/Espruino,lancernet\/Espruino,redbear\/Espruino,luetgendorf\/Espruino,wilberforce\/Espruino,redbear\/Espruino","old_file":"targetlibs\/nrf5x\/nrf5x_linkers\/linker_nrf52_ble_espruino.ld","new_file":"targetlibs\/nrf5x\/nrf5x_linkers\/linker_nrf52_ble_espruino.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/nkolban\/Espruino.git\/': The requested URL returned error: 403\n","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"0e9de56426fa96235d70c65ab93da1d1a89f4500","subject":"Create tlink_ap6.ld","message":"Create tlink_ap6.ld","repos":"izard\/RTBench,izard\/RTBench","old_file":"tools\/src\/disturber\/baremetal\/smallos\/tlink_ap6.ld","new_file":"tools\/src\/disturber\/baremetal\/smallos\/tlink_ap6.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/izard\/RTBench.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"f02f5bf8e6ed7c1cb415bf05c55c2fe82e0f7de9","subject":"stm32_flash: Add BKPSRAM section.","message":"stm32_flash: Add BKPSRAM section.\n\nThis is taken from the datasheet.  We can place variables in there by\ndeclaring them in the C code like this:\n\n\/*!\n * User preferences\n *\/\nstatic struct prefs_t {\n    \/*! Serial number *\/\n    uint64_t serial;\n    \/*! Menu frequency *\/\n    uint16_t menu_freq;\n    \/*! Menu speed *\/\n    uint8_t menu_speed;\n    \/*! Menu volume (attenuation) *\/\n    uint8_t menu_vol;\n    \/*! Default operating mode *\/\n    uint8_t op_mode;\n} prefs __attribute__((section(\".bkpsram\")));\n\ngit-svn-id: 3db15d9df66343e7f944511864f914adee1f7549@2408 01035d8c-6547-0410-b346-abe4f91aad63\n","repos":"freedv\/codec2,freedv\/codec2,freedv\/codec2,freedv\/codec2","old_file":"stm32\/stm32_flash.ld","new_file":"stm32\/stm32_flash.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/freedv\/codec2.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"513b1a25e0b9994a892fc49b156215b054164e0d","subject":"Use internal RAM only.","message":"Use internal RAM only.\n","repos":"FreeRTOS\/FreeRTOS-Kernel,FreeRTOS\/FreeRTOS-Kernel","old_file":"Demo\/ColdFire_MCF5282_Eclipse\/RTOSDemo\/m5282evb-dram_code-rambar_data-hosted.ld","new_file":"Demo\/ColdFire_MCF5282_Eclipse\/RTOSDemo\/m5282evb-dram_code-rambar_data-hosted.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/FreeRTOS\/FreeRTOS-Kernel.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"23da134557bd1b6b0b7998b3ea2bd6957849c61f","subject":"Fix bad linker","message":"Fix bad linker\n","repos":"Tutul-\/tumuxOS,Tutul-\/tumuxOS,Tutul-\/tumuxOS","old_file":"src\/kernel\/arch\/x86\/linker.ld","new_file":"src\/kernel\/arch\/x86\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Tutul-\/tumuxOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"0e53c52b88c611ebc1cf37e6a78cfe7d0bc1c3cd","subject":"Use the correct dtb section declaration","message":"Use the correct dtb section declaration\n\n(cherry picked from commit 66200b3fad4fc8f836cc3d5ef3545fe2ee6ab2cb)\n","repos":"kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa","old_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kalray\/odp-mppa.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"5e062659bfba18482c26ae9c0a03c445986d0e98","subject":"Removed the labels that were in there as they're not really required. Added some more sections.","message":"Removed the labels that were in there as they're not really required. Added some more sections.\n","repos":"Lucretia\/bare_bones,Lucretia\/tamp2,robdaemon\/bare_bones","old_file":"src\/pc\/linker.ld","new_file":"src\/pc\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Lucretia\/bare_bones.git\/': The requested URL returned error: 403\n","license":"cc0-1.0","lang":"Linker Script"}
{"commit":"8c41f2f3b19c8a7220e0bf3609d6439e013ab7b4","subject":"Fix missing fallback into kernel image","message":"Fix missing fallback into kernel image\n","repos":"Tutul-\/tumuxOS,Tutul-\/tumuxOS,Tutul-\/tumuxOS","old_file":"src\/tumux\/arch\/x86\/linker.ld","new_file":"src\/tumux\/arch\/x86\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Tutul-\/tumuxOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"36d29dedd5397f347d15ec9aa28cd9c40079ef8d","subject":"Allow clang for kernel compilation","message":"Allow clang for kernel compilation\n\nRemove .ident sections, and force separations of .text and\n.data sections into separate program headers, for the benefit\nof the check done by MINIX boot monitor in multiboot mode.\n","repos":"veritas-shine\/minix3-rpi,veritas-shine\/minix3-rpi,veritas-shine\/minix3-rpi,veritas-shine\/minix3-rpi,veritas-shine\/minix3-rpi,veritas-shine\/minix3-rpi,veritas-shine\/minix3-rpi,veritas-shine\/minix3-rpi","old_file":"kernel\/arch\/i386\/kernel.lds","new_file":"kernel\/arch\/i386\/kernel.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/veritas-shine\/minix3-rpi.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"457af36662a9534e9e59c0ee3c9a2fc595f98c03","subject":"fixed font segment size","message":"fixed font segment size\n","repos":"andrei7c4\/esptwitterclient,andrei7c4\/esptwitterclient,andrei7c4\/esptwitterclient","old_file":"ld\/eagle.app.v6.ld","new_file":"ld\/eagle.app.v6.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/andrei7c4\/esptwitterclient.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"2a1b3e3d313a9e0c44f97a6ea5cff6ed48672115","subject":"fixed the fixed the gcc compiling error in ubuntu host OS","message":"fixed the fixed the gcc compiling error in ubuntu host OS\n\n\ngit-svn-id: 839522a79b1d56a78fa446d2fd3a0c499f8e535e@2511 bbd45198-f89e-11dd-88c7-29a3b14d5316\n","repos":"yongli3\/rt-thread,FlyLu\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,weety\/rt-thread,hezlog\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,igou\/rt-thread,weety\/rt-thread,igou\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,zhaojuntao\/rt-thread,weiyuliang\/rt-thread,AubrCool\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,weiyuliang\/rt-thread,igou\/rt-thread,weiyuliang\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,yongli3\/rt-thread,zhaojuntao\/rt-thread,FlyLu\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,geniusgogo\/rt-thread,ArdaFu\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,yongli3\/rt-thread,zhaojuntao\/rt-thread,armink\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,AubrCool\/rt-thread,ArdaFu\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,armink\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,ArdaFu\/rt-thread,zhaojuntao\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,gbcwbz\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,geniusgogo\/rt-thread,zhaojuntao\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,yongli3\/rt-thread,zhaojuntao\/rt-thread,FlyLu\/rt-thread,geniusgogo\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,AubrCool\/rt-thread,weety\/rt-thread,wolfgangz2013\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,yongli3\/rt-thread,wolfgangz2013\/rt-thread,armink\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,weiyuliang\/rt-thread,hezlog\/rt-thread","old_file":"bsp\/efm32\/efm32gg_rom.ld","new_file":"bsp\/efm32\/efm32gg_rom.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/igou\/rt-thread.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"1ca71a1468eca60dba24259330932ab6c69a741b","subject":"And this one.","message":"And this one.\n\n\ngit-svn-id: fb278a52ad97f7fbef074986829f2c6a2a3c4b34@474 c25cc9d1-44fa-0310-b259-ad778cb1d433\n","repos":"dioptre\/newos,siraj\/newos,travisg\/newos,dioptre\/newos,zhouxh1023\/newos,siraj\/newos,zhouxh1023\/newos,dioptre\/newos,siraj\/newos,siraj\/newos,travisg\/newos,zhouxh1023\/newos,travisg\/newos","old_file":"lib\/nulibc\/library.ld","new_file":"lib\/nulibc\/library.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/zhouxh1023\/newos.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"34a130fea21a8db2129663d6c83cf68b066d936c","subject":"Forgot to include this debug linker script.","message":"Forgot to include this debug linker script.\n\n\nFormer-commit-id: 0567531f9e8bed863f44ac2320d3016059aff755","repos":"adamwolf\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,ricklon\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,chipKIT32\/chipKIT32-MAX,majenkotech\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,tintin304\/chipKIT32-MAX,adamwolf\/chipKIT32-MAX,EmbeddedMan\/chipKIT32-MAX","old_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-32MX250F128-nobootloader.ld","new_file":"hardware\/pic32\/cores\/pic32\/chipKIT-application-32MX250F128-nobootloader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ricklon\/chipKIT32-MAX.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"613a80bc99fa39a0da7af564091b32cca3416225","subject":"set up ldoc and documented rima.lib.object for a test","message":"set up ldoc and documented rima.lib.object for a test\n","repos":"geoffleyland\/rima,geoffleyland\/rima,geoffleyland\/rima","old_file":"config.ld","new_file":"config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/geoffleyland\/rima.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"8d47f8396442f34c82ca598ef700d476c9d3af7e","subject":"cpu\/stm32f1: added stm32f103c8 linkerscript","message":"cpu\/stm32f1: added stm32f103c8 linkerscript\n\nAdded stm32f103c8 memory definitions for cortexm common linkerscript\n","repos":"asanka-code\/RIOT,gbarnett\/RIOT,syin2\/RIOT,zhuoshuguo\/RIOT,rajma996\/RIOT,attdona\/RIOT,latsku\/RIOT,ThanhVic\/RIOT,FrancescoErmini\/RIOT,jfischer-phytec-iot\/RIOT,A-Paul\/RIOT,herrfz\/RIOT,herrfz\/RIOT,robixnai\/RIOT,ant9000\/RIOT,malosek\/RIOT,dhruvvyas90\/RIOT,RBartz\/RIOT,abkam07\/RIOT,wentaoshang\/RIOT,msolters\/RIOT,lebrush\/RIOT,jbeyerstedt\/RIOT-OTA-update,smlng\/RIOT,roberthartung\/RIOT,arvindpdmn\/RIOT,malosek\/RIOT,basilfx\/RIOT,kbumsik\/RIOT,neiljay\/RIOT,lazytech-org\/RIOT,stevenj\/RIOT,gbarnett\/RIOT,katezilla\/RIOT,dkm\/RIOT,dhruvvyas90\/RIOT,kb2ma\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,kerneltask\/RIOT,kbumsik\/RIOT,rfuentess\/RIOT,Ell-i\/RIOT,adrianghc\/RIOT,FrancescoErmini\/RIOT,cladmi\/RIOT,abkam07\/RIOT,FrancescoErmini\/RIOT,biboc\/RIOT,JensErdmann\/RIOT,mtausig\/RIOT,tfar\/RIOT,RubikonAlpha\/RIOT,toonst\/RIOT,patkan\/RIOT,TobiasFredersdorf\/RIOT,basilfx\/RIOT,msolters\/RIOT,altairpearl\/RIOT,RIOT-OS\/RIOT,Yonezawa-T2\/RIOT,mziegert\/RIOT,haoyangyu\/RIOT,x3ro\/RIOT,plushvoxel\/RIOT,BytesGalore\/RIOT,adjih\/RIOT,OTAkeys\/RIOT,l3nko\/RIOT,smlng\/RIOT,daniel-k\/RIOT,Josar\/RIOT,beurdouche\/RIOT,beurdouche\/RIOT,malosek\/RIOT,arvindpdmn\/RIOT,mziegert\/RIOT,cladmi\/RIOT,kb2ma\/RIOT,neumodisch\/RIOT,hamilton-mote\/RIOT-OS,immesys\/RiSyn,JensErdmann\/RIOT,haoyangyu\/RIOT,attdona\/RIOT,ThanhVic\/RIOT,brettswann\/RIOT,dailab\/RIOT,msolters\/RIOT,BytesGalore\/RIOT,aeneby\/RIOT,lebrush\/RIOT,tfar\/RIOT,jfischer-phytec-iot\/RIOT,alignan\/RIOT,dailab\/RIOT,rousselk\/RIOT,haoyangyu\/RIOT,rakendrathapa\/RIOT,lebrush\/RIOT,MohmadAyman\/RIOT,herrfz\/RIOT,syin2\/RIOT,asanka-code\/RIOT,khhhh\/RIOT,LudwigKnuepfer\/RIOT,wentaoshang\/RIOT,toonst\/RIOT,neumodisch\/RIOT,thiagohd\/RIOT,asanka-code\/RIOT,TobiasFredersdorf\/RIOT,robixnai\/RIOT,patkan\/RIOT,robixnai\/RIOT,josephnoir\/RIOT,mtausig\/RIOT,patkan\/RIOT,wentaoshang\/RIOT,ks156\/RIOT,RubikonAlpha\/RIOT,dhruvvyas90\/RIOT,Ell-i\/RIOT,zhuoshuguo\/RIOT,miri64\/RIOT,LudwigKnuepfer\/RIOT,RubikonAlpha\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,thomaseichinger\/RIOT,attdona\/RIOT,kb2ma\/RIOT,BytesGalore\/RIOT,cladmi\/RIOT,gbarnett\/RIOT,adrianghc\/RIOT,watr-li\/RIOT,A-Paul\/RIOT,JensErdmann\/RIOT,ThanhVic\/RIOT,gbarnett\/RIOT,Josar\/RIOT,robixnai\/RIOT,binarylemon\/RIOT,malosek\/RIOT,RBartz\/RIOT,altairpearl\/RIOT,RubikonAlpha\/RIOT,abp719\/RIOT,d00616\/RIOT,Yonezawa-T2\/RIOT,plushvoxel\/RIOT,herrfz\/RIOT,dkm\/RIOT,LudwigKnuepfer\/RIOT,alignan\/RIOT,Ell-i\/RIOT,kerneltask\/RIOT,lazytech-org\/RIOT,patkan\/RIOT,latsku\/RIOT,roberthartung\/RIOT,avmelnikoff\/RIOT,patkan\/RIOT,arvindpdmn\/RIOT,FrancescoErmini\/RIOT,OlegHahm\/RIOT,authmillenon\/RIOT,d00616\/RIOT,adrianghc\/RIOT,luciotorre\/RIOT,RubikonAlpha\/RIOT,Hyungsin\/RIOT-OS,abp719\/RIOT,gebart\/RIOT,zhuoshuguo\/RIOT,luciotorre\/RIOT,yogo1212\/RIOT,kerneltask\/RIOT,shady33\/RIOT,stevenj\/RIOT,cladmi\/RIOT,hamilton-mote\/RIOT-OS,x3ro\/RIOT,gautric\/RIOT,d00616\/RIOT,beurdouche\/RIOT,jfischer-phytec-iot\/RIOT,kerneltask\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,altairpearl\/RIOT,mfrey\/RIOT,backenklee\/RIOT,OTAkeys\/RIOT,shady33\/RIOT,dhruvvyas90\/RIOT,abp719\/RIOT,khhhh\/RIOT,dailab\/RIOT,stevenj\/RIOT,jbeyerstedt\/RIOT-OTA-update,MonsterCode8000\/RIOT,MonsterCode8000\/RIOT,adjih\/RIOT,backenklee\/RIOT,lazytech-org\/RIOT,yogo1212\/RIOT,abp719\/RIOT,jasonatran\/RIOT,tfar\/RIOT,RBartz\/RIOT,alignan\/RIOT,authmillenon\/RIOT,altairpearl\/RIOT,asanka-code\/RIOT,stevenj\/RIOT,l3nko\/RIOT,josephnoir\/RIOT,abkam07\/RIOT,dkm\/RIOT,khhhh\/RIOT,adjih\/RIOT,mziegert\/RIOT,alignan\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,MonsterCode8000\/RIOT,JensErdmann\/RIOT,Josar\/RIOT,beurdouche\/RIOT,rajma996\/RIOT,rakendrathapa\/RIOT,neumodisch\/RIOT,OlegHahm\/RIOT,RIOT-OS\/RIOT,rousselk\/RIOT,malosek\/RIOT,LudwigOrtmann\/RIOT,mfrey\/RIOT,neumodisch\/RIOT,l3nko\/RIOT,kYc0o\/RIOT,MonsterCode8000\/RIOT,rajma996\/RIOT,cladmi\/RIOT,abp719\/RIOT,Yonezawa-T2\/RIOT,mtausig\/RIOT,brettswann\/RIOT,neumodisch\/RIOT,kerneltask\/RIOT,shady33\/RIOT,gebart\/RIOT,rfuentess\/RIOT,MohmadAyman\/RIOT,BytesGalore\/RIOT,khhhh\/RIOT,miri64\/RIOT,MohmadAyman\/RIOT,rousselk\/RIOT,beurdouche\/RIOT,msolters\/RIOT,Ell-i\/RIOT,lebrush\/RIOT,avmelnikoff\/RIOT,altairpearl\/RIOT,jasonatran\/RIOT,rajma996\/RIOT,ant9000\/RIOT,neiljay\/RIOT,gbarnett\/RIOT,A-Paul\/RIOT,jremmert-phytec-iot\/RIOT,zhuoshuguo\/RIOT,abkam07\/RIOT,robixnai\/RIOT,MohmadAyman\/RIOT,daniel-k\/RIOT,attdona\/RIOT,katezilla\/RIOT,kaspar030\/RIOT,ThanhVic\/RIOT,jasonatran\/RIOT,adrianghc\/RIOT,JensErdmann\/RIOT,smlng\/RIOT,brettswann\/RIOT,toonst\/RIOT,rakendrathapa\/RIOT,kaleb-himes\/RIOT,attdona\/RIOT,latsku\/RIOT,thiagohd\/RIOT,dkm\/RIOT,josephnoir\/RIOT,dailab\/RIOT,binarylemon\/RIOT,TobiasFredersdorf\/RIOT,abkam07\/RIOT,robixnai\/RIOT,miri64\/RIOT,jbeyerstedt\/RIOT-OTA-update,authmillenon\/RIOT,binarylemon\/RIOT,mfrey\/RIOT,yogo1212\/RIOT,haoyangyu\/RIOT,wentaoshang\/RIOT,lazytech-org\/RIOT,arvindpdmn\/RIOT,jbeyerstedt\/RIOT-OTA-update,jasonatran\/RIOT,josephnoir\/RIOT,RBartz\/RIOT,hamilton-mote\/RIOT-OS,adjih\/RIOT,ks156\/RIOT,thomaseichinger\/RIOT,rfuentess\/RIOT,biboc\/RIOT,thomaseichinger\/RIOT,luciotorre\/RIOT,binarylemon\/RIOT,msolters\/RIOT,daniel-k\/RIOT,gebart\/RIOT,mtausig\/RIOT,ThanhVic\/RIOT,dkm\/RIOT,jremmert-phytec-iot\/RIOT,yogo1212\/RIOT,thiagohd\/RIOT,Hyungsin\/RIOT-OS,biboc\/RIOT,gautric\/RIOT,rajma996\/RIOT,thiagohd\/RIOT,jbeyerstedt\/RIOT-OTA-update,TobiasFredersdorf\/RIOT,khhhh\/RIOT,arvindpdmn\/RIOT,thiagohd\/RIOT,kbumsik\/RIOT,LudwigOrtmann\/RIOT,immesys\/RiSyn,brettswann\/RIOT,mziegert\/RIOT,FrancescoErmini\/RIOT,ks156\/RIOT,attdona\/RIOT,thomaseichinger\/RIOT,rousselk\/RIOT,aeneby\/RIOT,thomaseichinger\/RIOT,stevenj\/RIOT,latsku\/RIOT,kaspar030\/RIOT,hamilton-mote\/RIOT-OS,latsku\/RIOT,watr-li\/RIOT,rakendrathapa\/RIOT,binarylemon\/RIOT,neiljay\/RIOT,RIOT-OS\/RIOT,mfrey\/RIOT,LudwigOrtmann\/RIOT,plushvoxel\/RIOT,jremmert-phytec-iot\/RIOT,alignan\/RIOT,kYc0o\/RIOT,d00616\/RIOT,jremmert-phytec-iot\/RIOT,gautric\/RIOT,malosek\/RIOT,rousselk\/RIOT,rfuentess\/RIOT,dhruvvyas90\/RIOT,basilfx\/RIOT,lebrush\/RIOT,katezilla\/RIOT,OlegHahm\/RIOT,daniel-k\/RIOT,toonst\/RIOT,A-Paul\/RIOT,kaleb-himes\/RIOT,rakendrathapa\/RIOT,patkan\/RIOT,JensErdmann\/RIOT,adjih\/RIOT,Hyungsin\/RIOT-OS,RubikonAlpha\/RIOT,Josar\/RIOT,d00616\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,l3nko\/RIOT,OTAkeys\/RIOT,syin2\/RIOT,Josar\/RIOT,neumodisch\/RIOT,asanka-code\/RIOT,syin2\/RIOT,kaleb-himes\/RIOT,ant9000\/RIOT,kYc0o\/RIOT,Hyungsin\/RIOT-OS,LudwigKnuepfer\/RIOT,luciotorre\/RIOT,Yonezawa-T2\/RIOT,Yonezawa-T2\/RIOT,arvindpdmn\/RIOT,jremmert-phytec-iot\/RIOT,neiljay\/RIOT,brettswann\/RIOT,mziegert\/RIOT,OlegHahm\/RIOT,ks156\/RIOT,aeneby\/RIOT,x3ro\/RIOT,kbumsik\/RIOT,latsku\/RIOT,neiljay\/RIOT,MohmadAyman\/RIOT,shady33\/RIOT,l3nko\/RIOT,rakendrathapa\/RIOT,kaleb-himes\/RIOT,basilfx\/RIOT,RIOT-OS\/RIOT,RIOT-OS\/RIOT,avmelnikoff\/RIOT,lazytech-org\/RIOT,katezilla\/RIOT,biboc\/RIOT,kaleb-himes\/RIOT,backenklee\/RIOT,ThanhVic\/RIOT,adrianghc\/RIOT,kYc0o\/RIOT,x3ro\/RIOT,LudwigKnuepfer\/RIOT,ant9000\/RIOT,abkam07\/RIOT,aeneby\/RIOT,rousselk\/RIOT,plushvoxel\/RIOT,authmillenon\/RIOT,immesys\/RiSyn,lebrush\/RIOT,BytesGalore\/RIOT,dhruvvyas90\/RIOT,x3ro\/RIOT,roberthartung\/RIOT,msolters\/RIOT,kaspar030\/RIOT,shady33\/RIOT,zhuoshuguo\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,kaspar030\/RIOT,mziegert\/RIOT,gautric\/RIOT,Ell-i\/RIOT,authmillenon\/RIOT,gautric\/RIOT,gebart\/RIOT,Yonezawa-T2\/RIOT,kb2ma\/RIOT,asanka-code\/RIOT,authmillenon\/RIOT,mtausig\/RIOT,gbarnett\/RIOT,jremmert-phytec-iot\/RIOT,daniel-k\/RIOT,yogo1212\/RIOT,haoyangyu\/RIOT,kbumsik\/RIOT,rfuentess\/RIOT,smlng\/RIOT,mfrey\/RIOT,syin2\/RIOT,LudwigOrtmann\/RIOT,stevenj\/RIOT,toonst\/RIOT,hamilton-mote\/RIOT-OS,smlng\/RIOT,backenklee\/RIOT,ks156\/RIOT,aeneby\/RIOT,d00616\/RIOT,binarylemon\/RIOT,luciotorre\/RIOT,watr-li\/RIOT,kb2ma\/RIOT,daniel-k\/RIOT,ant9000\/RIOT,FrancescoErmini\/RIOT,wentaoshang\/RIOT,jfischer-phytec-iot\/RIOT,herrfz\/RIOT,abp719\/RIOT,LudwigOrtmann\/RIOT,Hyungsin\/RIOT-OS,basilfx\/RIOT,zhuoshuguo\/RIOT,katezilla\/RIOT,MonsterCode8000\/RIOT,tfar\/RIOT,biboc\/RIOT,avmelnikoff\/RIOT,gebart\/RIOT,roberthartung\/RIOT,l3nko\/RIOT,khhhh\/RIOT,RBartz\/RIOT,miri64\/RIOT,MonsterCode8000\/RIOT,wentaoshang\/RIOT,josephnoir\/RIOT,shady33\/RIOT,dailab\/RIOT,immesys\/RiSyn,jfischer-phytec-iot\/RIOT,TobiasFredersdorf\/RIOT,backenklee\/RIOT,avmelnikoff\/RIOT,plushvoxel\/RIOT,A-Paul\/RIOT,OlegHahm\/RIOT,RBartz\/RIOT,brettswann\/RIOT,LudwigOrtmann\/RIOT,OTAkeys\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,watr-li\/RIOT,altairpearl\/RIOT,immesys\/RiSyn,rajma996\/RIOT,watr-li\/RIOT,herrfz\/RIOT,MohmadAyman\/RIOT,miri64\/RIOT,roberthartung\/RIOT,kaspar030\/RIOT,watr-li\/RIOT,haoyangyu\/RIOT,immesys\/RiSyn,tfar\/RIOT,thiagohd\/RIOT,luciotorre\/RIOT","old_file":"cpu\/stm32f1\/ldscripts\/stm32f103c8.ld","new_file":"cpu\/stm32f1\/ldscripts\/stm32f103c8.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"1392198a3545b60df49ac5b966fa6c12d168bedf","subject":"Common daplink.ld gcc linker script.","message":"Common daplink.ld gcc linker script.\n","repos":"google\/DAPLink-port,google\/DAPLink-port,google\/DAPLink-port,google\/DAPLink-port","old_file":"source\/daplink\/daplink.ld","new_file":"source\/daplink\/daplink.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/google\/DAPLink-port.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"97771b3334f0cbfb28e438ea764421233d6a0b00","subject":"add GNU ld script.","message":"add GNU ld script.\n\ngit-svn-id: 839522a79b1d56a78fa446d2fd3a0c499f8e535e@1918 bbd45198-f89e-11dd-88c7-29a3b14d5316\n","repos":"FlyLu\/rt-thread,weiyuliang\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,weety\/rt-thread,RT-Thread\/rt-thread,zhaojuntao\/rt-thread,RT-Thread\/rt-thread,geniusgogo\/rt-thread,gbcwbz\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,gbcwbz\/rt-thread,zhaojuntao\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,nongxiaoming\/rt-thread,igou\/rt-thread,yongli3\/rt-thread,RT-Thread\/rt-thread,igou\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,geniusgogo\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,AubrCool\/rt-thread,AubrCool\/rt-thread,weiyuliang\/rt-thread,igou\/rt-thread,igou\/rt-thread,igou\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,yongli3\/rt-thread,nongxiaoming\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,weety\/rt-thread,armink\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,yongli3\/rt-thread,wolfgangz2013\/rt-thread,yongli3\/rt-thread,FlyLu\/rt-thread,ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,weiyuliang\/rt-thread,RT-Thread\/rt-thread,igou\/rt-thread,armink\/rt-thread,gbcwbz\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,weety\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,geniusgogo\/rt-thread,hezlog\/rt-thread,wolfgangz2013\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,hezlog\/rt-thread,weiyuliang\/rt-thread,geniusgogo\/rt-thread,igou\/rt-thread,nongxiaoming\/rt-thread,yongli3\/rt-thread,hezlog\/rt-thread,zhaojuntao\/rt-thread,nongxiaoming\/rt-thread,RT-Thread\/rt-thread,nongxiaoming\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,hezlog\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,yongli3\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,wolfgangz2013\/rt-thread,wolfgangz2013\/rt-thread,wolfgangz2013\/rt-thread,FlyLu\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,AubrCool\/rt-thread","old_file":"bsp\/lpc176x\/lpc17xx_rom.ld","new_file":"bsp\/lpc176x\/lpc17xx_rom.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/igou\/rt-thread.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"cbe0969130ef0ae716a91dd92fabe35b6e246fb4","subject":"stm32_flash: Add a section for EEPROM data.","message":"stm32_flash: Add a section for EEPROM data.\n\nThis allocates a few sectors of flash for the following purposes:\n- Sector 0: ISR vector data.  (This gets mapped to address 0; so we have\n  no choice, the ISR data *must* reside here.)\n- Sector 1..3: Virtual EEPROM.  We'll stash our configuration parameters\n  here.  We have 48kB available.\n- Sector 4.. onwards: Program data\n\nCredit: clive1, ST e2e Communities.\nhttps:\/\/my.st.com\/public\/STe2ecommunities\/mcu\/_layouts\/st\/getshorturl.aspx?List={697285D7-A9CA-445D-B16C-F23BF0E3B1A3}&ItemId=24079\n\ngit-svn-id: 3db15d9df66343e7f944511864f914adee1f7549@2390 01035d8c-6547-0410-b346-abe4f91aad63\n","repos":"freedv\/codec2,freedv\/codec2,freedv\/codec2,freedv\/codec2","old_file":"stm32\/stm32_flash.ld","new_file":"stm32\/stm32_flash.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/freedv\/codec2.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"e25510ad5bd0f34d3b179dac18675a8ec34f26fd","subject":"config.ld: add LDoc config","message":"config.ld: add LDoc config\n","repos":"ChickenNuggers\/Moon-Moon,wiseguiz\/Moon-Moon","old_file":"config.ld","new_file":"config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ChickenNuggers\/Moon-Moon.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"5d45b5a0cac814d46082ffc590138f5f8d6e7303","subject":"K66F: Move bss section to m_data_2 Section","message":"K66F: Move bss section to m_data_2 Section\n\nSigned-off-by: Mahadevan Mahesh <778f93d13cb34f99fc4522dcbb13a8dffe2c8547@nxp.com>\n","repos":"mikaleppanen\/mbed-os,kjbracey-arm\/mbed,fanghuaqi\/mbed,HeadsUpDisplayInc\/mbed,monkiineko\/mbed-os,ryankurte\/mbed-os,svogl\/mbed-os,YarivCol\/mbed-os,catiedev\/mbed-os,infinnovation\/mbed-os,bcostm\/mbed-os,bulislaw\/mbed-os,netzimme\/mbed-os,nRFMesh\/mbed-os,bulislaw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,fahhem\/mbed-os,catiedev\/mbed-os,pradeep-gr\/mbed-os5-onsemi,screamerbg\/mbed,adamgreen\/mbed,catiedev\/mbed-os,ryankurte\/mbed-os,karsev\/mbed-os,adamgreen\/mbed,karsev\/mbed-os,mikaleppanen\/mbed-os,andcor02\/mbed-os,pradeep-gr\/mbed-os5-onsemi,mmorenobarm\/mbed-os,nRFMesh\/mbed-os,screamerbg\/mbed,infinnovation\/mbed-os,nRFMesh\/mbed-os,betzw\/mbed-os,HeadsUpDisplayInc\/mbed,CalSol\/mbed,infinnovation\/mbed-os,mikaleppanen\/mbed-os,bcostm\/mbed-os,adamgreen\/mbed,mmorenobarm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,mikaleppanen\/mbed-os,fahhem\/mbed-os,mmorenobarm\/mbed-os,YarivCol\/mbed-os,cvtsi2sd\/mbed-os,svogl\/mbed-os,betzw\/mbed-os,fahhem\/mbed-os,catiedev\/mbed-os,cvtsi2sd\/mbed-os,svogl\/mbed-os,Archcady\/mbed-os,c1728p9\/mbed-os,kl-cruz\/mbed-os,andcor02\/mbed-os,HeadsUpDisplayInc\/mbed,kl-cruz\/mbed-os,infinnovation\/mbed-os,Archcady\/mbed-os,c1728p9\/mbed-os,fanghuaqi\/mbed,mazimkhan\/mbed-os,pradeep-gr\/mbed-os5-onsemi,arostm\/mbed-os,fahhem\/mbed-os,svogl\/mbed-os,bulislaw\/mbed-os,monkiineko\/mbed-os,arostm\/mbed-os,CalSol\/mbed,mmorenobarm\/mbed-os,screamerbg\/mbed,CalSol\/mbed,CalSol\/mbed,c1728p9\/mbed-os,YarivCol\/mbed-os,fahhem\/mbed-os,screamerbg\/mbed,mmorenobarm\/mbed-os,adamgreen\/mbed,mbedmicro\/mbed,netzimme\/mbed-os,HeadsUpDisplayInc\/mbed,kjbracey-arm\/mbed,adamgreen\/mbed,mazimkhan\/mbed-os,ryankurte\/mbed-os,NXPmicro\/mbed,Archcady\/mbed-os,YarivCol\/mbed-os,svogl\/mbed-os,CalSol\/mbed,Archcady\/mbed-os,andcor02\/mbed-os,kl-cruz\/mbed-os,andcor02\/mbed-os,Archcady\/mbed-os,fanghuaqi\/mbed,mbedmicro\/mbed,bcostm\/mbed-os,NXPmicro\/mbed,ryankurte\/mbed-os,andcor02\/mbed-os,nRFMesh\/mbed-os,screamerbg\/mbed,kjbracey-arm\/mbed,HeadsUpDisplayInc\/mbed,netzimme\/mbed-os,arostm\/mbed-os,betzw\/mbed-os,c1728p9\/mbed-os,ryankurte\/mbed-os,betzw\/mbed-os,NXPmicro\/mbed,bcostm\/mbed-os,HeadsUpDisplayInc\/mbed,arostm\/mbed-os,karsev\/mbed-os,mikaleppanen\/mbed-os,cvtsi2sd\/mbed-os,catiedev\/mbed-os,mikaleppanen\/mbed-os,netzimme\/mbed-os,arostm\/mbed-os,kl-cruz\/mbed-os,cvtsi2sd\/mbed-os,kl-cruz\/mbed-os,kl-cruz\/mbed-os,YarivCol\/mbed-os,mbedmicro\/mbed,Archcady\/mbed-os,svogl\/mbed-os,andcor02\/mbed-os,netzimme\/mbed-os,karsev\/mbed-os,NXPmicro\/mbed,betzw\/mbed-os,mmorenobarm\/mbed-os,infinnovation\/mbed-os,catiedev\/mbed-os,mbedmicro\/mbed,fanghuaqi\/mbed,monkiineko\/mbed-os,mazimkhan\/mbed-os,monkiineko\/mbed-os,bcostm\/mbed-os,betzw\/mbed-os,NXPmicro\/mbed,cvtsi2sd\/mbed-os,bulislaw\/mbed-os,monkiineko\/mbed-os,monkiineko\/mbed-os,mazimkhan\/mbed-os,adamgreen\/mbed,ryankurte\/mbed-os,YarivCol\/mbed-os,karsev\/mbed-os,bulislaw\/mbed-os,karsev\/mbed-os,CalSol\/mbed,arostm\/mbed-os,c1728p9\/mbed-os,c1728p9\/mbed-os,bulislaw\/mbed-os,kjbracey-arm\/mbed,nRFMesh\/mbed-os,cvtsi2sd\/mbed-os,mazimkhan\/mbed-os,mbedmicro\/mbed,netzimme\/mbed-os,pradeep-gr\/mbed-os5-onsemi,fahhem\/mbed-os,infinnovation\/mbed-os,mazimkhan\/mbed-os,nRFMesh\/mbed-os,screamerbg\/mbed,bcostm\/mbed-os,NXPmicro\/mbed,fanghuaqi\/mbed","old_file":"targets\/TARGET_Freescale\/TARGET_MCUXpresso_MCUS\/TARGET_K66F\/device\/TOOLCHAIN_GCC_ARM\/MK66FN2M0xxx18.ld","new_file":"targets\/TARGET_Freescale\/TARGET_MCUXpresso_MCUS\/TARGET_K66F\/device\/TOOLCHAIN_GCC_ARM\/MK66FN2M0xxx18.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/netzimme\/mbed-os.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"efe690cab3fb5c5d710dec49c472df09eaaaa5da","subject":"BaseTools GCC: add unified GCC linker script for all archs and versions","message":"BaseTools GCC: add unified GCC linker script for all archs and versions\n\nThis unifies all GCC linker scripts into a single parametrised GCC\nlinker script that can be used for all GCC versions and architectures.\n\nThe two parameters that can be set on the linker command line are:\n- PECOFF_HEADER_SIZE, this is a build time property of GenFw, but\n  its value is different between 32-bit and 64-bit;\n- common-page-size, this can be set using -z on the ld command line,\n  and controls the value of the COMMONPAGESIZE constant when used in\n  a linker script. This value is used for the minimum section alignment.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>\nTested-by: Liming Gao <liming.gao@intel.com>\nTested-by: Leif Lindholm <leif.lindholm@linaro.org>\n\ngit-svn-id: 3158a46dfd52e07d1fda3e32e1ab2e353a00b20f@18135 6f19259b-4bc3-4df7-8a09-765794883524\n","repos":"MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2,MattDevo\/edk2","old_file":"BaseTools\/Scripts\/GccBase.lds","new_file":"BaseTools\/Scripts\/GccBase.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/MattDevo\/edk2.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"5e2624634cf122251f7fcc74f685779dc4f8601c","subject":"Fork boards\/st-stm32f303re-nucleo\/memory_map.ld to boards\/st-stm32l432kc-nucleo\/memory_map.ld step 3","message":"Fork boards\/st-stm32f303re-nucleo\/memory_map.ld to boards\/st-stm32l432kc-nucleo\/memory_map.ld step 3\n","repos":"bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn,bakerstu\/openmrn","old_file":"boards\/st-stm32l432kc-nucleo\/memory_map.ld","new_file":"boards\/st-stm32l432kc-nucleo\/memory_map.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/bakerstu\/openmrn.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"352f853803a64c1fd0a67ae449c236cb056783f5","subject":"nios2: add missing linker script","message":"nios2: add missing linker script\n\nGot lost in the .gitignore when these files had .cmd\nextension.\n\nChange-Id: I8a8d51014b621026b739525f3f9a3e8a20cb5ad0\nSigned-off-by: Andrew Boie <aab045b28152628be6af0e556050d0381fd0a34d@intel.com>\n","repos":"holtmann\/zephyr,bboozzoo\/zephyr,nashif\/zephyr,zephyriot\/zephyr,bboozzoo\/zephyr,fbsder\/zephyr,aceofall\/zephyr-iotos,bigdinotech\/zephyr,rsalveti\/zephyr,holtmann\/zephyr,holtmann\/zephyr,ldts\/zephyr,runchip\/zephyr-cc3220,kraj\/zephyr,punitvara\/zephyr,rsalveti\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3220,zephyriot\/zephyr,erwango\/zephyr,Vudentz\/zephyr,Vudentz\/zephyr,explora26\/zephyr,runchip\/zephyr-cc3200,zephyrproject-rtos\/zephyr,ldts\/zephyr,finikorg\/zephyr,Vudentz\/zephyr,punitvara\/zephyr,runchip\/zephyr-cc3200,zephyrproject-rtos\/zephyr,erwango\/zephyr,fbsder\/zephyr,rsalveti\/zephyr,galak\/zephyr,pklazy\/zephyr,fractalclone\/zephyr-riscv,finikorg\/zephyr,sharronliu\/zephyr,runchip\/zephyr-cc3220,holtmann\/zephyr,nashif\/zephyr,galak\/zephyr,kraj\/zephyr,explora26\/zephyr,pklazy\/zephyr,mirzak\/zephyr-os,mbolivar\/zephyr,Vudentz\/zephyr,fbsder\/zephyr,nashif\/zephyr,fbsder\/zephyr,kraj\/zephyr,zephyrproject-rtos\/zephyr,Vudentz\/zephyr,aceofall\/zephyr-iotos,ldts\/zephyr,rsalveti\/zephyr,sharronliu\/zephyr,ldts\/zephyr,runchip\/zephyr-cc3220,erwango\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,fractalclone\/zephyr-riscv,tidyjiang8\/zephyr-doc,mirzak\/zephyr-os,punitvara\/zephyr,explora26\/zephyr,aceofall\/zephyr-iotos,aceofall\/zephyr-iotos,fbsder\/zephyr,fractalclone\/zephyr-riscv,kraj\/zephyr,mirzak\/zephyr-os,bigdinotech\/zephyr,fractalclone\/zephyr-riscv,fractalclone\/zephyr-riscv,tidyjiang8\/zephyr-doc,mirzak\/zephyr-os,bboozzoo\/zephyr,explora26\/zephyr,runchip\/zephyr-cc3200,aceofall\/zephyr-iotos,bigdinotech\/zephyr,punitvara\/zephyr,GiulianoFranchetto\/zephyr,pklazy\/zephyr,bboozzoo\/zephyr,galak\/zephyr,mirzak\/zephyr-os,GiulianoFranchetto\/zephyr,bboozzoo\/zephyr,nashif\/zephyr,explora26\/zephyr,erwango\/zephyr,sharronliu\/zephyr,galak\/zephyr,bigdinotech\/zephyr,tidyjiang8\/zephyr-doc,galak\/zephyr,sharronliu\/zephyr,kraj\/zephyr,GiulianoFranchetto\/zephyr,mbolivar\/zephyr,holtmann\/zephyr,GiulianoFranchetto\/zephyr,tidyjiang8\/zephyr-doc,mbolivar\/zephyr,GiulianoFranchetto\/zephyr,erwango\/zephyr,punitvara\/zephyr,tidyjiang8\/zephyr-doc,bigdinotech\/zephyr,ldts\/zephyr,finikorg\/zephyr,mbolivar\/zephyr,runchip\/zephyr-cc3200,rsalveti\/zephyr,finikorg\/zephyr,mbolivar\/zephyr,Vudentz\/zephyr,pklazy\/zephyr,pklazy\/zephyr,sharronliu\/zephyr,zephyriot\/zephyr,zephyrproject-rtos\/zephyr,zephyriot\/zephyr,runchip\/zephyr-cc3200,runchip\/zephyr-cc3220,finikorg\/zephyr","old_file":"include\/arch\/nios2\/linker.ld","new_file":"include\/arch\/nios2\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/finikorg\/zephyr.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"35660f93f3807ae7bbe8d57586269cc07ec8181d","subject":"add missing underscoree","message":"add missing underscoree\n","repos":"ShawnHuang\/x86-kernel,SL-IDE\/saki,ashleygwilliams\/x86-kernel","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ashleygwilliams\/x86-kernel.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"ea2a55401770a2537201fa0795b46411c6c4acfc","subject":"src: actually add single linker script","message":"src: actually add single linker script\n","repos":"bwitherspoon\/core,bwitherspoon\/core","old_file":"src\/link.ld","new_file":"src\/link.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/bwitherspoon\/core.git\/': The requested URL returned error: 403\n","license":"isc","lang":"Linker Script"}
{"commit":"76f9a6e6ab51817272ce2b02f4de7e955485f4f9","subject":"hide symbols from statically linked stdlibc++","message":"hide symbols from statically linked stdlibc++\n","repos":"mapycz\/python-mapnik,mapycz\/python-mapnik","old_file":"debian\/mapnik.lds","new_file":"debian\/mapnik.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mapycz\/python-mapnik.git\/': GnuTLS recv error (-54): Error in the pull function.\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"d938faf6dce3d57f64276e6332d130607873340c","subject":"Forgot this one. BTW, library link scripts need to be factored out.","message":"Forgot this one. BTW, library link scripts need to be factored out.\n\n\ngit-svn-id: fb278a52ad97f7fbef074986829f2c6a2a3c4b34@525 c25cc9d1-44fa-0310-b259-ad778cb1d433\n","repos":"dioptre\/newos,siraj\/newos,zhouxh1023\/newos,siraj\/newos,dioptre\/newos,dioptre\/newos,travisg\/newos,zhouxh1023\/newos,zhouxh1023\/newos,travisg\/newos,travisg\/newos,siraj\/newos,siraj\/newos","old_file":"lib\/libm\/library.ld","new_file":"lib\/libm\/library.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/travisg\/newos.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"7a92b06fc41b42f64099c6115fc5f61bab5ff83c","subject":"Provide end symbol in RISC-V linker script","message":"Provide end symbol in RISC-V linker script\n\nThe kernel needs this symbol in order to know where it ends.\n","repos":"jeffreyrogers\/pv6,jeffreyrogers\/pv6,jeffreyrogers\/pv6","old_file":"scripts\/arch\/riscv\/kernel.ld","new_file":"scripts\/arch\/riscv\/kernel.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/jeffreyrogers\/pv6.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"2ed8bceec5a1d22d55b7ad545763643eee395c8b","subject":"Add symbol before critical loader data (need to keep until memory managment is ready)","message":"Add symbol before critical loader data (need to keep until memory managment is ready)\n","repos":"Tutul-\/tumuxOS,Tutul-\/tumuxOS,Tutul-\/tumuxOS","old_file":"src\/kernel\/arch\/x86\/linker.ld","new_file":"src\/kernel\/arch\/x86\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Tutul-\/tumuxOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"be30dcbb0b356449135e612449df67341fb78a2f","subject":"Fixed GCC ARM linker script for STM32L1  (STM32L152XE.ld)","message":"Fixed GCC ARM linker script for STM32L1  (STM32L152XE.ld)\n\nFixed Flash and RAM definitions in GCC ARM linker script for STM32L1\n(STM32L152XE.ld)\n","repos":"HeadsUpDisplayInc\/mbed,al177\/mbed,RonEld\/mbed,devanlai\/mbed,mazimkhan\/mbed-os,rgrover\/mbed,netzimme\/mbed-os,jferreir\/mbed,JasonHow44\/mbed,tung7970\/mbed-os,fanghuaqi\/mbed,kl-cruz\/mbed-os,nvlsianpu\/mbed,arostm\/mbed-os,Willem23\/mbed,svogl\/mbed-os,bikeNomad\/mbed,theotherjimmy\/mbed,catiedev\/mbed-os,NitinBhaskar\/mbed,mmorenobarm\/mbed-os,struempelix\/mbed,NXPmicro\/mbed,screamerbg\/mbed,JasonHow44\/mbed,Shengliang\/mbed,YarivCol\/mbed-os,bcostm\/mbed-os,monkiineko\/mbed-os,Shengliang\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,kl-cruz\/mbed-os,fanghuaqi\/mbed,tung7970\/mbed-os-1,cvtsi2sd\/mbed-os,naves-thiago\/mbed-midi,theotherjimmy\/mbed,al177\/mbed,DanKupiniak\/mbed,jrjang\/mbed,dbestm\/mbed,autopulated\/mbed,nRFMesh\/mbed-os,maximmbed\/mbed,screamerbg\/mbed,andcor02\/mbed-os,tung7970\/mbed-os,pi19404\/mbed,EmuxEvans\/mbed,logost\/mbed,Timmmm\/mbed,andreaslarssonublox\/mbed,mbedmicro\/mbed,masaohamanaka\/mbed,mnlipp\/mbed,nabilbendafi\/mbed,bikeNomad\/mbed,kl-cruz\/mbed-os,betzw\/mbed-os,cvtsi2sd\/mbed-os,kl-cruz\/mbed-os,JasonHow44\/mbed,betzw\/mbed-os,bentwire\/mbed,ryankurte\/mbed-os,kpurusho\/mbed,JasonHow44\/mbed,GustavWi\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,maximmbed\/mbed,rgrover\/mbed,DanKupiniak\/mbed,kl-cruz\/mbed-os,adustm\/mbed,pi19404\/mbed,bentwire\/mbed,CalSol\/mbed,theotherjimmy\/mbed,pbrook\/mbed,mikaleppanen\/mbed-os,karsev\/mbed-os,cvtsi2sd\/mbed-os,sam-geek\/mbed,cvtsi2sd\/mbed-os,pedromes\/mbed,nRFMesh\/mbed-os,fahhem\/mbed-os,K4zuki\/mbed,betzw\/mbed-os,ban4jp\/mbed,theotherjimmy\/mbed,ban4jp\/mbed,geky\/mbed,infinnovation\/mbed-os,sam-geek\/mbed,HeadsUpDisplayInc\/mbed,FranklyDev\/mbed,kjbracey-arm\/mbed,NitinBhaskar\/mbed,xcrespo\/mbed,netzimme\/mbed-os,tung7970\/mbed-os,jamesadevine\/mbed,Sweet-Peas\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,getopenmono\/mbed,autopulated\/mbed,adamgreen\/mbed,jeremybrodt\/mbed,ARM-software\/mbed-beetle,rosterloh\/mbed,bcostm\/mbed-os,K4zuki\/mbed,hwfwgrp\/mbed,j-greffe\/mbed-os,RonEld\/mbed,fvincenzo\/mbed-os,larks\/mbed,NitinBhaskar\/mbed,Marcomissyou\/mbed,masaohamanaka\/mbed,catiedev\/mbed-os,monkiineko\/mbed-os,mazimkhan\/mbed-os,geky\/mbed,svastm\/mbed,struempelix\/mbed,Tiryoh\/mbed,masaohamanaka\/mbed,hwfwgrp\/mbed,sam-geek\/mbed,jeremybrodt\/mbed,struempelix\/mbed,RonEld\/mbed,bcostm\/mbed-os,pedromes\/mbed,j-greffe\/mbed-os,nabilbendafi\/mbed,logost\/mbed,bulislaw\/mbed-os,netzimme\/mbed-os,Timmmm\/mbed,jferreir\/mbed,K4zuki\/mbed,pradeep-gr\/mbed-os5-onsemi,arostm\/mbed-os,jamesadevine\/mbed,bulislaw\/mbed-os,Shengliang\/mbed,pedromes\/mbed,struempelix\/mbed,pradeep-gr\/mbed-os5-onsemi,jrjang\/mbed,c1728p9\/mbed-os,adustm\/mbed,adustm\/mbed,pi19404\/mbed,jpbrucker\/mbed,brstew\/MBED-BUILD,alertby\/mbed,nRFMesh\/mbed-os,monkiineko\/mbed-os,wodji\/mbed,maximmbed\/mbed,Tiryoh\/mbed,fpiot\/mbed-ats,maximmbed\/mbed,catiedev\/mbed-os,nvlsianpu\/mbed,EmuxEvans\/mbed,autopulated\/mbed,pbrook\/mbed,arostm\/mbed-os,mnlipp\/mbed,bentwire\/mbed,YarivCol\/mbed-os,pradeep-gr\/mbed-os5-onsemi,fahhem\/mbed-os,Marcomissyou\/mbed,jeremybrodt\/mbed,ARM-software\/mbed-beetle,rosterloh\/mbed,larks\/mbed,screamerbg\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,Marcomissyou\/mbed,fahhem\/mbed-os,HeadsUpDisplayInc\/mbed,j-greffe\/mbed-os,JasonHow44\/mbed,mmorenobarm\/mbed-os,monkiineko\/mbed-os,jpbrucker\/mbed,theotherjimmy\/mbed,kpurusho\/mbed,jrjang\/mbed,andreaslarssonublox\/mbed,fpiot\/mbed-ats,fanghuaqi\/mbed,mbedmicro\/mbed,CalSol\/mbed,jferreir\/mbed,mikaleppanen\/mbed-os,logost\/mbed,mmorenobarm\/mbed-os,catiedev\/mbed-os,DanKupiniak\/mbed,nRFMesh\/mbed-os,nabilbendafi\/mbed,adamgreen\/mbed,kpurusho\/mbed,NXPmicro\/mbed,geky\/mbed,jpbrucker\/mbed,al177\/mbed,mnlipp\/mbed,pradeep-gr\/mbed-os5-onsemi,xcrespo\/mbed,getopenmono\/mbed,infinnovation\/mbed-os,fpiot\/mbed-ats,Willem23\/mbed,svogl\/mbed-os,Shengliang\/mbed,bikeNomad\/mbed,jamesadevine\/mbed,Shengliang\/mbed,YarivCol\/mbed-os,j-greffe\/mbed-os,pi19404\/mbed,c1728p9\/mbed-os,adustm\/mbed,K4zuki\/mbed,EmuxEvans\/mbed,hwfwgrp\/mbed,kjbracey-arm\/mbed,GustavWi\/mbed,jamesadevine\/mbed,c1728p9\/mbed-os,ban4jp\/mbed,al177\/mbed,arostm\/mbed-os,FranklyDev\/mbed,svastm\/mbed,fvincenzo\/mbed-os,adustm\/mbed,geky\/mbed,jamesadevine\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,nRFMesh\/mbed-os,CalSol\/mbed,masaohamanaka\/mbed,ban4jp\/mbed,pbrook\/mbed,FranklyDev\/mbed,GustavWi\/mbed,c1728p9\/mbed-os,jferreir\/mbed,YarivCol\/mbed-os,ban4jp\/mbed,Willem23\/mbed,arostm\/mbed-os,adamgreen\/mbed,dbestm\/mbed,mikaleppanen\/mbed-os,ryankurte\/mbed-os,karsev\/mbed-os,netzimme\/mbed-os,alertby\/mbed,andcor02\/mbed-os,wodji\/mbed,RonEld\/mbed,EmuxEvans\/mbed,arostm\/mbed-os,netzimme\/mbed-os,screamerbg\/mbed,nabilbendafi\/mbed,hwfwgrp\/mbed,bentwire\/mbed,fahhem\/mbed-os,Marcomissyou\/mbed,Willem23\/mbed,svastm\/mbed,nvlsianpu\/mbed,mazimkhan\/mbed-os,getopenmono\/mbed,pradeep-gr\/mbed-os5-onsemi,karsev\/mbed-os,NXPmicro\/mbed,larks\/mbed,fahhem\/mbed-os,hwfwgrp\/mbed,dbestm\/mbed,rgrover\/mbed,wodji\/mbed,netzimme\/mbed-os,monkiineko\/mbed-os,CalSol\/mbed,bulislaw\/mbed-os,RonEld\/mbed,rosterloh\/mbed,bcostm\/mbed-os,svogl\/mbed-os,kpurusho\/mbed,mmorenobarm\/mbed-os,andcor02\/mbed-os,jamesadevine\/mbed,sam-geek\/mbed,rosterloh\/mbed,brstew\/MBED-BUILD,rgrover\/mbed,ryankurte\/mbed-os,bikeNomad\/mbed,karsev\/mbed-os,adustm\/mbed,Archcady\/mbed-os,masaohamanaka\/mbed,andreaslarssonublox\/mbed,bulislaw\/mbed-os,struempelix\/mbed,Willem23\/mbed,sam-geek\/mbed,bulislaw\/mbed-os,pedromes\/mbed,fanghuaqi\/mbed,Marcomissyou\/mbed,betzw\/mbed-os,CalSol\/mbed,Tiryoh\/mbed,fvincenzo\/mbed-os,nabilbendafi\/mbed,masaohamanaka\/mbed,mnlipp\/mbed,kl-cruz\/mbed-os,YarivCol\/mbed-os,maximmbed\/mbed,karsev\/mbed-os,fvincenzo\/mbed-os,EmuxEvans\/mbed,fpiot\/mbed-ats,fpiot\/mbed-ats,struempelix\/mbed,Shengliang\/mbed,jeremybrodt\/mbed,j-greffe\/mbed-os,brstew\/MBED-BUILD,mmorenobarm\/mbed-os,tung7970\/mbed-os-1,naves-thiago\/mbed-midi,Archcady\/mbed-os,screamerbg\/mbed,jeremybrodt\/mbed,tung7970\/mbed-os,pbrook\/mbed,screamerbg\/mbed,ban4jp\/mbed,K4zuki\/mbed,autopulated\/mbed,pi19404\/mbed,Timmmm\/mbed,mikaleppanen\/mbed-os,fanghuaqi\/mbed,catiedev\/mbed-os,nvlsianpu\/mbed,larks\/mbed,pbrook\/mbed,jferreir\/mbed,jpbrucker\/mbed,dbestm\/mbed,bikeNomad\/mbed,pedromes\/mbed,devanlai\/mbed,mbedmicro\/mbed,j-greffe\/mbed-os,brstew\/MBED-BUILD,CalSol\/mbed,al177\/mbed,dbestm\/mbed,infinnovation\/mbed-os,catiedev\/mbed-os,ARM-software\/mbed-beetle,Archcady\/mbed-os,logost\/mbed,rosterloh\/mbed,jferreir\/mbed,xcrespo\/mbed,NitinBhaskar\/mbed,devanlai\/mbed,getopenmono\/mbed,bulislaw\/mbed-os,GustavWi\/mbed,al177\/mbed,xcrespo\/mbed,jrjang\/mbed,EmuxEvans\/mbed,naves-thiago\/mbed-midi,maximmbed\/mbed,adamgreen\/mbed,Sweet-Peas\/mbed,devanlai\/mbed,naves-thiago\/mbed-midi,nvlsianpu\/mbed,wodji\/mbed,fpiot\/mbed-ats,nabilbendafi\/mbed,Sweet-Peas\/mbed,mikaleppanen\/mbed-os,xcrespo\/mbed,logost\/mbed,andcor02\/mbed-os,svastm\/mbed,devanlai\/mbed,pi19404\/mbed,theotherjimmy\/mbed,Tiryoh\/mbed,HeadsUpDisplayInc\/mbed,c1728p9\/mbed-os,svogl\/mbed-os,fvincenzo\/mbed-os,geky\/mbed,Sweet-Peas\/mbed,NitinBhaskar\/mbed,ryankurte\/mbed-os,Timmmm\/mbed,mbedmicro\/mbed,bcostm\/mbed-os,tung7970\/mbed-os-1,andreaslarssonublox\/mbed,pradeep-gr\/mbed-os5-onsemi,getopenmono\/mbed,DanKupiniak\/mbed,pbrook\/mbed,xcrespo\/mbed,Sweet-Peas\/mbed,alertby\/mbed,adamgreen\/mbed,bentwire\/mbed,svogl\/mbed-os,infinnovation\/mbed-os,infinnovation\/mbed-os,adamgreen\/mbed,YarivCol\/mbed-os,brstew\/MBED-BUILD,andcor02\/mbed-os,kjbracey-arm\/mbed,Timmmm\/mbed,wodji\/mbed,jpbrucker\/mbed,rgrover\/mbed,larks\/mbed,NXPmicro\/mbed,Tiryoh\/mbed,mazimkhan\/mbed-os,NXPmicro\/mbed,alertby\/mbed,mazimkhan\/mbed-os,rosterloh\/mbed,andreaslarssonublox\/mbed,kpurusho\/mbed,larks\/mbed,mikaleppanen\/mbed-os,brstew\/MBED-BUILD,HeadsUpDisplayInc\/mbed,RonEld\/mbed,alertby\/mbed,jrjang\/mbed,bentwire\/mbed,Archcady\/mbed-os,GustavWi\/mbed,bcostm\/mbed-os,FranklyDev\/mbed,betzw\/mbed-os,jpbrucker\/mbed,ARM-software\/mbed-beetle,mnlipp\/mbed,tung7970\/mbed-os-1,jrjang\/mbed,K4zuki\/mbed,alertby\/mbed,infinnovation\/mbed-os,Marcomissyou\/mbed,autopulated\/mbed,nvlsianpu\/mbed,mnlipp\/mbed,HeadsUpDisplayInc\/mbed,naves-thiago\/mbed-midi,naves-thiago\/mbed-midi,nRFMesh\/mbed-os,Tiryoh\/mbed,monkiineko\/mbed-os,Archcady\/mbed-os,c1728p9\/mbed-os,JasonHow44\/mbed,ryankurte\/mbed-os,pedromes\/mbed,cvtsi2sd\/mbed-os,mazimkhan\/mbed-os,kpurusho\/mbed,fahhem\/mbed-os,tung7970\/mbed-os-1,wodji\/mbed,karsev\/mbed-os,andcor02\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,mmorenobarm\/mbed-os,logost\/mbed,tung7970\/mbed-os,dbestm\/mbed,betzw\/mbed-os,svogl\/mbed-os,svastm\/mbed,NXPmicro\/mbed,ryankurte\/mbed-os,Archcady\/mbed-os,hwfwgrp\/mbed,kjbracey-arm\/mbed,Timmmm\/mbed,mbedmicro\/mbed,Sweet-Peas\/mbed,getopenmono\/mbed,devanlai\/mbed,FranklyDev\/mbed,cvtsi2sd\/mbed-os,autopulated\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_STM32L1\/TARGET_NUCLEO_L152RE\/TOOLCHAIN_GCC_ARM\/STM32L152XE.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_STM32L1\/TARGET_NUCLEO_L152RE\/TOOLCHAIN_GCC_ARM\/STM32L152XE.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/nvlsianpu\/mbed.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"eb6a39973984058b3b70c7e267ce07b4bb674831","subject":"stm32_flash: Fill EEPROM section with 0xff.","message":"stm32_flash: Fill EEPROM section with 0xff.\n\nFilling it with 0x00 (the default) makes the virtual EEPROM code think\nthe sectors are depleted.\n\ngit-svn-id: 3db15d9df66343e7f944511864f914adee1f7549@2395 01035d8c-6547-0410-b346-abe4f91aad63\n","repos":"freedv\/codec2,freedv\/codec2,freedv\/codec2,freedv\/codec2","old_file":"stm32\/stm32_flash.ld","new_file":"stm32\/stm32_flash.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/freedv\/codec2.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"1ac5e5fbdd08f5e665dec07589b680792d88286a","subject":"Added nrf51 ac variant","message":"Added nrf51 ac variant\n","repos":"kYc0o\/RIOT,kerneltask\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,hamilton-mote\/RIOT-OS,thomaseichinger\/RIOT,Josar\/RIOT,gebart\/RIOT,OTAkeys\/RIOT,ant9000\/RIOT,brettswann\/RIOT,d00616\/RIOT,cladmi\/RIOT,LudwigOrtmann\/RIOT,rajma996\/RIOT,jbeyerstedt\/RIOT-OTA-update,plushvoxel\/RIOT,roberthartung\/RIOT,d00616\/RIOT,LudwigOrtmann\/RIOT,ks156\/RIOT,A-Paul\/RIOT,basilfx\/RIOT,Josar\/RIOT,thomaseichinger\/RIOT,hamilton-mote\/RIOT-OS,Josar\/RIOT,Hyungsin\/RIOT-OS,adrianghc\/RIOT,RIOT-OS\/RIOT,dkm\/RIOT,smlng\/RIOT,roberthartung\/RIOT,tfar\/RIOT,tfar\/RIOT,altairpearl\/RIOT,wentaoshang\/RIOT,kYc0o\/RIOT,LudwigOrtmann\/RIOT,beurdouche\/RIOT,adrianghc\/RIOT,brettswann\/RIOT,immesys\/RiSyn,tfar\/RIOT,adrianghc\/RIOT,wentaoshang\/RIOT,gautric\/RIOT,smlng\/RIOT,syin2\/RIOT,BytesGalore\/RIOT,mtausig\/RIOT,malosek\/RIOT,alignan\/RIOT,lazytech-org\/RIOT,rousselk\/RIOT,syin2\/RIOT,yogo1212\/RIOT,kb2ma\/RIOT,backenklee\/RIOT,yogo1212\/RIOT,rousselk\/RIOT,ant9000\/RIOT,alignan\/RIOT,avmelnikoff\/RIOT,jfischer-phytec-iot\/RIOT,BytesGalore\/RIOT,jremmert-phytec-iot\/RIOT,brettswann\/RIOT,neiljay\/RIOT,jremmert-phytec-iot\/RIOT,d00616\/RIOT,dailab\/RIOT,jremmert-phytec-iot\/RIOT,lazytech-org\/RIOT,backenklee\/RIOT,immesys\/RiSyn,LudwigKnuepfer\/RIOT,mtausig\/RIOT,josephnoir\/RIOT,kaleb-himes\/RIOT,adrianghc\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,OlegHahm\/RIOT,brettswann\/RIOT,josephnoir\/RIOT,toonst\/RIOT,authmillenon\/RIOT,jbeyerstedt\/RIOT-OTA-update,BytesGalore\/RIOT,wentaoshang\/RIOT,altairpearl\/RIOT,malosek\/RIOT,dkm\/RIOT,jfischer-phytec-iot\/RIOT,backenklee\/RIOT,mtausig\/RIOT,jfischer-phytec-iot\/RIOT,ks156\/RIOT,rousselk\/RIOT,kbumsik\/RIOT,jremmert-phytec-iot\/RIOT,aeneby\/RIOT,beurdouche\/RIOT,neiljay\/RIOT,plushvoxel\/RIOT,josephnoir\/RIOT,x3ro\/RIOT,malosek\/RIOT,kb2ma\/RIOT,neumodisch\/RIOT,zhuoshuguo\/RIOT,RIOT-OS\/RIOT,backenklee\/RIOT,immesys\/RiSyn,neumodisch\/RIOT,OlegHahm\/RIOT,katezilla\/RIOT,wentaoshang\/RIOT,neumodisch\/RIOT,miri64\/RIOT,kaspar030\/RIOT,mfrey\/RIOT,beurdouche\/RIOT,x3ro\/RIOT,josephnoir\/RIOT,jfischer-phytec-iot\/RIOT,A-Paul\/RIOT,neiljay\/RIOT,smlng\/RIOT,LudwigOrtmann\/RIOT,miri64\/RIOT,BytesGalore\/RIOT,Ell-i\/RIOT,Josar\/RIOT,Hyungsin\/RIOT-OS,altairpearl\/RIOT,A-Paul\/RIOT,jasonatran\/RIOT,rfuentess\/RIOT,miri64\/RIOT,dailab\/RIOT,ks156\/RIOT,kaspar030\/RIOT,dailab\/RIOT,avmelnikoff\/RIOT,rfuentess\/RIOT,Ell-i\/RIOT,rfuentess\/RIOT,immesys\/RiSyn,aeneby\/RIOT,basilfx\/RIOT,mfrey\/RIOT,rfuentess\/RIOT,ks156\/RIOT,biboc\/RIOT,malosek\/RIOT,adrianghc\/RIOT,LudwigKnuepfer\/RIOT,gautric\/RIOT,jbeyerstedt\/RIOT-OTA-update,kYc0o\/RIOT,TobiasFredersdorf\/RIOT,wentaoshang\/RIOT,adjih\/RIOT,plushvoxel\/RIOT,altairpearl\/RIOT,josephnoir\/RIOT,BytesGalore\/RIOT,gautric\/RIOT,adjih\/RIOT,lazytech-org\/RIOT,avmelnikoff\/RIOT,miri64\/RIOT,cladmi\/RIOT,jasonatran\/RIOT,biboc\/RIOT,rajma996\/RIOT,zhuoshuguo\/RIOT,Ell-i\/RIOT,kaleb-himes\/RIOT,jasonatran\/RIOT,immesys\/RiSyn,x3ro\/RIOT,jfischer-phytec-iot\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,altairpearl\/RIOT,kb2ma\/RIOT,yogo1212\/RIOT,thomaseichinger\/RIOT,zhuoshuguo\/RIOT,biboc\/RIOT,alignan\/RIOT,toonst\/RIOT,dkm\/RIOT,beurdouche\/RIOT,hamilton-mote\/RIOT-OS,Ell-i\/RIOT,kYc0o\/RIOT,Ell-i\/RIOT,syin2\/RIOT,adjih\/RIOT,jbeyerstedt\/RIOT-OTA-update,katezilla\/RIOT,d00616\/RIOT,A-Paul\/RIOT,rousselk\/RIOT,immesys\/RiSyn,zhuoshuguo\/RIOT,basilfx\/RIOT,mtausig\/RIOT,gebart\/RIOT,malosek\/RIOT,mfrey\/RIOT,dailab\/RIOT,OTAkeys\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,jremmert-phytec-iot\/RIOT,Hyungsin\/RIOT-OS,roberthartung\/RIOT,kerneltask\/RIOT,authmillenon\/RIOT,cladmi\/RIOT,LudwigKnuepfer\/RIOT,cladmi\/RIOT,beurdouche\/RIOT,syin2\/RIOT,lazytech-org\/RIOT,brettswann\/RIOT,katezilla\/RIOT,gautric\/RIOT,RIOT-OS\/RIOT,gautric\/RIOT,kb2ma\/RIOT,avmelnikoff\/RIOT,jbeyerstedt\/RIOT-OTA-update,ks156\/RIOT,rousselk\/RIOT,malosek\/RIOT,dkm\/RIOT,OTAkeys\/RIOT,TobiasFredersdorf\/RIOT,x3ro\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,neumodisch\/RIOT,kerneltask\/RIOT,LudwigOrtmann\/RIOT,toonst\/RIOT,kaspar030\/RIOT,jasonatran\/RIOT,toonst\/RIOT,smlng\/RIOT,rajma996\/RIOT,rousselk\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,adjih\/RIOT,rajma996\/RIOT,ant9000\/RIOT,d00616\/RIOT,kb2ma\/RIOT,rajma996\/RIOT,alignan\/RIOT,hamilton-mote\/RIOT-OS,authmillenon\/RIOT,syin2\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,rajma996\/RIOT,zhuoshuguo\/RIOT,LudwigOrtmann\/RIOT,ant9000\/RIOT,yogo1212\/RIOT,tfar\/RIOT,tfar\/RIOT,smlng\/RIOT,brettswann\/RIOT,OTAkeys\/RIOT,gebart\/RIOT,kerneltask\/RIOT,wentaoshang\/RIOT,cladmi\/RIOT,neiljay\/RIOT,kbumsik\/RIOT,ant9000\/RIOT,kbumsik\/RIOT,roberthartung\/RIOT,biboc\/RIOT,zhuoshuguo\/RIOT,aeneby\/RIOT,d00616\/RIOT,TobiasFredersdorf\/RIOT,kaleb-himes\/RIOT,authmillenon\/RIOT,kerneltask\/RIOT,Hyungsin\/RIOT-OS,basilfx\/RIOT,thomaseichinger\/RIOT,jremmert-phytec-iot\/RIOT,dkm\/RIOT,x3ro\/RIOT,mfrey\/RIOT,altairpearl\/RIOT,alignan\/RIOT,OTAkeys\/RIOT,kbumsik\/RIOT,katezilla\/RIOT,kaspar030\/RIOT,yogo1212\/RIOT,avmelnikoff\/RIOT,adjih\/RIOT,authmillenon\/RIOT,aeneby\/RIOT,neumodisch\/RIOT,TobiasFredersdorf\/RIOT,Hyungsin\/RIOT-OS,neumodisch\/RIOT,kaspar030\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,OlegHahm\/RIOT,mfrey\/RIOT,kYc0o\/RIOT,plushvoxel\/RIOT,RIOT-OS\/RIOT,gebart\/RIOT,katezilla\/RIOT,kaleb-himes\/RIOT,mtausig\/RIOT,neiljay\/RIOT,gebart\/RIOT,TobiasFredersdorf\/RIOT,roberthartung\/RIOT,aeneby\/RIOT,LudwigKnuepfer\/RIOT,basilfx\/RIOT,toonst\/RIOT,kaleb-himes\/RIOT,lazytech-org\/RIOT,backenklee\/RIOT,kbumsik\/RIOT,A-Paul\/RIOT,dailab\/RIOT,hamilton-mote\/RIOT-OS,LudwigKnuepfer\/RIOT,biboc\/RIOT,plushvoxel\/RIOT,Josar\/RIOT,thomaseichinger\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT","old_file":"cpu\/nrf51\/ldscripts\/nrf51x22xxac.ld","new_file":"cpu\/nrf51\/ldscripts\/nrf51x22xxac.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"dfcb2c680f59bcde8de1d3f0025a37285614004a","subject":"Nordic: update application start address in GCC linker script","message":"Nordic: update application start address in GCC linker script\n\nThe S110 linker script is still using start address 0x16000, which was\nrequired by version 7.1 of the s110 SoftDevice. Update it to the current\naddress, required by S110 v8.0.0.\n","repos":"getopenmono\/mbed,catiedev\/mbed-os,Shengliang\/mbed,betzw\/mbed-os,Timmmm\/mbed,c1728p9\/mbed-os,devanlai\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,svogl\/mbed-os,larks\/mbed,fanghuaqi\/mbed,pbrook\/mbed,Tiryoh\/mbed,dbestm\/mbed,tung7970\/mbed-os-1,fanghuaqi\/mbed,pedromes\/mbed,jeremybrodt\/mbed,netzimme\/mbed-os,jpbrucker\/mbed,arostm\/mbed-os,netzimme\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,rgrover\/mbed,Timmmm\/mbed,kjbracey-arm\/mbed,catiedev\/mbed-os,j-greffe\/mbed-os,EmuxEvans\/mbed,Tiryoh\/mbed,struempelix\/mbed,karsev\/mbed-os,dbestm\/mbed,mbedmicro\/mbed,Tiryoh\/mbed,K4zuki\/mbed,andcor02\/mbed-os,mnlipp\/mbed,kl-cruz\/mbed-os,al177\/mbed,kpurusho\/mbed,adustm\/mbed,svogl\/mbed-os,jeremybrodt\/mbed,mmorenobarm\/mbed-os,adustm\/mbed,arostm\/mbed-os,monkiineko\/mbed-os,bikeNomad\/mbed,CalSol\/mbed,YarivCol\/mbed-os,masaohamanaka\/mbed,andcor02\/mbed-os,tung7970\/mbed-os,Shengliang\/mbed,mikaleppanen\/mbed-os,brstew\/MBED-BUILD,jpbrucker\/mbed,ryankurte\/mbed-os,c1728p9\/mbed-os,svastm\/mbed,netzimme\/mbed-os,mikaleppanen\/mbed-os,masaohamanaka\/mbed,bcostm\/mbed-os,nabilbendafi\/mbed,kjbracey-arm\/mbed,adustm\/mbed,fpiot\/mbed-ats,kl-cruz\/mbed-os,Timmmm\/mbed,netzimme\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,Shengliang\/mbed,pedromes\/mbed,bikeNomad\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,adamgreen\/mbed,karsev\/mbed-os,CalSol\/mbed,nvlsianpu\/mbed,kl-cruz\/mbed-os,hwfwgrp\/mbed,EmuxEvans\/mbed,geky\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,theotherjimmy\/mbed,getopenmono\/mbed,mnlipp\/mbed,ARM-software\/mbed-beetle,arostm\/mbed-os,K4zuki\/mbed,monkiineko\/mbed-os,tung7970\/mbed-os,maximmbed\/mbed,infinnovation\/mbed-os,CalSol\/mbed,al177\/mbed,mazimkhan\/mbed-os,mikaleppanen\/mbed-os,betzw\/mbed-os,mikaleppanen\/mbed-os,Tiryoh\/mbed,dbestm\/mbed,struempelix\/mbed,brstew\/MBED-BUILD,jpbrucker\/mbed,wodji\/mbed,tung7970\/mbed-os-1,cvtsi2sd\/mbed-os,fvincenzo\/mbed-os,kpurusho\/mbed,pi19404\/mbed,svastm\/mbed,infinnovation\/mbed-os,netzimme\/mbed-os,svogl\/mbed-os,monkiineko\/mbed-os,infinnovation\/mbed-os,screamerbg\/mbed,ryankurte\/mbed-os,pradeep-gr\/mbed-os5-onsemi,brstew\/MBED-BUILD,adamgreen\/mbed,al177\/mbed,infinnovation\/mbed-os,RonEld\/mbed,dbestm\/mbed,kpurusho\/mbed,bulislaw\/mbed-os,jpbrucker\/mbed,YarivCol\/mbed-os,Archcady\/mbed-os,bulislaw\/mbed-os,rgrover\/mbed,pradeep-gr\/mbed-os5-onsemi,EmuxEvans\/mbed,mazimkhan\/mbed-os,betzw\/mbed-os,karsev\/mbed-os,pedromes\/mbed,hwfwgrp\/mbed,adamgreen\/mbed,karsev\/mbed-os,hwfwgrp\/mbed,pradeep-gr\/mbed-os5-onsemi,bentwire\/mbed,bentwire\/mbed,HeadsUpDisplayInc\/mbed,andcor02\/mbed-os,fahhem\/mbed-os,RonEld\/mbed,bentwire\/mbed,mmorenobarm\/mbed-os,jeremybrodt\/mbed,infinnovation\/mbed-os,mnlipp\/mbed,dbestm\/mbed,K4zuki\/mbed,larks\/mbed,tung7970\/mbed-os,mbedmicro\/mbed,mazimkhan\/mbed-os,DanKupiniak\/mbed,getopenmono\/mbed,andreaslarssonublox\/mbed,devanlai\/mbed,andreaslarssonublox\/mbed,rosterloh\/mbed,andcor02\/mbed-os,netzimme\/mbed-os,mikaleppanen\/mbed-os,tung7970\/mbed-os,screamerbg\/mbed,Timmmm\/mbed,mbedmicro\/mbed,hwfwgrp\/mbed,betzw\/mbed-os,getopenmono\/mbed,DanKupiniak\/mbed,fpiot\/mbed-ats,jeremybrodt\/mbed,K4zuki\/mbed,nvlsianpu\/mbed,struempelix\/mbed,jrjang\/mbed,ryankurte\/mbed-os,pbrook\/mbed,RonEld\/mbed,fvincenzo\/mbed-os,rosterloh\/mbed,nRFMesh\/mbed-os,NXPmicro\/mbed,wodji\/mbed,kjbracey-arm\/mbed,c1728p9\/mbed-os,maximmbed\/mbed,pi19404\/mbed,brstew\/MBED-BUILD,svastm\/mbed,Archcady\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,andreaslarssonublox\/mbed,pedromes\/mbed,hwfwgrp\/mbed,mmorenobarm\/mbed-os,ARM-software\/mbed-beetle,c1728p9\/mbed-os,Archcady\/mbed-os,nabilbendafi\/mbed,masaohamanaka\/mbed,pi19404\/mbed,NXPmicro\/mbed,svastm\/mbed,kjbracey-arm\/mbed,bcostm\/mbed-os,ARM-software\/mbed-beetle,mnlipp\/mbed,devanlai\/mbed,getopenmono\/mbed,mbedmicro\/mbed,pradeep-gr\/mbed-os5-onsemi,wodji\/mbed,adustm\/mbed,tung7970\/mbed-os-1,Tiryoh\/mbed,geky\/mbed,nvlsianpu\/mbed,pbrook\/mbed,HeadsUpDisplayInc\/mbed,monkiineko\/mbed-os,pradeep-gr\/mbed-os5-onsemi,EmuxEvans\/mbed,Timmmm\/mbed,kl-cruz\/mbed-os,jferreir\/mbed,maximmbed\/mbed,theotherjimmy\/mbed,jrjang\/mbed,cvtsi2sd\/mbed-os,fanghuaqi\/mbed,bcostm\/mbed-os,pedromes\/mbed,larks\/mbed,rosterloh\/mbed,andreaslarssonublox\/mbed,al177\/mbed,Tiryoh\/mbed,HeadsUpDisplayInc\/mbed,j-greffe\/mbed-os,nRFMesh\/mbed-os,fvincenzo\/mbed-os,jferreir\/mbed,masaohamanaka\/mbed,jrjang\/mbed,masaohamanaka\/mbed,screamerbg\/mbed,bikeNomad\/mbed,svogl\/mbed-os,pi19404\/mbed,betzw\/mbed-os,andcor02\/mbed-os,catiedev\/mbed-os,autopulated\/mbed,Archcady\/mbed-os,wodji\/mbed,theotherjimmy\/mbed,betzw\/mbed-os,devanlai\/mbed,HeadsUpDisplayInc\/mbed,j-greffe\/mbed-os,pradeep-gr\/mbed-os5-onsemi,bcostm\/mbed-os,struempelix\/mbed,jferreir\/mbed,mbedmicro\/mbed,mmorenobarm\/mbed-os,Shengliang\/mbed,fpiot\/mbed-ats,geky\/mbed,fahhem\/mbed-os,adamgreen\/mbed,nRFMesh\/mbed-os,kpurusho\/mbed,bikeNomad\/mbed,RonEld\/mbed,tung7970\/mbed-os,K4zuki\/mbed,pi19404\/mbed,devanlai\/mbed,HeadsUpDisplayInc\/mbed,monkiineko\/mbed-os,HeadsUpDisplayInc\/mbed,nvlsianpu\/mbed,monkiineko\/mbed-os,nabilbendafi\/mbed,theotherjimmy\/mbed,catiedev\/mbed-os,arostm\/mbed-os,adamgreen\/mbed,bentwire\/mbed,nabilbendafi\/mbed,bentwire\/mbed,svogl\/mbed-os,jferreir\/mbed,struempelix\/mbed,CalSol\/mbed,screamerbg\/mbed,Shengliang\/mbed,kpurusho\/mbed,hwfwgrp\/mbed,fpiot\/mbed-ats,struempelix\/mbed,nRFMesh\/mbed-os,nabilbendafi\/mbed,adamgreen\/mbed,NXPmicro\/mbed,cvtsi2sd\/mbed-os,wodji\/mbed,nRFMesh\/mbed-os,screamerbg\/mbed,mazimkhan\/mbed-os,j-greffe\/mbed-os,ryankurte\/mbed-os,fahhem\/mbed-os,autopulated\/mbed,theotherjimmy\/mbed,jrjang\/mbed,K4zuki\/mbed,fahhem\/mbed-os,cvtsi2sd\/mbed-os,tung7970\/mbed-os-1,infinnovation\/mbed-os,fpiot\/mbed-ats,jeremybrodt\/mbed,YarivCol\/mbed-os,kl-cruz\/mbed-os,tung7970\/mbed-os-1,getopenmono\/mbed,j-greffe\/mbed-os,karsev\/mbed-os,Archcady\/mbed-os,RonEld\/mbed,maximmbed\/mbed,andcor02\/mbed-os,c1728p9\/mbed-os,NXPmicro\/mbed,fanghuaqi\/mbed,jpbrucker\/mbed,mazimkhan\/mbed-os,CalSol\/mbed,Timmmm\/mbed,maximmbed\/mbed,autopulated\/mbed,dbestm\/mbed,DanKupiniak\/mbed,nvlsianpu\/mbed,rosterloh\/mbed,svogl\/mbed-os,j-greffe\/mbed-os,pbrook\/mbed,al177\/mbed,bcostm\/mbed-os,autopulated\/mbed,larks\/mbed,jferreir\/mbed,pedromes\/mbed,karsev\/mbed-os,bulislaw\/mbed-os,fpiot\/mbed-ats,cvtsi2sd\/mbed-os,fahhem\/mbed-os,pbrook\/mbed,jrjang\/mbed,theotherjimmy\/mbed,YarivCol\/mbed-os,kpurusho\/mbed,c1728p9\/mbed-os,maximmbed\/mbed,kl-cruz\/mbed-os,adustm\/mbed,mazimkhan\/mbed-os,rgrover\/mbed,DanKupiniak\/mbed,larks\/mbed,NXPmicro\/mbed,jrjang\/mbed,bikeNomad\/mbed,mmorenobarm\/mbed-os,rosterloh\/mbed,nvlsianpu\/mbed,rgrover\/mbed,bulislaw\/mbed-os,jferreir\/mbed,mikaleppanen\/mbed-os,al177\/mbed,brstew\/MBED-BUILD,ryankurte\/mbed-os,bulislaw\/mbed-os,fvincenzo\/mbed-os,cvtsi2sd\/mbed-os,bentwire\/mbed,svastm\/mbed,YarivCol\/mbed-os,rgrover\/mbed,Shengliang\/mbed,geky\/mbed,EmuxEvans\/mbed,Archcady\/mbed-os,mnlipp\/mbed,catiedev\/mbed-os,fahhem\/mbed-os,EmuxEvans\/mbed,CalSol\/mbed,adustm\/mbed,autopulated\/mbed,fanghuaqi\/mbed,pi19404\/mbed,autopulated\/mbed,ARM-software\/mbed-beetle,andreaslarssonublox\/mbed,catiedev\/mbed-os,NXPmicro\/mbed,nRFMesh\/mbed-os,larks\/mbed,masaohamanaka\/mbed,wodji\/mbed,bcostm\/mbed-os,YarivCol\/mbed-os,rosterloh\/mbed,devanlai\/mbed,mmorenobarm\/mbed-os,arostm\/mbed-os,mnlipp\/mbed,brstew\/MBED-BUILD,ryankurte\/mbed-os,screamerbg\/mbed,geky\/mbed,pbrook\/mbed,nabilbendafi\/mbed,fvincenzo\/mbed-os,arostm\/mbed-os,jpbrucker\/mbed,RonEld\/mbed,bulislaw\/mbed-os","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NORDIC\/TARGET_MCU_NRF51822\/TOOLCHAIN_GCC_ARM\/TARGET_MCU_NRF51_16K_S110\/NRF51822.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_NORDIC\/TARGET_MCU_NRF51822\/TOOLCHAIN_GCC_ARM\/TARGET_MCU_NRF51_16K_S110\/NRF51822.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/nvlsianpu\/mbed.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"ca2cf6cc394ca056c6f42605e0720f1258d2f743","subject":"playground\/oses\/rust-os\/handwork\/linker.ld","message":"playground\/oses\/rust-os\/handwork\/linker.ld\n","repos":"sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis","old_file":"playground\/oses\/rust-os\/handwork\/linker.ld","new_file":"playground\/oses\/rust-os\/handwork\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/sharkspeed\/dororis.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"14e4afd2f8d444f26dd16f6b0620f1225c9446e7","subject":"Fix linker file","message":"Fix linker file\n\nPadding to 4KB?! No thanks..\n","repos":"ReturnInfinity\/Alloy,ReturnInfinity\/Alloy","old_file":"app.ld","new_file":"app.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ReturnInfinity\/Alloy.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"66200b3fad4fc8f836cc3d5ef3545fe2ee6ab2cb","subject":"Use the correct dtb section declaration","message":"Use the correct dtb section declaration\n","repos":"kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa","old_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kalray\/odp-mppa.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"d2a37caf9c00f8b0de7a7a307ff5b1f40a49b0c0","subject":"add microbit_v2 layout","message":"add microbit_v2 layout\n","repos":"tock\/libtock-rs","old_file":"runtime\/layouts\/microbit_v2.ld","new_file":"runtime\/layouts\/microbit_v2.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/tock\/libtock-rs.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"e8daf349fa7b6eba1a5b3b25ae8f32079ce5506d","subject":"linker script fix for stress test wip commit","message":"linker script fix for stress test wip commit\n","repos":"origintfj\/riscv","old_file":"rv32i\/verif\/link.ld","new_file":"rv32i\/verif\/link.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/origintfj\/riscv.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"040edcf7e94817b0a8444bc3cbb4d942f75378c0","subject":"arduino due version still under construction, pieces are missing","message":"arduino due version still under construction, pieces are missing\n","repos":"980f\/dro,980f\/dro,980f\/dro,980f\/dro","old_file":"sam3\/sam3x8e.ld","new_file":"sam3\/sam3x8e.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/980f\/dro.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"4a987dacca4760aed96c505a363ffde52405ff91","subject":"bootloader: keep bootloader_common code to retention region","message":"bootloader: keep bootloader_common code to retention region\n\nIt is possible to utilize some of the routines related to otadata\npartition validation, after firmware image is downloaded to RAM. Hence\nthese routines should be part of app cpu cache, so that they do not\nget overwritten by firmware.\n\nSigned-off-by: Mahavir Jain <9c73e8379fd97c516d9a7b9d112e2d11ad3c8e4a@espressif.com>\n","repos":"mashaoze\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,www220\/esp-idf,espressif\/esp-idf,www220\/esp-idf,www220\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf,armada-ai\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf,mashaoze\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/esp32.bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/esp32.bootloader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mashaoze\/esp-idf.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"759b75a5e9a964b0caaea993dedf4bbc4cde47f1","subject":"\u65b0\u3057\u3044\u30ea\u30f3\u30ab\u30b9\u30af\u30ea\u30d7\u30c8\u3092\u8ffd\u52a0","message":"\u65b0\u3057\u3044\u30ea\u30f3\u30ab\u30b9\u30af\u30ea\u30d7\u30c8\u3092\u8ffd\u52a0\n","repos":"AkihiroTakai\/yuri,AkihiroTakai\/yuri,AkihiroTakai\/yuri","old_file":"ls\/appyx.lds","new_file":"ls\/appyx.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/AkihiroTakai\/yuri.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"d968bd5de19678de5d0b44b95bad583f523596b0","subject":"load and run from flash","message":"load and run from flash\n","repos":"ppwwyyxx\/tensorflow,ghchinoy\/tensorflow,adit-chandra\/tensorflow,yongtang\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,jbedorf\/tensorflow,alsrgv\/tensorflow,yongtang\/tensorflow,jbedorf\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,arborh\/tensorflow,xzturn\/tensorflow,alsrgv\/tensorflow,yongtang\/tensorflow,jbedorf\/tensorflow,ageron\/tensorflow,DavidNorman\/tensorflow,renyi533\/tensorflow,kevin-coder\/tensorflow-fork,petewarden\/tensorflow,karllessard\/tensorflow,ghchinoy\/tensorflow,aam-at\/tensorflow,xzturn\/tensorflow,chemelnucfin\/tensorflow,ageron\/tensorflow,alsrgv\/tensorflow,gautam1858\/tensorflow,xzturn\/tensorflow,arborh\/tensorflow,adit-chandra\/tensorflow,DavidNorman\/tensorflow,gunan\/tensorflow,gunan\/tensorflow,yongtang\/tensorflow,alsrgv\/tensorflow,petewarden\/tensorflow,karllessard\/tensorflow,xzturn\/tensorflow,frreiss\/tensorflow-fred,paolodedios\/tensorflow,paolodedios\/tensorflow,renyi533\/tensorflow,Intel-Corporation\/tensorflow,jhseu\/tensorflow,ppwwyyxx\/tensorflow,gunan\/tensorflow,gunan\/tensorflow,arborh\/tensorflow,annarev\/tensorflow,paolodedios\/tensorflow,kevin-coder\/tensorflow-fork,Intel-tensorflow\/tensorflow,xzturn\/tensorflow,adit-chandra\/tensorflow,karllessard\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,chemelnucfin\/tensorflow,kevin-coder\/tensorflow-fork,DavidNorman\/tensorflow,sarvex\/tensorflow,DavidNorman\/tensorflow,aam-at\/tensorflow,ghchinoy\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,alsrgv\/tensorflow,theflofly\/tensorflow,arborh\/tensorflow,Intel-tensorflow\/tensorflow,jhseu\/tensorflow,jhseu\/tensorflow,freedomtan\/tensorflow,renyi533\/tensorflow,jhseu\/tensorflow,Intel-Corporation\/tensorflow,DavidNorman\/tensorflow,ppwwyyxx\/tensorflow,jbedorf\/tensorflow,tensorflow\/tensorflow,petewarden\/tensorflow,jhseu\/tensorflow,renyi533\/tensorflow,chemelnucfin\/tensorflow,DavidNorman\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,ageron\/tensorflow,aam-at\/tensorflow,adit-chandra\/tensorflow,karllessard\/tensorflow,karllessard\/tensorflow,arborh\/tensorflow,aldian\/tensorflow,adit-chandra\/tensorflow,gunan\/tensorflow,renyi533\/tensorflow,ghchinoy\/tensorflow,frreiss\/tensorflow-fred,jhseu\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,chemelnucfin\/tensorflow,chemelnucfin\/tensorflow,yongtang\/tensorflow,adit-chandra\/tensorflow,freedomtan\/tensorflow,cxxgtxy\/tensorflow,annarev\/tensorflow,petewarden\/tensorflow,davidzchen\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,theflofly\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,gunan\/tensorflow,paolodedios\/tensorflow,frreiss\/tensorflow-fred,ageron\/tensorflow,xzturn\/tensorflow,paolodedios\/tensorflow,davidzchen\/tensorflow,aldian\/tensorflow,freedomtan\/tensorflow,davidzchen\/tensorflow,karllessard\/tensorflow,kevin-coder\/tensorflow-fork,kevin-coder\/tensorflow-fork,gunan\/tensorflow,jbedorf\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,annarev\/tensorflow,alsrgv\/tensorflow,DavidNorman\/tensorflow,DavidNorman\/tensorflow,yongtang\/tensorflow,aam-at\/tensorflow,jbedorf\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,frreiss\/tensorflow-fred,arborh\/tensorflow,gautam1858\/tensorflow,aam-at\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow,annarev\/tensorflow,gautam1858\/tensorflow,karllessard\/tensorflow,alsrgv\/tensorflow,ageron\/tensorflow,ageron\/tensorflow,cxxgtxy\/tensorflow,frreiss\/tensorflow-fred,ghchinoy\/tensorflow,alsrgv\/tensorflow,DavidNorman\/tensorflow,jbedorf\/tensorflow,gautam1858\/tensorflow,ppwwyyxx\/tensorflow,gunan\/tensorflow,annarev\/tensorflow,sarvex\/tensorflow,paolodedios\/tensorflow,jbedorf\/tensorflow,frreiss\/tensorflow-fred,chemelnucfin\/tensorflow,Intel-tensorflow\/tensorflow,arborh\/tensorflow,aldian\/tensorflow,chemelnucfin\/tensorflow,kevin-coder\/tensorflow-fork,karllessard\/tensorflow,DavidNorman\/tensorflow,paolodedios\/tensorflow,paolodedios\/tensorflow,freedomtan\/tensorflow,jbedorf\/tensorflow,ageron\/tensorflow,alsrgv\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,renyi533\/tensorflow,davidzchen\/tensorflow,kevin-coder\/tensorflow-fork,ghchinoy\/tensorflow,aam-at\/tensorflow,cxxgtxy\/tensorflow,tensorflow\/tensorflow,alsrgv\/tensorflow,annarev\/tensorflow,theflofly\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,xzturn\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,yongtang\/tensorflow,aldian\/tensorflow,theflofly\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,renyi533\/tensorflow,Intel-Corporation\/tensorflow,frreiss\/tensorflow-fred,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_tf_optimizer,jbedorf\/tensorflow,karllessard\/tensorflow,petewarden\/tensorflow,theflofly\/tensorflow,gunan\/tensorflow,gautam1858\/tensorflow,renyi533\/tensorflow,petewarden\/tensorflow,theflofly\/tensorflow,ageron\/tensorflow,arborh\/tensorflow,gautam1858\/tensorflow,adit-chandra\/tensorflow,theflofly\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,davidzchen\/tensorflow,ghchinoy\/tensorflow,davidzchen\/tensorflow,ghchinoy\/tensorflow,adit-chandra\/tensorflow,ppwwyyxx\/tensorflow,gautam1858\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-tensorflow\/tensorflow,jbedorf\/tensorflow,xzturn\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,ageron\/tensorflow,DavidNorman\/tensorflow,freedomtan\/tensorflow,kevin-coder\/tensorflow-fork,yongtang\/tensorflow,theflofly\/tensorflow,renyi533\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,alsrgv\/tensorflow,jhseu\/tensorflow,aldian\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,davidzchen\/tensorflow,adit-chandra\/tensorflow,aldian\/tensorflow,kevin-coder\/tensorflow-fork,tensorflow\/tensorflow-pywrap_tf_optimizer,ppwwyyxx\/tensorflow,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,xzturn\/tensorflow,ghchinoy\/tensorflow,gautam1858\/tensorflow,kevin-coder\/tensorflow-fork,freedomtan\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,frreiss\/tensorflow-fred,chemelnucfin\/tensorflow,cxxgtxy\/tensorflow,yongtang\/tensorflow,aam-at\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,arborh\/tensorflow,renyi533\/tensorflow,petewarden\/tensorflow,jhseu\/tensorflow,paolodedios\/tensorflow,ageron\/tensorflow,ageron\/tensorflow,Intel-Corporation\/tensorflow,arborh\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,jhseu\/tensorflow,gautam1858\/tensorflow,jhseu\/tensorflow,chemelnucfin\/tensorflow,tensorflow\/tensorflow,davidzchen\/tensorflow,chemelnucfin\/tensorflow,ppwwyyxx\/tensorflow,petewarden\/tensorflow,chemelnucfin\/tensorflow,renyi533\/tensorflow,aam-at\/tensorflow,Intel-tensorflow\/tensorflow,ageron\/tensorflow,davidzchen\/tensorflow,karllessard\/tensorflow,theflofly\/tensorflow,gunan\/tensorflow,cxxgtxy\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,ghchinoy\/tensorflow,DavidNorman\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,annarev\/tensorflow,cxxgtxy\/tensorflow,aam-at\/tensorflow,Intel-Corporation\/tensorflow,theflofly\/tensorflow,cxxgtxy\/tensorflow,Intel-tensorflow\/tensorflow,arborh\/tensorflow,karllessard\/tensorflow,aldian\/tensorflow,jhseu\/tensorflow,freedomtan\/tensorflow,theflofly\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,kevin-coder\/tensorflow-fork,jbedorf\/tensorflow,yongtang\/tensorflow,sarvex\/tensorflow,davidzchen\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow,davidzchen\/tensorflow,freedomtan\/tensorflow,frreiss\/tensorflow-fred,adit-chandra\/tensorflow,paolodedios\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,ppwwyyxx\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,sarvex\/tensorflow,Intel-tensorflow\/tensorflow,chemelnucfin\/tensorflow,xzturn\/tensorflow,sarvex\/tensorflow,Intel-tensorflow\/tensorflow,adit-chandra\/tensorflow,theflofly\/tensorflow,xzturn\/tensorflow,petewarden\/tensorflow,davidzchen\/tensorflow,ppwwyyxx\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow,arborh\/tensorflow,ppwwyyxx\/tensorflow,ghchinoy\/tensorflow,gautam1858\/tensorflow,annarev\/tensorflow,xzturn\/tensorflow,gunan\/tensorflow,frreiss\/tensorflow-fred,freedomtan\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,annarev\/tensorflow,petewarden\/tensorflow,renyi533\/tensorflow,alsrgv\/tensorflow,annarev\/tensorflow,gunan\/tensorflow,adit-chandra\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,aam-at\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,annarev\/tensorflow,Intel-Corporation\/tensorflow,ghchinoy\/tensorflow,jhseu\/tensorflow,freedomtan\/tensorflow,aldian\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow","old_file":"tensorflow\/lite\/experimental\/micro\/tools\/make\/targets\/ecm3531\/ecm3531_flash.lds","new_file":"tensorflow\/lite\/experimental\/micro\/tools\/make\/targets\/ecm3531\/ecm3531_flash.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ageron\/tensorflow.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9fb60f7c3f2eca2f3f047aba66c0b82fdae77b0f","subject":"Linker script added","message":"Linker script added\n","repos":"rksdna\/swamp-m3","old_file":"kernel\/target\/stm32f103xc.ld","new_file":"kernel\/target\/stm32f103xc.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/rksdna\/swamp-m3.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"357c6bd7a5734bdb6dcf0edf62fd25c04c7f69b5","subject":"Initial linker script for raspberry pi","message":"Initial linker script for raspberry pi","repos":"ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme,ferrous26\/cs452-flaming-meme","old_file":"ld\/pi.ld","new_file":"ld\/pi.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ferrous26\/cs452-flaming-meme.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"d873ff6b7b72b88c5720d9b4dd7b147ef2598e4e","subject":"architecture\/ARM\/ARMv7-M: add ARMv7-M.ld","message":"architecture\/ARM\/ARMv7-M: add ARMv7-M.ld\n","repos":"CezaryGapinski\/distortos,jasmin-j\/distortos,DISTORTEC\/distortos,DISTORTEC\/distortos,DISTORTEC\/distortos,jasmin-j\/distortos,CezaryGapinski\/distortos,jasmin-j\/distortos,jasmin-j\/distortos,CezaryGapinski\/distortos,CezaryGapinski\/distortos,CezaryGapinski\/distortos,jasmin-j\/distortos,DISTORTEC\/distortos","old_file":"source\/architecture\/ARM\/ARMv7-M\/ARMv7-M.ld","new_file":"source\/architecture\/ARM\/ARMv7-M\/ARMv7-M.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/jasmin-j\/distortos.git\/': The requested URL returned error: 403\n","license":"mpl-2.0","lang":"Linker Script"}
{"commit":"a41a400ff3d84a2ea95f0ee719a468c73475a88b","subject":"ADD: added link script for lpc 4088","message":"ADD: added link script for lpc 4088\n\nSigned-off-by: Giuseppe Monteleone <59bd0a3ff43b32849b319e645d4798d8a5d1e889@ing-monteleone.com>\n","repos":"geppo12\/YasminOS,kobrabyte\/YasminOS,geppo12\/YasminOS,kobrabyte\/YasminOS","old_file":"src\/platform\/ld\/lpc40xx.ld","new_file":"src\/platform\/ld\/lpc40xx.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kobrabyte\/YasminOS.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"eabc91da8d7b74aed76dd71dd211e7315780c10f","subject":"AT91SAM7A3. Added linker script for A3 (just a copy of X256).","message":"AT91SAM7A3. Added linker script for A3 (just a copy of X256).\n\ngit-svn-id: 30f789d7039adee4ab6dc5f7dbec2df9251e516b@4802 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"os\/ports\/GCC\/ARM\/AT91SAM7\/ld\/AT91SAM7A3.ld","new_file":"os\/ports\/GCC\/ARM\/AT91SAM7\/ld\/AT91SAM7A3.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/roboknight\/chibios-lpc43xx.git\/': GnuTLS recv error (-54): Error in the pull function.\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f18b18d53db1ba3cab40908efdd1d4a44a2ceb5b","subject":"move libstdc++ to flash (#2804)","message":"move libstdc++ to flash (#2804)\n\n* move stdc++ to flash\r\n\r\n* Update : change tab to leading spaces, correct indentation\r\n","repos":"hallard\/Arduino,Juppit\/Arduino,Lan-Hekary\/Arduino,esp8266\/Arduino,me-no-dev\/Arduino,jes\/Arduino,me-no-dev\/Arduino,esp8266\/Arduino,esp8266\/Arduino,Lan-Hekary\/Arduino,Juppit\/Arduino,jes\/Arduino,Adam5Wu\/Arduino,jes\/Arduino,esp8266\/Arduino,Adam5Wu\/Arduino,wemos\/Arduino,me-no-dev\/Arduino,sticilface\/Arduino,lrmoreno007\/Arduino,wemos\/Arduino,Lan-Hekary\/Arduino,wemos\/Arduino,lrmoreno007\/Arduino,Adam5Wu\/Arduino,Juppit\/Arduino,lrmoreno007\/Arduino,sticilface\/Arduino,Juppit\/Arduino,me-no-dev\/Arduino,lrmoreno007\/Arduino,esp8266\/Arduino,lrmoreno007\/Arduino,sticilface\/Arduino,wemos\/Arduino,Adam5Wu\/Arduino,wemos\/Arduino,sticilface\/Arduino,Lan-Hekary\/Arduino,Juppit\/Arduino,sticilface\/Arduino,hallard\/Arduino,Adam5Wu\/Arduino,jes\/Arduino,jes\/Arduino,hallard\/Arduino,me-no-dev\/Arduino,Lan-Hekary\/Arduino,hallard\/Arduino,hallard\/Arduino","old_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Adam5Wu\/Arduino.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"6d2cf4fda6a459a5e6d5160c29a730aa8436b208","subject":"factory: simple PE linker script","message":"factory: simple PE linker script\n","repos":"gdelugre\/shell-factory,gdelugre\/shell-factory,gdelugre\/shell-factory","old_file":"factory-pe.lds","new_file":"factory-pe.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/gdelugre\/shell-factory.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"530ad91e2ac7c3fdb8054056d88182ab6c35e07c","subject":"Fix linker script","message":"Fix linker script\n","repos":"rexlunae\/redox,Lacaranian\/redox,rexlunae\/redox,Lacaranian\/redox,Lacaranian\/redox,rexlunae\/redox,Lacaranian\/redox,Lacaranian\/redox","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Lacaranian\/redox.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"f39970b0ffe9c9cba9643dc595206d3d21647aa2","subject":"Issue #235 issue resolved by adding 32MX340F512H.ld from local file system to github.","message":"Issue #235 issue resolved by adding 32MX340F512H.ld from local file system to github.\n\n\nFormer-commit-id: 2c9fc9e82cf046b6d95f50fdd77d75aa9925c9df\n","repos":"adamwolf\/chipKIT-core,adamwolf\/chipKIT-core,chipKIT32\/chipkit-core,EmbeddedMan\/chipKIT-core,EmbeddedMan\/chipKIT-core,chipKIT32\/chipkit-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,UECIDE\/chipKIT-core,pontech\/chipKIT-core,UECIDE\/chipKIT-core,chipKIT32\/chipkit-core,pontech\/chipKIT-core,pontech\/chipKIT-core,adamwolf\/chipKIT-core,chipKIT32\/chipkit-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,ricklon\/chipKIT-core,UECIDE\/chipKIT-core,ricklon\/chipKIT-core,UECIDE\/chipKIT-core,majenkotech\/chipKIT-core,EmbeddedMan\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,UECIDE\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,adamwolf\/chipKIT-core,chipKIT32\/chipkit-core,ricklon\/chipKIT-core,EmbeddedMan\/chipKIT-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core","old_file":"pic32\/cores\/pic32\/chipKIT-application-32MX340F512H.ld","new_file":"pic32\/cores\/pic32\/chipKIT-application-32MX340F512H.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/majenkotech\/chipKIT-core.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"80e2dd0d3d97a80672e3df3c64e4c8f9a6565bf7","subject":"add gcc.ld to bsp\/simulator","message":"add gcc.ld to bsp\/simulator\n","repos":"armink\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,yongli3\/rt-thread,yongli3\/rt-thread,armink\/rt-thread,RT-Thread\/rt-thread,zhaojuntao\/rt-thread,weety\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,armink\/rt-thread,weety\/rt-thread,AubrCool\/rt-thread,gbcwbz\/rt-thread,ArdaFu\/rt-thread,RT-Thread\/rt-thread,gbcwbz\/rt-thread,igou\/rt-thread,FlyLu\/rt-thread,FlyLu\/rt-thread,weiyuliang\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,wolfgangz2013\/rt-thread,AubrCool\/rt-thread,igou\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,zhaojuntao\/rt-thread,RT-Thread\/rt-thread,armink\/rt-thread,hezlog\/rt-thread,yongli3\/rt-thread,hezlog\/rt-thread,hezlog\/rt-thread,RT-Thread\/rt-thread,RT-Thread\/rt-thread,zhaojuntao\/rt-thread,nongxiaoming\/rt-thread,FlyLu\/rt-thread,AubrCool\/rt-thread,AubrCool\/rt-thread,nongxiaoming\/rt-thread,wolfgangz2013\/rt-thread,igou\/rt-thread,zhaojuntao\/rt-thread,weiyuliang\/rt-thread,ArdaFu\/rt-thread,AubrCool\/rt-thread,wolfgangz2013\/rt-thread,weiyuliang\/rt-thread,ArdaFu\/rt-thread,igou\/rt-thread,yongli3\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,zhaojuntao\/rt-thread,hezlog\/rt-thread,geniusgogo\/rt-thread,AubrCool\/rt-thread,hezlog\/rt-thread,nongxiaoming\/rt-thread,weety\/rt-thread,weety\/rt-thread,weiyuliang\/rt-thread,weety\/rt-thread,ArdaFu\/rt-thread,armink\/rt-thread,igou\/rt-thread,hezlog\/rt-thread,yongli3\/rt-thread,RT-Thread\/rt-thread,weiyuliang\/rt-thread,yongli3\/rt-thread,geniusgogo\/rt-thread,nongxiaoming\/rt-thread,zhaojuntao\/rt-thread,gbcwbz\/rt-thread,geniusgogo\/rt-thread,igou\/rt-thread,wolfgangz2013\/rt-thread,armink\/rt-thread,armink\/rt-thread,ArdaFu\/rt-thread,yongli3\/rt-thread,hezlog\/rt-thread,igou\/rt-thread,ArdaFu\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,gbcwbz\/rt-thread,wolfgangz2013\/rt-thread,geniusgogo\/rt-thread,AubrCool\/rt-thread,geniusgogo\/rt-thread,FlyLu\/rt-thread,nongxiaoming\/rt-thread,ArdaFu\/rt-thread,gbcwbz\/rt-thread","old_file":"bsp\/simulator\/gcc.ld","new_file":"bsp\/simulator\/gcc.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/igou\/rt-thread.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9b418402078b2c5e2202d0070f764d3ae5aec615","subject":"Create tlink_ap.ld","message":"Create tlink_ap.ld","repos":"izard\/RTBench,izard\/RTBench","old_file":"tools\/src\/disturber\/baremetal\/smallos\/tlink_ap.ld","new_file":"tools\/src\/disturber\/baremetal\/smallos\/tlink_ap.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/izard\/RTBench.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"1895bacb97ac5f44648ad149dd08c9a5a425a6fb","subject":"Linker","message":"Linker\n","repos":"prp-e\/NanOS-old","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/prp-e\/NanOS-old.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"3ef31fb615a22d8404614f440b7bc687201cad3c","subject":"hp.geojson with ld error","message":"hp.geojson with ld error\n","repos":"y12studio\/y12io,y12studio\/y12io,y12studio\/y12io,y12studio\/y12io,y12studio\/y12io,y12studio\/y12io,y12studio\/y12io","old_file":"projects\/g0v-er\/data\/hp.geojson.ld","new_file":"projects\/g0v-er\/data\/hp.geojson.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/y12studio\/y12io.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a294c28f0f764e5a9d187e5e20c2a8cd2c1c9d58","subject":"Common daplink.ld gcc linker script.","message":"Common daplink.ld gcc linker script.\n","repos":"google\/DAPLink-port,google\/DAPLink-port,google\/DAPLink-port,google\/DAPLink-port","old_file":"source\/daplink\/daplink.ld","new_file":"source\/daplink\/daplink.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/google\/DAPLink-port.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"36008de2ed90f73bd03c3acfd91d49280ace4b9d","subject":"added custom ld file for samd51 no crystal, ext flash","message":"added custom ld file for samd51 no crystal, ext flash\n","repos":"adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython","old_file":"ports\/atmel-samd\/boards\/samd51x19-bootloader-external-flash-crystalless.ld","new_file":"ports\/atmel-samd\/boards\/samd51x19-bootloader-external-flash-crystalless.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/adafruit\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"272b95e8ce35a849047cbfb9d0dc52cd19a43672","subject":"linker: Don't link all of 'soc' into IRAM","message":"linker: Don't link all of 'soc' into IRAM\n\nMoves any code in *_perpih.c, memory_layout_utils.c to flash\n","repos":"mashaoze\/esp-idf,mashaoze\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,armada-ai\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,espressif\/esp-idf,www220\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,mashaoze\/esp-idf,armada-ai\/esp-idf,www220\/esp-idf,www220\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf","old_file":"components\/esp32\/ld\/esp32.common.ld","new_file":"components\/esp32\/ld\/esp32.common.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mashaoze\/esp-idf.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2cb422fb192384dfe3df82e778fd2d58eed98139","subject":"Create W25Q128JV.ld","message":"Create W25Q128JV.ld\n\nAdd flash file needed for Teensy MicroMod,\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/mimxrt10xx\/linking\/flash\/W25Q128JV.ld","new_file":"ports\/mimxrt10xx\/linking\/flash\/W25Q128JV.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/adafruit\/circuitpython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"d484633e741d65349236bedb02574b90ee1535a9","subject":"Fix linker script.","message":"Fix linker script.\n\nSigned-off-by: Gerd Zellweger <1d6e1cf70ec6f9ab28d3ea4b27a49a77654d370e@gerdzellweger.com>\n","repos":"gz\/bespin,gz\/bespin,gz\/bespin","old_file":"kernel\/src\/arch\/x86_64\/link.ld","new_file":"kernel\/src\/arch\/x86_64\/link.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/gz\/bespin.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"02b2ad4fbdbfae3e06ee4d0c686be36509d53d7d","subject":"stm32\/boards\/STM32F769DISC: Fix length of FLASH_APP section.","message":"stm32\/boards\/STM32F769DISC: Fix length of FLASH_APP section.\n\nFixes issue #4924.\n","repos":"pramasoul\/micropython,adafruit\/circuitpython,tobbad\/micropython,pfalcon\/micropython,henriknelson\/micropython,pozetroninc\/micropython,tobbad\/micropython,tobbad\/micropython,pozetroninc\/micropython,MrSurly\/micropython,kerneltask\/micropython,MrSurly\/micropython,bvernoux\/micropython,pfalcon\/micropython,trezor\/micropython,adafruit\/circuitpython,selste\/micropython,trezor\/micropython,adafruit\/circuitpython,selste\/micropython,bvernoux\/micropython,kerneltask\/micropython,bvernoux\/micropython,pramasoul\/micropython,trezor\/micropython,trezor\/micropython,henriknelson\/micropython,MrSurly\/micropython,pozetroninc\/micropython,kerneltask\/micropython,adafruit\/circuitpython,pramasoul\/micropython,MrSurly\/micropython,selste\/micropython,selste\/micropython,trezor\/micropython,adafruit\/circuitpython,kerneltask\/micropython,kerneltask\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pozetroninc\/micropython,selste\/micropython,bvernoux\/micropython,pramasoul\/micropython,bvernoux\/micropython,henriknelson\/micropython,tobbad\/micropython,henriknelson\/micropython,pramasoul\/micropython,henriknelson\/micropython,MrSurly\/micropython,pozetroninc\/micropython,tobbad\/micropython,adafruit\/circuitpython","old_file":"ports\/stm32\/boards\/STM32F769DISC\/f769_qspi.ld","new_file":"ports\/stm32\/boards\/STM32F769DISC\/f769_qspi.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/pfalcon\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"7310c05d895ae9e923eb401c72179ff5b919542b","subject":"new file","message":"new file\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX71M\/R5F571MF.ld","new_file":"RX71M\/R5F571MF.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/hirakuni45\/RX.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"88b9a97cb19669de97b061de07ca8239897042fa","subject":"building ldoc documentation","message":"building ldoc documentation\n","repos":"henry4k\/LDoc,msva\/LDoc,cjtallman\/LDoc,stevedonovan\/LDoc","old_file":"config.ld","new_file":"config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/cjtallman\/LDoc.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"1bb6de57f3276557f0bcffed7246842ba268364f","subject":"Create linker.ld","message":"Create linker.ld\n\n","repos":"ColinMoulds\/SWAT-OS","old_file":"Source\/linker.ld","new_file":"Source\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ColinMoulds\/SWAT-OS.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"7a1203248b097eca220514b2519dd57a9d41ced6","subject":"Added linker script. Seems a good place for it as all the memory is internal so there's nothing board specific here.","message":"Added linker script. Seems a good place for it as all the memory is\ninternal so there's nothing board specific here.\n","repos":"thejpster\/lm4f120","old_file":"lm4f120.ld","new_file":"lm4f120.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/thejpster\/lm4f120.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"bbb47c5082e5d6cc084ab2b2c6ec6cbf95aa8254","subject":"hide symbols from statically linked stdlibc++","message":"hide symbols from statically linked stdlibc++\n","repos":"mapycz\/python-mapnik,mapycz\/python-mapnik","old_file":"debian\/mapnik.lds","new_file":"debian\/mapnik.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mapycz\/python-mapnik.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"686afd341de4a101303cd515eafed7f4f0793a29","subject":"new file","message":"new file\n","repos":"hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX,hirakuni45\/RX","old_file":"RX65x\/R5F565NE.ld","new_file":"RX65x\/R5F565NE.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/hirakuni45\/RX.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"7166b32bf410e22a0366b3e2c086de1e88fb285f","subject":"temporarily disabled CCMRAM","message":"temporarily disabled CCMRAM\n","repos":"craigsacco\/invetech-sumobot,craigsacco\/invetech-sumobot,craigsacco\/invetech-sumobot,craigsacco\/invetech-sumobot,craigsacco\/invetech-sumobot","old_file":"sumobot\/sumobot_stm32f407zg.ld","new_file":"sumobot\/sumobot_stm32f407zg.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/craigsacco\/invetech-sumobot.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"dfec3989195024d9fee636e326145ca6a7ce5e5d","subject":"Linker: Add F100xB linkerscript.","message":"Linker: Add F100xB linkerscript.","repos":"dergraaf\/xpcc,dergraaf\/xpcc,chrism333\/xpcc,chrism333\/xpcc,dergraaf\/xpcc,chrism333\/xpcc,chrism333\/xpcc,dergraaf\/xpcc","old_file":"src\/xpcc\/architecture\/platform\/linker\/stm32\/stm32f100_b.ld","new_file":"src\/xpcc\/architecture\/platform\/linker\/stm32\/stm32f100_b.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/dergraaf\/xpcc.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"d0067b451f2b7ef6ccb424d64efca3bd1587c2f5","subject":"cpu\/stm32_common\/ldscripts: add stm32_common.ld to manage specific ST ccmram","message":"cpu\/stm32_common\/ldscripts: add stm32_common.ld to manage specific ST ccmram\n","repos":"josephnoir\/RIOT,authmillenon\/RIOT,cladmi\/RIOT,ant9000\/RIOT,roberthartung\/RIOT,A-Paul\/RIOT,OTAkeys\/RIOT,aeneby\/RIOT,immesys\/RiSyn,toonst\/RIOT,LudwigKnuepfer\/RIOT,rfuentess\/RIOT,LudwigOrtmann\/RIOT,neiljay\/RIOT,biboc\/RIOT,neiljay\/RIOT,avmelnikoff\/RIOT,toonst\/RIOT,jasonatran\/RIOT,cladmi\/RIOT,kaspar030\/RIOT,toonst\/RIOT,RIOT-OS\/RIOT,miri64\/RIOT,x3ro\/RIOT,OTAkeys\/RIOT,basilfx\/RIOT,BytesGalore\/RIOT,BytesGalore\/RIOT,cladmi\/RIOT,RIOT-OS\/RIOT,lazytech-org\/RIOT,ant9000\/RIOT,LudwigKnuepfer\/RIOT,josephnoir\/RIOT,roberthartung\/RIOT,aeneby\/RIOT,LudwigOrtmann\/RIOT,OTAkeys\/RIOT,aeneby\/RIOT,avmelnikoff\/RIOT,authmillenon\/RIOT,kaspar030\/RIOT,smlng\/RIOT,kYc0o\/RIOT,basilfx\/RIOT,cladmi\/RIOT,roberthartung\/RIOT,Josar\/RIOT,kbumsik\/RIOT,immesys\/RiSyn,kYc0o\/RIOT,lazytech-org\/RIOT,Josar\/RIOT,kYc0o\/RIOT,lazytech-org\/RIOT,RIOT-OS\/RIOT,mfrey\/RIOT,OlegHahm\/RIOT,neiljay\/RIOT,A-Paul\/RIOT,toonst\/RIOT,biboc\/RIOT,immesys\/RiSyn,ant9000\/RIOT,authmillenon\/RIOT,smlng\/RIOT,Josar\/RIOT,LudwigOrtmann\/RIOT,josephnoir\/RIOT,gebart\/RIOT,ant9000\/RIOT,miri64\/RIOT,A-Paul\/RIOT,gebart\/RIOT,kbumsik\/RIOT,jasonatran\/RIOT,yogo1212\/RIOT,jasonatran\/RIOT,avmelnikoff\/RIOT,rfuentess\/RIOT,OlegHahm\/RIOT,authmillenon\/RIOT,yogo1212\/RIOT,LudwigKnuepfer\/RIOT,gebart\/RIOT,LudwigOrtmann\/RIOT,immesys\/RiSyn,authmillenon\/RIOT,roberthartung\/RIOT,miri64\/RIOT,LudwigKnuepfer\/RIOT,BytesGalore\/RIOT,lazytech-org\/RIOT,mtausig\/RIOT,smlng\/RIOT,biboc\/RIOT,mtausig\/RIOT,lazytech-org\/RIOT,mfrey\/RIOT,yogo1212\/RIOT,LudwigKnuepfer\/RIOT,yogo1212\/RIOT,basilfx\/RIOT,jasonatran\/RIOT,mfrey\/RIOT,kaspar030\/RIOT,mfrey\/RIOT,kbumsik\/RIOT,smlng\/RIOT,kaspar030\/RIOT,OlegHahm\/RIOT,immesys\/RiSyn,kYc0o\/RIOT,Josar\/RIOT,neiljay\/RIOT,OlegHahm\/RIOT,BytesGalore\/RIOT,aeneby\/RIOT,biboc\/RIOT,A-Paul\/RIOT,yogo1212\/RIOT,josephnoir\/RIOT,miri64\/RIOT,Josar\/RIOT,x3ro\/RIOT,aeneby\/RIOT,roberthartung\/RIOT,josephnoir\/RIOT,rfuentess\/RIOT,x3ro\/RIOT,LudwigOrtmann\/RIOT,mfrey\/RIOT,kbumsik\/RIOT,kbumsik\/RIOT,OTAkeys\/RIOT,kaspar030\/RIOT,BytesGalore\/RIOT,rfuentess\/RIOT,RIOT-OS\/RIOT,A-Paul\/RIOT,yogo1212\/RIOT,immesys\/RiSyn,x3ro\/RIOT,x3ro\/RIOT,OTAkeys\/RIOT,biboc\/RIOT,gebart\/RIOT,gebart\/RIOT,mtausig\/RIOT,basilfx\/RIOT,rfuentess\/RIOT,ant9000\/RIOT,cladmi\/RIOT,smlng\/RIOT,toonst\/RIOT,mtausig\/RIOT,avmelnikoff\/RIOT,OlegHahm\/RIOT,avmelnikoff\/RIOT,miri64\/RIOT,neiljay\/RIOT,mtausig\/RIOT,RIOT-OS\/RIOT,authmillenon\/RIOT,kYc0o\/RIOT,LudwigOrtmann\/RIOT,basilfx\/RIOT,jasonatran\/RIOT","old_file":"cpu\/stm32_common\/ldscripts\/stm32_common.ld","new_file":"cpu\/stm32_common\/ldscripts\/stm32_common.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"14377a482bfc51678587cf8774fc7f78d1377f03","subject":"Rename linker file","message":"Rename linker file\n","repos":"1nv1\/OpenKL25Z,1nv1\/OpenKL25Z,1nv1\/OpenKL25Z","old_file":"OpenKL25Z.ld","new_file":"OpenKL25Z.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/1nv1\/OpenKL25Z.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"2a61d4d4a5820dbbe349bb42963ebccaa1691d78","subject":"LDoc config for documentation","message":"LDoc config for documentation\n\nSigned-off-by: Vadim A. Misbakh-Soloviov <0317e6896132b03afd1b7513bbabbb42f0b8d888@mva.name>\n","repos":"moteus\/lua-lcurl,Lua-cURL\/Lua-cURLv3,Lua-cURL\/Lua-cURLv3,moteus\/lua-lcurl,Lua-cURL\/Lua-cURLv3","old_file":"doc\/config.ld","new_file":"doc\/config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Lua-cURL\/Lua-cURLv3.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"7841c59ba5d9027c9ce84b328c34ba220a18cbfc","subject":"added linker script. makefile is still missing","message":"added linker script. makefile is still missing\n","repos":"ornitorrincos\/OS,ornitorrincos\/OS","old_file":"kernel\/linker.ld","new_file":"kernel\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ornitorrincos\/OS.git\/': The requested URL returned error: 403\n","license":"isc","lang":"Linker Script"}
{"commit":"57c6279b4039b8d770c3f54e7bfeff320f461350","subject":"Added new linker file","message":"Added new linker file\n","repos":"adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython","old_file":"ports\/stm\/boards\/STM32F411_nofs.ld","new_file":"ports\/stm\/boards\/STM32F411_nofs.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/adafruit\/circuitpython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"338dc330bc7bd1d467ef1377aeb6806a66ff7063","subject":"\tnew file:   cortex-m3.ld","message":"\tnew file:   cortex-m3.ld\n","repos":"masilvabustos\/CabbageOS,masilvabustos\/CabbageOS","old_file":"lib\/ldscripts\/cortex-m3.ld","new_file":"lib\/ldscripts\/cortex-m3.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/masilvabustos\/CabbageOS.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"a78ec26c60d7c9f66a649dc6c4402630764d936f","subject":"Use the correct name for dtb_size","message":"Use the correct name for dtb_size\n\n(cherry picked from commit 1bb6bfee23440d78c0fb883174fc4d11eafff49d)\n","repos":"kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa","old_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kalray\/odp-mppa.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"c519e180ad4050c117b530cb1fba0f0d77daac93","subject":"Create linker.ld","message":"Create linker.ld","repos":"salahalami\/BruteOS","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/salahalami\/BruteOS.git\/': The requested URL returned error: 403\n","license":"unlicense","lang":"Linker Script"}
{"commit":"ddb3b84c70b2481e576a77277fda9b0601cf6b13","subject":"stm32\/boards: Add common_basic.ld for a board to have a single section.","message":"stm32\/boards: Add common_basic.ld for a board to have a single section.\n","repos":"henriknelson\/micropython,trezor\/micropython,pfalcon\/micropython,kerneltask\/micropython,bvernoux\/micropython,adafruit\/micropython,tobbad\/micropython,selste\/micropython,pfalcon\/micropython,trezor\/micropython,tralamazza\/micropython,pfalcon\/micropython,swegener\/micropython,tralamazza\/micropython,selste\/micropython,adafruit\/circuitpython,tobbad\/micropython,pramasoul\/micropython,swegener\/micropython,ryannathans\/micropython,henriknelson\/micropython,swegener\/micropython,kerneltask\/micropython,dmazzella\/micropython,pozetroninc\/micropython,adafruit\/circuitpython,pozetroninc\/micropython,ryannathans\/micropython,trezor\/micropython,trezor\/micropython,swegener\/micropython,ryannathans\/micropython,henriknelson\/micropython,adafruit\/micropython,kerneltask\/micropython,tralamazza\/micropython,dmazzella\/micropython,adafruit\/circuitpython,pramasoul\/micropython,bvernoux\/micropython,pramasoul\/micropython,pozetroninc\/micropython,bvernoux\/micropython,kerneltask\/micropython,adafruit\/circuitpython,pfalcon\/micropython,selste\/micropython,henriknelson\/micropython,pozetroninc\/micropython,pramasoul\/micropython,dmazzella\/micropython,swegener\/micropython,MrSurly\/micropython,kerneltask\/micropython,tralamazza\/micropython,MrSurly\/micropython,MrSurly\/micropython,ryannathans\/micropython,tobbad\/micropython,selste\/micropython,adafruit\/micropython,tobbad\/micropython,pfalcon\/micropython,henriknelson\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,pozetroninc\/micropython,bvernoux\/micropython,pramasoul\/micropython,tobbad\/micropython,dmazzella\/micropython,MrSurly\/micropython,selste\/micropython,MrSurly\/micropython,ryannathans\/micropython,bvernoux\/micropython,trezor\/micropython,adafruit\/micropython","old_file":"ports\/stm32\/boards\/common_basic.ld","new_file":"ports\/stm32\/boards\/common_basic.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/pfalcon\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"ffea9fc4e8c09fd9d1dbf22e9d596f2675abe39c","subject":"cpu\/cc2538: added linkerscript for cc2538sf53","message":"cpu\/cc2538: added linkerscript for cc2538sf53\n","repos":"d00616\/RIOT,kerneltask\/RIOT,Yonezawa-T2\/RIOT,alex1818\/RIOT,altairpearl\/RIOT,Lexandro92\/RIOT-CoAP,herrfz\/RIOT,khhhh\/RIOT,dhruvvyas90\/RIOT,koenning\/RIOT,msolters\/RIOT,abkam07\/RIOT,BytesGalore\/RIOT,luciotorre\/RIOT,haoyangyu\/RIOT,gautric\/RIOT,authmillenon\/RIOT,sgso\/RIOT,marcosalm\/RIOT,malosek\/RIOT,attdona\/RIOT,l3nko\/RIOT,kb2ma\/RIOT,latsku\/RIOT,JensErdmann\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,biboc\/RIOT,cladmi\/RIOT,mtausig\/RIOT,LudwigKnuepfer\/RIOT,Osblouf\/RIOT,avmelnikoff\/RIOT,avmelnikoff\/RIOT,basilfx\/RIOT,mziegert\/RIOT,kaspar030\/RIOT,latsku\/RIOT,FrancescoErmini\/RIOT,msolters\/RIOT,beurdouche\/RIOT,smlng\/RIOT,authmillenon\/RIOT,Josar\/RIOT,1blankz7\/RIOT,aeneby\/RIOT,MohmadAyman\/RIOT,malosek\/RIOT,DipSwitch\/RIOT,Osblouf\/RIOT,dkm\/RIOT,mtausig\/RIOT,watr-li\/RIOT,A-Paul\/RIOT,latsku\/RIOT,asanka-code\/RIOT,herrfz\/RIOT-old,JensErdmann\/RIOT,lazytech-org\/RIOT,JensErdmann\/RIOT,hamilton-mote\/RIOT-OS,shady33\/RIOT,wentaoshang\/RIOT,rfuentess\/RIOT,brettswann\/RIOT,herrfz\/RIOT,jasonatran\/RIOT,stevenj\/RIOT,changbiao\/RIOT,kYc0o\/RIOT,rakendrathapa\/RIOT,emmanuelsearch\/RIOT,adrianghc\/RIOT,immesys\/RiSyn,LudwigKnuepfer\/RIOT,FrancescoErmini\/RIOT,MarkXYang\/RIOT,TobiasFredersdorf\/RIOT,koenning\/RIOT,luciotorre\/RIOT,Osblouf\/RIOT,MarkXYang\/RIOT,katezilla\/RIOT,ks156\/RIOT,jhollister\/RIOT,rousselk\/RIOT,haoyangyu\/RIOT,alex1818\/RIOT,Josar\/RIOT,jremmert-phytec-iot\/RIOT,openkosmosorg\/RIOT,kb2ma\/RIOT,hamilton-mote\/RIOT-OS,RIOT-OS\/RIOT,Hyungsin\/RIOT-OS,toonst\/RIOT,AnonMall\/RIOT,malosek\/RIOT,DipSwitch\/RIOT,msolters\/RIOT,RIOT-OS\/RIOT,1blankz7\/RIOT,openkosmosorg\/RIOT,adjih\/RIOT,immesys\/RiSyn,chris-wood\/RIOT,robixnai\/RIOT,jremmert-phytec-iot\/RIOT,nsol-nmsu\/RIOT,tdautc19841202\/RIOT,rfuentess\/RIOT,asanka-code\/RIOT,RubikonAlpha\/RIOT,rfswarm\/RIOT,Osblouf\/RIOT,benoit-canet\/RIOT,AnonMall\/RIOT,zhuoshuguo\/RIOT,lebrush\/RIOT,Ell-i\/RIOT,josephnoir\/RIOT,ant9000\/RIOT,adrianghc\/RIOT,rfuentess\/RIOT,fnack\/RIOT,latsku\/RIOT,watr-li\/RIOT,mziegert\/RIOT,jferreir\/RIOT,abp719\/RIOT,FrancescoErmini\/RIOT,patkan\/RIOT,marcosalm\/RIOT,MarkXYang\/RIOT,msolters\/RIOT,rfswarm2\/RIOT,authmillenon\/RIOT,ximus\/RIOT,neumodisch\/RIOT,rajma996\/RIOT,miri64\/RIOT,jferreir\/RIOT,mziegert\/RIOT,EmuxEvans\/RIOT,backenklee\/RIOT,automote\/RIOT,ks156\/RIOT,ThanhVic\/RIOT,josephnoir\/RIOT,kb2ma\/RIOT,kaleb-himes\/RIOT,kaleb-himes\/RIOT,LudwigOrtmann\/RIOT,avmelnikoff\/RIOT,OlegHahm\/RIOT,chris-wood\/RIOT,koenning\/RIOT,roberthartung\/RIOT,daniel-k\/RIOT,mfrey\/RIOT,binarylemon\/RIOT,ThanhVic\/RIOT,rousselk\/RIOT,Yonezawa-T2\/RIOT,wentaoshang\/RIOT,backenklee\/RIOT,herrfz\/RIOT-old,lazytech-org\/RIOT,sumanpanchal\/RIOT,marcosalm\/RIOT,herrfz\/RIOT,rajma996\/RIOT,TobiasFredersdorf\/RIOT,immesys\/RiSyn,adjih\/RIOT,mfrey\/RIOT,rfuentess\/RIOT,hamilton-mote\/RIOT-OS,binarylemon\/RIOT,emmanuelsearch\/RIOT,LudwigOrtmann\/RIOT,gbarnett\/RIOT,tdautc19841202\/RIOT,phiros\/RIOT,abp719\/RIOT,EmuxEvans\/RIOT,openkosmosorg\/RIOT,dailab\/RIOT,BytesGalore\/RIOT,malosek\/RIOT,arvindpdmn\/RIOT,1blankz7\/RIOT,gebart\/RIOT,neumodisch\/RIOT,daniel-k\/RIOT,binarylemon\/RIOT,rfswarm\/RIOT,dailab\/RIOT,smlng\/RIOT,x3ro\/RIOT,benoit-canet\/RIOT,syin2\/RIOT,AnonMall\/RIOT,OTAkeys\/RIOT,ximus\/RIOT,centurysys\/RIOT,lazytech-org\/RIOT,TobiasFredersdorf\/RIOT,stevenj\/RIOT,patkan\/RIOT,RubikonAlpha\/RIOT,RIOT-OS\/RIOT,JensErdmann\/RIOT,changbiao\/RIOT,Lexandro92\/RIOT-CoAP,ks156\/RIOT,rfswarm2\/RIOT,cladmi\/RIOT,toonst\/RIOT,syin2\/RIOT,RubikonAlpha\/RIOT,centurysys\/RIOT,shady33\/RIOT,JensErdmann\/RIOT,neiljay\/RIOT,LudwigOrtmann\/RIOT,tfar\/RIOT,marcosalm\/RIOT,MonsterCode8000\/RIOT,thomaseichinger\/RIOT,luciotorre\/RIOT,rakendrathapa\/RIOT,neiljay\/RIOT,alex1818\/RIOT,BytesGalore\/RIOT,kaleb-himes\/RIOT,robixnai\/RIOT,altairpearl\/RIOT,MonsterCode8000\/RIOT,gbarnett\/RIOT,beurdouche\/RIOT,alignan\/RIOT,neiljay\/RIOT,tfar\/RIOT,plushvoxel\/RIOT,bartfaizoltan\/RIOT,kushalsingh007\/RIOT,katezilla\/RIOT,gbarnett\/RIOT,Osblouf\/RIOT,jasonatran\/RIOT,binarylemon\/RIOT,lebrush\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,tfar\/RIOT,abp719\/RIOT,abkam07\/RIOT,gebart\/RIOT,OTAkeys\/RIOT,gautric\/RIOT,centurysys\/RIOT,kaspar030\/RIOT,benoit-canet\/RIOT,josephnoir\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,brettswann\/RIOT,AnonMall\/RIOT,lebrush\/RIOT,ant9000\/RIOT,fnack\/RIOT,chris-wood\/RIOT,jferreir\/RIOT,fnack\/RIOT,thiagohd\/RIOT,jbeyerstedt\/RIOT-OTA-update,Josar\/RIOT,jbeyerstedt\/RIOT-OTA-update,ant9000\/RIOT,basilfx\/RIOT,altairpearl\/RIOT,jferreir\/RIOT,A-Paul\/RIOT,cladmi\/RIOT,bartfaizoltan\/RIOT,abkam07\/RIOT,abkam07\/RIOT,thiagohd\/RIOT,asanka-code\/RIOT,dkm\/RIOT,koenning\/RIOT,FrancescoErmini\/RIOT,robixnai\/RIOT,mtausig\/RIOT,stevenj\/RIOT,OTAkeys\/RIOT,ximus\/RIOT,dhruvvyas90\/RIOT,A-Paul\/RIOT,koenning\/RIOT,haoyangyu\/RIOT,robixnai\/RIOT,ximus\/RIOT,daniel-k\/RIOT,kYc0o\/RIOT,Lexandro92\/RIOT-CoAP,x3ro\/RIOT,dhruvvyas90\/RIOT,lebrush\/RIOT,LudwigOrtmann\/RIOT,DipSwitch\/RIOT,PSHIVANI\/Riot-Code,x3ro\/RIOT,khhhh\/RIOT,lazytech-org\/RIOT,rajma996\/RIOT,msolters\/RIOT,chris-wood\/RIOT,MonsterCode8000\/RIOT,smlng\/RIOT,RubikonAlpha\/RIOT,kbumsik\/RIOT,dhruvvyas90\/RIOT,MonsterCode8000\/RIOT,MarkXYang\/RIOT,OlegHahm\/RIOT,abp719\/RIOT,jfischer-phytec-iot\/RIOT,arvindpdmn\/RIOT,sgso\/RIOT,patkan\/RIOT,stevenj\/RIOT,EmuxEvans\/RIOT,sgso\/RIOT,alignan\/RIOT,changbiao\/RIOT,khhhh\/RIOT,khhhh\/RIOT,binarylemon\/RIOT,sgso\/RIOT,arvindpdmn\/RIOT,luciotorre\/RIOT,roberthartung\/RIOT,ant9000\/RIOT,rakendrathapa\/RIOT,biboc\/RIOT,automote\/RIOT,wentaoshang\/RIOT,kaspar030\/RIOT,thiagohd\/RIOT,rfswarm2\/RIOT,MohmadAyman\/RIOT,abkam07\/RIOT,mtausig\/RIOT,roberthartung\/RIOT,wentaoshang\/RIOT,daniel-k\/RIOT,immesys\/RiSyn,Ell-i\/RIOT,Hyungsin\/RIOT-OS,jasonatran\/RIOT,MohmadAyman\/RIOT,basilfx\/RIOT,kYc0o\/RIOT,changbiao\/RIOT,MarkXYang\/RIOT,gebart\/RIOT,kaleb-himes\/RIOT,biboc\/RIOT,lazytech-org\/RIOT,MohmadAyman\/RIOT,RubikonAlpha\/RIOT,kb2ma\/RIOT,ThanhVic\/RIOT,x3ro\/RIOT,mfrey\/RIOT,aeneby\/RIOT,ThanhVic\/RIOT,ks156\/RIOT,jhollister\/RIOT,dailab\/RIOT,tdautc19841202\/RIOT,attdona\/RIOT,kbumsik\/RIOT,AnonMall\/RIOT,BytesGalore\/RIOT,authmillenon\/RIOT,rousselk\/RIOT,rousselk\/RIOT,d00616\/RIOT,watr-li\/RIOT,plushvoxel\/RIOT,EmuxEvans\/RIOT,FrancescoErmini\/RIOT,smlng\/RIOT,Hyungsin\/RIOT-OS,watr-li\/RIOT,dkm\/RIOT,PSHIVANI\/Riot-Code,biboc\/RIOT,bartfaizoltan\/RIOT,emmanuelsearch\/RIOT,alex1818\/RIOT,tdautc19841202\/RIOT,EmuxEvans\/RIOT,MohmadAyman\/RIOT,chris-wood\/RIOT,backenklee\/RIOT,neumodisch\/RIOT,zhuoshuguo\/RIOT,rfswarm\/RIOT,shady33\/RIOT,neiljay\/RIOT,PSHIVANI\/Riot-Code,marcosalm\/RIOT,lebrush\/RIOT,luciotorre\/RIOT,kushalsingh007\/RIOT,adrianghc\/RIOT,authmillenon\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,msolters\/RIOT,josephnoir\/RIOT,A-Paul\/RIOT,arvindpdmn\/RIOT,kerneltask\/RIOT,LudwigKnuepfer\/RIOT,DipSwitch\/RIOT,Darredevil\/RIOT,shady33\/RIOT,MohmadAyman\/RIOT,jhollister\/RIOT,thiagohd\/RIOT,beurdouche\/RIOT,Josar\/RIOT,katezilla\/RIOT,gbarnett\/RIOT,jhollister\/RIOT,foss-for-synopsys-dwc-arc-processors\/RIOT,aeneby\/RIOT,yogo1212\/RIOT,kaleb-himes\/RIOT,marcosalm\/RIOT,Darredevil\/RIOT,gautric\/RIOT,wentaoshang\/RIOT,katezilla\/RIOT,gbarnett\/RIOT,dkm\/RIOT,FrancescoErmini\/RIOT,roberthartung\/RIOT,bartfaizoltan\/RIOT,kushalsingh007\/RIOT,nsol-nmsu\/RIOT,ant9000\/RIOT,dailab\/RIOT,Ell-i\/RIOT,attdona\/RIOT,malosek\/RIOT,TobiasFredersdorf\/RIOT,PSHIVANI\/Riot-Code,miri64\/RIOT,rfuentess\/RIOT,shady33\/RIOT,Hyungsin\/RIOT-OS,RubikonAlpha\/RIOT,biboc\/RIOT,MonsterCode8000\/RIOT,gebart\/RIOT,adjih\/RIOT,daniel-k\/RIOT,nsol-nmsu\/RIOT,syin2\/RIOT,emmanuelsearch\/RIOT,sgso\/RIOT,patkan\/RIOT,arvindpdmn\/RIOT,Lexandro92\/RIOT-CoAP,smlng\/RIOT,MarkXYang\/RIOT,lebrush\/RIOT,robixnai\/RIOT,dhruvvyas90\/RIOT,jasonatran\/RIOT,basilfx\/RIOT,openkosmosorg\/RIOT,ximus\/RIOT,alignan\/RIOT,zhuoshuguo\/RIOT,yogo1212\/RIOT,jremmert-phytec-iot\/RIOT,brettswann\/RIOT,mtausig\/RIOT,OlegHahm\/RIOT,watr-li\/RIOT,jhollister\/RIOT,automote\/RIOT,zhuoshuguo\/RIOT,backenklee\/RIOT,haoyangyu\/RIOT,Yonezawa-T2\/RIOT,chris-wood\/RIOT,Yonezawa-T2\/RIOT,EmuxEvans\/RIOT,alex1818\/RIOT,kushalsingh007\/RIOT,plushvoxel\/RIOT,jfischer-phytec-iot\/RIOT,x3ro\/RIOT,jasonatran\/RIOT,patkan\/RIOT,RBartz\/RIOT,tdautc19841202\/RIOT,rousselk\/RIOT,wentaoshang\/RIOT,jferreir\/RIOT,RIOT-OS\/RIOT,avmelnikoff\/RIOT,phiros\/RIOT,avmelnikoff\/RIOT,tfar\/RIOT,neumodisch\/RIOT,altairpearl\/RIOT,adjih\/RIOT,changbiao\/RIOT,mziegert\/RIOT,rajma996\/RIOT,bartfaizoltan\/RIOT,rfswarm2\/RIOT,haoyangyu\/RIOT,yogo1212\/RIOT,nsol-nmsu\/RIOT,ntrtrung\/RIOT,jbeyerstedt\/RIOT-OTA-update,hamilton-mote\/RIOT-OS,A-Paul\/RIOT,adrianghc\/RIOT,alignan\/RIOT,rfswarm2\/RIOT,attdona\/RIOT,yogo1212\/RIOT,plushvoxel\/RIOT,Darredevil\/RIOT,herrfz\/RIOT-old,shady33\/RIOT,haoyangyu\/RIOT,centurysys\/RIOT,JensErdmann\/RIOT,openkosmosorg\/RIOT,Lexandro92\/RIOT-CoAP,yogo1212\/RIOT,LudwigOrtmann\/RIOT,miri64\/RIOT,asanka-code\/RIOT,backenklee\/RIOT,plushvoxel\/RIOT,fnack\/RIOT,immesys\/RiSyn,neiljay\/RIOT,luciotorre\/RIOT,koenning\/RIOT,thomaseichinger\/RIOT,jremmert-phytec-iot\/RIOT,arvindpdmn\/RIOT,abp719\/RIOT,roberthartung\/RIOT,hamilton-mote\/RIOT-OS,rfswarm\/RIOT,Hyungsin\/RIOT-OS,herrfz\/RIOT-old,ks156\/RIOT,toonst\/RIOT,jfischer-phytec-iot\/RIOT,ThanhVic\/RIOT,openkosmosorg\/RIOT,LudwigKnuepfer\/RIOT,phiros\/RIOT,fnack\/RIOT,ThanhVic\/RIOT,emmanuelsearch\/RIOT,kYc0o\/RIOT,thomaseichinger\/RIOT,tfar\/RIOT,RBartz\/RIOT,LudwigOrtmann\/RIOT,Yonezawa-T2\/RIOT,kbumsik\/RIOT,ntrtrung\/RIOT,Darredevil\/RIOT,AnonMall\/RIOT,PSHIVANI\/Riot-Code,RBartz\/RIOT,d00616\/RIOT,brettswann\/RIOT,sumanpanchal\/RIOT,jferreir\/RIOT,thiagohd\/RIOT,MonsterCode8000\/RIOT,gebart\/RIOT,toonst\/RIOT,benoit-canet\/RIOT,1blankz7\/RIOT,Ell-i\/RIOT,l3nko\/RIOT,LudwigKnuepfer\/RIOT,kbumsik\/RIOT,mfrey\/RIOT,miri64\/RIOT,OlegHahm\/RIOT,abkam07\/RIOT,toonst\/RIOT,basilfx\/RIOT,binarylemon\/RIOT,watr-li\/RIOT,latsku\/RIOT,ntrtrung\/RIOT,daniel-k\/RIOT,kaspar030\/RIOT,RBartz\/RIOT,aeneby\/RIOT,cladmi\/RIOT,beurdouche\/RIOT,TobiasFredersdorf\/RIOT,mfrey\/RIOT,ximus\/RIOT,kYc0o\/RIOT,Ell-i\/RIOT,jfischer-phytec-iot\/RIOT,zhuoshuguo\/RIOT,Yonezawa-T2\/RIOT,DipSwitch\/RIOT,OTAkeys\/RIOT,changbiao\/RIOT,dailab\/RIOT,patkan\/RIOT,immesys\/RiSyn,stevenj\/RIOT,kerneltask\/RIOT,syin2\/RIOT,robixnai\/RIOT,l3nko\/RIOT,khhhh\/RIOT,jremmert-phytec-iot\/RIOT,zhuoshuguo\/RIOT,RBartz\/RIOT,cladmi\/RIOT,kaspar030\/RIOT,emmanuelsearch\/RIOT,yogo1212\/RIOT,miri64\/RIOT,phiros\/RIOT,ntrtrung\/RIOT,rfswarm\/RIOT,bartfaizoltan\/RIOT,jremmert-phytec-iot\/RIOT,adjih\/RIOT,OlegHahm\/RIOT,centurysys\/RIOT,RIOT-OS\/RIOT,rakendrathapa\/RIOT,kushalsingh007\/RIOT,ntrtrung\/RIOT,centurysys\/RIOT,asanka-code\/RIOT,attdona\/RIOT,l3nko\/RIOT,Darredevil\/RIOT,neumodisch\/RIOT,rajma996\/RIOT,tdautc19841202\/RIOT,nsol-nmsu\/RIOT,abp719\/RIOT,herrfz\/RIOT,dhruvvyas90\/RIOT,Josar\/RIOT,RBartz\/RIOT,DipSwitch\/RIOT,rakendrathapa\/RIOT,fnack\/RIOT,kerneltask\/RIOT,sumanpanchal\/RIOT,kerneltask\/RIOT,automote\/RIOT,stevenj\/RIOT,sumanpanchal\/RIOT,alignan\/RIOT,rakendrathapa\/RIOT,gautric\/RIOT,l3nko\/RIOT,automote\/RIOT,altairpearl\/RIOT,d00616\/RIOT,thomaseichinger\/RIOT,mziegert\/RIOT,khhhh\/RIOT,katezilla\/RIOT,herrfz\/RIOT,neumodisch\/RIOT,automote\/RIOT,1blankz7\/RIOT,jfischer-phytec-iot\/RIOT,jhollister\/RIOT,thomaseichinger\/RIOT,rajma996\/RIOT,rfswarm\/RIOT,ntrtrung\/RIOT,jbeyerstedt\/RIOT-OTA-update,OTAkeys\/RIOT,altairpearl\/RIOT,authmillenon\/RIOT,jbeyerstedt\/RIOT-OTA-update,mziegert\/RIOT,sgso\/RIOT,gautric\/RIOT,herrfz\/RIOT-old,BytesGalore\/RIOT,thiagohd\/RIOT,herrfz\/RIOT,brettswann\/RIOT,kbumsik\/RIOT,sumanpanchal\/RIOT,kushalsingh007\/RIOT,beurdouche\/RIOT,l3nko\/RIOT,rfswarm2\/RIOT,aeneby\/RIOT,dkm\/RIOT,benoit-canet\/RIOT,malosek\/RIOT,PSHIVANI\/Riot-Code,kb2ma\/RIOT,Lexandro92\/RIOT-CoAP,phiros\/RIOT,asanka-code\/RIOT,Osblouf\/RIOT,Darredevil\/RIOT,gbarnett\/RIOT,rousselk\/RIOT,latsku\/RIOT,adrianghc\/RIOT,josephnoir\/RIOT,syin2\/RIOT,1blankz7\/RIOT,d00616\/RIOT,d00616\/RIOT,phiros\/RIOT,attdona\/RIOT,brettswann\/RIOT,sumanpanchal\/RIOT,alex1818\/RIOT,benoit-canet\/RIOT","old_file":"cpu\/cc2538\/cc2538sf53_linkerscript.ld","new_file":"cpu\/cc2538\/cc2538sf53_linkerscript.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"0f1119135b47f30ed0e4c727705fce80f8891610","subject":"Fix odp with change in device tree","message":"Fix odp with change in device tree\n","repos":"kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa","old_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kalray\/odp-mppa.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"a186fabb56c333b6531fe3046920ec5cf6f5b5b5","subject":"arm: ip_k66f: Introduce board specific linker.ld file","message":"arm: ip_k66f: Introduce board specific linker.ld file\n\nThis patch introduces linker.ld file specific for ip_k66f board.\nIt reuses the \"common\" linker script for other NXP SoCs with defined\nNETWORK_RAM_SECTIONS() macro for explicit placement of network\ninterfaces on ip_k66f board.\n\ngrep -A13 net_if_area zephyr\/zephyr.map\nnet_if_area 0x00000000200012a0 0x820 load address 0x0000000000024ac4\n            0x00000000200012a0                _net_if_list_start = .\n*(SORT_BY_ALIGNMENT(._net_if.static.dts*))\n._net_if.static.dts_ord_51\n          0x00000000200012a0 0x208 zephyr\/libzephyr.a(eth_mcux.c.obj)\n*(SORT_BY_NAME(SORT_BY_ALIGNMENT(._net_if.static.dsa_slave*)))\n._net_if.static.dsa_slave_port_DT_N_S_soc_S_spi_4002d000_S_dsa_0_S_lan_1\n          0x00000000200014a8 0x208 zephyr\/libzephyr.a(dsa_ksz8794.c.obj)\n._net_if.static.dsa_slave_port_DT_N_S_soc_S_spi_4002d000_S_dsa_0_S_lan_2\n          0x00000000200016b0 0x208 zephyr\/libzephyr.a(dsa_ksz8794.c.obj)\n._net_if.static.dsa_slave_port_DT_N_S_soc_S_spi_4002d000_S_dsa_0_S_lan_3\n          0x00000000200018b8 0x208 zephyr\/libzephyr.a(dsa_ksz8794.c.obj)\n          0x0000000020001ac0                _net_if_list_end = .\n\nAs a result the eth0 (master DSA interface) is explicitly placed as the\nfirst one (with the 'dts_ord_51' automatically assigned name) followed\nby lan{123} interfaces (with 'dsa_slave_port' name assigned in\ndsa_ksz8794.c).\n\nAfter this patch network interfaces are explicitly placed in correct\norder, so 'net_if_get_by_index()' will work correctly.\n\nSigned-off-by: Lukasz Majewski <7acbb0643e3da1a0f6f894ebd720fb3807e67dff@denx.de>\n","repos":"zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,nashif\/zephyr,zephyrproject-rtos\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,finikorg\/zephyr,finikorg\/zephyr,finikorg\/zephyr,galak\/zephyr,finikorg\/zephyr,nashif\/zephyr,galak\/zephyr,galak\/zephyr,nashif\/zephyr,nashif\/zephyr,finikorg\/zephyr,zephyrproject-rtos\/zephyr,galak\/zephyr,nashif\/zephyr","old_file":"boards\/arm\/ip_k66f\/linker.ld","new_file":"boards\/arm\/ip_k66f\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/nashif\/zephyr.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8dd6bb003652d910f2cfaabd779f937ffc0edd2e","subject":"cpu: stm32f2: add linker-script.","message":"cpu: stm32f2: add linker-script.\n\nSigned-off-by: Takeyoshi Kikuchi <af72ecfe6d0bf60ad0be9363518c74b6bed5ff74@centurysys.co.jp>\n(cherry picked from commit 26ac0a621c7472bad79fee6f29058203779e3beb)\n","repos":"centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT","old_file":"cpu\/stm32f2\/stm32f205re_linkerscript.ld","new_file":"cpu\/stm32f2\/stm32f205re_linkerscript.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/centurysys\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"89e5cbc79f8e278e0093a9940f6f4bda01703e53","subject":"stm32_flash: Add a section for EEPROM data.","message":"stm32_flash: Add a section for EEPROM data.\n\nThis allocates a few sectors of flash for the following purposes:\n- Sector 0: ISR vector data.  (This gets mapped to address 0; so we have\n  no choice, the ISR data *must* reside here.)\n- Sector 1..3: Virtual EEPROM.  We'll stash our configuration parameters\n  here.  We have 48kB available.\n- Sector 4.. onwards: Program data\n\nCredit: clive1, ST e2e Communities.\nhttps:\/\/my.st.com\/public\/STe2ecommunities\/mcu\/_layouts\/st\/getshorturl.aspx?List={697285D7-A9CA-445D-B16C-F23BF0E3B1A3}&ItemId=24079","repos":"timofonic\/codec2-dev,timofonic\/codec2-dev,timofonic\/codec2-dev,timofonic\/codec2-dev","old_file":"stm32\/stm32_flash.ld","new_file":"stm32\/stm32_flash.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/timofonic\/codec2-dev.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"9e2c3875d487481e09286335accd83a836a70fe8","subject":"Add linker script for S310","message":"Add linker script for S310\n","repos":"jf87\/nrf51-pure-gcc-setup","old_file":"template\/gcc_nrf51_s310.ld","new_file":"template\/gcc_nrf51_s310.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/jf87\/nrf51-pure-gcc-setup.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"8d3849eb55edecb62695436c4510808dbaf72e8f","subject":"Create linker.ld","message":"Create linker.ld","repos":"LambdaSix\/Kerni,LambdaSix\/Kerni,LambdaSix\/Kerni","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/LambdaSix\/Kerni.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"e1daa579866f2b9e862f905d27e48cfd71c380d8","subject":"New linker script","message":"New linker script","repos":"farcaller\/arm-demos,farcaller\/arm-demos,farcaller\/arm-demos,farcaller\/arm-demos","old_file":"04-hello-world\/platform\/protoboard\/layout.ld","new_file":"04-hello-world\/platform\/protoboard\/layout.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/farcaller\/arm-demos.git\/': The requested URL returned error: 403\n","license":"unlicense","lang":"Linker Script"}
{"commit":"9281127b0375a4c4eb33e2c1a0a7ab013dbcfcd7","subject":"regent: Add LDoc config.","message":"regent: Add LDoc config.\n","repos":"StanfordLegion\/legion,StanfordLegion\/legion,StanfordLegion\/legion,StanfordLegion\/legion,StanfordLegion\/legion,StanfordLegion\/legion,StanfordLegion\/legion,StanfordLegion\/legion","old_file":"language\/config.ld","new_file":"language\/config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/StanfordLegion\/legion.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"6e980c44ac5f6723a7abb5aadbcafefc8fe75360","subject":"Create nasm.ld","message":"Create nasm.ld","repos":"ReturnInfinity\/BareMetal-kernel,ReturnInfinity\/BareMetal-kernel","old_file":"src\/x86-64\/nasm.ld","new_file":"src\/x86-64\/nasm.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/ReturnInfinity\/BareMetal-kernel.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"e2def200bfb6f68801568c6b26f73ee86b549be2","subject":"stm32\/boards\/PYBD_SF2: Put BTstack library in external QSPI XIP flash.","message":"stm32\/boards\/PYBD_SF2: Put BTstack library in external QSPI XIP flash.\n\nIn the same way the nimble stack is put there.\n","repos":"adafruit\/circuitpython,henriknelson\/micropython,bvernoux\/micropython,pramasoul\/micropython,MrSurly\/micropython,pramasoul\/micropython,kerneltask\/micropython,selste\/micropython,pramasoul\/micropython,tobbad\/micropython,adafruit\/circuitpython,kerneltask\/micropython,adafruit\/circuitpython,MrSurly\/micropython,bvernoux\/micropython,henriknelson\/micropython,bvernoux\/micropython,pramasoul\/micropython,pramasoul\/micropython,tobbad\/micropython,bvernoux\/micropython,tobbad\/micropython,kerneltask\/micropython,kerneltask\/micropython,selste\/micropython,selste\/micropython,tobbad\/micropython,MrSurly\/micropython,tobbad\/micropython,bvernoux\/micropython,adafruit\/circuitpython,selste\/micropython,selste\/micropython,henriknelson\/micropython,kerneltask\/micropython,adafruit\/circuitpython,MrSurly\/micropython,MrSurly\/micropython,henriknelson\/micropython,henriknelson\/micropython,adafruit\/circuitpython","old_file":"ports\/stm32\/boards\/PYBD_SF2\/f722_qspi.ld","new_file":"ports\/stm32\/boards\/PYBD_SF2\/f722_qspi.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kerneltask\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"59db31e40c30384c513f2cb629a3d4679fcce4f5","subject":"Seperate loader code\/data","message":"Seperate loader code\/data\n","repos":"Tutul-\/tumuxOS,Tutul-\/tumuxOS,Tutul-\/tumuxOS","old_file":"src\/kernel\/arch\/x86\/linker.ld","new_file":"src\/kernel\/arch\/x86\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Tutul-\/tumuxOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"a4ebc2097b5f79168f54fbde4f798b44b2e481e8","subject":"stm32_flash: Fill EEPROM section with 0xff.","message":"stm32_flash: Fill EEPROM section with 0xff.\n\nFilling it with 0x00 (the default) makes the virtual EEPROM code think\nthe sectors are depleted.","repos":"timofonic\/codec2-dev,timofonic\/codec2-dev,timofonic\/codec2-dev,timofonic\/codec2-dev","old_file":"stm32\/stm32_flash.ld","new_file":"stm32\/stm32_flash.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/timofonic\/codec2-dev.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"cd9153b9cb33f28a5bb39abebe25866337114835","subject":"added linker script (bx1 18.05) with license","message":"added linker script (bx1 18.05) with license\n","repos":"tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-tensorflow\/tensorflow,Intel-Corporation\/tensorflow,frreiss\/tensorflow-fred,petewarden\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-tensorflow\/tensorflow,paolodedios\/tensorflow,annarev\/tensorflow,petewarden\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,annarev\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,tensorflow\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,frreiss\/tensorflow-fred,sarvex\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,annarev\/tensorflow,Intel-tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-experimental_link_static_libraries_once,yongtang\/tensorflow,sarvex\/tensorflow,gautam1858\/tensorflow,frreiss\/tensorflow-fred,karllessard\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-Corporation\/tensorflow,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,karllessard\/tensorflow,frreiss\/tensorflow-fred,paolodedios\/tensorflow,annarev\/tensorflow,paolodedios\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,gautam1858\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_tf_optimizer,petewarden\/tensorflow,annarev\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,sarvex\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow,annarev\/tensorflow,yongtang\/tensorflow,frreiss\/tensorflow-fred,paolodedios\/tensorflow,petewarden\/tensorflow,paolodedios\/tensorflow,gautam1858\/tensorflow,Intel-tensorflow\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_saved_model,paolodedios\/tensorflow,petewarden\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,gautam1858\/tensorflow,Intel-Corporation\/tensorflow,sarvex\/tensorflow,Intel-Corporation\/tensorflow,karllessard\/tensorflow,petewarden\/tensorflow,Intel-Corporation\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,yongtang\/tensorflow,annarev\/tensorflow,frreiss\/tensorflow-fred,annarev\/tensorflow,annarev\/tensorflow,yongtang\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,karllessard\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_saved_model,sarvex\/tensorflow,petewarden\/tensorflow,gautam1858\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,sarvex\/tensorflow,Intel-Corporation\/tensorflow,gautam1858\/tensorflow,yongtang\/tensorflow,Intel-Corporation\/tensorflow,Intel-tensorflow\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,gautam1858\/tensorflow,yongtang\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow,petewarden\/tensorflow,petewarden\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow,tensorflow\/tensorflow,karllessard\/tensorflow,Intel-tensorflow\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow,sarvex\/tensorflow,sarvex\/tensorflow","old_file":"tensorflow\/lite\/micro\/tools\/make\/targets\/ceva\/CEVA_BX1_TFLM_18.0.5.ld","new_file":"tensorflow\/lite\/micro\/tools\/make\/targets\/ceva\/CEVA_BX1_TFLM_18.0.5.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/tensorflow\/tensorflow-experimental_link_static_libraries_once.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"64e4c045b48453cc87ac4abc3792e24b211f3fe6","subject":"added teensy linkerscript","message":"added teensy linkerscript\n","repos":"hdznrrd\/braindump","old_file":"programming\/embedded\/arm\/freescale-cortex-m4-teensy3.1\/snippets\/mk20dx256.ld","new_file":"programming\/embedded\/arm\/freescale-cortex-m4-teensy3.1\/snippets\/mk20dx256.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/hdznrrd\/braindump.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"50785a7ca2d06c0ce471d45857a85d614d973174","subject":" Adding placeholder linker script for BL","message":" Adding placeholder linker script for BL\n","repos":"MickMad\/ArduinoCore-samd,MickMad\/ArduinoCore-samd","old_file":"variants\/arduino_zero\/linker_scripts\/gcc\/flash_with_bootloader.ld","new_file":"variants\/arduino_zero\/linker_scripts\/gcc\/flash_with_bootloader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/MickMad\/ArduinoCore-samd.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"39132f37f15fee2f4444e84cc8c73f7338745398","subject":"playground\/oses\/rust-os\/autobuild\/src\/arch\/x86_64\/linker.ld","message":"playground\/oses\/rust-os\/autobuild\/src\/arch\/x86_64\/linker.ld\n","repos":"sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis","old_file":"playground\/oses\/rust-os\/autobuild\/src\/arch\/x86_64\/linker.ld","new_file":"playground\/oses\/rust-os\/autobuild\/src\/arch\/x86_64\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/sharkspeed\/dororis.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"624d34af2d7c9ce9f253dbea0f7f694166a13157","subject":"LPCCAPPUCCINO] initial port LPCCAPPUCCINO is the breakboard that has LPC11U37, https:\/\/strawberry-linux.com\/catalog\/items?code=12045 Schematic: https:\/\/strawberry-linux.com\/pub\/cappuccino-sch.pdf","message":"LPCCAPPUCCINO] initial port\nLPCCAPPUCCINO is the breakboard that has LPC11U37,\nhttps:\/\/strawberry-linux.com\/catalog\/items?code=12045\nSchematic:\nhttps:\/\/strawberry-linux.com\/pub\/cappuccino-sch.pdf\n","repos":"Psykar\/kubos,kubostech\/KubOS,kubostech\/KubOS,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos","old_file":"TARGET_NXP\/TARGET_LPC11UXX\/TOOLCHAIN_GCC_ARM\/TARGET_LPCCAPPUCCINO\/LPC11U37.ld","new_file":"TARGET_NXP\/TARGET_LPC11UXX\/TOOLCHAIN_GCC_ARM\/TARGET_LPCCAPPUCCINO\/LPC11U37.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Psykar\/kubos.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"2734e8176eba0dc8870a43ed41c0aa3a2f081df3","subject":"needs underscore","message":"needs underscore\n","repos":"paolodedios\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,karllessard\/tensorflow,tensorflow\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-tensorflow\/tensorflow,yongtang\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,yongtang\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,paolodedios\/tensorflow,yongtang\/tensorflow,karllessard\/tensorflow,tensorflow\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-Corporation\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,yongtang\/tensorflow,Intel-Corporation\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow,paolodedios\/tensorflow,paolodedios\/tensorflow,yongtang\/tensorflow,gautam1858\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,karllessard\/tensorflow,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,yongtang\/tensorflow,gautam1858\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_tf_optimizer,yongtang\/tensorflow,karllessard\/tensorflow,yongtang\/tensorflow,gautam1858\/tensorflow,Intel-tensorflow\/tensorflow,yongtang\/tensorflow,Intel-Corporation\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_saved_model,Intel-tensorflow\/tensorflow,Intel-tensorflow\/tensorflow,gautam1858\/tensorflow,paolodedios\/tensorflow,Intel-Corporation\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,karllessard\/tensorflow,tensorflow\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow,gautam1858\/tensorflow,Intel-tensorflow\/tensorflow,paolodedios\/tensorflow,gautam1858\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_tf_optimizer,karllessard\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow,gautam1858\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-experimental_link_static_libraries_once,Intel-Corporation\/tensorflow,gautam1858\/tensorflow,Intel-Corporation\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,paolodedios\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-pywrap_saved_model,tensorflow\/tensorflow-pywrap_tf_optimizer,tensorflow\/tensorflow-experimental_link_static_libraries_once,karllessard\/tensorflow","old_file":"tensorflow\/tf_private_symbols.lds","new_file":"tensorflow\/tf_private_symbols.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/tensorflow\/tensorflow-experimental_link_static_libraries_once.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"8f6f2b3505daa7db61b26405eaee9a4b6b5aa74b","subject":"Forgot to include this debug linker script.","message":"Forgot to include this debug linker script.\n\n\nFormer-commit-id: 0567531f9e8bed863f44ac2320d3016059aff755\n","repos":"chipKIT32\/chipkit-core,majenkotech\/chipKIT-core,adamwolf\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,chipKIT32\/chipkit-core,adamwolf\/chipKIT-core,adamwolf\/chipKIT-core,EmbeddedMan\/chipKIT-core,chipKIT32\/chipkit-core,adamwolf\/chipKIT-core,majenkotech\/chipKIT-core,UECIDE\/chipKIT-core,pontech\/chipKIT-core,ricklon\/chipKIT-core,majenkotech\/chipKIT-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core,majenkotech\/chipKIT-core,UECIDE\/chipKIT-core,pontech\/chipKIT-core,adamwolf\/chipKIT-core,pontech\/chipKIT-core,majenkotech\/chipKIT-core,pontech\/chipKIT-core,ricklon\/chipKIT-core,EmbeddedMan\/chipKIT-core,chipKIT32\/chipkit-core,EmbeddedMan\/chipKIT-core,ricklon\/chipKIT-core,UECIDE\/chipKIT-core,adamwolf\/chipKIT-core,adamwolf\/chipKIT-core,ricklon\/chipKIT-core,pontech\/chipKIT-core,EmbeddedMan\/chipKIT-core,EmbeddedMan\/chipKIT-core,UECIDE\/chipKIT-core,EmbeddedMan\/chipKIT-core,chipKIT32\/chipkit-core,UECIDE\/chipKIT-core,EmbeddedMan\/chipKIT-core","old_file":"pic32\/cores\/pic32\/chipKIT-application-32MX250F128-nobootloader.ld","new_file":"pic32\/cores\/pic32\/chipKIT-application-32MX250F128-nobootloader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/majenkotech\/chipKIT-core.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"d26039adc6f93d13fd1ca6f5f1697d622042b9b8","subject":"add ldoc config","message":"add ldoc config\n","repos":"remakeelectric\/lua-libmodbus","old_file":"config.ld","new_file":"config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/remakeelectric\/lua-libmodbus.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"d41ac5293a7faf0fc8dc1a83dfb3a97f4cedbfea","subject":"linker script added","message":"linker script added\n","repos":"m-rinaldi\/emuk86,m-rinaldi\/emuk86","old_file":"kernel.ld","new_file":"kernel.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/m-rinaldi\/emuk86.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"2e8ddbfa84def973d061deb269dd16f997a1b828","subject":"Add ldoc config (config.ld)","message":"Add ldoc config (config.ld)\n","repos":"Xamla\/torch-moveit","old_file":"config.ld","new_file":"config.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Xamla\/torch-moveit.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"046d84c37fe0f1cdd5e1a46ff168b9a887193bcc","subject":"keeping a spare copy of the flash loader script in case I have to reinstall the board package.","message":"keeping a spare copy of the flash loader script in case I have to reinstall the board package.\n","repos":"980f\/dro,980f\/dro,980f\/dro,980f\/dro","old_file":"arduino\/flash.ld","new_file":"arduino\/flash.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/980f\/dro.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"25d356276d8a0292ce3e304499172d4be170f994","subject":"Set correct size\/length for FLASH memory region","message":"Set correct size\/length for FLASH memory region\n","repos":"mbains\/bare-metal-arm,firebitsbr\/bare-metal-arm,payne92\/bare-metal-arm,mbains\/bare-metal-arm,payne92\/bare-metal-arm,firebitsbr\/bare-metal-arm,payne92\/bare-metal-arm","old_file":"mkl25z4.ld","new_file":"mkl25z4.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mbains\/bare-metal-arm.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"c9739f4a51b858aa8db5a823edd677fe845beb61","subject":"NCS36510 - decrease reserved heap space","message":"NCS36510 - decrease reserved heap space\n\nDecrease the minimum space reserved for the heap from 16K down to\n2K for GCC. This does not have an effect on the actual heap size since\nthe heap takes up all free RAM. This just allows code to compile in\nconfigurations where the heap is smaller than 16K.\n","repos":"pradeep-gr\/mbed-os5-onsemi,pradeep-gr\/mbed-os5-onsemi,radhika-raghavendran\/mbed-os5.1-onsemi,karsev\/mbed-os,pradeep-gr\/mbed-os5-onsemi,kjbracey-arm\/mbed,mikaleppanen\/mbed-os,andcor02\/mbed-os,RonEld\/mbed,nvlsianpu\/mbed,mmorenobarm\/mbed-os,adustm\/mbed,mmorenobarm\/mbed-os,RonEld\/mbed,pradeep-gr\/mbed-os5-onsemi,YarivCol\/mbed-os,arostm\/mbed-os,fahhem\/mbed-os,arostm\/mbed-os,netzimme\/mbed-os,NXPmicro\/mbed,RonEld\/mbed,fahhem\/mbed-os,theotherjimmy\/mbed,nvlsianpu\/mbed,bulislaw\/mbed-os,maximmbed\/mbed,mbedmicro\/mbed,Archcady\/mbed-os,svogl\/mbed-os,screamerbg\/mbed,Archcady\/mbed-os,fanghuaqi\/mbed,cvtsi2sd\/mbed-os,andcor02\/mbed-os,kl-cruz\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,adamgreen\/mbed,RonEld\/mbed,fahhem\/mbed-os,cvtsi2sd\/mbed-os,infinnovation\/mbed-os,RonEld\/mbed,CalSol\/mbed,svogl\/mbed-os,HeadsUpDisplayInc\/mbed,YarivCol\/mbed-os,bcostm\/mbed-os,CalSol\/mbed,mmorenobarm\/mbed-os,mbedmicro\/mbed,catiedev\/mbed-os,ryankurte\/mbed-os,betzw\/mbed-os,catiedev\/mbed-os,cvtsi2sd\/mbed-os,j-greffe\/mbed-os,NXPmicro\/mbed,betzw\/mbed-os,mazimkhan\/mbed-os,HeadsUpDisplayInc\/mbed,mikaleppanen\/mbed-os,nRFMesh\/mbed-os,c1728p9\/mbed-os,Archcady\/mbed-os,mbedmicro\/mbed,betzw\/mbed-os,svogl\/mbed-os,YarivCol\/mbed-os,HeadsUpDisplayInc\/mbed,bulislaw\/mbed-os,ryankurte\/mbed-os,karsev\/mbed-os,arostm\/mbed-os,mazimkhan\/mbed-os,kl-cruz\/mbed-os,monkiineko\/mbed-os,netzimme\/mbed-os,theotherjimmy\/mbed,svogl\/mbed-os,andcor02\/mbed-os,catiedev\/mbed-os,mazimkhan\/mbed-os,bcostm\/mbed-os,netzimme\/mbed-os,arostm\/mbed-os,Archcady\/mbed-os,adustm\/mbed,adamgreen\/mbed,CalSol\/mbed,adamgreen\/mbed,karsev\/mbed-os,monkiineko\/mbed-os,infinnovation\/mbed-os,betzw\/mbed-os,andcor02\/mbed-os,svogl\/mbed-os,mazimkhan\/mbed-os,theotherjimmy\/mbed,HeadsUpDisplayInc\/mbed,fahhem\/mbed-os,screamerbg\/mbed,nvlsianpu\/mbed,fanghuaqi\/mbed,HeadsUpDisplayInc\/mbed,ryankurte\/mbed-os,j-greffe\/mbed-os,nvlsianpu\/mbed,kjbracey-arm\/mbed,YarivCol\/mbed-os,cvtsi2sd\/mbed-os,bulislaw\/mbed-os,catiedev\/mbed-os,bulislaw\/mbed-os,screamerbg\/mbed,mmorenobarm\/mbed-os,j-greffe\/mbed-os,adamgreen\/mbed,c1728p9\/mbed-os,YarivCol\/mbed-os,infinnovation\/mbed-os,c1728p9\/mbed-os,adustm\/mbed,bcostm\/mbed-os,andcor02\/mbed-os,arostm\/mbed-os,maximmbed\/mbed,pradeep-gr\/mbed-os5-onsemi,fanghuaqi\/mbed,fahhem\/mbed-os,YarivCol\/mbed-os,nRFMesh\/mbed-os,kjbracey-arm\/mbed,andcor02\/mbed-os,kjbracey-arm\/mbed,HeadsUpDisplayInc\/mbed,pradeep-gr\/mbed-os5-onsemi,maximmbed\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,fanghuaqi\/mbed,infinnovation\/mbed-os,fanghuaqi\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,c1728p9\/mbed-os,ryankurte\/mbed-os,mbedmicro\/mbed,catiedev\/mbed-os,c1728p9\/mbed-os,maximmbed\/mbed,adustm\/mbed,screamerbg\/mbed,catiedev\/mbed-os,nRFMesh\/mbed-os,mikaleppanen\/mbed-os,c1728p9\/mbed-os,bulislaw\/mbed-os,mazimkhan\/mbed-os,nRFMesh\/mbed-os,bcostm\/mbed-os,netzimme\/mbed-os,RonEld\/mbed,maximmbed\/mbed,cvtsi2sd\/mbed-os,monkiineko\/mbed-os,kl-cruz\/mbed-os,NXPmicro\/mbed,j-greffe\/mbed-os,j-greffe\/mbed-os,nvlsianpu\/mbed,betzw\/mbed-os,netzimme\/mbed-os,betzw\/mbed-os,CalSol\/mbed,karsev\/mbed-os,kl-cruz\/mbed-os,mikaleppanen\/mbed-os,adustm\/mbed,mazimkhan\/mbed-os,arostm\/mbed-os,screamerbg\/mbed,adamgreen\/mbed,monkiineko\/mbed-os,svogl\/mbed-os,ryankurte\/mbed-os,monkiineko\/mbed-os,bcostm\/mbed-os,karsev\/mbed-os,fahhem\/mbed-os,mmorenobarm\/mbed-os,screamerbg\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,adustm\/mbed,maximmbed\/mbed,nRFMesh\/mbed-os,infinnovation\/mbed-os,bcostm\/mbed-os,nRFMesh\/mbed-os,Archcady\/mbed-os,CalSol\/mbed,mmorenobarm\/mbed-os,mikaleppanen\/mbed-os,NXPmicro\/mbed,theotherjimmy\/mbed,Archcady\/mbed-os,monkiineko\/mbed-os,theotherjimmy\/mbed,bulislaw\/mbed-os,kl-cruz\/mbed-os,cvtsi2sd\/mbed-os,karsev\/mbed-os,mikaleppanen\/mbed-os,kl-cruz\/mbed-os,ryankurte\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,adamgreen\/mbed,j-greffe\/mbed-os,mbedmicro\/mbed,NXPmicro\/mbed,netzimme\/mbed-os,infinnovation\/mbed-os,nvlsianpu\/mbed,NXPmicro\/mbed,CalSol\/mbed,theotherjimmy\/mbed","old_file":"targets\/cmsis\/TARGET_ONSEMI\/TARGET_NCS36510\/TOOLCHAIN_GCC_ARM\/NCS36510.ld","new_file":"targets\/cmsis\/TARGET_ONSEMI\/TARGET_NCS36510\/TOOLCHAIN_GCC_ARM\/NCS36510.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/RonEld\/mbed.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"f11a8eb47eaae187ca0e87e8a0768d4fed6533c0","subject":"Add default linker script for CI builds","message":"Add default linker script for CI builds\n","repos":"Adam5Wu\/Arduino,Adam5Wu\/Arduino,Adam5Wu\/Arduino,Adam5Wu\/Arduino,Adam5Wu\/Arduino","old_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_file":"tools\/sdk\/ld\/eagle.app.v6.common.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Adam5Wu\/Arduino.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"4d99513bdbc3022e6b8969c1cd4dfae984d3c939","subject":"bootloader: Fix crash enabling flash encryption","message":"bootloader: Fix crash enabling flash encryption\n\nRegression in 9c715d7946a9595bad53307cf0a141d4226d0a5a\n","repos":"mashaoze\/esp-idf,espressif\/esp-idf,armada-ai\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,espressif\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,www220\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,espressif\/esp-idf,armada-ai\/esp-idf,mashaoze\/esp-idf,www220\/esp-idf,armada-ai\/esp-idf,armada-ai\/esp-idf,espressif\/esp-idf","old_file":"components\/bootloader\/subproject\/main\/esp32.bootloader.ld","new_file":"components\/bootloader\/subproject\/main\/esp32.bootloader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mashaoze\/esp-idf.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"b7251cd666c362f5e616f42cbb37ffde32d294a5","subject":"Add workaround for bug in spike","message":"Add workaround for bug in spike\n","repos":"jeffreyrogers\/pv6,jeffreyrogers\/pv6,jeffreyrogers\/pv6","old_file":"scripts\/arch\/riscv\/kernel.ld","new_file":"scripts\/arch\/riscv\/kernel.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/jeffreyrogers\/pv6.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"2eaf99cc07879e8a4cd4ec2aed41e32522bc6dce","subject":"Create link.ld","message":"Create link.ld","repos":"TheJJ100100\/Q-OS,TheJJ100100\/Q-OS,TheJJ100100\/Q-OS","old_file":"kernel\/link.ld","new_file":"kernel\/link.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/TheJJ100100\/Q-OS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"f313d483017fb57759da3d17da1d1d119367e777","subject":"Fix bad linker","message":"Fix bad linker\n","repos":"Tutul-\/tumuxOS,Tutul-\/tumuxOS,Tutul-\/tumuxOS","old_file":"src\/kernel\/arch\/x86\/linker.ld","new_file":"src\/kernel\/arch\/x86\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Tutul-\/tumuxOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"383cfb7ea93698c8f834ffdd3730fdcb5ff3143c","subject":"Added linker script for STM32F103xD line.","message":"Added linker script for STM32F103xD line.\n\ngit-svn-id: 30f789d7039adee4ab6dc5f7dbec2df9251e516b@4466 35acf78f-673a-0410-8e92-d51de3d6d3f4\n","repos":"roboknight\/chibios-lpc43xx,roboknight\/chibios-lpc43xx","old_file":"os\/ports\/GCC\/ARMCMx\/STM32F1xx\/ld\/STM32F103xD.ld","new_file":"os\/ports\/GCC\/ARMCMx\/STM32F1xx\/ld\/STM32F103xD.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/roboknight\/chibios-lpc43xx.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"0c48fb48b59ed599bfd20bda3270b76b9e9b0ef0","subject":"Moved constructor pointers back to own section","message":"Moved constructor pointers back to own section\n","repos":"daveshep666\/davos,daveshep666\/davos","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/daveshep666\/davos.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"e0fa457cbcae388c5cd5127221bee20e84ea3f2f","subject":"[#120927185] Fix library_info.ld to follow Nordic SDK 12 conventions","message":"[#120927185] Fix library_info.ld to follow Nordic SDK 12 conventions\n","repos":"PulseOn\/Embedded_Build_System","old_file":"library_info.ld","new_file":"library_info.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/PulseOn\/Embedded_Build_System.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"eef753a933ee90839c8d531fae8818c922d2dcdd","subject":"cpu\/sam0: adapt support for samd21j18a with bootloader","message":"cpu\/sam0: adapt support for samd21j18a with bootloader\n","repos":"lazytech-org\/RIOT,x3ro\/RIOT,gebart\/RIOT,Josar\/RIOT,A-Paul\/RIOT,OlegHahm\/RIOT,beurdouche\/RIOT,ant9000\/RIOT,toonst\/RIOT,LudwigKnuepfer\/RIOT,aeneby\/RIOT,OlegHahm\/RIOT,Josar\/RIOT,yogo1212\/RIOT,authmillenon\/RIOT,x3ro\/RIOT,authmillenon\/RIOT,BytesGalore\/RIOT,gebart\/RIOT,BytesGalore\/RIOT,x3ro\/RIOT,kbumsik\/RIOT,LudwigKnuepfer\/RIOT,toonst\/RIOT,kbumsik\/RIOT,ks156\/RIOT,yogo1212\/RIOT,aeneby\/RIOT,basilfx\/RIOT,kaspar030\/RIOT,rfuentess\/RIOT,BytesGalore\/RIOT,biboc\/RIOT,kYc0o\/RIOT,ks156\/RIOT,avmelnikoff\/RIOT,immesys\/RiSyn,gebart\/RIOT,lazytech-org\/RIOT,A-Paul\/RIOT,yogo1212\/RIOT,OTAkeys\/RIOT,basilfx\/RIOT,basilfx\/RIOT,toonst\/RIOT,beurdouche\/RIOT,kbumsik\/RIOT,kaspar030\/RIOT,kbumsik\/RIOT,roberthartung\/RIOT,RIOT-OS\/RIOT,OTAkeys\/RIOT,biboc\/RIOT,adrianghc\/RIOT,authmillenon\/RIOT,josephnoir\/RIOT,RIOT-OS\/RIOT,cladmi\/RIOT,authmillenon\/RIOT,mtausig\/RIOT,immesys\/RiSyn,rfuentess\/RIOT,mfrey\/RIOT,LudwigKnuepfer\/RIOT,OTAkeys\/RIOT,neiljay\/RIOT,hamilton-mote\/RIOT-OS,jasonatran\/RIOT,mtausig\/RIOT,LudwigKnuepfer\/RIOT,LudwigOrtmann\/RIOT,LudwigOrtmann\/RIOT,ant9000\/RIOT,hamilton-mote\/RIOT-OS,miri64\/RIOT,mtausig\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,lazytech-org\/RIOT,ks156\/RIOT,adrianghc\/RIOT,roberthartung\/RIOT,Josar\/RIOT,jasonatran\/RIOT,kYc0o\/RIOT,OlegHahm\/RIOT,immesys\/RiSyn,ant9000\/RIOT,ks156\/RIOT,BytesGalore\/RIOT,aeneby\/RIOT,A-Paul\/RIOT,smlng\/RIOT,immesys\/RiSyn,jasonatran\/RIOT,BytesGalore\/RIOT,kaspar030\/RIOT,neiljay\/RIOT,josephnoir\/RIOT,beurdouche\/RIOT,hamilton-mote\/RIOT-OS,neiljay\/RIOT,kYc0o\/RIOT,avmelnikoff\/RIOT,kaspar030\/RIOT,mfrey\/RIOT,beurdouche\/RIOT,aeneby\/RIOT,biboc\/RIOT,ant9000\/RIOT,miri64\/RIOT,LudwigOrtmann\/RIOT,cladmi\/RIOT,josephnoir\/RIOT,kaspar030\/RIOT,mtausig\/RIOT,gebart\/RIOT,miri64\/RIOT,x3ro\/RIOT,adrianghc\/RIOT,yogo1212\/RIOT,Josar\/RIOT,authmillenon\/RIOT,rfuentess\/RIOT,beurdouche\/RIOT,avmelnikoff\/RIOT,mtausig\/RIOT,smlng\/RIOT,basilfx\/RIOT,yogo1212\/RIOT,smlng\/RIOT,avmelnikoff\/RIOT,miri64\/RIOT,adrianghc\/RIOT,A-Paul\/RIOT,adrianghc\/RIOT,cladmi\/RIOT,neiljay\/RIOT,josephnoir\/RIOT,lazytech-org\/RIOT,biboc\/RIOT,aeneby\/RIOT,hamilton-mote\/RIOT-OS,mfrey\/RIOT,josephnoir\/RIOT,toonst\/RIOT,roberthartung\/RIOT,neiljay\/RIOT,basilfx\/RIOT,avmelnikoff\/RIOT,mfrey\/RIOT,ks156\/RIOT,immesys\/RiSyn,RIOT-OS\/RIOT,mfrey\/RIOT,toonst\/RIOT,OTAkeys\/RIOT,lazytech-org\/RIOT,x3ro\/RIOT,kbumsik\/RIOT,RIOT-OS\/RIOT,jasonatran\/RIOT,cladmi\/RIOT,smlng\/RIOT,A-Paul\/RIOT,hamilton-mote\/RIOT-OS,cladmi\/RIOT,LudwigOrtmann\/RIOT,roberthartung\/RIOT,LudwigKnuepfer\/RIOT,LudwigOrtmann\/RIOT,roberthartung\/RIOT,LudwigOrtmann\/RIOT,OTAkeys\/RIOT,kYc0o\/RIOT,biboc\/RIOT,Josar\/RIOT,OlegHahm\/RIOT,immesys\/RiSyn,ant9000\/RIOT,gebart\/RIOT,jasonatran\/RIOT,RIOT-OS\/RIOT,OlegHahm\/RIOT,yogo1212\/RIOT,rfuentess\/RIOT,kYc0o\/RIOT,miri64\/RIOT,smlng\/RIOT","old_file":"cpu\/sam0_common\/ldscripts\/samd21j18a_arduino_bootloader.ld","new_file":"cpu\/sam0_common\/ldscripts\/samd21j18a_arduino_bootloader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Josar\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"ae5a2ad169ee637eeaf9f5edc30eb89726f6bc5f","subject":"Create tlink_ap4.ld","message":"Create tlink_ap4.ld","repos":"izard\/RTBench,izard\/RTBench","old_file":"tools\/src\/disturber\/baremetal\/smallos\/tlink_ap4.ld","new_file":"tools\/src\/disturber\/baremetal\/smallos\/tlink_ap4.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/izard\/RTBench.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"1c9b29c0194860eecd15bbfaaf2dd4314fd037a4","subject":"Our little linker script","message":"Our little linker script\n","repos":"nicholatian\/saturn,nicholatian\/saturn,nicholatian\/saturn","old_file":"util\/gba.ld","new_file":"util\/gba.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/nicholatian\/saturn.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"58f1e30f2e22edbfc381a864552500d53769af79","subject":"Oops, forgot to tell `ld` where to start looking","message":"Oops, forgot to tell `ld` where to start looking\n","repos":"Gen-OS\/bbb-proof-of-concept,Gen-OS\/bbb-proof-of-concept,Gen-OS\/bbb-proof-of-concept","old_file":"src\/arch\/thumbv7a\/linker.ld","new_file":"src\/arch\/thumbv7a\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Gen-OS\/bbb-proof-of-concept.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"b554c8c1a5b83f01390378ade8062f3231af6b79","subject":"Add lds","message":"Add lds\n","repos":"mycspring\/ClaveChain,mycspring\/ClaveChain","old_file":"Clave\/Enclave\/Enclave.lds","new_file":"Clave\/Enclave\/Enclave.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mycspring\/ClaveChain.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3bedee0259b1f01a6a2e2ad5f774243252e6e45f","subject":"playground\/operationsystems\/rust-os\/handwork\/linker.ld","message":"playground\/operationsystems\/rust-os\/handwork\/linker.ld\n","repos":"sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis,sharkspeed\/dororis","old_file":"playground\/operationsystems\/rust-os\/handwork\/linker.ld","new_file":"playground\/operationsystems\/rust-os\/handwork\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/sharkspeed\/dororis.git\/': The requested URL returned error: 403\n","license":"bsd-2-clause","lang":"Linker Script"}
{"commit":"de0ba56daaf4ea3c442274b0473ac203ce139566","subject":"Add linker file for multiboot headers and boot file","message":"Add linker file for multiboot headers and boot file\n","repos":"awesomeaniruddh\/sOS","old_file":"linker.ld","new_file":"linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/awesomeaniruddh\/sOS.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"a59d0dd59292bfa626306d2d077d3c35e7f6aae8","subject":"Added the linker script for UCB-BF512.","message":"Added the linker script for UCB-BF512.\n","repos":"shintamainjp\/MISO-DEV-2014,shintamainjp\/MISO-DEV-2014,shintamainjp\/MISO-DEV-2014,shintamainjp\/MISO-DEV-2014","old_file":"src\/uart_test\/ucb-bf512.ld","new_file":"src\/uart_test\/ucb-bf512.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/shintamainjp\/MISO-DEV-2014.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"1c82cbc5703a2785c2251cc19b3ffae413122d77","subject":"firmware: netedev: linker.ld: fix eth_control section position","message":"firmware: netedev: linker.ld: fix eth_control section position\n","repos":"kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa","old_file":"firmware\/common\/netdev\/linker.ld","new_file":"firmware\/common\/netdev\/linker.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kalray\/odp-mppa.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"35efc5aaa1b99414cac4babb06aa9f167ad0f617","subject":"Updated linker script to reserve space for BootRAM","message":"Updated linker script to reserve space for BootRAM\n\nUpdated linker script to reserve space for BootRAM at 0x138\n","repos":"masaohamanaka\/mbed,mazimkhan\/mbed-os,bentwire\/mbed,pradeep-gr\/mbed-os5-onsemi,NitinBhaskar\/mbed,Willem23\/mbed,HeadsUpDisplayInc\/mbed,RonEld\/mbed,K4zuki\/mbed,YarivCol\/mbed-os,brstew\/MBED-BUILD,kjbracey-arm\/mbed,catiedev\/mbed-os,logost\/mbed,naves-thiago\/mbed-midi,infinnovation\/mbed-os,fahhem\/mbed-os,mazimkhan\/mbed-os,monkiineko\/mbed-os,mbedmicro\/mbed,netzimme\/mbed-os,bcostm\/mbed-os,NXPmicro\/mbed,netzimme\/mbed-os,bikeNomad\/mbed,tung7970\/mbed-os,betzw\/mbed-os,karsev\/mbed-os,mbedmicro\/mbed,jferreir\/mbed,infinnovation\/mbed-os,betzw\/mbed-os,pedromes\/mbed,alertby\/mbed,svogl\/mbed-os,ban4jp\/mbed,hwfwgrp\/mbed,Archcady\/mbed-os,Timmmm\/mbed,nvlsianpu\/mbed,bcostm\/mbed-os,catiedev\/mbed-os,monkiineko\/mbed-os,nRFMesh\/mbed-os,masaohamanaka\/mbed,svastm\/mbed,svogl\/mbed-os,masaohamanaka\/mbed,FranklyDev\/mbed,karsev\/mbed-os,j-greffe\/mbed-os,bulislaw\/mbed-os,adustm\/mbed,al177\/mbed,betzw\/mbed-os,ARM-software\/mbed-beetle,xcrespo\/mbed,getopenmono\/mbed,kpurusho\/mbed,Sweet-Peas\/mbed,JasonHow44\/mbed,screamerbg\/mbed,larks\/mbed,fanghuaqi\/mbed,kl-cruz\/mbed-os,pedromes\/mbed,rosterloh\/mbed,hwfwgrp\/mbed,karsev\/mbed-os,monkiineko\/mbed-os,xcrespo\/mbed,netzimme\/mbed-os,struempelix\/mbed,jpbrucker\/mbed,Marcomissyou\/mbed,bikeNomad\/mbed,Willem23\/mbed,geky\/mbed,svastm\/mbed,Archcady\/mbed-os,screamerbg\/mbed,EmuxEvans\/mbed,fahhem\/mbed-os,catiedev\/mbed-os,mnlipp\/mbed,ryankurte\/mbed-os,adamgreen\/mbed,nabilbendafi\/mbed,brstew\/MBED-BUILD,masaohamanaka\/mbed,GustavWi\/mbed,ban4jp\/mbed,fvincenzo\/mbed-os,larks\/mbed,NXPmicro\/mbed,Tiryoh\/mbed,Tiryoh\/mbed,svogl\/mbed-os,autopulated\/mbed,fvincenzo\/mbed-os,ban4jp\/mbed,Shengliang\/mbed,monkiineko\/mbed-os,wodji\/mbed,jamesadevine\/mbed,rgrover\/mbed,jeremybrodt\/mbed,xcrespo\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,catiedev\/mbed-os,wodji\/mbed,kpurusho\/mbed,kl-cruz\/mbed-os,YarivCol\/mbed-os,nRFMesh\/mbed-os,Sweet-Peas\/mbed,bcostm\/mbed-os,Shengliang\/mbed,pedromes\/mbed,K4zuki\/mbed,adamgreen\/mbed,FranklyDev\/mbed,GustavWi\/mbed,pradeep-gr\/mbed-os5-onsemi,naves-thiago\/mbed-midi,bulislaw\/mbed-os,andcor02\/mbed-os,theotherjimmy\/mbed,autopulated\/mbed,Archcady\/mbed-os,c1728p9\/mbed-os,mazimkhan\/mbed-os,nvlsianpu\/mbed,masaohamanaka\/mbed,logost\/mbed,Shengliang\/mbed,Marcomissyou\/mbed,theotherjimmy\/mbed,FranklyDev\/mbed,bentwire\/mbed,struempelix\/mbed,karsev\/mbed-os,al177\/mbed,Timmmm\/mbed,fahhem\/mbed-os,masaohamanaka\/mbed,jpbrucker\/mbed,RonEld\/mbed,rosterloh\/mbed,EmuxEvans\/mbed,CalSol\/mbed,JasonHow44\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,getopenmono\/mbed,alertby\/mbed,pi19404\/mbed,screamerbg\/mbed,c1728p9\/mbed-os,EmuxEvans\/mbed,Marcomissyou\/mbed,larks\/mbed,andcor02\/mbed-os,Willem23\/mbed,pradeep-gr\/mbed-os5-onsemi,tung7970\/mbed-os-1,andcor02\/mbed-os,Timmmm\/mbed,HeadsUpDisplayInc\/mbed,struempelix\/mbed,ARM-software\/mbed-beetle,bentwire\/mbed,svogl\/mbed-os,HeadsUpDisplayInc\/mbed,arostm\/mbed-os,jeremybrodt\/mbed,larks\/mbed,Timmmm\/mbed,Archcady\/mbed-os,jferreir\/mbed,mnlipp\/mbed,naves-thiago\/mbed-midi,CalSol\/mbed,brstew\/MBED-BUILD,devanlai\/mbed,JasonHow44\/mbed,sam-geek\/mbed,DanKupiniak\/mbed,rosterloh\/mbed,pradeep-gr\/mbed-os5-onsemi,jeremybrodt\/mbed,adustm\/mbed,jferreir\/mbed,adamgreen\/mbed,nvlsianpu\/mbed,Archcady\/mbed-os,mmorenobarm\/mbed-os,RonEld\/mbed,jpbrucker\/mbed,naves-thiago\/mbed-midi,mmorenobarm\/mbed-os,Willem23\/mbed,logost\/mbed,netzimme\/mbed-os,CalSol\/mbed,catiedev\/mbed-os,c1728p9\/mbed-os,fanghuaqi\/mbed,fpiot\/mbed-ats,devanlai\/mbed,bcostm\/mbed-os,CalSol\/mbed,fvincenzo\/mbed-os,mnlipp\/mbed,maximmbed\/mbed,fanghuaqi\/mbed,mnlipp\/mbed,andcor02\/mbed-os,JasonHow44\/mbed,catiedev\/mbed-os,karsev\/mbed-os,ban4jp\/mbed,kl-cruz\/mbed-os,sam-geek\/mbed,kjbracey-arm\/mbed,sam-geek\/mbed,betzw\/mbed-os,devanlai\/mbed,kl-cruz\/mbed-os,kpurusho\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,svastm\/mbed,ryankurte\/mbed-os,GustavWi\/mbed,bcostm\/mbed-os,fpiot\/mbed-ats,jeremybrodt\/mbed,maximmbed\/mbed,nabilbendafi\/mbed,andreaslarssonublox\/mbed,pi19404\/mbed,pbrook\/mbed,pradeep-gr\/mbed-os5-onsemi,pedromes\/mbed,getopenmono\/mbed,kpurusho\/mbed,andreaslarssonublox\/mbed,arostm\/mbed-os,rgrover\/mbed,jamesadevine\/mbed,K4zuki\/mbed,ryankurte\/mbed-os,xcrespo\/mbed,jrjang\/mbed,xcrespo\/mbed,al177\/mbed,bulislaw\/mbed-os,kl-cruz\/mbed-os,CalSol\/mbed,EmuxEvans\/mbed,FranklyDev\/mbed,naves-thiago\/mbed-midi,mbedmicro\/mbed,Sweet-Peas\/mbed,devanlai\/mbed,jamesadevine\/mbed,fvincenzo\/mbed-os,adamgreen\/mbed,al177\/mbed,bulislaw\/mbed-os,HeadsUpDisplayInc\/mbed,Shengliang\/mbed,j-greffe\/mbed-os,mnlipp\/mbed,c1728p9\/mbed-os,cvtsi2sd\/mbed-os,alertby\/mbed,adustm\/mbed,brstew\/MBED-BUILD,dbestm\/mbed,pbrook\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,YarivCol\/mbed-os,bcostm\/mbed-os,fvincenzo\/mbed-os,wodji\/mbed,cvtsi2sd\/mbed-os,mazimkhan\/mbed-os,fanghuaqi\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,autopulated\/mbed,al177\/mbed,kpurusho\/mbed,geky\/mbed,DanKupiniak\/mbed,j-greffe\/mbed-os,c1728p9\/mbed-os,jamesadevine\/mbed,infinnovation\/mbed-os,nabilbendafi\/mbed,jrjang\/mbed,adustm\/mbed,GustavWi\/mbed,geky\/mbed,Archcady\/mbed-os,maximmbed\/mbed,fanghuaqi\/mbed,bikeNomad\/mbed,pbrook\/mbed,pedromes\/mbed,arostm\/mbed-os,fpiot\/mbed-ats,brstew\/MBED-BUILD,hwfwgrp\/mbed,rosterloh\/mbed,YarivCol\/mbed-os,theotherjimmy\/mbed,maximmbed\/mbed,K4zuki\/mbed,NitinBhaskar\/mbed,bikeNomad\/mbed,cvtsi2sd\/mbed-os,svogl\/mbed-os,jferreir\/mbed,rosterloh\/mbed,NitinBhaskar\/mbed,rgrover\/mbed,RonEld\/mbed,Willem23\/mbed,devanlai\/mbed,andreaslarssonublox\/mbed,xcrespo\/mbed,mmorenobarm\/mbed-os,K4zuki\/mbed,mnlipp\/mbed,JasonHow44\/mbed,j-greffe\/mbed-os,betzw\/mbed-os,theotherjimmy\/mbed,Tiryoh\/mbed,K4zuki\/mbed,mikaleppanen\/mbed-os,RonEld\/mbed,Timmmm\/mbed,fahhem\/mbed-os,NitinBhaskar\/mbed,fahhem\/mbed-os,DanKupiniak\/mbed,cvtsi2sd\/mbed-os,logost\/mbed,bulislaw\/mbed-os,jamesadevine\/mbed,maximmbed\/mbed,andcor02\/mbed-os,dbestm\/mbed,Tiryoh\/mbed,jrjang\/mbed,logost\/mbed,jpbrucker\/mbed,alertby\/mbed,tung7970\/mbed-os,andcor02\/mbed-os,bikeNomad\/mbed,nvlsianpu\/mbed,nRFMesh\/mbed-os,Sweet-Peas\/mbed,dbestm\/mbed,svastm\/mbed,fpiot\/mbed-ats,Sweet-Peas\/mbed,naves-thiago\/mbed-midi,YarivCol\/mbed-os,logost\/mbed,NXPmicro\/mbed,dbestm\/mbed,CalSol\/mbed,ARM-software\/mbed-beetle,NXPmicro\/mbed,Tiryoh\/mbed,fahhem\/mbed-os,infinnovation\/mbed-os,pbrook\/mbed,arostm\/mbed-os,bentwire\/mbed,EmuxEvans\/mbed,RonEld\/mbed,nvlsianpu\/mbed,jrjang\/mbed,JasonHow44\/mbed,sam-geek\/mbed,andreaslarssonublox\/mbed,mmorenobarm\/mbed-os,ryankurte\/mbed-os,ARM-software\/mbed-beetle,nRFMesh\/mbed-os,karsev\/mbed-os,tung7970\/mbed-os-1,rgrover\/mbed,ban4jp\/mbed,struempelix\/mbed,maximmbed\/mbed,hwfwgrp\/mbed,dbestm\/mbed,bulislaw\/mbed-os,alertby\/mbed,jferreir\/mbed,Timmmm\/mbed,cvtsi2sd\/mbed-os,infinnovation\/mbed-os,mikaleppanen\/mbed-os,theotherjimmy\/mbed,pi19404\/mbed,kl-cruz\/mbed-os,tung7970\/mbed-os-1,mbedmicro\/mbed,nabilbendafi\/mbed,kpurusho\/mbed,struempelix\/mbed,monkiineko\/mbed-os,jamesadevine\/mbed,jpbrucker\/mbed,kjbracey-arm\/mbed,ban4jp\/mbed,hwfwgrp\/mbed,svogl\/mbed-os,jpbrucker\/mbed,pbrook\/mbed,monkiineko\/mbed-os,netzimme\/mbed-os,FranklyDev\/mbed,screamerbg\/mbed,j-greffe\/mbed-os,cvtsi2sd\/mbed-os,getopenmono\/mbed,getopenmono\/mbed,HeadsUpDisplayInc\/mbed,c1728p9\/mbed-os,mikaleppanen\/mbed-os,DanKupiniak\/mbed,jferreir\/mbed,YarivCol\/mbed-os,wodji\/mbed,nvlsianpu\/mbed,larks\/mbed,wodji\/mbed,GustavWi\/mbed,arostm\/mbed-os,geky\/mbed,rgrover\/mbed,NitinBhaskar\/mbed,getopenmono\/mbed,NXPmicro\/mbed,tung7970\/mbed-os,andreaslarssonublox\/mbed,alertby\/mbed,wodji\/mbed,geky\/mbed,arostm\/mbed-os,rosterloh\/mbed,tung7970\/mbed-os,tung7970\/mbed-os,struempelix\/mbed,mmorenobarm\/mbed-os,mikaleppanen\/mbed-os,larks\/mbed,Shengliang\/mbed,mbedmicro\/mbed,mikaleppanen\/mbed-os,nRFMesh\/mbed-os,screamerbg\/mbed,Marcomissyou\/mbed,brstew\/MBED-BUILD,jeremybrodt\/mbed,jrjang\/mbed,HeadsUpDisplayInc\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,nabilbendafi\/mbed,dbestm\/mbed,Shengliang\/mbed,adamgreen\/mbed,adustm\/mbed,EmuxEvans\/mbed,nRFMesh\/mbed-os,mazimkhan\/mbed-os,ryankurte\/mbed-os,Tiryoh\/mbed,kjbracey-arm\/mbed,tung7970\/mbed-os-1,pedromes\/mbed,ryankurte\/mbed-os,fpiot\/mbed-ats,theotherjimmy\/mbed,Sweet-Peas\/mbed,tung7970\/mbed-os-1,mikaleppanen\/mbed-os,pi19404\/mbed,fpiot\/mbed-ats,netzimme\/mbed-os,adamgreen\/mbed,betzw\/mbed-os,pradeep-gr\/mbed-os5-onsemi,infinnovation\/mbed-os,screamerbg\/mbed,sam-geek\/mbed,devanlai\/mbed,Marcomissyou\/mbed,pi19404\/mbed,autopulated\/mbed,jrjang\/mbed,autopulated\/mbed,NXPmicro\/mbed,nabilbendafi\/mbed,al177\/mbed,Marcomissyou\/mbed,pbrook\/mbed,hwfwgrp\/mbed,adustm\/mbed,bentwire\/mbed,autopulated\/mbed,bentwire\/mbed,pi19404\/mbed,svastm\/mbed,mmorenobarm\/mbed-os,j-greffe\/mbed-os,mazimkhan\/mbed-os","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_STM32L1\/TARGET_NUCLEO_L152RE\/TOOLCHAIN_GCC_ARM\/STM32L152XE.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_STM\/TARGET_STM32L1\/TARGET_NUCLEO_L152RE\/TOOLCHAIN_GCC_ARM\/STM32L152XE.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/nvlsianpu\/mbed.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"a753321894de4aa8a2bd7b62710465ad61d5e134","subject":"The old linker script (nrf51dk.ld) is now the linker script for building an image that runs with a bootloader. This linker script should be used when running without a bootloader","message":"The old linker script (nrf51dk.ld) is now the linker script for building an image that runs with a bootloader. This linker script should be used when running without a bootloader\n","repos":"IMGJulian\/incubator-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,wes3\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,wes3\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,wes3\/incubator-mynewt-core","old_file":"hw\/bsp\/nrf51dk\/nrf51dk_no_boot.ld","new_file":"hw\/bsp\/nrf51dk\/nrf51dk_no_boot.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mlaz\/mynewt-core.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"bdf27e6b74f7cada990fb39febe11f8897b528f6","subject":"Add linker file","message":"Add linker file\n","repos":"Tech4Race\/nrf5x-base,Tech4Race\/nrf5x-base,Tech4Race\/nrf5x-base,Tech4Race\/nrf5x-base","old_file":"make\/ld\/gcc_nrf52_s132_2.0.0_64_512.ld","new_file":"make\/ld\/gcc_nrf52_s132_2.0.0_64_512.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Tech4Race\/nrf5x-base.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"6a6c1d85ff2abb4a98dea8109c4afc24be842a34","subject":"add S130 support","message":"add S130 support\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/Nordic\/nRF51\/src\/gcc_nrf51_s130_xxac.ld","new_file":"ARM\/Nordic\/nRF51\/src\/gcc_nrf51_s130_xxac.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/I-SYST\/EHAL.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"310e7d605c906f897950abd4801e87e809aaae6a","subject":"forgot linkerscript","message":"forgot linkerscript\n","repos":"cycl0ne\/poweros_x86,cycl0ne\/poweros_x86,cycl0ne\/poweros_x86","old_file":"arch_x86.ld","new_file":"arch_x86.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/cycl0ne\/poweros_x86.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4d3a34ee2923b6276ba11e6c6fcf8e096891ffaf","subject":"K66F: Move bss section to m_data_2 Section","message":"K66F: Move bss section to m_data_2 Section\n\nSigned-off-by: Mahadevan Mahesh <778f93d13cb34f99fc4522dcbb13a8dffe2c8547@nxp.com>\n","repos":"j-greffe\/mbed-os,j-greffe\/mbed-os,j-greffe\/mbed-os,j-greffe\/mbed-os,j-greffe\/mbed-os,j-greffe\/mbed-os","old_file":"targets\/TARGET_Freescale\/TARGET_MCUXpresso_MCUS\/TARGET_K66F\/device\/TOOLCHAIN_GCC_ARM\/MK66FN2M0xxx18.ld","new_file":"targets\/TARGET_Freescale\/TARGET_MCUXpresso_MCUS\/TARGET_K66F\/device\/TOOLCHAIN_GCC_ARM\/MK66FN2M0xxx18.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/j-greffe\/mbed-os.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"61c643bb16fedd29459f510889ede0a0486cb291","subject":"Create stm32f030f4p6.ld","message":"Create stm32f030f4p6.ld","repos":"crteensy\/STM32F030F4P6-breakout-board,crteensy\/STM32F030F4P6-breakout-board","old_file":"ld\/stm32f030f4p6.ld","new_file":"ld\/stm32f030f4p6.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/crteensy\/STM32F030F4P6-breakout-board.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"618aa60afc7afaf6da9e164bb6809d4cd16b4aeb","subject":" Adding placeholder linker script for BL","message":" Adding placeholder linker script for BL\n","repos":"MickMad\/ArduinoCore-samd,MickMad\/ArduinoCore-samd","old_file":"variants\/arduino_zero\/linker_scripts\/gcc\/flash_with_bootloader.ld","new_file":"variants\/arduino_zero\/linker_scripts\/gcc\/flash_with_bootloader.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/MickMad\/ArduinoCore-samd.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"83950c35c2a2a81dbb49112327287fc83fda8c62","subject":"Hide hwloc symbols in libtensorflow_framework.so","message":"Hide hwloc symbols in libtensorflow_framework.so\n","repos":"cxxgtxy\/tensorflow,tensorflow\/tensorflow,annarev\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,paolodedios\/tensorflow,Intel-Corporation\/tensorflow,adit-chandra\/tensorflow,Intel-Corporation\/tensorflow,DavidNorman\/tensorflow,annarev\/tensorflow,sarvex\/tensorflow,sarvex\/tensorflow,petewarden\/tensorflow,aam-at\/tensorflow,yongtang\/tensorflow,annarev\/tensorflow,adit-chandra\/tensorflow,Intel-tensorflow\/tensorflow,gautam1858\/tensorflow,karllessard\/tensorflow,xzturn\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,frreiss\/tensorflow-fred,tensorflow\/tensorflow,karllessard\/tensorflow,annarev\/tensorflow,DavidNorman\/tensorflow,freedomtan\/tensorflow,karllessard\/tensorflow,arborh\/tensorflow,annarev\/tensorflow,gunan\/tensorflow,arborh\/tensorflow,chemelnucfin\/tensorflow,gunan\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,arborh\/tensorflow,frreiss\/tensorflow-fred,davidzchen\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,ppwwyyxx\/tensorflow,karllessard\/tensorflow,gautam1858\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,freedomtan\/tensorflow,chemelnucfin\/tensorflow,gautam1858\/tensorflow,xzturn\/tensorflow,frreiss\/tensorflow-fred,cxxgtxy\/tensorflow,gunan\/tensorflow,xzturn\/tensorflow,frreiss\/tensorflow-fred,jhseu\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,arborh\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,arborh\/tensorflow,frreiss\/tensorflow-fred,ppwwyyxx\/tensorflow,adit-chandra\/tensorflow,paolodedios\/tensorflow,davidzchen\/tensorflow,DavidNorman\/tensorflow,Intel-Corporation\/tensorflow,freedomtan\/tensorflow,Intel-tensorflow\/tensorflow,renyi533\/tensorflow,ppwwyyxx\/tensorflow,renyi533\/tensorflow,renyi533\/tensorflow,tensorflow\/tensorflow,tensorflow\/tensorflow,yongtang\/tensorflow,adit-chandra\/tensorflow,Intel-tensorflow\/tensorflow,ppwwyyxx\/tensorflow,DavidNorman\/tensorflow,annarev\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow,DavidNorman\/tensorflow,cxxgtxy\/tensorflow,karllessard\/tensorflow,frreiss\/tensorflow-fred,freedomtan\/tensorflow,jhseu\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,karllessard\/tensorflow,Intel-Corporation\/tensorflow,aldian\/tensorflow,xzturn\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,frreiss\/tensorflow-fred,xzturn\/tensorflow,renyi533\/tensorflow,annarev\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,frreiss\/tensorflow-fred,arborh\/tensorflow,xzturn\/tensorflow,petewarden\/tensorflow,gautam1858\/tensorflow,gautam1858\/tensorflow,aam-at\/tensorflow,jhseu\/tensorflow,chemelnucfin\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,jhseu\/tensorflow,davidzchen\/tensorflow,aam-at\/tensorflow,cxxgtxy\/tensorflow,sarvex\/tensorflow,aam-at\/tensorflow,freedomtan\/tensorflow,freedomtan\/tensorflow,karllessard\/tensorflow,davidzchen\/tensorflow,renyi533\/tensorflow,ppwwyyxx\/tensorflow,DavidNorman\/tensorflow,jhseu\/tensorflow,arborh\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,davidzchen\/tensorflow,chemelnucfin\/tensorflow,arborh\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,aldian\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow,gunan\/tensorflow,xzturn\/tensorflow,paolodedios\/tensorflow,petewarden\/tensorflow,karllessard\/tensorflow,chemelnucfin\/tensorflow,adit-chandra\/tensorflow,arborh\/tensorflow,gunan\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,cxxgtxy\/tensorflow,karllessard\/tensorflow,gautam1858\/tensorflow,jhseu\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,Intel-Corporation\/tensorflow,renyi533\/tensorflow,yongtang\/tensorflow,adit-chandra\/tensorflow,aldian\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,freedomtan\/tensorflow,petewarden\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,davidzchen\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,ppwwyyxx\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,xzturn\/tensorflow,gautam1858\/tensorflow,gautam1858\/tensorflow,adit-chandra\/tensorflow,chemelnucfin\/tensorflow,petewarden\/tensorflow,Intel-tensorflow\/tensorflow,jhseu\/tensorflow,DavidNorman\/tensorflow,petewarden\/tensorflow,freedomtan\/tensorflow,aam-at\/tensorflow,gautam1858\/tensorflow,DavidNorman\/tensorflow,Intel-tensorflow\/tensorflow,aldian\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,adit-chandra\/tensorflow,petewarden\/tensorflow,cxxgtxy\/tensorflow,paolodedios\/tensorflow,freedomtan\/tensorflow,karllessard\/tensorflow,aldian\/tensorflow,aldian\/tensorflow,aldian\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,jhseu\/tensorflow,renyi533\/tensorflow,yongtang\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,arborh\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gautam1858\/tensorflow,petewarden\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow,petewarden\/tensorflow,annarev\/tensorflow,chemelnucfin\/tensorflow,Intel-Corporation\/tensorflow,gunan\/tensorflow,davidzchen\/tensorflow,annarev\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow-pywrap_saved_model,arborh\/tensorflow,ppwwyyxx\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,jhseu\/tensorflow,renyi533\/tensorflow,frreiss\/tensorflow-fred,aldian\/tensorflow,gunan\/tensorflow,chemelnucfin\/tensorflow,chemelnucfin\/tensorflow,DavidNorman\/tensorflow,jhseu\/tensorflow,freedomtan\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,arborh\/tensorflow,petewarden\/tensorflow,frreiss\/tensorflow-fred,tensorflow\/tensorflow-pywrap_tf_optimizer,adit-chandra\/tensorflow,aam-at\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gunan\/tensorflow,Intel-Corporation\/tensorflow,gunan\/tensorflow,frreiss\/tensorflow-fred,renyi533\/tensorflow,aam-at\/tensorflow,renyi533\/tensorflow,jhseu\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,chemelnucfin\/tensorflow,Intel-tensorflow\/tensorflow,tensorflow\/tensorflow,paolodedios\/tensorflow,petewarden\/tensorflow,Intel-Corporation\/tensorflow,renyi533\/tensorflow,xzturn\/tensorflow,karllessard\/tensorflow,davidzchen\/tensorflow,sarvex\/tensorflow,tensorflow\/tensorflow-experimental_link_static_libraries_once,gunan\/tensorflow,tensorflow\/tensorflow,DavidNorman\/tensorflow,Intel-tensorflow\/tensorflow,sarvex\/tensorflow,aam-at\/tensorflow,freedomtan\/tensorflow,adit-chandra\/tensorflow,annarev\/tensorflow,tensorflow\/tensorflow,cxxgtxy\/tensorflow,frreiss\/tensorflow-fred,yongtang\/tensorflow,adit-chandra\/tensorflow,gunan\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,davidzchen\/tensorflow,paolodedios\/tensorflow,yongtang\/tensorflow,xzturn\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,paolodedios\/tensorflow,ppwwyyxx\/tensorflow,DavidNorman\/tensorflow,yongtang\/tensorflow,freedomtan\/tensorflow,paolodedios\/tensorflow,tensorflow\/tensorflow,renyi533\/tensorflow,aam-at\/tensorflow,gautam1858\/tensorflow,aam-at\/tensorflow,petewarden\/tensorflow,yongtang\/tensorflow,sarvex\/tensorflow,cxxgtxy\/tensorflow,xzturn\/tensorflow,gunan\/tensorflow,xzturn\/tensorflow,chemelnucfin\/tensorflow,tensorflow\/tensorflow-pywrap_tf_optimizer,Intel-tensorflow\/tensorflow,davidzchen\/tensorflow,davidzchen\/tensorflow,chemelnucfin\/tensorflow,paolodedios\/tensorflow,Intel-tensorflow\/tensorflow,aam-at\/tensorflow,adit-chandra\/tensorflow,davidzchen\/tensorflow,jhseu\/tensorflow,gautam1858\/tensorflow,DavidNorman\/tensorflow","old_file":"tensorflow\/tf_framework_version_script.lds","new_file":"tensorflow\/tf_framework_version_script.lds","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Intel-tensorflow\/tensorflow.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"3c28c8d77e6309edf0180679eae088bc7f56eb89","subject":"[LPC11U35][GCC_ARM][GCC_CR]: Modificatins for build. 1. Added to the export table in export_test.py. 2. Added to the build table in build_release.py 3. Added the compilation directives to RTX os files.","message":"[LPC11U35][GCC_ARM][GCC_CR]: Modificatins for build.\n1. Added to the export table in export_test.py.\n2. Added to the build table in build_release.py\n3. Added the compilation directives to RTX os files.\n\nNotice:\n It would be better to change WORDS_STACK_SIZE definition in libraries\/rtos\/rtx\/cmsis_os.h\n from 512 to 128 for LPC11U35 and LPC1114 micros compiled by GCC toolchain with newlib-nano,\n but I don't know the good way at this moment.\n","repos":"Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,Psykar\/kubos,kubostech\/KubOS,Psykar\/kubos,kubostech\/KubOS","old_file":"TARGET_NXP\/TARGET_LPC11UXX\/TOOLCHAIN_GCC_ARM\/TARGET_LPC11U35_501\/LPC11U35.ld","new_file":"TARGET_NXP\/TARGET_LPC11UXX\/TOOLCHAIN_GCC_ARM\/TARGET_LPC11U35_501\/LPC11U35.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/Psykar\/kubos.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"5f3aca7fd5144b3dc66f9c55a1e7b0eb09b4ccbf","subject":"cpu: stm32f2: ldscripts: add linker script for firmup build.","message":"cpu: stm32f2: ldscripts: add linker script for firmup build.\n","repos":"centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT,centurysys\/RIOT","old_file":"cpu\/stm32f2\/ldscripts\/stm32f205re_MMA200FirmUp.ld","new_file":"cpu\/stm32f2\/ldscripts\/stm32f205re_MMA200FirmUp.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/centurysys\/RIOT.git\/': The requested URL returned error: 403\n","license":"lgpl-2.1","lang":"Linker Script"}
{"commit":"e47945e9fda8bb589765cf176b58c34e01e92425","subject":"add missed F373 linker script","message":"add missed F373 linker script\n","repos":"dmitrystu\/libusb_stm32","old_file":"demo\/stm32f373xc.ld","new_file":"demo\/stm32f373xc.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/dmitrystu\/libusb_stm32.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"4155a9a00356362976c53860195fe9df5222bce6","subject":"nrf\/boards: Add linker script for nrf52840 Open Bootloader 1.2.0.","message":"nrf\/boards: Add linker script for nrf52840 Open Bootloader 1.2.0.\n","repos":"pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython,pfalcon\/micropython","old_file":"ports\/nrf\/boards\/nrf52840_open_bootloader_1.2.x.ld","new_file":"ports\/nrf\/boards\/nrf52840_open_bootloader_1.2.x.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/pfalcon\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"dcf4eb8134f7392d462e1a4d9f3db7cb8e62517e","subject":"stm32\/boards: Add common_bl.ld for boards that need a bootloader.","message":"stm32\/boards: Add common_bl.ld for boards that need a bootloader.\n","repos":"bvernoux\/micropython,MrSurly\/micropython,pramasoul\/micropython,tobbad\/micropython,bvernoux\/micropython,dmazzella\/micropython,MrSurly\/micropython,adafruit\/circuitpython,swegener\/micropython,swegener\/micropython,henriknelson\/micropython,ryannathans\/micropython,trezor\/micropython,adafruit\/micropython,pramasoul\/micropython,adafruit\/micropython,adafruit\/micropython,MrSurly\/micropython,selste\/micropython,adafruit\/circuitpython,MrSurly\/micropython,pfalcon\/micropython,tralamazza\/micropython,dmazzella\/micropython,bvernoux\/micropython,trezor\/micropython,henriknelson\/micropython,selste\/micropython,pramasoul\/micropython,tralamazza\/micropython,ryannathans\/micropython,swegener\/micropython,adafruit\/micropython,adafruit\/circuitpython,selste\/micropython,bvernoux\/micropython,ryannathans\/micropython,kerneltask\/micropython,pozetroninc\/micropython,MrSurly\/micropython,pozetroninc\/micropython,pozetroninc\/micropython,tobbad\/micropython,pozetroninc\/micropython,kerneltask\/micropython,henriknelson\/micropython,adafruit\/circuitpython,henriknelson\/micropython,dmazzella\/micropython,swegener\/micropython,bvernoux\/micropython,pfalcon\/micropython,adafruit\/circuitpython,selste\/micropython,pfalcon\/micropython,pramasoul\/micropython,pfalcon\/micropython,dmazzella\/micropython,kerneltask\/micropython,tralamazza\/micropython,pramasoul\/micropython,adafruit\/circuitpython,selste\/micropython,pozetroninc\/micropython,trezor\/micropython,henriknelson\/micropython,swegener\/micropython,ryannathans\/micropython,tobbad\/micropython,adafruit\/micropython,kerneltask\/micropython,kerneltask\/micropython,ryannathans\/micropython,tobbad\/micropython,pfalcon\/micropython,trezor\/micropython,tralamazza\/micropython,trezor\/micropython,tobbad\/micropython","old_file":"ports\/stm32\/boards\/common_bl.ld","new_file":"ports\/stm32\/boards\/common_bl.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/pfalcon\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"1bb6bfee23440d78c0fb883174fc4d11eafff49d","subject":"Use the correct name for dtb_size","message":"Use the correct name for dtb_size\n","repos":"kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa","old_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kalray\/odp-mppa.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"a8b95545720984fae0eb3b62dd3d4836c63d9e77","subject":"Align dedicated linker script to feet with new tools one","message":"Align dedicated linker script to feet with new tools one\n","repos":"kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa,kalray\/odp-mppa","old_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_file":"firmware\/common\/ioeth-bsp\/platform.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/kalray\/odp-mppa.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"f2d98ae63dc64dedb00499289e13a50677f771f9","subject":"Linker script for the new x86 setup code","message":"Linker script for the new x86 setup code\n\nLinker script to define the layout of the new x86 setup code.\nIncludes assert for size overflow and a misaligned setup header.\n\nSigned-off-by: H. Peter Anvin <8a453bad9912ffe59bc0f0b8abe03df9be19379e@zytor.com>\nSigned-off-by: Linus Torvalds <69652caca27c8b940640ad396ab71f93cacec34f@linux-foundation.org>\n","repos":"TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas,TeamVee-Kanas\/android_kernel_samsung_kanas,KristFoundation\/Programs,KristFoundation\/Programs,TeamVee-Kanas\/android_kernel_samsung_kanas","old_file":"arch\/i386\/boot\/setup.ld","new_file":"arch\/i386\/boot\/setup.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/TeamVee-Kanas\/android_kernel_samsung_kanas.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"9d214455ab4397324b4fdb1eecf244afce7a1fb2","subject":"Add kernel.ld in rpiboot dir","message":"Add kernel.ld in rpiboot dir\n","repos":"aviatorRHK\/rpiForth","old_file":"rpiboot\/kernel.ld","new_file":"rpiboot\/kernel.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/aviatorRHK\/rpiForth.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"ec6502c1ea2b97688a8e3ca6c4142e331c99adb6","subject":"nrf5\/boards: Adding linker script for nrf52832 s132 v.2.0.1.","message":"nrf5\/boards: Adding linker script for nrf52832 s132 v.2.0.1.\n","repos":"tralamazza\/micropython,tralamazza\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/micropython,tralamazza\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,tralamazza\/micropython,adafruit\/micropython","old_file":"nrf5\/boards\/nrf52832_512k_64k_s132_2.0.1.ld","new_file":"nrf5\/boards\/nrf52832_512k_64k_s132_2.0.1.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/tralamazza\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"0d84cb06f98c685429171c0975449a360848683d","subject":"Fix nrf52840 linker script. (#1671)","message":"Fix nrf52840 linker script. (#1671)\n\n","repos":"vaas-krish\/openthread,JakubBrachTieto\/openthread,librasungirl\/openthread,aeliot\/openthread,LeZhang2016\/openthread,fbsder\/openthread,fbsder\/openthread,chshu\/openthread,abtink\/openthread,erja-gp\/openthread,abtink\/openthread,lanyuwen\/openthread,xiaom-GitHub\/openthread,gandreello\/openthread,aeliot\/openthread,jwhui\/openthread,xiaom-GitHub\/openthread,turon\/openthread,aeliot\/openthread,turon\/openthread,xiaom-GitHub\/openthread,gandreello\/openthread,srickardti\/openthread,georgecpr\/openthread,chshu\/openthread,openthread\/openthread,bukepo\/openthread,JakubBrachTieto\/openthread,chshu\/openthread,aeliot\/openthread,openthread\/openthread,mszczodrak\/openthread,srickardti\/openthread,JakubBrachTieto\/openthread,vaas-krish\/openthread,pvanhorn\/openthread,fbsder\/openthread,erja-gp\/openthread,fbsder\/openthread,lanyuwen\/openthread,fbsder\/openthread,pvanhorn\/openthread,gandreello\/openthread,jwhui\/openthread,pvanhorn\/openthread,LeZhang2016\/openthread,mszczodrak\/openthread,mszczodrak\/openthread,bukepo\/openthread,mszczodrak\/openthread,mszczodrak\/openthread,chshu\/openthread,librasungirl\/openthread,LeZhang2016\/openthread,pvanhorn\/openthread,erja-gp\/openthread,erja-gp\/openthread,jwhui\/openthread,vaas-krish\/openthread,JakubBrachTieto\/openthread,fbsder\/openthread,turon\/openthread,pvanhorn\/openthread,srickardti\/openthread,mszczodrak\/openthread,vaas-krish\/openthread,gandreello\/openthread,lanyuwen\/openthread,pvanhorn\/openthread,gandreello\/openthread,xiaom-GitHub\/openthread,georgecpr\/openthread,vaas-krish\/openthread,bukepo\/openthread,openthread\/openthread,LeZhang2016\/openthread,erja-gp\/openthread,bukepo\/openthread,georgecpr\/openthread,chshu\/openthread,lanyuwen\/openthread,librasungirl\/openthread,erja-gp\/openthread,JakubBrachTieto\/openthread,LeZhang2016\/openthread,LeZhang2016\/openthread,openthread\/openthread,turon\/openthread,abtink\/openthread,gandreello\/openthread,JakubBrachTieto\/openthread,georgecpr\/openthread,aeliot\/openthread,aeliot\/openthread,xiaom-GitHub\/openthread,lanyuwen\/openthread,librasungirl\/openthread,jwhui\/openthread,xiaom-GitHub\/openthread,georgecpr\/openthread,abtink\/openthread,georgecpr\/openthread,lanyuwen\/openthread,vaas-krish\/openthread,chshu\/openthread,srickardti\/openthread","old_file":"examples\/platforms\/nrf52840\/nrf52840.ld","new_file":"examples\/platforms\/nrf52840\/nrf52840.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/jwhui\/openthread.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"aacb1adcd10f6325719bfe4faa0c8593eef94016","subject":"atmel-samd: Add linker file for bootloaderless board with external flash.","message":"atmel-samd: Add linker file for bootloaderless board with external flash.\n","repos":"adafruit\/micropython,adafruit\/micropython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/circuitpython,adafruit\/micropython","old_file":"atmel-samd\/boards\/samd21x18-external-flash.ld","new_file":"atmel-samd\/boards\/samd21x18-external-flash.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/adafruit\/micropython.git\/': The requested URL returned error: 403\n","license":"mit","lang":"Linker Script"}
{"commit":"fcbbc1b86ae039407b94898afa85625be4330b39","subject":"Generic linker script","message":"Generic linker script\n","repos":"I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL,I-SYST\/EHAL","old_file":"ARM\/src\/gcc_arm.ld","new_file":"ARM\/src\/gcc_arm.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/I-SYST\/EHAL.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"d03c12afbfe0ad8366e813776aad379b606fbb86","subject":"Add comments to boot linker script.","message":"Add comments to boot linker script.\n","repos":"mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,IMGJulian\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,IMGJulian\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,andrzej-kaczmarek\/apache-mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core,IMGJulian\/incubator-mynewt-core,mlaz\/mynewt-core,andrzej-kaczmarek\/incubator-mynewt-core","old_file":"hw\/bsp\/stm32f7discovery\/boot-stm32f7discovery.ld","new_file":"hw\/bsp\/stm32f7discovery\/boot-stm32f7discovery.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/mlaz\/mynewt-core.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}
{"commit":"564e6faaead618ea80a88f9e9ba8991e7962c305","subject":"Architecture: Linker: Spaces -> Tabs.","message":"Architecture: Linker: Spaces -> Tabs.","repos":"dergraaf\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc,dergraaf\/xpcc","old_file":"src\/xpcc\/architecture\/platform\/linker\/stm32\/stm32_iccm.ld","new_file":"src\/xpcc\/architecture\/platform\/linker\/stm32\/stm32_iccm.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/dergraaf\/xpcc.git\/': GnuTLS recv error (-54): Error in the pull function.\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"f29c29cd52e7e19ebff5082f1e3d312e2ebd0fbc","subject":"remove obsolete file","message":"remove obsolete file\n","repos":"RWTH-OS\/HermitCore,RWTH-OS\/HermitCore,stlankes\/HermitCore,stlankes\/HermitCore,RWTH-OS\/HermitCore,RWTH-OS\/HermitCore,stlankes\/HermitCore,stlankes\/HermitCore,RWTH-OS\/HermitCore,stlankes\/HermitCore,RWTH-OS\/HermitCore,stlankes\/HermitCore","old_file":"link.ld","new_file":"link.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/RWTH-OS\/HermitCore.git\/': The requested URL returned error: 403\n","license":"bsd-3-clause","lang":"Linker Script"}
{"commit":"a1653f27085e823495e1a54b3a74209088fac107","subject":"Fix KL05Z GCC_ARM linker script","message":"Fix KL05Z GCC_ARM linker script\n\nIssue originally reported on mbed site here:\nhttps:\/\/developer.mbed.org\/questions\/5695\/FRDM-KL05z-hardfault-when-compiled-with-\/\n\nThe RAM base address was incorrectly set to the beginning of RAM\ninstead of at a 0xC0 byte offset to reserve room for the interrupt\nvectors. Without this fix, the global variables and the interrupt\nvectors were occupying the same space in RAM once the user enabled the\ntimer interrupt.\n\nThe user who originally reported the issue on the mbed site has tested\nthis fix and verified that it corrected the hard fault issue that they\nwere encountering.\n","repos":"hwfwgrp\/mbed,jrjang\/mbed,pbrook\/mbed,pbrook\/mbed,j-greffe\/mbed-os,bentwire\/mbed,CalSol\/mbed,jamesadevine\/mbed,devanlai\/mbed,mmorenobarm\/mbed-os,kl-cruz\/mbed-os,rosterloh\/mbed,Archcady\/mbed-os,Sweet-Peas\/mbed,mikaleppanen\/mbed-os,larks\/mbed,rgrover\/mbed,c1728p9\/mbed-os,struempelix\/mbed,ban4jp\/mbed,Shengliang\/mbed,brstew\/MBED-BUILD,Archcady\/mbed-os,svogl\/mbed-os,jferreir\/mbed,jamesadevine\/mbed,GustavWi\/mbed,tung7970\/mbed-os-1,screamerbg\/mbed,pradeep-gr\/mbed-os5-onsemi,svogl\/mbed-os,rgrover\/mbed,bulislaw\/mbed-os,svastm\/mbed,arostm\/mbed-os,bulislaw\/mbed-os,monkiineko\/mbed-os,theotherjimmy\/mbed,pbrook\/mbed,arostm\/mbed-os,naves-thiago\/mbed-midi,bikeNomad\/mbed,alertby\/mbed,fanghuaqi\/mbed,geky\/mbed,arostm\/mbed-os,logost\/mbed,pradeep-gr\/mbed-os5-onsemi,pbrook\/mbed,EmuxEvans\/mbed,nRFMesh\/mbed-os,dbestm\/mbed,andcor02\/mbed-os,tung7970\/mbed-os-1,NitinBhaskar\/mbed,NitinBhaskar\/mbed,hwfwgrp\/mbed,Marcomissyou\/mbed,theotherjimmy\/mbed,Archcady\/mbed-os,radhika-raghavendran\/mbed-os5.1-onsemi,brstew\/MBED-BUILD,ryankurte\/mbed-os,adamgreen\/mbed,JasonHow44\/mbed,infinnovation\/mbed-os,Tiryoh\/mbed,svogl\/mbed-os,nabilbendafi\/mbed,kl-cruz\/mbed-os,monkiineko\/mbed-os,adamgreen\/mbed,svogl\/mbed-os,mnlipp\/mbed,al177\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,mazimkhan\/mbed-os,struempelix\/mbed,Timmmm\/mbed,nRFMesh\/mbed-os,brstew\/MBED-BUILD,mazimkhan\/mbed-os,monkiineko\/mbed-os,j-greffe\/mbed-os,masaohamanaka\/mbed,CalSol\/mbed,alertby\/mbed,mmorenobarm\/mbed-os,dbestm\/mbed,JasonHow44\/mbed,jpbrucker\/mbed,wodji\/mbed,FranklyDev\/mbed,adamgreen\/mbed,ryankurte\/mbed-os,NitinBhaskar\/mbed,andreaslarssonublox\/mbed,xcrespo\/mbed,Sweet-Peas\/mbed,getopenmono\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,sam-geek\/mbed,betzw\/mbed-os,cvtsi2sd\/mbed-os,Timmmm\/mbed,fanghuaqi\/mbed,YarivCol\/mbed-os,mazimkhan\/mbed-os,rosterloh\/mbed,fahhem\/mbed-os,screamerbg\/mbed,devanlai\/mbed,Willem23\/mbed,mnlipp\/mbed,naves-thiago\/mbed-midi,infinnovation\/mbed-os,mikaleppanen\/mbed-os,andcor02\/mbed-os,jrjang\/mbed,masaohamanaka\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,HeadsUpDisplayInc\/mbed,screamerbg\/mbed,jeremybrodt\/mbed,nvlsianpu\/mbed,jrjang\/mbed,larks\/mbed,fpiot\/mbed-ats,devanlai\/mbed,mnlipp\/mbed,mnlipp\/mbed,DanKupiniak\/mbed,alertby\/mbed,Tiryoh\/mbed,ryankurte\/mbed-os,masaohamanaka\/mbed,hwfwgrp\/mbed,al177\/mbed,CalSol\/mbed,bentwire\/mbed,jferreir\/mbed,tung7970\/mbed-os,ban4jp\/mbed,pi19404\/mbed,dbestm\/mbed,YarivCol\/mbed-os,netzimme\/mbed-os,ban4jp\/mbed,struempelix\/mbed,mmorenobarm\/mbed-os,karsev\/mbed-os,DanKupiniak\/mbed,fpiot\/mbed-ats,c1728p9\/mbed-os,maximmbed\/mbed,bikeNomad\/mbed,svastm\/mbed,bentwire\/mbed,j-greffe\/mbed-os,rosterloh\/mbed,nRFMesh\/mbed-os,monkiineko\/mbed-os,maximmbed\/mbed,catiedev\/mbed-os,screamerbg\/mbed,EmuxEvans\/mbed,svastm\/mbed,pedromes\/mbed,K4zuki\/mbed,pedromes\/mbed,andcor02\/mbed-os,bcostm\/mbed-os,GustavWi\/mbed,mbedmicro\/mbed,Timmmm\/mbed,sam-geek\/mbed,struempelix\/mbed,nabilbendafi\/mbed,screamerbg\/mbed,cvtsi2sd\/mbed-os,jpbrucker\/mbed,karsev\/mbed-os,tung7970\/mbed-os,andreaslarssonublox\/mbed,ARM-software\/mbed-beetle,c1728p9\/mbed-os,netzimme\/mbed-os,adustm\/mbed,adustm\/mbed,nRFMesh\/mbed-os,CalSol\/mbed,FranklyDev\/mbed,JasonHow44\/mbed,kjbracey-arm\/mbed,ARM-software\/mbed-beetle,Sweet-Peas\/mbed,Willem23\/mbed,Marcomissyou\/mbed,bcostm\/mbed-os,betzw\/mbed-os,CalSol\/mbed,arostm\/mbed-os,HeadsUpDisplayInc\/mbed,mnlipp\/mbed,Tiryoh\/mbed,hwfwgrp\/mbed,YarivCol\/mbed-os,GustavWi\/mbed,nvlsianpu\/mbed,catiedev\/mbed-os,jferreir\/mbed,NXPmicro\/mbed,naves-thiago\/mbed-midi,brstew\/MBED-BUILD,bcostm\/mbed-os,Sweet-Peas\/mbed,theotherjimmy\/mbed,wodji\/mbed,Shengliang\/mbed,betzw\/mbed-os,xcrespo\/mbed,bcostm\/mbed-os,mbedmicro\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,jpbrucker\/mbed,bcostm\/mbed-os,nvlsianpu\/mbed,svogl\/mbed-os,JasonHow44\/mbed,kl-cruz\/mbed-os,NXPmicro\/mbed,wodji\/mbed,bentwire\/mbed,K4zuki\/mbed,bikeNomad\/mbed,Archcady\/mbed-os,sam-geek\/mbed,Willem23\/mbed,kpurusho\/mbed,K4zuki\/mbed,getopenmono\/mbed,geky\/mbed,kpurusho\/mbed,kl-cruz\/mbed-os,infinnovation\/mbed-os,fanghuaqi\/mbed,rgrover\/mbed,arostm\/mbed-os,tung7970\/mbed-os-1,theotherjimmy\/mbed,FranklyDev\/mbed,RonEld\/mbed,pradeep-gr\/mbed-os5-onsemi,Sweet-Peas\/mbed,infinnovation\/mbed-os,andreaslarssonublox\/mbed,radhika-raghavendran\/mbed-os5.1-onsemi,wodji\/mbed,struempelix\/mbed,svastm\/mbed,YarivCol\/mbed-os,EmuxEvans\/mbed,fvincenzo\/mbed-os,wodji\/mbed,autopulated\/mbed,kl-cruz\/mbed-os,jeremybrodt\/mbed,kjbracey-arm\/mbed,cvtsi2sd\/mbed-os,nabilbendafi\/mbed,nvlsianpu\/mbed,al177\/mbed,devanlai\/mbed,tung7970\/mbed-os,jamesadevine\/mbed,naves-thiago\/mbed-midi,karsev\/mbed-os,geky\/mbed,bulislaw\/mbed-os,JasonHow44\/mbed,adustm\/mbed,jrjang\/mbed,nRFMesh\/mbed-os,mmorenobarm\/mbed-os,screamerbg\/mbed,ryankurte\/mbed-os,YarivCol\/mbed-os,c1728p9\/mbed-os,Willem23\/mbed,al177\/mbed,adustm\/mbed,kl-cruz\/mbed-os,j-greffe\/mbed-os,betzw\/mbed-os,Archcady\/mbed-os,infinnovation\/mbed-os,EmuxEvans\/mbed,EmuxEvans\/mbed,hwfwgrp\/mbed,masaohamanaka\/mbed,andreaslarssonublox\/mbed,al177\/mbed,betzw\/mbed-os,Willem23\/mbed,Shengliang\/mbed,Tiryoh\/mbed,brstew\/MBED-BUILD,HeadsUpDisplayInc\/mbed,fvincenzo\/mbed-os,mbedmicro\/mbed,masaohamanaka\/mbed,jrjang\/mbed,NitinBhaskar\/mbed,jpbrucker\/mbed,CalSol\/mbed,rosterloh\/mbed,jeremybrodt\/mbed,mbedmicro\/mbed,pedromes\/mbed,maximmbed\/mbed,netzimme\/mbed-os,kpurusho\/mbed,bulislaw\/mbed-os,fvincenzo\/mbed-os,c1728p9\/mbed-os,RonEld\/mbed,naves-thiago\/mbed-midi,Tiryoh\/mbed,geky\/mbed,hwfwgrp\/mbed,autopulated\/mbed,nabilbendafi\/mbed,fpiot\/mbed-ats,naves-thiago\/mbed-midi,mbedmicro\/mbed,xcrespo\/mbed,netzimme\/mbed-os,jferreir\/mbed,pi19404\/mbed,logost\/mbed,fpiot\/mbed-ats,mikaleppanen\/mbed-os,ban4jp\/mbed,infinnovation\/mbed-os,alertby\/mbed,larks\/mbed,catiedev\/mbed-os,pi19404\/mbed,RonEld\/mbed,HeadsUpDisplayInc\/mbed,geky\/mbed,tung7970\/mbed-os-1,Timmmm\/mbed,andcor02\/mbed-os,mazimkhan\/mbed-os,devanlai\/mbed,andcor02\/mbed-os,larks\/mbed,jamesadevine\/mbed,cvtsi2sd\/mbed-os,Marcomissyou\/mbed,pedromes\/mbed,bulislaw\/mbed-os,jamesadevine\/mbed,bentwire\/mbed,bikeNomad\/mbed,fpiot\/mbed-ats,pi19404\/mbed,xcrespo\/mbed,autopulated\/mbed,karsev\/mbed-os,bcostm\/mbed-os,RonEld\/mbed,jamesadevine\/mbed,netzimme\/mbed-os,logost\/mbed,adamgreen\/mbed,Marcomissyou\/mbed,logost\/mbed,devanlai\/mbed,getopenmono\/mbed,Timmmm\/mbed,fanghuaqi\/mbed,catiedev\/mbed-os,karsev\/mbed-os,NXPmicro\/mbed,YarivCol\/mbed-os,mikaleppanen\/mbed-os,pbrook\/mbed,pradeep-gr\/mbed-os5-onsemi,netzimme\/mbed-os,fvincenzo\/mbed-os,Shengliang\/mbed,logost\/mbed,kpurusho\/mbed,Tiryoh\/mbed,mikaleppanen\/mbed-os,pedromes\/mbed,bikeNomad\/mbed,jpbrucker\/mbed,struempelix\/mbed,karsev\/mbed-os,EmuxEvans\/mbed,kjbracey-arm\/mbed,xcrespo\/mbed,tung7970\/mbed-os,j-greffe\/mbed-os,rgrover\/mbed,c1728p9\/mbed-os,mazimkhan\/mbed-os,theotherjimmy\/mbed,ban4jp\/mbed,Timmmm\/mbed,GustavWi\/mbed,theotherjimmy\/mbed,svogl\/mbed-os,pbrook\/mbed,maximmbed\/mbed,catiedev\/mbed-os,nRFMesh\/mbed-os,jferreir\/mbed,adustm\/mbed,mmorenobarm\/mbed-os,catiedev\/mbed-os,pi19404\/mbed,fahhem\/mbed-os,cvtsi2sd\/mbed-os,Shengliang\/mbed,sam-geek\/mbed,j-greffe\/mbed-os,bentwire\/mbed,fahhem\/mbed-os,Marcomissyou\/mbed,dbestm\/mbed,K4zuki\/mbed,ARM-software\/mbed-beetle,al177\/mbed,NXPmicro\/mbed,nvlsianpu\/mbed,adamgreen\/mbed,nabilbendafi\/mbed,arostm\/mbed-os,pradeep-gr\/mbed-os5-onsemi,pedromes\/mbed,getopenmono\/mbed,nvlsianpu\/mbed,tung7970\/mbed-os,sam-geek\/mbed,NitinBhaskar\/mbed,alertby\/mbed,maximmbed\/mbed,jferreir\/mbed,larks\/mbed,cvtsi2sd\/mbed-os,larks\/mbed,NXPmicro\/mbed,HeadsUpDisplayInc\/mbed,Shengliang\/mbed,monkiineko\/mbed-os,getopenmono\/mbed,K4zuki\/mbed,rosterloh\/mbed,jeremybrodt\/mbed,bulislaw\/mbed-os,autopulated\/mbed,wodji\/mbed,jpbrucker\/mbed,andcor02\/mbed-os,Sweet-Peas\/mbed,RonEld\/mbed,mikaleppanen\/mbed-os,alertby\/mbed,FranklyDev\/mbed,kpurusho\/mbed,pradeep-gr\/mbed-os5-onsemi,ryankurte\/mbed-os,fahhem\/mbed-os,fvincenzo\/mbed-os,HeadsUpDisplayInc\/mbed,pi19404\/mbed,brstew\/MBED-BUILD,K4zuki\/mbed,fahhem\/mbed-os,JasonHow44\/mbed,fanghuaqi\/mbed,RonEld\/mbed,adamgreen\/mbed,Archcady\/mbed-os,ban4jp\/mbed,adustm\/mbed,mmorenobarm\/mbed-os,jeremybrodt\/mbed,tung7970\/mbed-os-1,ARM-software\/mbed-beetle,mazimkhan\/mbed-os,jrjang\/mbed,ryankurte\/mbed-os,getopenmono\/mbed,nabilbendafi\/mbed,xcrespo\/mbed,DanKupiniak\/mbed,logost\/mbed,dbestm\/mbed,andreaslarssonublox\/mbed,autopulated\/mbed,kpurusho\/mbed,mnlipp\/mbed,Marcomissyou\/mbed,rosterloh\/mbed,fahhem\/mbed-os,GustavWi\/mbed,NXPmicro\/mbed,rgrover\/mbed,maximmbed\/mbed,betzw\/mbed-os,fpiot\/mbed-ats,FranklyDev\/mbed,masaohamanaka\/mbed,svastm\/mbed,DanKupiniak\/mbed,monkiineko\/mbed-os,autopulated\/mbed,kjbracey-arm\/mbed,dbestm\/mbed","old_file":"libraries\/mbed\/targets\/cmsis\/TARGET_Freescale\/TARGET_KLXX\/TARGET_KL05Z\/TOOLCHAIN_GCC_ARM\/MKL05Z4.ld","new_file":"libraries\/mbed\/targets\/cmsis\/TARGET_Freescale\/TARGET_KLXX\/TARGET_KL05Z\/TOOLCHAIN_GCC_ARM\/MKL05Z4.ld","new_contents":"","old_contents":"","returncode":128,"stderr":"fatal: unable to access 'https:\/\/github.com\/nvlsianpu\/mbed.git\/': The requested URL returned error: 403\n","license":"apache-2.0","lang":"Linker Script"}